5 files changed, 89 insertions, 5 deletions

diff --git a/Documentation/devicetree/bindings/arm/armada-38x.txt b/Documentation/devicetree/bindings/arm/armada-38x.txt
index 11f2330a6554..ad9f8ed4d9bd 100644
--- a/Documentation/devicetree/bindings/arm/armada-38x.txt
+++ b/Documentation/devicetree/bindings/arm/armada-38x.txt
@@ -6,5 +6,15 @@ following property:
 
 Required root node property:
 
- - compatible: must contain either "marvell,armada380" or
-   "marvell,armada385" depending on the variant of the SoC being used.
+ - compatible: must contain "marvell,armada380"
+
+In addition, boards using the Marvell Armada 385 SoC shall have the
+following property before the previous one:
+
+Required root node property:
+
+compatible: must contain "marvell,armada385"
+
+Example:
+
+compatible = "marvell,a385-rd", "marvell,armada385", "marvell,armada380";
diff --git a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
index 5216b419016a..8b4f7b7fe88b 100644
--- a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
+++ b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
@@ -9,6 +9,18 @@ Required Properties:
 - reg: physical base address of the controller and length of memory mapped
     region.
 
+Optional Properties:
+- clocks: List of clock handles. The parent clocks of the input clocks to the
+        devices in this power domain are set to oscclk before power gating
+        and restored back after powering on a domain. This is required for
+        all domains which are powered on and off and not required for unused
+        domains.
+- clock-names: The following clocks can be specified:
+        - oscclk: Oscillator clock.
+        - pclkN, clkN: Pairs of parent of input clock and input clock to the
+                devices in this power domain. Maximum of 4 pairs (N = 0 to 3)
+                are supported currently.
+
 Node of a device using power domains must have a samsung,power-domain property
 defined with a phandle to respective power domain.
 
@@ -19,6 +31,14 @@ Example:
                 reg = <0x10023C00 0x10>;
         };
 
+        mfc_pd: power-domain@10044060 {
+                compatible = "samsung,exynos4210-pd";
+                reg = <0x10044060 0x20>;
+                clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK333>,
+                        <&clock CLK_MOUT_USER_ACLK333>;
+                clock-names = "oscclk", "pclk0", "clk0";
+        };
+
 Example of the node using power domain:
 
         node {
diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt b/Documentation/devicetree/bindings/arm/l2cc.txt
index b513cb8196fe..af527ee111c2 100644
--- a/Documentation/devicetree/bindings/arm/l2cc.txt
+++ b/Documentation/devicetree/bindings/arm/l2cc.txt
@@ -40,6 +40,9 @@ Optional properties:
 - arm,filter-ranges : <start length> Starting address and length of window to
   filter. Addresses in the filter window are directed to the M1 port. Other
   addresses will go to the M0 port.
+- arm,io-coherent : indicates that the system is operating in an hardware
+  I/O coherent mode. Valid only when the arm,pl310-cache compatible
+  string is used.
 - interrupts : 1 combined interrupt.
 - cache-id-part: cache id part number to be used if it is not present
   on hardware
diff --git a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
index 5d49f2b37f68..adc61b095bd1 100644
--- a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
@@ -14,14 +14,21 @@ Required properties:
                                 for exynos4412/5250 controllers.
                         Must be "samsung,exynos-adc-v2" for
                                 future controllers.
+                        Must be "samsung,exynos3250-adc" for
+                                controllers compatible with ADC of Exynos3250.
 - reg:                  Contains ADC register address range (base address and
                         length) and the address of the phy enable register.
 - interrupts:           Contains the interrupt information for the timer. The
                         format is being dependent on which interrupt controller
                         the Samsung device uses.
 - #io-channel-cells = <1>; As ADC has multiple outputs
-- clocks                From common clock binding: handle to adc clock.
-- clock-names           From common clock binding: Shall be "adc".
+- clocks                From common clock bindings: handles to clocks specified
+                        in "clock-names" property, in the same order.
+- clock-names           From common clock bindings: list of clock input names
+                        used by ADC block:
+                        - "adc" : ADC bus clock
+                        - "sclk" : ADC special clock (only for Exynos3250 and
+                                   compatible ADC block)
 - vdd-supply            VDD input supply.
 
 Note: child nodes can be added for auto probing from device tree.
@@ -41,6 +48,20 @@ adc: adc@12D10000 {
         vdd-supply = <&buck5_reg>;
 };
 
+Example: adding device info in dtsi file for Exynos3250 with additional sclk
+
+adc: adc@126C0000 {
+        compatible = "samsung,exynos3250-adc", "samsung,exynos-adc-v2;
+        reg = <0x126C0000 0x100>, <0x10020718 0x4>;
+        interrupts = <0 137 0>;
+        #io-channel-cells = <1>;
+        io-channel-ranges;
+
+        clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
+        clock-names = "adc", "sclk";
+
+        vdd-supply = <&buck5_reg>;
+};
 
 Example: Adding child nodes in dts file
 
@@ -48,7 +69,7 @@ adc@12D10000 {
 
         /* NTC thermistor is a hwmon device */
         ncp15wb473@0 {
-                compatible = "ntc,ncp15wb473";
+                compatible = "murata,ncp15wb473";
                 pullup-uv = <1800000>;
                 pullup-ohm = <47000>;
                 pulldown-ohm = <0>;
diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.txt b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
index 2a4ab046a8a1..f9865e77e0b0 100644
--- a/Documentation/devicetree/bindings/arm/samsung/pmu.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
@@ -12,8 +12,38 @@ Properties:
 
  - reg : offset and length of the register set.
 
+ - #clock-cells : must be <1>, since PMU requires once cell as clock specifier.
+                The single specifier cell is used as index to list of clocks
+                provided by PMU, which is currently:
+                        0 : SoC clock output (CLKOUT pin)
+
+ - clock-names : list of clock names for particular CLKOUT mux inputs in
+                following format:
+                        "clkoutN", where N is a decimal number corresponding to
+                        CLKOUT mux control bits value for given input, e.g.
+                                "clkout0", "clkout7", "clkout15".
+
+ - clocks : list of phandles and specifiers to all input clocks listed in
+                clock-names property.
+
 Example :
 pmu_system_controller: system-controller@10040000 {
         compatible = "samsung,exynos5250-pmu", "syscon";
         reg = <0x10040000 0x5000>;
+        #clock-cells = <1>;
+        clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
+                        "clkout4", "clkout8", "clkout9";
+        clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
+                <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
+                <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>,
+                <&clock CLK_XUSBXTI>;
+};
+
+Example of clock consumer :
+
+usb3503: usb3503@08 {
+        /* ... */
+        clock-names = "refclk";
+        clocks = <&pmu_system_controller 0>;
+        /* ... */
 };