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-rw-r--r--Documentation/devicetree/bindings/arm/adapteva.txt7
-rw-r--r--Documentation/devicetree/bindings/arm/arm-boards6
-rw-r--r--Documentation/devicetree/bindings/arm/armada-380-mpcore-soc-ctrl.txt14
-rw-r--r--Documentation/devicetree/bindings/arm/atmel-aic.txt42
-rw-r--r--Documentation/devicetree/bindings/arm/atmel-pmc.txt5
-rw-r--r--Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351-cpu-method36
-rw-r--r--Documentation/devicetree/bindings/arm/brcm-brcmstb.txt95
-rw-r--r--Documentation/devicetree/bindings/arm/ccn.txt21
-rw-r--r--Documentation/devicetree/bindings/arm/cpu-enable-method/marvell,berlin-smp41
-rw-r--r--Documentation/devicetree/bindings/arm/cpus.txt4
-rw-r--r--Documentation/devicetree/bindings/arm/gic-v3.txt79
-rw-r--r--Documentation/devicetree/bindings/arm/gic.txt1
-rw-r--r--Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt11
-rw-r--r--Documentation/devicetree/bindings/arm/marvell,berlin.txt16
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek.txt8
-rw-r--r--Documentation/devicetree/bindings/arm/omap/crossbar.txt36
-rw-r--r--Documentation/devicetree/bindings/arm/omap/omap.txt3
-rw-r--r--Documentation/devicetree/bindings/arm/omap/prcm.txt65
-rw-r--r--Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt25
-rw-r--r--Documentation/devicetree/bindings/arm/samsung/pmu.txt2
-rw-r--r--Documentation/devicetree/bindings/arm/spear-misc.txt9
-rw-r--r--Documentation/devicetree/bindings/arm/tegra.txt2
-rw-r--r--Documentation/devicetree/bindings/arm/xilinx.txt8
23 files changed, 487 insertions, 49 deletions
diff --git a/Documentation/devicetree/bindings/arm/adapteva.txt b/Documentation/devicetree/bindings/arm/adapteva.txt
new file mode 100644
index 000000000000..1d8af9e36065
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/adapteva.txt
@@ -0,0 +1,7 @@
1Adapteva Platforms Device Tree Bindings
2---------------------------------------
3
4Parallella board
5
6Required root node properties:
7 - compatible = "adapteva,parallella";
diff --git a/Documentation/devicetree/bindings/arm/arm-boards b/Documentation/devicetree/bindings/arm/arm-boards
index 3509707f9320..c554ed3d44fb 100644
--- a/Documentation/devicetree/bindings/arm/arm-boards
+++ b/Documentation/devicetree/bindings/arm/arm-boards
@@ -86,3 +86,9 @@ Interrupt controllers:
86 compatible = "arm,versatile-sic"; 86 compatible = "arm,versatile-sic";
87 interrupt-controller; 87 interrupt-controller;
88 #interrupt-cells = <1>; 88 #interrupt-cells = <1>;
89
90Required nodes:
91
92- core-module: the root node to the Versatile platforms must have
93 a core-module with regs and the compatible strings
94 "arm,core-module-versatile", "syscon"
diff --git a/Documentation/devicetree/bindings/arm/armada-380-mpcore-soc-ctrl.txt b/Documentation/devicetree/bindings/arm/armada-380-mpcore-soc-ctrl.txt
new file mode 100644
index 000000000000..8781073029e9
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/armada-380-mpcore-soc-ctrl.txt
@@ -0,0 +1,14 @@
1Marvell Armada 38x CA9 MPcore SoC Controller
2============================================
3
4Required properties:
5
6- compatible: Should be "marvell,armada-380-mpcore-soc-ctrl".
7
8- reg: should be the register base and length as documented in the
9 datasheet for the CA9 MPcore SoC Control registers
10
11mpcore-soc-ctrl@20d20 {
12 compatible = "marvell,armada-380-mpcore-soc-ctrl";
13 reg = <0x20d20 0x6c>;
14};
diff --git a/Documentation/devicetree/bindings/arm/atmel-aic.txt b/Documentation/devicetree/bindings/arm/atmel-aic.txt
deleted file mode 100644
index 2742e9cfd6b1..000000000000
--- a/Documentation/devicetree/bindings/arm/atmel-aic.txt
+++ /dev/null
@@ -1,42 +0,0 @@
1* Advanced Interrupt Controller (AIC)
2
3Required properties:
4- compatible: Should be "atmel,<chip>-aic"
5 <chip> can be "at91rm9200" or "sama5d3"
6- interrupt-controller: Identifies the node as an interrupt controller.
7- interrupt-parent: For single AIC system, it is an empty property.
8- #interrupt-cells: The number of cells to define the interrupts. It should be 3.
9 The first cell is the IRQ number (aka "Peripheral IDentifier" on datasheet).
10 The second cell is used to specify flags:
11 bits[3:0] trigger type and level flags:
12 1 = low-to-high edge triggered.
13 2 = high-to-low edge triggered.
14 4 = active high level-sensitive.
15 8 = active low level-sensitive.
16 Valid combinations are 1, 2, 3, 4, 8.
17 Default flag for internal sources should be set to 4 (active high).
18 The third cell is used to specify the irq priority from 0 (lowest) to 7
19 (highest).
20- reg: Should contain AIC registers location and length
21- atmel,external-irqs: u32 array of external irqs.
22
23Examples:
24 /*
25 * AIC
26 */
27 aic: interrupt-controller@fffff000 {
28 compatible = "atmel,at91rm9200-aic";
29 interrupt-controller;
30 interrupt-parent;
31 #interrupt-cells = <3>;
32 reg = <0xfffff000 0x200>;
33 };
34
35 /*
36 * An interrupt generating device that is wired to an AIC.
37 */
38 dma: dma-controller@ffffec00 {
39 compatible = "atmel,at91sam9g45-dma";
40 reg = <0xffffec00 0x200>;
41 interrupts = <21 4 5>;
42 };
diff --git a/Documentation/devicetree/bindings/arm/atmel-pmc.txt b/Documentation/devicetree/bindings/arm/atmel-pmc.txt
index 389bed5056e8..795cc78543fe 100644
--- a/Documentation/devicetree/bindings/arm/atmel-pmc.txt
+++ b/Documentation/devicetree/bindings/arm/atmel-pmc.txt
@@ -1,7 +1,10 @@
1* Power Management Controller (PMC) 1* Power Management Controller (PMC)
2 2
3Required properties: 3Required properties:
4- compatible: Should be "atmel,at91rm9200-pmc" 4- compatible: Should be "atmel,<chip>-pmc".
5 <chip> can be: at91rm9200, at91sam9260, at91sam9g45, at91sam9n12,
6 at91sam9x5, sama5d3
7
5- reg: Should contain PMC registers location and length 8- reg: Should contain PMC registers location and length
6 9
7Examples: 10Examples:
diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351-cpu-method b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351-cpu-method
new file mode 100644
index 000000000000..8240c023e202
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351-cpu-method
@@ -0,0 +1,36 @@
1Broadcom Kona Family CPU Enable Method
2--------------------------------------
3This binding defines the enable method used for starting secondary
4CPUs in the following Broadcom SoCs:
5 BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664
6
7The enable method is specified by defining the following required
8properties in the "cpus" device tree node:
9 - enable-method = "brcm,bcm11351-cpu-method";
10 - secondary-boot-reg = <...>;
11
12The secondary-boot-reg property is a u32 value that specifies the
13physical address of the register used to request the ROM holding pen
14code release a secondary CPU. The value written to the register is
15formed by encoding the target CPU id into the low bits of the
16physical start address it should jump to.
17
18Example:
19 cpus {
20 #address-cells = <1>;
21 #size-cells = <0>;
22 enable-method = "brcm,bcm11351-cpu-method";
23 secondary-boot-reg = <0x3500417c>;
24
25 cpu0: cpu@0 {
26 device_type = "cpu";
27 compatible = "arm,cortex-a9";
28 reg = <0>;
29 };
30
31 cpu1: cpu@1 {
32 device_type = "cpu";
33 compatible = "arm,cortex-a9";
34 reg = <1>;
35 };
36 };
diff --git a/Documentation/devicetree/bindings/arm/brcm-brcmstb.txt b/Documentation/devicetree/bindings/arm/brcm-brcmstb.txt
new file mode 100644
index 000000000000..3c436cc4f35d
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/brcm-brcmstb.txt
@@ -0,0 +1,95 @@
1ARM Broadcom STB platforms Device Tree Bindings
2-----------------------------------------------
3Boards with Broadcom Brahma15 ARM-based BCMxxxx (generally BCM7xxx variants)
4SoC shall have the following DT organization:
5
6Required root node properties:
7 - compatible: "brcm,bcm<chip_id>", "brcm,brcmstb"
8
9example:
10/ {
11 #address-cells = <2>;
12 #size-cells = <2>;
13 model = "Broadcom STB (bcm7445)";
14 compatible = "brcm,bcm7445", "brcm,brcmstb";
15
16Further, syscon nodes that map platform-specific registers used for general
17system control is required:
18
19 - compatible: "brcm,bcm<chip_id>-sun-top-ctrl", "syscon"
20 - compatible: "brcm,bcm<chip_id>-hif-cpubiuctrl", "syscon"
21 - compatible: "brcm,bcm<chip_id>-hif-continuation", "syscon"
22
23example:
24 rdb {
25 #address-cells = <1>;
26 #size-cells = <1>;
27 compatible = "simple-bus";
28 ranges = <0 0x00 0xf0000000 0x1000000>;
29
30 sun_top_ctrl: syscon@404000 {
31 compatible = "brcm,bcm7445-sun-top-ctrl", "syscon";
32 reg = <0x404000 0x51c>;
33 };
34
35 hif_cpubiuctrl: syscon@3e2400 {
36 compatible = "brcm,bcm7445-hif-cpubiuctrl", "syscon";
37 reg = <0x3e2400 0x5b4>;
38 };
39
40 hif_continuation: syscon@452000 {
41 compatible = "brcm,bcm7445-hif-continuation", "syscon";
42 reg = <0x452000 0x100>;
43 };
44 };
45
46Lastly, nodes that allow for support of SMP initialization and reboot are
47required:
48
49smpboot
50-------
51Required properties:
52
53 - compatible
54 The string "brcm,brcmstb-smpboot".
55
56 - syscon-cpu
57 A phandle / integer array property which lets the BSP know the location
58 of certain CPU power-on registers.
59
60 The layout of the property is as follows:
61 o a phandle to the "hif_cpubiuctrl" syscon node
62 o offset to the base CPU power zone register
63 o offset to the base CPU reset register
64
65 - syscon-cont
66 A phandle pointing to the syscon node which describes the CPU boot
67 continuation registers.
68 o a phandle to the "hif_continuation" syscon node
69
70example:
71 smpboot {
72 compatible = "brcm,brcmstb-smpboot";
73 syscon-cpu = <&hif_cpubiuctrl 0x88 0x178>;
74 syscon-cont = <&hif_continuation>;
75 };
76
77reboot
78-------
79Required properties
80
81 - compatible
82 The string property "brcm,brcmstb-reboot".
83
84 - syscon
85 A phandle / integer array that points to the syscon node which describes
86 the general system reset registers.
87 o a phandle to "sun_top_ctrl"
88 o offset to the "reset source enable" register
89 o offset to the "software master reset" register
90
91example:
92 reboot {
93 compatible = "brcm,brcmstb-reboot";
94 syscon = <&sun_top_ctrl 0x304 0x308>;
95 };
diff --git a/Documentation/devicetree/bindings/arm/ccn.txt b/Documentation/devicetree/bindings/arm/ccn.txt
new file mode 100644
index 000000000000..b100d3847d88
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/ccn.txt
@@ -0,0 +1,21 @@
1* ARM CCN (Cache Coherent Network)
2
3Required properties:
4
5- compatible: (standard compatible string) should be one of:
6 "arm,ccn-504"
7 "arm,ccn-508"
8
9- reg: (standard registers property) physical address and size
10 (16MB) of the configuration registers block
11
12- interrupts: (standard interrupt property) single interrupt
13 generated by the control block
14
15Example:
16
17 ccn@0x2000000000 {
18 compatible = "arm,ccn-504";
19 reg = <0x20 0x00000000 0 0x1000000>;
20 interrupts = <0 181 4>;
21 };
diff --git a/Documentation/devicetree/bindings/arm/cpu-enable-method/marvell,berlin-smp b/Documentation/devicetree/bindings/arm/cpu-enable-method/marvell,berlin-smp
new file mode 100644
index 000000000000..cd236b727e2a
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/cpu-enable-method/marvell,berlin-smp
@@ -0,0 +1,41 @@
1========================================================
2Secondary CPU enable-method "marvell,berlin-smp" binding
3========================================================
4
5This document describes the "marvell,berlin-smp" method for enabling secondary
6CPUs. To apply to all CPUs, a single "marvell,berlin-smp" enable method should
7be defined in the "cpus" node.
8
9Enable method name: "marvell,berlin-smp"
10Compatible machines: "marvell,berlin2" and "marvell,berlin2q"
11Compatible CPUs: "marvell,pj4b" and "arm,cortex-a9"
12Related properties: (none)
13
14Note:
15This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and
16"marvell,berlin-cpu-ctrl"[1].
17
18Example:
19
20 cpus {
21 #address-cells = <1>;
22 #size-cells = <0>;
23 enable-method = "marvell,berlin-smp";
24
25 cpu@0 {
26 compatible = "marvell,pj4b";
27 device_type = "cpu";
28 next-level-cache = <&l2>;
29 reg = <0>;
30 };
31
32 cpu@1 {
33 compatible = "marvell,pj4b";
34 device_type = "cpu";
35 next-level-cache = <&l2>;
36 reg = <1>;
37 };
38 };
39
40--
41[1] arm/marvell,berlin.txt
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index 1fe72a0778cd..298e2f6b33c6 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -152,7 +152,9 @@ nodes to be present and contain the properties described below.
152 "arm,cortex-a7" 152 "arm,cortex-a7"
153 "arm,cortex-a8" 153 "arm,cortex-a8"
154 "arm,cortex-a9" 154 "arm,cortex-a9"
155 "arm,cortex-a12"
155 "arm,cortex-a15" 156 "arm,cortex-a15"
157 "arm,cortex-a17"
156 "arm,cortex-a53" 158 "arm,cortex-a53"
157 "arm,cortex-a57" 159 "arm,cortex-a57"
158 "arm,cortex-m0" 160 "arm,cortex-m0"
@@ -163,6 +165,7 @@ nodes to be present and contain the properties described below.
163 "arm,cortex-r4" 165 "arm,cortex-r4"
164 "arm,cortex-r5" 166 "arm,cortex-r5"
165 "arm,cortex-r7" 167 "arm,cortex-r7"
168 "brcm,brahma-b15"
166 "faraday,fa526" 169 "faraday,fa526"
167 "intel,sa110" 170 "intel,sa110"
168 "intel,sa1100" 171 "intel,sa1100"
@@ -184,6 +187,7 @@ nodes to be present and contain the properties described below.
184 can be one of: 187 can be one of:
185 "allwinner,sun6i-a31" 188 "allwinner,sun6i-a31"
186 "arm,psci" 189 "arm,psci"
190 "brcm,brahma-b15"
187 "marvell,armada-375-smp" 191 "marvell,armada-375-smp"
188 "marvell,armada-380-smp" 192 "marvell,armada-380-smp"
189 "marvell,armada-xp-smp" 193 "marvell,armada-xp-smp"
diff --git a/Documentation/devicetree/bindings/arm/gic-v3.txt b/Documentation/devicetree/bindings/arm/gic-v3.txt
new file mode 100644
index 000000000000..33cd05e6c125
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/gic-v3.txt
@@ -0,0 +1,79 @@
1* ARM Generic Interrupt Controller, version 3
2
3AArch64 SMP cores are often associated with a GICv3, providing Private
4Peripheral Interrupts (PPI), Shared Peripheral Interrupts (SPI),
5Software Generated Interrupts (SGI), and Locality-specific Peripheral
6Interrupts (LPI).
7
8Main node required properties:
9
10- compatible : should at least contain "arm,gic-v3".
11- interrupt-controller : Identifies the node as an interrupt controller
12- #interrupt-cells : Specifies the number of cells needed to encode an
13 interrupt source. Must be a single cell with a value of at least 3.
14
15 The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
16 interrupts. Other values are reserved for future use.
17
18 The 2nd cell contains the interrupt number for the interrupt type.
19 SPI interrupts are in the range [0-987]. PPI interrupts are in the
20 range [0-15].
21
22 The 3rd cell is the flags, encoded as follows:
23 bits[3:0] trigger type and level flags.
24 1 = edge triggered
25 4 = level triggered
26
27 Cells 4 and beyond are reserved for future use. When the 1st cell
28 has a value of 0 or 1, cells 4 and beyond act as padding, and may be
29 ignored. It is recommended that padding cells have a value of 0.
30
31- reg : Specifies base physical address(s) and size of the GIC
32 registers, in the following order:
33 - GIC Distributor interface (GICD)
34 - GIC Redistributors (GICR), one range per redistributor region
35 - GIC CPU interface (GICC)
36 - GIC Hypervisor interface (GICH)
37 - GIC Virtual CPU interface (GICV)
38
39 GICC, GICH and GICV are optional.
40
41- interrupts : Interrupt source of the VGIC maintenance interrupt.
42
43Optional
44
45- redistributor-stride : If using padding pages, specifies the stride
46 of consecutive redistributors. Must be a multiple of 64kB.
47
48- #redistributor-regions: The number of independent contiguous regions
49 occupied by the redistributors. Required if more than one such
50 region is present.
51
52Examples:
53
54 gic: interrupt-controller@2cf00000 {
55 compatible = "arm,gic-v3";
56 #interrupt-cells = <3>;
57 interrupt-controller;
58 reg = <0x0 0x2f000000 0 0x10000>, // GICD
59 <0x0 0x2f100000 0 0x200000>, // GICR
60 <0x0 0x2c000000 0 0x2000>, // GICC
61 <0x0 0x2c010000 0 0x2000>, // GICH
62 <0x0 0x2c020000 0 0x2000>; // GICV
63 interrupts = <1 9 4>;
64 };
65
66 gic: interrupt-controller@2c010000 {
67 compatible = "arm,gic-v3";
68 #interrupt-cells = <3>;
69 interrupt-controller;
70 redistributor-stride = <0x0 0x40000>; // 256kB stride
71 #redistributor-regions = <2>;
72 reg = <0x0 0x2c010000 0 0x10000>, // GICD
73 <0x0 0x2d000000 0 0x800000>, // GICR 1: CPUs 0-31
74 <0x0 0x2e000000 0 0x800000>; // GICR 2: CPUs 32-63
75 <0x0 0x2c040000 0 0x2000>, // GICC
76 <0x0 0x2c060000 0 0x2000>, // GICH
77 <0x0 0x2c080000 0 0x2000>; // GICV
78 interrupts = <1 9 4>;
79 };
diff --git a/Documentation/devicetree/bindings/arm/gic.txt b/Documentation/devicetree/bindings/arm/gic.txt
index 5573c08d3180..c7d2fa156678 100644
--- a/Documentation/devicetree/bindings/arm/gic.txt
+++ b/Documentation/devicetree/bindings/arm/gic.txt
@@ -16,6 +16,7 @@ Main node required properties:
16 "arm,cortex-a9-gic" 16 "arm,cortex-a9-gic"
17 "arm,cortex-a7-gic" 17 "arm,cortex-a7-gic"
18 "arm,arm11mp-gic" 18 "arm,arm11mp-gic"
19 "brcm,brahma-b15-gic"
19- interrupt-controller : Identifies the node as an interrupt controller 20- interrupt-controller : Identifies the node as an interrupt controller
20- #interrupt-cells : Specifies the number of cells needed to encode an 21- #interrupt-cells : Specifies the number of cells needed to encode an
21 interrupt source. The type shall be a <u32> and the value shall be 3. 22 interrupt source. The type shall be a <u32> and the value shall be 3.
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
index df0a452b8526..934f00025cc4 100644
--- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
+++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
@@ -31,6 +31,17 @@ Example:
31 reboot-offset = <0x4>; 31 reboot-offset = <0x4>;
32 }; 32 };
33 33
34-----------------------------------------------------------------------
35Hisilicon CPU controller
36
37Required properties:
38- compatible : "hisilicon,cpuctrl"
39- reg : Register address and size
40
41The clock registers and power registers of secondary cores are defined
42in CPU controller, especially in HIX5HD2 SoC.
43
44-----------------------------------------------------------------------
34PCTRL: Peripheral misc control register 45PCTRL: Peripheral misc control register
35 46
36Required Properties: 47Required Properties:
diff --git a/Documentation/devicetree/bindings/arm/marvell,berlin.txt b/Documentation/devicetree/bindings/arm/marvell,berlin.txt
index 94013a9a8769..904de5781f44 100644
--- a/Documentation/devicetree/bindings/arm/marvell,berlin.txt
+++ b/Documentation/devicetree/bindings/arm/marvell,berlin.txt
@@ -24,6 +24,22 @@ SoC and board used. Currently known SoC compatibles are:
24 ... 24 ...
25} 25}
26 26
27* Marvell Berlin CPU control bindings
28
29CPU control register allows various operations on CPUs, like resetting them
30independently.
31
32Required properties:
33- compatible: should be "marvell,berlin-cpu-ctrl"
34- reg: address and length of the register set
35
36Example:
37
38cpu-ctrl@f7dd0000 {
39 compatible = "marvell,berlin-cpu-ctrl";
40 reg = <0xf7dd0000 0x10000>;
41};
42
27* Marvell Berlin2 chip control binding 43* Marvell Berlin2 chip control binding
28 44
29Marvell Berlin SoCs have a chip control register set providing several 45Marvell Berlin SoCs have a chip control register set providing several
diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt b/Documentation/devicetree/bindings/arm/mediatek.txt
new file mode 100644
index 000000000000..d6ac71f37314
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mediatek.txt
@@ -0,0 +1,8 @@
1Mediatek MT6589 Platforms Device Tree Bindings
2
3Boards with a SoC of the Mediatek MT6589 shall have the following property:
4
5Required root node property:
6
7compatible: must contain "mediatek,mt6589"
8
diff --git a/Documentation/devicetree/bindings/arm/omap/crossbar.txt b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
index fb88585cfb93..4139db353d0a 100644
--- a/Documentation/devicetree/bindings/arm/omap/crossbar.txt
+++ b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
@@ -10,6 +10,7 @@ Required properties:
10- compatible : Should be "ti,irq-crossbar" 10- compatible : Should be "ti,irq-crossbar"
11- reg: Base address and the size of the crossbar registers. 11- reg: Base address and the size of the crossbar registers.
12- ti,max-irqs: Total number of irqs available at the interrupt controller. 12- ti,max-irqs: Total number of irqs available at the interrupt controller.
13- ti,max-crossbar-sources: Maximum number of crossbar sources that can be routed.
13- ti,reg-size: Size of a individual register in bytes. Every individual 14- ti,reg-size: Size of a individual register in bytes. Every individual
14 register is assumed to be of same size. Valid sizes are 1, 2, 4. 15 register is assumed to be of same size. Valid sizes are 1, 2, 4.
15- ti,irqs-reserved: List of the reserved irq lines that are not muxed using 16- ti,irqs-reserved: List of the reserved irq lines that are not muxed using
@@ -17,11 +18,46 @@ Required properties:
17 so crossbar bar driver should not consider them as free 18 so crossbar bar driver should not consider them as free
18 lines. 19 lines.
19 20
21Optional properties:
22- ti,irqs-skip: This is similar to "ti,irqs-reserved", but these are for
23 SOC-specific hard-wiring of those irqs which unexpectedly bypasses the
24 crossbar. These irqs have a crossbar register, but still cannot be used.
25
26- ti,irqs-safe-map: integer which maps to a safe configuration to use
27 when the interrupt controller irq is unused (when not provided, default is 0)
28
20Examples: 29Examples:
21 crossbar_mpu: @4a020000 { 30 crossbar_mpu: @4a020000 {
22 compatible = "ti,irq-crossbar"; 31 compatible = "ti,irq-crossbar";
23 reg = <0x4a002a48 0x130>; 32 reg = <0x4a002a48 0x130>;
24 ti,max-irqs = <160>; 33 ti,max-irqs = <160>;
34 ti,max-crossbar-sources = <400>;
25 ti,reg-size = <2>; 35 ti,reg-size = <2>;
26 ti,irqs-reserved = <0 1 2 3 5 6 131 132 139 140>; 36 ti,irqs-reserved = <0 1 2 3 5 6 131 132 139 140>;
37 ti,irqs-skip = <10 133 139 140>;
27 }; 38 };
39
40Consumer:
41========
42See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt and
43Documentation/devicetree/bindings/arm/gic.txt for further details.
44
45An interrupt consumer on an SoC using crossbar will use:
46 interrupts = <GIC_SPI request_number interrupt_level>
47When the request number is between 0 to that described by
48"ti,max-crossbar-sources", it is assumed to be a crossbar mapping. If the
49request_number is greater than "ti,max-crossbar-sources", then it is mapped as a
50quirky hardware mapping direct to GIC.
51
52Example:
53 device_x@0x4a023000 {
54 /* Crossbar 8 used */
55 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
56 ...
57 };
58
59 device_y@0x4a033000 {
60 /* Direct mapped GIC SPI 1 used */
61 interrupts = <GIC_SPI DIRECT_IRQ(1) IRQ_TYPE_LEVEL_HIGH>;
62 ...
63 };
diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt b/Documentation/devicetree/bindings/arm/omap/omap.txt
index d22b216f5d23..0edc90305dfe 100644
--- a/Documentation/devicetree/bindings/arm/omap/omap.txt
+++ b/Documentation/devicetree/bindings/arm/omap/omap.txt
@@ -129,6 +129,9 @@ Boards:
129- AM437x GP EVM 129- AM437x GP EVM
130 compatible = "ti,am437x-gp-evm", "ti,am4372", "ti,am43" 130 compatible = "ti,am437x-gp-evm", "ti,am4372", "ti,am43"
131 131
132- AM437x SK EVM: AM437x StarterKit Evaluation Module
133 compatible = "ti,am437x-sk-evm", "ti,am4372", "ti,am43"
134
132- DRA742 EVM: Software Development Board for DRA742 135- DRA742 EVM: Software Development Board for DRA742
133 compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7" 136 compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7"
134 137
diff --git a/Documentation/devicetree/bindings/arm/omap/prcm.txt b/Documentation/devicetree/bindings/arm/omap/prcm.txt
new file mode 100644
index 000000000000..79074dac684a
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/omap/prcm.txt
@@ -0,0 +1,65 @@
1OMAP PRCM bindings
2
3Power Reset and Clock Manager lists the device clocks and clockdomains under
4a DT hierarchy. Each TI SoC can have multiple PRCM entities listed for it,
5each describing one module and the clock hierarchy under it. see [1] for
6documentation about the individual clock/clockdomain nodes.
7
8[1] Documentation/devicetree/bindings/clock/ti/*
9
10Required properties:
11- compatible: Must be one of:
12 "ti,am3-prcm"
13 "ti,am3-scrm"
14 "ti,am4-prcm"
15 "ti,am4-scrm"
16 "ti,omap2-prcm"
17 "ti,omap2-scrm"
18 "ti,omap3-prm"
19 "ti,omap3-cm"
20 "ti,omap3-scrm"
21 "ti,omap4-cm1"
22 "ti,omap4-prm"
23 "ti,omap4-cm2"
24 "ti,omap4-scrm"
25 "ti,omap5-prm"
26 "ti,omap5-cm-core-aon"
27 "ti,omap5-scrm"
28 "ti,omap5-cm-core"
29 "ti,dra7-prm"
30 "ti,dra7-cm-core-aon"
31 "ti,dra7-cm-core"
32- reg: Contains PRCM module register address range
33 (base address and length)
34- clocks: clocks for this module
35- clockdomains: clockdomains for this module
36
37Example:
38
39cm: cm@48004000 {
40 compatible = "ti,omap3-cm";
41 reg = <0x48004000 0x4000>;
42
43 cm_clocks: clocks {
44 #address-cells = <1>;
45 #size-cells = <0>;
46 };
47
48 cm_clockdomains: clockdomains {
49 };
50}
51
52&cm_clocks {
53 omap2_32k_fck: omap_32k_fck {
54 #clock-cells = <0>;
55 compatible = "fixed-clock";
56 clock-frequency = <32768>;
57 };
58};
59
60&cm_clockdomains {
61 core_l3_clkdm: core_l3_clkdm {
62 compatible = "ti,clockdomain";
63 clocks = <&sdrc_ick>;
64 };
65};
diff --git a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
index 832fe8cc24d7..adc61b095bd1 100644
--- a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
@@ -14,14 +14,21 @@ Required properties:
14 for exynos4412/5250 controllers. 14 for exynos4412/5250 controllers.
15 Must be "samsung,exynos-adc-v2" for 15 Must be "samsung,exynos-adc-v2" for
16 future controllers. 16 future controllers.
17 Must be "samsung,exynos3250-adc" for
18 controllers compatible with ADC of Exynos3250.
17- reg: Contains ADC register address range (base address and 19- reg: Contains ADC register address range (base address and
18 length) and the address of the phy enable register. 20 length) and the address of the phy enable register.
19- interrupts: Contains the interrupt information for the timer. The 21- interrupts: Contains the interrupt information for the timer. The
20 format is being dependent on which interrupt controller 22 format is being dependent on which interrupt controller
21 the Samsung device uses. 23 the Samsung device uses.
22- #io-channel-cells = <1>; As ADC has multiple outputs 24- #io-channel-cells = <1>; As ADC has multiple outputs
23- clocks From common clock binding: handle to adc clock. 25- clocks From common clock bindings: handles to clocks specified
24- clock-names From common clock binding: Shall be "adc". 26 in "clock-names" property, in the same order.
27- clock-names From common clock bindings: list of clock input names
28 used by ADC block:
29 - "adc" : ADC bus clock
30 - "sclk" : ADC special clock (only for Exynos3250 and
31 compatible ADC block)
25- vdd-supply VDD input supply. 32- vdd-supply VDD input supply.
26 33
27Note: child nodes can be added for auto probing from device tree. 34Note: child nodes can be added for auto probing from device tree.
@@ -41,6 +48,20 @@ adc: adc@12D10000 {
41 vdd-supply = <&buck5_reg>; 48 vdd-supply = <&buck5_reg>;
42}; 49};
43 50
51Example: adding device info in dtsi file for Exynos3250 with additional sclk
52
53adc: adc@126C0000 {
54 compatible = "samsung,exynos3250-adc", "samsung,exynos-adc-v2;
55 reg = <0x126C0000 0x100>, <0x10020718 0x4>;
56 interrupts = <0 137 0>;
57 #io-channel-cells = <1>;
58 io-channel-ranges;
59
60 clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
61 clock-names = "adc", "sclk";
62
63 vdd-supply = <&buck5_reg>;
64};
44 65
45Example: Adding child nodes in dts file 66Example: Adding child nodes in dts file
46 67
diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.txt b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
index f9865e77e0b0..1e1979b229ff 100644
--- a/Documentation/devicetree/bindings/arm/samsung/pmu.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
@@ -7,6 +7,8 @@ Properties:
7 - "samsung,exynos4212-pmu" - for Exynos4212 SoC, 7 - "samsung,exynos4212-pmu" - for Exynos4212 SoC,
8 - "samsung,exynos4412-pmu" - for Exynos4412 SoC, 8 - "samsung,exynos4412-pmu" - for Exynos4412 SoC,
9 - "samsung,exynos5250-pmu" - for Exynos5250 SoC, 9 - "samsung,exynos5250-pmu" - for Exynos5250 SoC,
10 - "samsung,exynos5260-pmu" - for Exynos5260 SoC.
11 - "samsung,exynos5410-pmu" - for Exynos5410 SoC,
10 - "samsung,exynos5420-pmu" - for Exynos5420 SoC. 12 - "samsung,exynos5420-pmu" - for Exynos5420 SoC.
11 second value must be always "syscon". 13 second value must be always "syscon".
12 14
diff --git a/Documentation/devicetree/bindings/arm/spear-misc.txt b/Documentation/devicetree/bindings/arm/spear-misc.txt
new file mode 100644
index 000000000000..cf649827ffcd
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/spear-misc.txt
@@ -0,0 +1,9 @@
1SPEAr Misc configuration
2===========================
3SPEAr SOCs have some miscellaneous registers which are used to configure
4few properties of different peripheral controllers.
5
6misc node required properties:
7
8- compatible Should be "st,spear1340-misc", "syscon".
9- reg: Address range of misc space upto 8K
diff --git a/Documentation/devicetree/bindings/arm/tegra.txt b/Documentation/devicetree/bindings/arm/tegra.txt
index 558ed4b4ef39..73278c6d2dc3 100644
--- a/Documentation/devicetree/bindings/arm/tegra.txt
+++ b/Documentation/devicetree/bindings/arm/tegra.txt
@@ -30,6 +30,8 @@ board-specific compatible values:
30 nvidia,seaboard 30 nvidia,seaboard
31 nvidia,ventana 31 nvidia,ventana
32 nvidia,whistler 32 nvidia,whistler
33 toradex,apalis_t30
34 toradex,apalis_t30-eval
33 toradex,colibri_t20-512 35 toradex,colibri_t20-512
34 toradex,iris 36 toradex,iris
35 37
diff --git a/Documentation/devicetree/bindings/arm/xilinx.txt b/Documentation/devicetree/bindings/arm/xilinx.txt
index 6f1ed830b4f7..1f7995357888 100644
--- a/Documentation/devicetree/bindings/arm/xilinx.txt
+++ b/Documentation/devicetree/bindings/arm/xilinx.txt
@@ -1,7 +1,7 @@
1Xilinx Zynq EP107 Emulation Platform board 1Xilinx Zynq Platforms Device Tree Bindings
2 2
3This board is an emulation platform for the Zynq product which is 3Boards with Zynq-7000 SOC based on an ARM Cortex A9 processor
4based on an ARM Cortex A9 processor. 4shall have the following properties.
5 5
6Required root node properties: 6Required root node properties:
7 - compatible = "xlnx,zynq-ep107"; 7 - compatible = "xlnx,zynq-7000";
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-03 18:51:33 -0500