1 files changed, 11 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
index df0a452b8526..934f00025cc4 100644
--- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
+++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
@@ -31,6 +31,17 @@ Example:
                reboot-offset = <0x4>;
        };
+-----------------------------------------------------------------------
+Hisilicon CPU controller
+Required properties:
+- compatible : "hisilicon,cpuctrl"
+- reg : Register address and size
+The clock registers and power registers of secondary cores are defined
+in CPU controller, especially in HIX5HD2 SoC.
+-----------------------------------------------------------------------
 PCTRL: Peripheral misc control register
 Required Properties:

diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt index df0a452b8526..934f00025cc4 100644 --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
@@ -31,6 +31,17 @@ Example:
31	reboot-offset = <0x4>;	31	reboot-offset = <0x4>;
32	};	32	};
33		33
		34	-----------------------------------------------------------------------
		35	Hisilicon CPU controller
		36
		37	Required properties:
		38	- compatible : "hisilicon,cpuctrl"
		39	- reg : Register address and size
		40
		41	The clock registers and power registers of secondary cores are defined
		42	in CPU controller, especially in HIX5HD2 SoC.
		43
		44	-----------------------------------------------------------------------
34	PCTRL: Peripheral misc control register	45	PCTRL: Peripheral misc control register
35		46
36	Required Properties:	47	Required Properties: