1 files changed, 1 insertions, 1 deletions
diff --git a/Documentation/cachetlb.txt b/Documentation/cachetlb.txt
index 9164ae3b83bc..9b728dc17535 100644
--- a/Documentation/cachetlb.txt
+++ b/Documentation/cachetlb.txt
@@ -16,7 +16,7 @@ on all processors in the system.  Don't let this scare you into
 thinking SMP cache/tlb flushing must be so inefficient, this is in
 fact an area where many optimizations are possible.  For example,
 if it can be proven that a user address space has never executed
-on a cpu (see vma->cpu_vm_mask), one need not perform a flush
+on a cpu (see mm_cpumask()), one need not perform a flush
 for this address space on that cpu.
 First, the TLB flushing interfaces, since they are the simplest.  The

diff --git a/Documentation/cachetlb.txt b/Documentation/cachetlb.txt index 9164ae3b83bc..9b728dc17535 100644 --- a/Documentation/cachetlb.txt +++ b/Documentation/cachetlb.txt
@@ -16,7 +16,7 @@ on all processors in the system. Don't let this scare you into
16	thinking SMP cache/tlb flushing must be so inefficient, this is in	16	thinking SMP cache/tlb flushing must be so inefficient, this is in
17	fact an area where many optimizations are possible. For example,	17	fact an area where many optimizations are possible. For example,
18	if it can be proven that a user address space has never executed	18	if it can be proven that a user address space has never executed
19	on a cpu (see vma->cpu_vm_mask), one need not perform a flush	19	on a cpu (see mm_cpumask()), one need not perform a flush
20	for this address space on that cpu.	20	for this address space on that cpu.
21		21
22	First, the TLB flushing interfaces, since they are the simplest. The	22	First, the TLB flushing interfaces, since they are the simplest. The