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-rw-r--r--Documentation/devicetree/bindings/clock/exynos3250-clock.txt41
-rw-r--r--Documentation/devicetree/bindings/clock/exynos5260-clock.txt190
-rw-r--r--Documentation/devicetree/bindings/clock/exynos5420-clock.txt3
-rw-r--r--Documentation/devicetree/bindings/clock/samsung,s3c2410-clock.txt2
-rw-r--r--arch/arm/Kconfig4
-rw-r--r--arch/arm/boot/dts/exynos5420.dtsi14
-rw-r--r--arch/arm/mach-s3c24xx/Kconfig37
-rw-r--r--drivers/clk/Kconfig2
-rw-r--r--drivers/clk/Makefile2
-rw-r--r--drivers/clk/samsung/Kconfig26
-rw-r--r--drivers/clk/samsung/Makefile2
-rw-r--r--drivers/clk/samsung/clk-exynos3250.c780
-rw-r--r--drivers/clk/samsung/clk-exynos4.c51
-rw-r--r--drivers/clk/samsung/clk-exynos5250.c76
-rw-r--r--drivers/clk/samsung/clk-exynos5260.c1980
-rw-r--r--drivers/clk/samsung/clk-exynos5260.h459
-rw-r--r--drivers/clk/samsung/clk-exynos5420.c1127
-rw-r--r--drivers/clk/samsung/clk-exynos5440.c18
-rw-r--r--drivers/clk/samsung/clk-pll.c223
-rw-r--r--drivers/clk/samsung/clk-pll.h2
-rw-r--r--drivers/clk/samsung/clk-s3c2410.c51
-rw-r--r--drivers/clk/samsung/clk-s3c2412.c29
-rw-r--r--drivers/clk/samsung/clk-s3c2443.c46
-rw-r--r--drivers/clk/samsung/clk-s3c64xx.c44
-rw-r--r--drivers/clk/samsung/clk.c123
-rw-r--r--drivers/clk/samsung/clk.h72
-rw-r--r--include/dt-bindings/clock/exynos3250.h258
-rw-r--r--include/dt-bindings/clock/exynos4.h2
-rw-r--r--include/dt-bindings/clock/exynos5250.h21
-rw-r--r--include/dt-bindings/clock/exynos5260-clk.h469
-rw-r--r--include/dt-bindings/clock/exynos5420.h43
31 files changed, 5594 insertions, 603 deletions
diff --git a/Documentation/devicetree/bindings/clock/exynos3250-clock.txt b/Documentation/devicetree/bindings/clock/exynos3250-clock.txt
new file mode 100644
index 000000000000..aadc9c59e2d1
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos3250-clock.txt
@@ -0,0 +1,41 @@
1* Samsung Exynos3250 Clock Controller
2
3The Exynos3250 clock controller generates and supplies clock to various
4controllers within the Exynos3250 SoC.
5
6Required Properties:
7
8- compatible: should be one of the following.
9 - "samsung,exynos3250-cmu" - controller compatible with Exynos3250 SoC.
10
11- reg: physical base address of the controller and length of memory mapped
12 region.
13
14- #clock-cells: should be 1.
15
16Each clock is assigned an identifier and client nodes can use this identifier
17to specify the clock which they consume.
18
19All available clocks are defined as preprocessor macros in
20dt-bindings/clock/exynos3250.h header and can be used in device
21tree sources.
22
23Example 1: An example of a clock controller node is listed below.
24
25 cmu: clock-controller@10030000 {
26 compatible = "samsung,exynos3250-cmu";
27 reg = <0x10030000 0x20000>;
28 #clock-cells = <1>;
29 };
30
31Example 2: UART controller node that consumes the clock generated by the clock
32 controller. Refer to the standard clock bindings for information
33 about 'clocks' and 'clock-names' property.
34
35 serial@13800000 {
36 compatible = "samsung,exynos4210-uart";
37 reg = <0x13800000 0x100>;
38 interrupts = <0 109 0>;
39 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
40 clock-names = "uart", "clk_uart_baud0";
41 };
diff --git a/Documentation/devicetree/bindings/clock/exynos5260-clock.txt b/Documentation/devicetree/bindings/clock/exynos5260-clock.txt
new file mode 100644
index 000000000000..5496b2fac483
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos5260-clock.txt
@@ -0,0 +1,190 @@
1* Samsung Exynos5260 Clock Controller
2
3Exynos5260 has 13 clock controllers which are instantiated
4independently from the device-tree. These clock controllers
5generate and supply clocks to various hardware blocks within
6the SoC.
7
8Each clock is assigned an identifier and client nodes can use
9this identifier to specify the clock which they consume. All
10available clocks are defined as preprocessor macros in
11dt-bindings/clock/exynos5260-clk.h header and can be used in
12device tree sources.
13
14External clocks:
15
16There are several clocks that are generated outside the SoC. It
17is expected that they are defined using standard clock bindings
18with following clock-output-names:
19
20 - "fin_pll" - PLL input clock from XXTI
21 - "xrtcxti" - input clock from XRTCXTI
22 - "ioclk_pcm_extclk" - pcm external operation clock
23 - "ioclk_spdif_extclk" - spdif external operation clock
24 - "ioclk_i2s_cdclk" - i2s0 codec clock
25
26Phy clocks:
27
28There are several clocks which are generated by specific PHYs.
29These clocks are fed into the clock controller and then routed to
30the hardware blocks. These clocks are defined as fixed clocks in the
31driver with following names:
32
33 - "phyclk_dptx_phy_ch3_txd_clk" - dp phy clock for channel 3
34 - "phyclk_dptx_phy_ch2_txd_clk" - dp phy clock for channel 2
35 - "phyclk_dptx_phy_ch1_txd_clk" - dp phy clock for channel 1
36 - "phyclk_dptx_phy_ch0_txd_clk" - dp phy clock for channel 0
37 - "phyclk_hdmi_phy_tmds_clko" - hdmi phy tmds clock
38 - "phyclk_hdmi_phy_pixel_clko" - hdmi phy pixel clock
39 - "phyclk_hdmi_link_o_tmds_clkhi" - hdmi phy for hdmi link
40 - "phyclk_dptx_phy_o_ref_clk_24m" - dp phy reference clock
41 - "phyclk_dptx_phy_clk_div2"
42 - "phyclk_mipi_dphy_4l_m_rxclkesc0"
43 - "phyclk_usbhost20_phy_phyclock" - usb 2.0 phy clock
44 - "phyclk_usbhost20_phy_freeclk"
45 - "phyclk_usbhost20_phy_clk48mohci"
46 - "phyclk_usbdrd30_udrd30_pipe_pclk"
47 - "phyclk_usbdrd30_udrd30_phyclock" - usb 3.0 phy clock
48
49Required Properties for Clock Controller:
50
51 - compatible: should be one of the following.
52 1) "samsung,exynos5260-clock-top"
53 2) "samsung,exynos5260-clock-peri"
54 3) "samsung,exynos5260-clock-egl"
55 4) "samsung,exynos5260-clock-kfc"
56 5) "samsung,exynos5260-clock-g2d"
57 6) "samsung,exynos5260-clock-mif"
58 7) "samsung,exynos5260-clock-mfc"
59 8) "samsung,exynos5260-clock-g3d"
60 9) "samsung,exynos5260-clock-fsys"
61 10) "samsung,exynos5260-clock-aud"
62 11) "samsung,exynos5260-clock-isp"
63 12) "samsung,exynos5260-clock-gscl"
64 13) "samsung,exynos5260-clock-disp"
65
66 - reg: physical base address of the controller and the length of
67 memory mapped region.
68
69 - #clock-cells: should be 1.
70
71 - clocks: list of clock identifiers which are fed as the input to
72 the given clock controller. Please refer the next section to find
73 the input clocks for a given controller.
74
75 - clock-names: list of names of clocks which are fed as the input
76 to the given clock controller.
77
78Input clocks for top clock controller:
79 - fin_pll
80 - dout_mem_pll
81 - dout_bus_pll
82 - dout_media_pll
83
84Input clocks for peri clock controller:
85 - fin_pll
86 - ioclk_pcm_extclk
87 - ioclk_i2s_cdclk
88 - ioclk_spdif_extclk
89 - phyclk_hdmi_phy_ref_cko
90 - dout_aclk_peri_66
91 - dout_sclk_peri_uart0
92 - dout_sclk_peri_uart1
93 - dout_sclk_peri_uart2
94 - dout_sclk_peri_spi0_b
95 - dout_sclk_peri_spi1_b
96 - dout_sclk_peri_spi2_b
97 - dout_aclk_peri_aud
98 - dout_sclk_peri_spi0_b
99
100Input clocks for egl clock controller:
101 - fin_pll
102 - dout_bus_pll
103
104Input clocks for kfc clock controller:
105 - fin_pll
106 - dout_media_pll
107
108Input clocks for g2d clock controller:
109 - fin_pll
110 - dout_aclk_g2d_333
111
112Input clocks for mif clock controller:
113 - fin_pll
114
115Input clocks for mfc clock controller:
116 - fin_pll
117 - dout_aclk_mfc_333
118
119Input clocks for g3d clock controller:
120 - fin_pll
121
122Input clocks for fsys clock controller:
123 - fin_pll
124 - phyclk_usbhost20_phy_phyclock
125 - phyclk_usbhost20_phy_freeclk
126 - phyclk_usbhost20_phy_clk48mohci
127 - phyclk_usbdrd30_udrd30_pipe_pclk
128 - phyclk_usbdrd30_udrd30_phyclock
129 - dout_aclk_fsys_200
130
131Input clocks for aud clock controller:
132 - fin_pll
133 - fout_aud_pll
134 - ioclk_i2s_cdclk
135 - ioclk_pcm_extclk
136
137Input clocks for isp clock controller:
138 - fin_pll
139 - dout_aclk_isp1_266
140 - dout_aclk_isp1_400
141 - mout_aclk_isp1_266
142
143Input clocks for gscl clock controller:
144 - fin_pll
145 - dout_aclk_gscl_400
146 - dout_aclk_gscl_333
147
148Input clocks for disp clock controller:
149 - fin_pll
150 - phyclk_dptx_phy_ch3_txd_clk
151 - phyclk_dptx_phy_ch2_txd_clk
152 - phyclk_dptx_phy_ch1_txd_clk
153 - phyclk_dptx_phy_ch0_txd_clk
154 - phyclk_hdmi_phy_tmds_clko
155 - phyclk_hdmi_phy_ref_clko
156 - phyclk_hdmi_phy_pixel_clko
157 - phyclk_hdmi_link_o_tmds_clkhi
158 - phyclk_mipi_dphy_4l_m_txbyte_clkhs
159 - phyclk_dptx_phy_o_ref_clk_24m
160 - phyclk_dptx_phy_clk_div2
161 - phyclk_mipi_dphy_4l_m_rxclkesc0
162 - phyclk_hdmi_phy_ref_cko
163 - ioclk_spdif_extclk
164 - dout_aclk_peri_aud
165 - dout_aclk_disp_222
166 - dout_sclk_disp_pixel
167 - dout_aclk_disp_333
168
169Example 1: An example of a clock controller node is listed below.
170
171 clock_mfc: clock-controller@11090000 {
172 compatible = "samsung,exynos5260-clock-mfc";
173 clock = <&fin_pll>, <&clock_top TOP_DOUT_ACLK_MFC_333>;
174 clock-names = "fin_pll", "dout_aclk_mfc_333";
175 reg = <0x11090000 0x10000>;
176 #clock-cells = <1>;
177 };
178
179Example 2: UART controller node that consumes the clock generated by the
180 peri clock controller. Refer to the standard clock bindings for
181 information about 'clocks' and 'clock-names' property.
182
183 serial@12C00000 {
184 compatible = "samsung,exynos4210-uart";
185 reg = <0x12C00000 0x100>;
186 interrupts = <0 146 0>;
187 clocks = <&clock_peri PERI_PCLK_UART0>, <&clock_peri PERI_SCLK_UART0>;
188 clock-names = "uart", "clk_uart_baud0";
189 };
190
diff --git a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
index ca88c97a8562..d54f42cf0440 100644
--- a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
@@ -1,12 +1,13 @@
1* Samsung Exynos5420 Clock Controller 1* Samsung Exynos5420 Clock Controller
2 2
3The Exynos5420 clock controller generates and supplies clock to various 3The Exynos5420 clock controller generates and supplies clock to various
4controllers within the Exynos5420 SoC. 4controllers within the Exynos5420 SoC and for the Exynos5800 SoC.
5 5
6Required Properties: 6Required Properties:
7 7
8- compatible: should be one of the following. 8- compatible: should be one of the following.
9 - "samsung,exynos5420-clock" - controller compatible with Exynos5420 SoC. 9 - "samsung,exynos5420-clock" - controller compatible with Exynos5420 SoC.
10 - "samsung,exynos5800-clock" - controller compatible with Exynos5800 SoC.
10 11
11- reg: physical base address of the controller and length of memory mapped 12- reg: physical base address of the controller and length of memory mapped
12 region. 13 region.
diff --git a/Documentation/devicetree/bindings/clock/samsung,s3c2410-clock.txt b/Documentation/devicetree/bindings/clock/samsung,s3c2410-clock.txt
index 0b64ad8dadf6..822505e715ae 100644
--- a/Documentation/devicetree/bindings/clock/samsung,s3c2410-clock.txt
+++ b/Documentation/devicetree/bindings/clock/samsung,s3c2410-clock.txt
@@ -19,7 +19,7 @@ to specify the clock which they consume. Some of the clocks are available only
19on a particular SoC. 19on a particular SoC.
20 20
21All available clocks are defined as preprocessor macros in 21All available clocks are defined as preprocessor macros in
22dt-bindings/clock/samsung,s3c2410-clock.h header and can be used in device 22dt-bindings/clock/s3c2410.h header and can be used in device
23tree sources. 23tree sources.
24 24
25External clocks: 25External clocks:
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index db3c5414223e..044e32be02b5 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -755,7 +755,7 @@ config ARCH_S3C64XX
755 select ATAGS 755 select ATAGS
756 select CLKDEV_LOOKUP 756 select CLKDEV_LOOKUP
757 select CLKSRC_SAMSUNG_PWM 757 select CLKSRC_SAMSUNG_PWM
758 select COMMON_CLK 758 select COMMON_CLK_SAMSUNG
759 select CPU_V6K 759 select CPU_V6K
760 select GENERIC_CLOCKEVENTS 760 select GENERIC_CLOCKEVENTS
761 select GPIO_SAMSUNG 761 select GPIO_SAMSUNG
@@ -836,7 +836,7 @@ config ARCH_EXYNOS
836 select ARCH_REQUIRE_GPIOLIB 836 select ARCH_REQUIRE_GPIOLIB
837 select ARCH_SPARSEMEM_ENABLE 837 select ARCH_SPARSEMEM_ENABLE
838 select ARM_GIC 838 select ARM_GIC
839 select COMMON_CLK 839 select COMMON_CLK_SAMSUNG
840 select CPU_V7 840 select CPU_V7
841 select GENERIC_CLOCKEVENTS 841 select GENERIC_CLOCKEVENTS
842 select HAVE_S3C2410_I2C if I2C 842 select HAVE_S3C2410_I2C if I2C
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 418f2506aaf0..d433fe4d00f0 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -546,7 +546,7 @@
546 #size-cells = <0>; 546 #size-cells = <0>;
547 pinctrl-names = "default"; 547 pinctrl-names = "default";
548 pinctrl-0 = <&i2c4_hs_bus>; 548 pinctrl-0 = <&i2c4_hs_bus>;
549 clocks = <&clock CLK_I2C4>; 549 clocks = <&clock CLK_USI0>;
550 clock-names = "hsi2c"; 550 clock-names = "hsi2c";
551 status = "disabled"; 551 status = "disabled";
552 }; 552 };
@@ -559,7 +559,7 @@
559 #size-cells = <0>; 559 #size-cells = <0>;
560 pinctrl-names = "default"; 560 pinctrl-names = "default";
561 pinctrl-0 = <&i2c5_hs_bus>; 561 pinctrl-0 = <&i2c5_hs_bus>;
562 clocks = <&clock CLK_I2C5>; 562 clocks = <&clock CLK_USI1>;
563 clock-names = "hsi2c"; 563 clock-names = "hsi2c";
564 status = "disabled"; 564 status = "disabled";
565 }; 565 };
@@ -572,7 +572,7 @@
572 #size-cells = <0>; 572 #size-cells = <0>;
573 pinctrl-names = "default"; 573 pinctrl-names = "default";
574 pinctrl-0 = <&i2c6_hs_bus>; 574 pinctrl-0 = <&i2c6_hs_bus>;
575 clocks = <&clock CLK_I2C6>; 575 clocks = <&clock CLK_USI2>;
576 clock-names = "hsi2c"; 576 clock-names = "hsi2c";
577 status = "disabled"; 577 status = "disabled";
578 }; 578 };
@@ -585,7 +585,7 @@
585 #size-cells = <0>; 585 #size-cells = <0>;
586 pinctrl-names = "default"; 586 pinctrl-names = "default";
587 pinctrl-0 = <&i2c7_hs_bus>; 587 pinctrl-0 = <&i2c7_hs_bus>;
588 clocks = <&clock CLK_I2C7>; 588 clocks = <&clock CLK_USI3>;
589 clock-names = "hsi2c"; 589 clock-names = "hsi2c";
590 status = "disabled"; 590 status = "disabled";
591 }; 591 };
@@ -598,7 +598,7 @@
598 #size-cells = <0>; 598 #size-cells = <0>;
599 pinctrl-names = "default"; 599 pinctrl-names = "default";
600 pinctrl-0 = <&i2c8_hs_bus>; 600 pinctrl-0 = <&i2c8_hs_bus>;
601 clocks = <&clock CLK_I2C8>; 601 clocks = <&clock CLK_USI4>;
602 clock-names = "hsi2c"; 602 clock-names = "hsi2c";
603 status = "disabled"; 603 status = "disabled";
604 }; 604 };
@@ -611,7 +611,7 @@
611 #size-cells = <0>; 611 #size-cells = <0>;
612 pinctrl-names = "default"; 612 pinctrl-names = "default";
613 pinctrl-0 = <&i2c9_hs_bus>; 613 pinctrl-0 = <&i2c9_hs_bus>;
614 clocks = <&clock CLK_I2C9>; 614 clocks = <&clock CLK_USI5>;
615 clock-names = "hsi2c"; 615 clock-names = "hsi2c";
616 status = "disabled"; 616 status = "disabled";
617 }; 617 };
@@ -624,7 +624,7 @@
624 #size-cells = <0>; 624 #size-cells = <0>;
625 pinctrl-names = "default"; 625 pinctrl-names = "default";
626 pinctrl-0 = <&i2c10_hs_bus>; 626 pinctrl-0 = <&i2c10_hs_bus>;
627 clocks = <&clock CLK_I2C10>; 627 clocks = <&clock CLK_USI6>;
628 clock-names = "hsi2c"; 628 clock-names = "hsi2c";
629 status = "disabled"; 629 status = "disabled";
630 }; 630 };
diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index 45a7026e9419..04284de7aca5 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -18,17 +18,7 @@ config PLAT_S3C24XX
18 help 18 help
19 Base platform code for any Samsung S3C24XX device 19 Base platform code for any Samsung S3C24XX device
20 20
21config S3C2410_COMMON_CLK
22 bool
23 help
24 Build the s3c2410 clock driver based on the common clock framework.
25 21
26config S3C2410_COMMON_DCLK
27 bool
28 select REGMAP_MMIO
29 help
30 Temporary symbol to build the dclk driver based on the common clock
31 framework.
32 22
33menu "SAMSUNG S3C24XX SoCs Support" 23menu "SAMSUNG S3C24XX SoCs Support"
34 24
@@ -37,7 +27,6 @@ comment "S3C24XX SoCs"
37config CPU_S3C2410 27config CPU_S3C2410
38 bool "SAMSUNG S3C2410" 28 bool "SAMSUNG S3C2410"
39 default y 29 default y
40 select COMMON_CLK
41 select CPU_ARM920T 30 select CPU_ARM920T
42 select S3C2410_COMMON_CLK 31 select S3C2410_COMMON_CLK
43 select S3C2410_DMA if S3C24XX_DMA 32 select S3C2410_DMA if S3C24XX_DMA
@@ -50,7 +39,6 @@ config CPU_S3C2410
50 39
51config CPU_S3C2412 40config CPU_S3C2412
52 bool "SAMSUNG S3C2412" 41 bool "SAMSUNG S3C2412"
53 select COMMON_CLK
54 select CPU_ARM926T 42 select CPU_ARM926T
55 select S3C2412_COMMON_CLK 43 select S3C2412_COMMON_CLK
56 select S3C2412_DMA if S3C24XX_DMA 44 select S3C2412_DMA if S3C24XX_DMA
@@ -60,7 +48,6 @@ config CPU_S3C2412
60 48
61config CPU_S3C2416 49config CPU_S3C2416
62 bool "SAMSUNG S3C2416/S3C2450" 50 bool "SAMSUNG S3C2416/S3C2450"
63 select COMMON_CLK
64 select CPU_ARM926T 51 select CPU_ARM926T
65 select S3C2416_PM if PM 52 select S3C2416_PM if PM
66 select S3C2443_COMMON_CLK 53 select S3C2443_COMMON_CLK
@@ -70,7 +57,6 @@ config CPU_S3C2416
70 57
71config CPU_S3C2440 58config CPU_S3C2440
72 bool "SAMSUNG S3C2440" 59 bool "SAMSUNG S3C2440"
73 select COMMON_CLK
74 select CPU_ARM920T 60 select CPU_ARM920T
75 select S3C2410_COMMON_CLK 61 select S3C2410_COMMON_CLK
76 select S3C2410_PM if PM 62 select S3C2410_PM if PM
@@ -80,7 +66,6 @@ config CPU_S3C2440
80 66
81config CPU_S3C2442 67config CPU_S3C2442
82 bool "SAMSUNG S3C2442" 68 bool "SAMSUNG S3C2442"
83 select COMMON_CLK
84 select CPU_ARM920T 69 select CPU_ARM920T
85 select S3C2410_COMMON_CLK 70 select S3C2410_COMMON_CLK
86 select S3C2410_DMA if S3C24XX_DMA 71 select S3C2410_DMA if S3C24XX_DMA
@@ -95,7 +80,6 @@ config CPU_S3C244X
95 80
96config CPU_S3C2443 81config CPU_S3C2443
97 bool "SAMSUNG S3C2443" 82 bool "SAMSUNG S3C2443"
98 select COMMON_CLK
99 select CPU_ARM920T 83 select CPU_ARM920T
100 select S3C2443_COMMON_CLK 84 select S3C2443_COMMON_CLK
101 select S3C2443_DMA if S3C24XX_DMA 85 select S3C2443_DMA if S3C24XX_DMA
@@ -236,7 +220,7 @@ config ARCH_BAST
236 bool "Simtec Electronics BAST (EB2410ITX)" 220 bool "Simtec Electronics BAST (EB2410ITX)"
237 select ISA 221 select ISA
238 select MACH_BAST_IDE 222 select MACH_BAST_IDE
239 select S3C2410_COMMON_DCLK if COMMON_CLK 223 select S3C2410_COMMON_DCLK
240 select S3C2410_IOTIMING if ARM_S3C2410_CPUFREQ 224 select S3C2410_IOTIMING if ARM_S3C2410_CPUFREQ
241 select S3C24XX_SIMTEC_NOR 225 select S3C24XX_SIMTEC_NOR
242 select S3C24XX_SIMTEC_PM if PM 226 select S3C24XX_SIMTEC_PM if PM
@@ -318,7 +302,7 @@ config MACH_TCT_HAMMER
318config MACH_VR1000 302config MACH_VR1000
319 bool "Thorcom VR1000" 303 bool "Thorcom VR1000"
320 select MACH_BAST_IDE 304 select MACH_BAST_IDE
321 select S3C2410_COMMON_DCLK if COMMON_CLK 305 select S3C2410_COMMON_DCLK
322 select S3C24XX_SIMTEC_NOR 306 select S3C24XX_SIMTEC_NOR
323 select S3C24XX_SIMTEC_PM if PM 307 select S3C24XX_SIMTEC_PM if PM
324 select S3C24XX_SIMTEC_USB 308 select S3C24XX_SIMTEC_USB
@@ -337,11 +321,6 @@ config S3C2412_PM_SLEEP
337 321
338if CPU_S3C2412 322if CPU_S3C2412
339 323
340config S3C2412_COMMON_CLK
341 bool
342 help
343 Build the s3c2412 clock driver based on the common clock framework.
344
345config CPU_S3C2412_ONLY 324config CPU_S3C2412_ONLY
346 bool 325 bool
347 depends on !CPU_S3C2410 && !CPU_S3C2416 && !CPU_S3C2440 && \ 326 depends on !CPU_S3C2410 && !CPU_S3C2416 && !CPU_S3C2440 && \
@@ -502,7 +481,7 @@ comment "S3C2440 Boards"
502config MACH_ANUBIS 481config MACH_ANUBIS
503 bool "Simtec Electronics ANUBIS" 482 bool "Simtec Electronics ANUBIS"
504 select HAVE_PATA_PLATFORM 483 select HAVE_PATA_PLATFORM
505 select S3C2410_COMMON_DCLK if COMMON_CLK 484 select S3C2410_COMMON_DCLK
506 select S3C2440_XTAL_12000000 485 select S3C2440_XTAL_12000000
507 select S3C24XX_SIMTEC_PM if PM 486 select S3C24XX_SIMTEC_PM if PM
508 select S3C_DEV_USB_HOST 487 select S3C_DEV_USB_HOST
@@ -541,7 +520,7 @@ config MACH_NEXCODER_2440
541 520
542config MACH_OSIRIS 521config MACH_OSIRIS
543 bool "Simtec IM2440D20 (OSIRIS) module" 522 bool "Simtec IM2440D20 (OSIRIS) module"
544 select S3C2410_COMMON_DCLK if COMMON_CLK 523 select S3C2410_COMMON_DCLK
545 select S3C2410_IOTIMING if ARM_S3C2440_CPUFREQ 524 select S3C2410_IOTIMING if ARM_S3C2440_CPUFREQ
546 select S3C2440_XTAL_12000000 525 select S3C2440_XTAL_12000000
547 select S3C24XX_SIMTEC_PM if PM 526 select S3C24XX_SIMTEC_PM if PM
@@ -612,7 +591,7 @@ config MACH_RX1950
612 bool "HP iPAQ rx1950" 591 bool "HP iPAQ rx1950"
613 select I2C 592 select I2C
614 select PM_H1940 if PM 593 select PM_H1940 if PM
615 select S3C2410_COMMON_DCLK if COMMON_CLK 594 select S3C2410_COMMON_DCLK
616 select S3C2410_IOTIMING if ARM_S3C2440_CPUFREQ 595 select S3C2410_IOTIMING if ARM_S3C2440_CPUFREQ
617 select S3C2440_XTAL_16934400 596 select S3C2440_XTAL_16934400
618 select S3C24XX_PWM 597 select S3C24XX_PWM
@@ -624,12 +603,6 @@ endif # CPU_S3C2442
624 603
625if CPU_S3C2443 || CPU_S3C2416 604if CPU_S3C2443 || CPU_S3C2416
626 605
627config S3C2443_COMMON_CLK
628 bool
629 help
630 Temporary symbol to build the clock driver based on the common clock
631 framework.
632
633config S3C2443_DMA 606config S3C2443_DMA
634 bool 607 bool
635 help 608 help
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 6f56d3a4f010..ba2436622645 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -115,3 +115,5 @@ endmenu
115 115
116source "drivers/clk/bcm/Kconfig" 116source "drivers/clk/bcm/Kconfig"
117source "drivers/clk/mvebu/Kconfig" 117source "drivers/clk/mvebu/Kconfig"
118
119source "drivers/clk/samsung/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 5f8a28735c96..17d7f13d19a5 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -41,7 +41,7 @@ obj-$(CONFIG_PLAT_ORION) += mvebu/
41obj-$(CONFIG_ARCH_MXS) += mxs/ 41obj-$(CONFIG_ARCH_MXS) += mxs/
42obj-$(CONFIG_COMMON_CLK_QCOM) += qcom/ 42obj-$(CONFIG_COMMON_CLK_QCOM) += qcom/
43obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ 43obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
44obj-$(CONFIG_PLAT_SAMSUNG) += samsung/ 44obj-$(CONFIG_COMMON_CLK_SAMSUNG) += samsung/
45obj-$(CONFIG_ARCH_SHMOBILE_MULTI) += shmobile/ 45obj-$(CONFIG_ARCH_SHMOBILE_MULTI) += shmobile/
46obj-$(CONFIG_ARCH_SIRF) += sirf/ 46obj-$(CONFIG_ARCH_SIRF) += sirf/
47obj-$(CONFIG_ARCH_SOCFPGA) += socfpga/ 47obj-$(CONFIG_ARCH_SOCFPGA) += socfpga/
diff --git a/drivers/clk/samsung/Kconfig b/drivers/clk/samsung/Kconfig
new file mode 100644
index 000000000000..84196ecdaa12
--- /dev/null
+++ b/drivers/clk/samsung/Kconfig
@@ -0,0 +1,26 @@
1config COMMON_CLK_SAMSUNG
2 bool
3 select COMMON_CLK
4
5config S3C2410_COMMON_CLK
6 bool
7 select COMMON_CLK_SAMSUNG
8 help
9 Build the s3c2410 clock driver based on the common clock framework.
10
11config S3C2410_COMMON_DCLK
12 bool
13 select COMMON_CLK_SAMSUNG
14 select REGMAP_MMIO
15 help
16 Temporary symbol to build the dclk driver based on the common clock
17 framework.
18
19config S3C2412_COMMON_CLK
20 bool
21 select COMMON_CLK_SAMSUNG
22
23config S3C2443_COMMON_CLK
24 bool
25 select COMMON_CLK_SAMSUNG
26
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 2cb62f87e068..25646c61a02b 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -3,8 +3,10 @@
3# 3#
4 4
5obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o 5obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
6obj-$(CONFIG_SOC_EXYNOS3250) += clk-exynos3250.o
6obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o 7obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
7obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o 8obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
9obj-$(CONFIG_SOC_EXYNOS5260) += clk-exynos5260.o
8obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o 10obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
9obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o 11obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
10obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o 12obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c
new file mode 100644
index 000000000000..7a17bd40d1dd
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos3250.c
@@ -0,0 +1,780 @@
1/*
2 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * Common Clock Framework support for Exynos3250 SoC.
9 */
10
11#include <linux/clk.h>
12#include <linux/clkdev.h>
13#include <linux/clk-provider.h>
14#include <linux/of.h>
15#include <linux/of_address.h>
16#include <linux/platform_device.h>
17#include <linux/syscore_ops.h>
18
19#include <dt-bindings/clock/exynos3250.h>
20
21#include "clk.h"
22#include "clk-pll.h"
23
24#define SRC_LEFTBUS 0x4200
25#define DIV_LEFTBUS 0x4500
26#define GATE_IP_LEFTBUS 0x4800
27#define SRC_RIGHTBUS 0x8200
28#define DIV_RIGHTBUS 0x8500
29#define GATE_IP_RIGHTBUS 0x8800
30#define GATE_IP_PERIR 0x8960
31#define MPLL_LOCK 0xc010
32#define MPLL_CON0 0xc110
33#define VPLL_LOCK 0xc020
34#define VPLL_CON0 0xc120
35#define UPLL_LOCK 0xc030
36#define UPLL_CON0 0xc130
37#define SRC_TOP0 0xc210
38#define SRC_TOP1 0xc214
39#define SRC_CAM 0xc220
40#define SRC_MFC 0xc228
41#define SRC_G3D 0xc22c
42#define SRC_LCD 0xc234
43#define SRC_ISP 0xc238
44#define SRC_FSYS 0xc240
45#define SRC_PERIL0 0xc250
46#define SRC_PERIL1 0xc254
47#define SRC_MASK_TOP 0xc310
48#define SRC_MASK_CAM 0xc320
49#define SRC_MASK_LCD 0xc334
50#define SRC_MASK_ISP 0xc338
51#define SRC_MASK_FSYS 0xc340
52#define SRC_MASK_PERIL0 0xc350
53#define SRC_MASK_PERIL1 0xc354
54#define DIV_TOP 0xc510
55#define DIV_CAM 0xc520
56#define DIV_MFC 0xc528
57#define DIV_G3D 0xc52c
58#define DIV_LCD 0xc534
59#define DIV_ISP 0xc538
60#define DIV_FSYS0 0xc540
61#define DIV_FSYS1 0xc544
62#define DIV_FSYS2 0xc548
63#define DIV_PERIL0 0xc550
64#define DIV_PERIL1 0xc554
65#define DIV_PERIL3 0xc55c
66#define DIV_PERIL4 0xc560
67#define DIV_PERIL5 0xc564
68#define DIV_CAM1 0xc568
69#define CLKDIV2_RATIO 0xc580
70#define GATE_SCLK_CAM 0xc820
71#define GATE_SCLK_MFC 0xc828
72#define GATE_SCLK_G3D 0xc82c
73#define GATE_SCLK_LCD 0xc834
74#define GATE_SCLK_ISP_TOP 0xc838
75#define GATE_SCLK_FSYS 0xc840
76#define GATE_SCLK_PERIL 0xc850
77#define GATE_IP_CAM 0xc920
78#define GATE_IP_MFC 0xc928
79#define GATE_IP_G3D 0xc92c
80#define GATE_IP_LCD 0xc934
81#define GATE_IP_ISP 0xc938
82#define GATE_IP_FSYS 0xc940
83#define GATE_IP_PERIL 0xc950
84#define GATE_BLOCK 0xc970
85#define APLL_LOCK 0x14000
86#define APLL_CON0 0x14100
87#define SRC_CPU 0x14200
88#define DIV_CPU0 0x14500
89#define DIV_CPU1 0x14504
90
91/* list of PLLs to be registered */
92enum exynos3250_plls {
93 apll, mpll, vpll, upll,
94 nr_plls
95};
96
97static void __iomem *reg_base;
98
99/*
100 * Support for CMU save/restore across system suspends
101 */
102#ifdef CONFIG_PM_SLEEP
103static struct samsung_clk_reg_dump *exynos3250_clk_regs;
104
105static unsigned long exynos3250_cmu_clk_regs[] __initdata = {
106 SRC_LEFTBUS,
107 DIV_LEFTBUS,
108 GATE_IP_LEFTBUS,
109 SRC_RIGHTBUS,
110 DIV_RIGHTBUS,
111 GATE_IP_RIGHTBUS,
112 GATE_IP_PERIR,
113 MPLL_LOCK,
114 MPLL_CON0,
115 VPLL_LOCK,
116 VPLL_CON0,
117 UPLL_LOCK,
118 UPLL_CON0,
119 SRC_TOP0,
120 SRC_TOP1,
121 SRC_CAM,
122 SRC_MFC,
123 SRC_G3D,
124 SRC_LCD,
125 SRC_ISP,
126 SRC_FSYS,
127 SRC_PERIL0,
128 SRC_PERIL1,
129 SRC_MASK_TOP,
130 SRC_MASK_CAM,
131 SRC_MASK_LCD,
132 SRC_MASK_ISP,
133 SRC_MASK_FSYS,
134 SRC_MASK_PERIL0,
135 SRC_MASK_PERIL1,
136 DIV_TOP,
137 DIV_CAM,
138 DIV_MFC,
139 DIV_G3D,
140 DIV_LCD,
141 DIV_ISP,
142 DIV_FSYS0,
143 DIV_FSYS1,
144 DIV_FSYS2,
145 DIV_PERIL0,
146 DIV_PERIL1,
147 DIV_PERIL3,
148 DIV_PERIL4,
149 DIV_PERIL5,
150 DIV_CAM1,
151 CLKDIV2_RATIO,
152 GATE_SCLK_CAM,
153 GATE_SCLK_MFC,
154 GATE_SCLK_G3D,
155 GATE_SCLK_LCD,
156 GATE_SCLK_ISP_TOP,
157 GATE_SCLK_FSYS,
158 GATE_SCLK_PERIL,
159 GATE_IP_CAM,
160 GATE_IP_MFC,
161 GATE_IP_G3D,
162 GATE_IP_LCD,
163 GATE_IP_ISP,
164 GATE_IP_FSYS,
165 GATE_IP_PERIL,
166 GATE_BLOCK,
167 APLL_LOCK,
168 SRC_CPU,
169 DIV_CPU0,
170 DIV_CPU1,
171};
172
173static int exynos3250_clk_suspend(void)
174{
175 samsung_clk_save(reg_base, exynos3250_clk_regs,
176 ARRAY_SIZE(exynos3250_cmu_clk_regs));
177 return 0;
178}
179
180static void exynos3250_clk_resume(void)
181{
182 samsung_clk_restore(reg_base, exynos3250_clk_regs,
183 ARRAY_SIZE(exynos3250_cmu_clk_regs));
184}
185
186static struct syscore_ops exynos3250_clk_syscore_ops = {
187 .suspend = exynos3250_clk_suspend,
188 .resume = exynos3250_clk_resume,
189};
190
191static void exynos3250_clk_sleep_init(void)
192{
193 exynos3250_clk_regs =
194 samsung_clk_alloc_reg_dump(exynos3250_cmu_clk_regs,
195 ARRAY_SIZE(exynos3250_cmu_clk_regs));
196 if (!exynos3250_clk_regs) {
197 pr_warn("%s: Failed to allocate sleep save data\n", __func__);
198 goto err;
199 }
200
201 register_syscore_ops(&exynos3250_clk_syscore_ops);
202 return;
203err:
204 kfree(exynos3250_clk_regs);
205}
206#else
207static inline void exynos3250_clk_sleep_init(void) { }
208#endif
209
210/* list of all parent clock list */
211PNAME(mout_vpllsrc_p) = { "fin_pll", };
212
213PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
214PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", };
215PNAME(mout_vpll_p) = { "fin_pll", "fout_vpll", };
216PNAME(mout_upll_p) = { "fin_pll", "fout_upll", };
217
218PNAME(mout_mpll_user_p) = { "fin_pll", "div_mpll_pre", };
219PNAME(mout_epll_user_p) = { "fin_pll", "mout_epll", };
220PNAME(mout_core_p) = { "mout_apll", "mout_mpll_user_c", };
221PNAME(mout_hpm_p) = { "mout_apll", "mout_mpll_user_c", };
222
223PNAME(mout_ebi_p) = { "div_aclk_200", "div_aclk_160", };
224PNAME(mout_ebi_1_p) = { "mout_ebi", "mout_vpll", };
225
226PNAME(mout_gdl_p) = { "mout_mpll_user_l", };
227PNAME(mout_gdr_p) = { "mout_mpll_user_r", };
228
229PNAME(mout_aclk_400_mcuisp_sub_p)
230 = { "fin_pll", "div_aclk_400_mcuisp", };
231PNAME(mout_aclk_266_0_p) = { "div_mpll_pre", "mout_vpll", };
232PNAME(mout_aclk_266_1_p) = { "mout_epll_user", };
233PNAME(mout_aclk_266_p) = { "mout_aclk_266_0", "mout_aclk_266_1", };
234PNAME(mout_aclk_266_sub_p) = { "fin_pll", "div_aclk_266", };
235
236PNAME(group_div_mpll_pre_p) = { "div_mpll_pre", };
237PNAME(group_epll_vpll_p) = { "mout_epll_user", "mout_vpll" };
238PNAME(group_sclk_p) = { "xxti", "xusbxti",
239 "none", "none",
240 "none", "none", "div_mpll_pre",
241 "mout_epll_user", "mout_vpll", };
242PNAME(group_sclk_audio_p) = { "audiocdclk", "none",
243 "none", "none",
244 "xxti", "xusbxti",
245 "div_mpll_pre", "mout_epll_user",
246 "mout_vpll", };
247PNAME(group_sclk_cam_blk_p) = { "xxti", "xusbxti",
248 "none", "none", "none",
249 "none", "div_mpll_pre",
250 "mout_epll_user", "mout_vpll",
251 "div_cam_blk_320", };
252PNAME(group_sclk_fimd0_p) = { "xxti", "xusbxti",
253 "m_bitclkhsdiv4_2l", "none",
254 "none", "none", "div_mpll_pre",
255 "mout_epll_user", "mout_vpll",
256 "none", "none", "none",
257 "div_lcd_blk_145", };
258
259PNAME(mout_mfc_p) = { "mout_mfc_0", "mout_mfc_1" };
260PNAME(mout_g3d_p) = { "mout_g3d_0", "mout_g3d_1" };
261
262static struct samsung_fixed_factor_clock fixed_factor_clks[] __initdata = {
263 FFACTOR(0, "sclk_mpll_1600", "mout_mpll", 1, 1, 0),
264 FFACTOR(0, "sclk_mpll_mif", "mout_mpll", 1, 2, 0),
265 FFACTOR(0, "sclk_bpll", "fout_bpll", 1, 2, 0),
266 FFACTOR(0, "div_cam_blk_320", "sclk_mpll_1600", 1, 5, 0),
267 FFACTOR(0, "div_lcd_blk_145", "sclk_mpll_1600", 1, 11, 0),
268
269 /* HACK: fin_pll hardcoded to xusbxti until detection is implemented. */
270 FFACTOR(CLK_FIN_PLL, "fin_pll", "xusbxti", 1, 1, 0),
271};
272
273static struct samsung_mux_clock mux_clks[] __initdata = {
274 /*
275 * NOTE: Following table is sorted by register address in ascending
276 * order and then bitfield shift in descending order, as it is done
277 * in the User's Manual. When adding new entries, please make sure
278 * that the order is preserved, to avoid merge conflicts and make
279 * further work with defined data easier.
280 */
281
282 /* SRC_LEFTBUS */
283 MUX(CLK_MOUT_MPLL_USER_L, "mout_mpll_user_l", mout_mpll_user_p,
284 SRC_LEFTBUS, 4, 1),
285 MUX(CLK_MOUT_GDL, "mout_gdl", mout_gdl_p, SRC_LEFTBUS, 0, 1),
286
287 /* SRC_RIGHTBUS */
288 MUX(CLK_MOUT_MPLL_USER_R, "mout_mpll_user_r", mout_mpll_user_p,
289 SRC_RIGHTBUS, 4, 1),
290 MUX(CLK_MOUT_GDR, "mout_gdr", mout_gdr_p, SRC_RIGHTBUS, 0, 1),
291
292 /* SRC_TOP0 */
293 MUX(CLK_MOUT_EBI, "mout_ebi", mout_ebi_p, SRC_TOP0, 28, 1),
294 MUX(CLK_MOUT_ACLK_200, "mout_aclk_200", group_div_mpll_pre_p,SRC_TOP0, 24, 1),
295 MUX(CLK_MOUT_ACLK_160, "mout_aclk_160", group_div_mpll_pre_p, SRC_TOP0, 20, 1),
296 MUX(CLK_MOUT_ACLK_100, "mout_aclk_100", group_div_mpll_pre_p, SRC_TOP0, 16, 1),
297 MUX(CLK_MOUT_ACLK_266_1, "mout_aclk_266_1", mout_aclk_266_1_p, SRC_TOP0, 14, 1),
298 MUX(CLK_MOUT_ACLK_266_0, "mout_aclk_266_0", mout_aclk_266_0_p, SRC_TOP0, 13, 1),
299 MUX(CLK_MOUT_ACLK_266, "mout_aclk_266", mout_aclk_266_p, SRC_TOP0, 12, 1),
300 MUX(CLK_MOUT_VPLL, "mout_vpll", mout_vpll_p, SRC_TOP0, 8, 1),
301 MUX(CLK_MOUT_EPLL_USER, "mout_epll_user", mout_epll_user_p, SRC_TOP0, 4, 1),
302 MUX(CLK_MOUT_EBI_1, "mout_ebi_1", mout_ebi_1_p, SRC_TOP0, 0, 1),
303
304 /* SRC_TOP1 */
305 MUX(CLK_MOUT_UPLL, "mout_upll", mout_upll_p, SRC_TOP1, 28, 1),
306 MUX(CLK_MOUT_ACLK_400_MCUISP_SUB, "mout_aclk_400_mcuisp_sub", mout_aclk_400_mcuisp_sub_p,
307 SRC_TOP1, 24, 1),
308 MUX(CLK_MOUT_ACLK_266_SUB, "mout_aclk_266_sub", mout_aclk_266_sub_p, SRC_TOP1, 20, 1),
309 MUX(CLK_MOUT_MPLL, "mout_mpll", mout_mpll_p, SRC_TOP1, 12, 1),
310 MUX(CLK_MOUT_ACLK_400_MCUISP, "mout_aclk_400_mcuisp", group_div_mpll_pre_p, SRC_TOP1, 8, 1),
311 MUX(CLK_MOUT_VPLLSRC, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1),
312
313 /* SRC_CAM */
314 MUX(CLK_MOUT_CAM1, "mout_cam1", group_sclk_p, SRC_CAM, 20, 4),
315 MUX(CLK_MOUT_CAM_BLK, "mout_cam_blk", group_sclk_cam_blk_p, SRC_CAM, 0, 4),
316
317 /* SRC_MFC */
318 MUX(CLK_MOUT_MFC, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
319 MUX(CLK_MOUT_MFC_1, "mout_mfc_1", group_epll_vpll_p, SRC_MFC, 4, 1),
320 MUX(CLK_MOUT_MFC_0, "mout_mfc_0", group_div_mpll_pre_p, SRC_MFC, 0, 1),
321
322 /* SRC_G3D */
323 MUX(CLK_MOUT_G3D, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1),
324 MUX(CLK_MOUT_G3D_1, "mout_g3d_1", group_epll_vpll_p, SRC_G3D, 4, 1),
325 MUX(CLK_MOUT_G3D_0, "mout_g3d_0", group_div_mpll_pre_p, SRC_G3D, 0, 1),
326
327 /* SRC_LCD */
328 MUX(CLK_MOUT_MIPI0, "mout_mipi0", group_sclk_p, SRC_LCD, 12, 4),
329 MUX(CLK_MOUT_FIMD0, "mout_fimd0", group_sclk_fimd0_p, SRC_LCD, 0, 4),
330
331 /* SRC_ISP */
332 MUX(CLK_MOUT_UART_ISP, "mout_uart_isp", group_sclk_p, SRC_ISP, 12, 4),
333 MUX(CLK_MOUT_SPI1_ISP, "mout_spi1_isp", group_sclk_p, SRC_ISP, 8, 4),
334 MUX(CLK_MOUT_SPI0_ISP, "mout_spi0_isp", group_sclk_p, SRC_ISP, 4, 4),
335
336 /* SRC_FSYS */
337 MUX(CLK_MOUT_TSADC, "mout_tsadc", group_sclk_p, SRC_FSYS, 28, 4),
338 MUX(CLK_MOUT_MMC1, "mout_mmc1", group_sclk_p, SRC_FSYS, 4, 3),
339 MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 3),
340
341 /* SRC_PERIL0 */
342 MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0, 4, 4),
343 MUX(CLK_MOUT_UART0, "mout_uart0", group_sclk_p, SRC_PERIL0, 0, 4),
344
345 /* SRC_PERIL1 */
346 MUX(CLK_MOUT_SPI1, "mout_spi1", group_sclk_p, SRC_PERIL1, 20, 4),
347 MUX(CLK_MOUT_SPI0, "mout_spi0", group_sclk_p, SRC_PERIL1, 16, 4),
348 MUX(CLK_MOUT_AUDIO, "mout_audio", group_sclk_audio_p, SRC_PERIL1, 4, 4),
349
350 /* SRC_CPU */
351 MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p,
352 SRC_CPU, 24, 1),
353 MUX(CLK_MOUT_HPM, "mout_hpm", mout_hpm_p, SRC_CPU, 20, 1),
354 MUX(CLK_MOUT_CORE, "mout_core", mout_core_p, SRC_CPU, 16, 1),
355 MUX(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1),
356};
357
358static struct samsung_div_clock div_clks[] __initdata = {
359 /*
360 * NOTE: Following table is sorted by register address in ascending
361 * order and then bitfield shift in descending order, as it is done
362 * in the User's Manual. When adding new entries, please make sure
363 * that the order is preserved, to avoid merge conflicts and make
364 * further work with defined data easier.
365 */
366
367 /* DIV_LEFTBUS */
368 DIV(CLK_DIV_GPL, "div_gpl", "div_gdl", DIV_LEFTBUS, 4, 3),
369 DIV(CLK_DIV_GDL, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 4),
370
371 /* DIV_RIGHTBUS */
372 DIV(CLK_DIV_GPR, "div_gpr", "div_gdr", DIV_RIGHTBUS, 4, 3),
373 DIV(CLK_DIV_GDR, "div_gdr", "mout_gdr", DIV_RIGHTBUS, 0, 4),
374
375 /* DIV_TOP */
376 DIV(CLK_DIV_MPLL_PRE, "div_mpll_pre", "sclk_mpll_mif", DIV_TOP, 28, 2),
377 DIV(CLK_DIV_ACLK_400_MCUISP, "div_aclk_400_mcuisp",
378 "mout_aclk_400_mcuisp", DIV_TOP, 24, 3),
379 DIV(CLK_DIV_EBI, "div_ebi", "mout_ebi_1", DIV_TOP, 16, 3),
380 DIV(CLK_DIV_ACLK_200, "div_aclk_200", "mout_aclk_200", DIV_TOP, 12, 3),
381 DIV(CLK_DIV_ACLK_160, "div_aclk_160", "mout_aclk_160", DIV_TOP, 8, 3),
382 DIV(CLK_DIV_ACLK_100, "div_aclk_100", "mout_aclk_100", DIV_TOP, 4, 4),
383 DIV(CLK_DIV_ACLK_266, "div_aclk_266", "mout_aclk_266", DIV_TOP, 0, 3),
384
385 /* DIV_CAM */
386 DIV(CLK_DIV_CAM1, "div_cam1", "mout_cam1", DIV_CAM, 20, 4),
387 DIV(CLK_DIV_CAM_BLK, "div_cam_blk", "mout_cam_blk", DIV_CAM, 0, 4),
388
389 /* DIV_MFC */
390 DIV(CLK_DIV_MFC, "div_mfc", "mout_mfc", DIV_MFC, 0, 4),
391
392 /* DIV_G3D */
393 DIV(CLK_DIV_G3D, "div_g3d", "mout_g3d", DIV_G3D, 0, 4),
394
395 /* DIV_LCD */
396 DIV_F(CLK_DIV_MIPI0_PRE, "div_mipi0_pre", "div_mipi0", DIV_LCD, 20, 4,
397 CLK_SET_RATE_PARENT, 0),
398 DIV(CLK_DIV_MIPI0, "div_mipi0", "mout_mipi0", DIV_LCD, 16, 4),
399 DIV(CLK_DIV_FIMD0, "div_fimd0", "mout_fimd0", DIV_LCD, 0, 4),
400
401 /* DIV_ISP */
402 DIV(CLK_DIV_UART_ISP, "div_uart_isp", "mout_uart_isp", DIV_ISP, 28, 4),
403 DIV_F(CLK_DIV_SPI1_ISP_PRE, "div_spi1_isp_pre", "div_spi1_isp",
404 DIV_ISP, 20, 8, CLK_SET_RATE_PARENT, 0),
405 DIV(CLK_DIV_SPI1_ISP, "div_spi1_isp", "mout_spi1_isp", DIV_ISP, 16, 4),
406 DIV_F(CLK_DIV_SPI0_ISP_PRE, "div_spi0_isp_pre", "div_spi0_isp",
407 DIV_ISP, 8, 8, CLK_SET_RATE_PARENT, 0),
408 DIV(CLK_DIV_SPI0_ISP, "div_spi0_isp", "mout_spi0_isp", DIV_ISP, 0, 4),
409
410 /* DIV_FSYS0 */
411 DIV_F(CLK_DIV_TSADC_PRE, "div_tsadc_pre", "div_tsadc", DIV_FSYS0, 8, 8,
412 CLK_SET_RATE_PARENT, 0),
413 DIV(CLK_DIV_TSADC, "div_tsadc", "mout_tsadc", DIV_FSYS0, 0, 4),
414
415 /* DIV_FSYS1 */
416 DIV_F(CLK_DIV_MMC1_PRE, "div_mmc1_pre", "div_mmc1", DIV_FSYS1, 24, 8,
417 CLK_SET_RATE_PARENT, 0),
418 DIV(CLK_DIV_MMC1, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
419 DIV_F(CLK_DIV_MMC0_PRE, "div_mmc0_pre", "div_mmc0", DIV_FSYS1, 8, 8,
420 CLK_SET_RATE_PARENT, 0),
421 DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
422
423 /* DIV_PERIL0 */
424 DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
425 DIV(CLK_DIV_UART0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
426
427 /* DIV_PERIL1 */
428 DIV_F(CLK_DIV_SPI1_PRE, "div_spi1_pre", "div_spi1", DIV_PERIL1, 24, 8,
429 CLK_SET_RATE_PARENT, 0),
430 DIV(CLK_DIV_SPI1, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4),
431 DIV_F(CLK_DIV_SPI0_PRE, "div_spi0_pre", "div_spi0", DIV_PERIL1, 8, 8,
432 CLK_SET_RATE_PARENT, 0),
433 DIV(CLK_DIV_SPI0, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4),
434
435 /* DIV_PERIL4 */
436 DIV(CLK_DIV_PCM, "div_pcm", "div_audio", DIV_PERIL4, 20, 8),
437 DIV(CLK_DIV_AUDIO, "div_audio", "mout_audio", DIV_PERIL4, 16, 4),
438
439 /* DIV_PERIL5 */
440 DIV(CLK_DIV_I2S, "div_i2s", "div_audio", DIV_PERIL5, 8, 6),
441
442 /* DIV_CPU0 */
443 DIV(CLK_DIV_CORE2, "div_core2", "div_core", DIV_CPU0, 28, 3),
444 DIV(CLK_DIV_APLL, "div_apll", "mout_apll", DIV_CPU0, 24, 3),
445 DIV(CLK_DIV_PCLK_DBG, "div_pclk_dbg", "div_core2", DIV_CPU0, 20, 3),
446 DIV(CLK_DIV_ATB, "div_atb", "div_core2", DIV_CPU0, 16, 3),
447 DIV(CLK_DIV_COREM, "div_corem", "div_core2", DIV_CPU0, 4, 3),
448 DIV(CLK_DIV_CORE, "div_core", "mout_core", DIV_CPU0, 0, 3),
449
450 /* DIV_CPU1 */
451 DIV(CLK_DIV_HPM, "div_hpm", "div_copy", DIV_CPU1, 4, 3),
452 DIV(CLK_DIV_COPY, "div_copy", "mout_hpm", DIV_CPU1, 0, 3),
453};
454
455static struct samsung_gate_clock gate_clks[] __initdata = {
456 /*
457 * NOTE: Following table is sorted by register address in ascending
458 * order and then bitfield shift in descending order, as it is done
459 * in the User's Manual. When adding new entries, please make sure
460 * that the order is preserved, to avoid merge conflicts and make
461 * further work with defined data easier.
462 */
463
464 /* GATE_IP_LEFTBUS */
465 GATE(CLK_ASYNC_G3D, "async_g3d", "div_aclk_100", GATE_IP_LEFTBUS, 6,
466 CLK_IGNORE_UNUSED, 0),
467 GATE(CLK_ASYNC_MFCL, "async_mfcl", "div_aclk_100", GATE_IP_LEFTBUS, 4,
468 CLK_IGNORE_UNUSED, 0),
469 GATE(CLK_PPMULEFT, "ppmuleft", "div_aclk_100", GATE_IP_LEFTBUS, 1,
470 CLK_IGNORE_UNUSED, 0),
471 GATE(CLK_GPIO_LEFT, "gpio_left", "div_aclk_100", GATE_IP_LEFTBUS, 0,
472 CLK_IGNORE_UNUSED, 0),
473
474 /* GATE_IP_RIGHTBUS */
475 GATE(CLK_ASYNC_ISPMX, "async_ispmx", "div_aclk_100",
476 GATE_IP_RIGHTBUS, 9, CLK_IGNORE_UNUSED, 0),
477 GATE(CLK_ASYNC_FSYSD, "async_fsysd", "div_aclk_100",
478 GATE_IP_RIGHTBUS, 5, CLK_IGNORE_UNUSED, 0),
479 GATE(CLK_ASYNC_LCD0X, "async_lcd0x", "div_aclk_100",
480 GATE_IP_RIGHTBUS, 3, CLK_IGNORE_UNUSED, 0),
481 GATE(CLK_ASYNC_CAMX, "async_camx", "div_aclk_100", GATE_IP_RIGHTBUS, 2,
482 CLK_IGNORE_UNUSED, 0),
483 GATE(CLK_PPMURIGHT, "ppmuright", "div_aclk_100", GATE_IP_RIGHTBUS, 1,
484 CLK_IGNORE_UNUSED, 0),
485 GATE(CLK_GPIO_RIGHT, "gpio_right", "div_aclk_100", GATE_IP_RIGHTBUS, 0,
486 CLK_IGNORE_UNUSED, 0),
487
488 /* GATE_IP_PERIR */
489 GATE(CLK_MONOCNT, "monocnt", "div_aclk_100", GATE_IP_PERIR, 22,
490 CLK_IGNORE_UNUSED, 0),
491 GATE(CLK_TZPC6, "tzpc6", "div_aclk_100", GATE_IP_PERIR, 21,
492 CLK_IGNORE_UNUSED, 0),
493 GATE(CLK_PROVISIONKEY1, "provisionkey1", "div_aclk_100",
494 GATE_IP_PERIR, 20, CLK_IGNORE_UNUSED, 0),
495 GATE(CLK_PROVISIONKEY0, "provisionkey0", "div_aclk_100",
496 GATE_IP_PERIR, 19, CLK_IGNORE_UNUSED, 0),
497 GATE(CLK_CMU_ISPPART, "cmu_isppart", "div_aclk_100", GATE_IP_PERIR, 18,
498 CLK_IGNORE_UNUSED, 0),
499 GATE(CLK_TMU_APBIF, "tmu_apbif", "div_aclk_100",
500 GATE_IP_PERIR, 17, 0, 0),
501 GATE(CLK_KEYIF, "keyif", "div_aclk_100", GATE_IP_PERIR, 16, 0, 0),
502 GATE(CLK_RTC, "rtc", "div_aclk_100", GATE_IP_PERIR, 15, 0, 0),
503 GATE(CLK_WDT, "wdt", "div_aclk_100", GATE_IP_PERIR, 14, 0, 0),
504 GATE(CLK_MCT, "mct", "div_aclk_100", GATE_IP_PERIR, 13, 0, 0),
505 GATE(CLK_SECKEY, "seckey", "div_aclk_100", GATE_IP_PERIR, 12,
506 CLK_IGNORE_UNUSED, 0),
507 GATE(CLK_TZPC5, "tzpc5", "div_aclk_100", GATE_IP_PERIR, 10,
508 CLK_IGNORE_UNUSED, 0),
509 GATE(CLK_TZPC4, "tzpc4", "div_aclk_100", GATE_IP_PERIR, 9,
510 CLK_IGNORE_UNUSED, 0),
511 GATE(CLK_TZPC3, "tzpc3", "div_aclk_100", GATE_IP_PERIR, 8,
512 CLK_IGNORE_UNUSED, 0),
513 GATE(CLK_TZPC2, "tzpc2", "div_aclk_100", GATE_IP_PERIR, 7,
514 CLK_IGNORE_UNUSED, 0),
515 GATE(CLK_TZPC1, "tzpc1", "div_aclk_100", GATE_IP_PERIR, 6,
516 CLK_IGNORE_UNUSED, 0),
517 GATE(CLK_TZPC0, "tzpc0", "div_aclk_100", GATE_IP_PERIR, 5,
518 CLK_IGNORE_UNUSED, 0),
519 GATE(CLK_CMU_COREPART, "cmu_corepart", "div_aclk_100", GATE_IP_PERIR, 4,
520 CLK_IGNORE_UNUSED, 0),
521 GATE(CLK_CMU_TOPPART, "cmu_toppart", "div_aclk_100", GATE_IP_PERIR, 3,
522 CLK_IGNORE_UNUSED, 0),
523 GATE(CLK_PMU_APBIF, "pmu_apbif", "div_aclk_100", GATE_IP_PERIR, 2,
524 CLK_IGNORE_UNUSED, 0),
525 GATE(CLK_SYSREG, "sysreg", "div_aclk_100", GATE_IP_PERIR, 1,
526 CLK_IGNORE_UNUSED, 0),
527 GATE(CLK_CHIP_ID, "chip_id", "div_aclk_100", GATE_IP_PERIR, 0,
528 CLK_IGNORE_UNUSED, 0),
529
530 /* GATE_SCLK_CAM */
531 GATE(CLK_SCLK_JPEG, "sclk_jpeg", "div_cam_blk",
532 GATE_SCLK_CAM, 8, CLK_SET_RATE_PARENT, 0),
533 GATE(CLK_SCLK_M2MSCALER, "sclk_m2mscaler", "div_cam_blk",
534 GATE_SCLK_CAM, 2, CLK_SET_RATE_PARENT, 0),
535 GATE(CLK_SCLK_GSCALER1, "sclk_gscaler1", "div_cam_blk",
536 GATE_SCLK_CAM, 1, CLK_SET_RATE_PARENT, 0),
537 GATE(CLK_SCLK_GSCALER0, "sclk_gscaler0", "div_cam_blk",
538 GATE_SCLK_CAM, 0, CLK_SET_RATE_PARENT, 0),
539
540 /* GATE_SCLK_MFC */
541 GATE(CLK_SCLK_MFC, "sclk_mfc", "div_mfc",
542 GATE_SCLK_MFC, 0, CLK_SET_RATE_PARENT, 0),
543
544 /* GATE_SCLK_G3D */
545 GATE(CLK_SCLK_G3D, "sclk_g3d", "div_g3d",
546 GATE_SCLK_G3D, 0, CLK_SET_RATE_PARENT, 0),
547
548 /* GATE_SCLK_LCD */
549 GATE(CLK_SCLK_MIPIDPHY2L, "sclk_mipidphy2l", "div_mipi0",
550 GATE_SCLK_LCD, 4, CLK_SET_RATE_PARENT, 0),
551 GATE(CLK_SCLK_MIPI0, "sclk_mipi0", "div_mipi0_pre",
552 GATE_SCLK_LCD, 3, CLK_SET_RATE_PARENT, 0),
553 GATE(CLK_SCLK_FIMD0, "sclk_fimd0", "div_fimd0",
554 GATE_SCLK_LCD, 0, CLK_SET_RATE_PARENT, 0),
555
556 /* GATE_SCLK_ISP_TOP */
557 GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1",
558 GATE_SCLK_ISP_TOP, 4, CLK_SET_RATE_PARENT, 0),
559 GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "div_uart_isp",
560 GATE_SCLK_ISP_TOP, 3, CLK_SET_RATE_PARENT, 0),
561 GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "div_spi1_isp",
562 GATE_SCLK_ISP_TOP, 2, CLK_SET_RATE_PARENT, 0),
563 GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "div_spi0_isp",
564 GATE_SCLK_ISP_TOP, 1, CLK_SET_RATE_PARENT, 0),
565
566 /* GATE_SCLK_FSYS */
567 GATE(CLK_SCLK_UPLL, "sclk_upll", "mout_upll", GATE_SCLK_FSYS, 10, 0, 0),
568 GATE(CLK_SCLK_TSADC, "sclk_tsadc", "div_tsadc_pre",
569 GATE_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
570 GATE(CLK_SCLK_EBI, "sclk_ebi", "div_ebi",
571 GATE_SCLK_FSYS, 6, CLK_SET_RATE_PARENT, 0),
572 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc1_pre",
573 GATE_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
574 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc0_pre",
575 GATE_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
576
577 /* GATE_SCLK_PERIL */
578 GATE(CLK_SCLK_I2S, "sclk_i2s", "div_i2s",
579 GATE_SCLK_PERIL, 18, CLK_SET_RATE_PARENT, 0),
580 GATE(CLK_SCLK_PCM, "sclk_pcm", "div_pcm",
581 GATE_SCLK_PERIL, 16, CLK_SET_RATE_PARENT, 0),
582 GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi1_pre",
583 GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0),
584 GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre",
585 GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0),
586 GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
587 GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0),
588 GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
589 GATE_SCLK_PERIL, 0, CLK_SET_RATE_PARENT, 0),
590
591 /* GATE_IP_CAM */
592 GATE(CLK_QEJPEG, "qejpeg", "div_cam_blk_320", GATE_IP_CAM, 19,
593 CLK_IGNORE_UNUSED, 0),
594 GATE(CLK_PIXELASYNCM1, "pixelasyncm1", "div_cam_blk_320",
595 GATE_IP_CAM, 18, CLK_IGNORE_UNUSED, 0),
596 GATE(CLK_PIXELASYNCM0, "pixelasyncm0", "div_cam_blk_320",
597 GATE_IP_CAM, 17, CLK_IGNORE_UNUSED, 0),
598 GATE(CLK_PPMUCAMIF, "ppmucamif", "div_cam_blk_320",
599 GATE_IP_CAM, 16, CLK_IGNORE_UNUSED, 0),
600 GATE(CLK_QEM2MSCALER, "qem2mscaler", "div_cam_blk_320",
601 GATE_IP_CAM, 14, CLK_IGNORE_UNUSED, 0),
602 GATE(CLK_QEGSCALER1, "qegscaler1", "div_cam_blk_320",
603 GATE_IP_CAM, 13, CLK_IGNORE_UNUSED, 0),
604 GATE(CLK_QEGSCALER0, "qegscaler0", "div_cam_blk_320",
605 GATE_IP_CAM, 12, CLK_IGNORE_UNUSED, 0),
606 GATE(CLK_SMMUJPEG, "smmujpeg", "div_cam_blk_320",
607 GATE_IP_CAM, 11, 0, 0),
608 GATE(CLK_SMMUM2M2SCALER, "smmum2m2scaler", "div_cam_blk_320",
609 GATE_IP_CAM, 9, 0, 0),
610 GATE(CLK_SMMUGSCALER1, "smmugscaler1", "div_cam_blk_320",
611 GATE_IP_CAM, 8, 0, 0),
612 GATE(CLK_SMMUGSCALER0, "smmugscaler0", "div_cam_blk_320",
613 GATE_IP_CAM, 7, 0, 0),
614 GATE(CLK_JPEG, "jpeg", "div_cam_blk_320", GATE_IP_CAM, 6, 0, 0),
615 GATE(CLK_M2MSCALER, "m2mscaler", "div_cam_blk_320",
616 GATE_IP_CAM, 2, 0, 0),
617 GATE(CLK_GSCALER1, "gscaler1", "div_cam_blk_320", GATE_IP_CAM, 1, 0, 0),
618 GATE(CLK_GSCALER0, "gscaler0", "div_cam_blk_320", GATE_IP_CAM, 0, 0, 0),
619
620 /* GATE_IP_MFC */
621 GATE(CLK_QEMFC, "qemfc", "div_aclk_200", GATE_IP_MFC, 5,
622 CLK_IGNORE_UNUSED, 0),
623 GATE(CLK_PPMUMFC_L, "ppmumfc_l", "div_aclk_200", GATE_IP_MFC, 3,
624 CLK_IGNORE_UNUSED, 0),
625 GATE(CLK_SMMUMFC_L, "smmumfc_l", "div_aclk_200", GATE_IP_MFC, 1, 0, 0),
626 GATE(CLK_MFC, "mfc", "div_aclk_200", GATE_IP_MFC, 0, 0, 0),
627
628 /* GATE_IP_G3D */
629 GATE(CLK_SMMUG3D, "smmug3d", "div_aclk_200", GATE_IP_G3D, 3, 0, 0),
630 GATE(CLK_QEG3D, "qeg3d", "div_aclk_200", GATE_IP_G3D, 2,
631 CLK_IGNORE_UNUSED, 0),
632 GATE(CLK_PPMUG3D, "ppmug3d", "div_aclk_200", GATE_IP_G3D, 1,
633 CLK_IGNORE_UNUSED, 0),
634 GATE(CLK_G3D, "g3d", "div_aclk_200", GATE_IP_G3D, 0, 0, 0),
635
636 /* GATE_IP_LCD */
637 GATE(CLK_QE_CH1_LCD, "qe_ch1_lcd", "div_aclk_160", GATE_IP_LCD, 7,
638 CLK_IGNORE_UNUSED, 0),
639 GATE(CLK_QE_CH0_LCD, "qe_ch0_lcd", "div_aclk_160", GATE_IP_LCD, 6,
640 CLK_IGNORE_UNUSED, 0),
641 GATE(CLK_PPMULCD0, "ppmulcd0", "div_aclk_160", GATE_IP_LCD, 5,
642 CLK_IGNORE_UNUSED, 0),
643 GATE(CLK_SMMUFIMD0, "smmufimd0", "div_aclk_160", GATE_IP_LCD, 4, 0, 0),
644 GATE(CLK_DSIM0, "dsim0", "div_aclk_160", GATE_IP_LCD, 3, 0, 0),
645 GATE(CLK_SMIES, "smies", "div_aclk_160", GATE_IP_LCD, 2, 0, 0),
646 GATE(CLK_FIMD0, "fimd0", "div_aclk_160", GATE_IP_LCD, 0, 0, 0),
647
648 /* GATE_IP_ISP */
649 GATE(CLK_CAM1, "cam1", "mout_aclk_266_sub", GATE_IP_ISP, 5, 0, 0),
650 GATE(CLK_UART_ISP_TOP, "uart_isp_top", "mout_aclk_266_sub",
651 GATE_IP_ISP, 3, 0, 0),
652 GATE(CLK_SPI1_ISP_TOP, "spi1_isp_top", "mout_aclk_266_sub",
653 GATE_IP_ISP, 2, 0, 0),
654 GATE(CLK_SPI0_ISP_TOP, "spi0_isp_top", "mout_aclk_266_sub",
655 GATE_IP_ISP, 1, 0, 0),
656
657 /* GATE_IP_FSYS */
658 GATE(CLK_TSADC, "tsadc", "div_aclk_200", GATE_IP_FSYS, 20, 0, 0),
659 GATE(CLK_PPMUFILE, "ppmufile", "div_aclk_200", GATE_IP_FSYS, 17,
660 CLK_IGNORE_UNUSED, 0),
661 GATE(CLK_USBOTG, "usbotg", "div_aclk_200", GATE_IP_FSYS, 13, 0, 0),
662 GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12, 0, 0),
663 GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0, 0),
664 GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0, 0),
665 GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0, 0),
666 GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0),
667 GATE(CLK_PDMA0, "pdma0", "div_aclk_200", GATE_IP_FSYS, 0, 0, 0),
668
669 /* GATE_IP_PERIL */
670 GATE(CLK_PWM, "pwm", "div_aclk_100", GATE_IP_PERIL, 24, 0, 0),
671 GATE(CLK_PCM, "pcm", "div_aclk_100", GATE_IP_PERIL, 23, 0, 0),
672 GATE(CLK_I2S, "i2s", "div_aclk_100", GATE_IP_PERIL, 21, 0, 0),
673 GATE(CLK_SPI1, "spi1", "div_aclk_100", GATE_IP_PERIL, 17, 0, 0),
674 GATE(CLK_SPI0, "spi0", "div_aclk_100", GATE_IP_PERIL, 16, 0, 0),
675 GATE(CLK_I2C7, "i2c7", "div_aclk_100", GATE_IP_PERIL, 13, 0, 0),
676 GATE(CLK_I2C6, "i2c6", "div_aclk_100", GATE_IP_PERIL, 12, 0, 0),
677 GATE(CLK_I2C5, "i2c5", "div_aclk_100", GATE_IP_PERIL, 11, 0, 0),
678 GATE(CLK_I2C4, "i2c4", "div_aclk_100", GATE_IP_PERIL, 10, 0, 0),
679 GATE(CLK_I2C3, "i2c3", "div_aclk_100", GATE_IP_PERIL, 9, 0, 0),
680 GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0),
681 GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0),
682 GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0),
683 GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0),
684 GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0),
685};
686
687/* APLL & MPLL & BPLL & UPLL */
688static struct samsung_pll_rate_table exynos3250_pll_rates[] = {
689 PLL_35XX_RATE(1200000000, 400, 4, 1),
690 PLL_35XX_RATE(1100000000, 275, 3, 1),
691 PLL_35XX_RATE(1066000000, 533, 6, 1),
692 PLL_35XX_RATE(1000000000, 250, 3, 1),
693 PLL_35XX_RATE( 960000000, 320, 4, 1),
694 PLL_35XX_RATE( 900000000, 300, 4, 1),
695 PLL_35XX_RATE( 850000000, 425, 6, 1),
696 PLL_35XX_RATE( 800000000, 200, 3, 1),
697 PLL_35XX_RATE( 700000000, 175, 3, 1),
698 PLL_35XX_RATE( 667000000, 667, 12, 1),
699 PLL_35XX_RATE( 600000000, 400, 4, 2),
700 PLL_35XX_RATE( 533000000, 533, 6, 2),
701 PLL_35XX_RATE( 520000000, 260, 3, 2),
702 PLL_35XX_RATE( 500000000, 250, 3, 2),
703 PLL_35XX_RATE( 400000000, 200, 3, 2),
704 PLL_35XX_RATE( 200000000, 200, 3, 3),
705 PLL_35XX_RATE( 100000000, 200, 3, 4),
706 { /* sentinel */ }
707};
708
709/* VPLL */
710static struct samsung_pll_rate_table exynos3250_vpll_rates[] = {
711 PLL_36XX_RATE(600000000, 100, 2, 1, 0),
712 PLL_36XX_RATE(533000000, 266, 3, 2, 32768),
713 PLL_36XX_RATE(519230987, 173, 2, 2, 5046),
714 PLL_36XX_RATE(500000000, 250, 3, 2, 0),
715 PLL_36XX_RATE(445500000, 148, 2, 2, 32768),
716 PLL_36XX_RATE(445055007, 148, 2, 2, 23047),
717 PLL_36XX_RATE(400000000, 200, 3, 2, 0),
718 PLL_36XX_RATE(371250000, 123, 2, 2, 49152),
719 PLL_36XX_RATE(370878997, 185, 3, 2, 28803),
720 PLL_36XX_RATE(340000000, 170, 3, 2, 0),
721 PLL_36XX_RATE(335000015, 111, 2, 2, 43691),
722 PLL_36XX_RATE(333000000, 111, 2, 2, 0),
723 PLL_36XX_RATE(330000000, 110, 2, 2, 0),
724 PLL_36XX_RATE(320000015, 106, 2, 2, 43691),
725 PLL_36XX_RATE(300000000, 100, 2, 2, 0),
726 PLL_36XX_RATE(275000000, 275, 3, 3, 0),
727 PLL_36XX_RATE(222750000, 148, 2, 3, 32768),
728 PLL_36XX_RATE(222528007, 148, 2, 3, 23069),
729 PLL_36XX_RATE(160000000, 160, 3, 3, 0),
730 PLL_36XX_RATE(148500000, 99, 2, 3, 0),
731 PLL_36XX_RATE(148352005, 98, 2, 3, 59070),
732 PLL_36XX_RATE(108000000, 144, 2, 4, 0),
733 PLL_36XX_RATE( 74250000, 99, 2, 4, 0),
734 PLL_36XX_RATE( 74176002, 98, 3, 4, 59070),
735 PLL_36XX_RATE( 54054000, 216, 3, 5, 14156),
736 PLL_36XX_RATE( 54000000, 144, 2, 5, 0),
737 { /* sentinel */ }
738};
739
740static struct samsung_pll_clock exynos3250_plls[nr_plls] __initdata = {
741 [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
742 APLL_LOCK, APLL_CON0, NULL),
743 [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
744 MPLL_LOCK, MPLL_CON0, NULL),
745 [vpll] = PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "fin_pll",
746 VPLL_LOCK, VPLL_CON0, NULL),
747 [upll] = PLL(pll_35xx, CLK_FOUT_UPLL, "fout_upll", "fin_pll",
748 UPLL_LOCK, UPLL_CON0, NULL),
749};
750
751static void __init exynos3250_cmu_init(struct device_node *np)
752{
753 struct samsung_clk_provider *ctx;
754
755 reg_base = of_iomap(np, 0);
756 if (!reg_base)
757 panic("%s: failed to map registers\n", __func__);
758
759 ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
760 if (!ctx)
761 panic("%s: unable to allocate context.\n", __func__);
762
763 samsung_clk_register_fixed_factor(ctx, fixed_factor_clks,
764 ARRAY_SIZE(fixed_factor_clks));
765
766 exynos3250_plls[apll].rate_table = exynos3250_pll_rates;
767 exynos3250_plls[mpll].rate_table = exynos3250_pll_rates;
768 exynos3250_plls[vpll].rate_table = exynos3250_vpll_rates;
769 exynos3250_plls[upll].rate_table = exynos3250_pll_rates;
770
771 samsung_clk_register_pll(ctx, exynos3250_plls,
772 ARRAY_SIZE(exynos3250_plls), reg_base);
773
774 samsung_clk_register_mux(ctx, mux_clks, ARRAY_SIZE(mux_clks));
775 samsung_clk_register_div(ctx, div_clks, ARRAY_SIZE(div_clks));
776 samsung_clk_register_gate(ctx, gate_clks, ARRAY_SIZE(gate_clks));
777
778 exynos3250_clk_sleep_init();
779}
780CLK_OF_DECLARE(exynos3250_cmu, "samsung,exynos3250-cmu", exynos3250_cmu_init);
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index b4f967210175..c4df294bb7fb 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -428,7 +428,7 @@ static struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata
428/* fixed rate clocks generated inside the soc */ 428/* fixed rate clocks generated inside the soc */
429static struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = { 429static struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = {
430 FRATE(0, "sclk_hdmi24m", NULL, CLK_IS_ROOT, 24000000), 430 FRATE(0, "sclk_hdmi24m", NULL, CLK_IS_ROOT, 24000000),
431 FRATE(0, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000), 431 FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000),
432 FRATE(0, "sclk_usbphy0", NULL, CLK_IS_ROOT, 48000000), 432 FRATE(0, "sclk_usbphy0", NULL, CLK_IS_ROOT, 48000000),
433}; 433};
434 434
@@ -903,7 +903,7 @@ static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
903 GATE(CLK_AUDSS, "audss", "sclk_epll", E4X12_GATE_IP_MAUDIO, 0, 0, 0), 903 GATE(CLK_AUDSS, "audss", "sclk_epll", E4X12_GATE_IP_MAUDIO, 0, 0, 0),
904 GATE(CLK_MDNIE0, "mdnie0", "aclk160", GATE_IP_LCD0, 2, 0, 0), 904 GATE(CLK_MDNIE0, "mdnie0", "aclk160", GATE_IP_LCD0, 2, 0, 0),
905 GATE(CLK_ROTATOR, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0), 905 GATE(CLK_ROTATOR, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0),
906 GATE(CLK_MDMA2, "mdma2", "aclk200", E4X12_GATE_IP_IMAGE, 2, 0, 0), 906 GATE(CLK_MDMA, "mdma", "aclk200", E4X12_GATE_IP_IMAGE, 2, 0, 0),
907 GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0, 907 GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0,
908 0), 908 0),
909 GATE(CLK_MIPI_HSI, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0), 909 GATE(CLK_MIPI_HSI, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0),
@@ -1043,7 +1043,7 @@ static unsigned long exynos4_get_xom(void)
1043 return xom; 1043 return xom;
1044} 1044}
1045 1045
1046static void __init exynos4_clk_register_finpll(void) 1046static void __init exynos4_clk_register_finpll(struct samsung_clk_provider *ctx)
1047{ 1047{
1048 struct samsung_fixed_rate_clock fclk; 1048 struct samsung_fixed_rate_clock fclk;
1049 struct clk *clk; 1049 struct clk *clk;
@@ -1066,7 +1066,7 @@ static void __init exynos4_clk_register_finpll(void)
1066 fclk.parent_name = NULL; 1066 fclk.parent_name = NULL;
1067 fclk.flags = CLK_IS_ROOT; 1067 fclk.flags = CLK_IS_ROOT;
1068 fclk.fixed_rate = finpll_f; 1068 fclk.fixed_rate = finpll_f;
1069 samsung_clk_register_fixed_rate(&fclk, 1); 1069 samsung_clk_register_fixed_rate(ctx, &fclk, 1);
1070 1070
1071} 1071}
1072 1072
@@ -1176,22 +1176,25 @@ static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = {
1176static void __init exynos4_clk_init(struct device_node *np, 1176static void __init exynos4_clk_init(struct device_node *np,
1177 enum exynos4_soc soc) 1177 enum exynos4_soc soc)
1178{ 1178{
1179 struct samsung_clk_provider *ctx;
1179 exynos4_soc = soc; 1180 exynos4_soc = soc;
1180 1181
1181 reg_base = of_iomap(np, 0); 1182 reg_base = of_iomap(np, 0);
1182 if (!reg_base) 1183 if (!reg_base)
1183 panic("%s: failed to map registers\n", __func__); 1184 panic("%s: failed to map registers\n", __func__);
1184 1185
1185 samsung_clk_init(np, reg_base, CLK_NR_CLKS); 1186 ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
1187 if (!ctx)
1188 panic("%s: unable to allocate context.\n", __func__);
1186 1189
1187 samsung_clk_of_register_fixed_ext(exynos4_fixed_rate_ext_clks, 1190 samsung_clk_of_register_fixed_ext(ctx, exynos4_fixed_rate_ext_clks,
1188 ARRAY_SIZE(exynos4_fixed_rate_ext_clks), 1191 ARRAY_SIZE(exynos4_fixed_rate_ext_clks),
1189 ext_clk_match); 1192 ext_clk_match);
1190 1193
1191 exynos4_clk_register_finpll(); 1194 exynos4_clk_register_finpll(ctx);
1192 1195
1193 if (exynos4_soc == EXYNOS4210) { 1196 if (exynos4_soc == EXYNOS4210) {
1194 samsung_clk_register_mux(exynos4210_mux_early, 1197 samsung_clk_register_mux(ctx, exynos4210_mux_early,
1195 ARRAY_SIZE(exynos4210_mux_early)); 1198 ARRAY_SIZE(exynos4210_mux_early));
1196 1199
1197 if (_get_rate("fin_pll") == 24000000) { 1200 if (_get_rate("fin_pll") == 24000000) {
@@ -1205,7 +1208,7 @@ static void __init exynos4_clk_init(struct device_node *np,
1205 exynos4210_plls[vpll].rate_table = 1208 exynos4210_plls[vpll].rate_table =
1206 exynos4210_vpll_rates; 1209 exynos4210_vpll_rates;
1207 1210
1208 samsung_clk_register_pll(exynos4210_plls, 1211 samsung_clk_register_pll(ctx, exynos4210_plls,
1209 ARRAY_SIZE(exynos4210_plls), reg_base); 1212 ARRAY_SIZE(exynos4210_plls), reg_base);
1210 } else { 1213 } else {
1211 if (_get_rate("fin_pll") == 24000000) { 1214 if (_get_rate("fin_pll") == 24000000) {
@@ -1217,42 +1220,42 @@ static void __init exynos4_clk_init(struct device_node *np,
1217 exynos4x12_vpll_rates; 1220 exynos4x12_vpll_rates;
1218 } 1221 }
1219 1222
1220 samsung_clk_register_pll(exynos4x12_plls, 1223 samsung_clk_register_pll(ctx, exynos4x12_plls,
1221 ARRAY_SIZE(exynos4x12_plls), reg_base); 1224 ARRAY_SIZE(exynos4x12_plls), reg_base);
1222 } 1225 }
1223 1226
1224 samsung_clk_register_fixed_rate(exynos4_fixed_rate_clks, 1227 samsung_clk_register_fixed_rate(ctx, exynos4_fixed_rate_clks,
1225 ARRAY_SIZE(exynos4_fixed_rate_clks)); 1228 ARRAY_SIZE(exynos4_fixed_rate_clks));
1226 samsung_clk_register_mux(exynos4_mux_clks, 1229 samsung_clk_register_mux(ctx, exynos4_mux_clks,
1227 ARRAY_SIZE(exynos4_mux_clks)); 1230 ARRAY_SIZE(exynos4_mux_clks));
1228 samsung_clk_register_div(exynos4_div_clks, 1231 samsung_clk_register_div(ctx, exynos4_div_clks,
1229 ARRAY_SIZE(exynos4_div_clks)); 1232 ARRAY_SIZE(exynos4_div_clks));
1230 samsung_clk_register_gate(exynos4_gate_clks, 1233 samsung_clk_register_gate(ctx, exynos4_gate_clks,
1231 ARRAY_SIZE(exynos4_gate_clks)); 1234 ARRAY_SIZE(exynos4_gate_clks));
1232 1235
1233 if (exynos4_soc == EXYNOS4210) { 1236 if (exynos4_soc == EXYNOS4210) {
1234 samsung_clk_register_fixed_rate(exynos4210_fixed_rate_clks, 1237 samsung_clk_register_fixed_rate(ctx, exynos4210_fixed_rate_clks,
1235 ARRAY_SIZE(exynos4210_fixed_rate_clks)); 1238 ARRAY_SIZE(exynos4210_fixed_rate_clks));
1236 samsung_clk_register_mux(exynos4210_mux_clks, 1239 samsung_clk_register_mux(ctx, exynos4210_mux_clks,
1237 ARRAY_SIZE(exynos4210_mux_clks)); 1240 ARRAY_SIZE(exynos4210_mux_clks));
1238 samsung_clk_register_div(exynos4210_div_clks, 1241 samsung_clk_register_div(ctx, exynos4210_div_clks,
1239 ARRAY_SIZE(exynos4210_div_clks)); 1242 ARRAY_SIZE(exynos4210_div_clks));
1240 samsung_clk_register_gate(exynos4210_gate_clks, 1243 samsung_clk_register_gate(ctx, exynos4210_gate_clks,
1241 ARRAY_SIZE(exynos4210_gate_clks)); 1244 ARRAY_SIZE(exynos4210_gate_clks));
1242 samsung_clk_register_alias(exynos4210_aliases, 1245 samsung_clk_register_alias(ctx, exynos4210_aliases,
1243 ARRAY_SIZE(exynos4210_aliases)); 1246 ARRAY_SIZE(exynos4210_aliases));
1244 } else { 1247 } else {
1245 samsung_clk_register_mux(exynos4x12_mux_clks, 1248 samsung_clk_register_mux(ctx, exynos4x12_mux_clks,
1246 ARRAY_SIZE(exynos4x12_mux_clks)); 1249 ARRAY_SIZE(exynos4x12_mux_clks));
1247 samsung_clk_register_div(exynos4x12_div_clks, 1250 samsung_clk_register_div(ctx, exynos4x12_div_clks,
1248 ARRAY_SIZE(exynos4x12_div_clks)); 1251 ARRAY_SIZE(exynos4x12_div_clks));
1249 samsung_clk_register_gate(exynos4x12_gate_clks, 1252 samsung_clk_register_gate(ctx, exynos4x12_gate_clks,
1250 ARRAY_SIZE(exynos4x12_gate_clks)); 1253 ARRAY_SIZE(exynos4x12_gate_clks));
1251 samsung_clk_register_alias(exynos4x12_aliases, 1254 samsung_clk_register_alias(ctx, exynos4x12_aliases,
1252 ARRAY_SIZE(exynos4x12_aliases)); 1255 ARRAY_SIZE(exynos4x12_aliases));
1253 } 1256 }
1254 1257
1255 samsung_clk_register_alias(exynos4_aliases, 1258 samsung_clk_register_alias(ctx, exynos4_aliases,
1256 ARRAY_SIZE(exynos4_aliases)); 1259 ARRAY_SIZE(exynos4_aliases));
1257 1260
1258 exynos4_clk_sleep_init(); 1261 exynos4_clk_sleep_init();
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index e7ee4420da81..870e18b9a687 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -28,6 +28,8 @@
28#define MPLL_CON0 0x4100 28#define MPLL_CON0 0x4100
29#define SRC_CORE1 0x4204 29#define SRC_CORE1 0x4204
30#define GATE_IP_ACP 0x8800 30#define GATE_IP_ACP 0x8800
31#define GATE_IP_ISP0 0xc800
32#define GATE_IP_ISP1 0xc804
31#define CPLL_LOCK 0x10020 33#define CPLL_LOCK 0x10020
32#define EPLL_LOCK 0x10030 34#define EPLL_LOCK 0x10030
33#define VPLL_LOCK 0x10040 35#define VPLL_LOCK 0x10040
@@ -37,6 +39,7 @@
37#define VPLL_CON0 0x10140 39#define VPLL_CON0 0x10140
38#define GPLL_CON0 0x10150 40#define GPLL_CON0 0x10150
39#define SRC_TOP0 0x10210 41#define SRC_TOP0 0x10210
42#define SRC_TOP1 0x10214
40#define SRC_TOP2 0x10218 43#define SRC_TOP2 0x10218
41#define SRC_TOP3 0x1021c 44#define SRC_TOP3 0x1021c
42#define SRC_GSCL 0x10220 45#define SRC_GSCL 0x10220
@@ -71,6 +74,7 @@
71#define GATE_IP_GSCL 0x10920 74#define GATE_IP_GSCL 0x10920
72#define GATE_IP_DISP1 0x10928 75#define GATE_IP_DISP1 0x10928
73#define GATE_IP_MFC 0x1092c 76#define GATE_IP_MFC 0x1092c
77#define GATE_IP_G3D 0x10930
74#define GATE_IP_GEN 0x10934 78#define GATE_IP_GEN 0x10934
75#define GATE_IP_FSYS 0x10944 79#define GATE_IP_FSYS 0x10944
76#define GATE_IP_PERIC 0x10950 80#define GATE_IP_PERIC 0x10950
@@ -100,6 +104,7 @@ static unsigned long exynos5250_clk_regs[] __initdata = {
100 DIV_CPU0, 104 DIV_CPU0,
101 SRC_CORE1, 105 SRC_CORE1,
102 SRC_TOP0, 106 SRC_TOP0,
107 SRC_TOP1,
103 SRC_TOP2, 108 SRC_TOP2,
104 SRC_TOP3, 109 SRC_TOP3,
105 SRC_GSCL, 110 SRC_GSCL,
@@ -133,6 +138,7 @@ static unsigned long exynos5250_clk_regs[] __initdata = {
133 DIV_PERIC5, 138 DIV_PERIC5,
134 GATE_IP_GSCL, 139 GATE_IP_GSCL,
135 GATE_IP_MFC, 140 GATE_IP_MFC,
141 GATE_IP_G3D,
136 GATE_IP_GEN, 142 GATE_IP_GEN,
137 GATE_IP_FSYS, 143 GATE_IP_FSYS,
138 GATE_IP_PERIC, 144 GATE_IP_PERIC,
@@ -141,6 +147,8 @@ static unsigned long exynos5250_clk_regs[] __initdata = {
141 PLL_DIV2_SEL, 147 PLL_DIV2_SEL,
142 GATE_IP_DISP1, 148 GATE_IP_DISP1,
143 GATE_IP_ACP, 149 GATE_IP_ACP,
150 GATE_IP_ISP0,
151 GATE_IP_ISP1,
144}; 152};
145 153
146static int exynos5250_clk_suspend(void) 154static int exynos5250_clk_suspend(void)
@@ -189,13 +197,16 @@ PNAME(mout_vpllsrc_p) = { "fin_pll", "sclk_hdmi27m" };
189PNAME(mout_vpll_p) = { "mout_vpllsrc", "fout_vpll" }; 197PNAME(mout_vpll_p) = { "mout_vpllsrc", "fout_vpll" };
190PNAME(mout_cpll_p) = { "fin_pll", "fout_cpll" }; 198PNAME(mout_cpll_p) = { "fin_pll", "fout_cpll" };
191PNAME(mout_epll_p) = { "fin_pll", "fout_epll" }; 199PNAME(mout_epll_p) = { "fin_pll", "fout_epll" };
200PNAME(mout_gpll_p) = { "fin_pll", "fout_gpll" };
192PNAME(mout_mpll_user_p) = { "fin_pll", "mout_mpll" }; 201PNAME(mout_mpll_user_p) = { "fin_pll", "mout_mpll" };
193PNAME(mout_bpll_user_p) = { "fin_pll", "mout_bpll" }; 202PNAME(mout_bpll_user_p) = { "fin_pll", "mout_bpll" };
194PNAME(mout_aclk166_p) = { "mout_cpll", "mout_mpll_user" }; 203PNAME(mout_aclk166_p) = { "mout_cpll", "mout_mpll_user" };
195PNAME(mout_aclk200_p) = { "mout_mpll_user", "mout_bpll_user" }; 204PNAME(mout_aclk200_p) = { "mout_mpll_user", "mout_bpll_user" };
205PNAME(mout_aclk400_p) = { "mout_aclk400_g3d_mid", "mout_gpll" };
196PNAME(mout_aclk200_sub_p) = { "fin_pll", "div_aclk200" }; 206PNAME(mout_aclk200_sub_p) = { "fin_pll", "div_aclk200" };
197PNAME(mout_aclk266_sub_p) = { "fin_pll", "div_aclk266" }; 207PNAME(mout_aclk266_sub_p) = { "fin_pll", "div_aclk266" };
198PNAME(mout_aclk333_sub_p) = { "fin_pll", "div_aclk333" }; 208PNAME(mout_aclk333_sub_p) = { "fin_pll", "div_aclk333" };
209PNAME(mout_aclk400_isp_sub_p) = { "fin_pll", "div_aclk400_isp" };
199PNAME(mout_hdmi_p) = { "div_hdmi_pixel", "sclk_hdmiphy" }; 210PNAME(mout_hdmi_p) = { "div_hdmi_pixel", "sclk_hdmiphy" };
200PNAME(mout_usb3_p) = { "mout_mpll_user", "mout_cpll" }; 211PNAME(mout_usb3_p) = { "mout_mpll_user", "mout_cpll" };
201PNAME(mout_group1_p) = { "fin_pll", "fin_pll", "sclk_hdmi27m", 212PNAME(mout_group1_p) = { "fin_pll", "fin_pll", "sclk_hdmi27m",
@@ -273,15 +284,23 @@ static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
273 MUX(0, "mout_aclk166", mout_aclk166_p, SRC_TOP0, 8, 1), 284 MUX(0, "mout_aclk166", mout_aclk166_p, SRC_TOP0, 8, 1),
274 MUX(0, "mout_aclk200", mout_aclk200_p, SRC_TOP0, 12, 1), 285 MUX(0, "mout_aclk200", mout_aclk200_p, SRC_TOP0, 12, 1),
275 MUX(0, "mout_aclk333", mout_aclk166_p, SRC_TOP0, 16, 1), 286 MUX(0, "mout_aclk333", mout_aclk166_p, SRC_TOP0, 16, 1),
287 MUX(0, "mout_aclk400_g3d_mid", mout_aclk200_p, SRC_TOP0, 20, 1),
288
289 MUX(0, "mout_aclk400_isp", mout_aclk200_p, SRC_TOP1, 24, 1),
290 MUX(0, "mout_aclk400_g3d", mout_aclk400_p, SRC_TOP1, 28, 1),
276 291
277 MUX(0, "mout_cpll", mout_cpll_p, SRC_TOP2, 8, 1), 292 MUX(0, "mout_cpll", mout_cpll_p, SRC_TOP2, 8, 1),
278 MUX(0, "mout_epll", mout_epll_p, SRC_TOP2, 12, 1), 293 MUX(0, "mout_epll", mout_epll_p, SRC_TOP2, 12, 1),
279 MUX(0, "mout_vpll", mout_vpll_p, SRC_TOP2, 16, 1), 294 MUX(0, "mout_vpll", mout_vpll_p, SRC_TOP2, 16, 1),
280 MUX(0, "mout_mpll_user", mout_mpll_user_p, SRC_TOP2, 20, 1), 295 MUX(0, "mout_mpll_user", mout_mpll_user_p, SRC_TOP2, 20, 1),
281 MUX(0, "mout_bpll_user", mout_bpll_user_p, SRC_TOP2, 24, 1), 296 MUX(0, "mout_bpll_user", mout_bpll_user_p, SRC_TOP2, 24, 1),
297 MUX(CLK_MOUT_GPLL, "mout_gpll", mout_gpll_p, SRC_TOP2, 28, 1),
282 298
283 MUX(0, "mout_aclk200_disp1_sub", mout_aclk200_sub_p, SRC_TOP3, 4, 1), 299 MUX(0, "mout_aclk200_disp1_sub", mout_aclk200_sub_p, SRC_TOP3, 4, 1),
284 MUX(0, "mout_aclk266_gscl_sub", mout_aclk266_sub_p, SRC_TOP3, 8, 1), 300 MUX(0, "mout_aclk266_gscl_sub", mout_aclk266_sub_p, SRC_TOP3, 8, 1),
301 MUX(0, "mout_aclk_266_isp_sub", mout_aclk266_sub_p, SRC_TOP3, 16, 1),
302 MUX(0, "mout_aclk_400_isp_sub", mout_aclk400_isp_sub_p,
303 SRC_TOP3, 20, 1),
285 MUX(0, "mout_aclk333_sub", mout_aclk333_sub_p, SRC_TOP3, 24, 1), 304 MUX(0, "mout_aclk333_sub", mout_aclk333_sub_p, SRC_TOP3, 24, 1),
286 305
287 MUX(0, "mout_cam_bayer", mout_group1_p, SRC_GSCL, 12, 4), 306 MUX(0, "mout_cam_bayer", mout_group1_p, SRC_GSCL, 12, 4),
@@ -351,7 +370,10 @@ static struct samsung_div_clock exynos5250_div_clks[] __initdata = {
351 DIV(0, "div_aclk200", "mout_aclk200", DIV_TOP0, 12, 3), 370 DIV(0, "div_aclk200", "mout_aclk200", DIV_TOP0, 12, 3),
352 DIV(0, "div_aclk266", "mout_mpll_user", DIV_TOP0, 16, 3), 371 DIV(0, "div_aclk266", "mout_mpll_user", DIV_TOP0, 16, 3),
353 DIV(0, "div_aclk333", "mout_aclk333", DIV_TOP0, 20, 3), 372 DIV(0, "div_aclk333", "mout_aclk333", DIV_TOP0, 20, 3),
373 DIV(0, "div_aclk400_g3d", "mout_aclk400_g3d", DIV_TOP0,
374 24, 3),
354 375
376 DIV(0, "div_aclk400_isp", "mout_aclk400_isp", DIV_TOP1, 20, 3),
355 DIV(0, "div_aclk66_pre", "mout_mpll_user", DIV_TOP1, 24, 3), 377 DIV(0, "div_aclk66_pre", "mout_mpll_user", DIV_TOP1, 24, 3),
356 378
357 DIV(0, "div_cam_bayer", "mout_cam_bayer", DIV_GSCL, 12, 4), 379 DIV(0, "div_cam_bayer", "mout_cam_bayer", DIV_GSCL, 12, 4),
@@ -428,6 +450,7 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
428 * CMU_ACP 450 * CMU_ACP
429 */ 451 */
430 GATE(CLK_MDMA0, "mdma0", "div_aclk266", GATE_IP_ACP, 1, 0, 0), 452 GATE(CLK_MDMA0, "mdma0", "div_aclk266", GATE_IP_ACP, 1, 0, 0),
453 GATE(CLK_SSS, "sss", "div_aclk266", GATE_IP_ACP, 2, 0, 0),
431 GATE(CLK_G2D, "g2d", "div_aclk200", GATE_IP_ACP, 3, 0, 0), 454 GATE(CLK_G2D, "g2d", "div_aclk200", GATE_IP_ACP, 3, 0, 0),
432 GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "div_aclk266", GATE_IP_ACP, 5, 0, 0), 455 GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "div_aclk266", GATE_IP_ACP, 5, 0, 0),
433 456
@@ -533,7 +556,8 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
533 0), 556 0),
534 GATE(CLK_SMMU_MFCL, "smmu_mfcl", "mout_aclk333_sub", GATE_IP_MFC, 2, 0, 557 GATE(CLK_SMMU_MFCL, "smmu_mfcl", "mout_aclk333_sub", GATE_IP_MFC, 2, 0,
535 0), 558 0),
536 559 GATE(CLK_G3D, "g3d", "div_aclk400_g3d", GATE_IP_G3D, 0,
560 CLK_SET_RATE_PARENT, 0),
537 GATE(CLK_ROTATOR, "rotator", "div_aclk266", GATE_IP_GEN, 1, 0, 0), 561 GATE(CLK_ROTATOR, "rotator", "div_aclk266", GATE_IP_GEN, 1, 0, 0),
538 GATE(CLK_JPEG, "jpeg", "div_aclk166", GATE_IP_GEN, 2, 0, 0), 562 GATE(CLK_JPEG, "jpeg", "div_aclk166", GATE_IP_GEN, 2, 0, 0),
539 GATE(CLK_MDMA1, "mdma1", "div_aclk266", GATE_IP_GEN, 4, 0, 0), 563 GATE(CLK_MDMA1, "mdma1", "div_aclk266", GATE_IP_GEN, 4, 0, 0),
@@ -615,6 +639,31 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
615 GATE(CLK_WDT, "wdt", "div_aclk66", GATE_IP_PERIS, 19, 0, 0), 639 GATE(CLK_WDT, "wdt", "div_aclk66", GATE_IP_PERIS, 19, 0, 0),
616 GATE(CLK_RTC, "rtc", "div_aclk66", GATE_IP_PERIS, 20, 0, 0), 640 GATE(CLK_RTC, "rtc", "div_aclk66", GATE_IP_PERIS, 20, 0, 0),
617 GATE(CLK_TMU, "tmu", "div_aclk66", GATE_IP_PERIS, 21, 0, 0), 641 GATE(CLK_TMU, "tmu", "div_aclk66", GATE_IP_PERIS, 21, 0, 0),
642 GATE(CLK_SMMU_TV, "smmu_tv", "mout_aclk200_disp1_sub",
643 GATE_IP_DISP1, 2, 0, 0),
644 GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "mout_aclk200_disp1_sub",
645 GATE_IP_DISP1, 8, 0, 0),
646 GATE(CLK_SMMU_2D, "smmu_2d", "div_aclk200", GATE_IP_ACP, 7, 0, 0),
647 GATE(CLK_SMMU_FIMC_ISP, "smmu_fimc_isp", "mout_aclk_266_isp_sub",
648 GATE_IP_ISP0, 8, 0, 0),
649 GATE(CLK_SMMU_FIMC_DRC, "smmu_fimc_drc", "mout_aclk_266_isp_sub",
650 GATE_IP_ISP0, 9, 0, 0),
651 GATE(CLK_SMMU_FIMC_FD, "smmu_fimc_fd", "mout_aclk_266_isp_sub",
652 GATE_IP_ISP0, 10, 0, 0),
653 GATE(CLK_SMMU_FIMC_SCC, "smmu_fimc_scc", "mout_aclk_266_isp_sub",
654 GATE_IP_ISP0, 11, 0, 0),
655 GATE(CLK_SMMU_FIMC_SCP, "smmu_fimc_scp", "mout_aclk_266_isp_sub",
656 GATE_IP_ISP0, 12, 0, 0),
657 GATE(CLK_SMMU_FIMC_MCU, "smmu_fimc_mcu", "mout_aclk_400_isp_sub",
658 GATE_IP_ISP0, 13, 0, 0),
659 GATE(CLK_SMMU_FIMC_ODC, "smmu_fimc_odc", "mout_aclk_266_isp_sub",
660 GATE_IP_ISP1, 4, 0, 0),
661 GATE(CLK_SMMU_FIMC_DIS0, "smmu_fimc_dis0", "mout_aclk_266_isp_sub",
662 GATE_IP_ISP1, 5, 0, 0),
663 GATE(CLK_SMMU_FIMC_DIS1, "smmu_fimc_dis1", "mout_aclk_266_isp_sub",
664 GATE_IP_ISP1, 6, 0, 0),
665 GATE(CLK_SMMU_FIMC_3DNR, "smmu_fimc_3dnr", "mout_aclk_266_isp_sub",
666 GATE_IP_ISP1, 7, 0, 0),
618}; 667};
619 668
620static struct samsung_pll_rate_table vpll_24mhz_tbl[] __initdata = { 669static struct samsung_pll_rate_table vpll_24mhz_tbl[] __initdata = {
@@ -686,6 +735,8 @@ static struct of_device_id ext_clk_match[] __initdata = {
686/* register exynox5250 clocks */ 735/* register exynox5250 clocks */
687static void __init exynos5250_clk_init(struct device_node *np) 736static void __init exynos5250_clk_init(struct device_node *np)
688{ 737{
738 struct samsung_clk_provider *ctx;
739
689 if (np) { 740 if (np) {
690 reg_base = of_iomap(np, 0); 741 reg_base = of_iomap(np, 0);
691 if (!reg_base) 742 if (!reg_base)
@@ -694,11 +745,13 @@ static void __init exynos5250_clk_init(struct device_node *np)
694 panic("%s: unable to determine soc\n", __func__); 745 panic("%s: unable to determine soc\n", __func__);
695 } 746 }
696 747
697 samsung_clk_init(np, reg_base, CLK_NR_CLKS); 748 ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
698 samsung_clk_of_register_fixed_ext(exynos5250_fixed_rate_ext_clks, 749 if (!ctx)
750 panic("%s: unable to allocate context.\n", __func__);
751 samsung_clk_of_register_fixed_ext(ctx, exynos5250_fixed_rate_ext_clks,
699 ARRAY_SIZE(exynos5250_fixed_rate_ext_clks), 752 ARRAY_SIZE(exynos5250_fixed_rate_ext_clks),
700 ext_clk_match); 753 ext_clk_match);
701 samsung_clk_register_mux(exynos5250_pll_pmux_clks, 754 samsung_clk_register_mux(ctx, exynos5250_pll_pmux_clks,
702 ARRAY_SIZE(exynos5250_pll_pmux_clks)); 755 ARRAY_SIZE(exynos5250_pll_pmux_clks));
703 756
704 if (_get_rate("fin_pll") == 24 * MHZ) { 757 if (_get_rate("fin_pll") == 24 * MHZ) {
@@ -709,17 +762,18 @@ static void __init exynos5250_clk_init(struct device_node *np)
709 if (_get_rate("mout_vpllsrc") == 24 * MHZ) 762 if (_get_rate("mout_vpllsrc") == 24 * MHZ)
710 exynos5250_plls[vpll].rate_table = vpll_24mhz_tbl; 763 exynos5250_plls[vpll].rate_table = vpll_24mhz_tbl;
711 764
712 samsung_clk_register_pll(exynos5250_plls, ARRAY_SIZE(exynos5250_plls), 765 samsung_clk_register_pll(ctx, exynos5250_plls,
713 reg_base); 766 ARRAY_SIZE(exynos5250_plls),
714 samsung_clk_register_fixed_rate(exynos5250_fixed_rate_clks, 767 reg_base);
768 samsung_clk_register_fixed_rate(ctx, exynos5250_fixed_rate_clks,
715 ARRAY_SIZE(exynos5250_fixed_rate_clks)); 769 ARRAY_SIZE(exynos5250_fixed_rate_clks));
716 samsung_clk_register_fixed_factor(exynos5250_fixed_factor_clks, 770 samsung_clk_register_fixed_factor(ctx, exynos5250_fixed_factor_clks,
717 ARRAY_SIZE(exynos5250_fixed_factor_clks)); 771 ARRAY_SIZE(exynos5250_fixed_factor_clks));
718 samsung_clk_register_mux(exynos5250_mux_clks, 772 samsung_clk_register_mux(ctx, exynos5250_mux_clks,
719 ARRAY_SIZE(exynos5250_mux_clks)); 773 ARRAY_SIZE(exynos5250_mux_clks));
720 samsung_clk_register_div(exynos5250_div_clks, 774 samsung_clk_register_div(ctx, exynos5250_div_clks,
721 ARRAY_SIZE(exynos5250_div_clks)); 775 ARRAY_SIZE(exynos5250_div_clks));
722 samsung_clk_register_gate(exynos5250_gate_clks, 776 samsung_clk_register_gate(ctx, exynos5250_gate_clks,
723 ARRAY_SIZE(exynos5250_gate_clks)); 777 ARRAY_SIZE(exynos5250_gate_clks));
724 778
725 exynos5250_clk_sleep_init(); 779 exynos5250_clk_sleep_init();
diff --git a/drivers/clk/samsung/clk-exynos5260.c b/drivers/clk/samsung/clk-exynos5260.c
new file mode 100644
index 000000000000..64596ba58df1
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos5260.c
@@ -0,0 +1,1980 @@
1/*
2 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
3 * Author: Rahul Sharma <rahul.sharma@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * Common Clock Framework support for Exynos5260 SoC.
10 */
11
12#include <linux/clk.h>
13#include <linux/clkdev.h>
14#include <linux/clk-provider.h>
15#include <linux/of.h>
16#include <linux/of_address.h>
17#include <linux/syscore_ops.h>
18
19#include "clk-exynos5260.h"
20#include "clk.h"
21#include "clk-pll.h"
22
23#include <dt-bindings/clock/exynos5260-clk.h>
24
25static LIST_HEAD(clock_reg_cache_list);
26
27struct exynos5260_clock_reg_cache {
28 struct list_head node;
29 void __iomem *reg_base;
30 struct samsung_clk_reg_dump *rdump;
31 unsigned int rd_num;
32};
33
34struct exynos5260_cmu_info {
35 /* list of pll clocks and respective count */
36 struct samsung_pll_clock *pll_clks;
37 unsigned int nr_pll_clks;
38 /* list of mux clocks and respective count */
39 struct samsung_mux_clock *mux_clks;
40 unsigned int nr_mux_clks;
41 /* list of div clocks and respective count */
42 struct samsung_div_clock *div_clks;
43 unsigned int nr_div_clks;
44 /* list of gate clocks and respective count */
45 struct samsung_gate_clock *gate_clks;
46 unsigned int nr_gate_clks;
47 /* list of fixed clocks and respective count */
48 struct samsung_fixed_rate_clock *fixed_clks;
49 unsigned int nr_fixed_clks;
50 /* total number of clocks with IDs assigned*/
51 unsigned int nr_clk_ids;
52
53 /* list and number of clocks registers */
54 unsigned long *clk_regs;
55 unsigned int nr_clk_regs;
56};
57
58/*
59 * Applicable for all 2550 Type PLLS for Exynos5260, listed below
60 * DISP_PLL, EGL_PLL, KFC_PLL, MEM_PLL, BUS_PLL, MEDIA_PLL, G3D_PLL.
61 */
62static struct samsung_pll_rate_table pll2550_24mhz_tbl[] __initdata = {
63 PLL_35XX_RATE(1700000000, 425, 6, 0),
64 PLL_35XX_RATE(1600000000, 200, 3, 0),
65 PLL_35XX_RATE(1500000000, 250, 4, 0),
66 PLL_35XX_RATE(1400000000, 175, 3, 0),
67 PLL_35XX_RATE(1300000000, 325, 6, 0),
68 PLL_35XX_RATE(1200000000, 400, 4, 1),
69 PLL_35XX_RATE(1100000000, 275, 3, 1),
70 PLL_35XX_RATE(1000000000, 250, 3, 1),
71 PLL_35XX_RATE(933000000, 311, 4, 1),
72 PLL_35XX_RATE(900000000, 300, 4, 1),
73 PLL_35XX_RATE(800000000, 200, 3, 1),
74 PLL_35XX_RATE(733000000, 733, 12, 1),
75 PLL_35XX_RATE(700000000, 175, 3, 1),
76 PLL_35XX_RATE(667000000, 667, 12, 1),
77 PLL_35XX_RATE(633000000, 211, 4, 1),
78 PLL_35XX_RATE(620000000, 310, 3, 2),
79 PLL_35XX_RATE(600000000, 400, 4, 2),
80 PLL_35XX_RATE(543000000, 362, 4, 2),
81 PLL_35XX_RATE(533000000, 533, 6, 2),
82 PLL_35XX_RATE(500000000, 250, 3, 2),
83 PLL_35XX_RATE(450000000, 300, 4, 2),
84 PLL_35XX_RATE(400000000, 200, 3, 2),
85 PLL_35XX_RATE(350000000, 175, 3, 2),
86 PLL_35XX_RATE(300000000, 400, 4, 3),
87 PLL_35XX_RATE(266000000, 266, 3, 3),
88 PLL_35XX_RATE(200000000, 200, 3, 3),
89 PLL_35XX_RATE(160000000, 160, 3, 3),
90};
91
92/*
93 * Applicable for 2650 Type PLL for AUD_PLL.
94 */
95static struct samsung_pll_rate_table pll2650_24mhz_tbl[] __initdata = {
96 PLL_36XX_RATE(1600000000, 200, 3, 0, 0),
97 PLL_36XX_RATE(1200000000, 100, 2, 0, 0),
98 PLL_36XX_RATE(1000000000, 250, 3, 1, 0),
99 PLL_36XX_RATE(800000000, 200, 3, 1, 0),
100 PLL_36XX_RATE(600000000, 100, 2, 1, 0),
101 PLL_36XX_RATE(532000000, 266, 3, 2, 0),
102 PLL_36XX_RATE(480000000, 160, 2, 2, 0),
103 PLL_36XX_RATE(432000000, 144, 2, 2, 0),
104 PLL_36XX_RATE(400000000, 200, 3, 2, 0),
105 PLL_36XX_RATE(394073130, 459, 7, 2, 49282),
106 PLL_36XX_RATE(333000000, 111, 2, 2, 0),
107 PLL_36XX_RATE(300000000, 100, 2, 2, 0),
108 PLL_36XX_RATE(266000000, 266, 3, 3, 0),
109 PLL_36XX_RATE(200000000, 200, 3, 3, 0),
110 PLL_36XX_RATE(166000000, 166, 3, 3, 0),
111 PLL_36XX_RATE(133000000, 266, 3, 4, 0),
112 PLL_36XX_RATE(100000000, 200, 3, 4, 0),
113 PLL_36XX_RATE(66000000, 176, 2, 5, 0),
114};
115
116#ifdef CONFIG_PM_SLEEP
117
118static int exynos5260_clk_suspend(void)
119{
120 struct exynos5260_clock_reg_cache *cache;
121
122 list_for_each_entry(cache, &clock_reg_cache_list, node)
123 samsung_clk_save(cache->reg_base, cache->rdump,
124 cache->rd_num);
125
126 return 0;
127}
128
129static void exynos5260_clk_resume(void)
130{
131 struct exynos5260_clock_reg_cache *cache;
132
133 list_for_each_entry(cache, &clock_reg_cache_list, node)
134 samsung_clk_restore(cache->reg_base, cache->rdump,
135 cache->rd_num);
136}
137
138static struct syscore_ops exynos5260_clk_syscore_ops = {
139 .suspend = exynos5260_clk_suspend,
140 .resume = exynos5260_clk_resume,
141};
142
143static void exynos5260_clk_sleep_init(void __iomem *reg_base,
144 unsigned long *rdump,
145 unsigned long nr_rdump)
146{
147 struct exynos5260_clock_reg_cache *reg_cache;
148
149 reg_cache = kzalloc(sizeof(struct exynos5260_clock_reg_cache),
150 GFP_KERNEL);
151 if (!reg_cache)
152 panic("could not allocate register cache.\n");
153
154 reg_cache->rdump = samsung_clk_alloc_reg_dump(rdump, nr_rdump);
155
156 if (!reg_cache->rdump)
157 panic("could not allocate register dump storage.\n");
158
159 if (list_empty(&clock_reg_cache_list))
160 register_syscore_ops(&exynos5260_clk_syscore_ops);
161
162 reg_cache->rd_num = nr_rdump;
163 reg_cache->reg_base = reg_base;
164 list_add_tail(&reg_cache->node, &clock_reg_cache_list);
165}
166
167#else
168static void exynos5260_clk_sleep_init(void __iomem *reg_base,
169 unsigned long *rdump,
170 unsigned long nr_rdump){}
171#endif
172
173/*
174 * Common function which registers plls, muxes, dividers and gates
175 * for each CMU. It also add CMU register list to register cache.
176 */
177
178void __init exynos5260_cmu_register_one(struct device_node *np,
179 struct exynos5260_cmu_info *cmu)
180{
181 void __iomem *reg_base;
182 struct samsung_clk_provider *ctx;
183
184 reg_base = of_iomap(np, 0);
185 if (!reg_base)
186 panic("%s: failed to map registers\n", __func__);
187
188 ctx = samsung_clk_init(np, reg_base, cmu->nr_clk_ids);
189 if (!ctx)
190 panic("%s: unable to alllocate ctx\n", __func__);
191
192 if (cmu->pll_clks)
193 samsung_clk_register_pll(ctx, cmu->pll_clks, cmu->nr_pll_clks,
194 reg_base);
195 if (cmu->mux_clks)
196 samsung_clk_register_mux(ctx, cmu->mux_clks,
197 cmu->nr_mux_clks);
198 if (cmu->div_clks)
199 samsung_clk_register_div(ctx, cmu->div_clks, cmu->nr_div_clks);
200 if (cmu->gate_clks)
201 samsung_clk_register_gate(ctx, cmu->gate_clks,
202 cmu->nr_gate_clks);
203 if (cmu->fixed_clks)
204 samsung_clk_register_fixed_rate(ctx, cmu->fixed_clks,
205 cmu->nr_fixed_clks);
206 if (cmu->clk_regs)
207 exynos5260_clk_sleep_init(reg_base, cmu->clk_regs,
208 cmu->nr_clk_regs);
209}
210
211
212/* CMU_AUD */
213
214static unsigned long aud_clk_regs[] __initdata = {
215 MUX_SEL_AUD,
216 DIV_AUD0,
217 DIV_AUD1,
218 EN_ACLK_AUD,
219 EN_PCLK_AUD,
220 EN_SCLK_AUD,
221 EN_IP_AUD,
222};
223
224PNAME(mout_aud_pll_user_p) = {"fin_pll", "fout_aud_pll"};
225PNAME(mout_sclk_aud_i2s_p) = {"mout_aud_pll_user", "ioclk_i2s_cdclk"};
226PNAME(mout_sclk_aud_pcm_p) = {"mout_aud_pll_user", "ioclk_pcm_extclk"};
227
228struct samsung_mux_clock aud_mux_clks[] __initdata = {
229 MUX(AUD_MOUT_AUD_PLL_USER, "mout_aud_pll_user", mout_aud_pll_user_p,
230 MUX_SEL_AUD, 0, 1),
231 MUX(AUD_MOUT_SCLK_AUD_I2S, "mout_sclk_aud_i2s", mout_sclk_aud_i2s_p,
232 MUX_SEL_AUD, 4, 1),
233 MUX(AUD_MOUT_SCLK_AUD_PCM, "mout_sclk_aud_pcm", mout_sclk_aud_pcm_p,
234 MUX_SEL_AUD, 8, 1),
235};
236
237struct samsung_div_clock aud_div_clks[] __initdata = {
238 DIV(AUD_DOUT_ACLK_AUD_131, "dout_aclk_aud_131", "mout_aud_pll_user",
239 DIV_AUD0, 0, 4),
240
241 DIV(AUD_DOUT_SCLK_AUD_I2S, "dout_sclk_aud_i2s", "mout_sclk_aud_i2s",
242 DIV_AUD1, 0, 4),
243 DIV(AUD_DOUT_SCLK_AUD_PCM, "dout_sclk_aud_pcm", "mout_sclk_aud_pcm",
244 DIV_AUD1, 4, 8),
245 DIV(AUD_DOUT_SCLK_AUD_UART, "dout_sclk_aud_uart", "mout_aud_pll_user",
246 DIV_AUD1, 12, 4),
247};
248
249struct samsung_gate_clock aud_gate_clks[] __initdata = {
250 GATE(AUD_SCLK_I2S, "sclk_aud_i2s", "dout_sclk_aud_i2s",
251 EN_SCLK_AUD, 0, CLK_SET_RATE_PARENT, 0),
252 GATE(AUD_SCLK_PCM, "sclk_aud_pcm", "dout_sclk_aud_pcm",
253 EN_SCLK_AUD, 1, CLK_SET_RATE_PARENT, 0),
254 GATE(AUD_SCLK_AUD_UART, "sclk_aud_uart", "dout_sclk_aud_uart",
255 EN_SCLK_AUD, 2, CLK_SET_RATE_PARENT, 0),
256
257 GATE(AUD_CLK_SRAMC, "clk_sramc", "dout_aclk_aud_131", EN_IP_AUD,
258 0, 0, 0),
259 GATE(AUD_CLK_DMAC, "clk_dmac", "dout_aclk_aud_131",
260 EN_IP_AUD, 1, 0, 0),
261 GATE(AUD_CLK_I2S, "clk_i2s", "dout_aclk_aud_131", EN_IP_AUD, 2, 0, 0),
262 GATE(AUD_CLK_PCM, "clk_pcm", "dout_aclk_aud_131", EN_IP_AUD, 3, 0, 0),
263 GATE(AUD_CLK_AUD_UART, "clk_aud_uart", "dout_aclk_aud_131",
264 EN_IP_AUD, 4, 0, 0),
265};
266
267static void __init exynos5260_clk_aud_init(struct device_node *np)
268{
269 struct exynos5260_cmu_info cmu = {0};
270
271 cmu.mux_clks = aud_mux_clks;
272 cmu.nr_mux_clks = ARRAY_SIZE(aud_mux_clks);
273 cmu.div_clks = aud_div_clks;
274 cmu.nr_div_clks = ARRAY_SIZE(aud_div_clks);
275 cmu.gate_clks = aud_gate_clks;
276 cmu.nr_gate_clks = ARRAY_SIZE(aud_gate_clks);
277 cmu.nr_clk_ids = AUD_NR_CLK;
278 cmu.clk_regs = aud_clk_regs;
279 cmu.nr_clk_regs = ARRAY_SIZE(aud_clk_regs);
280
281 exynos5260_cmu_register_one(np, &cmu);
282}
283
284CLK_OF_DECLARE(exynos5260_clk_aud, "samsung,exynos5260-clock-aud",
285 exynos5260_clk_aud_init);
286
287
288/* CMU_DISP */
289
290static unsigned long disp_clk_regs[] __initdata = {
291 MUX_SEL_DISP0,
292 MUX_SEL_DISP1,
293 MUX_SEL_DISP2,
294 MUX_SEL_DISP3,
295 MUX_SEL_DISP4,
296 DIV_DISP,
297 EN_ACLK_DISP,
298 EN_PCLK_DISP,
299 EN_SCLK_DISP0,
300 EN_SCLK_DISP1,
301 EN_IP_DISP,
302 EN_IP_DISP_BUS,
303};
304
305PNAME(mout_phyclk_dptx_phy_ch3_txd_clk_user_p) = {"fin_pll",
306 "phyclk_dptx_phy_ch3_txd_clk"};
307PNAME(mout_phyclk_dptx_phy_ch2_txd_clk_user_p) = {"fin_pll",
308 "phyclk_dptx_phy_ch2_txd_clk"};
309PNAME(mout_phyclk_dptx_phy_ch1_txd_clk_user_p) = {"fin_pll",
310 "phyclk_dptx_phy_ch1_txd_clk"};
311PNAME(mout_phyclk_dptx_phy_ch0_txd_clk_user_p) = {"fin_pll",
312 "phyclk_dptx_phy_ch0_txd_clk"};
313PNAME(mout_aclk_disp_222_user_p) = {"fin_pll", "dout_aclk_disp_222"};
314PNAME(mout_sclk_disp_pixel_user_p) = {"fin_pll", "dout_sclk_disp_pixel"};
315PNAME(mout_aclk_disp_333_user_p) = {"fin_pll", "dout_aclk_disp_333"};
316PNAME(mout_phyclk_hdmi_phy_tmds_clko_user_p) = {"fin_pll",
317 "phyclk_hdmi_phy_tmds_clko"};
318PNAME(mout_phyclk_hdmi_phy_ref_clko_user_p) = {"fin_pll",
319 "phyclk_hdmi_phy_ref_clko"};
320PNAME(mout_phyclk_hdmi_phy_pixel_clko_user_p) = {"fin_pll",
321 "phyclk_hdmi_phy_pixel_clko"};
322PNAME(mout_phyclk_hdmi_link_o_tmds_clkhi_user_p) = {"fin_pll",
323 "phyclk_hdmi_link_o_tmds_clkhi"};
324PNAME(mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs_p) = {"fin_pll",
325 "phyclk_mipi_dphy_4l_m_txbyte_clkhs"};
326PNAME(mout_phyclk_dptx_phy_o_ref_clk_24m_user_p) = {"fin_pll",
327 "phyclk_dptx_phy_o_ref_clk_24m"};
328PNAME(mout_phyclk_dptx_phy_clk_div2_user_p) = {"fin_pll",
329 "phyclk_dptx_phy_clk_div2"};
330PNAME(mout_sclk_hdmi_pixel_p) = {"mout_sclk_disp_pixel_user",
331 "mout_aclk_disp_222_user"};
332PNAME(mout_phyclk_mipi_dphy_4lmrxclk_esc0_user_p) = {"fin_pll",
333 "phyclk_mipi_dphy_4l_m_rxclkesc0"};
334PNAME(mout_sclk_hdmi_spdif_p) = {"fin_pll", "ioclk_spdif_extclk",
335 "dout_aclk_peri_aud", "phyclk_hdmi_phy_ref_cko"};
336
337struct samsung_mux_clock disp_mux_clks[] __initdata = {
338 MUX(DISP_MOUT_ACLK_DISP_333_USER, "mout_aclk_disp_333_user",
339 mout_aclk_disp_333_user_p,
340 MUX_SEL_DISP0, 0, 1),
341 MUX(DISP_MOUT_SCLK_DISP_PIXEL_USER, "mout_sclk_disp_pixel_user",
342 mout_sclk_disp_pixel_user_p,
343 MUX_SEL_DISP0, 4, 1),
344 MUX(DISP_MOUT_ACLK_DISP_222_USER, "mout_aclk_disp_222_user",
345 mout_aclk_disp_222_user_p,
346 MUX_SEL_DISP0, 8, 1),
347 MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CH0_TXD_CLK_USER,
348 "mout_phyclk_dptx_phy_ch0_txd_clk_user",
349 mout_phyclk_dptx_phy_ch0_txd_clk_user_p,
350 MUX_SEL_DISP0, 16, 1),
351 MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CH1_TXD_CLK_USER,
352 "mout_phyclk_dptx_phy_ch1_txd_clk_user",
353 mout_phyclk_dptx_phy_ch1_txd_clk_user_p,
354 MUX_SEL_DISP0, 20, 1),
355 MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CH2_TXD_CLK_USER,
356 "mout_phyclk_dptx_phy_ch2_txd_clk_user",
357 mout_phyclk_dptx_phy_ch2_txd_clk_user_p,
358 MUX_SEL_DISP0, 24, 1),
359 MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CH3_TXD_CLK_USER,
360 "mout_phyclk_dptx_phy_ch3_txd_clk_user",
361 mout_phyclk_dptx_phy_ch3_txd_clk_user_p,
362 MUX_SEL_DISP0, 28, 1),
363
364 MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CLK_DIV2_USER,
365 "mout_phyclk_dptx_phy_clk_div2_user",
366 mout_phyclk_dptx_phy_clk_div2_user_p,
367 MUX_SEL_DISP1, 0, 1),
368 MUX(DISP_MOUT_PHYCLK_DPTX_PHY_O_REF_CLK_24M_USER,
369 "mout_phyclk_dptx_phy_o_ref_clk_24m_user",
370 mout_phyclk_dptx_phy_o_ref_clk_24m_user_p,
371 MUX_SEL_DISP1, 4, 1),
372 MUX(DISP_MOUT_PHYCLK_MIPI_DPHY_4L_M_TXBYTE_CLKHS,
373 "mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs",
374 mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs_p,
375 MUX_SEL_DISP1, 8, 1),
376 MUX(DISP_MOUT_PHYCLK_HDMI_LINK_O_TMDS_CLKHI_USER,
377 "mout_phyclk_hdmi_link_o_tmds_clkhi_user",
378 mout_phyclk_hdmi_link_o_tmds_clkhi_user_p,
379 MUX_SEL_DISP1, 16, 1),
380 MUX(DISP_MOUT_HDMI_PHY_PIXEL,
381 "mout_phyclk_hdmi_phy_pixel_clko_user",
382 mout_phyclk_hdmi_phy_pixel_clko_user_p,
383 MUX_SEL_DISP1, 20, 1),
384 MUX(DISP_MOUT_PHYCLK_HDMI_PHY_REF_CLKO_USER,
385 "mout_phyclk_hdmi_phy_ref_clko_user",
386 mout_phyclk_hdmi_phy_ref_clko_user_p,
387 MUX_SEL_DISP1, 24, 1),
388 MUX(DISP_MOUT_PHYCLK_HDMI_PHY_TMDS_CLKO_USER,
389 "mout_phyclk_hdmi_phy_tmds_clko_user",
390 mout_phyclk_hdmi_phy_tmds_clko_user_p,
391 MUX_SEL_DISP1, 28, 1),
392
393 MUX(DISP_MOUT_PHYCLK_MIPI_DPHY_4LMRXCLK_ESC0_USER,
394 "mout_phyclk_mipi_dphy_4lmrxclk_esc0_user",
395 mout_phyclk_mipi_dphy_4lmrxclk_esc0_user_p,
396 MUX_SEL_DISP2, 0, 1),
397 MUX(DISP_MOUT_SCLK_HDMI_PIXEL, "mout_sclk_hdmi_pixel",
398 mout_sclk_hdmi_pixel_p,
399 MUX_SEL_DISP2, 4, 1),
400
401 MUX(DISP_MOUT_SCLK_HDMI_SPDIF, "mout_sclk_hdmi_spdif",
402 mout_sclk_hdmi_spdif_p,
403 MUX_SEL_DISP4, 4, 2),
404};
405
406struct samsung_div_clock disp_div_clks[] __initdata = {
407 DIV(DISP_DOUT_PCLK_DISP_111, "dout_pclk_disp_111",
408 "mout_aclk_disp_222_user",
409 DIV_DISP, 8, 4),
410 DIV(DISP_DOUT_SCLK_FIMD1_EXTCLKPLL, "dout_sclk_fimd1_extclkpll",
411 "mout_sclk_disp_pixel_user",
412 DIV_DISP, 12, 4),
413 DIV(DISP_DOUT_SCLK_HDMI_PHY_PIXEL_CLKI,
414 "dout_sclk_hdmi_phy_pixel_clki",
415 "mout_sclk_hdmi_pixel",
416 DIV_DISP, 16, 4),
417};
418
419struct samsung_gate_clock disp_gate_clks[] __initdata = {
420 GATE(DISP_MOUT_HDMI_PHY_PIXEL_USER, "sclk_hdmi_link_i_pixel",
421 "mout_phyclk_hdmi_phy_pixel_clko_user",
422 EN_SCLK_DISP0, 26, CLK_SET_RATE_PARENT, 0),
423 GATE(DISP_SCLK_PIXEL, "sclk_hdmi_phy_pixel_clki",
424 "dout_sclk_hdmi_phy_pixel_clki",
425 EN_SCLK_DISP0, 29, CLK_SET_RATE_PARENT, 0),
426
427 GATE(DISP_CLK_DP, "clk_dptx_link", "mout_aclk_disp_222_user",
428 EN_IP_DISP, 4, 0, 0),
429 GATE(DISP_CLK_DPPHY, "clk_dptx_phy", "mout_aclk_disp_222_user",
430 EN_IP_DISP, 5, 0, 0),
431 GATE(DISP_CLK_DSIM1, "clk_dsim1", "mout_aclk_disp_222_user",
432 EN_IP_DISP, 6, 0, 0),
433 GATE(DISP_CLK_FIMD1, "clk_fimd1", "mout_aclk_disp_222_user",
434 EN_IP_DISP, 7, 0, 0),
435 GATE(DISP_CLK_HDMI, "clk_hdmi", "mout_aclk_disp_222_user",
436 EN_IP_DISP, 8, 0, 0),
437 GATE(DISP_CLK_HDMIPHY, "clk_hdmiphy", "mout_aclk_disp_222_user",
438 EN_IP_DISP, 9, 0, 0),
439 GATE(DISP_CLK_MIPIPHY, "clk_mipi_dphy", "mout_aclk_disp_222_user",
440 EN_IP_DISP, 10, 0, 0),
441 GATE(DISP_CLK_MIXER, "clk_mixer", "mout_aclk_disp_222_user",
442 EN_IP_DISP, 11, 0, 0),
443 GATE(DISP_CLK_PIXEL_DISP, "clk_pixel_disp", "mout_aclk_disp_222_user",
444 EN_IP_DISP, 12, CLK_IGNORE_UNUSED, 0),
445 GATE(DISP_CLK_PIXEL_MIXER, "clk_pixel_mixer", "mout_aclk_disp_222_user",
446 EN_IP_DISP, 13, CLK_IGNORE_UNUSED, 0),
447 GATE(DISP_CLK_SMMU_FIMD1M0, "clk_smmu3_fimd1m0",
448 "mout_aclk_disp_222_user",
449 EN_IP_DISP, 22, 0, 0),
450 GATE(DISP_CLK_SMMU_FIMD1M1, "clk_smmu3_fimd1m1",
451 "mout_aclk_disp_222_user",
452 EN_IP_DISP, 23, 0, 0),
453 GATE(DISP_CLK_SMMU_TV, "clk_smmu3_tv", "mout_aclk_disp_222_user",
454 EN_IP_DISP, 25, 0, 0),
455};
456
457static void __init exynos5260_clk_disp_init(struct device_node *np)
458{
459 struct exynos5260_cmu_info cmu = {0};
460
461 cmu.mux_clks = disp_mux_clks;
462 cmu.nr_mux_clks = ARRAY_SIZE(disp_mux_clks);
463 cmu.div_clks = disp_div_clks;
464 cmu.nr_div_clks = ARRAY_SIZE(disp_div_clks);
465 cmu.gate_clks = disp_gate_clks;
466 cmu.nr_gate_clks = ARRAY_SIZE(disp_gate_clks);
467 cmu.nr_clk_ids = DISP_NR_CLK;
468 cmu.clk_regs = disp_clk_regs;
469 cmu.nr_clk_regs = ARRAY_SIZE(disp_clk_regs);
470
471 exynos5260_cmu_register_one(np, &cmu);
472}
473
474CLK_OF_DECLARE(exynos5260_clk_disp, "samsung,exynos5260-clock-disp",
475 exynos5260_clk_disp_init);
476
477
478/* CMU_EGL */
479
480static unsigned long egl_clk_regs[] __initdata = {
481 EGL_PLL_LOCK,
482 EGL_PLL_CON0,
483 EGL_PLL_CON1,
484 EGL_PLL_FREQ_DET,
485 MUX_SEL_EGL,
486 MUX_ENABLE_EGL,
487 DIV_EGL,
488 DIV_EGL_PLL_FDET,
489 EN_ACLK_EGL,
490 EN_PCLK_EGL,
491 EN_SCLK_EGL,
492};
493
494PNAME(mout_egl_b_p) = {"mout_egl_pll", "dout_bus_pll"};
495PNAME(mout_egl_pll_p) = {"fin_pll", "fout_egl_pll"};
496
497struct samsung_mux_clock egl_mux_clks[] __initdata = {
498 MUX(EGL_MOUT_EGL_PLL, "mout_egl_pll", mout_egl_pll_p,
499 MUX_SEL_EGL, 4, 1),
500 MUX(EGL_MOUT_EGL_B, "mout_egl_b", mout_egl_b_p, MUX_SEL_EGL, 16, 1),
501};
502
503struct samsung_div_clock egl_div_clks[] __initdata = {
504 DIV(EGL_DOUT_EGL1, "dout_egl1", "mout_egl_b", DIV_EGL, 0, 3),
505 DIV(EGL_DOUT_EGL2, "dout_egl2", "dout_egl1", DIV_EGL, 4, 3),
506 DIV(EGL_DOUT_ACLK_EGL, "dout_aclk_egl", "dout_egl2", DIV_EGL, 8, 3),
507 DIV(EGL_DOUT_PCLK_EGL, "dout_pclk_egl", "dout_egl_atclk",
508 DIV_EGL, 12, 3),
509 DIV(EGL_DOUT_EGL_ATCLK, "dout_egl_atclk", "dout_egl2", DIV_EGL, 16, 3),
510 DIV(EGL_DOUT_EGL_PCLK_DBG, "dout_egl_pclk_dbg", "dout_egl_atclk",
511 DIV_EGL, 20, 3),
512 DIV(EGL_DOUT_EGL_PLL, "dout_egl_pll", "mout_egl_b", DIV_EGL, 24, 3),
513};
514
515static struct samsung_pll_clock egl_pll_clks[] __initdata = {
516 PLL(pll_2550xx, EGL_FOUT_EGL_PLL, "fout_egl_pll", "fin_pll",
517 EGL_PLL_LOCK, EGL_PLL_CON0,
518 pll2550_24mhz_tbl),
519};
520
521static void __init exynos5260_clk_egl_init(struct device_node *np)
522{
523 struct exynos5260_cmu_info cmu = {0};
524
525 cmu.pll_clks = egl_pll_clks;
526 cmu.nr_pll_clks = ARRAY_SIZE(egl_pll_clks);
527 cmu.mux_clks = egl_mux_clks;
528 cmu.nr_mux_clks = ARRAY_SIZE(egl_mux_clks);
529 cmu.div_clks = egl_div_clks;
530 cmu.nr_div_clks = ARRAY_SIZE(egl_div_clks);
531 cmu.nr_clk_ids = EGL_NR_CLK;
532 cmu.clk_regs = egl_clk_regs;
533 cmu.nr_clk_regs = ARRAY_SIZE(egl_clk_regs);
534
535 exynos5260_cmu_register_one(np, &cmu);
536}
537
538CLK_OF_DECLARE(exynos5260_clk_egl, "samsung,exynos5260-clock-egl",
539 exynos5260_clk_egl_init);
540
541
542/* CMU_FSYS */
543
544static unsigned long fsys_clk_regs[] __initdata = {
545 MUX_SEL_FSYS0,
546 MUX_SEL_FSYS1,
547 EN_ACLK_FSYS,
548 EN_ACLK_FSYS_SECURE_RTIC,
549 EN_ACLK_FSYS_SECURE_SMMU_RTIC,
550 EN_SCLK_FSYS,
551 EN_IP_FSYS,
552 EN_IP_FSYS_SECURE_RTIC,
553 EN_IP_FSYS_SECURE_SMMU_RTIC,
554};
555
556PNAME(mout_phyclk_usbhost20_phyclk_user_p) = {"fin_pll",
557 "phyclk_usbhost20_phy_phyclock"};
558PNAME(mout_phyclk_usbhost20_freeclk_user_p) = {"fin_pll",
559 "phyclk_usbhost20_phy_freeclk"};
560PNAME(mout_phyclk_usbhost20_clk48mohci_user_p) = {"fin_pll",
561 "phyclk_usbhost20_phy_clk48mohci"};
562PNAME(mout_phyclk_usbdrd30_pipe_pclk_user_p) = {"fin_pll",
563 "phyclk_usbdrd30_udrd30_pipe_pclk"};
564PNAME(mout_phyclk_usbdrd30_phyclock_user_p) = {"fin_pll",
565 "phyclk_usbdrd30_udrd30_phyclock"};
566
567struct samsung_mux_clock fsys_mux_clks[] __initdata = {
568 MUX(FSYS_MOUT_PHYCLK_USBDRD30_PHYCLOCK_USER,
569 "mout_phyclk_usbdrd30_phyclock_user",
570 mout_phyclk_usbdrd30_phyclock_user_p,
571 MUX_SEL_FSYS1, 0, 1),
572 MUX(FSYS_MOUT_PHYCLK_USBDRD30_PIPE_PCLK_USER,
573 "mout_phyclk_usbdrd30_pipe_pclk_user",
574 mout_phyclk_usbdrd30_pipe_pclk_user_p,
575 MUX_SEL_FSYS1, 4, 1),
576 MUX(FSYS_MOUT_PHYCLK_USBHOST20_CLK48MOHCI_USER,
577 "mout_phyclk_usbhost20_clk48mohci_user",
578 mout_phyclk_usbhost20_clk48mohci_user_p,
579 MUX_SEL_FSYS1, 8, 1),
580 MUX(FSYS_MOUT_PHYCLK_USBHOST20_FREECLK_USER,
581 "mout_phyclk_usbhost20_freeclk_user",
582 mout_phyclk_usbhost20_freeclk_user_p,
583 MUX_SEL_FSYS1, 12, 1),
584 MUX(FSYS_MOUT_PHYCLK_USBHOST20_PHYCLK_USER,
585 "mout_phyclk_usbhost20_phyclk_user",
586 mout_phyclk_usbhost20_phyclk_user_p,
587 MUX_SEL_FSYS1, 16, 1),
588};
589
590struct samsung_gate_clock fsys_gate_clks[] __initdata = {
591 GATE(FSYS_PHYCLK_USBHOST20, "phyclk_usbhost20_phyclock",
592 "mout_phyclk_usbdrd30_phyclock_user",
593 EN_SCLK_FSYS, 1, 0, 0),
594 GATE(FSYS_PHYCLK_USBDRD30, "phyclk_usbdrd30_udrd30_phyclock_g",
595 "mout_phyclk_usbdrd30_phyclock_user",
596 EN_SCLK_FSYS, 7, 0, 0),
597
598 GATE(FSYS_CLK_MMC0, "clk_mmc0", "dout_aclk_fsys_200",
599 EN_IP_FSYS, 6, 0, 0),
600 GATE(FSYS_CLK_MMC1, "clk_mmc1", "dout_aclk_fsys_200",
601 EN_IP_FSYS, 7, 0, 0),
602 GATE(FSYS_CLK_MMC2, "clk_mmc2", "dout_aclk_fsys_200",
603 EN_IP_FSYS, 8, 0, 0),
604 GATE(FSYS_CLK_PDMA, "clk_pdma", "dout_aclk_fsys_200",
605 EN_IP_FSYS, 9, 0, 0),
606 GATE(FSYS_CLK_SROMC, "clk_sromc", "dout_aclk_fsys_200",
607 EN_IP_FSYS, 13, 0, 0),
608 GATE(FSYS_CLK_USBDRD30, "clk_usbdrd30", "dout_aclk_fsys_200",
609 EN_IP_FSYS, 14, 0, 0),
610 GATE(FSYS_CLK_USBHOST20, "clk_usbhost20", "dout_aclk_fsys_200",
611 EN_IP_FSYS, 15, 0, 0),
612 GATE(FSYS_CLK_USBLINK, "clk_usblink", "dout_aclk_fsys_200",
613 EN_IP_FSYS, 18, 0, 0),
614 GATE(FSYS_CLK_TSI, "clk_tsi", "dout_aclk_fsys_200",
615 EN_IP_FSYS, 20, 0, 0),
616
617 GATE(FSYS_CLK_RTIC, "clk_rtic", "dout_aclk_fsys_200",
618 EN_IP_FSYS_SECURE_RTIC, 11, 0, 0),
619 GATE(FSYS_CLK_SMMU_RTIC, "clk_smmu_rtic", "dout_aclk_fsys_200",
620 EN_IP_FSYS_SECURE_SMMU_RTIC, 12, 0, 0),
621};
622
623static void __init exynos5260_clk_fsys_init(struct device_node *np)
624{
625 struct exynos5260_cmu_info cmu = {0};
626
627 cmu.mux_clks = fsys_mux_clks;
628 cmu.nr_mux_clks = ARRAY_SIZE(fsys_mux_clks);
629 cmu.gate_clks = fsys_gate_clks;
630 cmu.nr_gate_clks = ARRAY_SIZE(fsys_gate_clks);
631 cmu.nr_clk_ids = FSYS_NR_CLK;
632 cmu.clk_regs = fsys_clk_regs;
633 cmu.nr_clk_regs = ARRAY_SIZE(fsys_clk_regs);
634
635 exynos5260_cmu_register_one(np, &cmu);
636}
637
638CLK_OF_DECLARE(exynos5260_clk_fsys, "samsung,exynos5260-clock-fsys",
639 exynos5260_clk_fsys_init);
640
641
642/* CMU_G2D */
643
644static unsigned long g2d_clk_regs[] __initdata = {
645 MUX_SEL_G2D,
646 MUX_STAT_G2D,
647 DIV_G2D,
648 EN_ACLK_G2D,
649 EN_ACLK_G2D_SECURE_SSS,
650 EN_ACLK_G2D_SECURE_SLIM_SSS,
651 EN_ACLK_G2D_SECURE_SMMU_SLIM_SSS,
652 EN_ACLK_G2D_SECURE_SMMU_SSS,
653 EN_ACLK_G2D_SECURE_SMMU_MDMA,
654 EN_ACLK_G2D_SECURE_SMMU_G2D,
655 EN_PCLK_G2D,
656 EN_PCLK_G2D_SECURE_SMMU_SLIM_SSS,
657 EN_PCLK_G2D_SECURE_SMMU_SSS,
658 EN_PCLK_G2D_SECURE_SMMU_MDMA,
659 EN_PCLK_G2D_SECURE_SMMU_G2D,
660 EN_IP_G2D,
661 EN_IP_G2D_SECURE_SSS,
662 EN_IP_G2D_SECURE_SLIM_SSS,
663 EN_IP_G2D_SECURE_SMMU_SLIM_SSS,
664 EN_IP_G2D_SECURE_SMMU_SSS,
665 EN_IP_G2D_SECURE_SMMU_MDMA,
666 EN_IP_G2D_SECURE_SMMU_G2D,
667};
668
669PNAME(mout_aclk_g2d_333_user_p) = {"fin_pll", "dout_aclk_g2d_333"};
670
671struct samsung_mux_clock g2d_mux_clks[] __initdata = {
672 MUX(G2D_MOUT_ACLK_G2D_333_USER, "mout_aclk_g2d_333_user",
673 mout_aclk_g2d_333_user_p,
674 MUX_SEL_G2D, 0, 1),
675};
676
677struct samsung_div_clock g2d_div_clks[] __initdata = {
678 DIV(G2D_DOUT_PCLK_G2D_83, "dout_pclk_g2d_83", "mout_aclk_g2d_333_user",
679 DIV_G2D, 0, 3),
680};
681
682struct samsung_gate_clock g2d_gate_clks[] __initdata = {
683 GATE(G2D_CLK_G2D, "clk_g2d", "mout_aclk_g2d_333_user",
684 EN_IP_G2D, 4, 0, 0),
685 GATE(G2D_CLK_JPEG, "clk_jpeg", "mout_aclk_g2d_333_user",
686 EN_IP_G2D, 5, 0, 0),
687 GATE(G2D_CLK_MDMA, "clk_mdma", "mout_aclk_g2d_333_user",
688 EN_IP_G2D, 6, 0, 0),
689 GATE(G2D_CLK_SMMU3_JPEG, "clk_smmu3_jpeg", "mout_aclk_g2d_333_user",
690 EN_IP_G2D, 16, 0, 0),
691
692 GATE(G2D_CLK_SSS, "clk_sss", "mout_aclk_g2d_333_user",
693 EN_IP_G2D_SECURE_SSS, 17, 0, 0),
694
695 GATE(G2D_CLK_SLIM_SSS, "clk_slim_sss", "mout_aclk_g2d_333_user",
696 EN_IP_G2D_SECURE_SLIM_SSS, 11, 0, 0),
697
698 GATE(G2D_CLK_SMMU_SLIM_SSS, "clk_smmu_slim_sss",
699 "mout_aclk_g2d_333_user",
700 EN_IP_G2D_SECURE_SMMU_SLIM_SSS, 13, 0, 0),
701
702 GATE(G2D_CLK_SMMU_SSS, "clk_smmu_sss", "mout_aclk_g2d_333_user",
703 EN_IP_G2D_SECURE_SMMU_SSS, 14, 0, 0),
704
705 GATE(G2D_CLK_SMMU_MDMA, "clk_smmu_mdma", "mout_aclk_g2d_333_user",
706 EN_IP_G2D_SECURE_SMMU_MDMA, 12, 0, 0),
707
708 GATE(G2D_CLK_SMMU3_G2D, "clk_smmu3_g2d", "mout_aclk_g2d_333_user",
709 EN_IP_G2D_SECURE_SMMU_G2D, 15, 0, 0),
710};
711
712static void __init exynos5260_clk_g2d_init(struct device_node *np)
713{
714 struct exynos5260_cmu_info cmu = {0};
715
716 cmu.mux_clks = g2d_mux_clks;
717 cmu.nr_mux_clks = ARRAY_SIZE(g2d_mux_clks);
718 cmu.div_clks = g2d_div_clks;
719 cmu.nr_div_clks = ARRAY_SIZE(g2d_div_clks);
720 cmu.gate_clks = g2d_gate_clks;
721 cmu.nr_gate_clks = ARRAY_SIZE(g2d_gate_clks);
722 cmu.nr_clk_ids = G2D_NR_CLK;
723 cmu.clk_regs = g2d_clk_regs;
724 cmu.nr_clk_regs = ARRAY_SIZE(g2d_clk_regs);
725
726 exynos5260_cmu_register_one(np, &cmu);
727}
728
729CLK_OF_DECLARE(exynos5260_clk_g2d, "samsung,exynos5260-clock-g2d",
730 exynos5260_clk_g2d_init);
731
732
733/* CMU_G3D */
734
735static unsigned long g3d_clk_regs[] __initdata = {
736 G3D_PLL_LOCK,
737 G3D_PLL_CON0,
738 G3D_PLL_CON1,
739 G3D_PLL_FDET,
740 MUX_SEL_G3D,
741 DIV_G3D,
742 DIV_G3D_PLL_FDET,
743 EN_ACLK_G3D,
744 EN_PCLK_G3D,
745 EN_SCLK_G3D,
746 EN_IP_G3D,
747};
748
749PNAME(mout_g3d_pll_p) = {"fin_pll", "fout_g3d_pll"};
750
751struct samsung_mux_clock g3d_mux_clks[] __initdata = {
752 MUX(G3D_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p,
753 MUX_SEL_G3D, 0, 1),
754};
755
756struct samsung_div_clock g3d_div_clks[] __initdata = {
757 DIV(G3D_DOUT_PCLK_G3D, "dout_pclk_g3d", "dout_aclk_g3d", DIV_G3D, 0, 3),
758 DIV(G3D_DOUT_ACLK_G3D, "dout_aclk_g3d", "mout_g3d_pll", DIV_G3D, 4, 3),
759};
760
761struct samsung_gate_clock g3d_gate_clks[] __initdata = {
762 GATE(G3D_CLK_G3D, "clk_g3d", "dout_aclk_g3d", EN_IP_G3D, 2, 0, 0),
763 GATE(G3D_CLK_G3D_HPM, "clk_g3d_hpm", "dout_aclk_g3d",
764 EN_IP_G3D, 3, 0, 0),
765};
766
767static struct samsung_pll_clock g3d_pll_clks[] __initdata = {
768 PLL(pll_2550, G3D_FOUT_G3D_PLL, "fout_g3d_pll", "fin_pll",
769 G3D_PLL_LOCK, G3D_PLL_CON0,
770 pll2550_24mhz_tbl),
771};
772
773static void __init exynos5260_clk_g3d_init(struct device_node *np)
774{
775 struct exynos5260_cmu_info cmu = {0};
776
777 cmu.pll_clks = g3d_pll_clks;
778 cmu.nr_pll_clks = ARRAY_SIZE(g3d_pll_clks);
779 cmu.mux_clks = g3d_mux_clks;
780 cmu.nr_mux_clks = ARRAY_SIZE(g3d_mux_clks);
781 cmu.div_clks = g3d_div_clks;
782 cmu.nr_div_clks = ARRAY_SIZE(g3d_div_clks);
783 cmu.gate_clks = g3d_gate_clks;
784 cmu.nr_gate_clks = ARRAY_SIZE(g3d_gate_clks);
785 cmu.nr_clk_ids = G3D_NR_CLK;
786 cmu.clk_regs = g3d_clk_regs;
787 cmu.nr_clk_regs = ARRAY_SIZE(g3d_clk_regs);
788
789 exynos5260_cmu_register_one(np, &cmu);
790}
791
792CLK_OF_DECLARE(exynos5260_clk_g3d, "samsung,exynos5260-clock-g3d",
793 exynos5260_clk_g3d_init);
794
795
796/* CMU_GSCL */
797
798static unsigned long gscl_clk_regs[] __initdata = {
799 MUX_SEL_GSCL,
800 DIV_GSCL,
801 EN_ACLK_GSCL,
802 EN_ACLK_GSCL_FIMC,
803 EN_ACLK_GSCL_SECURE_SMMU_GSCL0,
804 EN_ACLK_GSCL_SECURE_SMMU_GSCL1,
805 EN_ACLK_GSCL_SECURE_SMMU_MSCL0,
806 EN_ACLK_GSCL_SECURE_SMMU_MSCL1,
807 EN_PCLK_GSCL,
808 EN_PCLK_GSCL_FIMC,
809 EN_PCLK_GSCL_SECURE_SMMU_GSCL0,
810 EN_PCLK_GSCL_SECURE_SMMU_GSCL1,
811 EN_PCLK_GSCL_SECURE_SMMU_MSCL0,
812 EN_PCLK_GSCL_SECURE_SMMU_MSCL1,
813 EN_SCLK_GSCL,
814 EN_SCLK_GSCL_FIMC,
815 EN_IP_GSCL,
816 EN_IP_GSCL_FIMC,
817 EN_IP_GSCL_SECURE_SMMU_GSCL0,
818 EN_IP_GSCL_SECURE_SMMU_GSCL1,
819 EN_IP_GSCL_SECURE_SMMU_MSCL0,
820 EN_IP_GSCL_SECURE_SMMU_MSCL1,
821};
822
823PNAME(mout_aclk_gscl_333_user_p) = {"fin_pll", "dout_aclk_gscl_333"};
824PNAME(mout_aclk_m2m_400_user_p) = {"fin_pll", "dout_aclk_gscl_400"};
825PNAME(mout_aclk_gscl_fimc_user_p) = {"fin_pll", "dout_aclk_gscl_400"};
826PNAME(mout_aclk_csis_p) = {"dout_aclk_csis_200", "mout_aclk_gscl_fimc_user"};
827
828struct samsung_mux_clock gscl_mux_clks[] __initdata = {
829 MUX(GSCL_MOUT_ACLK_GSCL_333_USER, "mout_aclk_gscl_333_user",
830 mout_aclk_gscl_333_user_p,
831 MUX_SEL_GSCL, 0, 1),
832 MUX(GSCL_MOUT_ACLK_M2M_400_USER, "mout_aclk_m2m_400_user",
833 mout_aclk_m2m_400_user_p,
834 MUX_SEL_GSCL, 4, 1),
835 MUX(GSCL_MOUT_ACLK_GSCL_FIMC_USER, "mout_aclk_gscl_fimc_user",
836 mout_aclk_gscl_fimc_user_p,
837 MUX_SEL_GSCL, 8, 1),
838 MUX(GSCL_MOUT_ACLK_CSIS, "mout_aclk_csis", mout_aclk_csis_p,
839 MUX_SEL_GSCL, 24, 1),
840};
841
842struct samsung_div_clock gscl_div_clks[] __initdata = {
843 DIV(GSCL_DOUT_PCLK_M2M_100, "dout_pclk_m2m_100",
844 "mout_aclk_m2m_400_user",
845 DIV_GSCL, 0, 3),
846 DIV(GSCL_DOUT_ACLK_CSIS_200, "dout_aclk_csis_200",
847 "mout_aclk_m2m_400_user",
848 DIV_GSCL, 4, 3),
849};
850
851struct samsung_gate_clock gscl_gate_clks[] __initdata = {
852 GATE(GSCL_SCLK_CSIS0_WRAP, "sclk_csis0_wrap", "dout_aclk_csis_200",
853 EN_SCLK_GSCL_FIMC, 0, CLK_SET_RATE_PARENT, 0),
854 GATE(GSCL_SCLK_CSIS1_WRAP, "sclk_csis1_wrap", "dout_aclk_csis_200",
855 EN_SCLK_GSCL_FIMC, 1, CLK_SET_RATE_PARENT, 0),
856
857 GATE(GSCL_CLK_GSCL0, "clk_gscl0", "mout_aclk_gscl_333_user",
858 EN_IP_GSCL, 2, 0, 0),
859 GATE(GSCL_CLK_GSCL1, "clk_gscl1", "mout_aclk_gscl_333_user",
860 EN_IP_GSCL, 3, 0, 0),
861 GATE(GSCL_CLK_MSCL0, "clk_mscl0", "mout_aclk_gscl_333_user",
862 EN_IP_GSCL, 4, 0, 0),
863 GATE(GSCL_CLK_MSCL1, "clk_mscl1", "mout_aclk_gscl_333_user",
864 EN_IP_GSCL, 5, 0, 0),
865 GATE(GSCL_CLK_PIXEL_GSCL0, "clk_pixel_gscl0",
866 "mout_aclk_gscl_333_user",
867 EN_IP_GSCL, 8, 0, 0),
868 GATE(GSCL_CLK_PIXEL_GSCL1, "clk_pixel_gscl1",
869 "mout_aclk_gscl_333_user",
870 EN_IP_GSCL, 9, 0, 0),
871
872 GATE(GSCL_CLK_SMMU3_LITE_A, "clk_smmu3_lite_a",
873 "mout_aclk_gscl_fimc_user",
874 EN_IP_GSCL_FIMC, 5, 0, 0),
875 GATE(GSCL_CLK_SMMU3_LITE_B, "clk_smmu3_lite_b",
876 "mout_aclk_gscl_fimc_user",
877 EN_IP_GSCL_FIMC, 6, 0, 0),
878 GATE(GSCL_CLK_SMMU3_LITE_D, "clk_smmu3_lite_d",
879 "mout_aclk_gscl_fimc_user",
880 EN_IP_GSCL_FIMC, 7, 0, 0),
881 GATE(GSCL_CLK_CSIS0, "clk_csis0", "mout_aclk_gscl_fimc_user",
882 EN_IP_GSCL_FIMC, 8, 0, 0),
883 GATE(GSCL_CLK_CSIS1, "clk_csis1", "mout_aclk_gscl_fimc_user",
884 EN_IP_GSCL_FIMC, 9, 0, 0),
885 GATE(GSCL_CLK_FIMC_LITE_A, "clk_fimc_lite_a",
886 "mout_aclk_gscl_fimc_user",
887 EN_IP_GSCL_FIMC, 10, 0, 0),
888 GATE(GSCL_CLK_FIMC_LITE_B, "clk_fimc_lite_b",
889 "mout_aclk_gscl_fimc_user",
890 EN_IP_GSCL_FIMC, 11, 0, 0),
891 GATE(GSCL_CLK_FIMC_LITE_D, "clk_fimc_lite_d",
892 "mout_aclk_gscl_fimc_user",
893 EN_IP_GSCL_FIMC, 12, 0, 0),
894
895 GATE(GSCL_CLK_SMMU3_GSCL0, "clk_smmu3_gscl0",
896 "mout_aclk_gscl_333_user",
897 EN_IP_GSCL_SECURE_SMMU_GSCL0, 17, 0, 0),
898 GATE(GSCL_CLK_SMMU3_GSCL1, "clk_smmu3_gscl1", "mout_aclk_gscl_333_user",
899 EN_IP_GSCL_SECURE_SMMU_GSCL1, 18, 0, 0),
900 GATE(GSCL_CLK_SMMU3_MSCL0, "clk_smmu3_mscl0",
901 "mout_aclk_m2m_400_user",
902 EN_IP_GSCL_SECURE_SMMU_MSCL0, 19, 0, 0),
903 GATE(GSCL_CLK_SMMU3_MSCL1, "clk_smmu3_mscl1",
904 "mout_aclk_m2m_400_user",
905 EN_IP_GSCL_SECURE_SMMU_MSCL1, 20, 0, 0),
906};
907
908static void __init exynos5260_clk_gscl_init(struct device_node *np)
909{
910 struct exynos5260_cmu_info cmu = {0};
911
912 cmu.mux_clks = gscl_mux_clks;
913 cmu.nr_mux_clks = ARRAY_SIZE(gscl_mux_clks);
914 cmu.div_clks = gscl_div_clks;
915 cmu.nr_div_clks = ARRAY_SIZE(gscl_div_clks);
916 cmu.gate_clks = gscl_gate_clks;
917 cmu.nr_gate_clks = ARRAY_SIZE(gscl_gate_clks);
918 cmu.nr_clk_ids = GSCL_NR_CLK;
919 cmu.clk_regs = gscl_clk_regs;
920 cmu.nr_clk_regs = ARRAY_SIZE(gscl_clk_regs);
921
922 exynos5260_cmu_register_one(np, &cmu);
923}
924
925CLK_OF_DECLARE(exynos5260_clk_gscl, "samsung,exynos5260-clock-gscl",
926 exynos5260_clk_gscl_init);
927
928
929/* CMU_ISP */
930
931static unsigned long isp_clk_regs[] __initdata = {
932 MUX_SEL_ISP0,
933 MUX_SEL_ISP1,
934 DIV_ISP,
935 EN_ACLK_ISP0,
936 EN_ACLK_ISP1,
937 EN_PCLK_ISP0,
938 EN_PCLK_ISP1,
939 EN_SCLK_ISP,
940 EN_IP_ISP0,
941 EN_IP_ISP1,
942};
943
944PNAME(mout_isp_400_user_p) = {"fin_pll", "dout_aclk_isp1_400"};
945PNAME(mout_isp_266_user_p) = {"fin_pll", "dout_aclk_isp1_266"};
946
947struct samsung_mux_clock isp_mux_clks[] __initdata = {
948 MUX(ISP_MOUT_ISP_266_USER, "mout_isp_266_user", mout_isp_266_user_p,
949 MUX_SEL_ISP0, 0, 1),
950 MUX(ISP_MOUT_ISP_400_USER, "mout_isp_400_user", mout_isp_400_user_p,
951 MUX_SEL_ISP0, 4, 1),
952};
953
954struct samsung_div_clock isp_div_clks[] __initdata = {
955 DIV(ISP_DOUT_PCLK_ISP_66, "dout_pclk_isp_66", "mout_kfc",
956 DIV_ISP, 0, 3),
957 DIV(ISP_DOUT_PCLK_ISP_133, "dout_pclk_isp_133", "mout_kfc",
958 DIV_ISP, 4, 4),
959 DIV(ISP_DOUT_CA5_ATCLKIN, "dout_ca5_atclkin", "mout_kfc",
960 DIV_ISP, 12, 3),
961 DIV(ISP_DOUT_CA5_PCLKDBG, "dout_ca5_pclkdbg", "mout_kfc",
962 DIV_ISP, 16, 4),
963 DIV(ISP_DOUT_SCLK_MPWM, "dout_sclk_mpwm", "mout_kfc", DIV_ISP, 20, 2),
964};
965
966struct samsung_gate_clock isp_gate_clks[] __initdata = {
967 GATE(ISP_CLK_GIC, "clk_isp_gic", "mout_aclk_isp1_266",
968 EN_IP_ISP0, 15, 0, 0),
969
970 GATE(ISP_CLK_CA5, "clk_isp_ca5", "mout_aclk_isp1_266",
971 EN_IP_ISP1, 1, 0, 0),
972 GATE(ISP_CLK_FIMC_DRC, "clk_isp_fimc_drc", "mout_aclk_isp1_266",
973 EN_IP_ISP1, 2, 0, 0),
974 GATE(ISP_CLK_FIMC_FD, "clk_isp_fimc_fd", "mout_aclk_isp1_266",
975 EN_IP_ISP1, 3, 0, 0),
976 GATE(ISP_CLK_FIMC, "clk_isp_fimc", "mout_aclk_isp1_266",
977 EN_IP_ISP1, 4, 0, 0),
978 GATE(ISP_CLK_FIMC_SCALERC, "clk_isp_fimc_scalerc",
979 "mout_aclk_isp1_266",
980 EN_IP_ISP1, 5, 0, 0),
981 GATE(ISP_CLK_FIMC_SCALERP, "clk_isp_fimc_scalerp",
982 "mout_aclk_isp1_266",
983 EN_IP_ISP1, 6, 0, 0),
984 GATE(ISP_CLK_I2C0, "clk_isp_i2c0", "mout_aclk_isp1_266",
985 EN_IP_ISP1, 7, 0, 0),
986 GATE(ISP_CLK_I2C1, "clk_isp_i2c1", "mout_aclk_isp1_266",
987 EN_IP_ISP1, 8, 0, 0),
988 GATE(ISP_CLK_MCUCTL, "clk_isp_mcuctl", "mout_aclk_isp1_266",
989 EN_IP_ISP1, 9, 0, 0),
990 GATE(ISP_CLK_MPWM, "clk_isp_mpwm", "mout_aclk_isp1_266",
991 EN_IP_ISP1, 10, 0, 0),
992 GATE(ISP_CLK_MTCADC, "clk_isp_mtcadc", "mout_aclk_isp1_266",
993 EN_IP_ISP1, 11, 0, 0),
994 GATE(ISP_CLK_PWM, "clk_isp_pwm", "mout_aclk_isp1_266",
995 EN_IP_ISP1, 14, 0, 0),
996 GATE(ISP_CLK_SMMU_DRC, "clk_smmu_drc", "mout_aclk_isp1_266",
997 EN_IP_ISP1, 21, 0, 0),
998 GATE(ISP_CLK_SMMU_FD, "clk_smmu_fd", "mout_aclk_isp1_266",
999 EN_IP_ISP1, 22, 0, 0),
1000 GATE(ISP_CLK_SMMU_ISP, "clk_smmu_isp", "mout_aclk_isp1_266",
1001 EN_IP_ISP1, 23, 0, 0),
1002 GATE(ISP_CLK_SMMU_ISPCX, "clk_smmu_ispcx", "mout_aclk_isp1_266",
1003 EN_IP_ISP1, 24, 0, 0),
1004 GATE(ISP_CLK_SMMU_SCALERC, "clk_isp_smmu_scalerc",
1005 "mout_aclk_isp1_266",
1006 EN_IP_ISP1, 25, 0, 0),
1007 GATE(ISP_CLK_SMMU_SCALERP, "clk_isp_smmu_scalerp",
1008 "mout_aclk_isp1_266",
1009 EN_IP_ISP1, 26, 0, 0),
1010 GATE(ISP_CLK_SPI0, "clk_isp_spi0", "mout_aclk_isp1_266",
1011 EN_IP_ISP1, 27, 0, 0),
1012 GATE(ISP_CLK_SPI1, "clk_isp_spi1", "mout_aclk_isp1_266",
1013 EN_IP_ISP1, 28, 0, 0),
1014 GATE(ISP_CLK_WDT, "clk_isp_wdt", "mout_aclk_isp1_266",
1015 EN_IP_ISP1, 31, 0, 0),
1016 GATE(ISP_CLK_UART, "clk_isp_uart", "mout_aclk_isp1_266",
1017 EN_IP_ISP1, 30, 0, 0),
1018
1019 GATE(ISP_SCLK_UART_EXT, "sclk_isp_uart_ext", "fin_pll",
1020 EN_SCLK_ISP, 7, CLK_SET_RATE_PARENT, 0),
1021 GATE(ISP_SCLK_SPI1_EXT, "sclk_isp_spi1_ext", "fin_pll",
1022 EN_SCLK_ISP, 8, CLK_SET_RATE_PARENT, 0),
1023 GATE(ISP_SCLK_SPI0_EXT, "sclk_isp_spi0_ext", "fin_pll",
1024 EN_SCLK_ISP, 9, CLK_SET_RATE_PARENT, 0),
1025};
1026
1027static void __init exynos5260_clk_isp_init(struct device_node *np)
1028{
1029 struct exynos5260_cmu_info cmu = {0};
1030
1031 cmu.mux_clks = isp_mux_clks;
1032 cmu.nr_mux_clks = ARRAY_SIZE(isp_mux_clks);
1033 cmu.div_clks = isp_div_clks;
1034 cmu.nr_div_clks = ARRAY_SIZE(isp_div_clks);
1035 cmu.gate_clks = isp_gate_clks;
1036 cmu.nr_gate_clks = ARRAY_SIZE(isp_gate_clks);
1037 cmu.nr_clk_ids = ISP_NR_CLK;
1038 cmu.clk_regs = isp_clk_regs;
1039 cmu.nr_clk_regs = ARRAY_SIZE(isp_clk_regs);
1040
1041 exynos5260_cmu_register_one(np, &cmu);
1042}
1043
1044CLK_OF_DECLARE(exynos5260_clk_isp, "samsung,exynos5260-clock-isp",
1045 exynos5260_clk_isp_init);
1046
1047
1048/* CMU_KFC */
1049
1050static unsigned long kfc_clk_regs[] __initdata = {
1051 KFC_PLL_LOCK,
1052 KFC_PLL_CON0,
1053 KFC_PLL_CON1,
1054 KFC_PLL_FDET,
1055 MUX_SEL_KFC0,
1056 MUX_SEL_KFC2,
1057 DIV_KFC,
1058 DIV_KFC_PLL_FDET,
1059 EN_ACLK_KFC,
1060 EN_PCLK_KFC,
1061 EN_SCLK_KFC,
1062 EN_IP_KFC,
1063};
1064
1065PNAME(mout_kfc_pll_p) = {"fin_pll", "fout_kfc_pll"};
1066PNAME(mout_kfc_p) = {"mout_kfc_pll", "dout_media_pll"};
1067
1068struct samsung_mux_clock kfc_mux_clks[] __initdata = {
1069 MUX(KFC_MOUT_KFC_PLL, "mout_kfc_pll", mout_kfc_pll_p,
1070 MUX_SEL_KFC0, 0, 1),
1071 MUX(KFC_MOUT_KFC, "mout_kfc", mout_kfc_p, MUX_SEL_KFC2, 0, 1),
1072};
1073
1074struct samsung_div_clock kfc_div_clks[] __initdata = {
1075 DIV(KFC_DOUT_KFC1, "dout_kfc1", "mout_kfc", DIV_KFC, 0, 3),
1076 DIV(KFC_DOUT_KFC2, "dout_kfc2", "dout_kfc1", DIV_KFC, 4, 3),
1077 DIV(KFC_DOUT_KFC_ATCLK, "dout_kfc_atclk", "dout_kfc2", DIV_KFC, 8, 3),
1078 DIV(KFC_DOUT_KFC_PCLK_DBG, "dout_kfc_pclk_dbg", "dout_kfc2",
1079 DIV_KFC, 12, 3),
1080 DIV(KFC_DOUT_ACLK_KFC, "dout_aclk_kfc", "dout_kfc2", DIV_KFC, 16, 3),
1081 DIV(KFC_DOUT_PCLK_KFC, "dout_pclk_kfc", "dout_kfc2", DIV_KFC, 20, 3),
1082 DIV(KFC_DOUT_KFC_PLL, "dout_kfc_pll", "mout_kfc", DIV_KFC, 24, 3),
1083};
1084
1085static struct samsung_pll_clock kfc_pll_clks[] __initdata = {
1086 PLL(pll_2550xx, KFC_FOUT_KFC_PLL, "fout_kfc_pll", "fin_pll",
1087 KFC_PLL_LOCK, KFC_PLL_CON0,
1088 pll2550_24mhz_tbl),
1089};
1090
1091static void __init exynos5260_clk_kfc_init(struct device_node *np)
1092{
1093 struct exynos5260_cmu_info cmu = {0};
1094
1095 cmu.pll_clks = kfc_pll_clks;
1096 cmu.nr_pll_clks = ARRAY_SIZE(kfc_pll_clks);
1097 cmu.mux_clks = kfc_mux_clks;
1098 cmu.nr_mux_clks = ARRAY_SIZE(kfc_mux_clks);
1099 cmu.div_clks = kfc_div_clks;
1100 cmu.nr_div_clks = ARRAY_SIZE(kfc_div_clks);
1101 cmu.nr_clk_ids = KFC_NR_CLK;
1102 cmu.clk_regs = kfc_clk_regs;
1103 cmu.nr_clk_regs = ARRAY_SIZE(kfc_clk_regs);
1104
1105 exynos5260_cmu_register_one(np, &cmu);
1106}
1107
1108CLK_OF_DECLARE(exynos5260_clk_kfc, "samsung,exynos5260-clock-kfc",
1109 exynos5260_clk_kfc_init);
1110
1111
1112/* CMU_MFC */
1113
1114static unsigned long mfc_clk_regs[] __initdata = {
1115 MUX_SEL_MFC,
1116 DIV_MFC,
1117 EN_ACLK_MFC,
1118 EN_ACLK_SECURE_SMMU2_MFC,
1119 EN_PCLK_MFC,
1120 EN_PCLK_SECURE_SMMU2_MFC,
1121 EN_IP_MFC,
1122 EN_IP_MFC_SECURE_SMMU2_MFC,
1123};
1124
1125PNAME(mout_aclk_mfc_333_user_p) = {"fin_pll", "dout_aclk_mfc_333"};
1126
1127struct samsung_mux_clock mfc_mux_clks[] __initdata = {
1128 MUX(MFC_MOUT_ACLK_MFC_333_USER, "mout_aclk_mfc_333_user",
1129 mout_aclk_mfc_333_user_p,
1130 MUX_SEL_MFC, 0, 1),
1131};
1132
1133struct samsung_div_clock mfc_div_clks[] __initdata = {
1134 DIV(MFC_DOUT_PCLK_MFC_83, "dout_pclk_mfc_83", "mout_aclk_mfc_333_user",
1135 DIV_MFC, 0, 3),
1136};
1137
1138struct samsung_gate_clock mfc_gate_clks[] __initdata = {
1139 GATE(MFC_CLK_MFC, "clk_mfc", "mout_aclk_mfc_333_user",
1140 EN_IP_MFC, 1, 0, 0),
1141 GATE(MFC_CLK_SMMU2_MFCM0, "clk_smmu2_mfcm0", "mout_aclk_mfc_333_user",
1142 EN_IP_MFC_SECURE_SMMU2_MFC, 6, 0, 0),
1143 GATE(MFC_CLK_SMMU2_MFCM1, "clk_smmu2_mfcm1", "mout_aclk_mfc_333_user",
1144 EN_IP_MFC_SECURE_SMMU2_MFC, 7, 0, 0),
1145};
1146
1147static void __init exynos5260_clk_mfc_init(struct device_node *np)
1148{
1149 struct exynos5260_cmu_info cmu = {0};
1150
1151 cmu.mux_clks = mfc_mux_clks;
1152 cmu.nr_mux_clks = ARRAY_SIZE(mfc_mux_clks);
1153 cmu.div_clks = mfc_div_clks;
1154 cmu.nr_div_clks = ARRAY_SIZE(mfc_div_clks);
1155 cmu.gate_clks = mfc_gate_clks;
1156 cmu.nr_gate_clks = ARRAY_SIZE(mfc_gate_clks);
1157 cmu.nr_clk_ids = MFC_NR_CLK;
1158 cmu.clk_regs = mfc_clk_regs;
1159 cmu.nr_clk_regs = ARRAY_SIZE(mfc_clk_regs);
1160
1161 exynos5260_cmu_register_one(np, &cmu);
1162}
1163
1164CLK_OF_DECLARE(exynos5260_clk_mfc, "samsung,exynos5260-clock-mfc",
1165 exynos5260_clk_mfc_init);
1166
1167
1168/* CMU_MIF */
1169
1170static unsigned long mif_clk_regs[] __initdata = {
1171 MEM_PLL_LOCK,
1172 BUS_PLL_LOCK,
1173 MEDIA_PLL_LOCK,
1174 MEM_PLL_CON0,
1175 MEM_PLL_CON1,
1176 MEM_PLL_FDET,
1177 BUS_PLL_CON0,
1178 BUS_PLL_CON1,
1179 BUS_PLL_FDET,
1180 MEDIA_PLL_CON0,
1181 MEDIA_PLL_CON1,
1182 MEDIA_PLL_FDET,
1183 MUX_SEL_MIF,
1184 DIV_MIF,
1185 DIV_MIF_PLL_FDET,
1186 EN_ACLK_MIF,
1187 EN_ACLK_MIF_SECURE_DREX1_TZ,
1188 EN_ACLK_MIF_SECURE_DREX0_TZ,
1189 EN_ACLK_MIF_SECURE_INTMEM,
1190 EN_PCLK_MIF,
1191 EN_PCLK_MIF_SECURE_MONOCNT,
1192 EN_PCLK_MIF_SECURE_RTC_APBIF,
1193 EN_PCLK_MIF_SECURE_DREX1_TZ,
1194 EN_PCLK_MIF_SECURE_DREX0_TZ,
1195 EN_SCLK_MIF,
1196 EN_IP_MIF,
1197 EN_IP_MIF_SECURE_MONOCNT,
1198 EN_IP_MIF_SECURE_RTC_APBIF,
1199 EN_IP_MIF_SECURE_DREX1_TZ,
1200 EN_IP_MIF_SECURE_DREX0_TZ,
1201 EN_IP_MIF_SECURE_INTEMEM,
1202};
1203
1204PNAME(mout_mem_pll_p) = {"fin_pll", "fout_mem_pll"};
1205PNAME(mout_bus_pll_p) = {"fin_pll", "fout_bus_pll"};
1206PNAME(mout_media_pll_p) = {"fin_pll", "fout_media_pll"};
1207PNAME(mout_mif_drex_p) = {"dout_mem_pll", "dout_bus_pll"};
1208PNAME(mout_mif_drex2x_p) = {"dout_mem_pll", "dout_bus_pll"};
1209PNAME(mout_clkm_phy_p) = {"mout_mif_drex", "dout_media_pll"};
1210PNAME(mout_clk2x_phy_p) = {"mout_mif_drex2x", "dout_media_pll"};
1211
1212struct samsung_mux_clock mif_mux_clks[] __initdata = {
1213 MUX(MIF_MOUT_MEM_PLL, "mout_mem_pll", mout_mem_pll_p,
1214 MUX_SEL_MIF, 0, 1),
1215 MUX(MIF_MOUT_BUS_PLL, "mout_bus_pll", mout_bus_pll_p,
1216 MUX_SEL_MIF, 4, 1),
1217 MUX(MIF_MOUT_MEDIA_PLL, "mout_media_pll", mout_media_pll_p,
1218 MUX_SEL_MIF, 8, 1),
1219 MUX(MIF_MOUT_MIF_DREX, "mout_mif_drex", mout_mif_drex_p,
1220 MUX_SEL_MIF, 12, 1),
1221 MUX(MIF_MOUT_CLKM_PHY, "mout_clkm_phy", mout_clkm_phy_p,
1222 MUX_SEL_MIF, 16, 1),
1223 MUX(MIF_MOUT_MIF_DREX2X, "mout_mif_drex2x", mout_mif_drex2x_p,
1224 MUX_SEL_MIF, 20, 1),
1225 MUX(MIF_MOUT_CLK2X_PHY, "mout_clk2x_phy", mout_clk2x_phy_p,
1226 MUX_SEL_MIF, 24, 1),
1227};
1228
1229struct samsung_div_clock mif_div_clks[] __initdata = {
1230 DIV(MIF_DOUT_MEDIA_PLL, "dout_media_pll", "mout_media_pll",
1231 DIV_MIF, 0, 3),
1232 DIV(MIF_DOUT_MEM_PLL, "dout_mem_pll", "mout_mem_pll",
1233 DIV_MIF, 4, 3),
1234 DIV(MIF_DOUT_BUS_PLL, "dout_bus_pll", "mout_bus_pll",
1235 DIV_MIF, 8, 3),
1236 DIV(MIF_DOUT_CLKM_PHY, "dout_clkm_phy", "mout_clkm_phy",
1237 DIV_MIF, 12, 3),
1238 DIV(MIF_DOUT_CLK2X_PHY, "dout_clk2x_phy", "mout_clk2x_phy",
1239 DIV_MIF, 16, 4),
1240 DIV(MIF_DOUT_ACLK_MIF_466, "dout_aclk_mif_466", "dout_clk2x_phy",
1241 DIV_MIF, 20, 3),
1242 DIV(MIF_DOUT_ACLK_BUS_200, "dout_aclk_bus_200", "dout_bus_pll",
1243 DIV_MIF, 24, 3),
1244 DIV(MIF_DOUT_ACLK_BUS_100, "dout_aclk_bus_100", "dout_bus_pll",
1245 DIV_MIF, 28, 4),
1246};
1247
1248struct samsung_gate_clock mif_gate_clks[] __initdata = {
1249 GATE(MIF_CLK_LPDDR3PHY_WRAP0, "clk_lpddr3phy_wrap0", "dout_clk2x_phy",
1250 EN_IP_MIF, 12, CLK_IGNORE_UNUSED, 0),
1251 GATE(MIF_CLK_LPDDR3PHY_WRAP1, "clk_lpddr3phy_wrap1", "dout_clk2x_phy",
1252 EN_IP_MIF, 13, CLK_IGNORE_UNUSED, 0),
1253
1254 GATE(MIF_CLK_MONOCNT, "clk_monocnt", "dout_aclk_bus_100",
1255 EN_IP_MIF_SECURE_MONOCNT, 22,
1256 CLK_IGNORE_UNUSED, 0),
1257
1258 GATE(MIF_CLK_MIF_RTC, "clk_mif_rtc", "dout_aclk_bus_100",
1259 EN_IP_MIF_SECURE_RTC_APBIF, 23,
1260 CLK_IGNORE_UNUSED, 0),
1261
1262 GATE(MIF_CLK_DREX1, "clk_drex1", "dout_aclk_mif_466",
1263 EN_IP_MIF_SECURE_DREX1_TZ, 9,
1264 CLK_IGNORE_UNUSED, 0),
1265
1266 GATE(MIF_CLK_DREX0, "clk_drex0", "dout_aclk_mif_466",
1267 EN_IP_MIF_SECURE_DREX0_TZ, 9,
1268 CLK_IGNORE_UNUSED, 0),
1269
1270 GATE(MIF_CLK_INTMEM, "clk_intmem", "dout_aclk_bus_200",
1271 EN_IP_MIF_SECURE_INTEMEM, 11,
1272 CLK_IGNORE_UNUSED, 0),
1273
1274 GATE(MIF_SCLK_LPDDR3PHY_WRAP_U0, "sclk_lpddr3phy_wrap_u0",
1275 "dout_clkm_phy", EN_SCLK_MIF, 0,
1276 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1277 GATE(MIF_SCLK_LPDDR3PHY_WRAP_U1, "sclk_lpddr3phy_wrap_u1",
1278 "dout_clkm_phy", EN_SCLK_MIF, 1,
1279 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1280};
1281
1282static struct samsung_pll_clock mif_pll_clks[] __initdata = {
1283 PLL(pll_2550xx, MIF_FOUT_MEM_PLL, "fout_mem_pll", "fin_pll",
1284 MEM_PLL_LOCK, MEM_PLL_CON0,
1285 pll2550_24mhz_tbl),
1286 PLL(pll_2550xx, MIF_FOUT_BUS_PLL, "fout_bus_pll", "fin_pll",
1287 BUS_PLL_LOCK, BUS_PLL_CON0,
1288 pll2550_24mhz_tbl),
1289 PLL(pll_2550xx, MIF_FOUT_MEDIA_PLL, "fout_media_pll", "fin_pll",
1290 MEDIA_PLL_LOCK, MEDIA_PLL_CON0,
1291 pll2550_24mhz_tbl),
1292};
1293
1294static void __init exynos5260_clk_mif_init(struct device_node *np)
1295{
1296 struct exynos5260_cmu_info cmu = {0};
1297
1298 cmu.pll_clks = mif_pll_clks;
1299 cmu.nr_pll_clks = ARRAY_SIZE(mif_pll_clks);
1300 cmu.mux_clks = mif_mux_clks;
1301 cmu.nr_mux_clks = ARRAY_SIZE(mif_mux_clks);
1302 cmu.div_clks = mif_div_clks;
1303 cmu.nr_div_clks = ARRAY_SIZE(mif_div_clks);
1304 cmu.gate_clks = mif_gate_clks;
1305 cmu.nr_gate_clks = ARRAY_SIZE(mif_gate_clks);
1306 cmu.nr_clk_ids = MIF_NR_CLK;
1307 cmu.clk_regs = mif_clk_regs;
1308 cmu.nr_clk_regs = ARRAY_SIZE(mif_clk_regs);
1309
1310 exynos5260_cmu_register_one(np, &cmu);
1311}
1312
1313CLK_OF_DECLARE(exynos5260_clk_mif, "samsung,exynos5260-clock-mif",
1314 exynos5260_clk_mif_init);
1315
1316
1317/* CMU_PERI */
1318
1319static unsigned long peri_clk_regs[] __initdata = {
1320 MUX_SEL_PERI,
1321 MUX_SEL_PERI1,
1322 DIV_PERI,
1323 EN_PCLK_PERI0,
1324 EN_PCLK_PERI1,
1325 EN_PCLK_PERI2,
1326 EN_PCLK_PERI3,
1327 EN_PCLK_PERI_SECURE_CHIPID,
1328 EN_PCLK_PERI_SECURE_PROVKEY0,
1329 EN_PCLK_PERI_SECURE_PROVKEY1,
1330 EN_PCLK_PERI_SECURE_SECKEY,
1331 EN_PCLK_PERI_SECURE_ANTIRBKCNT,
1332 EN_PCLK_PERI_SECURE_TOP_RTC,
1333 EN_PCLK_PERI_SECURE_TZPC,
1334 EN_SCLK_PERI,
1335 EN_SCLK_PERI_SECURE_TOP_RTC,
1336 EN_IP_PERI0,
1337 EN_IP_PERI1,
1338 EN_IP_PERI2,
1339 EN_IP_PERI_SECURE_CHIPID,
1340 EN_IP_PERI_SECURE_PROVKEY0,
1341 EN_IP_PERI_SECURE_PROVKEY1,
1342 EN_IP_PERI_SECURE_SECKEY,
1343 EN_IP_PERI_SECURE_ANTIRBKCNT,
1344 EN_IP_PERI_SECURE_TOP_RTC,
1345 EN_IP_PERI_SECURE_TZPC,
1346};
1347
1348PNAME(mout_sclk_pcm_p) = {"ioclk_pcm_extclk", "fin_pll", "dout_aclk_peri_aud",
1349 "phyclk_hdmi_phy_ref_cko"};
1350PNAME(mout_sclk_i2scod_p) = {"ioclk_i2s_cdclk", "fin_pll", "dout_aclk_peri_aud",
1351 "phyclk_hdmi_phy_ref_cko"};
1352PNAME(mout_sclk_spdif_p) = {"ioclk_spdif_extclk", "fin_pll",
1353 "dout_aclk_peri_aud", "phyclk_hdmi_phy_ref_cko"};
1354
1355struct samsung_mux_clock peri_mux_clks[] __initdata = {
1356 MUX(PERI_MOUT_SCLK_PCM, "mout_sclk_pcm", mout_sclk_pcm_p,
1357 MUX_SEL_PERI1, 4, 2),
1358 MUX(PERI_MOUT_SCLK_I2SCOD, "mout_sclk_i2scod", mout_sclk_i2scod_p,
1359 MUX_SEL_PERI1, 12, 2),
1360 MUX(PERI_MOUT_SCLK_SPDIF, "mout_sclk_spdif", mout_sclk_spdif_p,
1361 MUX_SEL_PERI1, 20, 2),
1362};
1363
1364struct samsung_div_clock peri_div_clks[] __initdata = {
1365 DIV(PERI_DOUT_PCM, "dout_pcm", "mout_sclk_pcm", DIV_PERI, 0, 8),
1366 DIV(PERI_DOUT_I2S, "dout_i2s", "mout_sclk_i2scod", DIV_PERI, 8, 6),
1367};
1368
1369struct samsung_gate_clock peri_gate_clks[] __initdata = {
1370 GATE(PERI_SCLK_PCM1, "sclk_pcm1", "dout_pcm", EN_SCLK_PERI, 0,
1371 CLK_SET_RATE_PARENT, 0),
1372 GATE(PERI_SCLK_I2S, "sclk_i2s", "dout_i2s", EN_SCLK_PERI, 1,
1373 CLK_SET_RATE_PARENT, 0),
1374 GATE(PERI_SCLK_SPDIF, "sclk_spdif", "dout_sclk_peri_spi0_b",
1375 EN_SCLK_PERI, 2, CLK_SET_RATE_PARENT, 0),
1376 GATE(PERI_SCLK_SPI0, "sclk_spi0", "dout_sclk_peri_spi0_b",
1377 EN_SCLK_PERI, 7, CLK_SET_RATE_PARENT, 0),
1378 GATE(PERI_SCLK_SPI1, "sclk_spi1", "dout_sclk_peri_spi1_b",
1379 EN_SCLK_PERI, 8, CLK_SET_RATE_PARENT, 0),
1380 GATE(PERI_SCLK_SPI2, "sclk_spi2", "dout_sclk_peri_spi2_b",
1381 EN_SCLK_PERI, 9, CLK_SET_RATE_PARENT, 0),
1382 GATE(PERI_SCLK_UART0, "sclk_uart0", "dout_sclk_peri_uart0",
1383 EN_SCLK_PERI, 10, CLK_SET_RATE_PARENT, 0),
1384 GATE(PERI_SCLK_UART1, "sclk_uart1", "dout_sclk_peri_uart1",
1385 EN_SCLK_PERI, 11, CLK_SET_RATE_PARENT, 0),
1386 GATE(PERI_SCLK_UART2, "sclk_uart2", "dout_sclk_peri_uart2",
1387 EN_SCLK_PERI, 12, CLK_SET_RATE_PARENT, 0),
1388
1389 GATE(PERI_CLK_ABB, "clk_abb", "dout_aclk_peri_66",
1390 EN_IP_PERI0, 1, 0, 0),
1391 GATE(PERI_CLK_EFUSE_WRITER, "clk_efuse_writer", "dout_aclk_peri_66",
1392 EN_IP_PERI0, 5, 0, 0),
1393 GATE(PERI_CLK_HDMICEC, "clk_hdmicec", "dout_aclk_peri_66",
1394 EN_IP_PERI0, 6, 0, 0),
1395 GATE(PERI_CLK_I2C10, "clk_i2c10", "dout_aclk_peri_66",
1396 EN_IP_PERI0, 7, 0, 0),
1397 GATE(PERI_CLK_I2C11, "clk_i2c11", "dout_aclk_peri_66",
1398 EN_IP_PERI0, 8, 0, 0),
1399 GATE(PERI_CLK_I2C8, "clk_i2c8", "dout_aclk_peri_66",
1400 EN_IP_PERI0, 9, 0, 0),
1401 GATE(PERI_CLK_I2C9, "clk_i2c9", "dout_aclk_peri_66",
1402 EN_IP_PERI0, 10, 0, 0),
1403 GATE(PERI_CLK_I2C4, "clk_i2c4", "dout_aclk_peri_66",
1404 EN_IP_PERI0, 11, 0, 0),
1405 GATE(PERI_CLK_I2C5, "clk_i2c5", "dout_aclk_peri_66",
1406 EN_IP_PERI0, 12, 0, 0),
1407 GATE(PERI_CLK_I2C6, "clk_i2c6", "dout_aclk_peri_66",
1408 EN_IP_PERI0, 13, 0, 0),
1409 GATE(PERI_CLK_I2C7, "clk_i2c7", "dout_aclk_peri_66",
1410 EN_IP_PERI0, 14, 0, 0),
1411 GATE(PERI_CLK_I2CHDMI, "clk_i2chdmi", "dout_aclk_peri_66",
1412 EN_IP_PERI0, 15, 0, 0),
1413 GATE(PERI_CLK_I2S, "clk_peri_i2s", "dout_aclk_peri_66",
1414 EN_IP_PERI0, 16, 0, 0),
1415 GATE(PERI_CLK_MCT, "clk_mct", "dout_aclk_peri_66",
1416 EN_IP_PERI0, 17, 0, 0),
1417 GATE(PERI_CLK_PCM, "clk_peri_pcm", "dout_aclk_peri_66",
1418 EN_IP_PERI0, 18, 0, 0),
1419 GATE(PERI_CLK_HSIC0, "clk_hsic0", "dout_aclk_peri_66",
1420 EN_IP_PERI0, 20, 0, 0),
1421 GATE(PERI_CLK_HSIC1, "clk_hsic1", "dout_aclk_peri_66",
1422 EN_IP_PERI0, 21, 0, 0),
1423 GATE(PERI_CLK_HSIC2, "clk_hsic2", "dout_aclk_peri_66",
1424 EN_IP_PERI0, 22, 0, 0),
1425 GATE(PERI_CLK_HSIC3, "clk_hsic3", "dout_aclk_peri_66",
1426 EN_IP_PERI0, 23, 0, 0),
1427 GATE(PERI_CLK_WDT_EGL, "clk_wdt_egl", "dout_aclk_peri_66",
1428 EN_IP_PERI0, 24, 0, 0),
1429 GATE(PERI_CLK_WDT_KFC, "clk_wdt_kfc", "dout_aclk_peri_66",
1430 EN_IP_PERI0, 25, 0, 0),
1431
1432 GATE(PERI_CLK_UART4, "clk_uart4", "dout_aclk_peri_66",
1433 EN_IP_PERI2, 0, 0, 0),
1434 GATE(PERI_CLK_PWM, "clk_pwm", "dout_aclk_peri_66",
1435 EN_IP_PERI2, 3, 0, 0),
1436 GATE(PERI_CLK_SPDIF, "clk_spdif", "dout_aclk_peri_66",
1437 EN_IP_PERI2, 6, 0, 0),
1438 GATE(PERI_CLK_SPI0, "clk_spi0", "dout_aclk_peri_66",
1439 EN_IP_PERI2, 7, 0, 0),
1440 GATE(PERI_CLK_SPI1, "clk_spi1", "dout_aclk_peri_66",
1441 EN_IP_PERI2, 8, 0, 0),
1442 GATE(PERI_CLK_SPI2, "clk_spi2", "dout_aclk_peri_66",
1443 EN_IP_PERI2, 9, 0, 0),
1444 GATE(PERI_CLK_TMU0, "clk_tmu0", "dout_aclk_peri_66",
1445 EN_IP_PERI2, 10, 0, 0),
1446 GATE(PERI_CLK_TMU1, "clk_tmu1", "dout_aclk_peri_66",
1447 EN_IP_PERI2, 11, 0, 0),
1448 GATE(PERI_CLK_TMU2, "clk_tmu2", "dout_aclk_peri_66",
1449 EN_IP_PERI2, 12, 0, 0),
1450 GATE(PERI_CLK_TMU3, "clk_tmu3", "dout_aclk_peri_66",
1451 EN_IP_PERI2, 13, 0, 0),
1452 GATE(PERI_CLK_TMU4, "clk_tmu4", "dout_aclk_peri_66",
1453 EN_IP_PERI2, 14, 0, 0),
1454 GATE(PERI_CLK_ADC, "clk_adc", "dout_aclk_peri_66",
1455 EN_IP_PERI2, 18, 0, 0),
1456 GATE(PERI_CLK_UART0, "clk_uart0", "dout_aclk_peri_66",
1457 EN_IP_PERI2, 19, 0, 0),
1458 GATE(PERI_CLK_UART1, "clk_uart1", "dout_aclk_peri_66",
1459 EN_IP_PERI2, 20, 0, 0),
1460 GATE(PERI_CLK_UART2, "clk_uart2", "dout_aclk_peri_66",
1461 EN_IP_PERI2, 21, 0, 0),
1462
1463 GATE(PERI_CLK_CHIPID, "clk_chipid", "dout_aclk_peri_66",
1464 EN_IP_PERI_SECURE_CHIPID, 2, 0, 0),
1465
1466 GATE(PERI_CLK_PROVKEY0, "clk_provkey0", "dout_aclk_peri_66",
1467 EN_IP_PERI_SECURE_PROVKEY0, 1, 0, 0),
1468
1469 GATE(PERI_CLK_PROVKEY1, "clk_provkey1", "dout_aclk_peri_66",
1470 EN_IP_PERI_SECURE_PROVKEY1, 2, 0, 0),
1471
1472 GATE(PERI_CLK_SECKEY, "clk_seckey", "dout_aclk_peri_66",
1473 EN_IP_PERI_SECURE_SECKEY, 5, 0, 0),
1474
1475 GATE(PERI_CLK_TOP_RTC, "clk_top_rtc", "dout_aclk_peri_66",
1476 EN_IP_PERI_SECURE_TOP_RTC, 5, 0, 0),
1477
1478 GATE(PERI_CLK_TZPC0, "clk_tzpc0", "dout_aclk_peri_66",
1479 EN_IP_PERI_SECURE_TZPC, 10, 0, 0),
1480 GATE(PERI_CLK_TZPC1, "clk_tzpc1", "dout_aclk_peri_66",
1481 EN_IP_PERI_SECURE_TZPC, 11, 0, 0),
1482 GATE(PERI_CLK_TZPC2, "clk_tzpc2", "dout_aclk_peri_66",
1483 EN_IP_PERI_SECURE_TZPC, 12, 0, 0),
1484 GATE(PERI_CLK_TZPC3, "clk_tzpc3", "dout_aclk_peri_66",
1485 EN_IP_PERI_SECURE_TZPC, 13, 0, 0),
1486 GATE(PERI_CLK_TZPC4, "clk_tzpc4", "dout_aclk_peri_66",
1487 EN_IP_PERI_SECURE_TZPC, 14, 0, 0),
1488 GATE(PERI_CLK_TZPC5, "clk_tzpc5", "dout_aclk_peri_66",
1489 EN_IP_PERI_SECURE_TZPC, 15, 0, 0),
1490 GATE(PERI_CLK_TZPC6, "clk_tzpc6", "dout_aclk_peri_66",
1491 EN_IP_PERI_SECURE_TZPC, 16, 0, 0),
1492 GATE(PERI_CLK_TZPC7, "clk_tzpc7", "dout_aclk_peri_66",
1493 EN_IP_PERI_SECURE_TZPC, 17, 0, 0),
1494 GATE(PERI_CLK_TZPC8, "clk_tzpc8", "dout_aclk_peri_66",
1495 EN_IP_PERI_SECURE_TZPC, 18, 0, 0),
1496 GATE(PERI_CLK_TZPC9, "clk_tzpc9", "dout_aclk_peri_66",
1497 EN_IP_PERI_SECURE_TZPC, 19, 0, 0),
1498 GATE(PERI_CLK_TZPC10, "clk_tzpc10", "dout_aclk_peri_66",
1499 EN_IP_PERI_SECURE_TZPC, 20, 0, 0),
1500};
1501
1502static void __init exynos5260_clk_peri_init(struct device_node *np)
1503{
1504 struct exynos5260_cmu_info cmu = {0};
1505
1506 cmu.mux_clks = peri_mux_clks;
1507 cmu.nr_mux_clks = ARRAY_SIZE(peri_mux_clks);
1508 cmu.div_clks = peri_div_clks;
1509 cmu.nr_div_clks = ARRAY_SIZE(peri_div_clks);
1510 cmu.gate_clks = peri_gate_clks;
1511 cmu.nr_gate_clks = ARRAY_SIZE(peri_gate_clks);
1512 cmu.nr_clk_ids = PERI_NR_CLK;
1513 cmu.clk_regs = peri_clk_regs;
1514 cmu.nr_clk_regs = ARRAY_SIZE(peri_clk_regs);
1515
1516 exynos5260_cmu_register_one(np, &cmu);
1517}
1518
1519CLK_OF_DECLARE(exynos5260_clk_peri, "samsung,exynos5260-clock-peri",
1520 exynos5260_clk_peri_init);
1521
1522
1523/* CMU_TOP */
1524
1525static unsigned long top_clk_regs[] __initdata = {
1526 DISP_PLL_LOCK,
1527 AUD_PLL_LOCK,
1528 DISP_PLL_CON0,
1529 DISP_PLL_CON1,
1530 DISP_PLL_FDET,
1531 AUD_PLL_CON0,
1532 AUD_PLL_CON1,
1533 AUD_PLL_CON2,
1534 AUD_PLL_FDET,
1535 MUX_SEL_TOP_PLL0,
1536 MUX_SEL_TOP_MFC,
1537 MUX_SEL_TOP_G2D,
1538 MUX_SEL_TOP_GSCL,
1539 MUX_SEL_TOP_ISP10,
1540 MUX_SEL_TOP_ISP11,
1541 MUX_SEL_TOP_DISP0,
1542 MUX_SEL_TOP_DISP1,
1543 MUX_SEL_TOP_BUS,
1544 MUX_SEL_TOP_PERI0,
1545 MUX_SEL_TOP_PERI1,
1546 MUX_SEL_TOP_FSYS,
1547 DIV_TOP_G2D_MFC,
1548 DIV_TOP_GSCL_ISP0,
1549 DIV_TOP_ISP10,
1550 DIV_TOP_ISP11,
1551 DIV_TOP_DISP,
1552 DIV_TOP_BUS,
1553 DIV_TOP_PERI0,
1554 DIV_TOP_PERI1,
1555 DIV_TOP_PERI2,
1556 DIV_TOP_FSYS0,
1557 DIV_TOP_FSYS1,
1558 DIV_TOP_HPM,
1559 DIV_TOP_PLL_FDET,
1560 EN_ACLK_TOP,
1561 EN_SCLK_TOP,
1562 EN_IP_TOP,
1563};
1564
1565/* fixed rate clocks generated inside the soc */
1566struct samsung_fixed_rate_clock fixed_rate_clks[] __initdata = {
1567 FRATE(PHYCLK_DPTX_PHY_CH3_TXD_CLK, "phyclk_dptx_phy_ch3_txd_clk", NULL,
1568 CLK_IS_ROOT, 270000000),
1569 FRATE(PHYCLK_DPTX_PHY_CH2_TXD_CLK, "phyclk_dptx_phy_ch2_txd_clk", NULL,
1570 CLK_IS_ROOT, 270000000),
1571 FRATE(PHYCLK_DPTX_PHY_CH1_TXD_CLK, "phyclk_dptx_phy_ch1_txd_clk", NULL,
1572 CLK_IS_ROOT, 270000000),
1573 FRATE(PHYCLK_DPTX_PHY_CH0_TXD_CLK, "phyclk_dptx_phy_ch0_txd_clk", NULL,
1574 CLK_IS_ROOT, 270000000),
1575 FRATE(phyclk_hdmi_phy_tmds_clko, "phyclk_hdmi_phy_tmds_clko", NULL,
1576 CLK_IS_ROOT, 250000000),
1577 FRATE(PHYCLK_HDMI_PHY_PIXEL_CLKO, "phyclk_hdmi_phy_pixel_clko", NULL,
1578 CLK_IS_ROOT, 1660000000),
1579 FRATE(PHYCLK_HDMI_LINK_O_TMDS_CLKHI, "phyclk_hdmi_link_o_tmds_clkhi",
1580 NULL, CLK_IS_ROOT, 125000000),
1581 FRATE(PHYCLK_MIPI_DPHY_4L_M_TXBYTECLKHS,
1582 "phyclk_mipi_dphy_4l_m_txbyteclkhs" , NULL,
1583 CLK_IS_ROOT, 187500000),
1584 FRATE(PHYCLK_DPTX_PHY_O_REF_CLK_24M, "phyclk_dptx_phy_o_ref_clk_24m",
1585 NULL, CLK_IS_ROOT, 24000000),
1586 FRATE(PHYCLK_DPTX_PHY_CLK_DIV2, "phyclk_dptx_phy_clk_div2", NULL,
1587 CLK_IS_ROOT, 135000000),
1588 FRATE(PHYCLK_MIPI_DPHY_4L_M_RXCLKESC0,
1589 "phyclk_mipi_dphy_4l_m_rxclkesc0", NULL,
1590 CLK_IS_ROOT, 20000000),
1591 FRATE(PHYCLK_USBHOST20_PHY_PHYCLOCK, "phyclk_usbhost20_phy_phyclock",
1592 NULL, CLK_IS_ROOT, 60000000),
1593 FRATE(PHYCLK_USBHOST20_PHY_FREECLK, "phyclk_usbhost20_phy_freeclk",
1594 NULL, CLK_IS_ROOT, 60000000),
1595 FRATE(PHYCLK_USBHOST20_PHY_CLK48MOHCI,
1596 "phyclk_usbhost20_phy_clk48mohci",
1597 NULL, CLK_IS_ROOT, 48000000),
1598 FRATE(PHYCLK_USBDRD30_UDRD30_PIPE_PCLK,
1599 "phyclk_usbdrd30_udrd30_pipe_pclk", NULL,
1600 CLK_IS_ROOT, 125000000),
1601 FRATE(PHYCLK_USBDRD30_UDRD30_PHYCLOCK,
1602 "phyclk_usbdrd30_udrd30_phyclock", NULL,
1603 CLK_IS_ROOT, 60000000),
1604};
1605
1606PNAME(mout_memtop_pll_user_p) = {"fin_pll", "dout_mem_pll"};
1607PNAME(mout_bustop_pll_user_p) = {"fin_pll", "dout_bus_pll"};
1608PNAME(mout_mediatop_pll_user_p) = {"fin_pll", "dout_media_pll"};
1609PNAME(mout_audtop_pll_user_p) = {"fin_pll", "mout_aud_pll"};
1610PNAME(mout_aud_pll_p) = {"fin_pll", "fout_aud_pll"};
1611PNAME(mout_disp_pll_p) = {"fin_pll", "fout_disp_pll"};
1612PNAME(mout_mfc_bustop_333_p) = {"mout_bustop_pll_user", "mout_disp_pll"};
1613PNAME(mout_aclk_mfc_333_p) = {"mout_mediatop_pll_user", "mout_mfc_bustop_333"};
1614PNAME(mout_g2d_bustop_333_p) = {"mout_bustop_pll_user", "mout_disp_pll"};
1615PNAME(mout_aclk_g2d_333_p) = {"mout_mediatop_pll_user", "mout_g2d_bustop_333"};
1616PNAME(mout_gscl_bustop_333_p) = {"mout_bustop_pll_user", "mout_disp_pll"};
1617PNAME(mout_aclk_gscl_333_p) = {"mout_mediatop_pll_user",
1618 "mout_gscl_bustop_333"};
1619PNAME(mout_m2m_mediatop_400_p) = {"mout_mediatop_pll_user", "mout_disp_pll"};
1620PNAME(mout_aclk_gscl_400_p) = {"mout_bustop_pll_user",
1621 "mout_m2m_mediatop_400"};
1622PNAME(mout_gscl_bustop_fimc_p) = {"mout_bustop_pll_user", "mout_disp_pll"};
1623PNAME(mout_aclk_gscl_fimc_p) = {"mout_mediatop_pll_user",
1624 "mout_gscl_bustop_fimc"};
1625PNAME(mout_isp1_media_266_p) = {"mout_mediatop_pll_user",
1626 "mout_memtop_pll_user"};
1627PNAME(mout_aclk_isp1_266_p) = {"mout_bustop_pll_user", "mout_isp1_media_266"};
1628PNAME(mout_isp1_media_400_p) = {"mout_mediatop_pll_user", "mout_disp_pll"};
1629PNAME(mout_aclk_isp1_400_p) = {"mout_bustop_pll_user", "mout_isp1_media_400"};
1630PNAME(mout_sclk_isp_spi_p) = {"fin_pll", "mout_bustop_pll_user"};
1631PNAME(mout_sclk_isp_uart_p) = {"fin_pll", "mout_bustop_pll_user"};
1632PNAME(mout_sclk_isp_sensor_p) = {"fin_pll", "mout_bustop_pll_user"};
1633PNAME(mout_disp_disp_333_p) = {"mout_disp_pll", "mout_bustop_pll_user"};
1634PNAME(mout_aclk_disp_333_p) = {"mout_mediatop_pll_user", "mout_disp_disp_333"};
1635PNAME(mout_disp_disp_222_p) = {"mout_disp_pll", "mout_bustop_pll_user"};
1636PNAME(mout_aclk_disp_222_p) = {"mout_mediatop_pll_user", "mout_disp_disp_222"};
1637PNAME(mout_disp_media_pixel_p) = {"mout_mediatop_pll_user",
1638 "mout_bustop_pll_user"};
1639PNAME(mout_sclk_disp_pixel_p) = {"mout_disp_pll", "mout_disp_media_pixel"};
1640PNAME(mout_bus_bustop_400_p) = {"mout_bustop_pll_user", "mout_memtop_pll_user"};
1641PNAME(mout_bus_bustop_100_p) = {"mout_bustop_pll_user", "mout_memtop_pll_user"};
1642PNAME(mout_sclk_peri_spi_clk_p) = {"fin_pll", "mout_bustop_pll_user"};
1643PNAME(mout_sclk_peri_uart_uclk_p) = {"fin_pll", "mout_bustop_pll_user"};
1644PNAME(mout_sclk_fsys_usb_p) = {"fin_pll", "mout_bustop_pll_user"};
1645PNAME(mout_sclk_fsys_mmc_sdclkin_a_p) = {"fin_pll", "mout_bustop_pll_user"};
1646PNAME(mout_sclk_fsys_mmc0_sdclkin_b_p) = {"mout_sclk_fsys_mmc0_sdclkin_a",
1647 "mout_mediatop_pll_user"};
1648PNAME(mout_sclk_fsys_mmc1_sdclkin_b_p) = {"mout_sclk_fsys_mmc1_sdclkin_a",
1649 "mout_mediatop_pll_user"};
1650PNAME(mout_sclk_fsys_mmc2_sdclkin_b_p) = {"mout_sclk_fsys_mmc2_sdclkin_a",
1651 "mout_mediatop_pll_user"};
1652
1653struct samsung_mux_clock top_mux_clks[] __initdata = {
1654 MUX(TOP_MOUT_MEDIATOP_PLL_USER, "mout_mediatop_pll_user",
1655 mout_mediatop_pll_user_p,
1656 MUX_SEL_TOP_PLL0, 0, 1),
1657 MUX(TOP_MOUT_MEMTOP_PLL_USER, "mout_memtop_pll_user",
1658 mout_memtop_pll_user_p,
1659 MUX_SEL_TOP_PLL0, 4, 1),
1660 MUX(TOP_MOUT_BUSTOP_PLL_USER, "mout_bustop_pll_user",
1661 mout_bustop_pll_user_p,
1662 MUX_SEL_TOP_PLL0, 8, 1),
1663 MUX(TOP_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p,
1664 MUX_SEL_TOP_PLL0, 12, 1),
1665 MUX(TOP_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p,
1666 MUX_SEL_TOP_PLL0, 16, 1),
1667 MUX(TOP_MOUT_AUDTOP_PLL_USER, "mout_audtop_pll_user",
1668 mout_audtop_pll_user_p,
1669 MUX_SEL_TOP_PLL0, 24, 1),
1670
1671 MUX(TOP_MOUT_DISP_DISP_333, "mout_disp_disp_333", mout_disp_disp_333_p,
1672 MUX_SEL_TOP_DISP0, 0, 1),
1673 MUX(TOP_MOUT_ACLK_DISP_333, "mout_aclk_disp_333", mout_aclk_disp_333_p,
1674 MUX_SEL_TOP_DISP0, 8, 1),
1675 MUX(TOP_MOUT_DISP_DISP_222, "mout_disp_disp_222", mout_disp_disp_222_p,
1676 MUX_SEL_TOP_DISP0, 12, 1),
1677 MUX(TOP_MOUT_ACLK_DISP_222, "mout_aclk_disp_222", mout_aclk_disp_222_p,
1678 MUX_SEL_TOP_DISP0, 20, 1),
1679
1680 MUX(TOP_MOUT_FIMD1, "mout_sclk_disp_pixel", mout_sclk_disp_pixel_p,
1681 MUX_SEL_TOP_DISP1, 0, 1),
1682 MUX(TOP_MOUT_DISP_MEDIA_PIXEL, "mout_disp_media_pixel",
1683 mout_disp_media_pixel_p,
1684 MUX_SEL_TOP_DISP1, 8, 1),
1685
1686 MUX(TOP_MOUT_SCLK_PERI_SPI2_CLK, "mout_sclk_peri_spi2_clk",
1687 mout_sclk_peri_spi_clk_p,
1688 MUX_SEL_TOP_PERI1, 0, 1),
1689 MUX(TOP_MOUT_SCLK_PERI_SPI1_CLK, "mout_sclk_peri_spi1_clk",
1690 mout_sclk_peri_spi_clk_p,
1691 MUX_SEL_TOP_PERI1, 4, 1),
1692 MUX(TOP_MOUT_SCLK_PERI_SPI0_CLK, "mout_sclk_peri_spi0_clk",
1693 mout_sclk_peri_spi_clk_p,
1694 MUX_SEL_TOP_PERI1, 8, 1),
1695 MUX(TOP_MOUT_SCLK_PERI_UART1_UCLK, "mout_sclk_peri_uart1_uclk",
1696 mout_sclk_peri_uart_uclk_p,
1697 MUX_SEL_TOP_PERI1, 12, 1),
1698 MUX(TOP_MOUT_SCLK_PERI_UART2_UCLK, "mout_sclk_peri_uart2_uclk",
1699 mout_sclk_peri_uart_uclk_p,
1700 MUX_SEL_TOP_PERI1, 16, 1),
1701 MUX(TOP_MOUT_SCLK_PERI_UART0_UCLK, "mout_sclk_peri_uart0_uclk",
1702 mout_sclk_peri_uart_uclk_p,
1703 MUX_SEL_TOP_PERI1, 20, 1),
1704
1705
1706 MUX(TOP_MOUT_BUS1_BUSTOP_400, "mout_bus1_bustop_400",
1707 mout_bus_bustop_400_p,
1708 MUX_SEL_TOP_BUS, 0, 1),
1709 MUX(TOP_MOUT_BUS1_BUSTOP_100, "mout_bus1_bustop_100",
1710 mout_bus_bustop_100_p,
1711 MUX_SEL_TOP_BUS, 4, 1),
1712 MUX(TOP_MOUT_BUS2_BUSTOP_100, "mout_bus2_bustop_100",
1713 mout_bus_bustop_100_p,
1714 MUX_SEL_TOP_BUS, 8, 1),
1715 MUX(TOP_MOUT_BUS2_BUSTOP_400, "mout_bus2_bustop_400",
1716 mout_bus_bustop_400_p,
1717 MUX_SEL_TOP_BUS, 12, 1),
1718 MUX(TOP_MOUT_BUS3_BUSTOP_400, "mout_bus3_bustop_400",
1719 mout_bus_bustop_400_p,
1720 MUX_SEL_TOP_BUS, 16, 1),
1721 MUX(TOP_MOUT_BUS3_BUSTOP_100, "mout_bus3_bustop_100",
1722 mout_bus_bustop_100_p,
1723 MUX_SEL_TOP_BUS, 20, 1),
1724 MUX(TOP_MOUT_BUS4_BUSTOP_400, "mout_bus4_bustop_400",
1725 mout_bus_bustop_400_p,
1726 MUX_SEL_TOP_BUS, 24, 1),
1727 MUX(TOP_MOUT_BUS4_BUSTOP_100, "mout_bus4_bustop_100",
1728 mout_bus_bustop_100_p,
1729 MUX_SEL_TOP_BUS, 28, 1),
1730
1731 MUX(TOP_MOUT_SCLK_FSYS_USB, "mout_sclk_fsys_usb",
1732 mout_sclk_fsys_usb_p,
1733 MUX_SEL_TOP_FSYS, 0, 1),
1734 MUX(TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A, "mout_sclk_fsys_mmc2_sdclkin_a",
1735 mout_sclk_fsys_mmc_sdclkin_a_p,
1736 MUX_SEL_TOP_FSYS, 4, 1),
1737 MUX(TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_B, "mout_sclk_fsys_mmc2_sdclkin_b",
1738 mout_sclk_fsys_mmc2_sdclkin_b_p,
1739 MUX_SEL_TOP_FSYS, 8, 1),
1740 MUX(TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A, "mout_sclk_fsys_mmc1_sdclkin_a",
1741 mout_sclk_fsys_mmc_sdclkin_a_p,
1742 MUX_SEL_TOP_FSYS, 12, 1),
1743 MUX(TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_B, "mout_sclk_fsys_mmc1_sdclkin_b",
1744 mout_sclk_fsys_mmc1_sdclkin_b_p,
1745 MUX_SEL_TOP_FSYS, 16, 1),
1746 MUX(TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A, "mout_sclk_fsys_mmc0_sdclkin_a",
1747 mout_sclk_fsys_mmc_sdclkin_a_p,
1748 MUX_SEL_TOP_FSYS, 20, 1),
1749 MUX(TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_B, "mout_sclk_fsys_mmc0_sdclkin_b",
1750 mout_sclk_fsys_mmc0_sdclkin_b_p,
1751 MUX_SEL_TOP_FSYS, 24, 1),
1752
1753 MUX(TOP_MOUT_ISP1_MEDIA_400, "mout_isp1_media_400",
1754 mout_isp1_media_400_p,
1755 MUX_SEL_TOP_ISP10, 4, 1),
1756 MUX(TOP_MOUT_ACLK_ISP1_400, "mout_aclk_isp1_400", mout_aclk_isp1_400_p,
1757 MUX_SEL_TOP_ISP10, 8 , 1),
1758 MUX(TOP_MOUT_ISP1_MEDIA_266, "mout_isp1_media_266",
1759 mout_isp1_media_266_p,
1760 MUX_SEL_TOP_ISP10, 16, 1),
1761 MUX(TOP_MOUT_ACLK_ISP1_266, "mout_aclk_isp1_266", mout_aclk_isp1_266_p,
1762 MUX_SEL_TOP_ISP10, 20, 1),
1763
1764 MUX(TOP_MOUT_SCLK_ISP1_SPI0, "mout_sclk_isp1_spi0", mout_sclk_isp_spi_p,
1765 MUX_SEL_TOP_ISP11, 4, 1),
1766 MUX(TOP_MOUT_SCLK_ISP1_SPI1, "mout_sclk_isp1_spi1", mout_sclk_isp_spi_p,
1767 MUX_SEL_TOP_ISP11, 8, 1),
1768 MUX(TOP_MOUT_SCLK_ISP1_UART, "mout_sclk_isp1_uart",
1769 mout_sclk_isp_uart_p,
1770 MUX_SEL_TOP_ISP11, 12, 1),
1771 MUX(TOP_MOUT_SCLK_ISP1_SENSOR0, "mout_sclk_isp1_sensor0",
1772 mout_sclk_isp_sensor_p,
1773 MUX_SEL_TOP_ISP11, 16, 1),
1774 MUX(TOP_MOUT_SCLK_ISP1_SENSOR1, "mout_sclk_isp1_sensor1",
1775 mout_sclk_isp_sensor_p,
1776 MUX_SEL_TOP_ISP11, 20, 1),
1777 MUX(TOP_MOUT_SCLK_ISP1_SENSOR2, "mout_sclk_isp1_sensor2",
1778 mout_sclk_isp_sensor_p,
1779 MUX_SEL_TOP_ISP11, 24, 1),
1780
1781 MUX(TOP_MOUT_MFC_BUSTOP_333, "mout_mfc_bustop_333",
1782 mout_mfc_bustop_333_p,
1783 MUX_SEL_TOP_MFC, 4, 1),
1784 MUX(TOP_MOUT_ACLK_MFC_333, "mout_aclk_mfc_333", mout_aclk_mfc_333_p,
1785 MUX_SEL_TOP_MFC, 8, 1),
1786
1787 MUX(TOP_MOUT_G2D_BUSTOP_333, "mout_g2d_bustop_333",
1788 mout_g2d_bustop_333_p,
1789 MUX_SEL_TOP_G2D, 4, 1),
1790 MUX(TOP_MOUT_ACLK_G2D_333, "mout_aclk_g2d_333", mout_aclk_g2d_333_p,
1791 MUX_SEL_TOP_G2D, 8, 1),
1792
1793 MUX(TOP_MOUT_M2M_MEDIATOP_400, "mout_m2m_mediatop_400",
1794 mout_m2m_mediatop_400_p,
1795 MUX_SEL_TOP_GSCL, 0, 1),
1796 MUX(TOP_MOUT_ACLK_GSCL_400, "mout_aclk_gscl_400",
1797 mout_aclk_gscl_400_p,
1798 MUX_SEL_TOP_GSCL, 4, 1),
1799 MUX(TOP_MOUT_GSCL_BUSTOP_333, "mout_gscl_bustop_333",
1800 mout_gscl_bustop_333_p,
1801 MUX_SEL_TOP_GSCL, 8, 1),
1802 MUX(TOP_MOUT_ACLK_GSCL_333, "mout_aclk_gscl_333",
1803 mout_aclk_gscl_333_p,
1804 MUX_SEL_TOP_GSCL, 12, 1),
1805 MUX(TOP_MOUT_GSCL_BUSTOP_FIMC, "mout_gscl_bustop_fimc",
1806 mout_gscl_bustop_fimc_p,
1807 MUX_SEL_TOP_GSCL, 16, 1),
1808 MUX(TOP_MOUT_ACLK_GSCL_FIMC, "mout_aclk_gscl_fimc",
1809 mout_aclk_gscl_fimc_p,
1810 MUX_SEL_TOP_GSCL, 20, 1),
1811};
1812
1813struct samsung_div_clock top_div_clks[] __initdata = {
1814 DIV(TOP_DOUT_ACLK_G2D_333, "dout_aclk_g2d_333", "mout_aclk_g2d_333",
1815 DIV_TOP_G2D_MFC, 0, 3),
1816 DIV(TOP_DOUT_ACLK_MFC_333, "dout_aclk_mfc_333", "mout_aclk_mfc_333",
1817 DIV_TOP_G2D_MFC, 4, 3),
1818
1819 DIV(TOP_DOUT_ACLK_GSCL_333, "dout_aclk_gscl_333", "mout_aclk_gscl_333",
1820 DIV_TOP_GSCL_ISP0, 0, 3),
1821 DIV(TOP_DOUT_ACLK_GSCL_400, "dout_aclk_gscl_400", "mout_aclk_gscl_400",
1822 DIV_TOP_GSCL_ISP0, 4, 3),
1823 DIV(TOP_DOUT_ACLK_GSCL_FIMC, "dout_aclk_gscl_fimc",
1824 "mout_aclk_gscl_fimc", DIV_TOP_GSCL_ISP0, 8, 3),
1825 DIV(TOP_DOUT_SCLK_ISP1_SENSOR0_A, "dout_sclk_isp1_sensor0_a",
1826 "mout_aclk_gscl_fimc", DIV_TOP_GSCL_ISP0, 16, 4),
1827 DIV(TOP_DOUT_SCLK_ISP1_SENSOR1_A, "dout_sclk_isp1_sensor1_a",
1828 "mout_aclk_gscl_400", DIV_TOP_GSCL_ISP0, 20, 4),
1829 DIV(TOP_DOUT_SCLK_ISP1_SENSOR2_A, "dout_sclk_isp1_sensor2_a",
1830 "mout_aclk_gscl_fimc", DIV_TOP_GSCL_ISP0, 24, 4),
1831
1832 DIV(TOP_DOUT_ACLK_ISP1_266, "dout_aclk_isp1_266", "mout_aclk_isp1_266",
1833 DIV_TOP_ISP10, 0, 3),
1834 DIV(TOP_DOUT_ACLK_ISP1_400, "dout_aclk_isp1_400", "mout_aclk_isp1_400",
1835 DIV_TOP_ISP10, 4, 3),
1836 DIV(TOP_DOUT_SCLK_ISP1_SPI0_A, "dout_sclk_isp1_spi0_a",
1837 "mout_sclk_isp1_spi0", DIV_TOP_ISP10, 12, 4),
1838 DIV(TOP_DOUT_SCLK_ISP1_SPI0_B, "dout_sclk_isp1_spi0_b",
1839 "dout_sclk_isp1_spi0_a", DIV_TOP_ISP10, 16, 8),
1840
1841 DIV(TOP_DOUT_SCLK_ISP1_SPI1_A, "dout_sclk_isp1_spi1_a",
1842 "mout_sclk_isp1_spi1", DIV_TOP_ISP11, 0, 4),
1843 DIV(TOP_DOUT_SCLK_ISP1_SPI1_B, "dout_sclk_isp1_spi1_b",
1844 "dout_sclk_isp1_spi1_a", DIV_TOP_ISP11, 4, 8),
1845 DIV(TOP_DOUT_SCLK_ISP1_UART, "dout_sclk_isp1_uart",
1846 "mout_sclk_isp1_uart", DIV_TOP_ISP11, 12, 4),
1847 DIV(TOP_DOUT_SCLK_ISP1_SENSOR0_B, "dout_sclk_isp1_sensor0_b",
1848 "dout_sclk_isp1_sensor0_a", DIV_TOP_ISP11, 16, 4),
1849 DIV(TOP_DOUT_SCLK_ISP1_SENSOR1_B, "dout_sclk_isp1_sensor1_b",
1850 "dout_sclk_isp1_sensor1_a", DIV_TOP_ISP11, 20, 4),
1851 DIV(TOP_DOUT_SCLK_ISP1_SENSOR2_B, "dout_sclk_isp1_sensor2_b",
1852 "dout_sclk_isp1_sensor2_a", DIV_TOP_ISP11, 24, 4),
1853
1854 DIV(TOP_DOUTTOP__SCLK_HPM_TARGETCLK, "dout_sclk_hpm_targetclk",
1855 "mout_bustop_pll_user", DIV_TOP_HPM, 0, 3),
1856
1857 DIV(TOP_DOUT_ACLK_DISP_333, "dout_aclk_disp_333", "mout_aclk_disp_333",
1858 DIV_TOP_DISP, 0, 3),
1859 DIV(TOP_DOUT_ACLK_DISP_222, "dout_aclk_disp_222", "mout_aclk_disp_222",
1860 DIV_TOP_DISP, 4, 3),
1861 DIV(TOP_DOUT_SCLK_DISP_PIXEL, "dout_sclk_disp_pixel",
1862 "mout_sclk_disp_pixel", DIV_TOP_DISP, 8, 3),
1863
1864 DIV(TOP_DOUT_ACLK_BUS1_400, "dout_aclk_bus1_400",
1865 "mout_bus1_bustop_400", DIV_TOP_BUS, 0, 3),
1866 DIV(TOP_DOUT_ACLK_BUS1_100, "dout_aclk_bus1_100",
1867 "mout_bus1_bustop_100", DIV_TOP_BUS, 4, 4),
1868 DIV(TOP_DOUT_ACLK_BUS2_400, "dout_aclk_bus2_400",
1869 "mout_bus2_bustop_400", DIV_TOP_BUS, 8, 3),
1870 DIV(TOP_DOUT_ACLK_BUS2_100, "dout_aclk_bus2_100",
1871 "mout_bus2_bustop_100", DIV_TOP_BUS, 12, 4),
1872 DIV(TOP_DOUT_ACLK_BUS3_400, "dout_aclk_bus3_400",
1873 "mout_bus3_bustop_400", DIV_TOP_BUS, 16, 3),
1874 DIV(TOP_DOUT_ACLK_BUS3_100, "dout_aclk_bus3_100",
1875 "mout_bus3_bustop_100", DIV_TOP_BUS, 20, 4),
1876 DIV(TOP_DOUT_ACLK_BUS4_400, "dout_aclk_bus4_400",
1877 "mout_bus4_bustop_400", DIV_TOP_BUS, 24, 3),
1878 DIV(TOP_DOUT_ACLK_BUS4_100, "dout_aclk_bus4_100",
1879 "mout_bus4_bustop_100", DIV_TOP_BUS, 28, 4),
1880
1881 DIV(TOP_DOUT_SCLK_PERI_SPI0_A, "dout_sclk_peri_spi0_a",
1882 "mout_sclk_peri_spi0_clk", DIV_TOP_PERI0, 4, 4),
1883 DIV(TOP_DOUT_SCLK_PERI_SPI0_B, "dout_sclk_peri_spi0_b",
1884 "dout_sclk_peri_spi0_a", DIV_TOP_PERI0, 8, 8),
1885 DIV(TOP_DOUT_SCLK_PERI_SPI1_A, "dout_sclk_peri_spi1_a",
1886 "mout_sclk_peri_spi1_clk", DIV_TOP_PERI0, 16, 4),
1887 DIV(TOP_DOUT_SCLK_PERI_SPI1_B, "dout_sclk_peri_spi1_b",
1888 "dout_sclk_peri_spi1_a", DIV_TOP_PERI0, 20, 8),
1889
1890 DIV(TOP_DOUT_SCLK_PERI_SPI2_A, "dout_sclk_peri_spi2_a",
1891 "mout_sclk_peri_spi2_clk", DIV_TOP_PERI1, 0, 4),
1892 DIV(TOP_DOUT_SCLK_PERI_SPI2_B, "dout_sclk_peri_spi2_b",
1893 "dout_sclk_peri_spi2_a", DIV_TOP_PERI1, 4, 8),
1894 DIV(TOP_DOUT_SCLK_PERI_UART1, "dout_sclk_peri_uart1",
1895 "mout_sclk_peri_uart1_uclk", DIV_TOP_PERI1, 16, 4),
1896 DIV(TOP_DOUT_SCLK_PERI_UART2, "dout_sclk_peri_uart2",
1897 "mout_sclk_peri_uart2_uclk", DIV_TOP_PERI1, 20, 4),
1898 DIV(TOP_DOUT_SCLK_PERI_UART0, "dout_sclk_peri_uart0",
1899 "mout_sclk_peri_uart0_uclk", DIV_TOP_PERI1, 24, 4),
1900
1901 DIV(TOP_DOUT_ACLK_PERI_66, "dout_aclk_peri_66", "mout_bustop_pll_user",
1902 DIV_TOP_PERI2, 20, 4),
1903 DIV(TOP_DOUT_ACLK_PERI_AUD, "dout_aclk_peri_aud",
1904 "mout_audtop_pll_user", DIV_TOP_PERI2, 24, 3),
1905
1906 DIV(TOP_DOUT_ACLK_FSYS_200, "dout_aclk_fsys_200",
1907 "mout_bustop_pll_user", DIV_TOP_FSYS0, 0, 3),
1908 DIV(TOP_DOUT_SCLK_FSYS_USBDRD30_SUSPEND_CLK,
1909 "dout_sclk_fsys_usbdrd30_suspend_clk",
1910 "mout_sclk_fsys_usb", DIV_TOP_FSYS0, 4, 4),
1911 DIV(TOP_DOUT_SCLK_FSYS_MMC0_SDCLKIN_A, "dout_sclk_fsys_mmc0_sdclkin_a",
1912 "mout_sclk_fsys_mmc0_sdclkin_b",
1913 DIV_TOP_FSYS0, 12, 4),
1914 DIV(TOP_DOUT_SCLK_FSYS_MMC0_SDCLKIN_B, "dout_sclk_fsys_mmc0_sdclkin_b",
1915 "dout_sclk_fsys_mmc0_sdclkin_a",
1916 DIV_TOP_FSYS0, 16, 8),
1917
1918
1919 DIV(TOP_DOUT_SCLK_FSYS_MMC1_SDCLKIN_A, "dout_sclk_fsys_mmc1_sdclkin_a",
1920 "mout_sclk_fsys_mmc1_sdclkin_b",
1921 DIV_TOP_FSYS1, 0, 4),
1922 DIV(TOP_DOUT_SCLK_FSYS_MMC1_SDCLKIN_B, "dout_sclk_fsys_mmc1_sdclkin_b",
1923 "dout_sclk_fsys_mmc1_sdclkin_a",
1924 DIV_TOP_FSYS1, 4, 8),
1925 DIV(TOP_DOUT_SCLK_FSYS_MMC2_SDCLKIN_A, "dout_sclk_fsys_mmc2_sdclkin_a",
1926 "mout_sclk_fsys_mmc2_sdclkin_b",
1927 DIV_TOP_FSYS1, 12, 4),
1928 DIV(TOP_DOUT_SCLK_FSYS_MMC2_SDCLKIN_B, "dout_sclk_fsys_mmc2_sdclkin_b",
1929 "dout_sclk_fsys_mmc2_sdclkin_a",
1930 DIV_TOP_FSYS1, 16, 8),
1931
1932};
1933
1934struct samsung_gate_clock top_gate_clks[] __initdata = {
1935 GATE(TOP_SCLK_MMC0, "sclk_fsys_mmc0_sdclkin",
1936 "dout_sclk_fsys_mmc0_sdclkin_b",
1937 EN_SCLK_TOP, 7, CLK_SET_RATE_PARENT, 0),
1938 GATE(TOP_SCLK_MMC1, "sclk_fsys_mmc1_sdclkin",
1939 "dout_sclk_fsys_mmc1_sdclkin_b",
1940 EN_SCLK_TOP, 8, CLK_SET_RATE_PARENT, 0),
1941 GATE(TOP_SCLK_MMC2, "sclk_fsys_mmc2_sdclkin",
1942 "dout_sclk_fsys_mmc2_sdclkin_b",
1943 EN_SCLK_TOP, 9, CLK_SET_RATE_PARENT, 0),
1944 GATE(TOP_SCLK_FIMD1, "sclk_disp_pixel", "dout_sclk_disp_pixel",
1945 EN_ACLK_TOP, 10, CLK_IGNORE_UNUSED |
1946 CLK_SET_RATE_PARENT, 0),
1947};
1948
1949static struct samsung_pll_clock top_pll_clks[] __initdata = {
1950 PLL(pll_2550xx, TOP_FOUT_DISP_PLL, "fout_disp_pll", "fin_pll",
1951 DISP_PLL_LOCK, DISP_PLL_CON0,
1952 pll2550_24mhz_tbl),
1953 PLL(pll_2650xx, TOP_FOUT_AUD_PLL, "fout_aud_pll", "fin_pll",
1954 AUD_PLL_LOCK, AUD_PLL_CON0,
1955 pll2650_24mhz_tbl),
1956};
1957
1958static void __init exynos5260_clk_top_init(struct device_node *np)
1959{
1960 struct exynos5260_cmu_info cmu = {0};
1961
1962 cmu.pll_clks = top_pll_clks;
1963 cmu.nr_pll_clks = ARRAY_SIZE(top_pll_clks);
1964 cmu.mux_clks = top_mux_clks;
1965 cmu.nr_mux_clks = ARRAY_SIZE(top_mux_clks);
1966 cmu.div_clks = top_div_clks;
1967 cmu.nr_div_clks = ARRAY_SIZE(top_div_clks);
1968 cmu.gate_clks = top_gate_clks;
1969 cmu.nr_gate_clks = ARRAY_SIZE(top_gate_clks);
1970 cmu.fixed_clks = fixed_rate_clks;
1971 cmu.nr_fixed_clks = ARRAY_SIZE(fixed_rate_clks);
1972 cmu.nr_clk_ids = TOP_NR_CLK;
1973 cmu.clk_regs = top_clk_regs;
1974 cmu.nr_clk_regs = ARRAY_SIZE(top_clk_regs);
1975
1976 exynos5260_cmu_register_one(np, &cmu);
1977}
1978
1979CLK_OF_DECLARE(exynos5260_clk_top, "samsung,exynos5260-clock-top",
1980 exynos5260_clk_top_init);
diff --git a/drivers/clk/samsung/clk-exynos5260.h b/drivers/clk/samsung/clk-exynos5260.h
new file mode 100644
index 000000000000..d739716d6ea1
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos5260.h
@@ -0,0 +1,459 @@
1/*
2 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
3 * Author: Rahul Sharma <rahul.sharma@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * Common Clock Framework support for Exynos5260 SoC.
10 */
11
12#ifndef __CLK_EXYNOS5260_H
13#define __CLK_EXYNOS5260_H
14
15/*
16*Registers for CMU_AUD
17*/
18#define MUX_SEL_AUD 0x0200
19#define MUX_ENABLE_AUD 0x0300
20#define MUX_STAT_AUD 0x0400
21#define MUX_IGNORE_AUD 0x0500
22#define DIV_AUD0 0x0600
23#define DIV_AUD1 0x0604
24#define DIV_STAT_AUD0 0x0700
25#define DIV_STAT_AUD1 0x0704
26#define EN_ACLK_AUD 0x0800
27#define EN_PCLK_AUD 0x0900
28#define EN_SCLK_AUD 0x0a00
29#define EN_IP_AUD 0x0b00
30
31/*
32*Registers for CMU_DISP
33*/
34#define MUX_SEL_DISP0 0x0200
35#define MUX_SEL_DISP1 0x0204
36#define MUX_SEL_DISP2 0x0208
37#define MUX_SEL_DISP3 0x020C
38#define MUX_SEL_DISP4 0x0210
39#define MUX_ENABLE_DISP0 0x0300
40#define MUX_ENABLE_DISP1 0x0304
41#define MUX_ENABLE_DISP2 0x0308
42#define MUX_ENABLE_DISP3 0x030c
43#define MUX_ENABLE_DISP4 0x0310
44#define MUX_STAT_DISP0 0x0400
45#define MUX_STAT_DISP1 0x0404
46#define MUX_STAT_DISP2 0x0408
47#define MUX_STAT_DISP3 0x040c
48#define MUX_STAT_DISP4 0x0410
49#define MUX_IGNORE_DISP0 0x0500
50#define MUX_IGNORE_DISP1 0x0504
51#define MUX_IGNORE_DISP2 0x0508
52#define MUX_IGNORE_DISP3 0x050c
53#define MUX_IGNORE_DISP4 0x0510
54#define DIV_DISP 0x0600
55#define DIV_STAT_DISP 0x0700
56#define EN_ACLK_DISP 0x0800
57#define EN_PCLK_DISP 0x0900
58#define EN_SCLK_DISP0 0x0a00
59#define EN_SCLK_DISP1 0x0a04
60#define EN_IP_DISP 0x0b00
61#define EN_IP_DISP_BUS 0x0b04
62
63
64/*
65*Registers for CMU_EGL
66*/
67#define EGL_PLL_LOCK 0x0000
68#define EGL_DPLL_LOCK 0x0004
69#define EGL_PLL_CON0 0x0100
70#define EGL_PLL_CON1 0x0104
71#define EGL_PLL_FREQ_DET 0x010c
72#define EGL_DPLL_CON0 0x0110
73#define EGL_DPLL_CON1 0x0114
74#define EGL_DPLL_FREQ_DET 0x011c
75#define MUX_SEL_EGL 0x0200
76#define MUX_ENABLE_EGL 0x0300
77#define MUX_STAT_EGL 0x0400
78#define DIV_EGL 0x0600
79#define DIV_EGL_PLL_FDET 0x0604
80#define DIV_STAT_EGL 0x0700
81#define DIV_STAT_EGL_PLL_FDET 0x0704
82#define EN_ACLK_EGL 0x0800
83#define EN_PCLK_EGL 0x0900
84#define EN_SCLK_EGL 0x0a00
85#define EN_IP_EGL 0x0b00
86#define CLKOUT_CMU_EGL 0x0c00
87#define CLKOUT_CMU_EGL_DIV_STAT 0x0c04
88#define ARMCLK_STOPCTRL 0x1000
89#define EAGLE_EMA_CTRL 0x1008
90#define EAGLE_EMA_STATUS 0x100c
91#define PWR_CTRL 0x1020
92#define PWR_CTRL2 0x1024
93#define CLKSTOP_CTRL 0x1028
94#define INTR_SPREAD_EN 0x1080
95#define INTR_SPREAD_USE_STANDBYWFI 0x1084
96#define INTR_SPREAD_BLOCKING_DURATION 0x1088
97#define CMU_EGL_SPARE0 0x2000
98#define CMU_EGL_SPARE1 0x2004
99#define CMU_EGL_SPARE2 0x2008
100#define CMU_EGL_SPARE3 0x200c
101#define CMU_EGL_SPARE4 0x2010
102
103/*
104*Registers for CMU_FSYS
105*/
106
107#define MUX_SEL_FSYS0 0x0200
108#define MUX_SEL_FSYS1 0x0204
109#define MUX_ENABLE_FSYS0 0x0300
110#define MUX_ENABLE_FSYS1 0x0304
111#define MUX_STAT_FSYS0 0x0400
112#define MUX_STAT_FSYS1 0x0404
113#define MUX_IGNORE_FSYS0 0x0500
114#define MUX_IGNORE_FSYS1 0x0504
115#define EN_ACLK_FSYS 0x0800
116#define EN_ACLK_FSYS_SECURE_RTIC 0x0804
117#define EN_ACLK_FSYS_SECURE_SMMU_RTIC 0x0808
118#define EN_PCLK_FSYS 0x0900
119#define EN_SCLK_FSYS 0x0a00
120#define EN_IP_FSYS 0x0b00
121#define EN_IP_FSYS_SECURE_RTIC 0x0b04
122#define EN_IP_FSYS_SECURE_SMMU_RTIC 0x0b08
123
124/*
125*Registers for CMU_G2D
126*/
127
128#define MUX_SEL_G2D 0x0200
129#define MUX_ENABLE_G2D 0x0300
130#define MUX_STAT_G2D 0x0400
131#define DIV_G2D 0x0600
132#define DIV_STAT_G2D 0x0700
133#define EN_ACLK_G2D 0x0800
134#define EN_ACLK_G2D_SECURE_SSS 0x0804
135#define EN_ACLK_G2D_SECURE_SLIM_SSS 0x0808
136#define EN_ACLK_G2D_SECURE_SMMU_SLIM_SSS 0x080c
137#define EN_ACLK_G2D_SECURE_SMMU_SSS 0x0810
138#define EN_ACLK_G2D_SECURE_SMMU_MDMA 0x0814
139#define EN_ACLK_G2D_SECURE_SMMU_G2D 0x0818
140#define EN_PCLK_G2D 0x0900
141#define EN_PCLK_G2D_SECURE_SMMU_SLIM_SSS 0x0904
142#define EN_PCLK_G2D_SECURE_SMMU_SSS 0x0908
143#define EN_PCLK_G2D_SECURE_SMMU_MDMA 0x090c
144#define EN_PCLK_G2D_SECURE_SMMU_G2D 0x0910
145#define EN_IP_G2D 0x0b00
146#define EN_IP_G2D_SECURE_SSS 0x0b04
147#define EN_IP_G2D_SECURE_SLIM_SSS 0x0b08
148#define EN_IP_G2D_SECURE_SMMU_SLIM_SSS 0x0b0c
149#define EN_IP_G2D_SECURE_SMMU_SSS 0x0b10
150#define EN_IP_G2D_SECURE_SMMU_MDMA 0x0b14
151#define EN_IP_G2D_SECURE_SMMU_G2D 0x0b18
152
153/*
154*Registers for CMU_G3D
155*/
156
157#define G3D_PLL_LOCK 0x0000
158#define G3D_PLL_CON0 0x0100
159#define G3D_PLL_CON1 0x0104
160#define G3D_PLL_FDET 0x010c
161#define MUX_SEL_G3D 0x0200
162#define MUX_EN_G3D 0x0300
163#define MUX_STAT_G3D 0x0400
164#define MUX_IGNORE_G3D 0x0500
165#define DIV_G3D 0x0600
166#define DIV_G3D_PLL_FDET 0x0604
167#define DIV_STAT_G3D 0x0700
168#define DIV_STAT_G3D_PLL_FDET 0x0704
169#define EN_ACLK_G3D 0x0800
170#define EN_PCLK_G3D 0x0900
171#define EN_SCLK_G3D 0x0a00
172#define EN_IP_G3D 0x0b00
173#define CLKOUT_CMU_G3D 0x0c00
174#define CLKOUT_CMU_G3D_DIV_STAT 0x0c04
175#define G3DCLK_STOPCTRL 0x1000
176#define G3D_EMA_CTRL 0x1008
177#define G3D_EMA_STATUS 0x100c
178
179/*
180*Registers for CMU_GSCL
181*/
182
183#define MUX_SEL_GSCL 0x0200
184#define MUX_EN_GSCL 0x0300
185#define MUX_STAT_GSCL 0x0400
186#define MUX_IGNORE_GSCL 0x0500
187#define DIV_GSCL 0x0600
188#define DIV_STAT_GSCL 0x0700
189#define EN_ACLK_GSCL 0x0800
190#define EN_ACLK_GSCL_FIMC 0x0804
191#define EN_ACLK_GSCL_SECURE_SMMU_GSCL0 0x0808
192#define EN_ACLK_GSCL_SECURE_SMMU_GSCL1 0x080c
193#define EN_ACLK_GSCL_SECURE_SMMU_MSCL0 0x0810
194#define EN_ACLK_GSCL_SECURE_SMMU_MSCL1 0x0814
195#define EN_PCLK_GSCL 0x0900
196#define EN_PCLK_GSCL_FIMC 0x0904
197#define EN_PCLK_GSCL_SECURE_SMMU_GSCL0 0x0908
198#define EN_PCLK_GSCL_SECURE_SMMU_GSCL1 0x090c
199#define EN_PCLK_GSCL_SECURE_SMMU_MSCL0 0x0910
200#define EN_PCLK_GSCL_SECURE_SMMU_MSCL1 0x0914
201#define EN_SCLK_GSCL 0x0a00
202#define EN_SCLK_GSCL_FIMC 0x0a04
203#define EN_IP_GSCL 0x0b00
204#define EN_IP_GSCL_FIMC 0x0b04
205#define EN_IP_GSCL_SECURE_SMMU_GSCL0 0x0b08
206#define EN_IP_GSCL_SECURE_SMMU_GSCL1 0x0b0c
207#define EN_IP_GSCL_SECURE_SMMU_MSCL0 0x0b10
208#define EN_IP_GSCL_SECURE_SMMU_MSCL1 0x0b14
209
210/*
211*Registers for CMU_ISP
212*/
213#define MUX_SEL_ISP0 0x0200
214#define MUX_SEL_ISP1 0x0204
215#define MUX_ENABLE_ISP0 0x0300
216#define MUX_ENABLE_ISP1 0x0304
217#define MUX_STAT_ISP0 0x0400
218#define MUX_STAT_ISP1 0x0404
219#define MUX_IGNORE_ISP0 0x0500
220#define MUX_IGNORE_ISP1 0x0504
221#define DIV_ISP 0x0600
222#define DIV_STAT_ISP 0x0700
223#define EN_ACLK_ISP0 0x0800
224#define EN_ACLK_ISP1 0x0804
225#define EN_PCLK_ISP0 0x0900
226#define EN_PCLK_ISP1 0x0904
227#define EN_SCLK_ISP 0x0a00
228#define EN_IP_ISP0 0x0b00
229#define EN_IP_ISP1 0x0b04
230
231/*
232*Registers for CMU_KFC
233*/
234#define KFC_PLL_LOCK 0x0000
235#define KFC_PLL_CON0 0x0100
236#define KFC_PLL_CON1 0x0104
237#define KFC_PLL_FDET 0x010c
238#define MUX_SEL_KFC0 0x0200
239#define MUX_SEL_KFC2 0x0208
240#define MUX_ENABLE_KFC0 0x0300
241#define MUX_ENABLE_KFC2 0x0308
242#define MUX_STAT_KFC0 0x0400
243#define MUX_STAT_KFC2 0x0408
244#define DIV_KFC 0x0600
245#define DIV_KFC_PLL_FDET 0x0604
246#define DIV_STAT_KFC 0x0700
247#define DIV_STAT_KFC_PLL_FDET 0x0704
248#define EN_ACLK_KFC 0x0800
249#define EN_PCLK_KFC 0x0900
250#define EN_SCLK_KFC 0x0a00
251#define EN_IP_KFC 0x0b00
252#define CLKOUT_CMU_KFC 0x0c00
253#define CLKOUT_CMU_KFC_DIV_STAT 0x0c04
254#define ARMCLK_STOPCTRL_KFC 0x1000
255#define ARM_EMA_CTRL 0x1008
256#define ARM_EMA_STATUS 0x100c
257#define PWR_CTRL_KFC 0x1020
258#define PWR_CTRL2_KFC 0x1024
259#define CLKSTOP_CTRL_KFC 0x1028
260#define INTR_SPREAD_ENABLE_KFC 0x1080
261#define INTR_SPREAD_USE_STANDBYWFI_KFC 0x1084
262#define INTR_SPREAD_BLOCKING_DURATION_KFC 0x1088
263#define CMU_KFC_SPARE0 0x2000
264#define CMU_KFC_SPARE1 0x2004
265#define CMU_KFC_SPARE2 0x2008
266#define CMU_KFC_SPARE3 0x200c
267#define CMU_KFC_SPARE4 0x2010
268
269/*
270*Registers for CMU_MFC
271*/
272#define MUX_SEL_MFC 0x0200
273#define MUX_ENABLE_MFC 0x0300
274#define MUX_STAT_MFC 0x0400
275#define DIV_MFC 0x0600
276#define DIV_STAT_MFC 0x0700
277#define EN_ACLK_MFC 0x0800
278#define EN_ACLK_SECURE_SMMU2_MFC 0x0804
279#define EN_PCLK_MFC 0x0900
280#define EN_PCLK_SECURE_SMMU2_MFC 0x0904
281#define EN_IP_MFC 0x0b00
282#define EN_IP_MFC_SECURE_SMMU2_MFC 0x0b04
283
284/*
285*Registers for CMU_MIF
286*/
287#define MEM_PLL_LOCK 0x0000
288#define BUS_PLL_LOCK 0x0004
289#define MEDIA_PLL_LOCK 0x0008
290#define MEM_PLL_CON0 0x0100
291#define MEM_PLL_CON1 0x0104
292#define MEM_PLL_FDET 0x010c
293#define BUS_PLL_CON0 0x0110
294#define BUS_PLL_CON1 0x0114
295#define BUS_PLL_FDET 0x011c
296#define MEDIA_PLL_CON0 0x0120
297#define MEDIA_PLL_CON1 0x0124
298#define MEDIA_PLL_FDET 0x012c
299#define MUX_SEL_MIF 0x0200
300#define MUX_ENABLE_MIF 0x0300
301#define MUX_STAT_MIF 0x0400
302#define MUX_IGNORE_MIF 0x0500
303#define DIV_MIF 0x0600
304#define DIV_MIF_PLL_FDET 0x0604
305#define DIV_STAT_MIF 0x0700
306#define DIV_STAT_MIF_PLL_FDET 0x0704
307#define EN_ACLK_MIF 0x0800
308#define EN_ACLK_MIF_SECURE_DREX1_TZ 0x0804
309#define EN_ACLK_MIF_SECURE_DREX0_TZ 0x0808
310#define EN_ACLK_MIF_SECURE_INTMEM 0x080c
311#define EN_PCLK_MIF 0x0900
312#define EN_PCLK_MIF_SECURE_MONOCNT 0x0904
313#define EN_PCLK_MIF_SECURE_RTC_APBIF 0x0908
314#define EN_PCLK_MIF_SECURE_DREX1_TZ 0x090c
315#define EN_PCLK_MIF_SECURE_DREX0_TZ 0x0910
316#define EN_SCLK_MIF 0x0a00
317#define EN_IP_MIF 0x0b00
318#define EN_IP_MIF_SECURE_MONOCNT 0x0b04
319#define EN_IP_MIF_SECURE_RTC_APBIF 0x0b08
320#define EN_IP_MIF_SECURE_DREX1_TZ 0x0b0c
321#define EN_IP_MIF_SECURE_DREX0_TZ 0x0b10
322#define EN_IP_MIF_SECURE_INTEMEM 0x0b14
323#define CLKOUT_CMU_MIF_DIV_STAT 0x0c04
324#define DREX_FREQ_CTRL 0x1000
325#define PAUSE 0x1004
326#define DDRPHY_LOCK_CTRL 0x1008
327#define CLKOUT_CMU_MIF 0xcb00
328
329/*
330*Registers for CMU_PERI
331*/
332#define MUX_SEL_PERI 0x0200
333#define MUX_SEL_PERI1 0x0204
334#define MUX_ENABLE_PERI 0x0300
335#define MUX_ENABLE_PERI1 0x0304
336#define MUX_STAT_PERI 0x0400
337#define MUX_STAT_PERI1 0x0404
338#define MUX_IGNORE_PERI 0x0500
339#define MUX_IGNORE_PERI1 0x0504
340#define DIV_PERI 0x0600
341#define DIV_STAT_PERI 0x0700
342#define EN_PCLK_PERI0 0x0800
343#define EN_PCLK_PERI1 0x0804
344#define EN_PCLK_PERI2 0x0808
345#define EN_PCLK_PERI3 0x080c
346#define EN_PCLK_PERI_SECURE_CHIPID 0x0810
347#define EN_PCLK_PERI_SECURE_PROVKEY0 0x0814
348#define EN_PCLK_PERI_SECURE_PROVKEY1 0x0818
349#define EN_PCLK_PERI_SECURE_SECKEY 0x081c
350#define EN_PCLK_PERI_SECURE_ANTIRBKCNT 0x0820
351#define EN_PCLK_PERI_SECURE_TOP_RTC 0x0824
352#define EN_PCLK_PERI_SECURE_TZPC 0x0828
353#define EN_SCLK_PERI 0x0a00
354#define EN_SCLK_PERI_SECURE_TOP_RTC 0x0a04
355#define EN_IP_PERI0 0x0b00
356#define EN_IP_PERI1 0x0b04
357#define EN_IP_PERI2 0x0b08
358#define EN_IP_PERI_SECURE_CHIPID 0x0b0c
359#define EN_IP_PERI_SECURE_PROVKEY0 0x0b10
360#define EN_IP_PERI_SECURE_PROVKEY1 0x0b14
361#define EN_IP_PERI_SECURE_SECKEY 0x0b18
362#define EN_IP_PERI_SECURE_ANTIRBKCNT 0x0b1c
363#define EN_IP_PERI_SECURE_TOP_RTC 0x0b20
364#define EN_IP_PERI_SECURE_TZPC 0x0b24
365
366/*
367*Registers for CMU_TOP
368*/
369#define DISP_PLL_LOCK 0x0000
370#define AUD_PLL_LOCK 0x0004
371#define DISP_PLL_CON0 0x0100
372#define DISP_PLL_CON1 0x0104
373#define DISP_PLL_FDET 0x0108
374#define AUD_PLL_CON0 0x0110
375#define AUD_PLL_CON1 0x0114
376#define AUD_PLL_CON2 0x0118
377#define AUD_PLL_FDET 0x011c
378#define MUX_SEL_TOP_PLL0 0x0200
379#define MUX_SEL_TOP_MFC 0x0204
380#define MUX_SEL_TOP_G2D 0x0208
381#define MUX_SEL_TOP_GSCL 0x020c
382#define MUX_SEL_TOP_ISP10 0x0214
383#define MUX_SEL_TOP_ISP11 0x0218
384#define MUX_SEL_TOP_DISP0 0x021c
385#define MUX_SEL_TOP_DISP1 0x0220
386#define MUX_SEL_TOP_BUS 0x0224
387#define MUX_SEL_TOP_PERI0 0x0228
388#define MUX_SEL_TOP_PERI1 0x022c
389#define MUX_SEL_TOP_FSYS 0x0230
390#define MUX_ENABLE_TOP_PLL0 0x0300
391#define MUX_ENABLE_TOP_MFC 0x0304
392#define MUX_ENABLE_TOP_G2D 0x0308
393#define MUX_ENABLE_TOP_GSCL 0x030c
394#define MUX_ENABLE_TOP_ISP10 0x0314
395#define MUX_ENABLE_TOP_ISP11 0x0318
396#define MUX_ENABLE_TOP_DISP0 0x031c
397#define MUX_ENABLE_TOP_DISP1 0x0320
398#define MUX_ENABLE_TOP_BUS 0x0324
399#define MUX_ENABLE_TOP_PERI0 0x0328
400#define MUX_ENABLE_TOP_PERI1 0x032c
401#define MUX_ENABLE_TOP_FSYS 0x0330
402#define MUX_STAT_TOP_PLL0 0x0400
403#define MUX_STAT_TOP_MFC 0x0404
404#define MUX_STAT_TOP_G2D 0x0408
405#define MUX_STAT_TOP_GSCL 0x040c
406#define MUX_STAT_TOP_ISP10 0x0414
407#define MUX_STAT_TOP_ISP11 0x0418
408#define MUX_STAT_TOP_DISP0 0x041c
409#define MUX_STAT_TOP_DISP1 0x0420
410#define MUX_STAT_TOP_BUS 0x0424
411#define MUX_STAT_TOP_PERI0 0x0428
412#define MUX_STAT_TOP_PERI1 0x042c
413#define MUX_STAT_TOP_FSYS 0x0430
414#define MUX_IGNORE_TOP_PLL0 0x0500
415#define MUX_IGNORE_TOP_MFC 0x0504
416#define MUX_IGNORE_TOP_G2D 0x0508
417#define MUX_IGNORE_TOP_GSCL 0x050c
418#define MUX_IGNORE_TOP_ISP10 0x0514
419#define MUX_IGNORE_TOP_ISP11 0x0518
420#define MUX_IGNORE_TOP_DISP0 0x051c
421#define MUX_IGNORE_TOP_DISP1 0x0520
422#define MUX_IGNORE_TOP_BUS 0x0524
423#define MUX_IGNORE_TOP_PERI0 0x0528
424#define MUX_IGNORE_TOP_PERI1 0x052c
425#define MUX_IGNORE_TOP_FSYS 0x0530
426#define DIV_TOP_G2D_MFC 0x0600
427#define DIV_TOP_GSCL_ISP0 0x0604
428#define DIV_TOP_ISP10 0x0608
429#define DIV_TOP_ISP11 0x060c
430#define DIV_TOP_DISP 0x0610
431#define DIV_TOP_BUS 0x0614
432#define DIV_TOP_PERI0 0x0618
433#define DIV_TOP_PERI1 0x061c
434#define DIV_TOP_PERI2 0x0620
435#define DIV_TOP_FSYS0 0x0624
436#define DIV_TOP_FSYS1 0x0628
437#define DIV_TOP_HPM 0x062c
438#define DIV_TOP_PLL_FDET 0x0630
439#define DIV_STAT_TOP_G2D_MFC 0x0700
440#define DIV_STAT_TOP_GSCL_ISP0 0x0704
441#define DIV_STAT_TOP_ISP10 0x0708
442#define DIV_STAT_TOP_ISP11 0x070c
443#define DIV_STAT_TOP_DISP 0x0710
444#define DIV_STAT_TOP_BUS 0x0714
445#define DIV_STAT_TOP_PERI0 0x0718
446#define DIV_STAT_TOP_PERI1 0x071c
447#define DIV_STAT_TOP_PERI2 0x0720
448#define DIV_STAT_TOP_FSYS0 0x0724
449#define DIV_STAT_TOP_FSYS1 0x0728
450#define DIV_STAT_TOP_HPM 0x072c
451#define DIV_STAT_TOP_PLL_FDET 0x0730
452#define EN_ACLK_TOP 0x0800
453#define EN_SCLK_TOP 0x0a00
454#define EN_IP_TOP 0x0b00
455#define CLKOUT_CMU_TOP 0x0c00
456#define CLKOUT_CMU_TOP_DIV_STAT 0x0c04
457
458#endif /*__CLK_EXYNOS5260_H */
459
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 60b26819bed5..9d7d7eed03fd 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -27,18 +27,24 @@
27#define DIV_CPU1 0x504 27#define DIV_CPU1 0x504
28#define GATE_BUS_CPU 0x700 28#define GATE_BUS_CPU 0x700
29#define GATE_SCLK_CPU 0x800 29#define GATE_SCLK_CPU 0x800
30#define CLKOUT_CMU_CPU 0xa00
31#define GATE_IP_G2D 0x8800
30#define CPLL_LOCK 0x10020 32#define CPLL_LOCK 0x10020
31#define DPLL_LOCK 0x10030 33#define DPLL_LOCK 0x10030
32#define EPLL_LOCK 0x10040 34#define EPLL_LOCK 0x10040
33#define RPLL_LOCK 0x10050 35#define RPLL_LOCK 0x10050
34#define IPLL_LOCK 0x10060 36#define IPLL_LOCK 0x10060
35#define SPLL_LOCK 0x10070 37#define SPLL_LOCK 0x10070
36#define VPLL_LOCK 0x10070 38#define VPLL_LOCK 0x10080
37#define MPLL_LOCK 0x10090 39#define MPLL_LOCK 0x10090
38#define CPLL_CON0 0x10120 40#define CPLL_CON0 0x10120
39#define DPLL_CON0 0x10128 41#define DPLL_CON0 0x10128
40#define EPLL_CON0 0x10130 42#define EPLL_CON0 0x10130
43#define EPLL_CON1 0x10134
44#define EPLL_CON2 0x10138
41#define RPLL_CON0 0x10140 45#define RPLL_CON0 0x10140
46#define RPLL_CON1 0x10144
47#define RPLL_CON2 0x10148
42#define IPLL_CON0 0x10150 48#define IPLL_CON0 0x10150
43#define SPLL_CON0 0x10160 49#define SPLL_CON0 0x10160
44#define VPLL_CON0 0x10170 50#define VPLL_CON0 0x10170
@@ -51,21 +57,31 @@
51#define SRC_TOP5 0x10214 57#define SRC_TOP5 0x10214
52#define SRC_TOP6 0x10218 58#define SRC_TOP6 0x10218
53#define SRC_TOP7 0x1021c 59#define SRC_TOP7 0x1021c
60#define SRC_TOP8 0x10220 /* 5800 specific */
61#define SRC_TOP9 0x10224 /* 5800 specific */
54#define SRC_DISP10 0x1022c 62#define SRC_DISP10 0x1022c
55#define SRC_MAU 0x10240 63#define SRC_MAU 0x10240
56#define SRC_FSYS 0x10244 64#define SRC_FSYS 0x10244
57#define SRC_PERIC0 0x10250 65#define SRC_PERIC0 0x10250
58#define SRC_PERIC1 0x10254 66#define SRC_PERIC1 0x10254
67#define SRC_ISP 0x10270
68#define SRC_CAM 0x10274 /* 5800 specific */
59#define SRC_TOP10 0x10280 69#define SRC_TOP10 0x10280
60#define SRC_TOP11 0x10284 70#define SRC_TOP11 0x10284
61#define SRC_TOP12 0x10288 71#define SRC_TOP12 0x10288
62#define SRC_MASK_DISP10 0x1032c 72#define SRC_TOP13 0x1028c /* 5800 specific */
73#define SRC_MASK_TOP2 0x10308
74#define SRC_MASK_TOP7 0x1031c
75#define SRC_MASK_DISP10 0x1032c
76#define SRC_MASK_MAU 0x10334
63#define SRC_MASK_FSYS 0x10340 77#define SRC_MASK_FSYS 0x10340
64#define SRC_MASK_PERIC0 0x10350 78#define SRC_MASK_PERIC0 0x10350
65#define SRC_MASK_PERIC1 0x10354 79#define SRC_MASK_PERIC1 0x10354
66#define DIV_TOP0 0x10500 80#define DIV_TOP0 0x10500
67#define DIV_TOP1 0x10504 81#define DIV_TOP1 0x10504
68#define DIV_TOP2 0x10508 82#define DIV_TOP2 0x10508
83#define DIV_TOP8 0x10520 /* 5800 specific */
84#define DIV_TOP9 0x10524 /* 5800 specific */
69#define DIV_DISP10 0x1052c 85#define DIV_DISP10 0x1052c
70#define DIV_MAU 0x10544 86#define DIV_MAU 0x10544
71#define DIV_FSYS0 0x10548 87#define DIV_FSYS0 0x10548
@@ -76,54 +92,82 @@
76#define DIV_PERIC2 0x10560 92#define DIV_PERIC2 0x10560
77#define DIV_PERIC3 0x10564 93#define DIV_PERIC3 0x10564
78#define DIV_PERIC4 0x10568 94#define DIV_PERIC4 0x10568
95#define DIV_CAM 0x10574 /* 5800 specific */
96#define SCLK_DIV_ISP0 0x10580
97#define SCLK_DIV_ISP1 0x10584
98#define DIV2_RATIO0 0x10590
99#define DIV4_RATIO 0x105a0
79#define GATE_BUS_TOP 0x10700 100#define GATE_BUS_TOP 0x10700
101#define GATE_BUS_GEN 0x1073c
80#define GATE_BUS_FSYS0 0x10740 102#define GATE_BUS_FSYS0 0x10740
103#define GATE_BUS_FSYS2 0x10748
81#define GATE_BUS_PERIC 0x10750 104#define GATE_BUS_PERIC 0x10750
82#define GATE_BUS_PERIC1 0x10754 105#define GATE_BUS_PERIC1 0x10754
83#define GATE_BUS_PERIS0 0x10760 106#define GATE_BUS_PERIS0 0x10760
84#define GATE_BUS_PERIS1 0x10764 107#define GATE_BUS_PERIS1 0x10764
108#define GATE_BUS_NOC 0x10770
109#define GATE_TOP_SCLK_ISP 0x10870
85#define GATE_IP_GSCL0 0x10910 110#define GATE_IP_GSCL0 0x10910
86#define GATE_IP_GSCL1 0x10920 111#define GATE_IP_GSCL1 0x10920
112#define GATE_IP_CAM 0x10924 /* 5800 specific */
87#define GATE_IP_MFC 0x1092c 113#define GATE_IP_MFC 0x1092c
88#define GATE_IP_DISP1 0x10928 114#define GATE_IP_DISP1 0x10928
89#define GATE_IP_G3D 0x10930 115#define GATE_IP_G3D 0x10930
90#define GATE_IP_GEN 0x10934 116#define GATE_IP_GEN 0x10934
117#define GATE_IP_FSYS 0x10944
118#define GATE_IP_PERIC 0x10950
119#define GATE_IP_PERIS 0x10960
91#define GATE_IP_MSCL 0x10970 120#define GATE_IP_MSCL 0x10970
92#define GATE_TOP_SCLK_GSCL 0x10820 121#define GATE_TOP_SCLK_GSCL 0x10820
93#define GATE_TOP_SCLK_DISP1 0x10828 122#define GATE_TOP_SCLK_DISP1 0x10828
94#define GATE_TOP_SCLK_MAU 0x1083c 123#define GATE_TOP_SCLK_MAU 0x1083c
95#define GATE_TOP_SCLK_FSYS 0x10840 124#define GATE_TOP_SCLK_FSYS 0x10840
96#define GATE_TOP_SCLK_PERIC 0x10850 125#define GATE_TOP_SCLK_PERIC 0x10850
126#define TOP_SPARE2 0x10b08
97#define BPLL_LOCK 0x20010 127#define BPLL_LOCK 0x20010
98#define BPLL_CON0 0x20110 128#define BPLL_CON0 0x20110
99#define SRC_CDREX 0x20200
100#define KPLL_LOCK 0x28000 129#define KPLL_LOCK 0x28000
101#define KPLL_CON0 0x28100 130#define KPLL_CON0 0x28100
102#define SRC_KFC 0x28200 131#define SRC_KFC 0x28200
103#define DIV_KFC0 0x28500 132#define DIV_KFC0 0x28500
104 133
134/* Exynos5x SoC type */
135enum exynos5x_soc {
136 EXYNOS5420,
137 EXYNOS5800,
138};
139
105/* list of PLLs */ 140/* list of PLLs */
106enum exynos5420_plls { 141enum exynos5x_plls {
107 apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll, 142 apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll,
108 bpll, kpll, 143 bpll, kpll,
109 nr_plls /* number of PLLs */ 144 nr_plls /* number of PLLs */
110}; 145};
111 146
112static void __iomem *reg_base; 147static void __iomem *reg_base;
148static enum exynos5x_soc exynos5x_soc;
113 149
114#ifdef CONFIG_PM_SLEEP 150#ifdef CONFIG_PM_SLEEP
115static struct samsung_clk_reg_dump *exynos5420_save; 151static struct samsung_clk_reg_dump *exynos5x_save;
152static struct samsung_clk_reg_dump *exynos5800_save;
116 153
117/* 154/*
118 * list of controller registers to be saved and restored during a 155 * list of controller registers to be saved and restored during a
119 * suspend/resume cycle. 156 * suspend/resume cycle.
120 */ 157 */
121static unsigned long exynos5420_clk_regs[] __initdata = { 158static unsigned long exynos5x_clk_regs[] __initdata = {
122 SRC_CPU, 159 SRC_CPU,
123 DIV_CPU0, 160 DIV_CPU0,
124 DIV_CPU1, 161 DIV_CPU1,
125 GATE_BUS_CPU, 162 GATE_BUS_CPU,
126 GATE_SCLK_CPU, 163 GATE_SCLK_CPU,
164 CLKOUT_CMU_CPU,
165 EPLL_CON0,
166 EPLL_CON1,
167 EPLL_CON2,
168 RPLL_CON0,
169 RPLL_CON1,
170 RPLL_CON2,
127 SRC_TOP0, 171 SRC_TOP0,
128 SRC_TOP1, 172 SRC_TOP1,
129 SRC_TOP2, 173 SRC_TOP2,
@@ -140,10 +184,13 @@ static unsigned long exynos5420_clk_regs[] __initdata = {
140 SRC_TOP10, 184 SRC_TOP10,
141 SRC_TOP11, 185 SRC_TOP11,
142 SRC_TOP12, 186 SRC_TOP12,
187 SRC_MASK_TOP2,
188 SRC_MASK_TOP7,
143 SRC_MASK_DISP10, 189 SRC_MASK_DISP10,
144 SRC_MASK_FSYS, 190 SRC_MASK_FSYS,
145 SRC_MASK_PERIC0, 191 SRC_MASK_PERIC0,
146 SRC_MASK_PERIC1, 192 SRC_MASK_PERIC1,
193 SRC_ISP,
147 DIV_TOP0, 194 DIV_TOP0,
148 DIV_TOP1, 195 DIV_TOP1,
149 DIV_TOP2, 196 DIV_TOP2,
@@ -157,41 +204,71 @@ static unsigned long exynos5420_clk_regs[] __initdata = {
157 DIV_PERIC2, 204 DIV_PERIC2,
158 DIV_PERIC3, 205 DIV_PERIC3,
159 DIV_PERIC4, 206 DIV_PERIC4,
207 SCLK_DIV_ISP0,
208 SCLK_DIV_ISP1,
209 DIV2_RATIO0,
210 DIV4_RATIO,
160 GATE_BUS_TOP, 211 GATE_BUS_TOP,
212 GATE_BUS_GEN,
161 GATE_BUS_FSYS0, 213 GATE_BUS_FSYS0,
214 GATE_BUS_FSYS2,
162 GATE_BUS_PERIC, 215 GATE_BUS_PERIC,
163 GATE_BUS_PERIC1, 216 GATE_BUS_PERIC1,
164 GATE_BUS_PERIS0, 217 GATE_BUS_PERIS0,
165 GATE_BUS_PERIS1, 218 GATE_BUS_PERIS1,
219 GATE_BUS_NOC,
220 GATE_TOP_SCLK_ISP,
166 GATE_IP_GSCL0, 221 GATE_IP_GSCL0,
167 GATE_IP_GSCL1, 222 GATE_IP_GSCL1,
168 GATE_IP_MFC, 223 GATE_IP_MFC,
169 GATE_IP_DISP1, 224 GATE_IP_DISP1,
170 GATE_IP_G3D, 225 GATE_IP_G3D,
171 GATE_IP_GEN, 226 GATE_IP_GEN,
227 GATE_IP_FSYS,
228 GATE_IP_PERIC,
229 GATE_IP_PERIS,
172 GATE_IP_MSCL, 230 GATE_IP_MSCL,
173 GATE_TOP_SCLK_GSCL, 231 GATE_TOP_SCLK_GSCL,
174 GATE_TOP_SCLK_DISP1, 232 GATE_TOP_SCLK_DISP1,
175 GATE_TOP_SCLK_MAU, 233 GATE_TOP_SCLK_MAU,
176 GATE_TOP_SCLK_FSYS, 234 GATE_TOP_SCLK_FSYS,
177 GATE_TOP_SCLK_PERIC, 235 GATE_TOP_SCLK_PERIC,
178 SRC_CDREX, 236 TOP_SPARE2,
179 SRC_KFC, 237 SRC_KFC,
180 DIV_KFC0, 238 DIV_KFC0,
181}; 239};
182 240
241static unsigned long exynos5800_clk_regs[] __initdata = {
242 SRC_TOP8,
243 SRC_TOP9,
244 SRC_CAM,
245 SRC_TOP1,
246 DIV_TOP8,
247 DIV_TOP9,
248 DIV_CAM,
249 GATE_IP_CAM,
250};
251
183static int exynos5420_clk_suspend(void) 252static int exynos5420_clk_suspend(void)
184{ 253{
185 samsung_clk_save(reg_base, exynos5420_save, 254 samsung_clk_save(reg_base, exynos5x_save,
186 ARRAY_SIZE(exynos5420_clk_regs)); 255 ARRAY_SIZE(exynos5x_clk_regs));
256
257 if (exynos5x_soc == EXYNOS5800)
258 samsung_clk_save(reg_base, exynos5800_save,
259 ARRAY_SIZE(exynos5800_clk_regs));
187 260
188 return 0; 261 return 0;
189} 262}
190 263
191static void exynos5420_clk_resume(void) 264static void exynos5420_clk_resume(void)
192{ 265{
193 samsung_clk_restore(reg_base, exynos5420_save, 266 samsung_clk_restore(reg_base, exynos5x_save,
194 ARRAY_SIZE(exynos5420_clk_regs)); 267 ARRAY_SIZE(exynos5x_clk_regs));
268
269 if (exynos5x_soc == EXYNOS5800)
270 samsung_clk_restore(reg_base, exynos5800_save,
271 ARRAY_SIZE(exynos5800_clk_regs));
195} 272}
196 273
197static struct syscore_ops exynos5420_clk_syscore_ops = { 274static struct syscore_ops exynos5420_clk_syscore_ops = {
@@ -201,108 +278,183 @@ static struct syscore_ops exynos5420_clk_syscore_ops = {
201 278
202static void exynos5420_clk_sleep_init(void) 279static void exynos5420_clk_sleep_init(void)
203{ 280{
204 exynos5420_save = samsung_clk_alloc_reg_dump(exynos5420_clk_regs, 281 exynos5x_save = samsung_clk_alloc_reg_dump(exynos5x_clk_regs,
205 ARRAY_SIZE(exynos5420_clk_regs)); 282 ARRAY_SIZE(exynos5x_clk_regs));
206 if (!exynos5420_save) { 283 if (!exynos5x_save) {
207 pr_warn("%s: failed to allocate sleep save data, no sleep support!\n", 284 pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
208 __func__); 285 __func__);
209 return; 286 return;
210 } 287 }
211 288
289 if (exynos5x_soc == EXYNOS5800) {
290 exynos5800_save =
291 samsung_clk_alloc_reg_dump(exynos5800_clk_regs,
292 ARRAY_SIZE(exynos5800_clk_regs));
293 if (!exynos5800_save)
294 goto err_soc;
295 }
296
212 register_syscore_ops(&exynos5420_clk_syscore_ops); 297 register_syscore_ops(&exynos5420_clk_syscore_ops);
298 return;
299err_soc:
300 kfree(exynos5x_save);
301 pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
302 __func__);
303 return;
213} 304}
214#else 305#else
215static void exynos5420_clk_sleep_init(void) {} 306static void exynos5420_clk_sleep_init(void) {}
216#endif 307#endif
217 308
218/* list of all parent clocks */ 309/* list of all parent clocks */
219PNAME(mspll_cpu_p) = { "sclk_cpll", "sclk_dpll", 310PNAME(mout_mspll_cpu_p) = {"mout_sclk_cpll", "mout_sclk_dpll",
220 "sclk_mpll", "sclk_spll" }; 311 "mout_sclk_mpll", "mout_sclk_spll"};
221PNAME(cpu_p) = { "mout_apll" , "mout_mspll_cpu" }; 312PNAME(mout_cpu_p) = {"mout_apll" , "mout_mspll_cpu"};
222PNAME(kfc_p) = { "mout_kpll" , "mout_mspll_kfc" }; 313PNAME(mout_kfc_p) = {"mout_kpll" , "mout_mspll_kfc"};
223PNAME(apll_p) = { "fin_pll", "fout_apll", }; 314PNAME(mout_apll_p) = {"fin_pll", "fout_apll"};
224PNAME(bpll_p) = { "fin_pll", "fout_bpll", }; 315PNAME(mout_bpll_p) = {"fin_pll", "fout_bpll"};
225PNAME(cpll_p) = { "fin_pll", "fout_cpll", }; 316PNAME(mout_cpll_p) = {"fin_pll", "fout_cpll"};
226PNAME(dpll_p) = { "fin_pll", "fout_dpll", }; 317PNAME(mout_dpll_p) = {"fin_pll", "fout_dpll"};
227PNAME(epll_p) = { "fin_pll", "fout_epll", }; 318PNAME(mout_epll_p) = {"fin_pll", "fout_epll"};
228PNAME(ipll_p) = { "fin_pll", "fout_ipll", }; 319PNAME(mout_ipll_p) = {"fin_pll", "fout_ipll"};
229PNAME(kpll_p) = { "fin_pll", "fout_kpll", }; 320PNAME(mout_kpll_p) = {"fin_pll", "fout_kpll"};
230PNAME(mpll_p) = { "fin_pll", "fout_mpll", }; 321PNAME(mout_mpll_p) = {"fin_pll", "fout_mpll"};
231PNAME(rpll_p) = { "fin_pll", "fout_rpll", }; 322PNAME(mout_rpll_p) = {"fin_pll", "fout_rpll"};
232PNAME(spll_p) = { "fin_pll", "fout_spll", }; 323PNAME(mout_spll_p) = {"fin_pll", "fout_spll"};
233PNAME(vpll_p) = { "fin_pll", "fout_vpll", }; 324PNAME(mout_vpll_p) = {"fin_pll", "fout_vpll"};
234 325
235PNAME(group1_p) = { "sclk_cpll", "sclk_dpll", "sclk_mpll" }; 326PNAME(mout_group1_p) = {"mout_sclk_cpll", "mout_sclk_dpll",
236PNAME(group2_p) = { "fin_pll", "sclk_cpll", "sclk_dpll", "sclk_mpll", 327 "mout_sclk_mpll"};
237 "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" }; 328PNAME(mout_group2_p) = {"fin_pll", "mout_sclk_cpll",
238PNAME(group3_p) = { "sclk_rpll", "sclk_spll" }; 329 "mout_sclk_dpll", "mout_sclk_mpll", "mout_sclk_spll",
239PNAME(group4_p) = { "sclk_ipll", "sclk_dpll", "sclk_mpll" }; 330 "mout_sclk_ipll", "mout_sclk_epll", "mout_sclk_rpll"};
240PNAME(group5_p) = { "sclk_vpll", "sclk_dpll" }; 331PNAME(mout_group3_p) = {"mout_sclk_rpll", "mout_sclk_spll"};
241 332PNAME(mout_group4_p) = {"mout_sclk_ipll", "mout_sclk_dpll", "mout_sclk_mpll"};
242PNAME(sw_aclk66_p) = { "dout_aclk66", "sclk_spll" }; 333PNAME(mout_group5_p) = {"mout_sclk_vpll", "mout_sclk_dpll"};
243PNAME(aclk66_peric_p) = { "fin_pll", "mout_sw_aclk66" }; 334
244 335PNAME(mout_fimd1_final_p) = {"mout_fimd1", "mout_fimd1_opt"};
245PNAME(sw_aclk200_fsys_p) = { "dout_aclk200_fsys", "sclk_spll"}; 336PNAME(mout_sw_aclk66_p) = {"dout_aclk66", "mout_sclk_spll"};
246PNAME(user_aclk200_fsys_p) = { "fin_pll", "mout_sw_aclk200_fsys" }; 337PNAME(mout_user_aclk66_peric_p) = { "fin_pll", "mout_sw_aclk66"};
247 338PNAME(mout_user_pclk66_gpio_p) = {"mout_sw_aclk66", "ff_sw_aclk66"};
248PNAME(sw_aclk200_fsys2_p) = { "dout_aclk200_fsys2", "sclk_spll"}; 339
249PNAME(user_aclk200_fsys2_p) = { "fin_pll", "mout_sw_aclk200_fsys2" }; 340PNAME(mout_sw_aclk200_fsys_p) = {"dout_aclk200_fsys", "mout_sclk_spll"};
250 341PNAME(mout_sw_pclk200_fsys_p) = {"dout_pclk200_fsys", "mout_sclk_spll"};
251PNAME(sw_aclk200_p) = { "dout_aclk200", "sclk_spll"}; 342PNAME(mout_user_pclk200_fsys_p) = {"fin_pll", "mout_sw_pclk200_fsys"};
252PNAME(aclk200_disp1_p) = { "fin_pll", "mout_sw_aclk200" }; 343PNAME(mout_user_aclk200_fsys_p) = {"fin_pll", "mout_sw_aclk200_fsys"};
253 344
254PNAME(sw_aclk400_mscl_p) = { "dout_aclk400_mscl", "sclk_spll"}; 345PNAME(mout_sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2", "mout_sclk_spll"};
255PNAME(user_aclk400_mscl_p) = { "fin_pll", "mout_sw_aclk400_mscl" }; 346PNAME(mout_user_aclk200_fsys2_p) = {"fin_pll", "mout_sw_aclk200_fsys2"};
256 347PNAME(mout_sw_aclk100_noc_p) = {"dout_aclk100_noc", "mout_sclk_spll"};
257PNAME(sw_aclk333_p) = { "dout_aclk333", "sclk_spll"}; 348PNAME(mout_user_aclk100_noc_p) = {"fin_pll", "mout_sw_aclk100_noc"};
258PNAME(user_aclk333_p) = { "fin_pll", "mout_sw_aclk333" }; 349
259 350PNAME(mout_sw_aclk400_wcore_p) = {"dout_aclk400_wcore", "mout_sclk_spll"};
260PNAME(sw_aclk166_p) = { "dout_aclk166", "sclk_spll"}; 351PNAME(mout_aclk400_wcore_bpll_p) = {"mout_aclk400_wcore", "sclk_bpll"};
261PNAME(user_aclk166_p) = { "fin_pll", "mout_sw_aclk166" }; 352PNAME(mout_user_aclk400_wcore_p) = {"fin_pll", "mout_sw_aclk400_wcore"};
262 353
263PNAME(sw_aclk266_p) = { "dout_aclk266", "sclk_spll"}; 354PNAME(mout_sw_aclk400_isp_p) = {"dout_aclk400_isp", "mout_sclk_spll"};
264PNAME(user_aclk266_p) = { "fin_pll", "mout_sw_aclk266" }; 355PNAME(mout_user_aclk400_isp_p) = {"fin_pll", "mout_sw_aclk400_isp"};
265 356
266PNAME(sw_aclk333_432_gscl_p) = { "dout_aclk333_432_gscl", "sclk_spll"}; 357PNAME(mout_sw_aclk333_432_isp0_p) = {"dout_aclk333_432_isp0",
267PNAME(user_aclk333_432_gscl_p) = { "fin_pll", "mout_sw_aclk333_432_gscl" }; 358 "mout_sclk_spll"};
268 359PNAME(mout_user_aclk333_432_isp0_p) = {"fin_pll", "mout_sw_aclk333_432_isp0"};
269PNAME(sw_aclk300_gscl_p) = { "dout_aclk300_gscl", "sclk_spll"}; 360
270PNAME(user_aclk300_gscl_p) = { "fin_pll", "mout_sw_aclk300_gscl" }; 361PNAME(mout_sw_aclk333_432_isp_p) = {"dout_aclk333_432_isp", "mout_sclk_spll"};
271 362PNAME(mout_user_aclk333_432_isp_p) = {"fin_pll", "mout_sw_aclk333_432_isp"};
272PNAME(sw_aclk300_disp1_p) = { "dout_aclk300_disp1", "sclk_spll"}; 363
273PNAME(user_aclk300_disp1_p) = { "fin_pll", "mout_sw_aclk300_disp1" }; 364PNAME(mout_sw_aclk200_p) = {"dout_aclk200", "mout_sclk_spll"};
274 365PNAME(mout_user_aclk200_disp1_p) = {"fin_pll", "mout_sw_aclk200"};
275PNAME(sw_aclk300_jpeg_p) = { "dout_aclk300_jpeg", "sclk_spll"}; 366
276PNAME(user_aclk300_jpeg_p) = { "fin_pll", "mout_sw_aclk300_jpeg" }; 367PNAME(mout_sw_aclk400_mscl_p) = {"dout_aclk400_mscl", "mout_sclk_spll"};
277 368PNAME(mout_user_aclk400_mscl_p) = {"fin_pll", "mout_sw_aclk400_mscl"};
278PNAME(sw_aclk_g3d_p) = { "dout_aclk_g3d", "sclk_spll"}; 369
279PNAME(user_aclk_g3d_p) = { "fin_pll", "mout_sw_aclk_g3d" }; 370PNAME(mout_sw_aclk333_p) = {"dout_aclk333", "mout_sclk_spll"};
280 371PNAME(mout_user_aclk333_p) = {"fin_pll", "mout_sw_aclk333"};
281PNAME(sw_aclk266_g2d_p) = { "dout_aclk266_g2d", "sclk_spll"}; 372
282PNAME(user_aclk266_g2d_p) = { "fin_pll", "mout_sw_aclk266_g2d" }; 373PNAME(mout_sw_aclk166_p) = {"dout_aclk166", "mout_sclk_spll"};
283 374PNAME(mout_user_aclk166_p) = {"fin_pll", "mout_sw_aclk166"};
284PNAME(sw_aclk333_g2d_p) = { "dout_aclk333_g2d", "sclk_spll"}; 375
285PNAME(user_aclk333_g2d_p) = { "fin_pll", "mout_sw_aclk333_g2d" }; 376PNAME(mout_sw_aclk266_p) = {"dout_aclk266", "mout_sclk_spll"};
286 377PNAME(mout_user_aclk266_p) = {"fin_pll", "mout_sw_aclk266"};
287PNAME(audio0_p) = { "fin_pll", "cdclk0", "sclk_dpll", "sclk_mpll", 378PNAME(mout_user_aclk266_isp_p) = {"fin_pll", "mout_sw_aclk266"};
288 "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" }; 379
289PNAME(audio1_p) = { "fin_pll", "cdclk1", "sclk_dpll", "sclk_mpll", 380PNAME(mout_sw_aclk333_432_gscl_p) = {"dout_aclk333_432_gscl", "mout_sclk_spll"};
290 "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" }; 381PNAME(mout_user_aclk333_432_gscl_p) = {"fin_pll", "mout_sw_aclk333_432_gscl"};
291PNAME(audio2_p) = { "fin_pll", "cdclk2", "sclk_dpll", "sclk_mpll", 382
292 "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" }; 383PNAME(mout_sw_aclk300_gscl_p) = {"dout_aclk300_gscl", "mout_sclk_spll"};
293PNAME(spdif_p) = { "fin_pll", "dout_audio0", "dout_audio1", "dout_audio2", 384PNAME(mout_user_aclk300_gscl_p) = {"fin_pll", "mout_sw_aclk300_gscl"};
294 "spdif_extclk", "sclk_ipll", "sclk_epll", "sclk_rpll" }; 385
295PNAME(hdmi_p) = { "dout_hdmi_pixel", "sclk_hdmiphy" }; 386PNAME(mout_sw_aclk300_disp1_p) = {"dout_aclk300_disp1", "mout_sclk_spll"};
296PNAME(maudio0_p) = { "fin_pll", "maudio_clk", "sclk_dpll", "sclk_mpll", 387PNAME(mout_sw_aclk400_disp1_p) = {"dout_aclk400_disp1", "mout_sclk_spll"};
297 "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" }; 388PNAME(mout_user_aclk300_disp1_p) = {"fin_pll", "mout_sw_aclk300_disp1"};
389PNAME(mout_user_aclk400_disp1_p) = {"fin_pll", "mout_sw_aclk400_disp1"};
390
391PNAME(mout_sw_aclk300_jpeg_p) = {"dout_aclk300_jpeg", "mout_sclk_spll"};
392PNAME(mout_user_aclk300_jpeg_p) = {"fin_pll", "mout_sw_aclk300_jpeg"};
393
394PNAME(mout_sw_aclk_g3d_p) = {"dout_aclk_g3d", "mout_sclk_spll"};
395PNAME(mout_user_aclk_g3d_p) = {"fin_pll", "mout_sw_aclk_g3d"};
396
397PNAME(mout_sw_aclk266_g2d_p) = {"dout_aclk266_g2d", "mout_sclk_spll"};
398PNAME(mout_user_aclk266_g2d_p) = {"fin_pll", "mout_sw_aclk266_g2d"};
399
400PNAME(mout_sw_aclk333_g2d_p) = {"dout_aclk333_g2d", "mout_sclk_spll"};
401PNAME(mout_user_aclk333_g2d_p) = {"fin_pll", "mout_sw_aclk333_g2d"};
402
403PNAME(mout_audio0_p) = {"fin_pll", "cdclk0", "mout_sclk_dpll",
404 "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
405 "mout_sclk_epll", "mout_sclk_rpll"};
406PNAME(mout_audio1_p) = {"fin_pll", "cdclk1", "mout_sclk_dpll",
407 "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
408 "mout_sclk_epll", "mout_sclk_rpll"};
409PNAME(mout_audio2_p) = {"fin_pll", "cdclk2", "mout_sclk_dpll",
410 "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
411 "mout_sclk_epll", "mout_sclk_rpll"};
412PNAME(mout_spdif_p) = {"fin_pll", "dout_audio0", "dout_audio1",
413 "dout_audio2", "spdif_extclk", "mout_sclk_ipll",
414 "mout_sclk_epll", "mout_sclk_rpll"};
415PNAME(mout_hdmi_p) = {"dout_hdmi_pixel", "sclk_hdmiphy"};
416PNAME(mout_maudio0_p) = {"fin_pll", "maudio_clk", "mout_sclk_dpll",
417 "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
418 "mout_sclk_epll", "mout_sclk_rpll"};
419PNAME(mout_mau_epll_clk_p) = {"mout_sclk_epll", "mout_sclk_dpll",
420 "mout_sclk_mpll", "mout_sclk_spll"};
421/* List of parents specific to exynos5800 */
422PNAME(mout_epll2_5800_p) = { "mout_sclk_epll", "ff_dout_epll2" };
423PNAME(mout_group1_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll",
424 "mout_sclk_mpll", "ff_dout_spll2" };
425PNAME(mout_group2_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll",
426 "mout_sclk_mpll", "ff_dout_spll2",
427 "mout_epll2", "mout_sclk_ipll" };
428PNAME(mout_group3_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll",
429 "mout_sclk_mpll", "ff_dout_spll2",
430 "mout_epll2" };
431PNAME(mout_group5_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll",
432 "mout_sclk_mpll", "mout_sclk_spll" };
433PNAME(mout_group6_5800_p) = { "mout_sclk_ipll", "mout_sclk_dpll",
434 "mout_sclk_mpll", "ff_dout_spll2" };
435PNAME(mout_group7_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll",
436 "mout_sclk_mpll", "mout_sclk_spll",
437 "mout_epll2", "mout_sclk_ipll" };
438PNAME(mout_mau_epll_clk_5800_p) = { "mout_sclk_epll", "mout_sclk_dpll",
439 "mout_sclk_mpll",
440 "ff_dout_spll2" };
441PNAME(mout_group8_5800_p) = { "dout_aclk432_scaler", "dout_sclk_sw" };
442PNAME(mout_group9_5800_p) = { "dout_osc_div", "mout_sw_aclk432_scaler" };
443PNAME(mout_group10_5800_p) = { "dout_aclk432_cam", "dout_sclk_sw" };
444PNAME(mout_group11_5800_p) = { "dout_osc_div", "mout_sw_aclk432_cam" };
445PNAME(mout_group12_5800_p) = { "dout_aclkfl1_550_cam", "dout_sclk_sw" };
446PNAME(mout_group13_5800_p) = { "dout_osc_div", "mout_sw_aclkfl1_550_cam" };
447PNAME(mout_group14_5800_p) = { "dout_aclk550_cam", "dout_sclk_sw" };
448PNAME(mout_group15_5800_p) = { "dout_osc_div", "mout_sw_aclk550_cam" };
298 449
299/* fixed rate clocks generated outside the soc */ 450/* fixed rate clocks generated outside the soc */
300static struct samsung_fixed_rate_clock exynos5420_fixed_rate_ext_clks[] __initdata = { 451static struct samsung_fixed_rate_clock
452 exynos5x_fixed_rate_ext_clks[] __initdata = {
301 FRATE(CLK_FIN_PLL, "fin_pll", NULL, CLK_IS_ROOT, 0), 453 FRATE(CLK_FIN_PLL, "fin_pll", NULL, CLK_IS_ROOT, 0),
302}; 454};
303 455
304/* fixed rate clocks generated inside the soc */ 456/* fixed rate clocks generated inside the soc */
305static struct samsung_fixed_rate_clock exynos5420_fixed_rate_clks[] __initdata = { 457static struct samsung_fixed_rate_clock exynos5x_fixed_rate_clks[] __initdata = {
306 FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000), 458 FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000),
307 FRATE(0, "sclk_pwi", NULL, CLK_IS_ROOT, 24000000), 459 FRATE(0, "sclk_pwi", NULL, CLK_IS_ROOT, 24000000),
308 FRATE(0, "sclk_usbh20", NULL, CLK_IS_ROOT, 48000000), 460 FRATE(0, "sclk_usbh20", NULL, CLK_IS_ROOT, 48000000),
@@ -310,146 +462,309 @@ static struct samsung_fixed_rate_clock exynos5420_fixed_rate_clks[] __initdata =
310 FRATE(0, "sclk_usbh20_scan_clk", NULL, CLK_IS_ROOT, 480000000), 462 FRATE(0, "sclk_usbh20_scan_clk", NULL, CLK_IS_ROOT, 480000000),
311}; 463};
312 464
313static struct samsung_fixed_factor_clock exynos5420_fixed_factor_clks[] __initdata = { 465static struct samsung_fixed_factor_clock
314 FFACTOR(0, "sclk_hsic_12m", "fin_pll", 1, 2, 0), 466 exynos5x_fixed_factor_clks[] __initdata = {
467 FFACTOR(0, "ff_hsic_12m", "fin_pll", 1, 2, 0),
468 FFACTOR(0, "ff_sw_aclk66", "mout_sw_aclk66", 1, 2, 0),
315}; 469};
316 470
317static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = { 471static struct samsung_fixed_factor_clock
318 MUX(0, "mout_mspll_kfc", mspll_cpu_p, SRC_TOP7, 8, 2), 472 exynos5800_fixed_factor_clks[] __initdata = {
319 MUX(0, "mout_mspll_cpu", mspll_cpu_p, SRC_TOP7, 12, 2), 473 FFACTOR(0, "ff_dout_epll2", "mout_sclk_epll", 1, 2, 0),
320 MUX(0, "mout_apll", apll_p, SRC_CPU, 0, 1), 474 FFACTOR(0, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0),
321 MUX(0, "mout_cpu", cpu_p, SRC_CPU, 16, 1), 475};
322 MUX(0, "mout_kpll", kpll_p, SRC_KFC, 0, 1), 476
323 MUX(0, "mout_cpu_kfc", kfc_p, SRC_KFC, 16, 1), 477struct samsung_mux_clock exynos5800_mux_clks[] __initdata = {
324 478 MUX(0, "mout_aclk400_isp", mout_group3_5800_p, SRC_TOP0, 0, 3),
325 MUX(0, "sclk_bpll", bpll_p, SRC_CDREX, 0, 1), 479 MUX(0, "mout_aclk400_mscl", mout_group3_5800_p, SRC_TOP0, 4, 3),
326 480 MUX(0, "mout_aclk400_wcore", mout_group2_5800_p, SRC_TOP0, 16, 3),
327 MUX_A(0, "mout_aclk400_mscl", group1_p, 481 MUX(0, "mout_aclk100_noc", mout_group1_5800_p, SRC_TOP0, 20, 2),
328 SRC_TOP0, 4, 2, "aclk400_mscl"), 482
329 MUX(0, "mout_aclk200", group1_p, SRC_TOP0, 8, 2), 483 MUX(0, "mout_aclk333_432_gscl", mout_group6_5800_p, SRC_TOP1, 0, 2),
330 MUX(0, "mout_aclk200_fsys2", group1_p, SRC_TOP0, 12, 2), 484 MUX(0, "mout_aclk333_432_isp", mout_group6_5800_p, SRC_TOP1, 4, 2),
331 MUX(0, "mout_aclk200_fsys", group1_p, SRC_TOP0, 28, 2), 485 MUX(0, "mout_aclk333_432_isp0", mout_group6_5800_p, SRC_TOP1, 12, 2),
332 486 MUX(0, "mout_aclk266", mout_group5_5800_p, SRC_TOP1, 20, 2),
333 MUX(0, "mout_aclk333_432_gscl", group4_p, SRC_TOP1, 0, 2), 487 MUX(0, "mout_aclk333", mout_group1_5800_p, SRC_TOP1, 28, 2),
334 MUX(0, "mout_aclk66", group1_p, SRC_TOP1, 8, 2), 488
335 MUX(0, "mout_aclk266", group1_p, SRC_TOP1, 20, 2), 489 MUX(0, "mout_aclk400_disp1", mout_group7_5800_p, SRC_TOP2, 4, 3),
336 MUX(0, "mout_aclk166", group1_p, SRC_TOP1, 24, 2), 490 MUX(0, "mout_aclk333_g2d", mout_group5_5800_p, SRC_TOP2, 8, 2),
337 MUX(0, "mout_aclk333", group1_p, SRC_TOP1, 28, 2), 491 MUX(0, "mout_aclk266_g2d", mout_group5_5800_p, SRC_TOP2, 12, 2),
338 492 MUX(0, "mout_aclk300_jpeg", mout_group5_5800_p, SRC_TOP2, 20, 2),
339 MUX(0, "mout_aclk333_g2d", group1_p, SRC_TOP2, 8, 2), 493 MUX(0, "mout_aclk300_disp1", mout_group5_5800_p, SRC_TOP2, 24, 2),
340 MUX(0, "mout_aclk266_g2d", group1_p, SRC_TOP2, 12, 2), 494 MUX(0, "mout_aclk300_gscl", mout_group5_5800_p, SRC_TOP2, 28, 2),
341 MUX(0, "mout_aclk_g3d", group5_p, SRC_TOP2, 16, 1), 495
342 MUX(0, "mout_aclk300_jpeg", group1_p, SRC_TOP2, 20, 2), 496 MUX(0, "mout_mau_epll_clk", mout_mau_epll_clk_5800_p, SRC_TOP7,
343 MUX(0, "mout_aclk300_disp1", group1_p, SRC_TOP2, 24, 2), 497 20, 2),
344 MUX(0, "mout_aclk300_gscl", group1_p, SRC_TOP2, 28, 2), 498 MUX(0, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1),
345 499 MUX(0, "mout_epll2", mout_epll2_5800_p, SRC_TOP7, 28, 1),
346 MUX(0, "mout_user_aclk400_mscl", user_aclk400_mscl_p, 500
501 MUX(0, "mout_aclk550_cam", mout_group3_5800_p, SRC_TOP8, 16, 3),
502 MUX(0, "mout_aclkfl1_550_cam", mout_group3_5800_p, SRC_TOP8, 20, 3),
503 MUX(0, "mout_aclk432_cam", mout_group6_5800_p, SRC_TOP8, 24, 2),
504 MUX(0, "mout_aclk432_scaler", mout_group6_5800_p, SRC_TOP8, 28, 2),
505
506 MUX(0, "mout_user_aclk550_cam", mout_group15_5800_p,
507 SRC_TOP9, 16, 1),
508 MUX(0, "mout_user_aclkfl1_550_cam", mout_group13_5800_p,
509 SRC_TOP9, 20, 1),
510 MUX(0, "mout_user_aclk432_cam", mout_group11_5800_p,
511 SRC_TOP9, 24, 1),
512 MUX(0, "mout_user_aclk432_scaler", mout_group9_5800_p,
513 SRC_TOP9, 28, 1),
514
515 MUX(0, "mout_sw_aclk550_cam", mout_group14_5800_p, SRC_TOP13, 16, 1),
516 MUX(0, "mout_sw_aclkfl1_550_cam", mout_group12_5800_p,
517 SRC_TOP13, 20, 1),
518 MUX(0, "mout_sw_aclk432_cam", mout_group10_5800_p,
519 SRC_TOP13, 24, 1),
520 MUX(0, "mout_sw_aclk432_scaler", mout_group8_5800_p,
521 SRC_TOP13, 28, 1),
522
523 MUX(0, "mout_fimd1", mout_group2_p, SRC_DISP10, 4, 3),
524};
525
526struct samsung_div_clock exynos5800_div_clks[] __initdata = {
527 DIV(0, "dout_aclk400_wcore", "mout_aclk400_wcore", DIV_TOP0, 16, 3),
528
529 DIV(0, "dout_aclk550_cam", "mout_aclk550_cam",
530 DIV_TOP8, 16, 3),
531 DIV(0, "dout_aclkfl1_550_cam", "mout_aclkfl1_550_cam",
532 DIV_TOP8, 20, 3),
533 DIV(0, "dout_aclk432_cam", "mout_aclk432_cam",
534 DIV_TOP8, 24, 3),
535 DIV(0, "dout_aclk432_scaler", "mout_aclk432_scaler",
536 DIV_TOP8, 28, 3),
537
538 DIV(0, "dout_osc_div", "fin_pll", DIV_TOP9, 20, 3),
539 DIV(0, "dout_sclk_sw", "sclk_spll", DIV_TOP9, 24, 6),
540};
541
542struct samsung_gate_clock exynos5800_gate_clks[] __initdata = {
543 GATE(CLK_ACLK550_CAM, "aclk550_cam", "mout_user_aclk550_cam",
544 GATE_BUS_TOP, 24, 0, 0),
545 GATE(CLK_ACLK432_SCALER, "aclk432_scaler", "mout_user_aclk432_scaler",
546 GATE_BUS_TOP, 27, 0, 0),
547};
548
549struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
550 MUX(0, "sclk_bpll", mout_bpll_p, TOP_SPARE2, 0, 1),
551 MUX(0, "mout_aclk400_wcore_bpll", mout_aclk400_wcore_bpll_p,
552 TOP_SPARE2, 4, 1),
553
554 MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2),
555 MUX_A(0, "mout_aclk400_mscl", mout_group1_p,
556 SRC_TOP0, 4, 2, "aclk400_mscl"),
557 MUX(0, "mout_aclk400_wcore", mout_group1_p, SRC_TOP0, 16, 2),
558 MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2),
559
560 MUX(0, "mout_aclk333_432_gscl", mout_group4_p, SRC_TOP1, 0, 2),
561 MUX(0, "mout_aclk333_432_isp", mout_group4_p,
562 SRC_TOP1, 4, 2),
563 MUX(0, "mout_aclk333_432_isp0", mout_group4_p, SRC_TOP1, 12, 2),
564 MUX(0, "mout_aclk266", mout_group1_p, SRC_TOP1, 20, 2),
565 MUX(0, "mout_aclk333", mout_group1_p, SRC_TOP1, 28, 2),
566
567 MUX(0, "mout_aclk400_disp1", mout_group1_p, SRC_TOP2, 4, 2),
568 MUX(0, "mout_aclk333_g2d", mout_group1_p, SRC_TOP2, 8, 2),
569 MUX(0, "mout_aclk266_g2d", mout_group1_p, SRC_TOP2, 12, 2),
570 MUX(0, "mout_aclk300_jpeg", mout_group1_p, SRC_TOP2, 20, 2),
571 MUX(0, "mout_aclk300_disp1", mout_group1_p, SRC_TOP2, 24, 2),
572 MUX(0, "mout_aclk300_gscl", mout_group1_p, SRC_TOP2, 28, 2),
573
574 MUX(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2),
575
576 MUX(0, "mout_fimd1", mout_group3_p, SRC_DISP10, 4, 1),
577};
578
579struct samsung_div_clock exynos5420_div_clks[] __initdata = {
580 DIV(0, "dout_aclk400_wcore", "mout_aclk400_wcore_bpll",
581 DIV_TOP0, 16, 3),
582};
583
584static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
585 MUX(0, "mout_user_pclk66_gpio", mout_user_pclk66_gpio_p,
586 SRC_TOP7, 4, 1),
587 MUX(0, "mout_mspll_kfc", mout_mspll_cpu_p, SRC_TOP7, 8, 2),
588 MUX(0, "mout_mspll_cpu", mout_mspll_cpu_p, SRC_TOP7, 12, 2),
589
590 MUX(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1),
591 MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
592 MUX(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1),
593 MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
594
595 MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2),
596 MUX(0, "mout_aclk200_fsys2", mout_group1_p, SRC_TOP0, 12, 2),
597 MUX(0, "mout_pclk200_fsys", mout_group1_p, SRC_TOP0, 24, 2),
598 MUX(0, "mout_aclk200_fsys", mout_group1_p, SRC_TOP0, 28, 2),
599
600 MUX(0, "mout_aclk66", mout_group1_p, SRC_TOP1, 8, 2),
601 MUX(0, "mout_aclk166", mout_group1_p, SRC_TOP1, 24, 2),
602
603 MUX(0, "mout_aclk_g3d", mout_group5_p, SRC_TOP2, 16, 1),
604
605 MUX(0, "mout_user_aclk400_isp", mout_user_aclk400_isp_p,
606 SRC_TOP3, 0, 1),
607 MUX(0, "mout_user_aclk400_mscl", mout_user_aclk400_mscl_p,
347 SRC_TOP3, 4, 1), 608 SRC_TOP3, 4, 1),
348 MUX_A(0, "mout_aclk200_disp1", aclk200_disp1_p, 609 MUX(0, "mout_user_aclk200_disp1", mout_user_aclk200_disp1_p,
349 SRC_TOP3, 8, 1, "aclk200_disp1"), 610 SRC_TOP3, 8, 1),
350 MUX(0, "mout_user_aclk200_fsys2", user_aclk200_fsys2_p, 611 MUX(0, "mout_user_aclk200_fsys2", mout_user_aclk200_fsys2_p,
351 SRC_TOP3, 12, 1), 612 SRC_TOP3, 12, 1),
352 MUX(0, "mout_user_aclk200_fsys", user_aclk200_fsys_p, 613 MUX(0, "mout_user_aclk400_wcore", mout_user_aclk400_wcore_p,
614 SRC_TOP3, 16, 1),
615 MUX(0, "mout_user_aclk100_noc", mout_user_aclk100_noc_p,
616 SRC_TOP3, 20, 1),
617 MUX(0, "mout_user_pclk200_fsys", mout_user_pclk200_fsys_p,
618 SRC_TOP3, 24, 1),
619 MUX(0, "mout_user_aclk200_fsys", mout_user_aclk200_fsys_p,
353 SRC_TOP3, 28, 1), 620 SRC_TOP3, 28, 1),
354 621
355 MUX(0, "mout_user_aclk333_432_gscl", user_aclk333_432_gscl_p, 622 MUX(0, "mout_user_aclk333_432_gscl", mout_user_aclk333_432_gscl_p,
356 SRC_TOP4, 0, 1), 623 SRC_TOP4, 0, 1),
357 MUX(0, "mout_aclk66_peric", aclk66_peric_p, SRC_TOP4, 8, 1), 624 MUX(0, "mout_user_aclk333_432_isp", mout_user_aclk333_432_isp_p,
358 MUX(0, "mout_user_aclk266", user_aclk266_p, SRC_TOP4, 20, 1), 625 SRC_TOP4, 4, 1),
359 MUX(0, "mout_user_aclk166", user_aclk166_p, SRC_TOP4, 24, 1), 626 MUX(0, "mout_user_aclk66_peric", mout_user_aclk66_peric_p,
360 MUX(0, "mout_user_aclk333", user_aclk333_p, SRC_TOP4, 28, 1), 627 SRC_TOP4, 8, 1),
361 628 MUX(0, "mout_user_aclk333_432_isp0", mout_user_aclk333_432_isp0_p,
362 MUX(0, "mout_aclk66_psgen", aclk66_peric_p, SRC_TOP5, 4, 1), 629 SRC_TOP4, 12, 1),
363 MUX(0, "mout_user_aclk333_g2d", user_aclk333_g2d_p, SRC_TOP5, 8, 1), 630 MUX(0, "mout_user_aclk266_isp", mout_user_aclk266_isp_p,
364 MUX(0, "mout_user_aclk266_g2d", user_aclk266_g2d_p, SRC_TOP5, 12, 1), 631 SRC_TOP4, 16, 1),
365 MUX_A(0, "mout_user_aclk_g3d", user_aclk_g3d_p, 632 MUX(0, "mout_user_aclk266", mout_user_aclk266_p, SRC_TOP4, 20, 1),
366 SRC_TOP5, 16, 1, "aclkg3d"), 633 MUX(0, "mout_user_aclk166", mout_user_aclk166_p, SRC_TOP4, 24, 1),
367 MUX(0, "mout_user_aclk300_jpeg", user_aclk300_jpeg_p, 634 MUX(0, "mout_user_aclk333", mout_user_aclk333_p, SRC_TOP4, 28, 1),
635
636 MUX(0, "mout_user_aclk400_disp1", mout_user_aclk400_disp1_p,
637 SRC_TOP5, 0, 1),
638 MUX(0, "mout_user_aclk66_psgen", mout_user_aclk66_peric_p,
639 SRC_TOP5, 4, 1),
640 MUX(0, "mout_user_aclk333_g2d", mout_user_aclk333_g2d_p,
641 SRC_TOP5, 8, 1),
642 MUX(0, "mout_user_aclk266_g2d", mout_user_aclk266_g2d_p,
643 SRC_TOP5, 12, 1),
644 MUX(CLK_MOUT_G3D, "mout_user_aclk_g3d", mout_user_aclk_g3d_p,
645 SRC_TOP5, 16, 1),
646 MUX(0, "mout_user_aclk300_jpeg", mout_user_aclk300_jpeg_p,
368 SRC_TOP5, 20, 1), 647 SRC_TOP5, 20, 1),
369 MUX(0, "mout_user_aclk300_disp1", user_aclk300_disp1_p, 648 MUX(0, "mout_user_aclk300_disp1", mout_user_aclk300_disp1_p,
370 SRC_TOP5, 24, 1), 649 SRC_TOP5, 24, 1),
371 MUX(0, "mout_user_aclk300_gscl", user_aclk300_gscl_p, 650 MUX(0, "mout_user_aclk300_gscl", mout_user_aclk300_gscl_p,
372 SRC_TOP5, 28, 1), 651 SRC_TOP5, 28, 1),
373 652
374 MUX(0, "sclk_mpll", mpll_p, SRC_TOP6, 0, 1), 653 MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1),
375 MUX(0, "sclk_vpll", vpll_p, SRC_TOP6, 4, 1), 654 MUX(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1),
376 MUX(0, "sclk_spll", spll_p, SRC_TOP6, 8, 1), 655 MUX(0, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1),
377 MUX(0, "sclk_ipll", ipll_p, SRC_TOP6, 12, 1), 656 MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1),
378 MUX(0, "sclk_rpll", rpll_p, SRC_TOP6, 16, 1), 657 MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1),
379 MUX(0, "sclk_epll", epll_p, SRC_TOP6, 20, 1), 658 MUX(0, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1),
380 MUX(0, "sclk_dpll", dpll_p, SRC_TOP6, 24, 1), 659 MUX(0, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1),
381 MUX(0, "sclk_cpll", cpll_p, SRC_TOP6, 28, 1), 660 MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1),
382 661
383 MUX(0, "mout_sw_aclk400_mscl", sw_aclk400_mscl_p, SRC_TOP10, 4, 1), 662 MUX(0, "mout_sw_aclk400_isp", mout_sw_aclk400_isp_p,
384 MUX(0, "mout_sw_aclk200", sw_aclk200_p, SRC_TOP10, 8, 1), 663 SRC_TOP10, 0, 1),
385 MUX(0, "mout_sw_aclk200_fsys2", sw_aclk200_fsys2_p, 664 MUX(0, "mout_sw_aclk400_mscl", mout_sw_aclk400_mscl_p,
665 SRC_TOP10, 4, 1),
666 MUX(0, "mout_sw_aclk200", mout_sw_aclk200_p, SRC_TOP10, 8, 1),
667 MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p,
386 SRC_TOP10, 12, 1), 668 SRC_TOP10, 12, 1),
387 MUX(0, "mout_sw_aclk200_fsys", sw_aclk200_fsys_p, SRC_TOP10, 28, 1), 669 MUX(0, "mout_sw_aclk400_wcore", mout_sw_aclk400_wcore_p,
388 670 SRC_TOP10, 16, 1),
389 MUX(0, "mout_sw_aclk333_432_gscl", sw_aclk333_432_gscl_p, 671 MUX(0, "mout_sw_aclk100_noc", mout_sw_aclk100_noc_p,
672 SRC_TOP10, 20, 1),
673 MUX(0, "mout_sw_pclk200_fsys", mout_sw_pclk200_fsys_p,
674 SRC_TOP10, 24, 1),
675 MUX(0, "mout_sw_aclk200_fsys", mout_sw_aclk200_fsys_p,
676 SRC_TOP10, 28, 1),
677
678 MUX(0, "mout_sw_aclk333_432_gscl", mout_sw_aclk333_432_gscl_p,
390 SRC_TOP11, 0, 1), 679 SRC_TOP11, 0, 1),
391 MUX(0, "mout_sw_aclk66", sw_aclk66_p, SRC_TOP11, 8, 1), 680 MUX(0, "mout_sw_aclk333_432_isp", mout_sw_aclk333_432_isp_p,
392 MUX(0, "mout_sw_aclk266", sw_aclk266_p, SRC_TOP11, 20, 1), 681 SRC_TOP11, 4, 1),
393 MUX(0, "mout_sw_aclk166", sw_aclk166_p, SRC_TOP11, 24, 1), 682 MUX(0, "mout_sw_aclk66", mout_sw_aclk66_p, SRC_TOP11, 8, 1),
394 MUX(0, "mout_sw_aclk333", sw_aclk333_p, SRC_TOP11, 28, 1), 683 MUX(0, "mout_sw_aclk333_432_isp0", mout_sw_aclk333_432_isp0_p,
395 684 SRC_TOP11, 12, 1),
396 MUX(0, "mout_sw_aclk333_g2d", sw_aclk333_g2d_p, SRC_TOP12, 8, 1), 685 MUX(0, "mout_sw_aclk266", mout_sw_aclk266_p, SRC_TOP11, 20, 1),
397 MUX(0, "mout_sw_aclk266_g2d", sw_aclk266_g2d_p, SRC_TOP12, 12, 1), 686 MUX(0, "mout_sw_aclk166", mout_sw_aclk166_p, SRC_TOP11, 24, 1),
398 MUX(0, "mout_sw_aclk_g3d", sw_aclk_g3d_p, SRC_TOP12, 16, 1), 687 MUX(0, "mout_sw_aclk333", mout_sw_aclk333_p, SRC_TOP11, 28, 1),
399 MUX(0, "mout_sw_aclk300_jpeg", sw_aclk300_jpeg_p, SRC_TOP12, 20, 1), 688
400 MUX(0, "mout_sw_aclk300_disp1", sw_aclk300_disp1_p, 689 MUX(0, "mout_sw_aclk400_disp1", mout_sw_aclk400_disp1_p,
690 SRC_TOP12, 4, 1),
691 MUX(0, "mout_sw_aclk333_g2d", mout_sw_aclk333_g2d_p,
692 SRC_TOP12, 8, 1),
693 MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p,
694 SRC_TOP12, 12, 1),
695 MUX(0, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p, SRC_TOP12, 16, 1),
696 MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p,
697 SRC_TOP12, 20, 1),
698 MUX(0, "mout_sw_aclk300_disp1", mout_sw_aclk300_disp1_p,
401 SRC_TOP12, 24, 1), 699 SRC_TOP12, 24, 1),
402 MUX(0, "mout_sw_aclk300_gscl", sw_aclk300_gscl_p, SRC_TOP12, 28, 1), 700 MUX(0, "mout_sw_aclk300_gscl", mout_sw_aclk300_gscl_p,
701 SRC_TOP12, 28, 1),
403 702
404 /* DISP1 Block */ 703 /* DISP1 Block */
405 MUX(0, "mout_fimd1", group3_p, SRC_DISP10, 4, 1), 704 MUX(0, "mout_mipi1", mout_group2_p, SRC_DISP10, 16, 3),
406 MUX(0, "mout_mipi1", group2_p, SRC_DISP10, 16, 3), 705 MUX(0, "mout_dp1", mout_group2_p, SRC_DISP10, 20, 3),
407 MUX(0, "mout_dp1", group2_p, SRC_DISP10, 20, 3), 706 MUX(0, "mout_pixel", mout_group2_p, SRC_DISP10, 24, 3),
408 MUX(0, "mout_pixel", group2_p, SRC_DISP10, 24, 3), 707 MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_DISP10, 28, 1),
409 MUX(CLK_MOUT_HDMI, "mout_hdmi", hdmi_p, SRC_DISP10, 28, 1), 708 MUX(0, "mout_fimd1_opt", mout_group2_p, SRC_DISP10, 8, 3),
709
710 MUX(0, "mout_fimd1_final", mout_fimd1_final_p, TOP_SPARE2, 8, 1),
410 711
411 /* MAU Block */ 712 /* MAU Block */
412 MUX(0, "mout_maudio0", maudio0_p, SRC_MAU, 28, 3), 713 MUX(CLK_MOUT_MAUDIO0, "mout_maudio0", mout_maudio0_p, SRC_MAU, 28, 3),
413 714
414 /* FSYS Block */ 715 /* FSYS Block */
415 MUX(0, "mout_usbd301", group2_p, SRC_FSYS, 4, 3), 716 MUX(0, "mout_usbd301", mout_group2_p, SRC_FSYS, 4, 3),
416 MUX(0, "mout_mmc0", group2_p, SRC_FSYS, 8, 3), 717 MUX(0, "mout_mmc0", mout_group2_p, SRC_FSYS, 8, 3),
417 MUX(0, "mout_mmc1", group2_p, SRC_FSYS, 12, 3), 718 MUX(0, "mout_mmc1", mout_group2_p, SRC_FSYS, 12, 3),
418 MUX(0, "mout_mmc2", group2_p, SRC_FSYS, 16, 3), 719 MUX(0, "mout_mmc2", mout_group2_p, SRC_FSYS, 16, 3),
419 MUX(0, "mout_usbd300", group2_p, SRC_FSYS, 20, 3), 720 MUX(0, "mout_usbd300", mout_group2_p, SRC_FSYS, 20, 3),
420 MUX(0, "mout_unipro", group2_p, SRC_FSYS, 24, 3), 721 MUX(0, "mout_unipro", mout_group2_p, SRC_FSYS, 24, 3),
722 MUX(0, "mout_mphy_refclk", mout_group2_p, SRC_FSYS, 28, 3),
421 723
422 /* PERIC Block */ 724 /* PERIC Block */
423 MUX(0, "mout_uart0", group2_p, SRC_PERIC0, 4, 3), 725 MUX(0, "mout_uart0", mout_group2_p, SRC_PERIC0, 4, 3),
424 MUX(0, "mout_uart1", group2_p, SRC_PERIC0, 8, 3), 726 MUX(0, "mout_uart1", mout_group2_p, SRC_PERIC0, 8, 3),
425 MUX(0, "mout_uart2", group2_p, SRC_PERIC0, 12, 3), 727 MUX(0, "mout_uart2", mout_group2_p, SRC_PERIC0, 12, 3),
426 MUX(0, "mout_uart3", group2_p, SRC_PERIC0, 16, 3), 728 MUX(0, "mout_uart3", mout_group2_p, SRC_PERIC0, 16, 3),
427 MUX(0, "mout_pwm", group2_p, SRC_PERIC0, 24, 3), 729 MUX(0, "mout_pwm", mout_group2_p, SRC_PERIC0, 24, 3),
428 MUX(0, "mout_spdif", spdif_p, SRC_PERIC0, 28, 3), 730 MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC0, 28, 3),
429 MUX(0, "mout_audio0", audio0_p, SRC_PERIC1, 8, 3), 731 MUX(0, "mout_audio0", mout_audio0_p, SRC_PERIC1, 8, 3),
430 MUX(0, "mout_audio1", audio1_p, SRC_PERIC1, 12, 3), 732 MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 12, 3),
431 MUX(0, "mout_audio2", audio2_p, SRC_PERIC1, 16, 3), 733 MUX(0, "mout_audio2", mout_audio2_p, SRC_PERIC1, 16, 3),
432 MUX(0, "mout_spi0", group2_p, SRC_PERIC1, 20, 3), 734 MUX(0, "mout_spi0", mout_group2_p, SRC_PERIC1, 20, 3),
433 MUX(0, "mout_spi1", group2_p, SRC_PERIC1, 24, 3), 735 MUX(0, "mout_spi1", mout_group2_p, SRC_PERIC1, 24, 3),
434 MUX(0, "mout_spi2", group2_p, SRC_PERIC1, 28, 3), 736 MUX(0, "mout_spi2", mout_group2_p, SRC_PERIC1, 28, 3),
737
738 /* ISP Block */
739 MUX(0, "mout_pwm_isp", mout_group2_p, SRC_ISP, 24, 3),
740 MUX(0, "mout_uart_isp", mout_group2_p, SRC_ISP, 20, 3),
741 MUX(0, "mout_spi0_isp", mout_group2_p, SRC_ISP, 12, 3),
742 MUX(0, "mout_spi1_isp", mout_group2_p, SRC_ISP, 16, 3),
743 MUX(0, "mout_isp_sensor", mout_group2_p, SRC_ISP, 28, 3),
435}; 744};
436 745
437static struct samsung_div_clock exynos5420_div_clks[] __initdata = { 746static struct samsung_div_clock exynos5x_div_clks[] __initdata = {
438 DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3), 747 DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
439 DIV(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3), 748 DIV(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
440 DIV(0, "armclk2", "div_arm", DIV_CPU0, 28, 3), 749 DIV(0, "armclk2", "div_arm", DIV_CPU0, 28, 3),
441 DIV(0, "div_kfc", "mout_cpu_kfc", DIV_KFC0, 0, 3), 750 DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3),
442 DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3), 751 DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3),
443 752
753 DIV(0, "dout_aclk400_isp", "mout_aclk400_isp", DIV_TOP0, 0, 3),
444 DIV(0, "dout_aclk400_mscl", "mout_aclk400_mscl", DIV_TOP0, 4, 3), 754 DIV(0, "dout_aclk400_mscl", "mout_aclk400_mscl", DIV_TOP0, 4, 3),
445 DIV(0, "dout_aclk200", "mout_aclk200", DIV_TOP0, 8, 3), 755 DIV(0, "dout_aclk200", "mout_aclk200", DIV_TOP0, 8, 3),
446 DIV(0, "dout_aclk200_fsys2", "mout_aclk200_fsys2", DIV_TOP0, 12, 3), 756 DIV(0, "dout_aclk200_fsys2", "mout_aclk200_fsys2", DIV_TOP0, 12, 3),
757 DIV(0, "dout_aclk100_noc", "mout_aclk100_noc", DIV_TOP0, 20, 3),
447 DIV(0, "dout_pclk200_fsys", "mout_pclk200_fsys", DIV_TOP0, 24, 3), 758 DIV(0, "dout_pclk200_fsys", "mout_pclk200_fsys", DIV_TOP0, 24, 3),
448 DIV(0, "dout_aclk200_fsys", "mout_aclk200_fsys", DIV_TOP0, 28, 3), 759 DIV(0, "dout_aclk200_fsys", "mout_aclk200_fsys", DIV_TOP0, 28, 3),
449 760
450 DIV(0, "dout_aclk333_432_gscl", "mout_aclk333_432_gscl", 761 DIV(0, "dout_aclk333_432_gscl", "mout_aclk333_432_gscl",
451 DIV_TOP1, 0, 3), 762 DIV_TOP1, 0, 3),
763 DIV(0, "dout_aclk333_432_isp", "mout_aclk333_432_isp",
764 DIV_TOP1, 4, 3),
452 DIV(0, "dout_aclk66", "mout_aclk66", DIV_TOP1, 8, 6), 765 DIV(0, "dout_aclk66", "mout_aclk66", DIV_TOP1, 8, 6),
766 DIV(0, "dout_aclk333_432_isp0", "mout_aclk333_432_isp0",
767 DIV_TOP1, 16, 3),
453 DIV(0, "dout_aclk266", "mout_aclk266", DIV_TOP1, 20, 3), 768 DIV(0, "dout_aclk266", "mout_aclk266", DIV_TOP1, 20, 3),
454 DIV(0, "dout_aclk166", "mout_aclk166", DIV_TOP1, 24, 3), 769 DIV(0, "dout_aclk166", "mout_aclk166", DIV_TOP1, 24, 3),
455 DIV(0, "dout_aclk333", "mout_aclk333", DIV_TOP1, 28, 3), 770 DIV(0, "dout_aclk333", "mout_aclk333", DIV_TOP1, 28, 3),
@@ -458,15 +773,16 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = {
458 DIV(0, "dout_aclk266_g2d", "mout_aclk266_g2d", DIV_TOP2, 12, 3), 773 DIV(0, "dout_aclk266_g2d", "mout_aclk266_g2d", DIV_TOP2, 12, 3),
459 DIV(0, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, 16, 3), 774 DIV(0, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, 16, 3),
460 DIV(0, "dout_aclk300_jpeg", "mout_aclk300_jpeg", DIV_TOP2, 20, 3), 775 DIV(0, "dout_aclk300_jpeg", "mout_aclk300_jpeg", DIV_TOP2, 20, 3),
461 DIV_A(0, "dout_aclk300_disp1", "mout_aclk300_disp1", 776 DIV(0, "dout_aclk300_disp1", "mout_aclk300_disp1", DIV_TOP2, 24, 3),
462 DIV_TOP2, 24, 3, "aclk300_disp1"),
463 DIV(0, "dout_aclk300_gscl", "mout_aclk300_gscl", DIV_TOP2, 28, 3), 777 DIV(0, "dout_aclk300_gscl", "mout_aclk300_gscl", DIV_TOP2, 28, 3),
464 778
465 /* DISP1 Block */ 779 /* DISP1 Block */
466 DIV(0, "dout_fimd1", "mout_fimd1", DIV_DISP10, 0, 4), 780 DIV(0, "dout_fimd1", "mout_fimd1_final", DIV_DISP10, 0, 4),
467 DIV(0, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8), 781 DIV(0, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8),
468 DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4), 782 DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4),
469 DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4), 783 DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4),
784 DIV(0, "dout_disp1_blk", "aclk200_disp1", DIV2_RATIO0, 16, 2),
785 DIV(0, "dout_aclk400_disp1", "mout_aclk400_disp1", DIV_TOP2, 4, 3),
470 786
471 /* Audio Block */ 787 /* Audio Block */
472 DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4), 788 DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),
@@ -484,6 +800,7 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = {
484 DIV(0, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10), 800 DIV(0, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10),
485 801
486 DIV(0, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8), 802 DIV(0, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8),
803 DIV(0, "dout_mphy_refclk", "mout_mphy_refclk", DIV_FSYS2, 16, 8),
487 804
488 /* UART and PWM */ 805 /* UART and PWM */
489 DIV(0, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4), 806 DIV(0, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4),
@@ -497,6 +814,9 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = {
497 DIV(0, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4), 814 DIV(0, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4),
498 DIV(0, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4), 815 DIV(0, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4),
499 816
817 /* Mfc Block */
818 DIV(0, "dout_mfc_blk", "mout_user_aclk333", DIV4_RATIO, 0, 2),
819
500 /* PCM */ 820 /* PCM */
501 DIV(0, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8), 821 DIV(0, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8),
502 DIV(0, "dout_pcm2", "dout_audio2", DIV_PERIC2, 24, 8), 822 DIV(0, "dout_pcm2", "dout_audio2", DIV_PERIC2, 24, 8),
@@ -509,15 +829,43 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = {
509 DIV(0, "dout_audio2", "mout_audio2", DIV_PERIC3, 28, 4), 829 DIV(0, "dout_audio2", "mout_audio2", DIV_PERIC3, 28, 4),
510 830
511 /* SPI Pre-Ratio */ 831 /* SPI Pre-Ratio */
512 DIV(0, "dout_pre_spi0", "dout_spi0", DIV_PERIC4, 8, 8), 832 DIV(0, "dout_spi0_pre", "dout_spi0", DIV_PERIC4, 8, 8),
513 DIV(0, "dout_pre_spi1", "dout_spi1", DIV_PERIC4, 16, 8), 833 DIV(0, "dout_spi1_pre", "dout_spi1", DIV_PERIC4, 16, 8),
514 DIV(0, "dout_pre_spi2", "dout_spi2", DIV_PERIC4, 24, 8), 834 DIV(0, "dout_spi2_pre", "dout_spi2", DIV_PERIC4, 24, 8),
835
836 /* GSCL Block */
837 DIV(0, "dout_gscl_blk_300", "mout_user_aclk300_gscl",
838 DIV2_RATIO0, 4, 2),
839 DIV(0, "dout_gscl_blk_333", "aclk333_432_gscl", DIV2_RATIO0, 6, 2),
840
841 /* MSCL Block */
842 DIV(0, "dout_mscl_blk", "aclk400_mscl", DIV2_RATIO0, 28, 2),
843
844 /* PSGEN */
845 DIV(0, "dout_gen_blk", "mout_user_aclk266", DIV2_RATIO0, 8, 1),
846 DIV(0, "dout_jpg_blk", "aclk166", DIV2_RATIO0, 20, 1),
847
848 /* ISP Block */
849 DIV(0, "dout_isp_sensor0", "mout_isp_sensor", SCLK_DIV_ISP0, 8, 8),
850 DIV(0, "dout_isp_sensor1", "mout_isp_sensor", SCLK_DIV_ISP0, 16, 8),
851 DIV(0, "dout_isp_sensor2", "mout_isp_sensor", SCLK_DIV_ISP0, 24, 8),
852 DIV(0, "dout_pwm_isp", "mout_pwm_isp", SCLK_DIV_ISP1, 28, 4),
853 DIV(0, "dout_uart_isp", "mout_uart_isp", SCLK_DIV_ISP1, 24, 4),
854 DIV(0, "dout_spi0_isp", "mout_spi0_isp", SCLK_DIV_ISP1, 16, 4),
855 DIV(0, "dout_spi1_isp", "mout_spi1_isp", SCLK_DIV_ISP1, 20, 4),
856 DIV_F(0, "dout_spi0_isp_pre", "dout_spi0_isp", SCLK_DIV_ISP1, 0, 8,
857 CLK_SET_RATE_PARENT, 0),
858 DIV_F(0, "dout_spi1_isp_pre", "dout_spi1_isp", SCLK_DIV_ISP1, 8, 8,
859 CLK_SET_RATE_PARENT, 0),
515}; 860};
516 861
517static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { 862static struct samsung_gate_clock exynos5x_gate_clks[] __initdata = {
518 /* TODO: Re-verify the CG bits for all the gate clocks */ 863 /* G2D */
519 GATE_A(CLK_MCT, "pclk_st", "aclk66_psgen", GATE_BUS_PERIS1, 2, 0, 0, 864 GATE(CLK_MDMA0, "mdma0", "aclk266_g2d", GATE_IP_G2D, 1, 0, 0),
520 "mct"), 865 GATE(CLK_SSS, "sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0),
866 GATE(CLK_G2D, "g2d", "aclk333_g2d", GATE_IP_G2D, 3, 0, 0),
867 GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "aclk266_g2d", GATE_IP_G2D, 5, 0, 0),
868 GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk333_g2d", GATE_IP_G2D, 7, 0, 0),
521 869
522 GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys", 870 GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys",
523 GATE_BUS_FSYS0, 9, CLK_IGNORE_UNUSED, 0), 871 GATE_BUS_FSYS0, 9, CLK_IGNORE_UNUSED, 0),
@@ -530,20 +878,42 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
530 GATE_BUS_TOP, 1, CLK_IGNORE_UNUSED, 0), 878 GATE_BUS_TOP, 1, CLK_IGNORE_UNUSED, 0),
531 GATE(0, "aclk300_jpeg", "mout_user_aclk300_jpeg", 879 GATE(0, "aclk300_jpeg", "mout_user_aclk300_jpeg",
532 GATE_BUS_TOP, 4, CLK_IGNORE_UNUSED, 0), 880 GATE_BUS_TOP, 4, CLK_IGNORE_UNUSED, 0),
881 GATE(0, "aclk333_432_isp0", "mout_user_aclk333_432_isp0",
882 GATE_BUS_TOP, 5, 0, 0),
533 GATE(0, "aclk300_gscl", "mout_user_aclk300_gscl", 883 GATE(0, "aclk300_gscl", "mout_user_aclk300_gscl",
534 GATE_BUS_TOP, 6, CLK_IGNORE_UNUSED, 0), 884 GATE_BUS_TOP, 6, CLK_IGNORE_UNUSED, 0),
535 GATE(0, "aclk333_432_gscl", "mout_user_aclk333_432_gscl", 885 GATE(0, "aclk333_432_gscl", "mout_user_aclk333_432_gscl",
536 GATE_BUS_TOP, 7, CLK_IGNORE_UNUSED, 0), 886 GATE_BUS_TOP, 7, CLK_IGNORE_UNUSED, 0),
537 GATE(0, "pclk66_gpio", "mout_sw_aclk66", 887 GATE(0, "aclk333_432_isp", "mout_user_aclk333_432_isp",
888 GATE_BUS_TOP, 8, 0, 0),
889 GATE(CLK_PCLK66_GPIO, "pclk66_gpio", "mout_user_pclk66_gpio",
538 GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0), 890 GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0),
539 GATE(0, "aclk66_psgen", "mout_aclk66_psgen", 891 GATE(0, "aclk66_psgen", "mout_user_aclk66_psgen",
540 GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0), 892 GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0),
541 GATE(0, "aclk66_peric", "mout_aclk66_peric", 893 GATE(CLK_ACLK66_PERIC, "aclk66_peric", "mout_user_aclk66_peric",
542 GATE_BUS_TOP, 11, 0, 0), 894 GATE_BUS_TOP, 11, CLK_IGNORE_UNUSED, 0),
895 GATE(0, "aclk266_isp", "mout_user_aclk266_isp",
896 GATE_BUS_TOP, 13, 0, 0),
543 GATE(0, "aclk166", "mout_user_aclk166", 897 GATE(0, "aclk166", "mout_user_aclk166",
544 GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0), 898 GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0),
545 GATE(0, "aclk333", "mout_aclk333", 899 GATE(0, "aclk333", "mout_aclk333",
546 GATE_BUS_TOP, 15, CLK_IGNORE_UNUSED, 0), 900 GATE_BUS_TOP, 15, CLK_IGNORE_UNUSED, 0),
901 GATE(0, "aclk400_isp", "mout_user_aclk400_isp",
902 GATE_BUS_TOP, 16, 0, 0),
903 GATE(0, "aclk400_mscl", "mout_user_aclk400_mscl",
904 GATE_BUS_TOP, 17, 0, 0),
905 GATE(0, "aclk200_disp1", "mout_user_aclk200_disp1",
906 GATE_BUS_TOP, 18, 0, 0),
907 GATE(CLK_SCLK_MPHY_IXTAL24, "sclk_mphy_ixtal24", "mphy_refclk_ixtal24",
908 GATE_BUS_TOP, 28, 0, 0),
909 GATE(CLK_SCLK_HSIC_12M, "sclk_hsic_12m", "ff_hsic_12m",
910 GATE_BUS_TOP, 29, 0, 0),
911
912 GATE(0, "aclk300_disp1", "mout_user_aclk300_disp1",
913 SRC_MASK_TOP2, 24, 0, 0),
914
915 GATE(CLK_MAU_EPLL, "mau_epll", "mout_mau_epll_clk",
916 SRC_MASK_TOP7, 20, 0, 0),
547 917
548 /* sclk */ 918 /* sclk */
549 GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_uart0", 919 GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_uart0",
@@ -554,11 +924,11 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
554 GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0), 924 GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0),
555 GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_uart3", 925 GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_uart3",
556 GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0), 926 GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0),
557 GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_pre_spi0", 927 GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_spi0_pre",
558 GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0), 928 GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0),
559 GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_pre_spi1", 929 GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_spi1_pre",
560 GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0), 930 GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
561 GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_pre_spi2", 931 GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_spi2_pre",
562 GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0), 932 GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
563 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif", 933 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif",
564 GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0), 934 GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0),
@@ -588,164 +958,191 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
588 GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301", 958 GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301",
589 GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0), 959 GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0),
590 960
591 GATE(CLK_SCLK_USBD301, "sclk_unipro", "dout_unipro",
592 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
593
594 GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "aclK333_432_gscl",
595 GATE_TOP_SCLK_GSCL, 6, CLK_SET_RATE_PARENT, 0),
596 GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "aclk333_432_gscl",
597 GATE_TOP_SCLK_GSCL, 7, CLK_SET_RATE_PARENT, 0),
598
599 /* Display */ 961 /* Display */
600 GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "dout_fimd1", 962 GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "dout_fimd1",
601 GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0), 963 GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0),
602 GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "dout_mipi1", 964 GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "dout_mipi1",
603 GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0), 965 GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0),
604 GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", 966 GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi",
605 GATE_TOP_SCLK_DISP1, 9, CLK_SET_RATE_PARENT, 0), 967 GATE_TOP_SCLK_DISP1, 9, 0, 0),
606 GATE(CLK_SCLK_PIXEL, "sclk_pixel", "dout_hdmi_pixel", 968 GATE(CLK_SCLK_PIXEL, "sclk_pixel", "dout_hdmi_pixel",
607 GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0), 969 GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0),
608 GATE(CLK_SCLK_DP1, "sclk_dp1", "dout_dp1", 970 GATE(CLK_SCLK_DP1, "sclk_dp1", "dout_dp1",
609 GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0), 971 GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0),
610 972
611 /* Maudio Block */ 973 /* Maudio Block */
612 GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0", 974 GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0",
613 GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0), 975 GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0),
614 GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0", 976 GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0",
615 GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0), 977 GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0),
616 /* FSYS */ 978
979 /* FSYS Block */
617 GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0), 980 GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0),
618 GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0), 981 GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
619 GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0), 982 GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
620 GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0), 983 GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0),
621 GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_BUS_FSYS0, 5, 0, 0), 984 GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_IP_FSYS, 9, 0, 0),
622 GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_BUS_FSYS0, 12, 0, 0), 985 GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_IP_FSYS, 12, 0, 0),
623 GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_BUS_FSYS0, 13, 0, 0), 986 GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_IP_FSYS, 13, 0, 0),
624 GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_BUS_FSYS0, 14, 0, 0), 987 GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_IP_FSYS, 14, 0, 0),
625 GATE(CLK_SROMC, "sromc", "aclk200_fsys2", 988 GATE(CLK_SROMC, "sromc", "aclk200_fsys2",
626 GATE_BUS_FSYS0, 19, CLK_IGNORE_UNUSED, 0), 989 GATE_IP_FSYS, 17, CLK_IGNORE_UNUSED, 0),
627 GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_BUS_FSYS0, 20, 0, 0), 990 GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0),
628 GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_BUS_FSYS0, 21, 0, 0), 991 GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0),
629 GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_BUS_FSYS0, 28, 0, 0), 992 GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0),
630 993 GATE(CLK_SCLK_UNIPRO, "sclk_unipro", "dout_unipro",
631 /* UART */ 994 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
632 GATE(CLK_UART0, "uart0", "aclk66_peric", GATE_BUS_PERIC, 4, 0, 0),
633 GATE(CLK_UART1, "uart1", "aclk66_peric", GATE_BUS_PERIC, 5, 0, 0),
634 GATE_A(CLK_UART2, "uart2", "aclk66_peric",
635 GATE_BUS_PERIC, 6, CLK_IGNORE_UNUSED, 0, "uart2"),
636 GATE(CLK_UART3, "uart3", "aclk66_peric", GATE_BUS_PERIC, 7, 0, 0),
637 /* I2C */
638 GATE(CLK_I2C0, "i2c0", "aclk66_peric", GATE_BUS_PERIC, 9, 0, 0),
639 GATE(CLK_I2C1, "i2c1", "aclk66_peric", GATE_BUS_PERIC, 10, 0, 0),
640 GATE(CLK_I2C2, "i2c2", "aclk66_peric", GATE_BUS_PERIC, 11, 0, 0),
641 GATE(CLK_I2C3, "i2c3", "aclk66_peric", GATE_BUS_PERIC, 12, 0, 0),
642 GATE(CLK_I2C4, "i2c4", "aclk66_peric", GATE_BUS_PERIC, 13, 0, 0),
643 GATE(CLK_I2C5, "i2c5", "aclk66_peric", GATE_BUS_PERIC, 14, 0, 0),
644 GATE(CLK_I2C6, "i2c6", "aclk66_peric", GATE_BUS_PERIC, 15, 0, 0),
645 GATE(CLK_I2C7, "i2c7", "aclk66_peric", GATE_BUS_PERIC, 16, 0, 0),
646 GATE(CLK_I2C_HDMI, "i2c_hdmi", "aclk66_peric", GATE_BUS_PERIC, 17, 0,
647 0),
648 GATE(CLK_TSADC, "tsadc", "aclk66_peric", GATE_BUS_PERIC, 18, 0, 0),
649 /* SPI */
650 GATE(CLK_SPI0, "spi0", "aclk66_peric", GATE_BUS_PERIC, 19, 0, 0),
651 GATE(CLK_SPI1, "spi1", "aclk66_peric", GATE_BUS_PERIC, 20, 0, 0),
652 GATE(CLK_SPI2, "spi2", "aclk66_peric", GATE_BUS_PERIC, 21, 0, 0),
653 GATE(CLK_KEYIF, "keyif", "aclk66_peric", GATE_BUS_PERIC, 22, 0, 0),
654 /* I2S */
655 GATE(CLK_I2S1, "i2s1", "aclk66_peric", GATE_BUS_PERIC, 23, 0, 0),
656 GATE(CLK_I2S2, "i2s2", "aclk66_peric", GATE_BUS_PERIC, 24, 0, 0),
657 /* PCM */
658 GATE(CLK_PCM1, "pcm1", "aclk66_peric", GATE_BUS_PERIC, 25, 0, 0),
659 GATE(CLK_PCM2, "pcm2", "aclk66_peric", GATE_BUS_PERIC, 26, 0, 0),
660 /* PWM */
661 GATE(CLK_PWM, "pwm", "aclk66_peric", GATE_BUS_PERIC, 27, 0, 0),
662 /* SPDIF */
663 GATE(CLK_SPDIF, "spdif", "aclk66_peric", GATE_BUS_PERIC, 29, 0, 0),
664 995
665 GATE(CLK_I2C8, "i2c8", "aclk66_peric", GATE_BUS_PERIC1, 0, 0, 0), 996 /* PERIC Block */
666 GATE(CLK_I2C9, "i2c9", "aclk66_peric", GATE_BUS_PERIC1, 1, 0, 0), 997 GATE(CLK_UART0, "uart0", "aclk66_peric", GATE_IP_PERIC, 0, 0, 0),
667 GATE(CLK_I2C10, "i2c10", "aclk66_peric", GATE_BUS_PERIC1, 2, 0, 0), 998 GATE(CLK_UART1, "uart1", "aclk66_peric", GATE_IP_PERIC, 1, 0, 0),
999 GATE(CLK_UART2, "uart2", "aclk66_peric", GATE_IP_PERIC, 2, 0, 0),
1000 GATE(CLK_UART3, "uart3", "aclk66_peric", GATE_IP_PERIC, 3, 0, 0),
1001 GATE(CLK_I2C0, "i2c0", "aclk66_peric", GATE_IP_PERIC, 6, 0, 0),
1002 GATE(CLK_I2C1, "i2c1", "aclk66_peric", GATE_IP_PERIC, 7, 0, 0),
1003 GATE(CLK_I2C2, "i2c2", "aclk66_peric", GATE_IP_PERIC, 8, 0, 0),
1004 GATE(CLK_I2C3, "i2c3", "aclk66_peric", GATE_IP_PERIC, 9, 0, 0),
1005 GATE(CLK_USI0, "usi0", "aclk66_peric", GATE_IP_PERIC, 10, 0, 0),
1006 GATE(CLK_USI1, "usi1", "aclk66_peric", GATE_IP_PERIC, 11, 0, 0),
1007 GATE(CLK_USI2, "usi2", "aclk66_peric", GATE_IP_PERIC, 12, 0, 0),
1008 GATE(CLK_USI3, "usi3", "aclk66_peric", GATE_IP_PERIC, 13, 0, 0),
1009 GATE(CLK_I2C_HDMI, "i2c_hdmi", "aclk66_peric", GATE_IP_PERIC, 14, 0, 0),
1010 GATE(CLK_TSADC, "tsadc", "aclk66_peric", GATE_IP_PERIC, 15, 0, 0),
1011 GATE(CLK_SPI0, "spi0", "aclk66_peric", GATE_IP_PERIC, 16, 0, 0),
1012 GATE(CLK_SPI1, "spi1", "aclk66_peric", GATE_IP_PERIC, 17, 0, 0),
1013 GATE(CLK_SPI2, "spi2", "aclk66_peric", GATE_IP_PERIC, 18, 0, 0),
1014 GATE(CLK_I2S1, "i2s1", "aclk66_peric", GATE_IP_PERIC, 20, 0, 0),
1015 GATE(CLK_I2S2, "i2s2", "aclk66_peric", GATE_IP_PERIC, 21, 0, 0),
1016 GATE(CLK_PCM1, "pcm1", "aclk66_peric", GATE_IP_PERIC, 22, 0, 0),
1017 GATE(CLK_PCM2, "pcm2", "aclk66_peric", GATE_IP_PERIC, 23, 0, 0),
1018 GATE(CLK_PWM, "pwm", "aclk66_peric", GATE_IP_PERIC, 24, 0, 0),
1019 GATE(CLK_SPDIF, "spdif", "aclk66_peric", GATE_IP_PERIC, 26, 0, 0),
1020 GATE(CLK_USI4, "usi4", "aclk66_peric", GATE_IP_PERIC, 28, 0, 0),
1021 GATE(CLK_USI5, "usi5", "aclk66_peric", GATE_IP_PERIC, 30, 0, 0),
1022 GATE(CLK_USI6, "usi6", "aclk66_peric", GATE_IP_PERIC, 31, 0, 0),
668 1023
1024 GATE(CLK_KEYIF, "keyif", "aclk66_peric", GATE_BUS_PERIC, 22, 0, 0),
1025
1026 /* PERIS Block */
669 GATE(CLK_CHIPID, "chipid", "aclk66_psgen", 1027 GATE(CLK_CHIPID, "chipid", "aclk66_psgen",
670 GATE_BUS_PERIS0, 12, CLK_IGNORE_UNUSED, 0), 1028 GATE_IP_PERIS, 0, CLK_IGNORE_UNUSED, 0),
671 GATE(CLK_SYSREG, "sysreg", "aclk66_psgen", 1029 GATE(CLK_SYSREG, "sysreg", "aclk66_psgen",
672 GATE_BUS_PERIS0, 13, CLK_IGNORE_UNUSED, 0), 1030 GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0),
673 GATE(CLK_TZPC0, "tzpc0", "aclk66_psgen", GATE_BUS_PERIS0, 18, 0, 0), 1031 GATE(CLK_TZPC0, "tzpc0", "aclk66_psgen", GATE_IP_PERIS, 6, 0, 0),
674 GATE(CLK_TZPC1, "tzpc1", "aclk66_psgen", GATE_BUS_PERIS0, 19, 0, 0), 1032 GATE(CLK_TZPC1, "tzpc1", "aclk66_psgen", GATE_IP_PERIS, 7, 0, 0),
675 GATE(CLK_TZPC2, "tzpc2", "aclk66_psgen", GATE_BUS_PERIS0, 20, 0, 0), 1033 GATE(CLK_TZPC2, "tzpc2", "aclk66_psgen", GATE_IP_PERIS, 8, 0, 0),
676 GATE(CLK_TZPC3, "tzpc3", "aclk66_psgen", GATE_BUS_PERIS0, 21, 0, 0), 1034 GATE(CLK_TZPC3, "tzpc3", "aclk66_psgen", GATE_IP_PERIS, 9, 0, 0),
677 GATE(CLK_TZPC4, "tzpc4", "aclk66_psgen", GATE_BUS_PERIS0, 22, 0, 0), 1035 GATE(CLK_TZPC4, "tzpc4", "aclk66_psgen", GATE_IP_PERIS, 10, 0, 0),
678 GATE(CLK_TZPC5, "tzpc5", "aclk66_psgen", GATE_BUS_PERIS0, 23, 0, 0), 1036 GATE(CLK_TZPC5, "tzpc5", "aclk66_psgen", GATE_IP_PERIS, 11, 0, 0),
679 GATE(CLK_TZPC6, "tzpc6", "aclk66_psgen", GATE_BUS_PERIS0, 24, 0, 0), 1037 GATE(CLK_TZPC6, "tzpc6", "aclk66_psgen", GATE_IP_PERIS, 12, 0, 0),
680 GATE(CLK_TZPC7, "tzpc7", "aclk66_psgen", GATE_BUS_PERIS0, 25, 0, 0), 1038 GATE(CLK_TZPC7, "tzpc7", "aclk66_psgen", GATE_IP_PERIS, 13, 0, 0),
681 GATE(CLK_TZPC8, "tzpc8", "aclk66_psgen", GATE_BUS_PERIS0, 26, 0, 0), 1039 GATE(CLK_TZPC8, "tzpc8", "aclk66_psgen", GATE_IP_PERIS, 14, 0, 0),
682 GATE(CLK_TZPC9, "tzpc9", "aclk66_psgen", GATE_BUS_PERIS0, 27, 0, 0), 1040 GATE(CLK_TZPC9, "tzpc9", "aclk66_psgen", GATE_IP_PERIS, 15, 0, 0),
683 1041 GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk66_psgen", GATE_IP_PERIS, 16, 0, 0),
684 GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk66_psgen", GATE_BUS_PERIS1, 0, 0, 1042 GATE(CLK_MCT, "mct", "aclk66_psgen", GATE_IP_PERIS, 18, 0, 0),
685 0), 1043 GATE(CLK_WDT, "wdt", "aclk66_psgen", GATE_IP_PERIS, 19, 0, 0),
1044 GATE(CLK_RTC, "rtc", "aclk66_psgen", GATE_IP_PERIS, 20, 0, 0),
1045 GATE(CLK_TMU, "tmu", "aclk66_psgen", GATE_IP_PERIS, 21, 0, 0),
1046 GATE(CLK_TMU_GPU, "tmu_gpu", "aclk66_psgen", GATE_IP_PERIS, 22, 0, 0),
1047
686 GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0), 1048 GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0),
687 GATE(CLK_WDT, "wdt", "aclk66_psgen", GATE_BUS_PERIS1, 3, 0, 0), 1049
688 GATE(CLK_RTC, "rtc", "aclk66_psgen", GATE_BUS_PERIS1, 4, 0, 0), 1050 /* GEN Block */
689 GATE(CLK_TMU, "tmu", "aclk66_psgen", GATE_BUS_PERIS1, 5, 0, 0), 1051 GATE(CLK_ROTATOR, "rotator", "mout_user_aclk266", GATE_IP_GEN, 1, 0, 0),
690 GATE(CLK_TMU_GPU, "tmu_gpu", "aclk66_psgen", GATE_BUS_PERIS1, 6, 0, 0), 1052 GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0),
1053 GATE(CLK_JPEG2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0),
1054 GATE(CLK_MDMA1, "mdma1", "mout_user_aclk266", GATE_IP_GEN, 4, 0, 0),
1055 GATE(CLK_TOP_RTC, "top_rtc", "aclk66_psgen", GATE_IP_GEN, 5, 0, 0),
1056 GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "dout_gen_blk",
1057 GATE_IP_GEN, 6, 0, 0),
1058 GATE(CLK_SMMU_JPEG, "smmu_jpeg", "dout_jpg_blk", GATE_IP_GEN, 7, 0, 0),
1059 GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "dout_gen_blk",
1060 GATE_IP_GEN, 9, 0, 0),
1061
1062 /* GATE_IP_GEN doesn't list gates for smmu_jpeg2 and mc */
1063 GATE(CLK_SMMU_JPEG2, "smmu_jpeg2", "dout_jpg_blk",
1064 GATE_BUS_GEN, 28, 0, 0),
1065 GATE(CLK_MC, "mc", "aclk66_psgen", GATE_BUS_GEN, 12, 0, 0),
1066
1067 /* GSCL Block */
1068 GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "mout_user_aclk333_432_gscl",
1069 GATE_TOP_SCLK_GSCL, 6, 0, 0),
1070 GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "mout_user_aclk333_432_gscl",
1071 GATE_TOP_SCLK_GSCL, 7, 0, 0),
691 1072
692 GATE(CLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0), 1073 GATE(CLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0),
693 GATE(CLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0), 1074 GATE(CLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0),
694 GATE(CLK_CLK_3AA, "clk_3aa", "aclk300_gscl", GATE_IP_GSCL0, 4, 0, 0), 1075 GATE(CLK_FIMC_3AA, "fimc_3aa", "aclk333_432_gscl",
695 1076 GATE_IP_GSCL0, 4, 0, 0),
696 GATE(CLK_SMMU_3AA, "smmu_3aa", "aclk333_432_gscl", GATE_IP_GSCL1, 2, 0, 1077 GATE(CLK_FIMC_LITE0, "fimc_lite0", "aclk333_432_gscl",
697 0), 1078 GATE_IP_GSCL0, 5, 0, 0),
698 GATE(CLK_SMMU_FIMCL0, "smmu_fimcl0", "aclk333_432_gscl", 1079 GATE(CLK_FIMC_LITE1, "fimc_lite1", "aclk333_432_gscl",
1080 GATE_IP_GSCL0, 6, 0, 0),
1081
1082 GATE(CLK_SMMU_3AA, "smmu_3aa", "dout_gscl_blk_333",
1083 GATE_IP_GSCL1, 2, 0, 0),
1084 GATE(CLK_SMMU_FIMCL0, "smmu_fimcl0", "dout_gscl_blk_333",
699 GATE_IP_GSCL1, 3, 0, 0), 1085 GATE_IP_GSCL1, 3, 0, 0),
700 GATE(CLK_SMMU_FIMCL1, "smmu_fimcl1", "aclk333_432_gscl", 1086 GATE(CLK_SMMU_FIMCL1, "smmu_fimcl1", "dout_gscl_blk_333",
701 GATE_IP_GSCL1, 4, 0, 0), 1087 GATE_IP_GSCL1, 4, 0, 0),
702 GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "aclk300_gscl", GATE_IP_GSCL1, 6, 0, 1088 GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "dout_gscl_blk_300",
703 0), 1089 GATE_IP_GSCL1, 6, 0, 0),
704 GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "aclk300_gscl", GATE_IP_GSCL1, 7, 0, 1090 GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "dout_gscl_blk_300",
705 0), 1091 GATE_IP_GSCL1, 7, 0, 0),
706 GATE(CLK_GSCL_WA, "gscl_wa", "aclk300_gscl", GATE_IP_GSCL1, 12, 0, 0), 1092 GATE(CLK_GSCL_WA, "gscl_wa", "sclk_gscl_wa", GATE_IP_GSCL1, 12, 0, 0),
707 GATE(CLK_GSCL_WB, "gscl_wb", "aclk300_gscl", GATE_IP_GSCL1, 13, 0, 0), 1093 GATE(CLK_GSCL_WB, "gscl_wb", "sclk_gscl_wb", GATE_IP_GSCL1, 13, 0, 0),
708 GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3,", "aclk333_432_gscl", 1094 GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3,", "dout_gscl_blk_333",
709 GATE_IP_GSCL1, 16, 0, 0), 1095 GATE_IP_GSCL1, 16, 0, 0),
710 GATE(CLK_FIMC_LITE3, "fimc_lite3", "aclk333_432_gscl", 1096 GATE(CLK_FIMC_LITE3, "fimc_lite3", "aclk333_432_gscl",
711 GATE_IP_GSCL1, 17, 0, 0), 1097 GATE_IP_GSCL1, 17, 0, 0),
712 1098
1099 /* MSCL Block */
1100 GATE(CLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0),
1101 GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0),
1102 GATE(CLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0),
1103 GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "dout_mscl_blk",
1104 GATE_IP_MSCL, 8, 0, 0),
1105 GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "dout_mscl_blk",
1106 GATE_IP_MSCL, 9, 0, 0),
1107 GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "dout_mscl_blk",
1108 GATE_IP_MSCL, 10, 0, 0),
1109
713 GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0), 1110 GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0),
714 GATE(CLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0), 1111 GATE(CLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0),
715 GATE(CLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0), 1112 GATE(CLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0),
716 GATE(CLK_MIXER, "mixer", "aclk166", GATE_IP_DISP1, 5, 0, 0), 1113 GATE(CLK_MIXER, "mixer", "aclk200_disp1", GATE_IP_DISP1, 5, 0, 0),
717 GATE(CLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0), 1114 GATE(CLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0),
718 GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "aclk300_disp1", GATE_IP_DISP1, 8, 0, 1115 GATE(CLK_SMMU_FIMD1M0, "smmu_fimd1m0", "dout_disp1_blk",
719 0), 1116 GATE_IP_DISP1, 7, 0, 0),
1117 GATE(CLK_SMMU_FIMD1M1, "smmu_fimd1m1", "dout_disp1_blk",
1118 GATE_IP_DISP1, 8, 0, 0),
1119 GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1",
1120 GATE_IP_DISP1, 9, 0, 0),
1121
1122 /* ISP */
1123 GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "dout_uart_isp",
1124 GATE_TOP_SCLK_ISP, 0, CLK_SET_RATE_PARENT, 0),
1125 GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "dout_spi0_isp_pre",
1126 GATE_TOP_SCLK_ISP, 1, CLK_SET_RATE_PARENT, 0),
1127 GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "dout_spi1_isp_pre",
1128 GATE_TOP_SCLK_ISP, 2, CLK_SET_RATE_PARENT, 0),
1129 GATE(CLK_SCLK_PWM_ISP, "sclk_pwm_isp", "dout_pwm_isp",
1130 GATE_TOP_SCLK_ISP, 3, CLK_SET_RATE_PARENT, 0),
1131 GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "dout_isp_sensor0",
1132 GATE_TOP_SCLK_ISP, 4, CLK_SET_RATE_PARENT, 0),
1133 GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "dout_isp_sensor1",
1134 GATE_TOP_SCLK_ISP, 8, CLK_SET_RATE_PARENT, 0),
1135 GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "dout_isp_sensor2",
1136 GATE_TOP_SCLK_ISP, 12, CLK_SET_RATE_PARENT, 0),
720 1137
721 GATE(CLK_MFC, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0), 1138 GATE(CLK_MFC, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0),
722 GATE(CLK_SMMU_MFCL, "smmu_mfcl", "aclk333", GATE_IP_MFC, 1, 0, 0), 1139 GATE(CLK_SMMU_MFCL, "smmu_mfcl", "dout_mfc_blk", GATE_IP_MFC, 1, 0, 0),
723 GATE(CLK_SMMU_MFCR, "smmu_mfcr", "aclk333", GATE_IP_MFC, 2, 0, 0), 1140 GATE(CLK_SMMU_MFCR, "smmu_mfcr", "dout_mfc_blk", GATE_IP_MFC, 2, 0, 0),
724
725 GATE(CLK_G3D, "g3d", "aclkg3d", GATE_IP_G3D, 9, 0, 0),
726 1141
727 GATE(CLK_ROTATOR, "rotator", "aclk266", GATE_IP_GEN, 1, 0, 0), 1142 GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0),
728 GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0),
729 GATE(CLK_JPEG2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0),
730 GATE(CLK_MDMA1, "mdma1", "aclk266", GATE_IP_GEN, 4, 0, 0),
731 GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "aclk266", GATE_IP_GEN, 6, 0, 0),
732 GATE(CLK_SMMU_JPEG, "smmu_jpeg", "aclk300_jpeg", GATE_IP_GEN, 7, 0, 0),
733 GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "aclk266", GATE_IP_GEN, 9, 0, 0),
734
735 GATE(CLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0),
736 GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0),
737 GATE(CLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0),
738 GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "aclk400_mscl", GATE_IP_MSCL, 8, 0,
739 0),
740 GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "aclk400_mscl", GATE_IP_MSCL, 9, 0,
741 0),
742 GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "aclk400_mscl", GATE_IP_MSCL, 10, 0,
743 0),
744 GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1", GATE_IP_DISP1, 9, 0,
745 0),
746}; 1143};
747 1144
748static struct samsung_pll_clock exynos5420_plls[nr_plls] __initdata = { 1145static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = {
749 [apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK, 1146 [apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
750 APLL_CON0, NULL), 1147 APLL_CON0, NULL),
751 [cpll] = PLL(pll_2550, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK, 1148 [cpll] = PLL(pll_2550, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
@@ -776,8 +1173,11 @@ static struct of_device_id ext_clk_match[] __initdata = {
776}; 1173};
777 1174
778/* register exynos5420 clocks */ 1175/* register exynos5420 clocks */
779static void __init exynos5420_clk_init(struct device_node *np) 1176static void __init exynos5x_clk_init(struct device_node *np,
1177 enum exynos5x_soc soc)
780{ 1178{
1179 struct samsung_clk_provider *ctx;
1180
781 if (np) { 1181 if (np) {
782 reg_base = of_iomap(np, 0); 1182 reg_base = of_iomap(np, 0);
783 if (!reg_base) 1183 if (!reg_base)
@@ -786,23 +1186,56 @@ static void __init exynos5420_clk_init(struct device_node *np)
786 panic("%s: unable to determine soc\n", __func__); 1186 panic("%s: unable to determine soc\n", __func__);
787 } 1187 }
788 1188
789 samsung_clk_init(np, reg_base, CLK_NR_CLKS); 1189 exynos5x_soc = soc;
790 samsung_clk_of_register_fixed_ext(exynos5420_fixed_rate_ext_clks, 1190
791 ARRAY_SIZE(exynos5420_fixed_rate_ext_clks), 1191 ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
1192 if (!ctx)
1193 panic("%s: unable to allocate context.\n", __func__);
1194
1195 samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks,
1196 ARRAY_SIZE(exynos5x_fixed_rate_ext_clks),
792 ext_clk_match); 1197 ext_clk_match);
793 samsung_clk_register_pll(exynos5420_plls, ARRAY_SIZE(exynos5420_plls), 1198 samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls),
794 reg_base); 1199 reg_base);
795 samsung_clk_register_fixed_rate(exynos5420_fixed_rate_clks, 1200 samsung_clk_register_fixed_rate(ctx, exynos5x_fixed_rate_clks,
796 ARRAY_SIZE(exynos5420_fixed_rate_clks)); 1201 ARRAY_SIZE(exynos5x_fixed_rate_clks));
797 samsung_clk_register_fixed_factor(exynos5420_fixed_factor_clks, 1202 samsung_clk_register_fixed_factor(ctx, exynos5x_fixed_factor_clks,
798 ARRAY_SIZE(exynos5420_fixed_factor_clks)); 1203 ARRAY_SIZE(exynos5x_fixed_factor_clks));
799 samsung_clk_register_mux(exynos5420_mux_clks, 1204 samsung_clk_register_mux(ctx, exynos5x_mux_clks,
800 ARRAY_SIZE(exynos5420_mux_clks)); 1205 ARRAY_SIZE(exynos5x_mux_clks));
801 samsung_clk_register_div(exynos5420_div_clks, 1206 samsung_clk_register_div(ctx, exynos5x_div_clks,
802 ARRAY_SIZE(exynos5420_div_clks)); 1207 ARRAY_SIZE(exynos5x_div_clks));
803 samsung_clk_register_gate(exynos5420_gate_clks, 1208 samsung_clk_register_gate(ctx, exynos5x_gate_clks,
804 ARRAY_SIZE(exynos5420_gate_clks)); 1209 ARRAY_SIZE(exynos5x_gate_clks));
1210
1211 if (soc == EXYNOS5420) {
1212 samsung_clk_register_mux(ctx, exynos5420_mux_clks,
1213 ARRAY_SIZE(exynos5420_mux_clks));
1214 samsung_clk_register_div(ctx, exynos5420_div_clks,
1215 ARRAY_SIZE(exynos5420_div_clks));
1216 } else {
1217 samsung_clk_register_fixed_factor(
1218 ctx, exynos5800_fixed_factor_clks,
1219 ARRAY_SIZE(exynos5800_fixed_factor_clks));
1220 samsung_clk_register_mux(ctx, exynos5800_mux_clks,
1221 ARRAY_SIZE(exynos5800_mux_clks));
1222 samsung_clk_register_div(ctx, exynos5800_div_clks,
1223 ARRAY_SIZE(exynos5800_div_clks));
1224 samsung_clk_register_gate(ctx, exynos5800_gate_clks,
1225 ARRAY_SIZE(exynos5800_gate_clks));
1226 }
805 1227
806 exynos5420_clk_sleep_init(); 1228 exynos5420_clk_sleep_init();
807} 1229}
1230
1231static void __init exynos5420_clk_init(struct device_node *np)
1232{
1233 exynos5x_clk_init(np, EXYNOS5420);
1234}
808CLK_OF_DECLARE(exynos5420_clk, "samsung,exynos5420-clock", exynos5420_clk_init); 1235CLK_OF_DECLARE(exynos5420_clk, "samsung,exynos5420-clock", exynos5420_clk_init);
1236
1237static void __init exynos5800_clk_init(struct device_node *np)
1238{
1239 exynos5x_clk_init(np, EXYNOS5800);
1240}
1241CLK_OF_DECLARE(exynos5800_clk, "samsung,exynos5800-clock", exynos5800_clk_init);
diff --git a/drivers/clk/samsung/clk-exynos5440.c b/drivers/clk/samsung/clk-exynos5440.c
index 2bfad5a993d0..647f1440aa6a 100644
--- a/drivers/clk/samsung/clk-exynos5440.c
+++ b/drivers/clk/samsung/clk-exynos5440.c
@@ -93,6 +93,7 @@ static struct of_device_id ext_clk_match[] __initdata = {
93static void __init exynos5440_clk_init(struct device_node *np) 93static void __init exynos5440_clk_init(struct device_node *np)
94{ 94{
95 void __iomem *reg_base; 95 void __iomem *reg_base;
96 struct samsung_clk_provider *ctx;
96 97
97 reg_base = of_iomap(np, 0); 98 reg_base = of_iomap(np, 0);
98 if (!reg_base) { 99 if (!reg_base) {
@@ -101,22 +102,25 @@ static void __init exynos5440_clk_init(struct device_node *np)
101 return; 102 return;
102 } 103 }
103 104
104 samsung_clk_init(np, reg_base, CLK_NR_CLKS); 105 ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
105 samsung_clk_of_register_fixed_ext(exynos5440_fixed_rate_ext_clks, 106 if (!ctx)
107 panic("%s: unable to allocate context.\n", __func__);
108
109 samsung_clk_of_register_fixed_ext(ctx, exynos5440_fixed_rate_ext_clks,
106 ARRAY_SIZE(exynos5440_fixed_rate_ext_clks), ext_clk_match); 110 ARRAY_SIZE(exynos5440_fixed_rate_ext_clks), ext_clk_match);
107 111
108 samsung_clk_register_pll2550x("cplla", "xtal", reg_base + 0x1c, 0x10); 112 samsung_clk_register_pll2550x("cplla", "xtal", reg_base + 0x1c, 0x10);
109 samsung_clk_register_pll2550x("cpllb", "xtal", reg_base + 0x20, 0x10); 113 samsung_clk_register_pll2550x("cpllb", "xtal", reg_base + 0x20, 0x10);
110 114
111 samsung_clk_register_fixed_rate(exynos5440_fixed_rate_clks, 115 samsung_clk_register_fixed_rate(ctx, exynos5440_fixed_rate_clks,
112 ARRAY_SIZE(exynos5440_fixed_rate_clks)); 116 ARRAY_SIZE(exynos5440_fixed_rate_clks));
113 samsung_clk_register_fixed_factor(exynos5440_fixed_factor_clks, 117 samsung_clk_register_fixed_factor(ctx, exynos5440_fixed_factor_clks,
114 ARRAY_SIZE(exynos5440_fixed_factor_clks)); 118 ARRAY_SIZE(exynos5440_fixed_factor_clks));
115 samsung_clk_register_mux(exynos5440_mux_clks, 119 samsung_clk_register_mux(ctx, exynos5440_mux_clks,
116 ARRAY_SIZE(exynos5440_mux_clks)); 120 ARRAY_SIZE(exynos5440_mux_clks));
117 samsung_clk_register_div(exynos5440_div_clks, 121 samsung_clk_register_div(ctx, exynos5440_div_clks,
118 ARRAY_SIZE(exynos5440_div_clks)); 122 ARRAY_SIZE(exynos5440_div_clks));
119 samsung_clk_register_gate(exynos5440_gate_clks, 123 samsung_clk_register_gate(ctx, exynos5440_gate_clks,
120 ARRAY_SIZE(exynos5440_gate_clks)); 124 ARRAY_SIZE(exynos5440_gate_clks));
121 125
122 pr_info("Exynos5440: arm_clk = %ldHz\n", _get_rate("arm_clk")); 126 pr_info("Exynos5440: arm_clk = %ldHz\n", _get_rate("arm_clk"));
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 7fb0a28e65d5..b07fad2a9167 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -947,8 +947,206 @@ struct clk * __init samsung_clk_register_pll2550x(const char *name,
947 return clk; 947 return clk;
948} 948}
949 949
950static void __init _samsung_clk_register_pll(struct samsung_pll_clock *pll_clk, 950/*
951 void __iomem *base) 951 * PLL2550xx Clock Type
952 */
953
954/* Maximum lock time can be 270 * PDIV cycles */
955#define PLL2550XX_LOCK_FACTOR 270
956
957#define PLL2550XX_M_MASK 0x3FF
958#define PLL2550XX_P_MASK 0x3F
959#define PLL2550XX_S_MASK 0x7
960#define PLL2550XX_LOCK_STAT_MASK 0x1
961#define PLL2550XX_M_SHIFT 9
962#define PLL2550XX_P_SHIFT 3
963#define PLL2550XX_S_SHIFT 0
964#define PLL2550XX_LOCK_STAT_SHIFT 21
965
966static unsigned long samsung_pll2550xx_recalc_rate(struct clk_hw *hw,
967 unsigned long parent_rate)
968{
969 struct samsung_clk_pll *pll = to_clk_pll(hw);
970 u32 mdiv, pdiv, sdiv, pll_con;
971 u64 fvco = parent_rate;
972
973 pll_con = __raw_readl(pll->con_reg);
974 mdiv = (pll_con >> PLL2550XX_M_SHIFT) & PLL2550XX_M_MASK;
975 pdiv = (pll_con >> PLL2550XX_P_SHIFT) & PLL2550XX_P_MASK;
976 sdiv = (pll_con >> PLL2550XX_S_SHIFT) & PLL2550XX_S_MASK;
977
978 fvco *= mdiv;
979 do_div(fvco, (pdiv << sdiv));
980
981 return (unsigned long)fvco;
982}
983
984static inline bool samsung_pll2550xx_mp_change(u32 mdiv, u32 pdiv, u32 pll_con)
985{
986 u32 old_mdiv, old_pdiv;
987
988 old_mdiv = (pll_con >> PLL2550XX_M_SHIFT) & PLL2550XX_M_MASK;
989 old_pdiv = (pll_con >> PLL2550XX_P_SHIFT) & PLL2550XX_P_MASK;
990
991 return mdiv != old_mdiv || pdiv != old_pdiv;
992}
993
994static int samsung_pll2550xx_set_rate(struct clk_hw *hw, unsigned long drate,
995 unsigned long prate)
996{
997 struct samsung_clk_pll *pll = to_clk_pll(hw);
998 const struct samsung_pll_rate_table *rate;
999 u32 tmp;
1000
1001 /* Get required rate settings from table */
1002 rate = samsung_get_pll_settings(pll, drate);
1003 if (!rate) {
1004 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
1005 drate, __clk_get_name(hw->clk));
1006 return -EINVAL;
1007 }
1008
1009 tmp = __raw_readl(pll->con_reg);
1010
1011 if (!(samsung_pll2550xx_mp_change(rate->mdiv, rate->pdiv, tmp))) {
1012 /* If only s change, change just s value only*/
1013 tmp &= ~(PLL2550XX_S_MASK << PLL2550XX_S_SHIFT);
1014 tmp |= rate->sdiv << PLL2550XX_S_SHIFT;
1015 __raw_writel(tmp, pll->con_reg);
1016
1017 return 0;
1018 }
1019
1020 /* Set PLL lock time. */
1021 __raw_writel(rate->pdiv * PLL2550XX_LOCK_FACTOR, pll->lock_reg);
1022
1023 /* Change PLL PMS values */
1024 tmp &= ~((PLL2550XX_M_MASK << PLL2550XX_M_SHIFT) |
1025 (PLL2550XX_P_MASK << PLL2550XX_P_SHIFT) |
1026 (PLL2550XX_S_MASK << PLL2550XX_S_SHIFT));
1027 tmp |= (rate->mdiv << PLL2550XX_M_SHIFT) |
1028 (rate->pdiv << PLL2550XX_P_SHIFT) |
1029 (rate->sdiv << PLL2550XX_S_SHIFT);
1030 __raw_writel(tmp, pll->con_reg);
1031
1032 /* wait_lock_time */
1033 do {
1034 cpu_relax();
1035 tmp = __raw_readl(pll->con_reg);
1036 } while (!(tmp & (PLL2550XX_LOCK_STAT_MASK
1037 << PLL2550XX_LOCK_STAT_SHIFT)));
1038
1039 return 0;
1040}
1041
1042static const struct clk_ops samsung_pll2550xx_clk_ops = {
1043 .recalc_rate = samsung_pll2550xx_recalc_rate,
1044 .round_rate = samsung_pll_round_rate,
1045 .set_rate = samsung_pll2550xx_set_rate,
1046};
1047
1048static const struct clk_ops samsung_pll2550xx_clk_min_ops = {
1049 .recalc_rate = samsung_pll2550xx_recalc_rate,
1050};
1051
1052/*
1053 * PLL2650XX Clock Type
1054 */
1055
1056/* Maximum lock time can be 3000 * PDIV cycles */
1057#define PLL2650XX_LOCK_FACTOR 3000
1058
1059#define PLL2650XX_MDIV_SHIFT 9
1060#define PLL2650XX_PDIV_SHIFT 3
1061#define PLL2650XX_SDIV_SHIFT 0
1062#define PLL2650XX_KDIV_SHIFT 0
1063#define PLL2650XX_MDIV_MASK 0x1ff
1064#define PLL2650XX_PDIV_MASK 0x3f
1065#define PLL2650XX_SDIV_MASK 0x7
1066#define PLL2650XX_KDIV_MASK 0xffff
1067#define PLL2650XX_PLL_ENABLE_SHIFT 23
1068#define PLL2650XX_PLL_LOCKTIME_SHIFT 21
1069#define PLL2650XX_PLL_FOUTMASK_SHIFT 31
1070
1071static unsigned long samsung_pll2650xx_recalc_rate(struct clk_hw *hw,
1072 unsigned long parent_rate)
1073{
1074 struct samsung_clk_pll *pll = to_clk_pll(hw);
1075 u32 mdiv, pdiv, sdiv, pll_con0, pll_con2;
1076 s16 kdiv;
1077 u64 fvco = parent_rate;
1078
1079 pll_con0 = __raw_readl(pll->con_reg);
1080 pll_con2 = __raw_readl(pll->con_reg + 8);
1081 mdiv = (pll_con0 >> PLL2650XX_MDIV_SHIFT) & PLL2650XX_MDIV_MASK;
1082 pdiv = (pll_con0 >> PLL2650XX_PDIV_SHIFT) & PLL2650XX_PDIV_MASK;
1083 sdiv = (pll_con0 >> PLL2650XX_SDIV_SHIFT) & PLL2650XX_SDIV_MASK;
1084 kdiv = (s16)(pll_con2 & PLL2650XX_KDIV_MASK);
1085
1086 fvco *= (mdiv << 16) + kdiv;
1087 do_div(fvco, (pdiv << sdiv));
1088 fvco >>= 16;
1089
1090 return (unsigned long)fvco;
1091}
1092
1093static int samsung_pll2650xx_set_rate(struct clk_hw *hw, unsigned long drate,
1094 unsigned long parent_rate)
1095{
1096 struct samsung_clk_pll *pll = to_clk_pll(hw);
1097 u32 tmp, pll_con0, pll_con2;
1098 const struct samsung_pll_rate_table *rate;
1099
1100 rate = samsung_get_pll_settings(pll, drate);
1101 if (!rate) {
1102 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
1103 drate, __clk_get_name(hw->clk));
1104 return -EINVAL;
1105 }
1106
1107 pll_con0 = __raw_readl(pll->con_reg);
1108 pll_con2 = __raw_readl(pll->con_reg + 8);
1109
1110 /* Change PLL PMS values */
1111 pll_con0 &= ~(PLL2650XX_MDIV_MASK << PLL2650XX_MDIV_SHIFT |
1112 PLL2650XX_PDIV_MASK << PLL2650XX_PDIV_SHIFT |
1113 PLL2650XX_SDIV_MASK << PLL2650XX_SDIV_SHIFT);
1114 pll_con0 |= rate->mdiv << PLL2650XX_MDIV_SHIFT;
1115 pll_con0 |= rate->pdiv << PLL2650XX_PDIV_SHIFT;
1116 pll_con0 |= rate->sdiv << PLL2650XX_SDIV_SHIFT;
1117 pll_con0 |= 1 << PLL2650XX_PLL_ENABLE_SHIFT;
1118 pll_con0 |= 1 << PLL2650XX_PLL_FOUTMASK_SHIFT;
1119
1120 pll_con2 &= ~(PLL2650XX_KDIV_MASK << PLL2650XX_KDIV_SHIFT);
1121 pll_con2 |= ((~(rate->kdiv) + 1) & PLL2650XX_KDIV_MASK)
1122 << PLL2650XX_KDIV_SHIFT;
1123
1124 /* Set PLL lock time. */
1125 __raw_writel(PLL2650XX_LOCK_FACTOR * rate->pdiv, pll->lock_reg);
1126
1127 __raw_writel(pll_con0, pll->con_reg);
1128 __raw_writel(pll_con2, pll->con_reg + 8);
1129
1130 do {
1131 tmp = __raw_readl(pll->con_reg);
1132 } while (!(tmp & (0x1 << PLL2650XX_PLL_LOCKTIME_SHIFT)));
1133
1134 return 0;
1135}
1136
1137static const struct clk_ops samsung_pll2650xx_clk_ops = {
1138 .recalc_rate = samsung_pll2650xx_recalc_rate,
1139 .set_rate = samsung_pll2650xx_set_rate,
1140 .round_rate = samsung_pll_round_rate,
1141};
1142
1143static const struct clk_ops samsung_pll2650xx_clk_min_ops = {
1144 .recalc_rate = samsung_pll2650xx_recalc_rate,
1145};
1146
1147static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
1148 struct samsung_pll_clock *pll_clk,
1149 void __iomem *base)
952{ 1150{
953 struct samsung_clk_pll *pll; 1151 struct samsung_clk_pll *pll;
954 struct clk *clk; 1152 struct clk *clk;
@@ -1048,6 +1246,18 @@ static void __init _samsung_clk_register_pll(struct samsung_pll_clock *pll_clk,
1048 else 1246 else
1049 init.ops = &samsung_s3c2440_mpll_clk_ops; 1247 init.ops = &samsung_s3c2440_mpll_clk_ops;
1050 break; 1248 break;
1249 case pll_2550xx:
1250 if (!pll->rate_table)
1251 init.ops = &samsung_pll2550xx_clk_min_ops;
1252 else
1253 init.ops = &samsung_pll2550xx_clk_ops;
1254 break;
1255 case pll_2650xx:
1256 if (!pll->rate_table)
1257 init.ops = &samsung_pll2650xx_clk_min_ops;
1258 else
1259 init.ops = &samsung_pll2650xx_clk_ops;
1260 break;
1051 default: 1261 default:
1052 pr_warn("%s: Unknown pll type for pll clk %s\n", 1262 pr_warn("%s: Unknown pll type for pll clk %s\n",
1053 __func__, pll_clk->name); 1263 __func__, pll_clk->name);
@@ -1066,7 +1276,7 @@ static void __init _samsung_clk_register_pll(struct samsung_pll_clock *pll_clk,
1066 return; 1276 return;
1067 } 1277 }
1068 1278
1069 samsung_clk_add_lookup(clk, pll_clk->id); 1279 samsung_clk_add_lookup(ctx, clk, pll_clk->id);
1070 1280
1071 if (!pll_clk->alias) 1281 if (!pll_clk->alias)
1072 return; 1282 return;
@@ -1077,11 +1287,12 @@ static void __init _samsung_clk_register_pll(struct samsung_pll_clock *pll_clk,
1077 __func__, pll_clk->name, ret); 1287 __func__, pll_clk->name, ret);
1078} 1288}
1079 1289
1080void __init samsung_clk_register_pll(struct samsung_pll_clock *pll_list, 1290void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx,
1081 unsigned int nr_pll, void __iomem *base) 1291 struct samsung_pll_clock *pll_list,
1292 unsigned int nr_pll, void __iomem *base)
1082{ 1293{
1083 int cnt; 1294 int cnt;
1084 1295
1085 for (cnt = 0; cnt < nr_pll; cnt++) 1296 for (cnt = 0; cnt < nr_pll; cnt++)
1086 _samsung_clk_register_pll(&pll_list[cnt], base); 1297 _samsung_clk_register_pll(ctx, &pll_list[cnt], base);
1087} 1298}
diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
index 6428bcc6df6f..c0ed4d41fd90 100644
--- a/drivers/clk/samsung/clk-pll.h
+++ b/drivers/clk/samsung/clk-pll.h
@@ -31,6 +31,8 @@ enum samsung_pll_type {
31 pll_s3c2410_mpll, 31 pll_s3c2410_mpll,
32 pll_s3c2410_upll, 32 pll_s3c2410_upll,
33 pll_s3c2440_mpll, 33 pll_s3c2440_mpll,
34 pll_2550xx,
35 pll_2650xx,
34}; 36};
35 37
36#define PLL_35XX_RATE(_rate, _m, _p, _s) \ 38#define PLL_35XX_RATE(_rate, _m, _p, _s) \
diff --git a/drivers/clk/samsung/clk-s3c2410.c b/drivers/clk/samsung/clk-s3c2410.c
index 7b4182186a30..ba0716801db2 100644
--- a/drivers/clk/samsung/clk-s3c2410.c
+++ b/drivers/clk/samsung/clk-s3c2410.c
@@ -344,21 +344,24 @@ struct samsung_fixed_rate_clock s3c2410_common_frate_clks[] __initdata = {
344 FRATE(XTI, "xti", NULL, CLK_IS_ROOT, 0), 344 FRATE(XTI, "xti", NULL, CLK_IS_ROOT, 0),
345}; 345};
346 346
347static void __init s3c2410_common_clk_register_fixed_ext(unsigned long xti_f) 347static void __init s3c2410_common_clk_register_fixed_ext(
348 struct samsung_clk_provider *ctx,
349 unsigned long xti_f)
348{ 350{
349 struct samsung_clock_alias xti_alias = ALIAS(XTI, NULL, "xtal"); 351 struct samsung_clock_alias xti_alias = ALIAS(XTI, NULL, "xtal");
350 352
351 s3c2410_common_frate_clks[0].fixed_rate = xti_f; 353 s3c2410_common_frate_clks[0].fixed_rate = xti_f;
352 samsung_clk_register_fixed_rate(s3c2410_common_frate_clks, 354 samsung_clk_register_fixed_rate(ctx, s3c2410_common_frate_clks,
353 ARRAY_SIZE(s3c2410_common_frate_clks)); 355 ARRAY_SIZE(s3c2410_common_frate_clks));
354 356
355 samsung_clk_register_alias(&xti_alias, 1); 357 samsung_clk_register_alias(ctx, &xti_alias, 1);
356} 358}
357 359
358void __init s3c2410_common_clk_init(struct device_node *np, unsigned long xti_f, 360void __init s3c2410_common_clk_init(struct device_node *np, unsigned long xti_f,
359 int current_soc, 361 int current_soc,
360 void __iomem *base) 362 void __iomem *base)
361{ 363{
364 struct samsung_clk_provider *ctx;
362 reg_base = base; 365 reg_base = base;
363 366
364 if (np) { 367 if (np) {
@@ -367,11 +370,13 @@ void __init s3c2410_common_clk_init(struct device_node *np, unsigned long xti_f,
367 panic("%s: failed to map registers\n", __func__); 370 panic("%s: failed to map registers\n", __func__);
368 } 371 }
369 372
370 samsung_clk_init(np, reg_base, NR_CLKS); 373 ctx = samsung_clk_init(np, reg_base, NR_CLKS);
374 if (!ctx)
375 panic("%s: unable to allocate context.\n", __func__);
371 376
372 /* Register external clocks only in non-dt cases */ 377 /* Register external clocks only in non-dt cases */
373 if (!np) 378 if (!np)
374 s3c2410_common_clk_register_fixed_ext(xti_f); 379 s3c2410_common_clk_register_fixed_ext(ctx, xti_f);
375 380
376 if (current_soc == 2410) { 381 if (current_soc == 2410) {
377 if (_get_rate("xti") == 12 * MHZ) { 382 if (_get_rate("xti") == 12 * MHZ) {
@@ -380,7 +385,7 @@ void __init s3c2410_common_clk_init(struct device_node *np, unsigned long xti_f,
380 } 385 }
381 386
382 /* Register PLLs. */ 387 /* Register PLLs. */
383 samsung_clk_register_pll(s3c2410_plls, 388 samsung_clk_register_pll(ctx, s3c2410_plls,
384 ARRAY_SIZE(s3c2410_plls), reg_base); 389 ARRAY_SIZE(s3c2410_plls), reg_base);
385 390
386 } else { /* S3C2440, S3C2442 */ 391 } else { /* S3C2440, S3C2442 */
@@ -396,49 +401,49 @@ void __init s3c2410_common_clk_init(struct device_node *np, unsigned long xti_f,
396 } 401 }
397 402
398 /* Register PLLs. */ 403 /* Register PLLs. */
399 samsung_clk_register_pll(s3c244x_common_plls, 404 samsung_clk_register_pll(ctx, s3c244x_common_plls,
400 ARRAY_SIZE(s3c244x_common_plls), reg_base); 405 ARRAY_SIZE(s3c244x_common_plls), reg_base);
401 } 406 }
402 407
403 /* Register common internal clocks. */ 408 /* Register common internal clocks. */
404 samsung_clk_register_mux(s3c2410_common_muxes, 409 samsung_clk_register_mux(ctx, s3c2410_common_muxes,
405 ARRAY_SIZE(s3c2410_common_muxes)); 410 ARRAY_SIZE(s3c2410_common_muxes));
406 samsung_clk_register_div(s3c2410_common_dividers, 411 samsung_clk_register_div(ctx, s3c2410_common_dividers,
407 ARRAY_SIZE(s3c2410_common_dividers)); 412 ARRAY_SIZE(s3c2410_common_dividers));
408 samsung_clk_register_gate(s3c2410_common_gates, 413 samsung_clk_register_gate(ctx, s3c2410_common_gates,
409 ARRAY_SIZE(s3c2410_common_gates)); 414 ARRAY_SIZE(s3c2410_common_gates));
410 415
411 if (current_soc == S3C2440 || current_soc == S3C2442) { 416 if (current_soc == S3C2440 || current_soc == S3C2442) {
412 samsung_clk_register_div(s3c244x_common_dividers, 417 samsung_clk_register_div(ctx, s3c244x_common_dividers,
413 ARRAY_SIZE(s3c244x_common_dividers)); 418 ARRAY_SIZE(s3c244x_common_dividers));
414 samsung_clk_register_gate(s3c244x_common_gates, 419 samsung_clk_register_gate(ctx, s3c244x_common_gates,
415 ARRAY_SIZE(s3c244x_common_gates)); 420 ARRAY_SIZE(s3c244x_common_gates));
416 samsung_clk_register_mux(s3c244x_common_muxes, 421 samsung_clk_register_mux(ctx, s3c244x_common_muxes,
417 ARRAY_SIZE(s3c244x_common_muxes)); 422 ARRAY_SIZE(s3c244x_common_muxes));
418 samsung_clk_register_fixed_factor(s3c244x_common_ffactor, 423 samsung_clk_register_fixed_factor(ctx, s3c244x_common_ffactor,
419 ARRAY_SIZE(s3c244x_common_ffactor)); 424 ARRAY_SIZE(s3c244x_common_ffactor));
420 } 425 }
421 426
422 /* Register SoC-specific clocks. */ 427 /* Register SoC-specific clocks. */
423 switch (current_soc) { 428 switch (current_soc) {
424 case S3C2410: 429 case S3C2410:
425 samsung_clk_register_div(s3c2410_dividers, 430 samsung_clk_register_div(ctx, s3c2410_dividers,
426 ARRAY_SIZE(s3c2410_dividers)); 431 ARRAY_SIZE(s3c2410_dividers));
427 samsung_clk_register_fixed_factor(s3c2410_ffactor, 432 samsung_clk_register_fixed_factor(ctx, s3c2410_ffactor,
428 ARRAY_SIZE(s3c2410_ffactor)); 433 ARRAY_SIZE(s3c2410_ffactor));
429 samsung_clk_register_alias(s3c2410_aliases, 434 samsung_clk_register_alias(ctx, s3c2410_aliases,
430 ARRAY_SIZE(s3c2410_common_aliases)); 435 ARRAY_SIZE(s3c2410_common_aliases));
431 break; 436 break;
432 case S3C2440: 437 case S3C2440:
433 samsung_clk_register_mux(s3c2440_muxes, 438 samsung_clk_register_mux(ctx, s3c2440_muxes,
434 ARRAY_SIZE(s3c2440_muxes)); 439 ARRAY_SIZE(s3c2440_muxes));
435 samsung_clk_register_gate(s3c2440_gates, 440 samsung_clk_register_gate(ctx, s3c2440_gates,
436 ARRAY_SIZE(s3c2440_gates)); 441 ARRAY_SIZE(s3c2440_gates));
437 break; 442 break;
438 case S3C2442: 443 case S3C2442:
439 samsung_clk_register_mux(s3c2442_muxes, 444 samsung_clk_register_mux(ctx, s3c2442_muxes,
440 ARRAY_SIZE(s3c2442_muxes)); 445 ARRAY_SIZE(s3c2442_muxes));
441 samsung_clk_register_fixed_factor(s3c2442_ffactor, 446 samsung_clk_register_fixed_factor(ctx, s3c2442_ffactor,
442 ARRAY_SIZE(s3c2442_ffactor)); 447 ARRAY_SIZE(s3c2442_ffactor));
443 break; 448 break;
444 } 449 }
@@ -447,11 +452,11 @@ void __init s3c2410_common_clk_init(struct device_node *np, unsigned long xti_f,
447 * Register common aliases at the end, as some of the aliased clocks 452 * Register common aliases at the end, as some of the aliased clocks
448 * are SoC specific. 453 * are SoC specific.
449 */ 454 */
450 samsung_clk_register_alias(s3c2410_common_aliases, 455 samsung_clk_register_alias(ctx, s3c2410_common_aliases,
451 ARRAY_SIZE(s3c2410_common_aliases)); 456 ARRAY_SIZE(s3c2410_common_aliases));
452 457
453 if (current_soc == S3C2440 || current_soc == S3C2442) { 458 if (current_soc == S3C2440 || current_soc == S3C2442) {
454 samsung_clk_register_alias(s3c244x_common_aliases, 459 samsung_clk_register_alias(ctx, s3c244x_common_aliases,
455 ARRAY_SIZE(s3c244x_common_aliases)); 460 ARRAY_SIZE(s3c244x_common_aliases));
456 } 461 }
457 462
diff --git a/drivers/clk/samsung/clk-s3c2412.c b/drivers/clk/samsung/clk-s3c2412.c
index 0f11a07d5c01..23e4313f625e 100644
--- a/drivers/clk/samsung/clk-s3c2412.c
+++ b/drivers/clk/samsung/clk-s3c2412.c
@@ -214,23 +214,25 @@ struct samsung_fixed_rate_clock s3c2412_common_frate_clks[] __initdata = {
214 FRATE(0, "ext", NULL, CLK_IS_ROOT, 0), 214 FRATE(0, "ext", NULL, CLK_IS_ROOT, 0),
215}; 215};
216 216
217static void __init s3c2412_common_clk_register_fixed_ext(unsigned long xti_f, 217static void __init s3c2412_common_clk_register_fixed_ext(
218 unsigned long ext_f) 218 struct samsung_clk_provider *ctx,
219 unsigned long xti_f, unsigned long ext_f)
219{ 220{
220 /* xtal alias is necessary for the current cpufreq driver */ 221 /* xtal alias is necessary for the current cpufreq driver */
221 struct samsung_clock_alias xti_alias = ALIAS(XTI, NULL, "xtal"); 222 struct samsung_clock_alias xti_alias = ALIAS(XTI, NULL, "xtal");
222 223
223 s3c2412_common_frate_clks[0].fixed_rate = xti_f; 224 s3c2412_common_frate_clks[0].fixed_rate = xti_f;
224 s3c2412_common_frate_clks[1].fixed_rate = ext_f; 225 s3c2412_common_frate_clks[1].fixed_rate = ext_f;
225 samsung_clk_register_fixed_rate(s3c2412_common_frate_clks, 226 samsung_clk_register_fixed_rate(ctx, s3c2412_common_frate_clks,
226 ARRAY_SIZE(s3c2412_common_frate_clks)); 227 ARRAY_SIZE(s3c2412_common_frate_clks));
227 228
228 samsung_clk_register_alias(&xti_alias, 1); 229 samsung_clk_register_alias(ctx, &xti_alias, 1);
229} 230}
230 231
231void __init s3c2412_common_clk_init(struct device_node *np, unsigned long xti_f, 232void __init s3c2412_common_clk_init(struct device_node *np, unsigned long xti_f,
232 unsigned long ext_f, void __iomem *base) 233 unsigned long ext_f, void __iomem *base)
233{ 234{
235 struct samsung_clk_provider *ctx;
234 reg_base = base; 236 reg_base = base;
235 237
236 if (np) { 238 if (np) {
@@ -239,24 +241,27 @@ void __init s3c2412_common_clk_init(struct device_node *np, unsigned long xti_f,
239 panic("%s: failed to map registers\n", __func__); 241 panic("%s: failed to map registers\n", __func__);
240 } 242 }
241 243
242 samsung_clk_init(np, reg_base, NR_CLKS); 244 ctx = samsung_clk_init(np, reg_base, NR_CLKS);
245 if (!ctx)
246 panic("%s: unable to allocate context.\n", __func__);
243 247
244 /* Register external clocks only in non-dt cases */ 248 /* Register external clocks only in non-dt cases */
245 if (!np) 249 if (!np)
246 s3c2412_common_clk_register_fixed_ext(xti_f, ext_f); 250 s3c2412_common_clk_register_fixed_ext(ctx, xti_f, ext_f);
247 251
248 /* Register PLLs. */ 252 /* Register PLLs. */
249 samsung_clk_register_pll(s3c2412_plls, ARRAY_SIZE(s3c2412_plls), 253 samsung_clk_register_pll(ctx, s3c2412_plls, ARRAY_SIZE(s3c2412_plls),
250 reg_base); 254 reg_base);
251 255
252 /* Register common internal clocks. */ 256 /* Register common internal clocks. */
253 samsung_clk_register_mux(s3c2412_muxes, ARRAY_SIZE(s3c2412_muxes)); 257 samsung_clk_register_mux(ctx, s3c2412_muxes, ARRAY_SIZE(s3c2412_muxes));
254 samsung_clk_register_div(s3c2412_dividers, 258 samsung_clk_register_div(ctx, s3c2412_dividers,
255 ARRAY_SIZE(s3c2412_dividers)); 259 ARRAY_SIZE(s3c2412_dividers));
256 samsung_clk_register_gate(s3c2412_gates, ARRAY_SIZE(s3c2412_gates)); 260 samsung_clk_register_gate(ctx, s3c2412_gates,
257 samsung_clk_register_fixed_factor(s3c2412_ffactor, 261 ARRAY_SIZE(s3c2412_gates));
262 samsung_clk_register_fixed_factor(ctx, s3c2412_ffactor,
258 ARRAY_SIZE(s3c2412_ffactor)); 263 ARRAY_SIZE(s3c2412_ffactor));
259 samsung_clk_register_alias(s3c2412_aliases, 264 samsung_clk_register_alias(ctx, s3c2412_aliases,
260 ARRAY_SIZE(s3c2412_aliases)); 265 ARRAY_SIZE(s3c2412_aliases));
261 266
262 s3c2412_clk_sleep_init(); 267 s3c2412_clk_sleep_init();
diff --git a/drivers/clk/samsung/clk-s3c2443.c b/drivers/clk/samsung/clk-s3c2443.c
index 8e4f4517e95c..c4bbdabebaa4 100644
--- a/drivers/clk/samsung/clk-s3c2443.c
+++ b/drivers/clk/samsung/clk-s3c2443.c
@@ -365,10 +365,11 @@ struct samsung_fixed_rate_clock s3c2443_common_frate_clks[] __initdata = {
365 FRATE(0, "ext_uart", NULL, CLK_IS_ROOT, 0), 365 FRATE(0, "ext_uart", NULL, CLK_IS_ROOT, 0),
366}; 366};
367 367
368static void __init s3c2443_common_clk_register_fixed_ext(unsigned long xti_f) 368static void __init s3c2443_common_clk_register_fixed_ext(
369 struct samsung_clk_provider *ctx, unsigned long xti_f)
369{ 370{
370 s3c2443_common_frate_clks[0].fixed_rate = xti_f; 371 s3c2443_common_frate_clks[0].fixed_rate = xti_f;
371 samsung_clk_register_fixed_rate(s3c2443_common_frate_clks, 372 samsung_clk_register_fixed_rate(ctx, s3c2443_common_frate_clks,
372 ARRAY_SIZE(s3c2443_common_frate_clks)); 373 ARRAY_SIZE(s3c2443_common_frate_clks));
373} 374}
374 375
@@ -376,6 +377,7 @@ void __init s3c2443_common_clk_init(struct device_node *np, unsigned long xti_f,
376 int current_soc, 377 int current_soc,
377 void __iomem *base) 378 void __iomem *base)
378{ 379{
380 struct samsung_clk_provider *ctx;
379 reg_base = base; 381 reg_base = base;
380 382
381 if (np) { 383 if (np) {
@@ -384,58 +386,60 @@ void __init s3c2443_common_clk_init(struct device_node *np, unsigned long xti_f,
384 panic("%s: failed to map registers\n", __func__); 386 panic("%s: failed to map registers\n", __func__);
385 } 387 }
386 388
387 samsung_clk_init(np, reg_base, NR_CLKS); 389 ctx = samsung_clk_init(np, reg_base, NR_CLKS);
390 if (!ctx)
391 panic("%s: unable to allocate context.\n", __func__);
388 392
389 /* Register external clocks only in non-dt cases */ 393 /* Register external clocks only in non-dt cases */
390 if (!np) 394 if (!np)
391 s3c2443_common_clk_register_fixed_ext(xti_f); 395 s3c2443_common_clk_register_fixed_ext(ctx, xti_f);
392 396
393 /* Register PLLs. */ 397 /* Register PLLs. */
394 if (current_soc == S3C2416 || current_soc == S3C2450) 398 if (current_soc == S3C2416 || current_soc == S3C2450)
395 samsung_clk_register_pll(s3c2416_pll_clks, 399 samsung_clk_register_pll(ctx, s3c2416_pll_clks,
396 ARRAY_SIZE(s3c2416_pll_clks), reg_base); 400 ARRAY_SIZE(s3c2416_pll_clks), reg_base);
397 else 401 else
398 samsung_clk_register_pll(s3c2443_pll_clks, 402 samsung_clk_register_pll(ctx, s3c2443_pll_clks,
399 ARRAY_SIZE(s3c2443_pll_clks), reg_base); 403 ARRAY_SIZE(s3c2443_pll_clks), reg_base);
400 404
401 /* Register common internal clocks. */ 405 /* Register common internal clocks. */
402 samsung_clk_register_mux(s3c2443_common_muxes, 406 samsung_clk_register_mux(ctx, s3c2443_common_muxes,
403 ARRAY_SIZE(s3c2443_common_muxes)); 407 ARRAY_SIZE(s3c2443_common_muxes));
404 samsung_clk_register_div(s3c2443_common_dividers, 408 samsung_clk_register_div(ctx, s3c2443_common_dividers,
405 ARRAY_SIZE(s3c2443_common_dividers)); 409 ARRAY_SIZE(s3c2443_common_dividers));
406 samsung_clk_register_gate(s3c2443_common_gates, 410 samsung_clk_register_gate(ctx, s3c2443_common_gates,
407 ARRAY_SIZE(s3c2443_common_gates)); 411 ARRAY_SIZE(s3c2443_common_gates));
408 samsung_clk_register_alias(s3c2443_common_aliases, 412 samsung_clk_register_alias(ctx, s3c2443_common_aliases,
409 ARRAY_SIZE(s3c2443_common_aliases)); 413 ARRAY_SIZE(s3c2443_common_aliases));
410 414
411 /* Register SoC-specific clocks. */ 415 /* Register SoC-specific clocks. */
412 switch (current_soc) { 416 switch (current_soc) {
413 case S3C2450: 417 case S3C2450:
414 samsung_clk_register_div(s3c2450_dividers, 418 samsung_clk_register_div(ctx, s3c2450_dividers,
415 ARRAY_SIZE(s3c2450_dividers)); 419 ARRAY_SIZE(s3c2450_dividers));
416 samsung_clk_register_mux(s3c2450_muxes, 420 samsung_clk_register_mux(ctx, s3c2450_muxes,
417 ARRAY_SIZE(s3c2450_muxes)); 421 ARRAY_SIZE(s3c2450_muxes));
418 samsung_clk_register_gate(s3c2450_gates, 422 samsung_clk_register_gate(ctx, s3c2450_gates,
419 ARRAY_SIZE(s3c2450_gates)); 423 ARRAY_SIZE(s3c2450_gates));
420 samsung_clk_register_alias(s3c2450_aliases, 424 samsung_clk_register_alias(ctx, s3c2450_aliases,
421 ARRAY_SIZE(s3c2450_aliases)); 425 ARRAY_SIZE(s3c2450_aliases));
422 /* fall through, as s3c2450 extends the s3c2416 clocks */ 426 /* fall through, as s3c2450 extends the s3c2416 clocks */
423 case S3C2416: 427 case S3C2416:
424 samsung_clk_register_div(s3c2416_dividers, 428 samsung_clk_register_div(ctx, s3c2416_dividers,
425 ARRAY_SIZE(s3c2416_dividers)); 429 ARRAY_SIZE(s3c2416_dividers));
426 samsung_clk_register_mux(s3c2416_muxes, 430 samsung_clk_register_mux(ctx, s3c2416_muxes,
427 ARRAY_SIZE(s3c2416_muxes)); 431 ARRAY_SIZE(s3c2416_muxes));
428 samsung_clk_register_gate(s3c2416_gates, 432 samsung_clk_register_gate(ctx, s3c2416_gates,
429 ARRAY_SIZE(s3c2416_gates)); 433 ARRAY_SIZE(s3c2416_gates));
430 samsung_clk_register_alias(s3c2416_aliases, 434 samsung_clk_register_alias(ctx, s3c2416_aliases,
431 ARRAY_SIZE(s3c2416_aliases)); 435 ARRAY_SIZE(s3c2416_aliases));
432 break; 436 break;
433 case S3C2443: 437 case S3C2443:
434 samsung_clk_register_div(s3c2443_dividers, 438 samsung_clk_register_div(ctx, s3c2443_dividers,
435 ARRAY_SIZE(s3c2443_dividers)); 439 ARRAY_SIZE(s3c2443_dividers));
436 samsung_clk_register_gate(s3c2443_gates, 440 samsung_clk_register_gate(ctx, s3c2443_gates,
437 ARRAY_SIZE(s3c2443_gates)); 441 ARRAY_SIZE(s3c2443_gates));
438 samsung_clk_register_alias(s3c2443_aliases, 442 samsung_clk_register_alias(ctx, s3c2443_aliases,
439 ARRAY_SIZE(s3c2443_aliases)); 443 ARRAY_SIZE(s3c2443_aliases));
440 break; 444 break;
441 } 445 }
diff --git a/drivers/clk/samsung/clk-s3c64xx.c b/drivers/clk/samsung/clk-s3c64xx.c
index 8bda658137a8..efa16ee592c8 100644
--- a/drivers/clk/samsung/clk-s3c64xx.c
+++ b/drivers/clk/samsung/clk-s3c64xx.c
@@ -442,12 +442,14 @@ static struct samsung_clock_alias s3c6410_clock_aliases[] = {
442 ALIAS(MEM0_SROM, NULL, "srom"), 442 ALIAS(MEM0_SROM, NULL, "srom"),
443}; 443};
444 444
445static void __init s3c64xx_clk_register_fixed_ext(unsigned long fin_pll_f, 445static void __init s3c64xx_clk_register_fixed_ext(
446 unsigned long xusbxti_f) 446 struct samsung_clk_provider *ctx,
447 unsigned long fin_pll_f,
448 unsigned long xusbxti_f)
447{ 449{
448 s3c64xx_fixed_rate_ext_clks[0].fixed_rate = fin_pll_f; 450 s3c64xx_fixed_rate_ext_clks[0].fixed_rate = fin_pll_f;
449 s3c64xx_fixed_rate_ext_clks[1].fixed_rate = xusbxti_f; 451 s3c64xx_fixed_rate_ext_clks[1].fixed_rate = xusbxti_f;
450 samsung_clk_register_fixed_rate(s3c64xx_fixed_rate_ext_clks, 452 samsung_clk_register_fixed_rate(ctx, s3c64xx_fixed_rate_ext_clks,
451 ARRAY_SIZE(s3c64xx_fixed_rate_ext_clks)); 453 ARRAY_SIZE(s3c64xx_fixed_rate_ext_clks));
452} 454}
453 455
@@ -456,6 +458,8 @@ void __init s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f,
456 unsigned long xusbxti_f, bool s3c6400, 458 unsigned long xusbxti_f, bool s3c6400,
457 void __iomem *base) 459 void __iomem *base)
458{ 460{
461 struct samsung_clk_provider *ctx;
462
459 reg_base = base; 463 reg_base = base;
460 is_s3c6400 = s3c6400; 464 is_s3c6400 = s3c6400;
461 465
@@ -465,48 +469,50 @@ void __init s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f,
465 panic("%s: failed to map registers\n", __func__); 469 panic("%s: failed to map registers\n", __func__);
466 } 470 }
467 471
468 samsung_clk_init(np, reg_base, NR_CLKS); 472 ctx = samsung_clk_init(np, reg_base, NR_CLKS);
473 if (!ctx)
474 panic("%s: unable to allocate context.\n", __func__);
469 475
470 /* Register external clocks. */ 476 /* Register external clocks. */
471 if (!np) 477 if (!np)
472 s3c64xx_clk_register_fixed_ext(xtal_f, xusbxti_f); 478 s3c64xx_clk_register_fixed_ext(ctx, xtal_f, xusbxti_f);
473 479
474 /* Register PLLs. */ 480 /* Register PLLs. */
475 samsung_clk_register_pll(s3c64xx_pll_clks, 481 samsung_clk_register_pll(ctx, s3c64xx_pll_clks,
476 ARRAY_SIZE(s3c64xx_pll_clks), reg_base); 482 ARRAY_SIZE(s3c64xx_pll_clks), reg_base);
477 483
478 /* Register common internal clocks. */ 484 /* Register common internal clocks. */
479 samsung_clk_register_fixed_rate(s3c64xx_fixed_rate_clks, 485 samsung_clk_register_fixed_rate(ctx, s3c64xx_fixed_rate_clks,
480 ARRAY_SIZE(s3c64xx_fixed_rate_clks)); 486 ARRAY_SIZE(s3c64xx_fixed_rate_clks));
481 samsung_clk_register_mux(s3c64xx_mux_clks, 487 samsung_clk_register_mux(ctx, s3c64xx_mux_clks,
482 ARRAY_SIZE(s3c64xx_mux_clks)); 488 ARRAY_SIZE(s3c64xx_mux_clks));
483 samsung_clk_register_div(s3c64xx_div_clks, 489 samsung_clk_register_div(ctx, s3c64xx_div_clks,
484 ARRAY_SIZE(s3c64xx_div_clks)); 490 ARRAY_SIZE(s3c64xx_div_clks));
485 samsung_clk_register_gate(s3c64xx_gate_clks, 491 samsung_clk_register_gate(ctx, s3c64xx_gate_clks,
486 ARRAY_SIZE(s3c64xx_gate_clks)); 492 ARRAY_SIZE(s3c64xx_gate_clks));
487 493
488 /* Register SoC-specific clocks. */ 494 /* Register SoC-specific clocks. */
489 if (is_s3c6400) { 495 if (is_s3c6400) {
490 samsung_clk_register_mux(s3c6400_mux_clks, 496 samsung_clk_register_mux(ctx, s3c6400_mux_clks,
491 ARRAY_SIZE(s3c6400_mux_clks)); 497 ARRAY_SIZE(s3c6400_mux_clks));
492 samsung_clk_register_div(s3c6400_div_clks, 498 samsung_clk_register_div(ctx, s3c6400_div_clks,
493 ARRAY_SIZE(s3c6400_div_clks)); 499 ARRAY_SIZE(s3c6400_div_clks));
494 samsung_clk_register_gate(s3c6400_gate_clks, 500 samsung_clk_register_gate(ctx, s3c6400_gate_clks,
495 ARRAY_SIZE(s3c6400_gate_clks)); 501 ARRAY_SIZE(s3c6400_gate_clks));
496 samsung_clk_register_alias(s3c6400_clock_aliases, 502 samsung_clk_register_alias(ctx, s3c6400_clock_aliases,
497 ARRAY_SIZE(s3c6400_clock_aliases)); 503 ARRAY_SIZE(s3c6400_clock_aliases));
498 } else { 504 } else {
499 samsung_clk_register_mux(s3c6410_mux_clks, 505 samsung_clk_register_mux(ctx, s3c6410_mux_clks,
500 ARRAY_SIZE(s3c6410_mux_clks)); 506 ARRAY_SIZE(s3c6410_mux_clks));
501 samsung_clk_register_div(s3c6410_div_clks, 507 samsung_clk_register_div(ctx, s3c6410_div_clks,
502 ARRAY_SIZE(s3c6410_div_clks)); 508 ARRAY_SIZE(s3c6410_div_clks));
503 samsung_clk_register_gate(s3c6410_gate_clks, 509 samsung_clk_register_gate(ctx, s3c6410_gate_clks,
504 ARRAY_SIZE(s3c6410_gate_clks)); 510 ARRAY_SIZE(s3c6410_gate_clks));
505 samsung_clk_register_alias(s3c6410_clock_aliases, 511 samsung_clk_register_alias(ctx, s3c6410_clock_aliases,
506 ARRAY_SIZE(s3c6410_clock_aliases)); 512 ARRAY_SIZE(s3c6410_clock_aliases));
507 } 513 }
508 514
509 samsung_clk_register_alias(s3c64xx_clock_aliases, 515 samsung_clk_register_alias(ctx, s3c64xx_clock_aliases,
510 ARRAY_SIZE(s3c64xx_clock_aliases)); 516 ARRAY_SIZE(s3c64xx_clock_aliases));
511 s3c64xx_clk_sleep_init(); 517 s3c64xx_clk_sleep_init();
512 518
diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c
index 91bec3ebdc8f..49629c71c9e7 100644
--- a/drivers/clk/samsung/clk.c
+++ b/drivers/clk/samsung/clk.c
@@ -14,13 +14,6 @@
14#include <linux/syscore_ops.h> 14#include <linux/syscore_ops.h>
15#include "clk.h" 15#include "clk.h"
16 16
17static DEFINE_SPINLOCK(lock);
18static struct clk **clk_table;
19static void __iomem *reg_base;
20#ifdef CONFIG_OF
21static struct clk_onecell_data clk_data;
22#endif
23
24void samsung_clk_save(void __iomem *base, 17void samsung_clk_save(void __iomem *base,
25 struct samsung_clk_reg_dump *rd, 18 struct samsung_clk_reg_dump *rd,
26 unsigned int num_regs) 19 unsigned int num_regs)
@@ -55,40 +48,58 @@ struct samsung_clk_reg_dump *samsung_clk_alloc_reg_dump(
55} 48}
56 49
57/* setup the essentials required to support clock lookup using ccf */ 50/* setup the essentials required to support clock lookup using ccf */
58void __init samsung_clk_init(struct device_node *np, void __iomem *base, 51struct samsung_clk_provider *__init samsung_clk_init(struct device_node *np,
59 unsigned long nr_clks) 52 void __iomem *base, unsigned long nr_clks)
60{ 53{
61 reg_base = base; 54 struct samsung_clk_provider *ctx;
55 struct clk **clk_table;
56 int ret;
57 int i;
62 58
63 clk_table = kzalloc(sizeof(struct clk *) * nr_clks, GFP_KERNEL); 59 ctx = kzalloc(sizeof(struct samsung_clk_provider), GFP_KERNEL);
60 if (!ctx)
61 panic("could not allocate clock provider context.\n");
62
63 clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL);
64 if (!clk_table) 64 if (!clk_table)
65 panic("could not allocate clock lookup table\n"); 65 panic("could not allocate clock lookup table\n");
66 66
67 for (i = 0; i < nr_clks; ++i)
68 clk_table[i] = ERR_PTR(-ENOENT);
69
70 ctx->reg_base = base;
71 ctx->clk_data.clks = clk_table;
72 ctx->clk_data.clk_num = nr_clks;
73 spin_lock_init(&ctx->lock);
74
67 if (!np) 75 if (!np)
68 return; 76 return ctx;
69 77
70#ifdef CONFIG_OF 78 ret = of_clk_add_provider(np, of_clk_src_onecell_get,
71 clk_data.clks = clk_table; 79 &ctx->clk_data);
72 clk_data.clk_num = nr_clks; 80 if (ret)
73 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); 81 panic("could not register clock provide\n");
74#endif 82
83 return ctx;
75} 84}
76 85
77/* add a clock instance to the clock lookup table used for dt based lookup */ 86/* add a clock instance to the clock lookup table used for dt based lookup */
78void samsung_clk_add_lookup(struct clk *clk, unsigned int id) 87void samsung_clk_add_lookup(struct samsung_clk_provider *ctx, struct clk *clk,
88 unsigned int id)
79{ 89{
80 if (clk_table && id) 90 if (ctx->clk_data.clks && id)
81 clk_table[id] = clk; 91 ctx->clk_data.clks[id] = clk;
82} 92}
83 93
84/* register a list of aliases */ 94/* register a list of aliases */
85void __init samsung_clk_register_alias(struct samsung_clock_alias *list, 95void __init samsung_clk_register_alias(struct samsung_clk_provider *ctx,
86 unsigned int nr_clk) 96 struct samsung_clock_alias *list,
97 unsigned int nr_clk)
87{ 98{
88 struct clk *clk; 99 struct clk *clk;
89 unsigned int idx, ret; 100 unsigned int idx, ret;
90 101
91 if (!clk_table) { 102 if (!ctx->clk_data.clks) {
92 pr_err("%s: clock table missing\n", __func__); 103 pr_err("%s: clock table missing\n", __func__);
93 return; 104 return;
94 } 105 }
@@ -100,7 +111,7 @@ void __init samsung_clk_register_alias(struct samsung_clock_alias *list,
100 continue; 111 continue;
101 } 112 }
102 113
103 clk = clk_table[list->id]; 114 clk = ctx->clk_data.clks[list->id];
104 if (!clk) { 115 if (!clk) {
105 pr_err("%s: failed to find clock %d\n", __func__, 116 pr_err("%s: failed to find clock %d\n", __func__,
106 list->id); 117 list->id);
@@ -115,7 +126,7 @@ void __init samsung_clk_register_alias(struct samsung_clock_alias *list,
115} 126}
116 127
117/* register a list of fixed clocks */ 128/* register a list of fixed clocks */
118void __init samsung_clk_register_fixed_rate( 129void __init samsung_clk_register_fixed_rate(struct samsung_clk_provider *ctx,
119 struct samsung_fixed_rate_clock *list, unsigned int nr_clk) 130 struct samsung_fixed_rate_clock *list, unsigned int nr_clk)
120{ 131{
121 struct clk *clk; 132 struct clk *clk;
@@ -130,7 +141,7 @@ void __init samsung_clk_register_fixed_rate(
130 continue; 141 continue;
131 } 142 }
132 143
133 samsung_clk_add_lookup(clk, list->id); 144 samsung_clk_add_lookup(ctx, clk, list->id);
134 145
135 /* 146 /*
136 * Unconditionally add a clock lookup for the fixed rate clocks. 147 * Unconditionally add a clock lookup for the fixed rate clocks.
@@ -144,7 +155,7 @@ void __init samsung_clk_register_fixed_rate(
144} 155}
145 156
146/* register a list of fixed factor clocks */ 157/* register a list of fixed factor clocks */
147void __init samsung_clk_register_fixed_factor( 158void __init samsung_clk_register_fixed_factor(struct samsung_clk_provider *ctx,
148 struct samsung_fixed_factor_clock *list, unsigned int nr_clk) 159 struct samsung_fixed_factor_clock *list, unsigned int nr_clk)
149{ 160{
150 struct clk *clk; 161 struct clk *clk;
@@ -159,28 +170,30 @@ void __init samsung_clk_register_fixed_factor(
159 continue; 170 continue;
160 } 171 }
161 172
162 samsung_clk_add_lookup(clk, list->id); 173 samsung_clk_add_lookup(ctx, clk, list->id);
163 } 174 }
164} 175}
165 176
166/* register a list of mux clocks */ 177/* register a list of mux clocks */
167void __init samsung_clk_register_mux(struct samsung_mux_clock *list, 178void __init samsung_clk_register_mux(struct samsung_clk_provider *ctx,
168 unsigned int nr_clk) 179 struct samsung_mux_clock *list,
180 unsigned int nr_clk)
169{ 181{
170 struct clk *clk; 182 struct clk *clk;
171 unsigned int idx, ret; 183 unsigned int idx, ret;
172 184
173 for (idx = 0; idx < nr_clk; idx++, list++) { 185 for (idx = 0; idx < nr_clk; idx++, list++) {
174 clk = clk_register_mux(NULL, list->name, list->parent_names, 186 clk = clk_register_mux(NULL, list->name, list->parent_names,
175 list->num_parents, list->flags, reg_base + list->offset, 187 list->num_parents, list->flags,
176 list->shift, list->width, list->mux_flags, &lock); 188 ctx->reg_base + list->offset,
189 list->shift, list->width, list->mux_flags, &ctx->lock);
177 if (IS_ERR(clk)) { 190 if (IS_ERR(clk)) {
178 pr_err("%s: failed to register clock %s\n", __func__, 191 pr_err("%s: failed to register clock %s\n", __func__,
179 list->name); 192 list->name);
180 continue; 193 continue;
181 } 194 }
182 195
183 samsung_clk_add_lookup(clk, list->id); 196 samsung_clk_add_lookup(ctx, clk, list->id);
184 197
185 /* register a clock lookup only if a clock alias is specified */ 198 /* register a clock lookup only if a clock alias is specified */
186 if (list->alias) { 199 if (list->alias) {
@@ -194,8 +207,9 @@ void __init samsung_clk_register_mux(struct samsung_mux_clock *list,
194} 207}
195 208
196/* register a list of div clocks */ 209/* register a list of div clocks */
197void __init samsung_clk_register_div(struct samsung_div_clock *list, 210void __init samsung_clk_register_div(struct samsung_clk_provider *ctx,
198 unsigned int nr_clk) 211 struct samsung_div_clock *list,
212 unsigned int nr_clk)
199{ 213{
200 struct clk *clk; 214 struct clk *clk;
201 unsigned int idx, ret; 215 unsigned int idx, ret;
@@ -203,22 +217,22 @@ void __init samsung_clk_register_div(struct samsung_div_clock *list,
203 for (idx = 0; idx < nr_clk; idx++, list++) { 217 for (idx = 0; idx < nr_clk; idx++, list++) {
204 if (list->table) 218 if (list->table)
205 clk = clk_register_divider_table(NULL, list->name, 219 clk = clk_register_divider_table(NULL, list->name,
206 list->parent_name, list->flags, 220 list->parent_name, list->flags,
207 reg_base + list->offset, list->shift, 221 ctx->reg_base + list->offset,
208 list->width, list->div_flags, 222 list->shift, list->width, list->div_flags,
209 list->table, &lock); 223 list->table, &ctx->lock);
210 else 224 else
211 clk = clk_register_divider(NULL, list->name, 225 clk = clk_register_divider(NULL, list->name,
212 list->parent_name, list->flags, 226 list->parent_name, list->flags,
213 reg_base + list->offset, list->shift, 227 ctx->reg_base + list->offset, list->shift,
214 list->width, list->div_flags, &lock); 228 list->width, list->div_flags, &ctx->lock);
215 if (IS_ERR(clk)) { 229 if (IS_ERR(clk)) {
216 pr_err("%s: failed to register clock %s\n", __func__, 230 pr_err("%s: failed to register clock %s\n", __func__,
217 list->name); 231 list->name);
218 continue; 232 continue;
219 } 233 }
220 234
221 samsung_clk_add_lookup(clk, list->id); 235 samsung_clk_add_lookup(ctx, clk, list->id);
222 236
223 /* register a clock lookup only if a clock alias is specified */ 237 /* register a clock lookup only if a clock alias is specified */
224 if (list->alias) { 238 if (list->alias) {
@@ -232,16 +246,17 @@ void __init samsung_clk_register_div(struct samsung_div_clock *list,
232} 246}
233 247
234/* register a list of gate clocks */ 248/* register a list of gate clocks */
235void __init samsung_clk_register_gate(struct samsung_gate_clock *list, 249void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx,
236 unsigned int nr_clk) 250 struct samsung_gate_clock *list,
251 unsigned int nr_clk)
237{ 252{
238 struct clk *clk; 253 struct clk *clk;
239 unsigned int idx, ret; 254 unsigned int idx, ret;
240 255
241 for (idx = 0; idx < nr_clk; idx++, list++) { 256 for (idx = 0; idx < nr_clk; idx++, list++) {
242 clk = clk_register_gate(NULL, list->name, list->parent_name, 257 clk = clk_register_gate(NULL, list->name, list->parent_name,
243 list->flags, reg_base + list->offset, 258 list->flags, ctx->reg_base + list->offset,
244 list->bit_idx, list->gate_flags, &lock); 259 list->bit_idx, list->gate_flags, &ctx->lock);
245 if (IS_ERR(clk)) { 260 if (IS_ERR(clk)) {
246 pr_err("%s: failed to register clock %s\n", __func__, 261 pr_err("%s: failed to register clock %s\n", __func__,
247 list->name); 262 list->name);
@@ -257,7 +272,7 @@ void __init samsung_clk_register_gate(struct samsung_gate_clock *list,
257 __func__, list->alias); 272 __func__, list->alias);
258 } 273 }
259 274
260 samsung_clk_add_lookup(clk, list->id); 275 samsung_clk_add_lookup(ctx, clk, list->id);
261 } 276 }
262} 277}
263 278
@@ -266,21 +281,21 @@ void __init samsung_clk_register_gate(struct samsung_gate_clock *list,
266 * tree and register it 281 * tree and register it
267 */ 282 */
268#ifdef CONFIG_OF 283#ifdef CONFIG_OF
269void __init samsung_clk_of_register_fixed_ext( 284void __init samsung_clk_of_register_fixed_ext(struct samsung_clk_provider *ctx,
270 struct samsung_fixed_rate_clock *fixed_rate_clk, 285 struct samsung_fixed_rate_clock *fixed_rate_clk,
271 unsigned int nr_fixed_rate_clk, 286 unsigned int nr_fixed_rate_clk,
272 struct of_device_id *clk_matches) 287 struct of_device_id *clk_matches)
273{ 288{
274 const struct of_device_id *match; 289 const struct of_device_id *match;
275 struct device_node *np; 290 struct device_node *clk_np;
276 u32 freq; 291 u32 freq;
277 292
278 for_each_matching_node_and_match(np, clk_matches, &match) { 293 for_each_matching_node_and_match(clk_np, clk_matches, &match) {
279 if (of_property_read_u32(np, "clock-frequency", &freq)) 294 if (of_property_read_u32(clk_np, "clock-frequency", &freq))
280 continue; 295 continue;
281 fixed_rate_clk[(u32)match->data].fixed_rate = freq; 296 fixed_rate_clk[(unsigned long)match->data].fixed_rate = freq;
282 } 297 }
283 samsung_clk_register_fixed_rate(fixed_rate_clk, nr_fixed_rate_clk); 298 samsung_clk_register_fixed_rate(ctx, fixed_rate_clk, nr_fixed_rate_clk);
284} 299}
285#endif 300#endif
286 301
diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h
index c7141ba826e0..9693b80d924f 100644
--- a/drivers/clk/samsung/clk.h
+++ b/drivers/clk/samsung/clk.h
@@ -22,6 +22,18 @@
22#include "clk-pll.h" 22#include "clk-pll.h"
23 23
24/** 24/**
25 * struct samsung_clk_provider: information about clock provider
26 * @reg_base: virtual address for the register base.
27 * @clk_data: holds clock related data like clk* and number of clocks.
28 * @lock: maintains exclusion bwtween callbacks for a given clock-provider.
29 */
30struct samsung_clk_provider {
31 void __iomem *reg_base;
32 struct clk_onecell_data clk_data;
33 spinlock_t lock;
34};
35
36/**
25 * struct samsung_clock_alias: information about mux clock 37 * struct samsung_clock_alias: information about mux clock
26 * @id: platform specific id of the clock. 38 * @id: platform specific id of the clock.
27 * @dev_name: name of the device to which this clock belongs. 39 * @dev_name: name of the device to which this clock belongs.
@@ -312,40 +324,52 @@ struct samsung_pll_clock {
312 __PLL(_typ, _id, NULL, _name, _pname, CLK_GET_RATE_NOCACHE, \ 324 __PLL(_typ, _id, NULL, _name, _pname, CLK_GET_RATE_NOCACHE, \
313 _lock, _con, _rtable, _alias) 325 _lock, _con, _rtable, _alias)
314 326
315extern void __init samsung_clk_init(struct device_node *np, void __iomem *base, 327extern struct samsung_clk_provider *__init samsung_clk_init(
316 unsigned long nr_clks); 328 struct device_node *np, void __iomem *base,
329 unsigned long nr_clks);
317extern void __init samsung_clk_of_register_fixed_ext( 330extern void __init samsung_clk_of_register_fixed_ext(
318 struct samsung_fixed_rate_clock *fixed_rate_clk, 331 struct samsung_clk_provider *ctx,
319 unsigned int nr_fixed_rate_clk, 332 struct samsung_fixed_rate_clock *fixed_rate_clk,
320 struct of_device_id *clk_matches); 333 unsigned int nr_fixed_rate_clk,
334 struct of_device_id *clk_matches);
321 335
322extern void samsung_clk_add_lookup(struct clk *clk, unsigned int id); 336extern void samsung_clk_add_lookup(struct samsung_clk_provider *ctx,
337 struct clk *clk, unsigned int id);
323 338
324extern void samsung_clk_register_alias(struct samsung_clock_alias *list, 339extern void samsung_clk_register_alias(struct samsung_clk_provider *ctx,
325 unsigned int nr_clk); 340 struct samsung_clock_alias *list,
341 unsigned int nr_clk);
326extern void __init samsung_clk_register_fixed_rate( 342extern void __init samsung_clk_register_fixed_rate(
327 struct samsung_fixed_rate_clock *clk_list, unsigned int nr_clk); 343 struct samsung_clk_provider *ctx,
344 struct samsung_fixed_rate_clock *clk_list,
345 unsigned int nr_clk);
328extern void __init samsung_clk_register_fixed_factor( 346extern void __init samsung_clk_register_fixed_factor(
329 struct samsung_fixed_factor_clock *list, unsigned int nr_clk); 347 struct samsung_clk_provider *ctx,
330extern void __init samsung_clk_register_mux(struct samsung_mux_clock *clk_list, 348 struct samsung_fixed_factor_clock *list,
331 unsigned int nr_clk); 349 unsigned int nr_clk);
332extern void __init samsung_clk_register_div(struct samsung_div_clock *clk_list, 350extern void __init samsung_clk_register_mux(struct samsung_clk_provider *ctx,
333 unsigned int nr_clk); 351 struct samsung_mux_clock *clk_list,
334extern void __init samsung_clk_register_gate( 352 unsigned int nr_clk);
335 struct samsung_gate_clock *clk_list, unsigned int nr_clk); 353extern void __init samsung_clk_register_div(struct samsung_clk_provider *ctx,
336extern void __init samsung_clk_register_pll(struct samsung_pll_clock *pll_list, 354 struct samsung_div_clock *clk_list,
337 unsigned int nr_clk, void __iomem *base); 355 unsigned int nr_clk);
356extern void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx,
357 struct samsung_gate_clock *clk_list,
358 unsigned int nr_clk);
359extern void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx,
360 struct samsung_pll_clock *pll_list,
361 unsigned int nr_clk, void __iomem *base);
338 362
339extern unsigned long _get_rate(const char *clk_name); 363extern unsigned long _get_rate(const char *clk_name);
340 364
341extern void samsung_clk_save(void __iomem *base, 365extern void samsung_clk_save(void __iomem *base,
342 struct samsung_clk_reg_dump *rd, 366 struct samsung_clk_reg_dump *rd,
343 unsigned int num_regs); 367 unsigned int num_regs);
344extern void samsung_clk_restore(void __iomem *base, 368extern void samsung_clk_restore(void __iomem *base,
345 const struct samsung_clk_reg_dump *rd, 369 const struct samsung_clk_reg_dump *rd,
346 unsigned int num_regs); 370 unsigned int num_regs);
347extern struct samsung_clk_reg_dump *samsung_clk_alloc_reg_dump( 371extern struct samsung_clk_reg_dump *samsung_clk_alloc_reg_dump(
348 const unsigned long *rdump, 372 const unsigned long *rdump,
349 unsigned long nr_rdump); 373 unsigned long nr_rdump);
350 374
351#endif /* __SAMSUNG_CLK_H */ 375#endif /* __SAMSUNG_CLK_H */
diff --git a/include/dt-bindings/clock/exynos3250.h b/include/dt-bindings/clock/exynos3250.h
new file mode 100644
index 000000000000..b535e9da7de6
--- /dev/null
+++ b/include/dt-bindings/clock/exynos3250.h
@@ -0,0 +1,258 @@
1/*
2 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
3 * Author: Tomasz Figa <t.figa@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * Device Tree binding constants for Samsung Exynos3250 clock controllers.
10 */
11
12#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H
13#define _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H
14
15/*
16 * Let each exported clock get a unique index, which is used on DT-enabled
17 * platforms to lookup the clock from a clock specifier. These indices are
18 * therefore considered an ABI and so must not be changed. This implies
19 * that new clocks should be added either in free spaces between clock groups
20 * or at the end.
21 */
22
23
24/*
25 * Main CMU
26 */
27
28#define CLK_OSCSEL 1
29#define CLK_FIN_PLL 2
30#define CLK_FOUT_APLL 3
31#define CLK_FOUT_VPLL 4
32#define CLK_FOUT_UPLL 5
33#define CLK_FOUT_MPLL 6
34
35/* Muxes */
36#define CLK_MOUT_MPLL_USER_L 16
37#define CLK_MOUT_GDL 17
38#define CLK_MOUT_MPLL_USER_R 18
39#define CLK_MOUT_GDR 19
40#define CLK_MOUT_EBI 20
41#define CLK_MOUT_ACLK_200 21
42#define CLK_MOUT_ACLK_160 22
43#define CLK_MOUT_ACLK_100 23
44#define CLK_MOUT_ACLK_266_1 24
45#define CLK_MOUT_ACLK_266_0 25
46#define CLK_MOUT_ACLK_266 26
47#define CLK_MOUT_VPLL 27
48#define CLK_MOUT_EPLL_USER 28
49#define CLK_MOUT_EBI_1 29
50#define CLK_MOUT_UPLL 30
51#define CLK_MOUT_ACLK_400_MCUISP_SUB 31
52#define CLK_MOUT_MPLL 32
53#define CLK_MOUT_ACLK_400_MCUISP 33
54#define CLK_MOUT_VPLLSRC 34
55#define CLK_MOUT_CAM1 35
56#define CLK_MOUT_CAM_BLK 36
57#define CLK_MOUT_MFC 37
58#define CLK_MOUT_MFC_1 38
59#define CLK_MOUT_MFC_0 39
60#define CLK_MOUT_G3D 40
61#define CLK_MOUT_G3D_1 41
62#define CLK_MOUT_G3D_0 42
63#define CLK_MOUT_MIPI0 43
64#define CLK_MOUT_FIMD0 44
65#define CLK_MOUT_UART_ISP 45
66#define CLK_MOUT_SPI1_ISP 46
67#define CLK_MOUT_SPI0_ISP 47
68#define CLK_MOUT_TSADC 48
69#define CLK_MOUT_MMC1 49
70#define CLK_MOUT_MMC0 50
71#define CLK_MOUT_UART1 51
72#define CLK_MOUT_UART0 52
73#define CLK_MOUT_SPI1 53
74#define CLK_MOUT_SPI0 54
75#define CLK_MOUT_AUDIO 55
76#define CLK_MOUT_MPLL_USER_C 56
77#define CLK_MOUT_HPM 57
78#define CLK_MOUT_CORE 58
79#define CLK_MOUT_APLL 59
80#define CLK_MOUT_ACLK_266_SUB 60
81
82/* Dividers */
83#define CLK_DIV_GPL 64
84#define CLK_DIV_GDL 65
85#define CLK_DIV_GPR 66
86#define CLK_DIV_GDR 67
87#define CLK_DIV_MPLL_PRE 68
88#define CLK_DIV_ACLK_400_MCUISP 69
89#define CLK_DIV_EBI 70
90#define CLK_DIV_ACLK_200 71
91#define CLK_DIV_ACLK_160 72
92#define CLK_DIV_ACLK_100 73
93#define CLK_DIV_ACLK_266 74
94#define CLK_DIV_CAM1 75
95#define CLK_DIV_CAM_BLK 76
96#define CLK_DIV_MFC 77
97#define CLK_DIV_G3D 78
98#define CLK_DIV_MIPI0_PRE 79
99#define CLK_DIV_MIPI0 80
100#define CLK_DIV_FIMD0 81
101#define CLK_DIV_UART_ISP 82
102#define CLK_DIV_SPI1_ISP_PRE 83
103#define CLK_DIV_SPI1_ISP 84
104#define CLK_DIV_SPI0_ISP_PRE 85
105#define CLK_DIV_SPI0_ISP 86
106#define CLK_DIV_TSADC_PRE 87
107#define CLK_DIV_TSADC 88
108#define CLK_DIV_MMC1_PRE 89
109#define CLK_DIV_MMC1 90
110#define CLK_DIV_MMC0_PRE 91
111#define CLK_DIV_MMC0 92
112#define CLK_DIV_UART1 93
113#define CLK_DIV_UART0 94
114#define CLK_DIV_SPI1_PRE 95
115#define CLK_DIV_SPI1 96
116#define CLK_DIV_SPI0_PRE 97
117#define CLK_DIV_SPI0 98
118#define CLK_DIV_PCM 99
119#define CLK_DIV_AUDIO 100
120#define CLK_DIV_I2S 101
121#define CLK_DIV_CORE2 102
122#define CLK_DIV_APLL 103
123#define CLK_DIV_PCLK_DBG 104
124#define CLK_DIV_ATB 105
125#define CLK_DIV_COREM 106
126#define CLK_DIV_CORE 107
127#define CLK_DIV_HPM 108
128#define CLK_DIV_COPY 109
129
130/* Gates */
131#define CLK_ASYNC_G3D 128
132#define CLK_ASYNC_MFCL 129
133#define CLK_PPMULEFT 130
134#define CLK_GPIO_LEFT 131
135#define CLK_ASYNC_ISPMX 132
136#define CLK_ASYNC_FSYSD 133
137#define CLK_ASYNC_LCD0X 134
138#define CLK_ASYNC_CAMX 135
139#define CLK_PPMURIGHT 136
140#define CLK_GPIO_RIGHT 137
141#define CLK_MONOCNT 138
142#define CLK_TZPC6 139
143#define CLK_PROVISIONKEY1 140
144#define CLK_PROVISIONKEY0 141
145#define CLK_CMU_ISPPART 142
146#define CLK_TMU_APBIF 143
147#define CLK_KEYIF 144
148#define CLK_RTC 145
149#define CLK_WDT 146
150#define CLK_MCT 147
151#define CLK_SECKEY 148
152#define CLK_TZPC5 149
153#define CLK_TZPC4 150
154#define CLK_TZPC3 151
155#define CLK_TZPC2 152
156#define CLK_TZPC1 153
157#define CLK_TZPC0 154
158#define CLK_CMU_COREPART 155
159#define CLK_CMU_TOPPART 156
160#define CLK_PMU_APBIF 157
161#define CLK_SYSREG 158
162#define CLK_CHIP_ID 159
163#define CLK_QEJPEG 160
164#define CLK_PIXELASYNCM1 161
165#define CLK_PIXELASYNCM0 162
166#define CLK_PPMUCAMIF 163
167#define CLK_QEM2MSCALER 164
168#define CLK_QEGSCALER1 165
169#define CLK_QEGSCALER0 166
170#define CLK_SMMUJPEG 167
171#define CLK_SMMUM2M2SCALER 168
172#define CLK_SMMUGSCALER1 169
173#define CLK_SMMUGSCALER0 170
174#define CLK_JPEG 171
175#define CLK_M2MSCALER 172
176#define CLK_GSCALER1 173
177#define CLK_GSCALER0 174
178#define CLK_QEMFC 175
179#define CLK_PPMUMFC_L 176
180#define CLK_SMMUMFC_L 177
181#define CLK_MFC 178
182#define CLK_SMMUG3D 179
183#define CLK_QEG3D 180
184#define CLK_PPMUG3D 181
185#define CLK_G3D 182
186#define CLK_QE_CH1_LCD 183
187#define CLK_QE_CH0_LCD 184
188#define CLK_PPMULCD0 185
189#define CLK_SMMUFIMD0 186
190#define CLK_DSIM0 187
191#define CLK_FIMD0 188
192#define CLK_CAM1 189
193#define CLK_UART_ISP_TOP 190
194#define CLK_SPI1_ISP_TOP 191
195#define CLK_SPI0_ISP_TOP 192
196#define CLK_TSADC 193
197#define CLK_PPMUFILE 194
198#define CLK_USBOTG 195
199#define CLK_USBHOST 196
200#define CLK_SROMC 197
201#define CLK_SDMMC1 198
202#define CLK_SDMMC0 199
203#define CLK_PDMA1 200
204#define CLK_PDMA0 201
205#define CLK_PWM 202
206#define CLK_PCM 203
207#define CLK_I2S 204
208#define CLK_SPI1 205
209#define CLK_SPI0 206
210#define CLK_I2C7 207
211#define CLK_I2C6 208
212#define CLK_I2C5 209
213#define CLK_I2C4 210
214#define CLK_I2C3 211
215#define CLK_I2C2 212
216#define CLK_I2C1 213
217#define CLK_I2C0 214
218#define CLK_UART1 215
219#define CLK_UART0 216
220#define CLK_BLOCK_LCD 217
221#define CLK_BLOCK_G3D 218
222#define CLK_BLOCK_MFC 219
223#define CLK_BLOCK_CAM 220
224#define CLK_SMIES 221
225
226/* Special clocks */
227#define CLK_SCLK_JPEG 224
228#define CLK_SCLK_M2MSCALER 225
229#define CLK_SCLK_GSCALER1 226
230#define CLK_SCLK_GSCALER0 227
231#define CLK_SCLK_MFC 228
232#define CLK_SCLK_G3D 229
233#define CLK_SCLK_MIPIDPHY2L 230
234#define CLK_SCLK_MIPI0 231
235#define CLK_SCLK_FIMD0 232
236#define CLK_SCLK_CAM1 233
237#define CLK_SCLK_UART_ISP 234
238#define CLK_SCLK_SPI1_ISP 235
239#define CLK_SCLK_SPI0_ISP 236
240#define CLK_SCLK_UPLL 237
241#define CLK_SCLK_TSADC 238
242#define CLK_SCLK_EBI 239
243#define CLK_SCLK_MMC1 240
244#define CLK_SCLK_MMC0 241
245#define CLK_SCLK_I2S 242
246#define CLK_SCLK_PCM 243
247#define CLK_SCLK_SPI1 244
248#define CLK_SCLK_SPI0 245
249#define CLK_SCLK_UART1 246
250#define CLK_SCLK_UART0 247
251
252/*
253 * Total number of clocks of main CMU.
254 * NOTE: Must be equal to last clock ID increased by one.
255 */
256#define CLK_NR_CLKS 248
257
258#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H */
diff --git a/include/dt-bindings/clock/exynos4.h b/include/dt-bindings/clock/exynos4.h
index 75aff336dfb0..1106ca540a96 100644
--- a/include/dt-bindings/clock/exynos4.h
+++ b/include/dt-bindings/clock/exynos4.h
@@ -33,6 +33,7 @@
33#define CLK_MOUT_MPLL_USER_C 18 /* Exynos4x12 only */ 33#define CLK_MOUT_MPLL_USER_C 18 /* Exynos4x12 only */
34#define CLK_MOUT_CORE 19 34#define CLK_MOUT_CORE 19
35#define CLK_MOUT_APLL 20 35#define CLK_MOUT_APLL 20
36#define CLK_SCLK_HDMIPHY 22
36 37
37/* gate for special clocks (sclk) */ 38/* gate for special clocks (sclk) */
38#define CLK_SCLK_FIMC0 128 39#define CLK_SCLK_FIMC0 128
@@ -181,7 +182,6 @@
181#define CLK_KEYIF 347 182#define CLK_KEYIF 347
182#define CLK_AUDSS 348 183#define CLK_AUDSS 348
183#define CLK_MIPI_HSI 349 /* Exynos4210 only */ 184#define CLK_MIPI_HSI 349 /* Exynos4210 only */
184#define CLK_MDMA2 350 /* Exynos4210 only */
185#define CLK_PIXELASYNCM0 351 185#define CLK_PIXELASYNCM0 351
186#define CLK_PIXELASYNCM1 352 186#define CLK_PIXELASYNCM1 352
187#define CLK_FIMC_LITE0 353 /* Exynos4x12 only */ 187#define CLK_FIMC_LITE0 353 /* Exynos4x12 only */
diff --git a/include/dt-bindings/clock/exynos5250.h b/include/dt-bindings/clock/exynos5250.h
index 922f2dca9bf0..be6e97c54f54 100644
--- a/include/dt-bindings/clock/exynos5250.h
+++ b/include/dt-bindings/clock/exynos5250.h
@@ -150,11 +150,30 @@
150#define CLK_G2D 345 150#define CLK_G2D 345
151#define CLK_MDMA0 346 151#define CLK_MDMA0 346
152#define CLK_SMMU_MDMA0 347 152#define CLK_SMMU_MDMA0 347
153#define CLK_SSS 348
154#define CLK_G3D 349
155#define CLK_SMMU_TV 350
156#define CLK_SMMU_FIMD1 351
157#define CLK_SMMU_2D 352
158#define CLK_SMMU_FIMC_ISP 353
159#define CLK_SMMU_FIMC_DRC 354
160#define CLK_SMMU_FIMC_SCC 355
161#define CLK_SMMU_FIMC_SCP 356
162#define CLK_SMMU_FIMC_FD 357
163#define CLK_SMMU_FIMC_MCU 358
164#define CLK_SMMU_FIMC_ODC 359
165#define CLK_SMMU_FIMC_DIS0 360
166#define CLK_SMMU_FIMC_DIS1 361
167#define CLK_SMMU_FIMC_3DNR 362
168#define CLK_SMMU_FIMC_LITE0 363
169#define CLK_SMMU_FIMC_LITE1 364
170#define CLK_CAMIF_TOP 365
153 171
154/* mux clocks */ 172/* mux clocks */
155#define CLK_MOUT_HDMI 1024 173#define CLK_MOUT_HDMI 1024
174#define CLK_MOUT_GPLL 1025
156 175
157/* must be greater than maximal clock id */ 176/* must be greater than maximal clock id */
158#define CLK_NR_CLKS 1025 177#define CLK_NR_CLKS 1026
159 178
160#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5250_H */ 179#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5250_H */
diff --git a/include/dt-bindings/clock/exynos5260-clk.h b/include/dt-bindings/clock/exynos5260-clk.h
new file mode 100644
index 000000000000..a4bac9a1764f
--- /dev/null
+++ b/include/dt-bindings/clock/exynos5260-clk.h
@@ -0,0 +1,469 @@
1/*
2 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
3 * Author: Rahul Sharma <rahul.sharma@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * Provides Constants for Exynos5260 clocks.
10*/
11
12#ifndef _DT_BINDINGS_CLK_EXYNOS5260_H
13#define _DT_BINDINGS_CLK_EXYNOS5260_H
14
15/* Clock names: <cmu><type><IP> */
16
17/* List Of Clocks For CMU_TOP */
18
19#define TOP_FOUT_DISP_PLL 1
20#define TOP_FOUT_AUD_PLL 2
21#define TOP_MOUT_AUDTOP_PLL_USER 3
22#define TOP_MOUT_AUD_PLL 4
23#define TOP_MOUT_DISP_PLL 5
24#define TOP_MOUT_BUSTOP_PLL_USER 6
25#define TOP_MOUT_MEMTOP_PLL_USER 7
26#define TOP_MOUT_MEDIATOP_PLL_USER 8
27#define TOP_MOUT_DISP_DISP_333 9
28#define TOP_MOUT_ACLK_DISP_333 10
29#define TOP_MOUT_DISP_DISP_222 11
30#define TOP_MOUT_ACLK_DISP_222 12
31#define TOP_MOUT_DISP_MEDIA_PIXEL 13
32#define TOP_MOUT_FIMD1 14
33#define TOP_MOUT_SCLK_PERI_SPI0_CLK 15
34#define TOP_MOUT_SCLK_PERI_SPI1_CLK 16
35#define TOP_MOUT_SCLK_PERI_SPI2_CLK 17
36#define TOP_MOUT_SCLK_PERI_UART0_UCLK 18
37#define TOP_MOUT_SCLK_PERI_UART2_UCLK 19
38#define TOP_MOUT_SCLK_PERI_UART1_UCLK 20
39#define TOP_MOUT_BUS4_BUSTOP_100 21
40#define TOP_MOUT_BUS4_BUSTOP_400 22
41#define TOP_MOUT_BUS3_BUSTOP_100 23
42#define TOP_MOUT_BUS3_BUSTOP_400 24
43#define TOP_MOUT_BUS2_BUSTOP_400 25
44#define TOP_MOUT_BUS2_BUSTOP_100 26
45#define TOP_MOUT_BUS1_BUSTOP_100 27
46#define TOP_MOUT_BUS1_BUSTOP_400 28
47#define TOP_MOUT_SCLK_FSYS_USB 29
48#define TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A 30
49#define TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A 31
50#define TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A 32
51#define TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_B 33
52#define TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_B 34
53#define TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_B 35
54#define TOP_MOUT_ACLK_ISP1_266 36
55#define TOP_MOUT_ISP1_MEDIA_266 37
56#define TOP_MOUT_ACLK_ISP1_400 38
57#define TOP_MOUT_ISP1_MEDIA_400 39
58#define TOP_MOUT_SCLK_ISP1_SPI0 40
59#define TOP_MOUT_SCLK_ISP1_SPI1 41
60#define TOP_MOUT_SCLK_ISP1_UART 42
61#define TOP_MOUT_SCLK_ISP1_SENSOR2 43
62#define TOP_MOUT_SCLK_ISP1_SENSOR1 44
63#define TOP_MOUT_SCLK_ISP1_SENSOR0 45
64#define TOP_MOUT_ACLK_MFC_333 46
65#define TOP_MOUT_MFC_BUSTOP_333 47
66#define TOP_MOUT_ACLK_G2D_333 48
67#define TOP_MOUT_G2D_BUSTOP_333 49
68#define TOP_MOUT_ACLK_GSCL_FIMC 50
69#define TOP_MOUT_GSCL_BUSTOP_FIMC 51
70#define TOP_MOUT_ACLK_GSCL_333 52
71#define TOP_MOUT_GSCL_BUSTOP_333 53
72#define TOP_MOUT_ACLK_GSCL_400 54
73#define TOP_MOUT_M2M_MEDIATOP_400 55
74#define TOP_DOUT_ACLK_MFC_333 56
75#define TOP_DOUT_ACLK_G2D_333 57
76#define TOP_DOUT_SCLK_ISP1_SENSOR2_A 58
77#define TOP_DOUT_SCLK_ISP1_SENSOR1_A 59
78#define TOP_DOUT_SCLK_ISP1_SENSOR0_A 60
79#define TOP_DOUT_ACLK_GSCL_FIMC 61
80#define TOP_DOUT_ACLK_GSCL_400 62
81#define TOP_DOUT_ACLK_GSCL_333 63
82#define TOP_DOUT_SCLK_ISP1_SPI0_B 64
83#define TOP_DOUT_SCLK_ISP1_SPI0_A 65
84#define TOP_DOUT_ACLK_ISP1_400 66
85#define TOP_DOUT_ACLK_ISP1_266 67
86#define TOP_DOUT_SCLK_ISP1_UART 68
87#define TOP_DOUT_SCLK_ISP1_SPI1_B 69
88#define TOP_DOUT_SCLK_ISP1_SPI1_A 70
89#define TOP_DOUT_SCLK_ISP1_SENSOR2_B 71
90#define TOP_DOUT_SCLK_ISP1_SENSOR1_B 72
91#define TOP_DOUT_SCLK_ISP1_SENSOR0_B 73
92#define TOP_DOUTTOP__SCLK_HPM_TARGETCLK 74
93#define TOP_DOUT_SCLK_DISP_PIXEL 75
94#define TOP_DOUT_ACLK_DISP_222 76
95#define TOP_DOUT_ACLK_DISP_333 77
96#define TOP_DOUT_ACLK_BUS4_100 78
97#define TOP_DOUT_ACLK_BUS4_400 79
98#define TOP_DOUT_ACLK_BUS3_100 80
99#define TOP_DOUT_ACLK_BUS3_400 81
100#define TOP_DOUT_ACLK_BUS2_100 82
101#define TOP_DOUT_ACLK_BUS2_400 83
102#define TOP_DOUT_ACLK_BUS1_100 84
103#define TOP_DOUT_ACLK_BUS1_400 85
104#define TOP_DOUT_SCLK_PERI_SPI1_B 86
105#define TOP_DOUT_SCLK_PERI_SPI1_A 87
106#define TOP_DOUT_SCLK_PERI_SPI0_B 88
107#define TOP_DOUT_SCLK_PERI_SPI0_A 89
108#define TOP_DOUT_SCLK_PERI_UART0 90
109#define TOP_DOUT_SCLK_PERI_UART2 91
110#define TOP_DOUT_SCLK_PERI_UART1 92
111#define TOP_DOUT_SCLK_PERI_SPI2_B 93
112#define TOP_DOUT_SCLK_PERI_SPI2_A 94
113#define TOP_DOUT_ACLK_PERI_AUD 95
114#define TOP_DOUT_ACLK_PERI_66 96
115#define TOP_DOUT_SCLK_FSYS_MMC0_SDCLKIN_B 97
116#define TOP_DOUT_SCLK_FSYS_MMC0_SDCLKIN_A 98
117#define TOP_DOUT_SCLK_FSYS_USBDRD30_SUSPEND_CLK 99
118#define TOP_DOUT_ACLK_FSYS_200 100
119#define TOP_DOUT_SCLK_FSYS_MMC2_SDCLKIN_B 101
120#define TOP_DOUT_SCLK_FSYS_MMC2_SDCLKIN_A 102
121#define TOP_DOUT_SCLK_FSYS_MMC1_SDCLKIN_B 103
122#define TOP_DOUT_SCLK_FSYS_MMC1_SDCLKIN_A 104
123#define TOP_SCLK_FIMD1 105
124#define TOP_SCLK_MMC2 106
125#define TOP_SCLK_MMC1 107
126#define TOP_SCLK_MMC0 108
127#define PHYCLK_DPTX_PHY_CH3_TXD_CLK 109
128#define PHYCLK_DPTX_PHY_CH2_TXD_CLK 110
129#define PHYCLK_DPTX_PHY_CH1_TXD_CLK 111
130#define PHYCLK_DPTX_PHY_CH0_TXD_CLK 112
131#define phyclk_hdmi_phy_tmds_clko 113
132#define PHYCLK_HDMI_PHY_PIXEL_CLKO 114
133#define PHYCLK_HDMI_LINK_O_TMDS_CLKHI 115
134#define PHYCLK_MIPI_DPHY_4L_M_TXBYTECLKHS 116
135#define PHYCLK_DPTX_PHY_O_REF_CLK_24M 117
136#define PHYCLK_DPTX_PHY_CLK_DIV2 118
137#define PHYCLK_MIPI_DPHY_4L_M_RXCLKESC0 119
138#define PHYCLK_USBHOST20_PHY_PHYCLOCK 120
139#define PHYCLK_USBHOST20_PHY_FREECLK 121
140#define PHYCLK_USBHOST20_PHY_CLK48MOHCI 122
141#define PHYCLK_USBDRD30_UDRD30_PIPE_PCLK 123
142#define PHYCLK_USBDRD30_UDRD30_PHYCLOCK 124
143#define TOP_NR_CLK 125
144
145
146/* List Of Clocks For CMU_EGL */
147
148#define EGL_FOUT_EGL_PLL 1
149#define EGL_FOUT_EGL_DPLL 2
150#define EGL_MOUT_EGL_B 3
151#define EGL_MOUT_EGL_PLL 4
152#define EGL_DOUT_EGL_PLL 5
153#define EGL_DOUT_EGL_PCLK_DBG 6
154#define EGL_DOUT_EGL_ATCLK 7
155#define EGL_DOUT_PCLK_EGL 8
156#define EGL_DOUT_ACLK_EGL 9
157#define EGL_DOUT_EGL2 10
158#define EGL_DOUT_EGL1 11
159#define EGL_NR_CLK 12
160
161
162/* List Of Clocks For CMU_KFC */
163
164#define KFC_FOUT_KFC_PLL 1
165#define KFC_MOUT_KFC_PLL 2
166#define KFC_MOUT_KFC 3
167#define KFC_DOUT_KFC_PLL 4
168#define KFC_DOUT_PCLK_KFC 5
169#define KFC_DOUT_ACLK_KFC 6
170#define KFC_DOUT_KFC_PCLK_DBG 7
171#define KFC_DOUT_KFC_ATCLK 8
172#define KFC_DOUT_KFC2 9
173#define KFC_DOUT_KFC1 10
174#define KFC_NR_CLK 11
175
176
177/* List Of Clocks For CMU_MIF */
178
179#define MIF_FOUT_MEM_PLL 1
180#define MIF_FOUT_MEDIA_PLL 2
181#define MIF_FOUT_BUS_PLL 3
182#define MIF_MOUT_CLK2X_PHY 4
183#define MIF_MOUT_MIF_DREX2X 5
184#define MIF_MOUT_CLKM_PHY 6
185#define MIF_MOUT_MIF_DREX 7
186#define MIF_MOUT_MEDIA_PLL 8
187#define MIF_MOUT_BUS_PLL 9
188#define MIF_MOUT_MEM_PLL 10
189#define MIF_DOUT_ACLK_BUS_100 11
190#define MIF_DOUT_ACLK_BUS_200 12
191#define MIF_DOUT_ACLK_MIF_466 13
192#define MIF_DOUT_CLK2X_PHY 14
193#define MIF_DOUT_CLKM_PHY 15
194#define MIF_DOUT_BUS_PLL 16
195#define MIF_DOUT_MEM_PLL 17
196#define MIF_DOUT_MEDIA_PLL 18
197#define MIF_CLK_LPDDR3PHY_WRAP1 19
198#define MIF_CLK_LPDDR3PHY_WRAP0 20
199#define MIF_CLK_MONOCNT 21
200#define MIF_CLK_MIF_RTC 22
201#define MIF_CLK_DREX1 23
202#define MIF_CLK_DREX0 24
203#define MIF_CLK_INTMEM 25
204#define MIF_SCLK_LPDDR3PHY_WRAP_U1 26
205#define MIF_SCLK_LPDDR3PHY_WRAP_U0 27
206#define MIF_NR_CLK 28
207
208
209/* List Of Clocks For CMU_G3D */
210
211#define G3D_FOUT_G3D_PLL 1
212#define G3D_MOUT_G3D_PLL 2
213#define G3D_DOUT_PCLK_G3D 3
214#define G3D_DOUT_ACLK_G3D 4
215#define G3D_CLK_G3D_HPM 5
216#define G3D_CLK_G3D 6
217#define G3D_NR_CLK 7
218
219
220/* List Of Clocks For CMU_AUD */
221
222#define AUD_MOUT_SCLK_AUD_PCM 1
223#define AUD_MOUT_SCLK_AUD_I2S 2
224#define AUD_MOUT_AUD_PLL_USER 3
225#define AUD_DOUT_ACLK_AUD_131 4
226#define AUD_DOUT_SCLK_AUD_UART 5
227#define AUD_DOUT_SCLK_AUD_PCM 6
228#define AUD_DOUT_SCLK_AUD_I2S 7
229#define AUD_CLK_AUD_UART 8
230#define AUD_CLK_PCM 9
231#define AUD_CLK_I2S 10
232#define AUD_CLK_DMAC 11
233#define AUD_CLK_SRAMC 12
234#define AUD_SCLK_AUD_UART 13
235#define AUD_SCLK_PCM 14
236#define AUD_SCLK_I2S 15
237#define AUD_NR_CLK 16
238
239
240/* List Of Clocks For CMU_MFC */
241
242#define MFC_MOUT_ACLK_MFC_333_USER 1
243#define MFC_DOUT_PCLK_MFC_83 2
244#define MFC_CLK_MFC 3
245#define MFC_CLK_SMMU2_MFCM1 4
246#define MFC_CLK_SMMU2_MFCM0 5
247#define MFC_NR_CLK 6
248
249
250/* List Of Clocks For CMU_GSCL */
251
252#define GSCL_MOUT_ACLK_CSIS 1
253#define GSCL_MOUT_ACLK_GSCL_FIMC_USER 2
254#define GSCL_MOUT_ACLK_M2M_400_USER 3
255#define GSCL_MOUT_ACLK_GSCL_333_USER 4
256#define GSCL_DOUT_ACLK_CSIS_200 5
257#define GSCL_DOUT_PCLK_M2M_100 6
258#define GSCL_CLK_PIXEL_GSCL1 7
259#define GSCL_CLK_PIXEL_GSCL0 8
260#define GSCL_CLK_MSCL1 9
261#define GSCL_CLK_MSCL0 10
262#define GSCL_CLK_GSCL1 11
263#define GSCL_CLK_GSCL0 12
264#define GSCL_CLK_FIMC_LITE_D 13
265#define GSCL_CLK_FIMC_LITE_B 14
266#define GSCL_CLK_FIMC_LITE_A 15
267#define GSCL_CLK_CSIS1 16
268#define GSCL_CLK_CSIS0 17
269#define GSCL_CLK_SMMU3_LITE_D 18
270#define GSCL_CLK_SMMU3_LITE_B 19
271#define GSCL_CLK_SMMU3_LITE_A 20
272#define GSCL_CLK_SMMU3_GSCL0 21
273#define GSCL_CLK_SMMU3_GSCL1 22
274#define GSCL_CLK_SMMU3_MSCL0 23
275#define GSCL_CLK_SMMU3_MSCL1 24
276#define GSCL_SCLK_CSIS1_WRAP 25
277#define GSCL_SCLK_CSIS0_WRAP 26
278#define GSCL_NR_CLK 27
279
280
281/* List Of Clocks For CMU_FSYS */
282
283#define FSYS_MOUT_PHYCLK_USBHOST20_PHYCLK_USER 1
284#define FSYS_MOUT_PHYCLK_USBHOST20_FREECLK_USER 2
285#define FSYS_MOUT_PHYCLK_USBHOST20_CLK48MOHCI_USER 3
286#define FSYS_MOUT_PHYCLK_USBDRD30_PIPE_PCLK_USER 4
287#define FSYS_MOUT_PHYCLK_USBDRD30_PHYCLOCK_USER 5
288#define FSYS_CLK_TSI 6
289#define FSYS_CLK_USBLINK 7
290#define FSYS_CLK_USBHOST20 8
291#define FSYS_CLK_USBDRD30 9
292#define FSYS_CLK_SROMC 10
293#define FSYS_CLK_PDMA 11
294#define FSYS_CLK_MMC2 12
295#define FSYS_CLK_MMC1 13
296#define FSYS_CLK_MMC0 14
297#define FSYS_CLK_RTIC 15
298#define FSYS_CLK_SMMU_RTIC 16
299#define FSYS_PHYCLK_USBDRD30 17
300#define FSYS_PHYCLK_USBHOST20 18
301#define FSYS_NR_CLK 19
302
303
304/* List Of Clocks For CMU_PERI */
305
306#define PERI_MOUT_SCLK_SPDIF 1
307#define PERI_MOUT_SCLK_I2SCOD 2
308#define PERI_MOUT_SCLK_PCM 3
309#define PERI_DOUT_I2S 4
310#define PERI_DOUT_PCM 5
311#define PERI_CLK_WDT_KFC 6
312#define PERI_CLK_WDT_EGL 7
313#define PERI_CLK_HSIC3 8
314#define PERI_CLK_HSIC2 9
315#define PERI_CLK_HSIC1 10
316#define PERI_CLK_HSIC0 11
317#define PERI_CLK_PCM 12
318#define PERI_CLK_MCT 13
319#define PERI_CLK_I2S 14
320#define PERI_CLK_I2CHDMI 15
321#define PERI_CLK_I2C7 16
322#define PERI_CLK_I2C6 17
323#define PERI_CLK_I2C5 18
324#define PERI_CLK_I2C4 19
325#define PERI_CLK_I2C9 20
326#define PERI_CLK_I2C8 21
327#define PERI_CLK_I2C11 22
328#define PERI_CLK_I2C10 23
329#define PERI_CLK_HDMICEC 24
330#define PERI_CLK_EFUSE_WRITER 25
331#define PERI_CLK_ABB 26
332#define PERI_CLK_UART2 27
333#define PERI_CLK_UART1 28
334#define PERI_CLK_UART0 29
335#define PERI_CLK_ADC 30
336#define PERI_CLK_TMU4 31
337#define PERI_CLK_TMU3 32
338#define PERI_CLK_TMU2 33
339#define PERI_CLK_TMU1 34
340#define PERI_CLK_TMU0 35
341#define PERI_CLK_SPI2 36
342#define PERI_CLK_SPI1 37
343#define PERI_CLK_SPI0 38
344#define PERI_CLK_SPDIF 39
345#define PERI_CLK_PWM 40
346#define PERI_CLK_UART4 41
347#define PERI_CLK_CHIPID 42
348#define PERI_CLK_PROVKEY0 43
349#define PERI_CLK_PROVKEY1 44
350#define PERI_CLK_SECKEY 45
351#define PERI_CLK_TOP_RTC 46
352#define PERI_CLK_TZPC10 47
353#define PERI_CLK_TZPC9 48
354#define PERI_CLK_TZPC8 49
355#define PERI_CLK_TZPC7 50
356#define PERI_CLK_TZPC6 51
357#define PERI_CLK_TZPC5 52
358#define PERI_CLK_TZPC4 53
359#define PERI_CLK_TZPC3 54
360#define PERI_CLK_TZPC2 55
361#define PERI_CLK_TZPC1 56
362#define PERI_CLK_TZPC0 57
363#define PERI_SCLK_UART2 58
364#define PERI_SCLK_UART1 59
365#define PERI_SCLK_UART0 60
366#define PERI_SCLK_SPI2 61
367#define PERI_SCLK_SPI1 62
368#define PERI_SCLK_SPI0 63
369#define PERI_SCLK_SPDIF 64
370#define PERI_SCLK_I2S 65
371#define PERI_SCLK_PCM1 66
372#define PERI_NR_CLK 67
373
374
375/* List Of Clocks For CMU_DISP */
376
377#define DISP_MOUT_SCLK_HDMI_SPDIF 1
378#define DISP_MOUT_SCLK_HDMI_PIXEL 2
379#define DISP_MOUT_PHYCLK_MIPI_DPHY_4LMRXCLK_ESC0_USER 3
380#define DISP_MOUT_PHYCLK_HDMI_PHY_TMDS_CLKO_USER 4
381#define DISP_MOUT_PHYCLK_HDMI_PHY_REF_CLKO_USER 5
382#define DISP_MOUT_HDMI_PHY_PIXEL 6
383#define DISP_MOUT_PHYCLK_HDMI_LINK_O_TMDS_CLKHI_USER 7
384#define DISP_MOUT_PHYCLK_MIPI_DPHY_4L_M_TXBYTE_CLKHS 8
385#define DISP_MOUT_PHYCLK_DPTX_PHY_O_REF_CLK_24M_USER 9
386#define DISP_MOUT_PHYCLK_DPTX_PHY_CLK_DIV2_USER 10
387#define DISP_MOUT_PHYCLK_DPTX_PHY_CH3_TXD_CLK_USER 11
388#define DISP_MOUT_PHYCLK_DPTX_PHY_CH2_TXD_CLK_USER 12
389#define DISP_MOUT_PHYCLK_DPTX_PHY_CH1_TXD_CLK_USER 13
390#define DISP_MOUT_PHYCLK_DPTX_PHY_CH0_TXD_CLK_USER 14
391#define DISP_MOUT_ACLK_DISP_222_USER 15
392#define DISP_MOUT_SCLK_DISP_PIXEL_USER 16
393#define DISP_MOUT_ACLK_DISP_333_USER 17
394#define DISP_DOUT_SCLK_HDMI_PHY_PIXEL_CLKI 18
395#define DISP_DOUT_SCLK_FIMD1_EXTCLKPLL 19
396#define DISP_DOUT_PCLK_DISP_111 20
397#define DISP_CLK_SMMU_TV 21
398#define DISP_CLK_SMMU_FIMD1M1 22
399#define DISP_CLK_SMMU_FIMD1M0 23
400#define DISP_CLK_PIXEL_MIXER 24
401#define DISP_CLK_PIXEL_DISP 25
402#define DISP_CLK_MIXER 26
403#define DISP_CLK_MIPIPHY 27
404#define DISP_CLK_HDMIPHY 28
405#define DISP_CLK_HDMI 29
406#define DISP_CLK_FIMD1 30
407#define DISP_CLK_DSIM1 31
408#define DISP_CLK_DPPHY 32
409#define DISP_CLK_DP 33
410#define DISP_SCLK_PIXEL 34
411#define DISP_MOUT_HDMI_PHY_PIXEL_USER 35
412#define DISP_NR_CLK 36
413
414
415/* List Of Clocks For CMU_G2D */
416
417#define G2D_MOUT_ACLK_G2D_333_USER 1
418#define G2D_DOUT_PCLK_G2D_83 2
419#define G2D_CLK_SMMU3_JPEG 3
420#define G2D_CLK_MDMA 4
421#define G2D_CLK_JPEG 5
422#define G2D_CLK_G2D 6
423#define G2D_CLK_SSS 7
424#define G2D_CLK_SLIM_SSS 8
425#define G2D_CLK_SMMU_SLIM_SSS 9
426#define G2D_CLK_SMMU_SSS 10
427#define G2D_CLK_SMMU_MDMA 11
428#define G2D_CLK_SMMU3_G2D 12
429#define G2D_NR_CLK 13
430
431
432/* List Of Clocks For CMU_ISP */
433
434#define ISP_MOUT_ISP_400_USER 1
435#define ISP_MOUT_ISP_266_USER 2
436#define ISP_DOUT_SCLK_MPWM 3
437#define ISP_DOUT_CA5_PCLKDBG 4
438#define ISP_DOUT_CA5_ATCLKIN 5
439#define ISP_DOUT_PCLK_ISP_133 6
440#define ISP_DOUT_PCLK_ISP_66 7
441#define ISP_CLK_GIC 8
442#define ISP_CLK_WDT 9
443#define ISP_CLK_UART 10
444#define ISP_CLK_SPI1 11
445#define ISP_CLK_SPI0 12
446#define ISP_CLK_SMMU_SCALERP 13
447#define ISP_CLK_SMMU_SCALERC 14
448#define ISP_CLK_SMMU_ISPCX 15
449#define ISP_CLK_SMMU_ISP 16
450#define ISP_CLK_SMMU_FD 17
451#define ISP_CLK_SMMU_DRC 18
452#define ISP_CLK_PWM 19
453#define ISP_CLK_MTCADC 20
454#define ISP_CLK_MPWM 21
455#define ISP_CLK_MCUCTL 22
456#define ISP_CLK_I2C1 23
457#define ISP_CLK_I2C0 24
458#define ISP_CLK_FIMC_SCALERP 25
459#define ISP_CLK_FIMC_SCALERC 26
460#define ISP_CLK_FIMC 27
461#define ISP_CLK_FIMC_FD 28
462#define ISP_CLK_FIMC_DRC 29
463#define ISP_CLK_CA5 30
464#define ISP_SCLK_SPI0_EXT 31
465#define ISP_SCLK_SPI1_EXT 32
466#define ISP_SCLK_UART_EXT 33
467#define ISP_NR_CLK 34
468
469#endif
diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h
index 5eefd8813f02..97dcb89d37d3 100644
--- a/include/dt-bindings/clock/exynos5420.h
+++ b/include/dt-bindings/clock/exynos5420.h
@@ -58,6 +58,9 @@
58#define CLK_SCLK_GSCL_WA 156 58#define CLK_SCLK_GSCL_WA 156
59#define CLK_SCLK_GSCL_WB 157 59#define CLK_SCLK_GSCL_WB 157
60#define CLK_SCLK_HDMIPHY 158 60#define CLK_SCLK_HDMIPHY 158
61#define CLK_MAU_EPLL 159
62#define CLK_SCLK_HSIC_12M 160
63#define CLK_SCLK_MPHY_IXTAL24 161
61 64
62/* gate clocks */ 65/* gate clocks */
63#define CLK_ACLK66_PERIC 256 66#define CLK_ACLK66_PERIC 256
@@ -69,10 +72,10 @@
69#define CLK_I2C1 262 72#define CLK_I2C1 262
70#define CLK_I2C2 263 73#define CLK_I2C2 263
71#define CLK_I2C3 264 74#define CLK_I2C3 264
72#define CLK_I2C4 265 75#define CLK_USI0 265
73#define CLK_I2C5 266 76#define CLK_USI1 266
74#define CLK_I2C6 267 77#define CLK_USI2 267
75#define CLK_I2C7 268 78#define CLK_USI3 268
76#define CLK_I2C_HDMI 269 79#define CLK_I2C_HDMI 269
77#define CLK_TSADC 270 80#define CLK_TSADC 270
78#define CLK_SPI0 271 81#define CLK_SPI0 271
@@ -85,9 +88,9 @@
85#define CLK_PCM2 278 88#define CLK_PCM2 278
86#define CLK_PWM 279 89#define CLK_PWM 279
87#define CLK_SPDIF 280 90#define CLK_SPDIF 280
88#define CLK_I2C8 281 91#define CLK_USI4 281
89#define CLK_I2C9 282 92#define CLK_USI5 282
90#define CLK_I2C10 283 93#define CLK_USI6 283
91#define CLK_ACLK66_PSGEN 300 94#define CLK_ACLK66_PSGEN 300
92#define CLK_CHIPID 301 95#define CLK_CHIPID 301
93#define CLK_SYSREG 302 96#define CLK_SYSREG 302
@@ -140,7 +143,8 @@
140#define CLK_HDMI 413 143#define CLK_HDMI 413
141#define CLK_ACLK300_DISP1 420 144#define CLK_ACLK300_DISP1 420
142#define CLK_FIMD1 421 145#define CLK_FIMD1 421
143#define CLK_SMMU_FIMD1 422 146#define CLK_SMMU_FIMD1M0 422
147#define CLK_SMMU_FIMD1M1 423
144#define CLK_ACLK166 430 148#define CLK_ACLK166 430
145#define CLK_MIXER 431 149#define CLK_MIXER 431
146#define CLK_ACLK266 440 150#define CLK_ACLK266 440
@@ -152,6 +156,7 @@
152#define CLK_JPEG 451 156#define CLK_JPEG 451
153#define CLK_JPEG2 452 157#define CLK_JPEG2 452
154#define CLK_SMMU_JPEG 453 158#define CLK_SMMU_JPEG 453
159#define CLK_SMMU_JPEG2 454
155#define CLK_ACLK300_GSCL 460 160#define CLK_ACLK300_GSCL 460
156#define CLK_SMMU_GSCL0 461 161#define CLK_SMMU_GSCL0 461
157#define CLK_SMMU_GSCL1 462 162#define CLK_SMMU_GSCL1 462
@@ -159,7 +164,7 @@
159#define CLK_GSCL_WB 464 164#define CLK_GSCL_WB 464
160#define CLK_GSCL0 465 165#define CLK_GSCL0 465
161#define CLK_GSCL1 466 166#define CLK_GSCL1 466
162#define CLK_CLK_3AA 467 167#define CLK_FIMC_3AA 467
163#define CLK_ACLK266_G2D 470 168#define CLK_ACLK266_G2D 470
164#define CLK_SSS 471 169#define CLK_SSS 471
165#define CLK_SLIM_SSS 472 170#define CLK_SLIM_SSS 472
@@ -172,12 +177,32 @@
172#define CLK_SMMU_FIMCL1 493 177#define CLK_SMMU_FIMCL1 493
173#define CLK_SMMU_FIMCL3 494 178#define CLK_SMMU_FIMCL3 494
174#define CLK_FIMC_LITE3 495 179#define CLK_FIMC_LITE3 495
180#define CLK_FIMC_LITE0 496
181#define CLK_FIMC_LITE1 497
175#define CLK_ACLK_G3D 500 182#define CLK_ACLK_G3D 500
176#define CLK_G3D 501 183#define CLK_G3D 501
177#define CLK_SMMU_MIXER 502 184#define CLK_SMMU_MIXER 502
185#define CLK_SMMU_G2D 503
186#define CLK_SMMU_MDMA0 504
187#define CLK_MC 505
188#define CLK_TOP_RTC 506
189#define CLK_SCLK_UART_ISP 510
190#define CLK_SCLK_SPI0_ISP 511
191#define CLK_SCLK_SPI1_ISP 512
192#define CLK_SCLK_PWM_ISP 513
193#define CLK_SCLK_ISP_SENSOR0 514
194#define CLK_SCLK_ISP_SENSOR1 515
195#define CLK_SCLK_ISP_SENSOR2 516
196#define CLK_ACLK432_SCALER 517
197#define CLK_ACLK432_CAM 518
198#define CLK_ACLK_FL1550_CAM 519
199#define CLK_ACLK550_CAM 520
178 200
179/* mux clocks */ 201/* mux clocks */
180#define CLK_MOUT_HDMI 640 202#define CLK_MOUT_HDMI 640
203#define CLK_MOUT_G3D 641
204#define CLK_MOUT_VPLL 642
205#define CLK_MOUT_MAUDIO0 643
181 206
182/* divider clocks */ 207/* divider clocks */
183#define CLK_DOUT_PIXEL 768 208#define CLK_DOUT_PIXEL 768
generated by cgit v1.2.2 (git 2.25.0) at 2025-10-01 10:46:52 -0400