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-rw-r--r--drivers/net/mv643xx_eth.c22
-rw-r--r--drivers/net/mv643xx_eth.h220
2 files changed, 117 insertions, 125 deletions
diff --git a/drivers/net/mv643xx_eth.c b/drivers/net/mv643xx_eth.c
index 98dd90500422..98b30e52f07d 100644
--- a/drivers/net/mv643xx_eth.c
+++ b/drivers/net/mv643xx_eth.c
@@ -78,26 +78,19 @@ static const struct ethtool_ops mv643xx_ethtool_ops;
78static char mv643xx_driver_name[] = "mv643xx_eth"; 78static char mv643xx_driver_name[] = "mv643xx_eth";
79static char mv643xx_driver_version[] = "1.0"; 79static char mv643xx_driver_version[] = "1.0";
80 80
81static void __iomem *mv643xx_eth_shared_base; 81static void __iomem *mv643xx_eth_base;
82 82
83/* used to protect MV643XX_ETH_SMI_REG, which is shared across ports */ 83/* used to protect MV643XX_ETH_SMI_REG, which is shared across ports */
84static DEFINE_SPINLOCK(mv643xx_eth_phy_lock); 84static DEFINE_SPINLOCK(mv643xx_eth_phy_lock);
85 85
86static inline u32 mv_read(int offset) 86static inline u32 mv_read(int offset)
87{ 87{
88 void __iomem *reg_base; 88 return readl(mv643xx_eth_base + offset);
89
90 reg_base = mv643xx_eth_shared_base - MV643XX_ETH_SHARED_REGS;
91
92 return readl(reg_base + offset);
93} 89}
94 90
95static inline void mv_write(int offset, u32 data) 91static inline void mv_write(int offset, u32 data)
96{ 92{
97 void __iomem *reg_base; 93 writel(data, mv643xx_eth_base + offset);
98
99 reg_base = mv643xx_eth_shared_base - MV643XX_ETH_SHARED_REGS;
100 writel(data, reg_base + offset);
101} 94}
102 95
103/* 96/*
@@ -1470,9 +1463,8 @@ static int mv643xx_eth_shared_probe(struct platform_device *pdev)
1470 if (res == NULL) 1463 if (res == NULL)
1471 return -ENODEV; 1464 return -ENODEV;
1472 1465
1473 mv643xx_eth_shared_base = ioremap(res->start, 1466 mv643xx_eth_base = ioremap(res->start, res->end - res->start + 1);
1474 MV643XX_ETH_SHARED_REGS_SIZE); 1467 if (mv643xx_eth_base == NULL)
1475 if (mv643xx_eth_shared_base == NULL)
1476 return -ENOMEM; 1468 return -ENOMEM;
1477 1469
1478 return 0; 1470 return 0;
@@ -1481,8 +1473,8 @@ static int mv643xx_eth_shared_probe(struct platform_device *pdev)
1481 1473
1482static int mv643xx_eth_shared_remove(struct platform_device *pdev) 1474static int mv643xx_eth_shared_remove(struct platform_device *pdev)
1483{ 1475{
1484 iounmap(mv643xx_eth_shared_base); 1476 iounmap(mv643xx_eth_base);
1485 mv643xx_eth_shared_base = NULL; 1477 mv643xx_eth_base = NULL;
1486 1478
1487 return 0; 1479 return 0;
1488} 1480}
diff --git a/drivers/net/mv643xx_eth.h b/drivers/net/mv643xx_eth.h
index d82b48d685c2..180859833e65 100644
--- a/drivers/net/mv643xx_eth.h
+++ b/drivers/net/mv643xx_eth.h
@@ -55,116 +55,116 @@
55/* Ethernet Unit Registers */ 55/* Ethernet Unit Registers */
56/****************************************/ 56/****************************************/
57 57
58#define MV643XX_ETH_PHY_ADDR_REG 0x2000 58#define MV643XX_ETH_PHY_ADDR_REG 0x0000
59#define MV643XX_ETH_SMI_REG 0x2004 59#define MV643XX_ETH_SMI_REG 0x0004
60#define MV643XX_ETH_UNIT_DEFAULT_ADDR_REG 0x2008 60#define MV643XX_ETH_UNIT_DEFAULT_ADDR_REG 0x0008
61#define MV643XX_ETH_UNIT_DEFAULTID_REG 0x200c 61#define MV643XX_ETH_UNIT_DEFAULTID_REG 0x000c
62#define MV643XX_ETH_UNIT_INTERRUPT_CAUSE_REG 0x2080 62#define MV643XX_ETH_UNIT_INTERRUPT_CAUSE_REG 0x0080
63#define MV643XX_ETH_UNIT_INTERRUPT_MASK_REG 0x2084 63#define MV643XX_ETH_UNIT_INTERRUPT_MASK_REG 0x0084
64#define MV643XX_ETH_UNIT_INTERNAL_USE_REG 0x24fc 64#define MV643XX_ETH_UNIT_INTERNAL_USE_REG 0x04fc
65#define MV643XX_ETH_UNIT_ERROR_ADDR_REG 0x2094 65#define MV643XX_ETH_UNIT_ERROR_ADDR_REG 0x0094
66#define MV643XX_ETH_BAR_0 0x2200 66#define MV643XX_ETH_BAR_0 0x0200
67#define MV643XX_ETH_BAR_1 0x2208 67#define MV643XX_ETH_BAR_1 0x0208
68#define MV643XX_ETH_BAR_2 0x2210 68#define MV643XX_ETH_BAR_2 0x0210
69#define MV643XX_ETH_BAR_3 0x2218 69#define MV643XX_ETH_BAR_3 0x0218
70#define MV643XX_ETH_BAR_4 0x2220 70#define MV643XX_ETH_BAR_4 0x0220
71#define MV643XX_ETH_BAR_5 0x2228 71#define MV643XX_ETH_BAR_5 0x0228
72#define MV643XX_ETH_SIZE_REG_0 0x2204 72#define MV643XX_ETH_SIZE_REG_0 0x0204
73#define MV643XX_ETH_SIZE_REG_1 0x220c 73#define MV643XX_ETH_SIZE_REG_1 0x020c
74#define MV643XX_ETH_SIZE_REG_2 0x2214 74#define MV643XX_ETH_SIZE_REG_2 0x0214
75#define MV643XX_ETH_SIZE_REG_3 0x221c 75#define MV643XX_ETH_SIZE_REG_3 0x021c
76#define MV643XX_ETH_SIZE_REG_4 0x2224 76#define MV643XX_ETH_SIZE_REG_4 0x0224
77#define MV643XX_ETH_SIZE_REG_5 0x222c 77#define MV643XX_ETH_SIZE_REG_5 0x022c
78#define MV643XX_ETH_HEADERS_RETARGET_BASE_REG 0x2230 78#define MV643XX_ETH_HEADERS_RETARGET_BASE_REG 0x0230
79#define MV643XX_ETH_HEADERS_RETARGET_CONTROL_REG 0x2234 79#define MV643XX_ETH_HEADERS_RETARGET_CONTROL_REG 0x0234
80#define MV643XX_ETH_HIGH_ADDR_REMAP_REG_0 0x2280 80#define MV643XX_ETH_HIGH_ADDR_REMAP_REG_0 0x0280
81#define MV643XX_ETH_HIGH_ADDR_REMAP_REG_1 0x2284 81#define MV643XX_ETH_HIGH_ADDR_REMAP_REG_1 0x0284
82#define MV643XX_ETH_HIGH_ADDR_REMAP_REG_2 0x2288 82#define MV643XX_ETH_HIGH_ADDR_REMAP_REG_2 0x0288
83#define MV643XX_ETH_HIGH_ADDR_REMAP_REG_3 0x228c 83#define MV643XX_ETH_HIGH_ADDR_REMAP_REG_3 0x028c
84#define MV643XX_ETH_BASE_ADDR_ENABLE_REG 0x2290 84#define MV643XX_ETH_BASE_ADDR_ENABLE_REG 0x0290
85#define MV643XX_ETH_ACCESS_PROTECTION_REG(port) (0x2294 + (port<<2)) 85#define MV643XX_ETH_ACCESS_PROTECTION_REG(port) (0x0294 + (port<<2))
86#define MV643XX_ETH_MIB_COUNTERS_BASE(port) (0x3000 + (port<<7)) 86#define MV643XX_ETH_MIB_COUNTERS_BASE(port) (0x1000 + (port<<7))
87#define MV643XX_ETH_PORT_CONFIG_REG(port) (0x2400 + (port<<10)) 87#define MV643XX_ETH_PORT_CONFIG_REG(port) (0x0400 + (port<<10))
88#define MV643XX_ETH_PORT_CONFIG_EXTEND_REG(port) (0x2404 + (port<<10)) 88#define MV643XX_ETH_PORT_CONFIG_EXTEND_REG(port) (0x0404 + (port<<10))
89#define MV643XX_ETH_MII_SERIAL_PARAMETRS_REG(port) (0x2408 + (port<<10)) 89#define MV643XX_ETH_MII_SERIAL_PARAMETRS_REG(port) (0x0408 + (port<<10))
90#define MV643XX_ETH_GMII_SERIAL_PARAMETRS_REG(port) (0x240c + (port<<10)) 90#define MV643XX_ETH_GMII_SERIAL_PARAMETRS_REG(port) (0x040c + (port<<10))
91#define MV643XX_ETH_VLAN_ETHERTYPE_REG(port) (0x2410 + (port<<10)) 91#define MV643XX_ETH_VLAN_ETHERTYPE_REG(port) (0x0410 + (port<<10))
92#define MV643XX_ETH_MAC_ADDR_LOW(port) (0x2414 + (port<<10)) 92#define MV643XX_ETH_MAC_ADDR_LOW(port) (0x0414 + (port<<10))
93#define MV643XX_ETH_MAC_ADDR_HIGH(port) (0x2418 + (port<<10)) 93#define MV643XX_ETH_MAC_ADDR_HIGH(port) (0x0418 + (port<<10))
94#define MV643XX_ETH_SDMA_CONFIG_REG(port) (0x241c + (port<<10)) 94#define MV643XX_ETH_SDMA_CONFIG_REG(port) (0x041c + (port<<10))
95#define MV643XX_ETH_DSCP_0(port) (0x2420 + (port<<10)) 95#define MV643XX_ETH_DSCP_0(port) (0x0420 + (port<<10))
96#define MV643XX_ETH_DSCP_1(port) (0x2424 + (port<<10)) 96#define MV643XX_ETH_DSCP_1(port) (0x0424 + (port<<10))
97#define MV643XX_ETH_DSCP_2(port) (0x2428 + (port<<10)) 97#define MV643XX_ETH_DSCP_2(port) (0x0428 + (port<<10))
98#define MV643XX_ETH_DSCP_3(port) (0x242c + (port<<10)) 98#define MV643XX_ETH_DSCP_3(port) (0x042c + (port<<10))
99#define MV643XX_ETH_DSCP_4(port) (0x2430 + (port<<10)) 99#define MV643XX_ETH_DSCP_4(port) (0x0430 + (port<<10))
100#define MV643XX_ETH_DSCP_5(port) (0x2434 + (port<<10)) 100#define MV643XX_ETH_DSCP_5(port) (0x0434 + (port<<10))
101#define MV643XX_ETH_DSCP_6(port) (0x2438 + (port<<10)) 101#define MV643XX_ETH_DSCP_6(port) (0x0438 + (port<<10))
102#define MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port) (0x243c + (port<<10)) 102#define MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port) (0x043c + (port<<10))
103#define MV643XX_ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port) (0x2440 + (port<<10)) 103#define MV643XX_ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port) (0x0440 + (port<<10))
104#define MV643XX_ETH_PORT_STATUS_REG(port) (0x2444 + (port<<10)) 104#define MV643XX_ETH_PORT_STATUS_REG(port) (0x0444 + (port<<10))
105#define MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port) (0x2448 + (port<<10)) 105#define MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port) (0x0448 + (port<<10))
106#define MV643XX_ETH_TX_QUEUE_FIXED_PRIORITY(port) (0x244c + (port<<10)) 106#define MV643XX_ETH_TX_QUEUE_FIXED_PRIORITY(port) (0x044c + (port<<10))
107#define MV643XX_ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port) (0x2450 + (port<<10)) 107#define MV643XX_ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port) (0x0450 + (port<<10))
108#define MV643XX_ETH_MAXIMUM_TRANSMIT_UNIT(port) (0x2458 + (port<<10)) 108#define MV643XX_ETH_MAXIMUM_TRANSMIT_UNIT(port) (0x0458 + (port<<10))
109#define MV643XX_ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port) (0x245c + (port<<10)) 109#define MV643XX_ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port) (0x045c + (port<<10))
110#define MV643XX_ETH_INTERRUPT_CAUSE_REG(port) (0x2460 + (port<<10)) 110#define MV643XX_ETH_INTERRUPT_CAUSE_REG(port) (0x0460 + (port<<10))
111#define MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port) (0x2464 + (port<<10)) 111#define MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port) (0x0464 + (port<<10))
112#define MV643XX_ETH_INTERRUPT_MASK_REG(port) (0x2468 + (port<<10)) 112#define MV643XX_ETH_INTERRUPT_MASK_REG(port) (0x0468 + (port<<10))
113#define MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port) (0x246c + (port<<10)) 113#define MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port) (0x046c + (port<<10))
114#define MV643XX_ETH_RX_FIFO_URGENT_THRESHOLD_REG(port) (0x2470 + (port<<10)) 114#define MV643XX_ETH_RX_FIFO_URGENT_THRESHOLD_REG(port) (0x0470 + (port<<10))
115#define MV643XX_ETH_TX_FIFO_URGENT_THRESHOLD_REG(port) (0x2474 + (port<<10)) 115#define MV643XX_ETH_TX_FIFO_URGENT_THRESHOLD_REG(port) (0x0474 + (port<<10))
116#define MV643XX_ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (0x247c + (port<<10)) 116#define MV643XX_ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (0x047c + (port<<10))
117#define MV643XX_ETH_RX_DISCARDED_FRAMES_COUNTER(port) (0x2484 + (port<<10)) 117#define MV643XX_ETH_RX_DISCARDED_FRAMES_COUNTER(port) (0x0484 + (port<<10))
118#define MV643XX_ETH_PORT_DEBUG_0_REG(port) (0x248c + (port<<10)) 118#define MV643XX_ETH_PORT_DEBUG_0_REG(port) (0x048c + (port<<10))
119#define MV643XX_ETH_PORT_DEBUG_1_REG(port) (0x2490 + (port<<10)) 119#define MV643XX_ETH_PORT_DEBUG_1_REG(port) (0x0490 + (port<<10))
120#define MV643XX_ETH_PORT_INTERNAL_ADDR_ERROR_REG(port) (0x2494 + (port<<10)) 120#define MV643XX_ETH_PORT_INTERNAL_ADDR_ERROR_REG(port) (0x0494 + (port<<10))
121#define MV643XX_ETH_INTERNAL_USE_REG(port) (0x24fc + (port<<10)) 121#define MV643XX_ETH_INTERNAL_USE_REG(port) (0x04fc + (port<<10))
122#define MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port) (0x2680 + (port<<10)) 122#define MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port) (0x0680 + (port<<10))
123#define MV643XX_ETH_CURRENT_SERVED_TX_DESC_PTR(port) (0x2684 + (port<<10)) 123#define MV643XX_ETH_CURRENT_SERVED_TX_DESC_PTR(port) (0x0684 + (port<<10))
124#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port) (0x260c + (port<<10)) 124#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port) (0x060c + (port<<10))
125#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port) (0x261c + (port<<10)) 125#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port) (0x061c + (port<<10))
126#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port) (0x262c + (port<<10)) 126#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port) (0x062c + (port<<10))
127#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port) (0x263c + (port<<10)) 127#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port) (0x063c + (port<<10))
128#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port) (0x264c + (port<<10)) 128#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port) (0x064c + (port<<10))
129#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port) (0x265c + (port<<10)) 129#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port) (0x065c + (port<<10))
130#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port) (0x266c + (port<<10)) 130#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port) (0x066c + (port<<10))
131#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port) (0x267c + (port<<10)) 131#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port) (0x067c + (port<<10))
132#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port) (0x26c0 + (port<<10)) 132#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port) (0x06c0 + (port<<10))
133#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port) (0x26c4 + (port<<10)) 133#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port) (0x06c4 + (port<<10))
134#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port) (0x26c8 + (port<<10)) 134#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port) (0x06c8 + (port<<10))
135#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port) (0x26cc + (port<<10)) 135#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port) (0x06cc + (port<<10))
136#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port) (0x26d0 + (port<<10)) 136#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port) (0x06d0 + (port<<10))
137#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port) (0x26d4 + (port<<10)) 137#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port) (0x06d4 + (port<<10))
138#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port) (0x26d8 + (port<<10)) 138#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port) (0x06d8 + (port<<10))
139#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port) (0x26dc + (port<<10)) 139#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port) (0x06dc + (port<<10))
140#define MV643XX_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port) (0x2700 + (port<<10)) 140#define MV643XX_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port) (0x0700 + (port<<10))
141#define MV643XX_ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port) (0x2710 + (port<<10)) 141#define MV643XX_ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port) (0x0710 + (port<<10))
142#define MV643XX_ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port) (0x2720 + (port<<10)) 142#define MV643XX_ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port) (0x0720 + (port<<10))
143#define MV643XX_ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port) (0x2730 + (port<<10)) 143#define MV643XX_ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port) (0x0730 + (port<<10))
144#define MV643XX_ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port) (0x2740 + (port<<10)) 144#define MV643XX_ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port) (0x0740 + (port<<10))
145#define MV643XX_ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port) (0x2750 + (port<<10)) 145#define MV643XX_ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port) (0x0750 + (port<<10))
146#define MV643XX_ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port) (0x2760 + (port<<10)) 146#define MV643XX_ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port) (0x0760 + (port<<10))
147#define MV643XX_ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port) (0x2770 + (port<<10)) 147#define MV643XX_ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port) (0x0770 + (port<<10))
148#define MV643XX_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port) (0x2704 + (port<<10)) 148#define MV643XX_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port) (0x0704 + (port<<10))
149#define MV643XX_ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port) (0x2714 + (port<<10)) 149#define MV643XX_ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port) (0x0714 + (port<<10))
150#define MV643XX_ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port) (0x2724 + (port<<10)) 150#define MV643XX_ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port) (0x0724 + (port<<10))
151#define MV643XX_ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port) (0x2734 + (port<<10)) 151#define MV643XX_ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port) (0x0734 + (port<<10))
152#define MV643XX_ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port) (0x2744 + (port<<10)) 152#define MV643XX_ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port) (0x0744 + (port<<10))
153#define MV643XX_ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port) (0x2754 + (port<<10)) 153#define MV643XX_ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port) (0x0754 + (port<<10))
154#define MV643XX_ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port) (0x2764 + (port<<10)) 154#define MV643XX_ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port) (0x0764 + (port<<10))
155#define MV643XX_ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port) (0x2774 + (port<<10)) 155#define MV643XX_ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port) (0x0774 + (port<<10))
156#define MV643XX_ETH_TX_QUEUE_0_ARBITER_CONFIG(port) (0x2708 + (port<<10)) 156#define MV643XX_ETH_TX_QUEUE_0_ARBITER_CONFIG(port) (0x0708 + (port<<10))
157#define MV643XX_ETH_TX_QUEUE_1_ARBITER_CONFIG(port) (0x2718 + (port<<10)) 157#define MV643XX_ETH_TX_QUEUE_1_ARBITER_CONFIG(port) (0x0718 + (port<<10))
158#define MV643XX_ETH_TX_QUEUE_2_ARBITER_CONFIG(port) (0x2728 + (port<<10)) 158#define MV643XX_ETH_TX_QUEUE_2_ARBITER_CONFIG(port) (0x0728 + (port<<10))
159#define MV643XX_ETH_TX_QUEUE_3_ARBITER_CONFIG(port) (0x2738 + (port<<10)) 159#define MV643XX_ETH_TX_QUEUE_3_ARBITER_CONFIG(port) (0x0738 + (port<<10))
160#define MV643XX_ETH_TX_QUEUE_4_ARBITER_CONFIG(port) (0x2748 + (port<<10)) 160#define MV643XX_ETH_TX_QUEUE_4_ARBITER_CONFIG(port) (0x0748 + (port<<10))
161#define MV643XX_ETH_TX_QUEUE_5_ARBITER_CONFIG(port) (0x2758 + (port<<10)) 161#define MV643XX_ETH_TX_QUEUE_5_ARBITER_CONFIG(port) (0x0758 + (port<<10))
162#define MV643XX_ETH_TX_QUEUE_6_ARBITER_CONFIG(port) (0x2768 + (port<<10)) 162#define MV643XX_ETH_TX_QUEUE_6_ARBITER_CONFIG(port) (0x0768 + (port<<10))
163#define MV643XX_ETH_TX_QUEUE_7_ARBITER_CONFIG(port) (0x2778 + (port<<10)) 163#define MV643XX_ETH_TX_QUEUE_7_ARBITER_CONFIG(port) (0x0778 + (port<<10))
164#define MV643XX_ETH_PORT_TX_TOKEN_BUCKET_COUNT(port) (0x2780 + (port<<10)) 164#define MV643XX_ETH_PORT_TX_TOKEN_BUCKET_COUNT(port) (0x0780 + (port<<10))
165#define MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port) (0x3400 + (port<<10)) 165#define MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port) (0x1400 + (port<<10))
166#define MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port) (0x3500 + (port<<10)) 166#define MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port) (0x1500 + (port<<10))
167#define MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE(port) (0x3600 + (port<<10)) 167#define MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE(port) (0x1600 + (port<<10))
168 168
169/* These macros describe Ethernet Port configuration reg (Px_cR) bits */ 169/* These macros describe Ethernet Port configuration reg (Px_cR) bits */
170#define MV643XX_ETH_UNICAST_NORMAL_MODE 0 170#define MV643XX_ETH_UNICAST_NORMAL_MODE 0
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-28 07:10:31 -0500