diff options
-rw-r--r-- | arch/microblaze/include/asm/pvr.h | 30 | ||||
-rw-r--r-- | arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c | 11 |
2 files changed, 29 insertions, 12 deletions
diff --git a/arch/microblaze/include/asm/pvr.h b/arch/microblaze/include/asm/pvr.h index 66f1b30dd097..e38abc7714b6 100644 --- a/arch/microblaze/include/asm/pvr.h +++ b/arch/microblaze/include/asm/pvr.h | |||
@@ -76,20 +76,23 @@ struct pvr_s { | |||
76 | #define PVR3_FSL_LINKS_MASK 0x00000380 | 76 | #define PVR3_FSL_LINKS_MASK 0x00000380 |
77 | 77 | ||
78 | /* ICache config PVR masks */ | 78 | /* ICache config PVR masks */ |
79 | #define PVR4_USE_ICACHE_MASK 0x80000000 | 79 | #define PVR4_USE_ICACHE_MASK 0x80000000 /* ICU */ |
80 | #define PVR4_ICACHE_ADDR_TAG_BITS_MASK 0x7C000000 | 80 | #define PVR4_ICACHE_ADDR_TAG_BITS_MASK 0x7C000000 /* ICTS */ |
81 | #define PVR4_ICACHE_USE_FSL_MASK 0x02000000 | 81 | #define PVR4_ICACHE_ALLOW_WR_MASK 0x01000000 /* ICW */ |
82 | #define PVR4_ICACHE_ALLOW_WR_MASK 0x01000000 | 82 | #define PVR4_ICACHE_LINE_LEN_MASK 0x00E00000 /* ICLL */ |
83 | #define PVR4_ICACHE_LINE_LEN_MASK 0x00E00000 | 83 | #define PVR4_ICACHE_BYTE_SIZE_MASK 0x001F0000 /* ICBS */ |
84 | #define PVR4_ICACHE_BYTE_SIZE_MASK 0x001F0000 | 84 | #define PVR4_ICACHE_ALWAYS_USED 0x00008000 /* IAU */ |
85 | #define PVR4_ICACHE_INTERFACE 0x00002000 /* ICI */ | ||
85 | 86 | ||
86 | /* DCache config PVR masks */ | 87 | /* DCache config PVR masks */ |
87 | #define PVR5_USE_DCACHE_MASK 0x80000000 | 88 | #define PVR5_USE_DCACHE_MASK 0x80000000 /* DCU */ |
88 | #define PVR5_DCACHE_ADDR_TAG_BITS_MASK 0x7C000000 | 89 | #define PVR5_DCACHE_ADDR_TAG_BITS_MASK 0x7C000000 /* DCTS */ |
89 | #define PVR5_DCACHE_USE_FSL_MASK 0x02000000 | 90 | #define PVR5_DCACHE_ALLOW_WR_MASK 0x01000000 /* DCW */ |
90 | #define PVR5_DCACHE_ALLOW_WR_MASK 0x01000000 | 91 | #define PVR5_DCACHE_LINE_LEN_MASK 0x00E00000 /* DCLL */ |
91 | #define PVR5_DCACHE_LINE_LEN_MASK 0x00E00000 | 92 | #define PVR5_DCACHE_BYTE_SIZE_MASK 0x001F0000 /* DCBS */ |
92 | #define PVR5_DCACHE_BYTE_SIZE_MASK 0x001F0000 | 93 | #define PVR5_DCACHE_ALWAYS_USED 0x00008000 /* DAU */ |
94 | #define PVR5_DCACHE_USE_WRITEBACK 0x00004000 /* DWB */ | ||
95 | #define PVR5_DCACHE_INTERFACE 0x00002000 /* DCI */ | ||
93 | 96 | ||
94 | /* ICache base address PVR mask */ | 97 | /* ICache base address PVR mask */ |
95 | #define PVR6_ICACHE_BASEADDR_MASK 0xFFFFFFFF | 98 | #define PVR6_ICACHE_BASEADDR_MASK 0xFFFFFFFF |
@@ -178,11 +181,14 @@ struct pvr_s { | |||
178 | ((pvr.pvr[5] & PVR5_DCACHE_ADDR_TAG_BITS_MASK) >> 26) | 181 | ((pvr.pvr[5] & PVR5_DCACHE_ADDR_TAG_BITS_MASK) >> 26) |
179 | #define PVR_DCACHE_USE_FSL(pvr) (pvr.pvr[5] & PVR5_DCACHE_USE_FSL_MASK) | 182 | #define PVR_DCACHE_USE_FSL(pvr) (pvr.pvr[5] & PVR5_DCACHE_USE_FSL_MASK) |
180 | #define PVR_DCACHE_ALLOW_WR(pvr) (pvr.pvr[5] & PVR5_DCACHE_ALLOW_WR_MASK) | 183 | #define PVR_DCACHE_ALLOW_WR(pvr) (pvr.pvr[5] & PVR5_DCACHE_ALLOW_WR_MASK) |
184 | /* FIXME two shifts on one line needs any comment */ | ||
181 | #define PVR_DCACHE_LINE_LEN(pvr) \ | 185 | #define PVR_DCACHE_LINE_LEN(pvr) \ |
182 | (1 << ((pvr.pvr[5] & PVR5_DCACHE_LINE_LEN_MASK) >> 21)) | 186 | (1 << ((pvr.pvr[5] & PVR5_DCACHE_LINE_LEN_MASK) >> 21)) |
183 | #define PVR_DCACHE_BYTE_SIZE(pvr) \ | 187 | #define PVR_DCACHE_BYTE_SIZE(pvr) \ |
184 | (1 << ((pvr.pvr[5] & PVR5_DCACHE_BYTE_SIZE_MASK) >> 16)) | 188 | (1 << ((pvr.pvr[5] & PVR5_DCACHE_BYTE_SIZE_MASK) >> 16)) |
185 | 189 | ||
190 | #define PVR_DCACHE_USE_WRITEBACK(pvr) \ | ||
191 | ((pvr.pvr[5] & PVR5_DCACHE_USE_WRITEBACK) >> 14) | ||
186 | 192 | ||
187 | #define PVR_ICACHE_BASEADDR(pvr) (pvr.pvr[6] & PVR6_ICACHE_BASEADDR_MASK) | 193 | #define PVR_ICACHE_BASEADDR(pvr) (pvr.pvr[6] & PVR6_ICACHE_BASEADDR_MASK) |
188 | #define PVR_ICACHE_HIGHADDR(pvr) (pvr.pvr[7] & PVR7_ICACHE_HIGHADDR_MASK) | 194 | #define PVR_ICACHE_HIGHADDR(pvr) (pvr.pvr[7] & PVR7_ICACHE_HIGHADDR_MASK) |
diff --git a/arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c b/arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c index c5acf2b56eed..f72dbd66c844 100644 --- a/arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c +++ b/arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c | |||
@@ -21,8 +21,14 @@ | |||
21 | */ | 21 | */ |
22 | 22 | ||
23 | #define CI(c, p) { ci->c = PVR_##p(pvr); } | 23 | #define CI(c, p) { ci->c = PVR_##p(pvr); } |
24 | |||
25 | #if defined(CONFIG_EARLY_PRINTK) && defined(CONFIG_SERIAL_UARTLITE_CONSOLE) | ||
24 | #define err_printk(x) \ | 26 | #define err_printk(x) \ |
25 | early_printk("ERROR: Microblaze " x "-different for PVR and DTS\n"); | 27 | early_printk("ERROR: Microblaze " x "-different for PVR and DTS\n"); |
28 | #else | ||
29 | #define err_printk(x) \ | ||
30 | printk(KERN_INFO "ERROR: Microblaze " x "-different for PVR and DTS\n"); | ||
31 | #endif | ||
26 | 32 | ||
27 | void set_cpuinfo_pvr_full(struct cpuinfo *ci, struct device_node *cpu) | 33 | void set_cpuinfo_pvr_full(struct cpuinfo *ci, struct device_node *cpu) |
28 | { | 34 | { |
@@ -83,6 +89,11 @@ void set_cpuinfo_pvr_full(struct cpuinfo *ci, struct device_node *cpu) | |||
83 | CI(dcache_base, DCACHE_BASEADDR); | 89 | CI(dcache_base, DCACHE_BASEADDR); |
84 | CI(dcache_high, DCACHE_HIGHADDR); | 90 | CI(dcache_high, DCACHE_HIGHADDR); |
85 | 91 | ||
92 | temp = PVR_DCACHE_USE_WRITEBACK(pvr); | ||
93 | if (ci->dcache_wb != temp) | ||
94 | err_printk("DCACHE WB"); | ||
95 | ci->dcache_wb = temp; | ||
96 | |||
86 | CI(use_dopb, D_OPB); | 97 | CI(use_dopb, D_OPB); |
87 | CI(use_iopb, I_OPB); | 98 | CI(use_iopb, I_OPB); |
88 | CI(use_dlmb, D_LMB); | 99 | CI(use_dlmb, D_LMB); |