diff options
-rw-r--r-- | Documentation/devicetree/bindings/dma/ste-dma40.txt | 74 |
1 files changed, 72 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/dma/ste-dma40.txt b/Documentation/devicetree/bindings/dma/ste-dma40.txt index 1f5729f10621..95800ab37bb0 100644 --- a/Documentation/devicetree/bindings/dma/ste-dma40.txt +++ b/Documentation/devicetree/bindings/dma/ste-dma40.txt | |||
@@ -35,9 +35,11 @@ Required properties: | |||
35 | 35 | ||
36 | Each dmas request consists of 4 cells: | 36 | Each dmas request consists of 4 cells: |
37 | 1. A phandle pointing to the DMA controller | 37 | 1. A phandle pointing to the DMA controller |
38 | 2. Device Type | 38 | 2. Device signal number, the signal line for single and burst requests |
39 | connected from the device to the DMA40 engine | ||
39 | 3. The DMA request line number (only when 'use fixed channel' is set) | 40 | 3. The DMA request line number (only when 'use fixed channel' is set) |
40 | 4. A 32bit mask specifying; mode, direction and endianness [NB: This list will grow] | 41 | 4. A 32bit mask specifying; mode, direction and endianness |
42 | [NB: This list will grow] | ||
41 | 0x00000001: Mode: | 43 | 0x00000001: Mode: |
42 | Logical channel when unset | 44 | Logical channel when unset |
43 | Physical channel when set | 45 | Physical channel when set |
@@ -54,6 +56,74 @@ Each dmas request consists of 4 cells: | |||
54 | Normal priority when unset | 56 | Normal priority when unset |
55 | High priority when set | 57 | High priority when set |
56 | 58 | ||
59 | Existing signal numbers for the DB8500 ASIC. Unless specified, the signals are | ||
60 | bidirectional, i.e. the same for RX and TX operations: | ||
61 | |||
62 | 0: SPI controller 0 | ||
63 | 1: SD/MMC controller 0 (unused) | ||
64 | 2: SD/MMC controller 1 (unused) | ||
65 | 3: SD/MMC controller 2 (unused) | ||
66 | 4: I2C port 1 | ||
67 | 5: I2C port 3 | ||
68 | 6: I2C port 2 | ||
69 | 7: I2C port 4 | ||
70 | 8: Synchronous Serial Port SSP0 | ||
71 | 9: Synchronous Serial Port SSP1 | ||
72 | 10: Multi-Channel Display Engine MCDE RX | ||
73 | 11: UART port 2 | ||
74 | 12: UART port 1 | ||
75 | 13: UART port 0 | ||
76 | 14: Multirate Serial Port MSP2 | ||
77 | 15: I2C port 0 | ||
78 | 16: USB OTG in/out endpoints 7 & 15 | ||
79 | 17: USB OTG in/out endpoints 6 & 14 | ||
80 | 18: USB OTG in/out endpoints 5 & 13 | ||
81 | 19: USB OTG in/out endpoints 4 & 12 | ||
82 | 20: SLIMbus or HSI channel 0 | ||
83 | 21: SLIMbus or HSI channel 1 | ||
84 | 22: SLIMbus or HSI channel 2 | ||
85 | 23: SLIMbus or HSI channel 3 | ||
86 | 24: Multimedia DSP SXA0 | ||
87 | 25: Multimedia DSP SXA1 | ||
88 | 26: Multimedia DSP SXA2 | ||
89 | 27: Multimedia DSP SXA3 | ||
90 | 28: SD/MM controller 2 | ||
91 | 29: SD/MM controller 0 | ||
92 | 30: MSP port 1 on DB8500 v1, MSP port 3 on DB8500 v2 | ||
93 | 31: MSP port 0 or SLIMbus channel 0 | ||
94 | 32: SD/MM controller 1 | ||
95 | 33: SPI controller 2 | ||
96 | 34: i2c3 RX2 TX2 | ||
97 | 35: SPI controller 1 | ||
98 | 36: USB OTG in/out endpoints 3 & 11 | ||
99 | 37: USB OTG in/out endpoints 2 & 10 | ||
100 | 38: USB OTG in/out endpoints 1 & 9 | ||
101 | 39: USB OTG in/out endpoints 8 | ||
102 | 40: SPI controller 3 | ||
103 | 41: SD/MM controller 3 | ||
104 | 42: SD/MM controller 4 | ||
105 | 43: SD/MM controller 5 | ||
106 | 44: Multimedia DSP SXA4 | ||
107 | 45: Multimedia DSP SXA5 | ||
108 | 46: SLIMbus channel 8 or Multimedia DSP SXA6 | ||
109 | 47: SLIMbus channel 9 or Multimedia DSP SXA7 | ||
110 | 48: Crypto Accelerator 1 | ||
111 | 49: Crypto Accelerator 1 TX or Hash Accelerator 1 TX | ||
112 | 50: Hash Accelerator 1 TX | ||
113 | 51: memcpy TX (to be used by the DMA driver for memcpy operations) | ||
114 | 52: SLIMbus or HSI channel 4 | ||
115 | 53: SLIMbus or HSI channel 5 | ||
116 | 54: SLIMbus or HSI channel 6 | ||
117 | 55: SLIMbus or HSI channel 7 | ||
118 | 56: memcpy (to be used by the DMA driver for memcpy operations) | ||
119 | 57: memcpy (to be used by the DMA driver for memcpy operations) | ||
120 | 58: memcpy (to be used by the DMA driver for memcpy operations) | ||
121 | 59: memcpy (to be used by the DMA driver for memcpy operations) | ||
122 | 60: memcpy (to be used by the DMA driver for memcpy operations) | ||
123 | 61: Crypto Accelerator 0 | ||
124 | 62: Crypto Accelerator 0 TX or Hash Accelerator 0 TX | ||
125 | 63: Hash Accelerator 0 TX | ||
126 | |||
57 | Example: | 127 | Example: |
58 | 128 | ||
59 | uart@80120000 { | 129 | uart@80120000 { |