2 files changed, 162 insertions, 150 deletions
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
index e885680f6b45..fcfed5bf73fb 100644
--- a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
@@ -12,155 +12,9 @@ Required properties :
 - clocks : Should contain phandle and clock specifiers for two clocks:
  the 32 KHz "32k_in", and the board-specific oscillator "osc".
 - #clock-cells : Should be 1.
-  In clock consumers, this cell represents the clock ID exposed by the CAR.
+  In clock consumers, this cell represents the clock ID exposed by the
+  CAR. The assignments may be found in header file
-  The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
+  <dt-bindings/clock/tegra20-car.h>.
-  registers. These IDs often match those in the CAR's RST_DEVICES registers,
-  but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
-  this case, those clocks are assigned IDs above 95 in order to highlight
-  this issue. Implementations that interpret these clock IDs as bit values
-  within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
-  explicitly handle these special cases.
-  The balance of the clocks controlled by the CAR are assigned IDs of 96 and
-  above.
-  0     cpu
-  1     unassigned
-  2     unassigned
-  3     ac97
-  4     rtc
-  5     tmr
-  6     uart1
-  7     unassigned      (register bit affects uart2 and vfir)
-  8     gpio
-  9     sdmmc2
-  10    unassigned      (register bit affects spdif_in and spdif_out)
-  11    i2s1
-  12    i2c1
-  13    ndflash
-  14    sdmmc1
-  15    sdmmc4
-  16    twc
-  17    pwm
-  18    i2s2
-  19    epp
-  20    unassigned      (register bit affects vi and vi_sensor)
-  21    2d
-  22    usbd
-  23    isp
-  24    3d
-  25    ide
-  26    disp2
-  27    disp1
-  28    host1x
-  29    vcp
-  30    unassigned
-  31    cache2
-  32    mem
-  33    ahbdma
-  34    apbdma
-  35    unassigned
-  36    kbc
-  37    stat_mon
-  38    pmc
-  39    fuse
-  40    kfuse
-  41    sbc1
-  42    snor
-  43    spi1
-  44    sbc2
-  45    xio
-  46    sbc3
-  47    dvc
-  48    dsi
-  49    unassigned      (register bit affects tvo and cve)
-  50    mipi
-  51    hdmi
-  52    csi
-  53    tvdac
-  54    i2c2
-  55    uart3
-  56    unassigned
-  57    emc
-  58    usb2
-  59    usb3
-  60    mpe
-  61    vde
-  62    bsea
-  63    bsev
-  64    speedo
-  65    uart4
-  66    uart5
-  67    i2c3
-  68    sbc4
-  69    sdmmc3
-  70    pcie
-  71    owr
-  72    afi
-  73    csite
-  74    unassigned
-  75    avpucq
-  76    la
-  77    unassigned
-  78    unassigned
-  79    unassigned
-  80    unassigned
-  81    unassigned
-  82    unassigned
-  83    unassigned
-  84    irama
-  85    iramb
-  86    iramc
-  87    iramd
-  88    cram2
-  89    audio_2x        a/k/a audio_2x_sync_clk
-  90    clk_d
-  91    unassigned
-  92    sus
-  93    cdev2
-  94    cdev1
-  95    unassigned
-  96    uart2
-  97    vfir
-  98    spdif_in
-  99    spdif_out
-  100   vi
-  101   vi_sensor
-  102   tvo
-  103   cve
-  104   osc
-  105   clk_32k         a/k/a clk_s
-  106   clk_m
-  107   sclk
-  108   cclk
-  109   hclk
-  110   pclk
-  111   blink
-  112   pll_a
-  113   pll_a_out0
-  114   pll_c
-  115   pll_c_out1
-  116   pll_d
-  117   pll_d_out0
-  118   pll_e
-  119   pll_m
-  120   pll_m_out1
-  121   pll_p
-  122   pll_p_out1
-  123   pll_p_out2
-  124   pll_p_out3
-  125   pll_p_out4
-  126   pll_s
-  127   pll_u
-  128   pll_x
-  129   cop             a/k/a avp
-  130   audio           a/k/a audio_sync_clk
-  131   pll_ref
-  132   twd
 Example SoC include file:
@@ -172,7 +26,7 @@ Example SoC include file:
        };
        usb@c5004000 {
-                clocks = <&tegra_car 58>; /* usb2 */
+                clocks = <&tegra_car TEGRA20_CLK_USB2>;
        };
 };
diff --git a/include/dt-bindings/clock/tegra20-car.h b/include/dt-bindings/clock/tegra20-car.h
new file mode 100644
index 000000000000..a1ae9a8fdd6c
--- /dev/null
+++ b/include/dt-bindings/clock/tegra20-car.h
@@ -0,0 +1,158 @@
+/*
+ * This header provides constants for binding nvidia,tegra20-car.
+ *
+ * The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
+ * registers. These IDs often match those in the CAR's RST_DEVICES registers,
+ * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
+ * this case, those clocks are assigned IDs above 95 in order to highlight
+ * this issue. Implementations that interpret these clock IDs as bit values
+ * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
+ * explicitly handle these special cases.
+ *
+ * The balance of the clocks controlled by the CAR are assigned IDs of 96 and
+ * above.
+ */
+#ifndef _DT_BINDINGS_CLOCK_TEGRA20_CAR_H
+#define _DT_BINDINGS_CLOCK_TEGRA20_CAR_H
+#define TEGRA20_CLK_CPU 0
+/* 1 */
+/* 2 */
+#define TEGRA20_CLK_AC97 3
+#define TEGRA20_CLK_RTC 4
+#define TEGRA20_CLK_TIMER 5
+#define TEGRA20_CLK_UARTA 6
+/* 7 (register bit affects uart2 and vfir) */
+#define TEGRA20_CLK_GPIO 8
+#define TEGRA20_CLK_SDMMC2 9
+/* 10 (register bit affects spdif_in and spdif_out) */
+#define TEGRA20_CLK_I2S1 11
+#define TEGRA20_CLK_I2C1 12
+#define TEGRA20_CLK_NDFLASH 13
+#define TEGRA20_CLK_SDMMC1 14
+#define TEGRA20_CLK_SDMMC4 15
+#define TEGRA20_CLK_TWC 16
+#define TEGRA20_CLK_PWM 17
+#define TEGRA20_CLK_I2S2 18
+#define TEGRA20_CLK_EPP 19
+/* 20 (register bit affects vi and vi_sensor) */
+#define TEGRA20_CLK_GR2D 21
+#define TEGRA20_CLK_USBD 22
+#define TEGRA20_CLK_ISP 23
+#define TEGRA20_CLK_GR3D 24
+#define TEGRA20_CLK_IDE 25
+#define TEGRA20_CLK_DISP2 26
+#define TEGRA20_CLK_DISP1 27
+#define TEGRA20_CLK_HOST1X 28
+#define TEGRA20_CLK_VCP 29
+/* 30 */
+#define TEGRA20_CLK_CACHE2 31
+#define TEGRA20_CLK_MEM 32
+#define TEGRA20_CLK_AHBDMA 33
+#define TEGRA20_CLK_APBDMA 34
+/* 35 */
+#define TEGRA20_CLK_KBC 36
+#define TEGRA20_CLK_STAT_MON 37
+#define TEGRA20_CLK_PMC 38
+#define TEGRA20_CLK_FUSE 39
+#define TEGRA20_CLK_KFUSE 40
+#define TEGRA20_CLK_SBC1 41
+#define TEGRA20_CLK_NOR 42
+#define TEGRA20_CLK_SPI 43
+#define TEGRA20_CLK_SBC2 44
+#define TEGRA20_CLK_XIO 45
+#define TEGRA20_CLK_SBC3 46
+#define TEGRA20_CLK_DVC 47
+#define TEGRA20_CLK_DSI 48
+/* 49 (register bit affects tvo and cve) */
+#define TEGRA20_CLK_MIPI 50
+#define TEGRA20_CLK_HDMI 51
+#define TEGRA20_CLK_CSI 52
+#define TEGRA20_CLK_TVDAC 53
+#define TEGRA20_CLK_I2C2 54
+#define TEGRA20_CLK_UARTC 55
+/* 56 */
+#define TEGRA20_CLK_EMC 57
+#define TEGRA20_CLK_USB2 58
+#define TEGRA20_CLK_USB3 59
+#define TEGRA20_CLK_MPE 60
+#define TEGRA20_CLK_VDE 61
+#define TEGRA20_CLK_BSEA 62
+#define TEGRA20_CLK_BSEV 63
+#define TEGRA20_CLK_SPEEDO 64
+#define TEGRA20_CLK_UARTD 65
+#define TEGRA20_CLK_UARTE 66
+#define TEGRA20_CLK_I2C3 67
+#define TEGRA20_CLK_SBC4 68
+#define TEGRA20_CLK_SDMMC3 69
+#define TEGRA20_CLK_PEX 70
+#define TEGRA20_CLK_OWR 71
+#define TEGRA20_CLK_AFI 72
+#define TEGRA20_CLK_CSITE 73
+#define TEGRA20_CLK_PCIE_XCLK 74
+#define TEGRA20_CLK_AVPUCQ 75
+#define TEGRA20_CLK_LA 76
+/* 77 */
+/* 78 */
+/* 79 */
+/* 80 */
+/* 81 */
+/* 82 */
+/* 83 */
+#define TEGRA20_CLK_IRAMA 84
+#define TEGRA20_CLK_IRAMB 85
+#define TEGRA20_CLK_IRAMC 86
+#define TEGRA20_CLK_IRAMD 87
+#define TEGRA20_CLK_CRAM2 88
+#define TEGRA20_CLK_AUDIO_2X 89 /* a/k/a audio_2x_sync_clk */
+#define TEGRA20_CLK_CLK_D 90
+/* 91 */
+#define TEGRA20_CLK_CSUS 92
+#define TEGRA20_CLK_CDEV2 93
+#define TEGRA20_CLK_CDEV1 94
+/* 95 */
+#define TEGRA20_CLK_UARTB 96
+#define TEGRA20_CLK_VFIR 97
+#define TEGRA20_CLK_SPDIF_IN 98
+#define TEGRA20_CLK_SPDIF_OUT 99
+#define TEGRA20_CLK_VI 100
+#define TEGRA20_CLK_VI_SENSOR 101
+#define TEGRA20_CLK_TVO 102
+#define TEGRA20_CLK_CVE 103
+#define TEGRA20_CLK_OSC 104
+#define TEGRA20_CLK_CLK_32K 105 /* a/k/a clk_s */
+#define TEGRA20_CLK_CLK_M 106
+#define TEGRA20_CLK_SCLK 107
+#define TEGRA20_CLK_CCLK 108
+#define TEGRA20_CLK_HCLK 109
+#define TEGRA20_CLK_PCLK 110
+#define TEGRA20_CLK_BLINK 111
+#define TEGRA20_CLK_PLL_A 112
+#define TEGRA20_CLK_PLL_A_OUT0 113
+#define TEGRA20_CLK_PLL_C 114
+#define TEGRA20_CLK_PLL_C_OUT1 115
+#define TEGRA20_CLK_PLL_D 116
+#define TEGRA20_CLK_PLL_D_OUT0 117
+#define TEGRA20_CLK_PLL_E 118
+#define TEGRA20_CLK_PLL_M 119
+#define TEGRA20_CLK_PLL_M_OUT1 120
+#define TEGRA20_CLK_PLL_P 121
+#define TEGRA20_CLK_PLL_P_OUT1 122
+#define TEGRA20_CLK_PLL_P_OUT2 123
+#define TEGRA20_CLK_PLL_P_OUT3 124
+#define TEGRA20_CLK_PLL_P_OUT4 125
+#define TEGRA20_CLK_PLL_S 126
+#define TEGRA20_CLK_PLL_U 127
+#define TEGRA20_CLK_PLL_X 128
+#define TEGRA20_CLK_COP 129 /* a/k/a avp */
+#define TEGRA20_CLK_AUDIO 130 /* a/k/a audio_sync_clk */
+#define TEGRA20_CLK_PLL_REF 131
+#define TEGRA20_CLK_TWD 132
+#define TEGRA20_CLK_CLK_MAX 133
+#endif  /* _DT_BINDINGS_CLOCK_TEGRA20_CAR_H */

diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt index e885680f6b45..fcfed5bf73fb 100644 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
@@ -12,155 +12,9 @@ Required properties :
12	- clocks : Should contain phandle and clock specifiers for two clocks:	12	- clocks : Should contain phandle and clock specifiers for two clocks:
13	the 32 KHz "32k_in", and the board-specific oscillator "osc".	13	the 32 KHz "32k_in", and the board-specific oscillator "osc".
14	- #clock-cells : Should be 1.	14	- #clock-cells : Should be 1.
15	In clock consumers, this cell represents the clock ID exposed by the CAR.	15	In clock consumers, this cell represents the clock ID exposed by the
16		16	CAR. The assignments may be found in header file
17	The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB	17	<dt-bindings/clock/tegra20-car.h>.
18	registers. These IDs often match those in the CAR's RST_DEVICES registers,
19	but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
20	this case, those clocks are assigned IDs above 95 in order to highlight
21	this issue. Implementations that interpret these clock IDs as bit values
22	within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
23	explicitly handle these special cases.
24
25	The balance of the clocks controlled by the CAR are assigned IDs of 96 and
26	above.
27
28	0 cpu
29	1 unassigned
30	2 unassigned
31	3 ac97
32	4 rtc
33	5 tmr
34	6 uart1
35	7 unassigned (register bit affects uart2 and vfir)
36	8 gpio
37	9 sdmmc2
38	10 unassigned (register bit affects spdif_in and spdif_out)
39	11 i2s1
40	12 i2c1
41	13 ndflash
42	14 sdmmc1
43	15 sdmmc4
44	16 twc
45	17 pwm
46	18 i2s2
47	19 epp
48	20 unassigned (register bit affects vi and vi_sensor)
49	21 2d
50	22 usbd
51	23 isp
52	24 3d
53	25 ide
54	26 disp2
55	27 disp1
56	28 host1x
57	29 vcp
58	30 unassigned
59	31 cache2
60
61	32 mem
62	33 ahbdma
63	34 apbdma
64	35 unassigned
65	36 kbc
66	37 stat_mon
67	38 pmc
68	39 fuse
69	40 kfuse
70	41 sbc1
71	42 snor
72	43 spi1
73	44 sbc2
74	45 xio
75	46 sbc3
76	47 dvc
77	48 dsi
78	49 unassigned (register bit affects tvo and cve)
79	50 mipi
80	51 hdmi
81	52 csi
82	53 tvdac
83	54 i2c2
84	55 uart3
85	56 unassigned
86	57 emc
87	58 usb2
88	59 usb3
89	60 mpe
90	61 vde
91	62 bsea
92	63 bsev
93
94	64 speedo
95	65 uart4
96	66 uart5
97	67 i2c3
98	68 sbc4
99	69 sdmmc3
100	70 pcie
101	71 owr
102	72 afi
103	73 csite
104	74 unassigned
105	75 avpucq
106	76 la
107	77 unassigned
108	78 unassigned
109	79 unassigned
110	80 unassigned
111	81 unassigned
112	82 unassigned
113	83 unassigned
114	84 irama
115	85 iramb
116	86 iramc
117	87 iramd
118	88 cram2
119	89 audio_2x a/k/a audio_2x_sync_clk
120	90 clk_d
121	91 unassigned
122	92 sus
123	93 cdev2
124	94 cdev1
125	95 unassigned
126
127	96 uart2
128	97 vfir
129	98 spdif_in
130	99 spdif_out
131	100 vi
132	101 vi_sensor
133	102 tvo
134	103 cve
135	104 osc
136	105 clk_32k a/k/a clk_s
137	106 clk_m
138	107 sclk
139	108 cclk
140	109 hclk
141	110 pclk
142	111 blink
143	112 pll_a
144	113 pll_a_out0
145	114 pll_c
146	115 pll_c_out1
147	116 pll_d
148	117 pll_d_out0
149	118 pll_e
150	119 pll_m
151	120 pll_m_out1
152	121 pll_p
153	122 pll_p_out1
154	123 pll_p_out2
155	124 pll_p_out3
156	125 pll_p_out4
157	126 pll_s
158	127 pll_u
159	128 pll_x
160	129 cop a/k/a avp
161	130 audio a/k/a audio_sync_clk
162	131 pll_ref
163	132 twd
164		18
165	Example SoC include file:	19	Example SoC include file:
166		20
@@ -172,7 +26,7 @@ Example SoC include file:
172	};	26	};
173		27
174	usb@c5004000 {	28	usb@c5004000 {
175	clocks = <&tegra_car 58>; /* usb2 */	29	clocks = <&tegra_car TEGRA20_CLK_USB2>;
176	};	30	};
177	};	31	};
178		32


diff --git a/include/dt-bindings/clock/tegra20-car.h b/include/dt-bindings/clock/tegra20-car.h new file mode 100644 index 000000000000..a1ae9a8fdd6c --- /dev/null +++ b/include/dt-bindings/clock/tegra20-car.h
@@ -0,0 +1,158 @@
		1	/*
		2	* This header provides constants for binding nvidia,tegra20-car.
		3	*
		4	* The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
		5	* registers. These IDs often match those in the CAR's RST_DEVICES registers,
		6	* but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
		7	* this case, those clocks are assigned IDs above 95 in order to highlight
		8	* this issue. Implementations that interpret these clock IDs as bit values
		9	* within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
		10	* explicitly handle these special cases.
		11	*
		12	* The balance of the clocks controlled by the CAR are assigned IDs of 96 and
		13	* above.
		14	*/
		15
		16	#ifndef _DT_BINDINGS_CLOCK_TEGRA20_CAR_H
		17	#define _DT_BINDINGS_CLOCK_TEGRA20_CAR_H
		18
		19	#define TEGRA20_CLK_CPU 0
		20	/* 1 */
		21	/* 2 */
		22	#define TEGRA20_CLK_AC97 3
		23	#define TEGRA20_CLK_RTC 4
		24	#define TEGRA20_CLK_TIMER 5
		25	#define TEGRA20_CLK_UARTA 6
		26	/* 7 (register bit affects uart2 and vfir) */
		27	#define TEGRA20_CLK_GPIO 8
		28	#define TEGRA20_CLK_SDMMC2 9
		29	/* 10 (register bit affects spdif_in and spdif_out) */
		30	#define TEGRA20_CLK_I2S1 11
		31	#define TEGRA20_CLK_I2C1 12
		32	#define TEGRA20_CLK_NDFLASH 13
		33	#define TEGRA20_CLK_SDMMC1 14
		34	#define TEGRA20_CLK_SDMMC4 15
		35	#define TEGRA20_CLK_TWC 16
		36	#define TEGRA20_CLK_PWM 17
		37	#define TEGRA20_CLK_I2S2 18
		38	#define TEGRA20_CLK_EPP 19
		39	/* 20 (register bit affects vi and vi_sensor) */
		40	#define TEGRA20_CLK_GR2D 21
		41	#define TEGRA20_CLK_USBD 22
		42	#define TEGRA20_CLK_ISP 23
		43	#define TEGRA20_CLK_GR3D 24
		44	#define TEGRA20_CLK_IDE 25
		45	#define TEGRA20_CLK_DISP2 26
		46	#define TEGRA20_CLK_DISP1 27
		47	#define TEGRA20_CLK_HOST1X 28
		48	#define TEGRA20_CLK_VCP 29
		49	/* 30 */
		50	#define TEGRA20_CLK_CACHE2 31
		51
		52	#define TEGRA20_CLK_MEM 32
		53	#define TEGRA20_CLK_AHBDMA 33
		54	#define TEGRA20_CLK_APBDMA 34
		55	/* 35 */
		56	#define TEGRA20_CLK_KBC 36
		57	#define TEGRA20_CLK_STAT_MON 37
		58	#define TEGRA20_CLK_PMC 38
		59	#define TEGRA20_CLK_FUSE 39
		60	#define TEGRA20_CLK_KFUSE 40
		61	#define TEGRA20_CLK_SBC1 41
		62	#define TEGRA20_CLK_NOR 42
		63	#define TEGRA20_CLK_SPI 43
		64	#define TEGRA20_CLK_SBC2 44
		65	#define TEGRA20_CLK_XIO 45
		66	#define TEGRA20_CLK_SBC3 46
		67	#define TEGRA20_CLK_DVC 47
		68	#define TEGRA20_CLK_DSI 48
		69	/* 49 (register bit affects tvo and cve) */
		70	#define TEGRA20_CLK_MIPI 50
		71	#define TEGRA20_CLK_HDMI 51
		72	#define TEGRA20_CLK_CSI 52
		73	#define TEGRA20_CLK_TVDAC 53
		74	#define TEGRA20_CLK_I2C2 54
		75	#define TEGRA20_CLK_UARTC 55
		76	/* 56 */
		77	#define TEGRA20_CLK_EMC 57
		78	#define TEGRA20_CLK_USB2 58
		79	#define TEGRA20_CLK_USB3 59
		80	#define TEGRA20_CLK_MPE 60
		81	#define TEGRA20_CLK_VDE 61
		82	#define TEGRA20_CLK_BSEA 62
		83	#define TEGRA20_CLK_BSEV 63
		84
		85	#define TEGRA20_CLK_SPEEDO 64
		86	#define TEGRA20_CLK_UARTD 65
		87	#define TEGRA20_CLK_UARTE 66
		88	#define TEGRA20_CLK_I2C3 67
		89	#define TEGRA20_CLK_SBC4 68
		90	#define TEGRA20_CLK_SDMMC3 69
		91	#define TEGRA20_CLK_PEX 70
		92	#define TEGRA20_CLK_OWR 71
		93	#define TEGRA20_CLK_AFI 72
		94	#define TEGRA20_CLK_CSITE 73
		95	#define TEGRA20_CLK_PCIE_XCLK 74
		96	#define TEGRA20_CLK_AVPUCQ 75
		97	#define TEGRA20_CLK_LA 76
		98	/* 77 */
		99	/* 78 */
		100	/* 79 */
		101	/* 80 */
		102	/* 81 */
		103	/* 82 */
		104	/* 83 */
		105	#define TEGRA20_CLK_IRAMA 84
		106	#define TEGRA20_CLK_IRAMB 85
		107	#define TEGRA20_CLK_IRAMC 86
		108	#define TEGRA20_CLK_IRAMD 87
		109	#define TEGRA20_CLK_CRAM2 88
		110	#define TEGRA20_CLK_AUDIO_2X 89 /* a/k/a audio_2x_sync_clk */
		111	#define TEGRA20_CLK_CLK_D 90
		112	/* 91 */
		113	#define TEGRA20_CLK_CSUS 92
		114	#define TEGRA20_CLK_CDEV2 93
		115	#define TEGRA20_CLK_CDEV1 94
		116	/* 95 */
		117
		118	#define TEGRA20_CLK_UARTB 96
		119	#define TEGRA20_CLK_VFIR 97
		120	#define TEGRA20_CLK_SPDIF_IN 98
		121	#define TEGRA20_CLK_SPDIF_OUT 99
		122	#define TEGRA20_CLK_VI 100
		123	#define TEGRA20_CLK_VI_SENSOR 101
		124	#define TEGRA20_CLK_TVO 102
		125	#define TEGRA20_CLK_CVE 103
		126	#define TEGRA20_CLK_OSC 104
		127	#define TEGRA20_CLK_CLK_32K 105 /* a/k/a clk_s */
		128	#define TEGRA20_CLK_CLK_M 106
		129	#define TEGRA20_CLK_SCLK 107
		130	#define TEGRA20_CLK_CCLK 108
		131	#define TEGRA20_CLK_HCLK 109
		132	#define TEGRA20_CLK_PCLK 110
		133	#define TEGRA20_CLK_BLINK 111
		134	#define TEGRA20_CLK_PLL_A 112
		135	#define TEGRA20_CLK_PLL_A_OUT0 113
		136	#define TEGRA20_CLK_PLL_C 114
		137	#define TEGRA20_CLK_PLL_C_OUT1 115
		138	#define TEGRA20_CLK_PLL_D 116
		139	#define TEGRA20_CLK_PLL_D_OUT0 117
		140	#define TEGRA20_CLK_PLL_E 118
		141	#define TEGRA20_CLK_PLL_M 119
		142	#define TEGRA20_CLK_PLL_M_OUT1 120
		143	#define TEGRA20_CLK_PLL_P 121
		144	#define TEGRA20_CLK_PLL_P_OUT1 122
		145	#define TEGRA20_CLK_PLL_P_OUT2 123
		146	#define TEGRA20_CLK_PLL_P_OUT3 124
		147	#define TEGRA20_CLK_PLL_P_OUT4 125
		148	#define TEGRA20_CLK_PLL_S 126
		149	#define TEGRA20_CLK_PLL_U 127
		150
		151	#define TEGRA20_CLK_PLL_X 128
		152	#define TEGRA20_CLK_COP 129 /* a/k/a avp */
		153	#define TEGRA20_CLK_AUDIO 130 /* a/k/a audio_sync_clk */
		154	#define TEGRA20_CLK_PLL_REF 131
		155	#define TEGRA20_CLK_TWD 132
		156	#define TEGRA20_CLK_CLK_MAX 133
		157
		158	#endif /* _DT_BINDINGS_CLOCK_TEGRA20_CAR_H */