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-rw-r--r--arch/sparc/include/asm/io_64.h381
-rw-r--r--arch/sparc/kernel/mdesc.c82
-rw-r--r--arch/sparc/kernel/unaligned_32.c2
-rw-r--r--arch/sparc/lib/PeeCeeI.c36
-rw-r--r--arch/sparc/mm/init_64.c66
-rw-r--r--drivers/input/misc/sparcspkr.c22
-rw-r--r--drivers/sbus/char/display7seg.c10
7 files changed, 313 insertions, 286 deletions
diff --git a/arch/sparc/include/asm/io_64.h b/arch/sparc/include/asm/io_64.h
index 05381c3a4228..80b54b326d49 100644
--- a/arch/sparc/include/asm/io_64.h
+++ b/arch/sparc/include/asm/io_64.h
@@ -9,125 +9,99 @@
9#include <asm/asi.h> 9#include <asm/asi.h>
10#include <asm-generic/pci_iomap.h> 10#include <asm-generic/pci_iomap.h>
11 11
12/* PC crapola... */
13#define __SLOW_DOWN_IO do { } while (0)
14#define SLOW_DOWN_IO do { } while (0)
15
16/* BIO layer definitions. */ 12/* BIO layer definitions. */
17extern unsigned long kern_base, kern_size; 13extern unsigned long kern_base, kern_size;
18 14
19static inline u8 _inb(unsigned long addr) 15/* __raw_{read,write}{b,w,l,q} uses direct access.
16 * Access the memory as big endian bypassing the cache
17 * by using ASI_PHYS_BYPASS_EC_E
18 */
19#define __raw_readb __raw_readb
20static inline u8 __raw_readb(const volatile void __iomem *addr)
20{ 21{
21 u8 ret; 22 u8 ret;
22 23
23 __asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_inb */" 24 __asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_raw_readb */"
24 : "=r" (ret) 25 : "=r" (ret)
25 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) 26 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
26 : "memory");
27 27
28 return ret; 28 return ret;
29} 29}
30 30
31static inline u16 _inw(unsigned long addr) 31#define __raw_readw __raw_readw
32static inline u16 __raw_readw(const volatile void __iomem *addr)
32{ 33{
33 u16 ret; 34 u16 ret;
34 35
35 __asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_inw */" 36 __asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_raw_readw */"
36 : "=r" (ret) 37 : "=r" (ret)
37 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) 38 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
38 : "memory");
39 39
40 return ret; 40 return ret;
41} 41}
42 42
43static inline u32 _inl(unsigned long addr) 43#define __raw_readl __raw_readl
44static inline u32 __raw_readl(const volatile void __iomem *addr)
44{ 45{
45 u32 ret; 46 u32 ret;
46 47
47 __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_inl */" 48 __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_raw_readl */"
48 : "=r" (ret) 49 : "=r" (ret)
49 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) 50 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
50 : "memory");
51 51
52 return ret; 52 return ret;
53} 53}
54 54
55static inline void _outb(u8 b, unsigned long addr) 55#define __raw_readq __raw_readq
56{ 56static inline u64 __raw_readq(const volatile void __iomem *addr)
57 __asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_outb */"
58 : /* no outputs */
59 : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
60 : "memory");
61}
62
63static inline void _outw(u16 w, unsigned long addr)
64{ 57{
65 __asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_outw */" 58 u64 ret;
66 : /* no outputs */
67 : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
68 : "memory");
69}
70
71static inline void _outl(u32 l, unsigned long addr)
72{
73 __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_outl */"
74 : /* no outputs */
75 : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
76 : "memory");
77}
78
79#define inb(__addr) (_inb((unsigned long)(__addr)))
80#define inw(__addr) (_inw((unsigned long)(__addr)))
81#define inl(__addr) (_inl((unsigned long)(__addr)))
82#define outb(__b, __addr) (_outb((u8)(__b), (unsigned long)(__addr)))
83#define outw(__w, __addr) (_outw((u16)(__w), (unsigned long)(__addr)))
84#define outl(__l, __addr) (_outl((u32)(__l), (unsigned long)(__addr)))
85
86#define inb_p(__addr) inb(__addr)
87#define outb_p(__b, __addr) outb(__b, __addr)
88#define inw_p(__addr) inw(__addr)
89#define outw_p(__w, __addr) outw(__w, __addr)
90#define inl_p(__addr) inl(__addr)
91#define outl_p(__l, __addr) outl(__l, __addr)
92 59
93void outsb(unsigned long, const void *, unsigned long); 60 __asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_raw_readq */"
94void outsw(unsigned long, const void *, unsigned long); 61 : "=r" (ret)
95void outsl(unsigned long, const void *, unsigned long); 62 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
96void insb(unsigned long, void *, unsigned long);
97void insw(unsigned long, void *, unsigned long);
98void insl(unsigned long, void *, unsigned long);
99 63
100static inline void ioread8_rep(void __iomem *port, void *buf, unsigned long count) 64 return ret;
101{
102 insb((unsigned long __force)port, buf, count);
103}
104static inline void ioread16_rep(void __iomem *port, void *buf, unsigned long count)
105{
106 insw((unsigned long __force)port, buf, count);
107} 65}
108 66
109static inline void ioread32_rep(void __iomem *port, void *buf, unsigned long count) 67#define __raw_writeb __raw_writeb
68static inline void __raw_writeb(u8 b, const volatile void __iomem *addr)
110{ 69{
111 insl((unsigned long __force)port, buf, count); 70 __asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_raw_writeb */"
71 : /* no outputs */
72 : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
112} 73}
113 74
114static inline void iowrite8_rep(void __iomem *port, const void *buf, unsigned long count) 75#define __raw_writew __raw_writew
76static inline void __raw_writew(u16 w, const volatile void __iomem *addr)
115{ 77{
116 outsb((unsigned long __force)port, buf, count); 78 __asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_raw_writew */"
79 : /* no outputs */
80 : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
117} 81}
118 82
119static inline void iowrite16_rep(void __iomem *port, const void *buf, unsigned long count) 83#define __raw_writel __raw_writel
84static inline void __raw_writel(u32 l, const volatile void __iomem *addr)
120{ 85{
121 outsw((unsigned long __force)port, buf, count); 86 __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_raw_writel */"
87 : /* no outputs */
88 : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
122} 89}
123 90
124static inline void iowrite32_rep(void __iomem *port, const void *buf, unsigned long count) 91#define __raw_writeq __raw_writeq
92static inline void __raw_writeq(u64 q, const volatile void __iomem *addr)
125{ 93{
126 outsl((unsigned long __force)port, buf, count); 94 __asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_raw_writeq */"
95 : /* no outputs */
96 : "Jr" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
127} 97}
128 98
129/* Memory functions, same as I/O accesses on Ultra. */ 99/* Memory functions, same as I/O accesses on Ultra.
130static inline u8 _readb(const volatile void __iomem *addr) 100 * Access memory as little endian bypassing
101 * the cache by using ASI_PHYS_BYPASS_EC_E_L
102 */
103#define readb readb
104static inline u8 readb(const volatile void __iomem *addr)
131{ u8 ret; 105{ u8 ret;
132 106
133 __asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_readb */" 107 __asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_readb */"
@@ -137,7 +111,8 @@ static inline u8 _readb(const volatile void __iomem *addr)
137 return ret; 111 return ret;
138} 112}
139 113
140static inline u16 _readw(const volatile void __iomem *addr) 114#define readw readw
115static inline u16 readw(const volatile void __iomem *addr)
141{ u16 ret; 116{ u16 ret;
142 117
143 __asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_readw */" 118 __asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_readw */"
@@ -148,7 +123,8 @@ static inline u16 _readw(const volatile void __iomem *addr)
148 return ret; 123 return ret;
149} 124}
150 125
151static inline u32 _readl(const volatile void __iomem *addr) 126#define readl readl
127static inline u32 readl(const volatile void __iomem *addr)
152{ u32 ret; 128{ u32 ret;
153 129
154 __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_readl */" 130 __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_readl */"
@@ -159,7 +135,8 @@ static inline u32 _readl(const volatile void __iomem *addr)
159 return ret; 135 return ret;
160} 136}
161 137
162static inline u64 _readq(const volatile void __iomem *addr) 138#define readq readq
139static inline u64 readq(const volatile void __iomem *addr)
163{ u64 ret; 140{ u64 ret;
164 141
165 __asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_readq */" 142 __asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_readq */"
@@ -170,7 +147,8 @@ static inline u64 _readq(const volatile void __iomem *addr)
170 return ret; 147 return ret;
171} 148}
172 149
173static inline void _writeb(u8 b, volatile void __iomem *addr) 150#define writeb writeb
151static inline void writeb(u8 b, volatile void __iomem *addr)
174{ 152{
175 __asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_writeb */" 153 __asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_writeb */"
176 : /* no outputs */ 154 : /* no outputs */
@@ -178,7 +156,8 @@ static inline void _writeb(u8 b, volatile void __iomem *addr)
178 : "memory"); 156 : "memory");
179} 157}
180 158
181static inline void _writew(u16 w, volatile void __iomem *addr) 159#define writew writew
160static inline void writew(u16 w, volatile void __iomem *addr)
182{ 161{
183 __asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_writew */" 162 __asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_writew */"
184 : /* no outputs */ 163 : /* no outputs */
@@ -186,7 +165,8 @@ static inline void _writew(u16 w, volatile void __iomem *addr)
186 : "memory"); 165 : "memory");
187} 166}
188 167
189static inline void _writel(u32 l, volatile void __iomem *addr) 168#define writel writel
169static inline void writel(u32 l, volatile void __iomem *addr)
190{ 170{
191 __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_writel */" 171 __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_writel */"
192 : /* no outputs */ 172 : /* no outputs */
@@ -194,7 +174,8 @@ static inline void _writel(u32 l, volatile void __iomem *addr)
194 : "memory"); 174 : "memory");
195} 175}
196 176
197static inline void _writeq(u64 q, volatile void __iomem *addr) 177#define writeq writeq
178static inline void writeq(u64 q, volatile void __iomem *addr)
198{ 179{
199 __asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_writeq */" 180 __asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_writeq */"
200 : /* no outputs */ 181 : /* no outputs */
@@ -202,100 +183,91 @@ static inline void _writeq(u64 q, volatile void __iomem *addr)
202 : "memory"); 183 : "memory");
203} 184}
204 185
205#define readb(__addr) _readb(__addr)
206#define readw(__addr) _readw(__addr)
207#define readl(__addr) _readl(__addr)
208#define readq(__addr) _readq(__addr)
209#define readb_relaxed(__addr) _readb(__addr)
210#define readw_relaxed(__addr) _readw(__addr)
211#define readl_relaxed(__addr) _readl(__addr)
212#define readq_relaxed(__addr) _readq(__addr)
213#define writeb(__b, __addr) _writeb(__b, __addr)
214#define writew(__w, __addr) _writew(__w, __addr)
215#define writel(__l, __addr) _writel(__l, __addr)
216#define writeq(__q, __addr) _writeq(__q, __addr)
217 186
218/* Now versions without byte-swapping. */ 187#define inb inb
219static inline u8 _raw_readb(unsigned long addr) 188static inline u8 inb(unsigned long addr)
220{ 189{
221 u8 ret; 190 return readb((volatile void __iomem *)addr);
222
223 __asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_raw_readb */"
224 : "=r" (ret)
225 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
226
227 return ret;
228} 191}
229 192
230static inline u16 _raw_readw(unsigned long addr) 193#define inw inw
194static inline u16 inw(unsigned long addr)
231{ 195{
232 u16 ret; 196 return readw((volatile void __iomem *)addr);
233
234 __asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_raw_readw */"
235 : "=r" (ret)
236 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
237
238 return ret;
239} 197}
240 198
241static inline u32 _raw_readl(unsigned long addr) 199#define inl inl
200static inline u32 inl(unsigned long addr)
242{ 201{
243 u32 ret; 202 return readl((volatile void __iomem *)addr);
203}
244 204
245 __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_raw_readl */" 205#define outb outb
246 : "=r" (ret) 206static inline void outb(u8 b, unsigned long addr)
247 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); 207{
208 writeb(b, (volatile void __iomem *)addr);
209}
248 210
249 return ret; 211#define outw outw
212static inline void outw(u16 w, unsigned long addr)
213{
214 writew(w, (volatile void __iomem *)addr);
250} 215}
251 216
252static inline u64 _raw_readq(unsigned long addr) 217#define outl outl
218static inline void outl(u32 l, unsigned long addr)
253{ 219{
254 u64 ret; 220 writel(l, (volatile void __iomem *)addr);
221}
255 222
256 __asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_raw_readq */"
257 : "=r" (ret)
258 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
259 223
260 return ret; 224#define inb_p(__addr) inb(__addr)
225#define outb_p(__b, __addr) outb(__b, __addr)
226#define inw_p(__addr) inw(__addr)
227#define outw_p(__w, __addr) outw(__w, __addr)
228#define inl_p(__addr) inl(__addr)
229#define outl_p(__l, __addr) outl(__l, __addr)
230
231void outsb(unsigned long, const void *, unsigned long);
232void outsw(unsigned long, const void *, unsigned long);
233void outsl(unsigned long, const void *, unsigned long);
234void insb(unsigned long, void *, unsigned long);
235void insw(unsigned long, void *, unsigned long);
236void insl(unsigned long, void *, unsigned long);
237
238static inline void ioread8_rep(void __iomem *port, void *buf, unsigned long count)
239{
240 insb((unsigned long __force)port, buf, count);
241}
242static inline void ioread16_rep(void __iomem *port, void *buf, unsigned long count)
243{
244 insw((unsigned long __force)port, buf, count);
261} 245}
262 246
263static inline void _raw_writeb(u8 b, unsigned long addr) 247static inline void ioread32_rep(void __iomem *port, void *buf, unsigned long count)
264{ 248{
265 __asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_raw_writeb */" 249 insl((unsigned long __force)port, buf, count);
266 : /* no outputs */
267 : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
268} 250}
269 251
270static inline void _raw_writew(u16 w, unsigned long addr) 252static inline void iowrite8_rep(void __iomem *port, const void *buf, unsigned long count)
271{ 253{
272 __asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_raw_writew */" 254 outsb((unsigned long __force)port, buf, count);
273 : /* no outputs */
274 : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
275} 255}
276 256
277static inline void _raw_writel(u32 l, unsigned long addr) 257static inline void iowrite16_rep(void __iomem *port, const void *buf, unsigned long count)
278{ 258{
279 __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_raw_writel */" 259 outsw((unsigned long __force)port, buf, count);
280 : /* no outputs */
281 : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
282} 260}
283 261
284static inline void _raw_writeq(u64 q, unsigned long addr) 262static inline void iowrite32_rep(void __iomem *port, const void *buf, unsigned long count)
285{ 263{
286 __asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_raw_writeq */" 264 outsl((unsigned long __force)port, buf, count);
287 : /* no outputs */
288 : "Jr" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
289} 265}
290 266
291#define __raw_readb(__addr) (_raw_readb((unsigned long)(__addr))) 267#define readb_relaxed(__addr) readb(__addr)
292#define __raw_readw(__addr) (_raw_readw((unsigned long)(__addr))) 268#define readw_relaxed(__addr) readw(__addr)
293#define __raw_readl(__addr) (_raw_readl((unsigned long)(__addr))) 269#define readl_relaxed(__addr) readl(__addr)
294#define __raw_readq(__addr) (_raw_readq((unsigned long)(__addr))) 270#define readq_relaxed(__addr) readq(__addr)
295#define __raw_writeb(__b, __addr) (_raw_writeb((u8)(__b), (unsigned long)(__addr)))
296#define __raw_writew(__w, __addr) (_raw_writew((u16)(__w), (unsigned long)(__addr)))
297#define __raw_writel(__l, __addr) (_raw_writel((u32)(__l), (unsigned long)(__addr)))
298#define __raw_writeq(__q, __addr) (_raw_writeq((u64)(__q), (unsigned long)(__addr)))
299 271
300/* Valid I/O Space regions are anywhere, because each PCI bus supported 272/* Valid I/O Space regions are anywhere, because each PCI bus supported
301 * can live in an arbitrary area of the physical address range. 273 * can live in an arbitrary area of the physical address range.
@@ -305,96 +277,47 @@ static inline void _raw_writeq(u64 q, unsigned long addr)
305/* Now, SBUS variants, only difference from PCI is that we do 277/* Now, SBUS variants, only difference from PCI is that we do
306 * not use little-endian ASIs. 278 * not use little-endian ASIs.
307 */ 279 */
308static inline u8 _sbus_readb(const volatile void __iomem *addr) 280static inline u8 sbus_readb(const volatile void __iomem *addr)
309{ 281{
310 u8 ret; 282 return __raw_readb(addr);
311
312 __asm__ __volatile__("lduba\t[%1] %2, %0\t/* sbus_readb */"
313 : "=r" (ret)
314 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
315 : "memory");
316
317 return ret;
318} 283}
319 284
320static inline u16 _sbus_readw(const volatile void __iomem *addr) 285static inline u16 sbus_readw(const volatile void __iomem *addr)
321{ 286{
322 u16 ret; 287 return __raw_readw(addr);
323
324 __asm__ __volatile__("lduha\t[%1] %2, %0\t/* sbus_readw */"
325 : "=r" (ret)
326 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
327 : "memory");
328
329 return ret;
330} 288}
331 289
332static inline u32 _sbus_readl(const volatile void __iomem *addr) 290static inline u32 sbus_readl(const volatile void __iomem *addr)
333{ 291{
334 u32 ret; 292 return __raw_readl(addr);
335
336 __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* sbus_readl */"
337 : "=r" (ret)
338 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
339 : "memory");
340
341 return ret;
342} 293}
343 294
344static inline u64 _sbus_readq(const volatile void __iomem *addr) 295static inline u64 sbus_readq(const volatile void __iomem *addr)
345{ 296{
346 u64 ret; 297 return __raw_readq(addr);
347
348 __asm__ __volatile__("ldxa\t[%1] %2, %0\t/* sbus_readq */"
349 : "=r" (ret)
350 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
351 : "memory");
352
353 return ret;
354} 298}
355 299
356static inline void _sbus_writeb(u8 b, volatile void __iomem *addr) 300static inline void sbus_writeb(u8 b, volatile void __iomem *addr)
357{ 301{
358 __asm__ __volatile__("stba\t%r0, [%1] %2\t/* sbus_writeb */" 302 __raw_writeb(b, addr);
359 : /* no outputs */
360 : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
361 : "memory");
362} 303}
363 304
364static inline void _sbus_writew(u16 w, volatile void __iomem *addr) 305static inline void sbus_writew(u16 w, volatile void __iomem *addr)
365{ 306{
366 __asm__ __volatile__("stha\t%r0, [%1] %2\t/* sbus_writew */" 307 __raw_writew(w, addr);
367 : /* no outputs */
368 : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
369 : "memory");
370} 308}
371 309
372static inline void _sbus_writel(u32 l, volatile void __iomem *addr) 310static inline void sbus_writel(u32 l, volatile void __iomem *addr)
373{ 311{
374 __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* sbus_writel */" 312 __raw_writel(l, addr);
375 : /* no outputs */
376 : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
377 : "memory");
378} 313}
379 314
380static inline void _sbus_writeq(u64 l, volatile void __iomem *addr) 315static inline void sbus_writeq(u64 q, volatile void __iomem *addr)
381{ 316{
382 __asm__ __volatile__("stxa\t%r0, [%1] %2\t/* sbus_writeq */" 317 __raw_writeq(q, addr);
383 : /* no outputs */
384 : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)
385 : "memory");
386} 318}
387 319
388#define sbus_readb(__addr) _sbus_readb(__addr) 320static inline void sbus_memset_io(volatile void __iomem *dst, int c, __kernel_size_t n)
389#define sbus_readw(__addr) _sbus_readw(__addr)
390#define sbus_readl(__addr) _sbus_readl(__addr)
391#define sbus_readq(__addr) _sbus_readq(__addr)
392#define sbus_writeb(__b, __addr) _sbus_writeb(__b, __addr)
393#define sbus_writew(__w, __addr) _sbus_writew(__w, __addr)
394#define sbus_writel(__l, __addr) _sbus_writel(__l, __addr)
395#define sbus_writeq(__l, __addr) _sbus_writeq(__l, __addr)
396
397static inline void _sbus_memset_io(volatile void __iomem *dst, int c, __kernel_size_t n)
398{ 321{
399 while(n--) { 322 while(n--) {
400 sbus_writeb(c, dst); 323 sbus_writeb(c, dst);
@@ -402,10 +325,7 @@ static inline void _sbus_memset_io(volatile void __iomem *dst, int c, __kernel_s
402 } 325 }
403} 326}
404 327
405#define sbus_memset_io(d,c,sz) _sbus_memset_io(d,c,sz) 328static inline void memset_io(volatile void __iomem *dst, int c, __kernel_size_t n)
406
407static inline void
408_memset_io(volatile void __iomem *dst, int c, __kernel_size_t n)
409{ 329{
410 volatile void __iomem *d = dst; 330 volatile void __iomem *d = dst;
411 331
@@ -415,11 +335,8 @@ _memset_io(volatile void __iomem *dst, int c, __kernel_size_t n)
415 } 335 }
416} 336}
417 337
418#define memset_io(d,c,sz) _memset_io(d,c,sz) 338static inline void sbus_memcpy_fromio(void *dst, const volatile void __iomem *src,
419 339 __kernel_size_t n)
420static inline void
421_sbus_memcpy_fromio(void *dst, const volatile void __iomem *src,
422 __kernel_size_t n)
423{ 340{
424 char *d = dst; 341 char *d = dst;
425 342
@@ -430,10 +347,9 @@ _sbus_memcpy_fromio(void *dst, const volatile void __iomem *src,
430 } 347 }
431} 348}
432 349
433#define sbus_memcpy_fromio(d, s, sz) _sbus_memcpy_fromio(d, s, sz)
434 350
435static inline void 351static inline void memcpy_fromio(void *dst, const volatile void __iomem *src,
436_memcpy_fromio(void *dst, const volatile void __iomem *src, __kernel_size_t n) 352 __kernel_size_t n)
437{ 353{
438 char *d = dst; 354 char *d = dst;
439 355
@@ -444,11 +360,8 @@ _memcpy_fromio(void *dst, const volatile void __iomem *src, __kernel_size_t n)
444 } 360 }
445} 361}
446 362
447#define memcpy_fromio(d,s,sz) _memcpy_fromio(d,s,sz) 363static inline void sbus_memcpy_toio(volatile void __iomem *dst, const void *src,
448 364 __kernel_size_t n)
449static inline void
450_sbus_memcpy_toio(volatile void __iomem *dst, const void *src,
451 __kernel_size_t n)
452{ 365{
453 const char *s = src; 366 const char *s = src;
454 volatile void __iomem *d = dst; 367 volatile void __iomem *d = dst;
@@ -460,10 +373,8 @@ _sbus_memcpy_toio(volatile void __iomem *dst, const void *src,
460 } 373 }
461} 374}
462 375
463#define sbus_memcpy_toio(d, s, sz) _sbus_memcpy_toio(d, s, sz) 376static inline void memcpy_toio(volatile void __iomem *dst, const void *src,
464 377 __kernel_size_t n)
465static inline void
466_memcpy_toio(volatile void __iomem *dst, const void *src, __kernel_size_t n)
467{ 378{
468 const char *s = src; 379 const char *s = src;
469 volatile void __iomem *d = dst; 380 volatile void __iomem *d = dst;
@@ -475,8 +386,6 @@ _memcpy_toio(volatile void __iomem *dst, const void *src, __kernel_size_t n)
475 } 386 }
476} 387}
477 388
478#define memcpy_toio(d,s,sz) _memcpy_toio(d,s,sz)
479
480#define mmiowb() 389#define mmiowb()
481 390
482#ifdef __KERNEL__ 391#ifdef __KERNEL__
diff --git a/arch/sparc/kernel/mdesc.c b/arch/sparc/kernel/mdesc.c
index a1a4400d4025..99632a87e697 100644
--- a/arch/sparc/kernel/mdesc.c
+++ b/arch/sparc/kernel/mdesc.c
@@ -906,29 +906,85 @@ void mdesc_fill_in_cpu_data(cpumask_t *mask)
906 smp_fill_in_sib_core_maps(); 906 smp_fill_in_sib_core_maps();
907} 907}
908 908
909static ssize_t mdesc_read(struct file *file, char __user *buf, 909/* mdesc_open() - Grab a reference to mdesc_handle when /dev/mdesc is
910 size_t len, loff_t *offp) 910 * opened. Hold this reference until /dev/mdesc is closed to ensure
911 * mdesc data structure is not released underneath us. Store the
912 * pointer to mdesc structure in private_data for read and seek to use
913 */
914static int mdesc_open(struct inode *inode, struct file *file)
911{ 915{
912 struct mdesc_handle *hp = mdesc_grab(); 916 struct mdesc_handle *hp = mdesc_grab();
913 int err;
914 917
915 if (!hp) 918 if (!hp)
916 return -ENODEV; 919 return -ENODEV;
917 920
918 err = hp->handle_size; 921 file->private_data = hp;
919 if (len < hp->handle_size) 922
920 err = -EMSGSIZE; 923 return 0;
921 else if (copy_to_user(buf, &hp->mdesc, hp->handle_size)) 924}
922 err = -EFAULT; 925
923 mdesc_release(hp); 926static ssize_t mdesc_read(struct file *file, char __user *buf,
927 size_t len, loff_t *offp)
928{
929 struct mdesc_handle *hp = file->private_data;
930 unsigned char *mdesc;
931 int bytes_left, count = len;
932
933 if (*offp >= hp->handle_size)
934 return 0;
935
936 bytes_left = hp->handle_size - *offp;
937 if (count > bytes_left)
938 count = bytes_left;
939
940 mdesc = (unsigned char *)&hp->mdesc;
941 mdesc += *offp;
942 if (!copy_to_user(buf, mdesc, count)) {
943 *offp += count;
944 return count;
945 } else {
946 return -EFAULT;
947 }
948}
924 949
925 return err; 950static loff_t mdesc_llseek(struct file *file, loff_t offset, int whence)
951{
952 struct mdesc_handle *hp;
953
954 switch (whence) {
955 case SEEK_CUR:
956 offset += file->f_pos;
957 break;
958 case SEEK_SET:
959 break;
960 default:
961 return -EINVAL;
962 }
963
964 hp = file->private_data;
965 if (offset > hp->handle_size)
966 return -EINVAL;
967 else
968 file->f_pos = offset;
969
970 return offset;
971}
972
973/* mdesc_close() - /dev/mdesc is being closed, release the reference to
974 * mdesc structure.
975 */
976static int mdesc_close(struct inode *inode, struct file *file)
977{
978 mdesc_release(file->private_data);
979 return 0;
926} 980}
927 981
928static const struct file_operations mdesc_fops = { 982static const struct file_operations mdesc_fops = {
929 .read = mdesc_read, 983 .open = mdesc_open,
930 .owner = THIS_MODULE, 984 .read = mdesc_read,
931 .llseek = noop_llseek, 985 .llseek = mdesc_llseek,
986 .release = mdesc_close,
987 .owner = THIS_MODULE,
932}; 988};
933 989
934static struct miscdevice mdesc_misc = { 990static struct miscdevice mdesc_misc = {
diff --git a/arch/sparc/kernel/unaligned_32.c b/arch/sparc/kernel/unaligned_32.c
index c5c61b3c6b56..32b61d1b6379 100644
--- a/arch/sparc/kernel/unaligned_32.c
+++ b/arch/sparc/kernel/unaligned_32.c
@@ -166,7 +166,7 @@ unsigned long safe_compute_effective_address(struct pt_regs *regs,
166/* This is just to make gcc think panic does return... */ 166/* This is just to make gcc think panic does return... */
167static void unaligned_panic(char *str) 167static void unaligned_panic(char *str)
168{ 168{
169 panic(str); 169 panic("%s", str);
170} 170}
171 171
172/* una_asm.S */ 172/* una_asm.S */
diff --git a/arch/sparc/lib/PeeCeeI.c b/arch/sparc/lib/PeeCeeI.c
index 6529f8657597..e6d183675990 100644
--- a/arch/sparc/lib/PeeCeeI.c
+++ b/arch/sparc/lib/PeeCeeI.c
@@ -15,7 +15,7 @@ void outsb(unsigned long __addr, const void *src, unsigned long count)
15 const u8 *p = src; 15 const u8 *p = src;
16 16
17 while (count--) 17 while (count--)
18 outb(*p++, addr); 18 __raw_writeb(*p++, addr);
19} 19}
20EXPORT_SYMBOL(outsb); 20EXPORT_SYMBOL(outsb);
21 21
@@ -93,21 +93,21 @@ void insb(unsigned long __addr, void *dst, unsigned long count)
93 u8 *pb = dst; 93 u8 *pb = dst;
94 94
95 while ((((unsigned long)pb) & 0x3) && count--) 95 while ((((unsigned long)pb) & 0x3) && count--)
96 *pb++ = inb(addr); 96 *pb++ = __raw_readb(addr);
97 pi = (u32 *)pb; 97 pi = (u32 *)pb;
98 while (count >= 4) { 98 while (count >= 4) {
99 u32 w; 99 u32 w;
100 100
101 w = (inb(addr) << 24); 101 w = (__raw_readb(addr) << 24);
102 w |= (inb(addr) << 16); 102 w |= (__raw_readb(addr) << 16);
103 w |= (inb(addr) << 8); 103 w |= (__raw_readb(addr) << 8);
104 w |= (inb(addr) << 0); 104 w |= (__raw_readb(addr) << 0);
105 *pi++ = w; 105 *pi++ = w;
106 count -= 4; 106 count -= 4;
107 } 107 }
108 pb = (u8 *)pi; 108 pb = (u8 *)pi;
109 while (count--) 109 while (count--)
110 *pb++ = inb(addr); 110 *pb++ = __raw_readb(addr);
111 } 111 }
112} 112}
113EXPORT_SYMBOL(insb); 113EXPORT_SYMBOL(insb);
@@ -121,21 +121,21 @@ void insw(unsigned long __addr, void *dst, unsigned long count)
121 u32 *pi; 121 u32 *pi;
122 122
123 if (((unsigned long)ps) & 0x2) { 123 if (((unsigned long)ps) & 0x2) {
124 *ps++ = le16_to_cpu(inw(addr)); 124 *ps++ = __raw_readw(addr);
125 count--; 125 count--;
126 } 126 }
127 pi = (u32 *)ps; 127 pi = (u32 *)ps;
128 while (count >= 2) { 128 while (count >= 2) {
129 u32 w; 129 u32 w;
130 130
131 w = (le16_to_cpu(inw(addr)) << 16); 131 w = __raw_readw(addr) << 16;
132 w |= (le16_to_cpu(inw(addr)) << 0); 132 w |= __raw_readw(addr) << 0;
133 *pi++ = w; 133 *pi++ = w;
134 count -= 2; 134 count -= 2;
135 } 135 }
136 ps = (u16 *)pi; 136 ps = (u16 *)pi;
137 if (count) 137 if (count)
138 *ps = le16_to_cpu(inw(addr)); 138 *ps = __raw_readw(addr);
139 } 139 }
140} 140}
141EXPORT_SYMBOL(insw); 141EXPORT_SYMBOL(insw);
@@ -148,7 +148,7 @@ void insl(unsigned long __addr, void *dst, unsigned long count)
148 if ((((unsigned long)dst) & 0x3) == 0) { 148 if ((((unsigned long)dst) & 0x3) == 0) {
149 u32 *pi = dst; 149 u32 *pi = dst;
150 while (count--) 150 while (count--)
151 *pi++ = le32_to_cpu(inl(addr)); 151 *pi++ = __raw_readl(addr);
152 } else { 152 } else {
153 u32 l = 0, l2, *pi; 153 u32 l = 0, l2, *pi;
154 u16 *ps; 154 u16 *ps;
@@ -158,11 +158,11 @@ void insl(unsigned long __addr, void *dst, unsigned long count)
158 case 0x2: 158 case 0x2:
159 ps = dst; 159 ps = dst;
160 count -= 1; 160 count -= 1;
161 l = le32_to_cpu(inl(addr)); 161 l = __raw_readl(addr);
162 *ps++ = l; 162 *ps++ = l;
163 pi = (u32 *)ps; 163 pi = (u32 *)ps;
164 while (count--) { 164 while (count--) {
165 l2 = le32_to_cpu(inl(addr)); 165 l2 = __raw_readl(addr);
166 *pi++ = (l << 16) | (l2 >> 16); 166 *pi++ = (l << 16) | (l2 >> 16);
167 l = l2; 167 l = l2;
168 } 168 }
@@ -173,13 +173,13 @@ void insl(unsigned long __addr, void *dst, unsigned long count)
173 case 0x1: 173 case 0x1:
174 pb = dst; 174 pb = dst;
175 count -= 1; 175 count -= 1;
176 l = le32_to_cpu(inl(addr)); 176 l = __raw_readl(addr);
177 *pb++ = l >> 24; 177 *pb++ = l >> 24;
178 ps = (u16 *)pb; 178 ps = (u16 *)pb;
179 *ps++ = ((l >> 8) & 0xffff); 179 *ps++ = ((l >> 8) & 0xffff);
180 pi = (u32 *)ps; 180 pi = (u32 *)ps;
181 while (count--) { 181 while (count--) {
182 l2 = le32_to_cpu(inl(addr)); 182 l2 = __raw_readl(addr);
183 *pi++ = (l << 24) | (l2 >> 8); 183 *pi++ = (l << 24) | (l2 >> 8);
184 l = l2; 184 l = l2;
185 } 185 }
@@ -190,11 +190,11 @@ void insl(unsigned long __addr, void *dst, unsigned long count)
190 case 0x3: 190 case 0x3:
191 pb = (u8 *)dst; 191 pb = (u8 *)dst;
192 count -= 1; 192 count -= 1;
193 l = le32_to_cpu(inl(addr)); 193 l = __raw_readl(addr);
194 *pb++ = l >> 24; 194 *pb++ = l >> 24;
195 pi = (u32 *)pb; 195 pi = (u32 *)pb;
196 while (count--) { 196 while (count--) {
197 l2 = le32_to_cpu(inl(addr)); 197 l2 = __raw_readl(addr);
198 *pi++ = (l << 8) | (l2 >> 24); 198 *pi++ = (l << 8) | (l2 >> 24);
199 l = l2; 199 l = l2;
200 } 200 }
diff --git a/arch/sparc/mm/init_64.c b/arch/sparc/mm/init_64.c
index 2cfb0f25e0ed..cdc9f145e3c3 100644
--- a/arch/sparc/mm/init_64.c
+++ b/arch/sparc/mm/init_64.c
@@ -22,6 +22,7 @@
22#include <linux/kprobes.h> 22#include <linux/kprobes.h>
23#include <linux/cache.h> 23#include <linux/cache.h>
24#include <linux/sort.h> 24#include <linux/sort.h>
25#include <linux/ioport.h>
25#include <linux/percpu.h> 26#include <linux/percpu.h>
26#include <linux/memblock.h> 27#include <linux/memblock.h>
27#include <linux/mmzone.h> 28#include <linux/mmzone.h>
@@ -2708,6 +2709,70 @@ void hugetlb_setup(struct pt_regs *regs)
2708} 2709}
2709#endif 2710#endif
2710 2711
2712static struct resource code_resource = {
2713 .name = "Kernel code",
2714 .flags = IORESOURCE_BUSY | IORESOURCE_MEM
2715};
2716
2717static struct resource data_resource = {
2718 .name = "Kernel data",
2719 .flags = IORESOURCE_BUSY | IORESOURCE_MEM
2720};
2721
2722static struct resource bss_resource = {
2723 .name = "Kernel bss",
2724 .flags = IORESOURCE_BUSY | IORESOURCE_MEM
2725};
2726
2727static inline resource_size_t compute_kern_paddr(void *addr)
2728{
2729 return (resource_size_t) (addr - KERNBASE + kern_base);
2730}
2731
2732static void __init kernel_lds_init(void)
2733{
2734 code_resource.start = compute_kern_paddr(_text);
2735 code_resource.end = compute_kern_paddr(_etext - 1);
2736 data_resource.start = compute_kern_paddr(_etext);
2737 data_resource.end = compute_kern_paddr(_edata - 1);
2738 bss_resource.start = compute_kern_paddr(__bss_start);
2739 bss_resource.end = compute_kern_paddr(_end - 1);
2740}
2741
2742static int __init report_memory(void)
2743{
2744 int i;
2745 struct resource *res;
2746
2747 kernel_lds_init();
2748
2749 for (i = 0; i < pavail_ents; i++) {
2750 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
2751
2752 if (!res) {
2753 pr_warn("Failed to allocate source.\n");
2754 break;
2755 }
2756
2757 res->name = "System RAM";
2758 res->start = pavail[i].phys_addr;
2759 res->end = pavail[i].phys_addr + pavail[i].reg_size - 1;
2760 res->flags = IORESOURCE_BUSY | IORESOURCE_MEM;
2761
2762 if (insert_resource(&iomem_resource, res) < 0) {
2763 pr_warn("Resource insertion failed.\n");
2764 break;
2765 }
2766
2767 insert_resource(res, &code_resource);
2768 insert_resource(res, &data_resource);
2769 insert_resource(res, &bss_resource);
2770 }
2771
2772 return 0;
2773}
2774device_initcall(report_memory);
2775
2711#ifdef CONFIG_SMP 2776#ifdef CONFIG_SMP
2712#define do_flush_tlb_kernel_range smp_flush_tlb_kernel_range 2777#define do_flush_tlb_kernel_range smp_flush_tlb_kernel_range
2713#else 2778#else
@@ -2730,3 +2795,4 @@ void flush_tlb_kernel_range(unsigned long start, unsigned long end)
2730 do_flush_tlb_kernel_range(start, end); 2795 do_flush_tlb_kernel_range(start, end);
2731 } 2796 }
2732} 2797}
2798>>>>>>> c78f77e20d2ba5d4d5e478e85a6fb42556893e2d
diff --git a/drivers/input/misc/sparcspkr.c b/drivers/input/misc/sparcspkr.c
index 65fd3150919b..179ff1cd6f6b 100644
--- a/drivers/input/misc/sparcspkr.c
+++ b/drivers/input/misc/sparcspkr.c
@@ -86,13 +86,13 @@ static int bbc_spkr_event(struct input_dev *dev, unsigned int type, unsigned int
86 spin_lock_irqsave(&state->lock, flags); 86 spin_lock_irqsave(&state->lock, flags);
87 87
88 if (count) { 88 if (count) {
89 outb(0x01, info->regs + 0); 89 sbus_writeb(0x01, info->regs + 0);
90 outb(0x00, info->regs + 2); 90 sbus_writeb(0x00, info->regs + 2);
91 outb((count >> 16) & 0xff, info->regs + 3); 91 sbus_writeb((count >> 16) & 0xff, info->regs + 3);
92 outb((count >> 8) & 0xff, info->regs + 4); 92 sbus_writeb((count >> 8) & 0xff, info->regs + 4);
93 outb(0x00, info->regs + 5); 93 sbus_writeb(0x00, info->regs + 5);
94 } else { 94 } else {
95 outb(0x00, info->regs + 0); 95 sbus_writeb(0x00, info->regs + 0);
96 } 96 }
97 97
98 spin_unlock_irqrestore(&state->lock, flags); 98 spin_unlock_irqrestore(&state->lock, flags);
@@ -123,15 +123,15 @@ static int grover_spkr_event(struct input_dev *dev, unsigned int type, unsigned
123 123
124 if (count) { 124 if (count) {
125 /* enable counter 2 */ 125 /* enable counter 2 */
126 outb(inb(info->enable_reg) | 3, info->enable_reg); 126 sbus_writeb(sbus_readb(info->enable_reg) | 3, info->enable_reg);
127 /* set command for counter 2, 2 byte write */ 127 /* set command for counter 2, 2 byte write */
128 outb(0xB6, info->freq_regs + 1); 128 sbus_writeb(0xB6, info->freq_regs + 1);
129 /* select desired HZ */ 129 /* select desired HZ */
130 outb(count & 0xff, info->freq_regs + 0); 130 sbus_writeb(count & 0xff, info->freq_regs + 0);
131 outb((count >> 8) & 0xff, info->freq_regs + 0); 131 sbus_writeb((count >> 8) & 0xff, info->freq_regs + 0);
132 } else { 132 } else {
133 /* disable counter 2 */ 133 /* disable counter 2 */
134 outb(inb_p(info->enable_reg) & 0xFC, info->enable_reg); 134 sbus_writeb(sbus_readb(info->enable_reg) & 0xFC, info->enable_reg);
135 } 135 }
136 136
137 spin_unlock_irqrestore(&state->lock, flags); 137 spin_unlock_irqrestore(&state->lock, flags);
diff --git a/drivers/sbus/char/display7seg.c b/drivers/sbus/char/display7seg.c
index 7c71e7b4febf..2b0ce7c350ee 100644
--- a/drivers/sbus/char/display7seg.c
+++ b/drivers/sbus/char/display7seg.c
@@ -4,6 +4,7 @@
4 * Copyright (c) 2000 Eric Brower (ebrower@usa.net) 4 * Copyright (c) 2000 Eric Brower (ebrower@usa.net)
5 */ 5 */
6 6
7#include <linux/device.h>
7#include <linux/kernel.h> 8#include <linux/kernel.h>
8#include <linux/module.h> 9#include <linux/module.h>
9#include <linux/fs.h> 10#include <linux/fs.h>
@@ -143,10 +144,7 @@ static long d7s_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
143 144
144 case D7SIOCTM: 145 case D7SIOCTM:
145 /* toggle device mode-- flip display orientation */ 146 /* toggle device mode-- flip display orientation */
146 if (regs & D7S_FLIP) 147 regs ^= D7S_FLIP;
147 regs &= ~D7S_FLIP;
148 else
149 regs |= D7S_FLIP;
150 writeb(regs, p->regs); 148 writeb(regs, p->regs);
151 break; 149 break;
152 } 150 }
@@ -180,7 +178,7 @@ static int d7s_probe(struct platform_device *op)
180 if (d7s_device) 178 if (d7s_device)
181 goto out; 179 goto out;
182 180
183 p = kzalloc(sizeof(*p), GFP_KERNEL); 181 p = devm_kzalloc(&op->dev, sizeof(*p), GFP_KERNEL);
184 err = -ENOMEM; 182 err = -ENOMEM;
185 if (!p) 183 if (!p)
186 goto out; 184 goto out;
@@ -231,7 +229,6 @@ out_iounmap:
231 of_iounmap(&op->resource[0], p->regs, sizeof(u8)); 229 of_iounmap(&op->resource[0], p->regs, sizeof(u8));
232 230
233out_free: 231out_free:
234 kfree(p);
235 goto out; 232 goto out;
236} 233}
237 234
@@ -251,7 +248,6 @@ static int d7s_remove(struct platform_device *op)
251 248
252 misc_deregister(&d7s_miscdev); 249 misc_deregister(&d7s_miscdev);
253 of_iounmap(&op->resource[0], p->regs, sizeof(u8)); 250 of_iounmap(&op->resource[0], p->regs, sizeof(u8));
254 kfree(p);
255 251
256 return 0; 252 return 0;
257} 253}
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-16 13:55:39 -0500