1 files changed, 3 insertions, 32 deletions

diff --git a/arch/sparc/kernel/perf_event.c b/arch/sparc/kernel/perf_event.c
index 86eebfa3b158..59cf917a77b5 100644
--- a/arch/sparc/kernel/perf_event.c
+++ b/arch/sparc/kernel/perf_event.c
@@ -737,25 +737,9 @@ static void sparc_vt_write_pmc(int idx, u64 val)
 {
         u64 pcr;
 
-        /* There seems to be an internal latch on the overflow event
-         * on SPARC-T4 that prevents it from triggering unless you
-         * update the PIC exactly as we do here.  The requirement
-         * seems to be that you have to turn off event counting in the
-         * PCR around the PIC update.
-         *
-         * For example, after the following sequence:
-         *
-         * 1) set PIC to -1
-         * 2) enable event counting and overflow reporting in PCR
-         * 3) overflow triggers, softint 15 handler invoked
-         * 4) clear OV bit in PCR
-         * 5) write PIC to -1
-         *
-         * a subsequent overflow event will not trigger.  This
-         * sequence works on SPARC-T3 and previous chips.
-         */
         pcr = pcr_ops->read_pcr(idx);
-        pcr_ops->write_pcr(idx, PCR_N4_PICNPT);
+        /* ensure ov and ntc are reset */
+        pcr &= ~(PCR_N4_OV | PCR_N4_NTC);
 
         pcr_ops->write_pic(idx, val & 0xffffffff);
 
@@ -792,25 +776,12 @@ static const struct sparc_pmu niagara4_pmu = {
         .num_pic_regs   = 4,
 };
 
-static void sparc_m7_write_pmc(int idx, u64 val)
-{
-        u64 pcr;
-
-        pcr = pcr_ops->read_pcr(idx);
-        /* ensure ov and ntc are reset */
-        pcr &= ~(PCR_N4_OV | PCR_N4_NTC);
-
-        pcr_ops->write_pic(idx, val & 0xffffffff);
-
-        pcr_ops->write_pcr(idx, pcr);
-}
-
 static const struct sparc_pmu sparc_m7_pmu = {
         .event_map      = niagara4_event_map,
         .cache_map      = &niagara4_cache_map,
         .max_events     = ARRAY_SIZE(niagara4_perfmon_event_map),
         .read_pmc       = sparc_vt_read_pmc,
-        .write_pmc      = sparc_m7_write_pmc,
+        .write_pmc      = sparc_vt_write_pmc,
         .upper_shift    = 5,
         .lower_shift    = 5,
         .event_mask     = 0x7ff,