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-rw-r--r--Documentation/Changes11
-rw-r--r--Documentation/DocBook/device-drivers.tmpl2
-rw-r--r--Documentation/devicetree/bindings/arm/arm-boards8
-rw-r--r--Documentation/devicetree/bindings/arm/atmel-aic.txt1
-rw-r--r--Documentation/devicetree/bindings/arm/atmel-at91.txt3
-rw-r--r--Documentation/devicetree/bindings/arm/moxart.txt12
-rw-r--r--Documentation/devicetree/bindings/arm/omap/mpu.txt8
-rw-r--r--Documentation/devicetree/bindings/arm/pmu.txt1
-rw-r--r--Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt2
-rw-r--r--Documentation/devicetree/bindings/arm/samsung/sysreg.txt7
-rw-r--r--Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt1
-rw-r--r--Documentation/devicetree/bindings/clock/at91-clock.txt339
-rw-r--r--Documentation/devicetree/bindings/clock/exynos4-clock.txt2
-rw-r--r--Documentation/devicetree/bindings/clock/exynos5250-clock.txt2
-rw-r--r--Documentation/devicetree/bindings/clock/exynos5420-clock.txt2
-rw-r--r--Documentation/devicetree/bindings/clock/exynos5440-clock.txt2
-rw-r--r--Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt4
-rw-r--r--Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt63
-rw-r--r--Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt4
-rw-r--r--Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt4
-rw-r--r--Documentation/devicetree/bindings/dma/ste-dma40.txt3
-rw-r--r--Documentation/devicetree/bindings/dma/tegra20-apbdma.txt14
-rw-r--r--Documentation/devicetree/bindings/gpio/8xxx_gpio.txt66
-rw-r--r--Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt122
-rw-r--r--Documentation/devicetree/bindings/i2c/i2c-omap.txt3
-rw-r--r--Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt27
-rw-r--r--Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt9
-rw-r--r--Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt2
-rw-r--r--Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt9
-rw-r--r--Documentation/devicetree/bindings/mmc/ti-omap.txt54
-rw-r--r--Documentation/devicetree/bindings/net/fsl-fec.txt2
-rw-r--r--Documentation/devicetree/bindings/nvec/nvidia,nvec.txt12
-rw-r--r--Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt26
-rw-r--r--Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt9
-rw-r--r--Documentation/devicetree/bindings/rng/qcom,prng.txt17
-rw-r--r--Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt3
-rw-r--r--Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt19
-rw-r--r--Documentation/devicetree/bindings/sound/nvidia,tegra-audio-alc5632.txt7
-rw-r--r--Documentation/devicetree/bindings/sound/nvidia,tegra-audio-rt5640.txt7
-rw-r--r--Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8753.txt7
-rw-r--r--Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8903.txt7
-rw-r--r--Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm9712.txt7
-rw-r--r--Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt20
-rw-r--r--Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt19
-rw-r--r--Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt63
-rw-r--r--Documentation/devicetree/bindings/sound/nvidia,tegra30-i2s.txt11
-rw-r--r--Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt24
-rw-r--r--Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt20
-rw-r--r--Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt20
-rw-r--r--Documentation/devicetree/bindings/spi/nvidia,tegra20-spi.txt5
-rw-r--r--Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt3
-rw-r--r--Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt3
-rw-r--r--Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt54
-rw-r--r--Documentation/devicetree/bindings/usb/keystone-phy.txt20
-rw-r--r--Documentation/devicetree/bindings/usb/keystone-usb.txt42
-rw-r--r--Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt7
-rw-r--r--Documentation/devicetree/bindings/vendor-prefixes.txt2
-rw-r--r--Documentation/gpio/00-INDEX14
-rw-r--r--Documentation/gpio/board.txt115
-rw-r--r--Documentation/gpio/consumer.txt197
-rw-r--r--Documentation/gpio/driver.txt75
-rw-r--r--Documentation/gpio/gpio-legacy.txt (renamed from Documentation/gpio.txt)0
-rw-r--r--Documentation/gpio/gpio.txt119
-rw-r--r--Documentation/gpio/sysfs.txt155
-rw-r--r--MAINTAINERS23
-rw-r--r--Makefile2
-rw-r--r--arch/arm/Kconfig14
-rw-r--r--arch/arm/Makefile1
-rw-r--r--arch/arm/boot/compressed/Makefile2
-rw-r--r--arch/arm/boot/dts/Makefile7
-rw-r--r--arch/arm/boot/dts/am335x-base0033.dts79
-rw-r--r--arch/arm/boot/dts/am335x-igep0033.dtsi29
-rw-r--r--arch/arm/boot/dts/animeo_ip.dts31
-rw-r--r--arch/arm/boot/dts/armada-370-db.dts28
-rw-r--r--arch/arm/boot/dts/armada-370-xp.dtsi2
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78230.dtsi24
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78260.dtsi109
-rw-r--r--arch/arm/boot/dts/at91-cosino.dtsi122
-rw-r--r--arch/arm/boot/dts/at91-cosino_mega2560.dts84
-rw-r--r--arch/arm/boot/dts/at91rm9200.dtsi4
-rw-r--r--arch/arm/boot/dts/at91rm9200ek.dts57
-rw-r--r--arch/arm/boot/dts/at91sam9263.dtsi46
-rw-r--r--arch/arm/boot/dts/at91sam9263ek.dts30
-rw-r--r--arch/arm/boot/dts/at91sam9g45.dtsi76
-rw-r--r--arch/arm/boot/dts/at91sam9m10g45ek.dts54
-rw-r--r--arch/arm/boot/dts/at91sam9n12.dtsi9
-rw-r--r--arch/arm/boot/dts/at91sam9x5.dtsi9
-rw-r--r--arch/arm/boot/dts/at91sam9x5_usart3.dtsi4
-rw-r--r--arch/arm/boot/dts/bcm2835.dtsi4
-rw-r--r--arch/arm/boot/dts/emev2-kzm9d.dts42
-rw-r--r--arch/arm/boot/dts/emev2.dtsi116
-rw-r--r--arch/arm/boot/dts/exynos4.dtsi6
-rw-r--r--arch/arm/boot/dts/exynos4210-origen.dts2
-rw-r--r--arch/arm/boot/dts/exynos4210.dtsi23
-rw-r--r--arch/arm/boot/dts/exynos4212.dtsi24
-rw-r--r--arch/arm/boot/dts/exynos4412-odroidx.dts5
-rw-r--r--arch/arm/boot/dts/exynos4412-origen.dts7
-rw-r--r--arch/arm/boot/dts/exynos4412-trats2.dts20
-rw-r--r--arch/arm/boot/dts/exynos4412.dtsi35
-rw-r--r--arch/arm/boot/dts/exynos4x12.dtsi33
-rw-r--r--arch/arm/boot/dts/exynos5.dtsi25
-rw-r--r--arch/arm/boot/dts/exynos5250-arndale.dts64
-rw-r--r--arch/arm/boot/dts/exynos5250-cros-common.dtsi (renamed from arch/arm/boot/dts/cros5250-common.dtsi)46
-rw-r--r--arch/arm/boot/dts/exynos5250-smdk5250.dts62
-rw-r--r--arch/arm/boot/dts/exynos5250-snow.dts16
-rw-r--r--arch/arm/boot/dts/exynos5250.dtsi60
-rw-r--r--arch/arm/boot/dts/exynos5420-pinctrl.dtsi2
-rw-r--r--arch/arm/boot/dts/exynos5420-smdk5420.dts33
-rw-r--r--arch/arm/boot/dts/exynos5420.dtsi346
-rw-r--r--arch/arm/boot/dts/exynos5440.dtsi2
-rw-r--r--arch/arm/boot/dts/imx6qdl.dtsi2
-rw-r--r--arch/arm/boot/dts/integrator.dtsi5
-rw-r--r--arch/arm/boot/dts/k2hk-evm.dts63
-rw-r--r--arch/arm/boot/dts/keystone-clocks.dtsi36
-rw-r--r--arch/arm/boot/dts/keystone.dtsi (renamed from arch/arm/boot/dts/keystone.dts)35
-rw-r--r--arch/arm/boot/dts/moxart-uc7112lx.dts109
-rw-r--r--arch/arm/boot/dts/moxart.dtsi154
-rw-r--r--arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi4
-rw-r--r--arch/arm/boot/dts/omap-zoom-common.dtsi2
-rw-r--r--arch/arm/boot/dts/omap2.dtsi96
-rw-r--r--arch/arm/boot/dts/omap2420.dtsi23
-rw-r--r--arch/arm/boot/dts/omap2430.dtsi49
-rw-r--r--arch/arm/boot/dts/omap3-beagle-xm.dts7
-rw-r--r--arch/arm/boot/dts/omap3-beagle.dts21
-rw-r--r--arch/arm/boot/dts/omap3-igep.dtsi85
-rw-r--r--arch/arm/boot/dts/omap3-igep0020.dts50
-rw-r--r--arch/arm/boot/dts/omap3-igep0030.dts4
-rw-r--r--arch/arm/boot/dts/omap3-n900.dts23
-rw-r--r--arch/arm/boot/dts/omap3.dtsi42
-rw-r--r--arch/arm/boot/dts/omap4-panda-common.dtsi20
-rw-r--r--arch/arm/boot/dts/omap4-sdp.dts12
-rw-r--r--arch/arm/boot/dts/pxa27x.dtsi24
-rw-r--r--arch/arm/boot/dts/qcom-msm8974.dtsi97
-rw-r--r--arch/arm/boot/dts/r7s72100-genmai.dts2
-rw-r--r--arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts15
-rw-r--r--arch/arm/boot/dts/r8a73a4-ape6evm.dts10
-rw-r--r--arch/arm/boot/dts/r8a73a4.dtsi168
-rw-r--r--arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts50
-rw-r--r--arch/arm/boot/dts/r8a7740-armadillo800eva.dts2
-rw-r--r--arch/arm/boot/dts/r8a7740.dtsi135
-rw-r--r--arch/arm/boot/dts/r8a7778-bockw-reference.dts57
-rw-r--r--arch/arm/boot/dts/r8a7778-bockw.dts2
-rw-r--r--arch/arm/boot/dts/r8a7778.dtsi172
-rw-r--r--arch/arm/boot/dts/r8a7779-marzen-reference.dts36
-rw-r--r--arch/arm/boot/dts/r8a7779-marzen.dts2
-rw-r--r--arch/arm/boot/dts/r8a7779.dtsi114
-rw-r--r--arch/arm/boot/dts/r8a7790-lager-reference.dts46
-rw-r--r--arch/arm/boot/dts/r8a7790-lager.dts7
-rw-r--r--arch/arm/boot/dts/r8a7790.dtsi73
-rw-r--r--arch/arm/boot/dts/r8a7791-koelsch-reference.dts115
-rw-r--r--arch/arm/boot/dts/r8a7791-koelsch.dts2
-rw-r--r--arch/arm/boot/dts/r8a7791.dtsi144
-rw-r--r--arch/arm/boot/dts/sama5d3.dtsi423
-rw-r--r--arch/arm/boot/dts/sama5d36.dtsi20
-rw-r--r--arch/arm/boot/dts/sama5d36ek.dts53
-rw-r--r--arch/arm/boot/dts/sama5d3_can.dtsi20
-rw-r--r--arch/arm/boot/dts/sama5d3_emac.dtsi11
-rw-r--r--arch/arm/boot/dts/sama5d3_gmac.dtsi11
-rw-r--r--arch/arm/boot/dts/sama5d3_lcd.dtsi17
-rw-r--r--arch/arm/boot/dts/sama5d3_mci2.dtsi12
-rw-r--r--arch/arm/boot/dts/sama5d3_tcb1.dtsi12
-rw-r--r--arch/arm/boot/dts/sama5d3_uart.dtsi26
-rw-r--r--arch/arm/boot/dts/sama5d3xcm.dtsi17
-rw-r--r--arch/arm/boot/dts/sama5d3xdm.dtsi1
-rw-r--r--arch/arm/boot/dts/sh7372-mackerel.dts2
-rw-r--r--arch/arm/boot/dts/sh73a0-kzm9g-reference.dts103
-rw-r--r--arch/arm/boot/dts/sh73a0-kzm9g.dts2
-rw-r--r--arch/arm/boot/dts/sh73a0.dtsi159
-rw-r--r--arch/arm/boot/dts/socfpga.dtsi7
-rw-r--r--arch/arm/boot/dts/st-pincfg.h2
-rw-r--r--arch/arm/boot/dts/ste-dbx5x0.dtsi32
-rw-r--r--arch/arm/boot/dts/ste-href-family-pinctrl.dtsi745
-rw-r--r--arch/arm/boot/dts/ste-href-stuib.dtsi41
-rw-r--r--arch/arm/boot/dts/ste-href-tvk1281618.dtsi90
-rw-r--r--arch/arm/boot/dts/ste-href.dtsi78
-rw-r--r--arch/arm/boot/dts/ste-hrefprev60.dtsi73
-rw-r--r--arch/arm/boot/dts/ste-hrefv60plus.dtsi217
-rw-r--r--arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi80
-rw-r--r--arch/arm/boot/dts/ste-nomadik-s8815.dts4
-rw-r--r--arch/arm/boot/dts/ste-nomadik-stn8815.dtsi4
-rw-r--r--arch/arm/boot/dts/ste-snowball.dts225
-rw-r--r--arch/arm/boot/dts/stih415-pinctrl.dtsi36
-rw-r--r--arch/arm/boot/dts/stih415.dtsi53
-rw-r--r--arch/arm/boot/dts/stih416-pinctrl.dtsi35
-rw-r--r--arch/arm/boot/dts/stih416.dtsi53
-rw-r--r--arch/arm/boot/dts/stih41x-b2000.dtsi9
-rw-r--r--arch/arm/boot/dts/stih41x-b2020.dtsi22
-rw-r--r--arch/arm/boot/dts/tegra114-dalmore.dts630
-rw-r--r--arch/arm/boot/dts/tegra114.dtsi295
-rw-r--r--arch/arm/boot/dts/tegra124-venice2.dts1064
-rw-r--r--arch/arm/boot/dts/tegra124.dtsi418
-rw-r--r--arch/arm/boot/dts/tegra20-colibri-512.dtsi205
-rw-r--r--arch/arm/boot/dts/tegra20-harmony.dts316
-rw-r--r--arch/arm/boot/dts/tegra20-iris-512.dts30
-rw-r--r--arch/arm/boot/dts/tegra20-medcom-wide.dts2
-rw-r--r--arch/arm/boot/dts/tegra20-paz00.dts52
-rw-r--r--arch/arm/boot/dts/tegra20-plutux.dts4
-rw-r--r--arch/arm/boot/dts/tegra20-seaboard.dts353
-rw-r--r--arch/arm/boot/dts/tegra20-tamonten.dtsi47
-rw-r--r--arch/arm/boot/dts/tegra20-tec.dts6
-rw-r--r--arch/arm/boot/dts/tegra20-trimslice.dts54
-rw-r--r--arch/arm/boot/dts/tegra20-ventana.dts62
-rw-r--r--arch/arm/boot/dts/tegra20-whistler.dts84
-rw-r--r--arch/arm/boot/dts/tegra20.dtsi191
-rw-r--r--arch/arm/boot/dts/tegra30-beaver.dts126
-rw-r--r--arch/arm/boot/dts/tegra30-cardhu-a02.dts14
-rw-r--r--arch/arm/boot/dts/tegra30-cardhu-a04.dts14
-rw-r--r--arch/arm/boot/dts/tegra30-cardhu.dtsi104
-rw-r--r--arch/arm/boot/dts/tegra30.dtsi247
-rw-r--r--arch/arm/boot/dts/zynq-7000.dtsi39
-rw-r--r--arch/arm/boot/dts/zynq-zc702.dts5
-rw-r--r--arch/arm/boot/dts/zynq-zc706.dts5
-rw-r--r--arch/arm/boot/dts/zynq-zed.dts5
-rw-r--r--arch/arm/configs/ape6evm_defconfig2
-rw-r--r--arch/arm/configs/armadillo800eva_defconfig2
-rw-r--r--arch/arm/configs/bockw_defconfig2
-rw-r--r--arch/arm/configs/koelsch_defconfig2
-rw-r--r--arch/arm/configs/kzm9d_defconfig2
-rw-r--r--arch/arm/configs/kzm9g_defconfig2
-rw-r--r--arch/arm/configs/lager_defconfig2
-rw-r--r--arch/arm/configs/mackerel_defconfig2
-rw-r--r--arch/arm/configs/marzen_defconfig2
-rw-r--r--arch/arm/configs/multi_v7_defconfig3
-rw-r--r--arch/arm/configs/omap2plus_defconfig1
-rw-r--r--arch/arm/configs/sunxi_defconfig7
-rw-r--r--arch/arm/configs/u8500_defconfig3
-rw-r--r--arch/arm/include/asm/pgtable.h2
-rw-r--r--arch/arm/kernel/machine_kexec.c17
-rw-r--r--arch/arm/kernel/relocate_kernel.S8
-rw-r--r--arch/arm/kernel/sigreturn_codes.S40
-rw-r--r--arch/arm/lib/delay-loop.S1
-rw-r--r--arch/arm/mach-at91/Kconfig43
-rw-r--r--arch/arm/mach-at91/Kconfig.non_dt6
-rw-r--r--arch/arm/mach-at91/Makefile2
-rw-r--r--arch/arm/mach-at91/at91rm9200.c2
-rw-r--r--arch/arm/mach-at91/at91rm9200_time.c7
-rw-r--r--arch/arm/mach-at91/at91sam9260.c2
-rw-r--r--arch/arm/mach-at91/at91sam9261.c2
-rw-r--r--arch/arm/mach-at91/at91sam9263.c2
-rw-r--r--arch/arm/mach-at91/at91sam926x_time.c14
-rw-r--r--arch/arm/mach-at91/at91sam9g45.c2
-rw-r--r--arch/arm/mach-at91/at91sam9n12.c2
-rw-r--r--arch/arm/mach-at91/at91sam9rl.c2
-rw-r--r--arch/arm/mach-at91/at91sam9x5.c2
-rw-r--r--arch/arm/mach-at91/board-dt-sama5.c10
-rw-r--r--arch/arm/mach-at91/clock.c7
-rw-r--r--arch/arm/mach-at91/generic.h3
-rw-r--r--arch/arm/mach-at91/pm.c2
-rw-r--r--arch/arm/mach-at91/pm.h4
-rw-r--r--arch/arm/mach-at91/pm_slowclock.S2
-rw-r--r--arch/arm/mach-at91/sama5d3.c344
-rw-r--r--arch/arm/mach-at91/setup.c8
-rw-r--r--arch/arm/mach-dove/common.c15
-rw-r--r--arch/arm/mach-footbridge/common.c3
-rw-r--r--arch/arm/mach-footbridge/dc21285.c2
-rw-r--r--arch/arm/mach-footbridge/ebsa285.c22
-rw-r--r--arch/arm/mach-integrator/integrator_ap.c60
-rw-r--r--arch/arm/mach-integrator/integrator_cp.c14
-rw-r--r--arch/arm/mach-kirkwood/board-dt.c40
-rw-r--r--arch/arm/mach-msm/Kconfig15
-rw-r--r--arch/arm/mach-msm/board-trout.c12
-rw-r--r--arch/arm/mach-mvebu/coherency.c1
-rw-r--r--arch/arm/mach-mvebu/coherency.h4
-rw-r--r--arch/arm/mach-mvebu/common.h1
-rw-r--r--arch/arm/mach-mvebu/hotplug.c1
-rw-r--r--arch/arm/mach-mvebu/platsmp.c4
-rw-r--r--arch/arm/mach-mvebu/pmsu.c3
-rw-r--r--arch/arm/mach-mvebu/system-controller.c5
-rw-r--r--arch/arm/mach-nomadik/cpu-8815.c32
-rw-r--r--arch/arm/mach-omap2/Makefile6
-rw-r--r--arch/arm/mach-omap2/common.h1
-rw-r--r--arch/arm/mach-omap2/display.c78
-rw-r--r--arch/arm/mach-omap2/dss-common.c2
-rw-r--r--arch/arm/mach-omap2/gpmc.c58
-rw-r--r--arch/arm/mach-omap2/omap-secure.h7
-rw-r--r--arch/arm/mach-omap2/omap4-common.c57
-rw-r--r--arch/arm/mach-omap2/pdata-quirks.c1
-rw-r--r--arch/arm/mach-omap2/pm34xx.c2
-rw-r--r--arch/arm/mach-omap2/powerdomain.c3
-rw-r--r--arch/arm/mach-omap2/prm44xx_54xx.h2
-rw-r--r--arch/arm/mach-orion5x/board-dt.c2
-rw-r--r--arch/arm/mach-orion5x/common.c7
-rw-r--r--arch/arm/mach-orion5x/db88f5281-setup.c2
-rw-r--r--arch/arm/mach-orion5x/irq.c1
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-rw-r--r--drivers/net/ethernet/sfc/mcdi_mon.c78
-rw-r--r--drivers/net/ethernet/smsc/smc91x.h22
-rw-r--r--drivers/net/ethernet/via/via-velocity.c11
-rw-r--r--drivers/net/macvtap.c12
-rw-r--r--drivers/net/phy/vitesse.c15
-rw-r--r--drivers/net/team/team.c4
-rw-r--r--drivers/net/virtio_net.c136
-rw-r--r--drivers/net/xen-netback/netback.c1
-rw-r--r--drivers/ntb/ntb_hw.c121
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-rw-r--r--drivers/ntb/ntb_transport.c77
-rw-r--r--drivers/pci/host/pci-tegra.c53
-rw-r--r--drivers/pci/quirks.c4
-rw-r--r--drivers/pinctrl/pinctrl-abx500.c6
-rw-r--r--drivers/pinctrl/pinctrl-abx500.h2
-rw-r--r--drivers/pinctrl/pinctrl-nomadik.c296
-rw-r--r--drivers/pinctrl/pinctrl-nomadik.h14
-rw-r--r--drivers/pinctrl/pinctrl-rockchip.c5
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-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7372.c2
-rw-r--r--drivers/platform/Kconfig1
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-rw-r--r--drivers/platform/chrome/Kconfig28
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-rw-r--r--drivers/platform/chrome/chromeos_laptop.c (renamed from drivers/platform/x86/chromeos_laptop.c)0
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-rw-r--r--drivers/platform/x86/asus-laptop.c5
-rw-r--r--drivers/platform/x86/dell-laptop.c288
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-rw-r--r--drivers/platform/x86/intel_scu_ipc.c117
-rw-r--r--drivers/platform/x86/panasonic-laptop.c5
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-rw-r--r--drivers/platform/x86/topstar-laptop.c4
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-rw-r--r--drivers/pnp/driver.c12
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-rw-r--r--drivers/s390/block/dasd_eckd.c2
-rw-r--r--drivers/scsi/3w-9xxx.c3
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-rw-r--r--drivers/scsi/bfa/bfad_attr.c7
-rw-r--r--drivers/scsi/gdth.c1
-rw-r--r--drivers/scsi/hosts.c1
-rw-r--r--drivers/scsi/hpsa.c5
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-rw-r--r--drivers/scsi/ips.c1
-rw-r--r--drivers/scsi/libsas/sas_ata.c2
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-rw-r--r--drivers/scsi/megaraid/megaraid_mbox.c1
-rw-r--r--drivers/scsi/megaraid/megaraid_sas_base.c1
-rw-r--r--drivers/scsi/pm8001/pm8001_hwi.c2
-rw-r--r--drivers/scsi/pm8001/pm8001_hwi.h4
-rw-r--r--drivers/scsi/pm8001/pm8001_init.c91
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-rw-r--r--drivers/spi/spi-bcm2835.c2
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-rw-r--r--drivers/spi/spi-mxs.c2
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-rw-r--r--drivers/spi/spi-rspi.c3
-rw-r--r--drivers/spi/spi-tegra114.c66
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-rw-r--r--drivers/spi/spi-ti-qspi.c23
-rw-r--r--drivers/spi/spi-txx9.c2
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-rw-r--r--drivers/staging/btmtk_usb/btmtk_usb.c3
-rw-r--r--drivers/staging/comedi/drivers/pcl730.c6
-rw-r--r--drivers/staging/comedi/drivers/s626.c2
-rw-r--r--drivers/staging/comedi/drivers/vmk80xx.c2
-rw-r--r--drivers/staging/ft1000/ft1000-usb/ft1000_download.c3
-rw-r--r--drivers/staging/iio/magnetometer/Kconfig2
-rw-r--r--drivers/staging/imx-drm/Makefile4
-rw-r--r--drivers/staging/imx-drm/imx-drm-core.c1
-rw-r--r--drivers/staging/lustre/lustre/ptlrpc/pinger.c4
-rw-r--r--drivers/staging/media/go7007/go7007-usb.c28
-rw-r--r--drivers/staging/nvec/nvec.c14
-rw-r--r--drivers/staging/nvec/nvec.h5
-rw-r--r--drivers/staging/rtl8188eu/core/rtw_ap.c3
-rw-r--r--drivers/staging/tidspbridge/Kconfig2
-rw-r--r--drivers/staging/vt6655/hostap.c3
-rw-r--r--drivers/staging/vt6656/baseband.c11
-rw-r--r--drivers/staging/vt6656/hostap.c3
-rw-r--r--drivers/staging/vt6656/rndis.h2
-rw-r--r--drivers/staging/zram/zram_drv.c19
-rw-r--r--drivers/staging/zsmalloc/zsmalloc-main.c17
-rw-r--r--drivers/tty/amiserial.c3
-rw-r--r--drivers/tty/n_tty.c16
-rw-r--r--drivers/tty/serial/8250/Kconfig2
-rw-r--r--drivers/tty/serial/pmac_zilog.c3
-rw-r--r--drivers/tty/serial/serial-tegra.c38
-rw-r--r--drivers/tty/tty_io.c1
-rw-r--r--drivers/uio/uio.c2
-rw-r--r--drivers/usb/gadget/atmel_usba_udc.c2
-rw-r--r--drivers/usb/host/ehci-tegra.c14
-rw-r--r--drivers/video/atmel_lcdfb.c1
-rw-r--r--drivers/video/kyro/fbdev.c6
-rw-r--r--drivers/video/omap2/displays-new/panel-sony-acx565akm.c5
-rw-r--r--drivers/video/sh_mobile_meram.c2
-rw-r--r--drivers/video/vt8500lcdfb.c25
-rw-r--r--drivers/xen/grant-table.c6
-rw-r--r--drivers/xen/swiotlb-xen.c5
-rw-r--r--fs/affs/Changes2
-rw-r--r--fs/aio.c8
-rw-r--r--fs/btrfs/check-integrity.c32
-rw-r--r--fs/btrfs/check-integrity.h2
-rw-r--r--fs/btrfs/extent_io.c12
-rw-r--r--fs/btrfs/scrub.c33
-rw-r--r--fs/ceph/addr.c2
-rw-r--r--fs/ceph/cache.c3
-rw-r--r--fs/ceph/caps.c27
-rw-r--r--fs/ceph/dir.c11
-rw-r--r--fs/ceph/inode.c49
-rw-r--r--fs/ceph/mds_client.c61
-rw-r--r--fs/ceph/mds_client.h1
-rw-r--r--fs/ceph/super.h8
-rw-r--r--fs/cifs/cifsglob.h1
-rw-r--r--fs/cifs/ioctl.c6
-rw-r--r--fs/cifs/smb2ops.c99
-rw-r--r--fs/cifs/smb2pdu.c92
-rw-r--r--fs/cifs/smb2pdu.h12
-rw-r--r--fs/cifs/smb2proto.h1
-rw-r--r--fs/cifs/smbfsctl.h2
-rw-r--r--fs/eventpoll.c3
-rw-r--r--fs/hfsplus/wrapper.c17
-rw-r--r--fs/logfs/dev_bdev.c13
-rw-r--r--fs/namei.c3
-rw-r--r--fs/nfs/blocklayout/blocklayout.h1
-rw-r--r--fs/nfs/blocklayout/extents.c2
-rw-r--r--fs/nfs/dns_resolve.c2
-rw-r--r--fs/nfs/inode.c2
-rw-r--r--fs/nfs/internal.h15
-rw-r--r--fs/nfs/nfs4_fs.h8
-rw-r--r--fs/nfs/nfs4proc.c30
-rw-r--r--fs/pipe.c39
-rw-r--r--fs/squashfs/file_direct.c5
-rw-r--r--fs/sysfs/file.c22
-rw-r--r--include/acpi/acconfig.h2
-rw-r--r--include/acpi/acpi_bus.h1
-rw-r--r--include/acpi/acpixf.h2
-rw-r--r--include/asm-generic/simd.h14
-rw-r--r--include/crypto/ablk_helper.h (renamed from arch/x86/include/asm/crypto/ablk_helper.h)0
-rw-r--r--include/crypto/algapi.h18
-rw-r--r--include/crypto/authenc.h12
-rw-r--r--include/crypto/scatterwalk.h1
-rw-r--r--include/dt-bindings/clk/at91.h22
-rw-r--r--include/dt-bindings/clock/tegra114-car.h8
-rw-r--r--include/dt-bindings/clock/tegra124-car.h341
-rw-r--r--include/dt-bindings/clock/tegra20-car.h2
-rw-r--r--include/dt-bindings/clock/tegra30-car.h12
-rw-r--r--include/dt-bindings/gpio/tegra-gpio.h1
-rw-r--r--include/dt-bindings/pinctrl/pinctrl-tegra.h45
-rw-r--r--include/linux/clk/at91_pmc.h (renamed from arch/arm/mach-at91/include/mach/at91_pmc.h)4
-rw-r--r--include/linux/clk/tegra.h7
-rw-r--r--include/linux/cpufreq.h8
-rw-r--r--include/linux/dmaengine.h9
-rw-r--r--include/linux/efi.h4
-rw-r--r--include/linux/ftrace_event.h16
-rw-r--r--include/linux/gpio/driver.h14
-rw-r--r--include/linux/hid-sensor-hub.h3
-rw-r--r--include/linux/irqreturn.h2
-rw-r--r--include/linux/nfs4.h10
-rw-r--r--include/linux/nfs_fs.h18
-rw-r--r--include/linux/padata.h3
-rw-r--r--include/linux/platform_data/clocksource-nomadik-mtu.h9
-rw-r--r--include/linux/platform_data/pinctrl-nomadik.h242
-rw-r--r--include/linux/sched.h2
-rw-r--r--include/linux/slab.h102
-rw-r--r--include/linux/tegra-powergate.h32
-rw-r--r--include/linux/tracepoint.h4
-rw-r--r--include/net/ip.h2
-rw-r--r--include/net/ipv6.h6
-rw-r--r--include/net/ping.h3
-rw-r--r--include/net/sctp/structs.h1
-rw-r--r--include/scsi/scsi_host.h6
-rw-r--r--include/sound/dmaengine_pcm.h10
-rw-r--r--include/sound/soc-dapm.h3
-rw-r--r--include/trace/ftrace.h12
-rw-r--r--include/uapi/linux/eventpoll.h13
-rw-r--r--include/uapi/linux/genetlink.h1
-rw-r--r--include/uapi/linux/if_link.h4
-rw-r--r--include/uapi/linux/netlink_diag.h1
-rw-r--r--include/uapi/linux/packet_diag.h1
-rw-r--r--include/uapi/linux/unix_diag.h1
-rw-r--r--kernel/cgroup.c35
-rw-r--r--kernel/cpuset.c8
-rw-r--r--kernel/events/core.c8
-rw-r--r--kernel/extable.c4
-rw-r--r--kernel/irq/pm.c2
-rw-r--r--kernel/padata.c9
-rw-r--r--kernel/rcu/tree_plugin.h4
-rw-r--r--kernel/sched/core.c8
-rw-r--r--kernel/sched/fair.c27
-rw-r--r--kernel/time/tick-common.c15
-rw-r--r--kernel/time/tick-sched.c25
-rw-r--r--kernel/time/timekeeping.c2
-rw-r--r--kernel/timer.c5
-rw-r--r--kernel/trace/ftrace.c64
-rw-r--r--kernel/trace/trace_event_perf.c8
-rw-r--r--kernel/trace/trace_events.c3
-rw-r--r--kernel/trace/trace_syscalls.c10
-rw-r--r--kernel/workqueue.c50
-rw-r--r--lib/lockref.c9
-rw-r--r--net/compat.c2
-rw-r--r--net/core/pktgen.c7
-rw-r--r--net/hsr/hsr_framereg.c3
-rw-r--r--net/hsr/hsr_netlink.c28
-rw-r--r--net/ipv4/ip_sockglue.c3
-rw-r--r--net/ipv4/ping.c7
-rw-r--r--net/ipv4/protocol.c8
-rw-r--r--net/ipv4/raw.c2
-rw-r--r--net/ipv4/tcp_ipv4.c2
-rw-r--r--net/ipv4/tcp_memcontrol.c2
-rw-r--r--net/ipv4/tcp_offload.c31
-rw-r--r--net/ipv4/udp.c7
-rw-r--r--net/ipv6/datagram.c8
-rw-r--r--net/ipv6/ip6_output.c4
-rw-r--r--net/ipv6/ping.c3
-rw-r--r--net/ipv6/protocol.c4
-rw-r--r--net/ipv6/raw.c4
-rw-r--r--net/ipv6/sit.c50
-rw-r--r--net/ipv6/tcpv6_offload.c32
-rw-r--r--net/ipv6/udp.c4
-rw-r--r--net/l2tp/l2tp_ip6.c2
-rw-r--r--net/netlink/genetlink.c13
-rw-r--r--net/packet/af_packet.c4
-rw-r--r--net/sched/sch_netem.c7
-rw-r--r--net/sched/sch_tbf.c32
-rw-r--r--net/sctp/output.c3
-rw-r--r--net/sctp/outqueue.c6
-rw-r--r--net/socket.c2
-rw-r--r--net/sunrpc/auth_gss/auth_gss.c2
-rwxr-xr-xscripts/recordmcount.pl3
-rw-r--r--security/integrity/digsig.c30
-rw-r--r--security/integrity/ima/Kconfig8
-rw-r--r--security/integrity/ima/ima.h7
-rw-r--r--security/integrity/ima/ima_api.c22
-rw-r--r--security/integrity/ima/ima_appraise.c11
-rw-r--r--security/integrity/ima/ima_crypto.c17
-rw-r--r--security/integrity/ima/ima_fs.c14
-rw-r--r--security/integrity/ima/ima_init.c3
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-rw-r--r--security/integrity/ima/ima_template_lib.c6
-rw-r--r--security/integrity/integrity.h7
-rw-r--r--sound/atmel/abdac.c3
-rw-r--r--sound/firewire/amdtp.c15
-rw-r--r--sound/firewire/dice.c4
-rw-r--r--sound/pci/hda/hda_codec.h1
-rw-r--r--sound/pci/hda/hda_generic.c79
-rw-r--r--sound/pci/hda/hda_intel.c12
-rw-r--r--sound/pci/hda/patch_analog.c6
-rw-r--r--sound/pci/hda/patch_conexant.c23
-rw-r--r--sound/pci/hda/patch_hdmi.c27
-rw-r--r--sound/pci/hda/patch_realtek.c130
-rw-r--r--sound/pci/hda/patch_sigmatel.c3
-rw-r--r--sound/soc/atmel/sam9x5_wm8731.c2
-rw-r--r--sound/soc/codecs/wm5110.c25
-rw-r--r--sound/soc/codecs/wm8731.c4
-rw-r--r--sound/soc/codecs/wm8990.c2
-rw-r--r--sound/soc/fsl/pcm030-audio-fabric.c3
-rw-r--r--sound/soc/kirkwood/kirkwood-i2s.c22
-rw-r--r--sound/soc/omap/n810.c4
-rw-r--r--sound/soc/sh/Kconfig1
-rw-r--r--sound/soc/soc-core.c4
-rw-r--r--sound/soc/soc-devres.c45
-rw-r--r--sound/soc/soc-generic-dmaengine-pcm.c94
-rw-r--r--sound/soc/soc-pcm.c18
-rw-r--r--sound/soc/tegra/Kconfig2
-rw-r--r--sound/soc/tegra/tegra20_ac97.c11
-rw-r--r--sound/soc/tegra/tegra20_i2s.c20
-rw-r--r--sound/soc/tegra/tegra30_ahub.c138
-rw-r--r--sound/soc/tegra/tegra30_ahub.h11
-rw-r--r--sound/soc/tegra/tegra30_i2s.c97
-rw-r--r--sound/soc/tegra/tegra30_i2s.h3
-rw-r--r--sound/soc/tegra/tegra_pcm.c17
-rw-r--r--sound/soc/tegra/tegra_pcm.h5
-rw-r--r--sound/usb/endpoint.c16
-rw-r--r--tools/lib/traceevent/event-parse.c25
-rw-r--r--tools/perf/util/header.c6
-rw-r--r--tools/perf/util/thread.c11
-rw-r--r--tools/power/cpupower/man/cpupower-idle-info.13
-rw-r--r--tools/power/cpupower/man/cpupower-idle-set.171
-rw-r--r--tools/power/cpupower/utils/helpers/sysfs.c4
929 files changed, 26883 insertions, 10770 deletions
diff --git a/Documentation/Changes b/Documentation/Changes
index b17580885273..07c75d18154e 100644
--- a/Documentation/Changes
+++ b/Documentation/Changes
@@ -196,13 +196,6 @@ chmod 0644 /dev/cpu/microcode
196as root before you can use this. You'll probably also want to 196as root before you can use this. You'll probably also want to
197get the user-space microcode_ctl utility to use with this. 197get the user-space microcode_ctl utility to use with this.
198 198
199Powertweak
200----------
201
202If you are running v0.1.17 or earlier, you should upgrade to
203version v0.99.0 or higher. Running old versions may cause problems
204with programs using shared memory.
205
206udev 199udev
207---- 200----
208udev is a userspace application for populating /dev dynamically with 201udev is a userspace application for populating /dev dynamically with
@@ -366,10 +359,6 @@ Intel P6 microcode
366------------------ 359------------------
367o <http://www.urbanmyth.org/microcode/> 360o <http://www.urbanmyth.org/microcode/>
368 361
369Powertweak
370----------
371o <http://powertweak.sourceforge.net/>
372
373udev 362udev
374---- 363----
375o <http://www.kernel.org/pub/linux/utils/kernel/hotplug/udev.html> 364o <http://www.kernel.org/pub/linux/utils/kernel/hotplug/udev.html>
diff --git a/Documentation/DocBook/device-drivers.tmpl b/Documentation/DocBook/device-drivers.tmpl
index 6c9d9d37c83a..f5170082bdb3 100644
--- a/Documentation/DocBook/device-drivers.tmpl
+++ b/Documentation/DocBook/device-drivers.tmpl
@@ -58,7 +58,7 @@
58 </sect1> 58 </sect1>
59 <sect1><title>Wait queues and Wake events</title> 59 <sect1><title>Wait queues and Wake events</title>
60!Iinclude/linux/wait.h 60!Iinclude/linux/wait.h
61!Ekernel/wait.c 61!Ekernel/sched/wait.c
62 </sect1> 62 </sect1>
63 <sect1><title>High-resolution timers</title> 63 <sect1><title>High-resolution timers</title>
64!Iinclude/linux/ktime.h 64!Iinclude/linux/ktime.h
diff --git a/Documentation/devicetree/bindings/arm/arm-boards b/Documentation/devicetree/bindings/arm/arm-boards
index 5fac246a9530..3509707f9320 100644
--- a/Documentation/devicetree/bindings/arm/arm-boards
+++ b/Documentation/devicetree/bindings/arm/arm-boards
@@ -14,6 +14,9 @@ Required nodes:
14- core-module: the root node to the Integrator platforms must have 14- core-module: the root node to the Integrator platforms must have
15 a core-module with regs and the compatible string 15 a core-module with regs and the compatible string
16 "arm,core-module-integrator" 16 "arm,core-module-integrator"
17- external-bus-interface: the root node to the Integrator platforms
18 must have an external bus interface with regs and the
19 compatible-string "arm,external-bus-interface"
17 20
18 Required properties for the core module: 21 Required properties for the core module:
19 - regs: the location and size of the core module registers, one 22 - regs: the location and size of the core module registers, one
@@ -48,6 +51,11 @@ Required nodes:
48 reg = <0x10000000 0x200>; 51 reg = <0x10000000 0x200>;
49 }; 52 };
50 53
54 ebi@12000000 {
55 compatible = "arm,external-bus-interface";
56 reg = <0x12000000 0x100>;
57 };
58
51 syscon { 59 syscon {
52 compatible = "arm,integrator-ap-syscon"; 60 compatible = "arm,integrator-ap-syscon";
53 reg = <0x11000000 0x100>; 61 reg = <0x11000000 0x100>;
diff --git a/Documentation/devicetree/bindings/arm/atmel-aic.txt b/Documentation/devicetree/bindings/arm/atmel-aic.txt
index ad031211b5b8..2742e9cfd6b1 100644
--- a/Documentation/devicetree/bindings/arm/atmel-aic.txt
+++ b/Documentation/devicetree/bindings/arm/atmel-aic.txt
@@ -2,6 +2,7 @@
2 2
3Required properties: 3Required properties:
4- compatible: Should be "atmel,<chip>-aic" 4- compatible: Should be "atmel,<chip>-aic"
5 <chip> can be "at91rm9200" or "sama5d3"
5- interrupt-controller: Identifies the node as an interrupt controller. 6- interrupt-controller: Identifies the node as an interrupt controller.
6- interrupt-parent: For single AIC system, it is an empty property. 7- interrupt-parent: For single AIC system, it is an empty property.
7- #interrupt-cells: The number of cells to define the interrupts. It should be 3. 8- #interrupt-cells: The number of cells to define the interrupts. It should be 3.
diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.txt b/Documentation/devicetree/bindings/arm/atmel-at91.txt
index 1196290082d1..d2170e780f0b 100644
--- a/Documentation/devicetree/bindings/arm/atmel-at91.txt
+++ b/Documentation/devicetree/bindings/arm/atmel-at91.txt
@@ -50,7 +50,8 @@ Example:
50 }; 50 };
51 51
52RAMC SDRAM/DDR Controller required properties: 52RAMC SDRAM/DDR Controller required properties:
53- compatible: Should be "atmel,at91sam9260-sdramc", 53- compatible: Should be "atmel,at91rm9200-sdramc",
54 "atmel,at91sam9260-sdramc",
54 "atmel,at91sam9g45-ddramc", 55 "atmel,at91sam9g45-ddramc",
55- reg: Should contain registers location and length 56- reg: Should contain registers location and length
56 For at91sam9263 and at91sam9g45 you must specify 2 entries. 57 For at91sam9263 and at91sam9g45 you must specify 2 entries.
diff --git a/Documentation/devicetree/bindings/arm/moxart.txt b/Documentation/devicetree/bindings/arm/moxart.txt
new file mode 100644
index 000000000000..11087edb0658
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/moxart.txt
@@ -0,0 +1,12 @@
1MOXA ART device tree bindings
2
3Boards with the MOXA ART SoC shall have the following properties:
4
5Required root node property:
6
7compatible = "moxa,moxart";
8
9Boards:
10
11- UC-7112-LX: embedded computer
12 compatible = "moxa,moxart-uc-7112-lx", "moxa,moxart"
diff --git a/Documentation/devicetree/bindings/arm/omap/mpu.txt b/Documentation/devicetree/bindings/arm/omap/mpu.txt
index 1a5a42ce21bb..83f405bde138 100644
--- a/Documentation/devicetree/bindings/arm/omap/mpu.txt
+++ b/Documentation/devicetree/bindings/arm/omap/mpu.txt
@@ -7,10 +7,18 @@ The MPU contain CPUs, GIC, L2 cache and a local PRCM.
7Required properties: 7Required properties:
8- compatible : Should be "ti,omap3-mpu" for OMAP3 8- compatible : Should be "ti,omap3-mpu" for OMAP3
9 Should be "ti,omap4-mpu" for OMAP4 9 Should be "ti,omap4-mpu" for OMAP4
10 Should be "ti,omap5-mpu" for OMAP5
10- ti,hwmods: "mpu" 11- ti,hwmods: "mpu"
11 12
12Examples: 13Examples:
13 14
15- For an OMAP5 SMP system:
16
17mpu {
18 compatible = "ti,omap5-mpu";
19 ti,hwmods = "mpu"
20};
21
14- For an OMAP4 SMP system: 22- For an OMAP4 SMP system:
15 23
16mpu { 24mpu {
diff --git a/Documentation/devicetree/bindings/arm/pmu.txt b/Documentation/devicetree/bindings/arm/pmu.txt
index 343781b9f246..3e1e498fea96 100644
--- a/Documentation/devicetree/bindings/arm/pmu.txt
+++ b/Documentation/devicetree/bindings/arm/pmu.txt
@@ -7,6 +7,7 @@ representation in the device tree should be done as under:-
7Required properties: 7Required properties:
8 8
9- compatible : should be one of 9- compatible : should be one of
10 "arm,armv8-pmuv3"
10 "arm,cortex-a15-pmu" 11 "arm,cortex-a15-pmu"
11 "arm,cortex-a9-pmu" 12 "arm,cortex-a9-pmu"
12 "arm,cortex-a8-pmu" 13 "arm,cortex-a8-pmu"
diff --git a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
index 47ada1dff216..5d49f2b37f68 100644
--- a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
@@ -49,7 +49,7 @@ adc@12D10000 {
49 /* NTC thermistor is a hwmon device */ 49 /* NTC thermistor is a hwmon device */
50 ncp15wb473@0 { 50 ncp15wb473@0 {
51 compatible = "ntc,ncp15wb473"; 51 compatible = "ntc,ncp15wb473";
52 pullup-uV = <1800000>; 52 pullup-uv = <1800000>;
53 pullup-ohm = <47000>; 53 pullup-ohm = <47000>;
54 pulldown-ohm = <0>; 54 pulldown-ohm = <0>;
55 io-channels = <&adc 4>; 55 io-channels = <&adc 4>;
diff --git a/Documentation/devicetree/bindings/arm/samsung/sysreg.txt b/Documentation/devicetree/bindings/arm/samsung/sysreg.txt
index 5039c0a12f55..0ab3251a6ec2 100644
--- a/Documentation/devicetree/bindings/arm/samsung/sysreg.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/sysreg.txt
@@ -1,7 +1,12 @@
1SAMSUNG S5P/Exynos SoC series System Registers (SYSREG) 1SAMSUNG S5P/Exynos SoC series System Registers (SYSREG)
2 2
3Properties: 3Properties:
4 - name : should be 'sysreg';
5 - compatible : should contain "samsung,<chip name>-sysreg", "syscon"; 4 - compatible : should contain "samsung,<chip name>-sysreg", "syscon";
6 For Exynos4 SoC series it should be "samsung,exynos4-sysreg", "syscon"; 5 For Exynos4 SoC series it should be "samsung,exynos4-sysreg", "syscon";
7 - reg : offset and length of the register set. 6 - reg : offset and length of the register set.
7
8Example:
9 syscon@10010000 {
10 compatible = "samsung,exynos4-sysreg", "syscon";
11 reg = <0x10010000 0x400>;
12 };
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt
index 1608a54e90e1..68ac65f82a1c 100644
--- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt
@@ -9,6 +9,7 @@ Required properties:
9- compatible : Should contain "nvidia,tegra<chip>-pmc". 9- compatible : Should contain "nvidia,tegra<chip>-pmc".
10- reg : Offset and length of the register set for the device 10- reg : Offset and length of the register set for the device
11- clocks : Must contain an entry for each entry in clock-names. 11- clocks : Must contain an entry for each entry in clock-names.
12 See ../clocks/clock-bindings.txt for details.
12- clock-names : Must include the following entries: 13- clock-names : Must include the following entries:
13 "pclk" (The Tegra clock of that name), 14 "pclk" (The Tegra clock of that name),
14 "clk32k_in" (The 32KHz clock input to Tegra). 15 "clk32k_in" (The 32KHz clock input to Tegra).
diff --git a/Documentation/devicetree/bindings/clock/at91-clock.txt b/Documentation/devicetree/bindings/clock/at91-clock.txt
new file mode 100644
index 000000000000..cd5e23912888
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/at91-clock.txt
@@ -0,0 +1,339 @@
1Device Tree Clock bindings for arch-at91
2
3This binding uses the common clock binding[1].
4
5[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
6
7Required properties:
8- compatible : shall be one of the following:
9 "atmel,at91rm9200-pmc" or
10 "atmel,at91sam9g45-pmc" or
11 "atmel,at91sam9n12-pmc" or
12 "atmel,at91sam9x5-pmc" or
13 "atmel,sama5d3-pmc":
14 at91 PMC (Power Management Controller)
15 All at91 specific clocks (clocks defined below) must be child
16 node of the PMC node.
17
18 "atmel,at91rm9200-clk-main":
19 at91 main oscillator
20
21 "atmel,at91rm9200-clk-master" or
22 "atmel,at91sam9x5-clk-master":
23 at91 master clock
24
25 "atmel,at91sam9x5-clk-peripheral" or
26 "atmel,at91rm9200-clk-peripheral":
27 at91 peripheral clocks
28
29 "atmel,at91rm9200-clk-pll" or
30 "atmel,at91sam9g45-clk-pll" or
31 "atmel,at91sam9g20-clk-pllb" or
32 "atmel,sama5d3-clk-pll":
33 at91 pll clocks
34
35 "atmel,at91sam9x5-clk-plldiv":
36 at91 plla divisor
37
38 "atmel,at91rm9200-clk-programmable" or
39 "atmel,at91sam9g45-clk-programmable" or
40 "atmel,at91sam9x5-clk-programmable":
41 at91 programmable clocks
42
43 "atmel,at91sam9x5-clk-smd":
44 at91 SMD (Soft Modem) clock
45
46 "atmel,at91rm9200-clk-system":
47 at91 system clocks
48
49 "atmel,at91rm9200-clk-usb" or
50 "atmel,at91sam9x5-clk-usb" or
51 "atmel,at91sam9n12-clk-usb":
52 at91 usb clock
53
54 "atmel,at91sam9x5-clk-utmi":
55 at91 utmi clock
56
57Required properties for PMC node:
58- reg : defines the IO memory reserved for the PMC.
59- #size-cells : shall be 0 (reg is used to encode clk id).
60- #address-cells : shall be 1 (reg is used to encode clk id).
61- interrupts : shall be set to PMC interrupt line.
62- interrupt-controller : tell that the PMC is an interrupt controller.
63- #interrupt-cells : must be set to 1. The first cell encodes the interrupt id,
64 and reflect the bit position in the PMC_ER/DR/SR registers.
65 You can use the dt macros defined in dt-bindings/clk/at91.h.
66 0 (AT91_PMC_MOSCS) -> main oscillator ready
67 1 (AT91_PMC_LOCKA) -> PLL A ready
68 2 (AT91_PMC_LOCKB) -> PLL B ready
69 3 (AT91_PMC_MCKRDY) -> master clock ready
70 6 (AT91_PMC_LOCKU) -> UTMI PLL clock ready
71 8 .. 15 (AT91_PMC_PCKRDY(id)) -> programmable clock ready
72 16 (AT91_PMC_MOSCSELS) -> main oscillator selected
73 17 (AT91_PMC_MOSCRCS) -> RC main oscillator stabilized
74 18 (AT91_PMC_CFDEV) -> clock failure detected
75
76For example:
77 pmc: pmc@fffffc00 {
78 compatible = "atmel,sama5d3-pmc";
79 interrupts = <1 4 7>;
80 interrupt-controller;
81 #interrupt-cells = <2>;
82 #size-cells = <0>;
83 #address-cells = <1>;
84
85 /* put at91 clocks here */
86 };
87
88Required properties for main clock:
89- interrupt-parent : must reference the PMC node.
90- interrupts : shall be set to "<0>".
91- #clock-cells : from common clock binding; shall be set to 0.
92- clocks (optional if clock-frequency is provided) : shall be the slow clock
93 phandle. This clock is used to calculate the main clock rate if
94 "clock-frequency" is not provided.
95- clock-frequency : the main oscillator frequency.Prefer the use of
96 "clock-frequency" over automatic clock rate calculation.
97
98For example:
99 main: mainck {
100 compatible = "atmel,at91rm9200-clk-main";
101 interrupt-parent = <&pmc>;
102 interrupts = <0>;
103 #clock-cells = <0>;
104 clocks = <&ck32k>;
105 clock-frequency = <18432000>;
106 };
107
108Required properties for master clock:
109- interrupt-parent : must reference the PMC node.
110- interrupts : shall be set to "<3>".
111- #clock-cells : from common clock binding; shall be set to 0.
112- clocks : shall be the master clock sources (see atmel datasheet) phandles.
113 e.g. "<&ck32k>, <&main>, <&plla>, <&pllb>".
114- atmel,clk-output-range : minimum and maximum clock frequency (two u32
115 fields).
116 e.g. output = <0 133000000>; <=> 0 to 133MHz.
117- atmel,clk-divisors : master clock divisors table (four u32 fields).
118 0 <=> reserved value.
119 e.g. divisors = <1 2 4 6>;
120- atmel,master-clk-have-div3-pres : some SoC use the reserved value 7 in the
121 PRES field as CLOCK_DIV3 (e.g sam9x5).
122
123For example:
124 mck: mck {
125 compatible = "atmel,at91rm9200-clk-master";
126 interrupt-parent = <&pmc>;
127 interrupts = <3>;
128 #clock-cells = <0>;
129 atmel,clk-output-range = <0 133000000>;
130 atmel,clk-divisors = <1 2 4 0>;
131 };
132
133Required properties for peripheral clocks:
134- #size-cells : shall be 0 (reg is used to encode clk id).
135- #address-cells : shall be 1 (reg is used to encode clk id).
136- clocks : shall be the master clock phandle.
137 e.g. clocks = <&mck>;
138- name: device tree node describing a specific system clock.
139 * #clock-cells : from common clock binding; shall be set to 0.
140 * reg: peripheral id. See Atmel's datasheets to get a full
141 list of peripheral ids.
142 * atmel,clk-output-range : minimum and maximum clock frequency
143 (two u32 fields). Only valid on at91sam9x5-clk-peripheral
144 compatible IPs.
145
146For example:
147 periph: periphck {
148 compatible = "atmel,at91sam9x5-clk-peripheral";
149 #size-cells = <0>;
150 #address-cells = <1>;
151 clocks = <&mck>;
152
153 ssc0_clk {
154 #clock-cells = <0>;
155 reg = <2>;
156 atmel,clk-output-range = <0 133000000>;
157 };
158
159 usart0_clk {
160 #clock-cells = <0>;
161 reg = <3>;
162 atmel,clk-output-range = <0 66000000>;
163 };
164 };
165
166
167Required properties for pll clocks:
168- interrupt-parent : must reference the PMC node.
169- interrupts : shall be set to "<1>".
170- #clock-cells : from common clock binding; shall be set to 0.
171- clocks : shall be the main clock phandle.
172- reg : pll id.
173 0 -> PLL A
174 1 -> PLL B
175- atmel,clk-input-range : minimum and maximum source clock frequency (two u32
176 fields).
177 e.g. input = <1 32000000>; <=> 1 to 32MHz.
178- #atmel,pll-clk-output-range-cells : number of cells reserved for pll output
179 range description. Sould be set to 2, 3
180 or 4.
181 * 1st and 2nd cells represent the frequency range (min-max).
182 * 3rd cell is optional and represents the OUT field value for the given
183 range.
184 * 4th cell is optional and represents the ICPLL field (PLLICPR
185 register)
186- atmel,pll-clk-output-ranges : pll output frequency ranges + optional parameter
187 depending on #atmel,pll-output-range-cells
188 property value.
189
190For example:
191 plla: pllack {
192 compatible = "atmel,at91sam9g45-clk-pll";
193 interrupt-parent = <&pmc>;
194 interrupts = <1>;
195 #clock-cells = <0>;
196 clocks = <&main>;
197 reg = <0>;
198 atmel,clk-input-range = <2000000 32000000>;
199 #atmel,pll-clk-output-range-cells = <4>;
200 atmel,pll-clk-output-ranges = <74500000 800000000 0 0
201 69500000 750000000 1 0
202 64500000 700000000 2 0
203 59500000 650000000 3 0
204 54500000 600000000 0 1
205 49500000 550000000 1 1
206 44500000 500000000 2 1
207 40000000 450000000 3 1>;
208 };
209
210Required properties for plldiv clocks (plldiv = pll / 2):
211- #clock-cells : from common clock binding; shall be set to 0.
212- clocks : shall be the plla clock phandle.
213
214The pll divisor is equal to 2 and cannot be changed.
215
216For example:
217 plladiv: plladivck {
218 compatible = "atmel,at91sam9x5-clk-plldiv";
219 #clock-cells = <0>;
220 clocks = <&plla>;
221 };
222
223Required properties for programmable clocks:
224- interrupt-parent : must reference the PMC node.
225- #size-cells : shall be 0 (reg is used to encode clk id).
226- #address-cells : shall be 1 (reg is used to encode clk id).
227- clocks : shall be the programmable clock source phandles.
228 e.g. clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
229- name: device tree node describing a specific prog clock.
230 * #clock-cells : from common clock binding; shall be set to 0.
231 * reg : programmable clock id (register offset from PCKx
232 register).
233 * interrupts : shall be set to "<(8 + id)>".
234
235For example:
236 prog: progck {
237 compatible = "atmel,at91sam9g45-clk-programmable";
238 #size-cells = <0>;
239 #address-cells = <1>;
240 interrupt-parent = <&pmc>;
241 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
242
243 prog0 {
244 #clock-cells = <0>;
245 reg = <0>;
246 interrupts = <8>;
247 };
248
249 prog1 {
250 #clock-cells = <0>;
251 reg = <1>;
252 interrupts = <9>;
253 };
254 };
255
256
257Required properties for smd clock:
258- #clock-cells : from common clock binding; shall be set to 0.
259- clocks : shall be the smd clock source phandles.
260 e.g. clocks = <&plladiv>, <&utmi>;
261
262For example:
263 smd: smdck {
264 compatible = "atmel,at91sam9x5-clk-smd";
265 #clock-cells = <0>;
266 clocks = <&plladiv>, <&utmi>;
267 };
268
269Required properties for system clocks:
270- #size-cells : shall be 0 (reg is used to encode clk id).
271- #address-cells : shall be 1 (reg is used to encode clk id).
272- name: device tree node describing a specific system clock.
273 * #clock-cells : from common clock binding; shall be set to 0.
274 * reg: system clock id (bit position in SCER/SCDR/SCSR registers).
275 See Atmel's datasheet to get a full list of system clock ids.
276
277For example:
278 system: systemck {
279 compatible = "atmel,at91rm9200-clk-system";
280 #address-cells = <1>;
281 #size-cells = <0>;
282
283 ddrck {
284 #clock-cells = <0>;
285 reg = <2>;
286 clocks = <&mck>;
287 };
288
289 uhpck {
290 #clock-cells = <0>;
291 reg = <6>;
292 clocks = <&usb>;
293 };
294
295 udpck {
296 #clock-cells = <0>;
297 reg = <7>;
298 clocks = <&usb>;
299 };
300 };
301
302
303Required properties for usb clock:
304- #clock-cells : from common clock binding; shall be set to 0.
305- clocks : shall be the smd clock source phandles.
306 e.g. clocks = <&pllb>;
307- atmel,clk-divisors (only available for "atmel,at91rm9200-clk-usb"):
308 usb clock divisor table.
309 e.g. divisors = <1 2 4 0>;
310
311For example:
312 usb: usbck {
313 compatible = "atmel,at91sam9x5-clk-usb";
314 #clock-cells = <0>;
315 clocks = <&plladiv>, <&utmi>;
316 };
317
318 usb: usbck {
319 compatible = "atmel,at91rm9200-clk-usb";
320 #clock-cells = <0>;
321 clocks = <&pllb>;
322 atmel,clk-divisors = <1 2 4 0>;
323 };
324
325
326Required properties for utmi clock:
327- interrupt-parent : must reference the PMC node.
328- interrupts : shall be set to "<AT91_PMC_LOCKU IRQ_TYPE_LEVEL_HIGH>".
329- #clock-cells : from common clock binding; shall be set to 0.
330- clocks : shall be the main clock source phandle.
331
332For example:
333 utmi: utmick {
334 compatible = "atmel,at91sam9x5-clk-utmi";
335 interrupt-parent = <&pmc>;
336 interrupts = <AT91_PMC_LOCKU IRQ_TYPE_LEVEL_HIGH>;
337 #clock-cells = <0>;
338 clocks = <&main>;
339 };
diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
index c6bf8a6c8f52..a2ac2d9ac71a 100644
--- a/Documentation/devicetree/bindings/clock/exynos4-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
@@ -6,7 +6,7 @@ SoC's in the Exynos4 family.
6 6
7Required Properties: 7Required Properties:
8 8
9- comptible: should be one of the following. 9- compatible: should be one of the following.
10 - "samsung,exynos4210-clock" - controller compatible with Exynos4210 SoC. 10 - "samsung,exynos4210-clock" - controller compatible with Exynos4210 SoC.
11 - "samsung,exynos4412-clock" - controller compatible with Exynos4412 SoC. 11 - "samsung,exynos4412-clock" - controller compatible with Exynos4412 SoC.
12 12
diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
index 24765c146e31..46f5c791ea0d 100644
--- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
@@ -5,7 +5,7 @@ controllers within the Exynos5250 SoC.
5 5
6Required Properties: 6Required Properties:
7 7
8- comptible: should be one of the following. 8- compatible: should be one of the following.
9 - "samsung,exynos5250-clock" - controller compatible with Exynos5250 SoC. 9 - "samsung,exynos5250-clock" - controller compatible with Exynos5250 SoC.
10 10
11- reg: physical base address of the controller and length of memory mapped 11- reg: physical base address of the controller and length of memory mapped
diff --git a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
index 32aa34ecad36..458f34789e5d 100644
--- a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
@@ -5,7 +5,7 @@ controllers within the Exynos5420 SoC.
5 5
6Required Properties: 6Required Properties:
7 7
8- comptible: should be one of the following. 8- compatible: should be one of the following.
9 - "samsung,exynos5420-clock" - controller compatible with Exynos5420 SoC. 9 - "samsung,exynos5420-clock" - controller compatible with Exynos5420 SoC.
10 10
11- reg: physical base address of the controller and length of memory mapped 11- reg: physical base address of the controller and length of memory mapped
diff --git a/Documentation/devicetree/bindings/clock/exynos5440-clock.txt b/Documentation/devicetree/bindings/clock/exynos5440-clock.txt
index 4499e9966bc9..9955dc9c7d96 100644
--- a/Documentation/devicetree/bindings/clock/exynos5440-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5440-clock.txt
@@ -5,7 +5,7 @@ controllers within the Exynos5440 SoC.
5 5
6Required Properties: 6Required Properties:
7 7
8- comptible: should be "samsung,exynos5440-clock". 8- compatible: should be "samsung,exynos5440-clock".
9 9
10- reg: physical base address of the controller and length of memory mapped 10- reg: physical base address of the controller and length of memory mapped
11 region. 11 region.
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt
index 0c80c2677104..9acea9d93160 100644
--- a/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt
@@ -15,6 +15,9 @@ Required properties :
15 In clock consumers, this cell represents the clock ID exposed by the 15 In clock consumers, this cell represents the clock ID exposed by the
16 CAR. The assignments may be found in header file 16 CAR. The assignments may be found in header file
17 <dt-bindings/clock/tegra114-car.h>. 17 <dt-bindings/clock/tegra114-car.h>.
18- #reset-cells : Should be 1.
19 In clock consumers, this cell represents the bit number in the CAR's
20 array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.
18 21
19Example SoC include file: 22Example SoC include file:
20 23
@@ -23,6 +26,7 @@ Example SoC include file:
23 compatible = "nvidia,tegra114-car"; 26 compatible = "nvidia,tegra114-car";
24 reg = <0x60006000 0x1000>; 27 reg = <0x60006000 0x1000>;
25 #clock-cells = <1>; 28 #clock-cells = <1>;
29 #reset-cells = <1>;
26 }; 30 };
27 31
28 usb@c5004000 { 32 usb@c5004000 {
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt
new file mode 100644
index 000000000000..ded5d6212c84
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt
@@ -0,0 +1,63 @@
1NVIDIA Tegra124 Clock And Reset Controller
2
3This binding uses the common clock binding:
4Documentation/devicetree/bindings/clock/clock-bindings.txt
5
6The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
7for muxing and gating Tegra's clocks, and setting their rates.
8
9Required properties :
10- compatible : Should be "nvidia,tegra124-car"
11- reg : Should contain CAR registers location and length
12- clocks : Should contain phandle and clock specifiers for two clocks:
13 the 32 KHz "32k_in", and the board-specific oscillator "osc".
14- #clock-cells : Should be 1.
15 In clock consumers, this cell represents the clock ID exposed by the
16 CAR. The assignments may be found in header file
17 <dt-bindings/clock/tegra124-car.h>.
18- #reset-cells : Should be 1.
19 In clock consumers, this cell represents the bit number in the CAR's
20 array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.
21
22Example SoC include file:
23
24/ {
25 tegra_car: clock {
26 compatible = "nvidia,tegra124-car";
27 reg = <0x60006000 0x1000>;
28 #clock-cells = <1>;
29 #reset-cells = <1>;
30 };
31
32 usb@c5004000 {
33 clocks = <&tegra_car TEGRA124_CLK_USB2>;
34 };
35};
36
37Example board file:
38
39/ {
40 clocks {
41 compatible = "simple-bus";
42 #address-cells = <1>;
43 #size-cells = <0>;
44
45 osc: clock@0 {
46 compatible = "fixed-clock";
47 reg = <0>;
48 #clock-cells = <0>;
49 clock-frequency = <112400000>;
50 };
51
52 clk_32k: clock@1 {
53 compatible = "fixed-clock";
54 reg = <1>;
55 #clock-cells = <0>;
56 clock-frequency = <32768>;
57 };
58 };
59
60 &tegra_car {
61 clocks = <&clk_32k> <&osc>;
62 };
63};
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
index fcfed5bf73fb..6c5901b503d0 100644
--- a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
@@ -15,6 +15,9 @@ Required properties :
15 In clock consumers, this cell represents the clock ID exposed by the 15 In clock consumers, this cell represents the clock ID exposed by the
16 CAR. The assignments may be found in header file 16 CAR. The assignments may be found in header file
17 <dt-bindings/clock/tegra20-car.h>. 17 <dt-bindings/clock/tegra20-car.h>.
18- #reset-cells : Should be 1.
19 In clock consumers, this cell represents the bit number in the CAR's
20 array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.
18 21
19Example SoC include file: 22Example SoC include file:
20 23
@@ -23,6 +26,7 @@ Example SoC include file:
23 compatible = "nvidia,tegra20-car"; 26 compatible = "nvidia,tegra20-car";
24 reg = <0x60006000 0x1000>; 27 reg = <0x60006000 0x1000>;
25 #clock-cells = <1>; 28 #clock-cells = <1>;
29 #reset-cells = <1>;
26 }; 30 };
27 31
28 usb@c5004000 { 32 usb@c5004000 {
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt
index 0f714081e986..63618cde12df 100644
--- a/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt
@@ -15,6 +15,9 @@ Required properties :
15 In clock consumers, this cell represents the clock ID exposed by the 15 In clock consumers, this cell represents the clock ID exposed by the
16 CAR. The assignments may be found in header file 16 CAR. The assignments may be found in header file
17 <dt-bindings/clock/tegra30-car.h>. 17 <dt-bindings/clock/tegra30-car.h>.
18- #reset-cells : Should be 1.
19 In clock consumers, this cell represents the bit number in the CAR's
20 array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.
18 21
19Example SoC include file: 22Example SoC include file:
20 23
@@ -23,6 +26,7 @@ Example SoC include file:
23 compatible = "nvidia,tegra30-car"; 26 compatible = "nvidia,tegra30-car";
24 reg = <0x60006000 0x1000>; 27 reg = <0x60006000 0x1000>;
25 #clock-cells = <1>; 28 #clock-cells = <1>;
29 #reset-cells = <1>;
26 }; 30 };
27 31
28 usb@c5004000 { 32 usb@c5004000 {
diff --git a/Documentation/devicetree/bindings/dma/ste-dma40.txt b/Documentation/devicetree/bindings/dma/ste-dma40.txt
index a8c21c256baa..1f5729f10621 100644
--- a/Documentation/devicetree/bindings/dma/ste-dma40.txt
+++ b/Documentation/devicetree/bindings/dma/ste-dma40.txt
@@ -50,6 +50,9 @@ Each dmas request consists of 4 cells:
50 0x00000008: Use fixed channel: 50 0x00000008: Use fixed channel:
51 Use automatic channel selection when unset 51 Use automatic channel selection when unset
52 Use DMA request line number when set 52 Use DMA request line number when set
53 0x00000010: Set channel as high priority:
54 Normal priority when unset
55 High priority when set
53 56
54Example: 57Example:
55 58
diff --git a/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt b/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt
index 90fa7da525b8..c6908e7c42cc 100644
--- a/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt
+++ b/Documentation/devicetree/bindings/dma/tegra20-apbdma.txt
@@ -5,6 +5,16 @@ Required properties:
5- reg: Should contain DMA registers location and length. This shuld include 5- reg: Should contain DMA registers location and length. This shuld include
6 all of the per-channel registers. 6 all of the per-channel registers.
7- interrupts: Should contain all of the per-channel DMA interrupts. 7- interrupts: Should contain all of the per-channel DMA interrupts.
8- clocks: Must contain one entry, for the module clock.
9 See ../clocks/clock-bindings.txt for details.
10- resets : Must contain an entry for each entry in reset-names.
11 See ../reset/reset.txt for details.
12- reset-names : Must include the following entries:
13 - dma
14- #dma-cells : Must be <1>. This dictates the length of DMA specifiers in
15 client nodes' dmas properties. The specifier represents the DMA request
16 select value for the peripheral. For more details, consult the Tegra TRM's
17 documentation of the APB DMA channel control register REQ_SEL field.
8 18
9Examples: 19Examples:
10 20
@@ -27,4 +37,8 @@ apbdma: dma@6000a000 {
27 0 149 0x04 37 0 149 0x04
28 0 150 0x04 38 0 150 0x04
29 0 151 0x04 >; 39 0 151 0x04 >;
40 clocks = <&tegra_car 34>;
41 resets = <&tegra_car 34>;
42 reset-names = "dma";
43 #dma-cells = <1>;
30}; 44};
diff --git a/Documentation/devicetree/bindings/gpio/8xxx_gpio.txt b/Documentation/devicetree/bindings/gpio/8xxx_gpio.txt
index b0019eb5330e..798cfc9d3839 100644
--- a/Documentation/devicetree/bindings/gpio/8xxx_gpio.txt
+++ b/Documentation/devicetree/bindings/gpio/8xxx_gpio.txt
@@ -5,16 +5,42 @@ This is for the non-QE/CPM/GUTs GPIO controllers as found on
5 5
6Every GPIO controller node must have #gpio-cells property defined, 6Every GPIO controller node must have #gpio-cells property defined,
7this information will be used to translate gpio-specifiers. 7this information will be used to translate gpio-specifiers.
8See bindings/gpio/gpio.txt for details of how to specify GPIO
9information for devices.
10
11The GPIO module usually is connected to the SoC's internal interrupt
12controller, see bindings/interrupt-controller/interrupts.txt (the
13interrupt client nodes section) for details how to specify this GPIO
14module's interrupt.
15
16The GPIO module may serve as another interrupt controller (cascaded to
17the SoC's internal interrupt controller). See the interrupt controller
18nodes section in bindings/interrupt-controller/interrupts.txt for
19details.
8 20
9Required properties: 21Required properties:
10- compatible : "fsl,<CHIP>-gpio" followed by "fsl,mpc8349-gpio" for 22- compatible: "fsl,<chip>-gpio" followed by "fsl,mpc8349-gpio"
11 83xx, "fsl,mpc8572-gpio" for 85xx and "fsl,mpc8610-gpio" for 86xx. 23 for 83xx, "fsl,mpc8572-gpio" for 85xx, or
12- #gpio-cells : Should be two. The first cell is the pin number and the 24 "fsl,mpc8610-gpio" for 86xx.
13 second cell is used to specify optional parameters (currently unused). 25- #gpio-cells: Should be two. The first cell is the pin number
14 - interrupts : Interrupt mapping for GPIO IRQ. 26 and the second cell is used to specify optional
15 - interrupt-parent : Phandle for the interrupt controller that 27 parameters (currently unused).
16 services interrupts for this device. 28- interrupt-parent: Phandle for the interrupt controller that
17- gpio-controller : Marks the port as GPIO controller. 29 services interrupts for this device.
30- interrupts: Interrupt mapping for GPIO IRQ.
31- gpio-controller: Marks the port as GPIO controller.
32
33Optional properties:
34- interrupt-controller: Empty boolean property which marks the GPIO
35 module as an IRQ controller.
36- #interrupt-cells: Should be two. Defines the number of integer
37 cells required to specify an interrupt within
38 this interrupt controller. The first cell
39 defines the pin number, the second cell
40 defines additional flags (trigger type,
41 trigger polarity). Note that the available
42 set of trigger conditions supported by the
43 GPIO module depends on the actual SoC.
18 44
19Example of gpio-controller nodes for a MPC8347 SoC: 45Example of gpio-controller nodes for a MPC8347 SoC:
20 46
@@ -22,39 +48,27 @@ Example of gpio-controller nodes for a MPC8347 SoC:
22 #gpio-cells = <2>; 48 #gpio-cells = <2>;
23 compatible = "fsl,mpc8347-gpio", "fsl,mpc8349-gpio"; 49 compatible = "fsl,mpc8347-gpio", "fsl,mpc8349-gpio";
24 reg = <0xc00 0x100>; 50 reg = <0xc00 0x100>;
25 interrupts = <74 0x8>;
26 interrupt-parent = <&ipic>; 51 interrupt-parent = <&ipic>;
52 interrupts = <74 0x8>;
27 gpio-controller; 53 gpio-controller;
54 interrupt-controller;
55 #interrupt-cells = <2>;
28 }; 56 };
29 57
30 gpio2: gpio-controller@d00 { 58 gpio2: gpio-controller@d00 {
31 #gpio-cells = <2>; 59 #gpio-cells = <2>;
32 compatible = "fsl,mpc8347-gpio", "fsl,mpc8349-gpio"; 60 compatible = "fsl,mpc8347-gpio", "fsl,mpc8349-gpio";
33 reg = <0xd00 0x100>; 61 reg = <0xd00 0x100>;
34 interrupts = <75 0x8>;
35 interrupt-parent = <&ipic>; 62 interrupt-parent = <&ipic>;
63 interrupts = <75 0x8>;
36 gpio-controller; 64 gpio-controller;
37 }; 65 };
38 66
39See booting-without-of.txt for details of how to specify GPIO 67Example of a peripheral using the GPIO module as an IRQ controller:
40information for devices.
41
42To use GPIO pins as interrupt sources for peripherals, specify the
43GPIO controller as the interrupt parent and define GPIO number +
44trigger mode using the interrupts property, which is defined like
45this:
46
47interrupts = <number trigger>, where:
48 - number: GPIO pin (0..31)
49 - trigger: trigger mode:
50 2 = trigger on falling edge
51 3 = trigger on both edges
52
53Example of device using this is:
54 68
55 funkyfpga@0 { 69 funkyfpga@0 {
56 compatible = "funky-fpga"; 70 compatible = "funky-fpga";
57 ... 71 ...
58 interrupts = <4 3>;
59 interrupt-parent = <&gpio1>; 72 interrupt-parent = <&gpio1>;
73 interrupts = <4 3>;
60 }; 74 };
diff --git a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
index b4fa934ae3a2..ab45c02aa658 100644
--- a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
+++ b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
@@ -9,6 +9,12 @@ Required properties:
9- #size-cells: The number of cells used to represent the size of an address 9- #size-cells: The number of cells used to represent the size of an address
10 range in the host1x address space. Should be 1. 10 range in the host1x address space. Should be 1.
11- ranges: The mapping of the host1x address space to the CPU address space. 11- ranges: The mapping of the host1x address space to the CPU address space.
12- clocks: Must contain one entry, for the module clock.
13 See ../clocks/clock-bindings.txt for details.
14- resets: Must contain an entry for each entry in reset-names.
15 See ../reset/reset.txt for details.
16- reset-names: Must include the following entries:
17 - host1x
12 18
13The host1x top-level node defines a number of children, each representing one 19The host1x top-level node defines a number of children, each representing one
14of the following host1x client modules: 20of the following host1x client modules:
@@ -19,6 +25,12 @@ of the following host1x client modules:
19 - compatible: "nvidia,tegra<chip>-mpe" 25 - compatible: "nvidia,tegra<chip>-mpe"
20 - reg: Physical base address and length of the controller's registers. 26 - reg: Physical base address and length of the controller's registers.
21 - interrupts: The interrupt outputs from the controller. 27 - interrupts: The interrupt outputs from the controller.
28 - clocks: Must contain one entry, for the module clock.
29 See ../clocks/clock-bindings.txt for details.
30 - resets: Must contain an entry for each entry in reset-names.
31 See ../reset/reset.txt for details.
32 - reset-names: Must include the following entries:
33 - mpe
22 34
23- vi: video input 35- vi: video input
24 36
@@ -26,6 +38,12 @@ of the following host1x client modules:
26 - compatible: "nvidia,tegra<chip>-vi" 38 - compatible: "nvidia,tegra<chip>-vi"
27 - reg: Physical base address and length of the controller's registers. 39 - reg: Physical base address and length of the controller's registers.
28 - interrupts: The interrupt outputs from the controller. 40 - interrupts: The interrupt outputs from the controller.
41 - clocks: Must contain one entry, for the module clock.
42 See ../clocks/clock-bindings.txt for details.
43 - resets: Must contain an entry for each entry in reset-names.
44 See ../reset/reset.txt for details.
45 - reset-names: Must include the following entries:
46 - vi
29 47
30- epp: encoder pre-processor 48- epp: encoder pre-processor
31 49
@@ -33,6 +51,12 @@ of the following host1x client modules:
33 - compatible: "nvidia,tegra<chip>-epp" 51 - compatible: "nvidia,tegra<chip>-epp"
34 - reg: Physical base address and length of the controller's registers. 52 - reg: Physical base address and length of the controller's registers.
35 - interrupts: The interrupt outputs from the controller. 53 - interrupts: The interrupt outputs from the controller.
54 - clocks: Must contain one entry, for the module clock.
55 See ../clocks/clock-bindings.txt for details.
56 - resets: Must contain an entry for each entry in reset-names.
57 See ../reset/reset.txt for details.
58 - reset-names: Must include the following entries:
59 - epp
36 60
37- isp: image signal processor 61- isp: image signal processor
38 62
@@ -40,6 +64,12 @@ of the following host1x client modules:
40 - compatible: "nvidia,tegra<chip>-isp" 64 - compatible: "nvidia,tegra<chip>-isp"
41 - reg: Physical base address and length of the controller's registers. 65 - reg: Physical base address and length of the controller's registers.
42 - interrupts: The interrupt outputs from the controller. 66 - interrupts: The interrupt outputs from the controller.
67 - clocks: Must contain one entry, for the module clock.
68 See ../clocks/clock-bindings.txt for details.
69 - resets: Must contain an entry for each entry in reset-names.
70 See ../reset/reset.txt for details.
71 - reset-names: Must include the following entries:
72 - isp
43 73
44- gr2d: 2D graphics engine 74- gr2d: 2D graphics engine
45 75
@@ -47,12 +77,30 @@ of the following host1x client modules:
47 - compatible: "nvidia,tegra<chip>-gr2d" 77 - compatible: "nvidia,tegra<chip>-gr2d"
48 - reg: Physical base address and length of the controller's registers. 78 - reg: Physical base address and length of the controller's registers.
49 - interrupts: The interrupt outputs from the controller. 79 - interrupts: The interrupt outputs from the controller.
80 - clocks: Must contain one entry, for the module clock.
81 See ../clocks/clock-bindings.txt for details.
82 - resets: Must contain an entry for each entry in reset-names.
83 See ../reset/reset.txt for details.
84 - reset-names: Must include the following entries:
85 - 2d
50 86
51- gr3d: 3D graphics engine 87- gr3d: 3D graphics engine
52 88
53 Required properties: 89 Required properties:
54 - compatible: "nvidia,tegra<chip>-gr3d" 90 - compatible: "nvidia,tegra<chip>-gr3d"
55 - reg: Physical base address and length of the controller's registers. 91 - reg: Physical base address and length of the controller's registers.
92 - clocks: Must contain an entry for each entry in clock-names.
93 See ../clocks/clock-bindings.txt for details.
94 - clock-names: Must include the following entries:
95 (This property may be omitted if the only clock in the list is "3d")
96 - 3d
97 This MUST be the first entry.
98 - 3d2 (Only required on SoCs with two 3D clocks)
99 - resets: Must contain an entry for each entry in reset-names.
100 See ../reset/reset.txt for details.
101 - reset-names: Must include the following entries:
102 - 3d
103 - 3d2 (Only required on SoCs with two 3D clocks)
56 104
57- dc: display controller 105- dc: display controller
58 106
@@ -60,6 +108,16 @@ of the following host1x client modules:
60 - compatible: "nvidia,tegra<chip>-dc" 108 - compatible: "nvidia,tegra<chip>-dc"
61 - reg: Physical base address and length of the controller's registers. 109 - reg: Physical base address and length of the controller's registers.
62 - interrupts: The interrupt outputs from the controller. 110 - interrupts: The interrupt outputs from the controller.
111 - clocks: Must contain an entry for each entry in clock-names.
112 See ../clocks/clock-bindings.txt for details.
113 - clock-names: Must include the following entries:
114 - dc
115 This MUST be the first entry.
116 - parent
117 - resets: Must contain an entry for each entry in reset-names.
118 See ../reset/reset.txt for details.
119 - reset-names: Must include the following entries:
120 - dc
63 121
64 Each display controller node has a child node, named "rgb", that represents 122 Each display controller node has a child node, named "rgb", that represents
65 the RGB output associated with the controller. It can take the following 123 the RGB output associated with the controller. It can take the following
@@ -76,6 +134,16 @@ of the following host1x client modules:
76 - interrupts: The interrupt outputs from the controller. 134 - interrupts: The interrupt outputs from the controller.
77 - vdd-supply: regulator for supply voltage 135 - vdd-supply: regulator for supply voltage
78 - pll-supply: regulator for PLL 136 - pll-supply: regulator for PLL
137 - clocks: Must contain an entry for each entry in clock-names.
138 See ../clocks/clock-bindings.txt for details.
139 - clock-names: Must include the following entries:
140 - hdmi
141 This MUST be the first entry.
142 - parent
143 - resets: Must contain an entry for each entry in reset-names.
144 See ../reset/reset.txt for details.
145 - reset-names: Must include the following entries:
146 - hdmi
79 147
80 Optional properties: 148 Optional properties:
81 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing 149 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
@@ -88,12 +156,24 @@ of the following host1x client modules:
88 - compatible: "nvidia,tegra<chip>-tvo" 156 - compatible: "nvidia,tegra<chip>-tvo"
89 - reg: Physical base address and length of the controller's registers. 157 - reg: Physical base address and length of the controller's registers.
90 - interrupts: The interrupt outputs from the controller. 158 - interrupts: The interrupt outputs from the controller.
159 - clocks: Must contain one entry, for the module clock.
160 See ../clocks/clock-bindings.txt for details.
91 161
92- dsi: display serial interface 162- dsi: display serial interface
93 163
94 Required properties: 164 Required properties:
95 - compatible: "nvidia,tegra<chip>-dsi" 165 - compatible: "nvidia,tegra<chip>-dsi"
96 - reg: Physical base address and length of the controller's registers. 166 - reg: Physical base address and length of the controller's registers.
167 - clocks: Must contain an entry for each entry in clock-names.
168 See ../clocks/clock-bindings.txt for details.
169 - clock-names: Must include the following entries:
170 - dsi
171 This MUST be the first entry.
172 - parent
173 - resets: Must contain an entry for each entry in reset-names.
174 See ../reset/reset.txt for details.
175 - reset-names: Must include the following entries:
176 - dsi
97 177
98Example: 178Example:
99 179
@@ -105,6 +185,9 @@ Example:
105 reg = <0x50000000 0x00024000>; 185 reg = <0x50000000 0x00024000>;
106 interrupts = <0 65 0x04 /* mpcore syncpt */ 186 interrupts = <0 65 0x04 /* mpcore syncpt */
107 0 67 0x04>; /* mpcore general */ 187 0 67 0x04>; /* mpcore general */
188 clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
189 resets = <&tegra_car 28>;
190 reset-names = "host1x";
108 191
109 #address-cells = <1>; 192 #address-cells = <1>;
110 #size-cells = <1>; 193 #size-cells = <1>;
@@ -115,41 +198,64 @@ Example:
115 compatible = "nvidia,tegra20-mpe"; 198 compatible = "nvidia,tegra20-mpe";
116 reg = <0x54040000 0x00040000>; 199 reg = <0x54040000 0x00040000>;
117 interrupts = <0 68 0x04>; 200 interrupts = <0 68 0x04>;
201 clocks = <&tegra_car TEGRA20_CLK_MPE>;
202 resets = <&tegra_car 60>;
203 reset-names = "mpe";
118 }; 204 };
119 205
120 vi { 206 vi {
121 compatible = "nvidia,tegra20-vi"; 207 compatible = "nvidia,tegra20-vi";
122 reg = <0x54080000 0x00040000>; 208 reg = <0x54080000 0x00040000>;
123 interrupts = <0 69 0x04>; 209 interrupts = <0 69 0x04>;
210 clocks = <&tegra_car TEGRA20_CLK_VI>;
211 resets = <&tegra_car 100>;
212 reset-names = "vi";
124 }; 213 };
125 214
126 epp { 215 epp {
127 compatible = "nvidia,tegra20-epp"; 216 compatible = "nvidia,tegra20-epp";
128 reg = <0x540c0000 0x00040000>; 217 reg = <0x540c0000 0x00040000>;
129 interrupts = <0 70 0x04>; 218 interrupts = <0 70 0x04>;
219 clocks = <&tegra_car TEGRA20_CLK_EPP>;
220 resets = <&tegra_car 19>;
221 reset-names = "epp";
130 }; 222 };
131 223
132 isp { 224 isp {
133 compatible = "nvidia,tegra20-isp"; 225 compatible = "nvidia,tegra20-isp";
134 reg = <0x54100000 0x00040000>; 226 reg = <0x54100000 0x00040000>;
135 interrupts = <0 71 0x04>; 227 interrupts = <0 71 0x04>;
228 clocks = <&tegra_car TEGRA20_CLK_ISP>;
229 resets = <&tegra_car 23>;
230 reset-names = "isp";
136 }; 231 };
137 232
138 gr2d { 233 gr2d {
139 compatible = "nvidia,tegra20-gr2d"; 234 compatible = "nvidia,tegra20-gr2d";
140 reg = <0x54140000 0x00040000>; 235 reg = <0x54140000 0x00040000>;
141 interrupts = <0 72 0x04>; 236 interrupts = <0 72 0x04>;
237 clocks = <&tegra_car TEGRA20_CLK_GR2D>;
238 resets = <&tegra_car 21>;
239 reset-names = "2d";
142 }; 240 };
143 241
144 gr3d { 242 gr3d {
145 compatible = "nvidia,tegra20-gr3d"; 243 compatible = "nvidia,tegra20-gr3d";
146 reg = <0x54180000 0x00040000>; 244 reg = <0x54180000 0x00040000>;
245 clocks = <&tegra_car TEGRA20_CLK_GR3D>;
246 resets = <&tegra_car 24>;
247 reset-names = "3d";
147 }; 248 };
148 249
149 dc@54200000 { 250 dc@54200000 {
150 compatible = "nvidia,tegra20-dc"; 251 compatible = "nvidia,tegra20-dc";
151 reg = <0x54200000 0x00040000>; 252 reg = <0x54200000 0x00040000>;
152 interrupts = <0 73 0x04>; 253 interrupts = <0 73 0x04>;
254 clocks = <&tegra_car TEGRA20_CLK_DISP1>,
255 <&tegra_car TEGRA20_CLK_PLL_P>;
256 clock-names = "disp1", "parent";
257 resets = <&tegra_car 27>;
258 reset-names = "dc";
153 259
154 rgb { 260 rgb {
155 status = "disabled"; 261 status = "disabled";
@@ -160,6 +266,11 @@ Example:
160 compatible = "nvidia,tegra20-dc"; 266 compatible = "nvidia,tegra20-dc";
161 reg = <0x54240000 0x00040000>; 267 reg = <0x54240000 0x00040000>;
162 interrupts = <0 74 0x04>; 268 interrupts = <0 74 0x04>;
269 clocks = <&tegra_car TEGRA20_CLK_DISP2>,
270 <&tegra_car TEGRA20_CLK_PLL_P>;
271 clock-names = "disp2", "parent";
272 resets = <&tegra_car 26>;
273 reset-names = "dc";
163 274
164 rgb { 275 rgb {
165 status = "disabled"; 276 status = "disabled";
@@ -170,6 +281,11 @@ Example:
170 compatible = "nvidia,tegra20-hdmi"; 281 compatible = "nvidia,tegra20-hdmi";
171 reg = <0x54280000 0x00040000>; 282 reg = <0x54280000 0x00040000>;
172 interrupts = <0 75 0x04>; 283 interrupts = <0 75 0x04>;
284 clocks = <&tegra_car TEGRA20_CLK_HDMI>,
285 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
286 clock-names = "hdmi", "parent";
287 resets = <&tegra_car 51>;
288 reset-names = "hdmi";
173 status = "disabled"; 289 status = "disabled";
174 }; 290 };
175 291
@@ -177,12 +293,18 @@ Example:
177 compatible = "nvidia,tegra20-tvo"; 293 compatible = "nvidia,tegra20-tvo";
178 reg = <0x542c0000 0x00040000>; 294 reg = <0x542c0000 0x00040000>;
179 interrupts = <0 76 0x04>; 295 interrupts = <0 76 0x04>;
296 clocks = <&tegra_car TEGRA20_CLK_TVO>;
180 status = "disabled"; 297 status = "disabled";
181 }; 298 };
182 299
183 dsi { 300 dsi {
184 compatible = "nvidia,tegra20-dsi"; 301 compatible = "nvidia,tegra20-dsi";
185 reg = <0x54300000 0x00040000>; 302 reg = <0x54300000 0x00040000>;
303 clocks = <&tegra_car TEGRA20_CLK_DSI>,
304 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
305 clock-names = "dsi", "parent";
306 resets = <&tegra_car 48>;
307 reset-names = "dsi";
186 status = "disabled"; 308 status = "disabled";
187 }; 309 };
188 }; 310 };
diff --git a/Documentation/devicetree/bindings/i2c/i2c-omap.txt b/Documentation/devicetree/bindings/i2c/i2c-omap.txt
index 56564aa4b444..7e49839d4124 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-omap.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-omap.txt
@@ -1,7 +1,8 @@
1I2C for OMAP platforms 1I2C for OMAP platforms
2 2
3Required properties : 3Required properties :
4- compatible : Must be "ti,omap3-i2c" or "ti,omap4-i2c" 4- compatible : Must be "ti,omap2420-i2c", "ti,omap2430-i2c", "ti,omap3-i2c"
5 or "ti,omap4-i2c"
5- ti,hwmods : Must be "i2c<n>", n being the instance number (1-based) 6- ti,hwmods : Must be "i2c<n>", n being the instance number (1-based)
6- #address-cells = <1>; 7- #address-cells = <1>;
7- #size-cells = <0>; 8- #size-cells = <0>;
diff --git a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt
index ef77cc7a0e46..87507e9ce6db 100644
--- a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt
+++ b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt
@@ -39,12 +39,23 @@ Required properties:
39- interrupts: Should contain I2C controller interrupts. 39- interrupts: Should contain I2C controller interrupts.
40- address-cells: Address cells for I2C device address. 40- address-cells: Address cells for I2C device address.
41- size-cells: Size of the I2C device address. 41- size-cells: Size of the I2C device address.
42- clocks: Clock ID as per 42- clocks: Must contain an entry for each entry in clock-names.
43 Documentation/devicetree/bindings/clock/tegra<chip-id>.txt 43 See ../clocks/clock-bindings.txt for details.
44 for I2C controller. 44- clock-names: Must include the following entries:
45- clock-names: Name of the clock: 45 Tegra20/Tegra30:
46 Tegra20/Tegra30 I2C controller: "div-clk and "fast-clk". 46 - div-clk
47 Tegra114 I2C controller: "div-clk". 47 - fast-clk
48 Tegra114:
49 - div-clk
50- resets: Must contain an entry for each entry in reset-names.
51 See ../reset/reset.txt for details.
52- reset-names: Must include the following entries:
53 - i2c
54- dmas: Must contain an entry for each entry in clock-names.
55 See ../dma/dma.txt for details.
56- dma-names: Must include the following entries:
57 - rx
58 - tx
48 59
49Example: 60Example:
50 61
@@ -56,5 +67,9 @@ Example:
56 #size-cells = <0>; 67 #size-cells = <0>;
57 clocks = <&tegra_car 12>, <&tegra_car 124>; 68 clocks = <&tegra_car 12>, <&tegra_car 124>;
58 clock-names = "div-clk", "fast-clk"; 69 clock-names = "div-clk", "fast-clk";
70 resets = <&tegra_car 12>;
71 reset-names = "i2c";
72 dmas = <&apbdma 16>, <&apbdma 16>;
73 dma-names = "rx", "tx";
59 status = "disabled"; 74 status = "disabled";
60 }; 75 };
diff --git a/Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt b/Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt
index 2995fae7ee47..0382b8bd69c6 100644
--- a/Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt
+++ b/Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt
@@ -13,6 +13,12 @@ Required properties:
13 array of pin numbers which is used as column. 13 array of pin numbers which is used as column.
14- linux,keymap: The keymap for keys as described in the binding document 14- linux,keymap: The keymap for keys as described in the binding document
15 devicetree/bindings/input/matrix-keymap.txt. 15 devicetree/bindings/input/matrix-keymap.txt.
16- clocks: Must contain one entry, for the module clock.
17 See ../clocks/clock-bindings.txt for details.
18- resets: Must contain an entry for each entry in reset-names.
19 See ../reset/reset.txt for details.
20- reset-names: Must include the following entries:
21 - kbc
16 22
17Optional properties, in addition to those specified by the shared 23Optional properties, in addition to those specified by the shared
18matrix-keyboard bindings: 24matrix-keyboard bindings:
@@ -31,6 +37,9 @@ keyboard: keyboard {
31 compatible = "nvidia,tegra20-kbc"; 37 compatible = "nvidia,tegra20-kbc";
32 reg = <0x7000e200 0x100>; 38 reg = <0x7000e200 0x100>;
33 interrupts = <0 85 0x04>; 39 interrupts = <0 85 0x04>;
40 clocks = <&tegra_car 36>;
41 resets = <&tegra_car 36>;
42 reset-names = "kbc";
34 nvidia,ghost-filter; 43 nvidia,ghost-filter;
35 nvidia,debounce-delay-ms = <640>; 44 nvidia,debounce-delay-ms = <640>;
36 nvidia,kbc-row-pins = <0 1 2>; /* pin 0, 1, 2 as rows */ 45 nvidia,kbc-row-pins = <0 1 2>; /* pin 0, 1, 2 as rows */
diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
index c67b975c8906..532b1d440abc 100644
--- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
@@ -16,6 +16,8 @@ Required Properties:
16 specific extensions. 16 specific extensions.
17 - "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250 17 - "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250
18 specific extensions. 18 specific extensions.
19 - "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420
20 specific extensions.
19 21
20* samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface 22* samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
21 unit (ciu) clock. This property is applicable only for Exynos5 SoC's and 23 unit (ciu) clock. This property is applicable only for Exynos5 SoC's and
diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
index c6d7b11db9eb..f357c16ea815 100644
--- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
+++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
@@ -8,6 +8,12 @@ by mmc.txt and the properties used by the sdhci-tegra driver.
8 8
9Required properties: 9Required properties:
10- compatible : Should be "nvidia,<chip>-sdhci" 10- compatible : Should be "nvidia,<chip>-sdhci"
11- clocks : Must contain one entry, for the module clock.
12 See ../clocks/clock-bindings.txt for details.
13- resets : Must contain an entry for each entry in reset-names.
14 See ../reset/reset.txt for details.
15- reset-names : Must include the following entries:
16 - sdhci
11 17
12Optional properties: 18Optional properties:
13- power-gpios : Specify GPIOs for power control 19- power-gpios : Specify GPIOs for power control
@@ -18,6 +24,9 @@ sdhci@c8000200 {
18 compatible = "nvidia,tegra20-sdhci"; 24 compatible = "nvidia,tegra20-sdhci";
19 reg = <0xc8000200 0x200>; 25 reg = <0xc8000200 0x200>;
20 interrupts = <47>; 26 interrupts = <47>;
27 clocks = <&tegra_car 14>;
28 resets = <&tegra_car 14>;
29 reset-names = "sdhci";
21 cd-gpios = <&gpio 69 0>; /* gpio PI5 */ 30 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
22 wp-gpios = <&gpio 57 0>; /* gpio PH1 */ 31 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
23 power-gpios = <&gpio 155 0>; /* gpio PT3 */ 32 power-gpios = <&gpio 155 0>; /* gpio PT3 */
diff --git a/Documentation/devicetree/bindings/mmc/ti-omap.txt b/Documentation/devicetree/bindings/mmc/ti-omap.txt
new file mode 100644
index 000000000000..8de579969763
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/ti-omap.txt
@@ -0,0 +1,54 @@
1* TI MMC host controller for OMAP1 and 2420
2
3The MMC Host Controller on TI OMAP1 and 2420 family provides
4an interface for MMC, SD, and SDIO types of memory cards.
5
6This file documents differences between the core properties described
7by mmc.txt and the properties used by the omap mmc driver.
8
9Note that this driver will not work with omap2430 or later omaps,
10please see the omap hsmmc driver for the current omaps.
11
12Required properties:
13- compatible: Must be "ti,omap2420-mmc", for OMAP2420 controllers
14- ti,hwmods: For 2420, must be "msdi<n>", where n is controller
15 instance starting 1
16
17Examples:
18
19 msdi1: mmc@4809c000 {
20 compatible = "ti,omap2420-mmc";
21 ti,hwmods = "msdi1";
22 reg = <0x4809c000 0x80>;
23 interrupts = <83>;
24 dmas = <&sdma 61 &sdma 62>;
25 dma-names = "tx", "rx";
26 };
27
28* TI MMC host controller for OMAP1 and 2420
29
30The MMC Host Controller on TI OMAP1 and 2420 family provides
31an interface for MMC, SD, and SDIO types of memory cards.
32
33This file documents differences between the core properties described
34by mmc.txt and the properties used by the omap mmc driver.
35
36Note that this driver will not work with omap2430 or later omaps,
37please see the omap hsmmc driver for the current omaps.
38
39Required properties:
40- compatible: Must be "ti,omap2420-mmc", for OMAP2420 controllers
41- ti,hwmods: For 2420, must be "msdi<n>", where n is controller
42 instance starting 1
43
44Examples:
45
46 msdi1: mmc@4809c000 {
47 compatible = "ti,omap2420-mmc";
48 ti,hwmods = "msdi1";
49 reg = <0x4809c000 0x80>;
50 interrupts = <83>;
51 dmas = <&sdma 61 &sdma 62>;
52 dma-names = "tx", "rx";
53 };
54
diff --git a/Documentation/devicetree/bindings/net/fsl-fec.txt b/Documentation/devicetree/bindings/net/fsl-fec.txt
index d53639221403..845ff848d895 100644
--- a/Documentation/devicetree/bindings/net/fsl-fec.txt
+++ b/Documentation/devicetree/bindings/net/fsl-fec.txt
@@ -15,6 +15,7 @@ Optional properties:
15 only if property "phy-reset-gpios" is available. Missing the property 15 only if property "phy-reset-gpios" is available. Missing the property
16 will have the duration be 1 millisecond. Numbers greater than 1000 are 16 will have the duration be 1 millisecond. Numbers greater than 1000 are
17 invalid and 1 millisecond will be used instead. 17 invalid and 1 millisecond will be used instead.
18- phy-supply: regulator that powers the Ethernet PHY.
18 19
19Example: 20Example:
20 21
@@ -25,4 +26,5 @@ ethernet@83fec000 {
25 phy-mode = "mii"; 26 phy-mode = "mii";
26 phy-reset-gpios = <&gpio2 14 0>; /* GPIO2_14 */ 27 phy-reset-gpios = <&gpio2 14 0>; /* GPIO2_14 */
27 local-mac-address = [00 04 9F 01 1B B9]; 28 local-mac-address = [00 04 9F 01 1B B9];
29 phy-supply = <&reg_fec_supply>;
28}; 30};
diff --git a/Documentation/devicetree/bindings/nvec/nvidia,nvec.txt b/Documentation/devicetree/bindings/nvec/nvidia,nvec.txt
index 5aeee53ff9f4..5ae601e7f51f 100644
--- a/Documentation/devicetree/bindings/nvec/nvidia,nvec.txt
+++ b/Documentation/devicetree/bindings/nvec/nvidia,nvec.txt
@@ -7,3 +7,15 @@ Required properties:
7- clock-frequency : the frequency of the i2c bus 7- clock-frequency : the frequency of the i2c bus
8- gpios : the gpio used for ec request 8- gpios : the gpio used for ec request
9- slave-addr: the i2c address of the slave controller 9- slave-addr: the i2c address of the slave controller
10- clocks : Must contain an entry for each entry in clock-names.
11 See ../clocks/clock-bindings.txt for details.
12- clock-names : Must include the following entries:
13 Tegra20/Tegra30:
14 - div-clk
15 - fast-clk
16 Tegra114:
17 - div-clk
18- resets : Must contain an entry for each entry in reset-names.
19 See ../reset/reset.txt for details.
20- reset-names : Must include the following entries:
21 - i2c
diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
index 6b7510775c50..24cee06915c9 100644
--- a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
@@ -42,14 +42,19 @@ Required properties:
42 - 0xc2000000: prefetchable memory region 42 - 0xc2000000: prefetchable memory region
43 Please refer to the standard PCI bus binding document for a more detailed 43 Please refer to the standard PCI bus binding document for a more detailed
44 explanation. 44 explanation.
45- clocks: List of clock inputs of the controller. Must contain an entry for 45- clocks: Must contain an entry for each entry in clock-names.
46 each entry in the clock-names property. 46 See ../clocks/clock-bindings.txt for details.
47- clock-names: Must include the following entries: 47- clock-names: Must include the following entries:
48 "pex": The Tegra clock of that name 48 - pex
49 "afi": The Tegra clock of that name 49 - afi
50 "pcie_xclk": The Tegra clock of that name 50 - pll_e
51 "pll_e": The Tegra clock of that name 51 - cml (not required for Tegra20)
52 "cml": The Tegra clock of that name (not required for Tegra20) 52- resets: Must contain an entry for each entry in reset-names.
53 See ../reset/reset.txt for details.
54- reset-names: Must include the following entries:
55 - pex
56 - afi
57 - pcie_x
53 58
54Root ports are defined as subnodes of the PCIe controller node. 59Root ports are defined as subnodes of the PCIe controller node.
55 60
@@ -91,9 +96,10 @@ SoC DTSI:
91 0x82000000 0 0xa0000000 0xa0000000 0 0x10000000 /* non-prefetchable memory */ 96 0x82000000 0 0xa0000000 0xa0000000 0 0x10000000 /* non-prefetchable memory */
92 0xc2000000 0 0xb0000000 0xb0000000 0 0x10000000>; /* prefetchable memory */ 97 0xc2000000 0 0xb0000000 0xb0000000 0 0x10000000>; /* prefetchable memory */
93 98
94 clocks = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 74>, 99 clocks = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 118>;
95 <&tegra_car 118>; 100 clock-names = "pex", "afi", "pll_e";
96 clock-names = "pex", "afi", "pcie_xclk", "pll_e"; 101 resets = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 74>;
102 reset-names = "pex", "afi", "pcie_x";
97 status = "disabled"; 103 status = "disabled";
98 104
99 pci@1,0 { 105 pci@1,0 {
diff --git a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
index c3fc57af8772..c7ea9d4a988b 100644
--- a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
+++ b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
@@ -7,6 +7,12 @@ Required properties:
7- reg: physical base address and length of the controller's registers 7- reg: physical base address and length of the controller's registers
8- #pwm-cells: should be 2. See pwm.txt in this directory for a description of 8- #pwm-cells: should be 2. See pwm.txt in this directory for a description of
9 the cells format. 9 the cells format.
10- clocks: Must contain one entry, for the module clock.
11 See ../clocks/clock-bindings.txt for details.
12- resets: Must contain an entry for each entry in reset-names.
13 See ../reset/reset.txt for details.
14- reset-names: Must include the following entries:
15 - pwm
10 16
11Example: 17Example:
12 18
@@ -14,4 +20,7 @@ Example:
14 compatible = "nvidia,tegra20-pwm"; 20 compatible = "nvidia,tegra20-pwm";
15 reg = <0x7000a000 0x100>; 21 reg = <0x7000a000 0x100>;
16 #pwm-cells = <2>; 22 #pwm-cells = <2>;
23 clocks = <&tegra_car 17>;
24 resets = <&tegra_car 17>;
25 reset-names = "pwm";
17 }; 26 };
diff --git a/Documentation/devicetree/bindings/rng/qcom,prng.txt b/Documentation/devicetree/bindings/rng/qcom,prng.txt
new file mode 100644
index 000000000000..8e5853c2879b
--- /dev/null
+++ b/Documentation/devicetree/bindings/rng/qcom,prng.txt
@@ -0,0 +1,17 @@
1Qualcomm MSM pseudo random number generator.
2
3Required properties:
4
5- compatible : should be "qcom,prng"
6- reg : specifies base physical address and size of the registers map
7- clocks : phandle to clock-controller plus clock-specifier pair
8- clock-names : "core" clocks all registers, FIFO and circuits in PRNG IP block
9
10Example:
11
12 rng@f9bff000 {
13 compatible = "qcom,prng";
14 reg = <0xf9bff000 0x200>;
15 clocks = <&clock GCC_PRNG_AHB_CLK>;
16 clock-names = "core";
17 };
diff --git a/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt b/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt
index 93f45e9dce7c..652d1ff2e8be 100644
--- a/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt
+++ b/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt
@@ -9,6 +9,8 @@ Required properties:
9- compatible : should be "nvidia,tegra20-rtc". 9- compatible : should be "nvidia,tegra20-rtc".
10- reg : Specifies base physical address and size of the registers. 10- reg : Specifies base physical address and size of the registers.
11- interrupts : A single interrupt specifier. 11- interrupts : A single interrupt specifier.
12- clocks : Must contain one entry, for the module clock.
13 See ../clocks/clock-bindings.txt for details.
12 14
13Example: 15Example:
14 16
@@ -16,4 +18,5 @@ timer {
16 compatible = "nvidia,tegra20-rtc"; 18 compatible = "nvidia,tegra20-rtc";
17 reg = <0x7000e000 0x100>; 19 reg = <0x7000e000 0x100>;
18 interrupts = <0 2 0x04>; 20 interrupts = <0 2 0x04>;
21 clocks = <&tegra_car 4>;
19}; 22};
diff --git a/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt b/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt
index 392a4493eebd..845850caf088 100644
--- a/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt
+++ b/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt
@@ -4,8 +4,17 @@ Required properties:
4- compatible : should be "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart". 4- compatible : should be "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
5- reg: Should contain UART controller registers location and length. 5- reg: Should contain UART controller registers location and length.
6- interrupts: Should contain UART controller interrupts. 6- interrupts: Should contain UART controller interrupts.
7- nvidia,dma-request-selector : The Tegra DMA controller's phandle and 7- clocks: Must contain one entry, for the module clock.
8 request selector for this UART controller. 8 See ../clocks/clock-bindings.txt for details.
9- resets : Must contain an entry for each entry in reset-names.
10 See ../reset/reset.txt for details.
11- reset-names : Must include the following entries:
12 - serial
13- dmas : Must contain an entry for each entry in clock-names.
14 See ../dma/dma.txt for details.
15- dma-names : Must include the following entries:
16 - rx
17 - tx
9 18
10Optional properties: 19Optional properties:
11- nvidia,enable-modem-interrupt: Enable modem interrupts. Should be enable 20- nvidia,enable-modem-interrupt: Enable modem interrupts. Should be enable
@@ -18,7 +27,11 @@ serial@70006000 {
18 reg = <0x70006000 0x40>; 27 reg = <0x70006000 0x40>;
19 reg-shift = <2>; 28 reg-shift = <2>;
20 interrupts = <0 36 0x04>; 29 interrupts = <0 36 0x04>;
21 nvidia,dma-request-selector = <&apbdma 8>;
22 nvidia,enable-modem-interrupt; 30 nvidia,enable-modem-interrupt;
31 clocks = <&tegra_car 6>;
32 resets = <&tegra_car 6>;
33 reset-names = "serial";
34 dmas = <&apbdma 8>, <&apbdma 8>;
35 dma-names = "rx", "tx";
23 status = "disabled"; 36 status = "disabled";
24}; 37};
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-alc5632.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-alc5632.txt
index 8b8903ef0800..57f40f93453e 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-alc5632.txt
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-alc5632.txt
@@ -3,10 +3,11 @@ NVIDIA Tegra audio complex
3Required properties: 3Required properties:
4- compatible : "nvidia,tegra-audio-alc5632" 4- compatible : "nvidia,tegra-audio-alc5632"
5- clocks : Must contain an entry for each entry in clock-names. 5- clocks : Must contain an entry for each entry in clock-names.
6 See ../clocks/clock-bindings.txt for details.
6- clock-names : Must include the following entries: 7- clock-names : Must include the following entries:
7 "pll_a" (The Tegra clock of that name), 8 - pll_a
8 "pll_a_out0" (The Tegra clock of that name), 9 - pll_a_out0
9 "mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk) 10 - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
10- nvidia,model : The user-visible name of this sound complex. 11- nvidia,model : The user-visible name of this sound complex.
11- nvidia,audio-routing : A list of the connections between audio components. 12- nvidia,audio-routing : A list of the connections between audio components.
12 Each entry is a pair of strings, the first being the connection's sink, 13 Each entry is a pair of strings, the first being the connection's sink,
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-rt5640.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-rt5640.txt
index dc6224994d69..7788808dcd0b 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-rt5640.txt
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-rt5640.txt
@@ -3,10 +3,11 @@ NVIDIA Tegra audio complex, with RT5640 CODEC
3Required properties: 3Required properties:
4- compatible : "nvidia,tegra-audio-rt5640" 4- compatible : "nvidia,tegra-audio-rt5640"
5- clocks : Must contain an entry for each entry in clock-names. 5- clocks : Must contain an entry for each entry in clock-names.
6 See ../clocks/clock-bindings.txt for details.
6- clock-names : Must include the following entries: 7- clock-names : Must include the following entries:
7 "pll_a" (The Tegra clock of that name), 8 - pll_a
8 "pll_a_out0" (The Tegra clock of that name), 9 - pll_a_out0
9 "mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk) 10 - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
10- nvidia,model : The user-visible name of this sound complex. 11- nvidia,model : The user-visible name of this sound complex.
11- nvidia,audio-routing : A list of the connections between audio components. 12- nvidia,audio-routing : A list of the connections between audio components.
12 Each entry is a pair of strings, the first being the connection's sink, 13 Each entry is a pair of strings, the first being the connection's sink,
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8753.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8753.txt
index aab6ce0ad2fc..96f6a57dd6b4 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8753.txt
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8753.txt
@@ -3,10 +3,11 @@ NVIDIA Tegra audio complex
3Required properties: 3Required properties:
4- compatible : "nvidia,tegra-audio-wm8753" 4- compatible : "nvidia,tegra-audio-wm8753"
5- clocks : Must contain an entry for each entry in clock-names. 5- clocks : Must contain an entry for each entry in clock-names.
6 See ../clocks/clock-bindings.txt for details.
6- clock-names : Must include the following entries: 7- clock-names : Must include the following entries:
7 "pll_a" (The Tegra clock of that name), 8 - pll_a
8 "pll_a_out0" (The Tegra clock of that name), 9 - pll_a_out0
9 "mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk) 10 - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
10- nvidia,model : The user-visible name of this sound complex. 11- nvidia,model : The user-visible name of this sound complex.
11- nvidia,audio-routing : A list of the connections between audio components. 12- nvidia,audio-routing : A list of the connections between audio components.
12 Each entry is a pair of strings, the first being the connection's sink, 13 Each entry is a pair of strings, the first being the connection's sink,
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8903.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8903.txt
index 4b44dfb6ca0d..b795d282818d 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8903.txt
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8903.txt
@@ -3,10 +3,11 @@ NVIDIA Tegra audio complex
3Required properties: 3Required properties:
4- compatible : "nvidia,tegra-audio-wm8903" 4- compatible : "nvidia,tegra-audio-wm8903"
5- clocks : Must contain an entry for each entry in clock-names. 5- clocks : Must contain an entry for each entry in clock-names.
6 See ../clocks/clock-bindings.txt for details.
6- clock-names : Must include the following entries: 7- clock-names : Must include the following entries:
7 "pll_a" (The Tegra clock of that name), 8 - pll_a
8 "pll_a_out0" (The Tegra clock of that name), 9 - pll_a_out0
9 "mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk) 10 - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
10- nvidia,model : The user-visible name of this sound complex. 11- nvidia,model : The user-visible name of this sound complex.
11- nvidia,audio-routing : A list of the connections between audio components. 12- nvidia,audio-routing : A list of the connections between audio components.
12 Each entry is a pair of strings, the first being the connection's sink, 13 Each entry is a pair of strings, the first being the connection's sink,
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm9712.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm9712.txt
index ad589b163639..436f6cd9d07c 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm9712.txt
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm9712.txt
@@ -3,10 +3,11 @@ NVIDIA Tegra audio complex
3Required properties: 3Required properties:
4- compatible : "nvidia,tegra-audio-wm9712" 4- compatible : "nvidia,tegra-audio-wm9712"
5- clocks : Must contain an entry for each entry in clock-names. 5- clocks : Must contain an entry for each entry in clock-names.
6 See ../clocks/clock-bindings.txt for details.
6- clock-names : Must include the following entries: 7- clock-names : Must include the following entries:
7 "pll_a" (The Tegra clock of that name), 8 - pll_a
8 "pll_a_out0" (The Tegra clock of that name), 9 - pll_a_out0
9 "mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk) 10 - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
10- nvidia,model : The user-visible name of this sound complex. 11- nvidia,model : The user-visible name of this sound complex.
11- nvidia,audio-routing : A list of the connections between audio components. 12- nvidia,audio-routing : A list of the connections between audio components.
12 Each entry is a pair of strings, the first being the connection's sink, 13 Each entry is a pair of strings, the first being the connection's sink,
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
index c1454979c1ef..eaf00102d92c 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
@@ -4,19 +4,33 @@ Required properties:
4- compatible : "nvidia,tegra20-ac97" 4- compatible : "nvidia,tegra20-ac97"
5- reg : Should contain AC97 controller registers location and length 5- reg : Should contain AC97 controller registers location and length
6- interrupts : Should contain AC97 interrupt 6- interrupts : Should contain AC97 interrupt
7- nvidia,dma-request-selector : The Tegra DMA controller's phandle and 7- resets : Must contain an entry for each entry in reset-names.
8 request selector for the AC97 controller 8 See ../reset/reset.txt for details.
9- reset-names : Must include the following entries:
10 - ac97
11- dmas : Must contain an entry for each entry in clock-names.
12 See ../dma/dma.txt for details.
13- dma-names : Must include the following entries:
14 - rx
15 - tx
16- clocks : Must contain one entry, for the module clock.
17 See ../clocks/clock-bindings.txt for details.
9- nvidia,codec-reset-gpio : The Tegra GPIO controller's phandle and the number 18- nvidia,codec-reset-gpio : The Tegra GPIO controller's phandle and the number
10 of the GPIO used to reset the external AC97 codec 19 of the GPIO used to reset the external AC97 codec
11- nvidia,codec-sync-gpio : The Tegra GPIO controller's phandle and the number 20- nvidia,codec-sync-gpio : The Tegra GPIO controller's phandle and the number
12 of the GPIO corresponding with the AC97 DAP _FS line 21 of the GPIO corresponding with the AC97 DAP _FS line
22
13Example: 23Example:
14 24
15ac97@70002000 { 25ac97@70002000 {
16 compatible = "nvidia,tegra20-ac97"; 26 compatible = "nvidia,tegra20-ac97";
17 reg = <0x70002000 0x200>; 27 reg = <0x70002000 0x200>;
18 interrupts = <0 81 0x04>; 28 interrupts = <0 81 0x04>;
19 nvidia,dma-request-selector = <&apbdma 12>;
20 nvidia,codec-reset-gpio = <&gpio 170 0>; 29 nvidia,codec-reset-gpio = <&gpio 170 0>;
21 nvidia,codec-sync-gpio = <&gpio 120 0>; 30 nvidia,codec-sync-gpio = <&gpio 120 0>;
31 clocks = <&tegra_car 3>;
32 resets = <&tegra_car 3>;
33 reset-names = "ac97";
34 dmas = <&apbdma 12>, <&apbdma 12>;
35 dma-names = "rx", "tx";
22}; 36};
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt
index 0df2b5c816e3..dc30c6bfbe95 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt
@@ -4,8 +4,17 @@ Required properties:
4- compatible : "nvidia,tegra20-i2s" 4- compatible : "nvidia,tegra20-i2s"
5- reg : Should contain I2S registers location and length 5- reg : Should contain I2S registers location and length
6- interrupts : Should contain I2S interrupt 6- interrupts : Should contain I2S interrupt
7- nvidia,dma-request-selector : The Tegra DMA controller's phandle and 7- resets : Must contain an entry for each entry in reset-names.
8 request selector for this I2S controller 8 See ../reset/reset.txt for details.
9- reset-names : Must include the following entries:
10 - i2s
11- dmas : Must contain an entry for each entry in clock-names.
12 See ../dma/dma.txt for details.
13- dma-names : Must include the following entries:
14 - rx
15 - tx
16- clocks : Must contain one entry, for the module clock.
17 See ../clocks/clock-bindings.txt for details.
9 18
10Example: 19Example:
11 20
@@ -13,5 +22,9 @@ i2s@70002800 {
13 compatible = "nvidia,tegra20-i2s"; 22 compatible = "nvidia,tegra20-i2s";
14 reg = <0x70002800 0x200>; 23 reg = <0x70002800 0x200>;
15 interrupts = < 45 >; 24 interrupts = < 45 >;
16 nvidia,dma-request-selector = < &apbdma 2 >; 25 clocks = <&tegra_car 11>;
26 resets = <&tegra_car 11>;
27 reset-names = "i2s";
28 dmas = <&apbdma 21>, <&apbdma 21>;
29 dma-names = "rx", "tx";
17}; 30};
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
index 0e5c12c66523..946e2ac46091 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
@@ -7,18 +7,48 @@ Required properties:
7 - Tegra30 requires 2 entries, for the APBIF and AHUB/AUDIO register blocks. 7 - Tegra30 requires 2 entries, for the APBIF and AHUB/AUDIO register blocks.
8 - Tegra114 requires an additional entry, for the APBIF2 register block. 8 - Tegra114 requires an additional entry, for the APBIF2 register block.
9- interrupts : Should contain AHUB interrupt 9- interrupts : Should contain AHUB interrupt
10- nvidia,dma-request-selector : A list of the DMA channel specifiers. Each 10- clocks : Must contain an entry for each entry in clock-names.
11 entry contains the Tegra DMA controller's phandle and request selector. 11 See ../clocks/clock-bindings.txt for details.
12 If a single entry is present, the request selectors for the channels are
13 assumed to be contiguous, and increment from this value.
14 If multiple values are given, one value must be given per channel.
15- clocks : Must contain an entry for each required entry in clock-names.
16- clock-names : Must include the following entries: 12- clock-names : Must include the following entries:
17 - Tegra30: Requires d_audio, apbif, i2s0, i2s1, i2s2, i2s3, i2s4, dam0, 13 - d_audio
18 dam1, dam2, spdif_in. 14 - apbif
19 - Tegra114: Additionally requires amx, adx. 15- resets : Must contain an entry for each entry in reset-names.
16 See ../reset/reset.txt for details.
17- reset-names : Must include the following entries:
18 Tegra30 and later:
19 - d_audio
20 - apbif
21 - i2s0
22 - i2s1
23 - i2s2
24 - i2s3
25 - i2s4
26 - dam0
27 - dam1
28 - dam2
29 - spdif
30 Tegra114 and later additionally require:
31 - amx
32 - adx
33 Tegra124 and later additionally require:
34 - amx1
35 - adx1
36 - afc0
37 - afc1
38 - afc2
39 - afc3
40 - afc4
41 - afc5
20- ranges : The bus address mapping for the configlink register bus. 42- ranges : The bus address mapping for the configlink register bus.
21 Can be empty since the mapping is 1:1. 43 Can be empty since the mapping is 1:1.
44- dmas : Must contain an entry for each entry in clock-names.
45 See ../dma/dma.txt for details.
46- dma-names : Must include the following entries:
47 - rx0 .. rx<n>
48 - tx0 .. tx<n>
49 ... where n is:
50 Tegra30: 3
51 Tegra114, Tegra124: 9
22- #address-cells : For the configlink bus. Should be <1>; 52- #address-cells : For the configlink bus. Should be <1>;
23- #size-cells : For the configlink bus. Should be <1>. 53- #size-cells : For the configlink bus. Should be <1>.
24 54
@@ -35,13 +65,20 @@ ahub@70080000 {
35 reg = <0x70080000 0x200 0x70080200 0x100>; 65 reg = <0x70080000 0x200 0x70080200 0x100>;
36 interrupts = < 0 103 0x04 >; 66 interrupts = < 0 103 0x04 >;
37 nvidia,dma-request-selector = <&apbdma 1>; 67 nvidia,dma-request-selector = <&apbdma 1>;
38 clocks = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>, 68 clocks = <&tegra_car 106>, <&tegra_car 107>;
69 clock-names = "d_audio", "apbif";
70 resets = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>,
39 <&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>, 71 <&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>,
40 <&tegra_car 102>, <&tegra_car 108>, <&tegra_car 109>, 72 <&tegra_car 102>, <&tegra_car 108>, <&tegra_car 109>,
41 <&tegra_car 110>, <&tegra_car 162>; 73 <&tegra_car 110>, <&tegra_car 10>;
42 clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", 74 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
43 "i2s3", "i2s4", "dam0", "dam1", "dam2", 75 "i2s3", "i2s4", "dam0", "dam1", "dam2",
44 "spdif_in"; 76 "spdif";
77 dmas = <&apbdma 1>, <&apbdma 1>;
78 <&apbdma 2>, <&apbdma 2>;
79 <&apbdma 3>, <&apbdma 3>;
80 <&apbdma 4>, <&apbdma 4>;
81 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", "rx3", "tx3";
45 ranges; 82 ranges;
46 #address-cells = <1>; 83 #address-cells = <1>;
47 #size-cells = <1>; 84 #size-cells = <1>;
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra30-i2s.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra30-i2s.txt
index dfa6c037124a..0c113ffe3814 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra30-i2s.txt
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra30-i2s.txt
@@ -3,13 +3,22 @@ NVIDIA Tegra30 I2S controller
3Required properties: 3Required properties:
4- compatible : "nvidia,tegra30-i2s" 4- compatible : "nvidia,tegra30-i2s"
5- reg : Should contain I2S registers location and length 5- reg : Should contain I2S registers location and length
6- clocks : Must contain one entry, for the module clock.
7 See ../clocks/clock-bindings.txt for details.
8- resets : Must contain an entry for each entry in reset-names.
9 See ../reset/reset.txt for details.
10- reset-names : Must include the following entries:
11 - i2s
6- nvidia,ahub-cif-ids : The list of AHUB CIF IDs for this port, rx (playback) 12- nvidia,ahub-cif-ids : The list of AHUB CIF IDs for this port, rx (playback)
7 first, tx (capture) second. See nvidia,tegra30-ahub.txt for values. 13 first, tx (capture) second. See nvidia,tegra30-ahub.txt for values.
8 14
9Example: 15Example:
10 16
11i2s@70002800 { 17i2s@70080300 {
12 compatible = "nvidia,tegra30-i2s"; 18 compatible = "nvidia,tegra30-i2s";
13 reg = <0x70080300 0x100>; 19 reg = <0x70080300 0x100>;
14 nvidia,ahub-cif-ids = <4 4>; 20 nvidia,ahub-cif-ids = <4 4>;
21 clocks = <&tegra_car 11>;
22 resets = <&tegra_car 11>;
23 reset-names = "i2s";
15}; 24};
diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
index 91ff771c7e77..7ea701e07dc2 100644
--- a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
+++ b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt
@@ -4,10 +4,19 @@ Required properties:
4- compatible : should be "nvidia,tegra114-spi". 4- compatible : should be "nvidia,tegra114-spi".
5- reg: Should contain SPI registers location and length. 5- reg: Should contain SPI registers location and length.
6- interrupts: Should contain SPI interrupts. 6- interrupts: Should contain SPI interrupts.
7- nvidia,dma-request-selector : The Tegra DMA controller's phandle and 7- clock-names : Must include the following entries:
8 request selector for this SPI controller. 8 - spi
9- This is also require clock named "spi" as per binding document 9- resets : Must contain an entry for each entry in reset-names.
10 Documentation/devicetree/bindings/clock/clock-bindings.txt 10 See ../reset/reset.txt for details.
11- reset-names : Must include the following entries:
12 - spi
13- dmas : Must contain an entry for each entry in clock-names.
14 See ../dma/dma.txt for details.
15- dma-names : Must include the following entries:
16 - rx
17 - tx
18- clocks : Must contain an entry for each entry in clock-names.
19 See ../clocks/clock-bindings.txt for details.
11 20
12Recommended properties: 21Recommended properties:
13- spi-max-frequency: Definition as per 22- spi-max-frequency: Definition as per
@@ -18,9 +27,14 @@ spi@7000d600 {
18 compatible = "nvidia,tegra114-spi"; 27 compatible = "nvidia,tegra114-spi";
19 reg = <0x7000d600 0x200>; 28 reg = <0x7000d600 0x200>;
20 interrupts = <0 82 0x04>; 29 interrupts = <0 82 0x04>;
21 nvidia,dma-request-selector = <&apbdma 16>;
22 spi-max-frequency = <25000000>; 30 spi-max-frequency = <25000000>;
23 #address-cells = <1>; 31 #address-cells = <1>;
24 #size-cells = <0>; 32 #size-cells = <0>;
33 clocks = <&tegra_car 44>;
34 clock-names = "spi";
35 resets = <&tegra_car 44>;
36 reset-names = "spi";
37 dmas = <&apbdma 16>, <&apbdma 16>;
38 dma-names = "rx", "tx";
25 status = "disabled"; 39 status = "disabled";
26}; 40};
diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
index 7b53da5cb75b..bdf08e6dec9b 100644
--- a/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
+++ b/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
@@ -4,8 +4,17 @@ Required properties:
4- compatible : should be "nvidia,tegra20-sflash". 4- compatible : should be "nvidia,tegra20-sflash".
5- reg: Should contain SFLASH registers location and length. 5- reg: Should contain SFLASH registers location and length.
6- interrupts: Should contain SFLASH interrupts. 6- interrupts: Should contain SFLASH interrupts.
7- nvidia,dma-request-selector : The Tegra DMA controller's phandle and 7- clocks : Must contain one entry, for the module clock.
8 request selector for this SFLASH controller. 8 See ../clocks/clock-bindings.txt for details.
9- resets : Must contain an entry for each entry in reset-names.
10 See ../reset/reset.txt for details.
11- reset-names : Must include the following entries:
12 - spi
13- dmas : Must contain an entry for each entry in clock-names.
14 See ../dma/dma.txt for details.
15- dma-names : Must include the following entries:
16 - rx
17 - tx
9 18
10Recommended properties: 19Recommended properties:
11- spi-max-frequency: Definition as per 20- spi-max-frequency: Definition as per
@@ -17,10 +26,13 @@ spi@7000c380 {
17 compatible = "nvidia,tegra20-sflash"; 26 compatible = "nvidia,tegra20-sflash";
18 reg = <0x7000c380 0x80>; 27 reg = <0x7000c380 0x80>;
19 interrupts = <0 39 0x04>; 28 interrupts = <0 39 0x04>;
20 nvidia,dma-request-selector = <&apbdma 16>;
21 spi-max-frequency = <25000000>; 29 spi-max-frequency = <25000000>;
22 #address-cells = <1>; 30 #address-cells = <1>;
23 #size-cells = <0>; 31 #size-cells = <0>;
32 clocks = <&tegra_car 43>;
33 resets = <&tegra_car 43>;
34 reset-names = "spi";
35 dmas = <&apbdma 11>, <&apbdma 11>;
36 dma-names = "rx", "tx";
24 status = "disabled"; 37 status = "disabled";
25}; 38};
26
diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt
index eefe15e3d95e..5db9144a33c8 100644
--- a/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt
+++ b/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt
@@ -4,8 +4,17 @@ Required properties:
4- compatible : should be "nvidia,tegra20-slink", "nvidia,tegra30-slink". 4- compatible : should be "nvidia,tegra20-slink", "nvidia,tegra30-slink".
5- reg: Should contain SLINK registers location and length. 5- reg: Should contain SLINK registers location and length.
6- interrupts: Should contain SLINK interrupts. 6- interrupts: Should contain SLINK interrupts.
7- nvidia,dma-request-selector : The Tegra DMA controller's phandle and 7- clocks : Must contain one entry, for the module clock.
8 request selector for this SLINK controller. 8 See ../clocks/clock-bindings.txt for details.
9- resets : Must contain an entry for each entry in reset-names.
10 See ../reset/reset.txt for details.
11- reset-names : Must include the following entries:
12 - spi
13- dmas : Must contain an entry for each entry in clock-names.
14 See ../dma/dma.txt for details.
15- dma-names : Must include the following entries:
16 - rx
17 - tx
9 18
10Recommended properties: 19Recommended properties:
11- spi-max-frequency: Definition as per 20- spi-max-frequency: Definition as per
@@ -17,10 +26,13 @@ spi@7000d600 {
17 compatible = "nvidia,tegra20-slink"; 26 compatible = "nvidia,tegra20-slink";
18 reg = <0x7000d600 0x200>; 27 reg = <0x7000d600 0x200>;
19 interrupts = <0 82 0x04>; 28 interrupts = <0 82 0x04>;
20 nvidia,dma-request-selector = <&apbdma 16>;
21 spi-max-frequency = <25000000>; 29 spi-max-frequency = <25000000>;
22 #address-cells = <1>; 30 #address-cells = <1>;
23 #size-cells = <0>; 31 #size-cells = <0>;
32 clocks = <&tegra_car 44>;
33 resets = <&tegra_car 44>;
34 reset-names = "spi";
35 dmas = <&apbdma 16>, <&apbdma 16>;
36 dma-names = "rx", "tx";
24 status = "disabled"; 37 status = "disabled";
25}; 38};
26
diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra20-spi.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra20-spi.txt
deleted file mode 100644
index 6b9e51896693..000000000000
--- a/Documentation/devicetree/bindings/spi/nvidia,tegra20-spi.txt
+++ /dev/null
@@ -1,5 +0,0 @@
1NVIDIA Tegra 2 SPI device
2
3Required properties:
4- compatible : should be "nvidia,tegra20-spi".
5- gpios : should specify GPIOs used for chipselect.
diff --git a/Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt b/Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt
index e019fdc38773..4a864bd10d3d 100644
--- a/Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt
+++ b/Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt
@@ -8,6 +8,8 @@ Required properties:
8- compatible : should be "nvidia,tegra20-timer". 8- compatible : should be "nvidia,tegra20-timer".
9- reg : Specifies base physical address and size of the registers. 9- reg : Specifies base physical address and size of the registers.
10- interrupts : A list of 4 interrupts; one per timer channel. 10- interrupts : A list of 4 interrupts; one per timer channel.
11- clocks : Must contain one entry, for the module clock.
12 See ../clocks/clock-bindings.txt for details.
11 13
12Example: 14Example:
13 15
@@ -18,4 +20,5 @@ timer {
18 0 1 0x04 20 0 1 0x04
19 0 41 0x04 21 0 41 0x04
20 0 42 0x04>; 22 0 42 0x04>;
23 clocks = <&tegra_car 132>;
21}; 24};
diff --git a/Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt b/Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt
index 906109d4c593..b5082a1cf461 100644
--- a/Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt
+++ b/Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt
@@ -10,6 +10,8 @@ Required properties:
10- reg : Specifies base physical address and size of the registers. 10- reg : Specifies base physical address and size of the registers.
11- interrupts : A list of 6 interrupts; one per each of timer channels 1 11- interrupts : A list of 6 interrupts; one per each of timer channels 1
12 through 5, and one for the shared interrupt for the remaining channels. 12 through 5, and one for the shared interrupt for the remaining channels.
13- clocks : Must contain one entry, for the module clock.
14 See ../clocks/clock-bindings.txt for details.
13 15
14timer { 16timer {
15 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer"; 17 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
@@ -20,4 +22,5 @@ timer {
20 0 42 0x04 22 0 42 0x04
21 0 121 0x04 23 0 121 0x04
22 0 122 0x04>; 24 0 122 0x04>;
25 clocks = <&tegra_car 214>;
23}; 26};
diff --git a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
index b5a86d20ee36..167d5dab9f64 100644
--- a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
+++ b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
@@ -31,38 +31,58 @@ Required properties:
31 7: .. 31 7: ..
32 i: Local Timer Interrupt n 32 i: Local Timer Interrupt n
33 33
34Example 1: In this example, the system uses only the first global timer 34 For MCT block that uses a per-processor interrupt for local timers, such
35 interrupt generated by MCT and the remaining three global timer 35 as ones compatible with "samsung,exynos4412-mct", only one local timer
36 interrupts are unused. Two local timer interrupts have been 36 interrupt might be specified, meaning that all local timers use the same
37 specified. 37 per processor interrupt.
38
39Example 1: In this example, the IP contains two local timers, using separate
40 interrupts, so two local timer interrupts have been specified,
41 in addition to four global timer interrupts.
38 42
39 mct@10050000 { 43 mct@10050000 {
40 compatible = "samsung,exynos4210-mct"; 44 compatible = "samsung,exynos4210-mct";
41 reg = <0x10050000 0x800>; 45 reg = <0x10050000 0x800>;
42 interrupts = <0 57 0>, <0 0 0>, <0 0 0>, <0 0 0>, 46 interrupts = <0 57 0>, <0 69 0>, <0 70 0>, <0 71 0>,
43 <0 42 0>, <0 48 0>; 47 <0 42 0>, <0 48 0>;
44 }; 48 };
45 49
46Example 2: In this example, the MCT global and local timer interrupts are 50Example 2: In this example, the timer interrupts are connected to two separate
47 connected to two separate interrupt controllers. Hence, an 51 interrupt controllers. Hence, an interrupt-map is created to map
48 interrupt-map is created to map the interrupts to the respective 52 the interrupts to the respective interrupt controllers.
49 interrupt controllers.
50 53
51 mct@101C0000 { 54 mct@101C0000 {
52 compatible = "samsung,exynos4210-mct"; 55 compatible = "samsung,exynos4210-mct";
53 reg = <0x101C0000 0x800>; 56 reg = <0x101C0000 0x800>;
54 interrupt-controller;
55 #interrups-cells = <2>;
56 interrupt-parent = <&mct_map>; 57 interrupt-parent = <&mct_map>;
57 interrupts = <0 0>, <1 0>, <2 0>, <3 0>, 58 interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
58 <4 0>, <5 0>;
59 59
60 mct_map: mct-map { 60 mct_map: mct-map {
61 #interrupt-cells = <2>; 61 #interrupt-cells = <1>;
62 #address-cells = <0>; 62 #address-cells = <0>;
63 #size-cells = <0>; 63 #size-cells = <0>;
64 interrupt-map = <0x0 0 &combiner 23 3>, 64 interrupt-map = <0 &gic 0 57 0>,
65 <0x4 0 &gic 0 120 0>, 65 <1 &gic 0 69 0>,
66 <0x5 0 &gic 0 121 0>; 66 <2 &combiner 12 6>,
67 <3 &combiner 12 7>,
68 <4 &gic 0 42 0>,
69 <5 &gic 0 48 0>;
67 }; 70 };
68 }; 71 };
72
73Example 3: In this example, the IP contains four local timers, but using
74 a per-processor interrupt to handle them. Either all the local
75 timer interrupts can be specified, with the same interrupt specifier
76 value or just the first one.
77
78 mct@10050000 {
79 compatible = "samsung,exynos4412-mct";
80 reg = <0x10050000 0x800>;
81
82 /* Both ways are possible in this case. Either: */
83 interrupts = <0 57 0>, <0 69 0>, <0 70 0>, <0 71 0>,
84 <0 42 0>;
85 /* or: */
86 interrupts = <0 57 0>, <0 69 0>, <0 70 0>, <0 71 0>,
87 <0 42 0>, <0 42 0>, <0 42 0>, <0 42 0>;
88 };
diff --git a/Documentation/devicetree/bindings/usb/keystone-phy.txt b/Documentation/devicetree/bindings/usb/keystone-phy.txt
new file mode 100644
index 000000000000..f37b3a86341d
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/keystone-phy.txt
@@ -0,0 +1,20 @@
1TI Keystone USB PHY
2
3Required properties:
4 - compatible: should be "ti,keystone-usbphy".
5 - #address-cells, #size-cells : should be '1' if the device has sub-nodes
6 with 'reg' property.
7 - reg : Address and length of the usb phy control register set.
8
9The main purpose of this PHY driver is to enable the USB PHY reference clock
10gate on the Keystone SOC for both the USB2 and USB3 PHY. Otherwise it is just
11an NOP PHY driver. Hence this node is referenced as both the usb2 and usb3
12phy node in the USB Glue layer driver node.
13
14usb_phy: usb_phy@2620738 {
15 compatible = "ti,keystone-usbphy";
16 #address-cells = <1>;
17 #size-cells = <1>;
18 reg = <0x2620738 32>;
19 status = "disabled";
20};
diff --git a/Documentation/devicetree/bindings/usb/keystone-usb.txt b/Documentation/devicetree/bindings/usb/keystone-usb.txt
new file mode 100644
index 000000000000..60527d335b58
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/keystone-usb.txt
@@ -0,0 +1,42 @@
1TI Keystone Soc USB Controller
2
3DWC3 GLUE
4
5Required properties:
6 - compatible: should be "ti,keystone-dwc3".
7 - #address-cells, #size-cells : should be '1' if the device has sub-nodes
8 with 'reg' property.
9 - reg : Address and length of the register set for the USB subsystem on
10 the SOC.
11 - interrupts : The irq number of this device that is used to interrupt the
12 MPU.
13 - ranges: allows valid 1:1 translation between child's address space and
14 parent's address space.
15 - clocks: Clock IDs array as required by the controller.
16 - clock-names: names of clocks correseponding to IDs in the clock property.
17
18Sub-nodes:
19The dwc3 core should be added as subnode to Keystone DWC3 glue.
20- dwc3 :
21 The binding details of dwc3 can be found in:
22 Documentation/devicetree/bindings/usb/dwc3.txt
23
24Example:
25 usb: usb@2680000 {
26 compatible = "ti,keystone-dwc3";
27 #address-cells = <1>;
28 #size-cells = <1>;
29 reg = <0x2680000 0x10000>;
30 clocks = <&clkusb>;
31 clock-names = "usb";
32 interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
33 ranges;
34 status = "disabled";
35
36 dwc3@2690000 {
37 compatible = "synopsys,dwc3";
38 reg = <0x2690000 0x70000>;
39 interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
40 usb-phy = <&usb_phy>, <&usb_phy>;
41 };
42 };
diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt b/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt
index df0933043a5b..3dc9140e3dfb 100644
--- a/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt
+++ b/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt
@@ -8,7 +8,12 @@ and additions :
8Required properties : 8Required properties :
9 - compatible : Should be "nvidia,tegra20-ehci". 9 - compatible : Should be "nvidia,tegra20-ehci".
10 - nvidia,phy : phandle of the PHY that the controller is connected to. 10 - nvidia,phy : phandle of the PHY that the controller is connected to.
11 - clocks : Contains a single entry which defines the USB controller's clock. 11 - clocks : Must contain one entry, for the module clock.
12 See ../clocks/clock-bindings.txt for details.
13 - resets : Must contain an entry for each entry in reset-names.
14 See ../reset/reset.txt for details.
15 - reset-names : Must include the following entries:
16 - usb
12 17
13Optional properties: 18Optional properties:
14 - nvidia,needs-double-reset : boolean is to be set for some of the Tegra20 19 - nvidia,needs-double-reset : boolean is to be set for some of the Tegra20
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index ce95ed1c6d3e..edbb8d88c85e 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -32,12 +32,14 @@ est ESTeem Wireless Modems
32fsl Freescale Semiconductor 32fsl Freescale Semiconductor
33GEFanuc GE Fanuc Intelligent Platforms Embedded Systems, Inc. 33GEFanuc GE Fanuc Intelligent Platforms Embedded Systems, Inc.
34gef GE Fanuc Intelligent Platforms Embedded Systems, Inc. 34gef GE Fanuc Intelligent Platforms Embedded Systems, Inc.
35gmt Global Mixed-mode Technology, Inc.
35hisilicon Hisilicon Limited. 36hisilicon Hisilicon Limited.
36hp Hewlett Packard 37hp Hewlett Packard
37ibm International Business Machines (IBM) 38ibm International Business Machines (IBM)
38idt Integrated Device Technologies, Inc. 39idt Integrated Device Technologies, Inc.
39img Imagination Technologies Ltd. 40img Imagination Technologies Ltd.
40intercontrol Inter Control Group 41intercontrol Inter Control Group
42lg LG Corporation
41linux Linux-specific binding 43linux Linux-specific binding
42lsi LSI Corp. (LSI Logic) 44lsi LSI Corp. (LSI Logic)
43marvell Marvell Technology Group Ltd. 45marvell Marvell Technology Group Ltd.
diff --git a/Documentation/gpio/00-INDEX b/Documentation/gpio/00-INDEX
new file mode 100644
index 000000000000..1de43ae46ae6
--- /dev/null
+++ b/Documentation/gpio/00-INDEX
@@ -0,0 +1,14 @@
100-INDEX
2 - This file
3gpio.txt
4 - Introduction to GPIOs and their kernel interfaces
5consumer.txt
6 - How to obtain and use GPIOs in a driver
7driver.txt
8 - How to write a GPIO driver
9board.txt
10 - How to assign GPIOs to a consumer device and a function
11sysfs.txt
12 - Information about the GPIO sysfs interface
13gpio-legacy.txt
14 - Historical documentation of the deprecated GPIO integer interface
diff --git a/Documentation/gpio/board.txt b/Documentation/gpio/board.txt
new file mode 100644
index 000000000000..0d03506f2cc5
--- /dev/null
+++ b/Documentation/gpio/board.txt
@@ -0,0 +1,115 @@
1GPIO Mappings
2=============
3
4This document explains how GPIOs can be assigned to given devices and functions.
5Note that it only applies to the new descriptor-based interface. For a
6description of the deprecated integer-based GPIO interface please refer to
7gpio-legacy.txt (actually, there is no real mapping possible with the old
8interface; you just fetch an integer from somewhere and request the
9corresponding GPIO.
10
11Platforms that make use of GPIOs must select ARCH_REQUIRE_GPIOLIB (if GPIO usage
12is mandatory) or ARCH_WANT_OPTIONAL_GPIOLIB (if GPIO support can be omitted) in
13their Kconfig. Then, how GPIOs are mapped depends on what the platform uses to
14describe its hardware layout. Currently, mappings can be defined through device
15tree, ACPI, and platform data.
16
17Device Tree
18-----------
19GPIOs can easily be mapped to devices and functions in the device tree. The
20exact way to do it depends on the GPIO controller providing the GPIOs, see the
21device tree bindings for your controller.
22
23GPIOs mappings are defined in the consumer device's node, in a property named
24<function>-gpios, where <function> is the function the driver will request
25through gpiod_get(). For example:
26
27 foo_device {
28 compatible = "acme,foo";
29 ...
30 led-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>, /* red */
31 <&gpio 16 GPIO_ACTIVE_HIGH>, /* green */
32 <&gpio 17 GPIO_ACTIVE_HIGH>; /* blue */
33
34 power-gpio = <&gpio 1 GPIO_ACTIVE_LOW>;
35 };
36
37This property will make GPIOs 15, 16 and 17 available to the driver under the
38"led" function, and GPIO 1 as the "power" GPIO:
39
40 struct gpio_desc *red, *green, *blue, *power;
41
42 red = gpiod_get_index(dev, "led", 0);
43 green = gpiod_get_index(dev, "led", 1);
44 blue = gpiod_get_index(dev, "led", 2);
45
46 power = gpiod_get(dev, "power");
47
48The led GPIOs will be active-high, while the power GPIO will be active-low (i.e.
49gpiod_is_active_low(power) will be true).
50
51ACPI
52----
53ACPI does not support function names for GPIOs. Therefore, only the "idx"
54argument of gpiod_get_index() is useful to discriminate between GPIOs assigned
55to a device. The "con_id" argument can still be set for debugging purposes (it
56will appear under error messages as well as debug and sysfs nodes).
57
58Platform Data
59-------------
60Finally, GPIOs can be bound to devices and functions using platform data. Board
61files that desire to do so need to include the following header:
62
63 #include <linux/gpio/driver.h>
64
65GPIOs are mapped by the means of tables of lookups, containing instances of the
66gpiod_lookup structure. Two macros are defined to help declaring such mappings:
67
68 GPIO_LOOKUP(chip_label, chip_hwnum, dev_id, con_id, flags)
69 GPIO_LOOKUP_IDX(chip_label, chip_hwnum, dev_id, con_id, idx, flags)
70
71where
72
73 - chip_label is the label of the gpiod_chip instance providing the GPIO
74 - chip_hwnum is the hardware number of the GPIO within the chip
75 - dev_id is the identifier of the device that will make use of this GPIO. If
76 NULL, the GPIO will be available to all devices.
77 - con_id is the name of the GPIO function from the device point of view. It
78 can be NULL.
79 - idx is the index of the GPIO within the function.
80 - flags is defined to specify the following properties:
81 * GPIOF_ACTIVE_LOW - to configure the GPIO as active-low
82 * GPIOF_OPEN_DRAIN - GPIO pin is open drain type.
83 * GPIOF_OPEN_SOURCE - GPIO pin is open source type.
84
85In the future, these flags might be extended to support more properties.
86
87Note that GPIO_LOOKUP() is just a shortcut to GPIO_LOOKUP_IDX() where idx = 0.
88
89A lookup table can then be defined as follows:
90
91 struct gpiod_lookup gpios_table[] = {
92 GPIO_LOOKUP_IDX("gpio.0", 15, "foo.0", "led", 0, GPIO_ACTIVE_HIGH),
93 GPIO_LOOKUP_IDX("gpio.0", 16, "foo.0", "led", 1, GPIO_ACTIVE_HIGH),
94 GPIO_LOOKUP_IDX("gpio.0", 17, "foo.0", "led", 2, GPIO_ACTIVE_HIGH),
95 GPIO_LOOKUP("gpio.0", 1, "foo.0", "power", GPIO_ACTIVE_LOW),
96 };
97
98And the table can be added by the board code as follows:
99
100 gpiod_add_table(gpios_table, ARRAY_SIZE(gpios_table));
101
102The driver controlling "foo.0" will then be able to obtain its GPIOs as follows:
103
104 struct gpio_desc *red, *green, *blue, *power;
105
106 red = gpiod_get_index(dev, "led", 0);
107 green = gpiod_get_index(dev, "led", 1);
108 blue = gpiod_get_index(dev, "led", 2);
109
110 power = gpiod_get(dev, "power");
111 gpiod_direction_output(power, 1);
112
113Since the "power" GPIO is mapped as active-low, its actual signal will be 0
114after this code. Contrary to the legacy integer GPIO interface, the active-low
115property is handled during mapping and is thus transparent to GPIO consumers.
diff --git a/Documentation/gpio/consumer.txt b/Documentation/gpio/consumer.txt
new file mode 100644
index 000000000000..07c74a3765a0
--- /dev/null
+++ b/Documentation/gpio/consumer.txt
@@ -0,0 +1,197 @@
1GPIO Descriptor Consumer Interface
2==================================
3
4This document describes the consumer interface of the GPIO framework. Note that
5it describes the new descriptor-based interface. For a description of the
6deprecated integer-based GPIO interface please refer to gpio-legacy.txt.
7
8
9Guidelines for GPIOs consumers
10==============================
11
12Drivers that can't work without standard GPIO calls should have Kconfig entries
13that depend on GPIOLIB. The functions that allow a driver to obtain and use
14GPIOs are available by including the following file:
15
16 #include <linux/gpio/consumer.h>
17
18All the functions that work with the descriptor-based GPIO interface are
19prefixed with gpiod_. The gpio_ prefix is used for the legacy interface. No
20other function in the kernel should use these prefixes.
21
22
23Obtaining and Disposing GPIOs
24=============================
25
26With the descriptor-based interface, GPIOs are identified with an opaque,
27non-forgeable handler that must be obtained through a call to one of the
28gpiod_get() functions. Like many other kernel subsystems, gpiod_get() takes the
29device that will use the GPIO and the function the requested GPIO is supposed to
30fulfill:
31
32 struct gpio_desc *gpiod_get(struct device *dev, const char *con_id)
33
34If a function is implemented by using several GPIOs together (e.g. a simple LED
35device that displays digits), an additional index argument can be specified:
36
37 struct gpio_desc *gpiod_get_index(struct device *dev,
38 const char *con_id, unsigned int idx)
39
40Both functions return either a valid GPIO descriptor, or an error code checkable
41with IS_ERR(). They will never return a NULL pointer.
42
43Device-managed variants of these functions are also defined:
44
45 struct gpio_desc *devm_gpiod_get(struct device *dev, const char *con_id)
46
47 struct gpio_desc *devm_gpiod_get_index(struct device *dev,
48 const char *con_id,
49 unsigned int idx)
50
51A GPIO descriptor can be disposed of using the gpiod_put() function:
52
53 void gpiod_put(struct gpio_desc *desc)
54
55It is strictly forbidden to use a descriptor after calling this function. The
56device-managed variant is, unsurprisingly:
57
58 void devm_gpiod_put(struct device *dev, struct gpio_desc *desc)
59
60
61Using GPIOs
62===========
63
64Setting Direction
65-----------------
66The first thing a driver must do with a GPIO is setting its direction. This is
67done by invoking one of the gpiod_direction_*() functions:
68
69 int gpiod_direction_input(struct gpio_desc *desc)
70 int gpiod_direction_output(struct gpio_desc *desc, int value)
71
72The return value is zero for success, else a negative errno. It should be
73checked, since the get/set calls don't return errors and since misconfiguration
74is possible. You should normally issue these calls from a task context. However,
75for spinlock-safe GPIOs it is OK to use them before tasking is enabled, as part
76of early board setup.
77
78For output GPIOs, the value provided becomes the initial output value. This
79helps avoid signal glitching during system startup.
80
81A driver can also query the current direction of a GPIO:
82
83 int gpiod_get_direction(const struct gpio_desc *desc)
84
85This function will return either GPIOF_DIR_IN or GPIOF_DIR_OUT.
86
87Be aware that there is no default direction for GPIOs. Therefore, **using a GPIO
88without setting its direction first is illegal and will result in undefined
89behavior!**
90
91
92Spinlock-Safe GPIO Access
93-------------------------
94Most GPIO controllers can be accessed with memory read/write instructions. Those
95don't need to sleep, and can safely be done from inside hard (non-threaded) IRQ
96handlers and similar contexts.
97
98Use the following calls to access GPIOs from an atomic context:
99
100 int gpiod_get_value(const struct gpio_desc *desc);
101 void gpiod_set_value(struct gpio_desc *desc, int value);
102
103The values are boolean, zero for low, nonzero for high. When reading the value
104of an output pin, the value returned should be what's seen on the pin. That
105won't always match the specified output value, because of issues including
106open-drain signaling and output latencies.
107
108The get/set calls do not return errors because "invalid GPIO" should have been
109reported earlier from gpiod_direction_*(). However, note that not all platforms
110can read the value of output pins; those that can't should always return zero.
111Also, using these calls for GPIOs that can't safely be accessed without sleeping
112(see below) is an error.
113
114
115GPIO Access That May Sleep
116--------------------------
117Some GPIO controllers must be accessed using message based buses like I2C or
118SPI. Commands to read or write those GPIO values require waiting to get to the
119head of a queue to transmit a command and get its response. This requires
120sleeping, which can't be done from inside IRQ handlers.
121
122Platforms that support this type of GPIO distinguish them from other GPIOs by
123returning nonzero from this call:
124
125 int gpiod_cansleep(const struct gpio_desc *desc)
126
127To access such GPIOs, a different set of accessors is defined:
128
129 int gpiod_get_value_cansleep(const struct gpio_desc *desc)
130 void gpiod_set_value_cansleep(struct gpio_desc *desc, int value)
131
132Accessing such GPIOs requires a context which may sleep, for example a threaded
133IRQ handler, and those accessors must be used instead of spinlock-safe
134accessors without the cansleep() name suffix.
135
136Other than the fact that these accessors might sleep, and will work on GPIOs
137that can't be accessed from hardIRQ handlers, these calls act the same as the
138spinlock-safe calls.
139
140
141Active-low State and Raw GPIO Values
142------------------------------------
143Device drivers like to manage the logical state of a GPIO, i.e. the value their
144device will actually receive, no matter what lies between it and the GPIO line.
145In some cases, it might make sense to control the actual GPIO line value. The
146following set of calls ignore the active-low property of a GPIO and work on the
147raw line value:
148
149 int gpiod_get_raw_value(const struct gpio_desc *desc)
150 void gpiod_set_raw_value(struct gpio_desc *desc, int value)
151 int gpiod_get_raw_value_cansleep(const struct gpio_desc *desc)
152 void gpiod_set_raw_value_cansleep(struct gpio_desc *desc, int value)
153
154The active-low state of a GPIO can also be queried using the following call:
155
156 int gpiod_is_active_low(const struct gpio_desc *desc)
157
158Note that these functions should only be used with great moderation ; a driver
159should not have to care about the physical line level.
160
161GPIOs mapped to IRQs
162--------------------
163GPIO lines can quite often be used as IRQs. You can get the IRQ number
164corresponding to a given GPIO using the following call:
165
166 int gpiod_to_irq(const struct gpio_desc *desc)
167
168It will return an IRQ number, or an negative errno code if the mapping can't be
169done (most likely because that particular GPIO cannot be used as IRQ). It is an
170unchecked error to use a GPIO that wasn't set up as an input using
171gpiod_direction_input(), or to use an IRQ number that didn't originally come
172from gpiod_to_irq(). gpiod_to_irq() is not allowed to sleep.
173
174Non-error values returned from gpiod_to_irq() can be passed to request_irq() or
175free_irq(). They will often be stored into IRQ resources for platform devices,
176by the board-specific initialization code. Note that IRQ trigger options are
177part of the IRQ interface, e.g. IRQF_TRIGGER_FALLING, as are system wakeup
178capabilities.
179
180
181Interacting With the Legacy GPIO Subsystem
182==========================================
183Many kernel subsystems still handle GPIOs using the legacy integer-based
184interface. Although it is strongly encouraged to upgrade them to the safer
185descriptor-based API, the following two functions allow you to convert a GPIO
186descriptor into the GPIO integer namespace and vice-versa:
187
188 int desc_to_gpio(const struct gpio_desc *desc)
189 struct gpio_desc *gpio_to_desc(unsigned gpio)
190
191The GPIO number returned by desc_to_gpio() can be safely used as long as the
192GPIO descriptor has not been freed. All the same, a GPIO number passed to
193gpio_to_desc() must have been properly acquired, and usage of the returned GPIO
194descriptor is only possible after the GPIO number has been released.
195
196Freeing a GPIO obtained by one API with the other API is forbidden and an
197unchecked error.
diff --git a/Documentation/gpio/driver.txt b/Documentation/gpio/driver.txt
new file mode 100644
index 000000000000..9da0bfa74781
--- /dev/null
+++ b/Documentation/gpio/driver.txt
@@ -0,0 +1,75 @@
1GPIO Descriptor Driver Interface
2================================
3
4This document serves as a guide for GPIO chip drivers writers. Note that it
5describes the new descriptor-based interface. For a description of the
6deprecated integer-based GPIO interface please refer to gpio-legacy.txt.
7
8Each GPIO controller driver needs to include the following header, which defines
9the structures used to define a GPIO driver:
10
11 #include <linux/gpio/driver.h>
12
13
14Internal Representation of GPIOs
15================================
16
17Inside a GPIO driver, individual GPIOs are identified by their hardware number,
18which is a unique number between 0 and n, n being the number of GPIOs managed by
19the chip. This number is purely internal: the hardware number of a particular
20GPIO descriptor is never made visible outside of the driver.
21
22On top of this internal number, each GPIO also need to have a global number in
23the integer GPIO namespace so that it can be used with the legacy GPIO
24interface. Each chip must thus have a "base" number (which can be automatically
25assigned), and for each GPIO the global number will be (base + hardware number).
26Although the integer representation is considered deprecated, it still has many
27users and thus needs to be maintained.
28
29So for example one platform could use numbers 32-159 for GPIOs, with a
30controller defining 128 GPIOs at a "base" of 32 ; while another platform uses
31numbers 0..63 with one set of GPIO controllers, 64-79 with another type of GPIO
32controller, and on one particular board 80-95 with an FPGA. The numbers need not
33be contiguous; either of those platforms could also use numbers 2000-2063 to
34identify GPIOs in a bank of I2C GPIO expanders.
35
36
37Controller Drivers: gpio_chip
38=============================
39
40In the gpiolib framework each GPIO controller is packaged as a "struct
41gpio_chip" (see linux/gpio/driver.h for its complete definition) with members
42common to each controller of that type:
43
44 - methods to establish GPIO direction
45 - methods used to access GPIO values
46 - method to return the IRQ number associated to a given GPIO
47 - flag saying whether calls to its methods may sleep
48 - optional debugfs dump method (showing extra state like pullup config)
49 - optional base number (will be automatically assigned if omitted)
50 - label for diagnostics and GPIOs mapping using platform data
51
52The code implementing a gpio_chip should support multiple instances of the
53controller, possibly using the driver model. That code will configure each
54gpio_chip and issue gpiochip_add(). Removing a GPIO controller should be rare;
55use gpiochip_remove() when it is unavoidable.
56
57Most often a gpio_chip is part of an instance-specific structure with state not
58exposed by the GPIO interfaces, such as addressing, power management, and more.
59Chips such as codecs will have complex non-GPIO state.
60
61Any debugfs dump method should normally ignore signals which haven't been
62requested as GPIOs. They can use gpiochip_is_requested(), which returns either
63NULL or the label associated with that GPIO when it was requested.
64
65Locking IRQ usage
66-----------------
67Input GPIOs can be used as IRQ signals. When this happens, a driver is requested
68to mark the GPIO as being used as an IRQ:
69
70 int gpiod_lock_as_irq(struct gpio_desc *desc)
71
72This will prevent the use of non-irq related GPIO APIs until the GPIO IRQ lock
73is released:
74
75 void gpiod_unlock_as_irq(struct gpio_desc *desc)
diff --git a/Documentation/gpio.txt b/Documentation/gpio/gpio-legacy.txt
index 6f83fa965b4b..6f83fa965b4b 100644
--- a/Documentation/gpio.txt
+++ b/Documentation/gpio/gpio-legacy.txt
diff --git a/Documentation/gpio/gpio.txt b/Documentation/gpio/gpio.txt
new file mode 100644
index 000000000000..cd9b356e88cd
--- /dev/null
+++ b/Documentation/gpio/gpio.txt
@@ -0,0 +1,119 @@
1GPIO Interfaces
2===============
3
4The documents in this directory give detailed instructions on how to access
5GPIOs in drivers, and how to write a driver for a device that provides GPIOs
6itself.
7
8Due to the history of GPIO interfaces in the kernel, there are two different
9ways to obtain and use GPIOs:
10
11 - The descriptor-based interface is the preferred way to manipulate GPIOs,
12and is described by all the files in this directory excepted gpio-legacy.txt.
13 - The legacy integer-based interface which is considered deprecated (but still
14usable for compatibility reasons) is documented in gpio-legacy.txt.
15
16The remainder of this document applies to the new descriptor-based interface.
17gpio-legacy.txt contains the same information applied to the legacy
18integer-based interface.
19
20
21What is a GPIO?
22===============
23
24A "General Purpose Input/Output" (GPIO) is a flexible software-controlled
25digital signal. They are provided from many kinds of chip, and are familiar
26to Linux developers working with embedded and custom hardware. Each GPIO
27represents a bit connected to a particular pin, or "ball" on Ball Grid Array
28(BGA) packages. Board schematics show which external hardware connects to
29which GPIOs. Drivers can be written generically, so that board setup code
30passes such pin configuration data to drivers.
31
32System-on-Chip (SOC) processors heavily rely on GPIOs. In some cases, every
33non-dedicated pin can be configured as a GPIO; and most chips have at least
34several dozen of them. Programmable logic devices (like FPGAs) can easily
35provide GPIOs; multifunction chips like power managers, and audio codecs
36often have a few such pins to help with pin scarcity on SOCs; and there are
37also "GPIO Expander" chips that connect using the I2C or SPI serial buses.
38Most PC southbridges have a few dozen GPIO-capable pins (with only the BIOS
39firmware knowing how they're used).
40
41The exact capabilities of GPIOs vary between systems. Common options:
42
43 - Output values are writable (high=1, low=0). Some chips also have
44 options about how that value is driven, so that for example only one
45 value might be driven, supporting "wire-OR" and similar schemes for the
46 other value (notably, "open drain" signaling).
47
48 - Input values are likewise readable (1, 0). Some chips support readback
49 of pins configured as "output", which is very useful in such "wire-OR"
50 cases (to support bidirectional signaling). GPIO controllers may have
51 input de-glitch/debounce logic, sometimes with software controls.
52
53 - Inputs can often be used as IRQ signals, often edge triggered but
54 sometimes level triggered. Such IRQs may be configurable as system
55 wakeup events, to wake the system from a low power state.
56
57 - Usually a GPIO will be configurable as either input or output, as needed
58 by different product boards; single direction ones exist too.
59
60 - Most GPIOs can be accessed while holding spinlocks, but those accessed
61 through a serial bus normally can't. Some systems support both types.
62
63On a given board each GPIO is used for one specific purpose like monitoring
64MMC/SD card insertion/removal, detecting card write-protect status, driving
65a LED, configuring a transceiver, bit-banging a serial bus, poking a hardware
66watchdog, sensing a switch, and so on.
67
68
69Common GPIO Properties
70======================
71
72These properties are met through all the other documents of the GPIO interface
73and it is useful to understand them, especially if you need to define GPIO
74mappings.
75
76Active-High and Active-Low
77--------------------------
78It is natural to assume that a GPIO is "active" when its output signal is 1
79("high"), and inactive when it is 0 ("low"). However in practice the signal of a
80GPIO may be inverted before is reaches its destination, or a device could decide
81to have different conventions about what "active" means. Such decisions should
82be transparent to device drivers, therefore it is possible to define a GPIO as
83being either active-high ("1" means "active", the default) or active-low ("0"
84means "active") so that drivers only need to worry about the logical signal and
85not about what happens at the line level.
86
87Open Drain and Open Source
88--------------------------
89Sometimes shared signals need to use "open drain" (where only the low signal
90level is actually driven), or "open source" (where only the high signal level is
91driven) signaling. That term applies to CMOS transistors; "open collector" is
92used for TTL. A pullup or pulldown resistor causes the high or low signal level.
93This is sometimes called a "wire-AND"; or more practically, from the negative
94logic (low=true) perspective this is a "wire-OR".
95
96One common example of an open drain signal is a shared active-low IRQ line.
97Also, bidirectional data bus signals sometimes use open drain signals.
98
99Some GPIO controllers directly support open drain and open source outputs; many
100don't. When you need open drain signaling but your hardware doesn't directly
101support it, there's a common idiom you can use to emulate it with any GPIO pin
102that can be used as either an input or an output:
103
104 LOW: gpiod_direction_output(gpio, 0) ... this drives the signal and overrides
105 the pullup.
106
107 HIGH: gpiod_direction_input(gpio) ... this turns off the output, so the pullup
108 (or some other device) controls the signal.
109
110The same logic can be applied to emulate open source signaling, by driving the
111high signal and configuring the GPIO as input for low. This open drain/open
112source emulation can be handled transparently by the GPIO framework.
113
114If you are "driving" the signal high but gpiod_get_value(gpio) reports a low
115value (after the appropriate rise time passes), you know some other component is
116driving the shared signal low. That's not necessarily an error. As one common
117example, that's how I2C clocks are stretched: a slave that needs a slower clock
118delays the rising edge of SCK, and the I2C master adjusts its signaling rate
119accordingly.
diff --git a/Documentation/gpio/sysfs.txt b/Documentation/gpio/sysfs.txt
new file mode 100644
index 000000000000..c2c3a97f8ff7
--- /dev/null
+++ b/Documentation/gpio/sysfs.txt
@@ -0,0 +1,155 @@
1GPIO Sysfs Interface for Userspace
2==================================
3
4Platforms which use the "gpiolib" implementors framework may choose to
5configure a sysfs user interface to GPIOs. This is different from the
6debugfs interface, since it provides control over GPIO direction and
7value instead of just showing a gpio state summary. Plus, it could be
8present on production systems without debugging support.
9
10Given appropriate hardware documentation for the system, userspace could
11know for example that GPIO #23 controls the write protect line used to
12protect boot loader segments in flash memory. System upgrade procedures
13may need to temporarily remove that protection, first importing a GPIO,
14then changing its output state, then updating the code before re-enabling
15the write protection. In normal use, GPIO #23 would never be touched,
16and the kernel would have no need to know about it.
17
18Again depending on appropriate hardware documentation, on some systems
19userspace GPIO can be used to determine system configuration data that
20standard kernels won't know about. And for some tasks, simple userspace
21GPIO drivers could be all that the system really needs.
22
23Note that standard kernel drivers exist for common "LEDs and Buttons"
24GPIO tasks: "leds-gpio" and "gpio_keys", respectively. Use those
25instead of talking directly to the GPIOs; they integrate with kernel
26frameworks better than your userspace code could.
27
28
29Paths in Sysfs
30--------------
31There are three kinds of entry in /sys/class/gpio:
32
33 - Control interfaces used to get userspace control over GPIOs;
34
35 - GPIOs themselves; and
36
37 - GPIO controllers ("gpio_chip" instances).
38
39That's in addition to standard files including the "device" symlink.
40
41The control interfaces are write-only:
42
43 /sys/class/gpio/
44
45 "export" ... Userspace may ask the kernel to export control of
46 a GPIO to userspace by writing its number to this file.
47
48 Example: "echo 19 > export" will create a "gpio19" node
49 for GPIO #19, if that's not requested by kernel code.
50
51 "unexport" ... Reverses the effect of exporting to userspace.
52
53 Example: "echo 19 > unexport" will remove a "gpio19"
54 node exported using the "export" file.
55
56GPIO signals have paths like /sys/class/gpio/gpio42/ (for GPIO #42)
57and have the following read/write attributes:
58
59 /sys/class/gpio/gpioN/
60
61 "direction" ... reads as either "in" or "out". This value may
62 normally be written. Writing as "out" defaults to
63 initializing the value as low. To ensure glitch free
64 operation, values "low" and "high" may be written to
65 configure the GPIO as an output with that initial value.
66
67 Note that this attribute *will not exist* if the kernel
68 doesn't support changing the direction of a GPIO, or
69 it was exported by kernel code that didn't explicitly
70 allow userspace to reconfigure this GPIO's direction.
71
72 "value" ... reads as either 0 (low) or 1 (high). If the GPIO
73 is configured as an output, this value may be written;
74 any nonzero value is treated as high.
75
76 If the pin can be configured as interrupt-generating interrupt
77 and if it has been configured to generate interrupts (see the
78 description of "edge"), you can poll(2) on that file and
79 poll(2) will return whenever the interrupt was triggered. If
80 you use poll(2), set the events POLLPRI and POLLERR. If you
81 use select(2), set the file descriptor in exceptfds. After
82 poll(2) returns, either lseek(2) to the beginning of the sysfs
83 file and read the new value or close the file and re-open it
84 to read the value.
85
86 "edge" ... reads as either "none", "rising", "falling", or
87 "both". Write these strings to select the signal edge(s)
88 that will make poll(2) on the "value" file return.
89
90 This file exists only if the pin can be configured as an
91 interrupt generating input pin.
92
93 "active_low" ... reads as either 0 (false) or 1 (true). Write
94 any nonzero value to invert the value attribute both
95 for reading and writing. Existing and subsequent
96 poll(2) support configuration via the edge attribute
97 for "rising" and "falling" edges will follow this
98 setting.
99
100GPIO controllers have paths like /sys/class/gpio/gpiochip42/ (for the
101controller implementing GPIOs starting at #42) and have the following
102read-only attributes:
103
104 /sys/class/gpio/gpiochipN/
105
106 "base" ... same as N, the first GPIO managed by this chip
107
108 "label" ... provided for diagnostics (not always unique)
109
110 "ngpio" ... how many GPIOs this manges (N to N + ngpio - 1)
111
112Board documentation should in most cases cover what GPIOs are used for
113what purposes. However, those numbers are not always stable; GPIOs on
114a daughtercard might be different depending on the base board being used,
115or other cards in the stack. In such cases, you may need to use the
116gpiochip nodes (possibly in conjunction with schematics) to determine
117the correct GPIO number to use for a given signal.
118
119
120Exporting from Kernel code
121--------------------------
122Kernel code can explicitly manage exports of GPIOs which have already been
123requested using gpio_request():
124
125 /* export the GPIO to userspace */
126 int gpiod_export(struct gpio_desc *desc, bool direction_may_change);
127
128 /* reverse gpio_export() */
129 void gpiod_unexport(struct gpio_desc *desc);
130
131 /* create a sysfs link to an exported GPIO node */
132 int gpiod_export_link(struct device *dev, const char *name,
133 struct gpio_desc *desc);
134
135 /* change the polarity of a GPIO node in sysfs */
136 int gpiod_sysfs_set_active_low(struct gpio_desc *desc, int value);
137
138After a kernel driver requests a GPIO, it may only be made available in
139the sysfs interface by gpiod_export(). The driver can control whether the
140signal direction may change. This helps drivers prevent userspace code
141from accidentally clobbering important system state.
142
143This explicit exporting can help with debugging (by making some kinds
144of experiments easier), or can provide an always-there interface that's
145suitable for documenting as part of a board support package.
146
147After the GPIO has been exported, gpiod_export_link() allows creating
148symlinks from elsewhere in sysfs to the GPIO sysfs node. Drivers can
149use this to provide the interface under their own device in sysfs with
150a descriptive name.
151
152Drivers can use gpiod_sysfs_set_active_low() to hide GPIO line polarity
153differences between boards from user space. Polarity change can be done both
154before and after gpiod_export(), and previously enabled poll(2) support for
155either rising or falling edge will be reconfigured to follow this setting.
diff --git a/MAINTAINERS b/MAINTAINERS
index 8285ed4676b6..13c15c83a46e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1934,7 +1934,8 @@ S: Maintained
1934F: drivers/gpio/gpio-bt8xx.c 1934F: drivers/gpio/gpio-bt8xx.c
1935 1935
1936BTRFS FILE SYSTEM 1936BTRFS FILE SYSTEM
1937M: Chris Mason <chris.mason@fusionio.com> 1937M: Chris Mason <clm@fb.com>
1938M: Josef Bacik <jbacik@fb.com>
1938L: linux-btrfs@vger.kernel.org 1939L: linux-btrfs@vger.kernel.org
1939W: http://btrfs.wiki.kernel.org/ 1940W: http://btrfs.wiki.kernel.org/
1940Q: http://patchwork.kernel.org/project/linux-btrfs/list/ 1941Q: http://patchwork.kernel.org/project/linux-btrfs/list/
@@ -2142,6 +2143,11 @@ L: linux-usb@vger.kernel.org
2142S: Maintained 2143S: Maintained
2143F: drivers/usb/chipidea/ 2144F: drivers/usb/chipidea/
2144 2145
2146CHROME HARDWARE PLATFORM SUPPORT
2147M: Olof Johansson <olof@lixom.net>
2148S: Maintained
2149F: drivers/platform/chrome/
2150
2145CISCO VIC ETHERNET NIC DRIVER 2151CISCO VIC ETHERNET NIC DRIVER
2146M: Christian Benvenuti <benve@cisco.com> 2152M: Christian Benvenuti <benve@cisco.com>
2147M: Sujith Sankar <ssujith@cisco.com> 2153M: Sujith Sankar <ssujith@cisco.com>
@@ -4044,6 +4050,12 @@ W: http://www.pharscape.org
4044S: Maintained 4050S: Maintained
4045F: drivers/net/usb/hso.c 4051F: drivers/net/usb/hso.c
4046 4052
4053HSR NETWORK PROTOCOL
4054M: Arvid Brodin <arvid.brodin@alten.se>
4055L: netdev@vger.kernel.org
4056S: Maintained
4057F: net/hsr/
4058
4047HTCPEN TOUCHSCREEN DRIVER 4059HTCPEN TOUCHSCREEN DRIVER
4048M: Pau Oliva Fora <pof@eslack.org> 4060M: Pau Oliva Fora <pof@eslack.org>
4049L: linux-input@vger.kernel.org 4061L: linux-input@vger.kernel.org
@@ -5256,7 +5268,7 @@ S: Maintained
5256F: Documentation/lockdep*.txt 5268F: Documentation/lockdep*.txt
5257F: Documentation/lockstat.txt 5269F: Documentation/lockstat.txt
5258F: include/linux/lockdep.h 5270F: include/linux/lockdep.h
5259F: kernel/lockdep* 5271F: kernel/locking/
5260 5272
5261LOGICAL DISK MANAGER SUPPORT (LDM, Windows 2000/XP/Vista Dynamic Disks) 5273LOGICAL DISK MANAGER SUPPORT (LDM, Windows 2000/XP/Vista Dynamic Disks)
5262M: "Richard Russon (FlatCap)" <ldm@flatcap.org> 5274M: "Richard Russon (FlatCap)" <ldm@flatcap.org>
@@ -5968,10 +5980,10 @@ F: drivers/nfc/
5968F: include/linux/platform_data/pn544.h 5980F: include/linux/platform_data/pn544.h
5969 5981
5970NFS, SUNRPC, AND LOCKD CLIENTS 5982NFS, SUNRPC, AND LOCKD CLIENTS
5971M: Trond Myklebust <Trond.Myklebust@netapp.com> 5983M: Trond Myklebust <trond.myklebust@primarydata.com>
5972L: linux-nfs@vger.kernel.org 5984L: linux-nfs@vger.kernel.org
5973W: http://client.linux-nfs.org 5985W: http://client.linux-nfs.org
5974T: git git://git.linux-nfs.org/pub/linux/nfs-2.6.git 5986T: git git://git.linux-nfs.org/projects/trondmy/linux-nfs.git
5975S: Maintained 5987S: Maintained
5976F: fs/lockd/ 5988F: fs/lockd/
5977F: fs/nfs/ 5989F: fs/nfs/
@@ -6238,8 +6250,8 @@ OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
6238M: Rob Herring <rob.herring@calxeda.com> 6250M: Rob Herring <rob.herring@calxeda.com>
6239M: Pawel Moll <pawel.moll@arm.com> 6251M: Pawel Moll <pawel.moll@arm.com>
6240M: Mark Rutland <mark.rutland@arm.com> 6252M: Mark Rutland <mark.rutland@arm.com>
6241M: Stephen Warren <swarren@wwwdotorg.org>
6242M: Ian Campbell <ijc+devicetree@hellion.org.uk> 6253M: Ian Campbell <ijc+devicetree@hellion.org.uk>
6254M: Kumar Gala <galak@codeaurora.org>
6243L: devicetree@vger.kernel.org 6255L: devicetree@vger.kernel.org
6244S: Maintained 6256S: Maintained
6245F: Documentation/devicetree/ 6257F: Documentation/devicetree/
@@ -7380,7 +7392,6 @@ S: Maintained
7380F: kernel/sched/ 7392F: kernel/sched/
7381F: include/linux/sched.h 7393F: include/linux/sched.h
7382F: include/uapi/linux/sched.h 7394F: include/uapi/linux/sched.h
7383F: kernel/wait.c
7384F: include/linux/wait.h 7395F: include/linux/wait.h
7385 7396
7386SCORE ARCHITECTURE 7397SCORE ARCHITECTURE
diff --git a/Makefile b/Makefile
index c0c2d58e3998..890392f1c7c0 100644
--- a/Makefile
+++ b/Makefile
@@ -1,7 +1,7 @@
1VERSION = 3 1VERSION = 3
2PATCHLEVEL = 13 2PATCHLEVEL = 13
3SUBLEVEL = 0 3SUBLEVEL = 0
4EXTRAVERSION = -rc1 4EXTRAVERSION = -rc3
5NAME = One Giant Leap for Frogkind 5NAME = One Giant Leap for Frogkind
6 6
7# *DOCUMENTATION* 7# *DOCUMENTATION*
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index c1f1a7eee953..483d316543ad 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -644,8 +644,9 @@ config ARCH_MSM
644 stack and controls some vital subsystems 644 stack and controls some vital subsystems
645 (clock and power control, etc). 645 (clock and power control, etc).
646 646
647config ARCH_SHMOBILE 647config ARCH_SHMOBILE_LEGACY
648 bool "Renesas SH-Mobile / R-Mobile" 648 bool "Renesas SH-Mobile / R-Mobile (non-multiplatform)"
649 select ARCH_SHMOBILE
649 select ARM_PATCH_PHYS_VIRT 650 select ARM_PATCH_PHYS_VIRT
650 select CLKDEV_LOOKUP 651 select CLKDEV_LOOKUP
651 select GENERIC_CLOCKEVENTS 652 select GENERIC_CLOCKEVENTS
@@ -660,7 +661,8 @@ config ARCH_SHMOBILE
660 select PM_GENERIC_DOMAINS if PM 661 select PM_GENERIC_DOMAINS if PM
661 select SPARSE_IRQ 662 select SPARSE_IRQ
662 help 663 help
663 Support for Renesas's SH-Mobile and R-Mobile ARM platforms. 664 Support for Renesas's SH-Mobile and R-Mobile ARM platforms using
665 a non-multiplatform kernel.
664 666
665config ARCH_RPC 667config ARCH_RPC
666 bool "RiscPC" 668 bool "RiscPC"
@@ -1611,7 +1613,7 @@ config HZ_FIXED
1611 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \ 1613 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1612 ARCH_S5PV210 || ARCH_EXYNOS4 1614 ARCH_S5PV210 || ARCH_EXYNOS4
1613 default AT91_TIMER_HZ if ARCH_AT91 1615 default AT91_TIMER_HZ if ARCH_AT91
1614 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE 1616 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1615 default 0 1617 default 0
1616 1618
1617choice 1619choice
@@ -1796,8 +1798,8 @@ config ARCH_WANT_GENERAL_HUGETLB
1796source "mm/Kconfig" 1798source "mm/Kconfig"
1797 1799
1798config FORCE_MAX_ZONEORDER 1800config FORCE_MAX_ZONEORDER
1799 int "Maximum zone order" if ARCH_SHMOBILE 1801 int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1800 range 11 64 if ARCH_SHMOBILE 1802 range 11 64 if ARCH_SHMOBILE_LEGACY
1801 default "12" if SOC_AM33XX 1803 default "12" if SOC_AM33XX
1802 default "9" if SA1111 1804 default "9" if SA1111
1803 default "11" 1805 default "11"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index c99b1086d83d..1edf8ebd8494 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -190,7 +190,6 @@ machine-$(CONFIG_ARCH_S5PC100) += s5pc100
190machine-$(CONFIG_ARCH_S5PV210) += s5pv210 190machine-$(CONFIG_ARCH_S5PV210) += s5pv210
191machine-$(CONFIG_ARCH_SA1100) += sa1100 191machine-$(CONFIG_ARCH_SA1100) += sa1100
192machine-$(CONFIG_ARCH_SHMOBILE) += shmobile 192machine-$(CONFIG_ARCH_SHMOBILE) += shmobile
193machine-$(CONFIG_ARCH_SHMOBILE_MULTI) += shmobile
194machine-$(CONFIG_ARCH_SIRF) += prima2 193machine-$(CONFIG_ARCH_SIRF) += prima2
195machine-$(CONFIG_ARCH_SOCFPGA) += socfpga 194machine-$(CONFIG_ARCH_SOCFPGA) += socfpga
196machine-$(CONFIG_ARCH_STI) += sti 195machine-$(CONFIG_ARCH_STI) += sti
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index e7190bb5998e..f54d5a25c7ee 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -64,7 +64,7 @@ else
64endif 64endif
65endif 65endif
66 66
67ifeq ($(CONFIG_ARCH_SHMOBILE),y) 67ifeq ($(CONFIG_ARCH_SHMOBILE_LEGACY),y)
68OBJS += head-shmobile.o 68OBJS += head-shmobile.o
69endif 69endif
70 70
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 09067804035f..2752a13f1b60 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -30,6 +30,7 @@ dtb-$(CONFIG_ARCH_AT91) += pm9g45.dtb
30dtb-$(CONFIG_ARCH_AT91) += at91sam9n12ek.dtb 30dtb-$(CONFIG_ARCH_AT91) += at91sam9n12ek.dtb
31# sam9x5 31# sam9x5
32dtb-$(CONFIG_ARCH_AT91) += at91-ariag25.dtb 32dtb-$(CONFIG_ARCH_AT91) += at91-ariag25.dtb
33dtb-$(CONFIG_ARCH_AT91) += at91-cosino_mega2560.dtb
33dtb-$(CONFIG_ARCH_AT91) += at91sam9g15ek.dtb 34dtb-$(CONFIG_ARCH_AT91) += at91sam9g15ek.dtb
34dtb-$(CONFIG_ARCH_AT91) += at91sam9g25ek.dtb 35dtb-$(CONFIG_ARCH_AT91) += at91sam9g25ek.dtb
35dtb-$(CONFIG_ARCH_AT91) += at91sam9g35ek.dtb 36dtb-$(CONFIG_ARCH_AT91) += at91sam9g35ek.dtb
@@ -40,6 +41,8 @@ dtb-$(CONFIG_ARCH_AT91) += sama5d31ek.dtb
40dtb-$(CONFIG_ARCH_AT91) += sama5d33ek.dtb 41dtb-$(CONFIG_ARCH_AT91) += sama5d33ek.dtb
41dtb-$(CONFIG_ARCH_AT91) += sama5d34ek.dtb 42dtb-$(CONFIG_ARCH_AT91) += sama5d34ek.dtb
42dtb-$(CONFIG_ARCH_AT91) += sama5d35ek.dtb 43dtb-$(CONFIG_ARCH_AT91) += sama5d35ek.dtb
44dtb-$(CONFIG_ARCH_AT91) += sama5d36ek.dtb
45
43dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb 46dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb
44dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb 47dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
45dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm11351-brt.dtb \ 48dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm11351-brt.dtb \
@@ -106,6 +109,7 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \
106 kirkwood-ts219-6281.dtb \ 109 kirkwood-ts219-6281.dtb \
107 kirkwood-ts219-6282.dtb 110 kirkwood-ts219-6282.dtb
108dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb 111dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb
112dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb
109dtb-$(CONFIG_ARCH_MSM) += qcom-msm8660-surf.dtb \ 113dtb-$(CONFIG_ARCH_MSM) += qcom-msm8660-surf.dtb \
110 qcom-msm8960-cdp.dtb 114 qcom-msm8960-cdp.dtb
111dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \ 115dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \
@@ -219,7 +223,7 @@ dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \
219dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb 223dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb
220dtb-$(CONFIG_ARCH_S3C64XX) += s3c6410-mini6410.dtb \ 224dtb-$(CONFIG_ARCH_S3C64XX) += s3c6410-mini6410.dtb \
221 s3c6410-smdk6410.dtb 225 s3c6410-smdk6410.dtb
222dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \ 226dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += emev2-kzm9d.dtb \
223 r7s72100-genmai.dtb \ 227 r7s72100-genmai.dtb \
224 r8a7740-armadillo800eva.dtb \ 228 r8a7740-armadillo800eva.dtb \
225 r8a7778-bockw.dtb \ 229 r8a7778-bockw.dtb \
@@ -228,6 +232,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \
228 r8a7779-marzen.dtb \ 232 r8a7779-marzen.dtb \
229 r8a7779-marzen-reference.dtb \ 233 r8a7779-marzen-reference.dtb \
230 r8a7791-koelsch.dtb \ 234 r8a7791-koelsch.dtb \
235 r8a7791-koelsch-reference.dtb \
231 r8a7790-lager.dtb \ 236 r8a7790-lager.dtb \
232 r8a7790-lager-reference.dtb \ 237 r8a7790-lager-reference.dtb \
233 sh73a0-kzm9g.dtb \ 238 sh73a0-kzm9g.dtb \
diff --git a/arch/arm/boot/dts/am335x-base0033.dts b/arch/arm/boot/dts/am335x-base0033.dts
index b4f95c2bbf74..72a9b3fc4251 100644
--- a/arch/arm/boot/dts/am335x-base0033.dts
+++ b/arch/arm/boot/dts/am335x-base0033.dts
@@ -13,4 +13,83 @@
13/ { 13/ {
14 model = "IGEP COM AM335x on AQUILA Expansion"; 14 model = "IGEP COM AM335x on AQUILA Expansion";
15 compatible = "isee,am335x-base0033", "isee,am335x-igep0033", "ti,am33xx"; 15 compatible = "isee,am335x-base0033", "isee,am335x-igep0033", "ti,am33xx";
16
17 hdmi {
18 compatible = "ti,tilcdc,slave";
19 i2c = <&i2c0>;
20 pinctrl-names = "default", "off";
21 pinctrl-0 = <&nxp_hdmi_pins>;
22 pinctrl-1 = <&nxp_hdmi_off_pins>;
23 status = "okay";
24 };
25
26 leds_base {
27 pinctrl-names = "default";
28 pinctrl-0 = <&leds_base_pins>;
29
30 compatible = "gpio-leds";
31
32 led@0 {
33 label = "base:red:user";
34 gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; /* gpio1_21 */
35 default-state = "off";
36 };
37
38 led@1 {
39 label = "base:green:user";
40 gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>; /* gpio2_0 */
41 default-state = "off";
42 };
43 };
44};
45
46&am33xx_pinmux {
47 nxp_hdmi_pins: pinmux_nxp_hdmi_pins {
48 pinctrl-single,pins = <
49 0x1b0 (PIN_OUTPUT | MUX_MODE3) /* xdma_event_intr0.clkout1 */
50 0xa0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data0 */
51 0xa4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data1 */
52 0xa8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data2 */
53 0xac (PIN_OUTPUT | MUX_MODE0) /* lcd_data3 */
54 0xb0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data4 */
55 0xb4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data5 */
56 0xb8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data6 */
57 0xbc (PIN_OUTPUT | MUX_MODE0) /* lcd_data7 */
58 0xc0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data8 */
59 0xc4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data9 */
60 0xc8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data10 */
61 0xcc (PIN_OUTPUT | MUX_MODE0) /* lcd_data11 */
62 0xd0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data12 */
63 0xd4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data13 */
64 0xd8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data14 */
65 0xdc (PIN_OUTPUT | MUX_MODE0) /* lcd_data15 */
66 0xe0 (PIN_OUTPUT | MUX_MODE0) /* lcd_vsync */
67 0xe4 (PIN_OUTPUT | MUX_MODE0) /* lcd_hsync */
68 0xe8 (PIN_OUTPUT | MUX_MODE0) /* lcd_pclk */
69 0xec (PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en */
70 >;
71 };
72 nxp_hdmi_off_pins: pinmux_nxp_hdmi_off_pins {
73 pinctrl-single,pins = <
74 0x1b0 (PIN_OUTPUT | MUX_MODE3) /* xdma_event_intr0.clkout1 */
75 >;
76 };
77
78 leds_base_pins: pinmux_leds_base_pins {
79 pinctrl-single,pins = <
80 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */
81 0x88 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn3.gpio2_0 */
82 >;
83 };
84};
85
86&lcdc {
87 status = "okay";
88};
89
90&i2c0 {
91 eeprom: eeprom@50 {
92 compatible = "at,24c256";
93 reg = <0x50>;
94 };
16}; 95};
diff --git a/arch/arm/boot/dts/am335x-igep0033.dtsi b/arch/arm/boot/dts/am335x-igep0033.dtsi
index 619624479311..7063311a58d9 100644
--- a/arch/arm/boot/dts/am335x-igep0033.dtsi
+++ b/arch/arm/boot/dts/am335x-igep0033.dtsi
@@ -199,6 +199,35 @@
199 pinctrl-0 = <&uart0_pins>; 199 pinctrl-0 = <&uart0_pins>;
200}; 200};
201 201
202&usb {
203 status = "okay";
204
205 control@44e10000 {
206 status = "okay";
207 };
208
209 usb-phy@47401300 {
210 status = "okay";
211 };
212
213 usb-phy@47401b00 {
214 status = "okay";
215 };
216
217 usb@47401000 {
218 status = "okay";
219 };
220
221 usb@47401800 {
222 status = "okay";
223 dr_mode = "host";
224 };
225
226 dma-controller@07402000 {
227 status = "okay";
228 };
229};
230
202#include "tps65910.dtsi" 231#include "tps65910.dtsi"
203 232
204&tps { 233&tps {
diff --git a/arch/arm/boot/dts/animeo_ip.dts b/arch/arm/boot/dts/animeo_ip.dts
index 3a1de9eb5111..3c4f6d983cbd 100644
--- a/arch/arm/boot/dts/animeo_ip.dts
+++ b/arch/arm/boot/dts/animeo_ip.dts
@@ -90,34 +90,19 @@
90 nand-on-flash-bbt; 90 nand-on-flash-bbt;
91 status = "okay"; 91 status = "okay";
92 92
93 at91bootstrap@0 { 93 barebox@0 {
94 label = "at91bootstrap";
95 reg = <0x0 0x8000>;
96 };
97
98 barebox@8000 {
99 label = "barebox"; 94 label = "barebox";
100 reg = <0x8000 0x40000>; 95 reg = <0x0 0x58000>;
101 };
102
103 bareboxenv@48000 {
104 label = "bareboxenv";
105 reg = <0x48000 0x8000>;
106 };
107
108 user_block@0x50000 {
109 label = "user_block";
110 reg = <0x50000 0xb0000>;
111 }; 96 };
112 97
113 kernel@100000 { 98 u_boot_env@58000 {
114 label = "kernel"; 99 label = "u_boot_env";
115 reg = <0x100000 0x1b0000>; 100 reg = <0x58000 0x8000>;
116 }; 101 };
117 102
118 root@2b0000 { 103 ubi@60000 {
119 label = "root"; 104 label = "ubi";
120 reg = <0x2b0000 0x1D50000>; 105 reg = <0x60000 0x1FA0000>;
121 }; 106 };
122 }; 107 };
123 108
diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
index 90ce29dbe119..08a56bcfc724 100644
--- a/arch/arm/boot/dts/armada-370-db.dts
+++ b/arch/arm/boot/dts/armada-370-db.dts
@@ -99,22 +99,22 @@
99 spi-max-frequency = <50000000>; 99 spi-max-frequency = <50000000>;
100 }; 100 };
101 }; 101 };
102 };
102 103
103 pcie-controller { 104 pcie-controller {
105 status = "okay";
106 /*
107 * The two PCIe units are accessible through
108 * both standard PCIe slots and mini-PCIe
109 * slots on the board.
110 */
111 pcie@1,0 {
112 /* Port 0, Lane 0 */
113 status = "okay";
114 };
115 pcie@2,0 {
116 /* Port 1, Lane 0 */
104 status = "okay"; 117 status = "okay";
105 /*
106 * The two PCIe units are accessible through
107 * both standard PCIe slots and mini-PCIe
108 * slots on the board.
109 */
110 pcie@1,0 {
111 /* Port 0, Lane 0 */
112 status = "okay";
113 };
114 pcie@2,0 {
115 /* Port 1, Lane 0 */
116 status = "okay";
117 };
118 }; 118 };
119 }; 119 };
120 }; 120 };
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 46a541e626e7..b6b253924893 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -191,7 +191,7 @@
191 191
192 coherency-fabric@20200 { 192 coherency-fabric@20200 {
193 compatible = "marvell,coherency-fabric"; 193 compatible = "marvell,coherency-fabric";
194 reg = <0x20200 0xb0>, <0x21810 0x1c>; 194 reg = <0x20200 0xb0>, <0x21010 0x1c>;
195 }; 195 };
196 196
197 timer@20300 { 197 timer@20300 {
diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
index 3f5e6121c730..98335fb34b7a 100644
--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
@@ -47,7 +47,7 @@
47 /* 47 /*
48 * MV78230 has 2 PCIe units Gen2.0: One unit can be 48 * MV78230 has 2 PCIe units Gen2.0: One unit can be
49 * configured as x4 or quad x1 lanes. One unit is 49 * configured as x4 or quad x1 lanes. One unit is
50 * x4/x1. 50 * x1 only.
51 */ 51 */
52 pcie-controller { 52 pcie-controller {
53 compatible = "marvell,armada-xp-pcie"; 53 compatible = "marvell,armada-xp-pcie";
@@ -62,10 +62,10 @@
62 62
63 ranges = 63 ranges =
64 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ 64 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
65 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
66 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ 65 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
67 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ 66 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
68 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ 67 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
68 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
69 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ 69 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
70 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ 70 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
71 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */ 71 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
@@ -74,8 +74,8 @@
74 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */ 74 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
75 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */ 75 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
76 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */ 76 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
77 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */ 77 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
78 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>; 78 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>;
79 79
80 pcie@1,0 { 80 pcie@1,0 {
81 device_type = "pci"; 81 device_type = "pci";
@@ -145,20 +145,20 @@
145 status = "disabled"; 145 status = "disabled";
146 }; 146 };
147 147
148 pcie@9,0 { 148 pcie@5,0 {
149 device_type = "pci"; 149 device_type = "pci";
150 assigned-addresses = <0x82000800 0 0x42000 0 0x2000>; 150 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
151 reg = <0x4800 0 0 0 0>; 151 reg = <0x2800 0 0 0 0>;
152 #address-cells = <3>; 152 #address-cells = <3>;
153 #size-cells = <2>; 153 #size-cells = <2>;
154 #interrupt-cells = <1>; 154 #interrupt-cells = <1>;
155 ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 155 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
156 0x81000000 0 0 0x81000000 0x9 0 1 0>; 156 0x81000000 0 0 0x81000000 0x5 0 1 0>;
157 interrupt-map-mask = <0 0 0 0>; 157 interrupt-map-mask = <0 0 0 0>;
158 interrupt-map = <0 0 0 0 &mpic 99>; 158 interrupt-map = <0 0 0 0 &mpic 62>;
159 marvell,pcie-port = <2>; 159 marvell,pcie-port = <1>;
160 marvell,pcie-lane = <0>; 160 marvell,pcie-lane = <0>;
161 clocks = <&gateclk 26>; 161 clocks = <&gateclk 9>;
162 status = "disabled"; 162 status = "disabled";
163 }; 163 };
164 }; 164 };
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
index 3e9fd1353f89..66609684d41b 100644
--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -48,7 +48,7 @@
48 /* 48 /*
49 * MV78260 has 3 PCIe units Gen2.0: Two units can be 49 * MV78260 has 3 PCIe units Gen2.0: Two units can be
50 * configured as x4 or quad x1 lanes. One unit is 50 * configured as x4 or quad x1 lanes. One unit is
51 * x4/x1. 51 * x4 only.
52 */ 52 */
53 pcie-controller { 53 pcie-controller {
54 compatible = "marvell,armada-xp-pcie"; 54 compatible = "marvell,armada-xp-pcie";
@@ -68,7 +68,9 @@
68 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ 68 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
69 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ 69 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
70 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */ 70 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
71 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */ 71 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
72 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
73 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
72 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ 74 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
73 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ 75 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
74 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */ 76 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
@@ -77,10 +79,18 @@
77 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */ 79 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
78 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */ 80 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
79 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */ 81 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
80 0x82000000 0x9 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ 82
81 0x81000000 0x9 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */ 83 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
82 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */ 84 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
83 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>; 85 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
86 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
87 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
88 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
89 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
90 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
91
92 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
93 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>;
84 94
85 pcie@1,0 { 95 pcie@1,0 {
86 device_type = "pci"; 96 device_type = "pci";
@@ -106,8 +116,8 @@
106 #address-cells = <3>; 116 #address-cells = <3>;
107 #size-cells = <2>; 117 #size-cells = <2>;
108 #interrupt-cells = <1>; 118 #interrupt-cells = <1>;
109 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 119 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
110 0x81000000 0 0 0x81000000 0x2 0 1 0>; 120 0x81000000 0 0 0x81000000 0x2 0 1 0>;
111 interrupt-map-mask = <0 0 0 0>; 121 interrupt-map-mask = <0 0 0 0>;
112 interrupt-map = <0 0 0 0 &mpic 59>; 122 interrupt-map = <0 0 0 0 &mpic 59>;
113 marvell,pcie-port = <0>; 123 marvell,pcie-port = <0>;
@@ -150,37 +160,88 @@
150 status = "disabled"; 160 status = "disabled";
151 }; 161 };
152 162
153 pcie@9,0 { 163 pcie@5,0 {
154 device_type = "pci"; 164 device_type = "pci";
155 assigned-addresses = <0x82000800 0 0x42000 0 0x2000>; 165 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
156 reg = <0x4800 0 0 0 0>; 166 reg = <0x2800 0 0 0 0>;
157 #address-cells = <3>; 167 #address-cells = <3>;
158 #size-cells = <2>; 168 #size-cells = <2>;
159 #interrupt-cells = <1>; 169 #interrupt-cells = <1>;
160 ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 170 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
161 0x81000000 0 0 0x81000000 0x9 0 1 0>; 171 0x81000000 0 0 0x81000000 0x5 0 1 0>;
162 interrupt-map-mask = <0 0 0 0>; 172 interrupt-map-mask = <0 0 0 0>;
163 interrupt-map = <0 0 0 0 &mpic 99>; 173 interrupt-map = <0 0 0 0 &mpic 62>;
164 marvell,pcie-port = <2>; 174 marvell,pcie-port = <1>;
165 marvell,pcie-lane = <0>; 175 marvell,pcie-lane = <0>;
166 clocks = <&gateclk 26>; 176 clocks = <&gateclk 9>;
167 status = "disabled"; 177 status = "disabled";
168 }; 178 };
169 179
170 pcie@10,0 { 180 pcie@6,0 {
171 device_type = "pci"; 181 device_type = "pci";
172 assigned-addresses = <0x82000800 0 0x82000 0 0x2000>; 182 assigned-addresses = <0x82000800 0 0x84000 0 0x2000>;
173 reg = <0x5000 0 0 0 0>; 183 reg = <0x3000 0 0 0 0>;
174 #address-cells = <3>; 184 #address-cells = <3>;
175 #size-cells = <2>; 185 #size-cells = <2>;
176 #interrupt-cells = <1>; 186 #interrupt-cells = <1>;
177 ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0 187 ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
178 0x81000000 0 0 0x81000000 0xa 0 1 0>; 188 0x81000000 0 0 0x81000000 0x6 0 1 0>;
179 interrupt-map-mask = <0 0 0 0>; 189 interrupt-map-mask = <0 0 0 0>;
180 interrupt-map = <0 0 0 0 &mpic 103>; 190 interrupt-map = <0 0 0 0 &mpic 63>;
181 marvell,pcie-port = <3>; 191 marvell,pcie-port = <1>;
192 marvell,pcie-lane = <1>;
193 clocks = <&gateclk 10>;
194 status = "disabled";
195 };
196
197 pcie@7,0 {
198 device_type = "pci";
199 assigned-addresses = <0x82000800 0 0x88000 0 0x2000>;
200 reg = <0x3800 0 0 0 0>;
201 #address-cells = <3>;
202 #size-cells = <2>;
203 #interrupt-cells = <1>;
204 ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
205 0x81000000 0 0 0x81000000 0x7 0 1 0>;
206 interrupt-map-mask = <0 0 0 0>;
207 interrupt-map = <0 0 0 0 &mpic 64>;
208 marvell,pcie-port = <1>;
209 marvell,pcie-lane = <2>;
210 clocks = <&gateclk 11>;
211 status = "disabled";
212 };
213
214 pcie@8,0 {
215 device_type = "pci";
216 assigned-addresses = <0x82000800 0 0x8c000 0 0x2000>;
217 reg = <0x4000 0 0 0 0>;
218 #address-cells = <3>;
219 #size-cells = <2>;
220 #interrupt-cells = <1>;
221 ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
222 0x81000000 0 0 0x81000000 0x8 0 1 0>;
223 interrupt-map-mask = <0 0 0 0>;
224 interrupt-map = <0 0 0 0 &mpic 65>;
225 marvell,pcie-port = <1>;
226 marvell,pcie-lane = <3>;
227 clocks = <&gateclk 12>;
228 status = "disabled";
229 };
230
231 pcie@9,0 {
232 device_type = "pci";
233 assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
234 reg = <0x4800 0 0 0 0>;
235 #address-cells = <3>;
236 #size-cells = <2>;
237 #interrupt-cells = <1>;
238 ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
239 0x81000000 0 0 0x81000000 0x9 0 1 0>;
240 interrupt-map-mask = <0 0 0 0>;
241 interrupt-map = <0 0 0 0 &mpic 99>;
242 marvell,pcie-port = <2>;
182 marvell,pcie-lane = <0>; 243 marvell,pcie-lane = <0>;
183 clocks = <&gateclk 27>; 244 clocks = <&gateclk 26>;
184 status = "disabled"; 245 status = "disabled";
185 }; 246 };
186 }; 247 };
diff --git a/arch/arm/boot/dts/at91-cosino.dtsi b/arch/arm/boot/dts/at91-cosino.dtsi
new file mode 100644
index 000000000000..2093c4d7cd6a
--- /dev/null
+++ b/arch/arm/boot/dts/at91-cosino.dtsi
@@ -0,0 +1,122 @@
1/*
2 * at91-cosino.dtsi - Device Tree file for Cosino core module
3 *
4 * Copyright (C) 2013 - Rodolfo Giometti <giometti@linux.it>
5 * HCE Engineering
6 *
7 * Derived from at91sam9x5ek.dtsi by:
8 * Copyright (C) 2012 Atmel,
9 * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
10 *
11 * Licensed under GPLv2 or later.
12 */
13
14#include "at91sam9g35.dtsi"
15
16/ {
17 model = "HCE Cosino core module";
18 compatible = "hce,cosino", "atmel,at91sam9x5", "atmel,at91sam9";
19
20 chosen {
21 bootargs = "console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootfstype=ext3 rootwait";
22 };
23
24 memory {
25 reg = <0x20000000 0x8000000>;
26 };
27
28 clocks {
29 #address-cells = <1>;
30 #size-cells = <1>;
31 ranges;
32
33 main_clock: clock@0 {
34 compatible = "atmel,osc", "fixed-clock";
35 clock-frequency = <12000000>;
36 };
37 };
38
39 ahb {
40 apb {
41 mmc0: mmc@f0008000 {
42 pinctrl-0 = <
43 &pinctrl_board_mmc0
44 &pinctrl_mmc0_slot0_clk_cmd_dat0
45 &pinctrl_mmc0_slot0_dat1_3>;
46 status = "okay";
47 slot@0 {
48 reg = <0>;
49 bus-width = <4>;
50 cd-gpios = <&pioD 15 GPIO_ACTIVE_HIGH>;
51 };
52 };
53
54 dbgu: serial@fffff200 {
55 status = "okay";
56 };
57
58 usart0: serial@f801c000 {
59 status = "okay";
60 };
61
62 i2c0: i2c@f8010000 {
63 status = "okay";
64 };
65
66 adc0: adc@f804c000 {
67 atmel,adc-clock-rate = <1000000>;
68 atmel,adc-ts-wires = <4>;
69 atmel,adc-ts-pressure-threshold = <10000>;
70 status = "okay";
71 };
72
73 pinctrl@fffff400 {
74 mmc0 {
75 pinctrl_board_mmc0: mmc0-board {
76 atmel,pins =
77 <AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PD15 gpio CD pin pull up and deglitch */
78 };
79 };
80 };
81
82 watchdog@fffffe40 {
83 status = "okay";
84 };
85 };
86
87 nand0: nand@40000000 {
88 nand-bus-width = <8>;
89 nand-ecc-mode = "hw";
90 atmel,has-pmecc; /* Enable PMECC */
91 atmel,pmecc-cap = <4>;
92 atmel,pmecc-sector-size = <512>;
93 nand-on-flash-bbt;
94 status = "okay";
95
96 at91bootstrap@0 {
97 label = "at91bootstrap";
98 reg = <0x0 0x40000>;
99 };
100
101 uboot@40000 {
102 label = "u-boot";
103 reg = <0x40000 0x80000>;
104 };
105
106 ubootenv@c0000 {
107 label = "U-Boot Env";
108 reg = <0xc0000 0x140000>;
109 };
110
111 kernel@200000 {
112 label = "kernel";
113 reg = <0x200000 0x600000>;
114 };
115
116 rootfs@800000 {
117 label = "rootfs";
118 reg = <0x800000 0x0f800000>;
119 };
120 };
121 };
122};
diff --git a/arch/arm/boot/dts/at91-cosino_mega2560.dts b/arch/arm/boot/dts/at91-cosino_mega2560.dts
new file mode 100644
index 000000000000..f9415dd11f17
--- /dev/null
+++ b/arch/arm/boot/dts/at91-cosino_mega2560.dts
@@ -0,0 +1,84 @@
1/*
2 * at91-cosino_mega2560.dts - Device Tree file for Cosino board with
3 * Mega 2560 extension
4 *
5 * Copyright (C) 2013 - Rodolfo Giometti <giometti@linux.it>
6 * HCE Engineering
7 *
8 * Derived from at91sam9g35ek.dts by:
9 * Copyright (C) 2012 Atmel,
10 * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
11 *
12 * Licensed under GPLv2 or later.
13 */
14
15/dts-v1/;
16#include "at91-cosino.dtsi"
17
18/ {
19 model = "HCE Cosino Mega 2560";
20 compatible = "hce,cosino_mega2560", "atmel,at91sam9x5", "atmel,at91sam9";
21
22 ahb {
23 apb {
24 macb0: ethernet@f802c000 {
25 phy-mode = "rmii";
26 status = "okay";
27 };
28
29 adc0: adc@f804c000 {
30 atmel,adc-clock-rate = <1000000>;
31 atmel,adc-ts-wires = <4>;
32 atmel,adc-ts-pressure-threshold = <10000>;
33 status = "okay";
34 };
35
36
37 tsadcc: tsadcc@f804c000 {
38 status = "okay";
39 };
40
41 rtc@fffffeb0 {
42 status = "okay";
43 };
44
45 usart1: serial@f8020000 {
46 status = "okay";
47 };
48
49 usart2: serial@f8024000 {
50 status = "okay";
51 };
52
53 usb2: gadget@f803c000 {
54 atmel,vbus-gpio = <&pioB 16 GPIO_ACTIVE_HIGH>;
55 status = "okay";
56 };
57
58 mmc1: mmc@f000c000 {
59 pinctrl-0 = <
60 &pinctrl_mmc1_slot0_clk_cmd_dat0
61 &pinctrl_mmc1_slot0_dat1_3>;
62 status = "okay";
63 slot@0 {
64 reg = <0>;
65 bus-width = <4>;
66 non-removable;
67 };
68 };
69 };
70
71 usb0: ohci@00600000 {
72 status = "okay";
73 num-ports = <3>;
74 atmel,vbus-gpio = <0 /* &pioD 18 GPIO_ACTIVE_LOW */
75 &pioD 19 GPIO_ACTIVE_LOW
76 &pioD 20 GPIO_ACTIVE_LOW
77 >;
78 };
79
80 usb1: ehci@00700000 {
81 status = "okay";
82 };
83 };
84};
diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi
index f77065506f1e..c61b16fba79b 100644
--- a/arch/arm/boot/dts/at91rm9200.dtsi
+++ b/arch/arm/boot/dts/at91rm9200.dtsi
@@ -191,12 +191,12 @@
191 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA18 periph A */ 191 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA18 periph A */
192 }; 192 };
193 193
194 pinctrl_uart0_rts: uart0_rts-0 { 194 pinctrl_uart0_cts: uart0_cts-0 {
195 atmel,pins = 195 atmel,pins =
196 <AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA20 periph A */ 196 <AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA20 periph A */
197 }; 197 };
198 198
199 pinctrl_uart0_cts: uart0_cts-0 { 199 pinctrl_uart0_rts: uart0_rts-0 {
200 atmel,pins = 200 atmel,pins =
201 <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA21 periph A */ 201 <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA21 periph A */
202 }; 202 };
diff --git a/arch/arm/boot/dts/at91rm9200ek.dts b/arch/arm/boot/dts/at91rm9200ek.dts
index d2d72c3b44c4..df6b0aa0e4dd 100644
--- a/arch/arm/boot/dts/at91rm9200ek.dts
+++ b/arch/arm/boot/dts/at91rm9200ek.dts
@@ -29,10 +29,22 @@
29 29
30 ahb { 30 ahb {
31 apb { 31 apb {
32 dbgu: serial@fffff200 { 32 usb1: gadget@fffb0000 {
33 atmel,vbus-gpio = <&pioD 4 GPIO_ACTIVE_HIGH>;
34 atmel,pullup-gpio = <&pioD 5 GPIO_ACTIVE_HIGH>;
33 status = "okay"; 35 status = "okay";
34 }; 36 };
35 37
38 macb0: ethernet@fffbc000 {
39 phy-mode = "rmii";
40 status = "okay";
41
42 phy0: ethernet-phy {
43 interrupt-parent = <&pioC>;
44 interrupts = <4 IRQ_TYPE_EDGE_BOTH>;
45 };
46 };
47
36 usart1: serial@fffc4000 { 48 usart1: serial@fffc4000 {
37 pinctrl-0 = 49 pinctrl-0 =
38 <&pinctrl_uart1 50 <&pinctrl_uart1
@@ -44,16 +56,6 @@
44 status = "okay"; 56 status = "okay";
45 }; 57 };
46 58
47 macb0: ethernet@fffbc000 {
48 phy-mode = "rmii";
49 status = "okay";
50 };
51
52 usb1: gadget@fffb0000 {
53 atmel,vbus-gpio = <&pioD 4 GPIO_ACTIVE_HIGH>;
54 status = "okay";
55 };
56
57 spi0: spi@fffe0000 { 59 spi0: spi@fffe0000 {
58 status = "okay"; 60 status = "okay";
59 cs-gpios = <&pioA 3 0>, <0>, <0>, <0>; 61 cs-gpios = <&pioA 3 0>, <0>, <0>, <0>;
@@ -63,12 +65,45 @@
63 reg = <0>; 65 reg = <0>;
64 }; 66 };
65 }; 67 };
68
69 dbgu: serial@fffff200 {
70 status = "okay";
71 };
66 }; 72 };
67 73
68 usb0: ohci@00300000 { 74 usb0: ohci@00300000 {
69 num-ports = <2>; 75 num-ports = <2>;
70 status = "okay"; 76 status = "okay";
71 }; 77 };
78
79 nor_flash@10000000 {
80 compatible = "cfi-flash";
81 reg = <0x10000000 0x800000>;
82 linux,mtd-name = "physmap-flash.0";
83 bank-width = <2>;
84 #address-cells = <1>;
85 #size-cells = <1>;
86
87 barebox@0 {
88 label = "barebox";
89 reg = <0x00000 0x40000>;
90 };
91
92 bareboxenv@40000 {
93 label = "bareboxenv";
94 reg = <0x40000 0x10000>;
95 };
96
97 kernel@50000 {
98 label = "kernel";
99 reg = <0x50000 0x300000>;
100 };
101
102 root@350000 {
103 label = "root";
104 reg = <0x350000 0x4B0000>;
105 };
106 };
72 }; 107 };
73 108
74 leds { 109 leds {
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index d5bd65f74602..c8fa9b9f07e3 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -30,6 +30,7 @@
30 i2c0 = &i2c0; 30 i2c0 = &i2c0;
31 ssc0 = &ssc0; 31 ssc0 = &ssc0;
32 ssc1 = &ssc1; 32 ssc1 = &ssc1;
33 pwm0 = &pwm0;
33 }; 34 };
34 cpus { 35 cpus {
35 #address-cells = <0>; 36 #address-cells = <0>;
@@ -366,6 +367,34 @@
366 }; 367 };
367 }; 368 };
368 369
370 fb {
371 pinctrl_fb: fb-0 {
372 atmel,pins =
373 <AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC1 periph A */
374 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC2 periph A */
375 AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC3 periph A */
376 AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB9 periph B */
377 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 periph A */
378 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 periph A */
379 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 periph A */
380 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC9 periph A */
381 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC10 periph A */
382 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC11 periph A */
383 AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC14 periph A */
384 AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC15 periph A */
385 AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC16 periph A */
386 AT91_PIOC 12 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC12 periph B */
387 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC18 periph A */
388 AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC19 periph A */
389 AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC22 periph A */
390 AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC23 periph A */
391 AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC24 periph A */
392 AT91_PIOC 17 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC17 periph B */
393 AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC26 periph A */
394 AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC27 periph A */
395 };
396 };
397
369 pioA: gpio@fffff200 { 398 pioA: gpio@fffff200 {
370 compatible = "atmel,at91rm9200-gpio"; 399 compatible = "atmel,at91rm9200-gpio";
371 reg = <0xfffff200 0x200>; 400 reg = <0xfffff200 0x200>;
@@ -547,6 +576,23 @@
547 pinctrl-0 = <&pinctrl_spi1>; 576 pinctrl-0 = <&pinctrl_spi1>;
548 status = "disabled"; 577 status = "disabled";
549 }; 578 };
579
580 pwm0: pwm@fffb8000 {
581 compatible = "atmel,at91sam9rl-pwm";
582 reg = <0xfffb8000 0x300>;
583 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 4>;
584 #pwm-cells = <3>;
585 status = "disabled";
586 };
587 };
588
589 fb0: fb@0x00700000 {
590 compatible = "atmel,at91sam9263-lcdc";
591 reg = <0x00700000 0x1000>;
592 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 3>;
593 pinctrl-names = "default";
594 pinctrl-0 = <&pinctrl_fb>;
595 status = "disabled";
550 }; 596 };
551 597
552 nand0: nand@40000000 { 598 nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/at91sam9263ek.dts
index 70f835b55c0b..15009c9f2293 100644
--- a/arch/arm/boot/dts/at91sam9263ek.dts
+++ b/arch/arm/boot/dts/at91sam9263ek.dts
@@ -95,6 +95,36 @@
95 }; 95 };
96 }; 96 };
97 97
98 fb0: fb@0x00700000 {
99 display = <&display0>;
100 status = "okay";
101
102 display0: display {
103 bits-per-pixel = <16>;
104 atmel,lcdcon-backlight;
105 atmel,dmacon = <0x1>;
106 atmel,lcdcon2 = <0x80008002>;
107 atmel,guard-time = <1>;
108
109 display-timings {
110 native-mode = <&timing0>;
111 timing0: timing0 {
112 clock-frequency = <4965000>;
113 hactive = <240>;
114 vactive = <320>;
115 hback-porch = <1>;
116 hfront-porch = <33>;
117 vback-porch = <1>;
118 vfront-porch = <0>;
119 hsync-len = <5>;
120 vsync-len = <1>;
121 hsync-active = <1>;
122 vsync-active = <1>;
123 };
124 };
125 };
126 };
127
98 nand0: nand@40000000 { 128 nand0: nand@40000000 {
99 nand-bus-width = <8>; 129 nand-bus-width = <8>;
100 nand-ecc-mode = "soft"; 130 nand-ecc-mode = "soft";
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index c3e514837074..ef0857cb171c 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -37,6 +37,7 @@
37 i2c1 = &i2c1; 37 i2c1 = &i2c1;
38 ssc0 = &ssc0; 38 ssc0 = &ssc0;
39 ssc1 = &ssc1; 39 ssc1 = &ssc1;
40 pwm0 = &pwm0;
40 }; 41 };
41 cpus { 42 cpus {
42 #address-cells = <0>; 43 #address-cells = <0>;
@@ -143,6 +144,22 @@
143 }; 144 };
144 }; 145 };
145 146
147 i2c0 {
148 pinctrl_i2c0: i2c0-0 {
149 atmel,pins =
150 <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA21 periph A TWCK0 */
151 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA20 periph A TWD0 */
152 };
153 };
154
155 i2c1 {
156 pinctrl_i2c1: i2c1-0 {
157 atmel,pins =
158 <AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A TWCK1 */
159 AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A TWD1 */
160 };
161 };
162
146 usart0 { 163 usart0 {
147 pinctrl_usart0: usart0-0 { 164 pinctrl_usart0: usart0-0 {
148 atmel,pins = 165 atmel,pins =
@@ -425,6 +442,42 @@
425 }; 442 };
426 }; 443 };
427 444
445 fb {
446 pinctrl_fb: fb-0 {
447 atmel,pins =
448 <AT91_PIOE 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE0 periph A */
449 AT91_PIOE 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE2 periph A */
450 AT91_PIOE 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE3 periph A */
451 AT91_PIOE 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE4 periph A */
452 AT91_PIOE 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE5 periph A */
453 AT91_PIOE 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE6 periph A */
454 AT91_PIOE 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE7 periph A */
455 AT91_PIOE 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE8 periph A */
456 AT91_PIOE 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE9 periph A */
457 AT91_PIOE 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE10 periph A */
458 AT91_PIOE 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE11 periph A */
459 AT91_PIOE 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE12 periph A */
460 AT91_PIOE 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE13 periph A */
461 AT91_PIOE 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE14 periph A */
462 AT91_PIOE 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE15 periph A */
463 AT91_PIOE 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE16 periph A */
464 AT91_PIOE 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE17 periph A */
465 AT91_PIOE 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE18 periph A */
466 AT91_PIOE 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE19 periph A */
467 AT91_PIOE 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE20 periph A */
468 AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE21 periph A */
469 AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE22 periph A */
470 AT91_PIOE 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE23 periph A */
471 AT91_PIOE 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE24 periph A */
472 AT91_PIOE 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE25 periph A */
473 AT91_PIOE 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE26 periph A */
474 AT91_PIOE 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE27 periph A */
475 AT91_PIOE 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE28 periph A */
476 AT91_PIOE 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE29 periph A */
477 AT91_PIOE 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PE30 periph A */
478 };
479 };
480
428 pioA: gpio@fffff200 { 481 pioA: gpio@fffff200 {
429 compatible = "atmel,at91rm9200-gpio"; 482 compatible = "atmel,at91rm9200-gpio";
430 reg = <0xfffff200 0x200>; 483 reg = <0xfffff200 0x200>;
@@ -542,6 +595,8 @@
542 compatible = "atmel,at91sam9g10-i2c"; 595 compatible = "atmel,at91sam9g10-i2c";
543 reg = <0xfff84000 0x100>; 596 reg = <0xfff84000 0x100>;
544 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>; 597 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>;
598 pinctrl-names = "default";
599 pinctrl-0 = <&pinctrl_i2c0>;
545 #address-cells = <1>; 600 #address-cells = <1>;
546 #size-cells = <0>; 601 #size-cells = <0>;
547 status = "disabled"; 602 status = "disabled";
@@ -551,6 +606,8 @@
551 compatible = "atmel,at91sam9g10-i2c"; 606 compatible = "atmel,at91sam9g10-i2c";
552 reg = <0xfff88000 0x100>; 607 reg = <0xfff88000 0x100>;
553 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>; 608 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>;
609 pinctrl-names = "default";
610 pinctrl-0 = <&pinctrl_i2c1>;
554 #address-cells = <1>; 611 #address-cells = <1>;
555 #size-cells = <0>; 612 #size-cells = <0>;
556 status = "disabled"; 613 status = "disabled";
@@ -614,10 +671,19 @@
614 }; 671 };
615 }; 672 };
616 673
674 pwm0: pwm@fffb8000 {
675 compatible = "atmel,at91sam9rl-pwm";
676 reg = <0xfffb8000 0x300>;
677 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>;
678 #pwm-cells = <3>;
679 status = "disabled";
680 };
681
617 mmc0: mmc@fff80000 { 682 mmc0: mmc@fff80000 {
618 compatible = "atmel,hsmci"; 683 compatible = "atmel,hsmci";
619 reg = <0xfff80000 0x600>; 684 reg = <0xfff80000 0x600>;
620 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; 685 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
686 pinctrl-names = "default";
621 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>; 687 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>;
622 dma-names = "rxtx"; 688 dma-names = "rxtx";
623 #address-cells = <1>; 689 #address-cells = <1>;
@@ -629,6 +695,7 @@
629 compatible = "atmel,hsmci"; 695 compatible = "atmel,hsmci";
630 reg = <0xfffd0000 0x600>; 696 reg = <0xfffd0000 0x600>;
631 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>; 697 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>;
698 pinctrl-names = "default";
632 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>; 699 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>;
633 dma-names = "rxtx"; 700 dma-names = "rxtx";
634 #address-cells = <1>; 701 #address-cells = <1>;
@@ -727,6 +794,15 @@
727 }; 794 };
728 }; 795 };
729 796
797 fb0: fb@0x00500000 {
798 compatible = "atmel,at91sam9g45-lcdc";
799 reg = <0x00500000 0x1000>;
800 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>;
801 pinctrl-names = "default";
802 pinctrl-0 = <&pinctrl_fb>;
803 status = "disabled";
804 };
805
730 nand0: nand@40000000 { 806 nand0: nand@40000000 {
731 compatible = "atmel,at91rm9200-nand"; 807 compatible = "atmel,at91rm9200-nand";
732 #address-cells = <1>; 808 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
index a4b00e5c61c0..7ff665a8c708 100644
--- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
+++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
@@ -105,6 +105,14 @@
105 AT91_PIOD 29 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PD29 gpio WP pin pull up */ 105 AT91_PIOD 29 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PD29 gpio WP pin pull up */
106 }; 106 };
107 }; 107 };
108
109 pwm0 {
110 pinctrl_pwm_leds: pwm-led {
111 atmel,pins =
112 <AT91_PIOD 0 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PD0 periph B */
113 AT91_PIOD 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PD31 periph B */
114 };
115 };
108 }; 116 };
109 117
110 spi0: spi@fffa4000{ 118 spi0: spi@fffa4000{
@@ -121,6 +129,42 @@
121 atmel,vbus-gpio = <&pioB 19 GPIO_ACTIVE_HIGH>; 129 atmel,vbus-gpio = <&pioB 19 GPIO_ACTIVE_HIGH>;
122 status = "okay"; 130 status = "okay";
123 }; 131 };
132
133 pwm0: pwm@fffb8000 {
134 status = "okay";
135
136 pinctrl-names = "default";
137 pinctrl-0 = <&pinctrl_pwm_leds>;
138 };
139 };
140
141 fb0: fb@0x00500000 {
142 display = <&display0>;
143 status = "okay";
144
145 display0: display {
146 bits-per-pixel = <32>;
147 atmel,lcdcon-backlight;
148 atmel,dmacon = <0x1>;
149 atmel,lcdcon2 = <0x80008002>;
150 atmel,guard-time = <9>;
151 atmel,lcd-wiring-mode = "RGB";
152
153 display-timings {
154 native-mode = <&timing0>;
155 timing0: timing0 {
156 clock-frequency = <9000000>;
157 hactive = <480>;
158 vactive = <272>;
159 hback-porch = <1>;
160 hfront-porch = <1>;
161 vback-porch = <40>;
162 vfront-porch = <1>;
163 hsync-len = <45>;
164 vsync-len = <1>;
165 };
166 };
167 };
124 }; 168 };
125 169
126 nand0: nand@40000000 { 170 nand0: nand@40000000 {
@@ -165,16 +209,22 @@
165 gpios = <&pioD 30 GPIO_ACTIVE_HIGH>; 209 gpios = <&pioD 30 GPIO_ACTIVE_HIGH>;
166 linux,default-trigger = "heartbeat"; 210 linux,default-trigger = "heartbeat";
167 }; 211 };
212 };
213
214 pwmleds {
215 compatible = "pwm-leds";
168 216
169 d6 { 217 d6 {
170 label = "d6"; 218 label = "d6";
171 gpios = <&pioD 0 GPIO_ACTIVE_LOW>; 219 pwms = <&pwm0 3 5000 0>;
220 max-brightness = <255>;
172 linux,default-trigger = "nand-disk"; 221 linux,default-trigger = "nand-disk";
173 }; 222 };
174 223
175 d7 { 224 d7 {
176 label = "d7"; 225 label = "d7";
177 gpios = <&pioD 31 GPIO_ACTIVE_LOW>; 226 pwms = <&pwm0 1 5000 0>;
227 max-brightness = <255>;
178 linux,default-trigger = "mmc0"; 228 linux,default-trigger = "mmc0";
179 }; 229 };
180 }; 230 };
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index 6224f9fe2f2b..7248270a3ea6 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -33,6 +33,7 @@
33 i2c0 = &i2c0; 33 i2c0 = &i2c0;
34 i2c1 = &i2c1; 34 i2c1 = &i2c1;
35 ssc0 = &ssc0; 35 ssc0 = &ssc0;
36 pwm0 = &pwm0;
36 }; 37 };
37 cpus { 38 cpus {
38 #address-cells = <0>; 39 #address-cells = <0>;
@@ -542,6 +543,14 @@
542 reg = <0xfffffe40 0x10>; 543 reg = <0xfffffe40 0x10>;
543 status = "disabled"; 544 status = "disabled";
544 }; 545 };
546
547 pwm0: pwm@f8034000 {
548 compatible = "atmel,at91sam9rl-pwm";
549 reg = <0xf8034000 0x300>;
550 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>;
551 #pwm-cells = <3>;
552 status = "disabled";
553 };
545 }; 554 };
546 555
547 nand0: nand@40000000 { 556 nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 40267a116c3c..6e5e9cfc3c49 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -35,6 +35,7 @@
35 i2c1 = &i2c1; 35 i2c1 = &i2c1;
36 i2c2 = &i2c2; 36 i2c2 = &i2c2;
37 ssc0 = &ssc0; 37 ssc0 = &ssc0;
38 pwm0 = &pwm0;
38 }; 39 };
39 cpus { 40 cpus {
40 #address-cells = <0>; 41 #address-cells = <0>;
@@ -762,6 +763,14 @@
762 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 763 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
763 status = "disabled"; 764 status = "disabled";
764 }; 765 };
766
767 pwm0: pwm@f8034000 {
768 compatible = "atmel,at91sam9rl-pwm";
769 reg = <0xf8034000 0x300>;
770 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>;
771 #pwm-cells = <3>;
772 status = "disabled";
773 };
765 }; 774 };
766 775
767 nand0: nand@40000000 { 776 nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9x5_usart3.dtsi b/arch/arm/boot/dts/at91sam9x5_usart3.dtsi
index 2347e9563cef..6801106fa1f8 100644
--- a/arch/arm/boot/dts/at91sam9x5_usart3.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5_usart3.dtsi
@@ -11,6 +11,10 @@
11#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/interrupt-controller/irq.h>
12 12
13/ { 13/ {
14 aliases {
15 serial4 = &usart3;
16 };
17
14 ahb { 18 ahb {
15 apb { 19 apb {
16 pinctrl@fffff400 { 20 pinctrl@fffff400 {
diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi
index 1e12aeff403b..aa537ed13f0a 100644
--- a/arch/arm/boot/dts/bcm2835.dtsi
+++ b/arch/arm/boot/dts/bcm2835.dtsi
@@ -85,6 +85,8 @@
85 reg = <0x7e205000 0x1000>; 85 reg = <0x7e205000 0x1000>;
86 interrupts = <2 21>; 86 interrupts = <2 21>;
87 clocks = <&clk_i2c>; 87 clocks = <&clk_i2c>;
88 #address-cells = <1>;
89 #size-cells = <0>;
88 status = "disabled"; 90 status = "disabled";
89 }; 91 };
90 92
@@ -93,6 +95,8 @@
93 reg = <0x7e804000 0x1000>; 95 reg = <0x7e804000 0x1000>;
94 interrupts = <2 21>; 96 interrupts = <2 21>;
95 clocks = <&clk_i2c>; 97 clocks = <&clk_i2c>;
98 #address-cells = <1>;
99 #size-cells = <0>;
96 status = "disabled"; 100 status = "disabled";
97 }; 101 };
98 102
diff --git a/arch/arm/boot/dts/emev2-kzm9d.dts b/arch/arm/boot/dts/emev2-kzm9d.dts
index 861aa7d6fc7d..50ccd151091e 100644
--- a/arch/arm/boot/dts/emev2-kzm9d.dts
+++ b/arch/arm/boot/dts/emev2-kzm9d.dts
@@ -9,7 +9,10 @@
9 */ 9 */
10/dts-v1/; 10/dts-v1/;
11 11
12/include/ "emev2.dtsi" 12#include "emev2.dtsi"
13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/input/input.h>
15#include <dt-bindings/interrupt-controller/irq.h>
13 16
14/ { 17/ {
15 model = "EMEV2 KZM9D Board"; 18 model = "EMEV2 KZM9D Board";
@@ -47,11 +50,46 @@
47 reg = <0x20000000 0x10000>; 50 reg = <0x20000000 0x10000>;
48 phy-mode = "mii"; 51 phy-mode = "mii";
49 interrupt-parent = <&gpio0>; 52 interrupt-parent = <&gpio0>;
50 interrupts = <1 1>; /* active high */ 53 interrupts = <1 IRQ_TYPE_EDGE_RISING>;
51 reg-io-width = <4>; 54 reg-io-width = <4>;
52 smsc,irq-active-high; 55 smsc,irq-active-high;
53 smsc,irq-push-pull; 56 smsc,irq-push-pull;
54 vddvario-supply = <&reg_1p8v>; 57 vddvario-supply = <&reg_1p8v>;
55 vdd33a-supply = <&reg_3p3v>; 58 vdd33a-supply = <&reg_3p3v>;
56 }; 59 };
60
61 gpio_keys {
62 compatible = "gpio-keys";
63 #address-cells = <1>;
64 #size-cells = <0>;
65
66 button@1 {
67 debounce_interval = <50>;
68 wakeup = <1>;
69 label = "DSW2-1";
70 linux,code = <KEY_1>;
71 gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
72 };
73 button@2 {
74 debounce_interval = <50>;
75 wakeup = <1>;
76 label = "DSW2-2";
77 linux,code = <KEY_2>;
78 gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>;
79 };
80 button@3 {
81 debounce_interval = <50>;
82 wakeup = <1>;
83 label = "DSW2-3";
84 linux,code = <KEY_3>;
85 gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
86 };
87 button@4 {
88 debounce_interval = <50>;
89 wakeup = <1>;
90 label = "DSW2-4";
91 linux,code = <KEY_4>;
92 gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>;
93 };
94 };
57}; 95};
diff --git a/arch/arm/boot/dts/emev2.dtsi b/arch/arm/boot/dts/emev2.dtsi
index 9063a4434d6a..e37985fa10e2 100644
--- a/arch/arm/boot/dts/emev2.dtsi
+++ b/arch/arm/boot/dts/emev2.dtsi
@@ -8,7 +8,8 @@
8 * kind, whether express or implied. 8 * kind, whether express or implied.
9 */ 9 */
10 10
11/include/ "skeleton.dtsi" 11#include "skeleton.dtsi"
12#include <dt-bindings/interrupt-controller/irq.h>
12 13
13/ { 14/ {
14 compatible = "renesas,emev2"; 15 compatible = "renesas,emev2";
@@ -48,44 +49,129 @@
48 49
49 pmu { 50 pmu {
50 compatible = "arm,cortex-a9-pmu"; 51 compatible = "arm,cortex-a9-pmu";
51 interrupts = <0 120 4>, 52 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
52 <0 121 4>; 53 <0 121 IRQ_TYPE_LEVEL_HIGH>;
54 };
55
56 smu@e0110000 {
57 compatible = "renesas,emev2-smu";
58 reg = <0xe0110000 0x10000>;
59 #address-cells = <2>;
60 #size-cells = <0>;
61
62 c32ki: c32ki {
63 compatible = "fixed-clock";
64 clock-frequency = <32768>;
65 #clock-cells = <0>;
66 };
67 pll3_fo: pll3_fo {
68 compatible = "fixed-factor-clock";
69 clocks = <&c32ki>;
70 clock-div = <1>;
71 clock-mult = <7000>;
72 #clock-cells = <0>;
73 };
74 usia_u0_sclkdiv: usia_u0_sclkdiv {
75 compatible = "renesas,emev2-smu-clkdiv";
76 reg = <0x610 0>;
77 clocks = <&pll3_fo>;
78 #clock-cells = <0>;
79 };
80 usib_u1_sclkdiv: usib_u1_sclkdiv {
81 compatible = "renesas,emev2-smu-clkdiv";
82 reg = <0x65c 0>;
83 clocks = <&pll3_fo>;
84 #clock-cells = <0>;
85 };
86 usib_u2_sclkdiv: usib_u2_sclkdiv {
87 compatible = "renesas,emev2-smu-clkdiv";
88 reg = <0x65c 16>;
89 clocks = <&pll3_fo>;
90 #clock-cells = <0>;
91 };
92 usib_u3_sclkdiv: usib_u3_sclkdiv {
93 compatible = "renesas,emev2-smu-clkdiv";
94 reg = <0x660 0>;
95 clocks = <&pll3_fo>;
96 #clock-cells = <0>;
97 };
98 usia_u0_sclk: usia_u0_sclk {
99 compatible = "renesas,emev2-smu-gclk";
100 reg = <0x4a0 1>;
101 clocks = <&usia_u0_sclkdiv>;
102 #clock-cells = <0>;
103 };
104 usib_u1_sclk: usib_u1_sclk {
105 compatible = "renesas,emev2-smu-gclk";
106 reg = <0x4b8 1>;
107 clocks = <&usib_u1_sclkdiv>;
108 #clock-cells = <0>;
109 };
110 usib_u2_sclk: usib_u2_sclk {
111 compatible = "renesas,emev2-smu-gclk";
112 reg = <0x4bc 1>;
113 clocks = <&usib_u2_sclkdiv>;
114 #clock-cells = <0>;
115 };
116 usib_u3_sclk: usib_u3_sclk {
117 compatible = "renesas,emev2-smu-gclk";
118 reg = <0x4c0 1>;
119 clocks = <&usib_u3_sclkdiv>;
120 #clock-cells = <0>;
121 };
122 sti_sclk: sti_sclk {
123 compatible = "renesas,emev2-smu-gclk";
124 reg = <0x528 1>;
125 clocks = <&c32ki>;
126 #clock-cells = <0>;
127 };
53 }; 128 };
54 129
55 sti@e0180000 { 130 sti@e0180000 {
56 compatible = "renesas,em-sti"; 131 compatible = "renesas,em-sti";
57 reg = <0xe0180000 0x54>; 132 reg = <0xe0180000 0x54>;
58 interrupts = <0 125 0>; 133 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
134 clocks = <&sti_sclk>;
135 clock-names = "sclk";
59 }; 136 };
60 137
61 uart@e1020000 { 138 uart@e1020000 {
62 compatible = "renesas,em-uart"; 139 compatible = "renesas,em-uart";
63 reg = <0xe1020000 0x38>; 140 reg = <0xe1020000 0x38>;
64 interrupts = <0 8 0>; 141 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
142 clocks = <&usia_u0_sclk>;
143 clock-names = "sclk";
65 }; 144 };
66 145
67 uart@e1030000 { 146 uart@e1030000 {
68 compatible = "renesas,em-uart"; 147 compatible = "renesas,em-uart";
69 reg = <0xe1030000 0x38>; 148 reg = <0xe1030000 0x38>;
70 interrupts = <0 9 0>; 149 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
150 clocks = <&usib_u1_sclk>;
151 clock-names = "sclk";
71 }; 152 };
72 153
73 uart@e1040000 { 154 uart@e1040000 {
74 compatible = "renesas,em-uart"; 155 compatible = "renesas,em-uart";
75 reg = <0xe1040000 0x38>; 156 reg = <0xe1040000 0x38>;
76 interrupts = <0 10 0>; 157 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
158 clocks = <&usib_u2_sclk>;
159 clock-names = "sclk";
77 }; 160 };
78 161
79 uart@e1050000 { 162 uart@e1050000 {
80 compatible = "renesas,em-uart"; 163 compatible = "renesas,em-uart";
81 reg = <0xe1050000 0x38>; 164 reg = <0xe1050000 0x38>;
82 interrupts = <0 11 0>; 165 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
166 clocks = <&usib_u3_sclk>;
167 clock-names = "sclk";
83 }; 168 };
84 169
85 gpio0: gpio@e0050000 { 170 gpio0: gpio@e0050000 {
86 compatible = "renesas,em-gio"; 171 compatible = "renesas,em-gio";
87 reg = <0xe0050000 0x2c>, <0xe0050040 0x20>; 172 reg = <0xe0050000 0x2c>, <0xe0050040 0x20>;
88 interrupts = <0 67 0>, <0 68 0>; 173 interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>,
174 <0 68 IRQ_TYPE_LEVEL_HIGH>;
89 gpio-controller; 175 gpio-controller;
90 #gpio-cells = <2>; 176 #gpio-cells = <2>;
91 ngpios = <32>; 177 ngpios = <32>;
@@ -95,7 +181,8 @@
95 gpio1: gpio@e0050080 { 181 gpio1: gpio@e0050080 {
96 compatible = "renesas,em-gio"; 182 compatible = "renesas,em-gio";
97 reg = <0xe0050080 0x2c>, <0xe00500c0 0x20>; 183 reg = <0xe0050080 0x2c>, <0xe00500c0 0x20>;
98 interrupts = <0 69 0>, <0 70 0>; 184 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>,
185 <0 70 IRQ_TYPE_LEVEL_HIGH>;
99 gpio-controller; 186 gpio-controller;
100 #gpio-cells = <2>; 187 #gpio-cells = <2>;
101 ngpios = <32>; 188 ngpios = <32>;
@@ -105,7 +192,8 @@
105 gpio2: gpio@e0050100 { 192 gpio2: gpio@e0050100 {
106 compatible = "renesas,em-gio"; 193 compatible = "renesas,em-gio";
107 reg = <0xe0050100 0x2c>, <0xe0050140 0x20>; 194 reg = <0xe0050100 0x2c>, <0xe0050140 0x20>;
108 interrupts = <0 71 0>, <0 72 0>; 195 interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>,
196 <0 72 IRQ_TYPE_LEVEL_HIGH>;
109 gpio-controller; 197 gpio-controller;
110 #gpio-cells = <2>; 198 #gpio-cells = <2>;
111 ngpios = <32>; 199 ngpios = <32>;
@@ -115,7 +203,8 @@
115 gpio3: gpio@e0050180 { 203 gpio3: gpio@e0050180 {
116 compatible = "renesas,em-gio"; 204 compatible = "renesas,em-gio";
117 reg = <0xe0050180 0x2c>, <0xe00501c0 0x20>; 205 reg = <0xe0050180 0x2c>, <0xe00501c0 0x20>;
118 interrupts = <0 73 0>, <0 74 0>; 206 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>,
207 <0 74 IRQ_TYPE_LEVEL_HIGH>;
119 gpio-controller; 208 gpio-controller;
120 #gpio-cells = <2>; 209 #gpio-cells = <2>;
121 ngpios = <32>; 210 ngpios = <32>;
@@ -125,7 +214,8 @@
125 gpio4: gpio@e0050200 { 214 gpio4: gpio@e0050200 {
126 compatible = "renesas,em-gio"; 215 compatible = "renesas,em-gio";
127 reg = <0xe0050200 0x2c>, <0xe0050240 0x20>; 216 reg = <0xe0050200 0x2c>, <0xe0050240 0x20>;
128 interrupts = <0 75 0>, <0 76 0>; 217 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>,
218 <0 76 IRQ_TYPE_LEVEL_HIGH>;
129 gpio-controller; 219 gpio-controller;
130 #gpio-cells = <2>; 220 #gpio-cells = <2>;
131 ngpios = <31>; 221 ngpios = <31>;
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index a73eeb5f258f..08452e183b57 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -85,21 +85,21 @@
85 reg = <0x10023CE0 0x20>; 85 reg = <0x10023CE0 0x20>;
86 }; 86 };
87 87
88 gic:interrupt-controller@10490000 { 88 gic: interrupt-controller@10490000 {
89 compatible = "arm,cortex-a9-gic"; 89 compatible = "arm,cortex-a9-gic";
90 #interrupt-cells = <3>; 90 #interrupt-cells = <3>;
91 interrupt-controller; 91 interrupt-controller;
92 reg = <0x10490000 0x1000>, <0x10480000 0x100>; 92 reg = <0x10490000 0x1000>, <0x10480000 0x100>;
93 }; 93 };
94 94
95 combiner:interrupt-controller@10440000 { 95 combiner: interrupt-controller@10440000 {
96 compatible = "samsung,exynos4210-combiner"; 96 compatible = "samsung,exynos4210-combiner";
97 #interrupt-cells = <2>; 97 #interrupt-cells = <2>;
98 interrupt-controller; 98 interrupt-controller;
99 reg = <0x10440000 0x1000>; 99 reg = <0x10440000 0x1000>;
100 }; 100 };
101 101
102 sys_reg: sysreg { 102 sys_reg: syscon@10010000 {
103 compatible = "samsung,exynos4-sysreg", "syscon"; 103 compatible = "samsung,exynos4-sysreg", "syscon";
104 reg = <0x10010000 0x400>; 104 reg = <0x10010000 0x400>;
105 }; 105 };
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts
index 1a12fb23767c..2aa13cb3bbed 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -313,7 +313,7 @@
313 display-timings { 313 display-timings {
314 native-mode = <&timing0>; 314 native-mode = <&timing0>;
315 timing0: timing { 315 timing0: timing {
316 clock-frequency = <50000>; 316 clock-frequency = <47500000>;
317 hactive = <1024>; 317 hactive = <1024>;
318 vactive = <600>; 318 vactive = <600>;
319 hfront-porch = <64>; 319 hfront-porch = <64>;
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 057d6829d319..48ecd7a755ab 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -36,11 +36,11 @@
36 reg = <0x10023CA0 0x20>; 36 reg = <0x10023CA0 0x20>;
37 }; 37 };
38 38
39 gic:interrupt-controller@10490000 { 39 gic: interrupt-controller@10490000 {
40 cpu-offset = <0x8000>; 40 cpu-offset = <0x8000>;
41 }; 41 };
42 42
43 combiner:interrupt-controller@10440000 { 43 combiner: interrupt-controller@10440000 {
44 samsung,combiner-nr = <16>; 44 samsung,combiner-nr = <16>;
45 interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, 45 interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
46 <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, 46 <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
@@ -51,24 +51,21 @@
51 mct@10050000 { 51 mct@10050000 {
52 compatible = "samsung,exynos4210-mct"; 52 compatible = "samsung,exynos4210-mct";
53 reg = <0x10050000 0x800>; 53 reg = <0x10050000 0x800>;
54 interrupt-controller;
55 #interrups-cells = <2>;
56 interrupt-parent = <&mct_map>; 54 interrupt-parent = <&mct_map>;
57 interrupts = <0 0>, <1 0>, <2 0>, <3 0>, 55 interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
58 <4 0>, <5 0>;
59 clocks = <&clock 3>, <&clock 344>; 56 clocks = <&clock 3>, <&clock 344>;
60 clock-names = "fin_pll", "mct"; 57 clock-names = "fin_pll", "mct";
61 58
62 mct_map: mct-map { 59 mct_map: mct-map {
63 #interrupt-cells = <2>; 60 #interrupt-cells = <1>;
64 #address-cells = <0>; 61 #address-cells = <0>;
65 #size-cells = <0>; 62 #size-cells = <0>;
66 interrupt-map = <0x0 0 &gic 0 57 0>, 63 interrupt-map = <0 &gic 0 57 0>,
67 <0x1 0 &gic 0 69 0>, 64 <1 &gic 0 69 0>,
68 <0x2 0 &combiner 12 6>, 65 <2 &combiner 12 6>,
69 <0x3 0 &combiner 12 7>, 66 <3 &combiner 12 7>,
70 <0x4 0 &gic 0 42 0>, 67 <4 &gic 0 42 0>,
71 <0x5 0 &gic 0 48 0>; 68 <5 &gic 0 48 0>;
72 }; 69 };
73 }; 70 };
74 71
diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi
index 6f34d7f6ba7e..94a43f9a05e2 100644
--- a/arch/arm/boot/dts/exynos4212.dtsi
+++ b/arch/arm/boot/dts/exynos4212.dtsi
@@ -22,7 +22,7 @@
22/ { 22/ {
23 compatible = "samsung,exynos4212"; 23 compatible = "samsung,exynos4212";
24 24
25 gic:interrupt-controller@10490000 { 25 gic: interrupt-controller@10490000 {
26 cpu-offset = <0x8000>; 26 cpu-offset = <0x8000>;
27 }; 27 };
28 28
@@ -34,26 +34,4 @@
34 <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>, 34 <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
35 <0 107 0>, <0 108 0>; 35 <0 107 0>, <0 108 0>;
36 }; 36 };
37
38 mct@10050000 {
39 compatible = "samsung,exynos4412-mct";
40 reg = <0x10050000 0x800>;
41 interrupt-controller;
42 #interrups-cells = <2>;
43 interrupt-parent = <&mct_map>;
44 interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
45 <4 0>, <5 0>;
46
47 mct_map: mct-map {
48 #interrupt-cells = <2>;
49 #address-cells = <0>;
50 #size-cells = <0>;
51 interrupt-map = <0x0 0 &gic 0 57 0>,
52 <0x1 0 &combiner 12 5>,
53 <0x2 0 &combiner 12 6>,
54 <0x3 0 &combiner 12 7>,
55 <0x4 0 &gic 1 12 0>,
56 <0x5 0 &gic 1 12 0>;
57 };
58 };
59}; 37};
diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts
index 46c678ee119c..8aad5f72ced7 100644
--- a/arch/arm/boot/dts/exynos4412-odroidx.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -38,9 +38,7 @@
38 }; 38 };
39 }; 39 };
40 40
41 mshc@12550000 { 41 mmc@12550000 {
42 #address-cells = <1>;
43 #size-cells = <0>;
44 pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; 42 pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
45 pinctrl-names = "default"; 43 pinctrl-names = "default";
46 vmmc-supply = <&ldo20_reg &buck8_reg>; 44 vmmc-supply = <&ldo20_reg &buck8_reg>;
@@ -49,7 +47,6 @@
49 num-slots = <1>; 47 num-slots = <1>;
50 supports-highspeed; 48 supports-highspeed;
51 broken-cd; 49 broken-cd;
52 fifo-depth = <0x80>;
53 card-detect-delay = <200>; 50 card-detect-delay = <200>;
54 samsung,dw-mshc-ciu-div = <3>; 51 samsung,dw-mshc-ciu-div = <3>;
55 samsung,dw-mshc-sdr-timing = <2 3>; 52 samsung,dw-mshc-sdr-timing = <2 3>;
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts
index d65984c440f6..6bc053924e9e 100644
--- a/arch/arm/boot/dts/exynos4412-origen.dts
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -122,9 +122,7 @@
122 status = "okay"; 122 status = "okay";
123 }; 123 };
124 124
125 mshc@12550000 { 125 mmc@12550000 {
126 #address-cells = <1>;
127 #size-cells = <0>;
128 pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; 126 pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
129 pinctrl-names = "default"; 127 pinctrl-names = "default";
130 status = "okay"; 128 status = "okay";
@@ -132,7 +130,6 @@
132 num-slots = <1>; 130 num-slots = <1>;
133 supports-highspeed; 131 supports-highspeed;
134 broken-cd; 132 broken-cd;
135 fifo-depth = <0x80>;
136 card-detect-delay = <200>; 133 card-detect-delay = <200>;
137 samsung,dw-mshc-ciu-div = <3>; 134 samsung,dw-mshc-ciu-div = <3>;
138 samsung,dw-mshc-sdr-timing = <2 3>; 135 samsung,dw-mshc-sdr-timing = <2 3>;
@@ -159,7 +156,7 @@
159 display-timings { 156 display-timings {
160 native-mode = <&timing0>; 157 native-mode = <&timing0>;
161 timing0: timing { 158 timing0: timing {
162 clock-frequency = <50000>; 159 clock-frequency = <47500000>;
163 hactive = <1024>; 160 hactive = <1024>;
164 vactive = <600>; 161 vactive = <600>;
165 hfront-porch = <64>; 162 hfront-porch = <64>;
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts
index fb7b9ae5f399..890ad275cb85 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -442,13 +442,25 @@
442 }; 442 };
443 }; 443 };
444 444
445 sdhci@12510000 { 445 mmc@12550000 {
446 bus-width = <8>; 446 num-slots = <1>;
447 supports-highspeed;
448 broken-cd;
447 non-removable; 449 non-removable;
448 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus8>; 450 card-detect-delay = <200>;
449 pinctrl-names = "default";
450 vmmc-supply = <&vemmc_reg>; 451 vmmc-supply = <&vemmc_reg>;
452 clock-frequency = <400000000>;
453 samsung,dw-mshc-ciu-div = <0>;
454 samsung,dw-mshc-sdr-timing = <2 3>;
455 samsung,dw-mshc-ddr-timing = <1 2>;
456 pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
457 pinctrl-names = "default";
451 status = "okay"; 458 status = "okay";
459
460 slot@0 {
461 reg = <0>;
462 bus-width = <8>;
463 };
452 }; 464 };
453 465
454 serial@13800000 { 466 serial@13800000 {
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
index e743e677a9e2..87b339c739de 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -22,7 +22,7 @@
22/ { 22/ {
23 compatible = "samsung,exynos4412"; 23 compatible = "samsung,exynos4412";
24 24
25 gic:interrupt-controller@10490000 { 25 gic: interrupt-controller@10490000 {
26 cpu-offset = <0x4000>; 26 cpu-offset = <0x4000>;
27 }; 27 };
28 28
@@ -35,37 +35,4 @@
35 <0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>; 35 <0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>;
36 }; 36 };
37 37
38 mct@10050000 {
39 compatible = "samsung,exynos4412-mct";
40 reg = <0x10050000 0x800>;
41 interrupt-controller;
42 #interrups-cells = <2>;
43 interrupt-parent = <&mct_map>;
44 interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
45 <4 0>, <5 0>, <6 0>, <7 0>;
46 clocks = <&clock 3>, <&clock 344>;
47 clock-names = "fin_pll", "mct";
48
49 mct_map: mct-map {
50 #interrupt-cells = <2>;
51 #address-cells = <0>;
52 #size-cells = <0>;
53 interrupt-map = <0x0 0 &gic 0 57 0>,
54 <0x1 0 &combiner 12 5>,
55 <0x2 0 &combiner 12 6>,
56 <0x3 0 &combiner 12 7>,
57 <0x4 0 &gic 1 12 0>,
58 <0x5 0 &gic 1 12 0>,
59 <0x6 0 &gic 1 12 0>,
60 <0x7 0 &gic 1 12 0>;
61 };
62 };
63
64 mshc@12550000 {
65 compatible = "samsung,exynos4412-dw-mshc";
66 reg = <0x12550000 0x1000>;
67 interrupts = <0 77 0>;
68 #address-cells = <1>;
69 #size-cells = <0>;
70 };
71}; 38};
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index ad531fe6ab95..5c412aa14738 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -28,6 +28,7 @@
28 pinctrl3 = &pinctrl_3; 28 pinctrl3 = &pinctrl_3;
29 fimc-lite0 = &fimc_lite_0; 29 fimc-lite0 = &fimc_lite_0;
30 fimc-lite1 = &fimc_lite_1; 30 fimc-lite1 = &fimc_lite_1;
31 mshc0 = &mshc_0;
31 }; 32 };
32 33
33 pd_isp: isp-power-domain@10023CA0 { 34 pd_isp: isp-power-domain@10023CA0 {
@@ -41,6 +42,26 @@
41 #clock-cells = <1>; 42 #clock-cells = <1>;
42 }; 43 };
43 44
45 mct@10050000 {
46 compatible = "samsung,exynos4412-mct";
47 reg = <0x10050000 0x800>;
48 interrupt-parent = <&mct_map>;
49 interrupts = <0>, <1>, <2>, <3>, <4>;
50 clocks = <&clock 3>, <&clock 344>;
51 clock-names = "fin_pll", "mct";
52
53 mct_map: mct-map {
54 #interrupt-cells = <1>;
55 #address-cells = <0>;
56 #size-cells = <0>;
57 interrupt-map = <0 &gic 0 57 0>,
58 <1 &combiner 12 5>,
59 <2 &combiner 12 6>,
60 <3 &combiner 12 7>,
61 <4 &gic 1 12 0>;
62 };
63 };
64
44 pinctrl_0: pinctrl@11400000 { 65 pinctrl_0: pinctrl@11400000 {
45 compatible = "samsung,exynos4x12-pinctrl"; 66 compatible = "samsung,exynos4x12-pinctrl";
46 reg = <0x11400000 0x1000>; 67 reg = <0x11400000 0x1000>;
@@ -176,4 +197,16 @@
176 }; 197 };
177 }; 198 };
178 }; 199 };
200
201 mshc_0: mmc@12550000 {
202 compatible = "samsung,exynos4412-dw-mshc";
203 reg = <0x12550000 0x1000>;
204 interrupts = <0 77 0>;
205 #address-cells = <1>;
206 #size-cells = <0>;
207 fifo-depth = <0x80>;
208 clocks = <&clock 301>, <&clock 149>;
209 clock-names = "biu", "ciu";
210 status = "disabled";
211 };
179}; 212};
diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index 074739d39e2d..258dca441f36 100644
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -23,7 +23,7 @@
23 reg = <0x10000000 0x100>; 23 reg = <0x10000000 0x100>;
24 }; 24 };
25 25
26 combiner:interrupt-controller@10440000 { 26 combiner: interrupt-controller@10440000 {
27 compatible = "samsung,exynos4210-combiner"; 27 compatible = "samsung,exynos4210-combiner";
28 #interrupt-cells = <2>; 28 #interrupt-cells = <2>;
29 interrupt-controller; 29 interrupt-controller;
@@ -39,7 +39,7 @@
39 <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>; 39 <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
40 }; 40 };
41 41
42 gic:interrupt-controller@10481000 { 42 gic: interrupt-controller@10481000 {
43 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; 43 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
44 #interrupt-cells = <3>; 44 #interrupt-cells = <3>;
45 interrupt-controller; 45 interrupt-controller;
@@ -50,27 +50,6 @@
50 interrupts = <1 9 0xf04>; 50 interrupts = <1 9 0xf04>;
51 }; 51 };
52 52
53 dwmmc_0: dwmmc0@12200000 {
54 compatible = "samsung,exynos5250-dw-mshc";
55 interrupts = <0 75 0>;
56 #address-cells = <1>;
57 #size-cells = <0>;
58 };
59
60 dwmmc_1: dwmmc1@12210000 {
61 compatible = "samsung,exynos5250-dw-mshc";
62 interrupts = <0 76 0>;
63 #address-cells = <1>;
64 #size-cells = <0>;
65 };
66
67 dwmmc_2: dwmmc2@12220000 {
68 compatible = "samsung,exynos5250-dw-mshc";
69 interrupts = <0 77 0>;
70 #address-cells = <1>;
71 #size-cells = <0>;
72 };
73
74 serial@12C00000 { 53 serial@12C00000 {
75 compatible = "samsung,exynos4210-uart"; 54 compatible = "samsung,exynos4210-uart";
76 reg = <0x12C00000 0x100>; 55 reg = <0x12C00000 0x100>;
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
index 684527087aa4..b42e658876e5 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -34,6 +34,7 @@
34 samsung,i2c-sda-delay = <100>; 34 samsung,i2c-sda-delay = <100>;
35 samsung,i2c-max-bus-freq = <20000>; 35 samsung,i2c-max-bus-freq = <20000>;
36 samsung,i2c-slave-addr = <0x66>; 36 samsung,i2c-slave-addr = <0x66>;
37 status = "okay";
37 38
38 s5m8767_pmic@66 { 39 s5m8767_pmic@66 {
39 compatible = "samsung,s5m8767-pmic"; 40 compatible = "samsung,s5m8767-pmic";
@@ -266,7 +267,7 @@
266 267
267 buck2_reg: BUCK2 { 268 buck2_reg: BUCK2 {
268 regulator-name = "vdd_arm"; 269 regulator-name = "vdd_arm";
269 regulator-min-microvolt = <925000>; 270 regulator-min-microvolt = <912500>;
270 regulator-max-microvolt = <1300000>; 271 regulator-max-microvolt = <1300000>;
271 regulator-always-on; 272 regulator-always-on;
272 regulator-boot-on; 273 regulator-boot-on;
@@ -302,11 +303,13 @@
302 buck7_reg: BUCK7 { 303 buck7_reg: BUCK7 {
303 regulator-name = "PVDD_BUCK7"; 304 regulator-name = "PVDD_BUCK7";
304 regulator-always-on; 305 regulator-always-on;
306 op_mode = <1>;
305 }; 307 };
306 308
307 buck8_reg: BUCK8 { 309 buck8_reg: BUCK8 {
308 regulator-name = "PVDD_BUCK8"; 310 regulator-name = "PVDD_BUCK8";
309 regulator-always-on; 311 regulator-always-on;
312 op_mode = <1>;
310 }; 313 };
311 314
312 buck9_reg: BUCK9 { 315 buck9_reg: BUCK9 {
@@ -319,11 +322,9 @@
319 }; 322 };
320 }; 323 };
321 324
322 i2c@12C70000 {
323 status = "disabled";
324 };
325
326 i2c@12C80000 { 325 i2c@12C80000 {
326 status = "okay";
327
327 samsung,i2c-sda-delay = <100>; 328 samsung,i2c-sda-delay = <100>;
328 samsung,i2c-max-bus-freq = <66000>; 329 samsung,i2c-max-bus-freq = <66000>;
329 samsung,i2c-slave-addr = <0x50>; 330 samsung,i2c-slave-addr = <0x50>;
@@ -335,7 +336,10 @@
335 }; 336 };
336 337
337 i2c@12C90000 { 338 i2c@12C90000 {
339 status = "okay";
340
338 wm1811a@1a { 341 wm1811a@1a {
342
339 compatible = "wlf,wm1811"; 343 compatible = "wlf,wm1811";
340 reg = <0x1a>; 344 reg = <0x1a>;
341 345
@@ -353,23 +357,9 @@
353 }; 357 };
354 }; 358 };
355 359
356 i2c@12CA0000 {
357 status = "disabled";
358 };
359
360 i2c@12CB0000 {
361 status = "disabled";
362 };
363
364 i2c@12CC0000 {
365 status = "disabled";
366 };
367
368 i2c@12CD0000 {
369 status = "disabled";
370 };
371
372 i2c@12CE0000 { 360 i2c@12CE0000 {
361 status = "okay";
362
373 samsung,i2c-sda-delay = <100>; 363 samsung,i2c-sda-delay = <100>;
374 samsung,i2c-max-bus-freq = <66000>; 364 samsung,i2c-max-bus-freq = <66000>;
375 samsung,i2c-slave-addr = <0x38>; 365 samsung,i2c-slave-addr = <0x38>;
@@ -380,15 +370,11 @@
380 }; 370 };
381 }; 371 };
382 372
383 i2c@121D0000 { 373 mmc_0: mmc@12200000 {
384 status = "disabled"; 374 status = "okay";
385 };
386
387 dwmmc_0: dwmmc0@12200000 {
388 num-slots = <1>; 375 num-slots = <1>;
389 supports-highspeed; 376 supports-highspeed;
390 broken-cd; 377 broken-cd;
391 fifo-depth = <0x80>;
392 card-detect-delay = <200>; 378 card-detect-delay = <200>;
393 samsung,dw-mshc-ciu-div = <3>; 379 samsung,dw-mshc-ciu-div = <3>;
394 samsung,dw-mshc-sdr-timing = <2 3>; 380 samsung,dw-mshc-sdr-timing = <2 3>;
@@ -403,14 +389,10 @@
403 }; 389 };
404 }; 390 };
405 391
406 dwmmc_1: dwmmc1@12210000 { 392 mmc_2: mmc@12220000 {
407 status = "disabled"; 393 status = "okay";
408 };
409
410 dwmmc_2: dwmmc2@12220000 {
411 num-slots = <1>; 394 num-slots = <1>;
412 supports-highspeed; 395 supports-highspeed;
413 fifo-depth = <0x80>;
414 card-detect-delay = <200>; 396 card-detect-delay = <200>;
415 samsung,dw-mshc-ciu-div = <3>; 397 samsung,dw-mshc-ciu-div = <3>;
416 samsung,dw-mshc-sdr-timing = <2 3>; 398 samsung,dw-mshc-sdr-timing = <2 3>;
@@ -426,26 +408,10 @@
426 }; 408 };
427 }; 409 };
428 410
429 dwmmc_3: dwmmc3@12230000 {
430 status = "disabled";
431 };
432
433 i2s0: i2s@03830000 { 411 i2s0: i2s@03830000 {
434 status = "okay"; 412 status = "okay";
435 }; 413 };
436 414
437 spi_0: spi@12d20000 {
438 status = "disabled";
439 };
440
441 spi_1: spi@12d30000 {
442 status = "disabled";
443 };
444
445 spi_2: spi@12d40000 {
446 status = "disabled";
447 };
448
449 gpio_keys { 415 gpio_keys {
450 compatible = "gpio-keys"; 416 compatible = "gpio-keys";
451 417
diff --git a/arch/arm/boot/dts/cros5250-common.dtsi b/arch/arm/boot/dts/exynos5250-cros-common.dtsi
index dc259e8b8a73..9a61494f45f5 100644
--- a/arch/arm/boot/dts/cros5250-common.dtsi
+++ b/arch/arm/boot/dts/exynos5250-cros-common.dtsi
@@ -27,14 +27,27 @@
27 i2c2_bus: i2c2-bus { 27 i2c2_bus: i2c2-bus {
28 samsung,pin-pud = <0>; 28 samsung,pin-pud = <0>;
29 }; 29 };
30
31 max77686_irq: max77686-irq {
32 samsung,pins = "gpx3-2";
33 samsung,pin-function = <0>;
34 samsung,pin-pud = <0>;
35 samsung,pin-drv = <0>;
36 };
30 }; 37 };
31 38
32 i2c@12C60000 { 39 i2c@12C60000 {
40 status = "okay";
33 samsung,i2c-sda-delay = <100>; 41 samsung,i2c-sda-delay = <100>;
34 samsung,i2c-max-bus-freq = <378000>; 42 samsung,i2c-max-bus-freq = <378000>;
35 43
36 max77686@09 { 44 max77686@09 {
37 compatible = "maxim,max77686"; 45 compatible = "maxim,max77686";
46 interrupt-parent = <&gpx3>;
47 interrupts = <2 0>;
48 pinctrl-names = "default";
49 pinctrl-0 = <&max77686_irq>;
50 wakeup-source;
38 reg = <0x09>; 51 reg = <0x09>;
39 52
40 voltage-regulators { 53 voltage-regulators {
@@ -173,6 +186,7 @@
173 }; 186 };
174 187
175 i2c@12C70000 { 188 i2c@12C70000 {
189 status = "okay";
176 samsung,i2c-sda-delay = <100>; 190 samsung,i2c-sda-delay = <100>;
177 samsung,i2c-max-bus-freq = <378000>; 191 samsung,i2c-max-bus-freq = <378000>;
178 192
@@ -186,6 +200,7 @@
186 }; 200 };
187 201
188 i2c@12C80000 { 202 i2c@12C80000 {
203 status = "okay";
189 samsung,i2c-sda-delay = <100>; 204 samsung,i2c-sda-delay = <100>;
190 samsung,i2c-max-bus-freq = <66000>; 205 samsung,i2c-max-bus-freq = <66000>;
191 206
@@ -196,30 +211,31 @@
196 }; 211 };
197 212
198 i2c@12C90000 { 213 i2c@12C90000 {
214 status = "okay";
199 samsung,i2c-sda-delay = <100>; 215 samsung,i2c-sda-delay = <100>;
200 samsung,i2c-max-bus-freq = <66000>; 216 samsung,i2c-max-bus-freq = <66000>;
201 }; 217 };
202 218
203 i2c@12CA0000 { 219 i2c@12CA0000 {
220 status = "okay";
204 samsung,i2c-sda-delay = <100>; 221 samsung,i2c-sda-delay = <100>;
205 samsung,i2c-max-bus-freq = <66000>; 222 samsung,i2c-max-bus-freq = <66000>;
206 }; 223 };
207 224
208 i2c@12CB0000 { 225 i2c@12CB0000 {
226 status = "okay";
209 samsung,i2c-sda-delay = <100>; 227 samsung,i2c-sda-delay = <100>;
210 samsung,i2c-max-bus-freq = <66000>; 228 samsung,i2c-max-bus-freq = <66000>;
211 }; 229 };
212 230
213 i2c@12CC0000 {
214 status = "disabled";
215 };
216
217 i2c@12CD0000 { 231 i2c@12CD0000 {
232 status = "okay";
218 samsung,i2c-sda-delay = <100>; 233 samsung,i2c-sda-delay = <100>;
219 samsung,i2c-max-bus-freq = <66000>; 234 samsung,i2c-max-bus-freq = <66000>;
220 }; 235 };
221 236
222 i2c@12CE0000 { 237 i2c@12CE0000 {
238 status = "okay";
223 samsung,i2c-sda-delay = <100>; 239 samsung,i2c-sda-delay = <100>;
224 samsung,i2c-max-bus-freq = <378000>; 240 samsung,i2c-max-bus-freq = <378000>;
225 241
@@ -229,11 +245,10 @@
229 }; 245 };
230 }; 246 };
231 247
232 dwmmc0@12200000 { 248 mmc@12200000 {
233 num-slots = <1>; 249 num-slots = <1>;
234 supports-highspeed; 250 supports-highspeed;
235 broken-cd; 251 broken-cd;
236 fifo-depth = <0x80>;
237 card-detect-delay = <200>; 252 card-detect-delay = <200>;
238 samsung,dw-mshc-ciu-div = <3>; 253 samsung,dw-mshc-ciu-div = <3>;
239 samsung,dw-mshc-sdr-timing = <2 3>; 254 samsung,dw-mshc-sdr-timing = <2 3>;
@@ -247,14 +262,9 @@
247 }; 262 };
248 }; 263 };
249 264
250 dwmmc1@12210000 { 265 mmc@12220000 {
251 status = "disabled";
252 };
253
254 dwmmc2@12220000 {
255 num-slots = <1>; 266 num-slots = <1>;
256 supports-highspeed; 267 supports-highspeed;
257 fifo-depth = <0x80>;
258 card-detect-delay = <200>; 268 card-detect-delay = <200>;
259 samsung,dw-mshc-ciu-div = <3>; 269 samsung,dw-mshc-ciu-div = <3>;
260 samsung,dw-mshc-sdr-timing = <2 3>; 270 samsung,dw-mshc-sdr-timing = <2 3>;
@@ -269,11 +279,10 @@
269 }; 279 };
270 }; 280 };
271 281
272 dwmmc3@12230000 { 282 mmc@12230000 {
273 num-slots = <1>; 283 num-slots = <1>;
274 supports-highspeed; 284 supports-highspeed;
275 broken-cd; 285 broken-cd;
276 fifo-depth = <0x80>;
277 card-detect-delay = <200>; 286 card-detect-delay = <200>;
278 samsung,dw-mshc-ciu-div = <3>; 287 samsung,dw-mshc-ciu-div = <3>;
279 samsung,dw-mshc-sdr-timing = <2 3>; 288 samsung,dw-mshc-sdr-timing = <2 3>;
@@ -286,19 +295,12 @@
286 }; 295 };
287 }; 296 };
288 297
289 spi_0: spi@12d20000 {
290 status = "disabled";
291 };
292
293 spi_1: spi@12d30000 { 298 spi_1: spi@12d30000 {
299 status = "okay";
294 samsung,spi-src-clk = <0>; 300 samsung,spi-src-clk = <0>;
295 num-cs = <1>; 301 num-cs = <1>;
296 }; 302 };
297 303
298 spi_2: spi@12d40000 {
299 status = "disabled";
300 };
301
302 hdmi { 304 hdmi {
303 hpd-gpio = <&gpx3 7 0>; 305 hpd-gpio = <&gpx3 7 0>;
304 }; 306 };
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index f86d56760a45..3e69837c435c 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -30,6 +30,7 @@
30 i2c@12C60000 { 30 i2c@12C60000 {
31 samsung,i2c-sda-delay = <100>; 31 samsung,i2c-sda-delay = <100>;
32 samsung,i2c-max-bus-freq = <20000>; 32 samsung,i2c-max-bus-freq = <20000>;
33 status = "okay";
33 34
34 eeprom@50 { 35 eeprom@50 {
35 compatible = "samsung,s524ad0xd1"; 36 compatible = "samsung,s524ad0xd1";
@@ -37,7 +38,7 @@
37 }; 38 };
38 }; 39 };
39 40
40 vdd:fixed-regulator@0 { 41 vdd: fixed-regulator@0 {
41 compatible = "regulator-fixed"; 42 compatible = "regulator-fixed";
42 regulator-name = "vdd-supply"; 43 regulator-name = "vdd-supply";
43 regulator-min-microvolt = <1800000>; 44 regulator-min-microvolt = <1800000>;
@@ -45,7 +46,7 @@
45 regulator-always-on; 46 regulator-always-on;
46 }; 47 };
47 48
48 dbvdd:fixed-regulator@1 { 49 dbvdd: fixed-regulator@1 {
49 compatible = "regulator-fixed"; 50 compatible = "regulator-fixed";
50 regulator-name = "dbvdd-supply"; 51 regulator-name = "dbvdd-supply";
51 regulator-min-microvolt = <3300000>; 52 regulator-min-microvolt = <3300000>;
@@ -53,7 +54,7 @@
53 regulator-always-on; 54 regulator-always-on;
54 }; 55 };
55 56
56 spkvdd:fixed-regulator@2 { 57 spkvdd: fixed-regulator@2 {
57 compatible = "regulator-fixed"; 58 compatible = "regulator-fixed";
58 regulator-name = "spkvdd-supply"; 59 regulator-name = "spkvdd-supply";
59 regulator-min-microvolt = <5000000>; 60 regulator-min-microvolt = <5000000>;
@@ -64,6 +65,7 @@
64 i2c@12C70000 { 65 i2c@12C70000 {
65 samsung,i2c-sda-delay = <100>; 66 samsung,i2c-sda-delay = <100>;
66 samsung,i2c-max-bus-freq = <20000>; 67 samsung,i2c-max-bus-freq = <20000>;
68 status = "okay";
67 69
68 eeprom@51 { 70 eeprom@51 {
69 compatible = "samsung,s524ad0xd1"; 71 compatible = "samsung,s524ad0xd1";
@@ -77,6 +79,9 @@
77 gpio-controller; 79 gpio-controller;
78 #gpio-cells = <2>; 80 #gpio-cells = <2>;
79 81
82 clocks = <&codec_mclk>;
83 clock-names = "MCLK1";
84
80 AVDD2-supply = <&vdd>; 85 AVDD2-supply = <&vdd>;
81 CPVDD-supply = <&vdd>; 86 CPVDD-supply = <&vdd>;
82 DBVDD-supply = <&dbvdd>; 87 DBVDD-supply = <&dbvdd>;
@@ -89,6 +94,7 @@
89 samsung,i2c-sda-delay = <100>; 94 samsung,i2c-sda-delay = <100>;
90 samsung,i2c-max-bus-freq = <40000>; 95 samsung,i2c-max-bus-freq = <40000>;
91 samsung,i2c-slave-addr = <0x38>; 96 samsung,i2c-slave-addr = <0x38>;
97 status = "okay";
92 98
93 sata-phy { 99 sata-phy {
94 compatible = "samsung,sata-phy"; 100 compatible = "samsung,sata-phy";
@@ -103,6 +109,7 @@
103 i2c@12C80000 { 109 i2c@12C80000 {
104 samsung,i2c-sda-delay = <100>; 110 samsung,i2c-sda-delay = <100>;
105 samsung,i2c-max-bus-freq = <66000>; 111 samsung,i2c-max-bus-freq = <66000>;
112 status = "okay";
106 113
107 hdmiddc@50 { 114 hdmiddc@50 {
108 compatible = "samsung,exynos4210-hdmiddc"; 115 compatible = "samsung,exynos4210-hdmiddc";
@@ -110,29 +117,10 @@
110 }; 117 };
111 }; 118 };
112 119
113 i2c@12C90000 {
114 status = "disabled";
115 };
116
117 i2c@12CA0000 {
118 status = "disabled";
119 };
120
121 i2c@12CB0000 {
122 status = "disabled";
123 };
124
125 i2c@12CC0000 {
126 status = "disabled";
127 };
128
129 i2c@12CD0000 {
130 status = "disabled";
131 };
132
133 i2c@12CE0000 { 120 i2c@12CE0000 {
134 samsung,i2c-sda-delay = <100>; 121 samsung,i2c-sda-delay = <100>;
135 samsung,i2c-max-bus-freq = <66000>; 122 samsung,i2c-max-bus-freq = <66000>;
123 status = "okay";
136 124
137 hdmiphy@38 { 125 hdmiphy@38 {
138 compatible = "samsung,exynos4212-hdmiphy"; 126 compatible = "samsung,exynos4212-hdmiphy";
@@ -140,11 +128,11 @@
140 }; 128 };
141 }; 129 };
142 130
143 dwmmc0@12200000 { 131 mmc@12200000 {
132 status = "okay";
144 num-slots = <1>; 133 num-slots = <1>;
145 supports-highspeed; 134 supports-highspeed;
146 broken-cd; 135 broken-cd;
147 fifo-depth = <0x80>;
148 card-detect-delay = <200>; 136 card-detect-delay = <200>;
149 samsung,dw-mshc-ciu-div = <3>; 137 samsung,dw-mshc-ciu-div = <3>;
150 samsung,dw-mshc-sdr-timing = <2 3>; 138 samsung,dw-mshc-sdr-timing = <2 3>;
@@ -158,14 +146,10 @@
158 }; 146 };
159 }; 147 };
160 148
161 dwmmc1@12210000 { 149 mmc@12220000 {
162 status = "disabled"; 150 status = "okay";
163 };
164
165 dwmmc2@12220000 {
166 num-slots = <1>; 151 num-slots = <1>;
167 supports-highspeed; 152 supports-highspeed;
168 fifo-depth = <0x80>;
169 card-detect-delay = <200>; 153 card-detect-delay = <200>;
170 samsung,dw-mshc-ciu-div = <3>; 154 samsung,dw-mshc-ciu-div = <3>;
171 samsung,dw-mshc-sdr-timing = <2 3>; 155 samsung,dw-mshc-sdr-timing = <2 3>;
@@ -180,15 +164,13 @@
180 }; 164 };
181 }; 165 };
182 166
183 dwmmc3@12230000 {
184 status = "disabled";
185 };
186
187 spi_0: spi@12d20000 { 167 spi_0: spi@12d20000 {
188 status = "disabled"; 168 status = "disabled";
189 }; 169 };
190 170
191 spi_1: spi@12d30000 { 171 spi_1: spi@12d30000 {
172 status = "okay";
173
192 w25q80bw@0 { 174 w25q80bw@0 {
193 #address-cells = <1>; 175 #address-cells = <1>;
194 #size-cells = <1>; 176 #size-cells = <1>;
@@ -214,10 +196,6 @@
214 }; 196 };
215 }; 197 };
216 198
217 spi_2: spi@12d40000 {
218 status = "disabled";
219 };
220
221 hdmi { 199 hdmi {
222 hpd-gpio = <&gpx3 7 0>; 200 hpd-gpio = <&gpx3 7 0>;
223 }; 201 };
@@ -279,5 +257,11 @@
279 compatible = "samsung,clock-xxti"; 257 compatible = "samsung,clock-xxti";
280 clock-frequency = <24000000>; 258 clock-frequency = <24000000>;
281 }; 259 };
260
261 codec_mclk: codec-mclk {
262 compatible = "fixed-clock";
263 #clock-cells = <0>;
264 clock-frequency = <16934000>;
265 };
282 }; 266 };
283}; 267};
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
index fd711e245e8d..7e45eea2d78f 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -10,7 +10,7 @@
10 10
11/dts-v1/; 11/dts-v1/;
12#include "exynos5250.dtsi" 12#include "exynos5250.dtsi"
13#include "cros5250-common.dtsi" 13#include "exynos5250-cros-common.dtsi"
14 14
15/ { 15/ {
16 model = "Google Snow"; 16 model = "Google Snow";
@@ -85,7 +85,7 @@
85 keypad,num-rows = <8>; 85 keypad,num-rows = <8>;
86 keypad,num-columns = <13>; 86 keypad,num-columns = <13>;
87 google,needs-ghost-filter; 87 google,needs-ghost-filter;
88 linux,keymap = <0x0001003a /* CAPSLK */ 88 linux,keymap = <0x0001007d /* L_META */
89 0x0002003b /* F1 */ 89 0x0002003b /* F1 */
90 0x00030030 /* B */ 90 0x00030030 /* B */
91 0x00040044 /* F10 */ 91 0x00040044 /* F10 */
@@ -130,6 +130,7 @@
130 0x04060024 /* J */ 130 0x04060024 /* J */
131 0x04080027 /* ; */ 131 0x04080027 /* ; */
132 0x04090026 /* L */ 132 0x04090026 /* L */
133 0x040a002b /* \ */
133 0x040b001c /* ENTER */ 134 0x040b001c /* ENTER */
134 135
135 0x0501002c /* Z */ 136 0x0501002c /* Z */
@@ -171,11 +172,20 @@
171 }; 172 };
172 }; 173 };
173 174
175 mmc@12200000 {
176 status = "okay";
177 };
178
179 mmc@12220000 {
180 status = "okay";
181 };
182
174 /* 183 /*
175 * On Snow we've got SIP WiFi and so can keep drive strengths low to 184 * On Snow we've got SIP WiFi and so can keep drive strengths low to
176 * reduce EMI. 185 * reduce EMI.
177 */ 186 */
178 dwmmc3@12230000 { 187 mmc@12230000 {
188 status = "okay";
179 slot@0 { 189 slot@0 {
180 pinctrl-names = "default"; 190 pinctrl-names = "default";
181 pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4>; 191 pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4>;
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 9db5047812f3..c341e55205cd 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -33,10 +33,10 @@
33 gsc1 = &gsc_1; 33 gsc1 = &gsc_1;
34 gsc2 = &gsc_2; 34 gsc2 = &gsc_2;
35 gsc3 = &gsc_3; 35 gsc3 = &gsc_3;
36 mshc0 = &dwmmc_0; 36 mshc0 = &mmc_0;
37 mshc1 = &dwmmc_1; 37 mshc1 = &mmc_1;
38 mshc2 = &dwmmc_2; 38 mshc2 = &mmc_2;
39 mshc3 = &dwmmc_3; 39 mshc3 = &mmc_3;
40 i2c0 = &i2c_0; 40 i2c0 = &i2c_0;
41 i2c1 = &i2c_1; 41 i2c1 = &i2c_1;
42 i2c2 = &i2c_2; 42 i2c2 = &i2c_2;
@@ -60,11 +60,13 @@
60 device_type = "cpu"; 60 device_type = "cpu";
61 compatible = "arm,cortex-a15"; 61 compatible = "arm,cortex-a15";
62 reg = <0>; 62 reg = <0>;
63 clock-frequency = <1700000000>;
63 }; 64 };
64 cpu@1 { 65 cpu@1 {
65 device_type = "cpu"; 66 device_type = "cpu";
66 compatible = "arm,cortex-a15"; 67 compatible = "arm,cortex-a15";
67 reg = <1>; 68 reg = <1>;
69 clock-frequency = <1700000000>;
68 }; 70 };
69 }; 71 };
70 72
@@ -242,6 +244,7 @@
242 clock-names = "i2c"; 244 clock-names = "i2c";
243 pinctrl-names = "default"; 245 pinctrl-names = "default";
244 pinctrl-0 = <&i2c0_bus>; 246 pinctrl-0 = <&i2c0_bus>;
247 status = "disabled";
245 }; 248 };
246 249
247 i2c_1: i2c@12C70000 { 250 i2c_1: i2c@12C70000 {
@@ -254,6 +257,7 @@
254 clock-names = "i2c"; 257 clock-names = "i2c";
255 pinctrl-names = "default"; 258 pinctrl-names = "default";
256 pinctrl-0 = <&i2c1_bus>; 259 pinctrl-0 = <&i2c1_bus>;
260 status = "disabled";
257 }; 261 };
258 262
259 i2c_2: i2c@12C80000 { 263 i2c_2: i2c@12C80000 {
@@ -266,6 +270,7 @@
266 clock-names = "i2c"; 270 clock-names = "i2c";
267 pinctrl-names = "default"; 271 pinctrl-names = "default";
268 pinctrl-0 = <&i2c2_bus>; 272 pinctrl-0 = <&i2c2_bus>;
273 status = "disabled";
269 }; 274 };
270 275
271 i2c_3: i2c@12C90000 { 276 i2c_3: i2c@12C90000 {
@@ -278,6 +283,7 @@
278 clock-names = "i2c"; 283 clock-names = "i2c";
279 pinctrl-names = "default"; 284 pinctrl-names = "default";
280 pinctrl-0 = <&i2c3_bus>; 285 pinctrl-0 = <&i2c3_bus>;
286 status = "disabled";
281 }; 287 };
282 288
283 i2c_4: i2c@12CA0000 { 289 i2c_4: i2c@12CA0000 {
@@ -290,6 +296,7 @@
290 clock-names = "i2c"; 296 clock-names = "i2c";
291 pinctrl-names = "default"; 297 pinctrl-names = "default";
292 pinctrl-0 = <&i2c4_bus>; 298 pinctrl-0 = <&i2c4_bus>;
299 status = "disabled";
293 }; 300 };
294 301
295 i2c_5: i2c@12CB0000 { 302 i2c_5: i2c@12CB0000 {
@@ -302,6 +309,7 @@
302 clock-names = "i2c"; 309 clock-names = "i2c";
303 pinctrl-names = "default"; 310 pinctrl-names = "default";
304 pinctrl-0 = <&i2c5_bus>; 311 pinctrl-0 = <&i2c5_bus>;
312 status = "disabled";
305 }; 313 };
306 314
307 i2c_6: i2c@12CC0000 { 315 i2c_6: i2c@12CC0000 {
@@ -314,6 +322,7 @@
314 clock-names = "i2c"; 322 clock-names = "i2c";
315 pinctrl-names = "default"; 323 pinctrl-names = "default";
316 pinctrl-0 = <&i2c6_bus>; 324 pinctrl-0 = <&i2c6_bus>;
325 status = "disabled";
317 }; 326 };
318 327
319 i2c_7: i2c@12CD0000 { 328 i2c_7: i2c@12CD0000 {
@@ -326,6 +335,7 @@
326 clock-names = "i2c"; 335 clock-names = "i2c";
327 pinctrl-names = "default"; 336 pinctrl-names = "default";
328 pinctrl-0 = <&i2c7_bus>; 337 pinctrl-0 = <&i2c7_bus>;
338 status = "disabled";
329 }; 339 };
330 340
331 i2c_8: i2c@12CE0000 { 341 i2c_8: i2c@12CE0000 {
@@ -336,6 +346,7 @@
336 #size-cells = <0>; 346 #size-cells = <0>;
337 clocks = <&clock 302>; 347 clocks = <&clock 302>;
338 clock-names = "i2c"; 348 clock-names = "i2c";
349 status = "disabled";
339 }; 350 };
340 351
341 i2c@121D0000 { 352 i2c@121D0000 {
@@ -345,10 +356,12 @@
345 #size-cells = <0>; 356 #size-cells = <0>;
346 clocks = <&clock 288>; 357 clocks = <&clock 288>;
347 clock-names = "i2c"; 358 clock-names = "i2c";
359 status = "disabled";
348 }; 360 };
349 361
350 spi_0: spi@12d20000 { 362 spi_0: spi@12d20000 {
351 compatible = "samsung,exynos4210-spi"; 363 compatible = "samsung,exynos4210-spi";
364 status = "disabled";
352 reg = <0x12d20000 0x100>; 365 reg = <0x12d20000 0x100>;
353 interrupts = <0 66 0>; 366 interrupts = <0 66 0>;
354 dmas = <&pdma0 5 367 dmas = <&pdma0 5
@@ -364,6 +377,7 @@
364 377
365 spi_1: spi@12d30000 { 378 spi_1: spi@12d30000 {
366 compatible = "samsung,exynos4210-spi"; 379 compatible = "samsung,exynos4210-spi";
380 status = "disabled";
367 reg = <0x12d30000 0x100>; 381 reg = <0x12d30000 0x100>;
368 interrupts = <0 67 0>; 382 interrupts = <0 67 0>;
369 dmas = <&pdma1 5 383 dmas = <&pdma1 5
@@ -379,6 +393,7 @@
379 393
380 spi_2: spi@12d40000 { 394 spi_2: spi@12d40000 {
381 compatible = "samsung,exynos4210-spi"; 395 compatible = "samsung,exynos4210-spi";
396 status = "disabled";
382 reg = <0x12d40000 0x100>; 397 reg = <0x12d40000 0x100>;
383 interrupts = <0 68 0>; 398 interrupts = <0 68 0>;
384 dmas = <&pdma0 7 399 dmas = <&pdma0 7
@@ -392,25 +407,43 @@
392 pinctrl-0 = <&spi2_bus>; 407 pinctrl-0 = <&spi2_bus>;
393 }; 408 };
394 409
395 dwmmc_0: dwmmc0@12200000 { 410 mmc_0: mmc@12200000 {
411 compatible = "samsung,exynos5250-dw-mshc";
412 interrupts = <0 75 0>;
413 #address-cells = <1>;
414 #size-cells = <0>;
396 reg = <0x12200000 0x1000>; 415 reg = <0x12200000 0x1000>;
397 clocks = <&clock 280>, <&clock 139>; 416 clocks = <&clock 280>, <&clock 139>;
398 clock-names = "biu", "ciu"; 417 clock-names = "biu", "ciu";
418 fifo-depth = <0x80>;
419 status = "disabled";
399 }; 420 };
400 421
401 dwmmc_1: dwmmc1@12210000 { 422 mmc_1: mmc@12210000 {
423 compatible = "samsung,exynos5250-dw-mshc";
424 interrupts = <0 76 0>;
425 #address-cells = <1>;
426 #size-cells = <0>;
402 reg = <0x12210000 0x1000>; 427 reg = <0x12210000 0x1000>;
403 clocks = <&clock 281>, <&clock 140>; 428 clocks = <&clock 281>, <&clock 140>;
404 clock-names = "biu", "ciu"; 429 clock-names = "biu", "ciu";
430 fifo-depth = <0x80>;
431 status = "disabled";
405 }; 432 };
406 433
407 dwmmc_2: dwmmc2@12220000 { 434 mmc_2: mmc@12220000 {
435 compatible = "samsung,exynos5250-dw-mshc";
436 interrupts = <0 77 0>;
437 #address-cells = <1>;
438 #size-cells = <0>;
408 reg = <0x12220000 0x1000>; 439 reg = <0x12220000 0x1000>;
409 clocks = <&clock 282>, <&clock 141>; 440 clocks = <&clock 282>, <&clock 141>;
410 clock-names = "biu", "ciu"; 441 clock-names = "biu", "ciu";
442 fifo-depth = <0x80>;
443 status = "disabled";
411 }; 444 };
412 445
413 dwmmc_3: dwmmc3@12230000 { 446 mmc_3: mmc@12230000 {
414 compatible = "samsung,exynos5250-dw-mshc"; 447 compatible = "samsung,exynos5250-dw-mshc";
415 reg = <0x12230000 0x1000>; 448 reg = <0x12230000 0x1000>;
416 interrupts = <0 78 0>; 449 interrupts = <0 78 0>;
@@ -418,6 +451,8 @@
418 #size-cells = <0>; 451 #size-cells = <0>;
419 clocks = <&clock 283>, <&clock 142>; 452 clocks = <&clock 283>, <&clock 142>;
420 clock-names = "biu", "ciu"; 453 clock-names = "biu", "ciu";
454 fifo-depth = <0x80>;
455 status = "disabled";
421 }; 456 };
422 457
423 i2s0: i2s@03830000 { 458 i2s0: i2s@03830000 {
@@ -526,6 +561,15 @@
526 }; 561 };
527 }; 562 };
528 563
564 pwm: pwm@12dd0000 {
565 compatible = "samsung,exynos4210-pwm";
566 reg = <0x12dd0000 0x100>;
567 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
568 #pwm-cells = <3>;
569 clocks = <&clock 311>;
570 clock-names = "timers";
571 };
572
529 amba { 573 amba {
530 #address-cells = <1>; 574 #address-cells = <1>;
531 #size-cells = <1>; 575 #size-cells = <1>;
diff --git a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
index e695aba5f73c..e62c8eb57438 100644
--- a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
@@ -64,7 +64,7 @@
64 samsung,pins = "gpx0-7"; 64 samsung,pins = "gpx0-7";
65 samsung,pin-function = <3>; 65 samsung,pin-function = <3>;
66 samsung,pin-pud = <0>; 66 samsung,pin-pud = <0>;
67 samaung,pin-drv = <0>; 67 samsung,pin-drv = <0>;
68 }; 68 };
69 }; 69 };
70 70
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index 79524c74c603..fb5a1e25c632 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -31,6 +31,39 @@
31 }; 31 };
32 }; 32 };
33 33
34 mmc@12200000 {
35 status = "okay";
36 broken-cd;
37 supports-highspeed;
38 card-detect-delay = <200>;
39 samsung,dw-mshc-ciu-div = <3>;
40 samsung,dw-mshc-sdr-timing = <0 4>;
41 samsung,dw-mshc-ddr-timing = <0 2>;
42 pinctrl-names = "default";
43 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
44
45 slot@0 {
46 reg = <0>;
47 bus-width = <8>;
48 };
49 };
50
51 mmc@12220000 {
52 status = "okay";
53 supports-highspeed;
54 card-detect-delay = <200>;
55 samsung,dw-mshc-ciu-div = <3>;
56 samsung,dw-mshc-sdr-timing = <2 3>;
57 samsung,dw-mshc-ddr-timing = <1 2>;
58 pinctrl-names = "default";
59 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
60
61 slot@0 {
62 reg = <0>;
63 bus-width = <4>;
64 };
65 };
66
34 dp-controller@145B0000 { 67 dp-controller@145B0000 {
35 pinctrl-names = "default"; 68 pinctrl-names = "default";
36 pinctrl-0 = <&dp_hpd>; 69 pinctrl-0 = <&dp_hpd>;
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 09aa06cb3d3a..11dd202c54bb 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -22,6 +22,9 @@
22 compatible = "samsung,exynos5420"; 22 compatible = "samsung,exynos5420";
23 23
24 aliases { 24 aliases {
25 mshc0 = &mmc_0;
26 mshc1 = &mmc_1;
27 mshc2 = &mmc_2;
25 pinctrl0 = &pinctrl_0; 28 pinctrl0 = &pinctrl_0;
26 pinctrl1 = &pinctrl_1; 29 pinctrl1 = &pinctrl_1;
27 pinctrl2 = &pinctrl_2; 30 pinctrl2 = &pinctrl_2;
@@ -31,6 +34,18 @@
31 i2c1 = &i2c_1; 34 i2c1 = &i2c_1;
32 i2c2 = &i2c_2; 35 i2c2 = &i2c_2;
33 i2c3 = &i2c_3; 36 i2c3 = &i2c_3;
37 i2c4 = &hsi2c_4;
38 i2c5 = &hsi2c_5;
39 i2c6 = &hsi2c_6;
40 i2c7 = &hsi2c_7;
41 i2c8 = &hsi2c_8;
42 i2c9 = &hsi2c_9;
43 i2c10 = &hsi2c_10;
44 gsc0 = &gsc_0;
45 gsc1 = &gsc_1;
46 spi0 = &spi_0;
47 spi1 = &spi_1;
48 spi2 = &spi_2;
34 }; 49 };
35 50
36 cpus { 51 cpus {
@@ -64,6 +79,34 @@
64 reg = <0x3>; 79 reg = <0x3>;
65 clock-frequency = <1800000000>; 80 clock-frequency = <1800000000>;
66 }; 81 };
82
83 cpu4: cpu@100 {
84 device_type = "cpu";
85 compatible = "arm,cortex-a7";
86 reg = <0x100>;
87 clock-frequency = <1000000000>;
88 };
89
90 cpu5: cpu@101 {
91 device_type = "cpu";
92 compatible = "arm,cortex-a7";
93 reg = <0x101>;
94 clock-frequency = <1000000000>;
95 };
96
97 cpu6: cpu@102 {
98 device_type = "cpu";
99 compatible = "arm,cortex-a7";
100 reg = <0x102>;
101 clock-frequency = <1000000000>;
102 };
103
104 cpu7: cpu@103 {
105 device_type = "cpu";
106 compatible = "arm,cortex-a7";
107 reg = <0x103>;
108 clock-frequency = <1000000000>;
109 };
67 }; 110 };
68 111
69 clock: clock-controller@10010000 { 112 clock: clock-controller@10010000 {
@@ -88,13 +131,50 @@
88 clock-names = "mfc"; 131 clock-names = "mfc";
89 }; 132 };
90 133
134 mmc_0: mmc@12200000 {
135 compatible = "samsung,exynos5420-dw-mshc-smu";
136 interrupts = <0 75 0>;
137 #address-cells = <1>;
138 #size-cells = <0>;
139 reg = <0x12200000 0x2000>;
140 clocks = <&clock 351>, <&clock 132>;
141 clock-names = "biu", "ciu";
142 fifo-depth = <0x40>;
143 status = "disabled";
144 };
145
146 mmc_1: mmc@12210000 {
147 compatible = "samsung,exynos5420-dw-mshc-smu";
148 interrupts = <0 76 0>;
149 #address-cells = <1>;
150 #size-cells = <0>;
151 reg = <0x12210000 0x2000>;
152 clocks = <&clock 352>, <&clock 133>;
153 clock-names = "biu", "ciu";
154 fifo-depth = <0x40>;
155 status = "disabled";
156 };
157
158 mmc_2: mmc@12220000 {
159 compatible = "samsung,exynos5420-dw-mshc";
160 interrupts = <0 77 0>;
161 #address-cells = <1>;
162 #size-cells = <0>;
163 reg = <0x12220000 0x1000>;
164 clocks = <&clock 353>, <&clock 134>;
165 clock-names = "biu", "ciu";
166 fifo-depth = <0x40>;
167 status = "disabled";
168 };
169
91 mct@101C0000 { 170 mct@101C0000 {
92 compatible = "samsung,exynos4210-mct"; 171 compatible = "samsung,exynos4210-mct";
93 reg = <0x101C0000 0x800>; 172 reg = <0x101C0000 0x800>;
94 interrupt-controller; 173 interrupt-controller;
95 #interrups-cells = <1>; 174 #interrups-cells = <1>;
96 interrupt-parent = <&mct_map>; 175 interrupt-parent = <&mct_map>;
97 interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>; 176 interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
177 <8>, <9>, <10>, <11>;
98 clocks = <&clock 1>, <&clock 315>; 178 clocks = <&clock 1>, <&clock 315>;
99 clock-names = "fin_pll", "mct"; 179 clock-names = "fin_pll", "mct";
100 180
@@ -109,7 +189,11 @@
109 <4 &gic 0 120 0>, 189 <4 &gic 0 120 0>,
110 <5 &gic 0 121 0>, 190 <5 &gic 0 121 0>,
111 <6 &gic 0 122 0>, 191 <6 &gic 0 122 0>,
112 <7 &gic 0 123 0>; 192 <7 &gic 0 123 0>,
193 <8 &gic 0 128 0>,
194 <9 &gic 0 129 0>,
195 <10 &gic 0 130 0>,
196 <11 &gic 0 131 0>;
113 }; 197 };
114 }; 198 };
115 199
@@ -190,6 +274,106 @@
190 status = "okay"; 274 status = "okay";
191 }; 275 };
192 276
277 amba {
278 #address-cells = <1>;
279 #size-cells = <1>;
280 compatible = "arm,amba-bus";
281 interrupt-parent = <&gic>;
282 ranges;
283
284 pdma0: pdma@121A0000 {
285 compatible = "arm,pl330", "arm,primecell";
286 reg = <0x121A0000 0x1000>;
287 interrupts = <0 34 0>;
288 clocks = <&clock 362>;
289 clock-names = "apb_pclk";
290 #dma-cells = <1>;
291 #dma-channels = <8>;
292 #dma-requests = <32>;
293 };
294
295 pdma1: pdma@121B0000 {
296 compatible = "arm,pl330", "arm,primecell";
297 reg = <0x121B0000 0x1000>;
298 interrupts = <0 35 0>;
299 clocks = <&clock 363>;
300 clock-names = "apb_pclk";
301 #dma-cells = <1>;
302 #dma-channels = <8>;
303 #dma-requests = <32>;
304 };
305
306 mdma0: mdma@10800000 {
307 compatible = "arm,pl330", "arm,primecell";
308 reg = <0x10800000 0x1000>;
309 interrupts = <0 33 0>;
310 clocks = <&clock 473>;
311 clock-names = "apb_pclk";
312 #dma-cells = <1>;
313 #dma-channels = <8>;
314 #dma-requests = <1>;
315 };
316
317 mdma1: mdma@11C10000 {
318 compatible = "arm,pl330", "arm,primecell";
319 reg = <0x11C10000 0x1000>;
320 interrupts = <0 124 0>;
321 clocks = <&clock 442>;
322 clock-names = "apb_pclk";
323 #dma-cells = <1>;
324 #dma-channels = <8>;
325 #dma-requests = <1>;
326 };
327 };
328
329 spi_0: spi@12d20000 {
330 compatible = "samsung,exynos4210-spi";
331 reg = <0x12d20000 0x100>;
332 interrupts = <0 66 0>;
333 dmas = <&pdma0 5
334 &pdma0 4>;
335 dma-names = "tx", "rx";
336 #address-cells = <1>;
337 #size-cells = <0>;
338 pinctrl-names = "default";
339 pinctrl-0 = <&spi0_bus>;
340 clocks = <&clock 271>, <&clock 135>;
341 clock-names = "spi", "spi_busclk0";
342 status = "disabled";
343 };
344
345 spi_1: spi@12d30000 {
346 compatible = "samsung,exynos4210-spi";
347 reg = <0x12d30000 0x100>;
348 interrupts = <0 67 0>;
349 dmas = <&pdma1 5
350 &pdma1 4>;
351 dma-names = "tx", "rx";
352 #address-cells = <1>;
353 #size-cells = <0>;
354 pinctrl-names = "default";
355 pinctrl-0 = <&spi1_bus>;
356 clocks = <&clock 272>, <&clock 136>;
357 clock-names = "spi", "spi_busclk0";
358 status = "disabled";
359 };
360
361 spi_2: spi@12d40000 {
362 compatible = "samsung,exynos4210-spi";
363 reg = <0x12d40000 0x100>;
364 interrupts = <0 68 0>;
365 dmas = <&pdma0 7
366 &pdma0 6>;
367 dma-names = "tx", "rx";
368 #address-cells = <1>;
369 #size-cells = <0>;
370 pinctrl-names = "default";
371 pinctrl-0 = <&spi2_bus>;
372 clocks = <&clock 273>, <&clock 137>;
373 clock-names = "spi", "spi_busclk0";
374 status = "disabled";
375 };
376
193 serial@12C00000 { 377 serial@12C00000 {
194 clocks = <&clock 257>, <&clock 128>; 378 clocks = <&clock 257>, <&clock 128>;
195 clock-names = "uart", "clk_uart_baud0"; 379 clock-names = "uart", "clk_uart_baud0";
@@ -210,6 +394,15 @@
210 clock-names = "uart", "clk_uart_baud0"; 394 clock-names = "uart", "clk_uart_baud0";
211 }; 395 };
212 396
397 pwm: pwm@12dd0000 {
398 compatible = "samsung,exynos4210-pwm";
399 reg = <0x12dd0000 0x100>;
400 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
401 #pwm-cells = <3>;
402 clocks = <&clock 279>;
403 clock-names = "timers";
404 };
405
213 dp_phy: video-phy@10040728 { 406 dp_phy: video-phy@10040728 {
214 compatible = "samsung,exynos5250-dp-video-phy"; 407 compatible = "samsung,exynos5250-dp-video-phy";
215 reg = <0x10040728 4>; 408 reg = <0x10040728 4>;
@@ -292,6 +485,97 @@
292 status = "disabled"; 485 status = "disabled";
293 }; 486 };
294 487
488 hsi2c_4: i2c@12CA0000 {
489 compatible = "samsung,exynos5-hsi2c";
490 reg = <0x12CA0000 0x1000>;
491 interrupts = <0 60 0>;
492 #address-cells = <1>;
493 #size-cells = <0>;
494 pinctrl-names = "default";
495 pinctrl-0 = <&i2c4_hs_bus>;
496 clocks = <&clock 265>;
497 clock-names = "hsi2c";
498 status = "disabled";
499 };
500
501 hsi2c_5: i2c@12CB0000 {
502 compatible = "samsung,exynos5-hsi2c";
503 reg = <0x12CB0000 0x1000>;
504 interrupts = <0 61 0>;
505 #address-cells = <1>;
506 #size-cells = <0>;
507 pinctrl-names = "default";
508 pinctrl-0 = <&i2c5_hs_bus>;
509 clocks = <&clock 266>;
510 clock-names = "hsi2c";
511 status = "disabled";
512 };
513
514 hsi2c_6: i2c@12CC0000 {
515 compatible = "samsung,exynos5-hsi2c";
516 reg = <0x12CC0000 0x1000>;
517 interrupts = <0 62 0>;
518 #address-cells = <1>;
519 #size-cells = <0>;
520 pinctrl-names = "default";
521 pinctrl-0 = <&i2c6_hs_bus>;
522 clocks = <&clock 267>;
523 clock-names = "hsi2c";
524 status = "disabled";
525 };
526
527 hsi2c_7: i2c@12CD0000 {
528 compatible = "samsung,exynos5-hsi2c";
529 reg = <0x12CD0000 0x1000>;
530 interrupts = <0 63 0>;
531 #address-cells = <1>;
532 #size-cells = <0>;
533 pinctrl-names = "default";
534 pinctrl-0 = <&i2c7_hs_bus>;
535 clocks = <&clock 268>;
536 clock-names = "hsi2c";
537 status = "disabled";
538 };
539
540 hsi2c_8: i2c@12E00000 {
541 compatible = "samsung,exynos5-hsi2c";
542 reg = <0x12E00000 0x1000>;
543 interrupts = <0 87 0>;
544 #address-cells = <1>;
545 #size-cells = <0>;
546 pinctrl-names = "default";
547 pinctrl-0 = <&i2c8_hs_bus>;
548 clocks = <&clock 281>;
549 clock-names = "hsi2c";
550 status = "disabled";
551 };
552
553 hsi2c_9: i2c@12E10000 {
554 compatible = "samsung,exynos5-hsi2c";
555 reg = <0x12E10000 0x1000>;
556 interrupts = <0 88 0>;
557 #address-cells = <1>;
558 #size-cells = <0>;
559 pinctrl-names = "default";
560 pinctrl-0 = <&i2c9_hs_bus>;
561 clocks = <&clock 282>;
562 clock-names = "hsi2c";
563 status = "disabled";
564 };
565
566 hsi2c_10: i2c@12E20000 {
567 compatible = "samsung,exynos5-hsi2c";
568 reg = <0x12E20000 0x1000>;
569 interrupts = <0 203 0>;
570 #address-cells = <1>;
571 #size-cells = <0>;
572 pinctrl-names = "default";
573 pinctrl-0 = <&i2c10_hs_bus>;
574 clocks = <&clock 283>;
575 clock-names = "hsi2c";
576 status = "disabled";
577 };
578
295 hdmi@14530000 { 579 hdmi@14530000 {
296 compatible = "samsung,exynos4212-hdmi"; 580 compatible = "samsung,exynos4212-hdmi";
297 reg = <0x14530000 0x70000>; 581 reg = <0x14530000 0x70000>;
@@ -310,4 +594,62 @@
310 clocks = <&clock 431>, <&clock 143>; 594 clocks = <&clock 431>, <&clock 143>;
311 clock-names = "mixer", "sclk_hdmi"; 595 clock-names = "mixer", "sclk_hdmi";
312 }; 596 };
597
598 gsc_0: video-scaler@13e00000 {
599 compatible = "samsung,exynos5-gsc";
600 reg = <0x13e00000 0x1000>;
601 interrupts = <0 85 0>;
602 clocks = <&clock 465>;
603 clock-names = "gscl";
604 samsung,power-domain = <&gsc_pd>;
605 };
606
607 gsc_1: video-scaler@13e10000 {
608 compatible = "samsung,exynos5-gsc";
609 reg = <0x13e10000 0x1000>;
610 interrupts = <0 86 0>;
611 clocks = <&clock 466>;
612 clock-names = "gscl";
613 samsung,power-domain = <&gsc_pd>;
614 };
615
616 tmu_cpu0: tmu@10060000 {
617 compatible = "samsung,exynos5420-tmu";
618 reg = <0x10060000 0x100>;
619 interrupts = <0 65 0>;
620 clocks = <&clock 318>;
621 clock-names = "tmu_apbif";
622 };
623
624 tmu_cpu1: tmu@10064000 {
625 compatible = "samsung,exynos5420-tmu";
626 reg = <0x10064000 0x100>;
627 interrupts = <0 183 0>;
628 clocks = <&clock 318>;
629 clock-names = "tmu_apbif";
630 };
631
632 tmu_cpu2: tmu@10068000 {
633 compatible = "samsung,exynos5420-tmu-ext-triminfo";
634 reg = <0x10068000 0x100>, <0x1006c000 0x4>;
635 interrupts = <0 184 0>;
636 clocks = <&clock 318>, <&clock 318>;
637 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
638 };
639
640 tmu_cpu3: tmu@1006c000 {
641 compatible = "samsung,exynos5420-tmu-ext-triminfo";
642 reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
643 interrupts = <0 185 0>;
644 clocks = <&clock 318>, <&clock 319>;
645 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
646 };
647
648 tmu_gpu: tmu@100a0000 {
649 compatible = "samsung,exynos5420-tmu-ext-triminfo";
650 reg = <0x100a0000 0x100>, <0x10068000 0x4>;
651 interrupts = <0 215 0>;
652 clocks = <&clock 319>, <&clock 318>;
653 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
654 };
313}; 655};
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
index 8da107088ce4..02a0a1226cef 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -29,7 +29,7 @@
29 #clock-cells = <1>; 29 #clock-cells = <1>;
30 }; 30 };
31 31
32 gic:interrupt-controller@2E0000 { 32 gic: interrupt-controller@2E0000 {
33 compatible = "arm,cortex-a15-gic"; 33 compatible = "arm,cortex-a15-gic";
34 #interrupt-cells = <3>; 34 #interrupt-cells = <3>;
35 interrupt-controller; 35 interrupt-controller;
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 59154dc15fe4..fb28b2ecb1db 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -161,7 +161,7 @@
161 clocks = <&clks 197>, <&clks 3>, 161 clocks = <&clks 197>, <&clks 3>,
162 <&clks 197>, <&clks 107>, 162 <&clks 197>, <&clks 107>,
163 <&clks 0>, <&clks 118>, 163 <&clks 0>, <&clks 118>,
164 <&clks 62>, <&clks 139>, 164 <&clks 0>, <&clks 139>,
165 <&clks 0>; 165 <&clks 0>;
166 clock-names = "core", "rxtx0", 166 clock-names = "core", "rxtx0",
167 "rxtx1", "rxtx2", 167 "rxtx1", "rxtx2",
diff --git a/arch/arm/boot/dts/integrator.dtsi b/arch/arm/boot/dts/integrator.dtsi
index 0f06f8687b0b..88e3d477bf16 100644
--- a/arch/arm/boot/dts/integrator.dtsi
+++ b/arch/arm/boot/dts/integrator.dtsi
@@ -10,6 +10,11 @@
10 reg = <0x10000000 0x200>; 10 reg = <0x10000000 0x200>;
11 }; 11 };
12 12
13 ebi@12000000 {
14 compatible = "arm,external-bus-interface";
15 reg = <0x12000000 0x100>;
16 };
17
13 timer@13000000 { 18 timer@13000000 {
14 reg = <0x13000000 0x100>; 19 reg = <0x13000000 0x100>;
15 interrupt-parent = <&pic>; 20 interrupt-parent = <&pic>;
diff --git a/arch/arm/boot/dts/k2hk-evm.dts b/arch/arm/boot/dts/k2hk-evm.dts
new file mode 100644
index 000000000000..eaefdfef65c3
--- /dev/null
+++ b/arch/arm/boot/dts/k2hk-evm.dts
@@ -0,0 +1,63 @@
1/*
2 * Copyright 2013 Texas Instruments, Inc.
3 *
4 * Keystone 2 Kepler/Hawking EVM device tree
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10/dts-v1/;
11
12#include "keystone.dtsi"
13
14/ {
15 compatible = "ti,keystone-evm";
16
17 soc {
18 clock {
19 refclksys: refclksys {
20 #clock-cells = <0>;
21 compatible = "fixed-clock";
22 clock-frequency = <122880000>;
23 clock-output-names = "refclk-sys";
24 };
25
26 refclkpass: refclkpass {
27 #clock-cells = <0>;
28 compatible = "fixed-clock";
29 clock-frequency = <122880000>;
30 clock-output-names = "refclk-pass";
31 };
32
33 refclkarm: refclkarm {
34 #clock-cells = <0>;
35 compatible = "fixed-clock";
36 clock-frequency = <125000000>;
37 clock-output-names = "refclk-arm";
38 };
39
40 refclkddr3a: refclkddr3a {
41 #clock-cells = <0>;
42 compatible = "fixed-clock";
43 clock-frequency = <100000000>;
44 clock-output-names = "refclk-ddr3a";
45 };
46
47 refclkddr3b: refclkddr3b {
48 #clock-cells = <0>;
49 compatible = "fixed-clock";
50 clock-frequency = <100000000>;
51 clock-output-names = "refclk-ddr3b";
52 };
53 };
54 };
55};
56
57&usb_phy {
58 status = "okay";
59};
60
61&usb {
62 status = "okay";
63};
diff --git a/arch/arm/boot/dts/keystone-clocks.dtsi b/arch/arm/boot/dts/keystone-clocks.dtsi
index d6713b113258..2363593e1050 100644
--- a/arch/arm/boot/dts/keystone-clocks.dtsi
+++ b/arch/arm/boot/dts/keystone-clocks.dtsi
@@ -13,17 +13,10 @@ clocks {
13 #size-cells = <1>; 13 #size-cells = <1>;
14 ranges; 14 ranges;
15 15
16 refclkmain: refclkmain {
17 #clock-cells = <0>;
18 compatible = "fixed-clock";
19 clock-frequency = <122880000>;
20 clock-output-names = "refclk-main";
21 };
22
23 mainpllclk: mainpllclk@2310110 { 16 mainpllclk: mainpllclk@2310110 {
24 #clock-cells = <0>; 17 #clock-cells = <0>;
25 compatible = "ti,keystone,main-pll-clock"; 18 compatible = "ti,keystone,main-pll-clock";
26 clocks = <&refclkmain>; 19 clocks = <&refclksys>;
27 reg = <0x02620350 4>, <0x02310110 4>; 20 reg = <0x02620350 4>, <0x02310110 4>;
28 reg-names = "control", "multiplier"; 21 reg-names = "control", "multiplier";
29 fixed-postdiv = <2>; 22 fixed-postdiv = <2>;
@@ -32,47 +25,43 @@ clocks {
32 papllclk: papllclk@2620358 { 25 papllclk: papllclk@2620358 {
33 #clock-cells = <0>; 26 #clock-cells = <0>;
34 compatible = "ti,keystone,pll-clock"; 27 compatible = "ti,keystone,pll-clock";
35 clocks = <&refclkmain>; 28 clocks = <&refclkpass>;
36 clock-output-names = "pa-pll-clk"; 29 clock-output-names = "pa-pll-clk";
37 reg = <0x02620358 4>; 30 reg = <0x02620358 4>;
38 reg-names = "control"; 31 reg-names = "control";
39 fixed-postdiv = <6>;
40 }; 32 };
41 33
42 ddr3allclk: ddr3apllclk@2620360 { 34 ddr3apllclk: ddr3apllclk@2620360 {
43 #clock-cells = <0>; 35 #clock-cells = <0>;
44 compatible = "ti,keystone,pll-clock"; 36 compatible = "ti,keystone,pll-clock";
45 clocks = <&refclkmain>; 37 clocks = <&refclkddr3a>;
46 clock-output-names = "ddr-3a-pll-clk"; 38 clock-output-names = "ddr-3a-pll-clk";
47 reg = <0x02620360 4>; 39 reg = <0x02620360 4>;
48 reg-names = "control"; 40 reg-names = "control";
49 fixed-postdiv = <6>;
50 }; 41 };
51 42
52 ddr3bllclk: ddr3bpllclk@2620368 { 43 ddr3bpllclk: ddr3bpllclk@2620368 {
53 #clock-cells = <0>; 44 #clock-cells = <0>;
54 compatible = "ti,keystone,pll-clock"; 45 compatible = "ti,keystone,pll-clock";
55 clocks = <&refclkmain>; 46 clocks = <&refclkddr3b>;
56 clock-output-names = "ddr-3b-pll-clk"; 47 clock-output-names = "ddr-3b-pll-clk";
57 reg = <0x02620368 4>; 48 reg = <0x02620368 4>;
58 reg-names = "control"; 49 reg-names = "control";
59 fixed-postdiv = <6>;
60 }; 50 };
61 51
62 armpllclk: armpllclk@2620370 { 52 armpllclk: armpllclk@2620370 {
63 #clock-cells = <0>; 53 #clock-cells = <0>;
64 compatible = "ti,keystone,pll-clock"; 54 compatible = "ti,keystone,pll-clock";
65 clocks = <&refclkmain>; 55 clocks = <&refclkarm>;
66 clock-output-names = "arm-pll-clk"; 56 clock-output-names = "arm-pll-clk";
67 reg = <0x02620370 4>; 57 reg = <0x02620370 4>;
68 reg-names = "control"; 58 reg-names = "control";
69 fixed-postdiv = <6>;
70 }; 59 };
71 60
72 mainmuxclk: mainmuxclk@2310108 { 61 mainmuxclk: mainmuxclk@2310108 {
73 #clock-cells = <0>; 62 #clock-cells = <0>;
74 compatible = "ti,keystone,pll-mux-clock"; 63 compatible = "ti,keystone,pll-mux-clock";
75 clocks = <&mainpllclk>, <&refclkmain>; 64 clocks = <&mainpllclk>, <&refclksys>;
76 reg = <0x02310108 4>; 65 reg = <0x02310108 4>;
77 bit-shift = <23>; 66 bit-shift = <23>;
78 bit-mask = <1>; 67 bit-mask = <1>;
@@ -135,6 +124,15 @@ clocks {
135 clock-output-names = "chipclk13"; 124 clock-output-names = "chipclk13";
136 }; 125 };
137 126
127 paclk13: paclk13 {
128 #clock-cells = <0>;
129 compatible = "fixed-factor-clock";
130 clocks = <&papllclk>;
131 clock-div = <3>;
132 clock-mult = <1>;
133 clock-output-names = "paclk13";
134 };
135
138 chipclk14: chipclk14 { 136 chipclk14: chipclk14 {
139 #clock-cells = <0>; 137 #clock-cells = <0>;
140 compatible = "fixed-factor-clock"; 138 compatible = "fixed-factor-clock";
diff --git a/arch/arm/boot/dts/keystone.dts b/arch/arm/boot/dts/keystone.dtsi
index 100bdf52b847..b4202907a27b 100644
--- a/arch/arm/boot/dts/keystone.dts
+++ b/arch/arm/boot/dts/keystone.dtsi
@@ -6,14 +6,12 @@
6 * published by the Free Software Foundation. 6 * published by the Free Software Foundation.
7 */ 7 */
8 8
9/dts-v1/;
10#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h>
11 10
12#include "skeleton.dtsi" 11#include "skeleton.dtsi"
13 12
14/ { 13/ {
15 model = "Texas Instruments Keystone 2 SoC"; 14 model = "Texas Instruments Keystone 2 SoC";
16 compatible = "ti,keystone-evm";
17 #address-cells = <2>; 15 #address-cells = <2>;
18 #size-cells = <2>; 16 #size-cells = <2>;
19 interrupt-parent = <&gic>; 17 interrupt-parent = <&gic>;
@@ -64,7 +62,11 @@
64 #address-cells = <1>; 62 #address-cells = <1>;
65 interrupt-controller; 63 interrupt-controller;
66 reg = <0x0 0x02561000 0x0 0x1000>, 64 reg = <0x0 0x02561000 0x0 0x1000>,
67 <0x0 0x02562000 0x0 0x2000>; 65 <0x0 0x02562000 0x0 0x2000>,
66 <0x0 0x02564000 0x0 0x1000>,
67 <0x0 0x02566000 0x0 0x2000>;
68 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
69 IRQ_TYPE_LEVEL_HIGH)>;
68 }; 70 };
69 71
70 timer { 72 timer {
@@ -179,5 +181,32 @@
179 interrupts = <GIC_SPI 300 IRQ_TYPE_EDGE_RISING>; 181 interrupts = <GIC_SPI 300 IRQ_TYPE_EDGE_RISING>;
180 clocks = <&clkspi>; 182 clocks = <&clkspi>;
181 }; 183 };
184
185 usb_phy: usb_phy@2620738 {
186 compatible = "ti,keystone-usbphy";
187 #address-cells = <1>;
188 #size-cells = <1>;
189 reg = <0x2620738 32>;
190 status = "disabled";
191 };
192
193 usb: usb@2680000 {
194 compatible = "ti,keystone-dwc3";
195 #address-cells = <1>;
196 #size-cells = <1>;
197 reg = <0x2680000 0x10000>;
198 clocks = <&clkusb>;
199 clock-names = "usb";
200 interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
201 ranges;
202 status = "disabled";
203
204 dwc3@2690000 {
205 compatible = "synopsys,dwc3";
206 reg = <0x2690000 0x70000>;
207 interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
208 usb-phy = <&usb_phy>, <&usb_phy>;
209 };
210 };
182 }; 211 };
183}; 212};
diff --git a/arch/arm/boot/dts/moxart-uc7112lx.dts b/arch/arm/boot/dts/moxart-uc7112lx.dts
new file mode 100644
index 000000000000..90749d55de0d
--- /dev/null
+++ b/arch/arm/boot/dts/moxart-uc7112lx.dts
@@ -0,0 +1,109 @@
1/* moxart-uc7112lx.dts - Device Tree file for MOXA UC-7112-LX
2 *
3 * Copyright (C) 2013 Jonas Jensen <jonas.jensen@gmail.com>
4 *
5 * Licensed under GPLv2 or later.
6 */
7
8/dts-v1/;
9/include/ "moxart.dtsi"
10
11/ {
12 model = "MOXA UC-7112-LX";
13 compatible = "moxa,moxart-uc-7112-lx", "moxa,moxart";
14
15 memory {
16 device_type = "memory";
17 reg = <0x0 0x2000000>;
18 };
19
20 flash@80000000,0 {
21 compatible = "numonyx,js28f128", "cfi-flash";
22 reg = <0x80000000 0x1000000>;
23 bank-width = <2>;
24 #address-cells = <1>;
25 #size-cells = <1>;
26 partition@0 {
27 label = "bootloader";
28 reg = <0x0 0x40000>;
29 };
30 partition@40000 {
31 label = "linux kernel";
32 reg = <0x40000 0x1C0000>;
33 };
34 partition@200000 {
35 label = "root filesystem";
36 reg = <0x200000 0x800000>;
37 };
38 partition@a00000 {
39 label = "user filesystem";
40 reg = <0xa00000 0x600000>;
41 };
42 };
43
44 leds {
45 compatible = "gpio-leds";
46 user-led {
47 label = "ready-led";
48 gpios = <&gpio 27 0x1>;
49 default-state = "on";
50 linux,default-trigger = "default-on";
51 };
52 };
53
54 gpio_keys_polled {
55 compatible = "gpio-keys-polled";
56 #address-cells = <1>;
57 #size-cells = <0>;
58 poll-interval = <500>;
59 button@25 {
60 label = "GPIO Reset";
61 linux,code = <116>;
62 gpios = <&gpio 25 1>;
63 };
64 };
65
66 chosen {
67 bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/mmcblk0p1 rw rootwait";
68 };
69};
70
71&clk_pll {
72 clocks = <&ref12>;
73};
74
75&sdhci {
76 status = "okay";
77};
78
79&mdio0 {
80 status = "okay";
81
82 ethphy0: ethernet-phy@1 {
83 device_type = "ethernet-phy";
84 compatible = "moxa,moxart-rtl8201cp", "ethernet-phy-ieee802.3-c22";
85 reg = <1>;
86 };
87};
88
89&mdio1 {
90 status = "okay";
91
92 ethphy1: ethernet-phy@1 {
93 device_type = "ethernet-phy";
94 compatible = "moxa,moxart-rtl8201cp", "ethernet-phy-ieee802.3-c22";
95 reg = <1>;
96 };
97};
98
99&mac0 {
100 status = "okay";
101};
102
103&mac1 {
104 status = "okay";
105};
106
107&uart0 {
108 status = "okay";
109};
diff --git a/arch/arm/boot/dts/moxart.dtsi b/arch/arm/boot/dts/moxart.dtsi
new file mode 100644
index 000000000000..da1d8effef97
--- /dev/null
+++ b/arch/arm/boot/dts/moxart.dtsi
@@ -0,0 +1,154 @@
1/* moxart.dtsi - Device Tree Include file for MOXA ART family SoC
2 *
3 * Copyright (C) 2013 Jonas Jensen <jonas.jensen@gmail.com>
4 *
5 * Licensed under GPLv2 or later.
6 */
7
8/include/ "skeleton.dtsi"
9
10/ {
11 compatible = "moxa,moxart";
12 model = "MOXART";
13 interrupt-parent = <&intc>;
14
15 cpus {
16 #address-cells = <1>;
17 #size-cells = <0>;
18
19 cpu@0 {
20 device_type = "cpu";
21 compatible = "faraday,fa526";
22 reg = <0>;
23 };
24 };
25
26 clocks {
27 #address-cells = <1>;
28 #size-cells = <0>;
29
30 ref12: ref12M {
31 compatible = "fixed-clock";
32 #clock-cells = <0>;
33 clock-frequency = <12000000>;
34 };
35 };
36
37 soc {
38 compatible = "simple-bus";
39 #address-cells = <1>;
40 #size-cells = <1>;
41 reg = <0x90000000 0x10000000>;
42 ranges;
43
44 intc: interrupt-controller@98800000 {
45 compatible = "moxa,moxart-ic";
46 reg = <0x98800000 0x38>;
47 interrupt-controller;
48 #interrupt-cells = <2>;
49 interrupt-mask = <0x00080000>;
50 };
51
52 clk_pll: clk_pll@98100000 {
53 compatible = "moxa,moxart-pll-clock";
54 #clock-cells = <0>;
55 reg = <0x98100000 0x34>;
56 };
57
58 clk_apb: clk_apb@98100000 {
59 compatible = "moxa,moxart-apb-clock";
60 #clock-cells = <0>;
61 reg = <0x98100000 0x34>;
62 clocks = <&clk_pll>;
63 };
64
65 timer: timer@98400000 {
66 compatible = "moxa,moxart-timer";
67 reg = <0x98400000 0x42>;
68 interrupts = <19 1>;
69 clocks = <&clk_apb>;
70 };
71
72 gpio: gpio@98700000 {
73 gpio-controller;
74 #gpio-cells = <2>;
75 compatible = "moxa,moxart-gpio";
76 reg = <0x98700000 0xC>;
77 };
78
79 rtc: rtc {
80 compatible = "moxa,moxart-rtc";
81 gpio-rtc-sclk = <&gpio 5 0>;
82 gpio-rtc-data = <&gpio 6 0>;
83 gpio-rtc-reset = <&gpio 7 0>;
84 };
85
86 dma: dma@90500000 {
87 compatible = "moxa,moxart-dma";
88 reg = <0x90500080 0x40>;
89 interrupts = <24 0>;
90 #dma-cells = <1>;
91 };
92
93 watchdog: watchdog@98500000 {
94 compatible = "moxa,moxart-watchdog";
95 reg = <0x98500000 0x10>;
96 clocks = <&clk_apb>;
97 };
98
99 sdhci: sdhci@98e00000 {
100 compatible = "moxa,moxart-sdhci";
101 reg = <0x98e00000 0x5C>;
102 interrupts = <5 0>;
103 clocks = <&clk_apb>;
104 dmas = <&dma 5>,
105 <&dma 5>;
106 dma-names = "tx", "rx";
107 status = "disabled";
108 };
109
110 mdio0: mdio@90900090 {
111 compatible = "moxa,moxart-mdio";
112 reg = <0x90900090 0x8>;
113 #address-cells = <1>;
114 #size-cells = <0>;
115 status = "disabled";
116 };
117
118 mdio1: mdio@92000090 {
119 compatible = "moxa,moxart-mdio";
120 reg = <0x92000090 0x8>;
121 #address-cells = <1>;
122 #size-cells = <0>;
123 status = "disabled";
124 };
125
126 mac0: mac@90900000 {
127 compatible = "moxa,moxart-mac";
128 reg = <0x90900000 0x90>;
129 interrupts = <25 0>;
130 phy-handle = <&ethphy0>;
131 phy-mode = "mii";
132 status = "disabled";
133 };
134
135 mac1: mac@92000000 {
136 compatible = "moxa,moxart-mac";
137 reg = <0x92000000 0x90>;
138 interrupts = <27 0>;
139 phy-handle = <&ethphy1>;
140 phy-mode = "mii";
141 status = "disabled";
142 };
143
144 uart0: uart@98200000 {
145 compatible = "ns16550a";
146 reg = <0x98200000 0x20>;
147 interrupts = <31 8>;
148 reg-shift = <2>;
149 reg-io-width = <4>;
150 clock-frequency = <14745600>;
151 status = "disabled";
152 };
153 };
154};
diff --git a/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi b/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi
index 9c18adf788f7..f577b7df9a29 100644
--- a/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi
+++ b/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi
@@ -44,8 +44,8 @@
44 gpmc,wr-access-ns = <186>; 44 gpmc,wr-access-ns = <186>;
45 gpmc,cycle2cycle-samecsen; 45 gpmc,cycle2cycle-samecsen;
46 gpmc,cycle2cycle-diffcsen; 46 gpmc,cycle2cycle-diffcsen;
47 vmmc-supply = <&vddvario>; 47 vddvario-supply = <&vddvario>;
48 vmmc_aux-supply = <&vdd33a>; 48 vdd33a-supply = <&vdd33a>;
49 reg-io-width = <4>; 49 reg-io-width = <4>;
50 smsc,save-mac-address; 50 smsc,save-mac-address;
51 }; 51 };
diff --git a/arch/arm/boot/dts/omap-zoom-common.dtsi b/arch/arm/boot/dts/omap-zoom-common.dtsi
index b0ee342598f0..68221fab978d 100644
--- a/arch/arm/boot/dts/omap-zoom-common.dtsi
+++ b/arch/arm/boot/dts/omap-zoom-common.dtsi
@@ -13,7 +13,7 @@
13 * they probably share the same GPIO IRQ 13 * they probably share the same GPIO IRQ
14 * REVISIT: Add timing support from slls644g.pdf 14 * REVISIT: Add timing support from slls644g.pdf
15 */ 15 */
16 8250@3,0 { 16 uart@3,0 {
17 compatible = "ns16550a"; 17 compatible = "ns16550a";
18 reg = <3 0 0x100>; 18 reg = <3 0 0x100>;
19 bank-width = <2>; 19 bank-width = <2>;
diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi
index a2bfcde858a6..d0c5b37e248c 100644
--- a/arch/arm/boot/dts/omap2.dtsi
+++ b/arch/arm/boot/dts/omap2.dtsi
@@ -9,6 +9,7 @@
9 */ 9 */
10 10
11#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/interrupt-controller/irq.h>
12#include <dt-bindings/pinctrl/omap.h> 13#include <dt-bindings/pinctrl/omap.h>
13 14
14#include "skeleton.dtsi" 15#include "skeleton.dtsi"
@@ -21,6 +22,8 @@
21 serial0 = &uart1; 22 serial0 = &uart1;
22 serial1 = &uart2; 23 serial1 = &uart2;
23 serial2 = &uart3; 24 serial2 = &uart3;
25 i2c0 = &i2c1;
26 i2c1 = &i2c2;
24 }; 27 };
25 28
26 cpus { 29 cpus {
@@ -53,6 +56,28 @@
53 ranges; 56 ranges;
54 ti,hwmods = "l3_main"; 57 ti,hwmods = "l3_main";
55 58
59 aes: aes@480a6000 {
60 compatible = "ti,omap2-aes";
61 ti,hwmods = "aes";
62 reg = <0x480a6000 0x50>;
63 dmas = <&sdma 9 &sdma 10>;
64 dma-names = "tx", "rx";
65 };
66
67 hdq1w: 1w@480b2000 {
68 compatible = "ti,omap2420-1w";
69 ti,hwmods = "hdq1w";
70 reg = <0x480b2000 0x1000>;
71 interrupts = <58>;
72 };
73
74 mailbox: mailbox@48094000 {
75 compatible = "ti,omap2-mailbox";
76 ti,hwmods = "mailbox";
77 reg = <0x48094000 0x200>;
78 interrupts = <26>;
79 };
80
56 intc: interrupt-controller@1 { 81 intc: interrupt-controller@1 {
57 compatible = "ti,omap2-intc"; 82 compatible = "ti,omap2-intc";
58 interrupt-controller; 83 interrupt-controller;
@@ -63,6 +88,7 @@
63 88
64 sdma: dma-controller@48056000 { 89 sdma: dma-controller@48056000 {
65 compatible = "ti,omap2430-sdma", "ti,omap2420-sdma"; 90 compatible = "ti,omap2430-sdma", "ti,omap2420-sdma";
91 ti,hwmods = "dma";
66 reg = <0x48056000 0x1000>; 92 reg = <0x48056000 0x1000>;
67 interrupts = <12>, 93 interrupts = <12>,
68 <13>, 94 <13>,
@@ -73,21 +99,91 @@
73 #dma-requests = <64>; 99 #dma-requests = <64>;
74 }; 100 };
75 101
102 i2c1: i2c@48070000 {
103 compatible = "ti,omap2-i2c";
104 ti,hwmods = "i2c1";
105 reg = <0x48070000 0x80>;
106 #address-cells = <1>;
107 #size-cells = <0>;
108 interrupts = <56>;
109 dmas = <&sdma 27 &sdma 28>;
110 dma-names = "tx", "rx";
111 };
112
113 i2c2: i2c@48072000 {
114 compatible = "ti,omap2-i2c";
115 ti,hwmods = "i2c2";
116 reg = <0x48072000 0x80>;
117 #address-cells = <1>;
118 #size-cells = <0>;
119 interrupts = <57>;
120 dmas = <&sdma 29 &sdma 30>;
121 dma-names = "tx", "rx";
122 };
123
124 mcspi1: mcspi@48098000 {
125 compatible = "ti,omap2-mcspi";
126 ti,hwmods = "mcspi1";
127 reg = <0x48098000 0x100>;
128 interrupts = <65>;
129 dmas = <&sdma 35 &sdma 36 &sdma 37 &sdma 38
130 &sdma 39 &sdma 40 &sdma 41 &sdma 42>;
131 dma-names = "tx0", "rx0", "tx1", "rx1",
132 "tx2", "rx2", "tx3", "rx3";
133 };
134
135 mcspi2: mcspi@4809a000 {
136 compatible = "ti,omap2-mcspi";
137 ti,hwmods = "mcspi2";
138 reg = <0x4809a000 0x100>;
139 interrupts = <66>;
140 dmas = <&sdma 43 &sdma 44 &sdma 45 &sdma 46>;
141 dma-names = "tx0", "rx0", "tx1", "rx1";
142 };
143
144 rng: rng@480a0000 {
145 compatible = "ti,omap2-rng";
146 ti,hwmods = "rng";
147 reg = <0x480a0000 0x50>;
148 interrupts = <36>;
149 };
150
151 sham: sham@480a4000 {
152 compatible = "ti,omap2-sham";
153 ti,hwmods = "sham";
154 reg = <0x480a4000 0x64>;
155 interrupts = <51>;
156 dmas = <&sdma 13>;
157 dma-names = "rx";
158 };
159
76 uart1: serial@4806a000 { 160 uart1: serial@4806a000 {
77 compatible = "ti,omap2-uart"; 161 compatible = "ti,omap2-uart";
78 ti,hwmods = "uart1"; 162 ti,hwmods = "uart1";
163 reg = <0x4806a000 0x2000>;
164 interrupts = <72>;
165 dmas = <&sdma 49 &sdma 50>;
166 dma-names = "tx", "rx";
79 clock-frequency = <48000000>; 167 clock-frequency = <48000000>;
80 }; 168 };
81 169
82 uart2: serial@4806c000 { 170 uart2: serial@4806c000 {
83 compatible = "ti,omap2-uart"; 171 compatible = "ti,omap2-uart";
84 ti,hwmods = "uart2"; 172 ti,hwmods = "uart2";
173 reg = <0x4806c000 0x400>;
174 interrupts = <73>;
175 dmas = <&sdma 51 &sdma 52>;
176 dma-names = "tx", "rx";
85 clock-frequency = <48000000>; 177 clock-frequency = <48000000>;
86 }; 178 };
87 179
88 uart3: serial@4806e000 { 180 uart3: serial@4806e000 {
89 compatible = "ti,omap2-uart"; 181 compatible = "ti,omap2-uart";
90 ti,hwmods = "uart3"; 182 ti,hwmods = "uart3";
183 reg = <0x4806e000 0x400>;
184 interrupts = <74>;
185 dmas = <&sdma 53 &sdma 54>;
186 dma-names = "tx", "rx";
91 clock-frequency = <48000000>; 187 clock-frequency = <48000000>;
92 }; 188 };
93 189
diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi
index c8f9c55169ea..60c605de22dd 100644
--- a/arch/arm/boot/dts/omap2420.dtsi
+++ b/arch/arm/boot/dts/omap2420.dtsi
@@ -114,6 +114,15 @@
114 dma-names = "tx", "rx"; 114 dma-names = "tx", "rx";
115 }; 115 };
116 116
117 msdi1: mmc@4809c000 {
118 compatible = "ti,omap2420-mmc";
119 ti,hwmods = "msdi1";
120 reg = <0x4809c000 0x80>;
121 interrupts = <83>;
122 dmas = <&sdma 61 &sdma 62>;
123 dma-names = "tx", "rx";
124 };
125
117 timer1: timer@48028000 { 126 timer1: timer@48028000 {
118 compatible = "ti,omap2420-timer"; 127 compatible = "ti,omap2420-timer";
119 reg = <0x48028000 0x400>; 128 reg = <0x48028000 0x400>;
@@ -121,5 +130,19 @@
121 ti,hwmods = "timer1"; 130 ti,hwmods = "timer1";
122 ti,timer-alwon; 131 ti,timer-alwon;
123 }; 132 };
133
134 wd_timer2: wdt@48022000 {
135 compatible = "ti,omap2-wdt";
136 ti,hwmods = "wd_timer2";
137 reg = <0x48022000 0x80>;
138 };
124 }; 139 };
125}; 140};
141
142&i2c1 {
143 compatible = "ti,omap2420-i2c";
144};
145
146&i2c2 {
147 compatible = "ti,omap2420-i2c";
148};
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi
index c535a5a2b27f..d624345666f5 100644
--- a/arch/arm/boot/dts/omap2430.dtsi
+++ b/arch/arm/boot/dts/omap2430.dtsi
@@ -175,6 +175,25 @@
175 dma-names = "tx", "rx"; 175 dma-names = "tx", "rx";
176 }; 176 };
177 177
178 mmc1: mmc@4809c000 {
179 compatible = "ti,omap2-hsmmc";
180 reg = <0x4809c000 0x200>;
181 interrupts = <83>;
182 ti,hwmods = "mmc1";
183 ti,dual-volt;
184 dmas = <&sdma 61>, <&sdma 62>;
185 dma-names = "tx", "rx";
186 };
187
188 mmc2: mmc@480b4000 {
189 compatible = "ti,omap2-hsmmc";
190 reg = <0x480b4000 0x200>;
191 interrupts = <86>;
192 ti,hwmods = "mmc2";
193 dmas = <&sdma 47>, <&sdma 48>;
194 dma-names = "tx", "rx";
195 };
196
178 timer1: timer@49018000 { 197 timer1: timer@49018000 {
179 compatible = "ti,omap2420-timer"; 198 compatible = "ti,omap2420-timer";
180 reg = <0x49018000 0x400>; 199 reg = <0x49018000 0x400>;
@@ -182,5 +201,35 @@
182 ti,hwmods = "timer1"; 201 ti,hwmods = "timer1";
183 ti,timer-alwon; 202 ti,timer-alwon;
184 }; 203 };
204
205 mcspi3: mcspi@480b8000 {
206 compatible = "ti,omap2-mcspi";
207 ti,hwmods = "mcspi3";
208 reg = <0x480b8000 0x100>;
209 interrupts = <91>;
210 dmas = <&sdma 15 &sdma 16 &sdma 23 &sdma 24>;
211 dma-names = "tx0", "rx0", "tx1", "rx1";
212 };
213
214 usb_otg_hs: usb_otg_hs@480ac000 {
215 compatible = "ti,omap2-musb";
216 ti,hwmods = "usb_otg_hs";
217 reg = <0x480ac000 0x1000>;
218 interrupts = <93>;
219 };
220
221 wd_timer2: wdt@49016000 {
222 compatible = "ti,omap2-wdt";
223 ti,hwmods = "wd_timer2";
224 reg = <0x49016000 0x80>;
225 };
185 }; 226 };
186}; 227};
228
229&i2c1 {
230 compatible = "ti,omap2430-i2c";
231};
232
233&i2c2 {
234 compatible = "ti,omap2430-i2c";
235};
diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts
index 31a632f7effb..df33a50bc070 100644
--- a/arch/arm/boot/dts/omap3-beagle-xm.dts
+++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
@@ -215,3 +215,10 @@
215&usbhsehci { 215&usbhsehci {
216 phys = <0 &hsusb2_phy>; 216 phys = <0 &hsusb2_phy>;
217}; 217};
218
219&vaux2 {
220 regulator-name = "usb_1v8";
221 regulator-min-microvolt = <1800000>;
222 regulator-max-microvolt = <1800000>;
223 regulator-always-on;
224};
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index fa532aaacc68..3ba4a625ea5b 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -61,6 +61,14 @@
61 vcc-supply = <&hsusb2_power>; 61 vcc-supply = <&hsusb2_power>;
62 }; 62 };
63 63
64 sound {
65 compatible = "ti,omap-twl4030";
66 ti,model = "omap3beagle";
67
68 ti,mcbsp = <&mcbsp2>;
69 ti,codec = <&twl_audio>;
70 };
71
64 gpio_keys { 72 gpio_keys {
65 compatible = "gpio-keys"; 73 compatible = "gpio-keys";
66 74
@@ -120,6 +128,12 @@
120 reg = <0x48>; 128 reg = <0x48>;
121 interrupts = <7>; /* SYS_NIRQ cascaded to intc */ 129 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
122 interrupt-parent = <&intc>; 130 interrupt-parent = <&intc>;
131
132 twl_audio: audio {
133 compatible = "ti,twl4030-audio";
134 codec {
135 };
136 };
123 }; 137 };
124}; 138};
125 139
@@ -178,3 +192,10 @@
178 mode = <3>; 192 mode = <3>;
179 power = <50>; 193 power = <50>;
180}; 194};
195
196&vaux2 {
197 regulator-name = "vdd_ehci";
198 regulator-min-microvolt = <1800000>;
199 regulator-max-microvolt = <1800000>;
200 regulator-always-on;
201};
diff --git a/arch/arm/boot/dts/omap3-igep.dtsi b/arch/arm/boot/dts/omap3-igep.dtsi
index ba1e58b7b7e3..165aaf7591ba 100644
--- a/arch/arm/boot/dts/omap3-igep.dtsi
+++ b/arch/arm/boot/dts/omap3-igep.dtsi
@@ -1,5 +1,5 @@
1/* 1/*
2 * Device Tree Source for IGEP Technology devices 2 * Common device tree for IGEP boards based on AM/DM37x
3 * 3 *
4 * Copyright (C) 2012 Javier Martinez Canillas <javier@collabora.co.uk> 4 * Copyright (C) 2012 Javier Martinez Canillas <javier@collabora.co.uk>
5 * Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com> 5 * Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com>
@@ -10,7 +10,7 @@
10 */ 10 */
11/dts-v1/; 11/dts-v1/;
12 12
13#include "omap34xx.dtsi" 13#include "omap36xx.dtsi"
14 14
15/ { 15/ {
16 memory { 16 memory {
@@ -24,6 +24,25 @@
24 ti,mcbsp = <&mcbsp2>; 24 ti,mcbsp = <&mcbsp2>;
25 ti,codec = <&twl_audio>; 25 ti,codec = <&twl_audio>;
26 }; 26 };
27
28 vdd33: regulator-vdd33 {
29 compatible = "regulator-fixed";
30 regulator-name = "vdd33";
31 regulator-always-on;
32 };
33
34 lbee1usjyc_vmmc: lbee1usjyc_vmmc {
35 pinctrl-names = "default";
36 pinctrl-0 = <&lbee1usjyc_pins>;
37 compatible = "regulator-fixed";
38 regulator-name = "regulator-lbee1usjyc";
39 regulator-min-microvolt = <3300000>;
40 regulator-max-microvolt = <3300000>;
41 gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>; /* gpio_138 WIFI_PDN */
42 startup-delay-us = <10000>;
43 enable-active-high;
44 vin-supply = <&vdd33>;
45 };
27}; 46};
28 47
29&omap3_pmx_core { 48&omap3_pmx_core {
@@ -48,6 +67,15 @@
48 >; 67 >;
49 }; 68 };
50 69
70 /* WiFi/BT combo */
71 lbee1usjyc_pins: pinmux_lbee1usjyc_pins {
72 pinctrl-single,pins = <
73 0x136 (PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 */
74 0x138 (PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 */
75 0x13a (PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 */
76 >;
77 };
78
51 mcbsp2_pins: pinmux_mcbsp2_pins { 79 mcbsp2_pins: pinmux_mcbsp2_pins {
52 pinctrl-single,pins = < 80 pinctrl-single,pins = <
53 0x10c (PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_fsx */ 81 0x10c (PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_fsx */
@@ -65,10 +93,17 @@
65 0x11a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ 93 0x11a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */
66 0x11c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ 94 0x11c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */
67 0x11e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ 95 0x11e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */
68 0x120 (PIN_INPUT | MUX_MODE0) /* sdmmc1_dat4.sdmmc1_dat4 */ 96 >;
69 0x122 (PIN_INPUT | MUX_MODE0) /* sdmmc1_dat5.sdmmc1_dat5 */ 97 };
70 0x124 (PIN_INPUT | MUX_MODE0) /* sdmmc1_dat6.sdmmc1_dat6 */ 98
71 0x126 (PIN_INPUT | MUX_MODE0) /* sdmmc1_dat7.sdmmc1_dat7 */ 99 mmc2_pins: pinmux_mmc2_pins {
100 pinctrl-single,pins = <
101 0x128 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */
102 0x12a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */
103 0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */
104 0x12e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */
105 0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */
106 0x132 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */
72 >; 107 >;
73 }; 108 };
74 109
@@ -78,10 +113,33 @@
78 >; 113 >;
79 }; 114 };
80 115
116 i2c1_pins: pinmux_i2c1_pins {
117 pinctrl-single,pins = <
118 0x18a (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
119 0x18c (PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
120 >;
121 };
122
123 i2c2_pins: pinmux_i2c2_pins {
124 pinctrl-single,pins = <
125 0x18e (PIN_INPUT | MUX_MODE0) /* i2c2_scl.i2c2_scl */
126 0x190 (PIN_INPUT | MUX_MODE0) /* i2c2_sda.i2c2_sda */
127 >;
128 };
129
130 i2c3_pins: pinmux_i2c3_pins {
131 pinctrl-single,pins = <
132 0x192 (PIN_INPUT | MUX_MODE0) /* i2c3_scl.i2c3_scl */
133 0x194 (PIN_INPUT | MUX_MODE0) /* i2c3_sda.i2c3_sda */
134 >;
135 };
136
81 leds_pins: pinmux_leds_pins { }; 137 leds_pins: pinmux_leds_pins { };
82}; 138};
83 139
84&i2c1 { 140&i2c1 {
141 pinctrl-names = "default";
142 pinctrl-0 = <&i2c1_pins>;
85 clock-frequency = <2600000>; 143 clock-frequency = <2600000>;
86 144
87 twl: twl@48 { 145 twl: twl@48 {
@@ -101,9 +159,16 @@
101#include "twl4030_omap3.dtsi" 159#include "twl4030_omap3.dtsi"
102 160
103&i2c2 { 161&i2c2 {
162 pinctrl-names = "default";
163 pinctrl-0 = <&i2c2_pins>;
104 clock-frequency = <400000>; 164 clock-frequency = <400000>;
105}; 165};
106 166
167&i2c3 {
168 pinctrl-names = "default";
169 pinctrl-0 = <&i2c3_pins>;
170};
171
107&mcbsp2 { 172&mcbsp2 {
108 pinctrl-names = "default"; 173 pinctrl-names = "default";
109 pinctrl-0 = <&mcbsp2_pins>; 174 pinctrl-0 = <&mcbsp2_pins>;
@@ -114,11 +179,15 @@
114 pinctrl-0 = <&mmc1_pins>; 179 pinctrl-0 = <&mmc1_pins>;
115 vmmc-supply = <&vmmc1>; 180 vmmc-supply = <&vmmc1>;
116 vmmc_aux-supply = <&vsim>; 181 vmmc_aux-supply = <&vsim>;
117 bus-width = <8>; 182 bus-width = <4>;
118}; 183};
119 184
120&mmc2 { 185&mmc2 {
121 status = "disabled"; 186 pinctrl-names = "default";
187 pinctrl-0 = <&mmc2_pins>;
188 vmmc-supply = <&lbee1usjyc_vmmc>;
189 bus-width = <4>;
190 non-removable;
122}; 191};
123 192
124&mmc3 { 193&mmc3 {
diff --git a/arch/arm/boot/dts/omap3-igep0020.dts b/arch/arm/boot/dts/omap3-igep0020.dts
index d5cc79267250..1c7e74d2d2bc 100644
--- a/arch/arm/boot/dts/omap3-igep0020.dts
+++ b/arch/arm/boot/dts/omap3-igep0020.dts
@@ -1,5 +1,5 @@
1/* 1/*
2 * Device Tree Source for IGEPv2 board 2 * Device Tree Source for IGEPv2 Rev. (TI OMAP AM/DM37x)
3 * 3 *
4 * Copyright (C) 2012 Javier Martinez Canillas <javier@collabora.co.uk> 4 * Copyright (C) 2012 Javier Martinez Canillas <javier@collabora.co.uk>
5 * Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com> 5 * Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com>
@@ -13,7 +13,7 @@
13#include "omap-gpmc-smsc911x.dtsi" 13#include "omap-gpmc-smsc911x.dtsi"
14 14
15/ { 15/ {
16 model = "IGEPv2"; 16 model = "IGEPv2 (TI OMAP AM/DM37x)";
17 compatible = "isee,omap3-igep0020", "ti,omap3"; 17 compatible = "isee,omap3-igep0020", "ti,omap3";
18 18
19 leds { 19 leds {
@@ -67,6 +67,8 @@
67 pinctrl-names = "default"; 67 pinctrl-names = "default";
68 pinctrl-0 = < 68 pinctrl-0 = <
69 &hsusbb1_pins 69 &hsusbb1_pins
70 &tfp410_pins
71 &dss_pins
70 >; 72 >;
71 73
72 hsusbb1_pins: pinmux_hsusbb1_pins { 74 hsusbb1_pins: pinmux_hsusbb1_pins {
@@ -85,6 +87,45 @@
85 0x5ba (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d7.hsusb1_data3 */ 87 0x5ba (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d7.hsusb1_data3 */
86 >; 88 >;
87 }; 89 };
90
91 tfp410_pins: tfp410_dvi_pins {
92 pinctrl-single,pins = <
93 0x196 (PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */
94 >;
95 };
96
97 dss_pins: pinmux_dss_dvi_pins {
98 pinctrl-single,pins = <
99 0x0a4 (PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
100 0x0a6 (PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
101 0x0a8 (PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
102 0x0aa (PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
103 0x0ac (PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */
104 0x0ae (PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */
105 0x0b0 (PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */
106 0x0b2 (PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */
107 0x0b4 (PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */
108 0x0b6 (PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */
109 0x0b8 (PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */
110 0x0ba (PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */
111 0x0bc (PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */
112 0x0be (PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */
113 0x0c0 (PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */
114 0x0c2 (PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */
115 0x0c4 (PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */
116 0x0c6 (PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */
117 0x0c8 (PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */
118 0x0ca (PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
119 0x0cc (PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */
120 0x0ce (PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */
121 0x0d0 (PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */
122 0x0d2 (PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */
123 0x0d4 (PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */
124 0x0d6 (PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */
125 0x0d8 (PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */
126 0x0da (PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */
127 >;
128 };
88}; 129};
89 130
90&leds_pins { 131&leds_pins {
@@ -174,3 +215,8 @@
174&usbhsehci { 215&usbhsehci {
175 phys = <&hsusb1_phy>; 216 phys = <&hsusb1_phy>;
176}; 217};
218
219&vpll2 {
220 /* Needed for DSS */
221 regulator-name = "vdds_dsi";
222};
diff --git a/arch/arm/boot/dts/omap3-igep0030.dts b/arch/arm/boot/dts/omap3-igep0030.dts
index 525e6d9b0978..02a23f8a3384 100644
--- a/arch/arm/boot/dts/omap3-igep0030.dts
+++ b/arch/arm/boot/dts/omap3-igep0030.dts
@@ -1,5 +1,5 @@
1/* 1/*
2 * Device Tree Source for IGEP COM Module 2 * Device Tree Source for IGEP COM MODULE (TI OMAP AM/DM37x)
3 * 3 *
4 * Copyright (C) 2012 Javier Martinez Canillas <javier@collabora.co.uk> 4 * Copyright (C) 2012 Javier Martinez Canillas <javier@collabora.co.uk>
5 * Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com> 5 * Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com>
@@ -12,7 +12,7 @@
12#include "omap3-igep.dtsi" 12#include "omap3-igep.dtsi"
13 13
14/ { 14/ {
15 model = "IGEP COM Module"; 15 model = "IGEP COM MODULE (TI OMAP AM/DM37x)";
16 compatible = "isee,omap3-igep0030", "ti,omap3"; 16 compatible = "isee,omap3-igep0030", "ti,omap3";
17 17
18 leds { 18 leds {
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts
index c4f20bfe4cce..c2c306d13b87 100644
--- a/arch/arm/boot/dts/omap3-n900.dts
+++ b/arch/arm/boot/dts/omap3-n900.dts
@@ -125,6 +125,21 @@
125 >; 125 >;
126 }; 126 };
127 127
128 mmc2_pins: pinmux_mmc2_pins {
129 pinctrl-single,pins = <
130 0x128 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk */
131 0x12a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd */
132 0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0 */
133 0x12e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1 */
134 0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2 */
135 0x132 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3 */
136 0x134 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat4 */
137 0x136 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat5 */
138 0x138 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat6 */
139 0x13a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat7 */
140 >;
141 };
142
128 display_pins: pinmux_display_pins { 143 display_pins: pinmux_display_pins {
129 pinctrl-single,pins = < 144 pinctrl-single,pins = <
130 0x0d4 (PIN_OUTPUT | MUX_MODE4) /* RX51_LCD_RESET_GPIO */ 145 0x0d4 (PIN_OUTPUT | MUX_MODE4) /* RX51_LCD_RESET_GPIO */
@@ -358,8 +373,14 @@
358 cd-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>; /* 160 */ 373 cd-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>; /* 160 */
359}; 374};
360 375
376/* most boards use vaux3, only some old versions use vmmc2 instead */
361&mmc2 { 377&mmc2 {
362 status = "disabled"; 378 pinctrl-names = "default";
379 pinctrl-0 = <&mmc2_pins>;
380 vmmc-supply = <&vaux3>;
381 vmmc_aux-supply = <&vsim>;
382 bus-width = <8>;
383 non-removable;
363}; 384};
364 385
365&mmc3 { 386&mmc3 {
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index f3a0c26ed0c2..daabf99d402a 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -82,6 +82,13 @@
82 ranges; 82 ranges;
83 ti,hwmods = "l3_main"; 83 ti,hwmods = "l3_main";
84 84
85 aes: aes@480c5000 {
86 compatible = "ti,omap3-aes";
87 ti,hwmods = "aes";
88 reg = <0x480c5000 0x50>;
89 interrupts = <0>;
90 };
91
85 counter32k: counter@48320000 { 92 counter32k: counter@48320000 {
86 compatible = "ti,omap-counter32k"; 93 compatible = "ti,omap-counter32k";
87 reg = <0x48320000 0x20>; 94 reg = <0x48320000 0x20>;
@@ -260,6 +267,13 @@
260 ti,hwmods = "i2c3"; 267 ti,hwmods = "i2c3";
261 }; 268 };
262 269
270 mailbox: mailbox@48094000 {
271 compatible = "ti,omap3-mailbox";
272 ti,hwmods = "mailbox";
273 reg = <0x48094000 0x200>;
274 interrupts = <26>;
275 };
276
263 mcspi1: spi@48098000 { 277 mcspi1: spi@48098000 {
264 compatible = "ti,omap2-mcspi"; 278 compatible = "ti,omap2-mcspi";
265 reg = <0x48098000 0x100>; 279 reg = <0x48098000 0x100>;
@@ -357,6 +371,13 @@
357 dma-names = "tx", "rx"; 371 dma-names = "tx", "rx";
358 }; 372 };
359 373
374 mmu_isp: mmu@480bd400 {
375 compatible = "ti,omap3-mmu-isp";
376 ti,hwmods = "mmu_isp";
377 reg = <0x480bd400 0x80>;
378 interrupts = <8>;
379 };
380
360 wdt2: wdt@48314000 { 381 wdt2: wdt@48314000 {
361 compatible = "ti,omap3-wdt"; 382 compatible = "ti,omap3-wdt";
362 reg = <0x48314000 0x80>; 383 reg = <0x48314000 0x80>;
@@ -442,6 +463,27 @@
442 dma-names = "tx", "rx"; 463 dma-names = "tx", "rx";
443 }; 464 };
444 465
466 sham: sham@480c3000 {
467 compatible = "ti,omap3-sham";
468 ti,hwmods = "sham";
469 reg = <0x480c3000 0x64>;
470 interrupts = <49>;
471 };
472
473 smartreflex_core: smartreflex@480cb000 {
474 compatible = "ti,omap3-smartreflex-core";
475 ti,hwmods = "smartreflex_core";
476 reg = <0x480cb000 0x400>;
477 interrupts = <19>;
478 };
479
480 smartreflex_mpu_iva: smartreflex@480c9000 {
481 compatible = "ti,omap3-smartreflex-iva";
482 ti,hwmods = "smartreflex_mpu_iva";
483 reg = <0x480c9000 0x400>;
484 interrupts = <18>;
485 };
486
445 timer1: timer@48318000 { 487 timer1: timer@48318000 {
446 compatible = "ti,omap3430-timer"; 488 compatible = "ti,omap3430-timer";
447 reg = <0x48318000 0x400>; 489 reg = <0x48318000 0x400>;
diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
index 298e85020e1b..88c6a05cab41 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -246,15 +246,6 @@
246 0xf0 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ 246 0xf0 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */
247 >; 247 >;
248 }; 248 };
249};
250
251&omap4_pmx_wkup {
252 led_wkgpio_pins: pinmux_leds_wkpins {
253 pinctrl-single,pins = <
254 0x1a (PIN_OUTPUT | MUX_MODE3) /* gpio_wk7 */
255 0x1c (PIN_OUTPUT | MUX_MODE3) /* gpio_wk8 */
256 >;
257 };
258 249
259 /* 250 /*
260 * wl12xx GPIO outputs for WLAN_EN, BT_EN, FM_EN, BT_WAKEUP 251 * wl12xx GPIO outputs for WLAN_EN, BT_EN, FM_EN, BT_WAKEUP
@@ -274,7 +265,7 @@
274 pinctrl-single,pins = < 265 pinctrl-single,pins = <
275 0x38 (PIN_INPUT | MUX_MODE3) /* gpmc_ncs2.gpio_52 */ 266 0x38 (PIN_INPUT | MUX_MODE3) /* gpmc_ncs2.gpio_52 */
276 0x3a (PIN_INPUT | MUX_MODE3) /* gpmc_ncs3.gpio_53 */ 267 0x3a (PIN_INPUT | MUX_MODE3) /* gpmc_ncs3.gpio_53 */
277 0x108 (PIN_OUTPUT | MUX_MODE0) /* sdmmc5_clk.sdmmc5_clk */ 268 0x108 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_clk.sdmmc5_clk */
278 0x10a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_cmd.sdmmc5_cmd */ 269 0x10a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_cmd.sdmmc5_cmd */
279 0x10c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat0.sdmmc5_dat0 */ 270 0x10c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat0.sdmmc5_dat0 */
280 0x10e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat1.sdmmc5_dat1 */ 271 0x10e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat1.sdmmc5_dat1 */
@@ -284,6 +275,15 @@
284 }; 275 };
285}; 276};
286 277
278&omap4_pmx_wkup {
279 led_wkgpio_pins: pinmux_leds_wkpins {
280 pinctrl-single,pins = <
281 0x1a (PIN_OUTPUT | MUX_MODE3) /* gpio_wk7 */
282 0x1c (PIN_OUTPUT | MUX_MODE3) /* gpio_wk8 */
283 >;
284 };
285};
286
287&i2c1 { 287&i2c1 {
288 pinctrl-names = "default"; 288 pinctrl-names = "default";
289 pinctrl-0 = <&i2c1_pins>; 289 pinctrl-0 = <&i2c1_pins>;
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index 5fc3f43c5a81..dbc81fb6ef03 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -300,12 +300,12 @@
300 wl12xx_pins: pinmux_wl12xx_pins { 300 wl12xx_pins: pinmux_wl12xx_pins {
301 pinctrl-single,pins = < 301 pinctrl-single,pins = <
302 0x3a (PIN_INPUT | MUX_MODE3) /* gpmc_ncs3.gpio_53 */ 302 0x3a (PIN_INPUT | MUX_MODE3) /* gpmc_ncs3.gpio_53 */
303 0x108 (PIN_OUTPUT | MUX_MODE3) /* sdmmc5_clk.sdmmc5_clk */ 303 0x108 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_clk.sdmmc5_clk */
304 0x10a (PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc5_cmd.sdmmc5_cmd */ 304 0x10a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_cmd.sdmmc5_cmd */
305 0x10c (PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc5_dat0.sdmmc5_dat0 */ 305 0x10c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat0.sdmmc5_dat0 */
306 0x10e (PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc5_dat1.sdmmc5_dat1 */ 306 0x10e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat1.sdmmc5_dat1 */
307 0x110 (PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc5_dat2.sdmmc5_dat2 */ 307 0x110 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat2.sdmmc5_dat2 */
308 0x112 (PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc5_dat3.sdmmc5_dat3 */ 308 0x112 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat3.sdmmc5_dat3 */
309 >; 309 >;
310 }; 310 };
311}; 311};
diff --git a/arch/arm/boot/dts/pxa27x.dtsi b/arch/arm/boot/dts/pxa27x.dtsi
index d7c5d721a5c7..a70546945985 100644
--- a/arch/arm/boot/dts/pxa27x.dtsi
+++ b/arch/arm/boot/dts/pxa27x.dtsi
@@ -10,5 +10,29 @@
10 marvell,intc-priority; 10 marvell,intc-priority;
11 marvell,intc-nr-irqs = <34>; 11 marvell,intc-nr-irqs = <34>;
12 }; 12 };
13
14 pwm0: pwm@40b00000 {
15 compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm";
16 reg = <0x40b00000 0x10>;
17 #pwm-cells = <1>;
18 };
19
20 pwm1: pwm@40b00010 {
21 compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm";
22 reg = <0x40b00010 0x10>;
23 #pwm-cells = <1>;
24 };
25
26 pwm2: pwm@40c00000 {
27 compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm";
28 reg = <0x40c00000 0x10>;
29 #pwm-cells = <1>;
30 };
31
32 pwm3: pwm@40c00010 {
33 compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm";
34 reg = <0x40c00010 0x10>;
35 #pwm-cells = <1>;
36 };
13 }; 37 };
14}; 38};
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
new file mode 100644
index 000000000000..6ac94967d2d3
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -0,0 +1,97 @@
1/dts-v1/;
2
3#include "skeleton.dtsi"
4
5/ {
6 model = "Qualcomm MSM8974";
7 compatible = "qcom,msm8974";
8 interrupt-parent = <&intc>;
9
10 soc: soc {
11 #address-cells = <1>;
12 #size-cells = <1>;
13 ranges;
14 compatible = "simple-bus";
15
16 intc: interrupt-controller@f9000000 {
17 compatible = "qcom,msm-qgic2";
18 interrupt-controller;
19 #interrupt-cells = <3>;
20 reg = <0xf9000000 0x1000>,
21 <0xf9002000 0x1000>;
22 };
23
24 timer {
25 compatible = "arm,armv7-timer";
26 interrupts = <1 2 0xf08>,
27 <1 3 0xf08>,
28 <1 4 0xf08>,
29 <1 1 0xf08>;
30 clock-frequency = <19200000>;
31 };
32
33 timer@f9020000 {
34 #address-cells = <1>;
35 #size-cells = <1>;
36 ranges;
37 compatible = "arm,armv7-timer-mem";
38 reg = <0xf9020000 0x1000>;
39 clock-frequency = <19200000>;
40
41 frame@f9021000 {
42 frame-number = <0>;
43 interrupts = <0 8 0x4>,
44 <0 7 0x4>;
45 reg = <0xf9021000 0x1000>,
46 <0xf9022000 0x1000>;
47 };
48
49 frame@f9023000 {
50 frame-number = <1>;
51 interrupts = <0 9 0x4>;
52 reg = <0xf9023000 0x1000>;
53 status = "disabled";
54 };
55
56 frame@f9024000 {
57 frame-number = <2>;
58 interrupts = <0 10 0x4>;
59 reg = <0xf9024000 0x1000>;
60 status = "disabled";
61 };
62
63 frame@f9025000 {
64 frame-number = <3>;
65 interrupts = <0 11 0x4>;
66 reg = <0xf9025000 0x1000>;
67 status = "disabled";
68 };
69
70 frame@f9026000 {
71 frame-number = <4>;
72 interrupts = <0 12 0x4>;
73 reg = <0xf9026000 0x1000>;
74 status = "disabled";
75 };
76
77 frame@f9027000 {
78 frame-number = <5>;
79 interrupts = <0 13 0x4>;
80 reg = <0xf9027000 0x1000>;
81 status = "disabled";
82 };
83
84 frame@f9028000 {
85 frame-number = <6>;
86 interrupts = <0 14 0x4>;
87 reg = <0xf9028000 0x1000>;
88 status = "disabled";
89 };
90 };
91
92 restart@fc4ab000 {
93 compatible = "qcom,pshold";
94 reg = <0xfc4ab000 0x4>;
95 };
96 };
97};
diff --git a/arch/arm/boot/dts/r7s72100-genmai.dts b/arch/arm/boot/dts/r7s72100-genmai.dts
index 1fb20f2333cc..b1deaf7e2e06 100644
--- a/arch/arm/boot/dts/r7s72100-genmai.dts
+++ b/arch/arm/boot/dts/r7s72100-genmai.dts
@@ -9,7 +9,7 @@
9 */ 9 */
10 10
11/dts-v1/; 11/dts-v1/;
12/include/ "r7s72100.dtsi" 12#include "r7s72100.dtsi"
13 13
14/ { 14/ {
15 model = "Genmai"; 15 model = "Genmai";
diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts
index 9443e93d3cac..70b1fff8f4a3 100644
--- a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts
+++ b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts
@@ -9,7 +9,7 @@
9 */ 9 */
10 10
11/dts-v1/; 11/dts-v1/;
12/include/ "r8a73a4.dtsi" 12#include "r8a73a4.dtsi"
13#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/gpio/gpio.h>
14 14
15/ { 15/ {
@@ -25,6 +25,11 @@
25 reg = <0 0x40000000 0 0x40000000>; 25 reg = <0 0x40000000 0 0x40000000>;
26 }; 26 };
27 27
28 memory@200000000 {
29 device_type = "memory";
30 reg = <2 0x00000000 0 0x40000000>;
31 };
32
28 vcc_mmc0: regulator@0 { 33 vcc_mmc0: regulator@0 {
29 compatible = "regulator-fixed"; 34 compatible = "regulator-fixed";
30 regulator-name = "MMC0 Vcc"; 35 regulator-name = "MMC0 Vcc";
@@ -88,22 +93,22 @@
88 pinctrl-0 = <&scifa0_pins>; 93 pinctrl-0 = <&scifa0_pins>;
89 pinctrl-names = "default"; 94 pinctrl-names = "default";
90 95
91 scifa0_pins: scifa0 { 96 scifa0_pins: serial0 {
92 renesas,groups = "scifa0_data"; 97 renesas,groups = "scifa0_data";
93 renesas,function = "scifa0"; 98 renesas,function = "scifa0";
94 }; 99 };
95 100
96 mmc0_pins: mmcif { 101 mmc0_pins: mmc {
97 renesas,groups = "mmc0_data8", "mmc0_ctrl"; 102 renesas,groups = "mmc0_data8", "mmc0_ctrl";
98 renesas,function = "mmc0"; 103 renesas,function = "mmc0";
99 }; 104 };
100 105
101 sdhi0_pins: sdhi0 { 106 sdhi0_pins: sd0 {
102 renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd"; 107 renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";
103 renesas,function = "sdhi0"; 108 renesas,function = "sdhi0";
104 }; 109 };
105 110
106 sdhi1_pins: sdhi1 { 111 sdhi1_pins: sd1 {
107 renesas,groups = "sdhi1_data4", "sdhi1_ctrl"; 112 renesas,groups = "sdhi1_data4", "sdhi1_ctrl";
108 renesas,function = "sdhi1"; 113 renesas,function = "sdhi1";
109 }; 114 };
diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
index 91436b58016f..ce085fa444a1 100644
--- a/arch/arm/boot/dts/r8a73a4-ape6evm.dts
+++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
@@ -9,7 +9,8 @@
9 */ 9 */
10 10
11/dts-v1/; 11/dts-v1/;
12/include/ "r8a73a4.dtsi" 12#include "r8a73a4.dtsi"
13#include <dt-bindings/interrupt-controller/irq.h>
13 14
14/ { 15/ {
15 model = "APE6EVM"; 16 model = "APE6EVM";
@@ -24,6 +25,11 @@
24 reg = <0 0x40000000 0 0x40000000>; 25 reg = <0 0x40000000 0 0x40000000>;
25 }; 26 };
26 27
28 memory@200000000 {
29 device_type = "memory";
30 reg = <2 0x00000000 0 0x40000000>;
31 };
32
27 ape6evm_fixed_3v3: fixedregulator@0 { 33 ape6evm_fixed_3v3: fixedregulator@0 {
28 compatible = "regulator-fixed"; 34 compatible = "regulator-fixed";
29 regulator-name = "3V3"; 35 regulator-name = "3V3";
@@ -40,7 +46,7 @@
40 compatible = "smsc,lan9118", "smsc,lan9115"; 46 compatible = "smsc,lan9118", "smsc,lan9115";
41 reg = <0x08000000 0x1000>; 47 reg = <0x08000000 0x1000>;
42 interrupt-parent = <&irqc1>; 48 interrupt-parent = <&irqc1>;
43 interrupts = <8 0x4>; 49 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
44 phy-mode = "mii"; 50 phy-mode = "mii";
45 reg-io-width = <4>; 51 reg-io-width = <4>;
46 smsc,irq-active-high; 52 smsc,irq-active-high;
diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
index 287e047592a0..6b7ce89a68f7 100644
--- a/arch/arm/boot/dts/r8a73a4.dtsi
+++ b/arch/arm/boot/dts/r8a73a4.dtsi
@@ -9,6 +9,9 @@
9 * kind, whether express or implied. 9 * kind, whether express or implied.
10 */ 10 */
11 11
12#include <dt-bindings/interrupt-controller/arm-gic.h>
13#include <dt-bindings/interrupt-controller/irq.h>
14
12/ { 15/ {
13 compatible = "renesas,r8a73a4"; 16 compatible = "renesas,r8a73a4";
14 interrupt-parent = <&gic>; 17 interrupt-parent = <&gic>;
@@ -36,15 +39,15 @@
36 <0 0xf1002000 0 0x1000>, 39 <0 0xf1002000 0 0x1000>,
37 <0 0xf1004000 0 0x2000>, 40 <0 0xf1004000 0 0x2000>,
38 <0 0xf1006000 0 0x2000>; 41 <0 0xf1006000 0 0x2000>;
39 interrupts = <1 9 0xf04>; 42 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
40 }; 43 };
41 44
42 timer { 45 timer {
43 compatible = "arm,armv7-timer"; 46 compatible = "arm,armv7-timer";
44 interrupts = <1 13 0xf08>, 47 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
45 <1 14 0xf08>, 48 <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
46 <1 11 0xf08>, 49 <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
47 <1 10 0xf08>; 50 <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
48 }; 51 };
49 52
50 irqc0: interrupt-controller@e61c0000 { 53 irqc0: interrupt-controller@e61c0000 {
@@ -53,14 +56,38 @@
53 interrupt-controller; 56 interrupt-controller;
54 reg = <0 0xe61c0000 0 0x200>; 57 reg = <0 0xe61c0000 0 0x200>;
55 interrupt-parent = <&gic>; 58 interrupt-parent = <&gic>;
56 interrupts = <0 0 4>, <0 1 4>, <0 2 4>, <0 3 4>, 59 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
57 <0 4 4>, <0 5 4>, <0 6 4>, <0 7 4>, 60 <0 1 IRQ_TYPE_LEVEL_HIGH>,
58 <0 8 4>, <0 9 4>, <0 10 4>, <0 11 4>, 61 <0 2 IRQ_TYPE_LEVEL_HIGH>,
59 <0 12 4>, <0 13 4>, <0 14 4>, <0 15 4>, 62 <0 3 IRQ_TYPE_LEVEL_HIGH>,
60 <0 16 4>, <0 17 4>, <0 18 4>, <0 19 4>, 63 <0 4 IRQ_TYPE_LEVEL_HIGH>,
61 <0 20 4>, <0 21 4>, <0 22 4>, <0 23 4>, 64 <0 5 IRQ_TYPE_LEVEL_HIGH>,
62 <0 24 4>, <0 25 4>, <0 26 4>, <0 27 4>, 65 <0 6 IRQ_TYPE_LEVEL_HIGH>,
63 <0 28 4>, <0 29 4>, <0 30 4>, <0 31 4>; 66 <0 7 IRQ_TYPE_LEVEL_HIGH>,
67 <0 8 IRQ_TYPE_LEVEL_HIGH>,
68 <0 9 IRQ_TYPE_LEVEL_HIGH>,
69 <0 10 IRQ_TYPE_LEVEL_HIGH>,
70 <0 11 IRQ_TYPE_LEVEL_HIGH>,
71 <0 12 IRQ_TYPE_LEVEL_HIGH>,
72 <0 13 IRQ_TYPE_LEVEL_HIGH>,
73 <0 14 IRQ_TYPE_LEVEL_HIGH>,
74 <0 15 IRQ_TYPE_LEVEL_HIGH>,
75 <0 16 IRQ_TYPE_LEVEL_HIGH>,
76 <0 17 IRQ_TYPE_LEVEL_HIGH>,
77 <0 18 IRQ_TYPE_LEVEL_HIGH>,
78 <0 19 IRQ_TYPE_LEVEL_HIGH>,
79 <0 20 IRQ_TYPE_LEVEL_HIGH>,
80 <0 21 IRQ_TYPE_LEVEL_HIGH>,
81 <0 22 IRQ_TYPE_LEVEL_HIGH>,
82 <0 23 IRQ_TYPE_LEVEL_HIGH>,
83 <0 24 IRQ_TYPE_LEVEL_HIGH>,
84 <0 25 IRQ_TYPE_LEVEL_HIGH>,
85 <0 26 IRQ_TYPE_LEVEL_HIGH>,
86 <0 27 IRQ_TYPE_LEVEL_HIGH>,
87 <0 28 IRQ_TYPE_LEVEL_HIGH>,
88 <0 29 IRQ_TYPE_LEVEL_HIGH>,
89 <0 30 IRQ_TYPE_LEVEL_HIGH>,
90 <0 31 IRQ_TYPE_LEVEL_HIGH>;
64 }; 91 };
65 92
66 irqc1: interrupt-controller@e61c0200 { 93 irqc1: interrupt-controller@e61c0200 {
@@ -69,13 +96,32 @@
69 interrupt-controller; 96 interrupt-controller;
70 reg = <0 0xe61c0200 0 0x200>; 97 reg = <0 0xe61c0200 0 0x200>;
71 interrupt-parent = <&gic>; 98 interrupt-parent = <&gic>;
72 interrupts = <0 32 4>, <0 33 4>, <0 34 4>, <0 35 4>, 99 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>,
73 <0 36 4>, <0 37 4>, <0 38 4>, <0 39 4>, 100 <0 33 IRQ_TYPE_LEVEL_HIGH>,
74 <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>, 101 <0 34 IRQ_TYPE_LEVEL_HIGH>,
75 <0 44 4>, <0 45 4>, <0 46 4>, <0 47 4>, 102 <0 35 IRQ_TYPE_LEVEL_HIGH>,
76 <0 48 4>, <0 49 4>, <0 50 4>, <0 51 4>, 103 <0 36 IRQ_TYPE_LEVEL_HIGH>,
77 <0 52 4>, <0 53 4>, <0 54 4>, <0 55 4>, 104 <0 37 IRQ_TYPE_LEVEL_HIGH>,
78 <0 56 4>, <0 57 4>; 105 <0 38 IRQ_TYPE_LEVEL_HIGH>,
106 <0 39 IRQ_TYPE_LEVEL_HIGH>,
107 <0 40 IRQ_TYPE_LEVEL_HIGH>,
108 <0 41 IRQ_TYPE_LEVEL_HIGH>,
109 <0 42 IRQ_TYPE_LEVEL_HIGH>,
110 <0 43 IRQ_TYPE_LEVEL_HIGH>,
111 <0 44 IRQ_TYPE_LEVEL_HIGH>,
112 <0 45 IRQ_TYPE_LEVEL_HIGH>,
113 <0 46 IRQ_TYPE_LEVEL_HIGH>,
114 <0 47 IRQ_TYPE_LEVEL_HIGH>,
115 <0 48 IRQ_TYPE_LEVEL_HIGH>,
116 <0 49 IRQ_TYPE_LEVEL_HIGH>,
117 <0 50 IRQ_TYPE_LEVEL_HIGH>,
118 <0 51 IRQ_TYPE_LEVEL_HIGH>,
119 <0 52 IRQ_TYPE_LEVEL_HIGH>,
120 <0 53 IRQ_TYPE_LEVEL_HIGH>,
121 <0 54 IRQ_TYPE_LEVEL_HIGH>,
122 <0 55 IRQ_TYPE_LEVEL_HIGH>,
123 <0 56 IRQ_TYPE_LEVEL_HIGH>,
124 <0 57 IRQ_TYPE_LEVEL_HIGH>;
79 }; 125 };
80 126
81 dmac: dma-multiplexer@0 { 127 dmac: dma-multiplexer@0 {
@@ -91,27 +137,27 @@
91 compatible = "renesas,shdma-r8a73a4"; 137 compatible = "renesas,shdma-r8a73a4";
92 reg = <0 0xe6700020 0 0x89e0>; 138 reg = <0 0xe6700020 0 0x89e0>;
93 interrupt-parent = <&gic>; 139 interrupt-parent = <&gic>;
94 interrupts = <0 220 4 140 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
95 0 200 4 141 0 200 IRQ_TYPE_LEVEL_HIGH
96 0 201 4 142 0 201 IRQ_TYPE_LEVEL_HIGH
97 0 202 4 143 0 202 IRQ_TYPE_LEVEL_HIGH
98 0 203 4 144 0 203 IRQ_TYPE_LEVEL_HIGH
99 0 204 4 145 0 204 IRQ_TYPE_LEVEL_HIGH
100 0 205 4 146 0 205 IRQ_TYPE_LEVEL_HIGH
101 0 206 4 147 0 206 IRQ_TYPE_LEVEL_HIGH
102 0 207 4 148 0 207 IRQ_TYPE_LEVEL_HIGH
103 0 208 4 149 0 208 IRQ_TYPE_LEVEL_HIGH
104 0 209 4 150 0 209 IRQ_TYPE_LEVEL_HIGH
105 0 210 4 151 0 210 IRQ_TYPE_LEVEL_HIGH
106 0 211 4 152 0 211 IRQ_TYPE_LEVEL_HIGH
107 0 212 4 153 0 212 IRQ_TYPE_LEVEL_HIGH
108 0 213 4 154 0 213 IRQ_TYPE_LEVEL_HIGH
109 0 214 4 155 0 214 IRQ_TYPE_LEVEL_HIGH
110 0 215 4 156 0 215 IRQ_TYPE_LEVEL_HIGH
111 0 216 4 157 0 216 IRQ_TYPE_LEVEL_HIGH
112 0 217 4 158 0 217 IRQ_TYPE_LEVEL_HIGH
113 0 218 4 159 0 218 IRQ_TYPE_LEVEL_HIGH
114 0 219 4>; 160 0 219 IRQ_TYPE_LEVEL_HIGH>;
115 interrupt-names = "error", 161 interrupt-names = "error",
116 "ch0", "ch1", "ch2", "ch3", 162 "ch0", "ch1", "ch2", "ch3",
117 "ch4", "ch5", "ch6", "ch7", 163 "ch4", "ch5", "ch6", "ch7",
@@ -126,7 +172,7 @@
126 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>, 172 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>,
127 <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>; 173 <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>;
128 interrupt-parent = <&gic>; 174 interrupt-parent = <&gic>;
129 interrupts = <0 69 4>; 175 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
130 }; 176 };
131 177
132 i2c0: i2c@e6500000 { 178 i2c0: i2c@e6500000 {
@@ -135,7 +181,7 @@
135 compatible = "renesas,rmobile-iic"; 181 compatible = "renesas,rmobile-iic";
136 reg = <0 0xe6500000 0 0x428>; 182 reg = <0 0xe6500000 0 0x428>;
137 interrupt-parent = <&gic>; 183 interrupt-parent = <&gic>;
138 interrupts = <0 174 0x4>; 184 interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
139 status = "disabled"; 185 status = "disabled";
140 }; 186 };
141 187
@@ -145,7 +191,7 @@
145 compatible = "renesas,rmobile-iic"; 191 compatible = "renesas,rmobile-iic";
146 reg = <0 0xe6510000 0 0x428>; 192 reg = <0 0xe6510000 0 0x428>;
147 interrupt-parent = <&gic>; 193 interrupt-parent = <&gic>;
148 interrupts = <0 175 0x4>; 194 interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
149 status = "disabled"; 195 status = "disabled";
150 }; 196 };
151 197
@@ -155,7 +201,7 @@
155 compatible = "renesas,rmobile-iic"; 201 compatible = "renesas,rmobile-iic";
156 reg = <0 0xe6520000 0 0x428>; 202 reg = <0 0xe6520000 0 0x428>;
157 interrupt-parent = <&gic>; 203 interrupt-parent = <&gic>;
158 interrupts = <0 176 0x4>; 204 interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>;
159 status = "disabled"; 205 status = "disabled";
160 }; 206 };
161 207
@@ -165,7 +211,7 @@
165 compatible = "renesas,rmobile-iic"; 211 compatible = "renesas,rmobile-iic";
166 reg = <0 0xe6530000 0 0x428>; 212 reg = <0 0xe6530000 0 0x428>;
167 interrupt-parent = <&gic>; 213 interrupt-parent = <&gic>;
168 interrupts = <0 177 0x4>; 214 interrupts = <0 177 IRQ_TYPE_LEVEL_HIGH>;
169 status = "disabled"; 215 status = "disabled";
170 }; 216 };
171 217
@@ -175,7 +221,7 @@
175 compatible = "renesas,rmobile-iic"; 221 compatible = "renesas,rmobile-iic";
176 reg = <0 0xe6540000 0 0x428>; 222 reg = <0 0xe6540000 0 0x428>;
177 interrupt-parent = <&gic>; 223 interrupt-parent = <&gic>;
178 interrupts = <0 178 0x4>; 224 interrupts = <0 178 IRQ_TYPE_LEVEL_HIGH>;
179 status = "disabled"; 225 status = "disabled";
180 }; 226 };
181 227
@@ -185,7 +231,7 @@
185 compatible = "renesas,rmobile-iic"; 231 compatible = "renesas,rmobile-iic";
186 reg = <0 0xe60b0000 0 0x428>; 232 reg = <0 0xe60b0000 0 0x428>;
187 interrupt-parent = <&gic>; 233 interrupt-parent = <&gic>;
188 interrupts = <0 179 0x4>; 234 interrupts = <0 179 IRQ_TYPE_LEVEL_HIGH>;
189 status = "disabled"; 235 status = "disabled";
190 }; 236 };
191 237
@@ -195,7 +241,7 @@
195 compatible = "renesas,rmobile-iic"; 241 compatible = "renesas,rmobile-iic";
196 reg = <0 0xe6550000 0 0x428>; 242 reg = <0 0xe6550000 0 0x428>;
197 interrupt-parent = <&gic>; 243 interrupt-parent = <&gic>;
198 interrupts = <0 184 0x4>; 244 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
199 status = "disabled"; 245 status = "disabled";
200 }; 246 };
201 247
@@ -205,7 +251,7 @@
205 compatible = "renesas,rmobile-iic"; 251 compatible = "renesas,rmobile-iic";
206 reg = <0 0xe6560000 0 0x428>; 252 reg = <0 0xe6560000 0 0x428>;
207 interrupt-parent = <&gic>; 253 interrupt-parent = <&gic>;
208 interrupts = <0 185 0x4>; 254 interrupts = <0 185 IRQ_TYPE_LEVEL_HIGH>;
209 status = "disabled"; 255 status = "disabled";
210 }; 256 };
211 257
@@ -215,24 +261,24 @@
215 compatible = "renesas,rmobile-iic"; 261 compatible = "renesas,rmobile-iic";
216 reg = <0 0xe6570000 0 0x428>; 262 reg = <0 0xe6570000 0 0x428>;
217 interrupt-parent = <&gic>; 263 interrupt-parent = <&gic>;
218 interrupts = <0 173 0x4>; 264 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
219 status = "disabled"; 265 status = "disabled";
220 }; 266 };
221 267
222 mmcif0: mmcif@ee200000 { 268 mmcif0: mmc@ee200000 {
223 compatible = "renesas,sh-mmcif"; 269 compatible = "renesas,sh-mmcif";
224 reg = <0 0xee200000 0 0x80>; 270 reg = <0 0xee200000 0 0x80>;
225 interrupt-parent = <&gic>; 271 interrupt-parent = <&gic>;
226 interrupts = <0 169 0x4>; 272 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
227 reg-io-width = <4>; 273 reg-io-width = <4>;
228 status = "disabled"; 274 status = "disabled";
229 }; 275 };
230 276
231 mmcif1: mmcif@ee220000 { 277 mmcif1: mmc@ee220000 {
232 compatible = "renesas,sh-mmcif"; 278 compatible = "renesas,sh-mmcif";
233 reg = <0 0xee220000 0 0x80>; 279 reg = <0 0xee220000 0 0x80>;
234 interrupt-parent = <&gic>; 280 interrupt-parent = <&gic>;
235 interrupts = <0 170 0x4>; 281 interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>;
236 reg-io-width = <4>; 282 reg-io-width = <4>;
237 status = "disabled"; 283 status = "disabled";
238 }; 284 };
@@ -244,29 +290,29 @@
244 #gpio-cells = <2>; 290 #gpio-cells = <2>;
245 }; 291 };
246 292
247 sdhi0: sdhi@ee100000 { 293 sdhi0: sd@ee100000 {
248 compatible = "renesas,sdhi-r8a73a4"; 294 compatible = "renesas,sdhi-r8a73a4";
249 reg = <0 0xee100000 0 0x100>; 295 reg = <0 0xee100000 0 0x100>;
250 interrupt-parent = <&gic>; 296 interrupt-parent = <&gic>;
251 interrupts = <0 165 4>; 297 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
252 cap-sd-highspeed; 298 cap-sd-highspeed;
253 status = "disabled"; 299 status = "disabled";
254 }; 300 };
255 301
256 sdhi1: sdhi@ee120000 { 302 sdhi1: sd@ee120000 {
257 compatible = "renesas,sdhi-r8a73a4"; 303 compatible = "renesas,sdhi-r8a73a4";
258 reg = <0 0xee120000 0 0x100>; 304 reg = <0 0xee120000 0 0x100>;
259 interrupt-parent = <&gic>; 305 interrupt-parent = <&gic>;
260 interrupts = <0 166 4>; 306 interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>;
261 cap-sd-highspeed; 307 cap-sd-highspeed;
262 status = "disabled"; 308 status = "disabled";
263 }; 309 };
264 310
265 sdhi2: sdhi@ee140000 { 311 sdhi2: sd@ee140000 {
266 compatible = "renesas,sdhi-r8a73a4"; 312 compatible = "renesas,sdhi-r8a73a4";
267 reg = <0 0xee140000 0 0x100>; 313 reg = <0 0xee140000 0 0x100>;
268 interrupt-parent = <&gic>; 314 interrupt-parent = <&gic>;
269 interrupts = <0 167 4>; 315 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
270 cap-sd-highspeed; 316 cap-sd-highspeed;
271 status = "disabled"; 317 status = "disabled";
272 }; 318 };
diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
index 1c56c5e56950..6d6fd3dff2d3 100644
--- a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
+++ b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
@@ -9,8 +9,9 @@
9 */ 9 */
10 10
11/dts-v1/; 11/dts-v1/;
12/include/ "r8a7740.dtsi" 12#include "r8a7740.dtsi"
13#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/interrupt-controller/irq.h>
14#include <dt-bindings/pwm/pwm.h> 15#include <dt-bindings/pwm/pwm.h>
15 16
16/ { 17/ {
@@ -86,31 +87,55 @@
86 pinctrl-0 = <&backlight_pins>; 87 pinctrl-0 = <&backlight_pins>;
87 pinctrl-names = "default"; 88 pinctrl-names = "default";
88 }; 89 };
90
91 sound {
92 compatible = "simple-audio-card";
93
94 simple-audio-card,format = "i2s";
95
96 simple-audio-card,cpu {
97 sound-dai = <&sh_fsi2 0>;
98 bitclock-inversion;
99 };
100
101 simple-audio-card,codec {
102 sound-dai = <&wm8978>;
103 bitclock-master;
104 frame-master;
105 system-clock-frequency = <12288000>;
106 };
107 };
89}; 108};
90 109
91&i2c0 { 110&i2c0 {
92 status = "okay"; 111 status = "okay";
93 touchscreen: st1232@55 { 112 touchscreen@55 {
94 compatible = "sitronix,st1232"; 113 compatible = "sitronix,st1232";
95 reg = <0x55>; 114 reg = <0x55>;
96 interrupt-parent = <&irqpin1>; 115 interrupt-parent = <&irqpin1>;
97 interrupts = <2 0>; /* IRQ10: hwirq 2 on irqpin1 */ 116 interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
98 pinctrl-0 = <&st1232_pins>; 117 pinctrl-0 = <&st1232_pins>;
99 pinctrl-names = "default"; 118 pinctrl-names = "default";
100 gpios = <&pfc 166 GPIO_ACTIVE_LOW>; 119 gpios = <&pfc 166 GPIO_ACTIVE_LOW>;
101 }; 120 };
121
122 wm8978: wm8978@1a {
123 #sound-dai-cells = <0>;
124 compatible = "wlf,wm8978";
125 reg = <0x1a>;
126 };
102}; 127};
103 128
104&pfc { 129&pfc {
105 pinctrl-0 = <&scifa1_pins>; 130 pinctrl-0 = <&scifa1_pins>;
106 pinctrl-names = "default"; 131 pinctrl-names = "default";
107 132
108 scifa1_pins: scifa1 { 133 scifa1_pins: serial1 {
109 renesas,groups = "scifa1_data"; 134 renesas,groups = "scifa1_data";
110 renesas,function = "scifa1"; 135 renesas,function = "scifa1";
111 }; 136 };
112 137
113 st1232_pins: st1232 { 138 st1232_pins: touchscreen {
114 renesas,groups = "intc_irq10"; 139 renesas,groups = "intc_irq10";
115 renesas,function = "intc"; 140 renesas,function = "intc";
116 }; 141 };
@@ -125,10 +150,16 @@
125 renesas,function = "mmc0"; 150 renesas,function = "mmc0";
126 }; 151 };
127 152
128 sdhi0_pins: sdhi0 { 153 sdhi0_pins: sd0 {
129 renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_wp"; 154 renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_wp";
130 renesas,function = "sdhi0"; 155 renesas,function = "sdhi0";
131 }; 156 };
157
158 fsia_pins: sounda {
159 renesas,groups = "fsia_sclk_in", "fsia_mclk_out",
160 "fsia_data_in_1", "fsia_data_out_0";
161 renesas,function = "fsia";
162 };
132}; 163};
133 164
134&tpu { 165&tpu {
@@ -155,3 +186,10 @@
155 cd-gpios = <&pfc 167 GPIO_ACTIVE_LOW>; 186 cd-gpios = <&pfc 167 GPIO_ACTIVE_LOW>;
156 status = "okay"; 187 status = "okay";
157}; 188};
189
190&sh_fsi2 {
191 pinctrl-0 = <&fsia_pins>;
192 pinctrl-names = "default";
193
194 status = "okay";
195};
diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
index 426cd9c3e1c4..a06a11e1a840 100644
--- a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
+++ b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
@@ -9,7 +9,7 @@
9 */ 9 */
10 10
11/dts-v1/; 11/dts-v1/;
12/include/ "r8a7740.dtsi" 12#include "r8a7740.dtsi"
13 13
14/ { 14/ {
15 model = "armadillo 800 eva"; 15 model = "armadillo 800 eva";
diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
index ae1e230f711d..2782f642acfc 100644
--- a/arch/arm/boot/dts/r8a7740.dtsi
+++ b/arch/arm/boot/dts/r8a7740.dtsi
@@ -10,6 +10,8 @@
10 10
11/include/ "skeleton.dtsi" 11/include/ "skeleton.dtsi"
12 12
13#include <dt-bindings/interrupt-controller/irq.h>
14
13/ { 15/ {
14 compatible = "renesas,r8a7740"; 16 compatible = "renesas,r8a7740";
15 17
@@ -34,12 +36,12 @@
34 36
35 pmu { 37 pmu {
36 compatible = "arm,cortex-a9-pmu"; 38 compatible = "arm,cortex-a9-pmu";
37 interrupts = <0 83 4>; 39 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
38 }; 40 };
39 41
40 /* irqpin0: IRQ0 - IRQ7 */ 42 /* irqpin0: IRQ0 - IRQ7 */
41 irqpin0: irqpin@e6900000 { 43 irqpin0: irqpin@e6900000 {
42 compatible = "renesas,intc-irqpin"; 44 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
43 #interrupt-cells = <2>; 45 #interrupt-cells = <2>;
44 interrupt-controller; 46 interrupt-controller;
45 reg = <0xe6900000 4>, 47 reg = <0xe6900000 4>,
@@ -48,19 +50,19 @@
48 <0xe6900040 1>, 50 <0xe6900040 1>,
49 <0xe6900060 1>; 51 <0xe6900060 1>;
50 interrupt-parent = <&gic>; 52 interrupt-parent = <&gic>;
51 interrupts = <0 149 0x4 53 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH
52 0 149 0x4 54 0 149 IRQ_TYPE_LEVEL_HIGH
53 0 149 0x4 55 0 149 IRQ_TYPE_LEVEL_HIGH
54 0 149 0x4 56 0 149 IRQ_TYPE_LEVEL_HIGH
55 0 149 0x4 57 0 149 IRQ_TYPE_LEVEL_HIGH
56 0 149 0x4 58 0 149 IRQ_TYPE_LEVEL_HIGH
57 0 149 0x4 59 0 149 IRQ_TYPE_LEVEL_HIGH
58 0 149 0x4>; 60 0 149 IRQ_TYPE_LEVEL_HIGH>;
59 }; 61 };
60 62
61 /* irqpin1: IRQ8 - IRQ15 */ 63 /* irqpin1: IRQ8 - IRQ15 */
62 irqpin1: irqpin@e6900004 { 64 irqpin1: irqpin@e6900004 {
63 compatible = "renesas,intc-irqpin"; 65 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
64 #interrupt-cells = <2>; 66 #interrupt-cells = <2>;
65 interrupt-controller; 67 interrupt-controller;
66 reg = <0xe6900004 4>, 68 reg = <0xe6900004 4>,
@@ -69,19 +71,19 @@
69 <0xe6900044 1>, 71 <0xe6900044 1>,
70 <0xe6900064 1>; 72 <0xe6900064 1>;
71 interrupt-parent = <&gic>; 73 interrupt-parent = <&gic>;
72 interrupts = <0 149 0x4 74 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH
73 0 149 0x4 75 0 149 IRQ_TYPE_LEVEL_HIGH
74 0 149 0x4 76 0 149 IRQ_TYPE_LEVEL_HIGH
75 0 149 0x4 77 0 149 IRQ_TYPE_LEVEL_HIGH
76 0 149 0x4 78 0 149 IRQ_TYPE_LEVEL_HIGH
77 0 149 0x4 79 0 149 IRQ_TYPE_LEVEL_HIGH
78 0 149 0x4 80 0 149 IRQ_TYPE_LEVEL_HIGH
79 0 149 0x4>; 81 0 149 IRQ_TYPE_LEVEL_HIGH>;
80 }; 82 };
81 83
82 /* irqpin2: IRQ16 - IRQ23 */ 84 /* irqpin2: IRQ16 - IRQ23 */
83 irqpin2: irqpin@e6900008 { 85 irqpin2: irqpin@e6900008 {
84 compatible = "renesas,intc-irqpin"; 86 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
85 #interrupt-cells = <2>; 87 #interrupt-cells = <2>;
86 interrupt-controller; 88 interrupt-controller;
87 reg = <0xe6900008 4>, 89 reg = <0xe6900008 4>,
@@ -90,19 +92,19 @@
90 <0xe6900048 1>, 92 <0xe6900048 1>,
91 <0xe6900068 1>; 93 <0xe6900068 1>;
92 interrupt-parent = <&gic>; 94 interrupt-parent = <&gic>;
93 interrupts = <0 149 0x4 95 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH
94 0 149 0x4 96 0 149 IRQ_TYPE_LEVEL_HIGH
95 0 149 0x4 97 0 149 IRQ_TYPE_LEVEL_HIGH
96 0 149 0x4 98 0 149 IRQ_TYPE_LEVEL_HIGH
97 0 149 0x4 99 0 149 IRQ_TYPE_LEVEL_HIGH
98 0 149 0x4 100 0 149 IRQ_TYPE_LEVEL_HIGH
99 0 149 0x4 101 0 149 IRQ_TYPE_LEVEL_HIGH
100 0 149 0x4>; 102 0 149 IRQ_TYPE_LEVEL_HIGH>;
101 }; 103 };
102 104
103 /* irqpin3: IRQ24 - IRQ31 */ 105 /* irqpin3: IRQ24 - IRQ31 */
104 irqpin3: irqpin@e690000c { 106 irqpin3: irqpin@e690000c {
105 compatible = "renesas,intc-irqpin"; 107 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
106 #interrupt-cells = <2>; 108 #interrupt-cells = <2>;
107 interrupt-controller; 109 interrupt-controller;
108 reg = <0xe690000c 4>, 110 reg = <0xe690000c 4>,
@@ -111,14 +113,14 @@
111 <0xe690004c 1>, 113 <0xe690004c 1>,
112 <0xe690006c 1>; 114 <0xe690006c 1>;
113 interrupt-parent = <&gic>; 115 interrupt-parent = <&gic>;
114 interrupts = <0 149 0x4 116 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH
115 0 149 0x4 117 0 149 IRQ_TYPE_LEVEL_HIGH
116 0 149 0x4 118 0 149 IRQ_TYPE_LEVEL_HIGH
117 0 149 0x4 119 0 149 IRQ_TYPE_LEVEL_HIGH
118 0 149 0x4 120 0 149 IRQ_TYPE_LEVEL_HIGH
119 0 149 0x4 121 0 149 IRQ_TYPE_LEVEL_HIGH
120 0 149 0x4 122 0 149 IRQ_TYPE_LEVEL_HIGH
121 0 149 0x4>; 123 0 149 IRQ_TYPE_LEVEL_HIGH>;
122 }; 124 };
123 125
124 i2c0: i2c@fff20000 { 126 i2c0: i2c@fff20000 {
@@ -127,10 +129,10 @@
127 compatible = "renesas,rmobile-iic"; 129 compatible = "renesas,rmobile-iic";
128 reg = <0xfff20000 0x425>; 130 reg = <0xfff20000 0x425>;
129 interrupt-parent = <&gic>; 131 interrupt-parent = <&gic>;
130 interrupts = <0 201 0x4 132 interrupts = <0 201 IRQ_TYPE_LEVEL_HIGH
131 0 202 0x4 133 0 202 IRQ_TYPE_LEVEL_HIGH
132 0 203 0x4 134 0 203 IRQ_TYPE_LEVEL_HIGH
133 0 204 0x4>; 135 0 204 IRQ_TYPE_LEVEL_HIGH>;
134 status = "disabled"; 136 status = "disabled";
135 }; 137 };
136 138
@@ -140,10 +142,10 @@
140 compatible = "renesas,rmobile-iic"; 142 compatible = "renesas,rmobile-iic";
141 reg = <0xe6c20000 0x425>; 143 reg = <0xe6c20000 0x425>;
142 interrupt-parent = <&gic>; 144 interrupt-parent = <&gic>;
143 interrupts = <0 70 0x4 145 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH
144 0 71 0x4 146 0 71 IRQ_TYPE_LEVEL_HIGH
145 0 72 0x4 147 0 72 IRQ_TYPE_LEVEL_HIGH
146 0 73 0x4>; 148 0 73 IRQ_TYPE_LEVEL_HIGH>;
147 status = "disabled"; 149 status = "disabled";
148 }; 150 };
149 151
@@ -162,36 +164,57 @@
162 #pwm-cells = <3>; 164 #pwm-cells = <3>;
163 }; 165 };
164 166
165 mmcif0: mmcif@e6bd0000 { 167 mmcif0: mmc@e6bd0000 {
166 compatible = "renesas,sh-mmcif"; 168 compatible = "renesas,sh-mmcif";
167 reg = <0xe6bd0000 0x100>; 169 reg = <0xe6bd0000 0x100>;
168 interrupt-parent = <&gic>; 170 interrupt-parent = <&gic>;
169 interrupts = <0 56 4 171 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH
170 0 57 4>; 172 0 57 IRQ_TYPE_LEVEL_HIGH>;
171 status = "disabled"; 173 status = "disabled";
172 }; 174 };
173 175
174 sdhi0: sdhi@e6850000 { 176 sdhi0: sd@e6850000 {
175 compatible = "renesas,sdhi-r8a7740"; 177 compatible = "renesas,sdhi-r8a7740";
176 reg = <0xe6850000 0x100>; 178 reg = <0xe6850000 0x100>;
177 interrupt-parent = <&gic>; 179 interrupt-parent = <&gic>;
178 interrupts = <0 117 4 180 interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH
179 0 118 4 181 0 118 IRQ_TYPE_LEVEL_HIGH
180 0 119 4>; 182 0 119 IRQ_TYPE_LEVEL_HIGH>;
181 cap-sd-highspeed; 183 cap-sd-highspeed;
182 cap-sdio-irq; 184 cap-sdio-irq;
183 status = "disabled"; 185 status = "disabled";
184 }; 186 };
185 187
186 sdhi1: sdhi@e6860000 { 188 sdhi1: sd@e6860000 {
187 compatible = "renesas,sdhi-r8a7740"; 189 compatible = "renesas,sdhi-r8a7740";
188 reg = <0xe6860000 0x100>; 190 reg = <0xe6860000 0x100>;
189 interrupt-parent = <&gic>; 191 interrupt-parent = <&gic>;
190 interrupts = <0 121 4 192 interrupts = <0 121 IRQ_TYPE_LEVEL_HIGH
191 0 122 4 193 0 122 IRQ_TYPE_LEVEL_HIGH
192 0 123 4>; 194 0 123 IRQ_TYPE_LEVEL_HIGH>;
195 cap-sd-highspeed;
196 cap-sdio-irq;
197 status = "disabled";
198 };
199
200 sdhi2: sd@e6870000 {
201 compatible = "renesas,sdhi-r8a7740";
202 reg = <0xe6870000 0x100>;
203 interrupt-parent = <&gic>;
204 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH
205 0 126 IRQ_TYPE_LEVEL_HIGH
206 0 127 IRQ_TYPE_LEVEL_HIGH>;
193 cap-sd-highspeed; 207 cap-sd-highspeed;
194 cap-sdio-irq; 208 cap-sdio-irq;
195 status = "disabled"; 209 status = "disabled";
196 }; 210 };
211
212 sh_fsi2: sound@fe1f0000 {
213 #sound-dai-cells = <1>;
214 compatible = "renesas,sh_fsi2";
215 reg = <0xfe1f0000 0x400>;
216 interrupt-parent = <&gic>;
217 interrupts = <0 9 0x4>;
218 status = "disabled";
219 };
197}; 220};
diff --git a/arch/arm/boot/dts/r8a7778-bockw-reference.dts b/arch/arm/boot/dts/r8a7778-bockw-reference.dts
index 969e386e852c..bb62c7a906f4 100644
--- a/arch/arm/boot/dts/r8a7778-bockw-reference.dts
+++ b/arch/arm/boot/dts/r8a7778-bockw-reference.dts
@@ -15,7 +15,8 @@
15 */ 15 */
16 16
17/dts-v1/; 17/dts-v1/;
18/include/ "r8a7778.dtsi" 18#include "r8a7778.dtsi"
19#include <dt-bindings/interrupt-controller/irq.h>
19 20
20/ { 21/ {
21 model = "bockw"; 22 model = "bockw";
@@ -45,13 +46,65 @@
45 46
46 phy-mode = "mii"; 47 phy-mode = "mii";
47 interrupt-parent = <&irqpin>; 48 interrupt-parent = <&irqpin>;
48 interrupts = <0 0>; /* IRQ0: hwirq 0 on irqpin */ 49 interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
49 reg-io-width = <4>; 50 reg-io-width = <4>;
50 vddvario-supply = <&fixedregulator3v3>; 51 vddvario-supply = <&fixedregulator3v3>;
51 vdd33a-supply = <&fixedregulator3v3>; 52 vdd33a-supply = <&fixedregulator3v3>;
52 }; 53 };
54
55};
56
57&mmcif {
58 pinctrl-0 = <&mmc_pins>;
59 pinctrl-names = "default";
60
61 vmmc-supply = <&fixedregulator3v3>;
62 bus-width = <8>;
63 broken-cd;
64 status = "okay";
53}; 65};
54 66
55&irqpin { 67&irqpin {
56 status = "okay"; 68 status = "okay";
57}; 69};
70
71&pfc {
72 pinctrl-0 = <&scif0_pins>;
73 pinctrl-names = "default";
74
75 scif0_pins: serial0 {
76 renesas,groups = "scif0_data_a", "scif0_ctrl";
77 renesas,function = "scif0";
78 };
79
80 mmc_pins: mmc {
81 renesas,groups = "mmc_data8", "mmc_ctrl";
82 renesas,function = "mmc";
83 };
84
85 sdhi0_pins: sd0 {
86 renesas,groups = "sdhi0_data4", "sdhi0_ctrl",
87 "sdhi0_cd", "sdhi0_wp";
88 renesas,function = "sdhi0";
89 };
90
91 hspi0_pins: hspi0 {
92 renesas,groups = "hspi0_a";
93 renesas,function = "hspi0";
94 };
95};
96
97&sdhi0 {
98 pinctrl-0 = <&sdhi0_pins>;
99 pinctrl-names = "default";
100
101 vmmc-supply = <&fixedregulator3v3>;
102 bus-width = <4>;
103 status = "okay";
104};
105
106&hspi0 {
107 pinctrl-0 = <&hspi0_pins>;
108 pinctrl-names = "default";
109 status = "okay";
110};
diff --git a/arch/arm/boot/dts/r8a7778-bockw.dts b/arch/arm/boot/dts/r8a7778-bockw.dts
index 12bbebc9c955..46a884d45175 100644
--- a/arch/arm/boot/dts/r8a7778-bockw.dts
+++ b/arch/arm/boot/dts/r8a7778-bockw.dts
@@ -15,7 +15,7 @@
15 */ 15 */
16 16
17/dts-v1/; 17/dts-v1/;
18/include/ "r8a7778.dtsi" 18#include "r8a7778.dtsi"
19 19
20/ { 20/ {
21 model = "bockw"; 21 model = "bockw";
diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi
index a6308a399e2d..ddb3bd7a8838 100644
--- a/arch/arm/boot/dts/r8a7778.dtsi
+++ b/arch/arm/boot/dts/r8a7778.dtsi
@@ -16,6 +16,8 @@
16 16
17/include/ "skeleton.dtsi" 17/include/ "skeleton.dtsi"
18 18
19#include <dt-bindings/interrupt-controller/irq.h>
20
19/ { 21/ {
20 compatible = "renesas,r8a7778"; 22 compatible = "renesas,r8a7778";
21 23
@@ -25,6 +27,12 @@
25 }; 27 };
26 }; 28 };
27 29
30 aliases {
31 spi0 = &hspi0;
32 spi1 = &hspi1;
33 spi2 = &hspi2;
34 };
35
28 gic: interrupt-controller@fe438000 { 36 gic: interrupt-controller@fe438000 {
29 compatible = "arm,cortex-a9-gic"; 37 compatible = "arm,cortex-a9-gic";
30 #interrupt-cells = <3>; 38 #interrupt-cells = <3>;
@@ -35,7 +43,7 @@
35 43
36 /* irqpin: IRQ0 - IRQ3 */ 44 /* irqpin: IRQ0 - IRQ3 */
37 irqpin: irqpin@fe78001c { 45 irqpin: irqpin@fe78001c {
38 compatible = "renesas,intc-irqpin"; 46 compatible = "renesas,intc-irqpin-r8a7778", "renesas,intc-irqpin";
39 #interrupt-cells = <2>; 47 #interrupt-cells = <2>;
40 interrupt-controller; 48 interrupt-controller;
41 status = "disabled"; /* default off */ 49 status = "disabled"; /* default off */
@@ -45,10 +53,10 @@
45 <0xfe780044 4>, 53 <0xfe780044 4>,
46 <0xfe780064 4>; 54 <0xfe780064 4>;
47 interrupt-parent = <&gic>; 55 interrupt-parent = <&gic>;
48 interrupts = <0 27 0x4 56 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH
49 0 28 0x4 57 0 28 IRQ_TYPE_LEVEL_HIGH
50 0 29 0x4 58 0 29 IRQ_TYPE_LEVEL_HIGH
51 0 30 0x4>; 59 0 30 IRQ_TYPE_LEVEL_HIGH>;
52 sense-bitfield-width = <2>; 60 sense-bitfield-width = <2>;
53 }; 61 };
54 62
@@ -56,7 +64,7 @@
56 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; 64 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
57 reg = <0xffc40000 0x2c>; 65 reg = <0xffc40000 0x2c>;
58 interrupt-parent = <&gic>; 66 interrupt-parent = <&gic>;
59 interrupts = <0 103 0x4>; 67 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
60 #gpio-cells = <2>; 68 #gpio-cells = <2>;
61 gpio-controller; 69 gpio-controller;
62 gpio-ranges = <&pfc 0 0 32>; 70 gpio-ranges = <&pfc 0 0 32>;
@@ -68,7 +76,7 @@
68 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; 76 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
69 reg = <0xffc41000 0x2c>; 77 reg = <0xffc41000 0x2c>;
70 interrupt-parent = <&gic>; 78 interrupt-parent = <&gic>;
71 interrupts = <0 103 0x4>; 79 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
72 #gpio-cells = <2>; 80 #gpio-cells = <2>;
73 gpio-controller; 81 gpio-controller;
74 gpio-ranges = <&pfc 0 32 32>; 82 gpio-ranges = <&pfc 0 32 32>;
@@ -80,7 +88,7 @@
80 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; 88 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
81 reg = <0xffc42000 0x2c>; 89 reg = <0xffc42000 0x2c>;
82 interrupt-parent = <&gic>; 90 interrupt-parent = <&gic>;
83 interrupts = <0 103 0x4>; 91 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
84 #gpio-cells = <2>; 92 #gpio-cells = <2>;
85 gpio-controller; 93 gpio-controller;
86 gpio-ranges = <&pfc 0 64 32>; 94 gpio-ranges = <&pfc 0 64 32>;
@@ -92,7 +100,7 @@
92 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; 100 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
93 reg = <0xffc43000 0x2c>; 101 reg = <0xffc43000 0x2c>;
94 interrupt-parent = <&gic>; 102 interrupt-parent = <&gic>;
95 interrupts = <0 103 0x4>; 103 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
96 #gpio-cells = <2>; 104 #gpio-cells = <2>;
97 gpio-controller; 105 gpio-controller;
98 gpio-ranges = <&pfc 0 96 32>; 106 gpio-ranges = <&pfc 0 96 32>;
@@ -104,7 +112,7 @@
104 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; 112 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
105 reg = <0xffc44000 0x2c>; 113 reg = <0xffc44000 0x2c>;
106 interrupt-parent = <&gic>; 114 interrupt-parent = <&gic>;
107 interrupts = <0 103 0x4>; 115 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
108 #gpio-cells = <2>; 116 #gpio-cells = <2>;
109 gpio-controller; 117 gpio-controller;
110 gpio-ranges = <&pfc 0 128 27>; 118 gpio-ranges = <&pfc 0 128 27>;
@@ -114,6 +122,148 @@
114 122
115 pfc: pfc@fffc0000 { 123 pfc: pfc@fffc0000 {
116 compatible = "renesas,pfc-r8a7778"; 124 compatible = "renesas,pfc-r8a7778";
117 reg = <0xfffc000 0x118>; 125 reg = <0xfffc0000 0x118>;
126 };
127
128 i2c0: i2c@ffc70000 {
129 #address-cells = <1>;
130 #size-cells = <0>;
131 compatible = "renesas,i2c-r8a7778";
132 reg = <0xffc70000 0x1000>;
133 interrupt-parent = <&gic>;
134 interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
135 status = "disabled";
136 };
137
138 i2c1: i2c@ffc71000 {
139 #address-cells = <1>;
140 #size-cells = <0>;
141 compatible = "renesas,i2c-r8a7778";
142 reg = <0xffc71000 0x1000>;
143 interrupt-parent = <&gic>;
144 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
145 status = "disabled";
146 };
147
148 i2c2: i2c@ffc72000 {
149 #address-cells = <1>;
150 #size-cells = <0>;
151 compatible = "renesas,i2c-r8a7778";
152 reg = <0xffc72000 0x1000>;
153 interrupt-parent = <&gic>;
154 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>;
155 status = "disabled";
156 };
157
158 i2c3: i2c@ffc73000 {
159 #address-cells = <1>;
160 #size-cells = <0>;
161 compatible = "renesas,i2c-r8a7778";
162 reg = <0xffc73000 0x1000>;
163 interrupt-parent = <&gic>;
164 interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>;
165 status = "disabled";
166 };
167
168 mmcif: mmc@ffe4e000 {
169 compatible = "renesas,sh-mmcif";
170 reg = <0xffe4e000 0x100>;
171 interrupt-parent = <&gic>;
172 interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>;
173 status = "disabled";
174 };
175
176 sdhi0: sd@ffe4c000 {
177 compatible = "renesas,sdhi-r8a7778";
178 reg = <0xffe4c000 0x100>;
179 interrupt-parent = <&gic>;
180 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>;
181 cap-sd-highspeed;
182 cap-sdio-irq;
183 status = "disabled";
184 };
185
186 sdhi1: sd@ffe4d000 {
187 compatible = "renesas,sdhi-r8a7778";
188 reg = <0xffe4d000 0x100>;
189 interrupt-parent = <&gic>;
190 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
191 cap-sd-highspeed;
192 cap-sdio-irq;
193 status = "disabled";
194 };
195
196 sdhi2: sd@ffe4f000 {
197 compatible = "renesas,sdhi-r8a7778";
198 reg = <0xffe4f000 0x100>;
199 interrupt-parent = <&gic>;
200 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
201 cap-sd-highspeed;
202 cap-sdio-irq;
203 status = "disabled";
204 };
205
206 i2c0: i2c@ffc70000 {
207 #address-cells = <1>;
208 #size-cells = <0>;
209 compatible = "renesas,i2c-r8a7778";
210 reg = <0xffc70000 0x1000>;
211 interrupt-parent = <&gic>;
212 interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
213 status = "disabled";
214 };
215
216 i2c1: i2c@ffc71000 {
217 #address-cells = <1>;
218 #size-cells = <0>;
219 compatible = "renesas,i2c-r8a7778";
220 reg = <0xffc71000 0x1000>;
221 interrupt-parent = <&gic>;
222 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
223 status = "disabled";
224 };
225
226 i2c2: i2c@ffc72000 {
227 #address-cells = <1>;
228 #size-cells = <0>;
229 compatible = "renesas,i2c-r8a7778";
230 reg = <0xffc72000 0x1000>;
231 interrupt-parent = <&gic>;
232 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>;
233 status = "disabled";
234 };
235
236 i2c3: i2c@ffc73000 {
237 #address-cells = <1>;
238 #size-cells = <0>;
239 compatible = "renesas,i2c-r8a7778";
240 reg = <0xffc73000 0x1000>;
241 interrupt-parent = <&gic>;
242 interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>;
243 status = "disabled";
244 };
245
246 hspi0: spi@fffc7000 {
247 compatible = "renesas,hspi";
248 reg = <0xfffc7000 0x18>;
249 interrupt-controller = <&gic>;
250 interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
251 status = "disabled";
252 };
253
254 hspi1: spi@fffc8000 {
255 compatible = "renesas,hspi";
256 reg = <0xfffc8000 0x18>;
257 interrupt-controller = <&gic>;
258 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
259 status = "disabled";
260 };
261
262 hspi2: spi@fffc6000 {
263 compatible = "renesas,hspi";
264 reg = <0xfffc6000 0x18>;
265 interrupt-controller = <&gic>;
266 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
267 status = "disabled";
118 }; 268 };
119}; 269};
diff --git a/arch/arm/boot/dts/r8a7779-marzen-reference.dts b/arch/arm/boot/dts/r8a7779-marzen-reference.dts
index ab4110aa3c3b..76f5eef7d1cc 100644
--- a/arch/arm/boot/dts/r8a7779-marzen-reference.dts
+++ b/arch/arm/boot/dts/r8a7779-marzen-reference.dts
@@ -10,8 +10,9 @@
10 */ 10 */
11 11
12/dts-v1/; 12/dts-v1/;
13/include/ "r8a7779.dtsi" 13#include "r8a7779.dtsi"
14#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/gpio/gpio.h>
15#include <dt-bindings/interrupt-controller/irq.h>
15 16
16/ { 17/ {
17 model = "marzen"; 18 model = "marzen";
@@ -43,7 +44,7 @@
43 44
44 phy-mode = "mii"; 45 phy-mode = "mii";
45 interrupt-parent = <&irqpin0>; 46 interrupt-parent = <&irqpin0>;
46 interrupts = <1 0>; /* IRQ1: hwirq 1 on irqpin0 */ 47 interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
47 reg-io-width = <4>; 48 reg-io-width = <4>;
48 vddvario-supply = <&fixedregulator3v3>; 49 vddvario-supply = <&fixedregulator3v3>;
49 vdd33a-supply = <&fixedregulator3v3>; 50 vdd33a-supply = <&fixedregulator3v3>;
@@ -68,7 +69,7 @@
68}; 69};
69 70
70&pfc { 71&pfc {
71 pinctrl-0 = <&scif2_pins &scif4_pins &sdhi0_pins>; 72 pinctrl-0 = <&scif2_pins &scif4_pins>;
72 pinctrl-names = "default"; 73 pinctrl-names = "default";
73 74
74 lan0_pins: lan0 { 75 lan0_pins: lan0 {
@@ -82,19 +83,38 @@
82 }; 83 };
83 }; 84 };
84 85
85 scif2_pins: scif2 { 86 scif2_pins: serial2 {
86 renesas,groups = "scif2_data_c"; 87 renesas,groups = "scif2_data_c";
87 renesas,function = "scif2"; 88 renesas,function = "scif2";
88 }; 89 };
89 90
90 scif4_pins: scif4 { 91 scif4_pins: serial4 {
91 renesas,groups = "scif4_data"; 92 renesas,groups = "scif4_data";
92 renesas,function = "scif4"; 93 renesas,function = "scif4";
93 }; 94 };
94 95
95 sdhi0_pins: sdhi0 { 96 sdhi0_pins: sd0 {
96 renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd", 97 renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";
97 "sdhi0_wp";
98 renesas,function = "sdhi0"; 98 renesas,function = "sdhi0";
99 }; 99 };
100
101 hspi0_pins: hspi0 {
102 renesas,groups = "hspi0";
103 renesas,function = "hspi0";
104 };
105};
106
107&sdhi0 {
108 pinctrl-0 = <&sdhi0_pins>;
109 pinctrl-names = "default";
110
111 vmmc-supply = <&fixedregulator3v3>;
112 bus-width = <4>;
113 status = "okay";
114};
115
116&hspi0 {
117 pinctrl-0 = <&hspi0_pins>;
118 pinctrl-names = "default";
119 status = "okay";
100}; 120};
diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts
index f3f7f7999736..a7af2c2371f2 100644
--- a/arch/arm/boot/dts/r8a7779-marzen.dts
+++ b/arch/arm/boot/dts/r8a7779-marzen.dts
@@ -10,7 +10,7 @@
10 */ 10 */
11 11
12/dts-v1/; 12/dts-v1/;
13/include/ "r8a7779.dtsi" 13#include "r8a7779.dtsi"
14 14
15/ { 15/ {
16 model = "marzen"; 16 model = "marzen";
diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index 19faeac3fd2e..d0561d4c7c46 100644
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -11,6 +11,8 @@
11 11
12/include/ "skeleton.dtsi" 12/include/ "skeleton.dtsi"
13 13
14#include <dt-bindings/interrupt-controller/irq.h>
15
14/ { 16/ {
15 compatible = "renesas,r8a7779"; 17 compatible = "renesas,r8a7779";
16 18
@@ -40,6 +42,12 @@
40 }; 42 };
41 }; 43 };
42 44
45 aliases {
46 spi0 = &hspi0;
47 spi1 = &hspi1;
48 spi2 = &hspi2;
49 };
50
43 gic: interrupt-controller@f0001000 { 51 gic: interrupt-controller@f0001000 {
44 compatible = "arm,cortex-a9-gic"; 52 compatible = "arm,cortex-a9-gic";
45 #interrupt-cells = <3>; 53 #interrupt-cells = <3>;
@@ -52,7 +60,7 @@
52 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; 60 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
53 reg = <0xffc40000 0x2c>; 61 reg = <0xffc40000 0x2c>;
54 interrupt-parent = <&gic>; 62 interrupt-parent = <&gic>;
55 interrupts = <0 141 0x4>; 63 interrupts = <0 141 IRQ_TYPE_LEVEL_HIGH>;
56 #gpio-cells = <2>; 64 #gpio-cells = <2>;
57 gpio-controller; 65 gpio-controller;
58 gpio-ranges = <&pfc 0 0 32>; 66 gpio-ranges = <&pfc 0 0 32>;
@@ -64,7 +72,7 @@
64 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; 72 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
65 reg = <0xffc41000 0x2c>; 73 reg = <0xffc41000 0x2c>;
66 interrupt-parent = <&gic>; 74 interrupt-parent = <&gic>;
67 interrupts = <0 142 0x4>; 75 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>;
68 #gpio-cells = <2>; 76 #gpio-cells = <2>;
69 gpio-controller; 77 gpio-controller;
70 gpio-ranges = <&pfc 0 32 32>; 78 gpio-ranges = <&pfc 0 32 32>;
@@ -76,7 +84,7 @@
76 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; 84 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
77 reg = <0xffc42000 0x2c>; 85 reg = <0xffc42000 0x2c>;
78 interrupt-parent = <&gic>; 86 interrupt-parent = <&gic>;
79 interrupts = <0 143 0x4>; 87 interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>;
80 #gpio-cells = <2>; 88 #gpio-cells = <2>;
81 gpio-controller; 89 gpio-controller;
82 gpio-ranges = <&pfc 0 64 32>; 90 gpio-ranges = <&pfc 0 64 32>;
@@ -88,7 +96,7 @@
88 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; 96 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
89 reg = <0xffc43000 0x2c>; 97 reg = <0xffc43000 0x2c>;
90 interrupt-parent = <&gic>; 98 interrupt-parent = <&gic>;
91 interrupts = <0 144 0x4>; 99 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
92 #gpio-cells = <2>; 100 #gpio-cells = <2>;
93 gpio-controller; 101 gpio-controller;
94 gpio-ranges = <&pfc 0 96 32>; 102 gpio-ranges = <&pfc 0 96 32>;
@@ -100,7 +108,7 @@
100 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; 108 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
101 reg = <0xffc44000 0x2c>; 109 reg = <0xffc44000 0x2c>;
102 interrupt-parent = <&gic>; 110 interrupt-parent = <&gic>;
103 interrupts = <0 145 0x4>; 111 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
104 #gpio-cells = <2>; 112 #gpio-cells = <2>;
105 gpio-controller; 113 gpio-controller;
106 gpio-ranges = <&pfc 0 128 32>; 114 gpio-ranges = <&pfc 0 128 32>;
@@ -112,7 +120,7 @@
112 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; 120 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
113 reg = <0xffc45000 0x2c>; 121 reg = <0xffc45000 0x2c>;
114 interrupt-parent = <&gic>; 122 interrupt-parent = <&gic>;
115 interrupts = <0 146 0x4>; 123 interrupts = <0 146 IRQ_TYPE_LEVEL_HIGH>;
116 #gpio-cells = <2>; 124 #gpio-cells = <2>;
117 gpio-controller; 125 gpio-controller;
118 gpio-ranges = <&pfc 0 160 32>; 126 gpio-ranges = <&pfc 0 160 32>;
@@ -124,7 +132,7 @@
124 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; 132 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
125 reg = <0xffc46000 0x2c>; 133 reg = <0xffc46000 0x2c>;
126 interrupt-parent = <&gic>; 134 interrupt-parent = <&gic>;
127 interrupts = <0 147 0x4>; 135 interrupts = <0 147 IRQ_TYPE_LEVEL_HIGH>;
128 #gpio-cells = <2>; 136 #gpio-cells = <2>;
129 gpio-controller; 137 gpio-controller;
130 gpio-ranges = <&pfc 0 192 9>; 138 gpio-ranges = <&pfc 0 192 9>;
@@ -133,7 +141,7 @@
133 }; 141 };
134 142
135 irqpin0: irqpin@fe780010 { 143 irqpin0: irqpin@fe780010 {
136 compatible = "renesas,intc-irqpin"; 144 compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin";
137 #interrupt-cells = <2>; 145 #interrupt-cells = <2>;
138 status = "disabled"; 146 status = "disabled";
139 interrupt-controller; 147 interrupt-controller;
@@ -143,50 +151,50 @@
143 <0xfe780044 4>, 151 <0xfe780044 4>,
144 <0xfe780064 4>; 152 <0xfe780064 4>;
145 interrupt-parent = <&gic>; 153 interrupt-parent = <&gic>;
146 interrupts = <0 27 0x4 154 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH
147 0 28 0x4 155 0 28 IRQ_TYPE_LEVEL_HIGH
148 0 29 0x4 156 0 29 IRQ_TYPE_LEVEL_HIGH
149 0 30 0x4>; 157 0 30 IRQ_TYPE_LEVEL_HIGH>;
150 sense-bitfield-width = <2>; 158 sense-bitfield-width = <2>;
151 }; 159 };
152 160
153 i2c0: i2c@ffc70000 { 161 i2c0: i2c@ffc70000 {
154 #address-cells = <1>; 162 #address-cells = <1>;
155 #size-cells = <0>; 163 #size-cells = <0>;
156 compatible = "renesas,rmobile-iic"; 164 compatible = "renesas,i2c-r8a7779";
157 reg = <0xffc70000 0x1000>; 165 reg = <0xffc70000 0x1000>;
158 interrupt-parent = <&gic>; 166 interrupt-parent = <&gic>;
159 interrupts = <0 79 0x4>; 167 interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
160 status = "disabled"; 168 status = "disabled";
161 }; 169 };
162 170
163 i2c1: i2c@ffc71000 { 171 i2c1: i2c@ffc71000 {
164 #address-cells = <1>; 172 #address-cells = <1>;
165 #size-cells = <0>; 173 #size-cells = <0>;
166 compatible = "renesas,rmobile-iic"; 174 compatible = "renesas,i2c-r8a7779";
167 reg = <0xffc71000 0x1000>; 175 reg = <0xffc71000 0x1000>;
168 interrupt-parent = <&gic>; 176 interrupt-parent = <&gic>;
169 interrupts = <0 82 0x4>; 177 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
170 status = "disabled"; 178 status = "disabled";
171 }; 179 };
172 180
173 i2c2: i2c@ffc72000 { 181 i2c2: i2c@ffc72000 {
174 #address-cells = <1>; 182 #address-cells = <1>;
175 #size-cells = <0>; 183 #size-cells = <0>;
176 compatible = "renesas,rmobile-iic"; 184 compatible = "renesas,i2c-r8a7779";
177 reg = <0xffc72000 0x1000>; 185 reg = <0xffc72000 0x1000>;
178 interrupt-parent = <&gic>; 186 interrupt-parent = <&gic>;
179 interrupts = <0 80 0x4>; 187 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
180 status = "disabled"; 188 status = "disabled";
181 }; 189 };
182 190
183 i2c3: i2c@ffc73000 { 191 i2c3: i2c@ffc73000 {
184 #address-cells = <1>; 192 #address-cells = <1>;
185 #size-cells = <0>; 193 #size-cells = <0>;
186 compatible = "renesas,rmobile-iic"; 194 compatible = "renesas,i2c-r8a7779";
187 reg = <0xffc73000 0x1000>; 195 reg = <0xffc73000 0x1000>;
188 interrupt-parent = <&gic>; 196 interrupt-parent = <&gic>;
189 interrupts = <0 81 0x4>; 197 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
190 status = "disabled"; 198 status = "disabled";
191 }; 199 };
192 200
@@ -204,6 +212,70 @@
204 compatible = "renesas,rcar-sata"; 212 compatible = "renesas,rcar-sata";
205 reg = <0xfc600000 0x2000>; 213 reg = <0xfc600000 0x2000>;
206 interrupt-parent = <&gic>; 214 interrupt-parent = <&gic>;
207 interrupts = <0 100 0x4>; 215 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
216 };
217
218 sdhi0: sd@ffe4c000 {
219 compatible = "renesas,sdhi-r8a7779";
220 reg = <0xffe4c000 0x100>;
221 interrupt-parent = <&gic>;
222 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
223 cap-sd-highspeed;
224 cap-sdio-irq;
225 status = "disabled";
226 };
227
228 sdhi1: sd@ffe4d000 {
229 compatible = "renesas,sdhi-r8a7779";
230 reg = <0xffe4d000 0x100>;
231 interrupt-parent = <&gic>;
232 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
233 cap-sd-highspeed;
234 cap-sdio-irq;
235 status = "disabled";
236 };
237
238 sdhi2: sd@ffe4e000 {
239 compatible = "renesas,sdhi-r8a7779";
240 reg = <0xffe4e000 0x100>;
241 interrupt-parent = <&gic>;
242 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
243 cap-sd-highspeed;
244 cap-sdio-irq;
245 status = "disabled";
246 };
247
248 sdhi3: sd@ffe4f000 {
249 compatible = "renesas,sdhi-r8a7779";
250 reg = <0xffe4f000 0x100>;
251 interrupt-parent = <&gic>;
252 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
253 cap-sd-highspeed;
254 cap-sdio-irq;
255 status = "disabled";
256 };
257
258 hspi0: spi@fffc7000 {
259 compatible = "renesas,hspi";
260 reg = <0xfffc7000 0x18>;
261 interrupt-controller = <&gic>;
262 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
263 status = "disabled";
264 };
265
266 hspi1: spi@fffc8000 {
267 compatible = "renesas,hspi";
268 reg = <0xfffc8000 0x18>;
269 interrupt-controller = <&gic>;
270 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
271 status = "disabled";
272 };
273
274 hspi2: spi@fffc6000 {
275 compatible = "renesas,hspi";
276 reg = <0xfffc6000 0x18>;
277 interrupt-controller = <&gic>;
278 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
279 status = "disabled";
208 }; 280 };
209}; 281};
diff --git a/arch/arm/boot/dts/r8a7790-lager-reference.dts b/arch/arm/boot/dts/r8a7790-lager-reference.dts
index c462ef138922..dfedc0ea82e1 100644
--- a/arch/arm/boot/dts/r8a7790-lager-reference.dts
+++ b/arch/arm/boot/dts/r8a7790-lager-reference.dts
@@ -9,7 +9,7 @@
9 */ 9 */
10 10
11/dts-v1/; 11/dts-v1/;
12/include/ "r8a7790.dtsi" 12#include "r8a7790.dtsi"
13#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/gpio/gpio.h>
14 14
15/ { 15/ {
@@ -25,6 +25,11 @@
25 reg = <0 0x40000000 0 0x80000000>; 25 reg = <0 0x40000000 0 0x80000000>;
26 }; 26 };
27 27
28 memory@180000000 {
29 device_type = "memory";
30 reg = <1 0x80000000 0 0x80000000>;
31 };
32
28 lbsc { 33 lbsc {
29 #address-cells = <1>; 34 #address-cells = <1>;
30 #size-cells = <1>; 35 #size-cells = <1>;
@@ -42,4 +47,43 @@
42 gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; 47 gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
43 }; 48 };
44 }; 49 };
50
51 fixedregulator3v3: fixedregulator@0 {
52 compatible = "regulator-fixed";
53 regulator-name = "fixed-3.3V";
54 regulator-min-microvolt = <3300000>;
55 regulator-max-microvolt = <3300000>;
56 regulator-boot-on;
57 regulator-always-on;
58 };
59};
60
61&pfc {
62 pinctrl-0 = <&scif0_pins &scif1_pins>;
63 pinctrl-names = "default";
64
65 scif0_pins: serial0 {
66 renesas,groups = "scif0_data";
67 renesas,function = "scif0";
68 };
69
70 scif1_pins: serial1 {
71 renesas,groups = "scif1_data";
72 renesas,function = "scif1";
73 };
74
75 mmc1_pins: mmc1 {
76 renesas,groups = "mmc1_data8", "mmc1_ctrl";
77 renesas,function = "mmc1";
78 };
79};
80
81&mmcif1 {
82 pinctrl-0 = <&mmc1_pins>;
83 pinctrl-names = "default";
84
85 vmmc-supply = <&fixedregulator3v3>;
86 bus-width = <8>;
87 non-removable;
88 status = "okay";
45}; 89};
diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index 203bd089af29..10e6a08164e5 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -9,7 +9,7 @@
9 */ 9 */
10 10
11/dts-v1/; 11/dts-v1/;
12/include/ "r8a7790.dtsi" 12#include "r8a7790.dtsi"
13 13
14/ { 14/ {
15 model = "Lager"; 15 model = "Lager";
@@ -24,6 +24,11 @@
24 reg = <0 0x40000000 0 0x80000000>; 24 reg = <0 0x40000000 0 0x80000000>;
25 }; 25 };
26 26
27 memory@180000000 {
28 device_type = "memory";
29 reg = <1 0x80000000 0 0x80000000>;
30 };
31
27 lbsc { 32 lbsc {
28 #address-cells = <1>; 33 #address-cells = <1>;
29 #size-cells = <1>; 34 #size-cells = <1>;
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index ee845fad939b..0e4d5b57c48b 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -8,6 +8,9 @@
8 * kind, whether express or implied. 8 * kind, whether express or implied.
9 */ 9 */
10 10
11#include <dt-bindings/interrupt-controller/arm-gic.h>
12#include <dt-bindings/interrupt-controller/irq.h>
13
11/ { 14/ {
12 compatible = "renesas,r8a7790"; 15 compatible = "renesas,r8a7790";
13 interrupt-parent = <&gic>; 16 interrupt-parent = <&gic>;
@@ -84,14 +87,14 @@
84 <0 0xf1002000 0 0x1000>, 87 <0 0xf1002000 0 0x1000>,
85 <0 0xf1004000 0 0x2000>, 88 <0 0xf1004000 0 0x2000>,
86 <0 0xf1006000 0 0x2000>; 89 <0 0xf1006000 0 0x2000>;
87 interrupts = <1 9 0xf04>; 90 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
88 }; 91 };
89 92
90 gpio0: gpio@ffc40000 { 93 gpio0: gpio@ffc40000 {
91 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; 94 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
92 reg = <0 0xffc40000 0 0x2c>; 95 reg = <0 0xffc40000 0 0x2c>;
93 interrupt-parent = <&gic>; 96 interrupt-parent = <&gic>;
94 interrupts = <0 4 0x4>; 97 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
95 #gpio-cells = <2>; 98 #gpio-cells = <2>;
96 gpio-controller; 99 gpio-controller;
97 gpio-ranges = <&pfc 0 0 32>; 100 gpio-ranges = <&pfc 0 0 32>;
@@ -103,7 +106,7 @@
103 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; 106 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
104 reg = <0 0xffc41000 0 0x2c>; 107 reg = <0 0xffc41000 0 0x2c>;
105 interrupt-parent = <&gic>; 108 interrupt-parent = <&gic>;
106 interrupts = <0 5 0x4>; 109 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
107 #gpio-cells = <2>; 110 #gpio-cells = <2>;
108 gpio-controller; 111 gpio-controller;
109 gpio-ranges = <&pfc 0 32 32>; 112 gpio-ranges = <&pfc 0 32 32>;
@@ -115,7 +118,7 @@
115 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; 118 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
116 reg = <0 0xffc42000 0 0x2c>; 119 reg = <0 0xffc42000 0 0x2c>;
117 interrupt-parent = <&gic>; 120 interrupt-parent = <&gic>;
118 interrupts = <0 6 0x4>; 121 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
119 #gpio-cells = <2>; 122 #gpio-cells = <2>;
120 gpio-controller; 123 gpio-controller;
121 gpio-ranges = <&pfc 0 64 32>; 124 gpio-ranges = <&pfc 0 64 32>;
@@ -127,7 +130,7 @@
127 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; 130 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
128 reg = <0 0xffc43000 0 0x2c>; 131 reg = <0 0xffc43000 0 0x2c>;
129 interrupt-parent = <&gic>; 132 interrupt-parent = <&gic>;
130 interrupts = <0 7 0x4>; 133 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
131 #gpio-cells = <2>; 134 #gpio-cells = <2>;
132 gpio-controller; 135 gpio-controller;
133 gpio-ranges = <&pfc 0 96 32>; 136 gpio-ranges = <&pfc 0 96 32>;
@@ -139,7 +142,7 @@
139 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; 142 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
140 reg = <0 0xffc44000 0 0x2c>; 143 reg = <0 0xffc44000 0 0x2c>;
141 interrupt-parent = <&gic>; 144 interrupt-parent = <&gic>;
142 interrupts = <0 8 0x4>; 145 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
143 #gpio-cells = <2>; 146 #gpio-cells = <2>;
144 gpio-controller; 147 gpio-controller;
145 gpio-ranges = <&pfc 0 128 32>; 148 gpio-ranges = <&pfc 0 128 32>;
@@ -151,7 +154,7 @@
151 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; 154 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
152 reg = <0 0xffc45000 0 0x2c>; 155 reg = <0 0xffc45000 0 0x2c>;
153 interrupt-parent = <&gic>; 156 interrupt-parent = <&gic>;
154 interrupts = <0 9 0x4>; 157 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
155 #gpio-cells = <2>; 158 #gpio-cells = <2>;
156 gpio-controller; 159 gpio-controller;
157 gpio-ranges = <&pfc 0 160 32>; 160 gpio-ranges = <&pfc 0 160 32>;
@@ -159,21 +162,31 @@
159 interrupt-controller; 162 interrupt-controller;
160 }; 163 };
161 164
165 thermal@e61f0000 {
166 compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal";
167 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
168 interrupt-parent = <&gic>;
169 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
170 };
171
162 timer { 172 timer {
163 compatible = "arm,armv7-timer"; 173 compatible = "arm,armv7-timer";
164 interrupts = <1 13 0xf08>, 174 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
165 <1 14 0xf08>, 175 <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
166 <1 11 0xf08>, 176 <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
167 <1 10 0xf08>; 177 <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
168 }; 178 };
169 179
170 irqc0: interrupt-controller@e61c0000 { 180 irqc0: interrupt-controller@e61c0000 {
171 compatible = "renesas,irqc"; 181 compatible = "renesas,irqc-r8a7790", "renesas,irqc";
172 #interrupt-cells = <2>; 182 #interrupt-cells = <2>;
173 interrupt-controller; 183 interrupt-controller;
174 reg = <0 0xe61c0000 0 0x200>; 184 reg = <0 0xe61c0000 0 0x200>;
175 interrupt-parent = <&gic>; 185 interrupt-parent = <&gic>;
176 interrupts = <0 0 4>, <0 1 4>, <0 2 4>, <0 3 4>; 186 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
187 <0 1 IRQ_TYPE_LEVEL_HIGH>,
188 <0 2 IRQ_TYPE_LEVEL_HIGH>,
189 <0 3 IRQ_TYPE_LEVEL_HIGH>;
177 }; 190 };
178 191
179 i2c0: i2c@e6508000 { 192 i2c0: i2c@e6508000 {
@@ -182,7 +195,7 @@
182 compatible = "renesas,i2c-r8a7790"; 195 compatible = "renesas,i2c-r8a7790";
183 reg = <0 0xe6508000 0 0x40>; 196 reg = <0 0xe6508000 0 0x40>;
184 interrupt-parent = <&gic>; 197 interrupt-parent = <&gic>;
185 interrupts = <0 287 0x4>; 198 interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
186 status = "disabled"; 199 status = "disabled";
187 }; 200 };
188 201
@@ -192,7 +205,7 @@
192 compatible = "renesas,i2c-r8a7790"; 205 compatible = "renesas,i2c-r8a7790";
193 reg = <0 0xe6518000 0 0x40>; 206 reg = <0 0xe6518000 0 0x40>;
194 interrupt-parent = <&gic>; 207 interrupt-parent = <&gic>;
195 interrupts = <0 288 0x4>; 208 interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
196 status = "disabled"; 209 status = "disabled";
197 }; 210 };
198 211
@@ -202,7 +215,7 @@
202 compatible = "renesas,i2c-r8a7790"; 215 compatible = "renesas,i2c-r8a7790";
203 reg = <0 0xe6530000 0 0x40>; 216 reg = <0 0xe6530000 0 0x40>;
204 interrupt-parent = <&gic>; 217 interrupt-parent = <&gic>;
205 interrupts = <0 286 0x4>; 218 interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
206 status = "disabled"; 219 status = "disabled";
207 }; 220 };
208 221
@@ -212,24 +225,24 @@
212 compatible = "renesas,i2c-r8a7790"; 225 compatible = "renesas,i2c-r8a7790";
213 reg = <0 0xe6540000 0 0x40>; 226 reg = <0 0xe6540000 0 0x40>;
214 interrupt-parent = <&gic>; 227 interrupt-parent = <&gic>;
215 interrupts = <0 290 0x4>; 228 interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
216 status = "disabled"; 229 status = "disabled";
217 }; 230 };
218 231
219 mmcif0: mmcif@ee200000 { 232 mmcif0: mmcif@ee200000 {
220 compatible = "renesas,sh-mmcif"; 233 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
221 reg = <0 0xee200000 0 0x80>; 234 reg = <0 0xee200000 0 0x80>;
222 interrupt-parent = <&gic>; 235 interrupt-parent = <&gic>;
223 interrupts = <0 169 0x4>; 236 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
224 reg-io-width = <4>; 237 reg-io-width = <4>;
225 status = "disabled"; 238 status = "disabled";
226 }; 239 };
227 240
228 mmcif1: mmcif@ee220000 { 241 mmcif1: mmc@ee220000 {
229 compatible = "renesas,sh-mmcif"; 242 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
230 reg = <0 0xee220000 0 0x80>; 243 reg = <0 0xee220000 0 0x80>;
231 interrupt-parent = <&gic>; 244 interrupt-parent = <&gic>;
232 interrupts = <0 170 0x4>; 245 interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>;
233 reg-io-width = <4>; 246 reg-io-width = <4>;
234 status = "disabled"; 247 status = "disabled";
235 }; 248 };
@@ -239,38 +252,38 @@
239 reg = <0 0xe6060000 0 0x250>; 252 reg = <0 0xe6060000 0 0x250>;
240 }; 253 };
241 254
242 sdhi0: sdhi@ee100000 { 255 sdhi0: sd@ee100000 {
243 compatible = "renesas,sdhi-r8a7790"; 256 compatible = "renesas,sdhi-r8a7790";
244 reg = <0 0xee100000 0 0x100>; 257 reg = <0 0xee100000 0 0x100>;
245 interrupt-parent = <&gic>; 258 interrupt-parent = <&gic>;
246 interrupts = <0 165 4>; 259 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
247 cap-sd-highspeed; 260 cap-sd-highspeed;
248 status = "disabled"; 261 status = "disabled";
249 }; 262 };
250 263
251 sdhi1: sdhi@ee120000 { 264 sdhi1: sd@ee120000 {
252 compatible = "renesas,sdhi-r8a7790"; 265 compatible = "renesas,sdhi-r8a7790";
253 reg = <0 0xee120000 0 0x100>; 266 reg = <0 0xee120000 0 0x100>;
254 interrupt-parent = <&gic>; 267 interrupt-parent = <&gic>;
255 interrupts = <0 166 4>; 268 interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>;
256 cap-sd-highspeed; 269 cap-sd-highspeed;
257 status = "disabled"; 270 status = "disabled";
258 }; 271 };
259 272
260 sdhi2: sdhi@ee140000 { 273 sdhi2: sd@ee140000 {
261 compatible = "renesas,sdhi-r8a7790"; 274 compatible = "renesas,sdhi-r8a7790";
262 reg = <0 0xee140000 0 0x100>; 275 reg = <0 0xee140000 0 0x100>;
263 interrupt-parent = <&gic>; 276 interrupt-parent = <&gic>;
264 interrupts = <0 167 4>; 277 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
265 cap-sd-highspeed; 278 cap-sd-highspeed;
266 status = "disabled"; 279 status = "disabled";
267 }; 280 };
268 281
269 sdhi3: sdhi@ee160000 { 282 sdhi3: sd@ee160000 {
270 compatible = "renesas,sdhi-r8a7790"; 283 compatible = "renesas,sdhi-r8a7790";
271 reg = <0 0xee160000 0 0x100>; 284 reg = <0 0xee160000 0 0x100>;
272 interrupt-parent = <&gic>; 285 interrupt-parent = <&gic>;
273 interrupts = <0 168 4>; 286 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
274 cap-sd-highspeed; 287 cap-sd-highspeed;
275 status = "disabled"; 288 status = "disabled";
276 }; 289 };
diff --git a/arch/arm/boot/dts/r8a7791-koelsch-reference.dts b/arch/arm/boot/dts/r8a7791-koelsch-reference.dts
new file mode 100644
index 000000000000..588ca17ea1f0
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7791-koelsch-reference.dts
@@ -0,0 +1,115 @@
1/*
2 * Device Tree Source for the Koelsch board
3 *
4 * Copyright (C) 2013 Renesas Electronics Corporation
5 * Copyright (C) 2013 Renesas Solutions Corp.
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
12/dts-v1/;
13#include "r8a7791.dtsi"
14#include <dt-bindings/gpio/gpio.h>
15
16/ {
17 model = "Koelsch";
18 compatible = "renesas,koelsch-reference", "renesas,r8a7791";
19
20 chosen {
21 bootargs = "console=ttySC6,115200 ignore_loglevel rw root=/dev/nfs ip=dhcp";
22 };
23
24 memory@40000000 {
25 device_type = "memory";
26 reg = <0 0x40000000 0 0x80000000>;
27 };
28
29 lbsc {
30 #address-cells = <1>;
31 #size-cells = <1>;
32 };
33
34 gpio-keys {
35 compatible = "gpio-keys";
36
37 key-a {
38 gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
39 linux,code = <30>;
40 label = "SW30";
41 gpio-key,wakeup;
42 debounce-interval = <20>;
43 };
44 key-b {
45 gpios = <&gpio7 1 GPIO_ACTIVE_LOW>;
46 linux,code = <48>;
47 label = "SW31";
48 gpio-key,wakeup;
49 debounce-interval = <20>;
50 };
51 key-c {
52 gpios = <&gpio7 2 GPIO_ACTIVE_LOW>;
53 linux,code = <46>;
54 label = "SW32";
55 gpio-key,wakeup;
56 debounce-interval = <20>;
57 };
58 key-d {
59 gpios = <&gpio7 3 GPIO_ACTIVE_LOW>;
60 linux,code = <32>;
61 label = "SW33";
62 gpio-key,wakeup;
63 debounce-interval = <20>;
64 };
65 key-e {
66 gpios = <&gpio7 4 GPIO_ACTIVE_LOW>;
67 linux,code = <18>;
68 label = "SW34";
69 gpio-key,wakeup;
70 debounce-interval = <20>;
71 };
72 key-f {
73 gpios = <&gpio7 5 GPIO_ACTIVE_LOW>;
74 linux,code = <33>;
75 label = "SW35";
76 gpio-key,wakeup;
77 debounce-interval = <20>;
78 };
79 key-g {
80 gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
81 linux,code = <34>;
82 label = "SW36";
83 gpio-key,wakeup;
84 debounce-interval = <20>;
85 };
86 };
87
88 leds {
89 compatible = "gpio-leds";
90 led6 {
91 gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
92 };
93 led7 {
94 gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
95 };
96 led8 {
97 gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
98 };
99 };
100};
101
102&pfc {
103 pinctrl-0 = <&scif0_pins &scif1_pins>;
104 pinctrl-names = "default";
105
106 scif0_pins: serial0 {
107 renesas,groups = "scif0_data_d";
108 renesas,function = "scif0";
109 };
110
111 scif1_pins: serial1 {
112 renesas,groups = "scif1_data_d";
113 renesas,function = "scif1";
114 };
115};
diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
index 1ce5250ec278..c4e8b3a0cd13 100644
--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
+++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
@@ -10,7 +10,7 @@
10 */ 10 */
11 11
12/dts-v1/; 12/dts-v1/;
13/include/ "r8a7791.dtsi" 13#include "r8a7791.dtsi"
14 14
15/ { 15/ {
16 model = "Koelsch"; 16 model = "Koelsch";
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index fea5cfef4691..a349aff54c76 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -9,6 +9,9 @@
9 * kind, whether express or implied. 9 * kind, whether express or implied.
10 */ 10 */
11 11
12#include <dt-bindings/interrupt-controller/arm-gic.h>
13#include <dt-bindings/interrupt-controller/irq.h>
14
12/ { 15/ {
13 compatible = "renesas,r8a7791"; 16 compatible = "renesas,r8a7791";
14 interrupt-parent = <&gic>; 17 interrupt-parent = <&gic>;
@@ -43,32 +46,141 @@
43 <0 0xf1002000 0 0x1000>, 46 <0 0xf1002000 0 0x1000>,
44 <0 0xf1004000 0 0x2000>, 47 <0 0xf1004000 0 0x2000>,
45 <0 0xf1006000 0 0x2000>; 48 <0 0xf1006000 0 0x2000>;
46 interrupts = <1 9 0xf04>; 49 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
50 };
51
52 gpio0: gpio@e6050000 {
53 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
54 reg = <0 0xe6050000 0 0x50>;
55 interrupt-parent = <&gic>;
56 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
57 #gpio-cells = <2>;
58 gpio-controller;
59 gpio-ranges = <&pfc 0 0 32>;
60 #interrupt-cells = <2>;
61 interrupt-controller;
62 };
63
64 gpio1: gpio@e6051000 {
65 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
66 reg = <0 0xe6051000 0 0x50>;
67 interrupt-parent = <&gic>;
68 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
69 #gpio-cells = <2>;
70 gpio-controller;
71 gpio-ranges = <&pfc 0 32 32>;
72 #interrupt-cells = <2>;
73 interrupt-controller;
74 };
75
76 gpio2: gpio@e6052000 {
77 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
78 reg = <0 0xe6052000 0 0x50>;
79 interrupt-parent = <&gic>;
80 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
81 #gpio-cells = <2>;
82 gpio-controller;
83 gpio-ranges = <&pfc 0 64 32>;
84 #interrupt-cells = <2>;
85 interrupt-controller;
86 };
87
88 gpio3: gpio@e6053000 {
89 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
90 reg = <0 0xe6053000 0 0x50>;
91 interrupt-parent = <&gic>;
92 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
93 #gpio-cells = <2>;
94 gpio-controller;
95 gpio-ranges = <&pfc 0 96 32>;
96 #interrupt-cells = <2>;
97 interrupt-controller;
98 };
99
100 gpio4: gpio@e6054000 {
101 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
102 reg = <0 0xe6054000 0 0x50>;
103 interrupt-parent = <&gic>;
104 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
105 #gpio-cells = <2>;
106 gpio-controller;
107 gpio-ranges = <&pfc 0 128 32>;
108 #interrupt-cells = <2>;
109 interrupt-controller;
110 };
111
112 gpio5: gpio@e6055000 {
113 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
114 reg = <0 0xe6055000 0 0x50>;
115 interrupt-parent = <&gic>;
116 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
117 #gpio-cells = <2>;
118 gpio-controller;
119 gpio-ranges = <&pfc 0 160 32>;
120 #interrupt-cells = <2>;
121 interrupt-controller;
122 };
123
124 gpio6: gpio@e6055400 {
125 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
126 reg = <0 0xe6055400 0 0x50>;
127 interrupt-parent = <&gic>;
128 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
129 #gpio-cells = <2>;
130 gpio-controller;
131 gpio-ranges = <&pfc 0 192 32>;
132 #interrupt-cells = <2>;
133 interrupt-controller;
134 };
135
136 gpio7: gpio@e6055800 {
137 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
138 reg = <0 0xe6055800 0 0x50>;
139 interrupt-parent = <&gic>;
140 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
141 #gpio-cells = <2>;
142 gpio-controller;
143 gpio-ranges = <&pfc 0 224 26>;
144 #interrupt-cells = <2>;
145 interrupt-controller;
146 };
147
148 thermal@e61f0000 {
149 compatible = "renesas,thermal-r8a7791", "renesas,rcar-thermal";
150 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
151 interrupt-parent = <&gic>;
152 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
47 }; 153 };
48 154
49 timer { 155 timer {
50 compatible = "arm,armv7-timer"; 156 compatible = "arm,armv7-timer";
51 interrupts = <1 13 0xf08>, 157 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
52 <1 14 0xf08>, 158 <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
53 <1 11 0xf08>, 159 <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
54 <1 10 0xf08>; 160 <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
55 }; 161 };
56 162
57 irqc0: interrupt-controller@e61c0000 { 163 irqc0: interrupt-controller@e61c0000 {
58 compatible = "renesas,irqc"; 164 compatible = "renesas,irqc-r8a7791", "renesas,irqc";
59 #interrupt-cells = <2>; 165 #interrupt-cells = <2>;
60 interrupt-controller; 166 interrupt-controller;
61 reg = <0 0xe61c0000 0 0x200>; 167 reg = <0 0xe61c0000 0 0x200>;
62 interrupt-parent = <&gic>; 168 interrupt-parent = <&gic>;
63 interrupts = <0 0 4>, 169 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
64 <0 1 4>, 170 <0 1 IRQ_TYPE_LEVEL_HIGH>,
65 <0 2 4>, 171 <0 2 IRQ_TYPE_LEVEL_HIGH>,
66 <0 3 4>, 172 <0 3 IRQ_TYPE_LEVEL_HIGH>,
67 <0 12 4>, 173 <0 12 IRQ_TYPE_LEVEL_HIGH>,
68 <0 13 4>, 174 <0 13 IRQ_TYPE_LEVEL_HIGH>,
69 <0 14 4>, 175 <0 14 IRQ_TYPE_LEVEL_HIGH>,
70 <0 15 4>, 176 <0 15 IRQ_TYPE_LEVEL_HIGH>,
71 <0 16 4>, 177 <0 16 IRQ_TYPE_LEVEL_HIGH>,
72 <0 17 4>; 178 <0 17 IRQ_TYPE_LEVEL_HIGH>;
179 };
180
181 pfc: pfc@e6060000 {
182 compatible = "renesas,pfc-r8a7791";
183 reg = <0 0xe6060000 0 0x250>;
184 #gpio-range-cells = <3>;
73 }; 185 };
74}; 186};
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index 5cdaba4cea86..1105558d188b 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -1,6 +1,6 @@
1/* 1/*
2 * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC 2 * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC
3 * applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35 SoC 3 * applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36 SoC
4 * 4 *
5 * Copyright (C) 2013 Atmel, 5 * Copyright (C) 2013 Atmel,
6 * 2013 Ludovic Desroches <ludovic.desroches@atmel.com> 6 * 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
@@ -13,6 +13,7 @@
13#include <dt-bindings/pinctrl/at91.h> 13#include <dt-bindings/pinctrl/at91.h>
14#include <dt-bindings/interrupt-controller/irq.h> 14#include <dt-bindings/interrupt-controller/irq.h>
15#include <dt-bindings/gpio/gpio.h> 15#include <dt-bindings/gpio/gpio.h>
16#include <dt-bindings/clk/at91.h>
16 17
17/ { 18/ {
18 model = "Atmel SAMA5D3 family SoC"; 19 model = "Atmel SAMA5D3 family SoC";
@@ -36,6 +37,7 @@
36 i2c2 = &i2c2; 37 i2c2 = &i2c2;
37 ssc0 = &ssc0; 38 ssc0 = &ssc0;
38 ssc1 = &ssc1; 39 ssc1 = &ssc1;
40 pwm0 = &pwm0;
39 }; 41 };
40 cpus { 42 cpus {
41 #address-cells = <1>; 43 #address-cells = <1>;
@@ -56,6 +58,14 @@
56 reg = <0x20000000 0x8000000>; 58 reg = <0x20000000 0x8000000>;
57 }; 59 };
58 60
61 clocks {
62 adc_op_clk: adc_op_clk{
63 compatible = "fixed-clock";
64 #clock-cells = <0>;
65 clock-frequency = <20000000>;
66 };
67 };
68
59 ahb { 69 ahb {
60 compatible = "simple-bus"; 70 compatible = "simple-bus";
61 #address-cells = <1>; 71 #address-cells = <1>;
@@ -79,6 +89,8 @@
79 status = "disabled"; 89 status = "disabled";
80 #address-cells = <1>; 90 #address-cells = <1>;
81 #size-cells = <0>; 91 #size-cells = <0>;
92 clocks = <&mci0_clk>;
93 clock-names = "mci_clk";
82 }; 94 };
83 95
84 spi0: spi@f0004000 { 96 spi0: spi@f0004000 {
@@ -92,6 +104,8 @@
92 dma-names = "tx", "rx"; 104 dma-names = "tx", "rx";
93 pinctrl-names = "default"; 105 pinctrl-names = "default";
94 pinctrl-0 = <&pinctrl_spi0>; 106 pinctrl-0 = <&pinctrl_spi0>;
107 clocks = <&spi0_clk>;
108 clock-names = "spi_clk";
95 status = "disabled"; 109 status = "disabled";
96 }; 110 };
97 111
@@ -101,6 +115,8 @@
101 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 4>; 115 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 4>;
102 pinctrl-names = "default"; 116 pinctrl-names = "default";
103 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; 117 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
118 clocks = <&ssc0_clk>;
119 clock-names = "pclk";
104 status = "disabled"; 120 status = "disabled";
105 }; 121 };
106 122
@@ -108,6 +124,8 @@
108 compatible = "atmel,at91sam9x5-tcb"; 124 compatible = "atmel,at91sam9x5-tcb";
109 reg = <0xf0010000 0x100>; 125 reg = <0xf0010000 0x100>;
110 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; 126 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
127 clocks = <&tcb0_clk>;
128 clock-names = "t0_clk";
111 }; 129 };
112 130
113 i2c0: i2c@f0014000 { 131 i2c0: i2c@f0014000 {
@@ -121,6 +139,7 @@
121 pinctrl-0 = <&pinctrl_i2c0>; 139 pinctrl-0 = <&pinctrl_i2c0>;
122 #address-cells = <1>; 140 #address-cells = <1>;
123 #size-cells = <0>; 141 #size-cells = <0>;
142 clocks = <&twi0_clk>;
124 status = "disabled"; 143 status = "disabled";
125 }; 144 };
126 145
@@ -135,6 +154,7 @@
135 pinctrl-0 = <&pinctrl_i2c1>; 154 pinctrl-0 = <&pinctrl_i2c1>;
136 #address-cells = <1>; 155 #address-cells = <1>;
137 #size-cells = <0>; 156 #size-cells = <0>;
157 clocks = <&twi1_clk>;
138 status = "disabled"; 158 status = "disabled";
139 }; 159 };
140 160
@@ -144,6 +164,8 @@
144 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>; 164 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>;
145 pinctrl-names = "default"; 165 pinctrl-names = "default";
146 pinctrl-0 = <&pinctrl_usart0>; 166 pinctrl-0 = <&pinctrl_usart0>;
167 clocks = <&usart0_clk>;
168 clock-names = "usart";
147 status = "disabled"; 169 status = "disabled";
148 }; 170 };
149 171
@@ -153,6 +175,17 @@
153 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>; 175 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>;
154 pinctrl-names = "default"; 176 pinctrl-names = "default";
155 pinctrl-0 = <&pinctrl_usart1>; 177 pinctrl-0 = <&pinctrl_usart1>;
178 clocks = <&usart1_clk>;
179 clock-names = "usart";
180 status = "disabled";
181 };
182
183 pwm0: pwm@f002c000 {
184 compatible = "atmel,sama5d3-pwm";
185 reg = <0xf002c000 0x300>;
186 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 4>;
187 #pwm-cells = <3>;
188 clocks = <&pwm_clk>;
156 status = "disabled"; 189 status = "disabled";
157 }; 190 };
158 191
@@ -174,6 +207,8 @@
174 status = "disabled"; 207 status = "disabled";
175 #address-cells = <1>; 208 #address-cells = <1>;
176 #size-cells = <0>; 209 #size-cells = <0>;
210 clocks = <&mci1_clk>;
211 clock-names = "mci_clk";
177 }; 212 };
178 213
179 spi1: spi@f8008000 { 214 spi1: spi@f8008000 {
@@ -187,6 +222,8 @@
187 dma-names = "tx", "rx"; 222 dma-names = "tx", "rx";
188 pinctrl-names = "default"; 223 pinctrl-names = "default";
189 pinctrl-0 = <&pinctrl_spi1>; 224 pinctrl-0 = <&pinctrl_spi1>;
225 clocks = <&spi1_clk>;
226 clock-names = "spi_clk";
190 status = "disabled"; 227 status = "disabled";
191 }; 228 };
192 229
@@ -196,6 +233,8 @@
196 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 4>; 233 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 4>;
197 pinctrl-names = "default"; 234 pinctrl-names = "default";
198 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; 235 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
236 clocks = <&ssc1_clk>;
237 clock-names = "pclk";
199 status = "disabled"; 238 status = "disabled";
200 }; 239 };
201 240
@@ -219,6 +258,9 @@
219 &pinctrl_adc0_ad10 258 &pinctrl_adc0_ad10
220 &pinctrl_adc0_ad11 259 &pinctrl_adc0_ad11
221 >; 260 >;
261 clocks = <&adc_clk>,
262 <&adc_op_clk>;
263 clock-names = "adc_clk", "adc_op_clk";
222 atmel,adc-channel-base = <0x50>; 264 atmel,adc-channel-base = <0x50>;
223 atmel,adc-channels-used = <0xfff>; 265 atmel,adc-channels-used = <0xfff>;
224 atmel,adc-drdy-mask = <0x1000000>; 266 atmel,adc-drdy-mask = <0x1000000>;
@@ -272,8 +314,11 @@
272 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(11)>, 314 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(11)>,
273 <&dma1 2 AT91_DMA_CFG_PER_ID(12)>; 315 <&dma1 2 AT91_DMA_CFG_PER_ID(12)>;
274 dma-names = "tx", "rx"; 316 dma-names = "tx", "rx";
317 pinctrl-names = "default";
318 pinctrl-0 = <&pinctrl_i2c2>;
275 #address-cells = <1>; 319 #address-cells = <1>;
276 #size-cells = <0>; 320 #size-cells = <0>;
321 clocks = <&twi2_clk>;
277 status = "disabled"; 322 status = "disabled";
278 }; 323 };
279 324
@@ -283,6 +328,8 @@
283 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; 328 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
284 pinctrl-names = "default"; 329 pinctrl-names = "default";
285 pinctrl-0 = <&pinctrl_usart2>; 330 pinctrl-0 = <&pinctrl_usart2>;
331 clocks = <&usart2_clk>;
332 clock-names = "usart";
286 status = "disabled"; 333 status = "disabled";
287 }; 334 };
288 335
@@ -292,25 +339,41 @@
292 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; 339 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
293 pinctrl-names = "default"; 340 pinctrl-names = "default";
294 pinctrl-0 = <&pinctrl_usart3>; 341 pinctrl-0 = <&pinctrl_usart3>;
342 clocks = <&usart3_clk>;
343 clock-names = "usart";
295 status = "disabled"; 344 status = "disabled";
296 }; 345 };
297 346
298 sha@f8034000 { 347 sha@f8034000 {
299 compatible = "atmel,sam9g46-sha"; 348 compatible = "atmel,at91sam9g46-sha";
300 reg = <0xf8034000 0x100>; 349 reg = <0xf8034000 0x100>;
301 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>; 350 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>;
351 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(17)>;
352 dma-names = "tx";
353 clocks = <&sha_clk>;
354 clock-names = "sha_clk";
302 }; 355 };
303 356
304 aes@f8038000 { 357 aes@f8038000 {
305 compatible = "atmel,sam9g46-aes"; 358 compatible = "atmel,at91sam9g46-aes";
306 reg = <0xf8038000 0x100>; 359 reg = <0xf8038000 0x100>;
307 interrupts = <43 4 0>; 360 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 0>;
361 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(18)>,
362 <&dma1 2 AT91_DMA_CFG_PER_ID(19)>;
363 dma-names = "tx", "rx";
364 clocks = <&aes_clk>;
365 clock-names = "aes_clk";
308 }; 366 };
309 367
310 tdes@f803c000 { 368 tdes@f803c000 {
311 compatible = "atmel,sam9g46-tdes"; 369 compatible = "atmel,at91sam9g46-tdes";
312 reg = <0xf803c000 0x100>; 370 reg = <0xf803c000 0x100>;
313 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 0>; 371 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 0>;
372 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(20)>,
373 <&dma1 2 AT91_DMA_CFG_PER_ID(21)>;
374 dma-names = "tx", "rx";
375 clocks = <&tdes_clk>;
376 clock-names = "tdes_clk";
314 }; 377 };
315 378
316 dma0: dma-controller@ffffe600 { 379 dma0: dma-controller@ffffe600 {
@@ -318,6 +381,8 @@
318 reg = <0xffffe600 0x200>; 381 reg = <0xffffe600 0x200>;
319 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>; 382 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>;
320 #dma-cells = <2>; 383 #dma-cells = <2>;
384 clocks = <&dma0_clk>;
385 clock-names = "dma_clk";
321 }; 386 };
322 387
323 dma1: dma-controller@ffffe800 { 388 dma1: dma-controller@ffffe800 {
@@ -325,6 +390,8 @@
325 reg = <0xffffe800 0x200>; 390 reg = <0xffffe800 0x200>;
326 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>; 391 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
327 #dma-cells = <2>; 392 #dma-cells = <2>;
393 clocks = <&dma1_clk>;
394 clock-names = "dma_clk";
328 }; 395 };
329 396
330 ramc0: ramc@ffffea00 { 397 ramc0: ramc@ffffea00 {
@@ -338,6 +405,8 @@
338 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>; 405 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>;
339 pinctrl-names = "default"; 406 pinctrl-names = "default";
340 pinctrl-0 = <&pinctrl_dbgu>; 407 pinctrl-0 = <&pinctrl_dbgu>;
408 clocks = <&dbgu_clk>;
409 clock-names = "usart";
341 status = "disabled"; 410 status = "disabled";
342 }; 411 };
343 412
@@ -443,6 +512,14 @@
443 }; 512 };
444 }; 513 };
445 514
515 i2c2 {
516 pinctrl_i2c2: i2c2-0 {
517 atmel,pins =
518 <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* TWD2 pin, conflicts with LCDDAT18, ISI_D2 */
519 AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TWCK2 pin, conflicts with LCDDAT19, ISI_D3 */
520 };
521 };
522
446 isi { 523 isi {
447 pinctrl_isi: isi-0 { 524 pinctrl_isi: isi-0 {
448 atmel,pins = 525 atmel,pins =
@@ -626,6 +703,7 @@
626 gpio-controller; 703 gpio-controller;
627 interrupt-controller; 704 interrupt-controller;
628 #interrupt-cells = <2>; 705 #interrupt-cells = <2>;
706 clocks = <&pioA_clk>;
629 }; 707 };
630 708
631 pioB: gpio@fffff400 { 709 pioB: gpio@fffff400 {
@@ -636,6 +714,7 @@
636 gpio-controller; 714 gpio-controller;
637 interrupt-controller; 715 interrupt-controller;
638 #interrupt-cells = <2>; 716 #interrupt-cells = <2>;
717 clocks = <&pioB_clk>;
639 }; 718 };
640 719
641 pioC: gpio@fffff600 { 720 pioC: gpio@fffff600 {
@@ -646,6 +725,7 @@
646 gpio-controller; 725 gpio-controller;
647 interrupt-controller; 726 interrupt-controller;
648 #interrupt-cells = <2>; 727 #interrupt-cells = <2>;
728 clocks = <&pioC_clk>;
649 }; 729 };
650 730
651 pioD: gpio@fffff800 { 731 pioD: gpio@fffff800 {
@@ -656,6 +736,7 @@
656 gpio-controller; 736 gpio-controller;
657 interrupt-controller; 737 interrupt-controller;
658 #interrupt-cells = <2>; 738 #interrupt-cells = <2>;
739 clocks = <&pioD_clk>;
659 }; 740 };
660 741
661 pioE: gpio@fffffa00 { 742 pioE: gpio@fffffa00 {
@@ -666,12 +747,334 @@
666 gpio-controller; 747 gpio-controller;
667 interrupt-controller; 748 interrupt-controller;
668 #interrupt-cells = <2>; 749 #interrupt-cells = <2>;
750 clocks = <&pioE_clk>;
669 }; 751 };
670 }; 752 };
671 753
672 pmc: pmc@fffffc00 { 754 pmc: pmc@fffffc00 {
673 compatible = "atmel,at91rm9200-pmc"; 755 compatible = "atmel,sama5d3-pmc";
674 reg = <0xfffffc00 0x120>; 756 reg = <0xfffffc00 0x120>;
757 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
758 interrupt-controller;
759 #address-cells = <1>;
760 #size-cells = <0>;
761 #interrupt-cells = <1>;
762
763 clk32k: slck {
764 compatible = "fixed-clock";
765 #clock-cells = <0>;
766 clock-frequency = <32768>;
767 };
768
769 main: mainck {
770 compatible = "atmel,at91rm9200-clk-main";
771 #clock-cells = <0>;
772 interrupt-parent = <&pmc>;
773 interrupts = <AT91_PMC_MOSCS>;
774 clocks = <&clk32k>;
775 };
776
777 plla: pllack {
778 compatible = "atmel,sama5d3-clk-pll";
779 #clock-cells = <0>;
780 interrupt-parent = <&pmc>;
781 interrupts = <AT91_PMC_LOCKA>;
782 clocks = <&main>;
783 reg = <0>;
784 atmel,clk-input-range = <8000000 50000000>;
785 #atmel,pll-clk-output-range-cells = <4>;
786 atmel,pll-clk-output-ranges = <400000000 1000000000 0 0>;
787 };
788
789 plladiv: plladivck {
790 compatible = "atmel,at91sam9x5-clk-plldiv";
791 #clock-cells = <0>;
792 clocks = <&plla>;
793 };
794
795 utmi: utmick {
796 compatible = "atmel,at91sam9x5-clk-utmi";
797 #clock-cells = <0>;
798 interrupt-parent = <&pmc>;
799 interrupts = <AT91_PMC_LOCKU>;
800 clocks = <&main>;
801 };
802
803 mck: masterck {
804 compatible = "atmel,at91sam9x5-clk-master";
805 #clock-cells = <0>;
806 interrupt-parent = <&pmc>;
807 interrupts = <AT91_PMC_MCKRDY>;
808 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
809 atmel,clk-output-range = <0 166000000>;
810 atmel,clk-divisors = <1 2 4 3>;
811 };
812
813 usb: usbck {
814 compatible = "atmel,at91sam9x5-clk-usb";
815 #clock-cells = <0>;
816 clocks = <&plladiv>, <&utmi>;
817 };
818
819 prog: progck {
820 compatible = "atmel,at91sam9x5-clk-programmable";
821 #address-cells = <1>;
822 #size-cells = <0>;
823 interrupt-parent = <&pmc>;
824 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
825
826 prog0: prog0 {
827 #clock-cells = <0>;
828 reg = <0>;
829 interrupts = <AT91_PMC_PCKRDY(0)>;
830 };
831
832 prog1: prog1 {
833 #clock-cells = <0>;
834 reg = <1>;
835 interrupts = <AT91_PMC_PCKRDY(1)>;
836 };
837
838 prog2: prog2 {
839 #clock-cells = <0>;
840 reg = <2>;
841 interrupts = <AT91_PMC_PCKRDY(2)>;
842 };
843 };
844
845 smd: smdclk {
846 compatible = "atmel,at91sam9x5-clk-smd";
847 #clock-cells = <0>;
848 clocks = <&plladiv>, <&utmi>;
849 };
850
851 systemck {
852 compatible = "atmel,at91rm9200-clk-system";
853 #address-cells = <1>;
854 #size-cells = <0>;
855
856 ddrck: ddrck {
857 #clock-cells = <0>;
858 reg = <2>;
859 clocks = <&mck>;
860 };
861
862 smdck: smdck {
863 #clock-cells = <0>;
864 reg = <4>;
865 clocks = <&smd>;
866 };
867
868 uhpck: uhpck {
869 #clock-cells = <0>;
870 reg = <6>;
871 clocks = <&usb>;
872 };
873
874 udpck: udpck {
875 #clock-cells = <0>;
876 reg = <7>;
877 clocks = <&usb>;
878 };
879
880 pck0: pck0 {
881 #clock-cells = <0>;
882 reg = <8>;
883 clocks = <&prog0>;
884 };
885
886 pck1: pck1 {
887 #clock-cells = <0>;
888 reg = <9>;
889 clocks = <&prog1>;
890 };
891
892 pck2: pck2 {
893 #clock-cells = <0>;
894 reg = <10>;
895 clocks = <&prog2>;
896 };
897 };
898
899 periphck {
900 compatible = "atmel,at91sam9x5-clk-peripheral";
901 #address-cells = <1>;
902 #size-cells = <0>;
903 clocks = <&mck>;
904
905 dbgu_clk: dbgu_clk {
906 #clock-cells = <0>;
907 reg = <2>;
908 };
909
910 pioA_clk: pioA_clk {
911 #clock-cells = <0>;
912 reg = <6>;
913 };
914
915 pioB_clk: pioB_clk {
916 #clock-cells = <0>;
917 reg = <7>;
918 };
919
920 pioC_clk: pioC_clk {
921 #clock-cells = <0>;
922 reg = <8>;
923 };
924
925 pioD_clk: pioD_clk {
926 #clock-cells = <0>;
927 reg = <9>;
928 };
929
930 pioE_clk: pioE_clk {
931 #clock-cells = <0>;
932 reg = <10>;
933 };
934
935 usart0_clk: usart0_clk {
936 #clock-cells = <0>;
937 reg = <12>;
938 atmel,clk-output-range = <0 66000000>;
939 };
940
941 usart1_clk: usart1_clk {
942 #clock-cells = <0>;
943 reg = <13>;
944 atmel,clk-output-range = <0 66000000>;
945 };
946
947 usart2_clk: usart2_clk {
948 #clock-cells = <0>;
949 reg = <14>;
950 atmel,clk-output-range = <0 66000000>;
951 };
952
953 usart3_clk: usart3_clk {
954 #clock-cells = <0>;
955 reg = <15>;
956 atmel,clk-output-range = <0 66000000>;
957 };
958
959 twi0_clk: twi0_clk {
960 reg = <18>;
961 #clock-cells = <0>;
962 atmel,clk-output-range = <0 16625000>;
963 };
964
965 twi1_clk: twi1_clk {
966 #clock-cells = <0>;
967 reg = <19>;
968 atmel,clk-output-range = <0 16625000>;
969 };
970
971 twi2_clk: twi2_clk {
972 #clock-cells = <0>;
973 reg = <20>;
974 atmel,clk-output-range = <0 16625000>;
975 };
976
977 mci0_clk: mci0_clk {
978 #clock-cells = <0>;
979 reg = <21>;
980 };
981
982 mci1_clk: mci1_clk {
983 #clock-cells = <0>;
984 reg = <22>;
985 };
986
987 spi0_clk: spi0_clk {
988 #clock-cells = <0>;
989 reg = <24>;
990 atmel,clk-output-range = <0 133000000>;
991 };
992
993 spi1_clk: spi1_clk {
994 #clock-cells = <0>;
995 reg = <25>;
996 atmel,clk-output-range = <0 133000000>;
997 };
998
999 tcb0_clk: tcb0_clk {
1000 #clock-cells = <0>;
1001 reg = <26>;
1002 atmel,clk-output-range = <0 133000000>;
1003 };
1004
1005 pwm_clk: pwm_clk {
1006 #clock-cells = <0>;
1007 reg = <28>;
1008 };
1009
1010 adc_clk: adc_clk {
1011 #clock-cells = <0>;
1012 reg = <29>;
1013 atmel,clk-output-range = <0 66000000>;
1014 };
1015
1016 dma0_clk: dma0_clk {
1017 #clock-cells = <0>;
1018 reg = <30>;
1019 };
1020
1021 dma1_clk: dma1_clk {
1022 #clock-cells = <0>;
1023 reg = <31>;
1024 };
1025
1026 uhphs_clk: uhphs_clk {
1027 #clock-cells = <0>;
1028 reg = <32>;
1029 };
1030
1031 udphs_clk: udphs_clk {
1032 #clock-cells = <0>;
1033 reg = <33>;
1034 };
1035
1036 isi_clk: isi_clk {
1037 #clock-cells = <0>;
1038 reg = <37>;
1039 };
1040
1041 ssc0_clk: ssc0_clk {
1042 #clock-cells = <0>;
1043 reg = <38>;
1044 atmel,clk-output-range = <0 66000000>;
1045 };
1046
1047 ssc1_clk: ssc1_clk {
1048 #clock-cells = <0>;
1049 reg = <39>;
1050 atmel,clk-output-range = <0 66000000>;
1051 };
1052
1053 sha_clk: sha_clk {
1054 #clock-cells = <0>;
1055 reg = <42>;
1056 };
1057
1058 aes_clk: aes_clk {
1059 #clock-cells = <0>;
1060 reg = <43>;
1061 };
1062
1063 tdes_clk: tdes_clk {
1064 #clock-cells = <0>;
1065 reg = <44>;
1066 };
1067
1068 trng_clk: trng_clk {
1069 #clock-cells = <0>;
1070 reg = <45>;
1071 };
1072
1073 fuse_clk: fuse_clk {
1074 #clock-cells = <0>;
1075 reg = <48>;
1076 };
1077 };
675 }; 1078 };
676 1079
677 rstc@fffffe00 { 1080 rstc@fffffe00 {
@@ -683,6 +1086,7 @@
683 compatible = "atmel,at91sam9260-pit"; 1086 compatible = "atmel,at91sam9260-pit";
684 reg = <0xfffffe30 0xf>; 1087 reg = <0xfffffe30 0xf>;
685 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; 1088 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
1089 clocks = <&mck>;
686 }; 1090 };
687 1091
688 watchdog@fffffe40 { 1092 watchdog@fffffe40 {
@@ -705,6 +1109,8 @@
705 reg = <0x00500000 0x100000 1109 reg = <0x00500000 0x100000
706 0xf8030000 0x4000>; 1110 0xf8030000 0x4000>;
707 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 2>; 1111 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 2>;
1112 clocks = <&udphs_clk>, <&utmi>;
1113 clock-names = "pclk", "hclk";
708 status = "disabled"; 1114 status = "disabled";
709 1115
710 ep0 { 1116 ep0 {
@@ -817,6 +1223,9 @@
817 compatible = "atmel,at91rm9200-ohci", "usb-ohci"; 1223 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
818 reg = <0x00600000 0x100000>; 1224 reg = <0x00600000 0x100000>;
819 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; 1225 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
1226 clocks = <&usb>, <&uhphs_clk>, <&udphs_clk>,
1227 <&uhpck>;
1228 clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
820 status = "disabled"; 1229 status = "disabled";
821 }; 1230 };
822 1231
@@ -824,6 +1233,8 @@
824 compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; 1233 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
825 reg = <0x00700000 0x100000>; 1234 reg = <0x00700000 0x100000>;
826 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; 1235 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
1236 clocks = <&usb>, <&uhphs_clk>, <&uhpck>;
1237 clock-names = "usb_clk", "ehci_clk", "uhpck";
827 status = "disabled"; 1238 status = "disabled";
828 }; 1239 };
829 1240
diff --git a/arch/arm/boot/dts/sama5d36.dtsi b/arch/arm/boot/dts/sama5d36.dtsi
new file mode 100644
index 000000000000..6c31c26e6cc0
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d36.dtsi
@@ -0,0 +1,20 @@
1/*
2 * sama5d36.dtsi - Device Tree Include file for SAMA5D36 SoC
3 *
4 * Copyright (C) 2013 Atmel,
5 * 2013 Josh Wu <josh.wu@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9#include "sama5d3.dtsi"
10#include "sama5d3_can.dtsi"
11#include "sama5d3_emac.dtsi"
12#include "sama5d3_gmac.dtsi"
13#include "sama5d3_lcd.dtsi"
14#include "sama5d3_mci2.dtsi"
15#include "sama5d3_tcb1.dtsi"
16#include "sama5d3_uart.dtsi"
17
18/ {
19 compatible = "atmel,samad36", "atmel,sama5d3", "atmel,sama5";
20};
diff --git a/arch/arm/boot/dts/sama5d36ek.dts b/arch/arm/boot/dts/sama5d36ek.dts
new file mode 100644
index 000000000000..59576c6f9826
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d36ek.dts
@@ -0,0 +1,53 @@
1/*
2 * sama5d36ek.dts - Device Tree file for SAMA5D36-EK board
3 *
4 * Copyright (C) 2013 Atmel,
5 * 2013 Josh Wu <josh.wu@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9/dts-v1/;
10#include "sama5d36.dtsi"
11#include "sama5d3xmb.dtsi"
12#include "sama5d3xdm.dtsi"
13
14/ {
15 model = "Atmel SAMA5D36-EK";
16 compatible = "atmel,sama5d36ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d36", "atmel,sama5d3", "atmel,sama5";
17
18 ahb {
19 apb {
20 spi0: spi@f0004000 {
21 status = "okay";
22 };
23
24 ssc0: ssc@f0008000 {
25 status = "okay";
26 };
27
28 can0: can@f000c000 {
29 status = "okay";
30 };
31
32 i2c0: i2c@f0014000 {
33 status = "okay";
34 };
35
36 i2c1: i2c@f0018000 {
37 status = "okay";
38 };
39
40 macb0: ethernet@f0028000 {
41 status = "okay";
42 };
43
44 macb1: ethernet@f802c000 {
45 status = "okay";
46 };
47 };
48 };
49
50 sound {
51 status = "okay";
52 };
53};
diff --git a/arch/arm/boot/dts/sama5d3_can.dtsi b/arch/arm/boot/dts/sama5d3_can.dtsi
index 8ed3260cef66..a0775851cce5 100644
--- a/arch/arm/boot/dts/sama5d3_can.dtsi
+++ b/arch/arm/boot/dts/sama5d3_can.dtsi
@@ -32,12 +32,30 @@
32 32
33 }; 33 };
34 34
35 pmc: pmc@fffffc00 {
36 periphck {
37 can0_clk: can0_clk {
38 #clock-cells = <0>;
39 reg = <40>;
40 atmel,clk-output-range = <0 66000000>;
41 };
42
43 can1_clk: can0_clk {
44 #clock-cells = <0>;
45 reg = <41>;
46 atmel,clk-output-range = <0 66000000>;
47 };
48 };
49 };
50
35 can0: can@f000c000 { 51 can0: can@f000c000 {
36 compatible = "atmel,at91sam9x5-can"; 52 compatible = "atmel,at91sam9x5-can";
37 reg = <0xf000c000 0x300>; 53 reg = <0xf000c000 0x300>;
38 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 3>; 54 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 3>;
39 pinctrl-names = "default"; 55 pinctrl-names = "default";
40 pinctrl-0 = <&pinctrl_can0_rx_tx>; 56 pinctrl-0 = <&pinctrl_can0_rx_tx>;
57 clocks = <&can0_clk>;
58 clock-names = "can_clk";
41 status = "disabled"; 59 status = "disabled";
42 }; 60 };
43 61
@@ -47,6 +65,8 @@
47 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 3>; 65 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 3>;
48 pinctrl-names = "default"; 66 pinctrl-names = "default";
49 pinctrl-0 = <&pinctrl_can1_rx_tx>; 67 pinctrl-0 = <&pinctrl_can1_rx_tx>;
68 clocks = <&can1_clk>;
69 clock-names = "can_clk";
50 status = "disabled"; 70 status = "disabled";
51 }; 71 };
52 }; 72 };
diff --git a/arch/arm/boot/dts/sama5d3_emac.dtsi b/arch/arm/boot/dts/sama5d3_emac.dtsi
index 4d4f351f1f9f..fe2af9276312 100644
--- a/arch/arm/boot/dts/sama5d3_emac.dtsi
+++ b/arch/arm/boot/dts/sama5d3_emac.dtsi
@@ -31,12 +31,23 @@
31 }; 31 };
32 }; 32 };
33 33
34 pmc: pmc@fffffc00 {
35 periphck {
36 macb1_clk: macb1_clk {
37 #clock-cells = <0>;
38 reg = <35>;
39 };
40 };
41 };
42
34 macb1: ethernet@f802c000 { 43 macb1: ethernet@f802c000 {
35 compatible = "cdns,at32ap7000-macb", "cdns,macb"; 44 compatible = "cdns,at32ap7000-macb", "cdns,macb";
36 reg = <0xf802c000 0x100>; 45 reg = <0xf802c000 0x100>;
37 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 3>; 46 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 3>;
38 pinctrl-names = "default"; 47 pinctrl-names = "default";
39 pinctrl-0 = <&pinctrl_macb1_rmii>; 48 pinctrl-0 = <&pinctrl_macb1_rmii>;
49 clocks = <&macb1_clk>, <&macb1_clk>;
50 clock-names = "hclk", "pclk";
40 status = "disabled"; 51 status = "disabled";
41 }; 52 };
42 }; 53 };
diff --git a/arch/arm/boot/dts/sama5d3_gmac.dtsi b/arch/arm/boot/dts/sama5d3_gmac.dtsi
index 0ba8be30ccd8..a6cb0508762f 100644
--- a/arch/arm/boot/dts/sama5d3_gmac.dtsi
+++ b/arch/arm/boot/dts/sama5d3_gmac.dtsi
@@ -64,12 +64,23 @@
64 }; 64 };
65 }; 65 };
66 66
67 pmc: pmc@fffffc00 {
68 periphck {
69 macb0_clk: macb0_clk {
70 #clock-cells = <0>;
71 reg = <34>;
72 };
73 };
74 };
75
67 macb0: ethernet@f0028000 { 76 macb0: ethernet@f0028000 {
68 compatible = "cdns,pc302-gem", "cdns,gem"; 77 compatible = "cdns,pc302-gem", "cdns,gem";
69 reg = <0xf0028000 0x100>; 78 reg = <0xf0028000 0x100>;
70 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 3>; 79 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 3>;
71 pinctrl-names = "default"; 80 pinctrl-names = "default";
72 pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>; 81 pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>;
82 clocks = <&macb0_clk>, <&macb0_clk>;
83 clock-names = "hclk", "pclk";
73 status = "disabled"; 84 status = "disabled";
74 }; 85 };
75 }; 86 };
diff --git a/arch/arm/boot/dts/sama5d3_lcd.dtsi b/arch/arm/boot/dts/sama5d3_lcd.dtsi
index 01f52a79f8ba..85d302701565 100644
--- a/arch/arm/boot/dts/sama5d3_lcd.dtsi
+++ b/arch/arm/boot/dts/sama5d3_lcd.dtsi
@@ -50,6 +50,23 @@
50 }; 50 };
51 }; 51 };
52 }; 52 };
53
54 pmc: pmc@fffffc00 {
55 periphck {
56 lcdc_clk: lcdc_clk {
57 #clock-cells = <0>;
58 reg = <36>;
59 };
60 };
61
62 systemck {
63 lcdck: lcdck {
64 #clock-cells = <0>;
65 reg = <3>;
66 clocks = <&mck>;
67 };
68 };
69 };
53 }; 70 };
54 }; 71 };
55}; 72};
diff --git a/arch/arm/boot/dts/sama5d3_mci2.dtsi b/arch/arm/boot/dts/sama5d3_mci2.dtsi
index 38e88e39e551..b029fe7ef17a 100644
--- a/arch/arm/boot/dts/sama5d3_mci2.dtsi
+++ b/arch/arm/boot/dts/sama5d3_mci2.dtsi
@@ -9,6 +9,7 @@
9 9
10#include <dt-bindings/pinctrl/at91.h> 10#include <dt-bindings/pinctrl/at91.h>
11#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/interrupt-controller/irq.h>
12#include <dt-bindings/clk/at91.h>
12 13
13/ { 14/ {
14 ahb { 15 ahb {
@@ -30,6 +31,15 @@
30 }; 31 };
31 }; 32 };
32 33
34 pmc: pmc@fffffc00 {
35 periphck {
36 mci2_clk: mci2_clk {
37 #clock-cells = <0>;
38 reg = <23>;
39 };
40 };
41 };
42
33 mmc2: mmc@f8004000 { 43 mmc2: mmc@f8004000 {
34 compatible = "atmel,hsmci"; 44 compatible = "atmel,hsmci";
35 reg = <0xf8004000 0x600>; 45 reg = <0xf8004000 0x600>;
@@ -38,6 +48,8 @@
38 dma-names = "rxtx"; 48 dma-names = "rxtx";
39 pinctrl-names = "default"; 49 pinctrl-names = "default";
40 pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>; 50 pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>;
51 clocks = <&mci2_clk>;
52 clock-names = "mci_clk";
41 status = "disabled"; 53 status = "disabled";
42 #address-cells = <1>; 54 #address-cells = <1>;
43 #size-cells = <0>; 55 #size-cells = <0>;
diff --git a/arch/arm/boot/dts/sama5d3_tcb1.dtsi b/arch/arm/boot/dts/sama5d3_tcb1.dtsi
index 5264bb4a6998..382b04431f66 100644
--- a/arch/arm/boot/dts/sama5d3_tcb1.dtsi
+++ b/arch/arm/boot/dts/sama5d3_tcb1.dtsi
@@ -9,6 +9,7 @@
9 9
10#include <dt-bindings/pinctrl/at91.h> 10#include <dt-bindings/pinctrl/at91.h>
11#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/interrupt-controller/irq.h>
12#include <dt-bindings/clk/at91.h>
12 13
13/ { 14/ {
14 aliases { 15 aliases {
@@ -17,10 +18,21 @@
17 18
18 ahb { 19 ahb {
19 apb { 20 apb {
21 pmc: pmc@fffffc00 {
22 periphck {
23 tcb1_clk: tcb1_clk {
24 #clock-cells = <0>;
25 reg = <27>;
26 };
27 };
28 };
29
20 tcb1: timer@f8014000 { 30 tcb1: timer@f8014000 {
21 compatible = "atmel,at91sam9x5-tcb"; 31 compatible = "atmel,at91sam9x5-tcb";
22 reg = <0xf8014000 0x100>; 32 reg = <0xf8014000 0x100>;
23 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>; 33 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>;
34 clocks = <&tcb1_clk>;
35 clock-names = "t0_clk";
24 }; 36 };
25 }; 37 };
26 }; 38 };
diff --git a/arch/arm/boot/dts/sama5d3_uart.dtsi b/arch/arm/boot/dts/sama5d3_uart.dtsi
index 98fcb2d57446..a9fa75e41652 100644
--- a/arch/arm/boot/dts/sama5d3_uart.dtsi
+++ b/arch/arm/boot/dts/sama5d3_uart.dtsi
@@ -9,8 +9,14 @@
9 9
10#include <dt-bindings/pinctrl/at91.h> 10#include <dt-bindings/pinctrl/at91.h>
11#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/interrupt-controller/irq.h>
12#include <dt-bindings/clk/at91.h>
12 13
13/ { 14/ {
15 aliases {
16 serial5 = &uart0;
17 serial6 = &uart1;
18 };
19
14 ahb { 20 ahb {
15 apb { 21 apb {
16 pinctrl@fffff200 { 22 pinctrl@fffff200 {
@@ -31,12 +37,30 @@
31 }; 37 };
32 }; 38 };
33 39
40 pmc: pmc@fffffc00 {
41 periphck {
42 uart0_clk: uart0_clk {
43 #clock-cells = <0>;
44 reg = <16>;
45 atmel,clk-output-range = <0 66000000>;
46 };
47
48 uart1_clk: uart1_clk {
49 #clock-cells = <0>;
50 reg = <17>;
51 atmel,clk-output-range = <0 66000000>;
52 };
53 };
54 };
55
34 uart0: serial@f0024000 { 56 uart0: serial@f0024000 {
35 compatible = "atmel,at91sam9260-usart"; 57 compatible = "atmel,at91sam9260-usart";
36 reg = <0xf0024000 0x200>; 58 reg = <0xf0024000 0x200>;
37 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; 59 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
38 pinctrl-names = "default"; 60 pinctrl-names = "default";
39 pinctrl-0 = <&pinctrl_uart0>; 61 pinctrl-0 = <&pinctrl_uart0>;
62 clocks = <&uart0_clk>;
63 clock-names = "usart";
40 status = "disabled"; 64 status = "disabled";
41 }; 65 };
42 66
@@ -46,6 +70,8 @@
46 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>; 70 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>;
47 pinctrl-names = "default"; 71 pinctrl-names = "default";
48 pinctrl-0 = <&pinctrl_uart1>; 72 pinctrl-0 = <&pinctrl_uart1>;
73 clocks = <&uart1_clk>;
74 clock-names = "usart";
49 status = "disabled"; 75 status = "disabled";
50 }; 76 };
51 }; 77 };
diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi
index 726a0f35100c..f55ed072c8e6 100644
--- a/arch/arm/boot/dts/sama5d3xcm.dtsi
+++ b/arch/arm/boot/dts/sama5d3xcm.dtsi
@@ -18,17 +18,6 @@
18 reg = <0x20000000 0x20000000>; 18 reg = <0x20000000 0x20000000>;
19 }; 19 };
20 20
21 clocks {
22 #address-cells = <1>;
23 #size-cells = <1>;
24 ranges;
25
26 main_clock: clock@0 {
27 compatible = "atmel,osc", "fixed-clock";
28 clock-frequency = <12000000>;
29 };
30 };
31
32 ahb { 21 ahb {
33 apb { 22 apb {
34 spi0: spi@f0004000 { 23 spi0: spi@f0004000 {
@@ -38,6 +27,12 @@
38 macb0: ethernet@f0028000 { 27 macb0: ethernet@f0028000 {
39 phy-mode = "rgmii"; 28 phy-mode = "rgmii";
40 }; 29 };
30
31 pmc: pmc@fffffc00 {
32 main: mainck {
33 clock-frequency = <12000000>;
34 };
35 };
41 }; 36 };
42 37
43 nand0: nand@60000000 { 38 nand0: nand@60000000 {
diff --git a/arch/arm/boot/dts/sama5d3xdm.dtsi b/arch/arm/boot/dts/sama5d3xdm.dtsi
index 1c296d6b2f2a..f9bdde542ced 100644
--- a/arch/arm/boot/dts/sama5d3xdm.dtsi
+++ b/arch/arm/boot/dts/sama5d3xdm.dtsi
@@ -18,6 +18,7 @@
18 interrupts = <31 0x0>; 18 interrupts = <31 0x0>;
19 pinctrl-names = "default"; 19 pinctrl-names = "default";
20 pinctrl-0 = <&pinctrl_qt1070_irq>; 20 pinctrl-0 = <&pinctrl_qt1070_irq>;
21 wakeup-source;
21 }; 22 };
22 }; 23 };
23 24
diff --git a/arch/arm/boot/dts/sh7372-mackerel.dts b/arch/arm/boot/dts/sh7372-mackerel.dts
index 8acf51e0cdae..a759a276c9a9 100644
--- a/arch/arm/boot/dts/sh7372-mackerel.dts
+++ b/arch/arm/boot/dts/sh7372-mackerel.dts
@@ -9,7 +9,7 @@
9 */ 9 */
10 10
11/dts-v1/; 11/dts-v1/;
12/include/ "sh7372.dtsi" 12#include "sh7372.dtsi"
13 13
14/ { 14/ {
15 model = "Mackerel (AP4 EVM 2nd)"; 15 model = "Mackerel (AP4 EVM 2nd)";
diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
index 8ee06dd81799..eb8886b535e4 100644
--- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
+++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
@@ -12,8 +12,9 @@
12 */ 12 */
13 13
14/dts-v1/; 14/dts-v1/;
15/include/ "sh73a0.dtsi" 15#include "sh73a0.dtsi"
16#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/gpio/gpio.h>
17#include <dt-bindings/interrupt-controller/irq.h>
17 18
18/ { 19/ {
19 model = "KZM-A9-GT"; 20 model = "KZM-A9-GT";
@@ -82,7 +83,7 @@
82 reg = <0x10000000 0x100>; 83 reg = <0x10000000 0x100>;
83 phy-mode = "mii"; 84 phy-mode = "mii";
84 interrupt-parent = <&irqpin0>; 85 interrupt-parent = <&irqpin0>;
85 interrupts = <3 0>; /* active low */ 86 interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
86 reg-io-width = <4>; 87 reg-io-width = <4>;
87 smsc,irq-push-pull; 88 smsc,irq-push-pull;
88 smsc,save-mac-address; 89 smsc,save-mac-address;
@@ -105,6 +106,66 @@
105 gpios = <&pfc 23 GPIO_ACTIVE_LOW>; 106 gpios = <&pfc 23 GPIO_ACTIVE_LOW>;
106 }; 107 };
107 }; 108 };
109
110 gpio-keys {
111 compatible = "gpio-keys";
112
113 back-key {
114 gpios = <&pcf8575 8 GPIO_ACTIVE_LOW>;
115 linux,code = <158>;
116 label = "SW3";
117 };
118
119 right-key {
120 gpios = <&pcf8575 9 GPIO_ACTIVE_LOW>;
121 linux,code = <106>;
122 label = "SW2-R";
123 };
124
125 left-key {
126 gpios = <&pcf8575 10 GPIO_ACTIVE_LOW>;
127 linux,code = <105>;
128 label = "SW2-L";
129 };
130
131 enter-key {
132 gpios = <&pcf8575 11 GPIO_ACTIVE_LOW>;
133 linux,code = <28>;
134 label = "SW2-P";
135 };
136
137 up-key {
138 gpios = <&pcf8575 12 GPIO_ACTIVE_LOW>;
139 linux,code = <103>;
140 label = "SW2-U";
141 };
142
143 down-key {
144 gpios = <&pcf8575 13 GPIO_ACTIVE_LOW>;
145 linux,code = <108>;
146 label = "SW2-D";
147 };
148
149 home-key {
150 gpios = <&pcf8575 14 GPIO_ACTIVE_LOW>;
151 linux,code = <102>;
152 label = "SW1";
153 };
154 };
155
156 sound {
157 compatible = "simple-audio-card";
158 simple-audio-card,format = "left_j";
159 simple-audio-card,cpu {
160 sound-dai = <&sh_fsi2 0>;
161 };
162 simple-audio-card,codec {
163 sound-dai = <&ak4648>;
164 bitclock-master;
165 frame-master;
166 system-clock-frequency = <11289600>;
167 };
168 };
108}; 169};
109 170
110&i2c0 { 171&i2c0 {
@@ -179,12 +240,29 @@
179 }; 240 };
180 }; 241 };
181 }; 242 };
243
244 ak4648: ak4648@0x12 {
245 #sound-dai-cells = <0>;
246 compatible = "asahi-kasei,ak4648";
247 reg = <0x12>;
248 };
182}; 249};
183 250
184&i2c3 { 251&i2c3 {
185 pinctrl-0 = <&i2c3_pins>; 252 pinctrl-0 = <&i2c3_pins>;
186 pinctrl-names = "default"; 253 pinctrl-names = "default";
187 status = "okay"; 254 status = "okay";
255
256 pcf8575: gpio@20 {
257 compatible = "nxp,pcf8575";
258 reg = <0x20>;
259 interrupt-parent = <&irqpin2>;
260 interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
261 gpio-controller;
262 #gpio-cells = <2>;
263 interrupt-controller;
264 #interrupt-cells = <2>;
265 };
188}; 266};
189 267
190&mmcif { 268&mmcif {
@@ -205,7 +283,7 @@
205 renesas,function = "i2c3"; 283 renesas,function = "i2c3";
206 }; 284 };
207 285
208 mmcif_pins: mmcif { 286 mmcif_pins: mmc {
209 mux { 287 mux {
210 renesas,groups = "mmc0_data8_0", "mmc0_ctrl_0"; 288 renesas,groups = "mmc0_data8_0", "mmc0_ctrl_0";
211 renesas,function = "mmc0"; 289 renesas,function = "mmc0";
@@ -217,20 +295,26 @@
217 }; 295 };
218 }; 296 };
219 297
220 scifa4_pins: scifa4 { 298 scifa4_pins: serial4 {
221 renesas,groups = "scifa4_data", "scifa4_ctrl"; 299 renesas,groups = "scifa4_data", "scifa4_ctrl";
222 renesas,function = "scifa4"; 300 renesas,function = "scifa4";
223 }; 301 };
224 302
225 sdhi0_pins: sdhi0 { 303 sdhi0_pins: sd0 {
226 renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd", "sdhi0_wp"; 304 renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd", "sdhi0_wp";
227 renesas,function = "sdhi0"; 305 renesas,function = "sdhi0";
228 }; 306 };
229 307
230 sdhi2_pins: sdhi2 { 308 sdhi2_pins: sd2 {
231 renesas,groups = "sdhi2_data4", "sdhi2_ctrl"; 309 renesas,groups = "sdhi2_data4", "sdhi2_ctrl";
232 renesas,function = "sdhi2"; 310 renesas,function = "sdhi2";
233 }; 311 };
312
313 fsia_pins: sounda {
314 renesas,groups = "fsia_mclk_in", "fsia_sclk_in",
315 "fsia_data_in", "fsia_data_out";
316 renesas,function = "fsia";
317 };
234}; 318};
235 319
236&sdhi0 { 320&sdhi0 {
@@ -251,3 +335,10 @@
251 broken-cd; 335 broken-cd;
252 status = "okay"; 336 status = "okay";
253}; 337};
338
339&sh_fsi2 {
340 pinctrl-0 = <&fsia_pins>;
341 pinctrl-names = "default";
342
343 status = "okay";
344};
diff --git a/arch/arm/boot/dts/sh73a0-kzm9g.dts b/arch/arm/boot/dts/sh73a0-kzm9g.dts
index 0f1ca7792c46..27c5f426d172 100644
--- a/arch/arm/boot/dts/sh73a0-kzm9g.dts
+++ b/arch/arm/boot/dts/sh73a0-kzm9g.dts
@@ -9,7 +9,7 @@
9 */ 9 */
10 10
11/dts-v1/; 11/dts-v1/;
12/include/ "sh73a0.dtsi" 12#include "sh73a0.dtsi"
13 13
14/ { 14/ {
15 model = "KZM-A9-GT"; 15 model = "KZM-A9-GT";
diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
index fcf26889a8a0..c460dd229b13 100644
--- a/arch/arm/boot/dts/sh73a0.dtsi
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -10,6 +10,8 @@
10 10
11/include/ "skeleton.dtsi" 11/include/ "skeleton.dtsi"
12 12
13#include <dt-bindings/interrupt-controller/irq.h>
14
13/ { 15/ {
14 compatible = "renesas,sh73a0"; 16 compatible = "renesas,sh73a0";
15 17
@@ -40,12 +42,12 @@
40 42
41 pmu { 43 pmu {
42 compatible = "arm,cortex-a9-pmu"; 44 compatible = "arm,cortex-a9-pmu";
43 interrupts = <0 55 4>, 45 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>,
44 <0 56 4>; 46 <0 56 IRQ_TYPE_LEVEL_HIGH>;
45 }; 47 };
46 48
47 irqpin0: irqpin@e6900000 { 49 irqpin0: irqpin@e6900000 {
48 compatible = "renesas,intc-irqpin"; 50 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
49 #interrupt-cells = <2>; 51 #interrupt-cells = <2>;
50 interrupt-controller; 52 interrupt-controller;
51 reg = <0xe6900000 4>, 53 reg = <0xe6900000 4>,
@@ -54,18 +56,18 @@
54 <0xe6900040 1>, 56 <0xe6900040 1>,
55 <0xe6900060 1>; 57 <0xe6900060 1>;
56 interrupt-parent = <&gic>; 58 interrupt-parent = <&gic>;
57 interrupts = <0 1 0x4 59 interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH
58 0 2 0x4 60 0 2 IRQ_TYPE_LEVEL_HIGH
59 0 3 0x4 61 0 3 IRQ_TYPE_LEVEL_HIGH
60 0 4 0x4 62 0 4 IRQ_TYPE_LEVEL_HIGH
61 0 5 0x4 63 0 5 IRQ_TYPE_LEVEL_HIGH
62 0 6 0x4 64 0 6 IRQ_TYPE_LEVEL_HIGH
63 0 7 0x4 65 0 7 IRQ_TYPE_LEVEL_HIGH
64 0 8 0x4>; 66 0 8 IRQ_TYPE_LEVEL_HIGH>;
65 }; 67 };
66 68
67 irqpin1: irqpin@e6900004 { 69 irqpin1: irqpin@e6900004 {
68 compatible = "renesas,intc-irqpin"; 70 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
69 #interrupt-cells = <2>; 71 #interrupt-cells = <2>;
70 interrupt-controller; 72 interrupt-controller;
71 reg = <0xe6900004 4>, 73 reg = <0xe6900004 4>,
@@ -74,19 +76,19 @@
74 <0xe6900044 1>, 76 <0xe6900044 1>,
75 <0xe6900064 1>; 77 <0xe6900064 1>;
76 interrupt-parent = <&gic>; 78 interrupt-parent = <&gic>;
77 interrupts = <0 9 0x4 79 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH
78 0 10 0x4 80 0 10 IRQ_TYPE_LEVEL_HIGH
79 0 11 0x4 81 0 11 IRQ_TYPE_LEVEL_HIGH
80 0 12 0x4 82 0 12 IRQ_TYPE_LEVEL_HIGH
81 0 13 0x4 83 0 13 IRQ_TYPE_LEVEL_HIGH
82 0 14 0x4 84 0 14 IRQ_TYPE_LEVEL_HIGH
83 0 15 0x4 85 0 15 IRQ_TYPE_LEVEL_HIGH
84 0 16 0x4>; 86 0 16 IRQ_TYPE_LEVEL_HIGH>;
85 control-parent; 87 control-parent;
86 }; 88 };
87 89
88 irqpin2: irqpin@e6900008 { 90 irqpin2: irqpin@e6900008 {
89 compatible = "renesas,intc-irqpin"; 91 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
90 #interrupt-cells = <2>; 92 #interrupt-cells = <2>;
91 interrupt-controller; 93 interrupt-controller;
92 reg = <0xe6900008 4>, 94 reg = <0xe6900008 4>,
@@ -95,18 +97,18 @@
95 <0xe6900048 1>, 97 <0xe6900048 1>,
96 <0xe6900068 1>; 98 <0xe6900068 1>;
97 interrupt-parent = <&gic>; 99 interrupt-parent = <&gic>;
98 interrupts = <0 17 0x4 100 interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH
99 0 18 0x4 101 0 18 IRQ_TYPE_LEVEL_HIGH
100 0 19 0x4 102 0 19 IRQ_TYPE_LEVEL_HIGH
101 0 20 0x4 103 0 20 IRQ_TYPE_LEVEL_HIGH
102 0 21 0x4 104 0 21 IRQ_TYPE_LEVEL_HIGH
103 0 22 0x4 105 0 22 IRQ_TYPE_LEVEL_HIGH
104 0 23 0x4 106 0 23 IRQ_TYPE_LEVEL_HIGH
105 0 24 0x4>; 107 0 24 IRQ_TYPE_LEVEL_HIGH>;
106 }; 108 };
107 109
108 irqpin3: irqpin@e690000c { 110 irqpin3: irqpin@e690000c {
109 compatible = "renesas,intc-irqpin"; 111 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
110 #interrupt-cells = <2>; 112 #interrupt-cells = <2>;
111 interrupt-controller; 113 interrupt-controller;
112 reg = <0xe690000c 4>, 114 reg = <0xe690000c 4>,
@@ -115,14 +117,14 @@
115 <0xe690004c 1>, 117 <0xe690004c 1>,
116 <0xe690006c 1>; 118 <0xe690006c 1>;
117 interrupt-parent = <&gic>; 119 interrupt-parent = <&gic>;
118 interrupts = <0 25 0x4 120 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH
119 0 26 0x4 121 0 26 IRQ_TYPE_LEVEL_HIGH
120 0 27 0x4 122 0 27 IRQ_TYPE_LEVEL_HIGH
121 0 28 0x4 123 0 28 IRQ_TYPE_LEVEL_HIGH
122 0 29 0x4 124 0 29 IRQ_TYPE_LEVEL_HIGH
123 0 30 0x4 125 0 30 IRQ_TYPE_LEVEL_HIGH
124 0 31 0x4 126 0 31 IRQ_TYPE_LEVEL_HIGH
125 0 32 0x4>; 127 0 32 IRQ_TYPE_LEVEL_HIGH>;
126 }; 128 };
127 129
128 i2c0: i2c@e6820000 { 130 i2c0: i2c@e6820000 {
@@ -131,10 +133,10 @@
131 compatible = "renesas,rmobile-iic"; 133 compatible = "renesas,rmobile-iic";
132 reg = <0xe6820000 0x425>; 134 reg = <0xe6820000 0x425>;
133 interrupt-parent = <&gic>; 135 interrupt-parent = <&gic>;
134 interrupts = <0 167 0x4 136 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH
135 0 168 0x4 137 0 168 IRQ_TYPE_LEVEL_HIGH
136 0 169 0x4 138 0 169 IRQ_TYPE_LEVEL_HIGH
137 0 170 0x4>; 139 0 170 IRQ_TYPE_LEVEL_HIGH>;
138 status = "disabled"; 140 status = "disabled";
139 }; 141 };
140 142
@@ -144,10 +146,10 @@
144 compatible = "renesas,rmobile-iic"; 146 compatible = "renesas,rmobile-iic";
145 reg = <0xe6822000 0x425>; 147 reg = <0xe6822000 0x425>;
146 interrupt-parent = <&gic>; 148 interrupt-parent = <&gic>;
147 interrupts = <0 51 0x4 149 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH
148 0 52 0x4 150 0 52 IRQ_TYPE_LEVEL_HIGH
149 0 53 0x4 151 0 53 IRQ_TYPE_LEVEL_HIGH
150 0 54 0x4>; 152 0 54 IRQ_TYPE_LEVEL_HIGH>;
151 status = "disabled"; 153 status = "disabled";
152 }; 154 };
153 155
@@ -157,10 +159,10 @@
157 compatible = "renesas,rmobile-iic"; 159 compatible = "renesas,rmobile-iic";
158 reg = <0xe6824000 0x425>; 160 reg = <0xe6824000 0x425>;
159 interrupt-parent = <&gic>; 161 interrupt-parent = <&gic>;
160 interrupts = <0 171 0x4 162 interrupts = <0 171 IRQ_TYPE_LEVEL_HIGH
161 0 172 0x4 163 0 172 IRQ_TYPE_LEVEL_HIGH
162 0 173 0x4 164 0 173 IRQ_TYPE_LEVEL_HIGH
163 0 174 0x4>; 165 0 174 IRQ_TYPE_LEVEL_HIGH>;
164 status = "disabled"; 166 status = "disabled";
165 }; 167 };
166 168
@@ -170,10 +172,10 @@
170 compatible = "renesas,rmobile-iic"; 172 compatible = "renesas,rmobile-iic";
171 reg = <0xe6826000 0x425>; 173 reg = <0xe6826000 0x425>;
172 interrupt-parent = <&gic>; 174 interrupt-parent = <&gic>;
173 interrupts = <0 183 0x4 175 interrupts = <0 183 IRQ_TYPE_LEVEL_HIGH
174 0 184 0x4 176 0 184 IRQ_TYPE_LEVEL_HIGH
175 0 185 0x4 177 0 185 IRQ_TYPE_LEVEL_HIGH
176 0 186 0x4>; 178 0 186 IRQ_TYPE_LEVEL_HIGH>;
177 status = "disabled"; 179 status = "disabled";
178 }; 180 };
179 181
@@ -183,52 +185,52 @@
183 compatible = "renesas,rmobile-iic"; 185 compatible = "renesas,rmobile-iic";
184 reg = <0xe6828000 0x425>; 186 reg = <0xe6828000 0x425>;
185 interrupt-parent = <&gic>; 187 interrupt-parent = <&gic>;
186 interrupts = <0 187 0x4 188 interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH
187 0 188 0x4 189 0 188 IRQ_TYPE_LEVEL_HIGH
188 0 189 0x4 190 0 189 IRQ_TYPE_LEVEL_HIGH
189 0 190 0x4>; 191 0 190 IRQ_TYPE_LEVEL_HIGH>;
190 status = "disabled"; 192 status = "disabled";
191 }; 193 };
192 194
193 mmcif: mmcif@e6bd0000 { 195 mmcif: mmc@e6bd0000 {
194 compatible = "renesas,sh-mmcif"; 196 compatible = "renesas,sh-mmcif";
195 reg = <0xe6bd0000 0x100>; 197 reg = <0xe6bd0000 0x100>;
196 interrupt-parent = <&gic>; 198 interrupt-parent = <&gic>;
197 interrupts = <0 140 0x4 199 interrupts = <0 140 IRQ_TYPE_LEVEL_HIGH
198 0 141 0x4>; 200 0 141 IRQ_TYPE_LEVEL_HIGH>;
199 reg-io-width = <4>; 201 reg-io-width = <4>;
200 status = "disabled"; 202 status = "disabled";
201 }; 203 };
202 204
203 sdhi0: sdhi@ee100000 { 205 sdhi0: sd@ee100000 {
204 compatible = "renesas,sdhi-r8a7740"; 206 compatible = "renesas,sdhi-sh73a0";
205 reg = <0xee100000 0x100>; 207 reg = <0xee100000 0x100>;
206 interrupt-parent = <&gic>; 208 interrupt-parent = <&gic>;
207 interrupts = <0 83 4 209 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH
208 0 84 4 210 0 84 IRQ_TYPE_LEVEL_HIGH
209 0 85 4>; 211 0 85 IRQ_TYPE_LEVEL_HIGH>;
210 cap-sd-highspeed; 212 cap-sd-highspeed;
211 status = "disabled"; 213 status = "disabled";
212 }; 214 };
213 215
214 /* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */ 216 /* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */
215 sdhi1: sdhi@ee120000 { 217 sdhi1: sd@ee120000 {
216 compatible = "renesas,sdhi-r8a7740"; 218 compatible = "renesas,sdhi-sh73a0";
217 reg = <0xee120000 0x100>; 219 reg = <0xee120000 0x100>;
218 interrupt-parent = <&gic>; 220 interrupt-parent = <&gic>;
219 interrupts = <0 88 4 221 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH
220 0 89 4>; 222 0 89 IRQ_TYPE_LEVEL_HIGH>;
221 toshiba,mmc-wrprotect-disable; 223 toshiba,mmc-wrprotect-disable;
222 cap-sd-highspeed; 224 cap-sd-highspeed;
223 status = "disabled"; 225 status = "disabled";
224 }; 226 };
225 227
226 sdhi2: sdhi@ee140000 { 228 sdhi2: sd@ee140000 {
227 compatible = "renesas,sdhi-r8a7740"; 229 compatible = "renesas,sdhi-sh73a0";
228 reg = <0xee140000 0x100>; 230 reg = <0xee140000 0x100>;
229 interrupt-parent = <&gic>; 231 interrupt-parent = <&gic>;
230 interrupts = <0 104 4 232 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH
231 0 105 4>; 233 0 105 IRQ_TYPE_LEVEL_HIGH>;
232 toshiba,mmc-wrprotect-disable; 234 toshiba,mmc-wrprotect-disable;
233 cap-sd-highspeed; 235 cap-sd-highspeed;
234 status = "disabled"; 236 status = "disabled";
@@ -241,4 +243,13 @@
241 gpio-controller; 243 gpio-controller;
242 #gpio-cells = <2>; 244 #gpio-cells = <2>;
243 }; 245 };
246
247 sh_fsi2: sound@ec230000 {
248 #sound-dai-cells = <1>;
249 compatible = "renesas,sh_fsi2";
250 reg = <0xec230000 0x400>;
251 interrupt-parent = <&gic>;
252 interrupts = <0 146 0x4>;
253 status = "disabled";
254 };
244}; 255};
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 6d09b8d42fdd..f936476c2753 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -245,14 +245,14 @@
245 245
246 mpu_periph_clk: mpu_periph_clk { 246 mpu_periph_clk: mpu_periph_clk {
247 #clock-cells = <0>; 247 #clock-cells = <0>;
248 compatible = "altr,socfpga-gate-clk"; 248 compatible = "altr,socfpga-perip-clk";
249 clocks = <&mpuclk>; 249 clocks = <&mpuclk>;
250 fixed-divider = <4>; 250 fixed-divider = <4>;
251 }; 251 };
252 252
253 mpu_l2_ram_clk: mpu_l2_ram_clk { 253 mpu_l2_ram_clk: mpu_l2_ram_clk {
254 #clock-cells = <0>; 254 #clock-cells = <0>;
255 compatible = "altr,socfpga-gate-clk"; 255 compatible = "altr,socfpga-perip-clk";
256 clocks = <&mpuclk>; 256 clocks = <&mpuclk>;
257 fixed-divider = <2>; 257 fixed-divider = <2>;
258 }; 258 };
@@ -266,8 +266,9 @@
266 266
267 l3_main_clk: l3_main_clk { 267 l3_main_clk: l3_main_clk {
268 #clock-cells = <0>; 268 #clock-cells = <0>;
269 compatible = "altr,socfpga-gate-clk"; 269 compatible = "altr,socfpga-perip-clk";
270 clocks = <&mainclk>; 270 clocks = <&mainclk>;
271 fixed-divider = <1>;
271 }; 272 };
272 273
273 l3_mp_clk: l3_mp_clk { 274 l3_mp_clk: l3_mp_clk {
diff --git a/arch/arm/boot/dts/st-pincfg.h b/arch/arm/boot/dts/st-pincfg.h
index 8c45d85ac13e..4851c387d52d 100644
--- a/arch/arm/boot/dts/st-pincfg.h
+++ b/arch/arm/boot/dts/st-pincfg.h
@@ -15,7 +15,7 @@
15/* Pull Up */ 15/* Pull Up */
16#define PU (1 << 26) 16#define PU (1 << 26)
17/* Open Drain */ 17/* Open Drain */
18#define OD (1 << 26) 18#define OD (1 << 25)
19#define RT (1 << 23) 19#define RT (1 << 23)
20#define INVERTCLK (1 << 22) 20#define INVERTCLK (1 << 22)
21#define CLKNOTDATA (1 << 21) 21#define CLKNOTDATA (1 << 21)
diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi
index 7da99fe497e1..e0853ea02df2 100644
--- a/arch/arm/boot/dts/ste-dbx5x0.dtsi
+++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi
@@ -913,6 +913,10 @@
913 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; 913 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
914 v-ape-supply = <&db8500_vape_reg>; 914 v-ape-supply = <&db8500_vape_reg>;
915 915
916 dmas = <&dma 31 0 0x12>, /* Logical - DevToMem - HighPrio */
917 <&dma 31 0 0x10>; /* Logical - MemToDev - HighPrio */
918 dma-names = "rx", "tx";
919
916 clocks = <&prcc_kclk 1 3>, <&prcc_pclk 1 3>; 920 clocks = <&prcc_kclk 1 3>, <&prcc_pclk 1 3>;
917 clock-names = "msp", "apb_pclk"; 921 clock-names = "msp", "apb_pclk";
918 922
@@ -925,6 +929,9 @@
925 interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>; 929 interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
926 v-ape-supply = <&db8500_vape_reg>; 930 v-ape-supply = <&db8500_vape_reg>;
927 931
932 dmas = <&dma 30 0 0x10>; /* Logical - MemToDev - HighPrio */
933 dma-names = "tx";
934
928 clocks = <&prcc_kclk 1 4>, <&prcc_pclk 1 4>; 935 clocks = <&prcc_kclk 1 4>, <&prcc_pclk 1 4>;
929 clock-names = "msp", "apb_pclk"; 936 clock-names = "msp", "apb_pclk";
930 937
@@ -938,6 +945,11 @@
938 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; 945 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
939 v-ape-supply = <&db8500_vape_reg>; 946 v-ape-supply = <&db8500_vape_reg>;
940 947
948 dmas = <&dma 14 0 0x12>, /* Logical - DevToMem - HighPrio */
949 <&dma 14 1 0x19>; /* Physical Chan 1 - MemToDev
950 HighPrio - Fixed */
951 dma-names = "rx", "tx";
952
941 clocks = <&prcc_kclk 2 3>, <&prcc_pclk 2 5>; 953 clocks = <&prcc_kclk 2 3>, <&prcc_pclk 2 5>;
942 clock-names = "msp", "apb_pclk"; 954 clock-names = "msp", "apb_pclk";
943 955
@@ -950,6 +962,9 @@
950 interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>; 962 interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
951 v-ape-supply = <&db8500_vape_reg>; 963 v-ape-supply = <&db8500_vape_reg>;
952 964
965 dmas = <&dma 30 0 0x12>; /* Logical - DevToMem - HighPrio */
966 dma-names = "rx";
967
953 clocks = <&prcc_kclk 1 10>, <&prcc_pclk 1 11>; 968 clocks = <&prcc_kclk 1 10>, <&prcc_pclk 1 11>;
954 clock-names = "msp", "apb_pclk"; 969 clock-names = "msp", "apb_pclk";
955 970
@@ -987,6 +1002,23 @@
987 status = "disabled"; 1002 status = "disabled";
988 }; 1003 };
989 1004
1005 mcde@a0350000 {
1006 compatible = "stericsson,mcde";
1007 reg = <0xa0350000 0x1000>, /* MCDE */
1008 <0xa0351000 0x1000>, /* DSI link 1 */
1009 <0xa0352000 0x1000>, /* DSI link 2 */
1010 <0xa0353000 0x1000>; /* DSI link 3 */
1011 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
1012 clocks = <&prcmu_clk PRCMU_MCDECLK>, /* Main MCDE clock */
1013 <&prcmu_clk PRCMU_LCDCLK>, /* LCD clock */
1014 <&prcmu_clk PRCMU_PLLDSI>, /* HDMI clock */
1015 <&prcmu_clk PRCMU_DSI0CLK>, /* DSI 0 */
1016 <&prcmu_clk PRCMU_DSI1CLK>, /* DSI 1 */
1017 <&prcmu_clk PRCMU_DSI0ESCCLK>, /* TVout clock 0 */
1018 <&prcmu_clk PRCMU_DSI1ESCCLK>, /* TVout clock 1 */
1019 <&prcmu_clk PRCMU_DSI2ESCCLK>; /* TVout clock 2 */
1020 };
1021
990 cryp@a03cb000 { 1022 cryp@a03cb000 {
991 compatible = "stericsson,ux500-cryp"; 1023 compatible = "stericsson,ux500-cryp";
992 reg = <0xa03cb000 0x1000>; 1024 reg = <0xa03cb000 0x1000>;
diff --git a/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi b/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi
new file mode 100644
index 000000000000..addfcc7c2750
--- /dev/null
+++ b/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi
@@ -0,0 +1,745 @@
1/*
2 * Copyright 2013 Linaro Ltd.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include "ste-nomadik-pinctrl.dtsi"
13
14/ {
15 soc {
16 pinctrl {
17 /* Settings for all UART default and sleep states */
18 uart0 {
19 uart0_default_mode: uart0_default {
20 default_mux {
21 ste,function = "u0";
22 ste,pins = "u0_a_1";
23 };
24 default_cfg1 {
25 ste,pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
26 ste,config = <&in_pu>;
27 };
28
29 default_cfg2 {
30 ste,pins = "GPIO1_AJ3", "GPIO3_AH3"; /* RTS+TXD */
31 ste,config = <&out_hi>;
32 };
33 };
34
35 uart0_sleep_mode: uart0_sleep {
36 sleep_cfg1 {
37 ste,pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
38 ste,config = <&slpm_in_wkup_pdis>;
39 };
40
41 sleep_cfg2 {
42 ste,pins = "GPIO1_AJ3"; /* RTS */
43 ste,config = <&slpm_out_hi_wkup_pdis>;
44 };
45
46 sleep_cfg3 {
47 ste,pins = "GPIO3_AH3"; /* TXD */
48 ste,config = <&slpm_out_wkup_pdis>;
49 };
50 };
51 };
52
53 uart1 {
54 uart1_default_mode: uart1_default {
55 default_mux {
56 ste,function = "u1";
57 ste,pins = "u1rxtx_a_1";
58 };
59 default_cfg1 {
60 ste,pins = "GPIO4_AH6"; /* RXD */
61 ste,config = <&in_pu>;
62 };
63
64 default_cfg2 {
65 ste,pins = "GPIO5_AG6"; /* TXD */
66 ste,config = <&out_hi>;
67 };
68 };
69
70 uart1_sleep_mode: uart1_sleep {
71 sleep_cfg1 {
72 ste,pins = "GPIO4_AH6"; /* RXD */
73 ste,config = <&slpm_in_wkup_pdis>;
74 };
75
76 sleep_cfg2 {
77 ste,pins = "GPIO5_AG6"; /* TXD */
78 ste,config = <&slpm_out_wkup_pdis>;
79 };
80 };
81 };
82
83 uart2 {
84 uart2_default_mode: uart2_default {
85 default_mux {
86 ste,function = "u2";
87 ste,pins = "u2rxtx_c_1";
88 };
89 default_cfg1 {
90 ste,pins = "GPIO29_W2"; /* RXD */
91 ste,config = <&in_pu>;
92 };
93
94 default_cfg2 {
95 ste,pins = "GPIO30_W3"; /* TXD */
96 ste,config = <&out_hi>;
97 };
98 };
99
100 uart2_sleep_mode: uart2_sleep {
101 sleep_cfg1 {
102 ste,pins = "GPIO29_W2"; /* RXD */
103 ste,config = <&in_wkup_pdis>;
104 };
105
106 sleep_cfg2 {
107 ste,pins = "GPIO30_W3"; /* TXD */
108 ste,config = <&out_wkup_pdis>;
109 };
110 };
111 };
112
113 /* Settings for all I2C default and sleep states */
114 i2c0 {
115 i2c0_default_mode: i2c_default {
116 default_mux {
117 ste,function = "i2c0";
118 ste,pins = "i2c0_a_1";
119 };
120 default_cfg1 {
121 ste,pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */
122 ste,config = <&in_pu>;
123 };
124 };
125
126 i2c0_sleep_mode: i2c_sleep {
127 sleep_cfg1 {
128 ste,pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */
129 ste,config = <&slpm_in_wkup_pdis>;
130 };
131 };
132 };
133
134 i2c1 {
135 i2c1_default_mode: i2c_default {
136 default_mux {
137 ste,function = "i2c1";
138 ste,pins = "i2c1_b_2";
139 };
140 default_cfg1 {
141 ste,pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */
142 ste,config = <&in_pu>;
143 };
144 };
145
146 i2c1_sleep_mode: i2c_sleep {
147 sleep_cfg1 {
148 ste,pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */
149 ste,config = <&slpm_in_wkup_pdis>;
150 };
151 };
152 };
153
154 i2c2 {
155 i2c2_default_mode: i2c_default {
156 default_mux {
157 ste,function = "i2c2";
158 ste,pins = "i2c2_b_2";
159 };
160 default_cfg1 {
161 ste,pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */
162 ste,config = <&in_pu>;
163 };
164 };
165
166 i2c2_sleep_mode: i2c_sleep {
167 sleep_cfg1 {
168 ste,pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */
169 ste,config = <&slpm_in_wkup_pdis>;
170 };
171 };
172 };
173
174 i2c3 {
175 i2c3_default_mode: i2c_default {
176 default_mux {
177 ste,function = "i2c3";
178 ste,pins = "i2c3_c_2";
179 };
180 default_cfg1 {
181 ste,pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */
182 ste,config = <&in_pu>;
183 };
184 };
185
186 i2c3_sleep_mode: i2c_sleep {
187 sleep_cfg1 {
188 ste,pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */
189 ste,config = <&slpm_in_wkup_pdis>;
190 };
191 };
192 };
193
194 /*
195 * Activating I2C4 will conflict with UART1 about the same pins so do not
196 * enable I2C4 and UART1 at the same time.
197 */
198 i2c4 {
199 i2c4_default_mode: i2c_default {
200 default_mux {
201 ste,function = "i2c4";
202 ste,pins = "i2c4_b_1";
203 };
204 default_cfg1 {
205 ste,pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */
206 ste,config = <&in_pu>;
207 };
208 };
209
210 i2c4_sleep_mode: i2c_sleep {
211 sleep_cfg1 {
212 ste,pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */
213 ste,config = <&slpm_in_wkup_pdis>;
214 };
215 };
216 };
217
218 /* Settings for all SPI default and sleep states */
219 spi2 {
220 spi2_default_mode: spi_default {
221 default_mux {
222 ste,function = "spi2";
223 ste,pins = "spi2_oc1_2";
224 };
225 default_cfg1 {
226 ste,pins = "GPIO216_AG12"; /* FRM */
227 ste,config = <&gpio_out_hi>;
228 };
229 default_cfg2 {
230 ste,pins = "GPIO218_AH11"; /* RXD */
231 ste,config = <&in_pd>;
232 };
233 default_cfg3 {
234 ste,pins =
235 "GPIO215_AH13", /* TXD */
236 "GPIO217_AH12"; /* CLK */
237 ste,config = <&out_lo>;
238 };
239 };
240
241 spi2_idle_mode: spi_idle {
242 /*
243 * The idle mode is basically sleep mode sans wakeups. Also
244 * note that we have muxes the pins off the function here
245 * as we do not state any muxing.
246 */
247 idle_cfg1 {
248 ste,pins = "GPIO218_AH11"; /* RXD */
249 ste,config = <&slpm_in_pdis>;
250 };
251 idle_cfg2 {
252 ste,pins = "GPIO215_AH13"; /* TXD */
253 ste,config = <&slpm_out_lo_pdis>;
254 };
255 idle_cfg3 {
256 ste,pins = "GPIO217_AH12"; /* CLK */
257 ste,config = <&slpm_pdis>;
258 };
259 };
260
261 spi2_sleep_mode: spi_sleep {
262 sleep_cfg1 {
263 ste,pins =
264 "GPIO216_AG12", /* FRM */
265 "GPIO218_AH11"; /* RXD */
266 ste,config = <&slpm_in_wkup_pdis>;
267 };
268 sleep_cfg2 {
269 ste,pins = "GPIO215_AH13"; /* TXD */
270 ste,config = <&slpm_out_lo_wkup_pdis>;
271 };
272 sleep_cfg3 {
273 ste,pins = "GPIO217_AH12"; /* CLK */
274 ste,config = <&slpm_wkup_pdis>;
275 };
276 };
277 };
278
279 /* Settings for all MMC/SD/SDIO default and sleep states */
280 sdi0 {
281 /* This is the external SD card slot, 4 bits wide */
282 sdi0_default_mode: sdi0_default {
283 default_mux {
284 ste,function = "mc0";
285 ste,pins = "mc0_a_1";
286 };
287 default_cfg1 {
288 ste,pins =
289 "GPIO18_AC2", /* CMDDIR */
290 "GPIO19_AC1", /* DAT0DIR */
291 "GPIO20_AB4"; /* DAT2DIR */
292 ste,config = <&out_hi>;
293 };
294 default_cfg2 {
295 ste,pins = "GPIO22_AA3"; /* FBCLK */
296 ste,config = <&in_nopull>;
297 };
298 default_cfg3 {
299 ste,pins = "GPIO23_AA4"; /* CLK */
300 ste,config = <&out_lo>;
301 };
302 default_cfg4 {
303 ste,pins =
304 "GPIO24_AB2", /* CMD */
305 "GPIO25_Y4", /* DAT0 */
306 "GPIO26_Y2", /* DAT1 */
307 "GPIO27_AA2", /* DAT2 */
308 "GPIO28_AA1"; /* DAT3 */
309 ste,config = <&in_pu>;
310 };
311 };
312
313 sdi0_sleep_mode: sdi0_sleep {
314 sleep_cfg1 {
315 ste,pins =
316 "GPIO18_AC2", /* CMDDIR */
317 "GPIO19_AC1", /* DAT0DIR */
318 "GPIO20_AB4"; /* DAT2DIR */
319 ste,config = <&slpm_out_hi_wkup_pdis>;
320 };
321 sleep_cfg2 {
322 ste,pins =
323 "GPIO22_AA3", /* FBCLK */
324 "GPIO24_AB2", /* CMD */
325 "GPIO25_Y4", /* DAT0 */
326 "GPIO26_Y2", /* DAT1 */
327 "GPIO27_AA2", /* DAT2 */
328 "GPIO28_AA1"; /* DAT3 */
329 ste,config = <&slpm_in_wkup_pdis>;
330 };
331 sleep_cfg3 {
332 ste,pins = "GPIO23_AA4"; /* CLK */
333 ste,config = <&slpm_out_lo_wkup_pdis>;
334 };
335 };
336 };
337
338 sdi1 {
339 /* This is the WLAN SDIO 4 bits wide */
340 sdi1_default_mode: sdi1_default {
341 default_mux {
342 ste,function = "mc1";
343 ste,pins = "mc1_a_1";
344 };
345 default_cfg1 {
346 ste,pins = "GPIO208_AH16"; /* CLK */
347 ste,config = <&out_lo>;
348 };
349 default_cfg2 {
350 ste,pins = "GPIO209_AG15"; /* FBCLK */
351 ste,config = <&in_nopull>;
352 };
353 default_cfg3 {
354 ste,pins =
355 "GPIO210_AJ15", /* CMD */
356 "GPIO211_AG14", /* DAT0 */
357 "GPIO212_AF13", /* DAT1 */
358 "GPIO213_AG13", /* DAT2 */
359 "GPIO214_AH15"; /* DAT3 */
360 ste,config = <&in_pu>;
361 };
362 };
363
364 sdi1_sleep_mode: sdi1_sleep {
365 sleep_cfg1 {
366 ste,pins = "GPIO208_AH16"; /* CLK */
367 ste,config = <&slpm_out_lo_wkup_pdis>;
368 };
369 sleep_cfg2 {
370 ste,pins =
371 "GPIO209_AG15", /* FBCLK */
372 "GPIO210_AJ15", /* CMD */
373 "GPIO211_AG14", /* DAT0 */
374 "GPIO212_AF13", /* DAT1 */
375 "GPIO213_AG13", /* DAT2 */
376 "GPIO214_AH15"; /* DAT3 */
377 ste,config = <&slpm_in_wkup_pdis>;
378 };
379 };
380 };
381
382 sdi2 {
383 /* This is the eMMC 8 bits wide, usually PoP eMMC */
384 sdi2_default_mode: sdi2_default {
385 default_mux {
386 ste,function = "mc2";
387 ste,pins = "mc2_a_1";
388 };
389 default_cfg1 {
390 ste,pins = "GPIO128_A5"; /* CLK */
391 ste,config = <&out_lo>;
392 };
393 default_cfg2 {
394 ste,pins = "GPIO130_C8"; /* FBCLK */
395 ste,config = <&in_nopull>;
396 };
397 default_cfg3 {
398 ste,pins =
399 "GPIO129_B4", /* CMD */
400 "GPIO131_A12", /* DAT0 */
401 "GPIO132_C10", /* DAT1 */
402 "GPIO133_B10", /* DAT2 */
403 "GPIO134_B9", /* DAT3 */
404 "GPIO135_A9", /* DAT4 */
405 "GPIO136_C7", /* DAT5 */
406 "GPIO137_A7", /* DAT6 */
407 "GPIO138_C5"; /* DAT7 */
408 ste,config = <&in_pu>;
409 };
410 };
411
412 sdi2_sleep_mode: sdi2_sleep {
413 sleep_cfg1 {
414 ste,pins = "GPIO128_A5"; /* CLK */
415 ste,config = <&out_lo_wkup_pdis>;
416 };
417 sleep_cfg2 {
418 ste,pins =
419 "GPIO130_C8", /* FBCLK */
420 "GPIO129_B4"; /* CMD */
421 ste,config = <&in_wkup_pdis_en>;
422 };
423 sleep_cfg3 {
424 ste,pins =
425 "GPIO131_A12", /* DAT0 */
426 "GPIO132_C10", /* DAT1 */
427 "GPIO133_B10", /* DAT2 */
428 "GPIO134_B9", /* DAT3 */
429 "GPIO135_A9", /* DAT4 */
430 "GPIO136_C7", /* DAT5 */
431 "GPIO137_A7", /* DAT6 */
432 "GPIO138_C5"; /* DAT7 */
433 ste,config = <&in_wkup_pdis>;
434 };
435 };
436 };
437
438 sdi4 {
439 /* This is the eMMC 8 bits wide, usually PCB-mounted eMMC */
440 sdi4_default_mode: sdi4_default {
441 default_mux {
442 ste,function = "mc4";
443 ste,pins = "mc4_a_1";
444 };
445 default_cfg1 {
446 ste,pins = "GPIO203_AE23"; /* CLK */
447 ste,config = <&out_lo>;
448 };
449 default_cfg2 {
450 ste,pins = "GPIO202_AF25"; /* FBCLK */
451 ste,config = <&in_nopull>;
452 };
453 default_cfg3 {
454 ste,pins =
455 "GPIO201_AF24", /* CMD */
456 "GPIO200_AH26", /* DAT0 */
457 "GPIO199_AH23", /* DAT1 */
458 "GPIO198_AG25", /* DAT2 */
459 "GPIO197_AH24", /* DAT3 */
460 "GPIO207_AJ23", /* DAT4 */
461 "GPIO206_AG24", /* DAT5 */
462 "GPIO205_AG23", /* DAT6 */
463 "GPIO204_AF23"; /* DAT7 */
464 ste,config = <&in_pu>;
465 };
466 };
467
468 sdi4_sleep_mode: sdi4_sleep {
469 sleep_cfg1 {
470 ste,pins = "GPIO203_AE23"; /* CLK */
471 ste,config = <&out_lo_wkup_pdis>;
472 };
473 sleep_cfg2 {
474 ste,pins =
475 "GPIO202_AF25", /* FBCLK */
476 "GPIO201_AF24", /* CMD */
477 "GPIO200_AH26", /* DAT0 */
478 "GPIO199_AH23", /* DAT1 */
479 "GPIO198_AG25", /* DAT2 */
480 "GPIO197_AH24", /* DAT3 */
481 "GPIO207_AJ23", /* DAT4 */
482 "GPIO206_AG24", /* DAT5 */
483 "GPIO205_AG23", /* DAT6 */
484 "GPIO204_AF23"; /* DAT7 */
485 ste,config = <&slpm_in_wkup_pdis>;
486 };
487 };
488 };
489
490 /*
491 * Multi-rate serial ports (MSPs) - MSP3 output is internal and
492 * cannot be muxed onto any pins.
493 */
494 msp0 {
495 msp0_default_mode: msp0_default {
496 default_msp0_mux {
497 ste,function = "msp0";
498 ste,pins = "msp0txrx_a_1", "msp0tfstck_a_1";
499 };
500 default_msp0_cfg {
501 ste,pins =
502 "GPIO12_AC4", /* TXD */
503 "GPIO15_AC3", /* RXD */
504 "GPIO13_AF3", /* TFS */
505 "GPIO14_AE3"; /* TCK */
506 ste,config = <&in_nopull>;
507 };
508 };
509 };
510
511 msp1 {
512 msp1_default_mode: msp1_default {
513 default_mux {
514 ste,function = "msp1";
515 ste,pins = "msp1txrx_a_1", "msp1_a_1";
516 };
517 default_cfg1 {
518 ste,pins = "GPIO33_AF2";
519 ste,config = <&out_lo>;
520 };
521 default_cfg2 {
522 ste,pins =
523 "GPIO34_AE1",
524 "GPIO35_AE2",
525 "GPIO36_AG2";
526 ste,config = <&in_nopull>;
527 };
528
529 };
530 };
531
532 msp2 {
533 msp2_default_mode: msp2_default {
534 /* MSP2 usually used for HDMI audio */
535 default_mux {
536 ste,function = "msp2";
537 ste,pins = "msp2_a_1";
538 };
539 default_cfg1 {
540 ste,pins =
541 "GPIO193_AH27", /* TXD */
542 "GPIO194_AF27", /* TCK */
543 "GPIO195_AG28"; /* TFS */
544 ste,config = <&in_pd>;
545 };
546 default_cfg2 {
547 ste,pins = "GPIO196_AG26"; /* RXD */
548 ste,config = <&out_lo>;
549 };
550 };
551 };
552
553
554 musb {
555 musb_default_mode: musb_default {
556 default_mux {
557 ste,function = "usb";
558 ste,pins = "usb_a_1";
559 };
560 default_cfg1 {
561 ste,pins =
562 "GPIO256_AF28", /* NXT */
563 "GPIO258_AD29", /* XCLK */
564 "GPIO259_AC29", /* DIR */
565 "GPIO260_AD28", /* DAT7 */
566 "GPIO261_AD26", /* DAT6 */
567 "GPIO262_AE26", /* DAT5 */
568 "GPIO263_AG29", /* DAT4 */
569 "GPIO264_AE27", /* DAT3 */
570 "GPIO265_AD27", /* DAT2 */
571 "GPIO266_AC28", /* DAT1 */
572 "GPIO267_AC27"; /* DAT0 */
573 ste,config = <&in_nopull>;
574 };
575 default_cfg2 {
576 ste,pins = "GPIO257_AE29"; /* STP */
577 ste,config = <&out_hi>;
578 };
579 };
580
581 musb_sleep_mode: musb_sleep {
582 sleep_cfg1 {
583 ste,pins =
584 "GPIO256_AF28", /* NXT */
585 "GPIO258_AD29", /* XCLK */
586 "GPIO259_AC29"; /* DIR */
587 ste,config = <&slpm_wkup_pdis_en>;
588 };
589 sleep_cfg2 {
590 ste,pins = "GPIO257_AE29"; /* STP */
591 ste,config = <&slpm_out_hi_wkup_pdis>;
592 };
593 sleep_cfg3 {
594 ste,pins =
595 "GPIO260_AD28", /* DAT7 */
596 "GPIO261_AD26", /* DAT6 */
597 "GPIO262_AE26", /* DAT5 */
598 "GPIO263_AG29", /* DAT4 */
599 "GPIO264_AE27", /* DAT3 */
600 "GPIO265_AD27", /* DAT2 */
601 "GPIO266_AC28", /* DAT1 */
602 "GPIO267_AC27"; /* DAT0 */
603 ste,config = <&slpm_in_wkup_pdis_en>;
604 };
605 };
606 };
607
608 mcde {
609 lcd_default_mode: lcd_default {
610 default_mux {
611 /* Mux in VSI0 and all the data lines */
612 ste,function = "lcd";
613 ste,pins =
614 "lcdvsi0_a_1", /* VSI0 for LCD */
615 "lcd_d0_d7_a_1", /* Data lines */
616 "lcd_d8_d11_a_1", /* TV-out */
617 "lcdaclk_b_1", /* Clock line for TV-out */
618 "lcdvsi1_a_1"; /* VSI1 for HDMI */
619 };
620 default_cfg1 {
621 ste,pins =
622 "GPIO68_E1", /* VSI0 */
623 "GPIO69_E2"; /* VSI1 */
624 ste,config = <&in_pu>;
625 };
626 };
627 lcd_sleep_mode: lcd_sleep {
628 sleep_cfg1 {
629 ste,pins = "GPIO69_E2"; /* VSI1 */
630 ste,config = <&slpm_in_wkup_pdis>;
631 };
632 };
633 };
634
635 ske {
636 /* SKE keys on position 2 in an 8x8 matrix */
637 ske_kpa2_default_mode: ske_kpa2_default {
638 default_mux {
639 ste,function = "kp";
640 ste,pins = "kp_a_2";
641 };
642 default_cfg1 {
643 ste,pins =
644 "GPIO153_B17", /* I7 */
645 "GPIO154_C16", /* I6 */
646 "GPIO155_C19", /* I5 */
647 "GPIO156_C17", /* I4 */
648 "GPIO161_D21", /* I3 */
649 "GPIO162_D20", /* I2 */
650 "GPIO163_C20", /* I1 */
651 "GPIO164_B21"; /* I0 */
652 ste,config = <&in_pd>;
653 };
654 default_cfg2 {
655 ste,pins =
656 "GPIO157_A18", /* O7 */
657 "GPIO158_C18", /* O6 */
658 "GPIO159_B19", /* O5 */
659 "GPIO160_B20", /* O4 */
660 "GPIO165_C21", /* O3 */
661 "GPIO166_A22", /* O2 */
662 "GPIO167_B24", /* O1 */
663 "GPIO168_C22"; /* O0 */
664 ste,config = <&out_lo>;
665 };
666 };
667 ske_kpa2_sleep_mode: ske_kpa2_sleep {
668 sleep_cfg1 {
669 ste,pins =
670 "GPIO153_B17", /* I7 */
671 "GPIO154_C16", /* I6 */
672 "GPIO155_C19", /* I5 */
673 "GPIO156_C17", /* I4 */
674 "GPIO161_D21", /* I3 */
675 "GPIO162_D20", /* I2 */
676 "GPIO163_C20", /* I1 */
677 "GPIO164_B21"; /* I0 */
678 ste,config = <&slpm_in_pu_wkup_pdis_en>;
679 };
680 sleep_cfg2 {
681 ste,pins =
682 "GPIO157_A18", /* O7 */
683 "GPIO158_C18", /* O6 */
684 "GPIO159_B19", /* O5 */
685 "GPIO160_B20", /* O4 */
686 "GPIO165_C21", /* O3 */
687 "GPIO166_A22", /* O2 */
688 "GPIO167_B24", /* O1 */
689 "GPIO168_C22"; /* O0 */
690 ste,config = <&slpm_out_lo_pdis>;
691 };
692 };
693 /*
694 * SKE keys on position 1 and "other C1" combi giving
695 * six rows of six keys.
696 */
697 ske_kpaoc1_default_mode: ske_kpaoc1_default {
698 default_mux {
699 ste,function = "kp";
700 ste,pins = "kp_a_1", "kp_oc1_1";
701 };
702 default_cfg1 {
703 ste,pins =
704 "GPIO91_B6", /* KP_O0 */
705 "GPIO90_A3", /* KP_O1 */
706 "GPIO87_B3", /* KP_O2 */
707 "GPIO86_C6", /* KP_O3 */
708 "GPIO96_D8", /* KP_O6 */
709 "GPIO94_D7"; /* KP_O7 */
710 ste,config = <&out_lo>;
711 };
712 default_cfg2 {
713 ste,pins =
714 "GPIO93_B7", /* KP_I0 */
715 "GPIO92_D6", /* KP_I1 */
716 "GPIO89_E6", /* KP_I2 */
717 "GPIO88_C4", /* KP_I3 */
718 "GPIO97_D9", /* KP_I6 */
719 "GPIO95_E8"; /* KP_I7 */
720 ste,config = <&in_pu>;
721 };
722 };
723 };
724
725 wlan {
726 wlan_default_mode: wlan_default {
727 /*
728 * Activate this mode with the WLAN chip.
729 * These are plain GPIO pins used by WLAN
730 */
731 default_cfg1 {
732 ste,pins =
733 "GPIO226_AF8", /* WLAN_PMU_EN */
734 "GPIO85_D5"; /* WLAN_ENA */
735 ste,config = <&gpio_out_lo>;
736 };
737 default_cfg2 {
738 ste,pins = "GPIO4_AH6"; /* WLAN_IRQ on UART1 */
739 ste,config = <&gpio_in_pu>;
740 };
741 };
742 };
743 };
744 };
745};
diff --git a/arch/arm/boot/dts/ste-href-stuib.dtsi b/arch/arm/boot/dts/ste-href-stuib.dtsi
index 76704ec0ffcc..1c3574435ea8 100644
--- a/arch/arm/boot/dts/ste-href-stuib.dtsi
+++ b/arch/arm/boot/dts/ste-href-stuib.dtsi
@@ -12,6 +12,28 @@
12#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/interrupt-controller/irq.h>
13 13
14/ { 14/ {
15 gpio_keys {
16 compatible = "gpio-keys";
17 #address-cells = <1>;
18 #size-cells = <0>;
19 vdd-supply = <&ab8500_ldo_aux1_reg>;
20 pinctrl-names = "default";
21 pinctrl-0 = <&prox_stuib_mode>, <&hall_stuib_mode>;
22
23 button@139 {
24 /* Proximity sensor */
25 gpios = <&gpio6 25 0x4>;
26 linux,code = <11>; /* SW_FRONT_PROXIMITY */
27 label = "SFH7741 Proximity Sensor";
28 };
29 button@145 {
30 /* Hall sensor */
31 gpios = <&gpio4 17 0x4>;
32 linux,code = <0>; /* SW_LID */
33 label = "HED54XXU11 Hall Effect Sensor";
34 };
35 };
36
15 soc { 37 soc {
16 i2c@80004000 { 38 i2c@80004000 {
17 stmpe1601: stmpe1601@40 { 39 stmpe1601: stmpe1601@40 {
@@ -74,5 +96,24 @@
74 rohm,flip-y; 96 rohm,flip-y;
75 }; 97 };
76 }; 98 };
99
100 pinctrl {
101 prox {
102 prox_stuib_mode: prox_stuib {
103 stuib_cfg {
104 ste,pins = "GPIO217_AH12";
105 ste,config = <&gpio_in_pu>;
106 };
107 };
108 };
109 hall {
110 hall_stuib_mode: stuib_tvk {
111 stuib_cfg {
112 ste,pins = "GPIO145_C13";
113 ste,config = <&gpio_in_pu>;
114 };
115 };
116 };
117 };
77 }; 118 };
78}; 119};
diff --git a/arch/arm/boot/dts/ste-href-tvk1281618.dtsi b/arch/arm/boot/dts/ste-href-tvk1281618.dtsi
index 76d3ef13175f..c40565320978 100644
--- a/arch/arm/boot/dts/ste-href-tvk1281618.dtsi
+++ b/arch/arm/boot/dts/ste-href-tvk1281618.dtsi
@@ -14,27 +14,105 @@
14#include <dt-bindings/interrupt-controller/irq.h> 14#include <dt-bindings/interrupt-controller/irq.h>
15 15
16/ { 16/ {
17 gpio_keys {
18 compatible = "gpio-keys";
19 #address-cells = <1>;
20 #size-cells = <0>;
21 vdd-supply = <&ab8500_ldo_aux1_reg>;
22 pinctrl-names = "default";
23 pinctrl-0 = <&prox_tvk_mode>, <&hall_tvk_mode>;
24
25 button@139 {
26 /* Proximity sensor */
27 gpios = <&gpio6 25 0x4>;
28 linux,code = <11>; /* SW_FRONT_PROXIMITY */
29 label = "SFH7741 Proximity Sensor";
30 };
31 button@145 {
32 /* Hall sensor */
33 gpios = <&gpio4 17 0x4>;
34 linux,code = <0>; /* SW_LID */
35 label = "HED54XXU11 Hall Effect Sensor";
36 };
37 };
38
17 soc { 39 soc {
18 /* Add Synaptics touch screen, TC35892 keypad etc here */ 40 /* Add Synaptics touch screen, TC35893 keypad etc here */
19 i2c@80004000 { 41 i2c@80004000 {
20 tc3589x@44 { 42 tc35893@44 {
21 compatible = "tc3589x"; 43 compatible = "toshiba,tc35893";
22 reg = <0x44>; 44 reg = <0x44>;
23 interrupt-parent = <&gpio6>; 45 interrupt-parent = <&gpio6>;
24 interrupts = <26 IRQ_TYPE_EDGE_RISING>; 46 interrupts = <26 IRQ_TYPE_EDGE_RISING>;
47 pinctrl-names = "default";
48 pinctrl-0 = <&tc35893_tvk_mode>;
25 49
26 interrupt-controller; 50 interrupt-controller;
27 #interrupt-cells = <2>; 51 #interrupt-cells = <1>;
28 52
29 tc3589x_gpio { 53 tc3589x_gpio {
30 compatible = "tc3589x-gpio"; 54 compatible = "toshiba,tc3589x-gpio";
31 interrupts = <0 IRQ_TYPE_EDGE_RISING>; 55 interrupts = <0>;
32 56
33 interrupt-controller; 57 interrupt-controller;
34 #interrupt-cells = <2>; 58 #interrupt-cells = <2>;
35 gpio-controller; 59 gpio-controller;
36 #gpio-cells = <2>; 60 #gpio-cells = <2>;
37 }; 61 };
62 tc3589x_keypad {
63 compatible = "toshiba,tc3589x-keypad";
64 interrupts = <6>;
65 debounce-delay-ms = <4>;
66 keypad,num-columns = <8>;
67 keypad,num-rows = <8>;
68 linux,no-autorepeat;
69 linux,wakeup;
70 linux,keymap = <0x0301006b
71 0x04010066
72 0x06040072
73 0x040200d7
74 0x0303006a
75 0x0205000e
76 0x0607008b
77 0x0500001c
78 0x0403000b
79 0x03040034
80 0x05020067
81 0x0305006c
82 0x040500e7
83 0x0005009e
84 0x06020073
85 0x01030039
86 0x07060069
87 0x050500d9>;
88 };
89 };
90 };
91 pinctrl {
92 /* Pull up this GPIO pin */
93 tc35893 {
94 tc35893_tvk_mode: tc35893_tvk {
95 tvk_cfg {
96 ste,pins = "GPIO218_AH11";
97 ste,config = <&gpio_in_pu>;
98 };
99 };
100 };
101 prox {
102 prox_tvk_mode: prox_tvk {
103 tvk_cfg {
104 ste,pins = "GPIO217_AH12";
105 ste,config = <&gpio_in_pu>;
106 };
107 };
108 };
109 hall {
110 hall_tvk_mode: hall_tvk {
111 tvk_cfg {
112 ste,pins = "GPIO145_C13";
113 ste,config = <&gpio_in_pu>;
114 };
115 };
38 }; 116 };
39 }; 117 };
40 }; 118 };
diff --git a/arch/arm/boot/dts/ste-href.dtsi b/arch/arm/boot/dts/ste-href.dtsi
index aa3f02060fdd..e28242173d18 100644
--- a/arch/arm/boot/dts/ste-href.dtsi
+++ b/arch/arm/boot/dts/ste-href.dtsi
@@ -11,37 +11,57 @@
11 11
12#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/interrupt-controller/irq.h>
13#include "ste-dbx5x0.dtsi" 13#include "ste-dbx5x0.dtsi"
14#include "ste-href-family-pinctrl.dtsi"
14 15
15/ { 16/ {
16 memory { 17 memory {
17 reg = <0x00000000 0x20000000>; 18 reg = <0x00000000 0x20000000>;
18 }; 19 };
19 20
20 gpio_keys { 21 soc {
21 compatible = "gpio-keys"; 22 usb_per5@a03e0000 {
22 #address-cells = <1>; 23 pinctrl-names = "default", "sleep";
23 #size-cells = <0>; 24 pinctrl-0 = <&musb_default_mode>;
24 25 pinctrl-1 = <&musb_sleep_mode>;
25 button@1 {
26 linux,code = <11>;
27 label = "SFH7741 Proximity Sensor";
28 }; 26 };
29 };
30 27
31 soc {
32 uart@80120000 { 28 uart@80120000 {
29 pinctrl-names = "default", "sleep";
30 pinctrl-0 = <&uart0_default_mode>;
31 pinctrl-1 = <&uart0_sleep_mode>;
33 status = "okay"; 32 status = "okay";
34 }; 33 };
35 34
36 uart@80121000 { 35 uart@80121000 {
36 pinctrl-names = "default", "sleep";
37 pinctrl-0 = <&uart1_default_mode>;
38 pinctrl-1 = <&uart1_sleep_mode>;
37 status = "okay"; 39 status = "okay";
38 }; 40 };
39 41
40 uart@80007000 { 42 uart@80007000 {
43 pinctrl-names = "default", "sleep";
44 pinctrl-0 = <&uart2_default_mode>;
45 pinctrl-1 = <&uart2_sleep_mode>;
41 status = "okay"; 46 status = "okay";
42 }; 47 };
43 48
49 i2c@80004000 {
50 pinctrl-names = "default","sleep";
51 pinctrl-0 = <&i2c0_default_mode>;
52 pinctrl-1 = <&i2c0_sleep_mode>;
53 };
54
55 i2c@80122000 {
56 pinctrl-names = "default","sleep";
57 pinctrl-0 = <&i2c1_default_mode>;
58 pinctrl-1 = <&i2c1_sleep_mode>;
59 };
60
44 i2c@80128000 { 61 i2c@80128000 {
62 pinctrl-names = "default","sleep";
63 pinctrl-0 = <&i2c2_default_mode>;
64 pinctrl-1 = <&i2c2_sleep_mode>;
45 lp5521@33 { 65 lp5521@33 {
46 compatible = "national,lp5521"; 66 compatible = "national,lp5521";
47 reg = <0x33>; 67 reg = <0x33>;
@@ -85,6 +105,12 @@
85 }; 105 };
86 }; 106 };
87 107
108 i2c@80110000 {
109 pinctrl-names = "default","sleep";
110 pinctrl-0 = <&i2c3_default_mode>;
111 pinctrl-1 = <&i2c3_sleep_mode>;
112 };
113
88 // External Micro SD slot 114 // External Micro SD slot
89 sdi0_per1@80126000 { 115 sdi0_per1@80126000 {
90 arm,primecell-periphid = <0x10480180>; 116 arm,primecell-periphid = <0x10480180>;
@@ -94,6 +120,9 @@
94 mmc-cap-mmc-highspeed; 120 mmc-cap-mmc-highspeed;
95 vmmc-supply = <&ab8500_ldo_aux3_reg>; 121 vmmc-supply = <&ab8500_ldo_aux3_reg>;
96 vqmmc-supply = <&vmmci>; 122 vqmmc-supply = <&vmmci>;
123 pinctrl-names = "default", "sleep";
124 pinctrl-0 = <&sdi0_default_mode>;
125 pinctrl-1 = <&sdi0_sleep_mode>;
97 126
98 cd-gpios = <&tc3589x_gpio 3 0x4>; 127 cd-gpios = <&tc3589x_gpio 3 0x4>;
99 128
@@ -105,6 +134,9 @@
105 arm,primecell-periphid = <0x10480180>; 134 arm,primecell-periphid = <0x10480180>;
106 max-frequency = <100000000>; 135 max-frequency = <100000000>;
107 bus-width = <4>; 136 bus-width = <4>;
137 pinctrl-names = "default", "sleep";
138 pinctrl-0 = <&sdi1_default_mode>;
139 pinctrl-1 = <&sdi1_sleep_mode>;
108 140
109 status = "okay"; 141 status = "okay";
110 }; 142 };
@@ -115,6 +147,9 @@
115 max-frequency = <100000000>; 147 max-frequency = <100000000>;
116 bus-width = <8>; 148 bus-width = <8>;
117 mmc-cap-mmc-highspeed; 149 mmc-cap-mmc-highspeed;
150 pinctrl-names = "default", "sleep";
151 pinctrl-0 = <&sdi2_default_mode>;
152 pinctrl-1 = <&sdi2_sleep_mode>;
118 153
119 status = "okay"; 154 status = "okay";
120 }; 155 };
@@ -126,6 +161,9 @@
126 bus-width = <8>; 161 bus-width = <8>;
127 mmc-cap-mmc-highspeed; 162 mmc-cap-mmc-highspeed;
128 vmmc-supply = <&ab8500_ldo_aux2_reg>; 163 vmmc-supply = <&ab8500_ldo_aux2_reg>;
164 pinctrl-names = "default", "sleep";
165 pinctrl-0 = <&sdi4_default_mode>;
166 pinctrl-1 = <&sdi4_sleep_mode>;
129 167
130 status = "okay"; 168 status = "okay";
131 }; 169 };
@@ -137,7 +175,21 @@
137 stericsson,audio-codec = <&codec>; 175 stericsson,audio-codec = <&codec>;
138 }; 176 };
139 177
178 msp0: msp@80123000 {
179 pinctrl-names = "default";
180 pinctrl-0 = <&msp0_default_mode>;
181 status = "okay";
182 };
183
140 msp1: msp@80124000 { 184 msp1: msp@80124000 {
185 pinctrl-names = "default";
186 pinctrl-0 = <&msp1_default_mode>;
187 status = "okay";
188 };
189
190 msp2: msp@80117000 {
191 pinctrl-names = "default";
192 pinctrl-0 = <&msp2_default_mode>;
141 status = "okay"; 193 status = "okay";
142 }; 194 };
143 195
@@ -198,5 +250,11 @@
198 }; 250 };
199 }; 251 };
200 }; 252 };
253
254 mcde@a0350000 {
255 pinctrl-names = "default", "sleep";
256 pinctrl-0 = <&lcd_default_mode>;
257 pinctrl-1 = <&lcd_sleep_mode>;
258 };
201 }; 259 };
202}; 260};
diff --git a/arch/arm/boot/dts/ste-hrefprev60.dtsi b/arch/arm/boot/dts/ste-hrefprev60.dtsi
index b2cd7bc2752f..b0f5def8e2a8 100644
--- a/arch/arm/boot/dts/ste-hrefprev60.dtsi
+++ b/arch/arm/boot/dts/ste-hrefprev60.dtsi
@@ -28,18 +28,20 @@
28 reg = <0x33>; 28 reg = <0x33>;
29 }; 29 };
30 30
31 tc3589x@42 { 31 tc35892@42 {
32 compatible = "tc3589x"; 32 compatible = "toshiba,tc35892";
33 reg = <0x42>; 33 reg = <0x42>;
34 interrupt-parent = <&gpio6>; 34 interrupt-parent = <&gpio6>;
35 interrupts = <25 IRQ_TYPE_EDGE_RISING>; 35 interrupts = <25 IRQ_TYPE_EDGE_RISING>;
36 pinctrl-names = "default";
37 pinctrl-0 = <&tc35892_hrefprev60_mode>;
36 38
37 interrupt-controller; 39 interrupt-controller;
38 #interrupt-cells = <2>; 40 #interrupt-cells = <1>;
39 41
40 tc3589x_gpio: tc3589x_gpio { 42 tc3589x_gpio: tc3589x_gpio {
41 compatible = "tc3589x-gpio"; 43 compatible = "tc3589x-gpio";
42 interrupts = <0 IRQ_TYPE_EDGE_RISING>; 44 interrupts = <0>;
43 45
44 interrupt-controller; 46 interrupt-controller;
45 #interrupt-cells = <2>; 47 #interrupt-cells = <2>;
@@ -49,11 +51,74 @@
49 }; 51 };
50 }; 52 };
51 53
54 ssp@80002000 {
55 /*
56 * On the first generation boards, this SSP/SPI port was connected
57 * to the AB8500.
58 */
59 pinctrl-names = "default";
60 pinctrl-0 = <&ssp0_hrefprev60_mode>;
61 };
62
52 vmmci: regulator-gpio { 63 vmmci: regulator-gpio {
53 gpios = <&tc3589x_gpio 18 0x4>; 64 gpios = <&tc3589x_gpio 18 0x4>;
54 enable-gpio = <&tc3589x_gpio 17 0x4>; 65 enable-gpio = <&tc3589x_gpio 17 0x4>;
55 66
56 status = "okay"; 67 status = "okay";
57 }; 68 };
69
70 pinctrl {
71 /* Set this up using hogs */
72 pinctrl-names = "default";
73 pinctrl-0 = <&ipgpio_hrefprev60_mode>;
74
75 ssp0 {
76 ssp0_hrefprev60_mode: ssp0_hrefprev60_default {
77 hrefprev60_mux {
78 ste,function = "ssp0";
79 ste,pins = "ssp0_a_1";
80 };
81 hrefprev60_cfg1 {
82 ste,pins = "GPIO145_C13"; /* RXD */
83 ste,config = <&in_pd>;
84 };
85
86 };
87 };
88 sdi0 {
89 /* This additional pin needed on early MOP500 and HREFs previous to v60 */
90 sdi0_default_mode: sdi0_default {
91 hrefprev60_mux {
92 ste,function = "mc0";
93 ste,pins = "mc0dat31dir_a_1";
94 };
95 hrefprev60_cfg1 {
96 ste,pins = "GPIO21_AB3"; /* DAT31DIR */
97 ste,config = <&out_hi>;
98 };
99
100 };
101 };
102 tc35892 {
103 tc35892_hrefprev60_mode: tc35892_hrefprev60 {
104 hrefprev60_cfg {
105 ste,pins = "GPIO217_AH12";
106 ste,config = <&gpio_in_pu>;
107 };
108 };
109 };
110 ipgpio {
111 ipgpio_hrefprev60_mode: ipgpio_hrefprev60 {
112 hrefprev60_mux {
113 ste,function = "ipgpio";
114 ste,pins = "ipgpio0_c_1", "ipgpio1_c_1";
115 };
116 hrefprev60_cfg1 {
117 ste,pins = "GPIO6_AF6", "GPIO7_AG5";
118 ste,config = <&in_pu>;
119 };
120 };
121 };
122 };
58 }; 123 };
59}; 124};
diff --git a/arch/arm/boot/dts/ste-hrefv60plus.dtsi b/arch/arm/boot/dts/ste-hrefv60plus.dtsi
index aed511b47a9e..941bf9ad6f01 100644
--- a/arch/arm/boot/dts/ste-hrefv60plus.dtsi
+++ b/arch/arm/boot/dts/ste-hrefv60plus.dtsi
@@ -16,12 +16,6 @@
16 model = "ST-Ericsson HREF (v60+) platform with Device Tree"; 16 model = "ST-Ericsson HREF (v60+) platform with Device Tree";
17 compatible = "st-ericsson,hrefv60+", "st-ericsson,u8500"; 17 compatible = "st-ericsson,hrefv60+", "st-ericsson,u8500";
18 18
19 gpio_keys {
20 button@1 {
21 gpios = <&gpio5 25 0x4>;
22 };
23 };
24
25 soc { 19 soc {
26 // External Micro SD slot 20 // External Micro SD slot
27 sdi0_per1@80126000 { 21 sdi0_per1@80126000 {
@@ -66,5 +60,216 @@
66 60
67 status = "okay"; 61 status = "okay";
68 }; 62 };
63
64 pinctrl {
65 /*
66 * Set this up using hogs, as time goes by and as seems fit, these
67 * can be moved over to being controlled by respective device.
68 */
69 pinctrl-names = "default";
70 pinctrl-0 = <&ipgpio_hrefv60_mode>,
71 <&accel_hrefv60_mode>,
72 <&magneto_hrefv60_mode>,
73 <&etm_hrefv60_mode>,
74 <&nahj_hrefv60_mode>,
75 <&nfc_hrefv60_mode>,
76 <&force_hrefv60_mode>,
77 <&dipro_hrefv60_mode>,
78 <&vaudio_hf_hrefv60_mode>,
79 <&gbf_hrefv60_mode>,
80 <&hdtv_hrefv60_mode>,
81 <&touch_hrefv60_mode>;
82
83 sdi0 {
84 /* SD card detect GPIO pin, extend default state */
85 sdi0_default_mode: sdi0_default {
86 default_hrefv60_cfg1 {
87 ste,pins = "GPIO95_E8";
88 ste,config = <&gpio_in_pu>;
89 };
90 };
91 };
92 ipgpio {
93 /*
94 * XENON Flashgun on image processor GPIO (controlled from image
95 * processor firmware), mux in these image processor GPIO lines 0
96 * (XENON_FLASH_ID), 1 (XENON_READY) and there is an assistant
97 * LED on IP GPIO 4 (XENON_EN2) on altfunction C, that need bias
98 * from GPIO21 so pull up 0, 1 and drive 4 and GPIO21 low as output.
99 */
100 ipgpio_hrefv60_mode: ipgpio_hrefv60 {
101 hrefv60_mux {
102 ste,function = "ipgpio";
103 ste,pins = "ipgpio0_c_1", "ipgpio1_c_1", "ipgpio4_c_1";
104 };
105 hrefv60_cfg1 {
106 ste,pins = "GPIO6_AF6", "GPIO7_AG5";
107 ste,config = <&in_pu>;
108 };
109 hrefv60_cfg2 {
110 ste,pins = "GPIO21_AB3";
111 ste,config = <&gpio_out_lo>;
112 };
113 hrefv60_cfg3 {
114 ste,pins = "GPIO64_F3";
115 ste,config = <&out_lo>;
116 };
117 };
118 };
119 accelerometer {
120 accel_hrefv60_mode: accel_hrefv60 {
121 /* Accelerometer interrupt lines 1 & 2 */
122 hrefv60_cfg1 {
123 ste,pins = "GPIO82_C1", "GPIO83_D3";
124 ste,config = <&gpio_in_pu>;
125 };
126 };
127 };
128 magnetometer {
129 magneto_hrefv60_mode: magneto_hrefv60 {
130 /* Magnetometer uses GPIO 31 and 32, pull these up/down respectively */
131 hrefv60_cfg1 {
132 ste,pins = "GPIO31_V3";
133 ste,config = <&gpio_in_pu>;
134 };
135 hrefv60_cfg2 {
136 ste,pins = "GPIO32_V2";
137 ste,config = <&gpio_in_pd>;
138 };
139 };
140 };
141 etm {
142 /*
143 * Drive D19-D23 for the ETM PTM trace interface low,
144 * (presumably pins are unconnected therefore grounded here,
145 * the "other alt C1" setting enables these pins)
146 */
147 etm_hrefv60_mode: etm_hrefv60 {
148 hrefv60_cfg1 {
149 ste,pins =
150 "GPIO70_G5",
151 "GPIO71_G4",
152 "GPIO72_H4",
153 "GPIO73_H3",
154 "GPIO74_J3";
155 ste,config = <&gpio_out_lo>;
156 };
157 };
158 };
159 nahj {
160 nahj_hrefv60_mode: nahj_hrefv60 {
161 /* NAHJ CTRL on GPIO76 to low, CTRL_INV on GPIO216 to high */
162 hrefv60_cfg1 {
163 ste,pins = "GPIO76_J2";
164 ste,config = <&gpio_out_lo>;
165 };
166 hrefv60_cfg2 {
167 ste,pins = "GPIO216_AG12";
168 ste,config = <&gpio_out_hi>;
169 };
170 };
171 };
172 nfc {
173 nfc_hrefv60_mode: nfc_hrefv60 {
174 /* NFC ENA and RESET to low, pulldown IRQ line */
175 hrefv60_cfg1 {
176 ste,pins =
177 "GPIO77_H1", /* NFC_ENA */
178 "GPIO142_C11"; /* NFC_RESET */
179 ste,config = <&gpio_out_lo>;
180 };
181 hrefv60_cfg2 {
182 ste,pins = "GPIO144_B13"; /* NFC_IRQ */
183 ste,config = <&gpio_in_pd>;
184 };
185 };
186 };
187 force {
188 force_hrefv60_mode: force_hrefv60 {
189 hrefv60_cfg1 {
190 ste,pins = "GPIO91_B6"; /* FORCE_SENSING_INT */
191 ste,config = <&gpio_in_pu>;
192 };
193 hrefv60_cfg2 {
194 ste,pins =
195 "GPIO92_D6", /* FORCE_SENSING_RST */
196 "GPIO97_D9"; /* FORCE_SENSING_WU */
197 ste,config = <&gpio_out_lo>;
198 };
199 };
200 };
201 dipro {
202 dipro_hrefv60_mode: dipro_hrefv60 {
203 hrefv60_cfg1 {
204 ste,pins = "GPIO139_C9"; /* DIPRO_INT */
205 ste,config = <&gpio_in_pu>;
206 };
207 };
208 };
209 vaudio_hf {
210 vaudio_hf_hrefv60_mode: vaudio_hf_hrefv60 {
211 /* Audio Amplifier HF enable GPIO */
212 hrefv60_cfg1 {
213 ste,pins = "GPIO149_B14"; /* VAUDIO_HF_EN, enable MAX8968 */
214 ste,config = <&gpio_out_hi>;
215 };
216 };
217 };
218 gbf {
219 gbf_hrefv60_mode: gbf_hrefv60 {
220 /*
221 * GBF (GPS, Bluetooth, FM-radio) interface,
222 * pull low to reset state
223 */
224 hrefv60_cfg1 {
225 ste,pins = "GPIO171_D23"; /* GBF_ENA_RESET */
226 ste,config = <&gpio_out_lo>;
227 };
228 };
229 };
230 hdtv {
231 hdtv_hrefv60_mode: hdtv_hrefv60 {
232 /* MSP : HDTV INTERFACE GPIO line */
233 hrefv60_cfg1 {
234 ste,pins = "GPIO192_AJ27";
235 ste,config = <&gpio_in_pd>;
236 };
237 };
238 };
239 touch {
240 touch_hrefv60_mode: touch_hrefv60 {
241 /*
242 * Touch screen uses GPIO 143 for RST1, GPIO 146 for RST2 and
243 * GPIO 67 for interrupts. Pull-up the IRQ line and drive both
244 * reset signals low.
245 */
246 hrefv60_cfg1 {
247 ste,pins = "GPIO143_D12", "GPIO146_D13";
248 ste,config = <&gpio_out_lo>;
249 };
250 hrefv60_cfg2 {
251 ste,pins = "GPIO67_G2";
252 ste,config = <&gpio_in_pu>;
253 };
254 };
255 };
256 mcde {
257 lcd_hrefv60_mode: lcd_hrefv60 {
258 /*
259 * Display Interface 1 uses GPIO 65 for RST (reset).
260 * Display Interface 2 uses GPIO 66 for RST (reset).
261 * Drive DISP1 reset high (not reset), driver DISP2 reset low (reset)
262 */
263 hrefv60_cfg1 {
264 ste,pins ="GPIO65_F1";
265 ste,config = <&gpio_out_hi>;
266 };
267 hrefv60_cfg2 {
268 ste,pins ="GPIO66_G3";
269 ste,config = <&gpio_out_lo>;
270 };
271 };
272 };
273 };
69 }; 274 };
70}; 275};
diff --git a/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi b/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi
index efddee9403c4..e6f22b266420 100644
--- a/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi
+++ b/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi
@@ -31,17 +31,57 @@
31 ste,output = <OUTPUT_LOW>; 31 ste,output = <OUTPUT_LOW>;
32 }; 32 };
33 33
34 gpio_in_pu: gpio_input_pull_up {
35 ste,gpio = <GPIOMODE_ENABLED>;
36 ste,input = <INPUT_PULLUP>;
37 };
38
39 gpio_in_pd: gpio_input_pull_down {
40 ste,gpio = <GPIOMODE_ENABLED>;
41 ste,input = <INPUT_PULLDOWN>;
42 };
43
34 gpio_out_lo: gpio_output_low { 44 gpio_out_lo: gpio_output_low {
35 ste,gpio = <GPIOMODE_ENABLED>; 45 ste,gpio = <GPIOMODE_ENABLED>;
36 ste,output = <OUTPUT_LOW>; 46 ste,output = <OUTPUT_LOW>;
37 }; 47 };
38 48
49 gpio_out_hi: gpio_output_high {
50 ste,gpio = <GPIOMODE_ENABLED>;
51 ste,output = <OUTPUT_HIGH>;
52 };
53
54 slpm_pdis: slpm_pdis {
55 ste,sleep = <SLPM_ENABLED>;
56 ste,sleep-wakeup = <SLPM_WAKEUP_DISABLE>;
57 ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>;
58 };
59
60 slpm_wkup_pdis: slpm_wkup_pdis {
61 ste,sleep = <SLPM_ENABLED>;
62 ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>;
63 ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>;
64 };
65
66 slpm_wkup_pdis_en: slpm_wkup_pdis_en {
67 ste,sleep = <SLPM_ENABLED>;
68 ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>;
69 ste,sleep-pull-disable = <SLPM_PDIS_ENABLED>;
70 };
71
39 slpm_in_pu: slpm_in_pu { 72 slpm_in_pu: slpm_in_pu {
40 ste,sleep = <SLPM_ENABLED>; 73 ste,sleep = <SLPM_ENABLED>;
41 ste,sleep-input = <SLPM_INPUT_PULLUP>; 74 ste,sleep-input = <SLPM_INPUT_PULLUP>;
42 ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>; 75 ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>;
43 }; 76 };
44 77
78 slpm_in_pdis: slpm_in_pdis {
79 ste,sleep = <SLPM_ENABLED>;
80 ste,sleep-input = <SLPM_DIR_INPUT>;
81 ste,sleep-wakeup = <SLPM_WAKEUP_DISABLE>;
82 ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>;
83 };
84
45 slpm_in_wkup_pdis: slpm_in_wkup_pdis { 85 slpm_in_wkup_pdis: slpm_in_wkup_pdis {
46 ste,sleep = <SLPM_ENABLED>; 86 ste,sleep = <SLPM_ENABLED>;
47 ste,sleep-input = <SLPM_DIR_INPUT>; 87 ste,sleep-input = <SLPM_DIR_INPUT>;
@@ -49,6 +89,20 @@
49 ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>; 89 ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>;
50 }; 90 };
51 91
92 slpm_in_wkup_pdis_en: slpm_in_wkup_pdis_en {
93 ste,sleep = <SLPM_ENABLED>;
94 ste,sleep-input = <SLPM_DIR_INPUT>;
95 ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>;
96 ste,sleep-pull-disable = <SLPM_PDIS_ENABLED>;
97 };
98
99 slpm_in_pu_wkup_pdis_en: slpm_in_wkup_pdis_en {
100 ste,sleep = <SLPM_ENABLED>;
101 ste,sleep-input = <SLPM_INPUT_PULLUP>;
102 ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>;
103 ste,sleep-pull-disable = <SLPM_PDIS_ENABLED>;
104 };
105
52 slpm_out_lo: slpm_out_lo { 106 slpm_out_lo: slpm_out_lo {
53 ste,sleep = <SLPM_ENABLED>; 107 ste,sleep = <SLPM_ENABLED>;
54 ste,sleep-output = <SLPM_OUTPUT_LOW>; 108 ste,sleep-output = <SLPM_OUTPUT_LOW>;
@@ -68,6 +122,20 @@
68 ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>; 122 ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>;
69 }; 123 };
70 124
125 slpm_out_lo_pdis: slpm_out_lo_pdis {
126 ste,sleep = <SLPM_ENABLED>;
127 ste,sleep-output = <SLPM_OUTPUT_LOW>;
128 ste,sleep-wakeup = <SLPM_WAKEUP_DISABLE>;
129 ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>;
130 };
131
132 slpm_out_lo_wkup_pdis: slpm_out_lo_wkup_pdis {
133 ste,sleep = <SLPM_ENABLED>;
134 ste,sleep-output = <SLPM_OUTPUT_LOW>;
135 ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>;
136 ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>;
137 };
138
71 slpm_out_wkup_pdis: slpm_out_wkup_pdis { 139 slpm_out_wkup_pdis: slpm_out_wkup_pdis {
72 ste,sleep = <SLPM_ENABLED>; 140 ste,sleep = <SLPM_ENABLED>;
73 ste,sleep-output = <SLPM_DIR_OUTPUT>; 141 ste,sleep-output = <SLPM_DIR_OUTPUT>;
@@ -81,6 +149,18 @@
81 ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>; 149 ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>;
82 }; 150 };
83 151
152 in_wkup_pdis_en: in_wkup_pdis_en {
153 ste,sleep-input = <SLPM_DIR_INPUT>;
154 ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>;
155 ste,sleep-pull-disable = <SLPM_PDIS_ENABLED>;
156 };
157
158 out_lo_wkup_pdis: out_lo_wkup_pdis {
159 ste,sleep-output = <SLPM_OUTPUT_LOW>;
160 ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>;
161 ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>;
162 };
163
84 out_hi_wkup_pdis: out_hi_wkup_pdis { 164 out_hi_wkup_pdis: out_hi_wkup_pdis {
85 ste,sleep-output = <SLPM_OUTPUT_HIGH>; 165 ste,sleep-output = <SLPM_OUTPUT_HIGH>;
86 ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>; 166 ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>;
diff --git a/arch/arm/boot/dts/ste-nomadik-s8815.dts b/arch/arm/boot/dts/ste-nomadik-s8815.dts
index 16c3888b7b15..f557feb997f4 100644
--- a/arch/arm/boot/dts/ste-nomadik-s8815.dts
+++ b/arch/arm/boot/dts/ste-nomadik-s8815.dts
@@ -67,10 +67,6 @@
67 67
68 /* Custom board node with GPIO pins to active etc */ 68 /* Custom board node with GPIO pins to active etc */
69 usb-s8815 { 69 usb-s8815 {
70 /* The S8815 is using this very GPIO pin for the SMSC91x IRQs */
71 ethernet-gpio {
72 gpios = <&gpio3 8 0x1>;
73 };
74 /* This will bias the MMC/SD card detect line */ 70 /* This will bias the MMC/SD card detect line */
75 mmcsd-gpio { 71 mmcsd-gpio {
76 gpios = <&gpio3 16 0x1>; 72 gpios = <&gpio3 16 0x1>;
diff --git a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
index 79425e3836ce..5acc0449676a 100644
--- a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
+++ b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
@@ -769,14 +769,14 @@
769 #size-cells = <1>; 769 #size-cells = <1>;
770 ranges; 770 ranges;
771 771
772 vica: intc@0x10140000 { 772 vica: intc@10140000 {
773 compatible = "arm,versatile-vic"; 773 compatible = "arm,versatile-vic";
774 interrupt-controller; 774 interrupt-controller;
775 #interrupt-cells = <1>; 775 #interrupt-cells = <1>;
776 reg = <0x10140000 0x20>; 776 reg = <0x10140000 0x20>;
777 }; 777 };
778 778
779 vicb: intc@0x10140020 { 779 vicb: intc@10140020 {
780 compatible = "arm,versatile-vic"; 780 compatible = "arm,versatile-vic";
781 interrupt-controller; 781 interrupt-controller;
782 #interrupt-cells = <1>; 782 #interrupt-cells = <1>;
diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/ste-snowball.dts
index f0b39f835914..9070c3701c89 100644
--- a/arch/arm/boot/dts/ste-snowball.dts
+++ b/arch/arm/boot/dts/ste-snowball.dts
@@ -11,6 +11,7 @@
11 11
12/dts-v1/; 12/dts-v1/;
13#include "ste-dbx5x0.dtsi" 13#include "ste-dbx5x0.dtsi"
14#include "ste-href-family-pinctrl.dtsi"
14 15
15/ { 16/ {
16 model = "Calao Systems Snowball platform with device tree"; 17 model = "Calao Systems Snowball platform with device tree";
@@ -75,6 +76,8 @@
75 76
76 leds { 77 leds {
77 compatible = "gpio-leds"; 78 compatible = "gpio-leds";
79 pinctrl-names = "default";
80 pinctrl-0 = <&gpioled_snowball_mode>;
78 used-led { 81 used-led {
79 label = "user_led"; 82 label = "user_led";
80 gpios = <&gpio4 14 0x4>; 83 gpios = <&gpio4 14 0x4>;
@@ -84,6 +87,11 @@
84 }; 87 };
85 88
86 soc { 89 soc {
90 usb_per5@a03e0000 {
91 pinctrl-names = "default", "sleep";
92 pinctrl-0 = <&musb_default_mode>;
93 pinctrl-1 = <&musb_sleep_mode>;
94 };
87 95
88 sound { 96 sound {
89 compatible = "stericsson,snd-soc-mop500"; 97 compatible = "stericsson,snd-soc-mop500";
@@ -92,7 +100,21 @@
92 stericsson,audio-codec = <&codec>; 100 stericsson,audio-codec = <&codec>;
93 }; 101 };
94 102
103 msp0: msp@80123000 {
104 pinctrl-names = "default";
105 pinctrl-0 = <&msp0_default_mode>;
106 status = "okay";
107 };
108
95 msp1: msp@80124000 { 109 msp1: msp@80124000 {
110 pinctrl-names = "default";
111 pinctrl-0 = <&msp1_default_mode>;
112 status = "okay";
113 };
114
115 msp2: msp@80117000 {
116 pinctrl-names = "default";
117 pinctrl-0 = <&msp2_default_mode>;
96 status = "okay"; 118 status = "okay";
97 }; 119 };
98 120
@@ -110,6 +132,8 @@
110 interrupt-parent = <&gpio4>; 132 interrupt-parent = <&gpio4>;
111 vdd33a-supply = <&en_3v3_reg>; 133 vdd33a-supply = <&en_3v3_reg>;
112 vddvario-supply = <&db8500_vape_reg>; 134 vddvario-supply = <&db8500_vape_reg>;
135 pinctrl-names = "default";
136 pinctrl-0 = <&eth_snowball_mode>;
113 137
114 reg-shift = <1>; 138 reg-shift = <1>;
115 reg-io-width = <2>; 139 reg-io-width = <2>;
@@ -136,6 +160,9 @@
136 mmc-cap-mmc-highspeed; 160 mmc-cap-mmc-highspeed;
137 vmmc-supply = <&ab8500_ldo_aux3_reg>; 161 vmmc-supply = <&ab8500_ldo_aux3_reg>;
138 vqmmc-supply = <&vmmci>; 162 vqmmc-supply = <&vmmci>;
163 pinctrl-names = "default", "sleep";
164 pinctrl-0 = <&sdi0_default_mode>;
165 pinctrl-1 = <&sdi0_sleep_mode>;
139 166
140 cd-gpios = <&gpio6 26 0x4>; // 218 167 cd-gpios = <&gpio6 26 0x4>; // 218
141 cd-inverted; 168 cd-inverted;
@@ -143,6 +170,27 @@
143 status = "okay"; 170 status = "okay";
144 }; 171 };
145 172
173 // WLAN SDIO channel
174 sdi1_per2@80118000 {
175 arm,primecell-periphid = <0x10480180>;
176 max-frequency = <100000000>;
177 bus-width = <4>;
178 pinctrl-names = "default", "sleep";
179 pinctrl-0 = <&sdi1_default_mode>;
180 pinctrl-1 = <&sdi1_sleep_mode>;
181
182 status = "okay";
183 };
184
185 // Unused PoP eMMC - register and put it to sleep by default */
186 sdi2_per3@80005000 {
187 arm,primecell-periphid = <0x10480180>;
188 pinctrl-names = "default";
189 pinctrl-0 = <&sdi2_sleep_mode>;
190
191 status = "okay";
192 };
193
146 // On-board eMMC 194 // On-board eMMC
147 sdi4_per2@80114000 { 195 sdi4_per2@80114000 {
148 arm,primecell-periphid = <0x10480180>; 196 arm,primecell-periphid = <0x10480180>;
@@ -150,22 +198,63 @@
150 bus-width = <8>; 198 bus-width = <8>;
151 mmc-cap-mmc-highspeed; 199 mmc-cap-mmc-highspeed;
152 vmmc-supply = <&ab8500_ldo_aux2_reg>; 200 vmmc-supply = <&ab8500_ldo_aux2_reg>;
201 pinctrl-names = "default", "sleep";
202 pinctrl-0 = <&sdi4_default_mode>;
203 pinctrl-1 = <&sdi4_sleep_mode>;
153 204
154 status = "okay"; 205 status = "okay";
155 }; 206 };
156 207
157 uart@80120000 { 208 uart@80120000 {
209 pinctrl-names = "default", "sleep";
210 pinctrl-0 = <&uart0_default_mode>;
211 pinctrl-1 = <&uart0_sleep_mode>;
158 status = "okay"; 212 status = "okay";
159 }; 213 };
160 214
161 uart@80121000 { 215 uart@80121000 {
216 pinctrl-names = "default", "sleep";
217 pinctrl-0 = <&uart1_default_mode>;
218 pinctrl-1 = <&uart1_sleep_mode>;
162 status = "okay"; 219 status = "okay";
163 }; 220 };
164 221
165 uart@80007000 { 222 uart@80007000 {
223 pinctrl-names = "default", "sleep";
224 pinctrl-0 = <&uart2_default_mode>;
225 pinctrl-1 = <&uart2_sleep_mode>;
166 status = "okay"; 226 status = "okay";
167 }; 227 };
168 228
229 i2c@80004000 {
230 pinctrl-names = "default","sleep";
231 pinctrl-0 = <&i2c0_default_mode>;
232 pinctrl-1 = <&i2c0_sleep_mode>;
233 };
234
235 i2c@80122000 {
236 pinctrl-names = "default","sleep";
237 pinctrl-0 = <&i2c1_default_mode>;
238 pinctrl-1 = <&i2c1_sleep_mode>;
239 };
240
241 i2c@80128000 {
242 pinctrl-names = "default","sleep";
243 pinctrl-0 = <&i2c2_default_mode>;
244 pinctrl-1 = <&i2c2_sleep_mode>;
245 };
246
247 i2c@80110000 {
248 pinctrl-names = "default","sleep";
249 pinctrl-0 = <&i2c3_default_mode>;
250 pinctrl-1 = <&i2c3_sleep_mode>;
251 };
252
253 ssp@80002000 {
254 pinctrl-names = "default";
255 pinctrl-0 = <&ssp0_snowball_mode>;
256 };
257
169 cpufreq-cooling { 258 cpufreq-cooling {
170 status = "okay"; 259 status = "okay";
171 }; 260 };
@@ -266,5 +355,141 @@
266 }; 355 };
267 }; 356 };
268 }; 357 };
358
359 pinctrl {
360 /*
361 * Set this up using hogs, as time goes by and as seems fit, these
362 * can be moved over to being controlled by respective device.
363 */
364 pinctrl-names = "default";
365 pinctrl-0 = <&accel_snowball_mode>,
366 <&magneto_snowball_mode>,
367 <&gbf_snowball_mode>,
368 <&wlan_snowball_mode>;
369
370 ethernet {
371 /*
372 * Mux in "SM" which is used for the
373 * SMSC911x Ethernet adapter
374 */
375 eth_snowball_mode: eth_snowball {
376 snowball_mux {
377 ste,function = "sm";
378 ste,pins = "sm_b_1";
379 };
380 /* LAN IRQ pin */
381 snowball_cfg1 {
382 ste,pins = "GPIO140_B11";
383 ste,config = <&in_nopull>;
384 };
385 /* LAN reset pin */
386 snowball_cfg2 {
387 ste,pins = "GPIO141_C12";
388 ste,config = <&gpio_out_hi>;
389 };
390
391 };
392 };
393 sdi0 {
394 sdi0_default_mode: sdi0_default {
395 snowball_mux {
396 ste,function = "mc0";
397 ste,pins = "mc0dat31dir_a_1";
398 };
399 snowball_cfg1 {
400 ste,pins = "GPIO21_AB3"; /* DAT31DIR */
401 ste,config = <&out_hi>;
402 };
403
404 };
405 };
406 ssp0 {
407 ssp0_snowball_mode: ssp0_snowball_default {
408 snowball_mux {
409 ste,function = "ssp0";
410 ste,pins = "ssp0_a_1";
411 };
412 snowball_cfg1 {
413 ste,pins = "GPIO144_B13"; /* FRM */
414 ste,config = <&gpio_out_hi>;
415 };
416 snowball_cfg2 {
417 ste,pins = "GPIO145_C13"; /* RXD */
418 ste,config = <&in_pd>;
419 };
420 snowball_cfg3 {
421 ste,pins =
422 "GPIO146_D13", /* TXD */
423 "GPIO143_D12"; /* CLK */
424 ste,config = <&out_lo>;
425 };
426
427 };
428 };
429 gpio_led {
430 gpioled_snowball_mode: gpioled_default {
431 snowball_cfg1 {
432 ste,pins = "GPIO142_C11";
433 ste,config = <&gpio_out_hi>;
434 };
435
436 };
437 };
438 accelerometer {
439 accel_snowball_mode: accel_snowball {
440 /* Accelerometer lines */
441 snowball_cfg1 {
442 ste,pins =
443 "GPIO163_C20", /* ACCEL_IRQ1 */
444 "GPIO164_B21"; /* ACCEL_IRQ2 */
445 ste,config = <&gpio_in_pu>;
446 };
447 };
448 };
449 magnetometer {
450 magneto_snowball_mode: magneto_snowball {
451 snowball_cfg1 {
452 ste,pins = "GPIO165_C21"; /* MAG_DRDY */
453 ste,config = <&gpio_in_pu>;
454 };
455 };
456 };
457 gbf {
458 gbf_snowball_mode: gbf_snowball {
459 /*
460 * GBF (GPS, Bluetooth, FM-radio) interface,
461 * pull low to reset state
462 */
463 snowball_cfg1 {
464 ste,pins = "GPIO171_D23"; /* GBF_ENA_RESET */
465 ste,config = <&gpio_out_lo>;
466 };
467 };
468 };
469 wlan {
470 wlan_snowball_mode: wlan_snowball {
471 /*
472 * Activate this mode with the WLAN chip.
473 * These are plain GPIO pins used by WLAN
474 */
475 snowball_cfg1 {
476 ste,pins =
477 "GPIO161_D21", /* WLAN_PMU_EN */
478 "GPIO215_AH13"; /* WLAN_ENA */
479 ste,config = <&gpio_out_lo>;
480 };
481 snowball_cfg2 {
482 ste,pins = "GPIO216_AG12"; /* WLAN_IRQ */
483 ste,config = <&gpio_in_pu>;
484 };
485 };
486 };
487 };
488
489 mcde@a0350000 {
490 pinctrl-names = "default", "sleep";
491 pinctrl-0 = <&lcd_default_mode>;
492 pinctrl-1 = <&lcd_sleep_mode>;
493 };
269 }; 494 };
270}; 495};
diff --git a/arch/arm/boot/dts/stih415-pinctrl.dtsi b/arch/arm/boot/dts/stih415-pinctrl.dtsi
index 1d322b24d1e4..e56449d41481 100644
--- a/arch/arm/boot/dts/stih415-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih415-pinctrl.dtsi
@@ -86,6 +86,24 @@
86 }; 86 };
87 }; 87 };
88 }; 88 };
89
90 sbc_i2c0 {
91 pinctrl_sbc_i2c0_default: sbc_i2c0-default {
92 st,pins {
93 sda = <&PIO4 6 ALT1 BIDIR>;
94 scl = <&PIO4 5 ALT1 BIDIR>;
95 };
96 };
97 };
98
99 sbc_i2c1 {
100 pinctrl_sbc_i2c1_default: sbc_i2c1-default {
101 st,pins {
102 sda = <&PIO3 2 ALT2 BIDIR>;
103 scl = <&PIO3 1 ALT2 BIDIR>;
104 };
105 };
106 };
89 }; 107 };
90 108
91 pin-controller-front { 109 pin-controller-front {
@@ -143,6 +161,24 @@
143 reg = <0x7000 0x100>; 161 reg = <0x7000 0x100>;
144 st,bank-name = "PIO12"; 162 st,bank-name = "PIO12";
145 }; 163 };
164
165 i2c0 {
166 pinctrl_i2c0_default: i2c0-default {
167 st,pins {
168 sda = <&PIO9 3 ALT1 BIDIR>;
169 scl = <&PIO9 2 ALT1 BIDIR>;
170 };
171 };
172 };
173
174 i2c1 {
175 pinctrl_i2c1_default: i2c1-default {
176 st,pins {
177 sda = <&PIO12 1 ALT1 BIDIR>;
178 scl = <&PIO12 0 ALT1 BIDIR>;
179 };
180 };
181 };
146 }; 182 };
147 183
148 pin-controller-rear { 184 pin-controller-rear {
diff --git a/arch/arm/boot/dts/stih415.dtsi b/arch/arm/boot/dts/stih415.dtsi
index 74ab8ded4b49..d9c7dd1d95a4 100644
--- a/arch/arm/boot/dts/stih415.dtsi
+++ b/arch/arm/boot/dts/stih415.dtsi
@@ -9,6 +9,7 @@
9#include "stih41x.dtsi" 9#include "stih41x.dtsi"
10#include "stih415-clock.dtsi" 10#include "stih415-clock.dtsi"
11#include "stih415-pinctrl.dtsi" 11#include "stih415-pinctrl.dtsi"
12#include <dt-bindings/interrupt-controller/arm-gic.h>
12/ { 13/ {
13 14
14 L2: cache-controller { 15 L2: cache-controller {
@@ -83,5 +84,57 @@
83 pinctrl-names = "default"; 84 pinctrl-names = "default";
84 pinctrl-0 = <&pinctrl_sbc_serial1>; 85 pinctrl-0 = <&pinctrl_sbc_serial1>;
85 }; 86 };
87
88 i2c@fed40000 {
89 compatible = "st,comms-ssc4-i2c";
90 reg = <0xfed40000 0x110>;
91 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
92 clocks = <&CLKS_ICN_REG_0>;
93 clock-names = "ssc";
94 clock-frequency = <400000>;
95 pinctrl-names = "default";
96 pinctrl-0 = <&pinctrl_i2c0_default>;
97
98 status = "disabled";
99 };
100
101 i2c@fed41000 {
102 compatible = "st,comms-ssc4-i2c";
103 reg = <0xfed41000 0x110>;
104 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
105 clocks = <&CLKS_ICN_REG_0>;
106 clock-names = "ssc";
107 clock-frequency = <400000>;
108 pinctrl-names = "default";
109 pinctrl-0 = <&pinctrl_i2c1_default>;
110
111 status = "disabled";
112 };
113
114 i2c@fe540000 {
115 compatible = "st,comms-ssc4-i2c";
116 reg = <0xfe540000 0x110>;
117 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
118 clocks = <&CLK_SYSIN>;
119 clock-names = "ssc";
120 clock-frequency = <400000>;
121 pinctrl-names = "default";
122 pinctrl-0 = <&pinctrl_sbc_i2c0_default>;
123
124 status = "disabled";
125 };
126
127 i2c@fe541000 {
128 compatible = "st,comms-ssc4-i2c";
129 reg = <0xfe541000 0x110>;
130 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
131 clocks = <&CLK_SYSIN>;
132 clock-names = "ssc";
133 clock-frequency = <400000>;
134 pinctrl-names = "default";
135 pinctrl-0 = <&pinctrl_sbc_i2c1_default>;
136
137 status = "disabled";
138 };
86 }; 139 };
87}; 140};
diff --git a/arch/arm/boot/dts/stih416-pinctrl.dtsi b/arch/arm/boot/dts/stih416-pinctrl.dtsi
index 0f246c979262..b29ff4ba542c 100644
--- a/arch/arm/boot/dts/stih416-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih416-pinctrl.dtsi
@@ -97,6 +97,24 @@
97 }; 97 };
98 }; 98 };
99 }; 99 };
100
101 sbc_i2c0 {
102 pinctrl_sbc_i2c0_default: sbc_i2c0-default {
103 st,pins {
104 sda = <&PIO4 6 ALT1 BIDIR>;
105 scl = <&PIO4 5 ALT1 BIDIR>;
106 };
107 };
108 };
109
110 sbc_i2c1 {
111 pinctrl_sbc_i2c1_default: sbc_i2c1-default {
112 st,pins {
113 sda = <&PIO3 2 ALT2 BIDIR>;
114 scl = <&PIO3 1 ALT2 BIDIR>;
115 };
116 };
117 };
100 }; 118 };
101 119
102 pin-controller-front { 120 pin-controller-front {
@@ -175,6 +193,23 @@
175 }; 193 };
176 }; 194 };
177 195
196 i2c0 {
197 pinctrl_i2c0_default: i2c0-default {
198 st,pins {
199 sda = <&PIO9 3 ALT1 BIDIR>;
200 scl = <&PIO9 2 ALT1 BIDIR>;
201 };
202 };
203 };
204
205 i2c1 {
206 pinctrl_i2c1_default: i2c1-default {
207 st,pins {
208 sda = <&PIO12 1 ALT1 BIDIR>;
209 scl = <&PIO12 0 ALT1 BIDIR>;
210 };
211 };
212 };
178 }; 213 };
179 214
180 pin-controller-rear { 215 pin-controller-rear {
diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
index 1a0326ea7d07..b7ab47b95816 100644
--- a/arch/arm/boot/dts/stih416.dtsi
+++ b/arch/arm/boot/dts/stih416.dtsi
@@ -9,6 +9,7 @@
9#include "stih41x.dtsi" 9#include "stih41x.dtsi"
10#include "stih416-clock.dtsi" 10#include "stih416-clock.dtsi"
11#include "stih416-pinctrl.dtsi" 11#include "stih416-pinctrl.dtsi"
12#include <dt-bindings/interrupt-controller/arm-gic.h>
12/ { 13/ {
13 L2: cache-controller { 14 L2: cache-controller {
14 compatible = "arm,pl310-cache"; 15 compatible = "arm,pl310-cache";
@@ -92,5 +93,57 @@
92 pinctrl-0 = <&pinctrl_sbc_serial1>; 93 pinctrl-0 = <&pinctrl_sbc_serial1>;
93 clocks = <&CLK_SYSIN>; 94 clocks = <&CLK_SYSIN>;
94 }; 95 };
96
97 i2c@fed40000 {
98 compatible = "st,comms-ssc4-i2c";
99 reg = <0xfed40000 0x110>;
100 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
101 clocks = <&CLK_S_ICN_REG_0>;
102 clock-names = "ssc";
103 clock-frequency = <400000>;
104 pinctrl-names = "default";
105 pinctrl-0 = <&pinctrl_i2c0_default>;
106
107 status = "disabled";
108 };
109
110 i2c@fed41000 {
111 compatible = "st,comms-ssc4-i2c";
112 reg = <0xfed41000 0x110>;
113 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
114 clocks = <&CLK_S_ICN_REG_0>;
115 clock-names = "ssc";
116 clock-frequency = <400000>;
117 pinctrl-names = "default";
118 pinctrl-0 = <&pinctrl_i2c1_default>;
119
120 status = "disabled";
121 };
122
123 i2c@fe540000 {
124 compatible = "st,comms-ssc4-i2c";
125 reg = <0xfe540000 0x110>;
126 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
127 clocks = <&CLK_SYSIN>;
128 clock-names = "ssc";
129 clock-frequency = <400000>;
130 pinctrl-names = "default";
131 pinctrl-0 = <&pinctrl_sbc_i2c0_default>;
132
133 status = "disabled";
134 };
135
136 i2c@fe541000 {
137 compatible = "st,comms-ssc4-i2c";
138 reg = <0xfe541000 0x110>;
139 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
140 clocks = <&CLK_SYSIN>;
141 clock-names = "ssc";
142 clock-frequency = <400000>;
143 pinctrl-names = "default";
144 pinctrl-0 = <&pinctrl_sbc_i2c1_default>;
145
146 status = "disabled";
147 };
95 }; 148 };
96}; 149};
diff --git a/arch/arm/boot/dts/stih41x-b2000.dtsi b/arch/arm/boot/dts/stih41x-b2000.dtsi
index 8e694d2b8f5b..1e6aa92772f5 100644
--- a/arch/arm/boot/dts/stih41x-b2000.dtsi
+++ b/arch/arm/boot/dts/stih41x-b2000.dtsi
@@ -37,5 +37,14 @@
37 }; 37 };
38 }; 38 };
39 39
40 /* HDMI Tx I2C */
41 i2c@fed41000 {
42 /* HDMI V1.3a supports Standard mode only */
43 clock-frequency = <100000>;
44 i2c-min-scl-pulse-width-us = <0>;
45 i2c-min-sda-pulse-width-us = <5>;
46
47 status = "okay";
48 };
40 }; 49 };
41}; 50};
diff --git a/arch/arm/boot/dts/stih41x-b2020.dtsi b/arch/arm/boot/dts/stih41x-b2020.dtsi
index 133e18143b1b..0ef0a69df8ea 100644
--- a/arch/arm/boot/dts/stih41x-b2020.dtsi
+++ b/arch/arm/boot/dts/stih41x-b2020.dtsi
@@ -38,5 +38,27 @@
38 default-state = "off"; 38 default-state = "off";
39 }; 39 };
40 }; 40 };
41
42 i2c@fed40000 {
43 status = "okay";
44 };
45
46 /* HDMI Tx I2C */
47 i2c@fed41000 {
48 /* HDMI V1.3a supports Standard mode only */
49 clock-frequency = <100000>;
50 i2c-min-scl-pulse-width-us = <0>;
51 i2c-min-sda-pulse-width-us = <5>;
52
53 status = "okay";
54 };
55
56 i2c@fe540000 {
57 status = "okay";
58 };
59
60 i2c@fe541000 {
61 status = "okay";
62 };
41 }; 63 };
42}; 64};
diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts
index cb5ec23b03a7..73aecfb57ccb 100644
--- a/arch/arm/boot/dts/tegra114-dalmore.dts
+++ b/arch/arm/boot/dts/tegra114-dalmore.dts
@@ -7,11 +7,42 @@
7 model = "NVIDIA Tegra114 Dalmore evaluation board"; 7 model = "NVIDIA Tegra114 Dalmore evaluation board";
8 compatible = "nvidia,dalmore", "nvidia,tegra114"; 8 compatible = "nvidia,dalmore", "nvidia,tegra114";
9 9
10 aliases {
11 rtc0 = "/i2c@7000d000/tps65913@58";
12 rtc1 = "/rtc@7000e000";
13 };
14
10 memory { 15 memory {
11 reg = <0x80000000 0x40000000>; 16 reg = <0x80000000 0x40000000>;
12 }; 17 };
13 18
14 pinmux { 19 host1x@50000000 {
20 hdmi@54280000 {
21 status = "okay";
22
23 vdd-supply = <&vdd_hdmi_reg>;
24 pll-supply = <&palmas_smps3_reg>;
25
26 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
27 nvidia,hpd-gpio =
28 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
29 };
30
31 dsi@54300000 {
32 status = "okay";
33
34 panel@0 {
35 compatible = "panasonic,vvx10f004b00",
36 "simple-panel";
37 reg = <0>;
38
39 power-supply = <&avdd_lcd_reg>;
40 backlight = <&backlight>;
41 };
42 };
43 };
44
45 pinmux@70000868 {
15 pinctrl-names = "default"; 46 pinctrl-names = "default";
16 pinctrl-0 = <&state_default>; 47 pinctrl-0 = <&state_default>;
17 48
@@ -19,41 +50,41 @@
19 clk1_out_pw4 { 50 clk1_out_pw4 {
20 nvidia,pins = "clk1_out_pw4"; 51 nvidia,pins = "clk1_out_pw4";
21 nvidia,function = "extperiph1"; 52 nvidia,function = "extperiph1";
22 nvidia,pull = <0>; 53 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
23 nvidia,tristate = <0>; 54 nvidia,tristate = <TEGRA_PIN_DISABLE>;
24 nvidia,enable-input = <0>; 55 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
25 }; 56 };
26 dap1_din_pn1 { 57 dap1_din_pn1 {
27 nvidia,pins = "dap1_din_pn1"; 58 nvidia,pins = "dap1_din_pn1";
28 nvidia,function = "i2s0"; 59 nvidia,function = "i2s0";
29 nvidia,pull = <0>; 60 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
30 nvidia,tristate = <1>; 61 nvidia,tristate = <TEGRA_PIN_ENABLE>;
31 nvidia,enable-input = <1>; 62 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
32 }; 63 };
33 dap1_dout_pn2 { 64 dap1_dout_pn2 {
34 nvidia,pins = "dap1_dout_pn2", 65 nvidia,pins = "dap1_dout_pn2",
35 "dap1_fs_pn0", 66 "dap1_fs_pn0",
36 "dap1_sclk_pn3"; 67 "dap1_sclk_pn3";
37 nvidia,function = "i2s0"; 68 nvidia,function = "i2s0";
38 nvidia,pull = <0>; 69 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
39 nvidia,tristate = <0>; 70 nvidia,tristate = <TEGRA_PIN_DISABLE>;
40 nvidia,enable-input = <1>; 71 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
41 }; 72 };
42 dap2_din_pa4 { 73 dap2_din_pa4 {
43 nvidia,pins = "dap2_din_pa4"; 74 nvidia,pins = "dap2_din_pa4";
44 nvidia,function = "i2s1"; 75 nvidia,function = "i2s1";
45 nvidia,pull = <0>; 76 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
46 nvidia,tristate = <1>; 77 nvidia,tristate = <TEGRA_PIN_ENABLE>;
47 nvidia,enable-input = <1>; 78 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
48 }; 79 };
49 dap2_dout_pa5 { 80 dap2_dout_pa5 {
50 nvidia,pins = "dap2_dout_pa5", 81 nvidia,pins = "dap2_dout_pa5",
51 "dap2_fs_pa2", 82 "dap2_fs_pa2",
52 "dap2_sclk_pa3"; 83 "dap2_sclk_pa3";
53 nvidia,function = "i2s1"; 84 nvidia,function = "i2s1";
54 nvidia,pull = <0>; 85 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
55 nvidia,tristate = <0>; 86 nvidia,tristate = <TEGRA_PIN_DISABLE>;
56 nvidia,enable-input = <1>; 87 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
57 }; 88 };
58 dap4_din_pp5 { 89 dap4_din_pp5 {
59 nvidia,pins = "dap4_din_pp5", 90 nvidia,pins = "dap4_din_pp5",
@@ -61,17 +92,17 @@
61 "dap4_fs_pp4", 92 "dap4_fs_pp4",
62 "dap4_sclk_pp7"; 93 "dap4_sclk_pp7";
63 nvidia,function = "i2s3"; 94 nvidia,function = "i2s3";
64 nvidia,pull = <0>; 95 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
65 nvidia,tristate = <0>; 96 nvidia,tristate = <TEGRA_PIN_DISABLE>;
66 nvidia,enable-input = <1>; 97 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
67 }; 98 };
68 dvfs_pwm_px0 { 99 dvfs_pwm_px0 {
69 nvidia,pins = "dvfs_pwm_px0", 100 nvidia,pins = "dvfs_pwm_px0",
70 "dvfs_clk_px2"; 101 "dvfs_clk_px2";
71 nvidia,function = "cldvfs"; 102 nvidia,function = "cldvfs";
72 nvidia,pull = <0>; 103 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
73 nvidia,tristate = <0>; 104 nvidia,tristate = <TEGRA_PIN_DISABLE>;
74 nvidia,enable-input = <0>; 105 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
75 }; 106 };
76 ulpi_clk_py0 { 107 ulpi_clk_py0 {
77 nvidia,pins = "ulpi_clk_py0", 108 nvidia,pins = "ulpi_clk_py0",
@@ -84,128 +115,128 @@
84 "ulpi_data6_po7", 115 "ulpi_data6_po7",
85 "ulpi_data7_po0"; 116 "ulpi_data7_po0";
86 nvidia,function = "ulpi"; 117 nvidia,function = "ulpi";
87 nvidia,pull = <0>; 118 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
88 nvidia,tristate = <0>; 119 nvidia,tristate = <TEGRA_PIN_DISABLE>;
89 nvidia,enable-input = <1>; 120 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
90 }; 121 };
91 ulpi_dir_py1 { 122 ulpi_dir_py1 {
92 nvidia,pins = "ulpi_dir_py1", 123 nvidia,pins = "ulpi_dir_py1",
93 "ulpi_nxt_py2"; 124 "ulpi_nxt_py2";
94 nvidia,function = "ulpi"; 125 nvidia,function = "ulpi";
95 nvidia,pull = <0>; 126 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
96 nvidia,tristate = <1>; 127 nvidia,tristate = <TEGRA_PIN_ENABLE>;
97 nvidia,enable-input = <1>; 128 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
98 }; 129 };
99 ulpi_stp_py3 { 130 ulpi_stp_py3 {
100 nvidia,pins = "ulpi_stp_py3"; 131 nvidia,pins = "ulpi_stp_py3";
101 nvidia,function = "ulpi"; 132 nvidia,function = "ulpi";
102 nvidia,pull = <0>; 133 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
103 nvidia,tristate = <0>; 134 nvidia,tristate = <TEGRA_PIN_DISABLE>;
104 nvidia,enable-input = <0>; 135 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
105 }; 136 };
106 cam_i2c_scl_pbb1 { 137 cam_i2c_scl_pbb1 {
107 nvidia,pins = "cam_i2c_scl_pbb1", 138 nvidia,pins = "cam_i2c_scl_pbb1",
108 "cam_i2c_sda_pbb2"; 139 "cam_i2c_sda_pbb2";
109 nvidia,function = "i2c3"; 140 nvidia,function = "i2c3";
110 nvidia,pull = <0>; 141 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
111 nvidia,tristate = <0>; 142 nvidia,tristate = <TEGRA_PIN_DISABLE>;
112 nvidia,enable-input = <1>; 143 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
113 nvidia,lock = <0>; 144 nvidia,lock = <TEGRA_PIN_DISABLE>;
114 nvidia,open-drain = <0>; 145 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
115 }; 146 };
116 cam_mclk_pcc0 { 147 cam_mclk_pcc0 {
117 nvidia,pins = "cam_mclk_pcc0", 148 nvidia,pins = "cam_mclk_pcc0",
118 "pbb0"; 149 "pbb0";
119 nvidia,function = "vi_alt3"; 150 nvidia,function = "vi_alt3";
120 nvidia,pull = <0>; 151 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
121 nvidia,tristate = <0>; 152 nvidia,tristate = <TEGRA_PIN_DISABLE>;
122 nvidia,enable-input = <0>; 153 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
123 nvidia,lock = <0>; 154 nvidia,lock = <TEGRA_PIN_DISABLE>;
124 }; 155 };
125 gen2_i2c_scl_pt5 { 156 gen2_i2c_scl_pt5 {
126 nvidia,pins = "gen2_i2c_scl_pt5", 157 nvidia,pins = "gen2_i2c_scl_pt5",
127 "gen2_i2c_sda_pt6"; 158 "gen2_i2c_sda_pt6";
128 nvidia,function = "i2c2"; 159 nvidia,function = "i2c2";
129 nvidia,pull = <0>; 160 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
130 nvidia,tristate = <0>; 161 nvidia,tristate = <TEGRA_PIN_DISABLE>;
131 nvidia,enable-input = <1>; 162 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
132 nvidia,lock = <0>; 163 nvidia,lock = <TEGRA_PIN_DISABLE>;
133 nvidia,open-drain = <0>; 164 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
134 }; 165 };
135 gmi_a16_pj7 { 166 gmi_a16_pj7 {
136 nvidia,pins = "gmi_a16_pj7"; 167 nvidia,pins = "gmi_a16_pj7";
137 nvidia,function = "uartd"; 168 nvidia,function = "uartd";
138 nvidia,pull = <0>; 169 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
139 nvidia,tristate = <0>; 170 nvidia,tristate = <TEGRA_PIN_DISABLE>;
140 nvidia,enable-input = <0>; 171 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
141 }; 172 };
142 gmi_a17_pb0 { 173 gmi_a17_pb0 {
143 nvidia,pins = "gmi_a17_pb0", 174 nvidia,pins = "gmi_a17_pb0",
144 "gmi_a18_pb1"; 175 "gmi_a18_pb1";
145 nvidia,function = "uartd"; 176 nvidia,function = "uartd";
146 nvidia,pull = <0>; 177 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
147 nvidia,tristate = <1>; 178 nvidia,tristate = <TEGRA_PIN_ENABLE>;
148 nvidia,enable-input = <1>; 179 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
149 }; 180 };
150 gmi_a19_pk7 { 181 gmi_a19_pk7 {
151 nvidia,pins = "gmi_a19_pk7"; 182 nvidia,pins = "gmi_a19_pk7";
152 nvidia,function = "uartd"; 183 nvidia,function = "uartd";
153 nvidia,pull = <0>; 184 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
154 nvidia,tristate = <0>; 185 nvidia,tristate = <TEGRA_PIN_DISABLE>;
155 nvidia,enable-input = <0>; 186 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
156 }; 187 };
157 gmi_ad5_pg5 { 188 gmi_ad5_pg5 {
158 nvidia,pins = "gmi_ad5_pg5", 189 nvidia,pins = "gmi_ad5_pg5",
159 "gmi_cs6_n_pi3", 190 "gmi_cs6_n_pi3",
160 "gmi_wr_n_pi0"; 191 "gmi_wr_n_pi0";
161 nvidia,function = "spi4"; 192 nvidia,function = "spi4";
162 nvidia,pull = <0>; 193 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
163 nvidia,tristate = <0>; 194 nvidia,tristate = <TEGRA_PIN_DISABLE>;
164 nvidia,enable-input = <1>; 195 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
165 }; 196 };
166 gmi_ad6_pg6 { 197 gmi_ad6_pg6 {
167 nvidia,pins = "gmi_ad6_pg6", 198 nvidia,pins = "gmi_ad6_pg6",
168 "gmi_ad7_pg7"; 199 "gmi_ad7_pg7";
169 nvidia,function = "spi4"; 200 nvidia,function = "spi4";
170 nvidia,pull = <2>; 201 nvidia,pull = <TEGRA_PIN_PULL_UP>;
171 nvidia,tristate = <0>; 202 nvidia,tristate = <TEGRA_PIN_DISABLE>;
172 nvidia,enable-input = <1>; 203 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
173 }; 204 };
174 gmi_ad12_ph4 { 205 gmi_ad12_ph4 {
175 nvidia,pins = "gmi_ad12_ph4"; 206 nvidia,pins = "gmi_ad12_ph4";
176 nvidia,function = "rsvd4"; 207 nvidia,function = "rsvd4";
177 nvidia,pull = <0>; 208 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
178 nvidia,tristate = <0>; 209 nvidia,tristate = <TEGRA_PIN_DISABLE>;
179 nvidia,enable-input = <0>; 210 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
180 }; 211 };
181 gmi_ad9_ph1 { 212 gmi_ad9_ph1 {
182 nvidia,pins = "gmi_ad9_ph1"; 213 nvidia,pins = "gmi_ad9_ph1";
183 nvidia,function = "pwm1"; 214 nvidia,function = "pwm1";
184 nvidia,pull = <0>; 215 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
185 nvidia,tristate = <0>; 216 nvidia,tristate = <TEGRA_PIN_DISABLE>;
186 nvidia,enable-input = <0>; 217 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
187 }; 218 };
188 gmi_cs1_n_pj2 { 219 gmi_cs1_n_pj2 {
189 nvidia,pins = "gmi_cs1_n_pj2", 220 nvidia,pins = "gmi_cs1_n_pj2",
190 "gmi_oe_n_pi1"; 221 "gmi_oe_n_pi1";
191 nvidia,function = "soc"; 222 nvidia,function = "soc";
192 nvidia,pull = <0>; 223 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
193 nvidia,tristate = <1>; 224 nvidia,tristate = <TEGRA_PIN_ENABLE>;
194 nvidia,enable-input = <1>; 225 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
195 }; 226 };
196 clk2_out_pw5 { 227 clk2_out_pw5 {
197 nvidia,pins = "clk2_out_pw5"; 228 nvidia,pins = "clk2_out_pw5";
198 nvidia,function = "extperiph2"; 229 nvidia,function = "extperiph2";
199 nvidia,pull = <0>; 230 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
200 nvidia,tristate = <0>; 231 nvidia,tristate = <TEGRA_PIN_DISABLE>;
201 nvidia,enable-input = <0>; 232 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
202 }; 233 };
203 sdmmc1_clk_pz0 { 234 sdmmc1_clk_pz0 {
204 nvidia,pins = "sdmmc1_clk_pz0"; 235 nvidia,pins = "sdmmc1_clk_pz0";
205 nvidia,function = "sdmmc1"; 236 nvidia,function = "sdmmc1";
206 nvidia,pull = <0>; 237 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
207 nvidia,tristate = <0>; 238 nvidia,tristate = <TEGRA_PIN_DISABLE>;
208 nvidia,enable-input = <1>; 239 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
209 }; 240 };
210 sdmmc1_cmd_pz1 { 241 sdmmc1_cmd_pz1 {
211 nvidia,pins = "sdmmc1_cmd_pz1", 242 nvidia,pins = "sdmmc1_cmd_pz1",
@@ -214,23 +245,23 @@
214 "sdmmc1_dat2_py5", 245 "sdmmc1_dat2_py5",
215 "sdmmc1_dat3_py4"; 246 "sdmmc1_dat3_py4";
216 nvidia,function = "sdmmc1"; 247 nvidia,function = "sdmmc1";
217 nvidia,pull = <2>; 248 nvidia,pull = <TEGRA_PIN_PULL_UP>;
218 nvidia,tristate = <0>; 249 nvidia,tristate = <TEGRA_PIN_DISABLE>;
219 nvidia,enable-input = <1>; 250 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
220 }; 251 };
221 sdmmc1_wp_n_pv3 { 252 sdmmc1_wp_n_pv3 {
222 nvidia,pins = "sdmmc1_wp_n_pv3"; 253 nvidia,pins = "sdmmc1_wp_n_pv3";
223 nvidia,function = "spi4"; 254 nvidia,function = "spi4";
224 nvidia,pull = <2>; 255 nvidia,pull = <TEGRA_PIN_PULL_UP>;
225 nvidia,tristate = <0>; 256 nvidia,tristate = <TEGRA_PIN_DISABLE>;
226 nvidia,enable-input = <0>; 257 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
227 }; 258 };
228 sdmmc3_clk_pa6 { 259 sdmmc3_clk_pa6 {
229 nvidia,pins = "sdmmc3_clk_pa6"; 260 nvidia,pins = "sdmmc3_clk_pa6";
230 nvidia,function = "sdmmc3"; 261 nvidia,function = "sdmmc3";
231 nvidia,pull = <0>; 262 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
232 nvidia,tristate = <0>; 263 nvidia,tristate = <TEGRA_PIN_DISABLE>;
233 nvidia,enable-input = <1>; 264 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
234 }; 265 };
235 sdmmc3_cmd_pa7 { 266 sdmmc3_cmd_pa7 {
236 nvidia,pins = "sdmmc3_cmd_pa7", 267 nvidia,pins = "sdmmc3_cmd_pa7",
@@ -242,16 +273,16 @@
242 "sdmmc3_clk_lb_out_pee4", 273 "sdmmc3_clk_lb_out_pee4",
243 "sdmmc3_clk_lb_in_pee5"; 274 "sdmmc3_clk_lb_in_pee5";
244 nvidia,function = "sdmmc3"; 275 nvidia,function = "sdmmc3";
245 nvidia,pull = <2>; 276 nvidia,pull = <TEGRA_PIN_PULL_UP>;
246 nvidia,tristate = <0>; 277 nvidia,tristate = <TEGRA_PIN_DISABLE>;
247 nvidia,enable-input = <1>; 278 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
248 }; 279 };
249 sdmmc4_clk_pcc4 { 280 sdmmc4_clk_pcc4 {
250 nvidia,pins = "sdmmc4_clk_pcc4"; 281 nvidia,pins = "sdmmc4_clk_pcc4";
251 nvidia,function = "sdmmc4"; 282 nvidia,function = "sdmmc4";
252 nvidia,pull = <0>; 283 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
253 nvidia,tristate = <0>; 284 nvidia,tristate = <TEGRA_PIN_DISABLE>;
254 nvidia,enable-input = <1>; 285 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
255 }; 286 };
256 sdmmc4_cmd_pt7 { 287 sdmmc4_cmd_pt7 {
257 nvidia,pins = "sdmmc4_cmd_pt7", 288 nvidia,pins = "sdmmc4_cmd_pt7",
@@ -264,16 +295,16 @@
264 "sdmmc4_dat6_paa6", 295 "sdmmc4_dat6_paa6",
265 "sdmmc4_dat7_paa7"; 296 "sdmmc4_dat7_paa7";
266 nvidia,function = "sdmmc4"; 297 nvidia,function = "sdmmc4";
267 nvidia,pull = <2>; 298 nvidia,pull = <TEGRA_PIN_PULL_UP>;
268 nvidia,tristate = <0>; 299 nvidia,tristate = <TEGRA_PIN_DISABLE>;
269 nvidia,enable-input = <1>; 300 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
270 }; 301 };
271 clk_32k_out_pa0 { 302 clk_32k_out_pa0 {
272 nvidia,pins = "clk_32k_out_pa0"; 303 nvidia,pins = "clk_32k_out_pa0";
273 nvidia,function = "blink"; 304 nvidia,function = "blink";
274 nvidia,pull = <0>; 305 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
275 nvidia,tristate = <0>; 306 nvidia,tristate = <TEGRA_PIN_DISABLE>;
276 nvidia,enable-input = <0>; 307 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
277 }; 308 };
278 kb_col0_pq0 { 309 kb_col0_pq0 {
279 nvidia,pins = "kb_col0_pq0", 310 nvidia,pins = "kb_col0_pq0",
@@ -283,265 +314,265 @@
283 "kb_row1_pr1", 314 "kb_row1_pr1",
284 "kb_row2_pr2"; 315 "kb_row2_pr2";
285 nvidia,function = "kbc"; 316 nvidia,function = "kbc";
286 nvidia,pull = <2>; 317 nvidia,pull = <TEGRA_PIN_PULL_UP>;
287 nvidia,tristate = <0>; 318 nvidia,tristate = <TEGRA_PIN_DISABLE>;
288 nvidia,enable-input = <1>; 319 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
289 }; 320 };
290 dap3_din_pp1 { 321 dap3_din_pp1 {
291 nvidia,pins = "dap3_din_pp1", 322 nvidia,pins = "dap3_din_pp1",
292 "dap3_sclk_pp3"; 323 "dap3_sclk_pp3";
293 nvidia,function = "displayb"; 324 nvidia,function = "displayb";
294 nvidia,pull = <0>; 325 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
295 nvidia,tristate = <1>; 326 nvidia,tristate = <TEGRA_PIN_ENABLE>;
296 nvidia,enable-input = <0>; 327 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
297 }; 328 };
298 pv0 { 329 pv0 {
299 nvidia,pins = "pv0"; 330 nvidia,pins = "pv0";
300 nvidia,function = "rsvd4"; 331 nvidia,function = "rsvd4";
301 nvidia,pull = <0>; 332 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
302 nvidia,tristate = <1>; 333 nvidia,tristate = <TEGRA_PIN_ENABLE>;
303 nvidia,enable-input = <0>; 334 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
304 }; 335 };
305 kb_row7_pr7 { 336 kb_row7_pr7 {
306 nvidia,pins = "kb_row7_pr7"; 337 nvidia,pins = "kb_row7_pr7";
307 nvidia,function = "rsvd2"; 338 nvidia,function = "rsvd2";
308 nvidia,pull = <2>; 339 nvidia,pull = <TEGRA_PIN_PULL_UP>;
309 nvidia,tristate = <0>; 340 nvidia,tristate = <TEGRA_PIN_DISABLE>;
310 nvidia,enable-input = <1>; 341 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
311 }; 342 };
312 kb_row10_ps2 { 343 kb_row10_ps2 {
313 nvidia,pins = "kb_row10_ps2"; 344 nvidia,pins = "kb_row10_ps2";
314 nvidia,function = "uarta"; 345 nvidia,function = "uarta";
315 nvidia,pull = <0>; 346 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
316 nvidia,tristate = <1>; 347 nvidia,tristate = <TEGRA_PIN_ENABLE>;
317 nvidia,enable-input = <1>; 348 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
318 }; 349 };
319 kb_row9_ps1 { 350 kb_row9_ps1 {
320 nvidia,pins = "kb_row9_ps1"; 351 nvidia,pins = "kb_row9_ps1";
321 nvidia,function = "uarta"; 352 nvidia,function = "uarta";
322 nvidia,pull = <0>; 353 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
323 nvidia,tristate = <0>; 354 nvidia,tristate = <TEGRA_PIN_DISABLE>;
324 nvidia,enable-input = <0>; 355 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
325 }; 356 };
326 pwr_i2c_scl_pz6 { 357 pwr_i2c_scl_pz6 {
327 nvidia,pins = "pwr_i2c_scl_pz6", 358 nvidia,pins = "pwr_i2c_scl_pz6",
328 "pwr_i2c_sda_pz7"; 359 "pwr_i2c_sda_pz7";
329 nvidia,function = "i2cpwr"; 360 nvidia,function = "i2cpwr";
330 nvidia,pull = <0>; 361 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
331 nvidia,tristate = <0>; 362 nvidia,tristate = <TEGRA_PIN_DISABLE>;
332 nvidia,enable-input = <1>; 363 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
333 nvidia,lock = <0>; 364 nvidia,lock = <TEGRA_PIN_DISABLE>;
334 nvidia,open-drain = <0>; 365 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
335 }; 366 };
336 sys_clk_req_pz5 { 367 sys_clk_req_pz5 {
337 nvidia,pins = "sys_clk_req_pz5"; 368 nvidia,pins = "sys_clk_req_pz5";
338 nvidia,function = "sysclk"; 369 nvidia,function = "sysclk";
339 nvidia,pull = <0>; 370 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
340 nvidia,tristate = <0>; 371 nvidia,tristate = <TEGRA_PIN_DISABLE>;
341 nvidia,enable-input = <0>; 372 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
342 }; 373 };
343 core_pwr_req { 374 core_pwr_req {
344 nvidia,pins = "core_pwr_req"; 375 nvidia,pins = "core_pwr_req";
345 nvidia,function = "pwron"; 376 nvidia,function = "pwron";
346 nvidia,pull = <0>; 377 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
347 nvidia,tristate = <0>; 378 nvidia,tristate = <TEGRA_PIN_DISABLE>;
348 nvidia,enable-input = <0>; 379 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
349 }; 380 };
350 cpu_pwr_req { 381 cpu_pwr_req {
351 nvidia,pins = "cpu_pwr_req"; 382 nvidia,pins = "cpu_pwr_req";
352 nvidia,function = "cpu"; 383 nvidia,function = "cpu";
353 nvidia,pull = <0>; 384 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
354 nvidia,tristate = <0>; 385 nvidia,tristate = <TEGRA_PIN_DISABLE>;
355 nvidia,enable-input = <0>; 386 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
356 }; 387 };
357 pwr_int_n { 388 pwr_int_n {
358 nvidia,pins = "pwr_int_n"; 389 nvidia,pins = "pwr_int_n";
359 nvidia,function = "pmi"; 390 nvidia,function = "pmi";
360 nvidia,pull = <0>; 391 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
361 nvidia,tristate = <1>; 392 nvidia,tristate = <TEGRA_PIN_ENABLE>;
362 nvidia,enable-input = <1>; 393 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
363 }; 394 };
364 reset_out_n { 395 reset_out_n {
365 nvidia,pins = "reset_out_n"; 396 nvidia,pins = "reset_out_n";
366 nvidia,function = "reset_out_n"; 397 nvidia,function = "reset_out_n";
367 nvidia,pull = <0>; 398 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
368 nvidia,tristate = <0>; 399 nvidia,tristate = <TEGRA_PIN_DISABLE>;
369 nvidia,enable-input = <0>; 400 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
370 }; 401 };
371 clk3_out_pee0 { 402 clk3_out_pee0 {
372 nvidia,pins = "clk3_out_pee0"; 403 nvidia,pins = "clk3_out_pee0";
373 nvidia,function = "extperiph3"; 404 nvidia,function = "extperiph3";
374 nvidia,pull = <0>; 405 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
375 nvidia,tristate = <0>; 406 nvidia,tristate = <TEGRA_PIN_DISABLE>;
376 nvidia,enable-input = <0>; 407 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
377 }; 408 };
378 gen1_i2c_scl_pc4 { 409 gen1_i2c_scl_pc4 {
379 nvidia,pins = "gen1_i2c_scl_pc4", 410 nvidia,pins = "gen1_i2c_scl_pc4",
380 "gen1_i2c_sda_pc5"; 411 "gen1_i2c_sda_pc5";
381 nvidia,function = "i2c1"; 412 nvidia,function = "i2c1";
382 nvidia,pull = <0>; 413 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
383 nvidia,tristate = <0>; 414 nvidia,tristate = <TEGRA_PIN_DISABLE>;
384 nvidia,enable-input = <1>; 415 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
385 nvidia,lock = <0>; 416 nvidia,lock = <TEGRA_PIN_DISABLE>;
386 nvidia,open-drain = <0>; 417 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
387 }; 418 };
388 uart2_cts_n_pj5 { 419 uart2_cts_n_pj5 {
389 nvidia,pins = "uart2_cts_n_pj5"; 420 nvidia,pins = "uart2_cts_n_pj5";
390 nvidia,function = "uartb"; 421 nvidia,function = "uartb";
391 nvidia,pull = <0>; 422 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
392 nvidia,tristate = <1>; 423 nvidia,tristate = <TEGRA_PIN_ENABLE>;
393 nvidia,enable-input = <1>; 424 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
394 }; 425 };
395 uart2_rts_n_pj6 { 426 uart2_rts_n_pj6 {
396 nvidia,pins = "uart2_rts_n_pj6"; 427 nvidia,pins = "uart2_rts_n_pj6";
397 nvidia,function = "uartb"; 428 nvidia,function = "uartb";
398 nvidia,pull = <0>; 429 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
399 nvidia,tristate = <0>; 430 nvidia,tristate = <TEGRA_PIN_DISABLE>;
400 nvidia,enable-input = <0>; 431 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
401 }; 432 };
402 uart2_rxd_pc3 { 433 uart2_rxd_pc3 {
403 nvidia,pins = "uart2_rxd_pc3"; 434 nvidia,pins = "uart2_rxd_pc3";
404 nvidia,function = "irda"; 435 nvidia,function = "irda";
405 nvidia,pull = <0>; 436 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
406 nvidia,tristate = <1>; 437 nvidia,tristate = <TEGRA_PIN_ENABLE>;
407 nvidia,enable-input = <1>; 438 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
408 }; 439 };
409 uart2_txd_pc2 { 440 uart2_txd_pc2 {
410 nvidia,pins = "uart2_txd_pc2"; 441 nvidia,pins = "uart2_txd_pc2";
411 nvidia,function = "irda"; 442 nvidia,function = "irda";
412 nvidia,pull = <0>; 443 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
413 nvidia,tristate = <0>; 444 nvidia,tristate = <TEGRA_PIN_DISABLE>;
414 nvidia,enable-input = <0>; 445 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
415 }; 446 };
416 uart3_cts_n_pa1 { 447 uart3_cts_n_pa1 {
417 nvidia,pins = "uart3_cts_n_pa1", 448 nvidia,pins = "uart3_cts_n_pa1",
418 "uart3_rxd_pw7"; 449 "uart3_rxd_pw7";
419 nvidia,function = "uartc"; 450 nvidia,function = "uartc";
420 nvidia,pull = <0>; 451 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
421 nvidia,tristate = <1>; 452 nvidia,tristate = <TEGRA_PIN_ENABLE>;
422 nvidia,enable-input = <1>; 453 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
423 }; 454 };
424 uart3_rts_n_pc0 { 455 uart3_rts_n_pc0 {
425 nvidia,pins = "uart3_rts_n_pc0", 456 nvidia,pins = "uart3_rts_n_pc0",
426 "uart3_txd_pw6"; 457 "uart3_txd_pw6";
427 nvidia,function = "uartc"; 458 nvidia,function = "uartc";
428 nvidia,pull = <0>; 459 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
429 nvidia,tristate = <0>; 460 nvidia,tristate = <TEGRA_PIN_DISABLE>;
430 nvidia,enable-input = <0>; 461 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
431 }; 462 };
432 owr { 463 owr {
433 nvidia,pins = "owr"; 464 nvidia,pins = "owr";
434 nvidia,function = "owr"; 465 nvidia,function = "owr";
435 nvidia,pull = <0>; 466 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
436 nvidia,tristate = <0>; 467 nvidia,tristate = <TEGRA_PIN_DISABLE>;
437 nvidia,enable-input = <1>; 468 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
438 }; 469 };
439 hdmi_cec_pee3 { 470 hdmi_cec_pee3 {
440 nvidia,pins = "hdmi_cec_pee3"; 471 nvidia,pins = "hdmi_cec_pee3";
441 nvidia,function = "cec"; 472 nvidia,function = "cec";
442 nvidia,pull = <0>; 473 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
443 nvidia,tristate = <0>; 474 nvidia,tristate = <TEGRA_PIN_DISABLE>;
444 nvidia,enable-input = <1>; 475 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
445 nvidia,lock = <0>; 476 nvidia,lock = <TEGRA_PIN_DISABLE>;
446 nvidia,open-drain = <0>; 477 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
447 }; 478 };
448 ddc_scl_pv4 { 479 ddc_scl_pv4 {
449 nvidia,pins = "ddc_scl_pv4", 480 nvidia,pins = "ddc_scl_pv4",
450 "ddc_sda_pv5"; 481 "ddc_sda_pv5";
451 nvidia,function = "i2c4"; 482 nvidia,function = "i2c4";
452 nvidia,pull = <0>; 483 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
453 nvidia,tristate = <0>; 484 nvidia,tristate = <TEGRA_PIN_DISABLE>;
454 nvidia,enable-input = <1>; 485 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
455 nvidia,lock = <0>; 486 nvidia,lock = <TEGRA_PIN_DISABLE>;
456 nvidia,rcv-sel = <1>; 487 nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
457 }; 488 };
458 spdif_in_pk6 { 489 spdif_in_pk6 {
459 nvidia,pins = "spdif_in_pk6"; 490 nvidia,pins = "spdif_in_pk6";
460 nvidia,function = "usb"; 491 nvidia,function = "usb";
461 nvidia,pull = <2>; 492 nvidia,pull = <TEGRA_PIN_PULL_UP>;
462 nvidia,tristate = <0>; 493 nvidia,tristate = <TEGRA_PIN_DISABLE>;
463 nvidia,enable-input = <1>; 494 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
464 nvidia,lock = <0>; 495 nvidia,lock = <TEGRA_PIN_DISABLE>;
465 }; 496 };
466 usb_vbus_en0_pn4 { 497 usb_vbus_en0_pn4 {
467 nvidia,pins = "usb_vbus_en0_pn4"; 498 nvidia,pins = "usb_vbus_en0_pn4";
468 nvidia,function = "usb"; 499 nvidia,function = "usb";
469 nvidia,pull = <2>; 500 nvidia,pull = <TEGRA_PIN_PULL_UP>;
470 nvidia,tristate = <0>; 501 nvidia,tristate = <TEGRA_PIN_DISABLE>;
471 nvidia,enable-input = <1>; 502 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
472 nvidia,lock = <0>; 503 nvidia,lock = <TEGRA_PIN_DISABLE>;
473 nvidia,open-drain = <1>; 504 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
474 }; 505 };
475 gpio_x6_aud_px6 { 506 gpio_x6_aud_px6 {
476 nvidia,pins = "gpio_x6_aud_px6"; 507 nvidia,pins = "gpio_x6_aud_px6";
477 nvidia,function = "spi6"; 508 nvidia,function = "spi6";
478 nvidia,pull = <2>; 509 nvidia,pull = <TEGRA_PIN_PULL_UP>;
479 nvidia,tristate = <1>; 510 nvidia,tristate = <TEGRA_PIN_ENABLE>;
480 nvidia,enable-input = <1>; 511 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
481 }; 512 };
482 gpio_x4_aud_px4 { 513 gpio_x4_aud_px4 {
483 nvidia,pins = "gpio_x4_aud_px4", 514 nvidia,pins = "gpio_x4_aud_px4",
484 "gpio_x7_aud_px7"; 515 "gpio_x7_aud_px7";
485 nvidia,function = "rsvd1"; 516 nvidia,function = "rsvd1";
486 nvidia,pull = <1>; 517 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
487 nvidia,tristate = <0>; 518 nvidia,tristate = <TEGRA_PIN_DISABLE>;
488 nvidia,enable-input = <0>; 519 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
489 }; 520 };
490 gpio_x5_aud_px5 { 521 gpio_x5_aud_px5 {
491 nvidia,pins = "gpio_x5_aud_px5"; 522 nvidia,pins = "gpio_x5_aud_px5";
492 nvidia,function = "rsvd1"; 523 nvidia,function = "rsvd1";
493 nvidia,pull = <2>; 524 nvidia,pull = <TEGRA_PIN_PULL_UP>;
494 nvidia,tristate = <0>; 525 nvidia,tristate = <TEGRA_PIN_DISABLE>;
495 nvidia,enable-input = <1>; 526 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
496 }; 527 };
497 gpio_w2_aud_pw2 { 528 gpio_w2_aud_pw2 {
498 nvidia,pins = "gpio_w2_aud_pw2"; 529 nvidia,pins = "gpio_w2_aud_pw2";
499 nvidia,function = "rsvd2"; 530 nvidia,function = "rsvd2";
500 nvidia,pull = <2>; 531 nvidia,pull = <TEGRA_PIN_PULL_UP>;
501 nvidia,tristate = <0>; 532 nvidia,tristate = <TEGRA_PIN_DISABLE>;
502 nvidia,enable-input = <1>; 533 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
503 }; 534 };
504 gpio_w3_aud_pw3 { 535 gpio_w3_aud_pw3 {
505 nvidia,pins = "gpio_w3_aud_pw3"; 536 nvidia,pins = "gpio_w3_aud_pw3";
506 nvidia,function = "spi6"; 537 nvidia,function = "spi6";
507 nvidia,pull = <2>; 538 nvidia,pull = <TEGRA_PIN_PULL_UP>;
508 nvidia,tristate = <0>; 539 nvidia,tristate = <TEGRA_PIN_DISABLE>;
509 nvidia,enable-input = <1>; 540 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
510 }; 541 };
511 gpio_x1_aud_px1 { 542 gpio_x1_aud_px1 {
512 nvidia,pins = "gpio_x1_aud_px1"; 543 nvidia,pins = "gpio_x1_aud_px1";
513 nvidia,function = "rsvd4"; 544 nvidia,function = "rsvd4";
514 nvidia,pull = <1>; 545 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
515 nvidia,tristate = <0>; 546 nvidia,tristate = <TEGRA_PIN_DISABLE>;
516 nvidia,enable-input = <1>; 547 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
517 }; 548 };
518 gpio_x3_aud_px3 { 549 gpio_x3_aud_px3 {
519 nvidia,pins = "gpio_x3_aud_px3"; 550 nvidia,pins = "gpio_x3_aud_px3";
520 nvidia,function = "rsvd4"; 551 nvidia,function = "rsvd4";
521 nvidia,pull = <2>; 552 nvidia,pull = <TEGRA_PIN_PULL_UP>;
522 nvidia,tristate = <0>; 553 nvidia,tristate = <TEGRA_PIN_DISABLE>;
523 nvidia,enable-input = <1>; 554 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
524 }; 555 };
525 dap3_fs_pp0 { 556 dap3_fs_pp0 {
526 nvidia,pins = "dap3_fs_pp0"; 557 nvidia,pins = "dap3_fs_pp0";
527 nvidia,function = "i2s2"; 558 nvidia,function = "i2s2";
528 nvidia,pull = <1>; 559 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
529 nvidia,tristate = <0>; 560 nvidia,tristate = <TEGRA_PIN_DISABLE>;
530 nvidia,enable-input = <0>; 561 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
531 }; 562 };
532 dap3_dout_pp2 { 563 dap3_dout_pp2 {
533 nvidia,pins = "dap3_dout_pp2"; 564 nvidia,pins = "dap3_dout_pp2";
534 nvidia,function = "i2s2"; 565 nvidia,function = "i2s2";
535 nvidia,pull = <1>; 566 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
536 nvidia,tristate = <0>; 567 nvidia,tristate = <TEGRA_PIN_DISABLE>;
537 nvidia,enable-input = <0>; 568 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
538 }; 569 };
539 pv1 { 570 pv1 {
540 nvidia,pins = "pv1"; 571 nvidia,pins = "pv1";
541 nvidia,function = "rsvd1"; 572 nvidia,function = "rsvd1";
542 nvidia,pull = <0>; 573 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
543 nvidia,tristate = <0>; 574 nvidia,tristate = <TEGRA_PIN_DISABLE>;
544 nvidia,enable-input = <1>; 575 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
545 }; 576 };
546 pbb3 { 577 pbb3 {
547 nvidia,pins = "pbb3", 578 nvidia,pins = "pbb3",
@@ -549,25 +580,25 @@
549 "pbb6", 580 "pbb6",
550 "pbb7"; 581 "pbb7";
551 nvidia,function = "rsvd4"; 582 nvidia,function = "rsvd4";
552 nvidia,pull = <1>; 583 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
553 nvidia,tristate = <0>; 584 nvidia,tristate = <TEGRA_PIN_DISABLE>;
554 nvidia,enable-input = <0>; 585 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
555 }; 586 };
556 pcc1 { 587 pcc1 {
557 nvidia,pins = "pcc1", 588 nvidia,pins = "pcc1",
558 "pcc2"; 589 "pcc2";
559 nvidia,function = "rsvd4"; 590 nvidia,function = "rsvd4";
560 nvidia,pull = <1>; 591 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
561 nvidia,tristate = <0>; 592 nvidia,tristate = <TEGRA_PIN_DISABLE>;
562 nvidia,enable-input = <1>; 593 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
563 }; 594 };
564 gmi_ad0_pg0 { 595 gmi_ad0_pg0 {
565 nvidia,pins = "gmi_ad0_pg0", 596 nvidia,pins = "gmi_ad0_pg0",
566 "gmi_ad1_pg1"; 597 "gmi_ad1_pg1";
567 nvidia,function = "gmi"; 598 nvidia,function = "gmi";
568 nvidia,pull = <0>; 599 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
569 nvidia,tristate = <0>; 600 nvidia,tristate = <TEGRA_PIN_DISABLE>;
570 nvidia,enable-input = <0>; 601 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
571 }; 602 };
572 gmi_ad10_ph2 { 603 gmi_ad10_ph2 {
573 nvidia,pins = "gmi_ad10_ph2", 604 nvidia,pins = "gmi_ad10_ph2",
@@ -576,17 +607,17 @@
576 "gmi_ad8_ph0", 607 "gmi_ad8_ph0",
577 "gmi_clk_pk1"; 608 "gmi_clk_pk1";
578 nvidia,function = "gmi"; 609 nvidia,function = "gmi";
579 nvidia,pull = <1>; 610 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
580 nvidia,tristate = <0>; 611 nvidia,tristate = <TEGRA_PIN_DISABLE>;
581 nvidia,enable-input = <0>; 612 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
582 }; 613 };
583 gmi_ad2_pg2 { 614 gmi_ad2_pg2 {
584 nvidia,pins = "gmi_ad2_pg2", 615 nvidia,pins = "gmi_ad2_pg2",
585 "gmi_ad3_pg3"; 616 "gmi_ad3_pg3";
586 nvidia,function = "gmi"; 617 nvidia,function = "gmi";
587 nvidia,pull = <0>; 618 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
588 nvidia,tristate = <0>; 619 nvidia,tristate = <TEGRA_PIN_DISABLE>;
589 nvidia,enable-input = <1>; 620 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
590 }; 621 };
591 gmi_adv_n_pk0 { 622 gmi_adv_n_pk0 {
592 nvidia,pins = "gmi_adv_n_pk0", 623 nvidia,pins = "gmi_adv_n_pk0",
@@ -598,39 +629,39 @@
598 "gmi_iordy_pi5", 629 "gmi_iordy_pi5",
599 "gmi_wp_n_pc7"; 630 "gmi_wp_n_pc7";
600 nvidia,function = "gmi"; 631 nvidia,function = "gmi";
601 nvidia,pull = <2>; 632 nvidia,pull = <TEGRA_PIN_PULL_UP>;
602 nvidia,tristate = <0>; 633 nvidia,tristate = <TEGRA_PIN_DISABLE>;
603 nvidia,enable-input = <1>; 634 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
604 }; 635 };
605 gmi_cs3_n_pk4 { 636 gmi_cs3_n_pk4 {
606 nvidia,pins = "gmi_cs3_n_pk4"; 637 nvidia,pins = "gmi_cs3_n_pk4";
607 nvidia,function = "gmi"; 638 nvidia,function = "gmi";
608 nvidia,pull = <2>; 639 nvidia,pull = <TEGRA_PIN_PULL_UP>;
609 nvidia,tristate = <0>; 640 nvidia,tristate = <TEGRA_PIN_DISABLE>;
610 nvidia,enable-input = <0>; 641 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
611 }; 642 };
612 clk2_req_pcc5 { 643 clk2_req_pcc5 {
613 nvidia,pins = "clk2_req_pcc5"; 644 nvidia,pins = "clk2_req_pcc5";
614 nvidia,function = "rsvd4"; 645 nvidia,function = "rsvd4";
615 nvidia,pull = <0>; 646 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
616 nvidia,tristate = <0>; 647 nvidia,tristate = <TEGRA_PIN_DISABLE>;
617 nvidia,enable-input = <0>; 648 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
618 }; 649 };
619 kb_col3_pq3 { 650 kb_col3_pq3 {
620 nvidia,pins = "kb_col3_pq3", 651 nvidia,pins = "kb_col3_pq3",
621 "kb_col6_pq6", 652 "kb_col6_pq6",
622 "kb_col7_pq7"; 653 "kb_col7_pq7";
623 nvidia,function = "kbc"; 654 nvidia,function = "kbc";
624 nvidia,pull = <2>; 655 nvidia,pull = <TEGRA_PIN_PULL_UP>;
625 nvidia,tristate = <0>; 656 nvidia,tristate = <TEGRA_PIN_DISABLE>;
626 nvidia,enable-input = <0>; 657 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
627 }; 658 };
628 kb_col5_pq5 { 659 kb_col5_pq5 {
629 nvidia,pins = "kb_col5_pq5"; 660 nvidia,pins = "kb_col5_pq5";
630 nvidia,function = "kbc"; 661 nvidia,function = "kbc";
631 nvidia,pull = <2>; 662 nvidia,pull = <TEGRA_PIN_PULL_UP>;
632 nvidia,tristate = <0>; 663 nvidia,tristate = <TEGRA_PIN_DISABLE>;
633 nvidia,enable-input = <1>; 664 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
634 }; 665 };
635 kb_row3_pr3 { 666 kb_row3_pr3 {
636 nvidia,pins = "kb_row3_pr3", 667 nvidia,pins = "kb_row3_pr3",
@@ -638,77 +669,77 @@
638 "kb_row6_pr6", 669 "kb_row6_pr6",
639 "kb_row8_ps0"; 670 "kb_row8_ps0";
640 nvidia,function = "kbc"; 671 nvidia,function = "kbc";
641 nvidia,pull = <1>; 672 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
642 nvidia,tristate = <0>; 673 nvidia,tristate = <TEGRA_PIN_DISABLE>;
643 nvidia,enable-input = <1>; 674 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
644 }; 675 };
645 clk3_req_pee1 { 676 clk3_req_pee1 {
646 nvidia,pins = "clk3_req_pee1"; 677 nvidia,pins = "clk3_req_pee1";
647 nvidia,function = "rsvd4"; 678 nvidia,function = "rsvd4";
648 nvidia,pull = <0>; 679 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
649 nvidia,tristate = <0>; 680 nvidia,tristate = <TEGRA_PIN_DISABLE>;
650 nvidia,enable-input = <0>; 681 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
651 }; 682 };
652 pu4 { 683 pu4 {
653 nvidia,pins = "pu4"; 684 nvidia,pins = "pu4";
654 nvidia,function = "displayb"; 685 nvidia,function = "displayb";
655 nvidia,pull = <0>; 686 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
656 nvidia,tristate = <0>; 687 nvidia,tristate = <TEGRA_PIN_DISABLE>;
657 nvidia,enable-input = <0>; 688 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
658 }; 689 };
659 pu5 { 690 pu5 {
660 nvidia,pins = "pu5", 691 nvidia,pins = "pu5",
661 "pu6"; 692 "pu6";
662 nvidia,function = "displayb"; 693 nvidia,function = "displayb";
663 nvidia,pull = <0>; 694 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
664 nvidia,tristate = <0>; 695 nvidia,tristate = <TEGRA_PIN_DISABLE>;
665 nvidia,enable-input = <1>; 696 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
666 }; 697 };
667 hdmi_int_pn7 { 698 hdmi_int_pn7 {
668 nvidia,pins = "hdmi_int_pn7"; 699 nvidia,pins = "hdmi_int_pn7";
669 nvidia,function = "rsvd1"; 700 nvidia,function = "rsvd1";
670 nvidia,pull = <1>; 701 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
671 nvidia,tristate = <0>; 702 nvidia,tristate = <TEGRA_PIN_DISABLE>;
672 nvidia,enable-input = <1>; 703 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
673 }; 704 };
674 clk1_req_pee2 { 705 clk1_req_pee2 {
675 nvidia,pins = "clk1_req_pee2", 706 nvidia,pins = "clk1_req_pee2",
676 "usb_vbus_en1_pn5"; 707 "usb_vbus_en1_pn5";
677 nvidia,function = "rsvd4"; 708 nvidia,function = "rsvd4";
678 nvidia,pull = <1>; 709 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
679 nvidia,tristate = <1>; 710 nvidia,tristate = <TEGRA_PIN_ENABLE>;
680 nvidia,enable-input = <0>; 711 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
681 }; 712 };
682 713
683 drive_sdio1 { 714 drive_sdio1 {
684 nvidia,pins = "drive_sdio1"; 715 nvidia,pins = "drive_sdio1";
685 nvidia,high-speed-mode = <1>; 716 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
686 nvidia,schmitt = <0>; 717 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
687 nvidia,low-power-mode = <3>; 718 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
688 nvidia,pull-down-strength = <36>; 719 nvidia,pull-down-strength = <36>;
689 nvidia,pull-up-strength = <20>; 720 nvidia,pull-up-strength = <20>;
690 nvidia,slew-rate-rising = <2>; 721 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>;
691 nvidia,slew-rate-falling = <2>; 722 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>;
692 }; 723 };
693 drive_sdio3 { 724 drive_sdio3 {
694 nvidia,pins = "drive_sdio3"; 725 nvidia,pins = "drive_sdio3";
695 nvidia,high-speed-mode = <1>; 726 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
696 nvidia,schmitt = <0>; 727 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
697 nvidia,low-power-mode = <3>; 728 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
698 nvidia,pull-down-strength = <22>; 729 nvidia,pull-down-strength = <22>;
699 nvidia,pull-up-strength = <36>; 730 nvidia,pull-up-strength = <36>;
700 nvidia,slew-rate-rising = <0>; 731 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
701 nvidia,slew-rate-falling = <0>; 732 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
702 }; 733 };
703 drive_gma { 734 drive_gma {
704 nvidia,pins = "drive_gma"; 735 nvidia,pins = "drive_gma";
705 nvidia,high-speed-mode = <1>; 736 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
706 nvidia,schmitt = <0>; 737 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
707 nvidia,low-power-mode = <3>; 738 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
708 nvidia,pull-down-strength = <2>; 739 nvidia,pull-down-strength = <2>;
709 nvidia,pull-up-strength = <1>; 740 nvidia,pull-up-strength = <1>;
710 nvidia,slew-rate-rising = <0>; 741 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
711 nvidia,slew-rate-falling = <0>; 742 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
712 nvidia,drive-type = <1>; 743 nvidia,drive-type = <1>;
713 }; 744 };
714 }; 745 };
@@ -718,11 +749,15 @@
718 status = "okay"; 749 status = "okay";
719 }; 750 };
720 751
752 pwm@7000a000 {
753 status = "okay";
754 };
755
721 i2c@7000c000 { 756 i2c@7000c000 {
722 status = "okay"; 757 status = "okay";
723 clock-frequency = <100000>; 758 clock-frequency = <100000>;
724 759
725 battery: smart-battery { 760 battery: smart-battery@b {
726 compatible = "ti,bq20z45", "sbs,sbs-battery"; 761 compatible = "ti,bq20z45", "sbs,sbs-battery";
727 reg = <0xb>; 762 reg = <0xb>;
728 battery-name = "battery"; 763 battery-name = "battery";
@@ -731,7 +766,7 @@
731 power-supplies = <&charger>; 766 power-supplies = <&charger>;
732 }; 767 };
733 768
734 rt5640: rt5640 { 769 rt5640: rt5640@1c {
735 compatible = "realtek,rt5640"; 770 compatible = "realtek,rt5640";
736 reg = <0x1c>; 771 reg = <0x1c>;
737 interrupt-parent = <&gpio>; 772 interrupt-parent = <&gpio>;
@@ -749,11 +784,15 @@
749 }; 784 };
750 }; 785 };
751 786
787 hdmi_ddc: i2c@7000c700 {
788 status = "okay";
789 };
790
752 i2c@7000d000 { 791 i2c@7000d000 {
753 status = "okay"; 792 status = "okay";
754 clock-frequency = <400000>; 793 clock-frequency = <400000>;
755 794
756 tps51632 { 795 tps51632@43 {
757 compatible = "ti,tps51632"; 796 compatible = "ti,tps51632";
758 reg = <0x43>; 797 reg = <0x43>;
759 regulator-name = "vdd-cpu"; 798 regulator-name = "vdd-cpu";
@@ -763,7 +802,7 @@
763 regulator-always-on; 802 regulator-always-on;
764 }; 803 };
765 804
766 tps65090 { 805 tps65090@48 {
767 compatible = "ti,tps65090"; 806 compatible = "ti,tps65090";
768 reg = <0x48>; 807 reg = <0x48>;
769 interrupt-parent = <&gpio>; 808 interrupt-parent = <&gpio>;
@@ -806,7 +845,7 @@
806 regulator-boot-on; 845 regulator-boot-on;
807 }; 846 };
808 847
809 fet1 { 848 vdd_bl_reg: fet1 {
810 regulator-name = "vdd-lcd-bl"; 849 regulator-name = "vdd-lcd-bl";
811 }; 850 };
812 851
@@ -814,7 +853,7 @@
814 regulator-name = "vdd-modem-3v3"; 853 regulator-name = "vdd-modem-3v3";
815 }; 854 };
816 855
817 fet4 { 856 avdd_lcd_reg: fet4 {
818 regulator-name = "avdd-lcd"; 857 regulator-name = "avdd-lcd";
819 }; 858 };
820 859
@@ -846,7 +885,7 @@
846 }; 885 };
847 }; 886 };
848 887
849 palmas: tps65913 { 888 palmas: tps65913@58 {
850 compatible = "ti,palmas"; 889 compatible = "ti,palmas";
851 reg = <0x58>; 890 reg = <0x58>;
852 interrupts = <0 86 IRQ_TYPE_LEVEL_LOW>; 891 interrupts = <0 86 IRQ_TYPE_LEVEL_LOW>;
@@ -1046,7 +1085,7 @@
1046 }; 1085 };
1047 }; 1086 };
1048 1087
1049 pmc { 1088 pmc@7000e400 {
1050 nvidia,invert-interrupt; 1089 nvidia,invert-interrupt;
1051 nvidia,suspend-mode = <1>; 1090 nvidia,suspend-mode = <1>;
1052 nvidia,cpu-pwr-good-time = <500>; 1091 nvidia,cpu-pwr-good-time = <500>;
@@ -1057,7 +1096,7 @@
1057 nvidia,sys-clock-req-active-high; 1096 nvidia,sys-clock-req-active-high;
1058 }; 1097 };
1059 1098
1060 ahub { 1099 ahub@70080000 {
1061 i2s@70080400 { 1100 i2s@70080400 {
1062 status = "okay"; 1101 status = "okay";
1063 }; 1102 };
@@ -1084,12 +1123,23 @@
1084 vbus-supply = <&usb3_vbus_reg>; 1123 vbus-supply = <&usb3_vbus_reg>;
1085 }; 1124 };
1086 1125
1126 backlight: backlight {
1127 compatible = "pwm-backlight";
1128
1129 enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
1130 power-supply = <&vdd_bl_reg>;
1131 pwms = <&pwm 1 1000000>;
1132
1133 brightness-levels = <0 4 8 16 32 64 128 255>;
1134 default-brightness-level = <6>;
1135 };
1136
1087 clocks { 1137 clocks {
1088 compatible = "simple-bus"; 1138 compatible = "simple-bus";
1089 #address-cells = <1>; 1139 #address-cells = <1>;
1090 #size-cells = <0>; 1140 #size-cells = <0>;
1091 1141
1092 clk32k_in: clock { 1142 clk32k_in: clock@0 {
1093 compatible = "fixed-clock"; 1143 compatible = "fixed-clock";
1094 reg=<0>; 1144 reg=<0>;
1095 #clock-cells = <0>; 1145 #clock-cells = <0>;
@@ -1150,16 +1200,6 @@
1150 gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>; 1200 gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>;
1151 }; 1201 };
1152 1202
1153 lcd_bl_en_reg: regulator@2 {
1154 compatible = "regulator-fixed";
1155 reg = <2>;
1156 regulator-name = "lcd_bl_en";
1157 regulator-min-microvolt = <5000000>;
1158 regulator-max-microvolt = <5000000>;
1159 enable-active-high;
1160 gpio = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
1161 };
1162
1163 usb1_vbus_reg: regulator@3 { 1203 usb1_vbus_reg: regulator@3 {
1164 compatible = "regulator-fixed"; 1204 compatible = "regulator-fixed";
1165 reg = <3>; 1205 reg = <3>;
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 8d42787c8ff1..389e987ec281 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -1,5 +1,6 @@
1#include <dt-bindings/clock/tegra114-car.h> 1#include <dt-bindings/clock/tegra114-car.h>
2#include <dt-bindings/gpio/tegra-gpio.h> 2#include <dt-bindings/gpio/tegra-gpio.h>
3#include <dt-bindings/pinctrl/pinctrl-tegra.h>
3#include <dt-bindings/interrupt-controller/arm-gic.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h>
4 5
5#include "skeleton.dtsi" 6#include "skeleton.dtsi"
@@ -15,7 +16,113 @@
15 serial3 = &uartd; 16 serial3 = &uartd;
16 }; 17 };
17 18
18 gic: interrupt-controller { 19 host1x@50000000 {
20 compatible = "nvidia,tegra114-host1x", "simple-bus";
21 reg = <0x50000000 0x00028000>;
22 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
23 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
24 clocks = <&tegra_car TEGRA114_CLK_HOST1X>;
25 resets = <&tegra_car 28>;
26 reset-names = "host1x";
27
28 #address-cells = <1>;
29 #size-cells = <1>;
30
31 ranges = <0x54000000 0x54000000 0x01000000>;
32
33 gr2d@54140000 {
34 compatible = "nvidia,tegra114-gr2d", "nvidia,tegra20-gr2d";
35 reg = <0x54140000 0x00040000>;
36 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
37 clocks = <&tegra_car TEGRA114_CLK_GR2D>;
38 resets = <&tegra_car 21>;
39 reset-names = "2d";
40 };
41
42 gr3d@54180000 {
43 compatible = "nvidia,tegra114-gr3d", "nvidia,tegra20-gr3d";
44 reg = <0x54180000 0x00040000>;
45 clocks = <&tegra_car TEGRA114_CLK_GR3D>;
46 resets = <&tegra_car 24>;
47 reset-names = "3d";
48 };
49
50 dc@54200000 {
51 compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc";
52 reg = <0x54200000 0x00040000>;
53 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
54 clocks = <&tegra_car TEGRA114_CLK_DISP1>,
55 <&tegra_car TEGRA114_CLK_PLL_P>;
56 clock-names = "dc", "parent";
57 resets = <&tegra_car 27>;
58 reset-names = "dc";
59
60 rgb {
61 status = "disabled";
62 };
63 };
64
65 dc@54240000 {
66 compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc";
67 reg = <0x54240000 0x00040000>;
68 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
69 clocks = <&tegra_car TEGRA114_CLK_DISP2>,
70 <&tegra_car TEGRA114_CLK_PLL_P>;
71 clock-names = "dc", "parent";
72 resets = <&tegra_car 26>;
73 reset-names = "dc";
74
75 rgb {
76 status = "disabled";
77 };
78 };
79
80 hdmi@54280000 {
81 compatible = "nvidia,tegra114-hdmi";
82 reg = <0x54280000 0x00040000>;
83 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
84 clocks = <&tegra_car TEGRA114_CLK_HDMI>,
85 <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>;
86 clock-names = "hdmi", "parent";
87 resets = <&tegra_car 51>;
88 reset-names = "hdmi";
89 status = "disabled";
90 };
91
92 dsi@54300000 {
93 compatible = "nvidia,tegra114-dsi";
94 reg = <0x54300000 0x00040000>;
95 clocks = <&tegra_car TEGRA114_CLK_DSIA>,
96 <&tegra_car TEGRA114_CLK_DSIALP>,
97 <&tegra_car TEGRA114_CLK_PLL_D_OUT0>;
98 clock-names = "dsi", "lp", "parent";
99 resets = <&tegra_car 48>;
100 reset-names = "dsi";
101 nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */
102 status = "disabled";
103
104 #address-cells = <1>;
105 #size-cells = <0>;
106 };
107
108 dsi@54400000 {
109 compatible = "nvidia,tegra114-dsi";
110 reg = <0x54400000 0x00040000>;
111 clocks = <&tegra_car TEGRA114_CLK_DSIB>,
112 <&tegra_car TEGRA114_CLK_DSIBLP>,
113 <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>;
114 clock-names = "dsi", "lp", "parent";
115 resets = <&tegra_car 82>;
116 reset-names = "dsi";
117 nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */
118 status = "disabled";
119
120 #address-cells = <1>;
121 #size-cells = <0>;
122 };
123 };
124
125 gic: interrupt-controller@50041000 {
19 compatible = "arm,cortex-a15-gic"; 126 compatible = "arm,cortex-a15-gic";
20 #interrupt-cells = <3>; 127 #interrupt-cells = <3>;
21 interrupt-controller; 128 interrupt-controller;
@@ -39,13 +146,14 @@
39 clocks = <&tegra_car TEGRA114_CLK_TIMER>; 146 clocks = <&tegra_car TEGRA114_CLK_TIMER>;
40 }; 147 };
41 148
42 tegra_car: clock { 149 tegra_car: clock@60006000 {
43 compatible = "nvidia,tegra114-car"; 150 compatible = "nvidia,tegra114-car";
44 reg = <0x60006000 0x1000>; 151 reg = <0x60006000 0x1000>;
45 #clock-cells = <1>; 152 #clock-cells = <1>;
153 #reset-cells = <1>;
46 }; 154 };
47 155
48 apbdma: dma { 156 apbdma: dma@6000a000 {
49 compatible = "nvidia,tegra114-apbdma"; 157 compatible = "nvidia,tegra114-apbdma";
50 reg = <0x6000a000 0x1400>; 158 reg = <0x6000a000 0x1400>;
51 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 159 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
@@ -81,14 +189,17 @@
81 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
82 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 190 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
83 clocks = <&tegra_car TEGRA114_CLK_APBDMA>; 191 clocks = <&tegra_car TEGRA114_CLK_APBDMA>;
192 resets = <&tegra_car 34>;
193 reset-names = "dma";
194 #dma-cells = <1>;
84 }; 195 };
85 196
86 ahb: ahb { 197 ahb: ahb@6000c004 {
87 compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb"; 198 compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
88 reg = <0x6000c004 0x14c>; 199 reg = <0x6000c004 0x14c>;
89 }; 200 };
90 201
91 gpio: gpio { 202 gpio: gpio@6000d000 {
92 compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio"; 203 compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
93 reg = <0x6000d000 0x1000>; 204 reg = <0x6000d000 0x1000>;
94 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 205 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
@@ -105,7 +216,7 @@
105 interrupt-controller; 216 interrupt-controller;
106 }; 217 };
107 218
108 pinmux: pinmux { 219 pinmux: pinmux@70000868 {
109 compatible = "nvidia,tegra114-pinmux"; 220 compatible = "nvidia,tegra114-pinmux";
110 reg = <0x70000868 0x148 /* Pad control registers */ 221 reg = <0x70000868 0x148 /* Pad control registers */
111 0x70003000 0x40c>; /* Mux registers */ 222 0x70003000 0x40c>; /* Mux registers */
@@ -124,9 +235,12 @@
124 reg = <0x70006000 0x40>; 235 reg = <0x70006000 0x40>;
125 reg-shift = <2>; 236 reg-shift = <2>;
126 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 237 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
127 nvidia,dma-request-selector = <&apbdma 8>;
128 status = "disabled";
129 clocks = <&tegra_car TEGRA114_CLK_UARTA>; 238 clocks = <&tegra_car TEGRA114_CLK_UARTA>;
239 resets = <&tegra_car 6>;
240 reset-names = "serial";
241 dmas = <&apbdma 8>, <&apbdma 8>;
242 dma-names = "rx", "tx";
243 status = "disabled";
130 }; 244 };
131 245
132 uartb: serial@70006040 { 246 uartb: serial@70006040 {
@@ -134,9 +248,12 @@
134 reg = <0x70006040 0x40>; 248 reg = <0x70006040 0x40>;
135 reg-shift = <2>; 249 reg-shift = <2>;
136 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 250 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
137 nvidia,dma-request-selector = <&apbdma 9>;
138 status = "disabled";
139 clocks = <&tegra_car TEGRA114_CLK_UARTB>; 251 clocks = <&tegra_car TEGRA114_CLK_UARTB>;
252 resets = <&tegra_car 7>;
253 reset-names = "serial";
254 dmas = <&apbdma 9>, <&apbdma 9>;
255 dma-names = "rx", "tx";
256 status = "disabled";
140 }; 257 };
141 258
142 uartc: serial@70006200 { 259 uartc: serial@70006200 {
@@ -144,9 +261,12 @@
144 reg = <0x70006200 0x100>; 261 reg = <0x70006200 0x100>;
145 reg-shift = <2>; 262 reg-shift = <2>;
146 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 263 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
147 nvidia,dma-request-selector = <&apbdma 10>;
148 status = "disabled";
149 clocks = <&tegra_car TEGRA114_CLK_UARTC>; 264 clocks = <&tegra_car TEGRA114_CLK_UARTC>;
265 resets = <&tegra_car 55>;
266 reset-names = "serial";
267 dmas = <&apbdma 10>, <&apbdma 10>;
268 dma-names = "rx", "tx";
269 status = "disabled";
150 }; 270 };
151 271
152 uartd: serial@70006300 { 272 uartd: serial@70006300 {
@@ -154,16 +274,21 @@
154 reg = <0x70006300 0x100>; 274 reg = <0x70006300 0x100>;
155 reg-shift = <2>; 275 reg-shift = <2>;
156 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 276 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
157 nvidia,dma-request-selector = <&apbdma 19>;
158 status = "disabled";
159 clocks = <&tegra_car TEGRA114_CLK_UARTD>; 277 clocks = <&tegra_car TEGRA114_CLK_UARTD>;
278 resets = <&tegra_car 65>;
279 reset-names = "serial";
280 dmas = <&apbdma 19>, <&apbdma 19>;
281 dma-names = "rx", "tx";
282 status = "disabled";
160 }; 283 };
161 284
162 pwm: pwm { 285 pwm: pwm@7000a000 {
163 compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm"; 286 compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
164 reg = <0x7000a000 0x100>; 287 reg = <0x7000a000 0x100>;
165 #pwm-cells = <2>; 288 #pwm-cells = <2>;
166 clocks = <&tegra_car TEGRA114_CLK_PWM>; 289 clocks = <&tegra_car TEGRA114_CLK_PWM>;
290 resets = <&tegra_car 17>;
291 reset-names = "pwm";
167 status = "disabled"; 292 status = "disabled";
168 }; 293 };
169 294
@@ -175,6 +300,10 @@
175 #size-cells = <0>; 300 #size-cells = <0>;
176 clocks = <&tegra_car TEGRA114_CLK_I2C1>; 301 clocks = <&tegra_car TEGRA114_CLK_I2C1>;
177 clock-names = "div-clk"; 302 clock-names = "div-clk";
303 resets = <&tegra_car 12>;
304 reset-names = "i2c";
305 dmas = <&apbdma 21>, <&apbdma 21>;
306 dma-names = "rx", "tx";
178 status = "disabled"; 307 status = "disabled";
179 }; 308 };
180 309
@@ -186,6 +315,10 @@
186 #size-cells = <0>; 315 #size-cells = <0>;
187 clocks = <&tegra_car TEGRA114_CLK_I2C2>; 316 clocks = <&tegra_car TEGRA114_CLK_I2C2>;
188 clock-names = "div-clk"; 317 clock-names = "div-clk";
318 resets = <&tegra_car 54>;
319 reset-names = "i2c";
320 dmas = <&apbdma 22>, <&apbdma 22>;
321 dma-names = "rx", "tx";
189 status = "disabled"; 322 status = "disabled";
190 }; 323 };
191 324
@@ -197,6 +330,10 @@
197 #size-cells = <0>; 330 #size-cells = <0>;
198 clocks = <&tegra_car TEGRA114_CLK_I2C3>; 331 clocks = <&tegra_car TEGRA114_CLK_I2C3>;
199 clock-names = "div-clk"; 332 clock-names = "div-clk";
333 resets = <&tegra_car 67>;
334 reset-names = "i2c";
335 dmas = <&apbdma 23>, <&apbdma 23>;
336 dma-names = "rx", "tx";
200 status = "disabled"; 337 status = "disabled";
201 }; 338 };
202 339
@@ -208,6 +345,10 @@
208 #size-cells = <0>; 345 #size-cells = <0>;
209 clocks = <&tegra_car TEGRA114_CLK_I2C4>; 346 clocks = <&tegra_car TEGRA114_CLK_I2C4>;
210 clock-names = "div-clk"; 347 clock-names = "div-clk";
348 resets = <&tegra_car 103>;
349 reset-names = "i2c";
350 dmas = <&apbdma 26>, <&apbdma 26>;
351 dma-names = "rx", "tx";
211 status = "disabled"; 352 status = "disabled";
212 }; 353 };
213 354
@@ -219,6 +360,10 @@
219 #size-cells = <0>; 360 #size-cells = <0>;
220 clocks = <&tegra_car TEGRA114_CLK_I2C5>; 361 clocks = <&tegra_car TEGRA114_CLK_I2C5>;
221 clock-names = "div-clk"; 362 clock-names = "div-clk";
363 resets = <&tegra_car 47>;
364 reset-names = "i2c";
365 dmas = <&apbdma 24>, <&apbdma 24>;
366 dma-names = "rx", "tx";
222 status = "disabled"; 367 status = "disabled";
223 }; 368 };
224 369
@@ -226,11 +371,14 @@
226 compatible = "nvidia,tegra114-spi"; 371 compatible = "nvidia,tegra114-spi";
227 reg = <0x7000d400 0x200>; 372 reg = <0x7000d400 0x200>;
228 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 373 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
229 nvidia,dma-request-selector = <&apbdma 15>;
230 #address-cells = <1>; 374 #address-cells = <1>;
231 #size-cells = <0>; 375 #size-cells = <0>;
232 clocks = <&tegra_car TEGRA114_CLK_SBC1>; 376 clocks = <&tegra_car TEGRA114_CLK_SBC1>;
233 clock-names = "spi"; 377 clock-names = "spi";
378 resets = <&tegra_car 41>;
379 reset-names = "spi";
380 dmas = <&apbdma 15>, <&apbdma 15>;
381 dma-names = "rx", "tx";
234 status = "disabled"; 382 status = "disabled";
235 }; 383 };
236 384
@@ -238,11 +386,14 @@
238 compatible = "nvidia,tegra114-spi"; 386 compatible = "nvidia,tegra114-spi";
239 reg = <0x7000d600 0x200>; 387 reg = <0x7000d600 0x200>;
240 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 388 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
241 nvidia,dma-request-selector = <&apbdma 16>;
242 #address-cells = <1>; 389 #address-cells = <1>;
243 #size-cells = <0>; 390 #size-cells = <0>;
244 clocks = <&tegra_car TEGRA114_CLK_SBC2>; 391 clocks = <&tegra_car TEGRA114_CLK_SBC2>;
245 clock-names = "spi"; 392 clock-names = "spi";
393 resets = <&tegra_car 44>;
394 reset-names = "spi";
395 dmas = <&apbdma 16>, <&apbdma 16>;
396 dma-names = "rx", "tx";
246 status = "disabled"; 397 status = "disabled";
247 }; 398 };
248 399
@@ -250,11 +401,14 @@
250 compatible = "nvidia,tegra114-spi"; 401 compatible = "nvidia,tegra114-spi";
251 reg = <0x7000d800 0x200>; 402 reg = <0x7000d800 0x200>;
252 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 403 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
253 nvidia,dma-request-selector = <&apbdma 17>;
254 #address-cells = <1>; 404 #address-cells = <1>;
255 #size-cells = <0>; 405 #size-cells = <0>;
256 clocks = <&tegra_car TEGRA114_CLK_SBC3>; 406 clocks = <&tegra_car TEGRA114_CLK_SBC3>;
257 clock-names = "spi"; 407 clock-names = "spi";
408 resets = <&tegra_car 46>;
409 reset-names = "spi";
410 dmas = <&apbdma 17>, <&apbdma 17>;
411 dma-names = "rx", "tx";
258 status = "disabled"; 412 status = "disabled";
259 }; 413 };
260 414
@@ -262,11 +416,14 @@
262 compatible = "nvidia,tegra114-spi"; 416 compatible = "nvidia,tegra114-spi";
263 reg = <0x7000da00 0x200>; 417 reg = <0x7000da00 0x200>;
264 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 418 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
265 nvidia,dma-request-selector = <&apbdma 18>;
266 #address-cells = <1>; 419 #address-cells = <1>;
267 #size-cells = <0>; 420 #size-cells = <0>;
268 clocks = <&tegra_car TEGRA114_CLK_SBC4>; 421 clocks = <&tegra_car TEGRA114_CLK_SBC4>;
269 clock-names = "spi"; 422 clock-names = "spi";
423 resets = <&tegra_car 68>;
424 reset-names = "spi";
425 dmas = <&apbdma 18>, <&apbdma 18>;
426 dma-names = "rx", "tx";
270 status = "disabled"; 427 status = "disabled";
271 }; 428 };
272 429
@@ -274,11 +431,14 @@
274 compatible = "nvidia,tegra114-spi"; 431 compatible = "nvidia,tegra114-spi";
275 reg = <0x7000dc00 0x200>; 432 reg = <0x7000dc00 0x200>;
276 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 433 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
277 nvidia,dma-request-selector = <&apbdma 27>;
278 #address-cells = <1>; 434 #address-cells = <1>;
279 #size-cells = <0>; 435 #size-cells = <0>;
280 clocks = <&tegra_car TEGRA114_CLK_SBC5>; 436 clocks = <&tegra_car TEGRA114_CLK_SBC5>;
281 clock-names = "spi"; 437 clock-names = "spi";
438 resets = <&tegra_car 104>;
439 reset-names = "spi";
440 dmas = <&apbdma 27>, <&apbdma 27>;
441 dma-names = "rx", "tx";
282 status = "disabled"; 442 status = "disabled";
283 }; 443 };
284 444
@@ -286,37 +446,42 @@
286 compatible = "nvidia,tegra114-spi"; 446 compatible = "nvidia,tegra114-spi";
287 reg = <0x7000de00 0x200>; 447 reg = <0x7000de00 0x200>;
288 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 448 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
289 nvidia,dma-request-selector = <&apbdma 28>;
290 #address-cells = <1>; 449 #address-cells = <1>;
291 #size-cells = <0>; 450 #size-cells = <0>;
292 clocks = <&tegra_car TEGRA114_CLK_SBC6>; 451 clocks = <&tegra_car TEGRA114_CLK_SBC6>;
293 clock-names = "spi"; 452 clock-names = "spi";
453 resets = <&tegra_car 105>;
454 reset-names = "spi";
455 dmas = <&apbdma 28>, <&apbdma 28>;
456 dma-names = "rx", "tx";
294 status = "disabled"; 457 status = "disabled";
295 }; 458 };
296 459
297 rtc { 460 rtc@7000e000 {
298 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc"; 461 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
299 reg = <0x7000e000 0x100>; 462 reg = <0x7000e000 0x100>;
300 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 463 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
301 clocks = <&tegra_car TEGRA114_CLK_RTC>; 464 clocks = <&tegra_car TEGRA114_CLK_RTC>;
302 }; 465 };
303 466
304 kbc { 467 kbc@7000e200 {
305 compatible = "nvidia,tegra114-kbc"; 468 compatible = "nvidia,tegra114-kbc";
306 reg = <0x7000e200 0x100>; 469 reg = <0x7000e200 0x100>;
307 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 470 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
308 clocks = <&tegra_car TEGRA114_CLK_KBC>; 471 clocks = <&tegra_car TEGRA114_CLK_KBC>;
472 resets = <&tegra_car 36>;
473 reset-names = "kbc";
309 status = "disabled"; 474 status = "disabled";
310 }; 475 };
311 476
312 pmc { 477 pmc@7000e400 {
313 compatible = "nvidia,tegra114-pmc"; 478 compatible = "nvidia,tegra114-pmc";
314 reg = <0x7000e400 0x400>; 479 reg = <0x7000e400 0x400>;
315 clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>; 480 clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>;
316 clock-names = "pclk", "clk32k_in"; 481 clock-names = "pclk", "clk32k_in";
317 }; 482 };
318 483
319 iommu { 484 iommu@70019010 {
320 compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu"; 485 compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu";
321 reg = <0x70019010 0x02c 486 reg = <0x70019010 0x02c
322 0x700191f0 0x010 487 0x700191f0 0x010
@@ -327,32 +492,45 @@
327 nvidia,ahb = <&ahb>; 492 nvidia,ahb = <&ahb>;
328 }; 493 };
329 494
330 ahub { 495 ahub@70080000 {
331 compatible = "nvidia,tegra114-ahub"; 496 compatible = "nvidia,tegra114-ahub";
332 reg = <0x70080000 0x200>, 497 reg = <0x70080000 0x200>,
333 <0x70080200 0x100>, 498 <0x70080200 0x100>,
334 <0x70081000 0x200>; 499 <0x70081000 0x200>;
335 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 500 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
336 nvidia,dma-request-selector = <&apbdma 1>, <&apbdma 2>,
337 <&apbdma 3>, <&apbdma 4>, <&apbdma 6>, <&apbdma 7>,
338 <&apbdma 12>, <&apbdma 13>, <&apbdma 14>,
339 <&apbdma 29>;
340 clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>, 501 clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>,
341 <&tegra_car TEGRA114_CLK_APBIF>, 502 <&tegra_car TEGRA114_CLK_APBIF>;
342 <&tegra_car TEGRA114_CLK_I2S0>, 503 clock-names = "d_audio", "apbif";
343 <&tegra_car TEGRA114_CLK_I2S1>, 504 resets = <&tegra_car 106>, /* d_audio */
344 <&tegra_car TEGRA114_CLK_I2S2>, 505 <&tegra_car 107>, /* apbif */
345 <&tegra_car TEGRA114_CLK_I2S3>, 506 <&tegra_car 30>, /* i2s0 */
346 <&tegra_car TEGRA114_CLK_I2S4>, 507 <&tegra_car 11>, /* i2s1 */
347 <&tegra_car TEGRA114_CLK_DAM0>, 508 <&tegra_car 18>, /* i2s2 */
348 <&tegra_car TEGRA114_CLK_DAM1>, 509 <&tegra_car 101>, /* i2s3 */
349 <&tegra_car TEGRA114_CLK_DAM2>, 510 <&tegra_car 102>, /* i2s4 */
350 <&tegra_car TEGRA114_CLK_SPDIF_IN>, 511 <&tegra_car 108>, /* dam0 */
351 <&tegra_car TEGRA114_CLK_AMX>, 512 <&tegra_car 109>, /* dam1 */
352 <&tegra_car TEGRA114_CLK_ADX>; 513 <&tegra_car 110>, /* dam2 */
353 clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", 514 <&tegra_car 10>, /* spdif */
515 <&tegra_car 153>, /* amx */
516 <&tegra_car 154>; /* adx */
517 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
354 "i2s3", "i2s4", "dam0", "dam1", "dam2", 518 "i2s3", "i2s4", "dam0", "dam1", "dam2",
355 "spdif_in", "amx", "adx"; 519 "spdif", "amx", "adx";
520 dmas = <&apbdma 1>, <&apbdma 1>,
521 <&apbdma 2>, <&apbdma 2>,
522 <&apbdma 3>, <&apbdma 3>,
523 <&apbdma 4>, <&apbdma 4>,
524 <&apbdma 6>, <&apbdma 6>,
525 <&apbdma 7>, <&apbdma 7>,
526 <&apbdma 12>, <&apbdma 12>,
527 <&apbdma 13>, <&apbdma 13>,
528 <&apbdma 14>, <&apbdma 14>,
529 <&apbdma 29>, <&apbdma 29>;
530 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
531 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
532 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
533 "rx9", "tx9";
356 ranges; 534 ranges;
357 #address-cells = <1>; 535 #address-cells = <1>;
358 #size-cells = <1>; 536 #size-cells = <1>;
@@ -362,6 +540,8 @@
362 reg = <0x70080300 0x100>; 540 reg = <0x70080300 0x100>;
363 nvidia,ahub-cif-ids = <4 4>; 541 nvidia,ahub-cif-ids = <4 4>;
364 clocks = <&tegra_car TEGRA114_CLK_I2S0>; 542 clocks = <&tegra_car TEGRA114_CLK_I2S0>;
543 resets = <&tegra_car 30>;
544 reset-names = "i2s";
365 status = "disabled"; 545 status = "disabled";
366 }; 546 };
367 547
@@ -370,6 +550,8 @@
370 reg = <0x70080400 0x100>; 550 reg = <0x70080400 0x100>;
371 nvidia,ahub-cif-ids = <5 5>; 551 nvidia,ahub-cif-ids = <5 5>;
372 clocks = <&tegra_car TEGRA114_CLK_I2S1>; 552 clocks = <&tegra_car TEGRA114_CLK_I2S1>;
553 resets = <&tegra_car 11>;
554 reset-names = "i2s";
373 status = "disabled"; 555 status = "disabled";
374 }; 556 };
375 557
@@ -378,6 +560,8 @@
378 reg = <0x70080500 0x100>; 560 reg = <0x70080500 0x100>;
379 nvidia,ahub-cif-ids = <6 6>; 561 nvidia,ahub-cif-ids = <6 6>;
380 clocks = <&tegra_car TEGRA114_CLK_I2S2>; 562 clocks = <&tegra_car TEGRA114_CLK_I2S2>;
563 resets = <&tegra_car 18>;
564 reset-names = "i2s";
381 status = "disabled"; 565 status = "disabled";
382 }; 566 };
383 567
@@ -386,6 +570,8 @@
386 reg = <0x70080600 0x100>; 570 reg = <0x70080600 0x100>;
387 nvidia,ahub-cif-ids = <7 7>; 571 nvidia,ahub-cif-ids = <7 7>;
388 clocks = <&tegra_car TEGRA114_CLK_I2S3>; 572 clocks = <&tegra_car TEGRA114_CLK_I2S3>;
573 resets = <&tegra_car 101>;
574 reset-names = "i2s";
389 status = "disabled"; 575 status = "disabled";
390 }; 576 };
391 577
@@ -394,15 +580,26 @@
394 reg = <0x70080700 0x100>; 580 reg = <0x70080700 0x100>;
395 nvidia,ahub-cif-ids = <8 8>; 581 nvidia,ahub-cif-ids = <8 8>;
396 clocks = <&tegra_car TEGRA114_CLK_I2S4>; 582 clocks = <&tegra_car TEGRA114_CLK_I2S4>;
583 resets = <&tegra_car 102>;
584 reset-names = "i2s";
397 status = "disabled"; 585 status = "disabled";
398 }; 586 };
399 }; 587 };
400 588
589 mipi: mipi@700e3000 {
590 compatible = "nvidia,tegra114-mipi";
591 reg = <0x700e3000 0x100>;
592 clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>;
593 #nvidia,mipi-calibrate-cells = <1>;
594 };
595
401 sdhci@78000000 { 596 sdhci@78000000 {
402 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; 597 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
403 reg = <0x78000000 0x200>; 598 reg = <0x78000000 0x200>;
404 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 599 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
405 clocks = <&tegra_car TEGRA114_CLK_SDMMC1>; 600 clocks = <&tegra_car TEGRA114_CLK_SDMMC1>;
601 resets = <&tegra_car 14>;
602 reset-names = "sdhci";
406 status = "disable"; 603 status = "disable";
407 }; 604 };
408 605
@@ -411,6 +608,8 @@
411 reg = <0x78000200 0x200>; 608 reg = <0x78000200 0x200>;
412 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 609 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
413 clocks = <&tegra_car TEGRA114_CLK_SDMMC2>; 610 clocks = <&tegra_car TEGRA114_CLK_SDMMC2>;
611 resets = <&tegra_car 9>;
612 reset-names = "sdhci";
414 status = "disable"; 613 status = "disable";
415 }; 614 };
416 615
@@ -419,6 +618,8 @@
419 reg = <0x78000400 0x200>; 618 reg = <0x78000400 0x200>;
420 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 619 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
421 clocks = <&tegra_car TEGRA114_CLK_SDMMC3>; 620 clocks = <&tegra_car TEGRA114_CLK_SDMMC3>;
621 resets = <&tegra_car 69>;
622 reset-names = "sdhci";
422 status = "disable"; 623 status = "disable";
423 }; 624 };
424 625
@@ -427,6 +628,8 @@
427 reg = <0x78000600 0x200>; 628 reg = <0x78000600 0x200>;
428 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 629 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
429 clocks = <&tegra_car TEGRA114_CLK_SDMMC4>; 630 clocks = <&tegra_car TEGRA114_CLK_SDMMC4>;
631 resets = <&tegra_car 15>;
632 reset-names = "sdhci";
430 status = "disable"; 633 status = "disable";
431 }; 634 };
432 635
@@ -436,6 +639,8 @@
436 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 639 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
437 phy_type = "utmi"; 640 phy_type = "utmi";
438 clocks = <&tegra_car TEGRA114_CLK_USBD>; 641 clocks = <&tegra_car TEGRA114_CLK_USBD>;
642 resets = <&tegra_car 22>;
643 reset-names = "usb";
439 nvidia,phy = <&phy1>; 644 nvidia,phy = <&phy1>;
440 status = "disabled"; 645 status = "disabled";
441 }; 646 };
@@ -467,6 +672,8 @@
467 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 672 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
468 phy_type = "utmi"; 673 phy_type = "utmi";
469 clocks = <&tegra_car TEGRA114_CLK_USB3>; 674 clocks = <&tegra_car TEGRA114_CLK_USB3>;
675 resets = <&tegra_car 59>;
676 reset-names = "usb";
470 nvidia,phy = <&phy3>; 677 nvidia,phy = <&phy3>;
471 status = "disabled"; 678 status = "disabled";
472 }; 679 };
diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts
index 431d67a2b413..c6dcef513e5d 100644
--- a/arch/arm/boot/dts/tegra124-venice2.dts
+++ b/arch/arm/boot/dts/tegra124-venice2.dts
@@ -1,19 +1,917 @@
1/dts-v1/; 1/dts-v1/;
2 2
3#include <dt-bindings/input/input.h>
3#include "tegra124.dtsi" 4#include "tegra124.dtsi"
4 5
5/ { 6/ {
6 model = "NVIDIA Tegra124 Venice2"; 7 model = "NVIDIA Tegra124 Venice2";
7 compatible = "nvidia,venice2", "nvidia,tegra124"; 8 compatible = "nvidia,venice2", "nvidia,tegra124";
8 9
10 aliases {
11 rtc0 = "/i2c@7000d000/as3722@40";
12 rtc1 = "/rtc@7000e000";
13 };
14
9 memory { 15 memory {
10 reg = <0x80000000 0x80000000>; 16 reg = <0x80000000 0x80000000>;
11 }; 17 };
12 18
19 pinmux: pinmux@70000868 {
20 pinctrl-names = "default";
21 pinctrl-0 = <&pinmux_default>;
22
23 pinmux_default: common {
24 dap_mclk1_pw4 {
25 nvidia,pins = "dap_mclk1_pw4";
26 nvidia,function = "extperiph1";
27 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
28 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
29 nvidia,tristate = <TEGRA_PIN_DISABLE>;
30 };
31 dap1_din_pn1 {
32 nvidia,pins = "dap1_din_pn1";
33 nvidia,function = "i2s0";
34 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
35 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
36 nvidia,tristate = <TEGRA_PIN_ENABLE>;
37 };
38 dap1_dout_pn2 {
39 nvidia,pins = "dap1_dout_pn2",
40 "dap1_fs_pn0",
41 "dap1_sclk_pn3";
42 nvidia,function = "i2s0";
43 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
44 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
45 nvidia,tristate = <TEGRA_PIN_ENABLE>;
46 };
47 dap2_din_pa4 {
48 nvidia,pins = "dap2_din_pa4";
49 nvidia,function = "i2s1";
50 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
51 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
52 nvidia,tristate = <TEGRA_PIN_DISABLE>;
53 };
54 dap2_dout_pa5 {
55 nvidia,pins = "dap2_dout_pa5",
56 "dap2_fs_pa2",
57 "dap2_sclk_pa3";
58 nvidia,function = "i2s1";
59 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
60 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
61 nvidia,tristate = <TEGRA_PIN_DISABLE>;
62 };
63 dvfs_pwm_px0 {
64 nvidia,pins = "dvfs_pwm_px0",
65 "dvfs_clk_px2";
66 nvidia,function = "cldvfs";
67 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
68 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
69 nvidia,tristate = <TEGRA_PIN_DISABLE>;
70 };
71 ulpi_clk_py0 {
72 nvidia,pins = "ulpi_clk_py0",
73 "ulpi_nxt_py2",
74 "ulpi_stp_py3";
75 nvidia,function = "spi1";
76 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
77 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
78 nvidia,tristate = <TEGRA_PIN_DISABLE>;
79 };
80 ulpi_dir_py1 {
81 nvidia,pins = "ulpi_dir_py1";
82 nvidia,function = "spi1";
83 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
84 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
85 nvidia,tristate = <TEGRA_PIN_DISABLE>;
86 };
87 cam_i2c_scl_pbb1 {
88 nvidia,pins = "cam_i2c_scl_pbb1",
89 "cam_i2c_sda_pbb2";
90 nvidia,function = "i2c3";
91 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
92 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
93 nvidia,tristate = <TEGRA_PIN_DISABLE>;
94 nvidia,lock = <TEGRA_PIN_DISABLE>;
95 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
96 };
97 gen2_i2c_scl_pt5 {
98 nvidia,pins = "gen2_i2c_scl_pt5",
99 "gen2_i2c_sda_pt6";
100 nvidia,function = "i2c2";
101 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
102 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
103 nvidia,tristate = <TEGRA_PIN_DISABLE>;
104 nvidia,lock = <TEGRA_PIN_DISABLE>;
105 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
106 };
107 pg4 {
108 nvidia,pins = "pg4",
109 "pg5",
110 "pg6",
111 "pi3";
112 nvidia,function = "spi4";
113 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
114 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
115 nvidia,tristate = <TEGRA_PIN_DISABLE>;
116 };
117 pg7 {
118 nvidia,pins = "pg7";
119 nvidia,function = "spi4";
120 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
121 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
122 nvidia,tristate = <TEGRA_PIN_DISABLE>;
123 };
124 ph1 {
125 nvidia,pins = "ph1";
126 nvidia,function = "pwm1";
127 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
128 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
129 nvidia,tristate = <TEGRA_PIN_DISABLE>;
130 };
131 pk0 {
132 nvidia,pins = "pk0",
133 "kb_row15_ps7",
134 "clk_32k_out_pa0";
135 nvidia,function = "soc";
136 nvidia,pull = <TEGRA_PIN_PULL_UP>;
137 nvidia,tristate = <TEGRA_PIN_DISABLE>;
138 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
139 };
140 sdmmc1_clk_pz0 {
141 nvidia,pins = "sdmmc1_clk_pz0",
142 "sdmmc1_cmd_pz1",
143 "sdmmc1_dat0_py7",
144 "sdmmc1_dat1_py6",
145 "sdmmc1_dat2_py5",
146 "sdmmc1_dat3_py4";
147 nvidia,function = "sdmmc1";
148 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
149 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
150 nvidia,tristate = <TEGRA_PIN_DISABLE>;
151 };
152 sdmmc1_cmd_pz1 {
153 nvidia,pins = "sdmmc1_cmd_pz1",
154 "sdmmc1_dat0_py7",
155 "sdmmc1_dat1_py6",
156 "sdmmc1_dat2_py5",
157 "sdmmc1_dat3_py4";
158 nvidia,function = "sdmmc1";
159 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
160 nvidia,pull = <TEGRA_PIN_PULL_UP>;
161 nvidia,tristate = <TEGRA_PIN_DISABLE>;
162 };
163 sdmmc3_clk_pa6 {
164 nvidia,pins = "sdmmc3_clk_pa6";
165 nvidia,function = "sdmmc3";
166 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
167 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
168 nvidia,tristate = <TEGRA_PIN_DISABLE>;
169 };
170 sdmmc3_cmd_pa7 {
171 nvidia,pins = "sdmmc3_cmd_pa7",
172 "sdmmc3_dat0_pb7",
173 "sdmmc3_dat1_pb6",
174 "sdmmc3_dat2_pb5",
175 "sdmmc3_dat3_pb4",
176 "sdmmc3_clk_lb_out_pee4",
177 "sdmmc3_clk_lb_in_pee5";
178 nvidia,function = "sdmmc3";
179 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
180 nvidia,pull = <TEGRA_PIN_PULL_UP>;
181 nvidia,tristate = <TEGRA_PIN_DISABLE>;
182 };
183 sdmmc4_clk_pcc4 {
184 nvidia,pins = "sdmmc4_clk_pcc4";
185 nvidia,function = "sdmmc4";
186 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
187 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
188 nvidia,tristate = <TEGRA_PIN_DISABLE>;
189 };
190 sdmmc4_cmd_pt7 {
191 nvidia,pins = "sdmmc4_cmd_pt7",
192 "sdmmc4_dat0_paa0",
193 "sdmmc4_dat1_paa1",
194 "sdmmc4_dat2_paa2",
195 "sdmmc4_dat3_paa3",
196 "sdmmc4_dat4_paa4",
197 "sdmmc4_dat5_paa5",
198 "sdmmc4_dat6_paa6",
199 "sdmmc4_dat7_paa7";
200 nvidia,function = "sdmmc4";
201 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
202 nvidia,pull = <TEGRA_PIN_PULL_UP>;
203 nvidia,tristate = <TEGRA_PIN_DISABLE>;
204 };
205 pwr_i2c_scl_pz6 {
206 nvidia,pins = "pwr_i2c_scl_pz6",
207 "pwr_i2c_sda_pz7";
208 nvidia,function = "i2cpwr";
209 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
210 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
211 nvidia,tristate = <TEGRA_PIN_DISABLE>;
212 nvidia,lock = <TEGRA_PIN_DISABLE>;
213 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
214 };
215 jtag_rtck {
216 nvidia,pins = "jtag_rtck";
217 nvidia,function = "rtck";
218 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
219 nvidia,pull = <TEGRA_PIN_PULL_UP>;
220 nvidia,tristate = <TEGRA_PIN_DISABLE>;
221 };
222 clk_32k_in {
223 nvidia,pins = "clk_32k_in";
224 nvidia,function = "clk";
225 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
226 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
227 nvidia,tristate = <TEGRA_PIN_DISABLE>;
228 };
229 core_pwr_req {
230 nvidia,pins = "core_pwr_req";
231 nvidia,function = "pwron";
232 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
233 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
234 nvidia,tristate = <TEGRA_PIN_DISABLE>;
235 };
236 cpu_pwr_req {
237 nvidia,pins = "cpu_pwr_req";
238 nvidia,function = "cpu";
239 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
240 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
241 nvidia,tristate = <TEGRA_PIN_DISABLE>;
242 };
243 pwr_int_n {
244 nvidia,pins = "pwr_int_n";
245 nvidia,function = "pmi";
246 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
247 nvidia,pull = <TEGRA_PIN_PULL_UP>;
248 nvidia,tristate = <TEGRA_PIN_DISABLE>;
249 };
250 reset_out_n {
251 nvidia,pins = "reset_out_n";
252 nvidia,function = "reset_out_n";
253 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
254 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
255 nvidia,tristate = <TEGRA_PIN_DISABLE>;
256 };
257 clk3_out_pee0 {
258 nvidia,pins = "clk3_out_pee0";
259 nvidia,function = "extperiph3";
260 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
261 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
262 nvidia,tristate = <TEGRA_PIN_DISABLE>;
263 };
264 dap4_din_pp5 {
265 nvidia,pins = "dap4_din_pp5";
266 nvidia,function = "i2s3";
267 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
268 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
269 nvidia,tristate = <TEGRA_PIN_ENABLE>;
270 };
271 dap4_dout_pp6 {
272 nvidia,pins = "dap4_dout_pp6",
273 "dap4_fs_pp4",
274 "dap4_sclk_pp7";
275 nvidia,function = "i2s3";
276 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
277 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
278 nvidia,tristate = <TEGRA_PIN_ENABLE>;
279 };
280 gen1_i2c_sda_pc5 {
281 nvidia,pins = "gen1_i2c_sda_pc5",
282 "gen1_i2c_scl_pc4";
283 nvidia,function = "i2c1";
284 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
285 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
286 nvidia,tristate = <TEGRA_PIN_DISABLE>;
287 nvidia,lock = <TEGRA_PIN_DISABLE>;
288 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
289 };
290 uart2_cts_n_pj5 {
291 nvidia,pins = "uart2_cts_n_pj5";
292 nvidia,function = "uartb";
293 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
294 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
295 nvidia,tristate = <TEGRA_PIN_DISABLE>;
296 };
297 uart2_rts_n_pj6 {
298 nvidia,pins = "uart2_rts_n_pj6";
299 nvidia,function = "uartb";
300 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
301 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
302 nvidia,tristate = <TEGRA_PIN_DISABLE>;
303 };
304 uart2_rxd_pc3 {
305 nvidia,pins = "uart2_rxd_pc3";
306 nvidia,function = "irda";
307 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
308 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
309 nvidia,tristate = <TEGRA_PIN_DISABLE>;
310 };
311 uart2_txd_pc2 {
312 nvidia,pins = "uart2_txd_pc2";
313 nvidia,function = "irda";
314 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
315 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
316 nvidia,tristate = <TEGRA_PIN_DISABLE>;
317 };
318 uart3_cts_n_pa1 {
319 nvidia,pins = "uart3_cts_n_pa1",
320 "uart3_rxd_pw7";
321 nvidia,function = "uartc";
322 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
323 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
324 nvidia,tristate = <TEGRA_PIN_DISABLE>;
325 };
326 uart3_rts_n_pc0 {
327 nvidia,pins = "uart3_rts_n_pc0",
328 "uart3_txd_pw6";
329 nvidia,function = "uartc";
330 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
331 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
332 nvidia,tristate = <TEGRA_PIN_DISABLE>;
333 };
334 hdmi_cec_pee3 {
335 nvidia,pins = "hdmi_cec_pee3";
336 nvidia,function = "cec";
337 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
338 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
339 nvidia,tristate = <TEGRA_PIN_DISABLE>;
340 nvidia,lock = <TEGRA_PIN_DISABLE>;
341 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
342 };
343 hdmi_int_pn7 {
344 nvidia,pins = "hdmi_int_pn7";
345 nvidia,function = "rsvd1";
346 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
347 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
348 nvidia,tristate = <TEGRA_PIN_DISABLE>;
349 };
350 ddc_scl_pv4 {
351 nvidia,pins = "ddc_scl_pv4",
352 "ddc_sda_pv5";
353 nvidia,function = "i2c4";
354 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
355 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
356 nvidia,tristate = <TEGRA_PIN_DISABLE>;
357 nvidia,lock = <TEGRA_PIN_DISABLE>;
358 nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
359 };
360 pj7 {
361 nvidia,pins = "pj7",
362 "pk7";
363 nvidia,function = "uartd";
364 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
365 nvidia,tristate = <TEGRA_PIN_DISABLE>;
366 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
367 };
368 pb0 {
369 nvidia,pins = "pb0",
370 "pb1";
371 nvidia,function = "uartd";
372 nvidia,pull = <TEGRA_PIN_PULL_UP>;
373 nvidia,tristate = <TEGRA_PIN_DISABLE>;
374 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
375 };
376 ph0 {
377 nvidia,pins = "ph0";
378 nvidia,function = "pwm0";
379 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
380 nvidia,tristate = <TEGRA_PIN_DISABLE>;
381 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
382 };
383 kb_row10_ps2 {
384 nvidia,pins = "kb_row10_ps2";
385 nvidia,function = "uarta";
386 nvidia,pull = <TEGRA_PIN_PULL_UP>;
387 nvidia,tristate = <TEGRA_PIN_DISABLE>;
388 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
389 };
390 kb_row9_ps1 {
391 nvidia,pins = "kb_row9_ps1";
392 nvidia,function = "uarta";
393 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
394 nvidia,tristate = <TEGRA_PIN_DISABLE>;
395 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
396 };
397 kb_row6_pr6 {
398 nvidia,pins = "kb_row6_pr6";
399 nvidia,function = "displaya_alt";
400 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
401 nvidia,tristate = <TEGRA_PIN_DISABLE>;
402 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
403 };
404 usb_vbus_en0_pn4 {
405 nvidia,pins = "usb_vbus_en0_pn4";
406 nvidia,function = "usb";
407 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
408 nvidia,pull = <TEGRA_PIN_PULL_UP>;
409 nvidia,tristate = <TEGRA_PIN_DISABLE>;
410 nvidia,lock = <TEGRA_PIN_DISABLE>;
411 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
412 };
413 usb_vbus_en1_pn5 {
414 nvidia,pins = "usb_vbus_en1_pn5";
415 nvidia,function = "usb";
416 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
417 nvidia,pull = <TEGRA_PIN_PULL_UP>;
418 nvidia,tristate = <TEGRA_PIN_DISABLE>;
419 nvidia,lock = <TEGRA_PIN_DISABLE>;
420 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
421 };
422 drive_sdio1 {
423 nvidia,pins = "drive_sdio1";
424 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
425 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
426 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
427 nvidia,pull-down-strength = <32>;
428 nvidia,pull-up-strength = <42>;
429 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
430 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
431 };
432 drive_sdio3 {
433 nvidia,pins = "drive_sdio3";
434 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
435 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
436 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
437 nvidia,pull-down-strength = <20>;
438 nvidia,pull-up-strength = <36>;
439 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
440 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
441 };
442 drive_gma {
443 nvidia,pins = "drive_gma";
444 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
445 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
446 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
447 nvidia,pull-down-strength = <1>;
448 nvidia,pull-up-strength = <2>;
449 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
450 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
451 nvidia,drive-type = <1>;
452 };
453 als_irq_l {
454 nvidia,pins = "gpio_x3_aud_px3";
455 nvidia,function = "gmi";
456 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
457 nvidia,tristate = <TEGRA_PIN_ENABLE>;
458 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
459 };
460 codec_irq_l {
461 nvidia,pins = "ph4";
462 nvidia,function = "gmi";
463 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
464 nvidia,tristate = <TEGRA_PIN_DISABLE>;
465 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
466 };
467 lcd_bl_en {
468 nvidia,pins = "ph2";
469 nvidia,function = "gmi";
470 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
471 nvidia,tristate = <TEGRA_PIN_DISABLE>;
472 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
473 };
474 touch_irq_l {
475 nvidia,pins = "gpio_w3_aud_pw3";
476 nvidia,function = "spi6";
477 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
478 nvidia,tristate = <TEGRA_PIN_ENABLE>;
479 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
480 };
481 tpm_davint_l {
482 nvidia,pins = "ph6";
483 nvidia,function = "gmi";
484 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
485 nvidia,tristate = <TEGRA_PIN_ENABLE>;
486 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
487 };
488 ts_irq_l {
489 nvidia,pins = "pk2";
490 nvidia,function = "gmi";
491 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
492 nvidia,tristate = <TEGRA_PIN_ENABLE>;
493 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
494 };
495 ts_reset_l {
496 nvidia,pins = "pk4";
497 nvidia,function = "gmi";
498 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
499 nvidia,tristate = <TEGRA_PIN_DISABLE>;
500 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
501 };
502 ts_shdn_l {
503 nvidia,pins = "pk1";
504 nvidia,function = "gmi";
505 nvidia,pull = <TEGRA_PIN_PULL_UP>;
506 nvidia,tristate = <TEGRA_PIN_DISABLE>;
507 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
508 };
509 ph7 {
510 nvidia,pins = "ph7";
511 nvidia,function = "gmi";
512 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
513 nvidia,tristate = <TEGRA_PIN_DISABLE>;
514 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
515 };
516 kb_col0_ap {
517 nvidia,pins = "kb_col0_pq0";
518 nvidia,function = "rsvd4";
519 nvidia,pull = <TEGRA_PIN_PULL_UP>;
520 nvidia,tristate = <TEGRA_PIN_DISABLE>;
521 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
522 };
523 lid_open {
524 nvidia,pins = "kb_row4_pr4";
525 nvidia,function = "rsvd3";
526 nvidia,pull = <TEGRA_PIN_PULL_UP>;
527 nvidia,tristate = <TEGRA_PIN_DISABLE>;
528 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
529 };
530 en_vdd_sd {
531 nvidia,pins = "kb_row0_pr0";
532 nvidia,function = "rsvd4";
533 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
534 nvidia,tristate = <TEGRA_PIN_DISABLE>;
535 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
536 };
537 ac_ok {
538 nvidia,pins = "pj0";
539 nvidia,function = "gmi";
540 nvidia,pull = <TEGRA_PIN_PULL_UP>;
541 nvidia,tristate = <TEGRA_PIN_ENABLE>;
542 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
543 };
544 sensor_irq_l {
545 nvidia,pins = "pi6";
546 nvidia,function = "gmi";
547 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
548 nvidia,tristate = <TEGRA_PIN_DISABLE>;
549 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
550 };
551 wifi_en {
552 nvidia,pins = "gpio_x7_aud_px7";
553 nvidia,function = "rsvd4";
554 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
555 nvidia,tristate = <TEGRA_PIN_DISABLE>;
556 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
557 };
558 wifi_rst_l {
559 nvidia,pins = "clk2_req_pcc5";
560 nvidia,function = "dap";
561 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
562 nvidia,tristate = <TEGRA_PIN_DISABLE>;
563 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
564 };
565 hp_det_l {
566 nvidia,pins = "ulpi_data1_po2";
567 nvidia,function = "spi3";
568 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
569 nvidia,tristate = <TEGRA_PIN_DISABLE>;
570 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
571 };
572 };
573 };
574
13 serial@70006000 { 575 serial@70006000 {
14 status = "okay"; 576 status = "okay";
15 }; 577 };
16 578
579 pwm: pwm@7000a000 {
580 status = "okay";
581 };
582
583 i2c@7000c000 {
584 status = "okay";
585 clock-frequency = <100000>;
586
587 acodec: audio-codec@10 {
588 compatible = "maxim,max98090";
589 reg = <0x10>;
590 interrupt-parent = <&gpio>;
591 interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
592 };
593 };
594
595 i2c@7000c400 {
596 status = "okay";
597 clock-frequency = <100000>;
598 };
599
600 i2c@7000c500 {
601 status = "okay";
602 clock-frequency = <100000>;
603 };
604
605 i2c@7000c700 {
606 status = "okay";
607 clock-frequency = <100000>;
608 };
609
610 i2c@7000d000 {
611 status = "okay";
612 clock-frequency = <400000>;
613
614 as3722: as3722@40 {
615 compatible = "ams,as3722";
616 reg = <0x40>;
617 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
618
619 #interrupt-cells = <2>;
620 interrupt-controller;
621
622 gpio-controller;
623 #gpio-cells = <2>;
624
625 pinctrl-names = "default";
626 pinctrl-0 = <&as3722_default>;
627
628 as3722_default: pinmux {
629 gpio0 {
630 pins = "gpio0";
631 function = "gpio";
632 bias-pull-down;
633 };
634
635 gpio1_2_4_7 {
636 pins = "gpio1", "gpio2", "gpio4", "gpio7";
637 function = "gpio";
638 bias-pull-up;
639 };
640
641 gpio3_6 {
642 pins = "gpio3", "gpio6";
643 bias-high-impedance;
644 };
645
646 gpio5 {
647 pins = "gpio5";
648 function = "clk32k-out";
649 };
650 };
651
652 regulators {
653 vsup-sd2-supply = <&vdd_ac_bat_reg>;
654 vsup-sd3-supply = <&vdd_ac_bat_reg>;
655 vsup-sd4-supply = <&vdd_ac_bat_reg>;
656 vsup-sd5-supply = <&vdd_ac_bat_reg>;
657 vin-ldo0-supply = <&as3722_sd2>;
658 vin-ldo1-6-supply = <&vdd_ac_bat_reg>;
659 vin-ldo2-5-7-supply = <&as3722_sd5>;
660 vin-ldo3-4-supply = <&vdd_ac_bat_reg>;
661 vin-ldo9-10-supply = <&vdd_ac_bat_reg>;
662 vin-ldo11-supply = <&vdd_ac_bat_reg>;
663
664 sd0 {
665 regulator-name = "vdd-cpu";
666 regulator-min-microvolt = <700000>;
667 regulator-max-microvolt = <1400000>;
668 regulator-min-microamp = <3500000>;
669 regulator-max-microamp = <3500000>;
670 regulator-always-on;
671 regulator-boot-on;
672 ams,external-control = <2>;
673 };
674
675 sd1 {
676 regulator-name = "vdd-core";
677 regulator-min-microvolt = <700000>;
678 regulator-max-microvolt = <1350000>;
679 regulator-min-microamp = <2500000>;
680 regulator-max-microamp = <2500000>;
681 regulator-always-on;
682 regulator-boot-on;
683 ams,external-control = <1>;
684 };
685
686 as3722_sd2: sd2 {
687 regulator-name = "vddio-ddr";
688 regulator-min-microvolt = <1350000>;
689 regulator-max-microvolt = <1350000>;
690 regulator-always-on;
691 regulator-boot-on;
692 };
693
694 sd3 {
695 regulator-name = "vddio-ddr-2phase";
696 regulator-min-microvolt = <1350000>;
697 regulator-max-microvolt = <1350000>;
698 regulator-always-on;
699 regulator-boot-on;
700 };
701
702 sd4 {
703 regulator-name = "avdd-pex-sata";
704 regulator-min-microvolt = <1050000>;
705 regulator-max-microvolt = <1050000>;
706 regulator-boot-on;
707 regulator-always-on;
708 };
709
710 as3722_sd5: sd5 {
711 regulator-name = "vddio-sys";
712 regulator-min-microvolt = <1800000>;
713 regulator-max-microvolt = <1800000>;
714 regulator-boot-on;
715 regulator-always-on;
716 };
717
718 sd6 {
719 regulator-name = "vdd-gpu";
720 regulator-min-microvolt = <650000>;
721 regulator-max-microvolt = <1200000>;
722 regulator-min-microamp = <3500000>;
723 regulator-max-microamp = <3500000>;
724 regulator-boot-on;
725 regulator-always-on;
726 };
727
728 ldo0 {
729 regulator-name = "avdd_pll";
730 regulator-min-microvolt = <1050000>;
731 regulator-max-microvolt = <1050000>;
732 regulator-boot-on;
733 regulator-always-on;
734 ams,external-control = <1>;
735 };
736
737 ldo1 {
738 regulator-name = "run-cam-1.8";
739 regulator-min-microvolt = <1800000>;
740 regulator-max-microvolt = <1800000>;
741 };
742
743 ldo2 {
744 regulator-name = "gen-avdd,vddio-hsic";
745 regulator-min-microvolt = <1200000>;
746 regulator-max-microvolt = <1200000>;
747 regulator-boot-on;
748 regulator-always-on;
749 };
750
751 ldo3 {
752 regulator-name = "vdd-rtc";
753 regulator-min-microvolt = <1000000>;
754 regulator-max-microvolt = <1000000>;
755 regulator-boot-on;
756 regulator-always-on;
757 ams,enable-tracking;
758 };
759
760 ldo4 {
761 regulator-name = "vdd-cam";
762 regulator-min-microvolt = <2800000>;
763 regulator-max-microvolt = <2800000>;
764 regulator-boot-on;
765 regulator-always-on;
766 };
767
768 ldo5 {
769 regulator-name = "vdd-cam-front";
770 regulator-min-microvolt = <1200000>;
771 regulator-max-microvolt = <1200000>;
772 };
773
774 ldo6 {
775 regulator-name = "vddio-sdmmc3";
776 regulator-min-microvolt = <1800000>;
777 regulator-max-microvolt = <3300000>;
778 regulator-boot-on;
779 regulator-always-on;
780 };
781
782 ldo7 {
783 regulator-name = "vdd-cam-rear";
784 regulator-min-microvolt = <1050000>;
785 regulator-max-microvolt = <1050000>;
786 };
787
788 ldo9 {
789 regulator-name = "vdd-touch";
790 regulator-min-microvolt = <2800000>;
791 regulator-max-microvolt = <2800000>;
792 };
793
794 ldo10 {
795 regulator-name = "vdd-cam-af";
796 regulator-min-microvolt = <2800000>;
797 regulator-max-microvolt = <2800000>;
798 };
799
800 ldo11 {
801 regulator-name = "vpp-fuse";
802 regulator-min-microvolt = <1800000>;
803 regulator-max-microvolt = <1800000>;
804 };
805 };
806 };
807 };
808
809 spi@7000d400 {
810 status = "okay";
811
812 cros-ec@0 {
813 compatible = "google,cros-ec-spi";
814 spi-max-frequency = <4000000>;
815 interrupt-parent = <&gpio>;
816 interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>;
817 reg = <0>;
818
819 google,cros-ec-spi-msg-delay = <2000>;
820
821 cros-ec-keyb {
822 compatible = "google,cros-ec-keyb";
823 keypad,num-rows = <8>;
824 keypad,num-columns = <13>;
825 google,needs-ghost-filter;
826
827 linux,keymap = <
828 MATRIX_KEY(0x00, 0x01, KEY_LEFTMETA)
829 MATRIX_KEY(0x00, 0x02, KEY_F1)
830 MATRIX_KEY(0x00, 0x03, KEY_B)
831 MATRIX_KEY(0x00, 0x04, KEY_F10)
832 MATRIX_KEY(0x00, 0x06, KEY_N)
833 MATRIX_KEY(0x00, 0x08, KEY_EQUAL)
834 MATRIX_KEY(0x00, 0x0a, KEY_RIGHTALT)
835
836 MATRIX_KEY(0x01, 0x01, KEY_ESC)
837 MATRIX_KEY(0x01, 0x02, KEY_F4)
838 MATRIX_KEY(0x01, 0x03, KEY_G)
839 MATRIX_KEY(0x01, 0x04, KEY_F7)
840 MATRIX_KEY(0x01, 0x06, KEY_H)
841 MATRIX_KEY(0x01, 0x08, KEY_APOSTROPHE)
842 MATRIX_KEY(0x01, 0x09, KEY_F9)
843 MATRIX_KEY(0x01, 0x0b, KEY_BACKSPACE)
844
845 MATRIX_KEY(0x02, 0x00, KEY_LEFTCTRL)
846 MATRIX_KEY(0x02, 0x01, KEY_TAB)
847 MATRIX_KEY(0x02, 0x02, KEY_F3)
848 MATRIX_KEY(0x02, 0x03, KEY_T)
849 MATRIX_KEY(0x02, 0x04, KEY_F6)
850 MATRIX_KEY(0x02, 0x05, KEY_RIGHTBRACE)
851 MATRIX_KEY(0x02, 0x06, KEY_Y)
852 MATRIX_KEY(0x02, 0x07, KEY_102ND)
853 MATRIX_KEY(0x02, 0x08, KEY_LEFTBRACE)
854 MATRIX_KEY(0x02, 0x09, KEY_F8)
855
856 MATRIX_KEY(0x03, 0x01, KEY_GRAVE)
857 MATRIX_KEY(0x03, 0x02, KEY_F2)
858 MATRIX_KEY(0x03, 0x03, KEY_5)
859 MATRIX_KEY(0x03, 0x04, KEY_F5)
860 MATRIX_KEY(0x03, 0x06, KEY_6)
861 MATRIX_KEY(0x03, 0x08, KEY_MINUS)
862 MATRIX_KEY(0x03, 0x0b, KEY_BACKSLASH)
863
864 MATRIX_KEY(0x04, 0x00, KEY_RIGHTCTRL)
865 MATRIX_KEY(0x04, 0x01, KEY_A)
866 MATRIX_KEY(0x04, 0x02, KEY_D)
867 MATRIX_KEY(0x04, 0x03, KEY_F)
868 MATRIX_KEY(0x04, 0x04, KEY_S)
869 MATRIX_KEY(0x04, 0x05, KEY_K)
870 MATRIX_KEY(0x04, 0x06, KEY_J)
871 MATRIX_KEY(0x04, 0x08, KEY_SEMICOLON)
872 MATRIX_KEY(0x04, 0x09, KEY_L)
873 MATRIX_KEY(0x04, 0x0a, KEY_BACKSLASH)
874 MATRIX_KEY(0x04, 0x0b, KEY_ENTER)
875
876 MATRIX_KEY(0x05, 0x01, KEY_Z)
877 MATRIX_KEY(0x05, 0x02, KEY_C)
878 MATRIX_KEY(0x05, 0x03, KEY_V)
879 MATRIX_KEY(0x05, 0x04, KEY_X)
880 MATRIX_KEY(0x05, 0x05, KEY_COMMA)
881 MATRIX_KEY(0x05, 0x06, KEY_M)
882 MATRIX_KEY(0x05, 0x07, KEY_LEFTSHIFT)
883 MATRIX_KEY(0x05, 0x08, KEY_SLASH)
884 MATRIX_KEY(0x05, 0x09, KEY_DOT)
885 MATRIX_KEY(0x05, 0x0b, KEY_SPACE)
886
887 MATRIX_KEY(0x06, 0x01, KEY_1)
888 MATRIX_KEY(0x06, 0x02, KEY_3)
889 MATRIX_KEY(0x06, 0x03, KEY_4)
890 MATRIX_KEY(0x06, 0x04, KEY_2)
891 MATRIX_KEY(0x06, 0x05, KEY_8)
892 MATRIX_KEY(0x06, 0x06, KEY_7)
893 MATRIX_KEY(0x06, 0x08, KEY_0)
894 MATRIX_KEY(0x06, 0x09, KEY_9)
895 MATRIX_KEY(0x06, 0x0a, KEY_LEFTALT)
896 MATRIX_KEY(0x06, 0x0b, KEY_DOWN)
897 MATRIX_KEY(0x06, 0x0c, KEY_RIGHT)
898
899 MATRIX_KEY(0x07, 0x01, KEY_Q)
900 MATRIX_KEY(0x07, 0x02, KEY_E)
901 MATRIX_KEY(0x07, 0x03, KEY_R)
902 MATRIX_KEY(0x07, 0x04, KEY_W)
903 MATRIX_KEY(0x07, 0x05, KEY_I)
904 MATRIX_KEY(0x07, 0x06, KEY_U)
905 MATRIX_KEY(0x07, 0x07, KEY_RIGHTSHIFT)
906 MATRIX_KEY(0x07, 0x08, KEY_P)
907 MATRIX_KEY(0x07, 0x09, KEY_O)
908 MATRIX_KEY(0x07, 0x0b, KEY_UP)
909 MATRIX_KEY(0x07, 0x0c, KEY_LEFT)
910 >;
911 };
912 };
913 };
914
17 pmc@7000e400 { 915 pmc@7000e400 {
18 nvidia,invert-interrupt; 916 nvidia,invert-interrupt;
19 nvidia,suspend-mode = <1>; 917 nvidia,suspend-mode = <1>;
@@ -24,4 +922,170 @@
24 nvidia,core-power-req-active-high; 922 nvidia,core-power-req-active-high;
25 nvidia,sys-clock-req-active-high; 923 nvidia,sys-clock-req-active-high;
26 }; 924 };
925
926 sdhci@700b0400 {
927 cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
928 power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
929 status = "okay";
930 bus-width = <4>;
931 };
932
933 sdhci@700b0600 {
934 status = "okay";
935 bus-width = <8>;
936 };
937
938 ahub@70300000 {
939 i2s@70301100 {
940 status = "okay";
941 };
942 };
943
944 clocks {
945 compatible = "simple-bus";
946 #address-cells = <1>;
947 #size-cells = <0>;
948
949 clk32k_in: clock@0 {
950 compatible = "fixed-clock";
951 reg=<0>;
952 #clock-cells = <0>;
953 clock-frequency = <32768>;
954 };
955 };
956
957 gpio-keys {
958 compatible = "gpio-keys";
959
960 power {
961 label = "Power";
962 gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
963 linux,code = <KEY_POWER>;
964 debounce-interval = <10>;
965 gpio-key,wakeup;
966 };
967 };
968
969 regulators {
970 compatible = "simple-bus";
971 #address-cells = <1>;
972 #size-cells = <0>;
973
974 vdd_ac_bat_reg: regulator@0 {
975 compatible = "regulator-fixed";
976 reg = <0>;
977 regulator-name = "vdd_ac_bat";
978 regulator-min-microvolt = <5000000>;
979 regulator-max-microvolt = <5000000>;
980 regulator-always-on;
981 };
982
983 vdd_3v3_reg: regulator@1 {
984 compatible = "regulator-fixed";
985 reg = <1>;
986 regulator-name = "vdd_3v3";
987 regulator-min-microvolt = <3300000>;
988 regulator-max-microvolt = <3300000>;
989 regulator-always-on;
990 regulator-boot-on;
991 enable-active-high;
992 gpio = <&as3722 1 GPIO_ACTIVE_HIGH>;
993 };
994
995 vdd_3v3_modem_reg: regulator@2 {
996 compatible = "regulator-fixed";
997 reg = <2>;
998 regulator-name = "vdd-modem-3v3";
999 regulator-min-microvolt = <3300000>;
1000 regulator-max-microvolt = <3300000>;
1001 enable-active-high;
1002 gpio = <&as3722 2 GPIO_ACTIVE_HIGH>;
1003 };
1004
1005 vdd_hdmi_5v0_reg: regulator@3 {
1006 compatible = "regulator-fixed";
1007 reg = <3>;
1008 regulator-name = "vdd-hdmi-5v0";
1009 regulator-min-microvolt = <5000000>;
1010 regulator-max-microvolt = <5000000>;
1011 enable-active-high;
1012 gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
1013 };
1014
1015 vdd_bl_reg: regulator@4 {
1016 compatible = "regulator-fixed";
1017 reg = <4>;
1018 regulator-name = "vdd-bl";
1019 regulator-min-microvolt = <3300000>;
1020 regulator-max-microvolt = <3300000>;
1021 gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_LOW>;
1022 };
1023
1024 vdd_ts_sw_5v0: regulator@5 {
1025 compatible = "regulator-fixed";
1026 reg = <5>;
1027 regulator-name = "vdd_ts_sw";
1028 regulator-min-microvolt = <5000000>;
1029 regulator-max-microvolt = <5000000>;
1030 enable-active-high;
1031 regulator-boot-on;
1032 gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_LOW>;
1033 };
1034
1035 usb1_vbus_reg: regulator@6 {
1036 compatible = "regulator-fixed";
1037 reg = <6>;
1038 regulator-name = "usb1_vbus";
1039 regulator-min-microvolt = <5000000>;
1040 regulator-max-microvolt = <5000000>;
1041 regulator-boot-on;
1042 enable-active-high;
1043 gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
1044 gpio-open-drain;
1045 };
1046
1047 usb3_vbus_reg: regulator@7 {
1048 compatible = "regulator-fixed";
1049 reg = <7>;
1050 regulator-name = "usb3_vbus";
1051 regulator-min-microvolt = <5000000>;
1052 regulator-max-microvolt = <5000000>;
1053 regulator-boot-on;
1054 enable-active-high;
1055 gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
1056 gpio-open-drain;
1057 };
1058
1059 panel_3v3_reg: regulator@8 {
1060 compatible = "regulator-fixed";
1061 reg = <8>;
1062 regulator-name = "panel_3v3";
1063 regulator-min-microvolt = <3300000>;
1064 regulator-max-microvolt = <3300000>;
1065 enable-active-high;
1066 gpio = <&as3722 4 GPIO_ACTIVE_HIGH>;
1067 };
1068 };
1069
1070 sound {
1071 compatible = "nvidia,tegra-audio-max98090-venice2",
1072 "nvidia,tegra-audio-max98090";
1073 nvidia,model = "NVIDIA Tegra Venice2";
1074
1075 nvidia,audio-routing =
1076 "Headphones", "HPR",
1077 "Headphones", "HPL",
1078 "Speakers", "SPKR",
1079 "Speakers", "SPKL",
1080 "Mic Jack", "MICBIAS",
1081 "IN34", "Mic Jack";
1082
1083 nvidia,i2s-controller = <&tegra_i2s1>;
1084 nvidia,audio-codec = <&acodec>;
1085
1086 clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
1087 <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
1088 <&tegra_car TEGRA124_CLK_EXTERN1>;
1089 clock-names = "pll_a", "pll_a_out0", "mclk";
1090 };
27}; 1091};
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index b7413004ee77..ec0698a8354a 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -1,4 +1,6 @@
1#include <dt-bindings/clock/tegra124-car.h>
1#include <dt-bindings/gpio/tegra-gpio.h> 2#include <dt-bindings/gpio/tegra-gpio.h>
3#include <dt-bindings/pinctrl/pinctrl-tegra.h>
2#include <dt-bindings/interrupt-controller/arm-gic.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h>
3 5
4#include "skeleton.dtsi" 6#include "skeleton.dtsi"
@@ -28,6 +30,14 @@
28 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
29 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
30 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 32 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
33 clocks = <&tegra_car TEGRA124_CLK_TIMER>;
34 };
35
36 tegra_car: clock@60006000 {
37 compatible = "nvidia,tegra124-car";
38 reg = <0x60006000 0x1000>;
39 #clock-cells = <1>;
40 #reset-cells = <1>;
31 }; 41 };
32 42
33 gpio: gpio@6000d000 { 43 gpio: gpio@6000d000 {
@@ -47,6 +57,53 @@
47 interrupt-controller; 57 interrupt-controller;
48 }; 58 };
49 59
60 apbdma: dma@60020000 {
61 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
62 reg = <0x60020000 0x1400>;
63 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
64 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
65 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
66 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
67 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
68 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
69 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
70 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
71 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
72 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
73 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
74 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
75 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
76 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
77 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
78 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
79 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
80 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
81 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
82 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
83 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
84 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
85 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
86 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
87 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
88 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
89 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
90 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
91 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
92 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
93 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
94 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
95 clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
96 resets = <&tegra_car 34>;
97 reset-names = "dma";
98 #dma-cells = <1>;
99 };
100
101 pinmux: pinmux@70000868 {
102 compatible = "nvidia,tegra124-pinmux";
103 reg = <0x70000868 0x164>, /* Pad control registers */
104 <0x70003000 0x434>; /* Mux registers */
105 };
106
50 /* 107 /*
51 * There are two serial driver i.e. 8250 based simple serial 108 * There are two serial driver i.e. 8250 based simple serial
52 * driver and APB DMA based serial driver for higher baudrate 109 * driver and APB DMA based serial driver for higher baudrate
@@ -60,6 +117,11 @@
60 reg = <0x70006000 0x40>; 117 reg = <0x70006000 0x40>;
61 reg-shift = <2>; 118 reg-shift = <2>;
62 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 119 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
120 clocks = <&tegra_car TEGRA124_CLK_UARTA>;
121 resets = <&tegra_car 6>;
122 reset-names = "serial";
123 dmas = <&apbdma 8>, <&apbdma 8>;
124 dma-names = "rx", "tx";
63 status = "disabled"; 125 status = "disabled";
64 }; 126 };
65 127
@@ -68,6 +130,11 @@
68 reg = <0x70006040 0x40>; 130 reg = <0x70006040 0x40>;
69 reg-shift = <2>; 131 reg-shift = <2>;
70 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 132 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
133 clocks = <&tegra_car TEGRA124_CLK_UARTB>;
134 resets = <&tegra_car 7>;
135 reset-names = "serial";
136 dmas = <&apbdma 9>, <&apbdma 9>;
137 dma-names = "rx", "tx";
71 status = "disabled"; 138 status = "disabled";
72 }; 139 };
73 140
@@ -76,6 +143,11 @@
76 reg = <0x70006200 0x40>; 143 reg = <0x70006200 0x40>;
77 reg-shift = <2>; 144 reg-shift = <2>;
78 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 145 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
146 clocks = <&tegra_car TEGRA124_CLK_UARTC>;
147 resets = <&tegra_car 55>;
148 reset-names = "serial";
149 dmas = <&apbdma 10>, <&apbdma 10>;
150 dma-names = "rx", "tx";
79 status = "disabled"; 151 status = "disabled";
80 }; 152 };
81 153
@@ -84,6 +156,11 @@
84 reg = <0x70006300 0x40>; 156 reg = <0x70006300 0x40>;
85 reg-shift = <2>; 157 reg-shift = <2>;
86 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 158 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
159 clocks = <&tegra_car TEGRA124_CLK_UARTD>;
160 resets = <&tegra_car 65>;
161 reset-names = "serial";
162 dmas = <&apbdma 19>, <&apbdma 19>;
163 dma-names = "rx", "tx";
87 status = "disabled"; 164 status = "disabled";
88 }; 165 };
89 166
@@ -92,6 +169,201 @@
92 reg = <0x70006400 0x40>; 169 reg = <0x70006400 0x40>;
93 reg-shift = <2>; 170 reg-shift = <2>;
94 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 171 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
172 clocks = <&tegra_car TEGRA124_CLK_UARTE>;
173 resets = <&tegra_car 66>;
174 reset-names = "serial";
175 dmas = <&apbdma 20>, <&apbdma 20>;
176 dma-names = "rx", "tx";
177 status = "disabled";
178 };
179
180 pwm@7000a000 {
181 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
182 reg = <0x7000a000 0x100>;
183 #pwm-cells = <2>;
184 clocks = <&tegra_car TEGRA124_CLK_PWM>;
185 resets = <&tegra_car 17>;
186 reset-names = "pwm";
187 status = "disabled";
188 };
189
190 i2c@7000c000 {
191 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
192 reg = <0x7000c000 0x100>;
193 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
194 #address-cells = <1>;
195 #size-cells = <0>;
196 clocks = <&tegra_car TEGRA124_CLK_I2C1>;
197 clock-names = "div-clk";
198 resets = <&tegra_car 12>;
199 reset-names = "i2c";
200 dmas = <&apbdma 21>, <&apbdma 21>;
201 dma-names = "rx", "tx";
202 status = "disabled";
203 };
204
205 i2c@7000c400 {
206 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
207 reg = <0x7000c400 0x100>;
208 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
209 #address-cells = <1>;
210 #size-cells = <0>;
211 clocks = <&tegra_car TEGRA124_CLK_I2C2>;
212 clock-names = "div-clk";
213 resets = <&tegra_car 54>;
214 reset-names = "i2c";
215 dmas = <&apbdma 22>, <&apbdma 22>;
216 dma-names = "rx", "tx";
217 status = "disabled";
218 };
219
220 i2c@7000c500 {
221 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
222 reg = <0x7000c500 0x100>;
223 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
224 #address-cells = <1>;
225 #size-cells = <0>;
226 clocks = <&tegra_car TEGRA124_CLK_I2C3>;
227 clock-names = "div-clk";
228 resets = <&tegra_car 67>;
229 reset-names = "i2c";
230 dmas = <&apbdma 23>, <&apbdma 23>;
231 dma-names = "rx", "tx";
232 status = "disabled";
233 };
234
235 i2c@7000c700 {
236 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
237 reg = <0x7000c700 0x100>;
238 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
239 #address-cells = <1>;
240 #size-cells = <0>;
241 clocks = <&tegra_car TEGRA124_CLK_I2C4>;
242 clock-names = "div-clk";
243 resets = <&tegra_car 103>;
244 reset-names = "i2c";
245 dmas = <&apbdma 26>, <&apbdma 26>;
246 dma-names = "rx", "tx";
247 status = "disabled";
248 };
249
250 i2c@7000d000 {
251 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
252 reg = <0x7000d000 0x100>;
253 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
254 #address-cells = <1>;
255 #size-cells = <0>;
256 clocks = <&tegra_car TEGRA124_CLK_I2C5>;
257 clock-names = "div-clk";
258 resets = <&tegra_car 47>;
259 reset-names = "i2c";
260 dmas = <&apbdma 24>, <&apbdma 24>;
261 dma-names = "rx", "tx";
262 status = "disabled";
263 };
264
265 i2c@7000d100 {
266 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
267 reg = <0x7000d100 0x100>;
268 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
269 #address-cells = <1>;
270 #size-cells = <0>;
271 clocks = <&tegra_car TEGRA124_CLK_I2C6>;
272 clock-names = "div-clk";
273 resets = <&tegra_car 166>;
274 reset-names = "i2c";
275 dmas = <&apbdma 30>, <&apbdma 30>;
276 dma-names = "rx", "tx";
277 status = "disabled";
278 };
279
280 spi@7000d400 {
281 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
282 reg = <0x7000d400 0x200>;
283 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
284 #address-cells = <1>;
285 #size-cells = <0>;
286 clocks = <&tegra_car TEGRA124_CLK_SBC1>;
287 clock-names = "spi";
288 resets = <&tegra_car 41>;
289 reset-names = "spi";
290 dmas = <&apbdma 15>, <&apbdma 15>;
291 dma-names = "rx", "tx";
292 status = "disabled";
293 };
294
295 spi@7000d600 {
296 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
297 reg = <0x7000d600 0x200>;
298 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
299 #address-cells = <1>;
300 #size-cells = <0>;
301 clocks = <&tegra_car TEGRA124_CLK_SBC2>;
302 clock-names = "spi";
303 resets = <&tegra_car 44>;
304 reset-names = "spi";
305 dmas = <&apbdma 16>, <&apbdma 16>;
306 dma-names = "rx", "tx";
307 status = "disabled";
308 };
309
310 spi@7000d800 {
311 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
312 reg = <0x7000d800 0x200>;
313 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
314 #address-cells = <1>;
315 #size-cells = <0>;
316 clocks = <&tegra_car TEGRA124_CLK_SBC3>;
317 clock-names = "spi";
318 resets = <&tegra_car 46>;
319 reset-names = "spi";
320 dmas = <&apbdma 17>, <&apbdma 17>;
321 dma-names = "rx", "tx";
322 status = "disabled";
323 };
324
325 spi@7000da00 {
326 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
327 reg = <0x7000da00 0x200>;
328 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
329 #address-cells = <1>;
330 #size-cells = <0>;
331 clocks = <&tegra_car TEGRA124_CLK_SBC4>;
332 clock-names = "spi";
333 resets = <&tegra_car 68>;
334 reset-names = "spi";
335 dmas = <&apbdma 18>, <&apbdma 18>;
336 dma-names = "rx", "tx";
337 status = "disabled";
338 };
339
340 spi@7000dc00 {
341 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
342 reg = <0x7000dc00 0x200>;
343 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
344 #address-cells = <1>;
345 #size-cells = <0>;
346 clocks = <&tegra_car TEGRA124_CLK_SBC5>;
347 clock-names = "spi";
348 resets = <&tegra_car 104>;
349 reset-names = "spi";
350 dmas = <&apbdma 27>, <&apbdma 27>;
351 dma-names = "rx", "tx";
352 status = "disabled";
353 };
354
355 spi@7000de00 {
356 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
357 reg = <0x7000de00 0x200>;
358 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
359 #address-cells = <1>;
360 #size-cells = <0>;
361 clocks = <&tegra_car TEGRA124_CLK_SBC6>;
362 clock-names = "spi";
363 resets = <&tegra_car 105>;
364 reset-names = "spi";
365 dmas = <&apbdma 28>, <&apbdma 28>;
366 dma-names = "rx", "tx";
95 status = "disabled"; 367 status = "disabled";
96 }; 368 };
97 369
@@ -99,11 +371,157 @@
99 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc"; 371 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
100 reg = <0x7000e000 0x100>; 372 reg = <0x7000e000 0x100>;
101 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 373 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
374 clocks = <&tegra_car TEGRA124_CLK_RTC>;
102 }; 375 };
103 376
104 pmc@7000e400 { 377 pmc@7000e400 {
105 compatible = "nvidia,tegra124-pmc"; 378 compatible = "nvidia,tegra124-pmc";
106 reg = <0x7000e400 0x400>; 379 reg = <0x7000e400 0x400>;
380 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
381 clock-names = "pclk", "clk32k_in";
382 };
383
384 sdhci@700b0000 {
385 compatible = "nvidia,tegra124-sdhci";
386 reg = <0x700b0000 0x200>;
387 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
388 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
389 resets = <&tegra_car 14>;
390 reset-names = "sdhci";
391 status = "disable";
392 };
393
394 sdhci@700b0200 {
395 compatible = "nvidia,tegra124-sdhci";
396 reg = <0x700b0200 0x200>;
397 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
398 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
399 resets = <&tegra_car 9>;
400 reset-names = "sdhci";
401 status = "disable";
402 };
403
404 sdhci@700b0400 {
405 compatible = "nvidia,tegra124-sdhci";
406 reg = <0x700b0400 0x200>;
407 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
408 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
409 resets = <&tegra_car 69>;
410 reset-names = "sdhci";
411 status = "disable";
412 };
413
414 sdhci@700b0600 {
415 compatible = "nvidia,tegra124-sdhci";
416 reg = <0x700b0600 0x200>;
417 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
418 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
419 resets = <&tegra_car 15>;
420 reset-names = "sdhci";
421 status = "disable";
422 };
423
424 ahub@70300000 {
425 compatible = "nvidia,tegra124-ahub";
426 reg = <0x70300000 0x200>,
427 <0x70300800 0x800>,
428 <0x70300200 0x600>;
429 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
430 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
431 <&tegra_car TEGRA124_CLK_APBIF>;
432 clock-names = "d_audio", "apbif";
433 resets = <&tegra_car 106>, /* d_audio */
434 <&tegra_car 107>, /* apbif */
435 <&tegra_car 30>, /* i2s0 */
436 <&tegra_car 11>, /* i2s1 */
437 <&tegra_car 18>, /* i2s2 */
438 <&tegra_car 101>, /* i2s3 */
439 <&tegra_car 102>, /* i2s4 */
440 <&tegra_car 108>, /* dam0 */
441 <&tegra_car 109>, /* dam1 */
442 <&tegra_car 110>, /* dam2 */
443 <&tegra_car 10>, /* spdif */
444 <&tegra_car 153>, /* amx */
445 <&tegra_car 185>, /* amx1 */
446 <&tegra_car 154>, /* adx */
447 <&tegra_car 180>, /* adx1 */
448 <&tegra_car 186>, /* afc0 */
449 <&tegra_car 187>, /* afc1 */
450 <&tegra_car 188>, /* afc2 */
451 <&tegra_car 189>, /* afc3 */
452 <&tegra_car 190>, /* afc4 */
453 <&tegra_car 191>; /* afc5 */
454 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
455 "i2s3", "i2s4", "dam0", "dam1", "dam2",
456 "spdif", "amx", "amx1", "adx", "adx1",
457 "afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
458 dmas = <&apbdma 1>, <&apbdma 1>,
459 <&apbdma 2>, <&apbdma 2>,
460 <&apbdma 3>, <&apbdma 3>,
461 <&apbdma 4>, <&apbdma 4>,
462 <&apbdma 6>, <&apbdma 6>,
463 <&apbdma 7>, <&apbdma 7>,
464 <&apbdma 12>, <&apbdma 12>,
465 <&apbdma 13>, <&apbdma 13>,
466 <&apbdma 14>, <&apbdma 14>,
467 <&apbdma 29>, <&apbdma 29>;
468 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
469 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
470 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
471 "rx9", "tx9";
472 ranges;
473 #address-cells = <1>;
474 #size-cells = <1>;
475
476 tegra_i2s0: i2s@70301000 {
477 compatible = "nvidia,tegra124-i2s";
478 reg = <0x70301000 0x100>;
479 nvidia,ahub-cif-ids = <4 4>;
480 clocks = <&tegra_car TEGRA124_CLK_I2S0>;
481 resets = <&tegra_car 30>;
482 reset-names = "i2s";
483 status = "disabled";
484 };
485
486 tegra_i2s1: i2s@70301100 {
487 compatible = "nvidia,tegra124-i2s";
488 reg = <0x70301100 0x100>;
489 nvidia,ahub-cif-ids = <5 5>;
490 clocks = <&tegra_car TEGRA124_CLK_I2S1>;
491 resets = <&tegra_car 11>;
492 reset-names = "i2s";
493 status = "disabled";
494 };
495
496 tegra_i2s2: i2s@70301200 {
497 compatible = "nvidia,tegra124-i2s";
498 reg = <0x70301200 0x100>;
499 nvidia,ahub-cif-ids = <6 6>;
500 clocks = <&tegra_car TEGRA124_CLK_I2S2>;
501 resets = <&tegra_car 18>;
502 reset-names = "i2s";
503 status = "disabled";
504 };
505
506 tegra_i2s3: i2s@70301300 {
507 compatible = "nvidia,tegra124-i2s";
508 reg = <0x70301300 0x100>;
509 nvidia,ahub-cif-ids = <7 7>;
510 clocks = <&tegra_car TEGRA124_CLK_I2S3>;
511 resets = <&tegra_car 101>;
512 reset-names = "i2s";
513 status = "disabled";
514 };
515
516 tegra_i2s4: i2s@70301400 {
517 compatible = "nvidia,tegra124-i2s";
518 reg = <0x70301400 0x100>;
519 nvidia,ahub-cif-ids = <8 8>;
520 clocks = <&tegra_car TEGRA124_CLK_I2S4>;
521 resets = <&tegra_car 102>;
522 reset-names = "i2s";
523 status = "disabled";
524 };
107 }; 525 };
108 526
109 cpus { 527 cpus {
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
index d5c9bca01232..61bc39335e3a 100644
--- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
@@ -4,12 +4,17 @@
4 model = "Toradex Colibri T20 512MB"; 4 model = "Toradex Colibri T20 512MB";
5 compatible = "toradex,colibri_t20-512", "nvidia,tegra20"; 5 compatible = "toradex,colibri_t20-512", "nvidia,tegra20";
6 6
7 aliases {
8 rtc0 = "/i2c@7000d000/tps6586x@34";
9 rtc1 = "/rtc@7000e000";
10 };
11
7 memory { 12 memory {
8 reg = <0x00000000 0x20000000>; 13 reg = <0x00000000 0x20000000>;
9 }; 14 };
10 15
11 host1x { 16 host1x@50000000 {
12 hdmi { 17 hdmi@54280000 {
13 vdd-supply = <&hdmi_vdd_reg>; 18 vdd-supply = <&hdmi_vdd_reg>;
14 pll-supply = <&hdmi_pll_reg>; 19 pll-supply = <&hdmi_pll_reg>;
15 20
@@ -19,7 +24,7 @@
19 }; 24 };
20 }; 25 };
21 26
22 pinmux { 27 pinmux@70000014 {
23 pinctrl-names = "default"; 28 pinctrl-names = "default";
24 pinctrl-0 = <&state_default>; 29 pinctrl-0 = <&state_default>;
25 30
@@ -27,20 +32,20 @@
27 audio_refclk { 32 audio_refclk {
28 nvidia,pins = "cdev1"; 33 nvidia,pins = "cdev1";
29 nvidia,function = "plla_out"; 34 nvidia,function = "plla_out";
30 nvidia,pull = <0>; 35 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
31 nvidia,tristate = <0>; 36 nvidia,tristate = <TEGRA_PIN_DISABLE>;
32 }; 37 };
33 crt { 38 crt {
34 nvidia,pins = "crtp"; 39 nvidia,pins = "crtp";
35 nvidia,function = "crt"; 40 nvidia,function = "crt";
36 nvidia,pull = <0>; 41 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
37 nvidia,tristate = <1>; 42 nvidia,tristate = <TEGRA_PIN_ENABLE>;
38 }; 43 };
39 dap3 { 44 dap3 {
40 nvidia,pins = "dap3"; 45 nvidia,pins = "dap3";
41 nvidia,function = "dap3"; 46 nvidia,function = "dap3";
42 nvidia,pull = <0>; 47 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
43 nvidia,tristate = <0>; 48 nvidia,tristate = <TEGRA_PIN_DISABLE>;
44 }; 49 };
45 displaya { 50 displaya {
46 nvidia,pins = "ld0", "ld1", "ld2", "ld3", 51 nvidia,pins = "ld0", "ld1", "ld2", "ld3",
@@ -50,155 +55,163 @@
50 "lhs", "lpw0", "lpw2", "lsc0", 55 "lhs", "lpw0", "lpw2", "lsc0",
51 "lsc1", "lsck", "lsda", "lspi", "lvs"; 56 "lsc1", "lsck", "lsda", "lspi", "lvs";
52 nvidia,function = "displaya"; 57 nvidia,function = "displaya";
53 nvidia,tristate = <1>; 58 nvidia,tristate = <TEGRA_PIN_ENABLE>;
54 }; 59 };
55 gpio_dte { 60 gpio_dte {
56 nvidia,pins = "dte"; 61 nvidia,pins = "dte";
57 nvidia,function = "rsvd1"; 62 nvidia,function = "rsvd1";
58 nvidia,pull = <0>; 63 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
59 nvidia,tristate = <0>; 64 nvidia,tristate = <TEGRA_PIN_DISABLE>;
60 }; 65 };
61 gpio_gmi { 66 gpio_gmi {
62 nvidia,pins = "ata", "atc", "atd", "ate", 67 nvidia,pins = "ata", "atc", "atd", "ate",
63 "dap1", "dap2", "dap4", "gpu", "irrx", 68 "dap1", "dap2", "dap4", "gpu", "irrx",
64 "irtx", "spia", "spib", "spic"; 69 "irtx", "spia", "spib", "spic";
65 nvidia,function = "gmi"; 70 nvidia,function = "gmi";
66 nvidia,pull = <0>; 71 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
67 nvidia,tristate = <0>; 72 nvidia,tristate = <TEGRA_PIN_DISABLE>;
68 }; 73 };
69 gpio_pta { 74 gpio_pta {
70 nvidia,pins = "pta"; 75 nvidia,pins = "pta";
71 nvidia,function = "rsvd4"; 76 nvidia,function = "rsvd4";
72 nvidia,pull = <0>; 77 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
73 nvidia,tristate = <0>; 78 nvidia,tristate = <TEGRA_PIN_DISABLE>;
74 }; 79 };
75 gpio_uac { 80 gpio_uac {
76 nvidia,pins = "uac"; 81 nvidia,pins = "uac";
77 nvidia,function = "rsvd2"; 82 nvidia,function = "rsvd2";
78 nvidia,pull = <0>; 83 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
79 nvidia,tristate = <0>; 84 nvidia,tristate = <TEGRA_PIN_DISABLE>;
80 }; 85 };
81 hdint { 86 hdint {
82 nvidia,pins = "hdint"; 87 nvidia,pins = "hdint";
83 nvidia,function = "hdmi"; 88 nvidia,function = "hdmi";
84 nvidia,tristate = <1>; 89 nvidia,tristate = <TEGRA_PIN_ENABLE>;
85 }; 90 };
86 i2c1 { 91 i2c1 {
87 nvidia,pins = "rm"; 92 nvidia,pins = "rm";
88 nvidia,function = "i2c1"; 93 nvidia,function = "i2c1";
89 nvidia,pull = <0>; 94 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
90 nvidia,tristate = <1>; 95 nvidia,tristate = <TEGRA_PIN_ENABLE>;
91 }; 96 };
92 i2c3 { 97 i2c3 {
93 nvidia,pins = "dtf"; 98 nvidia,pins = "dtf";
94 nvidia,function = "i2c3"; 99 nvidia,function = "i2c3";
95 nvidia,pull = <0>; 100 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
96 nvidia,tristate = <1>; 101 nvidia,tristate = <TEGRA_PIN_ENABLE>;
97 }; 102 };
98 i2cddc { 103 i2cddc {
99 nvidia,pins = "ddc"; 104 nvidia,pins = "ddc";
100 nvidia,function = "i2c2"; 105 nvidia,function = "i2c2";
101 nvidia,pull = <2>; 106 nvidia,pull = <TEGRA_PIN_PULL_UP>;
102 nvidia,tristate = <1>; 107 nvidia,tristate = <TEGRA_PIN_ENABLE>;
103 }; 108 };
104 i2cp { 109 i2cp {
105 nvidia,pins = "i2cp"; 110 nvidia,pins = "i2cp";
106 nvidia,function = "i2cp"; 111 nvidia,function = "i2cp";
107 nvidia,pull = <0>; 112 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
108 nvidia,tristate = <0>; 113 nvidia,tristate = <TEGRA_PIN_DISABLE>;
109 }; 114 };
110 irda { 115 irda {
111 nvidia,pins = "uad"; 116 nvidia,pins = "uad";
112 nvidia,function = "irda"; 117 nvidia,function = "irda";
113 nvidia,pull = <0>; 118 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
114 nvidia,tristate = <1>; 119 nvidia,tristate = <TEGRA_PIN_ENABLE>;
115 }; 120 };
116 nand { 121 nand {
117 nvidia,pins = "kbca", "kbcc", "kbcd", 122 nvidia,pins = "kbca", "kbcc", "kbcd",
118 "kbce", "kbcf"; 123 "kbce", "kbcf";
119 nvidia,function = "nand"; 124 nvidia,function = "nand";
120 nvidia,pull = <0>; 125 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
121 nvidia,tristate = <0>; 126 nvidia,tristate = <TEGRA_PIN_DISABLE>;
122 }; 127 };
123 owc { 128 owc {
124 nvidia,pins = "owc"; 129 nvidia,pins = "owc";
125 nvidia,function = "owr"; 130 nvidia,function = "owr";
126 nvidia,pull = <0>; 131 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
127 nvidia,tristate = <1>; 132 nvidia,tristate = <TEGRA_PIN_ENABLE>;
128 }; 133 };
129 pmc { 134 pmc {
130 nvidia,pins = "pmc"; 135 nvidia,pins = "pmc";
131 nvidia,function = "pwr_on"; 136 nvidia,function = "pwr_on";
132 nvidia,tristate = <0>; 137 nvidia,tristate = <TEGRA_PIN_DISABLE>;
133 }; 138 };
134 pwm { 139 pwm {
135 nvidia,pins = "sdb", "sdc", "sdd"; 140 nvidia,pins = "sdb", "sdc", "sdd";
136 nvidia,function = "pwm"; 141 nvidia,function = "pwm";
137 nvidia,tristate = <1>; 142 nvidia,tristate = <TEGRA_PIN_ENABLE>;
138 }; 143 };
139 sdio4 { 144 sdio4 {
140 nvidia,pins = "atb", "gma", "gme"; 145 nvidia,pins = "atb", "gma", "gme";
141 nvidia,function = "sdio4"; 146 nvidia,function = "sdio4";
142 nvidia,pull = <0>; 147 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
143 nvidia,tristate = <1>; 148 nvidia,tristate = <TEGRA_PIN_ENABLE>;
144 }; 149 };
145 spi1 { 150 spi1 {
146 nvidia,pins = "spid", "spie", "spif"; 151 nvidia,pins = "spid", "spie", "spif";
147 nvidia,function = "spi1"; 152 nvidia,function = "spi1";
148 nvidia,pull = <0>; 153 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
149 nvidia,tristate = <1>; 154 nvidia,tristate = <TEGRA_PIN_ENABLE>;
150 }; 155 };
151 spi4 { 156 spi4 {
152 nvidia,pins = "slxa", "slxc", "slxd", "slxk"; 157 nvidia,pins = "slxa", "slxc", "slxd", "slxk";
153 nvidia,function = "spi4"; 158 nvidia,function = "spi4";
154 nvidia,pull = <0>; 159 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
155 nvidia,tristate = <1>; 160 nvidia,tristate = <TEGRA_PIN_ENABLE>;
156 }; 161 };
157 uarta { 162 uarta {
158 nvidia,pins = "sdio1"; 163 nvidia,pins = "sdio1";
159 nvidia,function = "uarta"; 164 nvidia,function = "uarta";
160 nvidia,pull = <0>; 165 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
161 nvidia,tristate = <1>; 166 nvidia,tristate = <TEGRA_PIN_ENABLE>;
162 }; 167 };
163 uartd { 168 uartd {
164 nvidia,pins = "gmc"; 169 nvidia,pins = "gmc";
165 nvidia,function = "uartd"; 170 nvidia,function = "uartd";
166 nvidia,pull = <0>; 171 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
167 nvidia,tristate = <1>; 172 nvidia,tristate = <TEGRA_PIN_ENABLE>;
168 }; 173 };
169 ulpi { 174 ulpi {
170 nvidia,pins = "uaa", "uab", "uda"; 175 nvidia,pins = "uaa", "uab", "uda";
171 nvidia,function = "ulpi"; 176 nvidia,function = "ulpi";
172 nvidia,pull = <0>; 177 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
173 nvidia,tristate = <0>; 178 nvidia,tristate = <TEGRA_PIN_DISABLE>;
174 }; 179 };
175 ulpi_refclk { 180 ulpi_refclk {
176 nvidia,pins = "cdev2"; 181 nvidia,pins = "cdev2";
177 nvidia,function = "pllp_out4"; 182 nvidia,function = "pllp_out4";
178 nvidia,pull = <0>; 183 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
179 nvidia,tristate = <0>; 184 nvidia,tristate = <TEGRA_PIN_DISABLE>;
180 }; 185 };
181 usb_gpio { 186 usb_gpio {
182 nvidia,pins = "spig", "spih"; 187 nvidia,pins = "spig", "spih";
183 nvidia,function = "spi2_alt"; 188 nvidia,function = "spi2_alt";
184 nvidia,pull = <0>; 189 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
185 nvidia,tristate = <0>; 190 nvidia,tristate = <TEGRA_PIN_DISABLE>;
186 }; 191 };
187 vi { 192 vi {
188 nvidia,pins = "dta", "dtb", "dtc", "dtd"; 193 nvidia,pins = "dta", "dtb", "dtc", "dtd";
189 nvidia,function = "vi"; 194 nvidia,function = "vi";
190 nvidia,pull = <0>; 195 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
191 nvidia,tristate = <1>; 196 nvidia,tristate = <TEGRA_PIN_ENABLE>;
192 }; 197 };
193 vi_sc { 198 vi_sc {
194 nvidia,pins = "csus"; 199 nvidia,pins = "csus";
195 nvidia,function = "vi_sensor_clk"; 200 nvidia,function = "vi_sensor_clk";
196 nvidia,pull = <0>; 201 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
197 nvidia,tristate = <1>; 202 nvidia,tristate = <TEGRA_PIN_ENABLE>;
198 }; 203 };
199 }; 204 };
200 }; 205 };
201 206
207 ac97: ac97@70002000 {
208 status = "okay";
209 nvidia,codec-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
210 GPIO_ACTIVE_HIGH>;
211 nvidia,codec-sync-gpio = <&gpio TEGRA_GPIO(P, 0)
212 GPIO_ACTIVE_HIGH>;
213 };
214
202 i2c@7000c000 { 215 i2c@7000c000 {
203 clock-frequency = <400000>; 216 clock-frequency = <400000>;
204 }; 217 };
@@ -225,15 +238,15 @@
225 #gpio-cells = <2>; 238 #gpio-cells = <2>;
226 gpio-controller; 239 gpio-controller;
227 240
228 sys-supply = <&vdd_5v0_reg>; 241 sys-supply = <&vdd_3v3_reg>;
229 vin-sm0-supply = <&sys_reg>; 242 vin-sm0-supply = <&sys_reg>;
230 vin-sm1-supply = <&sys_reg>; 243 vin-sm1-supply = <&sys_reg>;
231 vin-sm2-supply = <&sys_reg>; 244 vin-sm2-supply = <&sys_reg>;
232 vinldo01-supply = <&sm2_reg>; 245 vinldo01-supply = <&sm2_reg>;
233 vinldo23-supply = <&sm2_reg>; 246 vinldo23-supply = <&vdd_3v3_reg>;
234 vinldo4-supply = <&sm2_reg>; 247 vinldo4-supply = <&vdd_3v3_reg>;
235 vinldo678-supply = <&sm2_reg>; 248 vinldo678-supply = <&vdd_3v3_reg>;
236 vinldo9-supply = <&sm2_reg>; 249 vinldo9-supply = <&vdd_3v3_reg>;
237 250
238 regulators { 251 regulators {
239 #address-cells = <1>; 252 #address-cells = <1>;
@@ -250,8 +263,8 @@
250 reg = <1>; 263 reg = <1>;
251 regulator-compatible = "sm0"; 264 regulator-compatible = "sm0";
252 regulator-name = "vdd_sm0,vdd_core"; 265 regulator-name = "vdd_sm0,vdd_core";
253 regulator-min-microvolt = <1275000>; 266 regulator-min-microvolt = <1200000>;
254 regulator-max-microvolt = <1275000>; 267 regulator-max-microvolt = <1200000>;
255 regulator-always-on; 268 regulator-always-on;
256 }; 269 };
257 270
@@ -259,8 +272,8 @@
259 reg = <2>; 272 reg = <2>;
260 regulator-compatible = "sm1"; 273 regulator-compatible = "sm1";
261 regulator-name = "vdd_sm1,vdd_cpu"; 274 regulator-name = "vdd_sm1,vdd_cpu";
262 regulator-min-microvolt = <1100000>; 275 regulator-min-microvolt = <1000000>;
263 regulator-max-microvolt = <1100000>; 276 regulator-max-microvolt = <1000000>;
264 regulator-always-on; 277 regulator-always-on;
265 }; 278 };
266 279
@@ -316,8 +329,8 @@
316 reg = <10>; 329 reg = <10>;
317 regulator-compatible = "ldo6"; 330 regulator-compatible = "ldo6";
318 regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam"; 331 regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
319 regulator-min-microvolt = <1800000>; 332 regulator-min-microvolt = <2850000>;
320 regulator-max-microvolt = <1800000>; 333 regulator-max-microvolt = <2850000>;
321 }; 334 };
322 335
323 hdmi_vdd_reg: regulator@11 { 336 hdmi_vdd_reg: regulator@11 {
@@ -362,7 +375,7 @@
362 }; 375 };
363 }; 376 };
364 377
365 pmc { 378 pmc@7000e400 {
366 nvidia,suspend-mode = <1>; 379 nvidia,suspend-mode = <1>;
367 nvidia,cpu-pwr-good-time = <5000>; 380 nvidia,cpu-pwr-good-time = <5000>;
368 nvidia,cpu-pwr-off-time = <5000>; 381 nvidia,cpu-pwr-off-time = <5000>;
@@ -442,14 +455,6 @@
442 }; 455 };
443 }; 456 };
444 457
445 ac97: ac97 {
446 status = "okay";
447 nvidia,codec-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
448 GPIO_ACTIVE_HIGH>;
449 nvidia,codec-sync-gpio = <&gpio TEGRA_GPIO(P, 0)
450 GPIO_ACTIVE_HIGH>;
451 };
452
453 usb@c5004000 { 458 usb@c5004000 {
454 status = "okay"; 459 status = "okay";
455 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) 460 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
@@ -471,7 +476,7 @@
471 #address-cells = <1>; 476 #address-cells = <1>;
472 #size-cells = <0>; 477 #size-cells = <0>;
473 478
474 clk32k_in: clock { 479 clk32k_in: clock@0 {
475 compatible = "fixed-clock"; 480 compatible = "fixed-clock";
476 reg=<0>; 481 reg=<0>;
477 #clock-cells = <0>; 482 #clock-cells = <0>;
@@ -479,37 +484,17 @@
479 }; 484 };
480 }; 485 };
481 486
482 sound {
483 compatible = "nvidia,tegra-audio-wm9712-colibri_t20",
484 "nvidia,tegra-audio-wm9712";
485 nvidia,model = "Colibri T20 AC97 Audio";
486
487 nvidia,audio-routing =
488 "Headphone", "HPOUTL",
489 "Headphone", "HPOUTR",
490 "LineIn", "LINEINL",
491 "LineIn", "LINEINR",
492 "Mic", "MIC1";
493
494 nvidia,ac97-controller = <&ac97>;
495
496 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
497 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
498 <&tegra_car TEGRA20_CLK_CDEV1>;
499 clock-names = "pll_a", "pll_a_out0", "mclk";
500 };
501
502 regulators { 487 regulators {
503 compatible = "simple-bus"; 488 compatible = "simple-bus";
504 #address-cells = <1>; 489 #address-cells = <1>;
505 #size-cells = <0>; 490 #size-cells = <0>;
506 491
507 vdd_5v0_reg: regulator@100 { 492 vdd_3v3_reg: regulator@100 {
508 compatible = "regulator-fixed"; 493 compatible = "regulator-fixed";
509 reg = <100>; 494 reg = <100>;
510 regulator-name = "vdd_5v0"; 495 regulator-name = "vdd_3v3";
511 regulator-min-microvolt = <5000000>; 496 regulator-min-microvolt = <3300000>;
512 regulator-max-microvolt = <5000000>; 497 regulator-max-microvolt = <3300000>;
513 regulator-always-on; 498 regulator-always-on;
514 }; 499 };
515 500
@@ -525,4 +510,24 @@
525 gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>; 510 gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
526 }; 511 };
527 }; 512 };
513
514 sound {
515 compatible = "nvidia,tegra-audio-wm9712-colibri_t20",
516 "nvidia,tegra-audio-wm9712";
517 nvidia,model = "Colibri T20 AC97 Audio";
518
519 nvidia,audio-routing =
520 "Headphone", "HPOUTL",
521 "Headphone", "HPOUTR",
522 "LineIn", "LINEINL",
523 "LineIn", "LINEINR",
524 "Mic", "MIC1";
525
526 nvidia,ac97-controller = <&ac97>;
527
528 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
529 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
530 <&tegra_car TEGRA20_CLK_CDEV1>;
531 clock-names = "pll_a", "pll_a_out0", "mclk";
532 };
528}; 533};
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
index e156ab30e763..3fb1f50f6d46 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -1,17 +1,31 @@
1/dts-v1/; 1/dts-v1/;
2 2
3#include <dt-bindings/input/input.h>
3#include "tegra20.dtsi" 4#include "tegra20.dtsi"
4 5
5/ { 6/ {
6 model = "NVIDIA Tegra20 Harmony evaluation board"; 7 model = "NVIDIA Tegra20 Harmony evaluation board";
7 compatible = "nvidia,harmony", "nvidia,tegra20"; 8 compatible = "nvidia,harmony", "nvidia,tegra20";
8 9
10 aliases {
11 rtc0 = "/i2c@7000d000/tps6586x@34";
12 rtc1 = "/rtc@7000e000";
13 };
14
9 memory { 15 memory {
10 reg = <0x00000000 0x40000000>; 16 reg = <0x00000000 0x40000000>;
11 }; 17 };
12 18
13 host1x { 19 host1x@50000000 {
14 hdmi { 20 dc@54200000 {
21 rgb {
22 status = "okay";
23
24 nvidia,panel = <&panel>;
25 };
26 };
27
28 hdmi@54280000 {
15 status = "okay"; 29 status = "okay";
16 30
17 vdd-supply = <&hdmi_vdd_reg>; 31 vdd-supply = <&hdmi_vdd_reg>;
@@ -23,7 +37,7 @@
23 }; 37 };
24 }; 38 };
25 39
26 pinmux { 40 pinmux@70000014 {
27 pinctrl-names = "default"; 41 pinctrl-names = "default";
28 pinctrl-0 = <&state_default>; 42 pinctrl-0 = <&state_default>;
29 43
@@ -184,50 +198,50 @@
184 "gmb", "gmc", "gmd", "gme", "gpu7", 198 "gmb", "gmc", "gmd", "gme", "gpu7",
185 "gpv", "i2cp", "pta", "rm", "slxa", 199 "gpv", "i2cp", "pta", "rm", "slxa",
186 "slxk", "spia", "spib", "uac"; 200 "slxk", "spia", "spib", "uac";
187 nvidia,pull = <0>; 201 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
188 nvidia,tristate = <0>; 202 nvidia,tristate = <TEGRA_PIN_DISABLE>;
189 }; 203 };
190 conf_ck32 { 204 conf_ck32 {
191 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", 205 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
192 "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; 206 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
193 nvidia,pull = <0>; 207 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
194 }; 208 };
195 conf_csus { 209 conf_csus {
196 nvidia,pins = "csus", "spid", "spif"; 210 nvidia,pins = "csus", "spid", "spif";
197 nvidia,pull = <1>; 211 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
198 nvidia,tristate = <1>; 212 nvidia,tristate = <TEGRA_PIN_ENABLE>;
199 }; 213 };
200 conf_crtp { 214 conf_crtp {
201 nvidia,pins = "crtp", "dap2", "dap3", "dap4", 215 nvidia,pins = "crtp", "dap2", "dap3", "dap4",
202 "dtc", "dte", "dtf", "gpu", "sdio1", 216 "dtc", "dte", "dtf", "gpu", "sdio1",
203 "slxc", "slxd", "spdi", "spdo", "spig", 217 "slxc", "slxd", "spdi", "spdo", "spig",
204 "uda"; 218 "uda";
205 nvidia,pull = <0>; 219 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
206 nvidia,tristate = <1>; 220 nvidia,tristate = <TEGRA_PIN_ENABLE>;
207 }; 221 };
208 conf_ddc { 222 conf_ddc {
209 nvidia,pins = "ddc", "dta", "dtd", "kbca", 223 nvidia,pins = "ddc", "dta", "dtd", "kbca",
210 "kbcb", "kbcc", "kbcd", "kbce", "kbcf", 224 "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
211 "sdc"; 225 "sdc";
212 nvidia,pull = <2>; 226 nvidia,pull = <TEGRA_PIN_PULL_UP>;
213 nvidia,tristate = <0>; 227 nvidia,tristate = <TEGRA_PIN_DISABLE>;
214 }; 228 };
215 conf_hdint { 229 conf_hdint {
216 nvidia,pins = "hdint", "lcsn", "ldc", "lm1", 230 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
217 "lpw1", "lsc1", "lsck", "lsda", "lsdi", 231 "lpw1", "lsc1", "lsck", "lsda", "lsdi",
218 "lvp0", "owc", "sdb"; 232 "lvp0", "owc", "sdb";
219 nvidia,tristate = <1>; 233 nvidia,tristate = <TEGRA_PIN_ENABLE>;
220 }; 234 };
221 conf_irrx { 235 conf_irrx {
222 nvidia,pins = "irrx", "irtx", "sdd", "spic", 236 nvidia,pins = "irrx", "irtx", "sdd", "spic",
223 "spie", "spih", "uaa", "uab", "uad", 237 "spie", "spih", "uaa", "uab", "uad",
224 "uca", "ucb"; 238 "uca", "ucb";
225 nvidia,pull = <2>; 239 nvidia,pull = <TEGRA_PIN_PULL_UP>;
226 nvidia,tristate = <1>; 240 nvidia,tristate = <TEGRA_PIN_ENABLE>;
227 }; 241 };
228 conf_lc { 242 conf_lc {
229 nvidia,pins = "lc", "ls"; 243 nvidia,pins = "lc", "ls";
230 nvidia,pull = <2>; 244 nvidia,pull = <TEGRA_PIN_PULL_UP>;
231 }; 245 };
232 conf_ld0 { 246 conf_ld0 {
233 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", 247 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
@@ -237,12 +251,12 @@
237 "lhp1", "lhp2", "lhs", "lm0", "lpp", 251 "lhp1", "lhp2", "lhs", "lm0", "lpp",
238 "lpw0", "lpw2", "lsc0", "lspi", "lvp1", 252 "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
239 "lvs", "pmc"; 253 "lvs", "pmc";
240 nvidia,tristate = <0>; 254 nvidia,tristate = <TEGRA_PIN_DISABLE>;
241 }; 255 };
242 conf_ld17_0 { 256 conf_ld17_0 {
243 nvidia,pins = "ld17_0", "ld19_18", "ld21_20", 257 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
244 "ld23_22"; 258 "ld23_22";
245 nvidia,pull = <1>; 259 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
246 }; 260 };
247 }; 261 };
248 }; 262 };
@@ -255,6 +269,10 @@
255 status = "okay"; 269 status = "okay";
256 }; 270 };
257 271
272 pwm: pwm@7000a000 {
273 status = "okay";
274 };
275
258 i2c@7000c000 { 276 i2c@7000c000 {
259 status = "okay"; 277 status = "okay";
260 clock-frequency = <400000>; 278 clock-frequency = <400000>;
@@ -415,7 +433,124 @@
415 }; 433 };
416 }; 434 };
417 435
418 pmc { 436 kbc@7000e200 {
437 status = "okay";
438 nvidia,debounce-delay-ms = <2>;
439 nvidia,repeat-delay-ms = <160>;
440 nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
441 nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
442 linux,keymap = <MATRIX_KEY(0x00, 0x02, KEY_W)
443 MATRIX_KEY(0x00, 0x03, KEY_S)
444 MATRIX_KEY(0x00, 0x04, KEY_A)
445 MATRIX_KEY(0x00, 0x05, KEY_Z)
446 MATRIX_KEY(0x00, 0x07, KEY_FN)
447 MATRIX_KEY(0x01, 0x07, KEY_MENU)
448 MATRIX_KEY(0x02, 0x06, KEY_LEFTALT)
449 MATRIX_KEY(0x02, 0x07, KEY_RIGHTALT)
450 MATRIX_KEY(0x03, 0x00, KEY_5)
451 MATRIX_KEY(0x03, 0x01, KEY_4)
452 MATRIX_KEY(0x03, 0x02, KEY_R)
453 MATRIX_KEY(0x03, 0x03, KEY_E)
454 MATRIX_KEY(0x03, 0x04, KEY_F)
455 MATRIX_KEY(0x03, 0x05, KEY_D)
456 MATRIX_KEY(0x03, 0x06, KEY_X)
457 MATRIX_KEY(0x04, 0x00, KEY_7)
458 MATRIX_KEY(0x04, 0x01, KEY_6)
459 MATRIX_KEY(0x04, 0x02, KEY_T)
460 MATRIX_KEY(0x04, 0x03, KEY_H)
461 MATRIX_KEY(0x04, 0x04, KEY_G)
462 MATRIX_KEY(0x04, 0x05, KEY_V)
463 MATRIX_KEY(0x04, 0x06, KEY_C)
464 MATRIX_KEY(0x04, 0x07, KEY_SPACE)
465 MATRIX_KEY(0x05, 0x00, KEY_9)
466 MATRIX_KEY(0x05, 0x01, KEY_8)
467 MATRIX_KEY(0x05, 0x02, KEY_U)
468 MATRIX_KEY(0x05, 0x03, KEY_Y)
469 MATRIX_KEY(0x05, 0x04, KEY_J)
470 MATRIX_KEY(0x05, 0x05, KEY_N)
471 MATRIX_KEY(0x05, 0x06, KEY_B)
472 MATRIX_KEY(0x05, 0x07, KEY_BACKSLASH)
473 MATRIX_KEY(0x06, 0x00, KEY_MINUS)
474 MATRIX_KEY(0x06, 0x01, KEY_0)
475 MATRIX_KEY(0x06, 0x02, KEY_O)
476 MATRIX_KEY(0x06, 0x03, KEY_I)
477 MATRIX_KEY(0x06, 0x04, KEY_L)
478 MATRIX_KEY(0x06, 0x05, KEY_K)
479 MATRIX_KEY(0x06, 0x06, KEY_COMMA)
480 MATRIX_KEY(0x06, 0x07, KEY_M)
481 MATRIX_KEY(0x07, 0x01, KEY_EQUAL)
482 MATRIX_KEY(0x07, 0x02, KEY_RIGHTBRACE)
483 MATRIX_KEY(0x07, 0x03, KEY_ENTER)
484 MATRIX_KEY(0x07, 0x07, KEY_MENU)
485 MATRIX_KEY(0x08, 0x04, KEY_LEFTSHIFT)
486 MATRIX_KEY(0x08, 0x05, KEY_RIGHTSHIFT)
487 MATRIX_KEY(0x09, 0x05, KEY_LEFTCTRL)
488 MATRIX_KEY(0x09, 0x07, KEY_RIGHTCTRL)
489 MATRIX_KEY(0x0B, 0x00, KEY_LEFTBRACE)
490 MATRIX_KEY(0x0B, 0x01, KEY_P)
491 MATRIX_KEY(0x0B, 0x02, KEY_APOSTROPHE)
492 MATRIX_KEY(0x0B, 0x03, KEY_SEMICOLON)
493 MATRIX_KEY(0x0B, 0x04, KEY_SLASH)
494 MATRIX_KEY(0x0B, 0x05, KEY_DOT)
495 MATRIX_KEY(0x0C, 0x00, KEY_F10)
496 MATRIX_KEY(0x0C, 0x01, KEY_F9)
497 MATRIX_KEY(0x0C, 0x02, KEY_BACKSPACE)
498 MATRIX_KEY(0x0C, 0x03, KEY_3)
499 MATRIX_KEY(0x0C, 0x04, KEY_2)
500 MATRIX_KEY(0x0C, 0x05, KEY_UP)
501 MATRIX_KEY(0x0C, 0x06, KEY_PRINT)
502 MATRIX_KEY(0x0C, 0x07, KEY_PAUSE)
503 MATRIX_KEY(0x0D, 0x00, KEY_INSERT)
504 MATRIX_KEY(0x0D, 0x01, KEY_DELETE)
505 MATRIX_KEY(0x0D, 0x03, KEY_PAGEUP )
506 MATRIX_KEY(0x0D, 0x04, KEY_PAGEDOWN)
507 MATRIX_KEY(0x0D, 0x05, KEY_RIGHT)
508 MATRIX_KEY(0x0D, 0x06, KEY_DOWN)
509 MATRIX_KEY(0x0D, 0x07, KEY_LEFT)
510 MATRIX_KEY(0x0E, 0x00, KEY_F11)
511 MATRIX_KEY(0x0E, 0x01, KEY_F12)
512 MATRIX_KEY(0x0E, 0x02, KEY_F8)
513 MATRIX_KEY(0x0E, 0x03, KEY_Q)
514 MATRIX_KEY(0x0E, 0x04, KEY_F4)
515 MATRIX_KEY(0x0E, 0x05, KEY_F3)
516 MATRIX_KEY(0x0E, 0x06, KEY_1)
517 MATRIX_KEY(0x0E, 0x07, KEY_F7)
518 MATRIX_KEY(0x0F, 0x00, KEY_ESC)
519 MATRIX_KEY(0x0F, 0x01, KEY_GRAVE)
520 MATRIX_KEY(0x0F, 0x02, KEY_F5)
521 MATRIX_KEY(0x0F, 0x03, KEY_TAB)
522 MATRIX_KEY(0x0F, 0x04, KEY_F1)
523 MATRIX_KEY(0x0F, 0x05, KEY_F2)
524 MATRIX_KEY(0x0F, 0x06, KEY_CAPSLOCK)
525 MATRIX_KEY(0x0F, 0x07, KEY_F6)
526 MATRIX_KEY(0x14, 0x00, KEY_KP7)
527 MATRIX_KEY(0x15, 0x00, KEY_KP9)
528 MATRIX_KEY(0x15, 0x01, KEY_KP8)
529 MATRIX_KEY(0x15, 0x02, KEY_KP4)
530 MATRIX_KEY(0x15, 0x04, KEY_KP1)
531 MATRIX_KEY(0x16, 0x01, KEY_KPSLASH)
532 MATRIX_KEY(0x16, 0x02, KEY_KP6)
533 MATRIX_KEY(0x16, 0x03, KEY_KP5)
534 MATRIX_KEY(0x16, 0x04, KEY_KP3)
535 MATRIX_KEY(0x16, 0x05, KEY_KP2)
536 MATRIX_KEY(0x16, 0x07, KEY_KP0)
537 MATRIX_KEY(0x1B, 0x01, KEY_KPASTERISK)
538 MATRIX_KEY(0x1B, 0x03, KEY_KPMINUS)
539 MATRIX_KEY(0x1B, 0x04, KEY_KPPLUS)
540 MATRIX_KEY(0x1B, 0x05, KEY_KPDOT)
541 MATRIX_KEY(0x1C, 0x05, KEY_VOLUMEUP)
542 MATRIX_KEY(0x1D, 0x03, KEY_HOME)
543 MATRIX_KEY(0x1D, 0x04, KEY_END)
544 MATRIX_KEY(0x1D, 0x05, KEY_BRIGHTNESSUP)
545 MATRIX_KEY(0x1D, 0x06, KEY_VOLUMEDOWN)
546 MATRIX_KEY(0x1D, 0x07, KEY_BRIGHTNESSDOWN)
547 MATRIX_KEY(0x1E, 0x00, KEY_NUMLOCK)
548 MATRIX_KEY(0x1E, 0x01, KEY_SCROLLLOCK)
549 MATRIX_KEY(0x1E, 0x02, KEY_MUTE)
550 MATRIX_KEY(0x1F, 0x04, KEY_QUESTION)>;
551 };
552
553 pmc@7000e400 {
419 nvidia,invert-interrupt; 554 nvidia,invert-interrupt;
420 nvidia,suspend-mode = <1>; 555 nvidia,suspend-mode = <1>;
421 nvidia,cpu-pwr-good-time = <5000>; 556 nvidia,cpu-pwr-good-time = <5000>;
@@ -425,7 +560,7 @@
425 nvidia,sys-clock-req-active-high; 560 nvidia,sys-clock-req-active-high;
426 }; 561 };
427 562
428 pcie-controller { 563 pcie-controller@80003000 {
429 pex-clk-supply = <&pci_clk_reg>; 564 pex-clk-supply = <&pci_clk_reg>;
430 vdd-supply = <&pci_vdd_reg>; 565 vdd-supply = <&pci_vdd_reg>;
431 status = "okay"; 566 status = "okay";
@@ -483,12 +618,23 @@
483 bus-width = <8>; 618 bus-width = <8>;
484 }; 619 };
485 620
621 backlight: backlight {
622 compatible = "pwm-backlight";
623
624 enable-gpios = <&gpio TEGRA_GPIO(B, 5) GPIO_ACTIVE_HIGH>;
625 power-supply = <&vdd_bl_reg>;
626 pwms = <&pwm 0 5000000>;
627
628 brightness-levels = <0 4 8 16 32 64 128 255>;
629 default-brightness-level = <6>;
630 };
631
486 clocks { 632 clocks {
487 compatible = "simple-bus"; 633 compatible = "simple-bus";
488 #address-cells = <1>; 634 #address-cells = <1>;
489 #size-cells = <0>; 635 #size-cells = <0>;
490 636
491 clk32k_in: clock { 637 clk32k_in: clock@0 {
492 compatible = "fixed-clock"; 638 compatible = "fixed-clock";
493 reg=<0>; 639 reg=<0>;
494 #clock-cells = <0>; 640 #clock-cells = <0>;
@@ -502,126 +648,18 @@
502 power { 648 power {
503 label = "Power"; 649 label = "Power";
504 gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; 650 gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
505 linux,code = <116>; /* KEY_POWER */ 651 linux,code = <KEY_POWER>;
506 gpio-key,wakeup; 652 gpio-key,wakeup;
507 }; 653 };
508 }; 654 };
509 655
510 kbc { 656 panel: panel {
511 status = "okay"; 657 compatible = "auo,b101aw03", "simple-panel";
512 nvidia,debounce-delay-ms = <2>; 658
513 nvidia,repeat-delay-ms = <160>; 659 power-supply = <&vdd_pnl_reg>;
514 nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>; 660 enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>;
515 nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>; 661
516 linux,keymap = <0x00020011 /* KEY_W */ 662 backlight = <&backlight>;
517 0x0003001F /* KEY_S */
518 0x0004001E /* KEY_A */
519 0x0005002C /* KEY_Z */
520 0x000701D0 /* KEY_FN */
521 0x0107008B /* KEY_MENU */
522 0x02060038 /* KEY_LEFTALT */
523 0x02070064 /* KEY_RIGHTALT */
524 0x03000006 /* KEY_5 */
525 0x03010005 /* KEY_4 */
526 0x03020013 /* KEY_R */
527 0x03030012 /* KEY_E */
528 0x03040021 /* KEY_F */
529 0x03050020 /* KEY_D */
530 0x0306002D /* KEY_X */
531 0x04000008 /* KEY_7 */
532 0x04010007 /* KEY_6 */
533 0x04020014 /* KEY_T */
534 0x04030023 /* KEY_H */
535 0x04040022 /* KEY_G */
536 0x0405002F /* KEY_V */
537 0x0406002E /* KEY_C */
538 0x04070039 /* KEY_SPACE */
539 0x0500000A /* KEY_9 */
540 0x05010009 /* KEY_8 */
541 0x05020016 /* KEY_U */
542 0x05030015 /* KEY_Y */
543 0x05040024 /* KEY_J */
544 0x05050031 /* KEY_N */
545 0x05060030 /* KEY_B */
546 0x0507002B /* KEY_BACKSLASH */
547 0x0600000C /* KEY_MINUS */
548 0x0601000B /* KEY_0 */
549 0x06020018 /* KEY_O */
550 0x06030017 /* KEY_I */
551 0x06040026 /* KEY_L */
552 0x06050025 /* KEY_K */
553 0x06060033 /* KEY_COMMA */
554 0x06070032 /* KEY_M */
555 0x0701000D /* KEY_EQUAL */
556 0x0702001B /* KEY_RIGHTBRACE */
557 0x0703001C /* KEY_ENTER */
558 0x0707008B /* KEY_MENU */
559 0x0804002A /* KEY_LEFTSHIFT */
560 0x08050036 /* KEY_RIGHTSHIFT */
561 0x0905001D /* KEY_LEFTCTRL */
562 0x09070061 /* KEY_RIGHTCTRL */
563 0x0B00001A /* KEY_LEFTBRACE */
564 0x0B010019 /* KEY_P */
565 0x0B020028 /* KEY_APOSTROPHE */
566 0x0B030027 /* KEY_SEMICOLON */
567 0x0B040035 /* KEY_SLASH */
568 0x0B050034 /* KEY_DOT */
569 0x0C000044 /* KEY_F10 */
570 0x0C010043 /* KEY_F9 */
571 0x0C02000E /* KEY_BACKSPACE */
572 0x0C030004 /* KEY_3 */
573 0x0C040003 /* KEY_2 */
574 0x0C050067 /* KEY_UP */
575 0x0C0600D2 /* KEY_PRINT */
576 0x0C070077 /* KEY_PAUSE */
577 0x0D00006E /* KEY_INSERT */
578 0x0D01006F /* KEY_DELETE */
579 0x0D030068 /* KEY_PAGEUP */
580 0x0D04006D /* KEY_PAGEDOWN */
581 0x0D05006A /* KEY_RIGHT */
582 0x0D06006C /* KEY_DOWN */
583 0x0D070069 /* KEY_LEFT */
584 0x0E000057 /* KEY_F11 */
585 0x0E010058 /* KEY_F12 */
586 0x0E020042 /* KEY_F8 */
587 0x0E030010 /* KEY_Q */
588 0x0E04003E /* KEY_F4 */
589 0x0E05003D /* KEY_F3 */
590 0x0E060002 /* KEY_1 */
591 0x0E070041 /* KEY_F7 */
592 0x0F000001 /* KEY_ESC */
593 0x0F010029 /* KEY_GRAVE */
594 0x0F02003F /* KEY_F5 */
595 0x0F03000F /* KEY_TAB */
596 0x0F04003B /* KEY_F1 */
597 0x0F05003C /* KEY_F2 */
598 0x0F06003A /* KEY_CAPSLOCK */
599 0x0F070040 /* KEY_F6 */
600 0x14000047 /* KEY_KP7 */
601 0x15000049 /* KEY_KP9 */
602 0x15010048 /* KEY_KP8 */
603 0x1502004B /* KEY_KP4 */
604 0x1504004F /* KEY_KP1 */
605 0x1601004E /* KEY_KPSLASH */
606 0x1602004D /* KEY_KP6 */
607 0x1603004C /* KEY_KP5 */
608 0x16040051 /* KEY_KP3 */
609 0x16050050 /* KEY_KP2 */
610 0x16070052 /* KEY_KP0 */
611 0x1B010037 /* KEY_KPASTERISK */
612 0x1B03004A /* KEY_KPMINUS */
613 0x1B04004E /* KEY_KPPLUS */
614 0x1B050053 /* KEY_KPDOT */
615 0x1C050073 /* KEY_VOLUMEUP */
616 0x1D030066 /* KEY_HOME */
617 0x1D04006B /* KEY_END */
618 0x1D0500E1 /* KEY_BRIGHTNESSUP */
619 0x1D060072 /* KEY_VOLUMEDOWN */
620 0x1D0700E0 /* KEY_BRIGHTNESSDOWN */
621 0x1E000045 /* KEY_NUMLOCK */
622 0x1E010046 /* KEY_SCROLLLOCK */
623 0x1E020071 /* KEY_MUTE */
624 0x1F0400D6>; /* KEY_QUESTION */
625 }; 663 };
626 664
627 regulators { 665 regulators {
@@ -667,7 +705,7 @@
667 enable-active-high; 705 enable-active-high;
668 }; 706 };
669 707
670 regulator@4 { 708 vdd_pnl_reg: regulator@4 {
671 compatible = "regulator-fixed"; 709 compatible = "regulator-fixed";
672 reg = <4>; 710 reg = <4>;
673 regulator-name = "vdd_pnl"; 711 regulator-name = "vdd_pnl";
@@ -677,7 +715,7 @@
677 enable-active-high; 715 enable-active-high;
678 }; 716 };
679 717
680 regulator@5 { 718 vdd_bl_reg: regulator@5 {
681 compatible = "regulator-fixed"; 719 compatible = "regulator-fixed";
682 reg = <5>; 720 reg = <5>;
683 regulator-name = "vdd_bl"; 721 regulator-name = "vdd_bl";
diff --git a/arch/arm/boot/dts/tegra20-iris-512.dts b/arch/arm/boot/dts/tegra20-iris-512.dts
index f2222bd74eab..8cfb83f42e1f 100644
--- a/arch/arm/boot/dts/tegra20-iris-512.dts
+++ b/arch/arm/boot/dts/tegra20-iris-512.dts
@@ -6,61 +6,61 @@
6 model = "Toradex Colibri T20 512MB on Iris"; 6 model = "Toradex Colibri T20 512MB on Iris";
7 compatible = "toradex,iris", "toradex,colibri_t20-512", "nvidia,tegra20"; 7 compatible = "toradex,iris", "toradex,colibri_t20-512", "nvidia,tegra20";
8 8
9 host1x { 9 host1x@50000000 {
10 hdmi { 10 hdmi@54280000 {
11 status = "okay"; 11 status = "okay";
12 }; 12 };
13 }; 13 };
14 14
15 pinmux { 15 pinmux@70000014 {
16 state_default: pinmux { 16 state_default: pinmux {
17 hdint { 17 hdint {
18 nvidia,tristate = <0>; 18 nvidia,tristate = <TEGRA_PIN_DISABLE>;
19 }; 19 };
20 20
21 i2cddc { 21 i2cddc {
22 nvidia,tristate = <0>; 22 nvidia,tristate = <TEGRA_PIN_DISABLE>;
23 }; 23 };
24 24
25 sdio4 { 25 sdio4 {
26 nvidia,tristate = <0>; 26 nvidia,tristate = <TEGRA_PIN_DISABLE>;
27 }; 27 };
28 28
29 uarta { 29 uarta {
30 nvidia,tristate = <0>; 30 nvidia,tristate = <TEGRA_PIN_DISABLE>;
31 }; 31 };
32 32
33 uartd { 33 uartd {
34 nvidia,tristate = <0>; 34 nvidia,tristate = <TEGRA_PIN_DISABLE>;
35 }; 35 };
36 }; 36 };
37 }; 37 };
38 38
39 usb@c5000000 { 39 serial@70006000 {
40 status = "okay"; 40 status = "okay";
41 }; 41 };
42 42
43 usb-phy@c5000000 { 43 serial@70006300 {
44 status = "okay"; 44 status = "okay";
45 }; 45 };
46 46
47 usb@c5008000 { 47 i2c_ddc: i2c@7000c400 {
48 status = "okay"; 48 status = "okay";
49 }; 49 };
50 50
51 usb-phy@c5008000 { 51 usb@c5000000 {
52 status = "okay"; 52 status = "okay";
53 }; 53 };
54 54
55 serial@70006000 { 55 usb-phy@c5000000 {
56 status = "okay"; 56 status = "okay";
57 }; 57 };
58 58
59 serial@70006300 { 59 usb@c5008000 {
60 status = "okay"; 60 status = "okay";
61 }; 61 };
62 62
63 i2c_ddc: i2c@7000c400 { 63 usb-phy@c5008000 {
64 status = "okay"; 64 status = "okay";
65 }; 65 };
66 66
diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts
index 7580578903cf..6d3a4cbc36cc 100644
--- a/arch/arm/boot/dts/tegra20-medcom-wide.dts
+++ b/arch/arm/boot/dts/tegra20-medcom-wide.dts
@@ -6,7 +6,7 @@
6 model = "Avionic Design Medcom-Wide board"; 6 model = "Avionic Design Medcom-Wide board";
7 compatible = "ad,medcom-wide", "ad,tamonten", "nvidia,tegra20"; 7 compatible = "ad,medcom-wide", "ad,tamonten", "nvidia,tegra20";
8 8
9 pwm { 9 pwm@7000a000 {
10 status = "okay"; 10 status = "okay";
11 }; 11 };
12 12
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index 8d71fc9d8a2f..c7cd8e6802d7 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -1,17 +1,23 @@
1/dts-v1/; 1/dts-v1/;
2 2
3#include <dt-bindings/input/input.h>
3#include "tegra20.dtsi" 4#include "tegra20.dtsi"
4 5
5/ { 6/ {
6 model = "Toshiba AC100 / Dynabook AZ"; 7 model = "Toshiba AC100 / Dynabook AZ";
7 compatible = "compal,paz00", "nvidia,tegra20"; 8 compatible = "compal,paz00", "nvidia,tegra20";
8 9
10 aliases {
11 rtc0 = "/i2c@7000d000/tps6586x@34";
12 rtc1 = "/rtc@7000e000";
13 };
14
9 memory { 15 memory {
10 reg = <0x00000000 0x20000000>; 16 reg = <0x00000000 0x20000000>;
11 }; 17 };
12 18
13 host1x { 19 host1x@50000000 {
14 hdmi { 20 hdmi@54280000 {
15 status = "okay"; 21 status = "okay";
16 22
17 vdd-supply = <&hdmi_vdd_reg>; 23 vdd-supply = <&hdmi_vdd_reg>;
@@ -23,7 +29,7 @@
23 }; 29 };
24 }; 30 };
25 31
26 pinmux { 32 pinmux@70000014 {
27 pinctrl-names = "default"; 33 pinctrl-names = "default";
28 pinctrl-0 = <&state_default>; 34 pinctrl-0 = <&state_default>;
29 35
@@ -177,39 +183,39 @@
177 "gpu", "gpu7", "gpv", "i2cp", "pta", 183 "gpu", "gpu7", "gpv", "i2cp", "pta",
178 "rm", "sdio1", "slxk", "spdo", "uac", 184 "rm", "sdio1", "slxk", "spdo", "uac",
179 "uda"; 185 "uda";
180 nvidia,pull = <0>; 186 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
181 nvidia,tristate = <0>; 187 nvidia,tristate = <TEGRA_PIN_DISABLE>;
182 }; 188 };
183 conf_ck32 { 189 conf_ck32 {
184 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", 190 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
185 "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; 191 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
186 nvidia,pull = <0>; 192 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
187 }; 193 };
188 conf_crtp { 194 conf_crtp {
189 nvidia,pins = "crtp", "dap3", "dap4", "dtb", 195 nvidia,pins = "crtp", "dap3", "dap4", "dtb",
190 "dtc", "dte", "slxa", "slxc", "slxd", 196 "dtc", "dte", "slxa", "slxc", "slxd",
191 "spdi"; 197 "spdi";
192 nvidia,pull = <0>; 198 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
193 nvidia,tristate = <1>; 199 nvidia,tristate = <TEGRA_PIN_ENABLE>;
194 }; 200 };
195 conf_csus { 201 conf_csus {
196 nvidia,pins = "csus", "spia", "spib", "spid", 202 nvidia,pins = "csus", "spia", "spib", "spid",
197 "spif"; 203 "spif";
198 nvidia,pull = <1>; 204 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
199 nvidia,tristate = <1>; 205 nvidia,tristate = <TEGRA_PIN_ENABLE>;
200 }; 206 };
201 conf_ddc { 207 conf_ddc {
202 nvidia,pins = "ddc", "irrx", "irtx", "kbca", 208 nvidia,pins = "ddc", "irrx", "irtx", "kbca",
203 "kbcb", "kbcc", "kbcd", "kbce", "kbcf", 209 "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
204 "spic", "spig", "uaa", "uab"; 210 "spic", "spig", "uaa", "uab";
205 nvidia,pull = <2>; 211 nvidia,pull = <TEGRA_PIN_PULL_UP>;
206 nvidia,tristate = <0>; 212 nvidia,tristate = <TEGRA_PIN_DISABLE>;
207 }; 213 };
208 conf_dta { 214 conf_dta {
209 nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd", 215 nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd",
210 "spie", "spih", "uad", "uca", "ucb"; 216 "spie", "spih", "uad", "uca", "ucb";
211 nvidia,pull = <2>; 217 nvidia,pull = <TEGRA_PIN_PULL_UP>;
212 nvidia,tristate = <1>; 218 nvidia,tristate = <TEGRA_PIN_ENABLE>;
213 }; 219 };
214 conf_hdint { 220 conf_hdint {
215 nvidia,pins = "hdint", "ld0", "ld1", "ld2", 221 nvidia,pins = "hdint", "ld0", "ld1", "ld2",
@@ -218,23 +224,23 @@
218 "ld13", "ld14", "ld15", "ld16", "ld17", 224 "ld13", "ld14", "ld15", "ld16", "ld17",
219 "ldc", "ldi", "lhs", "lsc0", "lspi", 225 "ldc", "ldi", "lhs", "lsc0", "lspi",
220 "lvs", "pmc"; 226 "lvs", "pmc";
221 nvidia,tristate = <0>; 227 nvidia,tristate = <TEGRA_PIN_DISABLE>;
222 }; 228 };
223 conf_lc { 229 conf_lc {
224 nvidia,pins = "lc", "ls"; 230 nvidia,pins = "lc", "ls";
225 nvidia,pull = <2>; 231 nvidia,pull = <TEGRA_PIN_PULL_UP>;
226 }; 232 };
227 conf_lcsn { 233 conf_lcsn {
228 nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2", 234 nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2",
229 "lm0", "lm1", "lpp", "lpw0", "lpw1", 235 "lm0", "lm1", "lpp", "lpw0", "lpw1",
230 "lpw2", "lsc1", "lsck", "lsda", "lsdi", 236 "lpw2", "lsc1", "lsck", "lsda", "lsdi",
231 "lvp0", "lvp1", "sdb"; 237 "lvp0", "lvp1", "sdb";
232 nvidia,tristate = <1>; 238 nvidia,tristate = <TEGRA_PIN_ENABLE>;
233 }; 239 };
234 conf_ld17_0 { 240 conf_ld17_0 {
235 nvidia,pins = "ld17_0", "ld19_18", "ld21_20", 241 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
236 "ld23_22"; 242 "ld23_22";
237 nvidia,pull = <1>; 243 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
238 }; 244 };
239 }; 245 };
240 }; 246 };
@@ -268,7 +274,7 @@
268 clock-frequency = <100000>; 274 clock-frequency = <100000>;
269 }; 275 };
270 276
271 nvec { 277 nvec@7000c500 {
272 compatible = "nvidia,nvec"; 278 compatible = "nvidia,nvec";
273 reg = <0x7000c500 0x100>; 279 reg = <0x7000c500 0x100>;
274 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 280 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
@@ -280,6 +286,8 @@
280 clocks = <&tegra_car TEGRA20_CLK_I2C3>, 286 clocks = <&tegra_car TEGRA20_CLK_I2C3>,
281 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; 287 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
282 clock-names = "div-clk", "fast-clk"; 288 clock-names = "div-clk", "fast-clk";
289 resets = <&tegra_car 67>;
290 reset-names = "i2c";
283 }; 291 };
284 292
285 i2c@7000d000 { 293 i2c@7000d000 {
@@ -415,7 +423,7 @@
415 }; 423 };
416 }; 424 };
417 425
418 pmc { 426 pmc@7000e400 {
419 nvidia,invert-interrupt; 427 nvidia,invert-interrupt;
420 nvidia,suspend-mode = <1>; 428 nvidia,suspend-mode = <1>;
421 nvidia,cpu-pwr-good-time = <2000>; 429 nvidia,cpu-pwr-good-time = <2000>;
@@ -472,7 +480,7 @@
472 #address-cells = <1>; 480 #address-cells = <1>;
473 #size-cells = <0>; 481 #size-cells = <0>;
474 482
475 clk32k_in: clock { 483 clk32k_in: clock@0 {
476 compatible = "fixed-clock"; 484 compatible = "fixed-clock";
477 reg=<0>; 485 reg=<0>;
478 #clock-cells = <0>; 486 #clock-cells = <0>;
@@ -486,7 +494,7 @@
486 power { 494 power {
487 label = "Power"; 495 label = "Power";
488 gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>; 496 gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>;
489 linux,code = <116>; /* KEY_POWER */ 497 linux,code = <KEY_POWER>;
490 gpio-key,wakeup; 498 gpio-key,wakeup;
491 }; 499 };
492 }; 500 };
diff --git a/arch/arm/boot/dts/tegra20-plutux.dts b/arch/arm/boot/dts/tegra20-plutux.dts
index d7a358a6a647..29051a2ae0ae 100644
--- a/arch/arm/boot/dts/tegra20-plutux.dts
+++ b/arch/arm/boot/dts/tegra20-plutux.dts
@@ -6,8 +6,8 @@
6 model = "Avionic Design Plutux board"; 6 model = "Avionic Design Plutux board";
7 compatible = "ad,plutux", "ad,tamonten", "nvidia,tegra20"; 7 compatible = "ad,plutux", "ad,tamonten", "nvidia,tegra20";
8 8
9 host1x { 9 host1x@50000000 {
10 hdmi { 10 hdmi@54280000 {
11 status = "okay"; 11 status = "okay";
12 }; 12 };
13 }; 13 };
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index 315aae26c3cd..a11b6e7b4759 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -1,17 +1,23 @@
1/dts-v1/; 1/dts-v1/;
2 2
3#include <dt-bindings/input/input.h>
3#include "tegra20.dtsi" 4#include "tegra20.dtsi"
4 5
5/ { 6/ {
6 model = "NVIDIA Seaboard"; 7 model = "NVIDIA Seaboard";
7 compatible = "nvidia,seaboard", "nvidia,tegra20"; 8 compatible = "nvidia,seaboard", "nvidia,tegra20";
8 9
10 aliases {
11 rtc0 = "/i2c@7000d000/tps6586x@34";
12 rtc1 = "/rtc@7000e000";
13 };
14
9 memory { 15 memory {
10 reg = <0x00000000 0x40000000>; 16 reg = <0x00000000 0x40000000>;
11 }; 17 };
12 18
13 host1x { 19 host1x@50000000 {
14 hdmi { 20 hdmi@54280000 {
15 status = "okay"; 21 status = "okay";
16 22
17 vdd-supply = <&hdmi_vdd_reg>; 23 vdd-supply = <&hdmi_vdd_reg>;
@@ -23,7 +29,7 @@
23 }; 29 };
24 }; 30 };
25 31
26 pinmux { 32 pinmux@70000014 {
27 pinctrl-names = "default"; 33 pinctrl-names = "default";
28 pinctrl-0 = <&state_default>; 34 pinctrl-0 = <&state_default>;
29 35
@@ -189,53 +195,53 @@
189 "irtx", "pta", "rm", "sdc", "sdd", 195 "irtx", "pta", "rm", "sdc", "sdd",
190 "slxd", "slxk", "spdi", "spdo", "uac", 196 "slxd", "slxk", "spdi", "spdo", "uac",
191 "uad", "uca", "ucb", "uda"; 197 "uad", "uca", "ucb", "uda";
192 nvidia,pull = <0>; 198 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
193 nvidia,tristate = <0>; 199 nvidia,tristate = <TEGRA_PIN_DISABLE>;
194 }; 200 };
195 conf_ate { 201 conf_ate {
196 nvidia,pins = "ate", "csus", "dap3", 202 nvidia,pins = "ate", "csus", "dap3",
197 "gpv", "owc", "slxc", "spib", "spid", 203 "gpv", "owc", "slxc", "spib", "spid",
198 "spie"; 204 "spie";
199 nvidia,pull = <0>; 205 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
200 nvidia,tristate = <1>; 206 nvidia,tristate = <TEGRA_PIN_ENABLE>;
201 }; 207 };
202 conf_ck32 { 208 conf_ck32 {
203 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", 209 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
204 "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; 210 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
205 nvidia,pull = <0>; 211 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
206 }; 212 };
207 conf_crtp { 213 conf_crtp {
208 nvidia,pins = "crtp", "gmb", "slxa", "spia", 214 nvidia,pins = "crtp", "gmb", "slxa", "spia",
209 "spig", "spih"; 215 "spig", "spih";
210 nvidia,pull = <2>; 216 nvidia,pull = <TEGRA_PIN_PULL_UP>;
211 nvidia,tristate = <1>; 217 nvidia,tristate = <TEGRA_PIN_ENABLE>;
212 }; 218 };
213 conf_dta { 219 conf_dta {
214 nvidia,pins = "dta", "dtb", "dtc", "dtd"; 220 nvidia,pins = "dta", "dtb", "dtc", "dtd";
215 nvidia,pull = <1>; 221 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
216 nvidia,tristate = <0>; 222 nvidia,tristate = <TEGRA_PIN_DISABLE>;
217 }; 223 };
218 conf_dte { 224 conf_dte {
219 nvidia,pins = "dte", "spif"; 225 nvidia,pins = "dte", "spif";
220 nvidia,pull = <1>; 226 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
221 nvidia,tristate = <1>; 227 nvidia,tristate = <TEGRA_PIN_ENABLE>;
222 }; 228 };
223 conf_hdint { 229 conf_hdint {
224 nvidia,pins = "hdint", "lcsn", "ldc", "lm1", 230 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
225 "lpw1", "lsc1", "lsck", "lsda", "lsdi", 231 "lpw1", "lsc1", "lsck", "lsda", "lsdi",
226 "lvp0"; 232 "lvp0";
227 nvidia,tristate = <1>; 233 nvidia,tristate = <TEGRA_PIN_ENABLE>;
228 }; 234 };
229 conf_kbca { 235 conf_kbca {
230 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", 236 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
231 "kbce", "kbcf", "sdio1", "spic", "uaa", 237 "kbce", "kbcf", "sdio1", "spic", "uaa",
232 "uab"; 238 "uab";
233 nvidia,pull = <2>; 239 nvidia,pull = <TEGRA_PIN_PULL_UP>;
234 nvidia,tristate = <0>; 240 nvidia,tristate = <TEGRA_PIN_DISABLE>;
235 }; 241 };
236 conf_lc { 242 conf_lc {
237 nvidia,pins = "lc", "ls"; 243 nvidia,pins = "lc", "ls";
238 nvidia,pull = <2>; 244 nvidia,pull = <TEGRA_PIN_PULL_UP>;
239 }; 245 };
240 conf_ld0 { 246 conf_ld0 {
241 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", 247 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
@@ -245,22 +251,22 @@
245 "lhp1", "lhp2", "lhs", "lm0", "lpp", 251 "lhp1", "lhp2", "lhs", "lm0", "lpp",
246 "lpw0", "lpw2", "lsc0", "lspi", "lvp1", 252 "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
247 "lvs", "pmc", "sdb"; 253 "lvs", "pmc", "sdb";
248 nvidia,tristate = <0>; 254 nvidia,tristate = <TEGRA_PIN_DISABLE>;
249 }; 255 };
250 conf_ld17_0 { 256 conf_ld17_0 {
251 nvidia,pins = "ld17_0", "ld19_18", "ld21_20", 257 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
252 "ld23_22"; 258 "ld23_22";
253 nvidia,pull = <1>; 259 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
254 }; 260 };
255 drive_sdio1 { 261 drive_sdio1 {
256 nvidia,pins = "drive_sdio1"; 262 nvidia,pins = "drive_sdio1";
257 nvidia,high-speed-mode = <0>; 263 nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
258 nvidia,schmitt = <0>; 264 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
259 nvidia,low-power-mode = <3>; 265 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
260 nvidia,pull-down-strength = <31>; 266 nvidia,pull-down-strength = <31>;
261 nvidia,pull-up-strength = <31>; 267 nvidia,pull-up-strength = <31>;
262 nvidia,slew-rate-rising = <3>; 268 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
263 nvidia,slew-rate-falling = <3>; 269 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
264 }; 270 };
265 }; 271 };
266 272
@@ -386,6 +392,13 @@
386 status = "okay"; 392 status = "okay";
387 clock-frequency = <400000>; 393 clock-frequency = <400000>;
388 394
395 magnetometer@c {
396 compatible = "ak,ak8975";
397 reg = <0xc>;
398 interrupt-parent = <&gpio>;
399 interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_LEVEL_HIGH>;
400 };
401
389 pmic: tps6586x@34 { 402 pmic: tps6586x@34 {
390 compatible = "ti,tps6586x"; 403 compatible = "ti,tps6586x";
391 reg = <0x34>; 404 reg = <0x34>;
@@ -507,16 +520,149 @@
507 compatible = "onnn,nct1008"; 520 compatible = "onnn,nct1008";
508 reg = <0x4c>; 521 reg = <0x4c>;
509 }; 522 };
523 };
510 524
511 magnetometer@c { 525 kbc@7000e200 {
512 compatible = "ak,ak8975"; 526 status = "okay";
513 reg = <0xc>; 527 nvidia,debounce-delay-ms = <32>;
514 interrupt-parent = <&gpio>; 528 nvidia,repeat-delay-ms = <160>;
515 interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_LEVEL_HIGH>; 529 nvidia,ghost-filter;
516 }; 530 nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
531 nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
532 linux,keymap = <MATRIX_KEY(0x00, 0x02, KEY_W)
533 MATRIX_KEY(0x00, 0x03, KEY_S)
534 MATRIX_KEY(0x00, 0x04, KEY_A)
535 MATRIX_KEY(0x00, 0x05, KEY_Z)
536 MATRIX_KEY(0x00, 0x07, KEY_FN)
537
538 MATRIX_KEY(0x01, 0x07, KEY_LEFTMETA)
539 MATRIX_KEY(0x02, 0x06, KEY_RIGHTALT)
540 MATRIX_KEY(0x02, 0x07, KEY_LEFTALT)
541
542 MATRIX_KEY(0x03, 0x00, KEY_5)
543 MATRIX_KEY(0x03, 0x01, KEY_4)
544 MATRIX_KEY(0x03, 0x02, KEY_R)
545 MATRIX_KEY(0x03, 0x03, KEY_E)
546 MATRIX_KEY(0x03, 0x04, KEY_F)
547 MATRIX_KEY(0x03, 0x05, KEY_D)
548 MATRIX_KEY(0x03, 0x06, KEY_X)
549
550 MATRIX_KEY(0x04, 0x00, KEY_7)
551 MATRIX_KEY(0x04, 0x01, KEY_6)
552 MATRIX_KEY(0x04, 0x02, KEY_T)
553 MATRIX_KEY(0x04, 0x03, KEY_H)
554 MATRIX_KEY(0x04, 0x04, KEY_G)
555 MATRIX_KEY(0x04, 0x05, KEY_V)
556 MATRIX_KEY(0x04, 0x06, KEY_C)
557 MATRIX_KEY(0x04, 0x07, KEY_SPACE)
558
559 MATRIX_KEY(0x05, 0x00, KEY_9)
560 MATRIX_KEY(0x05, 0x01, KEY_8)
561 MATRIX_KEY(0x05, 0x02, KEY_U)
562 MATRIX_KEY(0x05, 0x03, KEY_Y)
563 MATRIX_KEY(0x05, 0x04, KEY_J)
564 MATRIX_KEY(0x05, 0x05, KEY_N)
565 MATRIX_KEY(0x05, 0x06, KEY_B)
566 MATRIX_KEY(0x05, 0x07, KEY_BACKSLASH)
567
568 MATRIX_KEY(0x06, 0x00, KEY_MINUS)
569 MATRIX_KEY(0x06, 0x01, KEY_0)
570 MATRIX_KEY(0x06, 0x02, KEY_O)
571 MATRIX_KEY(0x06, 0x03, KEY_I)
572 MATRIX_KEY(0x06, 0x04, KEY_L)
573 MATRIX_KEY(0x06, 0x05, KEY_K)
574 MATRIX_KEY(0x06, 0x06, KEY_COMMA)
575 MATRIX_KEY(0x06, 0x07, KEY_M)
576
577 MATRIX_KEY(0x07, 0x01, KEY_EQUAL)
578 MATRIX_KEY(0x07, 0x02, KEY_RIGHTBRACE)
579 MATRIX_KEY(0x07, 0x03, KEY_ENTER)
580 MATRIX_KEY(0x07, 0x07, KEY_MENU)
581
582 MATRIX_KEY(0x08, 0x04, KEY_RIGHTSHIFT)
583 MATRIX_KEY(0x08, 0x05, KEY_LEFTSHIFT)
584
585 MATRIX_KEY(0x09, 0x05, KEY_RIGHTCTRL)
586 MATRIX_KEY(0x09, 0x07, KEY_LEFTCTRL)
587
588 MATRIX_KEY(0x0B, 0x00, KEY_LEFTBRACE)
589 MATRIX_KEY(0x0B, 0x01, KEY_P)
590 MATRIX_KEY(0x0B, 0x02, KEY_APOSTROPHE)
591 MATRIX_KEY(0x0B, 0x03, KEY_SEMICOLON)
592 MATRIX_KEY(0x0B, 0x04, KEY_SLASH)
593 MATRIX_KEY(0x0B, 0x05, KEY_DOT)
594
595 MATRIX_KEY(0x0C, 0x00, KEY_F10)
596 MATRIX_KEY(0x0C, 0x01, KEY_F9)
597 MATRIX_KEY(0x0C, 0x02, KEY_BACKSPACE)
598 MATRIX_KEY(0x0C, 0x03, KEY_3)
599 MATRIX_KEY(0x0C, 0x04, KEY_2)
600 MATRIX_KEY(0x0C, 0x05, KEY_UP)
601 MATRIX_KEY(0x0C, 0x06, KEY_PRINT)
602 MATRIX_KEY(0x0C, 0x07, KEY_PAUSE)
603
604 MATRIX_KEY(0x0D, 0x00, KEY_INSERT)
605 MATRIX_KEY(0x0D, 0x01, KEY_DELETE)
606 MATRIX_KEY(0x0D, 0x03, KEY_PAGEUP )
607 MATRIX_KEY(0x0D, 0x04, KEY_PAGEDOWN)
608 MATRIX_KEY(0x0D, 0x05, KEY_RIGHT)
609 MATRIX_KEY(0x0D, 0x06, KEY_DOWN)
610 MATRIX_KEY(0x0D, 0x07, KEY_LEFT)
611
612 MATRIX_KEY(0x0E, 0x00, KEY_F11)
613 MATRIX_KEY(0x0E, 0x01, KEY_F12)
614 MATRIX_KEY(0x0E, 0x02, KEY_F8)
615 MATRIX_KEY(0x0E, 0x03, KEY_Q)
616 MATRIX_KEY(0x0E, 0x04, KEY_F4)
617 MATRIX_KEY(0x0E, 0x05, KEY_F3)
618 MATRIX_KEY(0x0E, 0x06, KEY_1)
619 MATRIX_KEY(0x0E, 0x07, KEY_F7)
620
621 MATRIX_KEY(0x0F, 0x00, KEY_ESC)
622 MATRIX_KEY(0x0F, 0x01, KEY_GRAVE)
623 MATRIX_KEY(0x0F, 0x02, KEY_F5)
624 MATRIX_KEY(0x0F, 0x03, KEY_TAB)
625 MATRIX_KEY(0x0F, 0x04, KEY_F1)
626 MATRIX_KEY(0x0F, 0x05, KEY_F2)
627 MATRIX_KEY(0x0F, 0x06, KEY_CAPSLOCK)
628 MATRIX_KEY(0x0F, 0x07, KEY_F6)
629
630 /* Software Handled Function Keys */
631 MATRIX_KEY(0x14, 0x00, KEY_KP7)
632
633 MATRIX_KEY(0x15, 0x00, KEY_KP9)
634 MATRIX_KEY(0x15, 0x01, KEY_KP8)
635 MATRIX_KEY(0x15, 0x02, KEY_KP4)
636 MATRIX_KEY(0x15, 0x04, KEY_KP1)
637
638 MATRIX_KEY(0x16, 0x01, KEY_KPSLASH)
639 MATRIX_KEY(0x16, 0x02, KEY_KP6)
640 MATRIX_KEY(0x16, 0x03, KEY_KP5)
641 MATRIX_KEY(0x16, 0x04, KEY_KP3)
642 MATRIX_KEY(0x16, 0x05, KEY_KP2)
643 MATRIX_KEY(0x16, 0x07, KEY_KP0)
644
645 MATRIX_KEY(0x1B, 0x01, KEY_KPASTERISK)
646 MATRIX_KEY(0x1B, 0x03, KEY_KPMINUS)
647 MATRIX_KEY(0x1B, 0x04, KEY_KPPLUS)
648 MATRIX_KEY(0x1B, 0x05, KEY_KPDOT)
649
650 MATRIX_KEY(0x1C, 0x05, KEY_VOLUMEUP)
651
652 MATRIX_KEY(0x1D, 0x03, KEY_HOME)
653 MATRIX_KEY(0x1D, 0x04, KEY_END)
654 MATRIX_KEY(0x1D, 0x05, KEY_BRIGHTNESSDOWN)
655 MATRIX_KEY(0x1D, 0x06, KEY_VOLUMEDOWN)
656 MATRIX_KEY(0x1D, 0x07, KEY_BRIGHTNESSUP)
657
658 MATRIX_KEY(0x1E, 0x00, KEY_NUMLOCK)
659 MATRIX_KEY(0x1E, 0x01, KEY_SCROLLLOCK)
660 MATRIX_KEY(0x1E, 0x02, KEY_MUTE)
661
662 MATRIX_KEY(0x1F, 0x04, KEY_HELP)>;
517 }; 663 };
518 664
519 pmc { 665 pmc@7000e400 {
520 nvidia,invert-interrupt; 666 nvidia,invert-interrupt;
521 nvidia,suspend-mode = <1>; 667 nvidia,suspend-mode = <1>;
522 nvidia,cpu-pwr-good-time = <5000>; 668 nvidia,cpu-pwr-good-time = <5000>;
@@ -621,7 +767,7 @@
621 #address-cells = <1>; 767 #address-cells = <1>;
622 #size-cells = <0>; 768 #size-cells = <0>;
623 769
624 clk32k_in: clock { 770 clk32k_in: clock@0 {
625 compatible = "fixed-clock"; 771 compatible = "fixed-clock";
626 reg=<0>; 772 reg=<0>;
627 #clock-cells = <0>; 773 #clock-cells = <0>;
@@ -635,7 +781,7 @@
635 power { 781 power {
636 label = "Power"; 782 label = "Power";
637 gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; 783 gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
638 linux,code = <116>; /* KEY_POWER */ 784 linux,code = <KEY_POWER>;
639 gpio-key,wakeup; 785 gpio-key,wakeup;
640 }; 786 };
641 787
@@ -649,145 +795,6 @@
649 }; 795 };
650 }; 796 };
651 797
652 kbc {
653 status = "okay";
654 nvidia,debounce-delay-ms = <32>;
655 nvidia,repeat-delay-ms = <160>;
656 nvidia,ghost-filter;
657 nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
658 nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
659 linux,keymap = <0x00020011 /* KEY_W */
660 0x0003001F /* KEY_S */
661 0x0004001E /* KEY_A */
662 0x0005002C /* KEY_Z */
663 0x000701d0 /* KEY_FN */
664
665 0x0107007D /* KEY_LEFTMETA */
666 0x02060064 /* KEY_RIGHTALT */
667 0x02070038 /* KEY_LEFTALT */
668
669 0x03000006 /* KEY_5 */
670 0x03010005 /* KEY_4 */
671 0x03020013 /* KEY_R */
672 0x03030012 /* KEY_E */
673 0x03040021 /* KEY_F */
674 0x03050020 /* KEY_D */
675 0x0306002D /* KEY_X */
676
677 0x04000008 /* KEY_7 */
678 0x04010007 /* KEY_6 */
679 0x04020014 /* KEY_T */
680 0x04030023 /* KEY_H */
681 0x04040022 /* KEY_G */
682 0x0405002F /* KEY_V */
683 0x0406002E /* KEY_C */
684 0x04070039 /* KEY_SPACE */
685
686 0x0500000A /* KEY_9 */
687 0x05010009 /* KEY_8 */
688 0x05020016 /* KEY_U */
689 0x05030015 /* KEY_Y */
690 0x05040024 /* KEY_J */
691 0x05050031 /* KEY_N */
692 0x05060030 /* KEY_B */
693 0x0507002B /* KEY_BACKSLASH */
694
695 0x0600000C /* KEY_MINUS */
696 0x0601000B /* KEY_0 */
697 0x06020018 /* KEY_O */
698 0x06030017 /* KEY_I */
699 0x06040026 /* KEY_L */
700 0x06050025 /* KEY_K */
701 0x06060033 /* KEY_COMMA */
702 0x06070032 /* KEY_M */
703
704 0x0701000D /* KEY_EQUAL */
705 0x0702001B /* KEY_RIGHTBRACE */
706 0x0703001C /* KEY_ENTER */
707 0x0707008B /* KEY_MENU */
708
709 0x08040036 /* KEY_RIGHTSHIFT */
710 0x0805002A /* KEY_LEFTSHIFT */
711
712 0x09050061 /* KEY_RIGHTCTRL */
713 0x0907001D /* KEY_LEFTCTRL */
714
715 0x0B00001A /* KEY_LEFTBRACE */
716 0x0B010019 /* KEY_P */
717 0x0B020028 /* KEY_APOSTROPHE */
718 0x0B030027 /* KEY_SEMICOLON */
719 0x0B040035 /* KEY_SLASH */
720 0x0B050034 /* KEY_DOT */
721
722 0x0C000044 /* KEY_F10 */
723 0x0C010043 /* KEY_F9 */
724 0x0C02000E /* KEY_BACKSPACE */
725 0x0C030004 /* KEY_3 */
726 0x0C040003 /* KEY_2 */
727 0x0C050067 /* KEY_UP */
728 0x0C0600D2 /* KEY_PRINT */
729 0x0C070077 /* KEY_PAUSE */
730
731 0x0D00006E /* KEY_INSERT */
732 0x0D01006F /* KEY_DELETE */
733 0x0D030068 /* KEY_PAGEUP */
734 0x0D04006D /* KEY_PAGEDOWN */
735 0x0D05006A /* KEY_RIGHT */
736 0x0D06006C /* KEY_DOWN */
737 0x0D070069 /* KEY_LEFT */
738
739 0x0E000057 /* KEY_F11 */
740 0x0E010058 /* KEY_F12 */
741 0x0E020042 /* KEY_F8 */
742 0x0E030010 /* KEY_Q */
743 0x0E04003E /* KEY_F4 */
744 0x0E05003D /* KEY_F3 */
745 0x0E060002 /* KEY_1 */
746 0x0E070041 /* KEY_F7 */
747
748 0x0F000001 /* KEY_ESC */
749 0x0F010029 /* KEY_GRAVE */
750 0x0F02003F /* KEY_F5 */
751 0x0F03000F /* KEY_TAB */
752 0x0F04003B /* KEY_F1 */
753 0x0F05003C /* KEY_F2 */
754 0x0F06003A /* KEY_CAPSLOCK */
755 0x0F070040 /* KEY_F6 */
756
757 /* Software Handled Function Keys */
758 0x14000047 /* KEY_KP7 */
759
760 0x15000049 /* KEY_KP9 */
761 0x15010048 /* KEY_KP8 */
762 0x1502004B /* KEY_KP4 */
763 0x1504004F /* KEY_KP1 */
764
765 0x1601004E /* KEY_KPSLASH */
766 0x1602004D /* KEY_KP6 */
767 0x1603004C /* KEY_KP5 */
768 0x16040051 /* KEY_KP3 */
769 0x16050050 /* KEY_KP2 */
770 0x16070052 /* KEY_KP0 */
771
772 0x1B010037 /* KEY_KPASTERISK */
773 0x1B03004A /* KEY_KPMINUS */
774 0x1B04004E /* KEY_KPPLUS */
775 0x1B050053 /* KEY_KPDOT */
776
777 0x1C050073 /* KEY_VOLUMEUP */
778
779 0x1D030066 /* KEY_HOME */
780 0x1D04006B /* KEY_END */
781 0x1D0500E0 /* KEY_BRIGHTNESSDOWN */
782 0x1D060072 /* KEY_VOLUMEDOWN */
783 0x1D0700E1 /* KEY_BRIGHTNESSUP */
784
785 0x1E000045 /* KEY_NUMLOCK */
786 0x1E010046 /* KEY_SCROLLLOCK */
787 0x1E020071 /* KEY_MUTE */
788
789 0x1F04008A>; /* KEY_HELP */
790 };
791 regulators { 798 regulators {
792 compatible = "simple-bus"; 799 compatible = "simple-bus";
793 #address-cells = <1>; 800 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi
index 7726dab3d08d..a1b0d965757f 100644
--- a/arch/arm/boot/dts/tegra20-tamonten.dtsi
+++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi
@@ -4,12 +4,17 @@
4 model = "Avionic Design Tamonten SOM"; 4 model = "Avionic Design Tamonten SOM";
5 compatible = "ad,tamonten", "nvidia,tegra20"; 5 compatible = "ad,tamonten", "nvidia,tegra20";
6 6
7 aliases {
8 rtc0 = "/i2c@7000d000/tps6586x@34";
9 rtc1 = "/rtc@7000e000";
10 };
11
7 memory { 12 memory {
8 reg = <0x00000000 0x20000000>; 13 reg = <0x00000000 0x20000000>;
9 }; 14 };
10 15
11 host1x { 16 host1x@50000000 {
12 hdmi { 17 hdmi@54280000 {
13 vdd-supply = <&hdmi_vdd_reg>; 18 vdd-supply = <&hdmi_vdd_reg>;
14 pll-supply = <&hdmi_pll_reg>; 19 pll-supply = <&hdmi_pll_reg>;
15 20
@@ -19,7 +24,7 @@
19 }; 24 };
20 }; 25 };
21 26
22 pinmux { 27 pinmux@70000014 {
23 pinctrl-names = "default"; 28 pinctrl-names = "default";
24 pinctrl-0 = <&state_default>; 29 pinctrl-0 = <&state_default>;
25 30
@@ -176,50 +181,50 @@
176 "gmb", "gmc", "gmd", "gme", "gpu7", 181 "gmb", "gmc", "gmd", "gme", "gpu7",
177 "gpv", "i2cp", "pta", "rm", "slxa", 182 "gpv", "i2cp", "pta", "rm", "slxa",
178 "slxk", "spia", "spib", "uac"; 183 "slxk", "spia", "spib", "uac";
179 nvidia,pull = <0>; 184 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
180 nvidia,tristate = <0>; 185 nvidia,tristate = <TEGRA_PIN_DISABLE>;
181 }; 186 };
182 conf_ck32 { 187 conf_ck32 {
183 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", 188 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
184 "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; 189 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
185 nvidia,pull = <0>; 190 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
186 }; 191 };
187 conf_csus { 192 conf_csus {
188 nvidia,pins = "csus", "spid", "spif"; 193 nvidia,pins = "csus", "spid", "spif";
189 nvidia,pull = <1>; 194 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
190 nvidia,tristate = <1>; 195 nvidia,tristate = <TEGRA_PIN_ENABLE>;
191 }; 196 };
192 conf_crtp { 197 conf_crtp {
193 nvidia,pins = "crtp", "dap2", "dap3", "dap4", 198 nvidia,pins = "crtp", "dap2", "dap3", "dap4",
194 "dtc", "dte", "dtf", "gpu", "sdio1", 199 "dtc", "dte", "dtf", "gpu", "sdio1",
195 "slxc", "slxd", "spdi", "spdo", "spig", 200 "slxc", "slxd", "spdi", "spdo", "spig",
196 "uda"; 201 "uda";
197 nvidia,pull = <0>; 202 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
198 nvidia,tristate = <1>; 203 nvidia,tristate = <TEGRA_PIN_ENABLE>;
199 }; 204 };
200 conf_ddc { 205 conf_ddc {
201 nvidia,pins = "ddc", "dta", "dtd", "kbca", 206 nvidia,pins = "ddc", "dta", "dtd", "kbca",
202 "kbcb", "kbcc", "kbcd", "kbce", "kbcf", 207 "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
203 "sdc"; 208 "sdc";
204 nvidia,pull = <2>; 209 nvidia,pull = <TEGRA_PIN_PULL_UP>;
205 nvidia,tristate = <0>; 210 nvidia,tristate = <TEGRA_PIN_DISABLE>;
206 }; 211 };
207 conf_hdint { 212 conf_hdint {
208 nvidia,pins = "hdint", "lcsn", "ldc", "lm1", 213 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
209 "lpw1", "lsc1", "lsck", "lsda", "lsdi", 214 "lpw1", "lsc1", "lsck", "lsda", "lsdi",
210 "lvp0", "owc", "sdb"; 215 "lvp0", "owc", "sdb";
211 nvidia,tristate = <1>; 216 nvidia,tristate = <TEGRA_PIN_ENABLE>;
212 }; 217 };
213 conf_irrx { 218 conf_irrx {
214 nvidia,pins = "irrx", "irtx", "sdd", "spic", 219 nvidia,pins = "irrx", "irtx", "sdd", "spic",
215 "spie", "spih", "uaa", "uab", "uad", 220 "spie", "spih", "uaa", "uab", "uad",
216 "uca", "ucb"; 221 "uca", "ucb";
217 nvidia,pull = <2>; 222 nvidia,pull = <TEGRA_PIN_PULL_UP>;
218 nvidia,tristate = <1>; 223 nvidia,tristate = <TEGRA_PIN_ENABLE>;
219 }; 224 };
220 conf_lc { 225 conf_lc {
221 nvidia,pins = "lc", "ls"; 226 nvidia,pins = "lc", "ls";
222 nvidia,pull = <2>; 227 nvidia,pull = <TEGRA_PIN_PULL_UP>;
223 }; 228 };
224 conf_ld0 { 229 conf_ld0 {
225 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", 230 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
@@ -229,12 +234,12 @@
229 "lhp1", "lhp2", "lhs", "lm0", "lpp", 234 "lhp1", "lhp2", "lhs", "lm0", "lpp",
230 "lpw0", "lpw2", "lsc0", "lspi", "lvp1", 235 "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
231 "lvs", "pmc"; 236 "lvs", "pmc";
232 nvidia,tristate = <0>; 237 nvidia,tristate = <TEGRA_PIN_DISABLE>;
233 }; 238 };
234 conf_ld17_0 { 239 conf_ld17_0 {
235 nvidia,pins = "ld17_0", "ld19_18", "ld21_20", 240 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
236 "ld23_22"; 241 "ld23_22";
237 nvidia,pull = <1>; 242 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
238 }; 243 };
239 }; 244 };
240 245
@@ -457,7 +462,7 @@
457 }; 462 };
458 }; 463 };
459 464
460 pmc { 465 pmc@7000e400 {
461 nvidia,invert-interrupt; 466 nvidia,invert-interrupt;
462 nvidia,suspend-mode = <1>; 467 nvidia,suspend-mode = <1>;
463 nvidia,cpu-pwr-good-time = <5000>; 468 nvidia,cpu-pwr-good-time = <5000>;
@@ -467,7 +472,7 @@
467 nvidia,sys-clock-req-active-high; 472 nvidia,sys-clock-req-active-high;
468 }; 473 };
469 474
470 pcie-controller { 475 pcie-controller@80003000 {
471 pex-clk-supply = <&pci_clk_reg>; 476 pex-clk-supply = <&pci_clk_reg>;
472 vdd-supply = <&pci_vdd_reg>; 477 vdd-supply = <&pci_vdd_reg>;
473 }; 478 };
@@ -492,7 +497,7 @@
492 #address-cells = <1>; 497 #address-cells = <1>;
493 #size-cells = <0>; 498 #size-cells = <0>;
494 499
495 clk32k_in: clock { 500 clk32k_in: clock@0 {
496 compatible = "fixed-clock"; 501 compatible = "fixed-clock";
497 reg=<0>; 502 reg=<0>;
498 #clock-cells = <0>; 503 #clock-cells = <0>;
diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dts
index 3ada3cb67f07..890562c667fb 100644
--- a/arch/arm/boot/dts/tegra20-tec.dts
+++ b/arch/arm/boot/dts/tegra20-tec.dts
@@ -6,8 +6,8 @@
6 model = "Avionic Design Tamonten Evaluation Carrier"; 6 model = "Avionic Design Tamonten Evaluation Carrier";
7 compatible = "ad,tec", "ad,tamonten", "nvidia,tegra20"; 7 compatible = "ad,tec", "ad,tamonten", "nvidia,tegra20";
8 8
9 host1x { 9 host1x@50000000 {
10 hdmi { 10 hdmi@54280000 {
11 status = "okay"; 11 status = "okay";
12 }; 12 };
13 }; 13 };
@@ -32,7 +32,7 @@
32 }; 32 };
33 }; 33 };
34 34
35 pcie-controller { 35 pcie-controller@80003000 {
36 status = "okay"; 36 status = "okay";
37 37
38 pci@1,0 { 38 pci@1,0 {
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts
index 78deea5c0d21..216fa6d50c65 100644
--- a/arch/arm/boot/dts/tegra20-trimslice.dts
+++ b/arch/arm/boot/dts/tegra20-trimslice.dts
@@ -1,17 +1,23 @@
1/dts-v1/; 1/dts-v1/;
2 2
3#include <dt-bindings/input/input.h>
3#include "tegra20.dtsi" 4#include "tegra20.dtsi"
4 5
5/ { 6/ {
6 model = "Compulab TrimSlice board"; 7 model = "Compulab TrimSlice board";
7 compatible = "compulab,trimslice", "nvidia,tegra20"; 8 compatible = "compulab,trimslice", "nvidia,tegra20";
8 9
10 aliases {
11 rtc0 = "/i2c@7000c500/rtc@56";
12 rtc1 = "/rtc@7000e000";
13 };
14
9 memory { 15 memory {
10 reg = <0x00000000 0x40000000>; 16 reg = <0x00000000 0x40000000>;
11 }; 17 };
12 18
13 host1x { 19 host1x@50000000 {
14 hdmi { 20 hdmi@54280000 {
15 status = "okay"; 21 status = "okay";
16 22
17 vdd-supply = <&hdmi_vdd_reg>; 23 vdd-supply = <&hdmi_vdd_reg>;
@@ -23,7 +29,7 @@
23 }; 29 };
24 }; 30 };
25 31
26 pinmux { 32 pinmux@70000014 {
27 pinctrl-names = "default"; 33 pinctrl-names = "default";
28 pinctrl-0 = <&state_default>; 34 pinctrl-0 = <&state_default>;
29 35
@@ -191,49 +197,49 @@
191 "dtb", "dtc", "dtd", "dte", "gmb", 197 "dtb", "dtc", "dtd", "dte", "gmb",
192 "gme", "i2cp", "pta", "slxc", "slxd", 198 "gme", "i2cp", "pta", "slxc", "slxd",
193 "spdi", "spdo", "uda"; 199 "spdi", "spdo", "uda";
194 nvidia,pull = <0>; 200 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
195 nvidia,tristate = <1>; 201 nvidia,tristate = <TEGRA_PIN_ENABLE>;
196 }; 202 };
197 conf_atb { 203 conf_atb {
198 nvidia,pins = "atb", "cdev1", "cdev2", "dap1", 204 nvidia,pins = "atb", "cdev1", "cdev2", "dap1",
199 "gma", "gmc", "gmd", "gpu", "gpu7", 205 "gma", "gmc", "gmd", "gpu", "gpu7",
200 "gpv", "sdio1", "slxa", "slxk", "uac"; 206 "gpv", "sdio1", "slxa", "slxk", "uac";
201 nvidia,pull = <0>; 207 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
202 nvidia,tristate = <0>; 208 nvidia,tristate = <TEGRA_PIN_DISABLE>;
203 }; 209 };
204 conf_ck32 { 210 conf_ck32 {
205 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", 211 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
206 "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; 212 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
207 nvidia,pull = <0>; 213 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
208 }; 214 };
209 conf_csus { 215 conf_csus {
210 nvidia,pins = "csus", "spia", "spib", 216 nvidia,pins = "csus", "spia", "spib",
211 "spid", "spif"; 217 "spid", "spif";
212 nvidia,pull = <1>; 218 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
213 nvidia,tristate = <1>; 219 nvidia,tristate = <TEGRA_PIN_ENABLE>;
214 }; 220 };
215 conf_ddc { 221 conf_ddc {
216 nvidia,pins = "ddc", "dtf", "rm", "sdc", "sdd"; 222 nvidia,pins = "ddc", "dtf", "rm", "sdc", "sdd";
217 nvidia,pull = <2>; 223 nvidia,pull = <TEGRA_PIN_PULL_UP>;
218 nvidia,tristate = <0>; 224 nvidia,tristate = <TEGRA_PIN_DISABLE>;
219 }; 225 };
220 conf_hdint { 226 conf_hdint {
221 nvidia,pins = "hdint", "lcsn", "ldc", "lm1", 227 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
222 "lpw1", "lsc1", "lsck", "lsda", "lsdi", 228 "lpw1", "lsc1", "lsck", "lsda", "lsdi",
223 "lvp0", "pmc"; 229 "lvp0", "pmc";
224 nvidia,tristate = <1>; 230 nvidia,tristate = <TEGRA_PIN_ENABLE>;
225 }; 231 };
226 conf_irrx { 232 conf_irrx {
227 nvidia,pins = "irrx", "irtx", "kbca", "kbcb", 233 nvidia,pins = "irrx", "irtx", "kbca", "kbcb",
228 "kbcc", "kbcd", "kbce", "kbcf", "owc", 234 "kbcc", "kbcd", "kbce", "kbcf", "owc",
229 "spic", "spie", "spig", "spih", "uaa", 235 "spic", "spie", "spig", "spih", "uaa",
230 "uab", "uad", "uca", "ucb"; 236 "uab", "uad", "uca", "ucb";
231 nvidia,pull = <2>; 237 nvidia,pull = <TEGRA_PIN_PULL_UP>;
232 nvidia,tristate = <1>; 238 nvidia,tristate = <TEGRA_PIN_ENABLE>;
233 }; 239 };
234 conf_lc { 240 conf_lc {
235 nvidia,pins = "lc", "ls"; 241 nvidia,pins = "lc", "ls";
236 nvidia,pull = <2>; 242 nvidia,pull = <TEGRA_PIN_PULL_UP>;
237 }; 243 };
238 conf_ld0 { 244 conf_ld0 {
239 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", 245 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
@@ -243,17 +249,17 @@
243 "lhp1", "lhp2", "lhs", "lm0", "lpp", 249 "lhp1", "lhp2", "lhs", "lm0", "lpp",
244 "lpw0", "lpw2", "lsc0", "lspi", "lvp1", 250 "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
245 "lvs", "sdb"; 251 "lvs", "sdb";
246 nvidia,tristate = <0>; 252 nvidia,tristate = <TEGRA_PIN_DISABLE>;
247 }; 253 };
248 conf_ld17_0 { 254 conf_ld17_0 {
249 nvidia,pins = "ld17_0", "ld19_18", "ld21_20", 255 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
250 "ld23_22"; 256 "ld23_22";
251 nvidia,pull = <1>; 257 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
252 }; 258 };
253 conf_spif { 259 conf_spif {
254 nvidia,pins = "spif"; 260 nvidia,pins = "spif";
255 nvidia,pull = <1>; 261 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
256 nvidia,tristate = <0>; 262 nvidia,tristate = <TEGRA_PIN_DISABLE>;
257 }; 263 };
258 }; 264 };
259 }; 265 };
@@ -301,7 +307,7 @@
301 }; 307 };
302 }; 308 };
303 309
304 pmc { 310 pmc@7000e400 {
305 nvidia,suspend-mode = <1>; 311 nvidia,suspend-mode = <1>;
306 nvidia,cpu-pwr-good-time = <5000>; 312 nvidia,cpu-pwr-good-time = <5000>;
307 nvidia,cpu-pwr-off-time = <5000>; 313 nvidia,cpu-pwr-off-time = <5000>;
@@ -310,7 +316,7 @@
310 nvidia,sys-clock-req-active-high; 316 nvidia,sys-clock-req-active-high;
311 }; 317 };
312 318
313 pcie-controller { 319 pcie-controller@80003000 {
314 status = "okay"; 320 status = "okay";
315 pex-clk-supply = <&pci_clk_reg>; 321 pex-clk-supply = <&pci_clk_reg>;
316 vdd-supply = <&pci_vdd_reg>; 322 vdd-supply = <&pci_vdd_reg>;
@@ -366,7 +372,7 @@
366 #address-cells = <1>; 372 #address-cells = <1>;
367 #size-cells = <0>; 373 #size-cells = <0>;
368 374
369 clk32k_in: clock { 375 clk32k_in: clock@0 {
370 compatible = "fixed-clock"; 376 compatible = "fixed-clock";
371 reg=<0>; 377 reg=<0>;
372 #clock-cells = <0>; 378 #clock-cells = <0>;
@@ -380,7 +386,7 @@
380 power { 386 power {
381 label = "Power"; 387 label = "Power";
382 gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>; 388 gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>;
383 linux,code = <116>; /* KEY_POWER */ 389 linux,code = <KEY_POWER>;
384 gpio-key,wakeup; 390 gpio-key,wakeup;
385 }; 391 };
386 }; 392 };
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index aab872cd0530..571d12e6ac2d 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -1,17 +1,23 @@
1/dts-v1/; 1/dts-v1/;
2 2
3#include <dt-bindings/input/input.h>
3#include "tegra20.dtsi" 4#include "tegra20.dtsi"
4 5
5/ { 6/ {
6 model = "NVIDIA Tegra20 Ventana evaluation board"; 7 model = "NVIDIA Tegra20 Ventana evaluation board";
7 compatible = "nvidia,ventana", "nvidia,tegra20"; 8 compatible = "nvidia,ventana", "nvidia,tegra20";
8 9
10 aliases {
11 rtc0 = "/i2c@7000d000/tps6586x@34";
12 rtc1 = "/rtc@7000e000";
13 };
14
9 memory { 15 memory {
10 reg = <0x00000000 0x40000000>; 16 reg = <0x00000000 0x40000000>;
11 }; 17 };
12 18
13 host1x { 19 host1x@50000000 {
14 hdmi { 20 hdmi@54280000 {
15 status = "okay"; 21 status = "okay";
16 22
17 vdd-supply = <&hdmi_vdd_reg>; 23 vdd-supply = <&hdmi_vdd_reg>;
@@ -23,7 +29,7 @@
23 }; 29 };
24 }; 30 };
25 31
26 pinmux { 32 pinmux@70000014 {
27 pinctrl-names = "default"; 33 pinctrl-names = "default";
28 pinctrl-0 = <&state_default>; 34 pinctrl-0 = <&state_default>;
29 35
@@ -189,50 +195,50 @@
189 "irtx", "pta", "rm", "sdc", "sdd", 195 "irtx", "pta", "rm", "sdc", "sdd",
190 "slxc", "slxd", "slxk", "spdi", "spdo", 196 "slxc", "slxd", "slxk", "spdi", "spdo",
191 "uac", "uad", "uca", "ucb", "uda"; 197 "uac", "uad", "uca", "ucb", "uda";
192 nvidia,pull = <0>; 198 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
193 nvidia,tristate = <0>; 199 nvidia,tristate = <TEGRA_PIN_DISABLE>;
194 }; 200 };
195 conf_ate { 201 conf_ate {
196 nvidia,pins = "ate", "csus", "dap3", "gmd", 202 nvidia,pins = "ate", "csus", "dap3", "gmd",
197 "gpv", "owc", "spia", "spib", "spic", 203 "gpv", "owc", "spia", "spib", "spic",
198 "spid", "spie", "spig"; 204 "spid", "spie", "spig";
199 nvidia,pull = <0>; 205 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
200 nvidia,tristate = <1>; 206 nvidia,tristate = <TEGRA_PIN_ENABLE>;
201 }; 207 };
202 conf_ck32 { 208 conf_ck32 {
203 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", 209 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
204 "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; 210 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
205 nvidia,pull = <0>; 211 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
206 }; 212 };
207 conf_crtp { 213 conf_crtp {
208 nvidia,pins = "crtp", "gmb", "slxa", "spih"; 214 nvidia,pins = "crtp", "gmb", "slxa", "spih";
209 nvidia,pull = <2>; 215 nvidia,pull = <TEGRA_PIN_PULL_UP>;
210 nvidia,tristate = <1>; 216 nvidia,tristate = <TEGRA_PIN_ENABLE>;
211 }; 217 };
212 conf_dta { 218 conf_dta {
213 nvidia,pins = "dta", "dtb", "dtc", "dtd"; 219 nvidia,pins = "dta", "dtb", "dtc", "dtd";
214 nvidia,pull = <1>; 220 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
215 nvidia,tristate = <0>; 221 nvidia,tristate = <TEGRA_PIN_DISABLE>;
216 }; 222 };
217 conf_dte { 223 conf_dte {
218 nvidia,pins = "dte", "spif"; 224 nvidia,pins = "dte", "spif";
219 nvidia,pull = <1>; 225 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
220 nvidia,tristate = <1>; 226 nvidia,tristate = <TEGRA_PIN_ENABLE>;
221 }; 227 };
222 conf_hdint { 228 conf_hdint {
223 nvidia,pins = "hdint", "lcsn", "ldc", "lm1", 229 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
224 "lpw1", "lsck", "lsda", "lsdi", "lvp0"; 230 "lpw1", "lsck", "lsda", "lsdi", "lvp0";
225 nvidia,tristate = <1>; 231 nvidia,tristate = <TEGRA_PIN_ENABLE>;
226 }; 232 };
227 conf_kbca { 233 conf_kbca {
228 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", 234 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
229 "kbce", "kbcf", "sdio1", "uaa", "uab"; 235 "kbce", "kbcf", "sdio1", "uaa", "uab";
230 nvidia,pull = <2>; 236 nvidia,pull = <TEGRA_PIN_PULL_UP>;
231 nvidia,tristate = <0>; 237 nvidia,tristate = <TEGRA_PIN_DISABLE>;
232 }; 238 };
233 conf_lc { 239 conf_lc {
234 nvidia,pins = "lc", "ls"; 240 nvidia,pins = "lc", "ls";
235 nvidia,pull = <2>; 241 nvidia,pull = <TEGRA_PIN_PULL_UP>;
236 }; 242 };
237 conf_ld0 { 243 conf_ld0 {
238 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", 244 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
@@ -242,22 +248,22 @@
242 "lhp1", "lhp2", "lhs", "lm0", "lpp", 248 "lhp1", "lhp2", "lhs", "lm0", "lpp",
243 "lpw0", "lpw2", "lsc0", "lsc1", "lspi", 249 "lpw0", "lpw2", "lsc0", "lsc1", "lspi",
244 "lvp1", "lvs", "pmc", "sdb"; 250 "lvp1", "lvs", "pmc", "sdb";
245 nvidia,tristate = <0>; 251 nvidia,tristate = <TEGRA_PIN_DISABLE>;
246 }; 252 };
247 conf_ld17_0 { 253 conf_ld17_0 {
248 nvidia,pins = "ld17_0", "ld19_18", "ld21_20", 254 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
249 "ld23_22"; 255 "ld23_22";
250 nvidia,pull = <1>; 256 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
251 }; 257 };
252 drive_sdio1 { 258 drive_sdio1 {
253 nvidia,pins = "drive_sdio1"; 259 nvidia,pins = "drive_sdio1";
254 nvidia,high-speed-mode = <0>; 260 nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
255 nvidia,schmitt = <1>; 261 nvidia,schmitt = <TEGRA_PIN_ENABLE>;
256 nvidia,low-power-mode = <3>; 262 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
257 nvidia,pull-down-strength = <31>; 263 nvidia,pull-down-strength = <31>;
258 nvidia,pull-up-strength = <31>; 264 nvidia,pull-up-strength = <31>;
259 nvidia,slew-rate-rising = <3>; 265 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
260 nvidia,slew-rate-falling = <3>; 266 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
261 }; 267 };
262 }; 268 };
263 269
@@ -492,7 +498,7 @@
492 }; 498 };
493 }; 499 };
494 500
495 pmc { 501 pmc@7000e400 {
496 nvidia,invert-interrupt; 502 nvidia,invert-interrupt;
497 nvidia,suspend-mode = <1>; 503 nvidia,suspend-mode = <1>;
498 nvidia,cpu-pwr-good-time = <2000>; 504 nvidia,cpu-pwr-good-time = <2000>;
@@ -556,7 +562,7 @@
556 #address-cells = <1>; 562 #address-cells = <1>;
557 #size-cells = <0>; 563 #size-cells = <0>;
558 564
559 clk32k_in: clock { 565 clk32k_in: clock@0 {
560 compatible = "fixed-clock"; 566 compatible = "fixed-clock";
561 reg=<0>; 567 reg=<0>;
562 #clock-cells = <0>; 568 #clock-cells = <0>;
@@ -570,7 +576,7 @@
570 power { 576 power {
571 label = "Power"; 577 label = "Power";
572 gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; 578 gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
573 linux,code = <116>; /* KEY_POWER */ 579 linux,code = <KEY_POWER>;
574 gpio-key,wakeup; 580 gpio-key,wakeup;
575 }; 581 };
576 }; 582 };
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts
index d33a73cf167c..1843725785c9 100644
--- a/arch/arm/boot/dts/tegra20-whistler.dts
+++ b/arch/arm/boot/dts/tegra20-whistler.dts
@@ -1,17 +1,23 @@
1/dts-v1/; 1/dts-v1/;
2 2
3#include <dt-bindings/input/input.h>
3#include "tegra20.dtsi" 4#include "tegra20.dtsi"
4 5
5/ { 6/ {
6 model = "NVIDIA Tegra20 Whistler evaluation board"; 7 model = "NVIDIA Tegra20 Whistler evaluation board";
7 compatible = "nvidia,whistler", "nvidia,tegra20"; 8 compatible = "nvidia,whistler", "nvidia,tegra20";
8 9
10 aliases {
11 rtc0 = "/i2c@7000d000/max8907@3c";
12 rtc1 = "/rtc@7000e000";
13 };
14
9 memory { 15 memory {
10 reg = <0x00000000 0x20000000>; 16 reg = <0x00000000 0x20000000>;
11 }; 17 };
12 18
13 host1x { 19 host1x@50000000 {
14 hdmi { 20 hdmi@54280000 {
15 status = "okay"; 21 status = "okay";
16 22
17 vdd-supply = <&hdmi_vdd_reg>; 23 vdd-supply = <&hdmi_vdd_reg>;
@@ -23,7 +29,7 @@
23 }; 29 };
24 }; 30 };
25 31
26 pinmux { 32 pinmux@70000014 {
27 pinctrl-names = "default"; 33 pinctrl-names = "default";
28 pinctrl-0 = <&state_default>; 34 pinctrl-0 = <&state_default>;
29 35
@@ -189,8 +195,8 @@
189 "kbcf", "sdc", "sdd", "spie", "spig", 195 "kbcf", "sdc", "sdd", "spie", "spig",
190 "spih", "uaa", "uab", "uad", "uca", 196 "spih", "uaa", "uab", "uad", "uca",
191 "ucb"; 197 "ucb";
192 nvidia,pull = <2>; 198 nvidia,pull = <TEGRA_PIN_PULL_UP>;
193 nvidia,tristate = <0>; 199 nvidia,tristate = <TEGRA_PIN_DISABLE>;
194 }; 200 };
195 conf_atd { 201 conf_atd {
196 nvidia,pins = "atd", "ate", "cdev1", "csus", 202 nvidia,pins = "atd", "ate", "cdev1", "csus",
@@ -198,54 +204,54 @@
198 "dtf", "gpu", "gpu7", "gpv", "i2cp", 204 "dtf", "gpu", "gpu7", "gpv", "i2cp",
199 "rm", "sdio1", "slxa", "slxc", "slxd", 205 "rm", "sdio1", "slxa", "slxc", "slxd",
200 "slxk", "spdi", "spdo", "uac", "uda"; 206 "slxk", "spdi", "spdo", "uac", "uda";
201 nvidia,pull = <0>; 207 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
202 nvidia,tristate = <0>; 208 nvidia,tristate = <TEGRA_PIN_DISABLE>;
203 }; 209 };
204 conf_cdev2 { 210 conf_cdev2 {
205 nvidia,pins = "cdev2", "spia", "spib"; 211 nvidia,pins = "cdev2", "spia", "spib";
206 nvidia,pull = <1>; 212 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
207 nvidia,tristate = <1>; 213 nvidia,tristate = <TEGRA_PIN_ENABLE>;
208 }; 214 };
209 conf_ck32 { 215 conf_ck32 {
210 nvidia,pins = "ck32", "ddrc", "lc", "pmca", 216 nvidia,pins = "ck32", "ddrc", "lc", "pmca",
211 "pmcb", "pmcc", "pmcd", "xm2c", 217 "pmcb", "pmcc", "pmcd", "xm2c",
212 "xm2d"; 218 "xm2d";
213 nvidia,pull = <0>; 219 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
214 }; 220 };
215 conf_crtp { 221 conf_crtp {
216 nvidia,pins = "crtp"; 222 nvidia,pins = "crtp";
217 nvidia,pull = <0>; 223 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
218 nvidia,tristate = <1>; 224 nvidia,tristate = <TEGRA_PIN_ENABLE>;
219 }; 225 };
220 conf_dta { 226 conf_dta {
221 nvidia,pins = "dta", "dtb", "dtc", "dtd", 227 nvidia,pins = "dta", "dtb", "dtc", "dtd",
222 "spid", "spif"; 228 "spid", "spif";
223 nvidia,pull = <1>; 229 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
224 nvidia,tristate = <0>; 230 nvidia,tristate = <TEGRA_PIN_DISABLE>;
225 }; 231 };
226 conf_gme { 232 conf_gme {
227 nvidia,pins = "gme", "owc", "pta", "spic"; 233 nvidia,pins = "gme", "owc", "pta", "spic";
228 nvidia,pull = <2>; 234 nvidia,pull = <TEGRA_PIN_PULL_UP>;
229 nvidia,tristate = <1>; 235 nvidia,tristate = <TEGRA_PIN_ENABLE>;
230 }; 236 };
231 conf_ld17_0 { 237 conf_ld17_0 {
232 nvidia,pins = "ld17_0", "ld19_18", "ld21_20", 238 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
233 "ld23_22"; 239 "ld23_22";
234 nvidia,pull = <1>; 240 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
235 }; 241 };
236 conf_ls { 242 conf_ls {
237 nvidia,pins = "ls", "pmce"; 243 nvidia,pins = "ls", "pmce";
238 nvidia,pull = <2>; 244 nvidia,pull = <TEGRA_PIN_PULL_UP>;
239 }; 245 };
240 drive_dap1 { 246 drive_dap1 {
241 nvidia,pins = "drive_dap1"; 247 nvidia,pins = "drive_dap1";
242 nvidia,high-speed-mode = <0>; 248 nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
243 nvidia,schmitt = <1>; 249 nvidia,schmitt = <TEGRA_PIN_ENABLE>;
244 nvidia,low-power-mode = <0>; 250 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_8>;
245 nvidia,pull-down-strength = <0>; 251 nvidia,pull-down-strength = <0>;
246 nvidia,pull-up-strength = <0>; 252 nvidia,pull-up-strength = <0>;
247 nvidia,slew-rate-rising = <0>; 253 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
248 nvidia,slew-rate-falling = <0>; 254 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
249 }; 255 };
250 }; 256 };
251 }; 257 };
@@ -495,7 +501,20 @@
495 }; 501 };
496 }; 502 };
497 503
498 pmc { 504 kbc@7000e200 {
505 status = "okay";
506 nvidia,debounce-delay-ms = <20>;
507 nvidia,repeat-delay-ms = <160>;
508 nvidia,kbc-row-pins = <0 1 2>;
509 nvidia,kbc-col-pins = <16 17>;
510 nvidia,wakeup-source;
511 linux,keymap = <MATRIX_KEY(0x00, 0x00, KEY_POWER)
512 MATRIX_KEY(0x01, 0x00, KEY_HOME)
513 MATRIX_KEY(0x01, 0x01, KEY_BACK)
514 MATRIX_KEY(0x02, 0x01, KEY_MENU)>;
515 };
516
517 pmc@7000e400 {
499 nvidia,invert-interrupt; 518 nvidia,invert-interrupt;
500 nvidia,suspend-mode = <1>; 519 nvidia,suspend-mode = <1>;
501 nvidia,cpu-pwr-good-time = <2000>; 520 nvidia,cpu-pwr-good-time = <2000>;
@@ -543,7 +562,7 @@
543 #address-cells = <1>; 562 #address-cells = <1>;
544 #size-cells = <0>; 563 #size-cells = <0>;
545 564
546 clk32k_in: clock { 565 clk32k_in: clock@0 {
547 compatible = "fixed-clock"; 566 compatible = "fixed-clock";
548 reg=<0>; 567 reg=<0>;
549 #clock-cells = <0>; 568 #clock-cells = <0>;
@@ -551,25 +570,12 @@
551 }; 570 };
552 }; 571 };
553 572
554 kbc {
555 status = "okay";
556 nvidia,debounce-delay-ms = <20>;
557 nvidia,repeat-delay-ms = <160>;
558 nvidia,kbc-row-pins = <0 1 2>;
559 nvidia,kbc-col-pins = <16 17>;
560 nvidia,wakeup-source;
561 linux,keymap = <0x00000074 /* KEY_POWER */
562 0x01000066 /* KEY_HOME */
563 0x0101009E /* KEY_BACK */
564 0x0201008B>; /* KEY_MENU */
565 };
566
567 regulators { 573 regulators {
568 compatible = "simple-bus"; 574 compatible = "simple-bus";
569 #address-cells = <1>; 575 #address-cells = <1>;
570 #size-cells = <0>; 576 #size-cells = <0>;
571 577
572 usb0_vbus_reg: regulator { 578 usb0_vbus_reg: regulator@0 {
573 compatible = "regulator-fixed"; 579 compatible = "regulator-fixed";
574 reg = <0>; 580 reg = <0>;
575 regulator-name = "usb0_vbus"; 581 regulator-name = "usb0_vbus";
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index df40b54fd8bc..480ecda3416b 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -1,5 +1,6 @@
1#include <dt-bindings/clock/tegra20-car.h> 1#include <dt-bindings/clock/tegra20-car.h>
2#include <dt-bindings/gpio/tegra-gpio.h> 2#include <dt-bindings/gpio/tegra-gpio.h>
3#include <dt-bindings/pinctrl/pinctrl-tegra.h>
3#include <dt-bindings/interrupt-controller/arm-gic.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h>
4 5
5#include "skeleton.dtsi" 6#include "skeleton.dtsi"
@@ -16,57 +17,71 @@
16 serial4 = &uarte; 17 serial4 = &uarte;
17 }; 18 };
18 19
19 host1x { 20 host1x@50000000 {
20 compatible = "nvidia,tegra20-host1x", "simple-bus"; 21 compatible = "nvidia,tegra20-host1x", "simple-bus";
21 reg = <0x50000000 0x00024000>; 22 reg = <0x50000000 0x00024000>;
22 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 23 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
23 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 24 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
24 clocks = <&tegra_car TEGRA20_CLK_HOST1X>; 25 clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
26 resets = <&tegra_car 28>;
27 reset-names = "host1x";
25 28
26 #address-cells = <1>; 29 #address-cells = <1>;
27 #size-cells = <1>; 30 #size-cells = <1>;
28 31
29 ranges = <0x54000000 0x54000000 0x04000000>; 32 ranges = <0x54000000 0x54000000 0x04000000>;
30 33
31 mpe { 34 mpe@54040000 {
32 compatible = "nvidia,tegra20-mpe"; 35 compatible = "nvidia,tegra20-mpe";
33 reg = <0x54040000 0x00040000>; 36 reg = <0x54040000 0x00040000>;
34 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 37 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
35 clocks = <&tegra_car TEGRA20_CLK_MPE>; 38 clocks = <&tegra_car TEGRA20_CLK_MPE>;
39 resets = <&tegra_car 60>;
40 reset-names = "mpe";
36 }; 41 };
37 42
38 vi { 43 vi@54080000 {
39 compatible = "nvidia,tegra20-vi"; 44 compatible = "nvidia,tegra20-vi";
40 reg = <0x54080000 0x00040000>; 45 reg = <0x54080000 0x00040000>;
41 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 46 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
42 clocks = <&tegra_car TEGRA20_CLK_VI>; 47 clocks = <&tegra_car TEGRA20_CLK_VI>;
48 resets = <&tegra_car 20>;
49 reset-names = "vi";
43 }; 50 };
44 51
45 epp { 52 epp@540c0000 {
46 compatible = "nvidia,tegra20-epp"; 53 compatible = "nvidia,tegra20-epp";
47 reg = <0x540c0000 0x00040000>; 54 reg = <0x540c0000 0x00040000>;
48 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 55 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
49 clocks = <&tegra_car TEGRA20_CLK_EPP>; 56 clocks = <&tegra_car TEGRA20_CLK_EPP>;
57 resets = <&tegra_car 19>;
58 reset-names = "epp";
50 }; 59 };
51 60
52 isp { 61 isp@54100000 {
53 compatible = "nvidia,tegra20-isp"; 62 compatible = "nvidia,tegra20-isp";
54 reg = <0x54100000 0x00040000>; 63 reg = <0x54100000 0x00040000>;
55 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 64 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
56 clocks = <&tegra_car TEGRA20_CLK_ISP>; 65 clocks = <&tegra_car TEGRA20_CLK_ISP>;
66 resets = <&tegra_car 23>;
67 reset-names = "isp";
57 }; 68 };
58 69
59 gr2d { 70 gr2d@54140000 {
60 compatible = "nvidia,tegra20-gr2d"; 71 compatible = "nvidia,tegra20-gr2d";
61 reg = <0x54140000 0x00040000>; 72 reg = <0x54140000 0x00040000>;
62 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 73 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
63 clocks = <&tegra_car TEGRA20_CLK_GR2D>; 74 clocks = <&tegra_car TEGRA20_CLK_GR2D>;
75 resets = <&tegra_car 21>;
76 reset-names = "2d";
64 }; 77 };
65 78
66 gr3d { 79 gr3d@54140000 {
67 compatible = "nvidia,tegra20-gr3d"; 80 compatible = "nvidia,tegra20-gr3d";
68 reg = <0x54180000 0x00040000>; 81 reg = <0x54140000 0x00040000>;
69 clocks = <&tegra_car TEGRA20_CLK_GR3D>; 82 clocks = <&tegra_car TEGRA20_CLK_GR3D>;
83 resets = <&tegra_car 24>;
84 reset-names = "3d";
70 }; 85 };
71 86
72 dc@54200000 { 87 dc@54200000 {
@@ -75,7 +90,9 @@
75 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 90 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
76 clocks = <&tegra_car TEGRA20_CLK_DISP1>, 91 clocks = <&tegra_car TEGRA20_CLK_DISP1>,
77 <&tegra_car TEGRA20_CLK_PLL_P>; 92 <&tegra_car TEGRA20_CLK_PLL_P>;
78 clock-names = "disp1", "parent"; 93 clock-names = "dc", "parent";
94 resets = <&tegra_car 27>;
95 reset-names = "dc";
79 96
80 rgb { 97 rgb {
81 status = "disabled"; 98 status = "disabled";
@@ -88,24 +105,28 @@
88 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 105 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
89 clocks = <&tegra_car TEGRA20_CLK_DISP2>, 106 clocks = <&tegra_car TEGRA20_CLK_DISP2>,
90 <&tegra_car TEGRA20_CLK_PLL_P>; 107 <&tegra_car TEGRA20_CLK_PLL_P>;
91 clock-names = "disp2", "parent"; 108 clock-names = "dc", "parent";
109 resets = <&tegra_car 26>;
110 reset-names = "dc";
92 111
93 rgb { 112 rgb {
94 status = "disabled"; 113 status = "disabled";
95 }; 114 };
96 }; 115 };
97 116
98 hdmi { 117 hdmi@54280000 {
99 compatible = "nvidia,tegra20-hdmi"; 118 compatible = "nvidia,tegra20-hdmi";
100 reg = <0x54280000 0x00040000>; 119 reg = <0x54280000 0x00040000>;
101 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 120 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
102 clocks = <&tegra_car TEGRA20_CLK_HDMI>, 121 clocks = <&tegra_car TEGRA20_CLK_HDMI>,
103 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; 122 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
104 clock-names = "hdmi", "parent"; 123 clock-names = "hdmi", "parent";
124 resets = <&tegra_car 51>;
125 reset-names = "hdmi";
105 status = "disabled"; 126 status = "disabled";
106 }; 127 };
107 128
108 tvo { 129 tvo@542c0000 {
109 compatible = "nvidia,tegra20-tvo"; 130 compatible = "nvidia,tegra20-tvo";
110 reg = <0x542c0000 0x00040000>; 131 reg = <0x542c0000 0x00040000>;
111 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 132 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
@@ -113,10 +134,12 @@
113 status = "disabled"; 134 status = "disabled";
114 }; 135 };
115 136
116 dsi { 137 dsi@542c0000 {
117 compatible = "nvidia,tegra20-dsi"; 138 compatible = "nvidia,tegra20-dsi";
118 reg = <0x54300000 0x00040000>; 139 reg = <0x542c0000 0x00040000>;
119 clocks = <&tegra_car TEGRA20_CLK_DSI>; 140 clocks = <&tegra_car TEGRA20_CLK_DSI>;
141 resets = <&tegra_car 48>;
142 reset-names = "dsi";
120 status = "disabled"; 143 status = "disabled";
121 }; 144 };
122 }; 145 };
@@ -129,7 +152,7 @@
129 clocks = <&tegra_car TEGRA20_CLK_TWD>; 152 clocks = <&tegra_car TEGRA20_CLK_TWD>;
130 }; 153 };
131 154
132 intc: interrupt-controller { 155 intc: interrupt-controller@50041000 {
133 compatible = "arm,cortex-a9-gic"; 156 compatible = "arm,cortex-a9-gic";
134 reg = <0x50041000 0x1000 157 reg = <0x50041000 0x1000
135 0x50040100 0x0100>; 158 0x50040100 0x0100>;
@@ -137,7 +160,7 @@
137 #interrupt-cells = <3>; 160 #interrupt-cells = <3>;
138 }; 161 };
139 162
140 cache-controller { 163 cache-controller@50043000 {
141 compatible = "arm,pl310-cache"; 164 compatible = "arm,pl310-cache";
142 reg = <0x50043000 0x1000>; 165 reg = <0x50043000 0x1000>;
143 arm,data-latency = <5 5 2>; 166 arm,data-latency = <5 5 2>;
@@ -156,13 +179,14 @@
156 clocks = <&tegra_car TEGRA20_CLK_TIMER>; 179 clocks = <&tegra_car TEGRA20_CLK_TIMER>;
157 }; 180 };
158 181
159 tegra_car: clock { 182 tegra_car: clock@60006000 {
160 compatible = "nvidia,tegra20-car"; 183 compatible = "nvidia,tegra20-car";
161 reg = <0x60006000 0x1000>; 184 reg = <0x60006000 0x1000>;
162 #clock-cells = <1>; 185 #clock-cells = <1>;
186 #reset-cells = <1>;
163 }; 187 };
164 188
165 apbdma: dma { 189 apbdma: dma@6000a000 {
166 compatible = "nvidia,tegra20-apbdma"; 190 compatible = "nvidia,tegra20-apbdma";
167 reg = <0x6000a000 0x1200>; 191 reg = <0x6000a000 0x1200>;
168 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 192 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
@@ -182,14 +206,17 @@
182 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
183 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 207 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
184 clocks = <&tegra_car TEGRA20_CLK_APBDMA>; 208 clocks = <&tegra_car TEGRA20_CLK_APBDMA>;
209 resets = <&tegra_car 34>;
210 reset-names = "dma";
211 #dma-cells = <1>;
185 }; 212 };
186 213
187 ahb { 214 ahb@6000c004 {
188 compatible = "nvidia,tegra20-ahb"; 215 compatible = "nvidia,tegra20-ahb";
189 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */ 216 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
190 }; 217 };
191 218
192 gpio: gpio { 219 gpio: gpio@6000d000 {
193 compatible = "nvidia,tegra20-gpio"; 220 compatible = "nvidia,tegra20-gpio";
194 reg = <0x6000d000 0x1000>; 221 reg = <0x6000d000 0x1000>;
195 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 222 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
@@ -205,7 +232,7 @@
205 interrupt-controller; 232 interrupt-controller;
206 }; 233 };
207 234
208 pinmux: pinmux { 235 pinmux: pinmux@70000014 {
209 compatible = "nvidia,tegra20-pinmux"; 236 compatible = "nvidia,tegra20-pinmux";
210 reg = <0x70000014 0x10 /* Tri-state registers */ 237 reg = <0x70000014 0x10 /* Tri-state registers */
211 0x70000080 0x20 /* Mux registers */ 238 0x70000080 0x20 /* Mux registers */
@@ -213,17 +240,20 @@
213 0x70000868 0xa8>; /* Pad control registers */ 240 0x70000868 0xa8>; /* Pad control registers */
214 }; 241 };
215 242
216 das { 243 das@70000c00 {
217 compatible = "nvidia,tegra20-das"; 244 compatible = "nvidia,tegra20-das";
218 reg = <0x70000c00 0x80>; 245 reg = <0x70000c00 0x80>;
219 }; 246 };
220 247
221 tegra_ac97: ac97 { 248 tegra_ac97: ac97@70002000 {
222 compatible = "nvidia,tegra20-ac97"; 249 compatible = "nvidia,tegra20-ac97";
223 reg = <0x70002000 0x200>; 250 reg = <0x70002000 0x200>;
224 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 251 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
225 nvidia,dma-request-selector = <&apbdma 12>;
226 clocks = <&tegra_car TEGRA20_CLK_AC97>; 252 clocks = <&tegra_car TEGRA20_CLK_AC97>;
253 resets = <&tegra_car 3>;
254 reset-names = "ac97";
255 dmas = <&apbdma 12>, <&apbdma 12>;
256 dma-names = "rx", "tx";
227 status = "disabled"; 257 status = "disabled";
228 }; 258 };
229 259
@@ -231,8 +261,11 @@
231 compatible = "nvidia,tegra20-i2s"; 261 compatible = "nvidia,tegra20-i2s";
232 reg = <0x70002800 0x200>; 262 reg = <0x70002800 0x200>;
233 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 263 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
234 nvidia,dma-request-selector = <&apbdma 2>;
235 clocks = <&tegra_car TEGRA20_CLK_I2S1>; 264 clocks = <&tegra_car TEGRA20_CLK_I2S1>;
265 resets = <&tegra_car 11>;
266 reset-names = "i2s";
267 dmas = <&apbdma 2>, <&apbdma 2>;
268 dma-names = "rx", "tx";
236 status = "disabled"; 269 status = "disabled";
237 }; 270 };
238 271
@@ -240,8 +273,11 @@
240 compatible = "nvidia,tegra20-i2s"; 273 compatible = "nvidia,tegra20-i2s";
241 reg = <0x70002a00 0x200>; 274 reg = <0x70002a00 0x200>;
242 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 275 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
243 nvidia,dma-request-selector = <&apbdma 1>;
244 clocks = <&tegra_car TEGRA20_CLK_I2S2>; 276 clocks = <&tegra_car TEGRA20_CLK_I2S2>;
277 resets = <&tegra_car 18>;
278 reset-names = "i2s";
279 dmas = <&apbdma 1>, <&apbdma 1>;
280 dma-names = "rx", "tx";
245 status = "disabled"; 281 status = "disabled";
246 }; 282 };
247 283
@@ -257,8 +293,11 @@
257 reg = <0x70006000 0x40>; 293 reg = <0x70006000 0x40>;
258 reg-shift = <2>; 294 reg-shift = <2>;
259 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 295 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
260 nvidia,dma-request-selector = <&apbdma 8>;
261 clocks = <&tegra_car TEGRA20_CLK_UARTA>; 296 clocks = <&tegra_car TEGRA20_CLK_UARTA>;
297 resets = <&tegra_car 6>;
298 reset-names = "serial";
299 dmas = <&apbdma 8>, <&apbdma 8>;
300 dma-names = "rx", "tx";
262 status = "disabled"; 301 status = "disabled";
263 }; 302 };
264 303
@@ -267,8 +306,11 @@
267 reg = <0x70006040 0x40>; 306 reg = <0x70006040 0x40>;
268 reg-shift = <2>; 307 reg-shift = <2>;
269 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 308 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
270 nvidia,dma-request-selector = <&apbdma 9>;
271 clocks = <&tegra_car TEGRA20_CLK_UARTB>; 309 clocks = <&tegra_car TEGRA20_CLK_UARTB>;
310 resets = <&tegra_car 7>;
311 reset-names = "serial";
312 dmas = <&apbdma 9>, <&apbdma 9>;
313 dma-names = "rx", "tx";
272 status = "disabled"; 314 status = "disabled";
273 }; 315 };
274 316
@@ -277,8 +319,11 @@
277 reg = <0x70006200 0x100>; 319 reg = <0x70006200 0x100>;
278 reg-shift = <2>; 320 reg-shift = <2>;
279 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 321 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
280 nvidia,dma-request-selector = <&apbdma 10>;
281 clocks = <&tegra_car TEGRA20_CLK_UARTC>; 322 clocks = <&tegra_car TEGRA20_CLK_UARTC>;
323 resets = <&tegra_car 55>;
324 reset-names = "serial";
325 dmas = <&apbdma 10>, <&apbdma 10>;
326 dma-names = "rx", "tx";
282 status = "disabled"; 327 status = "disabled";
283 }; 328 };
284 329
@@ -287,8 +332,11 @@
287 reg = <0x70006300 0x100>; 332 reg = <0x70006300 0x100>;
288 reg-shift = <2>; 333 reg-shift = <2>;
289 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 334 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
290 nvidia,dma-request-selector = <&apbdma 19>;
291 clocks = <&tegra_car TEGRA20_CLK_UARTD>; 335 clocks = <&tegra_car TEGRA20_CLK_UARTD>;
336 resets = <&tegra_car 65>;
337 reset-names = "serial";
338 dmas = <&apbdma 19>, <&apbdma 19>;
339 dma-names = "rx", "tx";
292 status = "disabled"; 340 status = "disabled";
293 }; 341 };
294 342
@@ -297,20 +345,25 @@
297 reg = <0x70006400 0x100>; 345 reg = <0x70006400 0x100>;
298 reg-shift = <2>; 346 reg-shift = <2>;
299 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 347 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
300 nvidia,dma-request-selector = <&apbdma 20>;
301 clocks = <&tegra_car TEGRA20_CLK_UARTE>; 348 clocks = <&tegra_car TEGRA20_CLK_UARTE>;
349 resets = <&tegra_car 66>;
350 reset-names = "serial";
351 dmas = <&apbdma 20>, <&apbdma 20>;
352 dma-names = "rx", "tx";
302 status = "disabled"; 353 status = "disabled";
303 }; 354 };
304 355
305 pwm: pwm { 356 pwm: pwm@7000a000 {
306 compatible = "nvidia,tegra20-pwm"; 357 compatible = "nvidia,tegra20-pwm";
307 reg = <0x7000a000 0x100>; 358 reg = <0x7000a000 0x100>;
308 #pwm-cells = <2>; 359 #pwm-cells = <2>;
309 clocks = <&tegra_car TEGRA20_CLK_PWM>; 360 clocks = <&tegra_car TEGRA20_CLK_PWM>;
361 resets = <&tegra_car 17>;
362 reset-names = "pwm";
310 status = "disabled"; 363 status = "disabled";
311 }; 364 };
312 365
313 rtc { 366 rtc@7000e000 {
314 compatible = "nvidia,tegra20-rtc"; 367 compatible = "nvidia,tegra20-rtc";
315 reg = <0x7000e000 0x100>; 368 reg = <0x7000e000 0x100>;
316 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 369 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
@@ -326,6 +379,10 @@
326 clocks = <&tegra_car TEGRA20_CLK_I2C1>, 379 clocks = <&tegra_car TEGRA20_CLK_I2C1>,
327 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; 380 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
328 clock-names = "div-clk", "fast-clk"; 381 clock-names = "div-clk", "fast-clk";
382 resets = <&tegra_car 12>;
383 reset-names = "i2c";
384 dmas = <&apbdma 21>, <&apbdma 21>;
385 dma-names = "rx", "tx";
329 status = "disabled"; 386 status = "disabled";
330 }; 387 };
331 388
@@ -333,10 +390,13 @@
333 compatible = "nvidia,tegra20-sflash"; 390 compatible = "nvidia,tegra20-sflash";
334 reg = <0x7000c380 0x80>; 391 reg = <0x7000c380 0x80>;
335 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 392 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
336 nvidia,dma-request-selector = <&apbdma 11>;
337 #address-cells = <1>; 393 #address-cells = <1>;
338 #size-cells = <0>; 394 #size-cells = <0>;
339 clocks = <&tegra_car TEGRA20_CLK_SPI>; 395 clocks = <&tegra_car TEGRA20_CLK_SPI>;
396 resets = <&tegra_car 43>;
397 reset-names = "spi";
398 dmas = <&apbdma 11>, <&apbdma 11>;
399 dma-names = "rx", "tx";
340 status = "disabled"; 400 status = "disabled";
341 }; 401 };
342 402
@@ -349,6 +409,10 @@
349 clocks = <&tegra_car TEGRA20_CLK_I2C2>, 409 clocks = <&tegra_car TEGRA20_CLK_I2C2>,
350 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; 410 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
351 clock-names = "div-clk", "fast-clk"; 411 clock-names = "div-clk", "fast-clk";
412 resets = <&tegra_car 54>;
413 reset-names = "i2c";
414 dmas = <&apbdma 22>, <&apbdma 22>;
415 dma-names = "rx", "tx";
352 status = "disabled"; 416 status = "disabled";
353 }; 417 };
354 418
@@ -361,6 +425,10 @@
361 clocks = <&tegra_car TEGRA20_CLK_I2C3>, 425 clocks = <&tegra_car TEGRA20_CLK_I2C3>,
362 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; 426 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
363 clock-names = "div-clk", "fast-clk"; 427 clock-names = "div-clk", "fast-clk";
428 resets = <&tegra_car 67>;
429 reset-names = "i2c";
430 dmas = <&apbdma 23>, <&apbdma 23>;
431 dma-names = "rx", "tx";
364 status = "disabled"; 432 status = "disabled";
365 }; 433 };
366 434
@@ -373,6 +441,10 @@
373 clocks = <&tegra_car TEGRA20_CLK_DVC>, 441 clocks = <&tegra_car TEGRA20_CLK_DVC>,
374 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; 442 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
375 clock-names = "div-clk", "fast-clk"; 443 clock-names = "div-clk", "fast-clk";
444 resets = <&tegra_car 47>;
445 reset-names = "i2c";
446 dmas = <&apbdma 24>, <&apbdma 24>;
447 dma-names = "rx", "tx";
376 status = "disabled"; 448 status = "disabled";
377 }; 449 };
378 450
@@ -380,10 +452,13 @@
380 compatible = "nvidia,tegra20-slink"; 452 compatible = "nvidia,tegra20-slink";
381 reg = <0x7000d400 0x200>; 453 reg = <0x7000d400 0x200>;
382 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 454 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
383 nvidia,dma-request-selector = <&apbdma 15>;
384 #address-cells = <1>; 455 #address-cells = <1>;
385 #size-cells = <0>; 456 #size-cells = <0>;
386 clocks = <&tegra_car TEGRA20_CLK_SBC1>; 457 clocks = <&tegra_car TEGRA20_CLK_SBC1>;
458 resets = <&tegra_car 41>;
459 reset-names = "spi";
460 dmas = <&apbdma 15>, <&apbdma 15>;
461 dma-names = "rx", "tx";
387 status = "disabled"; 462 status = "disabled";
388 }; 463 };
389 464
@@ -391,10 +466,13 @@
391 compatible = "nvidia,tegra20-slink"; 466 compatible = "nvidia,tegra20-slink";
392 reg = <0x7000d600 0x200>; 467 reg = <0x7000d600 0x200>;
393 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 468 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
394 nvidia,dma-request-selector = <&apbdma 16>;
395 #address-cells = <1>; 469 #address-cells = <1>;
396 #size-cells = <0>; 470 #size-cells = <0>;
397 clocks = <&tegra_car TEGRA20_CLK_SBC2>; 471 clocks = <&tegra_car TEGRA20_CLK_SBC2>;
472 resets = <&tegra_car 44>;
473 reset-names = "spi";
474 dmas = <&apbdma 16>, <&apbdma 16>;
475 dma-names = "rx", "tx";
398 status = "disabled"; 476 status = "disabled";
399 }; 477 };
400 478
@@ -402,10 +480,13 @@
402 compatible = "nvidia,tegra20-slink"; 480 compatible = "nvidia,tegra20-slink";
403 reg = <0x7000d800 0x200>; 481 reg = <0x7000d800 0x200>;
404 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 482 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
405 nvidia,dma-request-selector = <&apbdma 17>;
406 #address-cells = <1>; 483 #address-cells = <1>;
407 #size-cells = <0>; 484 #size-cells = <0>;
408 clocks = <&tegra_car TEGRA20_CLK_SBC3>; 485 clocks = <&tegra_car TEGRA20_CLK_SBC3>;
486 resets = <&tegra_car 46>;
487 reset-names = "spi";
488 dmas = <&apbdma 17>, <&apbdma 17>;
489 dma-names = "rx", "tx";
409 status = "disabled"; 490 status = "disabled";
410 }; 491 };
411 492
@@ -413,22 +494,27 @@
413 compatible = "nvidia,tegra20-slink"; 494 compatible = "nvidia,tegra20-slink";
414 reg = <0x7000da00 0x200>; 495 reg = <0x7000da00 0x200>;
415 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 496 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
416 nvidia,dma-request-selector = <&apbdma 18>;
417 #address-cells = <1>; 497 #address-cells = <1>;
418 #size-cells = <0>; 498 #size-cells = <0>;
419 clocks = <&tegra_car TEGRA20_CLK_SBC4>; 499 clocks = <&tegra_car TEGRA20_CLK_SBC4>;
500 resets = <&tegra_car 68>;
501 reset-names = "spi";
502 dmas = <&apbdma 18>, <&apbdma 18>;
503 dma-names = "rx", "tx";
420 status = "disabled"; 504 status = "disabled";
421 }; 505 };
422 506
423 kbc { 507 kbc@7000e200 {
424 compatible = "nvidia,tegra20-kbc"; 508 compatible = "nvidia,tegra20-kbc";
425 reg = <0x7000e200 0x100>; 509 reg = <0x7000e200 0x100>;
426 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 510 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
427 clocks = <&tegra_car TEGRA20_CLK_KBC>; 511 clocks = <&tegra_car TEGRA20_CLK_KBC>;
512 resets = <&tegra_car 36>;
513 reset-names = "kbc";
428 status = "disabled"; 514 status = "disabled";
429 }; 515 };
430 516
431 pmc { 517 pmc@7000e400 {
432 compatible = "nvidia,tegra20-pmc"; 518 compatible = "nvidia,tegra20-pmc";
433 reg = <0x7000e400 0x400>; 519 reg = <0x7000e400 0x400>;
434 clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>; 520 clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;
@@ -442,7 +528,7 @@
442 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 528 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
443 }; 529 };
444 530
445 iommu { 531 iommu@7000f024 {
446 compatible = "nvidia,tegra20-gart"; 532 compatible = "nvidia,tegra20-gart";
447 reg = <0x7000f024 0x00000018 /* controller registers */ 533 reg = <0x7000f024 0x00000018 /* controller registers */
448 0x58000000 0x02000000>; /* GART aperture */ 534 0x58000000 0x02000000>; /* GART aperture */
@@ -455,7 +541,7 @@
455 #size-cells = <0>; 541 #size-cells = <0>;
456 }; 542 };
457 543
458 pcie-controller { 544 pcie-controller@80003000 {
459 compatible = "nvidia,tegra20-pcie"; 545 compatible = "nvidia,tegra20-pcie";
460 device_type = "pci"; 546 device_type = "pci";
461 reg = <0x80003000 0x00000800 /* PADS registers */ 547 reg = <0x80003000 0x00000800 /* PADS registers */
@@ -478,9 +564,12 @@
478 564
479 clocks = <&tegra_car TEGRA20_CLK_PEX>, 565 clocks = <&tegra_car TEGRA20_CLK_PEX>,
480 <&tegra_car TEGRA20_CLK_AFI>, 566 <&tegra_car TEGRA20_CLK_AFI>,
481 <&tegra_car TEGRA20_CLK_PCIE_XCLK>,
482 <&tegra_car TEGRA20_CLK_PLL_E>; 567 <&tegra_car TEGRA20_CLK_PLL_E>;
483 clock-names = "pex", "afi", "pcie_xclk", "pll_e"; 568 clock-names = "pex", "afi", "pll_e";
569 resets = <&tegra_car 70>,
570 <&tegra_car 72>,
571 <&tegra_car 74>;
572 reset-names = "pex", "afi", "pcie_x";
484 status = "disabled"; 573 status = "disabled";
485 574
486 pci@1,0 { 575 pci@1,0 {
@@ -517,6 +606,8 @@
517 phy_type = "utmi"; 606 phy_type = "utmi";
518 nvidia,has-legacy-mode; 607 nvidia,has-legacy-mode;
519 clocks = <&tegra_car TEGRA20_CLK_USBD>; 608 clocks = <&tegra_car TEGRA20_CLK_USBD>;
609 resets = <&tegra_car 22>;
610 reset-names = "usb";
520 nvidia,needs-double-reset; 611 nvidia,needs-double-reset;
521 nvidia,phy = <&phy1>; 612 nvidia,phy = <&phy1>;
522 status = "disabled"; 613 status = "disabled";
@@ -548,6 +639,8 @@
548 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 639 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
549 phy_type = "ulpi"; 640 phy_type = "ulpi";
550 clocks = <&tegra_car TEGRA20_CLK_USB2>; 641 clocks = <&tegra_car TEGRA20_CLK_USB2>;
642 resets = <&tegra_car 58>;
643 reset-names = "usb";
551 nvidia,phy = <&phy2>; 644 nvidia,phy = <&phy2>;
552 status = "disabled"; 645 status = "disabled";
553 }; 646 };
@@ -569,6 +662,8 @@
569 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 662 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
570 phy_type = "utmi"; 663 phy_type = "utmi";
571 clocks = <&tegra_car TEGRA20_CLK_USB3>; 664 clocks = <&tegra_car TEGRA20_CLK_USB3>;
665 resets = <&tegra_car 59>;
666 reset-names = "usb";
572 nvidia,phy = <&phy3>; 667 nvidia,phy = <&phy3>;
573 status = "disabled"; 668 status = "disabled";
574 }; 669 };
@@ -597,6 +692,8 @@
597 reg = <0xc8000000 0x200>; 692 reg = <0xc8000000 0x200>;
598 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 693 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
599 clocks = <&tegra_car TEGRA20_CLK_SDMMC1>; 694 clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
695 resets = <&tegra_car 14>;
696 reset-names = "sdhci";
600 status = "disabled"; 697 status = "disabled";
601 }; 698 };
602 699
@@ -605,6 +702,8 @@
605 reg = <0xc8000200 0x200>; 702 reg = <0xc8000200 0x200>;
606 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 703 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
607 clocks = <&tegra_car TEGRA20_CLK_SDMMC2>; 704 clocks = <&tegra_car TEGRA20_CLK_SDMMC2>;
705 resets = <&tegra_car 9>;
706 reset-names = "sdhci";
608 status = "disabled"; 707 status = "disabled";
609 }; 708 };
610 709
@@ -613,6 +712,8 @@
613 reg = <0xc8000400 0x200>; 712 reg = <0xc8000400 0x200>;
614 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 713 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
615 clocks = <&tegra_car TEGRA20_CLK_SDMMC3>; 714 clocks = <&tegra_car TEGRA20_CLK_SDMMC3>;
715 resets = <&tegra_car 69>;
716 reset-names = "sdhci";
616 status = "disabled"; 717 status = "disabled";
617 }; 718 };
618 719
@@ -621,6 +722,8 @@
621 reg = <0xc8000600 0x200>; 722 reg = <0xc8000600 0x200>;
622 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 723 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
623 clocks = <&tegra_car TEGRA20_CLK_SDMMC4>; 724 clocks = <&tegra_car TEGRA20_CLK_SDMMC4>;
725 resets = <&tegra_car 15>;
726 reset-names = "sdhci";
624 status = "disabled"; 727 status = "disabled";
625 }; 728 };
626 729
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
index 08cad696e89f..e93fe45b7803 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ b/arch/arm/boot/dts/tegra30-beaver.dts
@@ -6,11 +6,16 @@
6 model = "NVIDIA Tegra30 Beaver evaluation board"; 6 model = "NVIDIA Tegra30 Beaver evaluation board";
7 compatible = "nvidia,beaver", "nvidia,tegra30"; 7 compatible = "nvidia,beaver", "nvidia,tegra30";
8 8
9 aliases {
10 rtc0 = "/i2c@7000d000/tps65911@2d";
11 rtc1 = "/rtc@7000e000";
12 };
13
9 memory { 14 memory {
10 reg = <0x80000000 0x7ff00000>; 15 reg = <0x80000000 0x7ff00000>;
11 }; 16 };
12 17
13 pcie-controller { 18 pcie-controller@00003000 {
14 status = "okay"; 19 status = "okay";
15 pex-clk-supply = <&sys_3v3_pexs_reg>; 20 pex-clk-supply = <&sys_3v3_pexs_reg>;
16 vdd-supply = <&ldo1_reg>; 21 vdd-supply = <&ldo1_reg>;
@@ -31,8 +36,8 @@
31 }; 36 };
32 }; 37 };
33 38
34 host1x { 39 host1x@50000000 {
35 hdmi { 40 hdmi@54280000 {
36 status = "okay"; 41 status = "okay";
37 42
38 vdd-supply = <&sys_3v3_reg>; 43 vdd-supply = <&sys_3v3_reg>;
@@ -44,7 +49,7 @@
44 }; 49 };
45 }; 50 };
46 51
47 pinmux { 52 pinmux@70000868 {
48 pinctrl-names = "default"; 53 pinctrl-names = "default";
49 pinctrl-0 = <&state_default>; 54 pinctrl-0 = <&state_default>;
50 55
@@ -52,8 +57,8 @@
52 sdmmc1_clk_pz0 { 57 sdmmc1_clk_pz0 {
53 nvidia,pins = "sdmmc1_clk_pz0"; 58 nvidia,pins = "sdmmc1_clk_pz0";
54 nvidia,function = "sdmmc1"; 59 nvidia,function = "sdmmc1";
55 nvidia,pull = <0>; 60 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
56 nvidia,tristate = <0>; 61 nvidia,tristate = <TEGRA_PIN_DISABLE>;
57 }; 62 };
58 sdmmc1_cmd_pz1 { 63 sdmmc1_cmd_pz1 {
59 nvidia,pins = "sdmmc1_cmd_pz1", 64 nvidia,pins = "sdmmc1_cmd_pz1",
@@ -62,14 +67,14 @@
62 "sdmmc1_dat2_py5", 67 "sdmmc1_dat2_py5",
63 "sdmmc1_dat3_py4"; 68 "sdmmc1_dat3_py4";
64 nvidia,function = "sdmmc1"; 69 nvidia,function = "sdmmc1";
65 nvidia,pull = <2>; 70 nvidia,pull = <TEGRA_PIN_PULL_UP>;
66 nvidia,tristate = <0>; 71 nvidia,tristate = <TEGRA_PIN_DISABLE>;
67 }; 72 };
68 sdmmc3_clk_pa6 { 73 sdmmc3_clk_pa6 {
69 nvidia,pins = "sdmmc3_clk_pa6"; 74 nvidia,pins = "sdmmc3_clk_pa6";
70 nvidia,function = "sdmmc3"; 75 nvidia,function = "sdmmc3";
71 nvidia,pull = <0>; 76 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
72 nvidia,tristate = <0>; 77 nvidia,tristate = <TEGRA_PIN_DISABLE>;
73 }; 78 };
74 sdmmc3_cmd_pa7 { 79 sdmmc3_cmd_pa7 {
75 nvidia,pins = "sdmmc3_cmd_pa7", 80 nvidia,pins = "sdmmc3_cmd_pa7",
@@ -78,15 +83,15 @@
78 "sdmmc3_dat2_pb5", 83 "sdmmc3_dat2_pb5",
79 "sdmmc3_dat3_pb4"; 84 "sdmmc3_dat3_pb4";
80 nvidia,function = "sdmmc3"; 85 nvidia,function = "sdmmc3";
81 nvidia,pull = <2>; 86 nvidia,pull = <TEGRA_PIN_PULL_UP>;
82 nvidia,tristate = <0>; 87 nvidia,tristate = <TEGRA_PIN_DISABLE>;
83 }; 88 };
84 sdmmc4_clk_pcc4 { 89 sdmmc4_clk_pcc4 {
85 nvidia,pins = "sdmmc4_clk_pcc4", 90 nvidia,pins = "sdmmc4_clk_pcc4",
86 "sdmmc4_rst_n_pcc3"; 91 "sdmmc4_rst_n_pcc3";
87 nvidia,function = "sdmmc4"; 92 nvidia,function = "sdmmc4";
88 nvidia,pull = <0>; 93 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
89 nvidia,tristate = <0>; 94 nvidia,tristate = <TEGRA_PIN_DISABLE>;
90 }; 95 };
91 sdmmc4_dat0_paa0 { 96 sdmmc4_dat0_paa0 {
92 nvidia,pins = "sdmmc4_dat0_paa0", 97 nvidia,pins = "sdmmc4_dat0_paa0",
@@ -98,8 +103,8 @@
98 "sdmmc4_dat6_paa6", 103 "sdmmc4_dat6_paa6",
99 "sdmmc4_dat7_paa7"; 104 "sdmmc4_dat7_paa7";
100 nvidia,function = "sdmmc4"; 105 nvidia,function = "sdmmc4";
101 nvidia,pull = <2>; 106 nvidia,pull = <TEGRA_PIN_PULL_UP>;
102 nvidia,tristate = <0>; 107 nvidia,tristate = <TEGRA_PIN_DISABLE>;
103 }; 108 };
104 dap2_fs_pa2 { 109 dap2_fs_pa2 {
105 nvidia,pins = "dap2_fs_pa2", 110 nvidia,pins = "dap2_fs_pa2",
@@ -107,18 +112,18 @@
107 "dap2_din_pa4", 112 "dap2_din_pa4",
108 "dap2_dout_pa5"; 113 "dap2_dout_pa5";
109 nvidia,function = "i2s1"; 114 nvidia,function = "i2s1";
110 nvidia,pull = <0>; 115 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
111 nvidia,tristate = <0>; 116 nvidia,tristate = <TEGRA_PIN_DISABLE>;
112 }; 117 };
113 pex_l1_prsnt_n_pdd4 { 118 pex_l1_prsnt_n_pdd4 {
114 nvidia,pins = "pex_l1_prsnt_n_pdd4", 119 nvidia,pins = "pex_l1_prsnt_n_pdd4",
115 "pex_l1_clkreq_n_pdd6"; 120 "pex_l1_clkreq_n_pdd6";
116 nvidia,pull = <2>; 121 nvidia,pull = <TEGRA_PIN_PULL_UP>;
117 }; 122 };
118 sdio3 { 123 sdio3 {
119 nvidia,pins = "drive_sdio3"; 124 nvidia,pins = "drive_sdio3";
120 nvidia,high-speed-mode = <0>; 125 nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
121 nvidia,schmitt = <0>; 126 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
122 nvidia,pull-down-strength = <46>; 127 nvidia,pull-down-strength = <46>;
123 nvidia,pull-up-strength = <42>; 128 nvidia,pull-up-strength = <42>;
124 nvidia,slew-rate-rising = <1>; 129 nvidia,slew-rate-rising = <1>;
@@ -159,7 +164,7 @@
159 status = "okay"; 164 status = "okay";
160 clock-frequency = <100000>; 165 clock-frequency = <100000>;
161 166
162 rt5640: rt5640 { 167 rt5640: rt5640@1c {
163 compatible = "realtek,rt5640"; 168 compatible = "realtek,rt5640";
164 reg = <0x1c>; 169 reg = <0x1c>;
165 interrupt-parent = <&gpio>; 170 interrupt-parent = <&gpio>;
@@ -168,19 +173,6 @@
168 <&gpio TEGRA_GPIO(X, 2) GPIO_ACTIVE_HIGH>; 173 <&gpio TEGRA_GPIO(X, 2) GPIO_ACTIVE_HIGH>;
169 }; 174 };
170 175
171 tps62361 {
172 compatible = "ti,tps62361";
173 reg = <0x60>;
174
175 regulator-name = "tps62361-vout";
176 regulator-min-microvolt = <500000>;
177 regulator-max-microvolt = <1500000>;
178 regulator-boot-on;
179 regulator-always-on;
180 ti,vsel0-state-high;
181 ti,vsel1-state-high;
182 };
183
184 pmic: tps65911@2d { 176 pmic: tps65911@2d {
185 compatible = "ti,tps65911"; 177 compatible = "ti,tps65911";
186 reg = <0x2d>; 178 reg = <0x2d>;
@@ -284,6 +276,19 @@
284 }; 276 };
285 }; 277 };
286 }; 278 };
279
280 tps62361@60 {
281 compatible = "ti,tps62361";
282 reg = <0x60>;
283
284 regulator-name = "tps62361-vout";
285 regulator-min-microvolt = <500000>;
286 regulator-max-microvolt = <1500000>;
287 regulator-boot-on;
288 regulator-always-on;
289 ti,vsel0-state-high;
290 ti,vsel1-state-high;
291 };
287 }; 292 };
288 293
289 spi@7000da00 { 294 spi@7000da00 {
@@ -296,13 +301,7 @@
296 }; 301 };
297 }; 302 };
298 303
299 ahub { 304 pmc@7000e400 {
300 i2s@70080400 {
301 status = "okay";
302 };
303 };
304
305 pmc {
306 status = "okay"; 305 status = "okay";
307 nvidia,invert-interrupt; 306 nvidia,invert-interrupt;
308 nvidia,suspend-mode = <1>; 307 nvidia,suspend-mode = <1>;
@@ -314,6 +313,12 @@
314 nvidia,sys-clock-req-active-high; 313 nvidia,sys-clock-req-active-high;
315 }; 314 };
316 315
316 ahub@70080000 {
317 i2s@70080400 {
318 status = "okay";
319 };
320 };
321
317 sdhci@78000000 { 322 sdhci@78000000 {
318 status = "okay"; 323 status = "okay";
319 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; 324 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
@@ -328,6 +333,15 @@
328 non-removable; 333 non-removable;
329 }; 334 };
330 335
336 usb@7d004000 {
337 status = "okay";
338 };
339
340 phy2: usb-phy@7d004000 {
341 vbus-supply = <&sys_3v3_reg>;
342 status = "okay";
343 };
344
331 usb@7d008000 { 345 usb@7d008000 {
332 status = "okay"; 346 status = "okay";
333 }; 347 };
@@ -342,7 +356,7 @@
342 #address-cells = <1>; 356 #address-cells = <1>;
343 #size-cells = <0>; 357 #size-cells = <0>;
344 358
345 clk32k_in: clock { 359 clk32k_in: clock@0 {
346 compatible = "fixed-clock"; 360 compatible = "fixed-clock";
347 reg=<0>; 361 reg=<0>;
348 #clock-cells = <0>; 362 #clock-cells = <0>;
@@ -350,6 +364,19 @@
350 }; 364 };
351 }; 365 };
352 366
367 gpio-leds {
368 compatible = "gpio-leds";
369
370 gpled1 {
371 label = "LED1"; /* CR5A1 (blue) */
372 gpios = <&gpio TEGRA_GPIO(L, 1) GPIO_ACTIVE_HIGH>;
373 };
374 gpled2 {
375 label = "LED2"; /* CR4A2 (green) */
376 gpios = <&gpio TEGRA_GPIO(L, 0) GPIO_ACTIVE_HIGH>;
377 };
378 };
379
353 regulators { 380 regulators {
354 compatible = "simple-bus"; 381 compatible = "simple-bus";
355 #address-cells = <1>; 382 #address-cells = <1>;
@@ -453,19 +480,6 @@
453 }; 480 };
454 }; 481 };
455 482
456 gpio-leds {
457 compatible = "gpio-leds";
458
459 gpled1 {
460 label = "LED1"; /* CR5A1 (blue) */
461 gpios = <&gpio TEGRA_GPIO(L, 1) GPIO_ACTIVE_HIGH>;
462 };
463 gpled2 {
464 label = "LED2"; /* CR4A2 (green) */
465 gpios = <&gpio TEGRA_GPIO(L, 0) GPIO_ACTIVE_HIGH>;
466 };
467 };
468
469 sound { 483 sound {
470 compatible = "nvidia,tegra-audio-rt5640-beaver", 484 compatible = "nvidia,tegra-audio-rt5640-beaver",
471 "nvidia,tegra-audio-rt5640"; 485 "nvidia,tegra-audio-rt5640";
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a02.dts b/arch/arm/boot/dts/tegra30-cardhu-a02.dts
index 1082c5ed90d1..c9bfedcca6ed 100644
--- a/arch/arm/boot/dts/tegra30-cardhu-a02.dts
+++ b/arch/arm/boot/dts/tegra30-cardhu-a02.dts
@@ -8,6 +8,13 @@
8 model = "NVIDIA Tegra30 Cardhu A02 evaluation board"; 8 model = "NVIDIA Tegra30 Cardhu A02 evaluation board";
9 compatible = "nvidia,cardhu-a02", "nvidia,cardhu", "nvidia,tegra30"; 9 compatible = "nvidia,cardhu-a02", "nvidia,cardhu", "nvidia,tegra30";
10 10
11 sdhci@78000400 {
12 status = "okay";
13 power-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
14 bus-width = <4>;
15 keep-power-in-suspend;
16 };
17
11 regulators { 18 regulators {
12 compatible = "simple-bus"; 19 compatible = "simple-bus";
13 #address-cells = <1>; 20 #address-cells = <1>;
@@ -83,12 +90,5 @@
83 gpio = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_HIGH>; 90 gpio = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_HIGH>;
84 }; 91 };
85 }; 92 };
86
87 sdhci@78000400 {
88 status = "okay";
89 power-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
90 bus-width = <4>;
91 keep-power-in-suspend;
92 };
93}; 93};
94 94
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a04.dts b/arch/arm/boot/dts/tegra30-cardhu-a04.dts
index bf012bddaafb..fadf55e46b2b 100644
--- a/arch/arm/boot/dts/tegra30-cardhu-a04.dts
+++ b/arch/arm/boot/dts/tegra30-cardhu-a04.dts
@@ -8,6 +8,13 @@
8 model = "NVIDIA Tegra30 Cardhu A04 (A05, A06, A07) evaluation board"; 8 model = "NVIDIA Tegra30 Cardhu A04 (A05, A06, A07) evaluation board";
9 compatible = "nvidia,cardhu-a04", "nvidia,cardhu", "nvidia,tegra30"; 9 compatible = "nvidia,cardhu-a04", "nvidia,cardhu", "nvidia,tegra30";
10 10
11 sdhci@78000400 {
12 status = "okay";
13 power-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_HIGH>;
14 bus-width = <4>;
15 keep-power-in-suspend;
16 };
17
11 regulators { 18 regulators {
12 compatible = "simple-bus"; 19 compatible = "simple-bus";
13 #address-cells = <1>; 20 #address-cells = <1>;
@@ -95,11 +102,4 @@
95 gpio = <&gpio TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>; 102 gpio = <&gpio TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>;
96 }; 103 };
97 }; 104 };
98
99 sdhci@78000400 {
100 status = "okay";
101 power-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_HIGH>;
102 bus-width = <4>;
103 keep-power-in-suspend;
104 };
105}; 105};
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index 5ea7dfa4d9fa..9104224124ee 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -27,11 +27,16 @@
27 model = "NVIDIA Tegra30 Cardhu evaluation board"; 27 model = "NVIDIA Tegra30 Cardhu evaluation board";
28 compatible = "nvidia,cardhu", "nvidia,tegra30"; 28 compatible = "nvidia,cardhu", "nvidia,tegra30";
29 29
30 aliases {
31 rtc0 = "/i2c@7000d000/tps6586x@34";
32 rtc1 = "/rtc@7000e000";
33 };
34
30 memory { 35 memory {
31 reg = <0x80000000 0x40000000>; 36 reg = <0x80000000 0x40000000>;
32 }; 37 };
33 38
34 pcie-controller { 39 pcie-controller@00003000 {
35 status = "okay"; 40 status = "okay";
36 pex-clk-supply = <&pex_hvdd_3v3_reg>; 41 pex-clk-supply = <&pex_hvdd_3v3_reg>;
37 vdd-supply = <&ldo1_reg>; 42 vdd-supply = <&ldo1_reg>;
@@ -51,7 +56,17 @@
51 }; 56 };
52 }; 57 };
53 58
54 pinmux { 59 host1x@50000000 {
60 dc@54200000 {
61 rgb {
62 status = "okay";
63
64 nvidia,panel = <&panel>;
65 };
66 };
67 };
68
69 pinmux@70000868 {
55 pinctrl-names = "default"; 70 pinctrl-names = "default";
56 pinctrl-0 = <&state_default>; 71 pinctrl-0 = <&state_default>;
57 72
@@ -59,8 +74,8 @@
59 sdmmc1_clk_pz0 { 74 sdmmc1_clk_pz0 {
60 nvidia,pins = "sdmmc1_clk_pz0"; 75 nvidia,pins = "sdmmc1_clk_pz0";
61 nvidia,function = "sdmmc1"; 76 nvidia,function = "sdmmc1";
62 nvidia,pull = <0>; 77 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
63 nvidia,tristate = <0>; 78 nvidia,tristate = <TEGRA_PIN_DISABLE>;
64 }; 79 };
65 sdmmc1_cmd_pz1 { 80 sdmmc1_cmd_pz1 {
66 nvidia,pins = "sdmmc1_cmd_pz1", 81 nvidia,pins = "sdmmc1_cmd_pz1",
@@ -69,14 +84,14 @@
69 "sdmmc1_dat2_py5", 84 "sdmmc1_dat2_py5",
70 "sdmmc1_dat3_py4"; 85 "sdmmc1_dat3_py4";
71 nvidia,function = "sdmmc1"; 86 nvidia,function = "sdmmc1";
72 nvidia,pull = <2>; 87 nvidia,pull = <TEGRA_PIN_PULL_UP>;
73 nvidia,tristate = <0>; 88 nvidia,tristate = <TEGRA_PIN_DISABLE>;
74 }; 89 };
75 sdmmc3_clk_pa6 { 90 sdmmc3_clk_pa6 {
76 nvidia,pins = "sdmmc3_clk_pa6"; 91 nvidia,pins = "sdmmc3_clk_pa6";
77 nvidia,function = "sdmmc3"; 92 nvidia,function = "sdmmc3";
78 nvidia,pull = <0>; 93 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
79 nvidia,tristate = <0>; 94 nvidia,tristate = <TEGRA_PIN_DISABLE>;
80 }; 95 };
81 sdmmc3_cmd_pa7 { 96 sdmmc3_cmd_pa7 {
82 nvidia,pins = "sdmmc3_cmd_pa7", 97 nvidia,pins = "sdmmc3_cmd_pa7",
@@ -85,15 +100,15 @@
85 "sdmmc3_dat2_pb5", 100 "sdmmc3_dat2_pb5",
86 "sdmmc3_dat3_pb4"; 101 "sdmmc3_dat3_pb4";
87 nvidia,function = "sdmmc3"; 102 nvidia,function = "sdmmc3";
88 nvidia,pull = <2>; 103 nvidia,pull = <TEGRA_PIN_PULL_UP>;
89 nvidia,tristate = <0>; 104 nvidia,tristate = <TEGRA_PIN_DISABLE>;
90 }; 105 };
91 sdmmc4_clk_pcc4 { 106 sdmmc4_clk_pcc4 {
92 nvidia,pins = "sdmmc4_clk_pcc4", 107 nvidia,pins = "sdmmc4_clk_pcc4",
93 "sdmmc4_rst_n_pcc3"; 108 "sdmmc4_rst_n_pcc3";
94 nvidia,function = "sdmmc4"; 109 nvidia,function = "sdmmc4";
95 nvidia,pull = <0>; 110 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
96 nvidia,tristate = <0>; 111 nvidia,tristate = <TEGRA_PIN_DISABLE>;
97 }; 112 };
98 sdmmc4_dat0_paa0 { 113 sdmmc4_dat0_paa0 {
99 nvidia,pins = "sdmmc4_dat0_paa0", 114 nvidia,pins = "sdmmc4_dat0_paa0",
@@ -105,8 +120,8 @@
105 "sdmmc4_dat6_paa6", 120 "sdmmc4_dat6_paa6",
106 "sdmmc4_dat7_paa7"; 121 "sdmmc4_dat7_paa7";
107 nvidia,function = "sdmmc4"; 122 nvidia,function = "sdmmc4";
108 nvidia,pull = <2>; 123 nvidia,pull = <TEGRA_PIN_PULL_UP>;
109 nvidia,tristate = <0>; 124 nvidia,tristate = <TEGRA_PIN_DISABLE>;
110 }; 125 };
111 dap2_fs_pa2 { 126 dap2_fs_pa2 {
112 nvidia,pins = "dap2_fs_pa2", 127 nvidia,pins = "dap2_fs_pa2",
@@ -114,17 +129,17 @@
114 "dap2_din_pa4", 129 "dap2_din_pa4",
115 "dap2_dout_pa5"; 130 "dap2_dout_pa5";
116 nvidia,function = "i2s1"; 131 nvidia,function = "i2s1";
117 nvidia,pull = <0>; 132 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
118 nvidia,tristate = <0>; 133 nvidia,tristate = <TEGRA_PIN_DISABLE>;
119 }; 134 };
120 sdio3 { 135 sdio3 {
121 nvidia,pins = "drive_sdio3"; 136 nvidia,pins = "drive_sdio3";
122 nvidia,high-speed-mode = <0>; 137 nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
123 nvidia,schmitt = <0>; 138 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
124 nvidia,pull-down-strength = <46>; 139 nvidia,pull-down-strength = <46>;
125 nvidia,pull-up-strength = <42>; 140 nvidia,pull-up-strength = <42>;
126 nvidia,slew-rate-rising = <1>; 141 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>;
127 nvidia,slew-rate-falling = <1>; 142 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>;
128 }; 143 };
129 uart3_txd_pw6 { 144 uart3_txd_pw6 {
130 nvidia,pins = "uart3_txd_pw6", 145 nvidia,pins = "uart3_txd_pw6",
@@ -132,8 +147,8 @@
132 "uart3_rts_n_pc0", 147 "uart3_rts_n_pc0",
133 "uart3_rxd_pw7"; 148 "uart3_rxd_pw7";
134 nvidia,function = "uartc"; 149 nvidia,function = "uartc";
135 nvidia,pull = <0>; 150 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
136 nvidia,tristate = <0>; 151 nvidia,tristate = <TEGRA_PIN_DISABLE>;
137 }; 152 };
138 }; 153 };
139 }; 154 };
@@ -147,7 +162,11 @@
147 status = "okay"; 162 status = "okay";
148 }; 163 };
149 164
150 i2c@7000c000 { 165 pwm@7000a000 {
166 status = "okay";
167 };
168
169 panelddc: i2c@7000c000 {
151 status = "okay"; 170 status = "okay";
152 clock-frequency = <100000>; 171 clock-frequency = <100000>;
153 }; 172 };
@@ -302,7 +321,7 @@
302 interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_LEVEL_LOW>; 321 interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_LEVEL_LOW>;
303 }; 322 };
304 323
305 tps62361 { 324 tps62361@60 {
306 compatible = "ti,tps62361"; 325 compatible = "ti,tps62361";
307 reg = <0x60>; 326 reg = <0x60>;
308 327
@@ -326,13 +345,7 @@
326 }; 345 };
327 }; 346 };
328 347
329 ahub { 348 pmc@7000e400 {
330 i2s@70080400 {
331 status = "okay";
332 };
333 };
334
335 pmc {
336 status = "okay"; 349 status = "okay";
337 nvidia,invert-interrupt; 350 nvidia,invert-interrupt;
338 nvidia,suspend-mode = <1>; 351 nvidia,suspend-mode = <1>;
@@ -344,6 +357,12 @@
344 nvidia,sys-clock-req-active-high; 357 nvidia,sys-clock-req-active-high;
345 }; 358 };
346 359
360 ahub@70080000 {
361 i2s@70080400 {
362 status = "okay";
363 };
364 };
365
347 sdhci@78000000 { 366 sdhci@78000000 {
348 status = "okay"; 367 status = "okay";
349 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; 368 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
@@ -367,12 +386,23 @@
367 status = "okay"; 386 status = "okay";
368 }; 387 };
369 388
389 backlight: backlight {
390 compatible = "pwm-backlight";
391
392 enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
393 power-supply = <&vdd_bl_reg>;
394 pwms = <&pwm 0 5000000>;
395
396 brightness-levels = <0 4 8 16 32 64 128 255>;
397 default-brightness-level = <6>;
398 };
399
370 clocks { 400 clocks {
371 compatible = "simple-bus"; 401 compatible = "simple-bus";
372 #address-cells = <1>; 402 #address-cells = <1>;
373 #size-cells = <0>; 403 #size-cells = <0>;
374 404
375 clk32k_in: clock { 405 clk32k_in: clock@0 {
376 compatible = "fixed-clock"; 406 compatible = "fixed-clock";
377 reg=<0>; 407 reg=<0>;
378 #clock-cells = <0>; 408 #clock-cells = <0>;
@@ -380,6 +410,16 @@
380 }; 410 };
381 }; 411 };
382 412
413 panel: panel {
414 compatible = "chunghwa,claa101wb01", "simple-panel";
415 ddc-i2c-bus = <&panelddc>;
416
417 power-supply = <&vdd_pnl1_reg>;
418 enable-gpios = <&gpio TEGRA_GPIO(L, 2) GPIO_ACTIVE_HIGH>;
419
420 backlight = <&backlight>;
421 };
422
383 regulators { 423 regulators {
384 compatible = "simple-bus"; 424 compatible = "simple-bus";
385 #address-cells = <1>; 425 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 2bd55cfd88ad..ed8e7700b46d 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -1,5 +1,6 @@
1#include <dt-bindings/clock/tegra30-car.h> 1#include <dt-bindings/clock/tegra30-car.h>
2#include <dt-bindings/gpio/tegra-gpio.h> 2#include <dt-bindings/gpio/tegra-gpio.h>
3#include <dt-bindings/pinctrl/pinctrl-tegra.h>
3#include <dt-bindings/interrupt-controller/arm-gic.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h>
4 5
5#include "skeleton.dtsi" 6#include "skeleton.dtsi"
@@ -16,7 +17,7 @@
16 serial4 = &uarte; 17 serial4 = &uarte;
17 }; 18 };
18 19
19 pcie-controller { 20 pcie-controller@00003000 {
20 compatible = "nvidia,tegra30-pcie"; 21 compatible = "nvidia,tegra30-pcie";
21 device_type = "pci"; 22 device_type = "pci";
22 reg = <0x00003000 0x00000800 /* PADS registers */ 23 reg = <0x00003000 0x00000800 /* PADS registers */
@@ -40,10 +41,13 @@
40 41
41 clocks = <&tegra_car TEGRA30_CLK_PCIE>, 42 clocks = <&tegra_car TEGRA30_CLK_PCIE>,
42 <&tegra_car TEGRA30_CLK_AFI>, 43 <&tegra_car TEGRA30_CLK_AFI>,
43 <&tegra_car TEGRA30_CLK_PCIEX>,
44 <&tegra_car TEGRA30_CLK_PLL_E>, 44 <&tegra_car TEGRA30_CLK_PLL_E>,
45 <&tegra_car TEGRA30_CLK_CML0>; 45 <&tegra_car TEGRA30_CLK_CML0>;
46 clock-names = "pex", "afi", "pcie_xclk", "pll_e", "cml"; 46 clock-names = "pex", "afi", "pll_e", "cml";
47 resets = <&tegra_car 70>,
48 <&tegra_car 72>,
49 <&tegra_car 74>;
50 reset-names = "pex", "afi", "pcie_x";
47 status = "disabled"; 51 status = "disabled";
48 52
49 pci@1,0 { 53 pci@1,0 {
@@ -86,59 +90,74 @@
86 }; 90 };
87 }; 91 };
88 92
89 host1x { 93 host1x@50000000 {
90 compatible = "nvidia,tegra30-host1x", "simple-bus"; 94 compatible = "nvidia,tegra30-host1x", "simple-bus";
91 reg = <0x50000000 0x00024000>; 95 reg = <0x50000000 0x00024000>;
92 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 96 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
93 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 97 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
94 clocks = <&tegra_car TEGRA30_CLK_HOST1X>; 98 clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
99 resets = <&tegra_car 28>;
100 reset-names = "host1x";
95 101
96 #address-cells = <1>; 102 #address-cells = <1>;
97 #size-cells = <1>; 103 #size-cells = <1>;
98 104
99 ranges = <0x54000000 0x54000000 0x04000000>; 105 ranges = <0x54000000 0x54000000 0x04000000>;
100 106
101 mpe { 107 mpe@54040000 {
102 compatible = "nvidia,tegra30-mpe"; 108 compatible = "nvidia,tegra30-mpe";
103 reg = <0x54040000 0x00040000>; 109 reg = <0x54040000 0x00040000>;
104 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 110 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
105 clocks = <&tegra_car TEGRA30_CLK_MPE>; 111 clocks = <&tegra_car TEGRA30_CLK_MPE>;
112 resets = <&tegra_car 60>;
113 reset-names = "mpe";
106 }; 114 };
107 115
108 vi { 116 vi@54080000 {
109 compatible = "nvidia,tegra30-vi"; 117 compatible = "nvidia,tegra30-vi";
110 reg = <0x54080000 0x00040000>; 118 reg = <0x54080000 0x00040000>;
111 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 119 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
112 clocks = <&tegra_car TEGRA30_CLK_VI>; 120 clocks = <&tegra_car TEGRA30_CLK_VI>;
121 resets = <&tegra_car 20>;
122 reset-names = "vi";
113 }; 123 };
114 124
115 epp { 125 epp@540c0000 {
116 compatible = "nvidia,tegra30-epp"; 126 compatible = "nvidia,tegra30-epp";
117 reg = <0x540c0000 0x00040000>; 127 reg = <0x540c0000 0x00040000>;
118 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 128 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
119 clocks = <&tegra_car TEGRA30_CLK_EPP>; 129 clocks = <&tegra_car TEGRA30_CLK_EPP>;
130 resets = <&tegra_car 19>;
131 reset-names = "epp";
120 }; 132 };
121 133
122 isp { 134 isp@54100000 {
123 compatible = "nvidia,tegra30-isp"; 135 compatible = "nvidia,tegra30-isp";
124 reg = <0x54100000 0x00040000>; 136 reg = <0x54100000 0x00040000>;
125 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 137 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
126 clocks = <&tegra_car TEGRA30_CLK_ISP>; 138 clocks = <&tegra_car TEGRA30_CLK_ISP>;
139 resets = <&tegra_car 23>;
140 reset-names = "isp";
127 }; 141 };
128 142
129 gr2d { 143 gr2d@54140000 {
130 compatible = "nvidia,tegra30-gr2d"; 144 compatible = "nvidia,tegra30-gr2d";
131 reg = <0x54140000 0x00040000>; 145 reg = <0x54140000 0x00040000>;
132 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 146 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
147 resets = <&tegra_car 21>;
148 reset-names = "2d";
133 clocks = <&tegra_car TEGRA30_CLK_GR2D>; 149 clocks = <&tegra_car TEGRA30_CLK_GR2D>;
134 }; 150 };
135 151
136 gr3d { 152 gr3d@54180000 {
137 compatible = "nvidia,tegra30-gr3d"; 153 compatible = "nvidia,tegra30-gr3d";
138 reg = <0x54180000 0x00040000>; 154 reg = <0x54180000 0x00040000>;
139 clocks = <&tegra_car TEGRA30_CLK_GR3D 155 clocks = <&tegra_car TEGRA30_CLK_GR3D
140 &tegra_car TEGRA30_CLK_GR3D2>; 156 &tegra_car TEGRA30_CLK_GR3D2>;
141 clock-names = "3d", "3d2"; 157 clock-names = "3d", "3d2";
158 resets = <&tegra_car 24>,
159 <&tegra_car 98>;
160 reset-names = "3d", "3d2";
142 }; 161 };
143 162
144 dc@54200000 { 163 dc@54200000 {
@@ -147,7 +166,9 @@
147 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 166 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
148 clocks = <&tegra_car TEGRA30_CLK_DISP1>, 167 clocks = <&tegra_car TEGRA30_CLK_DISP1>,
149 <&tegra_car TEGRA30_CLK_PLL_P>; 168 <&tegra_car TEGRA30_CLK_PLL_P>;
150 clock-names = "disp1", "parent"; 169 clock-names = "dc", "parent";
170 resets = <&tegra_car 27>;
171 reset-names = "dc";
151 172
152 rgb { 173 rgb {
153 status = "disabled"; 174 status = "disabled";
@@ -160,24 +181,28 @@
160 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 181 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
161 clocks = <&tegra_car TEGRA30_CLK_DISP2>, 182 clocks = <&tegra_car TEGRA30_CLK_DISP2>,
162 <&tegra_car TEGRA30_CLK_PLL_P>; 183 <&tegra_car TEGRA30_CLK_PLL_P>;
163 clock-names = "disp2", "parent"; 184 clock-names = "dc", "parent";
185 resets = <&tegra_car 26>;
186 reset-names = "dc";
164 187
165 rgb { 188 rgb {
166 status = "disabled"; 189 status = "disabled";
167 }; 190 };
168 }; 191 };
169 192
170 hdmi { 193 hdmi@54280000 {
171 compatible = "nvidia,tegra30-hdmi"; 194 compatible = "nvidia,tegra30-hdmi";
172 reg = <0x54280000 0x00040000>; 195 reg = <0x54280000 0x00040000>;
173 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 196 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
174 clocks = <&tegra_car TEGRA30_CLK_HDMI>, 197 clocks = <&tegra_car TEGRA30_CLK_HDMI>,
175 <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>; 198 <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>;
176 clock-names = "hdmi", "parent"; 199 clock-names = "hdmi", "parent";
200 resets = <&tegra_car 51>;
201 reset-names = "hdmi";
177 status = "disabled"; 202 status = "disabled";
178 }; 203 };
179 204
180 tvo { 205 tvo@542c0000 {
181 compatible = "nvidia,tegra30-tvo"; 206 compatible = "nvidia,tegra30-tvo";
182 reg = <0x542c0000 0x00040000>; 207 reg = <0x542c0000 0x00040000>;
183 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 208 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
@@ -185,10 +210,12 @@
185 status = "disabled"; 210 status = "disabled";
186 }; 211 };
187 212
188 dsi { 213 dsi@54300000 {
189 compatible = "nvidia,tegra30-dsi"; 214 compatible = "nvidia,tegra30-dsi";
190 reg = <0x54300000 0x00040000>; 215 reg = <0x54300000 0x00040000>;
191 clocks = <&tegra_car TEGRA30_CLK_DSIA>; 216 clocks = <&tegra_car TEGRA30_CLK_DSIA>;
217 resets = <&tegra_car 48>;
218 reset-names = "dsi";
192 status = "disabled"; 219 status = "disabled";
193 }; 220 };
194 }; 221 };
@@ -201,7 +228,7 @@
201 clocks = <&tegra_car TEGRA30_CLK_TWD>; 228 clocks = <&tegra_car TEGRA30_CLK_TWD>;
202 }; 229 };
203 230
204 intc: interrupt-controller { 231 intc: interrupt-controller@50041000 {
205 compatible = "arm,cortex-a9-gic"; 232 compatible = "arm,cortex-a9-gic";
206 reg = <0x50041000 0x1000 233 reg = <0x50041000 0x1000
207 0x50040100 0x0100>; 234 0x50040100 0x0100>;
@@ -209,7 +236,7 @@
209 #interrupt-cells = <3>; 236 #interrupt-cells = <3>;
210 }; 237 };
211 238
212 cache-controller { 239 cache-controller@50043000 {
213 compatible = "arm,pl310-cache"; 240 compatible = "arm,pl310-cache";
214 reg = <0x50043000 0x1000>; 241 reg = <0x50043000 0x1000>;
215 arm,data-latency = <6 6 2>; 242 arm,data-latency = <6 6 2>;
@@ -230,13 +257,14 @@
230 clocks = <&tegra_car TEGRA30_CLK_TIMER>; 257 clocks = <&tegra_car TEGRA30_CLK_TIMER>;
231 }; 258 };
232 259
233 tegra_car: clock { 260 tegra_car: clock@60006000 {
234 compatible = "nvidia,tegra30-car"; 261 compatible = "nvidia,tegra30-car";
235 reg = <0x60006000 0x1000>; 262 reg = <0x60006000 0x1000>;
236 #clock-cells = <1>; 263 #clock-cells = <1>;
264 #reset-cells = <1>;
237 }; 265 };
238 266
239 apbdma: dma { 267 apbdma: dma@6000a000 {
240 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; 268 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
241 reg = <0x6000a000 0x1400>; 269 reg = <0x6000a000 0x1400>;
242 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 270 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
@@ -272,14 +300,17 @@
272 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 300 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
273 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 301 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
274 clocks = <&tegra_car TEGRA30_CLK_APBDMA>; 302 clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
303 resets = <&tegra_car 34>;
304 reset-names = "dma";
305 #dma-cells = <1>;
275 }; 306 };
276 307
277 ahb: ahb { 308 ahb: ahb@6000c004 {
278 compatible = "nvidia,tegra30-ahb"; 309 compatible = "nvidia,tegra30-ahb";
279 reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */ 310 reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
280 }; 311 };
281 312
282 gpio: gpio { 313 gpio: gpio@6000d000 {
283 compatible = "nvidia,tegra30-gpio"; 314 compatible = "nvidia,tegra30-gpio";
284 reg = <0x6000d000 0x1000>; 315 reg = <0x6000d000 0x1000>;
285 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 316 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
@@ -296,7 +327,7 @@
296 interrupt-controller; 327 interrupt-controller;
297 }; 328 };
298 329
299 pinmux: pinmux { 330 pinmux: pinmux@70000868 {
300 compatible = "nvidia,tegra30-pinmux"; 331 compatible = "nvidia,tegra30-pinmux";
301 reg = <0x70000868 0xd4 /* Pad control registers */ 332 reg = <0x70000868 0xd4 /* Pad control registers */
302 0x70003000 0x3e4>; /* Mux registers */ 333 0x70003000 0x3e4>; /* Mux registers */
@@ -315,8 +346,11 @@
315 reg = <0x70006000 0x40>; 346 reg = <0x70006000 0x40>;
316 reg-shift = <2>; 347 reg-shift = <2>;
317 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 348 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
318 nvidia,dma-request-selector = <&apbdma 8>;
319 clocks = <&tegra_car TEGRA30_CLK_UARTA>; 349 clocks = <&tegra_car TEGRA30_CLK_UARTA>;
350 resets = <&tegra_car 6>;
351 reset-names = "serial";
352 dmas = <&apbdma 8>, <&apbdma 8>;
353 dma-names = "rx", "tx";
320 status = "disabled"; 354 status = "disabled";
321 }; 355 };
322 356
@@ -325,8 +359,11 @@
325 reg = <0x70006040 0x40>; 359 reg = <0x70006040 0x40>;
326 reg-shift = <2>; 360 reg-shift = <2>;
327 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 361 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
328 nvidia,dma-request-selector = <&apbdma 9>;
329 clocks = <&tegra_car TEGRA30_CLK_UARTB>; 362 clocks = <&tegra_car TEGRA30_CLK_UARTB>;
363 resets = <&tegra_car 7>;
364 reset-names = "serial";
365 dmas = <&apbdma 9>, <&apbdma 9>;
366 dma-names = "rx", "tx";
330 status = "disabled"; 367 status = "disabled";
331 }; 368 };
332 369
@@ -335,8 +372,11 @@
335 reg = <0x70006200 0x100>; 372 reg = <0x70006200 0x100>;
336 reg-shift = <2>; 373 reg-shift = <2>;
337 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 374 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
338 nvidia,dma-request-selector = <&apbdma 10>;
339 clocks = <&tegra_car TEGRA30_CLK_UARTC>; 375 clocks = <&tegra_car TEGRA30_CLK_UARTC>;
376 resets = <&tegra_car 55>;
377 reset-names = "serial";
378 dmas = <&apbdma 10>, <&apbdma 10>;
379 dma-names = "rx", "tx";
340 status = "disabled"; 380 status = "disabled";
341 }; 381 };
342 382
@@ -345,8 +385,11 @@
345 reg = <0x70006300 0x100>; 385 reg = <0x70006300 0x100>;
346 reg-shift = <2>; 386 reg-shift = <2>;
347 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 387 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
348 nvidia,dma-request-selector = <&apbdma 19>;
349 clocks = <&tegra_car TEGRA30_CLK_UARTD>; 388 clocks = <&tegra_car TEGRA30_CLK_UARTD>;
389 resets = <&tegra_car 65>;
390 reset-names = "serial";
391 dmas = <&apbdma 19>, <&apbdma 19>;
392 dma-names = "rx", "tx";
350 status = "disabled"; 393 status = "disabled";
351 }; 394 };
352 395
@@ -355,20 +398,25 @@
355 reg = <0x70006400 0x100>; 398 reg = <0x70006400 0x100>;
356 reg-shift = <2>; 399 reg-shift = <2>;
357 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 400 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
358 nvidia,dma-request-selector = <&apbdma 20>;
359 clocks = <&tegra_car TEGRA30_CLK_UARTE>; 401 clocks = <&tegra_car TEGRA30_CLK_UARTE>;
402 resets = <&tegra_car 66>;
403 reset-names = "serial";
404 dmas = <&apbdma 20>, <&apbdma 20>;
405 dma-names = "rx", "tx";
360 status = "disabled"; 406 status = "disabled";
361 }; 407 };
362 408
363 pwm: pwm { 409 pwm: pwm@7000a000 {
364 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm"; 410 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
365 reg = <0x7000a000 0x100>; 411 reg = <0x7000a000 0x100>;
366 #pwm-cells = <2>; 412 #pwm-cells = <2>;
367 clocks = <&tegra_car TEGRA30_CLK_PWM>; 413 clocks = <&tegra_car TEGRA30_CLK_PWM>;
414 resets = <&tegra_car 17>;
415 reset-names = "pwm";
368 status = "disabled"; 416 status = "disabled";
369 }; 417 };
370 418
371 rtc { 419 rtc@7000e000 {
372 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc"; 420 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
373 reg = <0x7000e000 0x100>; 421 reg = <0x7000e000 0x100>;
374 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 422 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
@@ -384,6 +432,10 @@
384 clocks = <&tegra_car TEGRA30_CLK_I2C1>, 432 clocks = <&tegra_car TEGRA30_CLK_I2C1>,
385 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; 433 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
386 clock-names = "div-clk", "fast-clk"; 434 clock-names = "div-clk", "fast-clk";
435 resets = <&tegra_car 12>;
436 reset-names = "i2c";
437 dmas = <&apbdma 21>, <&apbdma 21>;
438 dma-names = "rx", "tx";
387 status = "disabled"; 439 status = "disabled";
388 }; 440 };
389 441
@@ -396,6 +448,10 @@
396 clocks = <&tegra_car TEGRA30_CLK_I2C2>, 448 clocks = <&tegra_car TEGRA30_CLK_I2C2>,
397 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; 449 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
398 clock-names = "div-clk", "fast-clk"; 450 clock-names = "div-clk", "fast-clk";
451 resets = <&tegra_car 54>;
452 reset-names = "i2c";
453 dmas = <&apbdma 22>, <&apbdma 22>;
454 dma-names = "rx", "tx";
399 status = "disabled"; 455 status = "disabled";
400 }; 456 };
401 457
@@ -408,6 +464,10 @@
408 clocks = <&tegra_car TEGRA30_CLK_I2C3>, 464 clocks = <&tegra_car TEGRA30_CLK_I2C3>,
409 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; 465 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
410 clock-names = "div-clk", "fast-clk"; 466 clock-names = "div-clk", "fast-clk";
467 resets = <&tegra_car 67>;
468 reset-names = "i2c";
469 dmas = <&apbdma 23>, <&apbdma 23>;
470 dma-names = "rx", "tx";
411 status = "disabled"; 471 status = "disabled";
412 }; 472 };
413 473
@@ -419,7 +479,11 @@
419 #size-cells = <0>; 479 #size-cells = <0>;
420 clocks = <&tegra_car TEGRA30_CLK_I2C4>, 480 clocks = <&tegra_car TEGRA30_CLK_I2C4>,
421 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; 481 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
482 resets = <&tegra_car 103>;
483 reset-names = "i2c";
422 clock-names = "div-clk", "fast-clk"; 484 clock-names = "div-clk", "fast-clk";
485 dmas = <&apbdma 26>, <&apbdma 26>;
486 dma-names = "rx", "tx";
423 status = "disabled"; 487 status = "disabled";
424 }; 488 };
425 489
@@ -432,6 +496,10 @@
432 clocks = <&tegra_car TEGRA30_CLK_I2C5>, 496 clocks = <&tegra_car TEGRA30_CLK_I2C5>,
433 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; 497 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
434 clock-names = "div-clk", "fast-clk"; 498 clock-names = "div-clk", "fast-clk";
499 resets = <&tegra_car 47>;
500 reset-names = "i2c";
501 dmas = <&apbdma 24>, <&apbdma 24>;
502 dma-names = "rx", "tx";
435 status = "disabled"; 503 status = "disabled";
436 }; 504 };
437 505
@@ -439,10 +507,13 @@
439 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; 507 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
440 reg = <0x7000d400 0x200>; 508 reg = <0x7000d400 0x200>;
441 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 509 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
442 nvidia,dma-request-selector = <&apbdma 15>;
443 #address-cells = <1>; 510 #address-cells = <1>;
444 #size-cells = <0>; 511 #size-cells = <0>;
445 clocks = <&tegra_car TEGRA30_CLK_SBC1>; 512 clocks = <&tegra_car TEGRA30_CLK_SBC1>;
513 resets = <&tegra_car 41>;
514 reset-names = "spi";
515 dmas = <&apbdma 15>, <&apbdma 15>;
516 dma-names = "rx", "tx";
446 status = "disabled"; 517 status = "disabled";
447 }; 518 };
448 519
@@ -450,10 +521,13 @@
450 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; 521 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
451 reg = <0x7000d600 0x200>; 522 reg = <0x7000d600 0x200>;
452 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 523 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
453 nvidia,dma-request-selector = <&apbdma 16>;
454 #address-cells = <1>; 524 #address-cells = <1>;
455 #size-cells = <0>; 525 #size-cells = <0>;
456 clocks = <&tegra_car TEGRA30_CLK_SBC2>; 526 clocks = <&tegra_car TEGRA30_CLK_SBC2>;
527 resets = <&tegra_car 44>;
528 reset-names = "spi";
529 dmas = <&apbdma 16>, <&apbdma 16>;
530 dma-names = "rx", "tx";
457 status = "disabled"; 531 status = "disabled";
458 }; 532 };
459 533
@@ -461,10 +535,13 @@
461 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; 535 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
462 reg = <0x7000d800 0x200>; 536 reg = <0x7000d800 0x200>;
463 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 537 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
464 nvidia,dma-request-selector = <&apbdma 17>;
465 #address-cells = <1>; 538 #address-cells = <1>;
466 #size-cells = <0>; 539 #size-cells = <0>;
467 clocks = <&tegra_car TEGRA30_CLK_SBC3>; 540 clocks = <&tegra_car TEGRA30_CLK_SBC3>;
541 resets = <&tegra_car 46>;
542 reset-names = "spi";
543 dmas = <&apbdma 17>, <&apbdma 17>;
544 dma-names = "rx", "tx";
468 status = "disabled"; 545 status = "disabled";
469 }; 546 };
470 547
@@ -472,10 +549,13 @@
472 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; 549 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
473 reg = <0x7000da00 0x200>; 550 reg = <0x7000da00 0x200>;
474 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 551 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
475 nvidia,dma-request-selector = <&apbdma 18>;
476 #address-cells = <1>; 552 #address-cells = <1>;
477 #size-cells = <0>; 553 #size-cells = <0>;
478 clocks = <&tegra_car TEGRA30_CLK_SBC4>; 554 clocks = <&tegra_car TEGRA30_CLK_SBC4>;
555 resets = <&tegra_car 68>;
556 reset-names = "spi";
557 dmas = <&apbdma 18>, <&apbdma 18>;
558 dma-names = "rx", "tx";
479 status = "disabled"; 559 status = "disabled";
480 }; 560 };
481 561
@@ -483,10 +563,13 @@
483 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; 563 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
484 reg = <0x7000dc00 0x200>; 564 reg = <0x7000dc00 0x200>;
485 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 565 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
486 nvidia,dma-request-selector = <&apbdma 27>;
487 #address-cells = <1>; 566 #address-cells = <1>;
488 #size-cells = <0>; 567 #size-cells = <0>;
489 clocks = <&tegra_car TEGRA30_CLK_SBC5>; 568 clocks = <&tegra_car TEGRA30_CLK_SBC5>;
569 resets = <&tegra_car 104>;
570 reset-names = "spi";
571 dmas = <&apbdma 27>, <&apbdma 27>;
572 dma-names = "rx", "tx";
490 status = "disabled"; 573 status = "disabled";
491 }; 574 };
492 575
@@ -494,29 +577,34 @@
494 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; 577 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
495 reg = <0x7000de00 0x200>; 578 reg = <0x7000de00 0x200>;
496 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 579 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
497 nvidia,dma-request-selector = <&apbdma 28>;
498 #address-cells = <1>; 580 #address-cells = <1>;
499 #size-cells = <0>; 581 #size-cells = <0>;
500 clocks = <&tegra_car TEGRA30_CLK_SBC6>; 582 clocks = <&tegra_car TEGRA30_CLK_SBC6>;
583 resets = <&tegra_car 106>;
584 reset-names = "spi";
585 dmas = <&apbdma 28>, <&apbdma 28>;
586 dma-names = "rx", "tx";
501 status = "disabled"; 587 status = "disabled";
502 }; 588 };
503 589
504 kbc { 590 kbc@7000e200 {
505 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc"; 591 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
506 reg = <0x7000e200 0x100>; 592 reg = <0x7000e200 0x100>;
507 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 593 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
508 clocks = <&tegra_car TEGRA30_CLK_KBC>; 594 clocks = <&tegra_car TEGRA30_CLK_KBC>;
595 resets = <&tegra_car 36>;
596 reset-names = "kbc";
509 status = "disabled"; 597 status = "disabled";
510 }; 598 };
511 599
512 pmc { 600 pmc@7000e400 {
513 compatible = "nvidia,tegra30-pmc"; 601 compatible = "nvidia,tegra30-pmc";
514 reg = <0x7000e400 0x400>; 602 reg = <0x7000e400 0x400>;
515 clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>; 603 clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
516 clock-names = "pclk", "clk32k_in"; 604 clock-names = "pclk", "clk32k_in";
517 }; 605 };
518 606
519 memory-controller { 607 memory-controller@7000f000 {
520 compatible = "nvidia,tegra30-mc"; 608 compatible = "nvidia,tegra30-mc";
521 reg = <0x7000f000 0x010 609 reg = <0x7000f000 0x010
522 0x7000f03c 0x1b4 610 0x7000f03c 0x1b4
@@ -525,7 +613,7 @@
525 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 613 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
526 }; 614 };
527 615
528 iommu { 616 iommu@7000f010 {
529 compatible = "nvidia,tegra30-smmu"; 617 compatible = "nvidia,tegra30-smmu";
530 reg = <0x7000f010 0x02c 618 reg = <0x7000f010 0x02c
531 0x7000f1f0 0x010 619 0x7000f1f0 0x010
@@ -535,26 +623,34 @@
535 nvidia,ahb = <&ahb>; 623 nvidia,ahb = <&ahb>;
536 }; 624 };
537 625
538 ahub { 626 ahub@70080000 {
539 compatible = "nvidia,tegra30-ahub"; 627 compatible = "nvidia,tegra30-ahub";
540 reg = <0x70080000 0x200 628 reg = <0x70080000 0x200
541 0x70080200 0x100>; 629 0x70080200 0x100>;
542 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 630 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
543 nvidia,dma-request-selector = <&apbdma 1>;
544 clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>, 631 clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
545 <&tegra_car TEGRA30_CLK_APBIF>, 632 <&tegra_car TEGRA30_CLK_APBIF>;
546 <&tegra_car TEGRA30_CLK_I2S0>, 633 clock-names = "d_audio", "apbif";
547 <&tegra_car TEGRA30_CLK_I2S1>, 634 resets = <&tegra_car 106>, /* d_audio */
548 <&tegra_car TEGRA30_CLK_I2S2>, 635 <&tegra_car 107>, /* apbif */
549 <&tegra_car TEGRA30_CLK_I2S3>, 636 <&tegra_car 30>, /* i2s0 */
550 <&tegra_car TEGRA30_CLK_I2S4>, 637 <&tegra_car 11>, /* i2s1 */
551 <&tegra_car TEGRA30_CLK_DAM0>, 638 <&tegra_car 18>, /* i2s2 */
552 <&tegra_car TEGRA30_CLK_DAM1>, 639 <&tegra_car 101>, /* i2s3 */
553 <&tegra_car TEGRA30_CLK_DAM2>, 640 <&tegra_car 102>, /* i2s4 */
554 <&tegra_car TEGRA30_CLK_SPDIF_IN>; 641 <&tegra_car 108>, /* dam0 */
555 clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", 642 <&tegra_car 109>, /* dam1 */
643 <&tegra_car 110>, /* dam2 */
644 <&tegra_car 10>; /* spdif */
645 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
556 "i2s3", "i2s4", "dam0", "dam1", "dam2", 646 "i2s3", "i2s4", "dam0", "dam1", "dam2",
557 "spdif_in"; 647 "spdif";
648 dmas = <&apbdma 1>, <&apbdma 1>,
649 <&apbdma 2>, <&apbdma 2>,
650 <&apbdma 3>, <&apbdma 3>,
651 <&apbdma 4>, <&apbdma 4>;
652 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
653 "rx3", "tx3";
558 ranges; 654 ranges;
559 #address-cells = <1>; 655 #address-cells = <1>;
560 #size-cells = <1>; 656 #size-cells = <1>;
@@ -564,6 +660,8 @@
564 reg = <0x70080300 0x100>; 660 reg = <0x70080300 0x100>;
565 nvidia,ahub-cif-ids = <4 4>; 661 nvidia,ahub-cif-ids = <4 4>;
566 clocks = <&tegra_car TEGRA30_CLK_I2S0>; 662 clocks = <&tegra_car TEGRA30_CLK_I2S0>;
663 resets = <&tegra_car 30>;
664 reset-names = "i2s";
567 status = "disabled"; 665 status = "disabled";
568 }; 666 };
569 667
@@ -572,6 +670,8 @@
572 reg = <0x70080400 0x100>; 670 reg = <0x70080400 0x100>;
573 nvidia,ahub-cif-ids = <5 5>; 671 nvidia,ahub-cif-ids = <5 5>;
574 clocks = <&tegra_car TEGRA30_CLK_I2S1>; 672 clocks = <&tegra_car TEGRA30_CLK_I2S1>;
673 resets = <&tegra_car 11>;
674 reset-names = "i2s";
575 status = "disabled"; 675 status = "disabled";
576 }; 676 };
577 677
@@ -580,6 +680,8 @@
580 reg = <0x70080500 0x100>; 680 reg = <0x70080500 0x100>;
581 nvidia,ahub-cif-ids = <6 6>; 681 nvidia,ahub-cif-ids = <6 6>;
582 clocks = <&tegra_car TEGRA30_CLK_I2S2>; 682 clocks = <&tegra_car TEGRA30_CLK_I2S2>;
683 resets = <&tegra_car 18>;
684 reset-names = "i2s";
583 status = "disabled"; 685 status = "disabled";
584 }; 686 };
585 687
@@ -588,6 +690,8 @@
588 reg = <0x70080600 0x100>; 690 reg = <0x70080600 0x100>;
589 nvidia,ahub-cif-ids = <7 7>; 691 nvidia,ahub-cif-ids = <7 7>;
590 clocks = <&tegra_car TEGRA30_CLK_I2S3>; 692 clocks = <&tegra_car TEGRA30_CLK_I2S3>;
693 resets = <&tegra_car 101>;
694 reset-names = "i2s";
591 status = "disabled"; 695 status = "disabled";
592 }; 696 };
593 697
@@ -596,6 +700,8 @@
596 reg = <0x70080700 0x100>; 700 reg = <0x70080700 0x100>;
597 nvidia,ahub-cif-ids = <8 8>; 701 nvidia,ahub-cif-ids = <8 8>;
598 clocks = <&tegra_car TEGRA30_CLK_I2S4>; 702 clocks = <&tegra_car TEGRA30_CLK_I2S4>;
703 resets = <&tegra_car 102>;
704 reset-names = "i2s";
599 status = "disabled"; 705 status = "disabled";
600 }; 706 };
601 }; 707 };
@@ -605,6 +711,8 @@
605 reg = <0x78000000 0x200>; 711 reg = <0x78000000 0x200>;
606 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 712 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
607 clocks = <&tegra_car TEGRA30_CLK_SDMMC1>; 713 clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
714 resets = <&tegra_car 14>;
715 reset-names = "sdhci";
608 status = "disabled"; 716 status = "disabled";
609 }; 717 };
610 718
@@ -613,6 +721,8 @@
613 reg = <0x78000200 0x200>; 721 reg = <0x78000200 0x200>;
614 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 722 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
615 clocks = <&tegra_car TEGRA30_CLK_SDMMC2>; 723 clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
724 resets = <&tegra_car 9>;
725 reset-names = "sdhci";
616 status = "disabled"; 726 status = "disabled";
617 }; 727 };
618 728
@@ -621,6 +731,8 @@
621 reg = <0x78000400 0x200>; 731 reg = <0x78000400 0x200>;
622 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 732 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
623 clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; 733 clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
734 resets = <&tegra_car 69>;
735 reset-names = "sdhci";
624 status = "disabled"; 736 status = "disabled";
625 }; 737 };
626 738
@@ -629,6 +741,8 @@
629 reg = <0x78000600 0x200>; 741 reg = <0x78000600 0x200>;
630 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 742 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
631 clocks = <&tegra_car TEGRA30_CLK_SDMMC4>; 743 clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
744 resets = <&tegra_car 15>;
745 reset-names = "sdhci";
632 status = "disabled"; 746 status = "disabled";
633 }; 747 };
634 748
@@ -638,6 +752,8 @@
638 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 752 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
639 phy_type = "utmi"; 753 phy_type = "utmi";
640 clocks = <&tegra_car TEGRA30_CLK_USBD>; 754 clocks = <&tegra_car TEGRA30_CLK_USBD>;
755 resets = <&tegra_car 22>;
756 reset-names = "usb";
641 nvidia,needs-double-reset; 757 nvidia,needs-double-reset;
642 nvidia,phy = <&phy1>; 758 nvidia,phy = <&phy1>;
643 status = "disabled"; 759 status = "disabled";
@@ -669,20 +785,33 @@
669 compatible = "nvidia,tegra30-ehci", "usb-ehci"; 785 compatible = "nvidia,tegra30-ehci", "usb-ehci";
670 reg = <0x7d004000 0x4000>; 786 reg = <0x7d004000 0x4000>;
671 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 787 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
672 phy_type = "ulpi"; 788 phy_type = "utmi";
673 clocks = <&tegra_car TEGRA30_CLK_USB2>; 789 clocks = <&tegra_car TEGRA30_CLK_USB2>;
790 resets = <&tegra_car 58>;
791 reset-names = "usb";
674 nvidia,phy = <&phy2>; 792 nvidia,phy = <&phy2>;
675 status = "disabled"; 793 status = "disabled";
676 }; 794 };
677 795
678 phy2: usb-phy@7d004000 { 796 phy2: usb-phy@7d004000 {
679 compatible = "nvidia,tegra30-usb-phy"; 797 compatible = "nvidia,tegra30-usb-phy";
680 reg = <0x7d004000 0x4000>; 798 reg = <0x7d004000 0x4000 0x7d000000 0x4000>;
681 phy_type = "ulpi"; 799 phy_type = "utmi";
682 clocks = <&tegra_car TEGRA30_CLK_USB2>, 800 clocks = <&tegra_car TEGRA30_CLK_USB2>,
683 <&tegra_car TEGRA30_CLK_PLL_U>, 801 <&tegra_car TEGRA30_CLK_PLL_U>,
684 <&tegra_car TEGRA30_CLK_CDEV2>; 802 <&tegra_car TEGRA30_CLK_USBD>;
685 clock-names = "reg", "pll_u", "ulpi-link"; 803 clock-names = "reg", "pll_u", "utmi-pads";
804 nvidia,hssync-start-delay = <9>;
805 nvidia,idle-wait-delay = <17>;
806 nvidia,elastic-limit = <16>;
807 nvidia,term-range-adj = <6>;
808 nvidia,xcvr-setup = <51>;
809 nvidia.xcvr-setup-use-fuses;
810 nvidia,xcvr-lsfslew = <2>;
811 nvidia,xcvr-lsrslew = <2>;
812 nvidia,xcvr-hsslew = <32>;
813 nvidia,hssquelch-level = <2>;
814 nvidia,hsdiscon-level = <5>;
686 status = "disabled"; 815 status = "disabled";
687 }; 816 };
688 817
@@ -692,6 +821,8 @@
692 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 821 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
693 phy_type = "utmi"; 822 phy_type = "utmi";
694 clocks = <&tegra_car TEGRA30_CLK_USB3>; 823 clocks = <&tegra_car TEGRA30_CLK_USB3>;
824 resets = <&tegra_car 59>;
825 reset-names = "usb";
695 nvidia,phy = <&phy3>; 826 nvidia,phy = <&phy3>;
696 status = "disabled"; 827 status = "disabled";
697 }; 828 };
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index e7f73b2e4550..5d7681be0580 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -15,6 +15,25 @@
15/ { 15/ {
16 compatible = "xlnx,zynq-7000"; 16 compatible = "xlnx,zynq-7000";
17 17
18 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
21
22 cpu@0 {
23 compatible = "arm,cortex-a9";
24 device_type = "cpu";
25 reg = <0>;
26 clocks = <&clkc 3>;
27 };
28
29 cpu@1 {
30 compatible = "arm,cortex-a9";
31 device_type = "cpu";
32 reg = <1>;
33 clocks = <&clkc 3>;
34 };
35 };
36
18 pmu { 37 pmu {
19 compatible = "arm,cortex-a9-pmu"; 38 compatible = "arm,cortex-a9-pmu";
20 interrupts = <0 5 4>, <0 6 4>; 39 interrupts = <0 5 4>, <0 6 4>;
@@ -65,6 +84,24 @@
65 interrupts = <0 50 4>; 84 interrupts = <0 50 4>;
66 }; 85 };
67 86
87 gem0: ethernet@e000b000 {
88 compatible = "cdns,gem";
89 reg = <0xe000b000 0x4000>;
90 status = "disabled";
91 interrupts = <0 22 4>;
92 clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
93 clock-names = "pclk", "hclk", "tx_clk";
94 };
95
96 gem1: ethernet@e000c000 {
97 compatible = "cdns,gem";
98 reg = <0xe000c000 0x4000>;
99 status = "disabled";
100 interrupts = <0 45 4>;
101 clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
102 clock-names = "pclk", "hclk", "tx_clk";
103 };
104
68 slcr: slcr@f8000000 { 105 slcr: slcr@f8000000 {
69 compatible = "xlnx,zynq-slcr"; 106 compatible = "xlnx,zynq-slcr";
70 reg = <0xF8000000 0x1000>; 107 reg = <0xF8000000 0x1000>;
@@ -106,7 +143,6 @@
106 compatible = "cdns,ttc"; 143 compatible = "cdns,ttc";
107 clocks = <&clkc 6>; 144 clocks = <&clkc 6>;
108 reg = <0xF8001000 0x1000>; 145 reg = <0xF8001000 0x1000>;
109 clock-ranges;
110 }; 146 };
111 147
112 ttc1: ttc1@f8002000 { 148 ttc1: ttc1@f8002000 {
@@ -115,7 +151,6 @@
115 compatible = "cdns,ttc"; 151 compatible = "cdns,ttc";
116 clocks = <&clkc 6>; 152 clocks = <&clkc 6>;
117 reg = <0xF8002000 0x1000>; 153 reg = <0xF8002000 0x1000>;
118 clock-ranges;
119 }; 154 };
120 scutimer: scutimer@f8f00600 { 155 scutimer: scutimer@f8f00600 {
121 interrupt-parent = <&intc>; 156 interrupt-parent = <&intc>;
diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts
index 21aea99a067b..34d680a46b7e 100644
--- a/arch/arm/boot/dts/zynq-zc702.dts
+++ b/arch/arm/boot/dts/zynq-zc702.dts
@@ -29,6 +29,11 @@
29 29
30}; 30};
31 31
32&gem0 {
33 status = "okay";
34 phy-mode = "rgmii";
35};
36
32&uart1 { 37&uart1 {
33 status = "okay"; 38 status = "okay";
34}; 39};
diff --git a/arch/arm/boot/dts/zynq-zc706.dts b/arch/arm/boot/dts/zynq-zc706.dts
index 79009e0b74b9..b2835d5fc09a 100644
--- a/arch/arm/boot/dts/zynq-zc706.dts
+++ b/arch/arm/boot/dts/zynq-zc706.dts
@@ -30,6 +30,11 @@
30 30
31}; 31};
32 32
33&gem0 {
34 status = "okay";
35 phy-mode = "rgmii";
36};
37
33&uart1 { 38&uart1 {
34 status = "okay"; 39 status = "okay";
35}; 40};
diff --git a/arch/arm/boot/dts/zynq-zed.dts b/arch/arm/boot/dts/zynq-zed.dts
index d6acf2b1cdf4..2eda06889dfc 100644
--- a/arch/arm/boot/dts/zynq-zed.dts
+++ b/arch/arm/boot/dts/zynq-zed.dts
@@ -30,6 +30,11 @@
30 30
31}; 31};
32 32
33&gem0 {
34 status = "okay";
35 phy-mode = "rgmii";
36};
37
33&uart1 { 38&uart1 {
34 status = "okay"; 39 status = "okay";
35}; 40};
diff --git a/arch/arm/configs/ape6evm_defconfig b/arch/arm/configs/ape6evm_defconfig
index 1ce39940795d..cb26c62dc722 100644
--- a/arch/arm/configs/ape6evm_defconfig
+++ b/arch/arm/configs/ape6evm_defconfig
@@ -13,7 +13,7 @@ CONFIG_EMBEDDED=y
13CONFIG_PERF_EVENTS=y 13CONFIG_PERF_EVENTS=y
14CONFIG_SLAB=y 14CONFIG_SLAB=y
15# CONFIG_BLOCK is not set 15# CONFIG_BLOCK is not set
16CONFIG_ARCH_SHMOBILE=y 16CONFIG_ARCH_SHMOBILE_LEGACY=y
17CONFIG_ARCH_R8A73A4=y 17CONFIG_ARCH_R8A73A4=y
18CONFIG_MACH_APE6EVM=y 18CONFIG_MACH_APE6EVM=y
19# CONFIG_ARM_THUMB is not set 19# CONFIG_ARM_THUMB is not set
diff --git a/arch/arm/configs/armadillo800eva_defconfig b/arch/arm/configs/armadillo800eva_defconfig
index fae939d3d7f0..5abf1a2e3160 100644
--- a/arch/arm/configs/armadillo800eva_defconfig
+++ b/arch/arm/configs/armadillo800eva_defconfig
@@ -15,7 +15,7 @@ CONFIG_MODULE_FORCE_UNLOAD=y
15# CONFIG_BLK_DEV_BSG is not set 15# CONFIG_BLK_DEV_BSG is not set
16# CONFIG_IOSCHED_DEADLINE is not set 16# CONFIG_IOSCHED_DEADLINE is not set
17# CONFIG_IOSCHED_CFQ is not set 17# CONFIG_IOSCHED_CFQ is not set
18CONFIG_ARCH_SHMOBILE=y 18CONFIG_ARCH_SHMOBILE_LEGACY=y
19CONFIG_ARCH_R8A7740=y 19CONFIG_ARCH_R8A7740=y
20CONFIG_MACH_ARMADILLO800EVA=y 20CONFIG_MACH_ARMADILLO800EVA=y
21# CONFIG_SH_TIMER_TMU is not set 21# CONFIG_SH_TIMER_TMU is not set
diff --git a/arch/arm/configs/bockw_defconfig b/arch/arm/configs/bockw_defconfig
index b38cd107f82d..1dd39716d7cb 100644
--- a/arch/arm/configs/bockw_defconfig
+++ b/arch/arm/configs/bockw_defconfig
@@ -8,7 +8,7 @@ CONFIG_SYSCTL_SYSCALL=y
8CONFIG_EMBEDDED=y 8CONFIG_EMBEDDED=y
9CONFIG_SLAB=y 9CONFIG_SLAB=y
10# CONFIG_IOSCHED_CFQ is not set 10# CONFIG_IOSCHED_CFQ is not set
11CONFIG_ARCH_SHMOBILE=y 11CONFIG_ARCH_SHMOBILE_LEGACY=y
12CONFIG_ARCH_R8A7778=y 12CONFIG_ARCH_R8A7778=y
13CONFIG_MACH_BOCKW=y 13CONFIG_MACH_BOCKW=y
14CONFIG_MEMORY_START=0x60000000 14CONFIG_MEMORY_START=0x60000000
diff --git a/arch/arm/configs/koelsch_defconfig b/arch/arm/configs/koelsch_defconfig
index 825c16dee8a0..7fd65a01ec7e 100644
--- a/arch/arm/configs/koelsch_defconfig
+++ b/arch/arm/configs/koelsch_defconfig
@@ -9,7 +9,7 @@ CONFIG_EMBEDDED=y
9CONFIG_PERF_EVENTS=y 9CONFIG_PERF_EVENTS=y
10CONFIG_SLAB=y 10CONFIG_SLAB=y
11# CONFIG_BLOCK is not set 11# CONFIG_BLOCK is not set
12CONFIG_ARCH_SHMOBILE=y 12CONFIG_ARCH_SHMOBILE_LEGACY=y
13CONFIG_ARCH_R8A7791=y 13CONFIG_ARCH_R8A7791=y
14CONFIG_MACH_KOELSCH=y 14CONFIG_MACH_KOELSCH=y
15# CONFIG_SWP_EMULATE is not set 15# CONFIG_SWP_EMULATE is not set
diff --git a/arch/arm/configs/kzm9d_defconfig b/arch/arm/configs/kzm9d_defconfig
index 6c37f4a98eb8..217f1dda2965 100644
--- a/arch/arm/configs/kzm9d_defconfig
+++ b/arch/arm/configs/kzm9d_defconfig
@@ -13,7 +13,7 @@ CONFIG_SLAB=y
13# CONFIG_BLK_DEV_BSG is not set 13# CONFIG_BLK_DEV_BSG is not set
14# CONFIG_IOSCHED_DEADLINE is not set 14# CONFIG_IOSCHED_DEADLINE is not set
15# CONFIG_IOSCHED_CFQ is not set 15# CONFIG_IOSCHED_CFQ is not set
16CONFIG_ARCH_SHMOBILE=y 16CONFIG_ARCH_SHMOBILE_LEGACY=y
17CONFIG_ARCH_EMEV2=y 17CONFIG_ARCH_EMEV2=y
18CONFIG_MACH_KZM9D=y 18CONFIG_MACH_KZM9D=y
19CONFIG_MEMORY_START=0x40000000 19CONFIG_MEMORY_START=0x40000000
diff --git a/arch/arm/configs/kzm9g_defconfig b/arch/arm/configs/kzm9g_defconfig
index 1ad028023a64..9934dbc23d64 100644
--- a/arch/arm/configs/kzm9g_defconfig
+++ b/arch/arm/configs/kzm9g_defconfig
@@ -22,7 +22,7 @@ CONFIG_MODULE_UNLOAD=y
22# CONFIG_BLK_DEV_BSG is not set 22# CONFIG_BLK_DEV_BSG is not set
23# CONFIG_IOSCHED_DEADLINE is not set 23# CONFIG_IOSCHED_DEADLINE is not set
24# CONFIG_IOSCHED_CFQ is not set 24# CONFIG_IOSCHED_CFQ is not set
25CONFIG_ARCH_SHMOBILE=y 25CONFIG_ARCH_SHMOBILE_LEGACY=y
26CONFIG_ARCH_SH73A0=y 26CONFIG_ARCH_SH73A0=y
27CONFIG_MACH_KZM9G=y 27CONFIG_MACH_KZM9G=y
28CONFIG_MEMORY_START=0x41000000 28CONFIG_MEMORY_START=0x41000000
diff --git a/arch/arm/configs/lager_defconfig b/arch/arm/configs/lager_defconfig
index 35bff5e0d57a..35dc8b2be47f 100644
--- a/arch/arm/configs/lager_defconfig
+++ b/arch/arm/configs/lager_defconfig
@@ -12,7 +12,7 @@ CONFIG_SLAB=y
12# CONFIG_BLK_DEV_BSG is not set 12# CONFIG_BLK_DEV_BSG is not set
13# CONFIG_IOSCHED_DEADLINE is not set 13# CONFIG_IOSCHED_DEADLINE is not set
14# CONFIG_IOSCHED_CFQ is not set 14# CONFIG_IOSCHED_CFQ is not set
15CONFIG_ARCH_SHMOBILE=y 15CONFIG_ARCH_SHMOBILE_LEGACY=y
16CONFIG_ARCH_R8A7790=y 16CONFIG_ARCH_R8A7790=y
17CONFIG_MACH_LAGER=y 17CONFIG_MACH_LAGER=y
18# CONFIG_SH_TIMER_TMU is not set 18# CONFIG_SH_TIMER_TMU is not set
diff --git a/arch/arm/configs/mackerel_defconfig b/arch/arm/configs/mackerel_defconfig
index 9fb11895b2e2..a61e1653fc5e 100644
--- a/arch/arm/configs/mackerel_defconfig
+++ b/arch/arm/configs/mackerel_defconfig
@@ -14,7 +14,7 @@ CONFIG_MODULE_UNLOAD=y
14# CONFIG_BLK_DEV_BSG is not set 14# CONFIG_BLK_DEV_BSG is not set
15# CONFIG_IOSCHED_DEADLINE is not set 15# CONFIG_IOSCHED_DEADLINE is not set
16# CONFIG_IOSCHED_CFQ is not set 16# CONFIG_IOSCHED_CFQ is not set
17CONFIG_ARCH_SHMOBILE=y 17CONFIG_ARCH_SHMOBILE_LEGACY=y
18CONFIG_ARCH_SH7372=y 18CONFIG_ARCH_SH7372=y
19CONFIG_MACH_MACKEREL=y 19CONFIG_MACH_MACKEREL=y
20CONFIG_MEMORY_SIZE=0x10000000 20CONFIG_MEMORY_SIZE=0x10000000
diff --git a/arch/arm/configs/marzen_defconfig b/arch/arm/configs/marzen_defconfig
index 5cc6360340b1..6981338cd08d 100644
--- a/arch/arm/configs/marzen_defconfig
+++ b/arch/arm/configs/marzen_defconfig
@@ -9,7 +9,7 @@ CONFIG_SYSCTL_SYSCALL=y
9CONFIG_EMBEDDED=y 9CONFIG_EMBEDDED=y
10CONFIG_SLAB=y 10CONFIG_SLAB=y
11# CONFIG_IOSCHED_CFQ is not set 11# CONFIG_IOSCHED_CFQ is not set
12CONFIG_ARCH_SHMOBILE=y 12CONFIG_ARCH_SHMOBILE_LEGACY=y
13CONFIG_ARCH_R8A7779=y 13CONFIG_ARCH_R8A7779=y
14CONFIG_MACH_MARZEN=y 14CONFIG_MACH_MARZEN=y
15CONFIG_MEMORY_START=0x60000000 15CONFIG_MEMORY_START=0x60000000
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 4a5903e04827..c1df4e9db140 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -69,6 +69,7 @@ CONFIG_KS8851=y
69CONFIG_SMSC911X=y 69CONFIG_SMSC911X=y
70CONFIG_STMMAC_ETH=y 70CONFIG_STMMAC_ETH=y
71CONFIG_MDIO_SUN4I=y 71CONFIG_MDIO_SUN4I=y
72CONFIG_TI_CPSW=y
72CONFIG_KEYBOARD_SPEAR=y 73CONFIG_KEYBOARD_SPEAR=y
73CONFIG_SERIO_AMBAKMI=y 74CONFIG_SERIO_AMBAKMI=y
74CONFIG_SERIAL_8250=y 75CONFIG_SERIAL_8250=y
@@ -133,12 +134,14 @@ CONFIG_USB_GPIO_VBUS=y
133CONFIG_USB_ISP1301=y 134CONFIG_USB_ISP1301=y
134CONFIG_USB_MXS_PHY=y 135CONFIG_USB_MXS_PHY=y
135CONFIG_MMC=y 136CONFIG_MMC=y
137CONFIG_MMC_BLOCK_MINORS=16
136CONFIG_MMC_ARMMMCI=y 138CONFIG_MMC_ARMMMCI=y
137CONFIG_MMC_SDHCI=y 139CONFIG_MMC_SDHCI=y
138CONFIG_MMC_SDHCI_PLTFM=y 140CONFIG_MMC_SDHCI_PLTFM=y
139CONFIG_MMC_SDHCI_ESDHC_IMX=y 141CONFIG_MMC_SDHCI_ESDHC_IMX=y
140CONFIG_MMC_SDHCI_TEGRA=y 142CONFIG_MMC_SDHCI_TEGRA=y
141CONFIG_MMC_SDHCI_SPEAR=y 143CONFIG_MMC_SDHCI_SPEAR=y
144CONFIG_MMC_SDHCI_BCM_KONA=y
142CONFIG_MMC_OMAP=y 145CONFIG_MMC_OMAP=y
143CONFIG_MMC_OMAP_HS=y 146CONFIG_MMC_OMAP_HS=y
144CONFIG_EDAC=y 147CONFIG_EDAC=y
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index 98a50c309b90..bfa80a11e8c7 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -173,6 +173,7 @@ CONFIG_MFD_PALMAS=y
173CONFIG_MFD_TPS65217=y 173CONFIG_MFD_TPS65217=y
174CONFIG_MFD_TPS65910=y 174CONFIG_MFD_TPS65910=y
175CONFIG_TWL6040_CORE=y 175CONFIG_TWL6040_CORE=y
176CONFIG_REGULATOR_FIXED_VOLTAGE=y
176CONFIG_REGULATOR_PALMAS=y 177CONFIG_REGULATOR_PALMAS=y
177CONFIG_REGULATOR_TPS65023=y 178CONFIG_REGULATOR_TPS65023=y
178CONFIG_REGULATOR_TPS6507X=y 179CONFIG_REGULATOR_TPS6507X=y
diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig
index d57a85badb5e..3e2259b60236 100644
--- a/arch/arm/configs/sunxi_defconfig
+++ b/arch/arm/configs/sunxi_defconfig
@@ -12,6 +12,9 @@ CONFIG_NET=y
12CONFIG_PACKET=y 12CONFIG_PACKET=y
13CONFIG_UNIX=y 13CONFIG_UNIX=y
14CONFIG_INET=y 14CONFIG_INET=y
15CONFIG_IP_PNP=y
16CONFIG_IP_PNP_DHCP=y
17CONFIG_IP_PNP_BOOTP=y
15# CONFIG_INET_XFRM_MODE_TRANSPORT is not set 18# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
16# CONFIG_INET_XFRM_MODE_TUNNEL is not set 19# CONFIG_INET_XFRM_MODE_TUNNEL is not set
17# CONFIG_INET_XFRM_MODE_BEET is not set 20# CONFIG_INET_XFRM_MODE_BEET is not set
@@ -58,4 +61,8 @@ CONFIG_LEDS_TRIGGER_HEARTBEAT=y
58CONFIG_LEDS_TRIGGER_DEFAULT_ON=y 61CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
59CONFIG_COMMON_CLK_DEBUG=y 62CONFIG_COMMON_CLK_DEBUG=y
60# CONFIG_IOMMU_SUPPORT is not set 63# CONFIG_IOMMU_SUPPORT is not set
64CONFIG_TMPFS=y
65CONFIG_NFS_FS=y
66CONFIG_ROOT_NFS=y
61CONFIG_NLS=y 67CONFIG_NLS=y
68CONFIG_PRINTK_TIME=y
diff --git a/arch/arm/configs/u8500_defconfig b/arch/arm/configs/u8500_defconfig
index ac632cc38f24..c6ebc184bf68 100644
--- a/arch/arm/configs/u8500_defconfig
+++ b/arch/arm/configs/u8500_defconfig
@@ -22,6 +22,7 @@ CONFIG_CMDLINE="root=/dev/ram0 console=ttyAMA2,115200n8"
22CONFIG_CPU_FREQ=y 22CONFIG_CPU_FREQ=y
23CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y 23CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
24CONFIG_CPU_IDLE=y 24CONFIG_CPU_IDLE=y
25CONFIG_ARM_U8500_CPUIDLE=y
25CONFIG_VFP=y 26CONFIG_VFP=y
26CONFIG_NEON=y 27CONFIG_NEON=y
27CONFIG_PM_RUNTIME=y 28CONFIG_PM_RUNTIME=y
@@ -109,6 +110,8 @@ CONFIG_EXT2_FS_SECURITY=y
109CONFIG_EXT3_FS=y 110CONFIG_EXT3_FS=y
110CONFIG_EXT4_FS=y 111CONFIG_EXT4_FS=y
111CONFIG_VFAT_FS=y 112CONFIG_VFAT_FS=y
113CONFIG_DEVTMPFS=y
114CONFIG_DEVTMPFS_MOUNT=y
112CONFIG_TMPFS=y 115CONFIG_TMPFS=y
113CONFIG_TMPFS_POSIX_ACL=y 116CONFIG_TMPFS_POSIX_ACL=y
114# CONFIG_MISC_FILESYSTEMS is not set 117# CONFIG_MISC_FILESYSTEMS is not set
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index be956dbf6bae..1571d126e9dd 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -61,7 +61,7 @@ extern void __pgd_error(const char *file, int line, pgd_t);
61 * mapping to be mapped at. This is particularly important for 61 * mapping to be mapped at. This is particularly important for
62 * non-high vector CPUs. 62 * non-high vector CPUs.
63 */ 63 */
64#define FIRST_USER_ADDRESS PAGE_SIZE 64#define FIRST_USER_ADDRESS (PAGE_SIZE * 2)
65 65
66/* 66/*
67 * Use TASK_SIZE as the ceiling argument for free_pgtables() and 67 * Use TASK_SIZE as the ceiling argument for free_pgtables() and
diff --git a/arch/arm/kernel/machine_kexec.c b/arch/arm/kernel/machine_kexec.c
index 57221e349a7c..f0d180d8b29f 100644
--- a/arch/arm/kernel/machine_kexec.c
+++ b/arch/arm/kernel/machine_kexec.c
@@ -14,11 +14,12 @@
14#include <asm/pgalloc.h> 14#include <asm/pgalloc.h>
15#include <asm/mmu_context.h> 15#include <asm/mmu_context.h>
16#include <asm/cacheflush.h> 16#include <asm/cacheflush.h>
17#include <asm/fncpy.h>
17#include <asm/mach-types.h> 18#include <asm/mach-types.h>
18#include <asm/smp_plat.h> 19#include <asm/smp_plat.h>
19#include <asm/system_misc.h> 20#include <asm/system_misc.h>
20 21
21extern const unsigned char relocate_new_kernel[]; 22extern void relocate_new_kernel(void);
22extern const unsigned int relocate_new_kernel_size; 23extern const unsigned int relocate_new_kernel_size;
23 24
24extern unsigned long kexec_start_address; 25extern unsigned long kexec_start_address;
@@ -142,6 +143,8 @@ void machine_kexec(struct kimage *image)
142{ 143{
143 unsigned long page_list; 144 unsigned long page_list;
144 unsigned long reboot_code_buffer_phys; 145 unsigned long reboot_code_buffer_phys;
146 unsigned long reboot_entry = (unsigned long)relocate_new_kernel;
147 unsigned long reboot_entry_phys;
145 void *reboot_code_buffer; 148 void *reboot_code_buffer;
146 149
147 /* 150 /*
@@ -168,16 +171,16 @@ void machine_kexec(struct kimage *image)
168 171
169 172
170 /* copy our kernel relocation code to the control code page */ 173 /* copy our kernel relocation code to the control code page */
171 memcpy(reboot_code_buffer, 174 reboot_entry = fncpy(reboot_code_buffer,
172 relocate_new_kernel, relocate_new_kernel_size); 175 reboot_entry,
176 relocate_new_kernel_size);
177 reboot_entry_phys = (unsigned long)reboot_entry +
178 (reboot_code_buffer_phys - (unsigned long)reboot_code_buffer);
173 179
174
175 flush_icache_range((unsigned long) reboot_code_buffer,
176 (unsigned long) reboot_code_buffer + KEXEC_CONTROL_PAGE_SIZE);
177 printk(KERN_INFO "Bye!\n"); 180 printk(KERN_INFO "Bye!\n");
178 181
179 if (kexec_reinit) 182 if (kexec_reinit)
180 kexec_reinit(); 183 kexec_reinit();
181 184
182 soft_restart(reboot_code_buffer_phys); 185 soft_restart(reboot_entry_phys);
183} 186}
diff --git a/arch/arm/kernel/relocate_kernel.S b/arch/arm/kernel/relocate_kernel.S
index d0cdedf4864d..95858966d84e 100644
--- a/arch/arm/kernel/relocate_kernel.S
+++ b/arch/arm/kernel/relocate_kernel.S
@@ -2,10 +2,12 @@
2 * relocate_kernel.S - put the kernel image in place to boot 2 * relocate_kernel.S - put the kernel image in place to boot
3 */ 3 */
4 4
5#include <linux/linkage.h>
5#include <asm/kexec.h> 6#include <asm/kexec.h>
6 7
7 .globl relocate_new_kernel 8 .align 3 /* not needed for this code, but keeps fncpy() happy */
8relocate_new_kernel: 9
10ENTRY(relocate_new_kernel)
9 11
10 ldr r0,kexec_indirection_page 12 ldr r0,kexec_indirection_page
11 ldr r1,kexec_start_address 13 ldr r1,kexec_start_address
@@ -79,6 +81,8 @@ kexec_mach_type:
79kexec_boot_atags: 81kexec_boot_atags:
80 .long 0x0 82 .long 0x0
81 83
84ENDPROC(relocate_new_kernel)
85
82relocate_new_kernel_end: 86relocate_new_kernel_end:
83 87
84 .globl relocate_new_kernel_size 88 .globl relocate_new_kernel_size
diff --git a/arch/arm/kernel/sigreturn_codes.S b/arch/arm/kernel/sigreturn_codes.S
index 3c5d0f2170fd..b84d0cb13682 100644
--- a/arch/arm/kernel/sigreturn_codes.S
+++ b/arch/arm/kernel/sigreturn_codes.S
@@ -30,6 +30,27 @@
30 * snippets. 30 * snippets.
31 */ 31 */
32 32
33/*
34 * In CPU_THUMBONLY case kernel arm opcodes are not allowed.
35 * Note in this case codes skips those instructions but it uses .org
36 * directive to keep correct layout of sigreturn_codes array.
37 */
38#ifndef CONFIG_CPU_THUMBONLY
39#define ARM_OK(code...) code
40#else
41#define ARM_OK(code...)
42#endif
43
44 .macro arm_slot n
45 .org sigreturn_codes + 12 * (\n)
46ARM_OK( .arm )
47 .endm
48
49 .macro thumb_slot n
50 .org sigreturn_codes + 12 * (\n) + 8
51 .thumb
52 .endm
53
33#if __LINUX_ARM_ARCH__ <= 4 54#if __LINUX_ARM_ARCH__ <= 4
34 /* 55 /*
35 * Note we manually set minimally required arch that supports 56 * Note we manually set minimally required arch that supports
@@ -45,26 +66,27 @@
45 .global sigreturn_codes 66 .global sigreturn_codes
46 .type sigreturn_codes, #object 67 .type sigreturn_codes, #object
47 68
48 .arm 69 .align
49 70
50sigreturn_codes: 71sigreturn_codes:
51 72
52 /* ARM sigreturn syscall code snippet */ 73 /* ARM sigreturn syscall code snippet */
53 mov r7, #(__NR_sigreturn - __NR_SYSCALL_BASE) 74 arm_slot 0
54 swi #(__NR_sigreturn)|(__NR_OABI_SYSCALL_BASE) 75ARM_OK( mov r7, #(__NR_sigreturn - __NR_SYSCALL_BASE) )
76ARM_OK( swi #(__NR_sigreturn)|(__NR_OABI_SYSCALL_BASE) )
55 77
56 /* Thumb sigreturn syscall code snippet */ 78 /* Thumb sigreturn syscall code snippet */
57 .thumb 79 thumb_slot 0
58 movs r7, #(__NR_sigreturn - __NR_SYSCALL_BASE) 80 movs r7, #(__NR_sigreturn - __NR_SYSCALL_BASE)
59 swi #0 81 swi #0
60 82
61 /* ARM sigreturn_rt syscall code snippet */ 83 /* ARM sigreturn_rt syscall code snippet */
62 .arm 84 arm_slot 1
63 mov r7, #(__NR_rt_sigreturn - __NR_SYSCALL_BASE) 85ARM_OK( mov r7, #(__NR_rt_sigreturn - __NR_SYSCALL_BASE) )
64 swi #(__NR_rt_sigreturn)|(__NR_OABI_SYSCALL_BASE) 86ARM_OK( swi #(__NR_rt_sigreturn)|(__NR_OABI_SYSCALL_BASE) )
65 87
66 /* Thumb sigreturn_rt syscall code snippet */ 88 /* Thumb sigreturn_rt syscall code snippet */
67 .thumb 89 thumb_slot 1
68 movs r7, #(__NR_rt_sigreturn - __NR_SYSCALL_BASE) 90 movs r7, #(__NR_rt_sigreturn - __NR_SYSCALL_BASE)
69 swi #0 91 swi #0
70 92
@@ -74,7 +96,7 @@ sigreturn_codes:
74 * it is thumb case or not, so we need additional 96 * it is thumb case or not, so we need additional
75 * word after real last entry. 97 * word after real last entry.
76 */ 98 */
77 .arm 99 arm_slot 2
78 .space 4 100 .space 4
79 101
80 .size sigreturn_codes, . - sigreturn_codes 102 .size sigreturn_codes, . - sigreturn_codes
diff --git a/arch/arm/lib/delay-loop.S b/arch/arm/lib/delay-loop.S
index 36b668d8e121..bc1033b897b4 100644
--- a/arch/arm/lib/delay-loop.S
+++ b/arch/arm/lib/delay-loop.S
@@ -40,6 +40,7 @@ ENTRY(__loop_const_udelay) @ 0 <= r0 <= 0x7fffff06
40/* 40/*
41 * loops = r0 * HZ * loops_per_jiffy / 1000000 41 * loops = r0 * HZ * loops_per_jiffy / 1000000
42 */ 42 */
43 .align 3
43 44
44@ Delay routine 45@ Delay routine
45ENTRY(__loop_delay) 46ENTRY(__loop_delay)
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 699b71e7f7ec..b4f7d6ffa30b 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -1,15 +1,33 @@
1if ARCH_AT91 1if ARCH_AT91
2 2
3config HAVE_AT91_UTMI
4 bool
5
6config HAVE_AT91_USB_CLK
7 bool
8
3config HAVE_AT91_DBGU0 9config HAVE_AT91_DBGU0
4 bool 10 bool
5 11
6config HAVE_AT91_DBGU1 12config HAVE_AT91_DBGU1
7 bool 13 bool
8 14
15config AT91_USE_OLD_CLK
16 bool
17
9config AT91_PMC_UNIT 18config AT91_PMC_UNIT
10 bool 19 bool
11 default !ARCH_AT91X40 20 default !ARCH_AT91X40
12 21
22config COMMON_CLK_AT91
23 bool
24 default AT91_PMC_UNIT && USE_OF && !AT91_USE_OLD_CLK
25 select COMMON_CLK
26
27config OLD_CLK_AT91
28 bool
29 default AT91_PMC_UNIT && AT91_USE_OLD_CLK
30
13config AT91_SAM9_ALT_RESET 31config AT91_SAM9_ALT_RESET
14 bool 32 bool
15 default !ARCH_AT91X40 33 default !ARCH_AT91X40
@@ -21,6 +39,9 @@ config AT91_SAM9G45_RESET
21config AT91_SAM9_TIME 39config AT91_SAM9_TIME
22 bool 40 bool
23 41
42config HAVE_AT91_SMD
43 bool
44
24config SOC_AT91SAM9 45config SOC_AT91SAM9
25 bool 46 bool
26 select AT91_SAM9_TIME 47 select AT91_SAM9_TIME
@@ -65,6 +86,9 @@ config SOC_SAMA5D3
65 select SOC_SAMA5 86 select SOC_SAMA5
66 select HAVE_FB_ATMEL 87 select HAVE_FB_ATMEL
67 select HAVE_AT91_DBGU1 88 select HAVE_AT91_DBGU1
89 select HAVE_AT91_UTMI
90 select HAVE_AT91_SMD
91 select HAVE_AT91_USB_CLK
68 help 92 help
69 Select this if you are using one of Atmel's SAMA5D3 family SoC. 93 Select this if you are using one of Atmel's SAMA5D3 family SoC.
70 This support covers SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35. 94 This support covers SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35.
@@ -78,11 +102,15 @@ config SOC_AT91RM9200
78 select HAVE_AT91_DBGU0 102 select HAVE_AT91_DBGU0
79 select MULTI_IRQ_HANDLER 103 select MULTI_IRQ_HANDLER
80 select SPARSE_IRQ 104 select SPARSE_IRQ
105 select AT91_USE_OLD_CLK
106 select HAVE_AT91_USB_CLK
81 107
82config SOC_AT91SAM9260 108config SOC_AT91SAM9260
83 bool "AT91SAM9260, AT91SAM9XE or AT91SAM9G20" 109 bool "AT91SAM9260, AT91SAM9XE or AT91SAM9G20"
84 select HAVE_AT91_DBGU0 110 select HAVE_AT91_DBGU0
85 select SOC_AT91SAM9 111 select SOC_AT91SAM9
112 select AT91_USE_OLD_CLK
113 select HAVE_AT91_USB_CLK
86 help 114 help
87 Select this if you are using one of Atmel's AT91SAM9260, AT91SAM9XE 115 Select this if you are using one of Atmel's AT91SAM9260, AT91SAM9XE
88 or AT91SAM9G20 SoC. 116 or AT91SAM9G20 SoC.
@@ -92,6 +120,8 @@ config SOC_AT91SAM9261
92 select HAVE_AT91_DBGU0 120 select HAVE_AT91_DBGU0
93 select HAVE_FB_ATMEL 121 select HAVE_FB_ATMEL
94 select SOC_AT91SAM9 122 select SOC_AT91SAM9
123 select AT91_USE_OLD_CLK
124 select HAVE_AT91_USB_CLK
95 help 125 help
96 Select this if you are using one of Atmel's AT91SAM9261 or AT91SAM9G10 SoC. 126 Select this if you are using one of Atmel's AT91SAM9261 or AT91SAM9G10 SoC.
97 127
@@ -100,18 +130,25 @@ config SOC_AT91SAM9263
100 select HAVE_AT91_DBGU1 130 select HAVE_AT91_DBGU1
101 select HAVE_FB_ATMEL 131 select HAVE_FB_ATMEL
102 select SOC_AT91SAM9 132 select SOC_AT91SAM9
133 select AT91_USE_OLD_CLK
134 select HAVE_AT91_USB_CLK
103 135
104config SOC_AT91SAM9RL 136config SOC_AT91SAM9RL
105 bool "AT91SAM9RL" 137 bool "AT91SAM9RL"
106 select HAVE_AT91_DBGU0 138 select HAVE_AT91_DBGU0
107 select HAVE_FB_ATMEL 139 select HAVE_FB_ATMEL
108 select SOC_AT91SAM9 140 select SOC_AT91SAM9
141 select AT91_USE_OLD_CLK
142 select HAVE_AT91_UTMI
109 143
110config SOC_AT91SAM9G45 144config SOC_AT91SAM9G45
111 bool "AT91SAM9G45 or AT91SAM9M10 families" 145 bool "AT91SAM9G45 or AT91SAM9M10 families"
112 select HAVE_AT91_DBGU1 146 select HAVE_AT91_DBGU1
113 select HAVE_FB_ATMEL 147 select HAVE_FB_ATMEL
114 select SOC_AT91SAM9 148 select SOC_AT91SAM9
149 select AT91_USE_OLD_CLK
150 select HAVE_AT91_UTMI
151 select HAVE_AT91_USB_CLK
115 help 152 help
116 Select this if you are using one of Atmel's AT91SAM9G45 family SoC. 153 Select this if you are using one of Atmel's AT91SAM9G45 family SoC.
117 This support covers AT91SAM9G45, AT91SAM9G46, AT91SAM9M10 and AT91SAM9M11. 154 This support covers AT91SAM9G45, AT91SAM9G46, AT91SAM9M10 and AT91SAM9M11.
@@ -121,6 +158,10 @@ config SOC_AT91SAM9X5
121 select HAVE_AT91_DBGU0 158 select HAVE_AT91_DBGU0
122 select HAVE_FB_ATMEL 159 select HAVE_FB_ATMEL
123 select SOC_AT91SAM9 160 select SOC_AT91SAM9
161 select AT91_USE_OLD_CLK
162 select HAVE_AT91_UTMI
163 select HAVE_AT91_SMD
164 select HAVE_AT91_USB_CLK
124 help 165 help
125 Select this if you are using one of Atmel's AT91SAM9x5 family SoC. 166 Select this if you are using one of Atmel's AT91SAM9x5 family SoC.
126 This means that your SAM9 name finishes with a '5' (except if it is 167 This means that your SAM9 name finishes with a '5' (except if it is
@@ -133,6 +174,8 @@ config SOC_AT91SAM9N12
133 select HAVE_AT91_DBGU0 174 select HAVE_AT91_DBGU0
134 select HAVE_FB_ATMEL 175 select HAVE_FB_ATMEL
135 select SOC_AT91SAM9 176 select SOC_AT91SAM9
177 select AT91_USE_OLD_CLK
178 select HAVE_AT91_USB_CLK
136 help 179 help
137 Select this if you are using Atmel's AT91SAM9N12 SoC. 180 Select this if you are using Atmel's AT91SAM9N12 SoC.
138 181
diff --git a/arch/arm/mach-at91/Kconfig.non_dt b/arch/arm/mach-at91/Kconfig.non_dt
index ca900be144ce..b736b571e882 100644
--- a/arch/arm/mach-at91/Kconfig.non_dt
+++ b/arch/arm/mach-at91/Kconfig.non_dt
@@ -12,26 +12,32 @@ config ARCH_AT91_NONE
12config ARCH_AT91RM9200 12config ARCH_AT91RM9200
13 bool "AT91RM9200" 13 bool "AT91RM9200"
14 select SOC_AT91RM9200 14 select SOC_AT91RM9200
15 select AT91_USE_OLD_CLK
15 16
16config ARCH_AT91SAM9260 17config ARCH_AT91SAM9260
17 bool "AT91SAM9260 or AT91SAM9XE or AT91SAM9G20" 18 bool "AT91SAM9260 or AT91SAM9XE or AT91SAM9G20"
18 select SOC_AT91SAM9260 19 select SOC_AT91SAM9260
20 select AT91_USE_OLD_CLK
19 21
20config ARCH_AT91SAM9261 22config ARCH_AT91SAM9261
21 bool "AT91SAM9261 or AT91SAM9G10" 23 bool "AT91SAM9261 or AT91SAM9G10"
22 select SOC_AT91SAM9261 24 select SOC_AT91SAM9261
25 select AT91_USE_OLD_CLK
23 26
24config ARCH_AT91SAM9263 27config ARCH_AT91SAM9263
25 bool "AT91SAM9263" 28 bool "AT91SAM9263"
26 select SOC_AT91SAM9263 29 select SOC_AT91SAM9263
30 select AT91_USE_OLD_CLK
27 31
28config ARCH_AT91SAM9RL 32config ARCH_AT91SAM9RL
29 bool "AT91SAM9RL" 33 bool "AT91SAM9RL"
30 select SOC_AT91SAM9RL 34 select SOC_AT91SAM9RL
35 select AT91_USE_OLD_CLK
31 36
32config ARCH_AT91SAM9G45 37config ARCH_AT91SAM9G45
33 bool "AT91SAM9G45" 38 bool "AT91SAM9G45"
34 select SOC_AT91SAM9G45 39 select SOC_AT91SAM9G45
40 select AT91_USE_OLD_CLK
35 41
36config ARCH_AT91X40 42config ARCH_AT91X40
37 bool "AT91x40" 43 bool "AT91x40"
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 90aab2d5a07f..705b38a179ec 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -7,7 +7,7 @@ obj-m :=
7obj-n := 7obj-n :=
8obj- := 8obj- :=
9 9
10obj-$(CONFIG_AT91_PMC_UNIT) += clock.o 10obj-$(CONFIG_OLD_CLK_AT91) += clock.o
11obj-$(CONFIG_AT91_SAM9_ALT_RESET) += at91sam9_alt_reset.o 11obj-$(CONFIG_AT91_SAM9_ALT_RESET) += at91sam9_alt_reset.o
12obj-$(CONFIG_AT91_SAM9G45_RESET) += at91sam9g45_reset.o 12obj-$(CONFIG_AT91_SAM9G45_RESET) += at91sam9g45_reset.o
13obj-$(CONFIG_AT91_SAM9_TIME) += at91sam926x_time.o 13obj-$(CONFIG_AT91_SAM9_TIME) += at91sam926x_time.o
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index 25805f2f6010..e47f5fd232f5 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -12,13 +12,13 @@
12 12
13#include <linux/module.h> 13#include <linux/module.h>
14#include <linux/reboot.h> 14#include <linux/reboot.h>
15#include <linux/clk/at91_pmc.h>
15 16
16#include <asm/irq.h> 17#include <asm/irq.h>
17#include <asm/mach/arch.h> 18#include <asm/mach/arch.h>
18#include <asm/mach/map.h> 19#include <asm/mach/map.h>
19#include <asm/system_misc.h> 20#include <asm/system_misc.h>
20#include <mach/at91rm9200.h> 21#include <mach/at91rm9200.h>
21#include <mach/at91_pmc.h>
22#include <mach/at91_st.h> 22#include <mach/at91_st.h>
23#include <mach/cpu.h> 23#include <mach/cpu.h>
24 24
diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c
index f607deb40f4d..bc7b363a3083 100644
--- a/arch/arm/mach-at91/at91rm9200_time.c
+++ b/arch/arm/mach-at91/at91rm9200_time.c
@@ -174,7 +174,6 @@ clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev)
174static struct clock_event_device clkevt = { 174static struct clock_event_device clkevt = {
175 .name = "at91_tick", 175 .name = "at91_tick",
176 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, 176 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
177 .shift = 32,
178 .rating = 150, 177 .rating = 150,
179 .set_next_event = clkevt32k_next_event, 178 .set_next_event = clkevt32k_next_event,
180 .set_mode = clkevt32k_mode, 179 .set_mode = clkevt32k_mode,
@@ -265,11 +264,9 @@ void __init at91rm9200_timer_init(void)
265 at91_st_write(AT91_ST_RTMR, 1); 264 at91_st_write(AT91_ST_RTMR, 1);
266 265
267 /* Setup timer clockevent, with minimum of two ticks (important!!) */ 266 /* Setup timer clockevent, with minimum of two ticks (important!!) */
268 clkevt.mult = div_sc(AT91_SLOW_CLOCK, NSEC_PER_SEC, clkevt.shift);
269 clkevt.max_delta_ns = clockevent_delta2ns(AT91_ST_ALMV, &clkevt);
270 clkevt.min_delta_ns = clockevent_delta2ns(2, &clkevt) + 1;
271 clkevt.cpumask = cpumask_of(0); 267 clkevt.cpumask = cpumask_of(0);
272 clockevents_register_device(&clkevt); 268 clockevents_config_and_register(&clkevt, AT91_SLOW_CLOCK,
269 2, AT91_ST_ALMV);
273 270
274 /* register clocksource */ 271 /* register clocksource */
275 clocksource_register_hz(&clk32k, AT91_SLOW_CLOCK); 272 clocksource_register_hz(&clk32k, AT91_SLOW_CLOCK);
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index d6a1fa85371d..6c821e562159 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -11,6 +11,7 @@
11 */ 11 */
12 12
13#include <linux/module.h> 13#include <linux/module.h>
14#include <linux/clk/at91_pmc.h>
14 15
15#include <asm/proc-fns.h> 16#include <asm/proc-fns.h>
16#include <asm/irq.h> 17#include <asm/irq.h>
@@ -20,7 +21,6 @@
20#include <mach/cpu.h> 21#include <mach/cpu.h>
21#include <mach/at91_dbgu.h> 22#include <mach/at91_dbgu.h>
22#include <mach/at91sam9260.h> 23#include <mach/at91sam9260.h>
23#include <mach/at91_pmc.h>
24 24
25#include "at91_aic.h" 25#include "at91_aic.h"
26#include "at91_rstc.h" 26#include "at91_rstc.h"
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index 23ba1d8a1531..6276b4c1acfe 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -11,6 +11,7 @@
11 */ 11 */
12 12
13#include <linux/module.h> 13#include <linux/module.h>
14#include <linux/clk/at91_pmc.h>
14 15
15#include <asm/proc-fns.h> 16#include <asm/proc-fns.h>
16#include <asm/irq.h> 17#include <asm/irq.h>
@@ -19,7 +20,6 @@
19#include <asm/system_misc.h> 20#include <asm/system_misc.h>
20#include <mach/cpu.h> 21#include <mach/cpu.h>
21#include <mach/at91sam9261.h> 22#include <mach/at91sam9261.h>
22#include <mach/at91_pmc.h>
23 23
24#include "at91_aic.h" 24#include "at91_aic.h"
25#include "at91_rstc.h" 25#include "at91_rstc.h"
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index 7eccb0fc57bc..37b90f4b990c 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -11,6 +11,7 @@
11 */ 11 */
12 12
13#include <linux/module.h> 13#include <linux/module.h>
14#include <linux/clk/at91_pmc.h>
14 15
15#include <asm/proc-fns.h> 16#include <asm/proc-fns.h>
16#include <asm/irq.h> 17#include <asm/irq.h>
@@ -18,7 +19,6 @@
18#include <asm/mach/map.h> 19#include <asm/mach/map.h>
19#include <asm/system_misc.h> 20#include <asm/system_misc.h>
20#include <mach/at91sam9263.h> 21#include <mach/at91sam9263.h>
21#include <mach/at91_pmc.h>
22 22
23#include "at91_aic.h" 23#include "at91_aic.h"
24#include "at91_rstc.h" 24#include "at91_rstc.h"
diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c
index bb392320a0dd..0f04ffe9c5a8 100644
--- a/arch/arm/mach-at91/at91sam926x_time.c
+++ b/arch/arm/mach-at91/at91sam926x_time.c
@@ -39,6 +39,7 @@
39static u32 pit_cycle; /* write-once */ 39static u32 pit_cycle; /* write-once */
40static u32 pit_cnt; /* access only w/system irq blocked */ 40static u32 pit_cnt; /* access only w/system irq blocked */
41static void __iomem *pit_base_addr __read_mostly; 41static void __iomem *pit_base_addr __read_mostly;
42static struct clk *mck;
42 43
43static inline unsigned int pit_read(unsigned int reg_offset) 44static inline unsigned int pit_read(unsigned int reg_offset)
44{ 45{
@@ -195,10 +196,14 @@ static int __init of_at91sam926x_pit_init(void)
195 if (!pit_base_addr) 196 if (!pit_base_addr)
196 goto node_err; 197 goto node_err;
197 198
199 mck = of_clk_get(np, 0);
200
198 /* Get the interrupts property */ 201 /* Get the interrupts property */
199 ret = irq_of_parse_and_map(np, 0); 202 ret = irq_of_parse_and_map(np, 0);
200 if (!ret) { 203 if (!ret) {
201 pr_crit("AT91: PIT: Unable to get IRQ from DT\n"); 204 pr_crit("AT91: PIT: Unable to get IRQ from DT\n");
205 if (!IS_ERR(mck))
206 clk_put(mck);
202 goto ioremap_err; 207 goto ioremap_err;
203 } 208 }
204 at91sam926x_pit_irq.irq = ret; 209 at91sam926x_pit_irq.irq = ret;
@@ -230,6 +235,8 @@ void __init at91sam926x_pit_init(void)
230 unsigned bits; 235 unsigned bits;
231 int ret; 236 int ret;
232 237
238 mck = ERR_PTR(-ENOENT);
239
233 /* For device tree enabled device: initialize here */ 240 /* For device tree enabled device: initialize here */
234 of_at91sam926x_pit_init(); 241 of_at91sam926x_pit_init();
235 242
@@ -237,7 +244,12 @@ void __init at91sam926x_pit_init(void)
237 * Use our actual MCK to figure out how many MCK/16 ticks per 244 * Use our actual MCK to figure out how many MCK/16 ticks per
238 * 1/HZ period (instead of a compile-time constant LATCH). 245 * 1/HZ period (instead of a compile-time constant LATCH).
239 */ 246 */
240 pit_rate = clk_get_rate(clk_get(NULL, "mck")) / 16; 247 if (IS_ERR(mck))
248 mck = clk_get(NULL, "mck");
249
250 if (IS_ERR(mck))
251 panic("AT91: PIT: Unable to get mck clk\n");
252 pit_rate = clk_get_rate(mck) / 16;
241 pit_cycle = (pit_rate + HZ/2) / HZ; 253 pit_cycle = (pit_rate + HZ/2) / HZ;
242 WARN_ON(((pit_cycle - 1) & ~AT91_PIT_PIV) != 0); 254 WARN_ON(((pit_cycle - 1) & ~AT91_PIT_PIV) != 0);
243 255
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 9405aa08b104..2f455ce35268 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -12,13 +12,13 @@
12 12
13#include <linux/module.h> 13#include <linux/module.h>
14#include <linux/dma-mapping.h> 14#include <linux/dma-mapping.h>
15#include <linux/clk/at91_pmc.h>
15 16
16#include <asm/irq.h> 17#include <asm/irq.h>
17#include <asm/mach/arch.h> 18#include <asm/mach/arch.h>
18#include <asm/mach/map.h> 19#include <asm/mach/map.h>
19#include <asm/system_misc.h> 20#include <asm/system_misc.h>
20#include <mach/at91sam9g45.h> 21#include <mach/at91sam9g45.h>
21#include <mach/at91_pmc.h>
22#include <mach/cpu.h> 22#include <mach/cpu.h>
23 23
24#include "at91_aic.h" 24#include "at91_aic.h"
diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c
index 388ec3aec4b9..4ef088c62eab 100644
--- a/arch/arm/mach-at91/at91sam9n12.c
+++ b/arch/arm/mach-at91/at91sam9n12.c
@@ -8,12 +8,12 @@
8 8
9#include <linux/module.h> 9#include <linux/module.h>
10#include <linux/dma-mapping.h> 10#include <linux/dma-mapping.h>
11#include <linux/clk/at91_pmc.h>
11 12
12#include <asm/irq.h> 13#include <asm/irq.h>
13#include <asm/mach/arch.h> 14#include <asm/mach/arch.h>
14#include <asm/mach/map.h> 15#include <asm/mach/map.h>
15#include <mach/at91sam9n12.h> 16#include <mach/at91sam9n12.h>
16#include <mach/at91_pmc.h>
17#include <mach/cpu.h> 17#include <mach/cpu.h>
18 18
19#include "board.h" 19#include "board.h"
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index 0750ffb7e6b1..3651517abedf 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -10,6 +10,7 @@
10 */ 10 */
11 11
12#include <linux/module.h> 12#include <linux/module.h>
13#include <linux/clk/at91_pmc.h>
13 14
14#include <asm/proc-fns.h> 15#include <asm/proc-fns.h>
15#include <asm/irq.h> 16#include <asm/irq.h>
@@ -19,7 +20,6 @@
19#include <mach/cpu.h> 20#include <mach/cpu.h>
20#include <mach/at91_dbgu.h> 21#include <mach/at91_dbgu.h>
21#include <mach/at91sam9rl.h> 22#include <mach/at91sam9rl.h>
22#include <mach/at91_pmc.h>
23 23
24#include "at91_aic.h" 24#include "at91_aic.h"
25#include "at91_rstc.h" 25#include "at91_rstc.h"
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index e8a2e075a1b8..3e8ec26e39dc 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -8,12 +8,12 @@
8 8
9#include <linux/module.h> 9#include <linux/module.h>
10#include <linux/dma-mapping.h> 10#include <linux/dma-mapping.h>
11#include <linux/clk/at91_pmc.h>
11 12
12#include <asm/irq.h> 13#include <asm/irq.h>
13#include <asm/mach/arch.h> 14#include <asm/mach/arch.h>
14#include <asm/mach/map.h> 15#include <asm/mach/map.h>
15#include <mach/at91sam9x5.h> 16#include <mach/at91sam9x5.h>
16#include <mach/at91_pmc.h>
17#include <mach/cpu.h> 17#include <mach/cpu.h>
18 18
19#include "board.h" 19#include "board.h"
diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c
index bf00d15d954d..075ec0576ada 100644
--- a/arch/arm/mach-at91/board-dt-sama5.c
+++ b/arch/arm/mach-at91/board-dt-sama5.c
@@ -16,6 +16,7 @@
16#include <linux/of_irq.h> 16#include <linux/of_irq.h>
17#include <linux/of_platform.h> 17#include <linux/of_platform.h>
18#include <linux/phy.h> 18#include <linux/phy.h>
19#include <linux/clk-provider.h>
19 20
20#include <asm/setup.h> 21#include <asm/setup.h>
21#include <asm/irq.h> 22#include <asm/irq.h>
@@ -26,6 +27,13 @@
26#include "at91_aic.h" 27#include "at91_aic.h"
27#include "generic.h" 28#include "generic.h"
28 29
30static void __init sama5_dt_timer_init(void)
31{
32#if defined(CONFIG_COMMON_CLK)
33 of_clk_init(NULL);
34#endif
35 at91sam926x_pit_init();
36}
29 37
30static const struct of_device_id irq_of_match[] __initconst = { 38static const struct of_device_id irq_of_match[] __initconst = {
31 39
@@ -72,7 +80,7 @@ static const char *sama5_dt_board_compat[] __initdata = {
72 80
73DT_MACHINE_START(sama5_dt, "Atmel SAMA5 (Device Tree)") 81DT_MACHINE_START(sama5_dt, "Atmel SAMA5 (Device Tree)")
74 /* Maintainer: Atmel */ 82 /* Maintainer: Atmel */
75 .init_time = at91sam926x_pit_init, 83 .init_time = sama5_dt_timer_init,
76 .map_io = at91_map_io, 84 .map_io = at91_map_io,
77 .handle_irq = at91_aic5_handle_irq, 85 .handle_irq = at91_aic5_handle_irq,
78 .init_early = at91_dt_initialize, 86 .init_early = at91_dt_initialize,
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index 6b2630a92f71..72b257944733 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -24,9 +24,9 @@
24#include <linux/clk.h> 24#include <linux/clk.h>
25#include <linux/io.h> 25#include <linux/io.h>
26#include <linux/of_address.h> 26#include <linux/of_address.h>
27#include <linux/clk/at91_pmc.h>
27 28
28#include <mach/hardware.h> 29#include <mach/hardware.h>
29#include <mach/at91_pmc.h>
30#include <mach/cpu.h> 30#include <mach/cpu.h>
31 31
32#include <asm/proc-fns.h> 32#include <asm/proc-fns.h>
@@ -884,6 +884,11 @@ static int __init at91_pmc_init(unsigned long main_clock)
884#if defined(CONFIG_OF) 884#if defined(CONFIG_OF)
885static struct of_device_id pmc_ids[] = { 885static struct of_device_id pmc_ids[] = {
886 { .compatible = "atmel,at91rm9200-pmc" }, 886 { .compatible = "atmel,at91rm9200-pmc" },
887 { .compatible = "atmel,at91sam9260-pmc" },
888 { .compatible = "atmel,at91sam9g45-pmc" },
889 { .compatible = "atmel,at91sam9n12-pmc" },
890 { .compatible = "atmel,at91sam9x5-pmc" },
891 { .compatible = "atmel,sama5d3-pmc" },
887 { /*sentinel*/ } 892 { /*sentinel*/ }
888}; 893};
889 894
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 26dee3ce9397..631fa3b8c16d 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -46,11 +46,12 @@ extern void at91sam926x_pit_init(void);
46extern void at91x40_timer_init(void); 46extern void at91x40_timer_init(void);
47 47
48 /* Clocks */ 48 /* Clocks */
49#ifdef CONFIG_AT91_PMC_UNIT 49#ifdef CONFIG_OLD_CLK_AT91
50extern int __init at91_clock_init(unsigned long main_clock); 50extern int __init at91_clock_init(unsigned long main_clock);
51extern int __init at91_dt_clock_init(void); 51extern int __init at91_dt_clock_init(void);
52#else 52#else
53static int inline at91_clock_init(unsigned long main_clock) { return 0; } 53static int inline at91_clock_init(unsigned long main_clock) { return 0; }
54static int inline at91_dt_clock_init(void) { return 0; }
54#endif 55#endif
55struct device; 56struct device;
56 57
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 9986542e8060..d43b79f56e94 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -19,13 +19,13 @@
19#include <linux/module.h> 19#include <linux/module.h>
20#include <linux/platform_device.h> 20#include <linux/platform_device.h>
21#include <linux/io.h> 21#include <linux/io.h>
22#include <linux/clk/at91_pmc.h>
22 23
23#include <asm/irq.h> 24#include <asm/irq.h>
24#include <linux/atomic.h> 25#include <linux/atomic.h>
25#include <asm/mach/time.h> 26#include <asm/mach/time.h>
26#include <asm/mach/irq.h> 27#include <asm/mach/irq.h>
27 28
28#include <mach/at91_pmc.h>
29#include <mach/cpu.h> 29#include <mach/cpu.h>
30 30
31#include "at91_aic.h" 31#include "at91_aic.h"
diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
index 3ed190ce062b..c5101dcb4fb0 100644
--- a/arch/arm/mach-at91/pm.h
+++ b/arch/arm/mach-at91/pm.h
@@ -16,7 +16,11 @@
16#include <mach/at91_ramc.h> 16#include <mach/at91_ramc.h>
17#include <mach/at91rm9200_sdramc.h> 17#include <mach/at91rm9200_sdramc.h>
18 18
19#ifdef CONFIG_PM
19extern void at91_pm_set_standby(void (*at91_standby)(void)); 20extern void at91_pm_set_standby(void (*at91_standby)(void));
21#else
22static inline void at91_pm_set_standby(void (*at91_standby)(void)) { }
23#endif
20 24
21/* 25/*
22 * The AT91RM9200 goes into self-refresh mode with this command, and will 26 * The AT91RM9200 goes into self-refresh mode with this command, and will
diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
index 098c28ddf025..20018779bae7 100644
--- a/arch/arm/mach-at91/pm_slowclock.S
+++ b/arch/arm/mach-at91/pm_slowclock.S
@@ -13,8 +13,8 @@
13 */ 13 */
14 14
15#include <linux/linkage.h> 15#include <linux/linkage.h>
16#include <linux/clk/at91_pmc.h>
16#include <mach/hardware.h> 17#include <mach/hardware.h>
17#include <mach/at91_pmc.h>
18#include <mach/at91_ramc.h> 18#include <mach/at91_ramc.h>
19 19
20 20
diff --git a/arch/arm/mach-at91/sama5d3.c b/arch/arm/mach-at91/sama5d3.c
index 3ea86428ee09..3d775d08de08 100644
--- a/arch/arm/mach-at91/sama5d3.c
+++ b/arch/arm/mach-at91/sama5d3.c
@@ -9,360 +9,19 @@
9 9
10#include <linux/module.h> 10#include <linux/module.h>
11#include <linux/dma-mapping.h> 11#include <linux/dma-mapping.h>
12#include <linux/clk/at91_pmc.h>
12 13
13#include <asm/irq.h> 14#include <asm/irq.h>
14#include <asm/mach/arch.h> 15#include <asm/mach/arch.h>
15#include <asm/mach/map.h> 16#include <asm/mach/map.h>
16#include <mach/sama5d3.h> 17#include <mach/sama5d3.h>
17#include <mach/at91_pmc.h>
18#include <mach/cpu.h> 18#include <mach/cpu.h>
19 19
20#include "soc.h" 20#include "soc.h"
21#include "generic.h" 21#include "generic.h"
22#include "clock.h"
23#include "sam9_smc.h" 22#include "sam9_smc.h"
24 23
25/* -------------------------------------------------------------------- 24/* --------------------------------------------------------------------
26 * Clocks
27 * -------------------------------------------------------------------- */
28
29/*
30 * The peripheral clocks.
31 */
32
33static struct clk pioA_clk = {
34 .name = "pioA_clk",
35 .pid = SAMA5D3_ID_PIOA,
36 .type = CLK_TYPE_PERIPHERAL,
37};
38static struct clk pioB_clk = {
39 .name = "pioB_clk",
40 .pid = SAMA5D3_ID_PIOB,
41 .type = CLK_TYPE_PERIPHERAL,
42};
43static struct clk pioC_clk = {
44 .name = "pioC_clk",
45 .pid = SAMA5D3_ID_PIOC,
46 .type = CLK_TYPE_PERIPHERAL,
47};
48static struct clk pioD_clk = {
49 .name = "pioD_clk",
50 .pid = SAMA5D3_ID_PIOD,
51 .type = CLK_TYPE_PERIPHERAL,
52};
53static struct clk pioE_clk = {
54 .name = "pioE_clk",
55 .pid = SAMA5D3_ID_PIOE,
56 .type = CLK_TYPE_PERIPHERAL,
57};
58static struct clk usart0_clk = {
59 .name = "usart0_clk",
60 .pid = SAMA5D3_ID_USART0,
61 .type = CLK_TYPE_PERIPHERAL,
62 .div = AT91_PMC_PCR_DIV2,
63};
64static struct clk usart1_clk = {
65 .name = "usart1_clk",
66 .pid = SAMA5D3_ID_USART1,
67 .type = CLK_TYPE_PERIPHERAL,
68 .div = AT91_PMC_PCR_DIV2,
69};
70static struct clk usart2_clk = {
71 .name = "usart2_clk",
72 .pid = SAMA5D3_ID_USART2,
73 .type = CLK_TYPE_PERIPHERAL,
74 .div = AT91_PMC_PCR_DIV2,
75};
76static struct clk usart3_clk = {
77 .name = "usart3_clk",
78 .pid = SAMA5D3_ID_USART3,
79 .type = CLK_TYPE_PERIPHERAL,
80 .div = AT91_PMC_PCR_DIV2,
81};
82static struct clk uart0_clk = {
83 .name = "uart0_clk",
84 .pid = SAMA5D3_ID_UART0,
85 .type = CLK_TYPE_PERIPHERAL,
86 .div = AT91_PMC_PCR_DIV2,
87};
88static struct clk uart1_clk = {
89 .name = "uart1_clk",
90 .pid = SAMA5D3_ID_UART1,
91 .type = CLK_TYPE_PERIPHERAL,
92 .div = AT91_PMC_PCR_DIV2,
93};
94static struct clk twi0_clk = {
95 .name = "twi0_clk",
96 .pid = SAMA5D3_ID_TWI0,
97 .type = CLK_TYPE_PERIPHERAL,
98 .div = AT91_PMC_PCR_DIV2,
99};
100static struct clk twi1_clk = {
101 .name = "twi1_clk",
102 .pid = SAMA5D3_ID_TWI1,
103 .type = CLK_TYPE_PERIPHERAL,
104 .div = AT91_PMC_PCR_DIV2,
105};
106static struct clk twi2_clk = {
107 .name = "twi2_clk",
108 .pid = SAMA5D3_ID_TWI2,
109 .type = CLK_TYPE_PERIPHERAL,
110 .div = AT91_PMC_PCR_DIV2,
111};
112static struct clk mmc0_clk = {
113 .name = "mci0_clk",
114 .pid = SAMA5D3_ID_HSMCI0,
115 .type = CLK_TYPE_PERIPHERAL,
116};
117static struct clk mmc1_clk = {
118 .name = "mci1_clk",
119 .pid = SAMA5D3_ID_HSMCI1,
120 .type = CLK_TYPE_PERIPHERAL,
121};
122static struct clk mmc2_clk = {
123 .name = "mci2_clk",
124 .pid = SAMA5D3_ID_HSMCI2,
125 .type = CLK_TYPE_PERIPHERAL,
126};
127static struct clk spi0_clk = {
128 .name = "spi0_clk",
129 .pid = SAMA5D3_ID_SPI0,
130 .type = CLK_TYPE_PERIPHERAL,
131};
132static struct clk spi1_clk = {
133 .name = "spi1_clk",
134 .pid = SAMA5D3_ID_SPI1,
135 .type = CLK_TYPE_PERIPHERAL,
136};
137static struct clk tcb0_clk = {
138 .name = "tcb0_clk",
139 .pid = SAMA5D3_ID_TC0,
140 .type = CLK_TYPE_PERIPHERAL,
141 .div = AT91_PMC_PCR_DIV2,
142};
143static struct clk tcb1_clk = {
144 .name = "tcb1_clk",
145 .pid = SAMA5D3_ID_TC1,
146 .type = CLK_TYPE_PERIPHERAL,
147 .div = AT91_PMC_PCR_DIV2,
148};
149static struct clk adc_clk = {
150 .name = "adc_clk",
151 .pid = SAMA5D3_ID_ADC,
152 .type = CLK_TYPE_PERIPHERAL,
153 .div = AT91_PMC_PCR_DIV2,
154};
155static struct clk adc_op_clk = {
156 .name = "adc_op_clk",
157 .type = CLK_TYPE_PERIPHERAL,
158 .rate_hz = 5000000,
159};
160static struct clk dma0_clk = {
161 .name = "dma0_clk",
162 .pid = SAMA5D3_ID_DMA0,
163 .type = CLK_TYPE_PERIPHERAL,
164};
165static struct clk dma1_clk = {
166 .name = "dma1_clk",
167 .pid = SAMA5D3_ID_DMA1,
168 .type = CLK_TYPE_PERIPHERAL,
169};
170static struct clk uhphs_clk = {
171 .name = "uhphs",
172 .pid = SAMA5D3_ID_UHPHS,
173 .type = CLK_TYPE_PERIPHERAL,
174};
175static struct clk udphs_clk = {
176 .name = "udphs_clk",
177 .pid = SAMA5D3_ID_UDPHS,
178 .type = CLK_TYPE_PERIPHERAL,
179};
180/* gmac only for sama5d33, sama5d34, sama5d35 */
181static struct clk macb0_clk = {
182 .name = "macb0_clk",
183 .pid = SAMA5D3_ID_GMAC,
184 .type = CLK_TYPE_PERIPHERAL,
185};
186/* emac only for sama5d31, sama5d35 */
187static struct clk macb1_clk = {
188 .name = "macb1_clk",
189 .pid = SAMA5D3_ID_EMAC,
190 .type = CLK_TYPE_PERIPHERAL,
191};
192/* lcd only for sama5d31, sama5d33, sama5d34 */
193static struct clk lcdc_clk = {
194 .name = "lcdc_clk",
195 .pid = SAMA5D3_ID_LCDC,
196 .type = CLK_TYPE_PERIPHERAL,
197};
198/* isi only for sama5d33, sama5d35 */
199static struct clk isi_clk = {
200 .name = "isi_clk",
201 .pid = SAMA5D3_ID_ISI,
202 .type = CLK_TYPE_PERIPHERAL,
203};
204static struct clk can0_clk = {
205 .name = "can0_clk",
206 .pid = SAMA5D3_ID_CAN0,
207 .type = CLK_TYPE_PERIPHERAL,
208 .div = AT91_PMC_PCR_DIV2,
209};
210static struct clk can1_clk = {
211 .name = "can1_clk",
212 .pid = SAMA5D3_ID_CAN1,
213 .type = CLK_TYPE_PERIPHERAL,
214 .div = AT91_PMC_PCR_DIV2,
215};
216static struct clk ssc0_clk = {
217 .name = "ssc0_clk",
218 .pid = SAMA5D3_ID_SSC0,
219 .type = CLK_TYPE_PERIPHERAL,
220 .div = AT91_PMC_PCR_DIV2,
221};
222static struct clk ssc1_clk = {
223 .name = "ssc1_clk",
224 .pid = SAMA5D3_ID_SSC1,
225 .type = CLK_TYPE_PERIPHERAL,
226 .div = AT91_PMC_PCR_DIV2,
227};
228static struct clk sha_clk = {
229 .name = "sha_clk",
230 .pid = SAMA5D3_ID_SHA,
231 .type = CLK_TYPE_PERIPHERAL,
232 .div = AT91_PMC_PCR_DIV8,
233};
234static struct clk aes_clk = {
235 .name = "aes_clk",
236 .pid = SAMA5D3_ID_AES,
237 .type = CLK_TYPE_PERIPHERAL,
238};
239static struct clk tdes_clk = {
240 .name = "tdes_clk",
241 .pid = SAMA5D3_ID_TDES,
242 .type = CLK_TYPE_PERIPHERAL,
243};
244
245static struct clk *periph_clocks[] __initdata = {
246 &pioA_clk,
247 &pioB_clk,
248 &pioC_clk,
249 &pioD_clk,
250 &pioE_clk,
251 &usart0_clk,
252 &usart1_clk,
253 &usart2_clk,
254 &usart3_clk,
255 &uart0_clk,
256 &uart1_clk,
257 &twi0_clk,
258 &twi1_clk,
259 &twi2_clk,
260 &mmc0_clk,
261 &mmc1_clk,
262 &mmc2_clk,
263 &spi0_clk,
264 &spi1_clk,
265 &tcb0_clk,
266 &tcb1_clk,
267 &adc_clk,
268 &adc_op_clk,
269 &dma0_clk,
270 &dma1_clk,
271 &uhphs_clk,
272 &udphs_clk,
273 &macb0_clk,
274 &macb1_clk,
275 &lcdc_clk,
276 &isi_clk,
277 &can0_clk,
278 &can1_clk,
279 &ssc0_clk,
280 &ssc1_clk,
281 &sha_clk,
282 &aes_clk,
283 &tdes_clk,
284};
285
286static struct clk pck0 = {
287 .name = "pck0",
288 .pmc_mask = AT91_PMC_PCK0,
289 .type = CLK_TYPE_PROGRAMMABLE,
290 .id = 0,
291};
292
293static struct clk pck1 = {
294 .name = "pck1",
295 .pmc_mask = AT91_PMC_PCK1,
296 .type = CLK_TYPE_PROGRAMMABLE,
297 .id = 1,
298};
299
300static struct clk pck2 = {
301 .name = "pck2",
302 .pmc_mask = AT91_PMC_PCK2,
303 .type = CLK_TYPE_PROGRAMMABLE,
304 .id = 2,
305};
306
307static struct clk_lookup periph_clocks_lookups[] = {
308 /* lookup table for DT entries */
309 CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
310 CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
311 CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk),
312 CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioC_clk),
313 CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioD_clk),
314 CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioE_clk),
315 CLKDEV_CON_DEV_ID("usart", "f001c000.serial", &usart0_clk),
316 CLKDEV_CON_DEV_ID("usart", "f0020000.serial", &usart1_clk),
317 CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart2_clk),
318 CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart3_clk),
319 CLKDEV_CON_DEV_ID(NULL, "f0014000.i2c", &twi0_clk),
320 CLKDEV_CON_DEV_ID(NULL, "f0018000.i2c", &twi1_clk),
321 CLKDEV_CON_DEV_ID(NULL, "f801c000.i2c", &twi2_clk),
322 CLKDEV_CON_DEV_ID("mci_clk", "f0000000.mmc", &mmc0_clk),
323 CLKDEV_CON_DEV_ID("mci_clk", "f8000000.mmc", &mmc1_clk),
324 CLKDEV_CON_DEV_ID("mci_clk", "f8004000.mmc", &mmc2_clk),
325 CLKDEV_CON_DEV_ID("spi_clk", "f0004000.spi", &spi0_clk),
326 CLKDEV_CON_DEV_ID("spi_clk", "f8008000.spi", &spi1_clk),
327 CLKDEV_CON_DEV_ID("t0_clk", "f0010000.timer", &tcb0_clk),
328 CLKDEV_CON_DEV_ID("t0_clk", "f8014000.timer", &tcb1_clk),
329 CLKDEV_CON_DEV_ID("tsc_clk", "f8018000.tsadcc", &adc_clk),
330 CLKDEV_CON_DEV_ID("dma_clk", "ffffe600.dma-controller", &dma0_clk),
331 CLKDEV_CON_DEV_ID("dma_clk", "ffffe800.dma-controller", &dma1_clk),
332 CLKDEV_CON_DEV_ID("hclk", "600000.ohci", &uhphs_clk),
333 CLKDEV_CON_DEV_ID("ohci_clk", "600000.ohci", &uhphs_clk),
334 CLKDEV_CON_DEV_ID("ehci_clk", "700000.ehci", &uhphs_clk),
335 CLKDEV_CON_DEV_ID("pclk", "500000.gadget", &udphs_clk),
336 CLKDEV_CON_DEV_ID("hclk", "500000.gadget", &utmi_clk),
337 CLKDEV_CON_DEV_ID("hclk", "f0028000.ethernet", &macb0_clk),
338 CLKDEV_CON_DEV_ID("pclk", "f0028000.ethernet", &macb0_clk),
339 CLKDEV_CON_DEV_ID("hclk", "f802c000.ethernet", &macb1_clk),
340 CLKDEV_CON_DEV_ID("pclk", "f802c000.ethernet", &macb1_clk),
341 CLKDEV_CON_DEV_ID("pclk", "f0008000.ssc", &ssc0_clk),
342 CLKDEV_CON_DEV_ID("pclk", "f000c000.ssc", &ssc1_clk),
343 CLKDEV_CON_DEV_ID("can_clk", "f000c000.can", &can0_clk),
344 CLKDEV_CON_DEV_ID("can_clk", "f8010000.can", &can1_clk),
345 CLKDEV_CON_DEV_ID("sha_clk", "f8034000.sha", &sha_clk),
346 CLKDEV_CON_DEV_ID("aes_clk", "f8038000.aes", &aes_clk),
347 CLKDEV_CON_DEV_ID("tdes_clk", "f803c000.tdes", &tdes_clk),
348};
349
350static void __init sama5d3_register_clocks(void)
351{
352 int i;
353
354 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
355 clk_register(periph_clocks[i]);
356
357 clkdev_add_table(periph_clocks_lookups,
358 ARRAY_SIZE(periph_clocks_lookups));
359
360 clk_register(&pck0);
361 clk_register(&pck1);
362 clk_register(&pck2);
363}
364
365/* --------------------------------------------------------------------
366 * AT91SAM9x5 processor initialization 25 * AT91SAM9x5 processor initialization
367 * -------------------------------------------------------------------- */ 26 * -------------------------------------------------------------------- */
368 27
@@ -378,6 +37,5 @@ static void __init sama5d3_initialize(void)
378 37
379AT91_SOC_START(sama5d3) 38AT91_SOC_START(sama5d3)
380 .map_io = sama5d3_map_io, 39 .map_io = sama5d3_map_io,
381 .register_clocks = sama5d3_register_clocks,
382 .init = sama5d3_initialize, 40 .init = sama5d3_initialize,
383AT91_SOC_END 41AT91_SOC_END
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index 094b3459c288..7d3f7cc61081 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -11,6 +11,7 @@
11#include <linux/pm.h> 11#include <linux/pm.h>
12#include <linux/of_address.h> 12#include <linux/of_address.h>
13#include <linux/pinctrl/machine.h> 13#include <linux/pinctrl/machine.h>
14#include <linux/clk/at91_pmc.h>
14 15
15#include <asm/system_misc.h> 16#include <asm/system_misc.h>
16#include <asm/mach/map.h> 17#include <asm/mach/map.h>
@@ -18,7 +19,6 @@
18#include <mach/hardware.h> 19#include <mach/hardware.h>
19#include <mach/cpu.h> 20#include <mach/cpu.h>
20#include <mach/at91_dbgu.h> 21#include <mach/at91_dbgu.h>
21#include <mach/at91_pmc.h>
22 22
23#include "at91_shdwc.h" 23#include "at91_shdwc.h"
24#include "soc.h" 24#include "soc.h"
@@ -491,7 +491,8 @@ void __init at91rm9200_dt_initialize(void)
491 at91_dt_clock_init(); 491 at91_dt_clock_init();
492 492
493 /* Register the processor-specific clocks */ 493 /* Register the processor-specific clocks */
494 at91_boot_soc.register_clocks(); 494 if (at91_boot_soc.register_clocks)
495 at91_boot_soc.register_clocks();
495 496
496 at91_boot_soc.init(); 497 at91_boot_soc.init();
497} 498}
@@ -506,7 +507,8 @@ void __init at91_dt_initialize(void)
506 at91_dt_clock_init(); 507 at91_dt_clock_init();
507 508
508 /* Register the processor-specific clocks */ 509 /* Register the processor-specific clocks */
509 at91_boot_soc.register_clocks(); 510 if (at91_boot_soc.register_clocks)
511 at91_boot_soc.register_clocks();
510 512
511 if (at91_boot_soc.init) 513 if (at91_boot_soc.init)
512 at91_boot_soc.init(); 514 at91_boot_soc.init();
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index c122bcff9f7c..0d1a89298ece 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -162,7 +162,7 @@ void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data)
162/***************************************************************************** 162/*****************************************************************************
163 * SoC RTC 163 * SoC RTC
164 ****************************************************************************/ 164 ****************************************************************************/
165void __init dove_rtc_init(void) 165static void __init dove_rtc_init(void)
166{ 166{
167 orion_rtc_init(DOVE_RTC_PHYS_BASE, IRQ_DOVE_RTC); 167 orion_rtc_init(DOVE_RTC_PHYS_BASE, IRQ_DOVE_RTC);
168} 168}
@@ -257,18 +257,9 @@ void __init dove_timer_init(void)
257} 257}
258 258
259/***************************************************************************** 259/*****************************************************************************
260 * Cryptographic Engines and Security Accelerator (CESA)
261 ****************************************************************************/
262void __init dove_crypto_init(void)
263{
264 orion_crypto_init(DOVE_CRYPT_PHYS_BASE, DOVE_CESA_PHYS_BASE,
265 DOVE_CESA_SIZE, IRQ_DOVE_CRYPTO);
266}
267
268/*****************************************************************************
269 * XOR 0 260 * XOR 0
270 ****************************************************************************/ 261 ****************************************************************************/
271void __init dove_xor0_init(void) 262static void __init dove_xor0_init(void)
272{ 263{
273 orion_xor0_init(DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE, 264 orion_xor0_init(DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE,
274 IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01); 265 IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01);
@@ -277,7 +268,7 @@ void __init dove_xor0_init(void)
277/***************************************************************************** 268/*****************************************************************************
278 * XOR 1 269 * XOR 1
279 ****************************************************************************/ 270 ****************************************************************************/
280void __init dove_xor1_init(void) 271static void __init dove_xor1_init(void)
281{ 272{
282 orion_xor1_init(DOVE_XOR1_PHYS_BASE, DOVE_XOR1_HIGH_PHYS_BASE, 273 orion_xor1_init(DOVE_XOR1_PHYS_BASE, DOVE_XOR1_HIGH_PHYS_BASE,
283 IRQ_DOVE_XOR_10, IRQ_DOVE_XOR_11); 274 IRQ_DOVE_XOR_10, IRQ_DOVE_XOR_11);
diff --git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c
index 2739ca2c1334..e0091685fd48 100644
--- a/arch/arm/mach-footbridge/common.c
+++ b/arch/arm/mach-footbridge/common.c
@@ -15,6 +15,7 @@
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/io.h> 16#include <linux/io.h>
17#include <linux/spinlock.h> 17#include <linux/spinlock.h>
18#include <video/vga.h>
18 19
19#include <asm/pgtable.h> 20#include <asm/pgtable.h>
20#include <asm/page.h> 21#include <asm/page.h>
@@ -196,6 +197,8 @@ void __init footbridge_map_io(void)
196 iotable_init(ebsa285_host_io_desc, ARRAY_SIZE(ebsa285_host_io_desc)); 197 iotable_init(ebsa285_host_io_desc, ARRAY_SIZE(ebsa285_host_io_desc));
197 pci_map_io_early(__phys_to_pfn(DC21285_PCI_IO)); 198 pci_map_io_early(__phys_to_pfn(DC21285_PCI_IO));
198 } 199 }
200
201 vga_base = PCIMEM_BASE;
199} 202}
200 203
201void footbridge_restart(enum reboot_mode mode, const char *cmd) 204void footbridge_restart(enum reboot_mode mode, const char *cmd)
diff --git a/arch/arm/mach-footbridge/dc21285.c b/arch/arm/mach-footbridge/dc21285.c
index 3490a24f969e..7c2fdae9a38b 100644
--- a/arch/arm/mach-footbridge/dc21285.c
+++ b/arch/arm/mach-footbridge/dc21285.c
@@ -18,7 +18,6 @@
18#include <linux/irq.h> 18#include <linux/irq.h>
19#include <linux/io.h> 19#include <linux/io.h>
20#include <linux/spinlock.h> 20#include <linux/spinlock.h>
21#include <video/vga.h>
22 21
23#include <asm/irq.h> 22#include <asm/irq.h>
24#include <asm/mach/pci.h> 23#include <asm/mach/pci.h>
@@ -291,7 +290,6 @@ void __init dc21285_preinit(void)
291 int cfn_mode; 290 int cfn_mode;
292 291
293 pcibios_min_mem = 0x81000000; 292 pcibios_min_mem = 0x81000000;
294 vga_base = PCIMEM_BASE;
295 293
296 mem_size = (unsigned int)high_memory - PAGE_OFFSET; 294 mem_size = (unsigned int)high_memory - PAGE_OFFSET;
297 for (mem_mask = 0x00100000; mem_mask < 0x10000000; mem_mask <<= 1) 295 for (mem_mask = 0x00100000; mem_mask < 0x10000000; mem_mask <<= 1)
diff --git a/arch/arm/mach-footbridge/ebsa285.c b/arch/arm/mach-footbridge/ebsa285.c
index b08243500e2e..1a7235fb52ac 100644
--- a/arch/arm/mach-footbridge/ebsa285.c
+++ b/arch/arm/mach-footbridge/ebsa285.c
@@ -30,21 +30,24 @@ static const struct {
30 const char *name; 30 const char *name;
31 const char *trigger; 31 const char *trigger;
32} ebsa285_leds[] = { 32} ebsa285_leds[] = {
33 { "ebsa285:amber", "heartbeat", }, 33 { "ebsa285:amber", "cpu0", },
34 { "ebsa285:green", "cpu0", }, 34 { "ebsa285:green", "heartbeat", },
35 { "ebsa285:red",}, 35 { "ebsa285:red",},
36}; 36};
37 37
38static unsigned char hw_led_state;
39
38static void ebsa285_led_set(struct led_classdev *cdev, 40static void ebsa285_led_set(struct led_classdev *cdev,
39 enum led_brightness b) 41 enum led_brightness b)
40{ 42{
41 struct ebsa285_led *led = container_of(cdev, 43 struct ebsa285_led *led = container_of(cdev,
42 struct ebsa285_led, cdev); 44 struct ebsa285_led, cdev);
43 45
44 if (b != LED_OFF) 46 if (b == LED_OFF)
45 *XBUS_LEDS |= led->mask; 47 hw_led_state |= led->mask;
46 else 48 else
47 *XBUS_LEDS &= ~led->mask; 49 hw_led_state &= ~led->mask;
50 *XBUS_LEDS = hw_led_state;
48} 51}
49 52
50static enum led_brightness ebsa285_led_get(struct led_classdev *cdev) 53static enum led_brightness ebsa285_led_get(struct led_classdev *cdev)
@@ -52,18 +55,19 @@ static enum led_brightness ebsa285_led_get(struct led_classdev *cdev)
52 struct ebsa285_led *led = container_of(cdev, 55 struct ebsa285_led *led = container_of(cdev,
53 struct ebsa285_led, cdev); 56 struct ebsa285_led, cdev);
54 57
55 return (*XBUS_LEDS & led->mask) ? LED_FULL : LED_OFF; 58 return hw_led_state & led->mask ? LED_OFF : LED_FULL;
56} 59}
57 60
58static int __init ebsa285_leds_init(void) 61static int __init ebsa285_leds_init(void)
59{ 62{
60 int i; 63 int i;
61 64
62 if (machine_is_ebsa285()) 65 if (!machine_is_ebsa285())
63 return -ENODEV; 66 return -ENODEV;
64 67
65 /* 3 LEDS All ON */ 68 /* 3 LEDS all off */
66 *XBUS_LEDS |= XBUS_LED_AMBER | XBUS_LED_GREEN | XBUS_LED_RED; 69 hw_led_state = XBUS_LED_AMBER | XBUS_LED_GREEN | XBUS_LED_RED;
70 *XBUS_LEDS = hw_led_state;
67 71
68 for (i = 0; i < ARRAY_SIZE(ebsa285_leds); i++) { 72 for (i = 0; i < ARRAY_SIZE(ebsa285_leds); i++) {
69 struct ebsa285_led *led; 73 struct ebsa285_led *led;
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index d50dc2dbfd89..cc1d3fe21c4e 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -63,6 +63,9 @@
63 63
64/* Base address to the AP system controller */ 64/* Base address to the AP system controller */
65void __iomem *ap_syscon_base; 65void __iomem *ap_syscon_base;
66/* Base address to the external bus interface */
67static void __iomem *ebi_base;
68
66 69
67/* 70/*
68 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx 71 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
@@ -72,15 +75,11 @@ void __iomem *ap_syscon_base;
72 * just for now). 75 * just for now).
73 */ 76 */
74#define VA_IC_BASE __io_address(INTEGRATOR_IC_BASE) 77#define VA_IC_BASE __io_address(INTEGRATOR_IC_BASE)
75#define VA_EBI_BASE __io_address(INTEGRATOR_EBI_BASE)
76#define VA_CMIC_BASE __io_address(INTEGRATOR_HDR_IC)
77 78
78/* 79/*
79 * Logical Physical 80 * Logical Physical
80 * ef000000 Cache flush 81 * ef000000 Cache flush
81 * f1000000 10000000 Core module registers
82 * f1100000 11000000 System controller registers 82 * f1100000 11000000 System controller registers
83 * f1200000 12000000 EBI registers
84 * f1300000 13000000 Counter/Timer 83 * f1300000 13000000 Counter/Timer
85 * f1400000 14000000 Interrupt controller 84 * f1400000 14000000 Interrupt controller
86 * f1600000 16000000 UART 0 85 * f1600000 16000000 UART 0
@@ -91,16 +90,6 @@ void __iomem *ap_syscon_base;
91 90
92static struct map_desc ap_io_desc[] __initdata __maybe_unused = { 91static struct map_desc ap_io_desc[] __initdata __maybe_unused = {
93 { 92 {
94 .virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE),
95 .pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE),
96 .length = SZ_4K,
97 .type = MT_DEVICE
98 }, {
99 .virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE),
100 .pfn = __phys_to_pfn(INTEGRATOR_EBI_BASE),
101 .length = SZ_4K,
102 .type = MT_DEVICE
103 }, {
104 .virtual = IO_ADDRESS(INTEGRATOR_CT_BASE), 93 .virtual = IO_ADDRESS(INTEGRATOR_CT_BASE),
105 .pfn = __phys_to_pfn(INTEGRATOR_CT_BASE), 94 .pfn = __phys_to_pfn(INTEGRATOR_CT_BASE),
106 .length = SZ_4K, 95 .length = SZ_4K,
@@ -174,9 +163,6 @@ device_initcall(irq_syscore_init);
174/* 163/*
175 * Flash handling. 164 * Flash handling.
176 */ 165 */
177#define EBI_CSR1 (VA_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
178#define EBI_LOCK (VA_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)
179
180static int ap_flash_init(struct platform_device *dev) 166static int ap_flash_init(struct platform_device *dev)
181{ 167{
182 u32 tmp; 168 u32 tmp;
@@ -184,13 +170,15 @@ static int ap_flash_init(struct platform_device *dev)
184 writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, 170 writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP,
185 ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET); 171 ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
186 172
187 tmp = readl(EBI_CSR1) | INTEGRATOR_EBI_WRITE_ENABLE; 173 tmp = readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET) |
188 writel(tmp, EBI_CSR1); 174 INTEGRATOR_EBI_WRITE_ENABLE;
175 writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET);
189 176
190 if (!(readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE)) { 177 if (!(readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET)
191 writel(0xa05f, EBI_LOCK); 178 & INTEGRATOR_EBI_WRITE_ENABLE)) {
192 writel(tmp, EBI_CSR1); 179 writel(0xa05f, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET);
193 writel(0, EBI_LOCK); 180 writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET);
181 writel(0, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET);
194 } 182 }
195 return 0; 183 return 0;
196} 184}
@@ -202,13 +190,15 @@ static void ap_flash_exit(struct platform_device *dev)
202 writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, 190 writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP,
203 ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET); 191 ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
204 192
205 tmp = readl(EBI_CSR1) & ~INTEGRATOR_EBI_WRITE_ENABLE; 193 tmp = readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET) &
206 writel(tmp, EBI_CSR1); 194 ~INTEGRATOR_EBI_WRITE_ENABLE;
195 writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET);
207 196
208 if (readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE) { 197 if (readl(ebi_base + INTEGRATOR_EBI_CSR1_OFFSET) &
209 writel(0xa05f, EBI_LOCK); 198 INTEGRATOR_EBI_WRITE_ENABLE) {
210 writel(tmp, EBI_CSR1); 199 writel(0xa05f, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET);
211 writel(0, EBI_LOCK); 200 writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET);
201 writel(0, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET);
212 } 202 }
213} 203}
214 204
@@ -475,11 +465,17 @@ static const struct of_device_id ap_syscon_match[] = {
475 { }, 465 { },
476}; 466};
477 467
468static const struct of_device_id ebi_match[] = {
469 { .compatible = "arm,external-bus-interface"},
470 { },
471};
472
478static void __init ap_init_of(void) 473static void __init ap_init_of(void)
479{ 474{
480 unsigned long sc_dec; 475 unsigned long sc_dec;
481 struct device_node *root; 476 struct device_node *root;
482 struct device_node *syscon; 477 struct device_node *syscon;
478 struct device_node *ebi;
483 struct device *parent; 479 struct device *parent;
484 struct soc_device *soc_dev; 480 struct soc_device *soc_dev;
485 struct soc_device_attribute *soc_dev_attr; 481 struct soc_device_attribute *soc_dev_attr;
@@ -495,10 +491,16 @@ static void __init ap_init_of(void)
495 syscon = of_find_matching_node(root, ap_syscon_match); 491 syscon = of_find_matching_node(root, ap_syscon_match);
496 if (!syscon) 492 if (!syscon)
497 return; 493 return;
494 ebi = of_find_matching_node(root, ebi_match);
495 if (!ebi)
496 return;
498 497
499 ap_syscon_base = of_iomap(syscon, 0); 498 ap_syscon_base = of_iomap(syscon, 0);
500 if (!ap_syscon_base) 499 if (!ap_syscon_base)
501 return; 500 return;
501 ebi_base = of_iomap(ebi, 0);
502 if (!ebi_base)
503 return;
502 504
503 ap_sc_id = readl(ap_syscon_base); 505 ap_sc_id = readl(ap_syscon_base);
504 506
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index 4fc0a195de01..5e84149d1790 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -64,9 +64,6 @@ static void __iomem *intcp_con_base;
64 64
65/* 65/*
66 * Logical Physical 66 * Logical Physical
67 * f1000000 10000000 Core module registers
68 * f1100000 11000000 System controller registers
69 * f1200000 12000000 EBI registers
70 * f1300000 13000000 Counter/Timer 67 * f1300000 13000000 Counter/Timer
71 * f1400000 14000000 Interrupt controller 68 * f1400000 14000000 Interrupt controller
72 * f1600000 16000000 UART 0 69 * f1600000 16000000 UART 0
@@ -74,21 +71,10 @@ static void __iomem *intcp_con_base;
74 * f1a00000 1a000000 Debug LEDs 71 * f1a00000 1a000000 Debug LEDs
75 * fc900000 c9000000 GPIO 72 * fc900000 c9000000 GPIO
76 * fca00000 ca000000 SIC 73 * fca00000 ca000000 SIC
77 * fcb00000 cb000000 CP system control
78 */ 74 */
79 75
80static struct map_desc intcp_io_desc[] __initdata __maybe_unused = { 76static struct map_desc intcp_io_desc[] __initdata __maybe_unused = {
81 { 77 {
82 .virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE),
83 .pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE),
84 .length = SZ_4K,
85 .type = MT_DEVICE
86 }, {
87 .virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE),
88 .pfn = __phys_to_pfn(INTEGRATOR_EBI_BASE),
89 .length = SZ_4K,
90 .type = MT_DEVICE
91 }, {
92 .virtual = IO_ADDRESS(INTEGRATOR_CT_BASE), 78 .virtual = IO_ADDRESS(INTEGRATOR_CT_BASE),
93 .pfn = __phys_to_pfn(INTEGRATOR_CT_BASE), 79 .pfn = __phys_to_pfn(INTEGRATOR_CT_BASE),
94 .length = SZ_4K, 80 .length = SZ_4K,
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index 9caa4fe95913..78188159484d 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -10,55 +10,21 @@
10 * warranty of any kind, whether express or implied. 10 * warranty of any kind, whether express or implied.
11 */ 11 */
12 12
13#include <linux/clk.h>
13#include <linux/kernel.h> 14#include <linux/kernel.h>
14#include <linux/init.h> 15#include <linux/init.h>
15#include <linux/of.h> 16#include <linux/of.h>
16#include <linux/of_address.h> 17#include <linux/of_address.h>
17#include <linux/of_net.h> 18#include <linux/of_net.h>
18#include <linux/of_platform.h> 19#include <linux/of_platform.h>
19#include <linux/clk-provider.h>
20#include <linux/dma-mapping.h> 20#include <linux/dma-mapping.h>
21#include <linux/irqchip.h> 21#include <linux/irqchip.h>
22#include <linux/kexec.h> 22#include <linux/kexec.h>
23#include <asm/mach/arch.h> 23#include <asm/mach/arch.h>
24#include <asm/mach/map.h>
25#include <mach/bridge-regs.h> 24#include <mach/bridge-regs.h>
26#include <linux/platform_data/usb-ehci-orion.h>
27#include <plat/irq.h>
28#include <plat/common.h> 25#include <plat/common.h>
29#include "common.h" 26#include "common.h"
30 27
31/*
32 * There are still devices that doesn't know about DT yet. Get clock
33 * gates here and add a clock lookup alias, so that old platform
34 * devices still work.
35*/
36
37static void __init kirkwood_legacy_clk_init(void)
38{
39
40 struct device_node *np = of_find_compatible_node(
41 NULL, NULL, "marvell,kirkwood-gating-clock");
42 struct of_phandle_args clkspec;
43 struct clk *clk;
44
45 clkspec.np = np;
46 clkspec.args_count = 1;
47
48 /*
49 * The ethernet interfaces forget the MAC address assigned by
50 * u-boot if the clocks are turned off. Until proper DT support
51 * is available we always enable them for now.
52 */
53 clkspec.args[0] = CGC_BIT_GE0;
54 clk = of_clk_get_from_provider(&clkspec);
55 clk_prepare_enable(clk);
56
57 clkspec.args[0] = CGC_BIT_GE1;
58 clk = of_clk_get_from_provider(&clkspec);
59 clk_prepare_enable(clk);
60}
61
62#define MV643XX_ETH_MAC_ADDR_LOW 0x0414 28#define MV643XX_ETH_MAC_ADDR_LOW 0x0414
63#define MV643XX_ETH_MAC_ADDR_HIGH 0x0418 29#define MV643XX_ETH_MAC_ADDR_HIGH 0x0418
64 30
@@ -140,7 +106,7 @@ eth_fixup_skip:
140 106
141static void __init kirkwood_dt_init(void) 107static void __init kirkwood_dt_init(void)
142{ 108{
143 pr_info("Kirkwood: %s, TCLK=%d.\n", kirkwood_id(), kirkwood_tclk); 109 pr_info("Kirkwood: %s.\n", kirkwood_id());
144 110
145 /* 111 /*
146 * Disable propagation of mbus errors to the CPU local bus, 112 * Disable propagation of mbus errors to the CPU local bus,
@@ -156,8 +122,6 @@ static void __init kirkwood_dt_init(void)
156 122
157 kirkwood_cpufreq_init(); 123 kirkwood_cpufreq_init();
158 kirkwood_cpuidle_init(); 124 kirkwood_cpuidle_init();
159 /* Setup clocks for legacy devices */
160 kirkwood_legacy_clk_init();
161 125
162 kirkwood_pm_init(); 126 kirkwood_pm_init();
163 kirkwood_dt_eth_fixup(); 127 kirkwood_dt_eth_fixup();
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index 2586c2865874..702553b96137 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -44,6 +44,7 @@ endchoice
44 44
45config ARCH_MSM8X60 45config ARCH_MSM8X60
46 bool "MSM8X60" 46 bool "MSM8X60"
47 select ARCH_MSM_DT
47 select ARM_GIC 48 select ARM_GIC
48 select CPU_V7 49 select CPU_V7
49 select GPIO_MSM_V2 50 select GPIO_MSM_V2
@@ -52,15 +53,25 @@ config ARCH_MSM8X60
52 53
53config ARCH_MSM8960 54config ARCH_MSM8960
54 bool "MSM8960" 55 bool "MSM8960"
56 select ARCH_MSM_DT
55 select ARM_GIC 57 select ARM_GIC
56 select CPU_V7 58 select CPU_V7
57 select HAVE_SMP 59 select HAVE_SMP
58 select GPIO_MSM_V2 60 select GPIO_MSM_V2
59 select MSM_SCM if SMP 61 select MSM_SCM if SMP
60 62
63config ARCH_MSM8974
64 bool "MSM8974"
65 select ARCH_MSM_DT
66 select ARM_GIC
67 select CPU_V7
68 select HAVE_ARM_ARCH_TIMER
69 select HAVE_SMP
70 select MSM_SCM if SMP
71 select USE_OF
72
61config ARCH_MSM_DT 73config ARCH_MSM_DT
62 def_bool y 74 bool
63 depends on (ARCH_MSM8X60 || ARCH_MSM8960)
64 select SPARSE_IRQ 75 select SPARSE_IRQ
65 select USE_OF 76 select USE_OF
66 77
diff --git a/arch/arm/mach-msm/board-trout.c b/arch/arm/mach-msm/board-trout.c
index ccf6621bc664..015d544aa017 100644
--- a/arch/arm/mach-msm/board-trout.c
+++ b/arch/arm/mach-msm/board-trout.c
@@ -13,6 +13,7 @@
13 * GNU General Public License for more details. 13 * GNU General Public License for more details.
14 * 14 *
15 */ 15 */
16#define pr_fmt(fmt) "%s: " fmt, __func__
16 17
17#include <linux/kernel.h> 18#include <linux/kernel.h>
18#include <linux/init.h> 19#include <linux/init.h>
@@ -68,12 +69,11 @@ static void __init trout_init(void)
68 69
69 platform_add_devices(devices, ARRAY_SIZE(devices)); 70 platform_add_devices(devices, ARRAY_SIZE(devices));
70 71
71#ifdef CONFIG_MMC 72 if (IS_ENABLED(CONFIG_MMC)) {
72 rc = trout_init_mmc(system_rev); 73 rc = trout_init_mmc(system_rev);
73 if (rc) 74 if (rc)
74 printk(KERN_CRIT "%s: MMC init failure (%d)\n", __func__, rc); 75 pr_crit("MMC init failure (%d)\n", rc);
75#endif 76 }
76
77} 77}
78 78
79static struct map_desc trout_io_desc[] __initdata = { 79static struct map_desc trout_io_desc[] __initdata = {
diff --git a/arch/arm/mach-mvebu/coherency.c b/arch/arm/mach-mvebu/coherency.c
index 58adf2fd9cfc..4e9d58148ca7 100644
--- a/arch/arm/mach-mvebu/coherency.c
+++ b/arch/arm/mach-mvebu/coherency.c
@@ -27,6 +27,7 @@
27#include <asm/smp_plat.h> 27#include <asm/smp_plat.h>
28#include <asm/cacheflush.h> 28#include <asm/cacheflush.h>
29#include "armada-370-xp.h" 29#include "armada-370-xp.h"
30#include "coherency.h"
30 31
31unsigned long coherency_phys_base; 32unsigned long coherency_phys_base;
32static void __iomem *coherency_base; 33static void __iomem *coherency_base;
diff --git a/arch/arm/mach-mvebu/coherency.h b/arch/arm/mach-mvebu/coherency.h
index df33ad8a6c08..760226c41353 100644
--- a/arch/arm/mach-mvebu/coherency.h
+++ b/arch/arm/mach-mvebu/coherency.h
@@ -14,7 +14,9 @@
14#ifndef __MACH_370_XP_COHERENCY_H 14#ifndef __MACH_370_XP_COHERENCY_H
15#define __MACH_370_XP_COHERENCY_H 15#define __MACH_370_XP_COHERENCY_H
16 16
17int set_cpu_coherent(int cpu_id, int smp_group_id); 17extern unsigned long coherency_phys_base;
18
19int set_cpu_coherent(unsigned int cpu_id, int smp_group_id);
18int coherency_init(void); 20int coherency_init(void);
19 21
20#endif /* __MACH_370_XP_COHERENCY_H */ 22#endif /* __MACH_370_XP_COHERENCY_H */
diff --git a/arch/arm/mach-mvebu/common.h b/arch/arm/mach-mvebu/common.h
index e366010e1d91..0e6016fadcc5 100644
--- a/arch/arm/mach-mvebu/common.h
+++ b/arch/arm/mach-mvebu/common.h
@@ -26,7 +26,6 @@ void armada_370_xp_handle_irq(struct pt_regs *regs);
26 26
27void armada_xp_cpu_die(unsigned int cpu); 27void armada_xp_cpu_die(unsigned int cpu);
28int armada_370_xp_coherency_init(void); 28int armada_370_xp_coherency_init(void);
29int armada_370_xp_pmsu_init(void);
30void armada_xp_secondary_startup(void); 29void armada_xp_secondary_startup(void);
31extern struct smp_operations armada_xp_smp_ops; 30extern struct smp_operations armada_xp_smp_ops;
32#endif 31#endif
diff --git a/arch/arm/mach-mvebu/hotplug.c b/arch/arm/mach-mvebu/hotplug.c
index b228b6a80c85..d95e91047168 100644
--- a/arch/arm/mach-mvebu/hotplug.c
+++ b/arch/arm/mach-mvebu/hotplug.c
@@ -15,6 +15,7 @@
15#include <linux/errno.h> 15#include <linux/errno.h>
16#include <linux/smp.h> 16#include <linux/smp.h>
17#include <asm/proc-fns.h> 17#include <asm/proc-fns.h>
18#include "common.h"
18 19
19/* 20/*
20 * platform-specific code to shutdown a CPU 21 * platform-specific code to shutdown a CPU
diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c
index ff69c2df298b..a6da03f5b24e 100644
--- a/arch/arm/mach-mvebu/platsmp.c
+++ b/arch/arm/mach-mvebu/platsmp.c
@@ -46,7 +46,7 @@ static struct clk *__init get_cpu_clk(int cpu)
46 return cpu_clk; 46 return cpu_clk;
47} 47}
48 48
49void __init set_secondary_cpus_clock(void) 49static void __init set_secondary_cpus_clock(void)
50{ 50{
51 int thiscpu, cpu; 51 int thiscpu, cpu;
52 unsigned long rate; 52 unsigned long rate;
@@ -94,7 +94,7 @@ static void __init armada_xp_smp_init_cpus(void)
94 set_smp_cross_call(armada_mpic_send_doorbell); 94 set_smp_cross_call(armada_mpic_send_doorbell);
95} 95}
96 96
97void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus) 97static void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus)
98{ 98{
99 struct device_node *node; 99 struct device_node *node;
100 struct resource res; 100 struct resource res;
diff --git a/arch/arm/mach-mvebu/pmsu.c b/arch/arm/mach-mvebu/pmsu.c
index 27fc4f049474..d71ef53107c4 100644
--- a/arch/arm/mach-mvebu/pmsu.c
+++ b/arch/arm/mach-mvebu/pmsu.c
@@ -22,6 +22,7 @@
22#include <linux/io.h> 22#include <linux/io.h>
23#include <linux/smp.h> 23#include <linux/smp.h>
24#include <asm/smp_plat.h> 24#include <asm/smp_plat.h>
25#include "pmsu.h"
25 26
26static void __iomem *pmsu_mp_base; 27static void __iomem *pmsu_mp_base;
27static void __iomem *pmsu_reset_base; 28static void __iomem *pmsu_reset_base;
@@ -58,7 +59,7 @@ int armada_xp_boot_cpu(unsigned int cpu_id, void *boot_addr)
58} 59}
59#endif 60#endif
60 61
61int __init armada_370_xp_pmsu_init(void) 62static int __init armada_370_xp_pmsu_init(void)
62{ 63{
63 struct device_node *np; 64 struct device_node *np;
64 65
diff --git a/arch/arm/mach-mvebu/system-controller.c b/arch/arm/mach-mvebu/system-controller.c
index 5175083cdb34..a7fb89a5b5d9 100644
--- a/arch/arm/mach-mvebu/system-controller.c
+++ b/arch/arm/mach-mvebu/system-controller.c
@@ -27,6 +27,7 @@
27#include <linux/of_address.h> 27#include <linux/of_address.h>
28#include <linux/io.h> 28#include <linux/io.h>
29#include <linux/reboot.h> 29#include <linux/reboot.h>
30#include "common.h"
30 31
31static void __iomem *system_controller_base; 32static void __iomem *system_controller_base;
32 33
@@ -39,14 +40,14 @@ struct mvebu_system_controller {
39}; 40};
40static struct mvebu_system_controller *mvebu_sc; 41static struct mvebu_system_controller *mvebu_sc;
41 42
42const struct mvebu_system_controller armada_370_xp_system_controller = { 43static const struct mvebu_system_controller armada_370_xp_system_controller = {
43 .rstoutn_mask_offset = 0x60, 44 .rstoutn_mask_offset = 0x60,
44 .system_soft_reset_offset = 0x64, 45 .system_soft_reset_offset = 0x64,
45 .rstoutn_mask_reset_out_en = 0x1, 46 .rstoutn_mask_reset_out_en = 0x1,
46 .system_soft_reset = 0x1, 47 .system_soft_reset = 0x1,
47}; 48};
48 49
49const struct mvebu_system_controller orion_system_controller = { 50static const struct mvebu_system_controller orion_system_controller = {
50 .rstoutn_mask_offset = 0x108, 51 .rstoutn_mask_offset = 0x108,
51 .system_soft_reset_offset = 0x10c, 52 .system_soft_reset_offset = 0x10c,
52 .rstoutn_mask_reset_out_en = 0x4, 53 .rstoutn_mask_reset_out_en = 0x4,
diff --git a/arch/arm/mach-nomadik/cpu-8815.c b/arch/arm/mach-nomadik/cpu-8815.c
index cce2c9dfb5d1..4a1065e41e9c 100644
--- a/arch/arm/mach-nomadik/cpu-8815.c
+++ b/arch/arm/mach-nomadik/cpu-8815.c
@@ -110,38 +110,6 @@ static void cpu8815_restart(enum reboot_mode mode, const char *cmd)
110} 110}
111 111
112/* 112/*
113 * The SMSC911x IRQ is connected to a GPIO pin, but the driver expects
114 * to simply request an IRQ passed as a resource. So the GPIO pin needs
115 * to be requested by this hog and set as input.
116 */
117static int __init cpu8815_eth_init(void)
118{
119 struct device_node *eth;
120 int gpio, irq, err;
121
122 eth = of_find_node_by_path("/usb-s8815/ethernet-gpio");
123 if (!eth) {
124 pr_info("could not find any ethernet GPIO\n");
125 return 0;
126 }
127 gpio = of_get_gpio(eth, 0);
128 err = gpio_request(gpio, "eth_irq");
129 if (err) {
130 pr_info("failed to request ethernet GPIO\n");
131 return -ENODEV;
132 }
133 err = gpio_direction_input(gpio);
134 if (err) {
135 pr_info("failed to set ethernet GPIO as input\n");
136 return -ENODEV;
137 }
138 irq = gpio_to_irq(gpio);
139 pr_info("enabled USB-S8815 ethernet GPIO %d, IRQ %d\n", gpio, irq);
140 return 0;
141}
142device_initcall(cpu8815_eth_init);
143
144/*
145 * This GPIO pin turns on a line that is used to detect card insertion 113 * This GPIO pin turns on a line that is used to detect card insertion
146 * on this board. 114 * on this board.
147 */ 115 */
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 1f25f3e99c05..adcef406ff0a 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -19,11 +19,11 @@ secure-common = omap-smc.o omap-secure.o
19 19
20obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common) 20obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
21obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common) 21obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
22obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common) 22obj-$(CONFIG_ARCH_OMAP4) += $(hwmod-common) $(secure-common)
23obj-$(CONFIG_SOC_AM33XX) += irq.o $(hwmod-common) 23obj-$(CONFIG_SOC_AM33XX) += irq.o $(hwmod-common)
24obj-$(CONFIG_SOC_OMAP5) += prm44xx.o $(hwmod-common) $(secure-common) 24obj-$(CONFIG_SOC_OMAP5) += $(hwmod-common) $(secure-common)
25obj-$(CONFIG_SOC_AM43XX) += $(hwmod-common) $(secure-common) 25obj-$(CONFIG_SOC_AM43XX) += $(hwmod-common) $(secure-common)
26obj-$(CONFIG_SOC_DRA7XX) += prm44xx.o $(hwmod-common) $(secure-common) 26obj-$(CONFIG_SOC_DRA7XX) += $(hwmod-common) $(secure-common)
27 27
28ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),) 28ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),)
29obj-y += mcbsp.o 29obj-y += mcbsp.o
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index f7644febee81..e30ef6797c63 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -299,7 +299,6 @@ struct omap_sdrc_params;
299extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0, 299extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
300 struct omap_sdrc_params *sdrc_cs1); 300 struct omap_sdrc_params *sdrc_cs1);
301struct omap2_hsmmc_info; 301struct omap2_hsmmc_info;
302extern int omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers);
303extern void omap_reserve(void); 302extern void omap_reserve(void);
304 303
305struct omap_hwmod; 304struct omap_hwmod;
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index a4e536b11ec9..58347bb874a0 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -32,7 +32,6 @@
32 32
33#include "soc.h" 33#include "soc.h"
34#include "iomap.h" 34#include "iomap.h"
35#include "mux.h"
36#include "control.h" 35#include "control.h"
37#include "display.h" 36#include "display.h"
38#include "prm.h" 37#include "prm.h"
@@ -102,90 +101,13 @@ static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initconst = {
102 { "dss_hdmi", "omapdss_hdmi", -1 }, 101 { "dss_hdmi", "omapdss_hdmi", -1 },
103}; 102};
104 103
105static void __init omap4_tpd12s015_mux_pads(void)
106{
107 omap_mux_init_signal("hdmi_cec",
108 OMAP_PIN_INPUT_PULLUP);
109 omap_mux_init_signal("hdmi_ddc_scl",
110 OMAP_PIN_INPUT_PULLUP);
111 omap_mux_init_signal("hdmi_ddc_sda",
112 OMAP_PIN_INPUT_PULLUP);
113}
114
115static void __init omap4_hdmi_mux_pads(enum omap_hdmi_flags flags)
116{
117 u32 reg;
118 u16 control_i2c_1;
119
120 /*
121 * CONTROL_I2C_1: HDMI_DDC_SDA_PULLUPRESX (bit 28) and
122 * HDMI_DDC_SCL_PULLUPRESX (bit 24) are set to disable
123 * internal pull up resistor.
124 */
125 if (flags & OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP) {
126 control_i2c_1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1;
127 reg = omap4_ctrl_pad_readl(control_i2c_1);
128 reg |= (OMAP4_HDMI_DDC_SDA_PULLUPRESX_MASK |
129 OMAP4_HDMI_DDC_SCL_PULLUPRESX_MASK);
130 omap4_ctrl_pad_writel(reg, control_i2c_1);
131 }
132}
133
134static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
135{
136 u32 enable_mask, enable_shift;
137 u32 pipd_mask, pipd_shift;
138 u32 reg;
139
140 if (dsi_id == 0) {
141 enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
142 enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT;
143 pipd_mask = OMAP4_DSI1_PIPD_MASK;
144 pipd_shift = OMAP4_DSI1_PIPD_SHIFT;
145 } else if (dsi_id == 1) {
146 enable_mask = OMAP4_DSI2_LANEENABLE_MASK;
147 enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT;
148 pipd_mask = OMAP4_DSI2_PIPD_MASK;
149 pipd_shift = OMAP4_DSI2_PIPD_SHIFT;
150 } else {
151 return -ENODEV;
152 }
153
154 reg = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
155
156 reg &= ~enable_mask;
157 reg &= ~pipd_mask;
158
159 reg |= (lanes << enable_shift) & enable_mask;
160 reg |= (lanes << pipd_shift) & pipd_mask;
161
162 omap4_ctrl_pad_writel(reg, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
163
164 return 0;
165}
166
167int __init omap_hdmi_init(enum omap_hdmi_flags flags)
168{
169 if (cpu_is_omap44xx()) {
170 omap4_hdmi_mux_pads(flags);
171 omap4_tpd12s015_mux_pads();
172 }
173
174 return 0;
175}
176
177static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask) 104static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
178{ 105{
179 if (cpu_is_omap44xx())
180 return omap4_dsi_mux_pads(dsi_id, lane_mask);
181
182 return 0; 106 return 0;
183} 107}
184 108
185static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask) 109static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask)
186{ 110{
187 if (cpu_is_omap44xx())
188 omap4_dsi_mux_pads(dsi_id, 0);
189} 111}
190 112
191static int omap_dss_set_min_bus_tput(struct device *dev, unsigned long tput) 113static int omap_dss_set_min_bus_tput(struct device *dev, unsigned long tput)
diff --git a/arch/arm/mach-omap2/dss-common.c b/arch/arm/mach-omap2/dss-common.c
index 365bfd3d9c68..dadccc91488c 100644
--- a/arch/arm/mach-omap2/dss-common.c
+++ b/arch/arm/mach-omap2/dss-common.c
@@ -223,7 +223,7 @@ void __init omap_4430sdp_display_init_of(void)
223static struct connector_dvi_platform_data omap3_igep2_dvi_connector_pdata = { 223static struct connector_dvi_platform_data omap3_igep2_dvi_connector_pdata = {
224 .name = "dvi", 224 .name = "dvi",
225 .source = "tfp410.0", 225 .source = "tfp410.0",
226 .i2c_bus_num = 3, 226 .i2c_bus_num = 2,
227}; 227};
228 228
229static struct platform_device omap3_igep2_dvi_connector_device = { 229static struct platform_device omap3_igep2_dvi_connector_device = {
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 81de56251955..d24926e6340f 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -1502,6 +1502,22 @@ static int gpmc_probe_generic_child(struct platform_device *pdev,
1502 } 1502 }
1503 1503
1504 /* 1504 /*
1505 * For some GPMC devices we still need to rely on the bootloader
1506 * timings because the devices can be connected via FPGA. So far
1507 * the list is smc91x on the omap2 SDP boards, and 8250 on zooms.
1508 * REVISIT: Add timing support from slls644g.pdf and from the
1509 * lan91c96 manual.
1510 */
1511 if (of_device_is_compatible(child, "ns16550a") ||
1512 of_device_is_compatible(child, "smsc,lan91c94") ||
1513 of_device_is_compatible(child, "smsc,lan91c111")) {
1514 dev_warn(&pdev->dev,
1515 "%s using bootloader timings on CS%d\n",
1516 child->name, cs);
1517 goto no_timings;
1518 }
1519
1520 /*
1505 * FIXME: gpmc_cs_request() will map the CS to an arbitary 1521 * FIXME: gpmc_cs_request() will map the CS to an arbitary
1506 * location in the gpmc address space. When booting with 1522 * location in the gpmc address space. When booting with
1507 * device-tree we want the NOR flash to be mapped to the 1523 * device-tree we want the NOR flash to be mapped to the
@@ -1529,6 +1545,7 @@ static int gpmc_probe_generic_child(struct platform_device *pdev,
1529 gpmc_read_timings_dt(child, &gpmc_t); 1545 gpmc_read_timings_dt(child, &gpmc_t);
1530 gpmc_cs_set_timings(cs, &gpmc_t); 1546 gpmc_cs_set_timings(cs, &gpmc_t);
1531 1547
1548no_timings:
1532 if (of_platform_device_create(child, NULL, &pdev->dev)) 1549 if (of_platform_device_create(child, NULL, &pdev->dev))
1533 return 0; 1550 return 0;
1534 1551
@@ -1541,42 +1558,6 @@ err:
1541 return ret; 1558 return ret;
1542} 1559}
1543 1560
1544/*
1545 * REVISIT: Add timing support from slls644g.pdf
1546 */
1547static int gpmc_probe_8250(struct platform_device *pdev,
1548 struct device_node *child)
1549{
1550 struct resource res;
1551 unsigned long base;
1552 int ret, cs;
1553
1554 if (of_property_read_u32(child, "reg", &cs) < 0) {
1555 dev_err(&pdev->dev, "%s has no 'reg' property\n",
1556 child->full_name);
1557 return -ENODEV;
1558 }
1559
1560 if (of_address_to_resource(child, 0, &res) < 0) {
1561 dev_err(&pdev->dev, "%s has malformed 'reg' property\n",
1562 child->full_name);
1563 return -ENODEV;
1564 }
1565
1566 ret = gpmc_cs_request(cs, resource_size(&res), &base);
1567 if (ret < 0) {
1568 dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs);
1569 return ret;
1570 }
1571
1572 if (of_platform_device_create(child, NULL, &pdev->dev))
1573 return 0;
1574
1575 dev_err(&pdev->dev, "failed to create gpmc child %s\n", child->name);
1576
1577 return -ENODEV;
1578}
1579
1580static int gpmc_probe_dt(struct platform_device *pdev) 1561static int gpmc_probe_dt(struct platform_device *pdev)
1581{ 1562{
1582 int ret; 1563 int ret;
@@ -1618,10 +1599,9 @@ static int gpmc_probe_dt(struct platform_device *pdev)
1618 else if (of_node_cmp(child->name, "onenand") == 0) 1599 else if (of_node_cmp(child->name, "onenand") == 0)
1619 ret = gpmc_probe_onenand_child(pdev, child); 1600 ret = gpmc_probe_onenand_child(pdev, child);
1620 else if (of_node_cmp(child->name, "ethernet") == 0 || 1601 else if (of_node_cmp(child->name, "ethernet") == 0 ||
1621 of_node_cmp(child->name, "nor") == 0) 1602 of_node_cmp(child->name, "nor") == 0 ||
1603 of_node_cmp(child->name, "uart") == 0)
1622 ret = gpmc_probe_generic_child(pdev, child); 1604 ret = gpmc_probe_generic_child(pdev, child);
1623 else if (of_node_cmp(child->name, "8250") == 0)
1624 ret = gpmc_probe_8250(pdev, child);
1625 1605
1626 if (WARN(ret < 0, "%s: probing gpmc child %s failed\n", 1606 if (WARN(ret < 0, "%s: probing gpmc child %s failed\n",
1627 __func__, child->full_name)) 1607 __func__, child->full_name))
diff --git a/arch/arm/mach-omap2/omap-secure.h b/arch/arm/mach-omap2/omap-secure.h
index 8cc7d331437d..3e97c6c8ecf1 100644
--- a/arch/arm/mach-omap2/omap-secure.h
+++ b/arch/arm/mach-omap2/omap-secure.h
@@ -76,6 +76,13 @@ static inline void omap_barrier_reserve_memblock(void)
76{ } 76{ }
77#endif 77#endif
78 78
79#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
79void set_cntfreq(void); 80void set_cntfreq(void);
81#else
82static inline void set_cntfreq(void)
83{
84}
85#endif
86
80#endif /* __ASSEMBLER__ */ 87#endif /* __ASSEMBLER__ */
81#endif /* OMAP_ARCH_OMAP_SECURE_H */ 88#endif /* OMAP_ARCH_OMAP_SECURE_H */
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 57911430324e..b39efd46abf9 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -35,7 +35,6 @@
35#include "iomap.h" 35#include "iomap.h"
36#include "common.h" 36#include "common.h"
37#include "mmc.h" 37#include "mmc.h"
38#include "hsmmc.h"
39#include "prminst44xx.h" 38#include "prminst44xx.h"
40#include "prcm_mpu44xx.h" 39#include "prcm_mpu44xx.h"
41#include "omap4-sar-layout.h" 40#include "omap4-sar-layout.h"
@@ -284,59 +283,3 @@ skip_errata_init:
284 omap_wakeupgen_init(); 283 omap_wakeupgen_init();
285 irqchip_init(); 284 irqchip_init();
286} 285}
287
288#if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
289static int omap4_twl6030_hsmmc_late_init(struct device *dev)
290{
291 int irq = 0;
292 struct platform_device *pdev = container_of(dev,
293 struct platform_device, dev);
294 struct omap_mmc_platform_data *pdata = dev->platform_data;
295
296 /* Setting MMC1 Card detect Irq */
297 if (pdev->id == 0) {
298 irq = twl6030_mmc_card_detect_config();
299 if (irq < 0) {
300 dev_err(dev, "%s: Error card detect config(%d)\n",
301 __func__, irq);
302 return irq;
303 }
304 pdata->slots[0].card_detect_irq = irq;
305 pdata->slots[0].card_detect = twl6030_mmc_card_detect;
306 }
307 return 0;
308}
309
310static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev)
311{
312 struct omap_mmc_platform_data *pdata;
313
314 /* dev can be null if CONFIG_MMC_OMAP_HS is not set */
315 if (!dev) {
316 pr_err("Failed %s\n", __func__);
317 return;
318 }
319 pdata = dev->platform_data;
320 pdata->init = omap4_twl6030_hsmmc_late_init;
321}
322
323int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
324{
325 struct omap2_hsmmc_info *c;
326
327 omap_hsmmc_init(controllers);
328 for (c = controllers; c->mmc; c++) {
329 /* pdev can be null if CONFIG_MMC_OMAP_HS is not set */
330 if (!c->pdev)
331 continue;
332 omap4_twl6030_hsmmc_set_late_init(&c->pdev->dev);
333 }
334
335 return 0;
336}
337#else
338int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
339{
340 return 0;
341}
342#endif
diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c
index 10c71450cf63..39f020c982e8 100644
--- a/arch/arm/mach-omap2/pdata-quirks.c
+++ b/arch/arm/mach-omap2/pdata-quirks.c
@@ -139,6 +139,7 @@ struct of_dev_auxdata omap_auxdata_lookup[] __initdata = {
139 139
140static struct pdata_init pdata_quirks[] __initdata = { 140static struct pdata_init pdata_quirks[] __initdata = {
141#ifdef CONFIG_ARCH_OMAP3 141#ifdef CONFIG_ARCH_OMAP3
142 { "nokia,omap3-n900", hsmmc2_internal_input_clk, },
142 { "nokia,omap3-n9", hsmmc2_internal_input_clk, }, 143 { "nokia,omap3-n9", hsmmc2_internal_input_clk, },
143 { "nokia,omap3-n950", hsmmc2_internal_input_clk, }, 144 { "nokia,omap3-n950", hsmmc2_internal_input_clk, },
144 { "isee,omap3-igep0020", omap3_igep0020_legacy_init, }, 145 { "isee,omap3-igep0020", omap3_igep0020_legacy_init, },
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 93b80e5da8d4..1f3770a8a728 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -120,7 +120,7 @@ static void omap3_save_secure_ram_context(void)
120 * will hang the system. 120 * will hang the system.
121 */ 121 */
122 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); 122 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
123 ret = _omap_save_secure_sram((u32 *) 123 ret = _omap_save_secure_sram((u32 *)(unsigned long)
124 __pa(omap3_secure_ram_storage)); 124 __pa(omap3_secure_ram_storage));
125 pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state); 125 pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state);
126 /* Following is for error tracking, it should not happen */ 126 /* Following is for error tracking, it should not happen */
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index e233dfcbc186..93a2a6e4260f 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -128,7 +128,8 @@ skip_voltdm:
128 for (i = 0; i < pwrdm->banks; i++) 128 for (i = 0; i < pwrdm->banks; i++)
129 pwrdm->ret_mem_off_counter[i] = 0; 129 pwrdm->ret_mem_off_counter[i] = 0;
130 130
131 arch_pwrdm->pwrdm_wait_transition(pwrdm); 131 if (arch_pwrdm && arch_pwrdm->pwrdm_wait_transition)
132 arch_pwrdm->pwrdm_wait_transition(pwrdm);
132 pwrdm->state = pwrdm_read_pwrst(pwrdm); 133 pwrdm->state = pwrdm_read_pwrst(pwrdm);
133 pwrdm->state_counter[pwrdm->state] = 1; 134 pwrdm->state_counter[pwrdm->state] = 1;
134 135
diff --git a/arch/arm/mach-omap2/prm44xx_54xx.h b/arch/arm/mach-omap2/prm44xx_54xx.h
index 7a976065e138..8d95aa543ef5 100644
--- a/arch/arm/mach-omap2/prm44xx_54xx.h
+++ b/arch/arm/mach-omap2/prm44xx_54xx.h
@@ -43,7 +43,7 @@ extern void omap4_prm_vcvp_write(u32 val, u8 offset);
43extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset); 43extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
44 44
45#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ 45#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
46 defined(CONFIG_SOC_DRA7XX) 46 defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM43XX)
47void omap44xx_prm_reconfigure_io_chain(void); 47void omap44xx_prm_reconfigure_io_chain(void);
48#else 48#else
49static inline void omap44xx_prm_reconfigure_io_chain(void) 49static inline void omap44xx_prm_reconfigure_io_chain(void)
diff --git a/arch/arm/mach-orion5x/board-dt.c b/arch/arm/mach-orion5x/board-dt.c
index b91002ca92f3..c134a826070a 100644
--- a/arch/arm/mach-orion5x/board-dt.c
+++ b/arch/arm/mach-orion5x/board-dt.c
@@ -21,7 +21,7 @@
21#include <plat/irq.h> 21#include <plat/irq.h>
22#include "common.h" 22#include "common.h"
23 23
24struct of_dev_auxdata orion5x_auxdata_lookup[] __initdata = { 24static struct of_dev_auxdata orion5x_auxdata_lookup[] __initdata = {
25 OF_DEV_AUXDATA("marvell,orion-spi", 0xf1010600, "orion_spi.0", NULL), 25 OF_DEV_AUXDATA("marvell,orion-spi", 0xf1010600, "orion_spi.0", NULL),
26 OF_DEV_AUXDATA("marvell,mv64xxx-i2c", 0xf1011000, "mv64xxx_i2c.0", 26 OF_DEV_AUXDATA("marvell,mv64xxx-i2c", 0xf1011000, "mv64xxx_i2c.0",
27 NULL), 27 NULL),
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index 91a5852b44f3..3f1de1111e0f 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -24,7 +24,6 @@
24#include <asm/page.h> 24#include <asm/page.h>
25#include <asm/setup.h> 25#include <asm/setup.h>
26#include <asm/system_misc.h> 26#include <asm/system_misc.h>
27#include <asm/timex.h>
28#include <asm/mach/arch.h> 27#include <asm/mach/arch.h>
29#include <asm/mach/map.h> 28#include <asm/mach/map.h>
30#include <asm/mach/time.h> 29#include <asm/mach/time.h>
@@ -135,7 +134,7 @@ void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
135/***************************************************************************** 134/*****************************************************************************
136 * SPI 135 * SPI
137 ****************************************************************************/ 136 ****************************************************************************/
138void __init orion5x_spi_init() 137void __init orion5x_spi_init(void)
139{ 138{
140 orion_spi_init(SPI_PHYS_BASE); 139 orion_spi_init(SPI_PHYS_BASE);
141} 140}
@@ -185,7 +184,7 @@ static void __init orion5x_crypto_init(void)
185/***************************************************************************** 184/*****************************************************************************
186 * Watchdog 185 * Watchdog
187 ****************************************************************************/ 186 ****************************************************************************/
188void __init orion5x_wdt_init(void) 187static void __init orion5x_wdt_init(void)
189{ 188{
190 orion_wdt_init(); 189 orion_wdt_init();
191} 190}
@@ -246,7 +245,7 @@ void orion5x_setup_wins(void)
246 245
247int orion5x_tclk; 246int orion5x_tclk;
248 247
249int __init orion5x_find_tclk(void) 248static int __init orion5x_find_tclk(void)
250{ 249{
251 u32 dev, rev; 250 u32 dev, rev;
252 251
diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c
index 4b2aefd1d961..dc01c4ffc9a8 100644
--- a/arch/arm/mach-orion5x/db88f5281-setup.c
+++ b/arch/arm/mach-orion5x/db88f5281-setup.c
@@ -202,7 +202,7 @@ __initcall(db88f5281_7seg_init);
202 * PCI 202 * PCI
203 ****************************************************************************/ 203 ****************************************************************************/
204 204
205void __init db88f5281_pci_preinit(void) 205static void __init db88f5281_pci_preinit(void)
206{ 206{
207 int pin; 207 int pin;
208 208
diff --git a/arch/arm/mach-orion5x/irq.c b/arch/arm/mach-orion5x/irq.c
index 30a192b9c517..9654b0cc5892 100644
--- a/arch/arm/mach-orion5x/irq.c
+++ b/arch/arm/mach-orion5x/irq.c
@@ -16,6 +16,7 @@
16#include <mach/bridge-regs.h> 16#include <mach/bridge-regs.h>
17#include <plat/orion-gpio.h> 17#include <plat/orion-gpio.h>
18#include <plat/irq.h> 18#include <plat/irq.h>
19#include "common.h"
19 20
20static int __initdata gpio0_irqs[4] = { 21static int __initdata gpio0_irqs[4] = {
21 IRQ_ORION5X_GPIO_0_7, 22 IRQ_ORION5X_GPIO_0_7,
diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c
index 7fab67053030..87a12d6930ff 100644
--- a/arch/arm/mach-orion5x/pci.c
+++ b/arch/arm/mach-orion5x/pci.c
@@ -240,11 +240,11 @@ static int __init pcie_setup(struct pci_sys_data *sys)
240#define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc08) : \ 240#define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc08) : \
241 ((n) == 1) ? ORION5X_PCI_REG(0xd08) : \ 241 ((n) == 1) ? ORION5X_PCI_REG(0xd08) : \
242 ((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \ 242 ((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \
243 ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : 0) 243 ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : NULL)
244#define PCI_BAR_REMAP_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc48) : \ 244#define PCI_BAR_REMAP_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc48) : \
245 ((n) == 1) ? ORION5X_PCI_REG(0xd48) : \ 245 ((n) == 1) ? ORION5X_PCI_REG(0xd48) : \
246 ((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \ 246 ((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \
247 ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : 0) 247 ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : NULL)
248#define PCI_BAR_ENABLE ORION5X_PCI_REG(0xc3c) 248#define PCI_BAR_ENABLE ORION5X_PCI_REG(0xc3c)
249#define PCI_ADDR_DECODE_CTRL ORION5X_PCI_REG(0xd3c) 249#define PCI_ADDR_DECODE_CTRL ORION5X_PCI_REG(0xd3c)
250 250
diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c
index b1cf68493ffc..b576ef5f18a1 100644
--- a/arch/arm/mach-orion5x/rd88f5182-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5182-setup.c
@@ -108,7 +108,7 @@ static struct platform_device rd88f5182_gpio_leds = {
108 * PCI 108 * PCI
109 ****************************************************************************/ 109 ****************************************************************************/
110 110
111void __init rd88f5182_pci_preinit(void) 111static void __init rd88f5182_pci_preinit(void)
112{ 112{
113 int pin; 113 int pin;
114 114
diff --git a/arch/arm/mach-orion5x/terastation_pro2-setup.c b/arch/arm/mach-orion5x/terastation_pro2-setup.c
index 7e9064844698..6208d125c1b9 100644
--- a/arch/arm/mach-orion5x/terastation_pro2-setup.c
+++ b/arch/arm/mach-orion5x/terastation_pro2-setup.c
@@ -77,7 +77,7 @@ static struct platform_device tsp2_nor_flash = {
77#define TSP2_PCI_SLOT0_OFFS 7 77#define TSP2_PCI_SLOT0_OFFS 7
78#define TSP2_PCI_SLOT0_IRQ_PIN 11 78#define TSP2_PCI_SLOT0_IRQ_PIN 11
79 79
80void __init tsp2_pci_preinit(void) 80static void __init tsp2_pci_preinit(void)
81{ 81{
82 int pin; 82 int pin;
83 83
diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c
index e90c0618fdad..9136797addb2 100644
--- a/arch/arm/mach-orion5x/ts209-setup.c
+++ b/arch/arm/mach-orion5x/ts209-setup.c
@@ -106,7 +106,7 @@ static struct platform_device qnap_ts209_nor_flash = {
106#define QNAP_TS209_PCI_SLOT0_IRQ_PIN 6 106#define QNAP_TS209_PCI_SLOT0_IRQ_PIN 6
107#define QNAP_TS209_PCI_SLOT1_IRQ_PIN 7 107#define QNAP_TS209_PCI_SLOT1_IRQ_PIN 7
108 108
109void __init qnap_ts209_pci_preinit(void) 109static void __init qnap_ts209_pci_preinit(void)
110{ 110{
111 int pin; 111 int pin;
112 112
diff --git a/arch/arm/mach-orion5x/ts78xx-setup.c b/arch/arm/mach-orion5x/ts78xx-setup.c
index e960855d32ac..db16dae441e2 100644
--- a/arch/arm/mach-orion5x/ts78xx-setup.c
+++ b/arch/arm/mach-orion5x/ts78xx-setup.c
@@ -57,7 +57,7 @@ static struct map_desc ts78xx_io_desc[] __initdata = {
57 }, 57 },
58}; 58};
59 59
60void __init ts78xx_map_io(void) 60static void __init ts78xx_map_io(void)
61{ 61{
62 orion5x_map_io(); 62 orion5x_map_io();
63 iotable_init(ts78xx_io_desc, ARRAY_SIZE(ts78xx_io_desc)); 63 iotable_init(ts78xx_io_desc, ARRAY_SIZE(ts78xx_io_desc));
diff --git a/arch/arm/mach-s3c64xx/mach-mini6410.c b/arch/arm/mach-s3c64xx/mach-mini6410.c
index 58d46a3d7b78..97ae4703cb78 100644
--- a/arch/arm/mach-s3c64xx/mach-mini6410.c
+++ b/arch/arm/mach-s3c64xx/mach-mini6410.c
@@ -36,7 +36,9 @@
36#include <plat/devs.h> 36#include <plat/devs.h>
37#include <plat/fb.h> 37#include <plat/fb.h>
38#include <linux/platform_data/mtd-nand-s3c2410.h> 38#include <linux/platform_data/mtd-nand-s3c2410.h>
39#include <linux/platform_data/mmc-sdhci-s3c.h>
39#include <plat/regs-serial.h> 40#include <plat/regs-serial.h>
41#include <plat/sdhci.h>
40#include <linux/platform_data/touchscreen-s3c2410.h> 42#include <linux/platform_data/touchscreen-s3c2410.h>
41 43
42#include <video/platform_lcd.h> 44#include <video/platform_lcd.h>
@@ -214,6 +216,13 @@ static struct platform_device mini6410_lcd_powerdev = {
214 .dev.platform_data = &mini6410_lcd_power_data, 216 .dev.platform_data = &mini6410_lcd_power_data,
215}; 217};
216 218
219static struct s3c_sdhci_platdata mini6410_hsmmc1_pdata = {
220 .max_width = 4,
221 .cd_type = S3C_SDHCI_CD_GPIO,
222 .ext_cd_gpio = S3C64XX_GPN(10),
223 .ext_cd_gpio_invert = true,
224};
225
217static struct platform_device *mini6410_devices[] __initdata = { 226static struct platform_device *mini6410_devices[] __initdata = {
218 &mini6410_device_eth, 227 &mini6410_device_eth,
219 &s3c_device_hsmmc0, 228 &s3c_device_hsmmc0,
@@ -321,6 +330,7 @@ static void __init mini6410_machine_init(void)
321 330
322 s3c_nand_set_platdata(&mini6410_nand_info); 331 s3c_nand_set_platdata(&mini6410_nand_info);
323 s3c_fb_set_platdata(&mini6410_lcd_pdata[features.lcd_index]); 332 s3c_fb_set_platdata(&mini6410_lcd_pdata[features.lcd_index]);
333 s3c_sdhci1_set_platdata(&mini6410_hsmmc1_pdata);
324 s3c24xx_ts_set_platdata(NULL); 334 s3c24xx_ts_set_platdata(NULL);
325 335
326 /* configure nCS1 width to 16 bits */ 336 /* configure nCS1 width to 16 bits */
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index a4a4b75109b2..aa9017bb750c 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -1,6 +1,10 @@
1config ARCH_SHMOBILE
2 bool
3
1config ARCH_SHMOBILE_MULTI 4config ARCH_SHMOBILE_MULTI
2 bool "SH-Mobile Series" if ARCH_MULTI_V7 5 bool "SH-Mobile Series" if ARCH_MULTI_V7
3 depends on MMU 6 depends on MMU
7 select ARCH_SHMOBILE
4 select CPU_V7 8 select CPU_V7
5 select GENERIC_CLOCKEVENTS 9 select GENERIC_CLOCKEVENTS
6 select HAVE_ARM_SCU if SMP 10 select HAVE_ARM_SCU if SMP
@@ -30,7 +34,7 @@ config MACH_KZM9D
30comment "SH-Mobile System Configuration" 34comment "SH-Mobile System Configuration"
31endif 35endif
32 36
33if ARCH_SHMOBILE 37if ARCH_SHMOBILE_LEGACY
34 38
35comment "SH-Mobile System Type" 39comment "SH-Mobile System Type"
36 40
@@ -97,18 +101,23 @@ config ARCH_R8A7790
97 101
98config ARCH_R8A7791 102config ARCH_R8A7791
99 bool "R-Car M2 (R8A77910)" 103 bool "R-Car M2 (R8A77910)"
104 select ARCH_WANT_OPTIONAL_GPIOLIB
100 select ARM_GIC 105 select ARM_GIC
101 select CPU_V7 106 select CPU_V7
102 select SH_CLK_CPG 107 select SH_CLK_CPG
108 select RENESAS_IRQC
103 109
104config ARCH_EMEV2 110config ARCH_EMEV2
105 bool "Emma Mobile EV2" 111 bool "Emma Mobile EV2"
106 select ARCH_WANT_OPTIONAL_GPIOLIB 112 select ARCH_WANT_OPTIONAL_GPIOLIB
107 select ARM_GIC 113 select ARM_GIC
108 select CPU_V7 114 select CPU_V7
115 select USE_OF
116 select AUTO_ZRELADDR
109 117
110config ARCH_R7S72100 118config ARCH_R7S72100
111 bool "RZ/A1H (R7S72100)" 119 bool "RZ/A1H (R7S72100)"
120 select ARCH_WANT_OPTIONAL_GPIOLIB
112 select ARM_GIC 121 select ARM_GIC
113 select CPU_V7 122 select CPU_V7
114 select SH_CLK_CPG 123 select SH_CLK_CPG
@@ -231,12 +240,6 @@ config MACH_KOELSCH
231 depends on ARCH_R8A7791 240 depends on ARCH_R8A7791
232 select USE_OF 241 select USE_OF
233 242
234config MACH_KZM9D
235 bool "KZM9D board"
236 depends on ARCH_EMEV2
237 select REGULATOR_FIXED_VOLTAGE if REGULATOR
238 select USE_OF
239
240config MACH_KZM9G 243config MACH_KZM9G
241 bool "KZM-A9-GT board" 244 bool "KZM-A9-GT board"
242 depends on ARCH_SH73A0 245 depends on ARCH_SH73A0
@@ -274,7 +277,7 @@ source "drivers/sh/Kconfig"
274 277
275endif 278endif
276 279
277if ARCH_SHMOBILE || ARCH_SHMOBILE_MULTI 280if ARCH_SHMOBILE
278 281
279menu "Timer and clock configuration" 282menu "Timer and clock configuration"
280 283
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index 51db2bcafabf..c7e877499dc2 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -71,7 +71,6 @@ obj-$(CONFIG_MACH_LAGER_REFERENCE) += board-lager-reference.o
71obj-$(CONFIG_MACH_ARMADILLO800EVA) += board-armadillo800eva.o 71obj-$(CONFIG_MACH_ARMADILLO800EVA) += board-armadillo800eva.o
72obj-$(CONFIG_MACH_ARMADILLO800EVA_REFERENCE) += board-armadillo800eva-reference.o 72obj-$(CONFIG_MACH_ARMADILLO800EVA_REFERENCE) += board-armadillo800eva-reference.o
73obj-$(CONFIG_MACH_KOELSCH) += board-koelsch.o 73obj-$(CONFIG_MACH_KOELSCH) += board-koelsch.o
74obj-$(CONFIG_MACH_KZM9D) += board-kzm9d.o
75obj-$(CONFIG_MACH_KZM9G) += board-kzm9g.o 74obj-$(CONFIG_MACH_KZM9G) += board-kzm9g.o
76obj-$(CONFIG_MACH_KZM9G_REFERENCE) += board-kzm9g-reference.o 75obj-$(CONFIG_MACH_KZM9G_REFERENCE) += board-kzm9g-reference.o
77endif 76endif
diff --git a/arch/arm/mach-shmobile/Makefile.boot b/arch/arm/mach-shmobile/Makefile.boot
index 391d72a5536c..4f30e3dc0919 100644
--- a/arch/arm/mach-shmobile/Makefile.boot
+++ b/arch/arm/mach-shmobile/Makefile.boot
@@ -8,7 +8,6 @@ loadaddr-$(CONFIG_MACH_BOCKW) += 0x60008000
8loadaddr-$(CONFIG_MACH_BOCKW_REFERENCE) += 0x60008000 8loadaddr-$(CONFIG_MACH_BOCKW_REFERENCE) += 0x60008000
9loadaddr-$(CONFIG_MACH_GENMAI) += 0x8008000 9loadaddr-$(CONFIG_MACH_GENMAI) += 0x8008000
10loadaddr-$(CONFIG_MACH_KOELSCH) += 0x40008000 10loadaddr-$(CONFIG_MACH_KOELSCH) += 0x40008000
11loadaddr-$(CONFIG_MACH_KZM9D) += 0x40008000
12loadaddr-$(CONFIG_MACH_KZM9G) += 0x41008000 11loadaddr-$(CONFIG_MACH_KZM9G) += 0x41008000
13loadaddr-$(CONFIG_MACH_KZM9G_REFERENCE) += 0x41008000 12loadaddr-$(CONFIG_MACH_KZM9G_REFERENCE) += 0x41008000
14loadaddr-$(CONFIG_MACH_LAGER) += 0x40008000 13loadaddr-$(CONFIG_MACH_LAGER) += 0x40008000
diff --git a/arch/arm/mach-shmobile/board-ape6evm.c b/arch/arm/mach-shmobile/board-ape6evm.c
index 0fa068e30a30..fe071a9130b7 100644
--- a/arch/arm/mach-shmobile/board-ape6evm.c
+++ b/arch/arm/mach-shmobile/board-ape6evm.c
@@ -168,7 +168,7 @@ static const struct sh_mmcif_plat_data mmcif0_pdata __initconst = {
168}; 168};
169 169
170static const struct resource mmcif0_resources[] __initconst = { 170static const struct resource mmcif0_resources[] __initconst = {
171 DEFINE_RES_MEM_NAMED(0xee200000, 0x100, "MMCIF0"), 171 DEFINE_RES_MEM(0xee200000, 0x100),
172 DEFINE_RES_IRQ(gic_spi(169)), 172 DEFINE_RES_IRQ(gic_spi(169)),
173}; 173};
174 174
@@ -179,7 +179,7 @@ static const struct sh_mobile_sdhi_info sdhi0_pdata __initconst = {
179}; 179};
180 180
181static const struct resource sdhi0_resources[] __initconst = { 181static const struct resource sdhi0_resources[] __initconst = {
182 DEFINE_RES_MEM_NAMED(0xee100000, 0x100, "SDHI0"), 182 DEFINE_RES_MEM(0xee100000, 0x100),
183 DEFINE_RES_IRQ(gic_spi(165)), 183 DEFINE_RES_IRQ(gic_spi(165)),
184}; 184};
185 185
@@ -191,7 +191,7 @@ static const struct sh_mobile_sdhi_info sdhi1_pdata __initconst = {
191}; 191};
192 192
193static const struct resource sdhi1_resources[] __initconst = { 193static const struct resource sdhi1_resources[] __initconst = {
194 DEFINE_RES_MEM_NAMED(0xee120000, 0x100, "SDHI1"), 194 DEFINE_RES_MEM(0xee120000, 0x100),
195 DEFINE_RES_IRQ(gic_spi(166)), 195 DEFINE_RES_IRQ(gic_spi(166)),
196}; 196};
197 197
diff --git a/arch/arm/mach-shmobile/board-bockw-reference.c b/arch/arm/mach-shmobile/board-bockw-reference.c
index ae88fdad4b3a..875cf3f3f503 100644
--- a/arch/arm/mach-shmobile/board-bockw-reference.c
+++ b/arch/arm/mach-shmobile/board-bockw-reference.c
@@ -19,7 +19,6 @@
19 */ 19 */
20 20
21#include <linux/of_platform.h> 21#include <linux/of_platform.h>
22#include <linux/pinctrl/machine.h>
23#include <mach/common.h> 22#include <mach/common.h>
24#include <mach/r8a7778.h> 23#include <mach/r8a7778.h>
25#include <asm/mach/arch.h> 24#include <asm/mach/arch.h>
@@ -28,14 +27,6 @@
28 * see board-bock.c for checking detail of dip-switch 27 * see board-bock.c for checking detail of dip-switch
29 */ 28 */
30 29
31static const struct pinctrl_map bockw_pinctrl_map[] = {
32 /* SCIF0 */
33 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778",
34 "scif0_data_a", "scif0"),
35 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778",
36 "scif0_ctrl", "scif0"),
37};
38
39#define FPGA 0x18200000 30#define FPGA 0x18200000
40#define IRQ0MR 0x30 31#define IRQ0MR 0x30
41#define COMCTLR 0x101c 32#define COMCTLR 0x101c
@@ -45,10 +36,6 @@ static void __init bockw_init(void)
45 36
46 r8a7778_clock_init(); 37 r8a7778_clock_init();
47 r8a7778_init_irq_extpin_dt(1); 38 r8a7778_init_irq_extpin_dt(1);
48
49 pinctrl_register_mappings(bockw_pinctrl_map,
50 ARRAY_SIZE(bockw_pinctrl_map));
51 r8a7778_pinmux_init();
52 r8a7778_add_dt_devices(); 39 r8a7778_add_dt_devices();
53 40
54 fpga = ioremap_nocache(FPGA, SZ_1M); 41 fpga = ioremap_nocache(FPGA, SZ_1M);
diff --git a/arch/arm/mach-shmobile/board-kzm9d.c b/arch/arm/mach-shmobile/board-kzm9d.c
deleted file mode 100644
index 30c2cc695b12..000000000000
--- a/arch/arm/mach-shmobile/board-kzm9d.c
+++ /dev/null
@@ -1,92 +0,0 @@
1/*
2 * kzm9d board support
3 *
4 * Copyright (C) 2012 Renesas Solutions Corp.
5 * Copyright (C) 2012 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/kernel.h>
22#include <linux/interrupt.h>
23#include <linux/platform_device.h>
24#include <linux/regulator/fixed.h>
25#include <linux/regulator/machine.h>
26#include <linux/smsc911x.h>
27#include <mach/common.h>
28#include <mach/emev2.h>
29#include <asm/mach-types.h>
30#include <asm/mach/arch.h>
31
32/* Dummy supplies, where voltage doesn't matter */
33static struct regulator_consumer_supply dummy_supplies[] = {
34 REGULATOR_SUPPLY("vddvario", "smsc911x"),
35 REGULATOR_SUPPLY("vdd33a", "smsc911x"),
36};
37
38/* Ether */
39static struct resource smsc911x_resources[] = {
40 [0] = {
41 .start = 0x20000000,
42 .end = 0x2000ffff,
43 .flags = IORESOURCE_MEM,
44 },
45 [1] = {
46 .start = EMEV2_GPIO_IRQ(1),
47 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH,
48 },
49};
50
51static struct smsc911x_platform_config smsc911x_platdata = {
52 .flags = SMSC911X_USE_32BIT,
53 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
54 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
55};
56
57static struct platform_device smsc91x_device = {
58 .name = "smsc911x",
59 .id = -1,
60 .dev = {
61 .platform_data = &smsc911x_platdata,
62 },
63 .num_resources = ARRAY_SIZE(smsc911x_resources),
64 .resource = smsc911x_resources,
65};
66
67static struct platform_device *kzm9d_devices[] __initdata = {
68 &smsc91x_device,
69};
70
71void __init kzm9d_add_standard_devices(void)
72{
73 regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
74
75 emev2_add_standard_devices();
76
77 platform_add_devices(kzm9d_devices, ARRAY_SIZE(kzm9d_devices));
78}
79
80static const char *kzm9d_boards_compat_dt[] __initdata = {
81 "renesas,kzm9d",
82 NULL,
83};
84
85DT_MACHINE_START(KZM9D_DT, "kzm9d")
86 .smp = smp_ops(emev2_smp_ops),
87 .map_io = emev2_map_io,
88 .init_early = emev2_init_delay,
89 .init_machine = kzm9d_add_standard_devices,
90 .init_late = shmobile_init_late,
91 .dt_compat = kzm9d_boards_compat_dt,
92MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-lager-reference.c b/arch/arm/mach-shmobile/board-lager-reference.c
index 1a1a4a888632..7df9ea0839db 100644
--- a/arch/arm/mach-shmobile/board-lager-reference.c
+++ b/arch/arm/mach-shmobile/board-lager-reference.c
@@ -20,16 +20,15 @@
20 20
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/of_platform.h> 22#include <linux/of_platform.h>
23#include <mach/rcar-gen2.h>
23#include <mach/r8a7790.h> 24#include <mach/r8a7790.h>
24#include <asm/mach/arch.h> 25#include <asm/mach/arch.h>
25 26
26static void __init lager_add_standard_devices(void) 27static void __init lager_add_standard_devices(void)
27{ 28{
28 /* clocks are setup late during boot in the case of DT */
29 r8a7790_clock_init(); 29 r8a7790_clock_init();
30
31 r8a7790_add_dt_devices(); 30 r8a7790_add_dt_devices();
32 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 31 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
33} 32}
34 33
35static const char *lager_boards_compat_dt[] __initdata = { 34static const char *lager_boards_compat_dt[] __initdata = {
diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c
index a8d3ce646fb9..78a31b667988 100644
--- a/arch/arm/mach-shmobile/board-lager.c
+++ b/arch/arm/mach-shmobile/board-lager.c
@@ -148,7 +148,7 @@ static const struct sh_mmcif_plat_data mmcif1_pdata __initconst = {
148}; 148};
149 149
150static const struct resource mmcif1_resources[] __initconst = { 150static const struct resource mmcif1_resources[] __initconst = {
151 DEFINE_RES_MEM_NAMED(0xee220000, 0x80, "MMCIF1"), 151 DEFINE_RES_MEM(0xee220000, 0x80),
152 DEFINE_RES_IRQ(gic_spi(170)), 152 DEFINE_RES_IRQ(gic_spi(170)),
153}; 153};
154 154
diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
index da1352f5f71b..d832a4477b4b 100644
--- a/arch/arm/mach-shmobile/board-marzen.c
+++ b/arch/arm/mach-shmobile/board-marzen.c
@@ -29,6 +29,7 @@
29#include <linux/leds.h> 29#include <linux/leds.h>
30#include <linux/dma-mapping.h> 30#include <linux/dma-mapping.h>
31#include <linux/pinctrl/machine.h> 31#include <linux/pinctrl/machine.h>
32#include <linux/platform_data/camera-rcar.h>
32#include <linux/platform_data/gpio-rcar.h> 33#include <linux/platform_data/gpio-rcar.h>
33#include <linux/platform_data/rcar-du.h> 34#include <linux/platform_data/rcar-du.h>
34#include <linux/platform_data/usb-rcar-phy.h> 35#include <linux/platform_data/usb-rcar-phy.h>
@@ -259,10 +260,30 @@ static struct platform_device leds_device = {
259 }, 260 },
260}; 261};
261 262
263/* VIN */
262static struct rcar_vin_platform_data vin_platform_data __initdata = { 264static struct rcar_vin_platform_data vin_platform_data __initdata = {
263 .flags = RCAR_VIN_BT656, 265 .flags = RCAR_VIN_BT656,
264}; 266};
265 267
268#define MARZEN_VIN(idx) \
269static struct resource vin##idx##_resources[] __initdata = { \
270 DEFINE_RES_MEM(0xffc50000 + 0x1000 * (idx), 0x1000), \
271 DEFINE_RES_IRQ(gic_iid(0x5f + (idx))), \
272}; \
273 \
274static struct platform_device_info vin##idx##_info __initdata = { \
275 .parent = &platform_bus, \
276 .name = "r8a7779-vin", \
277 .id = idx, \
278 .res = vin##idx##_resources, \
279 .num_res = ARRAY_SIZE(vin##idx##_resources), \
280 .dma_mask = DMA_BIT_MASK(32), \
281 .data = &vin_platform_data, \
282 .size_data = sizeof(vin_platform_data), \
283}
284MARZEN_VIN(1);
285MARZEN_VIN(3);
286
266#define MARZEN_CAMERA(idx) \ 287#define MARZEN_CAMERA(idx) \
267static struct i2c_board_info camera##idx##_info = { \ 288static struct i2c_board_info camera##idx##_info = { \
268 I2C_BOARD_INFO("adv7180", 0x20 + (idx)), \ 289 I2C_BOARD_INFO("adv7180", 0x20 + (idx)), \
@@ -326,8 +347,6 @@ static const struct pinctrl_map marzen_pinctrl_map[] = {
326 "sdhi0_ctrl", "sdhi0"), 347 "sdhi0_ctrl", "sdhi0"),
327 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779", 348 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
328 "sdhi0_cd", "sdhi0"), 349 "sdhi0_cd", "sdhi0"),
329 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
330 "sdhi0_wp", "sdhi0"),
331 /* SMSC */ 350 /* SMSC */
332 PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a7779", 351 PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a7779",
333 "intc_irq1_b", "intc"), 352 "intc_irq1_b", "intc"),
@@ -367,8 +386,8 @@ static void __init marzen_init(void)
367 r8a7779_init_irq_extpin(1); /* IRQ1 as individual interrupt */ 386 r8a7779_init_irq_extpin(1); /* IRQ1 as individual interrupt */
368 387
369 r8a7779_add_standard_devices(); 388 r8a7779_add_standard_devices();
370 r8a7779_add_vin_device(1, &vin_platform_data); 389 platform_device_register_full(&vin1_info);
371 r8a7779_add_vin_device(3, &vin_platform_data); 390 platform_device_register_full(&vin3_info);
372 platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices)); 391 platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices));
373 marzen_add_du_device(); 392 marzen_add_du_device();
374} 393}
diff --git a/arch/arm/mach-shmobile/clock-r7s72100.c b/arch/arm/mach-shmobile/clock-r7s72100.c
index 4aba20ca127e..7b457aed8253 100644
--- a/arch/arm/mach-shmobile/clock-r7s72100.c
+++ b/arch/arm/mach-shmobile/clock-r7s72100.c
@@ -170,6 +170,9 @@ static struct clk_lookup lookups[] = {
170 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), 170 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
171 171
172 /* MSTP clocks */ 172 /* MSTP clocks */
173 CLKDEV_CON_ID("mtu2_fck", &mstp_clks[MSTP33]),
174
175 /* ICK */
173 CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP47]), 176 CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP47]),
174 CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[MSTP46]), 177 CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[MSTP46]),
175 CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[MSTP45]), 178 CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[MSTP45]),
@@ -178,6 +181,7 @@ static struct clk_lookup lookups[] = {
178 CLKDEV_ICK_ID("sci_fck", "sh-sci.5", &mstp_clks[MSTP42]), 181 CLKDEV_ICK_ID("sci_fck", "sh-sci.5", &mstp_clks[MSTP42]),
179 CLKDEV_ICK_ID("sci_fck", "sh-sci.6", &mstp_clks[MSTP41]), 182 CLKDEV_ICK_ID("sci_fck", "sh-sci.6", &mstp_clks[MSTP41]),
180 CLKDEV_ICK_ID("sci_fck", "sh-sci.7", &mstp_clks[MSTP40]), 183 CLKDEV_ICK_ID("sci_fck", "sh-sci.7", &mstp_clks[MSTP40]),
184 CLKDEV_CON_ID("mtu2_fck", &mstp_clks[MSTP33]),
181}; 185};
182 186
183void __init r7s72100_clock_init(void) 187void __init r7s72100_clock_init(void)
diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c
index 571409b611d3..7348d58f500e 100644
--- a/arch/arm/mach-shmobile/clock-r8a73a4.c
+++ b/arch/arm/mach-shmobile/clock-r8a73a4.c
@@ -584,15 +584,15 @@ static struct clk_lookup lookups[] = {
584 CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]), 584 CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
585 CLKDEV_DEV_ID("e6520000.i2c", &mstp_clks[MSTP300]), 585 CLKDEV_DEV_ID("e6520000.i2c", &mstp_clks[MSTP300]),
586 CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]), 586 CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
587 CLKDEV_DEV_ID("ee220000.mmcif", &mstp_clks[MSTP305]), 587 CLKDEV_DEV_ID("ee220000.mmc", &mstp_clks[MSTP305]),
588 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]), 588 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]),
589 CLKDEV_DEV_ID("ee140000.sdhi", &mstp_clks[MSTP312]), 589 CLKDEV_DEV_ID("ee140000.sd", &mstp_clks[MSTP312]),
590 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), 590 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]),
591 CLKDEV_DEV_ID("ee120000.sdhi", &mstp_clks[MSTP313]), 591 CLKDEV_DEV_ID("ee120000.sd", &mstp_clks[MSTP313]),
592 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), 592 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]),
593 CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]), 593 CLKDEV_DEV_ID("ee100000.sd", &mstp_clks[MSTP314]),
594 CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]), 594 CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]),
595 CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]), 595 CLKDEV_DEV_ID("ee200000.mmc", &mstp_clks[MSTP315]),
596 CLKDEV_DEV_ID("e6550000.i2c", &mstp_clks[MSTP316]), 596 CLKDEV_DEV_ID("e6550000.i2c", &mstp_clks[MSTP316]),
597 CLKDEV_DEV_ID("e6560000.i2c", &mstp_clks[MSTP317]), 597 CLKDEV_DEV_ID("e6560000.i2c", &mstp_clks[MSTP317]),
598 CLKDEV_DEV_ID("e6500000.i2c", &mstp_clks[MSTP318]), 598 CLKDEV_DEV_ID("e6500000.i2c", &mstp_clks[MSTP318]),
diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
index c826bca4024e..dd989f93498f 100644
--- a/arch/arm/mach-shmobile/clock-r8a7740.c
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -585,22 +585,23 @@ static struct clk_lookup lookups[] = {
585 585
586 CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), 586 CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]),
587 CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), 587 CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]),
588 CLKDEV_DEV_ID("fe1f0000.sound", &mstp_clks[MSTP328]),
588 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), 589 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]),
589 CLKDEV_DEV_ID("e6c20000.i2c", &mstp_clks[MSTP323]), 590 CLKDEV_DEV_ID("e6c20000.i2c", &mstp_clks[MSTP323]),
590 CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP320]), 591 CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP320]),
591 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), 592 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]),
592 CLKDEV_DEV_ID("e6850000.sdhi", &mstp_clks[MSTP314]), 593 CLKDEV_DEV_ID("e6850000.sd", &mstp_clks[MSTP314]),
593 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), 594 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]),
594 CLKDEV_DEV_ID("e6860000.sdhi", &mstp_clks[MSTP313]), 595 CLKDEV_DEV_ID("e6860000.sd", &mstp_clks[MSTP313]),
595 CLKDEV_DEV_ID("sh_mmcif", &mstp_clks[MSTP312]), 596 CLKDEV_DEV_ID("sh_mmcif", &mstp_clks[MSTP312]),
596 CLKDEV_DEV_ID("e6bd0000.mmcif", &mstp_clks[MSTP312]), 597 CLKDEV_DEV_ID("e6bd0000.mmc", &mstp_clks[MSTP312]),
597 CLKDEV_DEV_ID("r8a7740-gether", &mstp_clks[MSTP309]), 598 CLKDEV_DEV_ID("r8a7740-gether", &mstp_clks[MSTP309]),
598 CLKDEV_DEV_ID("e9a00000.sh-eth", &mstp_clks[MSTP309]), 599 CLKDEV_DEV_ID("e9a00000.sh-eth", &mstp_clks[MSTP309]),
599 CLKDEV_DEV_ID("renesas-tpu-pwm", &mstp_clks[MSTP304]), 600 CLKDEV_DEV_ID("renesas-tpu-pwm", &mstp_clks[MSTP304]),
600 CLKDEV_DEV_ID("e6600000.pwm", &mstp_clks[MSTP304]), 601 CLKDEV_DEV_ID("e6600000.pwm", &mstp_clks[MSTP304]),
601 602
602 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP415]), 603 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP415]),
603 CLKDEV_DEV_ID("e6870000.sdhi", &mstp_clks[MSTP415]), 604 CLKDEV_DEV_ID("e6870000.sd", &mstp_clks[MSTP415]),
604 605
605 /* ICK */ 606 /* ICK */
606 CLKDEV_ICK_ID("host", "renesas_usbhs", &mstp_clks[MSTP416]), 607 CLKDEV_ICK_ID("host", "renesas_usbhs", &mstp_clks[MSTP416]),
diff --git a/arch/arm/mach-shmobile/clock-r8a7778.c b/arch/arm/mach-shmobile/clock-r8a7778.c
index fb6af83858e3..4b601bf4ede4 100644
--- a/arch/arm/mach-shmobile/clock-r8a7778.c
+++ b/arch/arm/mach-shmobile/clock-r8a7778.c
@@ -173,9 +173,13 @@ static struct clk_lookup lookups[] = {
173 173
174 /* MSTP32 clocks */ 174 /* MSTP32 clocks */
175 CLKDEV_DEV_ID("sh_mmcif", &mstp_clks[MSTP331]), /* MMC */ 175 CLKDEV_DEV_ID("sh_mmcif", &mstp_clks[MSTP331]), /* MMC */
176 CLKDEV_DEV_ID("ffe4e000.mmc", &mstp_clks[MSTP331]), /* MMC */
176 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */ 177 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */
178 CLKDEV_DEV_ID("ffe4c000.sd", &mstp_clks[MSTP323]), /* SDHI0 */
177 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */ 179 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */
180 CLKDEV_DEV_ID("ffe4d000.sd", &mstp_clks[MSTP322]), /* SDHI1 */
178 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */ 181 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */
182 CLKDEV_DEV_ID("ffe4f000.sd", &mstp_clks[MSTP321]), /* SDHI2 */
179 CLKDEV_DEV_ID("r8a777x-ether", &mstp_clks[MSTP114]), /* Ether */ 183 CLKDEV_DEV_ID("r8a777x-ether", &mstp_clks[MSTP114]), /* Ether */
180 CLKDEV_DEV_ID("r8a7778-vin.0", &mstp_clks[MSTP110]), /* VIN0 */ 184 CLKDEV_DEV_ID("r8a7778-vin.0", &mstp_clks[MSTP110]), /* VIN0 */
181 CLKDEV_DEV_ID("r8a7778-vin.1", &mstp_clks[MSTP109]), /* VIN1 */ 185 CLKDEV_DEV_ID("r8a7778-vin.1", &mstp_clks[MSTP109]), /* VIN1 */
@@ -183,9 +187,13 @@ static struct clk_lookup lookups[] = {
183 CLKDEV_DEV_ID("ohci-platform", &mstp_clks[MSTP100]), /* USB OHCI port0/1 */ 187 CLKDEV_DEV_ID("ohci-platform", &mstp_clks[MSTP100]), /* USB OHCI port0/1 */
184 CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP100]), /* USB FUNC */ 188 CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP100]), /* USB FUNC */
185 CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP030]), /* I2C0 */ 189 CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP030]), /* I2C0 */
190 CLKDEV_DEV_ID("ffc70000.i2c", &mstp_clks[MSTP030]), /* I2C0 */
186 CLKDEV_DEV_ID("i2c-rcar.1", &mstp_clks[MSTP029]), /* I2C1 */ 191 CLKDEV_DEV_ID("i2c-rcar.1", &mstp_clks[MSTP029]), /* I2C1 */
192 CLKDEV_DEV_ID("ffc71000.i2c", &mstp_clks[MSTP029]), /* I2C1 */
187 CLKDEV_DEV_ID("i2c-rcar.2", &mstp_clks[MSTP028]), /* I2C2 */ 193 CLKDEV_DEV_ID("i2c-rcar.2", &mstp_clks[MSTP028]), /* I2C2 */
194 CLKDEV_DEV_ID("ffc72000.i2c", &mstp_clks[MSTP028]), /* I2C2 */
188 CLKDEV_DEV_ID("i2c-rcar.3", &mstp_clks[MSTP027]), /* I2C3 */ 195 CLKDEV_DEV_ID("i2c-rcar.3", &mstp_clks[MSTP027]), /* I2C3 */
196 CLKDEV_DEV_ID("ffc73000.i2c", &mstp_clks[MSTP027]), /* I2C3 */
189 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */ 197 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */
190 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */ 198 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */
191 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */ 199 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */
@@ -195,8 +203,11 @@ static struct clk_lookup lookups[] = {
195 CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP016]), /* TMU00 */ 203 CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP016]), /* TMU00 */
196 CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP015]), /* TMU01 */ 204 CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP015]), /* TMU01 */
197 CLKDEV_DEV_ID("sh-hspi.0", &mstp_clks[MSTP007]), /* HSPI0 */ 205 CLKDEV_DEV_ID("sh-hspi.0", &mstp_clks[MSTP007]), /* HSPI0 */
206 CLKDEV_DEV_ID("fffc7000.spi", &mstp_clks[MSTP007]), /* HSPI0 */
198 CLKDEV_DEV_ID("sh-hspi.1", &mstp_clks[MSTP007]), /* HSPI1 */ 207 CLKDEV_DEV_ID("sh-hspi.1", &mstp_clks[MSTP007]), /* HSPI1 */
208 CLKDEV_DEV_ID("fffc8000.spi", &mstp_clks[MSTP007]), /* HSPI1 */
199 CLKDEV_DEV_ID("sh-hspi.2", &mstp_clks[MSTP007]), /* HSPI2 */ 209 CLKDEV_DEV_ID("sh-hspi.2", &mstp_clks[MSTP007]), /* HSPI2 */
210 CLKDEV_DEV_ID("fffc6000.spi", &mstp_clks[MSTP007]), /* HSPI2 */
200 CLKDEV_DEV_ID("rcar_sound", &mstp_clks[MSTP008]), /* SRU */ 211 CLKDEV_DEV_ID("rcar_sound", &mstp_clks[MSTP008]), /* SRU */
201 212
202 CLKDEV_ICK_ID("ssi.0", "rcar_sound", &mstp_clks[MSTP012]), 213 CLKDEV_ICK_ID("ssi.0", "rcar_sound", &mstp_clks[MSTP012]),
diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
index 1f7080fab0a5..f1fb89b76786 100644
--- a/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -184,9 +184,13 @@ static struct clk_lookup lookups[] = {
184 CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP016]), /* TMU01 */ 184 CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP016]), /* TMU01 */
185 CLKDEV_DEV_ID("sh_tmu.2", &mstp_clks[MSTP016]), /* TMU02 */ 185 CLKDEV_DEV_ID("sh_tmu.2", &mstp_clks[MSTP016]), /* TMU02 */
186 CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP030]), /* I2C0 */ 186 CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP030]), /* I2C0 */
187 CLKDEV_DEV_ID("ffc70000.i2c", &mstp_clks[MSTP030]), /* I2C0 */
187 CLKDEV_DEV_ID("i2c-rcar.1", &mstp_clks[MSTP029]), /* I2C1 */ 188 CLKDEV_DEV_ID("i2c-rcar.1", &mstp_clks[MSTP029]), /* I2C1 */
189 CLKDEV_DEV_ID("ffc71000.i2c", &mstp_clks[MSTP029]), /* I2C1 */
188 CLKDEV_DEV_ID("i2c-rcar.2", &mstp_clks[MSTP028]), /* I2C2 */ 190 CLKDEV_DEV_ID("i2c-rcar.2", &mstp_clks[MSTP028]), /* I2C2 */
191 CLKDEV_DEV_ID("ffc72000.i2c", &mstp_clks[MSTP028]), /* I2C2 */
189 CLKDEV_DEV_ID("i2c-rcar.3", &mstp_clks[MSTP027]), /* I2C3 */ 192 CLKDEV_DEV_ID("i2c-rcar.3", &mstp_clks[MSTP027]), /* I2C3 */
193 CLKDEV_DEV_ID("ffc73000.i2c", &mstp_clks[MSTP027]), /* I2C3 */
190 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */ 194 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */
191 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */ 195 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */
192 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */ 196 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */
@@ -194,12 +198,19 @@ static struct clk_lookup lookups[] = {
194 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */ 198 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */
195 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */ 199 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */
196 CLKDEV_DEV_ID("sh-hspi.0", &mstp_clks[MSTP007]), /* HSPI0 */ 200 CLKDEV_DEV_ID("sh-hspi.0", &mstp_clks[MSTP007]), /* HSPI0 */
201 CLKDEV_DEV_ID("fffc7000.spi", &mstp_clks[MSTP007]), /* HSPI0 */
197 CLKDEV_DEV_ID("sh-hspi.1", &mstp_clks[MSTP007]), /* HSPI1 */ 202 CLKDEV_DEV_ID("sh-hspi.1", &mstp_clks[MSTP007]), /* HSPI1 */
203 CLKDEV_DEV_ID("fffc8000.spi", &mstp_clks[MSTP007]), /* HSPI1 */
198 CLKDEV_DEV_ID("sh-hspi.2", &mstp_clks[MSTP007]), /* HSPI2 */ 204 CLKDEV_DEV_ID("sh-hspi.2", &mstp_clks[MSTP007]), /* HSPI2 */
205 CLKDEV_DEV_ID("fffc6000.spi", &mstp_clks[MSTP007]), /* HSPI2 */
199 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */ 206 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */
207 CLKDEV_DEV_ID("ffe4c000.sd", &mstp_clks[MSTP323]), /* SDHI0 */
200 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */ 208 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */
209 CLKDEV_DEV_ID("ffe4d000.sd", &mstp_clks[MSTP322]), /* SDHI1 */
201 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */ 210 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */
211 CLKDEV_DEV_ID("ffe4e000.sd", &mstp_clks[MSTP321]), /* SDHI2 */
202 CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP320]), /* SDHI3 */ 212 CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP320]), /* SDHI3 */
213 CLKDEV_DEV_ID("ffe4f000.sd", &mstp_clks[MSTP320]), /* SDHI3 */
203 CLKDEV_DEV_ID("rcar-du-r8a7779", &mstp_clks[MSTP103]), /* DU */ 214 CLKDEV_DEV_ID("rcar-du-r8a7779", &mstp_clks[MSTP103]), /* DU */
204}; 215};
205 216
diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
index a64f965c7da1..312376d2cfd1 100644
--- a/arch/arm/mach-shmobile/clock-r8a7790.c
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -53,6 +53,7 @@
53#define SMSTPCR7 0xe615014c 53#define SMSTPCR7 0xe615014c
54#define SMSTPCR8 0xe6150990 54#define SMSTPCR8 0xe6150990
55#define SMSTPCR9 0xe6150994 55#define SMSTPCR9 0xe6150994
56#define SMSTPCR10 0xe6150998
56 57
57#define SDCKCR 0xE6150074 58#define SDCKCR 0xE6150074
58#define SD2CKCR 0xE6150078 59#define SD2CKCR 0xE6150078
@@ -77,7 +78,7 @@ static struct sh_clk_ops followparent_clk_ops = {
77}; 78};
78 79
79static struct clk main_clk = { 80static struct clk main_clk = {
80 /* .parent will be set r8a73a4_clock_init */ 81 /* .parent will be set r8a7790_clock_init */
81 .ops = &followparent_clk_ops, 82 .ops = &followparent_clk_ops,
82}; 83};
83 84
@@ -182,10 +183,14 @@ static struct clk div6_clks[DIV6_NR] = {
182 183
183/* MSTP */ 184/* MSTP */
184enum { 185enum {
186 MSTP1015, MSTP1014, MSTP1013, MSTP1012, MSTP1011, MSTP1010,
187 MSTP1009, MSTP1008, MSTP1007, MSTP1006, MSTP1005,
185 MSTP931, MSTP930, MSTP929, MSTP928, 188 MSTP931, MSTP930, MSTP929, MSTP928,
189 MSTP917,
186 MSTP813, 190 MSTP813,
187 MSTP726, MSTP725, MSTP724, MSTP723, MSTP722, MSTP721, MSTP720, 191 MSTP726, MSTP725, MSTP724, MSTP723, MSTP722, MSTP721, MSTP720,
188 MSTP717, MSTP716, 192 MSTP717, MSTP716,
193 MSTP704,
189 MSTP522, 194 MSTP522,
190 MSTP315, MSTP314, MSTP313, MSTP312, MSTP311, MSTP305, MSTP304, 195 MSTP315, MSTP314, MSTP313, MSTP312, MSTP311, MSTP305, MSTP304,
191 MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, 196 MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202,
@@ -194,10 +199,22 @@ enum {
194}; 199};
195 200
196static struct clk mstp_clks[MSTP_NR] = { 201static struct clk mstp_clks[MSTP_NR] = {
197 [MSTP931] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 31, 0), /* I2C0 */ 202 [MSTP1015] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 15, 0), /* SSI0 */
198 [MSTP930] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 30, 0), /* I2C1 */ 203 [MSTP1014] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 14, 0), /* SSI1 */
199 [MSTP929] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 29, 0), /* I2C2 */ 204 [MSTP1013] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 13, 0), /* SSI2 */
200 [MSTP928] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 28, 0), /* I2C3 */ 205 [MSTP1012] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 12, 0), /* SSI3 */
206 [MSTP1011] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 11, 0), /* SSI4 */
207 [MSTP1010] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 10, 0), /* SSI5 */
208 [MSTP1009] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 9, 0), /* SSI6 */
209 [MSTP1008] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 8, 0), /* SSI7 */
210 [MSTP1007] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 7, 0), /* SSI8 */
211 [MSTP1006] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 6, 0), /* SSI9 */
212 [MSTP1005] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 5, 0), /* SSI ALL */
213 [MSTP931] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 31, 0), /* I2C0 */
214 [MSTP930] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 30, 0), /* I2C1 */
215 [MSTP929] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 29, 0), /* I2C2 */
216 [MSTP928] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 28, 0), /* I2C3 */
217 [MSTP917] = SH_CLK_MSTP32(&qspi_clk, SMSTPCR9, 17, 0), /* QSPI */
201 [MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */ 218 [MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */
202 [MSTP726] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 26, 0), /* LVDS0 */ 219 [MSTP726] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 26, 0), /* LVDS0 */
203 [MSTP725] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 25, 0), /* LVDS1 */ 220 [MSTP725] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 25, 0), /* LVDS1 */
@@ -208,6 +225,7 @@ static struct clk mstp_clks[MSTP_NR] = {
208 [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */ 225 [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
209 [MSTP717] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 17, 0), /* HSCIF0 */ 226 [MSTP717] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 17, 0), /* HSCIF0 */
210 [MSTP716] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 16, 0), /* HSCIF1 */ 227 [MSTP716] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 16, 0), /* HSCIF1 */
228 [MSTP704] = SH_CLK_MSTP32(&mp_clk, SMSTPCR7, 4, 0), /* HSUSB */
211 [MSTP522] = SH_CLK_MSTP32(&extal_clk, SMSTPCR5, 22, 0), /* Thermal */ 229 [MSTP522] = SH_CLK_MSTP32(&extal_clk, SMSTPCR5, 22, 0), /* Thermal */
212 [MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0], SMSTPCR3, 15, 0), /* MMC0 */ 230 [MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0], SMSTPCR3, 15, 0), /* MMC0 */
213 [MSTP314] = SH_CLK_MSTP32(&div4_clks[DIV4_SD0], SMSTPCR3, 14, 0), /* SDHI0 */ 231 [MSTP314] = SH_CLK_MSTP32(&div4_clks[DIV4_SD0], SMSTPCR3, 14, 0), /* SDHI0 */
@@ -262,11 +280,7 @@ static struct clk_lookup lookups[] = {
262 CLKDEV_CON_ID("ssprs", &div6_clks[DIV6_SSPRS]), 280 CLKDEV_CON_ID("ssprs", &div6_clks[DIV6_SSPRS]),
263 281
264 /* MSTP */ 282 /* MSTP */
265 CLKDEV_ICK_ID("lvds.0", "rcar-du-r8a7790", &mstp_clks[MSTP726]), 283 CLKDEV_DEV_ID("rcar_sound", &mstp_clks[MSTP1005]),
266 CLKDEV_ICK_ID("lvds.1", "rcar-du-r8a7790", &mstp_clks[MSTP725]),
267 CLKDEV_ICK_ID("du.0", "rcar-du-r8a7790", &mstp_clks[MSTP724]),
268 CLKDEV_ICK_ID("du.1", "rcar-du-r8a7790", &mstp_clks[MSTP723]),
269 CLKDEV_ICK_ID("du.2", "rcar-du-r8a7790", &mstp_clks[MSTP722]),
270 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), 284 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
271 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), 285 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
272 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]), 286 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
@@ -282,20 +296,42 @@ static struct clk_lookup lookups[] = {
282 CLKDEV_DEV_ID("e6530000.i2c", &mstp_clks[MSTP929]), 296 CLKDEV_DEV_ID("e6530000.i2c", &mstp_clks[MSTP929]),
283 CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP928]), 297 CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP928]),
284 CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]), 298 CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]),
299 CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
285 CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]), 300 CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
286 CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]), 301 CLKDEV_DEV_ID("ee200000.mmc", &mstp_clks[MSTP315]),
287 CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]), 302 CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]),
288 CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]), 303 CLKDEV_DEV_ID("ee100000.sd", &mstp_clks[MSTP314]),
289 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), 304 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]),
290 CLKDEV_DEV_ID("ee120000.sdhi", &mstp_clks[MSTP313]), 305 CLKDEV_DEV_ID("ee120000.sd", &mstp_clks[MSTP313]),
291 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), 306 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]),
292 CLKDEV_DEV_ID("ee140000.sdhi", &mstp_clks[MSTP312]), 307 CLKDEV_DEV_ID("ee140000.sd", &mstp_clks[MSTP312]),
293 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]), 308 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]),
294 CLKDEV_DEV_ID("ee160000.sdhi", &mstp_clks[MSTP311]), 309 CLKDEV_DEV_ID("ee160000.sd", &mstp_clks[MSTP311]),
295 CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP311]), 310 CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP311]),
296 CLKDEV_DEV_ID("ee220000.mmcif", &mstp_clks[MSTP305]), 311 CLKDEV_DEV_ID("ee220000.mmc", &mstp_clks[MSTP305]),
297 CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]), 312 CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
298 CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]), 313 CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]),
314 CLKDEV_DEV_ID("qspi.0", &mstp_clks[MSTP917]),
315 CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP704]),
316
317 /* ICK */
318 CLKDEV_ICK_ID("usbhs", "usb_phy_rcar_gen2", &mstp_clks[MSTP704]),
319 CLKDEV_ICK_ID("lvds.0", "rcar-du-r8a7790", &mstp_clks[MSTP726]),
320 CLKDEV_ICK_ID("lvds.1", "rcar-du-r8a7790", &mstp_clks[MSTP725]),
321 CLKDEV_ICK_ID("du.0", "rcar-du-r8a7790", &mstp_clks[MSTP724]),
322 CLKDEV_ICK_ID("du.1", "rcar-du-r8a7790", &mstp_clks[MSTP723]),
323 CLKDEV_ICK_ID("du.2", "rcar-du-r8a7790", &mstp_clks[MSTP722]),
324 CLKDEV_ICK_ID("ssi.0", "rcar_sound", &mstp_clks[MSTP1015]),
325 CLKDEV_ICK_ID("ssi.1", "rcar_sound", &mstp_clks[MSTP1014]),
326 CLKDEV_ICK_ID("ssi.2", "rcar_sound", &mstp_clks[MSTP1013]),
327 CLKDEV_ICK_ID("ssi.3", "rcar_sound", &mstp_clks[MSTP1012]),
328 CLKDEV_ICK_ID("ssi.4", "rcar_sound", &mstp_clks[MSTP1011]),
329 CLKDEV_ICK_ID("ssi.5", "rcar_sound", &mstp_clks[MSTP1010]),
330 CLKDEV_ICK_ID("ssi.6", "rcar_sound", &mstp_clks[MSTP1009]),
331 CLKDEV_ICK_ID("ssi.7", "rcar_sound", &mstp_clks[MSTP1008]),
332 CLKDEV_ICK_ID("ssi.8", "rcar_sound", &mstp_clks[MSTP1007]),
333 CLKDEV_ICK_ID("ssi.9", "rcar_sound", &mstp_clks[MSTP1006]),
334
299}; 335};
300 336
301#define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31) \ 337#define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31) \
@@ -321,10 +357,10 @@ void __init r8a7790_clock_init(void)
321 R8A7790_CLOCK_ROOT(20, &extal_clk, 130, 156, 80, 66); 357 R8A7790_CLOCK_ROOT(20, &extal_clk, 130, 156, 80, 66);
322 break; 358 break;
323 case MD(14): 359 case MD(14):
324 R8A7790_CLOCK_ROOT(26, &extal_div2_clk, 200, 240, 122, 102); 360 R8A7790_CLOCK_ROOT(26 / 2, &extal_div2_clk, 200, 240, 122, 102);
325 break; 361 break;
326 case MD(13) | MD(14): 362 case MD(13) | MD(14):
327 R8A7790_CLOCK_ROOT(30, &extal_div2_clk, 172, 208, 106, 88); 363 R8A7790_CLOCK_ROOT(30 / 2, &extal_div2_clk, 172, 208, 106, 88);
328 break; 364 break;
329 } 365 }
330 366
diff --git a/arch/arm/mach-shmobile/clock-r8a7791.c b/arch/arm/mach-shmobile/clock-r8a7791.c
index c9a26f16ce5b..ff2d60d55bd5 100644
--- a/arch/arm/mach-shmobile/clock-r8a7791.c
+++ b/arch/arm/mach-shmobile/clock-r8a7791.c
@@ -103,6 +103,7 @@ SH_FIXED_RATIO_CLK_SET(hp_clk, pll1_clk, 1, 12);
103SH_FIXED_RATIO_CLK_SET(p_clk, pll1_clk, 1, 24); 103SH_FIXED_RATIO_CLK_SET(p_clk, pll1_clk, 1, 24);
104SH_FIXED_RATIO_CLK_SET(rclk_clk, pll1_clk, 1, (48 * 1024)); 104SH_FIXED_RATIO_CLK_SET(rclk_clk, pll1_clk, 1, (48 * 1024));
105SH_FIXED_RATIO_CLK_SET(mp_clk, pll1_div2_clk, 1, 15); 105SH_FIXED_RATIO_CLK_SET(mp_clk, pll1_div2_clk, 1, 15);
106SH_FIXED_RATIO_CLK_SET(zx_clk, pll1_clk, 1, 3);
106 107
107static struct clk *main_clks[] = { 108static struct clk *main_clks[] = {
108 &extal_clk, 109 &extal_clk,
@@ -116,12 +117,14 @@ static struct clk *main_clks[] = {
116 &rclk_clk, 117 &rclk_clk,
117 &mp_clk, 118 &mp_clk,
118 &cp_clk, 119 &cp_clk,
120 &zx_clk,
119}; 121};
120 122
121/* MSTP */ 123/* MSTP */
122enum { 124enum {
123 MSTP721, MSTP720, 125 MSTP726, MSTP724, MSTP723, MSTP721, MSTP720,
124 MSTP719, MSTP718, MSTP715, MSTP714, 126 MSTP719, MSTP718, MSTP715, MSTP714,
127 MSTP522,
125 MSTP216, MSTP207, MSTP206, 128 MSTP216, MSTP207, MSTP206,
126 MSTP204, MSTP203, MSTP202, MSTP1105, MSTP1106, MSTP1107, 129 MSTP204, MSTP203, MSTP202, MSTP1105, MSTP1106, MSTP1107,
127 MSTP124, 130 MSTP124,
@@ -129,12 +132,16 @@ enum {
129}; 132};
130 133
131static struct clk mstp_clks[MSTP_NR] = { 134static struct clk mstp_clks[MSTP_NR] = {
135 [MSTP726] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 26, 0), /* LVDS0 */
136 [MSTP724] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 24, 0), /* DU0 */
137 [MSTP723] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 23, 0), /* DU1 */
132 [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */ 138 [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */
133 [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */ 139 [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
134 [MSTP719] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 19, 0), /* SCIF2 */ 140 [MSTP719] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 19, 0), /* SCIF2 */
135 [MSTP718] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 18, 0), /* SCIF3 */ 141 [MSTP718] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 18, 0), /* SCIF3 */
136 [MSTP715] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 15, 0), /* SCIF4 */ 142 [MSTP715] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 15, 0), /* SCIF4 */
137 [MSTP714] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 14, 0), /* SCIF5 */ 143 [MSTP714] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 14, 0), /* SCIF5 */
144 [MSTP522] = SH_CLK_MSTP32(&extal_clk, SMSTPCR5, 22, 0), /* Thermal */
138 [MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */ 145 [MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */
139 [MSTP207] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 7, 0), /* SCIFB1 */ 146 [MSTP207] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 7, 0), /* SCIFB1 */
140 [MSTP206] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 6, 0), /* SCIFB0 */ 147 [MSTP206] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 6, 0), /* SCIFB0 */
@@ -164,6 +171,9 @@ static struct clk_lookup lookups[] = {
164 CLKDEV_CON_ID("peripheral_clk", &hp_clk), 171 CLKDEV_CON_ID("peripheral_clk", &hp_clk),
165 172
166 /* MSTP */ 173 /* MSTP */
174 CLKDEV_ICK_ID("lvds.0", "rcar-du-r8a7791", &mstp_clks[MSTP726]),
175 CLKDEV_ICK_ID("du.0", "rcar-du-r8a7791", &mstp_clks[MSTP724]),
176 CLKDEV_ICK_ID("du.1", "rcar-du-r8a7791", &mstp_clks[MSTP723]),
167 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */ 177 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
168 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */ 178 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */
169 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]), /* SCIFB0 */ 179 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]), /* SCIFB0 */
@@ -180,6 +190,8 @@ static struct clk_lookup lookups[] = {
180 CLKDEV_DEV_ID("sh-sci.13", &mstp_clks[MSTP1106]), /* SCIFA4 */ 190 CLKDEV_DEV_ID("sh-sci.13", &mstp_clks[MSTP1106]), /* SCIFA4 */
181 CLKDEV_DEV_ID("sh-sci.14", &mstp_clks[MSTP1107]), /* SCIFA5 */ 191 CLKDEV_DEV_ID("sh-sci.14", &mstp_clks[MSTP1107]), /* SCIFA5 */
182 CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]), 192 CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]),
193 CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
194 CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
183}; 195};
184 196
185#define R8A7791_CLOCK_ROOT(e, m, p0, p1, p30, p31) \ 197#define R8A7791_CLOCK_ROOT(e, m, p0, p1, p30, p31) \
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c
index 5390c6bbbc02..28489978b09c 100644
--- a/arch/arm/mach-shmobile/clock-sh7372.c
+++ b/arch/arm/mach-shmobile/clock-sh7372.c
@@ -504,10 +504,6 @@ static struct clk_lookup lookups[] = {
504 CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_SPU]), 504 CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_SPU]),
505 CLKDEV_CON_ID("vou_clk", &div6_clks[DIV6_VOU]), 505 CLKDEV_CON_ID("vou_clk", &div6_clks[DIV6_VOU]),
506 CLKDEV_CON_ID("hdmi_clk", &div6_reparent_clks[DIV6_HDMI]), 506 CLKDEV_CON_ID("hdmi_clk", &div6_reparent_clks[DIV6_HDMI]),
507 CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSIT]),
508 CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSIT]),
509 CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSI0P]),
510 CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSI1P]),
511 507
512 /* MSTP32 clocks */ 508 /* MSTP32 clocks */
513 CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* IIC2 */ 509 CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* IIC2 */
@@ -574,6 +570,11 @@ static struct clk_lookup lookups[] = {
574 CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */ 570 CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
575 CLKDEV_DEV_ID("sh_cmt.2", &mstp_clks[MSTP400]), /* CMT2 */ 571 CLKDEV_DEV_ID("sh_cmt.2", &mstp_clks[MSTP400]), /* CMT2 */
576 572
573 /* ICK */
574 CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSIT]),
575 CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSIT]),
576 CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSI0P]),
577 CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSI1P]),
577 CLKDEV_ICK_ID("hdmi", "sh_mobile_lcdc_fb.1", 578 CLKDEV_ICK_ID("hdmi", "sh_mobile_lcdc_fb.1",
578 &div6_reparent_clks[DIV6_HDMI]), 579 &div6_reparent_clks[DIV6_HDMI]),
579 CLKDEV_ICK_ID("ick", "sh-mobile-hdmi", &div6_reparent_clks[DIV6_HDMI]), 580 CLKDEV_ICK_ID("ick", "sh-mobile-hdmi", &div6_reparent_clks[DIV6_HDMI]),
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index c92c023f0d27..30d88689a960 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -625,12 +625,6 @@ static struct clk_lookup lookups[] = {
625 CLKDEV_CON_ID("sdhi0_clk", &div6_clks[DIV6_SDHI0]), 625 CLKDEV_CON_ID("sdhi0_clk", &div6_clks[DIV6_SDHI0]),
626 CLKDEV_CON_ID("sdhi1_clk", &div6_clks[DIV6_SDHI1]), 626 CLKDEV_CON_ID("sdhi1_clk", &div6_clks[DIV6_SDHI1]),
627 CLKDEV_CON_ID("sdhi2_clk", &div6_clks[DIV6_SDHI2]), 627 CLKDEV_CON_ID("sdhi2_clk", &div6_clks[DIV6_SDHI2]),
628 CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSIT]),
629 CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSIT]),
630 CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSI0P]),
631 CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSI1P]),
632 CLKDEV_ICK_ID("dsiphy_clk", "sh-mipi-dsi.0", &dsi0phy_clk),
633 CLKDEV_ICK_ID("dsiphy_clk", "sh-mipi-dsi.1", &dsi1phy_clk),
634 628
635 /* MSTP32 clocks */ 629 /* MSTP32 clocks */
636 CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* I2C2 */ 630 CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* I2C2 */
@@ -663,13 +657,13 @@ static struct clk_lookup lookups[] = {
663 CLKDEV_DEV_ID("e6822000.i2c", &mstp_clks[MSTP323]), /* I2C1 */ 657 CLKDEV_DEV_ID("e6822000.i2c", &mstp_clks[MSTP323]), /* I2C1 */
664 CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP322]), /* USB */ 658 CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP322]), /* USB */
665 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */ 659 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */
666 CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]), /* SDHI0 */ 660 CLKDEV_DEV_ID("ee100000.sd", &mstp_clks[MSTP314]), /* SDHI0 */
667 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */ 661 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
668 CLKDEV_DEV_ID("ee120000.sdhi", &mstp_clks[MSTP313]), /* SDHI1 */ 662 CLKDEV_DEV_ID("ee120000.sd", &mstp_clks[MSTP313]), /* SDHI1 */
669 CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMCIF0 */ 663 CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMCIF0 */
670 CLKDEV_DEV_ID("e6bd0000.mmcif", &mstp_clks[MSTP312]), /* MMCIF0 */ 664 CLKDEV_DEV_ID("e6bd0000.mmc", &mstp_clks[MSTP312]), /* MMCIF0 */
671 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP311]), /* SDHI2 */ 665 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP311]), /* SDHI2 */
672 CLKDEV_DEV_ID("ee140000.sdhi", &mstp_clks[MSTP311]), /* SDHI2 */ 666 CLKDEV_DEV_ID("ee140000.sd", &mstp_clks[MSTP311]), /* SDHI2 */
673 CLKDEV_DEV_ID("renesas-tpu-pwm.0", &mstp_clks[MSTP304]), /* TPU0 */ 667 CLKDEV_DEV_ID("renesas-tpu-pwm.0", &mstp_clks[MSTP304]), /* TPU0 */
674 CLKDEV_DEV_ID("renesas-tpu-pwm.1", &mstp_clks[MSTP303]), /* TPU1 */ 668 CLKDEV_DEV_ID("renesas-tpu-pwm.1", &mstp_clks[MSTP303]), /* TPU1 */
675 CLKDEV_DEV_ID("renesas-tpu-pwm.2", &mstp_clks[MSTP302]), /* TPU2 */ 669 CLKDEV_DEV_ID("renesas-tpu-pwm.2", &mstp_clks[MSTP302]), /* TPU2 */
@@ -680,6 +674,14 @@ static struct clk_lookup lookups[] = {
680 CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* I2C4 */ 674 CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* I2C4 */
681 CLKDEV_DEV_ID("e6828000.i2c", &mstp_clks[MSTP410]), /* I2C4 */ 675 CLKDEV_DEV_ID("e6828000.i2c", &mstp_clks[MSTP410]), /* I2C4 */
682 CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */ 676 CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
677
678 /* ICK */
679 CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSIT]),
680 CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSIT]),
681 CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSI0P]),
682 CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSI1P]),
683 CLKDEV_ICK_ID("dsiphy_clk", "sh-mipi-dsi.0", &dsi0phy_clk),
684 CLKDEV_ICK_ID("dsiphy_clk", "sh-mipi-dsi.1", &dsi1phy_clk),
683}; 685};
684 686
685void __init sh73a0_clock_init(void) 687void __init sh73a0_clock_init(void)
diff --git a/arch/arm/mach-shmobile/include/mach/emev2.h b/arch/arm/mach-shmobile/include/mach/emev2.h
index c2eb7568d9be..fcb142a14e07 100644
--- a/arch/arm/mach-shmobile/include/mach/emev2.h
+++ b/arch/arm/mach-shmobile/include/mach/emev2.h
@@ -3,12 +3,7 @@
3 3
4extern void emev2_map_io(void); 4extern void emev2_map_io(void);
5extern void emev2_init_delay(void); 5extern void emev2_init_delay(void);
6extern void emev2_add_standard_devices(void);
7extern void emev2_clock_init(void); 6extern void emev2_clock_init(void);
8
9#define EMEV2_GPIO_BASE 200
10#define EMEV2_GPIO_IRQ(n) (EMEV2_GPIO_BASE + (n))
11
12extern struct smp_operations emev2_smp_ops; 7extern struct smp_operations emev2_smp_ops;
13 8
14#endif /* __ASM_EMEV2_H__ */ 9#endif /* __ASM_EMEV2_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7778.h b/arch/arm/mach-shmobile/include/mach/r8a7778.h
index 441886c9714b..b497f932d04f 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7778.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7778.h
@@ -27,6 +27,24 @@ enum {
27 HPBDMA_SLAVE_DUMMY, 27 HPBDMA_SLAVE_DUMMY,
28 HPBDMA_SLAVE_SDHI0_TX, 28 HPBDMA_SLAVE_SDHI0_TX,
29 HPBDMA_SLAVE_SDHI0_RX, 29 HPBDMA_SLAVE_SDHI0_RX,
30 HPBDMA_SLAVE_HPBIF0_TX,
31 HPBDMA_SLAVE_HPBIF0_RX,
32 HPBDMA_SLAVE_HPBIF1_TX,
33 HPBDMA_SLAVE_HPBIF1_RX,
34 HPBDMA_SLAVE_HPBIF2_TX,
35 HPBDMA_SLAVE_HPBIF2_RX,
36 HPBDMA_SLAVE_HPBIF3_TX,
37 HPBDMA_SLAVE_HPBIF3_RX,
38 HPBDMA_SLAVE_HPBIF4_TX,
39 HPBDMA_SLAVE_HPBIF4_RX,
40 HPBDMA_SLAVE_HPBIF5_TX,
41 HPBDMA_SLAVE_HPBIF5_RX,
42 HPBDMA_SLAVE_HPBIF6_TX,
43 HPBDMA_SLAVE_HPBIF6_RX,
44 HPBDMA_SLAVE_HPBIF7_TX,
45 HPBDMA_SLAVE_HPBIF7_RX,
46 HPBDMA_SLAVE_HPBIF8_TX,
47 HPBDMA_SLAVE_HPBIF8_RX,
30}; 48};
31 49
32extern void r8a7778_add_standard_devices(void); 50extern void r8a7778_add_standard_devices(void);
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h
index 17af34ed89c8..5014145f272e 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7779.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h
@@ -3,8 +3,6 @@
3 3
4#include <linux/sh_clk.h> 4#include <linux/sh_clk.h>
5#include <linux/pm_domain.h> 5#include <linux/pm_domain.h>
6#include <linux/sh_eth.h>
7#include <linux/platform_data/camera-rcar.h>
8 6
9/* HPB-DMA slave IDs */ 7/* HPB-DMA slave IDs */
10enum { 8enum {
@@ -40,9 +38,6 @@ extern void r8a7779_earlytimer_init(void);
40extern void r8a7779_add_early_devices(void); 38extern void r8a7779_add_early_devices(void);
41extern void r8a7779_add_standard_devices(void); 39extern void r8a7779_add_standard_devices(void);
42extern void r8a7779_add_standard_devices_dt(void); 40extern void r8a7779_add_standard_devices_dt(void);
43extern void r8a7779_add_ether_device(struct sh_eth_plat_data *pdata);
44extern void r8a7779_add_vin_device(int idx,
45 struct rcar_vin_platform_data *pdata);
46extern void r8a7779_init_late(void); 41extern void r8a7779_init_late(void);
47extern void r8a7779_clock_init(void); 42extern void r8a7779_clock_init(void);
48extern void r8a7779_pinmux_init(void); 43extern void r8a7779_pinmux_init(void);
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7791.h b/arch/arm/mach-shmobile/include/mach/r8a7791.h
index 051ead3c286e..200fa699f730 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7791.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7791.h
@@ -4,6 +4,7 @@
4void r8a7791_add_standard_devices(void); 4void r8a7791_add_standard_devices(void);
5void r8a7791_add_dt_devices(void); 5void r8a7791_add_dt_devices(void);
6void r8a7791_clock_init(void); 6void r8a7791_clock_init(void);
7void r8a7791_pinmux_init(void);
7void r8a7791_init_early(void); 8void r8a7791_init_early(void);
8extern struct smp_operations r8a7791_smp_ops; 9extern struct smp_operations r8a7791_smp_ops;
9 10
diff --git a/arch/arm/mach-shmobile/setup-emev2.c b/arch/arm/mach-shmobile/setup-emev2.c
index 3ad531caf4f0..c8f2a1a69a52 100644
--- a/arch/arm/mach-shmobile/setup-emev2.c
+++ b/arch/arm/mach-shmobile/setup-emev2.c
@@ -16,24 +16,15 @@
16 * along with this program; if not, write to the Free Software 16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */ 18 */
19#include <linux/clk-provider.h>
19#include <linux/kernel.h> 20#include <linux/kernel.h>
20#include <linux/init.h> 21#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/platform_device.h>
24#include <linux/platform_data/gpio-em.h>
25#include <linux/of_platform.h> 22#include <linux/of_platform.h>
26#include <linux/delay.h>
27#include <linux/input.h>
28#include <linux/io.h>
29#include <linux/irqchip/arm-gic.h>
30#include <mach/common.h> 23#include <mach/common.h>
31#include <mach/emev2.h> 24#include <mach/emev2.h>
32#include <mach/irqs.h>
33#include <asm/mach-types.h> 25#include <asm/mach-types.h>
34#include <asm/mach/arch.h> 26#include <asm/mach/arch.h>
35#include <asm/mach/map.h> 27#include <asm/mach/map.h>
36#include <asm/mach/time.h>
37 28
38static struct map_desc emev2_io_desc[] __initdata = { 29static struct map_desc emev2_io_desc[] __initdata = {
39#ifdef CONFIG_SMP 30#ifdef CONFIG_SMP
@@ -52,150 +43,20 @@ void __init emev2_map_io(void)
52 iotable_init(emev2_io_desc, ARRAY_SIZE(emev2_io_desc)); 43 iotable_init(emev2_io_desc, ARRAY_SIZE(emev2_io_desc));
53} 44}
54 45
55/* UART */
56static struct resource uart0_resources[] = {
57 DEFINE_RES_MEM(0xe1020000, 0x38),
58 DEFINE_RES_IRQ(40),
59};
60
61static struct resource uart1_resources[] = {
62 DEFINE_RES_MEM(0xe1030000, 0x38),
63 DEFINE_RES_IRQ(41),
64};
65
66static struct resource uart2_resources[] = {
67 DEFINE_RES_MEM(0xe1040000, 0x38),
68 DEFINE_RES_IRQ(42),
69};
70
71static struct resource uart3_resources[] = {
72 DEFINE_RES_MEM(0xe1050000, 0x38),
73 DEFINE_RES_IRQ(43),
74};
75
76#define emev2_register_uart(idx) \
77 platform_device_register_simple("serial8250-em", idx, \
78 uart##idx##_resources, \
79 ARRAY_SIZE(uart##idx##_resources))
80
81/* STI */
82static struct resource sti_resources[] = {
83 DEFINE_RES_MEM(0xe0180000, 0x54),
84 DEFINE_RES_IRQ(157),
85};
86
87#define emev2_register_sti() \
88 platform_device_register_simple("em_sti", 0, \
89 sti_resources, \
90 ARRAY_SIZE(sti_resources))
91
92/* GIO */
93static struct gpio_em_config gio0_config = {
94 .gpio_base = 0,
95 .irq_base = EMEV2_GPIO_IRQ(0),
96 .number_of_pins = 32,
97};
98
99static struct resource gio0_resources[] = {
100 DEFINE_RES_MEM(0xe0050000, 0x2c),
101 DEFINE_RES_MEM(0xe0050040, 0x20),
102 DEFINE_RES_IRQ(99),
103 DEFINE_RES_IRQ(100),
104};
105
106static struct gpio_em_config gio1_config = {
107 .gpio_base = 32,
108 .irq_base = EMEV2_GPIO_IRQ(32),
109 .number_of_pins = 32,
110};
111
112static struct resource gio1_resources[] = {
113 DEFINE_RES_MEM(0xe0050080, 0x2c),
114 DEFINE_RES_MEM(0xe00500c0, 0x20),
115 DEFINE_RES_IRQ(101),
116 DEFINE_RES_IRQ(102),
117};
118
119static struct gpio_em_config gio2_config = {
120 .gpio_base = 64,
121 .irq_base = EMEV2_GPIO_IRQ(64),
122 .number_of_pins = 32,
123};
124
125static struct resource gio2_resources[] = {
126 DEFINE_RES_MEM(0xe0050100, 0x2c),
127 DEFINE_RES_MEM(0xe0050140, 0x20),
128 DEFINE_RES_IRQ(103),
129 DEFINE_RES_IRQ(104),
130};
131
132static struct gpio_em_config gio3_config = {
133 .gpio_base = 96,
134 .irq_base = EMEV2_GPIO_IRQ(96),
135 .number_of_pins = 32,
136};
137
138static struct resource gio3_resources[] = {
139 DEFINE_RES_MEM(0xe0050180, 0x2c),
140 DEFINE_RES_MEM(0xe00501c0, 0x20),
141 DEFINE_RES_IRQ(105),
142 DEFINE_RES_IRQ(106),
143};
144
145static struct gpio_em_config gio4_config = {
146 .gpio_base = 128,
147 .irq_base = EMEV2_GPIO_IRQ(128),
148 .number_of_pins = 31,
149};
150
151static struct resource gio4_resources[] = {
152 DEFINE_RES_MEM(0xe0050200, 0x2c),
153 DEFINE_RES_MEM(0xe0050240, 0x20),
154 DEFINE_RES_IRQ(107),
155 DEFINE_RES_IRQ(108),
156};
157
158#define emev2_register_gio(idx) \
159 platform_device_register_resndata(&platform_bus, "em_gio", \
160 idx, gio##idx##_resources, \
161 ARRAY_SIZE(gio##idx##_resources), \
162 &gio##idx##_config, \
163 sizeof(struct gpio_em_config))
164
165static struct resource pmu_resources[] = {
166 DEFINE_RES_IRQ(152),
167 DEFINE_RES_IRQ(153),
168};
169
170#define emev2_register_pmu() \
171 platform_device_register_simple("arm-pmu", -1, \
172 pmu_resources, \
173 ARRAY_SIZE(pmu_resources))
174
175void __init emev2_add_standard_devices(void)
176{
177 if (!IS_ENABLED(CONFIG_COMMON_CLK))
178 emev2_clock_init();
179
180 emev2_register_uart(0);
181 emev2_register_uart(1);
182 emev2_register_uart(2);
183 emev2_register_uart(3);
184 emev2_register_sti();
185 emev2_register_gio(0);
186 emev2_register_gio(1);
187 emev2_register_gio(2);
188 emev2_register_gio(3);
189 emev2_register_gio(4);
190 emev2_register_pmu();
191}
192
193void __init emev2_init_delay(void) 46void __init emev2_init_delay(void)
194{ 47{
195 shmobile_setup_delay(533, 1, 3); /* Cortex-A9 @ 533MHz */ 48 shmobile_setup_delay(533, 1, 3); /* Cortex-A9 @ 533MHz */
196} 49}
197 50
198#ifdef CONFIG_USE_OF 51static void __init emev2_add_standard_devices_dt(void)
52{
53#ifdef CONFIG_COMMON_CLK
54 of_clk_init(NULL);
55#else
56 emev2_clock_init();
57#endif
58 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
59}
199 60
200static const char *emev2_boards_compat_dt[] __initdata = { 61static const char *emev2_boards_compat_dt[] __initdata = {
201 "renesas,emev2", 62 "renesas,emev2",
@@ -206,7 +67,7 @@ DT_MACHINE_START(EMEV2_DT, "Generic Emma Mobile EV2 (Flattened Device Tree)")
206 .smp = smp_ops(emev2_smp_ops), 67 .smp = smp_ops(emev2_smp_ops),
207 .map_io = emev2_map_io, 68 .map_io = emev2_map_io,
208 .init_early = emev2_init_delay, 69 .init_early = emev2_init_delay,
70 .init_machine = emev2_add_standard_devices_dt,
71 .init_late = shmobile_init_late,
209 .dt_compat = emev2_boards_compat_dt, 72 .dt_compat = emev2_boards_compat_dt,
210MACHINE_END 73MACHINE_END
211
212#endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/setup-r7s72100.c b/arch/arm/mach-shmobile/setup-r7s72100.c
index d4eb509a1c87..55f0b9c7c482 100644
--- a/arch/arm/mach-shmobile/setup-r7s72100.c
+++ b/arch/arm/mach-shmobile/setup-r7s72100.c
@@ -22,6 +22,7 @@
22#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <linux/of_platform.h> 23#include <linux/of_platform.h>
24#include <linux/serial_sci.h> 24#include <linux/serial_sci.h>
25#include <linux/sh_timer.h>
25#include <mach/common.h> 26#include <mach/common.h>
26#include <mach/irqs.h> 27#include <mach/irqs.h>
27#include <mach/r7s72100.h> 28#include <mach/r7s72100.h>
@@ -58,6 +59,26 @@ static inline void r7s72100_register_scif(int idx)
58 sizeof(struct plat_sci_port)); 59 sizeof(struct plat_sci_port));
59} 60}
60 61
62
63static struct sh_timer_config mtu2_0_platform_data __initdata = {
64 .name = "MTU2_0",
65 .timer_bit = 0,
66 .channel_offset = -0x80,
67 .clockevent_rating = 200,
68};
69
70static struct resource mtu2_0_resources[] __initdata = {
71 DEFINE_RES_MEM(0xfcff0300, 0x27),
72 DEFINE_RES_IRQ(gic_iid(139)), /* MTU2 TGI0A */
73};
74
75#define r7s72100_register_mtu2(idx) \
76 platform_device_register_resndata(&platform_bus, "sh_mtu2", \
77 idx, mtu2_##idx##_resources, \
78 ARRAY_SIZE(mtu2_##idx##_resources), \
79 &mtu2_##idx##_platform_data, \
80 sizeof(struct sh_timer_config))
81
61void __init r7s72100_add_dt_devices(void) 82void __init r7s72100_add_dt_devices(void)
62{ 83{
63 r7s72100_register_scif(SCIF0); 84 r7s72100_register_scif(SCIF0);
@@ -68,6 +89,7 @@ void __init r7s72100_add_dt_devices(void)
68 r7s72100_register_scif(SCIF5); 89 r7s72100_register_scif(SCIF5);
69 r7s72100_register_scif(SCIF6); 90 r7s72100_register_scif(SCIF6);
70 r7s72100_register_scif(SCIF7); 91 r7s72100_register_scif(SCIF7);
92 r7s72100_register_mtu2(0);
71} 93}
72 94
73void __init r7s72100_init_early(void) 95void __init r7s72100_init_early(void)
diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c
index b0f2749071be..cc94b64c2ef5 100644
--- a/arch/arm/mach-shmobile/setup-r8a73a4.c
+++ b/arch/arm/mach-shmobile/setup-r8a73a4.c
@@ -275,7 +275,7 @@ static const struct sh_dmae_pdata dma_pdata = {
275 275
276static struct resource dma_resources[] = { 276static struct resource dma_resources[] = {
277 DEFINE_RES_MEM(0xe6700020, 0x89e0), 277 DEFINE_RES_MEM(0xe6700020, 0x89e0),
278 DEFINE_RES_IRQ_NAMED(gic_spi(220), "error_irq"), 278 DEFINE_RES_IRQ(gic_spi(220)),
279 { 279 {
280 /* IRQ for channels 0-19 */ 280 /* IRQ for channels 0-19 */
281 .start = gic_spi(200), 281 .start = gic_spi(200),
diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c
index 03fcc5974ef9..81701cfb6cc6 100644
--- a/arch/arm/mach-shmobile/setup-r8a7778.c
+++ b/arch/arm/mach-shmobile/setup-r8a7778.c
@@ -319,6 +319,29 @@ void __init r8a7778_add_dt_devices(void)
319#define HPB_DMAE_ASYNCMDR_ASMD21_SINGLE BIT(1) /* SDHI0 */ 319#define HPB_DMAE_ASYNCMDR_ASMD21_SINGLE BIT(1) /* SDHI0 */
320#define HPB_DMAE_ASYNCMDR_ASMD21_MULTI 0 /* SDHI0 */ 320#define HPB_DMAE_ASYNCMDR_ASMD21_MULTI 0 /* SDHI0 */
321 321
322#define HPBDMA_HPBIF(_id) \
323{ \
324 .id = HPBDMA_SLAVE_HPBIF## _id ##_TX, \
325 .addr = 0xffda0000 + (_id * 0x1000), \
326 .dcr = HPB_DMAE_DCR_CT | \
327 HPB_DMAE_DCR_DIP | \
328 HPB_DMAE_DCR_SPDS_32BIT | \
329 HPB_DMAE_DCR_DMDL | \
330 HPB_DMAE_DCR_DPDS_32BIT, \
331 .port = 0x1111, \
332 .dma_ch = (28 + _id), \
333}, { \
334 .id = HPBDMA_SLAVE_HPBIF## _id ##_RX, \
335 .addr = 0xffda0000 + (_id * 0x1000), \
336 .dcr = HPB_DMAE_DCR_CT | \
337 HPB_DMAE_DCR_DIP | \
338 HPB_DMAE_DCR_SMDL | \
339 HPB_DMAE_DCR_SPDS_32BIT | \
340 HPB_DMAE_DCR_DPDS_32BIT, \
341 .port = 0x1111, \
342 .dma_ch = (28 + _id), \
343}
344
322static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = { 345static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = {
323 { 346 {
324 .id = HPBDMA_SLAVE_SDHI0_TX, 347 .id = HPBDMA_SLAVE_SDHI0_TX,
@@ -349,11 +372,39 @@ static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = {
349 .flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE, 372 .flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE,
350 .dma_ch = 22, 373 .dma_ch = 22,
351 }, 374 },
375
376 HPBDMA_HPBIF(0),
377 HPBDMA_HPBIF(1),
378 HPBDMA_HPBIF(2),
379 HPBDMA_HPBIF(3),
380 HPBDMA_HPBIF(4),
381 HPBDMA_HPBIF(5),
382 HPBDMA_HPBIF(6),
383 HPBDMA_HPBIF(7),
384 HPBDMA_HPBIF(8),
352}; 385};
353 386
354static const struct hpb_dmae_channel hpb_dmae_channels[] = { 387static const struct hpb_dmae_channel hpb_dmae_channels[] = {
355 HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_TX), /* ch. 21 */ 388 HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_TX), /* ch. 21 */
356 HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_RX), /* ch. 22 */ 389 HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_RX), /* ch. 22 */
390 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF0_TX), /* ch. 28 */
391 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF0_RX), /* ch. 28 */
392 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF1_TX), /* ch. 29 */
393 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF1_RX), /* ch. 29 */
394 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF2_TX), /* ch. 30 */
395 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF2_RX), /* ch. 30 */
396 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF3_TX), /* ch. 31 */
397 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF3_RX), /* ch. 31 */
398 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF4_TX), /* ch. 32 */
399 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF4_RX), /* ch. 32 */
400 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF5_TX), /* ch. 33 */
401 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF5_RX), /* ch. 33 */
402 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF6_TX), /* ch. 34 */
403 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF6_RX), /* ch. 34 */
404 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF7_TX), /* ch. 35 */
405 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF7_RX), /* ch. 35 */
406 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF8_TX), /* ch. 36 */
407 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF8_RX), /* ch. 36 */
357}; 408};
358 409
359static struct hpb_dmae_pdata dma_platform_data __initdata = { 410static struct hpb_dmae_pdata dma_platform_data __initdata = {
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index 13049e9d691c..8f9453152fb9 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -598,45 +598,6 @@ static struct platform_device ohci1_device = {
598 .resource = ohci1_resources, 598 .resource = ohci1_resources,
599}; 599};
600 600
601/* Ether */
602static struct resource ether_resources[] __initdata = {
603 {
604 .start = 0xfde00000,
605 .end = 0xfde003ff,
606 .flags = IORESOURCE_MEM,
607 }, {
608 .start = gic_iid(0xb4),
609 .flags = IORESOURCE_IRQ,
610 },
611};
612
613#define R8A7779_VIN(idx) \
614static struct resource vin##idx##_resources[] __initdata = { \
615 DEFINE_RES_MEM(0xffc50000 + 0x1000 * (idx), 0x1000), \
616 DEFINE_RES_IRQ(gic_iid(0x5f + (idx))), \
617}; \
618 \
619static struct platform_device_info vin##idx##_info __initdata = { \
620 .parent = &platform_bus, \
621 .name = "r8a7779-vin", \
622 .id = idx, \
623 .res = vin##idx##_resources, \
624 .num_res = ARRAY_SIZE(vin##idx##_resources), \
625 .dma_mask = DMA_BIT_MASK(32), \
626}
627
628R8A7779_VIN(0);
629R8A7779_VIN(1);
630R8A7779_VIN(2);
631R8A7779_VIN(3);
632
633static struct platform_device_info *vin_info_table[] __initdata = {
634 &vin0_info,
635 &vin1_info,
636 &vin2_info,
637 &vin3_info,
638};
639
640/* HPB-DMA */ 601/* HPB-DMA */
641 602
642/* Asynchronous mode register bits */ 603/* Asynchronous mode register bits */
@@ -825,24 +786,6 @@ void __init r8a7779_add_standard_devices(void)
825 r8a7779_register_hpb_dmae(); 786 r8a7779_register_hpb_dmae();
826} 787}
827 788
828void __init r8a7779_add_ether_device(struct sh_eth_plat_data *pdata)
829{
830 platform_device_register_resndata(&platform_bus, "r8a777x-ether", -1,
831 ether_resources,
832 ARRAY_SIZE(ether_resources),
833 pdata, sizeof(*pdata));
834}
835
836void __init r8a7779_add_vin_device(int id, struct rcar_vin_platform_data *pdata)
837{
838 BUG_ON(id < 0 || id > 3);
839
840 vin_info_table[id]->data = pdata;
841 vin_info_table[id]->size_data = sizeof(*pdata);
842
843 platform_device_register_full(vin_info_table[id]);
844}
845
846/* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */ 789/* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
847void __init __weak r8a7779_register_twd(void) { } 790void __init __weak r8a7779_register_twd(void) { }
848 791
diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
index c47bcebbcb00..3543c3bacb75 100644
--- a/arch/arm/mach-shmobile/setup-r8a7790.c
+++ b/arch/arm/mach-shmobile/setup-r8a7790.c
@@ -34,6 +34,10 @@ static const struct resource pfc_resources[] __initconst = {
34 DEFINE_RES_MEM(0xe6060000, 0x250), 34 DEFINE_RES_MEM(0xe6060000, 0x250),
35}; 35};
36 36
37#define r8a7790_register_pfc() \
38 platform_device_register_simple("pfc-r8a7790", -1, pfc_resources, \
39 ARRAY_SIZE(pfc_resources))
40
37#define R8A7790_GPIO(idx) \ 41#define R8A7790_GPIO(idx) \
38static const struct resource r8a7790_gpio##idx##_resources[] __initconst = { \ 42static const struct resource r8a7790_gpio##idx##_resources[] __initconst = { \
39 DEFINE_RES_MEM(0xe6050000 + 0x1000 * (idx), 0x50), \ 43 DEFINE_RES_MEM(0xe6050000 + 0x1000 * (idx), 0x50), \
@@ -65,8 +69,7 @@ R8A7790_GPIO(5);
65 69
66void __init r8a7790_pinmux_init(void) 70void __init r8a7790_pinmux_init(void)
67{ 71{
68 platform_device_register_simple("pfc-r8a7790", -1, pfc_resources, 72 r8a7790_register_pfc();
69 ARRAY_SIZE(pfc_resources));
70 r8a7790_register_gpio(0); 73 r8a7790_register_gpio(0);
71 r8a7790_register_gpio(1); 74 r8a7790_register_gpio(1);
72 r8a7790_register_gpio(2); 75 r8a7790_register_gpio(2);
diff --git a/arch/arm/mach-shmobile/setup-r8a7791.c b/arch/arm/mach-shmobile/setup-r8a7791.c
index d9393d61ee27..cddca99b434f 100644
--- a/arch/arm/mach-shmobile/setup-r8a7791.c
+++ b/arch/arm/mach-shmobile/setup-r8a7791.c
@@ -22,6 +22,7 @@
22#include <linux/irq.h> 22#include <linux/irq.h>
23#include <linux/kernel.h> 23#include <linux/kernel.h>
24#include <linux/of_platform.h> 24#include <linux/of_platform.h>
25#include <linux/platform_data/gpio-rcar.h>
25#include <linux/platform_data/irq-renesas-irqc.h> 26#include <linux/platform_data/irq-renesas-irqc.h>
26#include <linux/serial_sci.h> 27#include <linux/serial_sci.h>
27#include <linux/sh_timer.h> 28#include <linux/sh_timer.h>
@@ -31,6 +32,58 @@
31#include <mach/rcar-gen2.h> 32#include <mach/rcar-gen2.h>
32#include <asm/mach/arch.h> 33#include <asm/mach/arch.h>
33 34
35static const struct resource pfc_resources[] __initconst = {
36 DEFINE_RES_MEM(0xe6060000, 0x250),
37};
38
39#define r8a7791_register_pfc() \
40 platform_device_register_simple("pfc-r8a7791", -1, pfc_resources, \
41 ARRAY_SIZE(pfc_resources))
42
43#define R8A7791_GPIO(idx, base, nr) \
44static const struct resource r8a7791_gpio##idx##_resources[] __initconst = { \
45 DEFINE_RES_MEM((base), 0x50), \
46 DEFINE_RES_IRQ(gic_spi(4 + (idx))), \
47}; \
48 \
49static const struct gpio_rcar_config \
50r8a7791_gpio##idx##_platform_data __initconst = { \
51 .gpio_base = 32 * (idx), \
52 .irq_base = 0, \
53 .number_of_pins = (nr), \
54 .pctl_name = "pfc-r8a7791", \
55 .has_both_edge_trigger = 1, \
56}; \
57
58R8A7791_GPIO(0, 0xe6050000, 32);
59R8A7791_GPIO(1, 0xe6051000, 32);
60R8A7791_GPIO(2, 0xe6052000, 32);
61R8A7791_GPIO(3, 0xe6053000, 32);
62R8A7791_GPIO(4, 0xe6054000, 32);
63R8A7791_GPIO(5, 0xe6055000, 32);
64R8A7791_GPIO(6, 0xe6055400, 32);
65R8A7791_GPIO(7, 0xe6055800, 26);
66
67#define r8a7791_register_gpio(idx) \
68 platform_device_register_resndata(&platform_bus, "gpio_rcar", idx, \
69 r8a7791_gpio##idx##_resources, \
70 ARRAY_SIZE(r8a7791_gpio##idx##_resources), \
71 &r8a7791_gpio##idx##_platform_data, \
72 sizeof(r8a7791_gpio##idx##_platform_data))
73
74void __init r8a7791_pinmux_init(void)
75{
76 r8a7791_register_pfc();
77 r8a7791_register_gpio(0);
78 r8a7791_register_gpio(1);
79 r8a7791_register_gpio(2);
80 r8a7791_register_gpio(3);
81 r8a7791_register_gpio(4);
82 r8a7791_register_gpio(5);
83 r8a7791_register_gpio(6);
84 r8a7791_register_gpio(7);
85}
86
34#define SCIF_COMMON(scif_type, baseaddr, irq) \ 87#define SCIF_COMMON(scif_type, baseaddr, irq) \
35 .type = scif_type, \ 88 .type = scif_type, \
36 .mapbase = baseaddr, \ 89 .mapbase = baseaddr, \
@@ -136,6 +189,17 @@ static struct resource irqc0_resources[] = {
136 &irqc##idx##_data, \ 189 &irqc##idx##_data, \
137 sizeof(struct renesas_irqc_config)) 190 sizeof(struct renesas_irqc_config))
138 191
192static const struct resource thermal_resources[] __initconst = {
193 DEFINE_RES_MEM(0xe61f0000, 0x14),
194 DEFINE_RES_MEM(0xe61f0100, 0x38),
195 DEFINE_RES_IRQ(gic_spi(69)),
196};
197
198#define r8a7791_register_thermal() \
199 platform_device_register_simple("rcar_thermal", -1, \
200 thermal_resources, \
201 ARRAY_SIZE(thermal_resources))
202
139void __init r8a7791_add_dt_devices(void) 203void __init r8a7791_add_dt_devices(void)
140{ 204{
141 r8a7791_register_scif(SCIFA0); 205 r8a7791_register_scif(SCIFA0);
@@ -160,6 +224,7 @@ void __init r8a7791_add_standard_devices(void)
160{ 224{
161 r8a7791_add_dt_devices(); 225 r8a7791_add_dt_devices();
162 r8a7791_register_irqc(0); 226 r8a7791_register_irqc(0);
227 r8a7791_register_thermal();
163} 228}
164 229
165void __init r8a7791_init_early(void) 230void __init r8a7791_init_early(void)
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index 22de17417fd7..65151c48cbd4 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -273,7 +273,7 @@ static struct sh_timer_config tmu00_platform_data = {
273}; 273};
274 274
275static struct resource tmu00_resources[] = { 275static struct resource tmu00_resources[] = {
276 [0] = DEFINE_RES_MEM_NAMED(0xfff60008, 0xc, "TMU00"), 276 [0] = DEFINE_RES_MEM(0xfff60008, 0xc),
277 [1] = { 277 [1] = {
278 .start = intcs_evt2irq(0x0e80), /* TMU0_TUNI00 */ 278 .start = intcs_evt2irq(0x0e80), /* TMU0_TUNI00 */
279 .flags = IORESOURCE_IRQ, 279 .flags = IORESOURCE_IRQ,
@@ -298,7 +298,7 @@ static struct sh_timer_config tmu01_platform_data = {
298}; 298};
299 299
300static struct resource tmu01_resources[] = { 300static struct resource tmu01_resources[] = {
301 [0] = DEFINE_RES_MEM_NAMED(0xfff60014, 0xc, "TMU00"), 301 [0] = DEFINE_RES_MEM(0xfff60014, 0xc),
302 [1] = { 302 [1] = {
303 .start = intcs_evt2irq(0x0ea0), /* TMU0_TUNI01 */ 303 .start = intcs_evt2irq(0x0ea0), /* TMU0_TUNI01 */
304 .flags = IORESOURCE_IRQ, 304 .flags = IORESOURCE_IRQ,
@@ -316,7 +316,7 @@ static struct platform_device tmu01_device = {
316}; 316};
317 317
318static struct resource i2c0_resources[] = { 318static struct resource i2c0_resources[] = {
319 [0] = DEFINE_RES_MEM_NAMED(0xe6820000, 0x426, "IIC0"), 319 [0] = DEFINE_RES_MEM(0xe6820000, 0x426),
320 [1] = { 320 [1] = {
321 .start = gic_spi(167), 321 .start = gic_spi(167),
322 .end = gic_spi(170), 322 .end = gic_spi(170),
@@ -325,7 +325,7 @@ static struct resource i2c0_resources[] = {
325}; 325};
326 326
327static struct resource i2c1_resources[] = { 327static struct resource i2c1_resources[] = {
328 [0] = DEFINE_RES_MEM_NAMED(0xe6822000, 0x426, "IIC1"), 328 [0] = DEFINE_RES_MEM(0xe6822000, 0x426),
329 [1] = { 329 [1] = {
330 .start = gic_spi(51), 330 .start = gic_spi(51),
331 .end = gic_spi(54), 331 .end = gic_spi(54),
@@ -334,7 +334,7 @@ static struct resource i2c1_resources[] = {
334}; 334};
335 335
336static struct resource i2c2_resources[] = { 336static struct resource i2c2_resources[] = {
337 [0] = DEFINE_RES_MEM_NAMED(0xe6824000, 0x426, "IIC2"), 337 [0] = DEFINE_RES_MEM(0xe6824000, 0x426),
338 [1] = { 338 [1] = {
339 .start = gic_spi(171), 339 .start = gic_spi(171),
340 .end = gic_spi(174), 340 .end = gic_spi(174),
@@ -343,7 +343,7 @@ static struct resource i2c2_resources[] = {
343}; 343};
344 344
345static struct resource i2c3_resources[] = { 345static struct resource i2c3_resources[] = {
346 [0] = DEFINE_RES_MEM_NAMED(0xe6826000, 0x426, "IIC3"), 346 [0] = DEFINE_RES_MEM(0xe6826000, 0x426),
347 [1] = { 347 [1] = {
348 .start = gic_spi(183), 348 .start = gic_spi(183),
349 .end = gic_spi(186), 349 .end = gic_spi(186),
@@ -352,7 +352,7 @@ static struct resource i2c3_resources[] = {
352}; 352};
353 353
354static struct resource i2c4_resources[] = { 354static struct resource i2c4_resources[] = {
355 [0] = DEFINE_RES_MEM_NAMED(0xe6828000, 0x426, "IIC4"), 355 [0] = DEFINE_RES_MEM(0xe6828000, 0x426),
356 [1] = { 356 [1] = {
357 .start = gic_spi(187), 357 .start = gic_spi(187),
358 .end = gic_spi(190), 358 .end = gic_spi(190),
@@ -722,7 +722,7 @@ static struct platform_device pmu_device = {
722 722
723/* an IPMMU module for ICB */ 723/* an IPMMU module for ICB */
724static struct resource ipmmu_resources[] = { 724static struct resource ipmmu_resources[] = {
725 DEFINE_RES_MEM_NAMED(0xfe951000, 0x100, "IPMMU"), 725 DEFINE_RES_MEM(0xfe951000, 0x100),
726}; 726};
727 727
728static const char * const ipmmu_dev_names[] = { 728static const char * const ipmmu_dev_names[] = {
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 037100a1563a..aee77f06f887 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -10,6 +10,7 @@ config ARCH_SOCFPGA
10 select GENERIC_CLOCKEVENTS 10 select GENERIC_CLOCKEVENTS
11 select GPIO_PL061 if GPIOLIB 11 select GPIO_PL061 if GPIOLIB
12 select HAVE_ARM_SCU 12 select HAVE_ARM_SCU
13 select HAVE_ARM_TWD if SMP
13 select HAVE_SMP 14 select HAVE_SMP
14 select MFD_SYSCON 15 select MFD_SYSCON
15 select SPARSE_IRQ 16 select SPARSE_IRQ
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 09e740f58b27..15c09294effa 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -14,6 +14,8 @@ config ARCH_TEGRA
14 select MIGHT_HAVE_CACHE_L2X0 14 select MIGHT_HAVE_CACHE_L2X0
15 select MIGHT_HAVE_PCI 15 select MIGHT_HAVE_PCI
16 select PINCTRL 16 select PINCTRL
17 select ARCH_HAS_RESET_CONTROLLER
18 select RESET_CONTROLLER
17 select SOC_BUS 19 select SOC_BUS
18 select SPARSE_IRQ 20 select SPARSE_IRQ
19 select USB_ARCH_HAS_EHCI if USB_SUPPORT 21 select USB_ARCH_HAS_EHCI if USB_SUPPORT
diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c
index d4639c506622..9a4e910c3796 100644
--- a/arch/arm/mach-tegra/fuse.c
+++ b/arch/arm/mach-tegra/fuse.c
@@ -209,13 +209,3 @@ void __init tegra_init_fuse(void)
209 tegra_sku_id, tegra_cpu_process_id, 209 tegra_sku_id, tegra_cpu_process_id,
210 tegra_core_process_id); 210 tegra_core_process_id);
211} 211}
212
213unsigned long long tegra_chip_uid(void)
214{
215 unsigned long long lo, hi;
216
217 lo = tegra_fuse_readl(FUSE_UID_LOW);
218 hi = tegra_fuse_readl(FUSE_UID_HIGH);
219 return (hi << 32ull) | lo;
220}
221EXPORT_SYMBOL(tegra_chip_uid);
diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c
index 85d28e756bb7..f6f5b54ff95e 100644
--- a/arch/arm/mach-tegra/powergate.c
+++ b/arch/arm/mach-tegra/powergate.c
@@ -25,6 +25,7 @@
25#include <linux/export.h> 25#include <linux/export.h>
26#include <linux/init.h> 26#include <linux/init.h>
27#include <linux/io.h> 27#include <linux/io.h>
28#include <linux/reset.h>
28#include <linux/seq_file.h> 29#include <linux/seq_file.h>
29#include <linux/spinlock.h> 30#include <linux/spinlock.h>
30#include <linux/clk/tegra.h> 31#include <linux/clk/tegra.h>
@@ -144,11 +145,12 @@ int tegra_powergate_remove_clamping(int id)
144} 145}
145 146
146/* Must be called with clk disabled, and returns with clk enabled */ 147/* Must be called with clk disabled, and returns with clk enabled */
147int tegra_powergate_sequence_power_up(int id, struct clk *clk) 148int tegra_powergate_sequence_power_up(int id, struct clk *clk,
149 struct reset_control *rst)
148{ 150{
149 int ret; 151 int ret;
150 152
151 tegra_periph_reset_assert(clk); 153 reset_control_assert(rst);
152 154
153 ret = tegra_powergate_power_on(id); 155 ret = tegra_powergate_power_on(id);
154 if (ret) 156 if (ret)
@@ -165,7 +167,7 @@ int tegra_powergate_sequence_power_up(int id, struct clk *clk)
165 goto err_clamp; 167 goto err_clamp;
166 168
167 udelay(10); 169 udelay(10);
168 tegra_periph_reset_deassert(clk); 170 reset_control_deassert(rst);
169 171
170 return 0; 172 return 0;
171 173
diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile
index 616b96e86ad4..d05ba759da30 100644
--- a/arch/arm/mach-ux500/Makefile
+++ b/arch/arm/mach-ux500/Makefile
@@ -2,10 +2,10 @@
2# Makefile for the linux kernel, U8500 machine. 2# Makefile for the linux kernel, U8500 machine.
3# 3#
4 4
5obj-y := cpu.o devices.o id.o timer.o pm.o 5obj-y := cpu.o id.o timer.o pm.o
6obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o 6obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o
7obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o devices-db8500.o 7obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o
8obj-$(CONFIG_MACH_MOP500) += board-mop500.o board-mop500-sdi.o \ 8obj-$(CONFIG_MACH_MOP500) += board-mop500-sdi.o \
9 board-mop500-regulators.o \ 9 board-mop500-regulators.o \
10 board-mop500-pins.o \ 10 board-mop500-pins.o \
11 board-mop500-audio.o 11 board-mop500-audio.o
diff --git a/arch/arm/mach-ux500/board-mop500-audio.c b/arch/arm/mach-ux500/board-mop500-audio.c
index 154e15f59702..dc7f90157766 100644
--- a/arch/arm/mach-ux500/board-mop500-audio.c
+++ b/arch/arm/mach-ux500/board-mop500-audio.c
@@ -7,16 +7,13 @@
7#include <linux/platform_device.h> 7#include <linux/platform_device.h>
8#include <linux/init.h> 8#include <linux/init.h>
9#include <linux/gpio.h> 9#include <linux/gpio.h>
10#include <linux/platform_data/pinctrl-nomadik.h>
11#include <linux/platform_data/dma-ste-dma40.h> 10#include <linux/platform_data/dma-ste-dma40.h>
12 11
13#include "devices.h"
14#include "irqs.h" 12#include "irqs.h"
15#include <linux/platform_data/asoc-ux500-msp.h> 13#include <linux/platform_data/asoc-ux500-msp.h>
16 14
17#include "ste-dma40-db8500.h" 15#include "ste-dma40-db8500.h"
18#include "board-mop500.h" 16#include "board-mop500.h"
19#include "devices-db8500.h"
20 17
21static struct stedma40_chan_cfg msp0_dma_rx = { 18static struct stedma40_chan_cfg msp0_dma_rx = {
22 .high_priority = true, 19 .high_priority = true,
diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c
index 0efb1560fc35..f63619b69113 100644
--- a/arch/arm/mach-ux500/board-mop500-pins.c
+++ b/arch/arm/mach-ux500/board-mop500-pins.c
@@ -10,94 +10,18 @@
10#include <linux/string.h> 10#include <linux/string.h>
11#include <linux/pinctrl/machine.h> 11#include <linux/pinctrl/machine.h>
12#include <linux/pinctrl/pinconf-generic.h> 12#include <linux/pinctrl/pinconf-generic.h>
13#include <linux/platform_data/pinctrl-nomadik.h>
14 13
15#include <asm/mach-types.h> 14#include <asm/mach-types.h>
16 15
17#include "board-mop500.h" 16#include "board-mop500.h"
18 17
19enum custom_pin_cfg_t {
20 PINS_FOR_DEFAULT,
21 PINS_FOR_U9500,
22};
23
24static enum custom_pin_cfg_t pinsfor;
25
26/* These simply sets bias for pins */ 18/* These simply sets bias for pins */
27#define BIAS(a,b) static unsigned long a[] = { b } 19#define BIAS(a,b) static unsigned long a[] = { b }
28 20
29BIAS(pd, PIN_PULL_DOWN);
30BIAS(in_nopull, PIN_INPUT_NOPULL);
31BIAS(in_nopull_slpm_nowkup, PIN_INPUT_NOPULL|PIN_SLPM_WAKEUP_DISABLE);
32BIAS(in_pu, PIN_INPUT_PULLUP);
33BIAS(in_pd, PIN_INPUT_PULLDOWN);
34BIAS(out_hi, PIN_OUTPUT_HIGH);
35BIAS(out_lo, PIN_OUTPUT_LOW);
36BIAS(out_lo_slpm_nowkup, PIN_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE);
37
38BIAS(abx500_out_lo, PIN_CONF_PACKED(PIN_CONFIG_OUTPUT, 0)); 21BIAS(abx500_out_lo, PIN_CONF_PACKED(PIN_CONFIG_OUTPUT, 0));
39BIAS(abx500_in_pd, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 1)); 22BIAS(abx500_in_pd, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 1));
40BIAS(abx500_in_nopull, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 0)); 23BIAS(abx500_in_nopull, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 0));
41 24
42/* These also force them into GPIO mode */
43BIAS(gpio_in_pu, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED);
44BIAS(gpio_in_pd, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED);
45BIAS(gpio_in_pu_slpm_gpio_nopull, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED|PIN_SLPM_GPIO|PIN_SLPM_INPUT_NOPULL);
46BIAS(gpio_in_pd_slpm_gpio_nopull, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED|PIN_SLPM_GPIO|PIN_SLPM_INPUT_NOPULL);
47BIAS(gpio_out_hi, PIN_OUTPUT_HIGH|PIN_GPIOMODE_ENABLED);
48BIAS(gpio_out_lo, PIN_OUTPUT_LOW|PIN_GPIOMODE_ENABLED);
49/* Sleep modes */
50BIAS(slpm_in_wkup_pdis, PIN_SLEEPMODE_ENABLED|
51 PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
52BIAS(slpm_in_wkup_pdis_en, PIN_SLEEPMODE_ENABLED|
53 PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_ENABLED);
54BIAS(slpm_wkup_pdis, PIN_SLEEPMODE_ENABLED|
55 PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
56BIAS(slpm_wkup_pdis_en, PIN_SLEEPMODE_ENABLED|
57 PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_ENABLED);
58BIAS(slpm_out_lo_pdis, PIN_SLEEPMODE_ENABLED|
59 PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE|PIN_SLPM_PDIS_DISABLED);
60BIAS(slpm_out_lo_wkup_pdis, PIN_SLEEPMODE_ENABLED|
61 PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
62BIAS(slpm_out_hi_wkup_pdis, PIN_SLEEPMODE_ENABLED|PIN_SLPM_OUTPUT_HIGH|
63 PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
64BIAS(slpm_in_nopull_wkup_pdis, PIN_SLEEPMODE_ENABLED|
65 PIN_SLPM_INPUT_NOPULL|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
66BIAS(slpm_in_pu_wkup_pdis_en, PIN_SLEEPMODE_ENABLED|PIN_SLPM_INPUT_PULLUP|
67 PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_ENABLED);
68BIAS(slpm_out_wkup_pdis, PIN_SLEEPMODE_ENABLED|
69 PIN_SLPM_DIR_OUTPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
70BIAS(out_lo_wkup_pdis, PIN_SLPM_OUTPUT_LOW|
71 PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
72BIAS(in_wkup_pdis_en, PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|
73 PIN_SLPM_PDIS_ENABLED);
74BIAS(in_wkup_pdis, PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|
75 PIN_SLPM_PDIS_DISABLED);
76BIAS(out_wkup_pdis, PIN_SLPM_DIR_OUTPUT|PIN_SLPM_WAKEUP_ENABLE|
77 PIN_SLPM_PDIS_DISABLED);
78
79/* We use these to define hog settings that are always done on boot */
80#define DB8500_MUX_HOG(group,func) \
81 PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-db8500", group, func)
82#define DB8500_PIN_HOG(pin,conf) \
83 PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-db8500", pin, conf)
84
85/* These are default states associated with device and changed runtime */
86#define DB8500_MUX(group,func,dev) \
87 PIN_MAP_MUX_GROUP_DEFAULT(dev, "pinctrl-db8500", group, func)
88#define DB8500_PIN(pin,conf,dev) \
89 PIN_MAP_CONFIGS_PIN_DEFAULT(dev, "pinctrl-db8500", pin, conf)
90#define DB8500_PIN_IDLE(pin, conf, dev) \
91 PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_IDLE, "pinctrl-db8500", \
92 pin, conf)
93#define DB8500_PIN_SLEEP(pin, conf, dev) \
94 PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_SLEEP, "pinctrl-db8500", \
95 pin, conf)
96#define DB8500_MUX_STATE(group, func, dev, state) \
97 PIN_MAP_MUX_GROUP(dev, state, "pinctrl-db8500", group, func)
98#define DB8500_PIN_STATE(pin, conf, dev, state) \
99 PIN_MAP_CONFIGS_PIN(dev, state, "pinctrl-db8500", pin, conf)
100
101#define AB8500_MUX_HOG(group, func) \ 25#define AB8500_MUX_HOG(group, func) \
102 PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-ab8500.0", group, func) 26 PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-ab8500.0", group, func)
103#define AB8500_PIN_HOG(pin, conf) \ 27#define AB8500_PIN_HOG(pin, conf) \
@@ -344,725 +268,8 @@ static struct pinctrl_map __initdata ab8505_pinmap[] = {
344 AB8505_PIN_HOG("GPIO53_D15", in_pd), 268 AB8505_PIN_HOG("GPIO53_D15", in_pd),
345}; 269};
346 270
347/* Pin control settings */
348static struct pinctrl_map __initdata mop500_family_pinmap[] = {
349 /*
350 * uMSP0, mux in 4 pins, regular placement of RX/TX
351 * explicitly set the pins to no pull
352 */
353 DB8500_MUX_HOG("msp0txrx_a_1", "msp0"),
354 DB8500_MUX_HOG("msp0tfstck_a_1", "msp0"),
355 DB8500_PIN_HOG("GPIO12_AC4", in_nopull), /* TXD */
356 DB8500_PIN_HOG("GPIO15_AC3", in_nopull), /* RXD */
357 DB8500_PIN_HOG("GPIO13_AF3", in_nopull), /* TFS */
358 DB8500_PIN_HOG("GPIO14_AE3", in_nopull), /* TCK */
359 /* MSP2 for HDMI, pull down TXD, TCK, TFS */
360 DB8500_MUX_HOG("msp2_a_1", "msp2"),
361 DB8500_PIN_HOG("GPIO193_AH27", in_pd), /* TXD */
362 DB8500_PIN_HOG("GPIO194_AF27", in_pd), /* TCK */
363 DB8500_PIN_HOG("GPIO195_AG28", in_pd), /* TFS */
364 DB8500_PIN_HOG("GPIO196_AG26", out_lo), /* RXD */
365 /*
366 * LCD, set TE0 (using LCD VSI0) and D14 (touch screen interrupt) to
367 * pull-up
368 * TODO: is this really correct? Snowball doesn't have a LCD.
369 */
370 DB8500_MUX_HOG("lcdvsi0_a_1", "lcd"),
371 DB8500_PIN_HOG("GPIO68_E1", in_pu),
372 DB8500_PIN_HOG("GPIO84_C2", gpio_in_pu),
373 /*
374 * STMPE1601/tc35893 keypad IRQ GPIO 218
375 * TODO: set for snowball and HREF really??
376 */
377 DB8500_PIN_HOG("GPIO218_AH11", gpio_in_pu),
378 /*
379 * UART0, we do not mux in u0 here.
380 * uart-0 pins gpio configuration should be kept intact to prevent
381 * a glitch in tx line when the tty dev is opened. Later these pins
382 * are configured by uart driver
383 */
384 DB8500_PIN_HOG("GPIO0_AJ5", in_pu), /* CTS */
385 DB8500_PIN_HOG("GPIO1_AJ3", out_hi), /* RTS */
386 DB8500_PIN_HOG("GPIO2_AH4", in_pu), /* RXD */
387 DB8500_PIN_HOG("GPIO3_AH3", out_hi), /* TXD */
388 /*
389 * Mux in UART2 on altfunction C and set pull-ups.
390 * TODO: is this used on U8500 variants and Snowball really?
391 * The setting on GPIO31 conflicts with magnetometer use on hrefv60
392 */
393 /* default state for UART2 */
394 DB8500_MUX("u2rxtx_c_1", "u2", "uart2"),
395 DB8500_PIN("GPIO29_W2", in_pu, "uart2"), /* RXD */
396 DB8500_PIN("GPIO30_W3", out_hi, "uart2"), /* TXD */
397 /* Sleep state for UART2 */
398 DB8500_PIN_SLEEP("GPIO29_W2", in_wkup_pdis, "uart2"),
399 DB8500_PIN_SLEEP("GPIO30_W3", out_wkup_pdis, "uart2"),
400 /*
401 * The following pin sets were known as "runtime pins" before being
402 * converted to the pinctrl model. Here we model them as "default"
403 * states.
404 */
405 /* Mux in UART0 after initialization */
406 DB8500_MUX("u0_a_1", "u0", "uart0"),
407 DB8500_PIN("GPIO0_AJ5", in_pu, "uart0"), /* CTS */
408 DB8500_PIN("GPIO1_AJ3", out_hi, "uart0"), /* RTS */
409 DB8500_PIN("GPIO2_AH4", in_pu, "uart0"), /* RXD */
410 DB8500_PIN("GPIO3_AH3", out_hi, "uart0"), /* TXD */
411 /* Sleep state for UART0 */
412 DB8500_PIN_SLEEP("GPIO0_AJ5", slpm_in_wkup_pdis, "uart0"),
413 DB8500_PIN_SLEEP("GPIO1_AJ3", slpm_out_hi_wkup_pdis, "uart0"),
414 DB8500_PIN_SLEEP("GPIO2_AH4", slpm_in_wkup_pdis, "uart0"),
415 DB8500_PIN_SLEEP("GPIO3_AH3", slpm_out_wkup_pdis, "uart0"),
416 /* Mux in UART1 after initialization */
417 DB8500_MUX("u1rxtx_a_1", "u1", "uart1"),
418 DB8500_PIN("GPIO4_AH6", in_pu, "uart1"), /* RXD */
419 DB8500_PIN("GPIO5_AG6", out_hi, "uart1"), /* TXD */
420 /* Sleep state for UART1 */
421 DB8500_PIN_SLEEP("GPIO4_AH6", slpm_in_wkup_pdis, "uart1"),
422 DB8500_PIN_SLEEP("GPIO5_AG6", slpm_out_wkup_pdis, "uart1"),
423 /* MSP1 for ALSA codec */
424 DB8500_MUX_HOG("msp1txrx_a_1", "msp1"),
425 DB8500_MUX_HOG("msp1_a_1", "msp1"),
426 DB8500_PIN_HOG("GPIO33_AF2", out_lo_slpm_nowkup),
427 DB8500_PIN_HOG("GPIO34_AE1", in_nopull_slpm_nowkup),
428 DB8500_PIN_HOG("GPIO35_AE2", in_nopull_slpm_nowkup),
429 DB8500_PIN_HOG("GPIO36_AG2", in_nopull_slpm_nowkup),
430 /* Mux in LCD data lines 8 thru 11 and LCDA CLK for MCDE TVOUT */
431 DB8500_MUX("lcd_d8_d11_a_1", "lcd", "mcde-tvout"),
432 DB8500_MUX("lcdaclk_b_1", "lcda", "mcde-tvout"),
433 /* Mux in LCD VSI1 and pull it up for MCDE HDMI output */
434 DB8500_MUX("lcdvsi1_a_1", "lcd", "0-0070"),
435 DB8500_PIN("GPIO69_E2", in_pu, "0-0070"),
436 /* LCD VSI1 sleep state */
437 DB8500_PIN_SLEEP("GPIO69_E2", slpm_in_wkup_pdis, "0-0070"),
438 /* Mux in i2c0 block, default state */
439 DB8500_MUX("i2c0_a_1", "i2c0", "nmk-i2c.0"),
440 /* i2c0 sleep state */
441 DB8500_PIN_SLEEP("GPIO147_C15", slpm_in_nopull_wkup_pdis, "nmk-i2c.0"), /* SDA */
442 DB8500_PIN_SLEEP("GPIO148_B16", slpm_in_nopull_wkup_pdis, "nmk-i2c.0"), /* SCL */
443 /* Mux in i2c1 block, default state */
444 DB8500_MUX("i2c1_b_2", "i2c1", "nmk-i2c.1"),
445 /* i2c1 sleep state */
446 DB8500_PIN_SLEEP("GPIO16_AD3", slpm_in_nopull_wkup_pdis, "nmk-i2c.1"), /* SDA */
447 DB8500_PIN_SLEEP("GPIO17_AD4", slpm_in_nopull_wkup_pdis, "nmk-i2c.1"), /* SCL */
448 /* Mux in i2c2 block, default state */
449 DB8500_MUX("i2c2_b_2", "i2c2", "nmk-i2c.2"),
450 /* i2c2 sleep state */
451 DB8500_PIN_SLEEP("GPIO10_AF5", slpm_in_nopull_wkup_pdis, "nmk-i2c.2"), /* SDA */
452 DB8500_PIN_SLEEP("GPIO11_AG4", slpm_in_nopull_wkup_pdis, "nmk-i2c.2"), /* SCL */
453 /* Mux in i2c3 block, default state */
454 DB8500_MUX("i2c3_c_2", "i2c3", "nmk-i2c.3"),
455 /* i2c3 sleep state */
456 DB8500_PIN_SLEEP("GPIO229_AG7", slpm_in_nopull_wkup_pdis, "nmk-i2c.3"), /* SDA */
457 DB8500_PIN_SLEEP("GPIO230_AF7", slpm_in_nopull_wkup_pdis, "nmk-i2c.3"), /* SCL */
458 /* Mux in SDI0 (here called MC0) used for removable MMC/SD/SDIO cards */
459 DB8500_MUX("mc0_a_1", "mc0", "sdi0"),
460 DB8500_PIN("GPIO18_AC2", out_hi, "sdi0"), /* CMDDIR */
461 DB8500_PIN("GPIO19_AC1", out_hi, "sdi0"), /* DAT0DIR */
462 DB8500_PIN("GPIO20_AB4", out_hi, "sdi0"), /* DAT2DIR */
463 DB8500_PIN("GPIO22_AA3", in_nopull, "sdi0"), /* FBCLK */
464 DB8500_PIN("GPIO23_AA4", out_lo, "sdi0"), /* CLK */
465 DB8500_PIN("GPIO24_AB2", in_pu, "sdi0"), /* CMD */
466 DB8500_PIN("GPIO25_Y4", in_pu, "sdi0"), /* DAT0 */
467 DB8500_PIN("GPIO26_Y2", in_pu, "sdi0"), /* DAT1 */
468 DB8500_PIN("GPIO27_AA2", in_pu, "sdi0"), /* DAT2 */
469 DB8500_PIN("GPIO28_AA1", in_pu, "sdi0"), /* DAT3 */
470 /* SDI0 sleep state */
471 DB8500_PIN_SLEEP("GPIO18_AC2", slpm_out_hi_wkup_pdis, "sdi0"),
472 DB8500_PIN_SLEEP("GPIO19_AC1", slpm_out_hi_wkup_pdis, "sdi0"),
473 DB8500_PIN_SLEEP("GPIO20_AB4", slpm_out_hi_wkup_pdis, "sdi0"),
474 DB8500_PIN_SLEEP("GPIO22_AA3", slpm_in_wkup_pdis, "sdi0"),
475 DB8500_PIN_SLEEP("GPIO23_AA4", slpm_out_lo_wkup_pdis, "sdi0"),
476 DB8500_PIN_SLEEP("GPIO24_AB2", slpm_in_wkup_pdis, "sdi0"),
477 DB8500_PIN_SLEEP("GPIO25_Y4", slpm_in_wkup_pdis, "sdi0"),
478 DB8500_PIN_SLEEP("GPIO26_Y2", slpm_in_wkup_pdis, "sdi0"),
479 DB8500_PIN_SLEEP("GPIO27_AA2", slpm_in_wkup_pdis, "sdi0"),
480 DB8500_PIN_SLEEP("GPIO28_AA1", slpm_in_wkup_pdis, "sdi0"),
481
482 /* Mux in SDI1 (here called MC1) used for SDIO for CW1200 WLAN */
483 DB8500_MUX("mc1_a_1", "mc1", "sdi1"),
484 DB8500_PIN("GPIO208_AH16", out_lo, "sdi1"), /* CLK */
485 DB8500_PIN("GPIO209_AG15", in_nopull, "sdi1"), /* FBCLK */
486 DB8500_PIN("GPIO210_AJ15", in_pu, "sdi1"), /* CMD */
487 DB8500_PIN("GPIO211_AG14", in_pu, "sdi1"), /* DAT0 */
488 DB8500_PIN("GPIO212_AF13", in_pu, "sdi1"), /* DAT1 */
489 DB8500_PIN("GPIO213_AG13", in_pu, "sdi1"), /* DAT2 */
490 DB8500_PIN("GPIO214_AH15", in_pu, "sdi1"), /* DAT3 */
491 /* SDI1 sleep state */
492 DB8500_PIN_SLEEP("GPIO208_AH16", slpm_out_lo_wkup_pdis, "sdi1"), /* CLK */
493 DB8500_PIN_SLEEP("GPIO209_AG15", slpm_in_wkup_pdis, "sdi1"), /* FBCLK */
494 DB8500_PIN_SLEEP("GPIO210_AJ15", slpm_in_wkup_pdis, "sdi1"), /* CMD */
495 DB8500_PIN_SLEEP("GPIO211_AG14", slpm_in_wkup_pdis, "sdi1"), /* DAT0 */
496 DB8500_PIN_SLEEP("GPIO212_AF13", slpm_in_wkup_pdis, "sdi1"), /* DAT1 */
497 DB8500_PIN_SLEEP("GPIO213_AG13", slpm_in_wkup_pdis, "sdi1"), /* DAT2 */
498 DB8500_PIN_SLEEP("GPIO214_AH15", slpm_in_wkup_pdis, "sdi1"), /* DAT3 */
499
500 /* Mux in SDI2 (here called MC2) used for for PoP eMMC */
501 DB8500_MUX("mc2_a_1", "mc2", "sdi2"),
502 DB8500_PIN("GPIO128_A5", out_lo, "sdi2"), /* CLK */
503 DB8500_PIN("GPIO129_B4", in_pu, "sdi2"), /* CMD */
504 DB8500_PIN("GPIO130_C8", in_nopull, "sdi2"), /* FBCLK */
505 DB8500_PIN("GPIO131_A12", in_pu, "sdi2"), /* DAT0 */
506 DB8500_PIN("GPIO132_C10", in_pu, "sdi2"), /* DAT1 */
507 DB8500_PIN("GPIO133_B10", in_pu, "sdi2"), /* DAT2 */
508 DB8500_PIN("GPIO134_B9", in_pu, "sdi2"), /* DAT3 */
509 DB8500_PIN("GPIO135_A9", in_pu, "sdi2"), /* DAT4 */
510 DB8500_PIN("GPIO136_C7", in_pu, "sdi2"), /* DAT5 */
511 DB8500_PIN("GPIO137_A7", in_pu, "sdi2"), /* DAT6 */
512 DB8500_PIN("GPIO138_C5", in_pu, "sdi2"), /* DAT7 */
513 /* SDI2 sleep state */
514 DB8500_PIN_SLEEP("GPIO128_A5", out_lo_wkup_pdis, "sdi2"), /* CLK */
515 DB8500_PIN_SLEEP("GPIO129_B4", in_wkup_pdis_en, "sdi2"), /* CMD */
516 DB8500_PIN_SLEEP("GPIO130_C8", in_wkup_pdis_en, "sdi2"), /* FBCLK */
517 DB8500_PIN_SLEEP("GPIO131_A12", in_wkup_pdis, "sdi2"), /* DAT0 */
518 DB8500_PIN_SLEEP("GPIO132_C10", in_wkup_pdis, "sdi2"), /* DAT1 */
519 DB8500_PIN_SLEEP("GPIO133_B10", in_wkup_pdis, "sdi2"), /* DAT2 */
520 DB8500_PIN_SLEEP("GPIO134_B9", in_wkup_pdis, "sdi2"), /* DAT3 */
521 DB8500_PIN_SLEEP("GPIO135_A9", in_wkup_pdis, "sdi2"), /* DAT4 */
522 DB8500_PIN_SLEEP("GPIO136_C7", in_wkup_pdis, "sdi2"), /* DAT5 */
523 DB8500_PIN_SLEEP("GPIO137_A7", in_wkup_pdis, "sdi2"), /* DAT6 */
524 DB8500_PIN_SLEEP("GPIO138_C5", in_wkup_pdis, "sdi2"), /* DAT7 */
525
526 /* Mux in SDI4 (here called MC4) used for for PCB-mounted eMMC */
527 DB8500_MUX("mc4_a_1", "mc4", "sdi4"),
528 DB8500_PIN("GPIO197_AH24", in_pu, "sdi4"), /* DAT3 */
529 DB8500_PIN("GPIO198_AG25", in_pu, "sdi4"), /* DAT2 */
530 DB8500_PIN("GPIO199_AH23", in_pu, "sdi4"), /* DAT1 */
531 DB8500_PIN("GPIO200_AH26", in_pu, "sdi4"), /* DAT0 */
532 DB8500_PIN("GPIO201_AF24", in_pu, "sdi4"), /* CMD */
533 DB8500_PIN("GPIO202_AF25", in_nopull, "sdi4"), /* FBCLK */
534 DB8500_PIN("GPIO203_AE23", out_lo, "sdi4"), /* CLK */
535 DB8500_PIN("GPIO204_AF23", in_pu, "sdi4"), /* DAT7 */
536 DB8500_PIN("GPIO205_AG23", in_pu, "sdi4"), /* DAT6 */
537 DB8500_PIN("GPIO206_AG24", in_pu, "sdi4"), /* DAT5 */
538 DB8500_PIN("GPIO207_AJ23", in_pu, "sdi4"), /* DAT4 */
539 /*SDI4 sleep state */
540 DB8500_PIN_SLEEP("GPIO197_AH24", slpm_in_wkup_pdis, "sdi4"), /* DAT3 */
541 DB8500_PIN_SLEEP("GPIO198_AG25", slpm_in_wkup_pdis, "sdi4"), /* DAT2 */
542 DB8500_PIN_SLEEP("GPIO199_AH23", slpm_in_wkup_pdis, "sdi4"), /* DAT1 */
543 DB8500_PIN_SLEEP("GPIO200_AH26", slpm_in_wkup_pdis, "sdi4"), /* DAT0 */
544 DB8500_PIN_SLEEP("GPIO201_AF24", slpm_in_wkup_pdis, "sdi4"), /* CMD */
545 DB8500_PIN_SLEEP("GPIO202_AF25", slpm_in_wkup_pdis, "sdi4"), /* FBCLK */
546 DB8500_PIN_SLEEP("GPIO203_AE23", slpm_out_lo_wkup_pdis, "sdi4"), /* CLK */
547 DB8500_PIN_SLEEP("GPIO204_AF23", slpm_in_wkup_pdis, "sdi4"), /* DAT7 */
548 DB8500_PIN_SLEEP("GPIO205_AG23", slpm_in_wkup_pdis, "sdi4"), /* DAT6 */
549 DB8500_PIN_SLEEP("GPIO206_AG24", slpm_in_wkup_pdis, "sdi4"), /* DAT5 */
550 DB8500_PIN_SLEEP("GPIO207_AJ23", slpm_in_wkup_pdis, "sdi4"), /* DAT4 */
551
552 /* Mux in USB pins, drive STP high */
553 /* USB default state */
554 DB8500_MUX("usb_a_1", "usb", "ab8500-usb.0"),
555 DB8500_PIN("GPIO257_AE29", out_hi, "ab8500-usb.0"), /* STP */
556 /* USB sleep state */
557 DB8500_PIN_SLEEP("GPIO256_AF28", slpm_wkup_pdis_en, "ab8500-usb.0"), /* NXT */
558 DB8500_PIN_SLEEP("GPIO257_AE29", slpm_out_hi_wkup_pdis, "ab8500-usb.0"), /* STP */
559 DB8500_PIN_SLEEP("GPIO258_AD29", slpm_wkup_pdis_en, "ab8500-usb.0"), /* XCLK */
560 DB8500_PIN_SLEEP("GPIO259_AC29", slpm_wkup_pdis_en, "ab8500-usb.0"), /* DIR */
561 DB8500_PIN_SLEEP("GPIO260_AD28", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT7 */
562 DB8500_PIN_SLEEP("GPIO261_AD26", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT6 */
563 DB8500_PIN_SLEEP("GPIO262_AE26", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT5 */
564 DB8500_PIN_SLEEP("GPIO263_AG29", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT4 */
565 DB8500_PIN_SLEEP("GPIO264_AE27", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT3 */
566 DB8500_PIN_SLEEP("GPIO265_AD27", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT2 */
567 DB8500_PIN_SLEEP("GPIO266_AC28", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT1 */
568 DB8500_PIN_SLEEP("GPIO267_AC27", slpm_in_wkup_pdis_en, "ab8500-usb.0"), /* DAT0 */
569
570 /* Mux in SPI2 pins on the "other C1" altfunction */
571 DB8500_MUX("spi2_oc1_2", "spi2", "spi2"),
572 DB8500_PIN("GPIO216_AG12", gpio_out_hi, "spi2"), /* FRM */
573 DB8500_PIN("GPIO218_AH11", in_pd, "spi2"), /* RXD */
574 DB8500_PIN("GPIO215_AH13", out_lo, "spi2"), /* TXD */
575 DB8500_PIN("GPIO217_AH12", out_lo, "spi2"), /* CLK */
576 /* SPI2 idle state */
577 DB8500_PIN_IDLE("GPIO218_AH11", slpm_in_wkup_pdis, "spi2"), /* RXD */
578 DB8500_PIN_IDLE("GPIO215_AH13", slpm_out_lo_wkup_pdis, "spi2"), /* TXD */
579 DB8500_PIN_IDLE("GPIO217_AH12", slpm_wkup_pdis, "spi2"), /* CLK */
580 /* SPI2 sleep state */
581 DB8500_PIN_SLEEP("GPIO216_AG12", slpm_in_wkup_pdis, "spi2"), /* FRM */
582 DB8500_PIN_SLEEP("GPIO218_AH11", slpm_in_wkup_pdis, "spi2"), /* RXD */
583 DB8500_PIN_SLEEP("GPIO215_AH13", slpm_out_lo_wkup_pdis, "spi2"), /* TXD */
584 DB8500_PIN_SLEEP("GPIO217_AH12", slpm_wkup_pdis, "spi2"), /* CLK */
585
586 /* ske default state */
587 DB8500_MUX("kp_a_2", "kp", "nmk-ske-keypad"),
588 DB8500_PIN("GPIO153_B17", in_pd, "nmk-ske-keypad"), /* I7 */
589 DB8500_PIN("GPIO154_C16", in_pd, "nmk-ske-keypad"), /* I6 */
590 DB8500_PIN("GPIO155_C19", in_pd, "nmk-ske-keypad"), /* I5 */
591 DB8500_PIN("GPIO156_C17", in_pd, "nmk-ske-keypad"), /* I4 */
592 DB8500_PIN("GPIO161_D21", in_pd, "nmk-ske-keypad"), /* I3 */
593 DB8500_PIN("GPIO162_D20", in_pd, "nmk-ske-keypad"), /* I2 */
594 DB8500_PIN("GPIO163_C20", in_pd, "nmk-ske-keypad"), /* I1 */
595 DB8500_PIN("GPIO164_B21", in_pd, "nmk-ske-keypad"), /* I0 */
596 DB8500_PIN("GPIO157_A18", out_lo, "nmk-ske-keypad"), /* O7 */
597 DB8500_PIN("GPIO158_C18", out_lo, "nmk-ske-keypad"), /* O6 */
598 DB8500_PIN("GPIO159_B19", out_lo, "nmk-ske-keypad"), /* O5 */
599 DB8500_PIN("GPIO160_B20", out_lo, "nmk-ske-keypad"), /* O4 */
600 DB8500_PIN("GPIO165_C21", out_lo, "nmk-ske-keypad"), /* O3 */
601 DB8500_PIN("GPIO166_A22", out_lo, "nmk-ske-keypad"), /* O2 */
602 DB8500_PIN("GPIO167_B24", out_lo, "nmk-ske-keypad"), /* O1 */
603 DB8500_PIN("GPIO168_C22", out_lo, "nmk-ske-keypad"), /* O0 */
604 /* ske sleep state */
605 DB8500_PIN_SLEEP("GPIO153_B17", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I7 */
606 DB8500_PIN_SLEEP("GPIO154_C16", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I6 */
607 DB8500_PIN_SLEEP("GPIO155_C19", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I5 */
608 DB8500_PIN_SLEEP("GPIO156_C17", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I4 */
609 DB8500_PIN_SLEEP("GPIO161_D21", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I3 */
610 DB8500_PIN_SLEEP("GPIO162_D20", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I2 */
611 DB8500_PIN_SLEEP("GPIO163_C20", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I1 */
612 DB8500_PIN_SLEEP("GPIO164_B21", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I0 */
613 DB8500_PIN_SLEEP("GPIO157_A18", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O7 */
614 DB8500_PIN_SLEEP("GPIO158_C18", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O6 */
615 DB8500_PIN_SLEEP("GPIO159_B19", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O5 */
616 DB8500_PIN_SLEEP("GPIO160_B20", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O4 */
617 DB8500_PIN_SLEEP("GPIO165_C21", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O3 */
618 DB8500_PIN_SLEEP("GPIO166_A22", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O2 */
619 DB8500_PIN_SLEEP("GPIO167_B24", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O1 */
620 DB8500_PIN_SLEEP("GPIO168_C22", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O0 */
621
622 /* STM APE pins states */
623 DB8500_MUX_STATE("stmape_c_1", "stmape",
624 "stm", "ape_mipi34"),
625 DB8500_PIN_STATE("GPIO70_G5", in_nopull,
626 "stm", "ape_mipi34"), /* clk */
627 DB8500_PIN_STATE("GPIO71_G4", in_nopull,
628 "stm", "ape_mipi34"), /* dat3 */
629 DB8500_PIN_STATE("GPIO72_H4", in_nopull,
630 "stm", "ape_mipi34"), /* dat2 */
631 DB8500_PIN_STATE("GPIO73_H3", in_nopull,
632 "stm", "ape_mipi34"), /* dat1 */
633 DB8500_PIN_STATE("GPIO74_J3", in_nopull,
634 "stm", "ape_mipi34"), /* dat0 */
635
636 DB8500_PIN_STATE("GPIO70_G5", slpm_out_lo_pdis,
637 "stm", "ape_mipi34_sleep"), /* clk */
638 DB8500_PIN_STATE("GPIO71_G4", slpm_out_lo_pdis,
639 "stm", "ape_mipi34_sleep"), /* dat3 */
640 DB8500_PIN_STATE("GPIO72_H4", slpm_out_lo_pdis,
641 "stm", "ape_mipi34_sleep"), /* dat2 */
642 DB8500_PIN_STATE("GPIO73_H3", slpm_out_lo_pdis,
643 "stm", "ape_mipi34_sleep"), /* dat1 */
644 DB8500_PIN_STATE("GPIO74_J3", slpm_out_lo_pdis,
645 "stm", "ape_mipi34_sleep"), /* dat0 */
646
647 DB8500_MUX_STATE("stmape_oc1_1", "stmape",
648 "stm", "ape_microsd"),
649 DB8500_PIN_STATE("GPIO23_AA4", in_nopull,
650 "stm", "ape_microsd"), /* clk */
651 DB8500_PIN_STATE("GPIO25_Y4", in_nopull,
652 "stm", "ape_microsd"), /* dat0 */
653 DB8500_PIN_STATE("GPIO26_Y2", in_nopull,
654 "stm", "ape_microsd"), /* dat1 */
655 DB8500_PIN_STATE("GPIO27_AA2", in_nopull,
656 "stm", "ape_microsd"), /* dat2 */
657 DB8500_PIN_STATE("GPIO28_AA1", in_nopull,
658 "stm", "ape_microsd"), /* dat3 */
659
660 DB8500_PIN_STATE("GPIO23_AA4", slpm_out_lo_wkup_pdis,
661 "stm", "ape_microsd_sleep"), /* clk */
662 DB8500_PIN_STATE("GPIO25_Y4", slpm_in_wkup_pdis,
663 "stm", "ape_microsd_sleep"), /* dat0 */
664 DB8500_PIN_STATE("GPIO26_Y2", slpm_in_wkup_pdis,
665 "stm", "ape_microsd_sleep"), /* dat1 */
666 DB8500_PIN_STATE("GPIO27_AA2", slpm_in_wkup_pdis,
667 "stm", "ape_microsd_sleep"), /* dat2 */
668 DB8500_PIN_STATE("GPIO28_AA1", slpm_in_wkup_pdis,
669 "stm", "ape_microsd_sleep"), /* dat3 */
670
671 /* STM Modem pins states */
672 DB8500_MUX_STATE("stmmod_oc3_2", "stmmod",
673 "stm", "mod_mipi34"),
674 DB8500_MUX_STATE("uartmodrx_oc3_1", "uartmod",
675 "stm", "mod_mipi34"),
676 DB8500_MUX_STATE("uartmodtx_oc3_1", "uartmod",
677 "stm", "mod_mipi34"),
678 DB8500_PIN_STATE("GPIO70_G5", in_nopull,
679 "stm", "mod_mipi34"), /* clk */
680 DB8500_PIN_STATE("GPIO71_G4", in_nopull,
681 "stm", "mod_mipi34"), /* dat3 */
682 DB8500_PIN_STATE("GPIO72_H4", in_nopull,
683 "stm", "mod_mipi34"), /* dat2 */
684 DB8500_PIN_STATE("GPIO73_H3", in_nopull,
685 "stm", "mod_mipi34"), /* dat1 */
686 DB8500_PIN_STATE("GPIO74_J3", in_nopull,
687 "stm", "mod_mipi34"), /* dat0 */
688 DB8500_PIN_STATE("GPIO75_H2", in_pu,
689 "stm", "mod_mipi34"), /* uartmod rx */
690 DB8500_PIN_STATE("GPIO76_J2", out_lo,
691 "stm", "mod_mipi34"), /* uartmod tx */
692
693 DB8500_PIN_STATE("GPIO70_G5", slpm_out_lo_pdis,
694 "stm", "mod_mipi34_sleep"), /* clk */
695 DB8500_PIN_STATE("GPIO71_G4", slpm_out_lo_pdis,
696 "stm", "mod_mipi34_sleep"), /* dat3 */
697 DB8500_PIN_STATE("GPIO72_H4", slpm_out_lo_pdis,
698 "stm", "mod_mipi34_sleep"), /* dat2 */
699 DB8500_PIN_STATE("GPIO73_H3", slpm_out_lo_pdis,
700 "stm", "mod_mipi34_sleep"), /* dat1 */
701 DB8500_PIN_STATE("GPIO74_J3", slpm_out_lo_pdis,
702 "stm", "mod_mipi34_sleep"), /* dat0 */
703 DB8500_PIN_STATE("GPIO75_H2", slpm_in_wkup_pdis,
704 "stm", "mod_mipi34_sleep"), /* uartmod rx */
705 DB8500_PIN_STATE("GPIO76_J2", slpm_out_lo_wkup_pdis,
706 "stm", "mod_mipi34_sleep"), /* uartmod tx */
707
708 DB8500_MUX_STATE("stmmod_b_1", "stmmod",
709 "stm", "mod_microsd"),
710 DB8500_MUX_STATE("uartmodrx_oc3_1", "uartmod",
711 "stm", "mod_microsd"),
712 DB8500_MUX_STATE("uartmodtx_oc3_1", "uartmod",
713 "stm", "mod_microsd"),
714 DB8500_PIN_STATE("GPIO23_AA4", in_nopull,
715 "stm", "mod_microsd"), /* clk */
716 DB8500_PIN_STATE("GPIO25_Y4", in_nopull,
717 "stm", "mod_microsd"), /* dat0 */
718 DB8500_PIN_STATE("GPIO26_Y2", in_nopull,
719 "stm", "mod_microsd"), /* dat1 */
720 DB8500_PIN_STATE("GPIO27_AA2", in_nopull,
721 "stm", "mod_microsd"), /* dat2 */
722 DB8500_PIN_STATE("GPIO28_AA1", in_nopull,
723 "stm", "mod_microsd"), /* dat3 */
724 DB8500_PIN_STATE("GPIO75_H2", in_pu,
725 "stm", "mod_microsd"), /* uartmod rx */
726 DB8500_PIN_STATE("GPIO76_J2", out_lo,
727 "stm", "mod_microsd"), /* uartmod tx */
728
729 DB8500_PIN_STATE("GPIO23_AA4", slpm_out_lo_wkup_pdis,
730 "stm", "mod_microsd_sleep"), /* clk */
731 DB8500_PIN_STATE("GPIO25_Y4", slpm_in_wkup_pdis,
732 "stm", "mod_microsd_sleep"), /* dat0 */
733 DB8500_PIN_STATE("GPIO26_Y2", slpm_in_wkup_pdis,
734 "stm", "mod_microsd_sleep"), /* dat1 */
735 DB8500_PIN_STATE("GPIO27_AA2", slpm_in_wkup_pdis,
736 "stm", "mod_microsd_sleep"), /* dat2 */
737 DB8500_PIN_STATE("GPIO28_AA1", slpm_in_wkup_pdis,
738 "stm", "mod_microsd_sleep"), /* dat3 */
739 DB8500_PIN_STATE("GPIO75_H2", slpm_in_wkup_pdis,
740 "stm", "mod_microsd_sleep"), /* uartmod rx */
741 DB8500_PIN_STATE("GPIO76_J2", slpm_out_lo_wkup_pdis,
742 "stm", "mod_microsd_sleep"), /* uartmod tx */
743
744 /* STM dual Modem/APE pins state */
745 DB8500_MUX_STATE("stmmod_oc3_2", "stmmod",
746 "stm", "mod_mipi34_ape_mipi60"),
747 DB8500_MUX_STATE("stmape_c_2", "stmape",
748 "stm", "mod_mipi34_ape_mipi60"),
749 DB8500_MUX_STATE("uartmodrx_oc3_1", "uartmod",
750 "stm", "mod_mipi34_ape_mipi60"),
751 DB8500_MUX_STATE("uartmodtx_oc3_1", "uartmod",
752 "stm", "mod_mipi34_ape_mipi60"),
753 DB8500_PIN_STATE("GPIO70_G5", in_nopull,
754 "stm", "mod_mipi34_ape_mipi60"), /* clk */
755 DB8500_PIN_STATE("GPIO71_G4", in_nopull,
756 "stm", "mod_mipi34_ape_mipi60"), /* dat3 */
757 DB8500_PIN_STATE("GPIO72_H4", in_nopull,
758 "stm", "mod_mipi34_ape_mipi60"), /* dat2 */
759 DB8500_PIN_STATE("GPIO73_H3", in_nopull,
760 "stm", "mod_mipi34_ape_mipi60"), /* dat1 */
761 DB8500_PIN_STATE("GPIO74_J3", in_nopull,
762 "stm", "mod_mipi34_ape_mipi60"), /* dat0 */
763 DB8500_PIN_STATE("GPIO75_H2", in_pu,
764 "stm", "mod_mipi34_ape_mipi60"), /* uartmod rx */
765 DB8500_PIN_STATE("GPIO76_J2", out_lo,
766 "stm", "mod_mipi34_ape_mipi60"), /* uartmod tx */
767 DB8500_PIN_STATE("GPIO155_C19", in_nopull,
768 "stm", "mod_mipi34_ape_mipi60"), /* clk */
769 DB8500_PIN_STATE("GPIO156_C17", in_nopull,
770 "stm", "mod_mipi34_ape_mipi60"), /* dat3 */
771 DB8500_PIN_STATE("GPIO157_A18", in_nopull,
772 "stm", "mod_mipi34_ape_mipi60"), /* dat2 */
773 DB8500_PIN_STATE("GPIO158_C18", in_nopull,
774 "stm", "mod_mipi34_ape_mipi60"), /* dat1 */
775 DB8500_PIN_STATE("GPIO159_B19", in_nopull,
776 "stm", "mod_mipi34_ape_mipi60"), /* dat0 */
777
778 DB8500_PIN_STATE("GPIO70_G5", slpm_out_lo_pdis,
779 "stm", "mod_mipi34_ape_mipi60_sleep"), /* clk */
780 DB8500_PIN_STATE("GPIO71_G4", slpm_out_lo_pdis,
781 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat3 */
782 DB8500_PIN_STATE("GPIO72_H4", slpm_out_lo_pdis,
783 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat2 */
784 DB8500_PIN_STATE("GPIO73_H3", slpm_out_lo_pdis,
785 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat1 */
786 DB8500_PIN_STATE("GPIO74_J3", slpm_out_lo_pdis,
787 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat0 */
788 DB8500_PIN_STATE("GPIO75_H2", slpm_in_wkup_pdis,
789 "stm", "mod_mipi34_ape_mipi60_sleep"), /* uartmod rx */
790 DB8500_PIN_STATE("GPIO76_J2", slpm_out_lo_wkup_pdis,
791 "stm", "mod_mipi34_ape_mipi60_sleep"), /* uartmod tx */
792 DB8500_PIN_STATE("GPIO155_C19", slpm_in_wkup_pdis,
793 "stm", "mod_mipi34_ape_mipi60_sleep"), /* clk */
794 DB8500_PIN_STATE("GPIO156_C17", slpm_in_wkup_pdis,
795 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat3 */
796 DB8500_PIN_STATE("GPIO157_A18", slpm_in_wkup_pdis,
797 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat2 */
798 DB8500_PIN_STATE("GPIO158_C18", slpm_in_wkup_pdis,
799 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat1 */
800 DB8500_PIN_STATE("GPIO159_B19", slpm_in_wkup_pdis,
801 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat0 */
802};
803
804/*
805 * These are specifically for the MOP500 and HREFP (pre-v60) version of the
806 * board, which utilized a TC35892 GPIO expander instead of using a lot of
807 * on-chip pins as the HREFv60 and later does.
808 */
809static struct pinctrl_map __initdata mop500_pinmap[] = {
810 /* Mux in SSP0, pull down RXD pin */
811 DB8500_MUX_HOG("ssp0_a_1", "ssp0"),
812 DB8500_PIN_HOG("GPIO145_C13", pd),
813 /*
814 * XENON Flashgun on image processor GPIO (controlled from image
815 * processor firmware), mux in these image processor GPIO lines 0
816 * (XENON_FLASH_ID) and 1 (XENON_READY) on altfunction C and pull up
817 * the pins.
818 */
819 DB8500_MUX_HOG("ipgpio0_c_1", "ipgpio"),
820 DB8500_MUX_HOG("ipgpio1_c_1", "ipgpio"),
821 DB8500_PIN_HOG("GPIO6_AF6", in_pu),
822 DB8500_PIN_HOG("GPIO7_AG5", in_pu),
823 /* TC35892 IRQ, pull up the line, let the driver mux in the pin */
824 DB8500_PIN_HOG("GPIO217_AH12", gpio_in_pu),
825 /* Mux in UART1 and set the pull-ups */
826 DB8500_MUX_HOG("u1rxtx_a_1", "u1"),
827 DB8500_PIN_HOG("GPIO4_AH6", in_pu), /* RXD */
828 DB8500_PIN_HOG("GPIO5_AG6", out_hi), /* TXD */
829 /*
830 * Runtime stuff: make it possible to mux in the SKE keypad
831 * and bias the pins
832 */
833 /* ske default state */
834 DB8500_MUX("kp_a_2", "kp", "nmk-ske-keypad"),
835 DB8500_PIN("GPIO153_B17", in_pu, "nmk-ske-keypad"), /* I7 */
836 DB8500_PIN("GPIO154_C16", in_pu, "nmk-ske-keypad"), /* I6 */
837 DB8500_PIN("GPIO155_C19", in_pu, "nmk-ske-keypad"), /* I5 */
838 DB8500_PIN("GPIO156_C17", in_pu, "nmk-ske-keypad"), /* I4 */
839 DB8500_PIN("GPIO161_D21", in_pu, "nmk-ske-keypad"), /* I3 */
840 DB8500_PIN("GPIO162_D20", in_pu, "nmk-ske-keypad"), /* I2 */
841 DB8500_PIN("GPIO163_C20", in_pu, "nmk-ske-keypad"), /* I1 */
842 DB8500_PIN("GPIO164_B21", in_pu, "nmk-ske-keypad"), /* I0 */
843 DB8500_PIN("GPIO157_A18", out_lo, "nmk-ske-keypad"), /* O7 */
844 DB8500_PIN("GPIO158_C18", out_lo, "nmk-ske-keypad"), /* O6 */
845 DB8500_PIN("GPIO159_B19", out_lo, "nmk-ske-keypad"), /* O5 */
846 DB8500_PIN("GPIO160_B20", out_lo, "nmk-ske-keypad"), /* O4 */
847 DB8500_PIN("GPIO165_C21", out_lo, "nmk-ske-keypad"), /* O3 */
848 DB8500_PIN("GPIO166_A22", out_lo, "nmk-ske-keypad"), /* O2 */
849 DB8500_PIN("GPIO167_B24", out_lo, "nmk-ske-keypad"), /* O1 */
850 DB8500_PIN("GPIO168_C22", out_lo, "nmk-ske-keypad"), /* O0 */
851 /* ske sleep state */
852 DB8500_PIN_SLEEP("GPIO153_B17", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I7 */
853 DB8500_PIN_SLEEP("GPIO154_C16", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I6 */
854 DB8500_PIN_SLEEP("GPIO155_C19", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I5 */
855 DB8500_PIN_SLEEP("GPIO156_C17", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I4 */
856 DB8500_PIN_SLEEP("GPIO161_D21", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I3 */
857 DB8500_PIN_SLEEP("GPIO162_D20", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I2 */
858 DB8500_PIN_SLEEP("GPIO163_C20", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I1 */
859 DB8500_PIN_SLEEP("GPIO164_B21", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I0 */
860 DB8500_PIN_SLEEP("GPIO157_A18", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O7 */
861 DB8500_PIN_SLEEP("GPIO158_C18", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O6 */
862 DB8500_PIN_SLEEP("GPIO159_B19", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O5 */
863 DB8500_PIN_SLEEP("GPIO160_B20", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O4 */
864 DB8500_PIN_SLEEP("GPIO165_C21", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O3 */
865 DB8500_PIN_SLEEP("GPIO166_A22", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O2 */
866 DB8500_PIN_SLEEP("GPIO167_B24", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O1 */
867 DB8500_PIN_SLEEP("GPIO168_C22", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O0 */
868
869 /* Mux in and drive the SDI0 DAT31DIR line high at runtime */
870 DB8500_MUX("mc0dat31dir_a_1", "mc0", "sdi0"),
871 DB8500_PIN("GPIO21_AB3", out_hi, "sdi0"),
872};
873
874/*
875 * The HREFv60 series of platforms is using available pins on the DB8500
876 * insteaf of the Toshiba I2C GPIO expander, reusing some pins like the SSP0
877 * and SSP1 ports (previously connected to the AB8500) as generic GPIO lines.
878 */
879static struct pinctrl_map __initdata hrefv60_pinmap[] = {
880 /* Drive WLAN_ENA low */
881 DB8500_PIN_HOG("GPIO85_D5", gpio_out_lo), /* WLAN_ENA */
882 /*
883 * XENON Flashgun on image processor GPIO (controlled from image
884 * processor firmware), mux in these image processor GPIO lines 0
885 * (XENON_FLASH_ID), 1 (XENON_READY) and there is an assistant
886 * LED on IP GPIO 4 (XENON_EN2) on altfunction C, that need bias
887 * from GPIO21 so pull up 0, 1 and drive 4 and GPIO21 low as output.
888 */
889 DB8500_MUX_HOG("ipgpio0_c_1", "ipgpio"),
890 DB8500_MUX_HOG("ipgpio1_c_1", "ipgpio"),
891 DB8500_MUX_HOG("ipgpio4_c_1", "ipgpio"),
892 DB8500_PIN_HOG("GPIO6_AF6", in_pu), /* XENON_FLASH_ID */
893 DB8500_PIN_HOG("GPIO7_AG5", in_pu), /* XENON_READY */
894 DB8500_PIN_HOG("GPIO21_AB3", gpio_out_lo), /* XENON_EN1 */
895 DB8500_PIN_HOG("GPIO64_F3", out_lo), /* XENON_EN2 */
896 /* Magnetometer uses GPIO 31 and 32, pull these up/down respectively */
897 DB8500_PIN_HOG("GPIO31_V3", gpio_in_pu), /* EN1 */
898 DB8500_PIN_HOG("GPIO32_V2", gpio_in_pd), /* DRDY */
899 /*
900 * Display Interface 1 uses GPIO 65 for RST (reset).
901 * Display Interface 2 uses GPIO 66 for RST (reset).
902 * Drive DISP1 reset high (not reset), driver DISP2 reset low (reset)
903 */
904 DB8500_PIN_HOG("GPIO65_F1", gpio_out_hi), /* DISP1 NO RST */
905 DB8500_PIN_HOG("GPIO66_G3", gpio_out_lo), /* DISP2 RST */
906 /*
907 * Touch screen uses GPIO 143 for RST1, GPIO 146 for RST2 and
908 * GPIO 67 for interrupts. Pull-up the IRQ line and drive both
909 * reset signals low.
910 */
911 DB8500_PIN_HOG("GPIO143_D12", gpio_out_lo), /* TOUCH_RST1 */
912 DB8500_PIN_HOG("GPIO67_G2", gpio_in_pu), /* TOUCH_INT2 */
913 DB8500_PIN_HOG("GPIO146_D13", gpio_out_lo), /* TOUCH_RST2 */
914 /*
915 * Drive D19-D23 for the ETM PTM trace interface low,
916 * (presumably pins are unconnected therefore grounded here,
917 * the "other alt C1" setting enables these pins)
918 */
919 DB8500_PIN_HOG("GPIO70_G5", gpio_out_lo),
920 DB8500_PIN_HOG("GPIO71_G4", gpio_out_lo),
921 DB8500_PIN_HOG("GPIO72_H4", gpio_out_lo),
922 DB8500_PIN_HOG("GPIO73_H3", gpio_out_lo),
923 DB8500_PIN_HOG("GPIO74_J3", gpio_out_lo),
924 /* NAHJ CTRL on GPIO 76 to low, CTRL_INV on GPIO216 to high */
925 DB8500_PIN_HOG("GPIO76_J2", gpio_out_lo), /* CTRL */
926 DB8500_PIN_HOG("GPIO216_AG12", gpio_out_hi), /* CTRL_INV */
927 /* NFC ENA and RESET to low, pulldown IRQ line */
928 DB8500_PIN_HOG("GPIO77_H1", gpio_out_lo), /* NFC_ENA */
929 DB8500_PIN_HOG("GPIO144_B13", gpio_in_pd), /* NFC_IRQ */
930 DB8500_PIN_HOG("GPIO142_C11", gpio_out_lo), /* NFC_RESET */
931 /*
932 * SKE keyboard partly on alt A and partly on "Other alt C1"
933 * Driver KP_O1,2,3,6,7 low and pull up KP_I 0,2,3 for three
934 * rows of 6 keys, then pull up force sensing interrup and
935 * drive reset and force sensing WU low.
936 */
937 DB8500_MUX_HOG("kp_a_1", "kp"),
938 DB8500_MUX_HOG("kp_oc1_1", "kp"),
939 DB8500_PIN_HOG("GPIO90_A3", out_lo), /* KP_O1 */
940 DB8500_PIN_HOG("GPIO87_B3", out_lo), /* KP_O2 */
941 DB8500_PIN_HOG("GPIO86_C6", out_lo), /* KP_O3 */
942 DB8500_PIN_HOG("GPIO96_D8", out_lo), /* KP_O6 */
943 DB8500_PIN_HOG("GPIO94_D7", out_lo), /* KP_O7 */
944 DB8500_PIN_HOG("GPIO93_B7", in_pu), /* KP_I0 */
945 DB8500_PIN_HOG("GPIO89_E6", in_pu), /* KP_I2 */
946 DB8500_PIN_HOG("GPIO88_C4", in_pu), /* KP_I3 */
947 DB8500_PIN_HOG("GPIO91_B6", gpio_in_pu), /* FORCE_SENSING_INT */
948 DB8500_PIN_HOG("GPIO92_D6", gpio_out_lo), /* FORCE_SENSING_RST */
949 DB8500_PIN_HOG("GPIO97_D9", gpio_out_lo), /* FORCE_SENSING_WU */
950 /* DiPro Sensor interrupt */
951 DB8500_PIN_HOG("GPIO139_C9", gpio_in_pu), /* DIPRO_INT */
952 /* Audio Amplifier HF enable */
953 DB8500_PIN_HOG("GPIO149_B14", gpio_out_hi), /* VAUDIO_HF_EN, enable MAX8968 */
954 /* GBF interface, pull low to reset state */
955 DB8500_PIN_HOG("GPIO171_D23", gpio_out_lo), /* GBF_ENA_RESET */
956 /* MSP : HDTV INTERFACE GPIO line */
957 DB8500_PIN_HOG("GPIO192_AJ27", gpio_in_pd),
958 /* Accelerometer interrupt lines */
959 DB8500_PIN_HOG("GPIO82_C1", gpio_in_pu), /* ACC_INT1 */
960 DB8500_PIN_HOG("GPIO83_D3", gpio_in_pu), /* ACC_INT2 */
961 /* SD card detect GPIO pin */
962 DB8500_PIN_HOG("GPIO95_E8", gpio_in_pu),
963 /*
964 * Runtime stuff
965 * Pull up/down of some sensor GPIO pins, for proximity, HAL sensor
966 * etc.
967 */
968 DB8500_PIN("GPIO217_AH12", gpio_in_pu_slpm_gpio_nopull, "gpio-keys.0"),
969 DB8500_PIN("GPIO145_C13", gpio_in_pd_slpm_gpio_nopull, "gpio-keys.0"),
970 DB8500_PIN("GPIO139_C9", gpio_in_pu_slpm_gpio_nopull, "gpio-keys.0"),
971};
972
973static struct pinctrl_map __initdata u9500_pinmap[] = {
974 /* Mux in UART1 (just RX/TX) and set the pull-ups */
975 DB8500_MUX_HOG("u1rxtx_a_1", "u1"),
976 DB8500_PIN_HOG("GPIO4_AH6", in_pu),
977 DB8500_PIN_HOG("GPIO5_AG6", out_hi),
978 /* WLAN_IRQ line */
979 DB8500_PIN_HOG("GPIO144_B13", gpio_in_pu),
980 /* HSI */
981 DB8500_MUX_HOG("hsir_a_1", "hsi"),
982 DB8500_MUX_HOG("hsit_a_2", "hsi"),
983 DB8500_PIN_HOG("GPIO219_AG10", in_pd), /* RX FLA0 */
984 DB8500_PIN_HOG("GPIO220_AH10", in_pd), /* RX DAT0 */
985 DB8500_PIN_HOG("GPIO221_AJ11", out_lo), /* RX RDY0 */
986 DB8500_PIN_HOG("GPIO222_AJ9", out_lo), /* TX FLA0 */
987 DB8500_PIN_HOG("GPIO223_AH9", out_lo), /* TX DAT0 */
988 DB8500_PIN_HOG("GPIO224_AG9", in_pd), /* TX RDY0 */
989 DB8500_PIN_HOG("GPIO225_AG8", in_pd), /* CAWAKE0 */
990 DB8500_PIN_HOG("GPIO226_AF8", gpio_out_hi), /* ACWAKE0 */
991};
992
993static struct pinctrl_map __initdata u8500_pinmap[] = {
994 DB8500_PIN_HOG("GPIO226_AF8", gpio_out_lo), /* WLAN_PMU_EN */
995 DB8500_PIN_HOG("GPIO4_AH6", gpio_in_pu), /* WLAN_IRQ */
996};
997
998static struct pinctrl_map __initdata snowball_pinmap[] = {
999 /* Mux in SSP0 connected to AB8500, pull down RXD pin */
1000 DB8500_MUX_HOG("ssp0_a_1", "ssp0"),
1001 DB8500_PIN_HOG("GPIO145_C13", pd),
1002 /* Always drive the MC0 DAT31DIR line high on these boards */
1003 DB8500_PIN_HOG("GPIO21_AB3", out_hi),
1004 /* Mux in "SM" which is used for the SMSC911x Ethernet adapter */
1005 DB8500_MUX_HOG("sm_b_1", "sm"),
1006 /* User LED */
1007 DB8500_PIN_HOG("GPIO142_C11", gpio_out_hi),
1008 /* Drive RSTn_LAN high */
1009 DB8500_PIN_HOG("GPIO141_C12", gpio_out_hi),
1010 /* Accelerometer/Magnetometer */
1011 DB8500_PIN_HOG("GPIO163_C20", gpio_in_pu), /* ACCEL_IRQ1 */
1012 DB8500_PIN_HOG("GPIO164_B21", gpio_in_pu), /* ACCEL_IRQ2 */
1013 DB8500_PIN_HOG("GPIO165_C21", gpio_in_pu), /* MAG_DRDY */
1014 /* WLAN/GBF */
1015 DB8500_PIN_HOG("GPIO161_D21", gpio_out_lo), /* WLAN_PMU_EN */
1016 DB8500_PIN_HOG("GPIO171_D23", gpio_out_hi), /* GBF_ENA */
1017 DB8500_PIN_HOG("GPIO215_AH13", gpio_out_lo), /* WLAN_ENA */
1018 DB8500_PIN_HOG("GPIO216_AG12", gpio_in_pu), /* WLAN_IRQ */
1019};
1020
1021/*
1022 * passing "pinsfor=" in kernel cmdline allows for custom
1023 * configuration of GPIOs on u8500 derived boards.
1024 */
1025static int __init early_pinsfor(char *p)
1026{
1027 pinsfor = PINS_FOR_DEFAULT;
1028
1029 if (strcmp(p, "u9500-21") == 0)
1030 pinsfor = PINS_FOR_U9500;
1031
1032 return 0;
1033}
1034early_param("pinsfor", early_pinsfor);
1035
1036int pins_for_u9500(void)
1037{
1038 if (pinsfor == PINS_FOR_U9500)
1039 return 1;
1040
1041 return 0;
1042}
1043
1044static void __init mop500_href_family_pinmaps_init(void)
1045{
1046 switch (pinsfor) {
1047 case PINS_FOR_U9500:
1048 pinctrl_register_mappings(u9500_pinmap,
1049 ARRAY_SIZE(u9500_pinmap));
1050 break;
1051 case PINS_FOR_DEFAULT:
1052 pinctrl_register_mappings(u8500_pinmap,
1053 ARRAY_SIZE(u8500_pinmap));
1054 default:
1055 break;
1056 }
1057}
1058
1059void __init mop500_pinmaps_init(void) 271void __init mop500_pinmaps_init(void)
1060{ 272{
1061 pinctrl_register_mappings(mop500_family_pinmap,
1062 ARRAY_SIZE(mop500_family_pinmap));
1063 pinctrl_register_mappings(mop500_pinmap,
1064 ARRAY_SIZE(mop500_pinmap));
1065 mop500_href_family_pinmaps_init();
1066 if (machine_is_u8520()) 273 if (machine_is_u8520())
1067 pinctrl_register_mappings(ab8505_pinmap, 274 pinctrl_register_mappings(ab8505_pinmap,
1068 ARRAY_SIZE(ab8505_pinmap)); 275 ARRAY_SIZE(ab8505_pinmap));
@@ -1073,23 +280,12 @@ void __init mop500_pinmaps_init(void)
1073 280
1074void __init snowball_pinmaps_init(void) 281void __init snowball_pinmaps_init(void)
1075{ 282{
1076 pinctrl_register_mappings(mop500_family_pinmap,
1077 ARRAY_SIZE(mop500_family_pinmap));
1078 pinctrl_register_mappings(snowball_pinmap,
1079 ARRAY_SIZE(snowball_pinmap));
1080 pinctrl_register_mappings(u8500_pinmap,
1081 ARRAY_SIZE(u8500_pinmap));
1082 pinctrl_register_mappings(ab8500_pinmap, 283 pinctrl_register_mappings(ab8500_pinmap,
1083 ARRAY_SIZE(ab8500_pinmap)); 284 ARRAY_SIZE(ab8500_pinmap));
1084} 285}
1085 286
1086void __init hrefv60_pinmaps_init(void) 287void __init hrefv60_pinmaps_init(void)
1087{ 288{
1088 pinctrl_register_mappings(mop500_family_pinmap,
1089 ARRAY_SIZE(mop500_family_pinmap));
1090 pinctrl_register_mappings(hrefv60_pinmap,
1091 ARRAY_SIZE(hrefv60_pinmap));
1092 mop500_href_family_pinmaps_init();
1093 pinctrl_register_mappings(ab8500_pinmap, 289 pinctrl_register_mappings(ab8500_pinmap,
1094 ARRAY_SIZE(ab8500_pinmap)); 290 ARRAY_SIZE(ab8500_pinmap));
1095} 291}
diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c
index 26600a1c5319..fcbf3a13a539 100644
--- a/arch/arm/mach-ux500/board-mop500-sdi.c
+++ b/arch/arm/mach-ux500/board-mop500-sdi.c
@@ -14,10 +14,8 @@
14#include <linux/platform_data/dma-ste-dma40.h> 14#include <linux/platform_data/dma-ste-dma40.h>
15 15
16#include <asm/mach-types.h> 16#include <asm/mach-types.h>
17#include "devices.h"
18 17
19#include "db8500-regs.h" 18#include "db8500-regs.h"
20#include "devices-db8500.h"
21#include "board-mop500.h" 19#include "board-mop500.h"
22#include "ste-dma40-db8500.h" 20#include "ste-dma40-db8500.h"
23 21
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
deleted file mode 100644
index 514d40b625a4..000000000000
--- a/arch/arm/mach-ux500/board-mop500.c
+++ /dev/null
@@ -1,78 +0,0 @@
1/*
2 * Copyright (C) 2008-2012 ST-Ericsson
3 *
4 * Author: Srinidhi KASAGAR <srinidhi.kasagar@stericsson.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2, as
8 * published by the Free Software Foundation.
9 *
10 */
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/interrupt.h>
14#include <linux/platform_device.h>
15#include <linux/clk.h>
16#include <linux/io.h>
17#include <linux/platform_data/db8500_thermal.h>
18#include <linux/amba/bus.h>
19#include <linux/amba/pl022.h>
20#include <linux/mfd/abx500/ab8500.h>
21#include <linux/regulator/ab8500.h>
22#include <linux/regulator/fixed.h>
23#include <linux/regulator/driver.h>
24#include <linux/mfd/tps6105x.h>
25#include <linux/platform_data/leds-lp55xx.h>
26#include <linux/input.h>
27#include <linux/delay.h>
28#include <linux/leds.h>
29#include <linux/pinctrl/consumer.h>
30#include <linux/platform_data/pinctrl-nomadik.h>
31#include <linux/platform_data/dma-ste-dma40.h>
32
33#include <asm/mach-types.h>
34
35#include "setup.h"
36#include "devices.h"
37#include "irqs.h"
38
39#include "ste-dma40-db8500.h"
40#include "db8500-regs.h"
41#include "devices-db8500.h"
42#include "board-mop500.h"
43#include "board-mop500-regulators.h"
44
45struct ab8500_platform_data ab8500_platdata = {
46 .irq_base = MOP500_AB8500_IRQ_BASE,
47 .regulator = &ab8500_regulator_plat_data,
48};
49
50#ifdef CONFIG_STE_DMA40
51static struct stedma40_chan_cfg ssp0_dma_cfg_rx = {
52 .mode = STEDMA40_MODE_LOGICAL,
53 .dir = DMA_DEV_TO_MEM,
54 .dev_type = DB8500_DMA_DEV8_SSP0,
55};
56
57static struct stedma40_chan_cfg ssp0_dma_cfg_tx = {
58 .mode = STEDMA40_MODE_LOGICAL,
59 .dir = DMA_MEM_TO_DEV,
60 .dev_type = DB8500_DMA_DEV8_SSP0,
61};
62#endif
63
64struct pl022_ssp_controller ssp0_plat = {
65 .bus_id = 0,
66#ifdef CONFIG_STE_DMA40
67 .enable_dma = 1,
68 .dma_filter = stedma40_filter,
69 .dma_rx_param = &ssp0_dma_cfg_rx,
70 .dma_tx_param = &ssp0_dma_cfg_tx,
71#else
72 .enable_dma = 0,
73#endif
74 /* on this platform, gpio 31,142,144,214 &
75 * 224 are connected as chip selects
76 */
77 .num_chipselect = 5,
78};
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
index 511d6febbe99..d48e8662c676 100644
--- a/arch/arm/mach-ux500/board-mop500.h
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -87,7 +87,6 @@ extern struct msp_i2s_platform_data msp0_platform_data;
87extern struct msp_i2s_platform_data msp1_platform_data; 87extern struct msp_i2s_platform_data msp1_platform_data;
88extern struct msp_i2s_platform_data msp2_platform_data; 88extern struct msp_i2s_platform_data msp2_platform_data;
89extern struct msp_i2s_platform_data msp3_platform_data; 89extern struct msp_i2s_platform_data msp3_platform_data;
90extern struct pl022_ssp_controller ssp0_plat;
91 90
92void __init mop500_pinmaps_init(void); 91void __init mop500_pinmaps_init(void);
93void __init snowball_pinmaps_init(void); 92void __init snowball_pinmaps_init(void);
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 2e85c1e72535..d8f5ce430fa7 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -21,21 +21,32 @@
21#include <linux/of.h> 21#include <linux/of.h>
22#include <linux/of_platform.h> 22#include <linux/of_platform.h>
23#include <linux/regulator/machine.h> 23#include <linux/regulator/machine.h>
24#include <linux/platform_data/pinctrl-nomadik.h>
25#include <linux/random.h> 24#include <linux/random.h>
26 25
27#include <asm/pmu.h> 26#include <asm/pmu.h>
28#include <asm/mach/map.h> 27#include <asm/mach/map.h>
29 28
30#include "setup.h" 29#include "setup.h"
31#include "devices.h"
32#include "irqs.h" 30#include "irqs.h"
33 31
34#include "devices-db8500.h" 32#include "board-mop500-regulators.h"
35#include "db8500-regs.h"
36#include "board-mop500.h" 33#include "board-mop500.h"
34#include "db8500-regs.h"
37#include "id.h" 35#include "id.h"
38 36
37struct ab8500_platform_data ab8500_platdata = {
38 .irq_base = MOP500_AB8500_IRQ_BASE,
39 .regulator = &ab8500_regulator_plat_data,
40};
41
42struct prcmu_pdata db8500_prcmu_pdata = {
43 .ab_platdata = &ab8500_platdata,
44 .ab_irq = IRQ_DB8500_AB8500,
45 .irq_base = IRQ_PRCMU_BASE,
46 .version_offset = DB8500_PRCMU_FW_VERSION_OFFSET,
47 .legacy_offset = DB8500_PRCMU_LEGACY_OFFSET,
48};
49
39/* minimum static i/o mapping required to boot U8500 platforms */ 50/* minimum static i/o mapping required to boot U8500 platforms */
40static struct map_desc u8500_uart_io_desc[] __initdata = { 51static struct map_desc u8500_uart_io_desc[] __initdata = {
41 __IO_DEV_DESC(U8500_UART0_BASE, SZ_4K), 52 __IO_DEV_DESC(U8500_UART0_BASE, SZ_4K),
@@ -140,6 +151,10 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
140 /* Requires call-back bindings. */ 151 /* Requires call-back bindings. */
141 OF_DEV_AUXDATA("arm,cortex-a9-pmu", 0, "arm-pmu", &db8500_pmu_platdata), 152 OF_DEV_AUXDATA("arm,cortex-a9-pmu", 0, "arm-pmu", &db8500_pmu_platdata),
142 /* Requires DMA bindings. */ 153 /* Requires DMA bindings. */
154 OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0", &mop500_sdi0_data),
155 OF_DEV_AUXDATA("arm,pl18x", 0x80118000, "sdi1", &mop500_sdi1_data),
156 OF_DEV_AUXDATA("arm,pl18x", 0x80005000, "sdi2", &mop500_sdi2_data),
157 OF_DEV_AUXDATA("arm,pl18x", 0x80114000, "sdi4", &mop500_sdi4_data),
143 OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80123000, 158 OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80123000,
144 "ux500-msp-i2s.0", &msp0_platform_data), 159 "ux500-msp-i2s.0", &msp0_platform_data),
145 OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80124000, 160 OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80124000,
@@ -155,9 +170,6 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
155 OF_DEV_AUXDATA("stericsson,ux500-hash", 0xa03c2000, "hash1", NULL), 170 OF_DEV_AUXDATA("stericsson,ux500-hash", 0xa03c2000, "hash1", NULL),
156 OF_DEV_AUXDATA("stericsson,snd-soc-mop500", 0, "snd-soc-mop500.0", 171 OF_DEV_AUXDATA("stericsson,snd-soc-mop500", 0, "snd-soc-mop500.0",
157 NULL), 172 NULL),
158 /* Requires device name bindings. */
159 OF_DEV_AUXDATA("stericsson,db8500-pinctrl", U8500_PRCMU_BASE,
160 "pinctrl-db8500", NULL),
161 {}, 173 {},
162}; 174};
163 175
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index f84d4397896b..d11ac4bf336c 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -25,7 +25,6 @@
25#include <asm/mach/map.h> 25#include <asm/mach/map.h>
26 26
27#include "setup.h" 27#include "setup.h"
28#include "devices.h"
29 28
30#include "board-mop500.h" 29#include "board-mop500.h"
31#include "db8500-regs.h" 30#include "db8500-regs.h"
@@ -64,12 +63,7 @@ void __init ux500_init_irq(void)
64 } else 63 } else
65 ux500_unknown_soc(); 64 ux500_unknown_soc();
66 65
67#ifdef CONFIG_OF 66 irqchip_init();
68 if (of_have_populated_dt())
69 irqchip_init();
70 else
71#endif
72 gic_init(0, 29, dist_base, cpu_base);
73 67
74 /* 68 /*
75 * Init clocks here so that they are available for system timer 69 * Init clocks here so that they are available for system timer
@@ -79,16 +73,11 @@ void __init ux500_init_irq(void)
79 prcmu_early_init(U8500_PRCMU_BASE, SZ_8K - 1); 73 prcmu_early_init(U8500_PRCMU_BASE, SZ_8K - 1);
80 ux500_pm_init(U8500_PRCMU_BASE, SZ_8K - 1); 74 ux500_pm_init(U8500_PRCMU_BASE, SZ_8K - 1);
81 75
82 if (of_have_populated_dt()) 76 u8500_of_clk_init(U8500_CLKRST1_BASE,
83 u8500_of_clk_init(U8500_CLKRST1_BASE, 77 U8500_CLKRST2_BASE,
84 U8500_CLKRST2_BASE, 78 U8500_CLKRST3_BASE,
85 U8500_CLKRST3_BASE, 79 U8500_CLKRST5_BASE,
86 U8500_CLKRST5_BASE, 80 U8500_CLKRST6_BASE);
87 U8500_CLKRST6_BASE);
88 else
89 u8500_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE,
90 U8500_CLKRST3_BASE, U8500_CLKRST5_BASE,
91 U8500_CLKRST6_BASE);
92 } else if (cpu_is_u9540()) { 81 } else if (cpu_is_u9540()) {
93 prcmu_early_init(U8500_PRCMU_BASE, SZ_8K - 1); 82 prcmu_early_init(U8500_PRCMU_BASE, SZ_8K - 1);
94 ux500_pm_init(U8500_PRCMU_BASE, SZ_8K - 1); 83 ux500_pm_init(U8500_PRCMU_BASE, SZ_8K - 1);
diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c
deleted file mode 100644
index c59f89d058ff..000000000000
--- a/arch/arm/mach-ux500/devices-db8500.c
+++ /dev/null
@@ -1,28 +0,0 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
5 * License terms: GNU General Public License (GPL) version 2
6 */
7
8#include <linux/kernel.h>
9#include <linux/platform_device.h>
10#include <linux/interrupt.h>
11#include <linux/io.h>
12#include <linux/amba/bus.h>
13#include <linux/amba/pl022.h>
14#include <linux/mfd/dbx500-prcmu.h>
15
16#include "setup.h"
17#include "irqs.h"
18
19#include "db8500-regs.h"
20#include "devices-db8500.h"
21
22struct prcmu_pdata db8500_prcmu_pdata = {
23 .ab_platdata = &ab8500_platdata,
24 .ab_irq = IRQ_DB8500_AB8500,
25 .irq_base = IRQ_PRCMU_BASE,
26 .version_offset = DB8500_PRCMU_FW_VERSION_OFFSET,
27 .legacy_offset = DB8500_PRCMU_LEGACY_OFFSET,
28};
diff --git a/arch/arm/mach-ux500/devices-db8500.h b/arch/arm/mach-ux500/devices-db8500.h
deleted file mode 100644
index b8ffc9979bb2..000000000000
--- a/arch/arm/mach-ux500/devices-db8500.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
5 * License terms: GNU General Public License (GPL), version 2.
6 */
7
8#ifndef __DEVICES_DB8500_H
9#define __DEVICES_DB8500_H
10
11#include "irqs.h"
12#include "db8500-regs.h"
13
14struct platform_device;
15
16extern struct ab8500_platform_data ab8500_platdata;
17extern struct prcmu_pdata db8500_prcmu_pdata;
18
19#endif
diff --git a/arch/arm/mach-ux500/devices.c b/arch/arm/mach-ux500/devices.c
deleted file mode 100644
index 0f9e52b95935..000000000000
--- a/arch/arm/mach-ux500/devices.c
+++ /dev/null
@@ -1,26 +0,0 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
5 * License terms: GNU General Public License (GPL) version 2
6 */
7
8#include <linux/kernel.h>
9#include <linux/platform_device.h>
10#include <linux/interrupt.h>
11#include <linux/io.h>
12#include <linux/amba/bus.h>
13
14#include "setup.h"
15
16#include "db8500-regs.h"
17
18void __init amba_add_devices(struct amba_device *devs[], int num)
19{
20 int i;
21
22 for (i = 0; i < num; i++) {
23 struct amba_device *d = devs[i];
24 amba_device_register(d, &iomem_resource);
25 }
26}
diff --git a/arch/arm/mach-ux500/devices.h b/arch/arm/mach-ux500/devices.h
deleted file mode 100644
index 5bca7c605cd6..000000000000
--- a/arch/arm/mach-ux500/devices.h
+++ /dev/null
@@ -1,15 +0,0 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License terms: GNU General Public License (GPL) version 2
5 */
6
7#ifndef __ASM_ARCH_DEVICES_H__
8#define __ASM_ARCH_DEVICES_H__
9
10struct platform_device;
11struct amba_device;
12
13extern struct amba_device ux500_pl031_device;
14
15#endif
diff --git a/arch/arm/mach-ux500/setup.h b/arch/arm/mach-ux500/setup.h
index bdb356498a74..7164cfd99710 100644
--- a/arch/arm/mach-ux500/setup.h
+++ b/arch/arm/mach-ux500/setup.h
@@ -19,17 +19,11 @@
19void ux500_restart(enum reboot_mode mode, const char *cmd); 19void ux500_restart(enum reboot_mode mode, const char *cmd);
20 20
21void __init ux500_map_io(void); 21void __init ux500_map_io(void);
22extern void __init u8500_map_io(void);
23
24extern struct device * __init u8500_init_devices(void);
25 22
26extern void __init ux500_init_irq(void); 23extern void __init ux500_init_irq(void);
27 24
28extern struct device *ux500_soc_device_init(const char *soc_id); 25extern struct device *ux500_soc_device_init(const char *soc_id);
29 26
30struct amba_device;
31extern void __init amba_add_devices(struct amba_device *devs[], int num);
32
33extern void ux500_timer_init(void); 27extern void ux500_timer_init(void);
34 28
35#define __IO_DEV_DESC(x, sz) { \ 29#define __IO_DEV_DESC(x, sz) { \
diff --git a/arch/arm/mach-ux500/timer.c b/arch/arm/mach-ux500/timer.c
index 05a4ff78b3bd..87efda0aa348 100644
--- a/arch/arm/mach-ux500/timer.c
+++ b/arch/arm/mach-ux500/timer.c
@@ -10,40 +10,12 @@
10#include <linux/clocksource.h> 10#include <linux/clocksource.h>
11#include <linux/of.h> 11#include <linux/of.h>
12#include <linux/of_address.h> 12#include <linux/of_address.h>
13#include <linux/platform_data/clocksource-nomadik-mtu.h>
14
15#include <asm/smp_twd.h>
16 13
17#include "setup.h" 14#include "setup.h"
18#include "irqs.h"
19 15
20#include "db8500-regs.h" 16#include "db8500-regs.h"
21#include "id.h" 17#include "id.h"
22 18
23#ifdef CONFIG_HAVE_ARM_TWD
24static DEFINE_TWD_LOCAL_TIMER(u8500_twd_local_timer,
25 U8500_TWD_BASE, IRQ_LOCALTIMER);
26
27static void __init ux500_twd_init(void)
28{
29 struct twd_local_timer *twd_local_timer;
30 int err;
31
32 /* Use this to switch local timer base if changed in new ASICs */
33 twd_local_timer = &u8500_twd_local_timer;
34
35 if (of_have_populated_dt())
36 clocksource_of_init();
37 else {
38 err = twd_local_timer_register(twd_local_timer);
39 if (err)
40 pr_err("twd_local_timer_register failed %d\n", err);
41 }
42}
43#else
44#define ux500_twd_init() do { } while(0)
45#endif
46
47const static struct of_device_id prcmu_timer_of_match[] __initconst = { 19const static struct of_device_id prcmu_timer_of_match[] __initconst = {
48 { .compatible = "stericsson,db8500-prcmu-timer-4", }, 20 { .compatible = "stericsson,db8500-prcmu-timer-4", },
49 { }, 21 { },
@@ -51,54 +23,26 @@ const static struct of_device_id prcmu_timer_of_match[] __initconst = {
51 23
52void __init ux500_timer_init(void) 24void __init ux500_timer_init(void)
53{ 25{
54 void __iomem *mtu_timer_base;
55 void __iomem *prcmu_timer_base; 26 void __iomem *prcmu_timer_base;
56 void __iomem *tmp_base; 27 void __iomem *tmp_base;
57 struct device_node *np; 28 struct device_node *np;
58 29
59 if (cpu_is_u8500_family() || cpu_is_ux540_family()) { 30 if (cpu_is_u8500_family() || cpu_is_ux540_family())
60 mtu_timer_base = __io_address(U8500_MTU0_BASE);
61 prcmu_timer_base = __io_address(U8500_PRCMU_TIMER_4_BASE); 31 prcmu_timer_base = __io_address(U8500_PRCMU_TIMER_4_BASE);
62 } else { 32 else
63 ux500_unknown_soc(); 33 ux500_unknown_soc();
64 }
65 34
66 /* TODO: Once MTU has been DT:ed place code above into else. */ 35 np = of_find_matching_node(NULL, prcmu_timer_of_match);
67 if (of_have_populated_dt()) { 36 if (!np)
68#ifdef CONFIG_OF 37 goto dt_fail;
69 np = of_find_matching_node(NULL, prcmu_timer_of_match);
70 if (!np)
71#endif
72 goto dt_fail;
73 38
74 tmp_base = of_iomap(np, 0); 39 tmp_base = of_iomap(np, 0);
75 if (!tmp_base) 40 if (!tmp_base)
76 goto dt_fail; 41 goto dt_fail;
77 42
78 prcmu_timer_base = tmp_base; 43 prcmu_timer_base = tmp_base;
79 }
80 44
81dt_fail: 45dt_fail:
82 /* Doing it the old fashioned way. */
83
84 /*
85 * Here we register the timerblocks active in the system.
86 * Localtimers (twd) is started when both cpu is up and running.
87 * MTU register a clocksource, clockevent and sched_clock.
88 * Since the MTU is located in the VAPE power domain
89 * it will be cleared in sleep which makes it unsuitable.
90 * We however need it as a timer tick (clockevent)
91 * during boot to calibrate delay until twd is started.
92 * RTC-RTT have problems as timer tick during boot since it is
93 * depending on delay which is not yet calibrated. RTC-RTT is in the
94 * always-on powerdomain and is used as clockevent instead of twd when
95 * sleeping.
96 * The PRCMU timer 4 register a clocksource and
97 * sched_clock with higher rating then MTU since is always-on.
98 *
99 */
100 if (!of_have_populated_dt())
101 nmdk_timer_init(mtu_timer_base, IRQ_MTU0);
102 clksrc_dbx500_prcmu_init(prcmu_timer_base); 46 clksrc_dbx500_prcmu_init(prcmu_timer_base);
103 ux500_twd_init(); 47 clocksource_of_init();
104} 48}
diff --git a/arch/arm/mach-vexpress/spc.c b/arch/arm/mach-vexpress/spc.c
index 033d34dcbd3f..c26ef5b92ca7 100644
--- a/arch/arm/mach-vexpress/spc.c
+++ b/arch/arm/mach-vexpress/spc.c
@@ -53,6 +53,11 @@
53#define A15_BX_ADDR0 0x68 53#define A15_BX_ADDR0 0x68
54#define A7_BX_ADDR0 0x78 54#define A7_BX_ADDR0 0x78
55 55
56/* SPC CPU/cluster reset statue */
57#define STANDBYWFI_STAT 0x3c
58#define STANDBYWFI_STAT_A15_CPU_MASK(cpu) (1 << (cpu))
59#define STANDBYWFI_STAT_A7_CPU_MASK(cpu) (1 << (3 + (cpu)))
60
56/* SPC system config interface registers */ 61/* SPC system config interface registers */
57#define SYSCFG_WDATA 0x70 62#define SYSCFG_WDATA 0x70
58#define SYSCFG_RDATA 0x74 63#define SYSCFG_RDATA 0x74
@@ -213,6 +218,41 @@ void ve_spc_powerdown(u32 cluster, bool enable)
213 writel_relaxed(enable, info->baseaddr + pwdrn_reg); 218 writel_relaxed(enable, info->baseaddr + pwdrn_reg);
214} 219}
215 220
221static u32 standbywfi_cpu_mask(u32 cpu, u32 cluster)
222{
223 return cluster_is_a15(cluster) ?
224 STANDBYWFI_STAT_A15_CPU_MASK(cpu)
225 : STANDBYWFI_STAT_A7_CPU_MASK(cpu);
226}
227
228/**
229 * ve_spc_cpu_in_wfi(u32 cpu, u32 cluster)
230 *
231 * @cpu: mpidr[7:0] bitfield describing CPU affinity level within cluster
232 * @cluster: mpidr[15:8] bitfield describing cluster affinity level
233 *
234 * @return: non-zero if and only if the specified CPU is in WFI
235 *
236 * Take care when interpreting the result of this function: a CPU might
237 * be in WFI temporarily due to idle, and is not necessarily safely
238 * parked.
239 */
240int ve_spc_cpu_in_wfi(u32 cpu, u32 cluster)
241{
242 int ret;
243 u32 mask = standbywfi_cpu_mask(cpu, cluster);
244
245 if (cluster >= MAX_CLUSTERS)
246 return 1;
247
248 ret = readl_relaxed(info->baseaddr + STANDBYWFI_STAT);
249
250 pr_debug("%s: PCFGREG[0x%X] = 0x%08X, mask = 0x%X\n",
251 __func__, STANDBYWFI_STAT, ret, mask);
252
253 return ret & mask;
254}
255
216static int ve_spc_get_performance(int cluster, u32 *freq) 256static int ve_spc_get_performance(int cluster, u32 *freq)
217{ 257{
218 struct ve_spc_opp *opps = info->opps[cluster]; 258 struct ve_spc_opp *opps = info->opps[cluster];
diff --git a/arch/arm/mach-vexpress/spc.h b/arch/arm/mach-vexpress/spc.h
index dbd44c3720f9..793d065243b9 100644
--- a/arch/arm/mach-vexpress/spc.h
+++ b/arch/arm/mach-vexpress/spc.h
@@ -20,5 +20,6 @@ void ve_spc_global_wakeup_irq(bool set);
20void ve_spc_cpu_wakeup_irq(u32 cluster, u32 cpu, bool set); 20void ve_spc_cpu_wakeup_irq(u32 cluster, u32 cpu, bool set);
21void ve_spc_set_resume_addr(u32 cluster, u32 cpu, u32 addr); 21void ve_spc_set_resume_addr(u32 cluster, u32 cpu, u32 addr);
22void ve_spc_powerdown(u32 cluster, bool enable); 22void ve_spc_powerdown(u32 cluster, bool enable);
23int ve_spc_cpu_in_wfi(u32 cpu, u32 cluster);
23 24
24#endif 25#endif
diff --git a/arch/arm/mach-vexpress/tc2_pm.c b/arch/arm/mach-vexpress/tc2_pm.c
index 05a364c5077a..29e7785a54bc 100644
--- a/arch/arm/mach-vexpress/tc2_pm.c
+++ b/arch/arm/mach-vexpress/tc2_pm.c
@@ -12,6 +12,7 @@
12 * published by the Free Software Foundation. 12 * published by the Free Software Foundation.
13 */ 13 */
14 14
15#include <linux/delay.h>
15#include <linux/init.h> 16#include <linux/init.h>
16#include <linux/io.h> 17#include <linux/io.h>
17#include <linux/kernel.h> 18#include <linux/kernel.h>
@@ -32,11 +33,17 @@
32#include "spc.h" 33#include "spc.h"
33 34
34/* SCC conf registers */ 35/* SCC conf registers */
36#define RESET_CTRL 0x018
37#define RESET_A15_NCORERESET(cpu) (1 << (2 + (cpu)))
38#define RESET_A7_NCORERESET(cpu) (1 << (16 + (cpu)))
39
35#define A15_CONF 0x400 40#define A15_CONF 0x400
36#define A7_CONF 0x500 41#define A7_CONF 0x500
37#define SYS_INFO 0x700 42#define SYS_INFO 0x700
38#define SPC_BASE 0xb00 43#define SPC_BASE 0xb00
39 44
45static void __iomem *scc;
46
40/* 47/*
41 * We can't use regular spinlocks. In the switcher case, it is possible 48 * We can't use regular spinlocks. In the switcher case, it is possible
42 * for an outbound CPU to call power_down() after its inbound counterpart 49 * for an outbound CPU to call power_down() after its inbound counterpart
@@ -190,6 +197,55 @@ static void tc2_pm_power_down(void)
190 tc2_pm_down(0); 197 tc2_pm_down(0);
191} 198}
192 199
200static int tc2_core_in_reset(unsigned int cpu, unsigned int cluster)
201{
202 u32 mask = cluster ?
203 RESET_A7_NCORERESET(cpu)
204 : RESET_A15_NCORERESET(cpu);
205
206 return !(readl_relaxed(scc + RESET_CTRL) & mask);
207}
208
209#define POLL_MSEC 10
210#define TIMEOUT_MSEC 1000
211
212static int tc2_pm_power_down_finish(unsigned int cpu, unsigned int cluster)
213{
214 unsigned tries;
215
216 pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
217 BUG_ON(cluster >= TC2_CLUSTERS || cpu >= TC2_MAX_CPUS_PER_CLUSTER);
218
219 for (tries = 0; tries < TIMEOUT_MSEC / POLL_MSEC; ++tries) {
220 /*
221 * Only examine the hardware state if the target CPU has
222 * caught up at least as far as tc2_pm_down():
223 */
224 if (ACCESS_ONCE(tc2_pm_use_count[cpu][cluster]) == 0) {
225 pr_debug("%s(cpu=%u, cluster=%u): RESET_CTRL = 0x%08X\n",
226 __func__, cpu, cluster,
227 readl_relaxed(scc + RESET_CTRL));
228
229 /*
230 * We need the CPU to reach WFI, but the power
231 * controller may put the cluster in reset and
232 * power it off as soon as that happens, before
233 * we have a chance to see STANDBYWFI.
234 *
235 * So we need to check for both conditions:
236 */
237 if (tc2_core_in_reset(cpu, cluster) ||
238 ve_spc_cpu_in_wfi(cpu, cluster))
239 return 0; /* success: the CPU is halted */
240 }
241
242 /* Otherwise, wait and retry: */
243 msleep(POLL_MSEC);
244 }
245
246 return -ETIMEDOUT; /* timeout */
247}
248
193static void tc2_pm_suspend(u64 residency) 249static void tc2_pm_suspend(u64 residency)
194{ 250{
195 unsigned int mpidr, cpu, cluster; 251 unsigned int mpidr, cpu, cluster;
@@ -232,10 +288,11 @@ static void tc2_pm_powered_up(void)
232} 288}
233 289
234static const struct mcpm_platform_ops tc2_pm_power_ops = { 290static const struct mcpm_platform_ops tc2_pm_power_ops = {
235 .power_up = tc2_pm_power_up, 291 .power_up = tc2_pm_power_up,
236 .power_down = tc2_pm_power_down, 292 .power_down = tc2_pm_power_down,
237 .suspend = tc2_pm_suspend, 293 .power_down_finish = tc2_pm_power_down_finish,
238 .powered_up = tc2_pm_powered_up, 294 .suspend = tc2_pm_suspend,
295 .powered_up = tc2_pm_powered_up,
239}; 296};
240 297
241static bool __init tc2_pm_usage_count_init(void) 298static bool __init tc2_pm_usage_count_init(void)
@@ -269,7 +326,6 @@ static void __naked tc2_pm_power_up_setup(unsigned int affinity_level)
269static int __init tc2_pm_init(void) 326static int __init tc2_pm_init(void)
270{ 327{
271 int ret, irq; 328 int ret, irq;
272 void __iomem *scc;
273 u32 a15_cluster_id, a7_cluster_id, sys_info; 329 u32 a15_cluster_id, a7_cluster_id, sys_info;
274 struct device_node *np; 330 struct device_node *np;
275 331
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 79f8b39801a8..f6b6bfa88ecf 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -9,6 +9,7 @@
9 * 9 *
10 * DMA uncached mapping support. 10 * DMA uncached mapping support.
11 */ 11 */
12#include <linux/bootmem.h>
12#include <linux/module.h> 13#include <linux/module.h>
13#include <linux/mm.h> 14#include <linux/mm.h>
14#include <linux/gfp.h> 15#include <linux/gfp.h>
@@ -162,6 +163,8 @@ static u64 get_coherent_dma_mask(struct device *dev)
162 u64 mask = (u64)DMA_BIT_MASK(32); 163 u64 mask = (u64)DMA_BIT_MASK(32);
163 164
164 if (dev) { 165 if (dev) {
166 unsigned long max_dma_pfn;
167
165 mask = dev->coherent_dma_mask; 168 mask = dev->coherent_dma_mask;
166 169
167 /* 170 /*
@@ -173,6 +176,8 @@ static u64 get_coherent_dma_mask(struct device *dev)
173 return 0; 176 return 0;
174 } 177 }
175 178
179 max_dma_pfn = min(max_pfn, arm_dma_pfn_limit);
180
176 /* 181 /*
177 * If the mask allows for more memory than we can address, 182 * If the mask allows for more memory than we can address,
178 * and we actually have that much memory, then fail the 183 * and we actually have that much memory, then fail the
@@ -180,7 +185,7 @@ static u64 get_coherent_dma_mask(struct device *dev)
180 */ 185 */
181 if (sizeof(mask) != sizeof(dma_addr_t) && 186 if (sizeof(mask) != sizeof(dma_addr_t) &&
182 mask > (dma_addr_t)~0 && 187 mask > (dma_addr_t)~0 &&
183 dma_to_pfn(dev, ~0) > arm_dma_pfn_limit) { 188 dma_to_pfn(dev, ~0) > max_dma_pfn) {
184 dev_warn(dev, "Coherent DMA mask %#llx is larger than dma_addr_t allows\n", 189 dev_warn(dev, "Coherent DMA mask %#llx is larger than dma_addr_t allows\n",
185 mask); 190 mask);
186 dev_warn(dev, "Driver did not use or check the return value from dma_set_coherent_mask()?\n"); 191 dev_warn(dev, "Driver did not use or check the return value from dma_set_coherent_mask()?\n");
@@ -192,7 +197,7 @@ static u64 get_coherent_dma_mask(struct device *dev)
192 * fits within the allowable addresses which we can 197 * fits within the allowable addresses which we can
193 * allocate. 198 * allocate.
194 */ 199 */
195 if (dma_to_pfn(dev, mask) < arm_dma_pfn_limit) { 200 if (dma_to_pfn(dev, mask) < max_dma_pfn) {
196 dev_warn(dev, "Coherent DMA mask %#llx (pfn %#lx-%#lx) covers a smaller range of system memory than the DMA zone pfn 0x0-%#lx\n", 201 dev_warn(dev, "Coherent DMA mask %#llx (pfn %#lx-%#lx) covers a smaller range of system memory than the DMA zone pfn 0x0-%#lx\n",
197 mask, 202 mask,
198 dma_to_pfn(dev, 0), dma_to_pfn(dev, mask) + 1, 203 dma_to_pfn(dev, 0), dma_to_pfn(dev, mask) + 1,
diff --git a/arch/arm/mm/mmap.c b/arch/arm/mm/mmap.c
index d27158c38eb0..5e85ed371364 100644
--- a/arch/arm/mm/mmap.c
+++ b/arch/arm/mm/mmap.c
@@ -146,7 +146,7 @@ arch_get_unmapped_area_topdown(struct file *filp, const unsigned long addr0,
146 146
147 info.flags = VM_UNMAPPED_AREA_TOPDOWN; 147 info.flags = VM_UNMAPPED_AREA_TOPDOWN;
148 info.length = len; 148 info.length = len;
149 info.low_limit = PAGE_SIZE; 149 info.low_limit = FIRST_USER_ADDRESS;
150 info.high_limit = mm->mmap_base; 150 info.high_limit = mm->mmap_base;
151 info.align_mask = do_align ? (PAGE_MASK & (SHMLBA - 1)) : 0; 151 info.align_mask = do_align ? (PAGE_MASK & (SHMLBA - 1)) : 0;
152 info.align_offset = pgoff << PAGE_SHIFT; 152 info.align_offset = pgoff << PAGE_SHIFT;
diff --git a/arch/arm/mm/pgd.c b/arch/arm/mm/pgd.c
index 0acb089d0f70..1046b373d1ae 100644
--- a/arch/arm/mm/pgd.c
+++ b/arch/arm/mm/pgd.c
@@ -87,7 +87,8 @@ pgd_t *pgd_alloc(struct mm_struct *mm)
87 init_pud = pud_offset(init_pgd, 0); 87 init_pud = pud_offset(init_pgd, 0);
88 init_pmd = pmd_offset(init_pud, 0); 88 init_pmd = pmd_offset(init_pud, 0);
89 init_pte = pte_offset_map(init_pmd, 0); 89 init_pte = pte_offset_map(init_pmd, 0);
90 set_pte_ext(new_pte, *init_pte, 0); 90 set_pte_ext(new_pte + 0, init_pte[0], 0);
91 set_pte_ext(new_pte + 1, init_pte[1], 0);
91 pte_unmap(init_pte); 92 pte_unmap(init_pte);
92 pte_unmap(new_pte); 93 pte_unmap(new_pte);
93 } 94 }
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index fb92abb91628..2861b155485a 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -336,8 +336,11 @@ static inline void __omap_dm_timer_enable_posted(struct omap_dm_timer *timer)
336 if (timer->posted) 336 if (timer->posted)
337 return; 337 return;
338 338
339 if (timer->errata & OMAP_TIMER_ERRATA_I103_I767) 339 if (timer->errata & OMAP_TIMER_ERRATA_I103_I767) {
340 timer->posted = OMAP_TIMER_NONPOSTED;
341 __omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG, 0, 0);
340 return; 342 return;
343 }
341 344
342 __omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG, 345 __omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG,
343 OMAP_TIMER_CTRL_POSTED, 0); 346 OMAP_TIMER_CTRL_POSTED, 0);
diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c
index c66d163d7a2a..830ff07f3385 100644
--- a/arch/arm/plat-orion/common.c
+++ b/arch/arm/plat-orion/common.c
@@ -22,6 +22,7 @@
22#include <linux/platform_data/dma-mv_xor.h> 22#include <linux/platform_data/dma-mv_xor.h>
23#include <linux/platform_data/usb-ehci-orion.h> 23#include <linux/platform_data/usb-ehci-orion.h>
24#include <mach/bridge-regs.h> 24#include <mach/bridge-regs.h>
25#include <plat/common.h>
25 26
26/* Create a clkdev entry for a given device/clk */ 27/* Create a clkdev entry for a given device/clk */
27void __init orion_clkdev_add(const char *con_id, const char *dev_id, 28void __init orion_clkdev_add(const char *con_id, const char *dev_id,
@@ -256,7 +257,7 @@ static __init void ge_complete(
256/***************************************************************************** 257/*****************************************************************************
257 * GE00 258 * GE00
258 ****************************************************************************/ 259 ****************************************************************************/
259struct mv643xx_eth_shared_platform_data orion_ge00_shared_data; 260static struct mv643xx_eth_shared_platform_data orion_ge00_shared_data;
260 261
261static struct resource orion_ge00_shared_resources[] = { 262static struct resource orion_ge00_shared_resources[] = {
262 { 263 {
@@ -322,7 +323,7 @@ void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data,
322/***************************************************************************** 323/*****************************************************************************
323 * GE01 324 * GE01
324 ****************************************************************************/ 325 ****************************************************************************/
325struct mv643xx_eth_shared_platform_data orion_ge01_shared_data; 326static struct mv643xx_eth_shared_platform_data orion_ge01_shared_data;
326 327
327static struct resource orion_ge01_shared_resources[] = { 328static struct resource orion_ge01_shared_resources[] = {
328 { 329 {
@@ -373,7 +374,7 @@ void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data,
373/***************************************************************************** 374/*****************************************************************************
374 * GE10 375 * GE10
375 ****************************************************************************/ 376 ****************************************************************************/
376struct mv643xx_eth_shared_platform_data orion_ge10_shared_data; 377static struct mv643xx_eth_shared_platform_data orion_ge10_shared_data;
377 378
378static struct resource orion_ge10_shared_resources[] = { 379static struct resource orion_ge10_shared_resources[] = {
379 { 380 {
@@ -422,7 +423,7 @@ void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data,
422/***************************************************************************** 423/*****************************************************************************
423 * GE11 424 * GE11
424 ****************************************************************************/ 425 ****************************************************************************/
425struct mv643xx_eth_shared_platform_data orion_ge11_shared_data; 426static struct mv643xx_eth_shared_platform_data orion_ge11_shared_data;
426 427
427static struct resource orion_ge11_shared_resources[] = { 428static struct resource orion_ge11_shared_resources[] = {
428 { 429 {
diff --git a/arch/arm/plat-orion/time.c b/arch/arm/plat-orion/time.c
index 9d2b2ac74938..15921a1839d7 100644
--- a/arch/arm/plat-orion/time.c
+++ b/arch/arm/plat-orion/time.c
@@ -17,6 +17,7 @@
17#include <linux/interrupt.h> 17#include <linux/interrupt.h>
18#include <linux/irq.h> 18#include <linux/irq.h>
19#include <linux/sched_clock.h> 19#include <linux/sched_clock.h>
20#include <plat/time.h>
20 21
21/* 22/*
22 * MBus bridge block registers. 23 * MBus bridge block registers.
@@ -174,7 +175,7 @@ static irqreturn_t orion_timer_interrupt(int irq, void *dev_id)
174 175
175static struct irqaction orion_timer_irq = { 176static struct irqaction orion_timer_irq = {
176 .name = "orion_tick", 177 .name = "orion_tick",
177 .flags = IRQF_DISABLED | IRQF_TIMER, 178 .flags = IRQF_TIMER,
178 .handler = orion_timer_interrupt 179 .handler = orion_timer_interrupt
179}; 180};
180 181
diff --git a/arch/arm/plat-samsung/include/plat/uncompress.h b/arch/arm/plat-samsung/include/plat/uncompress.h
index 4afc32f90b6d..f48dc0a4736c 100644
--- a/arch/arm/plat-samsung/include/plat/uncompress.h
+++ b/arch/arm/plat-samsung/include/plat/uncompress.h
@@ -145,6 +145,8 @@ static inline void arch_enable_uart_fifo(void)
145 if (!(fifocon & S3C2410_UFCON_RESETBOTH)) 145 if (!(fifocon & S3C2410_UFCON_RESETBOTH))
146 break; 146 break;
147 } 147 }
148
149 uart_wr(S3C2410_UFCON, S3C2410_UFCON_FIFOMODE);
148 } 150 }
149} 151}
150#else 152#else
diff --git a/arch/arm/xen/p2m.c b/arch/arm/xen/p2m.c
index 23732cdff551..b31ee1b275b0 100644
--- a/arch/arm/xen/p2m.c
+++ b/arch/arm/xen/p2m.c
@@ -25,8 +25,9 @@ struct xen_p2m_entry {
25 struct rb_node rbnode_phys; 25 struct rb_node rbnode_phys;
26}; 26};
27 27
28rwlock_t p2m_lock; 28static rwlock_t p2m_lock;
29struct rb_root phys_to_mach = RB_ROOT; 29struct rb_root phys_to_mach = RB_ROOT;
30EXPORT_SYMBOL_GPL(phys_to_mach);
30static struct rb_root mach_to_phys = RB_ROOT; 31static struct rb_root mach_to_phys = RB_ROOT;
31 32
32static int xen_add_phys_to_mach_entry(struct xen_p2m_entry *new) 33static int xen_add_phys_to_mach_entry(struct xen_p2m_entry *new)
@@ -200,7 +201,7 @@ bool __set_phys_to_machine(unsigned long pfn, unsigned long mfn)
200} 201}
201EXPORT_SYMBOL_GPL(__set_phys_to_machine); 202EXPORT_SYMBOL_GPL(__set_phys_to_machine);
202 203
203int p2m_init(void) 204static int p2m_init(void)
204{ 205{
205 rwlock_init(&p2m_lock); 206 rwlock_init(&p2m_lock);
206 return 0; 207 return 0;
diff --git a/arch/arm64/boot/dts/foundation-v8.dts b/arch/arm64/boot/dts/foundation-v8.dts
index 84fcc5018284..519c4b2c0687 100644
--- a/arch/arm64/boot/dts/foundation-v8.dts
+++ b/arch/arm64/boot/dts/foundation-v8.dts
@@ -6,6 +6,8 @@
6 6
7/dts-v1/; 7/dts-v1/;
8 8
9/memreserve/ 0x80000000 0x00010000;
10
9/ { 11/ {
10 model = "Foundation-v8A"; 12 model = "Foundation-v8A";
11 compatible = "arm,foundation-aarch64", "arm,vexpress"; 13 compatible = "arm,foundation-aarch64", "arm,vexpress";
diff --git a/arch/arm64/include/asm/irqflags.h b/arch/arm64/include/asm/irqflags.h
index aa11943b8502..b2fcfbc51ecc 100644
--- a/arch/arm64/include/asm/irqflags.h
+++ b/arch/arm64/include/asm/irqflags.h
@@ -56,6 +56,9 @@ static inline void arch_local_irq_disable(void)
56#define local_fiq_enable() asm("msr daifclr, #1" : : : "memory") 56#define local_fiq_enable() asm("msr daifclr, #1" : : : "memory")
57#define local_fiq_disable() asm("msr daifset, #1" : : : "memory") 57#define local_fiq_disable() asm("msr daifset, #1" : : : "memory")
58 58
59#define local_async_enable() asm("msr daifclr, #4" : : : "memory")
60#define local_async_disable() asm("msr daifset, #4" : : : "memory")
61
59/* 62/*
60 * Save the current interrupt enable state. 63 * Save the current interrupt enable state.
61 */ 64 */
diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
index 17bd3af0a117..7f2b60affbb4 100644
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -25,10 +25,11 @@
25 * Software defined PTE bits definition. 25 * Software defined PTE bits definition.
26 */ 26 */
27#define PTE_VALID (_AT(pteval_t, 1) << 0) 27#define PTE_VALID (_AT(pteval_t, 1) << 0)
28#define PTE_PROT_NONE (_AT(pteval_t, 1) << 2) /* only when !PTE_VALID */ 28#define PTE_FILE (_AT(pteval_t, 1) << 2) /* only when !pte_present() */
29#define PTE_FILE (_AT(pteval_t, 1) << 3) /* only when !pte_present() */
30#define PTE_DIRTY (_AT(pteval_t, 1) << 55) 29#define PTE_DIRTY (_AT(pteval_t, 1) << 55)
31#define PTE_SPECIAL (_AT(pteval_t, 1) << 56) 30#define PTE_SPECIAL (_AT(pteval_t, 1) << 56)
31 /* bit 57 for PMD_SECT_SPLITTING */
32#define PTE_PROT_NONE (_AT(pteval_t, 1) << 58) /* only when !PTE_VALID */
32 33
33/* 34/*
34 * VMALLOC and SPARSEMEM_VMEMMAP ranges. 35 * VMALLOC and SPARSEMEM_VMEMMAP ranges.
@@ -254,7 +255,7 @@ static inline int has_transparent_hugepage(void)
254#define pgprot_noncached(prot) \ 255#define pgprot_noncached(prot) \
255 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE)) 256 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE))
256#define pgprot_writecombine(prot) \ 257#define pgprot_writecombine(prot) \
257 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_GRE)) 258 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC))
258#define pgprot_dmacoherent(prot) \ 259#define pgprot_dmacoherent(prot) \
259 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC)) 260 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC))
260#define __HAVE_PHYS_MEM_ACCESS_PROT 261#define __HAVE_PHYS_MEM_ACCESS_PROT
@@ -357,18 +358,20 @@ extern pgd_t idmap_pg_dir[PTRS_PER_PGD];
357 358
358/* 359/*
359 * Encode and decode a swap entry: 360 * Encode and decode a swap entry:
360 * bits 0, 2: present (must both be zero) 361 * bits 0-1: present (must be zero)
361 * bit 3: PTE_FILE 362 * bit 2: PTE_FILE
362 * bits 4-8: swap type 363 * bits 3-8: swap type
363 * bits 9-63: swap offset 364 * bits 9-57: swap offset
364 */ 365 */
365#define __SWP_TYPE_SHIFT 4 366#define __SWP_TYPE_SHIFT 3
366#define __SWP_TYPE_BITS 6 367#define __SWP_TYPE_BITS 6
368#define __SWP_OFFSET_BITS 49
367#define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1) 369#define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1)
368#define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) 370#define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT)
371#define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1)
369 372
370#define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) 373#define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK)
371#define __swp_offset(x) ((x).val >> __SWP_OFFSET_SHIFT) 374#define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK)
372#define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) 375#define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) })
373 376
374#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 377#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
@@ -382,15 +385,15 @@ extern pgd_t idmap_pg_dir[PTRS_PER_PGD];
382 385
383/* 386/*
384 * Encode and decode a file entry: 387 * Encode and decode a file entry:
385 * bits 0, 2: present (must both be zero) 388 * bits 0-1: present (must be zero)
386 * bit 3: PTE_FILE 389 * bit 2: PTE_FILE
387 * bits 4-63: file offset / PAGE_SIZE 390 * bits 3-57: file offset / PAGE_SIZE
388 */ 391 */
389#define pte_file(pte) (pte_val(pte) & PTE_FILE) 392#define pte_file(pte) (pte_val(pte) & PTE_FILE)
390#define pte_to_pgoff(x) (pte_val(x) >> 4) 393#define pte_to_pgoff(x) (pte_val(x) >> 3)
391#define pgoff_to_pte(x) __pte(((x) << 4) | PTE_FILE) 394#define pgoff_to_pte(x) __pte(((x) << 3) | PTE_FILE)
392 395
393#define PTE_FILE_MAX_BITS 60 396#define PTE_FILE_MAX_BITS 55
394 397
395extern int kern_addr_valid(unsigned long addr); 398extern int kern_addr_valid(unsigned long addr);
396 399
diff --git a/arch/arm64/kernel/debug-monitors.c b/arch/arm64/kernel/debug-monitors.c
index 6a0a9b132d7a..4ae68579031d 100644
--- a/arch/arm64/kernel/debug-monitors.c
+++ b/arch/arm64/kernel/debug-monitors.c
@@ -248,7 +248,8 @@ static int brk_handler(unsigned long addr, unsigned int esr,
248int aarch32_break_handler(struct pt_regs *regs) 248int aarch32_break_handler(struct pt_regs *regs)
249{ 249{
250 siginfo_t info; 250 siginfo_t info;
251 unsigned int instr; 251 u32 arm_instr;
252 u16 thumb_instr;
252 bool bp = false; 253 bool bp = false;
253 void __user *pc = (void __user *)instruction_pointer(regs); 254 void __user *pc = (void __user *)instruction_pointer(regs);
254 255
@@ -257,18 +258,21 @@ int aarch32_break_handler(struct pt_regs *regs)
257 258
258 if (compat_thumb_mode(regs)) { 259 if (compat_thumb_mode(regs)) {
259 /* get 16-bit Thumb instruction */ 260 /* get 16-bit Thumb instruction */
260 get_user(instr, (u16 __user *)pc); 261 get_user(thumb_instr, (u16 __user *)pc);
261 if (instr == AARCH32_BREAK_THUMB2_LO) { 262 thumb_instr = le16_to_cpu(thumb_instr);
263 if (thumb_instr == AARCH32_BREAK_THUMB2_LO) {
262 /* get second half of 32-bit Thumb-2 instruction */ 264 /* get second half of 32-bit Thumb-2 instruction */
263 get_user(instr, (u16 __user *)(pc + 2)); 265 get_user(thumb_instr, (u16 __user *)(pc + 2));
264 bp = instr == AARCH32_BREAK_THUMB2_HI; 266 thumb_instr = le16_to_cpu(thumb_instr);
267 bp = thumb_instr == AARCH32_BREAK_THUMB2_HI;
265 } else { 268 } else {
266 bp = instr == AARCH32_BREAK_THUMB; 269 bp = thumb_instr == AARCH32_BREAK_THUMB;
267 } 270 }
268 } else { 271 } else {
269 /* 32-bit ARM instruction */ 272 /* 32-bit ARM instruction */
270 get_user(instr, (u32 __user *)pc); 273 get_user(arm_instr, (u32 __user *)pc);
271 bp = (instr & ~0xf0000000) == AARCH32_BREAK_ARM; 274 arm_instr = le32_to_cpu(arm_instr);
275 bp = (arm_instr & ~0xf0000000) == AARCH32_BREAK_ARM;
272 } 276 }
273 277
274 if (!bp) 278 if (!bp)
diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S
index e1166145ca29..4d2c6f3f0c41 100644
--- a/arch/arm64/kernel/entry.S
+++ b/arch/arm64/kernel/entry.S
@@ -309,15 +309,12 @@ el1_irq:
309#ifdef CONFIG_TRACE_IRQFLAGS 309#ifdef CONFIG_TRACE_IRQFLAGS
310 bl trace_hardirqs_off 310 bl trace_hardirqs_off
311#endif 311#endif
312#ifdef CONFIG_PREEMPT 312
313 get_thread_info tsk
314 ldr w24, [tsk, #TI_PREEMPT] // get preempt count
315 add w0, w24, #1 // increment it
316 str w0, [tsk, #TI_PREEMPT]
317#endif
318 irq_handler 313 irq_handler
314
319#ifdef CONFIG_PREEMPT 315#ifdef CONFIG_PREEMPT
320 str w24, [tsk, #TI_PREEMPT] // restore preempt count 316 get_thread_info tsk
317 ldr w24, [tsk, #TI_PREEMPT] // restore preempt count
321 cbnz w24, 1f // preempt count != 0 318 cbnz w24, 1f // preempt count != 0
322 ldr x0, [tsk, #TI_FLAGS] // get flags 319 ldr x0, [tsk, #TI_FLAGS] // get flags
323 tbz x0, #TIF_NEED_RESCHED, 1f // needs rescheduling? 320 tbz x0, #TIF_NEED_RESCHED, 1f // needs rescheduling?
@@ -507,22 +504,10 @@ el0_irq_naked:
507#ifdef CONFIG_TRACE_IRQFLAGS 504#ifdef CONFIG_TRACE_IRQFLAGS
508 bl trace_hardirqs_off 505 bl trace_hardirqs_off
509#endif 506#endif
510 get_thread_info tsk 507
511#ifdef CONFIG_PREEMPT
512 ldr w24, [tsk, #TI_PREEMPT] // get preempt count
513 add w23, w24, #1 // increment it
514 str w23, [tsk, #TI_PREEMPT]
515#endif
516 irq_handler 508 irq_handler
517#ifdef CONFIG_PREEMPT 509 get_thread_info tsk
518 ldr w0, [tsk, #TI_PREEMPT] 510
519 str w24, [tsk, #TI_PREEMPT]
520 cmp w0, w23
521 b.eq 1f
522 mov x1, #0
523 str x1, [x1] // BUG
5241:
525#endif
526#ifdef CONFIG_TRACE_IRQFLAGS 511#ifdef CONFIG_TRACE_IRQFLAGS
527 bl trace_hardirqs_on 512 bl trace_hardirqs_on
528#endif 513#endif
diff --git a/arch/arm64/kernel/ptrace.c b/arch/arm64/kernel/ptrace.c
index fecdbf7de82e..6777a2192b83 100644
--- a/arch/arm64/kernel/ptrace.c
+++ b/arch/arm64/kernel/ptrace.c
@@ -636,28 +636,27 @@ static int compat_gpr_get(struct task_struct *target,
636 636
637 for (i = 0; i < num_regs; ++i) { 637 for (i = 0; i < num_regs; ++i) {
638 unsigned int idx = start + i; 638 unsigned int idx = start + i;
639 void *reg; 639 compat_ulong_t reg;
640 640
641 switch (idx) { 641 switch (idx) {
642 case 15: 642 case 15:
643 reg = (void *)&task_pt_regs(target)->pc; 643 reg = task_pt_regs(target)->pc;
644 break; 644 break;
645 case 16: 645 case 16:
646 reg = (void *)&task_pt_regs(target)->pstate; 646 reg = task_pt_regs(target)->pstate;
647 break; 647 break;
648 case 17: 648 case 17:
649 reg = (void *)&task_pt_regs(target)->orig_x0; 649 reg = task_pt_regs(target)->orig_x0;
650 break; 650 break;
651 default: 651 default:
652 reg = (void *)&task_pt_regs(target)->regs[idx]; 652 reg = task_pt_regs(target)->regs[idx];
653 } 653 }
654 654
655 ret = copy_to_user(ubuf, reg, sizeof(compat_ulong_t)); 655 ret = copy_to_user(ubuf, &reg, sizeof(reg));
656
657 if (ret) 656 if (ret)
658 break; 657 break;
659 else 658
660 ubuf += sizeof(compat_ulong_t); 659 ubuf += sizeof(reg);
661 } 660 }
662 661
663 return ret; 662 return ret;
@@ -685,28 +684,28 @@ static int compat_gpr_set(struct task_struct *target,
685 684
686 for (i = 0; i < num_regs; ++i) { 685 for (i = 0; i < num_regs; ++i) {
687 unsigned int idx = start + i; 686 unsigned int idx = start + i;
688 void *reg; 687 compat_ulong_t reg;
688
689 ret = copy_from_user(&reg, ubuf, sizeof(reg));
690 if (ret)
691 return ret;
692
693 ubuf += sizeof(reg);
689 694
690 switch (idx) { 695 switch (idx) {
691 case 15: 696 case 15:
692 reg = (void *)&newregs.pc; 697 newregs.pc = reg;
693 break; 698 break;
694 case 16: 699 case 16:
695 reg = (void *)&newregs.pstate; 700 newregs.pstate = reg;
696 break; 701 break;
697 case 17: 702 case 17:
698 reg = (void *)&newregs.orig_x0; 703 newregs.orig_x0 = reg;
699 break; 704 break;
700 default: 705 default:
701 reg = (void *)&newregs.regs[idx]; 706 newregs.regs[idx] = reg;
702 } 707 }
703 708
704 ret = copy_from_user(reg, ubuf, sizeof(compat_ulong_t));
705
706 if (ret)
707 goto out;
708 else
709 ubuf += sizeof(compat_ulong_t);
710 } 709 }
711 710
712 if (valid_user_regs(&newregs.user_regs)) 711 if (valid_user_regs(&newregs.user_regs))
@@ -714,7 +713,6 @@ static int compat_gpr_set(struct task_struct *target,
714 else 713 else
715 ret = -EINVAL; 714 ret = -EINVAL;
716 715
717out:
718 return ret; 716 return ret;
719} 717}
720 718
diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c
index 0bc5e4cbc017..bd9bbd0e44ed 100644
--- a/arch/arm64/kernel/setup.c
+++ b/arch/arm64/kernel/setup.c
@@ -205,6 +205,11 @@ u64 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = INVALID_HWID };
205 205
206void __init setup_arch(char **cmdline_p) 206void __init setup_arch(char **cmdline_p)
207{ 207{
208 /*
209 * Unmask asynchronous aborts early to catch possible system errors.
210 */
211 local_async_enable();
212
208 setup_processor(); 213 setup_processor();
209 214
210 setup_machine_fdt(__fdt_pointer); 215 setup_machine_fdt(__fdt_pointer);
diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c
index a5aeefab03c3..a0c2ca602cf8 100644
--- a/arch/arm64/kernel/smp.c
+++ b/arch/arm64/kernel/smp.c
@@ -160,6 +160,7 @@ asmlinkage void secondary_start_kernel(void)
160 160
161 local_irq_enable(); 161 local_irq_enable();
162 local_fiq_enable(); 162 local_fiq_enable();
163 local_async_enable();
163 164
164 /* 165 /*
165 * OK, it's off to the idle thread for us 166 * OK, it's off to the idle thread for us
diff --git a/arch/parisc/configs/c3000_defconfig b/arch/parisc/configs/c3000_defconfig
index ec1b014952b6..acacd348df89 100644
--- a/arch/parisc/configs/c3000_defconfig
+++ b/arch/parisc/configs/c3000_defconfig
@@ -50,7 +50,7 @@ CONFIG_BLK_DEV_CRYPTOLOOP=m
50CONFIG_IDE=y 50CONFIG_IDE=y
51CONFIG_BLK_DEV_IDECD=y 51CONFIG_BLK_DEV_IDECD=y
52CONFIG_BLK_DEV_NS87415=y 52CONFIG_BLK_DEV_NS87415=y
53CONFIG_BLK_DEV_SIIMAGE=m 53CONFIG_PATA_SIL680=m
54CONFIG_SCSI=y 54CONFIG_SCSI=y
55CONFIG_BLK_DEV_SD=y 55CONFIG_BLK_DEV_SD=y
56CONFIG_CHR_DEV_ST=y 56CONFIG_CHR_DEV_ST=y
diff --git a/arch/parisc/configs/c8000_defconfig b/arch/parisc/configs/c8000_defconfig
index e1c8d2015c89..8249ac9d9cfc 100644
--- a/arch/parisc/configs/c8000_defconfig
+++ b/arch/parisc/configs/c8000_defconfig
@@ -20,7 +20,6 @@ CONFIG_MODULE_FORCE_UNLOAD=y
20CONFIG_MODVERSIONS=y 20CONFIG_MODVERSIONS=y
21CONFIG_BLK_DEV_INTEGRITY=y 21CONFIG_BLK_DEV_INTEGRITY=y
22CONFIG_PA8X00=y 22CONFIG_PA8X00=y
23CONFIG_MLONGCALLS=y
24CONFIG_64BIT=y 23CONFIG_64BIT=y
25CONFIG_SMP=y 24CONFIG_SMP=y
26CONFIG_PREEMPT=y 25CONFIG_PREEMPT=y
@@ -81,8 +80,6 @@ CONFIG_IDE=y
81CONFIG_BLK_DEV_IDECD=y 80CONFIG_BLK_DEV_IDECD=y
82CONFIG_BLK_DEV_PLATFORM=y 81CONFIG_BLK_DEV_PLATFORM=y
83CONFIG_BLK_DEV_GENERIC=y 82CONFIG_BLK_DEV_GENERIC=y
84CONFIG_BLK_DEV_SIIMAGE=y
85CONFIG_SCSI=y
86CONFIG_BLK_DEV_SD=y 83CONFIG_BLK_DEV_SD=y
87CONFIG_CHR_DEV_ST=m 84CONFIG_CHR_DEV_ST=m
88CONFIG_BLK_DEV_SR=m 85CONFIG_BLK_DEV_SR=m
@@ -94,6 +91,8 @@ CONFIG_SCSI_FC_ATTRS=y
94CONFIG_SCSI_SAS_LIBSAS=m 91CONFIG_SCSI_SAS_LIBSAS=m
95CONFIG_ISCSI_TCP=m 92CONFIG_ISCSI_TCP=m
96CONFIG_ISCSI_BOOT_SYSFS=m 93CONFIG_ISCSI_BOOT_SYSFS=m
94CONFIG_ATA=y
95CONFIG_PATA_SIL680=y
97CONFIG_FUSION=y 96CONFIG_FUSION=y
98CONFIG_FUSION_SPI=y 97CONFIG_FUSION_SPI=y
99CONFIG_FUSION_SAS=y 98CONFIG_FUSION_SAS=y
@@ -114,9 +113,8 @@ CONFIG_INPUT_FF_MEMLESS=m
114# CONFIG_KEYBOARD_ATKBD is not set 113# CONFIG_KEYBOARD_ATKBD is not set
115# CONFIG_KEYBOARD_HIL_OLD is not set 114# CONFIG_KEYBOARD_HIL_OLD is not set
116# CONFIG_KEYBOARD_HIL is not set 115# CONFIG_KEYBOARD_HIL is not set
117CONFIG_MOUSE_PS2=m 116# CONFIG_MOUSE_PS2 is not set
118CONFIG_INPUT_MISC=y 117CONFIG_INPUT_MISC=y
119CONFIG_INPUT_CM109=m
120CONFIG_SERIO_SERPORT=m 118CONFIG_SERIO_SERPORT=m
121CONFIG_SERIO_PARKBD=m 119CONFIG_SERIO_PARKBD=m
122CONFIG_SERIO_GSCPS2=m 120CONFIG_SERIO_GSCPS2=m
@@ -167,34 +165,6 @@ CONFIG_SND_VERBOSE_PRINTK=y
167CONFIG_SND_AD1889=m 165CONFIG_SND_AD1889=m
168# CONFIG_SND_USB is not set 166# CONFIG_SND_USB is not set
169# CONFIG_SND_GSC is not set 167# CONFIG_SND_GSC is not set
170CONFIG_HID_A4TECH=m
171CONFIG_HID_APPLE=m
172CONFIG_HID_BELKIN=m
173CONFIG_HID_CHERRY=m
174CONFIG_HID_CHICONY=m
175CONFIG_HID_CYPRESS=m
176CONFIG_HID_DRAGONRISE=m
177CONFIG_HID_EZKEY=m
178CONFIG_HID_KYE=m
179CONFIG_HID_GYRATION=m
180CONFIG_HID_TWINHAN=m
181CONFIG_HID_KENSINGTON=m
182CONFIG_HID_LOGITECH=m
183CONFIG_HID_LOGITECH_DJ=m
184CONFIG_HID_MICROSOFT=m
185CONFIG_HID_MONTEREY=m
186CONFIG_HID_NTRIG=m
187CONFIG_HID_ORTEK=m
188CONFIG_HID_PANTHERLORD=m
189CONFIG_HID_PETALYNX=m
190CONFIG_HID_SAMSUNG=m
191CONFIG_HID_SUNPLUS=m
192CONFIG_HID_GREENASIA=m
193CONFIG_HID_SMARTJOYPLUS=m
194CONFIG_HID_TOPSEED=m
195CONFIG_HID_THRUSTMASTER=m
196CONFIG_HID_ZEROPLUS=m
197CONFIG_USB_HID=m
198CONFIG_USB=y 168CONFIG_USB=y
199CONFIG_USB_OHCI_HCD=y 169CONFIG_USB_OHCI_HCD=y
200CONFIG_USB_STORAGE=y 170CONFIG_USB_STORAGE=y
diff --git a/arch/parisc/configs/generic-64bit_defconfig b/arch/parisc/configs/generic-64bit_defconfig
index 5874cebee077..28c1b5de044e 100644
--- a/arch/parisc/configs/generic-64bit_defconfig
+++ b/arch/parisc/configs/generic-64bit_defconfig
@@ -24,7 +24,6 @@ CONFIG_MODVERSIONS=y
24CONFIG_BLK_DEV_INTEGRITY=y 24CONFIG_BLK_DEV_INTEGRITY=y
25# CONFIG_IOSCHED_DEADLINE is not set 25# CONFIG_IOSCHED_DEADLINE is not set
26CONFIG_PA8X00=y 26CONFIG_PA8X00=y
27CONFIG_MLONGCALLS=y
28CONFIG_64BIT=y 27CONFIG_64BIT=y
29CONFIG_SMP=y 28CONFIG_SMP=y
30# CONFIG_COMPACTION is not set 29# CONFIG_COMPACTION is not set
@@ -68,7 +67,6 @@ CONFIG_IDE_GD=m
68CONFIG_IDE_GD_ATAPI=y 67CONFIG_IDE_GD_ATAPI=y
69CONFIG_BLK_DEV_IDECD=m 68CONFIG_BLK_DEV_IDECD=m
70CONFIG_BLK_DEV_NS87415=y 69CONFIG_BLK_DEV_NS87415=y
71CONFIG_BLK_DEV_SIIMAGE=y
72# CONFIG_SCSI_PROC_FS is not set 70# CONFIG_SCSI_PROC_FS is not set
73CONFIG_BLK_DEV_SD=y 71CONFIG_BLK_DEV_SD=y
74CONFIG_BLK_DEV_SR=y 72CONFIG_BLK_DEV_SR=y
@@ -82,6 +80,7 @@ CONFIG_SCSI_ZALON=y
82CONFIG_SCSI_QLA_ISCSI=m 80CONFIG_SCSI_QLA_ISCSI=m
83CONFIG_SCSI_DH=y 81CONFIG_SCSI_DH=y
84CONFIG_ATA=y 82CONFIG_ATA=y
83CONFIG_PATA_SIL680=y
85CONFIG_ATA_GENERIC=y 84CONFIG_ATA_GENERIC=y
86CONFIG_MD=y 85CONFIG_MD=y
87CONFIG_MD_LINEAR=m 86CONFIG_MD_LINEAR=m
@@ -162,7 +161,7 @@ CONFIG_SLIP_MODE_SLIP6=y
162CONFIG_INPUT_EVDEV=y 161CONFIG_INPUT_EVDEV=y
163# CONFIG_KEYBOARD_HIL_OLD is not set 162# CONFIG_KEYBOARD_HIL_OLD is not set
164# CONFIG_KEYBOARD_HIL is not set 163# CONFIG_KEYBOARD_HIL is not set
165# CONFIG_INPUT_MOUSE is not set 164# CONFIG_MOUSE_PS2 is not set
166CONFIG_INPUT_MISC=y 165CONFIG_INPUT_MISC=y
167CONFIG_SERIO_SERPORT=m 166CONFIG_SERIO_SERPORT=m
168# CONFIG_HP_SDC is not set 167# CONFIG_HP_SDC is not set
@@ -216,32 +215,7 @@ CONFIG_BACKLIGHT_LCD_SUPPORT=y
216CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y 215CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
217CONFIG_LOGO=y 216CONFIG_LOGO=y
218# CONFIG_LOGO_LINUX_MONO is not set 217# CONFIG_LOGO_LINUX_MONO is not set
219CONFIG_HID=m
220CONFIG_HIDRAW=y 218CONFIG_HIDRAW=y
221CONFIG_HID_DRAGONRISE=m
222CONFIG_DRAGONRISE_FF=y
223CONFIG_HID_KYE=m
224CONFIG_HID_GYRATION=m
225CONFIG_HID_TWINHAN=m
226CONFIG_LOGITECH_FF=y
227CONFIG_LOGIRUMBLEPAD2_FF=y
228CONFIG_HID_NTRIG=m
229CONFIG_HID_PANTHERLORD=m
230CONFIG_PANTHERLORD_FF=y
231CONFIG_HID_PETALYNX=m
232CONFIG_HID_SAMSUNG=m
233CONFIG_HID_SONY=m
234CONFIG_HID_SUNPLUS=m
235CONFIG_HID_GREENASIA=m
236CONFIG_GREENASIA_FF=y
237CONFIG_HID_SMARTJOYPLUS=m
238CONFIG_SMARTJOYPLUS_FF=y
239CONFIG_HID_TOPSEED=m
240CONFIG_HID_THRUSTMASTER=m
241CONFIG_THRUSTMASTER_FF=y
242CONFIG_HID_ZEROPLUS=m
243CONFIG_ZEROPLUS_FF=y
244CONFIG_USB_HID=m
245CONFIG_HID_PID=y 219CONFIG_HID_PID=y
246CONFIG_USB_HIDDEV=y 220CONFIG_USB_HIDDEV=y
247CONFIG_USB=y 221CONFIG_USB=y
@@ -251,13 +225,8 @@ CONFIG_USB_DYNAMIC_MINORS=y
251CONFIG_USB_MON=m 225CONFIG_USB_MON=m
252CONFIG_USB_WUSB_CBAF=m 226CONFIG_USB_WUSB_CBAF=m
253CONFIG_USB_XHCI_HCD=m 227CONFIG_USB_XHCI_HCD=m
254CONFIG_USB_EHCI_HCD=m 228CONFIG_USB_EHCI_HCD=y
255CONFIG_USB_OHCI_HCD=m 229CONFIG_USB_OHCI_HCD=y
256CONFIG_USB_R8A66597_HCD=m
257CONFIG_USB_ACM=m
258CONFIG_USB_PRINTER=m
259CONFIG_USB_WDM=m
260CONFIG_USB_TMC=m
261CONFIG_NEW_LEDS=y 230CONFIG_NEW_LEDS=y
262CONFIG_LEDS_CLASS=y 231CONFIG_LEDS_CLASS=y
263CONFIG_LEDS_TRIGGERS=y 232CONFIG_LEDS_TRIGGERS=y
diff --git a/arch/parisc/include/asm/serial.h b/arch/parisc/include/asm/serial.h
index d7e3cc60dbc3..77e9b67c87ee 100644
--- a/arch/parisc/include/asm/serial.h
+++ b/arch/parisc/include/asm/serial.h
@@ -6,5 +6,3 @@
6 * This is used for 16550-compatible UARTs 6 * This is used for 16550-compatible UARTs
7 */ 7 */
8#define BASE_BAUD ( 1843200 / 16 ) 8#define BASE_BAUD ( 1843200 / 16 )
9
10#define SERIAL_PORT_DFNS
diff --git a/arch/parisc/kernel/hardware.c b/arch/parisc/kernel/hardware.c
index 06cb3992907e..608716f8496b 100644
--- a/arch/parisc/kernel/hardware.c
+++ b/arch/parisc/kernel/hardware.c
@@ -36,6 +36,9 @@
36 * HP PARISC Hardware Database 36 * HP PARISC Hardware Database
37 * Access to this database is only possible during bootup 37 * Access to this database is only possible during bootup
38 * so don't reference this table after starting the init process 38 * so don't reference this table after starting the init process
39 *
40 * NOTE: Product names which are listed here and ends with a '?'
41 * are guessed. If you know the correct name, please let us know.
39 */ 42 */
40 43
41static struct hp_hardware hp_hardware_list[] = { 44static struct hp_hardware hp_hardware_list[] = {
@@ -222,7 +225,7 @@ static struct hp_hardware hp_hardware_list[] = {
222 {HPHW_NPROC,0x5DD,0x4,0x81,"Duet W2"}, 225 {HPHW_NPROC,0x5DD,0x4,0x81,"Duet W2"},
223 {HPHW_NPROC,0x5DE,0x4,0x81,"Piccolo W+"}, 226 {HPHW_NPROC,0x5DE,0x4,0x81,"Piccolo W+"},
224 {HPHW_NPROC,0x5DF,0x4,0x81,"Cantata W2"}, 227 {HPHW_NPROC,0x5DF,0x4,0x81,"Cantata W2"},
225 {HPHW_NPROC,0x5DF,0x0,0x00,"Marcato W+? (rp5470)"}, 228 {HPHW_NPROC,0x5DF,0x0,0x00,"Marcato W+ (rp5470)?"},
226 {HPHW_NPROC,0x5E0,0x4,0x91,"Cantata DC- W2"}, 229 {HPHW_NPROC,0x5E0,0x4,0x91,"Cantata DC- W2"},
227 {HPHW_NPROC,0x5E1,0x4,0x91,"Crescendo DC- W2"}, 230 {HPHW_NPROC,0x5E1,0x4,0x91,"Crescendo DC- W2"},
228 {HPHW_NPROC,0x5E2,0x4,0x91,"Crescendo 650 W2"}, 231 {HPHW_NPROC,0x5E2,0x4,0x91,"Crescendo 650 W2"},
@@ -276,9 +279,11 @@ static struct hp_hardware hp_hardware_list[] = {
276 {HPHW_NPROC,0x888,0x4,0x91,"Storm Peak Fast DC-"}, 279 {HPHW_NPROC,0x888,0x4,0x91,"Storm Peak Fast DC-"},
277 {HPHW_NPROC,0x889,0x4,0x91,"Storm Peak Fast"}, 280 {HPHW_NPROC,0x889,0x4,0x91,"Storm Peak Fast"},
278 {HPHW_NPROC,0x88A,0x4,0x91,"Crestone Peak Slow"}, 281 {HPHW_NPROC,0x88A,0x4,0x91,"Crestone Peak Slow"},
282 {HPHW_NPROC,0x88B,0x4,0x91,"Crestone Peak Fast?"},
279 {HPHW_NPROC,0x88C,0x4,0x91,"Orca Mako+"}, 283 {HPHW_NPROC,0x88C,0x4,0x91,"Orca Mako+"},
280 {HPHW_NPROC,0x88D,0x4,0x91,"Rainier/Medel Mako+ Slow"}, 284 {HPHW_NPROC,0x88D,0x4,0x91,"Rainier/Medel Mako+ Slow"},
281 {HPHW_NPROC,0x88E,0x4,0x91,"Rainier/Medel Mako+ Fast"}, 285 {HPHW_NPROC,0x88E,0x4,0x91,"Rainier/Medel Mako+ Fast"},
286 {HPHW_NPROC,0x892,0x4,0x91,"Mt. Hamilton Slow Mako+?"},
282 {HPHW_NPROC,0x894,0x4,0x91,"Mt. Hamilton Fast Mako+"}, 287 {HPHW_NPROC,0x894,0x4,0x91,"Mt. Hamilton Fast Mako+"},
283 {HPHW_NPROC,0x895,0x4,0x91,"Storm Peak Slow Mako+"}, 288 {HPHW_NPROC,0x895,0x4,0x91,"Storm Peak Slow Mako+"},
284 {HPHW_NPROC,0x896,0x4,0x91,"Storm Peak Fast Mako+"}, 289 {HPHW_NPROC,0x896,0x4,0x91,"Storm Peak Fast Mako+"},
diff --git a/arch/parisc/kernel/head.S b/arch/parisc/kernel/head.S
index d2d58258aea6..d4dc588c0dc1 100644
--- a/arch/parisc/kernel/head.S
+++ b/arch/parisc/kernel/head.S
@@ -41,9 +41,7 @@ END(boot_args)
41 .import fault_vector_11,code /* IVA parisc 1.1 32 bit */ 41 .import fault_vector_11,code /* IVA parisc 1.1 32 bit */
42 .import $global$ /* forward declaration */ 42 .import $global$ /* forward declaration */
43#endif /*!CONFIG_64BIT*/ 43#endif /*!CONFIG_64BIT*/
44 .export _stext,data /* Kernel want it this way! */ 44ENTRY(parisc_kernel_start)
45_stext:
46ENTRY(stext)
47 .proc 45 .proc
48 .callinfo 46 .callinfo
49 47
@@ -347,7 +345,7 @@ smp_slave_stext:
347 .procend 345 .procend
348#endif /* CONFIG_SMP */ 346#endif /* CONFIG_SMP */
349 347
350ENDPROC(stext) 348ENDPROC(parisc_kernel_start)
351 349
352#ifndef CONFIG_64BIT 350#ifndef CONFIG_64BIT
353 .section .data..read_mostly 351 .section .data..read_mostly
diff --git a/arch/parisc/kernel/sys_parisc.c b/arch/parisc/kernel/sys_parisc.c
index 5dfd248e3f1a..0d3a9d4927b5 100644
--- a/arch/parisc/kernel/sys_parisc.c
+++ b/arch/parisc/kernel/sys_parisc.c
@@ -61,8 +61,15 @@ static int get_offset(struct address_space *mapping)
61 return (unsigned long) mapping >> 8; 61 return (unsigned long) mapping >> 8;
62} 62}
63 63
64static unsigned long get_shared_area(struct address_space *mapping, 64static unsigned long shared_align_offset(struct file *filp, unsigned long pgoff)
65 unsigned long addr, unsigned long len, unsigned long pgoff) 65{
66 struct address_space *mapping = filp ? filp->f_mapping : NULL;
67
68 return (get_offset(mapping) + pgoff) << PAGE_SHIFT;
69}
70
71static unsigned long get_shared_area(struct file *filp, unsigned long addr,
72 unsigned long len, unsigned long pgoff)
66{ 73{
67 struct vm_unmapped_area_info info; 74 struct vm_unmapped_area_info info;
68 75
@@ -71,7 +78,7 @@ static unsigned long get_shared_area(struct address_space *mapping,
71 info.low_limit = PAGE_ALIGN(addr); 78 info.low_limit = PAGE_ALIGN(addr);
72 info.high_limit = TASK_SIZE; 79 info.high_limit = TASK_SIZE;
73 info.align_mask = PAGE_MASK & (SHMLBA - 1); 80 info.align_mask = PAGE_MASK & (SHMLBA - 1);
74 info.align_offset = (get_offset(mapping) + pgoff) << PAGE_SHIFT; 81 info.align_offset = shared_align_offset(filp, pgoff);
75 return vm_unmapped_area(&info); 82 return vm_unmapped_area(&info);
76} 83}
77 84
@@ -82,20 +89,18 @@ unsigned long arch_get_unmapped_area(struct file *filp, unsigned long addr,
82 return -ENOMEM; 89 return -ENOMEM;
83 if (flags & MAP_FIXED) { 90 if (flags & MAP_FIXED) {
84 if ((flags & MAP_SHARED) && 91 if ((flags & MAP_SHARED) &&
85 (addr - (pgoff << PAGE_SHIFT)) & (SHMLBA - 1)) 92 (addr - shared_align_offset(filp, pgoff)) & (SHMLBA - 1))
86 return -EINVAL; 93 return -EINVAL;
87 return addr; 94 return addr;
88 } 95 }
89 if (!addr) 96 if (!addr)
90 addr = TASK_UNMAPPED_BASE; 97 addr = TASK_UNMAPPED_BASE;
91 98
92 if (filp) { 99 if (filp || (flags & MAP_SHARED))
93 addr = get_shared_area(filp->f_mapping, addr, len, pgoff); 100 addr = get_shared_area(filp, addr, len, pgoff);
94 } else if(flags & MAP_SHARED) { 101 else
95 addr = get_shared_area(NULL, addr, len, pgoff);
96 } else {
97 addr = get_unshared_area(addr, len); 102 addr = get_unshared_area(addr, len);
98 } 103
99 return addr; 104 return addr;
100} 105}
101 106
diff --git a/arch/parisc/kernel/unwind.c b/arch/parisc/kernel/unwind.c
index 76ed62ed785b..ddd988b267a9 100644
--- a/arch/parisc/kernel/unwind.c
+++ b/arch/parisc/kernel/unwind.c
@@ -168,7 +168,7 @@ void unwind_table_remove(struct unwind_table *table)
168} 168}
169 169
170/* Called from setup_arch to import the kernel unwind info */ 170/* Called from setup_arch to import the kernel unwind info */
171int unwind_init(void) 171int __init unwind_init(void)
172{ 172{
173 long start, stop; 173 long start, stop;
174 register unsigned long gp __asm__ ("r27"); 174 register unsigned long gp __asm__ ("r27");
@@ -233,7 +233,6 @@ static void unwind_frame_regs(struct unwind_frame_info *info)
233 e = find_unwind_entry(info->ip); 233 e = find_unwind_entry(info->ip);
234 if (e == NULL) { 234 if (e == NULL) {
235 unsigned long sp; 235 unsigned long sp;
236 extern char _stext[], _etext[];
237 236
238 dbg("Cannot find unwind entry for 0x%lx; forced unwinding\n", info->ip); 237 dbg("Cannot find unwind entry for 0x%lx; forced unwinding\n", info->ip);
239 238
@@ -281,8 +280,7 @@ static void unwind_frame_regs(struct unwind_frame_info *info)
281 break; 280 break;
282 info->prev_ip = tmp; 281 info->prev_ip = tmp;
283 sp = info->prev_sp; 282 sp = info->prev_sp;
284 } while (info->prev_ip < (unsigned long)_stext || 283 } while (!kernel_text_address(info->prev_ip));
285 info->prev_ip > (unsigned long)_etext);
286 284
287 info->rp = 0; 285 info->rp = 0;
288 286
@@ -435,9 +433,8 @@ unsigned long return_address(unsigned int level)
435 do { 433 do {
436 if (unwind_once(&info) < 0 || info.ip == 0) 434 if (unwind_once(&info) < 0 || info.ip == 0)
437 return 0; 435 return 0;
438 if (!__kernel_text_address(info.ip)) { 436 if (!kernel_text_address(info.ip))
439 return 0; 437 return 0;
440 }
441 } while (info.ip && level--); 438 } while (info.ip && level--);
442 439
443 return info.ip; 440 return info.ip;
diff --git a/arch/parisc/kernel/vmlinux.lds.S b/arch/parisc/kernel/vmlinux.lds.S
index 4bb095a2f6fc..0dacc5ca555a 100644
--- a/arch/parisc/kernel/vmlinux.lds.S
+++ b/arch/parisc/kernel/vmlinux.lds.S
@@ -6,24 +6,19 @@
6 * Copyright (C) 2000 Michael Ang <mang with subcarrier.org> 6 * Copyright (C) 2000 Michael Ang <mang with subcarrier.org>
7 * Copyright (C) 2002 Randolph Chung <tausq with parisc-linux.org> 7 * Copyright (C) 2002 Randolph Chung <tausq with parisc-linux.org>
8 * Copyright (C) 2003 James Bottomley <jejb with parisc-linux.org> 8 * Copyright (C) 2003 James Bottomley <jejb with parisc-linux.org>
9 * Copyright (C) 2006 Helge Deller <deller@gmx.de> 9 * Copyright (C) 2006-2013 Helge Deller <deller@gmx.de>
10 * 10 */
11 * 11
12 * This program is free software; you can redistribute it and/or modify 12/*
13 * it under the terms of the GNU General Public License as published by 13 * Put page table entries (swapper_pg_dir) as the first thing in .bss. This
14 * the Free Software Foundation; either version 2 of the License, or 14 * will ensure that it has .bss alignment (PAGE_SIZE).
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 */ 15 */
16#define BSS_FIRST_SECTIONS *(.data..vm0.pmd) \
17 *(.data..vm0.pgd) \
18 *(.data..vm0.pte)
19
26#include <asm-generic/vmlinux.lds.h> 20#include <asm-generic/vmlinux.lds.h>
21
27/* needed for the processor specific cache alignment size */ 22/* needed for the processor specific cache alignment size */
28#include <asm/cache.h> 23#include <asm/cache.h>
29#include <asm/page.h> 24#include <asm/page.h>
@@ -39,7 +34,7 @@ OUTPUT_FORMAT("elf64-hppa-linux")
39OUTPUT_ARCH(hppa:hppa2.0w) 34OUTPUT_ARCH(hppa:hppa2.0w)
40#endif 35#endif
41 36
42ENTRY(_stext) 37ENTRY(parisc_kernel_start)
43#ifndef CONFIG_64BIT 38#ifndef CONFIG_64BIT
44jiffies = jiffies_64 + 4; 39jiffies = jiffies_64 + 4;
45#else 40#else
@@ -49,11 +44,29 @@ SECTIONS
49{ 44{
50 . = KERNEL_BINARY_TEXT_START; 45 . = KERNEL_BINARY_TEXT_START;
51 46
47 __init_begin = .;
48 HEAD_TEXT_SECTION
49 INIT_TEXT_SECTION(8)
50
51 . = ALIGN(PAGE_SIZE);
52 INIT_DATA_SECTION(PAGE_SIZE)
53 /* we have to discard exit text and such at runtime, not link time */
54 .exit.text :
55 {
56 EXIT_TEXT
57 }
58 .exit.data :
59 {
60 EXIT_DATA
61 }
62 PERCPU_SECTION(8)
63 . = ALIGN(PAGE_SIZE);
64 __init_end = .;
65 /* freed after init ends here */
66
52 _text = .; /* Text and read-only data */ 67 _text = .; /* Text and read-only data */
53 .head ALIGN(16) : { 68 _stext = .;
54 HEAD_TEXT 69 .text ALIGN(PAGE_SIZE) : {
55 } = 0
56 .text ALIGN(16) : {
57 TEXT_TEXT 70 TEXT_TEXT
58 SCHED_TEXT 71 SCHED_TEXT
59 LOCK_TEXT 72 LOCK_TEXT
@@ -68,21 +81,28 @@ SECTIONS
68 *(.lock.text) /* out-of-line lock text */ 81 *(.lock.text) /* out-of-line lock text */
69 *(.gnu.warning) 82 *(.gnu.warning)
70 } 83 }
71 /* End of text section */ 84 . = ALIGN(PAGE_SIZE);
72 _etext = .; 85 _etext = .;
86 /* End of text section */
73 87
74 /* Start of data section */ 88 /* Start of data section */
75 _sdata = .; 89 _sdata = .;
76 90
77 RODATA 91 RO_DATA_SECTION(8)
78 92
79 /* writeable */ 93#ifdef CONFIG_64BIT
80 /* Make sure this is page aligned so 94 . = ALIGN(16);
81 * that we can properly leave these 95 /* Linkage tables */
82 * as writable 96 .opd : {
83 */ 97 *(.opd)
84 . = ALIGN(PAGE_SIZE); 98 } PROVIDE (__gp = .);
85 data_start = .; 99 .plt : {
100 *(.plt)
101 }
102 .dlt : {
103 *(.dlt)
104 }
105#endif
86 106
87 /* unwind info */ 107 /* unwind info */
88 .PARISC.unwind : { 108 .PARISC.unwind : {
@@ -91,7 +111,15 @@ SECTIONS
91 __stop___unwind = .; 111 __stop___unwind = .;
92 } 112 }
93 113
94 EXCEPTION_TABLE(16) 114 /* writeable */
115 /* Make sure this is page aligned so
116 * that we can properly leave these
117 * as writable
118 */
119 . = ALIGN(PAGE_SIZE);
120 data_start = .;
121
122 EXCEPTION_TABLE(8)
95 NOTES 123 NOTES
96 124
97 /* Data */ 125 /* Data */
@@ -107,54 +135,8 @@ SECTIONS
107 _edata = .; 135 _edata = .;
108 136
109 /* BSS */ 137 /* BSS */
110 __bss_start = .; 138 BSS_SECTION(PAGE_SIZE, PAGE_SIZE, 8)
111 /* page table entries need to be PAGE_SIZE aligned */
112 . = ALIGN(PAGE_SIZE);
113 .data..vmpages : {
114 *(.data..vm0.pmd)
115 *(.data..vm0.pgd)
116 *(.data..vm0.pte)
117 }
118 .bss : {
119 *(.bss)
120 *(COMMON)
121 }
122 __bss_stop = .;
123
124#ifdef CONFIG_64BIT
125 . = ALIGN(16);
126 /* Linkage tables */
127 .opd : {
128 *(.opd)
129 } PROVIDE (__gp = .);
130 .plt : {
131 *(.plt)
132 }
133 .dlt : {
134 *(.dlt)
135 }
136#endif
137 139
138 /* reserve space for interrupt stack by aligning __init* to 16k */
139 . = ALIGN(16384);
140 __init_begin = .;
141 INIT_TEXT_SECTION(16384)
142 . = ALIGN(PAGE_SIZE);
143 INIT_DATA_SECTION(16)
144 /* we have to discard exit text and such at runtime, not link time */
145 .exit.text :
146 {
147 EXIT_TEXT
148 }
149 .exit.data :
150 {
151 EXIT_DATA
152 }
153
154 PERCPU_SECTION(L1_CACHE_BYTES)
155 . = ALIGN(PAGE_SIZE);
156 __init_end = .;
157 /* freed after init ends here */
158 _end = . ; 140 _end = . ;
159 141
160 STABS_DEBUG 142 STABS_DEBUG
diff --git a/arch/parisc/mm/init.c b/arch/parisc/mm/init.c
index b0f96c0e6316..96f8168cf4ec 100644
--- a/arch/parisc/mm/init.c
+++ b/arch/parisc/mm/init.c
@@ -32,6 +32,7 @@
32#include <asm/sections.h> 32#include <asm/sections.h>
33 33
34extern int data_start; 34extern int data_start;
35extern void parisc_kernel_start(void); /* Kernel entry point in head.S */
35 36
36#if PT_NLEVELS == 3 37#if PT_NLEVELS == 3
37/* NOTE: This layout exactly conforms to the hybrid L2/L3 page table layout 38/* NOTE: This layout exactly conforms to the hybrid L2/L3 page table layout
@@ -324,8 +325,9 @@ static void __init setup_bootmem(void)
324 reserve_bootmem_node(NODE_DATA(0), 0UL, 325 reserve_bootmem_node(NODE_DATA(0), 0UL,
325 (unsigned long)(PAGE0->mem_free + 326 (unsigned long)(PAGE0->mem_free +
326 PDC_CONSOLE_IO_IODC_SIZE), BOOTMEM_DEFAULT); 327 PDC_CONSOLE_IO_IODC_SIZE), BOOTMEM_DEFAULT);
327 reserve_bootmem_node(NODE_DATA(0), __pa((unsigned long)_text), 328 reserve_bootmem_node(NODE_DATA(0), __pa(KERNEL_BINARY_TEXT_START),
328 (unsigned long)(_end - _text), BOOTMEM_DEFAULT); 329 (unsigned long)(_end - KERNEL_BINARY_TEXT_START),
330 BOOTMEM_DEFAULT);
329 reserve_bootmem_node(NODE_DATA(0), (bootmap_start_pfn << PAGE_SHIFT), 331 reserve_bootmem_node(NODE_DATA(0), (bootmap_start_pfn << PAGE_SHIFT),
330 ((bootmap_pfn - bootmap_start_pfn) << PAGE_SHIFT), 332 ((bootmap_pfn - bootmap_start_pfn) << PAGE_SHIFT),
331 BOOTMEM_DEFAULT); 333 BOOTMEM_DEFAULT);
@@ -378,6 +380,17 @@ static void __init setup_bootmem(void)
378 request_resource(&sysram_resources[0], &pdcdata_resource); 380 request_resource(&sysram_resources[0], &pdcdata_resource);
379} 381}
380 382
383static int __init parisc_text_address(unsigned long vaddr)
384{
385 static unsigned long head_ptr __initdata;
386
387 if (!head_ptr)
388 head_ptr = PAGE_MASK & (unsigned long)
389 dereference_function_descriptor(&parisc_kernel_start);
390
391 return core_kernel_text(vaddr) || vaddr == head_ptr;
392}
393
381static void __init map_pages(unsigned long start_vaddr, 394static void __init map_pages(unsigned long start_vaddr,
382 unsigned long start_paddr, unsigned long size, 395 unsigned long start_paddr, unsigned long size,
383 pgprot_t pgprot, int force) 396 pgprot_t pgprot, int force)
@@ -466,7 +479,7 @@ static void __init map_pages(unsigned long start_vaddr,
466 */ 479 */
467 if (force) 480 if (force)
468 pte = __mk_pte(address, pgprot); 481 pte = __mk_pte(address, pgprot);
469 else if (core_kernel_text(vaddr) && 482 else if (parisc_text_address(vaddr) &&
470 address != fv_addr) 483 address != fv_addr)
471 pte = __mk_pte(address, PAGE_KERNEL_EXEC); 484 pte = __mk_pte(address, PAGE_KERNEL_EXEC);
472 else 485 else
diff --git a/arch/powerpc/Makefile b/arch/powerpc/Makefile
index 8a2463670a5b..0f4344e6fbca 100644
--- a/arch/powerpc/Makefile
+++ b/arch/powerpc/Makefile
@@ -75,8 +75,10 @@ LDEMULATION := lppc
75GNUTARGET := powerpcle 75GNUTARGET := powerpcle
76MULTIPLEWORD := -mno-multiple 76MULTIPLEWORD := -mno-multiple
77else 77else
78ifeq ($(call cc-option-yn,-mbig-endian),y)
78override CC += -mbig-endian 79override CC += -mbig-endian
79override AS += -mbig-endian 80override AS += -mbig-endian
81endif
80override LD += -EB 82override LD += -EB
81LDEMULATION := ppc 83LDEMULATION := ppc
82GNUTARGET := powerpc 84GNUTARGET := powerpc
@@ -128,7 +130,12 @@ CFLAGS-$(CONFIG_POWER5_CPU) += $(call cc-option,-mcpu=power5)
128CFLAGS-$(CONFIG_POWER6_CPU) += $(call cc-option,-mcpu=power6) 130CFLAGS-$(CONFIG_POWER6_CPU) += $(call cc-option,-mcpu=power6)
129CFLAGS-$(CONFIG_POWER7_CPU) += $(call cc-option,-mcpu=power7) 131CFLAGS-$(CONFIG_POWER7_CPU) += $(call cc-option,-mcpu=power7)
130 132
133# Altivec option not allowed with e500mc64 in GCC.
134ifeq ($(CONFIG_ALTIVEC),y)
135E5500_CPU := -mcpu=powerpc64
136else
131E5500_CPU := $(call cc-option,-mcpu=e500mc64,-mcpu=powerpc64) 137E5500_CPU := $(call cc-option,-mcpu=e500mc64,-mcpu=powerpc64)
138endif
132CFLAGS-$(CONFIG_E5500_CPU) += $(E5500_CPU) 139CFLAGS-$(CONFIG_E5500_CPU) += $(E5500_CPU)
133CFLAGS-$(CONFIG_E6500_CPU) += $(call cc-option,-mcpu=e6500,$(E5500_CPU)) 140CFLAGS-$(CONFIG_E6500_CPU) += $(call cc-option,-mcpu=e6500,$(E5500_CPU))
134 141
diff --git a/arch/powerpc/boot/dts/xcalibur1501.dts b/arch/powerpc/boot/dts/xcalibur1501.dts
index cc00f4ddd9a7..c409cbafb126 100644
--- a/arch/powerpc/boot/dts/xcalibur1501.dts
+++ b/arch/powerpc/boot/dts/xcalibur1501.dts
@@ -637,14 +637,14 @@
637 tlu@2f000 { 637 tlu@2f000 {
638 compatible = "fsl,mpc8572-tlu", "fsl_tlu"; 638 compatible = "fsl,mpc8572-tlu", "fsl_tlu";
639 reg = <0x2f000 0x1000>; 639 reg = <0x2f000 0x1000>;
640 interupts = <61 2 >; 640 interrupts = <61 2>;
641 interrupt-parent = <&mpic>; 641 interrupt-parent = <&mpic>;
642 }; 642 };
643 643
644 tlu@15000 { 644 tlu@15000 {
645 compatible = "fsl,mpc8572-tlu", "fsl_tlu"; 645 compatible = "fsl,mpc8572-tlu", "fsl_tlu";
646 reg = <0x15000 0x1000>; 646 reg = <0x15000 0x1000>;
647 interupts = <75 2>; 647 interrupts = <75 2>;
648 interrupt-parent = <&mpic>; 648 interrupt-parent = <&mpic>;
649 }; 649 };
650 }; 650 };
diff --git a/arch/powerpc/boot/dts/xpedite5301.dts b/arch/powerpc/boot/dts/xpedite5301.dts
index 53c1c6a9752f..04cb410da48b 100644
--- a/arch/powerpc/boot/dts/xpedite5301.dts
+++ b/arch/powerpc/boot/dts/xpedite5301.dts
@@ -547,14 +547,14 @@
547 tlu@2f000 { 547 tlu@2f000 {
548 compatible = "fsl,mpc8572-tlu", "fsl_tlu"; 548 compatible = "fsl,mpc8572-tlu", "fsl_tlu";
549 reg = <0x2f000 0x1000>; 549 reg = <0x2f000 0x1000>;
550 interupts = <61 2 >; 550 interrupts = <61 2>;
551 interrupt-parent = <&mpic>; 551 interrupt-parent = <&mpic>;
552 }; 552 };
553 553
554 tlu@15000 { 554 tlu@15000 {
555 compatible = "fsl,mpc8572-tlu", "fsl_tlu"; 555 compatible = "fsl,mpc8572-tlu", "fsl_tlu";
556 reg = <0x15000 0x1000>; 556 reg = <0x15000 0x1000>;
557 interupts = <75 2>; 557 interrupts = <75 2>;
558 interrupt-parent = <&mpic>; 558 interrupt-parent = <&mpic>;
559 }; 559 };
560 }; 560 };
diff --git a/arch/powerpc/boot/dts/xpedite5330.dts b/arch/powerpc/boot/dts/xpedite5330.dts
index 215225983150..73f8620f1ce7 100644
--- a/arch/powerpc/boot/dts/xpedite5330.dts
+++ b/arch/powerpc/boot/dts/xpedite5330.dts
@@ -583,14 +583,14 @@
583 tlu@2f000 { 583 tlu@2f000 {
584 compatible = "fsl,mpc8572-tlu", "fsl_tlu"; 584 compatible = "fsl,mpc8572-tlu", "fsl_tlu";
585 reg = <0x2f000 0x1000>; 585 reg = <0x2f000 0x1000>;
586 interupts = <61 2 >; 586 interrupts = <61 2>;
587 interrupt-parent = <&mpic>; 587 interrupt-parent = <&mpic>;
588 }; 588 };
589 589
590 tlu@15000 { 590 tlu@15000 {
591 compatible = "fsl,mpc8572-tlu", "fsl_tlu"; 591 compatible = "fsl,mpc8572-tlu", "fsl_tlu";
592 reg = <0x15000 0x1000>; 592 reg = <0x15000 0x1000>;
593 interupts = <75 2>; 593 interrupts = <75 2>;
594 interrupt-parent = <&mpic>; 594 interrupt-parent = <&mpic>;
595 }; 595 };
596 }; 596 };
diff --git a/arch/powerpc/boot/dts/xpedite5370.dts b/arch/powerpc/boot/dts/xpedite5370.dts
index 11dbda10d756..cd0ea2b99362 100644
--- a/arch/powerpc/boot/dts/xpedite5370.dts
+++ b/arch/powerpc/boot/dts/xpedite5370.dts
@@ -545,14 +545,14 @@
545 tlu@2f000 { 545 tlu@2f000 {
546 compatible = "fsl,mpc8572-tlu", "fsl_tlu"; 546 compatible = "fsl,mpc8572-tlu", "fsl_tlu";
547 reg = <0x2f000 0x1000>; 547 reg = <0x2f000 0x1000>;
548 interupts = <61 2 >; 548 interrupts = <61 2>;
549 interrupt-parent = <&mpic>; 549 interrupt-parent = <&mpic>;
550 }; 550 };
551 551
552 tlu@15000 { 552 tlu@15000 {
553 compatible = "fsl,mpc8572-tlu", "fsl_tlu"; 553 compatible = "fsl,mpc8572-tlu", "fsl_tlu";
554 reg = <0x15000 0x1000>; 554 reg = <0x15000 0x1000>;
555 interupts = <75 2>; 555 interrupts = <75 2>;
556 interrupt-parent = <&mpic>; 556 interrupt-parent = <&mpic>;
557 }; 557 };
558 }; 558 };
diff --git a/arch/powerpc/boot/util.S b/arch/powerpc/boot/util.S
index 5143228e3e5f..6636b1d7821b 100644
--- a/arch/powerpc/boot/util.S
+++ b/arch/powerpc/boot/util.S
@@ -71,18 +71,32 @@ udelay:
71 add r4,r4,r5 71 add r4,r4,r5
72 addi r4,r4,-1 72 addi r4,r4,-1
73 divw r4,r4,r5 /* BUS ticks */ 73 divw r4,r4,r5 /* BUS ticks */
74#ifdef CONFIG_8xx
751: mftbu r5
76 mftb r6
77 mftbu r7
78#else
741: mfspr r5, SPRN_TBRU 791: mfspr r5, SPRN_TBRU
75 mfspr r6, SPRN_TBRL 80 mfspr r6, SPRN_TBRL
76 mfspr r7, SPRN_TBRU 81 mfspr r7, SPRN_TBRU
82#endif
77 cmpw 0,r5,r7 83 cmpw 0,r5,r7
78 bne 1b /* Get [synced] base time */ 84 bne 1b /* Get [synced] base time */
79 addc r9,r6,r4 /* Compute end time */ 85 addc r9,r6,r4 /* Compute end time */
80 addze r8,r5 86 addze r8,r5
87#ifdef CONFIG_8xx
882: mftbu r5
89#else
812: mfspr r5, SPRN_TBRU 902: mfspr r5, SPRN_TBRU
91#endif
82 cmpw 0,r5,r8 92 cmpw 0,r5,r8
83 blt 2b 93 blt 2b
84 bgt 3f 94 bgt 3f
95#ifdef CONFIG_8xx
96 mftb r6
97#else
85 mfspr r6, SPRN_TBRL 98 mfspr r6, SPRN_TBRL
99#endif
86 cmpw 0,r6,r9 100 cmpw 0,r6,r9
87 blt 2b 101 blt 2b
883: blr 1023: blr
diff --git a/arch/powerpc/include/asm/pgalloc-64.h b/arch/powerpc/include/asm/pgalloc-64.h
index 16cb92d215d2..694012877bf7 100644
--- a/arch/powerpc/include/asm/pgalloc-64.h
+++ b/arch/powerpc/include/asm/pgalloc-64.h
@@ -16,6 +16,7 @@ struct vmemmap_backing {
16 unsigned long phys; 16 unsigned long phys;
17 unsigned long virt_addr; 17 unsigned long virt_addr;
18}; 18};
19extern struct vmemmap_backing *vmemmap_list;
19 20
20/* 21/*
21 * Functions that deal with pagetables that could be at any level of 22 * Functions that deal with pagetables that could be at any level of
diff --git a/arch/powerpc/include/asm/ppc_asm.h b/arch/powerpc/include/asm/ppc_asm.h
index 3c1acc31a092..f595b98079ee 100644
--- a/arch/powerpc/include/asm/ppc_asm.h
+++ b/arch/powerpc/include/asm/ppc_asm.h
@@ -366,6 +366,8 @@ BEGIN_FTR_SECTION_NESTED(96); \
366 cmpwi dest,0; \ 366 cmpwi dest,0; \
367 beq- 90b; \ 367 beq- 90b; \
368END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96) 368END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96)
369#elif defined(CONFIG_8xx)
370#define MFTB(dest) mftb dest
369#else 371#else
370#define MFTB(dest) mfspr dest, SPRN_TBRL 372#define MFTB(dest) mfspr dest, SPRN_TBRL
371#endif 373#endif
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 5c45787d551e..fa8388ed94c5 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -1174,12 +1174,19 @@
1174 1174
1175#else /* __powerpc64__ */ 1175#else /* __powerpc64__ */
1176 1176
1177#if defined(CONFIG_8xx)
1178#define mftbl() ({unsigned long rval; \
1179 asm volatile("mftbl %0" : "=r" (rval)); rval;})
1180#define mftbu() ({unsigned long rval; \
1181 asm volatile("mftbu %0" : "=r" (rval)); rval;})
1182#else
1177#define mftbl() ({unsigned long rval; \ 1183#define mftbl() ({unsigned long rval; \
1178 asm volatile("mfspr %0, %1" : "=r" (rval) : \ 1184 asm volatile("mfspr %0, %1" : "=r" (rval) : \
1179 "i" (SPRN_TBRL)); rval;}) 1185 "i" (SPRN_TBRL)); rval;})
1180#define mftbu() ({unsigned long rval; \ 1186#define mftbu() ({unsigned long rval; \
1181 asm volatile("mfspr %0, %1" : "=r" (rval) : \ 1187 asm volatile("mfspr %0, %1" : "=r" (rval) : \
1182 "i" (SPRN_TBRU)); rval;}) 1188 "i" (SPRN_TBRU)); rval;})
1189#endif
1183#endif /* !__powerpc64__ */ 1190#endif /* !__powerpc64__ */
1184 1191
1185#define mttbl(v) asm volatile("mttbl %0":: "r"(v)) 1192#define mttbl(v) asm volatile("mttbl %0":: "r"(v))
diff --git a/arch/powerpc/include/asm/timex.h b/arch/powerpc/include/asm/timex.h
index 18908caa1f3b..2cf846edb3fc 100644
--- a/arch/powerpc/include/asm/timex.h
+++ b/arch/powerpc/include/asm/timex.h
@@ -29,7 +29,11 @@ static inline cycles_t get_cycles(void)
29 ret = 0; 29 ret = 0;
30 30
31 __asm__ __volatile__( 31 __asm__ __volatile__(
32#ifdef CONFIG_8xx
33 "97: mftb %0\n"
34#else
32 "97: mfspr %0, %2\n" 35 "97: mfspr %0, %2\n"
36#endif
33 "99:\n" 37 "99:\n"
34 ".section __ftr_fixup,\"a\"\n" 38 ".section __ftr_fixup,\"a\"\n"
35 ".align 2\n" 39 ".align 2\n"
@@ -41,7 +45,11 @@ static inline cycles_t get_cycles(void)
41 " .long 0\n" 45 " .long 0\n"
42 " .long 0\n" 46 " .long 0\n"
43 ".previous" 47 ".previous"
48#ifdef CONFIG_8xx
49 : "=r" (ret) : "i" (CPU_FTR_601));
50#else
44 : "=r" (ret) : "i" (CPU_FTR_601), "i" (SPRN_TBRL)); 51 : "=r" (ret) : "i" (CPU_FTR_601), "i" (SPRN_TBRL));
52#endif
45 return ret; 53 return ret;
46#endif 54#endif
47} 55}
diff --git a/arch/powerpc/kernel/machine_kexec.c b/arch/powerpc/kernel/machine_kexec.c
index e1ec57e87b3b..88a7fb458dfd 100644
--- a/arch/powerpc/kernel/machine_kexec.c
+++ b/arch/powerpc/kernel/machine_kexec.c
@@ -18,6 +18,7 @@
18#include <linux/ftrace.h> 18#include <linux/ftrace.h>
19 19
20#include <asm/machdep.h> 20#include <asm/machdep.h>
21#include <asm/pgalloc.h>
21#include <asm/prom.h> 22#include <asm/prom.h>
22#include <asm/sections.h> 23#include <asm/sections.h>
23 24
@@ -75,6 +76,17 @@ void arch_crash_save_vmcoreinfo(void)
75#ifndef CONFIG_NEED_MULTIPLE_NODES 76#ifndef CONFIG_NEED_MULTIPLE_NODES
76 VMCOREINFO_SYMBOL(contig_page_data); 77 VMCOREINFO_SYMBOL(contig_page_data);
77#endif 78#endif
79#if defined(CONFIG_PPC64) && defined(CONFIG_SPARSEMEM_VMEMMAP)
80 VMCOREINFO_SYMBOL(vmemmap_list);
81 VMCOREINFO_SYMBOL(mmu_vmemmap_psize);
82 VMCOREINFO_SYMBOL(mmu_psize_defs);
83 VMCOREINFO_STRUCT_SIZE(vmemmap_backing);
84 VMCOREINFO_OFFSET(vmemmap_backing, list);
85 VMCOREINFO_OFFSET(vmemmap_backing, phys);
86 VMCOREINFO_OFFSET(vmemmap_backing, virt_addr);
87 VMCOREINFO_STRUCT_SIZE(mmu_psize_def);
88 VMCOREINFO_OFFSET(mmu_psize_def, shift);
89#endif
78} 90}
79 91
80/* 92/*
diff --git a/arch/powerpc/kernel/nvram_64.c b/arch/powerpc/kernel/nvram_64.c
index fd82c289ab1c..28b898e68185 100644
--- a/arch/powerpc/kernel/nvram_64.c
+++ b/arch/powerpc/kernel/nvram_64.c
@@ -210,7 +210,7 @@ static void __init nvram_print_partitions(char * label)
210 printk(KERN_WARNING "--------%s---------\n", label); 210 printk(KERN_WARNING "--------%s---------\n", label);
211 printk(KERN_WARNING "indx\t\tsig\tchks\tlen\tname\n"); 211 printk(KERN_WARNING "indx\t\tsig\tchks\tlen\tname\n");
212 list_for_each_entry(tmp_part, &nvram_partitions, partition) { 212 list_for_each_entry(tmp_part, &nvram_partitions, partition) {
213 printk(KERN_WARNING "%4d \t%02x\t%02x\t%d\t%12s\n", 213 printk(KERN_WARNING "%4d \t%02x\t%02x\t%d\t%12.12s\n",
214 tmp_part->index, tmp_part->header.signature, 214 tmp_part->index, tmp_part->header.signature,
215 tmp_part->header.checksum, tmp_part->header.length, 215 tmp_part->header.checksum, tmp_part->header.length,
216 tmp_part->header.name); 216 tmp_part->header.name);
diff --git a/arch/powerpc/kernel/signal_32.c b/arch/powerpc/kernel/signal_32.c
index 1844298f5ea4..68027bfa5f8e 100644
--- a/arch/powerpc/kernel/signal_32.c
+++ b/arch/powerpc/kernel/signal_32.c
@@ -445,6 +445,12 @@ static int save_user_regs(struct pt_regs *regs, struct mcontext __user *frame,
445#endif /* CONFIG_ALTIVEC */ 445#endif /* CONFIG_ALTIVEC */
446 if (copy_fpr_to_user(&frame->mc_fregs, current)) 446 if (copy_fpr_to_user(&frame->mc_fregs, current))
447 return 1; 447 return 1;
448
449 /*
450 * Clear the MSR VSX bit to indicate there is no valid state attached
451 * to this context, except in the specific case below where we set it.
452 */
453 msr &= ~MSR_VSX;
448#ifdef CONFIG_VSX 454#ifdef CONFIG_VSX
449 /* 455 /*
450 * Copy VSR 0-31 upper half from thread_struct to local 456 * Copy VSR 0-31 upper half from thread_struct to local
@@ -457,15 +463,7 @@ static int save_user_regs(struct pt_regs *regs, struct mcontext __user *frame,
457 if (copy_vsx_to_user(&frame->mc_vsregs, current)) 463 if (copy_vsx_to_user(&frame->mc_vsregs, current))
458 return 1; 464 return 1;
459 msr |= MSR_VSX; 465 msr |= MSR_VSX;
460 } else if (!ctx_has_vsx_region) 466 }
461 /*
462 * With a small context structure we can't hold the VSX
463 * registers, hence clear the MSR value to indicate the state
464 * was not saved.
465 */
466 msr &= ~MSR_VSX;
467
468
469#endif /* CONFIG_VSX */ 467#endif /* CONFIG_VSX */
470#ifdef CONFIG_SPE 468#ifdef CONFIG_SPE
471 /* save spe registers */ 469 /* save spe registers */
diff --git a/arch/powerpc/kernel/signal_64.c b/arch/powerpc/kernel/signal_64.c
index e66f67b8b9e6..42991045349f 100644
--- a/arch/powerpc/kernel/signal_64.c
+++ b/arch/powerpc/kernel/signal_64.c
@@ -122,6 +122,12 @@ static long setup_sigcontext(struct sigcontext __user *sc, struct pt_regs *regs,
122 flush_fp_to_thread(current); 122 flush_fp_to_thread(current);
123 /* copy fpr regs and fpscr */ 123 /* copy fpr regs and fpscr */
124 err |= copy_fpr_to_user(&sc->fp_regs, current); 124 err |= copy_fpr_to_user(&sc->fp_regs, current);
125
126 /*
127 * Clear the MSR VSX bit to indicate there is no valid state attached
128 * to this context, except in the specific case below where we set it.
129 */
130 msr &= ~MSR_VSX;
125#ifdef CONFIG_VSX 131#ifdef CONFIG_VSX
126 /* 132 /*
127 * Copy VSX low doubleword to local buffer for formatting, 133 * Copy VSX low doubleword to local buffer for formatting,
diff --git a/arch/powerpc/kernel/vdso32/gettimeofday.S b/arch/powerpc/kernel/vdso32/gettimeofday.S
index 6b1f2a6d5517..6b2b69616e77 100644
--- a/arch/powerpc/kernel/vdso32/gettimeofday.S
+++ b/arch/powerpc/kernel/vdso32/gettimeofday.S
@@ -232,9 +232,15 @@ __do_get_tspec:
232 lwz r6,(CFG_TB_ORIG_STAMP+4)(r9) 232 lwz r6,(CFG_TB_ORIG_STAMP+4)(r9)
233 233
234 /* Get a stable TB value */ 234 /* Get a stable TB value */
235#ifdef CONFIG_8xx
2362: mftbu r3
237 mftbl r4
238 mftbu r0
239#else
2352: mfspr r3, SPRN_TBRU 2402: mfspr r3, SPRN_TBRU
236 mfspr r4, SPRN_TBRL 241 mfspr r4, SPRN_TBRL
237 mfspr r0, SPRN_TBRU 242 mfspr r0, SPRN_TBRU
243#endif
238 cmplw cr0,r3,r0 244 cmplw cr0,r3,r0
239 bne- 2b 245 bne- 2b
240 246
diff --git a/arch/powerpc/mm/hugetlbpage-book3e.c b/arch/powerpc/mm/hugetlbpage-book3e.c
index 3bc700655fc8..74551b5e41e5 100644
--- a/arch/powerpc/mm/hugetlbpage-book3e.c
+++ b/arch/powerpc/mm/hugetlbpage-book3e.c
@@ -117,6 +117,5 @@ void flush_hugetlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
117 struct hstate *hstate = hstate_file(vma->vm_file); 117 struct hstate *hstate = hstate_file(vma->vm_file);
118 unsigned long tsize = huge_page_shift(hstate) - 10; 118 unsigned long tsize = huge_page_shift(hstate) - 10;
119 119
120 __flush_tlb_page(vma ? vma->vm_mm : NULL, vmaddr, tsize, 0); 120 __flush_tlb_page(vma->vm_mm, vmaddr, tsize, 0);
121
122} 121}
diff --git a/arch/powerpc/mm/tlb_nohash.c b/arch/powerpc/mm/tlb_nohash.c
index 41cd68dee681..358d74303138 100644
--- a/arch/powerpc/mm/tlb_nohash.c
+++ b/arch/powerpc/mm/tlb_nohash.c
@@ -305,7 +305,7 @@ void __flush_tlb_page(struct mm_struct *mm, unsigned long vmaddr,
305void flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr) 305void flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
306{ 306{
307#ifdef CONFIG_HUGETLB_PAGE 307#ifdef CONFIG_HUGETLB_PAGE
308 if (is_vm_hugetlb_page(vma)) 308 if (vma && is_vm_hugetlb_page(vma))
309 flush_hugetlb_page(vma, vmaddr); 309 flush_hugetlb_page(vma, vmaddr);
310#endif 310#endif
311 311
diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/platforms/Kconfig.cputype
index 132f8726a257..bca2465a9c34 100644
--- a/arch/powerpc/platforms/Kconfig.cputype
+++ b/arch/powerpc/platforms/Kconfig.cputype
@@ -404,13 +404,27 @@ config PPC_DOORBELL
404 404
405endmenu 405endmenu
406 406
407config CPU_LITTLE_ENDIAN 407choice
408 bool "Build little endian kernel" 408 prompt "Endianness selection"
409 default n 409 default CPU_BIG_ENDIAN
410 help 410 help
411 This option selects whether a big endian or little endian kernel will 411 This option selects whether a big endian or little endian kernel will
412 be built. 412 be built.
413 413
414config CPU_BIG_ENDIAN
415 bool "Build big endian kernel"
416 help
417 Build a big endian kernel.
418
419 If unsure, select this option.
420
421config CPU_LITTLE_ENDIAN
422 bool "Build little endian kernel"
423 help
424 Build a little endian kernel.
425
414 Note that if cross compiling a little endian kernel, 426 Note that if cross compiling a little endian kernel,
415 CROSS_COMPILE must point to a toolchain capable of targeting 427 CROSS_COMPILE must point to a toolchain capable of targeting
416 little endian powerpc. 428 little endian powerpc.
429
430endchoice
diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig
index 314fced4fc14..5877e71901b3 100644
--- a/arch/s390/Kconfig
+++ b/arch/s390/Kconfig
@@ -101,7 +101,7 @@ config S390
101 select GENERIC_CPU_DEVICES if !SMP 101 select GENERIC_CPU_DEVICES if !SMP
102 select GENERIC_FIND_FIRST_BIT 102 select GENERIC_FIND_FIRST_BIT
103 select GENERIC_SMP_IDLE_THREAD 103 select GENERIC_SMP_IDLE_THREAD
104 select GENERIC_TIME_VSYSCALL_OLD 104 select GENERIC_TIME_VSYSCALL
105 select HAVE_ALIGNED_STRUCT_PAGE if SLUB 105 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
106 select HAVE_ARCH_JUMP_LABEL if !MARCH_G5 106 select HAVE_ARCH_JUMP_LABEL if !MARCH_G5
107 select HAVE_ARCH_SECCOMP_FILTER 107 select HAVE_ARCH_SECCOMP_FILTER
diff --git a/arch/s390/crypto/aes_s390.c b/arch/s390/crypto/aes_s390.c
index 46cae138ece2..b3feabd39f31 100644
--- a/arch/s390/crypto/aes_s390.c
+++ b/arch/s390/crypto/aes_s390.c
@@ -35,7 +35,6 @@ static u8 *ctrblk;
35static char keylen_flag; 35static char keylen_flag;
36 36
37struct s390_aes_ctx { 37struct s390_aes_ctx {
38 u8 iv[AES_BLOCK_SIZE];
39 u8 key[AES_MAX_KEY_SIZE]; 38 u8 key[AES_MAX_KEY_SIZE];
40 long enc; 39 long enc;
41 long dec; 40 long dec;
@@ -56,8 +55,7 @@ struct pcc_param {
56 55
57struct s390_xts_ctx { 56struct s390_xts_ctx {
58 u8 key[32]; 57 u8 key[32];
59 u8 xts_param[16]; 58 u8 pcc_key[32];
60 struct pcc_param pcc;
61 long enc; 59 long enc;
62 long dec; 60 long dec;
63 int key_len; 61 int key_len;
@@ -441,30 +439,36 @@ static int cbc_aes_set_key(struct crypto_tfm *tfm, const u8 *in_key,
441 return aes_set_key(tfm, in_key, key_len); 439 return aes_set_key(tfm, in_key, key_len);
442} 440}
443 441
444static int cbc_aes_crypt(struct blkcipher_desc *desc, long func, void *param, 442static int cbc_aes_crypt(struct blkcipher_desc *desc, long func,
445 struct blkcipher_walk *walk) 443 struct blkcipher_walk *walk)
446{ 444{
445 struct s390_aes_ctx *sctx = crypto_blkcipher_ctx(desc->tfm);
447 int ret = blkcipher_walk_virt(desc, walk); 446 int ret = blkcipher_walk_virt(desc, walk);
448 unsigned int nbytes = walk->nbytes; 447 unsigned int nbytes = walk->nbytes;
448 struct {
449 u8 iv[AES_BLOCK_SIZE];
450 u8 key[AES_MAX_KEY_SIZE];
451 } param;
449 452
450 if (!nbytes) 453 if (!nbytes)
451 goto out; 454 goto out;
452 455
453 memcpy(param, walk->iv, AES_BLOCK_SIZE); 456 memcpy(param.iv, walk->iv, AES_BLOCK_SIZE);
457 memcpy(param.key, sctx->key, sctx->key_len);
454 do { 458 do {
455 /* only use complete blocks */ 459 /* only use complete blocks */
456 unsigned int n = nbytes & ~(AES_BLOCK_SIZE - 1); 460 unsigned int n = nbytes & ~(AES_BLOCK_SIZE - 1);
457 u8 *out = walk->dst.virt.addr; 461 u8 *out = walk->dst.virt.addr;
458 u8 *in = walk->src.virt.addr; 462 u8 *in = walk->src.virt.addr;
459 463
460 ret = crypt_s390_kmc(func, param, out, in, n); 464 ret = crypt_s390_kmc(func, &param, out, in, n);
461 if (ret < 0 || ret != n) 465 if (ret < 0 || ret != n)
462 return -EIO; 466 return -EIO;
463 467
464 nbytes &= AES_BLOCK_SIZE - 1; 468 nbytes &= AES_BLOCK_SIZE - 1;
465 ret = blkcipher_walk_done(desc, walk, nbytes); 469 ret = blkcipher_walk_done(desc, walk, nbytes);
466 } while ((nbytes = walk->nbytes)); 470 } while ((nbytes = walk->nbytes));
467 memcpy(walk->iv, param, AES_BLOCK_SIZE); 471 memcpy(walk->iv, param.iv, AES_BLOCK_SIZE);
468 472
469out: 473out:
470 return ret; 474 return ret;
@@ -481,7 +485,7 @@ static int cbc_aes_encrypt(struct blkcipher_desc *desc,
481 return fallback_blk_enc(desc, dst, src, nbytes); 485 return fallback_blk_enc(desc, dst, src, nbytes);
482 486
483 blkcipher_walk_init(&walk, dst, src, nbytes); 487 blkcipher_walk_init(&walk, dst, src, nbytes);
484 return cbc_aes_crypt(desc, sctx->enc, sctx->iv, &walk); 488 return cbc_aes_crypt(desc, sctx->enc, &walk);
485} 489}
486 490
487static int cbc_aes_decrypt(struct blkcipher_desc *desc, 491static int cbc_aes_decrypt(struct blkcipher_desc *desc,
@@ -495,7 +499,7 @@ static int cbc_aes_decrypt(struct blkcipher_desc *desc,
495 return fallback_blk_dec(desc, dst, src, nbytes); 499 return fallback_blk_dec(desc, dst, src, nbytes);
496 500
497 blkcipher_walk_init(&walk, dst, src, nbytes); 501 blkcipher_walk_init(&walk, dst, src, nbytes);
498 return cbc_aes_crypt(desc, sctx->dec, sctx->iv, &walk); 502 return cbc_aes_crypt(desc, sctx->dec, &walk);
499} 503}
500 504
501static struct crypto_alg cbc_aes_alg = { 505static struct crypto_alg cbc_aes_alg = {
@@ -586,7 +590,7 @@ static int xts_aes_set_key(struct crypto_tfm *tfm, const u8 *in_key,
586 xts_ctx->enc = KM_XTS_128_ENCRYPT; 590 xts_ctx->enc = KM_XTS_128_ENCRYPT;
587 xts_ctx->dec = KM_XTS_128_DECRYPT; 591 xts_ctx->dec = KM_XTS_128_DECRYPT;
588 memcpy(xts_ctx->key + 16, in_key, 16); 592 memcpy(xts_ctx->key + 16, in_key, 16);
589 memcpy(xts_ctx->pcc.key + 16, in_key + 16, 16); 593 memcpy(xts_ctx->pcc_key + 16, in_key + 16, 16);
590 break; 594 break;
591 case 48: 595 case 48:
592 xts_ctx->enc = 0; 596 xts_ctx->enc = 0;
@@ -597,7 +601,7 @@ static int xts_aes_set_key(struct crypto_tfm *tfm, const u8 *in_key,
597 xts_ctx->enc = KM_XTS_256_ENCRYPT; 601 xts_ctx->enc = KM_XTS_256_ENCRYPT;
598 xts_ctx->dec = KM_XTS_256_DECRYPT; 602 xts_ctx->dec = KM_XTS_256_DECRYPT;
599 memcpy(xts_ctx->key, in_key, 32); 603 memcpy(xts_ctx->key, in_key, 32);
600 memcpy(xts_ctx->pcc.key, in_key + 32, 32); 604 memcpy(xts_ctx->pcc_key, in_key + 32, 32);
601 break; 605 break;
602 default: 606 default:
603 *flags |= CRYPTO_TFM_RES_BAD_KEY_LEN; 607 *flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
@@ -616,29 +620,33 @@ static int xts_aes_crypt(struct blkcipher_desc *desc, long func,
616 unsigned int nbytes = walk->nbytes; 620 unsigned int nbytes = walk->nbytes;
617 unsigned int n; 621 unsigned int n;
618 u8 *in, *out; 622 u8 *in, *out;
619 void *param; 623 struct pcc_param pcc_param;
624 struct {
625 u8 key[32];
626 u8 init[16];
627 } xts_param;
620 628
621 if (!nbytes) 629 if (!nbytes)
622 goto out; 630 goto out;
623 631
624 memset(xts_ctx->pcc.block, 0, sizeof(xts_ctx->pcc.block)); 632 memset(pcc_param.block, 0, sizeof(pcc_param.block));
625 memset(xts_ctx->pcc.bit, 0, sizeof(xts_ctx->pcc.bit)); 633 memset(pcc_param.bit, 0, sizeof(pcc_param.bit));
626 memset(xts_ctx->pcc.xts, 0, sizeof(xts_ctx->pcc.xts)); 634 memset(pcc_param.xts, 0, sizeof(pcc_param.xts));
627 memcpy(xts_ctx->pcc.tweak, walk->iv, sizeof(xts_ctx->pcc.tweak)); 635 memcpy(pcc_param.tweak, walk->iv, sizeof(pcc_param.tweak));
628 param = xts_ctx->pcc.key + offset; 636 memcpy(pcc_param.key, xts_ctx->pcc_key, 32);
629 ret = crypt_s390_pcc(func, param); 637 ret = crypt_s390_pcc(func, &pcc_param.key[offset]);
630 if (ret < 0) 638 if (ret < 0)
631 return -EIO; 639 return -EIO;
632 640
633 memcpy(xts_ctx->xts_param, xts_ctx->pcc.xts, 16); 641 memcpy(xts_param.key, xts_ctx->key, 32);
634 param = xts_ctx->key + offset; 642 memcpy(xts_param.init, pcc_param.xts, 16);
635 do { 643 do {
636 /* only use complete blocks */ 644 /* only use complete blocks */
637 n = nbytes & ~(AES_BLOCK_SIZE - 1); 645 n = nbytes & ~(AES_BLOCK_SIZE - 1);
638 out = walk->dst.virt.addr; 646 out = walk->dst.virt.addr;
639 in = walk->src.virt.addr; 647 in = walk->src.virt.addr;
640 648
641 ret = crypt_s390_km(func, param, out, in, n); 649 ret = crypt_s390_km(func, &xts_param.key[offset], out, in, n);
642 if (ret < 0 || ret != n) 650 if (ret < 0 || ret != n)
643 return -EIO; 651 return -EIO;
644 652
diff --git a/arch/s390/include/asm/page.h b/arch/s390/include/asm/page.h
index 316c8503a3b4..114258eeaacd 100644
--- a/arch/s390/include/asm/page.h
+++ b/arch/s390/include/asm/page.h
@@ -48,33 +48,21 @@ static inline void clear_page(void *page)
48 : "memory", "cc"); 48 : "memory", "cc");
49} 49}
50 50
51/*
52 * copy_page uses the mvcl instruction with 0xb0 padding byte in order to
53 * bypass caches when copying a page. Especially when copying huge pages
54 * this keeps L1 and L2 data caches alive.
55 */
51static inline void copy_page(void *to, void *from) 56static inline void copy_page(void *to, void *from)
52{ 57{
53 if (MACHINE_HAS_MVPG) { 58 register void *reg2 asm ("2") = to;
54 register unsigned long reg0 asm ("0") = 0; 59 register unsigned long reg3 asm ("3") = 0x1000;
55 asm volatile( 60 register void *reg4 asm ("4") = from;
56 " mvpg %0,%1" 61 register unsigned long reg5 asm ("5") = 0xb0001000;
57 : : "a" (to), "a" (from), "d" (reg0) 62 asm volatile(
58 : "memory", "cc"); 63 " mvcl 2,4"
59 } else 64 : "+d" (reg2), "+d" (reg3), "+d" (reg4), "+d" (reg5)
60 asm volatile( 65 : : "memory", "cc");
61 " mvc 0(256,%0),0(%1)\n"
62 " mvc 256(256,%0),256(%1)\n"
63 " mvc 512(256,%0),512(%1)\n"
64 " mvc 768(256,%0),768(%1)\n"
65 " mvc 1024(256,%0),1024(%1)\n"
66 " mvc 1280(256,%0),1280(%1)\n"
67 " mvc 1536(256,%0),1536(%1)\n"
68 " mvc 1792(256,%0),1792(%1)\n"
69 " mvc 2048(256,%0),2048(%1)\n"
70 " mvc 2304(256,%0),2304(%1)\n"
71 " mvc 2560(256,%0),2560(%1)\n"
72 " mvc 2816(256,%0),2816(%1)\n"
73 " mvc 3072(256,%0),3072(%1)\n"
74 " mvc 3328(256,%0),3328(%1)\n"
75 " mvc 3584(256,%0),3584(%1)\n"
76 " mvc 3840(256,%0),3840(%1)\n"
77 : : "a" (to), "a" (from) : "memory");
78} 66}
79 67
80#define clear_user_page(page, vaddr, pg) clear_page(page) 68#define clear_user_page(page, vaddr, pg) clear_page(page)
diff --git a/arch/s390/include/asm/vdso.h b/arch/s390/include/asm/vdso.h
index a73eb2e1e918..bc9746a7d47c 100644
--- a/arch/s390/include/asm/vdso.h
+++ b/arch/s390/include/asm/vdso.h
@@ -26,8 +26,9 @@ struct vdso_data {
26 __u64 wtom_clock_nsec; /* 0x28 */ 26 __u64 wtom_clock_nsec; /* 0x28 */
27 __u32 tz_minuteswest; /* Minutes west of Greenwich 0x30 */ 27 __u32 tz_minuteswest; /* Minutes west of Greenwich 0x30 */
28 __u32 tz_dsttime; /* Type of dst correction 0x34 */ 28 __u32 tz_dsttime; /* Type of dst correction 0x34 */
29 __u32 ectg_available; 29 __u32 ectg_available; /* ECTG instruction present 0x38 */
30 __u32 ntp_mult; /* NTP adjusted multiplier 0x3C */ 30 __u32 tk_mult; /* Mult. used for xtime_nsec 0x3c */
31 __u32 tk_shift; /* Shift used for xtime_nsec 0x40 */
31}; 32};
32 33
33struct vdso_per_cpu_data { 34struct vdso_per_cpu_data {
diff --git a/arch/s390/kernel/asm-offsets.c b/arch/s390/kernel/asm-offsets.c
index 2416138ebd3e..496116cd65ec 100644
--- a/arch/s390/kernel/asm-offsets.c
+++ b/arch/s390/kernel/asm-offsets.c
@@ -65,7 +65,8 @@ int main(void)
65 DEFINE(__VDSO_WTOM_NSEC, offsetof(struct vdso_data, wtom_clock_nsec)); 65 DEFINE(__VDSO_WTOM_NSEC, offsetof(struct vdso_data, wtom_clock_nsec));
66 DEFINE(__VDSO_TIMEZONE, offsetof(struct vdso_data, tz_minuteswest)); 66 DEFINE(__VDSO_TIMEZONE, offsetof(struct vdso_data, tz_minuteswest));
67 DEFINE(__VDSO_ECTG_OK, offsetof(struct vdso_data, ectg_available)); 67 DEFINE(__VDSO_ECTG_OK, offsetof(struct vdso_data, ectg_available));
68 DEFINE(__VDSO_NTP_MULT, offsetof(struct vdso_data, ntp_mult)); 68 DEFINE(__VDSO_TK_MULT, offsetof(struct vdso_data, tk_mult));
69 DEFINE(__VDSO_TK_SHIFT, offsetof(struct vdso_data, tk_shift));
69 DEFINE(__VDSO_ECTG_BASE, offsetof(struct vdso_per_cpu_data, ectg_timer_base)); 70 DEFINE(__VDSO_ECTG_BASE, offsetof(struct vdso_per_cpu_data, ectg_timer_base));
70 DEFINE(__VDSO_ECTG_USER, offsetof(struct vdso_per_cpu_data, ectg_user_time)); 71 DEFINE(__VDSO_ECTG_USER, offsetof(struct vdso_per_cpu_data, ectg_user_time));
71 /* constants used by the vdso */ 72 /* constants used by the vdso */
diff --git a/arch/s390/kernel/compat_signal.c b/arch/s390/kernel/compat_signal.c
index 6e2442978409..95e7ba0fbb7e 100644
--- a/arch/s390/kernel/compat_signal.c
+++ b/arch/s390/kernel/compat_signal.c
@@ -194,7 +194,7 @@ static int restore_sigregs32(struct pt_regs *regs,_sigregs32 __user *sregs)
194 return -EINVAL; 194 return -EINVAL;
195 195
196 /* Use regs->psw.mask instead of PSW_USER_BITS to preserve PER bit. */ 196 /* Use regs->psw.mask instead of PSW_USER_BITS to preserve PER bit. */
197 regs->psw.mask = (regs->psw.mask & ~PSW_MASK_USER) | 197 regs->psw.mask = (regs->psw.mask & ~(PSW_MASK_USER | PSW_MASK_RI)) |
198 (__u64)(user_sregs.regs.psw.mask & PSW32_MASK_USER) << 32 | 198 (__u64)(user_sregs.regs.psw.mask & PSW32_MASK_USER) << 32 |
199 (__u64)(user_sregs.regs.psw.mask & PSW32_MASK_RI) << 32 | 199 (__u64)(user_sregs.regs.psw.mask & PSW32_MASK_RI) << 32 |
200 (__u64)(user_sregs.regs.psw.addr & PSW32_ADDR_AMODE); 200 (__u64)(user_sregs.regs.psw.addr & PSW32_ADDR_AMODE);
diff --git a/arch/s390/kernel/pgm_check.S b/arch/s390/kernel/pgm_check.S
index 4a460c44e17e..813ec7260878 100644
--- a/arch/s390/kernel/pgm_check.S
+++ b/arch/s390/kernel/pgm_check.S
@@ -78,7 +78,7 @@ PGM_CHECK_DEFAULT /* 34 */
78PGM_CHECK_DEFAULT /* 35 */ 78PGM_CHECK_DEFAULT /* 35 */
79PGM_CHECK_DEFAULT /* 36 */ 79PGM_CHECK_DEFAULT /* 36 */
80PGM_CHECK_DEFAULT /* 37 */ 80PGM_CHECK_DEFAULT /* 37 */
81PGM_CHECK_DEFAULT /* 38 */ 81PGM_CHECK_64BIT(do_dat_exception) /* 38 */
82PGM_CHECK_64BIT(do_dat_exception) /* 39 */ 82PGM_CHECK_64BIT(do_dat_exception) /* 39 */
83PGM_CHECK_64BIT(do_dat_exception) /* 3a */ 83PGM_CHECK_64BIT(do_dat_exception) /* 3a */
84PGM_CHECK_64BIT(do_dat_exception) /* 3b */ 84PGM_CHECK_64BIT(do_dat_exception) /* 3b */
diff --git a/arch/s390/kernel/signal.c b/arch/s390/kernel/signal.c
index fb535874a246..d8fd508ccd1e 100644
--- a/arch/s390/kernel/signal.c
+++ b/arch/s390/kernel/signal.c
@@ -94,7 +94,7 @@ static int restore_sigregs(struct pt_regs *regs, _sigregs __user *sregs)
94 return -EINVAL; 94 return -EINVAL;
95 95
96 /* Use regs->psw.mask instead of PSW_USER_BITS to preserve PER bit. */ 96 /* Use regs->psw.mask instead of PSW_USER_BITS to preserve PER bit. */
97 regs->psw.mask = (regs->psw.mask & ~PSW_MASK_USER) | 97 regs->psw.mask = (regs->psw.mask & ~(PSW_MASK_USER | PSW_MASK_RI)) |
98 (user_sregs.regs.psw.mask & (PSW_MASK_USER | PSW_MASK_RI)); 98 (user_sregs.regs.psw.mask & (PSW_MASK_USER | PSW_MASK_RI));
99 /* Check for invalid user address space control. */ 99 /* Check for invalid user address space control. */
100 if ((regs->psw.mask & PSW_MASK_ASC) == PSW_ASC_HOME) 100 if ((regs->psw.mask & PSW_MASK_ASC) == PSW_ASC_HOME)
diff --git a/arch/s390/kernel/time.c b/arch/s390/kernel/time.c
index 064c3082ab33..dd95f1631621 100644
--- a/arch/s390/kernel/time.c
+++ b/arch/s390/kernel/time.c
@@ -108,20 +108,10 @@ static void fixup_clock_comparator(unsigned long long delta)
108 set_clock_comparator(S390_lowcore.clock_comparator); 108 set_clock_comparator(S390_lowcore.clock_comparator);
109} 109}
110 110
111static int s390_next_ktime(ktime_t expires, 111static int s390_next_event(unsigned long delta,
112 struct clock_event_device *evt) 112 struct clock_event_device *evt)
113{ 113{
114 struct timespec ts; 114 S390_lowcore.clock_comparator = get_tod_clock() + delta;
115 u64 nsecs;
116
117 ts.tv_sec = ts.tv_nsec = 0;
118 monotonic_to_bootbased(&ts);
119 nsecs = ktime_to_ns(ktime_add(timespec_to_ktime(ts), expires));
120 do_div(nsecs, 125);
121 S390_lowcore.clock_comparator = sched_clock_base_cc + (nsecs << 9);
122 /* Program the maximum value if we have an overflow (== year 2042) */
123 if (unlikely(S390_lowcore.clock_comparator < sched_clock_base_cc))
124 S390_lowcore.clock_comparator = -1ULL;
125 set_clock_comparator(S390_lowcore.clock_comparator); 115 set_clock_comparator(S390_lowcore.clock_comparator);
126 return 0; 116 return 0;
127} 117}
@@ -146,15 +136,14 @@ void init_cpu_timer(void)
146 cpu = smp_processor_id(); 136 cpu = smp_processor_id();
147 cd = &per_cpu(comparators, cpu); 137 cd = &per_cpu(comparators, cpu);
148 cd->name = "comparator"; 138 cd->name = "comparator";
149 cd->features = CLOCK_EVT_FEAT_ONESHOT | 139 cd->features = CLOCK_EVT_FEAT_ONESHOT;
150 CLOCK_EVT_FEAT_KTIME;
151 cd->mult = 16777; 140 cd->mult = 16777;
152 cd->shift = 12; 141 cd->shift = 12;
153 cd->min_delta_ns = 1; 142 cd->min_delta_ns = 1;
154 cd->max_delta_ns = LONG_MAX; 143 cd->max_delta_ns = LONG_MAX;
155 cd->rating = 400; 144 cd->rating = 400;
156 cd->cpumask = cpumask_of(cpu); 145 cd->cpumask = cpumask_of(cpu);
157 cd->set_next_ktime = s390_next_ktime; 146 cd->set_next_event = s390_next_event;
158 cd->set_mode = s390_set_mode; 147 cd->set_mode = s390_set_mode;
159 148
160 clockevents_register_device(cd); 149 clockevents_register_device(cd);
@@ -221,21 +210,30 @@ struct clocksource * __init clocksource_default_clock(void)
221 return &clocksource_tod; 210 return &clocksource_tod;
222} 211}
223 212
224void update_vsyscall_old(struct timespec *wall_time, struct timespec *wtm, 213void update_vsyscall(struct timekeeper *tk)
225 struct clocksource *clock, u32 mult)
226{ 214{
227 if (clock != &clocksource_tod) 215 u64 nsecps;
216
217 if (tk->clock != &clocksource_tod)
228 return; 218 return;
229 219
230 /* Make userspace gettimeofday spin until we're done. */ 220 /* Make userspace gettimeofday spin until we're done. */
231 ++vdso_data->tb_update_count; 221 ++vdso_data->tb_update_count;
232 smp_wmb(); 222 smp_wmb();
233 vdso_data->xtime_tod_stamp = clock->cycle_last; 223 vdso_data->xtime_tod_stamp = tk->clock->cycle_last;
234 vdso_data->xtime_clock_sec = wall_time->tv_sec; 224 vdso_data->xtime_clock_sec = tk->xtime_sec;
235 vdso_data->xtime_clock_nsec = wall_time->tv_nsec; 225 vdso_data->xtime_clock_nsec = tk->xtime_nsec;
236 vdso_data->wtom_clock_sec = wtm->tv_sec; 226 vdso_data->wtom_clock_sec =
237 vdso_data->wtom_clock_nsec = wtm->tv_nsec; 227 tk->xtime_sec + tk->wall_to_monotonic.tv_sec;
238 vdso_data->ntp_mult = mult; 228 vdso_data->wtom_clock_nsec = tk->xtime_nsec +
229 + (tk->wall_to_monotonic.tv_nsec << tk->shift);
230 nsecps = (u64) NSEC_PER_SEC << tk->shift;
231 while (vdso_data->wtom_clock_nsec >= nsecps) {
232 vdso_data->wtom_clock_nsec -= nsecps;
233 vdso_data->wtom_clock_sec++;
234 }
235 vdso_data->tk_mult = tk->mult;
236 vdso_data->tk_shift = tk->shift;
239 smp_wmb(); 237 smp_wmb();
240 ++vdso_data->tb_update_count; 238 ++vdso_data->tb_update_count;
241} 239}
diff --git a/arch/s390/kernel/vdso32/clock_gettime.S b/arch/s390/kernel/vdso32/clock_gettime.S
index b2224e0b974c..5be8e472f57d 100644
--- a/arch/s390/kernel/vdso32/clock_gettime.S
+++ b/arch/s390/kernel/vdso32/clock_gettime.S
@@ -38,25 +38,26 @@ __kernel_clock_gettime:
38 sl %r1,__VDSO_XTIME_STAMP+4(%r5) 38 sl %r1,__VDSO_XTIME_STAMP+4(%r5)
39 brc 3,2f 39 brc 3,2f
40 ahi %r0,-1 40 ahi %r0,-1
412: ms %r0,__VDSO_NTP_MULT(%r5) /* cyc2ns(clock,cycle_delta) */ 412: ms %r0,__VDSO_TK_MULT(%r5) /* * tk->mult */
42 lr %r2,%r0 42 lr %r2,%r0
43 l %r0,__VDSO_NTP_MULT(%r5) 43 l %r0,__VDSO_TK_MULT(%r5)
44 ltr %r1,%r1 44 ltr %r1,%r1
45 mr %r0,%r0 45 mr %r0,%r0
46 jnm 3f 46 jnm 3f
47 a %r0,__VDSO_NTP_MULT(%r5) 47 a %r0,__VDSO_TK_MULT(%r5)
483: alr %r0,%r2 483: alr %r0,%r2
49 srdl %r0,12 49 al %r0,__VDSO_XTIME_NSEC(%r5) /* + tk->xtime_nsec */
50 al %r0,__VDSO_XTIME_NSEC(%r5) /* + xtime */
51 al %r1,__VDSO_XTIME_NSEC+4(%r5) 50 al %r1,__VDSO_XTIME_NSEC+4(%r5)
52 brc 12,4f 51 brc 12,4f
53 ahi %r0,1 52 ahi %r0,1
544: l %r2,__VDSO_XTIME_SEC+4(%r5) 534: al %r0,__VDSO_WTOM_NSEC(%r5) /* + wall_to_monotonic.nsec */
55 al %r0,__VDSO_WTOM_NSEC(%r5) /* + wall_to_monotonic */
56 al %r1,__VDSO_WTOM_NSEC+4(%r5) 54 al %r1,__VDSO_WTOM_NSEC+4(%r5)
57 brc 12,5f 55 brc 12,5f
58 ahi %r0,1 56 ahi %r0,1
595: al %r2,__VDSO_WTOM_SEC+4(%r5) 575: l %r2,__VDSO_TK_SHIFT(%r5) /* Timekeeper shift */
58 srdl %r0,0(%r2) /* >> tk->shift */
59 l %r2,__VDSO_XTIME_SEC+4(%r5)
60 al %r2,__VDSO_WTOM_SEC+4(%r5)
60 cl %r4,__VDSO_UPD_COUNT+4(%r5) /* check update counter */ 61 cl %r4,__VDSO_UPD_COUNT+4(%r5) /* check update counter */
61 jne 1b 62 jne 1b
62 basr %r5,0 63 basr %r5,0
@@ -86,20 +87,21 @@ __kernel_clock_gettime:
86 sl %r1,__VDSO_XTIME_STAMP+4(%r5) 87 sl %r1,__VDSO_XTIME_STAMP+4(%r5)
87 brc 3,12f 88 brc 3,12f
88 ahi %r0,-1 89 ahi %r0,-1
8912: ms %r0,__VDSO_NTP_MULT(%r5) /* cyc2ns(clock,cycle_delta) */ 9012: ms %r0,__VDSO_TK_MULT(%r5) /* * tk->mult */
90 lr %r2,%r0 91 lr %r2,%r0
91 l %r0,__VDSO_NTP_MULT(%r5) 92 l %r0,__VDSO_TK_MULT(%r5)
92 ltr %r1,%r1 93 ltr %r1,%r1
93 mr %r0,%r0 94 mr %r0,%r0
94 jnm 13f 95 jnm 13f
95 a %r0,__VDSO_NTP_MULT(%r5) 96 a %r0,__VDSO_TK_MULT(%r5)
9613: alr %r0,%r2 9713: alr %r0,%r2
97 srdl %r0,12 98 al %r0,__VDSO_XTIME_NSEC(%r5) /* + tk->xtime_nsec */
98 al %r0,__VDSO_XTIME_NSEC(%r5) /* + xtime */
99 al %r1,__VDSO_XTIME_NSEC+4(%r5) 99 al %r1,__VDSO_XTIME_NSEC+4(%r5)
100 brc 12,14f 100 brc 12,14f
101 ahi %r0,1 101 ahi %r0,1
10214: l %r2,__VDSO_XTIME_SEC+4(%r5) 10214: l %r2,__VDSO_TK_SHIFT(%r5) /* Timekeeper shift */
103 srdl %r0,0(%r2) /* >> tk->shift */
104 l %r2,__VDSO_XTIME_SEC+4(%r5)
103 cl %r4,__VDSO_UPD_COUNT+4(%r5) /* check update counter */ 105 cl %r4,__VDSO_UPD_COUNT+4(%r5) /* check update counter */
104 jne 11b 106 jne 11b
105 basr %r5,0 107 basr %r5,0
diff --git a/arch/s390/kernel/vdso32/gettimeofday.S b/arch/s390/kernel/vdso32/gettimeofday.S
index 2d3633175e3b..fd621a950f7c 100644
--- a/arch/s390/kernel/vdso32/gettimeofday.S
+++ b/arch/s390/kernel/vdso32/gettimeofday.S
@@ -35,15 +35,14 @@ __kernel_gettimeofday:
35 sl %r1,__VDSO_XTIME_STAMP+4(%r5) 35 sl %r1,__VDSO_XTIME_STAMP+4(%r5)
36 brc 3,3f 36 brc 3,3f
37 ahi %r0,-1 37 ahi %r0,-1
383: ms %r0,__VDSO_NTP_MULT(%r5) /* cyc2ns(clock,cycle_delta) */ 383: ms %r0,__VDSO_TK_MULT(%r5) /* * tk->mult */
39 st %r0,24(%r15) 39 st %r0,24(%r15)
40 l %r0,__VDSO_NTP_MULT(%r5) 40 l %r0,__VDSO_TK_MULT(%r5)
41 ltr %r1,%r1 41 ltr %r1,%r1
42 mr %r0,%r0 42 mr %r0,%r0
43 jnm 4f 43 jnm 4f
44 a %r0,__VDSO_NTP_MULT(%r5) 44 a %r0,__VDSO_TK_MULT(%r5)
454: al %r0,24(%r15) 454: al %r0,24(%r15)
46 srdl %r0,12
47 al %r0,__VDSO_XTIME_NSEC(%r5) /* + xtime */ 46 al %r0,__VDSO_XTIME_NSEC(%r5) /* + xtime */
48 al %r1,__VDSO_XTIME_NSEC+4(%r5) 47 al %r1,__VDSO_XTIME_NSEC+4(%r5)
49 brc 12,5f 48 brc 12,5f
@@ -51,6 +50,8 @@ __kernel_gettimeofday:
515: mvc 24(4,%r15),__VDSO_XTIME_SEC+4(%r5) 505: mvc 24(4,%r15),__VDSO_XTIME_SEC+4(%r5)
52 cl %r4,__VDSO_UPD_COUNT+4(%r5) /* check update counter */ 51 cl %r4,__VDSO_UPD_COUNT+4(%r5) /* check update counter */
53 jne 1b 52 jne 1b
53 l %r4,__VDSO_TK_SHIFT(%r5) /* Timekeeper shift */
54 srdl %r0,0(%r4) /* >> tk->shift */
54 l %r4,24(%r15) /* get tv_sec from stack */ 55 l %r4,24(%r15) /* get tv_sec from stack */
55 basr %r5,0 56 basr %r5,0
566: ltr %r0,%r0 576: ltr %r0,%r0
diff --git a/arch/s390/kernel/vdso64/clock_gettime.S b/arch/s390/kernel/vdso64/clock_gettime.S
index d46c95ed5f19..0add1072ba30 100644
--- a/arch/s390/kernel/vdso64/clock_gettime.S
+++ b/arch/s390/kernel/vdso64/clock_gettime.S
@@ -34,14 +34,15 @@ __kernel_clock_gettime:
34 tmll %r4,0x0001 /* pending update ? loop */ 34 tmll %r4,0x0001 /* pending update ? loop */
35 jnz 0b 35 jnz 0b
36 stck 48(%r15) /* Store TOD clock */ 36 stck 48(%r15) /* Store TOD clock */
37 lgf %r2,__VDSO_TK_SHIFT(%r5) /* Timekeeper shift */
38 lg %r0,__VDSO_XTIME_SEC(%r5) /* tk->xtime_sec */
39 alg %r0,__VDSO_WTOM_SEC(%r5) /* + wall_to_monotonic.sec */
37 lg %r1,48(%r15) 40 lg %r1,48(%r15)
38 sg %r1,__VDSO_XTIME_STAMP(%r5) /* TOD - cycle_last */ 41 sg %r1,__VDSO_XTIME_STAMP(%r5) /* TOD - cycle_last */
39 msgf %r1,__VDSO_NTP_MULT(%r5) /* * NTP adjustment */ 42 msgf %r1,__VDSO_TK_MULT(%r5) /* * tk->mult */
40 srlg %r1,%r1,12 /* cyc2ns(clock,cycle_delta) */ 43 alg %r1,__VDSO_XTIME_NSEC(%r5) /* + tk->xtime_nsec */
41 alg %r1,__VDSO_XTIME_NSEC(%r5) /* + xtime */ 44 alg %r1,__VDSO_WTOM_NSEC(%r5) /* + wall_to_monotonic.nsec */
42 lg %r0,__VDSO_XTIME_SEC(%r5) 45 srlg %r1,%r1,0(%r2) /* >> tk->shift */
43 alg %r1,__VDSO_WTOM_NSEC(%r5) /* + wall_to_monotonic */
44 alg %r0,__VDSO_WTOM_SEC(%r5)
45 clg %r4,__VDSO_UPD_COUNT(%r5) /* check update counter */ 46 clg %r4,__VDSO_UPD_COUNT(%r5) /* check update counter */
46 jne 0b 47 jne 0b
47 larl %r5,13f 48 larl %r5,13f
@@ -62,12 +63,13 @@ __kernel_clock_gettime:
62 tmll %r4,0x0001 /* pending update ? loop */ 63 tmll %r4,0x0001 /* pending update ? loop */
63 jnz 5b 64 jnz 5b
64 stck 48(%r15) /* Store TOD clock */ 65 stck 48(%r15) /* Store TOD clock */
66 lgf %r2,__VDSO_TK_SHIFT(%r5) /* Timekeeper shift */
65 lg %r1,48(%r15) 67 lg %r1,48(%r15)
66 sg %r1,__VDSO_XTIME_STAMP(%r5) /* TOD - cycle_last */ 68 sg %r1,__VDSO_XTIME_STAMP(%r5) /* TOD - cycle_last */
67 msgf %r1,__VDSO_NTP_MULT(%r5) /* * NTP adjustment */ 69 msgf %r1,__VDSO_TK_MULT(%r5) /* * tk->mult */
68 srlg %r1,%r1,12 /* cyc2ns(clock,cycle_delta) */ 70 alg %r1,__VDSO_XTIME_NSEC(%r5) /* + tk->xtime_nsec */
69 alg %r1,__VDSO_XTIME_NSEC(%r5) /* + xtime */ 71 srlg %r1,%r1,0(%r2) /* >> tk->shift */
70 lg %r0,__VDSO_XTIME_SEC(%r5) 72 lg %r0,__VDSO_XTIME_SEC(%r5) /* tk->xtime_sec */
71 clg %r4,__VDSO_UPD_COUNT(%r5) /* check update counter */ 73 clg %r4,__VDSO_UPD_COUNT(%r5) /* check update counter */
72 jne 5b 74 jne 5b
73 larl %r5,13f 75 larl %r5,13f
diff --git a/arch/s390/kernel/vdso64/gettimeofday.S b/arch/s390/kernel/vdso64/gettimeofday.S
index 36ee674722ec..d0860d1d0ccc 100644
--- a/arch/s390/kernel/vdso64/gettimeofday.S
+++ b/arch/s390/kernel/vdso64/gettimeofday.S
@@ -31,12 +31,13 @@ __kernel_gettimeofday:
31 stck 48(%r15) /* Store TOD clock */ 31 stck 48(%r15) /* Store TOD clock */
32 lg %r1,48(%r15) 32 lg %r1,48(%r15)
33 sg %r1,__VDSO_XTIME_STAMP(%r5) /* TOD - cycle_last */ 33 sg %r1,__VDSO_XTIME_STAMP(%r5) /* TOD - cycle_last */
34 msgf %r1,__VDSO_NTP_MULT(%r5) /* * NTP adjustment */ 34 msgf %r1,__VDSO_TK_MULT(%r5) /* * tk->mult */
35 srlg %r1,%r1,12 /* cyc2ns(clock,cycle_delta) */ 35 alg %r1,__VDSO_XTIME_NSEC(%r5) /* + tk->xtime_nsec */
36 alg %r1,__VDSO_XTIME_NSEC(%r5) /* + xtime.tv_nsec */ 36 lg %r0,__VDSO_XTIME_SEC(%r5) /* tk->xtime_sec */
37 lg %r0,__VDSO_XTIME_SEC(%r5) /* xtime.tv_sec */
38 clg %r4,__VDSO_UPD_COUNT(%r5) /* check update counter */ 37 clg %r4,__VDSO_UPD_COUNT(%r5) /* check update counter */
39 jne 0b 38 jne 0b
39 lgf %r5,__VDSO_TK_SHIFT(%r5) /* Timekeeper shift */
40 srlg %r1,%r1,0(%r5) /* >> tk->shift */
40 larl %r5,5f 41 larl %r5,5f
412: clg %r1,0(%r5) 422: clg %r1,0(%r5)
42 jl 3f 43 jl 3f
diff --git a/arch/s390/lib/uaccess_pt.c b/arch/s390/lib/uaccess_pt.c
index 97e03caf7825..dbdab3e7a1a6 100644
--- a/arch/s390/lib/uaccess_pt.c
+++ b/arch/s390/lib/uaccess_pt.c
@@ -78,11 +78,14 @@ static size_t copy_in_kernel(size_t count, void __user *to,
78 * contains the (negative) exception code. 78 * contains the (negative) exception code.
79 */ 79 */
80#ifdef CONFIG_64BIT 80#ifdef CONFIG_64BIT
81
81static unsigned long follow_table(struct mm_struct *mm, 82static unsigned long follow_table(struct mm_struct *mm,
82 unsigned long address, int write) 83 unsigned long address, int write)
83{ 84{
84 unsigned long *table = (unsigned long *)__pa(mm->pgd); 85 unsigned long *table = (unsigned long *)__pa(mm->pgd);
85 86
87 if (unlikely(address > mm->context.asce_limit - 1))
88 return -0x38UL;
86 switch (mm->context.asce_bits & _ASCE_TYPE_MASK) { 89 switch (mm->context.asce_bits & _ASCE_TYPE_MASK) {
87 case _ASCE_TYPE_REGION1: 90 case _ASCE_TYPE_REGION1:
88 table = table + ((address >> 53) & 0x7ff); 91 table = table + ((address >> 53) & 0x7ff);
diff --git a/arch/um/Makefile b/arch/um/Makefile
index 48d92bbe62e9..36e658a4291c 100644
--- a/arch/um/Makefile
+++ b/arch/um/Makefile
@@ -33,12 +33,11 @@ MODE_INCLUDE += -I$(srctree)/$(ARCH_DIR)/include/shared/skas
33 33
34HEADER_ARCH := $(SUBARCH) 34HEADER_ARCH := $(SUBARCH)
35 35
36# Additional ARCH settings for x86 36ifneq ($(filter $(SUBARCH),x86 x86_64 i386),)
37ifeq ($(SUBARCH),i386) 37 HEADER_ARCH := x86
38 HEADER_ARCH := x86
39endif 38endif
40ifeq ($(SUBARCH),x86_64) 39
41 HEADER_ARCH := x86 40ifdef CONFIG_64BIT
42 KBUILD_CFLAGS += -mcmodel=large 41 KBUILD_CFLAGS += -mcmodel=large
43endif 42endif
44 43
diff --git a/arch/um/kernel/sysrq.c b/arch/um/kernel/sysrq.c
index 4d6fdf68edf3..799d7e413bf5 100644
--- a/arch/um/kernel/sysrq.c
+++ b/arch/um/kernel/sysrq.c
@@ -19,7 +19,7 @@ struct stack_frame {
19 unsigned long return_address; 19 unsigned long return_address;
20}; 20};
21 21
22static void print_stack_trace(unsigned long *sp, unsigned long bp) 22static void do_stack_trace(unsigned long *sp, unsigned long bp)
23{ 23{
24 int reliable; 24 int reliable;
25 unsigned long addr; 25 unsigned long addr;
@@ -94,5 +94,5 @@ void show_stack(struct task_struct *task, unsigned long *stack)
94 } 94 }
95 printk(KERN_CONT "\n"); 95 printk(KERN_CONT "\n");
96 96
97 print_stack_trace(sp, bp); 97 do_stack_trace(sp, bp);
98} 98}
diff --git a/arch/x86/Makefile b/arch/x86/Makefile
index 41250fb33985..eda00f9be0cf 100644
--- a/arch/x86/Makefile
+++ b/arch/x86/Makefile
@@ -31,6 +31,9 @@ ifeq ($(CONFIG_X86_32),y)
31 31
32 KBUILD_CFLAGS += -msoft-float -mregparm=3 -freg-struct-return 32 KBUILD_CFLAGS += -msoft-float -mregparm=3 -freg-struct-return
33 33
34 # Don't autogenerate SSE instructions
35 KBUILD_CFLAGS += -mno-sse
36
34 # Never want PIC in a 32-bit kernel, prevent breakage with GCC built 37 # Never want PIC in a 32-bit kernel, prevent breakage with GCC built
35 # with nonstandard options 38 # with nonstandard options
36 KBUILD_CFLAGS += -fno-pic 39 KBUILD_CFLAGS += -fno-pic
@@ -57,8 +60,11 @@ else
57 KBUILD_AFLAGS += -m64 60 KBUILD_AFLAGS += -m64
58 KBUILD_CFLAGS += -m64 61 KBUILD_CFLAGS += -m64
59 62
63 # Don't autogenerate SSE instructions
64 KBUILD_CFLAGS += -mno-sse
65
60 # Use -mpreferred-stack-boundary=3 if supported. 66 # Use -mpreferred-stack-boundary=3 if supported.
61 KBUILD_CFLAGS += $(call cc-option,-mno-sse -mpreferred-stack-boundary=3) 67 KBUILD_CFLAGS += $(call cc-option,-mpreferred-stack-boundary=3)
62 68
63 # FIXME - should be integrated in Makefile.cpu (Makefile_32.cpu) 69 # FIXME - should be integrated in Makefile.cpu (Makefile_32.cpu)
64 cflags-$(CONFIG_MK8) += $(call cc-option,-march=k8) 70 cflags-$(CONFIG_MK8) += $(call cc-option,-march=k8)
diff --git a/arch/x86/crypto/Makefile b/arch/x86/crypto/Makefile
index 7d6ba9db1be9..e0fc24db234a 100644
--- a/arch/x86/crypto/Makefile
+++ b/arch/x86/crypto/Makefile
@@ -3,8 +3,9 @@
3# 3#
4 4
5avx_supported := $(call as-instr,vpxor %xmm0$(comma)%xmm0$(comma)%xmm0,yes,no) 5avx_supported := $(call as-instr,vpxor %xmm0$(comma)%xmm0$(comma)%xmm0,yes,no)
6avx2_supported := $(call as-instr,vpgatherdd %ymm0$(comma)(%eax$(comma)%ymm1\
7 $(comma)4)$(comma)%ymm2,yes,no)
6 8
7obj-$(CONFIG_CRYPTO_ABLK_HELPER_X86) += ablk_helper.o
8obj-$(CONFIG_CRYPTO_GLUE_HELPER_X86) += glue_helper.o 9obj-$(CONFIG_CRYPTO_GLUE_HELPER_X86) += glue_helper.o
9 10
10obj-$(CONFIG_CRYPTO_AES_586) += aes-i586.o 11obj-$(CONFIG_CRYPTO_AES_586) += aes-i586.o
diff --git a/arch/x86/crypto/aesni-intel_glue.c b/arch/x86/crypto/aesni-intel_glue.c
index f80e668785c0..835488b745ee 100644
--- a/arch/x86/crypto/aesni-intel_glue.c
+++ b/arch/x86/crypto/aesni-intel_glue.c
@@ -34,7 +34,7 @@
34#include <asm/cpu_device_id.h> 34#include <asm/cpu_device_id.h>
35#include <asm/i387.h> 35#include <asm/i387.h>
36#include <asm/crypto/aes.h> 36#include <asm/crypto/aes.h>
37#include <asm/crypto/ablk_helper.h> 37#include <crypto/ablk_helper.h>
38#include <crypto/scatterwalk.h> 38#include <crypto/scatterwalk.h>
39#include <crypto/internal/aead.h> 39#include <crypto/internal/aead.h>
40#include <linux/workqueue.h> 40#include <linux/workqueue.h>
diff --git a/arch/x86/crypto/camellia_aesni_avx2_glue.c b/arch/x86/crypto/camellia_aesni_avx2_glue.c
index 414fe5d7946b..4209a76fcdaa 100644
--- a/arch/x86/crypto/camellia_aesni_avx2_glue.c
+++ b/arch/x86/crypto/camellia_aesni_avx2_glue.c
@@ -14,6 +14,7 @@
14#include <linux/types.h> 14#include <linux/types.h>
15#include <linux/crypto.h> 15#include <linux/crypto.h>
16#include <linux/err.h> 16#include <linux/err.h>
17#include <crypto/ablk_helper.h>
17#include <crypto/algapi.h> 18#include <crypto/algapi.h>
18#include <crypto/ctr.h> 19#include <crypto/ctr.h>
19#include <crypto/lrw.h> 20#include <crypto/lrw.h>
@@ -21,7 +22,6 @@
21#include <asm/xcr.h> 22#include <asm/xcr.h>
22#include <asm/xsave.h> 23#include <asm/xsave.h>
23#include <asm/crypto/camellia.h> 24#include <asm/crypto/camellia.h>
24#include <asm/crypto/ablk_helper.h>
25#include <asm/crypto/glue_helper.h> 25#include <asm/crypto/glue_helper.h>
26 26
27#define CAMELLIA_AESNI_PARALLEL_BLOCKS 16 27#define CAMELLIA_AESNI_PARALLEL_BLOCKS 16
diff --git a/arch/x86/crypto/camellia_aesni_avx_glue.c b/arch/x86/crypto/camellia_aesni_avx_glue.c
index 37fd0c0a81ea..87a041a10f4a 100644
--- a/arch/x86/crypto/camellia_aesni_avx_glue.c
+++ b/arch/x86/crypto/camellia_aesni_avx_glue.c
@@ -14,6 +14,7 @@
14#include <linux/types.h> 14#include <linux/types.h>
15#include <linux/crypto.h> 15#include <linux/crypto.h>
16#include <linux/err.h> 16#include <linux/err.h>
17#include <crypto/ablk_helper.h>
17#include <crypto/algapi.h> 18#include <crypto/algapi.h>
18#include <crypto/ctr.h> 19#include <crypto/ctr.h>
19#include <crypto/lrw.h> 20#include <crypto/lrw.h>
@@ -21,7 +22,6 @@
21#include <asm/xcr.h> 22#include <asm/xcr.h>
22#include <asm/xsave.h> 23#include <asm/xsave.h>
23#include <asm/crypto/camellia.h> 24#include <asm/crypto/camellia.h>
24#include <asm/crypto/ablk_helper.h>
25#include <asm/crypto/glue_helper.h> 25#include <asm/crypto/glue_helper.h>
26 26
27#define CAMELLIA_AESNI_PARALLEL_BLOCKS 16 27#define CAMELLIA_AESNI_PARALLEL_BLOCKS 16
diff --git a/arch/x86/crypto/cast5_avx_glue.c b/arch/x86/crypto/cast5_avx_glue.c
index c6631813dc11..e6a3700489b9 100644
--- a/arch/x86/crypto/cast5_avx_glue.c
+++ b/arch/x86/crypto/cast5_avx_glue.c
@@ -26,13 +26,13 @@
26#include <linux/types.h> 26#include <linux/types.h>
27#include <linux/crypto.h> 27#include <linux/crypto.h>
28#include <linux/err.h> 28#include <linux/err.h>
29#include <crypto/ablk_helper.h>
29#include <crypto/algapi.h> 30#include <crypto/algapi.h>
30#include <crypto/cast5.h> 31#include <crypto/cast5.h>
31#include <crypto/cryptd.h> 32#include <crypto/cryptd.h>
32#include <crypto/ctr.h> 33#include <crypto/ctr.h>
33#include <asm/xcr.h> 34#include <asm/xcr.h>
34#include <asm/xsave.h> 35#include <asm/xsave.h>
35#include <asm/crypto/ablk_helper.h>
36#include <asm/crypto/glue_helper.h> 36#include <asm/crypto/glue_helper.h>
37 37
38#define CAST5_PARALLEL_BLOCKS 16 38#define CAST5_PARALLEL_BLOCKS 16
diff --git a/arch/x86/crypto/cast6_avx_glue.c b/arch/x86/crypto/cast6_avx_glue.c
index 8d0dfb86a559..09f3677393e4 100644
--- a/arch/x86/crypto/cast6_avx_glue.c
+++ b/arch/x86/crypto/cast6_avx_glue.c
@@ -28,6 +28,7 @@
28#include <linux/types.h> 28#include <linux/types.h>
29#include <linux/crypto.h> 29#include <linux/crypto.h>
30#include <linux/err.h> 30#include <linux/err.h>
31#include <crypto/ablk_helper.h>
31#include <crypto/algapi.h> 32#include <crypto/algapi.h>
32#include <crypto/cast6.h> 33#include <crypto/cast6.h>
33#include <crypto/cryptd.h> 34#include <crypto/cryptd.h>
@@ -37,7 +38,6 @@
37#include <crypto/xts.h> 38#include <crypto/xts.h>
38#include <asm/xcr.h> 39#include <asm/xcr.h>
39#include <asm/xsave.h> 40#include <asm/xsave.h>
40#include <asm/crypto/ablk_helper.h>
41#include <asm/crypto/glue_helper.h> 41#include <asm/crypto/glue_helper.h>
42 42
43#define CAST6_PARALLEL_BLOCKS 8 43#define CAST6_PARALLEL_BLOCKS 8
diff --git a/arch/x86/crypto/serpent_avx2_glue.c b/arch/x86/crypto/serpent_avx2_glue.c
index 23aabc6c20a5..2fae489b1524 100644
--- a/arch/x86/crypto/serpent_avx2_glue.c
+++ b/arch/x86/crypto/serpent_avx2_glue.c
@@ -14,6 +14,7 @@
14#include <linux/types.h> 14#include <linux/types.h>
15#include <linux/crypto.h> 15#include <linux/crypto.h>
16#include <linux/err.h> 16#include <linux/err.h>
17#include <crypto/ablk_helper.h>
17#include <crypto/algapi.h> 18#include <crypto/algapi.h>
18#include <crypto/ctr.h> 19#include <crypto/ctr.h>
19#include <crypto/lrw.h> 20#include <crypto/lrw.h>
@@ -22,7 +23,6 @@
22#include <asm/xcr.h> 23#include <asm/xcr.h>
23#include <asm/xsave.h> 24#include <asm/xsave.h>
24#include <asm/crypto/serpent-avx.h> 25#include <asm/crypto/serpent-avx.h>
25#include <asm/crypto/ablk_helper.h>
26#include <asm/crypto/glue_helper.h> 26#include <asm/crypto/glue_helper.h>
27 27
28#define SERPENT_AVX2_PARALLEL_BLOCKS 16 28#define SERPENT_AVX2_PARALLEL_BLOCKS 16
diff --git a/arch/x86/crypto/serpent_avx_glue.c b/arch/x86/crypto/serpent_avx_glue.c
index 9ae83cf8d21e..ff4870870972 100644
--- a/arch/x86/crypto/serpent_avx_glue.c
+++ b/arch/x86/crypto/serpent_avx_glue.c
@@ -28,6 +28,7 @@
28#include <linux/types.h> 28#include <linux/types.h>
29#include <linux/crypto.h> 29#include <linux/crypto.h>
30#include <linux/err.h> 30#include <linux/err.h>
31#include <crypto/ablk_helper.h>
31#include <crypto/algapi.h> 32#include <crypto/algapi.h>
32#include <crypto/serpent.h> 33#include <crypto/serpent.h>
33#include <crypto/cryptd.h> 34#include <crypto/cryptd.h>
@@ -38,7 +39,6 @@
38#include <asm/xcr.h> 39#include <asm/xcr.h>
39#include <asm/xsave.h> 40#include <asm/xsave.h>
40#include <asm/crypto/serpent-avx.h> 41#include <asm/crypto/serpent-avx.h>
41#include <asm/crypto/ablk_helper.h>
42#include <asm/crypto/glue_helper.h> 42#include <asm/crypto/glue_helper.h>
43 43
44/* 8-way parallel cipher functions */ 44/* 8-way parallel cipher functions */
diff --git a/arch/x86/crypto/serpent_sse2_glue.c b/arch/x86/crypto/serpent_sse2_glue.c
index 97a356ece24d..8c95f8637306 100644
--- a/arch/x86/crypto/serpent_sse2_glue.c
+++ b/arch/x86/crypto/serpent_sse2_glue.c
@@ -34,6 +34,7 @@
34#include <linux/types.h> 34#include <linux/types.h>
35#include <linux/crypto.h> 35#include <linux/crypto.h>
36#include <linux/err.h> 36#include <linux/err.h>
37#include <crypto/ablk_helper.h>
37#include <crypto/algapi.h> 38#include <crypto/algapi.h>
38#include <crypto/serpent.h> 39#include <crypto/serpent.h>
39#include <crypto/cryptd.h> 40#include <crypto/cryptd.h>
@@ -42,7 +43,6 @@
42#include <crypto/lrw.h> 43#include <crypto/lrw.h>
43#include <crypto/xts.h> 44#include <crypto/xts.h>
44#include <asm/crypto/serpent-sse2.h> 45#include <asm/crypto/serpent-sse2.h>
45#include <asm/crypto/ablk_helper.h>
46#include <asm/crypto/glue_helper.h> 46#include <asm/crypto/glue_helper.h>
47 47
48static void serpent_decrypt_cbc_xway(void *ctx, u128 *dst, const u128 *src) 48static void serpent_decrypt_cbc_xway(void *ctx, u128 *dst, const u128 *src)
diff --git a/arch/x86/crypto/sha256_ssse3_glue.c b/arch/x86/crypto/sha256_ssse3_glue.c
index 50226c4b86ed..f248546da1ca 100644
--- a/arch/x86/crypto/sha256_ssse3_glue.c
+++ b/arch/x86/crypto/sha256_ssse3_glue.c
@@ -281,7 +281,7 @@ static int __init sha256_ssse3_mod_init(void)
281 /* allow AVX to override SSSE3, it's a little faster */ 281 /* allow AVX to override SSSE3, it's a little faster */
282 if (avx_usable()) { 282 if (avx_usable()) {
283#ifdef CONFIG_AS_AVX2 283#ifdef CONFIG_AS_AVX2
284 if (boot_cpu_has(X86_FEATURE_AVX2)) 284 if (boot_cpu_has(X86_FEATURE_AVX2) && boot_cpu_has(X86_FEATURE_BMI2))
285 sha256_transform_asm = sha256_transform_rorx; 285 sha256_transform_asm = sha256_transform_rorx;
286 else 286 else
287#endif 287#endif
@@ -319,4 +319,4 @@ MODULE_LICENSE("GPL");
319MODULE_DESCRIPTION("SHA256 Secure Hash Algorithm, Supplemental SSE3 accelerated"); 319MODULE_DESCRIPTION("SHA256 Secure Hash Algorithm, Supplemental SSE3 accelerated");
320 320
321MODULE_ALIAS("sha256"); 321MODULE_ALIAS("sha256");
322MODULE_ALIAS("sha384"); 322MODULE_ALIAS("sha224");
diff --git a/arch/x86/crypto/twofish_avx_glue.c b/arch/x86/crypto/twofish_avx_glue.c
index a62ba541884e..4e3c665be129 100644
--- a/arch/x86/crypto/twofish_avx_glue.c
+++ b/arch/x86/crypto/twofish_avx_glue.c
@@ -28,6 +28,7 @@
28#include <linux/types.h> 28#include <linux/types.h>
29#include <linux/crypto.h> 29#include <linux/crypto.h>
30#include <linux/err.h> 30#include <linux/err.h>
31#include <crypto/ablk_helper.h>
31#include <crypto/algapi.h> 32#include <crypto/algapi.h>
32#include <crypto/twofish.h> 33#include <crypto/twofish.h>
33#include <crypto/cryptd.h> 34#include <crypto/cryptd.h>
@@ -39,7 +40,6 @@
39#include <asm/xcr.h> 40#include <asm/xcr.h>
40#include <asm/xsave.h> 41#include <asm/xsave.h>
41#include <asm/crypto/twofish.h> 42#include <asm/crypto/twofish.h>
42#include <asm/crypto/ablk_helper.h>
43#include <asm/crypto/glue_helper.h> 43#include <asm/crypto/glue_helper.h>
44#include <crypto/scatterwalk.h> 44#include <crypto/scatterwalk.h>
45#include <linux/workqueue.h> 45#include <linux/workqueue.h>
diff --git a/arch/x86/include/asm/atomic.h b/arch/x86/include/asm/atomic.h
index da31c8b8a92d..b17f4f48ecd7 100644
--- a/arch/x86/include/asm/atomic.h
+++ b/arch/x86/include/asm/atomic.h
@@ -77,7 +77,7 @@ static inline void atomic_sub(int i, atomic_t *v)
77 */ 77 */
78static inline int atomic_sub_and_test(int i, atomic_t *v) 78static inline int atomic_sub_and_test(int i, atomic_t *v)
79{ 79{
80 GEN_BINARY_RMWcc(LOCK_PREFIX "subl", v->counter, i, "%0", "e"); 80 GEN_BINARY_RMWcc(LOCK_PREFIX "subl", v->counter, "er", i, "%0", "e");
81} 81}
82 82
83/** 83/**
@@ -141,7 +141,7 @@ static inline int atomic_inc_and_test(atomic_t *v)
141 */ 141 */
142static inline int atomic_add_negative(int i, atomic_t *v) 142static inline int atomic_add_negative(int i, atomic_t *v)
143{ 143{
144 GEN_BINARY_RMWcc(LOCK_PREFIX "addl", v->counter, i, "%0", "s"); 144 GEN_BINARY_RMWcc(LOCK_PREFIX "addl", v->counter, "er", i, "%0", "s");
145} 145}
146 146
147/** 147/**
diff --git a/arch/x86/include/asm/atomic64_64.h b/arch/x86/include/asm/atomic64_64.h
index 3f065c985aee..46e9052bbd28 100644
--- a/arch/x86/include/asm/atomic64_64.h
+++ b/arch/x86/include/asm/atomic64_64.h
@@ -72,7 +72,7 @@ static inline void atomic64_sub(long i, atomic64_t *v)
72 */ 72 */
73static inline int atomic64_sub_and_test(long i, atomic64_t *v) 73static inline int atomic64_sub_and_test(long i, atomic64_t *v)
74{ 74{
75 GEN_BINARY_RMWcc(LOCK_PREFIX "subq", v->counter, i, "%0", "e"); 75 GEN_BINARY_RMWcc(LOCK_PREFIX "subq", v->counter, "er", i, "%0", "e");
76} 76}
77 77
78/** 78/**
@@ -138,7 +138,7 @@ static inline int atomic64_inc_and_test(atomic64_t *v)
138 */ 138 */
139static inline int atomic64_add_negative(long i, atomic64_t *v) 139static inline int atomic64_add_negative(long i, atomic64_t *v)
140{ 140{
141 GEN_BINARY_RMWcc(LOCK_PREFIX "addq", v->counter, i, "%0", "s"); 141 GEN_BINARY_RMWcc(LOCK_PREFIX "addq", v->counter, "er", i, "%0", "s");
142} 142}
143 143
144/** 144/**
diff --git a/arch/x86/include/asm/bitops.h b/arch/x86/include/asm/bitops.h
index 6d76d0935989..9fc1af74dc83 100644
--- a/arch/x86/include/asm/bitops.h
+++ b/arch/x86/include/asm/bitops.h
@@ -205,7 +205,7 @@ static inline void change_bit(long nr, volatile unsigned long *addr)
205 */ 205 */
206static inline int test_and_set_bit(long nr, volatile unsigned long *addr) 206static inline int test_and_set_bit(long nr, volatile unsigned long *addr)
207{ 207{
208 GEN_BINARY_RMWcc(LOCK_PREFIX "bts", *addr, nr, "%0", "c"); 208 GEN_BINARY_RMWcc(LOCK_PREFIX "bts", *addr, "Ir", nr, "%0", "c");
209} 209}
210 210
211/** 211/**
@@ -251,7 +251,7 @@ static inline int __test_and_set_bit(long nr, volatile unsigned long *addr)
251 */ 251 */
252static inline int test_and_clear_bit(long nr, volatile unsigned long *addr) 252static inline int test_and_clear_bit(long nr, volatile unsigned long *addr)
253{ 253{
254 GEN_BINARY_RMWcc(LOCK_PREFIX "btr", *addr, nr, "%0", "c"); 254 GEN_BINARY_RMWcc(LOCK_PREFIX "btr", *addr, "Ir", nr, "%0", "c");
255} 255}
256 256
257/** 257/**
@@ -304,7 +304,7 @@ static inline int __test_and_change_bit(long nr, volatile unsigned long *addr)
304 */ 304 */
305static inline int test_and_change_bit(long nr, volatile unsigned long *addr) 305static inline int test_and_change_bit(long nr, volatile unsigned long *addr)
306{ 306{
307 GEN_BINARY_RMWcc(LOCK_PREFIX "btc", *addr, nr, "%0", "c"); 307 GEN_BINARY_RMWcc(LOCK_PREFIX "btc", *addr, "Ir", nr, "%0", "c");
308} 308}
309 309
310static __always_inline int constant_test_bit(long nr, const volatile unsigned long *addr) 310static __always_inline int constant_test_bit(long nr, const volatile unsigned long *addr)
diff --git a/arch/x86/include/asm/local.h b/arch/x86/include/asm/local.h
index 5b23e605e707..4ad6560847b1 100644
--- a/arch/x86/include/asm/local.h
+++ b/arch/x86/include/asm/local.h
@@ -52,7 +52,7 @@ static inline void local_sub(long i, local_t *l)
52 */ 52 */
53static inline int local_sub_and_test(long i, local_t *l) 53static inline int local_sub_and_test(long i, local_t *l)
54{ 54{
55 GEN_BINARY_RMWcc(_ASM_SUB, l->a.counter, i, "%0", "e"); 55 GEN_BINARY_RMWcc(_ASM_SUB, l->a.counter, "er", i, "%0", "e");
56} 56}
57 57
58/** 58/**
@@ -92,7 +92,7 @@ static inline int local_inc_and_test(local_t *l)
92 */ 92 */
93static inline int local_add_negative(long i, local_t *l) 93static inline int local_add_negative(long i, local_t *l)
94{ 94{
95 GEN_BINARY_RMWcc(_ASM_ADD, l->a.counter, i, "%0", "s"); 95 GEN_BINARY_RMWcc(_ASM_ADD, l->a.counter, "er", i, "%0", "s");
96} 96}
97 97
98/** 98/**
diff --git a/arch/x86/include/asm/rmwcc.h b/arch/x86/include/asm/rmwcc.h
index 1ff990f1de8e..8f7866a5b9a4 100644
--- a/arch/x86/include/asm/rmwcc.h
+++ b/arch/x86/include/asm/rmwcc.h
@@ -16,8 +16,8 @@ cc_label: \
16#define GEN_UNARY_RMWcc(op, var, arg0, cc) \ 16#define GEN_UNARY_RMWcc(op, var, arg0, cc) \
17 __GEN_RMWcc(op " " arg0, var, cc) 17 __GEN_RMWcc(op " " arg0, var, cc)
18 18
19#define GEN_BINARY_RMWcc(op, var, val, arg0, cc) \ 19#define GEN_BINARY_RMWcc(op, var, vcon, val, arg0, cc) \
20 __GEN_RMWcc(op " %1, " arg0, var, cc, "er" (val)) 20 __GEN_RMWcc(op " %1, " arg0, var, cc, vcon (val))
21 21
22#else /* !CC_HAVE_ASM_GOTO */ 22#else /* !CC_HAVE_ASM_GOTO */
23 23
@@ -33,8 +33,8 @@ do { \
33#define GEN_UNARY_RMWcc(op, var, arg0, cc) \ 33#define GEN_UNARY_RMWcc(op, var, arg0, cc) \
34 __GEN_RMWcc(op " " arg0, var, cc) 34 __GEN_RMWcc(op " " arg0, var, cc)
35 35
36#define GEN_BINARY_RMWcc(op, var, val, arg0, cc) \ 36#define GEN_BINARY_RMWcc(op, var, vcon, val, arg0, cc) \
37 __GEN_RMWcc(op " %2, " arg0, var, cc, "er" (val)) 37 __GEN_RMWcc(op " %2, " arg0, var, cc, vcon (val))
38 38
39#endif /* CC_HAVE_ASM_GOTO */ 39#endif /* CC_HAVE_ASM_GOTO */
40 40
diff --git a/arch/x86/include/asm/simd.h b/arch/x86/include/asm/simd.h
new file mode 100644
index 000000000000..ee80b92f0096
--- /dev/null
+++ b/arch/x86/include/asm/simd.h
@@ -0,0 +1,11 @@
1
2#include <asm/i387.h>
3
4/*
5 * may_use_simd - whether it is allowable at this time to issue SIMD
6 * instructions or access the SIMD register file
7 */
8static __must_check inline bool may_use_simd(void)
9{
10 return irq_fpu_usable();
11}
diff --git a/arch/x86/include/asm/trace/irq_vectors.h b/arch/x86/include/asm/trace/irq_vectors.h
index 2874df24e7a4..4cab890007a7 100644
--- a/arch/x86/include/asm/trace/irq_vectors.h
+++ b/arch/x86/include/asm/trace/irq_vectors.h
@@ -72,6 +72,17 @@ DEFINE_IRQ_VECTOR_EVENT(x86_platform_ipi);
72DEFINE_IRQ_VECTOR_EVENT(irq_work); 72DEFINE_IRQ_VECTOR_EVENT(irq_work);
73 73
74/* 74/*
75 * We must dis-allow sampling irq_work_exit() because perf event sampling
76 * itself can cause irq_work, which would lead to an infinite loop;
77 *
78 * 1) irq_work_exit happens
79 * 2) generates perf sample
80 * 3) generates irq_work
81 * 4) goto 1
82 */
83TRACE_EVENT_PERF_PERM(irq_work_exit, is_sampling_event(p_event) ? -EPERM : 0);
84
85/*
75 * call_function - called when entering/exiting a call function interrupt 86 * call_function - called when entering/exiting a call function interrupt
76 * vector handler 87 * vector handler
77 */ 88 */
diff --git a/arch/x86/kernel/reboot.c b/arch/x86/kernel/reboot.c
index da3c599584a3..c752cb43e52f 100644
--- a/arch/x86/kernel/reboot.c
+++ b/arch/x86/kernel/reboot.c
@@ -558,6 +558,17 @@ void native_machine_shutdown(void)
558{ 558{
559 /* Stop the cpus and apics */ 559 /* Stop the cpus and apics */
560#ifdef CONFIG_X86_IO_APIC 560#ifdef CONFIG_X86_IO_APIC
561 /*
562 * Disabling IO APIC before local APIC is a workaround for
563 * erratum AVR31 in "Intel Atom Processor C2000 Product Family
564 * Specification Update". In this situation, interrupts that target
565 * a Logical Processor whose Local APIC is either in the process of
566 * being hardware disabled or software disabled are neither delivered
567 * nor discarded. When this erratum occurs, the processor may hang.
568 *
569 * Even without the erratum, it still makes sense to quiet IO APIC
570 * before disabling Local APIC.
571 */
561 disable_IO_APIC(); 572 disable_IO_APIC();
562#endif 573#endif
563 574
diff --git a/arch/x86/platform/efi/early_printk.c b/arch/x86/platform/efi/early_printk.c
index 6599a0027b76..81b506d5befd 100644
--- a/arch/x86/platform/efi/early_printk.c
+++ b/arch/x86/platform/efi/early_printk.c
@@ -142,7 +142,7 @@ early_efi_write(struct console *con, const char *str, unsigned int num)
142 efi_y += font->height; 142 efi_y += font->height;
143 } 143 }
144 144
145 if (efi_y + font->height >= si->lfb_height) { 145 if (efi_y + font->height > si->lfb_height) {
146 u32 i; 146 u32 i;
147 147
148 efi_y -= font->height; 148 efi_y -= font->height;
diff --git a/block/blk-cgroup.h b/block/blk-cgroup.h
index 1610b22edf09..86154eab9523 100644
--- a/block/blk-cgroup.h
+++ b/block/blk-cgroup.h
@@ -435,9 +435,9 @@ static inline uint64_t blkg_stat_read(struct blkg_stat *stat)
435 uint64_t v; 435 uint64_t v;
436 436
437 do { 437 do {
438 start = u64_stats_fetch_begin(&stat->syncp); 438 start = u64_stats_fetch_begin_bh(&stat->syncp);
439 v = stat->cnt; 439 v = stat->cnt;
440 } while (u64_stats_fetch_retry(&stat->syncp, start)); 440 } while (u64_stats_fetch_retry_bh(&stat->syncp, start));
441 441
442 return v; 442 return v;
443} 443}
@@ -508,9 +508,9 @@ static inline struct blkg_rwstat blkg_rwstat_read(struct blkg_rwstat *rwstat)
508 struct blkg_rwstat tmp; 508 struct blkg_rwstat tmp;
509 509
510 do { 510 do {
511 start = u64_stats_fetch_begin(&rwstat->syncp); 511 start = u64_stats_fetch_begin_bh(&rwstat->syncp);
512 tmp = *rwstat; 512 tmp = *rwstat;
513 } while (u64_stats_fetch_retry(&rwstat->syncp, start)); 513 } while (u64_stats_fetch_retry_bh(&rwstat->syncp, start));
514 514
515 return tmp; 515 return tmp;
516} 516}
diff --git a/block/blk-flush.c b/block/blk-flush.c
index 331e627301ea..fb6f3c0ffa49 100644
--- a/block/blk-flush.c
+++ b/block/blk-flush.c
@@ -502,15 +502,6 @@ void blk_abort_flushes(struct request_queue *q)
502 } 502 }
503} 503}
504 504
505static void bio_end_flush(struct bio *bio, int err)
506{
507 if (err)
508 clear_bit(BIO_UPTODATE, &bio->bi_flags);
509 if (bio->bi_private)
510 complete(bio->bi_private);
511 bio_put(bio);
512}
513
514/** 505/**
515 * blkdev_issue_flush - queue a flush 506 * blkdev_issue_flush - queue a flush
516 * @bdev: blockdev to issue flush for 507 * @bdev: blockdev to issue flush for
@@ -526,7 +517,6 @@ static void bio_end_flush(struct bio *bio, int err)
526int blkdev_issue_flush(struct block_device *bdev, gfp_t gfp_mask, 517int blkdev_issue_flush(struct block_device *bdev, gfp_t gfp_mask,
527 sector_t *error_sector) 518 sector_t *error_sector)
528{ 519{
529 DECLARE_COMPLETION_ONSTACK(wait);
530 struct request_queue *q; 520 struct request_queue *q;
531 struct bio *bio; 521 struct bio *bio;
532 int ret = 0; 522 int ret = 0;
@@ -548,13 +538,9 @@ int blkdev_issue_flush(struct block_device *bdev, gfp_t gfp_mask,
548 return -ENXIO; 538 return -ENXIO;
549 539
550 bio = bio_alloc(gfp_mask, 0); 540 bio = bio_alloc(gfp_mask, 0);
551 bio->bi_end_io = bio_end_flush;
552 bio->bi_bdev = bdev; 541 bio->bi_bdev = bdev;
553 bio->bi_private = &wait;
554 542
555 bio_get(bio); 543 ret = submit_bio_wait(WRITE_FLUSH, bio);
556 submit_bio(WRITE_FLUSH, bio);
557 wait_for_completion_io(&wait);
558 544
559 /* 545 /*
560 * The driver must store the error location in ->bi_sector, if 546 * The driver must store the error location in ->bi_sector, if
@@ -564,9 +550,6 @@ int blkdev_issue_flush(struct block_device *bdev, gfp_t gfp_mask,
564 if (error_sector) 550 if (error_sector)
565 *error_sector = bio->bi_sector; 551 *error_sector = bio->bi_sector;
566 552
567 if (!bio_flagged(bio, BIO_UPTODATE))
568 ret = -EIO;
569
570 bio_put(bio); 553 bio_put(bio);
571 return ret; 554 return ret;
572} 555}
diff --git a/block/blk-mq.c b/block/blk-mq.c
index cdc629cf075b..c79126e11030 100644
--- a/block/blk-mq.c
+++ b/block/blk-mq.c
@@ -202,10 +202,12 @@ static struct request *blk_mq_alloc_request_pinned(struct request_queue *q,
202 if (rq) { 202 if (rq) {
203 blk_mq_rq_ctx_init(q, ctx, rq, rw); 203 blk_mq_rq_ctx_init(q, ctx, rq, rw);
204 break; 204 break;
205 } else if (!(gfp & __GFP_WAIT)) 205 }
206 break;
207 206
208 blk_mq_put_ctx(ctx); 207 blk_mq_put_ctx(ctx);
208 if (!(gfp & __GFP_WAIT))
209 break;
210
209 __blk_mq_run_hw_queue(hctx); 211 __blk_mq_run_hw_queue(hctx);
210 blk_mq_wait_for_tags(hctx->tags); 212 blk_mq_wait_for_tags(hctx->tags);
211 } while (1); 213 } while (1);
@@ -222,7 +224,8 @@ struct request *blk_mq_alloc_request(struct request_queue *q, int rw,
222 return NULL; 224 return NULL;
223 225
224 rq = blk_mq_alloc_request_pinned(q, rw, gfp, reserved); 226 rq = blk_mq_alloc_request_pinned(q, rw, gfp, reserved);
225 blk_mq_put_ctx(rq->mq_ctx); 227 if (rq)
228 blk_mq_put_ctx(rq->mq_ctx);
226 return rq; 229 return rq;
227} 230}
228 231
@@ -235,7 +238,8 @@ struct request *blk_mq_alloc_reserved_request(struct request_queue *q, int rw,
235 return NULL; 238 return NULL;
236 239
237 rq = blk_mq_alloc_request_pinned(q, rw, gfp, true); 240 rq = blk_mq_alloc_request_pinned(q, rw, gfp, true);
238 blk_mq_put_ctx(rq->mq_ctx); 241 if (rq)
242 blk_mq_put_ctx(rq->mq_ctx);
239 return rq; 243 return rq;
240} 244}
241EXPORT_SYMBOL(blk_mq_alloc_reserved_request); 245EXPORT_SYMBOL(blk_mq_alloc_reserved_request);
@@ -308,12 +312,12 @@ void blk_mq_complete_request(struct request *rq, int error)
308 312
309 blk_account_io_completion(rq, bytes); 313 blk_account_io_completion(rq, bytes);
310 314
315 blk_account_io_done(rq);
316
311 if (rq->end_io) 317 if (rq->end_io)
312 rq->end_io(rq, error); 318 rq->end_io(rq, error);
313 else 319 else
314 blk_mq_free_request(rq); 320 blk_mq_free_request(rq);
315
316 blk_account_io_done(rq);
317} 321}
318 322
319void __blk_mq_end_io(struct request *rq, int error) 323void __blk_mq_end_io(struct request *rq, int error)
diff --git a/crypto/Kconfig b/crypto/Kconfig
index 4ae5734fb473..7bcb70d216e1 100644
--- a/crypto/Kconfig
+++ b/crypto/Kconfig
@@ -174,9 +174,8 @@ config CRYPTO_TEST
174 help 174 help
175 Quick & dirty crypto test module. 175 Quick & dirty crypto test module.
176 176
177config CRYPTO_ABLK_HELPER_X86 177config CRYPTO_ABLK_HELPER
178 tristate 178 tristate
179 depends on X86
180 select CRYPTO_CRYPTD 179 select CRYPTO_CRYPTD
181 180
182config CRYPTO_GLUE_HELPER_X86 181config CRYPTO_GLUE_HELPER_X86
@@ -695,7 +694,7 @@ config CRYPTO_AES_NI_INTEL
695 select CRYPTO_AES_X86_64 if 64BIT 694 select CRYPTO_AES_X86_64 if 64BIT
696 select CRYPTO_AES_586 if !64BIT 695 select CRYPTO_AES_586 if !64BIT
697 select CRYPTO_CRYPTD 696 select CRYPTO_CRYPTD
698 select CRYPTO_ABLK_HELPER_X86 697 select CRYPTO_ABLK_HELPER
699 select CRYPTO_ALGAPI 698 select CRYPTO_ALGAPI
700 select CRYPTO_GLUE_HELPER_X86 if 64BIT 699 select CRYPTO_GLUE_HELPER_X86 if 64BIT
701 select CRYPTO_LRW 700 select CRYPTO_LRW
@@ -895,7 +894,7 @@ config CRYPTO_CAMELLIA_AESNI_AVX_X86_64
895 depends on CRYPTO 894 depends on CRYPTO
896 select CRYPTO_ALGAPI 895 select CRYPTO_ALGAPI
897 select CRYPTO_CRYPTD 896 select CRYPTO_CRYPTD
898 select CRYPTO_ABLK_HELPER_X86 897 select CRYPTO_ABLK_HELPER
899 select CRYPTO_GLUE_HELPER_X86 898 select CRYPTO_GLUE_HELPER_X86
900 select CRYPTO_CAMELLIA_X86_64 899 select CRYPTO_CAMELLIA_X86_64
901 select CRYPTO_LRW 900 select CRYPTO_LRW
@@ -917,7 +916,7 @@ config CRYPTO_CAMELLIA_AESNI_AVX2_X86_64
917 depends on CRYPTO 916 depends on CRYPTO
918 select CRYPTO_ALGAPI 917 select CRYPTO_ALGAPI
919 select CRYPTO_CRYPTD 918 select CRYPTO_CRYPTD
920 select CRYPTO_ABLK_HELPER_X86 919 select CRYPTO_ABLK_HELPER
921 select CRYPTO_GLUE_HELPER_X86 920 select CRYPTO_GLUE_HELPER_X86
922 select CRYPTO_CAMELLIA_X86_64 921 select CRYPTO_CAMELLIA_X86_64
923 select CRYPTO_CAMELLIA_AESNI_AVX_X86_64 922 select CRYPTO_CAMELLIA_AESNI_AVX_X86_64
@@ -969,7 +968,7 @@ config CRYPTO_CAST5_AVX_X86_64
969 depends on X86 && 64BIT 968 depends on X86 && 64BIT
970 select CRYPTO_ALGAPI 969 select CRYPTO_ALGAPI
971 select CRYPTO_CRYPTD 970 select CRYPTO_CRYPTD
972 select CRYPTO_ABLK_HELPER_X86 971 select CRYPTO_ABLK_HELPER
973 select CRYPTO_CAST_COMMON 972 select CRYPTO_CAST_COMMON
974 select CRYPTO_CAST5 973 select CRYPTO_CAST5
975 help 974 help
@@ -992,7 +991,7 @@ config CRYPTO_CAST6_AVX_X86_64
992 depends on X86 && 64BIT 991 depends on X86 && 64BIT
993 select CRYPTO_ALGAPI 992 select CRYPTO_ALGAPI
994 select CRYPTO_CRYPTD 993 select CRYPTO_CRYPTD
995 select CRYPTO_ABLK_HELPER_X86 994 select CRYPTO_ABLK_HELPER
996 select CRYPTO_GLUE_HELPER_X86 995 select CRYPTO_GLUE_HELPER_X86
997 select CRYPTO_CAST_COMMON 996 select CRYPTO_CAST_COMMON
998 select CRYPTO_CAST6 997 select CRYPTO_CAST6
@@ -1110,7 +1109,7 @@ config CRYPTO_SERPENT_SSE2_X86_64
1110 depends on X86 && 64BIT 1109 depends on X86 && 64BIT
1111 select CRYPTO_ALGAPI 1110 select CRYPTO_ALGAPI
1112 select CRYPTO_CRYPTD 1111 select CRYPTO_CRYPTD
1113 select CRYPTO_ABLK_HELPER_X86 1112 select CRYPTO_ABLK_HELPER
1114 select CRYPTO_GLUE_HELPER_X86 1113 select CRYPTO_GLUE_HELPER_X86
1115 select CRYPTO_SERPENT 1114 select CRYPTO_SERPENT
1116 select CRYPTO_LRW 1115 select CRYPTO_LRW
@@ -1132,7 +1131,7 @@ config CRYPTO_SERPENT_SSE2_586
1132 depends on X86 && !64BIT 1131 depends on X86 && !64BIT
1133 select CRYPTO_ALGAPI 1132 select CRYPTO_ALGAPI
1134 select CRYPTO_CRYPTD 1133 select CRYPTO_CRYPTD
1135 select CRYPTO_ABLK_HELPER_X86 1134 select CRYPTO_ABLK_HELPER
1136 select CRYPTO_GLUE_HELPER_X86 1135 select CRYPTO_GLUE_HELPER_X86
1137 select CRYPTO_SERPENT 1136 select CRYPTO_SERPENT
1138 select CRYPTO_LRW 1137 select CRYPTO_LRW
@@ -1154,7 +1153,7 @@ config CRYPTO_SERPENT_AVX_X86_64
1154 depends on X86 && 64BIT 1153 depends on X86 && 64BIT
1155 select CRYPTO_ALGAPI 1154 select CRYPTO_ALGAPI
1156 select CRYPTO_CRYPTD 1155 select CRYPTO_CRYPTD
1157 select CRYPTO_ABLK_HELPER_X86 1156 select CRYPTO_ABLK_HELPER
1158 select CRYPTO_GLUE_HELPER_X86 1157 select CRYPTO_GLUE_HELPER_X86
1159 select CRYPTO_SERPENT 1158 select CRYPTO_SERPENT
1160 select CRYPTO_LRW 1159 select CRYPTO_LRW
@@ -1176,7 +1175,7 @@ config CRYPTO_SERPENT_AVX2_X86_64
1176 depends on X86 && 64BIT 1175 depends on X86 && 64BIT
1177 select CRYPTO_ALGAPI 1176 select CRYPTO_ALGAPI
1178 select CRYPTO_CRYPTD 1177 select CRYPTO_CRYPTD
1179 select CRYPTO_ABLK_HELPER_X86 1178 select CRYPTO_ABLK_HELPER
1180 select CRYPTO_GLUE_HELPER_X86 1179 select CRYPTO_GLUE_HELPER_X86
1181 select CRYPTO_SERPENT 1180 select CRYPTO_SERPENT
1182 select CRYPTO_SERPENT_AVX_X86_64 1181 select CRYPTO_SERPENT_AVX_X86_64
@@ -1292,7 +1291,7 @@ config CRYPTO_TWOFISH_AVX_X86_64
1292 depends on X86 && 64BIT 1291 depends on X86 && 64BIT
1293 select CRYPTO_ALGAPI 1292 select CRYPTO_ALGAPI
1294 select CRYPTO_CRYPTD 1293 select CRYPTO_CRYPTD
1295 select CRYPTO_ABLK_HELPER_X86 1294 select CRYPTO_ABLK_HELPER
1296 select CRYPTO_GLUE_HELPER_X86 1295 select CRYPTO_GLUE_HELPER_X86
1297 select CRYPTO_TWOFISH_COMMON 1296 select CRYPTO_TWOFISH_COMMON
1298 select CRYPTO_TWOFISH_X86_64 1297 select CRYPTO_TWOFISH_X86_64
diff --git a/crypto/Makefile b/crypto/Makefile
index b3a7e807e08b..989c510da8cc 100644
--- a/crypto/Makefile
+++ b/crypto/Makefile
@@ -2,8 +2,13 @@
2# Cryptographic API 2# Cryptographic API
3# 3#
4 4
5# memneq MUST be built with -Os or -O0 to prevent early-return optimizations
6# that will defeat memneq's actual purpose to prevent timing attacks.
7CFLAGS_REMOVE_memneq.o := -O1 -O2 -O3
8CFLAGS_memneq.o := -Os
9
5obj-$(CONFIG_CRYPTO) += crypto.o 10obj-$(CONFIG_CRYPTO) += crypto.o
6crypto-y := api.o cipher.o compress.o 11crypto-y := api.o cipher.o compress.o memneq.o
7 12
8obj-$(CONFIG_CRYPTO_WORKQUEUE) += crypto_wq.o 13obj-$(CONFIG_CRYPTO_WORKQUEUE) += crypto_wq.o
9 14
@@ -105,3 +110,4 @@ obj-$(CONFIG_XOR_BLOCKS) += xor.o
105obj-$(CONFIG_ASYNC_CORE) += async_tx/ 110obj-$(CONFIG_ASYNC_CORE) += async_tx/
106obj-$(CONFIG_ASYMMETRIC_KEY_TYPE) += asymmetric_keys/ 111obj-$(CONFIG_ASYMMETRIC_KEY_TYPE) += asymmetric_keys/
107obj-$(CONFIG_CRYPTO_HASH_INFO) += hash_info.o 112obj-$(CONFIG_CRYPTO_HASH_INFO) += hash_info.o
113obj-$(CONFIG_CRYPTO_ABLK_HELPER) += ablk_helper.o
diff --git a/arch/x86/crypto/ablk_helper.c b/crypto/ablk_helper.c
index 43282fe04a8b..ffe7278d4bd8 100644
--- a/arch/x86/crypto/ablk_helper.c
+++ b/crypto/ablk_helper.c
@@ -28,10 +28,11 @@
28#include <linux/crypto.h> 28#include <linux/crypto.h>
29#include <linux/init.h> 29#include <linux/init.h>
30#include <linux/module.h> 30#include <linux/module.h>
31#include <linux/hardirq.h>
31#include <crypto/algapi.h> 32#include <crypto/algapi.h>
32#include <crypto/cryptd.h> 33#include <crypto/cryptd.h>
33#include <asm/i387.h> 34#include <crypto/ablk_helper.h>
34#include <asm/crypto/ablk_helper.h> 35#include <asm/simd.h>
35 36
36int ablk_set_key(struct crypto_ablkcipher *tfm, const u8 *key, 37int ablk_set_key(struct crypto_ablkcipher *tfm, const u8 *key,
37 unsigned int key_len) 38 unsigned int key_len)
@@ -70,11 +71,11 @@ int ablk_encrypt(struct ablkcipher_request *req)
70 struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req); 71 struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req);
71 struct async_helper_ctx *ctx = crypto_ablkcipher_ctx(tfm); 72 struct async_helper_ctx *ctx = crypto_ablkcipher_ctx(tfm);
72 73
73 if (!irq_fpu_usable()) { 74 if (!may_use_simd()) {
74 struct ablkcipher_request *cryptd_req = 75 struct ablkcipher_request *cryptd_req =
75 ablkcipher_request_ctx(req); 76 ablkcipher_request_ctx(req);
76 77
77 memcpy(cryptd_req, req, sizeof(*req)); 78 *cryptd_req = *req;
78 ablkcipher_request_set_tfm(cryptd_req, &ctx->cryptd_tfm->base); 79 ablkcipher_request_set_tfm(cryptd_req, &ctx->cryptd_tfm->base);
79 80
80 return crypto_ablkcipher_encrypt(cryptd_req); 81 return crypto_ablkcipher_encrypt(cryptd_req);
@@ -89,11 +90,11 @@ int ablk_decrypt(struct ablkcipher_request *req)
89 struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req); 90 struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req);
90 struct async_helper_ctx *ctx = crypto_ablkcipher_ctx(tfm); 91 struct async_helper_ctx *ctx = crypto_ablkcipher_ctx(tfm);
91 92
92 if (!irq_fpu_usable()) { 93 if (!may_use_simd()) {
93 struct ablkcipher_request *cryptd_req = 94 struct ablkcipher_request *cryptd_req =
94 ablkcipher_request_ctx(req); 95 ablkcipher_request_ctx(req);
95 96
96 memcpy(cryptd_req, req, sizeof(*req)); 97 *cryptd_req = *req;
97 ablkcipher_request_set_tfm(cryptd_req, &ctx->cryptd_tfm->base); 98 ablkcipher_request_set_tfm(cryptd_req, &ctx->cryptd_tfm->base);
98 99
99 return crypto_ablkcipher_decrypt(cryptd_req); 100 return crypto_ablkcipher_decrypt(cryptd_req);
diff --git a/crypto/ablkcipher.c b/crypto/ablkcipher.c
index 7d4a8d28277e..40886c489903 100644
--- a/crypto/ablkcipher.c
+++ b/crypto/ablkcipher.c
@@ -16,9 +16,7 @@
16#include <crypto/internal/skcipher.h> 16#include <crypto/internal/skcipher.h>
17#include <linux/cpumask.h> 17#include <linux/cpumask.h>
18#include <linux/err.h> 18#include <linux/err.h>
19#include <linux/init.h>
20#include <linux/kernel.h> 19#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/rtnetlink.h> 20#include <linux/rtnetlink.h>
23#include <linux/sched.h> 21#include <linux/sched.h>
24#include <linux/slab.h> 22#include <linux/slab.h>
@@ -30,8 +28,6 @@
30 28
31#include "internal.h" 29#include "internal.h"
32 30
33static const char *skcipher_default_geniv __read_mostly;
34
35struct ablkcipher_buffer { 31struct ablkcipher_buffer {
36 struct list_head entry; 32 struct list_head entry;
37 struct scatter_walk dst; 33 struct scatter_walk dst;
@@ -527,8 +523,7 @@ const char *crypto_default_geniv(const struct crypto_alg *alg)
527 alg->cra_blocksize) 523 alg->cra_blocksize)
528 return "chainiv"; 524 return "chainiv";
529 525
530 return alg->cra_flags & CRYPTO_ALG_ASYNC ? 526 return "eseqiv";
531 "eseqiv" : skcipher_default_geniv;
532} 527}
533 528
534static int crypto_givcipher_default(struct crypto_alg *alg, u32 type, u32 mask) 529static int crypto_givcipher_default(struct crypto_alg *alg, u32 type, u32 mask)
@@ -709,17 +704,3 @@ err:
709 return ERR_PTR(err); 704 return ERR_PTR(err);
710} 705}
711EXPORT_SYMBOL_GPL(crypto_alloc_ablkcipher); 706EXPORT_SYMBOL_GPL(crypto_alloc_ablkcipher);
712
713static int __init skcipher_module_init(void)
714{
715 skcipher_default_geniv = num_possible_cpus() > 1 ?
716 "eseqiv" : "chainiv";
717 return 0;
718}
719
720static void skcipher_module_exit(void)
721{
722}
723
724module_init(skcipher_module_init);
725module_exit(skcipher_module_exit);
diff --git a/crypto/algif_hash.c b/crypto/algif_hash.c
index ef5356cd280a..850246206b12 100644
--- a/crypto/algif_hash.c
+++ b/crypto/algif_hash.c
@@ -114,6 +114,9 @@ static ssize_t hash_sendpage(struct socket *sock, struct page *page,
114 struct hash_ctx *ctx = ask->private; 114 struct hash_ctx *ctx = ask->private;
115 int err; 115 int err;
116 116
117 if (flags & MSG_SENDPAGE_NOTLAST)
118 flags |= MSG_MORE;
119
117 lock_sock(sk); 120 lock_sock(sk);
118 sg_init_table(ctx->sgl.sg, 1); 121 sg_init_table(ctx->sgl.sg, 1);
119 sg_set_page(ctx->sgl.sg, page, size, offset); 122 sg_set_page(ctx->sgl.sg, page, size, offset);
diff --git a/crypto/algif_skcipher.c b/crypto/algif_skcipher.c
index 6a6dfc062d2a..a19c027b29bd 100644
--- a/crypto/algif_skcipher.c
+++ b/crypto/algif_skcipher.c
@@ -378,6 +378,9 @@ static ssize_t skcipher_sendpage(struct socket *sock, struct page *page,
378 struct skcipher_sg_list *sgl; 378 struct skcipher_sg_list *sgl;
379 int err = -EINVAL; 379 int err = -EINVAL;
380 380
381 if (flags & MSG_SENDPAGE_NOTLAST)
382 flags |= MSG_MORE;
383
381 lock_sock(sk); 384 lock_sock(sk);
382 if (!ctx->more && ctx->used) 385 if (!ctx->more && ctx->used)
383 goto unlock; 386 goto unlock;
diff --git a/crypto/ansi_cprng.c b/crypto/ansi_cprng.c
index c0bb3778f1ae..666f1962a160 100644
--- a/crypto/ansi_cprng.c
+++ b/crypto/ansi_cprng.c
@@ -230,11 +230,11 @@ remainder:
230 */ 230 */
231 if (byte_count < DEFAULT_BLK_SZ) { 231 if (byte_count < DEFAULT_BLK_SZ) {
232empty_rbuf: 232empty_rbuf:
233 for (; ctx->rand_data_valid < DEFAULT_BLK_SZ; 233 while (ctx->rand_data_valid < DEFAULT_BLK_SZ) {
234 ctx->rand_data_valid++) {
235 *ptr = ctx->rand_data[ctx->rand_data_valid]; 234 *ptr = ctx->rand_data[ctx->rand_data_valid];
236 ptr++; 235 ptr++;
237 byte_count--; 236 byte_count--;
237 ctx->rand_data_valid++;
238 if (byte_count == 0) 238 if (byte_count == 0)
239 goto done; 239 goto done;
240 } 240 }
diff --git a/crypto/asymmetric_keys/rsa.c b/crypto/asymmetric_keys/rsa.c
index 90a17f59ba28..459cf97a75e2 100644
--- a/crypto/asymmetric_keys/rsa.c
+++ b/crypto/asymmetric_keys/rsa.c
@@ -13,6 +13,7 @@
13#include <linux/module.h> 13#include <linux/module.h>
14#include <linux/kernel.h> 14#include <linux/kernel.h>
15#include <linux/slab.h> 15#include <linux/slab.h>
16#include <crypto/algapi.h>
16#include "public_key.h" 17#include "public_key.h"
17 18
18MODULE_LICENSE("GPL"); 19MODULE_LICENSE("GPL");
@@ -189,12 +190,12 @@ static int RSA_verify(const u8 *H, const u8 *EM, size_t k, size_t hash_size,
189 } 190 }
190 } 191 }
191 192
192 if (memcmp(asn1_template, EM + T_offset, asn1_size) != 0) { 193 if (crypto_memneq(asn1_template, EM + T_offset, asn1_size) != 0) {
193 kleave(" = -EBADMSG [EM[T] ASN.1 mismatch]"); 194 kleave(" = -EBADMSG [EM[T] ASN.1 mismatch]");
194 return -EBADMSG; 195 return -EBADMSG;
195 } 196 }
196 197
197 if (memcmp(H, EM + T_offset + asn1_size, hash_size) != 0) { 198 if (crypto_memneq(H, EM + T_offset + asn1_size, hash_size) != 0) {
198 kleave(" = -EKEYREJECTED [EM[T] hash mismatch]"); 199 kleave(" = -EKEYREJECTED [EM[T] hash mismatch]");
199 return -EKEYREJECTED; 200 return -EKEYREJECTED;
200 } 201 }
diff --git a/crypto/asymmetric_keys/x509_public_key.c b/crypto/asymmetric_keys/x509_public_key.c
index f83300b6e8c1..382ef0d2ff2e 100644
--- a/crypto/asymmetric_keys/x509_public_key.c
+++ b/crypto/asymmetric_keys/x509_public_key.c
@@ -18,60 +18,12 @@
18#include <linux/asn1_decoder.h> 18#include <linux/asn1_decoder.h>
19#include <keys/asymmetric-subtype.h> 19#include <keys/asymmetric-subtype.h>
20#include <keys/asymmetric-parser.h> 20#include <keys/asymmetric-parser.h>
21#include <keys/system_keyring.h>
22#include <crypto/hash.h> 21#include <crypto/hash.h>
23#include "asymmetric_keys.h" 22#include "asymmetric_keys.h"
24#include "public_key.h" 23#include "public_key.h"
25#include "x509_parser.h" 24#include "x509_parser.h"
26 25
27/* 26/*
28 * Find a key in the given keyring by issuer and authority.
29 */
30static struct key *x509_request_asymmetric_key(
31 struct key *keyring,
32 const char *signer, size_t signer_len,
33 const char *authority, size_t auth_len)
34{
35 key_ref_t key;
36 char *id;
37
38 /* Construct an identifier. */
39 id = kmalloc(signer_len + 2 + auth_len + 1, GFP_KERNEL);
40 if (!id)
41 return ERR_PTR(-ENOMEM);
42
43 memcpy(id, signer, signer_len);
44 id[signer_len + 0] = ':';
45 id[signer_len + 1] = ' ';
46 memcpy(id + signer_len + 2, authority, auth_len);
47 id[signer_len + 2 + auth_len] = 0;
48
49 pr_debug("Look up: \"%s\"\n", id);
50
51 key = keyring_search(make_key_ref(keyring, 1),
52 &key_type_asymmetric, id);
53 if (IS_ERR(key))
54 pr_debug("Request for module key '%s' err %ld\n",
55 id, PTR_ERR(key));
56 kfree(id);
57
58 if (IS_ERR(key)) {
59 switch (PTR_ERR(key)) {
60 /* Hide some search errors */
61 case -EACCES:
62 case -ENOTDIR:
63 case -EAGAIN:
64 return ERR_PTR(-ENOKEY);
65 default:
66 return ERR_CAST(key);
67 }
68 }
69
70 pr_devel("<==%s() = 0 [%x]\n", __func__, key_serial(key_ref_to_ptr(key)));
71 return key_ref_to_ptr(key);
72}
73
74/*
75 * Set up the signature parameters in an X.509 certificate. This involves 27 * Set up the signature parameters in an X.509 certificate. This involves
76 * digesting the signed data and extracting the signature. 28 * digesting the signed data and extracting the signature.
77 */ 29 */
@@ -151,33 +103,6 @@ int x509_check_signature(const struct public_key *pub,
151EXPORT_SYMBOL_GPL(x509_check_signature); 103EXPORT_SYMBOL_GPL(x509_check_signature);
152 104
153/* 105/*
154 * Check the new certificate against the ones in the trust keyring. If one of
155 * those is the signing key and validates the new certificate, then mark the
156 * new certificate as being trusted.
157 *
158 * Return 0 if the new certificate was successfully validated, 1 if we couldn't
159 * find a matching parent certificate in the trusted list and an error if there
160 * is a matching certificate but the signature check fails.
161 */
162static int x509_validate_trust(struct x509_certificate *cert,
163 struct key *trust_keyring)
164{
165 const struct public_key *pk;
166 struct key *key;
167 int ret = 1;
168
169 key = x509_request_asymmetric_key(trust_keyring,
170 cert->issuer, strlen(cert->issuer),
171 cert->authority,
172 strlen(cert->authority));
173 if (!IS_ERR(key)) {
174 pk = key->payload.data;
175 ret = x509_check_signature(pk, cert);
176 }
177 return ret;
178}
179
180/*
181 * Attempt to parse a data blob for a key as an X509 certificate. 106 * Attempt to parse a data blob for a key as an X509 certificate.
182 */ 107 */
183static int x509_key_preparse(struct key_preparsed_payload *prep) 108static int x509_key_preparse(struct key_preparsed_payload *prep)
@@ -230,13 +155,9 @@ static int x509_key_preparse(struct key_preparsed_payload *prep)
230 /* Check the signature on the key if it appears to be self-signed */ 155 /* Check the signature on the key if it appears to be self-signed */
231 if (!cert->authority || 156 if (!cert->authority ||
232 strcmp(cert->fingerprint, cert->authority) == 0) { 157 strcmp(cert->fingerprint, cert->authority) == 0) {
233 ret = x509_check_signature(cert->pub, cert); /* self-signed */ 158 ret = x509_check_signature(cert->pub, cert);
234 if (ret < 0) 159 if (ret < 0)
235 goto error_free_cert; 160 goto error_free_cert;
236 } else {
237 ret = x509_validate_trust(cert, system_trusted_keyring);
238 if (!ret)
239 prep->trusted = 1;
240 } 161 }
241 162
242 /* Propose a description */ 163 /* Propose a description */
diff --git a/crypto/authenc.c b/crypto/authenc.c
index ffce19de05cf..e1223559d5df 100644
--- a/crypto/authenc.c
+++ b/crypto/authenc.c
@@ -52,40 +52,52 @@ static void authenc_request_complete(struct aead_request *req, int err)
52 aead_request_complete(req, err); 52 aead_request_complete(req, err);
53} 53}
54 54
55static int crypto_authenc_setkey(struct crypto_aead *authenc, const u8 *key, 55int crypto_authenc_extractkeys(struct crypto_authenc_keys *keys, const u8 *key,
56 unsigned int keylen) 56 unsigned int keylen)
57{ 57{
58 unsigned int authkeylen; 58 struct rtattr *rta = (struct rtattr *)key;
59 unsigned int enckeylen;
60 struct crypto_authenc_ctx *ctx = crypto_aead_ctx(authenc);
61 struct crypto_ahash *auth = ctx->auth;
62 struct crypto_ablkcipher *enc = ctx->enc;
63 struct rtattr *rta = (void *)key;
64 struct crypto_authenc_key_param *param; 59 struct crypto_authenc_key_param *param;
65 int err = -EINVAL;
66 60
67 if (!RTA_OK(rta, keylen)) 61 if (!RTA_OK(rta, keylen))
68 goto badkey; 62 return -EINVAL;
69 if (rta->rta_type != CRYPTO_AUTHENC_KEYA_PARAM) 63 if (rta->rta_type != CRYPTO_AUTHENC_KEYA_PARAM)
70 goto badkey; 64 return -EINVAL;
71 if (RTA_PAYLOAD(rta) < sizeof(*param)) 65 if (RTA_PAYLOAD(rta) < sizeof(*param))
72 goto badkey; 66 return -EINVAL;
73 67
74 param = RTA_DATA(rta); 68 param = RTA_DATA(rta);
75 enckeylen = be32_to_cpu(param->enckeylen); 69 keys->enckeylen = be32_to_cpu(param->enckeylen);
76 70
77 key += RTA_ALIGN(rta->rta_len); 71 key += RTA_ALIGN(rta->rta_len);
78 keylen -= RTA_ALIGN(rta->rta_len); 72 keylen -= RTA_ALIGN(rta->rta_len);
79 73
80 if (keylen < enckeylen) 74 if (keylen < keys->enckeylen)
81 goto badkey; 75 return -EINVAL;
82 76
83 authkeylen = keylen - enckeylen; 77 keys->authkeylen = keylen - keys->enckeylen;
78 keys->authkey = key;
79 keys->enckey = key + keys->authkeylen;
80
81 return 0;
82}
83EXPORT_SYMBOL_GPL(crypto_authenc_extractkeys);
84
85static int crypto_authenc_setkey(struct crypto_aead *authenc, const u8 *key,
86 unsigned int keylen)
87{
88 struct crypto_authenc_ctx *ctx = crypto_aead_ctx(authenc);
89 struct crypto_ahash *auth = ctx->auth;
90 struct crypto_ablkcipher *enc = ctx->enc;
91 struct crypto_authenc_keys keys;
92 int err = -EINVAL;
93
94 if (crypto_authenc_extractkeys(&keys, key, keylen) != 0)
95 goto badkey;
84 96
85 crypto_ahash_clear_flags(auth, CRYPTO_TFM_REQ_MASK); 97 crypto_ahash_clear_flags(auth, CRYPTO_TFM_REQ_MASK);
86 crypto_ahash_set_flags(auth, crypto_aead_get_flags(authenc) & 98 crypto_ahash_set_flags(auth, crypto_aead_get_flags(authenc) &
87 CRYPTO_TFM_REQ_MASK); 99 CRYPTO_TFM_REQ_MASK);
88 err = crypto_ahash_setkey(auth, key, authkeylen); 100 err = crypto_ahash_setkey(auth, keys.authkey, keys.authkeylen);
89 crypto_aead_set_flags(authenc, crypto_ahash_get_flags(auth) & 101 crypto_aead_set_flags(authenc, crypto_ahash_get_flags(auth) &
90 CRYPTO_TFM_RES_MASK); 102 CRYPTO_TFM_RES_MASK);
91 103
@@ -95,7 +107,7 @@ static int crypto_authenc_setkey(struct crypto_aead *authenc, const u8 *key,
95 crypto_ablkcipher_clear_flags(enc, CRYPTO_TFM_REQ_MASK); 107 crypto_ablkcipher_clear_flags(enc, CRYPTO_TFM_REQ_MASK);
96 crypto_ablkcipher_set_flags(enc, crypto_aead_get_flags(authenc) & 108 crypto_ablkcipher_set_flags(enc, crypto_aead_get_flags(authenc) &
97 CRYPTO_TFM_REQ_MASK); 109 CRYPTO_TFM_REQ_MASK);
98 err = crypto_ablkcipher_setkey(enc, key + authkeylen, enckeylen); 110 err = crypto_ablkcipher_setkey(enc, keys.enckey, keys.enckeylen);
99 crypto_aead_set_flags(authenc, crypto_ablkcipher_get_flags(enc) & 111 crypto_aead_set_flags(authenc, crypto_ablkcipher_get_flags(enc) &
100 CRYPTO_TFM_RES_MASK); 112 CRYPTO_TFM_RES_MASK);
101 113
@@ -188,7 +200,7 @@ static void authenc_verify_ahash_update_done(struct crypto_async_request *areq,
188 scatterwalk_map_and_copy(ihash, areq_ctx->sg, areq_ctx->cryptlen, 200 scatterwalk_map_and_copy(ihash, areq_ctx->sg, areq_ctx->cryptlen,
189 authsize, 0); 201 authsize, 0);
190 202
191 err = memcmp(ihash, ahreq->result, authsize) ? -EBADMSG : 0; 203 err = crypto_memneq(ihash, ahreq->result, authsize) ? -EBADMSG : 0;
192 if (err) 204 if (err)
193 goto out; 205 goto out;
194 206
@@ -227,7 +239,7 @@ static void authenc_verify_ahash_done(struct crypto_async_request *areq,
227 scatterwalk_map_and_copy(ihash, areq_ctx->sg, areq_ctx->cryptlen, 239 scatterwalk_map_and_copy(ihash, areq_ctx->sg, areq_ctx->cryptlen,
228 authsize, 0); 240 authsize, 0);
229 241
230 err = memcmp(ihash, ahreq->result, authsize) ? -EBADMSG : 0; 242 err = crypto_memneq(ihash, ahreq->result, authsize) ? -EBADMSG : 0;
231 if (err) 243 if (err)
232 goto out; 244 goto out;
233 245
@@ -368,9 +380,10 @@ static void crypto_authenc_encrypt_done(struct crypto_async_request *req,
368 if (!err) { 380 if (!err) {
369 struct crypto_aead *authenc = crypto_aead_reqtfm(areq); 381 struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
370 struct crypto_authenc_ctx *ctx = crypto_aead_ctx(authenc); 382 struct crypto_authenc_ctx *ctx = crypto_aead_ctx(authenc);
371 struct ablkcipher_request *abreq = aead_request_ctx(areq); 383 struct authenc_request_ctx *areq_ctx = aead_request_ctx(areq);
372 u8 *iv = (u8 *)(abreq + 1) + 384 struct ablkcipher_request *abreq = (void *)(areq_ctx->tail
373 crypto_ablkcipher_reqsize(ctx->enc); 385 + ctx->reqoff);
386 u8 *iv = (u8 *)abreq - crypto_ablkcipher_ivsize(ctx->enc);
374 387
375 err = crypto_authenc_genicv(areq, iv, 0); 388 err = crypto_authenc_genicv(areq, iv, 0);
376 } 389 }
@@ -462,7 +475,7 @@ static int crypto_authenc_verify(struct aead_request *req,
462 ihash = ohash + authsize; 475 ihash = ohash + authsize;
463 scatterwalk_map_and_copy(ihash, areq_ctx->sg, areq_ctx->cryptlen, 476 scatterwalk_map_and_copy(ihash, areq_ctx->sg, areq_ctx->cryptlen,
464 authsize, 0); 477 authsize, 0);
465 return memcmp(ihash, ohash, authsize) ? -EBADMSG : 0; 478 return crypto_memneq(ihash, ohash, authsize) ? -EBADMSG : 0;
466} 479}
467 480
468static int crypto_authenc_iverify(struct aead_request *req, u8 *iv, 481static int crypto_authenc_iverify(struct aead_request *req, u8 *iv,
diff --git a/crypto/authencesn.c b/crypto/authencesn.c
index ab53762fc309..4be0dd4373a9 100644
--- a/crypto/authencesn.c
+++ b/crypto/authencesn.c
@@ -59,37 +59,19 @@ static void authenc_esn_request_complete(struct aead_request *req, int err)
59static int crypto_authenc_esn_setkey(struct crypto_aead *authenc_esn, const u8 *key, 59static int crypto_authenc_esn_setkey(struct crypto_aead *authenc_esn, const u8 *key,
60 unsigned int keylen) 60 unsigned int keylen)
61{ 61{
62 unsigned int authkeylen;
63 unsigned int enckeylen;
64 struct crypto_authenc_esn_ctx *ctx = crypto_aead_ctx(authenc_esn); 62 struct crypto_authenc_esn_ctx *ctx = crypto_aead_ctx(authenc_esn);
65 struct crypto_ahash *auth = ctx->auth; 63 struct crypto_ahash *auth = ctx->auth;
66 struct crypto_ablkcipher *enc = ctx->enc; 64 struct crypto_ablkcipher *enc = ctx->enc;
67 struct rtattr *rta = (void *)key; 65 struct crypto_authenc_keys keys;
68 struct crypto_authenc_key_param *param;
69 int err = -EINVAL; 66 int err = -EINVAL;
70 67
71 if (!RTA_OK(rta, keylen)) 68 if (crypto_authenc_extractkeys(&keys, key, keylen) != 0)
72 goto badkey; 69 goto badkey;
73 if (rta->rta_type != CRYPTO_AUTHENC_KEYA_PARAM)
74 goto badkey;
75 if (RTA_PAYLOAD(rta) < sizeof(*param))
76 goto badkey;
77
78 param = RTA_DATA(rta);
79 enckeylen = be32_to_cpu(param->enckeylen);
80
81 key += RTA_ALIGN(rta->rta_len);
82 keylen -= RTA_ALIGN(rta->rta_len);
83
84 if (keylen < enckeylen)
85 goto badkey;
86
87 authkeylen = keylen - enckeylen;
88 70
89 crypto_ahash_clear_flags(auth, CRYPTO_TFM_REQ_MASK); 71 crypto_ahash_clear_flags(auth, CRYPTO_TFM_REQ_MASK);
90 crypto_ahash_set_flags(auth, crypto_aead_get_flags(authenc_esn) & 72 crypto_ahash_set_flags(auth, crypto_aead_get_flags(authenc_esn) &
91 CRYPTO_TFM_REQ_MASK); 73 CRYPTO_TFM_REQ_MASK);
92 err = crypto_ahash_setkey(auth, key, authkeylen); 74 err = crypto_ahash_setkey(auth, keys.authkey, keys.authkeylen);
93 crypto_aead_set_flags(authenc_esn, crypto_ahash_get_flags(auth) & 75 crypto_aead_set_flags(authenc_esn, crypto_ahash_get_flags(auth) &
94 CRYPTO_TFM_RES_MASK); 76 CRYPTO_TFM_RES_MASK);
95 77
@@ -99,7 +81,7 @@ static int crypto_authenc_esn_setkey(struct crypto_aead *authenc_esn, const u8 *
99 crypto_ablkcipher_clear_flags(enc, CRYPTO_TFM_REQ_MASK); 81 crypto_ablkcipher_clear_flags(enc, CRYPTO_TFM_REQ_MASK);
100 crypto_ablkcipher_set_flags(enc, crypto_aead_get_flags(authenc_esn) & 82 crypto_ablkcipher_set_flags(enc, crypto_aead_get_flags(authenc_esn) &
101 CRYPTO_TFM_REQ_MASK); 83 CRYPTO_TFM_REQ_MASK);
102 err = crypto_ablkcipher_setkey(enc, key + authkeylen, enckeylen); 84 err = crypto_ablkcipher_setkey(enc, keys.enckey, keys.enckeylen);
103 crypto_aead_set_flags(authenc_esn, crypto_ablkcipher_get_flags(enc) & 85 crypto_aead_set_flags(authenc_esn, crypto_ablkcipher_get_flags(enc) &
104 CRYPTO_TFM_RES_MASK); 86 CRYPTO_TFM_RES_MASK);
105 87
@@ -247,7 +229,7 @@ static void authenc_esn_verify_ahash_update_done(struct crypto_async_request *ar
247 scatterwalk_map_and_copy(ihash, areq_ctx->sg, areq_ctx->cryptlen, 229 scatterwalk_map_and_copy(ihash, areq_ctx->sg, areq_ctx->cryptlen,
248 authsize, 0); 230 authsize, 0);
249 231
250 err = memcmp(ihash, ahreq->result, authsize) ? -EBADMSG : 0; 232 err = crypto_memneq(ihash, ahreq->result, authsize) ? -EBADMSG : 0;
251 if (err) 233 if (err)
252 goto out; 234 goto out;
253 235
@@ -296,7 +278,7 @@ static void authenc_esn_verify_ahash_update_done2(struct crypto_async_request *a
296 scatterwalk_map_and_copy(ihash, areq_ctx->sg, areq_ctx->cryptlen, 278 scatterwalk_map_and_copy(ihash, areq_ctx->sg, areq_ctx->cryptlen,
297 authsize, 0); 279 authsize, 0);
298 280
299 err = memcmp(ihash, ahreq->result, authsize) ? -EBADMSG : 0; 281 err = crypto_memneq(ihash, ahreq->result, authsize) ? -EBADMSG : 0;
300 if (err) 282 if (err)
301 goto out; 283 goto out;
302 284
@@ -336,7 +318,7 @@ static void authenc_esn_verify_ahash_done(struct crypto_async_request *areq,
336 scatterwalk_map_and_copy(ihash, areq_ctx->sg, areq_ctx->cryptlen, 318 scatterwalk_map_and_copy(ihash, areq_ctx->sg, areq_ctx->cryptlen,
337 authsize, 0); 319 authsize, 0);
338 320
339 err = memcmp(ihash, ahreq->result, authsize) ? -EBADMSG : 0; 321 err = crypto_memneq(ihash, ahreq->result, authsize) ? -EBADMSG : 0;
340 if (err) 322 if (err)
341 goto out; 323 goto out;
342 324
@@ -568,7 +550,7 @@ static int crypto_authenc_esn_verify(struct aead_request *req)
568 ihash = ohash + authsize; 550 ihash = ohash + authsize;
569 scatterwalk_map_and_copy(ihash, areq_ctx->sg, areq_ctx->cryptlen, 551 scatterwalk_map_and_copy(ihash, areq_ctx->sg, areq_ctx->cryptlen,
570 authsize, 0); 552 authsize, 0);
571 return memcmp(ihash, ohash, authsize) ? -EBADMSG : 0; 553 return crypto_memneq(ihash, ohash, authsize) ? -EBADMSG : 0;
572} 554}
573 555
574static int crypto_authenc_esn_iverify(struct aead_request *req, u8 *iv, 556static int crypto_authenc_esn_iverify(struct aead_request *req, u8 *iv,
diff --git a/crypto/ccm.c b/crypto/ccm.c
index 499c91717d93..1df84217f7c9 100644
--- a/crypto/ccm.c
+++ b/crypto/ccm.c
@@ -271,7 +271,8 @@ static int crypto_ccm_auth(struct aead_request *req, struct scatterlist *plain,
271 } 271 }
272 272
273 /* compute plaintext into mac */ 273 /* compute plaintext into mac */
274 get_data_to_compute(cipher, pctx, plain, cryptlen); 274 if (cryptlen)
275 get_data_to_compute(cipher, pctx, plain, cryptlen);
275 276
276out: 277out:
277 return err; 278 return err;
@@ -363,7 +364,7 @@ static void crypto_ccm_decrypt_done(struct crypto_async_request *areq,
363 364
364 if (!err) { 365 if (!err) {
365 err = crypto_ccm_auth(req, req->dst, cryptlen); 366 err = crypto_ccm_auth(req, req->dst, cryptlen);
366 if (!err && memcmp(pctx->auth_tag, pctx->odata, authsize)) 367 if (!err && crypto_memneq(pctx->auth_tag, pctx->odata, authsize))
367 err = -EBADMSG; 368 err = -EBADMSG;
368 } 369 }
369 aead_request_complete(req, err); 370 aead_request_complete(req, err);
@@ -422,7 +423,7 @@ static int crypto_ccm_decrypt(struct aead_request *req)
422 return err; 423 return err;
423 424
424 /* verify */ 425 /* verify */
425 if (memcmp(authtag, odata, authsize)) 426 if (crypto_memneq(authtag, odata, authsize))
426 return -EBADMSG; 427 return -EBADMSG;
427 428
428 return err; 429 return err;
diff --git a/crypto/gcm.c b/crypto/gcm.c
index 43e1fb05ea54..b4f017939004 100644
--- a/crypto/gcm.c
+++ b/crypto/gcm.c
@@ -582,7 +582,7 @@ static int crypto_gcm_verify(struct aead_request *req,
582 582
583 crypto_xor(auth_tag, iauth_tag, 16); 583 crypto_xor(auth_tag, iauth_tag, 16);
584 scatterwalk_map_and_copy(iauth_tag, req->src, cryptlen, authsize, 0); 584 scatterwalk_map_and_copy(iauth_tag, req->src, cryptlen, authsize, 0);
585 return memcmp(iauth_tag, auth_tag, authsize) ? -EBADMSG : 0; 585 return crypto_memneq(iauth_tag, auth_tag, authsize) ? -EBADMSG : 0;
586} 586}
587 587
588static void gcm_decrypt_done(struct crypto_async_request *areq, int err) 588static void gcm_decrypt_done(struct crypto_async_request *areq, int err)
diff --git a/crypto/memneq.c b/crypto/memneq.c
new file mode 100644
index 000000000000..cd0162221c14
--- /dev/null
+++ b/crypto/memneq.c
@@ -0,0 +1,138 @@
1/*
2 * Constant-time equality testing of memory regions.
3 *
4 * Authors:
5 *
6 * James Yonan <james@openvpn.net>
7 * Daniel Borkmann <dborkman@redhat.com>
8 *
9 * This file is provided under a dual BSD/GPLv2 license. When using or
10 * redistributing this file, you may do so under either license.
11 *
12 * GPL LICENSE SUMMARY
13 *
14 * Copyright(c) 2013 OpenVPN Technologies, Inc. All rights reserved.
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of version 2 of the GNU General Public License as
18 * published by the Free Software Foundation.
19 *
20 * This program is distributed in the hope that it will be useful, but
21 * WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
23 * General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
28 * The full GNU General Public License is included in this distribution
29 * in the file called LICENSE.GPL.
30 *
31 * BSD LICENSE
32 *
33 * Copyright(c) 2013 OpenVPN Technologies, Inc. All rights reserved.
34 *
35 * Redistribution and use in source and binary forms, with or without
36 * modification, are permitted provided that the following conditions
37 * are met:
38 *
39 * * Redistributions of source code must retain the above copyright
40 * notice, this list of conditions and the following disclaimer.
41 * * Redistributions in binary form must reproduce the above copyright
42 * notice, this list of conditions and the following disclaimer in
43 * the documentation and/or other materials provided with the
44 * distribution.
45 * * Neither the name of OpenVPN Technologies nor the names of its
46 * contributors may be used to endorse or promote products derived
47 * from this software without specific prior written permission.
48 *
49 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
50 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
51 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
52 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
53 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
54 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
55 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
56 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
57 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
58 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
59 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
60 */
61
62#include <crypto/algapi.h>
63
64#ifndef __HAVE_ARCH_CRYPTO_MEMNEQ
65
66/* Generic path for arbitrary size */
67static inline unsigned long
68__crypto_memneq_generic(const void *a, const void *b, size_t size)
69{
70 unsigned long neq = 0;
71
72#if defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
73 while (size >= sizeof(unsigned long)) {
74 neq |= *(unsigned long *)a ^ *(unsigned long *)b;
75 a += sizeof(unsigned long);
76 b += sizeof(unsigned long);
77 size -= sizeof(unsigned long);
78 }
79#endif /* CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS */
80 while (size > 0) {
81 neq |= *(unsigned char *)a ^ *(unsigned char *)b;
82 a += 1;
83 b += 1;
84 size -= 1;
85 }
86 return neq;
87}
88
89/* Loop-free fast-path for frequently used 16-byte size */
90static inline unsigned long __crypto_memneq_16(const void *a, const void *b)
91{
92#ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
93 if (sizeof(unsigned long) == 8)
94 return ((*(unsigned long *)(a) ^ *(unsigned long *)(b))
95 | (*(unsigned long *)(a+8) ^ *(unsigned long *)(b+8)));
96 else if (sizeof(unsigned int) == 4)
97 return ((*(unsigned int *)(a) ^ *(unsigned int *)(b))
98 | (*(unsigned int *)(a+4) ^ *(unsigned int *)(b+4))
99 | (*(unsigned int *)(a+8) ^ *(unsigned int *)(b+8))
100 | (*(unsigned int *)(a+12) ^ *(unsigned int *)(b+12)));
101 else
102#endif /* CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS */
103 return ((*(unsigned char *)(a) ^ *(unsigned char *)(b))
104 | (*(unsigned char *)(a+1) ^ *(unsigned char *)(b+1))
105 | (*(unsigned char *)(a+2) ^ *(unsigned char *)(b+2))
106 | (*(unsigned char *)(a+3) ^ *(unsigned char *)(b+3))
107 | (*(unsigned char *)(a+4) ^ *(unsigned char *)(b+4))
108 | (*(unsigned char *)(a+5) ^ *(unsigned char *)(b+5))
109 | (*(unsigned char *)(a+6) ^ *(unsigned char *)(b+6))
110 | (*(unsigned char *)(a+7) ^ *(unsigned char *)(b+7))
111 | (*(unsigned char *)(a+8) ^ *(unsigned char *)(b+8))
112 | (*(unsigned char *)(a+9) ^ *(unsigned char *)(b+9))
113 | (*(unsigned char *)(a+10) ^ *(unsigned char *)(b+10))
114 | (*(unsigned char *)(a+11) ^ *(unsigned char *)(b+11))
115 | (*(unsigned char *)(a+12) ^ *(unsigned char *)(b+12))
116 | (*(unsigned char *)(a+13) ^ *(unsigned char *)(b+13))
117 | (*(unsigned char *)(a+14) ^ *(unsigned char *)(b+14))
118 | (*(unsigned char *)(a+15) ^ *(unsigned char *)(b+15)));
119}
120
121/* Compare two areas of memory without leaking timing information,
122 * and with special optimizations for common sizes. Users should
123 * not call this function directly, but should instead use
124 * crypto_memneq defined in crypto/algapi.h.
125 */
126noinline unsigned long __crypto_memneq(const void *a, const void *b,
127 size_t size)
128{
129 switch (size) {
130 case 16:
131 return __crypto_memneq_16(a, b);
132 default:
133 return __crypto_memneq_generic(a, b, size);
134 }
135}
136EXPORT_SYMBOL(__crypto_memneq);
137
138#endif /* __HAVE_ARCH_CRYPTO_MEMNEQ */
diff --git a/crypto/tcrypt.c b/crypto/tcrypt.c
index 1ab8258fcf56..001f07cdb828 100644
--- a/crypto/tcrypt.c
+++ b/crypto/tcrypt.c
@@ -1242,6 +1242,10 @@ static int do_test(int m)
1242 ret += tcrypt_test("cmac(des3_ede)"); 1242 ret += tcrypt_test("cmac(des3_ede)");
1243 break; 1243 break;
1244 1244
1245 case 155:
1246 ret += tcrypt_test("authenc(hmac(sha1),cbc(aes))");
1247 break;
1248
1245 case 200: 1249 case 200:
1246 test_cipher_speed("ecb(aes)", ENCRYPT, sec, NULL, 0, 1250 test_cipher_speed("ecb(aes)", ENCRYPT, sec, NULL, 0,
1247 speed_template_16_24_32); 1251 speed_template_16_24_32);
diff --git a/crypto/testmgr.c b/crypto/testmgr.c
index 432afc03e7c3..77955507f6f1 100644
--- a/crypto/testmgr.c
+++ b/crypto/testmgr.c
@@ -503,16 +503,16 @@ static int __test_aead(struct crypto_aead *tfm, int enc,
503 goto out; 503 goto out;
504 } 504 }
505 505
506 sg_init_one(&sg[0], input,
507 template[i].ilen + (enc ? authsize : 0));
508
509 if (diff_dst) { 506 if (diff_dst) {
510 output = xoutbuf[0]; 507 output = xoutbuf[0];
511 output += align_offset; 508 output += align_offset;
509 sg_init_one(&sg[0], input, template[i].ilen);
512 sg_init_one(&sgout[0], output, 510 sg_init_one(&sgout[0], output,
511 template[i].rlen);
512 } else {
513 sg_init_one(&sg[0], input,
513 template[i].ilen + 514 template[i].ilen +
514 (enc ? authsize : 0)); 515 (enc ? authsize : 0));
515 } else {
516 output = input; 516 output = input;
517 } 517 }
518 518
@@ -612,12 +612,6 @@ static int __test_aead(struct crypto_aead *tfm, int enc,
612 memcpy(q, template[i].input + temp, 612 memcpy(q, template[i].input + temp,
613 template[i].tap[k]); 613 template[i].tap[k]);
614 614
615 n = template[i].tap[k];
616 if (k == template[i].np - 1 && enc)
617 n += authsize;
618 if (offset_in_page(q) + n < PAGE_SIZE)
619 q[n] = 0;
620
621 sg_set_buf(&sg[k], q, template[i].tap[k]); 615 sg_set_buf(&sg[k], q, template[i].tap[k]);
622 616
623 if (diff_dst) { 617 if (diff_dst) {
@@ -625,13 +619,17 @@ static int __test_aead(struct crypto_aead *tfm, int enc,
625 offset_in_page(IDX[k]); 619 offset_in_page(IDX[k]);
626 620
627 memset(q, 0, template[i].tap[k]); 621 memset(q, 0, template[i].tap[k]);
628 if (offset_in_page(q) + n < PAGE_SIZE)
629 q[n] = 0;
630 622
631 sg_set_buf(&sgout[k], q, 623 sg_set_buf(&sgout[k], q,
632 template[i].tap[k]); 624 template[i].tap[k]);
633 } 625 }
634 626
627 n = template[i].tap[k];
628 if (k == template[i].np - 1 && enc)
629 n += authsize;
630 if (offset_in_page(q) + n < PAGE_SIZE)
631 q[n] = 0;
632
635 temp += template[i].tap[k]; 633 temp += template[i].tap[k];
636 } 634 }
637 635
@@ -650,10 +648,10 @@ static int __test_aead(struct crypto_aead *tfm, int enc,
650 goto out; 648 goto out;
651 } 649 }
652 650
653 sg[k - 1].length += authsize;
654
655 if (diff_dst) 651 if (diff_dst)
656 sgout[k - 1].length += authsize; 652 sgout[k - 1].length += authsize;
653 else
654 sg[k - 1].length += authsize;
657 } 655 }
658 656
659 sg_init_table(asg, template[i].anp); 657 sg_init_table(asg, template[i].anp);
diff --git a/drivers/Makefile b/drivers/Makefile
index 3cc8214f9b26..8e3b8b06c0b2 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -118,7 +118,7 @@ obj-$(CONFIG_SGI_SN) += sn/
118obj-y += firmware/ 118obj-y += firmware/
119obj-$(CONFIG_CRYPTO) += crypto/ 119obj-$(CONFIG_CRYPTO) += crypto/
120obj-$(CONFIG_SUPERH) += sh/ 120obj-$(CONFIG_SUPERH) += sh/
121obj-$(CONFIG_ARCH_SHMOBILE) += sh/ 121obj-$(CONFIG_ARCH_SHMOBILE_LEGACY) += sh/
122ifndef CONFIG_ARCH_USES_GETTIMEOFFSET 122ifndef CONFIG_ARCH_USES_GETTIMEOFFSET
123obj-y += clocksource/ 123obj-y += clocksource/
124endif 124endif
diff --git a/drivers/acpi/acpica/acresrc.h b/drivers/acpi/acpica/acresrc.h
index f691d0e4d9fa..ff97430455cb 100644
--- a/drivers/acpi/acpica/acresrc.h
+++ b/drivers/acpi/acpica/acresrc.h
@@ -184,7 +184,7 @@ acpi_rs_create_resource_list(union acpi_operand_object *aml_buffer,
184 struct acpi_buffer *output_buffer); 184 struct acpi_buffer *output_buffer);
185 185
186acpi_status 186acpi_status
187acpi_rs_create_aml_resources(struct acpi_resource *linked_list_buffer, 187acpi_rs_create_aml_resources(struct acpi_buffer *resource_list,
188 struct acpi_buffer *output_buffer); 188 struct acpi_buffer *output_buffer);
189 189
190acpi_status 190acpi_status
@@ -227,8 +227,8 @@ acpi_rs_get_list_length(u8 * aml_buffer,
227 u32 aml_buffer_length, acpi_size * size_needed); 227 u32 aml_buffer_length, acpi_size * size_needed);
228 228
229acpi_status 229acpi_status
230acpi_rs_get_aml_length(struct acpi_resource *linked_list_buffer, 230acpi_rs_get_aml_length(struct acpi_resource *resource_list,
231 acpi_size * size_needed); 231 acpi_size resource_list_size, acpi_size * size_needed);
232 232
233acpi_status 233acpi_status
234acpi_rs_get_pci_routing_table_length(union acpi_operand_object *package_object, 234acpi_rs_get_pci_routing_table_length(union acpi_operand_object *package_object,
diff --git a/drivers/acpi/acpica/nsalloc.c b/drivers/acpi/acpica/nsalloc.c
index 243737363fb8..fd1ff54cda19 100644
--- a/drivers/acpi/acpica/nsalloc.c
+++ b/drivers/acpi/acpica/nsalloc.c
@@ -106,6 +106,7 @@ struct acpi_namespace_node *acpi_ns_create_node(u32 name)
106void acpi_ns_delete_node(struct acpi_namespace_node *node) 106void acpi_ns_delete_node(struct acpi_namespace_node *node)
107{ 107{
108 union acpi_operand_object *obj_desc; 108 union acpi_operand_object *obj_desc;
109 union acpi_operand_object *next_desc;
109 110
110 ACPI_FUNCTION_NAME(ns_delete_node); 111 ACPI_FUNCTION_NAME(ns_delete_node);
111 112
@@ -114,12 +115,13 @@ void acpi_ns_delete_node(struct acpi_namespace_node *node)
114 acpi_ns_detach_object(node); 115 acpi_ns_detach_object(node);
115 116
116 /* 117 /*
117 * Delete an attached data object if present (an object that was created 118 * Delete an attached data object list if present (objects that were
118 * and attached via acpi_attach_data). Note: After any normal object is 119 * attached via acpi_attach_data). Note: After any normal object is
119 * detached above, the only possible remaining object is a data object. 120 * detached above, the only possible remaining object(s) are data
121 * objects, in a linked list.
120 */ 122 */
121 obj_desc = node->object; 123 obj_desc = node->object;
122 if (obj_desc && (obj_desc->common.type == ACPI_TYPE_LOCAL_DATA)) { 124 while (obj_desc && (obj_desc->common.type == ACPI_TYPE_LOCAL_DATA)) {
123 125
124 /* Invoke the attached data deletion handler if present */ 126 /* Invoke the attached data deletion handler if present */
125 127
@@ -127,7 +129,15 @@ void acpi_ns_delete_node(struct acpi_namespace_node *node)
127 obj_desc->data.handler(node, obj_desc->data.pointer); 129 obj_desc->data.handler(node, obj_desc->data.pointer);
128 } 130 }
129 131
132 next_desc = obj_desc->common.next_object;
130 acpi_ut_remove_reference(obj_desc); 133 acpi_ut_remove_reference(obj_desc);
134 obj_desc = next_desc;
135 }
136
137 /* Special case for the statically allocated root node */
138
139 if (node == acpi_gbl_root_node) {
140 return;
131 } 141 }
132 142
133 /* Now we can delete the node */ 143 /* Now we can delete the node */
diff --git a/drivers/acpi/acpica/nsutils.c b/drivers/acpi/acpica/nsutils.c
index cc2fea94c5f0..4a0665b6bcc1 100644
--- a/drivers/acpi/acpica/nsutils.c
+++ b/drivers/acpi/acpica/nsutils.c
@@ -593,24 +593,26 @@ struct acpi_namespace_node *acpi_ns_validate_handle(acpi_handle handle)
593 593
594void acpi_ns_terminate(void) 594void acpi_ns_terminate(void)
595{ 595{
596 union acpi_operand_object *obj_desc; 596 acpi_status status;
597 597
598 ACPI_FUNCTION_TRACE(ns_terminate); 598 ACPI_FUNCTION_TRACE(ns_terminate);
599 599
600 /* 600 /*
601 * 1) Free the entire namespace -- all nodes and objects 601 * Free the entire namespace -- all nodes and all objects
602 * 602 * attached to the nodes
603 * Delete all object descriptors attached to namepsace nodes
604 */ 603 */
605 acpi_ns_delete_namespace_subtree(acpi_gbl_root_node); 604 acpi_ns_delete_namespace_subtree(acpi_gbl_root_node);
606 605
607 /* Detach any objects attached to the root */ 606 /* Delete any objects attached to the root node */
608 607
609 obj_desc = acpi_ns_get_attached_object(acpi_gbl_root_node); 608 status = acpi_ut_acquire_mutex(ACPI_MTX_NAMESPACE);
610 if (obj_desc) { 609 if (ACPI_FAILURE(status)) {
611 acpi_ns_detach_object(acpi_gbl_root_node); 610 return_VOID;
612 } 611 }
613 612
613 acpi_ns_delete_node(acpi_gbl_root_node);
614 (void)acpi_ut_release_mutex(ACPI_MTX_NAMESPACE);
615
614 ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Namespace freed\n")); 616 ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Namespace freed\n"));
615 return_VOID; 617 return_VOID;
616} 618}
diff --git a/drivers/acpi/acpica/rscalc.c b/drivers/acpi/acpica/rscalc.c
index b62a0f4f4f9b..b60c9cf82862 100644
--- a/drivers/acpi/acpica/rscalc.c
+++ b/drivers/acpi/acpica/rscalc.c
@@ -174,6 +174,7 @@ acpi_rs_stream_option_length(u32 resource_length,
174 * FUNCTION: acpi_rs_get_aml_length 174 * FUNCTION: acpi_rs_get_aml_length
175 * 175 *
176 * PARAMETERS: resource - Pointer to the resource linked list 176 * PARAMETERS: resource - Pointer to the resource linked list
177 * resource_list_size - Size of the resource linked list
177 * size_needed - Where the required size is returned 178 * size_needed - Where the required size is returned
178 * 179 *
179 * RETURN: Status 180 * RETURN: Status
@@ -185,16 +186,20 @@ acpi_rs_stream_option_length(u32 resource_length,
185 ******************************************************************************/ 186 ******************************************************************************/
186 187
187acpi_status 188acpi_status
188acpi_rs_get_aml_length(struct acpi_resource * resource, acpi_size * size_needed) 189acpi_rs_get_aml_length(struct acpi_resource *resource,
190 acpi_size resource_list_size, acpi_size * size_needed)
189{ 191{
190 acpi_size aml_size_needed = 0; 192 acpi_size aml_size_needed = 0;
193 struct acpi_resource *resource_end;
191 acpi_rs_length total_size; 194 acpi_rs_length total_size;
192 195
193 ACPI_FUNCTION_TRACE(rs_get_aml_length); 196 ACPI_FUNCTION_TRACE(rs_get_aml_length);
194 197
195 /* Traverse entire list of internal resource descriptors */ 198 /* Traverse entire list of internal resource descriptors */
196 199
197 while (resource) { 200 resource_end =
201 ACPI_ADD_PTR(struct acpi_resource, resource, resource_list_size);
202 while (resource < resource_end) {
198 203
199 /* Validate the descriptor type */ 204 /* Validate the descriptor type */
200 205
diff --git a/drivers/acpi/acpica/rscreate.c b/drivers/acpi/acpica/rscreate.c
index 65f3e1c5b598..3a2ace93e62c 100644
--- a/drivers/acpi/acpica/rscreate.c
+++ b/drivers/acpi/acpica/rscreate.c
@@ -418,22 +418,21 @@ acpi_rs_create_pci_routing_table(union acpi_operand_object *package_object,
418 * 418 *
419 * FUNCTION: acpi_rs_create_aml_resources 419 * FUNCTION: acpi_rs_create_aml_resources
420 * 420 *
421 * PARAMETERS: linked_list_buffer - Pointer to the resource linked list 421 * PARAMETERS: resource_list - Pointer to the resource list buffer
422 * output_buffer - Pointer to the user's buffer 422 * output_buffer - Where the AML buffer is returned
423 * 423 *
424 * RETURN: Status AE_OK if okay, else a valid acpi_status code. 424 * RETURN: Status AE_OK if okay, else a valid acpi_status code.
425 * If the output_buffer is too small, the error will be 425 * If the output_buffer is too small, the error will be
426 * AE_BUFFER_OVERFLOW and output_buffer->Length will point 426 * AE_BUFFER_OVERFLOW and output_buffer->Length will point
427 * to the size buffer needed. 427 * to the size buffer needed.
428 * 428 *
429 * DESCRIPTION: Takes the linked list of device resources and 429 * DESCRIPTION: Converts a list of device resources to an AML bytestream
430 * creates a bytestream to be used as input for the 430 * to be used as input for the _SRS control method.
431 * _SRS control method.
432 * 431 *
433 ******************************************************************************/ 432 ******************************************************************************/
434 433
435acpi_status 434acpi_status
436acpi_rs_create_aml_resources(struct acpi_resource *linked_list_buffer, 435acpi_rs_create_aml_resources(struct acpi_buffer *resource_list,
437 struct acpi_buffer *output_buffer) 436 struct acpi_buffer *output_buffer)
438{ 437{
439 acpi_status status; 438 acpi_status status;
@@ -441,16 +440,16 @@ acpi_rs_create_aml_resources(struct acpi_resource *linked_list_buffer,
441 440
442 ACPI_FUNCTION_TRACE(rs_create_aml_resources); 441 ACPI_FUNCTION_TRACE(rs_create_aml_resources);
443 442
444 ACPI_DEBUG_PRINT((ACPI_DB_INFO, "LinkedListBuffer = %p\n", 443 /* Params already validated, no need to re-validate here */
445 linked_list_buffer));
446 444
447 /* 445 ACPI_DEBUG_PRINT((ACPI_DB_INFO, "ResourceList Buffer = %p\n",
448 * Params already validated, so we don't re-validate here 446 resource_list->pointer));
449 * 447
450 * Pass the linked_list_buffer into a module that calculates 448 /* Get the buffer size needed for the AML byte stream */
451 * the buffer size needed for the byte stream. 449
452 */ 450 status = acpi_rs_get_aml_length(resource_list->pointer,
453 status = acpi_rs_get_aml_length(linked_list_buffer, &aml_size_needed); 451 resource_list->length,
452 &aml_size_needed);
454 453
455 ACPI_DEBUG_PRINT((ACPI_DB_INFO, "AmlSizeNeeded=%X, %s\n", 454 ACPI_DEBUG_PRINT((ACPI_DB_INFO, "AmlSizeNeeded=%X, %s\n",
456 (u32)aml_size_needed, acpi_format_exception(status))); 455 (u32)aml_size_needed, acpi_format_exception(status)));
@@ -467,10 +466,9 @@ acpi_rs_create_aml_resources(struct acpi_resource *linked_list_buffer,
467 466
468 /* Do the conversion */ 467 /* Do the conversion */
469 468
470 status = 469 status = acpi_rs_convert_resources_to_aml(resource_list->pointer,
471 acpi_rs_convert_resources_to_aml(linked_list_buffer, 470 aml_size_needed,
472 aml_size_needed, 471 output_buffer->pointer);
473 output_buffer->pointer);
474 if (ACPI_FAILURE(status)) { 472 if (ACPI_FAILURE(status)) {
475 return_ACPI_STATUS(status); 473 return_ACPI_STATUS(status);
476 } 474 }
diff --git a/drivers/acpi/acpica/rsutils.c b/drivers/acpi/acpica/rsutils.c
index aef303d56d86..14a7982c9961 100644
--- a/drivers/acpi/acpica/rsutils.c
+++ b/drivers/acpi/acpica/rsutils.c
@@ -753,7 +753,7 @@ acpi_rs_set_srs_method_data(struct acpi_namespace_node *node,
753 * Convert the linked list into a byte stream 753 * Convert the linked list into a byte stream
754 */ 754 */
755 buffer.length = ACPI_ALLOCATE_LOCAL_BUFFER; 755 buffer.length = ACPI_ALLOCATE_LOCAL_BUFFER;
756 status = acpi_rs_create_aml_resources(in_buffer->pointer, &buffer); 756 status = acpi_rs_create_aml_resources(in_buffer, &buffer);
757 if (ACPI_FAILURE(status)) { 757 if (ACPI_FAILURE(status)) {
758 goto cleanup; 758 goto cleanup;
759 } 759 }
diff --git a/drivers/acpi/acpica/utdebug.c b/drivers/acpi/acpica/utdebug.c
index 1a67b3944b3b..03ae8affe48f 100644
--- a/drivers/acpi/acpica/utdebug.c
+++ b/drivers/acpi/acpica/utdebug.c
@@ -185,6 +185,7 @@ acpi_debug_print(u32 requested_debug_level,
185 } 185 }
186 186
187 acpi_gbl_prev_thread_id = thread_id; 187 acpi_gbl_prev_thread_id = thread_id;
188 acpi_gbl_nesting_level = 0;
188 } 189 }
189 190
190 /* 191 /*
@@ -193,13 +194,21 @@ acpi_debug_print(u32 requested_debug_level,
193 */ 194 */
194 acpi_os_printf("%9s-%04ld ", module_name, line_number); 195 acpi_os_printf("%9s-%04ld ", module_name, line_number);
195 196
197#ifdef ACPI_EXEC_APP
198 /*
199 * For acpi_exec only, emit the thread ID and nesting level.
200 * Note: nesting level is really only useful during a single-thread
201 * execution. Otherwise, multiple threads will keep resetting the
202 * level.
203 */
196 if (ACPI_LV_THREADS & acpi_dbg_level) { 204 if (ACPI_LV_THREADS & acpi_dbg_level) {
197 acpi_os_printf("[%u] ", (u32)thread_id); 205 acpi_os_printf("[%u] ", (u32)thread_id);
198 } 206 }
199 207
200 acpi_os_printf("[%02ld] %-22.22s: ", 208 acpi_os_printf("[%02ld] ", acpi_gbl_nesting_level);
201 acpi_gbl_nesting_level, 209#endif
202 acpi_ut_trim_function_name(function_name)); 210
211 acpi_os_printf("%-22.22s: ", acpi_ut_trim_function_name(function_name));
203 212
204 va_start(args, format); 213 va_start(args, format);
205 acpi_os_vprintf(format, args); 214 acpi_os_vprintf(format, args);
@@ -420,7 +429,9 @@ acpi_ut_exit(u32 line_number,
420 component_id, "%s\n", acpi_gbl_fn_exit_str); 429 component_id, "%s\n", acpi_gbl_fn_exit_str);
421 } 430 }
422 431
423 acpi_gbl_nesting_level--; 432 if (acpi_gbl_nesting_level) {
433 acpi_gbl_nesting_level--;
434 }
424} 435}
425 436
426ACPI_EXPORT_SYMBOL(acpi_ut_exit) 437ACPI_EXPORT_SYMBOL(acpi_ut_exit)
@@ -467,7 +478,9 @@ acpi_ut_status_exit(u32 line_number,
467 } 478 }
468 } 479 }
469 480
470 acpi_gbl_nesting_level--; 481 if (acpi_gbl_nesting_level) {
482 acpi_gbl_nesting_level--;
483 }
471} 484}
472 485
473ACPI_EXPORT_SYMBOL(acpi_ut_status_exit) 486ACPI_EXPORT_SYMBOL(acpi_ut_status_exit)
@@ -504,7 +517,9 @@ acpi_ut_value_exit(u32 line_number,
504 ACPI_FORMAT_UINT64(value)); 517 ACPI_FORMAT_UINT64(value));
505 } 518 }
506 519
507 acpi_gbl_nesting_level--; 520 if (acpi_gbl_nesting_level) {
521 acpi_gbl_nesting_level--;
522 }
508} 523}
509 524
510ACPI_EXPORT_SYMBOL(acpi_ut_value_exit) 525ACPI_EXPORT_SYMBOL(acpi_ut_value_exit)
@@ -540,7 +555,9 @@ acpi_ut_ptr_exit(u32 line_number,
540 ptr); 555 ptr);
541 } 556 }
542 557
543 acpi_gbl_nesting_level--; 558 if (acpi_gbl_nesting_level) {
559 acpi_gbl_nesting_level--;
560 }
544} 561}
545 562
546#endif 563#endif
diff --git a/drivers/acpi/nvs.c b/drivers/acpi/nvs.c
index 266bc58ce0ce..386a9fe497b4 100644
--- a/drivers/acpi/nvs.c
+++ b/drivers/acpi/nvs.c
@@ -13,7 +13,6 @@
13#include <linux/slab.h> 13#include <linux/slab.h>
14#include <linux/acpi.h> 14#include <linux/acpi.h>
15#include <linux/acpi_io.h> 15#include <linux/acpi_io.h>
16#include <acpi/acpiosxf.h>
17 16
18/* ACPI NVS regions, APEI may use it */ 17/* ACPI NVS regions, APEI may use it */
19 18
diff --git a/drivers/acpi/pci_root.c b/drivers/acpi/pci_root.c
index 0703bff5e60e..20360e480bd8 100644
--- a/drivers/acpi/pci_root.c
+++ b/drivers/acpi/pci_root.c
@@ -65,6 +65,9 @@ static struct acpi_scan_handler pci_root_handler = {
65 .ids = root_device_ids, 65 .ids = root_device_ids,
66 .attach = acpi_pci_root_add, 66 .attach = acpi_pci_root_add,
67 .detach = acpi_pci_root_remove, 67 .detach = acpi_pci_root_remove,
68 .hotplug = {
69 .ignore = true,
70 },
68}; 71};
69 72
70static DEFINE_MUTEX(osc_lock); 73static DEFINE_MUTEX(osc_lock);
diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c
index 15daa21fcd05..fd39459926b1 100644
--- a/drivers/acpi/scan.c
+++ b/drivers/acpi/scan.c
@@ -1772,7 +1772,7 @@ static void acpi_scan_init_hotplug(acpi_handle handle, int type)
1772 */ 1772 */
1773 list_for_each_entry(hwid, &pnp.ids, list) { 1773 list_for_each_entry(hwid, &pnp.ids, list) {
1774 handler = acpi_scan_match_handler(hwid->id, NULL); 1774 handler = acpi_scan_match_handler(hwid->id, NULL);
1775 if (handler) { 1775 if (handler && !handler->hotplug.ignore) {
1776 acpi_install_notify_handler(handle, ACPI_SYSTEM_NOTIFY, 1776 acpi_install_notify_handler(handle, ACPI_SYSTEM_NOTIFY,
1777 acpi_hotplug_notify_cb, handler); 1777 acpi_hotplug_notify_cb, handler);
1778 break; 1778 break;
diff --git a/drivers/acpi/sleep.c b/drivers/acpi/sleep.c
index 14df30580e15..721e949e606e 100644
--- a/drivers/acpi/sleep.c
+++ b/drivers/acpi/sleep.c
@@ -525,7 +525,7 @@ static int acpi_suspend_enter(suspend_state_t pm_state)
525 * generate wakeup events. 525 * generate wakeup events.
526 */ 526 */
527 if (ACPI_SUCCESS(status) && (acpi_state == ACPI_STATE_S3)) { 527 if (ACPI_SUCCESS(status) && (acpi_state == ACPI_STATE_S3)) {
528 acpi_event_status pwr_btn_status; 528 acpi_event_status pwr_btn_status = ACPI_EVENT_FLAG_DISABLED;
529 529
530 acpi_get_event_status(ACPI_EVENT_POWER_BUTTON, &pwr_btn_status); 530 acpi_get_event_status(ACPI_EVENT_POWER_BUTTON, &pwr_btn_status);
531 531
diff --git a/drivers/acpi/sysfs.c b/drivers/acpi/sysfs.c
index db5293650f62..6dbc3ca45223 100644
--- a/drivers/acpi/sysfs.c
+++ b/drivers/acpi/sysfs.c
@@ -309,7 +309,7 @@ static void acpi_table_attr_init(struct acpi_table_attr *table_attr,
309 sprintf(table_attr->name + ACPI_NAME_SIZE, "%d", 309 sprintf(table_attr->name + ACPI_NAME_SIZE, "%d",
310 table_attr->instance); 310 table_attr->instance);
311 311
312 table_attr->attr.size = 0; 312 table_attr->attr.size = table_header->length;
313 table_attr->attr.read = acpi_table_show; 313 table_attr->attr.read = acpi_table_show;
314 table_attr->attr.attr.name = table_attr->name; 314 table_attr->attr.attr.name = table_attr->name;
315 table_attr->attr.attr.mode = 0400; 315 table_attr->attr.attr.mode = 0400;
@@ -354,8 +354,9 @@ static int acpi_tables_sysfs_init(void)
354{ 354{
355 struct acpi_table_attr *table_attr; 355 struct acpi_table_attr *table_attr;
356 struct acpi_table_header *table_header = NULL; 356 struct acpi_table_header *table_header = NULL;
357 int table_index = 0; 357 int table_index;
358 int result; 358 acpi_status status;
359 int ret;
359 360
360 tables_kobj = kobject_create_and_add("tables", acpi_kobj); 361 tables_kobj = kobject_create_and_add("tables", acpi_kobj);
361 if (!tables_kobj) 362 if (!tables_kobj)
@@ -365,33 +366,34 @@ static int acpi_tables_sysfs_init(void)
365 if (!dynamic_tables_kobj) 366 if (!dynamic_tables_kobj)
366 goto err_dynamic_tables; 367 goto err_dynamic_tables;
367 368
368 do { 369 for (table_index = 0;; table_index++) {
369 result = acpi_get_table_by_index(table_index, &table_header); 370 status = acpi_get_table_by_index(table_index, &table_header);
370 if (!result) { 371
371 table_index++; 372 if (status == AE_BAD_PARAMETER)
372 table_attr = NULL; 373 break;
373 table_attr = 374
374 kzalloc(sizeof(struct acpi_table_attr), GFP_KERNEL); 375 if (ACPI_FAILURE(status))
375 if (!table_attr) 376 continue;
376 return -ENOMEM; 377
377 378 table_attr = NULL;
378 acpi_table_attr_init(table_attr, table_header); 379 table_attr = kzalloc(sizeof(*table_attr), GFP_KERNEL);
379 result = 380 if (!table_attr)
380 sysfs_create_bin_file(tables_kobj, 381 return -ENOMEM;
381 &table_attr->attr); 382
382 if (result) { 383 acpi_table_attr_init(table_attr, table_header);
383 kfree(table_attr); 384 ret = sysfs_create_bin_file(tables_kobj, &table_attr->attr);
384 return result; 385 if (ret) {
385 } else 386 kfree(table_attr);
386 list_add_tail(&table_attr->node, 387 return ret;
387 &acpi_table_attr_list);
388 } 388 }
389 } while (!result); 389 list_add_tail(&table_attr->node, &acpi_table_attr_list);
390 }
391
390 kobject_uevent(tables_kobj, KOBJ_ADD); 392 kobject_uevent(tables_kobj, KOBJ_ADD);
391 kobject_uevent(dynamic_tables_kobj, KOBJ_ADD); 393 kobject_uevent(dynamic_tables_kobj, KOBJ_ADD);
392 result = acpi_install_table_handler(acpi_sysfs_table_handler, NULL); 394 status = acpi_install_table_handler(acpi_sysfs_table_handler, NULL);
393 395
394 return result == AE_OK ? 0 : -EINVAL; 396 return ACPI_FAILURE(status) ? -EINVAL : 0;
395err_dynamic_tables: 397err_dynamic_tables:
396 kobject_put(tables_kobj); 398 kobject_put(tables_kobj);
397err: 399err:
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index e2903d03180e..14f1e9506338 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -435,6 +435,8 @@ static const struct pci_device_id ahci_pci_tbl[] = {
435 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */ 435 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
436 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3), 436 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
437 .driver_data = board_ahci_yes_fbs }, 437 .driver_data = board_ahci_yes_fbs },
438 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
439 .driver_data = board_ahci_yes_fbs },
438 440
439 /* Promise */ 441 /* Promise */
440 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */ 442 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
diff --git a/drivers/ata/ahci_platform.c b/drivers/ata/ahci_platform.c
index f9554318504f..4b231baceb09 100644
--- a/drivers/ata/ahci_platform.c
+++ b/drivers/ata/ahci_platform.c
@@ -329,6 +329,7 @@ static SIMPLE_DEV_PM_OPS(ahci_pm_ops, ahci_suspend, ahci_resume);
329static const struct of_device_id ahci_of_match[] = { 329static const struct of_device_id ahci_of_match[] = {
330 { .compatible = "snps,spear-ahci", }, 330 { .compatible = "snps,spear-ahci", },
331 { .compatible = "snps,exynos5440-ahci", }, 331 { .compatible = "snps,exynos5440-ahci", },
332 { .compatible = "ibm,476gtr-ahci", },
332 {}, 333 {},
333}; 334};
334MODULE_DEVICE_TABLE(of, ahci_of_match); 335MODULE_DEVICE_TABLE(of, ahci_of_match);
diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c
index 81a94a3919db..75b93678bbcd 100644
--- a/drivers/ata/libata-core.c
+++ b/drivers/ata/libata-core.c
@@ -6304,10 +6304,9 @@ static void ata_port_detach(struct ata_port *ap)
6304 for (i = 0; i < SATA_PMP_MAX_PORTS; i++) 6304 for (i = 0; i < SATA_PMP_MAX_PORTS; i++)
6305 ata_tlink_delete(&ap->pmp_link[i]); 6305 ata_tlink_delete(&ap->pmp_link[i]);
6306 } 6306 }
6307 ata_tport_delete(ap);
6308
6309 /* remove the associated SCSI host */ 6307 /* remove the associated SCSI host */
6310 scsi_remove_host(ap->scsi_host); 6308 scsi_remove_host(ap->scsi_host);
6309 ata_tport_delete(ap);
6311} 6310}
6312 6311
6313/** 6312/**
diff --git a/drivers/ata/libata-scsi.c b/drivers/ata/libata-scsi.c
index db6dfcfa3e2e..ab58556d347c 100644
--- a/drivers/ata/libata-scsi.c
+++ b/drivers/ata/libata-scsi.c
@@ -3625,6 +3625,7 @@ int ata_scsi_add_hosts(struct ata_host *host, struct scsi_host_template *sht)
3625 shost->max_lun = 1; 3625 shost->max_lun = 1;
3626 shost->max_channel = 1; 3626 shost->max_channel = 1;
3627 shost->max_cmd_len = 16; 3627 shost->max_cmd_len = 16;
3628 shost->no_write_same = 1;
3628 3629
3629 /* Schedule policy is determined by ->qc_defer() 3630 /* Schedule policy is determined by ->qc_defer()
3630 * callback and it needs to see every deferred qc. 3631 * callback and it needs to see every deferred qc.
diff --git a/drivers/ata/libata-zpodd.c b/drivers/ata/libata-zpodd.c
index 68f9e3293e9c..88949c6d55dd 100644
--- a/drivers/ata/libata-zpodd.c
+++ b/drivers/ata/libata-zpodd.c
@@ -88,15 +88,13 @@ static enum odd_mech_type zpodd_get_mech_type(struct ata_device *dev)
88static bool odd_can_poweroff(struct ata_device *ata_dev) 88static bool odd_can_poweroff(struct ata_device *ata_dev)
89{ 89{
90 acpi_handle handle; 90 acpi_handle handle;
91 acpi_status status;
92 struct acpi_device *acpi_dev; 91 struct acpi_device *acpi_dev;
93 92
94 handle = ata_dev_acpi_handle(ata_dev); 93 handle = ata_dev_acpi_handle(ata_dev);
95 if (!handle) 94 if (!handle)
96 return false; 95 return false;
97 96
98 status = acpi_bus_get_device(handle, &acpi_dev); 97 if (acpi_bus_get_device(handle, &acpi_dev))
99 if (ACPI_FAILURE(status))
100 return false; 98 return false;
101 99
102 return acpi_device_can_poweroff(acpi_dev); 100 return acpi_device_can_poweroff(acpi_dev);
diff --git a/drivers/ata/pata_arasan_cf.c b/drivers/ata/pata_arasan_cf.c
index e88690ebfd82..73492dd4a4bc 100644
--- a/drivers/ata/pata_arasan_cf.c
+++ b/drivers/ata/pata_arasan_cf.c
@@ -319,6 +319,7 @@ static int cf_init(struct arasan_cf_dev *acdev)
319 ret = clk_set_rate(acdev->clk, 166000000); 319 ret = clk_set_rate(acdev->clk, 166000000);
320 if (ret) { 320 if (ret) {
321 dev_warn(acdev->host->dev, "clock set rate failed"); 321 dev_warn(acdev->host->dev, "clock set rate failed");
322 clk_disable_unprepare(acdev->clk);
322 return ret; 323 return ret;
323 } 324 }
324 325
diff --git a/drivers/base/power/main.c b/drivers/base/power/main.c
index 1b41fca3d65a..e3219dfd736c 100644
--- a/drivers/base/power/main.c
+++ b/drivers/base/power/main.c
@@ -29,6 +29,7 @@
29#include <linux/async.h> 29#include <linux/async.h>
30#include <linux/suspend.h> 30#include <linux/suspend.h>
31#include <trace/events/power.h> 31#include <trace/events/power.h>
32#include <linux/cpufreq.h>
32#include <linux/cpuidle.h> 33#include <linux/cpuidle.h>
33#include <linux/timer.h> 34#include <linux/timer.h>
34 35
@@ -540,6 +541,7 @@ static void dpm_resume_noirq(pm_message_t state)
540 dpm_show_time(starttime, state, "noirq"); 541 dpm_show_time(starttime, state, "noirq");
541 resume_device_irqs(); 542 resume_device_irqs();
542 cpuidle_resume(); 543 cpuidle_resume();
544 cpufreq_resume();
543} 545}
544 546
545/** 547/**
@@ -955,6 +957,7 @@ static int dpm_suspend_noirq(pm_message_t state)
955 ktime_t starttime = ktime_get(); 957 ktime_t starttime = ktime_get();
956 int error = 0; 958 int error = 0;
957 959
960 cpufreq_suspend();
958 cpuidle_pause(); 961 cpuidle_pause();
959 suspend_device_irqs(); 962 suspend_device_irqs();
960 mutex_lock(&dpm_list_mtx); 963 mutex_lock(&dpm_list_mtx);
diff --git a/drivers/block/xen-blkfront.c b/drivers/block/xen-blkfront.c
index 432db1b59b00..c4a4c9006288 100644
--- a/drivers/block/xen-blkfront.c
+++ b/drivers/block/xen-blkfront.c
@@ -489,7 +489,7 @@ static int blkif_queue_request(struct request *req)
489 489
490 if ((ring_req->operation == BLKIF_OP_INDIRECT) && 490 if ((ring_req->operation == BLKIF_OP_INDIRECT) &&
491 (i % SEGS_PER_INDIRECT_FRAME == 0)) { 491 (i % SEGS_PER_INDIRECT_FRAME == 0)) {
492 unsigned long pfn; 492 unsigned long uninitialized_var(pfn);
493 493
494 if (segments) 494 if (segments)
495 kunmap_atomic(segments); 495 kunmap_atomic(segments);
@@ -2011,6 +2011,10 @@ static void blkif_release(struct gendisk *disk, fmode_t mode)
2011 2011
2012 bdev = bdget_disk(disk, 0); 2012 bdev = bdget_disk(disk, 0);
2013 2013
2014 if (!bdev) {
2015 WARN(1, "Block device %s yanked out from us!\n", disk->disk_name);
2016 goto out_mutex;
2017 }
2014 if (bdev->bd_openers) 2018 if (bdev->bd_openers)
2015 goto out; 2019 goto out;
2016 2020
@@ -2041,6 +2045,7 @@ static void blkif_release(struct gendisk *disk, fmode_t mode)
2041 2045
2042out: 2046out:
2043 bdput(bdev); 2047 bdput(bdev);
2048out_mutex:
2044 mutex_unlock(&blkfront_mutex); 2049 mutex_unlock(&blkfront_mutex);
2045} 2050}
2046 2051
diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig
index c206de2951f2..2f2b08457c67 100644
--- a/drivers/char/hw_random/Kconfig
+++ b/drivers/char/hw_random/Kconfig
@@ -165,6 +165,19 @@ config HW_RANDOM_OMAP
165 165
166 If unsure, say Y. 166 If unsure, say Y.
167 167
168config HW_RANDOM_OMAP3_ROM
169 tristate "OMAP3 ROM Random Number Generator support"
170 depends on HW_RANDOM && ARCH_OMAP3
171 default HW_RANDOM
172 ---help---
173 This driver provides kernel-side support for the Random Number
174 Generator hardware found on OMAP34xx processors.
175
176 To compile this driver as a module, choose M here: the
177 module will be called omap3-rom-rng.
178
179 If unsure, say Y.
180
168config HW_RANDOM_OCTEON 181config HW_RANDOM_OCTEON
169 tristate "Octeon Random Number Generator support" 182 tristate "Octeon Random Number Generator support"
170 depends on HW_RANDOM && CAVIUM_OCTEON_SOC 183 depends on HW_RANDOM && CAVIUM_OCTEON_SOC
@@ -327,3 +340,15 @@ config HW_RANDOM_TPM
327 module will be called tpm-rng. 340 module will be called tpm-rng.
328 341
329 If unsure, say Y. 342 If unsure, say Y.
343
344config HW_RANDOM_MSM
345 tristate "Qualcomm MSM Random Number Generator support"
346 depends on HW_RANDOM && ARCH_MSM
347 ---help---
348 This driver provides kernel-side support for the Random Number
349 Generator hardware found on Qualcomm MSM SoCs.
350
351 To compile this driver as a module, choose M here. the
352 module will be called msm-rng.
353
354 If unsure, say Y.
diff --git a/drivers/char/hw_random/Makefile b/drivers/char/hw_random/Makefile
index d7d2435ff7fa..3ae7755a52e7 100644
--- a/drivers/char/hw_random/Makefile
+++ b/drivers/char/hw_random/Makefile
@@ -15,6 +15,7 @@ n2-rng-y := n2-drv.o n2-asm.o
15obj-$(CONFIG_HW_RANDOM_VIA) += via-rng.o 15obj-$(CONFIG_HW_RANDOM_VIA) += via-rng.o
16obj-$(CONFIG_HW_RANDOM_IXP4XX) += ixp4xx-rng.o 16obj-$(CONFIG_HW_RANDOM_IXP4XX) += ixp4xx-rng.o
17obj-$(CONFIG_HW_RANDOM_OMAP) += omap-rng.o 17obj-$(CONFIG_HW_RANDOM_OMAP) += omap-rng.o
18obj-$(CONFIG_HW_RANDOM_OMAP3_ROM) += omap3-rom-rng.o
18obj-$(CONFIG_HW_RANDOM_PASEMI) += pasemi-rng.o 19obj-$(CONFIG_HW_RANDOM_PASEMI) += pasemi-rng.o
19obj-$(CONFIG_HW_RANDOM_VIRTIO) += virtio-rng.o 20obj-$(CONFIG_HW_RANDOM_VIRTIO) += virtio-rng.o
20obj-$(CONFIG_HW_RANDOM_TX4939) += tx4939-rng.o 21obj-$(CONFIG_HW_RANDOM_TX4939) += tx4939-rng.o
@@ -28,3 +29,4 @@ obj-$(CONFIG_HW_RANDOM_POWERNV) += powernv-rng.o
28obj-$(CONFIG_HW_RANDOM_EXYNOS) += exynos-rng.o 29obj-$(CONFIG_HW_RANDOM_EXYNOS) += exynos-rng.o
29obj-$(CONFIG_HW_RANDOM_TPM) += tpm-rng.o 30obj-$(CONFIG_HW_RANDOM_TPM) += tpm-rng.o
30obj-$(CONFIG_HW_RANDOM_BCM2835) += bcm2835-rng.o 31obj-$(CONFIG_HW_RANDOM_BCM2835) += bcm2835-rng.o
32obj-$(CONFIG_HW_RANDOM_MSM) += msm-rng.o
diff --git a/drivers/char/hw_random/msm-rng.c b/drivers/char/hw_random/msm-rng.c
new file mode 100644
index 000000000000..148521e51dc6
--- /dev/null
+++ b/drivers/char/hw_random/msm-rng.c
@@ -0,0 +1,197 @@
1/*
2 * Copyright (c) 2011-2013, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 */
14#include <linux/clk.h>
15#include <linux/err.h>
16#include <linux/hw_random.h>
17#include <linux/io.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/platform_device.h>
21
22/* Device specific register offsets */
23#define PRNG_DATA_OUT 0x0000
24#define PRNG_STATUS 0x0004
25#define PRNG_LFSR_CFG 0x0100
26#define PRNG_CONFIG 0x0104
27
28/* Device specific register masks and config values */
29#define PRNG_LFSR_CFG_MASK 0x0000ffff
30#define PRNG_LFSR_CFG_CLOCKS 0x0000dddd
31#define PRNG_CONFIG_HW_ENABLE BIT(1)
32#define PRNG_STATUS_DATA_AVAIL BIT(0)
33
34#define MAX_HW_FIFO_DEPTH 16
35#define MAX_HW_FIFO_SIZE (MAX_HW_FIFO_DEPTH * 4)
36#define WORD_SZ 4
37
38struct msm_rng {
39 void __iomem *base;
40 struct clk *clk;
41 struct hwrng hwrng;
42};
43
44#define to_msm_rng(p) container_of(p, struct msm_rng, hwrng)
45
46static int msm_rng_enable(struct hwrng *hwrng, int enable)
47{
48 struct msm_rng *rng = to_msm_rng(hwrng);
49 u32 val;
50 int ret;
51
52 ret = clk_prepare_enable(rng->clk);
53 if (ret)
54 return ret;
55
56 if (enable) {
57 /* Enable PRNG only if it is not already enabled */
58 val = readl_relaxed(rng->base + PRNG_CONFIG);
59 if (val & PRNG_CONFIG_HW_ENABLE)
60 goto already_enabled;
61
62 val = readl_relaxed(rng->base + PRNG_LFSR_CFG);
63 val &= ~PRNG_LFSR_CFG_MASK;
64 val |= PRNG_LFSR_CFG_CLOCKS;
65 writel(val, rng->base + PRNG_LFSR_CFG);
66
67 val = readl_relaxed(rng->base + PRNG_CONFIG);
68 val |= PRNG_CONFIG_HW_ENABLE;
69 writel(val, rng->base + PRNG_CONFIG);
70 } else {
71 val = readl_relaxed(rng->base + PRNG_CONFIG);
72 val &= ~PRNG_CONFIG_HW_ENABLE;
73 writel(val, rng->base + PRNG_CONFIG);
74 }
75
76already_enabled:
77 clk_disable_unprepare(rng->clk);
78 return 0;
79}
80
81static int msm_rng_read(struct hwrng *hwrng, void *data, size_t max, bool wait)
82{
83 struct msm_rng *rng = to_msm_rng(hwrng);
84 size_t currsize = 0;
85 u32 *retdata = data;
86 size_t maxsize;
87 int ret;
88 u32 val;
89
90 /* calculate max size bytes to transfer back to caller */
91 maxsize = min_t(size_t, MAX_HW_FIFO_SIZE, max);
92
93 /* no room for word data */
94 if (maxsize < WORD_SZ)
95 return 0;
96
97 ret = clk_prepare_enable(rng->clk);
98 if (ret)
99 return ret;
100
101 /* read random data from hardware */
102 do {
103 val = readl_relaxed(rng->base + PRNG_STATUS);
104 if (!(val & PRNG_STATUS_DATA_AVAIL))
105 break;
106
107 val = readl_relaxed(rng->base + PRNG_DATA_OUT);
108 if (!val)
109 break;
110
111 *retdata++ = val;
112 currsize += WORD_SZ;
113
114 /* make sure we stay on 32bit boundary */
115 if ((maxsize - currsize) < WORD_SZ)
116 break;
117 } while (currsize < maxsize);
118
119 clk_disable_unprepare(rng->clk);
120
121 return currsize;
122}
123
124static int msm_rng_init(struct hwrng *hwrng)
125{
126 return msm_rng_enable(hwrng, 1);
127}
128
129static void msm_rng_cleanup(struct hwrng *hwrng)
130{
131 msm_rng_enable(hwrng, 0);
132}
133
134static int msm_rng_probe(struct platform_device *pdev)
135{
136 struct resource *res;
137 struct msm_rng *rng;
138 int ret;
139
140 rng = devm_kzalloc(&pdev->dev, sizeof(*rng), GFP_KERNEL);
141 if (!rng)
142 return -ENOMEM;
143
144 platform_set_drvdata(pdev, rng);
145
146 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
147 rng->base = devm_ioremap_resource(&pdev->dev, res);
148 if (IS_ERR(rng->base))
149 return PTR_ERR(rng->base);
150
151 rng->clk = devm_clk_get(&pdev->dev, "core");
152 if (IS_ERR(rng->clk))
153 return PTR_ERR(rng->clk);
154
155 rng->hwrng.name = KBUILD_MODNAME,
156 rng->hwrng.init = msm_rng_init,
157 rng->hwrng.cleanup = msm_rng_cleanup,
158 rng->hwrng.read = msm_rng_read,
159
160 ret = hwrng_register(&rng->hwrng);
161 if (ret) {
162 dev_err(&pdev->dev, "failed to register hwrng\n");
163 return ret;
164 }
165
166 return 0;
167}
168
169static int msm_rng_remove(struct platform_device *pdev)
170{
171 struct msm_rng *rng = platform_get_drvdata(pdev);
172
173 hwrng_unregister(&rng->hwrng);
174 return 0;
175}
176
177static const struct of_device_id msm_rng_of_match[] = {
178 { .compatible = "qcom,prng", },
179 {}
180};
181MODULE_DEVICE_TABLE(of, msm_rng_of_match);
182
183static struct platform_driver msm_rng_driver = {
184 .probe = msm_rng_probe,
185 .remove = msm_rng_remove,
186 .driver = {
187 .name = KBUILD_MODNAME,
188 .owner = THIS_MODULE,
189 .of_match_table = of_match_ptr(msm_rng_of_match),
190 }
191};
192module_platform_driver(msm_rng_driver);
193
194MODULE_ALIAS("platform:" KBUILD_MODNAME);
195MODULE_AUTHOR("The Linux Foundation");
196MODULE_DESCRIPTION("Qualcomm MSM random number generator driver");
197MODULE_LICENSE("GPL v2");
diff --git a/drivers/char/hw_random/omap3-rom-rng.c b/drivers/char/hw_random/omap3-rom-rng.c
new file mode 100644
index 000000000000..c853e9e68573
--- /dev/null
+++ b/drivers/char/hw_random/omap3-rom-rng.c
@@ -0,0 +1,141 @@
1/*
2 * omap3-rom-rng.c - RNG driver for TI OMAP3 CPU family
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Juha Yrjola <juha.yrjola@solidboot.com>
6 *
7 * Copyright (C) 2013 Pali Rohár <pali.rohar@gmail.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15
16#include <linux/module.h>
17#include <linux/init.h>
18#include <linux/random.h>
19#include <linux/hw_random.h>
20#include <linux/timer.h>
21#include <linux/clk.h>
22#include <linux/err.h>
23#include <linux/platform_device.h>
24
25#define RNG_RESET 0x01
26#define RNG_GEN_PRNG_HW_INIT 0x02
27#define RNG_GEN_HW 0x08
28
29/* param1: ptr, param2: count, param3: flag */
30static u32 (*omap3_rom_rng_call)(u32, u32, u32);
31
32static struct timer_list idle_timer;
33static int rng_idle;
34static struct clk *rng_clk;
35
36static void omap3_rom_rng_idle(unsigned long data)
37{
38 int r;
39
40 r = omap3_rom_rng_call(0, 0, RNG_RESET);
41 if (r != 0) {
42 pr_err("reset failed: %d\n", r);
43 return;
44 }
45 clk_disable_unprepare(rng_clk);
46 rng_idle = 1;
47}
48
49static int omap3_rom_rng_get_random(void *buf, unsigned int count)
50{
51 u32 r;
52 u32 ptr;
53
54 del_timer_sync(&idle_timer);
55 if (rng_idle) {
56 clk_prepare_enable(rng_clk);
57 r = omap3_rom_rng_call(0, 0, RNG_GEN_PRNG_HW_INIT);
58 if (r != 0) {
59 clk_disable_unprepare(rng_clk);
60 pr_err("HW init failed: %d\n", r);
61 return -EIO;
62 }
63 rng_idle = 0;
64 }
65
66 ptr = virt_to_phys(buf);
67 r = omap3_rom_rng_call(ptr, count, RNG_GEN_HW);
68 mod_timer(&idle_timer, jiffies + msecs_to_jiffies(500));
69 if (r != 0)
70 return -EINVAL;
71 return 0;
72}
73
74static int omap3_rom_rng_data_present(struct hwrng *rng, int wait)
75{
76 return 1;
77}
78
79static int omap3_rom_rng_data_read(struct hwrng *rng, u32 *data)
80{
81 int r;
82
83 r = omap3_rom_rng_get_random(data, 4);
84 if (r < 0)
85 return r;
86 return 4;
87}
88
89static struct hwrng omap3_rom_rng_ops = {
90 .name = "omap3-rom",
91 .data_present = omap3_rom_rng_data_present,
92 .data_read = omap3_rom_rng_data_read,
93};
94
95static int omap3_rom_rng_probe(struct platform_device *pdev)
96{
97 pr_info("initializing\n");
98
99 omap3_rom_rng_call = pdev->dev.platform_data;
100 if (!omap3_rom_rng_call) {
101 pr_err("omap3_rom_rng_call is NULL\n");
102 return -EINVAL;
103 }
104
105 setup_timer(&idle_timer, omap3_rom_rng_idle, 0);
106 rng_clk = clk_get(&pdev->dev, "ick");
107 if (IS_ERR(rng_clk)) {
108 pr_err("unable to get RNG clock\n");
109 return PTR_ERR(rng_clk);
110 }
111
112 /* Leave the RNG in reset state. */
113 clk_prepare_enable(rng_clk);
114 omap3_rom_rng_idle(0);
115
116 return hwrng_register(&omap3_rom_rng_ops);
117}
118
119static int omap3_rom_rng_remove(struct platform_device *pdev)
120{
121 hwrng_unregister(&omap3_rom_rng_ops);
122 clk_disable_unprepare(rng_clk);
123 clk_put(rng_clk);
124 return 0;
125}
126
127static struct platform_driver omap3_rom_rng_driver = {
128 .driver = {
129 .name = "omap3-rom-rng",
130 .owner = THIS_MODULE,
131 },
132 .probe = omap3_rom_rng_probe,
133 .remove = omap3_rom_rng_remove,
134};
135
136module_platform_driver(omap3_rom_rng_driver);
137
138MODULE_ALIAS("platform:omap3-rom-rng");
139MODULE_AUTHOR("Juha Yrjola");
140MODULE_AUTHOR("Pali Rohár <pali.rohar@gmail.com>");
141MODULE_LICENSE("GPL");
diff --git a/drivers/char/hw_random/pseries-rng.c b/drivers/char/hw_random/pseries-rng.c
index b761459a3436..ab7ffdec0ec3 100644
--- a/drivers/char/hw_random/pseries-rng.c
+++ b/drivers/char/hw_random/pseries-rng.c
@@ -24,7 +24,6 @@
24#include <linux/hw_random.h> 24#include <linux/hw_random.h>
25#include <asm/vio.h> 25#include <asm/vio.h>
26 26
27#define MODULE_NAME "pseries-rng"
28 27
29static int pseries_rng_data_read(struct hwrng *rng, u32 *data) 28static int pseries_rng_data_read(struct hwrng *rng, u32 *data)
30{ 29{
@@ -55,7 +54,7 @@ static unsigned long pseries_rng_get_desired_dma(struct vio_dev *vdev)
55}; 54};
56 55
57static struct hwrng pseries_rng = { 56static struct hwrng pseries_rng = {
58 .name = MODULE_NAME, 57 .name = KBUILD_MODNAME,
59 .data_read = pseries_rng_data_read, 58 .data_read = pseries_rng_data_read,
60}; 59};
61 60
@@ -78,7 +77,7 @@ static struct vio_device_id pseries_rng_driver_ids[] = {
78MODULE_DEVICE_TABLE(vio, pseries_rng_driver_ids); 77MODULE_DEVICE_TABLE(vio, pseries_rng_driver_ids);
79 78
80static struct vio_driver pseries_rng_driver = { 79static struct vio_driver pseries_rng_driver = {
81 .name = MODULE_NAME, 80 .name = KBUILD_MODNAME,
82 .probe = pseries_rng_probe, 81 .probe = pseries_rng_probe,
83 .remove = pseries_rng_remove, 82 .remove = pseries_rng_remove,
84 .get_desired_dma = pseries_rng_get_desired_dma, 83 .get_desired_dma = pseries_rng_get_desired_dma,
diff --git a/drivers/char/hw_random/via-rng.c b/drivers/char/hw_random/via-rng.c
index e737772ad69a..de5a6dcfb3e2 100644
--- a/drivers/char/hw_random/via-rng.c
+++ b/drivers/char/hw_random/via-rng.c
@@ -221,7 +221,7 @@ static void __exit mod_exit(void)
221module_init(mod_init); 221module_init(mod_init);
222module_exit(mod_exit); 222module_exit(mod_exit);
223 223
224static struct x86_cpu_id via_rng_cpu_id[] = { 224static struct x86_cpu_id __maybe_unused via_rng_cpu_id[] = {
225 X86_FEATURE_MATCH(X86_FEATURE_XSTORE), 225 X86_FEATURE_MATCH(X86_FEATURE_XSTORE),
226 {} 226 {}
227}; 227};
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 7a10bc9a23e7..ace7309c4369 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -35,6 +35,7 @@ obj-$(CONFIG_ARCH_TEGRA) += tegra/
35obj-$(CONFIG_PLAT_SAMSUNG) += samsung/ 35obj-$(CONFIG_PLAT_SAMSUNG) += samsung/
36obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o 36obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o
37obj-$(CONFIG_COMMON_CLK_KEYSTONE) += keystone/ 37obj-$(CONFIG_COMMON_CLK_KEYSTONE) += keystone/
38obj-$(CONFIG_COMMON_CLK_AT91) += at91/
38 39
39obj-$(CONFIG_X86) += x86/ 40obj-$(CONFIG_X86) += x86/
40 41
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
new file mode 100644
index 000000000000..0e92b716f934
--- /dev/null
+++ b/drivers/clk/at91/Makefile
@@ -0,0 +1,12 @@
1#
2# Makefile for at91 specific clk
3#
4
5obj-y += pmc.o
6obj-y += clk-main.o clk-pll.o clk-plldiv.o clk-master.o
7obj-y += clk-system.o clk-peripheral.o
8
9obj-$(CONFIG_AT91_PROGRAMMABLE_CLOCKS) += clk-programmable.o
10obj-$(CONFIG_HAVE_AT91_UTMI) += clk-utmi.o
11obj-$(CONFIG_HAVE_AT91_USB_CLK) += clk-usb.o
12obj-$(CONFIG_HAVE_AT91_SMD) += clk-smd.o
diff --git a/drivers/clk/at91/clk-main.c b/drivers/clk/at91/clk-main.c
new file mode 100644
index 000000000000..8e9e8cc0412d
--- /dev/null
+++ b/drivers/clk/at91/clk-main.c
@@ -0,0 +1,187 @@
1/*
2 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 */
10
11#include <linux/clk-provider.h>
12#include <linux/clkdev.h>
13#include <linux/clk/at91_pmc.h>
14#include <linux/delay.h>
15#include <linux/of.h>
16#include <linux/of_address.h>
17#include <linux/of_irq.h>
18#include <linux/io.h>
19#include <linux/interrupt.h>
20#include <linux/irq.h>
21#include <linux/sched.h>
22#include <linux/wait.h>
23
24#include "pmc.h"
25
26#define SLOW_CLOCK_FREQ 32768
27#define MAINF_DIV 16
28#define MAINFRDY_TIMEOUT (((MAINF_DIV + 1) * USEC_PER_SEC) / \
29 SLOW_CLOCK_FREQ)
30#define MAINF_LOOP_MIN_WAIT (USEC_PER_SEC / SLOW_CLOCK_FREQ)
31#define MAINF_LOOP_MAX_WAIT MAINFRDY_TIMEOUT
32
33struct clk_main {
34 struct clk_hw hw;
35 struct at91_pmc *pmc;
36 unsigned long rate;
37 unsigned int irq;
38 wait_queue_head_t wait;
39};
40
41#define to_clk_main(hw) container_of(hw, struct clk_main, hw)
42
43static irqreturn_t clk_main_irq_handler(int irq, void *dev_id)
44{
45 struct clk_main *clkmain = (struct clk_main *)dev_id;
46
47 wake_up(&clkmain->wait);
48 disable_irq_nosync(clkmain->irq);
49
50 return IRQ_HANDLED;
51}
52
53static int clk_main_prepare(struct clk_hw *hw)
54{
55 struct clk_main *clkmain = to_clk_main(hw);
56 struct at91_pmc *pmc = clkmain->pmc;
57 unsigned long halt_time, timeout;
58 u32 tmp;
59
60 while (!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCS)) {
61 enable_irq(clkmain->irq);
62 wait_event(clkmain->wait,
63 pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCS);
64 }
65
66 if (clkmain->rate)
67 return 0;
68
69 timeout = jiffies + usecs_to_jiffies(MAINFRDY_TIMEOUT);
70 do {
71 halt_time = jiffies;
72 tmp = pmc_read(pmc, AT91_CKGR_MCFR);
73 if (tmp & AT91_PMC_MAINRDY)
74 return 0;
75 usleep_range(MAINF_LOOP_MIN_WAIT, MAINF_LOOP_MAX_WAIT);
76 } while (time_before(halt_time, timeout));
77
78 return 0;
79}
80
81static int clk_main_is_prepared(struct clk_hw *hw)
82{
83 struct clk_main *clkmain = to_clk_main(hw);
84
85 return !!(pmc_read(clkmain->pmc, AT91_PMC_SR) & AT91_PMC_MOSCS);
86}
87
88static unsigned long clk_main_recalc_rate(struct clk_hw *hw,
89 unsigned long parent_rate)
90{
91 u32 tmp;
92 struct clk_main *clkmain = to_clk_main(hw);
93 struct at91_pmc *pmc = clkmain->pmc;
94
95 if (clkmain->rate)
96 return clkmain->rate;
97
98 tmp = pmc_read(pmc, AT91_CKGR_MCFR) & AT91_PMC_MAINF;
99 clkmain->rate = (tmp * parent_rate) / MAINF_DIV;
100
101 return clkmain->rate;
102}
103
104static const struct clk_ops main_ops = {
105 .prepare = clk_main_prepare,
106 .is_prepared = clk_main_is_prepared,
107 .recalc_rate = clk_main_recalc_rate,
108};
109
110static struct clk * __init
111at91_clk_register_main(struct at91_pmc *pmc,
112 unsigned int irq,
113 const char *name,
114 const char *parent_name,
115 unsigned long rate)
116{
117 int ret;
118 struct clk_main *clkmain;
119 struct clk *clk = NULL;
120 struct clk_init_data init;
121
122 if (!pmc || !irq || !name)
123 return ERR_PTR(-EINVAL);
124
125 if (!rate && !parent_name)
126 return ERR_PTR(-EINVAL);
127
128 clkmain = kzalloc(sizeof(*clkmain), GFP_KERNEL);
129 if (!clkmain)
130 return ERR_PTR(-ENOMEM);
131
132 init.name = name;
133 init.ops = &main_ops;
134 init.parent_names = parent_name ? &parent_name : NULL;
135 init.num_parents = parent_name ? 1 : 0;
136 init.flags = parent_name ? 0 : CLK_IS_ROOT;
137
138 clkmain->hw.init = &init;
139 clkmain->rate = rate;
140 clkmain->pmc = pmc;
141 clkmain->irq = irq;
142 init_waitqueue_head(&clkmain->wait);
143 irq_set_status_flags(clkmain->irq, IRQ_NOAUTOEN);
144 ret = request_irq(clkmain->irq, clk_main_irq_handler,
145 IRQF_TRIGGER_HIGH, "clk-main", clkmain);
146 if (ret)
147 return ERR_PTR(ret);
148
149 clk = clk_register(NULL, &clkmain->hw);
150 if (IS_ERR(clk)) {
151 free_irq(clkmain->irq, clkmain);
152 kfree(clkmain);
153 }
154
155 return clk;
156}
157
158
159
160static void __init
161of_at91_clk_main_setup(struct device_node *np, struct at91_pmc *pmc)
162{
163 struct clk *clk;
164 unsigned int irq;
165 const char *parent_name;
166 const char *name = np->name;
167 u32 rate = 0;
168
169 parent_name = of_clk_get_parent_name(np, 0);
170 of_property_read_string(np, "clock-output-names", &name);
171 of_property_read_u32(np, "clock-frequency", &rate);
172 irq = irq_of_parse_and_map(np, 0);
173 if (!irq)
174 return;
175
176 clk = at91_clk_register_main(pmc, irq, name, parent_name, rate);
177 if (IS_ERR(clk))
178 return;
179
180 of_clk_add_provider(np, of_clk_src_simple_get, clk);
181}
182
183void __init of_at91rm9200_clk_main_setup(struct device_node *np,
184 struct at91_pmc *pmc)
185{
186 of_at91_clk_main_setup(np, pmc);
187}
diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c
new file mode 100644
index 000000000000..bd313f7816a8
--- /dev/null
+++ b/drivers/clk/at91/clk-master.c
@@ -0,0 +1,270 @@
1/*
2 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 */
10
11#include <linux/clk-provider.h>
12#include <linux/clkdev.h>
13#include <linux/clk/at91_pmc.h>
14#include <linux/of.h>
15#include <linux/of_address.h>
16#include <linux/of_irq.h>
17#include <linux/io.h>
18#include <linux/wait.h>
19#include <linux/sched.h>
20#include <linux/interrupt.h>
21#include <linux/irq.h>
22
23#include "pmc.h"
24
25#define MASTER_SOURCE_MAX 4
26
27#define MASTER_PRES_MASK 0x7
28#define MASTER_PRES_MAX MASTER_PRES_MASK
29#define MASTER_DIV_SHIFT 8
30#define MASTER_DIV_MASK 0x3
31
32struct clk_master_characteristics {
33 struct clk_range output;
34 u32 divisors[4];
35 u8 have_div3_pres;
36};
37
38struct clk_master_layout {
39 u32 mask;
40 u8 pres_shift;
41};
42
43#define to_clk_master(hw) container_of(hw, struct clk_master, hw)
44
45struct clk_master {
46 struct clk_hw hw;
47 struct at91_pmc *pmc;
48 unsigned int irq;
49 wait_queue_head_t wait;
50 const struct clk_master_layout *layout;
51 const struct clk_master_characteristics *characteristics;
52};
53
54static irqreturn_t clk_master_irq_handler(int irq, void *dev_id)
55{
56 struct clk_master *master = (struct clk_master *)dev_id;
57
58 wake_up(&master->wait);
59 disable_irq_nosync(master->irq);
60
61 return IRQ_HANDLED;
62}
63static int clk_master_prepare(struct clk_hw *hw)
64{
65 struct clk_master *master = to_clk_master(hw);
66 struct at91_pmc *pmc = master->pmc;
67
68 while (!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MCKRDY)) {
69 enable_irq(master->irq);
70 wait_event(master->wait,
71 pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MCKRDY);
72 }
73
74 return 0;
75}
76
77static int clk_master_is_prepared(struct clk_hw *hw)
78{
79 struct clk_master *master = to_clk_master(hw);
80
81 return !!(pmc_read(master->pmc, AT91_PMC_SR) & AT91_PMC_MCKRDY);
82}
83
84static unsigned long clk_master_recalc_rate(struct clk_hw *hw,
85 unsigned long parent_rate)
86{
87 u8 pres;
88 u8 div;
89 unsigned long rate = parent_rate;
90 struct clk_master *master = to_clk_master(hw);
91 struct at91_pmc *pmc = master->pmc;
92 const struct clk_master_layout *layout = master->layout;
93 const struct clk_master_characteristics *characteristics =
94 master->characteristics;
95 u32 tmp;
96
97 pmc_lock(pmc);
98 tmp = pmc_read(pmc, AT91_PMC_MCKR) & layout->mask;
99 pmc_unlock(pmc);
100
101 pres = (tmp >> layout->pres_shift) & MASTER_PRES_MASK;
102 div = (tmp >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;
103
104 if (characteristics->have_div3_pres && pres == MASTER_PRES_MAX)
105 rate /= 3;
106 else
107 rate >>= pres;
108
109 rate /= characteristics->divisors[div];
110
111 if (rate < characteristics->output.min)
112 pr_warn("master clk is underclocked");
113 else if (rate > characteristics->output.max)
114 pr_warn("master clk is overclocked");
115
116 return rate;
117}
118
119static u8 clk_master_get_parent(struct clk_hw *hw)
120{
121 struct clk_master *master = to_clk_master(hw);
122 struct at91_pmc *pmc = master->pmc;
123
124 return pmc_read(pmc, AT91_PMC_MCKR) & AT91_PMC_CSS;
125}
126
127static const struct clk_ops master_ops = {
128 .prepare = clk_master_prepare,
129 .is_prepared = clk_master_is_prepared,
130 .recalc_rate = clk_master_recalc_rate,
131 .get_parent = clk_master_get_parent,
132};
133
134static struct clk * __init
135at91_clk_register_master(struct at91_pmc *pmc, unsigned int irq,
136 const char *name, int num_parents,
137 const char **parent_names,
138 const struct clk_master_layout *layout,
139 const struct clk_master_characteristics *characteristics)
140{
141 int ret;
142 struct clk_master *master;
143 struct clk *clk = NULL;
144 struct clk_init_data init;
145
146 if (!pmc || !irq || !name || !num_parents || !parent_names)
147 return ERR_PTR(-EINVAL);
148
149 master = kzalloc(sizeof(*master), GFP_KERNEL);
150 if (!master)
151 return ERR_PTR(-ENOMEM);
152
153 init.name = name;
154 init.ops = &master_ops;
155 init.parent_names = parent_names;
156 init.num_parents = num_parents;
157 init.flags = 0;
158
159 master->hw.init = &init;
160 master->layout = layout;
161 master->characteristics = characteristics;
162 master->pmc = pmc;
163 master->irq = irq;
164 init_waitqueue_head(&master->wait);
165 irq_set_status_flags(master->irq, IRQ_NOAUTOEN);
166 ret = request_irq(master->irq, clk_master_irq_handler,
167 IRQF_TRIGGER_HIGH, "clk-master", master);
168 if (ret)
169 return ERR_PTR(ret);
170
171 clk = clk_register(NULL, &master->hw);
172 if (IS_ERR(clk))
173 kfree(master);
174
175 return clk;
176}
177
178
179static const struct clk_master_layout at91rm9200_master_layout = {
180 .mask = 0x31F,
181 .pres_shift = 2,
182};
183
184static const struct clk_master_layout at91sam9x5_master_layout = {
185 .mask = 0x373,
186 .pres_shift = 4,
187};
188
189
190static struct clk_master_characteristics * __init
191of_at91_clk_master_get_characteristics(struct device_node *np)
192{
193 struct clk_master_characteristics *characteristics;
194
195 characteristics = kzalloc(sizeof(*characteristics), GFP_KERNEL);
196 if (!characteristics)
197 return NULL;
198
199 if (of_at91_get_clk_range(np, "atmel,clk-output-range", &characteristics->output))
200 goto out_free_characteristics;
201
202 of_property_read_u32_array(np, "atmel,clk-divisors",
203 characteristics->divisors, 4);
204
205 characteristics->have_div3_pres =
206 of_property_read_bool(np, "atmel,master-clk-have-div3-pres");
207
208 return characteristics;
209
210out_free_characteristics:
211 kfree(characteristics);
212 return NULL;
213}
214
215static void __init
216of_at91_clk_master_setup(struct device_node *np, struct at91_pmc *pmc,
217 const struct clk_master_layout *layout)
218{
219 struct clk *clk;
220 int num_parents;
221 int i;
222 unsigned int irq;
223 const char *parent_names[MASTER_SOURCE_MAX];
224 const char *name = np->name;
225 struct clk_master_characteristics *characteristics;
226
227 num_parents = of_count_phandle_with_args(np, "clocks", "#clock-cells");
228 if (num_parents <= 0 || num_parents > MASTER_SOURCE_MAX)
229 return;
230
231 for (i = 0; i < num_parents; ++i) {
232 parent_names[i] = of_clk_get_parent_name(np, i);
233 if (!parent_names[i])
234 return;
235 }
236
237 of_property_read_string(np, "clock-output-names", &name);
238
239 characteristics = of_at91_clk_master_get_characteristics(np);
240 if (!characteristics)
241 return;
242
243 irq = irq_of_parse_and_map(np, 0);
244 if (!irq)
245 return;
246
247 clk = at91_clk_register_master(pmc, irq, name, num_parents,
248 parent_names, layout,
249 characteristics);
250 if (IS_ERR(clk))
251 goto out_free_characteristics;
252
253 of_clk_add_provider(np, of_clk_src_simple_get, clk);
254 return;
255
256out_free_characteristics:
257 kfree(characteristics);
258}
259
260void __init of_at91rm9200_clk_master_setup(struct device_node *np,
261 struct at91_pmc *pmc)
262{
263 of_at91_clk_master_setup(np, pmc, &at91rm9200_master_layout);
264}
265
266void __init of_at91sam9x5_clk_master_setup(struct device_node *np,
267 struct at91_pmc *pmc)
268{
269 of_at91_clk_master_setup(np, pmc, &at91sam9x5_master_layout);
270}
diff --git a/drivers/clk/at91/clk-peripheral.c b/drivers/clk/at91/clk-peripheral.c
new file mode 100644
index 000000000000..597fed423d7d
--- /dev/null
+++ b/drivers/clk/at91/clk-peripheral.c
@@ -0,0 +1,410 @@
1/*
2 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 */
10
11#include <linux/clk-provider.h>
12#include <linux/clkdev.h>
13#include <linux/clk/at91_pmc.h>
14#include <linux/of.h>
15#include <linux/of_address.h>
16#include <linux/io.h>
17
18#include "pmc.h"
19
20#define PERIPHERAL_MAX 64
21
22#define PERIPHERAL_AT91RM9200 0
23#define PERIPHERAL_AT91SAM9X5 1
24
25#define PERIPHERAL_ID_MIN 2
26#define PERIPHERAL_ID_MAX 31
27#define PERIPHERAL_MASK(id) (1 << ((id) & PERIPHERAL_ID_MAX))
28
29#define PERIPHERAL_RSHIFT_MASK 0x3
30#define PERIPHERAL_RSHIFT(val) (((val) >> 16) & PERIPHERAL_RSHIFT_MASK)
31
32#define PERIPHERAL_MAX_SHIFT 4
33
34struct clk_peripheral {
35 struct clk_hw hw;
36 struct at91_pmc *pmc;
37 u32 id;
38};
39
40#define to_clk_peripheral(hw) container_of(hw, struct clk_peripheral, hw)
41
42struct clk_sam9x5_peripheral {
43 struct clk_hw hw;
44 struct at91_pmc *pmc;
45 struct clk_range range;
46 u32 id;
47 u32 div;
48 bool auto_div;
49};
50
51#define to_clk_sam9x5_peripheral(hw) \
52 container_of(hw, struct clk_sam9x5_peripheral, hw)
53
54static int clk_peripheral_enable(struct clk_hw *hw)
55{
56 struct clk_peripheral *periph = to_clk_peripheral(hw);
57 struct at91_pmc *pmc = periph->pmc;
58 int offset = AT91_PMC_PCER;
59 u32 id = periph->id;
60
61 if (id < PERIPHERAL_ID_MIN)
62 return 0;
63 if (id > PERIPHERAL_ID_MAX)
64 offset = AT91_PMC_PCER1;
65 pmc_write(pmc, offset, PERIPHERAL_MASK(id));
66 return 0;
67}
68
69static void clk_peripheral_disable(struct clk_hw *hw)
70{
71 struct clk_peripheral *periph = to_clk_peripheral(hw);
72 struct at91_pmc *pmc = periph->pmc;
73 int offset = AT91_PMC_PCDR;
74 u32 id = periph->id;
75
76 if (id < PERIPHERAL_ID_MIN)
77 return;
78 if (id > PERIPHERAL_ID_MAX)
79 offset = AT91_PMC_PCDR1;
80 pmc_write(pmc, offset, PERIPHERAL_MASK(id));
81}
82
83static int clk_peripheral_is_enabled(struct clk_hw *hw)
84{
85 struct clk_peripheral *periph = to_clk_peripheral(hw);
86 struct at91_pmc *pmc = periph->pmc;
87 int offset = AT91_PMC_PCSR;
88 u32 id = periph->id;
89
90 if (id < PERIPHERAL_ID_MIN)
91 return 1;
92 if (id > PERIPHERAL_ID_MAX)
93 offset = AT91_PMC_PCSR1;
94 return !!(pmc_read(pmc, offset) & PERIPHERAL_MASK(id));
95}
96
97static const struct clk_ops peripheral_ops = {
98 .enable = clk_peripheral_enable,
99 .disable = clk_peripheral_disable,
100 .is_enabled = clk_peripheral_is_enabled,
101};
102
103static struct clk * __init
104at91_clk_register_peripheral(struct at91_pmc *pmc, const char *name,
105 const char *parent_name, u32 id)
106{
107 struct clk_peripheral *periph;
108 struct clk *clk = NULL;
109 struct clk_init_data init;
110
111 if (!pmc || !name || !parent_name || id > PERIPHERAL_ID_MAX)
112 return ERR_PTR(-EINVAL);
113
114 periph = kzalloc(sizeof(*periph), GFP_KERNEL);
115 if (!periph)
116 return ERR_PTR(-ENOMEM);
117
118 init.name = name;
119 init.ops = &peripheral_ops;
120 init.parent_names = (parent_name ? &parent_name : NULL);
121 init.num_parents = (parent_name ? 1 : 0);
122 init.flags = 0;
123
124 periph->id = id;
125 periph->hw.init = &init;
126 periph->pmc = pmc;
127
128 clk = clk_register(NULL, &periph->hw);
129 if (IS_ERR(clk))
130 kfree(periph);
131
132 return clk;
133}
134
135static void clk_sam9x5_peripheral_autodiv(struct clk_sam9x5_peripheral *periph)
136{
137 struct clk *parent;
138 unsigned long parent_rate;
139 int shift = 0;
140
141 if (!periph->auto_div)
142 return;
143
144 if (periph->range.max) {
145 parent = clk_get_parent_by_index(periph->hw.clk, 0);
146 parent_rate = __clk_get_rate(parent);
147 if (!parent_rate)
148 return;
149
150 for (; shift < PERIPHERAL_MAX_SHIFT; shift++) {
151 if (parent_rate >> shift <= periph->range.max)
152 break;
153 }
154 }
155
156 periph->auto_div = false;
157 periph->div = shift;
158}
159
160static int clk_sam9x5_peripheral_enable(struct clk_hw *hw)
161{
162 struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
163 struct at91_pmc *pmc = periph->pmc;
164
165 if (periph->id < PERIPHERAL_ID_MIN)
166 return 0;
167
168 pmc_write(pmc, AT91_PMC_PCR, (periph->id & AT91_PMC_PCR_PID) |
169 AT91_PMC_PCR_CMD |
170 AT91_PMC_PCR_DIV(periph->div) |
171 AT91_PMC_PCR_EN);
172 return 0;
173}
174
175static void clk_sam9x5_peripheral_disable(struct clk_hw *hw)
176{
177 struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
178 struct at91_pmc *pmc = periph->pmc;
179
180 if (periph->id < PERIPHERAL_ID_MIN)
181 return;
182
183 pmc_write(pmc, AT91_PMC_PCR, (periph->id & AT91_PMC_PCR_PID) |
184 AT91_PMC_PCR_CMD);
185}
186
187static int clk_sam9x5_peripheral_is_enabled(struct clk_hw *hw)
188{
189 struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
190 struct at91_pmc *pmc = periph->pmc;
191 int ret;
192
193 if (periph->id < PERIPHERAL_ID_MIN)
194 return 1;
195
196 pmc_lock(pmc);
197 pmc_write(pmc, AT91_PMC_PCR, (periph->id & AT91_PMC_PCR_PID));
198 ret = !!(pmc_read(pmc, AT91_PMC_PCR) & AT91_PMC_PCR_EN);
199 pmc_unlock(pmc);
200
201 return ret;
202}
203
204static unsigned long
205clk_sam9x5_peripheral_recalc_rate(struct clk_hw *hw,
206 unsigned long parent_rate)
207{
208 struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
209 struct at91_pmc *pmc = periph->pmc;
210 u32 tmp;
211
212 if (periph->id < PERIPHERAL_ID_MIN)
213 return parent_rate;
214
215 pmc_lock(pmc);
216 pmc_write(pmc, AT91_PMC_PCR, (periph->id & AT91_PMC_PCR_PID));
217 tmp = pmc_read(pmc, AT91_PMC_PCR);
218 pmc_unlock(pmc);
219
220 if (tmp & AT91_PMC_PCR_EN) {
221 periph->div = PERIPHERAL_RSHIFT(tmp);
222 periph->auto_div = false;
223 } else {
224 clk_sam9x5_peripheral_autodiv(periph);
225 }
226
227 return parent_rate >> periph->div;
228}
229
230static long clk_sam9x5_peripheral_round_rate(struct clk_hw *hw,
231 unsigned long rate,
232 unsigned long *parent_rate)
233{
234 int shift = 0;
235 unsigned long best_rate;
236 unsigned long best_diff;
237 unsigned long cur_rate = *parent_rate;
238 unsigned long cur_diff;
239 struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
240
241 if (periph->id < PERIPHERAL_ID_MIN || !periph->range.max)
242 return *parent_rate;
243
244 if (periph->range.max) {
245 for (; shift < PERIPHERAL_MAX_SHIFT; shift++) {
246 cur_rate = *parent_rate >> shift;
247 if (cur_rate <= periph->range.max)
248 break;
249 }
250 }
251
252 if (rate >= cur_rate)
253 return cur_rate;
254
255 best_diff = cur_rate - rate;
256 best_rate = cur_rate;
257 for (; shift < PERIPHERAL_MAX_SHIFT; shift++) {
258 cur_rate = *parent_rate >> shift;
259 if (cur_rate < rate)
260 cur_diff = rate - cur_rate;
261 else
262 cur_diff = cur_rate - rate;
263
264 if (cur_diff < best_diff) {
265 best_diff = cur_diff;
266 best_rate = cur_rate;
267 }
268
269 if (!best_diff || cur_rate < rate)
270 break;
271 }
272
273 return best_rate;
274}
275
276static int clk_sam9x5_peripheral_set_rate(struct clk_hw *hw,
277 unsigned long rate,
278 unsigned long parent_rate)
279{
280 int shift;
281 struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
282 if (periph->id < PERIPHERAL_ID_MIN || !periph->range.max) {
283 if (parent_rate == rate)
284 return 0;
285 else
286 return -EINVAL;
287 }
288
289 if (periph->range.max && rate > periph->range.max)
290 return -EINVAL;
291
292 for (shift = 0; shift < PERIPHERAL_MAX_SHIFT; shift++) {
293 if (parent_rate >> shift == rate) {
294 periph->auto_div = false;
295 periph->div = shift;
296 return 0;
297 }
298 }
299
300 return -EINVAL;
301}
302
303static const struct clk_ops sam9x5_peripheral_ops = {
304 .enable = clk_sam9x5_peripheral_enable,
305 .disable = clk_sam9x5_peripheral_disable,
306 .is_enabled = clk_sam9x5_peripheral_is_enabled,
307 .recalc_rate = clk_sam9x5_peripheral_recalc_rate,
308 .round_rate = clk_sam9x5_peripheral_round_rate,
309 .set_rate = clk_sam9x5_peripheral_set_rate,
310};
311
312static struct clk * __init
313at91_clk_register_sam9x5_peripheral(struct at91_pmc *pmc, const char *name,
314 const char *parent_name, u32 id,
315 const struct clk_range *range)
316{
317 struct clk_sam9x5_peripheral *periph;
318 struct clk *clk = NULL;
319 struct clk_init_data init;
320
321 if (!pmc || !name || !parent_name)
322 return ERR_PTR(-EINVAL);
323
324 periph = kzalloc(sizeof(*periph), GFP_KERNEL);
325 if (!periph)
326 return ERR_PTR(-ENOMEM);
327
328 init.name = name;
329 init.ops = &sam9x5_peripheral_ops;
330 init.parent_names = (parent_name ? &parent_name : NULL);
331 init.num_parents = (parent_name ? 1 : 0);
332 init.flags = 0;
333
334 periph->id = id;
335 periph->hw.init = &init;
336 periph->div = 0;
337 periph->pmc = pmc;
338 periph->auto_div = true;
339 periph->range = *range;
340
341 clk = clk_register(NULL, &periph->hw);
342 if (IS_ERR(clk))
343 kfree(periph);
344 else
345 clk_sam9x5_peripheral_autodiv(periph);
346
347 return clk;
348}
349
350static void __init
351of_at91_clk_periph_setup(struct device_node *np, struct at91_pmc *pmc, u8 type)
352{
353 int num;
354 u32 id;
355 struct clk *clk;
356 const char *parent_name;
357 const char *name;
358 struct device_node *periphclknp;
359
360 parent_name = of_clk_get_parent_name(np, 0);
361 if (!parent_name)
362 return;
363
364 num = of_get_child_count(np);
365 if (!num || num > PERIPHERAL_MAX)
366 return;
367
368 for_each_child_of_node(np, periphclknp) {
369 if (of_property_read_u32(periphclknp, "reg", &id))
370 continue;
371
372 if (id >= PERIPHERAL_MAX)
373 continue;
374
375 if (of_property_read_string(np, "clock-output-names", &name))
376 name = periphclknp->name;
377
378 if (type == PERIPHERAL_AT91RM9200) {
379 clk = at91_clk_register_peripheral(pmc, name,
380 parent_name, id);
381 } else {
382 struct clk_range range = CLK_RANGE(0, 0);
383
384 of_at91_get_clk_range(periphclknp,
385 "atmel,clk-output-range",
386 &range);
387
388 clk = at91_clk_register_sam9x5_peripheral(pmc, name,
389 parent_name,
390 id, &range);
391 }
392
393 if (IS_ERR(clk))
394 continue;
395
396 of_clk_add_provider(periphclknp, of_clk_src_simple_get, clk);
397 }
398}
399
400void __init of_at91rm9200_clk_periph_setup(struct device_node *np,
401 struct at91_pmc *pmc)
402{
403 of_at91_clk_periph_setup(np, pmc, PERIPHERAL_AT91RM9200);
404}
405
406void __init of_at91sam9x5_clk_periph_setup(struct device_node *np,
407 struct at91_pmc *pmc)
408{
409 of_at91_clk_periph_setup(np, pmc, PERIPHERAL_AT91SAM9X5);
410}
diff --git a/drivers/clk/at91/clk-pll.c b/drivers/clk/at91/clk-pll.c
new file mode 100644
index 000000000000..cf6ed023504c
--- /dev/null
+++ b/drivers/clk/at91/clk-pll.c
@@ -0,0 +1,531 @@
1/*
2 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 */
10
11#include <linux/clk-provider.h>
12#include <linux/clkdev.h>
13#include <linux/clk/at91_pmc.h>
14#include <linux/of.h>
15#include <linux/of_address.h>
16#include <linux/of_irq.h>
17#include <linux/io.h>
18#include <linux/wait.h>
19#include <linux/sched.h>
20#include <linux/interrupt.h>
21#include <linux/irq.h>
22
23#include "pmc.h"
24
25#define PLL_STATUS_MASK(id) (1 << (1 + (id)))
26#define PLL_REG(id) (AT91_CKGR_PLLAR + ((id) * 4))
27#define PLL_DIV_MASK 0xff
28#define PLL_DIV_MAX PLL_DIV_MASK
29#define PLL_DIV(reg) ((reg) & PLL_DIV_MASK)
30#define PLL_MUL(reg, layout) (((reg) >> (layout)->mul_shift) & \
31 (layout)->mul_mask)
32#define PLL_ICPR_SHIFT(id) ((id) * 16)
33#define PLL_ICPR_MASK(id) (0xffff << PLL_ICPR_SHIFT(id))
34#define PLL_MAX_COUNT 0x3ff
35#define PLL_COUNT_SHIFT 8
36#define PLL_OUT_SHIFT 14
37#define PLL_MAX_ID 1
38
39struct clk_pll_characteristics {
40 struct clk_range input;
41 int num_output;
42 struct clk_range *output;
43 u16 *icpll;
44 u8 *out;
45};
46
47struct clk_pll_layout {
48 u32 pllr_mask;
49 u16 mul_mask;
50 u8 mul_shift;
51};
52
53#define to_clk_pll(hw) container_of(hw, struct clk_pll, hw)
54
55struct clk_pll {
56 struct clk_hw hw;
57 struct at91_pmc *pmc;
58 unsigned int irq;
59 wait_queue_head_t wait;
60 u8 id;
61 u8 div;
62 u8 range;
63 u16 mul;
64 const struct clk_pll_layout *layout;
65 const struct clk_pll_characteristics *characteristics;
66};
67
68static irqreturn_t clk_pll_irq_handler(int irq, void *dev_id)
69{
70 struct clk_pll *pll = (struct clk_pll *)dev_id;
71
72 wake_up(&pll->wait);
73 disable_irq_nosync(pll->irq);
74
75 return IRQ_HANDLED;
76}
77
78static int clk_pll_prepare(struct clk_hw *hw)
79{
80 struct clk_pll *pll = to_clk_pll(hw);
81 struct at91_pmc *pmc = pll->pmc;
82 const struct clk_pll_layout *layout = pll->layout;
83 const struct clk_pll_characteristics *characteristics =
84 pll->characteristics;
85 u8 id = pll->id;
86 u32 mask = PLL_STATUS_MASK(id);
87 int offset = PLL_REG(id);
88 u8 out = 0;
89 u32 pllr, icpr;
90 u8 div;
91 u16 mul;
92
93 pllr = pmc_read(pmc, offset);
94 div = PLL_DIV(pllr);
95 mul = PLL_MUL(pllr, layout);
96
97 if ((pmc_read(pmc, AT91_PMC_SR) & mask) &&
98 (div == pll->div && mul == pll->mul))
99 return 0;
100
101 if (characteristics->out)
102 out = characteristics->out[pll->range];
103 if (characteristics->icpll) {
104 icpr = pmc_read(pmc, AT91_PMC_PLLICPR) & ~PLL_ICPR_MASK(id);
105 icpr |= (characteristics->icpll[pll->range] <<
106 PLL_ICPR_SHIFT(id));
107 pmc_write(pmc, AT91_PMC_PLLICPR, icpr);
108 }
109
110 pllr &= ~layout->pllr_mask;
111 pllr |= layout->pllr_mask &
112 (pll->div | (PLL_MAX_COUNT << PLL_COUNT_SHIFT) |
113 (out << PLL_OUT_SHIFT) |
114 ((pll->mul & layout->mul_mask) << layout->mul_shift));
115 pmc_write(pmc, offset, pllr);
116
117 while (!(pmc_read(pmc, AT91_PMC_SR) & mask)) {
118 enable_irq(pll->irq);
119 wait_event(pll->wait,
120 pmc_read(pmc, AT91_PMC_SR) & mask);
121 }
122
123 return 0;
124}
125
126static int clk_pll_is_prepared(struct clk_hw *hw)
127{
128 struct clk_pll *pll = to_clk_pll(hw);
129 struct at91_pmc *pmc = pll->pmc;
130
131 return !!(pmc_read(pmc, AT91_PMC_SR) &
132 PLL_STATUS_MASK(pll->id));
133}
134
135static void clk_pll_unprepare(struct clk_hw *hw)
136{
137 struct clk_pll *pll = to_clk_pll(hw);
138 struct at91_pmc *pmc = pll->pmc;
139 const struct clk_pll_layout *layout = pll->layout;
140 int offset = PLL_REG(pll->id);
141 u32 tmp = pmc_read(pmc, offset) & ~(layout->pllr_mask);
142
143 pmc_write(pmc, offset, tmp);
144}
145
146static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
147 unsigned long parent_rate)
148{
149 struct clk_pll *pll = to_clk_pll(hw);
150 const struct clk_pll_layout *layout = pll->layout;
151 struct at91_pmc *pmc = pll->pmc;
152 int offset = PLL_REG(pll->id);
153 u32 tmp = pmc_read(pmc, offset) & layout->pllr_mask;
154 u8 div = PLL_DIV(tmp);
155 u16 mul = PLL_MUL(tmp, layout);
156 if (!div || !mul)
157 return 0;
158
159 return (parent_rate * (mul + 1)) / div;
160}
161
162static long clk_pll_get_best_div_mul(struct clk_pll *pll, unsigned long rate,
163 unsigned long parent_rate,
164 u32 *div, u32 *mul,
165 u32 *index) {
166 unsigned long maxrate;
167 unsigned long minrate;
168 unsigned long divrate;
169 unsigned long bestdiv = 1;
170 unsigned long bestmul;
171 unsigned long tmpdiv;
172 unsigned long roundup;
173 unsigned long rounddown;
174 unsigned long remainder;
175 unsigned long bestremainder;
176 unsigned long maxmul;
177 unsigned long maxdiv;
178 unsigned long mindiv;
179 int i = 0;
180 const struct clk_pll_layout *layout = pll->layout;
181 const struct clk_pll_characteristics *characteristics =
182 pll->characteristics;
183
184 /* Minimum divider = 1 */
185 /* Maximum multiplier = max_mul */
186 maxmul = layout->mul_mask + 1;
187 maxrate = (parent_rate * maxmul) / 1;
188
189 /* Maximum divider = max_div */
190 /* Minimum multiplier = 2 */
191 maxdiv = PLL_DIV_MAX;
192 minrate = (parent_rate * 2) / maxdiv;
193
194 if (parent_rate < characteristics->input.min ||
195 parent_rate < characteristics->input.max)
196 return -ERANGE;
197
198 if (parent_rate < minrate || parent_rate > maxrate)
199 return -ERANGE;
200
201 for (i = 0; i < characteristics->num_output; i++) {
202 if (parent_rate >= characteristics->output[i].min &&
203 parent_rate <= characteristics->output[i].max)
204 break;
205 }
206
207 if (i >= characteristics->num_output)
208 return -ERANGE;
209
210 bestmul = rate / parent_rate;
211 rounddown = parent_rate % rate;
212 roundup = rate - rounddown;
213 bestremainder = roundup < rounddown ? roundup : rounddown;
214
215 if (!bestremainder) {
216 if (div)
217 *div = bestdiv;
218 if (mul)
219 *mul = bestmul;
220 if (index)
221 *index = i;
222 return rate;
223 }
224
225 maxdiv = 255 / (bestmul + 1);
226 if (parent_rate / maxdiv < characteristics->input.min)
227 maxdiv = parent_rate / characteristics->input.min;
228 mindiv = parent_rate / characteristics->input.max;
229 if (parent_rate % characteristics->input.max)
230 mindiv++;
231
232 for (tmpdiv = mindiv; tmpdiv < maxdiv; tmpdiv++) {
233 divrate = parent_rate / tmpdiv;
234
235 rounddown = rate % divrate;
236 roundup = divrate - rounddown;
237 remainder = roundup < rounddown ? roundup : rounddown;
238
239 if (remainder < bestremainder) {
240 bestremainder = remainder;
241 bestmul = rate / divrate;
242 bestdiv = tmpdiv;
243 }
244
245 if (!remainder)
246 break;
247 }
248
249 rate = (parent_rate / bestdiv) * bestmul;
250
251 if (div)
252 *div = bestdiv;
253 if (mul)
254 *mul = bestmul;
255 if (index)
256 *index = i;
257
258 return rate;
259}
260
261static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
262 unsigned long *parent_rate)
263{
264 struct clk_pll *pll = to_clk_pll(hw);
265
266 return clk_pll_get_best_div_mul(pll, rate, *parent_rate,
267 NULL, NULL, NULL);
268}
269
270static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
271 unsigned long parent_rate)
272{
273 struct clk_pll *pll = to_clk_pll(hw);
274 long ret;
275 u32 div;
276 u32 mul;
277 u32 index;
278
279 ret = clk_pll_get_best_div_mul(pll, rate, parent_rate,
280 &div, &mul, &index);
281 if (ret < 0)
282 return ret;
283
284 pll->range = index;
285 pll->div = div;
286 pll->mul = mul;
287
288 return 0;
289}
290
291static const struct clk_ops pll_ops = {
292 .prepare = clk_pll_prepare,
293 .unprepare = clk_pll_unprepare,
294 .is_prepared = clk_pll_is_prepared,
295 .recalc_rate = clk_pll_recalc_rate,
296 .round_rate = clk_pll_round_rate,
297 .set_rate = clk_pll_set_rate,
298};
299
300static struct clk * __init
301at91_clk_register_pll(struct at91_pmc *pmc, unsigned int irq, const char *name,
302 const char *parent_name, u8 id,
303 const struct clk_pll_layout *layout,
304 const struct clk_pll_characteristics *characteristics)
305{
306 struct clk_pll *pll;
307 struct clk *clk = NULL;
308 struct clk_init_data init;
309 int ret;
310 int offset = PLL_REG(id);
311 u32 tmp;
312
313 if (id > PLL_MAX_ID)
314 return ERR_PTR(-EINVAL);
315
316 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
317 if (!pll)
318 return ERR_PTR(-ENOMEM);
319
320 init.name = name;
321 init.ops = &pll_ops;
322 init.parent_names = &parent_name;
323 init.num_parents = 1;
324 init.flags = CLK_SET_RATE_GATE;
325
326 pll->id = id;
327 pll->hw.init = &init;
328 pll->layout = layout;
329 pll->characteristics = characteristics;
330 pll->pmc = pmc;
331 pll->irq = irq;
332 tmp = pmc_read(pmc, offset) & layout->pllr_mask;
333 pll->div = PLL_DIV(tmp);
334 pll->mul = PLL_MUL(tmp, layout);
335 init_waitqueue_head(&pll->wait);
336 irq_set_status_flags(pll->irq, IRQ_NOAUTOEN);
337 ret = request_irq(pll->irq, clk_pll_irq_handler, IRQF_TRIGGER_HIGH,
338 id ? "clk-pllb" : "clk-plla", pll);
339 if (ret)
340 return ERR_PTR(ret);
341
342 clk = clk_register(NULL, &pll->hw);
343 if (IS_ERR(clk))
344 kfree(pll);
345
346 return clk;
347}
348
349
350static const struct clk_pll_layout at91rm9200_pll_layout = {
351 .pllr_mask = 0x7FFFFFF,
352 .mul_shift = 16,
353 .mul_mask = 0x7FF,
354};
355
356static const struct clk_pll_layout at91sam9g45_pll_layout = {
357 .pllr_mask = 0xFFFFFF,
358 .mul_shift = 16,
359 .mul_mask = 0xFF,
360};
361
362static const struct clk_pll_layout at91sam9g20_pllb_layout = {
363 .pllr_mask = 0x3FFFFF,
364 .mul_shift = 16,
365 .mul_mask = 0x3F,
366};
367
368static const struct clk_pll_layout sama5d3_pll_layout = {
369 .pllr_mask = 0x1FFFFFF,
370 .mul_shift = 18,
371 .mul_mask = 0x7F,
372};
373
374
375static struct clk_pll_characteristics * __init
376of_at91_clk_pll_get_characteristics(struct device_node *np)
377{
378 int i;
379 int offset;
380 u32 tmp;
381 int num_output;
382 u32 num_cells;
383 struct clk_range input;
384 struct clk_range *output;
385 u8 *out = NULL;
386 u16 *icpll = NULL;
387 struct clk_pll_characteristics *characteristics;
388
389 if (of_at91_get_clk_range(np, "atmel,clk-input-range", &input))
390 return NULL;
391
392 if (of_property_read_u32(np, "#atmel,pll-clk-output-range-cells",
393 &num_cells))
394 return NULL;
395
396 if (num_cells < 2 || num_cells > 4)
397 return NULL;
398
399 if (!of_get_property(np, "atmel,pll-clk-output-ranges", &tmp))
400 return NULL;
401 num_output = tmp / (sizeof(u32) * num_cells);
402
403 characteristics = kzalloc(sizeof(*characteristics), GFP_KERNEL);
404 if (!characteristics)
405 return NULL;
406
407 output = kzalloc(sizeof(*output) * num_output, GFP_KERNEL);
408 if (!output)
409 goto out_free_characteristics;
410
411 if (num_cells > 2) {
412 out = kzalloc(sizeof(*out) * num_output, GFP_KERNEL);
413 if (!out)
414 goto out_free_output;
415 }
416
417 if (num_cells > 3) {
418 icpll = kzalloc(sizeof(*icpll) * num_output, GFP_KERNEL);
419 if (!icpll)
420 goto out_free_output;
421 }
422
423 for (i = 0; i < num_output; i++) {
424 offset = i * num_cells;
425 if (of_property_read_u32_index(np,
426 "atmel,pll-clk-output-ranges",
427 offset, &tmp))
428 goto out_free_output;
429 output[i].min = tmp;
430 if (of_property_read_u32_index(np,
431 "atmel,pll-clk-output-ranges",
432 offset + 1, &tmp))
433 goto out_free_output;
434 output[i].max = tmp;
435
436 if (num_cells == 2)
437 continue;
438
439 if (of_property_read_u32_index(np,
440 "atmel,pll-clk-output-ranges",
441 offset + 2, &tmp))
442 goto out_free_output;
443 out[i] = tmp;
444
445 if (num_cells == 3)
446 continue;
447
448 if (of_property_read_u32_index(np,
449 "atmel,pll-clk-output-ranges",
450 offset + 3, &tmp))
451 goto out_free_output;
452 icpll[i] = tmp;
453 }
454
455 characteristics->input = input;
456 characteristics->num_output = num_output;
457 characteristics->output = output;
458 characteristics->out = out;
459 characteristics->icpll = icpll;
460 return characteristics;
461
462out_free_output:
463 kfree(icpll);
464 kfree(out);
465 kfree(output);
466out_free_characteristics:
467 kfree(characteristics);
468 return NULL;
469}
470
471static void __init
472of_at91_clk_pll_setup(struct device_node *np, struct at91_pmc *pmc,
473 const struct clk_pll_layout *layout)
474{
475 u32 id;
476 unsigned int irq;
477 struct clk *clk;
478 const char *parent_name;
479 const char *name = np->name;
480 struct clk_pll_characteristics *characteristics;
481
482 if (of_property_read_u32(np, "reg", &id))
483 return;
484
485 parent_name = of_clk_get_parent_name(np, 0);
486
487 of_property_read_string(np, "clock-output-names", &name);
488
489 characteristics = of_at91_clk_pll_get_characteristics(np);
490 if (!characteristics)
491 return;
492
493 irq = irq_of_parse_and_map(np, 0);
494 if (!irq)
495 return;
496
497 clk = at91_clk_register_pll(pmc, irq, name, parent_name, id, layout,
498 characteristics);
499 if (IS_ERR(clk))
500 goto out_free_characteristics;
501
502 of_clk_add_provider(np, of_clk_src_simple_get, clk);
503 return;
504
505out_free_characteristics:
506 kfree(characteristics);
507}
508
509void __init of_at91rm9200_clk_pll_setup(struct device_node *np,
510 struct at91_pmc *pmc)
511{
512 of_at91_clk_pll_setup(np, pmc, &at91rm9200_pll_layout);
513}
514
515void __init of_at91sam9g45_clk_pll_setup(struct device_node *np,
516 struct at91_pmc *pmc)
517{
518 of_at91_clk_pll_setup(np, pmc, &at91sam9g45_pll_layout);
519}
520
521void __init of_at91sam9g20_clk_pllb_setup(struct device_node *np,
522 struct at91_pmc *pmc)
523{
524 of_at91_clk_pll_setup(np, pmc, &at91sam9g20_pllb_layout);
525}
526
527void __init of_sama5d3_clk_pll_setup(struct device_node *np,
528 struct at91_pmc *pmc)
529{
530 of_at91_clk_pll_setup(np, pmc, &sama5d3_pll_layout);
531}
diff --git a/drivers/clk/at91/clk-plldiv.c b/drivers/clk/at91/clk-plldiv.c
new file mode 100644
index 000000000000..ea226562bb40
--- /dev/null
+++ b/drivers/clk/at91/clk-plldiv.c
@@ -0,0 +1,135 @@
1/*
2 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 */
10
11#include <linux/clk-provider.h>
12#include <linux/clkdev.h>
13#include <linux/clk/at91_pmc.h>
14#include <linux/of.h>
15#include <linux/of_address.h>
16#include <linux/io.h>
17
18#include "pmc.h"
19
20#define to_clk_plldiv(hw) container_of(hw, struct clk_plldiv, hw)
21
22struct clk_plldiv {
23 struct clk_hw hw;
24 struct at91_pmc *pmc;
25};
26
27static unsigned long clk_plldiv_recalc_rate(struct clk_hw *hw,
28 unsigned long parent_rate)
29{
30 struct clk_plldiv *plldiv = to_clk_plldiv(hw);
31 struct at91_pmc *pmc = plldiv->pmc;
32
33 if (pmc_read(pmc, AT91_PMC_MCKR) & AT91_PMC_PLLADIV2)
34 return parent_rate / 2;
35
36 return parent_rate;
37}
38
39static long clk_plldiv_round_rate(struct clk_hw *hw, unsigned long rate,
40 unsigned long *parent_rate)
41{
42 unsigned long div;
43
44 if (rate > *parent_rate)
45 return *parent_rate;
46 div = *parent_rate / 2;
47 if (rate < div)
48 return div;
49
50 if (rate - div < *parent_rate - rate)
51 return div;
52
53 return *parent_rate;
54}
55
56static int clk_plldiv_set_rate(struct clk_hw *hw, unsigned long rate,
57 unsigned long parent_rate)
58{
59 struct clk_plldiv *plldiv = to_clk_plldiv(hw);
60 struct at91_pmc *pmc = plldiv->pmc;
61 u32 tmp;
62
63 if (parent_rate != rate && (parent_rate / 2) != rate)
64 return -EINVAL;
65
66 pmc_lock(pmc);
67 tmp = pmc_read(pmc, AT91_PMC_MCKR) & ~AT91_PMC_PLLADIV2;
68 if ((parent_rate / 2) == rate)
69 tmp |= AT91_PMC_PLLADIV2;
70 pmc_write(pmc, AT91_PMC_MCKR, tmp);
71 pmc_unlock(pmc);
72
73 return 0;
74}
75
76static const struct clk_ops plldiv_ops = {
77 .recalc_rate = clk_plldiv_recalc_rate,
78 .round_rate = clk_plldiv_round_rate,
79 .set_rate = clk_plldiv_set_rate,
80};
81
82static struct clk * __init
83at91_clk_register_plldiv(struct at91_pmc *pmc, const char *name,
84 const char *parent_name)
85{
86 struct clk_plldiv *plldiv;
87 struct clk *clk = NULL;
88 struct clk_init_data init;
89
90 plldiv = kzalloc(sizeof(*plldiv), GFP_KERNEL);
91 if (!plldiv)
92 return ERR_PTR(-ENOMEM);
93
94 init.name = name;
95 init.ops = &plldiv_ops;
96 init.parent_names = parent_name ? &parent_name : NULL;
97 init.num_parents = parent_name ? 1 : 0;
98 init.flags = CLK_SET_RATE_GATE;
99
100 plldiv->hw.init = &init;
101 plldiv->pmc = pmc;
102
103 clk = clk_register(NULL, &plldiv->hw);
104
105 if (IS_ERR(clk))
106 kfree(plldiv);
107
108 return clk;
109}
110
111static void __init
112of_at91_clk_plldiv_setup(struct device_node *np, struct at91_pmc *pmc)
113{
114 struct clk *clk;
115 const char *parent_name;
116 const char *name = np->name;
117
118 parent_name = of_clk_get_parent_name(np, 0);
119
120 of_property_read_string(np, "clock-output-names", &name);
121
122 clk = at91_clk_register_plldiv(pmc, name, parent_name);
123
124 if (IS_ERR(clk))
125 return;
126
127 of_clk_add_provider(np, of_clk_src_simple_get, clk);
128 return;
129}
130
131void __init of_at91sam9x5_clk_plldiv_setup(struct device_node *np,
132 struct at91_pmc *pmc)
133{
134 of_at91_clk_plldiv_setup(np, pmc);
135}
diff --git a/drivers/clk/at91/clk-programmable.c b/drivers/clk/at91/clk-programmable.c
new file mode 100644
index 000000000000..fd792b203eaf
--- /dev/null
+++ b/drivers/clk/at91/clk-programmable.c
@@ -0,0 +1,366 @@
1/*
2 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 */
10
11#include <linux/clk-provider.h>
12#include <linux/clkdev.h>
13#include <linux/clk/at91_pmc.h>
14#include <linux/of.h>
15#include <linux/of_address.h>
16#include <linux/of_irq.h>
17#include <linux/io.h>
18#include <linux/wait.h>
19#include <linux/sched.h>
20#include <linux/interrupt.h>
21#include <linux/irq.h>
22
23#include "pmc.h"
24
25#define PROG_SOURCE_MAX 5
26#define PROG_ID_MAX 7
27
28#define PROG_STATUS_MASK(id) (1 << ((id) + 8))
29#define PROG_PRES_MASK 0x7
30#define PROG_MAX_RM9200_CSS 3
31
32struct clk_programmable_layout {
33 u8 pres_shift;
34 u8 css_mask;
35 u8 have_slck_mck;
36};
37
38struct clk_programmable {
39 struct clk_hw hw;
40 struct at91_pmc *pmc;
41 unsigned int irq;
42 wait_queue_head_t wait;
43 u8 id;
44 u8 css;
45 u8 pres;
46 u8 slckmck;
47 const struct clk_programmable_layout *layout;
48};
49
50#define to_clk_programmable(hw) container_of(hw, struct clk_programmable, hw)
51
52
53static irqreturn_t clk_programmable_irq_handler(int irq, void *dev_id)
54{
55 struct clk_programmable *prog = (struct clk_programmable *)dev_id;
56
57 wake_up(&prog->wait);
58
59 return IRQ_HANDLED;
60}
61
62static int clk_programmable_prepare(struct clk_hw *hw)
63{
64 u32 tmp;
65 struct clk_programmable *prog = to_clk_programmable(hw);
66 struct at91_pmc *pmc = prog->pmc;
67 const struct clk_programmable_layout *layout = prog->layout;
68 u8 id = prog->id;
69 u32 mask = PROG_STATUS_MASK(id);
70
71 tmp = prog->css | (prog->pres << layout->pres_shift);
72 if (layout->have_slck_mck && prog->slckmck)
73 tmp |= AT91_PMC_CSSMCK_MCK;
74
75 pmc_write(pmc, AT91_PMC_PCKR(id), tmp);
76
77 while (!(pmc_read(pmc, AT91_PMC_SR) & mask))
78 wait_event(prog->wait, pmc_read(pmc, AT91_PMC_SR) & mask);
79
80 return 0;
81}
82
83static int clk_programmable_is_ready(struct clk_hw *hw)
84{
85 struct clk_programmable *prog = to_clk_programmable(hw);
86 struct at91_pmc *pmc = prog->pmc;
87
88 return !!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_PCKR(prog->id));
89}
90
91static unsigned long clk_programmable_recalc_rate(struct clk_hw *hw,
92 unsigned long parent_rate)
93{
94 u32 tmp;
95 struct clk_programmable *prog = to_clk_programmable(hw);
96 struct at91_pmc *pmc = prog->pmc;
97 const struct clk_programmable_layout *layout = prog->layout;
98
99 tmp = pmc_read(pmc, AT91_PMC_PCKR(prog->id));
100 prog->pres = (tmp >> layout->pres_shift) & PROG_PRES_MASK;
101
102 return parent_rate >> prog->pres;
103}
104
105static long clk_programmable_round_rate(struct clk_hw *hw, unsigned long rate,
106 unsigned long *parent_rate)
107{
108 unsigned long best_rate = *parent_rate;
109 unsigned long best_diff;
110 unsigned long new_diff;
111 unsigned long cur_rate;
112 int shift = shift;
113
114 if (rate > *parent_rate)
115 return *parent_rate;
116 else
117 best_diff = *parent_rate - rate;
118
119 if (!best_diff)
120 return best_rate;
121
122 for (shift = 1; shift < PROG_PRES_MASK; shift++) {
123 cur_rate = *parent_rate >> shift;
124
125 if (cur_rate > rate)
126 new_diff = cur_rate - rate;
127 else
128 new_diff = rate - cur_rate;
129
130 if (!new_diff)
131 return cur_rate;
132
133 if (new_diff < best_diff) {
134 best_diff = new_diff;
135 best_rate = cur_rate;
136 }
137
138 if (rate > cur_rate)
139 break;
140 }
141
142 return best_rate;
143}
144
145static int clk_programmable_set_parent(struct clk_hw *hw, u8 index)
146{
147 struct clk_programmable *prog = to_clk_programmable(hw);
148 const struct clk_programmable_layout *layout = prog->layout;
149 if (index > layout->css_mask) {
150 if (index > PROG_MAX_RM9200_CSS && layout->have_slck_mck) {
151 prog->css = 0;
152 prog->slckmck = 1;
153 return 0;
154 } else {
155 return -EINVAL;
156 }
157 }
158
159 prog->css = index;
160 return 0;
161}
162
163static u8 clk_programmable_get_parent(struct clk_hw *hw)
164{
165 u32 tmp;
166 u8 ret;
167 struct clk_programmable *prog = to_clk_programmable(hw);
168 struct at91_pmc *pmc = prog->pmc;
169 const struct clk_programmable_layout *layout = prog->layout;
170
171 tmp = pmc_read(pmc, AT91_PMC_PCKR(prog->id));
172 prog->css = tmp & layout->css_mask;
173 ret = prog->css;
174 if (layout->have_slck_mck) {
175 prog->slckmck = !!(tmp & AT91_PMC_CSSMCK_MCK);
176 if (prog->slckmck && !ret)
177 ret = PROG_MAX_RM9200_CSS + 1;
178 }
179
180 return ret;
181}
182
183static int clk_programmable_set_rate(struct clk_hw *hw, unsigned long rate,
184 unsigned long parent_rate)
185{
186 struct clk_programmable *prog = to_clk_programmable(hw);
187 unsigned long best_rate = parent_rate;
188 unsigned long best_diff;
189 unsigned long new_diff;
190 unsigned long cur_rate;
191 int shift = 0;
192
193 if (rate > parent_rate)
194 return parent_rate;
195 else
196 best_diff = parent_rate - rate;
197
198 if (!best_diff) {
199 prog->pres = shift;
200 return 0;
201 }
202
203 for (shift = 1; shift < PROG_PRES_MASK; shift++) {
204 cur_rate = parent_rate >> shift;
205
206 if (cur_rate > rate)
207 new_diff = cur_rate - rate;
208 else
209 new_diff = rate - cur_rate;
210
211 if (!new_diff)
212 break;
213
214 if (new_diff < best_diff) {
215 best_diff = new_diff;
216 best_rate = cur_rate;
217 }
218
219 if (rate > cur_rate)
220 break;
221 }
222
223 prog->pres = shift;
224 return 0;
225}
226
227static const struct clk_ops programmable_ops = {
228 .prepare = clk_programmable_prepare,
229 .is_prepared = clk_programmable_is_ready,
230 .recalc_rate = clk_programmable_recalc_rate,
231 .round_rate = clk_programmable_round_rate,
232 .get_parent = clk_programmable_get_parent,
233 .set_parent = clk_programmable_set_parent,
234 .set_rate = clk_programmable_set_rate,
235};
236
237static struct clk * __init
238at91_clk_register_programmable(struct at91_pmc *pmc, unsigned int irq,
239 const char *name, const char **parent_names,
240 u8 num_parents, u8 id,
241 const struct clk_programmable_layout *layout)
242{
243 int ret;
244 struct clk_programmable *prog;
245 struct clk *clk = NULL;
246 struct clk_init_data init;
247 char irq_name[11];
248
249 if (id > PROG_ID_MAX)
250 return ERR_PTR(-EINVAL);
251
252 prog = kzalloc(sizeof(*prog), GFP_KERNEL);
253 if (!prog)
254 return ERR_PTR(-ENOMEM);
255
256 init.name = name;
257 init.ops = &programmable_ops;
258 init.parent_names = parent_names;
259 init.num_parents = num_parents;
260 init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
261
262 prog->id = id;
263 prog->layout = layout;
264 prog->hw.init = &init;
265 prog->pmc = pmc;
266 prog->irq = irq;
267 init_waitqueue_head(&prog->wait);
268 irq_set_status_flags(prog->irq, IRQ_NOAUTOEN);
269 snprintf(irq_name, sizeof(irq_name), "clk-prog%d", id);
270 ret = request_irq(prog->irq, clk_programmable_irq_handler,
271 IRQF_TRIGGER_HIGH, irq_name, prog);
272 if (ret)
273 return ERR_PTR(ret);
274
275 clk = clk_register(NULL, &prog->hw);
276 if (IS_ERR(clk))
277 kfree(prog);
278
279 return clk;
280}
281
282static const struct clk_programmable_layout at91rm9200_programmable_layout = {
283 .pres_shift = 2,
284 .css_mask = 0x3,
285 .have_slck_mck = 0,
286};
287
288static const struct clk_programmable_layout at91sam9g45_programmable_layout = {
289 .pres_shift = 2,
290 .css_mask = 0x3,
291 .have_slck_mck = 1,
292};
293
294static const struct clk_programmable_layout at91sam9x5_programmable_layout = {
295 .pres_shift = 4,
296 .css_mask = 0x7,
297 .have_slck_mck = 0,
298};
299
300static void __init
301of_at91_clk_prog_setup(struct device_node *np, struct at91_pmc *pmc,
302 const struct clk_programmable_layout *layout)
303{
304 int num;
305 u32 id;
306 int i;
307 unsigned int irq;
308 struct clk *clk;
309 int num_parents;
310 const char *parent_names[PROG_SOURCE_MAX];
311 const char *name;
312 struct device_node *progclknp;
313
314 num_parents = of_count_phandle_with_args(np, "clocks", "#clock-cells");
315 if (num_parents <= 0 || num_parents > PROG_SOURCE_MAX)
316 return;
317
318 for (i = 0; i < num_parents; ++i) {
319 parent_names[i] = of_clk_get_parent_name(np, i);
320 if (!parent_names[i])
321 return;
322 }
323
324 num = of_get_child_count(np);
325 if (!num || num > (PROG_ID_MAX + 1))
326 return;
327
328 for_each_child_of_node(np, progclknp) {
329 if (of_property_read_u32(progclknp, "reg", &id))
330 continue;
331
332 if (of_property_read_string(np, "clock-output-names", &name))
333 name = progclknp->name;
334
335 irq = irq_of_parse_and_map(progclknp, 0);
336 if (!irq)
337 continue;
338
339 clk = at91_clk_register_programmable(pmc, irq, name,
340 parent_names, num_parents,
341 id, layout);
342 if (IS_ERR(clk))
343 continue;
344
345 of_clk_add_provider(progclknp, of_clk_src_simple_get, clk);
346 }
347}
348
349
350void __init of_at91rm9200_clk_prog_setup(struct device_node *np,
351 struct at91_pmc *pmc)
352{
353 of_at91_clk_prog_setup(np, pmc, &at91rm9200_programmable_layout);
354}
355
356void __init of_at91sam9g45_clk_prog_setup(struct device_node *np,
357 struct at91_pmc *pmc)
358{
359 of_at91_clk_prog_setup(np, pmc, &at91sam9g45_programmable_layout);
360}
361
362void __init of_at91sam9x5_clk_prog_setup(struct device_node *np,
363 struct at91_pmc *pmc)
364{
365 of_at91_clk_prog_setup(np, pmc, &at91sam9x5_programmable_layout);
366}
diff --git a/drivers/clk/at91/clk-smd.c b/drivers/clk/at91/clk-smd.c
new file mode 100644
index 000000000000..144d47ecfe63
--- /dev/null
+++ b/drivers/clk/at91/clk-smd.c
@@ -0,0 +1,171 @@
1/*
2 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 */
10
11#include <linux/clk-provider.h>
12#include <linux/clkdev.h>
13#include <linux/clk/at91_pmc.h>
14#include <linux/of.h>
15#include <linux/of_address.h>
16#include <linux/io.h>
17
18#include "pmc.h"
19
20#define SMD_SOURCE_MAX 2
21
22#define SMD_DIV_SHIFT 8
23#define SMD_MAX_DIV 0xf
24
25struct at91sam9x5_clk_smd {
26 struct clk_hw hw;
27 struct at91_pmc *pmc;
28};
29
30#define to_at91sam9x5_clk_smd(hw) \
31 container_of(hw, struct at91sam9x5_clk_smd, hw)
32
33static unsigned long at91sam9x5_clk_smd_recalc_rate(struct clk_hw *hw,
34 unsigned long parent_rate)
35{
36 u32 tmp;
37 u8 smddiv;
38 struct at91sam9x5_clk_smd *smd = to_at91sam9x5_clk_smd(hw);
39 struct at91_pmc *pmc = smd->pmc;
40
41 tmp = pmc_read(pmc, AT91_PMC_SMD);
42 smddiv = (tmp & AT91_PMC_SMD_DIV) >> SMD_DIV_SHIFT;
43 return parent_rate / (smddiv + 1);
44}
45
46static long at91sam9x5_clk_smd_round_rate(struct clk_hw *hw, unsigned long rate,
47 unsigned long *parent_rate)
48{
49 unsigned long div;
50 unsigned long bestrate;
51 unsigned long tmp;
52
53 if (rate >= *parent_rate)
54 return *parent_rate;
55
56 div = *parent_rate / rate;
57 if (div > SMD_MAX_DIV)
58 return *parent_rate / (SMD_MAX_DIV + 1);
59
60 bestrate = *parent_rate / div;
61 tmp = *parent_rate / (div + 1);
62 if (bestrate - rate > rate - tmp)
63 bestrate = tmp;
64
65 return bestrate;
66}
67
68static int at91sam9x5_clk_smd_set_parent(struct clk_hw *hw, u8 index)
69{
70 u32 tmp;
71 struct at91sam9x5_clk_smd *smd = to_at91sam9x5_clk_smd(hw);
72 struct at91_pmc *pmc = smd->pmc;
73
74 if (index > 1)
75 return -EINVAL;
76 tmp = pmc_read(pmc, AT91_PMC_SMD) & ~AT91_PMC_SMDS;
77 if (index)
78 tmp |= AT91_PMC_SMDS;
79 pmc_write(pmc, AT91_PMC_SMD, tmp);
80 return 0;
81}
82
83static u8 at91sam9x5_clk_smd_get_parent(struct clk_hw *hw)
84{
85 struct at91sam9x5_clk_smd *smd = to_at91sam9x5_clk_smd(hw);
86 struct at91_pmc *pmc = smd->pmc;
87
88 return pmc_read(pmc, AT91_PMC_SMD) & AT91_PMC_SMDS;
89}
90
91static int at91sam9x5_clk_smd_set_rate(struct clk_hw *hw, unsigned long rate,
92 unsigned long parent_rate)
93{
94 u32 tmp;
95 struct at91sam9x5_clk_smd *smd = to_at91sam9x5_clk_smd(hw);
96 struct at91_pmc *pmc = smd->pmc;
97 unsigned long div = parent_rate / rate;
98
99 if (parent_rate % rate || div < 1 || div > (SMD_MAX_DIV + 1))
100 return -EINVAL;
101 tmp = pmc_read(pmc, AT91_PMC_SMD) & ~AT91_PMC_SMD_DIV;
102 tmp |= (div - 1) << SMD_DIV_SHIFT;
103 pmc_write(pmc, AT91_PMC_SMD, tmp);
104
105 return 0;
106}
107
108static const struct clk_ops at91sam9x5_smd_ops = {
109 .recalc_rate = at91sam9x5_clk_smd_recalc_rate,
110 .round_rate = at91sam9x5_clk_smd_round_rate,
111 .get_parent = at91sam9x5_clk_smd_get_parent,
112 .set_parent = at91sam9x5_clk_smd_set_parent,
113 .set_rate = at91sam9x5_clk_smd_set_rate,
114};
115
116static struct clk * __init
117at91sam9x5_clk_register_smd(struct at91_pmc *pmc, const char *name,
118 const char **parent_names, u8 num_parents)
119{
120 struct at91sam9x5_clk_smd *smd;
121 struct clk *clk = NULL;
122 struct clk_init_data init;
123
124 smd = kzalloc(sizeof(*smd), GFP_KERNEL);
125 if (!smd)
126 return ERR_PTR(-ENOMEM);
127
128 init.name = name;
129 init.ops = &at91sam9x5_smd_ops;
130 init.parent_names = parent_names;
131 init.num_parents = num_parents;
132 init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
133
134 smd->hw.init = &init;
135 smd->pmc = pmc;
136
137 clk = clk_register(NULL, &smd->hw);
138 if (IS_ERR(clk))
139 kfree(smd);
140
141 return clk;
142}
143
144void __init of_at91sam9x5_clk_smd_setup(struct device_node *np,
145 struct at91_pmc *pmc)
146{
147 struct clk *clk;
148 int i;
149 int num_parents;
150 const char *parent_names[SMD_SOURCE_MAX];
151 const char *name = np->name;
152
153 num_parents = of_count_phandle_with_args(np, "clocks", "#clock-cells");
154 if (num_parents <= 0 || num_parents > SMD_SOURCE_MAX)
155 return;
156
157 for (i = 0; i < num_parents; i++) {
158 parent_names[i] = of_clk_get_parent_name(np, i);
159 if (!parent_names[i])
160 return;
161 }
162
163 of_property_read_string(np, "clock-output-names", &name);
164
165 clk = at91sam9x5_clk_register_smd(pmc, name, parent_names,
166 num_parents);
167 if (IS_ERR(clk))
168 return;
169
170 of_clk_add_provider(np, of_clk_src_simple_get, clk);
171}
diff --git a/drivers/clk/at91/clk-system.c b/drivers/clk/at91/clk-system.c
new file mode 100644
index 000000000000..8f7c0434a09f
--- /dev/null
+++ b/drivers/clk/at91/clk-system.c
@@ -0,0 +1,135 @@
1/*
2 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 */
10
11#include <linux/clk-provider.h>
12#include <linux/clkdev.h>
13#include <linux/clk/at91_pmc.h>
14#include <linux/of.h>
15#include <linux/of_address.h>
16#include <linux/io.h>
17
18#include "pmc.h"
19
20#define SYSTEM_MAX_ID 31
21
22#define SYSTEM_MAX_NAME_SZ 32
23
24#define to_clk_system(hw) container_of(hw, struct clk_system, hw)
25struct clk_system {
26 struct clk_hw hw;
27 struct at91_pmc *pmc;
28 u8 id;
29};
30
31static int clk_system_enable(struct clk_hw *hw)
32{
33 struct clk_system *sys = to_clk_system(hw);
34 struct at91_pmc *pmc = sys->pmc;
35
36 pmc_write(pmc, AT91_PMC_SCER, 1 << sys->id);
37 return 0;
38}
39
40static void clk_system_disable(struct clk_hw *hw)
41{
42 struct clk_system *sys = to_clk_system(hw);
43 struct at91_pmc *pmc = sys->pmc;
44
45 pmc_write(pmc, AT91_PMC_SCDR, 1 << sys->id);
46}
47
48static int clk_system_is_enabled(struct clk_hw *hw)
49{
50 struct clk_system *sys = to_clk_system(hw);
51 struct at91_pmc *pmc = sys->pmc;
52
53 return !!(pmc_read(pmc, AT91_PMC_SCSR) & (1 << sys->id));
54}
55
56static const struct clk_ops system_ops = {
57 .enable = clk_system_enable,
58 .disable = clk_system_disable,
59 .is_enabled = clk_system_is_enabled,
60};
61
62static struct clk * __init
63at91_clk_register_system(struct at91_pmc *pmc, const char *name,
64 const char *parent_name, u8 id)
65{
66 struct clk_system *sys;
67 struct clk *clk = NULL;
68 struct clk_init_data init;
69
70 if (!parent_name || id > SYSTEM_MAX_ID)
71 return ERR_PTR(-EINVAL);
72
73 sys = kzalloc(sizeof(*sys), GFP_KERNEL);
74 if (!sys)
75 return ERR_PTR(-ENOMEM);
76
77 init.name = name;
78 init.ops = &system_ops;
79 init.parent_names = &parent_name;
80 init.num_parents = 1;
81 /*
82 * CLK_IGNORE_UNUSED is used to avoid ddrck switch off.
83 * TODO : we should implement a driver supporting at91 ddr controller
84 * (see drivers/memory) which would request and enable the ddrck clock.
85 * When this is done we will be able to remove CLK_IGNORE_UNUSED flag.
86 */
87 init.flags = CLK_IGNORE_UNUSED;
88
89 sys->id = id;
90 sys->hw.init = &init;
91 sys->pmc = pmc;
92
93 clk = clk_register(NULL, &sys->hw);
94 if (IS_ERR(clk))
95 kfree(sys);
96
97 return clk;
98}
99
100static void __init
101of_at91_clk_sys_setup(struct device_node *np, struct at91_pmc *pmc)
102{
103 int num;
104 u32 id;
105 struct clk *clk;
106 const char *name;
107 struct device_node *sysclknp;
108 const char *parent_name;
109
110 num = of_get_child_count(np);
111 if (num > (SYSTEM_MAX_ID + 1))
112 return;
113
114 for_each_child_of_node(np, sysclknp) {
115 if (of_property_read_u32(sysclknp, "reg", &id))
116 continue;
117
118 if (of_property_read_string(np, "clock-output-names", &name))
119 name = sysclknp->name;
120
121 parent_name = of_clk_get_parent_name(sysclknp, 0);
122
123 clk = at91_clk_register_system(pmc, name, parent_name, id);
124 if (IS_ERR(clk))
125 continue;
126
127 of_clk_add_provider(sysclknp, of_clk_src_simple_get, clk);
128 }
129}
130
131void __init of_at91rm9200_clk_sys_setup(struct device_node *np,
132 struct at91_pmc *pmc)
133{
134 of_at91_clk_sys_setup(np, pmc);
135}
diff --git a/drivers/clk/at91/clk-usb.c b/drivers/clk/at91/clk-usb.c
new file mode 100644
index 000000000000..7d1d26a4bd04
--- /dev/null
+++ b/drivers/clk/at91/clk-usb.c
@@ -0,0 +1,398 @@
1/*
2 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 */
10
11#include <linux/clk-provider.h>
12#include <linux/clkdev.h>
13#include <linux/clk/at91_pmc.h>
14#include <linux/of.h>
15#include <linux/of_address.h>
16#include <linux/io.h>
17
18#include "pmc.h"
19
20#define USB_SOURCE_MAX 2
21
22#define SAM9X5_USB_DIV_SHIFT 8
23#define SAM9X5_USB_MAX_DIV 0xf
24
25#define RM9200_USB_DIV_SHIFT 28
26#define RM9200_USB_DIV_TAB_SIZE 4
27
28struct at91sam9x5_clk_usb {
29 struct clk_hw hw;
30 struct at91_pmc *pmc;
31};
32
33#define to_at91sam9x5_clk_usb(hw) \
34 container_of(hw, struct at91sam9x5_clk_usb, hw)
35
36struct at91rm9200_clk_usb {
37 struct clk_hw hw;
38 struct at91_pmc *pmc;
39 u32 divisors[4];
40};
41
42#define to_at91rm9200_clk_usb(hw) \
43 container_of(hw, struct at91rm9200_clk_usb, hw)
44
45static unsigned long at91sam9x5_clk_usb_recalc_rate(struct clk_hw *hw,
46 unsigned long parent_rate)
47{
48 u32 tmp;
49 u8 usbdiv;
50 struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw);
51 struct at91_pmc *pmc = usb->pmc;
52
53 tmp = pmc_read(pmc, AT91_PMC_USB);
54 usbdiv = (tmp & AT91_PMC_OHCIUSBDIV) >> SAM9X5_USB_DIV_SHIFT;
55 return parent_rate / (usbdiv + 1);
56}
57
58static long at91sam9x5_clk_usb_round_rate(struct clk_hw *hw, unsigned long rate,
59 unsigned long *parent_rate)
60{
61 unsigned long div;
62 unsigned long bestrate;
63 unsigned long tmp;
64
65 if (rate >= *parent_rate)
66 return *parent_rate;
67
68 div = *parent_rate / rate;
69 if (div >= SAM9X5_USB_MAX_DIV)
70 return *parent_rate / (SAM9X5_USB_MAX_DIV + 1);
71
72 bestrate = *parent_rate / div;
73 tmp = *parent_rate / (div + 1);
74 if (bestrate - rate > rate - tmp)
75 bestrate = tmp;
76
77 return bestrate;
78}
79
80static int at91sam9x5_clk_usb_set_parent(struct clk_hw *hw, u8 index)
81{
82 u32 tmp;
83 struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw);
84 struct at91_pmc *pmc = usb->pmc;
85
86 if (index > 1)
87 return -EINVAL;
88 tmp = pmc_read(pmc, AT91_PMC_USB) & ~AT91_PMC_USBS;
89 if (index)
90 tmp |= AT91_PMC_USBS;
91 pmc_write(pmc, AT91_PMC_USB, tmp);
92 return 0;
93}
94
95static u8 at91sam9x5_clk_usb_get_parent(struct clk_hw *hw)
96{
97 struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw);
98 struct at91_pmc *pmc = usb->pmc;
99
100 return pmc_read(pmc, AT91_PMC_USB) & AT91_PMC_USBS;
101}
102
103static int at91sam9x5_clk_usb_set_rate(struct clk_hw *hw, unsigned long rate,
104 unsigned long parent_rate)
105{
106 u32 tmp;
107 struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw);
108 struct at91_pmc *pmc = usb->pmc;
109 unsigned long div = parent_rate / rate;
110
111 if (parent_rate % rate || div < 1 || div >= SAM9X5_USB_MAX_DIV)
112 return -EINVAL;
113
114 tmp = pmc_read(pmc, AT91_PMC_USB) & ~AT91_PMC_OHCIUSBDIV;
115 tmp |= (div - 1) << SAM9X5_USB_DIV_SHIFT;
116 pmc_write(pmc, AT91_PMC_USB, tmp);
117
118 return 0;
119}
120
121static const struct clk_ops at91sam9x5_usb_ops = {
122 .recalc_rate = at91sam9x5_clk_usb_recalc_rate,
123 .round_rate = at91sam9x5_clk_usb_round_rate,
124 .get_parent = at91sam9x5_clk_usb_get_parent,
125 .set_parent = at91sam9x5_clk_usb_set_parent,
126 .set_rate = at91sam9x5_clk_usb_set_rate,
127};
128
129static int at91sam9n12_clk_usb_enable(struct clk_hw *hw)
130{
131 struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw);
132 struct at91_pmc *pmc = usb->pmc;
133
134 pmc_write(pmc, AT91_PMC_USB,
135 pmc_read(pmc, AT91_PMC_USB) | AT91_PMC_USBS);
136 return 0;
137}
138
139static void at91sam9n12_clk_usb_disable(struct clk_hw *hw)
140{
141 struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw);
142 struct at91_pmc *pmc = usb->pmc;
143
144 pmc_write(pmc, AT91_PMC_USB,
145 pmc_read(pmc, AT91_PMC_USB) & ~AT91_PMC_USBS);
146}
147
148static int at91sam9n12_clk_usb_is_enabled(struct clk_hw *hw)
149{
150 struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw);
151 struct at91_pmc *pmc = usb->pmc;
152
153 return !!(pmc_read(pmc, AT91_PMC_USB) & AT91_PMC_USBS);
154}
155
156static const struct clk_ops at91sam9n12_usb_ops = {
157 .enable = at91sam9n12_clk_usb_enable,
158 .disable = at91sam9n12_clk_usb_disable,
159 .is_enabled = at91sam9n12_clk_usb_is_enabled,
160 .recalc_rate = at91sam9x5_clk_usb_recalc_rate,
161 .round_rate = at91sam9x5_clk_usb_round_rate,
162 .set_rate = at91sam9x5_clk_usb_set_rate,
163};
164
165static struct clk * __init
166at91sam9x5_clk_register_usb(struct at91_pmc *pmc, const char *name,
167 const char **parent_names, u8 num_parents)
168{
169 struct at91sam9x5_clk_usb *usb;
170 struct clk *clk = NULL;
171 struct clk_init_data init;
172
173 usb = kzalloc(sizeof(*usb), GFP_KERNEL);
174 if (!usb)
175 return ERR_PTR(-ENOMEM);
176
177 init.name = name;
178 init.ops = &at91sam9x5_usb_ops;
179 init.parent_names = parent_names;
180 init.num_parents = num_parents;
181 init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
182
183 usb->hw.init = &init;
184 usb->pmc = pmc;
185
186 clk = clk_register(NULL, &usb->hw);
187 if (IS_ERR(clk))
188 kfree(usb);
189
190 return clk;
191}
192
193static struct clk * __init
194at91sam9n12_clk_register_usb(struct at91_pmc *pmc, const char *name,
195 const char *parent_name)
196{
197 struct at91sam9x5_clk_usb *usb;
198 struct clk *clk = NULL;
199 struct clk_init_data init;
200
201 usb = kzalloc(sizeof(*usb), GFP_KERNEL);
202 if (!usb)
203 return ERR_PTR(-ENOMEM);
204
205 init.name = name;
206 init.ops = &at91sam9n12_usb_ops;
207 init.parent_names = &parent_name;
208 init.num_parents = 1;
209 init.flags = CLK_SET_RATE_GATE;
210
211 usb->hw.init = &init;
212 usb->pmc = pmc;
213
214 clk = clk_register(NULL, &usb->hw);
215 if (IS_ERR(clk))
216 kfree(usb);
217
218 return clk;
219}
220
221static unsigned long at91rm9200_clk_usb_recalc_rate(struct clk_hw *hw,
222 unsigned long parent_rate)
223{
224 struct at91rm9200_clk_usb *usb = to_at91rm9200_clk_usb(hw);
225 struct at91_pmc *pmc = usb->pmc;
226 u32 tmp;
227 u8 usbdiv;
228
229 tmp = pmc_read(pmc, AT91_CKGR_PLLBR);
230 usbdiv = (tmp & AT91_PMC_USBDIV) >> RM9200_USB_DIV_SHIFT;
231 if (usb->divisors[usbdiv])
232 return parent_rate / usb->divisors[usbdiv];
233
234 return 0;
235}
236
237static long at91rm9200_clk_usb_round_rate(struct clk_hw *hw, unsigned long rate,
238 unsigned long *parent_rate)
239{
240 struct at91rm9200_clk_usb *usb = to_at91rm9200_clk_usb(hw);
241 unsigned long bestrate = 0;
242 int bestdiff = -1;
243 unsigned long tmprate;
244 int tmpdiff;
245 int i = 0;
246
247 for (i = 0; i < 4; i++) {
248 if (!usb->divisors[i])
249 continue;
250 tmprate = *parent_rate / usb->divisors[i];
251 if (tmprate < rate)
252 tmpdiff = rate - tmprate;
253 else
254 tmpdiff = tmprate - rate;
255
256 if (bestdiff < 0 || bestdiff > tmpdiff) {
257 bestrate = tmprate;
258 bestdiff = tmpdiff;
259 }
260
261 if (!bestdiff)
262 break;
263 }
264
265 return bestrate;
266}
267
268static int at91rm9200_clk_usb_set_rate(struct clk_hw *hw, unsigned long rate,
269 unsigned long parent_rate)
270{
271 u32 tmp;
272 int i;
273 struct at91rm9200_clk_usb *usb = to_at91rm9200_clk_usb(hw);
274 struct at91_pmc *pmc = usb->pmc;
275 unsigned long div = parent_rate / rate;
276
277 if (parent_rate % rate)
278 return -EINVAL;
279 for (i = 0; i < RM9200_USB_DIV_TAB_SIZE; i++) {
280 if (usb->divisors[i] == div) {
281 tmp = pmc_read(pmc, AT91_CKGR_PLLBR) &
282 ~AT91_PMC_USBDIV;
283 tmp |= i << RM9200_USB_DIV_SHIFT;
284 pmc_write(pmc, AT91_CKGR_PLLBR, tmp);
285 return 0;
286 }
287 }
288
289 return -EINVAL;
290}
291
292static const struct clk_ops at91rm9200_usb_ops = {
293 .recalc_rate = at91rm9200_clk_usb_recalc_rate,
294 .round_rate = at91rm9200_clk_usb_round_rate,
295 .set_rate = at91rm9200_clk_usb_set_rate,
296};
297
298static struct clk * __init
299at91rm9200_clk_register_usb(struct at91_pmc *pmc, const char *name,
300 const char *parent_name, const u32 *divisors)
301{
302 struct at91rm9200_clk_usb *usb;
303 struct clk *clk = NULL;
304 struct clk_init_data init;
305
306 usb = kzalloc(sizeof(*usb), GFP_KERNEL);
307 if (!usb)
308 return ERR_PTR(-ENOMEM);
309
310 init.name = name;
311 init.ops = &at91rm9200_usb_ops;
312 init.parent_names = &parent_name;
313 init.num_parents = 1;
314 init.flags = 0;
315
316 usb->hw.init = &init;
317 usb->pmc = pmc;
318 memcpy(usb->divisors, divisors, sizeof(usb->divisors));
319
320 clk = clk_register(NULL, &usb->hw);
321 if (IS_ERR(clk))
322 kfree(usb);
323
324 return clk;
325}
326
327void __init of_at91sam9x5_clk_usb_setup(struct device_node *np,
328 struct at91_pmc *pmc)
329{
330 struct clk *clk;
331 int i;
332 int num_parents;
333 const char *parent_names[USB_SOURCE_MAX];
334 const char *name = np->name;
335
336 num_parents = of_count_phandle_with_args(np, "clocks", "#clock-cells");
337 if (num_parents <= 0 || num_parents > USB_SOURCE_MAX)
338 return;
339
340 for (i = 0; i < num_parents; i++) {
341 parent_names[i] = of_clk_get_parent_name(np, i);
342 if (!parent_names[i])
343 return;
344 }
345
346 of_property_read_string(np, "clock-output-names", &name);
347
348 clk = at91sam9x5_clk_register_usb(pmc, name, parent_names, num_parents);
349 if (IS_ERR(clk))
350 return;
351
352 of_clk_add_provider(np, of_clk_src_simple_get, clk);
353}
354
355void __init of_at91sam9n12_clk_usb_setup(struct device_node *np,
356 struct at91_pmc *pmc)
357{
358 struct clk *clk;
359 const char *parent_name;
360 const char *name = np->name;
361
362 parent_name = of_clk_get_parent_name(np, 0);
363 if (!parent_name)
364 return;
365
366 of_property_read_string(np, "clock-output-names", &name);
367
368 clk = at91sam9n12_clk_register_usb(pmc, name, parent_name);
369 if (IS_ERR(clk))
370 return;
371
372 of_clk_add_provider(np, of_clk_src_simple_get, clk);
373}
374
375void __init of_at91rm9200_clk_usb_setup(struct device_node *np,
376 struct at91_pmc *pmc)
377{
378 struct clk *clk;
379 const char *parent_name;
380 const char *name = np->name;
381 u32 divisors[4] = {0, 0, 0, 0};
382
383 parent_name = of_clk_get_parent_name(np, 0);
384 if (!parent_name)
385 return;
386
387 of_property_read_u32_array(np, "atmel,clk-divisors", divisors, 4);
388 if (!divisors[0])
389 return;
390
391 of_property_read_string(np, "clock-output-names", &name);
392
393 clk = at91rm9200_clk_register_usb(pmc, name, parent_name, divisors);
394 if (IS_ERR(clk))
395 return;
396
397 of_clk_add_provider(np, of_clk_src_simple_get, clk);
398}
diff --git a/drivers/clk/at91/clk-utmi.c b/drivers/clk/at91/clk-utmi.c
new file mode 100644
index 000000000000..ae3263bc1476
--- /dev/null
+++ b/drivers/clk/at91/clk-utmi.c
@@ -0,0 +1,159 @@
1/*
2 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 */
10
11#include <linux/clk-provider.h>
12#include <linux/clkdev.h>
13#include <linux/clk/at91_pmc.h>
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16#include <linux/of.h>
17#include <linux/of_address.h>
18#include <linux/of_irq.h>
19#include <linux/io.h>
20#include <linux/sched.h>
21#include <linux/wait.h>
22
23#include "pmc.h"
24
25#define UTMI_FIXED_MUL 40
26
27struct clk_utmi {
28 struct clk_hw hw;
29 struct at91_pmc *pmc;
30 unsigned int irq;
31 wait_queue_head_t wait;
32};
33
34#define to_clk_utmi(hw) container_of(hw, struct clk_utmi, hw)
35
36static irqreturn_t clk_utmi_irq_handler(int irq, void *dev_id)
37{
38 struct clk_utmi *utmi = (struct clk_utmi *)dev_id;
39
40 wake_up(&utmi->wait);
41 disable_irq_nosync(utmi->irq);
42
43 return IRQ_HANDLED;
44}
45
46static int clk_utmi_prepare(struct clk_hw *hw)
47{
48 struct clk_utmi *utmi = to_clk_utmi(hw);
49 struct at91_pmc *pmc = utmi->pmc;
50 u32 tmp = at91_pmc_read(AT91_CKGR_UCKR) | AT91_PMC_UPLLEN |
51 AT91_PMC_UPLLCOUNT | AT91_PMC_BIASEN;
52
53 pmc_write(pmc, AT91_CKGR_UCKR, tmp);
54
55 while (!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_LOCKU)) {
56 enable_irq(utmi->irq);
57 wait_event(utmi->wait,
58 pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_LOCKU);
59 }
60
61 return 0;
62}
63
64static int clk_utmi_is_prepared(struct clk_hw *hw)
65{
66 struct clk_utmi *utmi = to_clk_utmi(hw);
67 struct at91_pmc *pmc = utmi->pmc;
68
69 return !!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_LOCKU);
70}
71
72static void clk_utmi_unprepare(struct clk_hw *hw)
73{
74 struct clk_utmi *utmi = to_clk_utmi(hw);
75 struct at91_pmc *pmc = utmi->pmc;
76 u32 tmp = at91_pmc_read(AT91_CKGR_UCKR) & ~AT91_PMC_UPLLEN;
77
78 pmc_write(pmc, AT91_CKGR_UCKR, tmp);
79}
80
81static unsigned long clk_utmi_recalc_rate(struct clk_hw *hw,
82 unsigned long parent_rate)
83{
84 /* UTMI clk is a fixed clk multiplier */
85 return parent_rate * UTMI_FIXED_MUL;
86}
87
88static const struct clk_ops utmi_ops = {
89 .prepare = clk_utmi_prepare,
90 .unprepare = clk_utmi_unprepare,
91 .is_prepared = clk_utmi_is_prepared,
92 .recalc_rate = clk_utmi_recalc_rate,
93};
94
95static struct clk * __init
96at91_clk_register_utmi(struct at91_pmc *pmc, unsigned int irq,
97 const char *name, const char *parent_name)
98{
99 int ret;
100 struct clk_utmi *utmi;
101 struct clk *clk = NULL;
102 struct clk_init_data init;
103
104 utmi = kzalloc(sizeof(*utmi), GFP_KERNEL);
105 if (!utmi)
106 return ERR_PTR(-ENOMEM);
107
108 init.name = name;
109 init.ops = &utmi_ops;
110 init.parent_names = parent_name ? &parent_name : NULL;
111 init.num_parents = parent_name ? 1 : 0;
112 init.flags = CLK_SET_RATE_GATE;
113
114 utmi->hw.init = &init;
115 utmi->pmc = pmc;
116 utmi->irq = irq;
117 init_waitqueue_head(&utmi->wait);
118 irq_set_status_flags(utmi->irq, IRQ_NOAUTOEN);
119 ret = request_irq(utmi->irq, clk_utmi_irq_handler,
120 IRQF_TRIGGER_HIGH, "clk-utmi", utmi);
121 if (ret)
122 return ERR_PTR(ret);
123
124 clk = clk_register(NULL, &utmi->hw);
125 if (IS_ERR(clk))
126 kfree(utmi);
127
128 return clk;
129}
130
131static void __init
132of_at91_clk_utmi_setup(struct device_node *np, struct at91_pmc *pmc)
133{
134 unsigned int irq;
135 struct clk *clk;
136 const char *parent_name;
137 const char *name = np->name;
138
139 parent_name = of_clk_get_parent_name(np, 0);
140
141 of_property_read_string(np, "clock-output-names", &name);
142
143 irq = irq_of_parse_and_map(np, 0);
144 if (!irq)
145 return;
146
147 clk = at91_clk_register_utmi(pmc, irq, name, parent_name);
148 if (IS_ERR(clk))
149 return;
150
151 of_clk_add_provider(np, of_clk_src_simple_get, clk);
152 return;
153}
154
155void __init of_at91sam9x5_clk_utmi_setup(struct device_node *np,
156 struct at91_pmc *pmc)
157{
158 of_at91_clk_utmi_setup(np, pmc);
159}
diff --git a/drivers/clk/at91/pmc.c b/drivers/clk/at91/pmc.c
new file mode 100644
index 000000000000..7b9db603b936
--- /dev/null
+++ b/drivers/clk/at91/pmc.c
@@ -0,0 +1,397 @@
1/*
2 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 */
10
11#include <linux/clk-provider.h>
12#include <linux/clkdev.h>
13#include <linux/clk/at91_pmc.h>
14#include <linux/of.h>
15#include <linux/of_address.h>
16#include <linux/io.h>
17#include <linux/interrupt.h>
18#include <linux/irq.h>
19#include <linux/irqchip/chained_irq.h>
20#include <linux/irqdomain.h>
21#include <linux/of_irq.h>
22
23#include <asm/proc-fns.h>
24
25#include "pmc.h"
26
27void __iomem *at91_pmc_base;
28EXPORT_SYMBOL_GPL(at91_pmc_base);
29
30void at91sam9_idle(void)
31{
32 at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
33 cpu_do_idle();
34}
35
36int of_at91_get_clk_range(struct device_node *np, const char *propname,
37 struct clk_range *range)
38{
39 u32 min, max;
40 int ret;
41
42 ret = of_property_read_u32_index(np, propname, 0, &min);
43 if (ret)
44 return ret;
45
46 ret = of_property_read_u32_index(np, propname, 1, &max);
47 if (ret)
48 return ret;
49
50 if (range) {
51 range->min = min;
52 range->max = max;
53 }
54
55 return 0;
56}
57EXPORT_SYMBOL_GPL(of_at91_get_clk_range);
58
59static void pmc_irq_mask(struct irq_data *d)
60{
61 struct at91_pmc *pmc = irq_data_get_irq_chip_data(d);
62
63 pmc_write(pmc, AT91_PMC_IDR, 1 << d->hwirq);
64}
65
66static void pmc_irq_unmask(struct irq_data *d)
67{
68 struct at91_pmc *pmc = irq_data_get_irq_chip_data(d);
69
70 pmc_write(pmc, AT91_PMC_IER, 1 << d->hwirq);
71}
72
73static int pmc_irq_set_type(struct irq_data *d, unsigned type)
74{
75 if (type != IRQ_TYPE_LEVEL_HIGH) {
76 pr_warn("PMC: type not supported (support only IRQ_TYPE_LEVEL_HIGH type)\n");
77 return -EINVAL;
78 }
79
80 return 0;
81}
82
83static struct irq_chip pmc_irq = {
84 .name = "PMC",
85 .irq_disable = pmc_irq_mask,
86 .irq_mask = pmc_irq_mask,
87 .irq_unmask = pmc_irq_unmask,
88 .irq_set_type = pmc_irq_set_type,
89};
90
91static struct lock_class_key pmc_lock_class;
92
93static int pmc_irq_map(struct irq_domain *h, unsigned int virq,
94 irq_hw_number_t hw)
95{
96 struct at91_pmc *pmc = h->host_data;
97
98 irq_set_lockdep_class(virq, &pmc_lock_class);
99
100 irq_set_chip_and_handler(virq, &pmc_irq,
101 handle_level_irq);
102 set_irq_flags(virq, IRQF_VALID);
103 irq_set_chip_data(virq, pmc);
104
105 return 0;
106}
107
108static int pmc_irq_domain_xlate(struct irq_domain *d,
109 struct device_node *ctrlr,
110 const u32 *intspec, unsigned int intsize,
111 irq_hw_number_t *out_hwirq,
112 unsigned int *out_type)
113{
114 struct at91_pmc *pmc = d->host_data;
115 const struct at91_pmc_caps *caps = pmc->caps;
116
117 if (WARN_ON(intsize < 1))
118 return -EINVAL;
119
120 *out_hwirq = intspec[0];
121
122 if (!(caps->available_irqs & (1 << *out_hwirq)))
123 return -EINVAL;
124
125 *out_type = IRQ_TYPE_LEVEL_HIGH;
126
127 return 0;
128}
129
130static struct irq_domain_ops pmc_irq_ops = {
131 .map = pmc_irq_map,
132 .xlate = pmc_irq_domain_xlate,
133};
134
135static irqreturn_t pmc_irq_handler(int irq, void *data)
136{
137 struct at91_pmc *pmc = (struct at91_pmc *)data;
138 unsigned long sr;
139 int n;
140
141 sr = pmc_read(pmc, AT91_PMC_SR) & pmc_read(pmc, AT91_PMC_IMR);
142 if (!sr)
143 return IRQ_NONE;
144
145 for_each_set_bit(n, &sr, BITS_PER_LONG)
146 generic_handle_irq(irq_find_mapping(pmc->irqdomain, n));
147
148 return IRQ_HANDLED;
149}
150
151static const struct at91_pmc_caps at91rm9200_caps = {
152 .available_irqs = AT91_PMC_MOSCS | AT91_PMC_LOCKA | AT91_PMC_LOCKB |
153 AT91_PMC_MCKRDY | AT91_PMC_PCK0RDY |
154 AT91_PMC_PCK1RDY | AT91_PMC_PCK2RDY |
155 AT91_PMC_PCK3RDY,
156};
157
158static const struct at91_pmc_caps at91sam9260_caps = {
159 .available_irqs = AT91_PMC_MOSCS | AT91_PMC_LOCKA | AT91_PMC_LOCKB |
160 AT91_PMC_MCKRDY | AT91_PMC_PCK0RDY |
161 AT91_PMC_PCK1RDY,
162};
163
164static const struct at91_pmc_caps at91sam9g45_caps = {
165 .available_irqs = AT91_PMC_MOSCS | AT91_PMC_LOCKA | AT91_PMC_MCKRDY |
166 AT91_PMC_LOCKU | AT91_PMC_PCK0RDY |
167 AT91_PMC_PCK1RDY,
168};
169
170static const struct at91_pmc_caps at91sam9n12_caps = {
171 .available_irqs = AT91_PMC_MOSCS | AT91_PMC_LOCKA | AT91_PMC_LOCKB |
172 AT91_PMC_MCKRDY | AT91_PMC_PCK0RDY |
173 AT91_PMC_PCK1RDY | AT91_PMC_MOSCSELS |
174 AT91_PMC_MOSCRCS | AT91_PMC_CFDEV,
175};
176
177static const struct at91_pmc_caps at91sam9x5_caps = {
178 .available_irqs = AT91_PMC_MOSCS | AT91_PMC_LOCKA | AT91_PMC_MCKRDY |
179 AT91_PMC_LOCKU | AT91_PMC_PCK0RDY |
180 AT91_PMC_PCK1RDY | AT91_PMC_MOSCSELS |
181 AT91_PMC_MOSCRCS | AT91_PMC_CFDEV,
182};
183
184static const struct at91_pmc_caps sama5d3_caps = {
185 .available_irqs = AT91_PMC_MOSCS | AT91_PMC_LOCKA | AT91_PMC_MCKRDY |
186 AT91_PMC_LOCKU | AT91_PMC_PCK0RDY |
187 AT91_PMC_PCK1RDY | AT91_PMC_PCK2RDY |
188 AT91_PMC_MOSCSELS | AT91_PMC_MOSCRCS |
189 AT91_PMC_CFDEV,
190};
191
192static struct at91_pmc *__init at91_pmc_init(struct device_node *np,
193 void __iomem *regbase, int virq,
194 const struct at91_pmc_caps *caps)
195{
196 struct at91_pmc *pmc;
197
198 if (!regbase || !virq || !caps)
199 return NULL;
200
201 at91_pmc_base = regbase;
202
203 pmc = kzalloc(sizeof(*pmc), GFP_KERNEL);
204 if (!pmc)
205 return NULL;
206
207 spin_lock_init(&pmc->lock);
208 pmc->regbase = regbase;
209 pmc->virq = virq;
210 pmc->caps = caps;
211
212 pmc->irqdomain = irq_domain_add_linear(np, 32, &pmc_irq_ops, pmc);
213
214 if (!pmc->irqdomain)
215 goto out_free_pmc;
216
217 pmc_write(pmc, AT91_PMC_IDR, 0xffffffff);
218 if (request_irq(pmc->virq, pmc_irq_handler, IRQF_SHARED, "pmc", pmc))
219 goto out_remove_irqdomain;
220
221 return pmc;
222
223out_remove_irqdomain:
224 irq_domain_remove(pmc->irqdomain);
225out_free_pmc:
226 kfree(pmc);
227
228 return NULL;
229}
230
231static const struct of_device_id pmc_clk_ids[] __initdata = {
232 /* Main clock */
233 {
234 .compatible = "atmel,at91rm9200-clk-main",
235 .data = of_at91rm9200_clk_main_setup,
236 },
237 /* PLL clocks */
238 {
239 .compatible = "atmel,at91rm9200-clk-pll",
240 .data = of_at91rm9200_clk_pll_setup,
241 },
242 {
243 .compatible = "atmel,at91sam9g45-clk-pll",
244 .data = of_at91sam9g45_clk_pll_setup,
245 },
246 {
247 .compatible = "atmel,at91sam9g20-clk-pllb",
248 .data = of_at91sam9g20_clk_pllb_setup,
249 },
250 {
251 .compatible = "atmel,sama5d3-clk-pll",
252 .data = of_sama5d3_clk_pll_setup,
253 },
254 {
255 .compatible = "atmel,at91sam9x5-clk-plldiv",
256 .data = of_at91sam9x5_clk_plldiv_setup,
257 },
258 /* Master clock */
259 {
260 .compatible = "atmel,at91rm9200-clk-master",
261 .data = of_at91rm9200_clk_master_setup,
262 },
263 {
264 .compatible = "atmel,at91sam9x5-clk-master",
265 .data = of_at91sam9x5_clk_master_setup,
266 },
267 /* System clocks */
268 {
269 .compatible = "atmel,at91rm9200-clk-system",
270 .data = of_at91rm9200_clk_sys_setup,
271 },
272 /* Peripheral clocks */
273 {
274 .compatible = "atmel,at91rm9200-clk-peripheral",
275 .data = of_at91rm9200_clk_periph_setup,
276 },
277 {
278 .compatible = "atmel,at91sam9x5-clk-peripheral",
279 .data = of_at91sam9x5_clk_periph_setup,
280 },
281 /* Programmable clocks */
282#if defined(CONFIG_AT91_PROGRAMMABLE_CLOCKS)
283 {
284 .compatible = "atmel,at91rm9200-clk-programmable",
285 .data = of_at91rm9200_clk_prog_setup,
286 },
287 {
288 .compatible = "atmel,at91sam9g45-clk-programmable",
289 .data = of_at91sam9g45_clk_prog_setup,
290 },
291 {
292 .compatible = "atmel,at91sam9x5-clk-programmable",
293 .data = of_at91sam9x5_clk_prog_setup,
294 },
295#endif
296 /* UTMI clock */
297#if defined(CONFIG_HAVE_AT91_UTMI)
298 {
299 .compatible = "atmel,at91sam9x5-clk-utmi",
300 .data = of_at91sam9x5_clk_utmi_setup,
301 },
302#endif
303 /* USB clock */
304#if defined(CONFIG_HAVE_AT91_USB_CLK)
305 {
306 .compatible = "atmel,at91rm9200-clk-usb",
307 .data = of_at91rm9200_clk_usb_setup,
308 },
309 {
310 .compatible = "atmel,at91sam9x5-clk-usb",
311 .data = of_at91sam9x5_clk_usb_setup,
312 },
313 {
314 .compatible = "atmel,at91sam9n12-clk-usb",
315 .data = of_at91sam9n12_clk_usb_setup,
316 },
317#endif
318 /* SMD clock */
319#if defined(CONFIG_HAVE_AT91_SMD)
320 {
321 .compatible = "atmel,at91sam9x5-clk-smd",
322 .data = of_at91sam9x5_clk_smd_setup,
323 },
324#endif
325 { /*sentinel*/ }
326};
327
328static void __init of_at91_pmc_setup(struct device_node *np,
329 const struct at91_pmc_caps *caps)
330{
331 struct at91_pmc *pmc;
332 struct device_node *childnp;
333 void (*clk_setup)(struct device_node *, struct at91_pmc *);
334 const struct of_device_id *clk_id;
335 void __iomem *regbase = of_iomap(np, 0);
336 int virq;
337
338 if (!regbase)
339 return;
340
341 virq = irq_of_parse_and_map(np, 0);
342 if (!virq)
343 return;
344
345 pmc = at91_pmc_init(np, regbase, virq, caps);
346 if (!pmc)
347 return;
348 for_each_child_of_node(np, childnp) {
349 clk_id = of_match_node(pmc_clk_ids, childnp);
350 if (!clk_id)
351 continue;
352 clk_setup = clk_id->data;
353 clk_setup(childnp, pmc);
354 }
355}
356
357static void __init of_at91rm9200_pmc_setup(struct device_node *np)
358{
359 of_at91_pmc_setup(np, &at91rm9200_caps);
360}
361CLK_OF_DECLARE(at91rm9200_clk_pmc, "atmel,at91rm9200-pmc",
362 of_at91rm9200_pmc_setup);
363
364static void __init of_at91sam9260_pmc_setup(struct device_node *np)
365{
366 of_at91_pmc_setup(np, &at91sam9260_caps);
367}
368CLK_OF_DECLARE(at91sam9260_clk_pmc, "atmel,at91sam9260-pmc",
369 of_at91sam9260_pmc_setup);
370
371static void __init of_at91sam9g45_pmc_setup(struct device_node *np)
372{
373 of_at91_pmc_setup(np, &at91sam9g45_caps);
374}
375CLK_OF_DECLARE(at91sam9g45_clk_pmc, "atmel,at91sam9g45-pmc",
376 of_at91sam9g45_pmc_setup);
377
378static void __init of_at91sam9n12_pmc_setup(struct device_node *np)
379{
380 of_at91_pmc_setup(np, &at91sam9n12_caps);
381}
382CLK_OF_DECLARE(at91sam9n12_clk_pmc, "atmel,at91sam9n12-pmc",
383 of_at91sam9n12_pmc_setup);
384
385static void __init of_at91sam9x5_pmc_setup(struct device_node *np)
386{
387 of_at91_pmc_setup(np, &at91sam9x5_caps);
388}
389CLK_OF_DECLARE(at91sam9x5_clk_pmc, "atmel,at91sam9x5-pmc",
390 of_at91sam9x5_pmc_setup);
391
392static void __init of_sama5d3_pmc_setup(struct device_node *np)
393{
394 of_at91_pmc_setup(np, &sama5d3_caps);
395}
396CLK_OF_DECLARE(sama5d3_clk_pmc, "atmel,sama5d3-pmc",
397 of_sama5d3_pmc_setup);
diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h
new file mode 100644
index 000000000000..ba8d14233f80
--- /dev/null
+++ b/drivers/clk/at91/pmc.h
@@ -0,0 +1,116 @@
1/*
2 * drivers/clk/at91/pmc.h
3 *
4 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#ifndef __PMC_H_
13#define __PMC_H_
14
15#include <linux/io.h>
16#include <linux/irqdomain.h>
17#include <linux/spinlock.h>
18
19struct clk_range {
20 unsigned long min;
21 unsigned long max;
22};
23
24#define CLK_RANGE(MIN, MAX) {.min = MIN, .max = MAX,}
25
26struct at91_pmc_caps {
27 u32 available_irqs;
28};
29
30struct at91_pmc {
31 void __iomem *regbase;
32 int virq;
33 spinlock_t lock;
34 const struct at91_pmc_caps *caps;
35 struct irq_domain *irqdomain;
36};
37
38static inline void pmc_lock(struct at91_pmc *pmc)
39{
40 spin_lock(&pmc->lock);
41}
42
43static inline void pmc_unlock(struct at91_pmc *pmc)
44{
45 spin_unlock(&pmc->lock);
46}
47
48static inline u32 pmc_read(struct at91_pmc *pmc, int offset)
49{
50 return readl(pmc->regbase + offset);
51}
52
53static inline void pmc_write(struct at91_pmc *pmc, int offset, u32 value)
54{
55 writel(value, pmc->regbase + offset);
56}
57
58int of_at91_get_clk_range(struct device_node *np, const char *propname,
59 struct clk_range *range);
60
61extern void __init of_at91rm9200_clk_main_setup(struct device_node *np,
62 struct at91_pmc *pmc);
63
64extern void __init of_at91rm9200_clk_pll_setup(struct device_node *np,
65 struct at91_pmc *pmc);
66extern void __init of_at91sam9g45_clk_pll_setup(struct device_node *np,
67 struct at91_pmc *pmc);
68extern void __init of_at91sam9g20_clk_pllb_setup(struct device_node *np,
69 struct at91_pmc *pmc);
70extern void __init of_sama5d3_clk_pll_setup(struct device_node *np,
71 struct at91_pmc *pmc);
72extern void __init of_at91sam9x5_clk_plldiv_setup(struct device_node *np,
73 struct at91_pmc *pmc);
74
75extern void __init of_at91rm9200_clk_master_setup(struct device_node *np,
76 struct at91_pmc *pmc);
77extern void __init of_at91sam9x5_clk_master_setup(struct device_node *np,
78 struct at91_pmc *pmc);
79
80extern void __init of_at91rm9200_clk_sys_setup(struct device_node *np,
81 struct at91_pmc *pmc);
82
83extern void __init of_at91rm9200_clk_periph_setup(struct device_node *np,
84 struct at91_pmc *pmc);
85extern void __init of_at91sam9x5_clk_periph_setup(struct device_node *np,
86 struct at91_pmc *pmc);
87
88#if defined(CONFIG_AT91_PROGRAMMABLE_CLOCKS)
89extern void __init of_at91rm9200_clk_prog_setup(struct device_node *np,
90 struct at91_pmc *pmc);
91extern void __init of_at91sam9g45_clk_prog_setup(struct device_node *np,
92 struct at91_pmc *pmc);
93extern void __init of_at91sam9x5_clk_prog_setup(struct device_node *np,
94 struct at91_pmc *pmc);
95#endif
96
97#if defined(CONFIG_HAVE_AT91_UTMI)
98extern void __init of_at91sam9x5_clk_utmi_setup(struct device_node *np,
99 struct at91_pmc *pmc);
100#endif
101
102#if defined(CONFIG_HAVE_AT91_USB_CLK)
103extern void __init of_at91rm9200_clk_usb_setup(struct device_node *np,
104 struct at91_pmc *pmc);
105extern void __init of_at91sam9x5_clk_usb_setup(struct device_node *np,
106 struct at91_pmc *pmc);
107extern void __init of_at91sam9n12_clk_usb_setup(struct device_node *np,
108 struct at91_pmc *pmc);
109#endif
110
111#if defined(CONFIG_HAVE_AT91_SMD)
112extern void __init of_at91sam9x5_clk_smd_setup(struct device_node *np,
113 struct at91_pmc *pmc);
114#endif
115
116#endif /* __PMC_H_ */
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index ad5ff50c5f28..d967571d305e 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -530,7 +530,8 @@ static struct samsung_div_clock exynos4_div_clks[] __initdata = {
530 DIV(sclk_i2s1, "sclk_i2s1", "sclk_audio1", DIV_PERIL5, 0, 6), 530 DIV(sclk_i2s1, "sclk_i2s1", "sclk_audio1", DIV_PERIL5, 0, 6),
531 DIV(sclk_i2s2, "sclk_i2s2", "sclk_audio2", DIV_PERIL5, 8, 6), 531 DIV(sclk_i2s2, "sclk_i2s2", "sclk_audio2", DIV_PERIL5, 8, 6),
532 DIV(none, "div_mmc4", "mout_mmc4", DIV_FSYS3, 0, 4), 532 DIV(none, "div_mmc4", "mout_mmc4", DIV_FSYS3, 0, 4),
533 DIV(none, "div_mmc_pre4", "div_mmc4", DIV_FSYS3, 8, 8), 533 DIV_F(none, "div_mmc_pre4", "div_mmc4", DIV_FSYS3, 8, 8,
534 CLK_SET_RATE_PARENT, 0),
534 DIV(none, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4), 535 DIV(none, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
535 DIV(none, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4), 536 DIV(none, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
536 DIV(none, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4), 537 DIV(none, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile
index f49fac2d193a..f7dfb72884a4 100644
--- a/drivers/clk/tegra/Makefile
+++ b/drivers/clk/tegra/Makefile
@@ -6,7 +6,12 @@ obj-y += clk-periph-gate.o
6obj-y += clk-pll.o 6obj-y += clk-pll.o
7obj-y += clk-pll-out.o 7obj-y += clk-pll-out.o
8obj-y += clk-super.o 8obj-y += clk-super.o
9 9obj-y += clk-tegra-audio.o
10obj-y += clk-tegra-periph.o
11obj-y += clk-tegra-pmc.o
12obj-y += clk-tegra-fixed.o
13obj-y += clk-tegra-super-gen4.o
10obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clk-tegra20.o 14obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clk-tegra20.o
11obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += clk-tegra30.o 15obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += clk-tegra30.o
12obj-$(CONFIG_ARCH_TEGRA_114_SOC) += clk-tegra114.o 16obj-$(CONFIG_ARCH_TEGRA_114_SOC) += clk-tegra114.o
17obj-$(CONFIG_ARCH_TEGRA_124_SOC) += clk-tegra124.o
diff --git a/drivers/clk/tegra/clk-id.h b/drivers/clk/tegra/clk-id.h
new file mode 100644
index 000000000000..cf0c323f2c36
--- /dev/null
+++ b/drivers/clk/tegra/clk-id.h
@@ -0,0 +1,235 @@
1/*
2 * This header provides IDs for clocks common between several Tegra SoCs
3 */
4#ifndef _TEGRA_CLK_ID_H
5#define _TEGRA_CLK_ID_H
6
7enum clk_id {
8 tegra_clk_actmon,
9 tegra_clk_adx,
10 tegra_clk_adx1,
11 tegra_clk_afi,
12 tegra_clk_amx,
13 tegra_clk_amx1,
14 tegra_clk_apbdma,
15 tegra_clk_apbif,
16 tegra_clk_audio0,
17 tegra_clk_audio0_2x,
18 tegra_clk_audio0_mux,
19 tegra_clk_audio1,
20 tegra_clk_audio1_2x,
21 tegra_clk_audio1_mux,
22 tegra_clk_audio2,
23 tegra_clk_audio2_2x,
24 tegra_clk_audio2_mux,
25 tegra_clk_audio3,
26 tegra_clk_audio3_2x,
27 tegra_clk_audio3_mux,
28 tegra_clk_audio4,
29 tegra_clk_audio4_2x,
30 tegra_clk_audio4_mux,
31 tegra_clk_blink,
32 tegra_clk_bsea,
33 tegra_clk_bsev,
34 tegra_clk_cclk_g,
35 tegra_clk_cclk_lp,
36 tegra_clk_cilab,
37 tegra_clk_cilcd,
38 tegra_clk_cile,
39 tegra_clk_clk_32k,
40 tegra_clk_clk72Mhz,
41 tegra_clk_clk_m,
42 tegra_clk_clk_m_div2,
43 tegra_clk_clk_m_div4,
44 tegra_clk_clk_out_1,
45 tegra_clk_clk_out_1_mux,
46 tegra_clk_clk_out_2,
47 tegra_clk_clk_out_2_mux,
48 tegra_clk_clk_out_3,
49 tegra_clk_clk_out_3_mux,
50 tegra_clk_cml0,
51 tegra_clk_cml1,
52 tegra_clk_csi,
53 tegra_clk_csite,
54 tegra_clk_csus,
55 tegra_clk_cve,
56 tegra_clk_dam0,
57 tegra_clk_dam1,
58 tegra_clk_dam2,
59 tegra_clk_d_audio,
60 tegra_clk_dds,
61 tegra_clk_dfll_ref,
62 tegra_clk_dfll_soc,
63 tegra_clk_disp1,
64 tegra_clk_disp2,
65 tegra_clk_dp2,
66 tegra_clk_dpaux,
67 tegra_clk_dsia,
68 tegra_clk_dsialp,
69 tegra_clk_dsia_mux,
70 tegra_clk_dsib,
71 tegra_clk_dsiblp,
72 tegra_clk_dsib_mux,
73 tegra_clk_dtv,
74 tegra_clk_emc,
75 tegra_clk_entropy,
76 tegra_clk_epp,
77 tegra_clk_epp_8,
78 tegra_clk_extern1,
79 tegra_clk_extern2,
80 tegra_clk_extern3,
81 tegra_clk_fuse,
82 tegra_clk_fuse_burn,
83 tegra_clk_gpu,
84 tegra_clk_gr2d,
85 tegra_clk_gr2d_8,
86 tegra_clk_gr3d,
87 tegra_clk_gr3d_8,
88 tegra_clk_hclk,
89 tegra_clk_hda,
90 tegra_clk_hda2codec_2x,
91 tegra_clk_hda2hdmi,
92 tegra_clk_hdmi,
93 tegra_clk_hdmi_audio,
94 tegra_clk_host1x,
95 tegra_clk_host1x_8,
96 tegra_clk_i2c1,
97 tegra_clk_i2c2,
98 tegra_clk_i2c3,
99 tegra_clk_i2c4,
100 tegra_clk_i2c5,
101 tegra_clk_i2c6,
102 tegra_clk_i2cslow,
103 tegra_clk_i2s0,
104 tegra_clk_i2s0_sync,
105 tegra_clk_i2s1,
106 tegra_clk_i2s1_sync,
107 tegra_clk_i2s2,
108 tegra_clk_i2s2_sync,
109 tegra_clk_i2s3,
110 tegra_clk_i2s3_sync,
111 tegra_clk_i2s4,
112 tegra_clk_i2s4_sync,
113 tegra_clk_isp,
114 tegra_clk_isp_8,
115 tegra_clk_ispb,
116 tegra_clk_kbc,
117 tegra_clk_kfuse,
118 tegra_clk_la,
119 tegra_clk_mipi,
120 tegra_clk_mipi_cal,
121 tegra_clk_mpe,
122 tegra_clk_mselect,
123 tegra_clk_msenc,
124 tegra_clk_ndflash,
125 tegra_clk_ndflash_8,
126 tegra_clk_ndspeed,
127 tegra_clk_ndspeed_8,
128 tegra_clk_nor,
129 tegra_clk_owr,
130 tegra_clk_pcie,
131 tegra_clk_pclk,
132 tegra_clk_pll_a,
133 tegra_clk_pll_a_out0,
134 tegra_clk_pll_c,
135 tegra_clk_pll_c2,
136 tegra_clk_pll_c3,
137 tegra_clk_pll_c4,
138 tegra_clk_pll_c_out1,
139 tegra_clk_pll_d,
140 tegra_clk_pll_d2,
141 tegra_clk_pll_d2_out0,
142 tegra_clk_pll_d_out0,
143 tegra_clk_pll_dp,
144 tegra_clk_pll_e_out0,
145 tegra_clk_pll_m,
146 tegra_clk_pll_m_out1,
147 tegra_clk_pll_p,
148 tegra_clk_pll_p_out1,
149 tegra_clk_pll_p_out2,
150 tegra_clk_pll_p_out2_int,
151 tegra_clk_pll_p_out3,
152 tegra_clk_pll_p_out4,
153 tegra_clk_pll_p_out5,
154 tegra_clk_pll_ref,
155 tegra_clk_pll_re_out,
156 tegra_clk_pll_re_vco,
157 tegra_clk_pll_u,
158 tegra_clk_pll_u_12m,
159 tegra_clk_pll_u_480m,
160 tegra_clk_pll_u_48m,
161 tegra_clk_pll_u_60m,
162 tegra_clk_pll_x,
163 tegra_clk_pll_x_out0,
164 tegra_clk_pwm,
165 tegra_clk_rtc,
166 tegra_clk_sata,
167 tegra_clk_sata_cold,
168 tegra_clk_sata_oob,
169 tegra_clk_sbc1,
170 tegra_clk_sbc1_8,
171 tegra_clk_sbc2,
172 tegra_clk_sbc2_8,
173 tegra_clk_sbc3,
174 tegra_clk_sbc3_8,
175 tegra_clk_sbc4,
176 tegra_clk_sbc4_8,
177 tegra_clk_sbc5,
178 tegra_clk_sbc5_8,
179 tegra_clk_sbc6,
180 tegra_clk_sbc6_8,
181 tegra_clk_sclk,
182 tegra_clk_sdmmc1,
183 tegra_clk_sdmmc2,
184 tegra_clk_sdmmc3,
185 tegra_clk_sdmmc4,
186 tegra_clk_se,
187 tegra_clk_soc_therm,
188 tegra_clk_sor0,
189 tegra_clk_sor0_lvds,
190 tegra_clk_spdif,
191 tegra_clk_spdif_2x,
192 tegra_clk_spdif_in,
193 tegra_clk_spdif_in_sync,
194 tegra_clk_spdif_mux,
195 tegra_clk_spdif_out,
196 tegra_clk_timer,
197 tegra_clk_trace,
198 tegra_clk_tsec,
199 tegra_clk_tsensor,
200 tegra_clk_tvdac,
201 tegra_clk_tvo,
202 tegra_clk_uarta,
203 tegra_clk_uartb,
204 tegra_clk_uartc,
205 tegra_clk_uartd,
206 tegra_clk_uarte,
207 tegra_clk_usb2,
208 tegra_clk_usb3,
209 tegra_clk_usbd,
210 tegra_clk_vcp,
211 tegra_clk_vde,
212 tegra_clk_vde_8,
213 tegra_clk_vfir,
214 tegra_clk_vi,
215 tegra_clk_vi_8,
216 tegra_clk_vi_9,
217 tegra_clk_vic03,
218 tegra_clk_vim2_clk,
219 tegra_clk_vimclk_sync,
220 tegra_clk_vi_sensor,
221 tegra_clk_vi_sensor2,
222 tegra_clk_vi_sensor_8,
223 tegra_clk_xusb_dev,
224 tegra_clk_xusb_dev_src,
225 tegra_clk_xusb_falcon_src,
226 tegra_clk_xusb_fs_src,
227 tegra_clk_xusb_host,
228 tegra_clk_xusb_host_src,
229 tegra_clk_xusb_hs_src,
230 tegra_clk_xusb_ss,
231 tegra_clk_xusb_ss_src,
232 tegra_clk_max,
233};
234
235#endif /* _TEGRA_CLK_ID_H */
diff --git a/drivers/clk/tegra/clk-periph-gate.c b/drivers/clk/tegra/clk-periph-gate.c
index bafee9895a24..507015314827 100644
--- a/drivers/clk/tegra/clk-periph-gate.c
+++ b/drivers/clk/tegra/clk-periph-gate.c
@@ -36,8 +36,6 @@ static DEFINE_SPINLOCK(periph_ref_lock);
36 36
37#define read_rst(gate) \ 37#define read_rst(gate) \
38 readl_relaxed(gate->clk_base + (gate->regs->rst_reg)) 38 readl_relaxed(gate->clk_base + (gate->regs->rst_reg))
39#define write_rst_set(val, gate) \
40 writel_relaxed(val, gate->clk_base + (gate->regs->rst_set_reg))
41#define write_rst_clr(val, gate) \ 39#define write_rst_clr(val, gate) \
42 writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg)) 40 writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg))
43 41
@@ -123,26 +121,6 @@ static void clk_periph_disable(struct clk_hw *hw)
123 spin_unlock_irqrestore(&periph_ref_lock, flags); 121 spin_unlock_irqrestore(&periph_ref_lock, flags);
124} 122}
125 123
126void tegra_periph_reset(struct tegra_clk_periph_gate *gate, bool assert)
127{
128 if (gate->flags & TEGRA_PERIPH_NO_RESET)
129 return;
130
131 if (assert) {
132 /*
133 * If peripheral is in the APB bus then read the APB bus to
134 * flush the write operation in apb bus. This will avoid the
135 * peripheral access after disabling clock
136 */
137 if (gate->flags & TEGRA_PERIPH_ON_APB)
138 tegra_read_chipid();
139
140 write_rst_set(periph_clk_to_bit(gate), gate);
141 } else {
142 write_rst_clr(periph_clk_to_bit(gate), gate);
143 }
144}
145
146const struct clk_ops tegra_clk_periph_gate_ops = { 124const struct clk_ops tegra_clk_periph_gate_ops = {
147 .is_enabled = clk_periph_is_enabled, 125 .is_enabled = clk_periph_is_enabled,
148 .enable = clk_periph_enable, 126 .enable = clk_periph_enable,
@@ -151,12 +129,16 @@ const struct clk_ops tegra_clk_periph_gate_ops = {
151 129
152struct clk *tegra_clk_register_periph_gate(const char *name, 130struct clk *tegra_clk_register_periph_gate(const char *name,
153 const char *parent_name, u8 gate_flags, void __iomem *clk_base, 131 const char *parent_name, u8 gate_flags, void __iomem *clk_base,
154 unsigned long flags, int clk_num, 132 unsigned long flags, int clk_num, int *enable_refcnt)
155 struct tegra_clk_periph_regs *pregs, int *enable_refcnt)
156{ 133{
157 struct tegra_clk_periph_gate *gate; 134 struct tegra_clk_periph_gate *gate;
158 struct clk *clk; 135 struct clk *clk;
159 struct clk_init_data init; 136 struct clk_init_data init;
137 struct tegra_clk_periph_regs *pregs;
138
139 pregs = get_reg_bank(clk_num);
140 if (!pregs)
141 return ERR_PTR(-EINVAL);
160 142
161 gate = kzalloc(sizeof(*gate), GFP_KERNEL); 143 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
162 if (!gate) { 144 if (!gate) {
diff --git a/drivers/clk/tegra/clk-periph.c b/drivers/clk/tegra/clk-periph.c
index b2309d37a963..c534043c0481 100644
--- a/drivers/clk/tegra/clk-periph.c
+++ b/drivers/clk/tegra/clk-periph.c
@@ -111,46 +111,6 @@ static void clk_periph_disable(struct clk_hw *hw)
111 gate_ops->disable(gate_hw); 111 gate_ops->disable(gate_hw);
112} 112}
113 113
114void tegra_periph_reset_deassert(struct clk *c)
115{
116 struct clk_hw *hw = __clk_get_hw(c);
117 struct tegra_clk_periph *periph = to_clk_periph(hw);
118 struct tegra_clk_periph_gate *gate;
119
120 if (periph->magic != TEGRA_CLK_PERIPH_MAGIC) {
121 gate = to_clk_periph_gate(hw);
122 if (gate->magic != TEGRA_CLK_PERIPH_GATE_MAGIC) {
123 WARN_ON(1);
124 return;
125 }
126 } else {
127 gate = &periph->gate;
128 }
129
130 tegra_periph_reset(gate, 0);
131}
132EXPORT_SYMBOL(tegra_periph_reset_deassert);
133
134void tegra_periph_reset_assert(struct clk *c)
135{
136 struct clk_hw *hw = __clk_get_hw(c);
137 struct tegra_clk_periph *periph = to_clk_periph(hw);
138 struct tegra_clk_periph_gate *gate;
139
140 if (periph->magic != TEGRA_CLK_PERIPH_MAGIC) {
141 gate = to_clk_periph_gate(hw);
142 if (gate->magic != TEGRA_CLK_PERIPH_GATE_MAGIC) {
143 WARN_ON(1);
144 return;
145 }
146 } else {
147 gate = &periph->gate;
148 }
149
150 tegra_periph_reset(gate, 1);
151}
152EXPORT_SYMBOL(tegra_periph_reset_assert);
153
154const struct clk_ops tegra_clk_periph_ops = { 114const struct clk_ops tegra_clk_periph_ops = {
155 .get_parent = clk_periph_get_parent, 115 .get_parent = clk_periph_get_parent,
156 .set_parent = clk_periph_set_parent, 116 .set_parent = clk_periph_set_parent,
@@ -170,27 +130,50 @@ const struct clk_ops tegra_clk_periph_nodiv_ops = {
170 .disable = clk_periph_disable, 130 .disable = clk_periph_disable,
171}; 131};
172 132
133const struct clk_ops tegra_clk_periph_no_gate_ops = {
134 .get_parent = clk_periph_get_parent,
135 .set_parent = clk_periph_set_parent,
136 .recalc_rate = clk_periph_recalc_rate,
137 .round_rate = clk_periph_round_rate,
138 .set_rate = clk_periph_set_rate,
139};
140
173static struct clk *_tegra_clk_register_periph(const char *name, 141static struct clk *_tegra_clk_register_periph(const char *name,
174 const char **parent_names, int num_parents, 142 const char **parent_names, int num_parents,
175 struct tegra_clk_periph *periph, 143 struct tegra_clk_periph *periph,
176 void __iomem *clk_base, u32 offset, bool div, 144 void __iomem *clk_base, u32 offset,
177 unsigned long flags) 145 unsigned long flags)
178{ 146{
179 struct clk *clk; 147 struct clk *clk;
180 struct clk_init_data init; 148 struct clk_init_data init;
149 struct tegra_clk_periph_regs *bank;
150 bool div = !(periph->gate.flags & TEGRA_PERIPH_NO_DIV);
151
152 if (periph->gate.flags & TEGRA_PERIPH_NO_DIV) {
153 flags |= CLK_SET_RATE_PARENT;
154 init.ops = &tegra_clk_periph_nodiv_ops;
155 } else if (periph->gate.flags & TEGRA_PERIPH_NO_GATE)
156 init.ops = &tegra_clk_periph_no_gate_ops;
157 else
158 init.ops = &tegra_clk_periph_ops;
181 159
182 init.name = name; 160 init.name = name;
183 init.ops = div ? &tegra_clk_periph_ops : &tegra_clk_periph_nodiv_ops;
184 init.flags = flags; 161 init.flags = flags;
185 init.parent_names = parent_names; 162 init.parent_names = parent_names;
186 init.num_parents = num_parents; 163 init.num_parents = num_parents;
187 164
165 bank = get_reg_bank(periph->gate.clk_num);
166 if (!bank)
167 return ERR_PTR(-EINVAL);
168
188 /* Data in .init is copied by clk_register(), so stack variable OK */ 169 /* Data in .init is copied by clk_register(), so stack variable OK */
189 periph->hw.init = &init; 170 periph->hw.init = &init;
190 periph->magic = TEGRA_CLK_PERIPH_MAGIC; 171 periph->magic = TEGRA_CLK_PERIPH_MAGIC;
191 periph->mux.reg = clk_base + offset; 172 periph->mux.reg = clk_base + offset;
192 periph->divider.reg = div ? (clk_base + offset) : NULL; 173 periph->divider.reg = div ? (clk_base + offset) : NULL;
193 periph->gate.clk_base = clk_base; 174 periph->gate.clk_base = clk_base;
175 periph->gate.regs = bank;
176 periph->gate.enable_refcnt = periph_clk_enb_refcnt;
194 177
195 clk = clk_register(NULL, &periph->hw); 178 clk = clk_register(NULL, &periph->hw);
196 if (IS_ERR(clk)) 179 if (IS_ERR(clk))
@@ -209,7 +192,7 @@ struct clk *tegra_clk_register_periph(const char *name,
209 u32 offset, unsigned long flags) 192 u32 offset, unsigned long flags)
210{ 193{
211 return _tegra_clk_register_periph(name, parent_names, num_parents, 194 return _tegra_clk_register_periph(name, parent_names, num_parents,
212 periph, clk_base, offset, true, flags); 195 periph, clk_base, offset, flags);
213} 196}
214 197
215struct clk *tegra_clk_register_periph_nodiv(const char *name, 198struct clk *tegra_clk_register_periph_nodiv(const char *name,
@@ -217,6 +200,7 @@ struct clk *tegra_clk_register_periph_nodiv(const char *name,
217 struct tegra_clk_periph *periph, void __iomem *clk_base, 200 struct tegra_clk_periph *periph, void __iomem *clk_base,
218 u32 offset) 201 u32 offset)
219{ 202{
203 periph->gate.flags |= TEGRA_PERIPH_NO_DIV;
220 return _tegra_clk_register_periph(name, parent_names, num_parents, 204 return _tegra_clk_register_periph(name, parent_names, num_parents,
221 periph, clk_base, offset, false, CLK_SET_RATE_PARENT); 205 periph, clk_base, offset, CLK_SET_RATE_PARENT);
222} 206}
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 197074a57754..2dd432266ef6 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -77,7 +77,23 @@
77#define PLLE_MISC_SETUP_VALUE (7 << PLLE_MISC_SETUP_BASE_SHIFT) 77#define PLLE_MISC_SETUP_VALUE (7 << PLLE_MISC_SETUP_BASE_SHIFT)
78 78
79#define PLLE_SS_CTRL 0x68 79#define PLLE_SS_CTRL 0x68
80#define PLLE_SS_DISABLE (7 << 10) 80#define PLLE_SS_CNTL_BYPASS_SS BIT(10)
81#define PLLE_SS_CNTL_INTERP_RESET BIT(11)
82#define PLLE_SS_CNTL_SSC_BYP BIT(12)
83#define PLLE_SS_CNTL_CENTER BIT(14)
84#define PLLE_SS_CNTL_INVERT BIT(15)
85#define PLLE_SS_DISABLE (PLLE_SS_CNTL_BYPASS_SS | PLLE_SS_CNTL_INTERP_RESET |\
86 PLLE_SS_CNTL_SSC_BYP)
87#define PLLE_SS_MAX_MASK 0x1ff
88#define PLLE_SS_MAX_VAL 0x25
89#define PLLE_SS_INC_MASK (0xff << 16)
90#define PLLE_SS_INC_VAL (0x1 << 16)
91#define PLLE_SS_INCINTRV_MASK (0x3f << 24)
92#define PLLE_SS_INCINTRV_VAL (0x20 << 24)
93#define PLLE_SS_COEFFICIENTS_MASK \
94 (PLLE_SS_MAX_MASK | PLLE_SS_INC_MASK | PLLE_SS_INCINTRV_MASK)
95#define PLLE_SS_COEFFICIENTS_VAL \
96 (PLLE_SS_MAX_VAL | PLLE_SS_INC_VAL | PLLE_SS_INCINTRV_VAL)
81 97
82#define PLLE_AUX_PLLP_SEL BIT(2) 98#define PLLE_AUX_PLLP_SEL BIT(2)
83#define PLLE_AUX_ENABLE_SWCTL BIT(4) 99#define PLLE_AUX_ENABLE_SWCTL BIT(4)
@@ -121,6 +137,36 @@
121#define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE BIT(5) 137#define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE BIT(5)
122#define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL BIT(4) 138#define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL BIT(4)
123 139
140#define PLLSS_MISC_KCP 0
141#define PLLSS_MISC_KVCO 0
142#define PLLSS_MISC_SETUP 0
143#define PLLSS_EN_SDM 0
144#define PLLSS_EN_SSC 0
145#define PLLSS_EN_DITHER2 0
146#define PLLSS_EN_DITHER 1
147#define PLLSS_SDM_RESET 0
148#define PLLSS_CLAMP 0
149#define PLLSS_SDM_SSC_MAX 0
150#define PLLSS_SDM_SSC_MIN 0
151#define PLLSS_SDM_SSC_STEP 0
152#define PLLSS_SDM_DIN 0
153#define PLLSS_MISC_DEFAULT ((PLLSS_MISC_KCP << 25) | \
154 (PLLSS_MISC_KVCO << 24) | \
155 PLLSS_MISC_SETUP)
156#define PLLSS_CFG_DEFAULT ((PLLSS_EN_SDM << 31) | \
157 (PLLSS_EN_SSC << 30) | \
158 (PLLSS_EN_DITHER2 << 29) | \
159 (PLLSS_EN_DITHER << 28) | \
160 (PLLSS_SDM_RESET) << 27 | \
161 (PLLSS_CLAMP << 22))
162#define PLLSS_CTRL1_DEFAULT \
163 ((PLLSS_SDM_SSC_MAX << 16) | PLLSS_SDM_SSC_MIN)
164#define PLLSS_CTRL2_DEFAULT \
165 ((PLLSS_SDM_SSC_STEP << 16) | PLLSS_SDM_DIN)
166#define PLLSS_LOCK_OVERRIDE BIT(24)
167#define PLLSS_REF_SRC_SEL_SHIFT 25
168#define PLLSS_REF_SRC_SEL_MASK (3 << PLLSS_REF_SRC_SEL_SHIFT)
169
124#define pll_readl(offset, p) readl_relaxed(p->clk_base + offset) 170#define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
125#define pll_readl_base(p) pll_readl(p->params->base_reg, p) 171#define pll_readl_base(p) pll_readl(p->params->base_reg, p)
126#define pll_readl_misc(p) pll_readl(p->params->misc_reg, p) 172#define pll_readl_misc(p) pll_readl(p->params->misc_reg, p)
@@ -134,7 +180,7 @@
134#define mask(w) ((1 << (w)) - 1) 180#define mask(w) ((1 << (w)) - 1)
135#define divm_mask(p) mask(p->params->div_nmp->divm_width) 181#define divm_mask(p) mask(p->params->div_nmp->divm_width)
136#define divn_mask(p) mask(p->params->div_nmp->divn_width) 182#define divn_mask(p) mask(p->params->div_nmp->divn_width)
137#define divp_mask(p) (p->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK : \ 183#define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\
138 mask(p->params->div_nmp->divp_width)) 184 mask(p->params->div_nmp->divp_width))
139 185
140#define divm_max(p) (divm_mask(p)) 186#define divm_max(p) (divm_mask(p))
@@ -154,10 +200,10 @@ static void clk_pll_enable_lock(struct tegra_clk_pll *pll)
154{ 200{
155 u32 val; 201 u32 val;
156 202
157 if (!(pll->flags & TEGRA_PLL_USE_LOCK)) 203 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK))
158 return; 204 return;
159 205
160 if (!(pll->flags & TEGRA_PLL_HAS_LOCK_ENABLE)) 206 if (!(pll->params->flags & TEGRA_PLL_HAS_LOCK_ENABLE))
161 return; 207 return;
162 208
163 val = pll_readl_misc(pll); 209 val = pll_readl_misc(pll);
@@ -171,13 +217,13 @@ static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll)
171 u32 val, lock_mask; 217 u32 val, lock_mask;
172 void __iomem *lock_addr; 218 void __iomem *lock_addr;
173 219
174 if (!(pll->flags & TEGRA_PLL_USE_LOCK)) { 220 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) {
175 udelay(pll->params->lock_delay); 221 udelay(pll->params->lock_delay);
176 return 0; 222 return 0;
177 } 223 }
178 224
179 lock_addr = pll->clk_base; 225 lock_addr = pll->clk_base;
180 if (pll->flags & TEGRA_PLL_LOCK_MISC) 226 if (pll->params->flags & TEGRA_PLL_LOCK_MISC)
181 lock_addr += pll->params->misc_reg; 227 lock_addr += pll->params->misc_reg;
182 else 228 else
183 lock_addr += pll->params->base_reg; 229 lock_addr += pll->params->base_reg;
@@ -204,7 +250,7 @@ static int clk_pll_is_enabled(struct clk_hw *hw)
204 struct tegra_clk_pll *pll = to_clk_pll(hw); 250 struct tegra_clk_pll *pll = to_clk_pll(hw);
205 u32 val; 251 u32 val;
206 252
207 if (pll->flags & TEGRA_PLLM) { 253 if (pll->params->flags & TEGRA_PLLM) {
208 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); 254 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
209 if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE) 255 if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)
210 return val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE ? 1 : 0; 256 return val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE ? 1 : 0;
@@ -223,12 +269,12 @@ static void _clk_pll_enable(struct clk_hw *hw)
223 clk_pll_enable_lock(pll); 269 clk_pll_enable_lock(pll);
224 270
225 val = pll_readl_base(pll); 271 val = pll_readl_base(pll);
226 if (pll->flags & TEGRA_PLL_BYPASS) 272 if (pll->params->flags & TEGRA_PLL_BYPASS)
227 val &= ~PLL_BASE_BYPASS; 273 val &= ~PLL_BASE_BYPASS;
228 val |= PLL_BASE_ENABLE; 274 val |= PLL_BASE_ENABLE;
229 pll_writel_base(val, pll); 275 pll_writel_base(val, pll);
230 276
231 if (pll->flags & TEGRA_PLLM) { 277 if (pll->params->flags & TEGRA_PLLM) {
232 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); 278 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
233 val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE; 279 val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
234 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE); 280 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
@@ -241,12 +287,12 @@ static void _clk_pll_disable(struct clk_hw *hw)
241 u32 val; 287 u32 val;
242 288
243 val = pll_readl_base(pll); 289 val = pll_readl_base(pll);
244 if (pll->flags & TEGRA_PLL_BYPASS) 290 if (pll->params->flags & TEGRA_PLL_BYPASS)
245 val &= ~PLL_BASE_BYPASS; 291 val &= ~PLL_BASE_BYPASS;
246 val &= ~PLL_BASE_ENABLE; 292 val &= ~PLL_BASE_ENABLE;
247 pll_writel_base(val, pll); 293 pll_writel_base(val, pll);
248 294
249 if (pll->flags & TEGRA_PLLM) { 295 if (pll->params->flags & TEGRA_PLLM) {
250 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); 296 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
251 val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE; 297 val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
252 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE); 298 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
@@ -326,7 +372,7 @@ static int _get_table_rate(struct clk_hw *hw,
326 struct tegra_clk_pll *pll = to_clk_pll(hw); 372 struct tegra_clk_pll *pll = to_clk_pll(hw);
327 struct tegra_clk_pll_freq_table *sel; 373 struct tegra_clk_pll_freq_table *sel;
328 374
329 for (sel = pll->freq_table; sel->input_rate != 0; sel++) 375 for (sel = pll->params->freq_table; sel->input_rate != 0; sel++)
330 if (sel->input_rate == parent_rate && 376 if (sel->input_rate == parent_rate &&
331 sel->output_rate == rate) 377 sel->output_rate == rate)
332 break; 378 break;
@@ -389,12 +435,11 @@ static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
389 if (cfg->m > divm_max(pll) || cfg->n > divn_max(pll) || 435 if (cfg->m > divm_max(pll) || cfg->n > divn_max(pll) ||
390 (1 << p_div) > divp_max(pll) 436 (1 << p_div) > divp_max(pll)
391 || cfg->output_rate > pll->params->vco_max) { 437 || cfg->output_rate > pll->params->vco_max) {
392 pr_err("%s: Failed to set %s rate %lu\n",
393 __func__, __clk_get_name(hw->clk), rate);
394 WARN_ON(1);
395 return -EINVAL; 438 return -EINVAL;
396 } 439 }
397 440
441 cfg->output_rate >>= p_div;
442
398 if (pll->params->pdiv_tohw) { 443 if (pll->params->pdiv_tohw) {
399 ret = _p_div_to_hw(hw, 1 << p_div); 444 ret = _p_div_to_hw(hw, 1 << p_div);
400 if (ret < 0) 445 if (ret < 0)
@@ -414,7 +459,7 @@ static void _update_pll_mnp(struct tegra_clk_pll *pll,
414 struct tegra_clk_pll_params *params = pll->params; 459 struct tegra_clk_pll_params *params = pll->params;
415 struct div_nmp *div_nmp = params->div_nmp; 460 struct div_nmp *div_nmp = params->div_nmp;
416 461
417 if ((pll->flags & TEGRA_PLLM) && 462 if ((params->flags & TEGRA_PLLM) &&
418 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) & 463 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
419 PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) { 464 PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {
420 val = pll_override_readl(params->pmc_divp_reg, pll); 465 val = pll_override_readl(params->pmc_divp_reg, pll);
@@ -450,7 +495,7 @@ static void _get_pll_mnp(struct tegra_clk_pll *pll,
450 struct tegra_clk_pll_params *params = pll->params; 495 struct tegra_clk_pll_params *params = pll->params;
451 struct div_nmp *div_nmp = params->div_nmp; 496 struct div_nmp *div_nmp = params->div_nmp;
452 497
453 if ((pll->flags & TEGRA_PLLM) && 498 if ((params->flags & TEGRA_PLLM) &&
454 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) & 499 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
455 PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) { 500 PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {
456 val = pll_override_readl(params->pmc_divp_reg, pll); 501 val = pll_override_readl(params->pmc_divp_reg, pll);
@@ -479,11 +524,11 @@ static void _update_pll_cpcon(struct tegra_clk_pll *pll,
479 val &= ~(PLL_MISC_CPCON_MASK << PLL_MISC_CPCON_SHIFT); 524 val &= ~(PLL_MISC_CPCON_MASK << PLL_MISC_CPCON_SHIFT);
480 val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT; 525 val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT;
481 526
482 if (pll->flags & TEGRA_PLL_SET_LFCON) { 527 if (pll->params->flags & TEGRA_PLL_SET_LFCON) {
483 val &= ~(PLL_MISC_LFCON_MASK << PLL_MISC_LFCON_SHIFT); 528 val &= ~(PLL_MISC_LFCON_MASK << PLL_MISC_LFCON_SHIFT);
484 if (cfg->n >= PLLDU_LFCON_SET_DIVN) 529 if (cfg->n >= PLLDU_LFCON_SET_DIVN)
485 val |= 1 << PLL_MISC_LFCON_SHIFT; 530 val |= 1 << PLL_MISC_LFCON_SHIFT;
486 } else if (pll->flags & TEGRA_PLL_SET_DCCON) { 531 } else if (pll->params->flags & TEGRA_PLL_SET_DCCON) {
487 val &= ~(1 << PLL_MISC_DCCON_SHIFT); 532 val &= ~(1 << PLL_MISC_DCCON_SHIFT);
488 if (rate >= (pll->params->vco_max >> 1)) 533 if (rate >= (pll->params->vco_max >> 1))
489 val |= 1 << PLL_MISC_DCCON_SHIFT; 534 val |= 1 << PLL_MISC_DCCON_SHIFT;
@@ -505,7 +550,7 @@ static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
505 550
506 _update_pll_mnp(pll, cfg); 551 _update_pll_mnp(pll, cfg);
507 552
508 if (pll->flags & TEGRA_PLL_HAS_CPCON) 553 if (pll->params->flags & TEGRA_PLL_HAS_CPCON)
509 _update_pll_cpcon(pll, cfg, rate); 554 _update_pll_cpcon(pll, cfg, rate);
510 555
511 if (state) { 556 if (state) {
@@ -524,11 +569,11 @@ static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
524 unsigned long flags = 0; 569 unsigned long flags = 0;
525 int ret = 0; 570 int ret = 0;
526 571
527 if (pll->flags & TEGRA_PLL_FIXED) { 572 if (pll->params->flags & TEGRA_PLL_FIXED) {
528 if (rate != pll->fixed_rate) { 573 if (rate != pll->params->fixed_rate) {
529 pr_err("%s: Can not change %s fixed rate %lu to %lu\n", 574 pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
530 __func__, __clk_get_name(hw->clk), 575 __func__, __clk_get_name(hw->clk),
531 pll->fixed_rate, rate); 576 pll->params->fixed_rate, rate);
532 return -EINVAL; 577 return -EINVAL;
533 } 578 }
534 return 0; 579 return 0;
@@ -536,6 +581,8 @@ static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
536 581
537 if (_get_table_rate(hw, &cfg, rate, parent_rate) && 582 if (_get_table_rate(hw, &cfg, rate, parent_rate) &&
538 _calc_rate(hw, &cfg, rate, parent_rate)) { 583 _calc_rate(hw, &cfg, rate, parent_rate)) {
584 pr_err("%s: Failed to set %s rate %lu\n", __func__,
585 __clk_get_name(hw->clk), rate);
539 WARN_ON(1); 586 WARN_ON(1);
540 return -EINVAL; 587 return -EINVAL;
541 } 588 }
@@ -559,18 +606,16 @@ static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
559 struct tegra_clk_pll *pll = to_clk_pll(hw); 606 struct tegra_clk_pll *pll = to_clk_pll(hw);
560 struct tegra_clk_pll_freq_table cfg; 607 struct tegra_clk_pll_freq_table cfg;
561 608
562 if (pll->flags & TEGRA_PLL_FIXED) 609 if (pll->params->flags & TEGRA_PLL_FIXED)
563 return pll->fixed_rate; 610 return pll->params->fixed_rate;
564 611
565 /* PLLM is used for memory; we do not change rate */ 612 /* PLLM is used for memory; we do not change rate */
566 if (pll->flags & TEGRA_PLLM) 613 if (pll->params->flags & TEGRA_PLLM)
567 return __clk_get_rate(hw->clk); 614 return __clk_get_rate(hw->clk);
568 615
569 if (_get_table_rate(hw, &cfg, rate, *prate) && 616 if (_get_table_rate(hw, &cfg, rate, *prate) &&
570 _calc_rate(hw, &cfg, rate, *prate)) { 617 _calc_rate(hw, &cfg, rate, *prate))
571 WARN_ON(1);
572 return -EINVAL; 618 return -EINVAL;
573 }
574 619
575 return cfg.output_rate; 620 return cfg.output_rate;
576} 621}
@@ -586,17 +631,19 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
586 631
587 val = pll_readl_base(pll); 632 val = pll_readl_base(pll);
588 633
589 if ((pll->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS)) 634 if ((pll->params->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS))
590 return parent_rate; 635 return parent_rate;
591 636
592 if ((pll->flags & TEGRA_PLL_FIXED) && !(val & PLL_BASE_OVERRIDE)) { 637 if ((pll->params->flags & TEGRA_PLL_FIXED) &&
638 !(val & PLL_BASE_OVERRIDE)) {
593 struct tegra_clk_pll_freq_table sel; 639 struct tegra_clk_pll_freq_table sel;
594 if (_get_table_rate(hw, &sel, pll->fixed_rate, parent_rate)) { 640 if (_get_table_rate(hw, &sel, pll->params->fixed_rate,
641 parent_rate)) {
595 pr_err("Clock %s has unknown fixed frequency\n", 642 pr_err("Clock %s has unknown fixed frequency\n",
596 __clk_get_name(hw->clk)); 643 __clk_get_name(hw->clk));
597 BUG(); 644 BUG();
598 } 645 }
599 return pll->fixed_rate; 646 return pll->params->fixed_rate;
600 } 647 }
601 648
602 _get_pll_mnp(pll, &cfg); 649 _get_pll_mnp(pll, &cfg);
@@ -664,7 +711,7 @@ static int clk_plle_enable(struct clk_hw *hw)
664 u32 val; 711 u32 val;
665 int err; 712 int err;
666 713
667 if (_get_table_rate(hw, &sel, pll->fixed_rate, input_rate)) 714 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
668 return -EINVAL; 715 return -EINVAL;
669 716
670 clk_pll_disable(hw); 717 clk_pll_disable(hw);
@@ -680,7 +727,7 @@ static int clk_plle_enable(struct clk_hw *hw)
680 return err; 727 return err;
681 } 728 }
682 729
683 if (pll->flags & TEGRA_PLLE_CONFIGURE) { 730 if (pll->params->flags & TEGRA_PLLE_CONFIGURE) {
684 /* configure dividers */ 731 /* configure dividers */
685 val = pll_readl_base(pll); 732 val = pll_readl_base(pll);
686 val &= ~(divm_mask(pll) | divn_mask(pll) | divp_mask(pll)); 733 val &= ~(divm_mask(pll) | divn_mask(pll) | divp_mask(pll));
@@ -744,7 +791,7 @@ const struct clk_ops tegra_clk_plle_ops = {
744 .enable = clk_plle_enable, 791 .enable = clk_plle_enable,
745}; 792};
746 793
747#ifdef CONFIG_ARCH_TEGRA_114_SOC 794#if defined(CONFIG_ARCH_TEGRA_114_SOC) || defined(CONFIG_ARCH_TEGRA_124_SOC)
748 795
749static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params, 796static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params,
750 unsigned long parent_rate) 797 unsigned long parent_rate)
@@ -755,6 +802,48 @@ static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params,
755 return 1; 802 return 1;
756} 803}
757 804
805static unsigned long _clip_vco_min(unsigned long vco_min,
806 unsigned long parent_rate)
807{
808 return DIV_ROUND_UP(vco_min, parent_rate) * parent_rate;
809}
810
811static int _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params,
812 void __iomem *clk_base,
813 unsigned long parent_rate)
814{
815 u32 val;
816 u32 step_a, step_b;
817
818 switch (parent_rate) {
819 case 12000000:
820 case 13000000:
821 case 26000000:
822 step_a = 0x2B;
823 step_b = 0x0B;
824 break;
825 case 16800000:
826 step_a = 0x1A;
827 step_b = 0x09;
828 break;
829 case 19200000:
830 step_a = 0x12;
831 step_b = 0x08;
832 break;
833 default:
834 pr_err("%s: Unexpected reference rate %lu\n",
835 __func__, parent_rate);
836 WARN_ON(1);
837 return -EINVAL;
838 }
839
840 val = step_a << pll_params->stepa_shift;
841 val |= step_b << pll_params->stepb_shift;
842 writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg);
843
844 return 0;
845}
846
758static int clk_pll_iddq_enable(struct clk_hw *hw) 847static int clk_pll_iddq_enable(struct clk_hw *hw)
759{ 848{
760 struct tegra_clk_pll *pll = to_clk_pll(hw); 849 struct tegra_clk_pll *pll = to_clk_pll(hw);
@@ -1173,7 +1262,7 @@ static int clk_plle_tegra114_enable(struct clk_hw *hw)
1173 unsigned long flags = 0; 1262 unsigned long flags = 0;
1174 unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk)); 1263 unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk));
1175 1264
1176 if (_get_table_rate(hw, &sel, pll->fixed_rate, input_rate)) 1265 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
1177 return -EINVAL; 1266 return -EINVAL;
1178 1267
1179 if (pll->lock) 1268 if (pll->lock)
@@ -1217,6 +1306,18 @@ static int clk_plle_tegra114_enable(struct clk_hw *hw)
1217 if (ret < 0) 1306 if (ret < 0)
1218 goto out; 1307 goto out;
1219 1308
1309 val = pll_readl(PLLE_SS_CTRL, pll);
1310 val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
1311 val &= ~PLLE_SS_COEFFICIENTS_MASK;
1312 val |= PLLE_SS_COEFFICIENTS_VAL;
1313 pll_writel(val, PLLE_SS_CTRL, pll);
1314 val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
1315 pll_writel(val, PLLE_SS_CTRL, pll);
1316 udelay(1);
1317 val &= ~PLLE_SS_CNTL_INTERP_RESET;
1318 pll_writel(val, PLLE_SS_CTRL, pll);
1319 udelay(1);
1320
1220 /* TODO: enable hw control of xusb brick pll */ 1321 /* TODO: enable hw control of xusb brick pll */
1221 1322
1222out: 1323out:
@@ -1248,9 +1349,8 @@ static void clk_plle_tegra114_disable(struct clk_hw *hw)
1248#endif 1349#endif
1249 1350
1250static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base, 1351static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base,
1251 void __iomem *pmc, unsigned long fixed_rate, 1352 void __iomem *pmc, struct tegra_clk_pll_params *pll_params,
1252 struct tegra_clk_pll_params *pll_params, u32 pll_flags, 1353 spinlock_t *lock)
1253 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock)
1254{ 1354{
1255 struct tegra_clk_pll *pll; 1355 struct tegra_clk_pll *pll;
1256 1356
@@ -1261,10 +1361,7 @@ static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base,
1261 pll->clk_base = clk_base; 1361 pll->clk_base = clk_base;
1262 pll->pmc = pmc; 1362 pll->pmc = pmc;
1263 1363
1264 pll->freq_table = freq_table;
1265 pll->params = pll_params; 1364 pll->params = pll_params;
1266 pll->fixed_rate = fixed_rate;
1267 pll->flags = pll_flags;
1268 pll->lock = lock; 1365 pll->lock = lock;
1269 1366
1270 if (!pll_params->div_nmp) 1367 if (!pll_params->div_nmp)
@@ -1293,17 +1390,15 @@ static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll,
1293 1390
1294struct clk *tegra_clk_register_pll(const char *name, const char *parent_name, 1391struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
1295 void __iomem *clk_base, void __iomem *pmc, 1392 void __iomem *clk_base, void __iomem *pmc,
1296 unsigned long flags, unsigned long fixed_rate, 1393 unsigned long flags, struct tegra_clk_pll_params *pll_params,
1297 struct tegra_clk_pll_params *pll_params, u32 pll_flags, 1394 spinlock_t *lock)
1298 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock)
1299{ 1395{
1300 struct tegra_clk_pll *pll; 1396 struct tegra_clk_pll *pll;
1301 struct clk *clk; 1397 struct clk *clk;
1302 1398
1303 pll_flags |= TEGRA_PLL_BYPASS; 1399 pll_params->flags |= TEGRA_PLL_BYPASS;
1304 pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE; 1400 pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1305 pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags, 1401 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1306 freq_table, lock);
1307 if (IS_ERR(pll)) 1402 if (IS_ERR(pll))
1308 return ERR_CAST(pll); 1403 return ERR_CAST(pll);
1309 1404
@@ -1317,17 +1412,15 @@ struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
1317 1412
1318struct clk *tegra_clk_register_plle(const char *name, const char *parent_name, 1413struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
1319 void __iomem *clk_base, void __iomem *pmc, 1414 void __iomem *clk_base, void __iomem *pmc,
1320 unsigned long flags, unsigned long fixed_rate, 1415 unsigned long flags, struct tegra_clk_pll_params *pll_params,
1321 struct tegra_clk_pll_params *pll_params, u32 pll_flags, 1416 spinlock_t *lock)
1322 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock)
1323{ 1417{
1324 struct tegra_clk_pll *pll; 1418 struct tegra_clk_pll *pll;
1325 struct clk *clk; 1419 struct clk *clk;
1326 1420
1327 pll_flags |= TEGRA_PLL_LOCK_MISC | TEGRA_PLL_BYPASS; 1421 pll_params->flags |= TEGRA_PLL_LOCK_MISC | TEGRA_PLL_BYPASS;
1328 pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE; 1422 pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1329 pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags, 1423 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1330 freq_table, lock);
1331 if (IS_ERR(pll)) 1424 if (IS_ERR(pll))
1332 return ERR_CAST(pll); 1425 return ERR_CAST(pll);
1333 1426
@@ -1339,7 +1432,7 @@ struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
1339 return clk; 1432 return clk;
1340} 1433}
1341 1434
1342#ifdef CONFIG_ARCH_TEGRA_114_SOC 1435#if defined(CONFIG_ARCH_TEGRA_114_SOC) || defined(CONFIG_ARCH_TEGRA_124_SOC)
1343const struct clk_ops tegra_clk_pllxc_ops = { 1436const struct clk_ops tegra_clk_pllxc_ops = {
1344 .is_enabled = clk_pll_is_enabled, 1437 .is_enabled = clk_pll_is_enabled,
1345 .enable = clk_pll_iddq_enable, 1438 .enable = clk_pll_iddq_enable,
@@ -1386,21 +1479,46 @@ const struct clk_ops tegra_clk_plle_tegra114_ops = {
1386 1479
1387struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name, 1480struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
1388 void __iomem *clk_base, void __iomem *pmc, 1481 void __iomem *clk_base, void __iomem *pmc,
1389 unsigned long flags, unsigned long fixed_rate, 1482 unsigned long flags,
1390 struct tegra_clk_pll_params *pll_params, 1483 struct tegra_clk_pll_params *pll_params,
1391 u32 pll_flags,
1392 struct tegra_clk_pll_freq_table *freq_table,
1393 spinlock_t *lock) 1484 spinlock_t *lock)
1394{ 1485{
1395 struct tegra_clk_pll *pll; 1486 struct tegra_clk_pll *pll;
1396 struct clk *clk; 1487 struct clk *clk, *parent;
1488 unsigned long parent_rate;
1489 int err;
1490 u32 val, val_iddq;
1491
1492 parent = __clk_lookup(parent_name);
1493 if (!parent) {
1494 WARN(1, "parent clk %s of %s must be registered first\n",
1495 name, parent_name);
1496 return ERR_PTR(-EINVAL);
1497 }
1397 1498
1398 if (!pll_params->pdiv_tohw) 1499 if (!pll_params->pdiv_tohw)
1399 return ERR_PTR(-EINVAL); 1500 return ERR_PTR(-EINVAL);
1400 1501
1401 pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE; 1502 parent_rate = __clk_get_rate(parent);
1402 pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags, 1503
1403 freq_table, lock); 1504 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1505
1506 err = _setup_dynamic_ramp(pll_params, clk_base, parent_rate);
1507 if (err)
1508 return ERR_PTR(err);
1509
1510 val = readl_relaxed(clk_base + pll_params->base_reg);
1511 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
1512
1513 if (val & PLL_BASE_ENABLE)
1514 WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx));
1515 else {
1516 val_iddq |= BIT(pll_params->iddq_bit_idx);
1517 writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg);
1518 }
1519
1520 pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1521 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1404 if (IS_ERR(pll)) 1522 if (IS_ERR(pll))
1405 return ERR_CAST(pll); 1523 return ERR_CAST(pll);
1406 1524
@@ -1414,19 +1532,19 @@ struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
1414 1532
1415struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name, 1533struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
1416 void __iomem *clk_base, void __iomem *pmc, 1534 void __iomem *clk_base, void __iomem *pmc,
1417 unsigned long flags, unsigned long fixed_rate, 1535 unsigned long flags,
1418 struct tegra_clk_pll_params *pll_params, 1536 struct tegra_clk_pll_params *pll_params,
1419 u32 pll_flags,
1420 struct tegra_clk_pll_freq_table *freq_table,
1421 spinlock_t *lock, unsigned long parent_rate) 1537 spinlock_t *lock, unsigned long parent_rate)
1422{ 1538{
1423 u32 val; 1539 u32 val;
1424 struct tegra_clk_pll *pll; 1540 struct tegra_clk_pll *pll;
1425 struct clk *clk; 1541 struct clk *clk;
1426 1542
1427 pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_LOCK_MISC; 1543 pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_LOCK_MISC;
1428 pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags, 1544
1429 freq_table, lock); 1545 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1546
1547 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1430 if (IS_ERR(pll)) 1548 if (IS_ERR(pll))
1431 return ERR_CAST(pll); 1549 return ERR_CAST(pll);
1432 1550
@@ -1461,23 +1579,32 @@ struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
1461 1579
1462struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name, 1580struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
1463 void __iomem *clk_base, void __iomem *pmc, 1581 void __iomem *clk_base, void __iomem *pmc,
1464 unsigned long flags, unsigned long fixed_rate, 1582 unsigned long flags,
1465 struct tegra_clk_pll_params *pll_params, 1583 struct tegra_clk_pll_params *pll_params,
1466 u32 pll_flags,
1467 struct tegra_clk_pll_freq_table *freq_table,
1468 spinlock_t *lock) 1584 spinlock_t *lock)
1469{ 1585{
1470 struct tegra_clk_pll *pll; 1586 struct tegra_clk_pll *pll;
1471 struct clk *clk; 1587 struct clk *clk, *parent;
1588 unsigned long parent_rate;
1472 1589
1473 if (!pll_params->pdiv_tohw) 1590 if (!pll_params->pdiv_tohw)
1474 return ERR_PTR(-EINVAL); 1591 return ERR_PTR(-EINVAL);
1475 1592
1476 pll_flags |= TEGRA_PLL_BYPASS; 1593 parent = __clk_lookup(parent_name);
1477 pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE; 1594 if (!parent) {
1478 pll_flags |= TEGRA_PLLM; 1595 WARN(1, "parent clk %s of %s must be registered first\n",
1479 pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags, 1596 name, parent_name);
1480 freq_table, lock); 1597 return ERR_PTR(-EINVAL);
1598 }
1599
1600 parent_rate = __clk_get_rate(parent);
1601
1602 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1603
1604 pll_params->flags |= TEGRA_PLL_BYPASS;
1605 pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1606 pll_params->flags |= TEGRA_PLLM;
1607 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1481 if (IS_ERR(pll)) 1608 if (IS_ERR(pll))
1482 return ERR_CAST(pll); 1609 return ERR_CAST(pll);
1483 1610
@@ -1491,10 +1618,8 @@ struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
1491 1618
1492struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name, 1619struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
1493 void __iomem *clk_base, void __iomem *pmc, 1620 void __iomem *clk_base, void __iomem *pmc,
1494 unsigned long flags, unsigned long fixed_rate, 1621 unsigned long flags,
1495 struct tegra_clk_pll_params *pll_params, 1622 struct tegra_clk_pll_params *pll_params,
1496 u32 pll_flags,
1497 struct tegra_clk_pll_freq_table *freq_table,
1498 spinlock_t *lock) 1623 spinlock_t *lock)
1499{ 1624{
1500 struct clk *parent, *clk; 1625 struct clk *parent, *clk;
@@ -1507,20 +1632,21 @@ struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
1507 return ERR_PTR(-EINVAL); 1632 return ERR_PTR(-EINVAL);
1508 1633
1509 parent = __clk_lookup(parent_name); 1634 parent = __clk_lookup(parent_name);
1510 if (IS_ERR(parent)) { 1635 if (!parent) {
1511 WARN(1, "parent clk %s of %s must be registered first\n", 1636 WARN(1, "parent clk %s of %s must be registered first\n",
1512 name, parent_name); 1637 name, parent_name);
1513 return ERR_PTR(-EINVAL); 1638 return ERR_PTR(-EINVAL);
1514 } 1639 }
1515 1640
1516 pll_flags |= TEGRA_PLL_BYPASS; 1641 parent_rate = __clk_get_rate(parent);
1517 pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags, 1642
1518 freq_table, lock); 1643 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1644
1645 pll_params->flags |= TEGRA_PLL_BYPASS;
1646 pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1519 if (IS_ERR(pll)) 1647 if (IS_ERR(pll))
1520 return ERR_CAST(pll); 1648 return ERR_CAST(pll);
1521 1649
1522 parent_rate = __clk_get_rate(parent);
1523
1524 /* 1650 /*
1525 * Most of PLLC register fields are shadowed, and can not be read 1651 * Most of PLLC register fields are shadowed, and can not be read
1526 * directly from PLL h/w. Hence, actual PLLC boot state is unknown. 1652 * directly from PLL h/w. Hence, actual PLLC boot state is unknown.
@@ -1567,17 +1693,15 @@ struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
1567struct clk *tegra_clk_register_plle_tegra114(const char *name, 1693struct clk *tegra_clk_register_plle_tegra114(const char *name,
1568 const char *parent_name, 1694 const char *parent_name,
1569 void __iomem *clk_base, unsigned long flags, 1695 void __iomem *clk_base, unsigned long flags,
1570 unsigned long fixed_rate,
1571 struct tegra_clk_pll_params *pll_params, 1696 struct tegra_clk_pll_params *pll_params,
1572 struct tegra_clk_pll_freq_table *freq_table,
1573 spinlock_t *lock) 1697 spinlock_t *lock)
1574{ 1698{
1575 struct tegra_clk_pll *pll; 1699 struct tegra_clk_pll *pll;
1576 struct clk *clk; 1700 struct clk *clk;
1577 u32 val, val_aux; 1701 u32 val, val_aux;
1578 1702
1579 pll = _tegra_init_pll(clk_base, NULL, fixed_rate, pll_params, 1703 pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE;
1580 TEGRA_PLL_HAS_LOCK_ENABLE, freq_table, lock); 1704 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
1581 if (IS_ERR(pll)) 1705 if (IS_ERR(pll))
1582 return ERR_CAST(pll); 1706 return ERR_CAST(pll);
1583 1707
@@ -1587,11 +1711,13 @@ struct clk *tegra_clk_register_plle_tegra114(const char *name,
1587 val_aux = pll_readl(pll_params->aux_reg, pll); 1711 val_aux = pll_readl(pll_params->aux_reg, pll);
1588 1712
1589 if (val & PLL_BASE_ENABLE) { 1713 if (val & PLL_BASE_ENABLE) {
1590 if (!(val_aux & PLLE_AUX_PLLRE_SEL)) 1714 if ((val_aux & PLLE_AUX_PLLRE_SEL) ||
1715 (val_aux & PLLE_AUX_PLLP_SEL))
1591 WARN(1, "pll_e enabled with unsupported parent %s\n", 1716 WARN(1, "pll_e enabled with unsupported parent %s\n",
1592 (val & PLLE_AUX_PLLP_SEL) ? "pllp_out0" : "pll_ref"); 1717 (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" :
1718 "pll_re_vco");
1593 } else { 1719 } else {
1594 val_aux |= PLLE_AUX_PLLRE_SEL; 1720 val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL);
1595 pll_writel(val, pll_params->aux_reg, pll); 1721 pll_writel(val, pll_params->aux_reg, pll);
1596 } 1722 }
1597 1723
@@ -1603,3 +1729,92 @@ struct clk *tegra_clk_register_plle_tegra114(const char *name,
1603 return clk; 1729 return clk;
1604} 1730}
1605#endif 1731#endif
1732
1733#ifdef CONFIG_ARCH_TEGRA_124_SOC
1734const struct clk_ops tegra_clk_pllss_ops = {
1735 .is_enabled = clk_pll_is_enabled,
1736 .enable = clk_pll_iddq_enable,
1737 .disable = clk_pll_iddq_disable,
1738 .recalc_rate = clk_pll_recalc_rate,
1739 .round_rate = clk_pll_ramp_round_rate,
1740 .set_rate = clk_pllxc_set_rate,
1741};
1742
1743struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,
1744 void __iomem *clk_base, unsigned long flags,
1745 struct tegra_clk_pll_params *pll_params,
1746 spinlock_t *lock)
1747{
1748 struct tegra_clk_pll *pll;
1749 struct clk *clk, *parent;
1750 struct tegra_clk_pll_freq_table cfg;
1751 unsigned long parent_rate;
1752 u32 val;
1753 int i;
1754
1755 if (!pll_params->div_nmp)
1756 return ERR_PTR(-EINVAL);
1757
1758 parent = __clk_lookup(parent_name);
1759 if (!parent) {
1760 WARN(1, "parent clk %s of %s must be registered first\n",
1761 name, parent_name);
1762 return ERR_PTR(-EINVAL);
1763 }
1764
1765 pll_params->flags = TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_USE_LOCK;
1766 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
1767 if (IS_ERR(pll))
1768 return ERR_CAST(pll);
1769
1770 val = pll_readl_base(pll);
1771 val &= ~PLLSS_REF_SRC_SEL_MASK;
1772 pll_writel_base(val, pll);
1773
1774 parent_rate = __clk_get_rate(parent);
1775
1776 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1777
1778 /* initialize PLL to minimum rate */
1779
1780 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
1781 cfg.n = cfg.m * pll_params->vco_min / parent_rate;
1782
1783 for (i = 0; pll_params->pdiv_tohw[i].pdiv; i++)
1784 ;
1785 if (!i) {
1786 kfree(pll);
1787 return ERR_PTR(-EINVAL);
1788 }
1789
1790 cfg.p = pll_params->pdiv_tohw[i-1].hw_val;
1791
1792 _update_pll_mnp(pll, &cfg);
1793
1794 pll_writel_misc(PLLSS_MISC_DEFAULT, pll);
1795 pll_writel(PLLSS_CFG_DEFAULT, pll_params->ext_misc_reg[0], pll);
1796 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[1], pll);
1797 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll);
1798
1799 val = pll_readl_base(pll);
1800 if (val & PLL_BASE_ENABLE) {
1801 if (val & BIT(pll_params->iddq_bit_idx)) {
1802 WARN(1, "%s is on but IDDQ set\n", name);
1803 kfree(pll);
1804 return ERR_PTR(-EINVAL);
1805 }
1806 } else
1807 val |= BIT(pll_params->iddq_bit_idx);
1808
1809 val &= ~PLLSS_LOCK_OVERRIDE;
1810 pll_writel_base(val, pll);
1811
1812 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1813 &tegra_clk_pllss_ops);
1814
1815 if (IS_ERR(clk))
1816 kfree(pll);
1817
1818 return clk;
1819}
1820#endif
diff --git a/drivers/clk/tegra/clk-tegra-audio.c b/drivers/clk/tegra/clk-tegra-audio.c
new file mode 100644
index 000000000000..5c38aab2c5b8
--- /dev/null
+++ b/drivers/clk/tegra/clk-tegra-audio.c
@@ -0,0 +1,215 @@
1/*
2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/io.h>
18#include <linux/clk.h>
19#include <linux/clk-provider.h>
20#include <linux/of.h>
21#include <linux/of_address.h>
22#include <linux/delay.h>
23#include <linux/export.h>
24#include <linux/clk/tegra.h>
25
26#include "clk.h"
27#include "clk-id.h"
28
29#define AUDIO_SYNC_CLK_I2S0 0x4a0
30#define AUDIO_SYNC_CLK_I2S1 0x4a4
31#define AUDIO_SYNC_CLK_I2S2 0x4a8
32#define AUDIO_SYNC_CLK_I2S3 0x4ac
33#define AUDIO_SYNC_CLK_I2S4 0x4b0
34#define AUDIO_SYNC_CLK_SPDIF 0x4b4
35
36#define AUDIO_SYNC_DOUBLER 0x49c
37
38#define PLLA_OUT 0xb4
39
40struct tegra_sync_source_initdata {
41 char *name;
42 unsigned long rate;
43 unsigned long max_rate;
44 int clk_id;
45};
46
47#define SYNC(_name) \
48 {\
49 .name = #_name,\
50 .rate = 24000000,\
51 .max_rate = 24000000,\
52 .clk_id = tegra_clk_ ## _name,\
53 }
54
55struct tegra_audio_clk_initdata {
56 char *gate_name;
57 char *mux_name;
58 u32 offset;
59 int gate_clk_id;
60 int mux_clk_id;
61};
62
63#define AUDIO(_name, _offset) \
64 {\
65 .gate_name = #_name,\
66 .mux_name = #_name"_mux",\
67 .offset = _offset,\
68 .gate_clk_id = tegra_clk_ ## _name,\
69 .mux_clk_id = tegra_clk_ ## _name ## _mux,\
70 }
71
72struct tegra_audio2x_clk_initdata {
73 char *parent;
74 char *gate_name;
75 char *name_2x;
76 char *div_name;
77 int clk_id;
78 int clk_num;
79 u8 div_offset;
80};
81
82#define AUDIO2X(_name, _num, _offset) \
83 {\
84 .parent = #_name,\
85 .gate_name = #_name"_2x",\
86 .name_2x = #_name"_doubler",\
87 .div_name = #_name"_div",\
88 .clk_id = tegra_clk_ ## _name ## _2x,\
89 .clk_num = _num,\
90 .div_offset = _offset,\
91 }
92
93static DEFINE_SPINLOCK(clk_doubler_lock);
94
95static const char *mux_audio_sync_clk[] = { "spdif_in_sync", "i2s0_sync",
96 "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync",
97};
98
99static struct tegra_sync_source_initdata sync_source_clks[] __initdata = {
100 SYNC(spdif_in_sync),
101 SYNC(i2s0_sync),
102 SYNC(i2s1_sync),
103 SYNC(i2s2_sync),
104 SYNC(i2s3_sync),
105 SYNC(i2s4_sync),
106 SYNC(vimclk_sync),
107};
108
109static struct tegra_audio_clk_initdata audio_clks[] = {
110 AUDIO(audio0, AUDIO_SYNC_CLK_I2S0),
111 AUDIO(audio1, AUDIO_SYNC_CLK_I2S1),
112 AUDIO(audio2, AUDIO_SYNC_CLK_I2S2),
113 AUDIO(audio3, AUDIO_SYNC_CLK_I2S3),
114 AUDIO(audio4, AUDIO_SYNC_CLK_I2S4),
115 AUDIO(spdif, AUDIO_SYNC_CLK_SPDIF),
116};
117
118static struct tegra_audio2x_clk_initdata audio2x_clks[] = {
119 AUDIO2X(audio0, 113, 24),
120 AUDIO2X(audio1, 114, 25),
121 AUDIO2X(audio2, 115, 26),
122 AUDIO2X(audio3, 116, 27),
123 AUDIO2X(audio4, 117, 28),
124 AUDIO2X(spdif, 118, 29),
125};
126
127void __init tegra_audio_clk_init(void __iomem *clk_base,
128 void __iomem *pmc_base, struct tegra_clk *tegra_clks,
129 struct tegra_clk_pll_params *pll_a_params)
130{
131 struct clk *clk;
132 struct clk **dt_clk;
133 int i;
134
135 /* PLLA */
136 dt_clk = tegra_lookup_dt_id(tegra_clk_pll_a, tegra_clks);
137 if (dt_clk) {
138 clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base,
139 pmc_base, 0, pll_a_params, NULL);
140 *dt_clk = clk;
141 }
142
143 /* PLLA_OUT0 */
144 dt_clk = tegra_lookup_dt_id(tegra_clk_pll_a_out0, tegra_clks);
145 if (dt_clk) {
146 clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a",
147 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
148 8, 8, 1, NULL);
149 clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div",
150 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED |
151 CLK_SET_RATE_PARENT, 0, NULL);
152 *dt_clk = clk;
153 }
154
155 for (i = 0; i < ARRAY_SIZE(sync_source_clks); i++) {
156 struct tegra_sync_source_initdata *data;
157
158 data = &sync_source_clks[i];
159
160 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);
161 if (!dt_clk)
162 continue;
163
164 clk = tegra_clk_register_sync_source(data->name,
165 data->rate, data->max_rate);
166 *dt_clk = clk;
167 }
168
169 for (i = 0; i < ARRAY_SIZE(audio_clks); i++) {
170 struct tegra_audio_clk_initdata *data;
171
172 data = &audio_clks[i];
173 dt_clk = tegra_lookup_dt_id(data->mux_clk_id, tegra_clks);
174
175 if (!dt_clk)
176 continue;
177 clk = clk_register_mux(NULL, data->mux_name, mux_audio_sync_clk,
178 ARRAY_SIZE(mux_audio_sync_clk),
179 CLK_SET_RATE_NO_REPARENT,
180 clk_base + data->offset, 0, 3, 0,
181 NULL);
182 *dt_clk = clk;
183
184 dt_clk = tegra_lookup_dt_id(data->gate_clk_id, tegra_clks);
185 if (!dt_clk)
186 continue;
187
188 clk = clk_register_gate(NULL, data->gate_name, data->mux_name,
189 0, clk_base + data->offset, 4,
190 CLK_GATE_SET_TO_DISABLE, NULL);
191 *dt_clk = clk;
192 }
193
194 for (i = 0; i < ARRAY_SIZE(audio2x_clks); i++) {
195 struct tegra_audio2x_clk_initdata *data;
196
197 data = &audio2x_clks[i];
198 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);
199 if (!dt_clk)
200 continue;
201
202 clk = clk_register_fixed_factor(NULL, data->name_2x,
203 data->parent, CLK_SET_RATE_PARENT, 2, 1);
204 clk = tegra_clk_register_divider(data->div_name,
205 data->name_2x, clk_base + AUDIO_SYNC_DOUBLER,
206 0, 0, data->div_offset, 1, 0,
207 &clk_doubler_lock);
208 clk = tegra_clk_register_periph_gate(data->gate_name,
209 data->div_name, TEGRA_PERIPH_NO_RESET,
210 clk_base, CLK_SET_RATE_PARENT, data->clk_num,
211 periph_clk_enb_refcnt);
212 *dt_clk = clk;
213 }
214}
215
diff --git a/drivers/clk/tegra/clk-tegra-fixed.c b/drivers/clk/tegra/clk-tegra-fixed.c
new file mode 100644
index 000000000000..f3b773833429
--- /dev/null
+++ b/drivers/clk/tegra/clk-tegra-fixed.c
@@ -0,0 +1,111 @@
1/*
2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/io.h>
18#include <linux/clk.h>
19#include <linux/clk-provider.h>
20#include <linux/of.h>
21#include <linux/of_address.h>
22#include <linux/delay.h>
23#include <linux/export.h>
24#include <linux/clk/tegra.h>
25
26#include "clk.h"
27#include "clk-id.h"
28
29#define OSC_CTRL 0x50
30#define OSC_CTRL_OSC_FREQ_SHIFT 28
31#define OSC_CTRL_PLL_REF_DIV_SHIFT 26
32
33int __init tegra_osc_clk_init(void __iomem *clk_base,
34 struct tegra_clk *tegra_clks,
35 unsigned long *input_freqs, int num,
36 unsigned long *osc_freq,
37 unsigned long *pll_ref_freq)
38{
39 struct clk *clk;
40 struct clk **dt_clk;
41 u32 val, pll_ref_div;
42 unsigned osc_idx;
43
44 val = readl_relaxed(clk_base + OSC_CTRL);
45 osc_idx = val >> OSC_CTRL_OSC_FREQ_SHIFT;
46
47 if (osc_idx < num)
48 *osc_freq = input_freqs[osc_idx];
49 else
50 *osc_freq = 0;
51
52 if (!*osc_freq) {
53 WARN_ON(1);
54 return -EINVAL;
55 }
56
57 dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m, tegra_clks);
58 if (!dt_clk)
59 return 0;
60
61 clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT,
62 *osc_freq);
63 *dt_clk = clk;
64
65 /* pll_ref */
66 val = (val >> OSC_CTRL_PLL_REF_DIV_SHIFT) & 3;
67 pll_ref_div = 1 << val;
68 dt_clk = tegra_lookup_dt_id(tegra_clk_pll_ref, tegra_clks);
69 if (!dt_clk)
70 return 0;
71
72 clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m",
73 0, 1, pll_ref_div);
74 *dt_clk = clk;
75
76 if (pll_ref_freq)
77 *pll_ref_freq = *osc_freq / pll_ref_div;
78
79 return 0;
80}
81
82void __init tegra_fixed_clk_init(struct tegra_clk *tegra_clks)
83{
84 struct clk *clk;
85 struct clk **dt_clk;
86
87 /* clk_32k */
88 dt_clk = tegra_lookup_dt_id(tegra_clk_clk_32k, tegra_clks);
89 if (dt_clk) {
90 clk = clk_register_fixed_rate(NULL, "clk_32k", NULL,
91 CLK_IS_ROOT, 32768);
92 *dt_clk = clk;
93 }
94
95 /* clk_m_div2 */
96 dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m_div2, tegra_clks);
97 if (dt_clk) {
98 clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m",
99 CLK_SET_RATE_PARENT, 1, 2);
100 *dt_clk = clk;
101 }
102
103 /* clk_m_div4 */
104 dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m_div4, tegra_clks);
105 if (dt_clk) {
106 clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m",
107 CLK_SET_RATE_PARENT, 1, 4);
108 *dt_clk = clk;
109 }
110}
111
diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c
new file mode 100644
index 000000000000..5c35885f4a7c
--- /dev/null
+++ b/drivers/clk/tegra/clk-tegra-periph.c
@@ -0,0 +1,674 @@
1/*
2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/io.h>
18#include <linux/clk.h>
19#include <linux/clk-provider.h>
20#include <linux/clkdev.h>
21#include <linux/of.h>
22#include <linux/of_address.h>
23#include <linux/delay.h>
24#include <linux/export.h>
25#include <linux/clk/tegra.h>
26
27#include "clk.h"
28#include "clk-id.h"
29
30#define CLK_SOURCE_I2S0 0x1d8
31#define CLK_SOURCE_I2S1 0x100
32#define CLK_SOURCE_I2S2 0x104
33#define CLK_SOURCE_NDFLASH 0x160
34#define CLK_SOURCE_I2S3 0x3bc
35#define CLK_SOURCE_I2S4 0x3c0
36#define CLK_SOURCE_SPDIF_OUT 0x108
37#define CLK_SOURCE_SPDIF_IN 0x10c
38#define CLK_SOURCE_PWM 0x110
39#define CLK_SOURCE_ADX 0x638
40#define CLK_SOURCE_ADX1 0x670
41#define CLK_SOURCE_AMX 0x63c
42#define CLK_SOURCE_AMX1 0x674
43#define CLK_SOURCE_HDA 0x428
44#define CLK_SOURCE_HDA2CODEC_2X 0x3e4
45#define CLK_SOURCE_SBC1 0x134
46#define CLK_SOURCE_SBC2 0x118
47#define CLK_SOURCE_SBC3 0x11c
48#define CLK_SOURCE_SBC4 0x1b4
49#define CLK_SOURCE_SBC5 0x3c8
50#define CLK_SOURCE_SBC6 0x3cc
51#define CLK_SOURCE_SATA_OOB 0x420
52#define CLK_SOURCE_SATA 0x424
53#define CLK_SOURCE_NDSPEED 0x3f8
54#define CLK_SOURCE_VFIR 0x168
55#define CLK_SOURCE_SDMMC1 0x150
56#define CLK_SOURCE_SDMMC2 0x154
57#define CLK_SOURCE_SDMMC3 0x1bc
58#define CLK_SOURCE_SDMMC4 0x164
59#define CLK_SOURCE_CVE 0x140
60#define CLK_SOURCE_TVO 0x188
61#define CLK_SOURCE_TVDAC 0x194
62#define CLK_SOURCE_VDE 0x1c8
63#define CLK_SOURCE_CSITE 0x1d4
64#define CLK_SOURCE_LA 0x1f8
65#define CLK_SOURCE_TRACE 0x634
66#define CLK_SOURCE_OWR 0x1cc
67#define CLK_SOURCE_NOR 0x1d0
68#define CLK_SOURCE_MIPI 0x174
69#define CLK_SOURCE_I2C1 0x124
70#define CLK_SOURCE_I2C2 0x198
71#define CLK_SOURCE_I2C3 0x1b8
72#define CLK_SOURCE_I2C4 0x3c4
73#define CLK_SOURCE_I2C5 0x128
74#define CLK_SOURCE_I2C6 0x65c
75#define CLK_SOURCE_UARTA 0x178
76#define CLK_SOURCE_UARTB 0x17c
77#define CLK_SOURCE_UARTC 0x1a0
78#define CLK_SOURCE_UARTD 0x1c0
79#define CLK_SOURCE_UARTE 0x1c4
80#define CLK_SOURCE_3D 0x158
81#define CLK_SOURCE_2D 0x15c
82#define CLK_SOURCE_MPE 0x170
83#define CLK_SOURCE_UARTE 0x1c4
84#define CLK_SOURCE_VI_SENSOR 0x1a8
85#define CLK_SOURCE_VI 0x148
86#define CLK_SOURCE_EPP 0x16c
87#define CLK_SOURCE_MSENC 0x1f0
88#define CLK_SOURCE_TSEC 0x1f4
89#define CLK_SOURCE_HOST1X 0x180
90#define CLK_SOURCE_HDMI 0x18c
91#define CLK_SOURCE_DISP1 0x138
92#define CLK_SOURCE_DISP2 0x13c
93#define CLK_SOURCE_CILAB 0x614
94#define CLK_SOURCE_CILCD 0x618
95#define CLK_SOURCE_CILE 0x61c
96#define CLK_SOURCE_DSIALP 0x620
97#define CLK_SOURCE_DSIBLP 0x624
98#define CLK_SOURCE_TSENSOR 0x3b8
99#define CLK_SOURCE_D_AUDIO 0x3d0
100#define CLK_SOURCE_DAM0 0x3d8
101#define CLK_SOURCE_DAM1 0x3dc
102#define CLK_SOURCE_DAM2 0x3e0
103#define CLK_SOURCE_ACTMON 0x3e8
104#define CLK_SOURCE_EXTERN1 0x3ec
105#define CLK_SOURCE_EXTERN2 0x3f0
106#define CLK_SOURCE_EXTERN3 0x3f4
107#define CLK_SOURCE_I2CSLOW 0x3fc
108#define CLK_SOURCE_SE 0x42c
109#define CLK_SOURCE_MSELECT 0x3b4
110#define CLK_SOURCE_DFLL_REF 0x62c
111#define CLK_SOURCE_DFLL_SOC 0x630
112#define CLK_SOURCE_SOC_THERM 0x644
113#define CLK_SOURCE_XUSB_HOST_SRC 0x600
114#define CLK_SOURCE_XUSB_FALCON_SRC 0x604
115#define CLK_SOURCE_XUSB_FS_SRC 0x608
116#define CLK_SOURCE_XUSB_SS_SRC 0x610
117#define CLK_SOURCE_XUSB_DEV_SRC 0x60c
118#define CLK_SOURCE_ISP 0x144
119#define CLK_SOURCE_SOR0 0x414
120#define CLK_SOURCE_DPAUX 0x418
121#define CLK_SOURCE_SATA_OOB 0x420
122#define CLK_SOURCE_SATA 0x424
123#define CLK_SOURCE_ENTROPY 0x628
124#define CLK_SOURCE_VI_SENSOR2 0x658
125#define CLK_SOURCE_HDMI_AUDIO 0x668
126#define CLK_SOURCE_VIC03 0x678
127#define CLK_SOURCE_CLK72MHZ 0x66c
128
129#define MASK(x) (BIT(x) - 1)
130
131#define MUX(_name, _parents, _offset, \
132 _clk_num, _gate_flags, _clk_id) \
133 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
134 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
135 _clk_num, _gate_flags, _clk_id, _parents##_idx, 0,\
136 NULL)
137
138#define MUX_FLAGS(_name, _parents, _offset,\
139 _clk_num, _gate_flags, _clk_id, flags)\
140 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
141 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
142 _clk_num, _gate_flags, _clk_id, _parents##_idx, flags,\
143 NULL)
144
145#define MUX8(_name, _parents, _offset, \
146 _clk_num, _gate_flags, _clk_id) \
147 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
148 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
149 _clk_num, _gate_flags, _clk_id, _parents##_idx, 0,\
150 NULL)
151
152#define MUX8_NOGATE_LOCK(_name, _parents, _offset, _clk_id, _lock) \
153 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset, \
154 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
155 0, TEGRA_PERIPH_NO_GATE, _clk_id,\
156 _parents##_idx, 0, _lock)
157
158#define INT(_name, _parents, _offset, \
159 _clk_num, _gate_flags, _clk_id) \
160 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
161 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
162 TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\
163 _clk_id, _parents##_idx, 0, NULL)
164
165#define INT_FLAGS(_name, _parents, _offset,\
166 _clk_num, _gate_flags, _clk_id, flags)\
167 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
168 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
169 TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\
170 _clk_id, _parents##_idx, flags, NULL)
171
172#define INT8(_name, _parents, _offset,\
173 _clk_num, _gate_flags, _clk_id) \
174 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
175 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
176 TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\
177 _clk_id, _parents##_idx, 0, NULL)
178
179#define UART(_name, _parents, _offset,\
180 _clk_num, _clk_id) \
181 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
182 30, MASK(2), 0, 0, 16, 1, TEGRA_DIVIDER_UART| \
183 TEGRA_DIVIDER_ROUND_UP, _clk_num, 0, _clk_id,\
184 _parents##_idx, 0, NULL)
185
186#define I2C(_name, _parents, _offset,\
187 _clk_num, _clk_id) \
188 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
189 30, MASK(2), 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP,\
190 _clk_num, 0, _clk_id, _parents##_idx, 0, NULL)
191
192#define XUSB(_name, _parents, _offset, \
193 _clk_num, _gate_flags, _clk_id) \
194 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset, \
195 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
196 TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\
197 _clk_id, _parents##_idx, 0, NULL)
198
199#define AUDIO(_name, _offset, _clk_num,\
200 _gate_flags, _clk_id) \
201 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, mux_d_audio_clk, \
202 _offset, 16, 0xE01F, 0, 0, 8, 1, \
203 TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags, \
204 _clk_id, mux_d_audio_clk_idx, 0, NULL)
205
206#define NODIV(_name, _parents, _offset, \
207 _mux_shift, _mux_mask, _clk_num, \
208 _gate_flags, _clk_id, _lock) \
209 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
210 _mux_shift, _mux_mask, 0, 0, 0, 0, 0,\
211 _clk_num, (_gate_flags) | TEGRA_PERIPH_NO_DIV,\
212 _clk_id, _parents##_idx, 0, _lock)
213
214#define GATE(_name, _parent_name, \
215 _clk_num, _gate_flags, _clk_id, _flags) \
216 { \
217 .name = _name, \
218 .clk_id = _clk_id, \
219 .p.parent_name = _parent_name, \
220 .periph = TEGRA_CLK_PERIPH(0, 0, 0, 0, 0, 0, 0, \
221 _clk_num, _gate_flags, 0, NULL), \
222 .flags = _flags \
223 }
224
225#define PLLP_BASE 0xa0
226#define PLLP_MISC 0xac
227#define PLLP_OUTA 0xa4
228#define PLLP_OUTB 0xa8
229#define PLLP_OUTC 0x67c
230
231#define PLL_BASE_LOCK BIT(27)
232#define PLL_MISC_LOCK_ENABLE 18
233
234static DEFINE_SPINLOCK(PLLP_OUTA_lock);
235static DEFINE_SPINLOCK(PLLP_OUTB_lock);
236static DEFINE_SPINLOCK(PLLP_OUTC_lock);
237static DEFINE_SPINLOCK(sor0_lock);
238
239#define MUX_I2S_SPDIF(_id) \
240static const char *mux_pllaout0_##_id##_2x_pllp_clkm[] = { "pll_a_out0", \
241 #_id, "pll_p",\
242 "clk_m"};
243MUX_I2S_SPDIF(audio0)
244MUX_I2S_SPDIF(audio1)
245MUX_I2S_SPDIF(audio2)
246MUX_I2S_SPDIF(audio3)
247MUX_I2S_SPDIF(audio4)
248MUX_I2S_SPDIF(audio)
249
250#define mux_pllaout0_audio0_2x_pllp_clkm_idx NULL
251#define mux_pllaout0_audio1_2x_pllp_clkm_idx NULL
252#define mux_pllaout0_audio2_2x_pllp_clkm_idx NULL
253#define mux_pllaout0_audio3_2x_pllp_clkm_idx NULL
254#define mux_pllaout0_audio4_2x_pllp_clkm_idx NULL
255#define mux_pllaout0_audio_2x_pllp_clkm_idx NULL
256
257static const char *mux_pllp_pllc_pllm_clkm[] = {
258 "pll_p", "pll_c", "pll_m", "clk_m"
259};
260#define mux_pllp_pllc_pllm_clkm_idx NULL
261
262static const char *mux_pllp_pllc_pllm[] = { "pll_p", "pll_c", "pll_m" };
263#define mux_pllp_pllc_pllm_idx NULL
264
265static const char *mux_pllp_pllc_clk32_clkm[] = {
266 "pll_p", "pll_c", "clk_32k", "clk_m"
267};
268#define mux_pllp_pllc_clk32_clkm_idx NULL
269
270static const char *mux_plla_pllc_pllp_clkm[] = {
271 "pll_a_out0", "pll_c", "pll_p", "clk_m"
272};
273#define mux_plla_pllc_pllp_clkm_idx mux_pllp_pllc_pllm_clkm_idx
274
275static const char *mux_pllp_pllc2_c_c3_pllm_clkm[] = {
276 "pll_p", "pll_c2", "pll_c", "pll_c3", "pll_m", "clk_m"
277};
278static u32 mux_pllp_pllc2_c_c3_pllm_clkm_idx[] = {
279 [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6,
280};
281
282static const char *mux_pllp_clkm[] = {
283 "pll_p", "clk_m"
284};
285static u32 mux_pllp_clkm_idx[] = {
286 [0] = 0, [1] = 3,
287};
288
289static const char *mux_pllm_pllc2_c_c3_pllp_plla[] = {
290 "pll_m", "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a_out0"
291};
292#define mux_pllm_pllc2_c_c3_pllp_plla_idx mux_pllp_pllc2_c_c3_pllm_clkm_idx
293
294static const char *mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = {
295 "pll_p", "pll_m", "pll_d_out0", "pll_a_out0", "pll_c",
296 "pll_d2_out0", "clk_m"
297};
298#define mux_pllp_pllm_plld_plla_pllc_plld2_clkm_idx NULL
299
300static const char *mux_pllm_pllc_pllp_plla[] = {
301 "pll_m", "pll_c", "pll_p", "pll_a_out0"
302};
303#define mux_pllm_pllc_pllp_plla_idx mux_pllp_pllc_pllm_clkm_idx
304
305static const char *mux_pllp_pllc_clkm[] = {
306 "pll_p", "pll_c", "pll_m"
307};
308static u32 mux_pllp_pllc_clkm_idx[] = {
309 [0] = 0, [1] = 1, [2] = 3,
310};
311
312static const char *mux_pllp_pllc_clkm_clk32[] = {
313 "pll_p", "pll_c", "clk_m", "clk_32k"
314};
315#define mux_pllp_pllc_clkm_clk32_idx NULL
316
317static const char *mux_plla_clk32_pllp_clkm_plle[] = {
318 "pll_a_out0", "clk_32k", "pll_p", "clk_m", "pll_e_out0"
319};
320#define mux_plla_clk32_pllp_clkm_plle_idx NULL
321
322static const char *mux_clkm_pllp_pllc_pllre[] = {
323 "clk_m", "pll_p", "pll_c", "pll_re_out"
324};
325static u32 mux_clkm_pllp_pllc_pllre_idx[] = {
326 [0] = 0, [1] = 1, [2] = 3, [3] = 5,
327};
328
329static const char *mux_clkm_48M_pllp_480M[] = {
330 "clk_m", "pll_u_48M", "pll_p", "pll_u_480M"
331};
332#define mux_clkm_48M_pllp_480M_idx NULL
333
334static const char *mux_clkm_pllre_clk32_480M_pllc_ref[] = {
335 "clk_m", "pll_re_out", "clk_32k", "pll_u_480M", "pll_c", "pll_ref"
336};
337static u32 mux_clkm_pllre_clk32_480M_pllc_ref_idx[] = {
338 [0] = 0, [1] = 1, [2] = 3, [3] = 3, [4] = 4, [5] = 7,
339};
340
341static const char *mux_d_audio_clk[] = {
342 "pll_a_out0", "pll_p", "clk_m", "spdif_in_sync", "i2s0_sync",
343 "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync",
344};
345static u32 mux_d_audio_clk_idx[] = {
346 [0] = 0, [1] = 0x8000, [2] = 0xc000, [3] = 0xE000, [4] = 0xE001,
347 [5] = 0xE002, [6] = 0xE003, [7] = 0xE004, [8] = 0xE005, [9] = 0xE007,
348};
349
350static const char *mux_pllp_plld_pllc_clkm[] = {
351 "pll_p", "pll_d_out0", "pll_c", "clk_m"
352};
353#define mux_pllp_plld_pllc_clkm_idx NULL
354static const char *mux_pllm_pllc_pllp_plla_clkm_pllc4[] = {
355 "pll_m", "pll_c", "pll_p", "pll_a_out0", "clk_m", "pll_c4",
356};
357static u32 mux_pllm_pllc_pllp_plla_clkm_pllc4_idx[] = {
358 [0] = 0, [1] = 1, [2] = 3, [3] = 3, [4] = 6, [5] = 7,
359};
360
361static const char *mux_pllp_clkm1[] = {
362 "pll_p", "clk_m",
363};
364#define mux_pllp_clkm1_idx NULL
365
366static const char *mux_pllp3_pllc_clkm[] = {
367 "pll_p_out3", "pll_c", "pll_c2", "clk_m",
368};
369#define mux_pllp3_pllc_clkm_idx NULL
370
371static const char *mux_pllm_pllc_pllp_plla_pllc2_c3_clkm[] = {
372 "pll_m", "pll_c", "pll_p", "pll_a", "pll_c2", "pll_c3", "clk_m"
373};
374static u32 mux_pllm_pllc_pllp_plla_pllc2_c3_clkm_idx[] = {
375 [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6,
376};
377
378static const char *mux_pllm_pllc2_c_c3_pllp_plla_pllc4[] = {
379 "pll_m", "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a_out0", "pll_c4",
380};
381static u32 mux_pllm_pllc2_c_c3_pllp_plla_pllc4_idx[] = {
382 [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6, [6] = 7,
383};
384
385static const char *mux_clkm_plldp_sor0lvds[] = {
386 "clk_m", "pll_dp", "sor0_lvds",
387};
388#define mux_clkm_plldp_sor0lvds_idx NULL
389
390static struct tegra_periph_init_data periph_clks[] = {
391 AUDIO("d_audio", CLK_SOURCE_D_AUDIO, 106, TEGRA_PERIPH_ON_APB, tegra_clk_d_audio),
392 AUDIO("dam0", CLK_SOURCE_DAM0, 108, TEGRA_PERIPH_ON_APB, tegra_clk_dam0),
393 AUDIO("dam1", CLK_SOURCE_DAM1, 109, TEGRA_PERIPH_ON_APB, tegra_clk_dam1),
394 AUDIO("dam2", CLK_SOURCE_DAM2, 110, TEGRA_PERIPH_ON_APB, tegra_clk_dam2),
395 I2C("i2c1", mux_pllp_clkm, CLK_SOURCE_I2C1, 12, tegra_clk_i2c1),
396 I2C("i2c2", mux_pllp_clkm, CLK_SOURCE_I2C2, 54, tegra_clk_i2c2),
397 I2C("i2c3", mux_pllp_clkm, CLK_SOURCE_I2C3, 67, tegra_clk_i2c3),
398 I2C("i2c4", mux_pllp_clkm, CLK_SOURCE_I2C4, 103, tegra_clk_i2c4),
399 I2C("i2c5", mux_pllp_clkm, CLK_SOURCE_I2C5, 47, tegra_clk_i2c5),
400 INT("vde", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VDE, 61, 0, tegra_clk_vde),
401 INT("vi", mux_pllm_pllc_pllp_plla, CLK_SOURCE_VI, 20, 0, tegra_clk_vi),
402 INT("epp", mux_pllm_pllc_pllp_plla, CLK_SOURCE_EPP, 19, 0, tegra_clk_epp),
403 INT("host1x", mux_pllm_pllc_pllp_plla, CLK_SOURCE_HOST1X, 28, 0, tegra_clk_host1x),
404 INT("mpe", mux_pllm_pllc_pllp_plla, CLK_SOURCE_MPE, 60, 0, tegra_clk_mpe),
405 INT("2d", mux_pllm_pllc_pllp_plla, CLK_SOURCE_2D, 21, 0, tegra_clk_gr2d),
406 INT("3d", mux_pllm_pllc_pllp_plla, CLK_SOURCE_3D, 24, 0, tegra_clk_gr3d),
407 INT8("vde", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_VDE, 61, 0, tegra_clk_vde_8),
408 INT8("vi", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI, 20, 0, tegra_clk_vi_8),
409 INT8("vi", mux_pllm_pllc2_c_c3_pllp_plla_pllc4, CLK_SOURCE_VI, 20, 0, tegra_clk_vi_9),
410 INT8("epp", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_EPP, 19, 0, tegra_clk_epp_8),
411 INT8("msenc", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_MSENC, 91, TEGRA_PERIPH_WAR_1005168, tegra_clk_msenc),
412 INT8("tsec", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_TSEC, 83, 0, tegra_clk_tsec),
413 INT8("host1x", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_HOST1X, 28, 0, tegra_clk_host1x_8),
414 INT8("se", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SE, 127, TEGRA_PERIPH_ON_APB, tegra_clk_se),
415 INT8("2d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_2D, 21, 0, tegra_clk_gr2d_8),
416 INT8("3d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_3D, 24, 0, tegra_clk_gr3d_8),
417 INT8("vic03", mux_pllm_pllc_pllp_plla_pllc2_c3_clkm, CLK_SOURCE_VIC03, 178, 0, tegra_clk_vic03),
418 INT_FLAGS("mselect", mux_pllp_clkm, CLK_SOURCE_MSELECT, 99, 0, tegra_clk_mselect, CLK_IGNORE_UNUSED),
419 MUX("i2s0", mux_pllaout0_audio0_2x_pllp_clkm, CLK_SOURCE_I2S0, 30, TEGRA_PERIPH_ON_APB, tegra_clk_i2s0),
420 MUX("i2s1", mux_pllaout0_audio1_2x_pllp_clkm, CLK_SOURCE_I2S1, 11, TEGRA_PERIPH_ON_APB, tegra_clk_i2s1),
421 MUX("i2s2", mux_pllaout0_audio2_2x_pllp_clkm, CLK_SOURCE_I2S2, 18, TEGRA_PERIPH_ON_APB, tegra_clk_i2s2),
422 MUX("i2s3", mux_pllaout0_audio3_2x_pllp_clkm, CLK_SOURCE_I2S3, 101, TEGRA_PERIPH_ON_APB, tegra_clk_i2s3),
423 MUX("i2s4", mux_pllaout0_audio4_2x_pllp_clkm, CLK_SOURCE_I2S4, 102, TEGRA_PERIPH_ON_APB, tegra_clk_i2s4),
424 MUX("spdif_out", mux_pllaout0_audio_2x_pllp_clkm, CLK_SOURCE_SPDIF_OUT, 10, TEGRA_PERIPH_ON_APB, tegra_clk_spdif_out),
425 MUX("spdif_in", mux_pllp_pllc_pllm, CLK_SOURCE_SPDIF_IN, 10, TEGRA_PERIPH_ON_APB, tegra_clk_spdif_in),
426 MUX("pwm", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_PWM, 17, TEGRA_PERIPH_ON_APB, tegra_clk_pwm),
427 MUX("adx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX, 154, TEGRA_PERIPH_ON_APB, tegra_clk_adx),
428 MUX("amx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX, 153, TEGRA_PERIPH_ON_APB, tegra_clk_amx),
429 MUX("hda", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA, 125, TEGRA_PERIPH_ON_APB, tegra_clk_hda),
430 MUX("hda2codec_2x", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, TEGRA_PERIPH_ON_APB, tegra_clk_hda2codec_2x),
431 MUX("vfir", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VFIR, 7, TEGRA_PERIPH_ON_APB, tegra_clk_vfir),
432 MUX("sdmmc1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC1, 14, 0, tegra_clk_sdmmc1),
433 MUX("sdmmc2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC2, 9, 0, tegra_clk_sdmmc2),
434 MUX("sdmmc3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC3, 69, 0, tegra_clk_sdmmc3),
435 MUX("sdmmc4", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC4, 15, 0, tegra_clk_sdmmc4),
436 MUX("la", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_LA, 76, TEGRA_PERIPH_ON_APB, tegra_clk_la),
437 MUX("trace", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_TRACE, 77, TEGRA_PERIPH_ON_APB, tegra_clk_trace),
438 MUX("owr", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_OWR, 71, TEGRA_PERIPH_ON_APB, tegra_clk_owr),
439 MUX("nor", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NOR, 42, 0, tegra_clk_nor),
440 MUX("mipi", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_MIPI, 50, TEGRA_PERIPH_ON_APB, tegra_clk_mipi),
441 MUX("vi_sensor", mux_pllm_pllc_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor),
442 MUX("cilab", mux_pllp_pllc_clkm, CLK_SOURCE_CILAB, 144, 0, tegra_clk_cilab),
443 MUX("cilcd", mux_pllp_pllc_clkm, CLK_SOURCE_CILCD, 145, 0, tegra_clk_cilcd),
444 MUX("cile", mux_pllp_pllc_clkm, CLK_SOURCE_CILE, 146, 0, tegra_clk_cile),
445 MUX("dsialp", mux_pllp_pllc_clkm, CLK_SOURCE_DSIALP, 147, 0, tegra_clk_dsialp),
446 MUX("dsiblp", mux_pllp_pllc_clkm, CLK_SOURCE_DSIBLP, 148, 0, tegra_clk_dsiblp),
447 MUX("tsensor", mux_pllp_pllc_clkm_clk32, CLK_SOURCE_TSENSOR, 100, TEGRA_PERIPH_ON_APB, tegra_clk_tsensor),
448 MUX("actmon", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_ACTMON, 119, 0, tegra_clk_actmon),
449 MUX("dfll_ref", mux_pllp_clkm, CLK_SOURCE_DFLL_REF, 155, TEGRA_PERIPH_ON_APB, tegra_clk_dfll_ref),
450 MUX("dfll_soc", mux_pllp_clkm, CLK_SOURCE_DFLL_SOC, 155, TEGRA_PERIPH_ON_APB, tegra_clk_dfll_soc),
451 MUX("i2cslow", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_I2CSLOW, 81, TEGRA_PERIPH_ON_APB, tegra_clk_i2cslow),
452 MUX("sbc1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC1, 41, TEGRA_PERIPH_ON_APB, tegra_clk_sbc1),
453 MUX("sbc2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC2, 44, TEGRA_PERIPH_ON_APB, tegra_clk_sbc2),
454 MUX("sbc3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC3, 46, TEGRA_PERIPH_ON_APB, tegra_clk_sbc3),
455 MUX("sbc4", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC4, 68, TEGRA_PERIPH_ON_APB, tegra_clk_sbc4),
456 MUX("sbc5", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC5, 104, TEGRA_PERIPH_ON_APB, tegra_clk_sbc5),
457 MUX("sbc6", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC6, 105, TEGRA_PERIPH_ON_APB, tegra_clk_sbc6),
458 MUX("cve", mux_pllp_plld_pllc_clkm, CLK_SOURCE_CVE, 49, 0, tegra_clk_cve),
459 MUX("tvo", mux_pllp_plld_pllc_clkm, CLK_SOURCE_TVO, 49, 0, tegra_clk_tvo),
460 MUX("tvdac", mux_pllp_plld_pllc_clkm, CLK_SOURCE_TVDAC, 53, 0, tegra_clk_tvdac),
461 MUX("ndflash", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NDFLASH, 13, TEGRA_PERIPH_ON_APB, tegra_clk_ndflash),
462 MUX("ndspeed", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NDSPEED, 80, TEGRA_PERIPH_ON_APB, tegra_clk_ndspeed),
463 MUX("sata_oob", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SATA_OOB, 123, TEGRA_PERIPH_ON_APB, tegra_clk_sata_oob),
464 MUX("sata", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SATA, 124, TEGRA_PERIPH_ON_APB, tegra_clk_sata),
465 MUX("adx1", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX1, 180, TEGRA_PERIPH_ON_APB, tegra_clk_adx1),
466 MUX("amx1", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX1, 185, TEGRA_PERIPH_ON_APB, tegra_clk_amx1),
467 MUX("vi_sensor2", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR2, 20, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor2),
468 MUX8("sbc1", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC1, 41, TEGRA_PERIPH_ON_APB, tegra_clk_sbc1_8),
469 MUX8("sbc2", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC2, 44, TEGRA_PERIPH_ON_APB, tegra_clk_sbc2_8),
470 MUX8("sbc3", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC3, 46, TEGRA_PERIPH_ON_APB, tegra_clk_sbc3_8),
471 MUX8("sbc4", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC4, 68, TEGRA_PERIPH_ON_APB, tegra_clk_sbc4_8),
472 MUX8("sbc5", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC5, 104, TEGRA_PERIPH_ON_APB, tegra_clk_sbc5_8),
473 MUX8("sbc6", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC6, 105, TEGRA_PERIPH_ON_APB, tegra_clk_sbc6_8),
474 MUX8("ndflash", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDFLASH, 13, TEGRA_PERIPH_ON_APB, tegra_clk_ndflash_8),
475 MUX8("ndspeed", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDSPEED, 80, TEGRA_PERIPH_ON_APB, tegra_clk_ndspeed_8),
476 MUX8("hdmi", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_HDMI, 51, 0, tegra_clk_hdmi),
477 MUX8("extern1", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN1, 120, 0, tegra_clk_extern1),
478 MUX8("extern2", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN2, 121, 0, tegra_clk_extern2),
479 MUX8("extern3", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN3, 122, 0, tegra_clk_extern3),
480 MUX8("soc_therm", mux_pllm_pllc_pllp_plla, CLK_SOURCE_SOC_THERM, 78, TEGRA_PERIPH_ON_APB, tegra_clk_soc_therm),
481 MUX8("vi_sensor", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor_8),
482 MUX8("isp", mux_pllm_pllc_pllp_plla_clkm_pllc4, CLK_SOURCE_ISP, 23, TEGRA_PERIPH_ON_APB, tegra_clk_isp_8),
483 MUX8("entropy", mux_pllp_clkm1, CLK_SOURCE_ENTROPY, 149, 0, tegra_clk_entropy),
484 MUX8("hdmi_audio", mux_pllp3_pllc_clkm, CLK_SOURCE_HDMI_AUDIO, 176, TEGRA_PERIPH_NO_RESET, tegra_clk_hdmi_audio),
485 MUX8("clk72mhz", mux_pllp3_pllc_clkm, CLK_SOURCE_CLK72MHZ, 177, TEGRA_PERIPH_NO_RESET, tegra_clk_clk72Mhz),
486 MUX8_NOGATE_LOCK("sor0_lvds", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_SOR0, tegra_clk_sor0_lvds, &sor0_lock),
487 MUX_FLAGS("csite", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_CSITE, 73, TEGRA_PERIPH_ON_APB, tegra_clk_csite, CLK_IGNORE_UNUSED),
488 NODIV("disp1", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP1, 29, 7, 27, 0, tegra_clk_disp1, NULL),
489 NODIV("disp2", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP2, 29, 7, 26, 0, tegra_clk_disp2, NULL),
490 NODIV("sor0", mux_clkm_plldp_sor0lvds, CLK_SOURCE_SOR0, 14, 3, 182, 0, tegra_clk_sor0, &sor0_lock),
491 UART("uarta", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTA, 6, tegra_clk_uarta),
492 UART("uartb", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTB, 7, tegra_clk_uartb),
493 UART("uartc", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTC, 55, tegra_clk_uartc),
494 UART("uartd", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTD, 65, tegra_clk_uartd),
495 UART("uarte", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTE, 65, tegra_clk_uarte),
496 XUSB("xusb_host_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_HOST_SRC, 143, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_host_src),
497 XUSB("xusb_falcon_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_falcon_src),
498 XUSB("xusb_fs_src", mux_clkm_48M_pllp_480M, CLK_SOURCE_XUSB_FS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_fs_src),
499 XUSB("xusb_ss_src", mux_clkm_pllre_clk32_480M_pllc_ref, CLK_SOURCE_XUSB_SS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_ss_src),
500 XUSB("xusb_dev_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_dev_src),
501};
502
503static struct tegra_periph_init_data gate_clks[] = {
504 GATE("rtc", "clk_32k", 4, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_rtc, 0),
505 GATE("timer", "clk_m", 5, 0, tegra_clk_timer, 0),
506 GATE("isp", "clk_m", 23, 0, tegra_clk_isp, 0),
507 GATE("vcp", "clk_m", 29, 0, tegra_clk_vcp, 0),
508 GATE("apbdma", "clk_m", 34, 0, tegra_clk_apbdma, 0),
509 GATE("kbc", "clk_32k", 36, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_kbc, 0),
510 GATE("fuse", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, 0),
511 GATE("fuse_burn", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse_burn, 0),
512 GATE("kfuse", "clk_m", 40, TEGRA_PERIPH_ON_APB, tegra_clk_kfuse, 0),
513 GATE("apbif", "clk_m", 107, TEGRA_PERIPH_ON_APB, tegra_clk_apbif, 0),
514 GATE("hda2hdmi", "clk_m", 128, TEGRA_PERIPH_ON_APB, tegra_clk_hda2hdmi, 0),
515 GATE("bsea", "clk_m", 62, 0, tegra_clk_bsea, 0),
516 GATE("bsev", "clk_m", 63, 0, tegra_clk_bsev, 0),
517 GATE("mipi-cal", "clk_m", 56, 0, tegra_clk_mipi_cal, 0),
518 GATE("usbd", "clk_m", 22, 0, tegra_clk_usbd, 0),
519 GATE("usb2", "clk_m", 58, 0, tegra_clk_usb2, 0),
520 GATE("usb3", "clk_m", 59, 0, tegra_clk_usb3, 0),
521 GATE("csi", "pll_p_out3", 52, 0, tegra_clk_csi, 0),
522 GATE("afi", "clk_m", 72, 0, tegra_clk_afi, 0),
523 GATE("csus", "clk_m", 92, TEGRA_PERIPH_NO_RESET, tegra_clk_csus, 0),
524 GATE("dds", "clk_m", 150, TEGRA_PERIPH_ON_APB, tegra_clk_dds, 0),
525 GATE("dp2", "clk_m", 152, TEGRA_PERIPH_ON_APB, tegra_clk_dp2, 0),
526 GATE("dtv", "clk_m", 79, TEGRA_PERIPH_ON_APB, tegra_clk_dtv, 0),
527 GATE("xusb_host", "xusb_host_src", 89, 0, tegra_clk_xusb_host, 0),
528 GATE("xusb_ss", "xusb_ss_src", 156, 0, tegra_clk_xusb_ss, 0),
529 GATE("xusb_dev", "xusb_dev_src", 95, 0, tegra_clk_xusb_dev, 0),
530 GATE("dsia", "dsia_mux", 48, 0, tegra_clk_dsia, 0),
531 GATE("dsib", "dsib_mux", 82, 0, tegra_clk_dsib, 0),
532 GATE("emc", "emc_mux", 57, 0, tegra_clk_emc, CLK_IGNORE_UNUSED),
533 GATE("sata_cold", "clk_m", 129, TEGRA_PERIPH_ON_APB, tegra_clk_sata_cold, 0),
534 GATE("ispb", "clk_m", 3, 0, tegra_clk_ispb, 0),
535 GATE("vim2_clk", "clk_m", 11, 0, tegra_clk_vim2_clk, 0),
536 GATE("pcie", "clk_m", 70, 0, tegra_clk_pcie, 0),
537 GATE("dpaux", "clk_m", 181, 0, tegra_clk_dpaux, 0),
538 GATE("gpu", "pll_ref", 184, 0, tegra_clk_gpu, 0),
539};
540
541struct pll_out_data {
542 char *div_name;
543 char *pll_out_name;
544 u32 offset;
545 int clk_id;
546 u8 div_shift;
547 u8 div_flags;
548 u8 rst_shift;
549 spinlock_t *lock;
550};
551
552#define PLL_OUT(_num, _offset, _div_shift, _div_flags, _rst_shift, _id) \
553 {\
554 .div_name = "pll_p_out" #_num "_div",\
555 .pll_out_name = "pll_p_out" #_num,\
556 .offset = _offset,\
557 .div_shift = _div_shift,\
558 .div_flags = _div_flags | TEGRA_DIVIDER_FIXED |\
559 TEGRA_DIVIDER_ROUND_UP,\
560 .rst_shift = _rst_shift,\
561 .clk_id = tegra_clk_ ## _id,\
562 .lock = &_offset ##_lock,\
563 }
564
565static struct pll_out_data pllp_out_clks[] = {
566 PLL_OUT(1, PLLP_OUTA, 8, 0, 0, pll_p_out1),
567 PLL_OUT(2, PLLP_OUTA, 24, 0, 16, pll_p_out2),
568 PLL_OUT(2, PLLP_OUTA, 24, TEGRA_DIVIDER_INT, 16, pll_p_out2_int),
569 PLL_OUT(3, PLLP_OUTB, 8, 0, 0, pll_p_out3),
570 PLL_OUT(4, PLLP_OUTB, 24, 0, 16, pll_p_out4),
571 PLL_OUT(5, PLLP_OUTC, 24, 0, 16, pll_p_out5),
572};
573
574static void __init periph_clk_init(void __iomem *clk_base,
575 struct tegra_clk *tegra_clks)
576{
577 int i;
578 struct clk *clk;
579 struct clk **dt_clk;
580
581 for (i = 0; i < ARRAY_SIZE(periph_clks); i++) {
582 struct tegra_clk_periph_regs *bank;
583 struct tegra_periph_init_data *data;
584
585 data = periph_clks + i;
586
587 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);
588 if (!dt_clk)
589 continue;
590
591 bank = get_reg_bank(data->periph.gate.clk_num);
592 if (!bank)
593 continue;
594
595 data->periph.gate.regs = bank;
596 clk = tegra_clk_register_periph(data->name,
597 data->p.parent_names, data->num_parents,
598 &data->periph, clk_base, data->offset,
599 data->flags);
600 *dt_clk = clk;
601 }
602}
603
604static void __init gate_clk_init(void __iomem *clk_base,
605 struct tegra_clk *tegra_clks)
606{
607 int i;
608 struct clk *clk;
609 struct clk **dt_clk;
610
611 for (i = 0; i < ARRAY_SIZE(gate_clks); i++) {
612 struct tegra_periph_init_data *data;
613
614 data = gate_clks + i;
615
616 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);
617 if (!dt_clk)
618 continue;
619
620 clk = tegra_clk_register_periph_gate(data->name,
621 data->p.parent_name, data->periph.gate.flags,
622 clk_base, data->flags,
623 data->periph.gate.clk_num,
624 periph_clk_enb_refcnt);
625 *dt_clk = clk;
626 }
627}
628
629static void __init init_pllp(void __iomem *clk_base, void __iomem *pmc_base,
630 struct tegra_clk *tegra_clks,
631 struct tegra_clk_pll_params *pll_params)
632{
633 struct clk *clk;
634 struct clk **dt_clk;
635 int i;
636
637 dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p, tegra_clks);
638 if (dt_clk) {
639 /* PLLP */
640 clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base,
641 pmc_base, 0, pll_params, NULL);
642 clk_register_clkdev(clk, "pll_p", NULL);
643 *dt_clk = clk;
644 }
645
646 for (i = 0; i < ARRAY_SIZE(pllp_out_clks); i++) {
647 struct pll_out_data *data;
648
649 data = pllp_out_clks + i;
650
651 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);
652 if (!dt_clk)
653 continue;
654
655 clk = tegra_clk_register_divider(data->div_name, "pll_p",
656 clk_base + data->offset, 0, data->div_flags,
657 data->div_shift, 8, 1, data->lock);
658 clk = tegra_clk_register_pll_out(data->pll_out_name,
659 data->div_name, clk_base + data->offset,
660 data->rst_shift + 1, data->rst_shift,
661 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
662 data->lock);
663 *dt_clk = clk;
664 }
665}
666
667void __init tegra_periph_clk_init(void __iomem *clk_base,
668 void __iomem *pmc_base, struct tegra_clk *tegra_clks,
669 struct tegra_clk_pll_params *pll_params)
670{
671 init_pllp(clk_base, pmc_base, tegra_clks, pll_params);
672 periph_clk_init(clk_base, tegra_clks);
673 gate_clk_init(clk_base, tegra_clks);
674}
diff --git a/drivers/clk/tegra/clk-tegra-pmc.c b/drivers/clk/tegra/clk-tegra-pmc.c
new file mode 100644
index 000000000000..08b21c1ee867
--- /dev/null
+++ b/drivers/clk/tegra/clk-tegra-pmc.c
@@ -0,0 +1,132 @@
1/*
2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/io.h>
18#include <linux/clk.h>
19#include <linux/clk-provider.h>
20#include <linux/clkdev.h>
21#include <linux/of.h>
22#include <linux/of_address.h>
23#include <linux/delay.h>
24#include <linux/export.h>
25#include <linux/clk/tegra.h>
26
27#include "clk.h"
28#include "clk-id.h"
29
30#define PMC_CLK_OUT_CNTRL 0x1a8
31#define PMC_DPD_PADS_ORIDE 0x1c
32#define PMC_DPD_PADS_ORIDE_BLINK_ENB 20
33#define PMC_CTRL 0
34#define PMC_CTRL_BLINK_ENB 7
35#define PMC_BLINK_TIMER 0x40
36
37struct pmc_clk_init_data {
38 char *mux_name;
39 char *gate_name;
40 const char **parents;
41 int num_parents;
42 int mux_id;
43 int gate_id;
44 char *dev_name;
45 u8 mux_shift;
46 u8 gate_shift;
47};
48
49#define PMC_CLK(_num, _mux_shift, _gate_shift)\
50 {\
51 .mux_name = "clk_out_" #_num "_mux",\
52 .gate_name = "clk_out_" #_num,\
53 .parents = clk_out ##_num ##_parents,\
54 .num_parents = ARRAY_SIZE(clk_out ##_num ##_parents),\
55 .mux_id = tegra_clk_clk_out_ ##_num ##_mux,\
56 .gate_id = tegra_clk_clk_out_ ##_num,\
57 .dev_name = "extern" #_num,\
58 .mux_shift = _mux_shift,\
59 .gate_shift = _gate_shift,\
60 }
61
62static DEFINE_SPINLOCK(clk_out_lock);
63
64static const char *clk_out1_parents[] = { "clk_m", "clk_m_div2",
65 "clk_m_div4", "extern1",
66};
67
68static const char *clk_out2_parents[] = { "clk_m", "clk_m_div2",
69 "clk_m_div4", "extern2",
70};
71
72static const char *clk_out3_parents[] = { "clk_m", "clk_m_div2",
73 "clk_m_div4", "extern3",
74};
75
76static struct pmc_clk_init_data pmc_clks[] = {
77 PMC_CLK(1, 6, 2),
78 PMC_CLK(2, 14, 10),
79 PMC_CLK(3, 22, 18),
80};
81
82void __init tegra_pmc_clk_init(void __iomem *pmc_base,
83 struct tegra_clk *tegra_clks)
84{
85 struct clk *clk;
86 struct clk **dt_clk;
87 int i;
88
89 for (i = 0; i < ARRAY_SIZE(pmc_clks); i++) {
90 struct pmc_clk_init_data *data;
91
92 data = pmc_clks + i;
93
94 dt_clk = tegra_lookup_dt_id(data->mux_id, tegra_clks);
95 if (!dt_clk)
96 continue;
97
98 clk = clk_register_mux(NULL, data->mux_name, data->parents,
99 data->num_parents, CLK_SET_RATE_NO_REPARENT,
100 pmc_base + PMC_CLK_OUT_CNTRL, data->mux_shift,
101 3, 0, &clk_out_lock);
102 *dt_clk = clk;
103
104
105 dt_clk = tegra_lookup_dt_id(data->gate_id, tegra_clks);
106 if (!dt_clk)
107 continue;
108
109 clk = clk_register_gate(NULL, data->gate_name, data->mux_name,
110 0, pmc_base + PMC_CLK_OUT_CNTRL,
111 data->gate_shift, 0, &clk_out_lock);
112 *dt_clk = clk;
113 clk_register_clkdev(clk, data->dev_name, data->gate_name);
114 }
115
116 /* blink */
117 writel_relaxed(0, pmc_base + PMC_BLINK_TIMER);
118 clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0,
119 pmc_base + PMC_DPD_PADS_ORIDE,
120 PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL);
121
122 dt_clk = tegra_lookup_dt_id(tegra_clk_blink, tegra_clks);
123 if (!dt_clk)
124 return;
125
126 clk = clk_register_gate(NULL, "blink", "blink_override", 0,
127 pmc_base + PMC_CTRL,
128 PMC_CTRL_BLINK_ENB, 0, NULL);
129 clk_register_clkdev(clk, "blink", NULL);
130 *dt_clk = clk;
131}
132
diff --git a/drivers/clk/tegra/clk-tegra-super-gen4.c b/drivers/clk/tegra/clk-tegra-super-gen4.c
new file mode 100644
index 000000000000..05dce4aa2c11
--- /dev/null
+++ b/drivers/clk/tegra/clk-tegra-super-gen4.c
@@ -0,0 +1,149 @@
1/*
2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/io.h>
18#include <linux/clk.h>
19#include <linux/clk-provider.h>
20#include <linux/of.h>
21#include <linux/of_address.h>
22#include <linux/delay.h>
23#include <linux/export.h>
24#include <linux/clk/tegra.h>
25
26#include "clk.h"
27#include "clk-id.h"
28
29#define PLLX_BASE 0xe0
30#define PLLX_MISC 0xe4
31#define PLLX_MISC2 0x514
32#define PLLX_MISC3 0x518
33
34#define CCLKG_BURST_POLICY 0x368
35#define CCLKLP_BURST_POLICY 0x370
36#define SCLK_BURST_POLICY 0x028
37#define SYSTEM_CLK_RATE 0x030
38
39static DEFINE_SPINLOCK(sysrate_lock);
40
41static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
42 "pll_p", "pll_p_out2", "unused",
43 "clk_32k", "pll_m_out1" };
44
45static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
46 "pll_p", "pll_p_out4", "unused",
47 "unused", "pll_x" };
48
49static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
50 "pll_p", "pll_p_out4", "unused",
51 "unused", "pll_x", "pll_x_out0" };
52
53static void __init tegra_sclk_init(void __iomem *clk_base,
54 struct tegra_clk *tegra_clks)
55{
56 struct clk *clk;
57 struct clk **dt_clk;
58
59 /* SCLK */
60 dt_clk = tegra_lookup_dt_id(tegra_clk_sclk, tegra_clks);
61 if (dt_clk) {
62 clk = tegra_clk_register_super_mux("sclk", sclk_parents,
63 ARRAY_SIZE(sclk_parents),
64 CLK_SET_RATE_PARENT,
65 clk_base + SCLK_BURST_POLICY,
66 0, 4, 0, 0, NULL);
67 *dt_clk = clk;
68 }
69
70 /* HCLK */
71 dt_clk = tegra_lookup_dt_id(tegra_clk_hclk, tegra_clks);
72 if (dt_clk) {
73 clk = clk_register_divider(NULL, "hclk_div", "sclk", 0,
74 clk_base + SYSTEM_CLK_RATE, 4, 2, 0,
75 &sysrate_lock);
76 clk = clk_register_gate(NULL, "hclk", "hclk_div",
77 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
78 clk_base + SYSTEM_CLK_RATE,
79 7, CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
80 *dt_clk = clk;
81 }
82
83 /* PCLK */
84 dt_clk = tegra_lookup_dt_id(tegra_clk_pclk, tegra_clks);
85 if (!dt_clk)
86 return;
87
88 clk = clk_register_divider(NULL, "pclk_div", "hclk", 0,
89 clk_base + SYSTEM_CLK_RATE, 0, 2, 0,
90 &sysrate_lock);
91 clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT |
92 CLK_IGNORE_UNUSED, clk_base + SYSTEM_CLK_RATE,
93 3, CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
94 *dt_clk = clk;
95}
96
97void __init tegra_super_clk_gen4_init(void __iomem *clk_base,
98 void __iomem *pmc_base,
99 struct tegra_clk *tegra_clks,
100 struct tegra_clk_pll_params *params)
101{
102 struct clk *clk;
103 struct clk **dt_clk;
104
105 /* CCLKG */
106 dt_clk = tegra_lookup_dt_id(tegra_clk_cclk_g, tegra_clks);
107 if (dt_clk) {
108 clk = tegra_clk_register_super_mux("cclk_g", cclk_g_parents,
109 ARRAY_SIZE(cclk_g_parents),
110 CLK_SET_RATE_PARENT,
111 clk_base + CCLKG_BURST_POLICY,
112 0, 4, 0, 0, NULL);
113 *dt_clk = clk;
114 }
115
116 /* CCLKLP */
117 dt_clk = tegra_lookup_dt_id(tegra_clk_cclk_lp, tegra_clks);
118 if (dt_clk) {
119 clk = tegra_clk_register_super_mux("cclk_lp", cclk_lp_parents,
120 ARRAY_SIZE(cclk_lp_parents),
121 CLK_SET_RATE_PARENT,
122 clk_base + CCLKLP_BURST_POLICY,
123 0, 4, 8, 9, NULL);
124 *dt_clk = clk;
125 }
126
127 tegra_sclk_init(clk_base, tegra_clks);
128
129#if defined(CONFIG_ARCH_TEGRA_114_SOC) || defined(CONFIG_ARCH_TEGRA_124_SOC)
130 /* PLLX */
131 dt_clk = tegra_lookup_dt_id(tegra_clk_pll_x, tegra_clks);
132 if (!dt_clk)
133 return;
134
135 clk = tegra_clk_register_pllxc("pll_x", "pll_ref", clk_base,
136 pmc_base, CLK_IGNORE_UNUSED, params, NULL);
137 *dt_clk = clk;
138
139 /* PLLX_OUT0 */
140
141 dt_clk = tegra_lookup_dt_id(tegra_clk_pll_x_out0, tegra_clks);
142 if (!dt_clk)
143 return;
144 clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x",
145 CLK_SET_RATE_PARENT, 1, 2);
146 *dt_clk = clk;
147#endif
148}
149
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index 9467da7dee49..90d9d25f2228 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -23,30 +23,15 @@
23#include <linux/delay.h> 23#include <linux/delay.h>
24#include <linux/export.h> 24#include <linux/export.h>
25#include <linux/clk/tegra.h> 25#include <linux/clk/tegra.h>
26#include <dt-bindings/clock/tegra114-car.h>
26 27
27#include "clk.h" 28#include "clk.h"
29#include "clk-id.h"
28 30
29#define RST_DEVICES_L 0x004
30#define RST_DEVICES_H 0x008
31#define RST_DEVICES_U 0x00C
32#define RST_DFLL_DVCO 0x2F4 31#define RST_DFLL_DVCO 0x2F4
33#define RST_DEVICES_V 0x358
34#define RST_DEVICES_W 0x35C
35#define RST_DEVICES_X 0x28C
36#define RST_DEVICES_SET_L 0x300
37#define RST_DEVICES_CLR_L 0x304
38#define RST_DEVICES_SET_H 0x308
39#define RST_DEVICES_CLR_H 0x30c
40#define RST_DEVICES_SET_U 0x310
41#define RST_DEVICES_CLR_U 0x314
42#define RST_DEVICES_SET_V 0x430
43#define RST_DEVICES_CLR_V 0x434
44#define RST_DEVICES_SET_W 0x438
45#define RST_DEVICES_CLR_W 0x43c
46#define CPU_FINETRIM_SELECT 0x4d4 /* override default prop dlys */ 32#define CPU_FINETRIM_SELECT 0x4d4 /* override default prop dlys */
47#define CPU_FINETRIM_DR 0x4d8 /* rise->rise prop dly A */ 33#define CPU_FINETRIM_DR 0x4d8 /* rise->rise prop dly A */
48#define CPU_FINETRIM_R 0x4e4 /* rise->rise prop dly inc A */ 34#define CPU_FINETRIM_R 0x4e4 /* rise->rise prop dly inc A */
49#define RST_DEVICES_NUM 5
50 35
51/* RST_DFLL_DVCO bitfields */ 36/* RST_DFLL_DVCO bitfields */
52#define DVFS_DFLL_RESET_SHIFT 0 37#define DVFS_DFLL_RESET_SHIFT 0
@@ -73,25 +58,7 @@
73#define CPU_FINETRIM_R_FCPU_6_SHIFT 10 /* ftop */ 58#define CPU_FINETRIM_R_FCPU_6_SHIFT 10 /* ftop */
74#define CPU_FINETRIM_R_FCPU_6_MASK (0x3 << CPU_FINETRIM_R_FCPU_6_SHIFT) 59#define CPU_FINETRIM_R_FCPU_6_MASK (0x3 << CPU_FINETRIM_R_FCPU_6_SHIFT)
75 60
76#define CLK_OUT_ENB_L 0x010 61#define TEGRA114_CLK_PERIPH_BANKS 5
77#define CLK_OUT_ENB_H 0x014
78#define CLK_OUT_ENB_U 0x018
79#define CLK_OUT_ENB_V 0x360
80#define CLK_OUT_ENB_W 0x364
81#define CLK_OUT_ENB_X 0x280
82#define CLK_OUT_ENB_SET_L 0x320
83#define CLK_OUT_ENB_CLR_L 0x324
84#define CLK_OUT_ENB_SET_H 0x328
85#define CLK_OUT_ENB_CLR_H 0x32c
86#define CLK_OUT_ENB_SET_U 0x330
87#define CLK_OUT_ENB_CLR_U 0x334
88#define CLK_OUT_ENB_SET_V 0x440
89#define CLK_OUT_ENB_CLR_V 0x444
90#define CLK_OUT_ENB_SET_W 0x448
91#define CLK_OUT_ENB_CLR_W 0x44c
92#define CLK_OUT_ENB_SET_X 0x284
93#define CLK_OUT_ENB_CLR_X 0x288
94#define CLK_OUT_ENB_NUM 6
95 62
96#define PLLC_BASE 0x80 63#define PLLC_BASE 0x80
97#define PLLC_MISC2 0x88 64#define PLLC_MISC2 0x88
@@ -139,25 +106,6 @@
139#define PLLE_AUX 0x48c 106#define PLLE_AUX 0x48c
140#define PLLC_OUT 0x84 107#define PLLC_OUT 0x84
141#define PLLM_OUT 0x94 108#define PLLM_OUT 0x94
142#define PLLP_OUTA 0xa4
143#define PLLP_OUTB 0xa8
144#define PLLA_OUT 0xb4
145
146#define AUDIO_SYNC_CLK_I2S0 0x4a0
147#define AUDIO_SYNC_CLK_I2S1 0x4a4
148#define AUDIO_SYNC_CLK_I2S2 0x4a8
149#define AUDIO_SYNC_CLK_I2S3 0x4ac
150#define AUDIO_SYNC_CLK_I2S4 0x4b0
151#define AUDIO_SYNC_CLK_SPDIF 0x4b4
152
153#define AUDIO_SYNC_DOUBLER 0x49c
154
155#define PMC_CLK_OUT_CNTRL 0x1a8
156#define PMC_DPD_PADS_ORIDE 0x1c
157#define PMC_DPD_PADS_ORIDE_BLINK_ENB 20
158#define PMC_CTRL 0
159#define PMC_CTRL_BLINK_ENB 7
160#define PMC_BLINK_TIMER 0x40
161 109
162#define OSC_CTRL 0x50 110#define OSC_CTRL 0x50
163#define OSC_CTRL_OSC_FREQ_SHIFT 28 111#define OSC_CTRL_OSC_FREQ_SHIFT 28
@@ -166,9 +114,6 @@
166#define PLLXC_SW_MAX_P 6 114#define PLLXC_SW_MAX_P 6
167 115
168#define CCLKG_BURST_POLICY 0x368 116#define CCLKG_BURST_POLICY 0x368
169#define CCLKLP_BURST_POLICY 0x370
170#define SCLK_BURST_POLICY 0x028
171#define SYSTEM_CLK_RATE 0x030
172 117
173#define UTMIP_PLL_CFG2 0x488 118#define UTMIP_PLL_CFG2 0x488
174#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6) 119#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6)
@@ -196,91 +141,8 @@
196#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1) 141#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1)
197#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0) 142#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0)
198 143
199#define CLK_SOURCE_I2S0 0x1d8
200#define CLK_SOURCE_I2S1 0x100
201#define CLK_SOURCE_I2S2 0x104
202#define CLK_SOURCE_NDFLASH 0x160
203#define CLK_SOURCE_I2S3 0x3bc
204#define CLK_SOURCE_I2S4 0x3c0
205#define CLK_SOURCE_SPDIF_OUT 0x108
206#define CLK_SOURCE_SPDIF_IN 0x10c
207#define CLK_SOURCE_PWM 0x110
208#define CLK_SOURCE_ADX 0x638
209#define CLK_SOURCE_AMX 0x63c
210#define CLK_SOURCE_HDA 0x428
211#define CLK_SOURCE_HDA2CODEC_2X 0x3e4
212#define CLK_SOURCE_SBC1 0x134
213#define CLK_SOURCE_SBC2 0x118
214#define CLK_SOURCE_SBC3 0x11c
215#define CLK_SOURCE_SBC4 0x1b4
216#define CLK_SOURCE_SBC5 0x3c8
217#define CLK_SOURCE_SBC6 0x3cc
218#define CLK_SOURCE_SATA_OOB 0x420
219#define CLK_SOURCE_SATA 0x424
220#define CLK_SOURCE_NDSPEED 0x3f8
221#define CLK_SOURCE_VFIR 0x168
222#define CLK_SOURCE_SDMMC1 0x150
223#define CLK_SOURCE_SDMMC2 0x154
224#define CLK_SOURCE_SDMMC3 0x1bc
225#define CLK_SOURCE_SDMMC4 0x164
226#define CLK_SOURCE_VDE 0x1c8
227#define CLK_SOURCE_CSITE 0x1d4 144#define CLK_SOURCE_CSITE 0x1d4
228#define CLK_SOURCE_LA 0x1f8
229#define CLK_SOURCE_TRACE 0x634
230#define CLK_SOURCE_OWR 0x1cc
231#define CLK_SOURCE_NOR 0x1d0
232#define CLK_SOURCE_MIPI 0x174
233#define CLK_SOURCE_I2C1 0x124
234#define CLK_SOURCE_I2C2 0x198
235#define CLK_SOURCE_I2C3 0x1b8
236#define CLK_SOURCE_I2C4 0x3c4
237#define CLK_SOURCE_I2C5 0x128
238#define CLK_SOURCE_UARTA 0x178
239#define CLK_SOURCE_UARTB 0x17c
240#define CLK_SOURCE_UARTC 0x1a0
241#define CLK_SOURCE_UARTD 0x1c0
242#define CLK_SOURCE_UARTE 0x1c4
243#define CLK_SOURCE_UARTA_DBG 0x178
244#define CLK_SOURCE_UARTB_DBG 0x17c
245#define CLK_SOURCE_UARTC_DBG 0x1a0
246#define CLK_SOURCE_UARTD_DBG 0x1c0
247#define CLK_SOURCE_UARTE_DBG 0x1c4
248#define CLK_SOURCE_3D 0x158
249#define CLK_SOURCE_2D 0x15c
250#define CLK_SOURCE_VI_SENSOR 0x1a8
251#define CLK_SOURCE_VI 0x148
252#define CLK_SOURCE_EPP 0x16c
253#define CLK_SOURCE_MSENC 0x1f0
254#define CLK_SOURCE_TSEC 0x1f4
255#define CLK_SOURCE_HOST1X 0x180
256#define CLK_SOURCE_HDMI 0x18c
257#define CLK_SOURCE_DISP1 0x138
258#define CLK_SOURCE_DISP2 0x13c
259#define CLK_SOURCE_CILAB 0x614
260#define CLK_SOURCE_CILCD 0x618
261#define CLK_SOURCE_CILE 0x61c
262#define CLK_SOURCE_DSIALP 0x620
263#define CLK_SOURCE_DSIBLP 0x624
264#define CLK_SOURCE_TSENSOR 0x3b8
265#define CLK_SOURCE_D_AUDIO 0x3d0
266#define CLK_SOURCE_DAM0 0x3d8
267#define CLK_SOURCE_DAM1 0x3dc
268#define CLK_SOURCE_DAM2 0x3e0
269#define CLK_SOURCE_ACTMON 0x3e8
270#define CLK_SOURCE_EXTERN1 0x3ec
271#define CLK_SOURCE_EXTERN2 0x3f0
272#define CLK_SOURCE_EXTERN3 0x3f4
273#define CLK_SOURCE_I2CSLOW 0x3fc
274#define CLK_SOURCE_SE 0x42c
275#define CLK_SOURCE_MSELECT 0x3b4
276#define CLK_SOURCE_DFLL_REF 0x62c
277#define CLK_SOURCE_DFLL_SOC 0x630
278#define CLK_SOURCE_SOC_THERM 0x644
279#define CLK_SOURCE_XUSB_HOST_SRC 0x600
280#define CLK_SOURCE_XUSB_FALCON_SRC 0x604
281#define CLK_SOURCE_XUSB_FS_SRC 0x608
282#define CLK_SOURCE_XUSB_SS_SRC 0x610 145#define CLK_SOURCE_XUSB_SS_SRC 0x610
283#define CLK_SOURCE_XUSB_DEV_SRC 0x60c
284#define CLK_SOURCE_EMC 0x19c 146#define CLK_SOURCE_EMC 0x19c
285 147
286/* PLLM override registers */ 148/* PLLM override registers */
@@ -298,19 +160,13 @@ static struct cpu_clk_suspend_context {
298} tegra114_cpu_clk_sctx; 160} tegra114_cpu_clk_sctx;
299#endif 161#endif
300 162
301static int periph_clk_enb_refcnt[CLK_OUT_ENB_NUM * 32];
302
303static void __iomem *clk_base; 163static void __iomem *clk_base;
304static void __iomem *pmc_base; 164static void __iomem *pmc_base;
305 165
306static DEFINE_SPINLOCK(pll_d_lock); 166static DEFINE_SPINLOCK(pll_d_lock);
307static DEFINE_SPINLOCK(pll_d2_lock); 167static DEFINE_SPINLOCK(pll_d2_lock);
308static DEFINE_SPINLOCK(pll_u_lock); 168static DEFINE_SPINLOCK(pll_u_lock);
309static DEFINE_SPINLOCK(pll_div_lock);
310static DEFINE_SPINLOCK(pll_re_lock); 169static DEFINE_SPINLOCK(pll_re_lock);
311static DEFINE_SPINLOCK(clk_doubler_lock);
312static DEFINE_SPINLOCK(clk_out_lock);
313static DEFINE_SPINLOCK(sysrate_lock);
314 170
315static struct div_nmp pllxc_nmp = { 171static struct div_nmp pllxc_nmp = {
316 .divm_shift = 0, 172 .divm_shift = 0,
@@ -370,6 +226,8 @@ static struct tegra_clk_pll_params pll_c_params = {
370 .stepb_shift = 9, 226 .stepb_shift = 9,
371 .pdiv_tohw = pllxc_p, 227 .pdiv_tohw = pllxc_p,
372 .div_nmp = &pllxc_nmp, 228 .div_nmp = &pllxc_nmp,
229 .freq_table = pll_c_freq_table,
230 .flags = TEGRA_PLL_USE_LOCK,
373}; 231};
374 232
375static struct div_nmp pllcx_nmp = { 233static struct div_nmp pllcx_nmp = {
@@ -417,6 +275,8 @@ static struct tegra_clk_pll_params pll_c2_params = {
417 .ext_misc_reg[0] = 0x4f0, 275 .ext_misc_reg[0] = 0x4f0,
418 .ext_misc_reg[1] = 0x4f4, 276 .ext_misc_reg[1] = 0x4f4,
419 .ext_misc_reg[2] = 0x4f8, 277 .ext_misc_reg[2] = 0x4f8,
278 .freq_table = pll_cx_freq_table,
279 .flags = TEGRA_PLL_USE_LOCK,
420}; 280};
421 281
422static struct tegra_clk_pll_params pll_c3_params = { 282static struct tegra_clk_pll_params pll_c3_params = {
@@ -437,6 +297,8 @@ static struct tegra_clk_pll_params pll_c3_params = {
437 .ext_misc_reg[0] = 0x504, 297 .ext_misc_reg[0] = 0x504,
438 .ext_misc_reg[1] = 0x508, 298 .ext_misc_reg[1] = 0x508,
439 .ext_misc_reg[2] = 0x50c, 299 .ext_misc_reg[2] = 0x50c,
300 .freq_table = pll_cx_freq_table,
301 .flags = TEGRA_PLL_USE_LOCK,
440}; 302};
441 303
442static struct div_nmp pllm_nmp = { 304static struct div_nmp pllm_nmp = {
@@ -483,6 +345,8 @@ static struct tegra_clk_pll_params pll_m_params = {
483 .div_nmp = &pllm_nmp, 345 .div_nmp = &pllm_nmp,
484 .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE, 346 .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,
485 .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2, 347 .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2,
348 .freq_table = pll_m_freq_table,
349 .flags = TEGRA_PLL_USE_LOCK,
486}; 350};
487 351
488static struct div_nmp pllp_nmp = { 352static struct div_nmp pllp_nmp = {
@@ -516,6 +380,9 @@ static struct tegra_clk_pll_params pll_p_params = {
516 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 380 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
517 .lock_delay = 300, 381 .lock_delay = 300,
518 .div_nmp = &pllp_nmp, 382 .div_nmp = &pllp_nmp,
383 .freq_table = pll_p_freq_table,
384 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK,
385 .fixed_rate = 408000000,
519}; 386};
520 387
521static struct tegra_clk_pll_freq_table pll_a_freq_table[] = { 388static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
@@ -543,6 +410,8 @@ static struct tegra_clk_pll_params pll_a_params = {
543 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 410 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
544 .lock_delay = 300, 411 .lock_delay = 300,
545 .div_nmp = &pllp_nmp, 412 .div_nmp = &pllp_nmp,
413 .freq_table = pll_a_freq_table,
414 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK,
546}; 415};
547 416
548static struct tegra_clk_pll_freq_table pll_d_freq_table[] = { 417static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
@@ -579,6 +448,9 @@ static struct tegra_clk_pll_params pll_d_params = {
579 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 448 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
580 .lock_delay = 1000, 449 .lock_delay = 1000,
581 .div_nmp = &pllp_nmp, 450 .div_nmp = &pllp_nmp,
451 .freq_table = pll_d_freq_table,
452 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
453 TEGRA_PLL_USE_LOCK,
582}; 454};
583 455
584static struct tegra_clk_pll_params pll_d2_params = { 456static struct tegra_clk_pll_params pll_d2_params = {
@@ -594,6 +466,9 @@ static struct tegra_clk_pll_params pll_d2_params = {
594 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 466 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
595 .lock_delay = 1000, 467 .lock_delay = 1000,
596 .div_nmp = &pllp_nmp, 468 .div_nmp = &pllp_nmp,
469 .freq_table = pll_d_freq_table,
470 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
471 TEGRA_PLL_USE_LOCK,
597}; 472};
598 473
599static struct pdiv_map pllu_p[] = { 474static struct pdiv_map pllu_p[] = {
@@ -634,6 +509,9 @@ static struct tegra_clk_pll_params pll_u_params = {
634 .lock_delay = 1000, 509 .lock_delay = 1000,
635 .pdiv_tohw = pllu_p, 510 .pdiv_tohw = pllu_p,
636 .div_nmp = &pllu_nmp, 511 .div_nmp = &pllu_nmp,
512 .freq_table = pll_u_freq_table,
513 .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
514 TEGRA_PLL_USE_LOCK,
637}; 515};
638 516
639static struct tegra_clk_pll_freq_table pll_x_freq_table[] = { 517static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
@@ -667,12 +545,15 @@ static struct tegra_clk_pll_params pll_x_params = {
667 .stepb_shift = 24, 545 .stepb_shift = 24,
668 .pdiv_tohw = pllxc_p, 546 .pdiv_tohw = pllxc_p,
669 .div_nmp = &pllxc_nmp, 547 .div_nmp = &pllxc_nmp,
548 .freq_table = pll_x_freq_table,
549 .flags = TEGRA_PLL_USE_LOCK,
670}; 550};
671 551
672static struct tegra_clk_pll_freq_table pll_e_freq_table[] = { 552static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
673 /* PLLE special case: use cpcon field to store cml divider value */ 553 /* PLLE special case: use cpcon field to store cml divider value */
674 {336000000, 100000000, 100, 21, 16, 11}, 554 {336000000, 100000000, 100, 21, 16, 11},
675 {312000000, 100000000, 200, 26, 24, 13}, 555 {312000000, 100000000, 200, 26, 24, 13},
556 {12000000, 100000000, 200, 1, 24, 13},
676 {0, 0, 0, 0, 0, 0}, 557 {0, 0, 0, 0, 0, 0},
677}; 558};
678 559
@@ -699,6 +580,9 @@ static struct tegra_clk_pll_params pll_e_params = {
699 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE, 580 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
700 .lock_delay = 300, 581 .lock_delay = 300,
701 .div_nmp = &plle_nmp, 582 .div_nmp = &plle_nmp,
583 .freq_table = pll_e_freq_table,
584 .flags = TEGRA_PLL_FIXED,
585 .fixed_rate = 100000000,
702}; 586};
703 587
704static struct div_nmp pllre_nmp = { 588static struct div_nmp pllre_nmp = {
@@ -725,53 +609,7 @@ static struct tegra_clk_pll_params pll_re_vco_params = {
725 .iddq_reg = PLLRE_MISC, 609 .iddq_reg = PLLRE_MISC,
726 .iddq_bit_idx = PLLRE_IDDQ_BIT, 610 .iddq_bit_idx = PLLRE_IDDQ_BIT,
727 .div_nmp = &pllre_nmp, 611 .div_nmp = &pllre_nmp,
728}; 612 .flags = TEGRA_PLL_USE_LOCK,
729
730/* Peripheral clock registers */
731
732static struct tegra_clk_periph_regs periph_l_regs = {
733 .enb_reg = CLK_OUT_ENB_L,
734 .enb_set_reg = CLK_OUT_ENB_SET_L,
735 .enb_clr_reg = CLK_OUT_ENB_CLR_L,
736 .rst_reg = RST_DEVICES_L,
737 .rst_set_reg = RST_DEVICES_SET_L,
738 .rst_clr_reg = RST_DEVICES_CLR_L,
739};
740
741static struct tegra_clk_periph_regs periph_h_regs = {
742 .enb_reg = CLK_OUT_ENB_H,
743 .enb_set_reg = CLK_OUT_ENB_SET_H,
744 .enb_clr_reg = CLK_OUT_ENB_CLR_H,
745 .rst_reg = RST_DEVICES_H,
746 .rst_set_reg = RST_DEVICES_SET_H,
747 .rst_clr_reg = RST_DEVICES_CLR_H,
748};
749
750static struct tegra_clk_periph_regs periph_u_regs = {
751 .enb_reg = CLK_OUT_ENB_U,
752 .enb_set_reg = CLK_OUT_ENB_SET_U,
753 .enb_clr_reg = CLK_OUT_ENB_CLR_U,
754 .rst_reg = RST_DEVICES_U,
755 .rst_set_reg = RST_DEVICES_SET_U,
756 .rst_clr_reg = RST_DEVICES_CLR_U,
757};
758
759static struct tegra_clk_periph_regs periph_v_regs = {
760 .enb_reg = CLK_OUT_ENB_V,
761 .enb_set_reg = CLK_OUT_ENB_SET_V,
762 .enb_clr_reg = CLK_OUT_ENB_CLR_V,
763 .rst_reg = RST_DEVICES_V,
764 .rst_set_reg = RST_DEVICES_SET_V,
765 .rst_clr_reg = RST_DEVICES_CLR_V,
766};
767
768static struct tegra_clk_periph_regs periph_w_regs = {
769 .enb_reg = CLK_OUT_ENB_W,
770 .enb_set_reg = CLK_OUT_ENB_SET_W,
771 .enb_clr_reg = CLK_OUT_ENB_CLR_W,
772 .rst_reg = RST_DEVICES_W,
773 .rst_set_reg = RST_DEVICES_SET_W,
774 .rst_clr_reg = RST_DEVICES_CLR_W,
775}; 613};
776 614
777/* possible OSC frequencies in Hz */ 615/* possible OSC frequencies in Hz */
@@ -787,120 +625,6 @@ static unsigned long tegra114_input_freq[] = {
787 625
788#define MASK(x) (BIT(x) - 1) 626#define MASK(x) (BIT(x) - 1)
789 627
790#define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset, \
791 _clk_num, _regs, _gate_flags, _clk_id) \
792 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
793 30, MASK(2), 0, 0, 8, 1, 0, _regs, _clk_num, \
794 periph_clk_enb_refcnt, _gate_flags, _clk_id, \
795 _parents##_idx, 0)
796
797#define TEGRA_INIT_DATA_MUX_FLAGS(_name, _con_id, _dev_id, _parents, _offset,\
798 _clk_num, _regs, _gate_flags, _clk_id, flags)\
799 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
800 30, MASK(2), 0, 0, 8, 1, 0, _regs, _clk_num, \
801 periph_clk_enb_refcnt, _gate_flags, _clk_id, \
802 _parents##_idx, flags)
803
804#define TEGRA_INIT_DATA_MUX8(_name, _con_id, _dev_id, _parents, _offset, \
805 _clk_num, _regs, _gate_flags, _clk_id) \
806 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
807 29, MASK(3), 0, 0, 8, 1, 0, _regs, _clk_num, \
808 periph_clk_enb_refcnt, _gate_flags, _clk_id, \
809 _parents##_idx, 0)
810
811#define TEGRA_INIT_DATA_INT(_name, _con_id, _dev_id, _parents, _offset, \
812 _clk_num, _regs, _gate_flags, _clk_id) \
813 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
814 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs,\
815 _clk_num, periph_clk_enb_refcnt, _gate_flags, \
816 _clk_id, _parents##_idx, 0)
817
818#define TEGRA_INIT_DATA_INT_FLAGS(_name, _con_id, _dev_id, _parents, _offset,\
819 _clk_num, _regs, _gate_flags, _clk_id, flags)\
820 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
821 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs,\
822 _clk_num, periph_clk_enb_refcnt, _gate_flags, \
823 _clk_id, _parents##_idx, flags)
824
825#define TEGRA_INIT_DATA_INT8(_name, _con_id, _dev_id, _parents, _offset,\
826 _clk_num, _regs, _gate_flags, _clk_id) \
827 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
828 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs,\
829 _clk_num, periph_clk_enb_refcnt, _gate_flags, \
830 _clk_id, _parents##_idx, 0)
831
832#define TEGRA_INIT_DATA_UART(_name, _con_id, _dev_id, _parents, _offset,\
833 _clk_num, _regs, _clk_id) \
834 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
835 30, MASK(2), 0, 0, 16, 1, TEGRA_DIVIDER_UART, _regs,\
836 _clk_num, periph_clk_enb_refcnt, 0, _clk_id, \
837 _parents##_idx, 0)
838
839#define TEGRA_INIT_DATA_I2C(_name, _con_id, _dev_id, _parents, _offset,\
840 _clk_num, _regs, _clk_id) \
841 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
842 30, MASK(2), 0, 0, 16, 0, 0, _regs, _clk_num, \
843 periph_clk_enb_refcnt, 0, _clk_id, _parents##_idx, 0)
844
845#define TEGRA_INIT_DATA_NODIV(_name, _con_id, _dev_id, _parents, _offset, \
846 _mux_shift, _mux_mask, _clk_num, _regs, \
847 _gate_flags, _clk_id) \
848 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
849 _mux_shift, _mux_mask, 0, 0, 0, 0, 0, _regs, \
850 _clk_num, periph_clk_enb_refcnt, _gate_flags, \
851 _clk_id, _parents##_idx, 0)
852
853#define TEGRA_INIT_DATA_XUSB(_name, _con_id, _dev_id, _parents, _offset, \
854 _clk_num, _regs, _gate_flags, _clk_id) \
855 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset, \
856 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs, \
857 _clk_num, periph_clk_enb_refcnt, _gate_flags, \
858 _clk_id, _parents##_idx, 0)
859
860#define TEGRA_INIT_DATA_AUDIO(_name, _con_id, _dev_id, _offset, _clk_num,\
861 _regs, _gate_flags, _clk_id) \
862 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, mux_d_audio_clk, \
863 _offset, 16, 0xE01F, 0, 0, 8, 1, 0, _regs, _clk_num, \
864 periph_clk_enb_refcnt, _gate_flags , _clk_id, \
865 mux_d_audio_clk_idx, 0)
866
867enum tegra114_clk {
868 rtc = 4, timer = 5, uarta = 6, sdmmc2 = 9, i2s1 = 11, i2c1 = 12,
869 ndflash = 13, sdmmc1 = 14, sdmmc4 = 15, pwm = 17, i2s2 = 18, epp = 19,
870 gr_2d = 21, usbd = 22, isp = 23, gr_3d = 24, disp2 = 26, disp1 = 27,
871 host1x = 28, vcp = 29, i2s0 = 30, apbdma = 34, kbc = 36, kfuse = 40,
872 sbc1 = 41, nor = 42, sbc2 = 44, sbc3 = 46, i2c5 = 47, dsia = 48,
873 mipi = 50, hdmi = 51, csi = 52, i2c2 = 54, uartc = 55, mipi_cal = 56,
874 emc, usb2, usb3, vde = 61, bsea = 62, bsev = 63, uartd = 65,
875 i2c3 = 67, sbc4 = 68, sdmmc3 = 69, owr = 71, csite = 73,
876 la = 76, trace = 77, soc_therm = 78, dtv = 79, ndspeed = 80,
877 i2cslow = 81, dsib = 82, tsec = 83, xusb_host = 89, msenc = 91,
878 csus = 92, mselect = 99, tsensor = 100, i2s3 = 101, i2s4 = 102,
879 i2c4 = 103, sbc5 = 104, sbc6 = 105, d_audio, apbif = 107, dam0, dam1,
880 dam2, hda2codec_2x = 111, audio0_2x = 113, audio1_2x, audio2_2x,
881 audio3_2x, audio4_2x, spdif_2x, actmon = 119, extern1 = 120,
882 extern2 = 121, extern3 = 122, hda = 125, se = 127, hda2hdmi = 128,
883 cilab = 144, cilcd = 145, cile = 146, dsialp = 147, dsiblp = 148,
884 dds = 150, dp2 = 152, amx = 153, adx = 154, xusb_ss = 156, uartb = 192,
885 vfir, spdif_in, spdif_out, vi, vi_sensor, fuse, fuse_burn, clk_32k,
886 clk_m, clk_m_div2, clk_m_div4, pll_ref, pll_c, pll_c_out1, pll_c2,
887 pll_c3, pll_m, pll_m_out1, pll_p, pll_p_out1, pll_p_out2, pll_p_out3,
888 pll_p_out4, pll_a, pll_a_out0, pll_d, pll_d_out0, pll_d2, pll_d2_out0,
889 pll_u, pll_u_480M, pll_u_60M, pll_u_48M, pll_u_12M, pll_x, pll_x_out0,
890 pll_re_vco, pll_re_out, pll_e_out0, spdif_in_sync, i2s0_sync,
891 i2s1_sync, i2s2_sync, i2s3_sync, i2s4_sync, vimclk_sync, audio0,
892 audio1, audio2, audio3, audio4, spdif, clk_out_1, clk_out_2, clk_out_3,
893 blink, xusb_host_src = 252, xusb_falcon_src, xusb_fs_src, xusb_ss_src,
894 xusb_dev_src, xusb_dev, xusb_hs_src, sclk, hclk, pclk, cclk_g, cclk_lp,
895 dfll_ref = 264, dfll_soc,
896
897 /* Mux clocks */
898
899 audio0_mux = 300, audio1_mux, audio2_mux, audio3_mux, audio4_mux,
900 spdif_mux, clk_out_1_mux, clk_out_2_mux, clk_out_3_mux, dsia_mux,
901 dsib_mux, clk_max,
902};
903
904struct utmi_clk_param { 628struct utmi_clk_param {
905 /* Oscillator Frequency in KHz */ 629 /* Oscillator Frequency in KHz */
906 u32 osc_frequency; 630 u32 osc_frequency;
@@ -934,122 +658,11 @@ static const struct utmi_clk_param utmi_parameters[] = {
934 658
935/* peripheral mux definitions */ 659/* peripheral mux definitions */
936 660
937#define MUX_I2S_SPDIF(_id) \
938static const char *mux_pllaout0_##_id##_2x_pllp_clkm[] = { "pll_a_out0", \
939 #_id, "pll_p",\
940 "clk_m"};
941MUX_I2S_SPDIF(audio0)
942MUX_I2S_SPDIF(audio1)
943MUX_I2S_SPDIF(audio2)
944MUX_I2S_SPDIF(audio3)
945MUX_I2S_SPDIF(audio4)
946MUX_I2S_SPDIF(audio)
947
948#define mux_pllaout0_audio0_2x_pllp_clkm_idx NULL
949#define mux_pllaout0_audio1_2x_pllp_clkm_idx NULL
950#define mux_pllaout0_audio2_2x_pllp_clkm_idx NULL
951#define mux_pllaout0_audio3_2x_pllp_clkm_idx NULL
952#define mux_pllaout0_audio4_2x_pllp_clkm_idx NULL
953#define mux_pllaout0_audio_2x_pllp_clkm_idx NULL
954
955static const char *mux_pllp_pllc_pllm_clkm[] = {
956 "pll_p", "pll_c", "pll_m", "clk_m"
957};
958#define mux_pllp_pllc_pllm_clkm_idx NULL
959
960static const char *mux_pllp_pllc_pllm[] = { "pll_p", "pll_c", "pll_m" };
961#define mux_pllp_pllc_pllm_idx NULL
962
963static const char *mux_pllp_pllc_clk32_clkm[] = {
964 "pll_p", "pll_c", "clk_32k", "clk_m"
965};
966#define mux_pllp_pllc_clk32_clkm_idx NULL
967
968static const char *mux_plla_pllc_pllp_clkm[] = {
969 "pll_a_out0", "pll_c", "pll_p", "clk_m"
970};
971#define mux_plla_pllc_pllp_clkm_idx mux_pllp_pllc_pllm_clkm_idx
972
973static const char *mux_pllp_pllc2_c_c3_pllm_clkm[] = {
974 "pll_p", "pll_c2", "pll_c", "pll_c3", "pll_m", "clk_m"
975};
976static u32 mux_pllp_pllc2_c_c3_pllm_clkm_idx[] = {
977 [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6,
978};
979
980static const char *mux_pllp_clkm[] = {
981 "pll_p", "clk_m"
982};
983static u32 mux_pllp_clkm_idx[] = {
984 [0] = 0, [1] = 3,
985};
986
987static const char *mux_pllm_pllc2_c_c3_pllp_plla[] = {
988 "pll_m", "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a_out0"
989};
990#define mux_pllm_pllc2_c_c3_pllp_plla_idx mux_pllp_pllc2_c_c3_pllm_clkm_idx
991
992static const char *mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = {
993 "pll_p", "pll_m", "pll_d_out0", "pll_a_out0", "pll_c",
994 "pll_d2_out0", "clk_m"
995};
996#define mux_pllp_pllm_plld_plla_pllc_plld2_clkm_idx NULL
997
998static const char *mux_pllm_pllc_pllp_plla[] = {
999 "pll_m", "pll_c", "pll_p", "pll_a_out0"
1000};
1001#define mux_pllm_pllc_pllp_plla_idx mux_pllp_pllc_pllm_clkm_idx
1002
1003static const char *mux_pllp_pllc_clkm[] = {
1004 "pll_p", "pll_c", "pll_m"
1005};
1006static u32 mux_pllp_pllc_clkm_idx[] = {
1007 [0] = 0, [1] = 1, [2] = 3,
1008};
1009
1010static const char *mux_pllp_pllc_clkm_clk32[] = {
1011 "pll_p", "pll_c", "clk_m", "clk_32k"
1012};
1013#define mux_pllp_pllc_clkm_clk32_idx NULL
1014
1015static const char *mux_plla_clk32_pllp_clkm_plle[] = {
1016 "pll_a_out0", "clk_32k", "pll_p", "clk_m", "pll_e_out0"
1017};
1018#define mux_plla_clk32_pllp_clkm_plle_idx NULL
1019
1020static const char *mux_clkm_pllp_pllc_pllre[] = {
1021 "clk_m", "pll_p", "pll_c", "pll_re_out"
1022};
1023static u32 mux_clkm_pllp_pllc_pllre_idx[] = {
1024 [0] = 0, [1] = 1, [2] = 3, [3] = 5,
1025};
1026
1027static const char *mux_clkm_48M_pllp_480M[] = {
1028 "clk_m", "pll_u_48M", "pll_p", "pll_u_480M"
1029};
1030#define mux_clkm_48M_pllp_480M_idx NULL
1031
1032static const char *mux_clkm_pllre_clk32_480M_pllc_ref[] = {
1033 "clk_m", "pll_re_out", "clk_32k", "pll_u_480M", "pll_c", "pll_ref"
1034};
1035static u32 mux_clkm_pllre_clk32_480M_pllc_ref_idx[] = {
1036 [0] = 0, [1] = 1, [2] = 3, [3] = 3, [4] = 4, [5] = 7,
1037};
1038
1039static const char *mux_plld_out0_plld2_out0[] = { 661static const char *mux_plld_out0_plld2_out0[] = {
1040 "pll_d_out0", "pll_d2_out0", 662 "pll_d_out0", "pll_d2_out0",
1041}; 663};
1042#define mux_plld_out0_plld2_out0_idx NULL 664#define mux_plld_out0_plld2_out0_idx NULL
1043 665
1044static const char *mux_d_audio_clk[] = {
1045 "pll_a_out0", "pll_p", "clk_m", "spdif_in_sync", "i2s0_sync",
1046 "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync",
1047};
1048static u32 mux_d_audio_clk_idx[] = {
1049 [0] = 0, [1] = 0x8000, [2] = 0xc000, [3] = 0xE000, [4] = 0xE001,
1050 [5] = 0xE002, [6] = 0xE003, [7] = 0xE004, [8] = 0xE005, [9] = 0xE007,
1051};
1052
1053static const char *mux_pllmcp_clkm[] = { 666static const char *mux_pllmcp_clkm[] = {
1054 "pll_m_out0", "pll_c_out0", "pll_p_out0", "clk_m", "pll_m_ud", 667 "pll_m_out0", "pll_c_out0", "pll_p_out0", "clk_m", "pll_m_ud",
1055}; 668};
@@ -1064,8 +677,253 @@ static const struct clk_div_table pll_re_div_table[] = {
1064 { .val = 0, .div = 0 }, 677 { .val = 0, .div = 0 },
1065}; 678};
1066 679
1067static struct clk *clks[clk_max]; 680static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = {
1068static struct clk_onecell_data clk_data; 681 [tegra_clk_rtc] = { .dt_id = TEGRA114_CLK_RTC, .present = true },
682 [tegra_clk_timer] = { .dt_id = TEGRA114_CLK_TIMER, .present = true },
683 [tegra_clk_uarta] = { .dt_id = TEGRA114_CLK_UARTA, .present = true },
684 [tegra_clk_uartd] = { .dt_id = TEGRA114_CLK_UARTD, .present = true },
685 [tegra_clk_sdmmc2] = { .dt_id = TEGRA114_CLK_SDMMC2, .present = true },
686 [tegra_clk_i2s1] = { .dt_id = TEGRA114_CLK_I2S1, .present = true },
687 [tegra_clk_i2c1] = { .dt_id = TEGRA114_CLK_I2C1, .present = true },
688 [tegra_clk_ndflash] = { .dt_id = TEGRA114_CLK_NDFLASH, .present = true },
689 [tegra_clk_sdmmc1] = { .dt_id = TEGRA114_CLK_SDMMC1, .present = true },
690 [tegra_clk_sdmmc4] = { .dt_id = TEGRA114_CLK_SDMMC4, .present = true },
691 [tegra_clk_pwm] = { .dt_id = TEGRA114_CLK_PWM, .present = true },
692 [tegra_clk_i2s0] = { .dt_id = TEGRA114_CLK_I2S0, .present = true },
693 [tegra_clk_i2s2] = { .dt_id = TEGRA114_CLK_I2S2, .present = true },
694 [tegra_clk_epp_8] = { .dt_id = TEGRA114_CLK_EPP, .present = true },
695 [tegra_clk_gr2d_8] = { .dt_id = TEGRA114_CLK_GR2D, .present = true },
696 [tegra_clk_usbd] = { .dt_id = TEGRA114_CLK_USBD, .present = true },
697 [tegra_clk_isp] = { .dt_id = TEGRA114_CLK_ISP, .present = true },
698 [tegra_clk_gr3d_8] = { .dt_id = TEGRA114_CLK_GR3D, .present = true },
699 [tegra_clk_disp2] = { .dt_id = TEGRA114_CLK_DISP2, .present = true },
700 [tegra_clk_disp1] = { .dt_id = TEGRA114_CLK_DISP1, .present = true },
701 [tegra_clk_host1x_8] = { .dt_id = TEGRA114_CLK_HOST1X, .present = true },
702 [tegra_clk_vcp] = { .dt_id = TEGRA114_CLK_VCP, .present = true },
703 [tegra_clk_apbdma] = { .dt_id = TEGRA114_CLK_APBDMA, .present = true },
704 [tegra_clk_kbc] = { .dt_id = TEGRA114_CLK_KBC, .present = true },
705 [tegra_clk_kfuse] = { .dt_id = TEGRA114_CLK_KFUSE, .present = true },
706 [tegra_clk_sbc1_8] = { .dt_id = TEGRA114_CLK_SBC1, .present = true },
707 [tegra_clk_nor] = { .dt_id = TEGRA114_CLK_NOR, .present = true },
708 [tegra_clk_sbc2_8] = { .dt_id = TEGRA114_CLK_SBC2, .present = true },
709 [tegra_clk_sbc3_8] = { .dt_id = TEGRA114_CLK_SBC3, .present = true },
710 [tegra_clk_i2c5] = { .dt_id = TEGRA114_CLK_I2C5, .present = true },
711 [tegra_clk_dsia] = { .dt_id = TEGRA114_CLK_DSIA, .present = true },
712 [tegra_clk_mipi] = { .dt_id = TEGRA114_CLK_MIPI, .present = true },
713 [tegra_clk_hdmi] = { .dt_id = TEGRA114_CLK_HDMI, .present = true },
714 [tegra_clk_csi] = { .dt_id = TEGRA114_CLK_CSI, .present = true },
715 [tegra_clk_i2c2] = { .dt_id = TEGRA114_CLK_I2C2, .present = true },
716 [tegra_clk_uartc] = { .dt_id = TEGRA114_CLK_UARTC, .present = true },
717 [tegra_clk_mipi_cal] = { .dt_id = TEGRA114_CLK_MIPI_CAL, .present = true },
718 [tegra_clk_emc] = { .dt_id = TEGRA114_CLK_EMC, .present = true },
719 [tegra_clk_usb2] = { .dt_id = TEGRA114_CLK_USB2, .present = true },
720 [tegra_clk_usb3] = { .dt_id = TEGRA114_CLK_USB3, .present = true },
721 [tegra_clk_vde_8] = { .dt_id = TEGRA114_CLK_VDE, .present = true },
722 [tegra_clk_bsea] = { .dt_id = TEGRA114_CLK_BSEA, .present = true },
723 [tegra_clk_bsev] = { .dt_id = TEGRA114_CLK_BSEV, .present = true },
724 [tegra_clk_i2c3] = { .dt_id = TEGRA114_CLK_I2C3, .present = true },
725 [tegra_clk_sbc4_8] = { .dt_id = TEGRA114_CLK_SBC4, .present = true },
726 [tegra_clk_sdmmc3] = { .dt_id = TEGRA114_CLK_SDMMC3, .present = true },
727 [tegra_clk_owr] = { .dt_id = TEGRA114_CLK_OWR, .present = true },
728 [tegra_clk_csite] = { .dt_id = TEGRA114_CLK_CSITE, .present = true },
729 [tegra_clk_la] = { .dt_id = TEGRA114_CLK_LA, .present = true },
730 [tegra_clk_trace] = { .dt_id = TEGRA114_CLK_TRACE, .present = true },
731 [tegra_clk_soc_therm] = { .dt_id = TEGRA114_CLK_SOC_THERM, .present = true },
732 [tegra_clk_dtv] = { .dt_id = TEGRA114_CLK_DTV, .present = true },
733 [tegra_clk_ndspeed] = { .dt_id = TEGRA114_CLK_NDSPEED, .present = true },
734 [tegra_clk_i2cslow] = { .dt_id = TEGRA114_CLK_I2CSLOW, .present = true },
735 [tegra_clk_dsib] = { .dt_id = TEGRA114_CLK_DSIB, .present = true },
736 [tegra_clk_tsec] = { .dt_id = TEGRA114_CLK_TSEC, .present = true },
737 [tegra_clk_xusb_host] = { .dt_id = TEGRA114_CLK_XUSB_HOST, .present = true },
738 [tegra_clk_msenc] = { .dt_id = TEGRA114_CLK_MSENC, .present = true },
739 [tegra_clk_csus] = { .dt_id = TEGRA114_CLK_CSUS, .present = true },
740 [tegra_clk_mselect] = { .dt_id = TEGRA114_CLK_MSELECT, .present = true },
741 [tegra_clk_tsensor] = { .dt_id = TEGRA114_CLK_TSENSOR, .present = true },
742 [tegra_clk_i2s3] = { .dt_id = TEGRA114_CLK_I2S3, .present = true },
743 [tegra_clk_i2s4] = { .dt_id = TEGRA114_CLK_I2S4, .present = true },
744 [tegra_clk_i2c4] = { .dt_id = TEGRA114_CLK_I2C4, .present = true },
745 [tegra_clk_sbc5_8] = { .dt_id = TEGRA114_CLK_SBC5, .present = true },
746 [tegra_clk_sbc6_8] = { .dt_id = TEGRA114_CLK_SBC6, .present = true },
747 [tegra_clk_d_audio] = { .dt_id = TEGRA114_CLK_D_AUDIO, .present = true },
748 [tegra_clk_apbif] = { .dt_id = TEGRA114_CLK_APBIF, .present = true },
749 [tegra_clk_dam0] = { .dt_id = TEGRA114_CLK_DAM0, .present = true },
750 [tegra_clk_dam1] = { .dt_id = TEGRA114_CLK_DAM1, .present = true },
751 [tegra_clk_dam2] = { .dt_id = TEGRA114_CLK_DAM2, .present = true },
752 [tegra_clk_hda2codec_2x] = { .dt_id = TEGRA114_CLK_HDA2CODEC_2X, .present = true },
753 [tegra_clk_audio0_2x] = { .dt_id = TEGRA114_CLK_AUDIO0_2X, .present = true },
754 [tegra_clk_audio1_2x] = { .dt_id = TEGRA114_CLK_AUDIO1_2X, .present = true },
755 [tegra_clk_audio2_2x] = { .dt_id = TEGRA114_CLK_AUDIO2_2X, .present = true },
756 [tegra_clk_audio3_2x] = { .dt_id = TEGRA114_CLK_AUDIO3_2X, .present = true },
757 [tegra_clk_audio4_2x] = { .dt_id = TEGRA114_CLK_AUDIO4_2X, .present = true },
758 [tegra_clk_spdif_2x] = { .dt_id = TEGRA114_CLK_SPDIF_2X, .present = true },
759 [tegra_clk_actmon] = { .dt_id = TEGRA114_CLK_ACTMON, .present = true },
760 [tegra_clk_extern1] = { .dt_id = TEGRA114_CLK_EXTERN1, .present = true },
761 [tegra_clk_extern2] = { .dt_id = TEGRA114_CLK_EXTERN2, .present = true },
762 [tegra_clk_extern3] = { .dt_id = TEGRA114_CLK_EXTERN3, .present = true },
763 [tegra_clk_hda] = { .dt_id = TEGRA114_CLK_HDA, .present = true },
764 [tegra_clk_se] = { .dt_id = TEGRA114_CLK_SE, .present = true },
765 [tegra_clk_hda2hdmi] = { .dt_id = TEGRA114_CLK_HDA2HDMI, .present = true },
766 [tegra_clk_cilab] = { .dt_id = TEGRA114_CLK_CILAB, .present = true },
767 [tegra_clk_cilcd] = { .dt_id = TEGRA114_CLK_CILCD, .present = true },
768 [tegra_clk_cile] = { .dt_id = TEGRA114_CLK_CILE, .present = true },
769 [tegra_clk_dsialp] = { .dt_id = TEGRA114_CLK_DSIALP, .present = true },
770 [tegra_clk_dsiblp] = { .dt_id = TEGRA114_CLK_DSIBLP, .present = true },
771 [tegra_clk_dds] = { .dt_id = TEGRA114_CLK_DDS, .present = true },
772 [tegra_clk_dp2] = { .dt_id = TEGRA114_CLK_DP2, .present = true },
773 [tegra_clk_amx] = { .dt_id = TEGRA114_CLK_AMX, .present = true },
774 [tegra_clk_adx] = { .dt_id = TEGRA114_CLK_ADX, .present = true },
775 [tegra_clk_xusb_ss] = { .dt_id = TEGRA114_CLK_XUSB_SS, .present = true },
776 [tegra_clk_uartb] = { .dt_id = TEGRA114_CLK_UARTB, .present = true },
777 [tegra_clk_vfir] = { .dt_id = TEGRA114_CLK_VFIR, .present = true },
778 [tegra_clk_spdif_in] = { .dt_id = TEGRA114_CLK_SPDIF_IN, .present = true },
779 [tegra_clk_spdif_out] = { .dt_id = TEGRA114_CLK_SPDIF_OUT, .present = true },
780 [tegra_clk_vi_8] = { .dt_id = TEGRA114_CLK_VI, .present = true },
781 [tegra_clk_vi_sensor_8] = { .dt_id = TEGRA114_CLK_VI_SENSOR, .present = true },
782 [tegra_clk_fuse] = { .dt_id = TEGRA114_CLK_FUSE, .present = true },
783 [tegra_clk_fuse_burn] = { .dt_id = TEGRA114_CLK_FUSE_BURN, .present = true },
784 [tegra_clk_clk_32k] = { .dt_id = TEGRA114_CLK_CLK_32K, .present = true },
785 [tegra_clk_clk_m] = { .dt_id = TEGRA114_CLK_CLK_M, .present = true },
786 [tegra_clk_clk_m_div2] = { .dt_id = TEGRA114_CLK_CLK_M_DIV2, .present = true },
787 [tegra_clk_clk_m_div4] = { .dt_id = TEGRA114_CLK_CLK_M_DIV4, .present = true },
788 [tegra_clk_pll_ref] = { .dt_id = TEGRA114_CLK_PLL_REF, .present = true },
789 [tegra_clk_pll_c] = { .dt_id = TEGRA114_CLK_PLL_C, .present = true },
790 [tegra_clk_pll_c_out1] = { .dt_id = TEGRA114_CLK_PLL_C_OUT1, .present = true },
791 [tegra_clk_pll_c2] = { .dt_id = TEGRA114_CLK_PLL_C2, .present = true },
792 [tegra_clk_pll_c3] = { .dt_id = TEGRA114_CLK_PLL_C3, .present = true },
793 [tegra_clk_pll_m] = { .dt_id = TEGRA114_CLK_PLL_M, .present = true },
794 [tegra_clk_pll_m_out1] = { .dt_id = TEGRA114_CLK_PLL_M_OUT1, .present = true },
795 [tegra_clk_pll_p] = { .dt_id = TEGRA114_CLK_PLL_P, .present = true },
796 [tegra_clk_pll_p_out1] = { .dt_id = TEGRA114_CLK_PLL_P_OUT1, .present = true },
797 [tegra_clk_pll_p_out2_int] = { .dt_id = TEGRA114_CLK_PLL_P_OUT2, .present = true },
798 [tegra_clk_pll_p_out3] = { .dt_id = TEGRA114_CLK_PLL_P_OUT3, .present = true },
799 [tegra_clk_pll_p_out4] = { .dt_id = TEGRA114_CLK_PLL_P_OUT4, .present = true },
800 [tegra_clk_pll_a] = { .dt_id = TEGRA114_CLK_PLL_A, .present = true },
801 [tegra_clk_pll_a_out0] = { .dt_id = TEGRA114_CLK_PLL_A_OUT0, .present = true },
802 [tegra_clk_pll_d] = { .dt_id = TEGRA114_CLK_PLL_D, .present = true },
803 [tegra_clk_pll_d_out0] = { .dt_id = TEGRA114_CLK_PLL_D_OUT0, .present = true },
804 [tegra_clk_pll_d2] = { .dt_id = TEGRA114_CLK_PLL_D2, .present = true },
805 [tegra_clk_pll_d2_out0] = { .dt_id = TEGRA114_CLK_PLL_D2_OUT0, .present = true },
806 [tegra_clk_pll_u] = { .dt_id = TEGRA114_CLK_PLL_U, .present = true },
807 [tegra_clk_pll_u_480m] = { .dt_id = TEGRA114_CLK_PLL_U_480M, .present = true },
808 [tegra_clk_pll_u_60m] = { .dt_id = TEGRA114_CLK_PLL_U_60M, .present = true },
809 [tegra_clk_pll_u_48m] = { .dt_id = TEGRA114_CLK_PLL_U_48M, .present = true },
810 [tegra_clk_pll_u_12m] = { .dt_id = TEGRA114_CLK_PLL_U_12M, .present = true },
811 [tegra_clk_pll_x] = { .dt_id = TEGRA114_CLK_PLL_X, .present = true },
812 [tegra_clk_pll_x_out0] = { .dt_id = TEGRA114_CLK_PLL_X_OUT0, .present = true },
813 [tegra_clk_pll_re_vco] = { .dt_id = TEGRA114_CLK_PLL_RE_VCO, .present = true },
814 [tegra_clk_pll_re_out] = { .dt_id = TEGRA114_CLK_PLL_RE_OUT, .present = true },
815 [tegra_clk_pll_e_out0] = { .dt_id = TEGRA114_CLK_PLL_E_OUT0, .present = true },
816 [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA114_CLK_SPDIF_IN_SYNC, .present = true },
817 [tegra_clk_i2s0_sync] = { .dt_id = TEGRA114_CLK_I2S0_SYNC, .present = true },
818 [tegra_clk_i2s1_sync] = { .dt_id = TEGRA114_CLK_I2S1_SYNC, .present = true },
819 [tegra_clk_i2s2_sync] = { .dt_id = TEGRA114_CLK_I2S2_SYNC, .present = true },
820 [tegra_clk_i2s3_sync] = { .dt_id = TEGRA114_CLK_I2S3_SYNC, .present = true },
821 [tegra_clk_i2s4_sync] = { .dt_id = TEGRA114_CLK_I2S4_SYNC, .present = true },
822 [tegra_clk_vimclk_sync] = { .dt_id = TEGRA114_CLK_VIMCLK_SYNC, .present = true },
823 [tegra_clk_audio0] = { .dt_id = TEGRA114_CLK_AUDIO0, .present = true },
824 [tegra_clk_audio1] = { .dt_id = TEGRA114_CLK_AUDIO1, .present = true },
825 [tegra_clk_audio2] = { .dt_id = TEGRA114_CLK_AUDIO2, .present = true },
826 [tegra_clk_audio3] = { .dt_id = TEGRA114_CLK_AUDIO3, .present = true },
827 [tegra_clk_audio4] = { .dt_id = TEGRA114_CLK_AUDIO4, .present = true },
828 [tegra_clk_spdif] = { .dt_id = TEGRA114_CLK_SPDIF, .present = true },
829 [tegra_clk_clk_out_1] = { .dt_id = TEGRA114_CLK_CLK_OUT_1, .present = true },
830 [tegra_clk_clk_out_2] = { .dt_id = TEGRA114_CLK_CLK_OUT_2, .present = true },
831 [tegra_clk_clk_out_3] = { .dt_id = TEGRA114_CLK_CLK_OUT_3, .present = true },
832 [tegra_clk_blink] = { .dt_id = TEGRA114_CLK_BLINK, .present = true },
833 [tegra_clk_xusb_host_src] = { .dt_id = TEGRA114_CLK_XUSB_HOST_SRC, .present = true },
834 [tegra_clk_xusb_falcon_src] = { .dt_id = TEGRA114_CLK_XUSB_FALCON_SRC, .present = true },
835 [tegra_clk_xusb_fs_src] = { .dt_id = TEGRA114_CLK_XUSB_FS_SRC, .present = true },
836 [tegra_clk_xusb_ss_src] = { .dt_id = TEGRA114_CLK_XUSB_SS_SRC, .present = true },
837 [tegra_clk_xusb_dev_src] = { .dt_id = TEGRA114_CLK_XUSB_DEV_SRC, .present = true },
838 [tegra_clk_xusb_dev] = { .dt_id = TEGRA114_CLK_XUSB_DEV, .present = true },
839 [tegra_clk_xusb_hs_src] = { .dt_id = TEGRA114_CLK_XUSB_HS_SRC, .present = true },
840 [tegra_clk_sclk] = { .dt_id = TEGRA114_CLK_SCLK, .present = true },
841 [tegra_clk_hclk] = { .dt_id = TEGRA114_CLK_HCLK, .present = true },
842 [tegra_clk_pclk] = { .dt_id = TEGRA114_CLK_PCLK, .present = true },
843 [tegra_clk_cclk_g] = { .dt_id = TEGRA114_CLK_CCLK_G, .present = true },
844 [tegra_clk_cclk_lp] = { .dt_id = TEGRA114_CLK_CCLK_LP, .present = true },
845 [tegra_clk_dfll_ref] = { .dt_id = TEGRA114_CLK_DFLL_REF, .present = true },
846 [tegra_clk_dfll_soc] = { .dt_id = TEGRA114_CLK_DFLL_SOC, .present = true },
847 [tegra_clk_audio0_mux] = { .dt_id = TEGRA114_CLK_AUDIO0_MUX, .present = true },
848 [tegra_clk_audio1_mux] = { .dt_id = TEGRA114_CLK_AUDIO1_MUX, .present = true },
849 [tegra_clk_audio2_mux] = { .dt_id = TEGRA114_CLK_AUDIO2_MUX, .present = true },
850 [tegra_clk_audio3_mux] = { .dt_id = TEGRA114_CLK_AUDIO3_MUX, .present = true },
851 [tegra_clk_audio4_mux] = { .dt_id = TEGRA114_CLK_AUDIO4_MUX, .present = true },
852 [tegra_clk_spdif_mux] = { .dt_id = TEGRA114_CLK_SPDIF_MUX, .present = true },
853 [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA114_CLK_CLK_OUT_1_MUX, .present = true },
854 [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA114_CLK_CLK_OUT_2_MUX, .present = true },
855 [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA114_CLK_CLK_OUT_3_MUX, .present = true },
856 [tegra_clk_dsia_mux] = { .dt_id = TEGRA114_CLK_DSIA_MUX, .present = true },
857 [tegra_clk_dsib_mux] = { .dt_id = TEGRA114_CLK_DSIB_MUX, .present = true },
858};
859
860static struct tegra_devclk devclks[] __initdata = {
861 { .con_id = "clk_m", .dt_id = TEGRA114_CLK_CLK_M },
862 { .con_id = "pll_ref", .dt_id = TEGRA114_CLK_PLL_REF },
863 { .con_id = "clk_32k", .dt_id = TEGRA114_CLK_CLK_32K },
864 { .con_id = "clk_m_div2", .dt_id = TEGRA114_CLK_CLK_M_DIV2 },
865 { .con_id = "clk_m_div4", .dt_id = TEGRA114_CLK_CLK_M_DIV4 },
866 { .con_id = "pll_c", .dt_id = TEGRA114_CLK_PLL_C },
867 { .con_id = "pll_c_out1", .dt_id = TEGRA114_CLK_PLL_C_OUT1 },
868 { .con_id = "pll_c2", .dt_id = TEGRA114_CLK_PLL_C2 },
869 { .con_id = "pll_c3", .dt_id = TEGRA114_CLK_PLL_C3 },
870 { .con_id = "pll_p", .dt_id = TEGRA114_CLK_PLL_P },
871 { .con_id = "pll_p_out1", .dt_id = TEGRA114_CLK_PLL_P_OUT1 },
872 { .con_id = "pll_p_out2", .dt_id = TEGRA114_CLK_PLL_P_OUT2 },
873 { .con_id = "pll_p_out3", .dt_id = TEGRA114_CLK_PLL_P_OUT3 },
874 { .con_id = "pll_p_out4", .dt_id = TEGRA114_CLK_PLL_P_OUT4 },
875 { .con_id = "pll_m", .dt_id = TEGRA114_CLK_PLL_M },
876 { .con_id = "pll_m_out1", .dt_id = TEGRA114_CLK_PLL_M_OUT1 },
877 { .con_id = "pll_x", .dt_id = TEGRA114_CLK_PLL_X },
878 { .con_id = "pll_x_out0", .dt_id = TEGRA114_CLK_PLL_X_OUT0 },
879 { .con_id = "pll_u", .dt_id = TEGRA114_CLK_PLL_U },
880 { .con_id = "pll_u_480M", .dt_id = TEGRA114_CLK_PLL_U_480M },
881 { .con_id = "pll_u_60M", .dt_id = TEGRA114_CLK_PLL_U_60M },
882 { .con_id = "pll_u_48M", .dt_id = TEGRA114_CLK_PLL_U_48M },
883 { .con_id = "pll_u_12M", .dt_id = TEGRA114_CLK_PLL_U_12M },
884 { .con_id = "pll_d", .dt_id = TEGRA114_CLK_PLL_D },
885 { .con_id = "pll_d_out0", .dt_id = TEGRA114_CLK_PLL_D_OUT0 },
886 { .con_id = "pll_d2", .dt_id = TEGRA114_CLK_PLL_D2 },
887 { .con_id = "pll_d2_out0", .dt_id = TEGRA114_CLK_PLL_D2_OUT0 },
888 { .con_id = "pll_a", .dt_id = TEGRA114_CLK_PLL_A },
889 { .con_id = "pll_a_out0", .dt_id = TEGRA114_CLK_PLL_A_OUT0 },
890 { .con_id = "pll_re_vco", .dt_id = TEGRA114_CLK_PLL_RE_VCO },
891 { .con_id = "pll_re_out", .dt_id = TEGRA114_CLK_PLL_RE_OUT },
892 { .con_id = "pll_e_out0", .dt_id = TEGRA114_CLK_PLL_E_OUT0 },
893 { .con_id = "spdif_in_sync", .dt_id = TEGRA114_CLK_SPDIF_IN_SYNC },
894 { .con_id = "i2s0_sync", .dt_id = TEGRA114_CLK_I2S0_SYNC },
895 { .con_id = "i2s1_sync", .dt_id = TEGRA114_CLK_I2S1_SYNC },
896 { .con_id = "i2s2_sync", .dt_id = TEGRA114_CLK_I2S2_SYNC },
897 { .con_id = "i2s3_sync", .dt_id = TEGRA114_CLK_I2S3_SYNC },
898 { .con_id = "i2s4_sync", .dt_id = TEGRA114_CLK_I2S4_SYNC },
899 { .con_id = "vimclk_sync", .dt_id = TEGRA114_CLK_VIMCLK_SYNC },
900 { .con_id = "audio0", .dt_id = TEGRA114_CLK_AUDIO0 },
901 { .con_id = "audio1", .dt_id = TEGRA114_CLK_AUDIO1 },
902 { .con_id = "audio2", .dt_id = TEGRA114_CLK_AUDIO2 },
903 { .con_id = "audio3", .dt_id = TEGRA114_CLK_AUDIO3 },
904 { .con_id = "audio4", .dt_id = TEGRA114_CLK_AUDIO4 },
905 { .con_id = "spdif", .dt_id = TEGRA114_CLK_SPDIF },
906 { .con_id = "audio0_2x", .dt_id = TEGRA114_CLK_AUDIO0_2X },
907 { .con_id = "audio1_2x", .dt_id = TEGRA114_CLK_AUDIO1_2X },
908 { .con_id = "audio2_2x", .dt_id = TEGRA114_CLK_AUDIO2_2X },
909 { .con_id = "audio3_2x", .dt_id = TEGRA114_CLK_AUDIO3_2X },
910 { .con_id = "audio4_2x", .dt_id = TEGRA114_CLK_AUDIO4_2X },
911 { .con_id = "spdif_2x", .dt_id = TEGRA114_CLK_SPDIF_2X },
912 { .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA114_CLK_EXTERN1 },
913 { .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA114_CLK_EXTERN2 },
914 { .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA114_CLK_EXTERN3 },
915 { .con_id = "blink", .dt_id = TEGRA114_CLK_BLINK },
916 { .con_id = "cclk_g", .dt_id = TEGRA114_CLK_CCLK_G },
917 { .con_id = "cclk_lp", .dt_id = TEGRA114_CLK_CCLK_LP },
918 { .con_id = "sclk", .dt_id = TEGRA114_CLK_SCLK },
919 { .con_id = "hclk", .dt_id = TEGRA114_CLK_HCLK },
920 { .con_id = "pclk", .dt_id = TEGRA114_CLK_PCLK },
921 { .con_id = "fuse", .dt_id = TEGRA114_CLK_FUSE },
922 { .dev_id = "rtc-tegra", .dt_id = TEGRA114_CLK_RTC },
923 { .dev_id = "timer", .dt_id = TEGRA114_CLK_TIMER },
924};
925
926static struct clk **clks;
1069 927
1070static unsigned long osc_freq; 928static unsigned long osc_freq;
1071static unsigned long pll_ref_freq; 929static unsigned long pll_ref_freq;
@@ -1086,16 +944,14 @@ static int __init tegra114_osc_clk_init(void __iomem *clk_base)
1086 /* clk_m */ 944 /* clk_m */
1087 clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT, 945 clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT,
1088 osc_freq); 946 osc_freq);
1089 clk_register_clkdev(clk, "clk_m", NULL); 947 clks[TEGRA114_CLK_CLK_M] = clk;
1090 clks[clk_m] = clk;
1091 948
1092 /* pll_ref */ 949 /* pll_ref */
1093 val = (val >> OSC_CTRL_PLL_REF_DIV_SHIFT) & 3; 950 val = (val >> OSC_CTRL_PLL_REF_DIV_SHIFT) & 3;
1094 pll_ref_div = 1 << val; 951 pll_ref_div = 1 << val;
1095 clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m", 952 clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m",
1096 CLK_SET_RATE_PARENT, 1, pll_ref_div); 953 CLK_SET_RATE_PARENT, 1, pll_ref_div);
1097 clk_register_clkdev(clk, "pll_ref", NULL); 954 clks[TEGRA114_CLK_PLL_REF] = clk;
1098 clks[pll_ref] = clk;
1099 955
1100 pll_ref_freq = osc_freq / pll_ref_div; 956 pll_ref_freq = osc_freq / pll_ref_div;
1101 957
@@ -1109,20 +965,17 @@ static void __init tegra114_fixed_clk_init(void __iomem *clk_base)
1109 /* clk_32k */ 965 /* clk_32k */
1110 clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, CLK_IS_ROOT, 966 clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, CLK_IS_ROOT,
1111 32768); 967 32768);
1112 clk_register_clkdev(clk, "clk_32k", NULL); 968 clks[TEGRA114_CLK_CLK_32K] = clk;
1113 clks[clk_32k] = clk;
1114 969
1115 /* clk_m_div2 */ 970 /* clk_m_div2 */
1116 clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m", 971 clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m",
1117 CLK_SET_RATE_PARENT, 1, 2); 972 CLK_SET_RATE_PARENT, 1, 2);
1118 clk_register_clkdev(clk, "clk_m_div2", NULL); 973 clks[TEGRA114_CLK_CLK_M_DIV2] = clk;
1119 clks[clk_m_div2] = clk;
1120 974
1121 /* clk_m_div4 */ 975 /* clk_m_div4 */
1122 clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m", 976 clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m",
1123 CLK_SET_RATE_PARENT, 1, 4); 977 CLK_SET_RATE_PARENT, 1, 4);
1124 clk_register_clkdev(clk, "clk_m_div4", NULL); 978 clks[TEGRA114_CLK_CLK_M_DIV4] = clk;
1125 clks[clk_m_div4] = clk;
1126 979
1127} 980}
1128 981
@@ -1208,63 +1061,6 @@ static __init void tegra114_utmi_param_configure(void __iomem *clk_base)
1208 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); 1061 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
1209} 1062}
1210 1063
1211static void __init _clip_vco_min(struct tegra_clk_pll_params *pll_params)
1212{
1213 pll_params->vco_min =
1214 DIV_ROUND_UP(pll_params->vco_min, pll_ref_freq) * pll_ref_freq;
1215}
1216
1217static int __init _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params,
1218 void __iomem *clk_base)
1219{
1220 u32 val;
1221 u32 step_a, step_b;
1222
1223 switch (pll_ref_freq) {
1224 case 12000000:
1225 case 13000000:
1226 case 26000000:
1227 step_a = 0x2B;
1228 step_b = 0x0B;
1229 break;
1230 case 16800000:
1231 step_a = 0x1A;
1232 step_b = 0x09;
1233 break;
1234 case 19200000:
1235 step_a = 0x12;
1236 step_b = 0x08;
1237 break;
1238 default:
1239 pr_err("%s: Unexpected reference rate %lu\n",
1240 __func__, pll_ref_freq);
1241 WARN_ON(1);
1242 return -EINVAL;
1243 }
1244
1245 val = step_a << pll_params->stepa_shift;
1246 val |= step_b << pll_params->stepb_shift;
1247 writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg);
1248
1249 return 0;
1250}
1251
1252static void __init _init_iddq(struct tegra_clk_pll_params *pll_params,
1253 void __iomem *clk_base)
1254{
1255 u32 val, val_iddq;
1256
1257 val = readl_relaxed(clk_base + pll_params->base_reg);
1258 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
1259
1260 if (val & BIT(30))
1261 WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx));
1262 else {
1263 val_iddq |= BIT(pll_params->iddq_bit_idx);
1264 writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg);
1265 }
1266}
1267
1268static void __init tegra114_pll_init(void __iomem *clk_base, 1064static void __init tegra114_pll_init(void __iomem *clk_base,
1269 void __iomem *pmc) 1065 void __iomem *pmc)
1270{ 1066{
@@ -1272,104 +1068,34 @@ static void __init tegra114_pll_init(void __iomem *clk_base,
1272 struct clk *clk; 1068 struct clk *clk;
1273 1069
1274 /* PLLC */ 1070 /* PLLC */
1275 _clip_vco_min(&pll_c_params); 1071 clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base,
1276 if (_setup_dynamic_ramp(&pll_c_params, clk_base) >= 0) { 1072 pmc, 0, &pll_c_params, NULL);
1277 _init_iddq(&pll_c_params, clk_base); 1073 clks[TEGRA114_CLK_PLL_C] = clk;
1278 clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base, 1074
1279 pmc, 0, 0, &pll_c_params, TEGRA_PLL_USE_LOCK, 1075 /* PLLC_OUT1 */
1280 pll_c_freq_table, NULL); 1076 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
1281 clk_register_clkdev(clk, "pll_c", NULL); 1077 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
1282 clks[pll_c] = clk; 1078 8, 8, 1, NULL);
1283 1079 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
1284 /* PLLC_OUT1 */ 1080 clk_base + PLLC_OUT, 1, 0,
1285 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c", 1081 CLK_SET_RATE_PARENT, 0, NULL);
1286 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 1082 clks[TEGRA114_CLK_PLL_C_OUT1] = clk;
1287 8, 8, 1, NULL);
1288 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
1289 clk_base + PLLC_OUT, 1, 0,
1290 CLK_SET_RATE_PARENT, 0, NULL);
1291 clk_register_clkdev(clk, "pll_c_out1", NULL);
1292 clks[pll_c_out1] = clk;
1293 }
1294 1083
1295 /* PLLC2 */ 1084 /* PLLC2 */
1296 _clip_vco_min(&pll_c2_params); 1085 clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0,
1297 clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0, 0, 1086 &pll_c2_params, NULL);
1298 &pll_c2_params, TEGRA_PLL_USE_LOCK, 1087 clks[TEGRA114_CLK_PLL_C2] = clk;
1299 pll_cx_freq_table, NULL);
1300 clk_register_clkdev(clk, "pll_c2", NULL);
1301 clks[pll_c2] = clk;
1302 1088
1303 /* PLLC3 */ 1089 /* PLLC3 */
1304 _clip_vco_min(&pll_c3_params); 1090 clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0,
1305 clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0, 0, 1091 &pll_c3_params, NULL);
1306 &pll_c3_params, TEGRA_PLL_USE_LOCK, 1092 clks[TEGRA114_CLK_PLL_C3] = clk;
1307 pll_cx_freq_table, NULL);
1308 clk_register_clkdev(clk, "pll_c3", NULL);
1309 clks[pll_c3] = clk;
1310
1311 /* PLLP */
1312 clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base, pmc, 0,
1313 408000000, &pll_p_params,
1314 TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK,
1315 pll_p_freq_table, NULL);
1316 clk_register_clkdev(clk, "pll_p", NULL);
1317 clks[pll_p] = clk;
1318
1319 /* PLLP_OUT1 */
1320 clk = tegra_clk_register_divider("pll_p_out1_div", "pll_p",
1321 clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED |
1322 TEGRA_DIVIDER_ROUND_UP, 8, 8, 1, &pll_div_lock);
1323 clk = tegra_clk_register_pll_out("pll_p_out1", "pll_p_out1_div",
1324 clk_base + PLLP_OUTA, 1, 0,
1325 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
1326 &pll_div_lock);
1327 clk_register_clkdev(clk, "pll_p_out1", NULL);
1328 clks[pll_p_out1] = clk;
1329
1330 /* PLLP_OUT2 */
1331 clk = tegra_clk_register_divider("pll_p_out2_div", "pll_p",
1332 clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED |
1333 TEGRA_DIVIDER_ROUND_UP | TEGRA_DIVIDER_INT, 24,
1334 8, 1, &pll_div_lock);
1335 clk = tegra_clk_register_pll_out("pll_p_out2", "pll_p_out2_div",
1336 clk_base + PLLP_OUTA, 17, 16,
1337 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
1338 &pll_div_lock);
1339 clk_register_clkdev(clk, "pll_p_out2", NULL);
1340 clks[pll_p_out2] = clk;
1341
1342 /* PLLP_OUT3 */
1343 clk = tegra_clk_register_divider("pll_p_out3_div", "pll_p",
1344 clk_base + PLLP_OUTB, 0, TEGRA_DIVIDER_FIXED |
1345 TEGRA_DIVIDER_ROUND_UP, 8, 8, 1, &pll_div_lock);
1346 clk = tegra_clk_register_pll_out("pll_p_out3", "pll_p_out3_div",
1347 clk_base + PLLP_OUTB, 1, 0,
1348 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
1349 &pll_div_lock);
1350 clk_register_clkdev(clk, "pll_p_out3", NULL);
1351 clks[pll_p_out3] = clk;
1352
1353 /* PLLP_OUT4 */
1354 clk = tegra_clk_register_divider("pll_p_out4_div", "pll_p",
1355 clk_base + PLLP_OUTB, 0, TEGRA_DIVIDER_FIXED |
1356 TEGRA_DIVIDER_ROUND_UP, 24, 8, 1,
1357 &pll_div_lock);
1358 clk = tegra_clk_register_pll_out("pll_p_out4", "pll_p_out4_div",
1359 clk_base + PLLP_OUTB, 17, 16,
1360 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
1361 &pll_div_lock);
1362 clk_register_clkdev(clk, "pll_p_out4", NULL);
1363 clks[pll_p_out4] = clk;
1364 1093
1365 /* PLLM */ 1094 /* PLLM */
1366 _clip_vco_min(&pll_m_params);
1367 clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc, 1095 clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc,
1368 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE, 0, 1096 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
1369 &pll_m_params, TEGRA_PLL_USE_LOCK, 1097 &pll_m_params, NULL);
1370 pll_m_freq_table, NULL); 1098 clks[TEGRA114_CLK_PLL_M] = clk;
1371 clk_register_clkdev(clk, "pll_m", NULL);
1372 clks[pll_m] = clk;
1373 1099
1374 /* PLLM_OUT1 */ 1100 /* PLLM_OUT1 */
1375 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m", 1101 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
@@ -1378,41 +1104,20 @@ static void __init tegra114_pll_init(void __iomem *clk_base,
1378 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div", 1104 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
1379 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED | 1105 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |
1380 CLK_SET_RATE_PARENT, 0, NULL); 1106 CLK_SET_RATE_PARENT, 0, NULL);
1381 clk_register_clkdev(clk, "pll_m_out1", NULL); 1107 clks[TEGRA114_CLK_PLL_M_OUT1] = clk;
1382 clks[pll_m_out1] = clk;
1383 1108
1384 /* PLLM_UD */ 1109 /* PLLM_UD */
1385 clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m", 1110 clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m",
1386 CLK_SET_RATE_PARENT, 1, 1); 1111 CLK_SET_RATE_PARENT, 1, 1);
1387 1112
1388 /* PLLX */
1389 _clip_vco_min(&pll_x_params);
1390 if (_setup_dynamic_ramp(&pll_x_params, clk_base) >= 0) {
1391 _init_iddq(&pll_x_params, clk_base);
1392 clk = tegra_clk_register_pllxc("pll_x", "pll_ref", clk_base,
1393 pmc, CLK_IGNORE_UNUSED, 0, &pll_x_params,
1394 TEGRA_PLL_USE_LOCK, pll_x_freq_table, NULL);
1395 clk_register_clkdev(clk, "pll_x", NULL);
1396 clks[pll_x] = clk;
1397 }
1398
1399 /* PLLX_OUT0 */
1400 clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x",
1401 CLK_SET_RATE_PARENT, 1, 2);
1402 clk_register_clkdev(clk, "pll_x_out0", NULL);
1403 clks[pll_x_out0] = clk;
1404
1405 /* PLLU */ 1113 /* PLLU */
1406 val = readl(clk_base + pll_u_params.base_reg); 1114 val = readl(clk_base + pll_u_params.base_reg);
1407 val &= ~BIT(24); /* disable PLLU_OVERRIDE */ 1115 val &= ~BIT(24); /* disable PLLU_OVERRIDE */
1408 writel(val, clk_base + pll_u_params.base_reg); 1116 writel(val, clk_base + pll_u_params.base_reg);
1409 1117
1410 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc, 0, 1118 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc, 0,
1411 0, &pll_u_params, TEGRA_PLLU | 1119 &pll_u_params, &pll_u_lock);
1412 TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | 1120 clks[TEGRA114_CLK_PLL_U] = clk;
1413 TEGRA_PLL_USE_LOCK, pll_u_freq_table, &pll_u_lock);
1414 clk_register_clkdev(clk, "pll_u", NULL);
1415 clks[pll_u] = clk;
1416 1121
1417 tegra114_utmi_param_configure(clk_base); 1122 tegra114_utmi_param_configure(clk_base);
1418 1123
@@ -1420,731 +1125,97 @@ static void __init tegra114_pll_init(void __iomem *clk_base,
1420 clk = clk_register_gate(NULL, "pll_u_480M", "pll_u", 1125 clk = clk_register_gate(NULL, "pll_u_480M", "pll_u",
1421 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, 1126 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
1422 22, 0, &pll_u_lock); 1127 22, 0, &pll_u_lock);
1423 clk_register_clkdev(clk, "pll_u_480M", NULL); 1128 clks[TEGRA114_CLK_PLL_U_480M] = clk;
1424 clks[pll_u_480M] = clk;
1425 1129
1426 /* PLLU_60M */ 1130 /* PLLU_60M */
1427 clk = clk_register_fixed_factor(NULL, "pll_u_60M", "pll_u", 1131 clk = clk_register_fixed_factor(NULL, "pll_u_60M", "pll_u",
1428 CLK_SET_RATE_PARENT, 1, 8); 1132 CLK_SET_RATE_PARENT, 1, 8);
1429 clk_register_clkdev(clk, "pll_u_60M", NULL); 1133 clks[TEGRA114_CLK_PLL_U_60M] = clk;
1430 clks[pll_u_60M] = clk;
1431 1134
1432 /* PLLU_48M */ 1135 /* PLLU_48M */
1433 clk = clk_register_fixed_factor(NULL, "pll_u_48M", "pll_u", 1136 clk = clk_register_fixed_factor(NULL, "pll_u_48M", "pll_u",
1434 CLK_SET_RATE_PARENT, 1, 10); 1137 CLK_SET_RATE_PARENT, 1, 10);
1435 clk_register_clkdev(clk, "pll_u_48M", NULL); 1138 clks[TEGRA114_CLK_PLL_U_48M] = clk;
1436 clks[pll_u_48M] = clk;
1437 1139
1438 /* PLLU_12M */ 1140 /* PLLU_12M */
1439 clk = clk_register_fixed_factor(NULL, "pll_u_12M", "pll_u", 1141 clk = clk_register_fixed_factor(NULL, "pll_u_12M", "pll_u",
1440 CLK_SET_RATE_PARENT, 1, 40); 1142 CLK_SET_RATE_PARENT, 1, 40);
1441 clk_register_clkdev(clk, "pll_u_12M", NULL); 1143 clks[TEGRA114_CLK_PLL_U_12M] = clk;
1442 clks[pll_u_12M] = clk;
1443 1144
1444 /* PLLD */ 1145 /* PLLD */
1445 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0, 1146 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0,
1446 0, &pll_d_params, 1147 &pll_d_params, &pll_d_lock);
1447 TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | 1148 clks[TEGRA114_CLK_PLL_D] = clk;
1448 TEGRA_PLL_USE_LOCK, pll_d_freq_table, &pll_d_lock);
1449 clk_register_clkdev(clk, "pll_d", NULL);
1450 clks[pll_d] = clk;
1451 1149
1452 /* PLLD_OUT0 */ 1150 /* PLLD_OUT0 */
1453 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d", 1151 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
1454 CLK_SET_RATE_PARENT, 1, 2); 1152 CLK_SET_RATE_PARENT, 1, 2);
1455 clk_register_clkdev(clk, "pll_d_out0", NULL); 1153 clks[TEGRA114_CLK_PLL_D_OUT0] = clk;
1456 clks[pll_d_out0] = clk;
1457 1154
1458 /* PLLD2 */ 1155 /* PLLD2 */
1459 clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc, 0, 1156 clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc, 0,
1460 0, &pll_d2_params, 1157 &pll_d2_params, &pll_d2_lock);
1461 TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | 1158 clks[TEGRA114_CLK_PLL_D2] = clk;
1462 TEGRA_PLL_USE_LOCK, pll_d_freq_table, &pll_d2_lock);
1463 clk_register_clkdev(clk, "pll_d2", NULL);
1464 clks[pll_d2] = clk;
1465 1159
1466 /* PLLD2_OUT0 */ 1160 /* PLLD2_OUT0 */
1467 clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2", 1161 clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
1468 CLK_SET_RATE_PARENT, 1, 2); 1162 CLK_SET_RATE_PARENT, 1, 2);
1469 clk_register_clkdev(clk, "pll_d2_out0", NULL); 1163 clks[TEGRA114_CLK_PLL_D2_OUT0] = clk;
1470 clks[pll_d2_out0] = clk;
1471
1472 /* PLLA */
1473 clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, pmc, 0,
1474 0, &pll_a_params, TEGRA_PLL_HAS_CPCON |
1475 TEGRA_PLL_USE_LOCK, pll_a_freq_table, NULL);
1476 clk_register_clkdev(clk, "pll_a", NULL);
1477 clks[pll_a] = clk;
1478
1479 /* PLLA_OUT0 */
1480 clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a",
1481 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
1482 8, 8, 1, NULL);
1483 clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div",
1484 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED |
1485 CLK_SET_RATE_PARENT, 0, NULL);
1486 clk_register_clkdev(clk, "pll_a_out0", NULL);
1487 clks[pll_a_out0] = clk;
1488 1164
1489 /* PLLRE */ 1165 /* PLLRE */
1490 _clip_vco_min(&pll_re_vco_params);
1491 clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc, 1166 clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc,
1492 0, 0, &pll_re_vco_params, TEGRA_PLL_USE_LOCK, 1167 0, &pll_re_vco_params, &pll_re_lock, pll_ref_freq);
1493 NULL, &pll_re_lock, pll_ref_freq); 1168 clks[TEGRA114_CLK_PLL_RE_VCO] = clk;
1494 clk_register_clkdev(clk, "pll_re_vco", NULL);
1495 clks[pll_re_vco] = clk;
1496 1169
1497 clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0, 1170 clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0,
1498 clk_base + PLLRE_BASE, 16, 4, 0, 1171 clk_base + PLLRE_BASE, 16, 4, 0,
1499 pll_re_div_table, &pll_re_lock); 1172 pll_re_div_table, &pll_re_lock);
1500 clk_register_clkdev(clk, "pll_re_out", NULL); 1173 clks[TEGRA114_CLK_PLL_RE_OUT] = clk;
1501 clks[pll_re_out] = clk;
1502 1174
1503 /* PLLE */ 1175 /* PLLE */
1504 clk = tegra_clk_register_plle_tegra114("pll_e_out0", "pll_re_vco", 1176 clk = tegra_clk_register_plle_tegra114("pll_e_out0", "pll_ref",
1505 clk_base, 0, 100000000, &pll_e_params, 1177 clk_base, 0, &pll_e_params, NULL);
1506 pll_e_freq_table, NULL); 1178 clks[TEGRA114_CLK_PLL_E_OUT0] = clk;
1507 clk_register_clkdev(clk, "pll_e_out0", NULL);
1508 clks[pll_e_out0] = clk;
1509}
1510
1511static const char *mux_audio_sync_clk[] = { "spdif_in_sync", "i2s0_sync",
1512 "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync",
1513};
1514
1515static const char *clk_out1_parents[] = { "clk_m", "clk_m_div2",
1516 "clk_m_div4", "extern1",
1517};
1518
1519static const char *clk_out2_parents[] = { "clk_m", "clk_m_div2",
1520 "clk_m_div4", "extern2",
1521};
1522
1523static const char *clk_out3_parents[] = { "clk_m", "clk_m_div2",
1524 "clk_m_div4", "extern3",
1525};
1526
1527static void __init tegra114_audio_clk_init(void __iomem *clk_base)
1528{
1529 struct clk *clk;
1530
1531 /* spdif_in_sync */
1532 clk = tegra_clk_register_sync_source("spdif_in_sync", 24000000,
1533 24000000);
1534 clk_register_clkdev(clk, "spdif_in_sync", NULL);
1535 clks[spdif_in_sync] = clk;
1536
1537 /* i2s0_sync */
1538 clk = tegra_clk_register_sync_source("i2s0_sync", 24000000, 24000000);
1539 clk_register_clkdev(clk, "i2s0_sync", NULL);
1540 clks[i2s0_sync] = clk;
1541
1542 /* i2s1_sync */
1543 clk = tegra_clk_register_sync_source("i2s1_sync", 24000000, 24000000);
1544 clk_register_clkdev(clk, "i2s1_sync", NULL);
1545 clks[i2s1_sync] = clk;
1546
1547 /* i2s2_sync */
1548 clk = tegra_clk_register_sync_source("i2s2_sync", 24000000, 24000000);
1549 clk_register_clkdev(clk, "i2s2_sync", NULL);
1550 clks[i2s2_sync] = clk;
1551
1552 /* i2s3_sync */
1553 clk = tegra_clk_register_sync_source("i2s3_sync", 24000000, 24000000);
1554 clk_register_clkdev(clk, "i2s3_sync", NULL);
1555 clks[i2s3_sync] = clk;
1556
1557 /* i2s4_sync */
1558 clk = tegra_clk_register_sync_source("i2s4_sync", 24000000, 24000000);
1559 clk_register_clkdev(clk, "i2s4_sync", NULL);
1560 clks[i2s4_sync] = clk;
1561
1562 /* vimclk_sync */
1563 clk = tegra_clk_register_sync_source("vimclk_sync", 24000000, 24000000);
1564 clk_register_clkdev(clk, "vimclk_sync", NULL);
1565 clks[vimclk_sync] = clk;
1566
1567 /* audio0 */
1568 clk = clk_register_mux(NULL, "audio0_mux", mux_audio_sync_clk,
1569 ARRAY_SIZE(mux_audio_sync_clk),
1570 CLK_SET_RATE_NO_REPARENT,
1571 clk_base + AUDIO_SYNC_CLK_I2S0, 0, 3, 0,
1572 NULL);
1573 clks[audio0_mux] = clk;
1574 clk = clk_register_gate(NULL, "audio0", "audio0_mux", 0,
1575 clk_base + AUDIO_SYNC_CLK_I2S0, 4,
1576 CLK_GATE_SET_TO_DISABLE, NULL);
1577 clk_register_clkdev(clk, "audio0", NULL);
1578 clks[audio0] = clk;
1579
1580 /* audio1 */
1581 clk = clk_register_mux(NULL, "audio1_mux", mux_audio_sync_clk,
1582 ARRAY_SIZE(mux_audio_sync_clk),
1583 CLK_SET_RATE_NO_REPARENT,
1584 clk_base + AUDIO_SYNC_CLK_I2S1, 0, 3, 0,
1585 NULL);
1586 clks[audio1_mux] = clk;
1587 clk = clk_register_gate(NULL, "audio1", "audio1_mux", 0,
1588 clk_base + AUDIO_SYNC_CLK_I2S1, 4,
1589 CLK_GATE_SET_TO_DISABLE, NULL);
1590 clk_register_clkdev(clk, "audio1", NULL);
1591 clks[audio1] = clk;
1592
1593 /* audio2 */
1594 clk = clk_register_mux(NULL, "audio2_mux", mux_audio_sync_clk,
1595 ARRAY_SIZE(mux_audio_sync_clk),
1596 CLK_SET_RATE_NO_REPARENT,
1597 clk_base + AUDIO_SYNC_CLK_I2S2, 0, 3, 0,
1598 NULL);
1599 clks[audio2_mux] = clk;
1600 clk = clk_register_gate(NULL, "audio2", "audio2_mux", 0,
1601 clk_base + AUDIO_SYNC_CLK_I2S2, 4,
1602 CLK_GATE_SET_TO_DISABLE, NULL);
1603 clk_register_clkdev(clk, "audio2", NULL);
1604 clks[audio2] = clk;
1605
1606 /* audio3 */
1607 clk = clk_register_mux(NULL, "audio3_mux", mux_audio_sync_clk,
1608 ARRAY_SIZE(mux_audio_sync_clk),
1609 CLK_SET_RATE_NO_REPARENT,
1610 clk_base + AUDIO_SYNC_CLK_I2S3, 0, 3, 0,
1611 NULL);
1612 clks[audio3_mux] = clk;
1613 clk = clk_register_gate(NULL, "audio3", "audio3_mux", 0,
1614 clk_base + AUDIO_SYNC_CLK_I2S3, 4,
1615 CLK_GATE_SET_TO_DISABLE, NULL);
1616 clk_register_clkdev(clk, "audio3", NULL);
1617 clks[audio3] = clk;
1618
1619 /* audio4 */
1620 clk = clk_register_mux(NULL, "audio4_mux", mux_audio_sync_clk,
1621 ARRAY_SIZE(mux_audio_sync_clk),
1622 CLK_SET_RATE_NO_REPARENT,
1623 clk_base + AUDIO_SYNC_CLK_I2S4, 0, 3, 0,
1624 NULL);
1625 clks[audio4_mux] = clk;
1626 clk = clk_register_gate(NULL, "audio4", "audio4_mux", 0,
1627 clk_base + AUDIO_SYNC_CLK_I2S4, 4,
1628 CLK_GATE_SET_TO_DISABLE, NULL);
1629 clk_register_clkdev(clk, "audio4", NULL);
1630 clks[audio4] = clk;
1631
1632 /* spdif */
1633 clk = clk_register_mux(NULL, "spdif_mux", mux_audio_sync_clk,
1634 ARRAY_SIZE(mux_audio_sync_clk),
1635 CLK_SET_RATE_NO_REPARENT,
1636 clk_base + AUDIO_SYNC_CLK_SPDIF, 0, 3, 0,
1637 NULL);
1638 clks[spdif_mux] = clk;
1639 clk = clk_register_gate(NULL, "spdif", "spdif_mux", 0,
1640 clk_base + AUDIO_SYNC_CLK_SPDIF, 4,
1641 CLK_GATE_SET_TO_DISABLE, NULL);
1642 clk_register_clkdev(clk, "spdif", NULL);
1643 clks[spdif] = clk;
1644
1645 /* audio0_2x */
1646 clk = clk_register_fixed_factor(NULL, "audio0_doubler", "audio0",
1647 CLK_SET_RATE_PARENT, 2, 1);
1648 clk = tegra_clk_register_divider("audio0_div", "audio0_doubler",
1649 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 24, 1,
1650 0, &clk_doubler_lock);
1651 clk = tegra_clk_register_periph_gate("audio0_2x", "audio0_div",
1652 TEGRA_PERIPH_NO_RESET, clk_base,
1653 CLK_SET_RATE_PARENT, 113, &periph_v_regs,
1654 periph_clk_enb_refcnt);
1655 clk_register_clkdev(clk, "audio0_2x", NULL);
1656 clks[audio0_2x] = clk;
1657
1658 /* audio1_2x */
1659 clk = clk_register_fixed_factor(NULL, "audio1_doubler", "audio1",
1660 CLK_SET_RATE_PARENT, 2, 1);
1661 clk = tegra_clk_register_divider("audio1_div", "audio1_doubler",
1662 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 25, 1,
1663 0, &clk_doubler_lock);
1664 clk = tegra_clk_register_periph_gate("audio1_2x", "audio1_div",
1665 TEGRA_PERIPH_NO_RESET, clk_base,
1666 CLK_SET_RATE_PARENT, 114, &periph_v_regs,
1667 periph_clk_enb_refcnt);
1668 clk_register_clkdev(clk, "audio1_2x", NULL);
1669 clks[audio1_2x] = clk;
1670
1671 /* audio2_2x */
1672 clk = clk_register_fixed_factor(NULL, "audio2_doubler", "audio2",
1673 CLK_SET_RATE_PARENT, 2, 1);
1674 clk = tegra_clk_register_divider("audio2_div", "audio2_doubler",
1675 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 26, 1,
1676 0, &clk_doubler_lock);
1677 clk = tegra_clk_register_periph_gate("audio2_2x", "audio2_div",
1678 TEGRA_PERIPH_NO_RESET, clk_base,
1679 CLK_SET_RATE_PARENT, 115, &periph_v_regs,
1680 periph_clk_enb_refcnt);
1681 clk_register_clkdev(clk, "audio2_2x", NULL);
1682 clks[audio2_2x] = clk;
1683
1684 /* audio3_2x */
1685 clk = clk_register_fixed_factor(NULL, "audio3_doubler", "audio3",
1686 CLK_SET_RATE_PARENT, 2, 1);
1687 clk = tegra_clk_register_divider("audio3_div", "audio3_doubler",
1688 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 27, 1,
1689 0, &clk_doubler_lock);
1690 clk = tegra_clk_register_periph_gate("audio3_2x", "audio3_div",
1691 TEGRA_PERIPH_NO_RESET, clk_base,
1692 CLK_SET_RATE_PARENT, 116, &periph_v_regs,
1693 periph_clk_enb_refcnt);
1694 clk_register_clkdev(clk, "audio3_2x", NULL);
1695 clks[audio3_2x] = clk;
1696
1697 /* audio4_2x */
1698 clk = clk_register_fixed_factor(NULL, "audio4_doubler", "audio4",
1699 CLK_SET_RATE_PARENT, 2, 1);
1700 clk = tegra_clk_register_divider("audio4_div", "audio4_doubler",
1701 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 28, 1,
1702 0, &clk_doubler_lock);
1703 clk = tegra_clk_register_periph_gate("audio4_2x", "audio4_div",
1704 TEGRA_PERIPH_NO_RESET, clk_base,
1705 CLK_SET_RATE_PARENT, 117, &periph_v_regs,
1706 periph_clk_enb_refcnt);
1707 clk_register_clkdev(clk, "audio4_2x", NULL);
1708 clks[audio4_2x] = clk;
1709
1710 /* spdif_2x */
1711 clk = clk_register_fixed_factor(NULL, "spdif_doubler", "spdif",
1712 CLK_SET_RATE_PARENT, 2, 1);
1713 clk = tegra_clk_register_divider("spdif_div", "spdif_doubler",
1714 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 29, 1,
1715 0, &clk_doubler_lock);
1716 clk = tegra_clk_register_periph_gate("spdif_2x", "spdif_div",
1717 TEGRA_PERIPH_NO_RESET, clk_base,
1718 CLK_SET_RATE_PARENT, 118,
1719 &periph_v_regs, periph_clk_enb_refcnt);
1720 clk_register_clkdev(clk, "spdif_2x", NULL);
1721 clks[spdif_2x] = clk;
1722}
1723
1724static void __init tegra114_pmc_clk_init(void __iomem *pmc_base)
1725{
1726 struct clk *clk;
1727
1728 /* clk_out_1 */
1729 clk = clk_register_mux(NULL, "clk_out_1_mux", clk_out1_parents,
1730 ARRAY_SIZE(clk_out1_parents),
1731 CLK_SET_RATE_NO_REPARENT,
1732 pmc_base + PMC_CLK_OUT_CNTRL, 6, 3, 0,
1733 &clk_out_lock);
1734 clks[clk_out_1_mux] = clk;
1735 clk = clk_register_gate(NULL, "clk_out_1", "clk_out_1_mux", 0,
1736 pmc_base + PMC_CLK_OUT_CNTRL, 2, 0,
1737 &clk_out_lock);
1738 clk_register_clkdev(clk, "extern1", "clk_out_1");
1739 clks[clk_out_1] = clk;
1740
1741 /* clk_out_2 */
1742 clk = clk_register_mux(NULL, "clk_out_2_mux", clk_out2_parents,
1743 ARRAY_SIZE(clk_out2_parents),
1744 CLK_SET_RATE_NO_REPARENT,
1745 pmc_base + PMC_CLK_OUT_CNTRL, 14, 3, 0,
1746 &clk_out_lock);
1747 clks[clk_out_2_mux] = clk;
1748 clk = clk_register_gate(NULL, "clk_out_2", "clk_out_2_mux", 0,
1749 pmc_base + PMC_CLK_OUT_CNTRL, 10, 0,
1750 &clk_out_lock);
1751 clk_register_clkdev(clk, "extern2", "clk_out_2");
1752 clks[clk_out_2] = clk;
1753
1754 /* clk_out_3 */
1755 clk = clk_register_mux(NULL, "clk_out_3_mux", clk_out3_parents,
1756 ARRAY_SIZE(clk_out3_parents),
1757 CLK_SET_RATE_NO_REPARENT,
1758 pmc_base + PMC_CLK_OUT_CNTRL, 22, 3, 0,
1759 &clk_out_lock);
1760 clks[clk_out_3_mux] = clk;
1761 clk = clk_register_gate(NULL, "clk_out_3", "clk_out_3_mux", 0,
1762 pmc_base + PMC_CLK_OUT_CNTRL, 18, 0,
1763 &clk_out_lock);
1764 clk_register_clkdev(clk, "extern3", "clk_out_3");
1765 clks[clk_out_3] = clk;
1766
1767 /* blink */
1768 /* clear the blink timer register to directly output clk_32k */
1769 writel_relaxed(0, pmc_base + PMC_BLINK_TIMER);
1770 clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0,
1771 pmc_base + PMC_DPD_PADS_ORIDE,
1772 PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL);
1773 clk = clk_register_gate(NULL, "blink", "blink_override", 0,
1774 pmc_base + PMC_CTRL,
1775 PMC_CTRL_BLINK_ENB, 0, NULL);
1776 clk_register_clkdev(clk, "blink", NULL);
1777 clks[blink] = clk;
1778
1779} 1179}
1780 1180
1781static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4", 1181static __init void tegra114_periph_clk_init(void __iomem *clk_base,
1782 "pll_p", "pll_p_out2", "unused", 1182 void __iomem *pmc_base)
1783 "clk_32k", "pll_m_out1" };
1784
1785static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
1786 "pll_p", "pll_p_out4", "unused",
1787 "unused", "pll_x" };
1788
1789static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
1790 "pll_p", "pll_p_out4", "unused",
1791 "unused", "pll_x", "pll_x_out0" };
1792
1793static void __init tegra114_super_clk_init(void __iomem *clk_base)
1794{ 1183{
1795 struct clk *clk; 1184 struct clk *clk;
1185 u32 val;
1796 1186
1797 /* CCLKG */ 1187 /* xusb_hs_src */
1798 clk = tegra_clk_register_super_mux("cclk_g", cclk_g_parents, 1188 val = readl(clk_base + CLK_SOURCE_XUSB_SS_SRC);
1799 ARRAY_SIZE(cclk_g_parents), 1189 val |= BIT(25); /* always select PLLU_60M */
1800 CLK_SET_RATE_PARENT, 1190 writel(val, clk_base + CLK_SOURCE_XUSB_SS_SRC);
1801 clk_base + CCLKG_BURST_POLICY,
1802 0, 4, 0, 0, NULL);
1803 clk_register_clkdev(clk, "cclk_g", NULL);
1804 clks[cclk_g] = clk;
1805
1806 /* CCLKLP */
1807 clk = tegra_clk_register_super_mux("cclk_lp", cclk_lp_parents,
1808 ARRAY_SIZE(cclk_lp_parents),
1809 CLK_SET_RATE_PARENT,
1810 clk_base + CCLKLP_BURST_POLICY,
1811 0, 4, 8, 9, NULL);
1812 clk_register_clkdev(clk, "cclk_lp", NULL);
1813 clks[cclk_lp] = clk;
1814
1815 /* SCLK */
1816 clk = tegra_clk_register_super_mux("sclk", sclk_parents,
1817 ARRAY_SIZE(sclk_parents),
1818 CLK_SET_RATE_PARENT,
1819 clk_base + SCLK_BURST_POLICY,
1820 0, 4, 0, 0, NULL);
1821 clk_register_clkdev(clk, "sclk", NULL);
1822 clks[sclk] = clk;
1823
1824 /* HCLK */
1825 clk = clk_register_divider(NULL, "hclk_div", "sclk", 0,
1826 clk_base + SYSTEM_CLK_RATE, 4, 2, 0,
1827 &sysrate_lock);
1828 clk = clk_register_gate(NULL, "hclk", "hclk_div", CLK_SET_RATE_PARENT |
1829 CLK_IGNORE_UNUSED, clk_base + SYSTEM_CLK_RATE,
1830 7, CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
1831 clk_register_clkdev(clk, "hclk", NULL);
1832 clks[hclk] = clk;
1833
1834 /* PCLK */
1835 clk = clk_register_divider(NULL, "pclk_div", "hclk", 0,
1836 clk_base + SYSTEM_CLK_RATE, 0, 2, 0,
1837 &sysrate_lock);
1838 clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT |
1839 CLK_IGNORE_UNUSED, clk_base + SYSTEM_CLK_RATE,
1840 3, CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
1841 clk_register_clkdev(clk, "pclk", NULL);
1842 clks[pclk] = clk;
1843}
1844
1845static struct tegra_periph_init_data tegra_periph_clk_list[] = {
1846 TEGRA_INIT_DATA_MUX("i2s0", NULL, "tegra30-i2s.0", mux_pllaout0_audio0_2x_pllp_clkm, CLK_SOURCE_I2S0, 30, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s0),
1847 TEGRA_INIT_DATA_MUX("i2s1", NULL, "tegra30-i2s.1", mux_pllaout0_audio1_2x_pllp_clkm, CLK_SOURCE_I2S1, 11, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s1),
1848 TEGRA_INIT_DATA_MUX("i2s2", NULL, "tegra30-i2s.2", mux_pllaout0_audio2_2x_pllp_clkm, CLK_SOURCE_I2S2, 18, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s2),
1849 TEGRA_INIT_DATA_MUX("i2s3", NULL, "tegra30-i2s.3", mux_pllaout0_audio3_2x_pllp_clkm, CLK_SOURCE_I2S3, 101, &periph_v_regs, TEGRA_PERIPH_ON_APB, i2s3),
1850 TEGRA_INIT_DATA_MUX("i2s4", NULL, "tegra30-i2s.4", mux_pllaout0_audio4_2x_pllp_clkm, CLK_SOURCE_I2S4, 102, &periph_v_regs, TEGRA_PERIPH_ON_APB, i2s4),
1851 TEGRA_INIT_DATA_MUX("spdif_out", "spdif_out", "tegra30-spdif", mux_pllaout0_audio_2x_pllp_clkm, CLK_SOURCE_SPDIF_OUT, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_out),
1852 TEGRA_INIT_DATA_MUX("spdif_in", "spdif_in", "tegra30-spdif", mux_pllp_pllc_pllm, CLK_SOURCE_SPDIF_IN, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_in),
1853 TEGRA_INIT_DATA_MUX("pwm", NULL, "pwm", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_PWM, 17, &periph_l_regs, TEGRA_PERIPH_ON_APB, pwm),
1854 TEGRA_INIT_DATA_MUX("adx", NULL, "adx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX, 154, &periph_w_regs, TEGRA_PERIPH_ON_APB, adx),
1855 TEGRA_INIT_DATA_MUX("amx", NULL, "amx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX, 153, &periph_w_regs, TEGRA_PERIPH_ON_APB, amx),
1856 TEGRA_INIT_DATA_MUX("hda", "hda", "tegra30-hda", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA, 125, &periph_v_regs, TEGRA_PERIPH_ON_APB, hda),
1857 TEGRA_INIT_DATA_MUX("hda2codec_2x", "hda2codec", "tegra30-hda", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, &periph_v_regs, TEGRA_PERIPH_ON_APB, hda2codec_2x),
1858 TEGRA_INIT_DATA_MUX("sbc1", NULL, "tegra11-spi.0", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC1, 41, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc1),
1859 TEGRA_INIT_DATA_MUX("sbc2", NULL, "tegra11-spi.1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC2, 44, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc2),
1860 TEGRA_INIT_DATA_MUX("sbc3", NULL, "tegra11-spi.2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC3, 46, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc3),
1861 TEGRA_INIT_DATA_MUX("sbc4", NULL, "tegra11-spi.3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC4, 68, &periph_u_regs, TEGRA_PERIPH_ON_APB, sbc4),
1862 TEGRA_INIT_DATA_MUX("sbc5", NULL, "tegra11-spi.4", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC5, 104, &periph_v_regs, TEGRA_PERIPH_ON_APB, sbc5),
1863 TEGRA_INIT_DATA_MUX("sbc6", NULL, "tegra11-spi.5", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC6, 105, &periph_v_regs, TEGRA_PERIPH_ON_APB, sbc6),
1864 TEGRA_INIT_DATA_MUX8("ndflash", NULL, "tegra_nand", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDFLASH, 13, &periph_u_regs, TEGRA_PERIPH_ON_APB, ndspeed),
1865 TEGRA_INIT_DATA_MUX8("ndspeed", NULL, "tegra_nand_speed", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDSPEED, 80, &periph_u_regs, TEGRA_PERIPH_ON_APB, ndspeed),
1866 TEGRA_INIT_DATA_MUX("vfir", NULL, "vfir", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VFIR, 7, &periph_l_regs, TEGRA_PERIPH_ON_APB, vfir),
1867 TEGRA_INIT_DATA_MUX("sdmmc1", NULL, "sdhci-tegra.0", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC1, 14, &periph_l_regs, 0, sdmmc1),
1868 TEGRA_INIT_DATA_MUX("sdmmc2", NULL, "sdhci-tegra.1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC2, 9, &periph_l_regs, 0, sdmmc2),
1869 TEGRA_INIT_DATA_MUX("sdmmc3", NULL, "sdhci-tegra.2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC3, 69, &periph_u_regs, 0, sdmmc3),
1870 TEGRA_INIT_DATA_MUX("sdmmc4", NULL, "sdhci-tegra.3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC4, 15, &periph_l_regs, 0, sdmmc4),
1871 TEGRA_INIT_DATA_INT("vde", NULL, "vde", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_VDE, 61, &periph_h_regs, 0, vde),
1872 TEGRA_INIT_DATA_MUX_FLAGS("csite", NULL, "csite", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_CSITE, 73, &periph_u_regs, TEGRA_PERIPH_ON_APB, csite, CLK_IGNORE_UNUSED),
1873 TEGRA_INIT_DATA_MUX("la", NULL, "la", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_LA, 76, &periph_u_regs, TEGRA_PERIPH_ON_APB, la),
1874 TEGRA_INIT_DATA_MUX("trace", NULL, "trace", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_TRACE, 77, &periph_u_regs, TEGRA_PERIPH_ON_APB, trace),
1875 TEGRA_INIT_DATA_MUX("owr", NULL, "tegra_w1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_OWR, 71, &periph_u_regs, TEGRA_PERIPH_ON_APB, owr),
1876 TEGRA_INIT_DATA_MUX("nor", NULL, "tegra-nor", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NOR, 42, &periph_h_regs, 0, nor),
1877 TEGRA_INIT_DATA_MUX("mipi", NULL, "mipi", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_MIPI, 50, &periph_h_regs, TEGRA_PERIPH_ON_APB, mipi),
1878 TEGRA_INIT_DATA_I2C("i2c1", "div-clk", "tegra11-i2c.0", mux_pllp_clkm, CLK_SOURCE_I2C1, 12, &periph_l_regs, i2c1),
1879 TEGRA_INIT_DATA_I2C("i2c2", "div-clk", "tegra11-i2c.1", mux_pllp_clkm, CLK_SOURCE_I2C2, 54, &periph_h_regs, i2c2),
1880 TEGRA_INIT_DATA_I2C("i2c3", "div-clk", "tegra11-i2c.2", mux_pllp_clkm, CLK_SOURCE_I2C3, 67, &periph_u_regs, i2c3),
1881 TEGRA_INIT_DATA_I2C("i2c4", "div-clk", "tegra11-i2c.3", mux_pllp_clkm, CLK_SOURCE_I2C4, 103, &periph_v_regs, i2c4),
1882 TEGRA_INIT_DATA_I2C("i2c5", "div-clk", "tegra11-i2c.4", mux_pllp_clkm, CLK_SOURCE_I2C5, 47, &periph_h_regs, i2c5),
1883 TEGRA_INIT_DATA_UART("uarta", NULL, "tegra_uart.0", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTA, 6, &periph_l_regs, uarta),
1884 TEGRA_INIT_DATA_UART("uartb", NULL, "tegra_uart.1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTB, 7, &periph_l_regs, uartb),
1885 TEGRA_INIT_DATA_UART("uartc", NULL, "tegra_uart.2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTC, 55, &periph_h_regs, uartc),
1886 TEGRA_INIT_DATA_UART("uartd", NULL, "tegra_uart.3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTD, 65, &periph_u_regs, uartd),
1887 TEGRA_INIT_DATA_INT("3d", NULL, "3d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_3D, 24, &periph_l_regs, 0, gr_3d),
1888 TEGRA_INIT_DATA_INT("2d", NULL, "2d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_2D, 21, &periph_l_regs, 0, gr_2d),
1889 TEGRA_INIT_DATA_MUX("vi_sensor", "vi_sensor", "tegra_camera", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, &periph_l_regs, TEGRA_PERIPH_NO_RESET, vi_sensor),
1890 TEGRA_INIT_DATA_INT8("vi", "vi", "tegra_camera", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI, 20, &periph_l_regs, 0, vi),
1891 TEGRA_INIT_DATA_INT8("epp", NULL, "epp", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_EPP, 19, &periph_l_regs, 0, epp),
1892 TEGRA_INIT_DATA_INT8("msenc", NULL, "msenc", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_MSENC, 91, &periph_u_regs, TEGRA_PERIPH_WAR_1005168, msenc),
1893 TEGRA_INIT_DATA_INT8("tsec", NULL, "tsec", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_TSEC, 83, &periph_u_regs, 0, tsec),
1894 TEGRA_INIT_DATA_INT8("host1x", NULL, "host1x", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_HOST1X, 28, &periph_l_regs, 0, host1x),
1895 TEGRA_INIT_DATA_MUX8("hdmi", NULL, "hdmi", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_HDMI, 51, &periph_h_regs, 0, hdmi),
1896 TEGRA_INIT_DATA_MUX("cilab", "cilab", "tegra_camera", mux_pllp_pllc_clkm, CLK_SOURCE_CILAB, 144, &periph_w_regs, 0, cilab),
1897 TEGRA_INIT_DATA_MUX("cilcd", "cilcd", "tegra_camera", mux_pllp_pllc_clkm, CLK_SOURCE_CILCD, 145, &periph_w_regs, 0, cilcd),
1898 TEGRA_INIT_DATA_MUX("cile", "cile", "tegra_camera", mux_pllp_pllc_clkm, CLK_SOURCE_CILE, 146, &periph_w_regs, 0, cile),
1899 TEGRA_INIT_DATA_MUX("dsialp", "dsialp", "tegradc.0", mux_pllp_pllc_clkm, CLK_SOURCE_DSIALP, 147, &periph_w_regs, 0, dsialp),
1900 TEGRA_INIT_DATA_MUX("dsiblp", "dsiblp", "tegradc.1", mux_pllp_pllc_clkm, CLK_SOURCE_DSIBLP, 148, &periph_w_regs, 0, dsiblp),
1901 TEGRA_INIT_DATA_MUX("tsensor", NULL, "tegra-tsensor", mux_pllp_pllc_clkm_clk32, CLK_SOURCE_TSENSOR, 100, &periph_v_regs, TEGRA_PERIPH_ON_APB, tsensor),
1902 TEGRA_INIT_DATA_MUX("actmon", NULL, "actmon", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_ACTMON, 119, &periph_v_regs, 0, actmon),
1903 TEGRA_INIT_DATA_MUX8("extern1", NULL, "extern1", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN1, 120, &periph_v_regs, 0, extern1),
1904 TEGRA_INIT_DATA_MUX8("extern2", NULL, "extern2", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN2, 121, &periph_v_regs, 0, extern2),
1905 TEGRA_INIT_DATA_MUX8("extern3", NULL, "extern3", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN3, 122, &periph_v_regs, 0, extern3),
1906 TEGRA_INIT_DATA_MUX("i2cslow", NULL, "i2cslow", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_I2CSLOW, 81, &periph_u_regs, TEGRA_PERIPH_ON_APB, i2cslow),
1907 TEGRA_INIT_DATA_INT8("se", NULL, "se", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SE, 127, &periph_v_regs, TEGRA_PERIPH_ON_APB, se),
1908 TEGRA_INIT_DATA_INT_FLAGS("mselect", NULL, "mselect", mux_pllp_clkm, CLK_SOURCE_MSELECT, 99, &periph_v_regs, 0, mselect, CLK_IGNORE_UNUSED),
1909 TEGRA_INIT_DATA_MUX("dfll_ref", "ref", "t114_dfll", mux_pllp_clkm, CLK_SOURCE_DFLL_REF, 155, &periph_w_regs, TEGRA_PERIPH_ON_APB, dfll_ref),
1910 TEGRA_INIT_DATA_MUX("dfll_soc", "soc", "t114_dfll", mux_pllp_clkm, CLK_SOURCE_DFLL_SOC, 155, &periph_w_regs, TEGRA_PERIPH_ON_APB, dfll_soc),
1911 TEGRA_INIT_DATA_MUX8("soc_therm", NULL, "soc_therm", mux_pllm_pllc_pllp_plla, CLK_SOURCE_SOC_THERM, 78, &periph_u_regs, TEGRA_PERIPH_ON_APB, soc_therm),
1912 TEGRA_INIT_DATA_XUSB("xusb_host_src", "host_src", "tegra_xhci", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_HOST_SRC, 143, &periph_w_regs, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, xusb_host_src),
1913 TEGRA_INIT_DATA_XUSB("xusb_falcon_src", "falcon_src", "tegra_xhci", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, &periph_w_regs, TEGRA_PERIPH_NO_RESET, xusb_falcon_src),
1914 TEGRA_INIT_DATA_XUSB("xusb_fs_src", "fs_src", "tegra_xhci", mux_clkm_48M_pllp_480M, CLK_SOURCE_XUSB_FS_SRC, 143, &periph_w_regs, TEGRA_PERIPH_NO_RESET, xusb_fs_src),
1915 TEGRA_INIT_DATA_XUSB("xusb_ss_src", "ss_src", "tegra_xhci", mux_clkm_pllre_clk32_480M_pllc_ref, CLK_SOURCE_XUSB_SS_SRC, 143, &periph_w_regs, TEGRA_PERIPH_NO_RESET, xusb_ss_src),
1916 TEGRA_INIT_DATA_XUSB("xusb_dev_src", "dev_src", "tegra_xhci", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, &periph_u_regs, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, xusb_dev_src),
1917 TEGRA_INIT_DATA_AUDIO("d_audio", "d_audio", "tegra30-ahub", CLK_SOURCE_D_AUDIO, 106, &periph_v_regs, TEGRA_PERIPH_ON_APB, d_audio),
1918 TEGRA_INIT_DATA_AUDIO("dam0", NULL, "tegra30-dam.0", CLK_SOURCE_DAM0, 108, &periph_v_regs, TEGRA_PERIPH_ON_APB, dam0),
1919 TEGRA_INIT_DATA_AUDIO("dam1", NULL, "tegra30-dam.1", CLK_SOURCE_DAM1, 109, &periph_v_regs, TEGRA_PERIPH_ON_APB, dam1),
1920 TEGRA_INIT_DATA_AUDIO("dam2", NULL, "tegra30-dam.2", CLK_SOURCE_DAM2, 110, &periph_v_regs, TEGRA_PERIPH_ON_APB, dam2),
1921};
1922
1923static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = {
1924 TEGRA_INIT_DATA_NODIV("disp1", NULL, "tegradc.0", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP1, 29, 7, 27, &periph_l_regs, 0, disp1),
1925 TEGRA_INIT_DATA_NODIV("disp2", NULL, "tegradc.1", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP2, 29, 7, 26, &periph_l_regs, 0, disp2),
1926};
1927 1191
1928static __init void tegra114_periph_clk_init(void __iomem *clk_base) 1192 clk = clk_register_fixed_factor(NULL, "xusb_hs_src", "pll_u_60M", 0,
1929{ 1193 1, 1);
1930 struct tegra_periph_init_data *data; 1194 clks[TEGRA114_CLK_XUSB_HS_SRC] = clk;
1931 struct clk *clk;
1932 int i;
1933 u32 val;
1934 1195
1935 /* apbdma */ 1196 /* dsia mux */
1936 clk = tegra_clk_register_periph_gate("apbdma", "clk_m", 0, clk_base,
1937 0, 34, &periph_h_regs,
1938 periph_clk_enb_refcnt);
1939 clks[apbdma] = clk;
1940
1941 /* rtc */
1942 clk = tegra_clk_register_periph_gate("rtc", "clk_32k",
1943 TEGRA_PERIPH_ON_APB |
1944 TEGRA_PERIPH_NO_RESET, clk_base,
1945 0, 4, &periph_l_regs,
1946 periph_clk_enb_refcnt);
1947 clk_register_clkdev(clk, NULL, "rtc-tegra");
1948 clks[rtc] = clk;
1949
1950 /* kbc */
1951 clk = tegra_clk_register_periph_gate("kbc", "clk_32k",
1952 TEGRA_PERIPH_ON_APB |
1953 TEGRA_PERIPH_NO_RESET, clk_base,
1954 0, 36, &periph_h_regs,
1955 periph_clk_enb_refcnt);
1956 clks[kbc] = clk;
1957
1958 /* timer */
1959 clk = tegra_clk_register_periph_gate("timer", "clk_m", 0, clk_base,
1960 0, 5, &periph_l_regs,
1961 periph_clk_enb_refcnt);
1962 clk_register_clkdev(clk, NULL, "timer");
1963 clks[timer] = clk;
1964
1965 /* kfuse */
1966 clk = tegra_clk_register_periph_gate("kfuse", "clk_m",
1967 TEGRA_PERIPH_ON_APB, clk_base, 0, 40,
1968 &periph_h_regs, periph_clk_enb_refcnt);
1969 clks[kfuse] = clk;
1970
1971 /* fuse */
1972 clk = tegra_clk_register_periph_gate("fuse", "clk_m",
1973 TEGRA_PERIPH_ON_APB, clk_base, 0, 39,
1974 &periph_h_regs, periph_clk_enb_refcnt);
1975 clks[fuse] = clk;
1976
1977 /* fuse_burn */
1978 clk = tegra_clk_register_periph_gate("fuse_burn", "clk_m",
1979 TEGRA_PERIPH_ON_APB, clk_base, 0, 39,
1980 &periph_h_regs, periph_clk_enb_refcnt);
1981 clks[fuse_burn] = clk;
1982
1983 /* apbif */
1984 clk = tegra_clk_register_periph_gate("apbif", "clk_m",
1985 TEGRA_PERIPH_ON_APB, clk_base, 0, 107,
1986 &periph_v_regs, periph_clk_enb_refcnt);
1987 clks[apbif] = clk;
1988
1989 /* hda2hdmi */
1990 clk = tegra_clk_register_periph_gate("hda2hdmi", "clk_m",
1991 TEGRA_PERIPH_ON_APB, clk_base, 0, 128,
1992 &periph_w_regs, periph_clk_enb_refcnt);
1993 clks[hda2hdmi] = clk;
1994
1995 /* vcp */
1996 clk = tegra_clk_register_periph_gate("vcp", "clk_m", 0, clk_base, 0,
1997 29, &periph_l_regs,
1998 periph_clk_enb_refcnt);
1999 clks[vcp] = clk;
2000
2001 /* bsea */
2002 clk = tegra_clk_register_periph_gate("bsea", "clk_m", 0, clk_base,
2003 0, 62, &periph_h_regs,
2004 periph_clk_enb_refcnt);
2005 clks[bsea] = clk;
2006
2007 /* bsev */
2008 clk = tegra_clk_register_periph_gate("bsev", "clk_m", 0, clk_base,
2009 0, 63, &periph_h_regs,
2010 periph_clk_enb_refcnt);
2011 clks[bsev] = clk;
2012
2013 /* mipi-cal */
2014 clk = tegra_clk_register_periph_gate("mipi-cal", "clk_m", 0, clk_base,
2015 0, 56, &periph_h_regs,
2016 periph_clk_enb_refcnt);
2017 clks[mipi_cal] = clk;
2018
2019 /* usbd */
2020 clk = tegra_clk_register_periph_gate("usbd", "clk_m", 0, clk_base,
2021 0, 22, &periph_l_regs,
2022 periph_clk_enb_refcnt);
2023 clks[usbd] = clk;
2024
2025 /* usb2 */
2026 clk = tegra_clk_register_periph_gate("usb2", "clk_m", 0, clk_base,
2027 0, 58, &periph_h_regs,
2028 periph_clk_enb_refcnt);
2029 clks[usb2] = clk;
2030
2031 /* usb3 */
2032 clk = tegra_clk_register_periph_gate("usb3", "clk_m", 0, clk_base,
2033 0, 59, &periph_h_regs,
2034 periph_clk_enb_refcnt);
2035 clks[usb3] = clk;
2036
2037 /* csi */
2038 clk = tegra_clk_register_periph_gate("csi", "pll_p_out3", 0, clk_base,
2039 0, 52, &periph_h_regs,
2040 periph_clk_enb_refcnt);
2041 clks[csi] = clk;
2042
2043 /* isp */
2044 clk = tegra_clk_register_periph_gate("isp", "clk_m", 0, clk_base, 0,
2045 23, &periph_l_regs,
2046 periph_clk_enb_refcnt);
2047 clks[isp] = clk;
2048
2049 /* csus */
2050 clk = tegra_clk_register_periph_gate("csus", "clk_m",
2051 TEGRA_PERIPH_NO_RESET, clk_base, 0, 92,
2052 &periph_u_regs, periph_clk_enb_refcnt);
2053 clks[csus] = clk;
2054
2055 /* dds */
2056 clk = tegra_clk_register_periph_gate("dds", "clk_m",
2057 TEGRA_PERIPH_ON_APB, clk_base, 0, 150,
2058 &periph_w_regs, periph_clk_enb_refcnt);
2059 clks[dds] = clk;
2060
2061 /* dp2 */
2062 clk = tegra_clk_register_periph_gate("dp2", "clk_m",
2063 TEGRA_PERIPH_ON_APB, clk_base, 0, 152,
2064 &periph_w_regs, periph_clk_enb_refcnt);
2065 clks[dp2] = clk;
2066
2067 /* dtv */
2068 clk = tegra_clk_register_periph_gate("dtv", "clk_m",
2069 TEGRA_PERIPH_ON_APB, clk_base, 0, 79,
2070 &periph_u_regs, periph_clk_enb_refcnt);
2071 clks[dtv] = clk;
2072
2073 /* dsia */
2074 clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0, 1197 clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0,
2075 ARRAY_SIZE(mux_plld_out0_plld2_out0), 1198 ARRAY_SIZE(mux_plld_out0_plld2_out0),
2076 CLK_SET_RATE_NO_REPARENT, 1199 CLK_SET_RATE_NO_REPARENT,
2077 clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock); 1200 clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock);
2078 clks[dsia_mux] = clk; 1201 clks[TEGRA114_CLK_DSIA_MUX] = clk;
2079 clk = tegra_clk_register_periph_gate("dsia", "dsia_mux", 0, clk_base,
2080 0, 48, &periph_h_regs,
2081 periph_clk_enb_refcnt);
2082 clks[dsia] = clk;
2083 1202
2084 /* dsib */ 1203 /* dsib mux */
2085 clk = clk_register_mux(NULL, "dsib_mux", mux_plld_out0_plld2_out0, 1204 clk = clk_register_mux(NULL, "dsib_mux", mux_plld_out0_plld2_out0,
2086 ARRAY_SIZE(mux_plld_out0_plld2_out0), 1205 ARRAY_SIZE(mux_plld_out0_plld2_out0),
2087 CLK_SET_RATE_NO_REPARENT, 1206 CLK_SET_RATE_NO_REPARENT,
2088 clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock); 1207 clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock);
2089 clks[dsib_mux] = clk; 1208 clks[TEGRA114_CLK_DSIB_MUX] = clk;
2090 clk = tegra_clk_register_periph_gate("dsib", "dsib_mux", 0, clk_base,
2091 0, 82, &periph_u_regs,
2092 periph_clk_enb_refcnt);
2093 clks[dsib] = clk;
2094 1209
2095 /* xusb_hs_src */ 1210 /* emc mux */
2096 val = readl(clk_base + CLK_SOURCE_XUSB_SS_SRC);
2097 val |= BIT(25); /* always select PLLU_60M */
2098 writel(val, clk_base + CLK_SOURCE_XUSB_SS_SRC);
2099
2100 clk = clk_register_fixed_factor(NULL, "xusb_hs_src", "pll_u_60M", 0,
2101 1, 1);
2102 clks[xusb_hs_src] = clk;
2103
2104 /* xusb_host */
2105 clk = tegra_clk_register_periph_gate("xusb_host", "xusb_host_src", 0,
2106 clk_base, 0, 89, &periph_u_regs,
2107 periph_clk_enb_refcnt);
2108 clks[xusb_host] = clk;
2109
2110 /* xusb_ss */
2111 clk = tegra_clk_register_periph_gate("xusb_ss", "xusb_ss_src", 0,
2112 clk_base, 0, 156, &periph_w_regs,
2113 periph_clk_enb_refcnt);
2114 clks[xusb_host] = clk;
2115
2116 /* xusb_dev */
2117 clk = tegra_clk_register_periph_gate("xusb_dev", "xusb_dev_src", 0,
2118 clk_base, 0, 95, &periph_u_regs,
2119 periph_clk_enb_refcnt);
2120 clks[xusb_dev] = clk;
2121
2122 /* emc */
2123 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, 1211 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
2124 ARRAY_SIZE(mux_pllmcp_clkm), 1212 ARRAY_SIZE(mux_pllmcp_clkm),
2125 CLK_SET_RATE_NO_REPARENT, 1213 CLK_SET_RATE_NO_REPARENT,
2126 clk_base + CLK_SOURCE_EMC, 1214 clk_base + CLK_SOURCE_EMC,
2127 29, 3, 0, NULL); 1215 29, 3, 0, NULL);
2128 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base,
2129 CLK_IGNORE_UNUSED, 57, &periph_h_regs,
2130 periph_clk_enb_refcnt);
2131 clks[emc] = clk;
2132
2133 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
2134 data = &tegra_periph_clk_list[i];
2135 clk = tegra_clk_register_periph(data->name, data->parent_names,
2136 data->num_parents, &data->periph,
2137 clk_base, data->offset, data->flags);
2138 clks[data->clk_id] = clk;
2139 }
2140 1216
2141 for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) { 1217 tegra_periph_clk_init(clk_base, pmc_base, tegra114_clks,
2142 data = &tegra_periph_nodiv_clk_list[i]; 1218 &pll_p_params);
2143 clk = tegra_clk_register_periph_nodiv(data->name,
2144 data->parent_names, data->num_parents,
2145 &data->periph, clk_base, data->offset);
2146 clks[data->clk_id] = clk;
2147 }
2148} 1219}
2149 1220
2150/* Tegra114 CPU clock and reset control functions */ 1221/* Tegra114 CPU clock and reset control functions */
@@ -2207,28 +1278,37 @@ static const struct of_device_id pmc_match[] __initconst = {
2207 * breaks 1278 * breaks
2208 */ 1279 */
2209static struct tegra_clk_init_table init_table[] __initdata = { 1280static struct tegra_clk_init_table init_table[] __initdata = {
2210 {uarta, pll_p, 408000000, 0}, 1281 {TEGRA114_CLK_UARTA, TEGRA114_CLK_PLL_P, 408000000, 0},
2211 {uartb, pll_p, 408000000, 0}, 1282 {TEGRA114_CLK_UARTB, TEGRA114_CLK_PLL_P, 408000000, 0},
2212 {uartc, pll_p, 408000000, 0}, 1283 {TEGRA114_CLK_UARTC, TEGRA114_CLK_PLL_P, 408000000, 0},
2213 {uartd, pll_p, 408000000, 0}, 1284 {TEGRA114_CLK_UARTD, TEGRA114_CLK_PLL_P, 408000000, 0},
2214 {pll_a, clk_max, 564480000, 1}, 1285 {TEGRA114_CLK_PLL_A, TEGRA114_CLK_CLK_MAX, 564480000, 1},
2215 {pll_a_out0, clk_max, 11289600, 1}, 1286 {TEGRA114_CLK_PLL_A_OUT0, TEGRA114_CLK_CLK_MAX, 11289600, 1},
2216 {extern1, pll_a_out0, 0, 1}, 1287 {TEGRA114_CLK_EXTERN1, TEGRA114_CLK_PLL_A_OUT0, 0, 1},
2217 {clk_out_1_mux, extern1, 0, 1}, 1288 {TEGRA114_CLK_CLK_OUT_1_MUX, TEGRA114_CLK_EXTERN1, 0, 1},
2218 {clk_out_1, clk_max, 0, 1}, 1289 {TEGRA114_CLK_CLK_OUT_1, TEGRA114_CLK_CLK_MAX, 0, 1},
2219 {i2s0, pll_a_out0, 11289600, 0}, 1290 {TEGRA114_CLK_I2S0, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0},
2220 {i2s1, pll_a_out0, 11289600, 0}, 1291 {TEGRA114_CLK_I2S1, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0},
2221 {i2s2, pll_a_out0, 11289600, 0}, 1292 {TEGRA114_CLK_I2S2, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0},
2222 {i2s3, pll_a_out0, 11289600, 0}, 1293 {TEGRA114_CLK_I2S3, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0},
2223 {i2s4, pll_a_out0, 11289600, 0}, 1294 {TEGRA114_CLK_I2S4, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0},
2224 {dfll_soc, pll_p, 51000000, 1}, 1295 {TEGRA114_CLK_HOST1X, TEGRA114_CLK_PLL_P, 136000000, 0},
2225 {dfll_ref, pll_p, 51000000, 1}, 1296 {TEGRA114_CLK_DFLL_SOC, TEGRA114_CLK_PLL_P, 51000000, 1},
2226 {clk_max, clk_max, 0, 0}, /* This MUST be the last entry. */ 1297 {TEGRA114_CLK_DFLL_REF, TEGRA114_CLK_PLL_P, 51000000, 1},
1298 {TEGRA114_CLK_DISP1, TEGRA114_CLK_PLL_P, 0, 0},
1299 {TEGRA114_CLK_DISP2, TEGRA114_CLK_PLL_P, 0, 0},
1300 {TEGRA114_CLK_GR2D, TEGRA114_CLK_PLL_C2, 300000000, 0},
1301 {TEGRA114_CLK_GR3D, TEGRA114_CLK_PLL_C2, 300000000, 0},
1302 {TEGRA114_CLK_DSIALP, TEGRA114_CLK_PLL_P, 68000000, 0},
1303 {TEGRA114_CLK_DSIBLP, TEGRA114_CLK_PLL_P, 68000000, 0},
1304
1305 /* This MUST be the last entry. */
1306 {TEGRA114_CLK_CLK_MAX, TEGRA114_CLK_CLK_MAX, 0, 0},
2227}; 1307};
2228 1308
2229static void __init tegra114_clock_apply_init_table(void) 1309static void __init tegra114_clock_apply_init_table(void)
2230{ 1310{
2231 tegra_init_from_table(init_table, clks, clk_max); 1311 tegra_init_from_table(init_table, clks, TEGRA114_CLK_CLK_MAX);
2232} 1312}
2233 1313
2234 1314
@@ -2359,7 +1439,6 @@ EXPORT_SYMBOL(tegra114_clock_deassert_dfll_dvco_reset);
2359static void __init tegra114_clock_init(struct device_node *np) 1439static void __init tegra114_clock_init(struct device_node *np)
2360{ 1440{
2361 struct device_node *node; 1441 struct device_node *node;
2362 int i;
2363 1442
2364 clk_base = of_iomap(np, 0); 1443 clk_base = of_iomap(np, 0);
2365 if (!clk_base) { 1444 if (!clk_base) {
@@ -2381,29 +1460,24 @@ static void __init tegra114_clock_init(struct device_node *np)
2381 return; 1460 return;
2382 } 1461 }
2383 1462
1463 clks = tegra_clk_init(clk_base, TEGRA114_CLK_CLK_MAX,
1464 TEGRA114_CLK_PERIPH_BANKS);
1465 if (!clks)
1466 return;
1467
2384 if (tegra114_osc_clk_init(clk_base) < 0) 1468 if (tegra114_osc_clk_init(clk_base) < 0)
2385 return; 1469 return;
2386 1470
2387 tegra114_fixed_clk_init(clk_base); 1471 tegra114_fixed_clk_init(clk_base);
2388 tegra114_pll_init(clk_base, pmc_base); 1472 tegra114_pll_init(clk_base, pmc_base);
2389 tegra114_periph_clk_init(clk_base); 1473 tegra114_periph_clk_init(clk_base, pmc_base);
2390 tegra114_audio_clk_init(clk_base); 1474 tegra_audio_clk_init(clk_base, pmc_base, tegra114_clks, &pll_a_params);
2391 tegra114_pmc_clk_init(pmc_base); 1475 tegra_pmc_clk_init(pmc_base, tegra114_clks);
2392 tegra114_super_clk_init(clk_base); 1476 tegra_super_clk_gen4_init(clk_base, pmc_base, tegra114_clks,
2393 1477 &pll_x_params);
2394 for (i = 0; i < ARRAY_SIZE(clks); i++) { 1478
2395 if (IS_ERR(clks[i])) { 1479 tegra_add_of_provider(np);
2396 pr_err 1480 tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
2397 ("Tegra114 clk %d: register failed with %ld\n",
2398 i, PTR_ERR(clks[i]));
2399 }
2400 if (!clks[i])
2401 clks[i] = ERR_PTR(-EINVAL);
2402 }
2403
2404 clk_data.clks = clks;
2405 clk_data.clk_num = ARRAY_SIZE(clks);
2406 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
2407 1481
2408 tegra_clk_apply_init_table = tegra114_clock_apply_init_table; 1482 tegra_clk_apply_init_table = tegra114_clock_apply_init_table;
2409 1483
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
new file mode 100644
index 000000000000..aff86b5bc745
--- /dev/null
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -0,0 +1,1424 @@
1/*
2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/io.h>
18#include <linux/clk.h>
19#include <linux/clk-provider.h>
20#include <linux/clkdev.h>
21#include <linux/of.h>
22#include <linux/of_address.h>
23#include <linux/delay.h>
24#include <linux/export.h>
25#include <linux/clk/tegra.h>
26#include <dt-bindings/clock/tegra124-car.h>
27
28#include "clk.h"
29#include "clk-id.h"
30
31#define CLK_SOURCE_CSITE 0x1d4
32#define CLK_SOURCE_EMC 0x19c
33#define CLK_SOURCE_XUSB_SS_SRC 0x610
34
35#define PLLC_BASE 0x80
36#define PLLC_OUT 0x84
37#define PLLC_MISC2 0x88
38#define PLLC_MISC 0x8c
39#define PLLC2_BASE 0x4e8
40#define PLLC2_MISC 0x4ec
41#define PLLC3_BASE 0x4fc
42#define PLLC3_MISC 0x500
43#define PLLM_BASE 0x90
44#define PLLM_OUT 0x94
45#define PLLM_MISC 0x9c
46#define PLLP_BASE 0xa0
47#define PLLP_MISC 0xac
48#define PLLA_BASE 0xb0
49#define PLLA_MISC 0xbc
50#define PLLD_BASE 0xd0
51#define PLLD_MISC 0xdc
52#define PLLU_BASE 0xc0
53#define PLLU_MISC 0xcc
54#define PLLX_BASE 0xe0
55#define PLLX_MISC 0xe4
56#define PLLX_MISC2 0x514
57#define PLLX_MISC3 0x518
58#define PLLE_BASE 0xe8
59#define PLLE_MISC 0xec
60#define PLLD2_BASE 0x4b8
61#define PLLD2_MISC 0x4bc
62#define PLLE_AUX 0x48c
63#define PLLRE_BASE 0x4c4
64#define PLLRE_MISC 0x4c8
65#define PLLDP_BASE 0x590
66#define PLLDP_MISC 0x594
67#define PLLC4_BASE 0x5a4
68#define PLLC4_MISC 0x5a8
69
70#define PLLC_IDDQ_BIT 26
71#define PLLRE_IDDQ_BIT 16
72#define PLLSS_IDDQ_BIT 19
73
74#define PLL_BASE_LOCK BIT(27)
75#define PLLE_MISC_LOCK BIT(11)
76#define PLLRE_MISC_LOCK BIT(24)
77
78#define PLL_MISC_LOCK_ENABLE 18
79#define PLLC_MISC_LOCK_ENABLE 24
80#define PLLDU_MISC_LOCK_ENABLE 22
81#define PLLE_MISC_LOCK_ENABLE 9
82#define PLLRE_MISC_LOCK_ENABLE 30
83#define PLLSS_MISC_LOCK_ENABLE 30
84
85#define PLLXC_SW_MAX_P 6
86
87#define PMC_PLLM_WB0_OVERRIDE 0x1dc
88#define PMC_PLLM_WB0_OVERRIDE_2 0x2b0
89
90#define UTMIP_PLL_CFG2 0x488
91#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6)
92#define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
93#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)
94#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2)
95#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4)
96
97#define UTMIP_PLL_CFG1 0x484
98#define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6)
99#define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
100#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17)
101#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16)
102#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15)
103#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)
104#define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)
105
106#define UTMIPLL_HW_PWRDN_CFG0 0x52c
107#define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE BIT(25)
108#define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
109#define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
110#define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE BIT(5)
111#define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL BIT(4)
112#define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
113#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1)
114#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0)
115
116/* Tegra CPU clock and reset control regs */
117#define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470
118
119#ifdef CONFIG_PM_SLEEP
120static struct cpu_clk_suspend_context {
121 u32 clk_csite_src;
122} tegra124_cpu_clk_sctx;
123#endif
124
125static void __iomem *clk_base;
126static void __iomem *pmc_base;
127
128static unsigned long osc_freq;
129static unsigned long pll_ref_freq;
130
131static DEFINE_SPINLOCK(pll_d_lock);
132static DEFINE_SPINLOCK(pll_d2_lock);
133static DEFINE_SPINLOCK(pll_e_lock);
134static DEFINE_SPINLOCK(pll_re_lock);
135static DEFINE_SPINLOCK(pll_u_lock);
136
137/* possible OSC frequencies in Hz */
138static unsigned long tegra124_input_freq[] = {
139 [0] = 13000000,
140 [1] = 16800000,
141 [4] = 19200000,
142 [5] = 38400000,
143 [8] = 12000000,
144 [9] = 48000000,
145 [12] = 260000000,
146};
147
148static const char *mux_plld_out0_plld2_out0[] = {
149 "pll_d_out0", "pll_d2_out0",
150};
151#define mux_plld_out0_plld2_out0_idx NULL
152
153static const char *mux_pllmcp_clkm[] = {
154 "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_c2", "pll_c3",
155};
156#define mux_pllmcp_clkm_idx NULL
157
158static struct div_nmp pllxc_nmp = {
159 .divm_shift = 0,
160 .divm_width = 8,
161 .divn_shift = 8,
162 .divn_width = 8,
163 .divp_shift = 20,
164 .divp_width = 4,
165};
166
167static struct pdiv_map pllxc_p[] = {
168 { .pdiv = 1, .hw_val = 0 },
169 { .pdiv = 2, .hw_val = 1 },
170 { .pdiv = 3, .hw_val = 2 },
171 { .pdiv = 4, .hw_val = 3 },
172 { .pdiv = 5, .hw_val = 4 },
173 { .pdiv = 6, .hw_val = 5 },
174 { .pdiv = 8, .hw_val = 6 },
175 { .pdiv = 10, .hw_val = 7 },
176 { .pdiv = 12, .hw_val = 8 },
177 { .pdiv = 16, .hw_val = 9 },
178 { .pdiv = 12, .hw_val = 10 },
179 { .pdiv = 16, .hw_val = 11 },
180 { .pdiv = 20, .hw_val = 12 },
181 { .pdiv = 24, .hw_val = 13 },
182 { .pdiv = 32, .hw_val = 14 },
183 { .pdiv = 0, .hw_val = 0 },
184};
185
186static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
187 /* 1 GHz */
188 {12000000, 1000000000, 83, 0, 1}, /* actual: 996.0 MHz */
189 {13000000, 1000000000, 76, 0, 1}, /* actual: 988.0 MHz */
190 {16800000, 1000000000, 59, 0, 1}, /* actual: 991.2 MHz */
191 {19200000, 1000000000, 52, 0, 1}, /* actual: 998.4 MHz */
192 {26000000, 1000000000, 76, 1, 1}, /* actual: 988.0 MHz */
193 {0, 0, 0, 0, 0, 0},
194};
195
196static struct tegra_clk_pll_params pll_x_params = {
197 .input_min = 12000000,
198 .input_max = 800000000,
199 .cf_min = 12000000,
200 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
201 .vco_min = 700000000,
202 .vco_max = 3000000000UL,
203 .base_reg = PLLX_BASE,
204 .misc_reg = PLLX_MISC,
205 .lock_mask = PLL_BASE_LOCK,
206 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
207 .lock_delay = 300,
208 .iddq_reg = PLLX_MISC3,
209 .iddq_bit_idx = 3,
210 .max_p = 6,
211 .dyn_ramp_reg = PLLX_MISC2,
212 .stepa_shift = 16,
213 .stepb_shift = 24,
214 .pdiv_tohw = pllxc_p,
215 .div_nmp = &pllxc_nmp,
216 .freq_table = pll_x_freq_table,
217 .flags = TEGRA_PLL_USE_LOCK,
218};
219
220static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
221 { 12000000, 624000000, 104, 1, 2},
222 { 12000000, 600000000, 100, 1, 2},
223 { 13000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */
224 { 16800000, 600000000, 71, 1, 2}, /* actual: 596.4 MHz */
225 { 19200000, 600000000, 62, 1, 2}, /* actual: 595.2 MHz */
226 { 26000000, 600000000, 92, 2, 2}, /* actual: 598.0 MHz */
227 { 0, 0, 0, 0, 0, 0 },
228};
229
230static struct tegra_clk_pll_params pll_c_params = {
231 .input_min = 12000000,
232 .input_max = 800000000,
233 .cf_min = 12000000,
234 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
235 .vco_min = 600000000,
236 .vco_max = 1400000000,
237 .base_reg = PLLC_BASE,
238 .misc_reg = PLLC_MISC,
239 .lock_mask = PLL_BASE_LOCK,
240 .lock_enable_bit_idx = PLLC_MISC_LOCK_ENABLE,
241 .lock_delay = 300,
242 .iddq_reg = PLLC_MISC,
243 .iddq_bit_idx = PLLC_IDDQ_BIT,
244 .max_p = PLLXC_SW_MAX_P,
245 .dyn_ramp_reg = PLLC_MISC2,
246 .stepa_shift = 17,
247 .stepb_shift = 9,
248 .pdiv_tohw = pllxc_p,
249 .div_nmp = &pllxc_nmp,
250 .freq_table = pll_c_freq_table,
251 .flags = TEGRA_PLL_USE_LOCK,
252};
253
254static struct div_nmp pllcx_nmp = {
255 .divm_shift = 0,
256 .divm_width = 2,
257 .divn_shift = 8,
258 .divn_width = 8,
259 .divp_shift = 20,
260 .divp_width = 3,
261};
262
263static struct pdiv_map pllc_p[] = {
264 { .pdiv = 1, .hw_val = 0 },
265 { .pdiv = 2, .hw_val = 1 },
266 { .pdiv = 3, .hw_val = 2 },
267 { .pdiv = 4, .hw_val = 3 },
268 { .pdiv = 6, .hw_val = 4 },
269 { .pdiv = 8, .hw_val = 5 },
270 { .pdiv = 12, .hw_val = 6 },
271 { .pdiv = 16, .hw_val = 7 },
272 { .pdiv = 0, .hw_val = 0 },
273};
274
275static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = {
276 {12000000, 600000000, 100, 1, 2},
277 {13000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */
278 {16800000, 600000000, 71, 1, 2}, /* actual: 596.4 MHz */
279 {19200000, 600000000, 62, 1, 2}, /* actual: 595.2 MHz */
280 {26000000, 600000000, 92, 2, 2}, /* actual: 598.0 MHz */
281 {0, 0, 0, 0, 0, 0},
282};
283
284static struct tegra_clk_pll_params pll_c2_params = {
285 .input_min = 12000000,
286 .input_max = 48000000,
287 .cf_min = 12000000,
288 .cf_max = 19200000,
289 .vco_min = 600000000,
290 .vco_max = 1200000000,
291 .base_reg = PLLC2_BASE,
292 .misc_reg = PLLC2_MISC,
293 .lock_mask = PLL_BASE_LOCK,
294 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
295 .lock_delay = 300,
296 .pdiv_tohw = pllc_p,
297 .div_nmp = &pllcx_nmp,
298 .max_p = 7,
299 .ext_misc_reg[0] = 0x4f0,
300 .ext_misc_reg[1] = 0x4f4,
301 .ext_misc_reg[2] = 0x4f8,
302 .freq_table = pll_cx_freq_table,
303 .flags = TEGRA_PLL_USE_LOCK,
304};
305
306static struct tegra_clk_pll_params pll_c3_params = {
307 .input_min = 12000000,
308 .input_max = 48000000,
309 .cf_min = 12000000,
310 .cf_max = 19200000,
311 .vco_min = 600000000,
312 .vco_max = 1200000000,
313 .base_reg = PLLC3_BASE,
314 .misc_reg = PLLC3_MISC,
315 .lock_mask = PLL_BASE_LOCK,
316 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
317 .lock_delay = 300,
318 .pdiv_tohw = pllc_p,
319 .div_nmp = &pllcx_nmp,
320 .max_p = 7,
321 .ext_misc_reg[0] = 0x504,
322 .ext_misc_reg[1] = 0x508,
323 .ext_misc_reg[2] = 0x50c,
324 .freq_table = pll_cx_freq_table,
325 .flags = TEGRA_PLL_USE_LOCK,
326};
327
328static struct div_nmp pllss_nmp = {
329 .divm_shift = 0,
330 .divm_width = 8,
331 .divn_shift = 8,
332 .divn_width = 8,
333 .divp_shift = 20,
334 .divp_width = 4,
335};
336
337static struct pdiv_map pll12g_ssd_esd_p[] = {
338 { .pdiv = 1, .hw_val = 0 },
339 { .pdiv = 2, .hw_val = 1 },
340 { .pdiv = 3, .hw_val = 2 },
341 { .pdiv = 4, .hw_val = 3 },
342 { .pdiv = 5, .hw_val = 4 },
343 { .pdiv = 6, .hw_val = 5 },
344 { .pdiv = 8, .hw_val = 6 },
345 { .pdiv = 10, .hw_val = 7 },
346 { .pdiv = 12, .hw_val = 8 },
347 { .pdiv = 16, .hw_val = 9 },
348 { .pdiv = 12, .hw_val = 10 },
349 { .pdiv = 16, .hw_val = 11 },
350 { .pdiv = 20, .hw_val = 12 },
351 { .pdiv = 24, .hw_val = 13 },
352 { .pdiv = 32, .hw_val = 14 },
353 { .pdiv = 0, .hw_val = 0 },
354};
355
356static struct tegra_clk_pll_freq_table pll_c4_freq_table[] = {
357 { 12000000, 600000000, 100, 1, 1},
358 { 13000000, 600000000, 92, 1, 1}, /* actual: 598.0 MHz */
359 { 16800000, 600000000, 71, 1, 1}, /* actual: 596.4 MHz */
360 { 19200000, 600000000, 62, 1, 1}, /* actual: 595.2 MHz */
361 { 26000000, 600000000, 92, 2, 1}, /* actual: 598.0 MHz */
362 { 0, 0, 0, 0, 0, 0 },
363};
364
365static struct tegra_clk_pll_params pll_c4_params = {
366 .input_min = 12000000,
367 .input_max = 1000000000,
368 .cf_min = 12000000,
369 .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
370 .vco_min = 600000000,
371 .vco_max = 1200000000,
372 .base_reg = PLLC4_BASE,
373 .misc_reg = PLLC4_MISC,
374 .lock_mask = PLL_BASE_LOCK,
375 .lock_enable_bit_idx = PLLSS_MISC_LOCK_ENABLE,
376 .lock_delay = 300,
377 .iddq_reg = PLLC4_BASE,
378 .iddq_bit_idx = PLLSS_IDDQ_BIT,
379 .pdiv_tohw = pll12g_ssd_esd_p,
380 .div_nmp = &pllss_nmp,
381 .ext_misc_reg[0] = 0x5ac,
382 .ext_misc_reg[1] = 0x5b0,
383 .ext_misc_reg[2] = 0x5b4,
384 .freq_table = pll_c4_freq_table,
385};
386
387static struct pdiv_map pllm_p[] = {
388 { .pdiv = 1, .hw_val = 0 },
389 { .pdiv = 2, .hw_val = 1 },
390 { .pdiv = 0, .hw_val = 0 },
391};
392
393static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
394 {12000000, 800000000, 66, 1, 1}, /* actual: 792.0 MHz */
395 {13000000, 800000000, 61, 1, 1}, /* actual: 793.0 MHz */
396 {16800000, 800000000, 47, 1, 1}, /* actual: 789.6 MHz */
397 {19200000, 800000000, 41, 1, 1}, /* actual: 787.2 MHz */
398 {26000000, 800000000, 61, 2, 1}, /* actual: 793.0 MHz */
399 {0, 0, 0, 0, 0, 0},
400};
401
402static struct div_nmp pllm_nmp = {
403 .divm_shift = 0,
404 .divm_width = 8,
405 .override_divm_shift = 0,
406 .divn_shift = 8,
407 .divn_width = 8,
408 .override_divn_shift = 8,
409 .divp_shift = 20,
410 .divp_width = 1,
411 .override_divp_shift = 27,
412};
413
414static struct tegra_clk_pll_params pll_m_params = {
415 .input_min = 12000000,
416 .input_max = 500000000,
417 .cf_min = 12000000,
418 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
419 .vco_min = 400000000,
420 .vco_max = 1066000000,
421 .base_reg = PLLM_BASE,
422 .misc_reg = PLLM_MISC,
423 .lock_mask = PLL_BASE_LOCK,
424 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
425 .lock_delay = 300,
426 .max_p = 2,
427 .pdiv_tohw = pllm_p,
428 .div_nmp = &pllm_nmp,
429 .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,
430 .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2,
431 .freq_table = pll_m_freq_table,
432 .flags = TEGRA_PLL_USE_LOCK,
433};
434
435static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
436 /* PLLE special case: use cpcon field to store cml divider value */
437 {336000000, 100000000, 100, 21, 16, 11},
438 {312000000, 100000000, 200, 26, 24, 13},
439 {13000000, 100000000, 200, 1, 26, 13},
440 {12000000, 100000000, 200, 1, 24, 13},
441 {0, 0, 0, 0, 0, 0},
442};
443
444static struct div_nmp plle_nmp = {
445 .divm_shift = 0,
446 .divm_width = 8,
447 .divn_shift = 8,
448 .divn_width = 8,
449 .divp_shift = 24,
450 .divp_width = 4,
451};
452
453static struct tegra_clk_pll_params pll_e_params = {
454 .input_min = 12000000,
455 .input_max = 1000000000,
456 .cf_min = 12000000,
457 .cf_max = 75000000,
458 .vco_min = 1600000000,
459 .vco_max = 2400000000U,
460 .base_reg = PLLE_BASE,
461 .misc_reg = PLLE_MISC,
462 .aux_reg = PLLE_AUX,
463 .lock_mask = PLLE_MISC_LOCK,
464 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
465 .lock_delay = 300,
466 .div_nmp = &plle_nmp,
467 .freq_table = pll_e_freq_table,
468 .flags = TEGRA_PLL_FIXED,
469 .fixed_rate = 100000000,
470};
471
472static const struct clk_div_table pll_re_div_table[] = {
473 { .val = 0, .div = 1 },
474 { .val = 1, .div = 2 },
475 { .val = 2, .div = 3 },
476 { .val = 3, .div = 4 },
477 { .val = 4, .div = 5 },
478 { .val = 5, .div = 6 },
479 { .val = 0, .div = 0 },
480};
481
482static struct div_nmp pllre_nmp = {
483 .divm_shift = 0,
484 .divm_width = 8,
485 .divn_shift = 8,
486 .divn_width = 8,
487 .divp_shift = 16,
488 .divp_width = 4,
489};
490
491static struct tegra_clk_pll_params pll_re_vco_params = {
492 .input_min = 12000000,
493 .input_max = 1000000000,
494 .cf_min = 12000000,
495 .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
496 .vco_min = 300000000,
497 .vco_max = 600000000,
498 .base_reg = PLLRE_BASE,
499 .misc_reg = PLLRE_MISC,
500 .lock_mask = PLLRE_MISC_LOCK,
501 .lock_enable_bit_idx = PLLRE_MISC_LOCK_ENABLE,
502 .lock_delay = 300,
503 .iddq_reg = PLLRE_MISC,
504 .iddq_bit_idx = PLLRE_IDDQ_BIT,
505 .div_nmp = &pllre_nmp,
506 .flags = TEGRA_PLL_USE_LOCK,
507};
508
509static struct div_nmp pllp_nmp = {
510 .divm_shift = 0,
511 .divm_width = 5,
512 .divn_shift = 8,
513 .divn_width = 10,
514 .divp_shift = 20,
515 .divp_width = 3,
516};
517
518static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
519 {12000000, 216000000, 432, 12, 1, 8},
520 {13000000, 216000000, 432, 13, 1, 8},
521 {16800000, 216000000, 360, 14, 1, 8},
522 {19200000, 216000000, 360, 16, 1, 8},
523 {26000000, 216000000, 432, 26, 1, 8},
524 {0, 0, 0, 0, 0, 0},
525};
526
527static struct tegra_clk_pll_params pll_p_params = {
528 .input_min = 2000000,
529 .input_max = 31000000,
530 .cf_min = 1000000,
531 .cf_max = 6000000,
532 .vco_min = 200000000,
533 .vco_max = 700000000,
534 .base_reg = PLLP_BASE,
535 .misc_reg = PLLP_MISC,
536 .lock_mask = PLL_BASE_LOCK,
537 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
538 .lock_delay = 300,
539 .div_nmp = &pllp_nmp,
540 .freq_table = pll_p_freq_table,
541 .fixed_rate = 408000000,
542 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK,
543};
544
545static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
546 {9600000, 282240000, 147, 5, 0, 4},
547 {9600000, 368640000, 192, 5, 0, 4},
548 {9600000, 240000000, 200, 8, 0, 8},
549
550 {28800000, 282240000, 245, 25, 0, 8},
551 {28800000, 368640000, 320, 25, 0, 8},
552 {28800000, 240000000, 200, 24, 0, 8},
553 {0, 0, 0, 0, 0, 0},
554};
555
556static struct tegra_clk_pll_params pll_a_params = {
557 .input_min = 2000000,
558 .input_max = 31000000,
559 .cf_min = 1000000,
560 .cf_max = 6000000,
561 .vco_min = 200000000,
562 .vco_max = 700000000,
563 .base_reg = PLLA_BASE,
564 .misc_reg = PLLA_MISC,
565 .lock_mask = PLL_BASE_LOCK,
566 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
567 .lock_delay = 300,
568 .div_nmp = &pllp_nmp,
569 .freq_table = pll_a_freq_table,
570 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK,
571};
572
573static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
574 {12000000, 216000000, 864, 12, 4, 12},
575 {13000000, 216000000, 864, 13, 4, 12},
576 {16800000, 216000000, 720, 14, 4, 12},
577 {19200000, 216000000, 720, 16, 4, 12},
578 {26000000, 216000000, 864, 26, 4, 12},
579
580 {12000000, 594000000, 594, 12, 1, 12},
581 {13000000, 594000000, 594, 13, 1, 12},
582 {16800000, 594000000, 495, 14, 1, 12},
583 {19200000, 594000000, 495, 16, 1, 12},
584 {26000000, 594000000, 594, 26, 1, 12},
585
586 {12000000, 1000000000, 1000, 12, 1, 12},
587 {13000000, 1000000000, 1000, 13, 1, 12},
588 {19200000, 1000000000, 625, 12, 1, 12},
589 {26000000, 1000000000, 1000, 26, 1, 12},
590
591 {0, 0, 0, 0, 0, 0},
592};
593
594static struct tegra_clk_pll_params pll_d_params = {
595 .input_min = 2000000,
596 .input_max = 40000000,
597 .cf_min = 1000000,
598 .cf_max = 6000000,
599 .vco_min = 500000000,
600 .vco_max = 1000000000,
601 .base_reg = PLLD_BASE,
602 .misc_reg = PLLD_MISC,
603 .lock_mask = PLL_BASE_LOCK,
604 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
605 .lock_delay = 1000,
606 .div_nmp = &pllp_nmp,
607 .freq_table = pll_d_freq_table,
608 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
609 TEGRA_PLL_USE_LOCK,
610};
611
612static struct tegra_clk_pll_freq_table tegra124_pll_d2_freq_table[] = {
613 { 12000000, 148500000, 99, 1, 8},
614 { 12000000, 594000000, 99, 1, 1},
615 { 13000000, 594000000, 91, 1, 1}, /* actual: 591.5 MHz */
616 { 16800000, 594000000, 71, 1, 1}, /* actual: 596.4 MHz */
617 { 19200000, 594000000, 62, 1, 1}, /* actual: 595.2 MHz */
618 { 26000000, 594000000, 91, 2, 1}, /* actual: 591.5 MHz */
619 { 0, 0, 0, 0, 0, 0 },
620};
621
622static struct tegra_clk_pll_params tegra124_pll_d2_params = {
623 .input_min = 12000000,
624 .input_max = 1000000000,
625 .cf_min = 12000000,
626 .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
627 .vco_min = 600000000,
628 .vco_max = 1200000000,
629 .base_reg = PLLD2_BASE,
630 .misc_reg = PLLD2_MISC,
631 .lock_mask = PLL_BASE_LOCK,
632 .lock_enable_bit_idx = PLLSS_MISC_LOCK_ENABLE,
633 .lock_delay = 300,
634 .iddq_reg = PLLD2_BASE,
635 .iddq_bit_idx = PLLSS_IDDQ_BIT,
636 .pdiv_tohw = pll12g_ssd_esd_p,
637 .div_nmp = &pllss_nmp,
638 .ext_misc_reg[0] = 0x570,
639 .ext_misc_reg[1] = 0x574,
640 .ext_misc_reg[2] = 0x578,
641 .max_p = 15,
642 .freq_table = tegra124_pll_d2_freq_table,
643};
644
645static struct tegra_clk_pll_freq_table pll_dp_freq_table[] = {
646 { 12000000, 600000000, 100, 1, 1},
647 { 13000000, 600000000, 92, 1, 1}, /* actual: 598.0 MHz */
648 { 16800000, 600000000, 71, 1, 1}, /* actual: 596.4 MHz */
649 { 19200000, 600000000, 62, 1, 1}, /* actual: 595.2 MHz */
650 { 26000000, 600000000, 92, 2, 1}, /* actual: 598.0 MHz */
651 { 0, 0, 0, 0, 0, 0 },
652};
653
654static struct tegra_clk_pll_params pll_dp_params = {
655 .input_min = 12000000,
656 .input_max = 1000000000,
657 .cf_min = 12000000,
658 .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
659 .vco_min = 600000000,
660 .vco_max = 1200000000,
661 .base_reg = PLLDP_BASE,
662 .misc_reg = PLLDP_MISC,
663 .lock_mask = PLL_BASE_LOCK,
664 .lock_enable_bit_idx = PLLSS_MISC_LOCK_ENABLE,
665 .lock_delay = 300,
666 .iddq_reg = PLLDP_BASE,
667 .iddq_bit_idx = PLLSS_IDDQ_BIT,
668 .pdiv_tohw = pll12g_ssd_esd_p,
669 .div_nmp = &pllss_nmp,
670 .ext_misc_reg[0] = 0x598,
671 .ext_misc_reg[1] = 0x59c,
672 .ext_misc_reg[2] = 0x5a0,
673 .max_p = 5,
674 .freq_table = pll_dp_freq_table,
675};
676
677static struct pdiv_map pllu_p[] = {
678 { .pdiv = 1, .hw_val = 1 },
679 { .pdiv = 2, .hw_val = 0 },
680 { .pdiv = 0, .hw_val = 0 },
681};
682
683static struct div_nmp pllu_nmp = {
684 .divm_shift = 0,
685 .divm_width = 5,
686 .divn_shift = 8,
687 .divn_width = 10,
688 .divp_shift = 20,
689 .divp_width = 1,
690};
691
692static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
693 {12000000, 480000000, 960, 12, 2, 12},
694 {13000000, 480000000, 960, 13, 2, 12},
695 {16800000, 480000000, 400, 7, 2, 5},
696 {19200000, 480000000, 200, 4, 2, 3},
697 {26000000, 480000000, 960, 26, 2, 12},
698 {0, 0, 0, 0, 0, 0},
699};
700
701static struct tegra_clk_pll_params pll_u_params = {
702 .input_min = 2000000,
703 .input_max = 40000000,
704 .cf_min = 1000000,
705 .cf_max = 6000000,
706 .vco_min = 480000000,
707 .vco_max = 960000000,
708 .base_reg = PLLU_BASE,
709 .misc_reg = PLLU_MISC,
710 .lock_mask = PLL_BASE_LOCK,
711 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
712 .lock_delay = 1000,
713 .pdiv_tohw = pllu_p,
714 .div_nmp = &pllu_nmp,
715 .freq_table = pll_u_freq_table,
716 .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
717 TEGRA_PLL_USE_LOCK,
718};
719
720struct utmi_clk_param {
721 /* Oscillator Frequency in KHz */
722 u32 osc_frequency;
723 /* UTMIP PLL Enable Delay Count */
724 u8 enable_delay_count;
725 /* UTMIP PLL Stable count */
726 u8 stable_count;
727 /* UTMIP PLL Active delay count */
728 u8 active_delay_count;
729 /* UTMIP PLL Xtal frequency count */
730 u8 xtal_freq_count;
731};
732
733static const struct utmi_clk_param utmi_parameters[] = {
734 {.osc_frequency = 13000000, .enable_delay_count = 0x02,
735 .stable_count = 0x33, .active_delay_count = 0x05,
736 .xtal_freq_count = 0x7F},
737 {.osc_frequency = 19200000, .enable_delay_count = 0x03,
738 .stable_count = 0x4B, .active_delay_count = 0x06,
739 .xtal_freq_count = 0xBB},
740 {.osc_frequency = 12000000, .enable_delay_count = 0x02,
741 .stable_count = 0x2F, .active_delay_count = 0x04,
742 .xtal_freq_count = 0x76},
743 {.osc_frequency = 26000000, .enable_delay_count = 0x04,
744 .stable_count = 0x66, .active_delay_count = 0x09,
745 .xtal_freq_count = 0xFE},
746 {.osc_frequency = 16800000, .enable_delay_count = 0x03,
747 .stable_count = 0x41, .active_delay_count = 0x0A,
748 .xtal_freq_count = 0xA4},
749};
750
751static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
752 [tegra_clk_ispb] = { .dt_id = TEGRA124_CLK_ISPB, .present = true },
753 [tegra_clk_rtc] = { .dt_id = TEGRA124_CLK_RTC, .present = true },
754 [tegra_clk_timer] = { .dt_id = TEGRA124_CLK_TIMER, .present = true },
755 [tegra_clk_uarta] = { .dt_id = TEGRA124_CLK_UARTA, .present = true },
756 [tegra_clk_sdmmc2] = { .dt_id = TEGRA124_CLK_SDMMC2, .present = true },
757 [tegra_clk_i2s1] = { .dt_id = TEGRA124_CLK_I2S1, .present = true },
758 [tegra_clk_i2c1] = { .dt_id = TEGRA124_CLK_I2C1, .present = true },
759 [tegra_clk_ndflash] = { .dt_id = TEGRA124_CLK_NDFLASH, .present = true },
760 [tegra_clk_sdmmc1] = { .dt_id = TEGRA124_CLK_SDMMC1, .present = true },
761 [tegra_clk_sdmmc4] = { .dt_id = TEGRA124_CLK_SDMMC4, .present = true },
762 [tegra_clk_pwm] = { .dt_id = TEGRA124_CLK_PWM, .present = true },
763 [tegra_clk_i2s2] = { .dt_id = TEGRA124_CLK_I2S2, .present = true },
764 [tegra_clk_gr2d] = { .dt_id = TEGRA124_CLK_GR_2D, .present = true },
765 [tegra_clk_usbd] = { .dt_id = TEGRA124_CLK_USBD, .present = true },
766 [tegra_clk_isp_8] = { .dt_id = TEGRA124_CLK_ISP, .present = true },
767 [tegra_clk_gr3d] = { .dt_id = TEGRA124_CLK_GR_3D, .present = true },
768 [tegra_clk_disp2] = { .dt_id = TEGRA124_CLK_DISP2, .present = true },
769 [tegra_clk_disp1] = { .dt_id = TEGRA124_CLK_DISP1, .present = true },
770 [tegra_clk_host1x] = { .dt_id = TEGRA124_CLK_HOST1X, .present = true },
771 [tegra_clk_vcp] = { .dt_id = TEGRA124_CLK_VCP, .present = true },
772 [tegra_clk_i2s0] = { .dt_id = TEGRA124_CLK_I2S0, .present = true },
773 [tegra_clk_apbdma] = { .dt_id = TEGRA124_CLK_APBDMA, .present = true },
774 [tegra_clk_kbc] = { .dt_id = TEGRA124_CLK_KBC, .present = true },
775 [tegra_clk_kfuse] = { .dt_id = TEGRA124_CLK_KFUSE, .present = true },
776 [tegra_clk_sbc1] = { .dt_id = TEGRA124_CLK_SBC1, .present = true },
777 [tegra_clk_nor] = { .dt_id = TEGRA124_CLK_NOR, .present = true },
778 [tegra_clk_sbc2] = { .dt_id = TEGRA124_CLK_SBC2, .present = true },
779 [tegra_clk_sbc3] = { .dt_id = TEGRA124_CLK_SBC3, .present = true },
780 [tegra_clk_i2c5] = { .dt_id = TEGRA124_CLK_I2C5, .present = true },
781 [tegra_clk_dsia] = { .dt_id = TEGRA124_CLK_DSIA, .present = true },
782 [tegra_clk_mipi] = { .dt_id = TEGRA124_CLK_MIPI, .present = true },
783 [tegra_clk_hdmi] = { .dt_id = TEGRA124_CLK_HDMI, .present = true },
784 [tegra_clk_csi] = { .dt_id = TEGRA124_CLK_CSI, .present = true },
785 [tegra_clk_i2c2] = { .dt_id = TEGRA124_CLK_I2C2, .present = true },
786 [tegra_clk_uartc] = { .dt_id = TEGRA124_CLK_UARTC, .present = true },
787 [tegra_clk_mipi_cal] = { .dt_id = TEGRA124_CLK_MIPI_CAL, .present = true },
788 [tegra_clk_emc] = { .dt_id = TEGRA124_CLK_EMC, .present = true },
789 [tegra_clk_usb2] = { .dt_id = TEGRA124_CLK_USB2, .present = true },
790 [tegra_clk_usb3] = { .dt_id = TEGRA124_CLK_USB3, .present = true },
791 [tegra_clk_vde_8] = { .dt_id = TEGRA124_CLK_VDE, .present = true },
792 [tegra_clk_bsea] = { .dt_id = TEGRA124_CLK_BSEA, .present = true },
793 [tegra_clk_bsev] = { .dt_id = TEGRA124_CLK_BSEV, .present = true },
794 [tegra_clk_uartd] = { .dt_id = TEGRA124_CLK_UARTD, .present = true },
795 [tegra_clk_i2c3] = { .dt_id = TEGRA124_CLK_I2C3, .present = true },
796 [tegra_clk_sbc4] = { .dt_id = TEGRA124_CLK_SBC4, .present = true },
797 [tegra_clk_sdmmc3] = { .dt_id = TEGRA124_CLK_SDMMC3, .present = true },
798 [tegra_clk_pcie] = { .dt_id = TEGRA124_CLK_PCIE, .present = true },
799 [tegra_clk_owr] = { .dt_id = TEGRA124_CLK_OWR, .present = true },
800 [tegra_clk_afi] = { .dt_id = TEGRA124_CLK_AFI, .present = true },
801 [tegra_clk_csite] = { .dt_id = TEGRA124_CLK_CSITE, .present = true },
802 [tegra_clk_la] = { .dt_id = TEGRA124_CLK_LA, .present = true },
803 [tegra_clk_trace] = { .dt_id = TEGRA124_CLK_TRACE, .present = true },
804 [tegra_clk_soc_therm] = { .dt_id = TEGRA124_CLK_SOC_THERM, .present = true },
805 [tegra_clk_dtv] = { .dt_id = TEGRA124_CLK_DTV, .present = true },
806 [tegra_clk_ndspeed] = { .dt_id = TEGRA124_CLK_NDSPEED, .present = true },
807 [tegra_clk_i2cslow] = { .dt_id = TEGRA124_CLK_I2CSLOW, .present = true },
808 [tegra_clk_dsib] = { .dt_id = TEGRA124_CLK_DSIB, .present = true },
809 [tegra_clk_tsec] = { .dt_id = TEGRA124_CLK_TSEC, .present = true },
810 [tegra_clk_xusb_host] = { .dt_id = TEGRA124_CLK_XUSB_HOST, .present = true },
811 [tegra_clk_msenc] = { .dt_id = TEGRA124_CLK_MSENC, .present = true },
812 [tegra_clk_csus] = { .dt_id = TEGRA124_CLK_CSUS, .present = true },
813 [tegra_clk_mselect] = { .dt_id = TEGRA124_CLK_MSELECT, .present = true },
814 [tegra_clk_tsensor] = { .dt_id = TEGRA124_CLK_TSENSOR, .present = true },
815 [tegra_clk_i2s3] = { .dt_id = TEGRA124_CLK_I2S3, .present = true },
816 [tegra_clk_i2s4] = { .dt_id = TEGRA124_CLK_I2S4, .present = true },
817 [tegra_clk_i2c4] = { .dt_id = TEGRA124_CLK_I2C4, .present = true },
818 [tegra_clk_sbc5] = { .dt_id = TEGRA124_CLK_SBC5, .present = true },
819 [tegra_clk_sbc6] = { .dt_id = TEGRA124_CLK_SBC6, .present = true },
820 [tegra_clk_d_audio] = { .dt_id = TEGRA124_CLK_D_AUDIO, .present = true },
821 [tegra_clk_apbif] = { .dt_id = TEGRA124_CLK_APBIF, .present = true },
822 [tegra_clk_dam0] = { .dt_id = TEGRA124_CLK_DAM0, .present = true },
823 [tegra_clk_dam1] = { .dt_id = TEGRA124_CLK_DAM1, .present = true },
824 [tegra_clk_dam2] = { .dt_id = TEGRA124_CLK_DAM2, .present = true },
825 [tegra_clk_hda2codec_2x] = { .dt_id = TEGRA124_CLK_HDA2CODEC_2X, .present = true },
826 [tegra_clk_audio0_2x] = { .dt_id = TEGRA124_CLK_AUDIO0_2X, .present = true },
827 [tegra_clk_audio1_2x] = { .dt_id = TEGRA124_CLK_AUDIO1_2X, .present = true },
828 [tegra_clk_audio2_2x] = { .dt_id = TEGRA124_CLK_AUDIO2_2X, .present = true },
829 [tegra_clk_audio3_2x] = { .dt_id = TEGRA124_CLK_AUDIO3_2X, .present = true },
830 [tegra_clk_audio4_2x] = { .dt_id = TEGRA124_CLK_AUDIO4_2X, .present = true },
831 [tegra_clk_spdif_2x] = { .dt_id = TEGRA124_CLK_SPDIF_2X, .present = true },
832 [tegra_clk_actmon] = { .dt_id = TEGRA124_CLK_ACTMON, .present = true },
833 [tegra_clk_extern1] = { .dt_id = TEGRA124_CLK_EXTERN1, .present = true },
834 [tegra_clk_extern2] = { .dt_id = TEGRA124_CLK_EXTERN2, .present = true },
835 [tegra_clk_extern3] = { .dt_id = TEGRA124_CLK_EXTERN3, .present = true },
836 [tegra_clk_sata_oob] = { .dt_id = TEGRA124_CLK_SATA_OOB, .present = true },
837 [tegra_clk_sata] = { .dt_id = TEGRA124_CLK_SATA, .present = true },
838 [tegra_clk_hda] = { .dt_id = TEGRA124_CLK_HDA, .present = true },
839 [tegra_clk_se] = { .dt_id = TEGRA124_CLK_SE, .present = true },
840 [tegra_clk_hda2hdmi] = { .dt_id = TEGRA124_CLK_HDA2HDMI, .present = true },
841 [tegra_clk_sata_cold] = { .dt_id = TEGRA124_CLK_SATA_COLD, .present = true },
842 [tegra_clk_cilab] = { .dt_id = TEGRA124_CLK_CILAB, .present = true },
843 [tegra_clk_cilcd] = { .dt_id = TEGRA124_CLK_CILCD, .present = true },
844 [tegra_clk_cile] = { .dt_id = TEGRA124_CLK_CILE, .present = true },
845 [tegra_clk_dsialp] = { .dt_id = TEGRA124_CLK_DSIALP, .present = true },
846 [tegra_clk_dsiblp] = { .dt_id = TEGRA124_CLK_DSIBLP, .present = true },
847 [tegra_clk_entropy] = { .dt_id = TEGRA124_CLK_ENTROPY, .present = true },
848 [tegra_clk_dds] = { .dt_id = TEGRA124_CLK_DDS, .present = true },
849 [tegra_clk_dp2] = { .dt_id = TEGRA124_CLK_DP2, .present = true },
850 [tegra_clk_amx] = { .dt_id = TEGRA124_CLK_AMX, .present = true },
851 [tegra_clk_adx] = { .dt_id = TEGRA124_CLK_ADX, .present = true },
852 [tegra_clk_xusb_ss] = { .dt_id = TEGRA124_CLK_XUSB_SS, .present = true },
853 [tegra_clk_i2c6] = { .dt_id = TEGRA124_CLK_I2C6, .present = true },
854 [tegra_clk_vim2_clk] = { .dt_id = TEGRA124_CLK_VIM2_CLK, .present = true },
855 [tegra_clk_hdmi_audio] = { .dt_id = TEGRA124_CLK_HDMI_AUDIO, .present = true },
856 [tegra_clk_clk72Mhz] = { .dt_id = TEGRA124_CLK_CLK72MHZ, .present = true },
857 [tegra_clk_vic03] = { .dt_id = TEGRA124_CLK_VIC03, .present = true },
858 [tegra_clk_adx1] = { .dt_id = TEGRA124_CLK_ADX1, .present = true },
859 [tegra_clk_dpaux] = { .dt_id = TEGRA124_CLK_DPAUX, .present = true },
860 [tegra_clk_sor0] = { .dt_id = TEGRA124_CLK_SOR0, .present = true },
861 [tegra_clk_sor0_lvds] = { .dt_id = TEGRA124_CLK_SOR0_LVDS, .present = true },
862 [tegra_clk_gpu] = { .dt_id = TEGRA124_CLK_GPU, .present = true },
863 [tegra_clk_amx1] = { .dt_id = TEGRA124_CLK_AMX1, .present = true },
864 [tegra_clk_uartb] = { .dt_id = TEGRA124_CLK_UARTB, .present = true },
865 [tegra_clk_vfir] = { .dt_id = TEGRA124_CLK_VFIR, .present = true },
866 [tegra_clk_spdif_in] = { .dt_id = TEGRA124_CLK_SPDIF_IN, .present = true },
867 [tegra_clk_spdif_out] = { .dt_id = TEGRA124_CLK_SPDIF_OUT, .present = true },
868 [tegra_clk_vi_9] = { .dt_id = TEGRA124_CLK_VI, .present = true },
869 [tegra_clk_vi_sensor] = { .dt_id = TEGRA124_CLK_VI_SENSOR, .present = true },
870 [tegra_clk_fuse] = { .dt_id = TEGRA124_CLK_FUSE, .present = true },
871 [tegra_clk_fuse_burn] = { .dt_id = TEGRA124_CLK_FUSE_BURN, .present = true },
872 [tegra_clk_clk_32k] = { .dt_id = TEGRA124_CLK_CLK_32K, .present = true },
873 [tegra_clk_clk_m] = { .dt_id = TEGRA124_CLK_CLK_M, .present = true },
874 [tegra_clk_clk_m_div2] = { .dt_id = TEGRA124_CLK_CLK_M_DIV2, .present = true },
875 [tegra_clk_clk_m_div4] = { .dt_id = TEGRA124_CLK_CLK_M_DIV4, .present = true },
876 [tegra_clk_pll_ref] = { .dt_id = TEGRA124_CLK_PLL_REF, .present = true },
877 [tegra_clk_pll_c] = { .dt_id = TEGRA124_CLK_PLL_C, .present = true },
878 [tegra_clk_pll_c_out1] = { .dt_id = TEGRA124_CLK_PLL_C_OUT1, .present = true },
879 [tegra_clk_pll_c2] = { .dt_id = TEGRA124_CLK_PLL_C2, .present = true },
880 [tegra_clk_pll_c3] = { .dt_id = TEGRA124_CLK_PLL_C3, .present = true },
881 [tegra_clk_pll_m] = { .dt_id = TEGRA124_CLK_PLL_M, .present = true },
882 [tegra_clk_pll_m_out1] = { .dt_id = TEGRA124_CLK_PLL_M_OUT1, .present = true },
883 [tegra_clk_pll_p] = { .dt_id = TEGRA124_CLK_PLL_P, .present = true },
884 [tegra_clk_pll_p_out1] = { .dt_id = TEGRA124_CLK_PLL_P_OUT1, .present = true },
885 [tegra_clk_pll_p_out2] = { .dt_id = TEGRA124_CLK_PLL_P_OUT2, .present = true },
886 [tegra_clk_pll_p_out3] = { .dt_id = TEGRA124_CLK_PLL_P_OUT3, .present = true },
887 [tegra_clk_pll_p_out4] = { .dt_id = TEGRA124_CLK_PLL_P_OUT4, .present = true },
888 [tegra_clk_pll_a] = { .dt_id = TEGRA124_CLK_PLL_A, .present = true },
889 [tegra_clk_pll_a_out0] = { .dt_id = TEGRA124_CLK_PLL_A_OUT0, .present = true },
890 [tegra_clk_pll_d] = { .dt_id = TEGRA124_CLK_PLL_D, .present = true },
891 [tegra_clk_pll_d_out0] = { .dt_id = TEGRA124_CLK_PLL_D_OUT0, .present = true },
892 [tegra_clk_pll_d2] = { .dt_id = TEGRA124_CLK_PLL_D2, .present = true },
893 [tegra_clk_pll_d2_out0] = { .dt_id = TEGRA124_CLK_PLL_D2_OUT0, .present = true },
894 [tegra_clk_pll_u] = { .dt_id = TEGRA124_CLK_PLL_U, .present = true },
895 [tegra_clk_pll_u_480m] = { .dt_id = TEGRA124_CLK_PLL_U_480M, .present = true },
896 [tegra_clk_pll_u_60m] = { .dt_id = TEGRA124_CLK_PLL_U_60M, .present = true },
897 [tegra_clk_pll_u_48m] = { .dt_id = TEGRA124_CLK_PLL_U_48M, .present = true },
898 [tegra_clk_pll_u_12m] = { .dt_id = TEGRA124_CLK_PLL_U_12M, .present = true },
899 [tegra_clk_pll_x] = { .dt_id = TEGRA124_CLK_PLL_X, .present = true },
900 [tegra_clk_pll_x_out0] = { .dt_id = TEGRA124_CLK_PLL_X_OUT0, .present = true },
901 [tegra_clk_pll_re_vco] = { .dt_id = TEGRA124_CLK_PLL_RE_VCO, .present = true },
902 [tegra_clk_pll_re_out] = { .dt_id = TEGRA124_CLK_PLL_RE_OUT, .present = true },
903 [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA124_CLK_SPDIF_IN_SYNC, .present = true },
904 [tegra_clk_i2s0_sync] = { .dt_id = TEGRA124_CLK_I2S0_SYNC, .present = true },
905 [tegra_clk_i2s1_sync] = { .dt_id = TEGRA124_CLK_I2S1_SYNC, .present = true },
906 [tegra_clk_i2s2_sync] = { .dt_id = TEGRA124_CLK_I2S2_SYNC, .present = true },
907 [tegra_clk_i2s3_sync] = { .dt_id = TEGRA124_CLK_I2S3_SYNC, .present = true },
908 [tegra_clk_i2s4_sync] = { .dt_id = TEGRA124_CLK_I2S4_SYNC, .present = true },
909 [tegra_clk_vimclk_sync] = { .dt_id = TEGRA124_CLK_VIMCLK_SYNC, .present = true },
910 [tegra_clk_audio0] = { .dt_id = TEGRA124_CLK_AUDIO0, .present = true },
911 [tegra_clk_audio1] = { .dt_id = TEGRA124_CLK_AUDIO1, .present = true },
912 [tegra_clk_audio2] = { .dt_id = TEGRA124_CLK_AUDIO2, .present = true },
913 [tegra_clk_audio3] = { .dt_id = TEGRA124_CLK_AUDIO3, .present = true },
914 [tegra_clk_audio4] = { .dt_id = TEGRA124_CLK_AUDIO4, .present = true },
915 [tegra_clk_spdif] = { .dt_id = TEGRA124_CLK_SPDIF, .present = true },
916 [tegra_clk_clk_out_1] = { .dt_id = TEGRA124_CLK_CLK_OUT_1, .present = true },
917 [tegra_clk_clk_out_2] = { .dt_id = TEGRA124_CLK_CLK_OUT_2, .present = true },
918 [tegra_clk_clk_out_3] = { .dt_id = TEGRA124_CLK_CLK_OUT_3, .present = true },
919 [tegra_clk_blink] = { .dt_id = TEGRA124_CLK_BLINK, .present = true },
920 [tegra_clk_xusb_host_src] = { .dt_id = TEGRA124_CLK_XUSB_HOST_SRC, .present = true },
921 [tegra_clk_xusb_falcon_src] = { .dt_id = TEGRA124_CLK_XUSB_FALCON_SRC, .present = true },
922 [tegra_clk_xusb_fs_src] = { .dt_id = TEGRA124_CLK_XUSB_FS_SRC, .present = true },
923 [tegra_clk_xusb_ss_src] = { .dt_id = TEGRA124_CLK_XUSB_SS_SRC, .present = true },
924 [tegra_clk_xusb_dev_src] = { .dt_id = TEGRA124_CLK_XUSB_DEV_SRC, .present = true },
925 [tegra_clk_xusb_dev] = { .dt_id = TEGRA124_CLK_XUSB_DEV, .present = true },
926 [tegra_clk_xusb_hs_src] = { .dt_id = TEGRA124_CLK_XUSB_HS_SRC, .present = true },
927 [tegra_clk_sclk] = { .dt_id = TEGRA124_CLK_SCLK, .present = true },
928 [tegra_clk_hclk] = { .dt_id = TEGRA124_CLK_HCLK, .present = true },
929 [tegra_clk_pclk] = { .dt_id = TEGRA124_CLK_PCLK, .present = true },
930 [tegra_clk_cclk_g] = { .dt_id = TEGRA124_CLK_CCLK_G, .present = true },
931 [tegra_clk_cclk_lp] = { .dt_id = TEGRA124_CLK_CCLK_LP, .present = true },
932 [tegra_clk_dfll_ref] = { .dt_id = TEGRA124_CLK_DFLL_REF, .present = true },
933 [tegra_clk_dfll_soc] = { .dt_id = TEGRA124_CLK_DFLL_SOC, .present = true },
934 [tegra_clk_vi_sensor2] = { .dt_id = TEGRA124_CLK_VI_SENSOR2, .present = true },
935 [tegra_clk_pll_p_out5] = { .dt_id = TEGRA124_CLK_PLL_P_OUT5, .present = true },
936 [tegra_clk_pll_c4] = { .dt_id = TEGRA124_CLK_PLL_C4, .present = true },
937 [tegra_clk_pll_dp] = { .dt_id = TEGRA124_CLK_PLL_DP, .present = true },
938 [tegra_clk_audio0_mux] = { .dt_id = TEGRA124_CLK_AUDIO0_MUX, .present = true },
939 [tegra_clk_audio1_mux] = { .dt_id = TEGRA124_CLK_AUDIO1_MUX, .present = true },
940 [tegra_clk_audio2_mux] = { .dt_id = TEGRA124_CLK_AUDIO2_MUX, .present = true },
941 [tegra_clk_audio3_mux] = { .dt_id = TEGRA124_CLK_AUDIO3_MUX, .present = true },
942 [tegra_clk_audio4_mux] = { .dt_id = TEGRA124_CLK_AUDIO4_MUX, .present = true },
943 [tegra_clk_spdif_mux] = { .dt_id = TEGRA124_CLK_SPDIF_MUX, .present = true },
944 [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_1_MUX, .present = true },
945 [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_2_MUX, .present = true },
946 [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_3_MUX, .present = true },
947 [tegra_clk_dsia_mux] = { .dt_id = TEGRA124_CLK_DSIA_MUX, .present = true },
948 [tegra_clk_dsib_mux] = { .dt_id = TEGRA124_CLK_DSIB_MUX, .present = true },
949 [tegra_clk_uarte] = { .dt_id = TEGRA124_CLK_UARTE, .present = true },
950};
951
952static struct tegra_devclk devclks[] __initdata = {
953 { .con_id = "clk_m", .dt_id = TEGRA124_CLK_CLK_M },
954 { .con_id = "pll_ref", .dt_id = TEGRA124_CLK_PLL_REF },
955 { .con_id = "clk_32k", .dt_id = TEGRA124_CLK_CLK_32K },
956 { .con_id = "clk_m_div2", .dt_id = TEGRA124_CLK_CLK_M_DIV2 },
957 { .con_id = "clk_m_div4", .dt_id = TEGRA124_CLK_CLK_M_DIV4 },
958 { .con_id = "pll_c", .dt_id = TEGRA124_CLK_PLL_C },
959 { .con_id = "pll_c_out1", .dt_id = TEGRA124_CLK_PLL_C_OUT1 },
960 { .con_id = "pll_c2", .dt_id = TEGRA124_CLK_PLL_C2 },
961 { .con_id = "pll_c3", .dt_id = TEGRA124_CLK_PLL_C3 },
962 { .con_id = "pll_p", .dt_id = TEGRA124_CLK_PLL_P },
963 { .con_id = "pll_p_out1", .dt_id = TEGRA124_CLK_PLL_P_OUT1 },
964 { .con_id = "pll_p_out2", .dt_id = TEGRA124_CLK_PLL_P_OUT2 },
965 { .con_id = "pll_p_out3", .dt_id = TEGRA124_CLK_PLL_P_OUT3 },
966 { .con_id = "pll_p_out4", .dt_id = TEGRA124_CLK_PLL_P_OUT4 },
967 { .con_id = "pll_m", .dt_id = TEGRA124_CLK_PLL_M },
968 { .con_id = "pll_m_out1", .dt_id = TEGRA124_CLK_PLL_M_OUT1 },
969 { .con_id = "pll_x", .dt_id = TEGRA124_CLK_PLL_X },
970 { .con_id = "pll_x_out0", .dt_id = TEGRA124_CLK_PLL_X_OUT0 },
971 { .con_id = "pll_u", .dt_id = TEGRA124_CLK_PLL_U },
972 { .con_id = "pll_u_480M", .dt_id = TEGRA124_CLK_PLL_U_480M },
973 { .con_id = "pll_u_60M", .dt_id = TEGRA124_CLK_PLL_U_60M },
974 { .con_id = "pll_u_48M", .dt_id = TEGRA124_CLK_PLL_U_48M },
975 { .con_id = "pll_u_12M", .dt_id = TEGRA124_CLK_PLL_U_12M },
976 { .con_id = "pll_d", .dt_id = TEGRA124_CLK_PLL_D },
977 { .con_id = "pll_d_out0", .dt_id = TEGRA124_CLK_PLL_D_OUT0 },
978 { .con_id = "pll_d2", .dt_id = TEGRA124_CLK_PLL_D2 },
979 { .con_id = "pll_d2_out0", .dt_id = TEGRA124_CLK_PLL_D2_OUT0 },
980 { .con_id = "pll_a", .dt_id = TEGRA124_CLK_PLL_A },
981 { .con_id = "pll_a_out0", .dt_id = TEGRA124_CLK_PLL_A_OUT0 },
982 { .con_id = "pll_re_vco", .dt_id = TEGRA124_CLK_PLL_RE_VCO },
983 { .con_id = "pll_re_out", .dt_id = TEGRA124_CLK_PLL_RE_OUT },
984 { .con_id = "spdif_in_sync", .dt_id = TEGRA124_CLK_SPDIF_IN_SYNC },
985 { .con_id = "i2s0_sync", .dt_id = TEGRA124_CLK_I2S0_SYNC },
986 { .con_id = "i2s1_sync", .dt_id = TEGRA124_CLK_I2S1_SYNC },
987 { .con_id = "i2s2_sync", .dt_id = TEGRA124_CLK_I2S2_SYNC },
988 { .con_id = "i2s3_sync", .dt_id = TEGRA124_CLK_I2S3_SYNC },
989 { .con_id = "i2s4_sync", .dt_id = TEGRA124_CLK_I2S4_SYNC },
990 { .con_id = "vimclk_sync", .dt_id = TEGRA124_CLK_VIMCLK_SYNC },
991 { .con_id = "audio0", .dt_id = TEGRA124_CLK_AUDIO0 },
992 { .con_id = "audio1", .dt_id = TEGRA124_CLK_AUDIO1 },
993 { .con_id = "audio2", .dt_id = TEGRA124_CLK_AUDIO2 },
994 { .con_id = "audio3", .dt_id = TEGRA124_CLK_AUDIO3 },
995 { .con_id = "audio4", .dt_id = TEGRA124_CLK_AUDIO4 },
996 { .con_id = "spdif", .dt_id = TEGRA124_CLK_SPDIF },
997 { .con_id = "audio0_2x", .dt_id = TEGRA124_CLK_AUDIO0_2X },
998 { .con_id = "audio1_2x", .dt_id = TEGRA124_CLK_AUDIO1_2X },
999 { .con_id = "audio2_2x", .dt_id = TEGRA124_CLK_AUDIO2_2X },
1000 { .con_id = "audio3_2x", .dt_id = TEGRA124_CLK_AUDIO3_2X },
1001 { .con_id = "audio4_2x", .dt_id = TEGRA124_CLK_AUDIO4_2X },
1002 { .con_id = "spdif_2x", .dt_id = TEGRA124_CLK_SPDIF_2X },
1003 { .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA124_CLK_EXTERN1 },
1004 { .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA124_CLK_EXTERN2 },
1005 { .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA124_CLK_EXTERN3 },
1006 { .con_id = "blink", .dt_id = TEGRA124_CLK_BLINK },
1007 { .con_id = "cclk_g", .dt_id = TEGRA124_CLK_CCLK_G },
1008 { .con_id = "cclk_lp", .dt_id = TEGRA124_CLK_CCLK_LP },
1009 { .con_id = "sclk", .dt_id = TEGRA124_CLK_SCLK },
1010 { .con_id = "hclk", .dt_id = TEGRA124_CLK_HCLK },
1011 { .con_id = "pclk", .dt_id = TEGRA124_CLK_PCLK },
1012 { .con_id = "fuse", .dt_id = TEGRA124_CLK_FUSE },
1013 { .dev_id = "rtc-tegra", .dt_id = TEGRA124_CLK_RTC },
1014 { .dev_id = "timer", .dt_id = TEGRA124_CLK_TIMER },
1015};
1016
1017static struct clk **clks;
1018
1019static void tegra124_utmi_param_configure(void __iomem *clk_base)
1020{
1021 u32 reg;
1022 int i;
1023
1024 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
1025 if (osc_freq == utmi_parameters[i].osc_frequency)
1026 break;
1027 }
1028
1029 if (i >= ARRAY_SIZE(utmi_parameters)) {
1030 pr_err("%s: Unexpected oscillator freq %lu\n", __func__,
1031 osc_freq);
1032 return;
1033 }
1034
1035 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
1036
1037 /* Program UTMIP PLL stable and active counts */
1038 /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */
1039 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
1040 reg |= UTMIP_PLL_CFG2_STABLE_COUNT(utmi_parameters[i].stable_count);
1041
1042 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
1043
1044 reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(utmi_parameters[i].
1045 active_delay_count);
1046
1047 /* Remove power downs from UTMIP PLL control bits */
1048 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
1049 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
1050 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
1051
1052 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);
1053
1054 /* Program UTMIP PLL delay and oscillator frequency counts */
1055 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
1056 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
1057
1058 reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(utmi_parameters[i].
1059 enable_delay_count);
1060
1061 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
1062 reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(utmi_parameters[i].
1063 xtal_freq_count);
1064
1065 /* Remove power downs from UTMIP PLL control bits */
1066 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1067 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
1068 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP;
1069 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
1070 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
1071
1072 /* Setup HW control of UTMIPLL */
1073 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
1074 reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
1075 reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
1076 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE;
1077 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
1078
1079 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
1080 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
1081 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1082 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
1083
1084 udelay(1);
1085
1086 /* Setup SW override of UTMIPLL assuming USB2.0
1087 ports are assigned to USB2 */
1088 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
1089 reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL;
1090 reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
1091 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
1092
1093 udelay(1);
1094
1095 /* Enable HW control UTMIPLL */
1096 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
1097 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
1098 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
1099}
1100
1101static __init void tegra124_periph_clk_init(void __iomem *clk_base,
1102 void __iomem *pmc_base)
1103{
1104 struct clk *clk;
1105 u32 val;
1106
1107 /* xusb_hs_src */
1108 val = readl(clk_base + CLK_SOURCE_XUSB_SS_SRC);
1109 val |= BIT(25); /* always select PLLU_60M */
1110 writel(val, clk_base + CLK_SOURCE_XUSB_SS_SRC);
1111
1112 clk = clk_register_fixed_factor(NULL, "xusb_hs_src", "pll_u_60M", 0,
1113 1, 1);
1114 clks[TEGRA124_CLK_XUSB_HS_SRC] = clk;
1115
1116 /* dsia mux */
1117 clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0,
1118 ARRAY_SIZE(mux_plld_out0_plld2_out0), 0,
1119 clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock);
1120 clks[TEGRA124_CLK_DSIA_MUX] = clk;
1121
1122 /* dsib mux */
1123 clk = clk_register_mux(NULL, "dsib_mux", mux_plld_out0_plld2_out0,
1124 ARRAY_SIZE(mux_plld_out0_plld2_out0), 0,
1125 clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock);
1126 clks[TEGRA124_CLK_DSIB_MUX] = clk;
1127
1128 /* emc mux */
1129 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
1130 ARRAY_SIZE(mux_pllmcp_clkm), 0,
1131 clk_base + CLK_SOURCE_EMC,
1132 29, 3, 0, NULL);
1133
1134 /* cml0 */
1135 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,
1136 0, 0, &pll_e_lock);
1137 clk_register_clkdev(clk, "cml0", NULL);
1138 clks[TEGRA124_CLK_CML0] = clk;
1139
1140 /* cml1 */
1141 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,
1142 1, 0, &pll_e_lock);
1143 clk_register_clkdev(clk, "cml1", NULL);
1144 clks[TEGRA124_CLK_CML1] = clk;
1145
1146 tegra_periph_clk_init(clk_base, pmc_base, tegra124_clks, &pll_p_params);
1147}
1148
1149static void __init tegra124_pll_init(void __iomem *clk_base,
1150 void __iomem *pmc)
1151{
1152 u32 val;
1153 struct clk *clk;
1154
1155 /* PLLC */
1156 clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base,
1157 pmc, 0, &pll_c_params, NULL);
1158 clk_register_clkdev(clk, "pll_c", NULL);
1159 clks[TEGRA124_CLK_PLL_C] = clk;
1160
1161 /* PLLC_OUT1 */
1162 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
1163 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
1164 8, 8, 1, NULL);
1165 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
1166 clk_base + PLLC_OUT, 1, 0,
1167 CLK_SET_RATE_PARENT, 0, NULL);
1168 clk_register_clkdev(clk, "pll_c_out1", NULL);
1169 clks[TEGRA124_CLK_PLL_C_OUT1] = clk;
1170
1171 /* PLLC2 */
1172 clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0,
1173 &pll_c2_params, NULL);
1174 clk_register_clkdev(clk, "pll_c2", NULL);
1175 clks[TEGRA124_CLK_PLL_C2] = clk;
1176
1177 /* PLLC3 */
1178 clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0,
1179 &pll_c3_params, NULL);
1180 clk_register_clkdev(clk, "pll_c3", NULL);
1181 clks[TEGRA124_CLK_PLL_C3] = clk;
1182
1183 /* PLLM */
1184 clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc,
1185 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
1186 &pll_m_params, NULL);
1187 clk_register_clkdev(clk, "pll_m", NULL);
1188 clks[TEGRA124_CLK_PLL_M] = clk;
1189
1190 /* PLLM_OUT1 */
1191 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
1192 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
1193 8, 8, 1, NULL);
1194 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
1195 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |
1196 CLK_SET_RATE_PARENT, 0, NULL);
1197 clk_register_clkdev(clk, "pll_m_out1", NULL);
1198 clks[TEGRA124_CLK_PLL_M_OUT1] = clk;
1199
1200 /* PLLM_UD */
1201 clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m",
1202 CLK_SET_RATE_PARENT, 1, 1);
1203
1204 /* PLLU */
1205 val = readl(clk_base + pll_u_params.base_reg);
1206 val &= ~BIT(24); /* disable PLLU_OVERRIDE */
1207 writel(val, clk_base + pll_u_params.base_reg);
1208
1209 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc, 0,
1210 &pll_u_params, &pll_u_lock);
1211 clk_register_clkdev(clk, "pll_u", NULL);
1212 clks[TEGRA124_CLK_PLL_U] = clk;
1213
1214 tegra124_utmi_param_configure(clk_base);
1215
1216 /* PLLU_480M */
1217 clk = clk_register_gate(NULL, "pll_u_480M", "pll_u",
1218 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
1219 22, 0, &pll_u_lock);
1220 clk_register_clkdev(clk, "pll_u_480M", NULL);
1221 clks[TEGRA124_CLK_PLL_U_480M] = clk;
1222
1223 /* PLLU_60M */
1224 clk = clk_register_fixed_factor(NULL, "pll_u_60M", "pll_u",
1225 CLK_SET_RATE_PARENT, 1, 8);
1226 clk_register_clkdev(clk, "pll_u_60M", NULL);
1227 clks[TEGRA124_CLK_PLL_U_60M] = clk;
1228
1229 /* PLLU_48M */
1230 clk = clk_register_fixed_factor(NULL, "pll_u_48M", "pll_u",
1231 CLK_SET_RATE_PARENT, 1, 10);
1232 clk_register_clkdev(clk, "pll_u_48M", NULL);
1233 clks[TEGRA124_CLK_PLL_U_48M] = clk;
1234
1235 /* PLLU_12M */
1236 clk = clk_register_fixed_factor(NULL, "pll_u_12M", "pll_u",
1237 CLK_SET_RATE_PARENT, 1, 40);
1238 clk_register_clkdev(clk, "pll_u_12M", NULL);
1239 clks[TEGRA124_CLK_PLL_U_12M] = clk;
1240
1241 /* PLLD */
1242 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0,
1243 &pll_d_params, &pll_d_lock);
1244 clk_register_clkdev(clk, "pll_d", NULL);
1245 clks[TEGRA124_CLK_PLL_D] = clk;
1246
1247 /* PLLD_OUT0 */
1248 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
1249 CLK_SET_RATE_PARENT, 1, 2);
1250 clk_register_clkdev(clk, "pll_d_out0", NULL);
1251 clks[TEGRA124_CLK_PLL_D_OUT0] = clk;
1252
1253 /* PLLRE */
1254 clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc,
1255 0, &pll_re_vco_params, &pll_re_lock, pll_ref_freq);
1256 clk_register_clkdev(clk, "pll_re_vco", NULL);
1257 clks[TEGRA124_CLK_PLL_RE_VCO] = clk;
1258
1259 clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0,
1260 clk_base + PLLRE_BASE, 16, 4, 0,
1261 pll_re_div_table, &pll_re_lock);
1262 clk_register_clkdev(clk, "pll_re_out", NULL);
1263 clks[TEGRA124_CLK_PLL_RE_OUT] = clk;
1264
1265 /* PLLE */
1266 clk = tegra_clk_register_plle_tegra114("pll_e", "pll_ref",
1267 clk_base, 0, &pll_e_params, NULL);
1268 clk_register_clkdev(clk, "pll_e", NULL);
1269 clks[TEGRA124_CLK_PLL_E] = clk;
1270
1271 /* PLLC4 */
1272 clk = tegra_clk_register_pllss("pll_c4", "pll_ref", clk_base, 0,
1273 &pll_c4_params, NULL);
1274 clk_register_clkdev(clk, "pll_c4", NULL);
1275 clks[TEGRA124_CLK_PLL_C4] = clk;
1276
1277 /* PLLDP */
1278 clk = tegra_clk_register_pllss("pll_dp", "pll_ref", clk_base, 0,
1279 &pll_dp_params, NULL);
1280 clk_register_clkdev(clk, "pll_dp", NULL);
1281 clks[TEGRA124_CLK_PLL_DP] = clk;
1282
1283 /* PLLD2 */
1284 clk = tegra_clk_register_pllss("pll_d2", "pll_ref", clk_base, 0,
1285 &tegra124_pll_d2_params, NULL);
1286 clk_register_clkdev(clk, "pll_d2", NULL);
1287 clks[TEGRA124_CLK_PLL_D2] = clk;
1288
1289 /* PLLD2_OUT0 ?? */
1290 clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
1291 CLK_SET_RATE_PARENT, 1, 2);
1292 clk_register_clkdev(clk, "pll_d2_out0", NULL);
1293 clks[TEGRA124_CLK_PLL_D2_OUT0] = clk;
1294
1295}
1296
1297/* Tegra124 CPU clock and reset control functions */
1298static void tegra124_wait_cpu_in_reset(u32 cpu)
1299{
1300 unsigned int reg;
1301
1302 do {
1303 reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
1304 cpu_relax();
1305 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */
1306}
1307
1308static void tegra124_disable_cpu_clock(u32 cpu)
1309{
1310 /* flow controller would take care in the power sequence. */
1311}
1312
1313#ifdef CONFIG_PM_SLEEP
1314static void tegra124_cpu_clock_suspend(void)
1315{
1316 /* switch coresite to clk_m, save off original source */
1317 tegra124_cpu_clk_sctx.clk_csite_src =
1318 readl(clk_base + CLK_SOURCE_CSITE);
1319 writel(3 << 30, clk_base + CLK_SOURCE_CSITE);
1320}
1321
1322static void tegra124_cpu_clock_resume(void)
1323{
1324 writel(tegra124_cpu_clk_sctx.clk_csite_src,
1325 clk_base + CLK_SOURCE_CSITE);
1326}
1327#endif
1328
1329static struct tegra_cpu_car_ops tegra124_cpu_car_ops = {
1330 .wait_for_reset = tegra124_wait_cpu_in_reset,
1331 .disable_clock = tegra124_disable_cpu_clock,
1332#ifdef CONFIG_PM_SLEEP
1333 .suspend = tegra124_cpu_clock_suspend,
1334 .resume = tegra124_cpu_clock_resume,
1335#endif
1336};
1337
1338static const struct of_device_id pmc_match[] __initconst = {
1339 { .compatible = "nvidia,tegra124-pmc" },
1340 {},
1341};
1342
1343static struct tegra_clk_init_table init_table[] __initdata = {
1344 {TEGRA124_CLK_UARTA, TEGRA124_CLK_PLL_P, 408000000, 0},
1345 {TEGRA124_CLK_UARTB, TEGRA124_CLK_PLL_P, 408000000, 0},
1346 {TEGRA124_CLK_UARTC, TEGRA124_CLK_PLL_P, 408000000, 0},
1347 {TEGRA124_CLK_UARTD, TEGRA124_CLK_PLL_P, 408000000, 0},
1348 {TEGRA124_CLK_PLL_A, TEGRA124_CLK_CLK_MAX, 564480000, 1},
1349 {TEGRA124_CLK_PLL_A_OUT0, TEGRA124_CLK_CLK_MAX, 11289600, 1},
1350 {TEGRA124_CLK_EXTERN1, TEGRA124_CLK_PLL_A_OUT0, 0, 1},
1351 {TEGRA124_CLK_CLK_OUT_1_MUX, TEGRA124_CLK_EXTERN1, 0, 1},
1352 {TEGRA124_CLK_CLK_OUT_1, TEGRA124_CLK_CLK_MAX, 0, 1},
1353 {TEGRA124_CLK_I2S0, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0},
1354 {TEGRA124_CLK_I2S1, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0},
1355 {TEGRA124_CLK_I2S2, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0},
1356 {TEGRA124_CLK_I2S3, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0},
1357 {TEGRA124_CLK_I2S4, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0},
1358 {TEGRA124_CLK_VDE, TEGRA124_CLK_PLL_P, 0, 0},
1359 {TEGRA124_CLK_HOST1X, TEGRA124_CLK_PLL_P, 136000000, 1},
1360 {TEGRA124_CLK_SCLK, TEGRA124_CLK_PLL_P_OUT2, 102000000, 1},
1361 {TEGRA124_CLK_DFLL_SOC, TEGRA124_CLK_PLL_P, 51000000, 1},
1362 {TEGRA124_CLK_DFLL_REF, TEGRA124_CLK_PLL_P, 51000000, 1},
1363 {TEGRA124_CLK_PLL_C, TEGRA124_CLK_CLK_MAX, 768000000, 0},
1364 {TEGRA124_CLK_PLL_C_OUT1, TEGRA124_CLK_CLK_MAX, 100000000, 0},
1365 {TEGRA124_CLK_SBC4, TEGRA124_CLK_PLL_P, 12000000, 1},
1366 {TEGRA124_CLK_TSEC, TEGRA124_CLK_PLL_C3, 0, 0},
1367 {TEGRA124_CLK_MSENC, TEGRA124_CLK_PLL_C3, 0, 0},
1368 /* This MUST be the last entry. */
1369 {TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0},
1370};
1371
1372static void __init tegra124_clock_apply_init_table(void)
1373{
1374 tegra_init_from_table(init_table, clks, TEGRA124_CLK_CLK_MAX);
1375}
1376
1377static void __init tegra124_clock_init(struct device_node *np)
1378{
1379 struct device_node *node;
1380
1381 clk_base = of_iomap(np, 0);
1382 if (!clk_base) {
1383 pr_err("ioremap tegra124 CAR failed\n");
1384 return;
1385 }
1386
1387 node = of_find_matching_node(NULL, pmc_match);
1388 if (!node) {
1389 pr_err("Failed to find pmc node\n");
1390 WARN_ON(1);
1391 return;
1392 }
1393
1394 pmc_base = of_iomap(node, 0);
1395 if (!pmc_base) {
1396 pr_err("Can't map pmc registers\n");
1397 WARN_ON(1);
1398 return;
1399 }
1400
1401 clks = tegra_clk_init(clk_base, TEGRA124_CLK_CLK_MAX, 6);
1402 if (!clks)
1403 return;
1404
1405 if (tegra_osc_clk_init(clk_base, tegra124_clks, tegra124_input_freq,
1406 ARRAY_SIZE(tegra124_input_freq), &osc_freq, &pll_ref_freq) < 0)
1407 return;
1408
1409 tegra_fixed_clk_init(tegra124_clks);
1410 tegra124_pll_init(clk_base, pmc_base);
1411 tegra124_periph_clk_init(clk_base, pmc_base);
1412 tegra_audio_clk_init(clk_base, pmc_base, tegra124_clks, &pll_a_params);
1413 tegra_pmc_clk_init(pmc_base, tegra124_clks);
1414
1415 tegra_super_clk_gen4_init(clk_base, pmc_base, tegra124_clks,
1416 &pll_x_params);
1417 tegra_add_of_provider(np);
1418 tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
1419
1420 tegra_clk_apply_init_table = tegra124_clock_apply_init_table;
1421
1422 tegra_cpu_car_ops = &tegra124_cpu_car_ops;
1423}
1424CLK_OF_DECLARE(tegra124, "nvidia,tegra124-car", tegra124_clock_init);
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 056f649d0d89..dbace152b2fa 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -22,30 +22,10 @@
22#include <linux/of_address.h> 22#include <linux/of_address.h>
23#include <linux/clk/tegra.h> 23#include <linux/clk/tegra.h>
24#include <linux/delay.h> 24#include <linux/delay.h>
25#include <dt-bindings/clock/tegra20-car.h>
25 26
26#include "clk.h" 27#include "clk.h"
27 28#include "clk-id.h"
28#define RST_DEVICES_L 0x004
29#define RST_DEVICES_H 0x008
30#define RST_DEVICES_U 0x00c
31#define RST_DEVICES_SET_L 0x300
32#define RST_DEVICES_CLR_L 0x304
33#define RST_DEVICES_SET_H 0x308
34#define RST_DEVICES_CLR_H 0x30c
35#define RST_DEVICES_SET_U 0x310
36#define RST_DEVICES_CLR_U 0x314
37#define RST_DEVICES_NUM 3
38
39#define CLK_OUT_ENB_L 0x010
40#define CLK_OUT_ENB_H 0x014
41#define CLK_OUT_ENB_U 0x018
42#define CLK_OUT_ENB_SET_L 0x320
43#define CLK_OUT_ENB_CLR_L 0x324
44#define CLK_OUT_ENB_SET_H 0x328
45#define CLK_OUT_ENB_CLR_H 0x32c
46#define CLK_OUT_ENB_SET_U 0x330
47#define CLK_OUT_ENB_CLR_U 0x334
48#define CLK_OUT_ENB_NUM 3
49 29
50#define OSC_CTRL 0x50 30#define OSC_CTRL 0x50
51#define OSC_CTRL_OSC_FREQ_MASK (3<<30) 31#define OSC_CTRL_OSC_FREQ_MASK (3<<30)
@@ -67,6 +47,8 @@
67#define OSC_FREQ_DET_BUSY (1<<31) 47#define OSC_FREQ_DET_BUSY (1<<31)
68#define OSC_FREQ_DET_CNT_MASK 0xFFFF 48#define OSC_FREQ_DET_CNT_MASK 0xFFFF
69 49
50#define TEGRA20_CLK_PERIPH_BANKS 3
51
70#define PLLS_BASE 0xf0 52#define PLLS_BASE 0xf0
71#define PLLS_MISC 0xf4 53#define PLLS_MISC 0xf4
72#define PLLC_BASE 0x80 54#define PLLC_BASE 0x80
@@ -114,34 +96,15 @@
114 96
115#define CLK_SOURCE_I2S1 0x100 97#define CLK_SOURCE_I2S1 0x100
116#define CLK_SOURCE_I2S2 0x104 98#define CLK_SOURCE_I2S2 0x104
117#define CLK_SOURCE_SPDIF_OUT 0x108
118#define CLK_SOURCE_SPDIF_IN 0x10c
119#define CLK_SOURCE_PWM 0x110 99#define CLK_SOURCE_PWM 0x110
120#define CLK_SOURCE_SPI 0x114 100#define CLK_SOURCE_SPI 0x114
121#define CLK_SOURCE_SBC1 0x134
122#define CLK_SOURCE_SBC2 0x118
123#define CLK_SOURCE_SBC3 0x11c
124#define CLK_SOURCE_SBC4 0x1b4
125#define CLK_SOURCE_XIO 0x120 101#define CLK_SOURCE_XIO 0x120
126#define CLK_SOURCE_TWC 0x12c 102#define CLK_SOURCE_TWC 0x12c
127#define CLK_SOURCE_IDE 0x144 103#define CLK_SOURCE_IDE 0x144
128#define CLK_SOURCE_NDFLASH 0x160
129#define CLK_SOURCE_VFIR 0x168
130#define CLK_SOURCE_SDMMC1 0x150
131#define CLK_SOURCE_SDMMC2 0x154
132#define CLK_SOURCE_SDMMC3 0x1bc
133#define CLK_SOURCE_SDMMC4 0x164
134#define CLK_SOURCE_CVE 0x140
135#define CLK_SOURCE_TVO 0x188
136#define CLK_SOURCE_TVDAC 0x194
137#define CLK_SOURCE_HDMI 0x18c 104#define CLK_SOURCE_HDMI 0x18c
138#define CLK_SOURCE_DISP1 0x138 105#define CLK_SOURCE_DISP1 0x138
139#define CLK_SOURCE_DISP2 0x13c 106#define CLK_SOURCE_DISP2 0x13c
140#define CLK_SOURCE_CSITE 0x1d4 107#define CLK_SOURCE_CSITE 0x1d4
141#define CLK_SOURCE_LA 0x1f8
142#define CLK_SOURCE_OWR 0x1cc
143#define CLK_SOURCE_NOR 0x1d0
144#define CLK_SOURCE_MIPI 0x174
145#define CLK_SOURCE_I2C1 0x124 108#define CLK_SOURCE_I2C1 0x124
146#define CLK_SOURCE_I2C2 0x198 109#define CLK_SOURCE_I2C2 0x198
147#define CLK_SOURCE_I2C3 0x1b8 110#define CLK_SOURCE_I2C3 0x1b8
@@ -151,24 +114,10 @@
151#define CLK_SOURCE_UARTC 0x1a0 114#define CLK_SOURCE_UARTC 0x1a0
152#define CLK_SOURCE_UARTD 0x1c0 115#define CLK_SOURCE_UARTD 0x1c0
153#define CLK_SOURCE_UARTE 0x1c4 116#define CLK_SOURCE_UARTE 0x1c4
154#define CLK_SOURCE_3D 0x158
155#define CLK_SOURCE_2D 0x15c
156#define CLK_SOURCE_MPE 0x170
157#define CLK_SOURCE_EPP 0x16c
158#define CLK_SOURCE_HOST1X 0x180
159#define CLK_SOURCE_VDE 0x1c8
160#define CLK_SOURCE_VI 0x148
161#define CLK_SOURCE_VI_SENSOR 0x1a8
162#define CLK_SOURCE_EMC 0x19c 117#define CLK_SOURCE_EMC 0x19c
163 118
164#define AUDIO_SYNC_CLK 0x38 119#define AUDIO_SYNC_CLK 0x38
165 120
166#define PMC_CTRL 0x0
167#define PMC_CTRL_BLINK_ENB 7
168#define PMC_DPD_PADS_ORIDE 0x1c
169#define PMC_DPD_PADS_ORIDE_BLINK_ENB 20
170#define PMC_BLINK_TIMER 0x40
171
172/* Tegra CPU clock and reset control regs */ 121/* Tegra CPU clock and reset control regs */
173#define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c 122#define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c
174#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340 123#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340
@@ -188,64 +137,32 @@ static struct cpu_clk_suspend_context {
188} tegra20_cpu_clk_sctx; 137} tegra20_cpu_clk_sctx;
189#endif 138#endif
190 139
191static int periph_clk_enb_refcnt[CLK_OUT_ENB_NUM * 32];
192
193static void __iomem *clk_base; 140static void __iomem *clk_base;
194static void __iomem *pmc_base; 141static void __iomem *pmc_base;
195 142
196static DEFINE_SPINLOCK(pll_div_lock); 143#define TEGRA_INIT_DATA_MUX(_name, _parents, _offset, \
197static DEFINE_SPINLOCK(sysrate_lock); 144 _clk_num, _gate_flags, _clk_id) \
198 145 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
199#define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset, \
200 _clk_num, _regs, _gate_flags, _clk_id) \
201 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
202 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \ 146 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
203 _regs, _clk_num, periph_clk_enb_refcnt, \ 147 _clk_num, \
204 _gate_flags, _clk_id) 148 _gate_flags, _clk_id)
205 149
206#define TEGRA_INIT_DATA_INT(_name, _con_id, _dev_id, _parents, _offset, \ 150#define TEGRA_INIT_DATA_DIV16(_name, _parents, _offset, \
207 _clk_num, _regs, _gate_flags, _clk_id) \ 151 _clk_num, _gate_flags, _clk_id) \
208 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 152 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
209 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs, \ 153 30, 2, 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP, \
210 _clk_num, periph_clk_enb_refcnt, _gate_flags, \ 154 _clk_num, _gate_flags, \
211 _clk_id)
212
213#define TEGRA_INIT_DATA_DIV16(_name, _con_id, _dev_id, _parents, _offset, \
214 _clk_num, _regs, _gate_flags, _clk_id) \
215 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
216 30, 2, 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP, _regs, \
217 _clk_num, periph_clk_enb_refcnt, _gate_flags, \
218 _clk_id) 155 _clk_id)
219 156
220#define TEGRA_INIT_DATA_NODIV(_name, _con_id, _dev_id, _parents, _offset, \ 157#define TEGRA_INIT_DATA_NODIV(_name, _parents, _offset, \
221 _mux_shift, _mux_width, _clk_num, _regs, \ 158 _mux_shift, _mux_width, _clk_num, \
222 _gate_flags, _clk_id) \ 159 _gate_flags, _clk_id) \
223 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 160 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
224 _mux_shift, _mux_width, 0, 0, 0, 0, 0, _regs, \ 161 _mux_shift, _mux_width, 0, 0, 0, 0, 0, \
225 _clk_num, periph_clk_enb_refcnt, _gate_flags, \ 162 _clk_num, _gate_flags, \
226 _clk_id) 163 _clk_id)
227 164
228/* IDs assigned here must be in sync with DT bindings definition 165static struct clk **clks;
229 * for Tegra20 clocks .
230 */
231enum tegra20_clk {
232 cpu, ac97 = 3, rtc, timer, uarta, gpio = 8, sdmmc2, i2s1 = 11, i2c1,
233 ndflash, sdmmc1, sdmmc4, twc, pwm, i2s2, epp, gr2d = 21, usbd, isp,
234 gr3d, ide, disp2, disp1, host1x, vcp, cache2 = 31, mem, ahbdma, apbdma,
235 kbc = 36, stat_mon, pmc, fuse, kfuse, sbc1, nor, spi, sbc2, xio, sbc3,
236 dvc, dsi, mipi = 50, hdmi, csi, tvdac, i2c2, uartc, emc = 57, usb2,
237 usb3, mpe, vde, bsea, bsev, speedo, uartd, uarte, i2c3, sbc4, sdmmc3,
238 pex, owr, afi, csite, pcie_xclk, avpucq = 75, la, irama = 84, iramb,
239 iramc, iramd, cram2, audio_2x, clk_d, csus = 92, cdev2, cdev1,
240 uartb = 96, vfir, spdif_in, spdif_out, vi, vi_sensor, tvo, cve,
241 osc, clk_32k, clk_m, sclk, cclk, hclk, pclk, blink, pll_a, pll_a_out0,
242 pll_c, pll_c_out1, pll_d, pll_d_out0, pll_e, pll_m, pll_m_out1,
243 pll_p, pll_p_out1, pll_p_out2, pll_p_out3, pll_p_out4, pll_s, pll_u,
244 pll_x, cop, audio, pll_ref, twd, clk_max,
245};
246
247static struct clk *clks[clk_max];
248static struct clk_onecell_data clk_data;
249 166
250static struct tegra_clk_pll_freq_table pll_c_freq_table[] = { 167static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
251 { 12000000, 600000000, 600, 12, 0, 8 }, 168 { 12000000, 600000000, 600, 12, 0, 8 },
@@ -383,6 +300,8 @@ static struct tegra_clk_pll_params pll_c_params = {
383 .lock_mask = PLL_BASE_LOCK, 300 .lock_mask = PLL_BASE_LOCK,
384 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 301 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
385 .lock_delay = 300, 302 .lock_delay = 300,
303 .freq_table = pll_c_freq_table,
304 .flags = TEGRA_PLL_HAS_CPCON,
386}; 305};
387 306
388static struct tegra_clk_pll_params pll_m_params = { 307static struct tegra_clk_pll_params pll_m_params = {
@@ -397,6 +316,8 @@ static struct tegra_clk_pll_params pll_m_params = {
397 .lock_mask = PLL_BASE_LOCK, 316 .lock_mask = PLL_BASE_LOCK,
398 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 317 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
399 .lock_delay = 300, 318 .lock_delay = 300,
319 .freq_table = pll_m_freq_table,
320 .flags = TEGRA_PLL_HAS_CPCON,
400}; 321};
401 322
402static struct tegra_clk_pll_params pll_p_params = { 323static struct tegra_clk_pll_params pll_p_params = {
@@ -411,6 +332,9 @@ static struct tegra_clk_pll_params pll_p_params = {
411 .lock_mask = PLL_BASE_LOCK, 332 .lock_mask = PLL_BASE_LOCK,
412 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 333 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
413 .lock_delay = 300, 334 .lock_delay = 300,
335 .freq_table = pll_p_freq_table,
336 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_CPCON,
337 .fixed_rate = 216000000,
414}; 338};
415 339
416static struct tegra_clk_pll_params pll_a_params = { 340static struct tegra_clk_pll_params pll_a_params = {
@@ -425,6 +349,8 @@ static struct tegra_clk_pll_params pll_a_params = {
425 .lock_mask = PLL_BASE_LOCK, 349 .lock_mask = PLL_BASE_LOCK,
426 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 350 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
427 .lock_delay = 300, 351 .lock_delay = 300,
352 .freq_table = pll_a_freq_table,
353 .flags = TEGRA_PLL_HAS_CPCON,
428}; 354};
429 355
430static struct tegra_clk_pll_params pll_d_params = { 356static struct tegra_clk_pll_params pll_d_params = {
@@ -439,6 +365,8 @@ static struct tegra_clk_pll_params pll_d_params = {
439 .lock_mask = PLL_BASE_LOCK, 365 .lock_mask = PLL_BASE_LOCK,
440 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 366 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
441 .lock_delay = 1000, 367 .lock_delay = 1000,
368 .freq_table = pll_d_freq_table,
369 .flags = TEGRA_PLL_HAS_CPCON,
442}; 370};
443 371
444static struct pdiv_map pllu_p[] = { 372static struct pdiv_map pllu_p[] = {
@@ -460,6 +388,8 @@ static struct tegra_clk_pll_params pll_u_params = {
460 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 388 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
461 .lock_delay = 1000, 389 .lock_delay = 1000,
462 .pdiv_tohw = pllu_p, 390 .pdiv_tohw = pllu_p,
391 .freq_table = pll_u_freq_table,
392 .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON,
463}; 393};
464 394
465static struct tegra_clk_pll_params pll_x_params = { 395static struct tegra_clk_pll_params pll_x_params = {
@@ -474,6 +404,8 @@ static struct tegra_clk_pll_params pll_x_params = {
474 .lock_mask = PLL_BASE_LOCK, 404 .lock_mask = PLL_BASE_LOCK,
475 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 405 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
476 .lock_delay = 300, 406 .lock_delay = 300,
407 .freq_table = pll_x_freq_table,
408 .flags = TEGRA_PLL_HAS_CPCON,
477}; 409};
478 410
479static struct tegra_clk_pll_params pll_e_params = { 411static struct tegra_clk_pll_params pll_e_params = {
@@ -488,34 +420,160 @@ static struct tegra_clk_pll_params pll_e_params = {
488 .lock_mask = PLLE_MISC_LOCK, 420 .lock_mask = PLLE_MISC_LOCK,
489 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE, 421 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
490 .lock_delay = 0, 422 .lock_delay = 0,
423 .freq_table = pll_e_freq_table,
424 .flags = TEGRA_PLL_FIXED,
425 .fixed_rate = 100000000,
491}; 426};
492 427
493/* Peripheral clock registers */ 428static struct tegra_devclk devclks[] __initdata = {
494static struct tegra_clk_periph_regs periph_l_regs = { 429 { .con_id = "pll_c", .dt_id = TEGRA20_CLK_PLL_C },
495 .enb_reg = CLK_OUT_ENB_L, 430 { .con_id = "pll_c_out1", .dt_id = TEGRA20_CLK_PLL_C_OUT1 },
496 .enb_set_reg = CLK_OUT_ENB_SET_L, 431 { .con_id = "pll_p", .dt_id = TEGRA20_CLK_PLL_P },
497 .enb_clr_reg = CLK_OUT_ENB_CLR_L, 432 { .con_id = "pll_p_out1", .dt_id = TEGRA20_CLK_PLL_P_OUT1 },
498 .rst_reg = RST_DEVICES_L, 433 { .con_id = "pll_p_out2", .dt_id = TEGRA20_CLK_PLL_P_OUT2 },
499 .rst_set_reg = RST_DEVICES_SET_L, 434 { .con_id = "pll_p_out3", .dt_id = TEGRA20_CLK_PLL_P_OUT3 },
500 .rst_clr_reg = RST_DEVICES_CLR_L, 435 { .con_id = "pll_p_out4", .dt_id = TEGRA20_CLK_PLL_P_OUT4 },
501}; 436 { .con_id = "pll_m", .dt_id = TEGRA20_CLK_PLL_M },
502 437 { .con_id = "pll_m_out1", .dt_id = TEGRA20_CLK_PLL_M_OUT1 },
503static struct tegra_clk_periph_regs periph_h_regs = { 438 { .con_id = "pll_x", .dt_id = TEGRA20_CLK_PLL_X },
504 .enb_reg = CLK_OUT_ENB_H, 439 { .con_id = "pll_u", .dt_id = TEGRA20_CLK_PLL_U },
505 .enb_set_reg = CLK_OUT_ENB_SET_H, 440 { .con_id = "pll_d", .dt_id = TEGRA20_CLK_PLL_D },
506 .enb_clr_reg = CLK_OUT_ENB_CLR_H, 441 { .con_id = "pll_d_out0", .dt_id = TEGRA20_CLK_PLL_D_OUT0 },
507 .rst_reg = RST_DEVICES_H, 442 { .con_id = "pll_a", .dt_id = TEGRA20_CLK_PLL_A },
508 .rst_set_reg = RST_DEVICES_SET_H, 443 { .con_id = "pll_a_out0", .dt_id = TEGRA20_CLK_PLL_A_OUT0 },
509 .rst_clr_reg = RST_DEVICES_CLR_H, 444 { .con_id = "pll_e", .dt_id = TEGRA20_CLK_PLL_E },
445 { .con_id = "cclk", .dt_id = TEGRA20_CLK_CCLK },
446 { .con_id = "sclk", .dt_id = TEGRA20_CLK_SCLK },
447 { .con_id = "hclk", .dt_id = TEGRA20_CLK_HCLK },
448 { .con_id = "pclk", .dt_id = TEGRA20_CLK_PCLK },
449 { .con_id = "fuse", .dt_id = TEGRA20_CLK_FUSE },
450 { .con_id = "twd", .dt_id = TEGRA20_CLK_TWD },
451 { .con_id = "audio", .dt_id = TEGRA20_CLK_AUDIO },
452 { .con_id = "audio_2x", .dt_id = TEGRA20_CLK_AUDIO_2X },
453 { .dev_id = "tegra20-ac97", .dt_id = TEGRA20_CLK_AC97 },
454 { .dev_id = "tegra-apbdma", .dt_id = TEGRA20_CLK_APBDMA },
455 { .dev_id = "rtc-tegra", .dt_id = TEGRA20_CLK_RTC },
456 { .dev_id = "timer", .dt_id = TEGRA20_CLK_TIMER },
457 { .dev_id = "tegra-kbc", .dt_id = TEGRA20_CLK_KBC },
458 { .con_id = "csus", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_CSUS },
459 { .con_id = "vcp", .dev_id = "tegra-avp", .dt_id = TEGRA20_CLK_VCP },
460 { .con_id = "bsea", .dev_id = "tegra-avp", .dt_id = TEGRA20_CLK_BSEA },
461 { .con_id = "bsev", .dev_id = "tegra-aes", .dt_id = TEGRA20_CLK_BSEV },
462 { .con_id = "emc", .dt_id = TEGRA20_CLK_EMC },
463 { .dev_id = "fsl-tegra-udc", .dt_id = TEGRA20_CLK_USBD },
464 { .dev_id = "tegra-ehci.1", .dt_id = TEGRA20_CLK_USB2 },
465 { .dev_id = "tegra-ehci.2", .dt_id = TEGRA20_CLK_USB3 },
466 { .dev_id = "dsi", .dt_id = TEGRA20_CLK_DSI },
467 { .con_id = "csi", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_CSI },
468 { .con_id = "isp", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_ISP },
469 { .con_id = "pex", .dt_id = TEGRA20_CLK_PEX },
470 { .con_id = "afi", .dt_id = TEGRA20_CLK_AFI },
471 { .con_id = "cdev1", .dt_id = TEGRA20_CLK_CDEV1 },
472 { .con_id = "cdev2", .dt_id = TEGRA20_CLK_CDEV2 },
473 { .con_id = "clk_32k", .dt_id = TEGRA20_CLK_CLK_32K },
474 { .con_id = "blink", .dt_id = TEGRA20_CLK_BLINK },
475 { .con_id = "clk_m", .dt_id = TEGRA20_CLK_CLK_M },
476 { .con_id = "pll_ref", .dt_id = TEGRA20_CLK_PLL_REF },
477 { .dev_id = "tegra20-i2s.0", .dt_id = TEGRA20_CLK_I2S1 },
478 { .dev_id = "tegra20-i2s.1", .dt_id = TEGRA20_CLK_I2S2 },
479 { .con_id = "spdif_out", .dev_id = "tegra20-spdif", .dt_id = TEGRA20_CLK_SPDIF_OUT },
480 { .con_id = "spdif_in", .dev_id = "tegra20-spdif", .dt_id = TEGRA20_CLK_SPDIF_IN },
481 { .dev_id = "spi_tegra.0", .dt_id = TEGRA20_CLK_SBC1 },
482 { .dev_id = "spi_tegra.1", .dt_id = TEGRA20_CLK_SBC2 },
483 { .dev_id = "spi_tegra.2", .dt_id = TEGRA20_CLK_SBC3 },
484 { .dev_id = "spi_tegra.3", .dt_id = TEGRA20_CLK_SBC4 },
485 { .dev_id = "spi", .dt_id = TEGRA20_CLK_SPI },
486 { .dev_id = "xio", .dt_id = TEGRA20_CLK_XIO },
487 { .dev_id = "twc", .dt_id = TEGRA20_CLK_TWC },
488 { .dev_id = "ide", .dt_id = TEGRA20_CLK_IDE },
489 { .dev_id = "tegra_nand", .dt_id = TEGRA20_CLK_NDFLASH },
490 { .dev_id = "vfir", .dt_id = TEGRA20_CLK_VFIR },
491 { .dev_id = "csite", .dt_id = TEGRA20_CLK_CSITE },
492 { .dev_id = "la", .dt_id = TEGRA20_CLK_LA },
493 { .dev_id = "tegra_w1", .dt_id = TEGRA20_CLK_OWR },
494 { .dev_id = "mipi", .dt_id = TEGRA20_CLK_MIPI },
495 { .dev_id = "vde", .dt_id = TEGRA20_CLK_VDE },
496 { .con_id = "vi", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_VI },
497 { .dev_id = "epp", .dt_id = TEGRA20_CLK_EPP },
498 { .dev_id = "mpe", .dt_id = TEGRA20_CLK_MPE },
499 { .dev_id = "host1x", .dt_id = TEGRA20_CLK_HOST1X },
500 { .dev_id = "3d", .dt_id = TEGRA20_CLK_GR3D },
501 { .dev_id = "2d", .dt_id = TEGRA20_CLK_GR2D },
502 { .dev_id = "tegra-nor", .dt_id = TEGRA20_CLK_NOR },
503 { .dev_id = "sdhci-tegra.0", .dt_id = TEGRA20_CLK_SDMMC1 },
504 { .dev_id = "sdhci-tegra.1", .dt_id = TEGRA20_CLK_SDMMC2 },
505 { .dev_id = "sdhci-tegra.2", .dt_id = TEGRA20_CLK_SDMMC3 },
506 { .dev_id = "sdhci-tegra.3", .dt_id = TEGRA20_CLK_SDMMC4 },
507 { .dev_id = "cve", .dt_id = TEGRA20_CLK_CVE },
508 { .dev_id = "tvo", .dt_id = TEGRA20_CLK_TVO },
509 { .dev_id = "tvdac", .dt_id = TEGRA20_CLK_TVDAC },
510 { .con_id = "vi_sensor", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_VI_SENSOR },
511 { .dev_id = "hdmi", .dt_id = TEGRA20_CLK_HDMI },
512 { .con_id = "div-clk", .dev_id = "tegra-i2c.0", .dt_id = TEGRA20_CLK_I2C1 },
513 { .con_id = "div-clk", .dev_id = "tegra-i2c.1", .dt_id = TEGRA20_CLK_I2C2 },
514 { .con_id = "div-clk", .dev_id = "tegra-i2c.2", .dt_id = TEGRA20_CLK_I2C3 },
515 { .con_id = "div-clk", .dev_id = "tegra-i2c.3", .dt_id = TEGRA20_CLK_DVC },
516 { .dev_id = "tegra-pwm", .dt_id = TEGRA20_CLK_PWM },
517 { .dev_id = "tegra_uart.0", .dt_id = TEGRA20_CLK_UARTA },
518 { .dev_id = "tegra_uart.1", .dt_id = TEGRA20_CLK_UARTB },
519 { .dev_id = "tegra_uart.2", .dt_id = TEGRA20_CLK_UARTC },
520 { .dev_id = "tegra_uart.3", .dt_id = TEGRA20_CLK_UARTD },
521 { .dev_id = "tegra_uart.4", .dt_id = TEGRA20_CLK_UARTE },
522 { .dev_id = "tegradc.0", .dt_id = TEGRA20_CLK_DISP1 },
523 { .dev_id = "tegradc.1", .dt_id = TEGRA20_CLK_DISP2 },
510}; 524};
511 525
512static struct tegra_clk_periph_regs periph_u_regs = { 526static struct tegra_clk tegra20_clks[tegra_clk_max] __initdata = {
513 .enb_reg = CLK_OUT_ENB_U, 527 [tegra_clk_spdif_out] = { .dt_id = TEGRA20_CLK_SPDIF_OUT, .present = true },
514 .enb_set_reg = CLK_OUT_ENB_SET_U, 528 [tegra_clk_spdif_in] = { .dt_id = TEGRA20_CLK_SPDIF_IN, .present = true },
515 .enb_clr_reg = CLK_OUT_ENB_CLR_U, 529 [tegra_clk_sdmmc1] = { .dt_id = TEGRA20_CLK_SDMMC1, .present = true },
516 .rst_reg = RST_DEVICES_U, 530 [tegra_clk_sdmmc2] = { .dt_id = TEGRA20_CLK_SDMMC2, .present = true },
517 .rst_set_reg = RST_DEVICES_SET_U, 531 [tegra_clk_sdmmc3] = { .dt_id = TEGRA20_CLK_SDMMC3, .present = true },
518 .rst_clr_reg = RST_DEVICES_CLR_U, 532 [tegra_clk_sdmmc4] = { .dt_id = TEGRA20_CLK_SDMMC4, .present = true },
533 [tegra_clk_la] = { .dt_id = TEGRA20_CLK_LA, .present = true },
534 [tegra_clk_csite] = { .dt_id = TEGRA20_CLK_CSITE, .present = true },
535 [tegra_clk_vfir] = { .dt_id = TEGRA20_CLK_VFIR, .present = true },
536 [tegra_clk_mipi] = { .dt_id = TEGRA20_CLK_MIPI, .present = true },
537 [tegra_clk_nor] = { .dt_id = TEGRA20_CLK_NOR, .present = true },
538 [tegra_clk_rtc] = { .dt_id = TEGRA20_CLK_RTC, .present = true },
539 [tegra_clk_timer] = { .dt_id = TEGRA20_CLK_TIMER, .present = true },
540 [tegra_clk_kbc] = { .dt_id = TEGRA20_CLK_KBC, .present = true },
541 [tegra_clk_csus] = { .dt_id = TEGRA20_CLK_CSUS, .present = true },
542 [tegra_clk_vcp] = { .dt_id = TEGRA20_CLK_VCP, .present = true },
543 [tegra_clk_bsea] = { .dt_id = TEGRA20_CLK_BSEA, .present = true },
544 [tegra_clk_bsev] = { .dt_id = TEGRA20_CLK_BSEV, .present = true },
545 [tegra_clk_usbd] = { .dt_id = TEGRA20_CLK_USBD, .present = true },
546 [tegra_clk_usb2] = { .dt_id = TEGRA20_CLK_USB2, .present = true },
547 [tegra_clk_usb3] = { .dt_id = TEGRA20_CLK_USB3, .present = true },
548 [tegra_clk_csi] = { .dt_id = TEGRA20_CLK_CSI, .present = true },
549 [tegra_clk_isp] = { .dt_id = TEGRA20_CLK_ISP, .present = true },
550 [tegra_clk_clk_32k] = { .dt_id = TEGRA20_CLK_CLK_32K, .present = true },
551 [tegra_clk_blink] = { .dt_id = TEGRA20_CLK_BLINK, .present = true },
552 [tegra_clk_hclk] = { .dt_id = TEGRA20_CLK_HCLK, .present = true },
553 [tegra_clk_pclk] = { .dt_id = TEGRA20_CLK_PCLK, .present = true },
554 [tegra_clk_pll_p_out1] = { .dt_id = TEGRA20_CLK_PLL_P_OUT1, .present = true },
555 [tegra_clk_pll_p_out2] = { .dt_id = TEGRA20_CLK_PLL_P_OUT2, .present = true },
556 [tegra_clk_pll_p_out3] = { .dt_id = TEGRA20_CLK_PLL_P_OUT3, .present = true },
557 [tegra_clk_pll_p_out4] = { .dt_id = TEGRA20_CLK_PLL_P_OUT4, .present = true },
558 [tegra_clk_pll_p] = { .dt_id = TEGRA20_CLK_PLL_P, .present = true },
559 [tegra_clk_owr] = { .dt_id = TEGRA20_CLK_OWR, .present = true },
560 [tegra_clk_sbc1] = { .dt_id = TEGRA20_CLK_SBC1, .present = true },
561 [tegra_clk_sbc2] = { .dt_id = TEGRA20_CLK_SBC2, .present = true },
562 [tegra_clk_sbc3] = { .dt_id = TEGRA20_CLK_SBC3, .present = true },
563 [tegra_clk_sbc4] = { .dt_id = TEGRA20_CLK_SBC4, .present = true },
564 [tegra_clk_vde] = { .dt_id = TEGRA20_CLK_VDE, .present = true },
565 [tegra_clk_vi] = { .dt_id = TEGRA20_CLK_VI, .present = true },
566 [tegra_clk_epp] = { .dt_id = TEGRA20_CLK_EPP, .present = true },
567 [tegra_clk_mpe] = { .dt_id = TEGRA20_CLK_MPE, .present = true },
568 [tegra_clk_host1x] = { .dt_id = TEGRA20_CLK_HOST1X, .present = true },
569 [tegra_clk_gr2d] = { .dt_id = TEGRA20_CLK_GR2D, .present = true },
570 [tegra_clk_gr3d] = { .dt_id = TEGRA20_CLK_GR3D, .present = true },
571 [tegra_clk_ndflash] = { .dt_id = TEGRA20_CLK_NDFLASH, .present = true },
572 [tegra_clk_cve] = { .dt_id = TEGRA20_CLK_CVE, .present = true },
573 [tegra_clk_tvo] = { .dt_id = TEGRA20_CLK_TVO, .present = true },
574 [tegra_clk_tvdac] = { .dt_id = TEGRA20_CLK_TVDAC, .present = true },
575 [tegra_clk_vi_sensor] = { .dt_id = TEGRA20_CLK_VI_SENSOR, .present = true },
576 [tegra_clk_afi] = { .dt_id = TEGRA20_CLK_AFI, .present = true },
519}; 577};
520 578
521static unsigned long tegra20_clk_measure_input_freq(void) 579static unsigned long tegra20_clk_measure_input_freq(void)
@@ -577,10 +635,8 @@ static void tegra20_pll_init(void)
577 635
578 /* PLLC */ 636 /* PLLC */
579 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, NULL, 0, 637 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, NULL, 0,
580 0, &pll_c_params, TEGRA_PLL_HAS_CPCON, 638 &pll_c_params, NULL);
581 pll_c_freq_table, NULL); 639 clks[TEGRA20_CLK_PLL_C] = clk;
582 clk_register_clkdev(clk, "pll_c", NULL);
583 clks[pll_c] = clk;
584 640
585 /* PLLC_OUT1 */ 641 /* PLLC_OUT1 */
586 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c", 642 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
@@ -589,71 +645,13 @@ static void tegra20_pll_init(void)
589 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div", 645 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
590 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT, 646 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT,
591 0, NULL); 647 0, NULL);
592 clk_register_clkdev(clk, "pll_c_out1", NULL); 648 clks[TEGRA20_CLK_PLL_C_OUT1] = clk;
593 clks[pll_c_out1] = clk;
594
595 /* PLLP */
596 clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base, NULL, 0,
597 216000000, &pll_p_params, TEGRA_PLL_FIXED |
598 TEGRA_PLL_HAS_CPCON, pll_p_freq_table, NULL);
599 clk_register_clkdev(clk, "pll_p", NULL);
600 clks[pll_p] = clk;
601
602 /* PLLP_OUT1 */
603 clk = tegra_clk_register_divider("pll_p_out1_div", "pll_p",
604 clk_base + PLLP_OUTA, 0,
605 TEGRA_DIVIDER_FIXED | TEGRA_DIVIDER_ROUND_UP,
606 8, 8, 1, &pll_div_lock);
607 clk = tegra_clk_register_pll_out("pll_p_out1", "pll_p_out1_div",
608 clk_base + PLLP_OUTA, 1, 0,
609 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
610 &pll_div_lock);
611 clk_register_clkdev(clk, "pll_p_out1", NULL);
612 clks[pll_p_out1] = clk;
613
614 /* PLLP_OUT2 */
615 clk = tegra_clk_register_divider("pll_p_out2_div", "pll_p",
616 clk_base + PLLP_OUTA, 0,
617 TEGRA_DIVIDER_FIXED | TEGRA_DIVIDER_ROUND_UP,
618 24, 8, 1, &pll_div_lock);
619 clk = tegra_clk_register_pll_out("pll_p_out2", "pll_p_out2_div",
620 clk_base + PLLP_OUTA, 17, 16,
621 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
622 &pll_div_lock);
623 clk_register_clkdev(clk, "pll_p_out2", NULL);
624 clks[pll_p_out2] = clk;
625
626 /* PLLP_OUT3 */
627 clk = tegra_clk_register_divider("pll_p_out3_div", "pll_p",
628 clk_base + PLLP_OUTB, 0,
629 TEGRA_DIVIDER_FIXED | TEGRA_DIVIDER_ROUND_UP,
630 8, 8, 1, &pll_div_lock);
631 clk = tegra_clk_register_pll_out("pll_p_out3", "pll_p_out3_div",
632 clk_base + PLLP_OUTB, 1, 0,
633 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
634 &pll_div_lock);
635 clk_register_clkdev(clk, "pll_p_out3", NULL);
636 clks[pll_p_out3] = clk;
637
638 /* PLLP_OUT4 */
639 clk = tegra_clk_register_divider("pll_p_out4_div", "pll_p",
640 clk_base + PLLP_OUTB, 0,
641 TEGRA_DIVIDER_FIXED | TEGRA_DIVIDER_ROUND_UP,
642 24, 8, 1, &pll_div_lock);
643 clk = tegra_clk_register_pll_out("pll_p_out4", "pll_p_out4_div",
644 clk_base + PLLP_OUTB, 17, 16,
645 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
646 &pll_div_lock);
647 clk_register_clkdev(clk, "pll_p_out4", NULL);
648 clks[pll_p_out4] = clk;
649 649
650 /* PLLM */ 650 /* PLLM */
651 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, NULL, 651 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, NULL,
652 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE, 0, 652 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
653 &pll_m_params, TEGRA_PLL_HAS_CPCON, 653 &pll_m_params, NULL);
654 pll_m_freq_table, NULL); 654 clks[TEGRA20_CLK_PLL_M] = clk;
655 clk_register_clkdev(clk, "pll_m", NULL);
656 clks[pll_m] = clk;
657 655
658 /* PLLM_OUT1 */ 656 /* PLLM_OUT1 */
659 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m", 657 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
@@ -662,42 +660,32 @@ static void tegra20_pll_init(void)
662 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div", 660 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
663 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED | 661 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |
664 CLK_SET_RATE_PARENT, 0, NULL); 662 CLK_SET_RATE_PARENT, 0, NULL);
665 clk_register_clkdev(clk, "pll_m_out1", NULL); 663 clks[TEGRA20_CLK_PLL_M_OUT1] = clk;
666 clks[pll_m_out1] = clk;
667 664
668 /* PLLX */ 665 /* PLLX */
669 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, NULL, 0, 666 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, NULL, 0,
670 0, &pll_x_params, TEGRA_PLL_HAS_CPCON, 667 &pll_x_params, NULL);
671 pll_x_freq_table, NULL); 668 clks[TEGRA20_CLK_PLL_X] = clk;
672 clk_register_clkdev(clk, "pll_x", NULL);
673 clks[pll_x] = clk;
674 669
675 /* PLLU */ 670 /* PLLU */
676 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, NULL, 0, 671 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, NULL, 0,
677 0, &pll_u_params, TEGRA_PLLU | TEGRA_PLL_HAS_CPCON, 672 &pll_u_params, NULL);
678 pll_u_freq_table, NULL); 673 clks[TEGRA20_CLK_PLL_U] = clk;
679 clk_register_clkdev(clk, "pll_u", NULL);
680 clks[pll_u] = clk;
681 674
682 /* PLLD */ 675 /* PLLD */
683 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, NULL, 0, 676 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, NULL, 0,
684 0, &pll_d_params, TEGRA_PLL_HAS_CPCON, 677 &pll_d_params, NULL);
685 pll_d_freq_table, NULL); 678 clks[TEGRA20_CLK_PLL_D] = clk;
686 clk_register_clkdev(clk, "pll_d", NULL);
687 clks[pll_d] = clk;
688 679
689 /* PLLD_OUT0 */ 680 /* PLLD_OUT0 */
690 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d", 681 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
691 CLK_SET_RATE_PARENT, 1, 2); 682 CLK_SET_RATE_PARENT, 1, 2);
692 clk_register_clkdev(clk, "pll_d_out0", NULL); 683 clks[TEGRA20_CLK_PLL_D_OUT0] = clk;
693 clks[pll_d_out0] = clk;
694 684
695 /* PLLA */ 685 /* PLLA */
696 clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, NULL, 0, 686 clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, NULL, 0,
697 0, &pll_a_params, TEGRA_PLL_HAS_CPCON, 687 &pll_a_params, NULL);
698 pll_a_freq_table, NULL); 688 clks[TEGRA20_CLK_PLL_A] = clk;
699 clk_register_clkdev(clk, "pll_a", NULL);
700 clks[pll_a] = clk;
701 689
702 /* PLLA_OUT0 */ 690 /* PLLA_OUT0 */
703 clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a", 691 clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a",
@@ -706,15 +694,12 @@ static void tegra20_pll_init(void)
706 clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div", 694 clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div",
707 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED | 695 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED |
708 CLK_SET_RATE_PARENT, 0, NULL); 696 CLK_SET_RATE_PARENT, 0, NULL);
709 clk_register_clkdev(clk, "pll_a_out0", NULL); 697 clks[TEGRA20_CLK_PLL_A_OUT0] = clk;
710 clks[pll_a_out0] = clk;
711 698
712 /* PLLE */ 699 /* PLLE */
713 clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, pmc_base, 700 clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, pmc_base,
714 0, 100000000, &pll_e_params, 701 0, &pll_e_params, NULL);
715 0, pll_e_freq_table, NULL); 702 clks[TEGRA20_CLK_PLL_E] = clk;
716 clk_register_clkdev(clk, "pll_e", NULL);
717 clks[pll_e] = clk;
718} 703}
719 704
720static const char *cclk_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", 705static const char *cclk_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
@@ -732,40 +717,17 @@ static void tegra20_super_clk_init(void)
732 clk = tegra_clk_register_super_mux("cclk", cclk_parents, 717 clk = tegra_clk_register_super_mux("cclk", cclk_parents,
733 ARRAY_SIZE(cclk_parents), CLK_SET_RATE_PARENT, 718 ARRAY_SIZE(cclk_parents), CLK_SET_RATE_PARENT,
734 clk_base + CCLK_BURST_POLICY, 0, 4, 0, 0, NULL); 719 clk_base + CCLK_BURST_POLICY, 0, 4, 0, 0, NULL);
735 clk_register_clkdev(clk, "cclk", NULL); 720 clks[TEGRA20_CLK_CCLK] = clk;
736 clks[cclk] = clk;
737 721
738 /* SCLK */ 722 /* SCLK */
739 clk = tegra_clk_register_super_mux("sclk", sclk_parents, 723 clk = tegra_clk_register_super_mux("sclk", sclk_parents,
740 ARRAY_SIZE(sclk_parents), CLK_SET_RATE_PARENT, 724 ARRAY_SIZE(sclk_parents), CLK_SET_RATE_PARENT,
741 clk_base + SCLK_BURST_POLICY, 0, 4, 0, 0, NULL); 725 clk_base + SCLK_BURST_POLICY, 0, 4, 0, 0, NULL);
742 clk_register_clkdev(clk, "sclk", NULL); 726 clks[TEGRA20_CLK_SCLK] = clk;
743 clks[sclk] = clk;
744
745 /* HCLK */
746 clk = clk_register_divider(NULL, "hclk_div", "sclk", 0,
747 clk_base + CLK_SYSTEM_RATE, 4, 2, 0,
748 &sysrate_lock);
749 clk = clk_register_gate(NULL, "hclk", "hclk_div", CLK_SET_RATE_PARENT,
750 clk_base + CLK_SYSTEM_RATE, 7,
751 CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
752 clk_register_clkdev(clk, "hclk", NULL);
753 clks[hclk] = clk;
754
755 /* PCLK */
756 clk = clk_register_divider(NULL, "pclk_div", "hclk", 0,
757 clk_base + CLK_SYSTEM_RATE, 0, 2, 0,
758 &sysrate_lock);
759 clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT,
760 clk_base + CLK_SYSTEM_RATE, 3,
761 CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
762 clk_register_clkdev(clk, "pclk", NULL);
763 clks[pclk] = clk;
764 727
765 /* twd */ 728 /* twd */
766 clk = clk_register_fixed_factor(NULL, "twd", "cclk", 0, 1, 4); 729 clk = clk_register_fixed_factor(NULL, "twd", "cclk", 0, 1, 4);
767 clk_register_clkdev(clk, "twd", NULL); 730 clks[TEGRA20_CLK_TWD] = clk;
768 clks[twd] = clk;
769} 731}
770 732
771static const char *audio_parents[] = {"spdif_in", "i2s1", "i2s2", "unused", 733static const char *audio_parents[] = {"spdif_in", "i2s1", "i2s2", "unused",
@@ -784,18 +746,16 @@ static void __init tegra20_audio_clk_init(void)
784 clk = clk_register_gate(NULL, "audio", "audio_mux", 0, 746 clk = clk_register_gate(NULL, "audio", "audio_mux", 0,
785 clk_base + AUDIO_SYNC_CLK, 4, 747 clk_base + AUDIO_SYNC_CLK, 4,
786 CLK_GATE_SET_TO_DISABLE, NULL); 748 CLK_GATE_SET_TO_DISABLE, NULL);
787 clk_register_clkdev(clk, "audio", NULL); 749 clks[TEGRA20_CLK_AUDIO] = clk;
788 clks[audio] = clk;
789 750
790 /* audio_2x */ 751 /* audio_2x */
791 clk = clk_register_fixed_factor(NULL, "audio_doubler", "audio", 752 clk = clk_register_fixed_factor(NULL, "audio_doubler", "audio",
792 CLK_SET_RATE_PARENT, 2, 1); 753 CLK_SET_RATE_PARENT, 2, 1);
793 clk = tegra_clk_register_periph_gate("audio_2x", "audio_doubler", 754 clk = tegra_clk_register_periph_gate("audio_2x", "audio_doubler",
794 TEGRA_PERIPH_NO_RESET, clk_base, 755 TEGRA_PERIPH_NO_RESET, clk_base,
795 CLK_SET_RATE_PARENT, 89, &periph_u_regs, 756 CLK_SET_RATE_PARENT, 89,
796 periph_clk_enb_refcnt); 757 periph_clk_enb_refcnt);
797 clk_register_clkdev(clk, "audio_2x", NULL); 758 clks[TEGRA20_CLK_AUDIO_2X] = clk;
798 clks[audio_2x] = clk;
799 759
800} 760}
801 761
@@ -803,68 +763,36 @@ static const char *i2s1_parents[] = {"pll_a_out0", "audio_2x", "pll_p",
803 "clk_m"}; 763 "clk_m"};
804static const char *i2s2_parents[] = {"pll_a_out0", "audio_2x", "pll_p", 764static const char *i2s2_parents[] = {"pll_a_out0", "audio_2x", "pll_p",
805 "clk_m"}; 765 "clk_m"};
806static const char *spdif_out_parents[] = {"pll_a_out0", "audio_2x", "pll_p",
807 "clk_m"};
808static const char *spdif_in_parents[] = {"pll_p", "pll_c", "pll_m"};
809static const char *pwm_parents[] = {"pll_p", "pll_c", "audio", "clk_m", 766static const char *pwm_parents[] = {"pll_p", "pll_c", "audio", "clk_m",
810 "clk_32k"}; 767 "clk_32k"};
811static const char *mux_pllpcm_clkm[] = {"pll_p", "pll_c", "pll_m", "clk_m"}; 768static const char *mux_pllpcm_clkm[] = {"pll_p", "pll_c", "pll_m", "clk_m"};
812static const char *mux_pllmcpa[] = {"pll_m", "pll_c", "pll_c", "pll_a"};
813static const char *mux_pllpdc_clkm[] = {"pll_p", "pll_d_out0", "pll_c", 769static const char *mux_pllpdc_clkm[] = {"pll_p", "pll_d_out0", "pll_c",
814 "clk_m"}; 770 "clk_m"};
815static const char *mux_pllmcp_clkm[] = {"pll_m", "pll_c", "pll_p", "clk_m"}; 771static const char *mux_pllmcp_clkm[] = {"pll_m", "pll_c", "pll_p", "clk_m"};
816 772
817static struct tegra_periph_init_data tegra_periph_clk_list[] = { 773static struct tegra_periph_init_data tegra_periph_clk_list[] = {
818 TEGRA_INIT_DATA_MUX("i2s1", NULL, "tegra20-i2s.0", i2s1_parents, CLK_SOURCE_I2S1, 11, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s1), 774 TEGRA_INIT_DATA_MUX("i2s1", i2s1_parents, CLK_SOURCE_I2S1, 11, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2S1),
819 TEGRA_INIT_DATA_MUX("i2s2", NULL, "tegra20-i2s.1", i2s2_parents, CLK_SOURCE_I2S2, 18, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s2), 775 TEGRA_INIT_DATA_MUX("i2s2", i2s2_parents, CLK_SOURCE_I2S2, 18, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2S2),
820 TEGRA_INIT_DATA_MUX("spdif_out", "spdif_out", "tegra20-spdif", spdif_out_parents, CLK_SOURCE_SPDIF_OUT, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_out), 776 TEGRA_INIT_DATA_MUX("spi", mux_pllpcm_clkm, CLK_SOURCE_SPI, 43, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_SPI),
821 TEGRA_INIT_DATA_MUX("spdif_in", "spdif_in", "tegra20-spdif", spdif_in_parents, CLK_SOURCE_SPDIF_IN, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_in), 777 TEGRA_INIT_DATA_MUX("xio", mux_pllpcm_clkm, CLK_SOURCE_XIO, 45, 0, TEGRA20_CLK_XIO),
822 TEGRA_INIT_DATA_MUX("sbc1", NULL, "spi_tegra.0", mux_pllpcm_clkm, CLK_SOURCE_SBC1, 41, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc1), 778 TEGRA_INIT_DATA_MUX("twc", mux_pllpcm_clkm, CLK_SOURCE_TWC, 16, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_TWC),
823 TEGRA_INIT_DATA_MUX("sbc2", NULL, "spi_tegra.1", mux_pllpcm_clkm, CLK_SOURCE_SBC2, 44, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc2), 779 TEGRA_INIT_DATA_MUX("ide", mux_pllpcm_clkm, CLK_SOURCE_XIO, 25, 0, TEGRA20_CLK_IDE),
824 TEGRA_INIT_DATA_MUX("sbc3", NULL, "spi_tegra.2", mux_pllpcm_clkm, CLK_SOURCE_SBC3, 46, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc3), 780 TEGRA_INIT_DATA_DIV16("dvc", mux_pllpcm_clkm, CLK_SOURCE_DVC, 47, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_DVC),
825 TEGRA_INIT_DATA_MUX("sbc4", NULL, "spi_tegra.3", mux_pllpcm_clkm, CLK_SOURCE_SBC4, 68, &periph_u_regs, TEGRA_PERIPH_ON_APB, sbc4), 781 TEGRA_INIT_DATA_DIV16("i2c1", mux_pllpcm_clkm, CLK_SOURCE_I2C1, 12, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2C1),
826 TEGRA_INIT_DATA_MUX("spi", NULL, "spi", mux_pllpcm_clkm, CLK_SOURCE_SPI, 43, &periph_h_regs, TEGRA_PERIPH_ON_APB, spi), 782 TEGRA_INIT_DATA_DIV16("i2c2", mux_pllpcm_clkm, CLK_SOURCE_I2C2, 54, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2C2),
827 TEGRA_INIT_DATA_MUX("xio", NULL, "xio", mux_pllpcm_clkm, CLK_SOURCE_XIO, 45, &periph_h_regs, 0, xio), 783 TEGRA_INIT_DATA_DIV16("i2c3", mux_pllpcm_clkm, CLK_SOURCE_I2C3, 67, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2C3),
828 TEGRA_INIT_DATA_MUX("twc", NULL, "twc", mux_pllpcm_clkm, CLK_SOURCE_TWC, 16, &periph_l_regs, TEGRA_PERIPH_ON_APB, twc), 784 TEGRA_INIT_DATA_MUX("hdmi", mux_pllpdc_clkm, CLK_SOURCE_HDMI, 51, 0, TEGRA20_CLK_HDMI),
829 TEGRA_INIT_DATA_MUX("ide", NULL, "ide", mux_pllpcm_clkm, CLK_SOURCE_XIO, 25, &periph_l_regs, 0, ide), 785 TEGRA_INIT_DATA("pwm", NULL, NULL, pwm_parents, CLK_SOURCE_PWM, 28, 3, 0, 0, 8, 1, 0, 17, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_PWM),
830 TEGRA_INIT_DATA_MUX("ndflash", NULL, "tegra_nand", mux_pllpcm_clkm, CLK_SOURCE_NDFLASH, 13, &periph_l_regs, 0, ndflash),
831 TEGRA_INIT_DATA_MUX("vfir", NULL, "vfir", mux_pllpcm_clkm, CLK_SOURCE_VFIR, 7, &periph_l_regs, TEGRA_PERIPH_ON_APB, vfir),
832 TEGRA_INIT_DATA_MUX("csite", NULL, "csite", mux_pllpcm_clkm, CLK_SOURCE_CSITE, 73, &periph_u_regs, 0, csite),
833 TEGRA_INIT_DATA_MUX("la", NULL, "la", mux_pllpcm_clkm, CLK_SOURCE_LA, 76, &periph_u_regs, 0, la),
834 TEGRA_INIT_DATA_MUX("owr", NULL, "tegra_w1", mux_pllpcm_clkm, CLK_SOURCE_OWR, 71, &periph_u_regs, TEGRA_PERIPH_ON_APB, owr),
835 TEGRA_INIT_DATA_MUX("mipi", NULL, "mipi", mux_pllpcm_clkm, CLK_SOURCE_MIPI, 50, &periph_h_regs, TEGRA_PERIPH_ON_APB, mipi),
836 TEGRA_INIT_DATA_MUX("vde", NULL, "vde", mux_pllpcm_clkm, CLK_SOURCE_VDE, 61, &periph_h_regs, 0, vde),
837 TEGRA_INIT_DATA_MUX("vi", "vi", "tegra_camera", mux_pllmcpa, CLK_SOURCE_VI, 20, &periph_l_regs, 0, vi),
838 TEGRA_INIT_DATA_MUX("epp", NULL, "epp", mux_pllmcpa, CLK_SOURCE_EPP, 19, &periph_l_regs, 0, epp),
839 TEGRA_INIT_DATA_MUX("mpe", NULL, "mpe", mux_pllmcpa, CLK_SOURCE_MPE, 60, &periph_h_regs, 0, mpe),
840 TEGRA_INIT_DATA_MUX("host1x", NULL, "host1x", mux_pllmcpa, CLK_SOURCE_HOST1X, 28, &periph_l_regs, 0, host1x),
841 TEGRA_INIT_DATA_MUX("3d", NULL, "3d", mux_pllmcpa, CLK_SOURCE_3D, 24, &periph_l_regs, TEGRA_PERIPH_MANUAL_RESET, gr3d),
842 TEGRA_INIT_DATA_MUX("2d", NULL, "2d", mux_pllmcpa, CLK_SOURCE_2D, 21, &periph_l_regs, 0, gr2d),
843 TEGRA_INIT_DATA_MUX("nor", NULL, "tegra-nor", mux_pllpcm_clkm, CLK_SOURCE_NOR, 42, &periph_h_regs, 0, nor),
844 TEGRA_INIT_DATA_MUX("sdmmc1", NULL, "sdhci-tegra.0", mux_pllpcm_clkm, CLK_SOURCE_SDMMC1, 14, &periph_l_regs, 0, sdmmc1),
845 TEGRA_INIT_DATA_MUX("sdmmc2", NULL, "sdhci-tegra.1", mux_pllpcm_clkm, CLK_SOURCE_SDMMC2, 9, &periph_l_regs, 0, sdmmc2),
846 TEGRA_INIT_DATA_MUX("sdmmc3", NULL, "sdhci-tegra.2", mux_pllpcm_clkm, CLK_SOURCE_SDMMC3, 69, &periph_u_regs, 0, sdmmc3),
847 TEGRA_INIT_DATA_MUX("sdmmc4", NULL, "sdhci-tegra.3", mux_pllpcm_clkm, CLK_SOURCE_SDMMC4, 15, &periph_l_regs, 0, sdmmc4),
848 TEGRA_INIT_DATA_MUX("cve", NULL, "cve", mux_pllpdc_clkm, CLK_SOURCE_CVE, 49, &periph_h_regs, 0, cve),
849 TEGRA_INIT_DATA_MUX("tvo", NULL, "tvo", mux_pllpdc_clkm, CLK_SOURCE_TVO, 49, &periph_h_regs, 0, tvo),
850 TEGRA_INIT_DATA_MUX("tvdac", NULL, "tvdac", mux_pllpdc_clkm, CLK_SOURCE_TVDAC, 53, &periph_h_regs, 0, tvdac),
851 TEGRA_INIT_DATA_MUX("vi_sensor", "vi_sensor", "tegra_camera", mux_pllmcpa, CLK_SOURCE_VI_SENSOR, 20, &periph_l_regs, TEGRA_PERIPH_NO_RESET, vi_sensor),
852 TEGRA_INIT_DATA_DIV16("i2c1", "div-clk", "tegra-i2c.0", mux_pllpcm_clkm, CLK_SOURCE_I2C1, 12, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2c1),
853 TEGRA_INIT_DATA_DIV16("i2c2", "div-clk", "tegra-i2c.1", mux_pllpcm_clkm, CLK_SOURCE_I2C2, 54, &periph_h_regs, TEGRA_PERIPH_ON_APB, i2c2),
854 TEGRA_INIT_DATA_DIV16("i2c3", "div-clk", "tegra-i2c.2", mux_pllpcm_clkm, CLK_SOURCE_I2C3, 67, &periph_u_regs, TEGRA_PERIPH_ON_APB, i2c3),
855 TEGRA_INIT_DATA_DIV16("dvc", "div-clk", "tegra-i2c.3", mux_pllpcm_clkm, CLK_SOURCE_DVC, 47, &periph_h_regs, TEGRA_PERIPH_ON_APB, dvc),
856 TEGRA_INIT_DATA_MUX("hdmi", NULL, "hdmi", mux_pllpdc_clkm, CLK_SOURCE_HDMI, 51, &periph_h_regs, 0, hdmi),
857 TEGRA_INIT_DATA("pwm", NULL, "tegra-pwm", pwm_parents, CLK_SOURCE_PWM, 28, 3, 0, 0, 8, 1, 0, &periph_l_regs, 17, periph_clk_enb_refcnt, TEGRA_PERIPH_ON_APB, pwm),
858}; 786};
859 787
860static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = { 788static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = {
861 TEGRA_INIT_DATA_NODIV("uarta", NULL, "tegra_uart.0", mux_pllpcm_clkm, CLK_SOURCE_UARTA, 30, 2, 6, &periph_l_regs, TEGRA_PERIPH_ON_APB, uarta), 789 TEGRA_INIT_DATA_NODIV("uarta", mux_pllpcm_clkm, CLK_SOURCE_UARTA, 30, 2, 6, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTA),
862 TEGRA_INIT_DATA_NODIV("uartb", NULL, "tegra_uart.1", mux_pllpcm_clkm, CLK_SOURCE_UARTB, 30, 2, 7, &periph_l_regs, TEGRA_PERIPH_ON_APB, uartb), 790 TEGRA_INIT_DATA_NODIV("uartb", mux_pllpcm_clkm, CLK_SOURCE_UARTB, 30, 2, 7, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTB),
863 TEGRA_INIT_DATA_NODIV("uartc", NULL, "tegra_uart.2", mux_pllpcm_clkm, CLK_SOURCE_UARTC, 30, 2, 55, &periph_h_regs, TEGRA_PERIPH_ON_APB, uartc), 791 TEGRA_INIT_DATA_NODIV("uartc", mux_pllpcm_clkm, CLK_SOURCE_UARTC, 30, 2, 55, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTC),
864 TEGRA_INIT_DATA_NODIV("uartd", NULL, "tegra_uart.3", mux_pllpcm_clkm, CLK_SOURCE_UARTD, 30, 2, 65, &periph_u_regs, TEGRA_PERIPH_ON_APB, uartd), 792 TEGRA_INIT_DATA_NODIV("uartd", mux_pllpcm_clkm, CLK_SOURCE_UARTD, 30, 2, 65, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTD),
865 TEGRA_INIT_DATA_NODIV("uarte", NULL, "tegra_uart.4", mux_pllpcm_clkm, CLK_SOURCE_UARTE, 30, 2, 66, &periph_u_regs, TEGRA_PERIPH_ON_APB, uarte), 793 TEGRA_INIT_DATA_NODIV("uarte", mux_pllpcm_clkm, CLK_SOURCE_UARTE, 30, 2, 66, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTE),
866 TEGRA_INIT_DATA_NODIV("disp1", NULL, "tegradc.0", mux_pllpdc_clkm, CLK_SOURCE_DISP1, 30, 2, 27, &periph_l_regs, 0, disp1), 794 TEGRA_INIT_DATA_NODIV("disp1", mux_pllpdc_clkm, CLK_SOURCE_DISP1, 30, 2, 27, 0, TEGRA20_CLK_DISP1),
867 TEGRA_INIT_DATA_NODIV("disp2", NULL, "tegradc.1", mux_pllpdc_clkm, CLK_SOURCE_DISP2, 30, 2, 26, &periph_l_regs, 0, disp2), 795 TEGRA_INIT_DATA_NODIV("disp2", mux_pllpdc_clkm, CLK_SOURCE_DISP2, 30, 2, 26, 0, TEGRA20_CLK_DISP2),
868}; 796};
869 797
870static void __init tegra20_periph_clk_init(void) 798static void __init tegra20_periph_clk_init(void)
@@ -876,69 +804,13 @@ static void __init tegra20_periph_clk_init(void)
876 /* ac97 */ 804 /* ac97 */
877 clk = tegra_clk_register_periph_gate("ac97", "pll_a_out0", 805 clk = tegra_clk_register_periph_gate("ac97", "pll_a_out0",
878 TEGRA_PERIPH_ON_APB, 806 TEGRA_PERIPH_ON_APB,
879 clk_base, 0, 3, &periph_l_regs, 807 clk_base, 0, 3, periph_clk_enb_refcnt);
880 periph_clk_enb_refcnt); 808 clks[TEGRA20_CLK_AC97] = clk;
881 clk_register_clkdev(clk, NULL, "tegra20-ac97");
882 clks[ac97] = clk;
883 809
884 /* apbdma */ 810 /* apbdma */
885 clk = tegra_clk_register_periph_gate("apbdma", "pclk", 0, clk_base, 811 clk = tegra_clk_register_periph_gate("apbdma", "pclk", 0, clk_base,
886 0, 34, &periph_h_regs, 812 0, 34, periph_clk_enb_refcnt);
887 periph_clk_enb_refcnt); 813 clks[TEGRA20_CLK_APBDMA] = clk;
888 clk_register_clkdev(clk, NULL, "tegra-apbdma");
889 clks[apbdma] = clk;
890
891 /* rtc */
892 clk = tegra_clk_register_periph_gate("rtc", "clk_32k",
893 TEGRA_PERIPH_NO_RESET,
894 clk_base, 0, 4, &periph_l_regs,
895 periph_clk_enb_refcnt);
896 clk_register_clkdev(clk, NULL, "rtc-tegra");
897 clks[rtc] = clk;
898
899 /* timer */
900 clk = tegra_clk_register_periph_gate("timer", "clk_m", 0, clk_base,
901 0, 5, &periph_l_regs,
902 periph_clk_enb_refcnt);
903 clk_register_clkdev(clk, NULL, "timer");
904 clks[timer] = clk;
905
906 /* kbc */
907 clk = tegra_clk_register_periph_gate("kbc", "clk_32k",
908 TEGRA_PERIPH_NO_RESET | TEGRA_PERIPH_ON_APB,
909 clk_base, 0, 36, &periph_h_regs,
910 periph_clk_enb_refcnt);
911 clk_register_clkdev(clk, NULL, "tegra-kbc");
912 clks[kbc] = clk;
913
914 /* csus */
915 clk = tegra_clk_register_periph_gate("csus", "clk_m",
916 TEGRA_PERIPH_NO_RESET,
917 clk_base, 0, 92, &periph_u_regs,
918 periph_clk_enb_refcnt);
919 clk_register_clkdev(clk, "csus", "tengra_camera");
920 clks[csus] = clk;
921
922 /* vcp */
923 clk = tegra_clk_register_periph_gate("vcp", "clk_m", 0,
924 clk_base, 0, 29, &periph_l_regs,
925 periph_clk_enb_refcnt);
926 clk_register_clkdev(clk, "vcp", "tegra-avp");
927 clks[vcp] = clk;
928
929 /* bsea */
930 clk = tegra_clk_register_periph_gate("bsea", "clk_m", 0,
931 clk_base, 0, 62, &periph_h_regs,
932 periph_clk_enb_refcnt);
933 clk_register_clkdev(clk, "bsea", "tegra-avp");
934 clks[bsea] = clk;
935
936 /* bsev */
937 clk = tegra_clk_register_periph_gate("bsev", "clk_m", 0,
938 clk_base, 0, 63, &periph_h_regs,
939 periph_clk_enb_refcnt);
940 clk_register_clkdev(clk, "bsev", "tegra-aes");
941 clks[bsev] = clk;
942 814
943 /* emc */ 815 /* emc */
944 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, 816 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
@@ -947,130 +819,52 @@ static void __init tegra20_periph_clk_init(void)
947 clk_base + CLK_SOURCE_EMC, 819 clk_base + CLK_SOURCE_EMC,
948 30, 2, 0, NULL); 820 30, 2, 0, NULL);
949 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0, 821 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0,
950 57, &periph_h_regs, periph_clk_enb_refcnt); 822 57, periph_clk_enb_refcnt);
951 clk_register_clkdev(clk, "emc", NULL); 823 clks[TEGRA20_CLK_EMC] = clk;
952 clks[emc] = clk;
953
954 /* usbd */
955 clk = tegra_clk_register_periph_gate("usbd", "clk_m", 0, clk_base, 0,
956 22, &periph_l_regs, periph_clk_enb_refcnt);
957 clk_register_clkdev(clk, NULL, "fsl-tegra-udc");
958 clks[usbd] = clk;
959
960 /* usb2 */
961 clk = tegra_clk_register_periph_gate("usb2", "clk_m", 0, clk_base, 0,
962 58, &periph_h_regs, periph_clk_enb_refcnt);
963 clk_register_clkdev(clk, NULL, "tegra-ehci.1");
964 clks[usb2] = clk;
965
966 /* usb3 */
967 clk = tegra_clk_register_periph_gate("usb3", "clk_m", 0, clk_base, 0,
968 59, &periph_h_regs, periph_clk_enb_refcnt);
969 clk_register_clkdev(clk, NULL, "tegra-ehci.2");
970 clks[usb3] = clk;
971 824
972 /* dsi */ 825 /* dsi */
973 clk = tegra_clk_register_periph_gate("dsi", "pll_d", 0, clk_base, 0, 826 clk = tegra_clk_register_periph_gate("dsi", "pll_d", 0, clk_base, 0,
974 48, &periph_h_regs, periph_clk_enb_refcnt); 827 48, periph_clk_enb_refcnt);
975 clk_register_clkdev(clk, NULL, "dsi"); 828 clk_register_clkdev(clk, NULL, "dsi");
976 clks[dsi] = clk; 829 clks[TEGRA20_CLK_DSI] = clk;
977
978 /* csi */
979 clk = tegra_clk_register_periph_gate("csi", "pll_p_out3", 0, clk_base,
980 0, 52, &periph_h_regs,
981 periph_clk_enb_refcnt);
982 clk_register_clkdev(clk, "csi", "tegra_camera");
983 clks[csi] = clk;
984
985 /* isp */
986 clk = tegra_clk_register_periph_gate("isp", "clk_m", 0, clk_base, 0, 23,
987 &periph_l_regs, periph_clk_enb_refcnt);
988 clk_register_clkdev(clk, "isp", "tegra_camera");
989 clks[isp] = clk;
990 830
991 /* pex */ 831 /* pex */
992 clk = tegra_clk_register_periph_gate("pex", "clk_m", 0, clk_base, 0, 70, 832 clk = tegra_clk_register_periph_gate("pex", "clk_m", 0, clk_base, 0, 70,
993 &periph_u_regs, periph_clk_enb_refcnt);
994 clk_register_clkdev(clk, "pex", NULL);
995 clks[pex] = clk;
996
997 /* afi */
998 clk = tegra_clk_register_periph_gate("afi", "clk_m", 0, clk_base, 0, 72,
999 &periph_u_regs, periph_clk_enb_refcnt);
1000 clk_register_clkdev(clk, "afi", NULL);
1001 clks[afi] = clk;
1002
1003 /* pcie_xclk */
1004 clk = tegra_clk_register_periph_gate("pcie_xclk", "clk_m", 0, clk_base,
1005 0, 74, &periph_u_regs,
1006 periph_clk_enb_refcnt); 833 periph_clk_enb_refcnt);
1007 clk_register_clkdev(clk, "pcie_xclk", NULL); 834 clks[TEGRA20_CLK_PEX] = clk;
1008 clks[pcie_xclk] = clk;
1009 835
1010 /* cdev1 */ 836 /* cdev1 */
1011 clk = clk_register_fixed_rate(NULL, "cdev1_fixed", NULL, CLK_IS_ROOT, 837 clk = clk_register_fixed_rate(NULL, "cdev1_fixed", NULL, CLK_IS_ROOT,
1012 26000000); 838 26000000);
1013 clk = tegra_clk_register_periph_gate("cdev1", "cdev1_fixed", 0, 839 clk = tegra_clk_register_periph_gate("cdev1", "cdev1_fixed", 0,
1014 clk_base, 0, 94, &periph_u_regs, 840 clk_base, 0, 94, periph_clk_enb_refcnt);
1015 periph_clk_enb_refcnt); 841 clks[TEGRA20_CLK_CDEV1] = clk;
1016 clk_register_clkdev(clk, "cdev1", NULL);
1017 clks[cdev1] = clk;
1018 842
1019 /* cdev2 */ 843 /* cdev2 */
1020 clk = clk_register_fixed_rate(NULL, "cdev2_fixed", NULL, CLK_IS_ROOT, 844 clk = clk_register_fixed_rate(NULL, "cdev2_fixed", NULL, CLK_IS_ROOT,
1021 26000000); 845 26000000);
1022 clk = tegra_clk_register_periph_gate("cdev2", "cdev2_fixed", 0, 846 clk = tegra_clk_register_periph_gate("cdev2", "cdev2_fixed", 0,
1023 clk_base, 0, 93, &periph_u_regs, 847 clk_base, 0, 93, periph_clk_enb_refcnt);
1024 periph_clk_enb_refcnt); 848 clks[TEGRA20_CLK_CDEV2] = clk;
1025 clk_register_clkdev(clk, "cdev2", NULL);
1026 clks[cdev2] = clk;
1027 849
1028 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) { 850 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
1029 data = &tegra_periph_clk_list[i]; 851 data = &tegra_periph_clk_list[i];
1030 clk = tegra_clk_register_periph(data->name, data->parent_names, 852 clk = tegra_clk_register_periph(data->name, data->p.parent_names,
1031 data->num_parents, &data->periph, 853 data->num_parents, &data->periph,
1032 clk_base, data->offset, data->flags); 854 clk_base, data->offset, data->flags);
1033 clk_register_clkdev(clk, data->con_id, data->dev_id);
1034 clks[data->clk_id] = clk; 855 clks[data->clk_id] = clk;
1035 } 856 }
1036 857
1037 for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) { 858 for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) {
1038 data = &tegra_periph_nodiv_clk_list[i]; 859 data = &tegra_periph_nodiv_clk_list[i];
1039 clk = tegra_clk_register_periph_nodiv(data->name, 860 clk = tegra_clk_register_periph_nodiv(data->name,
1040 data->parent_names, 861 data->p.parent_names,
1041 data->num_parents, &data->periph, 862 data->num_parents, &data->periph,
1042 clk_base, data->offset); 863 clk_base, data->offset);
1043 clk_register_clkdev(clk, data->con_id, data->dev_id);
1044 clks[data->clk_id] = clk; 864 clks[data->clk_id] = clk;
1045 } 865 }
1046}
1047
1048
1049static void __init tegra20_fixed_clk_init(void)
1050{
1051 struct clk *clk;
1052
1053 /* clk_32k */
1054 clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, CLK_IS_ROOT,
1055 32768);
1056 clk_register_clkdev(clk, "clk_32k", NULL);
1057 clks[clk_32k] = clk;
1058}
1059
1060static void __init tegra20_pmc_clk_init(void)
1061{
1062 struct clk *clk;
1063 866
1064 /* blink */ 867 tegra_periph_clk_init(clk_base, pmc_base, tegra20_clks, &pll_p_params);
1065 writel_relaxed(0, pmc_base + PMC_BLINK_TIMER);
1066 clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0,
1067 pmc_base + PMC_DPD_PADS_ORIDE,
1068 PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL);
1069 clk = clk_register_gate(NULL, "blink", "blink_override", 0,
1070 pmc_base + PMC_CTRL,
1071 PMC_CTRL_BLINK_ENB, 0, NULL);
1072 clk_register_clkdev(clk, "blink", NULL);
1073 clks[blink] = clk;
1074} 868}
1075 869
1076static void __init tegra20_osc_clk_init(void) 870static void __init tegra20_osc_clk_init(void)
@@ -1084,15 +878,13 @@ static void __init tegra20_osc_clk_init(void)
1084 /* clk_m */ 878 /* clk_m */
1085 clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT | 879 clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT |
1086 CLK_IGNORE_UNUSED, input_freq); 880 CLK_IGNORE_UNUSED, input_freq);
1087 clk_register_clkdev(clk, "clk_m", NULL); 881 clks[TEGRA20_CLK_CLK_M] = clk;
1088 clks[clk_m] = clk;
1089 882
1090 /* pll_ref */ 883 /* pll_ref */
1091 pll_ref_div = tegra20_get_pll_ref_div(); 884 pll_ref_div = tegra20_get_pll_ref_div();
1092 clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m", 885 clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m",
1093 CLK_SET_RATE_PARENT, 1, pll_ref_div); 886 CLK_SET_RATE_PARENT, 1, pll_ref_div);
1094 clk_register_clkdev(clk, "pll_ref", NULL); 887 clks[TEGRA20_CLK_PLL_REF] = clk;
1095 clks[pll_ref] = clk;
1096} 888}
1097 889
1098/* Tegra20 CPU clock and reset control functions */ 890/* Tegra20 CPU clock and reset control functions */
@@ -1226,49 +1018,49 @@ static struct tegra_cpu_car_ops tegra20_cpu_car_ops = {
1226}; 1018};
1227 1019
1228static struct tegra_clk_init_table init_table[] __initdata = { 1020static struct tegra_clk_init_table init_table[] __initdata = {
1229 {pll_p, clk_max, 216000000, 1}, 1021 {TEGRA20_CLK_PLL_P, TEGRA20_CLK_CLK_MAX, 216000000, 1},
1230 {pll_p_out1, clk_max, 28800000, 1}, 1022 {TEGRA20_CLK_PLL_P_OUT1, TEGRA20_CLK_CLK_MAX, 28800000, 1},
1231 {pll_p_out2, clk_max, 48000000, 1}, 1023 {TEGRA20_CLK_PLL_P_OUT2, TEGRA20_CLK_CLK_MAX, 48000000, 1},
1232 {pll_p_out3, clk_max, 72000000, 1}, 1024 {TEGRA20_CLK_PLL_P_OUT3, TEGRA20_CLK_CLK_MAX, 72000000, 1},
1233 {pll_p_out4, clk_max, 24000000, 1}, 1025 {TEGRA20_CLK_PLL_P_OUT4, TEGRA20_CLK_CLK_MAX, 24000000, 1},
1234 {pll_c, clk_max, 600000000, 1}, 1026 {TEGRA20_CLK_PLL_C, TEGRA20_CLK_CLK_MAX, 600000000, 1},
1235 {pll_c_out1, clk_max, 120000000, 1}, 1027 {TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 120000000, 1},
1236 {sclk, pll_c_out1, 0, 1}, 1028 {TEGRA20_CLK_SCLK, TEGRA20_CLK_PLL_C_OUT1, 0, 1},
1237 {hclk, clk_max, 0, 1}, 1029 {TEGRA20_CLK_HCLK, TEGRA20_CLK_CLK_MAX, 0, 1},
1238 {pclk, clk_max, 60000000, 1}, 1030 {TEGRA20_CLK_PCLK, TEGRA20_CLK_CLK_MAX, 60000000, 1},
1239 {csite, clk_max, 0, 1}, 1031 {TEGRA20_CLK_CSITE, TEGRA20_CLK_CLK_MAX, 0, 1},
1240 {emc, clk_max, 0, 1}, 1032 {TEGRA20_CLK_EMC, TEGRA20_CLK_CLK_MAX, 0, 1},
1241 {cclk, clk_max, 0, 1}, 1033 {TEGRA20_CLK_CCLK, TEGRA20_CLK_CLK_MAX, 0, 1},
1242 {uarta, pll_p, 0, 0}, 1034 {TEGRA20_CLK_UARTA, TEGRA20_CLK_PLL_P, 0, 0},
1243 {uartb, pll_p, 0, 0}, 1035 {TEGRA20_CLK_UARTB, TEGRA20_CLK_PLL_P, 0, 0},
1244 {uartc, pll_p, 0, 0}, 1036 {TEGRA20_CLK_UARTC, TEGRA20_CLK_PLL_P, 0, 0},
1245 {uartd, pll_p, 0, 0}, 1037 {TEGRA20_CLK_UARTD, TEGRA20_CLK_PLL_P, 0, 0},
1246 {uarte, pll_p, 0, 0}, 1038 {TEGRA20_CLK_UARTE, TEGRA20_CLK_PLL_P, 0, 0},
1247 {pll_a, clk_max, 56448000, 1}, 1039 {TEGRA20_CLK_PLL_A, TEGRA20_CLK_CLK_MAX, 56448000, 1},
1248 {pll_a_out0, clk_max, 11289600, 1}, 1040 {TEGRA20_CLK_PLL_A_OUT0, TEGRA20_CLK_CLK_MAX, 11289600, 1},
1249 {cdev1, clk_max, 0, 1}, 1041 {TEGRA20_CLK_CDEV1, TEGRA20_CLK_CLK_MAX, 0, 1},
1250 {blink, clk_max, 32768, 1}, 1042 {TEGRA20_CLK_BLINK, TEGRA20_CLK_CLK_MAX, 32768, 1},
1251 {i2s1, pll_a_out0, 11289600, 0}, 1043 {TEGRA20_CLK_I2S1, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0},
1252 {i2s2, pll_a_out0, 11289600, 0}, 1044 {TEGRA20_CLK_I2S2, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0},
1253 {sdmmc1, pll_p, 48000000, 0}, 1045 {TEGRA20_CLK_SDMMC1, TEGRA20_CLK_PLL_P, 48000000, 0},
1254 {sdmmc3, pll_p, 48000000, 0}, 1046 {TEGRA20_CLK_SDMMC3, TEGRA20_CLK_PLL_P, 48000000, 0},
1255 {sdmmc4, pll_p, 48000000, 0}, 1047 {TEGRA20_CLK_SDMMC4, TEGRA20_CLK_PLL_P, 48000000, 0},
1256 {spi, pll_p, 20000000, 0}, 1048 {TEGRA20_CLK_SPI, TEGRA20_CLK_PLL_P, 20000000, 0},
1257 {sbc1, pll_p, 100000000, 0}, 1049 {TEGRA20_CLK_SBC1, TEGRA20_CLK_PLL_P, 100000000, 0},
1258 {sbc2, pll_p, 100000000, 0}, 1050 {TEGRA20_CLK_SBC2, TEGRA20_CLK_PLL_P, 100000000, 0},
1259 {sbc3, pll_p, 100000000, 0}, 1051 {TEGRA20_CLK_SBC3, TEGRA20_CLK_PLL_P, 100000000, 0},
1260 {sbc4, pll_p, 100000000, 0}, 1052 {TEGRA20_CLK_SBC4, TEGRA20_CLK_PLL_P, 100000000, 0},
1261 {host1x, pll_c, 150000000, 0}, 1053 {TEGRA20_CLK_HOST1X, TEGRA20_CLK_PLL_C, 150000000, 0},
1262 {disp1, pll_p, 600000000, 0}, 1054 {TEGRA20_CLK_DISP1, TEGRA20_CLK_PLL_P, 600000000, 0},
1263 {disp2, pll_p, 600000000, 0}, 1055 {TEGRA20_CLK_DISP2, TEGRA20_CLK_PLL_P, 600000000, 0},
1264 {gr2d, pll_c, 300000000, 0}, 1056 {TEGRA20_CLK_GR2D, TEGRA20_CLK_PLL_C, 300000000, 0},
1265 {gr3d, pll_c, 300000000, 0}, 1057 {TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 300000000, 0},
1266 {clk_max, clk_max, 0, 0}, /* This MUST be the last entry */ 1058 {TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0}, /* This MUST be the last entry */
1267}; 1059};
1268 1060
1269static void __init tegra20_clock_apply_init_table(void) 1061static void __init tegra20_clock_apply_init_table(void)
1270{ 1062{
1271 tegra_init_from_table(init_table, clks, clk_max); 1063 tegra_init_from_table(init_table, clks, TEGRA20_CLK_CLK_MAX);
1272} 1064}
1273 1065
1274/* 1066/*
@@ -1277,11 +1069,11 @@ static void __init tegra20_clock_apply_init_table(void)
1277 * table under two names. 1069 * table under two names.
1278 */ 1070 */
1279static struct tegra_clk_duplicate tegra_clk_duplicates[] = { 1071static struct tegra_clk_duplicate tegra_clk_duplicates[] = {
1280 TEGRA_CLK_DUPLICATE(usbd, "utmip-pad", NULL), 1072 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "utmip-pad", NULL),
1281 TEGRA_CLK_DUPLICATE(usbd, "tegra-ehci.0", NULL), 1073 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "tegra-ehci.0", NULL),
1282 TEGRA_CLK_DUPLICATE(usbd, "tegra-otg", NULL), 1074 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "tegra-otg", NULL),
1283 TEGRA_CLK_DUPLICATE(cclk, NULL, "cpu"), 1075 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_CCLK, NULL, "cpu"),
1284 TEGRA_CLK_DUPLICATE(clk_max, NULL, NULL), /* Must be the last entry */ 1076 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_CLK_MAX, NULL, NULL), /* Must be the last entry */
1285}; 1077};
1286 1078
1287static const struct of_device_id pmc_match[] __initconst = { 1079static const struct of_device_id pmc_match[] __initconst = {
@@ -1291,7 +1083,6 @@ static const struct of_device_id pmc_match[] __initconst = {
1291 1083
1292static void __init tegra20_clock_init(struct device_node *np) 1084static void __init tegra20_clock_init(struct device_node *np)
1293{ 1085{
1294 int i;
1295 struct device_node *node; 1086 struct device_node *node;
1296 1087
1297 clk_base = of_iomap(np, 0); 1088 clk_base = of_iomap(np, 0);
@@ -1312,30 +1103,24 @@ static void __init tegra20_clock_init(struct device_node *np)
1312 BUG(); 1103 BUG();
1313 } 1104 }
1314 1105
1106 clks = tegra_clk_init(clk_base, TEGRA20_CLK_CLK_MAX,
1107 TEGRA20_CLK_PERIPH_BANKS);
1108 if (!clks)
1109 return;
1110
1315 tegra20_osc_clk_init(); 1111 tegra20_osc_clk_init();
1316 tegra20_pmc_clk_init(); 1112 tegra_fixed_clk_init(tegra20_clks);
1317 tegra20_fixed_clk_init();
1318 tegra20_pll_init(); 1113 tegra20_pll_init();
1319 tegra20_super_clk_init(); 1114 tegra20_super_clk_init();
1115 tegra_super_clk_gen4_init(clk_base, pmc_base, tegra20_clks, NULL);
1320 tegra20_periph_clk_init(); 1116 tegra20_periph_clk_init();
1321 tegra20_audio_clk_init(); 1117 tegra20_audio_clk_init();
1118 tegra_pmc_clk_init(pmc_base, tegra20_clks);
1322 1119
1120 tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA20_CLK_CLK_MAX);
1323 1121
1324 for (i = 0; i < ARRAY_SIZE(clks); i++) { 1122 tegra_add_of_provider(np);
1325 if (IS_ERR(clks[i])) { 1123 tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
1326 pr_err("Tegra20 clk %d: register failed with %ld\n",
1327 i, PTR_ERR(clks[i]));
1328 BUG();
1329 }
1330 if (!clks[i])
1331 clks[i] = ERR_PTR(-EINVAL);
1332 }
1333
1334 tegra_init_dup_clks(tegra_clk_duplicates, clks, clk_max);
1335
1336 clk_data.clks = clks;
1337 clk_data.clk_num = ARRAY_SIZE(clks);
1338 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
1339 1124
1340 tegra_clk_apply_init_table = tegra20_clock_apply_init_table; 1125 tegra_clk_apply_init_table = tegra20_clock_apply_init_table;
1341 1126
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index dbe7c8003c5c..8b10c38b6e3c 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -23,42 +23,9 @@
23#include <linux/of_address.h> 23#include <linux/of_address.h>
24#include <linux/clk/tegra.h> 24#include <linux/clk/tegra.h>
25#include <linux/tegra-powergate.h> 25#include <linux/tegra-powergate.h>
26 26#include <dt-bindings/clock/tegra30-car.h>
27#include "clk.h" 27#include "clk.h"
28 28#include "clk-id.h"
29#define RST_DEVICES_L 0x004
30#define RST_DEVICES_H 0x008
31#define RST_DEVICES_U 0x00c
32#define RST_DEVICES_V 0x358
33#define RST_DEVICES_W 0x35c
34#define RST_DEVICES_SET_L 0x300
35#define RST_DEVICES_CLR_L 0x304
36#define RST_DEVICES_SET_H 0x308
37#define RST_DEVICES_CLR_H 0x30c
38#define RST_DEVICES_SET_U 0x310
39#define RST_DEVICES_CLR_U 0x314
40#define RST_DEVICES_SET_V 0x430
41#define RST_DEVICES_CLR_V 0x434
42#define RST_DEVICES_SET_W 0x438
43#define RST_DEVICES_CLR_W 0x43c
44#define RST_DEVICES_NUM 5
45
46#define CLK_OUT_ENB_L 0x010
47#define CLK_OUT_ENB_H 0x014
48#define CLK_OUT_ENB_U 0x018
49#define CLK_OUT_ENB_V 0x360
50#define CLK_OUT_ENB_W 0x364
51#define CLK_OUT_ENB_SET_L 0x320
52#define CLK_OUT_ENB_CLR_L 0x324
53#define CLK_OUT_ENB_SET_H 0x328
54#define CLK_OUT_ENB_CLR_H 0x32c
55#define CLK_OUT_ENB_SET_U 0x330
56#define CLK_OUT_ENB_CLR_U 0x334
57#define CLK_OUT_ENB_SET_V 0x440
58#define CLK_OUT_ENB_CLR_V 0x444
59#define CLK_OUT_ENB_SET_W 0x448
60#define CLK_OUT_ENB_CLR_W 0x44c
61#define CLK_OUT_ENB_NUM 5
62 29
63#define OSC_CTRL 0x50 30#define OSC_CTRL 0x50
64#define OSC_CTRL_OSC_FREQ_MASK (0xF<<28) 31#define OSC_CTRL_OSC_FREQ_MASK (0xF<<28)
@@ -92,6 +59,8 @@
92 59
93#define SYSTEM_CLK_RATE 0x030 60#define SYSTEM_CLK_RATE 0x030
94 61
62#define TEGRA30_CLK_PERIPH_BANKS 5
63
95#define PLLC_BASE 0x80 64#define PLLC_BASE 0x80
96#define PLLC_MISC 0x8c 65#define PLLC_MISC 0x8c
97#define PLLM_BASE 0x90 66#define PLLM_BASE 0x90
@@ -132,88 +101,21 @@
132#define AUDIO_SYNC_CLK_I2S4 0x4b0 101#define AUDIO_SYNC_CLK_I2S4 0x4b0
133#define AUDIO_SYNC_CLK_SPDIF 0x4b4 102#define AUDIO_SYNC_CLK_SPDIF 0x4b4
134 103
135#define PMC_CLK_OUT_CNTRL 0x1a8
136
137#define CLK_SOURCE_I2S0 0x1d8
138#define CLK_SOURCE_I2S1 0x100
139#define CLK_SOURCE_I2S2 0x104
140#define CLK_SOURCE_I2S3 0x3bc
141#define CLK_SOURCE_I2S4 0x3c0
142#define CLK_SOURCE_SPDIF_OUT 0x108 104#define CLK_SOURCE_SPDIF_OUT 0x108
143#define CLK_SOURCE_SPDIF_IN 0x10c
144#define CLK_SOURCE_PWM 0x110 105#define CLK_SOURCE_PWM 0x110
145#define CLK_SOURCE_D_AUDIO 0x3d0 106#define CLK_SOURCE_D_AUDIO 0x3d0
146#define CLK_SOURCE_DAM0 0x3d8 107#define CLK_SOURCE_DAM0 0x3d8
147#define CLK_SOURCE_DAM1 0x3dc 108#define CLK_SOURCE_DAM1 0x3dc
148#define CLK_SOURCE_DAM2 0x3e0 109#define CLK_SOURCE_DAM2 0x3e0
149#define CLK_SOURCE_HDA 0x428
150#define CLK_SOURCE_HDA2CODEC_2X 0x3e4
151#define CLK_SOURCE_SBC1 0x134
152#define CLK_SOURCE_SBC2 0x118
153#define CLK_SOURCE_SBC3 0x11c
154#define CLK_SOURCE_SBC4 0x1b4
155#define CLK_SOURCE_SBC5 0x3c8
156#define CLK_SOURCE_SBC6 0x3cc
157#define CLK_SOURCE_SATA_OOB 0x420
158#define CLK_SOURCE_SATA 0x424
159#define CLK_SOURCE_NDFLASH 0x160
160#define CLK_SOURCE_NDSPEED 0x3f8
161#define CLK_SOURCE_VFIR 0x168
162#define CLK_SOURCE_SDMMC1 0x150
163#define CLK_SOURCE_SDMMC2 0x154
164#define CLK_SOURCE_SDMMC3 0x1bc
165#define CLK_SOURCE_SDMMC4 0x164
166#define CLK_SOURCE_VDE 0x1c8
167#define CLK_SOURCE_CSITE 0x1d4
168#define CLK_SOURCE_LA 0x1f8
169#define CLK_SOURCE_OWR 0x1cc
170#define CLK_SOURCE_NOR 0x1d0
171#define CLK_SOURCE_MIPI 0x174
172#define CLK_SOURCE_I2C1 0x124
173#define CLK_SOURCE_I2C2 0x198
174#define CLK_SOURCE_I2C3 0x1b8
175#define CLK_SOURCE_I2C4 0x3c4
176#define CLK_SOURCE_I2C5 0x128
177#define CLK_SOURCE_UARTA 0x178
178#define CLK_SOURCE_UARTB 0x17c
179#define CLK_SOURCE_UARTC 0x1a0
180#define CLK_SOURCE_UARTD 0x1c0
181#define CLK_SOURCE_UARTE 0x1c4
182#define CLK_SOURCE_VI 0x148
183#define CLK_SOURCE_VI_SENSOR 0x1a8
184#define CLK_SOURCE_3D 0x158
185#define CLK_SOURCE_3D2 0x3b0 110#define CLK_SOURCE_3D2 0x3b0
186#define CLK_SOURCE_2D 0x15c 111#define CLK_SOURCE_2D 0x15c
187#define CLK_SOURCE_EPP 0x16c
188#define CLK_SOURCE_MPE 0x170
189#define CLK_SOURCE_HOST1X 0x180
190#define CLK_SOURCE_CVE 0x140
191#define CLK_SOURCE_TVO 0x188
192#define CLK_SOURCE_DTV 0x1dc
193#define CLK_SOURCE_HDMI 0x18c 112#define CLK_SOURCE_HDMI 0x18c
194#define CLK_SOURCE_TVDAC 0x194
195#define CLK_SOURCE_DISP1 0x138
196#define CLK_SOURCE_DISP2 0x13c
197#define CLK_SOURCE_DSIB 0xd0 113#define CLK_SOURCE_DSIB 0xd0
198#define CLK_SOURCE_TSENSOR 0x3b8
199#define CLK_SOURCE_ACTMON 0x3e8
200#define CLK_SOURCE_EXTERN1 0x3ec
201#define CLK_SOURCE_EXTERN2 0x3f0
202#define CLK_SOURCE_EXTERN3 0x3f4
203#define CLK_SOURCE_I2CSLOW 0x3fc
204#define CLK_SOURCE_SE 0x42c 114#define CLK_SOURCE_SE 0x42c
205#define CLK_SOURCE_MSELECT 0x3b4
206#define CLK_SOURCE_EMC 0x19c 115#define CLK_SOURCE_EMC 0x19c
207 116
208#define AUDIO_SYNC_DOUBLER 0x49c 117#define AUDIO_SYNC_DOUBLER 0x49c
209 118
210#define PMC_CTRL 0
211#define PMC_CTRL_BLINK_ENB 7
212
213#define PMC_DPD_PADS_ORIDE 0x1c
214#define PMC_DPD_PADS_ORIDE_BLINK_ENB 20
215#define PMC_BLINK_TIMER 0x40
216
217#define UTMIP_PLL_CFG2 0x488 119#define UTMIP_PLL_CFG2 0x488
218#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6) 120#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6)
219#define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18) 121#define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
@@ -266,89 +168,41 @@ static struct cpu_clk_suspend_context {
266} tegra30_cpu_clk_sctx; 168} tegra30_cpu_clk_sctx;
267#endif 169#endif
268 170
269static int periph_clk_enb_refcnt[CLK_OUT_ENB_NUM * 32];
270
271static void __iomem *clk_base; 171static void __iomem *clk_base;
272static void __iomem *pmc_base; 172static void __iomem *pmc_base;
273static unsigned long input_freq; 173static unsigned long input_freq;
274 174
275static DEFINE_SPINLOCK(clk_doubler_lock);
276static DEFINE_SPINLOCK(clk_out_lock);
277static DEFINE_SPINLOCK(pll_div_lock);
278static DEFINE_SPINLOCK(cml_lock); 175static DEFINE_SPINLOCK(cml_lock);
279static DEFINE_SPINLOCK(pll_d_lock); 176static DEFINE_SPINLOCK(pll_d_lock);
280static DEFINE_SPINLOCK(sysrate_lock);
281
282#define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset, \
283 _clk_num, _regs, _gate_flags, _clk_id) \
284 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
285 30, 2, 0, 0, 8, 1, 0, _regs, _clk_num, \
286 periph_clk_enb_refcnt, _gate_flags, _clk_id)
287
288#define TEGRA_INIT_DATA_DIV16(_name, _con_id, _dev_id, _parents, _offset, \
289 _clk_num, _regs, _gate_flags, _clk_id) \
290 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
291 30, 2, 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP, \
292 _regs, _clk_num, periph_clk_enb_refcnt, \
293 _gate_flags, _clk_id)
294
295#define TEGRA_INIT_DATA_MUX8(_name, _con_id, _dev_id, _parents, _offset, \
296 _clk_num, _regs, _gate_flags, _clk_id) \
297 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
298 29, 3, 0, 0, 8, 1, 0, _regs, _clk_num, \
299 periph_clk_enb_refcnt, _gate_flags, _clk_id)
300
301#define TEGRA_INIT_DATA_INT(_name, _con_id, _dev_id, _parents, _offset, \
302 _clk_num, _regs, _gate_flags, _clk_id) \
303 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
304 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs, \
305 _clk_num, periph_clk_enb_refcnt, _gate_flags, \
306 _clk_id)
307 177
308#define TEGRA_INIT_DATA_UART(_name, _con_id, _dev_id, _parents, _offset,\ 178#define TEGRA_INIT_DATA_MUX(_name, _parents, _offset, \
309 _clk_num, _regs, _clk_id) \ 179 _clk_num, _gate_flags, _clk_id) \
310 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 180 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
311 30, 2, 0, 0, 16, 1, TEGRA_DIVIDER_UART, _regs, \ 181 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
312 _clk_num, periph_clk_enb_refcnt, 0, _clk_id) 182 _clk_num, _gate_flags, _clk_id)
183
184#define TEGRA_INIT_DATA_MUX8(_name, _parents, _offset, \
185 _clk_num, _gate_flags, _clk_id) \
186 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
187 29, 3, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
188 _clk_num, _gate_flags, _clk_id)
189
190#define TEGRA_INIT_DATA_INT(_name, _parents, _offset, \
191 _clk_num, _gate_flags, _clk_id) \
192 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
193 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_INT | \
194 TEGRA_DIVIDER_ROUND_UP, _clk_num, \
195 _gate_flags, _clk_id)
313 196
314#define TEGRA_INIT_DATA_NODIV(_name, _con_id, _dev_id, _parents, _offset, \ 197#define TEGRA_INIT_DATA_NODIV(_name, _parents, _offset, \
315 _mux_shift, _mux_width, _clk_num, _regs, \ 198 _mux_shift, _mux_width, _clk_num, \
316 _gate_flags, _clk_id) \ 199 _gate_flags, _clk_id) \
317 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 200 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
318 _mux_shift, _mux_width, 0, 0, 0, 0, 0, _regs, \ 201 _mux_shift, _mux_width, 0, 0, 0, 0, 0,\
319 _clk_num, periph_clk_enb_refcnt, _gate_flags, \ 202 _clk_num, _gate_flags, \
320 _clk_id) 203 _clk_id)
321 204
322/* 205static struct clk **clks;
323 * IDs assigned here must be in sync with DT bindings definition
324 * for Tegra30 clocks.
325 */
326enum tegra30_clk {
327 cpu, rtc = 4, timer, uarta, gpio = 8, sdmmc2, i2s1 = 11, i2c1, ndflash,
328 sdmmc1, sdmmc4, pwm = 17, i2s2, epp, gr2d = 21, usbd, isp, gr3d,
329 disp2 = 26, disp1, host1x, vcp, i2s0, cop_cache, mc, ahbdma, apbdma,
330 kbc = 36, statmon, pmc, kfuse = 40, sbc1, nor, sbc2 = 44, sbc3 = 46,
331 i2c5, dsia, mipi = 50, hdmi, csi, tvdac, i2c2, uartc, emc = 57, usb2,
332 usb3, mpe, vde, bsea, bsev, speedo, uartd, uarte, i2c3, sbc4, sdmmc3,
333 pcie, owr, afi, csite, pciex, avpucq, la, dtv = 79, ndspeed, i2cslow,
334 dsib, irama = 84, iramb, iramc, iramd, cram2, audio_2x = 90, csus = 92,
335 cdev2, cdev1, cpu_g = 96, cpu_lp, gr3d2, mselect, tsensor, i2s3, i2s4,
336 i2c4, sbc5, sbc6, d_audio, apbif, dam0, dam1, dam2, hda2codec_2x,
337 atomics, audio0_2x, audio1_2x, audio2_2x, audio3_2x, audio4_2x,
338 spdif_2x, actmon, extern1, extern2, extern3, sata_oob, sata, hda,
339 se = 127, hda2hdmi, sata_cold, uartb = 160, vfir, spdif_in, spdif_out,
340 vi, vi_sensor, fuse, fuse_burn, cve, tvo, clk_32k, clk_m, clk_m_div2,
341 clk_m_div4, pll_ref, pll_c, pll_c_out1, pll_m, pll_m_out1, pll_p,
342 pll_p_out1, pll_p_out2, pll_p_out3, pll_p_out4, pll_a, pll_a_out0,
343 pll_d, pll_d_out0, pll_d2, pll_d2_out0, pll_u, pll_x, pll_x_out0, pll_e,
344 spdif_in_sync, i2s0_sync, i2s1_sync, i2s2_sync, i2s3_sync, i2s4_sync,
345 vimclk_sync, audio0, audio1, audio2, audio3, audio4, spdif, clk_out_1,
346 clk_out_2, clk_out_3, sclk, blink, cclk_g, cclk_lp, twd, cml0, cml1,
347 hclk, pclk, clk_out_1_mux = 300, clk_max
348};
349
350static struct clk *clks[clk_max];
351static struct clk_onecell_data clk_data;
352 206
353/* 207/*
354 * Structure defining the fields for USB UTMI clocks Parameters. 208 * Structure defining the fields for USB UTMI clocks Parameters.
@@ -564,6 +418,8 @@ static struct tegra_clk_pll_params pll_c_params = {
564 .lock_mask = PLL_BASE_LOCK, 418 .lock_mask = PLL_BASE_LOCK,
565 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 419 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
566 .lock_delay = 300, 420 .lock_delay = 300,
421 .freq_table = pll_c_freq_table,
422 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK,
567}; 423};
568 424
569static struct div_nmp pllm_nmp = { 425static struct div_nmp pllm_nmp = {
@@ -593,6 +449,9 @@ static struct tegra_clk_pll_params pll_m_params = {
593 .div_nmp = &pllm_nmp, 449 .div_nmp = &pllm_nmp,
594 .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE, 450 .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,
595 .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE, 451 .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE,
452 .freq_table = pll_m_freq_table,
453 .flags = TEGRA_PLLM | TEGRA_PLL_HAS_CPCON |
454 TEGRA_PLL_SET_DCCON | TEGRA_PLL_USE_LOCK,
596}; 455};
597 456
598static struct tegra_clk_pll_params pll_p_params = { 457static struct tegra_clk_pll_params pll_p_params = {
@@ -607,6 +466,9 @@ static struct tegra_clk_pll_params pll_p_params = {
607 .lock_mask = PLL_BASE_LOCK, 466 .lock_mask = PLL_BASE_LOCK,
608 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 467 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
609 .lock_delay = 300, 468 .lock_delay = 300,
469 .freq_table = pll_p_freq_table,
470 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK,
471 .fixed_rate = 408000000,
610}; 472};
611 473
612static struct tegra_clk_pll_params pll_a_params = { 474static struct tegra_clk_pll_params pll_a_params = {
@@ -621,6 +483,8 @@ static struct tegra_clk_pll_params pll_a_params = {
621 .lock_mask = PLL_BASE_LOCK, 483 .lock_mask = PLL_BASE_LOCK,
622 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 484 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
623 .lock_delay = 300, 485 .lock_delay = 300,
486 .freq_table = pll_a_freq_table,
487 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK,
624}; 488};
625 489
626static struct tegra_clk_pll_params pll_d_params = { 490static struct tegra_clk_pll_params pll_d_params = {
@@ -635,6 +499,10 @@ static struct tegra_clk_pll_params pll_d_params = {
635 .lock_mask = PLL_BASE_LOCK, 499 .lock_mask = PLL_BASE_LOCK,
636 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 500 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
637 .lock_delay = 1000, 501 .lock_delay = 1000,
502 .freq_table = pll_d_freq_table,
503 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
504 TEGRA_PLL_USE_LOCK,
505
638}; 506};
639 507
640static struct tegra_clk_pll_params pll_d2_params = { 508static struct tegra_clk_pll_params pll_d2_params = {
@@ -649,6 +517,9 @@ static struct tegra_clk_pll_params pll_d2_params = {
649 .lock_mask = PLL_BASE_LOCK, 517 .lock_mask = PLL_BASE_LOCK,
650 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 518 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
651 .lock_delay = 1000, 519 .lock_delay = 1000,
520 .freq_table = pll_d_freq_table,
521 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
522 TEGRA_PLL_USE_LOCK,
652}; 523};
653 524
654static struct tegra_clk_pll_params pll_u_params = { 525static struct tegra_clk_pll_params pll_u_params = {
@@ -664,6 +535,8 @@ static struct tegra_clk_pll_params pll_u_params = {
664 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 535 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
665 .lock_delay = 1000, 536 .lock_delay = 1000,
666 .pdiv_tohw = pllu_p, 537 .pdiv_tohw = pllu_p,
538 .freq_table = pll_u_freq_table,
539 .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON,
667}; 540};
668 541
669static struct tegra_clk_pll_params pll_x_params = { 542static struct tegra_clk_pll_params pll_x_params = {
@@ -678,6 +551,9 @@ static struct tegra_clk_pll_params pll_x_params = {
678 .lock_mask = PLL_BASE_LOCK, 551 .lock_mask = PLL_BASE_LOCK,
679 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 552 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
680 .lock_delay = 300, 553 .lock_delay = 300,
554 .freq_table = pll_x_freq_table,
555 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_DCCON |
556 TEGRA_PLL_USE_LOCK,
681}; 557};
682 558
683static struct tegra_clk_pll_params pll_e_params = { 559static struct tegra_clk_pll_params pll_e_params = {
@@ -692,116 +568,299 @@ static struct tegra_clk_pll_params pll_e_params = {
692 .lock_mask = PLLE_MISC_LOCK, 568 .lock_mask = PLLE_MISC_LOCK,
693 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE, 569 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
694 .lock_delay = 300, 570 .lock_delay = 300,
571 .freq_table = pll_e_freq_table,
572 .flags = TEGRA_PLLE_CONFIGURE | TEGRA_PLL_FIXED,
573 .fixed_rate = 100000000,
695}; 574};
696 575
697/* Peripheral clock registers */ 576static unsigned long tegra30_input_freq[] = {
698static struct tegra_clk_periph_regs periph_l_regs = { 577 [0] = 13000000,
699 .enb_reg = CLK_OUT_ENB_L, 578 [1] = 16800000,
700 .enb_set_reg = CLK_OUT_ENB_SET_L, 579 [4] = 19200000,
701 .enb_clr_reg = CLK_OUT_ENB_CLR_L, 580 [5] = 38400000,
702 .rst_reg = RST_DEVICES_L, 581 [8] = 12000000,
703 .rst_set_reg = RST_DEVICES_SET_L, 582 [9] = 48000000,
704 .rst_clr_reg = RST_DEVICES_CLR_L, 583 [12] = 260000000,
705}; 584};
706 585
707static struct tegra_clk_periph_regs periph_h_regs = { 586static struct tegra_devclk devclks[] __initdata = {
708 .enb_reg = CLK_OUT_ENB_H, 587 { .con_id = "pll_c", .dt_id = TEGRA30_CLK_PLL_C },
709 .enb_set_reg = CLK_OUT_ENB_SET_H, 588 { .con_id = "pll_c_out1", .dt_id = TEGRA30_CLK_PLL_C_OUT1 },
710 .enb_clr_reg = CLK_OUT_ENB_CLR_H, 589 { .con_id = "pll_p", .dt_id = TEGRA30_CLK_PLL_P },
711 .rst_reg = RST_DEVICES_H, 590 { .con_id = "pll_p_out1", .dt_id = TEGRA30_CLK_PLL_P_OUT1 },
712 .rst_set_reg = RST_DEVICES_SET_H, 591 { .con_id = "pll_p_out2", .dt_id = TEGRA30_CLK_PLL_P_OUT2 },
713 .rst_clr_reg = RST_DEVICES_CLR_H, 592 { .con_id = "pll_p_out3", .dt_id = TEGRA30_CLK_PLL_P_OUT3 },
593 { .con_id = "pll_p_out4", .dt_id = TEGRA30_CLK_PLL_P_OUT4 },
594 { .con_id = "pll_m", .dt_id = TEGRA30_CLK_PLL_M },
595 { .con_id = "pll_m_out1", .dt_id = TEGRA30_CLK_PLL_M_OUT1 },
596 { .con_id = "pll_x", .dt_id = TEGRA30_CLK_PLL_X },
597 { .con_id = "pll_x_out0", .dt_id = TEGRA30_CLK_PLL_X_OUT0 },
598 { .con_id = "pll_u", .dt_id = TEGRA30_CLK_PLL_U },
599 { .con_id = "pll_d", .dt_id = TEGRA30_CLK_PLL_D },
600 { .con_id = "pll_d_out0", .dt_id = TEGRA30_CLK_PLL_D_OUT0 },
601 { .con_id = "pll_d2", .dt_id = TEGRA30_CLK_PLL_D2 },
602 { .con_id = "pll_d2_out0", .dt_id = TEGRA30_CLK_PLL_D2_OUT0 },
603 { .con_id = "pll_a", .dt_id = TEGRA30_CLK_PLL_A },
604 { .con_id = "pll_a_out0", .dt_id = TEGRA30_CLK_PLL_A_OUT0 },
605 { .con_id = "pll_e", .dt_id = TEGRA30_CLK_PLL_E },
606 { .con_id = "spdif_in_sync", .dt_id = TEGRA30_CLK_SPDIF_IN_SYNC },
607 { .con_id = "i2s0_sync", .dt_id = TEGRA30_CLK_I2S0_SYNC },
608 { .con_id = "i2s1_sync", .dt_id = TEGRA30_CLK_I2S1_SYNC },
609 { .con_id = "i2s2_sync", .dt_id = TEGRA30_CLK_I2S2_SYNC },
610 { .con_id = "i2s3_sync", .dt_id = TEGRA30_CLK_I2S3_SYNC },
611 { .con_id = "i2s4_sync", .dt_id = TEGRA30_CLK_I2S4_SYNC },
612 { .con_id = "vimclk_sync", .dt_id = TEGRA30_CLK_VIMCLK_SYNC },
613 { .con_id = "audio0", .dt_id = TEGRA30_CLK_AUDIO0 },
614 { .con_id = "audio1", .dt_id = TEGRA30_CLK_AUDIO1 },
615 { .con_id = "audio2", .dt_id = TEGRA30_CLK_AUDIO2 },
616 { .con_id = "audio3", .dt_id = TEGRA30_CLK_AUDIO3 },
617 { .con_id = "audio4", .dt_id = TEGRA30_CLK_AUDIO4 },
618 { .con_id = "spdif", .dt_id = TEGRA30_CLK_SPDIF },
619 { .con_id = "audio0_2x", .dt_id = TEGRA30_CLK_AUDIO0_2X },
620 { .con_id = "audio1_2x", .dt_id = TEGRA30_CLK_AUDIO1_2X },
621 { .con_id = "audio2_2x", .dt_id = TEGRA30_CLK_AUDIO2_2X },
622 { .con_id = "audio3_2x", .dt_id = TEGRA30_CLK_AUDIO3_2X },
623 { .con_id = "audio4_2x", .dt_id = TEGRA30_CLK_AUDIO4_2X },
624 { .con_id = "spdif_2x", .dt_id = TEGRA30_CLK_SPDIF_2X },
625 { .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA30_CLK_EXTERN1 },
626 { .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA30_CLK_EXTERN2 },
627 { .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA30_CLK_EXTERN3 },
628 { .con_id = "blink", .dt_id = TEGRA30_CLK_BLINK },
629 { .con_id = "cclk_g", .dt_id = TEGRA30_CLK_CCLK_G },
630 { .con_id = "cclk_lp", .dt_id = TEGRA30_CLK_CCLK_LP },
631 { .con_id = "sclk", .dt_id = TEGRA30_CLK_SCLK },
632 { .con_id = "hclk", .dt_id = TEGRA30_CLK_HCLK },
633 { .con_id = "pclk", .dt_id = TEGRA30_CLK_PCLK },
634 { .con_id = "twd", .dt_id = TEGRA30_CLK_TWD },
635 { .con_id = "emc", .dt_id = TEGRA30_CLK_EMC },
636 { .con_id = "clk_32k", .dt_id = TEGRA30_CLK_CLK_32K },
637 { .con_id = "clk_m_div2", .dt_id = TEGRA30_CLK_CLK_M_DIV2 },
638 { .con_id = "clk_m_div4", .dt_id = TEGRA30_CLK_CLK_M_DIV4 },
639 { .con_id = "cml0", .dt_id = TEGRA30_CLK_CML0 },
640 { .con_id = "cml1", .dt_id = TEGRA30_CLK_CML1 },
641 { .con_id = "clk_m", .dt_id = TEGRA30_CLK_CLK_M },
642 { .con_id = "pll_ref", .dt_id = TEGRA30_CLK_PLL_REF },
643 { .con_id = "csus", .dev_id = "tengra_camera", .dt_id = TEGRA30_CLK_CSUS },
644 { .con_id = "vcp", .dev_id = "tegra-avp", .dt_id = TEGRA30_CLK_VCP },
645 { .con_id = "bsea", .dev_id = "tegra-avp", .dt_id = TEGRA30_CLK_BSEA },
646 { .con_id = "bsev", .dev_id = "tegra-aes", .dt_id = TEGRA30_CLK_BSEV },
647 { .con_id = "dsia", .dev_id = "tegradc.0", .dt_id = TEGRA30_CLK_DSIA },
648 { .con_id = "csi", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_CSI },
649 { .con_id = "isp", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_ISP },
650 { .con_id = "pcie", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_PCIE },
651 { .con_id = "afi", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_AFI },
652 { .con_id = "fuse", .dt_id = TEGRA30_CLK_FUSE },
653 { .con_id = "fuse_burn", .dev_id = "fuse-tegra", .dt_id = TEGRA30_CLK_FUSE_BURN },
654 { .con_id = "apbif", .dev_id = "tegra30-ahub", .dt_id = TEGRA30_CLK_APBIF },
655 { .con_id = "hda2hdmi", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA2HDMI },
656 { .dev_id = "tegra-apbdma", .dt_id = TEGRA30_CLK_APBDMA },
657 { .dev_id = "rtc-tegra", .dt_id = TEGRA30_CLK_RTC },
658 { .dev_id = "timer", .dt_id = TEGRA30_CLK_TIMER },
659 { .dev_id = "tegra-kbc", .dt_id = TEGRA30_CLK_KBC },
660 { .dev_id = "fsl-tegra-udc", .dt_id = TEGRA30_CLK_USBD },
661 { .dev_id = "tegra-ehci.1", .dt_id = TEGRA30_CLK_USB2 },
662 { .dev_id = "tegra-ehci.2", .dt_id = TEGRA30_CLK_USB2 },
663 { .dev_id = "kfuse-tegra", .dt_id = TEGRA30_CLK_KFUSE },
664 { .dev_id = "tegra_sata_cold", .dt_id = TEGRA30_CLK_SATA_COLD },
665 { .dev_id = "dtv", .dt_id = TEGRA30_CLK_DTV },
666 { .dev_id = "tegra30-i2s.0", .dt_id = TEGRA30_CLK_I2S0 },
667 { .dev_id = "tegra30-i2s.1", .dt_id = TEGRA30_CLK_I2S1 },
668 { .dev_id = "tegra30-i2s.2", .dt_id = TEGRA30_CLK_I2S2 },
669 { .dev_id = "tegra30-i2s.3", .dt_id = TEGRA30_CLK_I2S3 },
670 { .dev_id = "tegra30-i2s.4", .dt_id = TEGRA30_CLK_I2S4 },
671 { .con_id = "spdif_out", .dev_id = "tegra30-spdif", .dt_id = TEGRA30_CLK_SPDIF_OUT },
672 { .con_id = "spdif_in", .dev_id = "tegra30-spdif", .dt_id = TEGRA30_CLK_SPDIF_IN },
673 { .con_id = "d_audio", .dev_id = "tegra30-ahub", .dt_id = TEGRA30_CLK_D_AUDIO },
674 { .dev_id = "tegra30-dam.0", .dt_id = TEGRA30_CLK_DAM0 },
675 { .dev_id = "tegra30-dam.1", .dt_id = TEGRA30_CLK_DAM1 },
676 { .dev_id = "tegra30-dam.2", .dt_id = TEGRA30_CLK_DAM2 },
677 { .con_id = "hda", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA },
678 { .con_id = "hda2codec", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA2CODEC_2X },
679 { .dev_id = "spi_tegra.0", .dt_id = TEGRA30_CLK_SBC1 },
680 { .dev_id = "spi_tegra.1", .dt_id = TEGRA30_CLK_SBC2 },
681 { .dev_id = "spi_tegra.2", .dt_id = TEGRA30_CLK_SBC3 },
682 { .dev_id = "spi_tegra.3", .dt_id = TEGRA30_CLK_SBC4 },
683 { .dev_id = "spi_tegra.4", .dt_id = TEGRA30_CLK_SBC5 },
684 { .dev_id = "spi_tegra.5", .dt_id = TEGRA30_CLK_SBC6 },
685 { .dev_id = "tegra_sata_oob", .dt_id = TEGRA30_CLK_SATA_OOB },
686 { .dev_id = "tegra_sata", .dt_id = TEGRA30_CLK_SATA },
687 { .dev_id = "tegra_nand", .dt_id = TEGRA30_CLK_NDFLASH },
688 { .dev_id = "tegra_nand_speed", .dt_id = TEGRA30_CLK_NDSPEED },
689 { .dev_id = "vfir", .dt_id = TEGRA30_CLK_VFIR },
690 { .dev_id = "csite", .dt_id = TEGRA30_CLK_CSITE },
691 { .dev_id = "la", .dt_id = TEGRA30_CLK_LA },
692 { .dev_id = "tegra_w1", .dt_id = TEGRA30_CLK_OWR },
693 { .dev_id = "mipi", .dt_id = TEGRA30_CLK_MIPI },
694 { .dev_id = "tegra-tsensor", .dt_id = TEGRA30_CLK_TSENSOR },
695 { .dev_id = "i2cslow", .dt_id = TEGRA30_CLK_I2CSLOW },
696 { .dev_id = "vde", .dt_id = TEGRA30_CLK_VDE },
697 { .con_id = "vi", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_VI },
698 { .dev_id = "epp", .dt_id = TEGRA30_CLK_EPP },
699 { .dev_id = "mpe", .dt_id = TEGRA30_CLK_MPE },
700 { .dev_id = "host1x", .dt_id = TEGRA30_CLK_HOST1X },
701 { .dev_id = "3d", .dt_id = TEGRA30_CLK_GR3D },
702 { .dev_id = "3d2", .dt_id = TEGRA30_CLK_GR3D2 },
703 { .dev_id = "2d", .dt_id = TEGRA30_CLK_GR2D },
704 { .dev_id = "se", .dt_id = TEGRA30_CLK_SE },
705 { .dev_id = "mselect", .dt_id = TEGRA30_CLK_MSELECT },
706 { .dev_id = "tegra-nor", .dt_id = TEGRA30_CLK_NOR },
707 { .dev_id = "sdhci-tegra.0", .dt_id = TEGRA30_CLK_SDMMC1 },
708 { .dev_id = "sdhci-tegra.1", .dt_id = TEGRA30_CLK_SDMMC2 },
709 { .dev_id = "sdhci-tegra.2", .dt_id = TEGRA30_CLK_SDMMC3 },
710 { .dev_id = "sdhci-tegra.3", .dt_id = TEGRA30_CLK_SDMMC4 },
711 { .dev_id = "cve", .dt_id = TEGRA30_CLK_CVE },
712 { .dev_id = "tvo", .dt_id = TEGRA30_CLK_TVO },
713 { .dev_id = "tvdac", .dt_id = TEGRA30_CLK_TVDAC },
714 { .dev_id = "actmon", .dt_id = TEGRA30_CLK_ACTMON },
715 { .con_id = "vi_sensor", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_VI_SENSOR },
716 { .con_id = "div-clk", .dev_id = "tegra-i2c.0", .dt_id = TEGRA30_CLK_I2C1 },
717 { .con_id = "div-clk", .dev_id = "tegra-i2c.1", .dt_id = TEGRA30_CLK_I2C2 },
718 { .con_id = "div-clk", .dev_id = "tegra-i2c.2", .dt_id = TEGRA30_CLK_I2C3 },
719 { .con_id = "div-clk", .dev_id = "tegra-i2c.3", .dt_id = TEGRA30_CLK_I2C4 },
720 { .con_id = "div-clk", .dev_id = "tegra-i2c.4", .dt_id = TEGRA30_CLK_I2C5 },
721 { .dev_id = "tegra_uart.0", .dt_id = TEGRA30_CLK_UARTA },
722 { .dev_id = "tegra_uart.1", .dt_id = TEGRA30_CLK_UARTB },
723 { .dev_id = "tegra_uart.2", .dt_id = TEGRA30_CLK_UARTC },
724 { .dev_id = "tegra_uart.3", .dt_id = TEGRA30_CLK_UARTD },
725 { .dev_id = "tegra_uart.4", .dt_id = TEGRA30_CLK_UARTE },
726 { .dev_id = "hdmi", .dt_id = TEGRA30_CLK_HDMI },
727 { .dev_id = "extern1", .dt_id = TEGRA30_CLK_EXTERN1 },
728 { .dev_id = "extern2", .dt_id = TEGRA30_CLK_EXTERN2 },
729 { .dev_id = "extern3", .dt_id = TEGRA30_CLK_EXTERN3 },
730 { .dev_id = "pwm", .dt_id = TEGRA30_CLK_PWM },
731 { .dev_id = "tegradc.0", .dt_id = TEGRA30_CLK_DISP1 },
732 { .dev_id = "tegradc.1", .dt_id = TEGRA30_CLK_DISP2 },
733 { .dev_id = "tegradc.1", .dt_id = TEGRA30_CLK_DSIB },
714}; 734};
715 735
716static struct tegra_clk_periph_regs periph_u_regs = { 736static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = {
717 .enb_reg = CLK_OUT_ENB_U, 737 [tegra_clk_clk_32k] = { .dt_id = TEGRA30_CLK_CLK_32K, .present = true },
718 .enb_set_reg = CLK_OUT_ENB_SET_U, 738 [tegra_clk_clk_m] = { .dt_id = TEGRA30_CLK_CLK_M, .present = true },
719 .enb_clr_reg = CLK_OUT_ENB_CLR_U, 739 [tegra_clk_clk_m_div2] = { .dt_id = TEGRA30_CLK_CLK_M_DIV2, .present = true },
720 .rst_reg = RST_DEVICES_U, 740 [tegra_clk_clk_m_div4] = { .dt_id = TEGRA30_CLK_CLK_M_DIV4, .present = true },
721 .rst_set_reg = RST_DEVICES_SET_U, 741 [tegra_clk_pll_ref] = { .dt_id = TEGRA30_CLK_PLL_REF, .present = true },
722 .rst_clr_reg = RST_DEVICES_CLR_U, 742 [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA30_CLK_SPDIF_IN_SYNC, .present = true },
723}; 743 [tegra_clk_i2s0_sync] = { .dt_id = TEGRA30_CLK_I2S0_SYNC, .present = true },
744 [tegra_clk_i2s1_sync] = { .dt_id = TEGRA30_CLK_I2S1_SYNC, .present = true },
745 [tegra_clk_i2s2_sync] = { .dt_id = TEGRA30_CLK_I2S2_SYNC, .present = true },
746 [tegra_clk_i2s3_sync] = { .dt_id = TEGRA30_CLK_I2S3_SYNC, .present = true },
747 [tegra_clk_i2s4_sync] = { .dt_id = TEGRA30_CLK_I2S4_SYNC, .present = true },
748 [tegra_clk_vimclk_sync] = { .dt_id = TEGRA30_CLK_VIMCLK_SYNC, .present = true },
749 [tegra_clk_audio0] = { .dt_id = TEGRA30_CLK_AUDIO0, .present = true },
750 [tegra_clk_audio1] = { .dt_id = TEGRA30_CLK_AUDIO1, .present = true },
751 [tegra_clk_audio2] = { .dt_id = TEGRA30_CLK_AUDIO2, .present = true },
752 [tegra_clk_audio3] = { .dt_id = TEGRA30_CLK_AUDIO3, .present = true },
753 [tegra_clk_audio4] = { .dt_id = TEGRA30_CLK_AUDIO4, .present = true },
754 [tegra_clk_spdif] = { .dt_id = TEGRA30_CLK_SPDIF, .present = true },
755 [tegra_clk_audio0_mux] = { .dt_id = TEGRA30_CLK_AUDIO0_MUX, .present = true },
756 [tegra_clk_audio1_mux] = { .dt_id = TEGRA30_CLK_AUDIO1_MUX, .present = true },
757 [tegra_clk_audio2_mux] = { .dt_id = TEGRA30_CLK_AUDIO2_MUX, .present = true },
758 [tegra_clk_audio3_mux] = { .dt_id = TEGRA30_CLK_AUDIO3_MUX, .present = true },
759 [tegra_clk_audio4_mux] = { .dt_id = TEGRA30_CLK_AUDIO4_MUX, .present = true },
760 [tegra_clk_spdif_mux] = { .dt_id = TEGRA30_CLK_SPDIF_MUX, .present = true },
761 [tegra_clk_audio0_2x] = { .dt_id = TEGRA30_CLK_AUDIO0_2X, .present = true },
762 [tegra_clk_audio1_2x] = { .dt_id = TEGRA30_CLK_AUDIO1_2X, .present = true },
763 [tegra_clk_audio2_2x] = { .dt_id = TEGRA30_CLK_AUDIO2_2X, .present = true },
764 [tegra_clk_audio3_2x] = { .dt_id = TEGRA30_CLK_AUDIO3_2X, .present = true },
765 [tegra_clk_audio4_2x] = { .dt_id = TEGRA30_CLK_AUDIO4_2X, .present = true },
766 [tegra_clk_spdif_2x] = { .dt_id = TEGRA30_CLK_SPDIF_2X, .present = true },
767 [tegra_clk_clk_out_1] = { .dt_id = TEGRA30_CLK_CLK_OUT_1, .present = true },
768 [tegra_clk_clk_out_2] = { .dt_id = TEGRA30_CLK_CLK_OUT_2, .present = true },
769 [tegra_clk_clk_out_3] = { .dt_id = TEGRA30_CLK_CLK_OUT_3, .present = true },
770 [tegra_clk_blink] = { .dt_id = TEGRA30_CLK_BLINK, .present = true },
771 [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA30_CLK_CLK_OUT_1_MUX, .present = true },
772 [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA30_CLK_CLK_OUT_2_MUX, .present = true },
773 [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA30_CLK_CLK_OUT_3_MUX, .present = true },
774 [tegra_clk_hclk] = { .dt_id = TEGRA30_CLK_HCLK, .present = true },
775 [tegra_clk_pclk] = { .dt_id = TEGRA30_CLK_PCLK, .present = true },
776 [tegra_clk_i2s0] = { .dt_id = TEGRA30_CLK_I2S0, .present = true },
777 [tegra_clk_i2s1] = { .dt_id = TEGRA30_CLK_I2S1, .present = true },
778 [tegra_clk_i2s2] = { .dt_id = TEGRA30_CLK_I2S2, .present = true },
779 [tegra_clk_i2s3] = { .dt_id = TEGRA30_CLK_I2S3, .present = true },
780 [tegra_clk_i2s4] = { .dt_id = TEGRA30_CLK_I2S4, .present = true },
781 [tegra_clk_spdif_in] = { .dt_id = TEGRA30_CLK_SPDIF_IN, .present = true },
782 [tegra_clk_hda] = { .dt_id = TEGRA30_CLK_HDA, .present = true },
783 [tegra_clk_hda2codec_2x] = { .dt_id = TEGRA30_CLK_HDA2CODEC_2X, .present = true },
784 [tegra_clk_sbc1] = { .dt_id = TEGRA30_CLK_SBC1, .present = true },
785 [tegra_clk_sbc2] = { .dt_id = TEGRA30_CLK_SBC2, .present = true },
786 [tegra_clk_sbc3] = { .dt_id = TEGRA30_CLK_SBC3, .present = true },
787 [tegra_clk_sbc4] = { .dt_id = TEGRA30_CLK_SBC4, .present = true },
788 [tegra_clk_sbc5] = { .dt_id = TEGRA30_CLK_SBC5, .present = true },
789 [tegra_clk_sbc6] = { .dt_id = TEGRA30_CLK_SBC6, .present = true },
790 [tegra_clk_ndflash] = { .dt_id = TEGRA30_CLK_NDFLASH, .present = true },
791 [tegra_clk_ndspeed] = { .dt_id = TEGRA30_CLK_NDSPEED, .present = true },
792 [tegra_clk_vfir] = { .dt_id = TEGRA30_CLK_VFIR, .present = true },
793 [tegra_clk_la] = { .dt_id = TEGRA30_CLK_LA, .present = true },
794 [tegra_clk_csite] = { .dt_id = TEGRA30_CLK_CSITE, .present = true },
795 [tegra_clk_owr] = { .dt_id = TEGRA30_CLK_OWR, .present = true },
796 [tegra_clk_mipi] = { .dt_id = TEGRA30_CLK_MIPI, .present = true },
797 [tegra_clk_tsensor] = { .dt_id = TEGRA30_CLK_TSENSOR, .present = true },
798 [tegra_clk_i2cslow] = { .dt_id = TEGRA30_CLK_I2CSLOW, .present = true },
799 [tegra_clk_vde] = { .dt_id = TEGRA30_CLK_VDE, .present = true },
800 [tegra_clk_vi] = { .dt_id = TEGRA30_CLK_VI, .present = true },
801 [tegra_clk_epp] = { .dt_id = TEGRA30_CLK_EPP, .present = true },
802 [tegra_clk_mpe] = { .dt_id = TEGRA30_CLK_MPE, .present = true },
803 [tegra_clk_host1x] = { .dt_id = TEGRA30_CLK_HOST1X, .present = true },
804 [tegra_clk_gr2d] = { .dt_id = TEGRA30_CLK_GR2D, .present = true },
805 [tegra_clk_gr3d] = { .dt_id = TEGRA30_CLK_GR3D, .present = true },
806 [tegra_clk_mselect] = { .dt_id = TEGRA30_CLK_MSELECT, .present = true },
807 [tegra_clk_nor] = { .dt_id = TEGRA30_CLK_NOR, .present = true },
808 [tegra_clk_sdmmc1] = { .dt_id = TEGRA30_CLK_SDMMC1, .present = true },
809 [tegra_clk_sdmmc2] = { .dt_id = TEGRA30_CLK_SDMMC2, .present = true },
810 [tegra_clk_sdmmc3] = { .dt_id = TEGRA30_CLK_SDMMC3, .present = true },
811 [tegra_clk_sdmmc4] = { .dt_id = TEGRA30_CLK_SDMMC4, .present = true },
812 [tegra_clk_cve] = { .dt_id = TEGRA30_CLK_CVE, .present = true },
813 [tegra_clk_tvo] = { .dt_id = TEGRA30_CLK_TVO, .present = true },
814 [tegra_clk_tvdac] = { .dt_id = TEGRA30_CLK_TVDAC, .present = true },
815 [tegra_clk_actmon] = { .dt_id = TEGRA30_CLK_ACTMON, .present = true },
816 [tegra_clk_vi_sensor] = { .dt_id = TEGRA30_CLK_VI_SENSOR, .present = true },
817 [tegra_clk_i2c1] = { .dt_id = TEGRA30_CLK_I2C1, .present = true },
818 [tegra_clk_i2c2] = { .dt_id = TEGRA30_CLK_I2C2, .present = true },
819 [tegra_clk_i2c3] = { .dt_id = TEGRA30_CLK_I2C3, .present = true },
820 [tegra_clk_i2c4] = { .dt_id = TEGRA30_CLK_I2C4, .present = true },
821 [tegra_clk_i2c5] = { .dt_id = TEGRA30_CLK_I2C5, .present = true },
822 [tegra_clk_uarta] = { .dt_id = TEGRA30_CLK_UARTA, .present = true },
823 [tegra_clk_uartb] = { .dt_id = TEGRA30_CLK_UARTB, .present = true },
824 [tegra_clk_uartc] = { .dt_id = TEGRA30_CLK_UARTC, .present = true },
825 [tegra_clk_uartd] = { .dt_id = TEGRA30_CLK_UARTD, .present = true },
826 [tegra_clk_uarte] = { .dt_id = TEGRA30_CLK_UARTE, .present = true },
827 [tegra_clk_extern1] = { .dt_id = TEGRA30_CLK_EXTERN1, .present = true },
828 [tegra_clk_extern2] = { .dt_id = TEGRA30_CLK_EXTERN2, .present = true },
829 [tegra_clk_extern3] = { .dt_id = TEGRA30_CLK_EXTERN3, .present = true },
830 [tegra_clk_disp1] = { .dt_id = TEGRA30_CLK_DISP1, .present = true },
831 [tegra_clk_disp2] = { .dt_id = TEGRA30_CLK_DISP2, .present = true },
832 [tegra_clk_apbdma] = { .dt_id = TEGRA30_CLK_APBDMA, .present = true },
833 [tegra_clk_rtc] = { .dt_id = TEGRA30_CLK_RTC, .present = true },
834 [tegra_clk_timer] = { .dt_id = TEGRA30_CLK_TIMER, .present = true },
835 [tegra_clk_kbc] = { .dt_id = TEGRA30_CLK_KBC, .present = true },
836 [tegra_clk_csus] = { .dt_id = TEGRA30_CLK_CSUS, .present = true },
837 [tegra_clk_vcp] = { .dt_id = TEGRA30_CLK_VCP, .present = true },
838 [tegra_clk_bsea] = { .dt_id = TEGRA30_CLK_BSEA, .present = true },
839 [tegra_clk_bsev] = { .dt_id = TEGRA30_CLK_BSEV, .present = true },
840 [tegra_clk_usbd] = { .dt_id = TEGRA30_CLK_USBD, .present = true },
841 [tegra_clk_usb2] = { .dt_id = TEGRA30_CLK_USB2, .present = true },
842 [tegra_clk_usb3] = { .dt_id = TEGRA30_CLK_USB3, .present = true },
843 [tegra_clk_csi] = { .dt_id = TEGRA30_CLK_CSI, .present = true },
844 [tegra_clk_isp] = { .dt_id = TEGRA30_CLK_ISP, .present = true },
845 [tegra_clk_kfuse] = { .dt_id = TEGRA30_CLK_KFUSE, .present = true },
846 [tegra_clk_fuse] = { .dt_id = TEGRA30_CLK_FUSE, .present = true },
847 [tegra_clk_fuse_burn] = { .dt_id = TEGRA30_CLK_FUSE_BURN, .present = true },
848 [tegra_clk_apbif] = { .dt_id = TEGRA30_CLK_APBIF, .present = true },
849 [tegra_clk_hda2hdmi] = { .dt_id = TEGRA30_CLK_HDA2HDMI, .present = true },
850 [tegra_clk_sata_cold] = { .dt_id = TEGRA30_CLK_SATA_COLD, .present = true },
851 [tegra_clk_sata_oob] = { .dt_id = TEGRA30_CLK_SATA_OOB, .present = true },
852 [tegra_clk_sata] = { .dt_id = TEGRA30_CLK_SATA, .present = true },
853 [tegra_clk_dtv] = { .dt_id = TEGRA30_CLK_DTV, .present = true },
854 [tegra_clk_pll_p] = { .dt_id = TEGRA30_CLK_PLL_P, .present = true },
855 [tegra_clk_pll_p_out1] = { .dt_id = TEGRA30_CLK_PLL_P_OUT1, .present = true },
856 [tegra_clk_pll_p_out2] = { .dt_id = TEGRA30_CLK_PLL_P_OUT2, .present = true },
857 [tegra_clk_pll_p_out3] = { .dt_id = TEGRA30_CLK_PLL_P_OUT3, .present = true },
858 [tegra_clk_pll_p_out4] = { .dt_id = TEGRA30_CLK_PLL_P_OUT4, .present = true },
859 [tegra_clk_pll_a] = { .dt_id = TEGRA30_CLK_PLL_A, .present = true },
860 [tegra_clk_pll_a_out0] = { .dt_id = TEGRA30_CLK_PLL_A_OUT0, .present = true },
724 861
725static struct tegra_clk_periph_regs periph_v_regs = {
726 .enb_reg = CLK_OUT_ENB_V,
727 .enb_set_reg = CLK_OUT_ENB_SET_V,
728 .enb_clr_reg = CLK_OUT_ENB_CLR_V,
729 .rst_reg = RST_DEVICES_V,
730 .rst_set_reg = RST_DEVICES_SET_V,
731 .rst_clr_reg = RST_DEVICES_CLR_V,
732}; 862};
733 863
734static struct tegra_clk_periph_regs periph_w_regs = {
735 .enb_reg = CLK_OUT_ENB_W,
736 .enb_set_reg = CLK_OUT_ENB_SET_W,
737 .enb_clr_reg = CLK_OUT_ENB_CLR_W,
738 .rst_reg = RST_DEVICES_W,
739 .rst_set_reg = RST_DEVICES_SET_W,
740 .rst_clr_reg = RST_DEVICES_CLR_W,
741};
742
743static void tegra30_clk_measure_input_freq(void)
744{
745 u32 osc_ctrl = readl_relaxed(clk_base + OSC_CTRL);
746 u32 auto_clk_control = osc_ctrl & OSC_CTRL_OSC_FREQ_MASK;
747 u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK;
748
749 switch (auto_clk_control) {
750 case OSC_CTRL_OSC_FREQ_12MHZ:
751 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
752 input_freq = 12000000;
753 break;
754 case OSC_CTRL_OSC_FREQ_13MHZ:
755 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
756 input_freq = 13000000;
757 break;
758 case OSC_CTRL_OSC_FREQ_19_2MHZ:
759 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
760 input_freq = 19200000;
761 break;
762 case OSC_CTRL_OSC_FREQ_26MHZ:
763 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
764 input_freq = 26000000;
765 break;
766 case OSC_CTRL_OSC_FREQ_16_8MHZ:
767 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
768 input_freq = 16800000;
769 break;
770 case OSC_CTRL_OSC_FREQ_38_4MHZ:
771 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_2);
772 input_freq = 38400000;
773 break;
774 case OSC_CTRL_OSC_FREQ_48MHZ:
775 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_4);
776 input_freq = 48000000;
777 break;
778 default:
779 pr_err("Unexpected auto clock control value %d",
780 auto_clk_control);
781 BUG();
782 return;
783 }
784}
785
786static unsigned int tegra30_get_pll_ref_div(void)
787{
788 u32 pll_ref_div = readl_relaxed(clk_base + OSC_CTRL) &
789 OSC_CTRL_PLL_REF_DIV_MASK;
790
791 switch (pll_ref_div) {
792 case OSC_CTRL_PLL_REF_DIV_1:
793 return 1;
794 case OSC_CTRL_PLL_REF_DIV_2:
795 return 2;
796 case OSC_CTRL_PLL_REF_DIV_4:
797 return 4;
798 default:
799 pr_err("Invalid pll ref divider %d", pll_ref_div);
800 BUG();
801 }
802 return 0;
803}
804
805static void tegra30_utmi_param_configure(void) 864static void tegra30_utmi_param_configure(void)
806{ 865{
807 u32 reg; 866 u32 reg;
@@ -863,11 +922,8 @@ static void __init tegra30_pll_init(void)
863 922
864 /* PLLC */ 923 /* PLLC */
865 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, pmc_base, 0, 924 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, pmc_base, 0,
866 0, &pll_c_params, 925 &pll_c_params, NULL);
867 TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK, 926 clks[TEGRA30_CLK_PLL_C] = clk;
868 pll_c_freq_table, NULL);
869 clk_register_clkdev(clk, "pll_c", NULL);
870 clks[pll_c] = clk;
871 927
872 /* PLLC_OUT1 */ 928 /* PLLC_OUT1 */
873 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c", 929 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
@@ -876,73 +932,13 @@ static void __init tegra30_pll_init(void)
876 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div", 932 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
877 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT, 933 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT,
878 0, NULL); 934 0, NULL);
879 clk_register_clkdev(clk, "pll_c_out1", NULL); 935 clks[TEGRA30_CLK_PLL_C_OUT1] = clk;
880 clks[pll_c_out1] = clk;
881
882 /* PLLP */
883 clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base, pmc_base, 0,
884 408000000, &pll_p_params,
885 TEGRA_PLL_FIXED | TEGRA_PLL_HAS_CPCON |
886 TEGRA_PLL_USE_LOCK, pll_p_freq_table, NULL);
887 clk_register_clkdev(clk, "pll_p", NULL);
888 clks[pll_p] = clk;
889
890 /* PLLP_OUT1 */
891 clk = tegra_clk_register_divider("pll_p_out1_div", "pll_p",
892 clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED |
893 TEGRA_DIVIDER_ROUND_UP, 8, 8, 1,
894 &pll_div_lock);
895 clk = tegra_clk_register_pll_out("pll_p_out1", "pll_p_out1_div",
896 clk_base + PLLP_OUTA, 1, 0,
897 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
898 &pll_div_lock);
899 clk_register_clkdev(clk, "pll_p_out1", NULL);
900 clks[pll_p_out1] = clk;
901
902 /* PLLP_OUT2 */
903 clk = tegra_clk_register_divider("pll_p_out2_div", "pll_p",
904 clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED |
905 TEGRA_DIVIDER_ROUND_UP, 24, 8, 1,
906 &pll_div_lock);
907 clk = tegra_clk_register_pll_out("pll_p_out2", "pll_p_out2_div",
908 clk_base + PLLP_OUTA, 17, 16,
909 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
910 &pll_div_lock);
911 clk_register_clkdev(clk, "pll_p_out2", NULL);
912 clks[pll_p_out2] = clk;
913
914 /* PLLP_OUT3 */
915 clk = tegra_clk_register_divider("pll_p_out3_div", "pll_p",
916 clk_base + PLLP_OUTB, 0, TEGRA_DIVIDER_FIXED |
917 TEGRA_DIVIDER_ROUND_UP, 8, 8, 1,
918 &pll_div_lock);
919 clk = tegra_clk_register_pll_out("pll_p_out3", "pll_p_out3_div",
920 clk_base + PLLP_OUTB, 1, 0,
921 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
922 &pll_div_lock);
923 clk_register_clkdev(clk, "pll_p_out3", NULL);
924 clks[pll_p_out3] = clk;
925
926 /* PLLP_OUT4 */
927 clk = tegra_clk_register_divider("pll_p_out4_div", "pll_p",
928 clk_base + PLLP_OUTB, 0, TEGRA_DIVIDER_FIXED |
929 TEGRA_DIVIDER_ROUND_UP, 24, 8, 1,
930 &pll_div_lock);
931 clk = tegra_clk_register_pll_out("pll_p_out4", "pll_p_out4_div",
932 clk_base + PLLP_OUTB, 17, 16,
933 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
934 &pll_div_lock);
935 clk_register_clkdev(clk, "pll_p_out4", NULL);
936 clks[pll_p_out4] = clk;
937 936
938 /* PLLM */ 937 /* PLLM */
939 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, pmc_base, 938 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, pmc_base,
940 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE, 0, 939 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
941 &pll_m_params, TEGRA_PLLM | TEGRA_PLL_HAS_CPCON | 940 &pll_m_params, NULL);
942 TEGRA_PLL_SET_DCCON | TEGRA_PLL_USE_LOCK, 941 clks[TEGRA30_CLK_PLL_M] = clk;
943 pll_m_freq_table, NULL);
944 clk_register_clkdev(clk, "pll_m", NULL);
945 clks[pll_m] = clk;
946 942
947 /* PLLM_OUT1 */ 943 /* PLLM_OUT1 */
948 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m", 944 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
@@ -951,78 +947,44 @@ static void __init tegra30_pll_init(void)
951 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div", 947 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
952 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED | 948 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |
953 CLK_SET_RATE_PARENT, 0, NULL); 949 CLK_SET_RATE_PARENT, 0, NULL);
954 clk_register_clkdev(clk, "pll_m_out1", NULL); 950 clks[TEGRA30_CLK_PLL_M_OUT1] = clk;
955 clks[pll_m_out1] = clk;
956 951
957 /* PLLX */ 952 /* PLLX */
958 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, pmc_base, 0, 953 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, pmc_base, 0,
959 0, &pll_x_params, TEGRA_PLL_HAS_CPCON | 954 &pll_x_params, NULL);
960 TEGRA_PLL_SET_DCCON | TEGRA_PLL_USE_LOCK, 955 clks[TEGRA30_CLK_PLL_X] = clk;
961 pll_x_freq_table, NULL);
962 clk_register_clkdev(clk, "pll_x", NULL);
963 clks[pll_x] = clk;
964 956
965 /* PLLX_OUT0 */ 957 /* PLLX_OUT0 */
966 clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x", 958 clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x",
967 CLK_SET_RATE_PARENT, 1, 2); 959 CLK_SET_RATE_PARENT, 1, 2);
968 clk_register_clkdev(clk, "pll_x_out0", NULL); 960 clks[TEGRA30_CLK_PLL_X_OUT0] = clk;
969 clks[pll_x_out0] = clk;
970 961
971 /* PLLU */ 962 /* PLLU */
972 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc_base, 0, 963 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc_base, 0,
973 0, &pll_u_params, TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | 964 &pll_u_params, NULL);
974 TEGRA_PLL_SET_LFCON, 965 clks[TEGRA30_CLK_PLL_U] = clk;
975 pll_u_freq_table,
976 NULL);
977 clk_register_clkdev(clk, "pll_u", NULL);
978 clks[pll_u] = clk;
979 966
980 tegra30_utmi_param_configure(); 967 tegra30_utmi_param_configure();
981 968
982 /* PLLD */ 969 /* PLLD */
983 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc_base, 0, 970 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc_base, 0,
984 0, &pll_d_params, TEGRA_PLL_HAS_CPCON | 971 &pll_d_params, &pll_d_lock);
985 TEGRA_PLL_SET_LFCON | TEGRA_PLL_USE_LOCK, 972 clks[TEGRA30_CLK_PLL_D] = clk;
986 pll_d_freq_table, &pll_d_lock);
987 clk_register_clkdev(clk, "pll_d", NULL);
988 clks[pll_d] = clk;
989 973
990 /* PLLD_OUT0 */ 974 /* PLLD_OUT0 */
991 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d", 975 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
992 CLK_SET_RATE_PARENT, 1, 2); 976 CLK_SET_RATE_PARENT, 1, 2);
993 clk_register_clkdev(clk, "pll_d_out0", NULL); 977 clks[TEGRA30_CLK_PLL_D_OUT0] = clk;
994 clks[pll_d_out0] = clk;
995 978
996 /* PLLD2 */ 979 /* PLLD2 */
997 clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc_base, 0, 980 clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc_base, 0,
998 0, &pll_d2_params, TEGRA_PLL_HAS_CPCON | 981 &pll_d2_params, NULL);
999 TEGRA_PLL_SET_LFCON | TEGRA_PLL_USE_LOCK, 982 clks[TEGRA30_CLK_PLL_D2] = clk;
1000 pll_d_freq_table, NULL);
1001 clk_register_clkdev(clk, "pll_d2", NULL);
1002 clks[pll_d2] = clk;
1003 983
1004 /* PLLD2_OUT0 */ 984 /* PLLD2_OUT0 */
1005 clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2", 985 clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
1006 CLK_SET_RATE_PARENT, 1, 2); 986 CLK_SET_RATE_PARENT, 1, 2);
1007 clk_register_clkdev(clk, "pll_d2_out0", NULL); 987 clks[TEGRA30_CLK_PLL_D2_OUT0] = clk;
1008 clks[pll_d2_out0] = clk;
1009
1010 /* PLLA */
1011 clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, pmc_base,
1012 0, 0, &pll_a_params, TEGRA_PLL_HAS_CPCON |
1013 TEGRA_PLL_USE_LOCK, pll_a_freq_table, NULL);
1014 clk_register_clkdev(clk, "pll_a", NULL);
1015 clks[pll_a] = clk;
1016
1017 /* PLLA_OUT0 */
1018 clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a",
1019 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
1020 8, 8, 1, NULL);
1021 clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div",
1022 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED |
1023 CLK_SET_RATE_PARENT, 0, NULL);
1024 clk_register_clkdev(clk, "pll_a_out0", NULL);
1025 clks[pll_a_out0] = clk;
1026 988
1027 /* PLLE */ 989 /* PLLE */
1028 clk = clk_register_mux(NULL, "pll_e_mux", pll_e_parents, 990 clk = clk_register_mux(NULL, "pll_e_mux", pll_e_parents,
@@ -1030,258 +992,8 @@ static void __init tegra30_pll_init(void)
1030 CLK_SET_RATE_NO_REPARENT, 992 CLK_SET_RATE_NO_REPARENT,
1031 clk_base + PLLE_AUX, 2, 1, 0, NULL); 993 clk_base + PLLE_AUX, 2, 1, 0, NULL);
1032 clk = tegra_clk_register_plle("pll_e", "pll_e_mux", clk_base, pmc_base, 994 clk = tegra_clk_register_plle("pll_e", "pll_e_mux", clk_base, pmc_base,
1033 CLK_GET_RATE_NOCACHE, 100000000, &pll_e_params, 995 CLK_GET_RATE_NOCACHE, &pll_e_params, NULL);
1034 TEGRA_PLLE_CONFIGURE, pll_e_freq_table, NULL); 996 clks[TEGRA30_CLK_PLL_E] = clk;
1035 clk_register_clkdev(clk, "pll_e", NULL);
1036 clks[pll_e] = clk;
1037}
1038
1039static const char *mux_audio_sync_clk[] = { "spdif_in_sync", "i2s0_sync",
1040 "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync",};
1041static const char *clk_out1_parents[] = { "clk_m", "clk_m_div2",
1042 "clk_m_div4", "extern1", };
1043static const char *clk_out2_parents[] = { "clk_m", "clk_m_div2",
1044 "clk_m_div4", "extern2", };
1045static const char *clk_out3_parents[] = { "clk_m", "clk_m_div2",
1046 "clk_m_div4", "extern3", };
1047
1048static void __init tegra30_audio_clk_init(void)
1049{
1050 struct clk *clk;
1051
1052 /* spdif_in_sync */
1053 clk = tegra_clk_register_sync_source("spdif_in_sync", 24000000,
1054 24000000);
1055 clk_register_clkdev(clk, "spdif_in_sync", NULL);
1056 clks[spdif_in_sync] = clk;
1057
1058 /* i2s0_sync */
1059 clk = tegra_clk_register_sync_source("i2s0_sync", 24000000, 24000000);
1060 clk_register_clkdev(clk, "i2s0_sync", NULL);
1061 clks[i2s0_sync] = clk;
1062
1063 /* i2s1_sync */
1064 clk = tegra_clk_register_sync_source("i2s1_sync", 24000000, 24000000);
1065 clk_register_clkdev(clk, "i2s1_sync", NULL);
1066 clks[i2s1_sync] = clk;
1067
1068 /* i2s2_sync */
1069 clk = tegra_clk_register_sync_source("i2s2_sync", 24000000, 24000000);
1070 clk_register_clkdev(clk, "i2s2_sync", NULL);
1071 clks[i2s2_sync] = clk;
1072
1073 /* i2s3_sync */
1074 clk = tegra_clk_register_sync_source("i2s3_sync", 24000000, 24000000);
1075 clk_register_clkdev(clk, "i2s3_sync", NULL);
1076 clks[i2s3_sync] = clk;
1077
1078 /* i2s4_sync */
1079 clk = tegra_clk_register_sync_source("i2s4_sync", 24000000, 24000000);
1080 clk_register_clkdev(clk, "i2s4_sync", NULL);
1081 clks[i2s4_sync] = clk;
1082
1083 /* vimclk_sync */
1084 clk = tegra_clk_register_sync_source("vimclk_sync", 24000000, 24000000);
1085 clk_register_clkdev(clk, "vimclk_sync", NULL);
1086 clks[vimclk_sync] = clk;
1087
1088 /* audio0 */
1089 clk = clk_register_mux(NULL, "audio0_mux", mux_audio_sync_clk,
1090 ARRAY_SIZE(mux_audio_sync_clk),
1091 CLK_SET_RATE_NO_REPARENT,
1092 clk_base + AUDIO_SYNC_CLK_I2S0, 0, 3, 0, NULL);
1093 clk = clk_register_gate(NULL, "audio0", "audio0_mux", 0,
1094 clk_base + AUDIO_SYNC_CLK_I2S0, 4,
1095 CLK_GATE_SET_TO_DISABLE, NULL);
1096 clk_register_clkdev(clk, "audio0", NULL);
1097 clks[audio0] = clk;
1098
1099 /* audio1 */
1100 clk = clk_register_mux(NULL, "audio1_mux", mux_audio_sync_clk,
1101 ARRAY_SIZE(mux_audio_sync_clk),
1102 CLK_SET_RATE_NO_REPARENT,
1103 clk_base + AUDIO_SYNC_CLK_I2S1, 0, 3, 0, NULL);
1104 clk = clk_register_gate(NULL, "audio1", "audio1_mux", 0,
1105 clk_base + AUDIO_SYNC_CLK_I2S1, 4,
1106 CLK_GATE_SET_TO_DISABLE, NULL);
1107 clk_register_clkdev(clk, "audio1", NULL);
1108 clks[audio1] = clk;
1109
1110 /* audio2 */
1111 clk = clk_register_mux(NULL, "audio2_mux", mux_audio_sync_clk,
1112 ARRAY_SIZE(mux_audio_sync_clk),
1113 CLK_SET_RATE_NO_REPARENT,
1114 clk_base + AUDIO_SYNC_CLK_I2S2, 0, 3, 0, NULL);
1115 clk = clk_register_gate(NULL, "audio2", "audio2_mux", 0,
1116 clk_base + AUDIO_SYNC_CLK_I2S2, 4,
1117 CLK_GATE_SET_TO_DISABLE, NULL);
1118 clk_register_clkdev(clk, "audio2", NULL);
1119 clks[audio2] = clk;
1120
1121 /* audio3 */
1122 clk = clk_register_mux(NULL, "audio3_mux", mux_audio_sync_clk,
1123 ARRAY_SIZE(mux_audio_sync_clk),
1124 CLK_SET_RATE_NO_REPARENT,
1125 clk_base + AUDIO_SYNC_CLK_I2S3, 0, 3, 0, NULL);
1126 clk = clk_register_gate(NULL, "audio3", "audio3_mux", 0,
1127 clk_base + AUDIO_SYNC_CLK_I2S3, 4,
1128 CLK_GATE_SET_TO_DISABLE, NULL);
1129 clk_register_clkdev(clk, "audio3", NULL);
1130 clks[audio3] = clk;
1131
1132 /* audio4 */
1133 clk = clk_register_mux(NULL, "audio4_mux", mux_audio_sync_clk,
1134 ARRAY_SIZE(mux_audio_sync_clk),
1135 CLK_SET_RATE_NO_REPARENT,
1136 clk_base + AUDIO_SYNC_CLK_I2S4, 0, 3, 0, NULL);
1137 clk = clk_register_gate(NULL, "audio4", "audio4_mux", 0,
1138 clk_base + AUDIO_SYNC_CLK_I2S4, 4,
1139 CLK_GATE_SET_TO_DISABLE, NULL);
1140 clk_register_clkdev(clk, "audio4", NULL);
1141 clks[audio4] = clk;
1142
1143 /* spdif */
1144 clk = clk_register_mux(NULL, "spdif_mux", mux_audio_sync_clk,
1145 ARRAY_SIZE(mux_audio_sync_clk),
1146 CLK_SET_RATE_NO_REPARENT,
1147 clk_base + AUDIO_SYNC_CLK_SPDIF, 0, 3, 0, NULL);
1148 clk = clk_register_gate(NULL, "spdif", "spdif_mux", 0,
1149 clk_base + AUDIO_SYNC_CLK_SPDIF, 4,
1150 CLK_GATE_SET_TO_DISABLE, NULL);
1151 clk_register_clkdev(clk, "spdif", NULL);
1152 clks[spdif] = clk;
1153
1154 /* audio0_2x */
1155 clk = clk_register_fixed_factor(NULL, "audio0_doubler", "audio0",
1156 CLK_SET_RATE_PARENT, 2, 1);
1157 clk = tegra_clk_register_divider("audio0_div", "audio0_doubler",
1158 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 24, 1, 0,
1159 &clk_doubler_lock);
1160 clk = tegra_clk_register_periph_gate("audio0_2x", "audio0_div",
1161 TEGRA_PERIPH_NO_RESET, clk_base,
1162 CLK_SET_RATE_PARENT, 113, &periph_v_regs,
1163 periph_clk_enb_refcnt);
1164 clk_register_clkdev(clk, "audio0_2x", NULL);
1165 clks[audio0_2x] = clk;
1166
1167 /* audio1_2x */
1168 clk = clk_register_fixed_factor(NULL, "audio1_doubler", "audio1",
1169 CLK_SET_RATE_PARENT, 2, 1);
1170 clk = tegra_clk_register_divider("audio1_div", "audio1_doubler",
1171 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 25, 1, 0,
1172 &clk_doubler_lock);
1173 clk = tegra_clk_register_periph_gate("audio1_2x", "audio1_div",
1174 TEGRA_PERIPH_NO_RESET, clk_base,
1175 CLK_SET_RATE_PARENT, 114, &periph_v_regs,
1176 periph_clk_enb_refcnt);
1177 clk_register_clkdev(clk, "audio1_2x", NULL);
1178 clks[audio1_2x] = clk;
1179
1180 /* audio2_2x */
1181 clk = clk_register_fixed_factor(NULL, "audio2_doubler", "audio2",
1182 CLK_SET_RATE_PARENT, 2, 1);
1183 clk = tegra_clk_register_divider("audio2_div", "audio2_doubler",
1184 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 26, 1, 0,
1185 &clk_doubler_lock);
1186 clk = tegra_clk_register_periph_gate("audio2_2x", "audio2_div",
1187 TEGRA_PERIPH_NO_RESET, clk_base,
1188 CLK_SET_RATE_PARENT, 115, &periph_v_regs,
1189 periph_clk_enb_refcnt);
1190 clk_register_clkdev(clk, "audio2_2x", NULL);
1191 clks[audio2_2x] = clk;
1192
1193 /* audio3_2x */
1194 clk = clk_register_fixed_factor(NULL, "audio3_doubler", "audio3",
1195 CLK_SET_RATE_PARENT, 2, 1);
1196 clk = tegra_clk_register_divider("audio3_div", "audio3_doubler",
1197 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 27, 1, 0,
1198 &clk_doubler_lock);
1199 clk = tegra_clk_register_periph_gate("audio3_2x", "audio3_div",
1200 TEGRA_PERIPH_NO_RESET, clk_base,
1201 CLK_SET_RATE_PARENT, 116, &periph_v_regs,
1202 periph_clk_enb_refcnt);
1203 clk_register_clkdev(clk, "audio3_2x", NULL);
1204 clks[audio3_2x] = clk;
1205
1206 /* audio4_2x */
1207 clk = clk_register_fixed_factor(NULL, "audio4_doubler", "audio4",
1208 CLK_SET_RATE_PARENT, 2, 1);
1209 clk = tegra_clk_register_divider("audio4_div", "audio4_doubler",
1210 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 28, 1, 0,
1211 &clk_doubler_lock);
1212 clk = tegra_clk_register_periph_gate("audio4_2x", "audio4_div",
1213 TEGRA_PERIPH_NO_RESET, clk_base,
1214 CLK_SET_RATE_PARENT, 117, &periph_v_regs,
1215 periph_clk_enb_refcnt);
1216 clk_register_clkdev(clk, "audio4_2x", NULL);
1217 clks[audio4_2x] = clk;
1218
1219 /* spdif_2x */
1220 clk = clk_register_fixed_factor(NULL, "spdif_doubler", "spdif",
1221 CLK_SET_RATE_PARENT, 2, 1);
1222 clk = tegra_clk_register_divider("spdif_div", "spdif_doubler",
1223 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 29, 1, 0,
1224 &clk_doubler_lock);
1225 clk = tegra_clk_register_periph_gate("spdif_2x", "spdif_div",
1226 TEGRA_PERIPH_NO_RESET, clk_base,
1227 CLK_SET_RATE_PARENT, 118, &periph_v_regs,
1228 periph_clk_enb_refcnt);
1229 clk_register_clkdev(clk, "spdif_2x", NULL);
1230 clks[spdif_2x] = clk;
1231}
1232
1233static void __init tegra30_pmc_clk_init(void)
1234{
1235 struct clk *clk;
1236
1237 /* clk_out_1 */
1238 clk = clk_register_mux(NULL, "clk_out_1_mux", clk_out1_parents,
1239 ARRAY_SIZE(clk_out1_parents),
1240 CLK_SET_RATE_NO_REPARENT,
1241 pmc_base + PMC_CLK_OUT_CNTRL, 6, 3, 0,
1242 &clk_out_lock);
1243 clks[clk_out_1_mux] = clk;
1244 clk = clk_register_gate(NULL, "clk_out_1", "clk_out_1_mux", 0,
1245 pmc_base + PMC_CLK_OUT_CNTRL, 2, 0,
1246 &clk_out_lock);
1247 clk_register_clkdev(clk, "extern1", "clk_out_1");
1248 clks[clk_out_1] = clk;
1249
1250 /* clk_out_2 */
1251 clk = clk_register_mux(NULL, "clk_out_2_mux", clk_out2_parents,
1252 ARRAY_SIZE(clk_out2_parents),
1253 CLK_SET_RATE_NO_REPARENT,
1254 pmc_base + PMC_CLK_OUT_CNTRL, 14, 3, 0,
1255 &clk_out_lock);
1256 clk = clk_register_gate(NULL, "clk_out_2", "clk_out_2_mux", 0,
1257 pmc_base + PMC_CLK_OUT_CNTRL, 10, 0,
1258 &clk_out_lock);
1259 clk_register_clkdev(clk, "extern2", "clk_out_2");
1260 clks[clk_out_2] = clk;
1261
1262 /* clk_out_3 */
1263 clk = clk_register_mux(NULL, "clk_out_3_mux", clk_out3_parents,
1264 ARRAY_SIZE(clk_out3_parents),
1265 CLK_SET_RATE_NO_REPARENT,
1266 pmc_base + PMC_CLK_OUT_CNTRL, 22, 3, 0,
1267 &clk_out_lock);
1268 clk = clk_register_gate(NULL, "clk_out_3", "clk_out_3_mux", 0,
1269 pmc_base + PMC_CLK_OUT_CNTRL, 18, 0,
1270 &clk_out_lock);
1271 clk_register_clkdev(clk, "extern3", "clk_out_3");
1272 clks[clk_out_3] = clk;
1273
1274 /* blink */
1275 writel_relaxed(0, pmc_base + PMC_BLINK_TIMER);
1276 clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0,
1277 pmc_base + PMC_DPD_PADS_ORIDE,
1278 PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL);
1279 clk = clk_register_gate(NULL, "blink", "blink_override", 0,
1280 pmc_base + PMC_CTRL,
1281 PMC_CTRL_BLINK_ENB, 0, NULL);
1282 clk_register_clkdev(clk, "blink", NULL);
1283 clks[blink] = clk;
1284
1285} 997}
1286 998
1287static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", 999static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
@@ -1332,8 +1044,7 @@ static void __init tegra30_super_clk_init(void)
1332 CLK_SET_RATE_PARENT, 1044 CLK_SET_RATE_PARENT,
1333 clk_base + CCLKG_BURST_POLICY, 1045 clk_base + CCLKG_BURST_POLICY,
1334 0, 4, 0, 0, NULL); 1046 0, 4, 0, 0, NULL);
1335 clk_register_clkdev(clk, "cclk_g", NULL); 1047 clks[TEGRA30_CLK_CCLK_G] = clk;
1336 clks[cclk_g] = clk;
1337 1048
1338 /* 1049 /*
1339 * Clock input to cclk_lp divided from pll_p using 1050 * Clock input to cclk_lp divided from pll_p using
@@ -1369,8 +1080,7 @@ static void __init tegra30_super_clk_init(void)
1369 clk_base + CCLKLP_BURST_POLICY, 1080 clk_base + CCLKLP_BURST_POLICY,
1370 TEGRA_DIVIDER_2, 4, 8, 9, 1081 TEGRA_DIVIDER_2, 4, 8, 9,
1371 NULL); 1082 NULL);
1372 clk_register_clkdev(clk, "cclk_lp", NULL); 1083 clks[TEGRA30_CLK_CCLK_LP] = clk;
1373 clks[cclk_lp] = clk;
1374 1084
1375 /* SCLK */ 1085 /* SCLK */
1376 clk = tegra_clk_register_super_mux("sclk", sclk_parents, 1086 clk = tegra_clk_register_super_mux("sclk", sclk_parents,
@@ -1378,142 +1088,44 @@ static void __init tegra30_super_clk_init(void)
1378 CLK_SET_RATE_PARENT, 1088 CLK_SET_RATE_PARENT,
1379 clk_base + SCLK_BURST_POLICY, 1089 clk_base + SCLK_BURST_POLICY,
1380 0, 4, 0, 0, NULL); 1090 0, 4, 0, 0, NULL);
1381 clk_register_clkdev(clk, "sclk", NULL); 1091 clks[TEGRA30_CLK_SCLK] = clk;
1382 clks[sclk] = clk;
1383
1384 /* HCLK */
1385 clk = clk_register_divider(NULL, "hclk_div", "sclk", 0,
1386 clk_base + SYSTEM_CLK_RATE, 4, 2, 0,
1387 &sysrate_lock);
1388 clk = clk_register_gate(NULL, "hclk", "hclk_div", CLK_SET_RATE_PARENT,
1389 clk_base + SYSTEM_CLK_RATE, 7,
1390 CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
1391 clk_register_clkdev(clk, "hclk", NULL);
1392 clks[hclk] = clk;
1393
1394 /* PCLK */
1395 clk = clk_register_divider(NULL, "pclk_div", "hclk", 0,
1396 clk_base + SYSTEM_CLK_RATE, 0, 2, 0,
1397 &sysrate_lock);
1398 clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT,
1399 clk_base + SYSTEM_CLK_RATE, 3,
1400 CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
1401 clk_register_clkdev(clk, "pclk", NULL);
1402 clks[pclk] = clk;
1403 1092
1404 /* twd */ 1093 /* twd */
1405 clk = clk_register_fixed_factor(NULL, "twd", "cclk_g", 1094 clk = clk_register_fixed_factor(NULL, "twd", "cclk_g",
1406 CLK_SET_RATE_PARENT, 1, 2); 1095 CLK_SET_RATE_PARENT, 1, 2);
1407 clk_register_clkdev(clk, "twd", NULL); 1096 clks[TEGRA30_CLK_TWD] = clk;
1408 clks[twd] = clk; 1097
1098 tegra_super_clk_gen4_init(clk_base, pmc_base, tegra30_clks, NULL);
1409} 1099}
1410 1100
1411static const char *mux_pllacp_clkm[] = { "pll_a_out0", "unused", "pll_p", 1101static const char *mux_pllacp_clkm[] = { "pll_a_out0", "unused", "pll_p",
1412 "clk_m" }; 1102 "clk_m" };
1413static const char *mux_pllpcm_clkm[] = { "pll_p", "pll_c", "pll_m", "clk_m" }; 1103static const char *mux_pllpcm_clkm[] = { "pll_p", "pll_c", "pll_m", "clk_m" };
1414static const char *mux_pllmcp_clkm[] = { "pll_m", "pll_c", "pll_p", "clk_m" }; 1104static const char *mux_pllmcp_clkm[] = { "pll_m", "pll_c", "pll_p", "clk_m" };
1415static const char *i2s0_parents[] = { "pll_a_out0", "audio0_2x", "pll_p",
1416 "clk_m" };
1417static const char *i2s1_parents[] = { "pll_a_out0", "audio1_2x", "pll_p",
1418 "clk_m" };
1419static const char *i2s2_parents[] = { "pll_a_out0", "audio2_2x", "pll_p",
1420 "clk_m" };
1421static const char *i2s3_parents[] = { "pll_a_out0", "audio3_2x", "pll_p",
1422 "clk_m" };
1423static const char *i2s4_parents[] = { "pll_a_out0", "audio4_2x", "pll_p",
1424 "clk_m" };
1425static const char *spdif_out_parents[] = { "pll_a_out0", "spdif_2x", "pll_p", 1105static const char *spdif_out_parents[] = { "pll_a_out0", "spdif_2x", "pll_p",
1426 "clk_m" }; 1106 "clk_m" };
1427static const char *spdif_in_parents[] = { "pll_p", "pll_c", "pll_m" };
1428static const char *mux_pllpc_clk32k_clkm[] = { "pll_p", "pll_c", "clk_32k",
1429 "clk_m" };
1430static const char *mux_pllpc_clkm_clk32k[] = { "pll_p", "pll_c", "clk_m",
1431 "clk_32k" };
1432static const char *mux_pllmcpa[] = { "pll_m", "pll_c", "pll_p", "pll_a_out0" }; 1107static const char *mux_pllmcpa[] = { "pll_m", "pll_c", "pll_p", "pll_a_out0" };
1433static const char *mux_pllpdc_clkm[] = { "pll_p", "pll_d_out0", "pll_c",
1434 "clk_m" };
1435static const char *mux_pllp_clkm[] = { "pll_p", "unused", "unused", "clk_m" };
1436static const char *mux_pllpmdacd2_clkm[] = { "pll_p", "pll_m", "pll_d_out0", 1108static const char *mux_pllpmdacd2_clkm[] = { "pll_p", "pll_m", "pll_d_out0",
1437 "pll_a_out0", "pll_c", 1109 "pll_a_out0", "pll_c",
1438 "pll_d2_out0", "clk_m" }; 1110 "pll_d2_out0", "clk_m" };
1439static const char *mux_plla_clk32k_pllp_clkm_plle[] = { "pll_a_out0",
1440 "clk_32k", "pll_p",
1441 "clk_m", "pll_e" };
1442static const char *mux_plld_out0_plld2_out0[] = { "pll_d_out0", 1111static const char *mux_plld_out0_plld2_out0[] = { "pll_d_out0",
1443 "pll_d2_out0" }; 1112 "pll_d2_out0" };
1113static const char *pwm_parents[] = { "pll_p", "pll_c", "clk_32k", "clk_m" };
1444 1114
1445static struct tegra_periph_init_data tegra_periph_clk_list[] = { 1115static struct tegra_periph_init_data tegra_periph_clk_list[] = {
1446 TEGRA_INIT_DATA_MUX("i2s0", NULL, "tegra30-i2s.0", i2s0_parents, CLK_SOURCE_I2S0, 30, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s0), 1116 TEGRA_INIT_DATA_MUX("spdif_out", spdif_out_parents, CLK_SOURCE_SPDIF_OUT, 10, TEGRA_PERIPH_ON_APB, TEGRA30_CLK_SPDIF_OUT),
1447 TEGRA_INIT_DATA_MUX("i2s1", NULL, "tegra30-i2s.1", i2s1_parents, CLK_SOURCE_I2S1, 11, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s1), 1117 TEGRA_INIT_DATA_MUX("d_audio", mux_pllacp_clkm, CLK_SOURCE_D_AUDIO, 106, 0, TEGRA30_CLK_D_AUDIO),
1448 TEGRA_INIT_DATA_MUX("i2s2", NULL, "tegra30-i2s.2", i2s2_parents, CLK_SOURCE_I2S2, 18, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s2), 1118 TEGRA_INIT_DATA_MUX("dam0", mux_pllacp_clkm, CLK_SOURCE_DAM0, 108, 0, TEGRA30_CLK_DAM0),
1449 TEGRA_INIT_DATA_MUX("i2s3", NULL, "tegra30-i2s.3", i2s3_parents, CLK_SOURCE_I2S3, 101, &periph_v_regs, TEGRA_PERIPH_ON_APB, i2s3), 1119 TEGRA_INIT_DATA_MUX("dam1", mux_pllacp_clkm, CLK_SOURCE_DAM1, 109, 0, TEGRA30_CLK_DAM1),
1450 TEGRA_INIT_DATA_MUX("i2s4", NULL, "tegra30-i2s.4", i2s4_parents, CLK_SOURCE_I2S4, 102, &periph_v_regs, TEGRA_PERIPH_ON_APB, i2s4), 1120 TEGRA_INIT_DATA_MUX("dam2", mux_pllacp_clkm, CLK_SOURCE_DAM2, 110, 0, TEGRA30_CLK_DAM2),
1451 TEGRA_INIT_DATA_MUX("spdif_out", "spdif_out", "tegra30-spdif", spdif_out_parents, CLK_SOURCE_SPDIF_OUT, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_out), 1121 TEGRA_INIT_DATA_INT("3d2", mux_pllmcpa, CLK_SOURCE_3D2, 98, TEGRA_PERIPH_MANUAL_RESET, TEGRA30_CLK_GR3D2),
1452 TEGRA_INIT_DATA_MUX("spdif_in", "spdif_in", "tegra30-spdif", spdif_in_parents, CLK_SOURCE_SPDIF_IN, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_in), 1122 TEGRA_INIT_DATA_INT("se", mux_pllpcm_clkm, CLK_SOURCE_SE, 127, 0, TEGRA30_CLK_SE),
1453 TEGRA_INIT_DATA_MUX("d_audio", "d_audio", "tegra30-ahub", mux_pllacp_clkm, CLK_SOURCE_D_AUDIO, 106, &periph_v_regs, 0, d_audio), 1123 TEGRA_INIT_DATA_MUX8("hdmi", mux_pllpmdacd2_clkm, CLK_SOURCE_HDMI, 51, 0, TEGRA30_CLK_HDMI),
1454 TEGRA_INIT_DATA_MUX("dam0", NULL, "tegra30-dam.0", mux_pllacp_clkm, CLK_SOURCE_DAM0, 108, &periph_v_regs, 0, dam0), 1124 TEGRA_INIT_DATA("pwm", NULL, NULL, pwm_parents, CLK_SOURCE_PWM, 28, 2, 0, 0, 8, 1, 0, 17, TEGRA_PERIPH_ON_APB, TEGRA30_CLK_PWM),
1455 TEGRA_INIT_DATA_MUX("dam1", NULL, "tegra30-dam.1", mux_pllacp_clkm, CLK_SOURCE_DAM1, 109, &periph_v_regs, 0, dam1),
1456 TEGRA_INIT_DATA_MUX("dam2", NULL, "tegra30-dam.2", mux_pllacp_clkm, CLK_SOURCE_DAM2, 110, &periph_v_regs, 0, dam2),
1457 TEGRA_INIT_DATA_MUX("hda", "hda", "tegra30-hda", mux_pllpcm_clkm, CLK_SOURCE_HDA, 125, &periph_v_regs, 0, hda),
1458 TEGRA_INIT_DATA_MUX("hda2codec_2x", "hda2codec", "tegra30-hda", mux_pllpcm_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, &periph_v_regs, 0, hda2codec_2x),
1459 TEGRA_INIT_DATA_MUX("sbc1", NULL, "spi_tegra.0", mux_pllpcm_clkm, CLK_SOURCE_SBC1, 41, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc1),
1460 TEGRA_INIT_DATA_MUX("sbc2", NULL, "spi_tegra.1", mux_pllpcm_clkm, CLK_SOURCE_SBC2, 44, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc2),
1461 TEGRA_INIT_DATA_MUX("sbc3", NULL, "spi_tegra.2", mux_pllpcm_clkm, CLK_SOURCE_SBC3, 46, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc3),
1462 TEGRA_INIT_DATA_MUX("sbc4", NULL, "spi_tegra.3", mux_pllpcm_clkm, CLK_SOURCE_SBC4, 68, &periph_u_regs, TEGRA_PERIPH_ON_APB, sbc4),
1463 TEGRA_INIT_DATA_MUX("sbc5", NULL, "spi_tegra.4", mux_pllpcm_clkm, CLK_SOURCE_SBC5, 104, &periph_v_regs, TEGRA_PERIPH_ON_APB, sbc5),
1464 TEGRA_INIT_DATA_MUX("sbc6", NULL, "spi_tegra.5", mux_pllpcm_clkm, CLK_SOURCE_SBC6, 105, &periph_v_regs, TEGRA_PERIPH_ON_APB, sbc6),
1465 TEGRA_INIT_DATA_MUX("sata_oob", NULL, "tegra_sata_oob", mux_pllpcm_clkm, CLK_SOURCE_SATA_OOB, 123, &periph_v_regs, TEGRA_PERIPH_ON_APB, sata_oob),
1466 TEGRA_INIT_DATA_MUX("sata", NULL, "tegra_sata", mux_pllpcm_clkm, CLK_SOURCE_SATA, 124, &periph_v_regs, TEGRA_PERIPH_ON_APB, sata),
1467 TEGRA_INIT_DATA_MUX("ndflash", NULL, "tegra_nand", mux_pllpcm_clkm, CLK_SOURCE_NDFLASH, 13, &periph_l_regs, TEGRA_PERIPH_ON_APB, ndflash),
1468 TEGRA_INIT_DATA_MUX("ndspeed", NULL, "tegra_nand_speed", mux_pllpcm_clkm, CLK_SOURCE_NDSPEED, 80, &periph_u_regs, TEGRA_PERIPH_ON_APB, ndspeed),
1469 TEGRA_INIT_DATA_MUX("vfir", NULL, "vfir", mux_pllpcm_clkm, CLK_SOURCE_VFIR, 7, &periph_l_regs, TEGRA_PERIPH_ON_APB, vfir),
1470 TEGRA_INIT_DATA_MUX("csite", NULL, "csite", mux_pllpcm_clkm, CLK_SOURCE_CSITE, 73, &periph_u_regs, TEGRA_PERIPH_ON_APB, csite),
1471 TEGRA_INIT_DATA_MUX("la", NULL, "la", mux_pllpcm_clkm, CLK_SOURCE_LA, 76, &periph_u_regs, TEGRA_PERIPH_ON_APB, la),
1472 TEGRA_INIT_DATA_MUX("owr", NULL, "tegra_w1", mux_pllpcm_clkm, CLK_SOURCE_OWR, 71, &periph_u_regs, TEGRA_PERIPH_ON_APB, owr),
1473 TEGRA_INIT_DATA_MUX("mipi", NULL, "mipi", mux_pllpcm_clkm, CLK_SOURCE_MIPI, 50, &periph_h_regs, TEGRA_PERIPH_ON_APB, mipi),
1474 TEGRA_INIT_DATA_MUX("tsensor", NULL, "tegra-tsensor", mux_pllpc_clkm_clk32k, CLK_SOURCE_TSENSOR, 100, &periph_v_regs, TEGRA_PERIPH_ON_APB, tsensor),
1475 TEGRA_INIT_DATA_MUX("i2cslow", NULL, "i2cslow", mux_pllpc_clk32k_clkm, CLK_SOURCE_I2CSLOW, 81, &periph_u_regs, TEGRA_PERIPH_ON_APB, i2cslow),
1476 TEGRA_INIT_DATA_INT("vde", NULL, "vde", mux_pllpcm_clkm, CLK_SOURCE_VDE, 61, &periph_h_regs, 0, vde),
1477 TEGRA_INIT_DATA_INT("vi", "vi", "tegra_camera", mux_pllmcpa, CLK_SOURCE_VI, 20, &periph_l_regs, 0, vi),
1478 TEGRA_INIT_DATA_INT("epp", NULL, "epp", mux_pllmcpa, CLK_SOURCE_EPP, 19, &periph_l_regs, 0, epp),
1479 TEGRA_INIT_DATA_INT("mpe", NULL, "mpe", mux_pllmcpa, CLK_SOURCE_MPE, 60, &periph_h_regs, 0, mpe),
1480 TEGRA_INIT_DATA_INT("host1x", NULL, "host1x", mux_pllmcpa, CLK_SOURCE_HOST1X, 28, &periph_l_regs, 0, host1x),
1481 TEGRA_INIT_DATA_INT("3d", NULL, "3d", mux_pllmcpa, CLK_SOURCE_3D, 24, &periph_l_regs, TEGRA_PERIPH_MANUAL_RESET, gr3d),
1482 TEGRA_INIT_DATA_INT("3d2", NULL, "3d2", mux_pllmcpa, CLK_SOURCE_3D2, 98, &periph_v_regs, TEGRA_PERIPH_MANUAL_RESET, gr3d2),
1483 TEGRA_INIT_DATA_INT("2d", NULL, "2d", mux_pllmcpa, CLK_SOURCE_2D, 21, &periph_l_regs, 0, gr2d),
1484 TEGRA_INIT_DATA_INT("se", NULL, "se", mux_pllpcm_clkm, CLK_SOURCE_SE, 127, &periph_v_regs, 0, se),
1485 TEGRA_INIT_DATA_MUX("mselect", NULL, "mselect", mux_pllp_clkm, CLK_SOURCE_MSELECT, 99, &periph_v_regs, 0, mselect),
1486 TEGRA_INIT_DATA_MUX("nor", NULL, "tegra-nor", mux_pllpcm_clkm, CLK_SOURCE_NOR, 42, &periph_h_regs, 0, nor),
1487 TEGRA_INIT_DATA_MUX("sdmmc1", NULL, "sdhci-tegra.0", mux_pllpcm_clkm, CLK_SOURCE_SDMMC1, 14, &periph_l_regs, 0, sdmmc1),
1488 TEGRA_INIT_DATA_MUX("sdmmc2", NULL, "sdhci-tegra.1", mux_pllpcm_clkm, CLK_SOURCE_SDMMC2, 9, &periph_l_regs, 0, sdmmc2),
1489 TEGRA_INIT_DATA_MUX("sdmmc3", NULL, "sdhci-tegra.2", mux_pllpcm_clkm, CLK_SOURCE_SDMMC3, 69, &periph_u_regs, 0, sdmmc3),
1490 TEGRA_INIT_DATA_MUX("sdmmc4", NULL, "sdhci-tegra.3", mux_pllpcm_clkm, CLK_SOURCE_SDMMC4, 15, &periph_l_regs, 0, sdmmc4),
1491 TEGRA_INIT_DATA_MUX("cve", NULL, "cve", mux_pllpdc_clkm, CLK_SOURCE_CVE, 49, &periph_h_regs, 0, cve),
1492 TEGRA_INIT_DATA_MUX("tvo", NULL, "tvo", mux_pllpdc_clkm, CLK_SOURCE_TVO, 49, &periph_h_regs, 0, tvo),
1493 TEGRA_INIT_DATA_MUX("tvdac", NULL, "tvdac", mux_pllpdc_clkm, CLK_SOURCE_TVDAC, 53, &periph_h_regs, 0, tvdac),
1494 TEGRA_INIT_DATA_MUX("actmon", NULL, "actmon", mux_pllpc_clk32k_clkm, CLK_SOURCE_ACTMON, 119, &periph_v_regs, 0, actmon),
1495 TEGRA_INIT_DATA_MUX("vi_sensor", "vi_sensor", "tegra_camera", mux_pllmcpa, CLK_SOURCE_VI_SENSOR, 20, &periph_l_regs, TEGRA_PERIPH_NO_RESET, vi_sensor),
1496 TEGRA_INIT_DATA_DIV16("i2c1", "div-clk", "tegra-i2c.0", mux_pllp_clkm, CLK_SOURCE_I2C1, 12, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2c1),
1497 TEGRA_INIT_DATA_DIV16("i2c2", "div-clk", "tegra-i2c.1", mux_pllp_clkm, CLK_SOURCE_I2C2, 54, &periph_h_regs, TEGRA_PERIPH_ON_APB, i2c2),
1498 TEGRA_INIT_DATA_DIV16("i2c3", "div-clk", "tegra-i2c.2", mux_pllp_clkm, CLK_SOURCE_I2C3, 67, &periph_u_regs, TEGRA_PERIPH_ON_APB, i2c3),
1499 TEGRA_INIT_DATA_DIV16("i2c4", "div-clk", "tegra-i2c.3", mux_pllp_clkm, CLK_SOURCE_I2C4, 103, &periph_v_regs, TEGRA_PERIPH_ON_APB, i2c4),
1500 TEGRA_INIT_DATA_DIV16("i2c5", "div-clk", "tegra-i2c.4", mux_pllp_clkm, CLK_SOURCE_I2C5, 47, &periph_h_regs, TEGRA_PERIPH_ON_APB, i2c5),
1501 TEGRA_INIT_DATA_UART("uarta", NULL, "tegra_uart.0", mux_pllpcm_clkm, CLK_SOURCE_UARTA, 6, &periph_l_regs, uarta),
1502 TEGRA_INIT_DATA_UART("uartb", NULL, "tegra_uart.1", mux_pllpcm_clkm, CLK_SOURCE_UARTB, 7, &periph_l_regs, uartb),
1503 TEGRA_INIT_DATA_UART("uartc", NULL, "tegra_uart.2", mux_pllpcm_clkm, CLK_SOURCE_UARTC, 55, &periph_h_regs, uartc),
1504 TEGRA_INIT_DATA_UART("uartd", NULL, "tegra_uart.3", mux_pllpcm_clkm, CLK_SOURCE_UARTD, 65, &periph_u_regs, uartd),
1505 TEGRA_INIT_DATA_UART("uarte", NULL, "tegra_uart.4", mux_pllpcm_clkm, CLK_SOURCE_UARTE, 66, &periph_u_regs, uarte),
1506 TEGRA_INIT_DATA_MUX8("hdmi", NULL, "hdmi", mux_pllpmdacd2_clkm, CLK_SOURCE_HDMI, 51, &periph_h_regs, 0, hdmi),
1507 TEGRA_INIT_DATA_MUX8("extern1", NULL, "extern1", mux_plla_clk32k_pllp_clkm_plle, CLK_SOURCE_EXTERN1, 120, &periph_v_regs, 0, extern1),
1508 TEGRA_INIT_DATA_MUX8("extern2", NULL, "extern2", mux_plla_clk32k_pllp_clkm_plle, CLK_SOURCE_EXTERN2, 121, &periph_v_regs, 0, extern2),
1509 TEGRA_INIT_DATA_MUX8("extern3", NULL, "extern3", mux_plla_clk32k_pllp_clkm_plle, CLK_SOURCE_EXTERN3, 122, &periph_v_regs, 0, extern3),
1510 TEGRA_INIT_DATA("pwm", NULL, "pwm", mux_pllpc_clk32k_clkm, CLK_SOURCE_PWM, 28, 2, 0, 0, 8, 1, 0, &periph_l_regs, 17, periph_clk_enb_refcnt, 0, pwm),
1511}; 1125};
1512 1126
1513static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = { 1127static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = {
1514 TEGRA_INIT_DATA_NODIV("disp1", NULL, "tegradc.0", mux_pllpmdacd2_clkm, CLK_SOURCE_DISP1, 29, 3, 27, &periph_l_regs, 0, disp1), 1128 TEGRA_INIT_DATA_NODIV("dsib", mux_plld_out0_plld2_out0, CLK_SOURCE_DSIB, 25, 1, 82, 0, TEGRA30_CLK_DSIB),
1515 TEGRA_INIT_DATA_NODIV("disp2", NULL, "tegradc.1", mux_pllpmdacd2_clkm, CLK_SOURCE_DISP2, 29, 3, 26, &periph_l_regs, 0, disp2),
1516 TEGRA_INIT_DATA_NODIV("dsib", NULL, "tegradc.1", mux_plld_out0_plld2_out0, CLK_SOURCE_DSIB, 25, 1, 82, &periph_u_regs, 0, dsib),
1517}; 1129};
1518 1130
1519static void __init tegra30_periph_clk_init(void) 1131static void __init tegra30_periph_clk_init(void)
@@ -1522,170 +1134,20 @@ static void __init tegra30_periph_clk_init(void)
1522 struct clk *clk; 1134 struct clk *clk;
1523 int i; 1135 int i;
1524 1136
1525 /* apbdma */
1526 clk = tegra_clk_register_periph_gate("apbdma", "clk_m", 0, clk_base, 0, 34,
1527 &periph_h_regs, periph_clk_enb_refcnt);
1528 clk_register_clkdev(clk, NULL, "tegra-apbdma");
1529 clks[apbdma] = clk;
1530
1531 /* rtc */
1532 clk = tegra_clk_register_periph_gate("rtc", "clk_32k",
1533 TEGRA_PERIPH_NO_RESET | TEGRA_PERIPH_ON_APB,
1534 clk_base, 0, 4, &periph_l_regs,
1535 periph_clk_enb_refcnt);
1536 clk_register_clkdev(clk, NULL, "rtc-tegra");
1537 clks[rtc] = clk;
1538
1539 /* timer */
1540 clk = tegra_clk_register_periph_gate("timer", "clk_m", 0, clk_base, 0,
1541 5, &periph_l_regs, periph_clk_enb_refcnt);
1542 clk_register_clkdev(clk, NULL, "timer");
1543 clks[timer] = clk;
1544
1545 /* kbc */
1546 clk = tegra_clk_register_periph_gate("kbc", "clk_32k",
1547 TEGRA_PERIPH_NO_RESET | TEGRA_PERIPH_ON_APB,
1548 clk_base, 0, 36, &periph_h_regs,
1549 periph_clk_enb_refcnt);
1550 clk_register_clkdev(clk, NULL, "tegra-kbc");
1551 clks[kbc] = clk;
1552
1553 /* csus */
1554 clk = tegra_clk_register_periph_gate("csus", "clk_m",
1555 TEGRA_PERIPH_NO_RESET | TEGRA_PERIPH_ON_APB,
1556 clk_base, 0, 92, &periph_u_regs,
1557 periph_clk_enb_refcnt);
1558 clk_register_clkdev(clk, "csus", "tengra_camera");
1559 clks[csus] = clk;
1560
1561 /* vcp */
1562 clk = tegra_clk_register_periph_gate("vcp", "clk_m", 0, clk_base, 0, 29,
1563 &periph_l_regs, periph_clk_enb_refcnt);
1564 clk_register_clkdev(clk, "vcp", "tegra-avp");
1565 clks[vcp] = clk;
1566
1567 /* bsea */
1568 clk = tegra_clk_register_periph_gate("bsea", "clk_m", 0, clk_base, 0,
1569 62, &periph_h_regs, periph_clk_enb_refcnt);
1570 clk_register_clkdev(clk, "bsea", "tegra-avp");
1571 clks[bsea] = clk;
1572
1573 /* bsev */
1574 clk = tegra_clk_register_periph_gate("bsev", "clk_m", 0, clk_base, 0,
1575 63, &periph_h_regs, periph_clk_enb_refcnt);
1576 clk_register_clkdev(clk, "bsev", "tegra-aes");
1577 clks[bsev] = clk;
1578
1579 /* usbd */
1580 clk = tegra_clk_register_periph_gate("usbd", "clk_m", 0, clk_base, 0,
1581 22, &periph_l_regs, periph_clk_enb_refcnt);
1582 clk_register_clkdev(clk, NULL, "fsl-tegra-udc");
1583 clks[usbd] = clk;
1584
1585 /* usb2 */
1586 clk = tegra_clk_register_periph_gate("usb2", "clk_m", 0, clk_base, 0,
1587 58, &periph_h_regs, periph_clk_enb_refcnt);
1588 clk_register_clkdev(clk, NULL, "tegra-ehci.1");
1589 clks[usb2] = clk;
1590
1591 /* usb3 */
1592 clk = tegra_clk_register_periph_gate("usb3", "clk_m", 0, clk_base, 0,
1593 59, &periph_h_regs, periph_clk_enb_refcnt);
1594 clk_register_clkdev(clk, NULL, "tegra-ehci.2");
1595 clks[usb3] = clk;
1596
1597 /* dsia */ 1137 /* dsia */
1598 clk = tegra_clk_register_periph_gate("dsia", "pll_d_out0", 0, clk_base, 1138 clk = tegra_clk_register_periph_gate("dsia", "pll_d_out0", 0, clk_base,
1599 0, 48, &periph_h_regs, 1139 0, 48, periph_clk_enb_refcnt);
1600 periph_clk_enb_refcnt); 1140 clks[TEGRA30_CLK_DSIA] = clk;
1601 clk_register_clkdev(clk, "dsia", "tegradc.0");
1602 clks[dsia] = clk;
1603
1604 /* csi */
1605 clk = tegra_clk_register_periph_gate("csi", "pll_p_out3", 0, clk_base,
1606 0, 52, &periph_h_regs,
1607 periph_clk_enb_refcnt);
1608 clk_register_clkdev(clk, "csi", "tegra_camera");
1609 clks[csi] = clk;
1610
1611 /* isp */
1612 clk = tegra_clk_register_periph_gate("isp", "clk_m", 0, clk_base, 0, 23,
1613 &periph_l_regs, periph_clk_enb_refcnt);
1614 clk_register_clkdev(clk, "isp", "tegra_camera");
1615 clks[isp] = clk;
1616 1141
1617 /* pcie */ 1142 /* pcie */
1618 clk = tegra_clk_register_periph_gate("pcie", "clk_m", 0, clk_base, 0, 1143 clk = tegra_clk_register_periph_gate("pcie", "clk_m", 0, clk_base, 0,
1619 70, &periph_u_regs, periph_clk_enb_refcnt); 1144 70, periph_clk_enb_refcnt);
1620 clk_register_clkdev(clk, "pcie", "tegra-pcie"); 1145 clks[TEGRA30_CLK_PCIE] = clk;
1621 clks[pcie] = clk;
1622 1146
1623 /* afi */ 1147 /* afi */
1624 clk = tegra_clk_register_periph_gate("afi", "clk_m", 0, clk_base, 0, 72, 1148 clk = tegra_clk_register_periph_gate("afi", "clk_m", 0, clk_base, 0, 72,
1625 &periph_u_regs, periph_clk_enb_refcnt);
1626 clk_register_clkdev(clk, "afi", "tegra-pcie");
1627 clks[afi] = clk;
1628
1629 /* pciex */
1630 clk = tegra_clk_register_periph_gate("pciex", "pll_e", 0, clk_base, 0,
1631 74, &periph_u_regs, periph_clk_enb_refcnt);
1632 clk_register_clkdev(clk, "pciex", "tegra-pcie");
1633 clks[pciex] = clk;
1634
1635 /* kfuse */
1636 clk = tegra_clk_register_periph_gate("kfuse", "clk_m",
1637 TEGRA_PERIPH_ON_APB,
1638 clk_base, 0, 40, &periph_h_regs,
1639 periph_clk_enb_refcnt);
1640 clk_register_clkdev(clk, NULL, "kfuse-tegra");
1641 clks[kfuse] = clk;
1642
1643 /* fuse */
1644 clk = tegra_clk_register_periph_gate("fuse", "clk_m",
1645 TEGRA_PERIPH_ON_APB,
1646 clk_base, 0, 39, &periph_h_regs,
1647 periph_clk_enb_refcnt);
1648 clk_register_clkdev(clk, "fuse", "fuse-tegra");
1649 clks[fuse] = clk;
1650
1651 /* fuse_burn */
1652 clk = tegra_clk_register_periph_gate("fuse_burn", "clk_m",
1653 TEGRA_PERIPH_ON_APB,
1654 clk_base, 0, 39, &periph_h_regs,
1655 periph_clk_enb_refcnt); 1149 periph_clk_enb_refcnt);
1656 clk_register_clkdev(clk, "fuse_burn", "fuse-tegra"); 1150 clks[TEGRA30_CLK_AFI] = clk;
1657 clks[fuse_burn] = clk;
1658
1659 /* apbif */
1660 clk = tegra_clk_register_periph_gate("apbif", "clk_m", 0,
1661 clk_base, 0, 107, &periph_v_regs,
1662 periph_clk_enb_refcnt);
1663 clk_register_clkdev(clk, "apbif", "tegra30-ahub");
1664 clks[apbif] = clk;
1665
1666 /* hda2hdmi */
1667 clk = tegra_clk_register_periph_gate("hda2hdmi", "clk_m",
1668 TEGRA_PERIPH_ON_APB,
1669 clk_base, 0, 128, &periph_w_regs,
1670 periph_clk_enb_refcnt);
1671 clk_register_clkdev(clk, "hda2hdmi", "tegra30-hda");
1672 clks[hda2hdmi] = clk;
1673
1674 /* sata_cold */
1675 clk = tegra_clk_register_periph_gate("sata_cold", "clk_m",
1676 TEGRA_PERIPH_ON_APB,
1677 clk_base, 0, 129, &periph_w_regs,
1678 periph_clk_enb_refcnt);
1679 clk_register_clkdev(clk, NULL, "tegra_sata_cold");
1680 clks[sata_cold] = clk;
1681
1682 /* dtv */
1683 clk = tegra_clk_register_periph_gate("dtv", "clk_m",
1684 TEGRA_PERIPH_ON_APB,
1685 clk_base, 0, 79, &periph_u_regs,
1686 periph_clk_enb_refcnt);
1687 clk_register_clkdev(clk, NULL, "dtv");
1688 clks[dtv] = clk;
1689 1151
1690 /* emc */ 1152 /* emc */
1691 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, 1153 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
@@ -1694,84 +1156,37 @@ static void __init tegra30_periph_clk_init(void)
1694 clk_base + CLK_SOURCE_EMC, 1156 clk_base + CLK_SOURCE_EMC,
1695 30, 2, 0, NULL); 1157 30, 2, 0, NULL);
1696 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0, 1158 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0,
1697 57, &periph_h_regs, periph_clk_enb_refcnt); 1159 57, periph_clk_enb_refcnt);
1698 clk_register_clkdev(clk, "emc", NULL); 1160 clks[TEGRA30_CLK_EMC] = clk;
1699 clks[emc] = clk; 1161
1162 /* cml0 */
1163 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,
1164 0, 0, &cml_lock);
1165 clks[TEGRA30_CLK_CML0] = clk;
1166
1167 /* cml1 */
1168 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,
1169 1, 0, &cml_lock);
1170 clks[TEGRA30_CLK_CML1] = clk;
1700 1171
1701 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) { 1172 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
1702 data = &tegra_periph_clk_list[i]; 1173 data = &tegra_periph_clk_list[i];
1703 clk = tegra_clk_register_periph(data->name, data->parent_names, 1174 clk = tegra_clk_register_periph(data->name, data->p.parent_names,
1704 data->num_parents, &data->periph, 1175 data->num_parents, &data->periph,
1705 clk_base, data->offset, data->flags); 1176 clk_base, data->offset, data->flags);
1706 clk_register_clkdev(clk, data->con_id, data->dev_id);
1707 clks[data->clk_id] = clk; 1177 clks[data->clk_id] = clk;
1708 } 1178 }
1709 1179
1710 for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) { 1180 for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) {
1711 data = &tegra_periph_nodiv_clk_list[i]; 1181 data = &tegra_periph_nodiv_clk_list[i];
1712 clk = tegra_clk_register_periph_nodiv(data->name, 1182 clk = tegra_clk_register_periph_nodiv(data->name,
1713 data->parent_names, 1183 data->p.parent_names,
1714 data->num_parents, &data->periph, 1184 data->num_parents, &data->periph,
1715 clk_base, data->offset); 1185 clk_base, data->offset);
1716 clk_register_clkdev(clk, data->con_id, data->dev_id);
1717 clks[data->clk_id] = clk; 1186 clks[data->clk_id] = clk;
1718 } 1187 }
1719}
1720
1721static void __init tegra30_fixed_clk_init(void)
1722{
1723 struct clk *clk;
1724
1725 /* clk_32k */
1726 clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, CLK_IS_ROOT,
1727 32768);
1728 clk_register_clkdev(clk, "clk_32k", NULL);
1729 clks[clk_32k] = clk;
1730 1188
1731 /* clk_m_div2 */ 1189 tegra_periph_clk_init(clk_base, pmc_base, tegra30_clks, &pll_p_params);
1732 clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m",
1733 CLK_SET_RATE_PARENT, 1, 2);
1734 clk_register_clkdev(clk, "clk_m_div2", NULL);
1735 clks[clk_m_div2] = clk;
1736
1737 /* clk_m_div4 */
1738 clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m",
1739 CLK_SET_RATE_PARENT, 1, 4);
1740 clk_register_clkdev(clk, "clk_m_div4", NULL);
1741 clks[clk_m_div4] = clk;
1742
1743 /* cml0 */
1744 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,
1745 0, 0, &cml_lock);
1746 clk_register_clkdev(clk, "cml0", NULL);
1747 clks[cml0] = clk;
1748
1749 /* cml1 */
1750 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,
1751 1, 0, &cml_lock);
1752 clk_register_clkdev(clk, "cml1", NULL);
1753 clks[cml1] = clk;
1754}
1755
1756static void __init tegra30_osc_clk_init(void)
1757{
1758 struct clk *clk;
1759 unsigned int pll_ref_div;
1760
1761 tegra30_clk_measure_input_freq();
1762
1763 /* clk_m */
1764 clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT,
1765 input_freq);
1766 clk_register_clkdev(clk, "clk_m", NULL);
1767 clks[clk_m] = clk;
1768
1769 /* pll_ref */
1770 pll_ref_div = tegra30_get_pll_ref_div();
1771 clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m",
1772 CLK_SET_RATE_PARENT, 1, pll_ref_div);
1773 clk_register_clkdev(clk, "pll_ref", NULL);
1774 clks[pll_ref] = clk;
1775} 1190}
1776 1191
1777/* Tegra30 CPU clock and reset control functions */ 1192/* Tegra30 CPU clock and reset control functions */
@@ -1913,48 +1328,49 @@ static struct tegra_cpu_car_ops tegra30_cpu_car_ops = {
1913}; 1328};
1914 1329
1915static struct tegra_clk_init_table init_table[] __initdata = { 1330static struct tegra_clk_init_table init_table[] __initdata = {
1916 {uarta, pll_p, 408000000, 0}, 1331 {TEGRA30_CLK_UARTA, TEGRA30_CLK_PLL_P, 408000000, 0},
1917 {uartb, pll_p, 408000000, 0}, 1332 {TEGRA30_CLK_UARTB, TEGRA30_CLK_PLL_P, 408000000, 0},
1918 {uartc, pll_p, 408000000, 0}, 1333 {TEGRA30_CLK_UARTC, TEGRA30_CLK_PLL_P, 408000000, 0},
1919 {uartd, pll_p, 408000000, 0}, 1334 {TEGRA30_CLK_UARTD, TEGRA30_CLK_PLL_P, 408000000, 0},
1920 {uarte, pll_p, 408000000, 0}, 1335 {TEGRA30_CLK_UARTE, TEGRA30_CLK_PLL_P, 408000000, 0},
1921 {pll_a, clk_max, 564480000, 1}, 1336 {TEGRA30_CLK_PLL_A, TEGRA30_CLK_CLK_MAX, 564480000, 1},
1922 {pll_a_out0, clk_max, 11289600, 1}, 1337 {TEGRA30_CLK_PLL_A_OUT0, TEGRA30_CLK_CLK_MAX, 11289600, 1},
1923 {extern1, pll_a_out0, 0, 1}, 1338 {TEGRA30_CLK_EXTERN1, TEGRA30_CLK_PLL_A_OUT0, 0, 1},
1924 {clk_out_1_mux, extern1, 0, 0}, 1339 {TEGRA30_CLK_CLK_OUT_1_MUX, TEGRA30_CLK_EXTERN1, 0, 0},
1925 {clk_out_1, clk_max, 0, 1}, 1340 {TEGRA30_CLK_CLK_OUT_1, TEGRA30_CLK_CLK_MAX, 0, 1},
1926 {blink, clk_max, 0, 1}, 1341 {TEGRA30_CLK_BLINK, TEGRA30_CLK_CLK_MAX, 0, 1},
1927 {i2s0, pll_a_out0, 11289600, 0}, 1342 {TEGRA30_CLK_I2S0, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0},
1928 {i2s1, pll_a_out0, 11289600, 0}, 1343 {TEGRA30_CLK_I2S1, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0},
1929 {i2s2, pll_a_out0, 11289600, 0}, 1344 {TEGRA30_CLK_I2S2, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0},
1930 {i2s3, pll_a_out0, 11289600, 0}, 1345 {TEGRA30_CLK_I2S3, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0},
1931 {i2s4, pll_a_out0, 11289600, 0}, 1346 {TEGRA30_CLK_I2S4, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0},
1932 {sdmmc1, pll_p, 48000000, 0}, 1347 {TEGRA30_CLK_SDMMC1, TEGRA30_CLK_PLL_P, 48000000, 0},
1933 {sdmmc2, pll_p, 48000000, 0}, 1348 {TEGRA30_CLK_SDMMC2, TEGRA30_CLK_PLL_P, 48000000, 0},
1934 {sdmmc3, pll_p, 48000000, 0}, 1349 {TEGRA30_CLK_SDMMC3, TEGRA30_CLK_PLL_P, 48000000, 0},
1935 {pll_m, clk_max, 0, 1}, 1350 {TEGRA30_CLK_PLL_M, TEGRA30_CLK_CLK_MAX, 0, 1},
1936 {pclk, clk_max, 0, 1}, 1351 {TEGRA30_CLK_PCLK, TEGRA30_CLK_CLK_MAX, 0, 1},
1937 {csite, clk_max, 0, 1}, 1352 {TEGRA30_CLK_CSITE, TEGRA30_CLK_CLK_MAX, 0, 1},
1938 {emc, clk_max, 0, 1}, 1353 {TEGRA30_CLK_EMC, TEGRA30_CLK_CLK_MAX, 0, 1},
1939 {mselect, clk_max, 0, 1}, 1354 {TEGRA30_CLK_MSELECT, TEGRA30_CLK_CLK_MAX, 0, 1},
1940 {sbc1, pll_p, 100000000, 0}, 1355 {TEGRA30_CLK_SBC1, TEGRA30_CLK_PLL_P, 100000000, 0},
1941 {sbc2, pll_p, 100000000, 0}, 1356 {TEGRA30_CLK_SBC2, TEGRA30_CLK_PLL_P, 100000000, 0},
1942 {sbc3, pll_p, 100000000, 0}, 1357 {TEGRA30_CLK_SBC3, TEGRA30_CLK_PLL_P, 100000000, 0},
1943 {sbc4, pll_p, 100000000, 0}, 1358 {TEGRA30_CLK_SBC4, TEGRA30_CLK_PLL_P, 100000000, 0},
1944 {sbc5, pll_p, 100000000, 0}, 1359 {TEGRA30_CLK_SBC5, TEGRA30_CLK_PLL_P, 100000000, 0},
1945 {sbc6, pll_p, 100000000, 0}, 1360 {TEGRA30_CLK_SBC6, TEGRA30_CLK_PLL_P, 100000000, 0},
1946 {host1x, pll_c, 150000000, 0}, 1361 {TEGRA30_CLK_HOST1X, TEGRA30_CLK_PLL_C, 150000000, 0},
1947 {disp1, pll_p, 600000000, 0}, 1362 {TEGRA30_CLK_DISP1, TEGRA30_CLK_PLL_P, 600000000, 0},
1948 {disp2, pll_p, 600000000, 0}, 1363 {TEGRA30_CLK_DISP2, TEGRA30_CLK_PLL_P, 600000000, 0},
1949 {twd, clk_max, 0, 1}, 1364 {TEGRA30_CLK_TWD, TEGRA30_CLK_CLK_MAX, 0, 1},
1950 {gr2d, pll_c, 300000000, 0}, 1365 {TEGRA30_CLK_GR2D, TEGRA30_CLK_PLL_C, 300000000, 0},
1951 {gr3d, pll_c, 300000000, 0}, 1366 {TEGRA30_CLK_GR3D, TEGRA30_CLK_PLL_C, 300000000, 0},
1952 {clk_max, clk_max, 0, 0}, /* This MUST be the last entry. */ 1367 {TEGRA30_CLK_GR3D2, TEGRA30_CLK_PLL_C, 300000000, 0},
1368 {TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0}, /* This MUST be the last entry. */
1953}; 1369};
1954 1370
1955static void __init tegra30_clock_apply_init_table(void) 1371static void __init tegra30_clock_apply_init_table(void)
1956{ 1372{
1957 tegra_init_from_table(init_table, clks, clk_max); 1373 tegra_init_from_table(init_table, clks, TEGRA30_CLK_CLK_MAX);
1958} 1374}
1959 1375
1960/* 1376/*
@@ -1963,19 +1379,18 @@ static void __init tegra30_clock_apply_init_table(void)
1963 * table under two names. 1379 * table under two names.
1964 */ 1380 */
1965static struct tegra_clk_duplicate tegra_clk_duplicates[] = { 1381static struct tegra_clk_duplicate tegra_clk_duplicates[] = {
1966 TEGRA_CLK_DUPLICATE(usbd, "utmip-pad", NULL), 1382 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_USBD, "utmip-pad", NULL),
1967 TEGRA_CLK_DUPLICATE(usbd, "tegra-ehci.0", NULL), 1383 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_USBD, "tegra-ehci.0", NULL),
1968 TEGRA_CLK_DUPLICATE(usbd, "tegra-otg", NULL), 1384 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_USBD, "tegra-otg", NULL),
1969 TEGRA_CLK_DUPLICATE(bsev, "tegra-avp", "bsev"), 1385 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEV, "tegra-avp", "bsev"),
1970 TEGRA_CLK_DUPLICATE(bsev, "nvavp", "bsev"), 1386 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEV, "nvavp", "bsev"),
1971 TEGRA_CLK_DUPLICATE(vde, "tegra-aes", "vde"), 1387 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_VDE, "tegra-aes", "vde"),
1972 TEGRA_CLK_DUPLICATE(bsea, "tegra-aes", "bsea"), 1388 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEA, "tegra-aes", "bsea"),
1973 TEGRA_CLK_DUPLICATE(bsea, "nvavp", "bsea"), 1389 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEA, "nvavp", "bsea"),
1974 TEGRA_CLK_DUPLICATE(cml1, "tegra_sata_cml", NULL), 1390 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CML1, "tegra_sata_cml", NULL),
1975 TEGRA_CLK_DUPLICATE(cml0, "tegra_pcie", "cml"), 1391 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CML0, "tegra_pcie", "cml"),
1976 TEGRA_CLK_DUPLICATE(pciex, "tegra_pcie", "pciex"), 1392 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_VCP, "nvavp", "vcp"),
1977 TEGRA_CLK_DUPLICATE(vcp, "nvavp", "vcp"), 1393 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CLK_MAX, NULL, NULL), /* MUST be the last entry */
1978 TEGRA_CLK_DUPLICATE(clk_max, NULL, NULL), /* MUST be the last entry */
1979}; 1394};
1980 1395
1981static const struct of_device_id pmc_match[] __initconst = { 1396static const struct of_device_id pmc_match[] __initconst = {
@@ -1986,7 +1401,6 @@ static const struct of_device_id pmc_match[] __initconst = {
1986static void __init tegra30_clock_init(struct device_node *np) 1401static void __init tegra30_clock_init(struct device_node *np)
1987{ 1402{
1988 struct device_node *node; 1403 struct device_node *node;
1989 int i;
1990 1404
1991 clk_base = of_iomap(np, 0); 1405 clk_base = of_iomap(np, 0);
1992 if (!clk_base) { 1406 if (!clk_base) {
@@ -2006,29 +1420,27 @@ static void __init tegra30_clock_init(struct device_node *np)
2006 BUG(); 1420 BUG();
2007 } 1421 }
2008 1422
2009 tegra30_osc_clk_init(); 1423 clks = tegra_clk_init(clk_base, TEGRA30_CLK_CLK_MAX,
2010 tegra30_fixed_clk_init(); 1424 TEGRA30_CLK_PERIPH_BANKS);
1425 if (!clks)
1426 return;
1427
1428 if (tegra_osc_clk_init(clk_base, tegra30_clks, tegra30_input_freq,
1429 ARRAY_SIZE(tegra30_input_freq), &input_freq, NULL) < 0)
1430 return;
1431
1432
1433 tegra_fixed_clk_init(tegra30_clks);
2011 tegra30_pll_init(); 1434 tegra30_pll_init();
2012 tegra30_super_clk_init(); 1435 tegra30_super_clk_init();
2013 tegra30_periph_clk_init(); 1436 tegra30_periph_clk_init();
2014 tegra30_audio_clk_init(); 1437 tegra_audio_clk_init(clk_base, pmc_base, tegra30_clks, &pll_a_params);
2015 tegra30_pmc_clk_init(); 1438 tegra_pmc_clk_init(pmc_base, tegra30_clks);
2016
2017 for (i = 0; i < ARRAY_SIZE(clks); i++) {
2018 if (IS_ERR(clks[i])) {
2019 pr_err("Tegra30 clk %d: register failed with %ld\n",
2020 i, PTR_ERR(clks[i]));
2021 BUG();
2022 }
2023 if (!clks[i])
2024 clks[i] = ERR_PTR(-EINVAL);
2025 }
2026 1439
2027 tegra_init_dup_clks(tegra_clk_duplicates, clks, clk_max); 1440 tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA30_CLK_CLK_MAX);
2028 1441
2029 clk_data.clks = clks; 1442 tegra_add_of_provider(np);
2030 clk_data.clk_num = ARRAY_SIZE(clks); 1443 tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
2031 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
2032 1444
2033 tegra_clk_apply_init_table = tegra30_clock_apply_init_table; 1445 tegra_clk_apply_init_table = tegra30_clock_apply_init_table;
2034 1446
diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c
index 86581ac1fd69..c0a7d7723510 100644
--- a/drivers/clk/tegra/clk.c
+++ b/drivers/clk/tegra/clk.c
@@ -18,13 +18,175 @@
18#include <linux/clk-provider.h> 18#include <linux/clk-provider.h>
19#include <linux/of.h> 19#include <linux/of.h>
20#include <linux/clk/tegra.h> 20#include <linux/clk/tegra.h>
21#include <linux/reset-controller.h>
22#include <linux/tegra-soc.h>
21 23
22#include "clk.h" 24#include "clk.h"
23 25
26#define CLK_OUT_ENB_L 0x010
27#define CLK_OUT_ENB_H 0x014
28#define CLK_OUT_ENB_U 0x018
29#define CLK_OUT_ENB_V 0x360
30#define CLK_OUT_ENB_W 0x364
31#define CLK_OUT_ENB_X 0x280
32#define CLK_OUT_ENB_SET_L 0x320
33#define CLK_OUT_ENB_CLR_L 0x324
34#define CLK_OUT_ENB_SET_H 0x328
35#define CLK_OUT_ENB_CLR_H 0x32c
36#define CLK_OUT_ENB_SET_U 0x330
37#define CLK_OUT_ENB_CLR_U 0x334
38#define CLK_OUT_ENB_SET_V 0x440
39#define CLK_OUT_ENB_CLR_V 0x444
40#define CLK_OUT_ENB_SET_W 0x448
41#define CLK_OUT_ENB_CLR_W 0x44c
42#define CLK_OUT_ENB_SET_X 0x284
43#define CLK_OUT_ENB_CLR_X 0x288
44
45#define RST_DEVICES_L 0x004
46#define RST_DEVICES_H 0x008
47#define RST_DEVICES_U 0x00C
48#define RST_DFLL_DVCO 0x2F4
49#define RST_DEVICES_V 0x358
50#define RST_DEVICES_W 0x35C
51#define RST_DEVICES_X 0x28C
52#define RST_DEVICES_SET_L 0x300
53#define RST_DEVICES_CLR_L 0x304
54#define RST_DEVICES_SET_H 0x308
55#define RST_DEVICES_CLR_H 0x30c
56#define RST_DEVICES_SET_U 0x310
57#define RST_DEVICES_CLR_U 0x314
58#define RST_DEVICES_SET_V 0x430
59#define RST_DEVICES_CLR_V 0x434
60#define RST_DEVICES_SET_W 0x438
61#define RST_DEVICES_CLR_W 0x43c
62#define RST_DEVICES_SET_X 0x290
63#define RST_DEVICES_CLR_X 0x294
64
24/* Global data of Tegra CPU CAR ops */ 65/* Global data of Tegra CPU CAR ops */
25static struct tegra_cpu_car_ops dummy_car_ops; 66static struct tegra_cpu_car_ops dummy_car_ops;
26struct tegra_cpu_car_ops *tegra_cpu_car_ops = &dummy_car_ops; 67struct tegra_cpu_car_ops *tegra_cpu_car_ops = &dummy_car_ops;
27 68
69int *periph_clk_enb_refcnt;
70static int periph_banks;
71static struct clk **clks;
72static int clk_num;
73static struct clk_onecell_data clk_data;
74
75static struct tegra_clk_periph_regs periph_regs[] = {
76 [0] = {
77 .enb_reg = CLK_OUT_ENB_L,
78 .enb_set_reg = CLK_OUT_ENB_SET_L,
79 .enb_clr_reg = CLK_OUT_ENB_CLR_L,
80 .rst_reg = RST_DEVICES_L,
81 .rst_set_reg = RST_DEVICES_SET_L,
82 .rst_clr_reg = RST_DEVICES_CLR_L,
83 },
84 [1] = {
85 .enb_reg = CLK_OUT_ENB_H,
86 .enb_set_reg = CLK_OUT_ENB_SET_H,
87 .enb_clr_reg = CLK_OUT_ENB_CLR_H,
88 .rst_reg = RST_DEVICES_H,
89 .rst_set_reg = RST_DEVICES_SET_H,
90 .rst_clr_reg = RST_DEVICES_CLR_H,
91 },
92 [2] = {
93 .enb_reg = CLK_OUT_ENB_U,
94 .enb_set_reg = CLK_OUT_ENB_SET_U,
95 .enb_clr_reg = CLK_OUT_ENB_CLR_U,
96 .rst_reg = RST_DEVICES_U,
97 .rst_set_reg = RST_DEVICES_SET_U,
98 .rst_clr_reg = RST_DEVICES_CLR_U,
99 },
100 [3] = {
101 .enb_reg = CLK_OUT_ENB_V,
102 .enb_set_reg = CLK_OUT_ENB_SET_V,
103 .enb_clr_reg = CLK_OUT_ENB_CLR_V,
104 .rst_reg = RST_DEVICES_V,
105 .rst_set_reg = RST_DEVICES_SET_V,
106 .rst_clr_reg = RST_DEVICES_CLR_V,
107 },
108 [4] = {
109 .enb_reg = CLK_OUT_ENB_W,
110 .enb_set_reg = CLK_OUT_ENB_SET_W,
111 .enb_clr_reg = CLK_OUT_ENB_CLR_W,
112 .rst_reg = RST_DEVICES_W,
113 .rst_set_reg = RST_DEVICES_SET_W,
114 .rst_clr_reg = RST_DEVICES_CLR_W,
115 },
116 [5] = {
117 .enb_reg = CLK_OUT_ENB_X,
118 .enb_set_reg = CLK_OUT_ENB_SET_X,
119 .enb_clr_reg = CLK_OUT_ENB_CLR_X,
120 .rst_reg = RST_DEVICES_X,
121 .rst_set_reg = RST_DEVICES_SET_X,
122 .rst_clr_reg = RST_DEVICES_CLR_X,
123 },
124};
125
126static void __iomem *clk_base;
127
128static int tegra_clk_rst_assert(struct reset_controller_dev *rcdev,
129 unsigned long id)
130{
131 /*
132 * If peripheral is on the APB bus then we must read the APB bus to
133 * flush the write operation in apb bus. This will avoid peripheral
134 * access after disabling clock. Since the reset driver has no
135 * knowledge of which reset IDs represent which devices, simply do
136 * this all the time.
137 */
138 tegra_read_chipid();
139
140 writel_relaxed(BIT(id % 32),
141 clk_base + periph_regs[id / 32].rst_set_reg);
142
143 return 0;
144}
145
146static int tegra_clk_rst_deassert(struct reset_controller_dev *rcdev,
147 unsigned long id)
148{
149 writel_relaxed(BIT(id % 32),
150 clk_base + periph_regs[id / 32].rst_clr_reg);
151
152 return 0;
153}
154
155struct tegra_clk_periph_regs *get_reg_bank(int clkid)
156{
157 int reg_bank = clkid / 32;
158
159 if (reg_bank < periph_banks)
160 return &periph_regs[reg_bank];
161 else {
162 WARN_ON(1);
163 return NULL;
164 }
165}
166
167struct clk ** __init tegra_clk_init(void __iomem *regs, int num, int banks)
168{
169 clk_base = regs;
170
171 if (WARN_ON(banks > ARRAY_SIZE(periph_regs)))
172 return NULL;
173
174 periph_clk_enb_refcnt = kzalloc(32 * banks *
175 sizeof(*periph_clk_enb_refcnt), GFP_KERNEL);
176 if (!periph_clk_enb_refcnt)
177 return NULL;
178
179 periph_banks = banks;
180
181 clks = kzalloc(num * sizeof(struct clk *), GFP_KERNEL);
182 if (!clks)
183 kfree(periph_clk_enb_refcnt);
184
185 clk_num = num;
186
187 return clks;
188}
189
28void __init tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list, 190void __init tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list,
29 struct clk *clks[], int clk_max) 191 struct clk *clks[], int clk_max)
30{ 192{
@@ -74,6 +236,58 @@ void __init tegra_init_from_table(struct tegra_clk_init_table *tbl,
74 } 236 }
75} 237}
76 238
239static struct reset_control_ops rst_ops = {
240 .assert = tegra_clk_rst_assert,
241 .deassert = tegra_clk_rst_deassert,
242};
243
244static struct reset_controller_dev rst_ctlr = {
245 .ops = &rst_ops,
246 .owner = THIS_MODULE,
247 .of_reset_n_cells = 1,
248};
249
250void __init tegra_add_of_provider(struct device_node *np)
251{
252 int i;
253
254 for (i = 0; i < clk_num; i++) {
255 if (IS_ERR(clks[i])) {
256 pr_err
257 ("Tegra clk %d: register failed with %ld\n",
258 i, PTR_ERR(clks[i]));
259 }
260 if (!clks[i])
261 clks[i] = ERR_PTR(-EINVAL);
262 }
263
264 clk_data.clks = clks;
265 clk_data.clk_num = clk_num;
266 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
267
268 rst_ctlr.of_node = np;
269 rst_ctlr.nr_resets = clk_num * 32;
270 reset_controller_register(&rst_ctlr);
271}
272
273void __init tegra_register_devclks(struct tegra_devclk *dev_clks, int num)
274{
275 int i;
276
277 for (i = 0; i < num; i++, dev_clks++)
278 clk_register_clkdev(clks[dev_clks->dt_id], dev_clks->con_id,
279 dev_clks->dev_id);
280}
281
282struct clk ** __init tegra_lookup_dt_id(int clk_id,
283 struct tegra_clk *tegra_clk)
284{
285 if (tegra_clk[clk_id].present)
286 return &clks[tegra_clk[clk_id].dt_id];
287 else
288 return NULL;
289}
290
77tegra_clk_apply_init_table_func tegra_clk_apply_init_table; 291tegra_clk_apply_init_table_func tegra_clk_apply_init_table;
78 292
79void __init tegra_clocks_apply_init_table(void) 293void __init tegra_clocks_apply_init_table(void)
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 07cfacd91686..16ec8d6bb87f 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -37,6 +37,8 @@ struct tegra_clk_sync_source {
37 container_of(_hw, struct tegra_clk_sync_source, hw) 37 container_of(_hw, struct tegra_clk_sync_source, hw)
38 38
39extern const struct clk_ops tegra_clk_sync_source_ops; 39extern const struct clk_ops tegra_clk_sync_source_ops;
40extern int *periph_clk_enb_refcnt;
41
40struct clk *tegra_clk_register_sync_source(const char *name, 42struct clk *tegra_clk_register_sync_source(const char *name,
41 unsigned long fixed_rate, unsigned long max_rate); 43 unsigned long fixed_rate, unsigned long max_rate);
42 44
@@ -188,12 +190,15 @@ struct tegra_clk_pll_params {
188 u32 ext_misc_reg[3]; 190 u32 ext_misc_reg[3];
189 u32 pmc_divnm_reg; 191 u32 pmc_divnm_reg;
190 u32 pmc_divp_reg; 192 u32 pmc_divp_reg;
193 u32 flags;
191 int stepa_shift; 194 int stepa_shift;
192 int stepb_shift; 195 int stepb_shift;
193 int lock_delay; 196 int lock_delay;
194 int max_p; 197 int max_p;
195 struct pdiv_map *pdiv_tohw; 198 struct pdiv_map *pdiv_tohw;
196 struct div_nmp *div_nmp; 199 struct div_nmp *div_nmp;
200 struct tegra_clk_pll_freq_table *freq_table;
201 unsigned long fixed_rate;
197}; 202};
198 203
199/** 204/**
@@ -233,10 +238,7 @@ struct tegra_clk_pll {
233 struct clk_hw hw; 238 struct clk_hw hw;
234 void __iomem *clk_base; 239 void __iomem *clk_base;
235 void __iomem *pmc; 240 void __iomem *pmc;
236 u32 flags;
237 unsigned long fixed_rate;
238 spinlock_t *lock; 241 spinlock_t *lock;
239 struct tegra_clk_pll_freq_table *freq_table;
240 struct tegra_clk_pll_params *params; 242 struct tegra_clk_pll_params *params;
241}; 243};
242 244
@@ -258,56 +260,49 @@ extern const struct clk_ops tegra_clk_pll_ops;
258extern const struct clk_ops tegra_clk_plle_ops; 260extern const struct clk_ops tegra_clk_plle_ops;
259struct clk *tegra_clk_register_pll(const char *name, const char *parent_name, 261struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
260 void __iomem *clk_base, void __iomem *pmc, 262 void __iomem *clk_base, void __iomem *pmc,
261 unsigned long flags, unsigned long fixed_rate, 263 unsigned long flags, struct tegra_clk_pll_params *pll_params,
262 struct tegra_clk_pll_params *pll_params, u32 pll_flags, 264 spinlock_t *lock);
263 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock);
264 265
265struct clk *tegra_clk_register_plle(const char *name, const char *parent_name, 266struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
266 void __iomem *clk_base, void __iomem *pmc, 267 void __iomem *clk_base, void __iomem *pmc,
267 unsigned long flags, unsigned long fixed_rate, 268 unsigned long flags, struct tegra_clk_pll_params *pll_params,
268 struct tegra_clk_pll_params *pll_params, u32 pll_flags, 269 spinlock_t *lock);
269 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock);
270 270
271struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name, 271struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
272 void __iomem *clk_base, void __iomem *pmc, 272 void __iomem *clk_base, void __iomem *pmc,
273 unsigned long flags, unsigned long fixed_rate, 273 unsigned long flags,
274 struct tegra_clk_pll_params *pll_params, 274 struct tegra_clk_pll_params *pll_params,
275 u32 pll_flags,
276 struct tegra_clk_pll_freq_table *freq_table,
277 spinlock_t *lock); 275 spinlock_t *lock);
278 276
279struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name, 277struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
280 void __iomem *clk_base, void __iomem *pmc, 278 void __iomem *clk_base, void __iomem *pmc,
281 unsigned long flags, unsigned long fixed_rate, 279 unsigned long flags,
282 struct tegra_clk_pll_params *pll_params, 280 struct tegra_clk_pll_params *pll_params,
283 u32 pll_flags,
284 struct tegra_clk_pll_freq_table *freq_table,
285 spinlock_t *lock); 281 spinlock_t *lock);
286 282
287struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name, 283struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
288 void __iomem *clk_base, void __iomem *pmc, 284 void __iomem *clk_base, void __iomem *pmc,
289 unsigned long flags, unsigned long fixed_rate, 285 unsigned long flags,
290 struct tegra_clk_pll_params *pll_params, 286 struct tegra_clk_pll_params *pll_params,
291 u32 pll_flags,
292 struct tegra_clk_pll_freq_table *freq_table,
293 spinlock_t *lock); 287 spinlock_t *lock);
294 288
295struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name, 289struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
296 void __iomem *clk_base, void __iomem *pmc, 290 void __iomem *clk_base, void __iomem *pmc,
297 unsigned long flags, unsigned long fixed_rate, 291 unsigned long flags,
298 struct tegra_clk_pll_params *pll_params, 292 struct tegra_clk_pll_params *pll_params,
299 u32 pll_flags,
300 struct tegra_clk_pll_freq_table *freq_table,
301 spinlock_t *lock, unsigned long parent_rate); 293 spinlock_t *lock, unsigned long parent_rate);
302 294
303struct clk *tegra_clk_register_plle_tegra114(const char *name, 295struct clk *tegra_clk_register_plle_tegra114(const char *name,
304 const char *parent_name, 296 const char *parent_name,
305 void __iomem *clk_base, unsigned long flags, 297 void __iomem *clk_base, unsigned long flags,
306 unsigned long fixed_rate,
307 struct tegra_clk_pll_params *pll_params, 298 struct tegra_clk_pll_params *pll_params,
308 struct tegra_clk_pll_freq_table *freq_table,
309 spinlock_t *lock); 299 spinlock_t *lock);
310 300
301struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,
302 void __iomem *clk_base, unsigned long flags,
303 struct tegra_clk_pll_params *pll_params,
304 spinlock_t *lock);
305
311/** 306/**
312 * struct tegra_clk_pll_out - PLL divider down clock 307 * struct tegra_clk_pll_out - PLL divider down clock
313 * 308 *
@@ -395,13 +390,13 @@ struct tegra_clk_periph_gate {
395#define TEGRA_PERIPH_MANUAL_RESET BIT(1) 390#define TEGRA_PERIPH_MANUAL_RESET BIT(1)
396#define TEGRA_PERIPH_ON_APB BIT(2) 391#define TEGRA_PERIPH_ON_APB BIT(2)
397#define TEGRA_PERIPH_WAR_1005168 BIT(3) 392#define TEGRA_PERIPH_WAR_1005168 BIT(3)
393#define TEGRA_PERIPH_NO_DIV BIT(4)
394#define TEGRA_PERIPH_NO_GATE BIT(5)
398 395
399void tegra_periph_reset(struct tegra_clk_periph_gate *gate, bool assert);
400extern const struct clk_ops tegra_clk_periph_gate_ops; 396extern const struct clk_ops tegra_clk_periph_gate_ops;
401struct clk *tegra_clk_register_periph_gate(const char *name, 397struct clk *tegra_clk_register_periph_gate(const char *name,
402 const char *parent_name, u8 gate_flags, void __iomem *clk_base, 398 const char *parent_name, u8 gate_flags, void __iomem *clk_base,
403 unsigned long flags, int clk_num, 399 unsigned long flags, int clk_num, int *enable_refcnt);
404 struct tegra_clk_periph_regs *pregs, int *enable_refcnt);
405 400
406/** 401/**
407 * struct clk-periph - peripheral clock 402 * struct clk-periph - peripheral clock
@@ -443,26 +438,26 @@ struct clk *tegra_clk_register_periph_nodiv(const char *name,
443 438
444#define TEGRA_CLK_PERIPH(_mux_shift, _mux_mask, _mux_flags, \ 439#define TEGRA_CLK_PERIPH(_mux_shift, _mux_mask, _mux_flags, \
445 _div_shift, _div_width, _div_frac_width, \ 440 _div_shift, _div_width, _div_frac_width, \
446 _div_flags, _clk_num, _enb_refcnt, _regs, \ 441 _div_flags, _clk_num,\
447 _gate_flags, _table) \ 442 _gate_flags, _table, _lock) \
448 { \ 443 { \
449 .mux = { \ 444 .mux = { \
450 .flags = _mux_flags, \ 445 .flags = _mux_flags, \
451 .shift = _mux_shift, \ 446 .shift = _mux_shift, \
452 .mask = _mux_mask, \ 447 .mask = _mux_mask, \
453 .table = _table, \ 448 .table = _table, \
449 .lock = _lock, \
454 }, \ 450 }, \
455 .divider = { \ 451 .divider = { \
456 .flags = _div_flags, \ 452 .flags = _div_flags, \
457 .shift = _div_shift, \ 453 .shift = _div_shift, \
458 .width = _div_width, \ 454 .width = _div_width, \
459 .frac_width = _div_frac_width, \ 455 .frac_width = _div_frac_width, \
456 .lock = _lock, \
460 }, \ 457 }, \
461 .gate = { \ 458 .gate = { \
462 .flags = _gate_flags, \ 459 .flags = _gate_flags, \
463 .clk_num = _clk_num, \ 460 .clk_num = _clk_num, \
464 .enable_refcnt = _enb_refcnt, \
465 .regs = _regs, \
466 }, \ 461 }, \
467 .mux_ops = &clk_mux_ops, \ 462 .mux_ops = &clk_mux_ops, \
468 .div_ops = &tegra_clk_frac_div_ops, \ 463 .div_ops = &tegra_clk_frac_div_ops, \
@@ -472,7 +467,10 @@ struct clk *tegra_clk_register_periph_nodiv(const char *name,
472struct tegra_periph_init_data { 467struct tegra_periph_init_data {
473 const char *name; 468 const char *name;
474 int clk_id; 469 int clk_id;
475 const char **parent_names; 470 union {
471 const char **parent_names;
472 const char *parent_name;
473 } p;
476 int num_parents; 474 int num_parents;
477 struct tegra_clk_periph periph; 475 struct tegra_clk_periph periph;
478 u32 offset; 476 u32 offset;
@@ -483,20 +481,19 @@ struct tegra_periph_init_data {
483 481
484#define TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\ 482#define TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\
485 _mux_shift, _mux_mask, _mux_flags, _div_shift, \ 483 _mux_shift, _mux_mask, _mux_flags, _div_shift, \
486 _div_width, _div_frac_width, _div_flags, _regs, \ 484 _div_width, _div_frac_width, _div_flags, \
487 _clk_num, _enb_refcnt, _gate_flags, _clk_id, _table,\ 485 _clk_num, _gate_flags, _clk_id, _table, \
488 _flags) \ 486 _flags, _lock) \
489 { \ 487 { \
490 .name = _name, \ 488 .name = _name, \
491 .clk_id = _clk_id, \ 489 .clk_id = _clk_id, \
492 .parent_names = _parent_names, \ 490 .p.parent_names = _parent_names, \
493 .num_parents = ARRAY_SIZE(_parent_names), \ 491 .num_parents = ARRAY_SIZE(_parent_names), \
494 .periph = TEGRA_CLK_PERIPH(_mux_shift, _mux_mask, \ 492 .periph = TEGRA_CLK_PERIPH(_mux_shift, _mux_mask, \
495 _mux_flags, _div_shift, \ 493 _mux_flags, _div_shift, \
496 _div_width, _div_frac_width, \ 494 _div_width, _div_frac_width, \
497 _div_flags, _clk_num, \ 495 _div_flags, _clk_num, \
498 _enb_refcnt, _regs, \ 496 _gate_flags, _table, _lock), \
499 _gate_flags, _table), \
500 .offset = _offset, \ 497 .offset = _offset, \
501 .con_id = _con_id, \ 498 .con_id = _con_id, \
502 .dev_id = _dev_id, \ 499 .dev_id = _dev_id, \
@@ -505,13 +502,13 @@ struct tegra_periph_init_data {
505 502
506#define TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parent_names, _offset,\ 503#define TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parent_names, _offset,\
507 _mux_shift, _mux_width, _mux_flags, _div_shift, \ 504 _mux_shift, _mux_width, _mux_flags, _div_shift, \
508 _div_width, _div_frac_width, _div_flags, _regs, \ 505 _div_width, _div_frac_width, _div_flags, \
509 _clk_num, _enb_refcnt, _gate_flags, _clk_id) \ 506 _clk_num, _gate_flags, _clk_id) \
510 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\ 507 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\
511 _mux_shift, BIT(_mux_width) - 1, _mux_flags, \ 508 _mux_shift, BIT(_mux_width) - 1, _mux_flags, \
512 _div_shift, _div_width, _div_frac_width, _div_flags, \ 509 _div_shift, _div_width, _div_frac_width, _div_flags, \
513 _regs, _clk_num, _enb_refcnt, _gate_flags, _clk_id,\ 510 _clk_num, _gate_flags, _clk_id,\
514 NULL, 0) 511 NULL, 0, NULL)
515 512
516/** 513/**
517 * struct clk_super_mux - super clock 514 * struct clk_super_mux - super clock
@@ -581,12 +578,49 @@ struct tegra_clk_duplicate {
581 }, \ 578 }, \
582 } 579 }
583 580
581struct tegra_clk {
582 int dt_id;
583 bool present;
584};
585
586struct tegra_devclk {
587 int dt_id;
588 char *dev_id;
589 char *con_id;
590};
591
584void tegra_init_from_table(struct tegra_clk_init_table *tbl, 592void tegra_init_from_table(struct tegra_clk_init_table *tbl,
585 struct clk *clks[], int clk_max); 593 struct clk *clks[], int clk_max);
586 594
587void tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list, 595void tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list,
588 struct clk *clks[], int clk_max); 596 struct clk *clks[], int clk_max);
589 597
598struct tegra_clk_periph_regs *get_reg_bank(int clkid);
599struct clk **tegra_clk_init(void __iomem *clk_base, int num, int periph_banks);
600
601struct clk **tegra_lookup_dt_id(int clk_id, struct tegra_clk *tegra_clk);
602
603void tegra_add_of_provider(struct device_node *np);
604void tegra_register_devclks(struct tegra_devclk *dev_clks, int num);
605
606void tegra_audio_clk_init(void __iomem *clk_base,
607 void __iomem *pmc_base, struct tegra_clk *tegra_clks,
608 struct tegra_clk_pll_params *pll_params);
609
610void tegra_periph_clk_init(void __iomem *clk_base, void __iomem *pmc_base,
611 struct tegra_clk *tegra_clks,
612 struct tegra_clk_pll_params *pll_params);
613
614void tegra_pmc_clk_init(void __iomem *pmc_base, struct tegra_clk *tegra_clks);
615void tegra_fixed_clk_init(struct tegra_clk *tegra_clks);
616int tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *tegra_clks,
617 unsigned long *input_freqs, int num,
618 unsigned long *osc_freq,
619 unsigned long *pll_ref_freq);
620void tegra_super_clk_gen4_init(void __iomem *clk_base,
621 void __iomem *pmc_base, struct tegra_clk *tegra_clks,
622 struct tegra_clk_pll_params *pll_params);
623
590void tegra114_clock_tune_cpu_trimmers_high(void); 624void tegra114_clock_tune_cpu_trimmers_high(void);
591void tegra114_clock_tune_cpu_trimmers_low(void); 625void tegra114_clock_tune_cpu_trimmers_low(void);
592void tegra114_clock_tune_cpu_trimmers_init(void); 626void tegra114_clock_tune_cpu_trimmers_init(void);
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index bdb953e15d2a..5c07a56962db 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -87,6 +87,7 @@ config ARM_ARCH_TIMER
87config ARM_ARCH_TIMER_EVTSTREAM 87config ARM_ARCH_TIMER_EVTSTREAM
88 bool "Support for ARM architected timer event stream generation" 88 bool "Support for ARM architected timer event stream generation"
89 default y if ARM_ARCH_TIMER 89 default y if ARM_ARCH_TIMER
90 depends on ARM_ARCH_TIMER
90 help 91 help
91 This option enables support for event stream generation based on 92 This option enables support for event stream generation based on
92 the ARM architected timer. It is used for waking up CPUs executing 93 the ARM architected timer. It is used for waking up CPUs executing
diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index 62b0de6a1837..48f76bc05da0 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -71,6 +71,10 @@ enum {
71 MCT_L1_IRQ, 71 MCT_L1_IRQ,
72 MCT_L2_IRQ, 72 MCT_L2_IRQ,
73 MCT_L3_IRQ, 73 MCT_L3_IRQ,
74 MCT_L4_IRQ,
75 MCT_L5_IRQ,
76 MCT_L6_IRQ,
77 MCT_L7_IRQ,
74 MCT_NR_IRQS, 78 MCT_NR_IRQS,
75}; 79};
76 80
diff --git a/drivers/clocksource/nomadik-mtu.c b/drivers/clocksource/nomadik-mtu.c
index ed7b73b508e0..f00b5c9ce8b6 100644
--- a/drivers/clocksource/nomadik-mtu.c
+++ b/drivers/clocksource/nomadik-mtu.c
@@ -20,7 +20,6 @@
20#include <linux/jiffies.h> 20#include <linux/jiffies.h>
21#include <linux/delay.h> 21#include <linux/delay.h>
22#include <linux/err.h> 22#include <linux/err.h>
23#include <linux/platform_data/clocksource-nomadik-mtu.h>
24#include <linux/sched_clock.h> 23#include <linux/sched_clock.h>
25#include <asm/mach/time.h> 24#include <asm/mach/time.h>
26 25
@@ -103,7 +102,7 @@ static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev)
103 return 0; 102 return 0;
104} 103}
105 104
106void nmdk_clkevt_reset(void) 105static void nmdk_clkevt_reset(void)
107{ 106{
108 if (clkevt_periodic) { 107 if (clkevt_periodic) {
109 /* Timer: configure load and background-load, and fire it up */ 108 /* Timer: configure load and background-load, and fire it up */
@@ -144,7 +143,7 @@ static void nmdk_clkevt_mode(enum clock_event_mode mode,
144 } 143 }
145} 144}
146 145
147void nmdk_clksrc_reset(void) 146static void nmdk_clksrc_reset(void)
148{ 147{
149 /* Disable */ 148 /* Disable */
150 writel(0, mtu_base + MTU_CR(0)); 149 writel(0, mtu_base + MTU_CR(0));
@@ -192,8 +191,8 @@ static struct irqaction nmdk_timer_irq = {
192 .dev_id = &nmdk_clkevt, 191 .dev_id = &nmdk_clkevt,
193}; 192};
194 193
195static void __init __nmdk_timer_init(void __iomem *base, int irq, 194static void __init nmdk_timer_init(void __iomem *base, int irq,
196 struct clk *pclk, struct clk *clk) 195 struct clk *pclk, struct clk *clk)
197{ 196{
198 unsigned long rate; 197 unsigned long rate;
199 198
@@ -245,18 +244,6 @@ static void __init __nmdk_timer_init(void __iomem *base, int irq,
245 register_current_timer_delay(&mtu_delay_timer); 244 register_current_timer_delay(&mtu_delay_timer);
246} 245}
247 246
248void __init nmdk_timer_init(void __iomem *base, int irq)
249{
250 struct clk *clk0, *pclk0;
251
252 pclk0 = clk_get_sys("mtu0", "apb_pclk");
253 BUG_ON(IS_ERR(pclk0));
254 clk0 = clk_get_sys("mtu0", NULL);
255 BUG_ON(IS_ERR(clk0));
256
257 __nmdk_timer_init(base, irq, pclk0, clk0);
258}
259
260static void __init nmdk_timer_of_init(struct device_node *node) 247static void __init nmdk_timer_of_init(struct device_node *node)
261{ 248{
262 struct clk *pclk; 249 struct clk *pclk;
@@ -280,7 +267,7 @@ static void __init nmdk_timer_of_init(struct device_node *node)
280 if (irq <= 0) 267 if (irq <= 0)
281 panic("Can't parse IRQ"); 268 panic("Can't parse IRQ");
282 269
283 __nmdk_timer_init(base, irq, pclk, clk); 270 nmdk_timer_init(base, irq, pclk, clk);
284} 271}
285CLOCKSOURCE_OF_DECLARE(nomadik_mtu, "st,nomadik-mtu", 272CLOCKSOURCE_OF_DECLARE(nomadik_mtu, "st,nomadik-mtu",
286 nmdk_timer_of_init); 273 nmdk_timer_of_init);
diff --git a/drivers/clocksource/sh_mtu2.c b/drivers/clocksource/sh_mtu2.c
index 4aac9ee0d0c0..3cf12834681e 100644
--- a/drivers/clocksource/sh_mtu2.c
+++ b/drivers/clocksource/sh_mtu2.c
@@ -313,8 +313,20 @@ static int sh_mtu2_setup(struct sh_mtu2_priv *p, struct platform_device *pdev)
313 goto err1; 313 goto err1;
314 } 314 }
315 315
316 return sh_mtu2_register(p, (char *)dev_name(&p->pdev->dev), 316 ret = clk_prepare(p->clk);
317 cfg->clockevent_rating); 317 if (ret < 0)
318 goto err2;
319
320 ret = sh_mtu2_register(p, (char *)dev_name(&p->pdev->dev),
321 cfg->clockevent_rating);
322 if (ret < 0)
323 goto err3;
324
325 return 0;
326 err3:
327 clk_unprepare(p->clk);
328 err2:
329 clk_put(p->clk);
318 err1: 330 err1:
319 iounmap(p->mapbase); 331 iounmap(p->mapbase);
320 err0: 332 err0:
diff --git a/drivers/clocksource/sh_tmu.c b/drivers/clocksource/sh_tmu.c
index 78b8dae49628..63557cda0a7d 100644
--- a/drivers/clocksource/sh_tmu.c
+++ b/drivers/clocksource/sh_tmu.c
@@ -472,12 +472,26 @@ static int sh_tmu_setup(struct sh_tmu_priv *p, struct platform_device *pdev)
472 ret = PTR_ERR(p->clk); 472 ret = PTR_ERR(p->clk);
473 goto err1; 473 goto err1;
474 } 474 }
475
476 ret = clk_prepare(p->clk);
477 if (ret < 0)
478 goto err2;
479
475 p->cs_enabled = false; 480 p->cs_enabled = false;
476 p->enable_count = 0; 481 p->enable_count = 0;
477 482
478 return sh_tmu_register(p, (char *)dev_name(&p->pdev->dev), 483 ret = sh_tmu_register(p, (char *)dev_name(&p->pdev->dev),
479 cfg->clockevent_rating, 484 cfg->clockevent_rating,
480 cfg->clocksource_rating); 485 cfg->clocksource_rating);
486 if (ret < 0)
487 goto err3;
488
489 return 0;
490
491 err3:
492 clk_unprepare(p->clk);
493 err2:
494 clk_put(p->clk);
481 err1: 495 err1:
482 iounmap(p->mapbase); 496 iounmap(p->mapbase);
483 err0: 497 err0:
diff --git a/drivers/cpufreq/cpufreq.c b/drivers/cpufreq/cpufreq.c
index 02d534da22dd..81e9d4412db8 100644
--- a/drivers/cpufreq/cpufreq.c
+++ b/drivers/cpufreq/cpufreq.c
@@ -26,6 +26,7 @@
26#include <linux/module.h> 26#include <linux/module.h>
27#include <linux/mutex.h> 27#include <linux/mutex.h>
28#include <linux/slab.h> 28#include <linux/slab.h>
29#include <linux/suspend.h>
29#include <linux/syscore_ops.h> 30#include <linux/syscore_ops.h>
30#include <linux/tick.h> 31#include <linux/tick.h>
31#include <trace/events/power.h> 32#include <trace/events/power.h>
@@ -47,6 +48,9 @@ static LIST_HEAD(cpufreq_policy_list);
47static DEFINE_PER_CPU(char[CPUFREQ_NAME_LEN], cpufreq_cpu_governor); 48static DEFINE_PER_CPU(char[CPUFREQ_NAME_LEN], cpufreq_cpu_governor);
48#endif 49#endif
49 50
51/* Flag to suspend/resume CPUFreq governors */
52static bool cpufreq_suspended;
53
50static inline bool has_target(void) 54static inline bool has_target(void)
51{ 55{
52 return cpufreq_driver->target_index || cpufreq_driver->target; 56 return cpufreq_driver->target_index || cpufreq_driver->target;
@@ -1462,6 +1466,41 @@ static struct subsys_interface cpufreq_interface = {
1462 .remove_dev = cpufreq_remove_dev, 1466 .remove_dev = cpufreq_remove_dev,
1463}; 1467};
1464 1468
1469void cpufreq_suspend(void)
1470{
1471 struct cpufreq_policy *policy;
1472
1473 if (!has_target())
1474 return;
1475
1476 pr_debug("%s: Suspending Governors\n", __func__);
1477
1478 list_for_each_entry(policy, &cpufreq_policy_list, policy_list)
1479 if (__cpufreq_governor(policy, CPUFREQ_GOV_STOP))
1480 pr_err("%s: Failed to stop governor for policy: %p\n",
1481 __func__, policy);
1482
1483 cpufreq_suspended = true;
1484}
1485
1486void cpufreq_resume(void)
1487{
1488 struct cpufreq_policy *policy;
1489
1490 if (!has_target())
1491 return;
1492
1493 pr_debug("%s: Resuming Governors\n", __func__);
1494
1495 cpufreq_suspended = false;
1496
1497 list_for_each_entry(policy, &cpufreq_policy_list, policy_list)
1498 if (__cpufreq_governor(policy, CPUFREQ_GOV_START)
1499 || __cpufreq_governor(policy, CPUFREQ_GOV_LIMITS))
1500 pr_err("%s: Failed to start governor for policy: %p\n",
1501 __func__, policy);
1502}
1503
1465/** 1504/**
1466 * cpufreq_bp_suspend - Prepare the boot CPU for system suspend. 1505 * cpufreq_bp_suspend - Prepare the boot CPU for system suspend.
1467 * 1506 *
@@ -1764,6 +1803,10 @@ static int __cpufreq_governor(struct cpufreq_policy *policy,
1764 struct cpufreq_governor *gov = NULL; 1803 struct cpufreq_governor *gov = NULL;
1765#endif 1804#endif
1766 1805
1806 /* Don't start any governor operations if we are entering suspend */
1807 if (cpufreq_suspended)
1808 return 0;
1809
1767 if (policy->governor->max_transition_latency && 1810 if (policy->governor->max_transition_latency &&
1768 policy->cpuinfo.transition_latency > 1811 policy->cpuinfo.transition_latency >
1769 policy->governor->max_transition_latency) { 1812 policy->governor->max_transition_latency) {
@@ -2076,9 +2119,6 @@ static int cpufreq_cpu_callback(struct notifier_block *nfb,
2076 dev = get_cpu_device(cpu); 2119 dev = get_cpu_device(cpu);
2077 if (dev) { 2120 if (dev) {
2078 2121
2079 if (action & CPU_TASKS_FROZEN)
2080 frozen = true;
2081
2082 switch (action & ~CPU_TASKS_FROZEN) { 2122 switch (action & ~CPU_TASKS_FROZEN) {
2083 case CPU_ONLINE: 2123 case CPU_ONLINE:
2084 __cpufreq_add_dev(dev, NULL, frozen); 2124 __cpufreq_add_dev(dev, NULL, frozen);
diff --git a/drivers/cpufreq/exynos4210-cpufreq.c b/drivers/cpufreq/exynos4210-cpufreq.c
index f2c75065ce19..dfd1643b0b2f 100644
--- a/drivers/cpufreq/exynos4210-cpufreq.c
+++ b/drivers/cpufreq/exynos4210-cpufreq.c
@@ -157,4 +157,3 @@ err_moutcore:
157 pr_debug("%s: failed initialization\n", __func__); 157 pr_debug("%s: failed initialization\n", __func__);
158 return -EINVAL; 158 return -EINVAL;
159} 159}
160EXPORT_SYMBOL(exynos4210_cpufreq_init);
diff --git a/drivers/cpufreq/exynos4x12-cpufreq.c b/drivers/cpufreq/exynos4x12-cpufreq.c
index 8683304ce62c..efad5e657f6f 100644
--- a/drivers/cpufreq/exynos4x12-cpufreq.c
+++ b/drivers/cpufreq/exynos4x12-cpufreq.c
@@ -211,4 +211,3 @@ err_moutcore:
211 pr_debug("%s: failed initialization\n", __func__); 211 pr_debug("%s: failed initialization\n", __func__);
212 return -EINVAL; 212 return -EINVAL;
213} 213}
214EXPORT_SYMBOL(exynos4x12_cpufreq_init);
diff --git a/drivers/cpufreq/exynos5250-cpufreq.c b/drivers/cpufreq/exynos5250-cpufreq.c
index 9fae466d7746..8feda86fe42c 100644
--- a/drivers/cpufreq/exynos5250-cpufreq.c
+++ b/drivers/cpufreq/exynos5250-cpufreq.c
@@ -236,4 +236,3 @@ err_moutcore:
236 pr_err("%s: failed initialization\n", __func__); 236 pr_err("%s: failed initialization\n", __func__);
237 return -EINVAL; 237 return -EINVAL;
238} 238}
239EXPORT_SYMBOL(exynos5250_cpufreq_init);
diff --git a/drivers/cpufreq/tegra-cpufreq.c b/drivers/cpufreq/tegra-cpufreq.c
index f42df7ec03c5..b7309c37033d 100644
--- a/drivers/cpufreq/tegra-cpufreq.c
+++ b/drivers/cpufreq/tegra-cpufreq.c
@@ -142,10 +142,8 @@ static int tegra_target(struct cpufreq_policy *policy, unsigned int index)
142 142
143 mutex_lock(&tegra_cpu_lock); 143 mutex_lock(&tegra_cpu_lock);
144 144
145 if (is_suspended) { 145 if (is_suspended)
146 ret = -EBUSY;
147 goto out; 146 goto out;
148 }
149 147
150 freq = freq_table[index].frequency; 148 freq = freq_table[index].frequency;
151 149
diff --git a/drivers/cpuidle/cpuidle.c b/drivers/cpuidle/cpuidle.c
index 2a991e468f78..a55e68f2cfc8 100644
--- a/drivers/cpuidle/cpuidle.c
+++ b/drivers/cpuidle/cpuidle.c
@@ -400,7 +400,7 @@ EXPORT_SYMBOL_GPL(cpuidle_register_device);
400 */ 400 */
401void cpuidle_unregister_device(struct cpuidle_device *dev) 401void cpuidle_unregister_device(struct cpuidle_device *dev)
402{ 402{
403 if (dev->registered == 0) 403 if (!dev || dev->registered == 0)
404 return; 404 return;
405 405
406 cpuidle_pause_and_lock(); 406 cpuidle_pause_and_lock();
diff --git a/drivers/crypto/caam/Kconfig b/drivers/crypto/caam/Kconfig
index ca89f6b84b06..e7555ff4cafd 100644
--- a/drivers/crypto/caam/Kconfig
+++ b/drivers/crypto/caam/Kconfig
@@ -4,16 +4,29 @@ config CRYPTO_DEV_FSL_CAAM
4 help 4 help
5 Enables the driver module for Freescale's Cryptographic Accelerator 5 Enables the driver module for Freescale's Cryptographic Accelerator
6 and Assurance Module (CAAM), also known as the SEC version 4 (SEC4). 6 and Assurance Module (CAAM), also known as the SEC version 4 (SEC4).
7 This module adds a job ring operation interface, and configures h/w 7 This module creates job ring devices, and configures h/w
8 to operate as a DPAA component automatically, depending 8 to operate as a DPAA component automatically, depending
9 on h/w feature availability. 9 on h/w feature availability.
10 10
11 To compile this driver as a module, choose M here: the module 11 To compile this driver as a module, choose M here: the module
12 will be called caam. 12 will be called caam.
13 13
14config CRYPTO_DEV_FSL_CAAM_JR
15 tristate "Freescale CAAM Job Ring driver backend"
16 depends on CRYPTO_DEV_FSL_CAAM
17 default y
18 help
19 Enables the driver module for Job Rings which are part of
20 Freescale's Cryptographic Accelerator
21 and Assurance Module (CAAM). This module adds a job ring operation
22 interface.
23
24 To compile this driver as a module, choose M here: the module
25 will be called caam_jr.
26
14config CRYPTO_DEV_FSL_CAAM_RINGSIZE 27config CRYPTO_DEV_FSL_CAAM_RINGSIZE
15 int "Job Ring size" 28 int "Job Ring size"
16 depends on CRYPTO_DEV_FSL_CAAM 29 depends on CRYPTO_DEV_FSL_CAAM_JR
17 range 2 9 30 range 2 9
18 default "9" 31 default "9"
19 help 32 help
@@ -31,7 +44,7 @@ config CRYPTO_DEV_FSL_CAAM_RINGSIZE
31 44
32config CRYPTO_DEV_FSL_CAAM_INTC 45config CRYPTO_DEV_FSL_CAAM_INTC
33 bool "Job Ring interrupt coalescing" 46 bool "Job Ring interrupt coalescing"
34 depends on CRYPTO_DEV_FSL_CAAM 47 depends on CRYPTO_DEV_FSL_CAAM_JR
35 default n 48 default n
36 help 49 help
37 Enable the Job Ring's interrupt coalescing feature. 50 Enable the Job Ring's interrupt coalescing feature.
@@ -62,7 +75,7 @@ config CRYPTO_DEV_FSL_CAAM_INTC_TIME_THLD
62 75
63config CRYPTO_DEV_FSL_CAAM_CRYPTO_API 76config CRYPTO_DEV_FSL_CAAM_CRYPTO_API
64 tristate "Register algorithm implementations with the Crypto API" 77 tristate "Register algorithm implementations with the Crypto API"
65 depends on CRYPTO_DEV_FSL_CAAM 78 depends on CRYPTO_DEV_FSL_CAAM && CRYPTO_DEV_FSL_CAAM_JR
66 default y 79 default y
67 select CRYPTO_ALGAPI 80 select CRYPTO_ALGAPI
68 select CRYPTO_AUTHENC 81 select CRYPTO_AUTHENC
@@ -76,7 +89,7 @@ config CRYPTO_DEV_FSL_CAAM_CRYPTO_API
76 89
77config CRYPTO_DEV_FSL_CAAM_AHASH_API 90config CRYPTO_DEV_FSL_CAAM_AHASH_API
78 tristate "Register hash algorithm implementations with Crypto API" 91 tristate "Register hash algorithm implementations with Crypto API"
79 depends on CRYPTO_DEV_FSL_CAAM 92 depends on CRYPTO_DEV_FSL_CAAM && CRYPTO_DEV_FSL_CAAM_JR
80 default y 93 default y
81 select CRYPTO_HASH 94 select CRYPTO_HASH
82 help 95 help
@@ -88,7 +101,7 @@ config CRYPTO_DEV_FSL_CAAM_AHASH_API
88 101
89config CRYPTO_DEV_FSL_CAAM_RNG_API 102config CRYPTO_DEV_FSL_CAAM_RNG_API
90 tristate "Register caam device for hwrng API" 103 tristate "Register caam device for hwrng API"
91 depends on CRYPTO_DEV_FSL_CAAM 104 depends on CRYPTO_DEV_FSL_CAAM && CRYPTO_DEV_FSL_CAAM_JR
92 default y 105 default y
93 select CRYPTO_RNG 106 select CRYPTO_RNG
94 select HW_RANDOM 107 select HW_RANDOM
diff --git a/drivers/crypto/caam/Makefile b/drivers/crypto/caam/Makefile
index d56bd0ec65d8..550758a333e7 100644
--- a/drivers/crypto/caam/Makefile
+++ b/drivers/crypto/caam/Makefile
@@ -6,8 +6,10 @@ ifeq ($(CONFIG_CRYPTO_DEV_FSL_CAAM_DEBUG), y)
6endif 6endif
7 7
8obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM) += caam.o 8obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM) += caam.o
9obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_JR) += caam_jr.o
9obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API) += caamalg.o 10obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API) += caamalg.o
10obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API) += caamhash.o 11obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API) += caamhash.o
11obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API) += caamrng.o 12obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API) += caamrng.o
12 13
13caam-objs := ctrl.o jr.o error.o key_gen.o 14caam-objs := ctrl.o
15caam_jr-objs := jr.o key_gen.o error.o
diff --git a/drivers/crypto/caam/caamalg.c b/drivers/crypto/caam/caamalg.c
index 7c63b72ecd75..4cf5dec826e1 100644
--- a/drivers/crypto/caam/caamalg.c
+++ b/drivers/crypto/caam/caamalg.c
@@ -86,6 +86,7 @@
86#else 86#else
87#define debug(format, arg...) 87#define debug(format, arg...)
88#endif 88#endif
89static struct list_head alg_list;
89 90
90/* Set DK bit in class 1 operation if shared */ 91/* Set DK bit in class 1 operation if shared */
91static inline void append_dec_op1(u32 *desc, u32 type) 92static inline void append_dec_op1(u32 *desc, u32 type)
@@ -817,7 +818,7 @@ static void aead_decrypt_done(struct device *jrdev, u32 *desc, u32 err,
817 ivsize, 1); 818 ivsize, 1);
818 print_hex_dump(KERN_ERR, "dst @"__stringify(__LINE__)": ", 819 print_hex_dump(KERN_ERR, "dst @"__stringify(__LINE__)": ",
819 DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->dst), 820 DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->dst),
820 req->cryptlen, 1); 821 req->cryptlen - ctx->authsize, 1);
821#endif 822#endif
822 823
823 if (err) { 824 if (err) {
@@ -971,12 +972,9 @@ static void init_aead_job(u32 *sh_desc, dma_addr_t ptr,
971 (edesc->src_nents ? : 1); 972 (edesc->src_nents ? : 1);
972 in_options = LDST_SGF; 973 in_options = LDST_SGF;
973 } 974 }
974 if (encrypt) 975
975 append_seq_in_ptr(desc, src_dma, req->assoclen + ivsize + 976 append_seq_in_ptr(desc, src_dma, req->assoclen + ivsize + req->cryptlen,
976 req->cryptlen - authsize, in_options); 977 in_options);
977 else
978 append_seq_in_ptr(desc, src_dma, req->assoclen + ivsize +
979 req->cryptlen, in_options);
980 978
981 if (likely(req->src == req->dst)) { 979 if (likely(req->src == req->dst)) {
982 if (all_contig) { 980 if (all_contig) {
@@ -997,7 +995,8 @@ static void init_aead_job(u32 *sh_desc, dma_addr_t ptr,
997 } 995 }
998 } 996 }
999 if (encrypt) 997 if (encrypt)
1000 append_seq_out_ptr(desc, dst_dma, req->cryptlen, out_options); 998 append_seq_out_ptr(desc, dst_dma, req->cryptlen + authsize,
999 out_options);
1001 else 1000 else
1002 append_seq_out_ptr(desc, dst_dma, req->cryptlen - authsize, 1001 append_seq_out_ptr(desc, dst_dma, req->cryptlen - authsize,
1003 out_options); 1002 out_options);
@@ -1047,8 +1046,8 @@ static void init_aead_giv_job(u32 *sh_desc, dma_addr_t ptr,
1047 sec4_sg_index += edesc->assoc_nents + 1 + edesc->src_nents; 1046 sec4_sg_index += edesc->assoc_nents + 1 + edesc->src_nents;
1048 in_options = LDST_SGF; 1047 in_options = LDST_SGF;
1049 } 1048 }
1050 append_seq_in_ptr(desc, src_dma, req->assoclen + ivsize + 1049 append_seq_in_ptr(desc, src_dma, req->assoclen + ivsize + req->cryptlen,
1051 req->cryptlen - authsize, in_options); 1050 in_options);
1052 1051
1053 if (contig & GIV_DST_CONTIG) { 1052 if (contig & GIV_DST_CONTIG) {
1054 dst_dma = edesc->iv_dma; 1053 dst_dma = edesc->iv_dma;
@@ -1065,7 +1064,8 @@ static void init_aead_giv_job(u32 *sh_desc, dma_addr_t ptr,
1065 } 1064 }
1066 } 1065 }
1067 1066
1068 append_seq_out_ptr(desc, dst_dma, ivsize + req->cryptlen, out_options); 1067 append_seq_out_ptr(desc, dst_dma, ivsize + req->cryptlen + authsize,
1068 out_options);
1069} 1069}
1070 1070
1071/* 1071/*
@@ -1129,7 +1129,8 @@ static void init_ablkcipher_job(u32 *sh_desc, dma_addr_t ptr,
1129 * allocate and map the aead extended descriptor 1129 * allocate and map the aead extended descriptor
1130 */ 1130 */
1131static struct aead_edesc *aead_edesc_alloc(struct aead_request *req, 1131static struct aead_edesc *aead_edesc_alloc(struct aead_request *req,
1132 int desc_bytes, bool *all_contig_ptr) 1132 int desc_bytes, bool *all_contig_ptr,
1133 bool encrypt)
1133{ 1134{
1134 struct crypto_aead *aead = crypto_aead_reqtfm(req); 1135 struct crypto_aead *aead = crypto_aead_reqtfm(req);
1135 struct caam_ctx *ctx = crypto_aead_ctx(aead); 1136 struct caam_ctx *ctx = crypto_aead_ctx(aead);
@@ -1144,12 +1145,22 @@ static struct aead_edesc *aead_edesc_alloc(struct aead_request *req,
1144 bool assoc_chained = false, src_chained = false, dst_chained = false; 1145 bool assoc_chained = false, src_chained = false, dst_chained = false;
1145 int ivsize = crypto_aead_ivsize(aead); 1146 int ivsize = crypto_aead_ivsize(aead);
1146 int sec4_sg_index, sec4_sg_len = 0, sec4_sg_bytes; 1147 int sec4_sg_index, sec4_sg_len = 0, sec4_sg_bytes;
1148 unsigned int authsize = ctx->authsize;
1147 1149
1148 assoc_nents = sg_count(req->assoc, req->assoclen, &assoc_chained); 1150 assoc_nents = sg_count(req->assoc, req->assoclen, &assoc_chained);
1149 src_nents = sg_count(req->src, req->cryptlen, &src_chained);
1150 1151
1151 if (unlikely(req->dst != req->src)) 1152 if (unlikely(req->dst != req->src)) {
1152 dst_nents = sg_count(req->dst, req->cryptlen, &dst_chained); 1153 src_nents = sg_count(req->src, req->cryptlen, &src_chained);
1154 dst_nents = sg_count(req->dst,
1155 req->cryptlen +
1156 (encrypt ? authsize : (-authsize)),
1157 &dst_chained);
1158 } else {
1159 src_nents = sg_count(req->src,
1160 req->cryptlen +
1161 (encrypt ? authsize : 0),
1162 &src_chained);
1163 }
1153 1164
1154 sgc = dma_map_sg_chained(jrdev, req->assoc, assoc_nents ? : 1, 1165 sgc = dma_map_sg_chained(jrdev, req->assoc, assoc_nents ? : 1,
1155 DMA_TO_DEVICE, assoc_chained); 1166 DMA_TO_DEVICE, assoc_chained);
@@ -1233,11 +1244,9 @@ static int aead_encrypt(struct aead_request *req)
1233 u32 *desc; 1244 u32 *desc;
1234 int ret = 0; 1245 int ret = 0;
1235 1246
1236 req->cryptlen += ctx->authsize;
1237
1238 /* allocate extended descriptor */ 1247 /* allocate extended descriptor */
1239 edesc = aead_edesc_alloc(req, DESC_JOB_IO_LEN * 1248 edesc = aead_edesc_alloc(req, DESC_JOB_IO_LEN *
1240 CAAM_CMD_SZ, &all_contig); 1249 CAAM_CMD_SZ, &all_contig, true);
1241 if (IS_ERR(edesc)) 1250 if (IS_ERR(edesc))
1242 return PTR_ERR(edesc); 1251 return PTR_ERR(edesc);
1243 1252
@@ -1274,7 +1283,7 @@ static int aead_decrypt(struct aead_request *req)
1274 1283
1275 /* allocate extended descriptor */ 1284 /* allocate extended descriptor */
1276 edesc = aead_edesc_alloc(req, DESC_JOB_IO_LEN * 1285 edesc = aead_edesc_alloc(req, DESC_JOB_IO_LEN *
1277 CAAM_CMD_SZ, &all_contig); 1286 CAAM_CMD_SZ, &all_contig, false);
1278 if (IS_ERR(edesc)) 1287 if (IS_ERR(edesc))
1279 return PTR_ERR(edesc); 1288 return PTR_ERR(edesc);
1280 1289
@@ -1331,7 +1340,8 @@ static struct aead_edesc *aead_giv_edesc_alloc(struct aead_givcrypt_request
1331 src_nents = sg_count(req->src, req->cryptlen, &src_chained); 1340 src_nents = sg_count(req->src, req->cryptlen, &src_chained);
1332 1341
1333 if (unlikely(req->dst != req->src)) 1342 if (unlikely(req->dst != req->src))
1334 dst_nents = sg_count(req->dst, req->cryptlen, &dst_chained); 1343 dst_nents = sg_count(req->dst, req->cryptlen + ctx->authsize,
1344 &dst_chained);
1335 1345
1336 sgc = dma_map_sg_chained(jrdev, req->assoc, assoc_nents ? : 1, 1346 sgc = dma_map_sg_chained(jrdev, req->assoc, assoc_nents ? : 1,
1337 DMA_TO_DEVICE, assoc_chained); 1347 DMA_TO_DEVICE, assoc_chained);
@@ -1425,8 +1435,6 @@ static int aead_givencrypt(struct aead_givcrypt_request *areq)
1425 u32 *desc; 1435 u32 *desc;
1426 int ret = 0; 1436 int ret = 0;
1427 1437
1428 req->cryptlen += ctx->authsize;
1429
1430 /* allocate extended descriptor */ 1438 /* allocate extended descriptor */
1431 edesc = aead_giv_edesc_alloc(areq, DESC_JOB_IO_LEN * 1439 edesc = aead_giv_edesc_alloc(areq, DESC_JOB_IO_LEN *
1432 CAAM_CMD_SZ, &contig); 1440 CAAM_CMD_SZ, &contig);
@@ -2057,7 +2065,6 @@ static struct caam_alg_template driver_algs[] = {
2057 2065
2058struct caam_crypto_alg { 2066struct caam_crypto_alg {
2059 struct list_head entry; 2067 struct list_head entry;
2060 struct device *ctrldev;
2061 int class1_alg_type; 2068 int class1_alg_type;
2062 int class2_alg_type; 2069 int class2_alg_type;
2063 int alg_op; 2070 int alg_op;
@@ -2070,14 +2077,12 @@ static int caam_cra_init(struct crypto_tfm *tfm)
2070 struct caam_crypto_alg *caam_alg = 2077 struct caam_crypto_alg *caam_alg =
2071 container_of(alg, struct caam_crypto_alg, crypto_alg); 2078 container_of(alg, struct caam_crypto_alg, crypto_alg);
2072 struct caam_ctx *ctx = crypto_tfm_ctx(tfm); 2079 struct caam_ctx *ctx = crypto_tfm_ctx(tfm);
2073 struct caam_drv_private *priv = dev_get_drvdata(caam_alg->ctrldev);
2074 int tgt_jr = atomic_inc_return(&priv->tfm_count);
2075 2080
2076 /* 2081 ctx->jrdev = caam_jr_alloc();
2077 * distribute tfms across job rings to ensure in-order 2082 if (IS_ERR(ctx->jrdev)) {
2078 * crypto request processing per tfm 2083 pr_err("Job Ring Device allocation for transform failed\n");
2079 */ 2084 return PTR_ERR(ctx->jrdev);
2080 ctx->jrdev = priv->jrdev[(tgt_jr / 2) % priv->total_jobrs]; 2085 }
2081 2086
2082 /* copy descriptor header template value */ 2087 /* copy descriptor header template value */
2083 ctx->class1_alg_type = OP_TYPE_CLASS1_ALG | caam_alg->class1_alg_type; 2088 ctx->class1_alg_type = OP_TYPE_CLASS1_ALG | caam_alg->class1_alg_type;
@@ -2104,44 +2109,26 @@ static void caam_cra_exit(struct crypto_tfm *tfm)
2104 dma_unmap_single(ctx->jrdev, ctx->sh_desc_givenc_dma, 2109 dma_unmap_single(ctx->jrdev, ctx->sh_desc_givenc_dma,
2105 desc_bytes(ctx->sh_desc_givenc), 2110 desc_bytes(ctx->sh_desc_givenc),
2106 DMA_TO_DEVICE); 2111 DMA_TO_DEVICE);
2112
2113 caam_jr_free(ctx->jrdev);
2107} 2114}
2108 2115
2109static void __exit caam_algapi_exit(void) 2116static void __exit caam_algapi_exit(void)
2110{ 2117{
2111 2118
2112 struct device_node *dev_node;
2113 struct platform_device *pdev;
2114 struct device *ctrldev;
2115 struct caam_drv_private *priv;
2116 struct caam_crypto_alg *t_alg, *n; 2119 struct caam_crypto_alg *t_alg, *n;
2117 2120
2118 dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0"); 2121 if (!alg_list.next)
2119 if (!dev_node) {
2120 dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0");
2121 if (!dev_node)
2122 return;
2123 }
2124
2125 pdev = of_find_device_by_node(dev_node);
2126 if (!pdev)
2127 return;
2128
2129 ctrldev = &pdev->dev;
2130 of_node_put(dev_node);
2131 priv = dev_get_drvdata(ctrldev);
2132
2133 if (!priv->alg_list.next)
2134 return; 2122 return;
2135 2123
2136 list_for_each_entry_safe(t_alg, n, &priv->alg_list, entry) { 2124 list_for_each_entry_safe(t_alg, n, &alg_list, entry) {
2137 crypto_unregister_alg(&t_alg->crypto_alg); 2125 crypto_unregister_alg(&t_alg->crypto_alg);
2138 list_del(&t_alg->entry); 2126 list_del(&t_alg->entry);
2139 kfree(t_alg); 2127 kfree(t_alg);
2140 } 2128 }
2141} 2129}
2142 2130
2143static struct caam_crypto_alg *caam_alg_alloc(struct device *ctrldev, 2131static struct caam_crypto_alg *caam_alg_alloc(struct caam_alg_template
2144 struct caam_alg_template
2145 *template) 2132 *template)
2146{ 2133{
2147 struct caam_crypto_alg *t_alg; 2134 struct caam_crypto_alg *t_alg;
@@ -2149,7 +2136,7 @@ static struct caam_crypto_alg *caam_alg_alloc(struct device *ctrldev,
2149 2136
2150 t_alg = kzalloc(sizeof(struct caam_crypto_alg), GFP_KERNEL); 2137 t_alg = kzalloc(sizeof(struct caam_crypto_alg), GFP_KERNEL);
2151 if (!t_alg) { 2138 if (!t_alg) {
2152 dev_err(ctrldev, "failed to allocate t_alg\n"); 2139 pr_err("failed to allocate t_alg\n");
2153 return ERR_PTR(-ENOMEM); 2140 return ERR_PTR(-ENOMEM);
2154 } 2141 }
2155 2142
@@ -2181,62 +2168,39 @@ static struct caam_crypto_alg *caam_alg_alloc(struct device *ctrldev,
2181 t_alg->class1_alg_type = template->class1_alg_type; 2168 t_alg->class1_alg_type = template->class1_alg_type;
2182 t_alg->class2_alg_type = template->class2_alg_type; 2169 t_alg->class2_alg_type = template->class2_alg_type;
2183 t_alg->alg_op = template->alg_op; 2170 t_alg->alg_op = template->alg_op;
2184 t_alg->ctrldev = ctrldev;
2185 2171
2186 return t_alg; 2172 return t_alg;
2187} 2173}
2188 2174
2189static int __init caam_algapi_init(void) 2175static int __init caam_algapi_init(void)
2190{ 2176{
2191 struct device_node *dev_node;
2192 struct platform_device *pdev;
2193 struct device *ctrldev;
2194 struct caam_drv_private *priv;
2195 int i = 0, err = 0; 2177 int i = 0, err = 0;
2196 2178
2197 dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0"); 2179 INIT_LIST_HEAD(&alg_list);
2198 if (!dev_node) {
2199 dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0");
2200 if (!dev_node)
2201 return -ENODEV;
2202 }
2203
2204 pdev = of_find_device_by_node(dev_node);
2205 if (!pdev)
2206 return -ENODEV;
2207
2208 ctrldev = &pdev->dev;
2209 priv = dev_get_drvdata(ctrldev);
2210 of_node_put(dev_node);
2211
2212 INIT_LIST_HEAD(&priv->alg_list);
2213
2214 atomic_set(&priv->tfm_count, -1);
2215 2180
2216 /* register crypto algorithms the device supports */ 2181 /* register crypto algorithms the device supports */
2217 for (i = 0; i < ARRAY_SIZE(driver_algs); i++) { 2182 for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
2218 /* TODO: check if h/w supports alg */ 2183 /* TODO: check if h/w supports alg */
2219 struct caam_crypto_alg *t_alg; 2184 struct caam_crypto_alg *t_alg;
2220 2185
2221 t_alg = caam_alg_alloc(ctrldev, &driver_algs[i]); 2186 t_alg = caam_alg_alloc(&driver_algs[i]);
2222 if (IS_ERR(t_alg)) { 2187 if (IS_ERR(t_alg)) {
2223 err = PTR_ERR(t_alg); 2188 err = PTR_ERR(t_alg);
2224 dev_warn(ctrldev, "%s alg allocation failed\n", 2189 pr_warn("%s alg allocation failed\n",
2225 driver_algs[i].driver_name); 2190 driver_algs[i].driver_name);
2226 continue; 2191 continue;
2227 } 2192 }
2228 2193
2229 err = crypto_register_alg(&t_alg->crypto_alg); 2194 err = crypto_register_alg(&t_alg->crypto_alg);
2230 if (err) { 2195 if (err) {
2231 dev_warn(ctrldev, "%s alg registration failed\n", 2196 pr_warn("%s alg registration failed\n",
2232 t_alg->crypto_alg.cra_driver_name); 2197 t_alg->crypto_alg.cra_driver_name);
2233 kfree(t_alg); 2198 kfree(t_alg);
2234 } else 2199 } else
2235 list_add_tail(&t_alg->entry, &priv->alg_list); 2200 list_add_tail(&t_alg->entry, &alg_list);
2236 } 2201 }
2237 if (!list_empty(&priv->alg_list)) 2202 if (!list_empty(&alg_list))
2238 dev_info(ctrldev, "%s algorithms registered in /proc/crypto\n", 2203 pr_info("caam algorithms registered in /proc/crypto\n");
2239 (char *)of_get_property(dev_node, "compatible", NULL));
2240 2204
2241 return err; 2205 return err;
2242} 2206}
diff --git a/drivers/crypto/caam/caamhash.c b/drivers/crypto/caam/caamhash.c
index e732bd962e98..0378328f47a7 100644
--- a/drivers/crypto/caam/caamhash.c
+++ b/drivers/crypto/caam/caamhash.c
@@ -94,6 +94,9 @@
94#define debug(format, arg...) 94#define debug(format, arg...)
95#endif 95#endif
96 96
97
98static struct list_head hash_list;
99
97/* ahash per-session context */ 100/* ahash per-session context */
98struct caam_hash_ctx { 101struct caam_hash_ctx {
99 struct device *jrdev; 102 struct device *jrdev;
@@ -1653,7 +1656,6 @@ static struct caam_hash_template driver_hash[] = {
1653 1656
1654struct caam_hash_alg { 1657struct caam_hash_alg {
1655 struct list_head entry; 1658 struct list_head entry;
1656 struct device *ctrldev;
1657 int alg_type; 1659 int alg_type;
1658 int alg_op; 1660 int alg_op;
1659 struct ahash_alg ahash_alg; 1661 struct ahash_alg ahash_alg;
@@ -1670,7 +1672,6 @@ static int caam_hash_cra_init(struct crypto_tfm *tfm)
1670 struct caam_hash_alg *caam_hash = 1672 struct caam_hash_alg *caam_hash =
1671 container_of(alg, struct caam_hash_alg, ahash_alg); 1673 container_of(alg, struct caam_hash_alg, ahash_alg);
1672 struct caam_hash_ctx *ctx = crypto_tfm_ctx(tfm); 1674 struct caam_hash_ctx *ctx = crypto_tfm_ctx(tfm);
1673 struct caam_drv_private *priv = dev_get_drvdata(caam_hash->ctrldev);
1674 /* Sizes for MDHA running digests: MD5, SHA1, 224, 256, 384, 512 */ 1675 /* Sizes for MDHA running digests: MD5, SHA1, 224, 256, 384, 512 */
1675 static const u8 runninglen[] = { HASH_MSG_LEN + MD5_DIGEST_SIZE, 1676 static const u8 runninglen[] = { HASH_MSG_LEN + MD5_DIGEST_SIZE,
1676 HASH_MSG_LEN + SHA1_DIGEST_SIZE, 1677 HASH_MSG_LEN + SHA1_DIGEST_SIZE,
@@ -1678,15 +1679,17 @@ static int caam_hash_cra_init(struct crypto_tfm *tfm)
1678 HASH_MSG_LEN + SHA256_DIGEST_SIZE, 1679 HASH_MSG_LEN + SHA256_DIGEST_SIZE,
1679 HASH_MSG_LEN + 64, 1680 HASH_MSG_LEN + 64,
1680 HASH_MSG_LEN + SHA512_DIGEST_SIZE }; 1681 HASH_MSG_LEN + SHA512_DIGEST_SIZE };
1681 int tgt_jr = atomic_inc_return(&priv->tfm_count);
1682 int ret = 0; 1682 int ret = 0;
1683 1683
1684 /* 1684 /*
1685 * distribute tfms across job rings to ensure in-order 1685 * Get a Job ring from Job Ring driver to ensure in-order
1686 * crypto request processing per tfm 1686 * crypto request processing per tfm
1687 */ 1687 */
1688 ctx->jrdev = priv->jrdev[tgt_jr % priv->total_jobrs]; 1688 ctx->jrdev = caam_jr_alloc();
1689 1689 if (IS_ERR(ctx->jrdev)) {
1690 pr_err("Job Ring Device allocation for transform failed\n");
1691 return PTR_ERR(ctx->jrdev);
1692 }
1690 /* copy descriptor header template value */ 1693 /* copy descriptor header template value */
1691 ctx->alg_type = OP_TYPE_CLASS2_ALG | caam_hash->alg_type; 1694 ctx->alg_type = OP_TYPE_CLASS2_ALG | caam_hash->alg_type;
1692 ctx->alg_op = OP_TYPE_CLASS2_ALG | caam_hash->alg_op; 1695 ctx->alg_op = OP_TYPE_CLASS2_ALG | caam_hash->alg_op;
@@ -1729,35 +1732,18 @@ static void caam_hash_cra_exit(struct crypto_tfm *tfm)
1729 !dma_mapping_error(ctx->jrdev, ctx->sh_desc_finup_dma)) 1732 !dma_mapping_error(ctx->jrdev, ctx->sh_desc_finup_dma))
1730 dma_unmap_single(ctx->jrdev, ctx->sh_desc_finup_dma, 1733 dma_unmap_single(ctx->jrdev, ctx->sh_desc_finup_dma,
1731 desc_bytes(ctx->sh_desc_finup), DMA_TO_DEVICE); 1734 desc_bytes(ctx->sh_desc_finup), DMA_TO_DEVICE);
1735
1736 caam_jr_free(ctx->jrdev);
1732} 1737}
1733 1738
1734static void __exit caam_algapi_hash_exit(void) 1739static void __exit caam_algapi_hash_exit(void)
1735{ 1740{
1736 struct device_node *dev_node;
1737 struct platform_device *pdev;
1738 struct device *ctrldev;
1739 struct caam_drv_private *priv;
1740 struct caam_hash_alg *t_alg, *n; 1741 struct caam_hash_alg *t_alg, *n;
1741 1742
1742 dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0"); 1743 if (!hash_list.next)
1743 if (!dev_node) {
1744 dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0");
1745 if (!dev_node)
1746 return;
1747 }
1748
1749 pdev = of_find_device_by_node(dev_node);
1750 if (!pdev)
1751 return; 1744 return;
1752 1745
1753 ctrldev = &pdev->dev; 1746 list_for_each_entry_safe(t_alg, n, &hash_list, entry) {
1754 of_node_put(dev_node);
1755 priv = dev_get_drvdata(ctrldev);
1756
1757 if (!priv->hash_list.next)
1758 return;
1759
1760 list_for_each_entry_safe(t_alg, n, &priv->hash_list, entry) {
1761 crypto_unregister_ahash(&t_alg->ahash_alg); 1747 crypto_unregister_ahash(&t_alg->ahash_alg);
1762 list_del(&t_alg->entry); 1748 list_del(&t_alg->entry);
1763 kfree(t_alg); 1749 kfree(t_alg);
@@ -1765,7 +1751,7 @@ static void __exit caam_algapi_hash_exit(void)
1765} 1751}
1766 1752
1767static struct caam_hash_alg * 1753static struct caam_hash_alg *
1768caam_hash_alloc(struct device *ctrldev, struct caam_hash_template *template, 1754caam_hash_alloc(struct caam_hash_template *template,
1769 bool keyed) 1755 bool keyed)
1770{ 1756{
1771 struct caam_hash_alg *t_alg; 1757 struct caam_hash_alg *t_alg;
@@ -1774,7 +1760,7 @@ caam_hash_alloc(struct device *ctrldev, struct caam_hash_template *template,
1774 1760
1775 t_alg = kzalloc(sizeof(struct caam_hash_alg), GFP_KERNEL); 1761 t_alg = kzalloc(sizeof(struct caam_hash_alg), GFP_KERNEL);
1776 if (!t_alg) { 1762 if (!t_alg) {
1777 dev_err(ctrldev, "failed to allocate t_alg\n"); 1763 pr_err("failed to allocate t_alg\n");
1778 return ERR_PTR(-ENOMEM); 1764 return ERR_PTR(-ENOMEM);
1779 } 1765 }
1780 1766
@@ -1805,37 +1791,15 @@ caam_hash_alloc(struct device *ctrldev, struct caam_hash_template *template,
1805 1791
1806 t_alg->alg_type = template->alg_type; 1792 t_alg->alg_type = template->alg_type;
1807 t_alg->alg_op = template->alg_op; 1793 t_alg->alg_op = template->alg_op;
1808 t_alg->ctrldev = ctrldev;
1809 1794
1810 return t_alg; 1795 return t_alg;
1811} 1796}
1812 1797
1813static int __init caam_algapi_hash_init(void) 1798static int __init caam_algapi_hash_init(void)
1814{ 1799{
1815 struct device_node *dev_node;
1816 struct platform_device *pdev;
1817 struct device *ctrldev;
1818 struct caam_drv_private *priv;
1819 int i = 0, err = 0; 1800 int i = 0, err = 0;
1820 1801
1821 dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0"); 1802 INIT_LIST_HEAD(&hash_list);
1822 if (!dev_node) {
1823 dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0");
1824 if (!dev_node)
1825 return -ENODEV;
1826 }
1827
1828 pdev = of_find_device_by_node(dev_node);
1829 if (!pdev)
1830 return -ENODEV;
1831
1832 ctrldev = &pdev->dev;
1833 priv = dev_get_drvdata(ctrldev);
1834 of_node_put(dev_node);
1835
1836 INIT_LIST_HEAD(&priv->hash_list);
1837
1838 atomic_set(&priv->tfm_count, -1);
1839 1803
1840 /* register crypto algorithms the device supports */ 1804 /* register crypto algorithms the device supports */
1841 for (i = 0; i < ARRAY_SIZE(driver_hash); i++) { 1805 for (i = 0; i < ARRAY_SIZE(driver_hash); i++) {
@@ -1843,38 +1807,38 @@ static int __init caam_algapi_hash_init(void)
1843 struct caam_hash_alg *t_alg; 1807 struct caam_hash_alg *t_alg;
1844 1808
1845 /* register hmac version */ 1809 /* register hmac version */
1846 t_alg = caam_hash_alloc(ctrldev, &driver_hash[i], true); 1810 t_alg = caam_hash_alloc(&driver_hash[i], true);
1847 if (IS_ERR(t_alg)) { 1811 if (IS_ERR(t_alg)) {
1848 err = PTR_ERR(t_alg); 1812 err = PTR_ERR(t_alg);
1849 dev_warn(ctrldev, "%s alg allocation failed\n", 1813 pr_warn("%s alg allocation failed\n",
1850 driver_hash[i].driver_name); 1814 driver_hash[i].driver_name);
1851 continue; 1815 continue;
1852 } 1816 }
1853 1817
1854 err = crypto_register_ahash(&t_alg->ahash_alg); 1818 err = crypto_register_ahash(&t_alg->ahash_alg);
1855 if (err) { 1819 if (err) {
1856 dev_warn(ctrldev, "%s alg registration failed\n", 1820 pr_warn("%s alg registration failed\n",
1857 t_alg->ahash_alg.halg.base.cra_driver_name); 1821 t_alg->ahash_alg.halg.base.cra_driver_name);
1858 kfree(t_alg); 1822 kfree(t_alg);
1859 } else 1823 } else
1860 list_add_tail(&t_alg->entry, &priv->hash_list); 1824 list_add_tail(&t_alg->entry, &hash_list);
1861 1825
1862 /* register unkeyed version */ 1826 /* register unkeyed version */
1863 t_alg = caam_hash_alloc(ctrldev, &driver_hash[i], false); 1827 t_alg = caam_hash_alloc(&driver_hash[i], false);
1864 if (IS_ERR(t_alg)) { 1828 if (IS_ERR(t_alg)) {
1865 err = PTR_ERR(t_alg); 1829 err = PTR_ERR(t_alg);
1866 dev_warn(ctrldev, "%s alg allocation failed\n", 1830 pr_warn("%s alg allocation failed\n",
1867 driver_hash[i].driver_name); 1831 driver_hash[i].driver_name);
1868 continue; 1832 continue;
1869 } 1833 }
1870 1834
1871 err = crypto_register_ahash(&t_alg->ahash_alg); 1835 err = crypto_register_ahash(&t_alg->ahash_alg);
1872 if (err) { 1836 if (err) {
1873 dev_warn(ctrldev, "%s alg registration failed\n", 1837 pr_warn("%s alg registration failed\n",
1874 t_alg->ahash_alg.halg.base.cra_driver_name); 1838 t_alg->ahash_alg.halg.base.cra_driver_name);
1875 kfree(t_alg); 1839 kfree(t_alg);
1876 } else 1840 } else
1877 list_add_tail(&t_alg->entry, &priv->hash_list); 1841 list_add_tail(&t_alg->entry, &hash_list);
1878 } 1842 }
1879 1843
1880 return err; 1844 return err;
diff --git a/drivers/crypto/caam/caamrng.c b/drivers/crypto/caam/caamrng.c
index d1939a9539c0..28486b19fc36 100644
--- a/drivers/crypto/caam/caamrng.c
+++ b/drivers/crypto/caam/caamrng.c
@@ -273,34 +273,23 @@ static struct hwrng caam_rng = {
273 273
274static void __exit caam_rng_exit(void) 274static void __exit caam_rng_exit(void)
275{ 275{
276 caam_jr_free(rng_ctx.jrdev);
276 hwrng_unregister(&caam_rng); 277 hwrng_unregister(&caam_rng);
277} 278}
278 279
279static int __init caam_rng_init(void) 280static int __init caam_rng_init(void)
280{ 281{
281 struct device_node *dev_node; 282 struct device *dev;
282 struct platform_device *pdev;
283 struct device *ctrldev;
284 struct caam_drv_private *priv;
285
286 dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
287 if (!dev_node) {
288 dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0");
289 if (!dev_node)
290 return -ENODEV;
291 }
292
293 pdev = of_find_device_by_node(dev_node);
294 if (!pdev)
295 return -ENODEV;
296 283
297 ctrldev = &pdev->dev; 284 dev = caam_jr_alloc();
298 priv = dev_get_drvdata(ctrldev); 285 if (IS_ERR(dev)) {
299 of_node_put(dev_node); 286 pr_err("Job Ring Device allocation for transform failed\n");
287 return PTR_ERR(dev);
288 }
300 289
301 caam_init_rng(&rng_ctx, priv->jrdev[0]); 290 caam_init_rng(&rng_ctx, dev);
302 291
303 dev_info(priv->jrdev[0], "registering rng-caam\n"); 292 dev_info(dev, "registering rng-caam\n");
304 return hwrng_register(&caam_rng); 293 return hwrng_register(&caam_rng);
305} 294}
306 295
diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
index bc6d820812b6..63fb1af2c431 100644
--- a/drivers/crypto/caam/ctrl.c
+++ b/drivers/crypto/caam/ctrl.c
@@ -16,82 +16,75 @@
16#include "error.h" 16#include "error.h"
17#include "ctrl.h" 17#include "ctrl.h"
18 18
19static int caam_remove(struct platform_device *pdev)
20{
21 struct device *ctrldev;
22 struct caam_drv_private *ctrlpriv;
23 struct caam_drv_private_jr *jrpriv;
24 struct caam_full __iomem *topregs;
25 int ring, ret = 0;
26
27 ctrldev = &pdev->dev;
28 ctrlpriv = dev_get_drvdata(ctrldev);
29 topregs = (struct caam_full __iomem *)ctrlpriv->ctrl;
30
31 /* shut down JobRs */
32 for (ring = 0; ring < ctrlpriv->total_jobrs; ring++) {
33 ret |= caam_jr_shutdown(ctrlpriv->jrdev[ring]);
34 jrpriv = dev_get_drvdata(ctrlpriv->jrdev[ring]);
35 irq_dispose_mapping(jrpriv->irq);
36 }
37
38 /* Shut down debug views */
39#ifdef CONFIG_DEBUG_FS
40 debugfs_remove_recursive(ctrlpriv->dfs_root);
41#endif
42
43 /* Unmap controller region */
44 iounmap(&topregs->ctrl);
45
46 kfree(ctrlpriv->jrdev);
47 kfree(ctrlpriv);
48
49 return ret;
50}
51
52/* 19/*
53 * Descriptor to instantiate RNG State Handle 0 in normal mode and 20 * Descriptor to instantiate RNG State Handle 0 in normal mode and
54 * load the JDKEK, TDKEK and TDSK registers 21 * load the JDKEK, TDKEK and TDSK registers
55 */ 22 */
56static void build_instantiation_desc(u32 *desc) 23static void build_instantiation_desc(u32 *desc, int handle, int do_sk)
57{ 24{
58 u32 *jump_cmd; 25 u32 *jump_cmd, op_flags;
59 26
60 init_job_desc(desc, 0); 27 init_job_desc(desc, 0);
61 28
29 op_flags = OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
30 (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INIT;
31
62 /* INIT RNG in non-test mode */ 32 /* INIT RNG in non-test mode */
63 append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG | 33 append_operation(desc, op_flags);
64 OP_ALG_AS_INIT); 34
35 if (!handle && do_sk) {
36 /*
37 * For SH0, Secure Keys must be generated as well
38 */
39
40 /* wait for done */
41 jump_cmd = append_jump(desc, JUMP_CLASS_CLASS1);
42 set_jump_tgt_here(desc, jump_cmd);
43
44 /*
45 * load 1 to clear written reg:
46 * resets the done interrrupt and returns the RNG to idle.
47 */
48 append_load_imm_u32(desc, 1, LDST_SRCDST_WORD_CLRW);
49
50 /* Initialize State Handle */
51 append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
52 OP_ALG_AAI_RNG4_SK);
53 }
65 54
66 /* wait for done */ 55 append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT);
67 jump_cmd = append_jump(desc, JUMP_CLASS_CLASS1); 56}
68 set_jump_tgt_here(desc, jump_cmd);
69 57
70 /* 58/* Descriptor for deinstantiation of State Handle 0 of the RNG block. */
71 * load 1 to clear written reg: 59static void build_deinstantiation_desc(u32 *desc, int handle)
72 * resets the done interrupt and returns the RNG to idle. 60{
73 */ 61 init_job_desc(desc, 0);
74 append_load_imm_u32(desc, 1, LDST_SRCDST_WORD_CLRW);
75 62
76 /* generate secure keys (non-test) */ 63 /* Uninstantiate State Handle 0 */
77 append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG | 64 append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
78 OP_ALG_RNG4_SK); 65 (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INITFINAL);
66
67 append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT);
79} 68}
80 69
81static int instantiate_rng(struct device *ctrldev) 70/*
71 * run_descriptor_deco0 - runs a descriptor on DECO0, under direct control of
72 * the software (no JR/QI used).
73 * @ctrldev - pointer to device
74 * @status - descriptor status, after being run
75 *
76 * Return: - 0 if no error occurred
77 * - -ENODEV if the DECO couldn't be acquired
78 * - -EAGAIN if an error occurred while executing the descriptor
79 */
80static inline int run_descriptor_deco0(struct device *ctrldev, u32 *desc,
81 u32 *status)
82{ 82{
83 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev); 83 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
84 struct caam_full __iomem *topregs; 84 struct caam_full __iomem *topregs;
85 unsigned int timeout = 100000; 85 unsigned int timeout = 100000;
86 u32 *desc; 86 u32 deco_dbg_reg, flags;
87 int i, ret = 0; 87 int i;
88
89 desc = kmalloc(CAAM_CMD_SZ * 6, GFP_KERNEL | GFP_DMA);
90 if (!desc) {
91 dev_err(ctrldev, "can't allocate RNG init descriptor memory\n");
92 return -ENOMEM;
93 }
94 build_instantiation_desc(desc);
95 88
96 /* Set the bit to request direct access to DECO0 */ 89 /* Set the bit to request direct access to DECO0 */
97 topregs = (struct caam_full __iomem *)ctrlpriv->ctrl; 90 topregs = (struct caam_full __iomem *)ctrlpriv->ctrl;
@@ -103,36 +96,219 @@ static int instantiate_rng(struct device *ctrldev)
103 96
104 if (!timeout) { 97 if (!timeout) {
105 dev_err(ctrldev, "failed to acquire DECO 0\n"); 98 dev_err(ctrldev, "failed to acquire DECO 0\n");
106 ret = -EIO; 99 clrbits32(&topregs->ctrl.deco_rq, DECORR_RQD0ENABLE);
107 goto out; 100 return -ENODEV;
108 } 101 }
109 102
110 for (i = 0; i < desc_len(desc); i++) 103 for (i = 0; i < desc_len(desc); i++)
111 topregs->deco.descbuf[i] = *(desc + i); 104 wr_reg32(&topregs->deco.descbuf[i], *(desc + i));
105
106 flags = DECO_JQCR_WHL;
107 /*
108 * If the descriptor length is longer than 4 words, then the
109 * FOUR bit in JRCTRL register must be set.
110 */
111 if (desc_len(desc) >= 4)
112 flags |= DECO_JQCR_FOUR;
112 113
113 wr_reg32(&topregs->deco.jr_ctl_hi, DECO_JQCR_WHL | DECO_JQCR_FOUR); 114 /* Instruct the DECO to execute it */
115 wr_reg32(&topregs->deco.jr_ctl_hi, flags);
114 116
115 timeout = 10000000; 117 timeout = 10000000;
116 while ((rd_reg32(&topregs->deco.desc_dbg) & DECO_DBG_VALID) && 118 do {
117 --timeout) 119 deco_dbg_reg = rd_reg32(&topregs->deco.desc_dbg);
120 /*
121 * If an error occured in the descriptor, then
122 * the DECO status field will be set to 0x0D
123 */
124 if ((deco_dbg_reg & DESC_DBG_DECO_STAT_MASK) ==
125 DESC_DBG_DECO_STAT_HOST_ERR)
126 break;
118 cpu_relax(); 127 cpu_relax();
128 } while ((deco_dbg_reg & DESC_DBG_DECO_STAT_VALID) && --timeout);
119 129
120 if (!timeout) { 130 *status = rd_reg32(&topregs->deco.op_status_hi) &
121 dev_err(ctrldev, "failed to instantiate RNG\n"); 131 DECO_OP_STATUS_HI_ERR_MASK;
122 ret = -EIO;
123 }
124 132
133 /* Mark the DECO as free */
125 clrbits32(&topregs->ctrl.deco_rq, DECORR_RQD0ENABLE); 134 clrbits32(&topregs->ctrl.deco_rq, DECORR_RQD0ENABLE);
126out: 135
136 if (!timeout)
137 return -EAGAIN;
138
139 return 0;
140}
141
142/*
143 * instantiate_rng - builds and executes a descriptor on DECO0,
144 * which initializes the RNG block.
145 * @ctrldev - pointer to device
146 * @state_handle_mask - bitmask containing the instantiation status
147 * for the RNG4 state handles which exist in
148 * the RNG4 block: 1 if it's been instantiated
149 * by an external entry, 0 otherwise.
150 * @gen_sk - generate data to be loaded into the JDKEK, TDKEK and TDSK;
151 * Caution: this can be done only once; if the keys need to be
152 * regenerated, a POR is required
153 *
154 * Return: - 0 if no error occurred
155 * - -ENOMEM if there isn't enough memory to allocate the descriptor
156 * - -ENODEV if DECO0 couldn't be acquired
157 * - -EAGAIN if an error occurred when executing the descriptor
158 * f.i. there was a RNG hardware error due to not "good enough"
159 * entropy being aquired.
160 */
161static int instantiate_rng(struct device *ctrldev, int state_handle_mask,
162 int gen_sk)
163{
164 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
165 struct caam_full __iomem *topregs;
166 struct rng4tst __iomem *r4tst;
167 u32 *desc, status, rdsta_val;
168 int ret = 0, sh_idx;
169
170 topregs = (struct caam_full __iomem *)ctrlpriv->ctrl;
171 r4tst = &topregs->ctrl.r4tst[0];
172
173 desc = kmalloc(CAAM_CMD_SZ * 7, GFP_KERNEL);
174 if (!desc)
175 return -ENOMEM;
176
177 for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
178 /*
179 * If the corresponding bit is set, this state handle
180 * was initialized by somebody else, so it's left alone.
181 */
182 if ((1 << sh_idx) & state_handle_mask)
183 continue;
184
185 /* Create the descriptor for instantiating RNG State Handle */
186 build_instantiation_desc(desc, sh_idx, gen_sk);
187
188 /* Try to run it through DECO0 */
189 ret = run_descriptor_deco0(ctrldev, desc, &status);
190
191 /*
192 * If ret is not 0, or descriptor status is not 0, then
193 * something went wrong. No need to try the next state
194 * handle (if available), bail out here.
195 * Also, if for some reason, the State Handle didn't get
196 * instantiated although the descriptor has finished
197 * without any error (HW optimizations for later
198 * CAAM eras), then try again.
199 */
200 rdsta_val =
201 rd_reg32(&topregs->ctrl.r4tst[0].rdsta) & RDSTA_IFMASK;
202 if (status || !(rdsta_val & (1 << sh_idx)))
203 ret = -EAGAIN;
204 if (ret)
205 break;
206
207 dev_info(ctrldev, "Instantiated RNG4 SH%d\n", sh_idx);
208 /* Clear the contents before recreating the descriptor */
209 memset(desc, 0x00, CAAM_CMD_SZ * 7);
210 }
211
127 kfree(desc); 212 kfree(desc);
213
128 return ret; 214 return ret;
129} 215}
130 216
131/* 217/*
132 * By default, the TRNG runs for 200 clocks per sample; 218 * deinstantiate_rng - builds and executes a descriptor on DECO0,
133 * 1600 clocks per sample generates better entropy. 219 * which deinitializes the RNG block.
220 * @ctrldev - pointer to device
221 * @state_handle_mask - bitmask containing the instantiation status
222 * for the RNG4 state handles which exist in
223 * the RNG4 block: 1 if it's been instantiated
224 *
225 * Return: - 0 if no error occurred
226 * - -ENOMEM if there isn't enough memory to allocate the descriptor
227 * - -ENODEV if DECO0 couldn't be acquired
228 * - -EAGAIN if an error occurred when executing the descriptor
134 */ 229 */
135static void kick_trng(struct platform_device *pdev) 230static int deinstantiate_rng(struct device *ctrldev, int state_handle_mask)
231{
232 u32 *desc, status;
233 int sh_idx, ret = 0;
234
235 desc = kmalloc(CAAM_CMD_SZ * 3, GFP_KERNEL);
236 if (!desc)
237 return -ENOMEM;
238
239 for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
240 /*
241 * If the corresponding bit is set, then it means the state
242 * handle was initialized by us, and thus it needs to be
243 * deintialized as well
244 */
245 if ((1 << sh_idx) & state_handle_mask) {
246 /*
247 * Create the descriptor for deinstantating this state
248 * handle
249 */
250 build_deinstantiation_desc(desc, sh_idx);
251
252 /* Try to run it through DECO0 */
253 ret = run_descriptor_deco0(ctrldev, desc, &status);
254
255 if (ret || status) {
256 dev_err(ctrldev,
257 "Failed to deinstantiate RNG4 SH%d\n",
258 sh_idx);
259 break;
260 }
261 dev_info(ctrldev, "Deinstantiated RNG4 SH%d\n", sh_idx);
262 }
263 }
264
265 kfree(desc);
266
267 return ret;
268}
269
270static int caam_remove(struct platform_device *pdev)
271{
272 struct device *ctrldev;
273 struct caam_drv_private *ctrlpriv;
274 struct caam_full __iomem *topregs;
275 int ring, ret = 0;
276
277 ctrldev = &pdev->dev;
278 ctrlpriv = dev_get_drvdata(ctrldev);
279 topregs = (struct caam_full __iomem *)ctrlpriv->ctrl;
280
281 /* Remove platform devices for JobRs */
282 for (ring = 0; ring < ctrlpriv->total_jobrs; ring++) {
283 if (ctrlpriv->jrpdev[ring])
284 of_device_unregister(ctrlpriv->jrpdev[ring]);
285 }
286
287 /* De-initialize RNG state handles initialized by this driver. */
288 if (ctrlpriv->rng4_sh_init)
289 deinstantiate_rng(ctrldev, ctrlpriv->rng4_sh_init);
290
291 /* Shut down debug views */
292#ifdef CONFIG_DEBUG_FS
293 debugfs_remove_recursive(ctrlpriv->dfs_root);
294#endif
295
296 /* Unmap controller region */
297 iounmap(&topregs->ctrl);
298
299 kfree(ctrlpriv->jrpdev);
300 kfree(ctrlpriv);
301
302 return ret;
303}
304
305/*
306 * kick_trng - sets the various parameters for enabling the initialization
307 * of the RNG4 block in CAAM
308 * @pdev - pointer to the platform device
309 * @ent_delay - Defines the length (in system clocks) of each entropy sample.
310 */
311static void kick_trng(struct platform_device *pdev, int ent_delay)
136{ 312{
137 struct device *ctrldev = &pdev->dev; 313 struct device *ctrldev = &pdev->dev;
138 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev); 314 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
@@ -145,14 +321,31 @@ static void kick_trng(struct platform_device *pdev)
145 321
146 /* put RNG4 into program mode */ 322 /* put RNG4 into program mode */
147 setbits32(&r4tst->rtmctl, RTMCTL_PRGM); 323 setbits32(&r4tst->rtmctl, RTMCTL_PRGM);
148 /* 1600 clocks per sample */ 324
325 /*
326 * Performance-wise, it does not make sense to
327 * set the delay to a value that is lower
328 * than the last one that worked (i.e. the state handles
329 * were instantiated properly. Thus, instead of wasting
330 * time trying to set the values controlling the sample
331 * frequency, the function simply returns.
332 */
333 val = (rd_reg32(&r4tst->rtsdctl) & RTSDCTL_ENT_DLY_MASK)
334 >> RTSDCTL_ENT_DLY_SHIFT;
335 if (ent_delay <= val) {
336 /* put RNG4 into run mode */
337 clrbits32(&r4tst->rtmctl, RTMCTL_PRGM);
338 return;
339 }
340
149 val = rd_reg32(&r4tst->rtsdctl); 341 val = rd_reg32(&r4tst->rtsdctl);
150 val = (val & ~RTSDCTL_ENT_DLY_MASK) | (1600 << RTSDCTL_ENT_DLY_SHIFT); 342 val = (val & ~RTSDCTL_ENT_DLY_MASK) |
343 (ent_delay << RTSDCTL_ENT_DLY_SHIFT);
151 wr_reg32(&r4tst->rtsdctl, val); 344 wr_reg32(&r4tst->rtsdctl, val);
152 /* min. freq. count */ 345 /* min. freq. count, equal to 1/4 of the entropy sample length */
153 wr_reg32(&r4tst->rtfrqmin, 400); 346 wr_reg32(&r4tst->rtfrqmin, ent_delay >> 2);
154 /* max. freq. count */ 347 /* max. freq. count, equal to 8 times the entropy sample length */
155 wr_reg32(&r4tst->rtfrqmax, 6400); 348 wr_reg32(&r4tst->rtfrqmax, ent_delay << 3);
156 /* put RNG4 into run mode */ 349 /* put RNG4 into run mode */
157 clrbits32(&r4tst->rtmctl, RTMCTL_PRGM); 350 clrbits32(&r4tst->rtmctl, RTMCTL_PRGM);
158} 351}
@@ -193,7 +386,7 @@ EXPORT_SYMBOL(caam_get_era);
193/* Probe routine for CAAM top (controller) level */ 386/* Probe routine for CAAM top (controller) level */
194static int caam_probe(struct platform_device *pdev) 387static int caam_probe(struct platform_device *pdev)
195{ 388{
196 int ret, ring, rspec; 389 int ret, ring, rspec, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
197 u64 caam_id; 390 u64 caam_id;
198 struct device *dev; 391 struct device *dev;
199 struct device_node *nprop, *np; 392 struct device_node *nprop, *np;
@@ -258,8 +451,9 @@ static int caam_probe(struct platform_device *pdev)
258 rspec++; 451 rspec++;
259 } 452 }
260 453
261 ctrlpriv->jrdev = kzalloc(sizeof(struct device *) * rspec, GFP_KERNEL); 454 ctrlpriv->jrpdev = kzalloc(sizeof(struct platform_device *) * rspec,
262 if (ctrlpriv->jrdev == NULL) { 455 GFP_KERNEL);
456 if (ctrlpriv->jrpdev == NULL) {
263 iounmap(&topregs->ctrl); 457 iounmap(&topregs->ctrl);
264 return -ENOMEM; 458 return -ENOMEM;
265 } 459 }
@@ -267,13 +461,24 @@ static int caam_probe(struct platform_device *pdev)
267 ring = 0; 461 ring = 0;
268 ctrlpriv->total_jobrs = 0; 462 ctrlpriv->total_jobrs = 0;
269 for_each_compatible_node(np, NULL, "fsl,sec-v4.0-job-ring") { 463 for_each_compatible_node(np, NULL, "fsl,sec-v4.0-job-ring") {
270 caam_jr_probe(pdev, np, ring); 464 ctrlpriv->jrpdev[ring] =
465 of_platform_device_create(np, NULL, dev);
466 if (!ctrlpriv->jrpdev[ring]) {
467 pr_warn("JR%d Platform device creation error\n", ring);
468 continue;
469 }
271 ctrlpriv->total_jobrs++; 470 ctrlpriv->total_jobrs++;
272 ring++; 471 ring++;
273 } 472 }
274 if (!ring) { 473 if (!ring) {
275 for_each_compatible_node(np, NULL, "fsl,sec4.0-job-ring") { 474 for_each_compatible_node(np, NULL, "fsl,sec4.0-job-ring") {
276 caam_jr_probe(pdev, np, ring); 475 ctrlpriv->jrpdev[ring] =
476 of_platform_device_create(np, NULL, dev);
477 if (!ctrlpriv->jrpdev[ring]) {
478 pr_warn("JR%d Platform device creation error\n",
479 ring);
480 continue;
481 }
277 ctrlpriv->total_jobrs++; 482 ctrlpriv->total_jobrs++;
278 ring++; 483 ring++;
279 } 484 }
@@ -299,16 +504,55 @@ static int caam_probe(struct platform_device *pdev)
299 504
300 /* 505 /*
301 * If SEC has RNG version >= 4 and RNG state handle has not been 506 * If SEC has RNG version >= 4 and RNG state handle has not been
302 * already instantiated ,do RNG instantiation 507 * already instantiated, do RNG instantiation
303 */ 508 */
304 if ((cha_vid & CHA_ID_RNG_MASK) >> CHA_ID_RNG_SHIFT >= 4 && 509 if ((cha_vid & CHA_ID_RNG_MASK) >> CHA_ID_RNG_SHIFT >= 4) {
305 !(rd_reg32(&topregs->ctrl.r4tst[0].rdsta) & RDSTA_IF0)) { 510 ctrlpriv->rng4_sh_init =
306 kick_trng(pdev); 511 rd_reg32(&topregs->ctrl.r4tst[0].rdsta);
307 ret = instantiate_rng(dev); 512 /*
513 * If the secure keys (TDKEK, JDKEK, TDSK), were already
514 * generated, signal this to the function that is instantiating
515 * the state handles. An error would occur if RNG4 attempts
516 * to regenerate these keys before the next POR.
517 */
518 gen_sk = ctrlpriv->rng4_sh_init & RDSTA_SKVN ? 0 : 1;
519 ctrlpriv->rng4_sh_init &= RDSTA_IFMASK;
520 do {
521 int inst_handles =
522 rd_reg32(&topregs->ctrl.r4tst[0].rdsta) &
523 RDSTA_IFMASK;
524 /*
525 * If either SH were instantiated by somebody else
526 * (e.g. u-boot) then it is assumed that the entropy
527 * parameters are properly set and thus the function
528 * setting these (kick_trng(...)) is skipped.
529 * Also, if a handle was instantiated, do not change
530 * the TRNG parameters.
531 */
532 if (!(ctrlpriv->rng4_sh_init || inst_handles)) {
533 kick_trng(pdev, ent_delay);
534 ent_delay += 400;
535 }
536 /*
537 * if instantiate_rng(...) fails, the loop will rerun
538 * and the kick_trng(...) function will modfiy the
539 * upper and lower limits of the entropy sampling
540 * interval, leading to a sucessful initialization of
541 * the RNG.
542 */
543 ret = instantiate_rng(dev, inst_handles,
544 gen_sk);
545 } while ((ret == -EAGAIN) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
308 if (ret) { 546 if (ret) {
547 dev_err(dev, "failed to instantiate RNG");
309 caam_remove(pdev); 548 caam_remove(pdev);
310 return ret; 549 return ret;
311 } 550 }
551 /*
552 * Set handles init'ed by this module as the complement of the
553 * already initialized ones
554 */
555 ctrlpriv->rng4_sh_init = ~ctrlpriv->rng4_sh_init & RDSTA_IFMASK;
312 556
313 /* Enable RDB bit so that RNG works faster */ 557 /* Enable RDB bit so that RNG works faster */
314 setbits32(&topregs->ctrl.scfgr, SCFGR_RDBENABLE); 558 setbits32(&topregs->ctrl.scfgr, SCFGR_RDBENABLE);
diff --git a/drivers/crypto/caam/desc.h b/drivers/crypto/caam/desc.h
index 53b296f78b0d..7e4500f18df6 100644
--- a/drivers/crypto/caam/desc.h
+++ b/drivers/crypto/caam/desc.h
@@ -1155,8 +1155,15 @@ struct sec4_sg_entry {
1155 1155
1156/* randomizer AAI set */ 1156/* randomizer AAI set */
1157#define OP_ALG_AAI_RNG (0x00 << OP_ALG_AAI_SHIFT) 1157#define OP_ALG_AAI_RNG (0x00 << OP_ALG_AAI_SHIFT)
1158#define OP_ALG_AAI_RNG_NOZERO (0x10 << OP_ALG_AAI_SHIFT) 1158#define OP_ALG_AAI_RNG_NZB (0x10 << OP_ALG_AAI_SHIFT)
1159#define OP_ALG_AAI_RNG_ODD (0x20 << OP_ALG_AAI_SHIFT) 1159#define OP_ALG_AAI_RNG_OBP (0x20 << OP_ALG_AAI_SHIFT)
1160
1161/* RNG4 AAI set */
1162#define OP_ALG_AAI_RNG4_SH_0 (0x00 << OP_ALG_AAI_SHIFT)
1163#define OP_ALG_AAI_RNG4_SH_1 (0x01 << OP_ALG_AAI_SHIFT)
1164#define OP_ALG_AAI_RNG4_PS (0x40 << OP_ALG_AAI_SHIFT)
1165#define OP_ALG_AAI_RNG4_AI (0x80 << OP_ALG_AAI_SHIFT)
1166#define OP_ALG_AAI_RNG4_SK (0x100 << OP_ALG_AAI_SHIFT)
1160 1167
1161/* hmac/smac AAI set */ 1168/* hmac/smac AAI set */
1162#define OP_ALG_AAI_HASH (0x00 << OP_ALG_AAI_SHIFT) 1169#define OP_ALG_AAI_HASH (0x00 << OP_ALG_AAI_SHIFT)
@@ -1178,12 +1185,6 @@ struct sec4_sg_entry {
1178#define OP_ALG_AAI_GSM (0x10 << OP_ALG_AAI_SHIFT) 1185#define OP_ALG_AAI_GSM (0x10 << OP_ALG_AAI_SHIFT)
1179#define OP_ALG_AAI_EDGE (0x20 << OP_ALG_AAI_SHIFT) 1186#define OP_ALG_AAI_EDGE (0x20 << OP_ALG_AAI_SHIFT)
1180 1187
1181/* RNG4 set */
1182#define OP_ALG_RNG4_SHIFT 4
1183#define OP_ALG_RNG4_MASK (0x1f3 << OP_ALG_RNG4_SHIFT)
1184
1185#define OP_ALG_RNG4_SK (0x100 << OP_ALG_RNG4_SHIFT)
1186
1187#define OP_ALG_AS_SHIFT 2 1188#define OP_ALG_AS_SHIFT 2
1188#define OP_ALG_AS_MASK (0x3 << OP_ALG_AS_SHIFT) 1189#define OP_ALG_AS_MASK (0x3 << OP_ALG_AS_SHIFT)
1189#define OP_ALG_AS_UPDATE (0 << OP_ALG_AS_SHIFT) 1190#define OP_ALG_AS_UPDATE (0 << OP_ALG_AS_SHIFT)
diff --git a/drivers/crypto/caam/intern.h b/drivers/crypto/caam/intern.h
index 34c4b9f7fbfa..6d85fcc5bd0a 100644
--- a/drivers/crypto/caam/intern.h
+++ b/drivers/crypto/caam/intern.h
@@ -37,13 +37,16 @@ struct caam_jrentry_info {
37 37
38/* Private sub-storage for a single JobR */ 38/* Private sub-storage for a single JobR */
39struct caam_drv_private_jr { 39struct caam_drv_private_jr {
40 struct device *parentdev; /* points back to controller dev */ 40 struct list_head list_node; /* Job Ring device list */
41 struct platform_device *jr_pdev;/* points to platform device for JR */ 41 struct device *dev;
42 int ridx; 42 int ridx;
43 struct caam_job_ring __iomem *rregs; /* JobR's register space */ 43 struct caam_job_ring __iomem *rregs; /* JobR's register space */
44 struct tasklet_struct irqtask; 44 struct tasklet_struct irqtask;
45 int irq; /* One per queue */ 45 int irq; /* One per queue */
46 46
47 /* Number of scatterlist crypt transforms active on the JobR */
48 atomic_t tfm_count ____cacheline_aligned;
49
47 /* Job ring info */ 50 /* Job ring info */
48 int ringsize; /* Size of rings (assume input = output) */ 51 int ringsize; /* Size of rings (assume input = output) */
49 struct caam_jrentry_info *entinfo; /* Alloc'ed 1 per ring entry */ 52 struct caam_jrentry_info *entinfo; /* Alloc'ed 1 per ring entry */
@@ -63,7 +66,7 @@ struct caam_drv_private_jr {
63struct caam_drv_private { 66struct caam_drv_private {
64 67
65 struct device *dev; 68 struct device *dev;
66 struct device **jrdev; /* Alloc'ed array per sub-device */ 69 struct platform_device **jrpdev; /* Alloc'ed array per sub-device */
67 struct platform_device *pdev; 70 struct platform_device *pdev;
68 71
69 /* Physical-presence section */ 72 /* Physical-presence section */
@@ -80,12 +83,11 @@ struct caam_drv_private {
80 u8 qi_present; /* Nonzero if QI present in device */ 83 u8 qi_present; /* Nonzero if QI present in device */
81 int secvio_irq; /* Security violation interrupt number */ 84 int secvio_irq; /* Security violation interrupt number */
82 85
83 /* which jr allocated to scatterlist crypto */ 86#define RNG4_MAX_HANDLES 2
84 atomic_t tfm_count ____cacheline_aligned; 87 /* RNG4 block */
85 /* list of registered crypto algorithms (mk generic context handle?) */ 88 u32 rng4_sh_init; /* This bitmap shows which of the State
86 struct list_head alg_list; 89 Handles of the RNG4 block are initialized
87 /* list of registered hash algorithms (mk generic context handle?) */ 90 by this driver */
88 struct list_head hash_list;
89 91
90 /* 92 /*
91 * debugfs entries for developer view into driver/device 93 * debugfs entries for developer view into driver/device
diff --git a/drivers/crypto/caam/jr.c b/drivers/crypto/caam/jr.c
index bdb786d5a5e5..1d80bd3636c5 100644
--- a/drivers/crypto/caam/jr.c
+++ b/drivers/crypto/caam/jr.c
@@ -6,6 +6,7 @@
6 */ 6 */
7 7
8#include <linux/of_irq.h> 8#include <linux/of_irq.h>
9#include <linux/of_address.h>
9 10
10#include "compat.h" 11#include "compat.h"
11#include "regs.h" 12#include "regs.h"
@@ -13,6 +14,113 @@
13#include "desc.h" 14#include "desc.h"
14#include "intern.h" 15#include "intern.h"
15 16
17struct jr_driver_data {
18 /* List of Physical JobR's with the Driver */
19 struct list_head jr_list;
20 spinlock_t jr_alloc_lock; /* jr_list lock */
21} ____cacheline_aligned;
22
23static struct jr_driver_data driver_data;
24
25static int caam_reset_hw_jr(struct device *dev)
26{
27 struct caam_drv_private_jr *jrp = dev_get_drvdata(dev);
28 unsigned int timeout = 100000;
29
30 /*
31 * mask interrupts since we are going to poll
32 * for reset completion status
33 */
34 setbits32(&jrp->rregs->rconfig_lo, JRCFG_IMSK);
35
36 /* initiate flush (required prior to reset) */
37 wr_reg32(&jrp->rregs->jrcommand, JRCR_RESET);
38 while (((rd_reg32(&jrp->rregs->jrintstatus) & JRINT_ERR_HALT_MASK) ==
39 JRINT_ERR_HALT_INPROGRESS) && --timeout)
40 cpu_relax();
41
42 if ((rd_reg32(&jrp->rregs->jrintstatus) & JRINT_ERR_HALT_MASK) !=
43 JRINT_ERR_HALT_COMPLETE || timeout == 0) {
44 dev_err(dev, "failed to flush job ring %d\n", jrp->ridx);
45 return -EIO;
46 }
47
48 /* initiate reset */
49 timeout = 100000;
50 wr_reg32(&jrp->rregs->jrcommand, JRCR_RESET);
51 while ((rd_reg32(&jrp->rregs->jrcommand) & JRCR_RESET) && --timeout)
52 cpu_relax();
53
54 if (timeout == 0) {
55 dev_err(dev, "failed to reset job ring %d\n", jrp->ridx);
56 return -EIO;
57 }
58
59 /* unmask interrupts */
60 clrbits32(&jrp->rregs->rconfig_lo, JRCFG_IMSK);
61
62 return 0;
63}
64
65/*
66 * Shutdown JobR independent of platform property code
67 */
68int caam_jr_shutdown(struct device *dev)
69{
70 struct caam_drv_private_jr *jrp = dev_get_drvdata(dev);
71 dma_addr_t inpbusaddr, outbusaddr;
72 int ret;
73
74 ret = caam_reset_hw_jr(dev);
75
76 tasklet_kill(&jrp->irqtask);
77
78 /* Release interrupt */
79 free_irq(jrp->irq, dev);
80
81 /* Free rings */
82 inpbusaddr = rd_reg64(&jrp->rregs->inpring_base);
83 outbusaddr = rd_reg64(&jrp->rregs->outring_base);
84 dma_free_coherent(dev, sizeof(dma_addr_t) * JOBR_DEPTH,
85 jrp->inpring, inpbusaddr);
86 dma_free_coherent(dev, sizeof(struct jr_outentry) * JOBR_DEPTH,
87 jrp->outring, outbusaddr);
88 kfree(jrp->entinfo);
89
90 return ret;
91}
92
93static int caam_jr_remove(struct platform_device *pdev)
94{
95 int ret;
96 struct device *jrdev;
97 struct caam_drv_private_jr *jrpriv;
98
99 jrdev = &pdev->dev;
100 jrpriv = dev_get_drvdata(jrdev);
101
102 /*
103 * Return EBUSY if job ring already allocated.
104 */
105 if (atomic_read(&jrpriv->tfm_count)) {
106 dev_err(jrdev, "Device is busy\n");
107 return -EBUSY;
108 }
109
110 /* Remove the node from Physical JobR list maintained by driver */
111 spin_lock(&driver_data.jr_alloc_lock);
112 list_del(&jrpriv->list_node);
113 spin_unlock(&driver_data.jr_alloc_lock);
114
115 /* Release ring */
116 ret = caam_jr_shutdown(jrdev);
117 if (ret)
118 dev_err(jrdev, "Failed to shut down job ring\n");
119 irq_dispose_mapping(jrpriv->irq);
120
121 return ret;
122}
123
16/* Main per-ring interrupt handler */ 124/* Main per-ring interrupt handler */
17static irqreturn_t caam_jr_interrupt(int irq, void *st_dev) 125static irqreturn_t caam_jr_interrupt(int irq, void *st_dev)
18{ 126{
@@ -128,6 +236,59 @@ static void caam_jr_dequeue(unsigned long devarg)
128} 236}
129 237
130/** 238/**
239 * caam_jr_alloc() - Alloc a job ring for someone to use as needed.
240 *
241 * returns : pointer to the newly allocated physical
242 * JobR dev can be written to if successful.
243 **/
244struct device *caam_jr_alloc(void)
245{
246 struct caam_drv_private_jr *jrpriv, *min_jrpriv = NULL;
247 struct device *dev = NULL;
248 int min_tfm_cnt = INT_MAX;
249 int tfm_cnt;
250
251 spin_lock(&driver_data.jr_alloc_lock);
252
253 if (list_empty(&driver_data.jr_list)) {
254 spin_unlock(&driver_data.jr_alloc_lock);
255 return ERR_PTR(-ENODEV);
256 }
257
258 list_for_each_entry(jrpriv, &driver_data.jr_list, list_node) {
259 tfm_cnt = atomic_read(&jrpriv->tfm_count);
260 if (tfm_cnt < min_tfm_cnt) {
261 min_tfm_cnt = tfm_cnt;
262 min_jrpriv = jrpriv;
263 }
264 if (!min_tfm_cnt)
265 break;
266 }
267
268 if (min_jrpriv) {
269 atomic_inc(&min_jrpriv->tfm_count);
270 dev = min_jrpriv->dev;
271 }
272 spin_unlock(&driver_data.jr_alloc_lock);
273
274 return dev;
275}
276EXPORT_SYMBOL(caam_jr_alloc);
277
278/**
279 * caam_jr_free() - Free the Job Ring
280 * @rdev - points to the dev that identifies the Job ring to
281 * be released.
282 **/
283void caam_jr_free(struct device *rdev)
284{
285 struct caam_drv_private_jr *jrpriv = dev_get_drvdata(rdev);
286
287 atomic_dec(&jrpriv->tfm_count);
288}
289EXPORT_SYMBOL(caam_jr_free);
290
291/**
131 * caam_jr_enqueue() - Enqueue a job descriptor head. Returns 0 if OK, 292 * caam_jr_enqueue() - Enqueue a job descriptor head. Returns 0 if OK,
132 * -EBUSY if the queue is full, -EIO if it cannot map the caller's 293 * -EBUSY if the queue is full, -EIO if it cannot map the caller's
133 * descriptor. 294 * descriptor.
@@ -207,46 +368,6 @@ int caam_jr_enqueue(struct device *dev, u32 *desc,
207} 368}
208EXPORT_SYMBOL(caam_jr_enqueue); 369EXPORT_SYMBOL(caam_jr_enqueue);
209 370
210static int caam_reset_hw_jr(struct device *dev)
211{
212 struct caam_drv_private_jr *jrp = dev_get_drvdata(dev);
213 unsigned int timeout = 100000;
214
215 /*
216 * mask interrupts since we are going to poll
217 * for reset completion status
218 */
219 setbits32(&jrp->rregs->rconfig_lo, JRCFG_IMSK);
220
221 /* initiate flush (required prior to reset) */
222 wr_reg32(&jrp->rregs->jrcommand, JRCR_RESET);
223 while (((rd_reg32(&jrp->rregs->jrintstatus) & JRINT_ERR_HALT_MASK) ==
224 JRINT_ERR_HALT_INPROGRESS) && --timeout)
225 cpu_relax();
226
227 if ((rd_reg32(&jrp->rregs->jrintstatus) & JRINT_ERR_HALT_MASK) !=
228 JRINT_ERR_HALT_COMPLETE || timeout == 0) {
229 dev_err(dev, "failed to flush job ring %d\n", jrp->ridx);
230 return -EIO;
231 }
232
233 /* initiate reset */
234 timeout = 100000;
235 wr_reg32(&jrp->rregs->jrcommand, JRCR_RESET);
236 while ((rd_reg32(&jrp->rregs->jrcommand) & JRCR_RESET) && --timeout)
237 cpu_relax();
238
239 if (timeout == 0) {
240 dev_err(dev, "failed to reset job ring %d\n", jrp->ridx);
241 return -EIO;
242 }
243
244 /* unmask interrupts */
245 clrbits32(&jrp->rregs->rconfig_lo, JRCFG_IMSK);
246
247 return 0;
248}
249
250/* 371/*
251 * Init JobR independent of platform property detection 372 * Init JobR independent of platform property detection
252 */ 373 */
@@ -262,7 +383,7 @@ static int caam_jr_init(struct device *dev)
262 383
263 /* Connect job ring interrupt handler. */ 384 /* Connect job ring interrupt handler. */
264 error = request_irq(jrp->irq, caam_jr_interrupt, IRQF_SHARED, 385 error = request_irq(jrp->irq, caam_jr_interrupt, IRQF_SHARED,
265 "caam-jobr", dev); 386 dev_name(dev), dev);
266 if (error) { 387 if (error) {
267 dev_err(dev, "can't connect JobR %d interrupt (%d)\n", 388 dev_err(dev, "can't connect JobR %d interrupt (%d)\n",
268 jrp->ridx, jrp->irq); 389 jrp->ridx, jrp->irq);
@@ -318,86 +439,43 @@ static int caam_jr_init(struct device *dev)
318 return 0; 439 return 0;
319} 440}
320 441
321/*
322 * Shutdown JobR independent of platform property code
323 */
324int caam_jr_shutdown(struct device *dev)
325{
326 struct caam_drv_private_jr *jrp = dev_get_drvdata(dev);
327 dma_addr_t inpbusaddr, outbusaddr;
328 int ret;
329
330 ret = caam_reset_hw_jr(dev);
331
332 tasklet_kill(&jrp->irqtask);
333
334 /* Release interrupt */
335 free_irq(jrp->irq, dev);
336
337 /* Free rings */
338 inpbusaddr = rd_reg64(&jrp->rregs->inpring_base);
339 outbusaddr = rd_reg64(&jrp->rregs->outring_base);
340 dma_free_coherent(dev, sizeof(dma_addr_t) * JOBR_DEPTH,
341 jrp->inpring, inpbusaddr);
342 dma_free_coherent(dev, sizeof(struct jr_outentry) * JOBR_DEPTH,
343 jrp->outring, outbusaddr);
344 kfree(jrp->entinfo);
345 of_device_unregister(jrp->jr_pdev);
346
347 return ret;
348}
349 442
350/* 443/*
351 * Probe routine for each detected JobR subsystem. It assumes that 444 * Probe routine for each detected JobR subsystem.
352 * property detection was picked up externally.
353 */ 445 */
354int caam_jr_probe(struct platform_device *pdev, struct device_node *np, 446static int caam_jr_probe(struct platform_device *pdev)
355 int ring)
356{ 447{
357 struct device *ctrldev, *jrdev; 448 struct device *jrdev;
358 struct platform_device *jr_pdev; 449 struct device_node *nprop;
359 struct caam_drv_private *ctrlpriv; 450 struct caam_job_ring __iomem *ctrl;
360 struct caam_drv_private_jr *jrpriv; 451 struct caam_drv_private_jr *jrpriv;
361 u32 *jroffset; 452 static int total_jobrs;
362 int error; 453 int error;
363 454
364 ctrldev = &pdev->dev; 455 jrdev = &pdev->dev;
365 ctrlpriv = dev_get_drvdata(ctrldev);
366
367 jrpriv = kmalloc(sizeof(struct caam_drv_private_jr), 456 jrpriv = kmalloc(sizeof(struct caam_drv_private_jr),
368 GFP_KERNEL); 457 GFP_KERNEL);
369 if (jrpriv == NULL) { 458 if (!jrpriv)
370 dev_err(ctrldev, "can't alloc private mem for job ring %d\n",
371 ring);
372 return -ENOMEM; 459 return -ENOMEM;
373 }
374 jrpriv->parentdev = ctrldev; /* point back to parent */
375 jrpriv->ridx = ring; /* save ring identity relative to detection */
376 460
377 /* 461 dev_set_drvdata(jrdev, jrpriv);
378 * Derive a pointer to the detected JobRs regs
379 * Driver has already iomapped the entire space, we just
380 * need to add in the offset to this JobR. Don't know if I
381 * like this long-term, but it'll run
382 */
383 jroffset = (u32 *)of_get_property(np, "reg", NULL);
384 jrpriv->rregs = (struct caam_job_ring __iomem *)((void *)ctrlpriv->ctrl
385 + *jroffset);
386 462
387 /* Build a local dev for each detected queue */ 463 /* save ring identity relative to detection */
388 jr_pdev = of_platform_device_create(np, NULL, ctrldev); 464 jrpriv->ridx = total_jobrs++;
389 if (jr_pdev == NULL) { 465
390 kfree(jrpriv); 466 nprop = pdev->dev.of_node;
391 return -EINVAL; 467 /* Get configuration properties from device tree */
468 /* First, get register page */
469 ctrl = of_iomap(nprop, 0);
470 if (!ctrl) {
471 dev_err(jrdev, "of_iomap() failed\n");
472 return -ENOMEM;
392 } 473 }
393 474
394 jrpriv->jr_pdev = jr_pdev; 475 jrpriv->rregs = (struct caam_job_ring __force *)ctrl;
395 jrdev = &jr_pdev->dev;
396 dev_set_drvdata(jrdev, jrpriv);
397 ctrlpriv->jrdev[ring] = jrdev;
398 476
399 if (sizeof(dma_addr_t) == sizeof(u64)) 477 if (sizeof(dma_addr_t) == sizeof(u64))
400 if (of_device_is_compatible(np, "fsl,sec-v5.0-job-ring")) 478 if (of_device_is_compatible(nprop, "fsl,sec-v5.0-job-ring"))
401 dma_set_mask(jrdev, DMA_BIT_MASK(40)); 479 dma_set_mask(jrdev, DMA_BIT_MASK(40));
402 else 480 else
403 dma_set_mask(jrdev, DMA_BIT_MASK(36)); 481 dma_set_mask(jrdev, DMA_BIT_MASK(36));
@@ -405,15 +483,61 @@ int caam_jr_probe(struct platform_device *pdev, struct device_node *np,
405 dma_set_mask(jrdev, DMA_BIT_MASK(32)); 483 dma_set_mask(jrdev, DMA_BIT_MASK(32));
406 484
407 /* Identify the interrupt */ 485 /* Identify the interrupt */
408 jrpriv->irq = irq_of_parse_and_map(np, 0); 486 jrpriv->irq = irq_of_parse_and_map(nprop, 0);
409 487
410 /* Now do the platform independent part */ 488 /* Now do the platform independent part */
411 error = caam_jr_init(jrdev); /* now turn on hardware */ 489 error = caam_jr_init(jrdev); /* now turn on hardware */
412 if (error) { 490 if (error) {
413 of_device_unregister(jr_pdev);
414 kfree(jrpriv); 491 kfree(jrpriv);
415 return error; 492 return error;
416 } 493 }
417 494
418 return error; 495 jrpriv->dev = jrdev;
496 spin_lock(&driver_data.jr_alloc_lock);
497 list_add_tail(&jrpriv->list_node, &driver_data.jr_list);
498 spin_unlock(&driver_data.jr_alloc_lock);
499
500 atomic_set(&jrpriv->tfm_count, 0);
501
502 return 0;
503}
504
505static struct of_device_id caam_jr_match[] = {
506 {
507 .compatible = "fsl,sec-v4.0-job-ring",
508 },
509 {
510 .compatible = "fsl,sec4.0-job-ring",
511 },
512 {},
513};
514MODULE_DEVICE_TABLE(of, caam_jr_match);
515
516static struct platform_driver caam_jr_driver = {
517 .driver = {
518 .name = "caam_jr",
519 .owner = THIS_MODULE,
520 .of_match_table = caam_jr_match,
521 },
522 .probe = caam_jr_probe,
523 .remove = caam_jr_remove,
524};
525
526static int __init jr_driver_init(void)
527{
528 spin_lock_init(&driver_data.jr_alloc_lock);
529 INIT_LIST_HEAD(&driver_data.jr_list);
530 return platform_driver_register(&caam_jr_driver);
531}
532
533static void __exit jr_driver_exit(void)
534{
535 platform_driver_unregister(&caam_jr_driver);
419} 536}
537
538module_init(jr_driver_init);
539module_exit(jr_driver_exit);
540
541MODULE_LICENSE("GPL");
542MODULE_DESCRIPTION("FSL CAAM JR request backend");
543MODULE_AUTHOR("Freescale Semiconductor - NMG/STC");
diff --git a/drivers/crypto/caam/jr.h b/drivers/crypto/caam/jr.h
index 9d8741a59037..97113a6d6c58 100644
--- a/drivers/crypto/caam/jr.h
+++ b/drivers/crypto/caam/jr.h
@@ -8,12 +8,11 @@
8#define JR_H 8#define JR_H
9 9
10/* Prototypes for backend-level services exposed to APIs */ 10/* Prototypes for backend-level services exposed to APIs */
11struct device *caam_jr_alloc(void);
12void caam_jr_free(struct device *rdev);
11int caam_jr_enqueue(struct device *dev, u32 *desc, 13int caam_jr_enqueue(struct device *dev, u32 *desc,
12 void (*cbk)(struct device *dev, u32 *desc, u32 status, 14 void (*cbk)(struct device *dev, u32 *desc, u32 status,
13 void *areq), 15 void *areq),
14 void *areq); 16 void *areq);
15 17
16extern int caam_jr_probe(struct platform_device *pdev, struct device_node *np,
17 int ring);
18extern int caam_jr_shutdown(struct device *dev);
19#endif /* JR_H */ 18#endif /* JR_H */
diff --git a/drivers/crypto/caam/regs.h b/drivers/crypto/caam/regs.h
index 4455396918de..d50174f45b21 100644
--- a/drivers/crypto/caam/regs.h
+++ b/drivers/crypto/caam/regs.h
@@ -245,7 +245,7 @@ struct rngtst {
245 245
246/* RNG4 TRNG test registers */ 246/* RNG4 TRNG test registers */
247struct rng4tst { 247struct rng4tst {
248#define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */ 248#define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */
249 u32 rtmctl; /* misc. control register */ 249 u32 rtmctl; /* misc. control register */
250 u32 rtscmisc; /* statistical check misc. register */ 250 u32 rtscmisc; /* statistical check misc. register */
251 u32 rtpkrrng; /* poker range register */ 251 u32 rtpkrrng; /* poker range register */
@@ -255,6 +255,8 @@ struct rng4tst {
255 }; 255 };
256#define RTSDCTL_ENT_DLY_SHIFT 16 256#define RTSDCTL_ENT_DLY_SHIFT 16
257#define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT) 257#define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT)
258#define RTSDCTL_ENT_DLY_MIN 1200
259#define RTSDCTL_ENT_DLY_MAX 12800
258 u32 rtsdctl; /* seed control register */ 260 u32 rtsdctl; /* seed control register */
259 union { 261 union {
260 u32 rtsblim; /* PRGM=1: sparse bit limit register */ 262 u32 rtsblim; /* PRGM=1: sparse bit limit register */
@@ -266,7 +268,11 @@ struct rng4tst {
266 u32 rtfrqcnt; /* PRGM=0: freq. count register */ 268 u32 rtfrqcnt; /* PRGM=0: freq. count register */
267 }; 269 };
268 u32 rsvd1[40]; 270 u32 rsvd1[40];
271#define RDSTA_SKVT 0x80000000
272#define RDSTA_SKVN 0x40000000
269#define RDSTA_IF0 0x00000001 273#define RDSTA_IF0 0x00000001
274#define RDSTA_IF1 0x00000002
275#define RDSTA_IFMASK (RDSTA_IF1 | RDSTA_IF0)
270 u32 rdsta; 276 u32 rdsta;
271 u32 rsvd2[15]; 277 u32 rsvd2[15];
272}; 278};
@@ -692,6 +698,7 @@ struct caam_deco {
692 u32 jr_ctl_hi; /* CxJRR - JobR Control Register @800 */ 698 u32 jr_ctl_hi; /* CxJRR - JobR Control Register @800 */
693 u32 jr_ctl_lo; 699 u32 jr_ctl_lo;
694 u64 jr_descaddr; /* CxDADR - JobR Descriptor Address */ 700 u64 jr_descaddr; /* CxDADR - JobR Descriptor Address */
701#define DECO_OP_STATUS_HI_ERR_MASK 0xF00000FF
695 u32 op_status_hi; /* DxOPSTA - DECO Operation Status */ 702 u32 op_status_hi; /* DxOPSTA - DECO Operation Status */
696 u32 op_status_lo; 703 u32 op_status_lo;
697 u32 rsvd24[2]; 704 u32 rsvd24[2];
@@ -706,12 +713,13 @@ struct caam_deco {
706 u32 rsvd29[48]; 713 u32 rsvd29[48];
707 u32 descbuf[64]; /* DxDESB - Descriptor buffer */ 714 u32 descbuf[64]; /* DxDESB - Descriptor buffer */
708 u32 rscvd30[193]; 715 u32 rscvd30[193];
716#define DESC_DBG_DECO_STAT_HOST_ERR 0x00D00000
717#define DESC_DBG_DECO_STAT_VALID 0x80000000
718#define DESC_DBG_DECO_STAT_MASK 0x00F00000
709 u32 desc_dbg; /* DxDDR - DECO Debug Register */ 719 u32 desc_dbg; /* DxDDR - DECO Debug Register */
710 u32 rsvd31[126]; 720 u32 rsvd31[126];
711}; 721};
712 722
713/* DECO DBG Register Valid Bit*/
714#define DECO_DBG_VALID 0x80000000
715#define DECO_JQCR_WHL 0x20000000 723#define DECO_JQCR_WHL 0x20000000
716#define DECO_JQCR_FOUR 0x10000000 724#define DECO_JQCR_FOUR 0x10000000
717 725
diff --git a/drivers/crypto/caam/sg_sw_sec4.h b/drivers/crypto/caam/sg_sw_sec4.h
index e0037c8ee243..b12ff85f4241 100644
--- a/drivers/crypto/caam/sg_sw_sec4.h
+++ b/drivers/crypto/caam/sg_sw_sec4.h
@@ -117,6 +117,21 @@ static int dma_unmap_sg_chained(struct device *dev, struct scatterlist *sg,
117 return nents; 117 return nents;
118} 118}
119 119
120/* Map SG page in kernel virtual address space and copy */
121static inline void sg_map_copy(u8 *dest, struct scatterlist *sg,
122 int len, int offset)
123{
124 u8 *mapped_addr;
125
126 /*
127 * Page here can be user-space pinned using get_user_pages
128 * Same must be kmapped before use and kunmapped subsequently
129 */
130 mapped_addr = kmap_atomic(sg_page(sg));
131 memcpy(dest, mapped_addr + offset, len);
132 kunmap_atomic(mapped_addr);
133}
134
120/* Copy from len bytes of sg to dest, starting from beginning */ 135/* Copy from len bytes of sg to dest, starting from beginning */
121static inline void sg_copy(u8 *dest, struct scatterlist *sg, unsigned int len) 136static inline void sg_copy(u8 *dest, struct scatterlist *sg, unsigned int len)
122{ 137{
@@ -124,15 +139,15 @@ static inline void sg_copy(u8 *dest, struct scatterlist *sg, unsigned int len)
124 int cpy_index = 0, next_cpy_index = current_sg->length; 139 int cpy_index = 0, next_cpy_index = current_sg->length;
125 140
126 while (next_cpy_index < len) { 141 while (next_cpy_index < len) {
127 memcpy(dest + cpy_index, (u8 *) sg_virt(current_sg), 142 sg_map_copy(dest + cpy_index, current_sg, current_sg->length,
128 current_sg->length); 143 current_sg->offset);
129 current_sg = scatterwalk_sg_next(current_sg); 144 current_sg = scatterwalk_sg_next(current_sg);
130 cpy_index = next_cpy_index; 145 cpy_index = next_cpy_index;
131 next_cpy_index += current_sg->length; 146 next_cpy_index += current_sg->length;
132 } 147 }
133 if (cpy_index < len) 148 if (cpy_index < len)
134 memcpy(dest + cpy_index, (u8 *) sg_virt(current_sg), 149 sg_map_copy(dest + cpy_index, current_sg, len-cpy_index,
135 len - cpy_index); 150 current_sg->offset);
136} 151}
137 152
138/* Copy sg data, from to_skip to end, to dest */ 153/* Copy sg data, from to_skip to end, to dest */
@@ -140,7 +155,7 @@ static inline void sg_copy_part(u8 *dest, struct scatterlist *sg,
140 int to_skip, unsigned int end) 155 int to_skip, unsigned int end)
141{ 156{
142 struct scatterlist *current_sg = sg; 157 struct scatterlist *current_sg = sg;
143 int sg_index, cpy_index; 158 int sg_index, cpy_index, offset;
144 159
145 sg_index = current_sg->length; 160 sg_index = current_sg->length;
146 while (sg_index <= to_skip) { 161 while (sg_index <= to_skip) {
@@ -148,9 +163,10 @@ static inline void sg_copy_part(u8 *dest, struct scatterlist *sg,
148 sg_index += current_sg->length; 163 sg_index += current_sg->length;
149 } 164 }
150 cpy_index = sg_index - to_skip; 165 cpy_index = sg_index - to_skip;
151 memcpy(dest, (u8 *) sg_virt(current_sg) + 166 offset = current_sg->offset + current_sg->length - cpy_index;
152 current_sg->length - cpy_index, cpy_index); 167 sg_map_copy(dest, current_sg, cpy_index, offset);
153 current_sg = scatterwalk_sg_next(current_sg); 168 if (end - sg_index) {
154 if (end - sg_index) 169 current_sg = scatterwalk_sg_next(current_sg);
155 sg_copy(dest + cpy_index, current_sg, end - sg_index); 170 sg_copy(dest + cpy_index, current_sg, end - sg_index);
171 }
156} 172}
diff --git a/drivers/crypto/dcp.c b/drivers/crypto/dcp.c
index a8a7dd4b0d25..247ab8048f5b 100644
--- a/drivers/crypto/dcp.c
+++ b/drivers/crypto/dcp.c
@@ -733,12 +733,9 @@ static int dcp_probe(struct platform_device *pdev)
733 platform_set_drvdata(pdev, dev); 733 platform_set_drvdata(pdev, dev);
734 734
735 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 735 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
736 if (!r) { 736 dev->dcp_regs_base = devm_ioremap_resource(&pdev->dev, r);
737 dev_err(&pdev->dev, "failed to get IORESOURCE_MEM\n"); 737 if (IS_ERR(dev->dcp_regs_base))
738 return -ENXIO; 738 return PTR_ERR(dev->dcp_regs_base);
739 }
740 dev->dcp_regs_base = devm_ioremap(&pdev->dev, r->start,
741 resource_size(r));
742 739
743 dcp_set(dev, DCP_CTRL_SFRST, DCP_REG_CTRL); 740 dcp_set(dev, DCP_CTRL_SFRST, DCP_REG_CTRL);
744 udelay(10); 741 udelay(10);
@@ -762,7 +759,8 @@ static int dcp_probe(struct platform_device *pdev)
762 return -EIO; 759 return -EIO;
763 } 760 }
764 dev->dcp_vmi_irq = r->start; 761 dev->dcp_vmi_irq = r->start;
765 ret = request_irq(dev->dcp_vmi_irq, dcp_vmi_irq, 0, "dcp", dev); 762 ret = devm_request_irq(&pdev->dev, dev->dcp_vmi_irq, dcp_vmi_irq, 0,
763 "dcp", dev);
766 if (ret != 0) { 764 if (ret != 0) {
767 dev_err(&pdev->dev, "can't request_irq (0)\n"); 765 dev_err(&pdev->dev, "can't request_irq (0)\n");
768 return -EIO; 766 return -EIO;
@@ -771,15 +769,14 @@ static int dcp_probe(struct platform_device *pdev)
771 r = platform_get_resource(pdev, IORESOURCE_IRQ, 1); 769 r = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
772 if (!r) { 770 if (!r) {
773 dev_err(&pdev->dev, "can't get IRQ resource (1)\n"); 771 dev_err(&pdev->dev, "can't get IRQ resource (1)\n");
774 ret = -EIO; 772 return -EIO;
775 goto err_free_irq0;
776 } 773 }
777 dev->dcp_irq = r->start; 774 dev->dcp_irq = r->start;
778 ret = request_irq(dev->dcp_irq, dcp_irq, 0, "dcp", dev); 775 ret = devm_request_irq(&pdev->dev, dev->dcp_irq, dcp_irq, 0, "dcp",
776 dev);
779 if (ret != 0) { 777 if (ret != 0) {
780 dev_err(&pdev->dev, "can't request_irq (1)\n"); 778 dev_err(&pdev->dev, "can't request_irq (1)\n");
781 ret = -EIO; 779 return -EIO;
782 goto err_free_irq0;
783 } 780 }
784 781
785 dev->hw_pkg[0] = dma_alloc_coherent(&pdev->dev, 782 dev->hw_pkg[0] = dma_alloc_coherent(&pdev->dev,
@@ -788,8 +785,7 @@ static int dcp_probe(struct platform_device *pdev)
788 GFP_KERNEL); 785 GFP_KERNEL);
789 if (!dev->hw_pkg[0]) { 786 if (!dev->hw_pkg[0]) {
790 dev_err(&pdev->dev, "Could not allocate hw descriptors\n"); 787 dev_err(&pdev->dev, "Could not allocate hw descriptors\n");
791 ret = -ENOMEM; 788 return -ENOMEM;
792 goto err_free_irq1;
793 } 789 }
794 790
795 for (i = 1; i < DCP_MAX_PKG; i++) { 791 for (i = 1; i < DCP_MAX_PKG; i++) {
@@ -848,16 +844,14 @@ err_unregister:
848 for (j = 0; j < i; j++) 844 for (j = 0; j < i; j++)
849 crypto_unregister_alg(&algs[j]); 845 crypto_unregister_alg(&algs[j]);
850err_free_key_iv: 846err_free_key_iv:
847 tasklet_kill(&dev->done_task);
848 tasklet_kill(&dev->queue_task);
851 dma_free_coherent(&pdev->dev, 2 * AES_KEYSIZE_128, dev->payload_base, 849 dma_free_coherent(&pdev->dev, 2 * AES_KEYSIZE_128, dev->payload_base,
852 dev->payload_base_dma); 850 dev->payload_base_dma);
853err_free_hw_packet: 851err_free_hw_packet:
854 dma_free_coherent(&pdev->dev, DCP_MAX_PKG * 852 dma_free_coherent(&pdev->dev, DCP_MAX_PKG *
855 sizeof(struct dcp_hw_packet), dev->hw_pkg[0], 853 sizeof(struct dcp_hw_packet), dev->hw_pkg[0],
856 dev->hw_phys_pkg); 854 dev->hw_phys_pkg);
857err_free_irq1:
858 free_irq(dev->dcp_irq, dev);
859err_free_irq0:
860 free_irq(dev->dcp_vmi_irq, dev);
861 855
862 return ret; 856 return ret;
863} 857}
@@ -868,23 +862,20 @@ static int dcp_remove(struct platform_device *pdev)
868 int j; 862 int j;
869 dev = platform_get_drvdata(pdev); 863 dev = platform_get_drvdata(pdev);
870 864
871 dma_free_coherent(&pdev->dev, 865 misc_deregister(&dev->dcp_bootstream_misc);
872 DCP_MAX_PKG * sizeof(struct dcp_hw_packet),
873 dev->hw_pkg[0], dev->hw_phys_pkg);
874
875 dma_free_coherent(&pdev->dev, 2 * AES_KEYSIZE_128, dev->payload_base,
876 dev->payload_base_dma);
877 866
878 free_irq(dev->dcp_irq, dev); 867 for (j = 0; j < ARRAY_SIZE(algs); j++)
879 free_irq(dev->dcp_vmi_irq, dev); 868 crypto_unregister_alg(&algs[j]);
880 869
881 tasklet_kill(&dev->done_task); 870 tasklet_kill(&dev->done_task);
882 tasklet_kill(&dev->queue_task); 871 tasklet_kill(&dev->queue_task);
883 872
884 for (j = 0; j < ARRAY_SIZE(algs); j++) 873 dma_free_coherent(&pdev->dev, 2 * AES_KEYSIZE_128, dev->payload_base,
885 crypto_unregister_alg(&algs[j]); 874 dev->payload_base_dma);
886 875
887 misc_deregister(&dev->dcp_bootstream_misc); 876 dma_free_coherent(&pdev->dev,
877 DCP_MAX_PKG * sizeof(struct dcp_hw_packet),
878 dev->hw_pkg[0], dev->hw_phys_pkg);
888 879
889 return 0; 880 return 0;
890} 881}
diff --git a/drivers/crypto/ixp4xx_crypto.c b/drivers/crypto/ixp4xx_crypto.c
index 214357e12dc0..9dd6e01eac33 100644
--- a/drivers/crypto/ixp4xx_crypto.c
+++ b/drivers/crypto/ixp4xx_crypto.c
@@ -1149,32 +1149,24 @@ static int aead_setkey(struct crypto_aead *tfm, const u8 *key,
1149 unsigned int keylen) 1149 unsigned int keylen)
1150{ 1150{
1151 struct ixp_ctx *ctx = crypto_aead_ctx(tfm); 1151 struct ixp_ctx *ctx = crypto_aead_ctx(tfm);
1152 struct rtattr *rta = (struct rtattr *)key; 1152 struct crypto_authenc_keys keys;
1153 struct crypto_authenc_key_param *param;
1154 1153
1155 if (!RTA_OK(rta, keylen)) 1154 if (crypto_authenc_extractkeys(&keys, key, keylen) != 0)
1156 goto badkey;
1157 if (rta->rta_type != CRYPTO_AUTHENC_KEYA_PARAM)
1158 goto badkey;
1159 if (RTA_PAYLOAD(rta) < sizeof(*param))
1160 goto badkey; 1155 goto badkey;
1161 1156
1162 param = RTA_DATA(rta); 1157 if (keys.authkeylen > sizeof(ctx->authkey))
1163 ctx->enckey_len = be32_to_cpu(param->enckeylen); 1158 goto badkey;
1164
1165 key += RTA_ALIGN(rta->rta_len);
1166 keylen -= RTA_ALIGN(rta->rta_len);
1167 1159
1168 if (keylen < ctx->enckey_len) 1160 if (keys.enckeylen > sizeof(ctx->enckey))
1169 goto badkey; 1161 goto badkey;
1170 1162
1171 ctx->authkey_len = keylen - ctx->enckey_len; 1163 memcpy(ctx->authkey, keys.authkey, keys.authkeylen);
1172 memcpy(ctx->enckey, key + ctx->authkey_len, ctx->enckey_len); 1164 memcpy(ctx->enckey, keys.enckey, keys.enckeylen);
1173 memcpy(ctx->authkey, key, ctx->authkey_len); 1165 ctx->authkey_len = keys.authkeylen;
1166 ctx->enckey_len = keys.enckeylen;
1174 1167
1175 return aead_setup(tfm, crypto_aead_authsize(tfm)); 1168 return aead_setup(tfm, crypto_aead_authsize(tfm));
1176badkey: 1169badkey:
1177 ctx->enckey_len = 0;
1178 crypto_aead_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN); 1170 crypto_aead_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
1179 return -EINVAL; 1171 return -EINVAL;
1180} 1172}
diff --git a/drivers/crypto/mv_cesa.c b/drivers/crypto/mv_cesa.c
index 3374a3ebe4c7..8d1e6f8e9e9c 100644
--- a/drivers/crypto/mv_cesa.c
+++ b/drivers/crypto/mv_cesa.c
@@ -907,7 +907,7 @@ static int mv_cra_hash_hmac_sha1_init(struct crypto_tfm *tfm)
907 return mv_cra_hash_init(tfm, "sha1", COP_HMAC_SHA1, SHA1_BLOCK_SIZE); 907 return mv_cra_hash_init(tfm, "sha1", COP_HMAC_SHA1, SHA1_BLOCK_SIZE);
908} 908}
909 909
910irqreturn_t crypto_int(int irq, void *priv) 910static irqreturn_t crypto_int(int irq, void *priv)
911{ 911{
912 u32 val; 912 u32 val;
913 913
@@ -928,7 +928,7 @@ irqreturn_t crypto_int(int irq, void *priv)
928 return IRQ_HANDLED; 928 return IRQ_HANDLED;
929} 929}
930 930
931struct crypto_alg mv_aes_alg_ecb = { 931static struct crypto_alg mv_aes_alg_ecb = {
932 .cra_name = "ecb(aes)", 932 .cra_name = "ecb(aes)",
933 .cra_driver_name = "mv-ecb-aes", 933 .cra_driver_name = "mv-ecb-aes",
934 .cra_priority = 300, 934 .cra_priority = 300,
@@ -951,7 +951,7 @@ struct crypto_alg mv_aes_alg_ecb = {
951 }, 951 },
952}; 952};
953 953
954struct crypto_alg mv_aes_alg_cbc = { 954static struct crypto_alg mv_aes_alg_cbc = {
955 .cra_name = "cbc(aes)", 955 .cra_name = "cbc(aes)",
956 .cra_driver_name = "mv-cbc-aes", 956 .cra_driver_name = "mv-cbc-aes",
957 .cra_priority = 300, 957 .cra_priority = 300,
@@ -975,7 +975,7 @@ struct crypto_alg mv_aes_alg_cbc = {
975 }, 975 },
976}; 976};
977 977
978struct ahash_alg mv_sha1_alg = { 978static struct ahash_alg mv_sha1_alg = {
979 .init = mv_hash_init, 979 .init = mv_hash_init,
980 .update = mv_hash_update, 980 .update = mv_hash_update,
981 .final = mv_hash_final, 981 .final = mv_hash_final,
@@ -999,7 +999,7 @@ struct ahash_alg mv_sha1_alg = {
999 } 999 }
1000}; 1000};
1001 1001
1002struct ahash_alg mv_hmac_sha1_alg = { 1002static struct ahash_alg mv_hmac_sha1_alg = {
1003 .init = mv_hash_init, 1003 .init = mv_hash_init,
1004 .update = mv_hash_update, 1004 .update = mv_hash_update,
1005 .final = mv_hash_final, 1005 .final = mv_hash_final,
@@ -1084,7 +1084,7 @@ static int mv_probe(struct platform_device *pdev)
1084 goto err_unmap_sram; 1084 goto err_unmap_sram;
1085 } 1085 }
1086 1086
1087 ret = request_irq(irq, crypto_int, IRQF_DISABLED, dev_name(&pdev->dev), 1087 ret = request_irq(irq, crypto_int, 0, dev_name(&pdev->dev),
1088 cp); 1088 cp);
1089 if (ret) 1089 if (ret)
1090 goto err_thread; 1090 goto err_thread;
@@ -1187,7 +1187,7 @@ static struct platform_driver marvell_crypto = {
1187 .driver = { 1187 .driver = {
1188 .owner = THIS_MODULE, 1188 .owner = THIS_MODULE,
1189 .name = "mv_crypto", 1189 .name = "mv_crypto",
1190 .of_match_table = of_match_ptr(mv_cesa_of_match_table), 1190 .of_match_table = mv_cesa_of_match_table,
1191 }, 1191 },
1192}; 1192};
1193MODULE_ALIAS("platform:mv_crypto"); 1193MODULE_ALIAS("platform:mv_crypto");
diff --git a/drivers/crypto/omap-aes.c b/drivers/crypto/omap-aes.c
index ce791c2f81f7..a9ccbf14096e 100644
--- a/drivers/crypto/omap-aes.c
+++ b/drivers/crypto/omap-aes.c
@@ -275,7 +275,7 @@ static int omap_aes_write_ctrl(struct omap_aes_dev *dd)
275 if (dd->flags & FLAGS_CBC) 275 if (dd->flags & FLAGS_CBC)
276 val |= AES_REG_CTRL_CBC; 276 val |= AES_REG_CTRL_CBC;
277 if (dd->flags & FLAGS_CTR) { 277 if (dd->flags & FLAGS_CTR) {
278 val |= AES_REG_CTRL_CTR | AES_REG_CTRL_CTR_WIDTH_32; 278 val |= AES_REG_CTRL_CTR | AES_REG_CTRL_CTR_WIDTH_128;
279 mask = AES_REG_CTRL_CTR | AES_REG_CTRL_CTR_WIDTH_MASK; 279 mask = AES_REG_CTRL_CTR | AES_REG_CTRL_CTR_WIDTH_MASK;
280 } 280 }
281 if (dd->flags & FLAGS_ENCRYPT) 281 if (dd->flags & FLAGS_ENCRYPT)
@@ -554,7 +554,7 @@ static int omap_aes_crypt_dma_stop(struct omap_aes_dev *dd)
554 return err; 554 return err;
555} 555}
556 556
557int omap_aes_check_aligned(struct scatterlist *sg) 557static int omap_aes_check_aligned(struct scatterlist *sg)
558{ 558{
559 while (sg) { 559 while (sg) {
560 if (!IS_ALIGNED(sg->offset, 4)) 560 if (!IS_ALIGNED(sg->offset, 4))
@@ -566,7 +566,7 @@ int omap_aes_check_aligned(struct scatterlist *sg)
566 return 0; 566 return 0;
567} 567}
568 568
569int omap_aes_copy_sgs(struct omap_aes_dev *dd) 569static int omap_aes_copy_sgs(struct omap_aes_dev *dd)
570{ 570{
571 void *buf_in, *buf_out; 571 void *buf_in, *buf_out;
572 int pages; 572 int pages;
diff --git a/drivers/crypto/omap-sham.c b/drivers/crypto/omap-sham.c
index e28104b4aab0..e45aaaf0db30 100644
--- a/drivers/crypto/omap-sham.c
+++ b/drivers/crypto/omap-sham.c
@@ -2033,3 +2033,4 @@ module_platform_driver(omap_sham_driver);
2033MODULE_DESCRIPTION("OMAP SHA1/MD5 hw acceleration support."); 2033MODULE_DESCRIPTION("OMAP SHA1/MD5 hw acceleration support.");
2034MODULE_LICENSE("GPL v2"); 2034MODULE_LICENSE("GPL v2");
2035MODULE_AUTHOR("Dmitry Kasatkin"); 2035MODULE_AUTHOR("Dmitry Kasatkin");
2036MODULE_ALIAS("platform:omap-sham");
diff --git a/drivers/crypto/picoxcell_crypto.c b/drivers/crypto/picoxcell_crypto.c
index 888f7f4a6d3f..a6175ba6d238 100644
--- a/drivers/crypto/picoxcell_crypto.c
+++ b/drivers/crypto/picoxcell_crypto.c
@@ -495,45 +495,29 @@ static int spacc_aead_setkey(struct crypto_aead *tfm, const u8 *key,
495{ 495{
496 struct spacc_aead_ctx *ctx = crypto_aead_ctx(tfm); 496 struct spacc_aead_ctx *ctx = crypto_aead_ctx(tfm);
497 struct spacc_alg *alg = to_spacc_alg(tfm->base.__crt_alg); 497 struct spacc_alg *alg = to_spacc_alg(tfm->base.__crt_alg);
498 struct rtattr *rta = (void *)key; 498 struct crypto_authenc_keys keys;
499 struct crypto_authenc_key_param *param;
500 unsigned int authkeylen, enckeylen;
501 int err = -EINVAL; 499 int err = -EINVAL;
502 500
503 if (!RTA_OK(rta, keylen)) 501 if (crypto_authenc_extractkeys(&keys, key, keylen) != 0)
504 goto badkey; 502 goto badkey;
505 503
506 if (rta->rta_type != CRYPTO_AUTHENC_KEYA_PARAM) 504 if (keys.enckeylen > AES_MAX_KEY_SIZE)
507 goto badkey; 505 goto badkey;
508 506
509 if (RTA_PAYLOAD(rta) < sizeof(*param)) 507 if (keys.authkeylen > sizeof(ctx->hash_ctx))
510 goto badkey;
511
512 param = RTA_DATA(rta);
513 enckeylen = be32_to_cpu(param->enckeylen);
514
515 key += RTA_ALIGN(rta->rta_len);
516 keylen -= RTA_ALIGN(rta->rta_len);
517
518 if (keylen < enckeylen)
519 goto badkey;
520
521 authkeylen = keylen - enckeylen;
522
523 if (enckeylen > AES_MAX_KEY_SIZE)
524 goto badkey; 508 goto badkey;
525 509
526 if ((alg->ctrl_default & SPACC_CRYPTO_ALG_MASK) == 510 if ((alg->ctrl_default & SPACC_CRYPTO_ALG_MASK) ==
527 SPA_CTRL_CIPH_ALG_AES) 511 SPA_CTRL_CIPH_ALG_AES)
528 err = spacc_aead_aes_setkey(tfm, key + authkeylen, enckeylen); 512 err = spacc_aead_aes_setkey(tfm, keys.enckey, keys.enckeylen);
529 else 513 else
530 err = spacc_aead_des_setkey(tfm, key + authkeylen, enckeylen); 514 err = spacc_aead_des_setkey(tfm, keys.enckey, keys.enckeylen);
531 515
532 if (err) 516 if (err)
533 goto badkey; 517 goto badkey;
534 518
535 memcpy(ctx->hash_ctx, key, authkeylen); 519 memcpy(ctx->hash_ctx, keys.authkey, keys.authkeylen);
536 ctx->hash_key_len = authkeylen; 520 ctx->hash_key_len = keys.authkeylen;
537 521
538 return 0; 522 return 0;
539 523
diff --git a/drivers/crypto/sahara.c b/drivers/crypto/sahara.c
index d7bb8bac36e9..785a9ded7bdf 100644
--- a/drivers/crypto/sahara.c
+++ b/drivers/crypto/sahara.c
@@ -1058,7 +1058,7 @@ static struct platform_driver sahara_driver = {
1058 .driver = { 1058 .driver = {
1059 .name = SAHARA_NAME, 1059 .name = SAHARA_NAME,
1060 .owner = THIS_MODULE, 1060 .owner = THIS_MODULE,
1061 .of_match_table = of_match_ptr(sahara_dt_ids), 1061 .of_match_table = sahara_dt_ids,
1062 }, 1062 },
1063 .id_table = sahara_platform_ids, 1063 .id_table = sahara_platform_ids,
1064}; 1064};
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index 6cd0e6038583..b44f4ddc565c 100644
--- a/drivers/crypto/talitos.c
+++ b/drivers/crypto/talitos.c
@@ -673,39 +673,20 @@ static int aead_setkey(struct crypto_aead *authenc,
673 const u8 *key, unsigned int keylen) 673 const u8 *key, unsigned int keylen)
674{ 674{
675 struct talitos_ctx *ctx = crypto_aead_ctx(authenc); 675 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
676 struct rtattr *rta = (void *)key; 676 struct crypto_authenc_keys keys;
677 struct crypto_authenc_key_param *param;
678 unsigned int authkeylen;
679 unsigned int enckeylen;
680
681 if (!RTA_OK(rta, keylen))
682 goto badkey;
683 677
684 if (rta->rta_type != CRYPTO_AUTHENC_KEYA_PARAM) 678 if (crypto_authenc_extractkeys(&keys, key, keylen) != 0)
685 goto badkey; 679 goto badkey;
686 680
687 if (RTA_PAYLOAD(rta) < sizeof(*param)) 681 if (keys.authkeylen + keys.enckeylen > TALITOS_MAX_KEY_SIZE)
688 goto badkey; 682 goto badkey;
689 683
690 param = RTA_DATA(rta); 684 memcpy(ctx->key, keys.authkey, keys.authkeylen);
691 enckeylen = be32_to_cpu(param->enckeylen); 685 memcpy(&ctx->key[keys.authkeylen], keys.enckey, keys.enckeylen);
692
693 key += RTA_ALIGN(rta->rta_len);
694 keylen -= RTA_ALIGN(rta->rta_len);
695 686
696 if (keylen < enckeylen) 687 ctx->keylen = keys.authkeylen + keys.enckeylen;
697 goto badkey; 688 ctx->enckeylen = keys.enckeylen;
698 689 ctx->authkeylen = keys.authkeylen;
699 authkeylen = keylen - enckeylen;
700
701 if (keylen > TALITOS_MAX_KEY_SIZE)
702 goto badkey;
703
704 memcpy(&ctx->key, key, keylen);
705
706 ctx->keylen = keylen;
707 ctx->enckeylen = enckeylen;
708 ctx->authkeylen = authkeylen;
709 690
710 return 0; 691 return 0;
711 692
@@ -809,7 +790,7 @@ static void ipsec_esp_unmap(struct device *dev,
809 790
810 if (edesc->assoc_chained) 791 if (edesc->assoc_chained)
811 talitos_unmap_sg_chain(dev, areq->assoc, DMA_TO_DEVICE); 792 talitos_unmap_sg_chain(dev, areq->assoc, DMA_TO_DEVICE);
812 else 793 else if (areq->assoclen)
813 /* assoc_nents counts also for IV in non-contiguous cases */ 794 /* assoc_nents counts also for IV in non-contiguous cases */
814 dma_unmap_sg(dev, areq->assoc, 795 dma_unmap_sg(dev, areq->assoc,
815 edesc->assoc_nents ? edesc->assoc_nents - 1 : 1, 796 edesc->assoc_nents ? edesc->assoc_nents - 1 : 1,
@@ -992,7 +973,11 @@ static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
992 dma_sync_single_for_device(dev, edesc->dma_link_tbl, 973 dma_sync_single_for_device(dev, edesc->dma_link_tbl,
993 edesc->dma_len, DMA_BIDIRECTIONAL); 974 edesc->dma_len, DMA_BIDIRECTIONAL);
994 } else { 975 } else {
995 to_talitos_ptr(&desc->ptr[1], sg_dma_address(areq->assoc)); 976 if (areq->assoclen)
977 to_talitos_ptr(&desc->ptr[1],
978 sg_dma_address(areq->assoc));
979 else
980 to_talitos_ptr(&desc->ptr[1], edesc->iv_dma);
996 desc->ptr[1].j_extent = 0; 981 desc->ptr[1].j_extent = 0;
997 } 982 }
998 983
@@ -1127,7 +1112,8 @@ static struct talitos_edesc *talitos_edesc_alloc(struct device *dev,
1127 unsigned int authsize, 1112 unsigned int authsize,
1128 unsigned int ivsize, 1113 unsigned int ivsize,
1129 int icv_stashing, 1114 int icv_stashing,
1130 u32 cryptoflags) 1115 u32 cryptoflags,
1116 bool encrypt)
1131{ 1117{
1132 struct talitos_edesc *edesc; 1118 struct talitos_edesc *edesc;
1133 int assoc_nents = 0, src_nents, dst_nents, alloc_len, dma_len; 1119 int assoc_nents = 0, src_nents, dst_nents, alloc_len, dma_len;
@@ -1141,10 +1127,10 @@ static struct talitos_edesc *talitos_edesc_alloc(struct device *dev,
1141 return ERR_PTR(-EINVAL); 1127 return ERR_PTR(-EINVAL);
1142 } 1128 }
1143 1129
1144 if (iv) 1130 if (ivsize)
1145 iv_dma = dma_map_single(dev, iv, ivsize, DMA_TO_DEVICE); 1131 iv_dma = dma_map_single(dev, iv, ivsize, DMA_TO_DEVICE);
1146 1132
1147 if (assoc) { 1133 if (assoclen) {
1148 /* 1134 /*
1149 * Currently it is assumed that iv is provided whenever assoc 1135 * Currently it is assumed that iv is provided whenever assoc
1150 * is. 1136 * is.
@@ -1160,19 +1146,17 @@ static struct talitos_edesc *talitos_edesc_alloc(struct device *dev,
1160 assoc_nents = assoc_nents ? assoc_nents + 1 : 2; 1146 assoc_nents = assoc_nents ? assoc_nents + 1 : 2;
1161 } 1147 }
1162 1148
1163 src_nents = sg_count(src, cryptlen + authsize, &src_chained); 1149 if (!dst || dst == src) {
1164 src_nents = (src_nents == 1) ? 0 : src_nents; 1150 src_nents = sg_count(src, cryptlen + authsize, &src_chained);
1165 1151 src_nents = (src_nents == 1) ? 0 : src_nents;
1166 if (!dst) { 1152 dst_nents = dst ? src_nents : 0;
1167 dst_nents = 0; 1153 } else { /* dst && dst != src*/
1168 } else { 1154 src_nents = sg_count(src, cryptlen + (encrypt ? 0 : authsize),
1169 if (dst == src) { 1155 &src_chained);
1170 dst_nents = src_nents; 1156 src_nents = (src_nents == 1) ? 0 : src_nents;
1171 } else { 1157 dst_nents = sg_count(dst, cryptlen + (encrypt ? authsize : 0),
1172 dst_nents = sg_count(dst, cryptlen + authsize, 1158 &dst_chained);
1173 &dst_chained); 1159 dst_nents = (dst_nents == 1) ? 0 : dst_nents;
1174 dst_nents = (dst_nents == 1) ? 0 : dst_nents;
1175 }
1176 } 1160 }
1177 1161
1178 /* 1162 /*
@@ -1192,9 +1176,16 @@ static struct talitos_edesc *talitos_edesc_alloc(struct device *dev,
1192 1176
1193 edesc = kmalloc(alloc_len, GFP_DMA | flags); 1177 edesc = kmalloc(alloc_len, GFP_DMA | flags);
1194 if (!edesc) { 1178 if (!edesc) {
1195 talitos_unmap_sg_chain(dev, assoc, DMA_TO_DEVICE); 1179 if (assoc_chained)
1180 talitos_unmap_sg_chain(dev, assoc, DMA_TO_DEVICE);
1181 else if (assoclen)
1182 dma_unmap_sg(dev, assoc,
1183 assoc_nents ? assoc_nents - 1 : 1,
1184 DMA_TO_DEVICE);
1185
1196 if (iv_dma) 1186 if (iv_dma)
1197 dma_unmap_single(dev, iv_dma, ivsize, DMA_TO_DEVICE); 1187 dma_unmap_single(dev, iv_dma, ivsize, DMA_TO_DEVICE);
1188
1198 dev_err(dev, "could not allocate edescriptor\n"); 1189 dev_err(dev, "could not allocate edescriptor\n");
1199 return ERR_PTR(-ENOMEM); 1190 return ERR_PTR(-ENOMEM);
1200 } 1191 }
@@ -1216,7 +1207,7 @@ static struct talitos_edesc *talitos_edesc_alloc(struct device *dev,
1216} 1207}
1217 1208
1218static struct talitos_edesc *aead_edesc_alloc(struct aead_request *areq, u8 *iv, 1209static struct talitos_edesc *aead_edesc_alloc(struct aead_request *areq, u8 *iv,
1219 int icv_stashing) 1210 int icv_stashing, bool encrypt)
1220{ 1211{
1221 struct crypto_aead *authenc = crypto_aead_reqtfm(areq); 1212 struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
1222 struct talitos_ctx *ctx = crypto_aead_ctx(authenc); 1213 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
@@ -1225,7 +1216,7 @@ static struct talitos_edesc *aead_edesc_alloc(struct aead_request *areq, u8 *iv,
1225 return talitos_edesc_alloc(ctx->dev, areq->assoc, areq->src, areq->dst, 1216 return talitos_edesc_alloc(ctx->dev, areq->assoc, areq->src, areq->dst,
1226 iv, areq->assoclen, areq->cryptlen, 1217 iv, areq->assoclen, areq->cryptlen,
1227 ctx->authsize, ivsize, icv_stashing, 1218 ctx->authsize, ivsize, icv_stashing,
1228 areq->base.flags); 1219 areq->base.flags, encrypt);
1229} 1220}
1230 1221
1231static int aead_encrypt(struct aead_request *req) 1222static int aead_encrypt(struct aead_request *req)
@@ -1235,7 +1226,7 @@ static int aead_encrypt(struct aead_request *req)
1235 struct talitos_edesc *edesc; 1226 struct talitos_edesc *edesc;
1236 1227
1237 /* allocate extended descriptor */ 1228 /* allocate extended descriptor */
1238 edesc = aead_edesc_alloc(req, req->iv, 0); 1229 edesc = aead_edesc_alloc(req, req->iv, 0, true);
1239 if (IS_ERR(edesc)) 1230 if (IS_ERR(edesc))
1240 return PTR_ERR(edesc); 1231 return PTR_ERR(edesc);
1241 1232
@@ -1258,7 +1249,7 @@ static int aead_decrypt(struct aead_request *req)
1258 req->cryptlen -= authsize; 1249 req->cryptlen -= authsize;
1259 1250
1260 /* allocate extended descriptor */ 1251 /* allocate extended descriptor */
1261 edesc = aead_edesc_alloc(req, req->iv, 1); 1252 edesc = aead_edesc_alloc(req, req->iv, 1, false);
1262 if (IS_ERR(edesc)) 1253 if (IS_ERR(edesc))
1263 return PTR_ERR(edesc); 1254 return PTR_ERR(edesc);
1264 1255
@@ -1304,7 +1295,7 @@ static int aead_givencrypt(struct aead_givcrypt_request *req)
1304 struct talitos_edesc *edesc; 1295 struct talitos_edesc *edesc;
1305 1296
1306 /* allocate extended descriptor */ 1297 /* allocate extended descriptor */
1307 edesc = aead_edesc_alloc(areq, req->giv, 0); 1298 edesc = aead_edesc_alloc(areq, req->giv, 0, true);
1308 if (IS_ERR(edesc)) 1299 if (IS_ERR(edesc))
1309 return PTR_ERR(edesc); 1300 return PTR_ERR(edesc);
1310 1301
@@ -1460,7 +1451,7 @@ static int common_nonsnoop(struct talitos_edesc *edesc,
1460} 1451}
1461 1452
1462static struct talitos_edesc *ablkcipher_edesc_alloc(struct ablkcipher_request * 1453static struct talitos_edesc *ablkcipher_edesc_alloc(struct ablkcipher_request *
1463 areq) 1454 areq, bool encrypt)
1464{ 1455{
1465 struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq); 1456 struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1466 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher); 1457 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
@@ -1468,7 +1459,7 @@ static struct talitos_edesc *ablkcipher_edesc_alloc(struct ablkcipher_request *
1468 1459
1469 return talitos_edesc_alloc(ctx->dev, NULL, areq->src, areq->dst, 1460 return talitos_edesc_alloc(ctx->dev, NULL, areq->src, areq->dst,
1470 areq->info, 0, areq->nbytes, 0, ivsize, 0, 1461 areq->info, 0, areq->nbytes, 0, ivsize, 0,
1471 areq->base.flags); 1462 areq->base.flags, encrypt);
1472} 1463}
1473 1464
1474static int ablkcipher_encrypt(struct ablkcipher_request *areq) 1465static int ablkcipher_encrypt(struct ablkcipher_request *areq)
@@ -1478,7 +1469,7 @@ static int ablkcipher_encrypt(struct ablkcipher_request *areq)
1478 struct talitos_edesc *edesc; 1469 struct talitos_edesc *edesc;
1479 1470
1480 /* allocate extended descriptor */ 1471 /* allocate extended descriptor */
1481 edesc = ablkcipher_edesc_alloc(areq); 1472 edesc = ablkcipher_edesc_alloc(areq, true);
1482 if (IS_ERR(edesc)) 1473 if (IS_ERR(edesc))
1483 return PTR_ERR(edesc); 1474 return PTR_ERR(edesc);
1484 1475
@@ -1495,7 +1486,7 @@ static int ablkcipher_decrypt(struct ablkcipher_request *areq)
1495 struct talitos_edesc *edesc; 1486 struct talitos_edesc *edesc;
1496 1487
1497 /* allocate extended descriptor */ 1488 /* allocate extended descriptor */
1498 edesc = ablkcipher_edesc_alloc(areq); 1489 edesc = ablkcipher_edesc_alloc(areq, false);
1499 if (IS_ERR(edesc)) 1490 if (IS_ERR(edesc))
1500 return PTR_ERR(edesc); 1491 return PTR_ERR(edesc);
1501 1492
@@ -1647,7 +1638,7 @@ static struct talitos_edesc *ahash_edesc_alloc(struct ahash_request *areq,
1647 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq); 1638 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1648 1639
1649 return talitos_edesc_alloc(ctx->dev, NULL, req_ctx->psrc, NULL, NULL, 0, 1640 return talitos_edesc_alloc(ctx->dev, NULL, req_ctx->psrc, NULL, NULL, 0,
1650 nbytes, 0, 0, 0, areq->base.flags); 1641 nbytes, 0, 0, 0, areq->base.flags, false);
1651} 1642}
1652 1643
1653static int ahash_init(struct ahash_request *areq) 1644static int ahash_init(struct ahash_request *areq)
diff --git a/drivers/crypto/tegra-aes.c b/drivers/crypto/tegra-aes.c
index fa05e3c329bd..060eecc5dbc3 100644
--- a/drivers/crypto/tegra-aes.c
+++ b/drivers/crypto/tegra-aes.c
@@ -27,6 +27,8 @@
27 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 27 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
28 */ 28 */
29 29
30#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
30#include <linux/module.h> 32#include <linux/module.h>
31#include <linux/init.h> 33#include <linux/init.h>
32#include <linux/errno.h> 34#include <linux/errno.h>
@@ -199,8 +201,6 @@ static void aes_workqueue_handler(struct work_struct *work);
199static DECLARE_WORK(aes_work, aes_workqueue_handler); 201static DECLARE_WORK(aes_work, aes_workqueue_handler);
200static struct workqueue_struct *aes_wq; 202static struct workqueue_struct *aes_wq;
201 203
202extern unsigned long long tegra_chip_uid(void);
203
204static inline u32 aes_readl(struct tegra_aes_dev *dd, u32 offset) 204static inline u32 aes_readl(struct tegra_aes_dev *dd, u32 offset)
205{ 205{
206 return readl(dd->io_base + offset); 206 return readl(dd->io_base + offset);
@@ -713,13 +713,12 @@ static int tegra_aes_rng_reset(struct crypto_rng *tfm, u8 *seed,
713 struct tegra_aes_dev *dd = aes_dev; 713 struct tegra_aes_dev *dd = aes_dev;
714 struct tegra_aes_ctx *ctx = &rng_ctx; 714 struct tegra_aes_ctx *ctx = &rng_ctx;
715 struct tegra_aes_slot *key_slot; 715 struct tegra_aes_slot *key_slot;
716 struct timespec ts;
717 int ret = 0; 716 int ret = 0;
718 u64 nsec, tmp[2]; 717 u8 tmp[16]; /* 16 bytes = 128 bits of entropy */
719 u8 *dt; 718 u8 *dt;
720 719
721 if (!ctx || !dd) { 720 if (!ctx || !dd) {
722 dev_err(dd->dev, "ctx=0x%x, dd=0x%x\n", 721 pr_err("ctx=0x%x, dd=0x%x\n",
723 (unsigned int)ctx, (unsigned int)dd); 722 (unsigned int)ctx, (unsigned int)dd);
724 return -EINVAL; 723 return -EINVAL;
725 } 724 }
@@ -778,14 +777,8 @@ static int tegra_aes_rng_reset(struct crypto_rng *tfm, u8 *seed,
778 if (dd->ivlen >= (2 * DEFAULT_RNG_BLK_SZ + AES_KEYSIZE_128)) { 777 if (dd->ivlen >= (2 * DEFAULT_RNG_BLK_SZ + AES_KEYSIZE_128)) {
779 dt = dd->iv + DEFAULT_RNG_BLK_SZ + AES_KEYSIZE_128; 778 dt = dd->iv + DEFAULT_RNG_BLK_SZ + AES_KEYSIZE_128;
780 } else { 779 } else {
781 getnstimeofday(&ts); 780 get_random_bytes(tmp, sizeof(tmp));
782 nsec = timespec_to_ns(&ts); 781 dt = tmp;
783 do_div(nsec, 1000);
784 nsec ^= dd->ctr << 56;
785 dd->ctr++;
786 tmp[0] = nsec;
787 tmp[1] = tegra_chip_uid();
788 dt = (u8 *)tmp;
789 } 782 }
790 memcpy(dd->dt, dt, DEFAULT_RNG_BLK_SZ); 783 memcpy(dd->dt, dt, DEFAULT_RNG_BLK_SZ);
791 784
@@ -804,7 +797,7 @@ static int tegra_aes_cra_init(struct crypto_tfm *tfm)
804 return 0; 797 return 0;
805} 798}
806 799
807void tegra_aes_cra_exit(struct crypto_tfm *tfm) 800static void tegra_aes_cra_exit(struct crypto_tfm *tfm)
808{ 801{
809 struct tegra_aes_ctx *ctx = 802 struct tegra_aes_ctx *ctx =
810 crypto_ablkcipher_ctx((struct crypto_ablkcipher *)tfm); 803 crypto_ablkcipher_ctx((struct crypto_ablkcipher *)tfm);
@@ -924,7 +917,7 @@ static int tegra_aes_probe(struct platform_device *pdev)
924 } 917 }
925 918
926 /* Initialize the vde clock */ 919 /* Initialize the vde clock */
927 dd->aes_clk = clk_get(dev, "vde"); 920 dd->aes_clk = devm_clk_get(dev, "vde");
928 if (IS_ERR(dd->aes_clk)) { 921 if (IS_ERR(dd->aes_clk)) {
929 dev_err(dev, "iclock intialization failed.\n"); 922 dev_err(dev, "iclock intialization failed.\n");
930 err = -ENODEV; 923 err = -ENODEV;
@@ -1033,8 +1026,6 @@ out:
1033 if (dd->buf_out) 1026 if (dd->buf_out)
1034 dma_free_coherent(dev, AES_HW_DMA_BUFFER_SIZE_BYTES, 1027 dma_free_coherent(dev, AES_HW_DMA_BUFFER_SIZE_BYTES,
1035 dd->buf_out, dd->dma_buf_out); 1028 dd->buf_out, dd->dma_buf_out);
1036 if (!IS_ERR(dd->aes_clk))
1037 clk_put(dd->aes_clk);
1038 if (aes_wq) 1029 if (aes_wq)
1039 destroy_workqueue(aes_wq); 1030 destroy_workqueue(aes_wq);
1040 spin_lock(&list_lock); 1031 spin_lock(&list_lock);
@@ -1068,7 +1059,6 @@ static int tegra_aes_remove(struct platform_device *pdev)
1068 dd->buf_in, dd->dma_buf_in); 1059 dd->buf_in, dd->dma_buf_in);
1069 dma_free_coherent(dev, AES_HW_DMA_BUFFER_SIZE_BYTES, 1060 dma_free_coherent(dev, AES_HW_DMA_BUFFER_SIZE_BYTES,
1070 dd->buf_out, dd->dma_buf_out); 1061 dd->buf_out, dd->dma_buf_out);
1071 clk_put(dd->aes_clk);
1072 aes_dev = NULL; 1062 aes_dev = NULL;
1073 1063
1074 return 0; 1064 return 0;
diff --git a/drivers/dma/dmaengine.c b/drivers/dma/dmaengine.c
index ea806bdc12ef..24095ff8a93b 100644
--- a/drivers/dma/dmaengine.c
+++ b/drivers/dma/dmaengine.c
@@ -535,11 +535,41 @@ struct dma_chan *dma_get_slave_channel(struct dma_chan *chan)
535} 535}
536EXPORT_SYMBOL_GPL(dma_get_slave_channel); 536EXPORT_SYMBOL_GPL(dma_get_slave_channel);
537 537
538struct dma_chan *dma_get_any_slave_channel(struct dma_device *device)
539{
540 dma_cap_mask_t mask;
541 struct dma_chan *chan;
542 int err;
543
544 dma_cap_zero(mask);
545 dma_cap_set(DMA_SLAVE, mask);
546
547 /* lock against __dma_request_channel */
548 mutex_lock(&dma_list_mutex);
549
550 chan = private_candidate(&mask, device, NULL, NULL);
551 if (chan) {
552 err = dma_chan_get(chan);
553 if (err) {
554 pr_debug("%s: failed to get %s: (%d)\n",
555 __func__, dma_chan_name(chan), err);
556 chan = NULL;
557 }
558 }
559
560 mutex_unlock(&dma_list_mutex);
561
562 return chan;
563}
564EXPORT_SYMBOL_GPL(dma_get_any_slave_channel);
565
538/** 566/**
539 * __dma_request_channel - try to allocate an exclusive channel 567 * __dma_request_channel - try to allocate an exclusive channel
540 * @mask: capabilities that the channel must satisfy 568 * @mask: capabilities that the channel must satisfy
541 * @fn: optional callback to disposition available channels 569 * @fn: optional callback to disposition available channels
542 * @fn_param: opaque parameter to pass to dma_filter_fn 570 * @fn_param: opaque parameter to pass to dma_filter_fn
571 *
572 * Returns pointer to appropriate DMA channel on success or NULL.
543 */ 573 */
544struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask, 574struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
545 dma_filter_fn fn, void *fn_param) 575 dma_filter_fn fn, void *fn_param)
@@ -591,18 +621,43 @@ EXPORT_SYMBOL_GPL(__dma_request_channel);
591 * dma_request_slave_channel - try to allocate an exclusive slave channel 621 * dma_request_slave_channel - try to allocate an exclusive slave channel
592 * @dev: pointer to client device structure 622 * @dev: pointer to client device structure
593 * @name: slave channel name 623 * @name: slave channel name
624 *
625 * Returns pointer to appropriate DMA channel on success or an error pointer.
594 */ 626 */
595struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name) 627struct dma_chan *dma_request_slave_channel_reason(struct device *dev,
628 const char *name)
596{ 629{
630 struct dma_chan *chan;
631
597 /* If device-tree is present get slave info from here */ 632 /* If device-tree is present get slave info from here */
598 if (dev->of_node) 633 if (dev->of_node)
599 return of_dma_request_slave_channel(dev->of_node, name); 634 return of_dma_request_slave_channel(dev->of_node, name);
600 635
601 /* If device was enumerated by ACPI get slave info from here */ 636 /* If device was enumerated by ACPI get slave info from here */
602 if (ACPI_HANDLE(dev)) 637 if (ACPI_HANDLE(dev)) {
603 return acpi_dma_request_slave_chan_by_name(dev, name); 638 chan = acpi_dma_request_slave_chan_by_name(dev, name);
639 if (chan)
640 return chan;
641 }
604 642
605 return NULL; 643 return ERR_PTR(-ENODEV);
644}
645EXPORT_SYMBOL_GPL(dma_request_slave_channel_reason);
646
647/**
648 * dma_request_slave_channel - try to allocate an exclusive slave channel
649 * @dev: pointer to client device structure
650 * @name: slave channel name
651 *
652 * Returns pointer to appropriate DMA channel on success or NULL.
653 */
654struct dma_chan *dma_request_slave_channel(struct device *dev,
655 const char *name)
656{
657 struct dma_chan *ch = dma_request_slave_channel_reason(dev, name);
658 if (IS_ERR(ch))
659 return NULL;
660 return ch;
606} 661}
607EXPORT_SYMBOL_GPL(dma_request_slave_channel); 662EXPORT_SYMBOL_GPL(dma_request_slave_channel);
608 663
diff --git a/drivers/dma/mmp_pdma.c b/drivers/dma/mmp_pdma.c
index dcb1e05149a7..2998f1bffac1 100644
--- a/drivers/dma/mmp_pdma.c
+++ b/drivers/dma/mmp_pdma.c
@@ -893,33 +893,17 @@ static struct dma_chan *mmp_pdma_dma_xlate(struct of_phandle_args *dma_spec,
893 struct of_dma *ofdma) 893 struct of_dma *ofdma)
894{ 894{
895 struct mmp_pdma_device *d = ofdma->of_dma_data; 895 struct mmp_pdma_device *d = ofdma->of_dma_data;
896 struct dma_chan *chan, *candidate; 896 struct dma_chan *chan;
897 struct mmp_pdma_chan *c;
897 898
898retry: 899 chan = dma_get_any_slave_channel(&d->device);
899 candidate = NULL; 900 if (!chan)
900
901 /* walk the list of channels registered with the current instance and
902 * find one that is currently unused */
903 list_for_each_entry(chan, &d->device.channels, device_node)
904 if (chan->client_count == 0) {
905 candidate = chan;
906 break;
907 }
908
909 if (!candidate)
910 return NULL; 901 return NULL;
911 902
912 /* dma_get_slave_channel will return NULL if we lost a race between 903 c = to_mmp_pdma_chan(chan);
913 * the lookup and the reservation */ 904 c->drcmr = dma_spec->args[0];
914 chan = dma_get_slave_channel(candidate);
915
916 if (chan) {
917 struct mmp_pdma_chan *c = to_mmp_pdma_chan(chan);
918 c->drcmr = dma_spec->args[0];
919 return chan;
920 }
921 905
922 goto retry; 906 return chan;
923} 907}
924 908
925static int mmp_pdma_probe(struct platform_device *op) 909static int mmp_pdma_probe(struct platform_device *op)
diff --git a/drivers/dma/of-dma.c b/drivers/dma/of-dma.c
index 0b88dd3d05f4..e8fe9dc455f4 100644
--- a/drivers/dma/of-dma.c
+++ b/drivers/dma/of-dma.c
@@ -143,7 +143,7 @@ static int of_dma_match_channel(struct device_node *np, const char *name,
143 * @np: device node to get DMA request from 143 * @np: device node to get DMA request from
144 * @name: name of desired channel 144 * @name: name of desired channel
145 * 145 *
146 * Returns pointer to appropriate dma channel on success or NULL on error. 146 * Returns pointer to appropriate DMA channel on success or an error pointer.
147 */ 147 */
148struct dma_chan *of_dma_request_slave_channel(struct device_node *np, 148struct dma_chan *of_dma_request_slave_channel(struct device_node *np,
149 const char *name) 149 const char *name)
@@ -152,17 +152,18 @@ struct dma_chan *of_dma_request_slave_channel(struct device_node *np,
152 struct of_dma *ofdma; 152 struct of_dma *ofdma;
153 struct dma_chan *chan; 153 struct dma_chan *chan;
154 int count, i; 154 int count, i;
155 int ret_no_channel = -ENODEV;
155 156
156 if (!np || !name) { 157 if (!np || !name) {
157 pr_err("%s: not enough information provided\n", __func__); 158 pr_err("%s: not enough information provided\n", __func__);
158 return NULL; 159 return ERR_PTR(-ENODEV);
159 } 160 }
160 161
161 count = of_property_count_strings(np, "dma-names"); 162 count = of_property_count_strings(np, "dma-names");
162 if (count < 0) { 163 if (count < 0) {
163 pr_err("%s: dma-names property of node '%s' missing or empty\n", 164 pr_err("%s: dma-names property of node '%s' missing or empty\n",
164 __func__, np->full_name); 165 __func__, np->full_name);
165 return NULL; 166 return ERR_PTR(-ENODEV);
166 } 167 }
167 168
168 for (i = 0; i < count; i++) { 169 for (i = 0; i < count; i++) {
@@ -172,10 +173,12 @@ struct dma_chan *of_dma_request_slave_channel(struct device_node *np,
172 mutex_lock(&of_dma_lock); 173 mutex_lock(&of_dma_lock);
173 ofdma = of_dma_find_controller(&dma_spec); 174 ofdma = of_dma_find_controller(&dma_spec);
174 175
175 if (ofdma) 176 if (ofdma) {
176 chan = ofdma->of_dma_xlate(&dma_spec, ofdma); 177 chan = ofdma->of_dma_xlate(&dma_spec, ofdma);
177 else 178 } else {
179 ret_no_channel = -EPROBE_DEFER;
178 chan = NULL; 180 chan = NULL;
181 }
179 182
180 mutex_unlock(&of_dma_lock); 183 mutex_unlock(&of_dma_lock);
181 184
@@ -185,7 +188,7 @@ struct dma_chan *of_dma_request_slave_channel(struct device_node *np,
185 return chan; 188 return chan;
186 } 189 }
187 190
188 return NULL; 191 return ERR_PTR(ret_no_channel);
189} 192}
190 193
191/** 194/**
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index b8c031b7de4e..00a2de957b23 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -2409,6 +2409,7 @@ static void d40_set_prio_realtime(struct d40_chan *d40c)
2409#define D40_DT_FLAGS_DIR(flags) ((flags >> 1) & 0x1) 2409#define D40_DT_FLAGS_DIR(flags) ((flags >> 1) & 0x1)
2410#define D40_DT_FLAGS_BIG_ENDIAN(flags) ((flags >> 2) & 0x1) 2410#define D40_DT_FLAGS_BIG_ENDIAN(flags) ((flags >> 2) & 0x1)
2411#define D40_DT_FLAGS_FIXED_CHAN(flags) ((flags >> 3) & 0x1) 2411#define D40_DT_FLAGS_FIXED_CHAN(flags) ((flags >> 3) & 0x1)
2412#define D40_DT_FLAGS_HIGH_PRIO(flags) ((flags >> 4) & 0x1)
2412 2413
2413static struct dma_chan *d40_xlate(struct of_phandle_args *dma_spec, 2414static struct dma_chan *d40_xlate(struct of_phandle_args *dma_spec,
2414 struct of_dma *ofdma) 2415 struct of_dma *ofdma)
@@ -2446,6 +2447,9 @@ static struct dma_chan *d40_xlate(struct of_phandle_args *dma_spec,
2446 cfg.use_fixed_channel = true; 2447 cfg.use_fixed_channel = true;
2447 } 2448 }
2448 2449
2450 if (D40_DT_FLAGS_HIGH_PRIO(flags))
2451 cfg.high_priority = true;
2452
2449 return dma_request_channel(cap, stedma40_filter, &cfg); 2453 return dma_request_channel(cap, stedma40_filter, &cfg);
2450} 2454}
2451 2455
diff --git a/drivers/dma/tegra20-apb-dma.c b/drivers/dma/tegra20-apb-dma.c
index 73654e33f13b..d11bb3620f27 100644
--- a/drivers/dma/tegra20-apb-dma.c
+++ b/drivers/dma/tegra20-apb-dma.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * DMA driver for Nvidia's Tegra20 APB DMA controller. 2 * DMA driver for Nvidia's Tegra20 APB DMA controller.
3 * 3 *
4 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License, 7 * under the terms and conditions of the GNU General Public License,
@@ -29,11 +29,12 @@
29#include <linux/module.h> 29#include <linux/module.h>
30#include <linux/of.h> 30#include <linux/of.h>
31#include <linux/of_device.h> 31#include <linux/of_device.h>
32#include <linux/of_dma.h>
32#include <linux/platform_device.h> 33#include <linux/platform_device.h>
33#include <linux/pm.h> 34#include <linux/pm.h>
34#include <linux/pm_runtime.h> 35#include <linux/pm_runtime.h>
36#include <linux/reset.h>
35#include <linux/slab.h> 37#include <linux/slab.h>
36#include <linux/clk/tegra.h>
37 38
38#include "dmaengine.h" 39#include "dmaengine.h"
39 40
@@ -199,6 +200,7 @@ struct tegra_dma_channel {
199 void *callback_param; 200 void *callback_param;
200 201
201 /* Channel-slave specific configuration */ 202 /* Channel-slave specific configuration */
203 unsigned int slave_id;
202 struct dma_slave_config dma_sconfig; 204 struct dma_slave_config dma_sconfig;
203 struct tegra_dma_channel_regs channel_reg; 205 struct tegra_dma_channel_regs channel_reg;
204}; 206};
@@ -208,6 +210,7 @@ struct tegra_dma {
208 struct dma_device dma_dev; 210 struct dma_device dma_dev;
209 struct device *dev; 211 struct device *dev;
210 struct clk *dma_clk; 212 struct clk *dma_clk;
213 struct reset_control *rst;
211 spinlock_t global_lock; 214 spinlock_t global_lock;
212 void __iomem *base_addr; 215 void __iomem *base_addr;
213 const struct tegra_dma_chip_data *chip_data; 216 const struct tegra_dma_chip_data *chip_data;
@@ -339,6 +342,8 @@ static int tegra_dma_slave_config(struct dma_chan *dc,
339 } 342 }
340 343
341 memcpy(&tdc->dma_sconfig, sconfig, sizeof(*sconfig)); 344 memcpy(&tdc->dma_sconfig, sconfig, sizeof(*sconfig));
345 if (!tdc->slave_id)
346 tdc->slave_id = sconfig->slave_id;
342 tdc->config_init = true; 347 tdc->config_init = true;
343 return 0; 348 return 0;
344} 349}
@@ -941,7 +946,7 @@ static struct dma_async_tx_descriptor *tegra_dma_prep_slave_sg(
941 ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32; 946 ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32;
942 947
943 csr |= TEGRA_APBDMA_CSR_ONCE | TEGRA_APBDMA_CSR_FLOW; 948 csr |= TEGRA_APBDMA_CSR_ONCE | TEGRA_APBDMA_CSR_FLOW;
944 csr |= tdc->dma_sconfig.slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT; 949 csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
945 if (flags & DMA_PREP_INTERRUPT) 950 if (flags & DMA_PREP_INTERRUPT)
946 csr |= TEGRA_APBDMA_CSR_IE_EOC; 951 csr |= TEGRA_APBDMA_CSR_IE_EOC;
947 952
@@ -1085,7 +1090,7 @@ static struct dma_async_tx_descriptor *tegra_dma_prep_dma_cyclic(
1085 csr |= TEGRA_APBDMA_CSR_FLOW; 1090 csr |= TEGRA_APBDMA_CSR_FLOW;
1086 if (flags & DMA_PREP_INTERRUPT) 1091 if (flags & DMA_PREP_INTERRUPT)
1087 csr |= TEGRA_APBDMA_CSR_IE_EOC; 1092 csr |= TEGRA_APBDMA_CSR_IE_EOC;
1088 csr |= tdc->dma_sconfig.slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT; 1093 csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
1089 1094
1090 apb_seq |= TEGRA_APBDMA_APBSEQ_WRAP_WORD_1; 1095 apb_seq |= TEGRA_APBDMA_APBSEQ_WRAP_WORD_1;
1091 1096
@@ -1205,6 +1210,25 @@ static void tegra_dma_free_chan_resources(struct dma_chan *dc)
1205 kfree(sg_req); 1210 kfree(sg_req);
1206 } 1211 }
1207 clk_disable_unprepare(tdma->dma_clk); 1212 clk_disable_unprepare(tdma->dma_clk);
1213
1214 tdc->slave_id = 0;
1215}
1216
1217static struct dma_chan *tegra_dma_of_xlate(struct of_phandle_args *dma_spec,
1218 struct of_dma *ofdma)
1219{
1220 struct tegra_dma *tdma = ofdma->of_dma_data;
1221 struct dma_chan *chan;
1222 struct tegra_dma_channel *tdc;
1223
1224 chan = dma_get_any_slave_channel(&tdma->dma_dev);
1225 if (!chan)
1226 return NULL;
1227
1228 tdc = to_tegra_dma_chan(chan);
1229 tdc->slave_id = dma_spec->args[0];
1230
1231 return chan;
1208} 1232}
1209 1233
1210/* Tegra20 specific DMA controller information */ 1234/* Tegra20 specific DMA controller information */
@@ -1282,6 +1306,12 @@ static int tegra_dma_probe(struct platform_device *pdev)
1282 return PTR_ERR(tdma->dma_clk); 1306 return PTR_ERR(tdma->dma_clk);
1283 } 1307 }
1284 1308
1309 tdma->rst = devm_reset_control_get(&pdev->dev, "dma");
1310 if (IS_ERR(tdma->rst)) {
1311 dev_err(&pdev->dev, "Error: Missing reset\n");
1312 return PTR_ERR(tdma->rst);
1313 }
1314
1285 spin_lock_init(&tdma->global_lock); 1315 spin_lock_init(&tdma->global_lock);
1286 1316
1287 pm_runtime_enable(&pdev->dev); 1317 pm_runtime_enable(&pdev->dev);
@@ -1302,9 +1332,9 @@ static int tegra_dma_probe(struct platform_device *pdev)
1302 } 1332 }
1303 1333
1304 /* Reset DMA controller */ 1334 /* Reset DMA controller */
1305 tegra_periph_reset_assert(tdma->dma_clk); 1335 reset_control_assert(tdma->rst);
1306 udelay(2); 1336 udelay(2);
1307 tegra_periph_reset_deassert(tdma->dma_clk); 1337 reset_control_deassert(tdma->rst);
1308 1338
1309 /* Enable global DMA registers */ 1339 /* Enable global DMA registers */
1310 tdma_write(tdma, TEGRA_APBDMA_GENERAL, TEGRA_APBDMA_GENERAL_ENABLE); 1340 tdma_write(tdma, TEGRA_APBDMA_GENERAL, TEGRA_APBDMA_GENERAL_ENABLE);
@@ -1376,10 +1406,20 @@ static int tegra_dma_probe(struct platform_device *pdev)
1376 goto err_irq; 1406 goto err_irq;
1377 } 1407 }
1378 1408
1409 ret = of_dma_controller_register(pdev->dev.of_node,
1410 tegra_dma_of_xlate, tdma);
1411 if (ret < 0) {
1412 dev_err(&pdev->dev,
1413 "Tegra20 APB DMA OF registration failed %d\n", ret);
1414 goto err_unregister_dma_dev;
1415 }
1416
1379 dev_info(&pdev->dev, "Tegra20 APB DMA driver register %d channels\n", 1417 dev_info(&pdev->dev, "Tegra20 APB DMA driver register %d channels\n",
1380 cdata->nr_channels); 1418 cdata->nr_channels);
1381 return 0; 1419 return 0;
1382 1420
1421err_unregister_dma_dev:
1422 dma_async_device_unregister(&tdma->dma_dev);
1383err_irq: 1423err_irq:
1384 while (--i >= 0) { 1424 while (--i >= 0) {
1385 struct tegra_dma_channel *tdc = &tdma->channels[i]; 1425 struct tegra_dma_channel *tdc = &tdma->channels[i];
diff --git a/drivers/firewire/sbp2.c b/drivers/firewire/sbp2.c
index 281029daf98c..b0bb056458a3 100644
--- a/drivers/firewire/sbp2.c
+++ b/drivers/firewire/sbp2.c
@@ -1623,6 +1623,7 @@ static struct scsi_host_template scsi_driver_template = {
1623 .cmd_per_lun = 1, 1623 .cmd_per_lun = 1,
1624 .can_queue = 1, 1624 .can_queue = 1,
1625 .sdev_attrs = sbp2_scsi_sysfs_attrs, 1625 .sdev_attrs = sbp2_scsi_sysfs_attrs,
1626 .no_write_same = 1,
1626}; 1627};
1627 1628
1628MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>"); 1629MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
diff --git a/drivers/firmware/efi/efi-pstore.c b/drivers/firmware/efi/efi-pstore.c
index 5002d50e3781..743fd426f21b 100644
--- a/drivers/firmware/efi/efi-pstore.c
+++ b/drivers/firmware/efi/efi-pstore.c
@@ -18,14 +18,12 @@ module_param_named(pstore_disable, efivars_pstore_disable, bool, 0644);
18 18
19static int efi_pstore_open(struct pstore_info *psi) 19static int efi_pstore_open(struct pstore_info *psi)
20{ 20{
21 efivar_entry_iter_begin();
22 psi->data = NULL; 21 psi->data = NULL;
23 return 0; 22 return 0;
24} 23}
25 24
26static int efi_pstore_close(struct pstore_info *psi) 25static int efi_pstore_close(struct pstore_info *psi)
27{ 26{
28 efivar_entry_iter_end();
29 psi->data = NULL; 27 psi->data = NULL;
30 return 0; 28 return 0;
31} 29}
@@ -39,6 +37,12 @@ struct pstore_read_data {
39 char **buf; 37 char **buf;
40}; 38};
41 39
40static inline u64 generic_id(unsigned long timestamp,
41 unsigned int part, int count)
42{
43 return (timestamp * 100 + part) * 1000 + count;
44}
45
42static int efi_pstore_read_func(struct efivar_entry *entry, void *data) 46static int efi_pstore_read_func(struct efivar_entry *entry, void *data)
43{ 47{
44 efi_guid_t vendor = LINUX_EFI_CRASH_GUID; 48 efi_guid_t vendor = LINUX_EFI_CRASH_GUID;
@@ -57,7 +61,7 @@ static int efi_pstore_read_func(struct efivar_entry *entry, void *data)
57 61
58 if (sscanf(name, "dump-type%u-%u-%d-%lu-%c", 62 if (sscanf(name, "dump-type%u-%u-%d-%lu-%c",
59 cb_data->type, &part, &cnt, &time, &data_type) == 5) { 63 cb_data->type, &part, &cnt, &time, &data_type) == 5) {
60 *cb_data->id = part; 64 *cb_data->id = generic_id(time, part, cnt);
61 *cb_data->count = cnt; 65 *cb_data->count = cnt;
62 cb_data->timespec->tv_sec = time; 66 cb_data->timespec->tv_sec = time;
63 cb_data->timespec->tv_nsec = 0; 67 cb_data->timespec->tv_nsec = 0;
@@ -67,7 +71,7 @@ static int efi_pstore_read_func(struct efivar_entry *entry, void *data)
67 *cb_data->compressed = false; 71 *cb_data->compressed = false;
68 } else if (sscanf(name, "dump-type%u-%u-%d-%lu", 72 } else if (sscanf(name, "dump-type%u-%u-%d-%lu",
69 cb_data->type, &part, &cnt, &time) == 4) { 73 cb_data->type, &part, &cnt, &time) == 4) {
70 *cb_data->id = part; 74 *cb_data->id = generic_id(time, part, cnt);
71 *cb_data->count = cnt; 75 *cb_data->count = cnt;
72 cb_data->timespec->tv_sec = time; 76 cb_data->timespec->tv_sec = time;
73 cb_data->timespec->tv_nsec = 0; 77 cb_data->timespec->tv_nsec = 0;
@@ -79,7 +83,7 @@ static int efi_pstore_read_func(struct efivar_entry *entry, void *data)
79 * which doesn't support holding 83 * which doesn't support holding
80 * multiple logs, remains. 84 * multiple logs, remains.
81 */ 85 */
82 *cb_data->id = part; 86 *cb_data->id = generic_id(time, part, 0);
83 *cb_data->count = 0; 87 *cb_data->count = 0;
84 cb_data->timespec->tv_sec = time; 88 cb_data->timespec->tv_sec = time;
85 cb_data->timespec->tv_nsec = 0; 89 cb_data->timespec->tv_nsec = 0;
@@ -91,19 +95,125 @@ static int efi_pstore_read_func(struct efivar_entry *entry, void *data)
91 __efivar_entry_get(entry, &entry->var.Attributes, 95 __efivar_entry_get(entry, &entry->var.Attributes,
92 &entry->var.DataSize, entry->var.Data); 96 &entry->var.DataSize, entry->var.Data);
93 size = entry->var.DataSize; 97 size = entry->var.DataSize;
98 memcpy(*cb_data->buf, entry->var.Data,
99 (size_t)min_t(unsigned long, EFIVARS_DATA_SIZE_MAX, size));
94 100
95 *cb_data->buf = kmemdup(entry->var.Data, size, GFP_KERNEL);
96 if (*cb_data->buf == NULL)
97 return -ENOMEM;
98 return size; 101 return size;
99} 102}
100 103
104/**
105 * efi_pstore_scan_sysfs_enter
106 * @entry: scanning entry
107 * @next: next entry
108 * @head: list head
109 */
110static void efi_pstore_scan_sysfs_enter(struct efivar_entry *pos,
111 struct efivar_entry *next,
112 struct list_head *head)
113{
114 pos->scanning = true;
115 if (&next->list != head)
116 next->scanning = true;
117}
118
119/**
120 * __efi_pstore_scan_sysfs_exit
121 * @entry: deleting entry
122 * @turn_off_scanning: Check if a scanning flag should be turned off
123 */
124static inline void __efi_pstore_scan_sysfs_exit(struct efivar_entry *entry,
125 bool turn_off_scanning)
126{
127 if (entry->deleting) {
128 list_del(&entry->list);
129 efivar_entry_iter_end();
130 efivar_unregister(entry);
131 efivar_entry_iter_begin();
132 } else if (turn_off_scanning)
133 entry->scanning = false;
134}
135
136/**
137 * efi_pstore_scan_sysfs_exit
138 * @pos: scanning entry
139 * @next: next entry
140 * @head: list head
141 * @stop: a flag checking if scanning will stop
142 */
143static void efi_pstore_scan_sysfs_exit(struct efivar_entry *pos,
144 struct efivar_entry *next,
145 struct list_head *head, bool stop)
146{
147 __efi_pstore_scan_sysfs_exit(pos, true);
148 if (stop)
149 __efi_pstore_scan_sysfs_exit(next, &next->list != head);
150}
151
152/**
153 * efi_pstore_sysfs_entry_iter
154 *
155 * @data: function-specific data to pass to callback
156 * @pos: entry to begin iterating from
157 *
158 * You MUST call efivar_enter_iter_begin() before this function, and
159 * efivar_entry_iter_end() afterwards.
160 *
161 * It is possible to begin iteration from an arbitrary entry within
162 * the list by passing @pos. @pos is updated on return to point to
163 * the next entry of the last one passed to efi_pstore_read_func().
164 * To begin iterating from the beginning of the list @pos must be %NULL.
165 */
166static int efi_pstore_sysfs_entry_iter(void *data, struct efivar_entry **pos)
167{
168 struct efivar_entry *entry, *n;
169 struct list_head *head = &efivar_sysfs_list;
170 int size = 0;
171
172 if (!*pos) {
173 list_for_each_entry_safe(entry, n, head, list) {
174 efi_pstore_scan_sysfs_enter(entry, n, head);
175
176 size = efi_pstore_read_func(entry, data);
177 efi_pstore_scan_sysfs_exit(entry, n, head, size < 0);
178 if (size)
179 break;
180 }
181 *pos = n;
182 return size;
183 }
184
185 list_for_each_entry_safe_from((*pos), n, head, list) {
186 efi_pstore_scan_sysfs_enter((*pos), n, head);
187
188 size = efi_pstore_read_func((*pos), data);
189 efi_pstore_scan_sysfs_exit((*pos), n, head, size < 0);
190 if (size)
191 break;
192 }
193 *pos = n;
194 return size;
195}
196
197/**
198 * efi_pstore_read
199 *
200 * This function returns a size of NVRAM entry logged via efi_pstore_write().
201 * The meaning and behavior of efi_pstore/pstore are as below.
202 *
203 * size > 0: Got data of an entry logged via efi_pstore_write() successfully,
204 * and pstore filesystem will continue reading subsequent entries.
205 * size == 0: Entry was not logged via efi_pstore_write(),
206 * and efi_pstore driver will continue reading subsequent entries.
207 * size < 0: Failed to get data of entry logging via efi_pstore_write(),
208 * and pstore will stop reading entry.
209 */
101static ssize_t efi_pstore_read(u64 *id, enum pstore_type_id *type, 210static ssize_t efi_pstore_read(u64 *id, enum pstore_type_id *type,
102 int *count, struct timespec *timespec, 211 int *count, struct timespec *timespec,
103 char **buf, bool *compressed, 212 char **buf, bool *compressed,
104 struct pstore_info *psi) 213 struct pstore_info *psi)
105{ 214{
106 struct pstore_read_data data; 215 struct pstore_read_data data;
216 ssize_t size;
107 217
108 data.id = id; 218 data.id = id;
109 data.type = type; 219 data.type = type;
@@ -112,8 +222,17 @@ static ssize_t efi_pstore_read(u64 *id, enum pstore_type_id *type,
112 data.compressed = compressed; 222 data.compressed = compressed;
113 data.buf = buf; 223 data.buf = buf;
114 224
115 return __efivar_entry_iter(efi_pstore_read_func, &efivar_sysfs_list, &data, 225 *data.buf = kzalloc(EFIVARS_DATA_SIZE_MAX, GFP_KERNEL);
116 (struct efivar_entry **)&psi->data); 226 if (!*data.buf)
227 return -ENOMEM;
228
229 efivar_entry_iter_begin();
230 size = efi_pstore_sysfs_entry_iter(&data,
231 (struct efivar_entry **)&psi->data);
232 efivar_entry_iter_end();
233 if (size <= 0)
234 kfree(*data.buf);
235 return size;
117} 236}
118 237
119static int efi_pstore_write(enum pstore_type_id type, 238static int efi_pstore_write(enum pstore_type_id type,
@@ -184,9 +303,17 @@ static int efi_pstore_erase_func(struct efivar_entry *entry, void *data)
184 return 0; 303 return 0;
185 } 304 }
186 305
306 if (entry->scanning) {
307 /*
308 * Skip deletion because this entry will be deleted
309 * after scanning is completed.
310 */
311 entry->deleting = true;
312 } else
313 list_del(&entry->list);
314
187 /* found */ 315 /* found */
188 __efivar_entry_delete(entry); 316 __efivar_entry_delete(entry);
189 list_del(&entry->list);
190 317
191 return 1; 318 return 1;
192} 319}
@@ -199,14 +326,16 @@ static int efi_pstore_erase(enum pstore_type_id type, u64 id, int count,
199 char name[DUMP_NAME_LEN]; 326 char name[DUMP_NAME_LEN];
200 efi_char16_t efi_name[DUMP_NAME_LEN]; 327 efi_char16_t efi_name[DUMP_NAME_LEN];
201 int found, i; 328 int found, i;
329 unsigned int part;
202 330
203 sprintf(name, "dump-type%u-%u-%d-%lu", type, (unsigned int)id, count, 331 do_div(id, 1000);
204 time.tv_sec); 332 part = do_div(id, 100);
333 sprintf(name, "dump-type%u-%u-%d-%lu", type, part, count, time.tv_sec);
205 334
206 for (i = 0; i < DUMP_NAME_LEN; i++) 335 for (i = 0; i < DUMP_NAME_LEN; i++)
207 efi_name[i] = name[i]; 336 efi_name[i] = name[i];
208 337
209 edata.id = id; 338 edata.id = part;
210 edata.type = type; 339 edata.type = type;
211 edata.count = count; 340 edata.count = count;
212 edata.time = time; 341 edata.time = time;
@@ -214,10 +343,12 @@ static int efi_pstore_erase(enum pstore_type_id type, u64 id, int count,
214 343
215 efivar_entry_iter_begin(); 344 efivar_entry_iter_begin();
216 found = __efivar_entry_iter(efi_pstore_erase_func, &efivar_sysfs_list, &edata, &entry); 345 found = __efivar_entry_iter(efi_pstore_erase_func, &efivar_sysfs_list, &edata, &entry);
217 efivar_entry_iter_end();
218 346
219 if (found) 347 if (found && !entry->scanning) {
348 efivar_entry_iter_end();
220 efivar_unregister(entry); 349 efivar_unregister(entry);
350 } else
351 efivar_entry_iter_end();
221 352
222 return 0; 353 return 0;
223} 354}
diff --git a/drivers/firmware/efi/efivars.c b/drivers/firmware/efi/efivars.c
index 933eb027d527..3dc248239197 100644
--- a/drivers/firmware/efi/efivars.c
+++ b/drivers/firmware/efi/efivars.c
@@ -383,12 +383,16 @@ static ssize_t efivar_delete(struct file *filp, struct kobject *kobj,
383 else if (__efivar_entry_delete(entry)) 383 else if (__efivar_entry_delete(entry))
384 err = -EIO; 384 err = -EIO;
385 385
386 efivar_entry_iter_end(); 386 if (err) {
387 387 efivar_entry_iter_end();
388 if (err)
389 return err; 388 return err;
389 }
390 390
391 efivar_unregister(entry); 391 if (!entry->scanning) {
392 efivar_entry_iter_end();
393 efivar_unregister(entry);
394 } else
395 efivar_entry_iter_end();
392 396
393 /* It's dead Jim.... */ 397 /* It's dead Jim.... */
394 return count; 398 return count;
diff --git a/drivers/firmware/efi/vars.c b/drivers/firmware/efi/vars.c
index 391c67b182d9..b22659cccca4 100644
--- a/drivers/firmware/efi/vars.c
+++ b/drivers/firmware/efi/vars.c
@@ -683,8 +683,16 @@ struct efivar_entry *efivar_entry_find(efi_char16_t *name, efi_guid_t guid,
683 if (!found) 683 if (!found)
684 return NULL; 684 return NULL;
685 685
686 if (remove) 686 if (remove) {
687 list_del(&entry->list); 687 if (entry->scanning) {
688 /*
689 * The entry will be deleted
690 * after scanning is completed.
691 */
692 entry->deleting = true;
693 } else
694 list_del(&entry->list);
695 }
688 696
689 return entry; 697 return entry;
690} 698}
diff --git a/drivers/gpio/gpio-bcm-kona.c b/drivers/gpio/gpio-bcm-kona.c
index 72c927dc3be1..54c18c220a60 100644
--- a/drivers/gpio/gpio-bcm-kona.c
+++ b/drivers/gpio/gpio-bcm-kona.c
@@ -158,7 +158,7 @@ static int bcm_kona_gpio_get(struct gpio_chip *chip, unsigned gpio)
158 spin_unlock_irqrestore(&kona_gpio->lock, flags); 158 spin_unlock_irqrestore(&kona_gpio->lock, flags);
159 159
160 /* return the specified bit status */ 160 /* return the specified bit status */
161 return !!(val & bit); 161 return !!(val & BIT(bit));
162} 162}
163 163
164static int bcm_kona_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) 164static int bcm_kona_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
diff --git a/drivers/gpio/gpio-mpc8xxx.c b/drivers/gpio/gpio-mpc8xxx.c
index 914e859e3eda..d7d6d72eba33 100644
--- a/drivers/gpio/gpio-mpc8xxx.c
+++ b/drivers/gpio/gpio-mpc8xxx.c
@@ -70,10 +70,14 @@ static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
70 u32 val; 70 u32 val;
71 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); 71 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
72 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); 72 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
73 u32 out_mask, out_shadow;
73 74
74 val = in_be32(mm->regs + GPIO_DAT) & ~in_be32(mm->regs + GPIO_DIR); 75 out_mask = in_be32(mm->regs + GPIO_DIR);
75 76
76 return (val | mpc8xxx_gc->data) & mpc8xxx_gpio2mask(gpio); 77 val = in_be32(mm->regs + GPIO_DAT) & ~out_mask;
78 out_shadow = mpc8xxx_gc->data & out_mask;
79
80 return (val | out_shadow) & mpc8xxx_gpio2mask(gpio);
77} 81}
78 82
79static int mpc8xxx_gpio_get(struct gpio_chip *gc, unsigned int gpio) 83static int mpc8xxx_gpio_get(struct gpio_chip *gc, unsigned int gpio)
diff --git a/drivers/gpio/gpio-msm-v2.c b/drivers/gpio/gpio-msm-v2.c
index f7a0cc4da950..7b37300973db 100644
--- a/drivers/gpio/gpio-msm-v2.c
+++ b/drivers/gpio/gpio-msm-v2.c
@@ -102,7 +102,7 @@ struct msm_gpio_dev {
102 DECLARE_BITMAP(wake_irqs, MAX_NR_GPIO); 102 DECLARE_BITMAP(wake_irqs, MAX_NR_GPIO);
103 DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO); 103 DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO);
104 struct irq_domain *domain; 104 struct irq_domain *domain;
105 unsigned int summary_irq; 105 int summary_irq;
106 void __iomem *msm_tlmm_base; 106 void __iomem *msm_tlmm_base;
107}; 107};
108 108
diff --git a/drivers/gpio/gpio-mvebu.c b/drivers/gpio/gpio-mvebu.c
index 3c3321f94053..db3129043e63 100644
--- a/drivers/gpio/gpio-mvebu.c
+++ b/drivers/gpio/gpio-mvebu.c
@@ -79,7 +79,7 @@ struct mvebu_gpio_chip {
79 spinlock_t lock; 79 spinlock_t lock;
80 void __iomem *membase; 80 void __iomem *membase;
81 void __iomem *percpu_membase; 81 void __iomem *percpu_membase;
82 unsigned int irqbase; 82 int irqbase;
83 struct irq_domain *domain; 83 struct irq_domain *domain;
84 int soc_variant; 84 int soc_variant;
85}; 85};
diff --git a/drivers/gpio/gpio-pl061.c b/drivers/gpio/gpio-pl061.c
index f22f7f3e2e53..b4d42112d02d 100644
--- a/drivers/gpio/gpio-pl061.c
+++ b/drivers/gpio/gpio-pl061.c
@@ -286,11 +286,6 @@ static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
286 if (!chip->base) 286 if (!chip->base)
287 return -ENOMEM; 287 return -ENOMEM;
288 288
289 chip->domain = irq_domain_add_simple(adev->dev.of_node, PL061_GPIO_NR,
290 irq_base, &pl061_domain_ops, chip);
291 if (!chip->domain)
292 return -ENODEV;
293
294 spin_lock_init(&chip->lock); 289 spin_lock_init(&chip->lock);
295 290
296 chip->gc.request = pl061_gpio_request; 291 chip->gc.request = pl061_gpio_request;
@@ -320,6 +315,11 @@ static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
320 irq_set_chained_handler(irq, pl061_irq_handler); 315 irq_set_chained_handler(irq, pl061_irq_handler);
321 irq_set_handler_data(irq, chip); 316 irq_set_handler_data(irq, chip);
322 317
318 chip->domain = irq_domain_add_simple(adev->dev.of_node, PL061_GPIO_NR,
319 irq_base, &pl061_domain_ops, chip);
320 if (!chip->domain)
321 return -ENODEV;
322
323 for (i = 0; i < PL061_GPIO_NR; i++) { 323 for (i = 0; i < PL061_GPIO_NR; i++) {
324 if (pdata) { 324 if (pdata) {
325 if (pdata->directions & (1 << i)) 325 if (pdata->directions & (1 << i))
diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c
index d3f15ae93bd3..fe088a30567a 100644
--- a/drivers/gpio/gpio-rcar.c
+++ b/drivers/gpio/gpio-rcar.c
@@ -381,7 +381,7 @@ static int gpio_rcar_probe(struct platform_device *pdev)
381 if (!p->irq_domain) { 381 if (!p->irq_domain) {
382 ret = -ENXIO; 382 ret = -ENXIO;
383 dev_err(&pdev->dev, "cannot initialize irq domain\n"); 383 dev_err(&pdev->dev, "cannot initialize irq domain\n");
384 goto err1; 384 goto err0;
385 } 385 }
386 386
387 if (devm_request_irq(&pdev->dev, irq->start, 387 if (devm_request_irq(&pdev->dev, irq->start,
diff --git a/drivers/gpio/gpio-tb10x.c b/drivers/gpio/gpio-tb10x.c
index 0502b9a041a5..da071ddbad99 100644
--- a/drivers/gpio/gpio-tb10x.c
+++ b/drivers/gpio/gpio-tb10x.c
@@ -132,6 +132,7 @@ static int tb10x_gpio_direction_out(struct gpio_chip *chip,
132 int mask = BIT(offset); 132 int mask = BIT(offset);
133 int val = TB10X_GPIO_DIR_OUT << offset; 133 int val = TB10X_GPIO_DIR_OUT << offset;
134 134
135 tb10x_gpio_set(chip, offset, value);
135 tb10x_set_bits(tb10x_gpio, OFFSET_TO_REG_DDR, mask, val); 136 tb10x_set_bits(tb10x_gpio, OFFSET_TO_REG_DDR, mask, val);
136 137
137 return 0; 138 return 0;
diff --git a/drivers/gpio/gpio-twl4030.c b/drivers/gpio/gpio-twl4030.c
index 0c7e891c8651..b97d6a6577b9 100644
--- a/drivers/gpio/gpio-twl4030.c
+++ b/drivers/gpio/gpio-twl4030.c
@@ -354,17 +354,18 @@ static void twl_set(struct gpio_chip *chip, unsigned offset, int value)
354static int twl_direction_out(struct gpio_chip *chip, unsigned offset, int value) 354static int twl_direction_out(struct gpio_chip *chip, unsigned offset, int value)
355{ 355{
356 struct gpio_twl4030_priv *priv = to_gpio_twl4030(chip); 356 struct gpio_twl4030_priv *priv = to_gpio_twl4030(chip);
357 int ret = -EINVAL;
357 358
358 mutex_lock(&priv->mutex); 359 mutex_lock(&priv->mutex);
359 if (offset < TWL4030_GPIO_MAX) 360 if (offset < TWL4030_GPIO_MAX)
360 twl4030_set_gpio_dataout(offset, value); 361 ret = twl4030_set_gpio_direction(offset, 0);
361 362
362 priv->direction |= BIT(offset); 363 priv->direction |= BIT(offset);
363 mutex_unlock(&priv->mutex); 364 mutex_unlock(&priv->mutex);
364 365
365 twl_set(chip, offset, value); 366 twl_set(chip, offset, value);
366 367
367 return 0; 368 return ret;
368} 369}
369 370
370static int twl_to_irq(struct gpio_chip *chip, unsigned offset) 371static int twl_to_irq(struct gpio_chip *chip, unsigned offset)
@@ -435,7 +436,8 @@ static int gpio_twl4030_debounce(u32 debounce, u8 mmc_cd)
435 436
436static int gpio_twl4030_remove(struct platform_device *pdev); 437static int gpio_twl4030_remove(struct platform_device *pdev);
437 438
438static struct twl4030_gpio_platform_data *of_gpio_twl4030(struct device *dev) 439static struct twl4030_gpio_platform_data *of_gpio_twl4030(struct device *dev,
440 struct twl4030_gpio_platform_data *pdata)
439{ 441{
440 struct twl4030_gpio_platform_data *omap_twl_info; 442 struct twl4030_gpio_platform_data *omap_twl_info;
441 443
@@ -443,6 +445,9 @@ static struct twl4030_gpio_platform_data *of_gpio_twl4030(struct device *dev)
443 if (!omap_twl_info) 445 if (!omap_twl_info)
444 return NULL; 446 return NULL;
445 447
448 if (pdata)
449 *omap_twl_info = *pdata;
450
446 omap_twl_info->use_leds = of_property_read_bool(dev->of_node, 451 omap_twl_info->use_leds = of_property_read_bool(dev->of_node,
447 "ti,use-leds"); 452 "ti,use-leds");
448 453
@@ -500,7 +505,7 @@ no_irqs:
500 mutex_init(&priv->mutex); 505 mutex_init(&priv->mutex);
501 506
502 if (node) 507 if (node)
503 pdata = of_gpio_twl4030(&pdev->dev); 508 pdata = of_gpio_twl4030(&pdev->dev, pdata);
504 509
505 if (pdata == NULL) { 510 if (pdata == NULL) {
506 dev_err(&pdev->dev, "Platform data is missing\n"); 511 dev_err(&pdev->dev, "Platform data is missing\n");
diff --git a/drivers/gpio/gpio-ucb1400.c b/drivers/gpio/gpio-ucb1400.c
index 1a605f2a0f55..06fb5cf99ded 100644
--- a/drivers/gpio/gpio-ucb1400.c
+++ b/drivers/gpio/gpio-ucb1400.c
@@ -105,3 +105,4 @@ module_platform_driver(ucb1400_gpio_driver);
105 105
106MODULE_DESCRIPTION("Philips UCB1400 GPIO driver"); 106MODULE_DESCRIPTION("Philips UCB1400 GPIO driver");
107MODULE_LICENSE("GPL"); 107MODULE_LICENSE("GPL");
108MODULE_ALIAS("platform:ucb1400_gpio");
diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
index 4e10b10d3ddd..85f772c0b26a 100644
--- a/drivers/gpio/gpiolib.c
+++ b/drivers/gpio/gpiolib.c
@@ -14,6 +14,7 @@
14#include <linux/idr.h> 14#include <linux/idr.h>
15#include <linux/slab.h> 15#include <linux/slab.h>
16#include <linux/acpi.h> 16#include <linux/acpi.h>
17#include <linux/gpio/driver.h>
17 18
18#define CREATE_TRACE_POINTS 19#define CREATE_TRACE_POINTS
19#include <trace/events/gpio.h> 20#include <trace/events/gpio.h>
@@ -1308,6 +1309,18 @@ struct gpio_chip *gpiochip_find(void *data,
1308} 1309}
1309EXPORT_SYMBOL_GPL(gpiochip_find); 1310EXPORT_SYMBOL_GPL(gpiochip_find);
1310 1311
1312static int gpiochip_match_name(struct gpio_chip *chip, void *data)
1313{
1314 const char *name = data;
1315
1316 return !strcmp(chip->label, name);
1317}
1318
1319static struct gpio_chip *find_chip_by_name(const char *name)
1320{
1321 return gpiochip_find((void *)name, gpiochip_match_name);
1322}
1323
1311#ifdef CONFIG_PINCTRL 1324#ifdef CONFIG_PINCTRL
1312 1325
1313/** 1326/**
@@ -1341,8 +1354,10 @@ int gpiochip_add_pingroup_range(struct gpio_chip *chip,
1341 ret = pinctrl_get_group_pins(pctldev, pin_group, 1354 ret = pinctrl_get_group_pins(pctldev, pin_group,
1342 &pin_range->range.pins, 1355 &pin_range->range.pins,
1343 &pin_range->range.npins); 1356 &pin_range->range.npins);
1344 if (ret < 0) 1357 if (ret < 0) {
1358 kfree(pin_range);
1345 return ret; 1359 return ret;
1360 }
1346 1361
1347 pinctrl_add_gpio_range(pctldev, &pin_range->range); 1362 pinctrl_add_gpio_range(pctldev, &pin_range->range);
1348 1363
@@ -2260,26 +2275,10 @@ void gpiod_add_table(struct gpiod_lookup *table, size_t size)
2260 mutex_unlock(&gpio_lookup_lock); 2275 mutex_unlock(&gpio_lookup_lock);
2261} 2276}
2262 2277
2263/*
2264 * Caller must have a acquired gpio_lookup_lock
2265 */
2266static struct gpio_chip *find_chip_by_name(const char *name)
2267{
2268 struct gpio_chip *chip = NULL;
2269
2270 list_for_each_entry(chip, &gpio_lookup_list, list) {
2271 if (chip->label == NULL)
2272 continue;
2273 if (!strcmp(chip->label, name))
2274 break;
2275 }
2276
2277 return chip;
2278}
2279
2280#ifdef CONFIG_OF 2278#ifdef CONFIG_OF
2281static struct gpio_desc *of_find_gpio(struct device *dev, const char *con_id, 2279static struct gpio_desc *of_find_gpio(struct device *dev, const char *con_id,
2282 unsigned int idx, unsigned long *flags) 2280 unsigned int idx,
2281 enum gpio_lookup_flags *flags)
2283{ 2282{
2284 char prop_name[32]; /* 32 is max size of property name */ 2283 char prop_name[32]; /* 32 is max size of property name */
2285 enum of_gpio_flags of_flags; 2284 enum of_gpio_flags of_flags;
@@ -2297,20 +2296,22 @@ static struct gpio_desc *of_find_gpio(struct device *dev, const char *con_id,
2297 return desc; 2296 return desc;
2298 2297
2299 if (of_flags & OF_GPIO_ACTIVE_LOW) 2298 if (of_flags & OF_GPIO_ACTIVE_LOW)
2300 *flags |= GPIOF_ACTIVE_LOW; 2299 *flags |= GPIO_ACTIVE_LOW;
2301 2300
2302 return desc; 2301 return desc;
2303} 2302}
2304#else 2303#else
2305static struct gpio_desc *of_find_gpio(struct device *dev, const char *con_id, 2304static struct gpio_desc *of_find_gpio(struct device *dev, const char *con_id,
2306 unsigned int idx, unsigned long *flags) 2305 unsigned int idx,
2306 enum gpio_lookup_flags *flags)
2307{ 2307{
2308 return ERR_PTR(-ENODEV); 2308 return ERR_PTR(-ENODEV);
2309} 2309}
2310#endif 2310#endif
2311 2311
2312static struct gpio_desc *acpi_find_gpio(struct device *dev, const char *con_id, 2312static struct gpio_desc *acpi_find_gpio(struct device *dev, const char *con_id,
2313 unsigned int idx, unsigned long *flags) 2313 unsigned int idx,
2314 enum gpio_lookup_flags *flags)
2314{ 2315{
2315 struct acpi_gpio_info info; 2316 struct acpi_gpio_info info;
2316 struct gpio_desc *desc; 2317 struct gpio_desc *desc;
@@ -2320,13 +2321,14 @@ static struct gpio_desc *acpi_find_gpio(struct device *dev, const char *con_id,
2320 return desc; 2321 return desc;
2321 2322
2322 if (info.gpioint && info.active_low) 2323 if (info.gpioint && info.active_low)
2323 *flags |= GPIOF_ACTIVE_LOW; 2324 *flags |= GPIO_ACTIVE_LOW;
2324 2325
2325 return desc; 2326 return desc;
2326} 2327}
2327 2328
2328static struct gpio_desc *gpiod_find(struct device *dev, const char *con_id, 2329static struct gpio_desc *gpiod_find(struct device *dev, const char *con_id,
2329 unsigned int idx, unsigned long *flags) 2330 unsigned int idx,
2331 enum gpio_lookup_flags *flags)
2330{ 2332{
2331 const char *dev_id = dev ? dev_name(dev) : NULL; 2333 const char *dev_id = dev ? dev_name(dev) : NULL;
2332 struct gpio_desc *desc = ERR_PTR(-ENODEV); 2334 struct gpio_desc *desc = ERR_PTR(-ENODEV);
@@ -2366,7 +2368,7 @@ static struct gpio_desc *gpiod_find(struct device *dev, const char *con_id,
2366 continue; 2368 continue;
2367 } 2369 }
2368 2370
2369 if (chip->ngpio >= p->chip_hwnum) { 2371 if (chip->ngpio <= p->chip_hwnum) {
2370 dev_warn(dev, "GPIO chip %s has %d GPIOs\n", 2372 dev_warn(dev, "GPIO chip %s has %d GPIOs\n",
2371 chip->label, chip->ngpio); 2373 chip->label, chip->ngpio);
2372 continue; 2374 continue;
@@ -2416,9 +2418,9 @@ struct gpio_desc *__must_check gpiod_get_index(struct device *dev,
2416 const char *con_id, 2418 const char *con_id,
2417 unsigned int idx) 2419 unsigned int idx)
2418{ 2420{
2419 struct gpio_desc *desc; 2421 struct gpio_desc *desc = NULL;
2420 int status; 2422 int status;
2421 unsigned long flags = 0; 2423 enum gpio_lookup_flags flags = 0;
2422 2424
2423 dev_dbg(dev, "GPIO lookup for consumer %s\n", con_id); 2425 dev_dbg(dev, "GPIO lookup for consumer %s\n", con_id);
2424 2426
@@ -2429,13 +2431,23 @@ struct gpio_desc *__must_check gpiod_get_index(struct device *dev,
2429 } else if (IS_ENABLED(CONFIG_ACPI) && dev && ACPI_HANDLE(dev)) { 2431 } else if (IS_ENABLED(CONFIG_ACPI) && dev && ACPI_HANDLE(dev)) {
2430 dev_dbg(dev, "using ACPI for GPIO lookup\n"); 2432 dev_dbg(dev, "using ACPI for GPIO lookup\n");
2431 desc = acpi_find_gpio(dev, con_id, idx, &flags); 2433 desc = acpi_find_gpio(dev, con_id, idx, &flags);
2432 } else { 2434 }
2435
2436 /*
2437 * Either we are not using DT or ACPI, or their lookup did not return
2438 * a result. In that case, use platform lookup as a fallback.
2439 */
2440 if (!desc || IS_ERR(desc)) {
2441 struct gpio_desc *pdesc;
2433 dev_dbg(dev, "using lookup tables for GPIO lookup"); 2442 dev_dbg(dev, "using lookup tables for GPIO lookup");
2434 desc = gpiod_find(dev, con_id, idx, &flags); 2443 pdesc = gpiod_find(dev, con_id, idx, &flags);
2444 /* If used as fallback, do not replace the previous error */
2445 if (!IS_ERR(pdesc) || !desc)
2446 desc = pdesc;
2435 } 2447 }
2436 2448
2437 if (IS_ERR(desc)) { 2449 if (IS_ERR(desc)) {
2438 dev_warn(dev, "lookup for GPIO %s failed\n", con_id); 2450 dev_dbg(dev, "lookup for GPIO %s failed\n", con_id);
2439 return desc; 2451 return desc;
2440 } 2452 }
2441 2453
@@ -2444,8 +2456,12 @@ struct gpio_desc *__must_check gpiod_get_index(struct device *dev,
2444 if (status < 0) 2456 if (status < 0)
2445 return ERR_PTR(status); 2457 return ERR_PTR(status);
2446 2458
2447 if (flags & GPIOF_ACTIVE_LOW) 2459 if (flags & GPIO_ACTIVE_LOW)
2448 set_bit(FLAG_ACTIVE_LOW, &desc->flags); 2460 set_bit(FLAG_ACTIVE_LOW, &desc->flags);
2461 if (flags & GPIO_OPEN_DRAIN)
2462 set_bit(FLAG_OPEN_DRAIN, &desc->flags);
2463 if (flags & GPIO_OPEN_SOURCE)
2464 set_bit(FLAG_OPEN_SOURCE, &desc->flags);
2449 2465
2450 return desc; 2466 return desc;
2451} 2467}
diff --git a/drivers/gpu/drm/drm_sysfs.c b/drivers/gpu/drm/drm_sysfs.c
index bd2bca395792..c22c3097c3e8 100644
--- a/drivers/gpu/drm/drm_sysfs.c
+++ b/drivers/gpu/drm/drm_sysfs.c
@@ -516,7 +516,7 @@ int drm_sysfs_device_add(struct drm_minor *minor)
516 minor_str = "card%d"; 516 minor_str = "card%d";
517 517
518 minor->kdev = kzalloc(sizeof(*minor->kdev), GFP_KERNEL); 518 minor->kdev = kzalloc(sizeof(*minor->kdev), GFP_KERNEL);
519 if (!minor->dev) { 519 if (!minor->kdev) {
520 r = -ENOMEM; 520 r = -ENOMEM;
521 goto error; 521 goto error;
522 } 522 }
diff --git a/drivers/gpu/drm/nouveau/nouveau_hwmon.c b/drivers/gpu/drm/nouveau/nouveau_hwmon.c
index 38a4db5bfe21..4aff04fa483c 100644
--- a/drivers/gpu/drm/nouveau/nouveau_hwmon.c
+++ b/drivers/gpu/drm/nouveau/nouveau_hwmon.c
@@ -630,7 +630,6 @@ error:
630 hwmon->hwmon = NULL; 630 hwmon->hwmon = NULL;
631 return ret; 631 return ret;
632#else 632#else
633 hwmon->hwmon = NULL;
634 return 0; 633 return 0;
635#endif 634#endif
636} 635}
diff --git a/drivers/gpu/drm/qxl/qxl_release.c b/drivers/gpu/drm/qxl/qxl_release.c
index 0109a9644cb2..821ab7b9409b 100644
--- a/drivers/gpu/drm/qxl/qxl_release.c
+++ b/drivers/gpu/drm/qxl/qxl_release.c
@@ -92,6 +92,7 @@ qxl_release_free(struct qxl_device *qdev,
92 - DRM_FILE_OFFSET); 92 - DRM_FILE_OFFSET);
93 qxl_fence_remove_release(&bo->fence, release->id); 93 qxl_fence_remove_release(&bo->fence, release->id);
94 qxl_bo_unref(&bo); 94 qxl_bo_unref(&bo);
95 kfree(entry);
95 } 96 }
96 spin_lock(&qdev->release_idr_lock); 97 spin_lock(&qdev->release_idr_lock);
97 idr_remove(&qdev->release_idr, release->id); 98 idr_remove(&qdev->release_idr, release->id);
diff --git a/drivers/gpu/drm/tegra/Kconfig b/drivers/gpu/drm/tegra/Kconfig
index 8961ba6a34b8..8db9b3bce001 100644
--- a/drivers/gpu/drm/tegra/Kconfig
+++ b/drivers/gpu/drm/tegra/Kconfig
@@ -2,6 +2,7 @@ config DRM_TEGRA
2 bool "NVIDIA Tegra DRM" 2 bool "NVIDIA Tegra DRM"
3 depends on ARCH_TEGRA || ARCH_MULTIPLATFORM 3 depends on ARCH_TEGRA || ARCH_MULTIPLATFORM
4 depends on DRM 4 depends on DRM
5 depends on RESET_CONTROLLER
5 select TEGRA_HOST1X 6 select TEGRA_HOST1X
6 select DRM_KMS_HELPER 7 select DRM_KMS_HELPER
7 select DRM_KMS_FB_HELPER 8 select DRM_KMS_FB_HELPER
diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c
index ae1cb31ead7e..cd7f1e499616 100644
--- a/drivers/gpu/drm/tegra/dc.c
+++ b/drivers/gpu/drm/tegra/dc.c
@@ -8,8 +8,8 @@
8 */ 8 */
9 9
10#include <linux/clk.h> 10#include <linux/clk.h>
11#include <linux/clk/tegra.h>
12#include <linux/debugfs.h> 11#include <linux/debugfs.h>
12#include <linux/reset.h>
13 13
14#include "dc.h" 14#include "dc.h"
15#include "drm.h" 15#include "drm.h"
@@ -712,7 +712,7 @@ static void tegra_crtc_prepare(struct drm_crtc *crtc)
712 unsigned long value; 712 unsigned long value;
713 713
714 /* hardware initialization */ 714 /* hardware initialization */
715 tegra_periph_reset_deassert(dc->clk); 715 reset_control_deassert(dc->rst);
716 usleep_range(10000, 20000); 716 usleep_range(10000, 20000);
717 717
718 if (dc->pipe) 718 if (dc->pipe)
@@ -1187,6 +1187,12 @@ static int tegra_dc_probe(struct platform_device *pdev)
1187 return PTR_ERR(dc->clk); 1187 return PTR_ERR(dc->clk);
1188 } 1188 }
1189 1189
1190 dc->rst = devm_reset_control_get(&pdev->dev, "dc");
1191 if (IS_ERR(dc->rst)) {
1192 dev_err(&pdev->dev, "failed to get reset\n");
1193 return PTR_ERR(dc->rst);
1194 }
1195
1190 err = clk_prepare_enable(dc->clk); 1196 err = clk_prepare_enable(dc->clk);
1191 if (err < 0) 1197 if (err < 0)
1192 return err; 1198 return err;
diff --git a/drivers/gpu/drm/tegra/drm.h b/drivers/gpu/drm/tegra/drm.h
index fdfe259ed7f8..f717c18b28c2 100644
--- a/drivers/gpu/drm/tegra/drm.h
+++ b/drivers/gpu/drm/tegra/drm.h
@@ -19,6 +19,8 @@
19#include <drm/drm_fb_helper.h> 19#include <drm/drm_fb_helper.h>
20#include <drm/drm_fixed.h> 20#include <drm/drm_fixed.h>
21 21
22struct reset_control;
23
22struct tegra_fb { 24struct tegra_fb {
23 struct drm_framebuffer base; 25 struct drm_framebuffer base;
24 struct tegra_bo **planes; 26 struct tegra_bo **planes;
@@ -93,6 +95,7 @@ struct tegra_dc {
93 int pipe; 95 int pipe;
94 96
95 struct clk *clk; 97 struct clk *clk;
98 struct reset_control *rst;
96 void __iomem *regs; 99 void __iomem *regs;
97 int irq; 100 int irq;
98 101
diff --git a/drivers/gpu/drm/tegra/gr3d.c b/drivers/gpu/drm/tegra/gr3d.c
index 4cec8f526af7..0cbb24b1ae04 100644
--- a/drivers/gpu/drm/tegra/gr3d.c
+++ b/drivers/gpu/drm/tegra/gr3d.c
@@ -11,6 +11,7 @@
11#include <linux/host1x.h> 11#include <linux/host1x.h>
12#include <linux/module.h> 12#include <linux/module.h>
13#include <linux/platform_device.h> 13#include <linux/platform_device.h>
14#include <linux/reset.h>
14#include <linux/tegra-powergate.h> 15#include <linux/tegra-powergate.h>
15 16
16#include "drm.h" 17#include "drm.h"
@@ -22,6 +23,8 @@ struct gr3d {
22 struct host1x_channel *channel; 23 struct host1x_channel *channel;
23 struct clk *clk_secondary; 24 struct clk *clk_secondary;
24 struct clk *clk; 25 struct clk *clk;
26 struct reset_control *rst_secondary;
27 struct reset_control *rst;
25 28
26 DECLARE_BITMAP(addr_regs, GR3D_NUM_REGS); 29 DECLARE_BITMAP(addr_regs, GR3D_NUM_REGS);
27}; 30};
@@ -255,15 +258,29 @@ static int gr3d_probe(struct platform_device *pdev)
255 return PTR_ERR(gr3d->clk); 258 return PTR_ERR(gr3d->clk);
256 } 259 }
257 260
261 gr3d->rst = devm_reset_control_get(&pdev->dev, "3d");
262 if (IS_ERR(gr3d->rst)) {
263 dev_err(&pdev->dev, "cannot get reset\n");
264 return PTR_ERR(gr3d->rst);
265 }
266
258 if (of_device_is_compatible(np, "nvidia,tegra30-gr3d")) { 267 if (of_device_is_compatible(np, "nvidia,tegra30-gr3d")) {
259 gr3d->clk_secondary = devm_clk_get(&pdev->dev, "3d2"); 268 gr3d->clk_secondary = devm_clk_get(&pdev->dev, "3d2");
260 if (IS_ERR(gr3d->clk)) { 269 if (IS_ERR(gr3d->clk)) {
261 dev_err(&pdev->dev, "cannot get secondary clock\n"); 270 dev_err(&pdev->dev, "cannot get secondary clock\n");
262 return PTR_ERR(gr3d->clk); 271 return PTR_ERR(gr3d->clk);
263 } 272 }
273
274 gr3d->rst_secondary = devm_reset_control_get(&pdev->dev,
275 "3d2");
276 if (IS_ERR(gr3d->rst_secondary)) {
277 dev_err(&pdev->dev, "cannot get secondary reset\n");
278 return PTR_ERR(gr3d->rst_secondary);
279 }
264 } 280 }
265 281
266 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_3D, gr3d->clk); 282 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_3D, gr3d->clk,
283 gr3d->rst);
267 if (err < 0) { 284 if (err < 0) {
268 dev_err(&pdev->dev, "failed to power up 3D unit\n"); 285 dev_err(&pdev->dev, "failed to power up 3D unit\n");
269 return err; 286 return err;
@@ -271,7 +288,8 @@ static int gr3d_probe(struct platform_device *pdev)
271 288
272 if (gr3d->clk_secondary) { 289 if (gr3d->clk_secondary) {
273 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_3D1, 290 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_3D1,
274 gr3d->clk_secondary); 291 gr3d->clk_secondary,
292 gr3d->rst_secondary);
275 if (err < 0) { 293 if (err < 0) {
276 dev_err(&pdev->dev, 294 dev_err(&pdev->dev,
277 "failed to power up secondary 3D unit\n"); 295 "failed to power up secondary 3D unit\n");
diff --git a/drivers/gpu/drm/tegra/hdmi.c b/drivers/gpu/drm/tegra/hdmi.c
index 0cd9bc2056e8..7f6253ea5cb5 100644
--- a/drivers/gpu/drm/tegra/hdmi.c
+++ b/drivers/gpu/drm/tegra/hdmi.c
@@ -8,10 +8,10 @@
8 */ 8 */
9 9
10#include <linux/clk.h> 10#include <linux/clk.h>
11#include <linux/clk/tegra.h>
12#include <linux/debugfs.h> 11#include <linux/debugfs.h>
13#include <linux/hdmi.h> 12#include <linux/hdmi.h>
14#include <linux/regulator/consumer.h> 13#include <linux/regulator/consumer.h>
14#include <linux/reset.h>
15 15
16#include "hdmi.h" 16#include "hdmi.h"
17#include "drm.h" 17#include "drm.h"
@@ -49,6 +49,7 @@ struct tegra_hdmi {
49 49
50 struct clk *clk_parent; 50 struct clk *clk_parent;
51 struct clk *clk; 51 struct clk *clk;
52 struct reset_control *rst;
52 53
53 const struct tegra_hdmi_config *config; 54 const struct tegra_hdmi_config *config;
54 55
@@ -731,9 +732,9 @@ static int tegra_output_hdmi_enable(struct tegra_output *output)
731 return err; 732 return err;
732 } 733 }
733 734
734 tegra_periph_reset_assert(hdmi->clk); 735 reset_control_assert(hdmi->rst);
735 usleep_range(1000, 2000); 736 usleep_range(1000, 2000);
736 tegra_periph_reset_deassert(hdmi->clk); 737 reset_control_deassert(hdmi->rst);
737 738
738 tegra_dc_writel(dc, VSYNC_H_POSITION(1), 739 tegra_dc_writel(dc, VSYNC_H_POSITION(1),
739 DC_DISP_DISP_TIMING_OPTIONS); 740 DC_DISP_DISP_TIMING_OPTIONS);
@@ -912,7 +913,7 @@ static int tegra_output_hdmi_disable(struct tegra_output *output)
912{ 913{
913 struct tegra_hdmi *hdmi = to_hdmi(output); 914 struct tegra_hdmi *hdmi = to_hdmi(output);
914 915
915 tegra_periph_reset_assert(hdmi->clk); 916 reset_control_assert(hdmi->rst);
916 clk_disable(hdmi->clk); 917 clk_disable(hdmi->clk);
917 regulator_disable(hdmi->pll); 918 regulator_disable(hdmi->pll);
918 919
@@ -1338,6 +1339,12 @@ static int tegra_hdmi_probe(struct platform_device *pdev)
1338 return PTR_ERR(hdmi->clk); 1339 return PTR_ERR(hdmi->clk);
1339 } 1340 }
1340 1341
1342 hdmi->rst = devm_reset_control_get(&pdev->dev, "hdmi");
1343 if (IS_ERR(hdmi->rst)) {
1344 dev_err(&pdev->dev, "failed to get reset\n");
1345 return PTR_ERR(hdmi->rst);
1346 }
1347
1341 err = clk_prepare(hdmi->clk); 1348 err = clk_prepare(hdmi->clk);
1342 if (err < 0) 1349 if (err < 0)
1343 return err; 1350 return err;
diff --git a/drivers/hid/Kconfig b/drivers/hid/Kconfig
index 329fbb9b5976..34e2d39d4ce8 100644
--- a/drivers/hid/Kconfig
+++ b/drivers/hid/Kconfig
@@ -460,6 +460,7 @@ config HID_MULTITOUCH
460 - Stantum multitouch panels 460 - Stantum multitouch panels
461 - Touch International Panels 461 - Touch International Panels
462 - Unitec Panels 462 - Unitec Panels
463 - Wistron optical touch panels
463 - XAT optical touch panels 464 - XAT optical touch panels
464 - Xiroku optical touch panels 465 - Xiroku optical touch panels
465 - Zytronic touch panels 466 - Zytronic touch panels
diff --git a/drivers/hid/hid-appleir.c b/drivers/hid/hid-appleir.c
index a42e6a394c5e..0e6a42d37eb6 100644
--- a/drivers/hid/hid-appleir.c
+++ b/drivers/hid/hid-appleir.c
@@ -297,6 +297,9 @@ static int appleir_probe(struct hid_device *hid, const struct hid_device_id *id)
297 297
298 appleir->hid = hid; 298 appleir->hid = hid;
299 299
300 /* force input as some remotes bypass the input registration */
301 hid->quirks |= HID_QUIRK_HIDINPUT_FORCE;
302
300 spin_lock_init(&appleir->lock); 303 spin_lock_init(&appleir->lock);
301 setup_timer(&appleir->key_up_timer, 304 setup_timer(&appleir->key_up_timer,
302 key_up_tick, (unsigned long) appleir); 305 key_up_tick, (unsigned long) appleir);
diff --git a/drivers/hid/hid-core.c b/drivers/hid/hid-core.c
index 8c10f2742233..253fe23ef7fe 100644
--- a/drivers/hid/hid-core.c
+++ b/drivers/hid/hid-core.c
@@ -1723,6 +1723,7 @@ static const struct hid_device_id hid_have_special_driver[] = {
1723 { HID_USB_DEVICE(USB_VENDOR_ID_KENSINGTON, USB_DEVICE_ID_KS_SLIMBLADE) }, 1723 { HID_USB_DEVICE(USB_VENDOR_ID_KENSINGTON, USB_DEVICE_ID_KS_SLIMBLADE) },
1724 { HID_USB_DEVICE(USB_VENDOR_ID_KEYTOUCH, USB_DEVICE_ID_KEYTOUCH_IEC) }, 1724 { HID_USB_DEVICE(USB_VENDOR_ID_KEYTOUCH, USB_DEVICE_ID_KEYTOUCH_IEC) },
1725 { HID_USB_DEVICE(USB_VENDOR_ID_KYE, USB_DEVICE_ID_GENIUS_GILA_GAMING_MOUSE) }, 1725 { HID_USB_DEVICE(USB_VENDOR_ID_KYE, USB_DEVICE_ID_GENIUS_GILA_GAMING_MOUSE) },
1726 { HID_USB_DEVICE(USB_VENDOR_ID_KYE, USB_DEVICE_ID_GENIUS_MANTICORE) },
1726 { HID_USB_DEVICE(USB_VENDOR_ID_KYE, USB_DEVICE_ID_GENIUS_GX_IMPERATOR) }, 1727 { HID_USB_DEVICE(USB_VENDOR_ID_KYE, USB_DEVICE_ID_GENIUS_GX_IMPERATOR) },
1727 { HID_USB_DEVICE(USB_VENDOR_ID_KYE, USB_DEVICE_ID_KYE_ERGO_525V) }, 1728 { HID_USB_DEVICE(USB_VENDOR_ID_KYE, USB_DEVICE_ID_KYE_ERGO_525V) },
1728 { HID_USB_DEVICE(USB_VENDOR_ID_KYE, USB_DEVICE_ID_KYE_EASYPEN_I405X) }, 1729 { HID_USB_DEVICE(USB_VENDOR_ID_KYE, USB_DEVICE_ID_KYE_EASYPEN_I405X) },
@@ -1879,7 +1880,6 @@ static const struct hid_device_id hid_have_special_driver[] = {
1879 1880
1880 { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_PRESENTER_8K_BT) }, 1881 { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_PRESENTER_8K_BT) },
1881 { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_NINTENDO, USB_DEVICE_ID_NINTENDO_WIIMOTE) }, 1882 { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_NINTENDO, USB_DEVICE_ID_NINTENDO_WIIMOTE) },
1882 { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_NINTENDO2, USB_DEVICE_ID_NINTENDO_WIIMOTE) },
1883 { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_NINTENDO, USB_DEVICE_ID_NINTENDO_WIIMOTE2) }, 1883 { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_NINTENDO, USB_DEVICE_ID_NINTENDO_WIIMOTE2) },
1884 { } 1884 { }
1885}; 1885};
diff --git a/drivers/hid/hid-ids.h b/drivers/hid/hid-ids.h
index 76559629568c..f9304cb37154 100644
--- a/drivers/hid/hid-ids.h
+++ b/drivers/hid/hid-ids.h
@@ -489,6 +489,7 @@
489#define USB_VENDOR_ID_KYE 0x0458 489#define USB_VENDOR_ID_KYE 0x0458
490#define USB_DEVICE_ID_KYE_ERGO_525V 0x0087 490#define USB_DEVICE_ID_KYE_ERGO_525V 0x0087
491#define USB_DEVICE_ID_GENIUS_GILA_GAMING_MOUSE 0x0138 491#define USB_DEVICE_ID_GENIUS_GILA_GAMING_MOUSE 0x0138
492#define USB_DEVICE_ID_GENIUS_MANTICORE 0x0153
492#define USB_DEVICE_ID_GENIUS_GX_IMPERATOR 0x4018 493#define USB_DEVICE_ID_GENIUS_GX_IMPERATOR 0x4018
493#define USB_DEVICE_ID_KYE_GPEN_560 0x5003 494#define USB_DEVICE_ID_KYE_GPEN_560 0x5003
494#define USB_DEVICE_ID_KYE_EASYPEN_I405X 0x5010 495#define USB_DEVICE_ID_KYE_EASYPEN_I405X 0x5010
@@ -640,7 +641,6 @@
640#define USB_DEVICE_ID_NEXTWINDOW_TOUCHSCREEN 0x0003 641#define USB_DEVICE_ID_NEXTWINDOW_TOUCHSCREEN 0x0003
641 642
642#define USB_VENDOR_ID_NINTENDO 0x057e 643#define USB_VENDOR_ID_NINTENDO 0x057e
643#define USB_VENDOR_ID_NINTENDO2 0x054c
644#define USB_DEVICE_ID_NINTENDO_WIIMOTE 0x0306 644#define USB_DEVICE_ID_NINTENDO_WIIMOTE 0x0306
645#define USB_DEVICE_ID_NINTENDO_WIIMOTE2 0x0330 645#define USB_DEVICE_ID_NINTENDO_WIIMOTE2 0x0330
646 646
@@ -902,6 +902,9 @@
902#define USB_DEVICE_ID_SUPER_DUAL_BOX_PRO 0x8802 902#define USB_DEVICE_ID_SUPER_DUAL_BOX_PRO 0x8802
903#define USB_DEVICE_ID_SUPER_JOY_BOX_5_PRO 0x8804 903#define USB_DEVICE_ID_SUPER_JOY_BOX_5_PRO 0x8804
904 904
905#define USB_VENDOR_ID_WISTRON 0x0fb8
906#define USB_DEVICE_ID_WISTRON_OPTICAL_TOUCH 0x1109
907
905#define USB_VENDOR_ID_X_TENSIONS 0x1ae7 908#define USB_VENDOR_ID_X_TENSIONS 0x1ae7
906#define USB_DEVICE_ID_SPEEDLINK_VAD_CEZANNE 0x9001 909#define USB_DEVICE_ID_SPEEDLINK_VAD_CEZANNE 0x9001
907 910
diff --git a/drivers/hid/hid-kye.c b/drivers/hid/hid-kye.c
index 73845120295e..ecb5ca669e97 100644
--- a/drivers/hid/hid-kye.c
+++ b/drivers/hid/hid-kye.c
@@ -341,6 +341,9 @@ static __u8 *kye_report_fixup(struct hid_device *hdev, __u8 *rdesc,
341 case USB_DEVICE_ID_GENIUS_GX_IMPERATOR: 341 case USB_DEVICE_ID_GENIUS_GX_IMPERATOR:
342 rdesc = kye_consumer_control_fixup(hdev, rdesc, rsize, 83, 342 rdesc = kye_consumer_control_fixup(hdev, rdesc, rsize, 83,
343 "Genius Gx Imperator Keyboard"); 343 "Genius Gx Imperator Keyboard");
344 case USB_DEVICE_ID_GENIUS_MANTICORE:
345 rdesc = kye_consumer_control_fixup(hdev, rdesc, rsize, 104,
346 "Genius Manticore Keyboard");
344 break; 347 break;
345 } 348 }
346 return rdesc; 349 return rdesc;
@@ -418,6 +421,14 @@ static int kye_probe(struct hid_device *hdev, const struct hid_device_id *id)
418 goto enabling_err; 421 goto enabling_err;
419 } 422 }
420 break; 423 break;
424 case USB_DEVICE_ID_GENIUS_MANTICORE:
425 /*
426 * The manticore keyboard needs to have all the interfaces
427 * opened at least once to be fully functional.
428 */
429 if (hid_hw_open(hdev))
430 hid_hw_close(hdev);
431 break;
421 } 432 }
422 433
423 return 0; 434 return 0;
@@ -439,6 +450,8 @@ static const struct hid_device_id kye_devices[] = {
439 USB_DEVICE_ID_GENIUS_GILA_GAMING_MOUSE) }, 450 USB_DEVICE_ID_GENIUS_GILA_GAMING_MOUSE) },
440 { HID_USB_DEVICE(USB_VENDOR_ID_KYE, 451 { HID_USB_DEVICE(USB_VENDOR_ID_KYE,
441 USB_DEVICE_ID_GENIUS_GX_IMPERATOR) }, 452 USB_DEVICE_ID_GENIUS_GX_IMPERATOR) },
453 { HID_USB_DEVICE(USB_VENDOR_ID_KYE,
454 USB_DEVICE_ID_GENIUS_MANTICORE) },
442 { } 455 { }
443}; 456};
444MODULE_DEVICE_TABLE(hid, kye_devices); 457MODULE_DEVICE_TABLE(hid, kye_devices);
diff --git a/drivers/hid/hid-multitouch.c b/drivers/hid/hid-multitouch.c
index a2cedb8ae1c0..d83b1e8b505b 100644
--- a/drivers/hid/hid-multitouch.c
+++ b/drivers/hid/hid-multitouch.c
@@ -1335,6 +1335,12 @@ static const struct hid_device_id mt_devices[] = {
1335 { .driver_data = MT_CLS_NSMU, 1335 { .driver_data = MT_CLS_NSMU,
1336 MT_USB_DEVICE(USB_VENDOR_ID_UNITEC, 1336 MT_USB_DEVICE(USB_VENDOR_ID_UNITEC,
1337 USB_DEVICE_ID_UNITEC_USB_TOUCH_0A19) }, 1337 USB_DEVICE_ID_UNITEC_USB_TOUCH_0A19) },
1338
1339 /* Wistron panels */
1340 { .driver_data = MT_CLS_NSMU,
1341 MT_USB_DEVICE(USB_VENDOR_ID_WISTRON,
1342 USB_DEVICE_ID_WISTRON_OPTICAL_TOUCH) },
1343
1338 /* XAT */ 1344 /* XAT */
1339 { .driver_data = MT_CLS_NSMU, 1345 { .driver_data = MT_CLS_NSMU,
1340 MT_USB_DEVICE(USB_VENDOR_ID_XAT, 1346 MT_USB_DEVICE(USB_VENDOR_ID_XAT,
diff --git a/drivers/hid/hid-sony.c b/drivers/hid/hid-sony.c
index da551d113762..098af2f84b8c 100644
--- a/drivers/hid/hid-sony.c
+++ b/drivers/hid/hid-sony.c
@@ -225,6 +225,13 @@ static const unsigned int buzz_keymap[] = {
225struct sony_sc { 225struct sony_sc {
226 unsigned long quirks; 226 unsigned long quirks;
227 227
228#ifdef CONFIG_SONY_FF
229 struct work_struct rumble_worker;
230 struct hid_device *hdev;
231 __u8 left;
232 __u8 right;
233#endif
234
228 void *extra; 235 void *extra;
229}; 236};
230 237
@@ -615,9 +622,9 @@ static void buzz_remove(struct hid_device *hdev)
615} 622}
616 623
617#ifdef CONFIG_SONY_FF 624#ifdef CONFIG_SONY_FF
618static int sony_play_effect(struct input_dev *dev, void *data, 625static void sony_rumble_worker(struct work_struct *work)
619 struct ff_effect *effect)
620{ 626{
627 struct sony_sc *sc = container_of(work, struct sony_sc, rumble_worker);
621 unsigned char buf[] = { 628 unsigned char buf[] = {
622 0x01, 629 0x01,
623 0x00, 0xff, 0x00, 0xff, 0x00, 630 0x00, 0xff, 0x00, 0xff, 0x00,
@@ -628,21 +635,28 @@ static int sony_play_effect(struct input_dev *dev, void *data,
628 0xff, 0x27, 0x10, 0x00, 0x32, 635 0xff, 0x27, 0x10, 0x00, 0x32,
629 0x00, 0x00, 0x00, 0x00, 0x00 636 0x00, 0x00, 0x00, 0x00, 0x00
630 }; 637 };
631 __u8 left; 638
632 __u8 right; 639 buf[3] = sc->right;
640 buf[5] = sc->left;
641
642 sc->hdev->hid_output_raw_report(sc->hdev, buf, sizeof(buf),
643 HID_OUTPUT_REPORT);
644}
645
646static int sony_play_effect(struct input_dev *dev, void *data,
647 struct ff_effect *effect)
648{
633 struct hid_device *hid = input_get_drvdata(dev); 649 struct hid_device *hid = input_get_drvdata(dev);
650 struct sony_sc *sc = hid_get_drvdata(hid);
634 651
635 if (effect->type != FF_RUMBLE) 652 if (effect->type != FF_RUMBLE)
636 return 0; 653 return 0;
637 654
638 left = effect->u.rumble.strong_magnitude / 256; 655 sc->left = effect->u.rumble.strong_magnitude / 256;
639 right = effect->u.rumble.weak_magnitude ? 1 : 0; 656 sc->right = effect->u.rumble.weak_magnitude ? 1 : 0;
640
641 buf[3] = right;
642 buf[5] = left;
643 657
644 return hid->hid_output_raw_report(hid, buf, sizeof(buf), 658 schedule_work(&sc->rumble_worker);
645 HID_OUTPUT_REPORT); 659 return 0;
646} 660}
647 661
648static int sony_init_ff(struct hid_device *hdev) 662static int sony_init_ff(struct hid_device *hdev)
@@ -650,16 +664,31 @@ static int sony_init_ff(struct hid_device *hdev)
650 struct hid_input *hidinput = list_entry(hdev->inputs.next, 664 struct hid_input *hidinput = list_entry(hdev->inputs.next,
651 struct hid_input, list); 665 struct hid_input, list);
652 struct input_dev *input_dev = hidinput->input; 666 struct input_dev *input_dev = hidinput->input;
667 struct sony_sc *sc = hid_get_drvdata(hdev);
668
669 sc->hdev = hdev;
670 INIT_WORK(&sc->rumble_worker, sony_rumble_worker);
653 671
654 input_set_capability(input_dev, EV_FF, FF_RUMBLE); 672 input_set_capability(input_dev, EV_FF, FF_RUMBLE);
655 return input_ff_create_memless(input_dev, NULL, sony_play_effect); 673 return input_ff_create_memless(input_dev, NULL, sony_play_effect);
656} 674}
657 675
676static void sony_destroy_ff(struct hid_device *hdev)
677{
678 struct sony_sc *sc = hid_get_drvdata(hdev);
679
680 cancel_work_sync(&sc->rumble_worker);
681}
682
658#else 683#else
659static int sony_init_ff(struct hid_device *hdev) 684static int sony_init_ff(struct hid_device *hdev)
660{ 685{
661 return 0; 686 return 0;
662} 687}
688
689static void sony_destroy_ff(struct hid_device *hdev)
690{
691}
663#endif 692#endif
664 693
665static int sony_probe(struct hid_device *hdev, const struct hid_device_id *id) 694static int sony_probe(struct hid_device *hdev, const struct hid_device_id *id)
@@ -728,6 +757,8 @@ static void sony_remove(struct hid_device *hdev)
728 if (sc->quirks & BUZZ_CONTROLLER) 757 if (sc->quirks & BUZZ_CONTROLLER)
729 buzz_remove(hdev); 758 buzz_remove(hdev);
730 759
760 sony_destroy_ff(hdev);
761
731 hid_hw_stop(hdev); 762 hid_hw_stop(hdev);
732} 763}
733 764
diff --git a/drivers/hid/hid-wiimote-core.c b/drivers/hid/hid-wiimote-core.c
index 1446f526ee8b..abb20db2b443 100644
--- a/drivers/hid/hid-wiimote-core.c
+++ b/drivers/hid/hid-wiimote-core.c
@@ -834,8 +834,7 @@ static void wiimote_init_set_type(struct wiimote_data *wdata,
834 goto done; 834 goto done;
835 } 835 }
836 836
837 if (vendor == USB_VENDOR_ID_NINTENDO || 837 if (vendor == USB_VENDOR_ID_NINTENDO) {
838 vendor == USB_VENDOR_ID_NINTENDO2) {
839 if (product == USB_DEVICE_ID_NINTENDO_WIIMOTE) { 838 if (product == USB_DEVICE_ID_NINTENDO_WIIMOTE) {
840 devtype = WIIMOTE_DEV_GEN10; 839 devtype = WIIMOTE_DEV_GEN10;
841 goto done; 840 goto done;
@@ -1856,8 +1855,6 @@ static void wiimote_hid_remove(struct hid_device *hdev)
1856static const struct hid_device_id wiimote_hid_devices[] = { 1855static const struct hid_device_id wiimote_hid_devices[] = {
1857 { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_NINTENDO, 1856 { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_NINTENDO,
1858 USB_DEVICE_ID_NINTENDO_WIIMOTE) }, 1857 USB_DEVICE_ID_NINTENDO_WIIMOTE) },
1859 { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_NINTENDO2,
1860 USB_DEVICE_ID_NINTENDO_WIIMOTE) },
1861 { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_NINTENDO, 1858 { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_NINTENDO,
1862 USB_DEVICE_ID_NINTENDO_WIIMOTE2) }, 1859 USB_DEVICE_ID_NINTENDO_WIIMOTE2) },
1863 { } 1860 { }
diff --git a/drivers/hid/uhid.c b/drivers/hid/uhid.c
index 93b00d76374c..cedc6da93c19 100644
--- a/drivers/hid/uhid.c
+++ b/drivers/hid/uhid.c
@@ -287,7 +287,7 @@ static int uhid_event_from_user(const char __user *buffer, size_t len,
287 */ 287 */
288 struct uhid_create_req_compat *compat; 288 struct uhid_create_req_compat *compat;
289 289
290 compat = kmalloc(sizeof(*compat), GFP_KERNEL); 290 compat = kzalloc(sizeof(*compat), GFP_KERNEL);
291 if (!compat) 291 if (!compat)
292 return -ENOMEM; 292 return -ENOMEM;
293 293
diff --git a/drivers/hwmon/asus_atk0110.c b/drivers/hwmon/asus_atk0110.c
index 1d7ff46812c3..dafc63c6932d 100644
--- a/drivers/hwmon/asus_atk0110.c
+++ b/drivers/hwmon/asus_atk0110.c
@@ -18,7 +18,6 @@
18#include <linux/err.h> 18#include <linux/err.h>
19 19
20#include <acpi/acpi.h> 20#include <acpi/acpi.h>
21#include <acpi/acpixf.h>
22#include <acpi/acpi_drivers.h> 21#include <acpi/acpi_drivers.h>
23#include <acpi/acpi_bus.h> 22#include <acpi/acpi_bus.h>
24 23
diff --git a/drivers/i2c/busses/i2c-bcm-kona.c b/drivers/i2c/busses/i2c-bcm-kona.c
index 036cf03aeb61..18a74a6751a9 100644
--- a/drivers/i2c/busses/i2c-bcm-kona.c
+++ b/drivers/i2c/busses/i2c-bcm-kona.c
@@ -20,7 +20,6 @@
20#include <linux/platform_device.h> 20#include <linux/platform_device.h>
21#include <linux/clk.h> 21#include <linux/clk.h>
22#include <linux/io.h> 22#include <linux/io.h>
23#include <linux/clk.h>
24#include <linux/slab.h> 23#include <linux/slab.h>
25 24
26/* Hardware register offsets and field defintions */ 25/* Hardware register offsets and field defintions */
@@ -891,7 +890,7 @@ static const struct of_device_id bcm_kona_i2c_of_match[] = {
891 {.compatible = "brcm,kona-i2c",}, 890 {.compatible = "brcm,kona-i2c",},
892 {}, 891 {},
893}; 892};
894MODULE_DEVICE_TABLE(of, kona_i2c_of_match); 893MODULE_DEVICE_TABLE(of, bcm_kona_i2c_of_match);
895 894
896static struct platform_driver bcm_kona_i2c_driver = { 895static struct platform_driver bcm_kona_i2c_driver = {
897 .driver = { 896 .driver = {
diff --git a/drivers/i2c/busses/i2c-bcm2835.c b/drivers/i2c/busses/i2c-bcm2835.c
index d7e8600f31fb..77df97b932af 100644
--- a/drivers/i2c/busses/i2c-bcm2835.c
+++ b/drivers/i2c/busses/i2c-bcm2835.c
@@ -299,6 +299,7 @@ static int bcm2835_i2c_probe(struct platform_device *pdev)
299 strlcpy(adap->name, "bcm2835 I2C adapter", sizeof(adap->name)); 299 strlcpy(adap->name, "bcm2835 I2C adapter", sizeof(adap->name));
300 adap->algo = &bcm2835_i2c_algo; 300 adap->algo = &bcm2835_i2c_algo;
301 adap->dev.parent = &pdev->dev; 301 adap->dev.parent = &pdev->dev;
302 adap->dev.of_node = pdev->dev.of_node;
302 303
303 bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C, 0); 304 bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C, 0);
304 305
diff --git a/drivers/i2c/busses/i2c-davinci.c b/drivers/i2c/busses/i2c-davinci.c
index ff05d9fef4a8..af0b5830303d 100644
--- a/drivers/i2c/busses/i2c-davinci.c
+++ b/drivers/i2c/busses/i2c-davinci.c
@@ -125,12 +125,12 @@ static struct davinci_i2c_platform_data davinci_i2c_platform_data_default = {
125static inline void davinci_i2c_write_reg(struct davinci_i2c_dev *i2c_dev, 125static inline void davinci_i2c_write_reg(struct davinci_i2c_dev *i2c_dev,
126 int reg, u16 val) 126 int reg, u16 val)
127{ 127{
128 __raw_writew(val, i2c_dev->base + reg); 128 writew_relaxed(val, i2c_dev->base + reg);
129} 129}
130 130
131static inline u16 davinci_i2c_read_reg(struct davinci_i2c_dev *i2c_dev, int reg) 131static inline u16 davinci_i2c_read_reg(struct davinci_i2c_dev *i2c_dev, int reg)
132{ 132{
133 return __raw_readw(i2c_dev->base + reg); 133 return readw_relaxed(i2c_dev->base + reg);
134} 134}
135 135
136/* Generate a pulse on the i2c clock pin. */ 136/* Generate a pulse on the i2c clock pin. */
diff --git a/drivers/i2c/busses/i2c-diolan-u2c.c b/drivers/i2c/busses/i2c-diolan-u2c.c
index dae3ddfe7619..721f7ebf9a3b 100644
--- a/drivers/i2c/busses/i2c-diolan-u2c.c
+++ b/drivers/i2c/busses/i2c-diolan-u2c.c
@@ -25,8 +25,6 @@
25#define USB_VENDOR_ID_DIOLAN 0x0abf 25#define USB_VENDOR_ID_DIOLAN 0x0abf
26#define USB_DEVICE_ID_DIOLAN_U2C 0x3370 26#define USB_DEVICE_ID_DIOLAN_U2C 0x3370
27 27
28#define DIOLAN_OUT_EP 0x02
29#define DIOLAN_IN_EP 0x84
30 28
31/* commands via USB, must match command ids in the firmware */ 29/* commands via USB, must match command ids in the firmware */
32#define CMD_I2C_READ 0x01 30#define CMD_I2C_READ 0x01
@@ -84,6 +82,7 @@
84struct i2c_diolan_u2c { 82struct i2c_diolan_u2c {
85 u8 obuffer[DIOLAN_OUTBUF_LEN]; /* output buffer */ 83 u8 obuffer[DIOLAN_OUTBUF_LEN]; /* output buffer */
86 u8 ibuffer[DIOLAN_INBUF_LEN]; /* input buffer */ 84 u8 ibuffer[DIOLAN_INBUF_LEN]; /* input buffer */
85 int ep_in, ep_out; /* Endpoints */
87 struct usb_device *usb_dev; /* the usb device for this device */ 86 struct usb_device *usb_dev; /* the usb device for this device */
88 struct usb_interface *interface;/* the interface for this device */ 87 struct usb_interface *interface;/* the interface for this device */
89 struct i2c_adapter adapter; /* i2c related things */ 88 struct i2c_adapter adapter; /* i2c related things */
@@ -109,7 +108,7 @@ static int diolan_usb_transfer(struct i2c_diolan_u2c *dev)
109 return -EINVAL; 108 return -EINVAL;
110 109
111 ret = usb_bulk_msg(dev->usb_dev, 110 ret = usb_bulk_msg(dev->usb_dev,
112 usb_sndbulkpipe(dev->usb_dev, DIOLAN_OUT_EP), 111 usb_sndbulkpipe(dev->usb_dev, dev->ep_out),
113 dev->obuffer, dev->olen, &actual, 112 dev->obuffer, dev->olen, &actual,
114 DIOLAN_USB_TIMEOUT); 113 DIOLAN_USB_TIMEOUT);
115 if (!ret) { 114 if (!ret) {
@@ -118,7 +117,7 @@ static int diolan_usb_transfer(struct i2c_diolan_u2c *dev)
118 117
119 tmpret = usb_bulk_msg(dev->usb_dev, 118 tmpret = usb_bulk_msg(dev->usb_dev,
120 usb_rcvbulkpipe(dev->usb_dev, 119 usb_rcvbulkpipe(dev->usb_dev,
121 DIOLAN_IN_EP), 120 dev->ep_in),
122 dev->ibuffer, 121 dev->ibuffer,
123 sizeof(dev->ibuffer), &actual, 122 sizeof(dev->ibuffer), &actual,
124 DIOLAN_USB_TIMEOUT); 123 DIOLAN_USB_TIMEOUT);
@@ -210,7 +209,7 @@ static void diolan_flush_input(struct i2c_diolan_u2c *dev)
210 int ret; 209 int ret;
211 210
212 ret = usb_bulk_msg(dev->usb_dev, 211 ret = usb_bulk_msg(dev->usb_dev,
213 usb_rcvbulkpipe(dev->usb_dev, DIOLAN_IN_EP), 212 usb_rcvbulkpipe(dev->usb_dev, dev->ep_in),
214 dev->ibuffer, sizeof(dev->ibuffer), &actual, 213 dev->ibuffer, sizeof(dev->ibuffer), &actual,
215 DIOLAN_USB_TIMEOUT); 214 DIOLAN_USB_TIMEOUT);
216 if (ret < 0 || actual == 0) 215 if (ret < 0 || actual == 0)
@@ -445,9 +444,14 @@ static void diolan_u2c_free(struct i2c_diolan_u2c *dev)
445static int diolan_u2c_probe(struct usb_interface *interface, 444static int diolan_u2c_probe(struct usb_interface *interface,
446 const struct usb_device_id *id) 445 const struct usb_device_id *id)
447{ 446{
447 struct usb_host_interface *hostif = interface->cur_altsetting;
448 struct i2c_diolan_u2c *dev; 448 struct i2c_diolan_u2c *dev;
449 int ret; 449 int ret;
450 450
451 if (hostif->desc.bInterfaceNumber != 0
452 || hostif->desc.bNumEndpoints < 2)
453 return -ENODEV;
454
451 /* allocate memory for our device state and initialize it */ 455 /* allocate memory for our device state and initialize it */
452 dev = kzalloc(sizeof(*dev), GFP_KERNEL); 456 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
453 if (dev == NULL) { 457 if (dev == NULL) {
@@ -455,6 +459,8 @@ static int diolan_u2c_probe(struct usb_interface *interface,
455 ret = -ENOMEM; 459 ret = -ENOMEM;
456 goto error; 460 goto error;
457 } 461 }
462 dev->ep_out = hostif->endpoint[0].desc.bEndpointAddress;
463 dev->ep_in = hostif->endpoint[1].desc.bEndpointAddress;
458 464
459 dev->usb_dev = usb_get_dev(interface_to_usbdev(interface)); 465 dev->usb_dev = usb_get_dev(interface_to_usbdev(interface));
460 dev->interface = interface; 466 dev->interface = interface;
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index a6a891d7970d..90dcc2eaac5f 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -266,13 +266,13 @@ static const u8 reg_map_ip_v2[] = {
266static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev, 266static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
267 int reg, u16 val) 267 int reg, u16 val)
268{ 268{
269 __raw_writew(val, i2c_dev->base + 269 writew_relaxed(val, i2c_dev->base +
270 (i2c_dev->regs[reg] << i2c_dev->reg_shift)); 270 (i2c_dev->regs[reg] << i2c_dev->reg_shift));
271} 271}
272 272
273static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg) 273static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
274{ 274{
275 return __raw_readw(i2c_dev->base + 275 return readw_relaxed(i2c_dev->base +
276 (i2c_dev->regs[reg] << i2c_dev->reg_shift)); 276 (i2c_dev->regs[reg] << i2c_dev->reg_shift));
277} 277}
278 278
@@ -1037,6 +1037,20 @@ static const struct i2c_algorithm omap_i2c_algo = {
1037}; 1037};
1038 1038
1039#ifdef CONFIG_OF 1039#ifdef CONFIG_OF
1040static struct omap_i2c_bus_platform_data omap2420_pdata = {
1041 .rev = OMAP_I2C_IP_VERSION_1,
1042 .flags = OMAP_I2C_FLAG_NO_FIFO |
1043 OMAP_I2C_FLAG_SIMPLE_CLOCK |
1044 OMAP_I2C_FLAG_16BIT_DATA_REG |
1045 OMAP_I2C_FLAG_BUS_SHIFT_2,
1046};
1047
1048static struct omap_i2c_bus_platform_data omap2430_pdata = {
1049 .rev = OMAP_I2C_IP_VERSION_1,
1050 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2 |
1051 OMAP_I2C_FLAG_FORCE_19200_INT_CLK,
1052};
1053
1040static struct omap_i2c_bus_platform_data omap3_pdata = { 1054static struct omap_i2c_bus_platform_data omap3_pdata = {
1041 .rev = OMAP_I2C_IP_VERSION_1, 1055 .rev = OMAP_I2C_IP_VERSION_1,
1042 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2, 1056 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
@@ -1055,6 +1069,14 @@ static const struct of_device_id omap_i2c_of_match[] = {
1055 .compatible = "ti,omap3-i2c", 1069 .compatible = "ti,omap3-i2c",
1056 .data = &omap3_pdata, 1070 .data = &omap3_pdata,
1057 }, 1071 },
1072 {
1073 .compatible = "ti,omap2430-i2c",
1074 .data = &omap2430_pdata,
1075 },
1076 {
1077 .compatible = "ti,omap2420-i2c",
1078 .data = &omap2420_pdata,
1079 },
1058 { }, 1080 { },
1059}; 1081};
1060MODULE_DEVICE_TABLE(of, omap_i2c_of_match); 1082MODULE_DEVICE_TABLE(of, omap_i2c_of_match);
@@ -1140,9 +1162,9 @@ omap_i2c_probe(struct platform_device *pdev)
1140 * Read the Rev hi bit-[15:14] ie scheme this is 1 indicates ver2. 1162 * Read the Rev hi bit-[15:14] ie scheme this is 1 indicates ver2.
1141 * On omap1/3/2 Offset 4 is IE Reg the bit [15:14] is 0 at reset. 1163 * On omap1/3/2 Offset 4 is IE Reg the bit [15:14] is 0 at reset.
1142 * Also since the omap_i2c_read_reg uses reg_map_ip_* a 1164 * Also since the omap_i2c_read_reg uses reg_map_ip_* a
1143 * raw_readw is done. 1165 * readw_relaxed is done.
1144 */ 1166 */
1145 rev = __raw_readw(dev->base + 0x04); 1167 rev = readw_relaxed(dev->base + 0x04);
1146 1168
1147 dev->scheme = OMAP_I2C_SCHEME(rev); 1169 dev->scheme = OMAP_I2C_SCHEME(rev);
1148 switch (dev->scheme) { 1170 switch (dev->scheme) {
diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
index e661edee4d0c..9704537aee3c 100644
--- a/drivers/i2c/busses/i2c-tegra.c
+++ b/drivers/i2c/busses/i2c-tegra.c
@@ -27,7 +27,7 @@
27#include <linux/slab.h> 27#include <linux/slab.h>
28#include <linux/of_device.h> 28#include <linux/of_device.h>
29#include <linux/module.h> 29#include <linux/module.h>
30#include <linux/clk/tegra.h> 30#include <linux/reset.h>
31 31
32#include <asm/unaligned.h> 32#include <asm/unaligned.h>
33 33
@@ -160,6 +160,7 @@ struct tegra_i2c_dev {
160 struct i2c_adapter adapter; 160 struct i2c_adapter adapter;
161 struct clk *div_clk; 161 struct clk *div_clk;
162 struct clk *fast_clk; 162 struct clk *fast_clk;
163 struct reset_control *rst;
163 void __iomem *base; 164 void __iomem *base;
164 int cont_id; 165 int cont_id;
165 int irq; 166 int irq;
@@ -415,9 +416,9 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
415 return err; 416 return err;
416 } 417 }
417 418
418 tegra_periph_reset_assert(i2c_dev->div_clk); 419 reset_control_assert(i2c_dev->rst);
419 udelay(2); 420 udelay(2);
420 tegra_periph_reset_deassert(i2c_dev->div_clk); 421 reset_control_deassert(i2c_dev->rst);
421 422
422 if (i2c_dev->is_dvc) 423 if (i2c_dev->is_dvc)
423 tegra_dvc_init(i2c_dev); 424 tegra_dvc_init(i2c_dev);
@@ -743,6 +744,12 @@ static int tegra_i2c_probe(struct platform_device *pdev)
743 i2c_dev->cont_id = pdev->id; 744 i2c_dev->cont_id = pdev->id;
744 i2c_dev->dev = &pdev->dev; 745 i2c_dev->dev = &pdev->dev;
745 746
747 i2c_dev->rst = devm_reset_control_get(&pdev->dev, "i2c");
748 if (IS_ERR(i2c_dev->rst)) {
749 dev_err(&pdev->dev, "missing controller reset");
750 return PTR_ERR(i2c_dev->rst);
751 }
752
746 ret = of_property_read_u32(i2c_dev->dev->of_node, "clock-frequency", 753 ret = of_property_read_u32(i2c_dev->dev->of_node, "clock-frequency",
747 &i2c_dev->bus_clk_rate); 754 &i2c_dev->bus_clk_rate);
748 if (ret) 755 if (ret)
diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c
index cbd4e9abc47e..92d1206482a6 100644
--- a/drivers/idle/intel_idle.c
+++ b/drivers/idle/intel_idle.c
@@ -329,7 +329,7 @@ static struct cpuidle_state atom_cstates[] __initdata = {
329 { 329 {
330 .enter = NULL } 330 .enter = NULL }
331}; 331};
332static struct cpuidle_state avn_cstates[CPUIDLE_STATE_MAX] = { 332static struct cpuidle_state avn_cstates[] __initdata = {
333 { 333 {
334 .name = "C1-AVN", 334 .name = "C1-AVN",
335 .desc = "MWAIT 0x00", 335 .desc = "MWAIT 0x00",
@@ -340,7 +340,7 @@ static struct cpuidle_state avn_cstates[CPUIDLE_STATE_MAX] = {
340 { 340 {
341 .name = "C6-AVN", 341 .name = "C6-AVN",
342 .desc = "MWAIT 0x51", 342 .desc = "MWAIT 0x51",
343 .flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 343 .flags = MWAIT2flg(0x51) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
344 .exit_latency = 15, 344 .exit_latency = 15,
345 .target_residency = 45, 345 .target_residency = 45,
346 .enter = &intel_idle }, 346 .enter = &intel_idle },
diff --git a/drivers/iio/accel/hid-sensor-accel-3d.c b/drivers/iio/accel/hid-sensor-accel-3d.c
index dcda17395c4e..1cae4e920c9b 100644
--- a/drivers/iio/accel/hid-sensor-accel-3d.c
+++ b/drivers/iio/accel/hid-sensor-accel-3d.c
@@ -350,7 +350,7 @@ static int hid_accel_3d_probe(struct platform_device *pdev)
350error_iio_unreg: 350error_iio_unreg:
351 iio_device_unregister(indio_dev); 351 iio_device_unregister(indio_dev);
352error_remove_trigger: 352error_remove_trigger:
353 hid_sensor_remove_trigger(indio_dev); 353 hid_sensor_remove_trigger(&accel_state->common_attributes);
354error_unreg_buffer_funcs: 354error_unreg_buffer_funcs:
355 iio_triggered_buffer_cleanup(indio_dev); 355 iio_triggered_buffer_cleanup(indio_dev);
356error_free_dev_mem: 356error_free_dev_mem:
@@ -363,10 +363,11 @@ static int hid_accel_3d_remove(struct platform_device *pdev)
363{ 363{
364 struct hid_sensor_hub_device *hsdev = pdev->dev.platform_data; 364 struct hid_sensor_hub_device *hsdev = pdev->dev.platform_data;
365 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 365 struct iio_dev *indio_dev = platform_get_drvdata(pdev);
366 struct accel_3d_state *accel_state = iio_priv(indio_dev);
366 367
367 sensor_hub_remove_callback(hsdev, HID_USAGE_SENSOR_ACCEL_3D); 368 sensor_hub_remove_callback(hsdev, HID_USAGE_SENSOR_ACCEL_3D);
368 iio_device_unregister(indio_dev); 369 iio_device_unregister(indio_dev);
369 hid_sensor_remove_trigger(indio_dev); 370 hid_sensor_remove_trigger(&accel_state->common_attributes);
370 iio_triggered_buffer_cleanup(indio_dev); 371 iio_triggered_buffer_cleanup(indio_dev);
371 kfree(indio_dev->channels); 372 kfree(indio_dev->channels);
372 373
diff --git a/drivers/iio/accel/kxsd9.c b/drivers/iio/accel/kxsd9.c
index d72118d1189c..98ba761cbb9c 100644
--- a/drivers/iio/accel/kxsd9.c
+++ b/drivers/iio/accel/kxsd9.c
@@ -112,9 +112,10 @@ static int kxsd9_read(struct iio_dev *indio_dev, u8 address)
112 mutex_lock(&st->buf_lock); 112 mutex_lock(&st->buf_lock);
113 st->tx[0] = KXSD9_READ(address); 113 st->tx[0] = KXSD9_READ(address);
114 ret = spi_sync_transfer(st->us, xfers, ARRAY_SIZE(xfers)); 114 ret = spi_sync_transfer(st->us, xfers, ARRAY_SIZE(xfers));
115 if (ret) 115 if (!ret)
116 return ret; 116 ret = (((u16)(st->rx[0])) << 8) | (st->rx[1] & 0xF0);
117 return (((u16)(st->rx[0])) << 8) | (st->rx[1] & 0xF0); 117 mutex_unlock(&st->buf_lock);
118 return ret;
118} 119}
119 120
120static IIO_CONST_ATTR(accel_scale_available, 121static IIO_CONST_ATTR(accel_scale_available,
diff --git a/drivers/iio/adc/at91_adc.c b/drivers/iio/adc/at91_adc.c
index 17df74908db1..5b1aa027c034 100644
--- a/drivers/iio/adc/at91_adc.c
+++ b/drivers/iio/adc/at91_adc.c
@@ -1047,6 +1047,7 @@ static int at91_adc_probe(struct platform_device *pdev)
1047 } else { 1047 } else {
1048 if (!st->caps->has_tsmr) { 1048 if (!st->caps->has_tsmr) {
1049 dev_err(&pdev->dev, "We don't support non-TSMR adc\n"); 1049 dev_err(&pdev->dev, "We don't support non-TSMR adc\n");
1050 ret = -ENODEV;
1050 goto error_disable_adc_clk; 1051 goto error_disable_adc_clk;
1051 } 1052 }
1052 1053
diff --git a/drivers/iio/adc/mcp3422.c b/drivers/iio/adc/mcp3422.c
index 12948325431c..c8c1baaec6c1 100644
--- a/drivers/iio/adc/mcp3422.c
+++ b/drivers/iio/adc/mcp3422.c
@@ -88,10 +88,10 @@ static const int mcp3422_sample_rates[4] = {
88 88
89/* sample rates to sign extension table */ 89/* sample rates to sign extension table */
90static const int mcp3422_sign_extend[4] = { 90static const int mcp3422_sign_extend[4] = {
91 [MCP3422_SRATE_240] = 12, 91 [MCP3422_SRATE_240] = 11,
92 [MCP3422_SRATE_60] = 14, 92 [MCP3422_SRATE_60] = 13,
93 [MCP3422_SRATE_15] = 16, 93 [MCP3422_SRATE_15] = 15,
94 [MCP3422_SRATE_3] = 18 }; 94 [MCP3422_SRATE_3] = 17 };
95 95
96/* Client data (each client gets its own) */ 96/* Client data (each client gets its own) */
97struct mcp3422 { 97struct mcp3422 {
diff --git a/drivers/iio/adc/ti_am335x_adc.c b/drivers/iio/adc/ti_am335x_adc.c
index 728411ec7642..d4d748214e4b 100644
--- a/drivers/iio/adc/ti_am335x_adc.c
+++ b/drivers/iio/adc/ti_am335x_adc.c
@@ -229,12 +229,15 @@ static int tiadc_iio_buffered_hardware_setup(struct iio_dev *indio_dev,
229 unsigned long flags, 229 unsigned long flags,
230 const struct iio_buffer_setup_ops *setup_ops) 230 const struct iio_buffer_setup_ops *setup_ops)
231{ 231{
232 struct iio_buffer *buffer;
232 int ret; 233 int ret;
233 234
234 indio_dev->buffer = iio_kfifo_allocate(indio_dev); 235 buffer = iio_kfifo_allocate(indio_dev);
235 if (!indio_dev->buffer) 236 if (!buffer)
236 return -ENOMEM; 237 return -ENOMEM;
237 238
239 iio_device_attach_buffer(indio_dev, buffer);
240
238 ret = request_threaded_irq(irq, pollfunc_th, pollfunc_bh, 241 ret = request_threaded_irq(irq, pollfunc_th, pollfunc_bh,
239 flags, indio_dev->name, indio_dev); 242 flags, indio_dev->name, indio_dev);
240 if (ret) 243 if (ret)
diff --git a/drivers/iio/common/hid-sensors/hid-sensor-trigger.c b/drivers/iio/common/hid-sensors/hid-sensor-trigger.c
index b6e77e0fc420..bbd6426c9726 100644
--- a/drivers/iio/common/hid-sensors/hid-sensor-trigger.c
+++ b/drivers/iio/common/hid-sensors/hid-sensor-trigger.c
@@ -55,11 +55,10 @@ static int hid_sensor_data_rdy_trigger_set_state(struct iio_trigger *trig,
55 return 0; 55 return 0;
56} 56}
57 57
58void hid_sensor_remove_trigger(struct iio_dev *indio_dev) 58void hid_sensor_remove_trigger(struct hid_sensor_common *attrb)
59{ 59{
60 iio_trigger_unregister(indio_dev->trig); 60 iio_trigger_unregister(attrb->trigger);
61 iio_trigger_free(indio_dev->trig); 61 iio_trigger_free(attrb->trigger);
62 indio_dev->trig = NULL;
63} 62}
64EXPORT_SYMBOL(hid_sensor_remove_trigger); 63EXPORT_SYMBOL(hid_sensor_remove_trigger);
65 64
@@ -90,7 +89,7 @@ int hid_sensor_setup_trigger(struct iio_dev *indio_dev, const char *name,
90 dev_err(&indio_dev->dev, "Trigger Register Failed\n"); 89 dev_err(&indio_dev->dev, "Trigger Register Failed\n");
91 goto error_free_trig; 90 goto error_free_trig;
92 } 91 }
93 indio_dev->trig = trig; 92 indio_dev->trig = attrb->trigger = trig;
94 93
95 return ret; 94 return ret;
96 95
diff --git a/drivers/iio/common/hid-sensors/hid-sensor-trigger.h b/drivers/iio/common/hid-sensors/hid-sensor-trigger.h
index 9a8731478eda..ca02f7811aa8 100644
--- a/drivers/iio/common/hid-sensors/hid-sensor-trigger.h
+++ b/drivers/iio/common/hid-sensors/hid-sensor-trigger.h
@@ -21,6 +21,6 @@
21 21
22int hid_sensor_setup_trigger(struct iio_dev *indio_dev, const char *name, 22int hid_sensor_setup_trigger(struct iio_dev *indio_dev, const char *name,
23 struct hid_sensor_common *attrb); 23 struct hid_sensor_common *attrb);
24void hid_sensor_remove_trigger(struct iio_dev *indio_dev); 24void hid_sensor_remove_trigger(struct hid_sensor_common *attrb);
25 25
26#endif 26#endif
diff --git a/drivers/iio/gyro/hid-sensor-gyro-3d.c b/drivers/iio/gyro/hid-sensor-gyro-3d.c
index ea01c6bcfb56..e54f0f4959d3 100644
--- a/drivers/iio/gyro/hid-sensor-gyro-3d.c
+++ b/drivers/iio/gyro/hid-sensor-gyro-3d.c
@@ -348,7 +348,7 @@ static int hid_gyro_3d_probe(struct platform_device *pdev)
348error_iio_unreg: 348error_iio_unreg:
349 iio_device_unregister(indio_dev); 349 iio_device_unregister(indio_dev);
350error_remove_trigger: 350error_remove_trigger:
351 hid_sensor_remove_trigger(indio_dev); 351 hid_sensor_remove_trigger(&gyro_state->common_attributes);
352error_unreg_buffer_funcs: 352error_unreg_buffer_funcs:
353 iio_triggered_buffer_cleanup(indio_dev); 353 iio_triggered_buffer_cleanup(indio_dev);
354error_free_dev_mem: 354error_free_dev_mem:
@@ -361,10 +361,11 @@ static int hid_gyro_3d_remove(struct platform_device *pdev)
361{ 361{
362 struct hid_sensor_hub_device *hsdev = pdev->dev.platform_data; 362 struct hid_sensor_hub_device *hsdev = pdev->dev.platform_data;
363 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 363 struct iio_dev *indio_dev = platform_get_drvdata(pdev);
364 struct gyro_3d_state *gyro_state = iio_priv(indio_dev);
364 365
365 sensor_hub_remove_callback(hsdev, HID_USAGE_SENSOR_GYRO_3D); 366 sensor_hub_remove_callback(hsdev, HID_USAGE_SENSOR_GYRO_3D);
366 iio_device_unregister(indio_dev); 367 iio_device_unregister(indio_dev);
367 hid_sensor_remove_trigger(indio_dev); 368 hid_sensor_remove_trigger(&gyro_state->common_attributes);
368 iio_triggered_buffer_cleanup(indio_dev); 369 iio_triggered_buffer_cleanup(indio_dev);
369 kfree(indio_dev->channels); 370 kfree(indio_dev->channels);
370 371
diff --git a/drivers/iio/light/Kconfig b/drivers/iio/light/Kconfig
index f98c2b509254..b0d65df3ede2 100644
--- a/drivers/iio/light/Kconfig
+++ b/drivers/iio/light/Kconfig
@@ -81,6 +81,8 @@ config SENSORS_LM3533
81config TCS3472 81config TCS3472
82 tristate "TAOS TCS3472 color light-to-digital converter" 82 tristate "TAOS TCS3472 color light-to-digital converter"
83 depends on I2C 83 depends on I2C
84 select IIO_BUFFER
85 select IIO_TRIGGERED_BUFFER
84 help 86 help
85 If you say yes here you get support for the TAOS TCS3472 87 If you say yes here you get support for the TAOS TCS3472
86 family of color light-to-digital converters with IR filter. 88 family of color light-to-digital converters with IR filter.
diff --git a/drivers/iio/light/hid-sensor-als.c b/drivers/iio/light/hid-sensor-als.c
index fa6ae8cf89ea..8e8b9d722853 100644
--- a/drivers/iio/light/hid-sensor-als.c
+++ b/drivers/iio/light/hid-sensor-als.c
@@ -314,7 +314,7 @@ static int hid_als_probe(struct platform_device *pdev)
314error_iio_unreg: 314error_iio_unreg:
315 iio_device_unregister(indio_dev); 315 iio_device_unregister(indio_dev);
316error_remove_trigger: 316error_remove_trigger:
317 hid_sensor_remove_trigger(indio_dev); 317 hid_sensor_remove_trigger(&als_state->common_attributes);
318error_unreg_buffer_funcs: 318error_unreg_buffer_funcs:
319 iio_triggered_buffer_cleanup(indio_dev); 319 iio_triggered_buffer_cleanup(indio_dev);
320error_free_dev_mem: 320error_free_dev_mem:
@@ -327,10 +327,11 @@ static int hid_als_remove(struct platform_device *pdev)
327{ 327{
328 struct hid_sensor_hub_device *hsdev = pdev->dev.platform_data; 328 struct hid_sensor_hub_device *hsdev = pdev->dev.platform_data;
329 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 329 struct iio_dev *indio_dev = platform_get_drvdata(pdev);
330 struct als_state *als_state = iio_priv(indio_dev);
330 331
331 sensor_hub_remove_callback(hsdev, HID_USAGE_SENSOR_ALS); 332 sensor_hub_remove_callback(hsdev, HID_USAGE_SENSOR_ALS);
332 iio_device_unregister(indio_dev); 333 iio_device_unregister(indio_dev);
333 hid_sensor_remove_trigger(indio_dev); 334 hid_sensor_remove_trigger(&als_state->common_attributes);
334 iio_triggered_buffer_cleanup(indio_dev); 335 iio_triggered_buffer_cleanup(indio_dev);
335 kfree(indio_dev->channels); 336 kfree(indio_dev->channels);
336 337
diff --git a/drivers/iio/magnetometer/Kconfig b/drivers/iio/magnetometer/Kconfig
index 0cf09637b35b..d86d226dcd67 100644
--- a/drivers/iio/magnetometer/Kconfig
+++ b/drivers/iio/magnetometer/Kconfig
@@ -19,6 +19,8 @@ config AK8975
19config MAG3110 19config MAG3110
20 tristate "Freescale MAG3110 3-Axis Magnetometer" 20 tristate "Freescale MAG3110 3-Axis Magnetometer"
21 depends on I2C 21 depends on I2C
22 select IIO_BUFFER
23 select IIO_TRIGGERED_BUFFER
22 help 24 help
23 Say yes here to build support for the Freescale MAG3110 3-Axis 25 Say yes here to build support for the Freescale MAG3110 3-Axis
24 magnetometer. 26 magnetometer.
diff --git a/drivers/iio/magnetometer/hid-sensor-magn-3d.c b/drivers/iio/magnetometer/hid-sensor-magn-3d.c
index 2634920562fb..b26e1028a0a0 100644
--- a/drivers/iio/magnetometer/hid-sensor-magn-3d.c
+++ b/drivers/iio/magnetometer/hid-sensor-magn-3d.c
@@ -351,7 +351,7 @@ static int hid_magn_3d_probe(struct platform_device *pdev)
351error_iio_unreg: 351error_iio_unreg:
352 iio_device_unregister(indio_dev); 352 iio_device_unregister(indio_dev);
353error_remove_trigger: 353error_remove_trigger:
354 hid_sensor_remove_trigger(indio_dev); 354 hid_sensor_remove_trigger(&magn_state->common_attributes);
355error_unreg_buffer_funcs: 355error_unreg_buffer_funcs:
356 iio_triggered_buffer_cleanup(indio_dev); 356 iio_triggered_buffer_cleanup(indio_dev);
357error_free_dev_mem: 357error_free_dev_mem:
@@ -364,10 +364,11 @@ static int hid_magn_3d_remove(struct platform_device *pdev)
364{ 364{
365 struct hid_sensor_hub_device *hsdev = pdev->dev.platform_data; 365 struct hid_sensor_hub_device *hsdev = pdev->dev.platform_data;
366 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 366 struct iio_dev *indio_dev = platform_get_drvdata(pdev);
367 struct magn_3d_state *magn_state = iio_priv(indio_dev);
367 368
368 sensor_hub_remove_callback(hsdev, HID_USAGE_SENSOR_COMPASS_3D); 369 sensor_hub_remove_callback(hsdev, HID_USAGE_SENSOR_COMPASS_3D);
369 iio_device_unregister(indio_dev); 370 iio_device_unregister(indio_dev);
370 hid_sensor_remove_trigger(indio_dev); 371 hid_sensor_remove_trigger(&magn_state->common_attributes);
371 iio_triggered_buffer_cleanup(indio_dev); 372 iio_triggered_buffer_cleanup(indio_dev);
372 kfree(indio_dev->channels); 373 kfree(indio_dev->channels);
373 374
diff --git a/drivers/iio/magnetometer/mag3110.c b/drivers/iio/magnetometer/mag3110.c
index 783c5b417356..becf54496967 100644
--- a/drivers/iio/magnetometer/mag3110.c
+++ b/drivers/iio/magnetometer/mag3110.c
@@ -250,7 +250,12 @@ done:
250 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 250 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
251 BIT(IIO_CHAN_INFO_SCALE), \ 251 BIT(IIO_CHAN_INFO_SCALE), \
252 .scan_index = idx, \ 252 .scan_index = idx, \
253 .scan_type = IIO_ST('s', 16, 16, IIO_BE), \ 253 .scan_type = { \
254 .sign = 's', \
255 .realbits = 16, \
256 .storagebits = 16, \
257 .endianness = IIO_BE, \
258 }, \
254} 259}
255 260
256static const struct iio_chan_spec mag3110_channels[] = { 261static const struct iio_chan_spec mag3110_channels[] = {
diff --git a/drivers/input/keyboard/tegra-kbc.c b/drivers/input/keyboard/tegra-kbc.c
index 8508879f6faf..9757a58bc897 100644
--- a/drivers/input/keyboard/tegra-kbc.c
+++ b/drivers/input/keyboard/tegra-kbc.c
@@ -31,7 +31,7 @@
31#include <linux/clk.h> 31#include <linux/clk.h>
32#include <linux/slab.h> 32#include <linux/slab.h>
33#include <linux/input/matrix_keypad.h> 33#include <linux/input/matrix_keypad.h>
34#include <linux/clk/tegra.h> 34#include <linux/reset.h>
35#include <linux/err.h> 35#include <linux/err.h>
36 36
37#define KBC_MAX_KPENT 8 37#define KBC_MAX_KPENT 8
@@ -116,6 +116,7 @@ struct tegra_kbc {
116 u32 wakeup_key; 116 u32 wakeup_key;
117 struct timer_list timer; 117 struct timer_list timer;
118 struct clk *clk; 118 struct clk *clk;
119 struct reset_control *rst;
119 const struct tegra_kbc_hw_support *hw_support; 120 const struct tegra_kbc_hw_support *hw_support;
120 int max_keys; 121 int max_keys;
121 int num_rows_and_columns; 122 int num_rows_and_columns;
@@ -373,9 +374,9 @@ static int tegra_kbc_start(struct tegra_kbc *kbc)
373 clk_prepare_enable(kbc->clk); 374 clk_prepare_enable(kbc->clk);
374 375
375 /* Reset the KBC controller to clear all previous status.*/ 376 /* Reset the KBC controller to clear all previous status.*/
376 tegra_periph_reset_assert(kbc->clk); 377 reset_control_assert(kbc->rst);
377 udelay(100); 378 udelay(100);
378 tegra_periph_reset_deassert(kbc->clk); 379 reset_control_assert(kbc->rst);
379 udelay(100); 380 udelay(100);
380 381
381 tegra_kbc_config_pins(kbc); 382 tegra_kbc_config_pins(kbc);
@@ -663,6 +664,12 @@ static int tegra_kbc_probe(struct platform_device *pdev)
663 return PTR_ERR(kbc->clk); 664 return PTR_ERR(kbc->clk);
664 } 665 }
665 666
667 kbc->rst = devm_reset_control_get(&pdev->dev, "kbc");
668 if (IS_ERR(kbc->rst)) {
669 dev_err(&pdev->dev, "failed to get keyboard reset\n");
670 return PTR_ERR(kbc->rst);
671 }
672
666 /* 673 /*
667 * The time delay between two consecutive reads of the FIFO is 674 * The time delay between two consecutive reads of the FIFO is
668 * the sum of the repeat time and the time taken for scanning 675 * the sum of the repeat time and the time taken for scanning
diff --git a/drivers/input/misc/hp_sdc_rtc.c b/drivers/input/misc/hp_sdc_rtc.c
index 86b822806e95..45e0e3e55de2 100644
--- a/drivers/input/misc/hp_sdc_rtc.c
+++ b/drivers/input/misc/hp_sdc_rtc.c
@@ -180,7 +180,10 @@ static int64_t hp_sdc_rtc_read_i8042timer (uint8_t loadcmd, int numreg)
180 if (WARN_ON(down_interruptible(&i8042tregs))) 180 if (WARN_ON(down_interruptible(&i8042tregs)))
181 return -1; 181 return -1;
182 182
183 if (hp_sdc_enqueue_transaction(&t)) return -1; 183 if (hp_sdc_enqueue_transaction(&t)) {
184 up(&i8042tregs);
185 return -1;
186 }
184 187
185 /* Sleep until results come back. */ 188 /* Sleep until results come back. */
186 if (WARN_ON(down_interruptible(&i8042tregs))) 189 if (WARN_ON(down_interruptible(&i8042tregs)))
diff --git a/drivers/input/touchscreen/Kconfig b/drivers/input/touchscreen/Kconfig
index 00d1e547b211..961d58d32647 100644
--- a/drivers/input/touchscreen/Kconfig
+++ b/drivers/input/touchscreen/Kconfig
@@ -906,6 +906,17 @@ config TOUCHSCREEN_STMPE
906 To compile this driver as a module, choose M here: the 906 To compile this driver as a module, choose M here: the
907 module will be called stmpe-ts. 907 module will be called stmpe-ts.
908 908
909config TOUCHSCREEN_SUR40
910 tristate "Samsung SUR40 (Surface 2.0/PixelSense) touchscreen"
911 depends on USB
912 select INPUT_POLLDEV
913 help
914 Say Y here if you want support for the Samsung SUR40 touchscreen
915 (also known as Microsoft Surface 2.0 or Microsoft PixelSense).
916
917 To compile this driver as a module, choose M here: the
918 module will be called sur40.
919
909config TOUCHSCREEN_TPS6507X 920config TOUCHSCREEN_TPS6507X
910 tristate "TPS6507x based touchscreens" 921 tristate "TPS6507x based touchscreens"
911 depends on I2C 922 depends on I2C
diff --git a/drivers/input/touchscreen/Makefile b/drivers/input/touchscreen/Makefile
index 7587883b8d38..62801f213346 100644
--- a/drivers/input/touchscreen/Makefile
+++ b/drivers/input/touchscreen/Makefile
@@ -54,6 +54,7 @@ obj-$(CONFIG_TOUCHSCREEN_PIXCIR) += pixcir_i2c_ts.o
54obj-$(CONFIG_TOUCHSCREEN_S3C2410) += s3c2410_ts.o 54obj-$(CONFIG_TOUCHSCREEN_S3C2410) += s3c2410_ts.o
55obj-$(CONFIG_TOUCHSCREEN_ST1232) += st1232.o 55obj-$(CONFIG_TOUCHSCREEN_ST1232) += st1232.o
56obj-$(CONFIG_TOUCHSCREEN_STMPE) += stmpe-ts.o 56obj-$(CONFIG_TOUCHSCREEN_STMPE) += stmpe-ts.o
57obj-$(CONFIG_TOUCHSCREEN_SUR40) += sur40.o
57obj-$(CONFIG_TOUCHSCREEN_TI_AM335X_TSC) += ti_am335x_tsc.o 58obj-$(CONFIG_TOUCHSCREEN_TI_AM335X_TSC) += ti_am335x_tsc.o
58obj-$(CONFIG_TOUCHSCREEN_TNETV107X) += tnetv107x-ts.o 59obj-$(CONFIG_TOUCHSCREEN_TNETV107X) += tnetv107x-ts.o
59obj-$(CONFIG_TOUCHSCREEN_TOUCHIT213) += touchit213.o 60obj-$(CONFIG_TOUCHSCREEN_TOUCHIT213) += touchit213.o
diff --git a/drivers/input/touchscreen/atmel-wm97xx.c b/drivers/input/touchscreen/atmel-wm97xx.c
index 268a35e55d7f..279c0e42b8a7 100644
--- a/drivers/input/touchscreen/atmel-wm97xx.c
+++ b/drivers/input/touchscreen/atmel-wm97xx.c
@@ -391,7 +391,7 @@ static int __exit atmel_wm97xx_remove(struct platform_device *pdev)
391} 391}
392 392
393#ifdef CONFIG_PM_SLEEP 393#ifdef CONFIG_PM_SLEEP
394static int atmel_wm97xx_suspend(struct *dev) 394static int atmel_wm97xx_suspend(struct device *dev)
395{ 395{
396 struct platform_device *pdev = to_platform_device(dev); 396 struct platform_device *pdev = to_platform_device(dev);
397 struct atmel_wm97xx *atmel_wm97xx = platform_get_drvdata(pdev); 397 struct atmel_wm97xx *atmel_wm97xx = platform_get_drvdata(pdev);
diff --git a/drivers/input/touchscreen/cyttsp4_core.c b/drivers/input/touchscreen/cyttsp4_core.c
index 42d830efa316..a035a390f8e2 100644
--- a/drivers/input/touchscreen/cyttsp4_core.c
+++ b/drivers/input/touchscreen/cyttsp4_core.c
@@ -1246,8 +1246,7 @@ static void cyttsp4_watchdog_timer(unsigned long handle)
1246 1246
1247 dev_vdbg(cd->dev, "%s: Watchdog timer triggered\n", __func__); 1247 dev_vdbg(cd->dev, "%s: Watchdog timer triggered\n", __func__);
1248 1248
1249 if (!work_pending(&cd->watchdog_work)) 1249 schedule_work(&cd->watchdog_work);
1250 schedule_work(&cd->watchdog_work);
1251 1250
1252 return; 1251 return;
1253} 1252}
diff --git a/drivers/input/touchscreen/sur40.c b/drivers/input/touchscreen/sur40.c
new file mode 100644
index 000000000000..cfd1b7e8c001
--- /dev/null
+++ b/drivers/input/touchscreen/sur40.c
@@ -0,0 +1,466 @@
1/*
2 * Surface2.0/SUR40/PixelSense input driver
3 *
4 * Copyright (c) 2013 by Florian 'floe' Echtler <floe@butterbrot.org>
5 *
6 * Derived from the USB Skeleton driver 1.1,
7 * Copyright (c) 2003 Greg Kroah-Hartman (greg@kroah.com)
8 *
9 * and from the Apple USB BCM5974 multitouch driver,
10 * Copyright (c) 2008 Henrik Rydberg (rydberg@euromail.se)
11 *
12 * and from the generic hid-multitouch driver,
13 * Copyright (c) 2010-2012 Stephane Chatty <chatty@enac.fr>
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 */
20
21#include <linux/kernel.h>
22#include <linux/errno.h>
23#include <linux/delay.h>
24#include <linux/init.h>
25#include <linux/slab.h>
26#include <linux/module.h>
27#include <linux/completion.h>
28#include <linux/uaccess.h>
29#include <linux/usb.h>
30#include <linux/printk.h>
31#include <linux/input-polldev.h>
32#include <linux/input/mt.h>
33#include <linux/usb/input.h>
34
35/* read 512 bytes from endpoint 0x86 -> get header + blobs */
36struct sur40_header {
37
38 __le16 type; /* always 0x0001 */
39 __le16 count; /* count of blobs (if 0: continue prev. packet) */
40
41 __le32 packet_id; /* unique ID for all packets in one frame */
42
43 __le32 timestamp; /* milliseconds (inc. by 16 or 17 each frame) */
44 __le32 unknown; /* "epoch?" always 02/03 00 00 00 */
45
46} __packed;
47
48struct sur40_blob {
49
50 __le16 blob_id;
51
52 u8 action; /* 0x02 = enter/exit, 0x03 = update (?) */
53 u8 unknown; /* always 0x01 or 0x02 (no idea what this is?) */
54
55 __le16 bb_pos_x; /* upper left corner of bounding box */
56 __le16 bb_pos_y;
57
58 __le16 bb_size_x; /* size of bounding box */
59 __le16 bb_size_y;
60
61 __le16 pos_x; /* finger tip position */
62 __le16 pos_y;
63
64 __le16 ctr_x; /* centroid position */
65 __le16 ctr_y;
66
67 __le16 axis_x; /* somehow related to major/minor axis, mostly: */
68 __le16 axis_y; /* axis_x == bb_size_y && axis_y == bb_size_x */
69
70 __le32 angle; /* orientation in radians relative to x axis -
71 actually an IEEE754 float, don't use in kernel */
72
73 __le32 area; /* size in pixels/pressure (?) */
74
75 u8 padding[32];
76
77} __packed;
78
79/* combined header/blob data */
80struct sur40_data {
81 struct sur40_header header;
82 struct sur40_blob blobs[];
83} __packed;
84
85
86/* version information */
87#define DRIVER_SHORT "sur40"
88#define DRIVER_AUTHOR "Florian 'floe' Echtler <floe@butterbrot.org>"
89#define DRIVER_DESC "Surface2.0/SUR40/PixelSense input driver"
90
91/* vendor and device IDs */
92#define ID_MICROSOFT 0x045e
93#define ID_SUR40 0x0775
94
95/* sensor resolution */
96#define SENSOR_RES_X 1920
97#define SENSOR_RES_Y 1080
98
99/* touch data endpoint */
100#define TOUCH_ENDPOINT 0x86
101
102/* polling interval (ms) */
103#define POLL_INTERVAL 10
104
105/* maximum number of contacts FIXME: this is a guess? */
106#define MAX_CONTACTS 64
107
108/* control commands */
109#define SUR40_GET_VERSION 0xb0 /* 12 bytes string */
110#define SUR40_UNKNOWN1 0xb3 /* 5 bytes */
111#define SUR40_UNKNOWN2 0xc1 /* 24 bytes */
112
113#define SUR40_GET_STATE 0xc5 /* 4 bytes state (?) */
114#define SUR40_GET_SENSORS 0xb1 /* 8 bytes sensors */
115
116/*
117 * Note: an earlier, non-public version of this driver used USB_RECIP_ENDPOINT
118 * here by mistake which is very likely to have corrupted the firmware EEPROM
119 * on two separate SUR40 devices. Thanks to Alan Stern who spotted this bug.
120 * Should you ever run into a similar problem, the background story to this
121 * incident and instructions on how to fix the corrupted EEPROM are available
122 * at https://floe.butterbrot.org/matrix/hacking/surface/brick.html
123*/
124
125struct sur40_state {
126
127 struct usb_device *usbdev;
128 struct device *dev;
129 struct input_polled_dev *input;
130
131 struct sur40_data *bulk_in_buffer;
132 size_t bulk_in_size;
133 u8 bulk_in_epaddr;
134
135 char phys[64];
136};
137
138static int sur40_command(struct sur40_state *dev,
139 u8 command, u16 index, void *buffer, u16 size)
140{
141 return usb_control_msg(dev->usbdev, usb_rcvctrlpipe(dev->usbdev, 0),
142 command,
143 USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_DIR_IN,
144 0x00, index, buffer, size, 1000);
145}
146
147/* Initialization routine, called from sur40_open */
148static int sur40_init(struct sur40_state *dev)
149{
150 int result;
151 u8 buffer[24];
152
153 /* stupidly replay the original MS driver init sequence */
154 result = sur40_command(dev, SUR40_GET_VERSION, 0x00, buffer, 12);
155 if (result < 0)
156 return result;
157
158 result = sur40_command(dev, SUR40_GET_VERSION, 0x01, buffer, 12);
159 if (result < 0)
160 return result;
161
162 result = sur40_command(dev, SUR40_GET_VERSION, 0x02, buffer, 12);
163 if (result < 0)
164 return result;
165
166 result = sur40_command(dev, SUR40_UNKNOWN2, 0x00, buffer, 24);
167 if (result < 0)
168 return result;
169
170 result = sur40_command(dev, SUR40_UNKNOWN1, 0x00, buffer, 5);
171 if (result < 0)
172 return result;
173
174 result = sur40_command(dev, SUR40_GET_VERSION, 0x03, buffer, 12);
175
176 /*
177 * Discard the result buffer - no known data inside except
178 * some version strings, maybe extract these sometime...
179 */
180
181 return result;
182}
183
184/*
185 * Callback routines from input_polled_dev
186 */
187
188/* Enable the device, polling will now start. */
189static void sur40_open(struct input_polled_dev *polldev)
190{
191 struct sur40_state *sur40 = polldev->private;
192
193 dev_dbg(sur40->dev, "open\n");
194 sur40_init(sur40);
195}
196
197/* Disable device, polling has stopped. */
198static void sur40_close(struct input_polled_dev *polldev)
199{
200 struct sur40_state *sur40 = polldev->private;
201
202 dev_dbg(sur40->dev, "close\n");
203 /*
204 * There is no known way to stop the device, so we simply
205 * stop polling.
206 */
207}
208
209/*
210 * This function is called when a whole contact has been processed,
211 * so that it can assign it to a slot and store the data there.
212 */
213static void sur40_report_blob(struct sur40_blob *blob, struct input_dev *input)
214{
215 int wide, major, minor;
216
217 int bb_size_x = le16_to_cpu(blob->bb_size_x);
218 int bb_size_y = le16_to_cpu(blob->bb_size_y);
219
220 int pos_x = le16_to_cpu(blob->pos_x);
221 int pos_y = le16_to_cpu(blob->pos_y);
222
223 int ctr_x = le16_to_cpu(blob->ctr_x);
224 int ctr_y = le16_to_cpu(blob->ctr_y);
225
226 int slotnum = input_mt_get_slot_by_key(input, blob->blob_id);
227 if (slotnum < 0 || slotnum >= MAX_CONTACTS)
228 return;
229
230 input_mt_slot(input, slotnum);
231 input_mt_report_slot_state(input, MT_TOOL_FINGER, 1);
232 wide = (bb_size_x > bb_size_y);
233 major = max(bb_size_x, bb_size_y);
234 minor = min(bb_size_x, bb_size_y);
235
236 input_report_abs(input, ABS_MT_POSITION_X, pos_x);
237 input_report_abs(input, ABS_MT_POSITION_Y, pos_y);
238 input_report_abs(input, ABS_MT_TOOL_X, ctr_x);
239 input_report_abs(input, ABS_MT_TOOL_Y, ctr_y);
240
241 /* TODO: use a better orientation measure */
242 input_report_abs(input, ABS_MT_ORIENTATION, wide);
243 input_report_abs(input, ABS_MT_TOUCH_MAJOR, major);
244 input_report_abs(input, ABS_MT_TOUCH_MINOR, minor);
245}
246
247/* core function: poll for new input data */
248static void sur40_poll(struct input_polled_dev *polldev)
249{
250
251 struct sur40_state *sur40 = polldev->private;
252 struct input_dev *input = polldev->input;
253 int result, bulk_read, need_blobs, packet_blobs, i;
254 u32 packet_id;
255
256 struct sur40_header *header = &sur40->bulk_in_buffer->header;
257 struct sur40_blob *inblob = &sur40->bulk_in_buffer->blobs[0];
258
259 dev_dbg(sur40->dev, "poll\n");
260
261 need_blobs = -1;
262
263 do {
264
265 /* perform a blocking bulk read to get data from the device */
266 result = usb_bulk_msg(sur40->usbdev,
267 usb_rcvbulkpipe(sur40->usbdev, sur40->bulk_in_epaddr),
268 sur40->bulk_in_buffer, sur40->bulk_in_size,
269 &bulk_read, 1000);
270
271 dev_dbg(sur40->dev, "received %d bytes\n", bulk_read);
272
273 if (result < 0) {
274 dev_err(sur40->dev, "error in usb_bulk_read\n");
275 return;
276 }
277
278 result = bulk_read - sizeof(struct sur40_header);
279
280 if (result % sizeof(struct sur40_blob) != 0) {
281 dev_err(sur40->dev, "transfer size mismatch\n");
282 return;
283 }
284
285 /* first packet? */
286 if (need_blobs == -1) {
287 need_blobs = le16_to_cpu(header->count);
288 dev_dbg(sur40->dev, "need %d blobs\n", need_blobs);
289 packet_id = header->packet_id;
290 }
291
292 /*
293 * Sanity check. when video data is also being retrieved, the
294 * packet ID will usually increase in the middle of a series
295 * instead of at the end.
296 */
297 if (packet_id != header->packet_id)
298 dev_warn(sur40->dev, "packet ID mismatch\n");
299
300 packet_blobs = result / sizeof(struct sur40_blob);
301 dev_dbg(sur40->dev, "received %d blobs\n", packet_blobs);
302
303 /* packets always contain at least 4 blobs, even if empty */
304 if (packet_blobs > need_blobs)
305 packet_blobs = need_blobs;
306
307 for (i = 0; i < packet_blobs; i++) {
308 need_blobs--;
309 dev_dbg(sur40->dev, "processing blob\n");
310 sur40_report_blob(&(inblob[i]), input);
311 }
312
313 } while (need_blobs > 0);
314
315 input_mt_sync_frame(input);
316 input_sync(input);
317}
318
319/* Initialize input device parameters. */
320static void sur40_input_setup(struct input_dev *input_dev)
321{
322 __set_bit(EV_KEY, input_dev->evbit);
323 __set_bit(EV_ABS, input_dev->evbit);
324
325 input_set_abs_params(input_dev, ABS_MT_POSITION_X,
326 0, SENSOR_RES_X, 0, 0);
327 input_set_abs_params(input_dev, ABS_MT_POSITION_Y,
328 0, SENSOR_RES_Y, 0, 0);
329
330 input_set_abs_params(input_dev, ABS_MT_TOOL_X,
331 0, SENSOR_RES_X, 0, 0);
332 input_set_abs_params(input_dev, ABS_MT_TOOL_Y,
333 0, SENSOR_RES_Y, 0, 0);
334
335 /* max value unknown, but major/minor axis
336 * can never be larger than screen */
337 input_set_abs_params(input_dev, ABS_MT_TOUCH_MAJOR,
338 0, SENSOR_RES_X, 0, 0);
339 input_set_abs_params(input_dev, ABS_MT_TOUCH_MINOR,
340 0, SENSOR_RES_Y, 0, 0);
341
342 input_set_abs_params(input_dev, ABS_MT_ORIENTATION, 0, 1, 0, 0);
343
344 input_mt_init_slots(input_dev, MAX_CONTACTS,
345 INPUT_MT_DIRECT | INPUT_MT_DROP_UNUSED);
346}
347
348/* Check candidate USB interface. */
349static int sur40_probe(struct usb_interface *interface,
350 const struct usb_device_id *id)
351{
352 struct usb_device *usbdev = interface_to_usbdev(interface);
353 struct sur40_state *sur40;
354 struct usb_host_interface *iface_desc;
355 struct usb_endpoint_descriptor *endpoint;
356 struct input_polled_dev *poll_dev;
357 int error;
358
359 /* Check if we really have the right interface. */
360 iface_desc = &interface->altsetting[0];
361 if (iface_desc->desc.bInterfaceClass != 0xFF)
362 return -ENODEV;
363
364 /* Use endpoint #4 (0x86). */
365 endpoint = &iface_desc->endpoint[4].desc;
366 if (endpoint->bEndpointAddress != TOUCH_ENDPOINT)
367 return -ENODEV;
368
369 /* Allocate memory for our device state and initialize it. */
370 sur40 = kzalloc(sizeof(struct sur40_state), GFP_KERNEL);
371 if (!sur40)
372 return -ENOMEM;
373
374 poll_dev = input_allocate_polled_device();
375 if (!poll_dev) {
376 error = -ENOMEM;
377 goto err_free_dev;
378 }
379
380 /* Set up polled input device control structure */
381 poll_dev->private = sur40;
382 poll_dev->poll_interval = POLL_INTERVAL;
383 poll_dev->open = sur40_open;
384 poll_dev->poll = sur40_poll;
385 poll_dev->close = sur40_close;
386
387 /* Set up regular input device structure */
388 sur40_input_setup(poll_dev->input);
389
390 poll_dev->input->name = "Samsung SUR40";
391 usb_to_input_id(usbdev, &poll_dev->input->id);
392 usb_make_path(usbdev, sur40->phys, sizeof(sur40->phys));
393 strlcat(sur40->phys, "/input0", sizeof(sur40->phys));
394 poll_dev->input->phys = sur40->phys;
395 poll_dev->input->dev.parent = &interface->dev;
396
397 sur40->usbdev = usbdev;
398 sur40->dev = &interface->dev;
399 sur40->input = poll_dev;
400
401 /* use the bulk-in endpoint tested above */
402 sur40->bulk_in_size = usb_endpoint_maxp(endpoint);
403 sur40->bulk_in_epaddr = endpoint->bEndpointAddress;
404 sur40->bulk_in_buffer = kmalloc(sur40->bulk_in_size, GFP_KERNEL);
405 if (!sur40->bulk_in_buffer) {
406 dev_err(&interface->dev, "Unable to allocate input buffer.");
407 error = -ENOMEM;
408 goto err_free_polldev;
409 }
410
411 error = input_register_polled_device(poll_dev);
412 if (error) {
413 dev_err(&interface->dev,
414 "Unable to register polled input device.");
415 goto err_free_buffer;
416 }
417
418 /* we can register the device now, as it is ready */
419 usb_set_intfdata(interface, sur40);
420 dev_dbg(&interface->dev, "%s is now attached\n", DRIVER_DESC);
421
422 return 0;
423
424err_free_buffer:
425 kfree(sur40->bulk_in_buffer);
426err_free_polldev:
427 input_free_polled_device(sur40->input);
428err_free_dev:
429 kfree(sur40);
430
431 return error;
432}
433
434/* Unregister device & clean up. */
435static void sur40_disconnect(struct usb_interface *interface)
436{
437 struct sur40_state *sur40 = usb_get_intfdata(interface);
438
439 input_unregister_polled_device(sur40->input);
440 input_free_polled_device(sur40->input);
441 kfree(sur40->bulk_in_buffer);
442 kfree(sur40);
443
444 usb_set_intfdata(interface, NULL);
445 dev_dbg(&interface->dev, "%s is now disconnected\n", DRIVER_DESC);
446}
447
448static const struct usb_device_id sur40_table[] = {
449 { USB_DEVICE(ID_MICROSOFT, ID_SUR40) }, /* Samsung SUR40 */
450 { } /* terminating null entry */
451};
452MODULE_DEVICE_TABLE(usb, sur40_table);
453
454/* USB-specific object needed to register this driver with the USB subsystem. */
455static struct usb_driver sur40_driver = {
456 .name = DRIVER_SHORT,
457 .probe = sur40_probe,
458 .disconnect = sur40_disconnect,
459 .id_table = sur40_table,
460};
461
462module_usb_driver(sur40_driver);
463
464MODULE_AUTHOR(DRIVER_AUTHOR);
465MODULE_DESCRIPTION(DRIVER_DESC);
466MODULE_LICENSE("GPL");
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 9031171c141b..341c6016812d 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -957,12 +957,13 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
957 if (WARN_ON(!gic->domain)) 957 if (WARN_ON(!gic->domain))
958 return; 958 return;
959 959
960 if (gic_nr == 0) {
960#ifdef CONFIG_SMP 961#ifdef CONFIG_SMP
961 set_smp_cross_call(gic_raise_softirq); 962 set_smp_cross_call(gic_raise_softirq);
962 register_cpu_notifier(&gic_cpu_notifier); 963 register_cpu_notifier(&gic_cpu_notifier);
963#endif 964#endif
964 965 set_handle_irq(gic_handle_irq);
965 set_handle_irq(gic_handle_irq); 966 }
966 967
967 gic_chip.flags |= gic_arch_extn.flags; 968 gic_chip.flags |= gic_arch_extn.flags;
968 gic_dist_init(gic); 969 gic_dist_init(gic);
diff --git a/drivers/leds/leds-pwm.c b/drivers/leds/leds-pwm.c
index 2848171b8576..b31d8e99c419 100644
--- a/drivers/leds/leds-pwm.c
+++ b/drivers/leds/leds-pwm.c
@@ -82,22 +82,12 @@ static inline size_t sizeof_pwm_leds_priv(int num_leds)
82 (sizeof(struct led_pwm_data) * num_leds); 82 (sizeof(struct led_pwm_data) * num_leds);
83} 83}
84 84
85static struct led_pwm_priv *led_pwm_create_of(struct platform_device *pdev) 85static int led_pwm_create_of(struct platform_device *pdev,
86 struct led_pwm_priv *priv)
86{ 87{
87 struct device_node *node = pdev->dev.of_node; 88 struct device_node *node = pdev->dev.of_node;
88 struct device_node *child; 89 struct device_node *child;
89 struct led_pwm_priv *priv; 90 int ret;
90 int count, ret;
91
92 /* count LEDs in this device, so we know how much to allocate */
93 count = of_get_child_count(node);
94 if (!count)
95 return NULL;
96
97 priv = devm_kzalloc(&pdev->dev, sizeof_pwm_leds_priv(count),
98 GFP_KERNEL);
99 if (!priv)
100 return NULL;
101 91
102 for_each_child_of_node(node, child) { 92 for_each_child_of_node(node, child) {
103 struct led_pwm_data *led_dat = &priv->leds[priv->num_leds]; 93 struct led_pwm_data *led_dat = &priv->leds[priv->num_leds];
@@ -109,6 +99,7 @@ static struct led_pwm_priv *led_pwm_create_of(struct platform_device *pdev)
109 if (IS_ERR(led_dat->pwm)) { 99 if (IS_ERR(led_dat->pwm)) {
110 dev_err(&pdev->dev, "unable to request PWM for %s\n", 100 dev_err(&pdev->dev, "unable to request PWM for %s\n",
111 led_dat->cdev.name); 101 led_dat->cdev.name);
102 ret = PTR_ERR(led_dat->pwm);
112 goto err; 103 goto err;
113 } 104 }
114 /* Get the period from PWM core when n*/ 105 /* Get the period from PWM core when n*/
@@ -137,28 +128,36 @@ static struct led_pwm_priv *led_pwm_create_of(struct platform_device *pdev)
137 priv->num_leds++; 128 priv->num_leds++;
138 } 129 }
139 130
140 return priv; 131 return 0;
141err: 132err:
142 while (priv->num_leds--) 133 while (priv->num_leds--)
143 led_classdev_unregister(&priv->leds[priv->num_leds].cdev); 134 led_classdev_unregister(&priv->leds[priv->num_leds].cdev);
144 135
145 return NULL; 136 return ret;
146} 137}
147 138
148static int led_pwm_probe(struct platform_device *pdev) 139static int led_pwm_probe(struct platform_device *pdev)
149{ 140{
150 struct led_pwm_platform_data *pdata = dev_get_platdata(&pdev->dev); 141 struct led_pwm_platform_data *pdata = dev_get_platdata(&pdev->dev);
151 struct led_pwm_priv *priv; 142 struct led_pwm_priv *priv;
152 int i, ret = 0; 143 int count, i;
144 int ret = 0;
145
146 if (pdata)
147 count = pdata->num_leds;
148 else
149 count = of_get_child_count(pdev->dev.of_node);
150
151 if (!count)
152 return -EINVAL;
153 153
154 if (pdata && pdata->num_leds) { 154 priv = devm_kzalloc(&pdev->dev, sizeof_pwm_leds_priv(count),
155 priv = devm_kzalloc(&pdev->dev, 155 GFP_KERNEL);
156 sizeof_pwm_leds_priv(pdata->num_leds), 156 if (!priv)
157 GFP_KERNEL); 157 return -ENOMEM;
158 if (!priv)
159 return -ENOMEM;
160 158
161 for (i = 0; i < pdata->num_leds; i++) { 159 if (pdata) {
160 for (i = 0; i < count; i++) {
162 struct led_pwm *cur_led = &pdata->leds[i]; 161 struct led_pwm *cur_led = &pdata->leds[i];
163 struct led_pwm_data *led_dat = &priv->leds[i]; 162 struct led_pwm_data *led_dat = &priv->leds[i];
164 163
@@ -188,11 +187,11 @@ static int led_pwm_probe(struct platform_device *pdev)
188 if (ret < 0) 187 if (ret < 0)
189 goto err; 188 goto err;
190 } 189 }
191 priv->num_leds = pdata->num_leds; 190 priv->num_leds = count;
192 } else { 191 } else {
193 priv = led_pwm_create_of(pdev); 192 ret = led_pwm_create_of(pdev, priv);
194 if (!priv) 193 if (ret)
195 return -ENODEV; 194 return ret;
196 } 195 }
197 196
198 platform_set_drvdata(pdev, priv); 197 platform_set_drvdata(pdev, priv);
diff --git a/drivers/macintosh/Makefile b/drivers/macintosh/Makefile
index 6753b65f8ede..d2f0120bc878 100644
--- a/drivers/macintosh/Makefile
+++ b/drivers/macintosh/Makefile
@@ -40,6 +40,7 @@ obj-$(CONFIG_WINDFARM_RM31) += windfarm_fcu_controls.o \
40 windfarm_ad7417_sensor.o \ 40 windfarm_ad7417_sensor.o \
41 windfarm_lm75_sensor.o \ 41 windfarm_lm75_sensor.o \
42 windfarm_lm87_sensor.o \ 42 windfarm_lm87_sensor.o \
43 windfarm_max6690_sensor.o \
43 windfarm_pid.o \ 44 windfarm_pid.o \
44 windfarm_cpufreq_clamp.o \ 45 windfarm_cpufreq_clamp.o \
45 windfarm_rm31.o 46 windfarm_rm31.o
diff --git a/drivers/md/md.c b/drivers/md/md.c
index b6b7a2866c9e..21f4d7ff0da2 100644
--- a/drivers/md/md.c
+++ b/drivers/md/md.c
@@ -776,16 +776,10 @@ void md_super_wait(struct mddev *mddev)
776 finish_wait(&mddev->sb_wait, &wq); 776 finish_wait(&mddev->sb_wait, &wq);
777} 777}
778 778
779static void bi_complete(struct bio *bio, int error)
780{
781 complete((struct completion*)bio->bi_private);
782}
783
784int sync_page_io(struct md_rdev *rdev, sector_t sector, int size, 779int sync_page_io(struct md_rdev *rdev, sector_t sector, int size,
785 struct page *page, int rw, bool metadata_op) 780 struct page *page, int rw, bool metadata_op)
786{ 781{
787 struct bio *bio = bio_alloc_mddev(GFP_NOIO, 1, rdev->mddev); 782 struct bio *bio = bio_alloc_mddev(GFP_NOIO, 1, rdev->mddev);
788 struct completion event;
789 int ret; 783 int ret;
790 784
791 rw |= REQ_SYNC; 785 rw |= REQ_SYNC;
@@ -801,11 +795,7 @@ int sync_page_io(struct md_rdev *rdev, sector_t sector, int size,
801 else 795 else
802 bio->bi_sector = sector + rdev->data_offset; 796 bio->bi_sector = sector + rdev->data_offset;
803 bio_add_page(bio, page, size, 0); 797 bio_add_page(bio, page, size, 0);
804 init_completion(&event); 798 submit_bio_wait(rw, bio);
805 bio->bi_private = &event;
806 bio->bi_end_io = bi_complete;
807 submit_bio(rw, bio);
808 wait_for_completion(&event);
809 799
810 ret = test_bit(BIO_UPTODATE, &bio->bi_flags); 800 ret = test_bit(BIO_UPTODATE, &bio->bi_flags);
811 bio_put(bio); 801 bio_put(bio);
@@ -7777,7 +7767,7 @@ void md_check_recovery(struct mddev *mddev)
7777 if (mddev->ro && !test_bit(MD_RECOVERY_NEEDED, &mddev->recovery)) 7767 if (mddev->ro && !test_bit(MD_RECOVERY_NEEDED, &mddev->recovery))
7778 return; 7768 return;
7779 if ( ! ( 7769 if ( ! (
7780 (mddev->flags & ~ (1<<MD_CHANGE_PENDING)) || 7770 (mddev->flags & MD_UPDATE_SB_FLAGS & ~ (1<<MD_CHANGE_PENDING)) ||
7781 test_bit(MD_RECOVERY_NEEDED, &mddev->recovery) || 7771 test_bit(MD_RECOVERY_NEEDED, &mddev->recovery) ||
7782 test_bit(MD_RECOVERY_DONE, &mddev->recovery) || 7772 test_bit(MD_RECOVERY_DONE, &mddev->recovery) ||
7783 (mddev->external == 0 && mddev->safemode == 1) || 7773 (mddev->external == 0 && mddev->safemode == 1) ||
diff --git a/drivers/md/raid5.c b/drivers/md/raid5.c
index 47da0af6322b..cc055da02e2a 100644
--- a/drivers/md/raid5.c
+++ b/drivers/md/raid5.c
@@ -678,26 +678,23 @@ get_active_stripe(struct r5conf *conf, sector_t sector,
678 } else 678 } else
679 init_stripe(sh, sector, previous); 679 init_stripe(sh, sector, previous);
680 } else { 680 } else {
681 spin_lock(&conf->device_lock);
681 if (atomic_read(&sh->count)) { 682 if (atomic_read(&sh->count)) {
682 BUG_ON(!list_empty(&sh->lru) 683 BUG_ON(!list_empty(&sh->lru)
683 && !test_bit(STRIPE_EXPANDING, &sh->state) 684 && !test_bit(STRIPE_EXPANDING, &sh->state)
684 && !test_bit(STRIPE_ON_UNPLUG_LIST, &sh->state) 685 && !test_bit(STRIPE_ON_UNPLUG_LIST, &sh->state)
685 && !test_bit(STRIPE_ON_RELEASE_LIST, &sh->state)); 686 );
686 } else { 687 } else {
687 spin_lock(&conf->device_lock);
688 if (!test_bit(STRIPE_HANDLE, &sh->state)) 688 if (!test_bit(STRIPE_HANDLE, &sh->state))
689 atomic_inc(&conf->active_stripes); 689 atomic_inc(&conf->active_stripes);
690 if (list_empty(&sh->lru) && 690 BUG_ON(list_empty(&sh->lru));
691 !test_bit(STRIPE_ON_RELEASE_LIST, &sh->state) &&
692 !test_bit(STRIPE_EXPANDING, &sh->state))
693 BUG();
694 list_del_init(&sh->lru); 691 list_del_init(&sh->lru);
695 if (sh->group) { 692 if (sh->group) {
696 sh->group->stripes_cnt--; 693 sh->group->stripes_cnt--;
697 sh->group = NULL; 694 sh->group = NULL;
698 } 695 }
699 spin_unlock(&conf->device_lock);
700 } 696 }
697 spin_unlock(&conf->device_lock);
701 } 698 }
702 } while (sh == NULL); 699 } while (sh == NULL);
703 700
@@ -5471,7 +5468,7 @@ static int alloc_thread_groups(struct r5conf *conf, int cnt,
5471 for (i = 0; i < *group_cnt; i++) { 5468 for (i = 0; i < *group_cnt; i++) {
5472 struct r5worker_group *group; 5469 struct r5worker_group *group;
5473 5470
5474 group = worker_groups[i]; 5471 group = &(*worker_groups)[i];
5475 INIT_LIST_HEAD(&group->handle_list); 5472 INIT_LIST_HEAD(&group->handle_list);
5476 group->conf = conf; 5473 group->conf = conf;
5477 group->workers = workers + i * cnt; 5474 group->workers = workers + i * cnt;
diff --git a/drivers/misc/enclosure.c b/drivers/misc/enclosure.c
index 0e8df41aaf14..2cf2bbc0b927 100644
--- a/drivers/misc/enclosure.c
+++ b/drivers/misc/enclosure.c
@@ -198,6 +198,13 @@ static void enclosure_remove_links(struct enclosure_component *cdev)
198{ 198{
199 char name[ENCLOSURE_NAME_SIZE]; 199 char name[ENCLOSURE_NAME_SIZE];
200 200
201 /*
202 * In odd circumstances, like multipath devices, something else may
203 * already have removed the links, so check for this condition first.
204 */
205 if (!cdev->dev->kobj.sd)
206 return;
207
201 enclosure_link_name(cdev, name); 208 enclosure_link_name(cdev, name);
202 sysfs_remove_link(&cdev->dev->kobj, name); 209 sysfs_remove_link(&cdev->dev->kobj, name);
203 sysfs_remove_link(&cdev->cdev.kobj, "device"); 210 sysfs_remove_link(&cdev->cdev.kobj, "device");
diff --git a/drivers/mmc/host/omap.c b/drivers/mmc/host/omap.c
index 0b10a9030f4e..98b6b6ef7e5c 100644
--- a/drivers/mmc/host/omap.c
+++ b/drivers/mmc/host/omap.c
@@ -22,6 +22,7 @@
22#include <linux/delay.h> 22#include <linux/delay.h>
23#include <linux/spinlock.h> 23#include <linux/spinlock.h>
24#include <linux/timer.h> 24#include <linux/timer.h>
25#include <linux/of.h>
25#include <linux/omap-dma.h> 26#include <linux/omap-dma.h>
26#include <linux/mmc/host.h> 27#include <linux/mmc/host.h>
27#include <linux/mmc/card.h> 28#include <linux/mmc/card.h>
@@ -90,17 +91,6 @@
90#define OMAP_MMC_CMDTYPE_AC 2 91#define OMAP_MMC_CMDTYPE_AC 2
91#define OMAP_MMC_CMDTYPE_ADTC 3 92#define OMAP_MMC_CMDTYPE_ADTC 3
92 93
93#define OMAP_DMA_MMC_TX 21
94#define OMAP_DMA_MMC_RX 22
95#define OMAP_DMA_MMC2_TX 54
96#define OMAP_DMA_MMC2_RX 55
97
98#define OMAP24XX_DMA_MMC2_TX 47
99#define OMAP24XX_DMA_MMC2_RX 48
100#define OMAP24XX_DMA_MMC1_TX 61
101#define OMAP24XX_DMA_MMC1_RX 62
102
103
104#define DRIVER_NAME "mmci-omap" 94#define DRIVER_NAME "mmci-omap"
105 95
106/* Specifies how often in millisecs to poll for card status changes 96/* Specifies how often in millisecs to poll for card status changes
@@ -1330,7 +1320,7 @@ static int mmc_omap_probe(struct platform_device *pdev)
1330 struct mmc_omap_host *host = NULL; 1320 struct mmc_omap_host *host = NULL;
1331 struct resource *res; 1321 struct resource *res;
1332 dma_cap_mask_t mask; 1322 dma_cap_mask_t mask;
1333 unsigned sig; 1323 unsigned sig = 0;
1334 int i, ret = 0; 1324 int i, ret = 0;
1335 int irq; 1325 int irq;
1336 1326
@@ -1340,7 +1330,7 @@ static int mmc_omap_probe(struct platform_device *pdev)
1340 } 1330 }
1341 if (pdata->nr_slots == 0) { 1331 if (pdata->nr_slots == 0) {
1342 dev_err(&pdev->dev, "no slots\n"); 1332 dev_err(&pdev->dev, "no slots\n");
1343 return -ENXIO; 1333 return -EPROBE_DEFER;
1344 } 1334 }
1345 1335
1346 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1336 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -1407,19 +1397,20 @@ static int mmc_omap_probe(struct platform_device *pdev)
1407 host->dma_tx_burst = -1; 1397 host->dma_tx_burst = -1;
1408 host->dma_rx_burst = -1; 1398 host->dma_rx_burst = -1;
1409 1399
1410 if (mmc_omap2()) 1400 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1411 sig = host->id == 0 ? OMAP24XX_DMA_MMC1_TX : OMAP24XX_DMA_MMC2_TX; 1401 if (res)
1412 else 1402 sig = res->start;
1413 sig = host->id == 0 ? OMAP_DMA_MMC_TX : OMAP_DMA_MMC2_TX; 1403 host->dma_tx = dma_request_slave_channel_compat(mask,
1414 host->dma_tx = dma_request_channel(mask, omap_dma_filter_fn, &sig); 1404 omap_dma_filter_fn, &sig, &pdev->dev, "tx");
1415 if (!host->dma_tx) 1405 if (!host->dma_tx)
1416 dev_warn(host->dev, "unable to obtain TX DMA engine channel %u\n", 1406 dev_warn(host->dev, "unable to obtain TX DMA engine channel %u\n",
1417 sig); 1407 sig);
1418 if (mmc_omap2()) 1408
1419 sig = host->id == 0 ? OMAP24XX_DMA_MMC1_RX : OMAP24XX_DMA_MMC2_RX; 1409 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1420 else 1410 if (res)
1421 sig = host->id == 0 ? OMAP_DMA_MMC_RX : OMAP_DMA_MMC2_RX; 1411 sig = res->start;
1422 host->dma_rx = dma_request_channel(mask, omap_dma_filter_fn, &sig); 1412 host->dma_rx = dma_request_slave_channel_compat(mask,
1413 omap_dma_filter_fn, &sig, &pdev->dev, "rx");
1423 if (!host->dma_rx) 1414 if (!host->dma_rx)
1424 dev_warn(host->dev, "unable to obtain RX DMA engine channel %u\n", 1415 dev_warn(host->dev, "unable to obtain RX DMA engine channel %u\n",
1425 sig); 1416 sig);
@@ -1512,12 +1503,20 @@ static int mmc_omap_remove(struct platform_device *pdev)
1512 return 0; 1503 return 0;
1513} 1504}
1514 1505
1506#if IS_BUILTIN(CONFIG_OF)
1507static const struct of_device_id mmc_omap_match[] = {
1508 { .compatible = "ti,omap2420-mmc", },
1509 { },
1510};
1511#endif
1512
1515static struct platform_driver mmc_omap_driver = { 1513static struct platform_driver mmc_omap_driver = {
1516 .probe = mmc_omap_probe, 1514 .probe = mmc_omap_probe,
1517 .remove = mmc_omap_remove, 1515 .remove = mmc_omap_remove,
1518 .driver = { 1516 .driver = {
1519 .name = DRIVER_NAME, 1517 .name = DRIVER_NAME,
1520 .owner = THIS_MODULE, 1518 .owner = THIS_MODULE,
1519 .of_match_table = of_match_ptr(mmc_omap_match),
1521 }, 1520 },
1522}; 1521};
1523 1522
diff --git a/drivers/net/bonding/bond_main.c b/drivers/net/bonding/bond_main.c
index 4dd5ee2a34cc..36eab0c4fb33 100644
--- a/drivers/net/bonding/bond_main.c
+++ b/drivers/net/bonding/bond_main.c
@@ -4110,7 +4110,7 @@ static int bond_check_params(struct bond_params *params)
4110 if (!miimon) { 4110 if (!miimon) {
4111 pr_warning("Warning: miimon must be specified, otherwise bonding will not detect link failure, speed and duplex which are essential for 802.3ad operation\n"); 4111 pr_warning("Warning: miimon must be specified, otherwise bonding will not detect link failure, speed and duplex which are essential for 802.3ad operation\n");
4112 pr_warning("Forcing miimon to 100msec\n"); 4112 pr_warning("Forcing miimon to 100msec\n");
4113 miimon = 100; 4113 miimon = BOND_DEFAULT_MIIMON;
4114 } 4114 }
4115 } 4115 }
4116 4116
@@ -4147,7 +4147,7 @@ static int bond_check_params(struct bond_params *params)
4147 if (!miimon) { 4147 if (!miimon) {
4148 pr_warning("Warning: miimon must be specified, otherwise bonding will not detect link failure and link speed which are essential for TLB/ALB load balancing\n"); 4148 pr_warning("Warning: miimon must be specified, otherwise bonding will not detect link failure and link speed which are essential for TLB/ALB load balancing\n");
4149 pr_warning("Forcing miimon to 100msec\n"); 4149 pr_warning("Forcing miimon to 100msec\n");
4150 miimon = 100; 4150 miimon = BOND_DEFAULT_MIIMON;
4151 } 4151 }
4152 } 4152 }
4153 4153
diff --git a/drivers/net/bonding/bond_options.c b/drivers/net/bonding/bond_options.c
index 9a5223c7b4d1..ea6f640782b7 100644
--- a/drivers/net/bonding/bond_options.c
+++ b/drivers/net/bonding/bond_options.c
@@ -45,10 +45,15 @@ int bond_option_mode_set(struct bonding *bond, int mode)
45 return -EPERM; 45 return -EPERM;
46 } 46 }
47 47
48 if (BOND_MODE_IS_LB(mode) && bond->params.arp_interval) { 48 if (BOND_NO_USES_ARP(mode) && bond->params.arp_interval) {
49 pr_err("%s: %s mode is incompatible with arp monitoring.\n", 49 pr_info("%s: %s mode is incompatible with arp monitoring, start mii monitoring\n",
50 bond->dev->name, bond_mode_tbl[mode].modename); 50 bond->dev->name, bond_mode_tbl[mode].modename);
51 return -EINVAL; 51 /* disable arp monitoring */
52 bond->params.arp_interval = 0;
53 /* set miimon to default value */
54 bond->params.miimon = BOND_DEFAULT_MIIMON;
55 pr_info("%s: Setting MII monitoring interval to %d.\n",
56 bond->dev->name, bond->params.miimon);
52 } 57 }
53 58
54 /* don't cache arp_validate between modes */ 59 /* don't cache arp_validate between modes */
diff --git a/drivers/net/bonding/bond_sysfs.c b/drivers/net/bonding/bond_sysfs.c
index 0ec2a7e8c8a9..abf5e106edc5 100644
--- a/drivers/net/bonding/bond_sysfs.c
+++ b/drivers/net/bonding/bond_sysfs.c
@@ -523,9 +523,7 @@ static ssize_t bonding_store_arp_interval(struct device *d,
523 ret = -EINVAL; 523 ret = -EINVAL;
524 goto out; 524 goto out;
525 } 525 }
526 if (bond->params.mode == BOND_MODE_ALB || 526 if (BOND_NO_USES_ARP(bond->params.mode)) {
527 bond->params.mode == BOND_MODE_TLB ||
528 bond->params.mode == BOND_MODE_8023AD) {
529 pr_info("%s: ARP monitoring cannot be used with ALB/TLB/802.3ad. Only MII monitoring is supported on %s.\n", 527 pr_info("%s: ARP monitoring cannot be used with ALB/TLB/802.3ad. Only MII monitoring is supported on %s.\n",
530 bond->dev->name, bond->dev->name); 528 bond->dev->name, bond->dev->name);
531 ret = -EINVAL; 529 ret = -EINVAL;
diff --git a/drivers/net/bonding/bonding.h b/drivers/net/bonding/bonding.h
index ca31286aa028..a9f4f9f4d8ce 100644
--- a/drivers/net/bonding/bonding.h
+++ b/drivers/net/bonding/bonding.h
@@ -35,6 +35,8 @@
35 35
36#define BOND_MAX_ARP_TARGETS 16 36#define BOND_MAX_ARP_TARGETS 16
37 37
38#define BOND_DEFAULT_MIIMON 100
39
38#define IS_UP(dev) \ 40#define IS_UP(dev) \
39 ((((dev)->flags & IFF_UP) == IFF_UP) && \ 41 ((((dev)->flags & IFF_UP) == IFF_UP) && \
40 netif_running(dev) && \ 42 netif_running(dev) && \
@@ -55,6 +57,11 @@
55 ((mode) == BOND_MODE_TLB) || \ 57 ((mode) == BOND_MODE_TLB) || \
56 ((mode) == BOND_MODE_ALB)) 58 ((mode) == BOND_MODE_ALB))
57 59
60#define BOND_NO_USES_ARP(mode) \
61 (((mode) == BOND_MODE_8023AD) || \
62 ((mode) == BOND_MODE_TLB) || \
63 ((mode) == BOND_MODE_ALB))
64
58#define TX_QUEUE_OVERRIDE(mode) \ 65#define TX_QUEUE_OVERRIDE(mode) \
59 (((mode) == BOND_MODE_ACTIVEBACKUP) || \ 66 (((mode) == BOND_MODE_ACTIVEBACKUP) || \
60 ((mode) == BOND_MODE_ROUNDROBIN)) 67 ((mode) == BOND_MODE_ROUNDROBIN))
diff --git a/drivers/net/can/c_can/c_can.c b/drivers/net/can/c_can/c_can.c
index e3fc07cf2f62..77061eebb034 100644
--- a/drivers/net/can/c_can/c_can.c
+++ b/drivers/net/can/c_can/c_can.c
@@ -712,22 +712,31 @@ static int c_can_set_mode(struct net_device *dev, enum can_mode mode)
712 return 0; 712 return 0;
713} 713}
714 714
715static int c_can_get_berr_counter(const struct net_device *dev, 715static int __c_can_get_berr_counter(const struct net_device *dev,
716 struct can_berr_counter *bec) 716 struct can_berr_counter *bec)
717{ 717{
718 unsigned int reg_err_counter; 718 unsigned int reg_err_counter;
719 struct c_can_priv *priv = netdev_priv(dev); 719 struct c_can_priv *priv = netdev_priv(dev);
720 720
721 c_can_pm_runtime_get_sync(priv);
722
723 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG); 721 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG);
724 bec->rxerr = (reg_err_counter & ERR_CNT_REC_MASK) >> 722 bec->rxerr = (reg_err_counter & ERR_CNT_REC_MASK) >>
725 ERR_CNT_REC_SHIFT; 723 ERR_CNT_REC_SHIFT;
726 bec->txerr = reg_err_counter & ERR_CNT_TEC_MASK; 724 bec->txerr = reg_err_counter & ERR_CNT_TEC_MASK;
727 725
726 return 0;
727}
728
729static int c_can_get_berr_counter(const struct net_device *dev,
730 struct can_berr_counter *bec)
731{
732 struct c_can_priv *priv = netdev_priv(dev);
733 int err;
734
735 c_can_pm_runtime_get_sync(priv);
736 err = __c_can_get_berr_counter(dev, bec);
728 c_can_pm_runtime_put_sync(priv); 737 c_can_pm_runtime_put_sync(priv);
729 738
730 return 0; 739 return err;
731} 740}
732 741
733/* 742/*
@@ -754,6 +763,7 @@ static void c_can_do_tx(struct net_device *dev)
754 if (!(val & (1 << (msg_obj_no - 1)))) { 763 if (!(val & (1 << (msg_obj_no - 1)))) {
755 can_get_echo_skb(dev, 764 can_get_echo_skb(dev,
756 msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST); 765 msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST);
766 c_can_object_get(dev, 0, msg_obj_no, IF_COMM_ALL);
757 stats->tx_bytes += priv->read_reg(priv, 767 stats->tx_bytes += priv->read_reg(priv,
758 C_CAN_IFACE(MSGCTRL_REG, 0)) 768 C_CAN_IFACE(MSGCTRL_REG, 0))
759 & IF_MCONT_DLC_MASK; 769 & IF_MCONT_DLC_MASK;
@@ -872,7 +882,7 @@ static int c_can_handle_state_change(struct net_device *dev,
872 if (unlikely(!skb)) 882 if (unlikely(!skb))
873 return 0; 883 return 0;
874 884
875 c_can_get_berr_counter(dev, &bec); 885 __c_can_get_berr_counter(dev, &bec);
876 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG); 886 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG);
877 rx_err_passive = (reg_err_counter & ERR_CNT_RP_MASK) >> 887 rx_err_passive = (reg_err_counter & ERR_CNT_RP_MASK) >>
878 ERR_CNT_RP_SHIFT; 888 ERR_CNT_RP_SHIFT;
diff --git a/drivers/net/can/flexcan.c b/drivers/net/can/flexcan.c
index ae08cf129ebb..aaed97bee471 100644
--- a/drivers/net/can/flexcan.c
+++ b/drivers/net/can/flexcan.c
@@ -1020,13 +1020,13 @@ static int flexcan_probe(struct platform_device *pdev)
1020 dev_err(&pdev->dev, "no ipg clock defined\n"); 1020 dev_err(&pdev->dev, "no ipg clock defined\n");
1021 return PTR_ERR(clk_ipg); 1021 return PTR_ERR(clk_ipg);
1022 } 1022 }
1023 clock_freq = clk_get_rate(clk_ipg);
1024 1023
1025 clk_per = devm_clk_get(&pdev->dev, "per"); 1024 clk_per = devm_clk_get(&pdev->dev, "per");
1026 if (IS_ERR(clk_per)) { 1025 if (IS_ERR(clk_per)) {
1027 dev_err(&pdev->dev, "no per clock defined\n"); 1026 dev_err(&pdev->dev, "no per clock defined\n");
1028 return PTR_ERR(clk_per); 1027 return PTR_ERR(clk_per);
1029 } 1028 }
1029 clock_freq = clk_get_rate(clk_per);
1030 } 1030 }
1031 1031
1032 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1032 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
diff --git a/drivers/net/can/sja1000/sja1000.c b/drivers/net/can/sja1000/sja1000.c
index 7164a999f50f..f17c3018b7c7 100644
--- a/drivers/net/can/sja1000/sja1000.c
+++ b/drivers/net/can/sja1000/sja1000.c
@@ -494,20 +494,20 @@ irqreturn_t sja1000_interrupt(int irq, void *dev_id)
494 uint8_t isrc, status; 494 uint8_t isrc, status;
495 int n = 0; 495 int n = 0;
496 496
497 /* Shared interrupts and IRQ off? */
498 if (priv->read_reg(priv, SJA1000_IER) == IRQ_OFF)
499 return IRQ_NONE;
500
501 if (priv->pre_irq) 497 if (priv->pre_irq)
502 priv->pre_irq(priv); 498 priv->pre_irq(priv);
503 499
500 /* Shared interrupts and IRQ off? */
501 if (priv->read_reg(priv, SJA1000_IER) == IRQ_OFF)
502 goto out;
503
504 while ((isrc = priv->read_reg(priv, SJA1000_IR)) && 504 while ((isrc = priv->read_reg(priv, SJA1000_IR)) &&
505 (n < SJA1000_MAX_IRQ)) { 505 (n < SJA1000_MAX_IRQ)) {
506 n++; 506
507 status = priv->read_reg(priv, SJA1000_SR); 507 status = priv->read_reg(priv, SJA1000_SR);
508 /* check for absent controller due to hw unplug */ 508 /* check for absent controller due to hw unplug */
509 if (status == 0xFF && sja1000_is_absent(priv)) 509 if (status == 0xFF && sja1000_is_absent(priv))
510 return IRQ_NONE; 510 goto out;
511 511
512 if (isrc & IRQ_WUI) 512 if (isrc & IRQ_WUI)
513 netdev_warn(dev, "wakeup interrupt\n"); 513 netdev_warn(dev, "wakeup interrupt\n");
@@ -535,7 +535,7 @@ irqreturn_t sja1000_interrupt(int irq, void *dev_id)
535 status = priv->read_reg(priv, SJA1000_SR); 535 status = priv->read_reg(priv, SJA1000_SR);
536 /* check for absent controller */ 536 /* check for absent controller */
537 if (status == 0xFF && sja1000_is_absent(priv)) 537 if (status == 0xFF && sja1000_is_absent(priv))
538 return IRQ_NONE; 538 goto out;
539 } 539 }
540 } 540 }
541 if (isrc & (IRQ_DOI | IRQ_EI | IRQ_BEI | IRQ_EPI | IRQ_ALI)) { 541 if (isrc & (IRQ_DOI | IRQ_EI | IRQ_BEI | IRQ_EPI | IRQ_ALI)) {
@@ -543,8 +543,9 @@ irqreturn_t sja1000_interrupt(int irq, void *dev_id)
543 if (sja1000_err(dev, isrc, status)) 543 if (sja1000_err(dev, isrc, status))
544 break; 544 break;
545 } 545 }
546 n++;
546 } 547 }
547 548out:
548 if (priv->post_irq) 549 if (priv->post_irq)
549 priv->post_irq(priv); 550 priv->post_irq(priv);
550 551
diff --git a/drivers/net/ethernet/broadcom/tg3.c b/drivers/net/ethernet/broadcom/tg3.c
index a9e068423ba0..369b736dde05 100644
--- a/drivers/net/ethernet/broadcom/tg3.c
+++ b/drivers/net/ethernet/broadcom/tg3.c
@@ -10629,10 +10629,8 @@ static void tg3_sd_scan_scratchpad(struct tg3 *tp, struct tg3_ocir *ocir)
10629static ssize_t tg3_show_temp(struct device *dev, 10629static ssize_t tg3_show_temp(struct device *dev,
10630 struct device_attribute *devattr, char *buf) 10630 struct device_attribute *devattr, char *buf)
10631{ 10631{
10632 struct pci_dev *pdev = to_pci_dev(dev);
10633 struct net_device *netdev = pci_get_drvdata(pdev);
10634 struct tg3 *tp = netdev_priv(netdev);
10635 struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); 10632 struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
10633 struct tg3 *tp = dev_get_drvdata(dev);
10636 u32 temperature; 10634 u32 temperature;
10637 10635
10638 spin_lock_bh(&tp->lock); 10636 spin_lock_bh(&tp->lock);
@@ -10650,29 +10648,25 @@ static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, tg3_show_temp, NULL,
10650static SENSOR_DEVICE_ATTR(temp1_max, S_IRUGO, tg3_show_temp, NULL, 10648static SENSOR_DEVICE_ATTR(temp1_max, S_IRUGO, tg3_show_temp, NULL,
10651 TG3_TEMP_MAX_OFFSET); 10649 TG3_TEMP_MAX_OFFSET);
10652 10650
10653static struct attribute *tg3_attributes[] = { 10651static struct attribute *tg3_attrs[] = {
10654 &sensor_dev_attr_temp1_input.dev_attr.attr, 10652 &sensor_dev_attr_temp1_input.dev_attr.attr,
10655 &sensor_dev_attr_temp1_crit.dev_attr.attr, 10653 &sensor_dev_attr_temp1_crit.dev_attr.attr,
10656 &sensor_dev_attr_temp1_max.dev_attr.attr, 10654 &sensor_dev_attr_temp1_max.dev_attr.attr,
10657 NULL 10655 NULL
10658}; 10656};
10659 10657ATTRIBUTE_GROUPS(tg3);
10660static const struct attribute_group tg3_group = {
10661 .attrs = tg3_attributes,
10662};
10663 10658
10664static void tg3_hwmon_close(struct tg3 *tp) 10659static void tg3_hwmon_close(struct tg3 *tp)
10665{ 10660{
10666 if (tp->hwmon_dev) { 10661 if (tp->hwmon_dev) {
10667 hwmon_device_unregister(tp->hwmon_dev); 10662 hwmon_device_unregister(tp->hwmon_dev);
10668 tp->hwmon_dev = NULL; 10663 tp->hwmon_dev = NULL;
10669 sysfs_remove_group(&tp->pdev->dev.kobj, &tg3_group);
10670 } 10664 }
10671} 10665}
10672 10666
10673static void tg3_hwmon_open(struct tg3 *tp) 10667static void tg3_hwmon_open(struct tg3 *tp)
10674{ 10668{
10675 int i, err; 10669 int i;
10676 u32 size = 0; 10670 u32 size = 0;
10677 struct pci_dev *pdev = tp->pdev; 10671 struct pci_dev *pdev = tp->pdev;
10678 struct tg3_ocir ocirs[TG3_SD_NUM_RECS]; 10672 struct tg3_ocir ocirs[TG3_SD_NUM_RECS];
@@ -10690,18 +10684,11 @@ static void tg3_hwmon_open(struct tg3 *tp)
10690 if (!size) 10684 if (!size)
10691 return; 10685 return;
10692 10686
10693 /* Register hwmon sysfs hooks */ 10687 tp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev, "tg3",
10694 err = sysfs_create_group(&pdev->dev.kobj, &tg3_group); 10688 tp, tg3_groups);
10695 if (err) {
10696 dev_err(&pdev->dev, "Cannot create sysfs group, aborting\n");
10697 return;
10698 }
10699
10700 tp->hwmon_dev = hwmon_device_register(&pdev->dev);
10701 if (IS_ERR(tp->hwmon_dev)) { 10689 if (IS_ERR(tp->hwmon_dev)) {
10702 tp->hwmon_dev = NULL; 10690 tp->hwmon_dev = NULL;
10703 dev_err(&pdev->dev, "Cannot register hwmon device, aborting\n"); 10691 dev_err(&pdev->dev, "Cannot register hwmon device, aborting\n");
10704 sysfs_remove_group(&pdev->dev.kobj, &tg3_group);
10705 } 10692 }
10706} 10693}
10707 10694
diff --git a/drivers/net/ethernet/emulex/benet/be.h b/drivers/net/ethernet/emulex/benet/be.h
index f4825db5d179..5878df619b53 100644
--- a/drivers/net/ethernet/emulex/benet/be.h
+++ b/drivers/net/ethernet/emulex/benet/be.h
@@ -503,6 +503,7 @@ struct be_adapter {
503}; 503};
504 504
505#define be_physfn(adapter) (!adapter->virtfn) 505#define be_physfn(adapter) (!adapter->virtfn)
506#define be_virtfn(adapter) (adapter->virtfn)
506#define sriov_enabled(adapter) (adapter->num_vfs > 0) 507#define sriov_enabled(adapter) (adapter->num_vfs > 0)
507#define sriov_want(adapter) (be_physfn(adapter) && \ 508#define sriov_want(adapter) (be_physfn(adapter) && \
508 (num_vfs || pci_num_vf(adapter->pdev))) 509 (num_vfs || pci_num_vf(adapter->pdev)))
diff --git a/drivers/net/ethernet/emulex/benet/be_cmds.c b/drivers/net/ethernet/emulex/benet/be_cmds.c
index dbcd5262c016..e0e8bc1ef14c 100644
--- a/drivers/net/ethernet/emulex/benet/be_cmds.c
+++ b/drivers/net/ethernet/emulex/benet/be_cmds.c
@@ -1032,6 +1032,13 @@ int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq,
1032 } else { 1032 } else {
1033 req->hdr.version = 2; 1033 req->hdr.version = 2;
1034 req->page_size = 1; /* 1 for 4K */ 1034 req->page_size = 1; /* 1 for 4K */
1035
1036 /* coalesce-wm field in this cmd is not relevant to Lancer.
1037 * Lancer uses COMMON_MODIFY_CQ to set this field
1038 */
1039 if (!lancer_chip(adapter))
1040 AMAP_SET_BITS(struct amap_cq_context_v2, coalescwm,
1041 ctxt, coalesce_wm);
1035 AMAP_SET_BITS(struct amap_cq_context_v2, nodelay, ctxt, 1042 AMAP_SET_BITS(struct amap_cq_context_v2, nodelay, ctxt,
1036 no_delay); 1043 no_delay);
1037 AMAP_SET_BITS(struct amap_cq_context_v2, count, ctxt, 1044 AMAP_SET_BITS(struct amap_cq_context_v2, count, ctxt,
diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c
index abde97471636..fee64bf10446 100644
--- a/drivers/net/ethernet/emulex/benet/be_main.c
+++ b/drivers/net/ethernet/emulex/benet/be_main.c
@@ -2658,8 +2658,8 @@ static int be_close(struct net_device *netdev)
2658 2658
2659 be_roce_dev_close(adapter); 2659 be_roce_dev_close(adapter);
2660 2660
2661 for_all_evt_queues(adapter, eqo, i) { 2661 if (adapter->flags & BE_FLAGS_NAPI_ENABLED) {
2662 if (adapter->flags & BE_FLAGS_NAPI_ENABLED) { 2662 for_all_evt_queues(adapter, eqo, i) {
2663 napi_disable(&eqo->napi); 2663 napi_disable(&eqo->napi);
2664 be_disable_busy_poll(eqo); 2664 be_disable_busy_poll(eqo);
2665 } 2665 }
@@ -3253,12 +3253,10 @@ static int be_mac_setup(struct be_adapter *adapter)
3253 memcpy(mac, adapter->netdev->dev_addr, ETH_ALEN); 3253 memcpy(mac, adapter->netdev->dev_addr, ETH_ALEN);
3254 } 3254 }
3255 3255
3256 /* On BE3 VFs this cmd may fail due to lack of privilege. 3256 /* For BE3-R VFs, the PF programs the initial MAC address */
3257 * Ignore the failure as in this case pmac_id is fetched 3257 if (!(BEx_chip(adapter) && be_virtfn(adapter)))
3258 * in the IFACE_CREATE cmd. 3258 be_cmd_pmac_add(adapter, mac, adapter->if_handle,
3259 */ 3259 &adapter->pmac_id[0], 0);
3260 be_cmd_pmac_add(adapter, mac, adapter->if_handle,
3261 &adapter->pmac_id[0], 0);
3262 return 0; 3260 return 0;
3263} 3261}
3264 3262
@@ -4599,6 +4597,7 @@ static int be_suspend(struct pci_dev *pdev, pm_message_t state)
4599 if (adapter->wol) 4597 if (adapter->wol)
4600 be_setup_wol(adapter, true); 4598 be_setup_wol(adapter, true);
4601 4599
4600 be_intr_set(adapter, false);
4602 cancel_delayed_work_sync(&adapter->func_recovery_work); 4601 cancel_delayed_work_sync(&adapter->func_recovery_work);
4603 4602
4604 netif_device_detach(netdev); 4603 netif_device_detach(netdev);
@@ -4634,6 +4633,7 @@ static int be_resume(struct pci_dev *pdev)
4634 if (status) 4633 if (status)
4635 return status; 4634 return status;
4636 4635
4636 be_intr_set(adapter, true);
4637 /* tell fw we're ready to fire cmds */ 4637 /* tell fw we're ready to fire cmds */
4638 status = be_cmd_fw_init(adapter); 4638 status = be_cmd_fw_init(adapter);
4639 if (status) 4639 if (status)
diff --git a/drivers/net/ethernet/intel/e1000/e1000.h b/drivers/net/ethernet/intel/e1000/e1000.h
index 58c147271a36..f9313b36c887 100644
--- a/drivers/net/ethernet/intel/e1000/e1000.h
+++ b/drivers/net/ethernet/intel/e1000/e1000.h
@@ -83,6 +83,11 @@ struct e1000_adapter;
83 83
84#define E1000_MAX_INTR 10 84#define E1000_MAX_INTR 10
85 85
86/*
87 * Count for polling __E1000_RESET condition every 10-20msec.
88 */
89#define E1000_CHECK_RESET_COUNT 50
90
86/* TX/RX descriptor defines */ 91/* TX/RX descriptor defines */
87#define E1000_DEFAULT_TXD 256 92#define E1000_DEFAULT_TXD 256
88#define E1000_MAX_TXD 256 93#define E1000_MAX_TXD 256
@@ -312,8 +317,6 @@ struct e1000_adapter {
312 struct delayed_work watchdog_task; 317 struct delayed_work watchdog_task;
313 struct delayed_work fifo_stall_task; 318 struct delayed_work fifo_stall_task;
314 struct delayed_work phy_info_task; 319 struct delayed_work phy_info_task;
315
316 struct mutex mutex;
317}; 320};
318 321
319enum e1000_state_t { 322enum e1000_state_t {
diff --git a/drivers/net/ethernet/intel/e1000/e1000_main.c b/drivers/net/ethernet/intel/e1000/e1000_main.c
index e38622825fa7..46e6544ed1b7 100644
--- a/drivers/net/ethernet/intel/e1000/e1000_main.c
+++ b/drivers/net/ethernet/intel/e1000/e1000_main.c
@@ -494,13 +494,20 @@ static void e1000_down_and_stop(struct e1000_adapter *adapter)
494{ 494{
495 set_bit(__E1000_DOWN, &adapter->flags); 495 set_bit(__E1000_DOWN, &adapter->flags);
496 496
497 /* Only kill reset task if adapter is not resetting */
498 if (!test_bit(__E1000_RESETTING, &adapter->flags))
499 cancel_work_sync(&adapter->reset_task);
500
501 cancel_delayed_work_sync(&adapter->watchdog_task); 497 cancel_delayed_work_sync(&adapter->watchdog_task);
498
499 /*
500 * Since the watchdog task can reschedule other tasks, we should cancel
501 * it first, otherwise we can run into the situation when a work is
502 * still running after the adapter has been turned down.
503 */
504
502 cancel_delayed_work_sync(&adapter->phy_info_task); 505 cancel_delayed_work_sync(&adapter->phy_info_task);
503 cancel_delayed_work_sync(&adapter->fifo_stall_task); 506 cancel_delayed_work_sync(&adapter->fifo_stall_task);
507
508 /* Only kill reset task if adapter is not resetting */
509 if (!test_bit(__E1000_RESETTING, &adapter->flags))
510 cancel_work_sync(&adapter->reset_task);
504} 511}
505 512
506void e1000_down(struct e1000_adapter *adapter) 513void e1000_down(struct e1000_adapter *adapter)
@@ -544,21 +551,8 @@ void e1000_down(struct e1000_adapter *adapter)
544 e1000_clean_all_rx_rings(adapter); 551 e1000_clean_all_rx_rings(adapter);
545} 552}
546 553
547static void e1000_reinit_safe(struct e1000_adapter *adapter)
548{
549 while (test_and_set_bit(__E1000_RESETTING, &adapter->flags))
550 msleep(1);
551 mutex_lock(&adapter->mutex);
552 e1000_down(adapter);
553 e1000_up(adapter);
554 mutex_unlock(&adapter->mutex);
555 clear_bit(__E1000_RESETTING, &adapter->flags);
556}
557
558void e1000_reinit_locked(struct e1000_adapter *adapter) 554void e1000_reinit_locked(struct e1000_adapter *adapter)
559{ 555{
560 /* if rtnl_lock is not held the call path is bogus */
561 ASSERT_RTNL();
562 WARN_ON(in_interrupt()); 556 WARN_ON(in_interrupt());
563 while (test_and_set_bit(__E1000_RESETTING, &adapter->flags)) 557 while (test_and_set_bit(__E1000_RESETTING, &adapter->flags))
564 msleep(1); 558 msleep(1);
@@ -1316,7 +1310,6 @@ static int e1000_sw_init(struct e1000_adapter *adapter)
1316 e1000_irq_disable(adapter); 1310 e1000_irq_disable(adapter);
1317 1311
1318 spin_lock_init(&adapter->stats_lock); 1312 spin_lock_init(&adapter->stats_lock);
1319 mutex_init(&adapter->mutex);
1320 1313
1321 set_bit(__E1000_DOWN, &adapter->flags); 1314 set_bit(__E1000_DOWN, &adapter->flags);
1322 1315
@@ -1440,6 +1433,10 @@ static int e1000_close(struct net_device *netdev)
1440{ 1433{
1441 struct e1000_adapter *adapter = netdev_priv(netdev); 1434 struct e1000_adapter *adapter = netdev_priv(netdev);
1442 struct e1000_hw *hw = &adapter->hw; 1435 struct e1000_hw *hw = &adapter->hw;
1436 int count = E1000_CHECK_RESET_COUNT;
1437
1438 while (test_bit(__E1000_RESETTING, &adapter->flags) && count--)
1439 usleep_range(10000, 20000);
1443 1440
1444 WARN_ON(test_bit(__E1000_RESETTING, &adapter->flags)); 1441 WARN_ON(test_bit(__E1000_RESETTING, &adapter->flags));
1445 e1000_down(adapter); 1442 e1000_down(adapter);
@@ -2325,11 +2322,8 @@ static void e1000_update_phy_info_task(struct work_struct *work)
2325 struct e1000_adapter *adapter = container_of(work, 2322 struct e1000_adapter *adapter = container_of(work,
2326 struct e1000_adapter, 2323 struct e1000_adapter,
2327 phy_info_task.work); 2324 phy_info_task.work);
2328 if (test_bit(__E1000_DOWN, &adapter->flags)) 2325
2329 return;
2330 mutex_lock(&adapter->mutex);
2331 e1000_phy_get_info(&adapter->hw, &adapter->phy_info); 2326 e1000_phy_get_info(&adapter->hw, &adapter->phy_info);
2332 mutex_unlock(&adapter->mutex);
2333} 2327}
2334 2328
2335/** 2329/**
@@ -2345,9 +2339,6 @@ static void e1000_82547_tx_fifo_stall_task(struct work_struct *work)
2345 struct net_device *netdev = adapter->netdev; 2339 struct net_device *netdev = adapter->netdev;
2346 u32 tctl; 2340 u32 tctl;
2347 2341
2348 if (test_bit(__E1000_DOWN, &adapter->flags))
2349 return;
2350 mutex_lock(&adapter->mutex);
2351 if (atomic_read(&adapter->tx_fifo_stall)) { 2342 if (atomic_read(&adapter->tx_fifo_stall)) {
2352 if ((er32(TDT) == er32(TDH)) && 2343 if ((er32(TDT) == er32(TDH)) &&
2353 (er32(TDFT) == er32(TDFH)) && 2344 (er32(TDFT) == er32(TDFH)) &&
@@ -2368,7 +2359,6 @@ static void e1000_82547_tx_fifo_stall_task(struct work_struct *work)
2368 schedule_delayed_work(&adapter->fifo_stall_task, 1); 2359 schedule_delayed_work(&adapter->fifo_stall_task, 1);
2369 } 2360 }
2370 } 2361 }
2371 mutex_unlock(&adapter->mutex);
2372} 2362}
2373 2363
2374bool e1000_has_link(struct e1000_adapter *adapter) 2364bool e1000_has_link(struct e1000_adapter *adapter)
@@ -2422,10 +2412,6 @@ static void e1000_watchdog(struct work_struct *work)
2422 struct e1000_tx_ring *txdr = adapter->tx_ring; 2412 struct e1000_tx_ring *txdr = adapter->tx_ring;
2423 u32 link, tctl; 2413 u32 link, tctl;
2424 2414
2425 if (test_bit(__E1000_DOWN, &adapter->flags))
2426 return;
2427
2428 mutex_lock(&adapter->mutex);
2429 link = e1000_has_link(adapter); 2415 link = e1000_has_link(adapter);
2430 if ((netif_carrier_ok(netdev)) && link) 2416 if ((netif_carrier_ok(netdev)) && link)
2431 goto link_up; 2417 goto link_up;
@@ -2516,7 +2502,7 @@ link_up:
2516 adapter->tx_timeout_count++; 2502 adapter->tx_timeout_count++;
2517 schedule_work(&adapter->reset_task); 2503 schedule_work(&adapter->reset_task);
2518 /* exit immediately since reset is imminent */ 2504 /* exit immediately since reset is imminent */
2519 goto unlock; 2505 return;
2520 } 2506 }
2521 } 2507 }
2522 2508
@@ -2544,9 +2530,6 @@ link_up:
2544 /* Reschedule the task */ 2530 /* Reschedule the task */
2545 if (!test_bit(__E1000_DOWN, &adapter->flags)) 2531 if (!test_bit(__E1000_DOWN, &adapter->flags))
2546 schedule_delayed_work(&adapter->watchdog_task, 2 * HZ); 2532 schedule_delayed_work(&adapter->watchdog_task, 2 * HZ);
2547
2548unlock:
2549 mutex_unlock(&adapter->mutex);
2550} 2533}
2551 2534
2552enum latency_range { 2535enum latency_range {
@@ -3495,10 +3478,8 @@ static void e1000_reset_task(struct work_struct *work)
3495 struct e1000_adapter *adapter = 3478 struct e1000_adapter *adapter =
3496 container_of(work, struct e1000_adapter, reset_task); 3479 container_of(work, struct e1000_adapter, reset_task);
3497 3480
3498 if (test_bit(__E1000_DOWN, &adapter->flags))
3499 return;
3500 e_err(drv, "Reset adapter\n"); 3481 e_err(drv, "Reset adapter\n");
3501 e1000_reinit_safe(adapter); 3482 e1000_reinit_locked(adapter);
3502} 3483}
3503 3484
3504/** 3485/**
@@ -4963,6 +4944,11 @@ static int __e1000_shutdown(struct pci_dev *pdev, bool *enable_wake)
4963 netif_device_detach(netdev); 4944 netif_device_detach(netdev);
4964 4945
4965 if (netif_running(netdev)) { 4946 if (netif_running(netdev)) {
4947 int count = E1000_CHECK_RESET_COUNT;
4948
4949 while (test_bit(__E1000_RESETTING, &adapter->flags) && count--)
4950 usleep_range(10000, 20000);
4951
4966 WARN_ON(test_bit(__E1000_RESETTING, &adapter->flags)); 4952 WARN_ON(test_bit(__E1000_RESETTING, &adapter->flags));
4967 e1000_down(adapter); 4953 e1000_down(adapter);
4968 } 4954 }
diff --git a/drivers/net/ethernet/intel/igb/igb_ethtool.c b/drivers/net/ethernet/intel/igb/igb_ethtool.c
index b0f3666b1d7f..c3143da497c8 100644
--- a/drivers/net/ethernet/intel/igb/igb_ethtool.c
+++ b/drivers/net/ethernet/intel/igb/igb_ethtool.c
@@ -2062,14 +2062,15 @@ static void igb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2062{ 2062{
2063 struct igb_adapter *adapter = netdev_priv(netdev); 2063 struct igb_adapter *adapter = netdev_priv(netdev);
2064 2064
2065 wol->supported = WAKE_UCAST | WAKE_MCAST |
2066 WAKE_BCAST | WAKE_MAGIC |
2067 WAKE_PHY;
2068 wol->wolopts = 0; 2065 wol->wolopts = 0;
2069 2066
2070 if (!(adapter->flags & IGB_FLAG_WOL_SUPPORTED)) 2067 if (!(adapter->flags & IGB_FLAG_WOL_SUPPORTED))
2071 return; 2068 return;
2072 2069
2070 wol->supported = WAKE_UCAST | WAKE_MCAST |
2071 WAKE_BCAST | WAKE_MAGIC |
2072 WAKE_PHY;
2073
2073 /* apply any specific unsupported masks here */ 2074 /* apply any specific unsupported masks here */
2074 switch (adapter->hw.device_id) { 2075 switch (adapter->hw.device_id) {
2075 default: 2076 default:
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
index 0c55079ebee3..cc06854296a3 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
@@ -4251,8 +4251,8 @@ static void ixgbe_disable_fwd_ring(struct ixgbe_fwd_adapter *vadapter,
4251 rx_ring->l2_accel_priv = NULL; 4251 rx_ring->l2_accel_priv = NULL;
4252} 4252}
4253 4253
4254int ixgbe_fwd_ring_down(struct net_device *vdev, 4254static int ixgbe_fwd_ring_down(struct net_device *vdev,
4255 struct ixgbe_fwd_adapter *accel) 4255 struct ixgbe_fwd_adapter *accel)
4256{ 4256{
4257 struct ixgbe_adapter *adapter = accel->real_adapter; 4257 struct ixgbe_adapter *adapter = accel->real_adapter;
4258 unsigned int rxbase = accel->rx_base_queue; 4258 unsigned int rxbase = accel->rx_base_queue;
@@ -7986,10 +7986,9 @@ skip_sriov:
7986 NETIF_F_TSO | 7986 NETIF_F_TSO |
7987 NETIF_F_TSO6 | 7987 NETIF_F_TSO6 |
7988 NETIF_F_RXHASH | 7988 NETIF_F_RXHASH |
7989 NETIF_F_RXCSUM | 7989 NETIF_F_RXCSUM;
7990 NETIF_F_HW_L2FW_DOFFLOAD;
7991 7990
7992 netdev->hw_features = netdev->features; 7991 netdev->hw_features = netdev->features | NETIF_F_HW_L2FW_DOFFLOAD;
7993 7992
7994 switch (adapter->hw.mac.type) { 7993 switch (adapter->hw.mac.type) {
7995 case ixgbe_mac_82599EB: 7994 case ixgbe_mac_82599EB:
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c
index e4c676006be9..39217e5ff7dc 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c
@@ -46,6 +46,7 @@ static bool ixgbe_get_i2c_data(u32 *i2cctl);
46static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw); 46static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
47static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id); 47static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
48static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw); 48static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
49static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw);
49 50
50/** 51/**
51 * ixgbe_identify_phy_generic - Get physical layer module 52 * ixgbe_identify_phy_generic - Get physical layer module
@@ -1164,7 +1165,7 @@ err_read_i2c_eeprom:
1164 * 1165 *
1165 * Searches for and identifies the QSFP module and assigns appropriate PHY type 1166 * Searches for and identifies the QSFP module and assigns appropriate PHY type
1166 **/ 1167 **/
1167s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw) 1168static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1168{ 1169{
1169 struct ixgbe_adapter *adapter = hw->back; 1170 struct ixgbe_adapter *adapter = hw->back;
1170 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 1171 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h b/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h
index aae900a256da..fffcbdd2bf0e 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h
@@ -145,7 +145,6 @@ s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
145s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw); 145s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw);
146s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw); 146s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw);
147s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw); 147s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw);
148s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw);
149s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 148s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
150 u16 *list_offset, 149 u16 *list_offset,
151 u16 *data_offset); 150 u16 *data_offset);
diff --git a/drivers/net/ethernet/mellanox/mlx4/en_selftest.c b/drivers/net/ethernet/mellanox/mlx4/en_selftest.c
index 40626690e8a8..c11d063473e5 100644
--- a/drivers/net/ethernet/mellanox/mlx4/en_selftest.c
+++ b/drivers/net/ethernet/mellanox/mlx4/en_selftest.c
@@ -140,7 +140,6 @@ void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf)
140{ 140{
141 struct mlx4_en_priv *priv = netdev_priv(dev); 141 struct mlx4_en_priv *priv = netdev_priv(dev);
142 struct mlx4_en_dev *mdev = priv->mdev; 142 struct mlx4_en_dev *mdev = priv->mdev;
143 struct mlx4_en_tx_ring *tx_ring;
144 int i, carrier_ok; 143 int i, carrier_ok;
145 144
146 memset(buf, 0, sizeof(u64) * MLX4_EN_NUM_SELF_TEST); 145 memset(buf, 0, sizeof(u64) * MLX4_EN_NUM_SELF_TEST);
@@ -150,16 +149,10 @@ void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf)
150 carrier_ok = netif_carrier_ok(dev); 149 carrier_ok = netif_carrier_ok(dev);
151 150
152 netif_carrier_off(dev); 151 netif_carrier_off(dev);
153retry_tx:
154 /* Wait until all tx queues are empty. 152 /* Wait until all tx queues are empty.
155 * there should not be any additional incoming traffic 153 * there should not be any additional incoming traffic
156 * since we turned the carrier off */ 154 * since we turned the carrier off */
157 msleep(200); 155 msleep(200);
158 for (i = 0; i < priv->tx_ring_num && carrier_ok; i++) {
159 tx_ring = priv->tx_ring[i];
160 if (tx_ring->prod != (tx_ring->cons + tx_ring->last_nr_txbb))
161 goto retry_tx;
162 }
163 156
164 if (priv->mdev->dev->caps.flags & 157 if (priv->mdev->dev->caps.flags &
165 MLX4_DEV_CAP_FLAG_UC_LOOPBACK) { 158 MLX4_DEV_CAP_FLAG_UC_LOOPBACK) {
diff --git a/drivers/net/ethernet/realtek/8139cp.c b/drivers/net/ethernet/realtek/8139cp.c
index f2a2128165dd..737c1a881f78 100644
--- a/drivers/net/ethernet/realtek/8139cp.c
+++ b/drivers/net/ethernet/realtek/8139cp.c
@@ -678,9 +678,6 @@ static void cp_tx (struct cp_private *cp)
678 le32_to_cpu(txd->opts1) & 0xffff, 678 le32_to_cpu(txd->opts1) & 0xffff,
679 PCI_DMA_TODEVICE); 679 PCI_DMA_TODEVICE);
680 680
681 bytes_compl += skb->len;
682 pkts_compl++;
683
684 if (status & LastFrag) { 681 if (status & LastFrag) {
685 if (status & (TxError | TxFIFOUnder)) { 682 if (status & (TxError | TxFIFOUnder)) {
686 netif_dbg(cp, tx_err, cp->dev, 683 netif_dbg(cp, tx_err, cp->dev,
@@ -702,6 +699,8 @@ static void cp_tx (struct cp_private *cp)
702 netif_dbg(cp, tx_done, cp->dev, 699 netif_dbg(cp, tx_done, cp->dev,
703 "tx done, slot %d\n", tx_tail); 700 "tx done, slot %d\n", tx_tail);
704 } 701 }
702 bytes_compl += skb->len;
703 pkts_compl++;
705 dev_kfree_skb_irq(skb); 704 dev_kfree_skb_irq(skb);
706 } 705 }
707 706
diff --git a/drivers/net/ethernet/realtek/r8169.c b/drivers/net/ethernet/realtek/r8169.c
index 799387570766..c737f0ea5de7 100644
--- a/drivers/net/ethernet/realtek/r8169.c
+++ b/drivers/net/ethernet/realtek/r8169.c
@@ -3465,6 +3465,11 @@ static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3465 rtl_writephy(tp, 0x14, 0x9065); 3465 rtl_writephy(tp, 0x14, 0x9065);
3466 rtl_writephy(tp, 0x14, 0x1065); 3466 rtl_writephy(tp, 0x14, 0x1065);
3467 3467
3468 /* Check ALDPS bit, disable it if enabled */
3469 rtl_writephy(tp, 0x1f, 0x0a43);
3470 if (rtl_readphy(tp, 0x10) & 0x0004)
3471 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0004);
3472
3468 rtl_writephy(tp, 0x1f, 0x0000); 3473 rtl_writephy(tp, 0x1f, 0x0000);
3469} 3474}
3470 3475
diff --git a/drivers/net/ethernet/sfc/mcdi.h b/drivers/net/ethernet/sfc/mcdi.h
index 656a3277c2b2..15816cacb548 100644
--- a/drivers/net/ethernet/sfc/mcdi.h
+++ b/drivers/net/ethernet/sfc/mcdi.h
@@ -75,6 +75,8 @@ struct efx_mcdi_mon {
75 unsigned long last_update; 75 unsigned long last_update;
76 struct device *device; 76 struct device *device;
77 struct efx_mcdi_mon_attribute *attrs; 77 struct efx_mcdi_mon_attribute *attrs;
78 struct attribute_group group;
79 const struct attribute_group *groups[2];
78 unsigned int n_attrs; 80 unsigned int n_attrs;
79}; 81};
80 82
diff --git a/drivers/net/ethernet/sfc/mcdi_mon.c b/drivers/net/ethernet/sfc/mcdi_mon.c
index 4cc5d95b2a5a..d72ad4fc3617 100644
--- a/drivers/net/ethernet/sfc/mcdi_mon.c
+++ b/drivers/net/ethernet/sfc/mcdi_mon.c
@@ -139,17 +139,10 @@ static int efx_mcdi_mon_update(struct efx_nic *efx)
139 return rc; 139 return rc;
140} 140}
141 141
142static ssize_t efx_mcdi_mon_show_name(struct device *dev,
143 struct device_attribute *attr,
144 char *buf)
145{
146 return sprintf(buf, "%s\n", KBUILD_MODNAME);
147}
148
149static int efx_mcdi_mon_get_entry(struct device *dev, unsigned int index, 142static int efx_mcdi_mon_get_entry(struct device *dev, unsigned int index,
150 efx_dword_t *entry) 143 efx_dword_t *entry)
151{ 144{
152 struct efx_nic *efx = dev_get_drvdata(dev); 145 struct efx_nic *efx = dev_get_drvdata(dev->parent);
153 struct efx_mcdi_mon *hwmon = efx_mcdi_mon(efx); 146 struct efx_mcdi_mon *hwmon = efx_mcdi_mon(efx);
154 int rc; 147 int rc;
155 148
@@ -263,7 +256,7 @@ static ssize_t efx_mcdi_mon_show_label(struct device *dev,
263 efx_mcdi_sensor_type[mon_attr->type].label); 256 efx_mcdi_sensor_type[mon_attr->type].label);
264} 257}
265 258
266static int 259static void
267efx_mcdi_mon_add_attr(struct efx_nic *efx, const char *name, 260efx_mcdi_mon_add_attr(struct efx_nic *efx, const char *name,
268 ssize_t (*reader)(struct device *, 261 ssize_t (*reader)(struct device *,
269 struct device_attribute *, char *), 262 struct device_attribute *, char *),
@@ -272,7 +265,6 @@ efx_mcdi_mon_add_attr(struct efx_nic *efx, const char *name,
272{ 265{
273 struct efx_mcdi_mon *hwmon = efx_mcdi_mon(efx); 266 struct efx_mcdi_mon *hwmon = efx_mcdi_mon(efx);
274 struct efx_mcdi_mon_attribute *attr = &hwmon->attrs[hwmon->n_attrs]; 267 struct efx_mcdi_mon_attribute *attr = &hwmon->attrs[hwmon->n_attrs];
275 int rc;
276 268
277 strlcpy(attr->name, name, sizeof(attr->name)); 269 strlcpy(attr->name, name, sizeof(attr->name));
278 attr->index = index; 270 attr->index = index;
@@ -286,10 +278,7 @@ efx_mcdi_mon_add_attr(struct efx_nic *efx, const char *name,
286 attr->dev_attr.attr.name = attr->name; 278 attr->dev_attr.attr.name = attr->name;
287 attr->dev_attr.attr.mode = S_IRUGO; 279 attr->dev_attr.attr.mode = S_IRUGO;
288 attr->dev_attr.show = reader; 280 attr->dev_attr.show = reader;
289 rc = device_create_file(&efx->pci_dev->dev, &attr->dev_attr); 281 hwmon->group.attrs[hwmon->n_attrs++] = &attr->dev_attr.attr;
290 if (rc == 0)
291 ++hwmon->n_attrs;
292 return rc;
293} 282}
294 283
295int efx_mcdi_mon_probe(struct efx_nic *efx) 284int efx_mcdi_mon_probe(struct efx_nic *efx)
@@ -338,26 +327,22 @@ int efx_mcdi_mon_probe(struct efx_nic *efx)
338 efx_mcdi_mon_update(efx); 327 efx_mcdi_mon_update(efx);
339 328
340 /* Allocate space for the maximum possible number of 329 /* Allocate space for the maximum possible number of
341 * attributes for this set of sensors: name of the driver plus 330 * attributes for this set of sensors:
342 * value, min, max, crit, alarm and label for each sensor. 331 * value, min, max, crit, alarm and label for each sensor.
343 */ 332 */
344 n_attrs = 1 + 6 * n_sensors; 333 n_attrs = 6 * n_sensors;
345 hwmon->attrs = kcalloc(n_attrs, sizeof(*hwmon->attrs), GFP_KERNEL); 334 hwmon->attrs = kcalloc(n_attrs, sizeof(*hwmon->attrs), GFP_KERNEL);
346 if (!hwmon->attrs) { 335 if (!hwmon->attrs) {
347 rc = -ENOMEM; 336 rc = -ENOMEM;
348 goto fail; 337 goto fail;
349 } 338 }
350 339 hwmon->group.attrs = kcalloc(n_attrs + 1, sizeof(struct attribute *),
351 hwmon->device = hwmon_device_register(&efx->pci_dev->dev); 340 GFP_KERNEL);
352 if (IS_ERR(hwmon->device)) { 341 if (!hwmon->group.attrs) {
353 rc = PTR_ERR(hwmon->device); 342 rc = -ENOMEM;
354 goto fail; 343 goto fail;
355 } 344 }
356 345
357 rc = efx_mcdi_mon_add_attr(efx, "name", efx_mcdi_mon_show_name, 0, 0, 0);
358 if (rc)
359 goto fail;
360
361 for (i = 0, j = -1, type = -1; ; i++) { 346 for (i = 0, j = -1, type = -1; ; i++) {
362 enum efx_hwmon_type hwmon_type; 347 enum efx_hwmon_type hwmon_type;
363 const char *hwmon_prefix; 348 const char *hwmon_prefix;
@@ -372,7 +357,7 @@ int efx_mcdi_mon_probe(struct efx_nic *efx)
372 page = type / 32; 357 page = type / 32;
373 j = -1; 358 j = -1;
374 if (page == n_pages) 359 if (page == n_pages)
375 return 0; 360 goto hwmon_register;
376 361
377 MCDI_SET_DWORD(inbuf, SENSOR_INFO_EXT_IN_PAGE, 362 MCDI_SET_DWORD(inbuf, SENSOR_INFO_EXT_IN_PAGE,
378 page); 363 page);
@@ -453,28 +438,22 @@ int efx_mcdi_mon_probe(struct efx_nic *efx)
453 if (min1 != max1) { 438 if (min1 != max1) {
454 snprintf(name, sizeof(name), "%s%u_input", 439 snprintf(name, sizeof(name), "%s%u_input",
455 hwmon_prefix, hwmon_index); 440 hwmon_prefix, hwmon_index);
456 rc = efx_mcdi_mon_add_attr( 441 efx_mcdi_mon_add_attr(
457 efx, name, efx_mcdi_mon_show_value, i, type, 0); 442 efx, name, efx_mcdi_mon_show_value, i, type, 0);
458 if (rc)
459 goto fail;
460 443
461 if (hwmon_type != EFX_HWMON_POWER) { 444 if (hwmon_type != EFX_HWMON_POWER) {
462 snprintf(name, sizeof(name), "%s%u_min", 445 snprintf(name, sizeof(name), "%s%u_min",
463 hwmon_prefix, hwmon_index); 446 hwmon_prefix, hwmon_index);
464 rc = efx_mcdi_mon_add_attr( 447 efx_mcdi_mon_add_attr(
465 efx, name, efx_mcdi_mon_show_limit, 448 efx, name, efx_mcdi_mon_show_limit,
466 i, type, min1); 449 i, type, min1);
467 if (rc)
468 goto fail;
469 } 450 }
470 451
471 snprintf(name, sizeof(name), "%s%u_max", 452 snprintf(name, sizeof(name), "%s%u_max",
472 hwmon_prefix, hwmon_index); 453 hwmon_prefix, hwmon_index);
473 rc = efx_mcdi_mon_add_attr( 454 efx_mcdi_mon_add_attr(
474 efx, name, efx_mcdi_mon_show_limit, 455 efx, name, efx_mcdi_mon_show_limit,
475 i, type, max1); 456 i, type, max1);
476 if (rc)
477 goto fail;
478 457
479 if (min2 != max2) { 458 if (min2 != max2) {
480 /* Assume max2 is critical value. 459 /* Assume max2 is critical value.
@@ -482,32 +461,38 @@ int efx_mcdi_mon_probe(struct efx_nic *efx)
482 */ 461 */
483 snprintf(name, sizeof(name), "%s%u_crit", 462 snprintf(name, sizeof(name), "%s%u_crit",
484 hwmon_prefix, hwmon_index); 463 hwmon_prefix, hwmon_index);
485 rc = efx_mcdi_mon_add_attr( 464 efx_mcdi_mon_add_attr(
486 efx, name, efx_mcdi_mon_show_limit, 465 efx, name, efx_mcdi_mon_show_limit,
487 i, type, max2); 466 i, type, max2);
488 if (rc)
489 goto fail;
490 } 467 }
491 } 468 }
492 469
493 snprintf(name, sizeof(name), "%s%u_alarm", 470 snprintf(name, sizeof(name), "%s%u_alarm",
494 hwmon_prefix, hwmon_index); 471 hwmon_prefix, hwmon_index);
495 rc = efx_mcdi_mon_add_attr( 472 efx_mcdi_mon_add_attr(
496 efx, name, efx_mcdi_mon_show_alarm, i, type, 0); 473 efx, name, efx_mcdi_mon_show_alarm, i, type, 0);
497 if (rc)
498 goto fail;
499 474
500 if (type < ARRAY_SIZE(efx_mcdi_sensor_type) && 475 if (type < ARRAY_SIZE(efx_mcdi_sensor_type) &&
501 efx_mcdi_sensor_type[type].label) { 476 efx_mcdi_sensor_type[type].label) {
502 snprintf(name, sizeof(name), "%s%u_label", 477 snprintf(name, sizeof(name), "%s%u_label",
503 hwmon_prefix, hwmon_index); 478 hwmon_prefix, hwmon_index);
504 rc = efx_mcdi_mon_add_attr( 479 efx_mcdi_mon_add_attr(
505 efx, name, efx_mcdi_mon_show_label, i, type, 0); 480 efx, name, efx_mcdi_mon_show_label, i, type, 0);
506 if (rc)
507 goto fail;
508 } 481 }
509 } 482 }
510 483
484hwmon_register:
485 hwmon->groups[0] = &hwmon->group;
486 hwmon->device = hwmon_device_register_with_groups(&efx->pci_dev->dev,
487 KBUILD_MODNAME, NULL,
488 hwmon->groups);
489 if (IS_ERR(hwmon->device)) {
490 rc = PTR_ERR(hwmon->device);
491 goto fail;
492 }
493
494 return 0;
495
511fail: 496fail:
512 efx_mcdi_mon_remove(efx); 497 efx_mcdi_mon_remove(efx);
513 return rc; 498 return rc;
@@ -516,14 +501,11 @@ fail:
516void efx_mcdi_mon_remove(struct efx_nic *efx) 501void efx_mcdi_mon_remove(struct efx_nic *efx)
517{ 502{
518 struct efx_mcdi_mon *hwmon = efx_mcdi_mon(efx); 503 struct efx_mcdi_mon *hwmon = efx_mcdi_mon(efx);
519 unsigned int i;
520 504
521 for (i = 0; i < hwmon->n_attrs; i++)
522 device_remove_file(&efx->pci_dev->dev,
523 &hwmon->attrs[i].dev_attr);
524 kfree(hwmon->attrs);
525 if (hwmon->device) 505 if (hwmon->device)
526 hwmon_device_unregister(hwmon->device); 506 hwmon_device_unregister(hwmon->device);
507 kfree(hwmon->attrs);
508 kfree(hwmon->group.attrs);
527 efx_nic_free_buffer(efx, &hwmon->dma_buf); 509 efx_nic_free_buffer(efx, &hwmon->dma_buf);
528} 510}
529 511
diff --git a/drivers/net/ethernet/smsc/smc91x.h b/drivers/net/ethernet/smsc/smc91x.h
index c9d4c872e81d..749654b976bc 100644
--- a/drivers/net/ethernet/smsc/smc91x.h
+++ b/drivers/net/ethernet/smsc/smc91x.h
@@ -46,7 +46,8 @@
46 defined(CONFIG_MACH_LITTLETON) ||\ 46 defined(CONFIG_MACH_LITTLETON) ||\
47 defined(CONFIG_MACH_ZYLONITE2) ||\ 47 defined(CONFIG_MACH_ZYLONITE2) ||\
48 defined(CONFIG_ARCH_VIPER) ||\ 48 defined(CONFIG_ARCH_VIPER) ||\
49 defined(CONFIG_MACH_STARGATE2) 49 defined(CONFIG_MACH_STARGATE2) ||\
50 defined(CONFIG_ARCH_VERSATILE)
50 51
51#include <asm/mach-types.h> 52#include <asm/mach-types.h>
52 53
@@ -154,6 +155,8 @@ static inline void SMC_outw(u16 val, void __iomem *ioaddr, int reg)
154#define SMC_outl(v, a, r) writel(v, (a) + (r)) 155#define SMC_outl(v, a, r) writel(v, (a) + (r))
155#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) 156#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
156#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) 157#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
158#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
159#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
157#define SMC_IRQ_FLAGS (-1) /* from resource */ 160#define SMC_IRQ_FLAGS (-1) /* from resource */
158 161
159/* We actually can't write halfwords properly if not word aligned */ 162/* We actually can't write halfwords properly if not word aligned */
@@ -206,23 +209,6 @@ SMC_outw(u16 val, void __iomem *ioaddr, int reg)
206#define RPC_LSA_DEFAULT RPC_LED_TX_RX 209#define RPC_LSA_DEFAULT RPC_LED_TX_RX
207#define RPC_LSB_DEFAULT RPC_LED_100_10 210#define RPC_LSB_DEFAULT RPC_LED_100_10
208 211
209#elif defined(CONFIG_ARCH_VERSATILE)
210
211#define SMC_CAN_USE_8BIT 1
212#define SMC_CAN_USE_16BIT 1
213#define SMC_CAN_USE_32BIT 1
214#define SMC_NOWAIT 1
215
216#define SMC_inb(a, r) readb((a) + (r))
217#define SMC_inw(a, r) readw((a) + (r))
218#define SMC_inl(a, r) readl((a) + (r))
219#define SMC_outb(v, a, r) writeb(v, (a) + (r))
220#define SMC_outw(v, a, r) writew(v, (a) + (r))
221#define SMC_outl(v, a, r) writel(v, (a) + (r))
222#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
223#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
224#define SMC_IRQ_FLAGS (-1) /* from resource */
225
226#elif defined(CONFIG_MN10300) 212#elif defined(CONFIG_MN10300)
227 213
228/* 214/*
diff --git a/drivers/net/ethernet/via/via-velocity.c b/drivers/net/ethernet/via/via-velocity.c
index d022bf936572..ad61d26a44f3 100644
--- a/drivers/net/ethernet/via/via-velocity.c
+++ b/drivers/net/ethernet/via/via-velocity.c
@@ -2172,16 +2172,13 @@ static int velocity_poll(struct napi_struct *napi, int budget)
2172 unsigned int rx_done; 2172 unsigned int rx_done;
2173 unsigned long flags; 2173 unsigned long flags;
2174 2174
2175 spin_lock_irqsave(&vptr->lock, flags);
2176 /* 2175 /*
2177 * Do rx and tx twice for performance (taken from the VIA 2176 * Do rx and tx twice for performance (taken from the VIA
2178 * out-of-tree driver). 2177 * out-of-tree driver).
2179 */ 2178 */
2180 rx_done = velocity_rx_srv(vptr, budget / 2); 2179 rx_done = velocity_rx_srv(vptr, budget);
2181 velocity_tx_srv(vptr); 2180 spin_lock_irqsave(&vptr->lock, flags);
2182 rx_done += velocity_rx_srv(vptr, budget - rx_done);
2183 velocity_tx_srv(vptr); 2181 velocity_tx_srv(vptr);
2184
2185 /* If budget not fully consumed, exit the polling mode */ 2182 /* If budget not fully consumed, exit the polling mode */
2186 if (rx_done < budget) { 2183 if (rx_done < budget) {
2187 napi_complete(napi); 2184 napi_complete(napi);
@@ -2342,6 +2339,8 @@ static int velocity_change_mtu(struct net_device *dev, int new_mtu)
2342 if (ret < 0) 2339 if (ret < 0)
2343 goto out_free_tmp_vptr_1; 2340 goto out_free_tmp_vptr_1;
2344 2341
2342 napi_disable(&vptr->napi);
2343
2345 spin_lock_irqsave(&vptr->lock, flags); 2344 spin_lock_irqsave(&vptr->lock, flags);
2346 2345
2347 netif_stop_queue(dev); 2346 netif_stop_queue(dev);
@@ -2362,6 +2361,8 @@ static int velocity_change_mtu(struct net_device *dev, int new_mtu)
2362 2361
2363 velocity_give_many_rx_descs(vptr); 2362 velocity_give_many_rx_descs(vptr);
2364 2363
2364 napi_enable(&vptr->napi);
2365
2365 mac_enable_int(vptr->mac_regs); 2366 mac_enable_int(vptr->mac_regs);
2366 netif_start_queue(dev); 2367 netif_start_queue(dev);
2367 2368
diff --git a/drivers/net/macvtap.c b/drivers/net/macvtap.c
index dc76670c2f2a..9093004f9b63 100644
--- a/drivers/net/macvtap.c
+++ b/drivers/net/macvtap.c
@@ -744,7 +744,7 @@ err:
744 rcu_read_lock(); 744 rcu_read_lock();
745 vlan = rcu_dereference(q->vlan); 745 vlan = rcu_dereference(q->vlan);
746 if (vlan) 746 if (vlan)
747 vlan->dev->stats.tx_dropped++; 747 this_cpu_inc(vlan->pcpu_stats->tx_dropped);
748 rcu_read_unlock(); 748 rcu_read_unlock();
749 749
750 return err; 750 return err;
@@ -767,7 +767,6 @@ static ssize_t macvtap_put_user(struct macvtap_queue *q,
767 const struct sk_buff *skb, 767 const struct sk_buff *skb,
768 const struct iovec *iv, int len) 768 const struct iovec *iv, int len)
769{ 769{
770 struct macvlan_dev *vlan;
771 int ret; 770 int ret;
772 int vnet_hdr_len = 0; 771 int vnet_hdr_len = 0;
773 int vlan_offset = 0; 772 int vlan_offset = 0;
@@ -821,15 +820,6 @@ static ssize_t macvtap_put_user(struct macvtap_queue *q,
821 copied += len; 820 copied += len;
822 821
823done: 822done:
824 rcu_read_lock();
825 vlan = rcu_dereference(q->vlan);
826 if (vlan) {
827 preempt_disable();
828 macvlan_count_rx(vlan, copied - vnet_hdr_len, ret == 0, 0);
829 preempt_enable();
830 }
831 rcu_read_unlock();
832
833 return ret ? ret : copied; 823 return ret ? ret : copied;
834} 824}
835 825
diff --git a/drivers/net/phy/vitesse.c b/drivers/net/phy/vitesse.c
index 508e4359338b..14372c65a7e8 100644
--- a/drivers/net/phy/vitesse.c
+++ b/drivers/net/phy/vitesse.c
@@ -64,6 +64,7 @@
64 64
65#define PHY_ID_VSC8234 0x000fc620 65#define PHY_ID_VSC8234 0x000fc620
66#define PHY_ID_VSC8244 0x000fc6c0 66#define PHY_ID_VSC8244 0x000fc6c0
67#define PHY_ID_VSC8514 0x00070670
67#define PHY_ID_VSC8574 0x000704a0 68#define PHY_ID_VSC8574 0x000704a0
68#define PHY_ID_VSC8662 0x00070660 69#define PHY_ID_VSC8662 0x00070660
69#define PHY_ID_VSC8221 0x000fc550 70#define PHY_ID_VSC8221 0x000fc550
@@ -131,6 +132,7 @@ static int vsc82xx_config_intr(struct phy_device *phydev)
131 err = phy_write(phydev, MII_VSC8244_IMASK, 132 err = phy_write(phydev, MII_VSC8244_IMASK,
132 (phydev->drv->phy_id == PHY_ID_VSC8234 || 133 (phydev->drv->phy_id == PHY_ID_VSC8234 ||
133 phydev->drv->phy_id == PHY_ID_VSC8244 || 134 phydev->drv->phy_id == PHY_ID_VSC8244 ||
135 phydev->drv->phy_id == PHY_ID_VSC8514 ||
134 phydev->drv->phy_id == PHY_ID_VSC8574) ? 136 phydev->drv->phy_id == PHY_ID_VSC8574) ?
135 MII_VSC8244_IMASK_MASK : 137 MII_VSC8244_IMASK_MASK :
136 MII_VSC8221_IMASK_MASK); 138 MII_VSC8221_IMASK_MASK);
@@ -246,6 +248,18 @@ static struct phy_driver vsc82xx_driver[] = {
246 .config_intr = &vsc82xx_config_intr, 248 .config_intr = &vsc82xx_config_intr,
247 .driver = { .owner = THIS_MODULE,}, 249 .driver = { .owner = THIS_MODULE,},
248}, { 250}, {
251 .phy_id = PHY_ID_VSC8514,
252 .name = "Vitesse VSC8514",
253 .phy_id_mask = 0x000ffff0,
254 .features = PHY_GBIT_FEATURES,
255 .flags = PHY_HAS_INTERRUPT,
256 .config_init = &vsc824x_config_init,
257 .config_aneg = &vsc82x4_config_aneg,
258 .read_status = &genphy_read_status,
259 .ack_interrupt = &vsc824x_ack_interrupt,
260 .config_intr = &vsc82xx_config_intr,
261 .driver = { .owner = THIS_MODULE,},
262}, {
249 .phy_id = PHY_ID_VSC8574, 263 .phy_id = PHY_ID_VSC8574,
250 .name = "Vitesse VSC8574", 264 .name = "Vitesse VSC8574",
251 .phy_id_mask = 0x000ffff0, 265 .phy_id_mask = 0x000ffff0,
@@ -315,6 +329,7 @@ module_exit(vsc82xx_exit);
315static struct mdio_device_id __maybe_unused vitesse_tbl[] = { 329static struct mdio_device_id __maybe_unused vitesse_tbl[] = {
316 { PHY_ID_VSC8234, 0x000ffff0 }, 330 { PHY_ID_VSC8234, 0x000ffff0 },
317 { PHY_ID_VSC8244, 0x000fffc0 }, 331 { PHY_ID_VSC8244, 0x000fffc0 },
332 { PHY_ID_VSC8514, 0x000ffff0 },
318 { PHY_ID_VSC8574, 0x000ffff0 }, 333 { PHY_ID_VSC8574, 0x000ffff0 },
319 { PHY_ID_VSC8662, 0x000ffff0 }, 334 { PHY_ID_VSC8662, 0x000ffff0 },
320 { PHY_ID_VSC8221, 0x000ffff0 }, 335 { PHY_ID_VSC8221, 0x000ffff0 },
diff --git a/drivers/net/team/team.c b/drivers/net/team/team.c
index 34b0de09d881..736050d6b451 100644
--- a/drivers/net/team/team.c
+++ b/drivers/net/team/team.c
@@ -1366,6 +1366,8 @@ static int team_user_linkup_option_get(struct team *team,
1366 return 0; 1366 return 0;
1367} 1367}
1368 1368
1369static void __team_carrier_check(struct team *team);
1370
1369static int team_user_linkup_option_set(struct team *team, 1371static int team_user_linkup_option_set(struct team *team,
1370 struct team_gsetter_ctx *ctx) 1372 struct team_gsetter_ctx *ctx)
1371{ 1373{
@@ -1373,6 +1375,7 @@ static int team_user_linkup_option_set(struct team *team,
1373 1375
1374 port->user.linkup = ctx->data.bool_val; 1376 port->user.linkup = ctx->data.bool_val;
1375 team_refresh_port_linkup(port); 1377 team_refresh_port_linkup(port);
1378 __team_carrier_check(port->team);
1376 return 0; 1379 return 0;
1377} 1380}
1378 1381
@@ -1392,6 +1395,7 @@ static int team_user_linkup_en_option_set(struct team *team,
1392 1395
1393 port->user.linkup_enabled = ctx->data.bool_val; 1396 port->user.linkup_enabled = ctx->data.bool_val;
1394 team_refresh_port_linkup(port); 1397 team_refresh_port_linkup(port);
1398 __team_carrier_check(port->team);
1395 return 0; 1399 return 0;
1396} 1400}
1397 1401
diff --git a/drivers/net/virtio_net.c b/drivers/net/virtio_net.c
index 7bab4de658a9..916241d16c67 100644
--- a/drivers/net/virtio_net.c
+++ b/drivers/net/virtio_net.c
@@ -299,35 +299,76 @@ static struct sk_buff *page_to_skb(struct receive_queue *rq,
299 return skb; 299 return skb;
300} 300}
301 301
302static int receive_mergeable(struct receive_queue *rq, struct sk_buff *head_skb) 302static struct sk_buff *receive_small(void *buf, unsigned int len)
303{ 303{
304 struct skb_vnet_hdr *hdr = skb_vnet_hdr(head_skb); 304 struct sk_buff * skb = buf;
305
306 len -= sizeof(struct virtio_net_hdr);
307 skb_trim(skb, len);
308
309 return skb;
310}
311
312static struct sk_buff *receive_big(struct net_device *dev,
313 struct receive_queue *rq,
314 void *buf,
315 unsigned int len)
316{
317 struct page *page = buf;
318 struct sk_buff *skb = page_to_skb(rq, page, 0, len, PAGE_SIZE);
319
320 if (unlikely(!skb))
321 goto err;
322
323 return skb;
324
325err:
326 dev->stats.rx_dropped++;
327 give_pages(rq, page);
328 return NULL;
329}
330
331static struct sk_buff *receive_mergeable(struct net_device *dev,
332 struct receive_queue *rq,
333 void *buf,
334 unsigned int len)
335{
336 struct skb_vnet_hdr *hdr = buf;
337 int num_buf = hdr->mhdr.num_buffers;
338 struct page *page = virt_to_head_page(buf);
339 int offset = buf - page_address(page);
340 struct sk_buff *head_skb = page_to_skb(rq, page, offset, len,
341 MERGE_BUFFER_LEN);
305 struct sk_buff *curr_skb = head_skb; 342 struct sk_buff *curr_skb = head_skb;
306 char *buf;
307 struct page *page;
308 int num_buf, len, offset;
309 343
310 num_buf = hdr->mhdr.num_buffers; 344 if (unlikely(!curr_skb))
345 goto err_skb;
346
311 while (--num_buf) { 347 while (--num_buf) {
312 int num_skb_frags = skb_shinfo(curr_skb)->nr_frags; 348 int num_skb_frags;
349
313 buf = virtqueue_get_buf(rq->vq, &len); 350 buf = virtqueue_get_buf(rq->vq, &len);
314 if (unlikely(!buf)) { 351 if (unlikely(!buf)) {
315 pr_debug("%s: rx error: %d buffers missing\n", 352 pr_debug("%s: rx error: %d buffers out of %d missing\n",
316 head_skb->dev->name, hdr->mhdr.num_buffers); 353 dev->name, num_buf, hdr->mhdr.num_buffers);
317 head_skb->dev->stats.rx_length_errors++; 354 dev->stats.rx_length_errors++;
318 return -EINVAL; 355 goto err_buf;
319 } 356 }
320 if (unlikely(len > MERGE_BUFFER_LEN)) { 357 if (unlikely(len > MERGE_BUFFER_LEN)) {
321 pr_debug("%s: rx error: merge buffer too long\n", 358 pr_debug("%s: rx error: merge buffer too long\n",
322 head_skb->dev->name); 359 dev->name);
323 len = MERGE_BUFFER_LEN; 360 len = MERGE_BUFFER_LEN;
324 } 361 }
362
363 page = virt_to_head_page(buf);
364 --rq->num;
365
366 num_skb_frags = skb_shinfo(curr_skb)->nr_frags;
325 if (unlikely(num_skb_frags == MAX_SKB_FRAGS)) { 367 if (unlikely(num_skb_frags == MAX_SKB_FRAGS)) {
326 struct sk_buff *nskb = alloc_skb(0, GFP_ATOMIC); 368 struct sk_buff *nskb = alloc_skb(0, GFP_ATOMIC);
327 if (unlikely(!nskb)) { 369
328 head_skb->dev->stats.rx_dropped++; 370 if (unlikely(!nskb))
329 return -ENOMEM; 371 goto err_skb;
330 }
331 if (curr_skb == head_skb) 372 if (curr_skb == head_skb)
332 skb_shinfo(curr_skb)->frag_list = nskb; 373 skb_shinfo(curr_skb)->frag_list = nskb;
333 else 374 else
@@ -341,8 +382,7 @@ static int receive_mergeable(struct receive_queue *rq, struct sk_buff *head_skb)
341 head_skb->len += len; 382 head_skb->len += len;
342 head_skb->truesize += MERGE_BUFFER_LEN; 383 head_skb->truesize += MERGE_BUFFER_LEN;
343 } 384 }
344 page = virt_to_head_page(buf); 385 offset = buf - page_address(page);
345 offset = buf - (char *)page_address(page);
346 if (skb_can_coalesce(curr_skb, num_skb_frags, page, offset)) { 386 if (skb_can_coalesce(curr_skb, num_skb_frags, page, offset)) {
347 put_page(page); 387 put_page(page);
348 skb_coalesce_rx_frag(curr_skb, num_skb_frags - 1, 388 skb_coalesce_rx_frag(curr_skb, num_skb_frags - 1,
@@ -351,9 +391,28 @@ static int receive_mergeable(struct receive_queue *rq, struct sk_buff *head_skb)
351 skb_add_rx_frag(curr_skb, num_skb_frags, page, 391 skb_add_rx_frag(curr_skb, num_skb_frags, page,
352 offset, len, MERGE_BUFFER_LEN); 392 offset, len, MERGE_BUFFER_LEN);
353 } 393 }
394 }
395
396 return head_skb;
397
398err_skb:
399 put_page(page);
400 while (--num_buf) {
401 buf = virtqueue_get_buf(rq->vq, &len);
402 if (unlikely(!buf)) {
403 pr_debug("%s: rx error: %d buffers missing\n",
404 dev->name, num_buf);
405 dev->stats.rx_length_errors++;
406 break;
407 }
408 page = virt_to_head_page(buf);
409 put_page(page);
354 --rq->num; 410 --rq->num;
355 } 411 }
356 return 0; 412err_buf:
413 dev->stats.rx_dropped++;
414 dev_kfree_skb(head_skb);
415 return NULL;
357} 416}
358 417
359static void receive_buf(struct receive_queue *rq, void *buf, unsigned int len) 418static void receive_buf(struct receive_queue *rq, void *buf, unsigned int len)
@@ -362,7 +421,6 @@ static void receive_buf(struct receive_queue *rq, void *buf, unsigned int len)
362 struct net_device *dev = vi->dev; 421 struct net_device *dev = vi->dev;
363 struct virtnet_stats *stats = this_cpu_ptr(vi->stats); 422 struct virtnet_stats *stats = this_cpu_ptr(vi->stats);
364 struct sk_buff *skb; 423 struct sk_buff *skb;
365 struct page *page;
366 struct skb_vnet_hdr *hdr; 424 struct skb_vnet_hdr *hdr;
367 425
368 if (unlikely(len < sizeof(struct virtio_net_hdr) + ETH_HLEN)) { 426 if (unlikely(len < sizeof(struct virtio_net_hdr) + ETH_HLEN)) {
@@ -377,33 +435,15 @@ static void receive_buf(struct receive_queue *rq, void *buf, unsigned int len)
377 return; 435 return;
378 } 436 }
379 437
380 if (!vi->mergeable_rx_bufs && !vi->big_packets) { 438 if (vi->mergeable_rx_bufs)
381 skb = buf; 439 skb = receive_mergeable(dev, rq, buf, len);
382 len -= sizeof(struct virtio_net_hdr); 440 else if (vi->big_packets)
383 skb_trim(skb, len); 441 skb = receive_big(dev, rq, buf, len);
384 } else if (vi->mergeable_rx_bufs) { 442 else
385 struct page *page = virt_to_head_page(buf); 443 skb = receive_small(buf, len);
386 skb = page_to_skb(rq, page, 444
387 (char *)buf - (char *)page_address(page), 445 if (unlikely(!skb))
388 len, MERGE_BUFFER_LEN); 446 return;
389 if (unlikely(!skb)) {
390 dev->stats.rx_dropped++;
391 put_page(page);
392 return;
393 }
394 if (receive_mergeable(rq, skb)) {
395 dev_kfree_skb(skb);
396 return;
397 }
398 } else {
399 page = buf;
400 skb = page_to_skb(rq, page, 0, len, PAGE_SIZE);
401 if (unlikely(!skb)) {
402 dev->stats.rx_dropped++;
403 give_pages(rq, page);
404 return;
405 }
406 }
407 447
408 hdr = skb_vnet_hdr(skb); 448 hdr = skb_vnet_hdr(skb);
409 449
@@ -1084,7 +1124,7 @@ static void virtnet_set_rx_mode(struct net_device *dev)
1084 if (!virtnet_send_command(vi, VIRTIO_NET_CTRL_MAC, 1124 if (!virtnet_send_command(vi, VIRTIO_NET_CTRL_MAC,
1085 VIRTIO_NET_CTRL_MAC_TABLE_SET, 1125 VIRTIO_NET_CTRL_MAC_TABLE_SET,
1086 sg, NULL)) 1126 sg, NULL))
1087 dev_warn(&dev->dev, "Failed to set MAC fitler table.\n"); 1127 dev_warn(&dev->dev, "Failed to set MAC filter table.\n");
1088 1128
1089 kfree(buf); 1129 kfree(buf);
1090} 1130}
diff --git a/drivers/net/xen-netback/netback.c b/drivers/net/xen-netback/netback.c
index 919b6509455c..64f0e0d18b81 100644
--- a/drivers/net/xen-netback/netback.c
+++ b/drivers/net/xen-netback/netback.c
@@ -39,6 +39,7 @@
39#include <linux/udp.h> 39#include <linux/udp.h>
40 40
41#include <net/tcp.h> 41#include <net/tcp.h>
42#include <net/ip6_checksum.h>
42 43
43#include <xen/xen.h> 44#include <xen/xen.h>
44#include <xen/events.h> 45#include <xen/events.h>
diff --git a/drivers/ntb/ntb_hw.c b/drivers/ntb/ntb_hw.c
index 1cb6e51e6bda..170e8e60cdb7 100644
--- a/drivers/ntb/ntb_hw.c
+++ b/drivers/ntb/ntb_hw.c
@@ -141,6 +141,24 @@ void ntb_unregister_event_callback(struct ntb_device *ndev)
141 ndev->event_cb = NULL; 141 ndev->event_cb = NULL;
142} 142}
143 143
144static void ntb_irq_work(unsigned long data)
145{
146 struct ntb_db_cb *db_cb = (struct ntb_db_cb *)data;
147 int rc;
148
149 rc = db_cb->callback(db_cb->data, db_cb->db_num);
150 if (rc)
151 tasklet_schedule(&db_cb->irq_work);
152 else {
153 struct ntb_device *ndev = db_cb->ndev;
154 unsigned long mask;
155
156 mask = readw(ndev->reg_ofs.ldb_mask);
157 clear_bit(db_cb->db_num * ndev->bits_per_vector, &mask);
158 writew(mask, ndev->reg_ofs.ldb_mask);
159 }
160}
161
144/** 162/**
145 * ntb_register_db_callback() - register a callback for doorbell interrupt 163 * ntb_register_db_callback() - register a callback for doorbell interrupt
146 * @ndev: pointer to ntb_device instance 164 * @ndev: pointer to ntb_device instance
@@ -155,7 +173,7 @@ void ntb_unregister_event_callback(struct ntb_device *ndev)
155 * RETURNS: An appropriate -ERRNO error value on error, or zero for success. 173 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
156 */ 174 */
157int ntb_register_db_callback(struct ntb_device *ndev, unsigned int idx, 175int ntb_register_db_callback(struct ntb_device *ndev, unsigned int idx,
158 void *data, void (*func)(void *data, int db_num)) 176 void *data, int (*func)(void *data, int db_num))
159{ 177{
160 unsigned long mask; 178 unsigned long mask;
161 179
@@ -166,6 +184,10 @@ int ntb_register_db_callback(struct ntb_device *ndev, unsigned int idx,
166 184
167 ndev->db_cb[idx].callback = func; 185 ndev->db_cb[idx].callback = func;
168 ndev->db_cb[idx].data = data; 186 ndev->db_cb[idx].data = data;
187 ndev->db_cb[idx].ndev = ndev;
188
189 tasklet_init(&ndev->db_cb[idx].irq_work, ntb_irq_work,
190 (unsigned long) &ndev->db_cb[idx]);
169 191
170 /* unmask interrupt */ 192 /* unmask interrupt */
171 mask = readw(ndev->reg_ofs.ldb_mask); 193 mask = readw(ndev->reg_ofs.ldb_mask);
@@ -194,6 +216,8 @@ void ntb_unregister_db_callback(struct ntb_device *ndev, unsigned int idx)
194 set_bit(idx * ndev->bits_per_vector, &mask); 216 set_bit(idx * ndev->bits_per_vector, &mask);
195 writew(mask, ndev->reg_ofs.ldb_mask); 217 writew(mask, ndev->reg_ofs.ldb_mask);
196 218
219 tasklet_disable(&ndev->db_cb[idx].irq_work);
220
197 ndev->db_cb[idx].callback = NULL; 221 ndev->db_cb[idx].callback = NULL;
198} 222}
199 223
@@ -678,6 +702,7 @@ static int ntb_xeon_setup(struct ntb_device *ndev)
678 return -EINVAL; 702 return -EINVAL;
679 703
680 ndev->limits.max_mw = SNB_ERRATA_MAX_MW; 704 ndev->limits.max_mw = SNB_ERRATA_MAX_MW;
705 ndev->limits.max_db_bits = SNB_MAX_DB_BITS;
681 ndev->reg_ofs.spad_write = ndev->mw[1].vbase + 706 ndev->reg_ofs.spad_write = ndev->mw[1].vbase +
682 SNB_SPAD_OFFSET; 707 SNB_SPAD_OFFSET;
683 ndev->reg_ofs.rdb = ndev->mw[1].vbase + 708 ndev->reg_ofs.rdb = ndev->mw[1].vbase +
@@ -688,8 +713,21 @@ static int ntb_xeon_setup(struct ntb_device *ndev)
688 */ 713 */
689 writeq(ndev->mw[1].bar_sz + 0x1000, ndev->reg_base + 714 writeq(ndev->mw[1].bar_sz + 0x1000, ndev->reg_base +
690 SNB_PBAR4LMT_OFFSET); 715 SNB_PBAR4LMT_OFFSET);
716 /* HW errata on the Limit registers. They can only be
717 * written when the base register is 4GB aligned and
718 * < 32bit. This should already be the case based on the
719 * driver defaults, but write the Limit registers first
720 * just in case.
721 */
691 } else { 722 } else {
692 ndev->limits.max_mw = SNB_MAX_MW; 723 ndev->limits.max_mw = SNB_MAX_MW;
724
725 /* HW Errata on bit 14 of b2bdoorbell register. Writes
726 * will not be mirrored to the remote system. Shrink
727 * the number of bits by one, since bit 14 is the last
728 * bit.
729 */
730 ndev->limits.max_db_bits = SNB_MAX_DB_BITS - 1;
693 ndev->reg_ofs.spad_write = ndev->reg_base + 731 ndev->reg_ofs.spad_write = ndev->reg_base +
694 SNB_B2B_SPAD_OFFSET; 732 SNB_B2B_SPAD_OFFSET;
695 ndev->reg_ofs.rdb = ndev->reg_base + 733 ndev->reg_ofs.rdb = ndev->reg_base +
@@ -699,6 +737,12 @@ static int ntb_xeon_setup(struct ntb_device *ndev)
699 * something silly 737 * something silly
700 */ 738 */
701 writeq(0, ndev->reg_base + SNB_PBAR4LMT_OFFSET); 739 writeq(0, ndev->reg_base + SNB_PBAR4LMT_OFFSET);
740 /* HW errata on the Limit registers. They can only be
741 * written when the base register is 4GB aligned and
742 * < 32bit. This should already be the case based on the
743 * driver defaults, but write the Limit registers first
744 * just in case.
745 */
702 } 746 }
703 747
704 /* The Xeon errata workaround requires setting SBAR Base 748 /* The Xeon errata workaround requires setting SBAR Base
@@ -769,6 +813,7 @@ static int ntb_xeon_setup(struct ntb_device *ndev)
769 * have an equal amount. 813 * have an equal amount.
770 */ 814 */
771 ndev->limits.max_spads = SNB_MAX_COMPAT_SPADS / 2; 815 ndev->limits.max_spads = SNB_MAX_COMPAT_SPADS / 2;
816 ndev->limits.max_db_bits = SNB_MAX_DB_BITS;
772 /* Note: The SDOORBELL is the cause of the errata. You REALLY 817 /* Note: The SDOORBELL is the cause of the errata. You REALLY
773 * don't want to touch it. 818 * don't want to touch it.
774 */ 819 */
@@ -793,6 +838,7 @@ static int ntb_xeon_setup(struct ntb_device *ndev)
793 * have an equal amount. 838 * have an equal amount.
794 */ 839 */
795 ndev->limits.max_spads = SNB_MAX_COMPAT_SPADS / 2; 840 ndev->limits.max_spads = SNB_MAX_COMPAT_SPADS / 2;
841 ndev->limits.max_db_bits = SNB_MAX_DB_BITS;
796 ndev->reg_ofs.rdb = ndev->reg_base + SNB_PDOORBELL_OFFSET; 842 ndev->reg_ofs.rdb = ndev->reg_base + SNB_PDOORBELL_OFFSET;
797 ndev->reg_ofs.ldb = ndev->reg_base + SNB_SDOORBELL_OFFSET; 843 ndev->reg_ofs.ldb = ndev->reg_base + SNB_SDOORBELL_OFFSET;
798 ndev->reg_ofs.ldb_mask = ndev->reg_base + SNB_SDBMSK_OFFSET; 844 ndev->reg_ofs.ldb_mask = ndev->reg_base + SNB_SDBMSK_OFFSET;
@@ -819,7 +865,6 @@ static int ntb_xeon_setup(struct ntb_device *ndev)
819 ndev->reg_ofs.lnk_stat = ndev->reg_base + SNB_SLINK_STATUS_OFFSET; 865 ndev->reg_ofs.lnk_stat = ndev->reg_base + SNB_SLINK_STATUS_OFFSET;
820 ndev->reg_ofs.spci_cmd = ndev->reg_base + SNB_PCICMD_OFFSET; 866 ndev->reg_ofs.spci_cmd = ndev->reg_base + SNB_PCICMD_OFFSET;
821 867
822 ndev->limits.max_db_bits = SNB_MAX_DB_BITS;
823 ndev->limits.msix_cnt = SNB_MSIX_CNT; 868 ndev->limits.msix_cnt = SNB_MSIX_CNT;
824 ndev->bits_per_vector = SNB_DB_BITS_PER_VEC; 869 ndev->bits_per_vector = SNB_DB_BITS_PER_VEC;
825 870
@@ -934,12 +979,16 @@ static irqreturn_t bwd_callback_msix_irq(int irq, void *data)
934{ 979{
935 struct ntb_db_cb *db_cb = data; 980 struct ntb_db_cb *db_cb = data;
936 struct ntb_device *ndev = db_cb->ndev; 981 struct ntb_device *ndev = db_cb->ndev;
982 unsigned long mask;
937 983
938 dev_dbg(&ndev->pdev->dev, "MSI-X irq %d received for DB %d\n", irq, 984 dev_dbg(&ndev->pdev->dev, "MSI-X irq %d received for DB %d\n", irq,
939 db_cb->db_num); 985 db_cb->db_num);
940 986
941 if (db_cb->callback) 987 mask = readw(ndev->reg_ofs.ldb_mask);
942 db_cb->callback(db_cb->data, db_cb->db_num); 988 set_bit(db_cb->db_num * ndev->bits_per_vector, &mask);
989 writew(mask, ndev->reg_ofs.ldb_mask);
990
991 tasklet_schedule(&db_cb->irq_work);
943 992
944 /* No need to check for the specific HB irq, any interrupt means 993 /* No need to check for the specific HB irq, any interrupt means
945 * we're connected. 994 * we're connected.
@@ -955,12 +1004,16 @@ static irqreturn_t xeon_callback_msix_irq(int irq, void *data)
955{ 1004{
956 struct ntb_db_cb *db_cb = data; 1005 struct ntb_db_cb *db_cb = data;
957 struct ntb_device *ndev = db_cb->ndev; 1006 struct ntb_device *ndev = db_cb->ndev;
1007 unsigned long mask;
958 1008
959 dev_dbg(&ndev->pdev->dev, "MSI-X irq %d received for DB %d\n", irq, 1009 dev_dbg(&ndev->pdev->dev, "MSI-X irq %d received for DB %d\n", irq,
960 db_cb->db_num); 1010 db_cb->db_num);
961 1011
962 if (db_cb->callback) 1012 mask = readw(ndev->reg_ofs.ldb_mask);
963 db_cb->callback(db_cb->data, db_cb->db_num); 1013 set_bit(db_cb->db_num * ndev->bits_per_vector, &mask);
1014 writew(mask, ndev->reg_ofs.ldb_mask);
1015
1016 tasklet_schedule(&db_cb->irq_work);
964 1017
965 /* On Sandybridge, there are 16 bits in the interrupt register 1018 /* On Sandybridge, there are 16 bits in the interrupt register
966 * but only 4 vectors. So, 5 bits are assigned to the first 3 1019 * but only 4 vectors. So, 5 bits are assigned to the first 3
@@ -986,7 +1039,7 @@ static irqreturn_t xeon_event_msix_irq(int irq, void *dev)
986 dev_err(&ndev->pdev->dev, "Error determining link status\n"); 1039 dev_err(&ndev->pdev->dev, "Error determining link status\n");
987 1040
988 /* bit 15 is always the link bit */ 1041 /* bit 15 is always the link bit */
989 writew(1 << ndev->limits.max_db_bits, ndev->reg_ofs.ldb); 1042 writew(1 << SNB_LINK_DB, ndev->reg_ofs.ldb);
990 1043
991 return IRQ_HANDLED; 1044 return IRQ_HANDLED;
992} 1045}
@@ -1075,6 +1128,10 @@ static int ntb_setup_msix(struct ntb_device *ndev)
1075 "Only %d MSI-X vectors. Limiting the number of queues to that number.\n", 1128 "Only %d MSI-X vectors. Limiting the number of queues to that number.\n",
1076 rc); 1129 rc);
1077 msix_entries = rc; 1130 msix_entries = rc;
1131
1132 rc = pci_enable_msix(pdev, ndev->msix_entries, msix_entries);
1133 if (rc)
1134 goto err1;
1078 } 1135 }
1079 1136
1080 for (i = 0; i < msix_entries; i++) { 1137 for (i = 0; i < msix_entries; i++) {
@@ -1176,9 +1233,10 @@ static int ntb_setup_interrupts(struct ntb_device *ndev)
1176 */ 1233 */
1177 if (ndev->hw_type == BWD_HW) 1234 if (ndev->hw_type == BWD_HW)
1178 writeq(~0, ndev->reg_ofs.ldb_mask); 1235 writeq(~0, ndev->reg_ofs.ldb_mask);
1179 else 1236 else {
1180 writew(~(1 << ndev->limits.max_db_bits), 1237 u16 var = 1 << SNB_LINK_DB;
1181 ndev->reg_ofs.ldb_mask); 1238 writew(~var, ndev->reg_ofs.ldb_mask);
1239 }
1182 1240
1183 rc = ntb_setup_msix(ndev); 1241 rc = ntb_setup_msix(ndev);
1184 if (!rc) 1242 if (!rc)
@@ -1286,6 +1344,39 @@ static void ntb_free_debugfs(struct ntb_device *ndev)
1286 } 1344 }
1287} 1345}
1288 1346
1347static void ntb_hw_link_up(struct ntb_device *ndev)
1348{
1349 if (ndev->conn_type == NTB_CONN_TRANSPARENT)
1350 ntb_link_event(ndev, NTB_LINK_UP);
1351 else {
1352 u32 ntb_cntl;
1353
1354 /* Let's bring the NTB link up */
1355 ntb_cntl = readl(ndev->reg_ofs.lnk_cntl);
1356 ntb_cntl &= ~(NTB_CNTL_LINK_DISABLE | NTB_CNTL_CFG_LOCK);
1357 ntb_cntl |= NTB_CNTL_P2S_BAR23_SNOOP | NTB_CNTL_S2P_BAR23_SNOOP;
1358 ntb_cntl |= NTB_CNTL_P2S_BAR45_SNOOP | NTB_CNTL_S2P_BAR45_SNOOP;
1359 writel(ntb_cntl, ndev->reg_ofs.lnk_cntl);
1360 }
1361}
1362
1363static void ntb_hw_link_down(struct ntb_device *ndev)
1364{
1365 u32 ntb_cntl;
1366
1367 if (ndev->conn_type == NTB_CONN_TRANSPARENT) {
1368 ntb_link_event(ndev, NTB_LINK_DOWN);
1369 return;
1370 }
1371
1372 /* Bring NTB link down */
1373 ntb_cntl = readl(ndev->reg_ofs.lnk_cntl);
1374 ntb_cntl &= ~(NTB_CNTL_P2S_BAR23_SNOOP | NTB_CNTL_S2P_BAR23_SNOOP);
1375 ntb_cntl &= ~(NTB_CNTL_P2S_BAR45_SNOOP | NTB_CNTL_S2P_BAR45_SNOOP);
1376 ntb_cntl |= NTB_CNTL_LINK_DISABLE | NTB_CNTL_CFG_LOCK;
1377 writel(ntb_cntl, ndev->reg_ofs.lnk_cntl);
1378}
1379
1289static int ntb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1380static int ntb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1290{ 1381{
1291 struct ntb_device *ndev; 1382 struct ntb_device *ndev;
@@ -1374,9 +1465,7 @@ static int ntb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1374 if (rc) 1465 if (rc)
1375 goto err6; 1466 goto err6;
1376 1467
1377 /* Let's bring the NTB link up */ 1468 ntb_hw_link_up(ndev);
1378 writel(NTB_CNTL_BAR23_SNOOP | NTB_CNTL_BAR45_SNOOP,
1379 ndev->reg_ofs.lnk_cntl);
1380 1469
1381 return 0; 1470 return 0;
1382 1471
@@ -1406,12 +1495,8 @@ static void ntb_pci_remove(struct pci_dev *pdev)
1406{ 1495{
1407 struct ntb_device *ndev = pci_get_drvdata(pdev); 1496 struct ntb_device *ndev = pci_get_drvdata(pdev);
1408 int i; 1497 int i;
1409 u32 ntb_cntl;
1410 1498
1411 /* Bring NTB link down */ 1499 ntb_hw_link_down(ndev);
1412 ntb_cntl = readl(ndev->reg_ofs.lnk_cntl);
1413 ntb_cntl |= NTB_CNTL_LINK_DISABLE;
1414 writel(ntb_cntl, ndev->reg_ofs.lnk_cntl);
1415 1500
1416 ntb_transport_free(ndev->ntb_transport); 1501 ntb_transport_free(ndev->ntb_transport);
1417 1502
diff --git a/drivers/ntb/ntb_hw.h b/drivers/ntb/ntb_hw.h
index 0a31cedae7d4..bbdb7edca10c 100644
--- a/drivers/ntb/ntb_hw.h
+++ b/drivers/ntb/ntb_hw.h
@@ -106,10 +106,11 @@ struct ntb_mw {
106}; 106};
107 107
108struct ntb_db_cb { 108struct ntb_db_cb {
109 void (*callback) (void *data, int db_num); 109 int (*callback)(void *data, int db_num);
110 unsigned int db_num; 110 unsigned int db_num;
111 void *data; 111 void *data;
112 struct ntb_device *ndev; 112 struct ntb_device *ndev;
113 struct tasklet_struct irq_work;
113}; 114};
114 115
115struct ntb_device { 116struct ntb_device {
@@ -228,8 +229,8 @@ struct ntb_device *ntb_register_transport(struct pci_dev *pdev,
228void ntb_unregister_transport(struct ntb_device *ndev); 229void ntb_unregister_transport(struct ntb_device *ndev);
229void ntb_set_mw_addr(struct ntb_device *ndev, unsigned int mw, u64 addr); 230void ntb_set_mw_addr(struct ntb_device *ndev, unsigned int mw, u64 addr);
230int ntb_register_db_callback(struct ntb_device *ndev, unsigned int idx, 231int ntb_register_db_callback(struct ntb_device *ndev, unsigned int idx,
231 void *data, void (*db_cb_func) (void *data, 232 void *data, int (*db_cb_func)(void *data,
232 int db_num)); 233 int db_num));
233void ntb_unregister_db_callback(struct ntb_device *ndev, unsigned int idx); 234void ntb_unregister_db_callback(struct ntb_device *ndev, unsigned int idx);
234int ntb_register_event_callback(struct ntb_device *ndev, 235int ntb_register_event_callback(struct ntb_device *ndev,
235 void (*event_cb_func) (void *handle, 236 void (*event_cb_func) (void *handle,
diff --git a/drivers/ntb/ntb_regs.h b/drivers/ntb/ntb_regs.h
index aa4bdd393c58..9774506419d7 100644
--- a/drivers/ntb/ntb_regs.h
+++ b/drivers/ntb/ntb_regs.h
@@ -55,6 +55,7 @@
55#define SNB_MAX_COMPAT_SPADS 16 55#define SNB_MAX_COMPAT_SPADS 16
56/* Reserve the uppermost bit for link interrupt */ 56/* Reserve the uppermost bit for link interrupt */
57#define SNB_MAX_DB_BITS 15 57#define SNB_MAX_DB_BITS 15
58#define SNB_LINK_DB 15
58#define SNB_DB_BITS_PER_VEC 5 59#define SNB_DB_BITS_PER_VEC 5
59#define SNB_MAX_MW 2 60#define SNB_MAX_MW 2
60#define SNB_ERRATA_MAX_MW 1 61#define SNB_ERRATA_MAX_MW 1
@@ -75,9 +76,6 @@
75#define SNB_SBAR2XLAT_OFFSET 0x0030 76#define SNB_SBAR2XLAT_OFFSET 0x0030
76#define SNB_SBAR4XLAT_OFFSET 0x0038 77#define SNB_SBAR4XLAT_OFFSET 0x0038
77#define SNB_SBAR0BASE_OFFSET 0x0040 78#define SNB_SBAR0BASE_OFFSET 0x0040
78#define SNB_SBAR0BASE_OFFSET 0x0040
79#define SNB_SBAR2BASE_OFFSET 0x0048
80#define SNB_SBAR4BASE_OFFSET 0x0050
81#define SNB_SBAR2BASE_OFFSET 0x0048 79#define SNB_SBAR2BASE_OFFSET 0x0048
82#define SNB_SBAR4BASE_OFFSET 0x0050 80#define SNB_SBAR4BASE_OFFSET 0x0050
83#define SNB_NTBCNTL_OFFSET 0x0058 81#define SNB_NTBCNTL_OFFSET 0x0058
@@ -145,11 +143,13 @@
145#define BWD_LTSSMSTATEJMP_FORCEDETECT (1 << 2) 143#define BWD_LTSSMSTATEJMP_FORCEDETECT (1 << 2)
146#define BWD_IBIST_ERR_OFLOW 0x7FFF7FFF 144#define BWD_IBIST_ERR_OFLOW 0x7FFF7FFF
147 145
148#define NTB_CNTL_CFG_LOCK (1 << 0) 146#define NTB_CNTL_CFG_LOCK (1 << 0)
149#define NTB_CNTL_LINK_DISABLE (1 << 1) 147#define NTB_CNTL_LINK_DISABLE (1 << 1)
150#define NTB_CNTL_BAR23_SNOOP (1 << 2) 148#define NTB_CNTL_S2P_BAR23_SNOOP (1 << 2)
151#define NTB_CNTL_BAR45_SNOOP (1 << 6) 149#define NTB_CNTL_P2S_BAR23_SNOOP (1 << 4)
152#define BWD_CNTL_LINK_DOWN (1 << 16) 150#define NTB_CNTL_S2P_BAR45_SNOOP (1 << 6)
151#define NTB_CNTL_P2S_BAR45_SNOOP (1 << 8)
152#define BWD_CNTL_LINK_DOWN (1 << 16)
153 153
154#define NTB_PPD_OFFSET 0x00D4 154#define NTB_PPD_OFFSET 0x00D4
155#define SNB_PPD_CONN_TYPE 0x0003 155#define SNB_PPD_CONN_TYPE 0x0003
diff --git a/drivers/ntb/ntb_transport.c b/drivers/ntb/ntb_transport.c
index d0222f13d154..3217f394d45b 100644
--- a/drivers/ntb/ntb_transport.c
+++ b/drivers/ntb/ntb_transport.c
@@ -119,7 +119,6 @@ struct ntb_transport_qp {
119 119
120 void (*rx_handler) (struct ntb_transport_qp *qp, void *qp_data, 120 void (*rx_handler) (struct ntb_transport_qp *qp, void *qp_data,
121 void *data, int len); 121 void *data, int len);
122 struct tasklet_struct rx_work;
123 struct list_head rx_pend_q; 122 struct list_head rx_pend_q;
124 struct list_head rx_free_q; 123 struct list_head rx_free_q;
125 spinlock_t ntb_rx_pend_q_lock; 124 spinlock_t ntb_rx_pend_q_lock;
@@ -584,11 +583,8 @@ static int ntb_set_mw(struct ntb_transport *nt, int num_mw, unsigned int size)
584 return 0; 583 return 0;
585} 584}
586 585
587static void ntb_qp_link_cleanup(struct work_struct *work) 586static void ntb_qp_link_cleanup(struct ntb_transport_qp *qp)
588{ 587{
589 struct ntb_transport_qp *qp = container_of(work,
590 struct ntb_transport_qp,
591 link_cleanup);
592 struct ntb_transport *nt = qp->transport; 588 struct ntb_transport *nt = qp->transport;
593 struct pci_dev *pdev = ntb_query_pdev(nt->ndev); 589 struct pci_dev *pdev = ntb_query_pdev(nt->ndev);
594 590
@@ -602,6 +598,16 @@ static void ntb_qp_link_cleanup(struct work_struct *work)
602 598
603 dev_info(&pdev->dev, "qp %d: Link Down\n", qp->qp_num); 599 dev_info(&pdev->dev, "qp %d: Link Down\n", qp->qp_num);
604 qp->qp_link = NTB_LINK_DOWN; 600 qp->qp_link = NTB_LINK_DOWN;
601}
602
603static void ntb_qp_link_cleanup_work(struct work_struct *work)
604{
605 struct ntb_transport_qp *qp = container_of(work,
606 struct ntb_transport_qp,
607 link_cleanup);
608 struct ntb_transport *nt = qp->transport;
609
610 ntb_qp_link_cleanup(qp);
605 611
606 if (nt->transport_link == NTB_LINK_UP) 612 if (nt->transport_link == NTB_LINK_UP)
607 schedule_delayed_work(&qp->link_work, 613 schedule_delayed_work(&qp->link_work,
@@ -613,22 +619,20 @@ static void ntb_qp_link_down(struct ntb_transport_qp *qp)
613 schedule_work(&qp->link_cleanup); 619 schedule_work(&qp->link_cleanup);
614} 620}
615 621
616static void ntb_transport_link_cleanup(struct work_struct *work) 622static void ntb_transport_link_cleanup(struct ntb_transport *nt)
617{ 623{
618 struct ntb_transport *nt = container_of(work, struct ntb_transport,
619 link_cleanup);
620 int i; 624 int i;
621 625
626 /* Pass along the info to any clients */
627 for (i = 0; i < nt->max_qps; i++)
628 if (!test_bit(i, &nt->qp_bitmap))
629 ntb_qp_link_cleanup(&nt->qps[i]);
630
622 if (nt->transport_link == NTB_LINK_DOWN) 631 if (nt->transport_link == NTB_LINK_DOWN)
623 cancel_delayed_work_sync(&nt->link_work); 632 cancel_delayed_work_sync(&nt->link_work);
624 else 633 else
625 nt->transport_link = NTB_LINK_DOWN; 634 nt->transport_link = NTB_LINK_DOWN;
626 635
627 /* Pass along the info to any clients */
628 for (i = 0; i < nt->max_qps; i++)
629 if (!test_bit(i, &nt->qp_bitmap))
630 ntb_qp_link_down(&nt->qps[i]);
631
632 /* The scratchpad registers keep the values if the remote side 636 /* The scratchpad registers keep the values if the remote side
633 * goes down, blast them now to give them a sane value the next 637 * goes down, blast them now to give them a sane value the next
634 * time they are accessed 638 * time they are accessed
@@ -637,6 +641,14 @@ static void ntb_transport_link_cleanup(struct work_struct *work)
637 ntb_write_local_spad(nt->ndev, i, 0); 641 ntb_write_local_spad(nt->ndev, i, 0);
638} 642}
639 643
644static void ntb_transport_link_cleanup_work(struct work_struct *work)
645{
646 struct ntb_transport *nt = container_of(work, struct ntb_transport,
647 link_cleanup);
648
649 ntb_transport_link_cleanup(nt);
650}
651
640static void ntb_transport_event_callback(void *data, enum ntb_hw_event event) 652static void ntb_transport_event_callback(void *data, enum ntb_hw_event event)
641{ 653{
642 struct ntb_transport *nt = data; 654 struct ntb_transport *nt = data;
@@ -880,7 +892,7 @@ static int ntb_transport_init_queue(struct ntb_transport *nt,
880 } 892 }
881 893
882 INIT_DELAYED_WORK(&qp->link_work, ntb_qp_link_work); 894 INIT_DELAYED_WORK(&qp->link_work, ntb_qp_link_work);
883 INIT_WORK(&qp->link_cleanup, ntb_qp_link_cleanup); 895 INIT_WORK(&qp->link_cleanup, ntb_qp_link_cleanup_work);
884 896
885 spin_lock_init(&qp->ntb_rx_pend_q_lock); 897 spin_lock_init(&qp->ntb_rx_pend_q_lock);
886 spin_lock_init(&qp->ntb_rx_free_q_lock); 898 spin_lock_init(&qp->ntb_rx_free_q_lock);
@@ -936,7 +948,7 @@ int ntb_transport_init(struct pci_dev *pdev)
936 } 948 }
937 949
938 INIT_DELAYED_WORK(&nt->link_work, ntb_transport_link_work); 950 INIT_DELAYED_WORK(&nt->link_work, ntb_transport_link_work);
939 INIT_WORK(&nt->link_cleanup, ntb_transport_link_cleanup); 951 INIT_WORK(&nt->link_cleanup, ntb_transport_link_cleanup_work);
940 952
941 rc = ntb_register_event_callback(nt->ndev, 953 rc = ntb_register_event_callback(nt->ndev,
942 ntb_transport_event_callback); 954 ntb_transport_event_callback);
@@ -972,7 +984,7 @@ void ntb_transport_free(void *transport)
972 struct ntb_device *ndev = nt->ndev; 984 struct ntb_device *ndev = nt->ndev;
973 int i; 985 int i;
974 986
975 nt->transport_link = NTB_LINK_DOWN; 987 ntb_transport_link_cleanup(nt);
976 988
977 /* verify that all the qp's are freed */ 989 /* verify that all the qp's are freed */
978 for (i = 0; i < nt->max_qps; i++) { 990 for (i = 0; i < nt->max_qps; i++) {
@@ -1188,11 +1200,14 @@ err:
1188 goto out; 1200 goto out;
1189} 1201}
1190 1202
1191static void ntb_transport_rx(unsigned long data) 1203static int ntb_transport_rxc_db(void *data, int db_num)
1192{ 1204{
1193 struct ntb_transport_qp *qp = (struct ntb_transport_qp *)data; 1205 struct ntb_transport_qp *qp = data;
1194 int rc, i; 1206 int rc, i;
1195 1207
1208 dev_dbg(&ntb_query_pdev(qp->ndev)->dev, "%s: doorbell %d received\n",
1209 __func__, db_num);
1210
1196 /* Limit the number of packets processed in a single interrupt to 1211 /* Limit the number of packets processed in a single interrupt to
1197 * provide fairness to others 1212 * provide fairness to others
1198 */ 1213 */
@@ -1204,16 +1219,8 @@ static void ntb_transport_rx(unsigned long data)
1204 1219
1205 if (qp->dma_chan) 1220 if (qp->dma_chan)
1206 dma_async_issue_pending(qp->dma_chan); 1221 dma_async_issue_pending(qp->dma_chan);
1207}
1208
1209static void ntb_transport_rxc_db(void *data, int db_num)
1210{
1211 struct ntb_transport_qp *qp = data;
1212
1213 dev_dbg(&ntb_query_pdev(qp->ndev)->dev, "%s: doorbell %d received\n",
1214 __func__, db_num);
1215 1222
1216 tasklet_schedule(&qp->rx_work); 1223 return i;
1217} 1224}
1218 1225
1219static void ntb_tx_copy_callback(void *data) 1226static void ntb_tx_copy_callback(void *data)
@@ -1432,11 +1439,12 @@ ntb_transport_create_queue(void *data, struct pci_dev *pdev,
1432 qp->tx_handler = handlers->tx_handler; 1439 qp->tx_handler = handlers->tx_handler;
1433 qp->event_handler = handlers->event_handler; 1440 qp->event_handler = handlers->event_handler;
1434 1441
1442 dmaengine_get();
1435 qp->dma_chan = dma_find_channel(DMA_MEMCPY); 1443 qp->dma_chan = dma_find_channel(DMA_MEMCPY);
1436 if (!qp->dma_chan) 1444 if (!qp->dma_chan) {
1445 dmaengine_put();
1437 dev_info(&pdev->dev, "Unable to allocate DMA channel, using CPU instead\n"); 1446 dev_info(&pdev->dev, "Unable to allocate DMA channel, using CPU instead\n");
1438 else 1447 }
1439 dmaengine_get();
1440 1448
1441 for (i = 0; i < NTB_QP_DEF_NUM_ENTRIES; i++) { 1449 for (i = 0; i < NTB_QP_DEF_NUM_ENTRIES; i++) {
1442 entry = kzalloc(sizeof(struct ntb_queue_entry), GFP_ATOMIC); 1450 entry = kzalloc(sizeof(struct ntb_queue_entry), GFP_ATOMIC);
@@ -1458,25 +1466,23 @@ ntb_transport_create_queue(void *data, struct pci_dev *pdev,
1458 &qp->tx_free_q); 1466 &qp->tx_free_q);
1459 } 1467 }
1460 1468
1461 tasklet_init(&qp->rx_work, ntb_transport_rx, (unsigned long) qp);
1462
1463 rc = ntb_register_db_callback(qp->ndev, free_queue, qp, 1469 rc = ntb_register_db_callback(qp->ndev, free_queue, qp,
1464 ntb_transport_rxc_db); 1470 ntb_transport_rxc_db);
1465 if (rc) 1471 if (rc)
1466 goto err3; 1472 goto err2;
1467 1473
1468 dev_info(&pdev->dev, "NTB Transport QP %d created\n", qp->qp_num); 1474 dev_info(&pdev->dev, "NTB Transport QP %d created\n", qp->qp_num);
1469 1475
1470 return qp; 1476 return qp;
1471 1477
1472err3:
1473 tasklet_disable(&qp->rx_work);
1474err2: 1478err2:
1475 while ((entry = ntb_list_rm(&qp->ntb_tx_free_q_lock, &qp->tx_free_q))) 1479 while ((entry = ntb_list_rm(&qp->ntb_tx_free_q_lock, &qp->tx_free_q)))
1476 kfree(entry); 1480 kfree(entry);
1477err1: 1481err1:
1478 while ((entry = ntb_list_rm(&qp->ntb_rx_free_q_lock, &qp->rx_free_q))) 1482 while ((entry = ntb_list_rm(&qp->ntb_rx_free_q_lock, &qp->rx_free_q)))
1479 kfree(entry); 1483 kfree(entry);
1484 if (qp->dma_chan)
1485 dmaengine_put();
1480 set_bit(free_queue, &nt->qp_bitmap); 1486 set_bit(free_queue, &nt->qp_bitmap);
1481err: 1487err:
1482 return NULL; 1488 return NULL;
@@ -1515,7 +1521,6 @@ void ntb_transport_free_queue(struct ntb_transport_qp *qp)
1515 } 1521 }
1516 1522
1517 ntb_unregister_db_callback(qp->ndev, qp->qp_num); 1523 ntb_unregister_db_callback(qp->ndev, qp->qp_num);
1518 tasklet_disable(&qp->rx_work);
1519 1524
1520 cancel_delayed_work_sync(&qp->link_work); 1525 cancel_delayed_work_sync(&qp->link_work);
1521 1526
diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
index 0afbbbc55c81..0175041ab728 100644
--- a/drivers/pci/host/pci-tegra.c
+++ b/drivers/pci/host/pci-tegra.c
@@ -25,7 +25,6 @@
25 */ 25 */
26 26
27#include <linux/clk.h> 27#include <linux/clk.h>
28#include <linux/clk/tegra.h>
29#include <linux/delay.h> 28#include <linux/delay.h>
30#include <linux/export.h> 29#include <linux/export.h>
31#include <linux/interrupt.h> 30#include <linux/interrupt.h>
@@ -39,6 +38,7 @@
39#include <linux/of_platform.h> 38#include <linux/of_platform.h>
40#include <linux/pci.h> 39#include <linux/pci.h>
41#include <linux/platform_device.h> 40#include <linux/platform_device.h>
41#include <linux/reset.h>
42#include <linux/sizes.h> 42#include <linux/sizes.h>
43#include <linux/slab.h> 43#include <linux/slab.h>
44#include <linux/tegra-cpuidle.h> 44#include <linux/tegra-cpuidle.h>
@@ -259,10 +259,13 @@ struct tegra_pcie {
259 259
260 struct clk *pex_clk; 260 struct clk *pex_clk;
261 struct clk *afi_clk; 261 struct clk *afi_clk;
262 struct clk *pcie_xclk;
263 struct clk *pll_e; 262 struct clk *pll_e;
264 struct clk *cml_clk; 263 struct clk *cml_clk;
265 264
265 struct reset_control *pex_rst;
266 struct reset_control *afi_rst;
267 struct reset_control *pcie_xrst;
268
266 struct tegra_msi msi; 269 struct tegra_msi msi;
267 270
268 struct list_head ports; 271 struct list_head ports;
@@ -858,7 +861,7 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
858 pads_writel(pcie, value, PADS_CTL); 861 pads_writel(pcie, value, PADS_CTL);
859 862
860 /* take the PCIe interface module out of reset */ 863 /* take the PCIe interface module out of reset */
861 tegra_periph_reset_deassert(pcie->pcie_xclk); 864 reset_control_deassert(pcie->pcie_xrst);
862 865
863 /* finally enable PCIe */ 866 /* finally enable PCIe */
864 value = afi_readl(pcie, AFI_CONFIGURATION); 867 value = afi_readl(pcie, AFI_CONFIGURATION);
@@ -891,9 +894,9 @@ static void tegra_pcie_power_off(struct tegra_pcie *pcie)
891 894
892 /* TODO: disable and unprepare clocks? */ 895 /* TODO: disable and unprepare clocks? */
893 896
894 tegra_periph_reset_assert(pcie->pcie_xclk); 897 reset_control_assert(pcie->pcie_xrst);
895 tegra_periph_reset_assert(pcie->afi_clk); 898 reset_control_assert(pcie->afi_rst);
896 tegra_periph_reset_assert(pcie->pex_clk); 899 reset_control_assert(pcie->pex_rst);
897 900
898 tegra_powergate_power_off(TEGRA_POWERGATE_PCIE); 901 tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
899 902
@@ -921,9 +924,9 @@ static int tegra_pcie_power_on(struct tegra_pcie *pcie)
921 const struct tegra_pcie_soc_data *soc = pcie->soc_data; 924 const struct tegra_pcie_soc_data *soc = pcie->soc_data;
922 int err; 925 int err;
923 926
924 tegra_periph_reset_assert(pcie->pcie_xclk); 927 reset_control_assert(pcie->pcie_xrst);
925 tegra_periph_reset_assert(pcie->afi_clk); 928 reset_control_assert(pcie->afi_rst);
926 tegra_periph_reset_assert(pcie->pex_clk); 929 reset_control_assert(pcie->pex_rst);
927 930
928 tegra_powergate_power_off(TEGRA_POWERGATE_PCIE); 931 tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
929 932
@@ -952,13 +955,14 @@ static int tegra_pcie_power_on(struct tegra_pcie *pcie)
952 } 955 }
953 956
954 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE, 957 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE,
955 pcie->pex_clk); 958 pcie->pex_clk,
959 pcie->pex_rst);
956 if (err) { 960 if (err) {
957 dev_err(pcie->dev, "powerup sequence failed: %d\n", err); 961 dev_err(pcie->dev, "powerup sequence failed: %d\n", err);
958 return err; 962 return err;
959 } 963 }
960 964
961 tegra_periph_reset_deassert(pcie->afi_clk); 965 reset_control_deassert(pcie->afi_rst);
962 966
963 err = clk_prepare_enable(pcie->afi_clk); 967 err = clk_prepare_enable(pcie->afi_clk);
964 if (err < 0) { 968 if (err < 0) {
@@ -996,10 +1000,6 @@ static int tegra_pcie_clocks_get(struct tegra_pcie *pcie)
996 if (IS_ERR(pcie->afi_clk)) 1000 if (IS_ERR(pcie->afi_clk))
997 return PTR_ERR(pcie->afi_clk); 1001 return PTR_ERR(pcie->afi_clk);
998 1002
999 pcie->pcie_xclk = devm_clk_get(pcie->dev, "pcie_xclk");
1000 if (IS_ERR(pcie->pcie_xclk))
1001 return PTR_ERR(pcie->pcie_xclk);
1002
1003 pcie->pll_e = devm_clk_get(pcie->dev, "pll_e"); 1003 pcie->pll_e = devm_clk_get(pcie->dev, "pll_e");
1004 if (IS_ERR(pcie->pll_e)) 1004 if (IS_ERR(pcie->pll_e))
1005 return PTR_ERR(pcie->pll_e); 1005 return PTR_ERR(pcie->pll_e);
@@ -1013,6 +1013,23 @@ static int tegra_pcie_clocks_get(struct tegra_pcie *pcie)
1013 return 0; 1013 return 0;
1014} 1014}
1015 1015
1016static int tegra_pcie_resets_get(struct tegra_pcie *pcie)
1017{
1018 pcie->pex_rst = devm_reset_control_get(pcie->dev, "pex");
1019 if (IS_ERR(pcie->pex_rst))
1020 return PTR_ERR(pcie->pex_rst);
1021
1022 pcie->afi_rst = devm_reset_control_get(pcie->dev, "afi");
1023 if (IS_ERR(pcie->afi_rst))
1024 return PTR_ERR(pcie->afi_rst);
1025
1026 pcie->pcie_xrst = devm_reset_control_get(pcie->dev, "pcie_x");
1027 if (IS_ERR(pcie->pcie_xrst))
1028 return PTR_ERR(pcie->pcie_xrst);
1029
1030 return 0;
1031}
1032
1016static int tegra_pcie_get_resources(struct tegra_pcie *pcie) 1033static int tegra_pcie_get_resources(struct tegra_pcie *pcie)
1017{ 1034{
1018 struct platform_device *pdev = to_platform_device(pcie->dev); 1035 struct platform_device *pdev = to_platform_device(pcie->dev);
@@ -1025,6 +1042,12 @@ static int tegra_pcie_get_resources(struct tegra_pcie *pcie)
1025 return err; 1042 return err;
1026 } 1043 }
1027 1044
1045 err = tegra_pcie_resets_get(pcie);
1046 if (err) {
1047 dev_err(&pdev->dev, "failed to get resets: %d\n", err);
1048 return err;
1049 }
1050
1028 err = tegra_pcie_power_on(pcie); 1051 err = tegra_pcie_power_on(pcie);
1029 if (err) { 1052 if (err) {
1030 dev_err(&pdev->dev, "failed to power up: %d\n", err); 1053 dev_err(&pdev->dev, "failed to power up: %d\n", err);
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index b3b1b9aa8863..3a02717473ad 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -9,10 +9,6 @@
9 * 9 *
10 * Init/reset quirks for USB host controllers should be in the 10 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it. 11 * USB quirks file, where their drivers can access reuse it.
12 *
13 * The bridge optimization stuff has been removed. If you really
14 * have a silly BIOS which is unable to set your host bridge right,
15 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
16 */ 12 */
17 13
18#include <linux/types.h> 14#include <linux/types.h>
diff --git a/drivers/pinctrl/pinctrl-abx500.c b/drivers/pinctrl/pinctrl-abx500.c
index 4780959e11d4..5183e7bb8de3 100644
--- a/drivers/pinctrl/pinctrl-abx500.c
+++ b/drivers/pinctrl/pinctrl-abx500.c
@@ -418,7 +418,7 @@ static int abx500_set_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip,
418 ret = abx500_gpio_set_bits(chip, 418 ret = abx500_gpio_set_bits(chip,
419 AB8500_GPIO_ALTFUN_REG, 419 AB8500_GPIO_ALTFUN_REG,
420 af.alt_bit1, 420 af.alt_bit1,
421 !!(af.alta_val && BIT(0))); 421 !!(af.alta_val & BIT(0)));
422 if (ret < 0) 422 if (ret < 0)
423 goto out; 423 goto out;
424 424
@@ -439,7 +439,7 @@ static int abx500_set_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip,
439 goto out; 439 goto out;
440 440
441 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG, 441 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG,
442 af.alt_bit1, !!(af.altb_val && BIT(0))); 442 af.alt_bit1, !!(af.altb_val & BIT(0)));
443 if (ret < 0) 443 if (ret < 0)
444 goto out; 444 goto out;
445 445
@@ -462,7 +462,7 @@ static int abx500_set_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip,
462 goto out; 462 goto out;
463 463
464 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG, 464 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG,
465 af.alt_bit2, !!(af.altc_val && BIT(1))); 465 af.alt_bit2, !!(af.altc_val & BIT(1)));
466 break; 466 break;
467 467
468 default: 468 default:
diff --git a/drivers/pinctrl/pinctrl-abx500.h b/drivers/pinctrl/pinctrl-abx500.h
index eeca8f973999..82293806e842 100644
--- a/drivers/pinctrl/pinctrl-abx500.h
+++ b/drivers/pinctrl/pinctrl-abx500.h
@@ -1,4 +1,4 @@
1#ifndef PINCTRL_PINCTRL_ABx5O0_H 1#ifndef PINCTRL_PINCTRL_ABx500_H
2#define PINCTRL_PINCTRL_ABx500_H 2#define PINCTRL_PINCTRL_ABx500_H
3 3
4/* Package definitions */ 4/* Package definitions */
diff --git a/drivers/pinctrl/pinctrl-nomadik.c b/drivers/pinctrl/pinctrl-nomadik.c
index 7111c3b59130..983662e846a4 100644
--- a/drivers/pinctrl/pinctrl-nomadik.c
+++ b/drivers/pinctrl/pinctrl-nomadik.c
@@ -4,7 +4,7 @@
4 * Copyright (C) 2008,2009 STMicroelectronics 4 * Copyright (C) 2008,2009 STMicroelectronics
5 * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it> 5 * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
6 * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com> 6 * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com>
7 * Copyright (C) 2011 Linus Walleij <linus.walleij@linaro.org> 7 * Copyright (C) 2011-2013 Linus Walleij <linus.walleij@linaro.org>
8 * 8 *
9 * This program is free software; you can redistribute it and/or modify 9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as 10 * it under the terms of the GNU General Public License version 2 as
@@ -33,7 +33,6 @@
33#include <linux/pinctrl/pinconf.h> 33#include <linux/pinctrl/pinconf.h>
34/* Since we request GPIOs from ourself */ 34/* Since we request GPIOs from ourself */
35#include <linux/pinctrl/consumer.h> 35#include <linux/pinctrl/consumer.h>
36#include <linux/platform_data/pinctrl-nomadik.h>
37#include "pinctrl-nomadik.h" 36#include "pinctrl-nomadik.h"
38#include "core.h" 37#include "core.h"
39 38
@@ -45,6 +44,221 @@
45 * Symbols in this file are called "nmk_gpio" for "nomadik gpio" 44 * Symbols in this file are called "nmk_gpio" for "nomadik gpio"
46 */ 45 */
47 46
47/*
48 * pin configurations are represented by 32-bit integers:
49 *
50 * bit 0.. 8 - Pin Number (512 Pins Maximum)
51 * bit 9..10 - Alternate Function Selection
52 * bit 11..12 - Pull up/down state
53 * bit 13 - Sleep mode behaviour
54 * bit 14 - Direction
55 * bit 15 - Value (if output)
56 * bit 16..18 - SLPM pull up/down state
57 * bit 19..20 - SLPM direction
58 * bit 21..22 - SLPM Value (if output)
59 * bit 23..25 - PDIS value (if input)
60 * bit 26 - Gpio mode
61 * bit 27 - Sleep mode
62 *
63 * to facilitate the definition, the following macros are provided
64 *
65 * PIN_CFG_DEFAULT - default config (0):
66 * pull up/down = disabled
67 * sleep mode = input/wakeup
68 * direction = input
69 * value = low
70 * SLPM direction = same as normal
71 * SLPM pull = same as normal
72 * SLPM value = same as normal
73 *
74 * PIN_CFG - default config with alternate function
75 */
76
77typedef unsigned long pin_cfg_t;
78
79#define PIN_NUM_MASK 0x1ff
80#define PIN_NUM(x) ((x) & PIN_NUM_MASK)
81
82#define PIN_ALT_SHIFT 9
83#define PIN_ALT_MASK (0x3 << PIN_ALT_SHIFT)
84#define PIN_ALT(x) (((x) & PIN_ALT_MASK) >> PIN_ALT_SHIFT)
85#define PIN_GPIO (NMK_GPIO_ALT_GPIO << PIN_ALT_SHIFT)
86#define PIN_ALT_A (NMK_GPIO_ALT_A << PIN_ALT_SHIFT)
87#define PIN_ALT_B (NMK_GPIO_ALT_B << PIN_ALT_SHIFT)
88#define PIN_ALT_C (NMK_GPIO_ALT_C << PIN_ALT_SHIFT)
89
90#define PIN_PULL_SHIFT 11
91#define PIN_PULL_MASK (0x3 << PIN_PULL_SHIFT)
92#define PIN_PULL(x) (((x) & PIN_PULL_MASK) >> PIN_PULL_SHIFT)
93#define PIN_PULL_NONE (NMK_GPIO_PULL_NONE << PIN_PULL_SHIFT)
94#define PIN_PULL_UP (NMK_GPIO_PULL_UP << PIN_PULL_SHIFT)
95#define PIN_PULL_DOWN (NMK_GPIO_PULL_DOWN << PIN_PULL_SHIFT)
96
97#define PIN_SLPM_SHIFT 13
98#define PIN_SLPM_MASK (0x1 << PIN_SLPM_SHIFT)
99#define PIN_SLPM(x) (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT)
100#define PIN_SLPM_MAKE_INPUT (NMK_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT)
101#define PIN_SLPM_NOCHANGE (NMK_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT)
102/* These two replace the above in DB8500v2+ */
103#define PIN_SLPM_WAKEUP_ENABLE (NMK_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT)
104#define PIN_SLPM_WAKEUP_DISABLE (NMK_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT)
105#define PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP PIN_SLPM_WAKEUP_DISABLE
106
107#define PIN_SLPM_GPIO PIN_SLPM_WAKEUP_ENABLE /* In SLPM, pin is a gpio */
108#define PIN_SLPM_ALTFUNC PIN_SLPM_WAKEUP_DISABLE /* In SLPM, pin is altfunc */
109
110#define PIN_DIR_SHIFT 14
111#define PIN_DIR_MASK (0x1 << PIN_DIR_SHIFT)
112#define PIN_DIR(x) (((x) & PIN_DIR_MASK) >> PIN_DIR_SHIFT)
113#define PIN_DIR_INPUT (0 << PIN_DIR_SHIFT)
114#define PIN_DIR_OUTPUT (1 << PIN_DIR_SHIFT)
115
116#define PIN_VAL_SHIFT 15
117#define PIN_VAL_MASK (0x1 << PIN_VAL_SHIFT)
118#define PIN_VAL(x) (((x) & PIN_VAL_MASK) >> PIN_VAL_SHIFT)
119#define PIN_VAL_LOW (0 << PIN_VAL_SHIFT)
120#define PIN_VAL_HIGH (1 << PIN_VAL_SHIFT)
121
122#define PIN_SLPM_PULL_SHIFT 16
123#define PIN_SLPM_PULL_MASK (0x7 << PIN_SLPM_PULL_SHIFT)
124#define PIN_SLPM_PULL(x) \
125 (((x) & PIN_SLPM_PULL_MASK) >> PIN_SLPM_PULL_SHIFT)
126#define PIN_SLPM_PULL_NONE \
127 ((1 + NMK_GPIO_PULL_NONE) << PIN_SLPM_PULL_SHIFT)
128#define PIN_SLPM_PULL_UP \
129 ((1 + NMK_GPIO_PULL_UP) << PIN_SLPM_PULL_SHIFT)
130#define PIN_SLPM_PULL_DOWN \
131 ((1 + NMK_GPIO_PULL_DOWN) << PIN_SLPM_PULL_SHIFT)
132
133#define PIN_SLPM_DIR_SHIFT 19
134#define PIN_SLPM_DIR_MASK (0x3 << PIN_SLPM_DIR_SHIFT)
135#define PIN_SLPM_DIR(x) \
136 (((x) & PIN_SLPM_DIR_MASK) >> PIN_SLPM_DIR_SHIFT)
137#define PIN_SLPM_DIR_INPUT ((1 + 0) << PIN_SLPM_DIR_SHIFT)
138#define PIN_SLPM_DIR_OUTPUT ((1 + 1) << PIN_SLPM_DIR_SHIFT)
139
140#define PIN_SLPM_VAL_SHIFT 21
141#define PIN_SLPM_VAL_MASK (0x3 << PIN_SLPM_VAL_SHIFT)
142#define PIN_SLPM_VAL(x) \
143 (((x) & PIN_SLPM_VAL_MASK) >> PIN_SLPM_VAL_SHIFT)
144#define PIN_SLPM_VAL_LOW ((1 + 0) << PIN_SLPM_VAL_SHIFT)
145#define PIN_SLPM_VAL_HIGH ((1 + 1) << PIN_SLPM_VAL_SHIFT)
146
147#define PIN_SLPM_PDIS_SHIFT 23
148#define PIN_SLPM_PDIS_MASK (0x3 << PIN_SLPM_PDIS_SHIFT)
149#define PIN_SLPM_PDIS(x) \
150 (((x) & PIN_SLPM_PDIS_MASK) >> PIN_SLPM_PDIS_SHIFT)
151#define PIN_SLPM_PDIS_NO_CHANGE (0 << PIN_SLPM_PDIS_SHIFT)
152#define PIN_SLPM_PDIS_DISABLED (1 << PIN_SLPM_PDIS_SHIFT)
153#define PIN_SLPM_PDIS_ENABLED (2 << PIN_SLPM_PDIS_SHIFT)
154
155#define PIN_LOWEMI_SHIFT 25
156#define PIN_LOWEMI_MASK (0x1 << PIN_LOWEMI_SHIFT)
157#define PIN_LOWEMI(x) (((x) & PIN_LOWEMI_MASK) >> PIN_LOWEMI_SHIFT)
158#define PIN_LOWEMI_DISABLED (0 << PIN_LOWEMI_SHIFT)
159#define PIN_LOWEMI_ENABLED (1 << PIN_LOWEMI_SHIFT)
160
161#define PIN_GPIOMODE_SHIFT 26
162#define PIN_GPIOMODE_MASK (0x1 << PIN_GPIOMODE_SHIFT)
163#define PIN_GPIOMODE(x) (((x) & PIN_GPIOMODE_MASK) >> PIN_GPIOMODE_SHIFT)
164#define PIN_GPIOMODE_DISABLED (0 << PIN_GPIOMODE_SHIFT)
165#define PIN_GPIOMODE_ENABLED (1 << PIN_GPIOMODE_SHIFT)
166
167#define PIN_SLEEPMODE_SHIFT 27
168#define PIN_SLEEPMODE_MASK (0x1 << PIN_SLEEPMODE_SHIFT)
169#define PIN_SLEEPMODE(x) (((x) & PIN_SLEEPMODE_MASK) >> PIN_SLEEPMODE_SHIFT)
170#define PIN_SLEEPMODE_DISABLED (0 << PIN_SLEEPMODE_SHIFT)
171#define PIN_SLEEPMODE_ENABLED (1 << PIN_SLEEPMODE_SHIFT)
172
173
174/* Shortcuts. Use these instead of separate DIR, PULL, and VAL. */
175#define PIN_INPUT_PULLDOWN (PIN_DIR_INPUT | PIN_PULL_DOWN)
176#define PIN_INPUT_PULLUP (PIN_DIR_INPUT | PIN_PULL_UP)
177#define PIN_INPUT_NOPULL (PIN_DIR_INPUT | PIN_PULL_NONE)
178#define PIN_OUTPUT_LOW (PIN_DIR_OUTPUT | PIN_VAL_LOW)
179#define PIN_OUTPUT_HIGH (PIN_DIR_OUTPUT | PIN_VAL_HIGH)
180
181#define PIN_SLPM_INPUT_PULLDOWN (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_DOWN)
182#define PIN_SLPM_INPUT_PULLUP (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_UP)
183#define PIN_SLPM_INPUT_NOPULL (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_NONE)
184#define PIN_SLPM_OUTPUT_LOW (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_LOW)
185#define PIN_SLPM_OUTPUT_HIGH (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_HIGH)
186
187#define PIN_CFG_DEFAULT (0)
188
189#define PIN_CFG(num, alt) \
190 (PIN_CFG_DEFAULT |\
191 (PIN_NUM(num) | PIN_##alt))
192
193#define PIN_CFG_INPUT(num, alt, pull) \
194 (PIN_CFG_DEFAULT |\
195 (PIN_NUM(num) | PIN_##alt | PIN_INPUT_##pull))
196
197#define PIN_CFG_OUTPUT(num, alt, val) \
198 (PIN_CFG_DEFAULT |\
199 (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val))
200
201/*
202 * "nmk_gpio" and "NMK_GPIO" stand for "Nomadik GPIO", leaving
203 * the "gpio" namespace for generic and cross-machine functions
204 */
205
206#define GPIO_BLOCK_SHIFT 5
207#define NMK_GPIO_PER_CHIP (1 << GPIO_BLOCK_SHIFT)
208
209/* Register in the logic block */
210#define NMK_GPIO_DAT 0x00
211#define NMK_GPIO_DATS 0x04
212#define NMK_GPIO_DATC 0x08
213#define NMK_GPIO_PDIS 0x0c
214#define NMK_GPIO_DIR 0x10
215#define NMK_GPIO_DIRS 0x14
216#define NMK_GPIO_DIRC 0x18
217#define NMK_GPIO_SLPC 0x1c
218#define NMK_GPIO_AFSLA 0x20
219#define NMK_GPIO_AFSLB 0x24
220#define NMK_GPIO_LOWEMI 0x28
221
222#define NMK_GPIO_RIMSC 0x40
223#define NMK_GPIO_FIMSC 0x44
224#define NMK_GPIO_IS 0x48
225#define NMK_GPIO_IC 0x4c
226#define NMK_GPIO_RWIMSC 0x50
227#define NMK_GPIO_FWIMSC 0x54
228#define NMK_GPIO_WKS 0x58
229/* These appear in DB8540 and later ASICs */
230#define NMK_GPIO_EDGELEVEL 0x5C
231#define NMK_GPIO_LEVEL 0x60
232
233
234/* Pull up/down values */
235enum nmk_gpio_pull {
236 NMK_GPIO_PULL_NONE,
237 NMK_GPIO_PULL_UP,
238 NMK_GPIO_PULL_DOWN,
239};
240
241/* Sleep mode */
242enum nmk_gpio_slpm {
243 NMK_GPIO_SLPM_INPUT,
244 NMK_GPIO_SLPM_WAKEUP_ENABLE = NMK_GPIO_SLPM_INPUT,
245 NMK_GPIO_SLPM_NOCHANGE,
246 NMK_GPIO_SLPM_WAKEUP_DISABLE = NMK_GPIO_SLPM_NOCHANGE,
247};
248
249/*
250 * Platform data to register a block: only the initial gpio/irq number.
251 */
252struct nmk_gpio_platform_data {
253 char *name;
254 int first_gpio;
255 int first_irq;
256 int num_gpio;
257 u32 (*get_secondary_status)(unsigned int bank);
258 void (*set_ioforce)(bool enable);
259 bool supports_sleepmode;
260};
261
48struct nmk_gpio_chip { 262struct nmk_gpio_chip {
49 struct gpio_chip chip; 263 struct gpio_chip chip;
50 struct irq_domain *domain; 264 struct irq_domain *domain;
@@ -1026,7 +1240,7 @@ static const struct irq_domain_ops nmk_gpio_irq_simple_ops = {
1026 1240
1027static int nmk_gpio_probe(struct platform_device *dev) 1241static int nmk_gpio_probe(struct platform_device *dev)
1028{ 1242{
1029 struct nmk_gpio_platform_data *pdata = dev->dev.platform_data; 1243 struct nmk_gpio_platform_data *pdata;
1030 struct device_node *np = dev->dev.of_node; 1244 struct device_node *np = dev->dev.of_node;
1031 struct nmk_gpio_chip *nmk_chip; 1245 struct nmk_gpio_chip *nmk_chip;
1032 struct gpio_chip *chip; 1246 struct gpio_chip *chip;
@@ -1034,32 +1248,24 @@ static int nmk_gpio_probe(struct platform_device *dev)
1034 struct clk *clk; 1248 struct clk *clk;
1035 int secondary_irq; 1249 int secondary_irq;
1036 void __iomem *base; 1250 void __iomem *base;
1037 int irq_start = 0;
1038 int irq; 1251 int irq;
1039 int ret; 1252 int ret;
1040 1253
1041 if (!pdata && !np) { 1254 pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL);
1042 dev_err(&dev->dev, "No platform data or device tree found\n"); 1255 if (!pdata)
1043 return -ENODEV; 1256 return -ENOMEM;
1044 }
1045
1046 if (np) {
1047 pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL);
1048 if (!pdata)
1049 return -ENOMEM;
1050
1051 if (of_get_property(np, "st,supports-sleepmode", NULL))
1052 pdata->supports_sleepmode = true;
1053 1257
1054 if (of_property_read_u32(np, "gpio-bank", &dev->id)) { 1258 if (of_get_property(np, "st,supports-sleepmode", NULL))
1055 dev_err(&dev->dev, "gpio-bank property not found\n"); 1259 pdata->supports_sleepmode = true;
1056 return -EINVAL;
1057 }
1058 1260
1059 pdata->first_gpio = dev->id * NMK_GPIO_PER_CHIP; 1261 if (of_property_read_u32(np, "gpio-bank", &dev->id)) {
1060 pdata->num_gpio = NMK_GPIO_PER_CHIP; 1262 dev_err(&dev->dev, "gpio-bank property not found\n");
1263 return -EINVAL;
1061 } 1264 }
1062 1265
1266 pdata->first_gpio = dev->id * NMK_GPIO_PER_CHIP;
1267 pdata->num_gpio = NMK_GPIO_PER_CHIP;
1268
1063 irq = platform_get_irq(dev, 0); 1269 irq = platform_get_irq(dev, 0);
1064 if (irq < 0) 1270 if (irq < 0)
1065 return irq; 1271 return irq;
@@ -1107,10 +1313,7 @@ static int nmk_gpio_probe(struct platform_device *dev)
1107 clk_enable(nmk_chip->clk); 1313 clk_enable(nmk_chip->clk);
1108 nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI); 1314 nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI);
1109 clk_disable(nmk_chip->clk); 1315 clk_disable(nmk_chip->clk);
1110
1111#ifdef CONFIG_OF_GPIO
1112 chip->of_node = np; 1316 chip->of_node = np;
1113#endif
1114 1317
1115 ret = gpiochip_add(&nmk_chip->chip); 1318 ret = gpiochip_add(&nmk_chip->chip);
1116 if (ret) 1319 if (ret)
@@ -1122,10 +1325,8 @@ static int nmk_gpio_probe(struct platform_device *dev)
1122 1325
1123 platform_set_drvdata(dev, nmk_chip); 1326 platform_set_drvdata(dev, nmk_chip);
1124 1327
1125 if (!np)
1126 irq_start = pdata->first_irq;
1127 nmk_chip->domain = irq_domain_add_simple(np, 1328 nmk_chip->domain = irq_domain_add_simple(np,
1128 NMK_GPIO_PER_CHIP, irq_start, 1329 NMK_GPIO_PER_CHIP, 0,
1129 &nmk_gpio_irq_simple_ops, nmk_chip); 1330 &nmk_gpio_irq_simple_ops, nmk_chip);
1130 if (!nmk_chip->domain) { 1331 if (!nmk_chip->domain) {
1131 dev_err(&dev->dev, "failed to create irqdomain\n"); 1332 dev_err(&dev->dev, "failed to create irqdomain\n");
@@ -1858,11 +2059,10 @@ static int nmk_pinctrl_resume(struct platform_device *pdev)
1858 2059
1859static int nmk_pinctrl_probe(struct platform_device *pdev) 2060static int nmk_pinctrl_probe(struct platform_device *pdev)
1860{ 2061{
1861 const struct platform_device_id *platid = platform_get_device_id(pdev); 2062 const struct of_device_id *match;
1862 struct device_node *np = pdev->dev.of_node; 2063 struct device_node *np = pdev->dev.of_node;
1863 struct device_node *prcm_np; 2064 struct device_node *prcm_np;
1864 struct nmk_pinctrl *npct; 2065 struct nmk_pinctrl *npct;
1865 struct resource *res;
1866 unsigned int version = 0; 2066 unsigned int version = 0;
1867 int i; 2067 int i;
1868 2068
@@ -1870,16 +2070,10 @@ static int nmk_pinctrl_probe(struct platform_device *pdev)
1870 if (!npct) 2070 if (!npct)
1871 return -ENOMEM; 2071 return -ENOMEM;
1872 2072
1873 if (platid) 2073 match = of_match_device(nmk_pinctrl_match, &pdev->dev);
1874 version = platid->driver_data; 2074 if (!match)
1875 else if (np) { 2075 return -ENODEV;
1876 const struct of_device_id *match; 2076 version = (unsigned int) match->data;
1877
1878 match = of_match_device(nmk_pinctrl_match, &pdev->dev);
1879 if (!match)
1880 return -ENODEV;
1881 version = (unsigned int) match->data;
1882 }
1883 2077
1884 /* Poke in other ASIC variants here */ 2078 /* Poke in other ASIC variants here */
1885 if (version == PINCTRL_NMK_STN8815) 2079 if (version == PINCTRL_NMK_STN8815)
@@ -1889,17 +2083,9 @@ static int nmk_pinctrl_probe(struct platform_device *pdev)
1889 if (version == PINCTRL_NMK_DB8540) 2083 if (version == PINCTRL_NMK_DB8540)
1890 nmk_pinctrl_db8540_init(&npct->soc); 2084 nmk_pinctrl_db8540_init(&npct->soc);
1891 2085
1892 if (np) { 2086 prcm_np = of_parse_phandle(np, "prcm", 0);
1893 prcm_np = of_parse_phandle(np, "prcm", 0); 2087 if (prcm_np)
1894 if (prcm_np) 2088 npct->prcm_base = of_iomap(prcm_np, 0);
1895 npct->prcm_base = of_iomap(prcm_np, 0);
1896 }
1897
1898 /* Allow platform passed information to over-write DT. */
1899 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1900 if (res)
1901 npct->prcm_base = devm_ioremap(&pdev->dev, res->start,
1902 resource_size(res));
1903 if (!npct->prcm_base) { 2089 if (!npct->prcm_base) {
1904 if (version == PINCTRL_NMK_STN8815) { 2090 if (version == PINCTRL_NMK_STN8815) {
1905 dev_info(&pdev->dev, 2091 dev_info(&pdev->dev,
@@ -1958,13 +2144,6 @@ static struct platform_driver nmk_gpio_driver = {
1958 .probe = nmk_gpio_probe, 2144 .probe = nmk_gpio_probe,
1959}; 2145};
1960 2146
1961static const struct platform_device_id nmk_pinctrl_id[] = {
1962 { "pinctrl-stn8815", PINCTRL_NMK_STN8815 },
1963 { "pinctrl-db8500", PINCTRL_NMK_DB8500 },
1964 { "pinctrl-db8540", PINCTRL_NMK_DB8540 },
1965 { }
1966};
1967
1968static struct platform_driver nmk_pinctrl_driver = { 2147static struct platform_driver nmk_pinctrl_driver = {
1969 .driver = { 2148 .driver = {
1970 .owner = THIS_MODULE, 2149 .owner = THIS_MODULE,
@@ -1972,7 +2151,6 @@ static struct platform_driver nmk_pinctrl_driver = {
1972 .of_match_table = nmk_pinctrl_match, 2151 .of_match_table = nmk_pinctrl_match,
1973 }, 2152 },
1974 .probe = nmk_pinctrl_probe, 2153 .probe = nmk_pinctrl_probe,
1975 .id_table = nmk_pinctrl_id,
1976#ifdef CONFIG_PM 2154#ifdef CONFIG_PM
1977 .suspend = nmk_pinctrl_suspend, 2155 .suspend = nmk_pinctrl_suspend,
1978 .resume = nmk_pinctrl_resume, 2156 .resume = nmk_pinctrl_resume,
diff --git a/drivers/pinctrl/pinctrl-nomadik.h b/drivers/pinctrl/pinctrl-nomadik.h
index bcd4191e10ea..d8215f1e70c7 100644
--- a/drivers/pinctrl/pinctrl-nomadik.h
+++ b/drivers/pinctrl/pinctrl-nomadik.h
@@ -1,13 +1,23 @@
1#ifndef PINCTRL_PINCTRL_NOMADIK_H 1#ifndef PINCTRL_PINCTRL_NOMADIK_H
2#define PINCTRL_PINCTRL_NOMADIK_H 2#define PINCTRL_PINCTRL_NOMADIK_H
3 3
4#include <linux/platform_data/pinctrl-nomadik.h>
5
6/* Package definitions */ 4/* Package definitions */
7#define PINCTRL_NMK_STN8815 0 5#define PINCTRL_NMK_STN8815 0
8#define PINCTRL_NMK_DB8500 1 6#define PINCTRL_NMK_DB8500 1
9#define PINCTRL_NMK_DB8540 2 7#define PINCTRL_NMK_DB8540 2
10 8
9/* Alternate functions: function C is set in hw by setting both A and B */
10#define NMK_GPIO_ALT_GPIO 0
11#define NMK_GPIO_ALT_A 1
12#define NMK_GPIO_ALT_B 2
13#define NMK_GPIO_ALT_C (NMK_GPIO_ALT_A | NMK_GPIO_ALT_B)
14
15#define NMK_GPIO_ALT_CX_SHIFT 2
16#define NMK_GPIO_ALT_C1 ((1<<NMK_GPIO_ALT_CX_SHIFT) | NMK_GPIO_ALT_C)
17#define NMK_GPIO_ALT_C2 ((2<<NMK_GPIO_ALT_CX_SHIFT) | NMK_GPIO_ALT_C)
18#define NMK_GPIO_ALT_C3 ((3<<NMK_GPIO_ALT_CX_SHIFT) | NMK_GPIO_ALT_C)
19#define NMK_GPIO_ALT_C4 ((4<<NMK_GPIO_ALT_CX_SHIFT) | NMK_GPIO_ALT_C)
20
11#define PRCM_GPIOCR_ALTCX(pin_num,\ 21#define PRCM_GPIOCR_ALTCX(pin_num,\
12 altc1_used, altc1_ri, altc1_cb,\ 22 altc1_used, altc1_ri, altc1_cb,\
13 altc2_used, altc2_ri, altc2_cb,\ 23 altc2_used, altc2_ri, altc2_cb,\
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index e939c28cbf1f..46dddc159286 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -504,6 +504,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
504 data |= (3 << bit); 504 data |= (3 << bit);
505 break; 505 break;
506 default: 506 default:
507 spin_unlock_irqrestore(&bank->slock, flags);
507 dev_err(info->dev, "unsupported pull setting %d\n", 508 dev_err(info->dev, "unsupported pull setting %d\n",
508 pull); 509 pull);
509 return -EINVAL; 510 return -EINVAL;
@@ -1453,8 +1454,8 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev)
1453 if (ctrl->type == RK3188) { 1454 if (ctrl->type == RK3188) {
1454 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1455 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1455 info->reg_pull = devm_ioremap_resource(&pdev->dev, res); 1456 info->reg_pull = devm_ioremap_resource(&pdev->dev, res);
1456 if (IS_ERR(info->reg_base)) 1457 if (IS_ERR(info->reg_pull))
1457 return PTR_ERR(info->reg_base); 1458 return PTR_ERR(info->reg_pull);
1458 } 1459 }
1459 1460
1460 ret = rockchip_gpiolib_register(pdev, info); 1461 ret = rockchip_gpiolib_register(pdev, info);
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
index 009174d07767..bc5eb453a45c 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
@@ -3720,7 +3720,7 @@ static void __iomem *r8a7740_pinmux_portcr(struct sh_pfc *pfc, unsigned int pin)
3720 const struct r8a7740_portcr_group *group = 3720 const struct r8a7740_portcr_group *group =
3721 &r8a7740_portcr_offsets[i]; 3721 &r8a7740_portcr_offsets[i];
3722 3722
3723 if (i <= group->end_pin) 3723 if (pin <= group->end_pin)
3724 return pfc->window->virt + group->offset + pin; 3724 return pfc->window->virt + group->offset + pin;
3725 } 3725 }
3726 3726
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
index 70b522d34821..cc097b693820 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
@@ -2584,7 +2584,7 @@ static void __iomem *sh7372_pinmux_portcr(struct sh_pfc *pfc, unsigned int pin)
2584 const struct sh7372_portcr_group *group = 2584 const struct sh7372_portcr_group *group =
2585 &sh7372_portcr_offsets[i]; 2585 &sh7372_portcr_offsets[i];
2586 2586
2587 if (i <= group->end_pin) 2587 if (pin <= group->end_pin)
2588 return pfc->window->virt + group->offset + pin; 2588 return pfc->window->virt + group->offset + pin;
2589 } 2589 }
2590 2590
diff --git a/drivers/platform/Kconfig b/drivers/platform/Kconfig
index 69616aeaa966..09fde58b12e0 100644
--- a/drivers/platform/Kconfig
+++ b/drivers/platform/Kconfig
@@ -5,3 +5,4 @@ if GOLDFISH
5source "drivers/platform/goldfish/Kconfig" 5source "drivers/platform/goldfish/Kconfig"
6endif 6endif
7 7
8source "drivers/platform/chrome/Kconfig"
diff --git a/drivers/platform/Makefile b/drivers/platform/Makefile
index 8a44a4cd6d1e..3656b7b17b99 100644
--- a/drivers/platform/Makefile
+++ b/drivers/platform/Makefile
@@ -5,3 +5,4 @@
5obj-$(CONFIG_X86) += x86/ 5obj-$(CONFIG_X86) += x86/
6obj-$(CONFIG_OLPC) += olpc/ 6obj-$(CONFIG_OLPC) += olpc/
7obj-$(CONFIG_GOLDFISH) += goldfish/ 7obj-$(CONFIG_GOLDFISH) += goldfish/
8obj-$(CONFIG_CHROME_PLATFORMS) += chrome/
diff --git a/drivers/platform/chrome/Kconfig b/drivers/platform/chrome/Kconfig
new file mode 100644
index 000000000000..b13303e75a34
--- /dev/null
+++ b/drivers/platform/chrome/Kconfig
@@ -0,0 +1,28 @@
1#
2# Platform support for Chrome OS hardware (Chromebooks and Chromeboxes)
3#
4
5menuconfig CHROME_PLATFORMS
6 bool "Platform support for Chrome hardware"
7 depends on X86
8 ---help---
9 Say Y here to get to see options for platform support for
10 various Chromebooks and Chromeboxes. This option alone does
11 not add any kernel code.
12
13 If you say N, all options in this submenu will be skipped and disabled.
14
15if CHROME_PLATFORMS
16
17config CHROMEOS_LAPTOP
18 tristate "Chrome OS Laptop"
19 depends on I2C
20 depends on DMI
21 ---help---
22 This driver instantiates i2c and smbus devices such as
23 light sensors and touchpads.
24
25 If you have a supported Chromebook, choose Y or M here.
26 The module will be called chromeos_laptop.
27
28endif # CHROMEOS_PLATFORMS
diff --git a/drivers/platform/chrome/Makefile b/drivers/platform/chrome/Makefile
new file mode 100644
index 000000000000..015e9195e226
--- /dev/null
+++ b/drivers/platform/chrome/Makefile
@@ -0,0 +1,2 @@
1
2obj-$(CONFIG_CHROMEOS_LAPTOP) += chromeos_laptop.o
diff --git a/drivers/platform/x86/chromeos_laptop.c b/drivers/platform/chrome/chromeos_laptop.c
index 3e5b4497a1d0..3e5b4497a1d0 100644
--- a/drivers/platform/x86/chromeos_laptop.c
+++ b/drivers/platform/chrome/chromeos_laptop.c
diff --git a/drivers/platform/x86/Kconfig b/drivers/platform/x86/Kconfig
index b51a7460cc49..d9dcd37b5a52 100644
--- a/drivers/platform/x86/Kconfig
+++ b/drivers/platform/x86/Kconfig
@@ -79,17 +79,6 @@ config ASUS_LAPTOP
79 79
80 If you have an ACPI-compatible ASUS laptop, say Y or M here. 80 If you have an ACPI-compatible ASUS laptop, say Y or M here.
81 81
82config CHROMEOS_LAPTOP
83 tristate "Chrome OS Laptop"
84 depends on I2C
85 depends on DMI
86 ---help---
87 This driver instantiates i2c and smbus devices such as
88 light sensors and touchpads.
89
90 If you have a supported Chromebook, choose Y or M here.
91 The module will be called chromeos_laptop.
92
93config DELL_LAPTOP 82config DELL_LAPTOP
94 tristate "Dell Laptop Extras" 83 tristate "Dell Laptop Extras"
95 depends on X86 84 depends on X86
diff --git a/drivers/platform/x86/Makefile b/drivers/platform/x86/Makefile
index 5dbe19324351..f0e6aa407ffb 100644
--- a/drivers/platform/x86/Makefile
+++ b/drivers/platform/x86/Makefile
@@ -50,7 +50,6 @@ obj-$(CONFIG_INTEL_MID_POWER_BUTTON) += intel_mid_powerbtn.o
50obj-$(CONFIG_INTEL_OAKTRAIL) += intel_oaktrail.o 50obj-$(CONFIG_INTEL_OAKTRAIL) += intel_oaktrail.o
51obj-$(CONFIG_SAMSUNG_Q10) += samsung-q10.o 51obj-$(CONFIG_SAMSUNG_Q10) += samsung-q10.o
52obj-$(CONFIG_APPLE_GMUX) += apple-gmux.o 52obj-$(CONFIG_APPLE_GMUX) += apple-gmux.o
53obj-$(CONFIG_CHROMEOS_LAPTOP) += chromeos_laptop.o
54obj-$(CONFIG_INTEL_RST) += intel-rst.o 53obj-$(CONFIG_INTEL_RST) += intel-rst.o
55obj-$(CONFIG_INTEL_SMARTCONNECT) += intel-smartconnect.o 54obj-$(CONFIG_INTEL_SMARTCONNECT) += intel-smartconnect.o
56 55
diff --git a/drivers/platform/x86/asus-laptop.c b/drivers/platform/x86/asus-laptop.c
index 0e9c169b42f8..594323a926cf 100644
--- a/drivers/platform/x86/asus-laptop.c
+++ b/drivers/platform/x86/asus-laptop.c
@@ -1494,10 +1494,9 @@ static int asus_input_init(struct asus_laptop *asus)
1494 int error; 1494 int error;
1495 1495
1496 input = input_allocate_device(); 1496 input = input_allocate_device();
1497 if (!input) { 1497 if (!input)
1498 pr_warn("Unable to allocate input device\n");
1499 return -ENOMEM; 1498 return -ENOMEM;
1500 } 1499
1501 input->name = "Asus Laptop extra buttons"; 1500 input->name = "Asus Laptop extra buttons";
1502 input->phys = ASUS_LAPTOP_FILE "/input0"; 1501 input->phys = ASUS_LAPTOP_FILE "/input0";
1503 input->id.bustype = BUS_HOST; 1502 input->id.bustype = BUS_HOST;
diff --git a/drivers/platform/x86/dell-laptop.c b/drivers/platform/x86/dell-laptop.c
index bb77e18b3dd4..c608b1d33f4a 100644
--- a/drivers/platform/x86/dell-laptop.c
+++ b/drivers/platform/x86/dell-laptop.c
@@ -21,6 +21,7 @@
21#include <linux/err.h> 21#include <linux/err.h>
22#include <linux/dmi.h> 22#include <linux/dmi.h>
23#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/rfkill.h>
24#include <linux/power_supply.h> 25#include <linux/power_supply.h>
25#include <linux/acpi.h> 26#include <linux/acpi.h>
26#include <linux/mm.h> 27#include <linux/mm.h>
@@ -89,6 +90,13 @@ static struct platform_driver platform_driver = {
89 90
90static struct platform_device *platform_device; 91static struct platform_device *platform_device;
91static struct backlight_device *dell_backlight_device; 92static struct backlight_device *dell_backlight_device;
93static struct rfkill *wifi_rfkill;
94static struct rfkill *bluetooth_rfkill;
95static struct rfkill *wwan_rfkill;
96static bool force_rfkill;
97
98module_param(force_rfkill, bool, 0444);
99MODULE_PARM_DESC(force_rfkill, "enable rfkill on non whitelisted models");
92 100
93static const struct dmi_system_id dell_device_table[] __initconst = { 101static const struct dmi_system_id dell_device_table[] __initconst = {
94 { 102 {
@@ -355,6 +363,108 @@ dell_send_request(struct calling_interface_buffer *buffer, int class,
355 return buffer; 363 return buffer;
356} 364}
357 365
366/* Derived from information in DellWirelessCtl.cpp:
367 Class 17, select 11 is radio control. It returns an array of 32-bit values.
368
369 Input byte 0 = 0: Wireless information
370
371 result[0]: return code
372 result[1]:
373 Bit 0: Hardware switch supported
374 Bit 1: Wifi locator supported
375 Bit 2: Wifi is supported
376 Bit 3: Bluetooth is supported
377 Bit 4: WWAN is supported
378 Bit 5: Wireless keyboard supported
379 Bits 6-7: Reserved
380 Bit 8: Wifi is installed
381 Bit 9: Bluetooth is installed
382 Bit 10: WWAN is installed
383 Bits 11-15: Reserved
384 Bit 16: Hardware switch is on
385 Bit 17: Wifi is blocked
386 Bit 18: Bluetooth is blocked
387 Bit 19: WWAN is blocked
388 Bits 20-31: Reserved
389 result[2]: NVRAM size in bytes
390 result[3]: NVRAM format version number
391
392 Input byte 0 = 2: Wireless switch configuration
393 result[0]: return code
394 result[1]:
395 Bit 0: Wifi controlled by switch
396 Bit 1: Bluetooth controlled by switch
397 Bit 2: WWAN controlled by switch
398 Bits 3-6: Reserved
399 Bit 7: Wireless switch config locked
400 Bit 8: Wifi locator enabled
401 Bits 9-14: Reserved
402 Bit 15: Wifi locator setting locked
403 Bits 16-31: Reserved
404*/
405
406static int dell_rfkill_set(void *data, bool blocked)
407{
408 int disable = blocked ? 1 : 0;
409 unsigned long radio = (unsigned long)data;
410 int hwswitch_bit = (unsigned long)data - 1;
411
412 get_buffer();
413 dell_send_request(buffer, 17, 11);
414
415 /* If the hardware switch controls this radio, and the hardware
416 switch is disabled, always disable the radio */
417 if ((hwswitch_state & BIT(hwswitch_bit)) &&
418 !(buffer->output[1] & BIT(16)))
419 disable = 1;
420
421 buffer->input[0] = (1 | (radio<<8) | (disable << 16));
422 dell_send_request(buffer, 17, 11);
423
424 release_buffer();
425 return 0;
426}
427
428/* Must be called with the buffer held */
429static void dell_rfkill_update_sw_state(struct rfkill *rfkill, int radio,
430 int status)
431{
432 if (status & BIT(0)) {
433 /* Has hw-switch, sync sw_state to BIOS */
434 int block = rfkill_blocked(rfkill);
435 buffer->input[0] = (1 | (radio << 8) | (block << 16));
436 dell_send_request(buffer, 17, 11);
437 } else {
438 /* No hw-switch, sync BIOS state to sw_state */
439 rfkill_set_sw_state(rfkill, !!(status & BIT(radio + 16)));
440 }
441}
442
443static void dell_rfkill_update_hw_state(struct rfkill *rfkill, int radio,
444 int status)
445{
446 if (hwswitch_state & (BIT(radio - 1)))
447 rfkill_set_hw_state(rfkill, !(status & BIT(16)));
448}
449
450static void dell_rfkill_query(struct rfkill *rfkill, void *data)
451{
452 int status;
453
454 get_buffer();
455 dell_send_request(buffer, 17, 11);
456 status = buffer->output[1];
457
458 dell_rfkill_update_hw_state(rfkill, (unsigned long)data, status);
459
460 release_buffer();
461}
462
463static const struct rfkill_ops dell_rfkill_ops = {
464 .set_block = dell_rfkill_set,
465 .query = dell_rfkill_query,
466};
467
358static struct dentry *dell_laptop_dir; 468static struct dentry *dell_laptop_dir;
359 469
360static int dell_debugfs_show(struct seq_file *s, void *data) 470static int dell_debugfs_show(struct seq_file *s, void *data)
@@ -424,6 +534,136 @@ static const struct file_operations dell_debugfs_fops = {
424 .release = single_release, 534 .release = single_release,
425}; 535};
426 536
537static void dell_update_rfkill(struct work_struct *ignored)
538{
539 int status;
540
541 get_buffer();
542 dell_send_request(buffer, 17, 11);
543 status = buffer->output[1];
544
545 if (wifi_rfkill) {
546 dell_rfkill_update_hw_state(wifi_rfkill, 1, status);
547 dell_rfkill_update_sw_state(wifi_rfkill, 1, status);
548 }
549 if (bluetooth_rfkill) {
550 dell_rfkill_update_hw_state(bluetooth_rfkill, 2, status);
551 dell_rfkill_update_sw_state(bluetooth_rfkill, 2, status);
552 }
553 if (wwan_rfkill) {
554 dell_rfkill_update_hw_state(wwan_rfkill, 3, status);
555 dell_rfkill_update_sw_state(wwan_rfkill, 3, status);
556 }
557
558 release_buffer();
559}
560static DECLARE_DELAYED_WORK(dell_rfkill_work, dell_update_rfkill);
561
562
563static int __init dell_setup_rfkill(void)
564{
565 int status;
566 int ret;
567 const char *product;
568
569 /*
570 * rfkill causes trouble on various non Latitudes, according to Dell
571 * actually testing the rfkill functionality is only done on Latitudes.
572 */
573 product = dmi_get_system_info(DMI_PRODUCT_NAME);
574 if (!force_rfkill && (!product || strncmp(product, "Latitude", 8)))
575 return 0;
576
577 get_buffer();
578 dell_send_request(buffer, 17, 11);
579 status = buffer->output[1];
580 buffer->input[0] = 0x2;
581 dell_send_request(buffer, 17, 11);
582 hwswitch_state = buffer->output[1];
583 release_buffer();
584
585 if (!(status & BIT(0))) {
586 if (force_rfkill) {
587 /* No hwsitch, clear all hw-controlled bits */
588 hwswitch_state &= ~7;
589 } else {
590 /* rfkill is only tested on laptops with a hwswitch */
591 return 0;
592 }
593 }
594
595 if ((status & (1<<2|1<<8)) == (1<<2|1<<8)) {
596 wifi_rfkill = rfkill_alloc("dell-wifi", &platform_device->dev,
597 RFKILL_TYPE_WLAN,
598 &dell_rfkill_ops, (void *) 1);
599 if (!wifi_rfkill) {
600 ret = -ENOMEM;
601 goto err_wifi;
602 }
603 ret = rfkill_register(wifi_rfkill);
604 if (ret)
605 goto err_wifi;
606 }
607
608 if ((status & (1<<3|1<<9)) == (1<<3|1<<9)) {
609 bluetooth_rfkill = rfkill_alloc("dell-bluetooth",
610 &platform_device->dev,
611 RFKILL_TYPE_BLUETOOTH,
612 &dell_rfkill_ops, (void *) 2);
613 if (!bluetooth_rfkill) {
614 ret = -ENOMEM;
615 goto err_bluetooth;
616 }
617 ret = rfkill_register(bluetooth_rfkill);
618 if (ret)
619 goto err_bluetooth;
620 }
621
622 if ((status & (1<<4|1<<10)) == (1<<4|1<<10)) {
623 wwan_rfkill = rfkill_alloc("dell-wwan",
624 &platform_device->dev,
625 RFKILL_TYPE_WWAN,
626 &dell_rfkill_ops, (void *) 3);
627 if (!wwan_rfkill) {
628 ret = -ENOMEM;
629 goto err_wwan;
630 }
631 ret = rfkill_register(wwan_rfkill);
632 if (ret)
633 goto err_wwan;
634 }
635
636 return 0;
637err_wwan:
638 rfkill_destroy(wwan_rfkill);
639 if (bluetooth_rfkill)
640 rfkill_unregister(bluetooth_rfkill);
641err_bluetooth:
642 rfkill_destroy(bluetooth_rfkill);
643 if (wifi_rfkill)
644 rfkill_unregister(wifi_rfkill);
645err_wifi:
646 rfkill_destroy(wifi_rfkill);
647
648 return ret;
649}
650
651static void dell_cleanup_rfkill(void)
652{
653 if (wifi_rfkill) {
654 rfkill_unregister(wifi_rfkill);
655 rfkill_destroy(wifi_rfkill);
656 }
657 if (bluetooth_rfkill) {
658 rfkill_unregister(bluetooth_rfkill);
659 rfkill_destroy(bluetooth_rfkill);
660 }
661 if (wwan_rfkill) {
662 rfkill_unregister(wwan_rfkill);
663 rfkill_destroy(wwan_rfkill);
664 }
665}
666
427static int dell_send_intensity(struct backlight_device *bd) 667static int dell_send_intensity(struct backlight_device *bd)
428{ 668{
429 int ret = 0; 669 int ret = 0;
@@ -515,6 +755,30 @@ static void touchpad_led_exit(void)
515 led_classdev_unregister(&touchpad_led); 755 led_classdev_unregister(&touchpad_led);
516} 756}
517 757
758static bool dell_laptop_i8042_filter(unsigned char data, unsigned char str,
759 struct serio *port)
760{
761 static bool extended;
762
763 if (str & 0x20)
764 return false;
765
766 if (unlikely(data == 0xe0)) {
767 extended = true;
768 return false;
769 } else if (unlikely(extended)) {
770 switch (data) {
771 case 0x8:
772 schedule_delayed_work(&dell_rfkill_work,
773 round_jiffies_relative(HZ / 4));
774 break;
775 }
776 extended = false;
777 }
778
779 return false;
780}
781
518static int __init dell_init(void) 782static int __init dell_init(void)
519{ 783{
520 int max_intensity = 0; 784 int max_intensity = 0;
@@ -557,10 +821,26 @@ static int __init dell_init(void)
557 } 821 }
558 buffer = page_address(bufferpage); 822 buffer = page_address(bufferpage);
559 823
824 ret = dell_setup_rfkill();
825
826 if (ret) {
827 pr_warn("Unable to setup rfkill\n");
828 goto fail_rfkill;
829 }
830
831 ret = i8042_install_filter(dell_laptop_i8042_filter);
832 if (ret) {
833 pr_warn("Unable to install key filter\n");
834 goto fail_filter;
835 }
836
560 if (quirks && quirks->touchpad_led) 837 if (quirks && quirks->touchpad_led)
561 touchpad_led_init(&platform_device->dev); 838 touchpad_led_init(&platform_device->dev);
562 839
563 dell_laptop_dir = debugfs_create_dir("dell_laptop", NULL); 840 dell_laptop_dir = debugfs_create_dir("dell_laptop", NULL);
841 if (dell_laptop_dir != NULL)
842 debugfs_create_file("rfkill", 0444, dell_laptop_dir, NULL,
843 &dell_debugfs_fops);
564 844
565#ifdef CONFIG_ACPI 845#ifdef CONFIG_ACPI
566 /* In the event of an ACPI backlight being available, don't 846 /* In the event of an ACPI backlight being available, don't
@@ -603,6 +883,11 @@ static int __init dell_init(void)
603 return 0; 883 return 0;
604 884
605fail_backlight: 885fail_backlight:
886 i8042_remove_filter(dell_laptop_i8042_filter);
887 cancel_delayed_work_sync(&dell_rfkill_work);
888fail_filter:
889 dell_cleanup_rfkill();
890fail_rfkill:
606 free_page((unsigned long)bufferpage); 891 free_page((unsigned long)bufferpage);
607fail_buffer: 892fail_buffer:
608 platform_device_del(platform_device); 893 platform_device_del(platform_device);
@@ -620,7 +905,10 @@ static void __exit dell_exit(void)
620 debugfs_remove_recursive(dell_laptop_dir); 905 debugfs_remove_recursive(dell_laptop_dir);
621 if (quirks && quirks->touchpad_led) 906 if (quirks && quirks->touchpad_led)
622 touchpad_led_exit(); 907 touchpad_led_exit();
908 i8042_remove_filter(dell_laptop_i8042_filter);
909 cancel_delayed_work_sync(&dell_rfkill_work);
623 backlight_device_unregister(dell_backlight_device); 910 backlight_device_unregister(dell_backlight_device);
911 dell_cleanup_rfkill();
624 if (platform_device) { 912 if (platform_device) {
625 platform_device_unregister(platform_device); 913 platform_device_unregister(platform_device);
626 platform_driver_unregister(&platform_driver); 914 platform_driver_unregister(&platform_driver);
diff --git a/drivers/platform/x86/dell-wmi.c b/drivers/platform/x86/dell-wmi.c
index fa9a2171cc13..60e0900bc117 100644
--- a/drivers/platform/x86/dell-wmi.c
+++ b/drivers/platform/x86/dell-wmi.c
@@ -130,7 +130,8 @@ static const u16 bios_to_linux_keycode[256] __initconst = {
130 KEY_BRIGHTNESSUP, KEY_UNKNOWN, KEY_KBDILLUMTOGGLE, 130 KEY_BRIGHTNESSUP, KEY_UNKNOWN, KEY_KBDILLUMTOGGLE,
131 KEY_UNKNOWN, KEY_SWITCHVIDEOMODE, KEY_UNKNOWN, KEY_UNKNOWN, 131 KEY_UNKNOWN, KEY_SWITCHVIDEOMODE, KEY_UNKNOWN, KEY_UNKNOWN,
132 KEY_SWITCHVIDEOMODE, KEY_UNKNOWN, KEY_UNKNOWN, KEY_PROG2, 132 KEY_SWITCHVIDEOMODE, KEY_UNKNOWN, KEY_UNKNOWN, KEY_PROG2,
133 KEY_UNKNOWN, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 133 KEY_UNKNOWN, KEY_UNKNOWN, KEY_UNKNOWN, KEY_UNKNOWN,
134 KEY_UNKNOWN, KEY_UNKNOWN, KEY_UNKNOWN, KEY_MICMUTE,
134 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 135 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
135 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 136 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
136 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 137 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -139,8 +140,8 @@ static const u16 bios_to_linux_keycode[256] __initconst = {
139 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 140 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
140 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 141 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
141 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 142 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
142 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 143 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
143 KEY_PROG3 144 0, 0, 0, 0, 0, 0, 0, 0, 0, KEY_PROG3
144}; 145};
145 146
146static struct input_dev *dell_wmi_input_dev; 147static struct input_dev *dell_wmi_input_dev;
diff --git a/drivers/platform/x86/eeepc-laptop.c b/drivers/platform/x86/eeepc-laptop.c
index aefcc32e5634..dec68e7a99c7 100644
--- a/drivers/platform/x86/eeepc-laptop.c
+++ b/drivers/platform/x86/eeepc-laptop.c
@@ -1203,10 +1203,8 @@ static int eeepc_input_init(struct eeepc_laptop *eeepc)
1203 int error; 1203 int error;
1204 1204
1205 input = input_allocate_device(); 1205 input = input_allocate_device();
1206 if (!input) { 1206 if (!input)
1207 pr_info("Unable to allocate input device\n");
1208 return -ENOMEM; 1207 return -ENOMEM;
1209 }
1210 1208
1211 input->name = "Asus EeePC extra buttons"; 1209 input->name = "Asus EeePC extra buttons";
1212 input->phys = EEEPC_LAPTOP_FILE "/input0"; 1210 input->phys = EEEPC_LAPTOP_FILE "/input0";
diff --git a/drivers/platform/x86/hp-wmi.c b/drivers/platform/x86/hp-wmi.c
index 1c86fa0857c8..8ba8956b5a48 100644
--- a/drivers/platform/x86/hp-wmi.c
+++ b/drivers/platform/x86/hp-wmi.c
@@ -54,6 +54,7 @@ MODULE_ALIAS("wmi:5FB7F034-2C63-45e9-BE91-3D44E2C707E4");
54#define HPWMI_HARDWARE_QUERY 0x4 54#define HPWMI_HARDWARE_QUERY 0x4
55#define HPWMI_WIRELESS_QUERY 0x5 55#define HPWMI_WIRELESS_QUERY 0x5
56#define HPWMI_HOTKEY_QUERY 0xc 56#define HPWMI_HOTKEY_QUERY 0xc
57#define HPWMI_FEATURE_QUERY 0xd
57#define HPWMI_WIRELESS2_QUERY 0x1b 58#define HPWMI_WIRELESS2_QUERY 0x1b
58#define HPWMI_POSTCODEERROR_QUERY 0x2a 59#define HPWMI_POSTCODEERROR_QUERY 0x2a
59 60
@@ -292,6 +293,17 @@ static int hp_wmi_tablet_state(void)
292 return (state & 0x4) ? 1 : 0; 293 return (state & 0x4) ? 1 : 0;
293} 294}
294 295
296static int hp_wmi_bios_2009_later(void)
297{
298 int state = 0;
299 int ret = hp_wmi_perform_query(HPWMI_FEATURE_QUERY, 0, &state,
300 sizeof(state), sizeof(state));
301 if (ret)
302 return ret;
303
304 return (state & 0x10) ? 1 : 0;
305}
306
295static int hp_wmi_set_block(void *data, bool blocked) 307static int hp_wmi_set_block(void *data, bool blocked)
296{ 308{
297 enum hp_wmi_radio r = (enum hp_wmi_radio) data; 309 enum hp_wmi_radio r = (enum hp_wmi_radio) data;
@@ -871,7 +883,7 @@ static int __init hp_wmi_bios_setup(struct platform_device *device)
871 gps_rfkill = NULL; 883 gps_rfkill = NULL;
872 rfkill2_count = 0; 884 rfkill2_count = 0;
873 885
874 if (hp_wmi_rfkill_setup(device)) 886 if (hp_wmi_bios_2009_later() || hp_wmi_rfkill_setup(device))
875 hp_wmi_rfkill2_setup(device); 887 hp_wmi_rfkill2_setup(device);
876 888
877 err = device_create_file(&device->dev, &dev_attr_display); 889 err = device_create_file(&device->dev, &dev_attr_display);
diff --git a/drivers/platform/x86/ideapad-laptop.c b/drivers/platform/x86/ideapad-laptop.c
index 6788acc22ab9..19ec95147f69 100644
--- a/drivers/platform/x86/ideapad-laptop.c
+++ b/drivers/platform/x86/ideapad-laptop.c
@@ -570,10 +570,8 @@ static int ideapad_input_init(struct ideapad_private *priv)
570 int error; 570 int error;
571 571
572 inputdev = input_allocate_device(); 572 inputdev = input_allocate_device();
573 if (!inputdev) { 573 if (!inputdev)
574 pr_info("Unable to allocate input device\n");
575 return -ENOMEM; 574 return -ENOMEM;
576 }
577 575
578 inputdev->name = "Ideapad extra buttons"; 576 inputdev->name = "Ideapad extra buttons";
579 inputdev->phys = "ideapad/input0"; 577 inputdev->phys = "ideapad/input0";
diff --git a/drivers/platform/x86/intel_mid_powerbtn.c b/drivers/platform/x86/intel_mid_powerbtn.c
index 6b18aba82cfa..8d6775266d66 100644
--- a/drivers/platform/x86/intel_mid_powerbtn.c
+++ b/drivers/platform/x86/intel_mid_powerbtn.c
@@ -66,10 +66,8 @@ static int mfld_pb_probe(struct platform_device *pdev)
66 return -EINVAL; 66 return -EINVAL;
67 67
68 input = input_allocate_device(); 68 input = input_allocate_device();
69 if (!input) { 69 if (!input)
70 dev_err(&pdev->dev, "Input device allocation error\n");
71 return -ENOMEM; 70 return -ENOMEM;
72 }
73 71
74 input->name = pdev->name; 72 input->name = pdev->name;
75 input->phys = "power-button/input0"; 73 input->phys = "power-button/input0";
diff --git a/drivers/platform/x86/intel_scu_ipc.c b/drivers/platform/x86/intel_scu_ipc.c
index d654f831410d..60ea476a9130 100644
--- a/drivers/platform/x86/intel_scu_ipc.c
+++ b/drivers/platform/x86/intel_scu_ipc.c
@@ -58,12 +58,56 @@
58 * message handler is called within firmware. 58 * message handler is called within firmware.
59 */ 59 */
60 60
61#define IPC_BASE_ADDR 0xFF11C000 /* IPC1 base register address */
62#define IPC_MAX_ADDR 0x100 /* Maximum IPC regisers */
63#define IPC_WWBUF_SIZE 20 /* IPC Write buffer Size */ 61#define IPC_WWBUF_SIZE 20 /* IPC Write buffer Size */
64#define IPC_RWBUF_SIZE 20 /* IPC Read buffer Size */ 62#define IPC_RWBUF_SIZE 20 /* IPC Read buffer Size */
65#define IPC_I2C_BASE 0xFF12B000 /* I2C control register base address */ 63#define IPC_IOC 0x100 /* IPC command register IOC bit */
66#define IPC_I2C_MAX_ADDR 0x10 /* Maximum I2C regisers */ 64
65enum {
66 SCU_IPC_LINCROFT,
67 SCU_IPC_PENWELL,
68 SCU_IPC_CLOVERVIEW,
69 SCU_IPC_TANGIER,
70};
71
72/* intel scu ipc driver data*/
73struct intel_scu_ipc_pdata_t {
74 u32 ipc_base;
75 u32 i2c_base;
76 u32 ipc_len;
77 u32 i2c_len;
78 u8 irq_mode;
79};
80
81static struct intel_scu_ipc_pdata_t intel_scu_ipc_pdata[] = {
82 [SCU_IPC_LINCROFT] = {
83 .ipc_base = 0xff11c000,
84 .i2c_base = 0xff12b000,
85 .ipc_len = 0x100,
86 .i2c_len = 0x10,
87 .irq_mode = 0,
88 },
89 [SCU_IPC_PENWELL] = {
90 .ipc_base = 0xff11c000,
91 .i2c_base = 0xff12b000,
92 .ipc_len = 0x100,
93 .i2c_len = 0x10,
94 .irq_mode = 1,
95 },
96 [SCU_IPC_CLOVERVIEW] = {
97 .ipc_base = 0xff11c000,
98 .i2c_base = 0xff12b000,
99 .ipc_len = 0x100,
100 .i2c_len = 0x10,
101 .irq_mode = 1,
102 },
103 [SCU_IPC_TANGIER] = {
104 .ipc_base = 0xff009000,
105 .i2c_base = 0xff00d000,
106 .ipc_len = 0x100,
107 .i2c_len = 0x10,
108 .irq_mode = 0,
109 },
110};
67 111
68static int ipc_probe(struct pci_dev *dev, const struct pci_device_id *id); 112static int ipc_probe(struct pci_dev *dev, const struct pci_device_id *id);
69static void ipc_remove(struct pci_dev *pdev); 113static void ipc_remove(struct pci_dev *pdev);
@@ -72,6 +116,8 @@ struct intel_scu_ipc_dev {
72 struct pci_dev *pdev; 116 struct pci_dev *pdev;
73 void __iomem *ipc_base; 117 void __iomem *ipc_base;
74 void __iomem *i2c_base; 118 void __iomem *i2c_base;
119 struct completion cmd_complete;
120 u8 irq_mode;
75}; 121};
76 122
77static struct intel_scu_ipc_dev ipcdev; /* Only one for now */ 123static struct intel_scu_ipc_dev ipcdev; /* Only one for now */
@@ -98,6 +144,10 @@ static DEFINE_MUTEX(ipclock); /* lock used to prevent multiple call to SCU */
98 */ 144 */
99static inline void ipc_command(u32 cmd) /* Send ipc command */ 145static inline void ipc_command(u32 cmd) /* Send ipc command */
100{ 146{
147 if (ipcdev.irq_mode) {
148 reinit_completion(&ipcdev.cmd_complete);
149 writel(cmd | IPC_IOC, ipcdev.ipc_base);
150 }
101 writel(cmd, ipcdev.ipc_base); 151 writel(cmd, ipcdev.ipc_base);
102} 152}
103 153
@@ -156,6 +206,30 @@ static inline int busy_loop(void) /* Wait till scu status is busy */
156 return 0; 206 return 0;
157} 207}
158 208
209/* Wait till ipc ioc interrupt is received or timeout in 3 HZ */
210static inline int ipc_wait_for_interrupt(void)
211{
212 int status;
213
214 if (!wait_for_completion_timeout(&ipcdev.cmd_complete, 3 * HZ)) {
215 struct device *dev = &ipcdev.pdev->dev;
216 dev_err(dev, "IPC timed out\n");
217 return -ETIMEDOUT;
218 }
219
220 status = ipc_read_status();
221
222 if ((status >> 1) & 1)
223 return -EIO;
224
225 return 0;
226}
227
228int intel_scu_ipc_check_status(void)
229{
230 return ipcdev.irq_mode ? ipc_wait_for_interrupt() : busy_loop();
231}
232
159/* Read/Write power control(PMIC in Langwell, MSIC in PenWell) registers */ 233/* Read/Write power control(PMIC in Langwell, MSIC in PenWell) registers */
160static int pwr_reg_rdwr(u16 *addr, u8 *data, u32 count, u32 op, u32 id) 234static int pwr_reg_rdwr(u16 *addr, u8 *data, u32 count, u32 op, u32 id)
161{ 235{
@@ -196,8 +270,8 @@ static int pwr_reg_rdwr(u16 *addr, u8 *data, u32 count, u32 op, u32 id)
196 ipc_command(4 << 16 | id << 12 | 0 << 8 | op); 270 ipc_command(4 << 16 | id << 12 | 0 << 8 | op);
197 } 271 }
198 272
199 err = busy_loop(); 273 err = intel_scu_ipc_check_status();
200 if (id == IPC_CMD_PCNTRL_R) { /* Read rbuf */ 274 if (!err && id == IPC_CMD_PCNTRL_R) { /* Read rbuf */
201 /* Workaround: values are read as 0 without memcpy_fromio */ 275 /* Workaround: values are read as 0 without memcpy_fromio */
202 memcpy_fromio(cbuf, ipcdev.ipc_base + 0x90, 16); 276 memcpy_fromio(cbuf, ipcdev.ipc_base + 0x90, 16);
203 for (nc = 0; nc < count; nc++) 277 for (nc = 0; nc < count; nc++)
@@ -391,7 +465,7 @@ int intel_scu_ipc_simple_command(int cmd, int sub)
391 return -ENODEV; 465 return -ENODEV;
392 } 466 }
393 ipc_command(sub << 12 | cmd); 467 ipc_command(sub << 12 | cmd);
394 err = busy_loop(); 468 err = intel_scu_ipc_check_status();
395 mutex_unlock(&ipclock); 469 mutex_unlock(&ipclock);
396 return err; 470 return err;
397} 471}
@@ -425,10 +499,12 @@ int intel_scu_ipc_command(int cmd, int sub, u32 *in, int inlen,
425 ipc_data_writel(*in++, 4 * i); 499 ipc_data_writel(*in++, 4 * i);
426 500
427 ipc_command((inlen << 16) | (sub << 12) | cmd); 501 ipc_command((inlen << 16) | (sub << 12) | cmd);
428 err = busy_loop(); 502 err = intel_scu_ipc_check_status();
429 503
430 for (i = 0; i < outlen; i++) 504 if (!err) {
431 *out++ = ipc_data_readl(4 * i); 505 for (i = 0; i < outlen; i++)
506 *out++ = ipc_data_readl(4 * i);
507 }
432 508
433 mutex_unlock(&ipclock); 509 mutex_unlock(&ipclock);
434 return err; 510 return err;
@@ -491,6 +567,9 @@ EXPORT_SYMBOL(intel_scu_ipc_i2c_cntrl);
491 */ 567 */
492static irqreturn_t ioc(int irq, void *dev_id) 568static irqreturn_t ioc(int irq, void *dev_id)
493{ 569{
570 if (ipcdev.irq_mode)
571 complete(&ipcdev.cmd_complete);
572
494 return IRQ_HANDLED; 573 return IRQ_HANDLED;
495} 574}
496 575
@@ -504,13 +583,18 @@ static irqreturn_t ioc(int irq, void *dev_id)
504 */ 583 */
505static int ipc_probe(struct pci_dev *dev, const struct pci_device_id *id) 584static int ipc_probe(struct pci_dev *dev, const struct pci_device_id *id)
506{ 585{
507 int err; 586 int err, pid;
587 struct intel_scu_ipc_pdata_t *pdata;
508 resource_size_t pci_resource; 588 resource_size_t pci_resource;
509 589
510 if (ipcdev.pdev) /* We support only one SCU */ 590 if (ipcdev.pdev) /* We support only one SCU */
511 return -EBUSY; 591 return -EBUSY;
512 592
593 pid = id->driver_data;
594 pdata = &intel_scu_ipc_pdata[pid];
595
513 ipcdev.pdev = pci_dev_get(dev); 596 ipcdev.pdev = pci_dev_get(dev);
597 ipcdev.irq_mode = pdata->irq_mode;
514 598
515 err = pci_enable_device(dev); 599 err = pci_enable_device(dev);
516 if (err) 600 if (err)
@@ -524,14 +608,16 @@ static int ipc_probe(struct pci_dev *dev, const struct pci_device_id *id)
524 if (!pci_resource) 608 if (!pci_resource)
525 return -ENOMEM; 609 return -ENOMEM;
526 610
611 init_completion(&ipcdev.cmd_complete);
612
527 if (request_irq(dev->irq, ioc, 0, "intel_scu_ipc", &ipcdev)) 613 if (request_irq(dev->irq, ioc, 0, "intel_scu_ipc", &ipcdev))
528 return -EBUSY; 614 return -EBUSY;
529 615
530 ipcdev.ipc_base = ioremap_nocache(IPC_BASE_ADDR, IPC_MAX_ADDR); 616 ipcdev.ipc_base = ioremap_nocache(pdata->ipc_base, pdata->ipc_len);
531 if (!ipcdev.ipc_base) 617 if (!ipcdev.ipc_base)
532 return -ENOMEM; 618 return -ENOMEM;
533 619
534 ipcdev.i2c_base = ioremap_nocache(IPC_I2C_BASE, IPC_I2C_MAX_ADDR); 620 ipcdev.i2c_base = ioremap_nocache(pdata->i2c_base, pdata->i2c_len);
535 if (!ipcdev.i2c_base) { 621 if (!ipcdev.i2c_base) {
536 iounmap(ipcdev.ipc_base); 622 iounmap(ipcdev.ipc_base);
537 return -ENOMEM; 623 return -ENOMEM;
@@ -564,7 +650,10 @@ static void ipc_remove(struct pci_dev *pdev)
564} 650}
565 651
566static DEFINE_PCI_DEVICE_TABLE(pci_ids) = { 652static DEFINE_PCI_DEVICE_TABLE(pci_ids) = {
567 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x082a)}, 653 {PCI_VDEVICE(INTEL, 0x082a), SCU_IPC_LINCROFT},
654 {PCI_VDEVICE(INTEL, 0x080e), SCU_IPC_PENWELL},
655 {PCI_VDEVICE(INTEL, 0x08ea), SCU_IPC_CLOVERVIEW},
656 {PCI_VDEVICE(INTEL, 0x11a0), SCU_IPC_TANGIER},
568 { 0,} 657 { 0,}
569}; 658};
570MODULE_DEVICE_TABLE(pci, pci_ids); 659MODULE_DEVICE_TABLE(pci, pci_ids);
diff --git a/drivers/platform/x86/panasonic-laptop.c b/drivers/platform/x86/panasonic-laptop.c
index 10d12b221601..3008fd20572e 100644
--- a/drivers/platform/x86/panasonic-laptop.c
+++ b/drivers/platform/x86/panasonic-laptop.c
@@ -490,11 +490,8 @@ static int acpi_pcc_init_input(struct pcc_acpi *pcc)
490 int error; 490 int error;
491 491
492 input_dev = input_allocate_device(); 492 input_dev = input_allocate_device();
493 if (!input_dev) { 493 if (!input_dev)
494 ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
495 "Couldn't allocate input device for hotkey"));
496 return -ENOMEM; 494 return -ENOMEM;
497 }
498 495
499 input_dev->name = ACPI_PCC_DRIVER_NAME; 496 input_dev->name = ACPI_PCC_DRIVER_NAME;
500 input_dev->phys = ACPI_PCC_INPUT_PHYS; 497 input_dev->phys = ACPI_PCC_INPUT_PHYS;
diff --git a/drivers/platform/x86/sony-laptop.c b/drivers/platform/x86/sony-laptop.c
index 47caab0ea7a1..fb233ae7bb0e 100644
--- a/drivers/platform/x86/sony-laptop.c
+++ b/drivers/platform/x86/sony-laptop.c
@@ -140,12 +140,12 @@ MODULE_PARM_DESC(kbd_backlight_timeout,
140 "on the model (default: no change from current value)"); 140 "on the model (default: no change from current value)");
141 141
142#ifdef CONFIG_PM_SLEEP 142#ifdef CONFIG_PM_SLEEP
143static void sony_nc_kbd_backlight_resume(void);
144static void sony_nc_thermal_resume(void); 143static void sony_nc_thermal_resume(void);
145#endif 144#endif
146static int sony_nc_kbd_backlight_setup(struct platform_device *pd, 145static int sony_nc_kbd_backlight_setup(struct platform_device *pd,
147 unsigned int handle); 146 unsigned int handle);
148static void sony_nc_kbd_backlight_cleanup(struct platform_device *pd); 147static void sony_nc_kbd_backlight_cleanup(struct platform_device *pd,
148 unsigned int handle);
149 149
150static int sony_nc_battery_care_setup(struct platform_device *pd, 150static int sony_nc_battery_care_setup(struct platform_device *pd,
151 unsigned int handle); 151 unsigned int handle);
@@ -304,8 +304,8 @@ static int sony_laptop_input_keycode_map[] = {
304 KEY_FN_F10, /* 14 SONYPI_EVENT_FNKEY_F10 */ 304 KEY_FN_F10, /* 14 SONYPI_EVENT_FNKEY_F10 */
305 KEY_FN_F11, /* 15 SONYPI_EVENT_FNKEY_F11 */ 305 KEY_FN_F11, /* 15 SONYPI_EVENT_FNKEY_F11 */
306 KEY_FN_F12, /* 16 SONYPI_EVENT_FNKEY_F12 */ 306 KEY_FN_F12, /* 16 SONYPI_EVENT_FNKEY_F12 */
307 KEY_FN_F1, /* 17 SONYPI_EVENT_FNKEY_1 */ 307 KEY_FN_1, /* 17 SONYPI_EVENT_FNKEY_1 */
308 KEY_FN_F2, /* 18 SONYPI_EVENT_FNKEY_2 */ 308 KEY_FN_2, /* 18 SONYPI_EVENT_FNKEY_2 */
309 KEY_FN_D, /* 19 SONYPI_EVENT_FNKEY_D */ 309 KEY_FN_D, /* 19 SONYPI_EVENT_FNKEY_D */
310 KEY_FN_E, /* 20 SONYPI_EVENT_FNKEY_E */ 310 KEY_FN_E, /* 20 SONYPI_EVENT_FNKEY_E */
311 KEY_FN_F, /* 21 SONYPI_EVENT_FNKEY_F */ 311 KEY_FN_F, /* 21 SONYPI_EVENT_FNKEY_F */
@@ -1444,7 +1444,7 @@ static void sony_nc_function_cleanup(struct platform_device *pd)
1444 case 0x014b: 1444 case 0x014b:
1445 case 0x014c: 1445 case 0x014c:
1446 case 0x0163: 1446 case 0x0163:
1447 sony_nc_kbd_backlight_cleanup(pd); 1447 sony_nc_kbd_backlight_cleanup(pd, handle);
1448 break; 1448 break;
1449 default: 1449 default:
1450 continue; 1450 continue;
@@ -1486,13 +1486,6 @@ static void sony_nc_function_resume(void)
1486 case 0x0135: 1486 case 0x0135:
1487 sony_nc_rfkill_update(); 1487 sony_nc_rfkill_update();
1488 break; 1488 break;
1489 case 0x0137:
1490 case 0x0143:
1491 case 0x014b:
1492 case 0x014c:
1493 case 0x0163:
1494 sony_nc_kbd_backlight_resume();
1495 break;
1496 default: 1489 default:
1497 continue; 1490 continue;
1498 } 1491 }
@@ -1822,6 +1815,12 @@ static int sony_nc_kbd_backlight_setup(struct platform_device *pd,
1822 int result; 1815 int result;
1823 int ret = 0; 1816 int ret = 0;
1824 1817
1818 if (kbdbl_ctl) {
1819 pr_warn("handle 0x%.4x: keyboard backlight setup already done for 0x%.4x\n",
1820 handle, kbdbl_ctl->handle);
1821 return -EBUSY;
1822 }
1823
1825 /* verify the kbd backlight presence, these handles are not used for 1824 /* verify the kbd backlight presence, these handles are not used for
1826 * keyboard backlight only 1825 * keyboard backlight only
1827 */ 1826 */
@@ -1881,9 +1880,10 @@ outkzalloc:
1881 return ret; 1880 return ret;
1882} 1881}
1883 1882
1884static void sony_nc_kbd_backlight_cleanup(struct platform_device *pd) 1883static void sony_nc_kbd_backlight_cleanup(struct platform_device *pd,
1884 unsigned int handle)
1885{ 1885{
1886 if (kbdbl_ctl) { 1886 if (kbdbl_ctl && handle == kbdbl_ctl->handle) {
1887 device_remove_file(&pd->dev, &kbdbl_ctl->mode_attr); 1887 device_remove_file(&pd->dev, &kbdbl_ctl->mode_attr);
1888 device_remove_file(&pd->dev, &kbdbl_ctl->timeout_attr); 1888 device_remove_file(&pd->dev, &kbdbl_ctl->timeout_attr);
1889 kfree(kbdbl_ctl); 1889 kfree(kbdbl_ctl);
@@ -1891,25 +1891,6 @@ static void sony_nc_kbd_backlight_cleanup(struct platform_device *pd)
1891 } 1891 }
1892} 1892}
1893 1893
1894#ifdef CONFIG_PM_SLEEP
1895static void sony_nc_kbd_backlight_resume(void)
1896{
1897 int ignore = 0;
1898
1899 if (!kbdbl_ctl)
1900 return;
1901
1902 if (kbdbl_ctl->mode == 0)
1903 sony_call_snc_handle(kbdbl_ctl->handle, kbdbl_ctl->base,
1904 &ignore);
1905
1906 if (kbdbl_ctl->timeout != 0)
1907 sony_call_snc_handle(kbdbl_ctl->handle,
1908 (kbdbl_ctl->base + 0x200) |
1909 (kbdbl_ctl->timeout << 0x10), &ignore);
1910}
1911#endif
1912
1913struct battery_care_control { 1894struct battery_care_control {
1914 struct device_attribute attrs[2]; 1895 struct device_attribute attrs[2];
1915 unsigned int handle; 1896 unsigned int handle;
diff --git a/drivers/platform/x86/thinkpad_acpi.c b/drivers/platform/x86/thinkpad_acpi.c
index 05e046aa5e31..58b0274d24cc 100644
--- a/drivers/platform/x86/thinkpad_acpi.c
+++ b/drivers/platform/x86/thinkpad_acpi.c
@@ -6438,7 +6438,12 @@ static struct ibm_struct brightness_driver_data = {
6438#define TPACPI_ALSA_SHRTNAME "ThinkPad Console Audio Control" 6438#define TPACPI_ALSA_SHRTNAME "ThinkPad Console Audio Control"
6439#define TPACPI_ALSA_MIXERNAME TPACPI_ALSA_SHRTNAME 6439#define TPACPI_ALSA_MIXERNAME TPACPI_ALSA_SHRTNAME
6440 6440
6441static int alsa_index = ~((1 << (SNDRV_CARDS - 3)) - 1); /* last three slots */ 6441#if SNDRV_CARDS <= 32
6442#define DEFAULT_ALSA_IDX ~((1 << (SNDRV_CARDS - 3)) - 1)
6443#else
6444#define DEFAULT_ALSA_IDX ~((1 << (32 - 3)) - 1)
6445#endif
6446static int alsa_index = DEFAULT_ALSA_IDX; /* last three slots */
6442static char *alsa_id = "ThinkPadEC"; 6447static char *alsa_id = "ThinkPadEC";
6443static bool alsa_enable = SNDRV_DEFAULT_ENABLE1; 6448static bool alsa_enable = SNDRV_DEFAULT_ENABLE1;
6444 6449
@@ -9163,7 +9168,6 @@ static int __init thinkpad_acpi_module_init(void)
9163 mutex_init(&tpacpi_inputdev_send_mutex); 9168 mutex_init(&tpacpi_inputdev_send_mutex);
9164 tpacpi_inputdev = input_allocate_device(); 9169 tpacpi_inputdev = input_allocate_device();
9165 if (!tpacpi_inputdev) { 9170 if (!tpacpi_inputdev) {
9166 pr_err("unable to allocate input device\n");
9167 thinkpad_acpi_module_exit(); 9171 thinkpad_acpi_module_exit();
9168 return -ENOMEM; 9172 return -ENOMEM;
9169 } else { 9173 } else {
diff --git a/drivers/platform/x86/topstar-laptop.c b/drivers/platform/x86/topstar-laptop.c
index 67897c8740ba..e597de05e6c2 100644
--- a/drivers/platform/x86/topstar-laptop.c
+++ b/drivers/platform/x86/topstar-laptop.c
@@ -97,10 +97,8 @@ static int acpi_topstar_init_hkey(struct topstar_hkey *hkey)
97 int error; 97 int error;
98 98
99 input = input_allocate_device(); 99 input = input_allocate_device();
100 if (!input) { 100 if (!input)
101 pr_err("Unable to allocate input device\n");
102 return -ENOMEM; 101 return -ENOMEM;
103 }
104 102
105 input->name = "Topstar Laptop extra buttons"; 103 input->name = "Topstar Laptop extra buttons";
106 input->phys = "topstar/input0"; 104 input->phys = "topstar/input0";
diff --git a/drivers/platform/x86/toshiba_acpi.c b/drivers/platform/x86/toshiba_acpi.c
index 0cfadb65f7c6..7fce391818d3 100644
--- a/drivers/platform/x86/toshiba_acpi.c
+++ b/drivers/platform/x86/toshiba_acpi.c
@@ -975,10 +975,8 @@ static int toshiba_acpi_setup_keyboard(struct toshiba_acpi_dev *dev)
975 u32 hci_result; 975 u32 hci_result;
976 976
977 dev->hotkey_dev = input_allocate_device(); 977 dev->hotkey_dev = input_allocate_device();
978 if (!dev->hotkey_dev) { 978 if (!dev->hotkey_dev)
979 pr_info("Unable to register input device\n");
980 return -ENOMEM; 979 return -ENOMEM;
981 }
982 980
983 dev->hotkey_dev->name = "Toshiba input device"; 981 dev->hotkey_dev->name = "Toshiba input device";
984 dev->hotkey_dev->phys = "toshiba_acpi/input0"; 982 dev->hotkey_dev->phys = "toshiba_acpi/input0";
diff --git a/drivers/platform/x86/wmi.c b/drivers/platform/x86/wmi.c
index 62e8c221d01e..c2e7b2657aeb 100644
--- a/drivers/platform/x86/wmi.c
+++ b/drivers/platform/x86/wmi.c
@@ -672,8 +672,10 @@ static ssize_t modalias_show(struct device *dev, struct device_attribute *attr,
672 struct wmi_block *wblock; 672 struct wmi_block *wblock;
673 673
674 wblock = dev_get_drvdata(dev); 674 wblock = dev_get_drvdata(dev);
675 if (!wblock) 675 if (!wblock) {
676 return -ENOMEM; 676 strcat(buf, "\n");
677 return strlen(buf);
678 }
677 679
678 wmi_gtoa(wblock->gblock.guid, guid_string); 680 wmi_gtoa(wblock->gblock.guid, guid_string);
679 681
diff --git a/drivers/pnp/driver.c b/drivers/pnp/driver.c
index 6936e0acedcd..f748cc8cbb03 100644
--- a/drivers/pnp/driver.c
+++ b/drivers/pnp/driver.c
@@ -197,6 +197,11 @@ static int pnp_bus_freeze(struct device *dev)
197 return __pnp_bus_suspend(dev, PMSG_FREEZE); 197 return __pnp_bus_suspend(dev, PMSG_FREEZE);
198} 198}
199 199
200static int pnp_bus_poweroff(struct device *dev)
201{
202 return __pnp_bus_suspend(dev, PMSG_HIBERNATE);
203}
204
200static int pnp_bus_resume(struct device *dev) 205static int pnp_bus_resume(struct device *dev)
201{ 206{
202 struct pnp_dev *pnp_dev = to_pnp_dev(dev); 207 struct pnp_dev *pnp_dev = to_pnp_dev(dev);
@@ -234,9 +239,14 @@ static int pnp_bus_resume(struct device *dev)
234} 239}
235 240
236static const struct dev_pm_ops pnp_bus_dev_pm_ops = { 241static const struct dev_pm_ops pnp_bus_dev_pm_ops = {
242 /* Suspend callbacks */
237 .suspend = pnp_bus_suspend, 243 .suspend = pnp_bus_suspend,
238 .freeze = pnp_bus_freeze,
239 .resume = pnp_bus_resume, 244 .resume = pnp_bus_resume,
245 /* Hibernate callbacks */
246 .freeze = pnp_bus_freeze,
247 .thaw = pnp_bus_resume,
248 .poweroff = pnp_bus_poweroff,
249 .restore = pnp_bus_resume,
240}; 250};
241 251
242struct bus_type pnp_bus_type = { 252struct bus_type pnp_bus_type = {
diff --git a/drivers/powercap/powercap_sys.c b/drivers/powercap/powercap_sys.c
index 8d0fe431dbdd..84419af16f77 100644
--- a/drivers/powercap/powercap_sys.c
+++ b/drivers/powercap/powercap_sys.c
@@ -377,9 +377,14 @@ static void create_power_zone_common_attributes(
377 if (power_zone->ops->get_max_energy_range_uj) 377 if (power_zone->ops->get_max_energy_range_uj)
378 power_zone->zone_dev_attrs[count++] = 378 power_zone->zone_dev_attrs[count++] =
379 &dev_attr_max_energy_range_uj.attr; 379 &dev_attr_max_energy_range_uj.attr;
380 if (power_zone->ops->get_energy_uj) 380 if (power_zone->ops->get_energy_uj) {
381 if (power_zone->ops->reset_energy_uj)
382 dev_attr_energy_uj.attr.mode = S_IWUSR | S_IRUGO;
383 else
384 dev_attr_energy_uj.attr.mode = S_IRUGO;
381 power_zone->zone_dev_attrs[count++] = 385 power_zone->zone_dev_attrs[count++] =
382 &dev_attr_energy_uj.attr; 386 &dev_attr_energy_uj.attr;
387 }
383 if (power_zone->ops->get_power_uw) 388 if (power_zone->ops->get_power_uw)
384 power_zone->zone_dev_attrs[count++] = 389 power_zone->zone_dev_attrs[count++] =
385 &dev_attr_power_uw.attr; 390 &dev_attr_power_uw.attr;
diff --git a/drivers/regulator/arizona-micsupp.c b/drivers/regulator/arizona-micsupp.c
index 724706a97dc4..fd3154d86901 100644
--- a/drivers/regulator/arizona-micsupp.c
+++ b/drivers/regulator/arizona-micsupp.c
@@ -174,6 +174,33 @@ static const struct regulator_desc arizona_micsupp = {
174 .owner = THIS_MODULE, 174 .owner = THIS_MODULE,
175}; 175};
176 176
177static const struct regulator_linear_range arizona_micsupp_ext_ranges[] = {
178 REGULATOR_LINEAR_RANGE(900000, 0, 0x14, 25000),
179 REGULATOR_LINEAR_RANGE(1500000, 0x15, 0x27, 100000),
180};
181
182static const struct regulator_desc arizona_micsupp_ext = {
183 .name = "MICVDD",
184 .supply_name = "CPVDD",
185 .type = REGULATOR_VOLTAGE,
186 .n_voltages = 40,
187 .ops = &arizona_micsupp_ops,
188
189 .vsel_reg = ARIZONA_LDO2_CONTROL_1,
190 .vsel_mask = ARIZONA_LDO2_VSEL_MASK,
191 .enable_reg = ARIZONA_MIC_CHARGE_PUMP_1,
192 .enable_mask = ARIZONA_CPMIC_ENA,
193 .bypass_reg = ARIZONA_MIC_CHARGE_PUMP_1,
194 .bypass_mask = ARIZONA_CPMIC_BYPASS,
195
196 .linear_ranges = arizona_micsupp_ext_ranges,
197 .n_linear_ranges = ARRAY_SIZE(arizona_micsupp_ext_ranges),
198
199 .enable_time = 3000,
200
201 .owner = THIS_MODULE,
202};
203
177static const struct regulator_init_data arizona_micsupp_default = { 204static const struct regulator_init_data arizona_micsupp_default = {
178 .constraints = { 205 .constraints = {
179 .valid_ops_mask = REGULATOR_CHANGE_STATUS | 206 .valid_ops_mask = REGULATOR_CHANGE_STATUS |
@@ -186,9 +213,22 @@ static const struct regulator_init_data arizona_micsupp_default = {
186 .num_consumer_supplies = 1, 213 .num_consumer_supplies = 1,
187}; 214};
188 215
216static const struct regulator_init_data arizona_micsupp_ext_default = {
217 .constraints = {
218 .valid_ops_mask = REGULATOR_CHANGE_STATUS |
219 REGULATOR_CHANGE_VOLTAGE |
220 REGULATOR_CHANGE_BYPASS,
221 .min_uV = 900000,
222 .max_uV = 3300000,
223 },
224
225 .num_consumer_supplies = 1,
226};
227
189static int arizona_micsupp_probe(struct platform_device *pdev) 228static int arizona_micsupp_probe(struct platform_device *pdev)
190{ 229{
191 struct arizona *arizona = dev_get_drvdata(pdev->dev.parent); 230 struct arizona *arizona = dev_get_drvdata(pdev->dev.parent);
231 const struct regulator_desc *desc;
192 struct regulator_config config = { }; 232 struct regulator_config config = { };
193 struct arizona_micsupp *micsupp; 233 struct arizona_micsupp *micsupp;
194 int ret; 234 int ret;
@@ -207,7 +247,17 @@ static int arizona_micsupp_probe(struct platform_device *pdev)
207 * default init_data for it. This will be overridden with 247 * default init_data for it. This will be overridden with
208 * platform data if provided. 248 * platform data if provided.
209 */ 249 */
210 micsupp->init_data = arizona_micsupp_default; 250 switch (arizona->type) {
251 case WM5110:
252 desc = &arizona_micsupp_ext;
253 micsupp->init_data = arizona_micsupp_ext_default;
254 break;
255 default:
256 desc = &arizona_micsupp;
257 micsupp->init_data = arizona_micsupp_default;
258 break;
259 }
260
211 micsupp->init_data.consumer_supplies = &micsupp->supply; 261 micsupp->init_data.consumer_supplies = &micsupp->supply;
212 micsupp->supply.supply = "MICVDD"; 262 micsupp->supply.supply = "MICVDD";
213 micsupp->supply.dev_name = dev_name(arizona->dev); 263 micsupp->supply.dev_name = dev_name(arizona->dev);
@@ -226,7 +276,7 @@ static int arizona_micsupp_probe(struct platform_device *pdev)
226 ARIZONA_CPMIC_BYPASS, 0); 276 ARIZONA_CPMIC_BYPASS, 0);
227 277
228 micsupp->regulator = devm_regulator_register(&pdev->dev, 278 micsupp->regulator = devm_regulator_register(&pdev->dev,
229 &arizona_micsupp, 279 desc,
230 &config); 280 &config);
231 if (IS_ERR(micsupp->regulator)) { 281 if (IS_ERR(micsupp->regulator)) {
232 ret = PTR_ERR(micsupp->regulator); 282 ret = PTR_ERR(micsupp->regulator);
diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c
index 6382f0af353b..3fe13130baec 100644
--- a/drivers/regulator/core.c
+++ b/drivers/regulator/core.c
@@ -2184,6 +2184,9 @@ int regulator_list_voltage(struct regulator *regulator, unsigned selector)
2184 struct regulator_ops *ops = rdev->desc->ops; 2184 struct regulator_ops *ops = rdev->desc->ops;
2185 int ret; 2185 int ret;
2186 2186
2187 if (rdev->desc->fixed_uV && rdev->desc->n_voltages == 1 && !selector)
2188 return rdev->desc->fixed_uV;
2189
2187 if (!ops->list_voltage || selector >= rdev->desc->n_voltages) 2190 if (!ops->list_voltage || selector >= rdev->desc->n_voltages)
2188 return -EINVAL; 2191 return -EINVAL;
2189 2192
diff --git a/drivers/regulator/gpio-regulator.c b/drivers/regulator/gpio-regulator.c
index 04406a918c04..234960dc9607 100644
--- a/drivers/regulator/gpio-regulator.c
+++ b/drivers/regulator/gpio-regulator.c
@@ -139,6 +139,7 @@ of_get_gpio_regulator_config(struct device *dev, struct device_node *np)
139 struct property *prop; 139 struct property *prop;
140 const char *regtype; 140 const char *regtype;
141 int proplen, gpio, i; 141 int proplen, gpio, i;
142 int ret;
142 143
143 config = devm_kzalloc(dev, 144 config = devm_kzalloc(dev,
144 sizeof(struct gpio_regulator_config), 145 sizeof(struct gpio_regulator_config),
@@ -202,7 +203,11 @@ of_get_gpio_regulator_config(struct device *dev, struct device_node *np)
202 } 203 }
203 config->nr_states = i; 204 config->nr_states = i;
204 205
205 of_property_read_string(np, "regulator-type", &regtype); 206 ret = of_property_read_string(np, "regulator-type", &regtype);
207 if (ret < 0) {
208 dev_err(dev, "Missing 'regulator-type' property\n");
209 return ERR_PTR(-EINVAL);
210 }
206 211
207 if (!strncmp("voltage", regtype, 7)) 212 if (!strncmp("voltage", regtype, 7))
208 config->type = REGULATOR_VOLTAGE; 213 config->type = REGULATOR_VOLTAGE;
diff --git a/drivers/regulator/pfuze100-regulator.c b/drivers/regulator/pfuze100-regulator.c
index ba67b2c4e2e7..032df3799efb 100644
--- a/drivers/regulator/pfuze100-regulator.c
+++ b/drivers/regulator/pfuze100-regulator.c
@@ -308,9 +308,15 @@ static int pfuze_identify(struct pfuze_chip *pfuze_chip)
308 if (ret) 308 if (ret)
309 return ret; 309 return ret;
310 310
311 if (value & 0x0f) { 311 switch (value & 0x0f) {
312 dev_warn(pfuze_chip->dev, "Illegal ID: %x\n", value); 312 /* Freescale misprogrammed 1-3% of parts prior to week 8 of 2013 as ID=8 */
313 return -ENODEV; 313 case 0x8:
314 dev_info(pfuze_chip->dev, "Assuming misprogrammed ID=0x8");
315 case 0x0:
316 break;
317 default:
318 dev_warn(pfuze_chip->dev, "Illegal ID: %x\n", value);
319 return -ENODEV;
314 } 320 }
315 321
316 ret = regmap_read(pfuze_chip->regmap, PFUZE100_REVID, &value); 322 ret = regmap_read(pfuze_chip->regmap, PFUZE100_REVID, &value);
diff --git a/drivers/s390/block/dasd_eckd.c b/drivers/s390/block/dasd_eckd.c
index cee7e2708a1f..95e45782692f 100644
--- a/drivers/s390/block/dasd_eckd.c
+++ b/drivers/s390/block/dasd_eckd.c
@@ -3224,6 +3224,8 @@ static struct dasd_ccw_req *dasd_eckd_build_cp(struct dasd_device *startdev,
3224 3224
3225 fcx_multitrack = private->features.feature[40] & 0x20; 3225 fcx_multitrack = private->features.feature[40] & 0x20;
3226 data_size = blk_rq_bytes(req); 3226 data_size = blk_rq_bytes(req);
3227 if (data_size % blksize)
3228 return ERR_PTR(-EINVAL);
3227 /* tpm write request add CBC data on each track boundary */ 3229 /* tpm write request add CBC data on each track boundary */
3228 if (rq_data_dir(req) == WRITE) 3230 if (rq_data_dir(req) == WRITE)
3229 data_size += (last_trk - first_trk) * 4; 3231 data_size += (last_trk - first_trk) * 4;
diff --git a/drivers/scsi/3w-9xxx.c b/drivers/scsi/3w-9xxx.c
index 5e1e12c0cf42..0a7325361d29 100644
--- a/drivers/scsi/3w-9xxx.c
+++ b/drivers/scsi/3w-9xxx.c
@@ -2025,7 +2025,8 @@ static struct scsi_host_template driver_template = {
2025 .cmd_per_lun = TW_MAX_CMDS_PER_LUN, 2025 .cmd_per_lun = TW_MAX_CMDS_PER_LUN,
2026 .use_clustering = ENABLE_CLUSTERING, 2026 .use_clustering = ENABLE_CLUSTERING,
2027 .shost_attrs = twa_host_attrs, 2027 .shost_attrs = twa_host_attrs,
2028 .emulated = 1 2028 .emulated = 1,
2029 .no_write_same = 1,
2029}; 2030};
2030 2031
2031/* This function will probe and initialize a card */ 2032/* This function will probe and initialize a card */
diff --git a/drivers/scsi/3w-sas.c b/drivers/scsi/3w-sas.c
index c845bdbeb6c0..4de346017e9f 100644
--- a/drivers/scsi/3w-sas.c
+++ b/drivers/scsi/3w-sas.c
@@ -1600,7 +1600,8 @@ static struct scsi_host_template driver_template = {
1600 .cmd_per_lun = TW_MAX_CMDS_PER_LUN, 1600 .cmd_per_lun = TW_MAX_CMDS_PER_LUN,
1601 .use_clustering = ENABLE_CLUSTERING, 1601 .use_clustering = ENABLE_CLUSTERING,
1602 .shost_attrs = twl_host_attrs, 1602 .shost_attrs = twl_host_attrs,
1603 .emulated = 1 1603 .emulated = 1,
1604 .no_write_same = 1,
1604}; 1605};
1605 1606
1606/* This function will probe and initialize a card */ 1607/* This function will probe and initialize a card */
diff --git a/drivers/scsi/3w-xxxx.c b/drivers/scsi/3w-xxxx.c
index b9276d10b25c..752624e6bc00 100644
--- a/drivers/scsi/3w-xxxx.c
+++ b/drivers/scsi/3w-xxxx.c
@@ -2279,7 +2279,8 @@ static struct scsi_host_template driver_template = {
2279 .cmd_per_lun = TW_MAX_CMDS_PER_LUN, 2279 .cmd_per_lun = TW_MAX_CMDS_PER_LUN,
2280 .use_clustering = ENABLE_CLUSTERING, 2280 .use_clustering = ENABLE_CLUSTERING,
2281 .shost_attrs = tw_host_attrs, 2281 .shost_attrs = tw_host_attrs,
2282 .emulated = 1 2282 .emulated = 1,
2283 .no_write_same = 1,
2283}; 2284};
2284 2285
2285/* This function will probe and initialize a card */ 2286/* This function will probe and initialize a card */
diff --git a/drivers/scsi/aacraid/linit.c b/drivers/scsi/aacraid/linit.c
index f0d432c139d0..4921ed19a027 100644
--- a/drivers/scsi/aacraid/linit.c
+++ b/drivers/scsi/aacraid/linit.c
@@ -1081,6 +1081,7 @@ static struct scsi_host_template aac_driver_template = {
1081#endif 1081#endif
1082 .use_clustering = ENABLE_CLUSTERING, 1082 .use_clustering = ENABLE_CLUSTERING,
1083 .emulated = 1, 1083 .emulated = 1,
1084 .no_write_same = 1,
1084}; 1085};
1085 1086
1086static void __aac_shutdown(struct aac_dev * aac) 1087static void __aac_shutdown(struct aac_dev * aac)
diff --git a/drivers/scsi/arcmsr/arcmsr_hba.c b/drivers/scsi/arcmsr/arcmsr_hba.c
index 97fd450aff09..4f6a30b8e5f9 100644
--- a/drivers/scsi/arcmsr/arcmsr_hba.c
+++ b/drivers/scsi/arcmsr/arcmsr_hba.c
@@ -137,6 +137,7 @@ static struct scsi_host_template arcmsr_scsi_host_template = {
137 .cmd_per_lun = ARCMSR_MAX_CMD_PERLUN, 137 .cmd_per_lun = ARCMSR_MAX_CMD_PERLUN,
138 .use_clustering = ENABLE_CLUSTERING, 138 .use_clustering = ENABLE_CLUSTERING,
139 .shost_attrs = arcmsr_host_attrs, 139 .shost_attrs = arcmsr_host_attrs,
140 .no_write_same = 1,
140}; 141};
141static struct pci_device_id arcmsr_device_id_table[] = { 142static struct pci_device_id arcmsr_device_id_table[] = {
142 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1110)}, 143 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1110)},
diff --git a/drivers/scsi/bfa/bfa_fcs.h b/drivers/scsi/bfa/bfa_fcs.h
index 94d5d0102f7d..42bcb970445a 100644
--- a/drivers/scsi/bfa/bfa_fcs.h
+++ b/drivers/scsi/bfa/bfa_fcs.h
@@ -296,6 +296,7 @@ wwn_t bfa_fcs_lport_get_rport(struct bfa_fcs_lport_s *port, wwn_t wwn,
296struct bfa_fcs_lport_s *bfa_fcs_lookup_port(struct bfa_fcs_s *fcs, 296struct bfa_fcs_lport_s *bfa_fcs_lookup_port(struct bfa_fcs_s *fcs,
297 u16 vf_id, wwn_t lpwwn); 297 u16 vf_id, wwn_t lpwwn);
298 298
299void bfa_fcs_lport_set_symname(struct bfa_fcs_lport_s *port, char *symname);
299void bfa_fcs_lport_get_info(struct bfa_fcs_lport_s *port, 300void bfa_fcs_lport_get_info(struct bfa_fcs_lport_s *port,
300 struct bfa_lport_info_s *port_info); 301 struct bfa_lport_info_s *port_info);
301void bfa_fcs_lport_get_attr(struct bfa_fcs_lport_s *port, 302void bfa_fcs_lport_get_attr(struct bfa_fcs_lport_s *port,
diff --git a/drivers/scsi/bfa/bfa_fcs_lport.c b/drivers/scsi/bfa/bfa_fcs_lport.c
index 2f61a5af3658..f5e4e61a0fd7 100644
--- a/drivers/scsi/bfa/bfa_fcs_lport.c
+++ b/drivers/scsi/bfa/bfa_fcs_lport.c
@@ -1097,6 +1097,17 @@ bfa_fcs_lport_init(struct bfa_fcs_lport_s *lport,
1097 bfa_sm_send_event(lport, BFA_FCS_PORT_SM_CREATE); 1097 bfa_sm_send_event(lport, BFA_FCS_PORT_SM_CREATE);
1098} 1098}
1099 1099
1100void
1101bfa_fcs_lport_set_symname(struct bfa_fcs_lport_s *port,
1102 char *symname)
1103{
1104 strcpy(port->port_cfg.sym_name.symname, symname);
1105
1106 if (bfa_sm_cmp_state(port, bfa_fcs_lport_sm_online))
1107 bfa_fcs_lport_ns_util_send_rspn_id(
1108 BFA_FCS_GET_NS_FROM_PORT(port), NULL);
1109}
1110
1100/* 1111/*
1101 * fcs_lport_api 1112 * fcs_lport_api
1102 */ 1113 */
@@ -5140,9 +5151,6 @@ bfa_fcs_lport_ns_util_send_rspn_id(void *cbarg, struct bfa_fcxp_s *fcxp_alloced)
5140 u8 *psymbl = &symbl[0]; 5151 u8 *psymbl = &symbl[0];
5141 int len; 5152 int len;
5142 5153
5143 if (!bfa_sm_cmp_state(port, bfa_fcs_lport_sm_online))
5144 return;
5145
5146 /* Avoid sending RSPN in the following states. */ 5154 /* Avoid sending RSPN in the following states. */
5147 if (bfa_sm_cmp_state(ns, bfa_fcs_lport_ns_sm_offline) || 5155 if (bfa_sm_cmp_state(ns, bfa_fcs_lport_ns_sm_offline) ||
5148 bfa_sm_cmp_state(ns, bfa_fcs_lport_ns_sm_plogi_sending) || 5156 bfa_sm_cmp_state(ns, bfa_fcs_lport_ns_sm_plogi_sending) ||
diff --git a/drivers/scsi/bfa/bfad_attr.c b/drivers/scsi/bfa/bfad_attr.c
index e9a681d31223..40be670a1cbc 100644
--- a/drivers/scsi/bfa/bfad_attr.c
+++ b/drivers/scsi/bfa/bfad_attr.c
@@ -593,11 +593,8 @@ bfad_im_vport_set_symbolic_name(struct fc_vport *fc_vport)
593 return; 593 return;
594 594
595 spin_lock_irqsave(&bfad->bfad_lock, flags); 595 spin_lock_irqsave(&bfad->bfad_lock, flags);
596 if (strlen(sym_name) > 0) { 596 if (strlen(sym_name) > 0)
597 strcpy(fcs_vport->lport.port_cfg.sym_name.symname, sym_name); 597 bfa_fcs_lport_set_symname(&fcs_vport->lport, sym_name);
598 bfa_fcs_lport_ns_util_send_rspn_id(
599 BFA_FCS_GET_NS_FROM_PORT((&fcs_vport->lport)), NULL);
600 }
601 spin_unlock_irqrestore(&bfad->bfad_lock, flags); 598 spin_unlock_irqrestore(&bfad->bfad_lock, flags);
602} 599}
603 600
diff --git a/drivers/scsi/gdth.c b/drivers/scsi/gdth.c
index ee4fa40a50b1..ce5ef0190bad 100644
--- a/drivers/scsi/gdth.c
+++ b/drivers/scsi/gdth.c
@@ -4684,6 +4684,7 @@ static struct scsi_host_template gdth_template = {
4684 .cmd_per_lun = GDTH_MAXC_P_L, 4684 .cmd_per_lun = GDTH_MAXC_P_L,
4685 .unchecked_isa_dma = 1, 4685 .unchecked_isa_dma = 1,
4686 .use_clustering = ENABLE_CLUSTERING, 4686 .use_clustering = ENABLE_CLUSTERING,
4687 .no_write_same = 1,
4687}; 4688};
4688 4689
4689#ifdef CONFIG_ISA 4690#ifdef CONFIG_ISA
diff --git a/drivers/scsi/hosts.c b/drivers/scsi/hosts.c
index f334859024c0..f2c5005f312a 100644
--- a/drivers/scsi/hosts.c
+++ b/drivers/scsi/hosts.c
@@ -395,6 +395,7 @@ struct Scsi_Host *scsi_host_alloc(struct scsi_host_template *sht, int privsize)
395 shost->use_clustering = sht->use_clustering; 395 shost->use_clustering = sht->use_clustering;
396 shost->ordered_tag = sht->ordered_tag; 396 shost->ordered_tag = sht->ordered_tag;
397 shost->eh_deadline = shost_eh_deadline * HZ; 397 shost->eh_deadline = shost_eh_deadline * HZ;
398 shost->no_write_same = sht->no_write_same;
398 399
399 if (sht->supported_mode == MODE_UNKNOWN) 400 if (sht->supported_mode == MODE_UNKNOWN)
400 /* means we didn't set it ... default to INITIATOR */ 401 /* means we didn't set it ... default to INITIATOR */
diff --git a/drivers/scsi/hpsa.c b/drivers/scsi/hpsa.c
index 22f6432eb475..20a5e6ecf945 100644
--- a/drivers/scsi/hpsa.c
+++ b/drivers/scsi/hpsa.c
@@ -561,6 +561,7 @@ static struct scsi_host_template hpsa_driver_template = {
561 .sdev_attrs = hpsa_sdev_attrs, 561 .sdev_attrs = hpsa_sdev_attrs,
562 .shost_attrs = hpsa_shost_attrs, 562 .shost_attrs = hpsa_shost_attrs,
563 .max_sectors = 8192, 563 .max_sectors = 8192,
564 .no_write_same = 1,
564}; 565};
565 566
566 567
@@ -1288,7 +1289,7 @@ static void complete_scsi_command(struct CommandList *cp)
1288 "has check condition: aborted command: " 1289 "has check condition: aborted command: "
1289 "ASC: 0x%x, ASCQ: 0x%x\n", 1290 "ASC: 0x%x, ASCQ: 0x%x\n",
1290 cp, asc, ascq); 1291 cp, asc, ascq);
1291 cmd->result = DID_SOFT_ERROR << 16; 1292 cmd->result |= DID_SOFT_ERROR << 16;
1292 break; 1293 break;
1293 } 1294 }
1294 /* Must be some other type of check condition */ 1295 /* Must be some other type of check condition */
@@ -4925,7 +4926,7 @@ reinit_after_soft_reset:
4925 hpsa_hba_inquiry(h); 4926 hpsa_hba_inquiry(h);
4926 hpsa_register_scsi(h); /* hook ourselves into SCSI subsystem */ 4927 hpsa_register_scsi(h); /* hook ourselves into SCSI subsystem */
4927 start_controller_lockup_detector(h); 4928 start_controller_lockup_detector(h);
4928 return 1; 4929 return 0;
4929 4930
4930clean4: 4931clean4:
4931 hpsa_free_sg_chain_blocks(h); 4932 hpsa_free_sg_chain_blocks(h);
diff --git a/drivers/scsi/ipr.c b/drivers/scsi/ipr.c
index 36ac1c34ce97..573f4128b6b6 100644
--- a/drivers/scsi/ipr.c
+++ b/drivers/scsi/ipr.c
@@ -6305,7 +6305,8 @@ static struct scsi_host_template driver_template = {
6305 .use_clustering = ENABLE_CLUSTERING, 6305 .use_clustering = ENABLE_CLUSTERING,
6306 .shost_attrs = ipr_ioa_attrs, 6306 .shost_attrs = ipr_ioa_attrs,
6307 .sdev_attrs = ipr_dev_attrs, 6307 .sdev_attrs = ipr_dev_attrs,
6308 .proc_name = IPR_NAME 6308 .proc_name = IPR_NAME,
6309 .no_write_same = 1,
6309}; 6310};
6310 6311
6311/** 6312/**
diff --git a/drivers/scsi/ips.c b/drivers/scsi/ips.c
index 8d5ea8a1e5a6..52a216f21ae5 100644
--- a/drivers/scsi/ips.c
+++ b/drivers/scsi/ips.c
@@ -374,6 +374,7 @@ static struct scsi_host_template ips_driver_template = {
374 .sg_tablesize = IPS_MAX_SG, 374 .sg_tablesize = IPS_MAX_SG,
375 .cmd_per_lun = 3, 375 .cmd_per_lun = 3,
376 .use_clustering = ENABLE_CLUSTERING, 376 .use_clustering = ENABLE_CLUSTERING,
377 .no_write_same = 1,
377}; 378};
378 379
379 380
diff --git a/drivers/scsi/libsas/sas_ata.c b/drivers/scsi/libsas/sas_ata.c
index 161c98efade9..d2895836f9fa 100644
--- a/drivers/scsi/libsas/sas_ata.c
+++ b/drivers/scsi/libsas/sas_ata.c
@@ -211,7 +211,7 @@ static unsigned int sas_ata_qc_issue(struct ata_queued_cmd *qc)
211 qc->tf.nsect = 0; 211 qc->tf.nsect = 0;
212 } 212 }
213 213
214 ata_tf_to_fis(&qc->tf, 1, 0, (u8*)&task->ata_task.fis); 214 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, (u8 *)&task->ata_task.fis);
215 task->uldd_task = qc; 215 task->uldd_task = qc;
216 if (ata_is_atapi(qc->tf.protocol)) { 216 if (ata_is_atapi(qc->tf.protocol)) {
217 memcpy(task->ata_task.atapi_packet, qc->cdb, qc->dev->cdb_len); 217 memcpy(task->ata_task.atapi_packet, qc->cdb, qc->dev->cdb_len);
diff --git a/drivers/scsi/megaraid.c b/drivers/scsi/megaraid.c
index 90c95a3385d1..816db12ef5d5 100644
--- a/drivers/scsi/megaraid.c
+++ b/drivers/scsi/megaraid.c
@@ -4244,6 +4244,7 @@ static struct scsi_host_template megaraid_template = {
4244 .eh_device_reset_handler = megaraid_reset, 4244 .eh_device_reset_handler = megaraid_reset,
4245 .eh_bus_reset_handler = megaraid_reset, 4245 .eh_bus_reset_handler = megaraid_reset,
4246 .eh_host_reset_handler = megaraid_reset, 4246 .eh_host_reset_handler = megaraid_reset,
4247 .no_write_same = 1,
4247}; 4248};
4248 4249
4249static int 4250static int
diff --git a/drivers/scsi/megaraid/megaraid_mbox.c b/drivers/scsi/megaraid/megaraid_mbox.c
index d1a4b82836ea..e2237a97cb9d 100644
--- a/drivers/scsi/megaraid/megaraid_mbox.c
+++ b/drivers/scsi/megaraid/megaraid_mbox.c
@@ -367,6 +367,7 @@ static struct scsi_host_template megaraid_template_g = {
367 .eh_host_reset_handler = megaraid_reset_handler, 367 .eh_host_reset_handler = megaraid_reset_handler,
368 .change_queue_depth = megaraid_change_queue_depth, 368 .change_queue_depth = megaraid_change_queue_depth,
369 .use_clustering = ENABLE_CLUSTERING, 369 .use_clustering = ENABLE_CLUSTERING,
370 .no_write_same = 1,
370 .sdev_attrs = megaraid_sdev_attrs, 371 .sdev_attrs = megaraid_sdev_attrs,
371 .shost_attrs = megaraid_shost_attrs, 372 .shost_attrs = megaraid_shost_attrs,
372}; 373};
diff --git a/drivers/scsi/megaraid/megaraid_sas_base.c b/drivers/scsi/megaraid/megaraid_sas_base.c
index 0a743a5d1647..c99812bf2a73 100644
--- a/drivers/scsi/megaraid/megaraid_sas_base.c
+++ b/drivers/scsi/megaraid/megaraid_sas_base.c
@@ -2148,6 +2148,7 @@ static struct scsi_host_template megasas_template = {
2148 .bios_param = megasas_bios_param, 2148 .bios_param = megasas_bios_param,
2149 .use_clustering = ENABLE_CLUSTERING, 2149 .use_clustering = ENABLE_CLUSTERING,
2150 .change_queue_depth = megasas_change_queue_depth, 2150 .change_queue_depth = megasas_change_queue_depth,
2151 .no_write_same = 1,
2151}; 2152};
2152 2153
2153/** 2154/**
diff --git a/drivers/scsi/pm8001/pm8001_hwi.c b/drivers/scsi/pm8001/pm8001_hwi.c
index f16ece91b94a..0a1296a87d66 100644
--- a/drivers/scsi/pm8001/pm8001_hwi.c
+++ b/drivers/scsi/pm8001/pm8001_hwi.c
@@ -3403,6 +3403,7 @@ hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3403 unsigned long flags; 3403 unsigned long flags;
3404 u8 deviceType = pPayload->sas_identify.dev_type; 3404 u8 deviceType = pPayload->sas_identify.dev_type;
3405 port->port_state = portstate; 3405 port->port_state = portstate;
3406 phy->phy_state = PHY_STATE_LINK_UP_SPC;
3406 PM8001_MSG_DBG(pm8001_ha, 3407 PM8001_MSG_DBG(pm8001_ha,
3407 pm8001_printk("HW_EVENT_SAS_PHY_UP port id = %d, phy id = %d\n", 3408 pm8001_printk("HW_EVENT_SAS_PHY_UP port id = %d, phy id = %d\n",
3408 port_id, phy_id)); 3409 port_id, phy_id));
@@ -3483,6 +3484,7 @@ hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3483 pm8001_printk("HW_EVENT_SATA_PHY_UP port id = %d," 3484 pm8001_printk("HW_EVENT_SATA_PHY_UP port id = %d,"
3484 " phy id = %d\n", port_id, phy_id)); 3485 " phy id = %d\n", port_id, phy_id));
3485 port->port_state = portstate; 3486 port->port_state = portstate;
3487 phy->phy_state = PHY_STATE_LINK_UP_SPC;
3486 port->port_attached = 1; 3488 port->port_attached = 1;
3487 pm8001_get_lrate_mode(phy, link_rate); 3489 pm8001_get_lrate_mode(phy, link_rate);
3488 phy->phy_type |= PORT_TYPE_SATA; 3490 phy->phy_type |= PORT_TYPE_SATA;
diff --git a/drivers/scsi/pm8001/pm8001_hwi.h b/drivers/scsi/pm8001/pm8001_hwi.h
index 6d91e2446542..e4867e690c84 100644
--- a/drivers/scsi/pm8001/pm8001_hwi.h
+++ b/drivers/scsi/pm8001/pm8001_hwi.h
@@ -131,6 +131,10 @@
131#define LINKRATE_30 (0x02 << 8) 131#define LINKRATE_30 (0x02 << 8)
132#define LINKRATE_60 (0x04 << 8) 132#define LINKRATE_60 (0x04 << 8)
133 133
134/* for phy state */
135
136#define PHY_STATE_LINK_UP_SPC 0x1
137
134/* for new SPC controllers MEMBASE III is shared between BIOS and DATA */ 138/* for new SPC controllers MEMBASE III is shared between BIOS and DATA */
135#define GSM_SM_BASE 0x4F0000 139#define GSM_SM_BASE 0x4F0000
136struct mpi_msg_hdr{ 140struct mpi_msg_hdr{
diff --git a/drivers/scsi/pm8001/pm8001_init.c b/drivers/scsi/pm8001/pm8001_init.c
index 34f5f5ffef05..73a120d81b4d 100644
--- a/drivers/scsi/pm8001/pm8001_init.c
+++ b/drivers/scsi/pm8001/pm8001_init.c
@@ -175,20 +175,16 @@ static void pm8001_free(struct pm8001_hba_info *pm8001_ha)
175static void pm8001_tasklet(unsigned long opaque) 175static void pm8001_tasklet(unsigned long opaque)
176{ 176{
177 struct pm8001_hba_info *pm8001_ha; 177 struct pm8001_hba_info *pm8001_ha;
178 u32 vec; 178 struct isr_param *irq_vector;
179 pm8001_ha = (struct pm8001_hba_info *)opaque; 179
180 irq_vector = (struct isr_param *)opaque;
181 pm8001_ha = irq_vector->drv_inst;
180 if (unlikely(!pm8001_ha)) 182 if (unlikely(!pm8001_ha))
181 BUG_ON(1); 183 BUG_ON(1);
182 vec = pm8001_ha->int_vector; 184 PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
183 PM8001_CHIP_DISP->isr(pm8001_ha, vec);
184} 185}
185#endif 186#endif
186 187
187static struct pm8001_hba_info *outq_to_hba(u8 *outq)
188{
189 return container_of((outq - *outq), struct pm8001_hba_info, outq[0]);
190}
191
192/** 188/**
193 * pm8001_interrupt_handler_msix - main MSIX interrupt handler. 189 * pm8001_interrupt_handler_msix - main MSIX interrupt handler.
194 * It obtains the vector number and calls the equivalent bottom 190 * It obtains the vector number and calls the equivalent bottom
@@ -198,18 +194,20 @@ static struct pm8001_hba_info *outq_to_hba(u8 *outq)
198 */ 194 */
199static irqreturn_t pm8001_interrupt_handler_msix(int irq, void *opaque) 195static irqreturn_t pm8001_interrupt_handler_msix(int irq, void *opaque)
200{ 196{
201 struct pm8001_hba_info *pm8001_ha = outq_to_hba(opaque); 197 struct isr_param *irq_vector;
202 u8 outq = *(u8 *)opaque; 198 struct pm8001_hba_info *pm8001_ha;
203 irqreturn_t ret = IRQ_HANDLED; 199 irqreturn_t ret = IRQ_HANDLED;
200 irq_vector = (struct isr_param *)opaque;
201 pm8001_ha = irq_vector->drv_inst;
202
204 if (unlikely(!pm8001_ha)) 203 if (unlikely(!pm8001_ha))
205 return IRQ_NONE; 204 return IRQ_NONE;
206 if (!PM8001_CHIP_DISP->is_our_interupt(pm8001_ha)) 205 if (!PM8001_CHIP_DISP->is_our_interupt(pm8001_ha))
207 return IRQ_NONE; 206 return IRQ_NONE;
208 pm8001_ha->int_vector = outq;
209#ifdef PM8001_USE_TASKLET 207#ifdef PM8001_USE_TASKLET
210 tasklet_schedule(&pm8001_ha->tasklet); 208 tasklet_schedule(&pm8001_ha->tasklet[irq_vector->irq_id]);
211#else 209#else
212 ret = PM8001_CHIP_DISP->isr(pm8001_ha, outq); 210 ret = PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
213#endif 211#endif
214 return ret; 212 return ret;
215} 213}
@@ -230,9 +228,8 @@ static irqreturn_t pm8001_interrupt_handler_intx(int irq, void *dev_id)
230 if (!PM8001_CHIP_DISP->is_our_interupt(pm8001_ha)) 228 if (!PM8001_CHIP_DISP->is_our_interupt(pm8001_ha))
231 return IRQ_NONE; 229 return IRQ_NONE;
232 230
233 pm8001_ha->int_vector = 0;
234#ifdef PM8001_USE_TASKLET 231#ifdef PM8001_USE_TASKLET
235 tasklet_schedule(&pm8001_ha->tasklet); 232 tasklet_schedule(&pm8001_ha->tasklet[0]);
236#else 233#else
237 ret = PM8001_CHIP_DISP->isr(pm8001_ha, 0); 234 ret = PM8001_CHIP_DISP->isr(pm8001_ha, 0);
238#endif 235#endif
@@ -457,7 +454,7 @@ static struct pm8001_hba_info *pm8001_pci_alloc(struct pci_dev *pdev,
457{ 454{
458 struct pm8001_hba_info *pm8001_ha; 455 struct pm8001_hba_info *pm8001_ha;
459 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); 456 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
460 457 int j;
461 458
462 pm8001_ha = sha->lldd_ha; 459 pm8001_ha = sha->lldd_ha;
463 if (!pm8001_ha) 460 if (!pm8001_ha)
@@ -480,12 +477,14 @@ static struct pm8001_hba_info *pm8001_pci_alloc(struct pci_dev *pdev,
480 pm8001_ha->iomb_size = IOMB_SIZE_SPC; 477 pm8001_ha->iomb_size = IOMB_SIZE_SPC;
481 478
482#ifdef PM8001_USE_TASKLET 479#ifdef PM8001_USE_TASKLET
483 /** 480 /* Tasklet for non msi-x interrupt handler */
484 * default tasklet for non msi-x interrupt handler/first msi-x 481 if ((!pdev->msix_cap) || (pm8001_ha->chip_id == chip_8001))
485 * interrupt handler 482 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
486 **/ 483 (unsigned long)&(pm8001_ha->irq_vector[0]));
487 tasklet_init(&pm8001_ha->tasklet, pm8001_tasklet, 484 else
488 (unsigned long)pm8001_ha); 485 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
486 tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
487 (unsigned long)&(pm8001_ha->irq_vector[j]));
489#endif 488#endif
490 pm8001_ioremap(pm8001_ha); 489 pm8001_ioremap(pm8001_ha);
491 if (!pm8001_alloc(pm8001_ha, ent)) 490 if (!pm8001_alloc(pm8001_ha, ent))
@@ -733,19 +732,20 @@ static u32 pm8001_setup_msix(struct pm8001_hba_info *pm8001_ha)
733 "pci_enable_msix request ret:%d no of intr %d\n", 732 "pci_enable_msix request ret:%d no of intr %d\n",
734 rc, pm8001_ha->number_of_intr)); 733 rc, pm8001_ha->number_of_intr));
735 734
736 for (i = 0; i < number_of_intr; i++)
737 pm8001_ha->outq[i] = i;
738 735
739 for (i = 0; i < number_of_intr; i++) { 736 for (i = 0; i < number_of_intr; i++) {
740 snprintf(intr_drvname[i], sizeof(intr_drvname[0]), 737 snprintf(intr_drvname[i], sizeof(intr_drvname[0]),
741 DRV_NAME"%d", i); 738 DRV_NAME"%d", i);
739 pm8001_ha->irq_vector[i].irq_id = i;
740 pm8001_ha->irq_vector[i].drv_inst = pm8001_ha;
741
742 if (request_irq(pm8001_ha->msix_entries[i].vector, 742 if (request_irq(pm8001_ha->msix_entries[i].vector,
743 pm8001_interrupt_handler_msix, flag, 743 pm8001_interrupt_handler_msix, flag,
744 intr_drvname[i], &pm8001_ha->outq[i])) { 744 intr_drvname[i], &(pm8001_ha->irq_vector[i]))) {
745 for (j = 0; j < i; j++) 745 for (j = 0; j < i; j++)
746 free_irq( 746 free_irq(
747 pm8001_ha->msix_entries[j].vector, 747 pm8001_ha->msix_entries[j].vector,
748 &pm8001_ha->outq[j]); 748 &(pm8001_ha->irq_vector[i]));
749 pci_disable_msix(pm8001_ha->pdev); 749 pci_disable_msix(pm8001_ha->pdev);
750 break; 750 break;
751 } 751 }
@@ -907,7 +907,7 @@ static void pm8001_pci_remove(struct pci_dev *pdev)
907{ 907{
908 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 908 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
909 struct pm8001_hba_info *pm8001_ha; 909 struct pm8001_hba_info *pm8001_ha;
910 int i; 910 int i, j;
911 pm8001_ha = sha->lldd_ha; 911 pm8001_ha = sha->lldd_ha;
912 sas_unregister_ha(sha); 912 sas_unregister_ha(sha);
913 sas_remove_host(pm8001_ha->shost); 913 sas_remove_host(pm8001_ha->shost);
@@ -921,13 +921,18 @@ static void pm8001_pci_remove(struct pci_dev *pdev)
921 synchronize_irq(pm8001_ha->msix_entries[i].vector); 921 synchronize_irq(pm8001_ha->msix_entries[i].vector);
922 for (i = 0; i < pm8001_ha->number_of_intr; i++) 922 for (i = 0; i < pm8001_ha->number_of_intr; i++)
923 free_irq(pm8001_ha->msix_entries[i].vector, 923 free_irq(pm8001_ha->msix_entries[i].vector,
924 &pm8001_ha->outq[i]); 924 &(pm8001_ha->irq_vector[i]));
925 pci_disable_msix(pdev); 925 pci_disable_msix(pdev);
926#else 926#else
927 free_irq(pm8001_ha->irq, sha); 927 free_irq(pm8001_ha->irq, sha);
928#endif 928#endif
929#ifdef PM8001_USE_TASKLET 929#ifdef PM8001_USE_TASKLET
930 tasklet_kill(&pm8001_ha->tasklet); 930 /* For non-msix and msix interrupts */
931 if ((!pdev->msix_cap) || (pm8001_ha->chip_id == chip_8001))
932 tasklet_kill(&pm8001_ha->tasklet[0]);
933 else
934 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
935 tasklet_kill(&pm8001_ha->tasklet[j]);
931#endif 936#endif
932 pm8001_free(pm8001_ha); 937 pm8001_free(pm8001_ha);
933 kfree(sha->sas_phy); 938 kfree(sha->sas_phy);
@@ -948,7 +953,7 @@ static int pm8001_pci_suspend(struct pci_dev *pdev, pm_message_t state)
948{ 953{
949 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 954 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
950 struct pm8001_hba_info *pm8001_ha; 955 struct pm8001_hba_info *pm8001_ha;
951 int i; 956 int i, j;
952 u32 device_state; 957 u32 device_state;
953 pm8001_ha = sha->lldd_ha; 958 pm8001_ha = sha->lldd_ha;
954 flush_workqueue(pm8001_wq); 959 flush_workqueue(pm8001_wq);
@@ -964,13 +969,18 @@ static int pm8001_pci_suspend(struct pci_dev *pdev, pm_message_t state)
964 synchronize_irq(pm8001_ha->msix_entries[i].vector); 969 synchronize_irq(pm8001_ha->msix_entries[i].vector);
965 for (i = 0; i < pm8001_ha->number_of_intr; i++) 970 for (i = 0; i < pm8001_ha->number_of_intr; i++)
966 free_irq(pm8001_ha->msix_entries[i].vector, 971 free_irq(pm8001_ha->msix_entries[i].vector,
967 &pm8001_ha->outq[i]); 972 &(pm8001_ha->irq_vector[i]));
968 pci_disable_msix(pdev); 973 pci_disable_msix(pdev);
969#else 974#else
970 free_irq(pm8001_ha->irq, sha); 975 free_irq(pm8001_ha->irq, sha);
971#endif 976#endif
972#ifdef PM8001_USE_TASKLET 977#ifdef PM8001_USE_TASKLET
973 tasklet_kill(&pm8001_ha->tasklet); 978 /* For non-msix and msix interrupts */
979 if ((!pdev->msix_cap) || (pm8001_ha->chip_id == chip_8001))
980 tasklet_kill(&pm8001_ha->tasklet[0]);
981 else
982 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
983 tasklet_kill(&pm8001_ha->tasklet[j]);
974#endif 984#endif
975 device_state = pci_choose_state(pdev, state); 985 device_state = pci_choose_state(pdev, state);
976 pm8001_printk("pdev=0x%p, slot=%s, entering " 986 pm8001_printk("pdev=0x%p, slot=%s, entering "
@@ -993,7 +1003,7 @@ static int pm8001_pci_resume(struct pci_dev *pdev)
993 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 1003 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
994 struct pm8001_hba_info *pm8001_ha; 1004 struct pm8001_hba_info *pm8001_ha;
995 int rc; 1005 int rc;
996 u8 i = 0; 1006 u8 i = 0, j;
997 u32 device_state; 1007 u32 device_state;
998 pm8001_ha = sha->lldd_ha; 1008 pm8001_ha = sha->lldd_ha;
999 device_state = pdev->current_state; 1009 device_state = pdev->current_state;
@@ -1033,10 +1043,14 @@ static int pm8001_pci_resume(struct pci_dev *pdev)
1033 if (rc) 1043 if (rc)
1034 goto err_out_disable; 1044 goto err_out_disable;
1035#ifdef PM8001_USE_TASKLET 1045#ifdef PM8001_USE_TASKLET
1036 /* default tasklet for non msi-x interrupt handler/first msi-x 1046 /* Tasklet for non msi-x interrupt handler */
1037 * interrupt handler */ 1047 if ((!pdev->msix_cap) || (pm8001_ha->chip_id == chip_8001))
1038 tasklet_init(&pm8001_ha->tasklet, pm8001_tasklet, 1048 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
1039 (unsigned long)pm8001_ha); 1049 (unsigned long)&(pm8001_ha->irq_vector[0]));
1050 else
1051 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1052 tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
1053 (unsigned long)&(pm8001_ha->irq_vector[j]));
1040#endif 1054#endif
1041 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0); 1055 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1042 if (pm8001_ha->chip_id != chip_8001) { 1056 if (pm8001_ha->chip_id != chip_8001) {
@@ -1169,6 +1183,7 @@ module_exit(pm8001_exit);
1169MODULE_AUTHOR("Jack Wang <jack_wang@usish.com>"); 1183MODULE_AUTHOR("Jack Wang <jack_wang@usish.com>");
1170MODULE_AUTHOR("Anand Kumar Santhanam <AnandKumar.Santhanam@pmcs.com>"); 1184MODULE_AUTHOR("Anand Kumar Santhanam <AnandKumar.Santhanam@pmcs.com>");
1171MODULE_AUTHOR("Sangeetha Gnanasekaran <Sangeetha.Gnanasekaran@pmcs.com>"); 1185MODULE_AUTHOR("Sangeetha Gnanasekaran <Sangeetha.Gnanasekaran@pmcs.com>");
1186MODULE_AUTHOR("Nikith Ganigarakoppal <Nikith.Ganigarakoppal@pmcs.com>");
1172MODULE_DESCRIPTION( 1187MODULE_DESCRIPTION(
1173 "PMC-Sierra PM8001/8081/8088/8089/8074/8076/8077 " 1188 "PMC-Sierra PM8001/8081/8088/8089/8074/8076/8077 "
1174 "SAS/SATA controller driver"); 1189 "SAS/SATA controller driver");
diff --git a/drivers/scsi/pm8001/pm8001_sas.c b/drivers/scsi/pm8001/pm8001_sas.c
index f4eb18e51631..f50ac44b950e 100644
--- a/drivers/scsi/pm8001/pm8001_sas.c
+++ b/drivers/scsi/pm8001/pm8001_sas.c
@@ -1098,15 +1098,17 @@ int pm8001_lu_reset(struct domain_device *dev, u8 *lun)
1098 struct pm8001_tmf_task tmf_task; 1098 struct pm8001_tmf_task tmf_task;
1099 struct pm8001_device *pm8001_dev = dev->lldd_dev; 1099 struct pm8001_device *pm8001_dev = dev->lldd_dev;
1100 struct pm8001_hba_info *pm8001_ha = pm8001_find_ha_by_dev(dev); 1100 struct pm8001_hba_info *pm8001_ha = pm8001_find_ha_by_dev(dev);
1101 DECLARE_COMPLETION_ONSTACK(completion_setstate);
1101 if (dev_is_sata(dev)) { 1102 if (dev_is_sata(dev)) {
1102 struct sas_phy *phy = sas_get_local_phy(dev); 1103 struct sas_phy *phy = sas_get_local_phy(dev);
1103 rc = pm8001_exec_internal_task_abort(pm8001_ha, pm8001_dev , 1104 rc = pm8001_exec_internal_task_abort(pm8001_ha, pm8001_dev ,
1104 dev, 1, 0); 1105 dev, 1, 0);
1105 rc = sas_phy_reset(phy, 1); 1106 rc = sas_phy_reset(phy, 1);
1106 sas_put_local_phy(phy); 1107 sas_put_local_phy(phy);
1108 pm8001_dev->setds_completion = &completion_setstate;
1107 rc = PM8001_CHIP_DISP->set_dev_state_req(pm8001_ha, 1109 rc = PM8001_CHIP_DISP->set_dev_state_req(pm8001_ha,
1108 pm8001_dev, 0x01); 1110 pm8001_dev, 0x01);
1109 msleep(2000); 1111 wait_for_completion(&completion_setstate);
1110 } else { 1112 } else {
1111 tmf_task.tmf = TMF_LU_RESET; 1113 tmf_task.tmf = TMF_LU_RESET;
1112 rc = pm8001_issue_ssp_tmf(dev, lun, &tmf_task); 1114 rc = pm8001_issue_ssp_tmf(dev, lun, &tmf_task);
diff --git a/drivers/scsi/pm8001/pm8001_sas.h b/drivers/scsi/pm8001/pm8001_sas.h
index 6037d477a183..6c5fd5ee22d3 100644
--- a/drivers/scsi/pm8001/pm8001_sas.h
+++ b/drivers/scsi/pm8001/pm8001_sas.h
@@ -466,6 +466,10 @@ struct pm8001_hba_memspace {
466 u64 membase; 466 u64 membase;
467 u32 memsize; 467 u32 memsize;
468}; 468};
469struct isr_param {
470 struct pm8001_hba_info *drv_inst;
471 u32 irq_id;
472};
469struct pm8001_hba_info { 473struct pm8001_hba_info {
470 char name[PM8001_NAME_LENGTH]; 474 char name[PM8001_NAME_LENGTH];
471 struct list_head list; 475 struct list_head list;
@@ -519,14 +523,13 @@ struct pm8001_hba_info {
519 int number_of_intr;/*will be used in remove()*/ 523 int number_of_intr;/*will be used in remove()*/
520#endif 524#endif
521#ifdef PM8001_USE_TASKLET 525#ifdef PM8001_USE_TASKLET
522 struct tasklet_struct tasklet; 526 struct tasklet_struct tasklet[PM8001_MAX_MSIX_VEC];
523#endif 527#endif
524 u32 logging_level; 528 u32 logging_level;
525 u32 fw_status; 529 u32 fw_status;
526 u32 smp_exp_mode; 530 u32 smp_exp_mode;
527 u32 int_vector;
528 const struct firmware *fw_image; 531 const struct firmware *fw_image;
529 u8 outq[PM8001_MAX_MSIX_VEC]; 532 struct isr_param irq_vector[PM8001_MAX_MSIX_VEC];
530}; 533};
531 534
532struct pm8001_work { 535struct pm8001_work {
diff --git a/drivers/scsi/pm8001/pm80xx_hwi.c b/drivers/scsi/pm8001/pm80xx_hwi.c
index 8987b1706216..c950dc5c9943 100644
--- a/drivers/scsi/pm8001/pm80xx_hwi.c
+++ b/drivers/scsi/pm8001/pm80xx_hwi.c
@@ -2894,6 +2894,7 @@ hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
2894 unsigned long flags; 2894 unsigned long flags;
2895 u8 deviceType = pPayload->sas_identify.dev_type; 2895 u8 deviceType = pPayload->sas_identify.dev_type;
2896 port->port_state = portstate; 2896 port->port_state = portstate;
2897 phy->phy_state = PHY_STATE_LINK_UP_SPCV;
2897 PM8001_MSG_DBG(pm8001_ha, pm8001_printk( 2898 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
2898 "portid:%d; phyid:%d; linkrate:%d; " 2899 "portid:%d; phyid:%d; linkrate:%d; "
2899 "portstate:%x; devicetype:%x\n", 2900 "portstate:%x; devicetype:%x\n",
@@ -2978,6 +2979,7 @@ hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
2978 port_id, phy_id, link_rate, portstate)); 2979 port_id, phy_id, link_rate, portstate));
2979 2980
2980 port->port_state = portstate; 2981 port->port_state = portstate;
2982 phy->phy_state = PHY_STATE_LINK_UP_SPCV;
2981 port->port_attached = 1; 2983 port->port_attached = 1;
2982 pm8001_get_lrate_mode(phy, link_rate); 2984 pm8001_get_lrate_mode(phy, link_rate);
2983 phy->phy_type |= PORT_TYPE_SATA; 2985 phy->phy_type |= PORT_TYPE_SATA;
diff --git a/drivers/scsi/pm8001/pm80xx_hwi.h b/drivers/scsi/pm8001/pm80xx_hwi.h
index c86816bea424..9970a385795d 100644
--- a/drivers/scsi/pm8001/pm80xx_hwi.h
+++ b/drivers/scsi/pm8001/pm80xx_hwi.h
@@ -215,6 +215,8 @@
215#define SAS_DOPNRJT_RTRY_TMO 128 215#define SAS_DOPNRJT_RTRY_TMO 128
216#define SAS_COPNRJT_RTRY_TMO 128 216#define SAS_COPNRJT_RTRY_TMO 128
217 217
218/* for phy state */
219#define PHY_STATE_LINK_UP_SPCV 0x2
218/* 220/*
219 Making ORR bigger than IT NEXUS LOSS which is 2000000us = 2 second. 221 Making ORR bigger than IT NEXUS LOSS which is 2000000us = 2 second.
220 Assuming a bigger value 3 second, 3000000/128 = 23437.5 where 128 222 Assuming a bigger value 3 second, 3000000/128 = 23437.5 where 128
diff --git a/drivers/scsi/pmcraid.c b/drivers/scsi/pmcraid.c
index bd6f743d87a7..be8ce54f99b2 100644
--- a/drivers/scsi/pmcraid.c
+++ b/drivers/scsi/pmcraid.c
@@ -1404,11 +1404,22 @@ enum {
1404}; 1404};
1405#define PMCRAID_AEN_CMD_MAX (__PMCRAID_AEN_CMD_MAX - 1) 1405#define PMCRAID_AEN_CMD_MAX (__PMCRAID_AEN_CMD_MAX - 1)
1406 1406
1407static struct genl_multicast_group pmcraid_mcgrps[] = {
1408 { .name = "events", /* not really used - see ID discussion below */ },
1409};
1410
1407static struct genl_family pmcraid_event_family = { 1411static struct genl_family pmcraid_event_family = {
1408 .id = GENL_ID_GENERATE, 1412 /*
1413 * Due to prior multicast group abuse (the code having assumed that
1414 * the family ID can be used as a multicast group ID) we need to
1415 * statically allocate a family (and thus group) ID.
1416 */
1417 .id = GENL_ID_PMCRAID,
1409 .name = "pmcraid", 1418 .name = "pmcraid",
1410 .version = 1, 1419 .version = 1,
1411 .maxattr = PMCRAID_AEN_ATTR_MAX 1420 .maxattr = PMCRAID_AEN_ATTR_MAX,
1421 .mcgrps = pmcraid_mcgrps,
1422 .n_mcgrps = ARRAY_SIZE(pmcraid_mcgrps),
1412}; 1423};
1413 1424
1414/** 1425/**
@@ -1511,9 +1522,8 @@ static int pmcraid_notify_aen(
1511 return result; 1522 return result;
1512 } 1523 }
1513 1524
1514 result = 1525 result = genlmsg_multicast(&pmcraid_event_family, skb,
1515 genlmsg_multicast(&pmcraid_event_family, skb, 0, 1526 0, 0, GFP_ATOMIC);
1516 pmcraid_event_family.id, GFP_ATOMIC);
1517 1527
1518 /* If there are no listeners, genlmsg_multicast may return non-zero 1528 /* If there are no listeners, genlmsg_multicast may return non-zero
1519 * value. 1529 * value.
@@ -4315,6 +4325,7 @@ static struct scsi_host_template pmcraid_host_template = {
4315 .this_id = -1, 4325 .this_id = -1,
4316 .sg_tablesize = PMCRAID_MAX_IOADLS, 4326 .sg_tablesize = PMCRAID_MAX_IOADLS,
4317 .max_sectors = PMCRAID_IOA_MAX_SECTORS, 4327 .max_sectors = PMCRAID_IOA_MAX_SECTORS,
4328 .no_write_same = 1,
4318 .cmd_per_lun = PMCRAID_MAX_CMD_PER_LUN, 4329 .cmd_per_lun = PMCRAID_MAX_CMD_PER_LUN,
4319 .use_clustering = ENABLE_CLUSTERING, 4330 .use_clustering = ENABLE_CLUSTERING,
4320 .shost_attrs = pmcraid_host_attrs, 4331 .shost_attrs = pmcraid_host_attrs,
diff --git a/drivers/scsi/sd.c b/drivers/scsi/sd.c
index e6c4bff04339..69725f7c32c1 100644
--- a/drivers/scsi/sd.c
+++ b/drivers/scsi/sd.c
@@ -2659,6 +2659,12 @@ static void sd_read_write_same(struct scsi_disk *sdkp, unsigned char *buffer)
2659{ 2659{
2660 struct scsi_device *sdev = sdkp->device; 2660 struct scsi_device *sdev = sdkp->device;
2661 2661
2662 if (sdev->host->no_write_same) {
2663 sdev->no_write_same = 1;
2664
2665 return;
2666 }
2667
2662 if (scsi_report_opcode(sdev, buffer, SD_BUF_SIZE, INQUIRY) < 0) { 2668 if (scsi_report_opcode(sdev, buffer, SD_BUF_SIZE, INQUIRY) < 0) {
2663 /* too large values might cause issues with arcmsr */ 2669 /* too large values might cause issues with arcmsr */
2664 int vpd_buf_len = 64; 2670 int vpd_buf_len = 64;
diff --git a/drivers/scsi/storvsc_drv.c b/drivers/scsi/storvsc_drv.c
index 1a28f5632797..17d740427240 100644
--- a/drivers/scsi/storvsc_drv.c
+++ b/drivers/scsi/storvsc_drv.c
@@ -1697,6 +1697,7 @@ static struct scsi_host_template scsi_driver = {
1697 .use_clustering = DISABLE_CLUSTERING, 1697 .use_clustering = DISABLE_CLUSTERING,
1698 /* Make sure we dont get a sg segment crosses a page boundary */ 1698 /* Make sure we dont get a sg segment crosses a page boundary */
1699 .dma_boundary = PAGE_SIZE-1, 1699 .dma_boundary = PAGE_SIZE-1,
1700 .no_write_same = 1,
1700}; 1701};
1701 1702
1702enum { 1703enum {
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index eb1f1ef5fa2e..9fc66e83c1a7 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -448,6 +448,7 @@ config SPI_MXS
448config SPI_TEGRA114 448config SPI_TEGRA114
449 tristate "NVIDIA Tegra114 SPI Controller" 449 tristate "NVIDIA Tegra114 SPI Controller"
450 depends on (ARCH_TEGRA && TEGRA20_APB_DMA) || COMPILE_TEST 450 depends on (ARCH_TEGRA && TEGRA20_APB_DMA) || COMPILE_TEST
451 depends on RESET_CONTROLLER
451 help 452 help
452 SPI driver for NVIDIA Tegra114 SPI Controller interface. This controller 453 SPI driver for NVIDIA Tegra114 SPI Controller interface. This controller
453 is different than the older SoCs SPI controller and also register interface 454 is different than the older SoCs SPI controller and also register interface
@@ -456,6 +457,7 @@ config SPI_TEGRA114
456config SPI_TEGRA20_SFLASH 457config SPI_TEGRA20_SFLASH
457 tristate "Nvidia Tegra20 Serial flash Controller" 458 tristate "Nvidia Tegra20 Serial flash Controller"
458 depends on ARCH_TEGRA || COMPILE_TEST 459 depends on ARCH_TEGRA || COMPILE_TEST
460 depends on RESET_CONTROLLER
459 help 461 help
460 SPI driver for Nvidia Tegra20 Serial flash Controller interface. 462 SPI driver for Nvidia Tegra20 Serial flash Controller interface.
461 The main usecase of this controller is to use spi flash as boot 463 The main usecase of this controller is to use spi flash as boot
@@ -464,6 +466,7 @@ config SPI_TEGRA20_SFLASH
464config SPI_TEGRA20_SLINK 466config SPI_TEGRA20_SLINK
465 tristate "Nvidia Tegra20/Tegra30 SLINK Controller" 467 tristate "Nvidia Tegra20/Tegra30 SLINK Controller"
466 depends on (ARCH_TEGRA && TEGRA20_APB_DMA) || COMPILE_TEST 468 depends on (ARCH_TEGRA && TEGRA20_APB_DMA) || COMPILE_TEST
469 depends on RESET_CONTROLLER
467 help 470 help
468 SPI driver for Nvidia Tegra20/Tegra30 SLINK Controller interface. 471 SPI driver for Nvidia Tegra20/Tegra30 SLINK Controller interface.
469 472
diff --git a/drivers/spi/spi-bcm2835.c b/drivers/spi/spi-bcm2835.c
index 3ed666fe840a..9025edd7dc45 100644
--- a/drivers/spi/spi-bcm2835.c
+++ b/drivers/spi/spi-bcm2835.c
@@ -377,7 +377,7 @@ out_master_put:
377 377
378static int bcm2835_spi_remove(struct platform_device *pdev) 378static int bcm2835_spi_remove(struct platform_device *pdev)
379{ 379{
380 struct spi_master *master = spi_master_get(platform_get_drvdata(pdev)); 380 struct spi_master *master = platform_get_drvdata(pdev);
381 struct bcm2835_spi *bs = spi_master_get_devdata(master); 381 struct bcm2835_spi *bs = spi_master_get_devdata(master);
382 382
383 free_irq(bs->irq, master); 383 free_irq(bs->irq, master);
diff --git a/drivers/spi/spi-bcm63xx.c b/drivers/spi/spi-bcm63xx.c
index 80d56b214eb5..469ecd876358 100644
--- a/drivers/spi/spi-bcm63xx.c
+++ b/drivers/spi/spi-bcm63xx.c
@@ -435,7 +435,7 @@ out:
435 435
436static int bcm63xx_spi_remove(struct platform_device *pdev) 436static int bcm63xx_spi_remove(struct platform_device *pdev)
437{ 437{
438 struct spi_master *master = spi_master_get(platform_get_drvdata(pdev)); 438 struct spi_master *master = platform_get_drvdata(pdev);
439 struct bcm63xx_spi *bs = spi_master_get_devdata(master); 439 struct bcm63xx_spi *bs = spi_master_get_devdata(master);
440 440
441 /* reset spi block */ 441 /* reset spi block */
diff --git a/drivers/spi/spi-mpc512x-psc.c b/drivers/spi/spi-mpc512x-psc.c
index 9602bbd8d7ea..87676587d783 100644
--- a/drivers/spi/spi-mpc512x-psc.c
+++ b/drivers/spi/spi-mpc512x-psc.c
@@ -557,7 +557,7 @@ free_master:
557 557
558static int mpc512x_psc_spi_do_remove(struct device *dev) 558static int mpc512x_psc_spi_do_remove(struct device *dev)
559{ 559{
560 struct spi_master *master = spi_master_get(dev_get_drvdata(dev)); 560 struct spi_master *master = dev_get_drvdata(dev);
561 struct mpc512x_psc_spi *mps = spi_master_get_devdata(master); 561 struct mpc512x_psc_spi *mps = spi_master_get_devdata(master);
562 562
563 clk_disable_unprepare(mps->clk_mclk); 563 clk_disable_unprepare(mps->clk_mclk);
diff --git a/drivers/spi/spi-mxs.c b/drivers/spi/spi-mxs.c
index 73afb56c08cc..3adebfa22e3d 100644
--- a/drivers/spi/spi-mxs.c
+++ b/drivers/spi/spi-mxs.c
@@ -565,7 +565,7 @@ static int mxs_spi_remove(struct platform_device *pdev)
565 struct mxs_spi *spi; 565 struct mxs_spi *spi;
566 struct mxs_ssp *ssp; 566 struct mxs_ssp *ssp;
567 567
568 master = spi_master_get(platform_get_drvdata(pdev)); 568 master = platform_get_drvdata(pdev);
569 spi = spi_master_get_devdata(master); 569 spi = spi_master_get_devdata(master);
570 ssp = &spi->ssp; 570 ssp = &spi->ssp;
571 571
diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c
index cb0e1f1137ad..7765b1999537 100644
--- a/drivers/spi/spi-pxa2xx.c
+++ b/drivers/spi/spi-pxa2xx.c
@@ -1073,6 +1073,8 @@ pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev)
1073static struct acpi_device_id pxa2xx_spi_acpi_match[] = { 1073static struct acpi_device_id pxa2xx_spi_acpi_match[] = {
1074 { "INT33C0", 0 }, 1074 { "INT33C0", 0 },
1075 { "INT33C1", 0 }, 1075 { "INT33C1", 0 },
1076 { "INT3430", 0 },
1077 { "INT3431", 0 },
1076 { "80860F0E", 0 }, 1078 { "80860F0E", 0 },
1077 { }, 1079 { },
1078}; 1080};
@@ -1291,6 +1293,9 @@ static int pxa2xx_spi_resume(struct device *dev)
1291 /* Enable the SSP clock */ 1293 /* Enable the SSP clock */
1292 clk_prepare_enable(ssp->clk); 1294 clk_prepare_enable(ssp->clk);
1293 1295
1296 /* Restore LPSS private register bits */
1297 lpss_ssp_setup(drv_data);
1298
1294 /* Start the queue running */ 1299 /* Start the queue running */
1295 status = spi_master_resume(drv_data->master); 1300 status = spi_master_resume(drv_data->master);
1296 if (status != 0) { 1301 if (status != 0) {
diff --git a/drivers/spi/spi-rspi.c b/drivers/spi/spi-rspi.c
index 58449ad4ad0d..9e829cee7357 100644
--- a/drivers/spi/spi-rspi.c
+++ b/drivers/spi/spi-rspi.c
@@ -885,14 +885,13 @@ static void rspi_release_dma(struct rspi_data *rspi)
885 885
886static int rspi_remove(struct platform_device *pdev) 886static int rspi_remove(struct platform_device *pdev)
887{ 887{
888 struct rspi_data *rspi = spi_master_get(platform_get_drvdata(pdev)); 888 struct rspi_data *rspi = platform_get_drvdata(pdev);
889 889
890 spi_unregister_master(rspi->master); 890 spi_unregister_master(rspi->master);
891 rspi_release_dma(rspi); 891 rspi_release_dma(rspi);
892 free_irq(platform_get_irq(pdev, 0), rspi); 892 free_irq(platform_get_irq(pdev, 0), rspi);
893 clk_put(rspi->clk); 893 clk_put(rspi->clk);
894 iounmap(rspi->addr); 894 iounmap(rspi->addr);
895 spi_master_put(rspi->master);
896 895
897 return 0; 896 return 0;
898} 897}
diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c
index aaecfb3ebf58..c8604981a058 100644
--- a/drivers/spi/spi-tegra114.c
+++ b/drivers/spi/spi-tegra114.c
@@ -17,7 +17,6 @@
17 */ 17 */
18 18
19#include <linux/clk.h> 19#include <linux/clk.h>
20#include <linux/clk/tegra.h>
21#include <linux/completion.h> 20#include <linux/completion.h>
22#include <linux/delay.h> 21#include <linux/delay.h>
23#include <linux/dmaengine.h> 22#include <linux/dmaengine.h>
@@ -34,6 +33,7 @@
34#include <linux/pm_runtime.h> 33#include <linux/pm_runtime.h>
35#include <linux/of.h> 34#include <linux/of.h>
36#include <linux/of_device.h> 35#include <linux/of_device.h>
36#include <linux/reset.h>
37#include <linux/spi/spi.h> 37#include <linux/spi/spi.h>
38 38
39#define SPI_COMMAND1 0x000 39#define SPI_COMMAND1 0x000
@@ -174,10 +174,10 @@ struct tegra_spi_data {
174 spinlock_t lock; 174 spinlock_t lock;
175 175
176 struct clk *clk; 176 struct clk *clk;
177 struct reset_control *rst;
177 void __iomem *base; 178 void __iomem *base;
178 phys_addr_t phys; 179 phys_addr_t phys;
179 unsigned irq; 180 unsigned irq;
180 int dma_req_sel;
181 u32 spi_max_frequency; 181 u32 spi_max_frequency;
182 u32 cur_speed; 182 u32 cur_speed;
183 183
@@ -600,15 +600,15 @@ static int tegra_spi_init_dma_param(struct tegra_spi_data *tspi,
600 dma_addr_t dma_phys; 600 dma_addr_t dma_phys;
601 int ret; 601 int ret;
602 struct dma_slave_config dma_sconfig; 602 struct dma_slave_config dma_sconfig;
603 dma_cap_mask_t mask;
604 603
605 dma_cap_zero(mask); 604 dma_chan = dma_request_slave_channel_reason(tspi->dev,
606 dma_cap_set(DMA_SLAVE, mask); 605 dma_to_memory ? "rx" : "tx");
607 dma_chan = dma_request_channel(mask, NULL, NULL); 606 if (IS_ERR(dma_chan)) {
608 if (!dma_chan) { 607 ret = PTR_ERR(dma_chan);
609 dev_err(tspi->dev, 608 if (ret != -EPROBE_DEFER)
610 "Dma channel is not available, will try later\n"); 609 dev_err(tspi->dev,
611 return -EPROBE_DEFER; 610 "Dma channel is not available: %d\n", ret);
611 return ret;
612 } 612 }
613 613
614 dma_buf = dma_alloc_coherent(tspi->dev, tspi->dma_buf_size, 614 dma_buf = dma_alloc_coherent(tspi->dev, tspi->dma_buf_size,
@@ -619,7 +619,6 @@ static int tegra_spi_init_dma_param(struct tegra_spi_data *tspi,
619 return -ENOMEM; 619 return -ENOMEM;
620 } 620 }
621 621
622 dma_sconfig.slave_id = tspi->dma_req_sel;
623 if (dma_to_memory) { 622 if (dma_to_memory) {
624 dma_sconfig.src_addr = tspi->phys + SPI_RX_FIFO; 623 dma_sconfig.src_addr = tspi->phys + SPI_RX_FIFO;
625 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 624 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
@@ -918,9 +917,9 @@ static irqreturn_t handle_cpu_based_xfer(struct tegra_spi_data *tspi)
918 tspi->status_reg); 917 tspi->status_reg);
919 dev_err(tspi->dev, "CpuXfer 0x%08x:0x%08x\n", 918 dev_err(tspi->dev, "CpuXfer 0x%08x:0x%08x\n",
920 tspi->command1_reg, tspi->dma_control_reg); 919 tspi->command1_reg, tspi->dma_control_reg);
921 tegra_periph_reset_assert(tspi->clk); 920 reset_control_assert(tspi->rst);
922 udelay(2); 921 udelay(2);
923 tegra_periph_reset_deassert(tspi->clk); 922 reset_control_deassert(tspi->rst);
924 complete(&tspi->xfer_completion); 923 complete(&tspi->xfer_completion);
925 goto exit; 924 goto exit;
926 } 925 }
@@ -990,9 +989,9 @@ static irqreturn_t handle_dma_based_xfer(struct tegra_spi_data *tspi)
990 tspi->status_reg); 989 tspi->status_reg);
991 dev_err(tspi->dev, "DmaXfer 0x%08x:0x%08x\n", 990 dev_err(tspi->dev, "DmaXfer 0x%08x:0x%08x\n",
992 tspi->command1_reg, tspi->dma_control_reg); 991 tspi->command1_reg, tspi->dma_control_reg);
993 tegra_periph_reset_assert(tspi->clk); 992 reset_control_assert(tspi->rst);
994 udelay(2); 993 udelay(2);
995 tegra_periph_reset_deassert(tspi->clk); 994 reset_control_deassert(tspi->rst);
996 complete(&tspi->xfer_completion); 995 complete(&tspi->xfer_completion);
997 spin_unlock_irqrestore(&tspi->lock, flags); 996 spin_unlock_irqrestore(&tspi->lock, flags);
998 return IRQ_HANDLED; 997 return IRQ_HANDLED;
@@ -1054,11 +1053,6 @@ static void tegra_spi_parse_dt(struct platform_device *pdev,
1054 struct tegra_spi_data *tspi) 1053 struct tegra_spi_data *tspi)
1055{ 1054{
1056 struct device_node *np = pdev->dev.of_node; 1055 struct device_node *np = pdev->dev.of_node;
1057 u32 of_dma[2];
1058
1059 if (of_property_read_u32_array(np, "nvidia,dma-request-selector",
1060 of_dma, 2) >= 0)
1061 tspi->dma_req_sel = of_dma[1];
1062 1056
1063 if (of_property_read_u32(np, "spi-max-frequency", 1057 if (of_property_read_u32(np, "spi-max-frequency",
1064 &tspi->spi_max_frequency)) 1058 &tspi->spi_max_frequency))
@@ -1127,25 +1121,25 @@ static int tegra_spi_probe(struct platform_device *pdev)
1127 goto exit_free_irq; 1121 goto exit_free_irq;
1128 } 1122 }
1129 1123
1124 tspi->rst = devm_reset_control_get(&pdev->dev, "spi");
1125 if (IS_ERR(tspi->rst)) {
1126 dev_err(&pdev->dev, "can not get reset\n");
1127 ret = PTR_ERR(tspi->rst);
1128 goto exit_free_irq;
1129 }
1130
1130 tspi->max_buf_size = SPI_FIFO_DEPTH << 2; 1131 tspi->max_buf_size = SPI_FIFO_DEPTH << 2;
1131 tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN; 1132 tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN;
1132 1133
1133 if (tspi->dma_req_sel) { 1134 ret = tegra_spi_init_dma_param(tspi, true);
1134 ret = tegra_spi_init_dma_param(tspi, true); 1135 if (ret < 0)
1135 if (ret < 0) { 1136 goto exit_free_irq;
1136 dev_err(&pdev->dev, "RxDma Init failed, err %d\n", ret); 1137 ret = tegra_spi_init_dma_param(tspi, false);
1137 goto exit_free_irq; 1138 if (ret < 0)
1138 } 1139 goto exit_rx_dma_free;
1139 1140 tspi->max_buf_size = tspi->dma_buf_size;
1140 ret = tegra_spi_init_dma_param(tspi, false); 1141 init_completion(&tspi->tx_dma_complete);
1141 if (ret < 0) { 1142 init_completion(&tspi->rx_dma_complete);
1142 dev_err(&pdev->dev, "TxDma Init failed, err %d\n", ret);
1143 goto exit_rx_dma_free;
1144 }
1145 tspi->max_buf_size = tspi->dma_buf_size;
1146 init_completion(&tspi->tx_dma_complete);
1147 init_completion(&tspi->rx_dma_complete);
1148 }
1149 1143
1150 init_completion(&tspi->xfer_completion); 1144 init_completion(&tspi->xfer_completion);
1151 1145
diff --git a/drivers/spi/spi-tegra20-sflash.c b/drivers/spi/spi-tegra20-sflash.c
index 4dc8e8129459..e6f382b33818 100644
--- a/drivers/spi/spi-tegra20-sflash.c
+++ b/drivers/spi/spi-tegra20-sflash.c
@@ -32,8 +32,8 @@
32#include <linux/pm_runtime.h> 32#include <linux/pm_runtime.h>
33#include <linux/of.h> 33#include <linux/of.h>
34#include <linux/of_device.h> 34#include <linux/of_device.h>
35#include <linux/reset.h>
35#include <linux/spi/spi.h> 36#include <linux/spi/spi.h>
36#include <linux/clk/tegra.h>
37 37
38#define SPI_COMMAND 0x000 38#define SPI_COMMAND 0x000
39#define SPI_GO BIT(30) 39#define SPI_GO BIT(30)
@@ -118,6 +118,7 @@ struct tegra_sflash_data {
118 spinlock_t lock; 118 spinlock_t lock;
119 119
120 struct clk *clk; 120 struct clk *clk;
121 struct reset_control *rst;
121 void __iomem *base; 122 void __iomem *base;
122 unsigned irq; 123 unsigned irq;
123 u32 spi_max_frequency; 124 u32 spi_max_frequency;
@@ -389,9 +390,9 @@ static irqreturn_t handle_cpu_based_xfer(struct tegra_sflash_data *tsd)
389 dev_err(tsd->dev, 390 dev_err(tsd->dev,
390 "CpuXfer 0x%08x:0x%08x\n", tsd->command_reg, 391 "CpuXfer 0x%08x:0x%08x\n", tsd->command_reg,
391 tsd->dma_control_reg); 392 tsd->dma_control_reg);
392 tegra_periph_reset_assert(tsd->clk); 393 reset_control_assert(tsd->rst);
393 udelay(2); 394 udelay(2);
394 tegra_periph_reset_deassert(tsd->clk); 395 reset_control_deassert(tsd->rst);
395 complete(&tsd->xfer_completion); 396 complete(&tsd->xfer_completion);
396 goto exit; 397 goto exit;
397 } 398 }
@@ -505,6 +506,13 @@ static int tegra_sflash_probe(struct platform_device *pdev)
505 goto exit_free_irq; 506 goto exit_free_irq;
506 } 507 }
507 508
509 tsd->rst = devm_reset_control_get(&pdev->dev, "spi");
510 if (IS_ERR(tsd->rst)) {
511 dev_err(&pdev->dev, "can not get reset\n");
512 ret = PTR_ERR(tsd->rst);
513 goto exit_free_irq;
514 }
515
508 init_completion(&tsd->xfer_completion); 516 init_completion(&tsd->xfer_completion);
509 pm_runtime_enable(&pdev->dev); 517 pm_runtime_enable(&pdev->dev);
510 if (!pm_runtime_enabled(&pdev->dev)) { 518 if (!pm_runtime_enabled(&pdev->dev)) {
@@ -520,9 +528,9 @@ static int tegra_sflash_probe(struct platform_device *pdev)
520 } 528 }
521 529
522 /* Reset controller */ 530 /* Reset controller */
523 tegra_periph_reset_assert(tsd->clk); 531 reset_control_assert(tsd->rst);
524 udelay(2); 532 udelay(2);
525 tegra_periph_reset_deassert(tsd->clk); 533 reset_control_deassert(tsd->rst);
526 534
527 tsd->def_command_reg = SPI_M_S | SPI_CS_SW; 535 tsd->def_command_reg = SPI_M_S | SPI_CS_SW;
528 tegra_sflash_writel(tsd, tsd->def_command_reg, SPI_COMMAND); 536 tegra_sflash_writel(tsd, tsd->def_command_reg, SPI_COMMAND);
diff --git a/drivers/spi/spi-tegra20-slink.c b/drivers/spi/spi-tegra20-slink.c
index e66715ba37ed..a728bb82090f 100644
--- a/drivers/spi/spi-tegra20-slink.c
+++ b/drivers/spi/spi-tegra20-slink.c
@@ -33,8 +33,8 @@
33#include <linux/pm_runtime.h> 33#include <linux/pm_runtime.h>
34#include <linux/of.h> 34#include <linux/of.h>
35#include <linux/of_device.h> 35#include <linux/of_device.h>
36#include <linux/reset.h>
36#include <linux/spi/spi.h> 37#include <linux/spi/spi.h>
37#include <linux/clk/tegra.h>
38 38
39#define SLINK_COMMAND 0x000 39#define SLINK_COMMAND 0x000
40#define SLINK_BIT_LENGTH(x) (((x) & 0x1f) << 0) 40#define SLINK_BIT_LENGTH(x) (((x) & 0x1f) << 0)
@@ -167,10 +167,10 @@ struct tegra_slink_data {
167 spinlock_t lock; 167 spinlock_t lock;
168 168
169 struct clk *clk; 169 struct clk *clk;
170 struct reset_control *rst;
170 void __iomem *base; 171 void __iomem *base;
171 phys_addr_t phys; 172 phys_addr_t phys;
172 unsigned irq; 173 unsigned irq;
173 int dma_req_sel;
174 u32 spi_max_frequency; 174 u32 spi_max_frequency;
175 u32 cur_speed; 175 u32 cur_speed;
176 176
@@ -629,15 +629,15 @@ static int tegra_slink_init_dma_param(struct tegra_slink_data *tspi,
629 dma_addr_t dma_phys; 629 dma_addr_t dma_phys;
630 int ret; 630 int ret;
631 struct dma_slave_config dma_sconfig; 631 struct dma_slave_config dma_sconfig;
632 dma_cap_mask_t mask;
633 632
634 dma_cap_zero(mask); 633 dma_chan = dma_request_slave_channel_reason(tspi->dev,
635 dma_cap_set(DMA_SLAVE, mask); 634 dma_to_memory ? "rx" : "tx");
636 dma_chan = dma_request_channel(mask, NULL, NULL); 635 if (IS_ERR(dma_chan)) {
637 if (!dma_chan) { 636 ret = PTR_ERR(dma_chan);
638 dev_err(tspi->dev, 637 if (ret != -EPROBE_DEFER)
639 "Dma channel is not available, will try later\n"); 638 dev_err(tspi->dev,
640 return -EPROBE_DEFER; 639 "Dma channel is not available: %d\n", ret);
640 return ret;
641 } 641 }
642 642
643 dma_buf = dma_alloc_coherent(tspi->dev, tspi->dma_buf_size, 643 dma_buf = dma_alloc_coherent(tspi->dev, tspi->dma_buf_size,
@@ -648,7 +648,6 @@ static int tegra_slink_init_dma_param(struct tegra_slink_data *tspi,
648 return -ENOMEM; 648 return -ENOMEM;
649 } 649 }
650 650
651 dma_sconfig.slave_id = tspi->dma_req_sel;
652 if (dma_to_memory) { 651 if (dma_to_memory) {
653 dma_sconfig.src_addr = tspi->phys + SLINK_RX_FIFO; 652 dma_sconfig.src_addr = tspi->phys + SLINK_RX_FIFO;
654 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 653 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
@@ -884,9 +883,9 @@ static irqreturn_t handle_cpu_based_xfer(struct tegra_slink_data *tspi)
884 dev_err(tspi->dev, 883 dev_err(tspi->dev,
885 "CpuXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg, 884 "CpuXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg,
886 tspi->command2_reg, tspi->dma_control_reg); 885 tspi->command2_reg, tspi->dma_control_reg);
887 tegra_periph_reset_assert(tspi->clk); 886 reset_control_assert(tspi->rst);
888 udelay(2); 887 udelay(2);
889 tegra_periph_reset_deassert(tspi->clk); 888 reset_control_deassert(tspi->rst);
890 complete(&tspi->xfer_completion); 889 complete(&tspi->xfer_completion);
891 goto exit; 890 goto exit;
892 } 891 }
@@ -957,9 +956,9 @@ static irqreturn_t handle_dma_based_xfer(struct tegra_slink_data *tspi)
957 dev_err(tspi->dev, 956 dev_err(tspi->dev,
958 "DmaXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg, 957 "DmaXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg,
959 tspi->command2_reg, tspi->dma_control_reg); 958 tspi->command2_reg, tspi->dma_control_reg);
960 tegra_periph_reset_assert(tspi->clk); 959 reset_control_assert(tspi->rst);
961 udelay(2); 960 udelay(2);
962 tegra_periph_reset_deassert(tspi->clk); 961 reset_control_assert(tspi->rst);
963 complete(&tspi->xfer_completion); 962 complete(&tspi->xfer_completion);
964 spin_unlock_irqrestore(&tspi->lock, flags); 963 spin_unlock_irqrestore(&tspi->lock, flags);
965 return IRQ_HANDLED; 964 return IRQ_HANDLED;
@@ -1020,11 +1019,6 @@ static irqreturn_t tegra_slink_isr(int irq, void *context_data)
1020static void tegra_slink_parse_dt(struct tegra_slink_data *tspi) 1019static void tegra_slink_parse_dt(struct tegra_slink_data *tspi)
1021{ 1020{
1022 struct device_node *np = tspi->dev->of_node; 1021 struct device_node *np = tspi->dev->of_node;
1023 u32 of_dma[2];
1024
1025 if (of_property_read_u32_array(np, "nvidia,dma-request-selector",
1026 of_dma, 2) >= 0)
1027 tspi->dma_req_sel = of_dma[1];
1028 1022
1029 if (of_property_read_u32(np, "spi-max-frequency", 1023 if (of_property_read_u32(np, "spi-max-frequency",
1030 &tspi->spi_max_frequency)) 1024 &tspi->spi_max_frequency))
@@ -1118,25 +1112,25 @@ static int tegra_slink_probe(struct platform_device *pdev)
1118 goto exit_free_irq; 1112 goto exit_free_irq;
1119 } 1113 }
1120 1114
1115 tspi->rst = devm_reset_control_get(&pdev->dev, "spi");
1116 if (IS_ERR(tspi->rst)) {
1117 dev_err(&pdev->dev, "can not get reset\n");
1118 ret = PTR_ERR(tspi->rst);
1119 goto exit_free_irq;
1120 }
1121
1121 tspi->max_buf_size = SLINK_FIFO_DEPTH << 2; 1122 tspi->max_buf_size = SLINK_FIFO_DEPTH << 2;
1122 tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN; 1123 tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN;
1123 1124
1124 if (tspi->dma_req_sel) { 1125 ret = tegra_slink_init_dma_param(tspi, true);
1125 ret = tegra_slink_init_dma_param(tspi, true); 1126 if (ret < 0)
1126 if (ret < 0) { 1127 goto exit_free_irq;
1127 dev_err(&pdev->dev, "RxDma Init failed, err %d\n", ret); 1128 ret = tegra_slink_init_dma_param(tspi, false);
1128 goto exit_free_irq; 1129 if (ret < 0)
1129 } 1130 goto exit_rx_dma_free;
1130 1131 tspi->max_buf_size = tspi->dma_buf_size;
1131 ret = tegra_slink_init_dma_param(tspi, false); 1132 init_completion(&tspi->tx_dma_complete);
1132 if (ret < 0) { 1133 init_completion(&tspi->rx_dma_complete);
1133 dev_err(&pdev->dev, "TxDma Init failed, err %d\n", ret);
1134 goto exit_rx_dma_free;
1135 }
1136 tspi->max_buf_size = tspi->dma_buf_size;
1137 init_completion(&tspi->tx_dma_complete);
1138 init_completion(&tspi->rx_dma_complete);
1139 }
1140 1134
1141 init_completion(&tspi->xfer_completion); 1135 init_completion(&tspi->xfer_completion);
1142 1136
diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
index 0b71270fbf67..4396bd448540 100644
--- a/drivers/spi/spi-ti-qspi.c
+++ b/drivers/spi/spi-ti-qspi.c
@@ -161,7 +161,7 @@ static int ti_qspi_setup(struct spi_device *spi)
161 qspi->spi_max_frequency, clk_div); 161 qspi->spi_max_frequency, clk_div);
162 162
163 ret = pm_runtime_get_sync(qspi->dev); 163 ret = pm_runtime_get_sync(qspi->dev);
164 if (ret) { 164 if (ret < 0) {
165 dev_err(qspi->dev, "pm_runtime_get_sync() failed\n"); 165 dev_err(qspi->dev, "pm_runtime_get_sync() failed\n");
166 return ret; 166 return ret;
167 } 167 }
@@ -459,11 +459,10 @@ static int ti_qspi_probe(struct platform_device *pdev)
459 if (!of_property_read_u32(np, "num-cs", &num_cs)) 459 if (!of_property_read_u32(np, "num-cs", &num_cs))
460 master->num_chipselect = num_cs; 460 master->num_chipselect = num_cs;
461 461
462 platform_set_drvdata(pdev, master);
463
464 qspi = spi_master_get_devdata(master); 462 qspi = spi_master_get_devdata(master);
465 qspi->master = master; 463 qspi->master = master;
466 qspi->dev = &pdev->dev; 464 qspi->dev = &pdev->dev;
465 platform_set_drvdata(pdev, qspi);
467 466
468 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 467 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
469 468
@@ -517,10 +516,26 @@ free_master:
517 516
518static int ti_qspi_remove(struct platform_device *pdev) 517static int ti_qspi_remove(struct platform_device *pdev)
519{ 518{
520 struct ti_qspi *qspi = platform_get_drvdata(pdev); 519 struct spi_master *master;
520 struct ti_qspi *qspi;
521 int ret;
522
523 master = platform_get_drvdata(pdev);
524 qspi = spi_master_get_devdata(master);
525
526 ret = pm_runtime_get_sync(qspi->dev);
527 if (ret < 0) {
528 dev_err(qspi->dev, "pm_runtime_get_sync() failed\n");
529 return ret;
530 }
521 531
522 ti_qspi_write(qspi, QSPI_WC_INT_DISABLE, QSPI_INTR_ENABLE_CLEAR_REG); 532 ti_qspi_write(qspi, QSPI_WC_INT_DISABLE, QSPI_INTR_ENABLE_CLEAR_REG);
523 533
534 pm_runtime_put(qspi->dev);
535 pm_runtime_disable(&pdev->dev);
536
537 spi_unregister_master(master);
538
524 return 0; 539 return 0;
525} 540}
526 541
diff --git a/drivers/spi/spi-txx9.c b/drivers/spi/spi-txx9.c
index 637cce2b8bdd..18c9bb2b5f39 100644
--- a/drivers/spi/spi-txx9.c
+++ b/drivers/spi/spi-txx9.c
@@ -425,7 +425,7 @@ exit:
425 425
426static int txx9spi_remove(struct platform_device *dev) 426static int txx9spi_remove(struct platform_device *dev)
427{ 427{
428 struct spi_master *master = spi_master_get(platform_get_drvdata(dev)); 428 struct spi_master *master = platform_get_drvdata(dev);
429 struct txx9spi *c = spi_master_get_devdata(master); 429 struct txx9spi *c = spi_master_get_devdata(master);
430 430
431 destroy_workqueue(c->workqueue); 431 destroy_workqueue(c->workqueue);
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index 18cc625d887f..349ebba4b199 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -1415,7 +1415,7 @@ int devm_spi_register_master(struct device *dev, struct spi_master *master)
1415 return -ENOMEM; 1415 return -ENOMEM;
1416 1416
1417 ret = spi_register_master(master); 1417 ret = spi_register_master(master);
1418 if (ret != 0) { 1418 if (!ret) {
1419 *ptr = master; 1419 *ptr = master;
1420 devres_add(dev, ptr); 1420 devres_add(dev, ptr);
1421 } else { 1421 } else {
diff --git a/drivers/staging/btmtk_usb/btmtk_usb.c b/drivers/staging/btmtk_usb/btmtk_usb.c
index 7a9bf3b57810..9a5ebd6cc512 100644
--- a/drivers/staging/btmtk_usb/btmtk_usb.c
+++ b/drivers/staging/btmtk_usb/btmtk_usb.c
@@ -1284,9 +1284,8 @@ done:
1284 kfree_skb(skb); 1284 kfree_skb(skb);
1285} 1285}
1286 1286
1287static int btmtk_usb_send_frame(struct sk_buff *skb) 1287static int btmtk_usb_send_frame(struct hci_dev *hdev, struct sk_buff *skb)
1288{ 1288{
1289 struct hci_dev *hdev = (struct hci_dev *)skb->dev;
1290 struct btmtk_usb_data *data = hci_get_drvdata(hdev); 1289 struct btmtk_usb_data *data = hci_get_drvdata(hdev);
1291 struct usb_ctrlrequest *dr; 1290 struct usb_ctrlrequest *dr;
1292 struct urb *urb; 1291 struct urb *urb;
diff --git a/drivers/staging/comedi/drivers/pcl730.c b/drivers/staging/comedi/drivers/pcl730.c
index d041b714db29..2baaf1db6fbf 100644
--- a/drivers/staging/comedi/drivers/pcl730.c
+++ b/drivers/staging/comedi/drivers/pcl730.c
@@ -173,11 +173,11 @@ static int pcl730_do_insn_bits(struct comedi_device *dev,
173 if (mask) { 173 if (mask) {
174 if (mask & 0x00ff) 174 if (mask & 0x00ff)
175 outb(s->state & 0xff, dev->iobase + reg); 175 outb(s->state & 0xff, dev->iobase + reg);
176 if ((mask & 0xff00) & (s->n_chan > 8)) 176 if ((mask & 0xff00) && (s->n_chan > 8))
177 outb((s->state >> 8) & 0xff, dev->iobase + reg + 1); 177 outb((s->state >> 8) & 0xff, dev->iobase + reg + 1);
178 if ((mask & 0xff0000) & (s->n_chan > 16)) 178 if ((mask & 0xff0000) && (s->n_chan > 16))
179 outb((s->state >> 16) & 0xff, dev->iobase + reg + 2); 179 outb((s->state >> 16) & 0xff, dev->iobase + reg + 2);
180 if ((mask & 0xff000000) & (s->n_chan > 24)) 180 if ((mask & 0xff000000) && (s->n_chan > 24))
181 outb((s->state >> 24) & 0xff, dev->iobase + reg + 3); 181 outb((s->state >> 24) & 0xff, dev->iobase + reg + 3);
182 } 182 }
183 183
diff --git a/drivers/staging/comedi/drivers/s626.c b/drivers/staging/comedi/drivers/s626.c
index 6815cfe2664e..b486099b543d 100644
--- a/drivers/staging/comedi/drivers/s626.c
+++ b/drivers/staging/comedi/drivers/s626.c
@@ -494,7 +494,7 @@ static void s626_send_dac(struct comedi_device *dev, uint32_t val)
494 * Private helper function: Write setpoint to an application DAC channel. 494 * Private helper function: Write setpoint to an application DAC channel.
495 */ 495 */
496static void s626_set_dac(struct comedi_device *dev, uint16_t chan, 496static void s626_set_dac(struct comedi_device *dev, uint16_t chan,
497 unsigned short dacdata) 497 int16_t dacdata)
498{ 498{
499 struct s626_private *devpriv = dev->private; 499 struct s626_private *devpriv = dev->private;
500 uint16_t signmask; 500 uint16_t signmask;
diff --git a/drivers/staging/comedi/drivers/vmk80xx.c b/drivers/staging/comedi/drivers/vmk80xx.c
index 933b01a0f03d..0adf3cffddb0 100644
--- a/drivers/staging/comedi/drivers/vmk80xx.c
+++ b/drivers/staging/comedi/drivers/vmk80xx.c
@@ -465,7 +465,7 @@ static int vmk80xx_do_insn_bits(struct comedi_device *dev,
465 unsigned char *rx_buf = devpriv->usb_rx_buf; 465 unsigned char *rx_buf = devpriv->usb_rx_buf;
466 unsigned char *tx_buf = devpriv->usb_tx_buf; 466 unsigned char *tx_buf = devpriv->usb_tx_buf;
467 int reg, cmd; 467 int reg, cmd;
468 int ret; 468 int ret = 0;
469 469
470 if (devpriv->model == VMK8061_MODEL) { 470 if (devpriv->model == VMK8061_MODEL) {
471 reg = VMK8061_DO_REG; 471 reg = VMK8061_DO_REG;
diff --git a/drivers/staging/ft1000/ft1000-usb/ft1000_download.c b/drivers/staging/ft1000/ft1000-usb/ft1000_download.c
index 68ded17c0f5c..12f333fa59b5 100644
--- a/drivers/staging/ft1000/ft1000-usb/ft1000_download.c
+++ b/drivers/staging/ft1000/ft1000-usb/ft1000_download.c
@@ -578,7 +578,7 @@ static int request_code_segment(struct ft1000_usb *ft1000dev, u16 **s_file,
578 u8 **c_file, const u8 *endpoint, bool boot_case) 578 u8 **c_file, const u8 *endpoint, bool boot_case)
579{ 579{
580 long word_length; 580 long word_length;
581 int status; 581 int status = 0;
582 582
583 /*DEBUG("FT1000:REQUEST_CODE_SEGMENT\n");i*/ 583 /*DEBUG("FT1000:REQUEST_CODE_SEGMENT\n");i*/
584 word_length = get_request_value(ft1000dev); 584 word_length = get_request_value(ft1000dev);
@@ -1074,4 +1074,3 @@ int scram_dnldr(struct ft1000_usb *ft1000dev, void *pFileStart,
1074 1074
1075 return status; 1075 return status;
1076} 1076}
1077
diff --git a/drivers/staging/iio/magnetometer/Kconfig b/drivers/staging/iio/magnetometer/Kconfig
index a3ea69e9d800..34634da1f9f7 100644
--- a/drivers/staging/iio/magnetometer/Kconfig
+++ b/drivers/staging/iio/magnetometer/Kconfig
@@ -6,6 +6,8 @@ menu "Magnetometer sensors"
6config SENSORS_HMC5843 6config SENSORS_HMC5843
7 tristate "Honeywell HMC5843/5883/5883L 3-Axis Magnetometer" 7 tristate "Honeywell HMC5843/5883/5883L 3-Axis Magnetometer"
8 depends on I2C 8 depends on I2C
9 select IIO_BUFFER
10 select IIO_TRIGGERED_BUFFER
9 help 11 help
10 Say Y here to add support for the Honeywell HMC5843, HMC5883 and 12 Say Y here to add support for the Honeywell HMC5843, HMC5883 and
11 HMC5883L 3-Axis Magnetometer (digital compass). 13 HMC5883L 3-Axis Magnetometer (digital compass).
diff --git a/drivers/staging/imx-drm/Makefile b/drivers/staging/imx-drm/Makefile
index 2c3a9e178fb5..8742432d7b01 100644
--- a/drivers/staging/imx-drm/Makefile
+++ b/drivers/staging/imx-drm/Makefile
@@ -8,4 +8,6 @@ obj-$(CONFIG_DRM_IMX_TVE) += imx-tve.o
8obj-$(CONFIG_DRM_IMX_LDB) += imx-ldb.o 8obj-$(CONFIG_DRM_IMX_LDB) += imx-ldb.o
9obj-$(CONFIG_DRM_IMX_FB_HELPER) += imx-fbdev.o 9obj-$(CONFIG_DRM_IMX_FB_HELPER) += imx-fbdev.o
10obj-$(CONFIG_DRM_IMX_IPUV3_CORE) += ipu-v3/ 10obj-$(CONFIG_DRM_IMX_IPUV3_CORE) += ipu-v3/
11obj-$(CONFIG_DRM_IMX_IPUV3) += ipuv3-crtc.o ipuv3-plane.o 11
12imx-ipuv3-crtc-objs := ipuv3-crtc.o ipuv3-plane.o
13obj-$(CONFIG_DRM_IMX_IPUV3) += imx-ipuv3-crtc.o
diff --git a/drivers/staging/imx-drm/imx-drm-core.c b/drivers/staging/imx-drm/imx-drm-core.c
index 51aa9772f959..6bd015ac9d68 100644
--- a/drivers/staging/imx-drm/imx-drm-core.c
+++ b/drivers/staging/imx-drm/imx-drm-core.c
@@ -72,6 +72,7 @@ int imx_drm_crtc_id(struct imx_drm_crtc *crtc)
72{ 72{
73 return crtc->pipe; 73 return crtc->pipe;
74} 74}
75EXPORT_SYMBOL_GPL(imx_drm_crtc_id);
75 76
76static void imx_drm_driver_lastclose(struct drm_device *drm) 77static void imx_drm_driver_lastclose(struct drm_device *drm)
77{ 78{
diff --git a/drivers/staging/lustre/lustre/ptlrpc/pinger.c b/drivers/staging/lustre/lustre/ptlrpc/pinger.c
index 5dec771d70ee..4d340f4a2198 100644
--- a/drivers/staging/lustre/lustre/ptlrpc/pinger.c
+++ b/drivers/staging/lustre/lustre/ptlrpc/pinger.c
@@ -409,8 +409,8 @@ int ptlrpc_stop_pinger(void)
409 struct l_wait_info lwi = { 0 }; 409 struct l_wait_info lwi = { 0 };
410 int rc = 0; 410 int rc = 0;
411 411
412 if (!thread_is_init(&pinger_thread) && 412 if (thread_is_init(&pinger_thread) ||
413 !thread_is_stopped(&pinger_thread)) 413 thread_is_stopped(&pinger_thread))
414 return -EALREADY; 414 return -EALREADY;
415 415
416 ptlrpc_pinger_remove_timeouts(); 416 ptlrpc_pinger_remove_timeouts();
diff --git a/drivers/staging/media/go7007/go7007-usb.c b/drivers/staging/media/go7007/go7007-usb.c
index 58684da45e6c..b658c2316df3 100644
--- a/drivers/staging/media/go7007/go7007-usb.c
+++ b/drivers/staging/media/go7007/go7007-usb.c
@@ -15,6 +15,8 @@
15 * Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 15 * Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
16 */ 16 */
17 17
18#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
18#include <linux/module.h> 20#include <linux/module.h>
19#include <linux/kernel.h> 21#include <linux/kernel.h>
20#include <linux/init.h> 22#include <linux/init.h>
@@ -661,7 +663,7 @@ static int go7007_usb_interface_reset(struct go7007 *go)
661 663
662 if (usb->board->flags & GO7007_USB_EZUSB) { 664 if (usb->board->flags & GO7007_USB_EZUSB) {
663 /* Reset buffer in EZ-USB */ 665 /* Reset buffer in EZ-USB */
664 dev_dbg(go->dev, "resetting EZ-USB buffers\n"); 666 pr_debug("resetting EZ-USB buffers\n");
665 if (go7007_usb_vendor_request(go, 0x10, 0, 0, NULL, 0, 0) < 0 || 667 if (go7007_usb_vendor_request(go, 0x10, 0, 0, NULL, 0, 0) < 0 ||
666 go7007_usb_vendor_request(go, 0x10, 0, 0, NULL, 0, 0) < 0) 668 go7007_usb_vendor_request(go, 0x10, 0, 0, NULL, 0, 0) < 0)
667 return -1; 669 return -1;
@@ -689,7 +691,7 @@ static int go7007_usb_ezusb_write_interrupt(struct go7007 *go,
689 u16 status_reg = 0; 691 u16 status_reg = 0;
690 int timeout = 500; 692 int timeout = 500;
691 693
692 dev_dbg(go->dev, "WriteInterrupt: %04x %04x\n", addr, data); 694 pr_debug("WriteInterrupt: %04x %04x\n", addr, data);
693 695
694 for (i = 0; i < 100; ++i) { 696 for (i = 0; i < 100; ++i) {
695 r = usb_control_msg(usb->usbdev, 697 r = usb_control_msg(usb->usbdev,
@@ -734,7 +736,7 @@ static int go7007_usb_onboard_write_interrupt(struct go7007 *go,
734 int r; 736 int r;
735 int timeout = 500; 737 int timeout = 500;
736 738
737 dev_dbg(go->dev, "WriteInterrupt: %04x %04x\n", addr, data); 739 pr_debug("WriteInterrupt: %04x %04x\n", addr, data);
738 740
739 go->usb_buf[0] = data & 0xff; 741 go->usb_buf[0] = data & 0xff;
740 go->usb_buf[1] = data >> 8; 742 go->usb_buf[1] = data >> 8;
@@ -771,7 +773,7 @@ static void go7007_usb_readinterrupt_complete(struct urb *urb)
771 go->interrupt_available = 1; 773 go->interrupt_available = 1;
772 go->interrupt_data = __le16_to_cpu(regs[0]); 774 go->interrupt_data = __le16_to_cpu(regs[0]);
773 go->interrupt_value = __le16_to_cpu(regs[1]); 775 go->interrupt_value = __le16_to_cpu(regs[1]);
774 dev_dbg(go->dev, "ReadInterrupt: %04x %04x\n", 776 pr_debug("ReadInterrupt: %04x %04x\n",
775 go->interrupt_value, go->interrupt_data); 777 go->interrupt_value, go->interrupt_data);
776 } 778 }
777 779
@@ -891,7 +893,7 @@ static int go7007_usb_send_firmware(struct go7007 *go, u8 *data, int len)
891 int transferred, pipe; 893 int transferred, pipe;
892 int timeout = 500; 894 int timeout = 500;
893 895
894 dev_dbg(go->dev, "DownloadBuffer sending %d bytes\n", len); 896 pr_debug("DownloadBuffer sending %d bytes\n", len);
895 897
896 if (usb->board->flags & GO7007_USB_EZUSB) 898 if (usb->board->flags & GO7007_USB_EZUSB)
897 pipe = usb_sndbulkpipe(usb->usbdev, 2); 899 pipe = usb_sndbulkpipe(usb->usbdev, 2);
@@ -977,7 +979,7 @@ static int go7007_usb_i2c_master_xfer(struct i2c_adapter *adapter,
977 !(msgs[i].flags & I2C_M_RD) && 979 !(msgs[i].flags & I2C_M_RD) &&
978 (msgs[i + 1].flags & I2C_M_RD)) { 980 (msgs[i + 1].flags & I2C_M_RD)) {
979#ifdef GO7007_I2C_DEBUG 981#ifdef GO7007_I2C_DEBUG
980 dev_dbg(go->dev, "i2c write/read %d/%d bytes on %02x\n", 982 pr_debug("i2c write/read %d/%d bytes on %02x\n",
981 msgs[i].len, msgs[i + 1].len, msgs[i].addr); 983 msgs[i].len, msgs[i + 1].len, msgs[i].addr);
982#endif 984#endif
983 buf[0] = 0x01; 985 buf[0] = 0x01;
@@ -988,7 +990,7 @@ static int go7007_usb_i2c_master_xfer(struct i2c_adapter *adapter,
988 buf[buf_len++] = msgs[++i].len; 990 buf[buf_len++] = msgs[++i].len;
989 } else if (msgs[i].flags & I2C_M_RD) { 991 } else if (msgs[i].flags & I2C_M_RD) {
990#ifdef GO7007_I2C_DEBUG 992#ifdef GO7007_I2C_DEBUG
991 dev_dbg(go->dev, "i2c read %d bytes on %02x\n", 993 pr_debug("i2c read %d bytes on %02x\n",
992 msgs[i].len, msgs[i].addr); 994 msgs[i].len, msgs[i].addr);
993#endif 995#endif
994 buf[0] = 0x01; 996 buf[0] = 0x01;
@@ -998,7 +1000,7 @@ static int go7007_usb_i2c_master_xfer(struct i2c_adapter *adapter,
998 buf_len = 4; 1000 buf_len = 4;
999 } else { 1001 } else {
1000#ifdef GO7007_I2C_DEBUG 1002#ifdef GO7007_I2C_DEBUG
1001 dev_dbg(go->dev, "i2c write %d bytes on %02x\n", 1003 pr_debug("i2c write %d bytes on %02x\n",
1002 msgs[i].len, msgs[i].addr); 1004 msgs[i].len, msgs[i].addr);
1003#endif 1005#endif
1004 buf[0] = 0x00; 1006 buf[0] = 0x00;
@@ -1057,7 +1059,7 @@ static int go7007_usb_probe(struct usb_interface *intf,
1057 char *name; 1059 char *name;
1058 int video_pipe, i, v_urb_len; 1060 int video_pipe, i, v_urb_len;
1059 1061
1060 dev_dbg(go->dev, "probing new GO7007 USB board\n"); 1062 pr_debug("probing new GO7007 USB board\n");
1061 1063
1062 switch (id->driver_info) { 1064 switch (id->driver_info) {
1063 case GO7007_BOARDID_MATRIX_II: 1065 case GO7007_BOARDID_MATRIX_II:
@@ -1097,13 +1099,13 @@ static int go7007_usb_probe(struct usb_interface *intf,
1097 board = &board_px_tv402u; 1099 board = &board_px_tv402u;
1098 break; 1100 break;
1099 case GO7007_BOARDID_LIFEVIEW_LR192: 1101 case GO7007_BOARDID_LIFEVIEW_LR192:
1100 dev_err(go->dev, "The Lifeview TV Walker Ultra is not supported. Sorry!\n"); 1102 dev_err(&intf->dev, "The Lifeview TV Walker Ultra is not supported. Sorry!\n");
1101 return -ENODEV; 1103 return -ENODEV;
1102 name = "Lifeview TV Walker Ultra"; 1104 name = "Lifeview TV Walker Ultra";
1103 board = &board_lifeview_lr192; 1105 board = &board_lifeview_lr192;
1104 break; 1106 break;
1105 case GO7007_BOARDID_SENSORAY_2250: 1107 case GO7007_BOARDID_SENSORAY_2250:
1106 dev_info(go->dev, "Sensoray 2250 found\n"); 1108 dev_info(&intf->dev, "Sensoray 2250 found\n");
1107 name = "Sensoray 2250/2251"; 1109 name = "Sensoray 2250/2251";
1108 board = &board_sensoray_2250; 1110 board = &board_sensoray_2250;
1109 break; 1111 break;
@@ -1112,7 +1114,7 @@ static int go7007_usb_probe(struct usb_interface *intf,
1112 board = &board_ads_usbav_709; 1114 board = &board_ads_usbav_709;
1113 break; 1115 break;
1114 default: 1116 default:
1115 dev_err(go->dev, "unknown board ID %d!\n", 1117 dev_err(&intf->dev, "unknown board ID %d!\n",
1116 (unsigned int)id->driver_info); 1118 (unsigned int)id->driver_info);
1117 return -ENODEV; 1119 return -ENODEV;
1118 } 1120 }
@@ -1247,7 +1249,7 @@ static int go7007_usb_probe(struct usb_interface *intf,
1247 sizeof(go->name)); 1249 sizeof(go->name));
1248 break; 1250 break;
1249 default: 1251 default:
1250 dev_dbg(go->dev, "unable to detect tuner type!\n"); 1252 pr_debug("unable to detect tuner type!\n");
1251 break; 1253 break;
1252 } 1254 }
1253 /* Configure tuner mode selection inputs connected 1255 /* Configure tuner mode selection inputs connected
diff --git a/drivers/staging/nvec/nvec.c b/drivers/staging/nvec/nvec.c
index 3066ee2e753b..986870593b0c 100644
--- a/drivers/staging/nvec/nvec.c
+++ b/drivers/staging/nvec/nvec.c
@@ -36,7 +36,6 @@
36#include <linux/slab.h> 36#include <linux/slab.h>
37#include <linux/spinlock.h> 37#include <linux/spinlock.h>
38#include <linux/workqueue.h> 38#include <linux/workqueue.h>
39#include <linux/clk/tegra.h>
40 39
41#include "nvec.h" 40#include "nvec.h"
42 41
@@ -681,7 +680,8 @@ static irqreturn_t nvec_interrupt(int irq, void *dev)
681 dev_err(nvec->dev, 680 dev_err(nvec->dev,
682 "RX buffer overflow on %p: " 681 "RX buffer overflow on %p: "
683 "Trying to write byte %u of %u\n", 682 "Trying to write byte %u of %u\n",
684 nvec->rx, nvec->rx->pos, NVEC_MSG_SIZE); 683 nvec->rx, nvec->rx ? nvec->rx->pos : 0,
684 NVEC_MSG_SIZE);
685 break; 685 break;
686 default: 686 default:
687 nvec->state = 0; 687 nvec->state = 0;
@@ -733,9 +733,9 @@ static void tegra_init_i2c_slave(struct nvec_chip *nvec)
733 733
734 clk_prepare_enable(nvec->i2c_clk); 734 clk_prepare_enable(nvec->i2c_clk);
735 735
736 tegra_periph_reset_assert(nvec->i2c_clk); 736 reset_control_assert(nvec->rst);
737 udelay(2); 737 udelay(2);
738 tegra_periph_reset_deassert(nvec->i2c_clk); 738 reset_control_deassert(nvec->rst);
739 739
740 val = I2C_CNFG_NEW_MASTER_SFM | I2C_CNFG_PACKET_MODE_EN | 740 val = I2C_CNFG_NEW_MASTER_SFM | I2C_CNFG_PACKET_MODE_EN |
741 (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT); 741 (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT);
@@ -836,6 +836,12 @@ static int tegra_nvec_probe(struct platform_device *pdev)
836 return -ENODEV; 836 return -ENODEV;
837 } 837 }
838 838
839 nvec->rst = devm_reset_control_get(&pdev->dev, "i2c");
840 if (IS_ERR(nvec->rst)) {
841 dev_err(nvec->dev, "failed to get controller reset\n");
842 return PTR_ERR(nvec->rst);
843 }
844
839 nvec->base = base; 845 nvec->base = base;
840 nvec->irq = res->start; 846 nvec->irq = res->start;
841 nvec->i2c_clk = i2c_clk; 847 nvec->i2c_clk = i2c_clk;
diff --git a/drivers/staging/nvec/nvec.h b/drivers/staging/nvec/nvec.h
index e880518935fb..e271375053fa 100644
--- a/drivers/staging/nvec/nvec.h
+++ b/drivers/staging/nvec/nvec.h
@@ -23,6 +23,7 @@
23#include <linux/list.h> 23#include <linux/list.h>
24#include <linux/mutex.h> 24#include <linux/mutex.h>
25#include <linux/notifier.h> 25#include <linux/notifier.h>
26#include <linux/reset.h>
26#include <linux/spinlock.h> 27#include <linux/spinlock.h>
27#include <linux/workqueue.h> 28#include <linux/workqueue.h>
28 29
@@ -109,7 +110,8 @@ struct nvec_msg {
109 * @irq: The IRQ of the I2C device 110 * @irq: The IRQ of the I2C device
110 * @i2c_addr: The address of the I2C slave 111 * @i2c_addr: The address of the I2C slave
111 * @base: The base of the memory mapped region of the I2C device 112 * @base: The base of the memory mapped region of the I2C device
112 * @clk: The clock of the I2C device 113 * @i2c_clk: The clock of the I2C device
114 * @rst: The reset of the I2C device
113 * @notifier_list: Notifiers to be called on received messages, see 115 * @notifier_list: Notifiers to be called on received messages, see
114 * nvec_register_notifier() 116 * nvec_register_notifier()
115 * @rx_data: Received messages that have to be processed 117 * @rx_data: Received messages that have to be processed
@@ -139,6 +141,7 @@ struct nvec_chip {
139 int i2c_addr; 141 int i2c_addr;
140 void __iomem *base; 142 void __iomem *base;
141 struct clk *i2c_clk; 143 struct clk *i2c_clk;
144 struct reset_control *rst;
142 struct atomic_notifier_head notifier_list; 145 struct atomic_notifier_head notifier_list;
143 struct list_head rx_data, tx_data; 146 struct list_head rx_data, tx_data;
144 struct notifier_block nvec_status_notifier; 147 struct notifier_block nvec_status_notifier;
diff --git a/drivers/staging/rtl8188eu/core/rtw_ap.c b/drivers/staging/rtl8188eu/core/rtw_ap.c
index 2c678f409573..2f548ebada59 100644
--- a/drivers/staging/rtl8188eu/core/rtw_ap.c
+++ b/drivers/staging/rtl8188eu/core/rtw_ap.c
@@ -1115,6 +1115,9 @@ int rtw_check_beacon_data(struct adapter *padapter, u8 *pbuf, int len)
1115 return _FAIL; 1115 return _FAIL;
1116 } 1116 }
1117 1117
1118 /* fix bug of flush_cam_entry at STOP AP mode */
1119 psta->state |= WIFI_AP_STATE;
1120 rtw_indicate_connect(padapter);
1118 pmlmepriv->cur_network.join_res = true;/* for check if already set beacon */ 1121 pmlmepriv->cur_network.join_res = true;/* for check if already set beacon */
1119 return ret; 1122 return ret;
1120} 1123}
diff --git a/drivers/staging/tidspbridge/Kconfig b/drivers/staging/tidspbridge/Kconfig
index 165b918b8171..1b6d581c438b 100644
--- a/drivers/staging/tidspbridge/Kconfig
+++ b/drivers/staging/tidspbridge/Kconfig
@@ -4,7 +4,7 @@
4 4
5menuconfig TIDSPBRIDGE 5menuconfig TIDSPBRIDGE
6 tristate "DSP Bridge driver" 6 tristate "DSP Bridge driver"
7 depends on ARCH_OMAP3 && !ARCH_MULTIPLATFORM 7 depends on ARCH_OMAP3 && !ARCH_MULTIPLATFORM && BROKEN
8 select MAILBOX 8 select MAILBOX
9 select OMAP2PLUS_MBOX 9 select OMAP2PLUS_MBOX
10 help 10 help
diff --git a/drivers/staging/vt6655/hostap.c b/drivers/staging/vt6655/hostap.c
index aab0012bba92..ab8b2ba6eedd 100644
--- a/drivers/staging/vt6655/hostap.c
+++ b/drivers/staging/vt6655/hostap.c
@@ -143,7 +143,8 @@ static int hostap_disable_hostapd(PSDevice pDevice, int rtnl_locked)
143 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO "%s: Netdevice %s unregistered\n", 143 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO "%s: Netdevice %s unregistered\n",
144 pDevice->dev->name, pDevice->apdev->name); 144 pDevice->dev->name, pDevice->apdev->name);
145 } 145 }
146 free_netdev(pDevice->apdev); 146 if (pDevice->apdev)
147 free_netdev(pDevice->apdev);
147 pDevice->apdev = NULL; 148 pDevice->apdev = NULL;
148 pDevice->bEnable8021x = false; 149 pDevice->bEnable8021x = false;
149 pDevice->bEnableHostWEP = false; 150 pDevice->bEnableHostWEP = false;
diff --git a/drivers/staging/vt6656/baseband.c b/drivers/staging/vt6656/baseband.c
index 1e8b8412e67e..4aa5ef54b683 100644
--- a/drivers/staging/vt6656/baseband.c
+++ b/drivers/staging/vt6656/baseband.c
@@ -939,6 +939,7 @@ int BBbVT3184Init(struct vnt_private *pDevice)
939 u8 * pbyAgc; 939 u8 * pbyAgc;
940 u16 wLengthAgc; 940 u16 wLengthAgc;
941 u8 abyArray[256]; 941 u8 abyArray[256];
942 u8 data;
942 943
943 ntStatus = CONTROLnsRequestIn(pDevice, 944 ntStatus = CONTROLnsRequestIn(pDevice,
944 MESSAGE_TYPE_READ, 945 MESSAGE_TYPE_READ,
@@ -1104,6 +1105,16 @@ else {
1104 ControlvWriteByte(pDevice,MESSAGE_REQUEST_BBREG,0x0D,0x01); 1105 ControlvWriteByte(pDevice,MESSAGE_REQUEST_BBREG,0x0D,0x01);
1105 1106
1106 RFbRFTableDownload(pDevice); 1107 RFbRFTableDownload(pDevice);
1108
1109 /* Fix for TX USB resets from vendors driver */
1110 CONTROLnsRequestIn(pDevice, MESSAGE_TYPE_READ, USB_REG4,
1111 MESSAGE_REQUEST_MEM, sizeof(data), &data);
1112
1113 data |= 0x2;
1114
1115 CONTROLnsRequestOut(pDevice, MESSAGE_TYPE_WRITE, USB_REG4,
1116 MESSAGE_REQUEST_MEM, sizeof(data), &data);
1117
1107 return true;//ntStatus; 1118 return true;//ntStatus;
1108} 1119}
1109 1120
diff --git a/drivers/staging/vt6656/hostap.c b/drivers/staging/vt6656/hostap.c
index ae1676d190c5..67ba48b9a8d9 100644
--- a/drivers/staging/vt6656/hostap.c
+++ b/drivers/staging/vt6656/hostap.c
@@ -133,7 +133,8 @@ static int hostap_disable_hostapd(struct vnt_private *pDevice, int rtnl_locked)
133 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO "%s: Netdevice %s unregistered\n", 133 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO "%s: Netdevice %s unregistered\n",
134 pDevice->dev->name, pDevice->apdev->name); 134 pDevice->dev->name, pDevice->apdev->name);
135 } 135 }
136 free_netdev(pDevice->apdev); 136 if (pDevice->apdev)
137 free_netdev(pDevice->apdev);
137 pDevice->apdev = NULL; 138 pDevice->apdev = NULL;
138 pDevice->bEnable8021x = false; 139 pDevice->bEnable8021x = false;
139 pDevice->bEnableHostWEP = false; 140 pDevice->bEnableHostWEP = false;
diff --git a/drivers/staging/vt6656/rndis.h b/drivers/staging/vt6656/rndis.h
index 5e073062017a..5cf5e732a36f 100644
--- a/drivers/staging/vt6656/rndis.h
+++ b/drivers/staging/vt6656/rndis.h
@@ -66,6 +66,8 @@
66 66
67#define VIAUSB20_PACKET_HEADER 0x04 67#define VIAUSB20_PACKET_HEADER 0x04
68 68
69#define USB_REG4 0x604
70
69typedef struct _CMD_MESSAGE 71typedef struct _CMD_MESSAGE
70{ 72{
71 u8 byData[256]; 73 u8 byData[256];
diff --git a/drivers/staging/zram/zram_drv.c b/drivers/staging/zram/zram_drv.c
index 79ce363b2ea9..3277d9838f4e 100644
--- a/drivers/staging/zram/zram_drv.c
+++ b/drivers/staging/zram/zram_drv.c
@@ -652,21 +652,30 @@ static ssize_t reset_store(struct device *dev,
652 return -ENOMEM; 652 return -ENOMEM;
653 653
654 /* Do not reset an active device! */ 654 /* Do not reset an active device! */
655 if (bdev->bd_holders) 655 if (bdev->bd_holders) {
656 return -EBUSY; 656 ret = -EBUSY;
657 goto out;
658 }
657 659
658 ret = kstrtou16(buf, 10, &do_reset); 660 ret = kstrtou16(buf, 10, &do_reset);
659 if (ret) 661 if (ret)
660 return ret; 662 goto out;
661 663
662 if (!do_reset) 664 if (!do_reset) {
663 return -EINVAL; 665 ret = -EINVAL;
666 goto out;
667 }
664 668
665 /* Make sure all pending I/O is finished */ 669 /* Make sure all pending I/O is finished */
666 fsync_bdev(bdev); 670 fsync_bdev(bdev);
671 bdput(bdev);
667 672
668 zram_reset_device(zram, true); 673 zram_reset_device(zram, true);
669 return len; 674 return len;
675
676out:
677 bdput(bdev);
678 return ret;
670} 679}
671 680
672static void __zram_make_request(struct zram *zram, struct bio *bio, int rw) 681static void __zram_make_request(struct zram *zram, struct bio *bio, int rw)
diff --git a/drivers/staging/zsmalloc/zsmalloc-main.c b/drivers/staging/zsmalloc/zsmalloc-main.c
index 1a67537dbc56..3b950e5a918f 100644
--- a/drivers/staging/zsmalloc/zsmalloc-main.c
+++ b/drivers/staging/zsmalloc/zsmalloc-main.c
@@ -430,7 +430,12 @@ static struct page *get_next_page(struct page *page)
430 return next; 430 return next;
431} 431}
432 432
433/* Encode <page, obj_idx> as a single handle value */ 433/*
434 * Encode <page, obj_idx> as a single handle value.
435 * On hardware platforms with physical memory starting at 0x0 the pfn
436 * could be 0 so we ensure that the handle will never be 0 by adjusting the
437 * encoded obj_idx value before encoding.
438 */
434static void *obj_location_to_handle(struct page *page, unsigned long obj_idx) 439static void *obj_location_to_handle(struct page *page, unsigned long obj_idx)
435{ 440{
436 unsigned long handle; 441 unsigned long handle;
@@ -441,17 +446,21 @@ static void *obj_location_to_handle(struct page *page, unsigned long obj_idx)
441 } 446 }
442 447
443 handle = page_to_pfn(page) << OBJ_INDEX_BITS; 448 handle = page_to_pfn(page) << OBJ_INDEX_BITS;
444 handle |= (obj_idx & OBJ_INDEX_MASK); 449 handle |= ((obj_idx + 1) & OBJ_INDEX_MASK);
445 450
446 return (void *)handle; 451 return (void *)handle;
447} 452}
448 453
449/* Decode <page, obj_idx> pair from the given object handle */ 454/*
455 * Decode <page, obj_idx> pair from the given object handle. We adjust the
456 * decoded obj_idx back to its original value since it was adjusted in
457 * obj_location_to_handle().
458 */
450static void obj_handle_to_location(unsigned long handle, struct page **page, 459static void obj_handle_to_location(unsigned long handle, struct page **page,
451 unsigned long *obj_idx) 460 unsigned long *obj_idx)
452{ 461{
453 *page = pfn_to_page(handle >> OBJ_INDEX_BITS); 462 *page = pfn_to_page(handle >> OBJ_INDEX_BITS);
454 *obj_idx = handle & OBJ_INDEX_MASK; 463 *obj_idx = (handle & OBJ_INDEX_MASK) - 1;
455} 464}
456 465
457static unsigned long obj_idx_to_offset(struct page *page, 466static unsigned long obj_idx_to_offset(struct page *page,
diff --git a/drivers/tty/amiserial.c b/drivers/tty/amiserial.c
index 2b86f8e0fb58..71630a2af42c 100644
--- a/drivers/tty/amiserial.c
+++ b/drivers/tty/amiserial.c
@@ -1855,6 +1855,9 @@ static struct console sercons = {
1855 */ 1855 */
1856static int __init amiserial_console_init(void) 1856static int __init amiserial_console_init(void)
1857{ 1857{
1858 if (!MACH_IS_AMIGA)
1859 return -ENODEV;
1860
1858 register_console(&sercons); 1861 register_console(&sercons);
1859 return 0; 1862 return 0;
1860} 1863}
diff --git a/drivers/tty/n_tty.c b/drivers/tty/n_tty.c
index 7cdd1eb9406c..0f74945af624 100644
--- a/drivers/tty/n_tty.c
+++ b/drivers/tty/n_tty.c
@@ -768,7 +768,7 @@ static size_t __process_echoes(struct tty_struct *tty)
768 * data at the tail to prevent a subsequent overrun */ 768 * data at the tail to prevent a subsequent overrun */
769 while (ldata->echo_commit - tail >= ECHO_DISCARD_WATERMARK) { 769 while (ldata->echo_commit - tail >= ECHO_DISCARD_WATERMARK) {
770 if (echo_buf(ldata, tail) == ECHO_OP_START) { 770 if (echo_buf(ldata, tail) == ECHO_OP_START) {
771 if (echo_buf(ldata, tail) == ECHO_OP_ERASE_TAB) 771 if (echo_buf(ldata, tail + 1) == ECHO_OP_ERASE_TAB)
772 tail += 3; 772 tail += 3;
773 else 773 else
774 tail += 2; 774 tail += 2;
@@ -1998,7 +1998,10 @@ static int canon_copy_from_read_buf(struct tty_struct *tty,
1998 found = 1; 1998 found = 1;
1999 1999
2000 size = N_TTY_BUF_SIZE - tail; 2000 size = N_TTY_BUF_SIZE - tail;
2001 n = (found + eol + size) & (N_TTY_BUF_SIZE - 1); 2001 n = eol - tail;
2002 if (n > 4096)
2003 n += 4096;
2004 n += found;
2002 c = n; 2005 c = n;
2003 2006
2004 if (found && read_buf(ldata, eol) == __DISABLED_CHAR) { 2007 if (found && read_buf(ldata, eol) == __DISABLED_CHAR) {
@@ -2243,18 +2246,19 @@ static ssize_t n_tty_read(struct tty_struct *tty, struct file *file,
2243 if (time) 2246 if (time)
2244 timeout = time; 2247 timeout = time;
2245 } 2248 }
2246 mutex_unlock(&ldata->atomic_read_lock); 2249 n_tty_set_room(tty);
2247 remove_wait_queue(&tty->read_wait, &wait); 2250 up_read(&tty->termios_rwsem);
2248 2251
2252 remove_wait_queue(&tty->read_wait, &wait);
2249 if (!waitqueue_active(&tty->read_wait)) 2253 if (!waitqueue_active(&tty->read_wait))
2250 ldata->minimum_to_wake = minimum; 2254 ldata->minimum_to_wake = minimum;
2251 2255
2256 mutex_unlock(&ldata->atomic_read_lock);
2257
2252 __set_current_state(TASK_RUNNING); 2258 __set_current_state(TASK_RUNNING);
2253 if (b - buf) 2259 if (b - buf)
2254 retval = b - buf; 2260 retval = b - buf;
2255 2261
2256 n_tty_set_room(tty);
2257 up_read(&tty->termios_rwsem);
2258 return retval; 2262 return retval;
2259} 2263}
2260 2264
diff --git a/drivers/tty/serial/8250/Kconfig b/drivers/tty/serial/8250/Kconfig
index f3b306efaa59..23329918f229 100644
--- a/drivers/tty/serial/8250/Kconfig
+++ b/drivers/tty/serial/8250/Kconfig
@@ -41,7 +41,7 @@ config SERIAL_8250_DEPRECATED_OPTIONS
41 accept kernel parameters in both forms like 8250_core.nr_uarts=4 and 41 accept kernel parameters in both forms like 8250_core.nr_uarts=4 and
42 8250.nr_uarts=4. We now renamed the module back to 8250, but if 42 8250.nr_uarts=4. We now renamed the module back to 8250, but if
43 anybody noticed in 3.7 and changed their userspace we still have to 43 anybody noticed in 3.7 and changed their userspace we still have to
44 keep the 8350_core.* options around until they revert the changes 44 keep the 8250_core.* options around until they revert the changes
45 they already did. 45 they already did.
46 46
47 If 8250 is built as a module, this adds 8250_core alias instead. 47 If 8250 is built as a module, this adds 8250_core alias instead.
diff --git a/drivers/tty/serial/pmac_zilog.c b/drivers/tty/serial/pmac_zilog.c
index 481b781b26e3..e9d420ff3931 100644
--- a/drivers/tty/serial/pmac_zilog.c
+++ b/drivers/tty/serial/pmac_zilog.c
@@ -2052,6 +2052,9 @@ static int __init pmz_console_init(void)
2052 /* Probe ports */ 2052 /* Probe ports */
2053 pmz_probe(); 2053 pmz_probe();
2054 2054
2055 if (pmz_ports_count == 0)
2056 return -ENODEV;
2057
2055 /* TODO: Autoprobe console based on OF */ 2058 /* TODO: Autoprobe console based on OF */
2056 /* pmz_console.index = i; */ 2059 /* pmz_console.index = i; */
2057 register_console(&pmz_console); 2060 register_console(&pmz_console);
diff --git a/drivers/tty/serial/serial-tegra.c b/drivers/tty/serial/serial-tegra.c
index dfe79ccc4fb3..d5c2a287b7e7 100644
--- a/drivers/tty/serial/serial-tegra.c
+++ b/drivers/tty/serial/serial-tegra.c
@@ -34,6 +34,7 @@
34#include <linux/of_device.h> 34#include <linux/of_device.h>
35#include <linux/pagemap.h> 35#include <linux/pagemap.h>
36#include <linux/platform_device.h> 36#include <linux/platform_device.h>
37#include <linux/reset.h>
37#include <linux/serial.h> 38#include <linux/serial.h>
38#include <linux/serial_8250.h> 39#include <linux/serial_8250.h>
39#include <linux/serial_core.h> 40#include <linux/serial_core.h>
@@ -44,8 +45,6 @@
44#include <linux/tty.h> 45#include <linux/tty.h>
45#include <linux/tty_flip.h> 46#include <linux/tty_flip.h>
46 47
47#include <linux/clk/tegra.h>
48
49#define TEGRA_UART_TYPE "TEGRA_UART" 48#define TEGRA_UART_TYPE "TEGRA_UART"
50#define TX_EMPTY_STATUS (UART_LSR_TEMT | UART_LSR_THRE) 49#define TX_EMPTY_STATUS (UART_LSR_TEMT | UART_LSR_THRE)
51#define BYTES_TO_ALIGN(x) ((unsigned long)(x) & 0x3) 50#define BYTES_TO_ALIGN(x) ((unsigned long)(x) & 0x3)
@@ -103,6 +102,7 @@ struct tegra_uart_port {
103 const struct tegra_uart_chip_data *cdata; 102 const struct tegra_uart_chip_data *cdata;
104 103
105 struct clk *uart_clk; 104 struct clk *uart_clk;
105 struct reset_control *rst;
106 unsigned int current_baud; 106 unsigned int current_baud;
107 107
108 /* Register shadow */ 108 /* Register shadow */
@@ -120,7 +120,6 @@ struct tegra_uart_port {
120 bool rx_timeout; 120 bool rx_timeout;
121 int rx_in_progress; 121 int rx_in_progress;
122 int symb_bit; 122 int symb_bit;
123 int dma_req_sel;
124 123
125 struct dma_chan *rx_dma_chan; 124 struct dma_chan *rx_dma_chan;
126 struct dma_chan *tx_dma_chan; 125 struct dma_chan *tx_dma_chan;
@@ -832,9 +831,9 @@ static int tegra_uart_hw_init(struct tegra_uart_port *tup)
832 clk_prepare_enable(tup->uart_clk); 831 clk_prepare_enable(tup->uart_clk);
833 832
834 /* Reset the UART controller to clear all previous status.*/ 833 /* Reset the UART controller to clear all previous status.*/
835 tegra_periph_reset_assert(tup->uart_clk); 834 reset_control_assert(tup->rst);
836 udelay(10); 835 udelay(10);
837 tegra_periph_reset_deassert(tup->uart_clk); 836 reset_control_deassert(tup->rst);
838 837
839 tup->rx_in_progress = 0; 838 tup->rx_in_progress = 0;
840 tup->tx_in_progress = 0; 839 tup->tx_in_progress = 0;
@@ -910,15 +909,14 @@ static int tegra_uart_dma_channel_allocate(struct tegra_uart_port *tup,
910 dma_addr_t dma_phys; 909 dma_addr_t dma_phys;
911 int ret; 910 int ret;
912 struct dma_slave_config dma_sconfig; 911 struct dma_slave_config dma_sconfig;
913 dma_cap_mask_t mask;
914 912
915 dma_cap_zero(mask); 913 dma_chan = dma_request_slave_channel_reason(tup->uport.dev,
916 dma_cap_set(DMA_SLAVE, mask); 914 dma_to_memory ? "rx" : "tx");
917 dma_chan = dma_request_channel(mask, NULL, NULL); 915 if (IS_ERR(dma_chan)) {
918 if (!dma_chan) { 916 ret = PTR_ERR(dma_chan);
919 dev_err(tup->uport.dev, 917 dev_err(tup->uport.dev,
920 "Dma channel is not available, will try later\n"); 918 "DMA channel alloc failed: %d\n", ret);
921 return -EPROBE_DEFER; 919 return ret;
922 } 920 }
923 921
924 if (dma_to_memory) { 922 if (dma_to_memory) {
@@ -938,7 +936,6 @@ static int tegra_uart_dma_channel_allocate(struct tegra_uart_port *tup,
938 dma_buf = tup->uport.state->xmit.buf; 936 dma_buf = tup->uport.state->xmit.buf;
939 } 937 }
940 938
941 dma_sconfig.slave_id = tup->dma_req_sel;
942 if (dma_to_memory) { 939 if (dma_to_memory) {
943 dma_sconfig.src_addr = tup->uport.mapbase; 940 dma_sconfig.src_addr = tup->uport.mapbase;
944 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 941 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
@@ -1222,17 +1219,8 @@ static int tegra_uart_parse_dt(struct platform_device *pdev,
1222 struct tegra_uart_port *tup) 1219 struct tegra_uart_port *tup)
1223{ 1220{
1224 struct device_node *np = pdev->dev.of_node; 1221 struct device_node *np = pdev->dev.of_node;
1225 u32 of_dma[2];
1226 int port; 1222 int port;
1227 1223
1228 if (of_property_read_u32_array(np, "nvidia,dma-request-selector",
1229 of_dma, 2) >= 0) {
1230 tup->dma_req_sel = of_dma[1];
1231 } else {
1232 dev_err(&pdev->dev, "missing dma requestor in device tree\n");
1233 return -EINVAL;
1234 }
1235
1236 port = of_alias_get_id(np, "serial"); 1224 port = of_alias_get_id(np, "serial");
1237 if (port < 0) { 1225 if (port < 0) {
1238 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", port); 1226 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", port);
@@ -1320,6 +1308,12 @@ static int tegra_uart_probe(struct platform_device *pdev)
1320 return PTR_ERR(tup->uart_clk); 1308 return PTR_ERR(tup->uart_clk);
1321 } 1309 }
1322 1310
1311 tup->rst = devm_reset_control_get(&pdev->dev, "serial");
1312 if (IS_ERR(tup->rst)) {
1313 dev_err(&pdev->dev, "Couldn't get the reset\n");
1314 return PTR_ERR(tup->rst);
1315 }
1316
1323 u->iotype = UPIO_MEM32; 1317 u->iotype = UPIO_MEM32;
1324 u->irq = platform_get_irq(pdev, 0); 1318 u->irq = platform_get_irq(pdev, 0);
1325 u->regshift = 2; 1319 u->regshift = 2;
diff --git a/drivers/tty/tty_io.c b/drivers/tty/tty_io.c
index 3a1a01af9a80..c74a00ad7add 100644
--- a/drivers/tty/tty_io.c
+++ b/drivers/tty/tty_io.c
@@ -2086,6 +2086,7 @@ retry_open:
2086 filp->f_op = &tty_fops; 2086 filp->f_op = &tty_fops;
2087 goto retry_open; 2087 goto retry_open;
2088 } 2088 }
2089 clear_bit(TTY_HUPPED, &tty->flags);
2089 tty_unlock(tty); 2090 tty_unlock(tty);
2090 2091
2091 2092
diff --git a/drivers/uio/uio.c b/drivers/uio/uio.c
index 67beb8444930..f7beb6eb40c7 100644
--- a/drivers/uio/uio.c
+++ b/drivers/uio/uio.c
@@ -653,6 +653,8 @@ static int uio_mmap_physical(struct vm_area_struct *vma)
653 return -EINVAL; 653 return -EINVAL;
654 mem = idev->info->mem + mi; 654 mem = idev->info->mem + mi;
655 655
656 if (mem->addr & ~PAGE_MASK)
657 return -ENODEV;
656 if (vma->vm_end - vma->vm_start > mem->size) 658 if (vma->vm_end - vma->vm_start > mem->size)
657 return -EINVAL; 659 return -EINVAL;
658 660
diff --git a/drivers/usb/gadget/atmel_usba_udc.c b/drivers/usb/gadget/atmel_usba_udc.c
index 2cb52e0438df..9f71d9fdcc14 100644
--- a/drivers/usb/gadget/atmel_usba_udc.c
+++ b/drivers/usb/gadget/atmel_usba_udc.c
@@ -326,7 +326,7 @@ static int vbus_is_present(struct usba_udc *udc)
326 326
327#if defined(CONFIG_ARCH_AT91SAM9RL) 327#if defined(CONFIG_ARCH_AT91SAM9RL)
328 328
329#include <mach/at91_pmc.h> 329#include <linux/clk/at91_pmc.h>
330 330
331static void toggle_bias(int is_on) 331static void toggle_bias(int is_on)
332{ 332{
diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c
index b9fd0396011e..6f7e23dd1417 100644
--- a/drivers/usb/host/ehci-tegra.c
+++ b/drivers/usb/host/ehci-tegra.c
@@ -17,7 +17,6 @@
17 */ 17 */
18 18
19#include <linux/clk.h> 19#include <linux/clk.h>
20#include <linux/clk/tegra.h>
21#include <linux/dma-mapping.h> 20#include <linux/dma-mapping.h>
22#include <linux/err.h> 21#include <linux/err.h>
23#include <linux/gpio.h> 22#include <linux/gpio.h>
@@ -29,6 +28,7 @@
29#include <linux/of_gpio.h> 28#include <linux/of_gpio.h>
30#include <linux/platform_device.h> 29#include <linux/platform_device.h>
31#include <linux/pm_runtime.h> 30#include <linux/pm_runtime.h>
31#include <linux/reset.h>
32#include <linux/slab.h> 32#include <linux/slab.h>
33#include <linux/usb/ehci_def.h> 33#include <linux/usb/ehci_def.h>
34#include <linux/usb/tegra_usb_phy.h> 34#include <linux/usb/tegra_usb_phy.h>
@@ -62,6 +62,7 @@ static int (*orig_hub_control)(struct usb_hcd *hcd,
62struct tegra_ehci_hcd { 62struct tegra_ehci_hcd {
63 struct tegra_usb_phy *phy; 63 struct tegra_usb_phy *phy;
64 struct clk *clk; 64 struct clk *clk;
65 struct reset_control *rst;
65 int port_resuming; 66 int port_resuming;
66 bool needs_double_reset; 67 bool needs_double_reset;
67 enum tegra_usb_phy_port_speed port_speed; 68 enum tegra_usb_phy_port_speed port_speed;
@@ -385,13 +386,20 @@ static int tegra_ehci_probe(struct platform_device *pdev)
385 goto cleanup_hcd_create; 386 goto cleanup_hcd_create;
386 } 387 }
387 388
389 tegra->rst = devm_reset_control_get(&pdev->dev, "usb");
390 if (IS_ERR(tegra->rst)) {
391 dev_err(&pdev->dev, "Can't get ehci reset\n");
392 err = PTR_ERR(tegra->rst);
393 goto cleanup_hcd_create;
394 }
395
388 err = clk_prepare_enable(tegra->clk); 396 err = clk_prepare_enable(tegra->clk);
389 if (err) 397 if (err)
390 goto cleanup_hcd_create; 398 goto cleanup_hcd_create;
391 399
392 tegra_periph_reset_assert(tegra->clk); 400 reset_control_assert(tegra->rst);
393 udelay(1); 401 udelay(1);
394 tegra_periph_reset_deassert(tegra->clk); 402 reset_control_deassert(tegra->rst);
395 403
396 u_phy = devm_usb_get_phy_by_phandle(&pdev->dev, "nvidia,phy", 0); 404 u_phy = devm_usb_get_phy_by_phandle(&pdev->dev, "nvidia,phy", 0);
397 if (IS_ERR(u_phy)) { 405 if (IS_ERR(u_phy)) {
diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c
index 8521051cf946..cd961622f9c1 100644
--- a/drivers/video/atmel_lcdfb.c
+++ b/drivers/video/atmel_lcdfb.c
@@ -131,6 +131,7 @@ static const struct platform_device_id atmel_lcdfb_devtypes[] = {
131 /* terminator */ 131 /* terminator */
132 } 132 }
133}; 133};
134MODULE_DEVICE_TABLE(platform, atmel_lcdfb_devtypes);
134 135
135static struct atmel_lcdfb_config * 136static struct atmel_lcdfb_config *
136atmel_lcdfb_get_config(struct platform_device *pdev) 137atmel_lcdfb_get_config(struct platform_device *pdev)
diff --git a/drivers/video/kyro/fbdev.c b/drivers/video/kyro/fbdev.c
index 50c857477e4f..65041e15fd59 100644
--- a/drivers/video/kyro/fbdev.c
+++ b/drivers/video/kyro/fbdev.c
@@ -624,15 +624,15 @@ static int kyrofb_ioctl(struct fb_info *info,
624 return -EINVAL; 624 return -EINVAL;
625 } 625 }
626 case KYRO_IOCTL_UVSTRIDE: 626 case KYRO_IOCTL_UVSTRIDE:
627 if (copy_to_user(argp, &deviceInfo.ulOverlayUVStride, sizeof(unsigned long))) 627 if (copy_to_user(argp, &deviceInfo.ulOverlayUVStride, sizeof(deviceInfo.ulOverlayUVStride)))
628 return -EFAULT; 628 return -EFAULT;
629 break; 629 break;
630 case KYRO_IOCTL_STRIDE: 630 case KYRO_IOCTL_STRIDE:
631 if (copy_to_user(argp, &deviceInfo.ulOverlayStride, sizeof(unsigned long))) 631 if (copy_to_user(argp, &deviceInfo.ulOverlayStride, sizeof(deviceInfo.ulOverlayStride)))
632 return -EFAULT; 632 return -EFAULT;
633 break; 633 break;
634 case KYRO_IOCTL_OVERLAY_OFFSET: 634 case KYRO_IOCTL_OVERLAY_OFFSET:
635 if (copy_to_user(argp, &deviceInfo.ulOverlayOffset, sizeof(unsigned long))) 635 if (copy_to_user(argp, &deviceInfo.ulOverlayOffset, sizeof(deviceInfo.ulOverlayOffset)))
636 return -EFAULT; 636 return -EFAULT;
637 break; 637 break;
638 } 638 }
diff --git a/drivers/video/omap2/displays-new/panel-sony-acx565akm.c b/drivers/video/omap2/displays-new/panel-sony-acx565akm.c
index e6d56f714ae4..d94f35dbd536 100644
--- a/drivers/video/omap2/displays-new/panel-sony-acx565akm.c
+++ b/drivers/video/omap2/displays-new/panel-sony-acx565akm.c
@@ -526,6 +526,8 @@ static int acx565akm_panel_power_on(struct omap_dss_device *dssdev)
526 struct omap_dss_device *in = ddata->in; 526 struct omap_dss_device *in = ddata->in;
527 int r; 527 int r;
528 528
529 mutex_lock(&ddata->mutex);
530
529 dev_dbg(&ddata->spi->dev, "%s\n", __func__); 531 dev_dbg(&ddata->spi->dev, "%s\n", __func__);
530 532
531 in->ops.sdi->set_timings(in, &ddata->videomode); 533 in->ops.sdi->set_timings(in, &ddata->videomode);
@@ -614,10 +616,7 @@ static int acx565akm_enable(struct omap_dss_device *dssdev)
614 if (omapdss_device_is_enabled(dssdev)) 616 if (omapdss_device_is_enabled(dssdev))
615 return 0; 617 return 0;
616 618
617 mutex_lock(&ddata->mutex);
618 r = acx565akm_panel_power_on(dssdev); 619 r = acx565akm_panel_power_on(dssdev);
619 mutex_unlock(&ddata->mutex);
620
621 if (r) 620 if (r)
622 return r; 621 return r;
623 622
diff --git a/drivers/video/sh_mobile_meram.c b/drivers/video/sh_mobile_meram.c
index e0f098562a74..a297de5cc859 100644
--- a/drivers/video/sh_mobile_meram.c
+++ b/drivers/video/sh_mobile_meram.c
@@ -569,6 +569,7 @@ EXPORT_SYMBOL_GPL(sh_mobile_meram_cache_update);
569 * Power management 569 * Power management
570 */ 570 */
571 571
572#if defined(CONFIG_PM_SLEEP) || defined(CONFIG_PM_RUNTIME)
572static int sh_mobile_meram_suspend(struct device *dev) 573static int sh_mobile_meram_suspend(struct device *dev)
573{ 574{
574 struct platform_device *pdev = to_platform_device(dev); 575 struct platform_device *pdev = to_platform_device(dev);
@@ -611,6 +612,7 @@ static int sh_mobile_meram_resume(struct device *dev)
611 meram_write_reg(priv->base, common_regs[i], priv->regs[i]); 612 meram_write_reg(priv->base, common_regs[i], priv->regs[i]);
612 return 0; 613 return 0;
613} 614}
615#endif /* CONFIG_PM_SLEEP || CONFIG_PM_RUNTIME */
614 616
615static UNIVERSAL_DEV_PM_OPS(sh_mobile_meram_dev_pm_ops, 617static UNIVERSAL_DEV_PM_OPS(sh_mobile_meram_dev_pm_ops,
616 sh_mobile_meram_suspend, 618 sh_mobile_meram_suspend,
diff --git a/drivers/video/vt8500lcdfb.c b/drivers/video/vt8500lcdfb.c
index b30e5a439d1f..a8f2b280f796 100644
--- a/drivers/video/vt8500lcdfb.c
+++ b/drivers/video/vt8500lcdfb.c
@@ -293,8 +293,7 @@ static int vt8500lcd_probe(struct platform_device *pdev)
293 + sizeof(u32) * 16, GFP_KERNEL); 293 + sizeof(u32) * 16, GFP_KERNEL);
294 if (!fbi) { 294 if (!fbi) {
295 dev_err(&pdev->dev, "Failed to initialize framebuffer device\n"); 295 dev_err(&pdev->dev, "Failed to initialize framebuffer device\n");
296 ret = -ENOMEM; 296 return -ENOMEM;
297 goto failed;
298 } 297 }
299 298
300 strcpy(fbi->fb.fix.id, "VT8500 LCD"); 299 strcpy(fbi->fb.fix.id, "VT8500 LCD");
@@ -327,15 +326,13 @@ static int vt8500lcd_probe(struct platform_device *pdev)
327 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 326 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
328 if (res == NULL) { 327 if (res == NULL) {
329 dev_err(&pdev->dev, "no I/O memory resource defined\n"); 328 dev_err(&pdev->dev, "no I/O memory resource defined\n");
330 ret = -ENODEV; 329 return -ENODEV;
331 goto failed_fbi;
332 } 330 }
333 331
334 res = request_mem_region(res->start, resource_size(res), "vt8500lcd"); 332 res = request_mem_region(res->start, resource_size(res), "vt8500lcd");
335 if (res == NULL) { 333 if (res == NULL) {
336 dev_err(&pdev->dev, "failed to request I/O memory\n"); 334 dev_err(&pdev->dev, "failed to request I/O memory\n");
337 ret = -EBUSY; 335 return -EBUSY;
338 goto failed_fbi;
339 } 336 }
340 337
341 fbi->regbase = ioremap(res->start, resource_size(res)); 338 fbi->regbase = ioremap(res->start, resource_size(res));
@@ -346,17 +343,19 @@ static int vt8500lcd_probe(struct platform_device *pdev)
346 } 343 }
347 344
348 disp_timing = of_get_display_timings(pdev->dev.of_node); 345 disp_timing = of_get_display_timings(pdev->dev.of_node);
349 if (!disp_timing) 346 if (!disp_timing) {
350 return -EINVAL; 347 ret = -EINVAL;
348 goto failed_free_io;
349 }
351 350
352 ret = of_get_fb_videomode(pdev->dev.of_node, &of_mode, 351 ret = of_get_fb_videomode(pdev->dev.of_node, &of_mode,
353 OF_USE_NATIVE_MODE); 352 OF_USE_NATIVE_MODE);
354 if (ret) 353 if (ret)
355 return ret; 354 goto failed_free_io;
356 355
357 ret = of_property_read_u32(pdev->dev.of_node, "bits-per-pixel", &bpp); 356 ret = of_property_read_u32(pdev->dev.of_node, "bits-per-pixel", &bpp);
358 if (ret) 357 if (ret)
359 return ret; 358 goto failed_free_io;
360 359
361 /* try allocating the framebuffer */ 360 /* try allocating the framebuffer */
362 fb_mem_len = of_mode.xres * of_mode.yres * 2 * (bpp / 8); 361 fb_mem_len = of_mode.xres * of_mode.yres * 2 * (bpp / 8);
@@ -364,7 +363,8 @@ static int vt8500lcd_probe(struct platform_device *pdev)
364 GFP_KERNEL); 363 GFP_KERNEL);
365 if (!fb_mem_virt) { 364 if (!fb_mem_virt) {
366 pr_err("%s: Failed to allocate framebuffer\n", __func__); 365 pr_err("%s: Failed to allocate framebuffer\n", __func__);
367 return -ENOMEM; 366 ret = -ENOMEM;
367 goto failed_free_io;
368 } 368 }
369 369
370 fbi->fb.fix.smem_start = fb_mem_phys; 370 fbi->fb.fix.smem_start = fb_mem_phys;
@@ -447,9 +447,6 @@ failed_free_io:
447 iounmap(fbi->regbase); 447 iounmap(fbi->regbase);
448failed_free_res: 448failed_free_res:
449 release_mem_region(res->start, resource_size(res)); 449 release_mem_region(res->start, resource_size(res));
450failed_fbi:
451 kfree(fbi);
452failed:
453 return ret; 450 return ret;
454} 451}
455 452
diff --git a/drivers/xen/grant-table.c b/drivers/xen/grant-table.c
index 62ccf5424ba8..028387192b60 100644
--- a/drivers/xen/grant-table.c
+++ b/drivers/xen/grant-table.c
@@ -930,9 +930,10 @@ int gnttab_map_refs(struct gnttab_map_grant_ref *map_ops,
930 ret = m2p_add_override(mfn, pages[i], kmap_ops ? 930 ret = m2p_add_override(mfn, pages[i], kmap_ops ?
931 &kmap_ops[i] : NULL); 931 &kmap_ops[i] : NULL);
932 if (ret) 932 if (ret)
933 return ret; 933 goto out;
934 } 934 }
935 935
936 out:
936 if (lazy) 937 if (lazy)
937 arch_leave_lazy_mmu_mode(); 938 arch_leave_lazy_mmu_mode();
938 939
@@ -969,9 +970,10 @@ int gnttab_unmap_refs(struct gnttab_unmap_grant_ref *unmap_ops,
969 ret = m2p_remove_override(pages[i], kmap_ops ? 970 ret = m2p_remove_override(pages[i], kmap_ops ?
970 &kmap_ops[i] : NULL); 971 &kmap_ops[i] : NULL);
971 if (ret) 972 if (ret)
972 return ret; 973 goto out;
973 } 974 }
974 975
976 out:
975 if (lazy) 977 if (lazy)
976 arch_leave_lazy_mmu_mode(); 978 arch_leave_lazy_mmu_mode();
977 979
diff --git a/drivers/xen/swiotlb-xen.c b/drivers/xen/swiotlb-xen.c
index a224bc74b6b9..1eac0731c349 100644
--- a/drivers/xen/swiotlb-xen.c
+++ b/drivers/xen/swiotlb-xen.c
@@ -555,6 +555,11 @@ xen_swiotlb_map_sg_attrs(struct device *hwdev, struct scatterlist *sgl,
555 sg_dma_len(sgl) = 0; 555 sg_dma_len(sgl) = 0;
556 return 0; 556 return 0;
557 } 557 }
558 xen_dma_map_page(hwdev, pfn_to_page(map >> PAGE_SHIFT),
559 map & ~PAGE_MASK,
560 sg->length,
561 dir,
562 attrs);
558 sg->dma_address = xen_phys_to_bus(map); 563 sg->dma_address = xen_phys_to_bus(map);
559 } else { 564 } else {
560 /* we are not interested in the dma_addr returned by 565 /* we are not interested in the dma_addr returned by
diff --git a/fs/affs/Changes b/fs/affs/Changes
index a29409c1ffe0..b41c2c9792ff 100644
--- a/fs/affs/Changes
+++ b/fs/affs/Changes
@@ -91,7 +91,7 @@ more 2.4 fixes: [Roman Zippel]
91Version 3.11 91Version 3.11
92------------ 92------------
93 93
94- Converted to use 2.3.x page cache [Dave Jones <dave@powertweak.com>] 94- Converted to use 2.3.x page cache [Dave Jones]
95- Corruption in truncate() bugfix [Ken Tyler <kent@werple.net.au>] 95- Corruption in truncate() bugfix [Ken Tyler <kent@werple.net.au>]
96 96
97Version 3.10 97Version 3.10
diff --git a/fs/aio.c b/fs/aio.c
index 08159ed13649..6efb7f6cb22e 100644
--- a/fs/aio.c
+++ b/fs/aio.c
@@ -367,8 +367,10 @@ static int aio_setup_ring(struct kioctx *ctx)
367 if (nr_pages > AIO_RING_PAGES) { 367 if (nr_pages > AIO_RING_PAGES) {
368 ctx->ring_pages = kcalloc(nr_pages, sizeof(struct page *), 368 ctx->ring_pages = kcalloc(nr_pages, sizeof(struct page *),
369 GFP_KERNEL); 369 GFP_KERNEL);
370 if (!ctx->ring_pages) 370 if (!ctx->ring_pages) {
371 put_aio_ring_file(ctx);
371 return -ENOMEM; 372 return -ENOMEM;
373 }
372 } 374 }
373 375
374 ctx->mmap_size = nr_pages * PAGE_SIZE; 376 ctx->mmap_size = nr_pages * PAGE_SIZE;
@@ -645,7 +647,7 @@ static struct kioctx *ioctx_alloc(unsigned nr_events)
645 aio_nr + nr_events < aio_nr) { 647 aio_nr + nr_events < aio_nr) {
646 spin_unlock(&aio_nr_lock); 648 spin_unlock(&aio_nr_lock);
647 err = -EAGAIN; 649 err = -EAGAIN;
648 goto err; 650 goto err_ctx;
649 } 651 }
650 aio_nr += ctx->max_reqs; 652 aio_nr += ctx->max_reqs;
651 spin_unlock(&aio_nr_lock); 653 spin_unlock(&aio_nr_lock);
@@ -662,6 +664,8 @@ static struct kioctx *ioctx_alloc(unsigned nr_events)
662 664
663err_cleanup: 665err_cleanup:
664 aio_nr_sub(ctx->max_reqs); 666 aio_nr_sub(ctx->max_reqs);
667err_ctx:
668 aio_free_ring(ctx);
665err: 669err:
666 free_percpu(ctx->cpu); 670 free_percpu(ctx->cpu);
667 free_percpu(ctx->reqs.pcpu_count); 671 free_percpu(ctx->reqs.pcpu_count);
diff --git a/fs/btrfs/check-integrity.c b/fs/btrfs/check-integrity.c
index b50764bef141..131d82800b3a 100644
--- a/fs/btrfs/check-integrity.c
+++ b/fs/btrfs/check-integrity.c
@@ -333,7 +333,6 @@ static void btrfsic_release_block_ctx(struct btrfsic_block_data_ctx *block_ctx);
333static int btrfsic_read_block(struct btrfsic_state *state, 333static int btrfsic_read_block(struct btrfsic_state *state,
334 struct btrfsic_block_data_ctx *block_ctx); 334 struct btrfsic_block_data_ctx *block_ctx);
335static void btrfsic_dump_database(struct btrfsic_state *state); 335static void btrfsic_dump_database(struct btrfsic_state *state);
336static void btrfsic_complete_bio_end_io(struct bio *bio, int err);
337static int btrfsic_test_for_metadata(struct btrfsic_state *state, 336static int btrfsic_test_for_metadata(struct btrfsic_state *state,
338 char **datav, unsigned int num_pages); 337 char **datav, unsigned int num_pages);
339static void btrfsic_process_written_block(struct btrfsic_dev_state *dev_state, 338static void btrfsic_process_written_block(struct btrfsic_dev_state *dev_state,
@@ -1687,7 +1686,6 @@ static int btrfsic_read_block(struct btrfsic_state *state,
1687 for (i = 0; i < num_pages;) { 1686 for (i = 0; i < num_pages;) {
1688 struct bio *bio; 1687 struct bio *bio;
1689 unsigned int j; 1688 unsigned int j;
1690 DECLARE_COMPLETION_ONSTACK(complete);
1691 1689
1692 bio = btrfs_io_bio_alloc(GFP_NOFS, num_pages - i); 1690 bio = btrfs_io_bio_alloc(GFP_NOFS, num_pages - i);
1693 if (!bio) { 1691 if (!bio) {
@@ -1698,8 +1696,6 @@ static int btrfsic_read_block(struct btrfsic_state *state,
1698 } 1696 }
1699 bio->bi_bdev = block_ctx->dev->bdev; 1697 bio->bi_bdev = block_ctx->dev->bdev;
1700 bio->bi_sector = dev_bytenr >> 9; 1698 bio->bi_sector = dev_bytenr >> 9;
1701 bio->bi_end_io = btrfsic_complete_bio_end_io;
1702 bio->bi_private = &complete;
1703 1699
1704 for (j = i; j < num_pages; j++) { 1700 for (j = i; j < num_pages; j++) {
1705 ret = bio_add_page(bio, block_ctx->pagev[j], 1701 ret = bio_add_page(bio, block_ctx->pagev[j],
@@ -1712,12 +1708,7 @@ static int btrfsic_read_block(struct btrfsic_state *state,
1712 "btrfsic: error, failed to add a single page!\n"); 1708 "btrfsic: error, failed to add a single page!\n");
1713 return -1; 1709 return -1;
1714 } 1710 }
1715 submit_bio(READ, bio); 1711 if (submit_bio_wait(READ, bio)) {
1716
1717 /* this will also unplug the queue */
1718 wait_for_completion(&complete);
1719
1720 if (!test_bit(BIO_UPTODATE, &bio->bi_flags)) {
1721 printk(KERN_INFO 1712 printk(KERN_INFO
1722 "btrfsic: read error at logical %llu dev %s!\n", 1713 "btrfsic: read error at logical %llu dev %s!\n",
1723 block_ctx->start, block_ctx->dev->name); 1714 block_ctx->start, block_ctx->dev->name);
@@ -1740,11 +1731,6 @@ static int btrfsic_read_block(struct btrfsic_state *state,
1740 return block_ctx->len; 1731 return block_ctx->len;
1741} 1732}
1742 1733
1743static void btrfsic_complete_bio_end_io(struct bio *bio, int err)
1744{
1745 complete((struct completion *)bio->bi_private);
1746}
1747
1748static void btrfsic_dump_database(struct btrfsic_state *state) 1734static void btrfsic_dump_database(struct btrfsic_state *state)
1749{ 1735{
1750 struct list_head *elem_all; 1736 struct list_head *elem_all;
@@ -3008,14 +2994,12 @@ int btrfsic_submit_bh(int rw, struct buffer_head *bh)
3008 return submit_bh(rw, bh); 2994 return submit_bh(rw, bh);
3009} 2995}
3010 2996
3011void btrfsic_submit_bio(int rw, struct bio *bio) 2997static void __btrfsic_submit_bio(int rw, struct bio *bio)
3012{ 2998{
3013 struct btrfsic_dev_state *dev_state; 2999 struct btrfsic_dev_state *dev_state;
3014 3000
3015 if (!btrfsic_is_initialized) { 3001 if (!btrfsic_is_initialized)
3016 submit_bio(rw, bio);
3017 return; 3002 return;
3018 }
3019 3003
3020 mutex_lock(&btrfsic_mutex); 3004 mutex_lock(&btrfsic_mutex);
3021 /* since btrfsic_submit_bio() is also called before 3005 /* since btrfsic_submit_bio() is also called before
@@ -3106,10 +3090,20 @@ void btrfsic_submit_bio(int rw, struct bio *bio)
3106 } 3090 }
3107leave: 3091leave:
3108 mutex_unlock(&btrfsic_mutex); 3092 mutex_unlock(&btrfsic_mutex);
3093}
3109 3094
3095void btrfsic_submit_bio(int rw, struct bio *bio)
3096{
3097 __btrfsic_submit_bio(rw, bio);
3110 submit_bio(rw, bio); 3098 submit_bio(rw, bio);
3111} 3099}
3112 3100
3101int btrfsic_submit_bio_wait(int rw, struct bio *bio)
3102{
3103 __btrfsic_submit_bio(rw, bio);
3104 return submit_bio_wait(rw, bio);
3105}
3106
3113int btrfsic_mount(struct btrfs_root *root, 3107int btrfsic_mount(struct btrfs_root *root,
3114 struct btrfs_fs_devices *fs_devices, 3108 struct btrfs_fs_devices *fs_devices,
3115 int including_extent_data, u32 print_mask) 3109 int including_extent_data, u32 print_mask)
diff --git a/fs/btrfs/check-integrity.h b/fs/btrfs/check-integrity.h
index 8b59175cc502..13b8566c97ab 100644
--- a/fs/btrfs/check-integrity.h
+++ b/fs/btrfs/check-integrity.h
@@ -22,9 +22,11 @@
22#ifdef CONFIG_BTRFS_FS_CHECK_INTEGRITY 22#ifdef CONFIG_BTRFS_FS_CHECK_INTEGRITY
23int btrfsic_submit_bh(int rw, struct buffer_head *bh); 23int btrfsic_submit_bh(int rw, struct buffer_head *bh);
24void btrfsic_submit_bio(int rw, struct bio *bio); 24void btrfsic_submit_bio(int rw, struct bio *bio);
25int btrfsic_submit_bio_wait(int rw, struct bio *bio);
25#else 26#else
26#define btrfsic_submit_bh submit_bh 27#define btrfsic_submit_bh submit_bh
27#define btrfsic_submit_bio submit_bio 28#define btrfsic_submit_bio submit_bio
29#define btrfsic_submit_bio_wait submit_bio_wait
28#endif 30#endif
29 31
30int btrfsic_mount(struct btrfs_root *root, 32int btrfsic_mount(struct btrfs_root *root,
diff --git a/fs/btrfs/extent_io.c b/fs/btrfs/extent_io.c
index 8e457fca0a0b..ff43802a7c88 100644
--- a/fs/btrfs/extent_io.c
+++ b/fs/btrfs/extent_io.c
@@ -1952,11 +1952,6 @@ static int free_io_failure(struct inode *inode, struct io_failure_record *rec,
1952 return err; 1952 return err;
1953} 1953}
1954 1954
1955static void repair_io_failure_callback(struct bio *bio, int err)
1956{
1957 complete(bio->bi_private);
1958}
1959
1960/* 1955/*
1961 * this bypasses the standard btrfs submit functions deliberately, as 1956 * this bypasses the standard btrfs submit functions deliberately, as
1962 * the standard behavior is to write all copies in a raid setup. here we only 1957 * the standard behavior is to write all copies in a raid setup. here we only
@@ -1973,7 +1968,6 @@ int repair_io_failure(struct btrfs_fs_info *fs_info, u64 start,
1973{ 1968{
1974 struct bio *bio; 1969 struct bio *bio;
1975 struct btrfs_device *dev; 1970 struct btrfs_device *dev;
1976 DECLARE_COMPLETION_ONSTACK(compl);
1977 u64 map_length = 0; 1971 u64 map_length = 0;
1978 u64 sector; 1972 u64 sector;
1979 struct btrfs_bio *bbio = NULL; 1973 struct btrfs_bio *bbio = NULL;
@@ -1990,8 +1984,6 @@ int repair_io_failure(struct btrfs_fs_info *fs_info, u64 start,
1990 bio = btrfs_io_bio_alloc(GFP_NOFS, 1); 1984 bio = btrfs_io_bio_alloc(GFP_NOFS, 1);
1991 if (!bio) 1985 if (!bio)
1992 return -EIO; 1986 return -EIO;
1993 bio->bi_private = &compl;
1994 bio->bi_end_io = repair_io_failure_callback;
1995 bio->bi_size = 0; 1987 bio->bi_size = 0;
1996 map_length = length; 1988 map_length = length;
1997 1989
@@ -2012,10 +2004,8 @@ int repair_io_failure(struct btrfs_fs_info *fs_info, u64 start,
2012 } 2004 }
2013 bio->bi_bdev = dev->bdev; 2005 bio->bi_bdev = dev->bdev;
2014 bio_add_page(bio, page, length, start - page_offset(page)); 2006 bio_add_page(bio, page, length, start - page_offset(page));
2015 btrfsic_submit_bio(WRITE_SYNC, bio);
2016 wait_for_completion(&compl);
2017 2007
2018 if (!test_bit(BIO_UPTODATE, &bio->bi_flags)) { 2008 if (btrfsic_submit_bio_wait(WRITE_SYNC, bio)) {
2019 /* try to remap that extent elsewhere? */ 2009 /* try to remap that extent elsewhere? */
2020 bio_put(bio); 2010 bio_put(bio);
2021 btrfs_dev_stat_inc_and_print(dev, BTRFS_DEV_STAT_WRITE_ERRS); 2011 btrfs_dev_stat_inc_and_print(dev, BTRFS_DEV_STAT_WRITE_ERRS);
diff --git a/fs/btrfs/scrub.c b/fs/btrfs/scrub.c
index 561e2f16ba3e..1fd3f33c330a 100644
--- a/fs/btrfs/scrub.c
+++ b/fs/btrfs/scrub.c
@@ -208,7 +208,6 @@ static void scrub_recheck_block_checksum(struct btrfs_fs_info *fs_info,
208 int is_metadata, int have_csum, 208 int is_metadata, int have_csum,
209 const u8 *csum, u64 generation, 209 const u8 *csum, u64 generation,
210 u16 csum_size); 210 u16 csum_size);
211static void scrub_complete_bio_end_io(struct bio *bio, int err);
212static int scrub_repair_block_from_good_copy(struct scrub_block *sblock_bad, 211static int scrub_repair_block_from_good_copy(struct scrub_block *sblock_bad,
213 struct scrub_block *sblock_good, 212 struct scrub_block *sblock_good,
214 int force_write); 213 int force_write);
@@ -1294,7 +1293,6 @@ static void scrub_recheck_block(struct btrfs_fs_info *fs_info,
1294 for (page_num = 0; page_num < sblock->page_count; page_num++) { 1293 for (page_num = 0; page_num < sblock->page_count; page_num++) {
1295 struct bio *bio; 1294 struct bio *bio;
1296 struct scrub_page *page = sblock->pagev[page_num]; 1295 struct scrub_page *page = sblock->pagev[page_num];
1297 DECLARE_COMPLETION_ONSTACK(complete);
1298 1296
1299 if (page->dev->bdev == NULL) { 1297 if (page->dev->bdev == NULL) {
1300 page->io_error = 1; 1298 page->io_error = 1;
@@ -1311,18 +1309,11 @@ static void scrub_recheck_block(struct btrfs_fs_info *fs_info,
1311 } 1309 }
1312 bio->bi_bdev = page->dev->bdev; 1310 bio->bi_bdev = page->dev->bdev;
1313 bio->bi_sector = page->physical >> 9; 1311 bio->bi_sector = page->physical >> 9;
1314 bio->bi_end_io = scrub_complete_bio_end_io;
1315 bio->bi_private = &complete;
1316 1312
1317 bio_add_page(bio, page->page, PAGE_SIZE, 0); 1313 bio_add_page(bio, page->page, PAGE_SIZE, 0);
1318 btrfsic_submit_bio(READ, bio); 1314 if (btrfsic_submit_bio_wait(READ, bio))
1319
1320 /* this will also unplug the queue */
1321 wait_for_completion(&complete);
1322
1323 page->io_error = !test_bit(BIO_UPTODATE, &bio->bi_flags);
1324 if (!test_bit(BIO_UPTODATE, &bio->bi_flags))
1325 sblock->no_io_error_seen = 0; 1315 sblock->no_io_error_seen = 0;
1316
1326 bio_put(bio); 1317 bio_put(bio);
1327 } 1318 }
1328 1319
@@ -1391,11 +1382,6 @@ static void scrub_recheck_block_checksum(struct btrfs_fs_info *fs_info,
1391 sblock->checksum_error = 1; 1382 sblock->checksum_error = 1;
1392} 1383}
1393 1384
1394static void scrub_complete_bio_end_io(struct bio *bio, int err)
1395{
1396 complete((struct completion *)bio->bi_private);
1397}
1398
1399static int scrub_repair_block_from_good_copy(struct scrub_block *sblock_bad, 1385static int scrub_repair_block_from_good_copy(struct scrub_block *sblock_bad,
1400 struct scrub_block *sblock_good, 1386 struct scrub_block *sblock_good,
1401 int force_write) 1387 int force_write)
@@ -1430,7 +1416,6 @@ static int scrub_repair_page_from_good_copy(struct scrub_block *sblock_bad,
1430 sblock_bad->checksum_error || page_bad->io_error) { 1416 sblock_bad->checksum_error || page_bad->io_error) {
1431 struct bio *bio; 1417 struct bio *bio;
1432 int ret; 1418 int ret;
1433 DECLARE_COMPLETION_ONSTACK(complete);
1434 1419
1435 if (!page_bad->dev->bdev) { 1420 if (!page_bad->dev->bdev) {
1436 printk_ratelimited(KERN_WARNING 1421 printk_ratelimited(KERN_WARNING
@@ -1443,19 +1428,14 @@ static int scrub_repair_page_from_good_copy(struct scrub_block *sblock_bad,
1443 return -EIO; 1428 return -EIO;
1444 bio->bi_bdev = page_bad->dev->bdev; 1429 bio->bi_bdev = page_bad->dev->bdev;
1445 bio->bi_sector = page_bad->physical >> 9; 1430 bio->bi_sector = page_bad->physical >> 9;
1446 bio->bi_end_io = scrub_complete_bio_end_io;
1447 bio->bi_private = &complete;
1448 1431
1449 ret = bio_add_page(bio, page_good->page, PAGE_SIZE, 0); 1432 ret = bio_add_page(bio, page_good->page, PAGE_SIZE, 0);
1450 if (PAGE_SIZE != ret) { 1433 if (PAGE_SIZE != ret) {
1451 bio_put(bio); 1434 bio_put(bio);
1452 return -EIO; 1435 return -EIO;
1453 } 1436 }
1454 btrfsic_submit_bio(WRITE, bio);
1455 1437
1456 /* this will also unplug the queue */ 1438 if (btrfsic_submit_bio_wait(WRITE, bio)) {
1457 wait_for_completion(&complete);
1458 if (!bio_flagged(bio, BIO_UPTODATE)) {
1459 btrfs_dev_stat_inc_and_print(page_bad->dev, 1439 btrfs_dev_stat_inc_and_print(page_bad->dev,
1460 BTRFS_DEV_STAT_WRITE_ERRS); 1440 BTRFS_DEV_STAT_WRITE_ERRS);
1461 btrfs_dev_replace_stats_inc( 1441 btrfs_dev_replace_stats_inc(
@@ -3375,7 +3355,6 @@ static int write_page_nocow(struct scrub_ctx *sctx,
3375 struct bio *bio; 3355 struct bio *bio;
3376 struct btrfs_device *dev; 3356 struct btrfs_device *dev;
3377 int ret; 3357 int ret;
3378 DECLARE_COMPLETION_ONSTACK(compl);
3379 3358
3380 dev = sctx->wr_ctx.tgtdev; 3359 dev = sctx->wr_ctx.tgtdev;
3381 if (!dev) 3360 if (!dev)
@@ -3392,8 +3371,6 @@ static int write_page_nocow(struct scrub_ctx *sctx,
3392 spin_unlock(&sctx->stat_lock); 3371 spin_unlock(&sctx->stat_lock);
3393 return -ENOMEM; 3372 return -ENOMEM;
3394 } 3373 }
3395 bio->bi_private = &compl;
3396 bio->bi_end_io = scrub_complete_bio_end_io;
3397 bio->bi_size = 0; 3374 bio->bi_size = 0;
3398 bio->bi_sector = physical_for_dev_replace >> 9; 3375 bio->bi_sector = physical_for_dev_replace >> 9;
3399 bio->bi_bdev = dev->bdev; 3376 bio->bi_bdev = dev->bdev;
@@ -3404,10 +3381,8 @@ leave_with_eio:
3404 btrfs_dev_stat_inc_and_print(dev, BTRFS_DEV_STAT_WRITE_ERRS); 3381 btrfs_dev_stat_inc_and_print(dev, BTRFS_DEV_STAT_WRITE_ERRS);
3405 return -EIO; 3382 return -EIO;
3406 } 3383 }
3407 btrfsic_submit_bio(WRITE_SYNC, bio);
3408 wait_for_completion(&compl);
3409 3384
3410 if (!test_bit(BIO_UPTODATE, &bio->bi_flags)) 3385 if (btrfsic_submit_bio_wait(WRITE_SYNC, bio))
3411 goto leave_with_eio; 3386 goto leave_with_eio;
3412 3387
3413 bio_put(bio); 3388 bio_put(bio);
diff --git a/fs/ceph/addr.c b/fs/ceph/addr.c
index 6df8bd481425..1e561c059539 100644
--- a/fs/ceph/addr.c
+++ b/fs/ceph/addr.c
@@ -216,7 +216,7 @@ static int readpage_nounlock(struct file *filp, struct page *page)
216 } 216 }
217 SetPageUptodate(page); 217 SetPageUptodate(page);
218 218
219 if (err == 0) 219 if (err >= 0)
220 ceph_readpage_to_fscache(inode, page); 220 ceph_readpage_to_fscache(inode, page);
221 221
222out: 222out:
diff --git a/fs/ceph/cache.c b/fs/ceph/cache.c
index 7db2e6ca4b8f..8c44fdd4e1c3 100644
--- a/fs/ceph/cache.c
+++ b/fs/ceph/cache.c
@@ -324,6 +324,9 @@ void ceph_invalidate_fscache_page(struct inode* inode, struct page *page)
324{ 324{
325 struct ceph_inode_info *ci = ceph_inode(inode); 325 struct ceph_inode_info *ci = ceph_inode(inode);
326 326
327 if (!PageFsCache(page))
328 return;
329
327 fscache_wait_on_page_write(ci->fscache, page); 330 fscache_wait_on_page_write(ci->fscache, page);
328 fscache_uncache_page(ci->fscache, page); 331 fscache_uncache_page(ci->fscache, page);
329} 332}
diff --git a/fs/ceph/caps.c b/fs/ceph/caps.c
index 13976c33332e..3c0a4bd74996 100644
--- a/fs/ceph/caps.c
+++ b/fs/ceph/caps.c
@@ -897,7 +897,7 @@ static int __ceph_is_any_caps(struct ceph_inode_info *ci)
897 * caller should hold i_ceph_lock. 897 * caller should hold i_ceph_lock.
898 * caller will not hold session s_mutex if called from destroy_inode. 898 * caller will not hold session s_mutex if called from destroy_inode.
899 */ 899 */
900void __ceph_remove_cap(struct ceph_cap *cap) 900void __ceph_remove_cap(struct ceph_cap *cap, bool queue_release)
901{ 901{
902 struct ceph_mds_session *session = cap->session; 902 struct ceph_mds_session *session = cap->session;
903 struct ceph_inode_info *ci = cap->ci; 903 struct ceph_inode_info *ci = cap->ci;
@@ -909,6 +909,16 @@ void __ceph_remove_cap(struct ceph_cap *cap)
909 909
910 /* remove from session list */ 910 /* remove from session list */
911 spin_lock(&session->s_cap_lock); 911 spin_lock(&session->s_cap_lock);
912 /*
913 * s_cap_reconnect is protected by s_cap_lock. no one changes
914 * s_cap_gen while session is in the reconnect state.
915 */
916 if (queue_release &&
917 (!session->s_cap_reconnect ||
918 cap->cap_gen == session->s_cap_gen))
919 __queue_cap_release(session, ci->i_vino.ino, cap->cap_id,
920 cap->mseq, cap->issue_seq);
921
912 if (session->s_cap_iterator == cap) { 922 if (session->s_cap_iterator == cap) {
913 /* not yet, we are iterating over this very cap */ 923 /* not yet, we are iterating over this very cap */
914 dout("__ceph_remove_cap delaying %p removal from session %p\n", 924 dout("__ceph_remove_cap delaying %p removal from session %p\n",
@@ -1023,7 +1033,6 @@ void __queue_cap_release(struct ceph_mds_session *session,
1023 struct ceph_mds_cap_release *head; 1033 struct ceph_mds_cap_release *head;
1024 struct ceph_mds_cap_item *item; 1034 struct ceph_mds_cap_item *item;
1025 1035
1026 spin_lock(&session->s_cap_lock);
1027 BUG_ON(!session->s_num_cap_releases); 1036 BUG_ON(!session->s_num_cap_releases);
1028 msg = list_first_entry(&session->s_cap_releases, 1037 msg = list_first_entry(&session->s_cap_releases,
1029 struct ceph_msg, list_head); 1038 struct ceph_msg, list_head);
@@ -1052,7 +1061,6 @@ void __queue_cap_release(struct ceph_mds_session *session,
1052 (int)CEPH_CAPS_PER_RELEASE, 1061 (int)CEPH_CAPS_PER_RELEASE,
1053 (int)msg->front.iov_len); 1062 (int)msg->front.iov_len);
1054 } 1063 }
1055 spin_unlock(&session->s_cap_lock);
1056} 1064}
1057 1065
1058/* 1066/*
@@ -1067,12 +1075,8 @@ void ceph_queue_caps_release(struct inode *inode)
1067 p = rb_first(&ci->i_caps); 1075 p = rb_first(&ci->i_caps);
1068 while (p) { 1076 while (p) {
1069 struct ceph_cap *cap = rb_entry(p, struct ceph_cap, ci_node); 1077 struct ceph_cap *cap = rb_entry(p, struct ceph_cap, ci_node);
1070 struct ceph_mds_session *session = cap->session;
1071
1072 __queue_cap_release(session, ceph_ino(inode), cap->cap_id,
1073 cap->mseq, cap->issue_seq);
1074 p = rb_next(p); 1078 p = rb_next(p);
1075 __ceph_remove_cap(cap); 1079 __ceph_remove_cap(cap, true);
1076 } 1080 }
1077} 1081}
1078 1082
@@ -2791,7 +2795,7 @@ static void handle_cap_export(struct inode *inode, struct ceph_mds_caps *ex,
2791 } 2795 }
2792 spin_unlock(&mdsc->cap_dirty_lock); 2796 spin_unlock(&mdsc->cap_dirty_lock);
2793 } 2797 }
2794 __ceph_remove_cap(cap); 2798 __ceph_remove_cap(cap, false);
2795 } 2799 }
2796 /* else, we already released it */ 2800 /* else, we already released it */
2797 2801
@@ -2931,9 +2935,12 @@ void ceph_handle_caps(struct ceph_mds_session *session,
2931 if (!inode) { 2935 if (!inode) {
2932 dout(" i don't have ino %llx\n", vino.ino); 2936 dout(" i don't have ino %llx\n", vino.ino);
2933 2937
2934 if (op == CEPH_CAP_OP_IMPORT) 2938 if (op == CEPH_CAP_OP_IMPORT) {
2939 spin_lock(&session->s_cap_lock);
2935 __queue_cap_release(session, vino.ino, cap_id, 2940 __queue_cap_release(session, vino.ino, cap_id,
2936 mseq, seq); 2941 mseq, seq);
2942 spin_unlock(&session->s_cap_lock);
2943 }
2937 goto flush_cap_releases; 2944 goto flush_cap_releases;
2938 } 2945 }
2939 2946
diff --git a/fs/ceph/dir.c b/fs/ceph/dir.c
index 868b61d56cac..2a0bcaeb189a 100644
--- a/fs/ceph/dir.c
+++ b/fs/ceph/dir.c
@@ -352,8 +352,18 @@ more:
352 } 352 }
353 353
354 /* note next offset and last dentry name */ 354 /* note next offset and last dentry name */
355 rinfo = &req->r_reply_info;
356 if (le32_to_cpu(rinfo->dir_dir->frag) != frag) {
357 frag = le32_to_cpu(rinfo->dir_dir->frag);
358 if (ceph_frag_is_leftmost(frag))
359 fi->next_offset = 2;
360 else
361 fi->next_offset = 0;
362 off = fi->next_offset;
363 }
355 fi->offset = fi->next_offset; 364 fi->offset = fi->next_offset;
356 fi->last_readdir = req; 365 fi->last_readdir = req;
366 fi->frag = frag;
357 367
358 if (req->r_reply_info.dir_end) { 368 if (req->r_reply_info.dir_end) {
359 kfree(fi->last_name); 369 kfree(fi->last_name);
@@ -363,7 +373,6 @@ more:
363 else 373 else
364 fi->next_offset = 0; 374 fi->next_offset = 0;
365 } else { 375 } else {
366 rinfo = &req->r_reply_info;
367 err = note_last_dentry(fi, 376 err = note_last_dentry(fi,
368 rinfo->dir_dname[rinfo->dir_nr-1], 377 rinfo->dir_dname[rinfo->dir_nr-1],
369 rinfo->dir_dname_len[rinfo->dir_nr-1]); 378 rinfo->dir_dname_len[rinfo->dir_nr-1]);
diff --git a/fs/ceph/inode.c b/fs/ceph/inode.c
index 8549a48115f7..9a8e396aed89 100644
--- a/fs/ceph/inode.c
+++ b/fs/ceph/inode.c
@@ -577,6 +577,8 @@ static int fill_inode(struct inode *inode,
577 int issued = 0, implemented; 577 int issued = 0, implemented;
578 struct timespec mtime, atime, ctime; 578 struct timespec mtime, atime, ctime;
579 u32 nsplits; 579 u32 nsplits;
580 struct ceph_inode_frag *frag;
581 struct rb_node *rb_node;
580 struct ceph_buffer *xattr_blob = NULL; 582 struct ceph_buffer *xattr_blob = NULL;
581 int err = 0; 583 int err = 0;
582 int queue_trunc = 0; 584 int queue_trunc = 0;
@@ -751,15 +753,38 @@ no_change:
751 /* FIXME: move me up, if/when version reflects fragtree changes */ 753 /* FIXME: move me up, if/when version reflects fragtree changes */
752 nsplits = le32_to_cpu(info->fragtree.nsplits); 754 nsplits = le32_to_cpu(info->fragtree.nsplits);
753 mutex_lock(&ci->i_fragtree_mutex); 755 mutex_lock(&ci->i_fragtree_mutex);
756 rb_node = rb_first(&ci->i_fragtree);
754 for (i = 0; i < nsplits; i++) { 757 for (i = 0; i < nsplits; i++) {
755 u32 id = le32_to_cpu(info->fragtree.splits[i].frag); 758 u32 id = le32_to_cpu(info->fragtree.splits[i].frag);
756 struct ceph_inode_frag *frag = __get_or_create_frag(ci, id); 759 frag = NULL;
757 760 while (rb_node) {
758 if (IS_ERR(frag)) 761 frag = rb_entry(rb_node, struct ceph_inode_frag, node);
759 continue; 762 if (ceph_frag_compare(frag->frag, id) >= 0) {
763 if (frag->frag != id)
764 frag = NULL;
765 else
766 rb_node = rb_next(rb_node);
767 break;
768 }
769 rb_node = rb_next(rb_node);
770 rb_erase(&frag->node, &ci->i_fragtree);
771 kfree(frag);
772 frag = NULL;
773 }
774 if (!frag) {
775 frag = __get_or_create_frag(ci, id);
776 if (IS_ERR(frag))
777 continue;
778 }
760 frag->split_by = le32_to_cpu(info->fragtree.splits[i].by); 779 frag->split_by = le32_to_cpu(info->fragtree.splits[i].by);
761 dout(" frag %x split by %d\n", frag->frag, frag->split_by); 780 dout(" frag %x split by %d\n", frag->frag, frag->split_by);
762 } 781 }
782 while (rb_node) {
783 frag = rb_entry(rb_node, struct ceph_inode_frag, node);
784 rb_node = rb_next(rb_node);
785 rb_erase(&frag->node, &ci->i_fragtree);
786 kfree(frag);
787 }
763 mutex_unlock(&ci->i_fragtree_mutex); 788 mutex_unlock(&ci->i_fragtree_mutex);
764 789
765 /* were we issued a capability? */ 790 /* were we issued a capability? */
@@ -1250,8 +1275,20 @@ int ceph_readdir_prepopulate(struct ceph_mds_request *req,
1250 int err = 0, i; 1275 int err = 0, i;
1251 struct inode *snapdir = NULL; 1276 struct inode *snapdir = NULL;
1252 struct ceph_mds_request_head *rhead = req->r_request->front.iov_base; 1277 struct ceph_mds_request_head *rhead = req->r_request->front.iov_base;
1253 u64 frag = le32_to_cpu(rhead->args.readdir.frag);
1254 struct ceph_dentry_info *di; 1278 struct ceph_dentry_info *di;
1279 u64 r_readdir_offset = req->r_readdir_offset;
1280 u32 frag = le32_to_cpu(rhead->args.readdir.frag);
1281
1282 if (rinfo->dir_dir &&
1283 le32_to_cpu(rinfo->dir_dir->frag) != frag) {
1284 dout("readdir_prepopulate got new frag %x -> %x\n",
1285 frag, le32_to_cpu(rinfo->dir_dir->frag));
1286 frag = le32_to_cpu(rinfo->dir_dir->frag);
1287 if (ceph_frag_is_leftmost(frag))
1288 r_readdir_offset = 2;
1289 else
1290 r_readdir_offset = 0;
1291 }
1255 1292
1256 if (req->r_aborted) 1293 if (req->r_aborted)
1257 return readdir_prepopulate_inodes_only(req, session); 1294 return readdir_prepopulate_inodes_only(req, session);
@@ -1315,7 +1352,7 @@ retry_lookup:
1315 } 1352 }
1316 1353
1317 di = dn->d_fsdata; 1354 di = dn->d_fsdata;
1318 di->offset = ceph_make_fpos(frag, i + req->r_readdir_offset); 1355 di->offset = ceph_make_fpos(frag, i + r_readdir_offset);
1319 1356
1320 /* inode */ 1357 /* inode */
1321 if (dn->d_inode) { 1358 if (dn->d_inode) {
diff --git a/fs/ceph/mds_client.c b/fs/ceph/mds_client.c
index b7bda5d9611d..d90861f45210 100644
--- a/fs/ceph/mds_client.c
+++ b/fs/ceph/mds_client.c
@@ -43,6 +43,7 @@
43 */ 43 */
44 44
45struct ceph_reconnect_state { 45struct ceph_reconnect_state {
46 int nr_caps;
46 struct ceph_pagelist *pagelist; 47 struct ceph_pagelist *pagelist;
47 bool flock; 48 bool flock;
48}; 49};
@@ -443,6 +444,7 @@ static struct ceph_mds_session *register_session(struct ceph_mds_client *mdsc,
443 INIT_LIST_HEAD(&s->s_waiting); 444 INIT_LIST_HEAD(&s->s_waiting);
444 INIT_LIST_HEAD(&s->s_unsafe); 445 INIT_LIST_HEAD(&s->s_unsafe);
445 s->s_num_cap_releases = 0; 446 s->s_num_cap_releases = 0;
447 s->s_cap_reconnect = 0;
446 s->s_cap_iterator = NULL; 448 s->s_cap_iterator = NULL;
447 INIT_LIST_HEAD(&s->s_cap_releases); 449 INIT_LIST_HEAD(&s->s_cap_releases);
448 INIT_LIST_HEAD(&s->s_cap_releases_done); 450 INIT_LIST_HEAD(&s->s_cap_releases_done);
@@ -642,6 +644,8 @@ static void __unregister_request(struct ceph_mds_client *mdsc,
642 req->r_unsafe_dir = NULL; 644 req->r_unsafe_dir = NULL;
643 } 645 }
644 646
647 complete_all(&req->r_safe_completion);
648
645 ceph_mdsc_put_request(req); 649 ceph_mdsc_put_request(req);
646} 650}
647 651
@@ -986,7 +990,7 @@ static int remove_session_caps_cb(struct inode *inode, struct ceph_cap *cap,
986 dout("removing cap %p, ci is %p, inode is %p\n", 990 dout("removing cap %p, ci is %p, inode is %p\n",
987 cap, ci, &ci->vfs_inode); 991 cap, ci, &ci->vfs_inode);
988 spin_lock(&ci->i_ceph_lock); 992 spin_lock(&ci->i_ceph_lock);
989 __ceph_remove_cap(cap); 993 __ceph_remove_cap(cap, false);
990 if (!__ceph_is_any_real_caps(ci)) { 994 if (!__ceph_is_any_real_caps(ci)) {
991 struct ceph_mds_client *mdsc = 995 struct ceph_mds_client *mdsc =
992 ceph_sb_to_client(inode->i_sb)->mdsc; 996 ceph_sb_to_client(inode->i_sb)->mdsc;
@@ -1231,9 +1235,7 @@ static int trim_caps_cb(struct inode *inode, struct ceph_cap *cap, void *arg)
1231 session->s_trim_caps--; 1235 session->s_trim_caps--;
1232 if (oissued) { 1236 if (oissued) {
1233 /* we aren't the only cap.. just remove us */ 1237 /* we aren't the only cap.. just remove us */
1234 __queue_cap_release(session, ceph_ino(inode), cap->cap_id, 1238 __ceph_remove_cap(cap, true);
1235 cap->mseq, cap->issue_seq);
1236 __ceph_remove_cap(cap);
1237 } else { 1239 } else {
1238 /* try to drop referring dentries */ 1240 /* try to drop referring dentries */
1239 spin_unlock(&ci->i_ceph_lock); 1241 spin_unlock(&ci->i_ceph_lock);
@@ -1416,7 +1418,6 @@ static void discard_cap_releases(struct ceph_mds_client *mdsc,
1416 unsigned num; 1418 unsigned num;
1417 1419
1418 dout("discard_cap_releases mds%d\n", session->s_mds); 1420 dout("discard_cap_releases mds%d\n", session->s_mds);
1419 spin_lock(&session->s_cap_lock);
1420 1421
1421 /* zero out the in-progress message */ 1422 /* zero out the in-progress message */
1422 msg = list_first_entry(&session->s_cap_releases, 1423 msg = list_first_entry(&session->s_cap_releases,
@@ -1443,8 +1444,6 @@ static void discard_cap_releases(struct ceph_mds_client *mdsc,
1443 msg->front.iov_len = sizeof(*head); 1444 msg->front.iov_len = sizeof(*head);
1444 list_add(&msg->list_head, &session->s_cap_releases); 1445 list_add(&msg->list_head, &session->s_cap_releases);
1445 } 1446 }
1446
1447 spin_unlock(&session->s_cap_lock);
1448} 1447}
1449 1448
1450/* 1449/*
@@ -1875,8 +1874,11 @@ static int __do_request(struct ceph_mds_client *mdsc,
1875 int mds = -1; 1874 int mds = -1;
1876 int err = -EAGAIN; 1875 int err = -EAGAIN;
1877 1876
1878 if (req->r_err || req->r_got_result) 1877 if (req->r_err || req->r_got_result) {
1878 if (req->r_aborted)
1879 __unregister_request(mdsc, req);
1879 goto out; 1880 goto out;
1881 }
1880 1882
1881 if (req->r_timeout && 1883 if (req->r_timeout &&
1882 time_after_eq(jiffies, req->r_started + req->r_timeout)) { 1884 time_after_eq(jiffies, req->r_started + req->r_timeout)) {
@@ -2186,7 +2188,6 @@ static void handle_reply(struct ceph_mds_session *session, struct ceph_msg *msg)
2186 if (head->safe) { 2188 if (head->safe) {
2187 req->r_got_safe = true; 2189 req->r_got_safe = true;
2188 __unregister_request(mdsc, req); 2190 __unregister_request(mdsc, req);
2189 complete_all(&req->r_safe_completion);
2190 2191
2191 if (req->r_got_unsafe) { 2192 if (req->r_got_unsafe) {
2192 /* 2193 /*
@@ -2238,8 +2239,7 @@ static void handle_reply(struct ceph_mds_session *session, struct ceph_msg *msg)
2238 err = ceph_fill_trace(mdsc->fsc->sb, req, req->r_session); 2239 err = ceph_fill_trace(mdsc->fsc->sb, req, req->r_session);
2239 if (err == 0) { 2240 if (err == 0) {
2240 if (result == 0 && (req->r_op == CEPH_MDS_OP_READDIR || 2241 if (result == 0 && (req->r_op == CEPH_MDS_OP_READDIR ||
2241 req->r_op == CEPH_MDS_OP_LSSNAP) && 2242 req->r_op == CEPH_MDS_OP_LSSNAP))
2242 rinfo->dir_nr)
2243 ceph_readdir_prepopulate(req, req->r_session); 2243 ceph_readdir_prepopulate(req, req->r_session);
2244 ceph_unreserve_caps(mdsc, &req->r_caps_reservation); 2244 ceph_unreserve_caps(mdsc, &req->r_caps_reservation);
2245 } 2245 }
@@ -2490,6 +2490,7 @@ static int encode_caps_cb(struct inode *inode, struct ceph_cap *cap,
2490 cap->seq = 0; /* reset cap seq */ 2490 cap->seq = 0; /* reset cap seq */
2491 cap->issue_seq = 0; /* and issue_seq */ 2491 cap->issue_seq = 0; /* and issue_seq */
2492 cap->mseq = 0; /* and migrate_seq */ 2492 cap->mseq = 0; /* and migrate_seq */
2493 cap->cap_gen = cap->session->s_cap_gen;
2493 2494
2494 if (recon_state->flock) { 2495 if (recon_state->flock) {
2495 rec.v2.cap_id = cpu_to_le64(cap->cap_id); 2496 rec.v2.cap_id = cpu_to_le64(cap->cap_id);
@@ -2552,6 +2553,8 @@ encode_again:
2552 } else { 2553 } else {
2553 err = ceph_pagelist_append(pagelist, &rec, reclen); 2554 err = ceph_pagelist_append(pagelist, &rec, reclen);
2554 } 2555 }
2556
2557 recon_state->nr_caps++;
2555out_free: 2558out_free:
2556 kfree(path); 2559 kfree(path);
2557out_dput: 2560out_dput:
@@ -2579,6 +2582,7 @@ static void send_mds_reconnect(struct ceph_mds_client *mdsc,
2579 struct rb_node *p; 2582 struct rb_node *p;
2580 int mds = session->s_mds; 2583 int mds = session->s_mds;
2581 int err = -ENOMEM; 2584 int err = -ENOMEM;
2585 int s_nr_caps;
2582 struct ceph_pagelist *pagelist; 2586 struct ceph_pagelist *pagelist;
2583 struct ceph_reconnect_state recon_state; 2587 struct ceph_reconnect_state recon_state;
2584 2588
@@ -2610,20 +2614,38 @@ static void send_mds_reconnect(struct ceph_mds_client *mdsc,
2610 dout("session %p state %s\n", session, 2614 dout("session %p state %s\n", session,
2611 session_state_name(session->s_state)); 2615 session_state_name(session->s_state));
2612 2616
2617 spin_lock(&session->s_gen_ttl_lock);
2618 session->s_cap_gen++;
2619 spin_unlock(&session->s_gen_ttl_lock);
2620
2621 spin_lock(&session->s_cap_lock);
2622 /*
2623 * notify __ceph_remove_cap() that we are composing cap reconnect.
2624 * If a cap get released before being added to the cap reconnect,
2625 * __ceph_remove_cap() should skip queuing cap release.
2626 */
2627 session->s_cap_reconnect = 1;
2613 /* drop old cap expires; we're about to reestablish that state */ 2628 /* drop old cap expires; we're about to reestablish that state */
2614 discard_cap_releases(mdsc, session); 2629 discard_cap_releases(mdsc, session);
2630 spin_unlock(&session->s_cap_lock);
2615 2631
2616 /* traverse this session's caps */ 2632 /* traverse this session's caps */
2617 err = ceph_pagelist_encode_32(pagelist, session->s_nr_caps); 2633 s_nr_caps = session->s_nr_caps;
2634 err = ceph_pagelist_encode_32(pagelist, s_nr_caps);
2618 if (err) 2635 if (err)
2619 goto fail; 2636 goto fail;
2620 2637
2638 recon_state.nr_caps = 0;
2621 recon_state.pagelist = pagelist; 2639 recon_state.pagelist = pagelist;
2622 recon_state.flock = session->s_con.peer_features & CEPH_FEATURE_FLOCK; 2640 recon_state.flock = session->s_con.peer_features & CEPH_FEATURE_FLOCK;
2623 err = iterate_session_caps(session, encode_caps_cb, &recon_state); 2641 err = iterate_session_caps(session, encode_caps_cb, &recon_state);
2624 if (err < 0) 2642 if (err < 0)
2625 goto fail; 2643 goto fail;
2626 2644
2645 spin_lock(&session->s_cap_lock);
2646 session->s_cap_reconnect = 0;
2647 spin_unlock(&session->s_cap_lock);
2648
2627 /* 2649 /*
2628 * snaprealms. we provide mds with the ino, seq (version), and 2650 * snaprealms. we provide mds with the ino, seq (version), and
2629 * parent for all of our realms. If the mds has any newer info, 2651 * parent for all of our realms. If the mds has any newer info,
@@ -2646,11 +2668,18 @@ static void send_mds_reconnect(struct ceph_mds_client *mdsc,
2646 2668
2647 if (recon_state.flock) 2669 if (recon_state.flock)
2648 reply->hdr.version = cpu_to_le16(2); 2670 reply->hdr.version = cpu_to_le16(2);
2649 if (pagelist->length) { 2671
2650 /* set up outbound data if we have any */ 2672 /* raced with cap release? */
2651 reply->hdr.data_len = cpu_to_le32(pagelist->length); 2673 if (s_nr_caps != recon_state.nr_caps) {
2652 ceph_msg_data_add_pagelist(reply, pagelist); 2674 struct page *page = list_first_entry(&pagelist->head,
2675 struct page, lru);
2676 __le32 *addr = kmap_atomic(page);
2677 *addr = cpu_to_le32(recon_state.nr_caps);
2678 kunmap_atomic(addr);
2653 } 2679 }
2680
2681 reply->hdr.data_len = cpu_to_le32(pagelist->length);
2682 ceph_msg_data_add_pagelist(reply, pagelist);
2654 ceph_con_send(&session->s_con, reply); 2683 ceph_con_send(&session->s_con, reply);
2655 2684
2656 mutex_unlock(&session->s_mutex); 2685 mutex_unlock(&session->s_mutex);
diff --git a/fs/ceph/mds_client.h b/fs/ceph/mds_client.h
index c2a19fbbe517..4c053d099ae4 100644
--- a/fs/ceph/mds_client.h
+++ b/fs/ceph/mds_client.h
@@ -132,6 +132,7 @@ struct ceph_mds_session {
132 struct list_head s_caps; /* all caps issued by this session */ 132 struct list_head s_caps; /* all caps issued by this session */
133 int s_nr_caps, s_trim_caps; 133 int s_nr_caps, s_trim_caps;
134 int s_num_cap_releases; 134 int s_num_cap_releases;
135 int s_cap_reconnect;
135 struct list_head s_cap_releases; /* waiting cap_release messages */ 136 struct list_head s_cap_releases; /* waiting cap_release messages */
136 struct list_head s_cap_releases_done; /* ready to send */ 137 struct list_head s_cap_releases_done; /* ready to send */
137 struct ceph_cap *s_cap_iterator; 138 struct ceph_cap *s_cap_iterator;
diff --git a/fs/ceph/super.h b/fs/ceph/super.h
index 6014b0a3c405..ef4ac38bb614 100644
--- a/fs/ceph/super.h
+++ b/fs/ceph/super.h
@@ -741,13 +741,7 @@ extern int ceph_add_cap(struct inode *inode,
741 int fmode, unsigned issued, unsigned wanted, 741 int fmode, unsigned issued, unsigned wanted,
742 unsigned cap, unsigned seq, u64 realmino, int flags, 742 unsigned cap, unsigned seq, u64 realmino, int flags,
743 struct ceph_cap_reservation *caps_reservation); 743 struct ceph_cap_reservation *caps_reservation);
744extern void __ceph_remove_cap(struct ceph_cap *cap); 744extern void __ceph_remove_cap(struct ceph_cap *cap, bool queue_release);
745static inline void ceph_remove_cap(struct ceph_cap *cap)
746{
747 spin_lock(&cap->ci->i_ceph_lock);
748 __ceph_remove_cap(cap);
749 spin_unlock(&cap->ci->i_ceph_lock);
750}
751extern void ceph_put_cap(struct ceph_mds_client *mdsc, 745extern void ceph_put_cap(struct ceph_mds_client *mdsc,
752 struct ceph_cap *cap); 746 struct ceph_cap *cap);
753 747
diff --git a/fs/cifs/cifsglob.h b/fs/cifs/cifsglob.h
index d9ea7ada1378..f918a998a087 100644
--- a/fs/cifs/cifsglob.h
+++ b/fs/cifs/cifsglob.h
@@ -384,6 +384,7 @@ struct smb_version_operations {
384 int (*clone_range)(const unsigned int, struct cifsFileInfo *src_file, 384 int (*clone_range)(const unsigned int, struct cifsFileInfo *src_file,
385 struct cifsFileInfo *target_file, u64 src_off, u64 len, 385 struct cifsFileInfo *target_file, u64 src_off, u64 len,
386 u64 dest_off); 386 u64 dest_off);
387 int (*validate_negotiate)(const unsigned int, struct cifs_tcon *);
387}; 388};
388 389
389struct smb_version_values { 390struct smb_version_values {
diff --git a/fs/cifs/ioctl.c b/fs/cifs/ioctl.c
index 409b45eefe70..77492301cc2b 100644
--- a/fs/cifs/ioctl.c
+++ b/fs/cifs/ioctl.c
@@ -26,13 +26,15 @@
26#include <linux/mount.h> 26#include <linux/mount.h>
27#include <linux/mm.h> 27#include <linux/mm.h>
28#include <linux/pagemap.h> 28#include <linux/pagemap.h>
29#include <linux/btrfs.h>
30#include "cifspdu.h" 29#include "cifspdu.h"
31#include "cifsglob.h" 30#include "cifsglob.h"
32#include "cifsproto.h" 31#include "cifsproto.h"
33#include "cifs_debug.h" 32#include "cifs_debug.h"
34#include "cifsfs.h" 33#include "cifsfs.h"
35 34
35#define CIFS_IOCTL_MAGIC 0xCF
36#define CIFS_IOC_COPYCHUNK_FILE _IOW(CIFS_IOCTL_MAGIC, 3, int)
37
36static long cifs_ioctl_clone(unsigned int xid, struct file *dst_file, 38static long cifs_ioctl_clone(unsigned int xid, struct file *dst_file,
37 unsigned long srcfd, u64 off, u64 len, u64 destoff) 39 unsigned long srcfd, u64 off, u64 len, u64 destoff)
38{ 40{
@@ -213,7 +215,7 @@ long cifs_ioctl(struct file *filep, unsigned int command, unsigned long arg)
213 cifs_dbg(FYI, "set compress flag rc %d\n", rc); 215 cifs_dbg(FYI, "set compress flag rc %d\n", rc);
214 } 216 }
215 break; 217 break;
216 case BTRFS_IOC_CLONE: 218 case CIFS_IOC_COPYCHUNK_FILE:
217 rc = cifs_ioctl_clone(xid, filep, arg, 0, 0, 0); 219 rc = cifs_ioctl_clone(xid, filep, arg, 0, 0, 0);
218 break; 220 break;
219 default: 221 default:
diff --git a/fs/cifs/smb2ops.c b/fs/cifs/smb2ops.c
index 11dde4b24f8a..757da3e54d3d 100644
--- a/fs/cifs/smb2ops.c
+++ b/fs/cifs/smb2ops.c
@@ -532,7 +532,10 @@ smb2_clone_range(const unsigned int xid,
532 int rc; 532 int rc;
533 unsigned int ret_data_len; 533 unsigned int ret_data_len;
534 struct copychunk_ioctl *pcchunk; 534 struct copychunk_ioctl *pcchunk;
535 char *retbuf = NULL; 535 struct copychunk_ioctl_rsp *retbuf = NULL;
536 struct cifs_tcon *tcon;
537 int chunks_copied = 0;
538 bool chunk_sizes_updated = false;
536 539
537 pcchunk = kmalloc(sizeof(struct copychunk_ioctl), GFP_KERNEL); 540 pcchunk = kmalloc(sizeof(struct copychunk_ioctl), GFP_KERNEL);
538 541
@@ -547,27 +550,96 @@ smb2_clone_range(const unsigned int xid,
547 550
548 /* Note: request_res_key sets res_key null only if rc !=0 */ 551 /* Note: request_res_key sets res_key null only if rc !=0 */
549 if (rc) 552 if (rc)
550 return rc; 553 goto cchunk_out;
551 554
552 /* For now array only one chunk long, will make more flexible later */ 555 /* For now array only one chunk long, will make more flexible later */
553 pcchunk->ChunkCount = __constant_cpu_to_le32(1); 556 pcchunk->ChunkCount = __constant_cpu_to_le32(1);
554 pcchunk->Reserved = 0; 557 pcchunk->Reserved = 0;
555 pcchunk->SourceOffset = cpu_to_le64(src_off);
556 pcchunk->TargetOffset = cpu_to_le64(dest_off);
557 pcchunk->Length = cpu_to_le32(len);
558 pcchunk->Reserved2 = 0; 558 pcchunk->Reserved2 = 0;
559 559
560 /* Request that server copy to target from src file identified by key */ 560 tcon = tlink_tcon(trgtfile->tlink);
561 rc = SMB2_ioctl(xid, tlink_tcon(trgtfile->tlink),
562 trgtfile->fid.persistent_fid,
563 trgtfile->fid.volatile_fid, FSCTL_SRV_COPYCHUNK_WRITE,
564 true /* is_fsctl */, (char *)pcchunk,
565 sizeof(struct copychunk_ioctl), &retbuf, &ret_data_len);
566 561
567 /* BB need to special case rc = EINVAL to alter chunk size */ 562 while (len > 0) {
563 pcchunk->SourceOffset = cpu_to_le64(src_off);
564 pcchunk->TargetOffset = cpu_to_le64(dest_off);
565 pcchunk->Length =
566 cpu_to_le32(min_t(u32, len, tcon->max_bytes_chunk));
568 567
569 cifs_dbg(FYI, "rc %d data length out %d\n", rc, ret_data_len); 568 /* Request server copy to target from src identified by key */
569 rc = SMB2_ioctl(xid, tcon, trgtfile->fid.persistent_fid,
570 trgtfile->fid.volatile_fid, FSCTL_SRV_COPYCHUNK_WRITE,
571 true /* is_fsctl */, (char *)pcchunk,
572 sizeof(struct copychunk_ioctl), (char **)&retbuf,
573 &ret_data_len);
574 if (rc == 0) {
575 if (ret_data_len !=
576 sizeof(struct copychunk_ioctl_rsp)) {
577 cifs_dbg(VFS, "invalid cchunk response size\n");
578 rc = -EIO;
579 goto cchunk_out;
580 }
581 if (retbuf->TotalBytesWritten == 0) {
582 cifs_dbg(FYI, "no bytes copied\n");
583 rc = -EIO;
584 goto cchunk_out;
585 }
586 /*
587 * Check if server claimed to write more than we asked
588 */
589 if (le32_to_cpu(retbuf->TotalBytesWritten) >
590 le32_to_cpu(pcchunk->Length)) {
591 cifs_dbg(VFS, "invalid copy chunk response\n");
592 rc = -EIO;
593 goto cchunk_out;
594 }
595 if (le32_to_cpu(retbuf->ChunksWritten) != 1) {
596 cifs_dbg(VFS, "invalid num chunks written\n");
597 rc = -EIO;
598 goto cchunk_out;
599 }
600 chunks_copied++;
601
602 src_off += le32_to_cpu(retbuf->TotalBytesWritten);
603 dest_off += le32_to_cpu(retbuf->TotalBytesWritten);
604 len -= le32_to_cpu(retbuf->TotalBytesWritten);
605
606 cifs_dbg(FYI, "Chunks %d PartialChunk %d Total %d\n",
607 le32_to_cpu(retbuf->ChunksWritten),
608 le32_to_cpu(retbuf->ChunkBytesWritten),
609 le32_to_cpu(retbuf->TotalBytesWritten));
610 } else if (rc == -EINVAL) {
611 if (ret_data_len != sizeof(struct copychunk_ioctl_rsp))
612 goto cchunk_out;
613
614 cifs_dbg(FYI, "MaxChunks %d BytesChunk %d MaxCopy %d\n",
615 le32_to_cpu(retbuf->ChunksWritten),
616 le32_to_cpu(retbuf->ChunkBytesWritten),
617 le32_to_cpu(retbuf->TotalBytesWritten));
618
619 /*
620 * Check if this is the first request using these sizes,
621 * (ie check if copy succeed once with original sizes
622 * and check if the server gave us different sizes after
623 * we already updated max sizes on previous request).
624 * if not then why is the server returning an error now
625 */
626 if ((chunks_copied != 0) || chunk_sizes_updated)
627 goto cchunk_out;
628
629 /* Check that server is not asking us to grow size */
630 if (le32_to_cpu(retbuf->ChunkBytesWritten) <
631 tcon->max_bytes_chunk)
632 tcon->max_bytes_chunk =
633 le32_to_cpu(retbuf->ChunkBytesWritten);
634 else
635 goto cchunk_out; /* server gave us bogus size */
636
637 /* No need to change MaxChunks since already set to 1 */
638 chunk_sizes_updated = true;
639 }
640 }
570 641
642cchunk_out:
571 kfree(pcchunk); 643 kfree(pcchunk);
572 return rc; 644 return rc;
573} 645}
@@ -1247,6 +1319,7 @@ struct smb_version_operations smb30_operations = {
1247 .create_lease_buf = smb3_create_lease_buf, 1319 .create_lease_buf = smb3_create_lease_buf,
1248 .parse_lease_buf = smb3_parse_lease_buf, 1320 .parse_lease_buf = smb3_parse_lease_buf,
1249 .clone_range = smb2_clone_range, 1321 .clone_range = smb2_clone_range,
1322 .validate_negotiate = smb3_validate_negotiate,
1250}; 1323};
1251 1324
1252struct smb_version_values smb20_values = { 1325struct smb_version_values smb20_values = {
diff --git a/fs/cifs/smb2pdu.c b/fs/cifs/smb2pdu.c
index d65270c290a1..2013234b73ad 100644
--- a/fs/cifs/smb2pdu.c
+++ b/fs/cifs/smb2pdu.c
@@ -454,6 +454,81 @@ neg_exit:
454 return rc; 454 return rc;
455} 455}
456 456
457int smb3_validate_negotiate(const unsigned int xid, struct cifs_tcon *tcon)
458{
459 int rc = 0;
460 struct validate_negotiate_info_req vneg_inbuf;
461 struct validate_negotiate_info_rsp *pneg_rsp;
462 u32 rsplen;
463
464 cifs_dbg(FYI, "validate negotiate\n");
465
466 /*
467 * validation ioctl must be signed, so no point sending this if we
468 * can not sign it. We could eventually change this to selectively
469 * sign just this, the first and only signed request on a connection.
470 * This is good enough for now since a user who wants better security
471 * would also enable signing on the mount. Having validation of
472 * negotiate info for signed connections helps reduce attack vectors
473 */
474 if (tcon->ses->server->sign == false)
475 return 0; /* validation requires signing */
476
477 vneg_inbuf.Capabilities =
478 cpu_to_le32(tcon->ses->server->vals->req_capabilities);
479 memcpy(vneg_inbuf.Guid, cifs_client_guid, SMB2_CLIENT_GUID_SIZE);
480
481 if (tcon->ses->sign)
482 vneg_inbuf.SecurityMode =
483 cpu_to_le16(SMB2_NEGOTIATE_SIGNING_REQUIRED);
484 else if (global_secflags & CIFSSEC_MAY_SIGN)
485 vneg_inbuf.SecurityMode =
486 cpu_to_le16(SMB2_NEGOTIATE_SIGNING_ENABLED);
487 else
488 vneg_inbuf.SecurityMode = 0;
489
490 vneg_inbuf.DialectCount = cpu_to_le16(1);
491 vneg_inbuf.Dialects[0] =
492 cpu_to_le16(tcon->ses->server->vals->protocol_id);
493
494 rc = SMB2_ioctl(xid, tcon, NO_FILE_ID, NO_FILE_ID,
495 FSCTL_VALIDATE_NEGOTIATE_INFO, true /* is_fsctl */,
496 (char *)&vneg_inbuf, sizeof(struct validate_negotiate_info_req),
497 (char **)&pneg_rsp, &rsplen);
498
499 if (rc != 0) {
500 cifs_dbg(VFS, "validate protocol negotiate failed: %d\n", rc);
501 return -EIO;
502 }
503
504 if (rsplen != sizeof(struct validate_negotiate_info_rsp)) {
505 cifs_dbg(VFS, "invalid size of protocol negotiate response\n");
506 return -EIO;
507 }
508
509 /* check validate negotiate info response matches what we got earlier */
510 if (pneg_rsp->Dialect !=
511 cpu_to_le16(tcon->ses->server->vals->protocol_id))
512 goto vneg_out;
513
514 if (pneg_rsp->SecurityMode != cpu_to_le16(tcon->ses->server->sec_mode))
515 goto vneg_out;
516
517 /* do not validate server guid because not saved at negprot time yet */
518
519 if ((le32_to_cpu(pneg_rsp->Capabilities) | SMB2_NT_FIND |
520 SMB2_LARGE_FILES) != tcon->ses->server->capabilities)
521 goto vneg_out;
522
523 /* validate negotiate successful */
524 cifs_dbg(FYI, "validate negotiate info successful\n");
525 return 0;
526
527vneg_out:
528 cifs_dbg(VFS, "protocol revalidation - security settings mismatch\n");
529 return -EIO;
530}
531
457int 532int
458SMB2_sess_setup(const unsigned int xid, struct cifs_ses *ses, 533SMB2_sess_setup(const unsigned int xid, struct cifs_ses *ses,
459 const struct nls_table *nls_cp) 534 const struct nls_table *nls_cp)
@@ -829,6 +904,8 @@ SMB2_tcon(const unsigned int xid, struct cifs_ses *ses, const char *tree,
829 ((tcon->share_flags & SHI1005_FLAGS_DFS) == 0)) 904 ((tcon->share_flags & SHI1005_FLAGS_DFS) == 0))
830 cifs_dbg(VFS, "DFS capability contradicts DFS flag\n"); 905 cifs_dbg(VFS, "DFS capability contradicts DFS flag\n");
831 init_copy_chunk_defaults(tcon); 906 init_copy_chunk_defaults(tcon);
907 if (tcon->ses->server->ops->validate_negotiate)
908 rc = tcon->ses->server->ops->validate_negotiate(xid, tcon);
832tcon_exit: 909tcon_exit:
833 free_rsp_buf(resp_buftype, rsp); 910 free_rsp_buf(resp_buftype, rsp);
834 kfree(unc_path); 911 kfree(unc_path);
@@ -1214,10 +1291,17 @@ SMB2_ioctl(const unsigned int xid, struct cifs_tcon *tcon, u64 persistent_fid,
1214 rc = SendReceive2(xid, ses, iov, num_iovecs, &resp_buftype, 0); 1291 rc = SendReceive2(xid, ses, iov, num_iovecs, &resp_buftype, 0);
1215 rsp = (struct smb2_ioctl_rsp *)iov[0].iov_base; 1292 rsp = (struct smb2_ioctl_rsp *)iov[0].iov_base;
1216 1293
1217 if (rc != 0) { 1294 if ((rc != 0) && (rc != -EINVAL)) {
1218 if (tcon) 1295 if (tcon)
1219 cifs_stats_fail_inc(tcon, SMB2_IOCTL_HE); 1296 cifs_stats_fail_inc(tcon, SMB2_IOCTL_HE);
1220 goto ioctl_exit; 1297 goto ioctl_exit;
1298 } else if (rc == -EINVAL) {
1299 if ((opcode != FSCTL_SRV_COPYCHUNK_WRITE) &&
1300 (opcode != FSCTL_SRV_COPYCHUNK)) {
1301 if (tcon)
1302 cifs_stats_fail_inc(tcon, SMB2_IOCTL_HE);
1303 goto ioctl_exit;
1304 }
1221 } 1305 }
1222 1306
1223 /* check if caller wants to look at return data or just return rc */ 1307 /* check if caller wants to look at return data or just return rc */
@@ -2154,11 +2238,9 @@ send_set_info(const unsigned int xid, struct cifs_tcon *tcon,
2154 rc = SendReceive2(xid, ses, iov, num, &resp_buftype, 0); 2238 rc = SendReceive2(xid, ses, iov, num, &resp_buftype, 0);
2155 rsp = (struct smb2_set_info_rsp *)iov[0].iov_base; 2239 rsp = (struct smb2_set_info_rsp *)iov[0].iov_base;
2156 2240
2157 if (rc != 0) { 2241 if (rc != 0)
2158 cifs_stats_fail_inc(tcon, SMB2_SET_INFO_HE); 2242 cifs_stats_fail_inc(tcon, SMB2_SET_INFO_HE);
2159 goto out; 2243
2160 }
2161out:
2162 free_rsp_buf(resp_buftype, rsp); 2244 free_rsp_buf(resp_buftype, rsp);
2163 kfree(iov); 2245 kfree(iov);
2164 return rc; 2246 return rc;
diff --git a/fs/cifs/smb2pdu.h b/fs/cifs/smb2pdu.h
index f88320bbb477..2022c542ea3a 100644
--- a/fs/cifs/smb2pdu.h
+++ b/fs/cifs/smb2pdu.h
@@ -577,13 +577,19 @@ struct copychunk_ioctl_rsp {
577 __le32 TotalBytesWritten; 577 __le32 TotalBytesWritten;
578} __packed; 578} __packed;
579 579
580/* Response and Request are the same format */ 580struct validate_negotiate_info_req {
581struct validate_negotiate_info {
582 __le32 Capabilities; 581 __le32 Capabilities;
583 __u8 Guid[SMB2_CLIENT_GUID_SIZE]; 582 __u8 Guid[SMB2_CLIENT_GUID_SIZE];
584 __le16 SecurityMode; 583 __le16 SecurityMode;
585 __le16 DialectCount; 584 __le16 DialectCount;
586 __le16 Dialect[1]; 585 __le16 Dialects[1]; /* dialect (someday maybe list) client asked for */
586} __packed;
587
588struct validate_negotiate_info_rsp {
589 __le32 Capabilities;
590 __u8 Guid[SMB2_CLIENT_GUID_SIZE];
591 __le16 SecurityMode;
592 __le16 Dialect; /* Dialect in use for the connection */
587} __packed; 593} __packed;
588 594
589#define RSS_CAPABLE 0x00000001 595#define RSS_CAPABLE 0x00000001
diff --git a/fs/cifs/smb2proto.h b/fs/cifs/smb2proto.h
index b4eea105b08c..93adc64666f3 100644
--- a/fs/cifs/smb2proto.h
+++ b/fs/cifs/smb2proto.h
@@ -162,5 +162,6 @@ extern int smb2_lockv(const unsigned int xid, struct cifs_tcon *tcon,
162 struct smb2_lock_element *buf); 162 struct smb2_lock_element *buf);
163extern int SMB2_lease_break(const unsigned int xid, struct cifs_tcon *tcon, 163extern int SMB2_lease_break(const unsigned int xid, struct cifs_tcon *tcon,
164 __u8 *lease_key, const __le32 lease_state); 164 __u8 *lease_key, const __le32 lease_state);
165extern int smb3_validate_negotiate(const unsigned int, struct cifs_tcon *);
165 166
166#endif /* _SMB2PROTO_H */ 167#endif /* _SMB2PROTO_H */
diff --git a/fs/cifs/smbfsctl.h b/fs/cifs/smbfsctl.h
index a4b2391fe66e..0e538b5c9622 100644
--- a/fs/cifs/smbfsctl.h
+++ b/fs/cifs/smbfsctl.h
@@ -90,7 +90,7 @@
90#define FSCTL_LMR_REQUEST_RESILIENCY 0x001401D4 /* BB add struct */ 90#define FSCTL_LMR_REQUEST_RESILIENCY 0x001401D4 /* BB add struct */
91#define FSCTL_LMR_GET_LINK_TRACK_INF 0x001400E8 /* BB add struct */ 91#define FSCTL_LMR_GET_LINK_TRACK_INF 0x001400E8 /* BB add struct */
92#define FSCTL_LMR_SET_LINK_TRACK_INF 0x001400EC /* BB add struct */ 92#define FSCTL_LMR_SET_LINK_TRACK_INF 0x001400EC /* BB add struct */
93#define FSCTL_VALIDATE_NEGOTIATE_INFO 0x00140204 /* BB add struct */ 93#define FSCTL_VALIDATE_NEGOTIATE_INFO 0x00140204
94/* Perform server-side data movement */ 94/* Perform server-side data movement */
95#define FSCTL_SRV_COPYCHUNK 0x001440F2 95#define FSCTL_SRV_COPYCHUNK 0x001440F2
96#define FSCTL_SRV_COPYCHUNK_WRITE 0x001480F2 96#define FSCTL_SRV_COPYCHUNK_WRITE 0x001480F2
diff --git a/fs/eventpoll.c b/fs/eventpoll.c
index 79b65c3b9e87..8b5e2584c840 100644
--- a/fs/eventpoll.c
+++ b/fs/eventpoll.c
@@ -1852,8 +1852,7 @@ SYSCALL_DEFINE4(epoll_ctl, int, epfd, int, op, int, fd,
1852 goto error_tgt_fput; 1852 goto error_tgt_fput;
1853 1853
1854 /* Check if EPOLLWAKEUP is allowed */ 1854 /* Check if EPOLLWAKEUP is allowed */
1855 if ((epds.events & EPOLLWAKEUP) && !capable(CAP_BLOCK_SUSPEND)) 1855 ep_take_care_of_epollwakeup(&epds);
1856 epds.events &= ~EPOLLWAKEUP;
1857 1856
1858 /* 1857 /*
1859 * We have to check that the file structure underneath the file descriptor 1858 * We have to check that the file structure underneath the file descriptor
diff --git a/fs/hfsplus/wrapper.c b/fs/hfsplus/wrapper.c
index b51a6079108d..e9a97a0d4314 100644
--- a/fs/hfsplus/wrapper.c
+++ b/fs/hfsplus/wrapper.c
@@ -24,13 +24,6 @@ struct hfsplus_wd {
24 u16 embed_count; 24 u16 embed_count;
25}; 25};
26 26
27static void hfsplus_end_io_sync(struct bio *bio, int err)
28{
29 if (err)
30 clear_bit(BIO_UPTODATE, &bio->bi_flags);
31 complete(bio->bi_private);
32}
33
34/* 27/*
35 * hfsplus_submit_bio - Perfrom block I/O 28 * hfsplus_submit_bio - Perfrom block I/O
36 * @sb: super block of volume for I/O 29 * @sb: super block of volume for I/O
@@ -53,7 +46,6 @@ static void hfsplus_end_io_sync(struct bio *bio, int err)
53int hfsplus_submit_bio(struct super_block *sb, sector_t sector, 46int hfsplus_submit_bio(struct super_block *sb, sector_t sector,
54 void *buf, void **data, int rw) 47 void *buf, void **data, int rw)
55{ 48{
56 DECLARE_COMPLETION_ONSTACK(wait);
57 struct bio *bio; 49 struct bio *bio;
58 int ret = 0; 50 int ret = 0;
59 u64 io_size; 51 u64 io_size;
@@ -73,8 +65,6 @@ int hfsplus_submit_bio(struct super_block *sb, sector_t sector,
73 bio = bio_alloc(GFP_NOIO, 1); 65 bio = bio_alloc(GFP_NOIO, 1);
74 bio->bi_sector = sector; 66 bio->bi_sector = sector;
75 bio->bi_bdev = sb->s_bdev; 67 bio->bi_bdev = sb->s_bdev;
76 bio->bi_end_io = hfsplus_end_io_sync;
77 bio->bi_private = &wait;
78 68
79 if (!(rw & WRITE) && data) 69 if (!(rw & WRITE) && data)
80 *data = (u8 *)buf + offset; 70 *data = (u8 *)buf + offset;
@@ -93,12 +83,7 @@ int hfsplus_submit_bio(struct super_block *sb, sector_t sector,
93 buf = (u8 *)buf + len; 83 buf = (u8 *)buf + len;
94 } 84 }
95 85
96 submit_bio(rw, bio); 86 ret = submit_bio_wait(rw, bio);
97 wait_for_completion(&wait);
98
99 if (!bio_flagged(bio, BIO_UPTODATE))
100 ret = -EIO;
101
102out: 87out:
103 bio_put(bio); 88 bio_put(bio);
104 return ret < 0 ? ret : 0; 89 return ret < 0 ? ret : 0;
diff --git a/fs/logfs/dev_bdev.c b/fs/logfs/dev_bdev.c
index 550475ca6a0e..0f95f0d0b313 100644
--- a/fs/logfs/dev_bdev.c
+++ b/fs/logfs/dev_bdev.c
@@ -14,16 +14,10 @@
14 14
15#define PAGE_OFS(ofs) ((ofs) & (PAGE_SIZE-1)) 15#define PAGE_OFS(ofs) ((ofs) & (PAGE_SIZE-1))
16 16
17static void request_complete(struct bio *bio, int err)
18{
19 complete((struct completion *)bio->bi_private);
20}
21
22static int sync_request(struct page *page, struct block_device *bdev, int rw) 17static int sync_request(struct page *page, struct block_device *bdev, int rw)
23{ 18{
24 struct bio bio; 19 struct bio bio;
25 struct bio_vec bio_vec; 20 struct bio_vec bio_vec;
26 struct completion complete;
27 21
28 bio_init(&bio); 22 bio_init(&bio);
29 bio.bi_max_vecs = 1; 23 bio.bi_max_vecs = 1;
@@ -35,13 +29,8 @@ static int sync_request(struct page *page, struct block_device *bdev, int rw)
35 bio.bi_size = PAGE_SIZE; 29 bio.bi_size = PAGE_SIZE;
36 bio.bi_bdev = bdev; 30 bio.bi_bdev = bdev;
37 bio.bi_sector = page->index * (PAGE_SIZE >> 9); 31 bio.bi_sector = page->index * (PAGE_SIZE >> 9);
38 init_completion(&complete);
39 bio.bi_private = &complete;
40 bio.bi_end_io = request_complete;
41 32
42 submit_bio(rw, &bio); 33 return submit_bio_wait(rw, &bio);
43 wait_for_completion(&complete);
44 return test_bit(BIO_UPTODATE, &bio.bi_flags) ? 0 : -EIO;
45} 34}
46 35
47static int bdev_readpage(void *_sb, struct page *page) 36static int bdev_readpage(void *_sb, struct page *page)
diff --git a/fs/namei.c b/fs/namei.c
index 8f77a8cea289..c53d3a9547f9 100644
--- a/fs/namei.c
+++ b/fs/namei.c
@@ -513,8 +513,7 @@ static int unlazy_walk(struct nameidata *nd, struct dentry *dentry)
513 513
514 if (!lockref_get_not_dead(&parent->d_lockref)) { 514 if (!lockref_get_not_dead(&parent->d_lockref)) {
515 nd->path.dentry = NULL; 515 nd->path.dentry = NULL;
516 rcu_read_unlock(); 516 goto out;
517 return -ECHILD;
518 } 517 }
519 518
520 /* 519 /*
diff --git a/fs/nfs/blocklayout/blocklayout.h b/fs/nfs/blocklayout/blocklayout.h
index 8485978993e8..9838fb020473 100644
--- a/fs/nfs/blocklayout/blocklayout.h
+++ b/fs/nfs/blocklayout/blocklayout.h
@@ -36,6 +36,7 @@
36#include <linux/nfs_fs.h> 36#include <linux/nfs_fs.h>
37#include <linux/sunrpc/rpc_pipe_fs.h> 37#include <linux/sunrpc/rpc_pipe_fs.h>
38 38
39#include "../nfs4_fs.h"
39#include "../pnfs.h" 40#include "../pnfs.h"
40#include "../netns.h" 41#include "../netns.h"
41 42
diff --git a/fs/nfs/blocklayout/extents.c b/fs/nfs/blocklayout/extents.c
index 9c3e117c3ed1..4d0161442565 100644
--- a/fs/nfs/blocklayout/extents.c
+++ b/fs/nfs/blocklayout/extents.c
@@ -44,7 +44,7 @@
44static inline sector_t normalize(sector_t s, int base) 44static inline sector_t normalize(sector_t s, int base)
45{ 45{
46 sector_t tmp = s; /* Since do_div modifies its argument */ 46 sector_t tmp = s; /* Since do_div modifies its argument */
47 return s - do_div(tmp, base); 47 return s - sector_div(tmp, base);
48} 48}
49 49
50static inline sector_t normalize_up(sector_t s, int base) 50static inline sector_t normalize_up(sector_t s, int base)
diff --git a/fs/nfs/dns_resolve.c b/fs/nfs/dns_resolve.c
index fc0f95ec7358..d25f10fb4926 100644
--- a/fs/nfs/dns_resolve.c
+++ b/fs/nfs/dns_resolve.c
@@ -46,7 +46,9 @@ ssize_t nfs_dns_resolve_name(struct net *net, char *name, size_t namelen,
46#include <linux/sunrpc/cache.h> 46#include <linux/sunrpc/cache.h>
47#include <linux/sunrpc/svcauth.h> 47#include <linux/sunrpc/svcauth.h>
48#include <linux/sunrpc/rpc_pipe_fs.h> 48#include <linux/sunrpc/rpc_pipe_fs.h>
49#include <linux/nfs_fs.h>
49 50
51#include "nfs4_fs.h"
50#include "dns_resolve.h" 52#include "dns_resolve.h"
51#include "cache_lib.h" 53#include "cache_lib.h"
52#include "netns.h" 54#include "netns.h"
diff --git a/fs/nfs/inode.c b/fs/nfs/inode.c
index 18ab2da4eeb6..00ad1c2b217d 100644
--- a/fs/nfs/inode.c
+++ b/fs/nfs/inode.c
@@ -312,7 +312,7 @@ struct nfs4_label *nfs4_label_alloc(struct nfs_server *server, gfp_t flags)
312} 312}
313EXPORT_SYMBOL_GPL(nfs4_label_alloc); 313EXPORT_SYMBOL_GPL(nfs4_label_alloc);
314#else 314#else
315void inline nfs_setsecurity(struct inode *inode, struct nfs_fattr *fattr, 315void nfs_setsecurity(struct inode *inode, struct nfs_fattr *fattr,
316 struct nfs4_label *label) 316 struct nfs4_label *label)
317{ 317{
318} 318}
diff --git a/fs/nfs/internal.h b/fs/nfs/internal.h
index bca6a3e3c49c..8b5cc04a8611 100644
--- a/fs/nfs/internal.h
+++ b/fs/nfs/internal.h
@@ -269,6 +269,21 @@ extern const u32 nfs41_maxgetdevinfo_overhead;
269extern struct rpc_procinfo nfs4_procedures[]; 269extern struct rpc_procinfo nfs4_procedures[];
270#endif 270#endif
271 271
272#ifdef CONFIG_NFS_V4_SECURITY_LABEL
273extern struct nfs4_label *nfs4_label_alloc(struct nfs_server *server, gfp_t flags);
274static inline void nfs4_label_free(struct nfs4_label *label)
275{
276 if (label) {
277 kfree(label->label);
278 kfree(label);
279 }
280 return;
281}
282#else
283static inline struct nfs4_label *nfs4_label_alloc(struct nfs_server *server, gfp_t flags) { return NULL; }
284static inline void nfs4_label_free(void *label) {}
285#endif /* CONFIG_NFS_V4_SECURITY_LABEL */
286
272/* proc.c */ 287/* proc.c */
273void nfs_close_context(struct nfs_open_context *ctx, int is_sync); 288void nfs_close_context(struct nfs_open_context *ctx, int is_sync);
274extern struct nfs_client *nfs_init_client(struct nfs_client *clp, 289extern struct nfs_client *nfs_init_client(struct nfs_client *clp,
diff --git a/fs/nfs/nfs4_fs.h b/fs/nfs/nfs4_fs.h
index 3ce79b04522e..5609edc742a0 100644
--- a/fs/nfs/nfs4_fs.h
+++ b/fs/nfs/nfs4_fs.h
@@ -9,6 +9,14 @@
9#ifndef __LINUX_FS_NFS_NFS4_FS_H 9#ifndef __LINUX_FS_NFS_NFS4_FS_H
10#define __LINUX_FS_NFS_NFS4_FS_H 10#define __LINUX_FS_NFS_NFS4_FS_H
11 11
12#if defined(CONFIG_NFS_V4_2)
13#define NFS4_MAX_MINOR_VERSION 2
14#elif defined(CONFIG_NFS_V4_1)
15#define NFS4_MAX_MINOR_VERSION 1
16#else
17#define NFS4_MAX_MINOR_VERSION 0
18#endif
19
12#if IS_ENABLED(CONFIG_NFS_V4) 20#if IS_ENABLED(CONFIG_NFS_V4)
13 21
14#define NFS4_MAX_LOOP_ON_RECOVER (10) 22#define NFS4_MAX_LOOP_ON_RECOVER (10)
diff --git a/fs/nfs/nfs4proc.c b/fs/nfs/nfs4proc.c
index 659990c0109e..15052b81df42 100644
--- a/fs/nfs/nfs4proc.c
+++ b/fs/nfs/nfs4proc.c
@@ -2518,9 +2518,8 @@ static void nfs4_close_done(struct rpc_task *task, void *data)
2518 calldata->roc_barrier); 2518 calldata->roc_barrier);
2519 nfs_set_open_stateid(state, &calldata->res.stateid, 0); 2519 nfs_set_open_stateid(state, &calldata->res.stateid, 0);
2520 renew_lease(server, calldata->timestamp); 2520 renew_lease(server, calldata->timestamp);
2521 nfs4_close_clear_stateid_flags(state,
2522 calldata->arg.fmode);
2523 break; 2521 break;
2522 case -NFS4ERR_ADMIN_REVOKED:
2524 case -NFS4ERR_STALE_STATEID: 2523 case -NFS4ERR_STALE_STATEID:
2525 case -NFS4ERR_OLD_STATEID: 2524 case -NFS4ERR_OLD_STATEID:
2526 case -NFS4ERR_BAD_STATEID: 2525 case -NFS4ERR_BAD_STATEID:
@@ -2528,9 +2527,13 @@ static void nfs4_close_done(struct rpc_task *task, void *data)
2528 if (calldata->arg.fmode == 0) 2527 if (calldata->arg.fmode == 0)
2529 break; 2528 break;
2530 default: 2529 default:
2531 if (nfs4_async_handle_error(task, server, state) == -EAGAIN) 2530 if (nfs4_async_handle_error(task, server, state) == -EAGAIN) {
2532 rpc_restart_call_prepare(task); 2531 rpc_restart_call_prepare(task);
2532 goto out_release;
2533 }
2533 } 2534 }
2535 nfs4_close_clear_stateid_flags(state, calldata->arg.fmode);
2536out_release:
2534 nfs_release_seqid(calldata->arg.seqid); 2537 nfs_release_seqid(calldata->arg.seqid);
2535 nfs_refresh_inode(calldata->inode, calldata->res.fattr); 2538 nfs_refresh_inode(calldata->inode, calldata->res.fattr);
2536 dprintk("%s: done, ret = %d!\n", __func__, task->tk_status); 2539 dprintk("%s: done, ret = %d!\n", __func__, task->tk_status);
@@ -4802,7 +4805,7 @@ nfs4_async_handle_error(struct rpc_task *task, const struct nfs_server *server,
4802 dprintk("%s ERROR %d, Reset session\n", __func__, 4805 dprintk("%s ERROR %d, Reset session\n", __func__,
4803 task->tk_status); 4806 task->tk_status);
4804 nfs4_schedule_session_recovery(clp->cl_session, task->tk_status); 4807 nfs4_schedule_session_recovery(clp->cl_session, task->tk_status);
4805 goto restart_call; 4808 goto wait_on_recovery;
4806#endif /* CONFIG_NFS_V4_1 */ 4809#endif /* CONFIG_NFS_V4_1 */
4807 case -NFS4ERR_DELAY: 4810 case -NFS4ERR_DELAY:
4808 nfs_inc_server_stats(server, NFSIOS_DELAY); 4811 nfs_inc_server_stats(server, NFSIOS_DELAY);
@@ -4987,11 +4990,17 @@ static void nfs4_delegreturn_done(struct rpc_task *task, void *calldata)
4987 4990
4988 trace_nfs4_delegreturn_exit(&data->args, &data->res, task->tk_status); 4991 trace_nfs4_delegreturn_exit(&data->args, &data->res, task->tk_status);
4989 switch (task->tk_status) { 4992 switch (task->tk_status) {
4990 case -NFS4ERR_STALE_STATEID:
4991 case -NFS4ERR_EXPIRED:
4992 case 0: 4993 case 0:
4993 renew_lease(data->res.server, data->timestamp); 4994 renew_lease(data->res.server, data->timestamp);
4994 break; 4995 break;
4996 case -NFS4ERR_ADMIN_REVOKED:
4997 case -NFS4ERR_DELEG_REVOKED:
4998 case -NFS4ERR_BAD_STATEID:
4999 case -NFS4ERR_OLD_STATEID:
5000 case -NFS4ERR_STALE_STATEID:
5001 case -NFS4ERR_EXPIRED:
5002 task->tk_status = 0;
5003 break;
4995 default: 5004 default:
4996 if (nfs4_async_handle_error(task, data->res.server, NULL) == 5005 if (nfs4_async_handle_error(task, data->res.server, NULL) ==
4997 -EAGAIN) { 5006 -EAGAIN) {
@@ -7589,7 +7598,14 @@ static void nfs4_layoutreturn_done(struct rpc_task *task, void *calldata)
7589 return; 7598 return;
7590 7599
7591 server = NFS_SERVER(lrp->args.inode); 7600 server = NFS_SERVER(lrp->args.inode);
7592 if (nfs4_async_handle_error(task, server, NULL) == -EAGAIN) { 7601 switch (task->tk_status) {
7602 default:
7603 task->tk_status = 0;
7604 case 0:
7605 break;
7606 case -NFS4ERR_DELAY:
7607 if (nfs4_async_handle_error(task, server, NULL) != -EAGAIN)
7608 break;
7593 rpc_restart_call_prepare(task); 7609 rpc_restart_call_prepare(task);
7594 return; 7610 return;
7595 } 7611 }
diff --git a/fs/pipe.c b/fs/pipe.c
index d2c45e14e6d8..0e0752ef2715 100644
--- a/fs/pipe.c
+++ b/fs/pipe.c
@@ -726,11 +726,25 @@ pipe_poll(struct file *filp, poll_table *wait)
726 return mask; 726 return mask;
727} 727}
728 728
729static void put_pipe_info(struct inode *inode, struct pipe_inode_info *pipe)
730{
731 int kill = 0;
732
733 spin_lock(&inode->i_lock);
734 if (!--pipe->files) {
735 inode->i_pipe = NULL;
736 kill = 1;
737 }
738 spin_unlock(&inode->i_lock);
739
740 if (kill)
741 free_pipe_info(pipe);
742}
743
729static int 744static int
730pipe_release(struct inode *inode, struct file *file) 745pipe_release(struct inode *inode, struct file *file)
731{ 746{
732 struct pipe_inode_info *pipe = inode->i_pipe; 747 struct pipe_inode_info *pipe = file->private_data;
733 int kill = 0;
734 748
735 __pipe_lock(pipe); 749 __pipe_lock(pipe);
736 if (file->f_mode & FMODE_READ) 750 if (file->f_mode & FMODE_READ)
@@ -743,17 +757,9 @@ pipe_release(struct inode *inode, struct file *file)
743 kill_fasync(&pipe->fasync_readers, SIGIO, POLL_IN); 757 kill_fasync(&pipe->fasync_readers, SIGIO, POLL_IN);
744 kill_fasync(&pipe->fasync_writers, SIGIO, POLL_OUT); 758 kill_fasync(&pipe->fasync_writers, SIGIO, POLL_OUT);
745 } 759 }
746 spin_lock(&inode->i_lock);
747 if (!--pipe->files) {
748 inode->i_pipe = NULL;
749 kill = 1;
750 }
751 spin_unlock(&inode->i_lock);
752 __pipe_unlock(pipe); 760 __pipe_unlock(pipe);
753 761
754 if (kill) 762 put_pipe_info(inode, pipe);
755 free_pipe_info(pipe);
756
757 return 0; 763 return 0;
758} 764}
759 765
@@ -1014,7 +1020,6 @@ static int fifo_open(struct inode *inode, struct file *filp)
1014{ 1020{
1015 struct pipe_inode_info *pipe; 1021 struct pipe_inode_info *pipe;
1016 bool is_pipe = inode->i_sb->s_magic == PIPEFS_MAGIC; 1022 bool is_pipe = inode->i_sb->s_magic == PIPEFS_MAGIC;
1017 int kill = 0;
1018 int ret; 1023 int ret;
1019 1024
1020 filp->f_version = 0; 1025 filp->f_version = 0;
@@ -1130,15 +1135,9 @@ err_wr:
1130 goto err; 1135 goto err;
1131 1136
1132err: 1137err:
1133 spin_lock(&inode->i_lock);
1134 if (!--pipe->files) {
1135 inode->i_pipe = NULL;
1136 kill = 1;
1137 }
1138 spin_unlock(&inode->i_lock);
1139 __pipe_unlock(pipe); 1138 __pipe_unlock(pipe);
1140 if (kill) 1139
1141 free_pipe_info(pipe); 1140 put_pipe_info(inode, pipe);
1142 return ret; 1141 return ret;
1143} 1142}
1144 1143
diff --git a/fs/squashfs/file_direct.c b/fs/squashfs/file_direct.c
index 2943b2bfae48..62a0de6632e1 100644
--- a/fs/squashfs/file_direct.c
+++ b/fs/squashfs/file_direct.c
@@ -84,6 +84,9 @@ int squashfs_readpage_block(struct page *target_page, u64 block, int bsize)
84 */ 84 */
85 res = squashfs_read_cache(target_page, block, bsize, pages, 85 res = squashfs_read_cache(target_page, block, bsize, pages,
86 page); 86 page);
87 if (res < 0)
88 goto mark_errored;
89
87 goto out; 90 goto out;
88 } 91 }
89 92
@@ -119,7 +122,7 @@ mark_errored:
119 * dealt with by the caller 122 * dealt with by the caller
120 */ 123 */
121 for (i = 0; i < pages; i++) { 124 for (i = 0; i < pages; i++) {
122 if (page[i] == target_page) 125 if (page[i] == NULL || page[i] == target_page)
123 continue; 126 continue;
124 flush_dcache_page(page[i]); 127 flush_dcache_page(page[i]);
125 SetPageError(page[i]); 128 SetPageError(page[i]);
diff --git a/fs/sysfs/file.c b/fs/sysfs/file.c
index 79b5da2acbe1..b94f93685093 100644
--- a/fs/sysfs/file.c
+++ b/fs/sysfs/file.c
@@ -609,7 +609,7 @@ static int sysfs_open_file(struct inode *inode, struct file *file)
609 struct sysfs_dirent *attr_sd = file->f_path.dentry->d_fsdata; 609 struct sysfs_dirent *attr_sd = file->f_path.dentry->d_fsdata;
610 struct kobject *kobj = attr_sd->s_parent->s_dir.kobj; 610 struct kobject *kobj = attr_sd->s_parent->s_dir.kobj;
611 struct sysfs_open_file *of; 611 struct sysfs_open_file *of;
612 bool has_read, has_write; 612 bool has_read, has_write, has_mmap;
613 int error = -EACCES; 613 int error = -EACCES;
614 614
615 /* need attr_sd for attr and ops, its parent for kobj */ 615 /* need attr_sd for attr and ops, its parent for kobj */
@@ -621,6 +621,7 @@ static int sysfs_open_file(struct inode *inode, struct file *file)
621 621
622 has_read = battr->read || battr->mmap; 622 has_read = battr->read || battr->mmap;
623 has_write = battr->write || battr->mmap; 623 has_write = battr->write || battr->mmap;
624 has_mmap = battr->mmap;
624 } else { 625 } else {
625 const struct sysfs_ops *ops = sysfs_file_ops(attr_sd); 626 const struct sysfs_ops *ops = sysfs_file_ops(attr_sd);
626 627
@@ -632,6 +633,7 @@ static int sysfs_open_file(struct inode *inode, struct file *file)
632 633
633 has_read = ops->show; 634 has_read = ops->show;
634 has_write = ops->store; 635 has_write = ops->store;
636 has_mmap = false;
635 } 637 }
636 638
637 /* check perms and supported operations */ 639 /* check perms and supported operations */
@@ -649,7 +651,23 @@ static int sysfs_open_file(struct inode *inode, struct file *file)
649 if (!of) 651 if (!of)
650 goto err_out; 652 goto err_out;
651 653
652 mutex_init(&of->mutex); 654 /*
655 * The following is done to give a different lockdep key to
656 * @of->mutex for files which implement mmap. This is a rather
657 * crude way to avoid false positive lockdep warning around
658 * mm->mmap_sem - mmap nests @of->mutex under mm->mmap_sem and
659 * reading /sys/block/sda/trace/act_mask grabs sr_mutex, under
660 * which mm->mmap_sem nests, while holding @of->mutex. As each
661 * open file has a separate mutex, it's okay as long as those don't
662 * happen on the same file. At this point, we can't easily give
663 * each file a separate locking class. Let's differentiate on
664 * whether the file has mmap or not for now.
665 */
666 if (has_mmap)
667 mutex_init(&of->mutex);
668 else
669 mutex_init(&of->mutex);
670
653 of->sd = attr_sd; 671 of->sd = attr_sd;
654 of->file = file; 672 of->file = file;
655 673
diff --git a/include/acpi/acconfig.h b/include/acpi/acconfig.h
index d98c67001840..3ea214cff349 100644
--- a/include/acpi/acconfig.h
+++ b/include/acpi/acconfig.h
@@ -83,7 +83,9 @@
83 * Should the subsystem abort the loading of an ACPI table if the 83 * Should the subsystem abort the loading of an ACPI table if the
84 * table checksum is incorrect? 84 * table checksum is incorrect?
85 */ 85 */
86#ifndef ACPI_CHECKSUM_ABORT
86#define ACPI_CHECKSUM_ABORT FALSE 87#define ACPI_CHECKSUM_ABORT FALSE
88#endif
87 89
88/* 90/*
89 * Generate a version of ACPICA that only supports "reduced hardware" 91 * Generate a version of ACPICA that only supports "reduced hardware"
diff --git a/include/acpi/acpi_bus.h b/include/acpi/acpi_bus.h
index 7b2de026a4f3..c602c7718421 100644
--- a/include/acpi/acpi_bus.h
+++ b/include/acpi/acpi_bus.h
@@ -100,6 +100,7 @@ enum acpi_hotplug_mode {
100struct acpi_hotplug_profile { 100struct acpi_hotplug_profile {
101 struct kobject kobj; 101 struct kobject kobj;
102 bool enabled:1; 102 bool enabled:1;
103 bool ignore:1;
103 enum acpi_hotplug_mode mode; 104 enum acpi_hotplug_mode mode;
104}; 105};
105 106
diff --git a/include/acpi/acpixf.h b/include/acpi/acpixf.h
index d8f9457755b4..4278aba96503 100644
--- a/include/acpi/acpixf.h
+++ b/include/acpi/acpixf.h
@@ -46,7 +46,7 @@
46 46
47/* Current ACPICA subsystem version in YYYYMMDD format */ 47/* Current ACPICA subsystem version in YYYYMMDD format */
48 48
49#define ACPI_CA_VERSION 0x20130927 49#define ACPI_CA_VERSION 0x20131115
50 50
51#include <acpi/acconfig.h> 51#include <acpi/acconfig.h>
52#include <acpi/actypes.h> 52#include <acpi/actypes.h>
diff --git a/include/asm-generic/simd.h b/include/asm-generic/simd.h
new file mode 100644
index 000000000000..f57eb7b5c23b
--- /dev/null
+++ b/include/asm-generic/simd.h
@@ -0,0 +1,14 @@
1
2#include <linux/hardirq.h>
3
4/*
5 * may_use_simd - whether it is allowable at this time to issue SIMD
6 * instructions or access the SIMD register file
7 *
8 * As architectures typically don't preserve the SIMD register file when
9 * taking an interrupt, !in_interrupt() should be a reasonable default.
10 */
11static __must_check inline bool may_use_simd(void)
12{
13 return !in_interrupt();
14}
diff --git a/arch/x86/include/asm/crypto/ablk_helper.h b/include/crypto/ablk_helper.h
index 4f93df50c23e..4f93df50c23e 100644
--- a/arch/x86/include/asm/crypto/ablk_helper.h
+++ b/include/crypto/ablk_helper.h
diff --git a/include/crypto/algapi.h b/include/crypto/algapi.h
index 418d270e1806..e73c19e90e38 100644
--- a/include/crypto/algapi.h
+++ b/include/crypto/algapi.h
@@ -386,5 +386,21 @@ static inline int crypto_requires_sync(u32 type, u32 mask)
386 return (type ^ CRYPTO_ALG_ASYNC) & mask & CRYPTO_ALG_ASYNC; 386 return (type ^ CRYPTO_ALG_ASYNC) & mask & CRYPTO_ALG_ASYNC;
387} 387}
388 388
389#endif /* _CRYPTO_ALGAPI_H */ 389noinline unsigned long __crypto_memneq(const void *a, const void *b, size_t size);
390
391/**
392 * crypto_memneq - Compare two areas of memory without leaking
393 * timing information.
394 *
395 * @a: One area of memory
396 * @b: Another area of memory
397 * @size: The size of the area.
398 *
399 * Returns 0 when data is equal, 1 otherwise.
400 */
401static inline int crypto_memneq(const void *a, const void *b, size_t size)
402{
403 return __crypto_memneq(a, b, size) != 0UL ? 1 : 0;
404}
390 405
406#endif /* _CRYPTO_ALGAPI_H */
diff --git a/include/crypto/authenc.h b/include/crypto/authenc.h
index e47b044929a8..6775059539b5 100644
--- a/include/crypto/authenc.h
+++ b/include/crypto/authenc.h
@@ -23,5 +23,15 @@ struct crypto_authenc_key_param {
23 __be32 enckeylen; 23 __be32 enckeylen;
24}; 24};
25 25
26#endif /* _CRYPTO_AUTHENC_H */ 26struct crypto_authenc_keys {
27 const u8 *authkey;
28 const u8 *enckey;
29
30 unsigned int authkeylen;
31 unsigned int enckeylen;
32};
27 33
34int crypto_authenc_extractkeys(struct crypto_authenc_keys *keys, const u8 *key,
35 unsigned int keylen);
36
37#endif /* _CRYPTO_AUTHENC_H */
diff --git a/include/crypto/scatterwalk.h b/include/crypto/scatterwalk.h
index 13621cc8cf4c..64ebede184f1 100644
--- a/include/crypto/scatterwalk.h
+++ b/include/crypto/scatterwalk.h
@@ -36,6 +36,7 @@ static inline void scatterwalk_sg_chain(struct scatterlist *sg1, int num,
36{ 36{
37 sg_set_page(&sg1[num - 1], (void *)sg2, 0, 0); 37 sg_set_page(&sg1[num - 1], (void *)sg2, 0, 0);
38 sg1[num - 1].page_link &= ~0x02; 38 sg1[num - 1].page_link &= ~0x02;
39 sg1[num - 1].page_link |= 0x01;
39} 40}
40 41
41static inline struct scatterlist *scatterwalk_sg_next(struct scatterlist *sg) 42static inline struct scatterlist *scatterwalk_sg_next(struct scatterlist *sg)
diff --git a/include/dt-bindings/clk/at91.h b/include/dt-bindings/clk/at91.h
new file mode 100644
index 000000000000..0b4cb999a3f7
--- /dev/null
+++ b/include/dt-bindings/clk/at91.h
@@ -0,0 +1,22 @@
1/*
2 * This header provides constants for AT91 pmc status.
3 *
4 * The constants defined in this header are being used in dts.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#ifndef _DT_BINDINGS_CLK_AT91_H
10#define _DT_BINDINGS_CLK_AT91_H
11
12#define AT91_PMC_MOSCS 0 /* MOSCS Flag */
13#define AT91_PMC_LOCKA 1 /* PLLA Lock */
14#define AT91_PMC_LOCKB 2 /* PLLB Lock */
15#define AT91_PMC_MCKRDY 3 /* Master Clock */
16#define AT91_PMC_LOCKU 6 /* UPLL Lock */
17#define AT91_PMC_PCKRDY(id) (8 + (id)) /* Programmable Clock */
18#define AT91_PMC_MOSCSELS 16 /* Main Oscillator Selection */
19#define AT91_PMC_MOSCRCS 17 /* Main On-Chip RC */
20#define AT91_PMC_CFDEV 18 /* Clock Failure Detector Event */
21
22#endif
diff --git a/include/dt-bindings/clock/tegra114-car.h b/include/dt-bindings/clock/tegra114-car.h
index 614aec417902..6d0d8d8ef31e 100644
--- a/include/dt-bindings/clock/tegra114-car.h
+++ b/include/dt-bindings/clock/tegra114-car.h
@@ -37,10 +37,10 @@
37#define TEGRA114_CLK_I2S2 18 37#define TEGRA114_CLK_I2S2 18
38#define TEGRA114_CLK_EPP 19 38#define TEGRA114_CLK_EPP 19
39/* 20 (register bit affects vi and vi_sensor) */ 39/* 20 (register bit affects vi and vi_sensor) */
40#define TEGRA114_CLK_GR_2D 21 40#define TEGRA114_CLK_GR2D 21
41#define TEGRA114_CLK_USBD 22 41#define TEGRA114_CLK_USBD 22
42#define TEGRA114_CLK_ISP 23 42#define TEGRA114_CLK_ISP 23
43#define TEGRA114_CLK_GR_3D 24 43#define TEGRA114_CLK_GR3D 24
44/* 25 */ 44/* 25 */
45#define TEGRA114_CLK_DISP2 26 45#define TEGRA114_CLK_DISP2 26
46#define TEGRA114_CLK_DISP1 27 46#define TEGRA114_CLK_DISP1 27
@@ -289,8 +289,8 @@
289#define TEGRA114_CLK_PCLK 261 289#define TEGRA114_CLK_PCLK 261
290#define TEGRA114_CLK_CCLK_G 262 290#define TEGRA114_CLK_CCLK_G 262
291#define TEGRA114_CLK_CCLK_LP 263 291#define TEGRA114_CLK_CCLK_LP 263
292/* 264 */ 292#define TEGRA114_CLK_DFLL_REF 264
293/* 265 */ 293#define TEGRA114_CLK_DFLL_SOC 265
294/* 266 */ 294/* 266 */
295/* 267 */ 295/* 267 */
296/* 268 */ 296/* 268 */
diff --git a/include/dt-bindings/clock/tegra124-car.h b/include/dt-bindings/clock/tegra124-car.h
new file mode 100644
index 000000000000..a1116a3b54ef
--- /dev/null
+++ b/include/dt-bindings/clock/tegra124-car.h
@@ -0,0 +1,341 @@
1/*
2 * This header provides constants for binding nvidia,tegra124-car.
3 *
4 * The first 192 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
5 * registers. These IDs often match those in the CAR's RST_DEVICES registers,
6 * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
7 * this case, those clocks are assigned IDs above 185 in order to highlight
8 * this issue. Implementations that interpret these clock IDs as bit values
9 * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
10 * explicitly handle these special cases.
11 *
12 * The balance of the clocks controlled by the CAR are assigned IDs of 185 and
13 * above.
14 */
15
16#ifndef _DT_BINDINGS_CLOCK_TEGRA124_CAR_H
17#define _DT_BINDINGS_CLOCK_TEGRA124_CAR_H
18
19/* 0 */
20/* 1 */
21/* 2 */
22#define TEGRA124_CLK_ISPB 3
23#define TEGRA124_CLK_RTC 4
24#define TEGRA124_CLK_TIMER 5
25#define TEGRA124_CLK_UARTA 6
26/* 7 (register bit affects uartb and vfir) */
27/* 8 */
28#define TEGRA124_CLK_SDMMC2 9
29/* 10 (register bit affects spdif_in and spdif_out) */
30#define TEGRA124_CLK_I2S1 11
31#define TEGRA124_CLK_I2C1 12
32#define TEGRA124_CLK_NDFLASH 13
33#define TEGRA124_CLK_SDMMC1 14
34#define TEGRA124_CLK_SDMMC4 15
35/* 16 */
36#define TEGRA124_CLK_PWM 17
37#define TEGRA124_CLK_I2S2 18
38/* 20 (register bit affects vi and vi_sensor) */
39#define TEGRA124_CLK_GR_2D 21
40#define TEGRA124_CLK_USBD 22
41#define TEGRA124_CLK_ISP 23
42#define TEGRA124_CLK_GR_3D 24
43/* 25 */
44#define TEGRA124_CLK_DISP2 26
45#define TEGRA124_CLK_DISP1 27
46#define TEGRA124_CLK_HOST1X 28
47#define TEGRA124_CLK_VCP 29
48#define TEGRA124_CLK_I2S0 30
49/* 31 */
50
51/* 32 */
52/* 33 */
53#define TEGRA124_CLK_APBDMA 34
54/* 35 */
55#define TEGRA124_CLK_KBC 36
56/* 37 */
57/* 38 */
58/* 39 (register bit affects fuse and fuse_burn) */
59#define TEGRA124_CLK_KFUSE 40
60#define TEGRA124_CLK_SBC1 41
61#define TEGRA124_CLK_NOR 42
62/* 43 */
63#define TEGRA124_CLK_SBC2 44
64/* 45 */
65#define TEGRA124_CLK_SBC3 46
66#define TEGRA124_CLK_I2C5 47
67#define TEGRA124_CLK_DSIA 48
68/* 49 */
69#define TEGRA124_CLK_MIPI 50
70#define TEGRA124_CLK_HDMI 51
71#define TEGRA124_CLK_CSI 52
72/* 53 */
73#define TEGRA124_CLK_I2C2 54
74#define TEGRA124_CLK_UARTC 55
75#define TEGRA124_CLK_MIPI_CAL 56
76#define TEGRA124_CLK_EMC 57
77#define TEGRA124_CLK_USB2 58
78#define TEGRA124_CLK_USB3 59
79/* 60 */
80#define TEGRA124_CLK_VDE 61
81#define TEGRA124_CLK_BSEA 62
82#define TEGRA124_CLK_BSEV 63
83
84/* 64 */
85#define TEGRA124_CLK_UARTD 65
86#define TEGRA124_CLK_UARTE 66
87#define TEGRA124_CLK_I2C3 67
88#define TEGRA124_CLK_SBC4 68
89#define TEGRA124_CLK_SDMMC3 69
90#define TEGRA124_CLK_PCIE 70
91#define TEGRA124_CLK_OWR 71
92#define TEGRA124_CLK_AFI 72
93#define TEGRA124_CLK_CSITE 73
94/* 74 */
95/* 75 */
96#define TEGRA124_CLK_LA 76
97#define TEGRA124_CLK_TRACE 77
98#define TEGRA124_CLK_SOC_THERM 78
99#define TEGRA124_CLK_DTV 79
100#define TEGRA124_CLK_NDSPEED 80
101#define TEGRA124_CLK_I2CSLOW 81
102#define TEGRA124_CLK_DSIB 82
103#define TEGRA124_CLK_TSEC 83
104/* 84 */
105/* 85 */
106/* 86 */
107/* 87 */
108/* 88 */
109#define TEGRA124_CLK_XUSB_HOST 89
110/* 90 */
111#define TEGRA124_CLK_MSENC 91
112#define TEGRA124_CLK_CSUS 92
113/* 93 */
114/* 94 */
115/* 95 (bit affects xusb_dev and xusb_dev_src) */
116
117/* 96 */
118/* 97 */
119/* 98 */
120#define TEGRA124_CLK_MSELECT 99
121#define TEGRA124_CLK_TSENSOR 100
122#define TEGRA124_CLK_I2S3 101
123#define TEGRA124_CLK_I2S4 102
124#define TEGRA124_CLK_I2C4 103
125#define TEGRA124_CLK_SBC5 104
126#define TEGRA124_CLK_SBC6 105
127#define TEGRA124_CLK_D_AUDIO 106
128#define TEGRA124_CLK_APBIF 107
129#define TEGRA124_CLK_DAM0 108
130#define TEGRA124_CLK_DAM1 109
131#define TEGRA124_CLK_DAM2 110
132#define TEGRA124_CLK_HDA2CODEC_2X 111
133/* 112 */
134#define TEGRA124_CLK_AUDIO0_2X 113
135#define TEGRA124_CLK_AUDIO1_2X 114
136#define TEGRA124_CLK_AUDIO2_2X 115
137#define TEGRA124_CLK_AUDIO3_2X 116
138#define TEGRA124_CLK_AUDIO4_2X 117
139#define TEGRA124_CLK_SPDIF_2X 118
140#define TEGRA124_CLK_ACTMON 119
141#define TEGRA124_CLK_EXTERN1 120
142#define TEGRA124_CLK_EXTERN2 121
143#define TEGRA124_CLK_EXTERN3 122
144#define TEGRA124_CLK_SATA_OOB 123
145#define TEGRA124_CLK_SATA 124
146#define TEGRA124_CLK_HDA 125
147/* 126 */
148#define TEGRA124_CLK_SE 127
149
150#define TEGRA124_CLK_HDA2HDMI 128
151#define TEGRA124_CLK_SATA_COLD 129
152/* 130 */
153/* 131 */
154/* 132 */
155/* 133 */
156/* 134 */
157/* 135 */
158/* 136 */
159/* 137 */
160/* 138 */
161/* 139 */
162/* 140 */
163/* 141 */
164/* 142 */
165/* 143 (bit affects xusb_falcon_src, xusb_fs_src, */
166/* xusb_host_src and xusb_ss_src) */
167#define TEGRA124_CLK_CILAB 144
168#define TEGRA124_CLK_CILCD 145
169#define TEGRA124_CLK_CILE 146
170#define TEGRA124_CLK_DSIALP 147
171#define TEGRA124_CLK_DSIBLP 148
172#define TEGRA124_CLK_ENTROPY 149
173#define TEGRA124_CLK_DDS 150
174/* 151 */
175#define TEGRA124_CLK_DP2 152
176#define TEGRA124_CLK_AMX 153
177#define TEGRA124_CLK_ADX 154
178/* 155 (bit affects dfll_ref and dfll_soc) */
179#define TEGRA124_CLK_XUSB_SS 156
180/* 157 */
181/* 158 */
182/* 159 */
183
184/* 160 */
185/* 161 */
186/* 162 */
187/* 163 */
188/* 164 */
189/* 165 */
190#define TEGRA124_CLK_I2C6 166
191/* 167 */
192/* 168 */
193/* 169 */
194/* 170 */
195#define TEGRA124_CLK_VIM2_CLK 171
196/* 172 */
197/* 173 */
198/* 174 */
199/* 175 */
200#define TEGRA124_CLK_HDMI_AUDIO 176
201#define TEGRA124_CLK_CLK72MHZ 177
202#define TEGRA124_CLK_VIC03 178
203/* 179 */
204#define TEGRA124_CLK_ADX1 180
205#define TEGRA124_CLK_DPAUX 181
206#define TEGRA124_CLK_SOR0 182
207/* 183 */
208#define TEGRA124_CLK_GPU 184
209#define TEGRA124_CLK_AMX1 185
210/* 186 */
211/* 187 */
212/* 188 */
213/* 189 */
214/* 190 */
215/* 191 */
216#define TEGRA124_CLK_UARTB 192
217#define TEGRA124_CLK_VFIR 193
218#define TEGRA124_CLK_SPDIF_IN 194
219#define TEGRA124_CLK_SPDIF_OUT 195
220#define TEGRA124_CLK_VI 196
221#define TEGRA124_CLK_VI_SENSOR 197
222#define TEGRA124_CLK_FUSE 198
223#define TEGRA124_CLK_FUSE_BURN 199
224#define TEGRA124_CLK_CLK_32K 200
225#define TEGRA124_CLK_CLK_M 201
226#define TEGRA124_CLK_CLK_M_DIV2 202
227#define TEGRA124_CLK_CLK_M_DIV4 203
228#define TEGRA124_CLK_PLL_REF 204
229#define TEGRA124_CLK_PLL_C 205
230#define TEGRA124_CLK_PLL_C_OUT1 206
231#define TEGRA124_CLK_PLL_C2 207
232#define TEGRA124_CLK_PLL_C3 208
233#define TEGRA124_CLK_PLL_M 209
234#define TEGRA124_CLK_PLL_M_OUT1 210
235#define TEGRA124_CLK_PLL_P 211
236#define TEGRA124_CLK_PLL_P_OUT1 212
237#define TEGRA124_CLK_PLL_P_OUT2 213
238#define TEGRA124_CLK_PLL_P_OUT3 214
239#define TEGRA124_CLK_PLL_P_OUT4 215
240#define TEGRA124_CLK_PLL_A 216
241#define TEGRA124_CLK_PLL_A_OUT0 217
242#define TEGRA124_CLK_PLL_D 218
243#define TEGRA124_CLK_PLL_D_OUT0 219
244#define TEGRA124_CLK_PLL_D2 220
245#define TEGRA124_CLK_PLL_D2_OUT0 221
246#define TEGRA124_CLK_PLL_U 222
247#define TEGRA124_CLK_PLL_U_480M 223
248
249#define TEGRA124_CLK_PLL_U_60M 224
250#define TEGRA124_CLK_PLL_U_48M 225
251#define TEGRA124_CLK_PLL_U_12M 226
252#define TEGRA124_CLK_PLL_X 227
253#define TEGRA124_CLK_PLL_X_OUT0 228
254#define TEGRA124_CLK_PLL_RE_VCO 229
255#define TEGRA124_CLK_PLL_RE_OUT 230
256#define TEGRA124_CLK_PLL_E 231
257#define TEGRA124_CLK_SPDIF_IN_SYNC 232
258#define TEGRA124_CLK_I2S0_SYNC 233
259#define TEGRA124_CLK_I2S1_SYNC 234
260#define TEGRA124_CLK_I2S2_SYNC 235
261#define TEGRA124_CLK_I2S3_SYNC 236
262#define TEGRA124_CLK_I2S4_SYNC 237
263#define TEGRA124_CLK_VIMCLK_SYNC 238
264#define TEGRA124_CLK_AUDIO0 239
265#define TEGRA124_CLK_AUDIO1 240
266#define TEGRA124_CLK_AUDIO2 241
267#define TEGRA124_CLK_AUDIO3 242
268#define TEGRA124_CLK_AUDIO4 243
269#define TEGRA124_CLK_SPDIF 244
270#define TEGRA124_CLK_CLK_OUT_1 245
271#define TEGRA124_CLK_CLK_OUT_2 246
272#define TEGRA124_CLK_CLK_OUT_3 247
273#define TEGRA124_CLK_BLINK 248
274/* 249 */
275/* 250 */
276/* 251 */
277#define TEGRA124_CLK_XUSB_HOST_SRC 252
278#define TEGRA124_CLK_XUSB_FALCON_SRC 253
279#define TEGRA124_CLK_XUSB_FS_SRC 254
280#define TEGRA124_CLK_XUSB_SS_SRC 255
281
282#define TEGRA124_CLK_XUSB_DEV_SRC 256
283#define TEGRA124_CLK_XUSB_DEV 257
284#define TEGRA124_CLK_XUSB_HS_SRC 258
285#define TEGRA124_CLK_SCLK 259
286#define TEGRA124_CLK_HCLK 260
287#define TEGRA124_CLK_PCLK 261
288#define TEGRA124_CLK_CCLK_G 262
289#define TEGRA124_CLK_CCLK_LP 263
290#define TEGRA124_CLK_DFLL_REF 264
291#define TEGRA124_CLK_DFLL_SOC 265
292#define TEGRA124_CLK_VI_SENSOR2 266
293#define TEGRA124_CLK_PLL_P_OUT5 267
294#define TEGRA124_CLK_CML0 268
295#define TEGRA124_CLK_CML1 269
296#define TEGRA124_CLK_PLL_C4 270
297#define TEGRA124_CLK_PLL_DP 271
298#define TEGRA124_CLK_PLL_E_MUX 272
299/* 273 */
300/* 274 */
301/* 275 */
302/* 276 */
303/* 277 */
304/* 278 */
305/* 279 */
306/* 280 */
307/* 281 */
308/* 282 */
309/* 283 */
310/* 284 */
311/* 285 */
312/* 286 */
313/* 287 */
314
315/* 288 */
316/* 289 */
317/* 290 */
318/* 291 */
319/* 292 */
320/* 293 */
321/* 294 */
322/* 295 */
323/* 296 */
324/* 297 */
325/* 298 */
326/* 299 */
327#define TEGRA124_CLK_AUDIO0_MUX 300
328#define TEGRA124_CLK_AUDIO1_MUX 301
329#define TEGRA124_CLK_AUDIO2_MUX 302
330#define TEGRA124_CLK_AUDIO3_MUX 303
331#define TEGRA124_CLK_AUDIO4_MUX 304
332#define TEGRA124_CLK_SPDIF_MUX 305
333#define TEGRA124_CLK_CLK_OUT_1_MUX 306
334#define TEGRA124_CLK_CLK_OUT_2_MUX 307
335#define TEGRA124_CLK_CLK_OUT_3_MUX 308
336#define TEGRA124_CLK_DSIA_MUX 309
337#define TEGRA124_CLK_DSIB_MUX 310
338#define TEGRA124_CLK_SOR0_LVDS 311
339#define TEGRA124_CLK_CLK_MAX 312
340
341#endif /* _DT_BINDINGS_CLOCK_TEGRA124_CAR_H */
diff --git a/include/dt-bindings/clock/tegra20-car.h b/include/dt-bindings/clock/tegra20-car.h
index a1ae9a8fdd6c..9406207cfac8 100644
--- a/include/dt-bindings/clock/tegra20-car.h
+++ b/include/dt-bindings/clock/tegra20-car.h
@@ -92,7 +92,7 @@
92#define TEGRA20_CLK_OWR 71 92#define TEGRA20_CLK_OWR 71
93#define TEGRA20_CLK_AFI 72 93#define TEGRA20_CLK_AFI 72
94#define TEGRA20_CLK_CSITE 73 94#define TEGRA20_CLK_CSITE 73
95#define TEGRA20_CLK_PCIE_XCLK 74 95/* 74 */
96#define TEGRA20_CLK_AVPUCQ 75 96#define TEGRA20_CLK_AVPUCQ 75
97#define TEGRA20_CLK_LA 76 97#define TEGRA20_CLK_LA 76
98/* 77 */ 98/* 77 */
diff --git a/include/dt-bindings/clock/tegra30-car.h b/include/dt-bindings/clock/tegra30-car.h
index e40fae8f9a8d..889e49ba0aa3 100644
--- a/include/dt-bindings/clock/tegra30-car.h
+++ b/include/dt-bindings/clock/tegra30-car.h
@@ -92,7 +92,7 @@
92#define TEGRA30_CLK_OWR 71 92#define TEGRA30_CLK_OWR 71
93#define TEGRA30_CLK_AFI 72 93#define TEGRA30_CLK_AFI 72
94#define TEGRA30_CLK_CSITE 73 94#define TEGRA30_CLK_CSITE 73
95#define TEGRA30_CLK_PCIEX 74 95/* 74 */
96#define TEGRA30_CLK_AVPUCQ 75 96#define TEGRA30_CLK_AVPUCQ 75
97#define TEGRA30_CLK_LA 76 97#define TEGRA30_CLK_LA 76
98/* 77 */ 98/* 77 */
@@ -260,6 +260,14 @@
260/* 298 */ 260/* 298 */
261/* 299 */ 261/* 299 */
262#define TEGRA30_CLK_CLK_OUT_1_MUX 300 262#define TEGRA30_CLK_CLK_OUT_1_MUX 300
263#define TEGRA30_CLK_CLK_MAX 301 263#define TEGRA30_CLK_CLK_OUT_2_MUX 301
264#define TEGRA30_CLK_CLK_OUT_3_MUX 302
265#define TEGRA30_CLK_AUDIO0_MUX 303
266#define TEGRA30_CLK_AUDIO1_MUX 304
267#define TEGRA30_CLK_AUDIO2_MUX 305
268#define TEGRA30_CLK_AUDIO3_MUX 306
269#define TEGRA30_CLK_AUDIO4_MUX 307
270#define TEGRA30_CLK_SPDIF_MUX 308
271#define TEGRA30_CLK_CLK_MAX 309
264 272
265#endif /* _DT_BINDINGS_CLOCK_TEGRA30_CAR_H */ 273#endif /* _DT_BINDINGS_CLOCK_TEGRA30_CAR_H */
diff --git a/include/dt-bindings/gpio/tegra-gpio.h b/include/dt-bindings/gpio/tegra-gpio.h
index 4d179c00f081..197dc28b676e 100644
--- a/include/dt-bindings/gpio/tegra-gpio.h
+++ b/include/dt-bindings/gpio/tegra-gpio.h
@@ -43,6 +43,7 @@
43#define TEGRA_GPIO_BANK_ID_CC 28 43#define TEGRA_GPIO_BANK_ID_CC 28
44#define TEGRA_GPIO_BANK_ID_DD 29 44#define TEGRA_GPIO_BANK_ID_DD 29
45#define TEGRA_GPIO_BANK_ID_EE 30 45#define TEGRA_GPIO_BANK_ID_EE 30
46#define TEGRA_GPIO_BANK_ID_FF 31
46 47
47#define TEGRA_GPIO(bank, offset) \ 48#define TEGRA_GPIO(bank, offset) \
48 ((TEGRA_GPIO_BANK_ID_##bank * 8) + offset) 49 ((TEGRA_GPIO_BANK_ID_##bank * 8) + offset)
diff --git a/include/dt-bindings/pinctrl/pinctrl-tegra.h b/include/dt-bindings/pinctrl/pinctrl-tegra.h
new file mode 100644
index 000000000000..ebafa498be0f
--- /dev/null
+++ b/include/dt-bindings/pinctrl/pinctrl-tegra.h
@@ -0,0 +1,45 @@
1/*
2 * This header provides constants for Tegra pinctrl bindings.
3 *
4 * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Author: Laxman Dewangan <ldewangan@nvidia.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 */
17
18#ifndef _DT_BINDINGS_PINCTRL_TEGRA_H
19#define _DT_BINDINGS_PINCTRL_TEGRA_H
20
21/*
22 * Enable/disable for diffeent dt properties. This is applicable for
23 * properties nvidia,enable-input, nvidia,tristate, nvidia,open-drain,
24 * nvidia,lock, nvidia,rcv-sel, nvidia,high-speed-mode, nvidia,schmitt.
25 */
26#define TEGRA_PIN_DISABLE 0
27#define TEGRA_PIN_ENABLE 1
28
29#define TEGRA_PIN_PULL_NONE 0
30#define TEGRA_PIN_PULL_DOWN 1
31#define TEGRA_PIN_PULL_UP 2
32
33/* Low power mode driver */
34#define TEGRA_PIN_LP_DRIVE_DIV_8 0
35#define TEGRA_PIN_LP_DRIVE_DIV_4 1
36#define TEGRA_PIN_LP_DRIVE_DIV_2 2
37#define TEGRA_PIN_LP_DRIVE_DIV_1 3
38
39/* Rising/Falling slew rate */
40#define TEGRA_PIN_SLEW_RATE_FASTEST 0
41#define TEGRA_PIN_SLEW_RATE_FAST 1
42#define TEGRA_PIN_SLEW_RATE_SLOW 2
43#define TEGRA_PIN_SLEW_RATE_SLOWEST 3
44
45#endif
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/include/linux/clk/at91_pmc.h
index c604cc69acb5..a6911ebbd02a 100644
--- a/arch/arm/mach-at91/include/mach/at91_pmc.h
+++ b/include/linux/clk/at91_pmc.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * arch/arm/mach-at91/include/mach/at91_pmc.h 2 * include/linux/clk/at91_pmc.h
3 * 3 *
4 * Copyright (C) 2005 Ivan Kokshaysky 4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People 5 * Copyright (C) SAN People
@@ -164,6 +164,8 @@ extern void __iomem *at91_pmc_base;
164#define AT91_PMC_CFDEV (1 << 18) /* Clock Failure Detector Event [some SAM9] */ 164#define AT91_PMC_CFDEV (1 << 18) /* Clock Failure Detector Event [some SAM9] */
165#define AT91_PMC_IMR 0x6c /* Interrupt Mask Register */ 165#define AT91_PMC_IMR 0x6c /* Interrupt Mask Register */
166 166
167#define AT91_PMC_PLLICPR 0x80 /* PLL Charge Pump Current Register */
168
167#define AT91_PMC_PROT 0xe4 /* Write Protect Mode Register [some SAM9] */ 169#define AT91_PMC_PROT 0xe4 /* Write Protect Mode Register [some SAM9] */
168#define AT91_PMC_WPEN (0x1 << 0) /* Write Protect Enable */ 170#define AT91_PMC_WPEN (0x1 << 0) /* Write Protect Enable */
169#define AT91_PMC_WPKEY (0xffffff << 8) /* Write Protect Key */ 171#define AT91_PMC_WPKEY (0xffffff << 8) /* Write Protect Key */
diff --git a/include/linux/clk/tegra.h b/include/linux/clk/tegra.h
index 23a0ceee831f..3ca9fca827a2 100644
--- a/include/linux/clk/tegra.h
+++ b/include/linux/clk/tegra.h
@@ -120,13 +120,6 @@ static inline void tegra_cpu_clock_resume(void)
120} 120}
121#endif 121#endif
122 122
123#ifdef CONFIG_ARCH_TEGRA
124void tegra_periph_reset_deassert(struct clk *c);
125void tegra_periph_reset_assert(struct clk *c);
126#else
127static inline void tegra_periph_reset_deassert(struct clk *c) {}
128static inline void tegra_periph_reset_assert(struct clk *c) {}
129#endif
130void tegra_clocks_apply_init_table(void); 123void tegra_clocks_apply_init_table(void);
131 124
132#endif /* __LINUX_CLK_TEGRA_H_ */ 125#endif /* __LINUX_CLK_TEGRA_H_ */
diff --git a/include/linux/cpufreq.h b/include/linux/cpufreq.h
index dc196bbcf227..ee5fe9d77ae8 100644
--- a/include/linux/cpufreq.h
+++ b/include/linux/cpufreq.h
@@ -280,6 +280,14 @@ cpufreq_verify_within_cpu_limits(struct cpufreq_policy *policy)
280 policy->cpuinfo.max_freq); 280 policy->cpuinfo.max_freq);
281} 281}
282 282
283#ifdef CONFIG_CPU_FREQ
284void cpufreq_suspend(void);
285void cpufreq_resume(void);
286#else
287static inline void cpufreq_suspend(void) {}
288static inline void cpufreq_resume(void) {}
289#endif
290
283/********************************************************************* 291/*********************************************************************
284 * CPUFREQ NOTIFIER INTERFACE * 292 * CPUFREQ NOTIFIER INTERFACE *
285 *********************************************************************/ 293 *********************************************************************/
diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
index 41cf0c399288..bae1568416f8 100644
--- a/include/linux/dmaengine.h
+++ b/include/linux/dmaengine.h
@@ -22,6 +22,7 @@
22#define LINUX_DMAENGINE_H 22#define LINUX_DMAENGINE_H
23 23
24#include <linux/device.h> 24#include <linux/device.h>
25#include <linux/err.h>
25#include <linux/uio.h> 26#include <linux/uio.h>
26#include <linux/bug.h> 27#include <linux/bug.h>
27#include <linux/scatterlist.h> 28#include <linux/scatterlist.h>
@@ -1040,6 +1041,8 @@ enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx);
1040void dma_issue_pending_all(void); 1041void dma_issue_pending_all(void);
1041struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask, 1042struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
1042 dma_filter_fn fn, void *fn_param); 1043 dma_filter_fn fn, void *fn_param);
1044struct dma_chan *dma_request_slave_channel_reason(struct device *dev,
1045 const char *name);
1043struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name); 1046struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name);
1044void dma_release_channel(struct dma_chan *chan); 1047void dma_release_channel(struct dma_chan *chan);
1045#else 1048#else
@@ -1063,6 +1066,11 @@ static inline struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
1063{ 1066{
1064 return NULL; 1067 return NULL;
1065} 1068}
1069static inline struct dma_chan *dma_request_slave_channel_reason(
1070 struct device *dev, const char *name)
1071{
1072 return ERR_PTR(-ENODEV);
1073}
1066static inline struct dma_chan *dma_request_slave_channel(struct device *dev, 1074static inline struct dma_chan *dma_request_slave_channel(struct device *dev,
1067 const char *name) 1075 const char *name)
1068{ 1076{
@@ -1079,6 +1087,7 @@ int dma_async_device_register(struct dma_device *device);
1079void dma_async_device_unregister(struct dma_device *device); 1087void dma_async_device_unregister(struct dma_device *device);
1080void dma_run_dependencies(struct dma_async_tx_descriptor *tx); 1088void dma_run_dependencies(struct dma_async_tx_descriptor *tx);
1081struct dma_chan *dma_get_slave_channel(struct dma_chan *chan); 1089struct dma_chan *dma_get_slave_channel(struct dma_chan *chan);
1090struct dma_chan *dma_get_any_slave_channel(struct dma_device *device);
1082struct dma_chan *net_dma_find_channel(void); 1091struct dma_chan *net_dma_find_channel(void);
1083#define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y) 1092#define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y)
1084#define dma_request_slave_channel_compat(mask, x, y, dev, name) \ 1093#define dma_request_slave_channel_compat(mask, x, y, dev, name) \
diff --git a/include/linux/efi.h b/include/linux/efi.h
index bc5687d0f315..11ce6784a196 100644
--- a/include/linux/efi.h
+++ b/include/linux/efi.h
@@ -801,6 +801,8 @@ struct efivar_entry {
801 struct efi_variable var; 801 struct efi_variable var;
802 struct list_head list; 802 struct list_head list;
803 struct kobject kobj; 803 struct kobject kobj;
804 bool scanning;
805 bool deleting;
804}; 806};
805 807
806 808
@@ -866,6 +868,8 @@ void efivar_run_worker(void);
866#if defined(CONFIG_EFI_VARS) || defined(CONFIG_EFI_VARS_MODULE) 868#if defined(CONFIG_EFI_VARS) || defined(CONFIG_EFI_VARS_MODULE)
867int efivars_sysfs_init(void); 869int efivars_sysfs_init(void);
868 870
871#define EFIVARS_DATA_SIZE_MAX 1024
872
869#endif /* CONFIG_EFI_VARS */ 873#endif /* CONFIG_EFI_VARS */
870 874
871#endif /* _LINUX_EFI_H */ 875#endif /* _LINUX_EFI_H */
diff --git a/include/linux/ftrace_event.h b/include/linux/ftrace_event.h
index 9abbe630c456..8c9b7a1c4138 100644
--- a/include/linux/ftrace_event.h
+++ b/include/linux/ftrace_event.h
@@ -248,6 +248,9 @@ struct ftrace_event_call {
248#ifdef CONFIG_PERF_EVENTS 248#ifdef CONFIG_PERF_EVENTS
249 int perf_refcount; 249 int perf_refcount;
250 struct hlist_head __percpu *perf_events; 250 struct hlist_head __percpu *perf_events;
251
252 int (*perf_perm)(struct ftrace_event_call *,
253 struct perf_event *);
251#endif 254#endif
252}; 255};
253 256
@@ -317,6 +320,19 @@ struct ftrace_event_file {
317 } \ 320 } \
318 early_initcall(trace_init_flags_##name); 321 early_initcall(trace_init_flags_##name);
319 322
323#define __TRACE_EVENT_PERF_PERM(name, expr...) \
324 static int perf_perm_##name(struct ftrace_event_call *tp_event, \
325 struct perf_event *p_event) \
326 { \
327 return ({ expr; }); \
328 } \
329 static int __init trace_init_perf_perm_##name(void) \
330 { \
331 event_##name.perf_perm = &perf_perm_##name; \
332 return 0; \
333 } \
334 early_initcall(trace_init_perf_perm_##name);
335
320#define PERF_MAX_TRACE_SIZE 2048 336#define PERF_MAX_TRACE_SIZE 2048
321 337
322#define MAX_FILTER_STR_VAL 256 /* Should handle KSYM_SYMBOL_LEN */ 338#define MAX_FILTER_STR_VAL 256 /* Should handle KSYM_SYMBOL_LEN */
diff --git a/include/linux/gpio/driver.h b/include/linux/gpio/driver.h
index 656a27efb2c8..3ea2cf6b0e6c 100644
--- a/include/linux/gpio/driver.h
+++ b/include/linux/gpio/driver.h
@@ -2,9 +2,12 @@
2#define __LINUX_GPIO_DRIVER_H 2#define __LINUX_GPIO_DRIVER_H
3 3
4#include <linux/types.h> 4#include <linux/types.h>
5#include <linux/module.h>
5 6
6struct device; 7struct device;
7struct gpio_desc; 8struct gpio_desc;
9struct of_phandle_args;
10struct device_node;
8struct seq_file; 11struct seq_file;
9 12
10/** 13/**
@@ -125,6 +128,13 @@ extern struct gpio_chip *gpiochip_find(void *data,
125int gpiod_lock_as_irq(struct gpio_desc *desc); 128int gpiod_lock_as_irq(struct gpio_desc *desc);
126void gpiod_unlock_as_irq(struct gpio_desc *desc); 129void gpiod_unlock_as_irq(struct gpio_desc *desc);
127 130
131enum gpio_lookup_flags {
132 GPIO_ACTIVE_HIGH = (0 << 0),
133 GPIO_ACTIVE_LOW = (1 << 0),
134 GPIO_OPEN_DRAIN = (1 << 1),
135 GPIO_OPEN_SOURCE = (1 << 2),
136};
137
128/** 138/**
129 * Lookup table for associating GPIOs to specific devices and functions using 139 * Lookup table for associating GPIOs to specific devices and functions using
130 * platform data. 140 * platform data.
@@ -152,9 +162,9 @@ struct gpiod_lookup {
152 */ 162 */
153 unsigned int idx; 163 unsigned int idx;
154 /* 164 /*
155 * mask of GPIOF_* values 165 * mask of GPIO_* values
156 */ 166 */
157 unsigned long flags; 167 enum gpio_lookup_flags flags;
158}; 168};
159 169
160/* 170/*
diff --git a/include/linux/hid-sensor-hub.h b/include/linux/hid-sensor-hub.h
index a265af294ea4..206a2af6b62b 100644
--- a/include/linux/hid-sensor-hub.h
+++ b/include/linux/hid-sensor-hub.h
@@ -21,6 +21,8 @@
21 21
22#include <linux/hid.h> 22#include <linux/hid.h>
23#include <linux/hid-sensor-ids.h> 23#include <linux/hid-sensor-ids.h>
24#include <linux/iio/iio.h>
25#include <linux/iio/trigger.h>
24 26
25/** 27/**
26 * struct hid_sensor_hub_attribute_info - Attribute info 28 * struct hid_sensor_hub_attribute_info - Attribute info
@@ -184,6 +186,7 @@ struct hid_sensor_common {
184 struct platform_device *pdev; 186 struct platform_device *pdev;
185 unsigned usage_id; 187 unsigned usage_id;
186 bool data_ready; 188 bool data_ready;
189 struct iio_trigger *trigger;
187 struct hid_sensor_hub_attribute_info poll; 190 struct hid_sensor_hub_attribute_info poll;
188 struct hid_sensor_hub_attribute_info report_state; 191 struct hid_sensor_hub_attribute_info report_state;
189 struct hid_sensor_hub_attribute_info power_state; 192 struct hid_sensor_hub_attribute_info power_state;
diff --git a/include/linux/irqreturn.h b/include/linux/irqreturn.h
index 714ba08dc092..e374e369fb2f 100644
--- a/include/linux/irqreturn.h
+++ b/include/linux/irqreturn.h
@@ -14,6 +14,6 @@ enum irqreturn {
14}; 14};
15 15
16typedef enum irqreturn irqreturn_t; 16typedef enum irqreturn irqreturn_t;
17#define IRQ_RETVAL(x) ((x) != IRQ_NONE) 17#define IRQ_RETVAL(x) ((x) ? IRQ_HANDLED : IRQ_NONE)
18 18
19#endif 19#endif
diff --git a/include/linux/nfs4.h b/include/linux/nfs4.h
index c1637062c1ce..12c2cb947df5 100644
--- a/include/linux/nfs4.h
+++ b/include/linux/nfs4.h
@@ -413,16 +413,6 @@ enum lock_type4 {
413#define NFS4_VERSION 4 413#define NFS4_VERSION 4
414#define NFS4_MINOR_VERSION 0 414#define NFS4_MINOR_VERSION 0
415 415
416#if defined(CONFIG_NFS_V4_2)
417#define NFS4_MAX_MINOR_VERSION 2
418#else
419#if defined(CONFIG_NFS_V4_1)
420#define NFS4_MAX_MINOR_VERSION 1
421#else
422#define NFS4_MAX_MINOR_VERSION 0
423#endif /* CONFIG_NFS_V4_1 */
424#endif /* CONFIG_NFS_V4_2 */
425
426#define NFS4_DEBUG 1 416#define NFS4_DEBUG 1
427 417
428/* Index of predefined Linux client operations */ 418/* Index of predefined Linux client operations */
diff --git a/include/linux/nfs_fs.h b/include/linux/nfs_fs.h
index 14a48207a304..48997374eaf0 100644
--- a/include/linux/nfs_fs.h
+++ b/include/linux/nfs_fs.h
@@ -507,24 +507,6 @@ extern int nfs_mountpoint_expiry_timeout;
507extern void nfs_release_automount_timer(void); 507extern void nfs_release_automount_timer(void);
508 508
509/* 509/*
510 * linux/fs/nfs/nfs4proc.c
511 */
512#ifdef CONFIG_NFS_V4_SECURITY_LABEL
513extern struct nfs4_label *nfs4_label_alloc(struct nfs_server *server, gfp_t flags);
514static inline void nfs4_label_free(struct nfs4_label *label)
515{
516 if (label) {
517 kfree(label->label);
518 kfree(label);
519 }
520 return;
521}
522#else
523static inline struct nfs4_label *nfs4_label_alloc(struct nfs_server *server, gfp_t flags) { return NULL; }
524static inline void nfs4_label_free(void *label) {}
525#endif
526
527/*
528 * linux/fs/nfs/unlink.c 510 * linux/fs/nfs/unlink.c
529 */ 511 */
530extern void nfs_complete_unlink(struct dentry *dentry, struct inode *); 512extern void nfs_complete_unlink(struct dentry *dentry, struct inode *);
diff --git a/include/linux/padata.h b/include/linux/padata.h
index 86292beebfe2..438694650471 100644
--- a/include/linux/padata.h
+++ b/include/linux/padata.h
@@ -129,10 +129,9 @@ struct parallel_data {
129 struct padata_serial_queue __percpu *squeue; 129 struct padata_serial_queue __percpu *squeue;
130 atomic_t reorder_objects; 130 atomic_t reorder_objects;
131 atomic_t refcnt; 131 atomic_t refcnt;
132 atomic_t seq_nr;
132 struct padata_cpumask cpumask; 133 struct padata_cpumask cpumask;
133 spinlock_t lock ____cacheline_aligned; 134 spinlock_t lock ____cacheline_aligned;
134 spinlock_t seq_lock;
135 unsigned int seq_nr;
136 unsigned int processed; 135 unsigned int processed;
137 struct timer_list timer; 136 struct timer_list timer;
138}; 137};
diff --git a/include/linux/platform_data/clocksource-nomadik-mtu.h b/include/linux/platform_data/clocksource-nomadik-mtu.h
deleted file mode 100644
index 80088973b734..000000000000
--- a/include/linux/platform_data/clocksource-nomadik-mtu.h
+++ /dev/null
@@ -1,9 +0,0 @@
1#ifndef __PLAT_MTU_H
2#define __PLAT_MTU_H
3
4void nmdk_timer_init(void __iomem *base, int irq);
5void nmdk_clkevt_reset(void);
6void nmdk_clksrc_reset(void);
7
8#endif /* __PLAT_MTU_H */
9
diff --git a/include/linux/platform_data/pinctrl-nomadik.h b/include/linux/platform_data/pinctrl-nomadik.h
deleted file mode 100644
index abf5bed84df3..000000000000
--- a/include/linux/platform_data/pinctrl-nomadik.h
+++ /dev/null
@@ -1,242 +0,0 @@
1/*
2 * Structures and registers for GPIO access in the Nomadik SoC
3 *
4 * Copyright (C) 2008 STMicroelectronics
5 * Author: Prafulla WADASKAR <prafulla.wadaskar@st.com>
6 * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __PLAT_NOMADIK_GPIO
14#define __PLAT_NOMADIK_GPIO
15
16/*
17 * pin configurations are represented by 32-bit integers:
18 *
19 * bit 0.. 8 - Pin Number (512 Pins Maximum)
20 * bit 9..10 - Alternate Function Selection
21 * bit 11..12 - Pull up/down state
22 * bit 13 - Sleep mode behaviour
23 * bit 14 - Direction
24 * bit 15 - Value (if output)
25 * bit 16..18 - SLPM pull up/down state
26 * bit 19..20 - SLPM direction
27 * bit 21..22 - SLPM Value (if output)
28 * bit 23..25 - PDIS value (if input)
29 * bit 26 - Gpio mode
30 * bit 27 - Sleep mode
31 *
32 * to facilitate the definition, the following macros are provided
33 *
34 * PIN_CFG_DEFAULT - default config (0):
35 * pull up/down = disabled
36 * sleep mode = input/wakeup
37 * direction = input
38 * value = low
39 * SLPM direction = same as normal
40 * SLPM pull = same as normal
41 * SLPM value = same as normal
42 *
43 * PIN_CFG - default config with alternate function
44 */
45
46typedef unsigned long pin_cfg_t;
47
48#define PIN_NUM_MASK 0x1ff
49#define PIN_NUM(x) ((x) & PIN_NUM_MASK)
50
51#define PIN_ALT_SHIFT 9
52#define PIN_ALT_MASK (0x3 << PIN_ALT_SHIFT)
53#define PIN_ALT(x) (((x) & PIN_ALT_MASK) >> PIN_ALT_SHIFT)
54#define PIN_GPIO (NMK_GPIO_ALT_GPIO << PIN_ALT_SHIFT)
55#define PIN_ALT_A (NMK_GPIO_ALT_A << PIN_ALT_SHIFT)
56#define PIN_ALT_B (NMK_GPIO_ALT_B << PIN_ALT_SHIFT)
57#define PIN_ALT_C (NMK_GPIO_ALT_C << PIN_ALT_SHIFT)
58
59#define PIN_PULL_SHIFT 11
60#define PIN_PULL_MASK (0x3 << PIN_PULL_SHIFT)
61#define PIN_PULL(x) (((x) & PIN_PULL_MASK) >> PIN_PULL_SHIFT)
62#define PIN_PULL_NONE (NMK_GPIO_PULL_NONE << PIN_PULL_SHIFT)
63#define PIN_PULL_UP (NMK_GPIO_PULL_UP << PIN_PULL_SHIFT)
64#define PIN_PULL_DOWN (NMK_GPIO_PULL_DOWN << PIN_PULL_SHIFT)
65
66#define PIN_SLPM_SHIFT 13
67#define PIN_SLPM_MASK (0x1 << PIN_SLPM_SHIFT)
68#define PIN_SLPM(x) (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT)
69#define PIN_SLPM_MAKE_INPUT (NMK_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT)
70#define PIN_SLPM_NOCHANGE (NMK_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT)
71/* These two replace the above in DB8500v2+ */
72#define PIN_SLPM_WAKEUP_ENABLE (NMK_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT)
73#define PIN_SLPM_WAKEUP_DISABLE (NMK_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT)
74#define PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP PIN_SLPM_WAKEUP_DISABLE
75
76#define PIN_SLPM_GPIO PIN_SLPM_WAKEUP_ENABLE /* In SLPM, pin is a gpio */
77#define PIN_SLPM_ALTFUNC PIN_SLPM_WAKEUP_DISABLE /* In SLPM, pin is altfunc */
78
79#define PIN_DIR_SHIFT 14
80#define PIN_DIR_MASK (0x1 << PIN_DIR_SHIFT)
81#define PIN_DIR(x) (((x) & PIN_DIR_MASK) >> PIN_DIR_SHIFT)
82#define PIN_DIR_INPUT (0 << PIN_DIR_SHIFT)
83#define PIN_DIR_OUTPUT (1 << PIN_DIR_SHIFT)
84
85#define PIN_VAL_SHIFT 15
86#define PIN_VAL_MASK (0x1 << PIN_VAL_SHIFT)
87#define PIN_VAL(x) (((x) & PIN_VAL_MASK) >> PIN_VAL_SHIFT)
88#define PIN_VAL_LOW (0 << PIN_VAL_SHIFT)
89#define PIN_VAL_HIGH (1 << PIN_VAL_SHIFT)
90
91#define PIN_SLPM_PULL_SHIFT 16
92#define PIN_SLPM_PULL_MASK (0x7 << PIN_SLPM_PULL_SHIFT)
93#define PIN_SLPM_PULL(x) \
94 (((x) & PIN_SLPM_PULL_MASK) >> PIN_SLPM_PULL_SHIFT)
95#define PIN_SLPM_PULL_NONE \
96 ((1 + NMK_GPIO_PULL_NONE) << PIN_SLPM_PULL_SHIFT)
97#define PIN_SLPM_PULL_UP \
98 ((1 + NMK_GPIO_PULL_UP) << PIN_SLPM_PULL_SHIFT)
99#define PIN_SLPM_PULL_DOWN \
100 ((1 + NMK_GPIO_PULL_DOWN) << PIN_SLPM_PULL_SHIFT)
101
102#define PIN_SLPM_DIR_SHIFT 19
103#define PIN_SLPM_DIR_MASK (0x3 << PIN_SLPM_DIR_SHIFT)
104#define PIN_SLPM_DIR(x) \
105 (((x) & PIN_SLPM_DIR_MASK) >> PIN_SLPM_DIR_SHIFT)
106#define PIN_SLPM_DIR_INPUT ((1 + 0) << PIN_SLPM_DIR_SHIFT)
107#define PIN_SLPM_DIR_OUTPUT ((1 + 1) << PIN_SLPM_DIR_SHIFT)
108
109#define PIN_SLPM_VAL_SHIFT 21
110#define PIN_SLPM_VAL_MASK (0x3 << PIN_SLPM_VAL_SHIFT)
111#define PIN_SLPM_VAL(x) \
112 (((x) & PIN_SLPM_VAL_MASK) >> PIN_SLPM_VAL_SHIFT)
113#define PIN_SLPM_VAL_LOW ((1 + 0) << PIN_SLPM_VAL_SHIFT)
114#define PIN_SLPM_VAL_HIGH ((1 + 1) << PIN_SLPM_VAL_SHIFT)
115
116#define PIN_SLPM_PDIS_SHIFT 23
117#define PIN_SLPM_PDIS_MASK (0x3 << PIN_SLPM_PDIS_SHIFT)
118#define PIN_SLPM_PDIS(x) \
119 (((x) & PIN_SLPM_PDIS_MASK) >> PIN_SLPM_PDIS_SHIFT)
120#define PIN_SLPM_PDIS_NO_CHANGE (0 << PIN_SLPM_PDIS_SHIFT)
121#define PIN_SLPM_PDIS_DISABLED (1 << PIN_SLPM_PDIS_SHIFT)
122#define PIN_SLPM_PDIS_ENABLED (2 << PIN_SLPM_PDIS_SHIFT)
123
124#define PIN_LOWEMI_SHIFT 25
125#define PIN_LOWEMI_MASK (0x1 << PIN_LOWEMI_SHIFT)
126#define PIN_LOWEMI(x) (((x) & PIN_LOWEMI_MASK) >> PIN_LOWEMI_SHIFT)
127#define PIN_LOWEMI_DISABLED (0 << PIN_LOWEMI_SHIFT)
128#define PIN_LOWEMI_ENABLED (1 << PIN_LOWEMI_SHIFT)
129
130#define PIN_GPIOMODE_SHIFT 26
131#define PIN_GPIOMODE_MASK (0x1 << PIN_GPIOMODE_SHIFT)
132#define PIN_GPIOMODE(x) (((x) & PIN_GPIOMODE_MASK) >> PIN_GPIOMODE_SHIFT)
133#define PIN_GPIOMODE_DISABLED (0 << PIN_GPIOMODE_SHIFT)
134#define PIN_GPIOMODE_ENABLED (1 << PIN_GPIOMODE_SHIFT)
135
136#define PIN_SLEEPMODE_SHIFT 27
137#define PIN_SLEEPMODE_MASK (0x1 << PIN_SLEEPMODE_SHIFT)
138#define PIN_SLEEPMODE(x) (((x) & PIN_SLEEPMODE_MASK) >> PIN_SLEEPMODE_SHIFT)
139#define PIN_SLEEPMODE_DISABLED (0 << PIN_SLEEPMODE_SHIFT)
140#define PIN_SLEEPMODE_ENABLED (1 << PIN_SLEEPMODE_SHIFT)
141
142
143/* Shortcuts. Use these instead of separate DIR, PULL, and VAL. */
144#define PIN_INPUT_PULLDOWN (PIN_DIR_INPUT | PIN_PULL_DOWN)
145#define PIN_INPUT_PULLUP (PIN_DIR_INPUT | PIN_PULL_UP)
146#define PIN_INPUT_NOPULL (PIN_DIR_INPUT | PIN_PULL_NONE)
147#define PIN_OUTPUT_LOW (PIN_DIR_OUTPUT | PIN_VAL_LOW)
148#define PIN_OUTPUT_HIGH (PIN_DIR_OUTPUT | PIN_VAL_HIGH)
149
150#define PIN_SLPM_INPUT_PULLDOWN (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_DOWN)
151#define PIN_SLPM_INPUT_PULLUP (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_UP)
152#define PIN_SLPM_INPUT_NOPULL (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_NONE)
153#define PIN_SLPM_OUTPUT_LOW (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_LOW)
154#define PIN_SLPM_OUTPUT_HIGH (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_HIGH)
155
156#define PIN_CFG_DEFAULT (0)
157
158#define PIN_CFG(num, alt) \
159 (PIN_CFG_DEFAULT |\
160 (PIN_NUM(num) | PIN_##alt))
161
162#define PIN_CFG_INPUT(num, alt, pull) \
163 (PIN_CFG_DEFAULT |\
164 (PIN_NUM(num) | PIN_##alt | PIN_INPUT_##pull))
165
166#define PIN_CFG_OUTPUT(num, alt, val) \
167 (PIN_CFG_DEFAULT |\
168 (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val))
169
170/*
171 * "nmk_gpio" and "NMK_GPIO" stand for "Nomadik GPIO", leaving
172 * the "gpio" namespace for generic and cross-machine functions
173 */
174
175#define GPIO_BLOCK_SHIFT 5
176#define NMK_GPIO_PER_CHIP (1 << GPIO_BLOCK_SHIFT)
177
178/* Register in the logic block */
179#define NMK_GPIO_DAT 0x00
180#define NMK_GPIO_DATS 0x04
181#define NMK_GPIO_DATC 0x08
182#define NMK_GPIO_PDIS 0x0c
183#define NMK_GPIO_DIR 0x10
184#define NMK_GPIO_DIRS 0x14
185#define NMK_GPIO_DIRC 0x18
186#define NMK_GPIO_SLPC 0x1c
187#define NMK_GPIO_AFSLA 0x20
188#define NMK_GPIO_AFSLB 0x24
189#define NMK_GPIO_LOWEMI 0x28
190
191#define NMK_GPIO_RIMSC 0x40
192#define NMK_GPIO_FIMSC 0x44
193#define NMK_GPIO_IS 0x48
194#define NMK_GPIO_IC 0x4c
195#define NMK_GPIO_RWIMSC 0x50
196#define NMK_GPIO_FWIMSC 0x54
197#define NMK_GPIO_WKS 0x58
198/* These appear in DB8540 and later ASICs */
199#define NMK_GPIO_EDGELEVEL 0x5C
200#define NMK_GPIO_LEVEL 0x60
201
202/* Alternate functions: function C is set in hw by setting both A and B */
203#define NMK_GPIO_ALT_GPIO 0
204#define NMK_GPIO_ALT_A 1
205#define NMK_GPIO_ALT_B 2
206#define NMK_GPIO_ALT_C (NMK_GPIO_ALT_A | NMK_GPIO_ALT_B)
207
208#define NMK_GPIO_ALT_CX_SHIFT 2
209#define NMK_GPIO_ALT_C1 ((1<<NMK_GPIO_ALT_CX_SHIFT) | NMK_GPIO_ALT_C)
210#define NMK_GPIO_ALT_C2 ((2<<NMK_GPIO_ALT_CX_SHIFT) | NMK_GPIO_ALT_C)
211#define NMK_GPIO_ALT_C3 ((3<<NMK_GPIO_ALT_CX_SHIFT) | NMK_GPIO_ALT_C)
212#define NMK_GPIO_ALT_C4 ((4<<NMK_GPIO_ALT_CX_SHIFT) | NMK_GPIO_ALT_C)
213
214/* Pull up/down values */
215enum nmk_gpio_pull {
216 NMK_GPIO_PULL_NONE,
217 NMK_GPIO_PULL_UP,
218 NMK_GPIO_PULL_DOWN,
219};
220
221/* Sleep mode */
222enum nmk_gpio_slpm {
223 NMK_GPIO_SLPM_INPUT,
224 NMK_GPIO_SLPM_WAKEUP_ENABLE = NMK_GPIO_SLPM_INPUT,
225 NMK_GPIO_SLPM_NOCHANGE,
226 NMK_GPIO_SLPM_WAKEUP_DISABLE = NMK_GPIO_SLPM_NOCHANGE,
227};
228
229/*
230 * Platform data to register a block: only the initial gpio/irq number.
231 */
232struct nmk_gpio_platform_data {
233 char *name;
234 int first_gpio;
235 int first_irq;
236 int num_gpio;
237 u32 (*get_secondary_status)(unsigned int bank);
238 void (*set_ioforce)(bool enable);
239 bool supports_sleepmode;
240};
241
242#endif /* __PLAT_NOMADIK_GPIO */
diff --git a/include/linux/sched.h b/include/linux/sched.h
index 7e35d4b9e14a..768b037dfacb 100644
--- a/include/linux/sched.h
+++ b/include/linux/sched.h
@@ -831,8 +831,6 @@ struct sched_domain {
831 unsigned int balance_interval; /* initialise to 1. units in ms. */ 831 unsigned int balance_interval; /* initialise to 1. units in ms. */
832 unsigned int nr_balance_failed; /* initialise to 0 */ 832 unsigned int nr_balance_failed; /* initialise to 0 */
833 833
834 u64 last_update;
835
836 /* idle_balance() stats */ 834 /* idle_balance() stats */
837 u64 max_newidle_lb_cost; 835 u64 max_newidle_lb_cost;
838 unsigned long next_decay_max_lb_cost; 836 unsigned long next_decay_max_lb_cost;
diff --git a/include/linux/slab.h b/include/linux/slab.h
index c2bba248fa63..1e2f4fe12773 100644
--- a/include/linux/slab.h
+++ b/include/linux/slab.h
@@ -388,10 +388,55 @@ static __always_inline void *kmalloc_large(size_t size, gfp_t flags)
388/** 388/**
389 * kmalloc - allocate memory 389 * kmalloc - allocate memory
390 * @size: how many bytes of memory are required. 390 * @size: how many bytes of memory are required.
391 * @flags: the type of memory to allocate (see kcalloc). 391 * @flags: the type of memory to allocate.
392 * 392 *
393 * kmalloc is the normal method of allocating memory 393 * kmalloc is the normal method of allocating memory
394 * for objects smaller than page size in the kernel. 394 * for objects smaller than page size in the kernel.
395 *
396 * The @flags argument may be one of:
397 *
398 * %GFP_USER - Allocate memory on behalf of user. May sleep.
399 *
400 * %GFP_KERNEL - Allocate normal kernel ram. May sleep.
401 *
402 * %GFP_ATOMIC - Allocation will not sleep. May use emergency pools.
403 * For example, use this inside interrupt handlers.
404 *
405 * %GFP_HIGHUSER - Allocate pages from high memory.
406 *
407 * %GFP_NOIO - Do not do any I/O at all while trying to get memory.
408 *
409 * %GFP_NOFS - Do not make any fs calls while trying to get memory.
410 *
411 * %GFP_NOWAIT - Allocation will not sleep.
412 *
413 * %GFP_THISNODE - Allocate node-local memory only.
414 *
415 * %GFP_DMA - Allocation suitable for DMA.
416 * Should only be used for kmalloc() caches. Otherwise, use a
417 * slab created with SLAB_DMA.
418 *
419 * Also it is possible to set different flags by OR'ing
420 * in one or more of the following additional @flags:
421 *
422 * %__GFP_COLD - Request cache-cold pages instead of
423 * trying to return cache-warm pages.
424 *
425 * %__GFP_HIGH - This allocation has high priority and may use emergency pools.
426 *
427 * %__GFP_NOFAIL - Indicate that this allocation is in no way allowed to fail
428 * (think twice before using).
429 *
430 * %__GFP_NORETRY - If memory is not immediately available,
431 * then give up at once.
432 *
433 * %__GFP_NOWARN - If allocation fails, don't issue any warnings.
434 *
435 * %__GFP_REPEAT - If allocation fails initially, try once more before failing.
436 *
437 * There are other flags available as well, but these are not intended
438 * for general use, and so are not documented here. For a full list of
439 * potential flags, always refer to linux/gfp.h.
395 */ 440 */
396static __always_inline void *kmalloc(size_t size, gfp_t flags) 441static __always_inline void *kmalloc(size_t size, gfp_t flags)
397{ 442{
@@ -502,61 +547,6 @@ int cache_show(struct kmem_cache *s, struct seq_file *m);
502void print_slabinfo_header(struct seq_file *m); 547void print_slabinfo_header(struct seq_file *m);
503 548
504/** 549/**
505 * kmalloc - allocate memory
506 * @size: how many bytes of memory are required.
507 * @flags: the type of memory to allocate.
508 *
509 * The @flags argument may be one of:
510 *
511 * %GFP_USER - Allocate memory on behalf of user. May sleep.
512 *
513 * %GFP_KERNEL - Allocate normal kernel ram. May sleep.
514 *
515 * %GFP_ATOMIC - Allocation will not sleep. May use emergency pools.
516 * For example, use this inside interrupt handlers.
517 *
518 * %GFP_HIGHUSER - Allocate pages from high memory.
519 *
520 * %GFP_NOIO - Do not do any I/O at all while trying to get memory.
521 *
522 * %GFP_NOFS - Do not make any fs calls while trying to get memory.
523 *
524 * %GFP_NOWAIT - Allocation will not sleep.
525 *
526 * %GFP_THISNODE - Allocate node-local memory only.
527 *
528 * %GFP_DMA - Allocation suitable for DMA.
529 * Should only be used for kmalloc() caches. Otherwise, use a
530 * slab created with SLAB_DMA.
531 *
532 * Also it is possible to set different flags by OR'ing
533 * in one or more of the following additional @flags:
534 *
535 * %__GFP_COLD - Request cache-cold pages instead of
536 * trying to return cache-warm pages.
537 *
538 * %__GFP_HIGH - This allocation has high priority and may use emergency pools.
539 *
540 * %__GFP_NOFAIL - Indicate that this allocation is in no way allowed to fail
541 * (think twice before using).
542 *
543 * %__GFP_NORETRY - If memory is not immediately available,
544 * then give up at once.
545 *
546 * %__GFP_NOWARN - If allocation fails, don't issue any warnings.
547 *
548 * %__GFP_REPEAT - If allocation fails initially, try once more before failing.
549 *
550 * There are other flags available as well, but these are not intended
551 * for general use, and so are not documented here. For a full list of
552 * potential flags, always refer to linux/gfp.h.
553 *
554 * kmalloc is the normal method of allocating memory
555 * in the kernel.
556 */
557static __always_inline void *kmalloc(size_t size, gfp_t flags);
558
559/**
560 * kmalloc_array - allocate memory for an array. 550 * kmalloc_array - allocate memory for an array.
561 * @n: number of elements. 551 * @n: number of elements.
562 * @size: element size. 552 * @size: element size.
diff --git a/include/linux/tegra-powergate.h b/include/linux/tegra-powergate.h
index c98cfa406952..afe442d2629a 100644
--- a/include/linux/tegra-powergate.h
+++ b/include/linux/tegra-powergate.h
@@ -19,6 +19,7 @@
19#define _MACH_TEGRA_POWERGATE_H_ 19#define _MACH_TEGRA_POWERGATE_H_
20 20
21struct clk; 21struct clk;
22struct reset_control;
22 23
23#define TEGRA_POWERGATE_CPU 0 24#define TEGRA_POWERGATE_CPU 0
24#define TEGRA_POWERGATE_3D 1 25#define TEGRA_POWERGATE_3D 1
@@ -45,12 +46,41 @@ struct clk;
45 46
46#define TEGRA_POWERGATE_3D0 TEGRA_POWERGATE_3D 47#define TEGRA_POWERGATE_3D0 TEGRA_POWERGATE_3D
47 48
49#ifdef CONFIG_ARCH_TEGRA
48int tegra_powergate_is_powered(int id); 50int tegra_powergate_is_powered(int id);
49int tegra_powergate_power_on(int id); 51int tegra_powergate_power_on(int id);
50int tegra_powergate_power_off(int id); 52int tegra_powergate_power_off(int id);
51int tegra_powergate_remove_clamping(int id); 53int tegra_powergate_remove_clamping(int id);
52 54
53/* Must be called with clk disabled, and returns with clk enabled */ 55/* Must be called with clk disabled, and returns with clk enabled */
54int tegra_powergate_sequence_power_up(int id, struct clk *clk); 56int tegra_powergate_sequence_power_up(int id, struct clk *clk,
57 struct reset_control *rst);
58#else
59static inline int tegra_powergate_is_powered(int id)
60{
61 return -ENOSYS;
62}
63
64static inline int tegra_powergate_power_on(int id)
65{
66 return -ENOSYS;
67}
68
69static inline int tegra_powergate_power_off(int id)
70{
71 return -ENOSYS;
72}
73
74static inline int tegra_powergate_remove_clamping(int id)
75{
76 return -ENOSYS;
77}
78
79static inline int tegra_powergate_sequence_power_up(int id, struct clk *clk,
80 struct reset_control *rst);
81{
82 return -ENOSYS;
83}
84#endif
55 85
56#endif /* _MACH_TEGRA_POWERGATE_H_ */ 86#endif /* _MACH_TEGRA_POWERGATE_H_ */
diff --git a/include/linux/tracepoint.h b/include/linux/tracepoint.h
index ebeab360d851..f16dc0a40049 100644
--- a/include/linux/tracepoint.h
+++ b/include/linux/tracepoint.h
@@ -267,6 +267,8 @@ static inline void tracepoint_synchronize_unregister(void)
267 267
268#define TRACE_EVENT_FLAGS(event, flag) 268#define TRACE_EVENT_FLAGS(event, flag)
269 269
270#define TRACE_EVENT_PERF_PERM(event, expr...)
271
270#endif /* DECLARE_TRACE */ 272#endif /* DECLARE_TRACE */
271 273
272#ifndef TRACE_EVENT 274#ifndef TRACE_EVENT
@@ -399,4 +401,6 @@ static inline void tracepoint_synchronize_unregister(void)
399 401
400#define TRACE_EVENT_FLAGS(event, flag) 402#define TRACE_EVENT_FLAGS(event, flag)
401 403
404#define TRACE_EVENT_PERF_PERM(event, expr...)
405
402#endif /* ifdef TRACE_EVENT (see note above) */ 406#endif /* ifdef TRACE_EVENT (see note above) */
diff --git a/include/net/ip.h b/include/net/ip.h
index 217bc5bfc6c6..5a25f36fe3a7 100644
--- a/include/net/ip.h
+++ b/include/net/ip.h
@@ -473,7 +473,7 @@ int compat_ip_getsockopt(struct sock *sk, int level, int optname,
473int ip_ra_control(struct sock *sk, unsigned char on, 473int ip_ra_control(struct sock *sk, unsigned char on,
474 void (*destructor)(struct sock *)); 474 void (*destructor)(struct sock *));
475 475
476int ip_recv_error(struct sock *sk, struct msghdr *msg, int len); 476int ip_recv_error(struct sock *sk, struct msghdr *msg, int len, int *addr_len);
477void ip_icmp_error(struct sock *sk, struct sk_buff *skb, int err, __be16 port, 477void ip_icmp_error(struct sock *sk, struct sk_buff *skb, int err, __be16 port,
478 u32 info, u8 *payload); 478 u32 info, u8 *payload);
479void ip_local_error(struct sock *sk, int err, __be32 daddr, __be16 dport, 479void ip_local_error(struct sock *sk, int err, __be32 daddr, __be16 dport,
diff --git a/include/net/ipv6.h b/include/net/ipv6.h
index 2a5f668cd683..eb198acaac1d 100644
--- a/include/net/ipv6.h
+++ b/include/net/ipv6.h
@@ -776,8 +776,10 @@ int compat_ipv6_getsockopt(struct sock *sk, int level, int optname,
776 776
777int ip6_datagram_connect(struct sock *sk, struct sockaddr *addr, int addr_len); 777int ip6_datagram_connect(struct sock *sk, struct sockaddr *addr, int addr_len);
778 778
779int ipv6_recv_error(struct sock *sk, struct msghdr *msg, int len); 779int ipv6_recv_error(struct sock *sk, struct msghdr *msg, int len,
780int ipv6_recv_rxpmtu(struct sock *sk, struct msghdr *msg, int len); 780 int *addr_len);
781int ipv6_recv_rxpmtu(struct sock *sk, struct msghdr *msg, int len,
782 int *addr_len);
781void ipv6_icmp_error(struct sock *sk, struct sk_buff *skb, int err, __be16 port, 783void ipv6_icmp_error(struct sock *sk, struct sk_buff *skb, int err, __be16 port,
782 u32 info, u8 *payload); 784 u32 info, u8 *payload);
783void ipv6_local_error(struct sock *sk, int err, struct flowi6 *fl6, u32 info); 785void ipv6_local_error(struct sock *sk, int err, struct flowi6 *fl6, u32 info);
diff --git a/include/net/ping.h b/include/net/ping.h
index 3f67704f3747..90f48417b03d 100644
--- a/include/net/ping.h
+++ b/include/net/ping.h
@@ -31,7 +31,8 @@
31 31
32/* Compatibility glue so we can support IPv6 when it's compiled as a module */ 32/* Compatibility glue so we can support IPv6 when it's compiled as a module */
33struct pingv6_ops { 33struct pingv6_ops {
34 int (*ipv6_recv_error)(struct sock *sk, struct msghdr *msg, int len); 34 int (*ipv6_recv_error)(struct sock *sk, struct msghdr *msg, int len,
35 int *addr_len);
35 int (*ip6_datagram_recv_ctl)(struct sock *sk, struct msghdr *msg, 36 int (*ip6_datagram_recv_ctl)(struct sock *sk, struct msghdr *msg,
36 struct sk_buff *skb); 37 struct sk_buff *skb);
37 int (*icmpv6_err_convert)(u8 type, u8 code, int *err); 38 int (*icmpv6_err_convert)(u8 type, u8 code, int *err);
diff --git a/include/net/sctp/structs.h b/include/net/sctp/structs.h
index 2174d8da0770..ea0ca5f6e629 100644
--- a/include/net/sctp/structs.h
+++ b/include/net/sctp/structs.h
@@ -629,6 +629,7 @@ struct sctp_chunk {
629#define SCTP_NEED_FRTX 0x1 629#define SCTP_NEED_FRTX 0x1
630#define SCTP_DONT_FRTX 0x2 630#define SCTP_DONT_FRTX 0x2
631 __u16 rtt_in_progress:1, /* This chunk used for RTT calc? */ 631 __u16 rtt_in_progress:1, /* This chunk used for RTT calc? */
632 resent:1, /* Has this chunk ever been resent. */
632 has_tsn:1, /* Does this chunk have a TSN yet? */ 633 has_tsn:1, /* Does this chunk have a TSN yet? */
633 has_ssn:1, /* Does this chunk have a SSN yet? */ 634 has_ssn:1, /* Does this chunk have a SSN yet? */
634 singleton:1, /* Only chunk in the packet? */ 635 singleton:1, /* Only chunk in the packet? */
diff --git a/include/scsi/scsi_host.h b/include/scsi/scsi_host.h
index 546084964d55..fe3b58e836c8 100644
--- a/include/scsi/scsi_host.h
+++ b/include/scsi/scsi_host.h
@@ -475,6 +475,9 @@ struct scsi_host_template {
475 */ 475 */
476 unsigned ordered_tag:1; 476 unsigned ordered_tag:1;
477 477
478 /* True if the controller does not support WRITE SAME */
479 unsigned no_write_same:1;
480
478 /* 481 /*
479 * Countdown for host blocking with no commands outstanding. 482 * Countdown for host blocking with no commands outstanding.
480 */ 483 */
@@ -677,6 +680,9 @@ struct Scsi_Host {
677 /* Don't resume host in EH */ 680 /* Don't resume host in EH */
678 unsigned eh_noresume:1; 681 unsigned eh_noresume:1;
679 682
683 /* The controller does not support WRITE SAME */
684 unsigned no_write_same:1;
685
680 /* 686 /*
681 * Optional work queue to be utilized by the transport 687 * Optional work queue to be utilized by the transport
682 */ 688 */
diff --git a/include/sound/dmaengine_pcm.h b/include/sound/dmaengine_pcm.h
index 15017311f2e9..eb73a3a39ec2 100644
--- a/include/sound/dmaengine_pcm.h
+++ b/include/sound/dmaengine_pcm.h
@@ -114,6 +114,10 @@ void snd_dmaengine_pcm_set_config_from_dai_data(
114 * @compat_filter_fn: Will be used as the filter function when requesting a 114 * @compat_filter_fn: Will be used as the filter function when requesting a
115 * channel for platforms which do not use devicetree. The filter parameter 115 * channel for platforms which do not use devicetree. The filter parameter
116 * will be the DAI's DMA data. 116 * will be the DAI's DMA data.
117 * @dma_dev: If set, request DMA channel on this device rather than the DAI
118 * device.
119 * @chan_names: If set, these custom DMA channel names will be requested at
120 * registration time.
117 * @pcm_hardware: snd_pcm_hardware struct to be used for the PCM. 121 * @pcm_hardware: snd_pcm_hardware struct to be used for the PCM.
118 * @prealloc_buffer_size: Size of the preallocated audio buffer. 122 * @prealloc_buffer_size: Size of the preallocated audio buffer.
119 * 123 *
@@ -130,6 +134,8 @@ struct snd_dmaengine_pcm_config {
130 struct snd_soc_pcm_runtime *rtd, 134 struct snd_soc_pcm_runtime *rtd,
131 struct snd_pcm_substream *substream); 135 struct snd_pcm_substream *substream);
132 dma_filter_fn compat_filter_fn; 136 dma_filter_fn compat_filter_fn;
137 struct device *dma_dev;
138 const char *chan_names[SNDRV_PCM_STREAM_LAST + 1];
133 139
134 const struct snd_pcm_hardware *pcm_hardware; 140 const struct snd_pcm_hardware *pcm_hardware;
135 unsigned int prealloc_buffer_size; 141 unsigned int prealloc_buffer_size;
@@ -140,6 +146,10 @@ int snd_dmaengine_pcm_register(struct device *dev,
140 unsigned int flags); 146 unsigned int flags);
141void snd_dmaengine_pcm_unregister(struct device *dev); 147void snd_dmaengine_pcm_unregister(struct device *dev);
142 148
149int devm_snd_dmaengine_pcm_register(struct device *dev,
150 const struct snd_dmaengine_pcm_config *config,
151 unsigned int flags);
152
143int snd_dmaengine_pcm_prepare_slave_config(struct snd_pcm_substream *substream, 153int snd_dmaengine_pcm_prepare_slave_config(struct snd_pcm_substream *substream,
144 struct snd_pcm_hw_params *params, 154 struct snd_pcm_hw_params *params,
145 struct dma_slave_config *slave_config); 155 struct dma_slave_config *slave_config);
diff --git a/include/sound/soc-dapm.h b/include/sound/soc-dapm.h
index 2037c45adfe6..56ebdfca6273 100644
--- a/include/sound/soc-dapm.h
+++ b/include/sound/soc-dapm.h
@@ -104,7 +104,8 @@ struct device;
104 SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ 104 SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \
105 .kcontrol_news = wcontrols, .num_kcontrols = 1} 105 .kcontrol_news = wcontrols, .num_kcontrols = 1}
106#define SND_SOC_DAPM_MUX(wname, wreg, wshift, winvert, wcontrols) \ 106#define SND_SOC_DAPM_MUX(wname, wreg, wshift, winvert, wcontrols) \
107{ .id = snd_soc_dapm_mux, .name = wname, .reg = wreg, \ 107{ .id = snd_soc_dapm_mux, .name = wname, \
108 SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \
108 .kcontrol_news = wcontrols, .num_kcontrols = 1} 109 .kcontrol_news = wcontrols, .num_kcontrols = 1}
109#define SND_SOC_DAPM_VIRT_MUX(wname, wreg, wshift, winvert, wcontrols) \ 110#define SND_SOC_DAPM_VIRT_MUX(wname, wreg, wshift, winvert, wcontrols) \
110{ .id = snd_soc_dapm_virt_mux, .name = wname, \ 111{ .id = snd_soc_dapm_virt_mux, .name = wname, \
diff --git a/include/trace/ftrace.h b/include/trace/ftrace.h
index 52594b20179e..5c38606613d8 100644
--- a/include/trace/ftrace.h
+++ b/include/trace/ftrace.h
@@ -90,6 +90,10 @@
90#define TRACE_EVENT_FLAGS(name, value) \ 90#define TRACE_EVENT_FLAGS(name, value) \
91 __TRACE_EVENT_FLAGS(name, value) 91 __TRACE_EVENT_FLAGS(name, value)
92 92
93#undef TRACE_EVENT_PERF_PERM
94#define TRACE_EVENT_PERF_PERM(name, expr...) \
95 __TRACE_EVENT_PERF_PERM(name, expr)
96
93#include TRACE_INCLUDE(TRACE_INCLUDE_FILE) 97#include TRACE_INCLUDE(TRACE_INCLUDE_FILE)
94 98
95 99
@@ -140,6 +144,9 @@
140#undef TRACE_EVENT_FLAGS 144#undef TRACE_EVENT_FLAGS
141#define TRACE_EVENT_FLAGS(event, flag) 145#define TRACE_EVENT_FLAGS(event, flag)
142 146
147#undef TRACE_EVENT_PERF_PERM
148#define TRACE_EVENT_PERF_PERM(event, expr...)
149
143#include TRACE_INCLUDE(TRACE_INCLUDE_FILE) 150#include TRACE_INCLUDE(TRACE_INCLUDE_FILE)
144 151
145/* 152/*
@@ -372,7 +379,8 @@ ftrace_define_fields_##call(struct ftrace_event_call *event_call) \
372 __data_size += (len) * sizeof(type); 379 __data_size += (len) * sizeof(type);
373 380
374#undef __string 381#undef __string
375#define __string(item, src) __dynamic_array(char, item, strlen(src) + 1) 382#define __string(item, src) __dynamic_array(char, item, \
383 strlen((src) ? (const char *)(src) : "(null)") + 1)
376 384
377#undef DECLARE_EVENT_CLASS 385#undef DECLARE_EVENT_CLASS
378#define DECLARE_EVENT_CLASS(call, proto, args, tstruct, assign, print) \ 386#define DECLARE_EVENT_CLASS(call, proto, args, tstruct, assign, print) \
@@ -501,7 +509,7 @@ static inline notrace int ftrace_get_offsets_##call( \
501 509
502#undef __assign_str 510#undef __assign_str
503#define __assign_str(dst, src) \ 511#define __assign_str(dst, src) \
504 strcpy(__get_str(dst), src); 512 strcpy(__get_str(dst), (src) ? (const char *)(src) : "(null)");
505 513
506#undef TP_fast_assign 514#undef TP_fast_assign
507#define TP_fast_assign(args...) args 515#define TP_fast_assign(args...) args
diff --git a/include/uapi/linux/eventpoll.h b/include/uapi/linux/eventpoll.h
index 2c267bcbb85c..bc81fb2e1f0e 100644
--- a/include/uapi/linux/eventpoll.h
+++ b/include/uapi/linux/eventpoll.h
@@ -61,5 +61,16 @@ struct epoll_event {
61 __u64 data; 61 __u64 data;
62} EPOLL_PACKED; 62} EPOLL_PACKED;
63 63
64 64#ifdef CONFIG_PM_SLEEP
65static inline void ep_take_care_of_epollwakeup(struct epoll_event *epev)
66{
67 if ((epev->events & EPOLLWAKEUP) && !capable(CAP_BLOCK_SUSPEND))
68 epev->events &= ~EPOLLWAKEUP;
69}
70#else
71static inline void ep_take_care_of_epollwakeup(struct epoll_event *epev)
72{
73 epev->events &= ~EPOLLWAKEUP;
74}
75#endif
65#endif /* _UAPI_LINUX_EVENTPOLL_H */ 76#endif /* _UAPI_LINUX_EVENTPOLL_H */
diff --git a/include/uapi/linux/genetlink.h b/include/uapi/linux/genetlink.h
index 1af72d8228e0..c3363ba1ae05 100644
--- a/include/uapi/linux/genetlink.h
+++ b/include/uapi/linux/genetlink.h
@@ -28,6 +28,7 @@ struct genlmsghdr {
28#define GENL_ID_GENERATE 0 28#define GENL_ID_GENERATE 0
29#define GENL_ID_CTRL NLMSG_MIN_TYPE 29#define GENL_ID_CTRL NLMSG_MIN_TYPE
30#define GENL_ID_VFS_DQUOT (NLMSG_MIN_TYPE + 1) 30#define GENL_ID_VFS_DQUOT (NLMSG_MIN_TYPE + 1)
31#define GENL_ID_PMCRAID (NLMSG_MIN_TYPE + 2)
31 32
32/************************************************************************** 33/**************************************************************************
33 * Controller 34 * Controller
diff --git a/include/uapi/linux/if_link.h b/include/uapi/linux/if_link.h
index b78566f59aba..6db460121f84 100644
--- a/include/uapi/linux/if_link.h
+++ b/include/uapi/linux/if_link.h
@@ -488,7 +488,9 @@ enum {
488 IFLA_HSR_UNSPEC, 488 IFLA_HSR_UNSPEC,
489 IFLA_HSR_SLAVE1, 489 IFLA_HSR_SLAVE1,
490 IFLA_HSR_SLAVE2, 490 IFLA_HSR_SLAVE2,
491 IFLA_HSR_MULTICAST_SPEC, 491 IFLA_HSR_MULTICAST_SPEC, /* Last byte of supervision addr */
492 IFLA_HSR_SUPERVISION_ADDR, /* Supervision frame multicast addr */
493 IFLA_HSR_SEQ_NR,
492 __IFLA_HSR_MAX, 494 __IFLA_HSR_MAX,
493}; 495};
494 496
diff --git a/include/uapi/linux/netlink_diag.h b/include/uapi/linux/netlink_diag.h
index 4e31db4eea41..f2159d30d1f5 100644
--- a/include/uapi/linux/netlink_diag.h
+++ b/include/uapi/linux/netlink_diag.h
@@ -33,6 +33,7 @@ struct netlink_diag_ring {
33}; 33};
34 34
35enum { 35enum {
36 /* NETLINK_DIAG_NONE, standard nl API requires this attribute! */
36 NETLINK_DIAG_MEMINFO, 37 NETLINK_DIAG_MEMINFO,
37 NETLINK_DIAG_GROUPS, 38 NETLINK_DIAG_GROUPS,
38 NETLINK_DIAG_RX_RING, 39 NETLINK_DIAG_RX_RING,
diff --git a/include/uapi/linux/packet_diag.h b/include/uapi/linux/packet_diag.h
index b2cc0cd9c4d9..d08c63f3dd6f 100644
--- a/include/uapi/linux/packet_diag.h
+++ b/include/uapi/linux/packet_diag.h
@@ -29,6 +29,7 @@ struct packet_diag_msg {
29}; 29};
30 30
31enum { 31enum {
32 /* PACKET_DIAG_NONE, standard nl API requires this attribute! */
32 PACKET_DIAG_INFO, 33 PACKET_DIAG_INFO,
33 PACKET_DIAG_MCLIST, 34 PACKET_DIAG_MCLIST,
34 PACKET_DIAG_RX_RING, 35 PACKET_DIAG_RX_RING,
diff --git a/include/uapi/linux/unix_diag.h b/include/uapi/linux/unix_diag.h
index b9e2a6a7446f..1eb0b8dd1830 100644
--- a/include/uapi/linux/unix_diag.h
+++ b/include/uapi/linux/unix_diag.h
@@ -31,6 +31,7 @@ struct unix_diag_msg {
31}; 31};
32 32
33enum { 33enum {
34 /* UNIX_DIAG_NONE, standard nl API requires this attribute! */
34 UNIX_DIAG_NAME, 35 UNIX_DIAG_NAME,
35 UNIX_DIAG_VFS, 36 UNIX_DIAG_VFS,
36 UNIX_DIAG_PEER, 37 UNIX_DIAG_PEER,
diff --git a/kernel/cgroup.c b/kernel/cgroup.c
index 4c62513fe19f..8b729c278b64 100644
--- a/kernel/cgroup.c
+++ b/kernel/cgroup.c
@@ -90,6 +90,14 @@ static DEFINE_MUTEX(cgroup_mutex);
90static DEFINE_MUTEX(cgroup_root_mutex); 90static DEFINE_MUTEX(cgroup_root_mutex);
91 91
92/* 92/*
93 * cgroup destruction makes heavy use of work items and there can be a lot
94 * of concurrent destructions. Use a separate workqueue so that cgroup
95 * destruction work items don't end up filling up max_active of system_wq
96 * which may lead to deadlock.
97 */
98static struct workqueue_struct *cgroup_destroy_wq;
99
100/*
93 * Generate an array of cgroup subsystem pointers. At boot time, this is 101 * Generate an array of cgroup subsystem pointers. At boot time, this is
94 * populated with the built in subsystems, and modular subsystems are 102 * populated with the built in subsystems, and modular subsystems are
95 * registered after that. The mutable section of this array is protected by 103 * registered after that. The mutable section of this array is protected by
@@ -191,6 +199,7 @@ static void cgroup_destroy_css_killed(struct cgroup *cgrp);
191static int cgroup_destroy_locked(struct cgroup *cgrp); 199static int cgroup_destroy_locked(struct cgroup *cgrp);
192static int cgroup_addrm_files(struct cgroup *cgrp, struct cftype cfts[], 200static int cgroup_addrm_files(struct cgroup *cgrp, struct cftype cfts[],
193 bool is_add); 201 bool is_add);
202static int cgroup_file_release(struct inode *inode, struct file *file);
194 203
195/** 204/**
196 * cgroup_css - obtain a cgroup's css for the specified subsystem 205 * cgroup_css - obtain a cgroup's css for the specified subsystem
@@ -871,7 +880,7 @@ static void cgroup_free_rcu(struct rcu_head *head)
871 struct cgroup *cgrp = container_of(head, struct cgroup, rcu_head); 880 struct cgroup *cgrp = container_of(head, struct cgroup, rcu_head);
872 881
873 INIT_WORK(&cgrp->destroy_work, cgroup_free_fn); 882 INIT_WORK(&cgrp->destroy_work, cgroup_free_fn);
874 schedule_work(&cgrp->destroy_work); 883 queue_work(cgroup_destroy_wq, &cgrp->destroy_work);
875} 884}
876 885
877static void cgroup_diput(struct dentry *dentry, struct inode *inode) 886static void cgroup_diput(struct dentry *dentry, struct inode *inode)
@@ -2421,7 +2430,7 @@ static const struct file_operations cgroup_seqfile_operations = {
2421 .read = seq_read, 2430 .read = seq_read,
2422 .write = cgroup_file_write, 2431 .write = cgroup_file_write,
2423 .llseek = seq_lseek, 2432 .llseek = seq_lseek,
2424 .release = single_release, 2433 .release = cgroup_file_release,
2425}; 2434};
2426 2435
2427static int cgroup_file_open(struct inode *inode, struct file *file) 2436static int cgroup_file_open(struct inode *inode, struct file *file)
@@ -2482,6 +2491,8 @@ static int cgroup_file_release(struct inode *inode, struct file *file)
2482 ret = cft->release(inode, file); 2491 ret = cft->release(inode, file);
2483 if (css->ss) 2492 if (css->ss)
2484 css_put(css); 2493 css_put(css);
2494 if (file->f_op == &cgroup_seqfile_operations)
2495 single_release(inode, file);
2485 return ret; 2496 return ret;
2486} 2497}
2487 2498
@@ -4249,7 +4260,7 @@ static void css_free_rcu_fn(struct rcu_head *rcu_head)
4249 * css_put(). dput() requires process context which we don't have. 4260 * css_put(). dput() requires process context which we don't have.
4250 */ 4261 */
4251 INIT_WORK(&css->destroy_work, css_free_work_fn); 4262 INIT_WORK(&css->destroy_work, css_free_work_fn);
4252 schedule_work(&css->destroy_work); 4263 queue_work(cgroup_destroy_wq, &css->destroy_work);
4253} 4264}
4254 4265
4255static void css_release(struct percpu_ref *ref) 4266static void css_release(struct percpu_ref *ref)
@@ -4539,7 +4550,7 @@ static void css_killed_ref_fn(struct percpu_ref *ref)
4539 container_of(ref, struct cgroup_subsys_state, refcnt); 4550 container_of(ref, struct cgroup_subsys_state, refcnt);
4540 4551
4541 INIT_WORK(&css->destroy_work, css_killed_work_fn); 4552 INIT_WORK(&css->destroy_work, css_killed_work_fn);
4542 schedule_work(&css->destroy_work); 4553 queue_work(cgroup_destroy_wq, &css->destroy_work);
4543} 4554}
4544 4555
4545/** 4556/**
@@ -5063,6 +5074,22 @@ out:
5063 return err; 5074 return err;
5064} 5075}
5065 5076
5077static int __init cgroup_wq_init(void)
5078{
5079 /*
5080 * There isn't much point in executing destruction path in
5081 * parallel. Good chunk is serialized with cgroup_mutex anyway.
5082 * Use 1 for @max_active.
5083 *
5084 * We would prefer to do this in cgroup_init() above, but that
5085 * is called before init_workqueues(): so leave this until after.
5086 */
5087 cgroup_destroy_wq = alloc_workqueue("cgroup_destroy", 0, 1);
5088 BUG_ON(!cgroup_destroy_wq);
5089 return 0;
5090}
5091core_initcall(cgroup_wq_init);
5092
5066/* 5093/*
5067 * proc_cgroup_show() 5094 * proc_cgroup_show()
5068 * - Print task's cgroup paths into seq_file, one line for each hierarchy 5095 * - Print task's cgroup paths into seq_file, one line for each hierarchy
diff --git a/kernel/cpuset.c b/kernel/cpuset.c
index 6bf981e13c43..4772034b4b17 100644
--- a/kernel/cpuset.c
+++ b/kernel/cpuset.c
@@ -1033,8 +1033,10 @@ static void cpuset_change_task_nodemask(struct task_struct *tsk,
1033 need_loop = task_has_mempolicy(tsk) || 1033 need_loop = task_has_mempolicy(tsk) ||
1034 !nodes_intersects(*newmems, tsk->mems_allowed); 1034 !nodes_intersects(*newmems, tsk->mems_allowed);
1035 1035
1036 if (need_loop) 1036 if (need_loop) {
1037 local_irq_disable();
1037 write_seqcount_begin(&tsk->mems_allowed_seq); 1038 write_seqcount_begin(&tsk->mems_allowed_seq);
1039 }
1038 1040
1039 nodes_or(tsk->mems_allowed, tsk->mems_allowed, *newmems); 1041 nodes_or(tsk->mems_allowed, tsk->mems_allowed, *newmems);
1040 mpol_rebind_task(tsk, newmems, MPOL_REBIND_STEP1); 1042 mpol_rebind_task(tsk, newmems, MPOL_REBIND_STEP1);
@@ -1042,8 +1044,10 @@ static void cpuset_change_task_nodemask(struct task_struct *tsk,
1042 mpol_rebind_task(tsk, newmems, MPOL_REBIND_STEP2); 1044 mpol_rebind_task(tsk, newmems, MPOL_REBIND_STEP2);
1043 tsk->mems_allowed = *newmems; 1045 tsk->mems_allowed = *newmems;
1044 1046
1045 if (need_loop) 1047 if (need_loop) {
1046 write_seqcount_end(&tsk->mems_allowed_seq); 1048 write_seqcount_end(&tsk->mems_allowed_seq);
1049 local_irq_enable();
1050 }
1047 1051
1048 task_unlock(tsk); 1052 task_unlock(tsk);
1049} 1053}
diff --git a/kernel/events/core.c b/kernel/events/core.c
index d724e7757cd1..72348dc192c1 100644
--- a/kernel/events/core.c
+++ b/kernel/events/core.c
@@ -5680,11 +5680,6 @@ static void swevent_hlist_put(struct perf_event *event)
5680{ 5680{
5681 int cpu; 5681 int cpu;
5682 5682
5683 if (event->cpu != -1) {
5684 swevent_hlist_put_cpu(event, event->cpu);
5685 return;
5686 }
5687
5688 for_each_possible_cpu(cpu) 5683 for_each_possible_cpu(cpu)
5689 swevent_hlist_put_cpu(event, cpu); 5684 swevent_hlist_put_cpu(event, cpu);
5690} 5685}
@@ -5718,9 +5713,6 @@ static int swevent_hlist_get(struct perf_event *event)
5718 int err; 5713 int err;
5719 int cpu, failed_cpu; 5714 int cpu, failed_cpu;
5720 5715
5721 if (event->cpu != -1)
5722 return swevent_hlist_get_cpu(event, event->cpu);
5723
5724 get_online_cpus(); 5716 get_online_cpus();
5725 for_each_possible_cpu(cpu) { 5717 for_each_possible_cpu(cpu) {
5726 err = swevent_hlist_get_cpu(event, cpu); 5718 err = swevent_hlist_get_cpu(event, cpu);
diff --git a/kernel/extable.c b/kernel/extable.c
index 832cb28105bb..763faf037ec1 100644
--- a/kernel/extable.c
+++ b/kernel/extable.c
@@ -61,7 +61,7 @@ const struct exception_table_entry *search_exception_tables(unsigned long addr)
61static inline int init_kernel_text(unsigned long addr) 61static inline int init_kernel_text(unsigned long addr)
62{ 62{
63 if (addr >= (unsigned long)_sinittext && 63 if (addr >= (unsigned long)_sinittext &&
64 addr <= (unsigned long)_einittext) 64 addr < (unsigned long)_einittext)
65 return 1; 65 return 1;
66 return 0; 66 return 0;
67} 67}
@@ -69,7 +69,7 @@ static inline int init_kernel_text(unsigned long addr)
69int core_kernel_text(unsigned long addr) 69int core_kernel_text(unsigned long addr)
70{ 70{
71 if (addr >= (unsigned long)_stext && 71 if (addr >= (unsigned long)_stext &&
72 addr <= (unsigned long)_etext) 72 addr < (unsigned long)_etext)
73 return 1; 73 return 1;
74 74
75 if (system_state == SYSTEM_BOOTING && 75 if (system_state == SYSTEM_BOOTING &&
diff --git a/kernel/irq/pm.c b/kernel/irq/pm.c
index cb228bf21760..abcd6ca86cb7 100644
--- a/kernel/irq/pm.c
+++ b/kernel/irq/pm.c
@@ -50,7 +50,7 @@ static void resume_irqs(bool want_early)
50 bool is_early = desc->action && 50 bool is_early = desc->action &&
51 desc->action->flags & IRQF_EARLY_RESUME; 51 desc->action->flags & IRQF_EARLY_RESUME;
52 52
53 if (is_early != want_early) 53 if (!is_early && want_early)
54 continue; 54 continue;
55 55
56 raw_spin_lock_irqsave(&desc->lock, flags); 56 raw_spin_lock_irqsave(&desc->lock, flags);
diff --git a/kernel/padata.c b/kernel/padata.c
index 07af2c95dcfe..2abd25d79cc8 100644
--- a/kernel/padata.c
+++ b/kernel/padata.c
@@ -46,6 +46,7 @@ static int padata_index_to_cpu(struct parallel_data *pd, int cpu_index)
46 46
47static int padata_cpu_hash(struct parallel_data *pd) 47static int padata_cpu_hash(struct parallel_data *pd)
48{ 48{
49 unsigned int seq_nr;
49 int cpu_index; 50 int cpu_index;
50 51
51 /* 52 /*
@@ -53,10 +54,8 @@ static int padata_cpu_hash(struct parallel_data *pd)
53 * seq_nr mod. number of cpus in use. 54 * seq_nr mod. number of cpus in use.
54 */ 55 */
55 56
56 spin_lock(&pd->seq_lock); 57 seq_nr = atomic_inc_return(&pd->seq_nr);
57 cpu_index = pd->seq_nr % cpumask_weight(pd->cpumask.pcpu); 58 cpu_index = seq_nr % cpumask_weight(pd->cpumask.pcpu);
58 pd->seq_nr++;
59 spin_unlock(&pd->seq_lock);
60 59
61 return padata_index_to_cpu(pd, cpu_index); 60 return padata_index_to_cpu(pd, cpu_index);
62} 61}
@@ -429,7 +428,7 @@ static struct parallel_data *padata_alloc_pd(struct padata_instance *pinst,
429 padata_init_pqueues(pd); 428 padata_init_pqueues(pd);
430 padata_init_squeues(pd); 429 padata_init_squeues(pd);
431 setup_timer(&pd->timer, padata_reorder_timer, (unsigned long)pd); 430 setup_timer(&pd->timer, padata_reorder_timer, (unsigned long)pd);
432 pd->seq_nr = 0; 431 atomic_set(&pd->seq_nr, -1);
433 atomic_set(&pd->reorder_objects, 0); 432 atomic_set(&pd->reorder_objects, 0);
434 atomic_set(&pd->refcnt, 0); 433 atomic_set(&pd->refcnt, 0);
435 pd->pinst = pinst; 434 pd->pinst = pinst;
diff --git a/kernel/rcu/tree_plugin.h b/kernel/rcu/tree_plugin.h
index 6abb03dff5c0..08a765232432 100644
--- a/kernel/rcu/tree_plugin.h
+++ b/kernel/rcu/tree_plugin.h
@@ -1632,7 +1632,7 @@ module_param(rcu_idle_gp_delay, int, 0644);
1632static int rcu_idle_lazy_gp_delay = RCU_IDLE_LAZY_GP_DELAY; 1632static int rcu_idle_lazy_gp_delay = RCU_IDLE_LAZY_GP_DELAY;
1633module_param(rcu_idle_lazy_gp_delay, int, 0644); 1633module_param(rcu_idle_lazy_gp_delay, int, 0644);
1634 1634
1635extern int tick_nohz_enabled; 1635extern int tick_nohz_active;
1636 1636
1637/* 1637/*
1638 * Try to advance callbacks for all flavors of RCU on the current CPU, but 1638 * Try to advance callbacks for all flavors of RCU on the current CPU, but
@@ -1729,7 +1729,7 @@ static void rcu_prepare_for_idle(int cpu)
1729 int tne; 1729 int tne;
1730 1730
1731 /* Handle nohz enablement switches conservatively. */ 1731 /* Handle nohz enablement switches conservatively. */
1732 tne = ACCESS_ONCE(tick_nohz_enabled); 1732 tne = ACCESS_ONCE(tick_nohz_active);
1733 if (tne != rdtp->tick_nohz_enabled_snap) { 1733 if (tne != rdtp->tick_nohz_enabled_snap) {
1734 if (rcu_cpu_has_callbacks(cpu, NULL)) 1734 if (rcu_cpu_has_callbacks(cpu, NULL))
1735 invoke_rcu_core(); /* force nohz to see update. */ 1735 invoke_rcu_core(); /* force nohz to see update. */
diff --git a/kernel/sched/core.c b/kernel/sched/core.c
index c1808606ee5f..e85cda20ab2b 100644
--- a/kernel/sched/core.c
+++ b/kernel/sched/core.c
@@ -2660,6 +2660,7 @@ asmlinkage void __sched notrace preempt_schedule(void)
2660 } while (need_resched()); 2660 } while (need_resched());
2661} 2661}
2662EXPORT_SYMBOL(preempt_schedule); 2662EXPORT_SYMBOL(preempt_schedule);
2663#endif /* CONFIG_PREEMPT */
2663 2664
2664/* 2665/*
2665 * this is the entry point to schedule() from kernel preemption 2666 * this is the entry point to schedule() from kernel preemption
@@ -2693,8 +2694,6 @@ asmlinkage void __sched preempt_schedule_irq(void)
2693 exception_exit(prev_state); 2694 exception_exit(prev_state);
2694} 2695}
2695 2696
2696#endif /* CONFIG_PREEMPT */
2697
2698int default_wake_function(wait_queue_t *curr, unsigned mode, int wake_flags, 2697int default_wake_function(wait_queue_t *curr, unsigned mode, int wake_flags,
2699 void *key) 2698 void *key)
2700{ 2699{
@@ -4762,7 +4761,7 @@ static void rq_attach_root(struct rq *rq, struct root_domain *rd)
4762 cpumask_clear_cpu(rq->cpu, old_rd->span); 4761 cpumask_clear_cpu(rq->cpu, old_rd->span);
4763 4762
4764 /* 4763 /*
4765 * If we dont want to free the old_rt yet then 4764 * If we dont want to free the old_rd yet then
4766 * set old_rd to NULL to skip the freeing later 4765 * set old_rd to NULL to skip the freeing later
4767 * in this function: 4766 * in this function:
4768 */ 4767 */
@@ -4910,8 +4909,9 @@ static void update_top_cache_domain(int cpu)
4910 if (sd) { 4909 if (sd) {
4911 id = cpumask_first(sched_domain_span(sd)); 4910 id = cpumask_first(sched_domain_span(sd));
4912 size = cpumask_weight(sched_domain_span(sd)); 4911 size = cpumask_weight(sched_domain_span(sd));
4913 rcu_assign_pointer(per_cpu(sd_busy, cpu), sd->parent); 4912 sd = sd->parent; /* sd_busy */
4914 } 4913 }
4914 rcu_assign_pointer(per_cpu(sd_busy, cpu), sd);
4915 4915
4916 rcu_assign_pointer(per_cpu(sd_llc, cpu), sd); 4916 rcu_assign_pointer(per_cpu(sd_llc, cpu), sd);
4917 per_cpu(sd_llc_size, cpu) = size; 4917 per_cpu(sd_llc_size, cpu) = size;
diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c
index e8b652ebe027..fd773ade1a31 100644
--- a/kernel/sched/fair.c
+++ b/kernel/sched/fair.c
@@ -5379,10 +5379,31 @@ void update_group_power(struct sched_domain *sd, int cpu)
5379 */ 5379 */
5380 5380
5381 for_each_cpu(cpu, sched_group_cpus(sdg)) { 5381 for_each_cpu(cpu, sched_group_cpus(sdg)) {
5382 struct sched_group *sg = cpu_rq(cpu)->sd->groups; 5382 struct sched_group_power *sgp;
5383 struct rq *rq = cpu_rq(cpu);
5383 5384
5384 power_orig += sg->sgp->power_orig; 5385 /*
5385 power += sg->sgp->power; 5386 * build_sched_domains() -> init_sched_groups_power()
5387 * gets here before we've attached the domains to the
5388 * runqueues.
5389 *
5390 * Use power_of(), which is set irrespective of domains
5391 * in update_cpu_power().
5392 *
5393 * This avoids power/power_orig from being 0 and
5394 * causing divide-by-zero issues on boot.
5395 *
5396 * Runtime updates will correct power_orig.
5397 */
5398 if (unlikely(!rq->sd)) {
5399 power_orig += power_of(cpu);
5400 power += power_of(cpu);
5401 continue;
5402 }
5403
5404 sgp = rq->sd->groups->sgp;
5405 power_orig += sgp->power_orig;
5406 power += sgp->power;
5386 } 5407 }
5387 } else { 5408 } else {
5388 /* 5409 /*
diff --git a/kernel/time/tick-common.c b/kernel/time/tick-common.c
index 64522ecdfe0e..162b03ab0ad2 100644
--- a/kernel/time/tick-common.c
+++ b/kernel/time/tick-common.c
@@ -33,6 +33,21 @@ DEFINE_PER_CPU(struct tick_device, tick_cpu_device);
33 */ 33 */
34ktime_t tick_next_period; 34ktime_t tick_next_period;
35ktime_t tick_period; 35ktime_t tick_period;
36
37/*
38 * tick_do_timer_cpu is a timer core internal variable which holds the CPU NR
39 * which is responsible for calling do_timer(), i.e. the timekeeping stuff. This
40 * variable has two functions:
41 *
42 * 1) Prevent a thundering herd issue of a gazillion of CPUs trying to grab the
43 * timekeeping lock all at once. Only the CPU which is assigned to do the
44 * update is handling it.
45 *
46 * 2) Hand off the duty in the NOHZ idle case by setting the value to
47 * TICK_DO_TIMER_NONE, i.e. a non existing CPU. So the next cpu which looks
48 * at it will take over and keep the time keeping alive. The handover
49 * procedure also covers cpu hotplug.
50 */
36int tick_do_timer_cpu __read_mostly = TICK_DO_TIMER_BOOT; 51int tick_do_timer_cpu __read_mostly = TICK_DO_TIMER_BOOT;
37 52
38/* 53/*
diff --git a/kernel/time/tick-sched.c b/kernel/time/tick-sched.c
index 3612fc77f834..ea20f7d1ac2c 100644
--- a/kernel/time/tick-sched.c
+++ b/kernel/time/tick-sched.c
@@ -361,8 +361,8 @@ void __init tick_nohz_init(void)
361/* 361/*
362 * NO HZ enabled ? 362 * NO HZ enabled ?
363 */ 363 */
364int tick_nohz_enabled __read_mostly = 1; 364static int tick_nohz_enabled __read_mostly = 1;
365 365int tick_nohz_active __read_mostly;
366/* 366/*
367 * Enable / Disable tickless mode 367 * Enable / Disable tickless mode
368 */ 368 */
@@ -465,7 +465,7 @@ u64 get_cpu_idle_time_us(int cpu, u64 *last_update_time)
465 struct tick_sched *ts = &per_cpu(tick_cpu_sched, cpu); 465 struct tick_sched *ts = &per_cpu(tick_cpu_sched, cpu);
466 ktime_t now, idle; 466 ktime_t now, idle;
467 467
468 if (!tick_nohz_enabled) 468 if (!tick_nohz_active)
469 return -1; 469 return -1;
470 470
471 now = ktime_get(); 471 now = ktime_get();
@@ -506,7 +506,7 @@ u64 get_cpu_iowait_time_us(int cpu, u64 *last_update_time)
506 struct tick_sched *ts = &per_cpu(tick_cpu_sched, cpu); 506 struct tick_sched *ts = &per_cpu(tick_cpu_sched, cpu);
507 ktime_t now, iowait; 507 ktime_t now, iowait;
508 508
509 if (!tick_nohz_enabled) 509 if (!tick_nohz_active)
510 return -1; 510 return -1;
511 511
512 now = ktime_get(); 512 now = ktime_get();
@@ -711,8 +711,10 @@ static bool can_stop_idle_tick(int cpu, struct tick_sched *ts)
711 return false; 711 return false;
712 } 712 }
713 713
714 if (unlikely(ts->nohz_mode == NOHZ_MODE_INACTIVE)) 714 if (unlikely(ts->nohz_mode == NOHZ_MODE_INACTIVE)) {
715 ts->sleep_length = (ktime_t) { .tv64 = NSEC_PER_SEC/HZ };
715 return false; 716 return false;
717 }
716 718
717 if (need_resched()) 719 if (need_resched())
718 return false; 720 return false;
@@ -799,11 +801,6 @@ void tick_nohz_idle_enter(void)
799 local_irq_disable(); 801 local_irq_disable();
800 802
801 ts = &__get_cpu_var(tick_cpu_sched); 803 ts = &__get_cpu_var(tick_cpu_sched);
802 /*
803 * set ts->inidle unconditionally. even if the system did not
804 * switch to nohz mode the cpu frequency governers rely on the
805 * update of the idle time accounting in tick_nohz_start_idle().
806 */
807 ts->inidle = 1; 804 ts->inidle = 1;
808 __tick_nohz_idle_enter(ts); 805 __tick_nohz_idle_enter(ts);
809 806
@@ -973,7 +970,7 @@ static void tick_nohz_switch_to_nohz(void)
973 struct tick_sched *ts = &__get_cpu_var(tick_cpu_sched); 970 struct tick_sched *ts = &__get_cpu_var(tick_cpu_sched);
974 ktime_t next; 971 ktime_t next;
975 972
976 if (!tick_nohz_enabled) 973 if (!tick_nohz_active)
977 return; 974 return;
978 975
979 local_irq_disable(); 976 local_irq_disable();
@@ -981,7 +978,7 @@ static void tick_nohz_switch_to_nohz(void)
981 local_irq_enable(); 978 local_irq_enable();
982 return; 979 return;
983 } 980 }
984 981 tick_nohz_active = 1;
985 ts->nohz_mode = NOHZ_MODE_LOWRES; 982 ts->nohz_mode = NOHZ_MODE_LOWRES;
986 983
987 /* 984 /*
@@ -1139,8 +1136,10 @@ void tick_setup_sched_timer(void)
1139 } 1136 }
1140 1137
1141#ifdef CONFIG_NO_HZ_COMMON 1138#ifdef CONFIG_NO_HZ_COMMON
1142 if (tick_nohz_enabled) 1139 if (tick_nohz_enabled) {
1143 ts->nohz_mode = NOHZ_MODE_HIGHRES; 1140 ts->nohz_mode = NOHZ_MODE_HIGHRES;
1141 tick_nohz_active = 1;
1142 }
1144#endif 1143#endif
1145} 1144}
1146#endif /* HIGH_RES_TIMERS */ 1145#endif /* HIGH_RES_TIMERS */
diff --git a/kernel/time/timekeeping.c b/kernel/time/timekeeping.c
index 3abf53418b67..87b4f00284c9 100644
--- a/kernel/time/timekeeping.c
+++ b/kernel/time/timekeeping.c
@@ -1347,7 +1347,7 @@ static inline void old_vsyscall_fixup(struct timekeeper *tk)
1347 tk->xtime_nsec -= remainder; 1347 tk->xtime_nsec -= remainder;
1348 tk->xtime_nsec += 1ULL << tk->shift; 1348 tk->xtime_nsec += 1ULL << tk->shift;
1349 tk->ntp_error += remainder << tk->ntp_error_shift; 1349 tk->ntp_error += remainder << tk->ntp_error_shift;
1350 1350 tk->ntp_error -= (1ULL << tk->shift) << tk->ntp_error_shift;
1351} 1351}
1352#else 1352#else
1353#define old_vsyscall_fixup(tk) 1353#define old_vsyscall_fixup(tk)
diff --git a/kernel/timer.c b/kernel/timer.c
index 6582b82fa966..accfd241b9e5 100644
--- a/kernel/timer.c
+++ b/kernel/timer.c
@@ -1518,9 +1518,8 @@ static int init_timers_cpu(int cpu)
1518 /* 1518 /*
1519 * The APs use this path later in boot 1519 * The APs use this path later in boot
1520 */ 1520 */
1521 base = kmalloc_node(sizeof(*base), 1521 base = kzalloc_node(sizeof(*base), GFP_KERNEL,
1522 GFP_KERNEL | __GFP_ZERO, 1522 cpu_to_node(cpu));
1523 cpu_to_node(cpu));
1524 if (!base) 1523 if (!base)
1525 return -ENOMEM; 1524 return -ENOMEM;
1526 1525
diff --git a/kernel/trace/ftrace.c b/kernel/trace/ftrace.c
index 22fa55696760..0e9f9eaade2f 100644
--- a/kernel/trace/ftrace.c
+++ b/kernel/trace/ftrace.c
@@ -367,9 +367,6 @@ static int remove_ftrace_list_ops(struct ftrace_ops **list,
367 367
368static int __register_ftrace_function(struct ftrace_ops *ops) 368static int __register_ftrace_function(struct ftrace_ops *ops)
369{ 369{
370 if (unlikely(ftrace_disabled))
371 return -ENODEV;
372
373 if (FTRACE_WARN_ON(ops == &global_ops)) 370 if (FTRACE_WARN_ON(ops == &global_ops))
374 return -EINVAL; 371 return -EINVAL;
375 372
@@ -428,9 +425,6 @@ static int __unregister_ftrace_function(struct ftrace_ops *ops)
428{ 425{
429 int ret; 426 int ret;
430 427
431 if (ftrace_disabled)
432 return -ENODEV;
433
434 if (WARN_ON(!(ops->flags & FTRACE_OPS_FL_ENABLED))) 428 if (WARN_ON(!(ops->flags & FTRACE_OPS_FL_ENABLED)))
435 return -EBUSY; 429 return -EBUSY;
436 430
@@ -2088,10 +2082,15 @@ static void ftrace_startup_enable(int command)
2088static int ftrace_startup(struct ftrace_ops *ops, int command) 2082static int ftrace_startup(struct ftrace_ops *ops, int command)
2089{ 2083{
2090 bool hash_enable = true; 2084 bool hash_enable = true;
2085 int ret;
2091 2086
2092 if (unlikely(ftrace_disabled)) 2087 if (unlikely(ftrace_disabled))
2093 return -ENODEV; 2088 return -ENODEV;
2094 2089
2090 ret = __register_ftrace_function(ops);
2091 if (ret)
2092 return ret;
2093
2095 ftrace_start_up++; 2094 ftrace_start_up++;
2096 command |= FTRACE_UPDATE_CALLS; 2095 command |= FTRACE_UPDATE_CALLS;
2097 2096
@@ -2113,12 +2112,17 @@ static int ftrace_startup(struct ftrace_ops *ops, int command)
2113 return 0; 2112 return 0;
2114} 2113}
2115 2114
2116static void ftrace_shutdown(struct ftrace_ops *ops, int command) 2115static int ftrace_shutdown(struct ftrace_ops *ops, int command)
2117{ 2116{
2118 bool hash_disable = true; 2117 bool hash_disable = true;
2118 int ret;
2119 2119
2120 if (unlikely(ftrace_disabled)) 2120 if (unlikely(ftrace_disabled))
2121 return; 2121 return -ENODEV;
2122
2123 ret = __unregister_ftrace_function(ops);
2124 if (ret)
2125 return ret;
2122 2126
2123 ftrace_start_up--; 2127 ftrace_start_up--;
2124 /* 2128 /*
@@ -2153,9 +2157,10 @@ static void ftrace_shutdown(struct ftrace_ops *ops, int command)
2153 } 2157 }
2154 2158
2155 if (!command || !ftrace_enabled) 2159 if (!command || !ftrace_enabled)
2156 return; 2160 return 0;
2157 2161
2158 ftrace_run_update_code(command); 2162 ftrace_run_update_code(command);
2163 return 0;
2159} 2164}
2160 2165
2161static void ftrace_startup_sysctl(void) 2166static void ftrace_startup_sysctl(void)
@@ -3060,16 +3065,13 @@ static void __enable_ftrace_function_probe(void)
3060 if (i == FTRACE_FUNC_HASHSIZE) 3065 if (i == FTRACE_FUNC_HASHSIZE)
3061 return; 3066 return;
3062 3067
3063 ret = __register_ftrace_function(&trace_probe_ops); 3068 ret = ftrace_startup(&trace_probe_ops, 0);
3064 if (!ret)
3065 ret = ftrace_startup(&trace_probe_ops, 0);
3066 3069
3067 ftrace_probe_registered = 1; 3070 ftrace_probe_registered = 1;
3068} 3071}
3069 3072
3070static void __disable_ftrace_function_probe(void) 3073static void __disable_ftrace_function_probe(void)
3071{ 3074{
3072 int ret;
3073 int i; 3075 int i;
3074 3076
3075 if (!ftrace_probe_registered) 3077 if (!ftrace_probe_registered)
@@ -3082,9 +3084,7 @@ static void __disable_ftrace_function_probe(void)
3082 } 3084 }
3083 3085
3084 /* no more funcs left */ 3086 /* no more funcs left */
3085 ret = __unregister_ftrace_function(&trace_probe_ops); 3087 ftrace_shutdown(&trace_probe_ops, 0);
3086 if (!ret)
3087 ftrace_shutdown(&trace_probe_ops, 0);
3088 3088
3089 ftrace_probe_registered = 0; 3089 ftrace_probe_registered = 0;
3090} 3090}
@@ -4366,12 +4366,15 @@ core_initcall(ftrace_nodyn_init);
4366static inline int ftrace_init_dyn_debugfs(struct dentry *d_tracer) { return 0; } 4366static inline int ftrace_init_dyn_debugfs(struct dentry *d_tracer) { return 0; }
4367static inline void ftrace_startup_enable(int command) { } 4367static inline void ftrace_startup_enable(int command) { }
4368/* Keep as macros so we do not need to define the commands */ 4368/* Keep as macros so we do not need to define the commands */
4369# define ftrace_startup(ops, command) \ 4369# define ftrace_startup(ops, command) \
4370 ({ \ 4370 ({ \
4371 (ops)->flags |= FTRACE_OPS_FL_ENABLED; \ 4371 int ___ret = __register_ftrace_function(ops); \
4372 0; \ 4372 if (!___ret) \
4373 (ops)->flags |= FTRACE_OPS_FL_ENABLED; \
4374 ___ret; \
4373 }) 4375 })
4374# define ftrace_shutdown(ops, command) do { } while (0) 4376# define ftrace_shutdown(ops, command) __unregister_ftrace_function(ops)
4377
4375# define ftrace_startup_sysctl() do { } while (0) 4378# define ftrace_startup_sysctl() do { } while (0)
4376# define ftrace_shutdown_sysctl() do { } while (0) 4379# define ftrace_shutdown_sysctl() do { } while (0)
4377 4380
@@ -4780,9 +4783,7 @@ int register_ftrace_function(struct ftrace_ops *ops)
4780 4783
4781 mutex_lock(&ftrace_lock); 4784 mutex_lock(&ftrace_lock);
4782 4785
4783 ret = __register_ftrace_function(ops); 4786 ret = ftrace_startup(ops, 0);
4784 if (!ret)
4785 ret = ftrace_startup(ops, 0);
4786 4787
4787 mutex_unlock(&ftrace_lock); 4788 mutex_unlock(&ftrace_lock);
4788 4789
@@ -4801,9 +4802,7 @@ int unregister_ftrace_function(struct ftrace_ops *ops)
4801 int ret; 4802 int ret;
4802 4803
4803 mutex_lock(&ftrace_lock); 4804 mutex_lock(&ftrace_lock);
4804 ret = __unregister_ftrace_function(ops); 4805 ret = ftrace_shutdown(ops, 0);
4805 if (!ret)
4806 ftrace_shutdown(ops, 0);
4807 mutex_unlock(&ftrace_lock); 4806 mutex_unlock(&ftrace_lock);
4808 4807
4809 return ret; 4808 return ret;
@@ -4997,6 +4996,13 @@ ftrace_suspend_notifier_call(struct notifier_block *bl, unsigned long state,
4997 return NOTIFY_DONE; 4996 return NOTIFY_DONE;
4998} 4997}
4999 4998
4999/* Just a place holder for function graph */
5000static struct ftrace_ops fgraph_ops __read_mostly = {
5001 .func = ftrace_stub,
5002 .flags = FTRACE_OPS_FL_STUB | FTRACE_OPS_FL_GLOBAL |
5003 FTRACE_OPS_FL_RECURSION_SAFE,
5004};
5005
5000int register_ftrace_graph(trace_func_graph_ret_t retfunc, 5006int register_ftrace_graph(trace_func_graph_ret_t retfunc,
5001 trace_func_graph_ent_t entryfunc) 5007 trace_func_graph_ent_t entryfunc)
5002{ 5008{
@@ -5023,7 +5029,7 @@ int register_ftrace_graph(trace_func_graph_ret_t retfunc,
5023 ftrace_graph_return = retfunc; 5029 ftrace_graph_return = retfunc;
5024 ftrace_graph_entry = entryfunc; 5030 ftrace_graph_entry = entryfunc;
5025 5031
5026 ret = ftrace_startup(&global_ops, FTRACE_START_FUNC_RET); 5032 ret = ftrace_startup(&fgraph_ops, FTRACE_START_FUNC_RET);
5027 5033
5028out: 5034out:
5029 mutex_unlock(&ftrace_lock); 5035 mutex_unlock(&ftrace_lock);
@@ -5040,7 +5046,7 @@ void unregister_ftrace_graph(void)
5040 ftrace_graph_active--; 5046 ftrace_graph_active--;
5041 ftrace_graph_return = (trace_func_graph_ret_t)ftrace_stub; 5047 ftrace_graph_return = (trace_func_graph_ret_t)ftrace_stub;
5042 ftrace_graph_entry = ftrace_graph_entry_stub; 5048 ftrace_graph_entry = ftrace_graph_entry_stub;
5043 ftrace_shutdown(&global_ops, FTRACE_STOP_FUNC_RET); 5049 ftrace_shutdown(&fgraph_ops, FTRACE_STOP_FUNC_RET);
5044 unregister_pm_notifier(&ftrace_suspend_notifier); 5050 unregister_pm_notifier(&ftrace_suspend_notifier);
5045 unregister_trace_sched_switch(ftrace_graph_probe_sched_switch, NULL); 5051 unregister_trace_sched_switch(ftrace_graph_probe_sched_switch, NULL);
5046 5052
diff --git a/kernel/trace/trace_event_perf.c b/kernel/trace/trace_event_perf.c
index 78e27e3b52ac..e854f420e033 100644
--- a/kernel/trace/trace_event_perf.c
+++ b/kernel/trace/trace_event_perf.c
@@ -24,6 +24,12 @@ static int total_ref_count;
24static int perf_trace_event_perm(struct ftrace_event_call *tp_event, 24static int perf_trace_event_perm(struct ftrace_event_call *tp_event,
25 struct perf_event *p_event) 25 struct perf_event *p_event)
26{ 26{
27 if (tp_event->perf_perm) {
28 int ret = tp_event->perf_perm(tp_event, p_event);
29 if (ret)
30 return ret;
31 }
32
27 /* The ftrace function trace is allowed only for root. */ 33 /* The ftrace function trace is allowed only for root. */
28 if (ftrace_event_is_function(tp_event) && 34 if (ftrace_event_is_function(tp_event) &&
29 perf_paranoid_tracepoint_raw() && !capable(CAP_SYS_ADMIN)) 35 perf_paranoid_tracepoint_raw() && !capable(CAP_SYS_ADMIN))
@@ -173,7 +179,7 @@ static int perf_trace_event_init(struct ftrace_event_call *tp_event,
173int perf_trace_init(struct perf_event *p_event) 179int perf_trace_init(struct perf_event *p_event)
174{ 180{
175 struct ftrace_event_call *tp_event; 181 struct ftrace_event_call *tp_event;
176 int event_id = p_event->attr.config; 182 u64 event_id = p_event->attr.config;
177 int ret = -EINVAL; 183 int ret = -EINVAL;
178 184
179 mutex_lock(&event_mutex); 185 mutex_lock(&event_mutex);
diff --git a/kernel/trace/trace_events.c b/kernel/trace/trace_events.c
index f919a2e21bf3..a11800ae96de 100644
--- a/kernel/trace/trace_events.c
+++ b/kernel/trace/trace_events.c
@@ -2314,6 +2314,9 @@ int event_trace_del_tracer(struct trace_array *tr)
2314 /* Disable any running events */ 2314 /* Disable any running events */
2315 __ftrace_set_clr_event_nolock(tr, NULL, NULL, NULL, 0); 2315 __ftrace_set_clr_event_nolock(tr, NULL, NULL, NULL, 0);
2316 2316
2317 /* Access to events are within rcu_read_lock_sched() */
2318 synchronize_sched();
2319
2317 down_write(&trace_event_sem); 2320 down_write(&trace_event_sem);
2318 __trace_remove_event_dirs(tr); 2321 __trace_remove_event_dirs(tr);
2319 debugfs_remove_recursive(tr->event_dir); 2322 debugfs_remove_recursive(tr->event_dir);
diff --git a/kernel/trace/trace_syscalls.c b/kernel/trace/trace_syscalls.c
index e4b6d11bdf78..ea90eb5f6f17 100644
--- a/kernel/trace/trace_syscalls.c
+++ b/kernel/trace/trace_syscalls.c
@@ -431,11 +431,6 @@ static void unreg_event_syscall_enter(struct ftrace_event_file *file,
431 if (!tr->sys_refcount_enter) 431 if (!tr->sys_refcount_enter)
432 unregister_trace_sys_enter(ftrace_syscall_enter, tr); 432 unregister_trace_sys_enter(ftrace_syscall_enter, tr);
433 mutex_unlock(&syscall_trace_lock); 433 mutex_unlock(&syscall_trace_lock);
434 /*
435 * Callers expect the event to be completely disabled on
436 * return, so wait for current handlers to finish.
437 */
438 synchronize_sched();
439} 434}
440 435
441static int reg_event_syscall_exit(struct ftrace_event_file *file, 436static int reg_event_syscall_exit(struct ftrace_event_file *file,
@@ -474,11 +469,6 @@ static void unreg_event_syscall_exit(struct ftrace_event_file *file,
474 if (!tr->sys_refcount_exit) 469 if (!tr->sys_refcount_exit)
475 unregister_trace_sys_exit(ftrace_syscall_exit, tr); 470 unregister_trace_sys_exit(ftrace_syscall_exit, tr);
476 mutex_unlock(&syscall_trace_lock); 471 mutex_unlock(&syscall_trace_lock);
477 /*
478 * Callers expect the event to be completely disabled on
479 * return, so wait for current handlers to finish.
480 */
481 synchronize_sched();
482} 472}
483 473
484static int __init init_syscall_trace(struct ftrace_event_call *call) 474static int __init init_syscall_trace(struct ftrace_event_call *call)
diff --git a/kernel/workqueue.c b/kernel/workqueue.c
index 987293d03ebc..c66912be990f 100644
--- a/kernel/workqueue.c
+++ b/kernel/workqueue.c
@@ -305,6 +305,9 @@ static DEFINE_HASHTABLE(unbound_pool_hash, UNBOUND_POOL_HASH_ORDER);
305/* I: attributes used when instantiating standard unbound pools on demand */ 305/* I: attributes used when instantiating standard unbound pools on demand */
306static struct workqueue_attrs *unbound_std_wq_attrs[NR_STD_WORKER_POOLS]; 306static struct workqueue_attrs *unbound_std_wq_attrs[NR_STD_WORKER_POOLS];
307 307
308/* I: attributes used when instantiating ordered pools on demand */
309static struct workqueue_attrs *ordered_wq_attrs[NR_STD_WORKER_POOLS];
310
308struct workqueue_struct *system_wq __read_mostly; 311struct workqueue_struct *system_wq __read_mostly;
309EXPORT_SYMBOL(system_wq); 312EXPORT_SYMBOL(system_wq);
310struct workqueue_struct *system_highpri_wq __read_mostly; 313struct workqueue_struct *system_highpri_wq __read_mostly;
@@ -518,14 +521,21 @@ static inline void debug_work_activate(struct work_struct *work) { }
518static inline void debug_work_deactivate(struct work_struct *work) { } 521static inline void debug_work_deactivate(struct work_struct *work) { }
519#endif 522#endif
520 523
521/* allocate ID and assign it to @pool */ 524/**
525 * worker_pool_assign_id - allocate ID and assing it to @pool
526 * @pool: the pool pointer of interest
527 *
528 * Returns 0 if ID in [0, WORK_OFFQ_POOL_NONE) is allocated and assigned
529 * successfully, -errno on failure.
530 */
522static int worker_pool_assign_id(struct worker_pool *pool) 531static int worker_pool_assign_id(struct worker_pool *pool)
523{ 532{
524 int ret; 533 int ret;
525 534
526 lockdep_assert_held(&wq_pool_mutex); 535 lockdep_assert_held(&wq_pool_mutex);
527 536
528 ret = idr_alloc(&worker_pool_idr, pool, 0, 0, GFP_KERNEL); 537 ret = idr_alloc(&worker_pool_idr, pool, 0, WORK_OFFQ_POOL_NONE,
538 GFP_KERNEL);
529 if (ret >= 0) { 539 if (ret >= 0) {
530 pool->id = ret; 540 pool->id = ret;
531 return 0; 541 return 0;
@@ -1320,7 +1330,7 @@ static void __queue_work(int cpu, struct workqueue_struct *wq,
1320 1330
1321 debug_work_activate(work); 1331 debug_work_activate(work);
1322 1332
1323 /* if dying, only works from the same workqueue are allowed */ 1333 /* if draining, only works from the same workqueue are allowed */
1324 if (unlikely(wq->flags & __WQ_DRAINING) && 1334 if (unlikely(wq->flags & __WQ_DRAINING) &&
1325 WARN_ON_ONCE(!is_chained_work(wq))) 1335 WARN_ON_ONCE(!is_chained_work(wq)))
1326 return; 1336 return;
@@ -1736,16 +1746,17 @@ static struct worker *create_worker(struct worker_pool *pool)
1736 if (IS_ERR(worker->task)) 1746 if (IS_ERR(worker->task))
1737 goto fail; 1747 goto fail;
1738 1748
1749 set_user_nice(worker->task, pool->attrs->nice);
1750
1751 /* prevent userland from meddling with cpumask of workqueue workers */
1752 worker->task->flags |= PF_NO_SETAFFINITY;
1753
1739 /* 1754 /*
1740 * set_cpus_allowed_ptr() will fail if the cpumask doesn't have any 1755 * set_cpus_allowed_ptr() will fail if the cpumask doesn't have any
1741 * online CPUs. It'll be re-applied when any of the CPUs come up. 1756 * online CPUs. It'll be re-applied when any of the CPUs come up.
1742 */ 1757 */
1743 set_user_nice(worker->task, pool->attrs->nice);
1744 set_cpus_allowed_ptr(worker->task, pool->attrs->cpumask); 1758 set_cpus_allowed_ptr(worker->task, pool->attrs->cpumask);
1745 1759
1746 /* prevent userland from meddling with cpumask of workqueue workers */
1747 worker->task->flags |= PF_NO_SETAFFINITY;
1748
1749 /* 1760 /*
1750 * The caller is responsible for ensuring %POOL_DISASSOCIATED 1761 * The caller is responsible for ensuring %POOL_DISASSOCIATED
1751 * remains stable across this function. See the comments above the 1762 * remains stable across this function. See the comments above the
@@ -4106,7 +4117,7 @@ out_unlock:
4106static int alloc_and_link_pwqs(struct workqueue_struct *wq) 4117static int alloc_and_link_pwqs(struct workqueue_struct *wq)
4107{ 4118{
4108 bool highpri = wq->flags & WQ_HIGHPRI; 4119 bool highpri = wq->flags & WQ_HIGHPRI;
4109 int cpu; 4120 int cpu, ret;
4110 4121
4111 if (!(wq->flags & WQ_UNBOUND)) { 4122 if (!(wq->flags & WQ_UNBOUND)) {
4112 wq->cpu_pwqs = alloc_percpu(struct pool_workqueue); 4123 wq->cpu_pwqs = alloc_percpu(struct pool_workqueue);
@@ -4126,6 +4137,13 @@ static int alloc_and_link_pwqs(struct workqueue_struct *wq)
4126 mutex_unlock(&wq->mutex); 4137 mutex_unlock(&wq->mutex);
4127 } 4138 }
4128 return 0; 4139 return 0;
4140 } else if (wq->flags & __WQ_ORDERED) {
4141 ret = apply_workqueue_attrs(wq, ordered_wq_attrs[highpri]);
4142 /* there should only be single pwq for ordering guarantee */
4143 WARN(!ret && (wq->pwqs.next != &wq->dfl_pwq->pwqs_node ||
4144 wq->pwqs.prev != &wq->dfl_pwq->pwqs_node),
4145 "ordering guarantee broken for workqueue %s\n", wq->name);
4146 return ret;
4129 } else { 4147 } else {
4130 return apply_workqueue_attrs(wq, unbound_std_wq_attrs[highpri]); 4148 return apply_workqueue_attrs(wq, unbound_std_wq_attrs[highpri]);
4131 } 4149 }
@@ -5009,10 +5027,6 @@ static int __init init_workqueues(void)
5009 int std_nice[NR_STD_WORKER_POOLS] = { 0, HIGHPRI_NICE_LEVEL }; 5027 int std_nice[NR_STD_WORKER_POOLS] = { 0, HIGHPRI_NICE_LEVEL };
5010 int i, cpu; 5028 int i, cpu;
5011 5029
5012 /* make sure we have enough bits for OFFQ pool ID */
5013 BUILD_BUG_ON((1LU << (BITS_PER_LONG - WORK_OFFQ_POOL_SHIFT)) <
5014 WORK_CPU_END * NR_STD_WORKER_POOLS);
5015
5016 WARN_ON(__alignof__(struct pool_workqueue) < __alignof__(long long)); 5030 WARN_ON(__alignof__(struct pool_workqueue) < __alignof__(long long));
5017 5031
5018 pwq_cache = KMEM_CACHE(pool_workqueue, SLAB_PANIC); 5032 pwq_cache = KMEM_CACHE(pool_workqueue, SLAB_PANIC);
@@ -5051,13 +5065,23 @@ static int __init init_workqueues(void)
5051 } 5065 }
5052 } 5066 }
5053 5067
5054 /* create default unbound wq attrs */ 5068 /* create default unbound and ordered wq attrs */
5055 for (i = 0; i < NR_STD_WORKER_POOLS; i++) { 5069 for (i = 0; i < NR_STD_WORKER_POOLS; i++) {
5056 struct workqueue_attrs *attrs; 5070 struct workqueue_attrs *attrs;
5057 5071
5058 BUG_ON(!(attrs = alloc_workqueue_attrs(GFP_KERNEL))); 5072 BUG_ON(!(attrs = alloc_workqueue_attrs(GFP_KERNEL)));
5059 attrs->nice = std_nice[i]; 5073 attrs->nice = std_nice[i];
5060 unbound_std_wq_attrs[i] = attrs; 5074 unbound_std_wq_attrs[i] = attrs;
5075
5076 /*
5077 * An ordered wq should have only one pwq as ordering is
5078 * guaranteed by max_active which is enforced by pwqs.
5079 * Turn off NUMA so that dfl_pwq is used for all nodes.
5080 */
5081 BUG_ON(!(attrs = alloc_workqueue_attrs(GFP_KERNEL)));
5082 attrs->nice = std_nice[i];
5083 attrs->no_numa = true;
5084 ordered_wq_attrs[i] = attrs;
5061 } 5085 }
5062 5086
5063 system_wq = alloc_workqueue("events", 0, 0); 5087 system_wq = alloc_workqueue("events", 0, 0);
diff --git a/lib/lockref.c b/lib/lockref.c
index d2b123f8456b..f07a40d33871 100644
--- a/lib/lockref.c
+++ b/lib/lockref.c
@@ -1,5 +1,6 @@
1#include <linux/export.h> 1#include <linux/export.h>
2#include <linux/lockref.h> 2#include <linux/lockref.h>
3#include <linux/mutex.h>
3 4
4#if USE_CMPXCHG_LOCKREF 5#if USE_CMPXCHG_LOCKREF
5 6
@@ -12,14 +13,6 @@
12#endif 13#endif
13 14
14/* 15/*
15 * Allow architectures to override the default cpu_relax() within CMPXCHG_LOOP.
16 * This is useful for architectures with an expensive cpu_relax().
17 */
18#ifndef arch_mutex_cpu_relax
19# define arch_mutex_cpu_relax() cpu_relax()
20#endif
21
22/*
23 * Note that the "cmpxchg()" reloads the "old" value for the 16 * Note that the "cmpxchg()" reloads the "old" value for the
24 * failure case. 17 * failure case.
25 */ 18 */
diff --git a/net/compat.c b/net/compat.c
index 618c6a8a911b..dd32e34c1e2c 100644
--- a/net/compat.c
+++ b/net/compat.c
@@ -72,7 +72,7 @@ int get_compat_msghdr(struct msghdr *kmsg, struct compat_msghdr __user *umsg)
72 __get_user(kmsg->msg_flags, &umsg->msg_flags)) 72 __get_user(kmsg->msg_flags, &umsg->msg_flags))
73 return -EFAULT; 73 return -EFAULT;
74 if (kmsg->msg_namelen > sizeof(struct sockaddr_storage)) 74 if (kmsg->msg_namelen > sizeof(struct sockaddr_storage))
75 return -EINVAL; 75 kmsg->msg_namelen = sizeof(struct sockaddr_storage);
76 kmsg->msg_name = compat_ptr(tmp1); 76 kmsg->msg_name = compat_ptr(tmp1);
77 kmsg->msg_iov = compat_ptr(tmp2); 77 kmsg->msg_iov = compat_ptr(tmp2);
78 kmsg->msg_control = compat_ptr(tmp3); 78 kmsg->msg_control = compat_ptr(tmp3);
diff --git a/net/core/pktgen.c b/net/core/pktgen.c
index 261357a66300..a797fff7f222 100644
--- a/net/core/pktgen.c
+++ b/net/core/pktgen.c
@@ -2527,6 +2527,8 @@ static int process_ipsec(struct pktgen_dev *pkt_dev,
2527 if (x) { 2527 if (x) {
2528 int ret; 2528 int ret;
2529 __u8 *eth; 2529 __u8 *eth;
2530 struct iphdr *iph;
2531
2530 nhead = x->props.header_len - skb_headroom(skb); 2532 nhead = x->props.header_len - skb_headroom(skb);
2531 if (nhead > 0) { 2533 if (nhead > 0) {
2532 ret = pskb_expand_head(skb, nhead, 0, GFP_ATOMIC); 2534 ret = pskb_expand_head(skb, nhead, 0, GFP_ATOMIC);
@@ -2548,6 +2550,11 @@ static int process_ipsec(struct pktgen_dev *pkt_dev,
2548 eth = (__u8 *) skb_push(skb, ETH_HLEN); 2550 eth = (__u8 *) skb_push(skb, ETH_HLEN);
2549 memcpy(eth, pkt_dev->hh, 12); 2551 memcpy(eth, pkt_dev->hh, 12);
2550 *(u16 *) &eth[12] = protocol; 2552 *(u16 *) &eth[12] = protocol;
2553
2554 /* Update IPv4 header len as well as checksum value */
2555 iph = ip_hdr(skb);
2556 iph->tot_len = htons(skb->len - ETH_HLEN);
2557 ip_send_check(iph);
2551 } 2558 }
2552 } 2559 }
2553 return 1; 2560 return 1;
diff --git a/net/hsr/hsr_framereg.c b/net/hsr/hsr_framereg.c
index 003f5bb3acd2..4bdab1521878 100644
--- a/net/hsr/hsr_framereg.c
+++ b/net/hsr/hsr_framereg.c
@@ -288,7 +288,8 @@ void hsr_addr_subst_dest(struct hsr_priv *hsr_priv, struct ethhdr *ethhdr,
288static bool seq_nr_after(u16 a, u16 b) 288static bool seq_nr_after(u16 a, u16 b)
289{ 289{
290 /* Remove inconsistency where 290 /* Remove inconsistency where
291 * seq_nr_after(a, b) == seq_nr_before(a, b) */ 291 * seq_nr_after(a, b) == seq_nr_before(a, b)
292 */
292 if ((int) b - a == 32768) 293 if ((int) b - a == 32768)
293 return false; 294 return false;
294 295
diff --git a/net/hsr/hsr_netlink.c b/net/hsr/hsr_netlink.c
index 5325af85eea6..01a5261ac7a5 100644
--- a/net/hsr/hsr_netlink.c
+++ b/net/hsr/hsr_netlink.c
@@ -23,6 +23,8 @@ static const struct nla_policy hsr_policy[IFLA_HSR_MAX + 1] = {
23 [IFLA_HSR_SLAVE1] = { .type = NLA_U32 }, 23 [IFLA_HSR_SLAVE1] = { .type = NLA_U32 },
24 [IFLA_HSR_SLAVE2] = { .type = NLA_U32 }, 24 [IFLA_HSR_SLAVE2] = { .type = NLA_U32 },
25 [IFLA_HSR_MULTICAST_SPEC] = { .type = NLA_U8 }, 25 [IFLA_HSR_MULTICAST_SPEC] = { .type = NLA_U8 },
26 [IFLA_HSR_SUPERVISION_ADDR] = { .type = NLA_BINARY, .len = ETH_ALEN },
27 [IFLA_HSR_SEQ_NR] = { .type = NLA_U16 },
26}; 28};
27 29
28 30
@@ -59,6 +61,31 @@ static int hsr_newlink(struct net *src_net, struct net_device *dev,
59 return hsr_dev_finalize(dev, link, multicast_spec); 61 return hsr_dev_finalize(dev, link, multicast_spec);
60} 62}
61 63
64static int hsr_fill_info(struct sk_buff *skb, const struct net_device *dev)
65{
66 struct hsr_priv *hsr_priv;
67
68 hsr_priv = netdev_priv(dev);
69
70 if (hsr_priv->slave[0])
71 if (nla_put_u32(skb, IFLA_HSR_SLAVE1, hsr_priv->slave[0]->ifindex))
72 goto nla_put_failure;
73
74 if (hsr_priv->slave[1])
75 if (nla_put_u32(skb, IFLA_HSR_SLAVE2, hsr_priv->slave[1]->ifindex))
76 goto nla_put_failure;
77
78 if (nla_put(skb, IFLA_HSR_SUPERVISION_ADDR, ETH_ALEN,
79 hsr_priv->sup_multicast_addr) ||
80 nla_put_u16(skb, IFLA_HSR_SEQ_NR, hsr_priv->sequence_nr))
81 goto nla_put_failure;
82
83 return 0;
84
85nla_put_failure:
86 return -EMSGSIZE;
87}
88
62static struct rtnl_link_ops hsr_link_ops __read_mostly = { 89static struct rtnl_link_ops hsr_link_ops __read_mostly = {
63 .kind = "hsr", 90 .kind = "hsr",
64 .maxtype = IFLA_HSR_MAX, 91 .maxtype = IFLA_HSR_MAX,
@@ -66,6 +93,7 @@ static struct rtnl_link_ops hsr_link_ops __read_mostly = {
66 .priv_size = sizeof(struct hsr_priv), 93 .priv_size = sizeof(struct hsr_priv),
67 .setup = hsr_dev_setup, 94 .setup = hsr_dev_setup,
68 .newlink = hsr_newlink, 95 .newlink = hsr_newlink,
96 .fill_info = hsr_fill_info,
69}; 97};
70 98
71 99
diff --git a/net/ipv4/ip_sockglue.c b/net/ipv4/ip_sockglue.c
index 3f858266fa7e..ddf32a6bc415 100644
--- a/net/ipv4/ip_sockglue.c
+++ b/net/ipv4/ip_sockglue.c
@@ -386,7 +386,7 @@ void ip_local_error(struct sock *sk, int err, __be32 daddr, __be16 port, u32 inf
386/* 386/*
387 * Handle MSG_ERRQUEUE 387 * Handle MSG_ERRQUEUE
388 */ 388 */
389int ip_recv_error(struct sock *sk, struct msghdr *msg, int len) 389int ip_recv_error(struct sock *sk, struct msghdr *msg, int len, int *addr_len)
390{ 390{
391 struct sock_exterr_skb *serr; 391 struct sock_exterr_skb *serr;
392 struct sk_buff *skb, *skb2; 392 struct sk_buff *skb, *skb2;
@@ -423,6 +423,7 @@ int ip_recv_error(struct sock *sk, struct msghdr *msg, int len)
423 serr->addr_offset); 423 serr->addr_offset);
424 sin->sin_port = serr->port; 424 sin->sin_port = serr->port;
425 memset(&sin->sin_zero, 0, sizeof(sin->sin_zero)); 425 memset(&sin->sin_zero, 0, sizeof(sin->sin_zero));
426 *addr_len = sizeof(*sin);
426 } 427 }
427 428
428 memcpy(&errhdr.ee, &serr->ee, sizeof(struct sock_extended_err)); 429 memcpy(&errhdr.ee, &serr->ee, sizeof(struct sock_extended_err));
diff --git a/net/ipv4/ping.c b/net/ipv4/ping.c
index 876c6ca2d8f9..242e7f4ed6f4 100644
--- a/net/ipv4/ping.c
+++ b/net/ipv4/ping.c
@@ -772,7 +772,7 @@ int ping_v4_sendmsg(struct kiocb *iocb, struct sock *sk, struct msghdr *msg,
772 err = PTR_ERR(rt); 772 err = PTR_ERR(rt);
773 rt = NULL; 773 rt = NULL;
774 if (err == -ENETUNREACH) 774 if (err == -ENETUNREACH)
775 IP_INC_STATS_BH(net, IPSTATS_MIB_OUTNOROUTES); 775 IP_INC_STATS(net, IPSTATS_MIB_OUTNOROUTES);
776 goto out; 776 goto out;
777 } 777 }
778 778
@@ -841,10 +841,11 @@ int ping_recvmsg(struct kiocb *iocb, struct sock *sk, struct msghdr *msg,
841 841
842 if (flags & MSG_ERRQUEUE) { 842 if (flags & MSG_ERRQUEUE) {
843 if (family == AF_INET) { 843 if (family == AF_INET) {
844 return ip_recv_error(sk, msg, len); 844 return ip_recv_error(sk, msg, len, addr_len);
845#if IS_ENABLED(CONFIG_IPV6) 845#if IS_ENABLED(CONFIG_IPV6)
846 } else if (family == AF_INET6) { 846 } else if (family == AF_INET6) {
847 return pingv6_ops.ipv6_recv_error(sk, msg, len); 847 return pingv6_ops.ipv6_recv_error(sk, msg, len,
848 addr_len);
848#endif 849#endif
849 } 850 }
850 } 851 }
diff --git a/net/ipv4/protocol.c b/net/ipv4/protocol.c
index ce848461acbb..46d6a1c923a8 100644
--- a/net/ipv4/protocol.c
+++ b/net/ipv4/protocol.c
@@ -31,10 +31,6 @@
31const struct net_protocol __rcu *inet_protos[MAX_INET_PROTOS] __read_mostly; 31const struct net_protocol __rcu *inet_protos[MAX_INET_PROTOS] __read_mostly;
32const struct net_offload __rcu *inet_offloads[MAX_INET_PROTOS] __read_mostly; 32const struct net_offload __rcu *inet_offloads[MAX_INET_PROTOS] __read_mostly;
33 33
34/*
35 * Add a protocol handler to the hash tables
36 */
37
38int inet_add_protocol(const struct net_protocol *prot, unsigned char protocol) 34int inet_add_protocol(const struct net_protocol *prot, unsigned char protocol)
39{ 35{
40 if (!prot->netns_ok) { 36 if (!prot->netns_ok) {
@@ -55,10 +51,6 @@ int inet_add_offload(const struct net_offload *prot, unsigned char protocol)
55} 51}
56EXPORT_SYMBOL(inet_add_offload); 52EXPORT_SYMBOL(inet_add_offload);
57 53
58/*
59 * Remove a protocol from the hash tables.
60 */
61
62int inet_del_protocol(const struct net_protocol *prot, unsigned char protocol) 54int inet_del_protocol(const struct net_protocol *prot, unsigned char protocol)
63{ 55{
64 int ret; 56 int ret;
diff --git a/net/ipv4/raw.c b/net/ipv4/raw.c
index 5cb8ddb505ee..23c3e5b5bb53 100644
--- a/net/ipv4/raw.c
+++ b/net/ipv4/raw.c
@@ -697,7 +697,7 @@ static int raw_recvmsg(struct kiocb *iocb, struct sock *sk, struct msghdr *msg,
697 goto out; 697 goto out;
698 698
699 if (flags & MSG_ERRQUEUE) { 699 if (flags & MSG_ERRQUEUE) {
700 err = ip_recv_error(sk, msg, len); 700 err = ip_recv_error(sk, msg, len, addr_len);
701 goto out; 701 goto out;
702 } 702 }
703 703
diff --git a/net/ipv4/tcp_ipv4.c b/net/ipv4/tcp_ipv4.c
index 59a6f8b90cd9..067213924751 100644
--- a/net/ipv4/tcp_ipv4.c
+++ b/net/ipv4/tcp_ipv4.c
@@ -177,7 +177,7 @@ int tcp_v4_connect(struct sock *sk, struct sockaddr *uaddr, int addr_len)
177 if (IS_ERR(rt)) { 177 if (IS_ERR(rt)) {
178 err = PTR_ERR(rt); 178 err = PTR_ERR(rt);
179 if (err == -ENETUNREACH) 179 if (err == -ENETUNREACH)
180 IP_INC_STATS_BH(sock_net(sk), IPSTATS_MIB_OUTNOROUTES); 180 IP_INC_STATS(sock_net(sk), IPSTATS_MIB_OUTNOROUTES);
181 return err; 181 return err;
182 } 182 }
183 183
diff --git a/net/ipv4/tcp_memcontrol.c b/net/ipv4/tcp_memcontrol.c
index 03e9154f7e68..269a89ecd2f4 100644
--- a/net/ipv4/tcp_memcontrol.c
+++ b/net/ipv4/tcp_memcontrol.c
@@ -60,7 +60,6 @@ EXPORT_SYMBOL(tcp_destroy_cgroup);
60static int tcp_update_limit(struct mem_cgroup *memcg, u64 val) 60static int tcp_update_limit(struct mem_cgroup *memcg, u64 val)
61{ 61{
62 struct cg_proto *cg_proto; 62 struct cg_proto *cg_proto;
63 u64 old_lim;
64 int i; 63 int i;
65 int ret; 64 int ret;
66 65
@@ -71,7 +70,6 @@ static int tcp_update_limit(struct mem_cgroup *memcg, u64 val)
71 if (val > RES_COUNTER_MAX) 70 if (val > RES_COUNTER_MAX)
72 val = RES_COUNTER_MAX; 71 val = RES_COUNTER_MAX;
73 72
74 old_lim = res_counter_read_u64(&cg_proto->memory_allocated, RES_LIMIT);
75 ret = res_counter_set_limit(&cg_proto->memory_allocated, val); 73 ret = res_counter_set_limit(&cg_proto->memory_allocated, val);
76 if (ret) 74 if (ret)
77 return ret; 75 return ret;
diff --git a/net/ipv4/tcp_offload.c b/net/ipv4/tcp_offload.c
index a2b68a108eae..05606353c7e7 100644
--- a/net/ipv4/tcp_offload.c
+++ b/net/ipv4/tcp_offload.c
@@ -274,33 +274,32 @@ static struct sk_buff **tcp4_gro_receive(struct sk_buff **head, struct sk_buff *
274{ 274{
275 const struct iphdr *iph = skb_gro_network_header(skb); 275 const struct iphdr *iph = skb_gro_network_header(skb);
276 __wsum wsum; 276 __wsum wsum;
277 __sum16 sum; 277
278 /* Don't bother verifying checksum if we're going to flush anyway. */
279 if (NAPI_GRO_CB(skb)->flush)
280 goto skip_csum;
281
282 wsum = skb->csum;
278 283
279 switch (skb->ip_summed) { 284 switch (skb->ip_summed) {
285 case CHECKSUM_NONE:
286 wsum = skb_checksum(skb, skb_gro_offset(skb), skb_gro_len(skb),
287 0);
288
289 /* fall through */
290
280 case CHECKSUM_COMPLETE: 291 case CHECKSUM_COMPLETE:
281 if (!tcp_v4_check(skb_gro_len(skb), iph->saddr, iph->daddr, 292 if (!tcp_v4_check(skb_gro_len(skb), iph->saddr, iph->daddr,
282 skb->csum)) { 293 wsum)) {
283 skb->ip_summed = CHECKSUM_UNNECESSARY; 294 skb->ip_summed = CHECKSUM_UNNECESSARY;
284 break; 295 break;
285 } 296 }
286flush: 297
287 NAPI_GRO_CB(skb)->flush = 1; 298 NAPI_GRO_CB(skb)->flush = 1;
288 return NULL; 299 return NULL;
289
290 case CHECKSUM_NONE:
291 wsum = csum_tcpudp_nofold(iph->saddr, iph->daddr,
292 skb_gro_len(skb), IPPROTO_TCP, 0);
293 sum = csum_fold(skb_checksum(skb,
294 skb_gro_offset(skb),
295 skb_gro_len(skb),
296 wsum));
297 if (sum)
298 goto flush;
299
300 skb->ip_summed = CHECKSUM_UNNECESSARY;
301 break;
302 } 300 }
303 301
302skip_csum:
304 return tcp_gro_receive(head, skb); 303 return tcp_gro_receive(head, skb);
305} 304}
306 305
diff --git a/net/ipv4/udp.c b/net/ipv4/udp.c
index 5944d7d668dd..44f6a20fa29d 100644
--- a/net/ipv4/udp.c
+++ b/net/ipv4/udp.c
@@ -999,7 +999,7 @@ int udp_sendmsg(struct kiocb *iocb, struct sock *sk, struct msghdr *msg,
999 err = PTR_ERR(rt); 999 err = PTR_ERR(rt);
1000 rt = NULL; 1000 rt = NULL;
1001 if (err == -ENETUNREACH) 1001 if (err == -ENETUNREACH)
1002 IP_INC_STATS_BH(net, IPSTATS_MIB_OUTNOROUTES); 1002 IP_INC_STATS(net, IPSTATS_MIB_OUTNOROUTES);
1003 goto out; 1003 goto out;
1004 } 1004 }
1005 1005
@@ -1098,6 +1098,9 @@ int udp_sendpage(struct sock *sk, struct page *page, int offset,
1098 struct udp_sock *up = udp_sk(sk); 1098 struct udp_sock *up = udp_sk(sk);
1099 int ret; 1099 int ret;
1100 1100
1101 if (flags & MSG_SENDPAGE_NOTLAST)
1102 flags |= MSG_MORE;
1103
1101 if (!up->pending) { 1104 if (!up->pending) {
1102 struct msghdr msg = { .msg_flags = flags|MSG_MORE }; 1105 struct msghdr msg = { .msg_flags = flags|MSG_MORE };
1103 1106
@@ -1236,7 +1239,7 @@ int udp_recvmsg(struct kiocb *iocb, struct sock *sk, struct msghdr *msg,
1236 bool slow; 1239 bool slow;
1237 1240
1238 if (flags & MSG_ERRQUEUE) 1241 if (flags & MSG_ERRQUEUE)
1239 return ip_recv_error(sk, msg, len); 1242 return ip_recv_error(sk, msg, len, addr_len);
1240 1243
1241try_again: 1244try_again:
1242 skb = __skb_recv_datagram(sk, flags | (noblock ? MSG_DONTWAIT : 0), 1245 skb = __skb_recv_datagram(sk, flags | (noblock ? MSG_DONTWAIT : 0),
diff --git a/net/ipv6/datagram.c b/net/ipv6/datagram.c
index a454b0ff57c7..8dfe1f4d3c1a 100644
--- a/net/ipv6/datagram.c
+++ b/net/ipv6/datagram.c
@@ -318,7 +318,7 @@ void ipv6_local_rxpmtu(struct sock *sk, struct flowi6 *fl6, u32 mtu)
318/* 318/*
319 * Handle MSG_ERRQUEUE 319 * Handle MSG_ERRQUEUE
320 */ 320 */
321int ipv6_recv_error(struct sock *sk, struct msghdr *msg, int len) 321int ipv6_recv_error(struct sock *sk, struct msghdr *msg, int len, int *addr_len)
322{ 322{
323 struct ipv6_pinfo *np = inet6_sk(sk); 323 struct ipv6_pinfo *np = inet6_sk(sk);
324 struct sock_exterr_skb *serr; 324 struct sock_exterr_skb *serr;
@@ -369,6 +369,7 @@ int ipv6_recv_error(struct sock *sk, struct msghdr *msg, int len)
369 &sin->sin6_addr); 369 &sin->sin6_addr);
370 sin->sin6_scope_id = 0; 370 sin->sin6_scope_id = 0;
371 } 371 }
372 *addr_len = sizeof(*sin);
372 } 373 }
373 374
374 memcpy(&errhdr.ee, &serr->ee, sizeof(struct sock_extended_err)); 375 memcpy(&errhdr.ee, &serr->ee, sizeof(struct sock_extended_err));
@@ -377,6 +378,7 @@ int ipv6_recv_error(struct sock *sk, struct msghdr *msg, int len)
377 if (serr->ee.ee_origin != SO_EE_ORIGIN_LOCAL) { 378 if (serr->ee.ee_origin != SO_EE_ORIGIN_LOCAL) {
378 sin->sin6_family = AF_INET6; 379 sin->sin6_family = AF_INET6;
379 sin->sin6_flowinfo = 0; 380 sin->sin6_flowinfo = 0;
381 sin->sin6_port = 0;
380 if (skb->protocol == htons(ETH_P_IPV6)) { 382 if (skb->protocol == htons(ETH_P_IPV6)) {
381 sin->sin6_addr = ipv6_hdr(skb)->saddr; 383 sin->sin6_addr = ipv6_hdr(skb)->saddr;
382 if (np->rxopt.all) 384 if (np->rxopt.all)
@@ -423,7 +425,8 @@ EXPORT_SYMBOL_GPL(ipv6_recv_error);
423/* 425/*
424 * Handle IPV6_RECVPATHMTU 426 * Handle IPV6_RECVPATHMTU
425 */ 427 */
426int ipv6_recv_rxpmtu(struct sock *sk, struct msghdr *msg, int len) 428int ipv6_recv_rxpmtu(struct sock *sk, struct msghdr *msg, int len,
429 int *addr_len)
427{ 430{
428 struct ipv6_pinfo *np = inet6_sk(sk); 431 struct ipv6_pinfo *np = inet6_sk(sk);
429 struct sk_buff *skb; 432 struct sk_buff *skb;
@@ -457,6 +460,7 @@ int ipv6_recv_rxpmtu(struct sock *sk, struct msghdr *msg, int len)
457 sin->sin6_port = 0; 460 sin->sin6_port = 0;
458 sin->sin6_scope_id = mtu_info.ip6m_addr.sin6_scope_id; 461 sin->sin6_scope_id = mtu_info.ip6m_addr.sin6_scope_id;
459 sin->sin6_addr = mtu_info.ip6m_addr.sin6_addr; 462 sin->sin6_addr = mtu_info.ip6m_addr.sin6_addr;
463 *addr_len = sizeof(*sin);
460 } 464 }
461 465
462 put_cmsg(msg, SOL_IPV6, IPV6_PATHMTU, sizeof(mtu_info), &mtu_info); 466 put_cmsg(msg, SOL_IPV6, IPV6_PATHMTU, sizeof(mtu_info), &mtu_info);
diff --git a/net/ipv6/ip6_output.c b/net/ipv6/ip6_output.c
index 59df872e2f4d..4acdb63495db 100644
--- a/net/ipv6/ip6_output.c
+++ b/net/ipv6/ip6_output.c
@@ -116,8 +116,8 @@ static int ip6_finish_output2(struct sk_buff *skb)
116 } 116 }
117 rcu_read_unlock_bh(); 117 rcu_read_unlock_bh();
118 118
119 IP6_INC_STATS_BH(dev_net(dst->dev), 119 IP6_INC_STATS(dev_net(dst->dev),
120 ip6_dst_idev(dst), IPSTATS_MIB_OUTNOROUTES); 120 ip6_dst_idev(dst), IPSTATS_MIB_OUTNOROUTES);
121 kfree_skb(skb); 121 kfree_skb(skb);
122 return -EINVAL; 122 return -EINVAL;
123} 123}
diff --git a/net/ipv6/ping.c b/net/ipv6/ping.c
index 8815e31a87fe..a83243c3d656 100644
--- a/net/ipv6/ping.c
+++ b/net/ipv6/ping.c
@@ -57,7 +57,8 @@ static struct inet_protosw pingv6_protosw = {
57 57
58 58
59/* Compatibility glue so we can support IPv6 when it's compiled as a module */ 59/* Compatibility glue so we can support IPv6 when it's compiled as a module */
60static int dummy_ipv6_recv_error(struct sock *sk, struct msghdr *msg, int len) 60static int dummy_ipv6_recv_error(struct sock *sk, struct msghdr *msg, int len,
61 int *addr_len)
61{ 62{
62 return -EAFNOSUPPORT; 63 return -EAFNOSUPPORT;
63} 64}
diff --git a/net/ipv6/protocol.c b/net/ipv6/protocol.c
index 22d1bd4670da..e048cf1bb6a2 100644
--- a/net/ipv6/protocol.c
+++ b/net/ipv6/protocol.c
@@ -36,10 +36,6 @@ int inet6_add_protocol(const struct inet6_protocol *prot, unsigned char protocol
36} 36}
37EXPORT_SYMBOL(inet6_add_protocol); 37EXPORT_SYMBOL(inet6_add_protocol);
38 38
39/*
40 * Remove a protocol from the hash tables.
41 */
42
43int inet6_del_protocol(const struct inet6_protocol *prot, unsigned char protocol) 39int inet6_del_protocol(const struct inet6_protocol *prot, unsigned char protocol)
44{ 40{
45 int ret; 41 int ret;
diff --git a/net/ipv6/raw.c b/net/ipv6/raw.c
index e24ff1df0401..7fb4e14c467f 100644
--- a/net/ipv6/raw.c
+++ b/net/ipv6/raw.c
@@ -466,10 +466,10 @@ static int rawv6_recvmsg(struct kiocb *iocb, struct sock *sk,
466 return -EOPNOTSUPP; 466 return -EOPNOTSUPP;
467 467
468 if (flags & MSG_ERRQUEUE) 468 if (flags & MSG_ERRQUEUE)
469 return ipv6_recv_error(sk, msg, len); 469 return ipv6_recv_error(sk, msg, len, addr_len);
470 470
471 if (np->rxpmtu && np->rxopt.bits.rxpmtu) 471 if (np->rxpmtu && np->rxopt.bits.rxpmtu)
472 return ipv6_recv_rxpmtu(sk, msg, len); 472 return ipv6_recv_rxpmtu(sk, msg, len, addr_len);
473 473
474 skb = skb_recv_datagram(sk, flags, noblock, &err); 474 skb = skb_recv_datagram(sk, flags, noblock, &err);
475 if (!skb) 475 if (!skb)
diff --git a/net/ipv6/sit.c b/net/ipv6/sit.c
index 1b4a4a953675..366fbba3359a 100644
--- a/net/ipv6/sit.c
+++ b/net/ipv6/sit.c
@@ -478,14 +478,44 @@ static void ipip6_tunnel_uninit(struct net_device *dev)
478 dev_put(dev); 478 dev_put(dev);
479} 479}
480 480
481/* Generate icmpv6 with type/code ICMPV6_DEST_UNREACH/ICMPV6_ADDR_UNREACH
482 * if sufficient data bytes are available
483 */
484static int ipip6_err_gen_icmpv6_unreach(struct sk_buff *skb)
485{
486 const struct iphdr *iph = (const struct iphdr *) skb->data;
487 struct rt6_info *rt;
488 struct sk_buff *skb2;
489
490 if (!pskb_may_pull(skb, iph->ihl * 4 + sizeof(struct ipv6hdr) + 8))
491 return 1;
492
493 skb2 = skb_clone(skb, GFP_ATOMIC);
494
495 if (!skb2)
496 return 1;
497
498 skb_dst_drop(skb2);
499 skb_pull(skb2, iph->ihl * 4);
500 skb_reset_network_header(skb2);
501
502 rt = rt6_lookup(dev_net(skb->dev), &ipv6_hdr(skb2)->saddr, NULL, 0, 0);
503
504 if (rt && rt->dst.dev)
505 skb2->dev = rt->dst.dev;
506
507 icmpv6_send(skb2, ICMPV6_DEST_UNREACH, ICMPV6_ADDR_UNREACH, 0);
508
509 if (rt)
510 ip6_rt_put(rt);
511
512 kfree_skb(skb2);
513
514 return 0;
515}
481 516
482static int ipip6_err(struct sk_buff *skb, u32 info) 517static int ipip6_err(struct sk_buff *skb, u32 info)
483{ 518{
484
485/* All the routers (except for Linux) return only
486 8 bytes of packet payload. It means, that precise relaying of
487 ICMP in the real Internet is absolutely infeasible.
488 */
489 const struct iphdr *iph = (const struct iphdr *)skb->data; 519 const struct iphdr *iph = (const struct iphdr *)skb->data;
490 const int type = icmp_hdr(skb)->type; 520 const int type = icmp_hdr(skb)->type;
491 const int code = icmp_hdr(skb)->code; 521 const int code = icmp_hdr(skb)->code;
@@ -500,7 +530,6 @@ static int ipip6_err(struct sk_buff *skb, u32 info)
500 case ICMP_DEST_UNREACH: 530 case ICMP_DEST_UNREACH:
501 switch (code) { 531 switch (code) {
502 case ICMP_SR_FAILED: 532 case ICMP_SR_FAILED:
503 case ICMP_PORT_UNREACH:
504 /* Impossible event. */ 533 /* Impossible event. */
505 return 0; 534 return 0;
506 default: 535 default:
@@ -545,6 +574,9 @@ static int ipip6_err(struct sk_buff *skb, u32 info)
545 goto out; 574 goto out;
546 575
547 err = 0; 576 err = 0;
577 if (!ipip6_err_gen_icmpv6_unreach(skb))
578 goto out;
579
548 if (t->parms.iph.ttl == 0 && type == ICMP_TIME_EXCEEDED) 580 if (t->parms.iph.ttl == 0 && type == ICMP_TIME_EXCEEDED)
549 goto out; 581 goto out;
550 582
@@ -919,7 +951,7 @@ static netdev_tx_t ipip6_tunnel_xmit(struct sk_buff *skb,
919 if (!new_skb) { 951 if (!new_skb) {
920 ip_rt_put(rt); 952 ip_rt_put(rt);
921 dev->stats.tx_dropped++; 953 dev->stats.tx_dropped++;
922 dev_kfree_skb(skb); 954 kfree_skb(skb);
923 return NETDEV_TX_OK; 955 return NETDEV_TX_OK;
924 } 956 }
925 if (skb->sk) 957 if (skb->sk)
@@ -945,7 +977,7 @@ static netdev_tx_t ipip6_tunnel_xmit(struct sk_buff *skb,
945tx_error_icmp: 977tx_error_icmp:
946 dst_link_failure(skb); 978 dst_link_failure(skb);
947tx_error: 979tx_error:
948 dev_kfree_skb(skb); 980 kfree_skb(skb);
949out: 981out:
950 dev->stats.tx_errors++; 982 dev->stats.tx_errors++;
951 return NETDEV_TX_OK; 983 return NETDEV_TX_OK;
@@ -985,7 +1017,7 @@ static netdev_tx_t sit_tunnel_xmit(struct sk_buff *skb,
985 1017
986tx_err: 1018tx_err:
987 dev->stats.tx_errors++; 1019 dev->stats.tx_errors++;
988 dev_kfree_skb(skb); 1020 kfree_skb(skb);
989 return NETDEV_TX_OK; 1021 return NETDEV_TX_OK;
990 1022
991} 1023}
diff --git a/net/ipv6/tcpv6_offload.c b/net/ipv6/tcpv6_offload.c
index c1097c798900..6d18157dc32c 100644
--- a/net/ipv6/tcpv6_offload.c
+++ b/net/ipv6/tcpv6_offload.c
@@ -37,34 +37,32 @@ static struct sk_buff **tcp6_gro_receive(struct sk_buff **head,
37{ 37{
38 const struct ipv6hdr *iph = skb_gro_network_header(skb); 38 const struct ipv6hdr *iph = skb_gro_network_header(skb);
39 __wsum wsum; 39 __wsum wsum;
40 __sum16 sum; 40
41 /* Don't bother verifying checksum if we're going to flush anyway. */
42 if (NAPI_GRO_CB(skb)->flush)
43 goto skip_csum;
44
45 wsum = skb->csum;
41 46
42 switch (skb->ip_summed) { 47 switch (skb->ip_summed) {
48 case CHECKSUM_NONE:
49 wsum = skb_checksum(skb, skb_gro_offset(skb), skb_gro_len(skb),
50 wsum);
51
52 /* fall through */
53
43 case CHECKSUM_COMPLETE: 54 case CHECKSUM_COMPLETE:
44 if (!tcp_v6_check(skb_gro_len(skb), &iph->saddr, &iph->daddr, 55 if (!tcp_v6_check(skb_gro_len(skb), &iph->saddr, &iph->daddr,
45 skb->csum)) { 56 wsum)) {
46 skb->ip_summed = CHECKSUM_UNNECESSARY; 57 skb->ip_summed = CHECKSUM_UNNECESSARY;
47 break; 58 break;
48 } 59 }
49flush: 60
50 NAPI_GRO_CB(skb)->flush = 1; 61 NAPI_GRO_CB(skb)->flush = 1;
51 return NULL; 62 return NULL;
52
53 case CHECKSUM_NONE:
54 wsum = ~csum_unfold(csum_ipv6_magic(&iph->saddr, &iph->daddr,
55 skb_gro_len(skb),
56 IPPROTO_TCP, 0));
57 sum = csum_fold(skb_checksum(skb,
58 skb_gro_offset(skb),
59 skb_gro_len(skb),
60 wsum));
61 if (sum)
62 goto flush;
63
64 skb->ip_summed = CHECKSUM_UNNECESSARY;
65 break;
66 } 63 }
67 64
65skip_csum:
68 return tcp_gro_receive(head, skb); 66 return tcp_gro_receive(head, skb);
69} 67}
70 68
diff --git a/net/ipv6/udp.c b/net/ipv6/udp.c
index 81eb8cf8389b..bcd5699313c3 100644
--- a/net/ipv6/udp.c
+++ b/net/ipv6/udp.c
@@ -393,10 +393,10 @@ int udpv6_recvmsg(struct kiocb *iocb, struct sock *sk,
393 bool slow; 393 bool slow;
394 394
395 if (flags & MSG_ERRQUEUE) 395 if (flags & MSG_ERRQUEUE)
396 return ipv6_recv_error(sk, msg, len); 396 return ipv6_recv_error(sk, msg, len, addr_len);
397 397
398 if (np->rxpmtu && np->rxopt.bits.rxpmtu) 398 if (np->rxpmtu && np->rxopt.bits.rxpmtu)
399 return ipv6_recv_rxpmtu(sk, msg, len); 399 return ipv6_recv_rxpmtu(sk, msg, len, addr_len);
400 400
401try_again: 401try_again:
402 skb = __skb_recv_datagram(sk, flags | (noblock ? MSG_DONTWAIT : 0), 402 skb = __skb_recv_datagram(sk, flags | (noblock ? MSG_DONTWAIT : 0),
diff --git a/net/l2tp/l2tp_ip6.c b/net/l2tp/l2tp_ip6.c
index cfd65304be60..d9b437e55007 100644
--- a/net/l2tp/l2tp_ip6.c
+++ b/net/l2tp/l2tp_ip6.c
@@ -665,7 +665,7 @@ static int l2tp_ip6_recvmsg(struct kiocb *iocb, struct sock *sk,
665 *addr_len = sizeof(*lsa); 665 *addr_len = sizeof(*lsa);
666 666
667 if (flags & MSG_ERRQUEUE) 667 if (flags & MSG_ERRQUEUE)
668 return ipv6_recv_error(sk, msg, len); 668 return ipv6_recv_error(sk, msg, len, addr_len);
669 669
670 skb = skb_recv_datagram(sk, flags, noblock, &err); 670 skb = skb_recv_datagram(sk, flags, noblock, &err);
671 if (!skb) 671 if (!skb)
diff --git a/net/netlink/genetlink.c b/net/netlink/genetlink.c
index 4518a57aa5fe..713671ae45af 100644
--- a/net/netlink/genetlink.c
+++ b/net/netlink/genetlink.c
@@ -74,9 +74,12 @@ static struct list_head family_ht[GENL_FAM_TAB_SIZE];
74 * Bit 17 is marked as already used since the VFS quota code 74 * Bit 17 is marked as already used since the VFS quota code
75 * also abused this API and relied on family == group ID, we 75 * also abused this API and relied on family == group ID, we
76 * cater to that by giving it a static family and group ID. 76 * cater to that by giving it a static family and group ID.
77 * Bit 18 is marked as already used since the PMCRAID driver
78 * did the same thing as the VFS quota code (maybe copied?)
77 */ 79 */
78static unsigned long mc_group_start = 0x3 | BIT(GENL_ID_CTRL) | 80static unsigned long mc_group_start = 0x3 | BIT(GENL_ID_CTRL) |
79 BIT(GENL_ID_VFS_DQUOT); 81 BIT(GENL_ID_VFS_DQUOT) |
82 BIT(GENL_ID_PMCRAID);
80static unsigned long *mc_groups = &mc_group_start; 83static unsigned long *mc_groups = &mc_group_start;
81static unsigned long mc_groups_longs = 1; 84static unsigned long mc_groups_longs = 1;
82 85
@@ -139,6 +142,7 @@ static u16 genl_generate_id(void)
139 142
140 for (i = 0; i <= GENL_MAX_ID - GENL_MIN_ID; i++) { 143 for (i = 0; i <= GENL_MAX_ID - GENL_MIN_ID; i++) {
141 if (id_gen_idx != GENL_ID_VFS_DQUOT && 144 if (id_gen_idx != GENL_ID_VFS_DQUOT &&
145 id_gen_idx != GENL_ID_PMCRAID &&
142 !genl_family_find_byid(id_gen_idx)) 146 !genl_family_find_byid(id_gen_idx))
143 return id_gen_idx; 147 return id_gen_idx;
144 if (++id_gen_idx > GENL_MAX_ID) 148 if (++id_gen_idx > GENL_MAX_ID)
@@ -214,7 +218,7 @@ static int genl_validate_assign_mc_groups(struct genl_family *family)
214{ 218{
215 int first_id; 219 int first_id;
216 int n_groups = family->n_mcgrps; 220 int n_groups = family->n_mcgrps;
217 int err, i; 221 int err = 0, i;
218 bool groups_allocated = false; 222 bool groups_allocated = false;
219 223
220 if (!n_groups) 224 if (!n_groups)
@@ -236,9 +240,12 @@ static int genl_validate_assign_mc_groups(struct genl_family *family)
236 } else if (strcmp(family->name, "NET_DM") == 0) { 240 } else if (strcmp(family->name, "NET_DM") == 0) {
237 first_id = 1; 241 first_id = 1;
238 BUG_ON(n_groups != 1); 242 BUG_ON(n_groups != 1);
239 } else if (strcmp(family->name, "VFS_DQUOT") == 0) { 243 } else if (family->id == GENL_ID_VFS_DQUOT) {
240 first_id = GENL_ID_VFS_DQUOT; 244 first_id = GENL_ID_VFS_DQUOT;
241 BUG_ON(n_groups != 1); 245 BUG_ON(n_groups != 1);
246 } else if (family->id == GENL_ID_PMCRAID) {
247 first_id = GENL_ID_PMCRAID;
248 BUG_ON(n_groups != 1);
242 } else { 249 } else {
243 groups_allocated = true; 250 groups_allocated = true;
244 err = genl_allocate_reserve_groups(n_groups, &first_id); 251 err = genl_allocate_reserve_groups(n_groups, &first_id);
diff --git a/net/packet/af_packet.c b/net/packet/af_packet.c
index ac27c86ef6d1..ba2548bd85bf 100644
--- a/net/packet/af_packet.c
+++ b/net/packet/af_packet.c
@@ -439,9 +439,9 @@ static void prb_shutdown_retire_blk_timer(struct packet_sock *po,
439 439
440 pkc = tx_ring ? &po->tx_ring.prb_bdqc : &po->rx_ring.prb_bdqc; 440 pkc = tx_ring ? &po->tx_ring.prb_bdqc : &po->rx_ring.prb_bdqc;
441 441
442 spin_lock(&rb_queue->lock); 442 spin_lock_bh(&rb_queue->lock);
443 pkc->delete_blk_timer = 1; 443 pkc->delete_blk_timer = 1;
444 spin_unlock(&rb_queue->lock); 444 spin_unlock_bh(&rb_queue->lock);
445 445
446 prb_del_retire_blk_timer(pkc); 446 prb_del_retire_blk_timer(pkc);
447} 447}
diff --git a/net/sched/sch_netem.c b/net/sched/sch_netem.c
index 75c94e59a3bd..bccd52b36e97 100644
--- a/net/sched/sch_netem.c
+++ b/net/sched/sch_netem.c
@@ -215,10 +215,10 @@ static bool loss_4state(struct netem_sched_data *q)
215 if (rnd < clg->a4) { 215 if (rnd < clg->a4) {
216 clg->state = 4; 216 clg->state = 4;
217 return true; 217 return true;
218 } else if (clg->a4 < rnd && rnd < clg->a1) { 218 } else if (clg->a4 < rnd && rnd < clg->a1 + clg->a4) {
219 clg->state = 3; 219 clg->state = 3;
220 return true; 220 return true;
221 } else if (clg->a1 < rnd) 221 } else if (clg->a1 + clg->a4 < rnd)
222 clg->state = 1; 222 clg->state = 1;
223 223
224 break; 224 break;
@@ -268,10 +268,11 @@ static bool loss_gilb_ell(struct netem_sched_data *q)
268 clg->state = 2; 268 clg->state = 2;
269 if (net_random() < clg->a4) 269 if (net_random() < clg->a4)
270 return true; 270 return true;
271 break;
271 case 2: 272 case 2:
272 if (net_random() < clg->a2) 273 if (net_random() < clg->a2)
273 clg->state = 1; 274 clg->state = 1;
274 if (clg->a3 > net_random()) 275 if (net_random() > clg->a3)
275 return true; 276 return true;
276 } 277 }
277 278
diff --git a/net/sched/sch_tbf.c b/net/sched/sch_tbf.c
index 68f98595819c..a6090051c5db 100644
--- a/net/sched/sch_tbf.c
+++ b/net/sched/sch_tbf.c
@@ -21,6 +21,7 @@
21#include <net/netlink.h> 21#include <net/netlink.h>
22#include <net/sch_generic.h> 22#include <net/sch_generic.h>
23#include <net/pkt_sched.h> 23#include <net/pkt_sched.h>
24#include <net/tcp.h>
24 25
25 26
26/* Simple Token Bucket Filter. 27/* Simple Token Bucket Filter.
@@ -117,6 +118,22 @@ struct tbf_sched_data {
117}; 118};
118 119
119 120
121/*
122 * Return length of individual segments of a gso packet,
123 * including all headers (MAC, IP, TCP/UDP)
124 */
125static unsigned int skb_gso_seglen(const struct sk_buff *skb)
126{
127 unsigned int hdr_len = skb_transport_header(skb) - skb_mac_header(skb);
128 const struct skb_shared_info *shinfo = skb_shinfo(skb);
129
130 if (likely(shinfo->gso_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)))
131 hdr_len += tcp_hdrlen(skb);
132 else
133 hdr_len += sizeof(struct udphdr);
134 return hdr_len + shinfo->gso_size;
135}
136
120/* GSO packet is too big, segment it so that tbf can transmit 137/* GSO packet is too big, segment it so that tbf can transmit
121 * each segment in time 138 * each segment in time
122 */ 139 */
@@ -136,12 +153,8 @@ static int tbf_segment(struct sk_buff *skb, struct Qdisc *sch)
136 while (segs) { 153 while (segs) {
137 nskb = segs->next; 154 nskb = segs->next;
138 segs->next = NULL; 155 segs->next = NULL;
139 if (likely(segs->len <= q->max_size)) { 156 qdisc_skb_cb(segs)->pkt_len = segs->len;
140 qdisc_skb_cb(segs)->pkt_len = segs->len; 157 ret = qdisc_enqueue(segs, q->qdisc);
141 ret = qdisc_enqueue(segs, q->qdisc);
142 } else {
143 ret = qdisc_reshape_fail(skb, sch);
144 }
145 if (ret != NET_XMIT_SUCCESS) { 158 if (ret != NET_XMIT_SUCCESS) {
146 if (net_xmit_drop_count(ret)) 159 if (net_xmit_drop_count(ret))
147 sch->qstats.drops++; 160 sch->qstats.drops++;
@@ -163,7 +176,7 @@ static int tbf_enqueue(struct sk_buff *skb, struct Qdisc *sch)
163 int ret; 176 int ret;
164 177
165 if (qdisc_pkt_len(skb) > q->max_size) { 178 if (qdisc_pkt_len(skb) > q->max_size) {
166 if (skb_is_gso(skb)) 179 if (skb_is_gso(skb) && skb_gso_seglen(skb) <= q->max_size)
167 return tbf_segment(skb, sch); 180 return tbf_segment(skb, sch);
168 return qdisc_reshape_fail(skb, sch); 181 return qdisc_reshape_fail(skb, sch);
169 } 182 }
@@ -319,6 +332,11 @@ static int tbf_change(struct Qdisc *sch, struct nlattr *opt)
319 if (max_size < 0) 332 if (max_size < 0)
320 goto done; 333 goto done;
321 334
335 if (max_size < psched_mtu(qdisc_dev(sch)))
336 pr_warn_ratelimited("sch_tbf: burst %u is lower than device %s mtu (%u) !\n",
337 max_size, qdisc_dev(sch)->name,
338 psched_mtu(qdisc_dev(sch)));
339
322 if (q->qdisc != &noop_qdisc) { 340 if (q->qdisc != &noop_qdisc) {
323 err = fifo_set_limit(q->qdisc, qopt->limit); 341 err = fifo_set_limit(q->qdisc, qopt->limit);
324 if (err) 342 if (err)
diff --git a/net/sctp/output.c b/net/sctp/output.c
index e650978daf27..0e2644d0a773 100644
--- a/net/sctp/output.c
+++ b/net/sctp/output.c
@@ -474,10 +474,11 @@ int sctp_packet_transmit(struct sctp_packet *packet)
474 * for a given destination transport address. 474 * for a given destination transport address.
475 */ 475 */
476 476
477 if (!tp->rto_pending) { 477 if (!chunk->resent && !tp->rto_pending) {
478 chunk->rtt_in_progress = 1; 478 chunk->rtt_in_progress = 1;
479 tp->rto_pending = 1; 479 tp->rto_pending = 1;
480 } 480 }
481
481 has_data = 1; 482 has_data = 1;
482 } 483 }
483 484
diff --git a/net/sctp/outqueue.c b/net/sctp/outqueue.c
index 94df75877869..f51ba985a36e 100644
--- a/net/sctp/outqueue.c
+++ b/net/sctp/outqueue.c
@@ -446,6 +446,8 @@ void sctp_retransmit_mark(struct sctp_outq *q,
446 transport->rto_pending = 0; 446 transport->rto_pending = 0;
447 } 447 }
448 448
449 chunk->resent = 1;
450
449 /* Move the chunk to the retransmit queue. The chunks 451 /* Move the chunk to the retransmit queue. The chunks
450 * on the retransmit queue are always kept in order. 452 * on the retransmit queue are always kept in order.
451 */ 453 */
@@ -1375,6 +1377,7 @@ static void sctp_check_transmitted(struct sctp_outq *q,
1375 * instance). 1377 * instance).
1376 */ 1378 */
1377 if (!tchunk->tsn_gap_acked && 1379 if (!tchunk->tsn_gap_acked &&
1380 !tchunk->resent &&
1378 tchunk->rtt_in_progress) { 1381 tchunk->rtt_in_progress) {
1379 tchunk->rtt_in_progress = 0; 1382 tchunk->rtt_in_progress = 0;
1380 rtt = jiffies - tchunk->sent_at; 1383 rtt = jiffies - tchunk->sent_at;
@@ -1391,7 +1394,8 @@ static void sctp_check_transmitted(struct sctp_outq *q,
1391 */ 1394 */
1392 if (!tchunk->tsn_gap_acked) { 1395 if (!tchunk->tsn_gap_acked) {
1393 tchunk->tsn_gap_acked = 1; 1396 tchunk->tsn_gap_acked = 1;
1394 *highest_new_tsn_in_sack = tsn; 1397 if (TSN_lt(*highest_new_tsn_in_sack, tsn))
1398 *highest_new_tsn_in_sack = tsn;
1395 bytes_acked += sctp_data_size(tchunk); 1399 bytes_acked += sctp_data_size(tchunk);
1396 if (!tchunk->transport) 1400 if (!tchunk->transport)
1397 migrate_bytes += sctp_data_size(tchunk); 1401 migrate_bytes += sctp_data_size(tchunk);
diff --git a/net/socket.c b/net/socket.c
index 0b18693f2be6..e83c416708af 100644
--- a/net/socket.c
+++ b/net/socket.c
@@ -1973,7 +1973,7 @@ static int copy_msghdr_from_user(struct msghdr *kmsg,
1973 if (copy_from_user(kmsg, umsg, sizeof(struct msghdr))) 1973 if (copy_from_user(kmsg, umsg, sizeof(struct msghdr)))
1974 return -EFAULT; 1974 return -EFAULT;
1975 if (kmsg->msg_namelen > sizeof(struct sockaddr_storage)) 1975 if (kmsg->msg_namelen > sizeof(struct sockaddr_storage))
1976 return -EINVAL; 1976 kmsg->msg_namelen = sizeof(struct sockaddr_storage);
1977 return 0; 1977 return 0;
1978} 1978}
1979 1979
diff --git a/net/sunrpc/auth_gss/auth_gss.c b/net/sunrpc/auth_gss/auth_gss.c
index 97912b40c254..42fdfc634e56 100644
--- a/net/sunrpc/auth_gss/auth_gss.c
+++ b/net/sunrpc/auth_gss/auth_gss.c
@@ -1517,7 +1517,7 @@ out:
1517static int 1517static int
1518gss_refresh_null(struct rpc_task *task) 1518gss_refresh_null(struct rpc_task *task)
1519{ 1519{
1520 return -EACCES; 1520 return 0;
1521} 1521}
1522 1522
1523static __be32 * 1523static __be32 *
diff --git a/scripts/recordmcount.pl b/scripts/recordmcount.pl
index d0da66396f62..91280b82da08 100755
--- a/scripts/recordmcount.pl
+++ b/scripts/recordmcount.pl
@@ -364,7 +364,8 @@ if ($arch eq "x86_64") {
364} elsif ($arch eq "blackfin") { 364} elsif ($arch eq "blackfin") {
365 $mcount_regex = "^\\s*([0-9a-fA-F]+):.*\\s__mcount\$"; 365 $mcount_regex = "^\\s*([0-9a-fA-F]+):.*\\s__mcount\$";
366 $mcount_adjust = -4; 366 $mcount_adjust = -4;
367} elsif ($arch eq "tilegx") { 367} elsif ($arch eq "tilegx" || $arch eq "tile") {
368 # Default to the newer TILE-Gx architecture if only "tile" is given.
368 $mcount_regex = "^\\s*([0-9a-fA-F]+):.*\\s__mcount\$"; 369 $mcount_regex = "^\\s*([0-9a-fA-F]+):.*\\s__mcount\$";
369 $type = ".quad"; 370 $type = ".quad";
370 $alignment = 8; 371 $alignment = 8;
diff --git a/security/integrity/digsig.c b/security/integrity/digsig.c
index 77ca965ab684..b4af4ebc5be2 100644
--- a/security/integrity/digsig.c
+++ b/security/integrity/digsig.c
@@ -13,9 +13,7 @@
13#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 13#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14 14
15#include <linux/err.h> 15#include <linux/err.h>
16#include <linux/sched.h>
17#include <linux/rbtree.h> 16#include <linux/rbtree.h>
18#include <linux/cred.h>
19#include <linux/key-type.h> 17#include <linux/key-type.h>
20#include <linux/digsig.h> 18#include <linux/digsig.h>
21 19
@@ -23,19 +21,11 @@
23 21
24static struct key *keyring[INTEGRITY_KEYRING_MAX]; 22static struct key *keyring[INTEGRITY_KEYRING_MAX];
25 23
26#ifdef CONFIG_IMA_TRUSTED_KEYRING
27static const char *keyring_name[INTEGRITY_KEYRING_MAX] = {
28 ".evm",
29 ".module",
30 ".ima",
31};
32#else
33static const char *keyring_name[INTEGRITY_KEYRING_MAX] = { 24static const char *keyring_name[INTEGRITY_KEYRING_MAX] = {
34 "_evm", 25 "_evm",
35 "_module", 26 "_module",
36 "_ima", 27 "_ima",
37}; 28};
38#endif
39 29
40int integrity_digsig_verify(const unsigned int id, const char *sig, int siglen, 30int integrity_digsig_verify(const unsigned int id, const char *sig, int siglen,
41 const char *digest, int digestlen) 31 const char *digest, int digestlen)
@@ -45,7 +35,7 @@ int integrity_digsig_verify(const unsigned int id, const char *sig, int siglen,
45 35
46 if (!keyring[id]) { 36 if (!keyring[id]) {
47 keyring[id] = 37 keyring[id] =
48 request_key(&key_type_keyring, keyring_name[id], NULL); 38 request_key(&key_type_keyring, keyring_name[id], NULL);
49 if (IS_ERR(keyring[id])) { 39 if (IS_ERR(keyring[id])) {
50 int err = PTR_ERR(keyring[id]); 40 int err = PTR_ERR(keyring[id]);
51 pr_err("no %s keyring: %d\n", keyring_name[id], err); 41 pr_err("no %s keyring: %d\n", keyring_name[id], err);
@@ -66,21 +56,3 @@ int integrity_digsig_verify(const unsigned int id, const char *sig, int siglen,
66 56
67 return -EOPNOTSUPP; 57 return -EOPNOTSUPP;
68} 58}
69
70int integrity_init_keyring(const unsigned int id)
71{
72 const struct cred *cred = current_cred();
73 const struct user_struct *user = cred->user;
74
75 keyring[id] = keyring_alloc(keyring_name[id], KUIDT_INIT(0),
76 KGIDT_INIT(0), cred,
77 ((KEY_POS_ALL & ~KEY_POS_SETATTR) |
78 KEY_USR_VIEW | KEY_USR_READ),
79 KEY_ALLOC_NOT_IN_QUOTA, user->uid_keyring);
80 if (!IS_ERR(keyring[id]))
81 set_bit(KEY_FLAG_TRUSTED_ONLY, &keyring[id]->flags);
82 else
83 pr_info("Can't allocate %s keyring (%ld)\n",
84 keyring_name[id], PTR_ERR(keyring[id]));
85 return 0;
86}
diff --git a/security/integrity/ima/Kconfig b/security/integrity/ima/Kconfig
index dad8d4ca2437..81a27971d884 100644
--- a/security/integrity/ima/Kconfig
+++ b/security/integrity/ima/Kconfig
@@ -123,11 +123,3 @@ config IMA_APPRAISE
123 For more information on integrity appraisal refer to: 123 For more information on integrity appraisal refer to:
124 <http://linux-ima.sourceforge.net> 124 <http://linux-ima.sourceforge.net>
125 If unsure, say N. 125 If unsure, say N.
126
127config IMA_TRUSTED_KEYRING
128 bool "Require all keys on the _ima keyring be signed"
129 depends on IMA_APPRAISE && SYSTEM_TRUSTED_KEYRING
130 default y
131 help
132 This option requires that all keys added to the _ima
133 keyring be signed by a key on the system trusted keyring.
diff --git a/security/integrity/ima/ima.h b/security/integrity/ima/ima.h
index bf03c6a16cc8..0356e1d437ca 100644
--- a/security/integrity/ima/ima.h
+++ b/security/integrity/ima/ima.h
@@ -26,7 +26,8 @@
26 26
27#include "../integrity.h" 27#include "../integrity.h"
28 28
29enum ima_show_type { IMA_SHOW_BINARY, IMA_SHOW_ASCII }; 29enum ima_show_type { IMA_SHOW_BINARY, IMA_SHOW_BINARY_NO_FIELD_LEN,
30 IMA_SHOW_ASCII };
30enum tpm_pcrs { TPM_PCR0 = 0, TPM_PCR8 = 8 }; 31enum tpm_pcrs { TPM_PCR0 = 0, TPM_PCR8 = 8 };
31 32
32/* digest size for IMA, fits SHA1 or MD5 */ 33/* digest size for IMA, fits SHA1 or MD5 */
@@ -97,7 +98,8 @@ int ima_add_template_entry(struct ima_template_entry *entry, int violation,
97 const char *op, struct inode *inode, 98 const char *op, struct inode *inode,
98 const unsigned char *filename); 99 const unsigned char *filename);
99int ima_calc_file_hash(struct file *file, struct ima_digest_data *hash); 100int ima_calc_file_hash(struct file *file, struct ima_digest_data *hash);
100int ima_calc_field_array_hash(struct ima_field_data *field_data, int num_fields, 101int ima_calc_field_array_hash(struct ima_field_data *field_data,
102 struct ima_template_desc *desc, int num_fields,
101 struct ima_digest_data *hash); 103 struct ima_digest_data *hash);
102int __init ima_calc_boot_aggregate(struct ima_digest_data *hash); 104int __init ima_calc_boot_aggregate(struct ima_digest_data *hash);
103void ima_add_violation(struct file *file, const unsigned char *filename, 105void ima_add_violation(struct file *file, const unsigned char *filename,
@@ -146,6 +148,7 @@ int ima_alloc_init_template(struct integrity_iint_cache *iint,
146 int xattr_len, struct ima_template_entry **entry); 148 int xattr_len, struct ima_template_entry **entry);
147int ima_store_template(struct ima_template_entry *entry, int violation, 149int ima_store_template(struct ima_template_entry *entry, int violation,
148 struct inode *inode, const unsigned char *filename); 150 struct inode *inode, const unsigned char *filename);
151void ima_free_template_entry(struct ima_template_entry *entry);
149const char *ima_d_path(struct path *path, char **pathbuf); 152const char *ima_d_path(struct path *path, char **pathbuf);
150 153
151/* rbtree tree calls to lookup, insert, delete 154/* rbtree tree calls to lookup, insert, delete
diff --git a/security/integrity/ima/ima_api.c b/security/integrity/ima/ima_api.c
index 0e7540863fc2..c38bbce8c6a6 100644
--- a/security/integrity/ima/ima_api.c
+++ b/security/integrity/ima/ima_api.c
@@ -22,6 +22,19 @@
22#include "ima.h" 22#include "ima.h"
23 23
24/* 24/*
25 * ima_free_template_entry - free an existing template entry
26 */
27void ima_free_template_entry(struct ima_template_entry *entry)
28{
29 int i;
30
31 for (i = 0; i < entry->template_desc->num_fields; i++)
32 kfree(entry->template_data[i].data);
33
34 kfree(entry);
35}
36
37/*
25 * ima_alloc_init_template - create and initialize a new template entry 38 * ima_alloc_init_template - create and initialize a new template entry
26 */ 39 */
27int ima_alloc_init_template(struct integrity_iint_cache *iint, 40int ima_alloc_init_template(struct integrity_iint_cache *iint,
@@ -37,6 +50,7 @@ int ima_alloc_init_template(struct integrity_iint_cache *iint,
37 if (!*entry) 50 if (!*entry)
38 return -ENOMEM; 51 return -ENOMEM;
39 52
53 (*entry)->template_desc = template_desc;
40 for (i = 0; i < template_desc->num_fields; i++) { 54 for (i = 0; i < template_desc->num_fields; i++) {
41 struct ima_template_field *field = template_desc->fields[i]; 55 struct ima_template_field *field = template_desc->fields[i];
42 u32 len; 56 u32 len;
@@ -51,10 +65,9 @@ int ima_alloc_init_template(struct integrity_iint_cache *iint,
51 (*entry)->template_data_len += sizeof(len); 65 (*entry)->template_data_len += sizeof(len);
52 (*entry)->template_data_len += len; 66 (*entry)->template_data_len += len;
53 } 67 }
54 (*entry)->template_desc = template_desc;
55 return 0; 68 return 0;
56out: 69out:
57 kfree(*entry); 70 ima_free_template_entry(*entry);
58 *entry = NULL; 71 *entry = NULL;
59 return result; 72 return result;
60} 73}
@@ -94,6 +107,7 @@ int ima_store_template(struct ima_template_entry *entry,
94 /* this function uses default algo */ 107 /* this function uses default algo */
95 hash.hdr.algo = HASH_ALGO_SHA1; 108 hash.hdr.algo = HASH_ALGO_SHA1;
96 result = ima_calc_field_array_hash(&entry->template_data[0], 109 result = ima_calc_field_array_hash(&entry->template_data[0],
110 entry->template_desc,
97 num_fields, &hash.hdr); 111 num_fields, &hash.hdr);
98 if (result < 0) { 112 if (result < 0) {
99 integrity_audit_msg(AUDIT_INTEGRITY_PCR, inode, 113 integrity_audit_msg(AUDIT_INTEGRITY_PCR, inode,
@@ -133,7 +147,7 @@ void ima_add_violation(struct file *file, const unsigned char *filename,
133 } 147 }
134 result = ima_store_template(entry, violation, inode, filename); 148 result = ima_store_template(entry, violation, inode, filename);
135 if (result < 0) 149 if (result < 0)
136 kfree(entry); 150 ima_free_template_entry(entry);
137err_out: 151err_out:
138 integrity_audit_msg(AUDIT_INTEGRITY_PCR, inode, filename, 152 integrity_audit_msg(AUDIT_INTEGRITY_PCR, inode, filename,
139 op, cause, result, 0); 153 op, cause, result, 0);
@@ -268,7 +282,7 @@ void ima_store_measurement(struct integrity_iint_cache *iint,
268 if (!result || result == -EEXIST) 282 if (!result || result == -EEXIST)
269 iint->flags |= IMA_MEASURED; 283 iint->flags |= IMA_MEASURED;
270 if (result < 0) 284 if (result < 0)
271 kfree(entry); 285 ima_free_template_entry(entry);
272} 286}
273 287
274void ima_audit_measurement(struct integrity_iint_cache *iint, 288void ima_audit_measurement(struct integrity_iint_cache *iint,
diff --git a/security/integrity/ima/ima_appraise.c b/security/integrity/ima/ima_appraise.c
index 46353ee517f6..734e9468aca0 100644
--- a/security/integrity/ima/ima_appraise.c
+++ b/security/integrity/ima/ima_appraise.c
@@ -381,14 +381,3 @@ int ima_inode_removexattr(struct dentry *dentry, const char *xattr_name)
381 } 381 }
382 return result; 382 return result;
383} 383}
384
385#ifdef CONFIG_IMA_TRUSTED_KEYRING
386static int __init init_ima_keyring(void)
387{
388 int ret;
389
390 ret = integrity_init_keyring(INTEGRITY_KEYRING_IMA);
391 return 0;
392}
393late_initcall(init_ima_keyring);
394#endif
diff --git a/security/integrity/ima/ima_crypto.c b/security/integrity/ima/ima_crypto.c
index 676e0292dfec..fdf60def52e9 100644
--- a/security/integrity/ima/ima_crypto.c
+++ b/security/integrity/ima/ima_crypto.c
@@ -140,6 +140,7 @@ int ima_calc_file_hash(struct file *file, struct ima_digest_data *hash)
140 * Calculate the hash of template data 140 * Calculate the hash of template data
141 */ 141 */
142static int ima_calc_field_array_hash_tfm(struct ima_field_data *field_data, 142static int ima_calc_field_array_hash_tfm(struct ima_field_data *field_data,
143 struct ima_template_desc *td,
143 int num_fields, 144 int num_fields,
144 struct ima_digest_data *hash, 145 struct ima_digest_data *hash,
145 struct crypto_shash *tfm) 146 struct crypto_shash *tfm)
@@ -160,9 +161,13 @@ static int ima_calc_field_array_hash_tfm(struct ima_field_data *field_data,
160 return rc; 161 return rc;
161 162
162 for (i = 0; i < num_fields; i++) { 163 for (i = 0; i < num_fields; i++) {
163 rc = crypto_shash_update(&desc.shash, 164 if (strcmp(td->name, IMA_TEMPLATE_IMA_NAME) != 0) {
164 (const u8 *) &field_data[i].len, 165 rc = crypto_shash_update(&desc.shash,
165 sizeof(field_data[i].len)); 166 (const u8 *) &field_data[i].len,
167 sizeof(field_data[i].len));
168 if (rc)
169 break;
170 }
166 rc = crypto_shash_update(&desc.shash, field_data[i].data, 171 rc = crypto_shash_update(&desc.shash, field_data[i].data,
167 field_data[i].len); 172 field_data[i].len);
168 if (rc) 173 if (rc)
@@ -175,7 +180,8 @@ static int ima_calc_field_array_hash_tfm(struct ima_field_data *field_data,
175 return rc; 180 return rc;
176} 181}
177 182
178int ima_calc_field_array_hash(struct ima_field_data *field_data, int num_fields, 183int ima_calc_field_array_hash(struct ima_field_data *field_data,
184 struct ima_template_desc *desc, int num_fields,
179 struct ima_digest_data *hash) 185 struct ima_digest_data *hash)
180{ 186{
181 struct crypto_shash *tfm; 187 struct crypto_shash *tfm;
@@ -185,7 +191,8 @@ int ima_calc_field_array_hash(struct ima_field_data *field_data, int num_fields,
185 if (IS_ERR(tfm)) 191 if (IS_ERR(tfm))
186 return PTR_ERR(tfm); 192 return PTR_ERR(tfm);
187 193
188 rc = ima_calc_field_array_hash_tfm(field_data, num_fields, hash, tfm); 194 rc = ima_calc_field_array_hash_tfm(field_data, desc, num_fields,
195 hash, tfm);
189 196
190 ima_free_tfm(tfm); 197 ima_free_tfm(tfm);
191 198
diff --git a/security/integrity/ima/ima_fs.c b/security/integrity/ima/ima_fs.c
index d47a7c86a21d..db01125926bd 100644
--- a/security/integrity/ima/ima_fs.c
+++ b/security/integrity/ima/ima_fs.c
@@ -120,6 +120,7 @@ static int ima_measurements_show(struct seq_file *m, void *v)
120 struct ima_template_entry *e; 120 struct ima_template_entry *e;
121 int namelen; 121 int namelen;
122 u32 pcr = CONFIG_IMA_MEASURE_PCR_IDX; 122 u32 pcr = CONFIG_IMA_MEASURE_PCR_IDX;
123 bool is_ima_template = false;
123 int i; 124 int i;
124 125
125 /* get entry */ 126 /* get entry */
@@ -145,14 +146,21 @@ static int ima_measurements_show(struct seq_file *m, void *v)
145 ima_putc(m, e->template_desc->name, namelen); 146 ima_putc(m, e->template_desc->name, namelen);
146 147
147 /* 5th: template length (except for 'ima' template) */ 148 /* 5th: template length (except for 'ima' template) */
148 if (strcmp(e->template_desc->name, IMA_TEMPLATE_IMA_NAME) != 0) 149 if (strcmp(e->template_desc->name, IMA_TEMPLATE_IMA_NAME) == 0)
150 is_ima_template = true;
151
152 if (!is_ima_template)
149 ima_putc(m, &e->template_data_len, 153 ima_putc(m, &e->template_data_len,
150 sizeof(e->template_data_len)); 154 sizeof(e->template_data_len));
151 155
152 /* 6th: template specific data */ 156 /* 6th: template specific data */
153 for (i = 0; i < e->template_desc->num_fields; i++) { 157 for (i = 0; i < e->template_desc->num_fields; i++) {
154 e->template_desc->fields[i]->field_show(m, IMA_SHOW_BINARY, 158 enum ima_show_type show = IMA_SHOW_BINARY;
155 &e->template_data[i]); 159 struct ima_template_field *field = e->template_desc->fields[i];
160
161 if (is_ima_template && strcmp(field->field_id, "d") == 0)
162 show = IMA_SHOW_BINARY_NO_FIELD_LEN;
163 field->field_show(m, show, &e->template_data[i]);
156 } 164 }
157 return 0; 165 return 0;
158} 166}
diff --git a/security/integrity/ima/ima_init.c b/security/integrity/ima/ima_init.c
index 15f34bd40abe..37122768554a 100644
--- a/security/integrity/ima/ima_init.c
+++ b/security/integrity/ima/ima_init.c
@@ -63,7 +63,6 @@ static void __init ima_add_boot_aggregate(void)
63 result = ima_calc_boot_aggregate(&hash.hdr); 63 result = ima_calc_boot_aggregate(&hash.hdr);
64 if (result < 0) { 64 if (result < 0) {
65 audit_cause = "hashing_error"; 65 audit_cause = "hashing_error";
66 kfree(entry);
67 goto err_out; 66 goto err_out;
68 } 67 }
69 } 68 }
@@ -76,7 +75,7 @@ static void __init ima_add_boot_aggregate(void)
76 result = ima_store_template(entry, violation, NULL, 75 result = ima_store_template(entry, violation, NULL,
77 boot_aggregate_name); 76 boot_aggregate_name);
78 if (result < 0) 77 if (result < 0)
79 kfree(entry); 78 ima_free_template_entry(entry);
80 return; 79 return;
81err_out: 80err_out:
82 integrity_audit_msg(AUDIT_INTEGRITY_PCR, NULL, boot_aggregate_name, op, 81 integrity_audit_msg(AUDIT_INTEGRITY_PCR, NULL, boot_aggregate_name, op,
diff --git a/security/integrity/ima/ima_template.c b/security/integrity/ima/ima_template.c
index 4e5da990630b..635695f6a185 100644
--- a/security/integrity/ima/ima_template.c
+++ b/security/integrity/ima/ima_template.c
@@ -90,7 +90,7 @@ static struct ima_template_field *lookup_template_field(const char *field_id)
90 return NULL; 90 return NULL;
91} 91}
92 92
93static int template_fmt_size(char *template_fmt) 93static int template_fmt_size(const char *template_fmt)
94{ 94{
95 char c; 95 char c;
96 int template_fmt_len = strlen(template_fmt); 96 int template_fmt_len = strlen(template_fmt);
@@ -106,22 +106,29 @@ static int template_fmt_size(char *template_fmt)
106 return j + 1; 106 return j + 1;
107} 107}
108 108
109static int template_desc_init_fields(char *template_fmt, 109static int template_desc_init_fields(const char *template_fmt,
110 struct ima_template_field ***fields, 110 struct ima_template_field ***fields,
111 int *num_fields) 111 int *num_fields)
112{ 112{
113 char *c, *template_fmt_ptr = template_fmt; 113 char *c, *template_fmt_copy, *template_fmt_ptr;
114 int template_num_fields = template_fmt_size(template_fmt); 114 int template_num_fields = template_fmt_size(template_fmt);
115 int i, result = 0; 115 int i, result = 0;
116 116
117 if (template_num_fields > IMA_TEMPLATE_NUM_FIELDS_MAX) 117 if (template_num_fields > IMA_TEMPLATE_NUM_FIELDS_MAX)
118 return -EINVAL; 118 return -EINVAL;
119 119
120 /* copying is needed as strsep() modifies the original buffer */
121 template_fmt_copy = kstrdup(template_fmt, GFP_KERNEL);
122 if (template_fmt_copy == NULL)
123 return -ENOMEM;
124
120 *fields = kzalloc(template_num_fields * sizeof(*fields), GFP_KERNEL); 125 *fields = kzalloc(template_num_fields * sizeof(*fields), GFP_KERNEL);
121 if (*fields == NULL) { 126 if (*fields == NULL) {
122 result = -ENOMEM; 127 result = -ENOMEM;
123 goto out; 128 goto out;
124 } 129 }
130
131 template_fmt_ptr = template_fmt_copy;
125 for (i = 0; (c = strsep(&template_fmt_ptr, "|")) != NULL && 132 for (i = 0; (c = strsep(&template_fmt_ptr, "|")) != NULL &&
126 i < template_num_fields; i++) { 133 i < template_num_fields; i++) {
127 struct ima_template_field *f = lookup_template_field(c); 134 struct ima_template_field *f = lookup_template_field(c);
@@ -133,10 +140,12 @@ static int template_desc_init_fields(char *template_fmt,
133 (*fields)[i] = f; 140 (*fields)[i] = f;
134 } 141 }
135 *num_fields = i; 142 *num_fields = i;
136 return 0;
137out: 143out:
138 kfree(*fields); 144 if (result < 0) {
139 *fields = NULL; 145 kfree(*fields);
146 *fields = NULL;
147 }
148 kfree(template_fmt_copy);
140 return result; 149 return result;
141} 150}
142 151
diff --git a/security/integrity/ima/ima_template_lib.c b/security/integrity/ima/ima_template_lib.c
index 6d66ad6ed265..c38adcc910fb 100644
--- a/security/integrity/ima/ima_template_lib.c
+++ b/security/integrity/ima/ima_template_lib.c
@@ -109,9 +109,12 @@ static void ima_show_template_data_binary(struct seq_file *m,
109 enum data_formats datafmt, 109 enum data_formats datafmt,
110 struct ima_field_data *field_data) 110 struct ima_field_data *field_data)
111{ 111{
112 ima_putc(m, &field_data->len, sizeof(u32)); 112 if (show != IMA_SHOW_BINARY_NO_FIELD_LEN)
113 ima_putc(m, &field_data->len, sizeof(u32));
114
113 if (!field_data->len) 115 if (!field_data->len)
114 return; 116 return;
117
115 ima_putc(m, field_data->data, field_data->len); 118 ima_putc(m, field_data->data, field_data->len);
116} 119}
117 120
@@ -125,6 +128,7 @@ static void ima_show_template_field_data(struct seq_file *m,
125 ima_show_template_data_ascii(m, show, datafmt, field_data); 128 ima_show_template_data_ascii(m, show, datafmt, field_data);
126 break; 129 break;
127 case IMA_SHOW_BINARY: 130 case IMA_SHOW_BINARY:
131 case IMA_SHOW_BINARY_NO_FIELD_LEN:
128 ima_show_template_data_binary(m, show, datafmt, field_data); 132 ima_show_template_data_binary(m, show, datafmt, field_data);
129 break; 133 break;
130 default: 134 default:
diff --git a/security/integrity/integrity.h b/security/integrity/integrity.h
index b9e7c133734a..2fb5e53e927f 100644
--- a/security/integrity/integrity.h
+++ b/security/integrity/integrity.h
@@ -137,19 +137,12 @@ static inline int integrity_digsig_verify(const unsigned int id,
137#ifdef CONFIG_INTEGRITY_ASYMMETRIC_KEYS 137#ifdef CONFIG_INTEGRITY_ASYMMETRIC_KEYS
138int asymmetric_verify(struct key *keyring, const char *sig, 138int asymmetric_verify(struct key *keyring, const char *sig,
139 int siglen, const char *data, int datalen); 139 int siglen, const char *data, int datalen);
140
141int integrity_init_keyring(const unsigned int id);
142#else 140#else
143static inline int asymmetric_verify(struct key *keyring, const char *sig, 141static inline int asymmetric_verify(struct key *keyring, const char *sig,
144 int siglen, const char *data, int datalen) 142 int siglen, const char *data, int datalen)
145{ 143{
146 return -EOPNOTSUPP; 144 return -EOPNOTSUPP;
147} 145}
148
149static int integrity_init_keyring(const unsigned int id)
150{
151 return 0;
152}
153#endif 146#endif
154 147
155#ifdef CONFIG_INTEGRITY_AUDIT 148#ifdef CONFIG_INTEGRITY_AUDIT
diff --git a/sound/atmel/abdac.c b/sound/atmel/abdac.c
index 872d59e35ee2..721d8fd45685 100644
--- a/sound/atmel/abdac.c
+++ b/sound/atmel/abdac.c
@@ -357,7 +357,8 @@ static int set_sample_rates(struct atmel_abdac *dac)
357 if (new_rate < 0) 357 if (new_rate < 0)
358 break; 358 break;
359 /* make sure we are below the ABDAC clock */ 359 /* make sure we are below the ABDAC clock */
360 if (new_rate <= clk_get_rate(dac->pclk)) { 360 if (index < MAX_NUM_RATES &&
361 new_rate <= clk_get_rate(dac->pclk)) {
361 dac->rates[index] = new_rate / 256; 362 dac->rates[index] = new_rate / 256;
362 index++; 363 index++;
363 } 364 }
diff --git a/sound/firewire/amdtp.c b/sound/firewire/amdtp.c
index d3226892ad6b..9048777228e2 100644
--- a/sound/firewire/amdtp.c
+++ b/sound/firewire/amdtp.c
@@ -434,17 +434,14 @@ static void queue_out_packet(struct amdtp_out_stream *s, unsigned int cycle)
434 return; 434 return;
435 index = s->packet_index; 435 index = s->packet_index;
436 436
437 /* this module generate empty packet for 'no data' */
437 syt = calculate_syt(s, cycle); 438 syt = calculate_syt(s, cycle);
438 if (!(s->flags & CIP_BLOCKING)) { 439 if (!(s->flags & CIP_BLOCKING))
439 data_blocks = calculate_data_blocks(s); 440 data_blocks = calculate_data_blocks(s);
440 } else { 441 else if (syt != 0xffff)
441 if (syt != 0xffff) { 442 data_blocks = s->syt_interval;
442 data_blocks = s->syt_interval; 443 else
443 } else { 444 data_blocks = 0;
444 data_blocks = 0;
445 syt = 0xffffff;
446 }
447 }
448 445
449 buffer = s->buffer.packets[index].buffer; 446 buffer = s->buffer.packets[index].buffer;
450 buffer[0] = cpu_to_be32(ACCESS_ONCE(s->source_node_id_field) | 447 buffer[0] = cpu_to_be32(ACCESS_ONCE(s->source_node_id_field) |
diff --git a/sound/firewire/dice.c b/sound/firewire/dice.c
index 57bcd31fcc12..c0aa64941cee 100644
--- a/sound/firewire/dice.c
+++ b/sound/firewire/dice.c
@@ -1019,7 +1019,7 @@ static void dice_proc_read(struct snd_info_entry *entry,
1019 1019
1020 if (dice_proc_read_mem(dice, &tx_rx_header, sections[2], 2) < 0) 1020 if (dice_proc_read_mem(dice, &tx_rx_header, sections[2], 2) < 0)
1021 return; 1021 return;
1022 quadlets = min_t(u32, tx_rx_header.size, sizeof(buf.tx)); 1022 quadlets = min_t(u32, tx_rx_header.size, sizeof(buf.tx) / 4);
1023 for (stream = 0; stream < tx_rx_header.number; ++stream) { 1023 for (stream = 0; stream < tx_rx_header.number; ++stream) {
1024 if (dice_proc_read_mem(dice, &buf.tx, sections[2] + 2 + 1024 if (dice_proc_read_mem(dice, &buf.tx, sections[2] + 2 +
1025 stream * tx_rx_header.size, 1025 stream * tx_rx_header.size,
@@ -1045,7 +1045,7 @@ static void dice_proc_read(struct snd_info_entry *entry,
1045 1045
1046 if (dice_proc_read_mem(dice, &tx_rx_header, sections[4], 2) < 0) 1046 if (dice_proc_read_mem(dice, &tx_rx_header, sections[4], 2) < 0)
1047 return; 1047 return;
1048 quadlets = min_t(u32, tx_rx_header.size, sizeof(buf.rx)); 1048 quadlets = min_t(u32, tx_rx_header.size, sizeof(buf.rx) / 4);
1049 for (stream = 0; stream < tx_rx_header.number; ++stream) { 1049 for (stream = 0; stream < tx_rx_header.number; ++stream) {
1050 if (dice_proc_read_mem(dice, &buf.rx, sections[4] + 2 + 1050 if (dice_proc_read_mem(dice, &buf.rx, sections[4] + 2 +
1051 stream * tx_rx_header.size, 1051 stream * tx_rx_header.size,
diff --git a/sound/pci/hda/hda_codec.h b/sound/pci/hda/hda_codec.h
index 77db69480c19..7aa9870040c1 100644
--- a/sound/pci/hda/hda_codec.h
+++ b/sound/pci/hda/hda_codec.h
@@ -698,7 +698,6 @@ struct hda_bus {
698 unsigned int in_reset:1; /* during reset operation */ 698 unsigned int in_reset:1; /* during reset operation */
699 unsigned int power_keep_link_on:1; /* don't power off HDA link */ 699 unsigned int power_keep_link_on:1; /* don't power off HDA link */
700 unsigned int no_response_fallback:1; /* don't fallback at RIRB error */ 700 unsigned int no_response_fallback:1; /* don't fallback at RIRB error */
701 unsigned int avoid_link_reset:1; /* don't reset link at runtime PM */
702 701
703 int primary_dig_out_type; /* primary digital out PCM type */ 702 int primary_dig_out_type; /* primary digital out PCM type */
704}; 703};
diff --git a/sound/pci/hda/hda_generic.c b/sound/pci/hda/hda_generic.c
index 3067ed4fe3b2..c4671d00babd 100644
--- a/sound/pci/hda/hda_generic.c
+++ b/sound/pci/hda/hda_generic.c
@@ -2506,12 +2506,8 @@ static int create_out_jack_modes(struct hda_codec *codec, int num_pins,
2506 2506
2507 for (i = 0; i < num_pins; i++) { 2507 for (i = 0; i < num_pins; i++) {
2508 hda_nid_t pin = pins[i]; 2508 hda_nid_t pin = pins[i];
2509 if (pin == spec->hp_mic_pin) { 2509 if (pin == spec->hp_mic_pin)
2510 int ret = create_hp_mic_jack_mode(codec, pin);
2511 if (ret < 0)
2512 return ret;
2513 continue; 2510 continue;
2514 }
2515 if (get_out_jack_num_items(codec, pin) > 1) { 2511 if (get_out_jack_num_items(codec, pin) > 1) {
2516 struct snd_kcontrol_new *knew; 2512 struct snd_kcontrol_new *knew;
2517 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 2513 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
@@ -2764,7 +2760,7 @@ static int hp_mic_jack_mode_put(struct snd_kcontrol *kcontrol,
2764 val &= ~(AC_PINCTL_VREFEN | PIN_HP); 2760 val &= ~(AC_PINCTL_VREFEN | PIN_HP);
2765 val |= get_vref_idx(vref_caps, idx) | PIN_IN; 2761 val |= get_vref_idx(vref_caps, idx) | PIN_IN;
2766 } else 2762 } else
2767 val = snd_hda_get_default_vref(codec, nid); 2763 val = snd_hda_get_default_vref(codec, nid) | PIN_IN;
2768 } 2764 }
2769 snd_hda_set_pin_ctl_cache(codec, nid, val); 2765 snd_hda_set_pin_ctl_cache(codec, nid, val);
2770 call_hp_automute(codec, NULL); 2766 call_hp_automute(codec, NULL);
@@ -2784,9 +2780,6 @@ static int create_hp_mic_jack_mode(struct hda_codec *codec, hda_nid_t pin)
2784 struct hda_gen_spec *spec = codec->spec; 2780 struct hda_gen_spec *spec = codec->spec;
2785 struct snd_kcontrol_new *knew; 2781 struct snd_kcontrol_new *knew;
2786 2782
2787 if (get_out_jack_num_items(codec, pin) <= 1 &&
2788 get_in_jack_num_items(codec, pin) <= 1)
2789 return 0; /* no need */
2790 knew = snd_hda_gen_add_kctl(spec, "Headphone Mic Jack Mode", 2783 knew = snd_hda_gen_add_kctl(spec, "Headphone Mic Jack Mode",
2791 &hp_mic_jack_mode_enum); 2784 &hp_mic_jack_mode_enum);
2792 if (!knew) 2785 if (!knew)
@@ -2815,6 +2808,42 @@ static int add_loopback_list(struct hda_gen_spec *spec, hda_nid_t mix, int idx)
2815 return 0; 2808 return 0;
2816} 2809}
2817 2810
2811/* return true if either a volume or a mute amp is found for the given
2812 * aamix path; the amp has to be either in the mixer node or its direct leaf
2813 */
2814static bool look_for_mix_leaf_ctls(struct hda_codec *codec, hda_nid_t mix_nid,
2815 hda_nid_t pin, unsigned int *mix_val,
2816 unsigned int *mute_val)
2817{
2818 int idx, num_conns;
2819 const hda_nid_t *list;
2820 hda_nid_t nid;
2821
2822 idx = snd_hda_get_conn_index(codec, mix_nid, pin, true);
2823 if (idx < 0)
2824 return false;
2825
2826 *mix_val = *mute_val = 0;
2827 if (nid_has_volume(codec, mix_nid, HDA_INPUT))
2828 *mix_val = HDA_COMPOSE_AMP_VAL(mix_nid, 3, idx, HDA_INPUT);
2829 if (nid_has_mute(codec, mix_nid, HDA_INPUT))
2830 *mute_val = HDA_COMPOSE_AMP_VAL(mix_nid, 3, idx, HDA_INPUT);
2831 if (*mix_val && *mute_val)
2832 return true;
2833
2834 /* check leaf node */
2835 num_conns = snd_hda_get_conn_list(codec, mix_nid, &list);
2836 if (num_conns < idx)
2837 return false;
2838 nid = list[idx];
2839 if (!*mix_val && nid_has_volume(codec, nid, HDA_OUTPUT))
2840 *mix_val = HDA_COMPOSE_AMP_VAL(nid, 3, 0, HDA_OUTPUT);
2841 if (!*mute_val && nid_has_mute(codec, nid, HDA_OUTPUT))
2842 *mute_val = HDA_COMPOSE_AMP_VAL(nid, 3, 0, HDA_OUTPUT);
2843
2844 return *mix_val || *mute_val;
2845}
2846
2818/* create input playback/capture controls for the given pin */ 2847/* create input playback/capture controls for the given pin */
2819static int new_analog_input(struct hda_codec *codec, int input_idx, 2848static int new_analog_input(struct hda_codec *codec, int input_idx,
2820 hda_nid_t pin, const char *ctlname, int ctlidx, 2849 hda_nid_t pin, const char *ctlname, int ctlidx,
@@ -2822,12 +2851,11 @@ static int new_analog_input(struct hda_codec *codec, int input_idx,
2822{ 2851{
2823 struct hda_gen_spec *spec = codec->spec; 2852 struct hda_gen_spec *spec = codec->spec;
2824 struct nid_path *path; 2853 struct nid_path *path;
2825 unsigned int val; 2854 unsigned int mix_val, mute_val;
2826 int err, idx; 2855 int err, idx;
2827 2856
2828 if (!nid_has_volume(codec, mix_nid, HDA_INPUT) && 2857 if (!look_for_mix_leaf_ctls(codec, mix_nid, pin, &mix_val, &mute_val))
2829 !nid_has_mute(codec, mix_nid, HDA_INPUT)) 2858 return 0;
2830 return 0; /* no need for analog loopback */
2831 2859
2832 path = snd_hda_add_new_path(codec, pin, mix_nid, 0); 2860 path = snd_hda_add_new_path(codec, pin, mix_nid, 0);
2833 if (!path) 2861 if (!path)
@@ -2836,20 +2864,18 @@ static int new_analog_input(struct hda_codec *codec, int input_idx,
2836 spec->loopback_paths[input_idx] = snd_hda_get_path_idx(codec, path); 2864 spec->loopback_paths[input_idx] = snd_hda_get_path_idx(codec, path);
2837 2865
2838 idx = path->idx[path->depth - 1]; 2866 idx = path->idx[path->depth - 1];
2839 if (nid_has_volume(codec, mix_nid, HDA_INPUT)) { 2867 if (mix_val) {
2840 val = HDA_COMPOSE_AMP_VAL(mix_nid, 3, idx, HDA_INPUT); 2868 err = __add_pb_vol_ctrl(spec, HDA_CTL_WIDGET_VOL, ctlname, ctlidx, mix_val);
2841 err = __add_pb_vol_ctrl(spec, HDA_CTL_WIDGET_VOL, ctlname, ctlidx, val);
2842 if (err < 0) 2869 if (err < 0)
2843 return err; 2870 return err;
2844 path->ctls[NID_PATH_VOL_CTL] = val; 2871 path->ctls[NID_PATH_VOL_CTL] = mix_val;
2845 } 2872 }
2846 2873
2847 if (nid_has_mute(codec, mix_nid, HDA_INPUT)) { 2874 if (mute_val) {
2848 val = HDA_COMPOSE_AMP_VAL(mix_nid, 3, idx, HDA_INPUT); 2875 err = __add_pb_sw_ctrl(spec, HDA_CTL_WIDGET_MUTE, ctlname, ctlidx, mute_val);
2849 err = __add_pb_sw_ctrl(spec, HDA_CTL_WIDGET_MUTE, ctlname, ctlidx, val);
2850 if (err < 0) 2876 if (err < 0)
2851 return err; 2877 return err;
2852 path->ctls[NID_PATH_MUTE_CTL] = val; 2878 path->ctls[NID_PATH_MUTE_CTL] = mute_val;
2853 } 2879 }
2854 2880
2855 path->active = true; 2881 path->active = true;
@@ -4383,6 +4409,17 @@ int snd_hda_gen_parse_auto_config(struct hda_codec *codec,
4383 if (err < 0) 4409 if (err < 0)
4384 return err; 4410 return err;
4385 4411
4412 /* create "Headphone Mic Jack Mode" if no input selection is
4413 * available (or user specifies add_jack_modes hint)
4414 */
4415 if (spec->hp_mic_pin &&
4416 (spec->auto_mic || spec->input_mux.num_items == 1 ||
4417 spec->add_jack_modes)) {
4418 err = create_hp_mic_jack_mode(codec, spec->hp_mic_pin);
4419 if (err < 0)
4420 return err;
4421 }
4422
4386 if (spec->add_jack_modes) { 4423 if (spec->add_jack_modes) {
4387 if (cfg->line_out_type != AUTO_PIN_SPEAKER_OUT) { 4424 if (cfg->line_out_type != AUTO_PIN_SPEAKER_OUT) {
4388 err = create_out_jack_modes(codec, cfg->line_outs, 4425 err = create_out_jack_modes(codec, cfg->line_outs,
diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
index 7a09404579a7..27aa14007cbd 100644
--- a/sound/pci/hda/hda_intel.c
+++ b/sound/pci/hda/hda_intel.c
@@ -2994,8 +2994,7 @@ static int azx_runtime_suspend(struct device *dev)
2994 STATESTS_INT_MASK); 2994 STATESTS_INT_MASK);
2995 2995
2996 azx_stop_chip(chip); 2996 azx_stop_chip(chip);
2997 if (!chip->bus->avoid_link_reset) 2997 azx_enter_link_reset(chip);
2998 azx_enter_link_reset(chip);
2999 azx_clear_irq_pending(chip); 2998 azx_clear_irq_pending(chip);
3000 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) 2999 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
3001 hda_display_power(false); 3000 hda_display_power(false);
@@ -3877,7 +3876,8 @@ static int azx_probe(struct pci_dev *pci,
3877 } 3876 }
3878 3877
3879 dev++; 3878 dev++;
3880 complete_all(&chip->probe_wait); 3879 if (chip->disabled)
3880 complete_all(&chip->probe_wait);
3881 return 0; 3881 return 0;
3882 3882
3883out_free: 3883out_free:
@@ -3954,10 +3954,10 @@ static int azx_probe_continue(struct azx *chip)
3954 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME) || chip->use_vga_switcheroo) 3954 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME) || chip->use_vga_switcheroo)
3955 pm_runtime_put_noidle(&pci->dev); 3955 pm_runtime_put_noidle(&pci->dev);
3956 3956
3957 return 0;
3958
3959out_free: 3957out_free:
3960 chip->init_failed = 1; 3958 if (err < 0)
3959 chip->init_failed = 1;
3960 complete_all(&chip->probe_wait);
3961 return err; 3961 return err;
3962} 3962}
3963 3963
diff --git a/sound/pci/hda/patch_analog.c b/sound/pci/hda/patch_analog.c
index 1a83559f4cbd..cac015be3325 100644
--- a/sound/pci/hda/patch_analog.c
+++ b/sound/pci/hda/patch_analog.c
@@ -147,6 +147,8 @@ static void ad_vmaster_eapd_hook(void *private_data, int enabled)
147 147
148 if (!spec->eapd_nid) 148 if (!spec->eapd_nid)
149 return; 149 return;
150 if (codec->inv_eapd)
151 enabled = !enabled;
150 snd_hda_codec_update_cache(codec, spec->eapd_nid, 0, 152 snd_hda_codec_update_cache(codec, spec->eapd_nid, 0,
151 AC_VERB_SET_EAPD_BTLENABLE, 153 AC_VERB_SET_EAPD_BTLENABLE,
152 enabled ? 0x02 : 0x00); 154 enabled ? 0x02 : 0x00);
@@ -359,6 +361,9 @@ static int patch_ad1986a(struct hda_codec *codec)
359 */ 361 */
360 spec->gen.multiout.no_share_stream = 1; 362 spec->gen.multiout.no_share_stream = 1;
361 363
364 /* AD1986A can't manage the dynamic pin on/off smoothly */
365 spec->gen.auto_mute_via_amp = 1;
366
362 snd_hda_pick_fixup(codec, ad1986a_fixup_models, ad1986a_fixup_tbl, 367 snd_hda_pick_fixup(codec, ad1986a_fixup_models, ad1986a_fixup_tbl,
363 ad1986a_fixups); 368 ad1986a_fixups);
364 snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PRE_PROBE); 369 snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PRE_PROBE);
@@ -962,6 +967,7 @@ static void ad1884_fixup_hp_eapd(struct hda_codec *codec,
962 switch (action) { 967 switch (action) {
963 case HDA_FIXUP_ACT_PRE_PROBE: 968 case HDA_FIXUP_ACT_PRE_PROBE:
964 spec->gen.vmaster_mute.hook = ad1884_vmaster_hp_gpio_hook; 969 spec->gen.vmaster_mute.hook = ad1884_vmaster_hp_gpio_hook;
970 spec->gen.own_eapd_ctl = 1;
965 snd_hda_sequence_write_cache(codec, gpio_init_verbs); 971 snd_hda_sequence_write_cache(codec, gpio_init_verbs);
966 break; 972 break;
967 case HDA_FIXUP_ACT_PROBE: 973 case HDA_FIXUP_ACT_PROBE:
diff --git a/sound/pci/hda/patch_conexant.c b/sound/pci/hda/patch_conexant.c
index c205bb1747fd..1f2717f817a0 100644
--- a/sound/pci/hda/patch_conexant.c
+++ b/sound/pci/hda/patch_conexant.c
@@ -3244,9 +3244,29 @@ enum {
3244#if IS_ENABLED(CONFIG_THINKPAD_ACPI) 3244#if IS_ENABLED(CONFIG_THINKPAD_ACPI)
3245 3245
3246#include <linux/thinkpad_acpi.h> 3246#include <linux/thinkpad_acpi.h>
3247#include <acpi/acpi.h>
3247 3248
3248static int (*led_set_func)(int, bool); 3249static int (*led_set_func)(int, bool);
3249 3250
3251static acpi_status acpi_check_cb(acpi_handle handle, u32 lvl, void *context,
3252 void **rv)
3253{
3254 bool *found = context;
3255 *found = true;
3256 return AE_OK;
3257}
3258
3259static bool is_thinkpad(struct hda_codec *codec)
3260{
3261 bool found = false;
3262 if (codec->subsystem_id >> 16 != 0x17aa)
3263 return false;
3264 if (ACPI_SUCCESS(acpi_get_devices("LEN0068", acpi_check_cb, &found, NULL)) && found)
3265 return true;
3266 found = false;
3267 return ACPI_SUCCESS(acpi_get_devices("IBM0068", acpi_check_cb, &found, NULL)) && found;
3268}
3269
3250static void update_tpacpi_mute_led(void *private_data, int enabled) 3270static void update_tpacpi_mute_led(void *private_data, int enabled)
3251{ 3271{
3252 struct hda_codec *codec = private_data; 3272 struct hda_codec *codec = private_data;
@@ -3279,6 +3299,8 @@ static void cxt_fixup_thinkpad_acpi(struct hda_codec *codec,
3279 bool removefunc = false; 3299 bool removefunc = false;
3280 3300
3281 if (action == HDA_FIXUP_ACT_PROBE) { 3301 if (action == HDA_FIXUP_ACT_PROBE) {
3302 if (!is_thinkpad(codec))
3303 return;
3282 if (!led_set_func) 3304 if (!led_set_func)
3283 led_set_func = symbol_request(tpacpi_led_set); 3305 led_set_func = symbol_request(tpacpi_led_set);
3284 if (!led_set_func) { 3306 if (!led_set_func) {
@@ -3494,6 +3516,7 @@ static const struct snd_pci_quirk cxt5066_fixups[] = {
3494 SND_PCI_QUIRK(0x17aa, 0x3975, "Lenovo U300s", CXT_FIXUP_STEREO_DMIC), 3516 SND_PCI_QUIRK(0x17aa, 0x3975, "Lenovo U300s", CXT_FIXUP_STEREO_DMIC),
3495 SND_PCI_QUIRK(0x17aa, 0x3977, "Lenovo IdeaPad U310", CXT_FIXUP_STEREO_DMIC), 3517 SND_PCI_QUIRK(0x17aa, 0x3977, "Lenovo IdeaPad U310", CXT_FIXUP_STEREO_DMIC),
3496 SND_PCI_QUIRK(0x17aa, 0x397b, "Lenovo S205", CXT_FIXUP_STEREO_DMIC), 3518 SND_PCI_QUIRK(0x17aa, 0x397b, "Lenovo S205", CXT_FIXUP_STEREO_DMIC),
3519 SND_PCI_QUIRK_VENDOR(0x17aa, "Thinkpad", CXT_FIXUP_THINKPAD_ACPI),
3497 SND_PCI_QUIRK(0x1c06, 0x2011, "Lemote A1004", CXT_PINCFG_LEMOTE_A1004), 3520 SND_PCI_QUIRK(0x1c06, 0x2011, "Lemote A1004", CXT_PINCFG_LEMOTE_A1004),
3498 SND_PCI_QUIRK(0x1c06, 0x2012, "Lemote A1205", CXT_PINCFG_LEMOTE_A1205), 3521 SND_PCI_QUIRK(0x1c06, 0x2012, "Lemote A1205", CXT_PINCFG_LEMOTE_A1205),
3499 {} 3522 {}
diff --git a/sound/pci/hda/patch_hdmi.c b/sound/pci/hda/patch_hdmi.c
index 08407bed093e..c4a66ef6cf6f 100644
--- a/sound/pci/hda/patch_hdmi.c
+++ b/sound/pci/hda/patch_hdmi.c
@@ -1142,32 +1142,34 @@ static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
1142 1142
1143static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll); 1143static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
1144 1144
1145static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res) 1145static void jack_callback(struct hda_codec *codec, struct hda_jack_tbl *jack)
1146{ 1146{
1147 struct hdmi_spec *spec = codec->spec; 1147 struct hdmi_spec *spec = codec->spec;
1148 int pin_idx = pin_nid_to_pin_index(spec, jack->nid);
1149 if (pin_idx < 0)
1150 return;
1151
1152 if (hdmi_present_sense(get_pin(spec, pin_idx), 1))
1153 snd_hda_jack_report_sync(codec);
1154}
1155
1156static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
1157{
1148 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 1158 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1149 int pin_nid;
1150 int pin_idx;
1151 struct hda_jack_tbl *jack; 1159 struct hda_jack_tbl *jack;
1152 int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT; 1160 int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
1153 1161
1154 jack = snd_hda_jack_tbl_get_from_tag(codec, tag); 1162 jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
1155 if (!jack) 1163 if (!jack)
1156 return; 1164 return;
1157 pin_nid = jack->nid;
1158 jack->jack_dirty = 1; 1165 jack->jack_dirty = 1;
1159 1166
1160 _snd_printd(SND_PR_VERBOSE, 1167 _snd_printd(SND_PR_VERBOSE,
1161 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n", 1168 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
1162 codec->addr, pin_nid, dev_entry, !!(res & AC_UNSOL_RES_IA), 1169 codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
1163 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV)); 1170 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
1164 1171
1165 pin_idx = pin_nid_to_pin_index(spec, pin_nid); 1172 jack_callback(codec, jack);
1166 if (pin_idx < 0)
1167 return;
1168
1169 if (hdmi_present_sense(get_pin(spec, pin_idx), 1))
1170 snd_hda_jack_report_sync(codec);
1171} 1173}
1172 1174
1173static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res) 1175static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
@@ -2095,7 +2097,8 @@ static int generic_hdmi_init(struct hda_codec *codec)
2095 hda_nid_t pin_nid = per_pin->pin_nid; 2097 hda_nid_t pin_nid = per_pin->pin_nid;
2096 2098
2097 hdmi_init_pin(codec, pin_nid); 2099 hdmi_init_pin(codec, pin_nid);
2098 snd_hda_jack_detect_enable(codec, pin_nid, pin_nid); 2100 snd_hda_jack_detect_enable_callback(codec, pin_nid, pin_nid,
2101 codec->jackpoll_interval > 0 ? jack_callback : NULL);
2099 } 2102 }
2100 return 0; 2103 return 0;
2101} 2104}
diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c
index 5e42059f10a1..c5ea483d7559 100644
--- a/sound/pci/hda/patch_realtek.c
+++ b/sound/pci/hda/patch_realtek.c
@@ -1780,8 +1780,11 @@ enum {
1780 ALC889_FIXUP_DAC_ROUTE, 1780 ALC889_FIXUP_DAC_ROUTE,
1781 ALC889_FIXUP_MBP_VREF, 1781 ALC889_FIXUP_MBP_VREF,
1782 ALC889_FIXUP_IMAC91_VREF, 1782 ALC889_FIXUP_IMAC91_VREF,
1783 ALC889_FIXUP_MBA21_VREF,
1783 ALC882_FIXUP_INV_DMIC, 1784 ALC882_FIXUP_INV_DMIC,
1784 ALC882_FIXUP_NO_PRIMARY_HP, 1785 ALC882_FIXUP_NO_PRIMARY_HP,
1786 ALC887_FIXUP_ASUS_BASS,
1787 ALC887_FIXUP_BASS_CHMAP,
1785}; 1788};
1786 1789
1787static void alc889_fixup_coef(struct hda_codec *codec, 1790static void alc889_fixup_coef(struct hda_codec *codec,
@@ -1882,17 +1885,13 @@ static void alc889_fixup_mbp_vref(struct hda_codec *codec,
1882 } 1885 }
1883} 1886}
1884 1887
1885/* Set VREF on speaker pins on imac91 */ 1888static void alc889_fixup_mac_pins(struct hda_codec *codec,
1886static void alc889_fixup_imac91_vref(struct hda_codec *codec, 1889 const hda_nid_t *nids, int num_nids)
1887 const struct hda_fixup *fix, int action)
1888{ 1890{
1889 struct alc_spec *spec = codec->spec; 1891 struct alc_spec *spec = codec->spec;
1890 static hda_nid_t nids[2] = { 0x18, 0x1a };
1891 int i; 1892 int i;
1892 1893
1893 if (action != HDA_FIXUP_ACT_INIT) 1894 for (i = 0; i < num_nids; i++) {
1894 return;
1895 for (i = 0; i < ARRAY_SIZE(nids); i++) {
1896 unsigned int val; 1895 unsigned int val;
1897 val = snd_hda_codec_get_pin_target(codec, nids[i]); 1896 val = snd_hda_codec_get_pin_target(codec, nids[i]);
1898 val |= AC_PINCTL_VREF_50; 1897 val |= AC_PINCTL_VREF_50;
@@ -1901,6 +1900,26 @@ static void alc889_fixup_imac91_vref(struct hda_codec *codec,
1901 spec->gen.keep_vref_in_automute = 1; 1900 spec->gen.keep_vref_in_automute = 1;
1902} 1901}
1903 1902
1903/* Set VREF on speaker pins on imac91 */
1904static void alc889_fixup_imac91_vref(struct hda_codec *codec,
1905 const struct hda_fixup *fix, int action)
1906{
1907 static hda_nid_t nids[2] = { 0x18, 0x1a };
1908
1909 if (action == HDA_FIXUP_ACT_INIT)
1910 alc889_fixup_mac_pins(codec, nids, ARRAY_SIZE(nids));
1911}
1912
1913/* Set VREF on speaker pins on mba21 */
1914static void alc889_fixup_mba21_vref(struct hda_codec *codec,
1915 const struct hda_fixup *fix, int action)
1916{
1917 static hda_nid_t nids[2] = { 0x18, 0x19 };
1918
1919 if (action == HDA_FIXUP_ACT_INIT)
1920 alc889_fixup_mac_pins(codec, nids, ARRAY_SIZE(nids));
1921}
1922
1904/* Don't take HP output as primary 1923/* Don't take HP output as primary
1905 * Strangely, the speaker output doesn't work on Vaio Z and some Vaio 1924 * Strangely, the speaker output doesn't work on Vaio Z and some Vaio
1906 * all-in-one desktop PCs (for example VGC-LN51JGB) through DAC 0x05 1925 * all-in-one desktop PCs (for example VGC-LN51JGB) through DAC 0x05
@@ -1915,6 +1934,9 @@ static void alc882_fixup_no_primary_hp(struct hda_codec *codec,
1915 } 1934 }
1916} 1935}
1917 1936
1937static void alc_fixup_bass_chmap(struct hda_codec *codec,
1938 const struct hda_fixup *fix, int action);
1939
1918static const struct hda_fixup alc882_fixups[] = { 1940static const struct hda_fixup alc882_fixups[] = {
1919 [ALC882_FIXUP_ABIT_AW9D_MAX] = { 1941 [ALC882_FIXUP_ABIT_AW9D_MAX] = {
1920 .type = HDA_FIXUP_PINS, 1942 .type = HDA_FIXUP_PINS,
@@ -2097,6 +2119,12 @@ static const struct hda_fixup alc882_fixups[] = {
2097 .chained = true, 2119 .chained = true,
2098 .chain_id = ALC882_FIXUP_GPIO1, 2120 .chain_id = ALC882_FIXUP_GPIO1,
2099 }, 2121 },
2122 [ALC889_FIXUP_MBA21_VREF] = {
2123 .type = HDA_FIXUP_FUNC,
2124 .v.func = alc889_fixup_mba21_vref,
2125 .chained = true,
2126 .chain_id = ALC889_FIXUP_MBP_VREF,
2127 },
2100 [ALC882_FIXUP_INV_DMIC] = { 2128 [ALC882_FIXUP_INV_DMIC] = {
2101 .type = HDA_FIXUP_FUNC, 2129 .type = HDA_FIXUP_FUNC,
2102 .v.func = alc_fixup_inv_dmic_0x12, 2130 .v.func = alc_fixup_inv_dmic_0x12,
@@ -2105,6 +2133,19 @@ static const struct hda_fixup alc882_fixups[] = {
2105 .type = HDA_FIXUP_FUNC, 2133 .type = HDA_FIXUP_FUNC,
2106 .v.func = alc882_fixup_no_primary_hp, 2134 .v.func = alc882_fixup_no_primary_hp,
2107 }, 2135 },
2136 [ALC887_FIXUP_ASUS_BASS] = {
2137 .type = HDA_FIXUP_PINS,
2138 .v.pins = (const struct hda_pintbl[]) {
2139 {0x16, 0x99130130}, /* bass speaker */
2140 {}
2141 },
2142 .chained = true,
2143 .chain_id = ALC887_FIXUP_BASS_CHMAP,
2144 },
2145 [ALC887_FIXUP_BASS_CHMAP] = {
2146 .type = HDA_FIXUP_FUNC,
2147 .v.func = alc_fixup_bass_chmap,
2148 },
2108}; 2149};
2109 2150
2110static const struct snd_pci_quirk alc882_fixup_tbl[] = { 2151static const struct snd_pci_quirk alc882_fixup_tbl[] = {
@@ -2138,6 +2179,7 @@ static const struct snd_pci_quirk alc882_fixup_tbl[] = {
2138 SND_PCI_QUIRK(0x1043, 0x1873, "ASUS W90V", ALC882_FIXUP_ASUS_W90V), 2179 SND_PCI_QUIRK(0x1043, 0x1873, "ASUS W90V", ALC882_FIXUP_ASUS_W90V),
2139 SND_PCI_QUIRK(0x1043, 0x1971, "Asus W2JC", ALC882_FIXUP_ASUS_W2JC), 2180 SND_PCI_QUIRK(0x1043, 0x1971, "Asus W2JC", ALC882_FIXUP_ASUS_W2JC),
2140 SND_PCI_QUIRK(0x1043, 0x835f, "Asus Eee 1601", ALC888_FIXUP_EEE1601), 2181 SND_PCI_QUIRK(0x1043, 0x835f, "Asus Eee 1601", ALC888_FIXUP_EEE1601),
2182 SND_PCI_QUIRK(0x1043, 0x84bc, "ASUS ET2700", ALC887_FIXUP_ASUS_BASS),
2141 SND_PCI_QUIRK(0x104d, 0x9047, "Sony Vaio TT", ALC889_FIXUP_VAIO_TT), 2183 SND_PCI_QUIRK(0x104d, 0x9047, "Sony Vaio TT", ALC889_FIXUP_VAIO_TT),
2142 SND_PCI_QUIRK(0x104d, 0x905a, "Sony Vaio Z", ALC882_FIXUP_NO_PRIMARY_HP), 2184 SND_PCI_QUIRK(0x104d, 0x905a, "Sony Vaio Z", ALC882_FIXUP_NO_PRIMARY_HP),
2143 SND_PCI_QUIRK(0x104d, 0x9043, "Sony Vaio VGC-LN51JGB", ALC882_FIXUP_NO_PRIMARY_HP), 2185 SND_PCI_QUIRK(0x104d, 0x9043, "Sony Vaio VGC-LN51JGB", ALC882_FIXUP_NO_PRIMARY_HP),
@@ -2153,7 +2195,7 @@ static const struct snd_pci_quirk alc882_fixup_tbl[] = {
2153 SND_PCI_QUIRK(0x106b, 0x3000, "iMac", ALC889_FIXUP_MBP_VREF), 2195 SND_PCI_QUIRK(0x106b, 0x3000, "iMac", ALC889_FIXUP_MBP_VREF),
2154 SND_PCI_QUIRK(0x106b, 0x3200, "iMac 7,1 Aluminum", ALC882_FIXUP_EAPD), 2196 SND_PCI_QUIRK(0x106b, 0x3200, "iMac 7,1 Aluminum", ALC882_FIXUP_EAPD),
2155 SND_PCI_QUIRK(0x106b, 0x3400, "MacBookAir 1,1", ALC889_FIXUP_MBP_VREF), 2197 SND_PCI_QUIRK(0x106b, 0x3400, "MacBookAir 1,1", ALC889_FIXUP_MBP_VREF),
2156 SND_PCI_QUIRK(0x106b, 0x3500, "MacBookAir 2,1", ALC889_FIXUP_MBP_VREF), 2198 SND_PCI_QUIRK(0x106b, 0x3500, "MacBookAir 2,1", ALC889_FIXUP_MBA21_VREF),
2157 SND_PCI_QUIRK(0x106b, 0x3600, "Macbook 3,1", ALC889_FIXUP_MBP_VREF), 2199 SND_PCI_QUIRK(0x106b, 0x3600, "Macbook 3,1", ALC889_FIXUP_MBP_VREF),
2158 SND_PCI_QUIRK(0x106b, 0x3800, "MacbookPro 4,1", ALC889_FIXUP_MBP_VREF), 2200 SND_PCI_QUIRK(0x106b, 0x3800, "MacbookPro 4,1", ALC889_FIXUP_MBP_VREF),
2159 SND_PCI_QUIRK(0x106b, 0x3e00, "iMac 24 Aluminum", ALC885_FIXUP_MACPRO_GPIO), 2201 SND_PCI_QUIRK(0x106b, 0x3e00, "iMac 24 Aluminum", ALC885_FIXUP_MACPRO_GPIO),
@@ -3268,6 +3310,7 @@ static void alc_headset_mode_ctia(struct hda_codec *codec)
3268 alc_write_coef_idx(codec, 0x18, 0x7388); 3310 alc_write_coef_idx(codec, 0x18, 0x7388);
3269 break; 3311 break;
3270 case 0x10ec0668: 3312 case 0x10ec0668:
3313 alc_write_coef_idx(codec, 0x11, 0x0001);
3271 alc_write_coef_idx(codec, 0x15, 0x0d60); 3314 alc_write_coef_idx(codec, 0x15, 0x0d60);
3272 alc_write_coef_idx(codec, 0xc3, 0x0000); 3315 alc_write_coef_idx(codec, 0xc3, 0x0000);
3273 break; 3316 break;
@@ -3296,6 +3339,7 @@ static void alc_headset_mode_omtp(struct hda_codec *codec)
3296 alc_write_coef_idx(codec, 0x18, 0x7388); 3339 alc_write_coef_idx(codec, 0x18, 0x7388);
3297 break; 3340 break;
3298 case 0x10ec0668: 3341 case 0x10ec0668:
3342 alc_write_coef_idx(codec, 0x11, 0x0001);
3299 alc_write_coef_idx(codec, 0x15, 0x0d50); 3343 alc_write_coef_idx(codec, 0x15, 0x0d50);
3300 alc_write_coef_idx(codec, 0xc3, 0x0000); 3344 alc_write_coef_idx(codec, 0xc3, 0x0000);
3301 break; 3345 break;
@@ -3581,11 +3625,6 @@ static void alc283_hp_automute_hook(struct hda_codec *codec,
3581 vref); 3625 vref);
3582} 3626}
3583 3627
3584static void alc283_chromebook_caps(struct hda_codec *codec)
3585{
3586 snd_hda_override_wcaps(codec, 0x03, 0);
3587}
3588
3589static void alc283_fixup_chromebook(struct hda_codec *codec, 3628static void alc283_fixup_chromebook(struct hda_codec *codec,
3590 const struct hda_fixup *fix, int action) 3629 const struct hda_fixup *fix, int action)
3591{ 3630{
@@ -3594,9 +3633,26 @@ static void alc283_fixup_chromebook(struct hda_codec *codec,
3594 3633
3595 switch (action) { 3634 switch (action) {
3596 case HDA_FIXUP_ACT_PRE_PROBE: 3635 case HDA_FIXUP_ACT_PRE_PROBE:
3597 alc283_chromebook_caps(codec); 3636 snd_hda_override_wcaps(codec, 0x03, 0);
3598 /* Disable AA-loopback as it causes white noise */ 3637 /* Disable AA-loopback as it causes white noise */
3599 spec->gen.mixer_nid = 0; 3638 spec->gen.mixer_nid = 0;
3639 break;
3640 case HDA_FIXUP_ACT_INIT:
3641 /* Enable Line1 input control by verb */
3642 val = alc_read_coef_idx(codec, 0x1a);
3643 alc_write_coef_idx(codec, 0x1a, val | (1 << 4));
3644 break;
3645 }
3646}
3647
3648static void alc283_fixup_sense_combo_jack(struct hda_codec *codec,
3649 const struct hda_fixup *fix, int action)
3650{
3651 struct alc_spec *spec = codec->spec;
3652 int val;
3653
3654 switch (action) {
3655 case HDA_FIXUP_ACT_PRE_PROBE:
3600 spec->gen.hp_automute_hook = alc283_hp_automute_hook; 3656 spec->gen.hp_automute_hook = alc283_hp_automute_hook;
3601 break; 3657 break;
3602 case HDA_FIXUP_ACT_INIT: 3658 case HDA_FIXUP_ACT_INIT:
@@ -3604,9 +3660,6 @@ static void alc283_fixup_chromebook(struct hda_codec *codec,
3604 /* Set to manual mode */ 3660 /* Set to manual mode */
3605 val = alc_read_coef_idx(codec, 0x06); 3661 val = alc_read_coef_idx(codec, 0x06);
3606 alc_write_coef_idx(codec, 0x06, val & ~0x000c); 3662 alc_write_coef_idx(codec, 0x06, val & ~0x000c);
3607 /* Enable Line1 input control by verb */
3608 val = alc_read_coef_idx(codec, 0x1a);
3609 alc_write_coef_idx(codec, 0x1a, val | (1 << 4));
3610 break; 3663 break;
3611 } 3664 }
3612} 3665}
@@ -3798,9 +3851,11 @@ enum {
3798 ALC271_FIXUP_HP_GATE_MIC_JACK, 3851 ALC271_FIXUP_HP_GATE_MIC_JACK,
3799 ALC269_FIXUP_ACER_AC700, 3852 ALC269_FIXUP_ACER_AC700,
3800 ALC269_FIXUP_LIMIT_INT_MIC_BOOST, 3853 ALC269_FIXUP_LIMIT_INT_MIC_BOOST,
3854 ALC269VB_FIXUP_ASUS_ZENBOOK,
3801 ALC269_FIXUP_LIMIT_INT_MIC_BOOST_MUTE_LED, 3855 ALC269_FIXUP_LIMIT_INT_MIC_BOOST_MUTE_LED,
3802 ALC269VB_FIXUP_ORDISSIMO_EVE2, 3856 ALC269VB_FIXUP_ORDISSIMO_EVE2,
3803 ALC283_FIXUP_CHROME_BOOK, 3857 ALC283_FIXUP_CHROME_BOOK,
3858 ALC283_FIXUP_SENSE_COMBO_JACK,
3804 ALC282_FIXUP_ASUS_TX300, 3859 ALC282_FIXUP_ASUS_TX300,
3805 ALC283_FIXUP_INT_MIC, 3860 ALC283_FIXUP_INT_MIC,
3806 ALC290_FIXUP_MONO_SPEAKERS, 3861 ALC290_FIXUP_MONO_SPEAKERS,
@@ -4075,6 +4130,12 @@ static const struct hda_fixup alc269_fixups[] = {
4075 .chained = true, 4130 .chained = true,
4076 .chain_id = ALC269_FIXUP_THINKPAD_ACPI, 4131 .chain_id = ALC269_FIXUP_THINKPAD_ACPI,
4077 }, 4132 },
4133 [ALC269VB_FIXUP_ASUS_ZENBOOK] = {
4134 .type = HDA_FIXUP_FUNC,
4135 .v.func = alc269_fixup_limit_int_mic_boost,
4136 .chained = true,
4137 .chain_id = ALC269VB_FIXUP_DMIC,
4138 },
4078 [ALC269_FIXUP_LIMIT_INT_MIC_BOOST_MUTE_LED] = { 4139 [ALC269_FIXUP_LIMIT_INT_MIC_BOOST_MUTE_LED] = {
4079 .type = HDA_FIXUP_FUNC, 4140 .type = HDA_FIXUP_FUNC,
4080 .v.func = alc269_fixup_limit_int_mic_boost, 4141 .v.func = alc269_fixup_limit_int_mic_boost,
@@ -4094,6 +4155,12 @@ static const struct hda_fixup alc269_fixups[] = {
4094 .type = HDA_FIXUP_FUNC, 4155 .type = HDA_FIXUP_FUNC,
4095 .v.func = alc283_fixup_chromebook, 4156 .v.func = alc283_fixup_chromebook,
4096 }, 4157 },
4158 [ALC283_FIXUP_SENSE_COMBO_JACK] = {
4159 .type = HDA_FIXUP_FUNC,
4160 .v.func = alc283_fixup_sense_combo_jack,
4161 .chained = true,
4162 .chain_id = ALC283_FIXUP_CHROME_BOOK,
4163 },
4097 [ALC282_FIXUP_ASUS_TX300] = { 4164 [ALC282_FIXUP_ASUS_TX300] = {
4098 .type = HDA_FIXUP_FUNC, 4165 .type = HDA_FIXUP_FUNC,
4099 .v.func = alc282_fixup_asus_tx300, 4166 .v.func = alc282_fixup_asus_tx300,
@@ -4176,6 +4243,7 @@ static const struct snd_pci_quirk alc269_fixup_tbl[] = {
4176 SND_PCI_QUIRK(0x1028, 0x0614, "Dell Inspiron 3135", ALC269_FIXUP_DELL1_MIC_NO_PRESENCE), 4243 SND_PCI_QUIRK(0x1028, 0x0614, "Dell Inspiron 3135", ALC269_FIXUP_DELL1_MIC_NO_PRESENCE),
4177 SND_PCI_QUIRK(0x1028, 0x0616, "Dell Vostro 5470", ALC290_FIXUP_MONO_SPEAKERS), 4244 SND_PCI_QUIRK(0x1028, 0x0616, "Dell Vostro 5470", ALC290_FIXUP_MONO_SPEAKERS),
4178 SND_PCI_QUIRK(0x1028, 0x061f, "Dell", ALC255_FIXUP_DELL1_MIC_NO_PRESENCE), 4245 SND_PCI_QUIRK(0x1028, 0x061f, "Dell", ALC255_FIXUP_DELL1_MIC_NO_PRESENCE),
4246 SND_PCI_QUIRK(0x1028, 0x0638, "Dell Inspiron 5439", ALC290_FIXUP_MONO_SPEAKERS),
4179 SND_PCI_QUIRK(0x1028, 0x063f, "Dell", ALC255_FIXUP_DELL1_MIC_NO_PRESENCE), 4247 SND_PCI_QUIRK(0x1028, 0x063f, "Dell", ALC255_FIXUP_DELL1_MIC_NO_PRESENCE),
4180 SND_PCI_QUIRK(0x1028, 0x15cc, "Dell X5 Precision", ALC269_FIXUP_DELL2_MIC_NO_PRESENCE), 4248 SND_PCI_QUIRK(0x1028, 0x15cc, "Dell X5 Precision", ALC269_FIXUP_DELL2_MIC_NO_PRESENCE),
4181 SND_PCI_QUIRK(0x1028, 0x15cd, "Dell X5 Precision", ALC269_FIXUP_DELL2_MIC_NO_PRESENCE), 4249 SND_PCI_QUIRK(0x1028, 0x15cd, "Dell X5 Precision", ALC269_FIXUP_DELL2_MIC_NO_PRESENCE),
@@ -4184,13 +4252,12 @@ static const struct snd_pci_quirk alc269_fixup_tbl[] = {
4184 SND_PCI_QUIRK(0x103c, 0x1973, "HP Pavilion", ALC269_FIXUP_HP_MUTE_LED_MIC1), 4252 SND_PCI_QUIRK(0x103c, 0x1973, "HP Pavilion", ALC269_FIXUP_HP_MUTE_LED_MIC1),
4185 SND_PCI_QUIRK(0x103c, 0x1983, "HP Pavilion", ALC269_FIXUP_HP_MUTE_LED_MIC1), 4253 SND_PCI_QUIRK(0x103c, 0x1983, "HP Pavilion", ALC269_FIXUP_HP_MUTE_LED_MIC1),
4186 SND_PCI_QUIRK(0x103c, 0x218b, "HP", ALC269_FIXUP_LIMIT_INT_MIC_BOOST_MUTE_LED), 4254 SND_PCI_QUIRK(0x103c, 0x218b, "HP", ALC269_FIXUP_LIMIT_INT_MIC_BOOST_MUTE_LED),
4187 SND_PCI_QUIRK(0x103c, 0x21ed, "HP Falco Chromebook", ALC283_FIXUP_CHROME_BOOK),
4188 SND_PCI_QUIRK_VENDOR(0x103c, "HP", ALC269_FIXUP_HP_MUTE_LED), 4255 SND_PCI_QUIRK_VENDOR(0x103c, "HP", ALC269_FIXUP_HP_MUTE_LED),
4189 SND_PCI_QUIRK(0x1043, 0x103f, "ASUS TX300", ALC282_FIXUP_ASUS_TX300), 4256 SND_PCI_QUIRK(0x1043, 0x103f, "ASUS TX300", ALC282_FIXUP_ASUS_TX300),
4190 SND_PCI_QUIRK(0x1043, 0x106d, "Asus K53BE", ALC269_FIXUP_LIMIT_INT_MIC_BOOST), 4257 SND_PCI_QUIRK(0x1043, 0x106d, "Asus K53BE", ALC269_FIXUP_LIMIT_INT_MIC_BOOST),
4191 SND_PCI_QUIRK(0x1043, 0x115d, "Asus 1015E", ALC269_FIXUP_LIMIT_INT_MIC_BOOST), 4258 SND_PCI_QUIRK(0x1043, 0x115d, "Asus 1015E", ALC269_FIXUP_LIMIT_INT_MIC_BOOST),
4192 SND_PCI_QUIRK(0x1043, 0x1427, "Asus Zenbook UX31E", ALC269VB_FIXUP_DMIC), 4259 SND_PCI_QUIRK(0x1043, 0x1427, "Asus Zenbook UX31E", ALC269VB_FIXUP_ASUS_ZENBOOK),
4193 SND_PCI_QUIRK(0x1043, 0x1517, "Asus Zenbook UX31A", ALC269VB_FIXUP_DMIC), 4260 SND_PCI_QUIRK(0x1043, 0x1517, "Asus Zenbook UX31A", ALC269VB_FIXUP_ASUS_ZENBOOK),
4194 SND_PCI_QUIRK(0x1043, 0x16e3, "ASUS UX50", ALC269_FIXUP_STEREO_DMIC), 4261 SND_PCI_QUIRK(0x1043, 0x16e3, "ASUS UX50", ALC269_FIXUP_STEREO_DMIC),
4195 SND_PCI_QUIRK(0x1043, 0x1a13, "Asus G73Jw", ALC269_FIXUP_ASUS_G73JW), 4262 SND_PCI_QUIRK(0x1043, 0x1a13, "Asus G73Jw", ALC269_FIXUP_ASUS_G73JW),
4196 SND_PCI_QUIRK(0x1043, 0x1b13, "Asus U41SV", ALC269_FIXUP_INV_DMIC), 4263 SND_PCI_QUIRK(0x1043, 0x1b13, "Asus U41SV", ALC269_FIXUP_INV_DMIC),
@@ -4292,6 +4359,8 @@ static const struct hda_model_fixup alc269_fixup_models[] = {
4292 {.id = ALC269_FIXUP_HP_GPIO_LED, .name = "hp-gpio-led"}, 4359 {.id = ALC269_FIXUP_HP_GPIO_LED, .name = "hp-gpio-led"},
4293 {.id = ALC269_FIXUP_DELL1_MIC_NO_PRESENCE, .name = "dell-headset-multi"}, 4360 {.id = ALC269_FIXUP_DELL1_MIC_NO_PRESENCE, .name = "dell-headset-multi"},
4294 {.id = ALC269_FIXUP_DELL2_MIC_NO_PRESENCE, .name = "dell-headset-dock"}, 4361 {.id = ALC269_FIXUP_DELL2_MIC_NO_PRESENCE, .name = "dell-headset-dock"},
4362 {.id = ALC283_FIXUP_CHROME_BOOK, .name = "alc283-chrome"},
4363 {.id = ALC283_FIXUP_SENSE_COMBO_JACK, .name = "alc283-sense-combo"},
4295 {} 4364 {}
4296}; 4365};
4297 4366
@@ -4467,6 +4536,7 @@ enum {
4467 ALC861_FIXUP_AMP_VREF_0F, 4536 ALC861_FIXUP_AMP_VREF_0F,
4468 ALC861_FIXUP_NO_JACK_DETECT, 4537 ALC861_FIXUP_NO_JACK_DETECT,
4469 ALC861_FIXUP_ASUS_A6RP, 4538 ALC861_FIXUP_ASUS_A6RP,
4539 ALC660_FIXUP_ASUS_W7J,
4470}; 4540};
4471 4541
4472/* On some laptops, VREF of pin 0x0f is abused for controlling the main amp */ 4542/* On some laptops, VREF of pin 0x0f is abused for controlling the main amp */
@@ -4516,10 +4586,22 @@ static const struct hda_fixup alc861_fixups[] = {
4516 .v.func = alc861_fixup_asus_amp_vref_0f, 4586 .v.func = alc861_fixup_asus_amp_vref_0f,
4517 .chained = true, 4587 .chained = true,
4518 .chain_id = ALC861_FIXUP_NO_JACK_DETECT, 4588 .chain_id = ALC861_FIXUP_NO_JACK_DETECT,
4589 },
4590 [ALC660_FIXUP_ASUS_W7J] = {
4591 .type = HDA_FIXUP_VERBS,
4592 .v.verbs = (const struct hda_verb[]) {
4593 /* ASUS W7J needs a magic pin setup on unused NID 0x10
4594 * for enabling outputs
4595 */
4596 {0x10, AC_VERB_SET_PIN_WIDGET_CONTROL, 0x24},
4597 { }
4598 },
4519 } 4599 }
4520}; 4600};
4521 4601
4522static const struct snd_pci_quirk alc861_fixup_tbl[] = { 4602static const struct snd_pci_quirk alc861_fixup_tbl[] = {
4603 SND_PCI_QUIRK(0x1043, 0x1253, "ASUS W7J", ALC660_FIXUP_ASUS_W7J),
4604 SND_PCI_QUIRK(0x1043, 0x1263, "ASUS Z35HL", ALC660_FIXUP_ASUS_W7J),
4523 SND_PCI_QUIRK(0x1043, 0x1393, "ASUS A6Rp", ALC861_FIXUP_ASUS_A6RP), 4605 SND_PCI_QUIRK(0x1043, 0x1393, "ASUS A6Rp", ALC861_FIXUP_ASUS_A6RP),
4524 SND_PCI_QUIRK_VENDOR(0x1043, "ASUS laptop", ALC861_FIXUP_AMP_VREF_0F), 4606 SND_PCI_QUIRK_VENDOR(0x1043, "ASUS laptop", ALC861_FIXUP_AMP_VREF_0F),
4525 SND_PCI_QUIRK(0x1462, 0x7254, "HP DX2200", ALC861_FIXUP_NO_JACK_DETECT), 4607 SND_PCI_QUIRK(0x1462, 0x7254, "HP DX2200", ALC861_FIXUP_NO_JACK_DETECT),
@@ -4715,7 +4797,7 @@ static const struct snd_pcm_chmap_elem asus_pcm_2_1_chmaps[] = {
4715}; 4797};
4716 4798
4717/* override the 2.1 chmap */ 4799/* override the 2.1 chmap */
4718static void alc662_fixup_bass_chmap(struct hda_codec *codec, 4800static void alc_fixup_bass_chmap(struct hda_codec *codec,
4719 const struct hda_fixup *fix, int action) 4801 const struct hda_fixup *fix, int action)
4720{ 4802{
4721 if (action == HDA_FIXUP_ACT_BUILD) { 4803 if (action == HDA_FIXUP_ACT_BUILD) {
@@ -4923,7 +5005,7 @@ static const struct hda_fixup alc662_fixups[] = {
4923 }, 5005 },
4924 [ALC662_FIXUP_BASS_CHMAP] = { 5006 [ALC662_FIXUP_BASS_CHMAP] = {
4925 .type = HDA_FIXUP_FUNC, 5007 .type = HDA_FIXUP_FUNC,
4926 .v.func = alc662_fixup_bass_chmap, 5008 .v.func = alc_fixup_bass_chmap,
4927 .chained = true, 5009 .chained = true,
4928 .chain_id = ALC662_FIXUP_ASUS_MODE4 5010 .chain_id = ALC662_FIXUP_ASUS_MODE4
4929 }, 5011 },
@@ -4936,7 +5018,7 @@ static const struct hda_fixup alc662_fixups[] = {
4936 }, 5018 },
4937 [ALC662_FIXUP_BASS_1A_CHMAP] = { 5019 [ALC662_FIXUP_BASS_1A_CHMAP] = {
4938 .type = HDA_FIXUP_FUNC, 5020 .type = HDA_FIXUP_FUNC,
4939 .v.func = alc662_fixup_bass_chmap, 5021 .v.func = alc_fixup_bass_chmap,
4940 .chained = true, 5022 .chained = true,
4941 .chain_id = ALC662_FIXUP_BASS_1A, 5023 .chain_id = ALC662_FIXUP_BASS_1A,
4942 }, 5024 },
@@ -5118,6 +5200,7 @@ static int patch_alc662(struct hda_codec *codec)
5118 case 0x10ec0272: 5200 case 0x10ec0272:
5119 case 0x10ec0663: 5201 case 0x10ec0663:
5120 case 0x10ec0665: 5202 case 0x10ec0665:
5203 case 0x10ec0668:
5121 set_beep_amp(spec, 0x0b, 0x04, HDA_INPUT); 5204 set_beep_amp(spec, 0x0b, 0x04, HDA_INPUT);
5122 break; 5205 break;
5123 case 0x10ec0273: 5206 case 0x10ec0273:
@@ -5175,6 +5258,7 @@ static int patch_alc680(struct hda_codec *codec)
5175 */ 5258 */
5176static const struct hda_codec_preset snd_hda_preset_realtek[] = { 5259static const struct hda_codec_preset snd_hda_preset_realtek[] = {
5177 { .id = 0x10ec0221, .name = "ALC221", .patch = patch_alc269 }, 5260 { .id = 0x10ec0221, .name = "ALC221", .patch = patch_alc269 },
5261 { .id = 0x10ec0231, .name = "ALC231", .patch = patch_alc269 },
5178 { .id = 0x10ec0233, .name = "ALC233", .patch = patch_alc269 }, 5262 { .id = 0x10ec0233, .name = "ALC233", .patch = patch_alc269 },
5179 { .id = 0x10ec0255, .name = "ALC255", .patch = patch_alc269 }, 5263 { .id = 0x10ec0255, .name = "ALC255", .patch = patch_alc269 },
5180 { .id = 0x10ec0260, .name = "ALC260", .patch = patch_alc260 }, 5264 { .id = 0x10ec0260, .name = "ALC260", .patch = patch_alc260 },
diff --git a/sound/pci/hda/patch_sigmatel.c b/sound/pci/hda/patch_sigmatel.c
index d2cc0041d9d3..088a5afbd1b9 100644
--- a/sound/pci/hda/patch_sigmatel.c
+++ b/sound/pci/hda/patch_sigmatel.c
@@ -2094,7 +2094,8 @@ static void stac92hd83xxx_fixup_hp_mic_led(struct hda_codec *codec,
2094 2094
2095 if (action == HDA_FIXUP_ACT_PRE_PROBE) { 2095 if (action == HDA_FIXUP_ACT_PRE_PROBE) {
2096 spec->mic_mute_led_gpio = 0x08; /* GPIO3 */ 2096 spec->mic_mute_led_gpio = 0x08; /* GPIO3 */
2097 codec->bus->avoid_link_reset = 1; 2097 /* resetting controller clears GPIO, so we need to keep on */
2098 codec->bus->power_keep_link_on = 1;
2098 } 2099 }
2099} 2100}
2100 2101
diff --git a/sound/soc/atmel/sam9x5_wm8731.c b/sound/soc/atmel/sam9x5_wm8731.c
index 992ae38d5a15..1b372283bd01 100644
--- a/sound/soc/atmel/sam9x5_wm8731.c
+++ b/sound/soc/atmel/sam9x5_wm8731.c
@@ -97,6 +97,8 @@ static int sam9x5_wm8731_driver_probe(struct platform_device *pdev)
97 goto out; 97 goto out;
98 } 98 }
99 99
100 snd_soc_card_set_drvdata(card, priv);
101
100 card->dev = &pdev->dev; 102 card->dev = &pdev->dev;
101 card->owner = THIS_MODULE; 103 card->owner = THIS_MODULE;
102 card->dai_link = dai; 104 card->dai_link = dai;
diff --git a/sound/soc/codecs/wm5110.c b/sound/soc/codecs/wm5110.c
index c3c7396a6181..99b359e19d35 100644
--- a/sound/soc/codecs/wm5110.c
+++ b/sound/soc/codecs/wm5110.c
@@ -248,19 +248,6 @@ ARIZONA_MIXER_CONTROLS("SPKDAT1R", ARIZONA_OUT5RMIX_INPUT_1_SOURCE),
248ARIZONA_MIXER_CONTROLS("SPKDAT2L", ARIZONA_OUT6LMIX_INPUT_1_SOURCE), 248ARIZONA_MIXER_CONTROLS("SPKDAT2L", ARIZONA_OUT6LMIX_INPUT_1_SOURCE),
249ARIZONA_MIXER_CONTROLS("SPKDAT2R", ARIZONA_OUT6RMIX_INPUT_1_SOURCE), 249ARIZONA_MIXER_CONTROLS("SPKDAT2R", ARIZONA_OUT6RMIX_INPUT_1_SOURCE),
250 250
251SOC_SINGLE("HPOUT1 High Performance Switch", ARIZONA_OUTPUT_PATH_CONFIG_1L,
252 ARIZONA_OUT1_OSR_SHIFT, 1, 0),
253SOC_SINGLE("HPOUT2 High Performance Switch", ARIZONA_OUTPUT_PATH_CONFIG_2L,
254 ARIZONA_OUT2_OSR_SHIFT, 1, 0),
255SOC_SINGLE("HPOUT3 High Performance Switch", ARIZONA_OUTPUT_PATH_CONFIG_3L,
256 ARIZONA_OUT3_OSR_SHIFT, 1, 0),
257SOC_SINGLE("Speaker High Performance Switch", ARIZONA_OUTPUT_PATH_CONFIG_4L,
258 ARIZONA_OUT4_OSR_SHIFT, 1, 0),
259SOC_SINGLE("SPKDAT1 High Performance Switch", ARIZONA_OUTPUT_PATH_CONFIG_5L,
260 ARIZONA_OUT5_OSR_SHIFT, 1, 0),
261SOC_SINGLE("SPKDAT2 High Performance Switch", ARIZONA_OUTPUT_PATH_CONFIG_6L,
262 ARIZONA_OUT6_OSR_SHIFT, 1, 0),
263
264SOC_DOUBLE_R("HPOUT1 Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_1L, 251SOC_DOUBLE_R("HPOUT1 Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_1L,
265 ARIZONA_DAC_DIGITAL_VOLUME_1R, ARIZONA_OUT1L_MUTE_SHIFT, 1, 1), 252 ARIZONA_DAC_DIGITAL_VOLUME_1R, ARIZONA_OUT1L_MUTE_SHIFT, 1, 1),
266SOC_DOUBLE_R("HPOUT2 Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_2L, 253SOC_DOUBLE_R("HPOUT2 Digital Switch", ARIZONA_DAC_DIGITAL_VOLUME_2L,
@@ -293,18 +280,6 @@ SOC_DOUBLE_R_TLV("SPKDAT2 Digital Volume", ARIZONA_DAC_DIGITAL_VOLUME_6L,
293 ARIZONA_DAC_DIGITAL_VOLUME_6R, ARIZONA_OUT6L_VOL_SHIFT, 280 ARIZONA_DAC_DIGITAL_VOLUME_6R, ARIZONA_OUT6L_VOL_SHIFT,
294 0xbf, 0, digital_tlv), 281 0xbf, 0, digital_tlv),
295 282
296SOC_DOUBLE_R_RANGE_TLV("HPOUT1 Volume", ARIZONA_OUTPUT_PATH_CONFIG_1L,
297 ARIZONA_OUTPUT_PATH_CONFIG_1R,
298 ARIZONA_OUT1L_PGA_VOL_SHIFT,
299 0x34, 0x40, 0, ana_tlv),
300SOC_DOUBLE_R_RANGE_TLV("HPOUT2 Volume", ARIZONA_OUTPUT_PATH_CONFIG_2L,
301 ARIZONA_OUTPUT_PATH_CONFIG_2R,
302 ARIZONA_OUT2L_PGA_VOL_SHIFT,
303 0x34, 0x40, 0, ana_tlv),
304SOC_DOUBLE_R_RANGE_TLV("HPOUT3 Volume", ARIZONA_OUTPUT_PATH_CONFIG_3L,
305 ARIZONA_OUTPUT_PATH_CONFIG_3R,
306 ARIZONA_OUT3L_PGA_VOL_SHIFT, 0x34, 0x40, 0, ana_tlv),
307
308SOC_DOUBLE("SPKDAT1 Switch", ARIZONA_PDM_SPK1_CTRL_1, ARIZONA_SPK1L_MUTE_SHIFT, 283SOC_DOUBLE("SPKDAT1 Switch", ARIZONA_PDM_SPK1_CTRL_1, ARIZONA_SPK1L_MUTE_SHIFT,
309 ARIZONA_SPK1R_MUTE_SHIFT, 1, 1), 284 ARIZONA_SPK1R_MUTE_SHIFT, 1, 1),
310SOC_DOUBLE("SPKDAT2 Switch", ARIZONA_PDM_SPK2_CTRL_1, ARIZONA_SPK2L_MUTE_SHIFT, 285SOC_DOUBLE("SPKDAT2 Switch", ARIZONA_PDM_SPK2_CTRL_1, ARIZONA_SPK2L_MUTE_SHIFT,
diff --git a/sound/soc/codecs/wm8731.c b/sound/soc/codecs/wm8731.c
index 456bb8c6d759..bc7472c968e3 100644
--- a/sound/soc/codecs/wm8731.c
+++ b/sound/soc/codecs/wm8731.c
@@ -447,10 +447,10 @@ static int wm8731_set_dai_fmt(struct snd_soc_dai *codec_dai,
447 iface |= 0x0001; 447 iface |= 0x0001;
448 break; 448 break;
449 case SND_SOC_DAIFMT_DSP_A: 449 case SND_SOC_DAIFMT_DSP_A:
450 iface |= 0x0003; 450 iface |= 0x0013;
451 break; 451 break;
452 case SND_SOC_DAIFMT_DSP_B: 452 case SND_SOC_DAIFMT_DSP_B:
453 iface |= 0x0013; 453 iface |= 0x0003;
454 break; 454 break;
455 default: 455 default:
456 return -EINVAL; 456 return -EINVAL;
diff --git a/sound/soc/codecs/wm8990.c b/sound/soc/codecs/wm8990.c
index 253c88bb7a4c..4f05fb88bddf 100644
--- a/sound/soc/codecs/wm8990.c
+++ b/sound/soc/codecs/wm8990.c
@@ -1259,6 +1259,8 @@ static int wm8990_set_bias_level(struct snd_soc_codec *codec,
1259 1259
1260 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */ 1260 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
1261 snd_soc_write(codec, WM8990_ANTIPOP2, 0x0); 1261 snd_soc_write(codec, WM8990_ANTIPOP2, 0x0);
1262
1263 codec->cache_sync = 1;
1262 break; 1264 break;
1263 } 1265 }
1264 1266
diff --git a/sound/soc/fsl/pcm030-audio-fabric.c b/sound/soc/fsl/pcm030-audio-fabric.c
index eb4373840bb6..3665f612819d 100644
--- a/sound/soc/fsl/pcm030-audio-fabric.c
+++ b/sound/soc/fsl/pcm030-audio-fabric.c
@@ -69,7 +69,6 @@ static int pcm030_fabric_probe(struct platform_device *op)
69 return -ENOMEM; 69 return -ENOMEM;
70 70
71 card->dev = &op->dev; 71 card->dev = &op->dev;
72 platform_set_drvdata(op, pdata);
73 72
74 pdata->card = card; 73 pdata->card = card;
75 74
@@ -98,6 +97,8 @@ static int pcm030_fabric_probe(struct platform_device *op)
98 if (ret) 97 if (ret)
99 dev_err(&op->dev, "snd_soc_register_card() failed: %d\n", ret); 98 dev_err(&op->dev, "snd_soc_register_card() failed: %d\n", ret);
100 99
100 platform_set_drvdata(op, pdata);
101
101 return ret; 102 return ret;
102} 103}
103 104
diff --git a/sound/soc/kirkwood/kirkwood-i2s.c b/sound/soc/kirkwood/kirkwood-i2s.c
index d34d91743e3f..0b18f654b413 100644
--- a/sound/soc/kirkwood/kirkwood-i2s.c
+++ b/sound/soc/kirkwood/kirkwood-i2s.c
@@ -33,6 +33,10 @@
33 SNDRV_PCM_FMTBIT_S24_LE | \ 33 SNDRV_PCM_FMTBIT_S24_LE | \
34 SNDRV_PCM_FMTBIT_S32_LE) 34 SNDRV_PCM_FMTBIT_S32_LE)
35 35
36#define KIRKWOOD_SPDIF_FORMATS \
37 (SNDRV_PCM_FMTBIT_S16_LE | \
38 SNDRV_PCM_FMTBIT_S24_LE)
39
36static int kirkwood_i2s_set_fmt(struct snd_soc_dai *cpu_dai, 40static int kirkwood_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
37 unsigned int fmt) 41 unsigned int fmt)
38{ 42{
@@ -244,15 +248,15 @@ static int kirkwood_i2s_play_trigger(struct snd_pcm_substream *substream,
244 ctl); 248 ctl);
245 } 249 }
246 250
247 if (dai->id == 0)
248 ctl &= ~KIRKWOOD_PLAYCTL_SPDIF_EN; /* i2s */
249 else
250 ctl &= ~KIRKWOOD_PLAYCTL_I2S_EN; /* spdif */
251
252 switch (cmd) { 251 switch (cmd) {
253 case SNDRV_PCM_TRIGGER_START: 252 case SNDRV_PCM_TRIGGER_START:
254 /* configure */ 253 /* configure */
255 ctl = priv->ctl_play; 254 ctl = priv->ctl_play;
255 if (dai->id == 0)
256 ctl &= ~KIRKWOOD_PLAYCTL_SPDIF_EN; /* i2s */
257 else
258 ctl &= ~KIRKWOOD_PLAYCTL_I2S_EN; /* spdif */
259
256 value = ctl & ~KIRKWOOD_PLAYCTL_ENABLE_MASK; 260 value = ctl & ~KIRKWOOD_PLAYCTL_ENABLE_MASK;
257 writel(value, priv->io + KIRKWOOD_PLAYCTL); 261 writel(value, priv->io + KIRKWOOD_PLAYCTL);
258 262
@@ -449,14 +453,14 @@ static struct snd_soc_dai_driver kirkwood_i2s_dai[2] = {
449 .channels_max = 2, 453 .channels_max = 2,
450 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | 454 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |
451 SNDRV_PCM_RATE_96000, 455 SNDRV_PCM_RATE_96000,
452 .formats = KIRKWOOD_I2S_FORMATS, 456 .formats = KIRKWOOD_SPDIF_FORMATS,
453 }, 457 },
454 .capture = { 458 .capture = {
455 .channels_min = 1, 459 .channels_min = 1,
456 .channels_max = 2, 460 .channels_max = 2,
457 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | 461 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |
458 SNDRV_PCM_RATE_96000, 462 SNDRV_PCM_RATE_96000,
459 .formats = KIRKWOOD_I2S_FORMATS, 463 .formats = KIRKWOOD_SPDIF_FORMATS,
460 }, 464 },
461 .ops = &kirkwood_i2s_dai_ops, 465 .ops = &kirkwood_i2s_dai_ops,
462 }, 466 },
@@ -493,7 +497,7 @@ static struct snd_soc_dai_driver kirkwood_i2s_dai_extclk[2] = {
493 .rates = SNDRV_PCM_RATE_8000_192000 | 497 .rates = SNDRV_PCM_RATE_8000_192000 |
494 SNDRV_PCM_RATE_CONTINUOUS | 498 SNDRV_PCM_RATE_CONTINUOUS |
495 SNDRV_PCM_RATE_KNOT, 499 SNDRV_PCM_RATE_KNOT,
496 .formats = KIRKWOOD_I2S_FORMATS, 500 .formats = KIRKWOOD_SPDIF_FORMATS,
497 }, 501 },
498 .capture = { 502 .capture = {
499 .channels_min = 1, 503 .channels_min = 1,
@@ -501,7 +505,7 @@ static struct snd_soc_dai_driver kirkwood_i2s_dai_extclk[2] = {
501 .rates = SNDRV_PCM_RATE_8000_192000 | 505 .rates = SNDRV_PCM_RATE_8000_192000 |
502 SNDRV_PCM_RATE_CONTINUOUS | 506 SNDRV_PCM_RATE_CONTINUOUS |
503 SNDRV_PCM_RATE_KNOT, 507 SNDRV_PCM_RATE_KNOT,
504 .formats = KIRKWOOD_I2S_FORMATS, 508 .formats = KIRKWOOD_SPDIF_FORMATS,
505 }, 509 },
506 .ops = &kirkwood_i2s_dai_ops, 510 .ops = &kirkwood_i2s_dai_ops,
507 }, 511 },
diff --git a/sound/soc/omap/n810.c b/sound/soc/omap/n810.c
index 6d216cb6c19b..3fde9e402710 100644
--- a/sound/soc/omap/n810.c
+++ b/sound/soc/omap/n810.c
@@ -100,12 +100,12 @@ static int n810_startup(struct snd_pcm_substream *substream)
100 SNDRV_PCM_HW_PARAM_CHANNELS, 2, 2); 100 SNDRV_PCM_HW_PARAM_CHANNELS, 2, 2);
101 101
102 n810_ext_control(&codec->dapm); 102 n810_ext_control(&codec->dapm);
103 return clk_enable(sys_clkout2); 103 return clk_prepare_enable(sys_clkout2);
104} 104}
105 105
106static void n810_shutdown(struct snd_pcm_substream *substream) 106static void n810_shutdown(struct snd_pcm_substream *substream)
107{ 107{
108 clk_disable(sys_clkout2); 108 clk_disable_unprepare(sys_clkout2);
109} 109}
110 110
111static int n810_hw_params(struct snd_pcm_substream *substream, 111static int n810_hw_params(struct snd_pcm_substream *substream,
diff --git a/sound/soc/sh/Kconfig b/sound/soc/sh/Kconfig
index 14011d90d70a..ff60e11ecb56 100644
--- a/sound/soc/sh/Kconfig
+++ b/sound/soc/sh/Kconfig
@@ -37,6 +37,7 @@ config SND_SOC_SH4_SIU
37config SND_SOC_RCAR 37config SND_SOC_RCAR
38 tristate "R-Car series SRU/SCU/SSIU/SSI support" 38 tristate "R-Car series SRU/SCU/SSIU/SSI support"
39 select SND_SIMPLE_CARD 39 select SND_SIMPLE_CARD
40 select REGMAP
40 help 41 help
41 This option enables R-Car SUR/SCU/SSIU/SSI sound support 42 This option enables R-Car SUR/SCU/SSIU/SSI sound support
42 43
diff --git a/sound/soc/soc-core.c b/sound/soc/soc-core.c
index 4e53d87e881d..a66783e13a9c 100644
--- a/sound/soc/soc-core.c
+++ b/sound/soc/soc-core.c
@@ -3212,11 +3212,11 @@ int snd_soc_bytes_get(struct snd_kcontrol *kcontrol,
3212 break; 3212 break;
3213 case 2: 3213 case 2:
3214 ((u16 *)(&ucontrol->value.bytes.data))[0] 3214 ((u16 *)(&ucontrol->value.bytes.data))[0]
3215 &= ~params->mask; 3215 &= cpu_to_be16(~params->mask);
3216 break; 3216 break;
3217 case 4: 3217 case 4:
3218 ((u32 *)(&ucontrol->value.bytes.data))[0] 3218 ((u32 *)(&ucontrol->value.bytes.data))[0]
3219 &= ~params->mask; 3219 &= cpu_to_be32(~params->mask);
3220 break; 3220 break;
3221 default: 3221 default:
3222 return -EINVAL; 3222 return -EINVAL;
diff --git a/sound/soc/soc-devres.c b/sound/soc/soc-devres.c
index b1d732255c02..7ac745df1412 100644
--- a/sound/soc/soc-devres.c
+++ b/sound/soc/soc-devres.c
@@ -12,6 +12,7 @@
12#include <linux/module.h> 12#include <linux/module.h>
13#include <linux/moduleparam.h> 13#include <linux/moduleparam.h>
14#include <sound/soc.h> 14#include <sound/soc.h>
15#include <sound/dmaengine_pcm.h>
15 16
16static void devm_component_release(struct device *dev, void *res) 17static void devm_component_release(struct device *dev, void *res)
17{ 18{
@@ -66,7 +67,7 @@ static void devm_card_release(struct device *dev, void *res)
66 */ 67 */
67int devm_snd_soc_register_card(struct device *dev, struct snd_soc_card *card) 68int devm_snd_soc_register_card(struct device *dev, struct snd_soc_card *card)
68{ 69{
69 struct device **ptr; 70 struct snd_soc_card **ptr;
70 int ret; 71 int ret;
71 72
72 ptr = devres_alloc(devm_card_release, sizeof(*ptr), GFP_KERNEL); 73 ptr = devres_alloc(devm_card_release, sizeof(*ptr), GFP_KERNEL);
@@ -75,7 +76,7 @@ int devm_snd_soc_register_card(struct device *dev, struct snd_soc_card *card)
75 76
76 ret = snd_soc_register_card(card); 77 ret = snd_soc_register_card(card);
77 if (ret == 0) { 78 if (ret == 0) {
78 *ptr = dev; 79 *ptr = card;
79 devres_add(dev, ptr); 80 devres_add(dev, ptr);
80 } else { 81 } else {
81 devres_free(ptr); 82 devres_free(ptr);
@@ -84,3 +85,43 @@ int devm_snd_soc_register_card(struct device *dev, struct snd_soc_card *card)
84 return ret; 85 return ret;
85} 86}
86EXPORT_SYMBOL_GPL(devm_snd_soc_register_card); 87EXPORT_SYMBOL_GPL(devm_snd_soc_register_card);
88
89#ifdef CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM
90
91static void devm_dmaengine_pcm_release(struct device *dev, void *res)
92{
93 snd_dmaengine_pcm_unregister(*(struct device **)res);
94}
95
96/**
97 * devm_snd_dmaengine_pcm_register - resource managed dmaengine PCM registration
98 * @dev: The parent device for the PCM device
99 * @config: Platform specific PCM configuration
100 * @flags: Platform specific quirks
101 *
102 * Register a dmaengine based PCM device with automatic unregistration when the
103 * device is unregistered.
104 */
105int devm_snd_dmaengine_pcm_register(struct device *dev,
106 const struct snd_dmaengine_pcm_config *config, unsigned int flags)
107{
108 struct device **ptr;
109 int ret;
110
111 ptr = devres_alloc(devm_dmaengine_pcm_release, sizeof(*ptr), GFP_KERNEL);
112 if (!ptr)
113 return -ENOMEM;
114
115 ret = snd_dmaengine_pcm_register(dev, config, flags);
116 if (ret == 0) {
117 *ptr = dev;
118 devres_add(dev, ptr);
119 } else {
120 devres_free(ptr);
121 }
122
123 return ret;
124}
125EXPORT_SYMBOL_GPL(devm_snd_dmaengine_pcm_register);
126
127#endif
diff --git a/sound/soc/soc-generic-dmaengine-pcm.c b/sound/soc/soc-generic-dmaengine-pcm.c
index cbc9c96ce1f4..7483922f6ee3 100644
--- a/sound/soc/soc-generic-dmaengine-pcm.c
+++ b/sound/soc/soc-generic-dmaengine-pcm.c
@@ -137,6 +137,9 @@ static int dmaengine_pcm_set_runtime_hwparams(struct snd_pcm_substream *substrea
137 hw.buffer_bytes_max = SIZE_MAX; 137 hw.buffer_bytes_max = SIZE_MAX;
138 hw.fifo_size = dma_data->fifo_size; 138 hw.fifo_size = dma_data->fifo_size;
139 139
140 if (pcm->flags & SND_DMAENGINE_PCM_FLAG_NO_RESIDUE)
141 hw.info |= SNDRV_PCM_INFO_BATCH;
142
140 ret = dma_get_slave_caps(chan, &dma_caps); 143 ret = dma_get_slave_caps(chan, &dma_caps);
141 if (ret == 0) { 144 if (ret == 0) {
142 if (dma_caps.cmd_pause) 145 if (dma_caps.cmd_pause)
@@ -284,24 +287,67 @@ static const char * const dmaengine_pcm_dma_channel_names[] = {
284 [SNDRV_PCM_STREAM_CAPTURE] = "rx", 287 [SNDRV_PCM_STREAM_CAPTURE] = "rx",
285}; 288};
286 289
287static void dmaengine_pcm_request_chan_of(struct dmaengine_pcm *pcm, 290static int dmaengine_pcm_request_chan_of(struct dmaengine_pcm *pcm,
288 struct device *dev) 291 struct device *dev, const struct snd_dmaengine_pcm_config *config)
289{ 292{
290 unsigned int i; 293 unsigned int i;
294 const char *name;
295 struct dma_chan *chan;
291 296
292 if ((pcm->flags & (SND_DMAENGINE_PCM_FLAG_NO_DT | 297 if ((pcm->flags & (SND_DMAENGINE_PCM_FLAG_NO_DT |
293 SND_DMAENGINE_PCM_FLAG_CUSTOM_CHANNEL_NAME)) || 298 SND_DMAENGINE_PCM_FLAG_CUSTOM_CHANNEL_NAME)) ||
294 !dev->of_node) 299 !dev->of_node)
295 return; 300 return 0;
301
302 if (config->dma_dev) {
303 /*
304 * If this warning is seen, it probably means that your Linux
305 * device structure does not match your HW device structure.
306 * It would be best to refactor the Linux device structure to
307 * correctly match the HW structure.
308 */
309 dev_warn(dev, "DMA channels sourced from device %s",
310 dev_name(config->dma_dev));
311 dev = config->dma_dev;
312 }
296 313
297 if (pcm->flags & SND_DMAENGINE_PCM_FLAG_HALF_DUPLEX) { 314 for (i = SNDRV_PCM_STREAM_PLAYBACK; i <= SNDRV_PCM_STREAM_CAPTURE;
298 pcm->chan[0] = dma_request_slave_channel(dev, "rx-tx"); 315 i++) {
299 pcm->chan[1] = pcm->chan[0]; 316 if (pcm->flags & SND_DMAENGINE_PCM_FLAG_HALF_DUPLEX)
300 } else { 317 name = "rx-tx";
301 for (i = SNDRV_PCM_STREAM_PLAYBACK; i <= SNDRV_PCM_STREAM_CAPTURE; i++) { 318 else
302 pcm->chan[i] = dma_request_slave_channel(dev, 319 name = dmaengine_pcm_dma_channel_names[i];
303 dmaengine_pcm_dma_channel_names[i]); 320 if (config->chan_names[i])
321 name = config->chan_names[i];
322 chan = dma_request_slave_channel_reason(dev, name);
323 if (IS_ERR(chan)) {
324 if (PTR_ERR(chan) == -EPROBE_DEFER)
325 return -EPROBE_DEFER;
326 pcm->chan[i] = NULL;
327 } else {
328 pcm->chan[i] = chan;
304 } 329 }
330 if (pcm->flags & SND_DMAENGINE_PCM_FLAG_HALF_DUPLEX)
331 break;
332 }
333
334 if (pcm->flags & SND_DMAENGINE_PCM_FLAG_HALF_DUPLEX)
335 pcm->chan[1] = pcm->chan[0];
336
337 return 0;
338}
339
340static void dmaengine_pcm_release_chan(struct dmaengine_pcm *pcm)
341{
342 unsigned int i;
343
344 for (i = SNDRV_PCM_STREAM_PLAYBACK; i <= SNDRV_PCM_STREAM_CAPTURE;
345 i++) {
346 if (!pcm->chan[i])
347 continue;
348 dma_release_channel(pcm->chan[i]);
349 if (pcm->flags & SND_DMAENGINE_PCM_FLAG_HALF_DUPLEX)
350 break;
305 } 351 }
306} 352}
307 353
@@ -315,6 +361,7 @@ int snd_dmaengine_pcm_register(struct device *dev,
315 const struct snd_dmaengine_pcm_config *config, unsigned int flags) 361 const struct snd_dmaengine_pcm_config *config, unsigned int flags)
316{ 362{
317 struct dmaengine_pcm *pcm; 363 struct dmaengine_pcm *pcm;
364 int ret;
318 365
319 pcm = kzalloc(sizeof(*pcm), GFP_KERNEL); 366 pcm = kzalloc(sizeof(*pcm), GFP_KERNEL);
320 if (!pcm) 367 if (!pcm)
@@ -323,14 +370,25 @@ int snd_dmaengine_pcm_register(struct device *dev,
323 pcm->config = config; 370 pcm->config = config;
324 pcm->flags = flags; 371 pcm->flags = flags;
325 372
326 dmaengine_pcm_request_chan_of(pcm, dev); 373 ret = dmaengine_pcm_request_chan_of(pcm, dev, config);
374 if (ret)
375 goto err_free_dma;
327 376
328 if (flags & SND_DMAENGINE_PCM_FLAG_NO_RESIDUE) 377 if (flags & SND_DMAENGINE_PCM_FLAG_NO_RESIDUE)
329 return snd_soc_add_platform(dev, &pcm->platform, 378 ret = snd_soc_add_platform(dev, &pcm->platform,
330 &dmaengine_no_residue_pcm_platform); 379 &dmaengine_no_residue_pcm_platform);
331 else 380 else
332 return snd_soc_add_platform(dev, &pcm->platform, 381 ret = snd_soc_add_platform(dev, &pcm->platform,
333 &dmaengine_pcm_platform); 382 &dmaengine_pcm_platform);
383 if (ret)
384 goto err_free_dma;
385
386 return 0;
387
388err_free_dma:
389 dmaengine_pcm_release_chan(pcm);
390 kfree(pcm);
391 return ret;
334} 392}
335EXPORT_SYMBOL_GPL(snd_dmaengine_pcm_register); 393EXPORT_SYMBOL_GPL(snd_dmaengine_pcm_register);
336 394
@@ -345,7 +403,6 @@ void snd_dmaengine_pcm_unregister(struct device *dev)
345{ 403{
346 struct snd_soc_platform *platform; 404 struct snd_soc_platform *platform;
347 struct dmaengine_pcm *pcm; 405 struct dmaengine_pcm *pcm;
348 unsigned int i;
349 406
350 platform = snd_soc_lookup_platform(dev); 407 platform = snd_soc_lookup_platform(dev);
351 if (!platform) 408 if (!platform)
@@ -353,15 +410,8 @@ void snd_dmaengine_pcm_unregister(struct device *dev)
353 410
354 pcm = soc_platform_to_pcm(platform); 411 pcm = soc_platform_to_pcm(platform);
355 412
356 for (i = SNDRV_PCM_STREAM_PLAYBACK; i <= SNDRV_PCM_STREAM_CAPTURE; i++) {
357 if (pcm->chan[i]) {
358 dma_release_channel(pcm->chan[i]);
359 if (pcm->flags & SND_DMAENGINE_PCM_FLAG_HALF_DUPLEX)
360 break;
361 }
362 }
363
364 snd_soc_remove_platform(platform); 413 snd_soc_remove_platform(platform);
414 dmaengine_pcm_release_chan(pcm);
365 kfree(pcm); 415 kfree(pcm);
366} 416}
367EXPORT_SYMBOL_GPL(snd_dmaengine_pcm_unregister); 417EXPORT_SYMBOL_GPL(snd_dmaengine_pcm_unregister);
diff --git a/sound/soc/soc-pcm.c b/sound/soc/soc-pcm.c
index 42782c01e413..11a90cd027fa 100644
--- a/sound/soc/soc-pcm.c
+++ b/sound/soc/soc-pcm.c
@@ -148,12 +148,12 @@ static void soc_pcm_apply_msb(struct snd_pcm_substream *substream,
148 } 148 }
149} 149}
150 150
151static void soc_pcm_init_runtime_hw(struct snd_pcm_hardware *hw, 151static void soc_pcm_init_runtime_hw(struct snd_pcm_runtime *runtime,
152 struct snd_soc_pcm_stream *codec_stream, 152 struct snd_soc_pcm_stream *codec_stream,
153 struct snd_soc_pcm_stream *cpu_stream) 153 struct snd_soc_pcm_stream *cpu_stream)
154{ 154{
155 hw->rate_min = max(codec_stream->rate_min, cpu_stream->rate_min); 155 struct snd_pcm_hardware *hw = &runtime->hw;
156 hw->rate_max = max(codec_stream->rate_max, cpu_stream->rate_max); 156
157 hw->channels_min = max(codec_stream->channels_min, 157 hw->channels_min = max(codec_stream->channels_min,
158 cpu_stream->channels_min); 158 cpu_stream->channels_min);
159 hw->channels_max = min(codec_stream->channels_max, 159 hw->channels_max = min(codec_stream->channels_max,
@@ -166,6 +166,13 @@ static void soc_pcm_init_runtime_hw(struct snd_pcm_hardware *hw,
166 if (cpu_stream->rates 166 if (cpu_stream->rates
167 & (SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_CONTINUOUS)) 167 & (SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_CONTINUOUS))
168 hw->rates |= codec_stream->rates; 168 hw->rates |= codec_stream->rates;
169
170 snd_pcm_limit_hw_rates(runtime);
171
172 hw->rate_min = max(hw->rate_min, cpu_stream->rate_min);
173 hw->rate_min = max(hw->rate_min, codec_stream->rate_min);
174 hw->rate_max = min_not_zero(hw->rate_max, cpu_stream->rate_max);
175 hw->rate_max = min_not_zero(hw->rate_max, codec_stream->rate_max);
169} 176}
170 177
171/* 178/*
@@ -235,15 +242,14 @@ static int soc_pcm_open(struct snd_pcm_substream *substream)
235 242
236 /* Check that the codec and cpu DAIs are compatible */ 243 /* Check that the codec and cpu DAIs are compatible */
237 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 244 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
238 soc_pcm_init_runtime_hw(&runtime->hw, &codec_dai_drv->playback, 245 soc_pcm_init_runtime_hw(runtime, &codec_dai_drv->playback,
239 &cpu_dai_drv->playback); 246 &cpu_dai_drv->playback);
240 } else { 247 } else {
241 soc_pcm_init_runtime_hw(&runtime->hw, &codec_dai_drv->capture, 248 soc_pcm_init_runtime_hw(runtime, &codec_dai_drv->capture,
242 &cpu_dai_drv->capture); 249 &cpu_dai_drv->capture);
243 } 250 }
244 251
245 ret = -EINVAL; 252 ret = -EINVAL;
246 snd_pcm_limit_hw_rates(runtime);
247 if (!runtime->hw.rates) { 253 if (!runtime->hw.rates) {
248 printk(KERN_ERR "ASoC: %s <-> %s No matching rates\n", 254 printk(KERN_ERR "ASoC: %s <-> %s No matching rates\n",
249 codec_dai->name, cpu_dai->name); 255 codec_dai->name, cpu_dai->name);
diff --git a/sound/soc/tegra/Kconfig b/sound/soc/tegra/Kconfig
index 8fc653ca3ab4..896292bb853f 100644
--- a/sound/soc/tegra/Kconfig
+++ b/sound/soc/tegra/Kconfig
@@ -1,6 +1,8 @@
1config SND_SOC_TEGRA 1config SND_SOC_TEGRA
2 tristate "SoC Audio for the Tegra System-on-Chip" 2 tristate "SoC Audio for the Tegra System-on-Chip"
3 depends on (ARCH_TEGRA && TEGRA20_APB_DMA) || COMPILE_TEST 3 depends on (ARCH_TEGRA && TEGRA20_APB_DMA) || COMPILE_TEST
4 depends on COMMON_CLK
5 depends on RESET_CONTROLLER
4 select REGMAP_MMIO 6 select REGMAP_MMIO
5 select SND_SOC_GENERIC_DMAENGINE_PCM 7 select SND_SOC_GENERIC_DMAENGINE_PCM
6 help 8 help
diff --git a/sound/soc/tegra/tegra20_ac97.c b/sound/soc/tegra/tegra20_ac97.c
index ae27bcd586d2..d8b98d70ff41 100644
--- a/sound/soc/tegra/tegra20_ac97.c
+++ b/sound/soc/tegra/tegra20_ac97.c
@@ -313,7 +313,6 @@ static int tegra20_ac97_platform_probe(struct platform_device *pdev)
313{ 313{
314 struct tegra20_ac97 *ac97; 314 struct tegra20_ac97 *ac97;
315 struct resource *mem; 315 struct resource *mem;
316 u32 of_dma[2];
317 void __iomem *regs; 316 void __iomem *regs;
318 int ret = 0; 317 int ret = 0;
319 318
@@ -348,14 +347,6 @@ static int tegra20_ac97_platform_probe(struct platform_device *pdev)
348 goto err_clk_put; 347 goto err_clk_put;
349 } 348 }
350 349
351 if (of_property_read_u32_array(pdev->dev.of_node,
352 "nvidia,dma-request-selector",
353 of_dma, 2) < 0) {
354 dev_err(&pdev->dev, "No DMA resource\n");
355 ret = -ENODEV;
356 goto err_clk_put;
357 }
358
359 ac97->reset_gpio = of_get_named_gpio(pdev->dev.of_node, 350 ac97->reset_gpio = of_get_named_gpio(pdev->dev.of_node,
360 "nvidia,codec-reset-gpio", 0); 351 "nvidia,codec-reset-gpio", 0);
361 if (gpio_is_valid(ac97->reset_gpio)) { 352 if (gpio_is_valid(ac97->reset_gpio)) {
@@ -380,12 +371,10 @@ static int tegra20_ac97_platform_probe(struct platform_device *pdev)
380 ac97->capture_dma_data.addr = mem->start + TEGRA20_AC97_FIFO_RX1; 371 ac97->capture_dma_data.addr = mem->start + TEGRA20_AC97_FIFO_RX1;
381 ac97->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 372 ac97->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
382 ac97->capture_dma_data.maxburst = 4; 373 ac97->capture_dma_data.maxburst = 4;
383 ac97->capture_dma_data.slave_id = of_dma[1];
384 374
385 ac97->playback_dma_data.addr = mem->start + TEGRA20_AC97_FIFO_TX1; 375 ac97->playback_dma_data.addr = mem->start + TEGRA20_AC97_FIFO_TX1;
386 ac97->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 376 ac97->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
387 ac97->playback_dma_data.maxburst = 4; 377 ac97->playback_dma_data.maxburst = 4;
388 ac97->playback_dma_data.slave_id = of_dma[1];
389 378
390 ret = tegra_asoc_utils_init(&ac97->util_data, &pdev->dev); 379 ret = tegra_asoc_utils_init(&ac97->util_data, &pdev->dev);
391 if (ret) 380 if (ret)
diff --git a/sound/soc/tegra/tegra20_i2s.c b/sound/soc/tegra/tegra20_i2s.c
index 364bf6a907e1..1dc869c475e7 100644
--- a/sound/soc/tegra/tegra20_i2s.c
+++ b/sound/soc/tegra/tegra20_i2s.c
@@ -339,9 +339,7 @@ static const struct regmap_config tegra20_i2s_regmap_config = {
339static int tegra20_i2s_platform_probe(struct platform_device *pdev) 339static int tegra20_i2s_platform_probe(struct platform_device *pdev)
340{ 340{
341 struct tegra20_i2s *i2s; 341 struct tegra20_i2s *i2s;
342 struct resource *mem, *memregion, *dmareq; 342 struct resource *mem, *memregion;
343 u32 of_dma[2];
344 u32 dma_ch;
345 void __iomem *regs; 343 void __iomem *regs;
346 int ret; 344 int ret;
347 345
@@ -370,20 +368,6 @@ static int tegra20_i2s_platform_probe(struct platform_device *pdev)
370 goto err_clk_put; 368 goto err_clk_put;
371 } 369 }
372 370
373 dmareq = platform_get_resource(pdev, IORESOURCE_DMA, 0);
374 if (!dmareq) {
375 if (of_property_read_u32_array(pdev->dev.of_node,
376 "nvidia,dma-request-selector",
377 of_dma, 2) < 0) {
378 dev_err(&pdev->dev, "No DMA resource\n");
379 ret = -ENODEV;
380 goto err_clk_put;
381 }
382 dma_ch = of_dma[1];
383 } else {
384 dma_ch = dmareq->start;
385 }
386
387 memregion = devm_request_mem_region(&pdev->dev, mem->start, 371 memregion = devm_request_mem_region(&pdev->dev, mem->start,
388 resource_size(mem), DRV_NAME); 372 resource_size(mem), DRV_NAME);
389 if (!memregion) { 373 if (!memregion) {
@@ -410,12 +394,10 @@ static int tegra20_i2s_platform_probe(struct platform_device *pdev)
410 i2s->capture_dma_data.addr = mem->start + TEGRA20_I2S_FIFO2; 394 i2s->capture_dma_data.addr = mem->start + TEGRA20_I2S_FIFO2;
411 i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 395 i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
412 i2s->capture_dma_data.maxburst = 4; 396 i2s->capture_dma_data.maxburst = 4;
413 i2s->capture_dma_data.slave_id = dma_ch;
414 397
415 i2s->playback_dma_data.addr = mem->start + TEGRA20_I2S_FIFO1; 398 i2s->playback_dma_data.addr = mem->start + TEGRA20_I2S_FIFO1;
416 i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 399 i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
417 i2s->playback_dma_data.maxburst = 4; 400 i2s->playback_dma_data.maxburst = 4;
418 i2s->playback_dma_data.slave_id = dma_ch;
419 401
420 pm_runtime_enable(&pdev->dev); 402 pm_runtime_enable(&pdev->dev);
421 if (!pm_runtime_enabled(&pdev->dev)) { 403 if (!pm_runtime_enabled(&pdev->dev)) {
diff --git a/sound/soc/tegra/tegra30_ahub.c b/sound/soc/tegra/tegra30_ahub.c
index 31154338c1eb..d6f4c9940e0c 100644
--- a/sound/soc/tegra/tegra30_ahub.c
+++ b/sound/soc/tegra/tegra30_ahub.c
@@ -24,8 +24,8 @@
24#include <linux/platform_device.h> 24#include <linux/platform_device.h>
25#include <linux/pm_runtime.h> 25#include <linux/pm_runtime.h>
26#include <linux/regmap.h> 26#include <linux/regmap.h>
27#include <linux/reset.h>
27#include <linux/slab.h> 28#include <linux/slab.h>
28#include <linux/clk/tegra.h>
29#include <sound/soc.h> 29#include <sound/soc.h>
30#include "tegra30_ahub.h" 30#include "tegra30_ahub.h"
31 31
@@ -95,8 +95,8 @@ static int tegra30_ahub_runtime_resume(struct device *dev)
95} 95}
96 96
97int tegra30_ahub_allocate_rx_fifo(enum tegra30_ahub_rxcif *rxcif, 97int tegra30_ahub_allocate_rx_fifo(enum tegra30_ahub_rxcif *rxcif,
98 dma_addr_t *fiforeg, 98 char *dmachan, int dmachan_len,
99 unsigned int *reqsel) 99 dma_addr_t *fiforeg)
100{ 100{
101 int channel; 101 int channel;
102 u32 reg, val; 102 u32 reg, val;
@@ -110,9 +110,11 @@ int tegra30_ahub_allocate_rx_fifo(enum tegra30_ahub_rxcif *rxcif,
110 __set_bit(channel, ahub->rx_usage); 110 __set_bit(channel, ahub->rx_usage);
111 111
112 *rxcif = TEGRA30_AHUB_RXCIF_APBIF_RX0 + channel; 112 *rxcif = TEGRA30_AHUB_RXCIF_APBIF_RX0 + channel;
113 snprintf(dmachan, dmachan_len, "rx%d", channel);
113 *fiforeg = ahub->apbif_addr + TEGRA30_AHUB_CHANNEL_RXFIFO + 114 *fiforeg = ahub->apbif_addr + TEGRA30_AHUB_CHANNEL_RXFIFO +
114 (channel * TEGRA30_AHUB_CHANNEL_RXFIFO_STRIDE); 115 (channel * TEGRA30_AHUB_CHANNEL_RXFIFO_STRIDE);
115 *reqsel = ahub->dma_sel + channel; 116
117 pm_runtime_get_sync(ahub->dev);
116 118
117 reg = TEGRA30_AHUB_CHANNEL_CTRL + 119 reg = TEGRA30_AHUB_CHANNEL_CTRL +
118 (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE); 120 (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE);
@@ -140,6 +142,8 @@ int tegra30_ahub_allocate_rx_fifo(enum tegra30_ahub_rxcif *rxcif,
140 (channel * TEGRA30_AHUB_CIF_RX_CTRL_STRIDE); 142 (channel * TEGRA30_AHUB_CIF_RX_CTRL_STRIDE);
141 ahub->soc_data->set_audio_cif(ahub->regmap_apbif, reg, &cif_conf); 143 ahub->soc_data->set_audio_cif(ahub->regmap_apbif, reg, &cif_conf);
142 144
145 pm_runtime_put(ahub->dev);
146
143 return 0; 147 return 0;
144} 148}
145EXPORT_SYMBOL_GPL(tegra30_ahub_allocate_rx_fifo); 149EXPORT_SYMBOL_GPL(tegra30_ahub_allocate_rx_fifo);
@@ -149,12 +153,16 @@ int tegra30_ahub_enable_rx_fifo(enum tegra30_ahub_rxcif rxcif)
149 int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0; 153 int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0;
150 int reg, val; 154 int reg, val;
151 155
156 pm_runtime_get_sync(ahub->dev);
157
152 reg = TEGRA30_AHUB_CHANNEL_CTRL + 158 reg = TEGRA30_AHUB_CHANNEL_CTRL +
153 (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE); 159 (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE);
154 val = tegra30_apbif_read(reg); 160 val = tegra30_apbif_read(reg);
155 val |= TEGRA30_AHUB_CHANNEL_CTRL_RX_EN; 161 val |= TEGRA30_AHUB_CHANNEL_CTRL_RX_EN;
156 tegra30_apbif_write(reg, val); 162 tegra30_apbif_write(reg, val);
157 163
164 pm_runtime_put(ahub->dev);
165
158 return 0; 166 return 0;
159} 167}
160EXPORT_SYMBOL_GPL(tegra30_ahub_enable_rx_fifo); 168EXPORT_SYMBOL_GPL(tegra30_ahub_enable_rx_fifo);
@@ -164,12 +172,16 @@ int tegra30_ahub_disable_rx_fifo(enum tegra30_ahub_rxcif rxcif)
164 int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0; 172 int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0;
165 int reg, val; 173 int reg, val;
166 174
175 pm_runtime_get_sync(ahub->dev);
176
167 reg = TEGRA30_AHUB_CHANNEL_CTRL + 177 reg = TEGRA30_AHUB_CHANNEL_CTRL +
168 (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE); 178 (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE);
169 val = tegra30_apbif_read(reg); 179 val = tegra30_apbif_read(reg);
170 val &= ~TEGRA30_AHUB_CHANNEL_CTRL_RX_EN; 180 val &= ~TEGRA30_AHUB_CHANNEL_CTRL_RX_EN;
171 tegra30_apbif_write(reg, val); 181 tegra30_apbif_write(reg, val);
172 182
183 pm_runtime_put(ahub->dev);
184
173 return 0; 185 return 0;
174} 186}
175EXPORT_SYMBOL_GPL(tegra30_ahub_disable_rx_fifo); 187EXPORT_SYMBOL_GPL(tegra30_ahub_disable_rx_fifo);
@@ -185,8 +197,8 @@ int tegra30_ahub_free_rx_fifo(enum tegra30_ahub_rxcif rxcif)
185EXPORT_SYMBOL_GPL(tegra30_ahub_free_rx_fifo); 197EXPORT_SYMBOL_GPL(tegra30_ahub_free_rx_fifo);
186 198
187int tegra30_ahub_allocate_tx_fifo(enum tegra30_ahub_txcif *txcif, 199int tegra30_ahub_allocate_tx_fifo(enum tegra30_ahub_txcif *txcif,
188 dma_addr_t *fiforeg, 200 char *dmachan, int dmachan_len,
189 unsigned int *reqsel) 201 dma_addr_t *fiforeg)
190{ 202{
191 int channel; 203 int channel;
192 u32 reg, val; 204 u32 reg, val;
@@ -200,9 +212,11 @@ int tegra30_ahub_allocate_tx_fifo(enum tegra30_ahub_txcif *txcif,
200 __set_bit(channel, ahub->tx_usage); 212 __set_bit(channel, ahub->tx_usage);
201 213
202 *txcif = TEGRA30_AHUB_TXCIF_APBIF_TX0 + channel; 214 *txcif = TEGRA30_AHUB_TXCIF_APBIF_TX0 + channel;
215 snprintf(dmachan, dmachan_len, "tx%d", channel);
203 *fiforeg = ahub->apbif_addr + TEGRA30_AHUB_CHANNEL_TXFIFO + 216 *fiforeg = ahub->apbif_addr + TEGRA30_AHUB_CHANNEL_TXFIFO +
204 (channel * TEGRA30_AHUB_CHANNEL_TXFIFO_STRIDE); 217 (channel * TEGRA30_AHUB_CHANNEL_TXFIFO_STRIDE);
205 *reqsel = ahub->dma_sel + channel; 218
219 pm_runtime_get_sync(ahub->dev);
206 220
207 reg = TEGRA30_AHUB_CHANNEL_CTRL + 221 reg = TEGRA30_AHUB_CHANNEL_CTRL +
208 (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE); 222 (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE);
@@ -230,6 +244,8 @@ int tegra30_ahub_allocate_tx_fifo(enum tegra30_ahub_txcif *txcif,
230 (channel * TEGRA30_AHUB_CIF_TX_CTRL_STRIDE); 244 (channel * TEGRA30_AHUB_CIF_TX_CTRL_STRIDE);
231 ahub->soc_data->set_audio_cif(ahub->regmap_apbif, reg, &cif_conf); 245 ahub->soc_data->set_audio_cif(ahub->regmap_apbif, reg, &cif_conf);
232 246
247 pm_runtime_put(ahub->dev);
248
233 return 0; 249 return 0;
234} 250}
235EXPORT_SYMBOL_GPL(tegra30_ahub_allocate_tx_fifo); 251EXPORT_SYMBOL_GPL(tegra30_ahub_allocate_tx_fifo);
@@ -239,12 +255,16 @@ int tegra30_ahub_enable_tx_fifo(enum tegra30_ahub_txcif txcif)
239 int channel = txcif - TEGRA30_AHUB_TXCIF_APBIF_TX0; 255 int channel = txcif - TEGRA30_AHUB_TXCIF_APBIF_TX0;
240 int reg, val; 256 int reg, val;
241 257
258 pm_runtime_get_sync(ahub->dev);
259
242 reg = TEGRA30_AHUB_CHANNEL_CTRL + 260 reg = TEGRA30_AHUB_CHANNEL_CTRL +
243 (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE); 261 (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE);
244 val = tegra30_apbif_read(reg); 262 val = tegra30_apbif_read(reg);
245 val |= TEGRA30_AHUB_CHANNEL_CTRL_TX_EN; 263 val |= TEGRA30_AHUB_CHANNEL_CTRL_TX_EN;
246 tegra30_apbif_write(reg, val); 264 tegra30_apbif_write(reg, val);
247 265
266 pm_runtime_put(ahub->dev);
267
248 return 0; 268 return 0;
249} 269}
250EXPORT_SYMBOL_GPL(tegra30_ahub_enable_tx_fifo); 270EXPORT_SYMBOL_GPL(tegra30_ahub_enable_tx_fifo);
@@ -254,12 +274,16 @@ int tegra30_ahub_disable_tx_fifo(enum tegra30_ahub_txcif txcif)
254 int channel = txcif - TEGRA30_AHUB_TXCIF_APBIF_TX0; 274 int channel = txcif - TEGRA30_AHUB_TXCIF_APBIF_TX0;
255 int reg, val; 275 int reg, val;
256 276
277 pm_runtime_get_sync(ahub->dev);
278
257 reg = TEGRA30_AHUB_CHANNEL_CTRL + 279 reg = TEGRA30_AHUB_CHANNEL_CTRL +
258 (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE); 280 (channel * TEGRA30_AHUB_CHANNEL_CTRL_STRIDE);
259 val = tegra30_apbif_read(reg); 281 val = tegra30_apbif_read(reg);
260 val &= ~TEGRA30_AHUB_CHANNEL_CTRL_TX_EN; 282 val &= ~TEGRA30_AHUB_CHANNEL_CTRL_TX_EN;
261 tegra30_apbif_write(reg, val); 283 tegra30_apbif_write(reg, val);
262 284
285 pm_runtime_put(ahub->dev);
286
263 return 0; 287 return 0;
264} 288}
265EXPORT_SYMBOL_GPL(tegra30_ahub_disable_tx_fifo); 289EXPORT_SYMBOL_GPL(tegra30_ahub_disable_tx_fifo);
@@ -280,10 +304,14 @@ int tegra30_ahub_set_rx_cif_source(enum tegra30_ahub_rxcif rxcif,
280 int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0; 304 int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0;
281 int reg; 305 int reg;
282 306
307 pm_runtime_get_sync(ahub->dev);
308
283 reg = TEGRA30_AHUB_AUDIO_RX + 309 reg = TEGRA30_AHUB_AUDIO_RX +
284 (channel * TEGRA30_AHUB_AUDIO_RX_STRIDE); 310 (channel * TEGRA30_AHUB_AUDIO_RX_STRIDE);
285 tegra30_audio_write(reg, 1 << txcif); 311 tegra30_audio_write(reg, 1 << txcif);
286 312
313 pm_runtime_put(ahub->dev);
314
287 return 0; 315 return 0;
288} 316}
289EXPORT_SYMBOL_GPL(tegra30_ahub_set_rx_cif_source); 317EXPORT_SYMBOL_GPL(tegra30_ahub_set_rx_cif_source);
@@ -293,35 +321,51 @@ int tegra30_ahub_unset_rx_cif_source(enum tegra30_ahub_rxcif rxcif)
293 int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0; 321 int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0;
294 int reg; 322 int reg;
295 323
324 pm_runtime_get_sync(ahub->dev);
325
296 reg = TEGRA30_AHUB_AUDIO_RX + 326 reg = TEGRA30_AHUB_AUDIO_RX +
297 (channel * TEGRA30_AHUB_AUDIO_RX_STRIDE); 327 (channel * TEGRA30_AHUB_AUDIO_RX_STRIDE);
298 tegra30_audio_write(reg, 0); 328 tegra30_audio_write(reg, 0);
299 329
330 pm_runtime_put(ahub->dev);
331
300 return 0; 332 return 0;
301} 333}
302EXPORT_SYMBOL_GPL(tegra30_ahub_unset_rx_cif_source); 334EXPORT_SYMBOL_GPL(tegra30_ahub_unset_rx_cif_source);
303 335
304#define CLK_LIST_MASK_TEGRA30 BIT(0) 336#define MOD_LIST_MASK_TEGRA30 BIT(0)
305#define CLK_LIST_MASK_TEGRA114 BIT(1) 337#define MOD_LIST_MASK_TEGRA114 BIT(1)
338#define MOD_LIST_MASK_TEGRA124 BIT(2)
306 339
307#define CLK_LIST_MASK_TEGRA30_OR_LATER \ 340#define MOD_LIST_MASK_TEGRA30_OR_LATER \
308 (CLK_LIST_MASK_TEGRA30 | CLK_LIST_MASK_TEGRA114) 341 (MOD_LIST_MASK_TEGRA30 | MOD_LIST_MASK_TEGRA114 | \
342 MOD_LIST_MASK_TEGRA124)
343#define MOD_LIST_MASK_TEGRA114_OR_LATER \
344 (MOD_LIST_MASK_TEGRA114 | MOD_LIST_MASK_TEGRA124)
309 345
310static const struct { 346static const struct {
311 const char *clk_name; 347 const char *rst_name;
312 u32 clk_list_mask; 348 u32 mod_list_mask;
313} configlink_clocks[] = { 349} configlink_mods[] = {
314 { "i2s0", CLK_LIST_MASK_TEGRA30_OR_LATER }, 350 { "i2s0", MOD_LIST_MASK_TEGRA30_OR_LATER },
315 { "i2s1", CLK_LIST_MASK_TEGRA30_OR_LATER }, 351 { "i2s1", MOD_LIST_MASK_TEGRA30_OR_LATER },
316 { "i2s2", CLK_LIST_MASK_TEGRA30_OR_LATER }, 352 { "i2s2", MOD_LIST_MASK_TEGRA30_OR_LATER },
317 { "i2s3", CLK_LIST_MASK_TEGRA30_OR_LATER }, 353 { "i2s3", MOD_LIST_MASK_TEGRA30_OR_LATER },
318 { "i2s4", CLK_LIST_MASK_TEGRA30_OR_LATER }, 354 { "i2s4", MOD_LIST_MASK_TEGRA30_OR_LATER },
319 { "dam0", CLK_LIST_MASK_TEGRA30_OR_LATER }, 355 { "dam0", MOD_LIST_MASK_TEGRA30_OR_LATER },
320 { "dam1", CLK_LIST_MASK_TEGRA30_OR_LATER }, 356 { "dam1", MOD_LIST_MASK_TEGRA30_OR_LATER },
321 { "dam2", CLK_LIST_MASK_TEGRA30_OR_LATER }, 357 { "dam2", MOD_LIST_MASK_TEGRA30_OR_LATER },
322 { "spdif_in", CLK_LIST_MASK_TEGRA30_OR_LATER }, 358 { "spdif", MOD_LIST_MASK_TEGRA30_OR_LATER },
323 { "amx", CLK_LIST_MASK_TEGRA114 }, 359 { "amx", MOD_LIST_MASK_TEGRA114_OR_LATER },
324 { "adx", CLK_LIST_MASK_TEGRA114 }, 360 { "adx", MOD_LIST_MASK_TEGRA114_OR_LATER },
361 { "amx1", MOD_LIST_MASK_TEGRA124 },
362 { "adx1", MOD_LIST_MASK_TEGRA124 },
363 { "afc0", MOD_LIST_MASK_TEGRA124 },
364 { "afc1", MOD_LIST_MASK_TEGRA124 },
365 { "afc2", MOD_LIST_MASK_TEGRA124 },
366 { "afc3", MOD_LIST_MASK_TEGRA124 },
367 { "afc4", MOD_LIST_MASK_TEGRA124 },
368 { "afc5", MOD_LIST_MASK_TEGRA124 },
325}; 369};
326 370
327#define LAST_REG(name) \ 371#define LAST_REG(name) \
@@ -450,17 +494,17 @@ static const struct regmap_config tegra30_ahub_ahub_regmap_config = {
450}; 494};
451 495
452static struct tegra30_ahub_soc_data soc_data_tegra30 = { 496static struct tegra30_ahub_soc_data soc_data_tegra30 = {
453 .clk_list_mask = CLK_LIST_MASK_TEGRA30, 497 .mod_list_mask = MOD_LIST_MASK_TEGRA30,
454 .set_audio_cif = tegra30_ahub_set_cif, 498 .set_audio_cif = tegra30_ahub_set_cif,
455}; 499};
456 500
457static struct tegra30_ahub_soc_data soc_data_tegra114 = { 501static struct tegra30_ahub_soc_data soc_data_tegra114 = {
458 .clk_list_mask = CLK_LIST_MASK_TEGRA114, 502 .mod_list_mask = MOD_LIST_MASK_TEGRA114,
459 .set_audio_cif = tegra30_ahub_set_cif, 503 .set_audio_cif = tegra30_ahub_set_cif,
460}; 504};
461 505
462static struct tegra30_ahub_soc_data soc_data_tegra124 = { 506static struct tegra30_ahub_soc_data soc_data_tegra124 = {
463 .clk_list_mask = CLK_LIST_MASK_TEGRA114, 507 .mod_list_mask = MOD_LIST_MASK_TEGRA124,
464 .set_audio_cif = tegra124_ahub_set_cif, 508 .set_audio_cif = tegra124_ahub_set_cif,
465}; 509};
466 510
@@ -475,10 +519,9 @@ static int tegra30_ahub_probe(struct platform_device *pdev)
475{ 519{
476 const struct of_device_id *match; 520 const struct of_device_id *match;
477 const struct tegra30_ahub_soc_data *soc_data; 521 const struct tegra30_ahub_soc_data *soc_data;
478 struct clk *clk; 522 struct reset_control *rst;
479 int i; 523 int i;
480 struct resource *res0, *res1, *region; 524 struct resource *res0, *res1, *region;
481 u32 of_dma[2];
482 void __iomem *regs_apbif, *regs_ahub; 525 void __iomem *regs_apbif, *regs_ahub;
483 int ret = 0; 526 int ret = 0;
484 527
@@ -495,19 +538,24 @@ static int tegra30_ahub_probe(struct platform_device *pdev)
495 * operate correctly, all devices on this bus must be out of reset. 538 * operate correctly, all devices on this bus must be out of reset.
496 * Ensure that here. 539 * Ensure that here.
497 */ 540 */
498 for (i = 0; i < ARRAY_SIZE(configlink_clocks); i++) { 541 for (i = 0; i < ARRAY_SIZE(configlink_mods); i++) {
499 if (!(configlink_clocks[i].clk_list_mask & 542 if (!(configlink_mods[i].mod_list_mask &
500 soc_data->clk_list_mask)) 543 soc_data->mod_list_mask))
501 continue; 544 continue;
502 clk = clk_get(&pdev->dev, configlink_clocks[i].clk_name); 545
503 if (IS_ERR(clk)) { 546 rst = reset_control_get(&pdev->dev,
504 dev_err(&pdev->dev, "Can't get clock %s\n", 547 configlink_mods[i].rst_name);
505 configlink_clocks[i].clk_name); 548 if (IS_ERR(rst)) {
506 ret = PTR_ERR(clk); 549 dev_err(&pdev->dev, "Can't get reset %s\n",
550 configlink_mods[i].rst_name);
551 ret = PTR_ERR(rst);
507 goto err; 552 goto err;
508 } 553 }
509 tegra_periph_reset_deassert(clk); 554
510 clk_put(clk); 555 ret = reset_control_deassert(rst);
556 reset_control_put(rst);
557 if (ret)
558 goto err;
511 } 559 }
512 560
513 ahub = devm_kzalloc(&pdev->dev, sizeof(struct tegra30_ahub), 561 ahub = devm_kzalloc(&pdev->dev, sizeof(struct tegra30_ahub),
@@ -536,16 +584,6 @@ static int tegra30_ahub_probe(struct platform_device *pdev)
536 goto err_clk_put_d_audio; 584 goto err_clk_put_d_audio;
537 } 585 }
538 586
539 if (of_property_read_u32_array(pdev->dev.of_node,
540 "nvidia,dma-request-selector",
541 of_dma, 2) < 0) {
542 dev_err(&pdev->dev,
543 "Missing property nvidia,dma-request-selector\n");
544 ret = -ENODEV;
545 goto err_clk_put_d_audio;
546 }
547 ahub->dma_sel = of_dma[1];
548
549 res0 = platform_get_resource(pdev, IORESOURCE_MEM, 0); 587 res0 = platform_get_resource(pdev, IORESOURCE_MEM, 0);
550 if (!res0) { 588 if (!res0) {
551 dev_err(&pdev->dev, "No apbif memory resource\n"); 589 dev_err(&pdev->dev, "No apbif memory resource\n");
diff --git a/sound/soc/tegra/tegra30_ahub.h b/sound/soc/tegra/tegra30_ahub.h
index d67321d90faa..fd7ba75ed814 100644
--- a/sound/soc/tegra/tegra30_ahub.h
+++ b/sound/soc/tegra/tegra30_ahub.h
@@ -465,15 +465,15 @@ enum tegra30_ahub_rxcif {
465}; 465};
466 466
467extern int tegra30_ahub_allocate_rx_fifo(enum tegra30_ahub_rxcif *rxcif, 467extern int tegra30_ahub_allocate_rx_fifo(enum tegra30_ahub_rxcif *rxcif,
468 dma_addr_t *fiforeg, 468 char *dmachan, int dmachan_len,
469 unsigned int *reqsel); 469 dma_addr_t *fiforeg);
470extern int tegra30_ahub_enable_rx_fifo(enum tegra30_ahub_rxcif rxcif); 470extern int tegra30_ahub_enable_rx_fifo(enum tegra30_ahub_rxcif rxcif);
471extern int tegra30_ahub_disable_rx_fifo(enum tegra30_ahub_rxcif rxcif); 471extern int tegra30_ahub_disable_rx_fifo(enum tegra30_ahub_rxcif rxcif);
472extern int tegra30_ahub_free_rx_fifo(enum tegra30_ahub_rxcif rxcif); 472extern int tegra30_ahub_free_rx_fifo(enum tegra30_ahub_rxcif rxcif);
473 473
474extern int tegra30_ahub_allocate_tx_fifo(enum tegra30_ahub_txcif *txcif, 474extern int tegra30_ahub_allocate_tx_fifo(enum tegra30_ahub_txcif *txcif,
475 dma_addr_t *fiforeg, 475 char *dmachan, int dmachan_len,
476 unsigned int *reqsel); 476 dma_addr_t *fiforeg);
477extern int tegra30_ahub_enable_tx_fifo(enum tegra30_ahub_txcif txcif); 477extern int tegra30_ahub_enable_tx_fifo(enum tegra30_ahub_txcif txcif);
478extern int tegra30_ahub_disable_tx_fifo(enum tegra30_ahub_txcif txcif); 478extern int tegra30_ahub_disable_tx_fifo(enum tegra30_ahub_txcif txcif);
479extern int tegra30_ahub_free_tx_fifo(enum tegra30_ahub_txcif txcif); 479extern int tegra30_ahub_free_tx_fifo(enum tegra30_ahub_txcif txcif);
@@ -502,7 +502,7 @@ void tegra124_ahub_set_cif(struct regmap *regmap, unsigned int reg,
502 struct tegra30_ahub_cif_conf *conf); 502 struct tegra30_ahub_cif_conf *conf);
503 503
504struct tegra30_ahub_soc_data { 504struct tegra30_ahub_soc_data {
505 u32 clk_list_mask; 505 u32 mod_list_mask;
506 void (*set_audio_cif)(struct regmap *regmap, 506 void (*set_audio_cif)(struct regmap *regmap,
507 unsigned int reg, 507 unsigned int reg,
508 struct tegra30_ahub_cif_conf *conf); 508 struct tegra30_ahub_cif_conf *conf);
@@ -524,7 +524,6 @@ struct tegra30_ahub {
524 struct device *dev; 524 struct device *dev;
525 struct clk *clk_d_audio; 525 struct clk *clk_d_audio;
526 struct clk *clk_apbif; 526 struct clk *clk_apbif;
527 int dma_sel;
528 resource_size_t apbif_addr; 527 resource_size_t apbif_addr;
529 struct regmap *regmap_apbif; 528 struct regmap *regmap_apbif;
530 struct regmap *regmap_ahub; 529 struct regmap *regmap_ahub;
diff --git a/sound/soc/tegra/tegra30_i2s.c b/sound/soc/tegra/tegra30_i2s.c
index 231a785b3921..362e8f728ddf 100644
--- a/sound/soc/tegra/tegra30_i2s.c
+++ b/sound/soc/tegra/tegra30_i2s.c
@@ -73,47 +73,6 @@ static int tegra30_i2s_runtime_resume(struct device *dev)
73 return 0; 73 return 0;
74} 74}
75 75
76static int tegra30_i2s_startup(struct snd_pcm_substream *substream,
77 struct snd_soc_dai *dai)
78{
79 struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
80 int ret;
81
82 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
83 ret = tegra30_ahub_allocate_tx_fifo(&i2s->playback_fifo_cif,
84 &i2s->playback_dma_data.addr,
85 &i2s->playback_dma_data.slave_id);
86 i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
87 i2s->playback_dma_data.maxburst = 4;
88 tegra30_ahub_set_rx_cif_source(i2s->playback_i2s_cif,
89 i2s->playback_fifo_cif);
90 } else {
91 ret = tegra30_ahub_allocate_rx_fifo(&i2s->capture_fifo_cif,
92 &i2s->capture_dma_data.addr,
93 &i2s->capture_dma_data.slave_id);
94 i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
95 i2s->capture_dma_data.maxburst = 4;
96 tegra30_ahub_set_rx_cif_source(i2s->capture_fifo_cif,
97 i2s->capture_i2s_cif);
98 }
99
100 return ret;
101}
102
103static void tegra30_i2s_shutdown(struct snd_pcm_substream *substream,
104 struct snd_soc_dai *dai)
105{
106 struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
107
108 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
109 tegra30_ahub_unset_rx_cif_source(i2s->playback_i2s_cif);
110 tegra30_ahub_free_tx_fifo(i2s->playback_fifo_cif);
111 } else {
112 tegra30_ahub_unset_rx_cif_source(i2s->capture_fifo_cif);
113 tegra30_ahub_free_rx_fifo(i2s->capture_fifo_cif);
114 }
115}
116
117static int tegra30_i2s_set_fmt(struct snd_soc_dai *dai, 76static int tegra30_i2s_set_fmt(struct snd_soc_dai *dai,
118 unsigned int fmt) 77 unsigned int fmt)
119{ 78{
@@ -317,8 +276,6 @@ static int tegra30_i2s_probe(struct snd_soc_dai *dai)
317} 276}
318 277
319static struct snd_soc_dai_ops tegra30_i2s_dai_ops = { 278static struct snd_soc_dai_ops tegra30_i2s_dai_ops = {
320 .startup = tegra30_i2s_startup,
321 .shutdown = tegra30_i2s_shutdown,
322 .set_fmt = tegra30_i2s_set_fmt, 279 .set_fmt = tegra30_i2s_set_fmt,
323 .hw_params = tegra30_i2s_hw_params, 280 .hw_params = tegra30_i2s_hw_params,
324 .trigger = tegra30_i2s_trigger, 281 .trigger = tegra30_i2s_trigger,
@@ -499,15 +456,51 @@ static int tegra30_i2s_platform_probe(struct platform_device *pdev)
499 goto err_pm_disable; 456 goto err_pm_disable;
500 } 457 }
501 458
459 i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
460 i2s->playback_dma_data.maxburst = 4;
461 ret = tegra30_ahub_allocate_tx_fifo(&i2s->playback_fifo_cif,
462 i2s->playback_dma_chan,
463 sizeof(i2s->playback_dma_chan),
464 &i2s->playback_dma_data.addr);
465 if (ret) {
466 dev_err(&pdev->dev, "Could not alloc TX FIFO: %d\n", ret);
467 goto err_suspend;
468 }
469 ret = tegra30_ahub_set_rx_cif_source(i2s->playback_i2s_cif,
470 i2s->playback_fifo_cif);
471 if (ret) {
472 dev_err(&pdev->dev, "Could not route TX FIFO: %d\n", ret);
473 goto err_free_tx_fifo;
474 }
475
476 i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
477 i2s->capture_dma_data.maxburst = 4;
478 ret = tegra30_ahub_allocate_rx_fifo(&i2s->capture_fifo_cif,
479 i2s->capture_dma_chan,
480 sizeof(i2s->capture_dma_chan),
481 &i2s->capture_dma_data.addr);
482 if (ret) {
483 dev_err(&pdev->dev, "Could not alloc RX FIFO: %d\n", ret);
484 goto err_unroute_tx_fifo;
485 }
486 ret = tegra30_ahub_set_rx_cif_source(i2s->capture_fifo_cif,
487 i2s->capture_i2s_cif);
488 if (ret) {
489 dev_err(&pdev->dev, "Could not route TX FIFO: %d\n", ret);
490 goto err_free_rx_fifo;
491 }
492
502 ret = snd_soc_register_component(&pdev->dev, &tegra30_i2s_component, 493 ret = snd_soc_register_component(&pdev->dev, &tegra30_i2s_component,
503 &i2s->dai, 1); 494 &i2s->dai, 1);
504 if (ret) { 495 if (ret) {
505 dev_err(&pdev->dev, "Could not register DAI: %d\n", ret); 496 dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
506 ret = -ENOMEM; 497 ret = -ENOMEM;
507 goto err_suspend; 498 goto err_unroute_rx_fifo;
508 } 499 }
509 500
510 ret = tegra_pcm_platform_register(&pdev->dev); 501 ret = tegra_pcm_platform_register_with_chan_names(&pdev->dev,
502 &i2s->dma_config, i2s->playback_dma_chan,
503 i2s->capture_dma_chan);
511 if (ret) { 504 if (ret) {
512 dev_err(&pdev->dev, "Could not register PCM: %d\n", ret); 505 dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
513 goto err_unregister_component; 506 goto err_unregister_component;
@@ -517,6 +510,14 @@ static int tegra30_i2s_platform_probe(struct platform_device *pdev)
517 510
518err_unregister_component: 511err_unregister_component:
519 snd_soc_unregister_component(&pdev->dev); 512 snd_soc_unregister_component(&pdev->dev);
513err_unroute_rx_fifo:
514 tegra30_ahub_unset_rx_cif_source(i2s->capture_fifo_cif);
515err_free_rx_fifo:
516 tegra30_ahub_free_rx_fifo(i2s->capture_fifo_cif);
517err_unroute_tx_fifo:
518 tegra30_ahub_unset_rx_cif_source(i2s->playback_i2s_cif);
519err_free_tx_fifo:
520 tegra30_ahub_free_tx_fifo(i2s->playback_fifo_cif);
520err_suspend: 521err_suspend:
521 if (!pm_runtime_status_suspended(&pdev->dev)) 522 if (!pm_runtime_status_suspended(&pdev->dev))
522 tegra30_i2s_runtime_suspend(&pdev->dev); 523 tegra30_i2s_runtime_suspend(&pdev->dev);
@@ -539,6 +540,12 @@ static int tegra30_i2s_platform_remove(struct platform_device *pdev)
539 tegra_pcm_platform_unregister(&pdev->dev); 540 tegra_pcm_platform_unregister(&pdev->dev);
540 snd_soc_unregister_component(&pdev->dev); 541 snd_soc_unregister_component(&pdev->dev);
541 542
543 tegra30_ahub_unset_rx_cif_source(i2s->capture_fifo_cif);
544 tegra30_ahub_free_rx_fifo(i2s->capture_fifo_cif);
545
546 tegra30_ahub_unset_rx_cif_source(i2s->playback_i2s_cif);
547 tegra30_ahub_free_tx_fifo(i2s->playback_fifo_cif);
548
542 clk_put(i2s->clk_i2s); 549 clk_put(i2s->clk_i2s);
543 550
544 return 0; 551 return 0;
diff --git a/sound/soc/tegra/tegra30_i2s.h b/sound/soc/tegra/tegra30_i2s.h
index 4d0b0a30dbfb..774fc6ad2026 100644
--- a/sound/soc/tegra/tegra30_i2s.h
+++ b/sound/soc/tegra/tegra30_i2s.h
@@ -238,11 +238,14 @@ struct tegra30_i2s {
238 struct clk *clk_i2s; 238 struct clk *clk_i2s;
239 enum tegra30_ahub_txcif capture_i2s_cif; 239 enum tegra30_ahub_txcif capture_i2s_cif;
240 enum tegra30_ahub_rxcif capture_fifo_cif; 240 enum tegra30_ahub_rxcif capture_fifo_cif;
241 char capture_dma_chan[8];
241 struct snd_dmaengine_dai_dma_data capture_dma_data; 242 struct snd_dmaengine_dai_dma_data capture_dma_data;
242 enum tegra30_ahub_rxcif playback_i2s_cif; 243 enum tegra30_ahub_rxcif playback_i2s_cif;
243 enum tegra30_ahub_txcif playback_fifo_cif; 244 enum tegra30_ahub_txcif playback_fifo_cif;
245 char playback_dma_chan[8];
244 struct snd_dmaengine_dai_dma_data playback_dma_data; 246 struct snd_dmaengine_dai_dma_data playback_dma_data;
245 struct regmap *regmap; 247 struct regmap *regmap;
248 struct snd_dmaengine_pcm_config dma_config;
246}; 249};
247 250
248#endif 251#endif
diff --git a/sound/soc/tegra/tegra_pcm.c b/sound/soc/tegra/tegra_pcm.c
index 7b2d23ba69b3..7ce5c334a660 100644
--- a/sound/soc/tegra/tegra_pcm.c
+++ b/sound/soc/tegra/tegra_pcm.c
@@ -61,12 +61,23 @@ static const struct snd_dmaengine_pcm_config tegra_dmaengine_pcm_config = {
61 61
62int tegra_pcm_platform_register(struct device *dev) 62int tegra_pcm_platform_register(struct device *dev)
63{ 63{
64 return snd_dmaengine_pcm_register(dev, &tegra_dmaengine_pcm_config, 64 return snd_dmaengine_pcm_register(dev, &tegra_dmaengine_pcm_config, 0);
65 SND_DMAENGINE_PCM_FLAG_NO_DT |
66 SND_DMAENGINE_PCM_FLAG_COMPAT);
67} 65}
68EXPORT_SYMBOL_GPL(tegra_pcm_platform_register); 66EXPORT_SYMBOL_GPL(tegra_pcm_platform_register);
69 67
68int tegra_pcm_platform_register_with_chan_names(struct device *dev,
69 struct snd_dmaengine_pcm_config *config,
70 char *txdmachan, char *rxdmachan)
71{
72 *config = tegra_dmaengine_pcm_config;
73 config->dma_dev = dev->parent;
74 config->chan_names[0] = txdmachan;
75 config->chan_names[1] = rxdmachan;
76
77 return snd_dmaengine_pcm_register(dev, config, 0);
78}
79EXPORT_SYMBOL_GPL(tegra_pcm_platform_register_with_chan_names);
80
70void tegra_pcm_platform_unregister(struct device *dev) 81void tegra_pcm_platform_unregister(struct device *dev)
71{ 82{
72 return snd_dmaengine_pcm_unregister(dev); 83 return snd_dmaengine_pcm_unregister(dev);
diff --git a/sound/soc/tegra/tegra_pcm.h b/sound/soc/tegra/tegra_pcm.h
index 68ad901714a9..7883dec748a3 100644
--- a/sound/soc/tegra/tegra_pcm.h
+++ b/sound/soc/tegra/tegra_pcm.h
@@ -31,7 +31,12 @@
31#ifndef __TEGRA_PCM_H__ 31#ifndef __TEGRA_PCM_H__
32#define __TEGRA_PCM_H__ 32#define __TEGRA_PCM_H__
33 33
34struct snd_dmaengine_pcm_config;
35
34int tegra_pcm_platform_register(struct device *dev); 36int tegra_pcm_platform_register(struct device *dev);
37int tegra_pcm_platform_register_with_chan_names(struct device *dev,
38 struct snd_dmaengine_pcm_config *config,
39 char *txdmachan, char *rxdmachan);
35void tegra_pcm_platform_unregister(struct device *dev); 40void tegra_pcm_platform_unregister(struct device *dev);
36 41
37#endif 42#endif
diff --git a/sound/usb/endpoint.c b/sound/usb/endpoint.c
index b9ba0fcc45df..83aabea259d7 100644
--- a/sound/usb/endpoint.c
+++ b/sound/usb/endpoint.c
@@ -636,8 +636,22 @@ static int data_ep_set_params(struct snd_usb_endpoint *ep,
636 if (usb_pipein(ep->pipe) || 636 if (usb_pipein(ep->pipe) ||
637 snd_usb_endpoint_implicit_feedback_sink(ep)) { 637 snd_usb_endpoint_implicit_feedback_sink(ep)) {
638 638
639 urb_packs = packs_per_ms;
640 /*
641 * Wireless devices can poll at a max rate of once per 4ms.
642 * For dataintervals less than 5, increase the packet count to
643 * allow the host controller to use bursting to fill in the
644 * gaps.
645 */
646 if (snd_usb_get_speed(ep->chip->dev) == USB_SPEED_WIRELESS) {
647 int interval = ep->datainterval;
648 while (interval < 5) {
649 urb_packs <<= 1;
650 ++interval;
651 }
652 }
639 /* make capture URBs <= 1 ms and smaller than a period */ 653 /* make capture URBs <= 1 ms and smaller than a period */
640 urb_packs = min(max_packs_per_urb, packs_per_ms); 654 urb_packs = min(max_packs_per_urb, urb_packs);
641 while (urb_packs > 1 && urb_packs * maxsize >= period_bytes) 655 while (urb_packs > 1 && urb_packs * maxsize >= period_bytes)
642 urb_packs >>= 1; 656 urb_packs >>= 1;
643 ep->nurbs = MAX_URBS; 657 ep->nurbs = MAX_URBS;
diff --git a/tools/lib/traceevent/event-parse.c b/tools/lib/traceevent/event-parse.c
index 0362d575de7d..217c82ee3665 100644
--- a/tools/lib/traceevent/event-parse.c
+++ b/tools/lib/traceevent/event-parse.c
@@ -1606,6 +1606,24 @@ process_arg(struct event_format *event, struct print_arg *arg, char **tok)
1606static enum event_type 1606static enum event_type
1607process_op(struct event_format *event, struct print_arg *arg, char **tok); 1607process_op(struct event_format *event, struct print_arg *arg, char **tok);
1608 1608
1609/*
1610 * For __print_symbolic() and __print_flags, we need to completely
1611 * evaluate the first argument, which defines what to print next.
1612 */
1613static enum event_type
1614process_field_arg(struct event_format *event, struct print_arg *arg, char **tok)
1615{
1616 enum event_type type;
1617
1618 type = process_arg(event, arg, tok);
1619
1620 while (type == EVENT_OP) {
1621 type = process_op(event, arg, tok);
1622 }
1623
1624 return type;
1625}
1626
1609static enum event_type 1627static enum event_type
1610process_cond(struct event_format *event, struct print_arg *top, char **tok) 1628process_cond(struct event_format *event, struct print_arg *top, char **tok)
1611{ 1629{
@@ -2371,7 +2389,7 @@ process_flags(struct event_format *event, struct print_arg *arg, char **tok)
2371 goto out_free; 2389 goto out_free;
2372 } 2390 }
2373 2391
2374 type = process_arg(event, field, &token); 2392 type = process_field_arg(event, field, &token);
2375 2393
2376 /* Handle operations in the first argument */ 2394 /* Handle operations in the first argument */
2377 while (type == EVENT_OP) 2395 while (type == EVENT_OP)
@@ -2424,7 +2442,8 @@ process_symbols(struct event_format *event, struct print_arg *arg, char **tok)
2424 goto out_free; 2442 goto out_free;
2425 } 2443 }
2426 2444
2427 type = process_arg(event, field, &token); 2445 type = process_field_arg(event, field, &token);
2446
2428 if (test_type_token(type, token, EVENT_DELIM, ",")) 2447 if (test_type_token(type, token, EVENT_DELIM, ","))
2429 goto out_free_field; 2448 goto out_free_field;
2430 2449
@@ -3446,7 +3465,7 @@ eval_num_arg(void *data, int size, struct event_format *event, struct print_arg
3446 * is in the bottom half of the 32 bit field. 3465 * is in the bottom half of the 32 bit field.
3447 */ 3466 */
3448 offset &= 0xffff; 3467 offset &= 0xffff;
3449 val = (unsigned long long)(data + offset); 3468 val = (unsigned long long)((unsigned long)data + offset);
3450 break; 3469 break;
3451 default: /* not sure what to do there */ 3470 default: /* not sure what to do there */
3452 return 0; 3471 return 0;
diff --git a/tools/perf/util/header.c b/tools/perf/util/header.c
index 369c03648f88..1cd035708931 100644
--- a/tools/perf/util/header.c
+++ b/tools/perf/util/header.c
@@ -2078,8 +2078,10 @@ static int process_group_desc(struct perf_file_section *section __maybe_unused,
2078 if (evsel->idx == (int) desc[i].leader_idx) { 2078 if (evsel->idx == (int) desc[i].leader_idx) {
2079 evsel->leader = evsel; 2079 evsel->leader = evsel;
2080 /* {anon_group} is a dummy name */ 2080 /* {anon_group} is a dummy name */
2081 if (strcmp(desc[i].name, "{anon_group}")) 2081 if (strcmp(desc[i].name, "{anon_group}")) {
2082 evsel->group_name = desc[i].name; 2082 evsel->group_name = desc[i].name;
2083 desc[i].name = NULL;
2084 }
2083 evsel->nr_members = desc[i].nr_members; 2085 evsel->nr_members = desc[i].nr_members;
2084 2086
2085 if (i >= nr_groups || nr > 0) { 2087 if (i >= nr_groups || nr > 0) {
@@ -2105,7 +2107,7 @@ static int process_group_desc(struct perf_file_section *section __maybe_unused,
2105 2107
2106 ret = 0; 2108 ret = 0;
2107out_free: 2109out_free:
2108 while ((int) --i >= 0) 2110 for (i = 0; i < nr_groups; i++)
2109 free(desc[i].name); 2111 free(desc[i].name);
2110 free(desc); 2112 free(desc);
2111 2113
diff --git a/tools/perf/util/thread.c b/tools/perf/util/thread.c
index cd8e2f592719..49eaf1d7d89d 100644
--- a/tools/perf/util/thread.c
+++ b/tools/perf/util/thread.c
@@ -70,14 +70,13 @@ int thread__set_comm(struct thread *thread, const char *str, u64 timestamp)
70 /* Override latest entry if it had no specific time coverage */ 70 /* Override latest entry if it had no specific time coverage */
71 if (!curr->start) { 71 if (!curr->start) {
72 comm__override(curr, str, timestamp); 72 comm__override(curr, str, timestamp);
73 return 0; 73 } else {
74 new = comm__new(str, timestamp);
75 if (!new)
76 return -ENOMEM;
77 list_add(&new->list, &thread->comm_list);
74 } 78 }
75 79
76 new = comm__new(str, timestamp);
77 if (!new)
78 return -ENOMEM;
79
80 list_add(&new->list, &thread->comm_list);
81 thread->comm_set = true; 80 thread->comm_set = true;
82 81
83 return 0; 82 return 0;
diff --git a/tools/power/cpupower/man/cpupower-idle-info.1 b/tools/power/cpupower/man/cpupower-idle-info.1
index 4178effd9e99..7b3646adb92f 100644
--- a/tools/power/cpupower/man/cpupower-idle-info.1
+++ b/tools/power/cpupower/man/cpupower-idle-info.1
@@ -87,4 +87,5 @@ Thomas Renninger <trenn@suse.de>
87.fi 87.fi
88.SH "SEE ALSO" 88.SH "SEE ALSO"
89.LP 89.LP
90cpupower(1), cpupower\-monitor(1), cpupower\-info(1), cpupower\-set(1) 90cpupower(1), cpupower\-monitor(1), cpupower\-info(1), cpupower\-set(1),
91cpupower\-idle\-set(1)
diff --git a/tools/power/cpupower/man/cpupower-idle-set.1 b/tools/power/cpupower/man/cpupower-idle-set.1
new file mode 100644
index 000000000000..6b1607272a5b
--- /dev/null
+++ b/tools/power/cpupower/man/cpupower-idle-set.1
@@ -0,0 +1,71 @@
1.TH "CPUPOWER-IDLE-SET" "1" "0.1" "" "cpupower Manual"
2.SH "NAME"
3.LP
4cpupower idle\-set \- Utility to set cpu idle state specific kernel options
5.SH "SYNTAX"
6.LP
7cpupower [ \-c cpulist ] idle\-info [\fIoptions\fP]
8.SH "DESCRIPTION"
9.LP
10The cpupower idle\-set subcommand allows to set cpu idle, also called cpu
11sleep state, specific options offered by the kernel. One example is disabling
12sleep states. This can be handy for power vs performance tuning.
13.SH "OPTIONS"
14.LP
15.TP
16\fB\-d\fR \fB\-\-disable\fR
17Disable a specific processor sleep state.
18.TP
19\fB\-e\fR \fB\-\-enable\fR
20Enable a specific processor sleep state.
21
22.SH "REMARKS"
23.LP
24Cpuidle Governors Policy on Disabling Sleep States
25
26.RS 4
27Depending on the used cpuidle governor, implementing the kernel policy
28how to choose sleep states, subsequent sleep states on this core, might get
29disabled as well.
30
31There are two cpuidle governors ladder and menu. While the ladder
32governor is always available, if CONFIG_CPU_IDLE is selected, the
33menu governor additionally requires CONFIG_NO_HZ.
34
35The behavior and the effect of the disable variable depends on the
36implementation of a particular governor. In the ladder governor, for
37example, it is not coherent, i.e. if one is disabling a light state,
38then all deeper states are disabled as well. Likewise, if one enables a
39deep state but a lighter state still is disabled, then this has no effect.
40.RE
41.LP
42Disabling the Lightest Sleep State may not have any Affect
43
44.RS 4
45If criteria are not met to enter deeper sleep states and the lightest sleep
46state is chosen when idle, the kernel may still enter this sleep state,
47irrespective of whether it is disabled or not. This is also reflected in
48the usage count of the disabled sleep state when using the cpupower idle-info
49command.
50.RE
51.LP
52Selecting specific CPU Cores
53
54.RS 4
55By default processor sleep states of all CPU cores are set. Please refer
56to the cpupower(1) manpage in the \-\-cpu option section how to disable
57C-states of specific cores.
58.RE
59.SH "FILES"
60.nf
61\fI/sys/devices/system/cpu/cpu*/cpuidle/state*\fP
62\fI/sys/devices/system/cpu/cpuidle/*\fP
63.fi
64.SH "AUTHORS"
65.nf
66Thomas Renninger <trenn@suse.de>
67.fi
68.SH "SEE ALSO"
69.LP
70cpupower(1), cpupower\-monitor(1), cpupower\-info(1), cpupower\-set(1),
71cpupower\-idle\-info(1)
diff --git a/tools/power/cpupower/utils/helpers/sysfs.c b/tools/power/cpupower/utils/helpers/sysfs.c
index 5cdc600e8152..851c7a16ca49 100644
--- a/tools/power/cpupower/utils/helpers/sysfs.c
+++ b/tools/power/cpupower/utils/helpers/sysfs.c
@@ -278,7 +278,7 @@ static char *sysfs_idlestate_get_one_string(unsigned int cpu,
278int sysfs_is_idlestate_disabled(unsigned int cpu, 278int sysfs_is_idlestate_disabled(unsigned int cpu,
279 unsigned int idlestate) 279 unsigned int idlestate)
280{ 280{
281 if (sysfs_get_idlestate_count(cpu) < idlestate) 281 if (sysfs_get_idlestate_count(cpu) <= idlestate)
282 return -1; 282 return -1;
283 283
284 if (!sysfs_idlestate_file_exists(cpu, idlestate, 284 if (!sysfs_idlestate_file_exists(cpu, idlestate,
@@ -303,7 +303,7 @@ int sysfs_idlestate_disable(unsigned int cpu,
303 char value[SYSFS_PATH_MAX]; 303 char value[SYSFS_PATH_MAX];
304 int bytes_written; 304 int bytes_written;
305 305
306 if (sysfs_get_idlestate_count(cpu) < idlestate) 306 if (sysfs_get_idlestate_count(cpu) <= idlestate)
307 return -1; 307 return -1;
308 308
309 if (!sysfs_idlestate_file_exists(cpu, idlestate, 309 if (!sysfs_idlestate_file_exists(cpu, idlestate,