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-rw-r--r--drivers/video/Kconfig14
-rw-r--r--drivers/video/Makefile1
-rw-r--r--drivers/video/bf537-lq035.c914
3 files changed, 929 insertions, 0 deletions
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 954f6e9d8d5a..04d09cac5a4d 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -643,6 +643,20 @@ config FB_BFIN_LQ035Q1
643 To compile this driver as a module, choose M here: the 643 To compile this driver as a module, choose M here: the
644 module will be called bfin-lq035q1-fb. 644 module will be called bfin-lq035q1-fb.
645 645
646config FB_BF537_LQ035
647 tristate "SHARP LQ035 TFT LCD (BF537 STAMP)"
648 depends on FB && (BF534 || BF536 || BF537) && I2C_BLACKFIN_TWI
649 select FB_CFB_FILLRECT
650 select FB_CFB_COPYAREA
651 select FB_CFB_IMAGEBLIT
652 select BFIN_GPTIMERS
653 help
654 This is the framebuffer device for a SHARP LQ035Q7DB03 TFT LCD
655 attached to a BF537.
656
657 To compile this driver as a module, choose M here: the
658 module will be called bf537-lq035.
659
646config FB_STI 660config FB_STI
647 tristate "HP STI frame buffer device support" 661 tristate "HP STI frame buffer device support"
648 depends on FB && PARISC 662 depends on FB && PARISC
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 8d916dcb379f..cf1c45d2e22d 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -144,6 +144,7 @@ obj-$(CONFIG_FB_VESA) += vesafb.o
144obj-$(CONFIG_FB_EFI) += efifb.o 144obj-$(CONFIG_FB_EFI) += efifb.o
145obj-$(CONFIG_FB_VGA16) += vga16fb.o 145obj-$(CONFIG_FB_VGA16) += vga16fb.o
146obj-$(CONFIG_FB_OF) += offb.o 146obj-$(CONFIG_FB_OF) += offb.o
147obj-$(CONFIG_FB_BF537_LQ035) += bf537-lq035.o
147obj-$(CONFIG_FB_BF54X_LQ043) += bf54x-lq043fb.o 148obj-$(CONFIG_FB_BF54X_LQ043) += bf54x-lq043fb.o
148obj-$(CONFIG_FB_BFIN_LQ035Q1) += bfin-lq035q1-fb.o 149obj-$(CONFIG_FB_BFIN_LQ035Q1) += bfin-lq035q1-fb.o
149obj-$(CONFIG_FB_BFIN_T350MCQB) += bfin-t350mcqb-fb.o 150obj-$(CONFIG_FB_BFIN_T350MCQB) += bfin-t350mcqb-fb.o
diff --git a/drivers/video/bf537-lq035.c b/drivers/video/bf537-lq035.c
new file mode 100644
index 000000000000..18c507874ff1
--- /dev/null
+++ b/drivers/video/bf537-lq035.c
@@ -0,0 +1,914 @@
1/*
2 * Analog Devices Blackfin(BF537 STAMP) + SHARP TFT LCD.
3 * http://docs.blackfin.uclinux.org/doku.php?id=hw:cards:tft-lcd
4 *
5 * Copyright 2006-2010 Analog Devices Inc.
6 * Licensed under the GPL-2.
7 */
8
9#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10
11#include <linux/module.h>
12#include <linux/kernel.h>
13#include <linux/errno.h>
14#include <linux/string.h>
15#include <linux/mm.h>
16#include <linux/delay.h>
17#include <linux/fb.h>
18#include <linux/ioport.h>
19#include <linux/init.h>
20#include <linux/types.h>
21#include <linux/gpio.h>
22#include <linux/interrupt.h>
23#include <linux/sched.h>
24#include <linux/timer.h>
25#include <linux/device.h>
26#include <linux/backlight.h>
27#include <linux/lcd.h>
28#include <linux/i2c.h>
29#include <linux/spinlock.h>
30#include <linux/dma-mapping.h>
31#include <linux/slab.h>
32#include <linux/platform_device.h>
33
34#include <asm/blackfin.h>
35#include <asm/irq.h>
36#include <asm/dpmc.h>
37#include <asm/dma.h>
38#include <asm/portmux.h>
39
40#define NO_BL 1
41
42#define MAX_BRIGHENESS 95
43#define MIN_BRIGHENESS 5
44#define NBR_PALETTE 256
45
46static const unsigned short ppi_pins[] = {
47 P_PPI0_CLK, P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
48 P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
49 P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
50 P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15, 0
51};
52
53static unsigned char *fb_buffer; /* RGB Buffer */
54static unsigned long *dma_desc_table;
55static int t_conf_done, lq035_open_cnt;
56static DEFINE_SPINLOCK(bfin_lq035_lock);
57
58static int landscape;
59module_param(landscape, int, 0);
60MODULE_PARM_DESC(landscape,
61 "LANDSCAPE use 320x240 instead of Native 240x320 Resolution");
62
63static int bgr;
64module_param(bgr, int, 0);
65MODULE_PARM_DESC(bgr,
66 "BGR use 16-bit BGR-565 instead of RGB-565");
67
68static int nocursor = 1;
69module_param(nocursor, int, 0644);
70MODULE_PARM_DESC(nocursor, "cursor enable/disable");
71
72static unsigned long current_brightness; /* backlight */
73
74/* AD5280 vcomm */
75static unsigned char vcomm_value = 150;
76static struct i2c_client *ad5280_client;
77
78static void set_vcomm(void)
79{
80 int nr;
81
82 if (!ad5280_client)
83 return;
84
85 nr = i2c_smbus_write_byte_data(ad5280_client, 0x00, vcomm_value);
86 if (nr)
87 pr_err("i2c_smbus_write_byte_data fail: %d\n", nr);
88}
89
90static int __devinit ad5280_probe(struct i2c_client *client,
91 const struct i2c_device_id *id)
92{
93 int ret;
94 if (!i2c_check_functionality(client->adapter,
95 I2C_FUNC_SMBUS_BYTE_DATA)) {
96 dev_err(&client->dev, "SMBUS Byte Data not Supported\n");
97 return -EIO;
98 }
99
100 ret = i2c_smbus_write_byte_data(client, 0x00, vcomm_value);
101 if (ret) {
102 dev_err(&client->dev, "write fail: %d\n", ret);
103 return ret;
104 }
105
106 ad5280_client = client;
107
108 return 0;
109}
110
111static int __devexit ad5280_remove(struct i2c_client *client)
112{
113 ad5280_client = NULL;
114 return 0;
115}
116
117static const struct i2c_device_id ad5280_id[] = {
118 {"bf537-lq035-ad5280", 0},
119 {}
120};
121
122MODULE_DEVICE_TABLE(i2c, ad5280_id);
123
124static struct i2c_driver ad5280_driver = {
125 .driver = {
126 .name = "bf537-lq035-ad5280",
127 },
128 .probe = ad5280_probe,
129 .remove = __devexit_p(ad5280_remove),
130 .id_table = ad5280_id,
131};
132
133#ifdef CONFIG_PNAV10
134#define MOD GPIO_PH13
135
136#define bfin_write_TIMER_LP_CONFIG bfin_write_TIMER0_CONFIG
137#define bfin_write_TIMER_LP_WIDTH bfin_write_TIMER0_WIDTH
138#define bfin_write_TIMER_LP_PERIOD bfin_write_TIMER0_PERIOD
139#define bfin_read_TIMER_LP_COUNTER bfin_read_TIMER0_COUNTER
140#define TIMDIS_LP TIMDIS0
141#define TIMEN_LP TIMEN0
142
143#define bfin_write_TIMER_SPS_CONFIG bfin_write_TIMER1_CONFIG
144#define bfin_write_TIMER_SPS_WIDTH bfin_write_TIMER1_WIDTH
145#define bfin_write_TIMER_SPS_PERIOD bfin_write_TIMER1_PERIOD
146#define TIMDIS_SPS TIMDIS1
147#define TIMEN_SPS TIMEN1
148
149#define bfin_write_TIMER_SP_CONFIG bfin_write_TIMER5_CONFIG
150#define bfin_write_TIMER_SP_WIDTH bfin_write_TIMER5_WIDTH
151#define bfin_write_TIMER_SP_PERIOD bfin_write_TIMER5_PERIOD
152#define TIMDIS_SP TIMDIS5
153#define TIMEN_SP TIMEN5
154
155#define bfin_write_TIMER_PS_CLS_CONFIG bfin_write_TIMER2_CONFIG
156#define bfin_write_TIMER_PS_CLS_WIDTH bfin_write_TIMER2_WIDTH
157#define bfin_write_TIMER_PS_CLS_PERIOD bfin_write_TIMER2_PERIOD
158#define TIMDIS_PS_CLS TIMDIS2
159#define TIMEN_PS_CLS TIMEN2
160
161#define bfin_write_TIMER_REV_CONFIG bfin_write_TIMER3_CONFIG
162#define bfin_write_TIMER_REV_WIDTH bfin_write_TIMER3_WIDTH
163#define bfin_write_TIMER_REV_PERIOD bfin_write_TIMER3_PERIOD
164#define TIMDIS_REV TIMDIS3
165#define TIMEN_REV TIMEN3
166#define bfin_read_TIMER_REV_COUNTER bfin_read_TIMER3_COUNTER
167
168#define FREQ_PPI_CLK (5*1024*1024) /* PPI_CLK 5MHz */
169
170#define TIMERS {P_TMR0, P_TMR1, P_TMR2, P_TMR3, P_TMR5, 0}
171
172#else
173
174#define UD GPIO_PF13 /* Up / Down */
175#define MOD GPIO_PF10
176#define LBR GPIO_PF14 /* Left Right */
177
178#define bfin_write_TIMER_LP_CONFIG bfin_write_TIMER6_CONFIG
179#define bfin_write_TIMER_LP_WIDTH bfin_write_TIMER6_WIDTH
180#define bfin_write_TIMER_LP_PERIOD bfin_write_TIMER6_PERIOD
181#define bfin_read_TIMER_LP_COUNTER bfin_read_TIMER6_COUNTER
182#define TIMDIS_LP TIMDIS6
183#define TIMEN_LP TIMEN6
184
185#define bfin_write_TIMER_SPS_CONFIG bfin_write_TIMER1_CONFIG
186#define bfin_write_TIMER_SPS_WIDTH bfin_write_TIMER1_WIDTH
187#define bfin_write_TIMER_SPS_PERIOD bfin_write_TIMER1_PERIOD
188#define TIMDIS_SPS TIMDIS1
189#define TIMEN_SPS TIMEN1
190
191#define bfin_write_TIMER_SP_CONFIG bfin_write_TIMER0_CONFIG
192#define bfin_write_TIMER_SP_WIDTH bfin_write_TIMER0_WIDTH
193#define bfin_write_TIMER_SP_PERIOD bfin_write_TIMER0_PERIOD
194#define TIMDIS_SP TIMDIS0
195#define TIMEN_SP TIMEN0
196
197#define bfin_write_TIMER_PS_CLS_CONFIG bfin_write_TIMER7_CONFIG
198#define bfin_write_TIMER_PS_CLS_WIDTH bfin_write_TIMER7_WIDTH
199#define bfin_write_TIMER_PS_CLS_PERIOD bfin_write_TIMER7_PERIOD
200#define TIMDIS_PS_CLS TIMDIS7
201#define TIMEN_PS_CLS TIMEN7
202
203#define bfin_write_TIMER_REV_CONFIG bfin_write_TIMER5_CONFIG
204#define bfin_write_TIMER_REV_WIDTH bfin_write_TIMER5_WIDTH
205#define bfin_write_TIMER_REV_PERIOD bfin_write_TIMER5_PERIOD
206#define TIMDIS_REV TIMDIS5
207#define TIMEN_REV TIMEN5
208#define bfin_read_TIMER_REV_COUNTER bfin_read_TIMER5_COUNTER
209
210#define FREQ_PPI_CLK (6*1000*1000) /* PPI_CLK 6MHz */
211#define TIMERS {P_TMR0, P_TMR1, P_TMR5, P_TMR6, P_TMR7, 0}
212
213#endif
214
215#define LCD_X_RES 240 /* Horizontal Resolution */
216#define LCD_Y_RES 320 /* Vertical Resolution */
217
218#define LCD_BBP 16 /* Bit Per Pixel */
219
220/* the LCD and the DMA start counting differently;
221 * since one starts at 0 and the other starts at 1,
222 * we have a difference of 1 between START_LINES
223 * and U_LINES.
224 */
225#define START_LINES 8 /* lines for field flyback or field blanking signal */
226#define U_LINES 9 /* number of undisplayed blanking lines */
227
228#define FRAMES_PER_SEC (60)
229
230#define DCLKS_PER_FRAME (FREQ_PPI_CLK/FRAMES_PER_SEC)
231#define DCLKS_PER_LINE (DCLKS_PER_FRAME/(LCD_Y_RES+U_LINES))
232
233#define PPI_CONFIG_VALUE (PORT_DIR|XFR_TYPE|DLEN_16|POLS)
234#define PPI_DELAY_VALUE (0)
235#define TIMER_CONFIG (PWM_OUT|PERIOD_CNT|TIN_SEL|CLK_SEL)
236
237#define ACTIVE_VIDEO_MEM_OFFSET (LCD_X_RES*START_LINES*(LCD_BBP/8))
238#define ACTIVE_VIDEO_MEM_SIZE (LCD_Y_RES*LCD_X_RES*(LCD_BBP/8))
239#define TOTAL_VIDEO_MEM_SIZE ((LCD_Y_RES+U_LINES)*LCD_X_RES*(LCD_BBP/8))
240#define TOTAL_DMA_DESC_SIZE (2 * sizeof(u32) * (LCD_Y_RES + U_LINES))
241
242static void start_timers(void) /* CHECK with HW */
243{
244 unsigned long flags;
245
246 local_irq_save(flags);
247
248 bfin_write_TIMER_ENABLE(TIMEN_REV);
249 SSYNC();
250
251 while (bfin_read_TIMER_REV_COUNTER() <= 11)
252 continue;
253 bfin_write_TIMER_ENABLE(TIMEN_LP);
254 SSYNC();
255
256 while (bfin_read_TIMER_LP_COUNTER() < 3)
257 continue;
258 bfin_write_TIMER_ENABLE(TIMEN_SP|TIMEN_SPS|TIMEN_PS_CLS);
259 SSYNC();
260 t_conf_done = 1;
261 local_irq_restore(flags);
262}
263
264static void config_timers(void)
265{
266 /* Stop timers */
267 bfin_write_TIMER_DISABLE(TIMDIS_SP|TIMDIS_SPS|TIMDIS_REV|
268 TIMDIS_LP|TIMDIS_PS_CLS);
269 SSYNC();
270
271 /* LP, timer 6 */
272 bfin_write_TIMER_LP_CONFIG(TIMER_CONFIG|PULSE_HI);
273 bfin_write_TIMER_LP_WIDTH(1);
274
275 bfin_write_TIMER_LP_PERIOD(DCLKS_PER_LINE);
276 SSYNC();
277
278 /* SPS, timer 1 */
279 bfin_write_TIMER_SPS_CONFIG(TIMER_CONFIG|PULSE_HI);
280 bfin_write_TIMER_SPS_WIDTH(DCLKS_PER_LINE*2);
281 bfin_write_TIMER_SPS_PERIOD((DCLKS_PER_LINE * (LCD_Y_RES+U_LINES)));
282 SSYNC();
283
284 /* SP, timer 0 */
285 bfin_write_TIMER_SP_CONFIG(TIMER_CONFIG|PULSE_HI);
286 bfin_write_TIMER_SP_WIDTH(1);
287 bfin_write_TIMER_SP_PERIOD(DCLKS_PER_LINE);
288 SSYNC();
289
290 /* PS & CLS, timer 7 */
291 bfin_write_TIMER_PS_CLS_CONFIG(TIMER_CONFIG);
292 bfin_write_TIMER_PS_CLS_WIDTH(LCD_X_RES + START_LINES);
293 bfin_write_TIMER_PS_CLS_PERIOD(DCLKS_PER_LINE);
294
295 SSYNC();
296
297#ifdef NO_BL
298 /* REV, timer 5 */
299 bfin_write_TIMER_REV_CONFIG(TIMER_CONFIG|PULSE_HI);
300
301 bfin_write_TIMER_REV_WIDTH(DCLKS_PER_LINE);
302 bfin_write_TIMER_REV_PERIOD(DCLKS_PER_LINE*2);
303
304 SSYNC();
305#endif
306}
307
308static void config_ppi(void)
309{
310 bfin_write_PPI_DELAY(PPI_DELAY_VALUE);
311 bfin_write_PPI_COUNT(LCD_X_RES-1);
312 /* 0x10 -> PORT_CFG -> 2 or 3 frame syncs */
313 bfin_write_PPI_CONTROL((PPI_CONFIG_VALUE|0x10) & (~POLS));
314}
315
316static int config_dma(void)
317{
318 u32 i;
319
320 if (landscape) {
321
322 for (i = 0; i < U_LINES; ++i) {
323 /* blanking lines point to first line of fb_buffer */
324 dma_desc_table[2*i] = (unsigned long)&dma_desc_table[2*i+2];
325 dma_desc_table[2*i+1] = (unsigned long)fb_buffer;
326 }
327
328 for (i = U_LINES; i < U_LINES + LCD_Y_RES; ++i) {
329 /* visible lines */
330 dma_desc_table[2*i] = (unsigned long)&dma_desc_table[2*i+2];
331 dma_desc_table[2*i+1] = (unsigned long)fb_buffer +
332 (LCD_Y_RES+U_LINES-1-i)*2;
333 }
334
335 /* last descriptor points to first */
336 dma_desc_table[2*(LCD_Y_RES+U_LINES-1)] = (unsigned long)&dma_desc_table[0];
337
338 set_dma_x_count(CH_PPI, LCD_X_RES);
339 set_dma_x_modify(CH_PPI, LCD_Y_RES * (LCD_BBP / 8));
340 set_dma_y_count(CH_PPI, 0);
341 set_dma_y_modify(CH_PPI, 0);
342 set_dma_next_desc_addr(CH_PPI, (void *)dma_desc_table[0]);
343 set_dma_config(CH_PPI, DMAFLOW_LARGE | NDSIZE_4 | WDSIZE_16);
344
345 } else {
346
347 set_dma_config(CH_PPI, set_bfin_dma_config(DIR_READ,
348 DMA_FLOW_AUTO,
349 INTR_DISABLE,
350 DIMENSION_2D,
351 DATA_SIZE_16,
352 DMA_NOSYNC_KEEP_DMA_BUF));
353 set_dma_x_count(CH_PPI, LCD_X_RES);
354 set_dma_x_modify(CH_PPI, LCD_BBP / 8);
355 set_dma_y_count(CH_PPI, LCD_Y_RES+U_LINES);
356 set_dma_y_modify(CH_PPI, LCD_BBP / 8);
357 set_dma_start_addr(CH_PPI, (unsigned long) fb_buffer);
358 }
359
360 return 0;
361}
362
363static int __devinit request_ports(void)
364{
365 u16 tmr_req[] = TIMERS;
366
367 /*
368 UD: PF13
369 MOD: PF10
370 LBR: PF14
371 PPI_CLK: PF15
372 */
373
374 if (peripheral_request_list(ppi_pins, KBUILD_MODNAME)) {
375 pr_err("requesting PPI peripheral failed\n");
376 return -EBUSY;
377 }
378
379 if (peripheral_request_list(tmr_req, KBUILD_MODNAME)) {
380 peripheral_free_list(ppi_pins);
381 pr_err("requesting timer peripheral failed\n");
382 return -EBUSY;
383 }
384
385#if (defined(UD) && defined(LBR))
386 if (gpio_request(UD, KBUILD_MODNAME)) {
387 pr_err("requesting GPIO %d failed\n", UD);
388 return -EBUSY;
389 }
390
391 if (gpio_request(LBR, KBUILD_MODNAME)) {
392 pr_err("requesting GPIO %d failed\n", LBR);
393 gpio_free(UD);
394 return -EBUSY;
395 }
396
397 gpio_direction_output(UD, 0);
398 gpio_direction_output(LBR, 1);
399
400#endif
401
402 if (gpio_request(MOD, KBUILD_MODNAME)) {
403 pr_err("requesting GPIO %d failed\n", MOD);
404#if (defined(UD) && defined(LBR))
405 gpio_free(LBR);
406 gpio_free(UD);
407#endif
408 return -EBUSY;
409 }
410
411 gpio_direction_output(MOD, 1);
412
413 SSYNC();
414 return 0;
415}
416
417static void free_ports(void)
418{
419 u16 tmr_req[] = TIMERS;
420
421 peripheral_free_list(ppi_pins);
422 peripheral_free_list(tmr_req);
423
424#if defined(UD) && defined(LBR)
425 gpio_free(LBR);
426 gpio_free(UD);
427#endif
428 gpio_free(MOD);
429}
430
431static struct fb_info bfin_lq035_fb;
432
433static struct fb_var_screeninfo bfin_lq035_fb_defined = {
434 .bits_per_pixel = LCD_BBP,
435 .activate = FB_ACTIVATE_TEST,
436 .xres = LCD_X_RES, /*default portrait mode RGB*/
437 .yres = LCD_Y_RES,
438 .xres_virtual = LCD_X_RES,
439 .yres_virtual = LCD_Y_RES,
440 .height = -1,
441 .width = -1,
442 .left_margin = 0,
443 .right_margin = 0,
444 .upper_margin = 0,
445 .lower_margin = 0,
446 .red = {11, 5, 0},
447 .green = {5, 6, 0},
448 .blue = {0, 5, 0},
449 .transp = {0, 0, 0},
450};
451
452static struct fb_fix_screeninfo bfin_lq035_fb_fix __devinitdata = {
453 .id = KBUILD_MODNAME,
454 .smem_len = ACTIVE_VIDEO_MEM_SIZE,
455 .type = FB_TYPE_PACKED_PIXELS,
456 .visual = FB_VISUAL_TRUECOLOR,
457 .xpanstep = 0,
458 .ypanstep = 0,
459 .line_length = LCD_X_RES*(LCD_BBP/8),
460 .accel = FB_ACCEL_NONE,
461};
462
463
464static int bfin_lq035_fb_open(struct fb_info *info, int user)
465{
466 unsigned long flags;
467
468 spin_lock_irqsave(&bfin_lq035_lock, flags);
469 lq035_open_cnt++;
470 spin_unlock_irqrestore(&bfin_lq035_lock, flags);
471
472 if (lq035_open_cnt <= 1) {
473 bfin_write_PPI_CONTROL(0);
474 SSYNC();
475
476 set_vcomm();
477 config_dma();
478 config_ppi();
479
480 /* start dma */
481 enable_dma(CH_PPI);
482 SSYNC();
483 bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() | PORT_EN);
484 SSYNC();
485
486 if (!t_conf_done) {
487 config_timers();
488 start_timers();
489 }
490 /* gpio_set_value(MOD,1); */
491 }
492
493 return 0;
494}
495
496static int bfin_lq035_fb_release(struct fb_info *info, int user)
497{
498 unsigned long flags;
499
500 spin_lock_irqsave(&bfin_lq035_lock, flags);
501 lq035_open_cnt--;
502 spin_unlock_irqrestore(&bfin_lq035_lock, flags);
503
504
505 if (lq035_open_cnt <= 0) {
506
507 bfin_write_PPI_CONTROL(0);
508 SSYNC();
509
510 disable_dma(CH_PPI);
511 }
512
513 return 0;
514}
515
516
517static int bfin_lq035_fb_check_var(struct fb_var_screeninfo *var,
518 struct fb_info *info)
519{
520 switch (var->bits_per_pixel) {
521 case 16:/* DIRECTCOLOUR, 64k */
522 var->red.offset = info->var.red.offset;
523 var->green.offset = info->var.green.offset;
524 var->blue.offset = info->var.blue.offset;
525 var->red.length = info->var.red.length;
526 var->green.length = info->var.green.length;
527 var->blue.length = info->var.blue.length;
528 var->transp.offset = 0;
529 var->transp.length = 0;
530 var->transp.msb_right = 0;
531 var->red.msb_right = 0;
532 var->green.msb_right = 0;
533 var->blue.msb_right = 0;
534 break;
535 default:
536 pr_debug("%s: depth not supported: %u BPP\n", __func__,
537 var->bits_per_pixel);
538 return -EINVAL;
539 }
540
541 if (info->var.xres != var->xres ||
542 info->var.yres != var->yres ||
543 info->var.xres_virtual != var->xres_virtual ||
544 info->var.yres_virtual != var->yres_virtual) {
545 pr_debug("%s: Resolution not supported: X%u x Y%u\n",
546 __func__, var->xres, var->yres);
547 return -EINVAL;
548 }
549
550 /*
551 * Memory limit
552 */
553
554 if ((info->fix.line_length * var->yres_virtual) > info->fix.smem_len) {
555 pr_debug("%s: Memory Limit requested yres_virtual = %u\n",
556 __func__, var->yres_virtual);
557 return -ENOMEM;
558 }
559
560 return 0;
561}
562
563/* fb_rotate
564 * Rotate the display of this angle. This doesn't seems to be used by the core,
565 * but as our hardware supports it, so why not implementing it...
566 */
567static void bfin_lq035_fb_rotate(struct fb_info *fbi, int angle)
568{
569 pr_debug("%s: %p %d", __func__, fbi, angle);
570#if (defined(UD) && defined(LBR))
571 switch (angle) {
572
573 case 180:
574 gpio_set_value(LBR, 0);
575 gpio_set_value(UD, 1);
576 break;
577 default:
578 gpio_set_value(LBR, 1);
579 gpio_set_value(UD, 0);
580 break;
581 }
582#endif
583}
584
585static int bfin_lq035_fb_cursor(struct fb_info *info, struct fb_cursor *cursor)
586{
587 if (nocursor)
588 return 0;
589 else
590 return -EINVAL; /* just to force soft_cursor() call */
591}
592
593static int bfin_lq035_fb_setcolreg(u_int regno, u_int red, u_int green,
594 u_int blue, u_int transp,
595 struct fb_info *info)
596{
597 if (regno >= NBR_PALETTE)
598 return -EINVAL;
599
600 if (info->var.grayscale)
601 /* grayscale = 0.30*R + 0.59*G + 0.11*B */
602 red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
603
604 if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
605
606 u32 value;
607 /* Place color in the pseudopalette */
608 if (regno > 16)
609 return -EINVAL;
610
611 red >>= (16 - info->var.red.length);
612 green >>= (16 - info->var.green.length);
613 blue >>= (16 - info->var.blue.length);
614
615 value = (red << info->var.red.offset) |
616 (green << info->var.green.offset)|
617 (blue << info->var.blue.offset);
618 value &= 0xFFFF;
619
620 ((u32 *) (info->pseudo_palette))[regno] = value;
621
622 }
623
624 return 0;
625}
626
627static struct fb_ops bfin_lq035_fb_ops = {
628 .owner = THIS_MODULE,
629 .fb_open = bfin_lq035_fb_open,
630 .fb_release = bfin_lq035_fb_release,
631 .fb_check_var = bfin_lq035_fb_check_var,
632 .fb_rotate = bfin_lq035_fb_rotate,
633 .fb_fillrect = cfb_fillrect,
634 .fb_copyarea = cfb_copyarea,
635 .fb_imageblit = cfb_imageblit,
636 .fb_cursor = bfin_lq035_fb_cursor,
637 .fb_setcolreg = bfin_lq035_fb_setcolreg,
638};
639
640static int bl_get_brightness(struct backlight_device *bd)
641{
642 return current_brightness;
643}
644
645static const struct backlight_ops bfin_lq035fb_bl_ops = {
646 .get_brightness = bl_get_brightness,
647};
648
649static struct backlight_device *bl_dev;
650
651static int bfin_lcd_get_power(struct lcd_device *dev)
652{
653 return 0;
654}
655
656static int bfin_lcd_set_power(struct lcd_device *dev, int power)
657{
658 return 0;
659}
660
661static int bfin_lcd_get_contrast(struct lcd_device *dev)
662{
663 return (int)vcomm_value;
664}
665
666static int bfin_lcd_set_contrast(struct lcd_device *dev, int contrast)
667{
668 if (contrast > 255)
669 contrast = 255;
670 if (contrast < 0)
671 contrast = 0;
672
673 vcomm_value = (unsigned char)contrast;
674 set_vcomm();
675 return 0;
676}
677
678static int bfin_lcd_check_fb(struct lcd_device *lcd, struct fb_info *fi)
679{
680 if (!fi || (fi == &bfin_lq035_fb))
681 return 1;
682 return 0;
683}
684
685static struct lcd_ops bfin_lcd_ops = {
686 .get_power = bfin_lcd_get_power,
687 .set_power = bfin_lcd_set_power,
688 .get_contrast = bfin_lcd_get_contrast,
689 .set_contrast = bfin_lcd_set_contrast,
690 .check_fb = bfin_lcd_check_fb,
691};
692
693static struct lcd_device *lcd_dev;
694
695static int __devinit bfin_lq035_probe(struct platform_device *pdev)
696{
697 struct backlight_properties props;
698 dma_addr_t dma_handle;
699
700 if (request_dma(CH_PPI, KBUILD_MODNAME)) {
701 pr_err("couldn't request PPI DMA\n");
702 return -EFAULT;
703 }
704
705 if (request_ports()) {
706 pr_err("couldn't request gpio port\n");
707 free_dma(CH_PPI);
708 return -EFAULT;
709 }
710
711 fb_buffer = dma_alloc_coherent(NULL, TOTAL_VIDEO_MEM_SIZE,
712 &dma_handle, GFP_KERNEL);
713 if (fb_buffer == NULL) {
714 pr_err("couldn't allocate dma buffer\n");
715 free_dma(CH_PPI);
716 free_ports();
717 return -ENOMEM;
718 }
719
720 if (L1_DATA_A_LENGTH)
721 dma_desc_table = l1_data_sram_zalloc(TOTAL_DMA_DESC_SIZE);
722 else
723 dma_desc_table = dma_alloc_coherent(NULL, TOTAL_DMA_DESC_SIZE,
724 &dma_handle, 0);
725
726 if (dma_desc_table == NULL) {
727 pr_err("couldn't allocate dma descriptor\n");
728 free_dma(CH_PPI);
729 free_ports();
730 dma_free_coherent(NULL, TOTAL_VIDEO_MEM_SIZE, fb_buffer, 0);
731 return -ENOMEM;
732 }
733
734 bfin_lq035_fb.screen_base = (void *)fb_buffer;
735 bfin_lq035_fb_fix.smem_start = (int)fb_buffer;
736 if (landscape) {
737 bfin_lq035_fb_defined.xres = LCD_Y_RES;
738 bfin_lq035_fb_defined.yres = LCD_X_RES;
739 bfin_lq035_fb_defined.xres_virtual = LCD_Y_RES;
740 bfin_lq035_fb_defined.yres_virtual = LCD_X_RES;
741
742 bfin_lq035_fb_fix.line_length = LCD_Y_RES*(LCD_BBP/8);
743 } else {
744 bfin_lq035_fb.screen_base += ACTIVE_VIDEO_MEM_OFFSET;
745 bfin_lq035_fb_fix.smem_start += ACTIVE_VIDEO_MEM_OFFSET;
746 }
747
748 bfin_lq035_fb_defined.green.msb_right = 0;
749 bfin_lq035_fb_defined.red.msb_right = 0;
750 bfin_lq035_fb_defined.blue.msb_right = 0;
751 bfin_lq035_fb_defined.green.offset = 5;
752 bfin_lq035_fb_defined.green.length = 6;
753 bfin_lq035_fb_defined.red.length = 5;
754 bfin_lq035_fb_defined.blue.length = 5;
755
756 if (bgr) {
757 bfin_lq035_fb_defined.red.offset = 0;
758 bfin_lq035_fb_defined.blue.offset = 11;
759 } else {
760 bfin_lq035_fb_defined.red.offset = 11;
761 bfin_lq035_fb_defined.blue.offset = 0;
762 }
763
764 bfin_lq035_fb.fbops = &bfin_lq035_fb_ops;
765 bfin_lq035_fb.var = bfin_lq035_fb_defined;
766
767 bfin_lq035_fb.fix = bfin_lq035_fb_fix;
768 bfin_lq035_fb.flags = FBINFO_DEFAULT;
769
770
771 bfin_lq035_fb.pseudo_palette = kzalloc(sizeof(u32) * 16, GFP_KERNEL);
772 if (bfin_lq035_fb.pseudo_palette == NULL) {
773 pr_err("failed to allocate pseudo_palette\n");
774 free_dma(CH_PPI);
775 free_ports();
776 dma_free_coherent(NULL, TOTAL_VIDEO_MEM_SIZE, fb_buffer, 0);
777 return -ENOMEM;
778 }
779
780 if (fb_alloc_cmap(&bfin_lq035_fb.cmap, NBR_PALETTE, 0) < 0) {
781 pr_err("failed to allocate colormap (%d entries)\n",
782 NBR_PALETTE);
783 free_dma(CH_PPI);
784 free_ports();
785 dma_free_coherent(NULL, TOTAL_VIDEO_MEM_SIZE, fb_buffer, 0);
786 kfree(bfin_lq035_fb.pseudo_palette);
787 return -EFAULT;
788 }
789
790 if (register_framebuffer(&bfin_lq035_fb) < 0) {
791 pr_err("unable to register framebuffer\n");
792 free_dma(CH_PPI);
793 free_ports();
794 dma_free_coherent(NULL, TOTAL_VIDEO_MEM_SIZE, fb_buffer, 0);
795 fb_buffer = NULL;
796 kfree(bfin_lq035_fb.pseudo_palette);
797 fb_dealloc_cmap(&bfin_lq035_fb.cmap);
798 return -EINVAL;
799 }
800
801 i2c_add_driver(&ad5280_driver);
802
803 memset(&props, 0, sizeof(props));
804 props.max_brightness = MAX_BRIGHENESS;
805 bl_dev = backlight_device_register("bf537-bl", NULL, NULL,
806 &bfin_lq035fb_bl_ops, &props);
807
808 lcd_dev = lcd_device_register(KBUILD_MODNAME, &pdev->dev, NULL,
809 &bfin_lcd_ops);
810 lcd_dev->props.max_contrast = 255,
811
812 pr_info("initialized");
813
814 return 0;
815}
816
817static int __devexit bfin_lq035_remove(struct platform_device *pdev)
818{
819 if (fb_buffer != NULL)
820 dma_free_coherent(NULL, TOTAL_VIDEO_MEM_SIZE, fb_buffer, 0);
821
822 if (L1_DATA_A_LENGTH)
823 l1_data_sram_free(dma_desc_table);
824 else
825 dma_free_coherent(NULL, TOTAL_DMA_DESC_SIZE, NULL, 0);
826
827 bfin_write_TIMER_DISABLE(TIMEN_SP|TIMEN_SPS|TIMEN_PS_CLS|
828 TIMEN_LP|TIMEN_REV);
829 t_conf_done = 0;
830
831 free_dma(CH_PPI);
832
833
834 kfree(bfin_lq035_fb.pseudo_palette);
835 fb_dealloc_cmap(&bfin_lq035_fb.cmap);
836
837
838 lcd_device_unregister(lcd_dev);
839 backlight_device_unregister(bl_dev);
840
841 unregister_framebuffer(&bfin_lq035_fb);
842 i2c_del_driver(&ad5280_driver);
843
844 free_ports();
845
846 pr_info("unregistered LCD driver\n");
847
848 return 0;
849}
850
851#ifdef CONFIG_PM
852static int bfin_lq035_suspend(struct platform_device *pdev, pm_message_t state)
853{
854 if (lq035_open_cnt > 0) {
855 bfin_write_PPI_CONTROL(0);
856 SSYNC();
857 disable_dma(CH_PPI);
858 }
859
860 return 0;
861}
862
863static int bfin_lq035_resume(struct platform_device *pdev)
864{
865 if (lq035_open_cnt > 0) {
866 bfin_write_PPI_CONTROL(0);
867 SSYNC();
868
869 config_dma();
870 config_ppi();
871
872 enable_dma(CH_PPI);
873 bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() | PORT_EN);
874 SSYNC();
875
876 config_timers();
877 start_timers();
878 } else {
879 t_conf_done = 0;
880 }
881
882 return 0;
883}
884#else
885# define bfin_lq035_suspend NULL
886# define bfin_lq035_resume NULL
887#endif
888
889static struct platform_driver bfin_lq035_driver = {
890 .probe = bfin_lq035_probe,
891 .remove = __devexit_p(bfin_lq035_remove),
892 .suspend = bfin_lq035_suspend,
893 .resume = bfin_lq035_resume,
894 .driver = {
895 .name = KBUILD_MODNAME,
896 .owner = THIS_MODULE,
897 },
898};
899
900static int __init bfin_lq035_driver_init(void)
901{
902 request_module("i2c-bfin-twi");
903 return platform_driver_register(&bfin_lq035_driver);
904}
905module_init(bfin_lq035_driver_init);
906
907static void __exit bfin_lq035_driver_cleanup(void)
908{
909 platform_driver_unregister(&bfin_lq035_driver);
910}
911module_exit(bfin_lq035_driver_cleanup);
912
913MODULE_DESCRIPTION("SHARP LQ035Q7DB03 TFT LCD Driver");
914MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-06 01:00:43 -0500