12 files changed, 599 insertions, 14 deletions

diff --git a/Documentation/devicetree/bindings/gpio/sodaville.txt b/Documentation/devicetree/bindings/gpio/sodaville.txt
new file mode 100644
index 000000000000..563eff22b975
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/sodaville.txt
@@ -0,0 +1,48 @@
+GPIO controller on CE4100 / Sodaville SoCs
+==========================================
+
+The bindings for CE4100's GPIO controller match the generic description
+which is covered by the gpio.txt file in this folder.
+
+The only additional property is the intel,muxctl property which holds the
+value which is written into the MUXCNTL register.
+
+There is no compatible property for now because the driver is probed via
+PCI id (vendor 0x8086 device 0x2e67).
+
+The interrupt specifier consists of two cells encoded as follows:
+ - <1st cell>: The interrupt-number that identifies the interrupt source.
+ - <2nd cell>: The level-sense information, encoded as follows:
+                4 - active high level-sensitive
+                8 - active low level-sensitive
+
+Example of the GPIO device and one user:
+
+        pcigpio: gpio@b,1 {
+                        /* two cells for GPIO and interrupt */
+                        #gpio-cells = <2>;
+                        #interrupt-cells = <2>;
+                        compatible = "pci8086,2e67.2",
+                                           "pci8086,2e67",
+                                           "pciclassff0000",
+                                           "pciclassff00";
+
+                        reg = <0x15900 0x0 0x0 0x0 0x0>;
+                        /* Interrupt line of the gpio device */
+                        interrupts = <15 1>;
+                        /* It is an interrupt and GPIO controller itself */
+                        interrupt-controller;
+                        gpio-controller;
+                        intel,muxctl = <0>;
+        };
+
+        testuser@20 {
+                        compatible = "example,testuser";
+                        /* User the 11th GPIO line as an active high triggered
+                         * level interrupt
+                         */
+                        interrupts = <11 8>;
+                        interrupt-parent = <&pcigpio>;
+                        /* Use this GPIO also with the gpio functions */
+                        gpios = <&pcigpio 11 0>;
+        };
diff --git a/arch/x86/platform/ce4100/falconfalls.dts b/arch/x86/platform/ce4100/falconfalls.dts
index e70be38ce039..ce874f872cc6 100644
--- a/arch/x86/platform/ce4100/falconfalls.dts
+++ b/arch/x86/platform/ce4100/falconfalls.dts
@@ -208,16 +208,19 @@
                                         interrupts = <14 1>;
                                 };
 
-                                gpio@b,1 {
+                                pcigpio: gpio@b,1 {
+                                        #gpio-cells = <2>;
+                                        #interrupt-cells = <2>;
                                         compatible = "pci8086,2e67.2",
                                                    "pci8086,2e67",
                                                    "pciclassff0000",
                                                    "pciclassff00";
 
-                                        #gpio-cells = <2>;
                                         reg = <0x15900 0x0 0x0 0x0 0x0>;
                                         interrupts = <15 1>;
+                                        interrupt-controller;
                                         gpio-controller;
+                                        intel,muxctl = <0>;
                                 };
 
                                 i2c-controller@b,2 {
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index d0c41188d4e5..dbb1909ca0a2 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -225,6 +225,12 @@ config GPIO_MAX732X_IRQ
           Say yes here to enable the max732x to be used as an interrupt
           controller. It requires the driver to be built in the kernel.
 
+config GPIO_MC9S08DZ60
+        bool "MX35 3DS BOARD MC9S08DZ60 GPIO functions"
+        depends on I2C && MACH_MX35_3DS
+        help
+          Select this to enable the MC9S08DZ60 GPIO driver
+
 config GPIO_PCA953X
         tristate "PCA953x, PCA955x, TCA64xx, and MAX7310 I/O ports"
         depends on I2C
@@ -411,6 +417,14 @@ config GPIO_ML_IOH
           Hub) which is for IVI(In-Vehicle Infotainment) use.
           This driver can access the IOH's GPIO device.
 
+config GPIO_SODAVILLE
+        bool "Intel Sodaville GPIO support"
+        depends on X86 && PCI && OF
+        select GPIO_GENERIC
+        select GENERIC_IRQ_CHIP
+        help
+          Say Y here to support Intel Sodaville GPIO.
+
 config GPIO_TIMBERDALE
         bool "Support for timberdale GPIO IP"
         depends on MFD_TIMBERDALE && HAS_IOMEM
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index fa10df604c01..593bdcd1976e 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_GPIO_MAX7300)	+= gpio-max7300.o
 obj-$(CONFIG_GPIO_MAX7301)      += gpio-max7301.o
 obj-$(CONFIG_GPIO_MAX732X)      += gpio-max732x.o
 obj-$(CONFIG_GPIO_MC33880)      += gpio-mc33880.o
+obj-$(CONFIG_GPIO_MC9S08DZ60)   += gpio-mc9s08dz60.o
 obj-$(CONFIG_GPIO_MCP23S08)     += gpio-mcp23s08.o
 obj-$(CONFIG_GPIO_ML_IOH)       += gpio-ml-ioh.o
 obj-$(CONFIG_GPIO_MPC5200)      += gpio-mpc5200.o
@@ -45,6 +46,7 @@ obj-$(CONFIG_GPIO_RDC321X)	+= gpio-rdc321x.o
 obj-$(CONFIG_PLAT_SAMSUNG)      += gpio-samsung.o
 obj-$(CONFIG_ARCH_SA1100)       += gpio-sa1100.o
 obj-$(CONFIG_GPIO_SCH)          += gpio-sch.o
+obj-$(CONFIG_GPIO_SODAVILLE)    += gpio-sodaville.o
 obj-$(CONFIG_GPIO_STMPE)        += gpio-stmpe.o
 obj-$(CONFIG_GPIO_SX150X)       += gpio-sx150x.o
 obj-$(CONFIG_GPIO_TC3589X)      += gpio-tc3589x.o
diff --git a/drivers/gpio/gpio-mc9s08dz60.c b/drivers/gpio/gpio-mc9s08dz60.c
new file mode 100644
index 000000000000..2738cc44d636
--- /dev/null
+++ b/drivers/gpio/gpio-mc9s08dz60.c
@@ -0,0 +1,161 @@
+/*
+ * Copyright 2009-2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * Author: Wu Guoxing <b39297@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/i2c.h>
+#include <linux/gpio.h>
+
+#define GPIO_GROUP_NUM 2
+#define GPIO_NUM_PER_GROUP 8
+#define GPIO_NUM (GPIO_GROUP_NUM*GPIO_NUM_PER_GROUP)
+
+struct mc9s08dz60 {
+        struct i2c_client *client;
+        struct gpio_chip chip;
+};
+
+static inline struct mc9s08dz60 *to_mc9s08dz60(struct gpio_chip *gc)
+{
+        return container_of(gc, struct mc9s08dz60, chip);
+}
+
+
+static void mc9s_gpio_to_reg_and_bit(int offset, u8 *reg, u8 *bit)
+{
+        *reg = 0x20 + offset / GPIO_NUM_PER_GROUP;
+        *bit = offset % GPIO_NUM_PER_GROUP;
+}
+
+static int mc9s08dz60_get_value(struct gpio_chip *gc, unsigned offset)
+{
+        u8 reg, bit;
+        s32 value;
+        struct mc9s08dz60 *mc9s = to_mc9s08dz60(gc);
+
+        mc9s_gpio_to_reg_and_bit(offset, &reg, &bit);
+        value = i2c_smbus_read_byte_data(mc9s->client, reg);
+
+        return (value >= 0) ? (value >> bit) & 0x1 : 0;
+}
+
+static int mc9s08dz60_set(struct mc9s08dz60 *mc9s, unsigned offset, int val)
+{
+        u8 reg, bit;
+        s32 value;
+
+        mc9s_gpio_to_reg_and_bit(offset, &reg, &bit);
+        value = i2c_smbus_read_byte_data(mc9s->client, reg);
+        if (value >= 0) {
+                if (val)
+                        value |= 1 << bit;
+                else
+                        value &= ~(1 << bit);
+
+                return i2c_smbus_write_byte_data(mc9s->client, reg, value);
+        } else
+                return value;
+
+}
+
+
+static void mc9s08dz60_set_value(struct gpio_chip *gc, unsigned offset, int val)
+{
+        struct mc9s08dz60 *mc9s = to_mc9s08dz60(gc);
+
+        mc9s08dz60_set(mc9s, offset, val);
+}
+
+static int mc9s08dz60_direction_output(struct gpio_chip *gc,
+                                       unsigned offset, int val)
+{
+        struct mc9s08dz60 *mc9s = to_mc9s08dz60(gc);
+
+        return mc9s08dz60_set(mc9s, offset, val);
+}
+
+static int mc9s08dz60_probe(struct i2c_client *client,
+                            const struct i2c_device_id *id)
+{
+        int ret = 0;
+        struct mc9s08dz60 *mc9s;
+
+        mc9s = kzalloc(sizeof(*mc9s), GFP_KERNEL);
+        if (!mc9s)
+                return -ENOMEM;
+
+        mc9s->chip.label = client->name;
+        mc9s->chip.base = -1;
+        mc9s->chip.dev = &client->dev;
+        mc9s->chip.owner = THIS_MODULE;
+        mc9s->chip.ngpio = GPIO_NUM;
+        mc9s->chip.can_sleep = 1;
+        mc9s->chip.get = mc9s08dz60_get_value;
+        mc9s->chip.set = mc9s08dz60_set_value;
+        mc9s->chip.direction_output = mc9s08dz60_direction_output;
+        mc9s->client = client;
+        i2c_set_clientdata(client, mc9s);
+
+        ret = gpiochip_add(&mc9s->chip);
+        if (ret)
+                goto error;
+
+        return 0;
+
+ error:
+        kfree(mc9s);
+        return ret;
+}
+
+static int mc9s08dz60_remove(struct i2c_client *client)
+{
+        struct mc9s08dz60 *mc9s;
+        int ret;
+
+        mc9s = i2c_get_clientdata(client);
+
+        ret = gpiochip_remove(&mc9s->chip);
+        if (!ret)
+                kfree(mc9s);
+
+        return ret;
+
+}
+
+static const struct i2c_device_id mc9s08dz60_id[] = {
+        {"mc9s08dz60", 0},
+        {},
+};
+
+MODULE_DEVICE_TABLE(i2c, mc9s08dz60_id);
+
+static struct i2c_driver mc9s08dz60_i2c_driver = {
+        .driver = {
+                .owner = THIS_MODULE,
+                .name = "mc9s08dz60",
+        },
+        .probe = mc9s08dz60_probe,
+        .remove = mc9s08dz60_remove,
+        .id_table = mc9s08dz60_id,
+};
+
+module_i2c_driver(mc9s08dz60_i2c_driver);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc. "
+                "Wu Guoxing <b39297@freescale.com>");
+MODULE_DESCRIPTION("mc9s08dz60 gpio function on mx35 3ds board");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpio/gpio-pl061.c b/drivers/gpio/gpio-pl061.c
index 77c9cc70fa77..b4b5da4fd2cc 100644
--- a/drivers/gpio/gpio-pl061.c
+++ b/drivers/gpio/gpio-pl061.c
@@ -352,7 +352,12 @@ static int pl061_resume(struct device *dev)
         return 0;
 }
 
-static SIMPLE_DEV_PM_OPS(pl061_dev_pm_ops, pl061_suspend, pl061_resume);
+static const struct dev_pm_ops pl061_dev_pm_ops = {
+        .suspend = pl061_suspend,
+        .resume = pl061_resume,
+        .freeze = pl061_suspend,
+        .restore = pl061_resume,
+};
 #endif
 
 static struct amba_id pl061_ids[] = {
diff --git a/drivers/gpio/gpio-sodaville.c b/drivers/gpio/gpio-sodaville.c
new file mode 100644
index 000000000000..9ba15d31d242
--- /dev/null
+++ b/drivers/gpio/gpio-sodaville.c
@@ -0,0 +1,302 @@
+/*
+ *  GPIO interface for Intel Sodaville SoCs.
+ *
+ *  Copyright (c) 2010, 2011 Intel Corporation
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License 2 as published
+ *  by the Free Software Foundation.
+ *
+ */
+
+#include <linux/errno.h>
+#include <linux/gpio.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/platform_device.h>
+#include <linux/of_irq.h>
+#include <linux/basic_mmio_gpio.h>
+
+#define DRV_NAME                "sdv_gpio"
+#define SDV_NUM_PUB_GPIOS       12
+#define PCI_DEVICE_ID_SDV_GPIO  0x2e67
+#define GPIO_BAR                0
+
+#define GPOUTR          0x00
+#define GPOER           0x04
+#define GPINR           0x08
+
+#define GPSTR           0x0c
+#define GPIT1R0         0x10
+#define GPIO_INT        0x14
+#define GPIT1R1         0x18
+
+#define GPMUXCTL        0x1c
+
+struct sdv_gpio_chip_data {
+        int irq_base;
+        void __iomem *gpio_pub_base;
+        struct irq_domain id;
+        struct irq_chip_generic *gc;
+        struct bgpio_chip bgpio;
+};
+
+static int sdv_gpio_pub_set_type(struct irq_data *d, unsigned int type)
+{
+        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+        struct sdv_gpio_chip_data *sd = gc->private;
+        void __iomem *type_reg;
+        u32 irq_offs = d->irq - sd->irq_base;
+        u32 reg;
+
+        if (irq_offs < 8)
+                type_reg = sd->gpio_pub_base + GPIT1R0;
+        else
+                type_reg = sd->gpio_pub_base + GPIT1R1;
+
+        reg = readl(type_reg);
+
+        switch (type) {
+        case IRQ_TYPE_LEVEL_HIGH:
+                reg &= ~BIT(4 * (irq_offs % 8));
+                break;
+
+        case IRQ_TYPE_LEVEL_LOW:
+                reg |= BIT(4 * (irq_offs % 8));
+                break;
+
+        default:
+                return -EINVAL;
+        }
+
+        writel(reg, type_reg);
+        return 0;
+}
+
+static irqreturn_t sdv_gpio_pub_irq_handler(int irq, void *data)
+{
+        struct sdv_gpio_chip_data *sd = data;
+        u32 irq_stat = readl(sd->gpio_pub_base + GPSTR);
+
+        irq_stat &= readl(sd->gpio_pub_base + GPIO_INT);
+        if (!irq_stat)
+                return IRQ_NONE;
+
+        while (irq_stat) {
+                u32 irq_bit = __fls(irq_stat);
+
+                irq_stat &= ~BIT(irq_bit);
+                generic_handle_irq(sd->irq_base + irq_bit);
+        }
+
+        return IRQ_HANDLED;
+}
+
+static int sdv_xlate(struct irq_domain *h, struct device_node *node,
+                const u32 *intspec, u32 intsize, irq_hw_number_t *out_hwirq,
+                u32 *out_type)
+{
+        u32 line, type;
+
+        if (node != h->of_node)
+                return -EINVAL;
+
+        if (intsize < 2)
+                return -EINVAL;
+
+        line = *intspec;
+        *out_hwirq = line;
+
+        intspec++;
+        type = *intspec;
+
+        switch (type) {
+        case IRQ_TYPE_LEVEL_LOW:
+        case IRQ_TYPE_LEVEL_HIGH:
+                *out_type = type;
+                break;
+        default:
+                return -EINVAL;
+        }
+        return 0;
+}
+
+static struct irq_domain_ops irq_domain_sdv_ops = {
+        .dt_translate   = sdv_xlate,
+};
+
+static __devinit int sdv_register_irqsupport(struct sdv_gpio_chip_data *sd,
+                struct pci_dev *pdev)
+{
+        struct irq_chip_type *ct;
+        int ret;
+
+        sd->irq_base = irq_alloc_descs(-1, 0, SDV_NUM_PUB_GPIOS, -1);
+        if (sd->irq_base < 0)
+                return sd->irq_base;
+
+        /* mask + ACK all interrupt sources */
+        writel(0, sd->gpio_pub_base + GPIO_INT);
+        writel((1 << 11) - 1, sd->gpio_pub_base + GPSTR);
+
+        ret = request_irq(pdev->irq, sdv_gpio_pub_irq_handler, IRQF_SHARED,
+                        "sdv_gpio", sd);
+        if (ret)
+                goto out_free_desc;
+
+        sd->id.irq_base = sd->irq_base;
+        sd->id.of_node = of_node_get(pdev->dev.of_node);
+        sd->id.ops = &irq_domain_sdv_ops;
+
+        /*
+         * This gpio irq controller latches level irqs. Testing shows that if
+         * we unmask & ACK the IRQ before the source of the interrupt is gone
+         * then the interrupt is active again.
+         */
+        sd->gc = irq_alloc_generic_chip("sdv-gpio", 1, sd->irq_base,
+                        sd->gpio_pub_base, handle_fasteoi_irq);
+        if (!sd->gc) {
+                ret = -ENOMEM;
+                goto out_free_irq;
+        }
+
+        sd->gc->private = sd;
+        ct = sd->gc->chip_types;
+        ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
+        ct->regs.eoi = GPSTR;
+        ct->regs.mask = GPIO_INT;
+        ct->chip.irq_mask = irq_gc_mask_clr_bit;
+        ct->chip.irq_unmask = irq_gc_mask_set_bit;
+        ct->chip.irq_eoi = irq_gc_eoi;
+        ct->chip.irq_set_type = sdv_gpio_pub_set_type;
+
+        irq_setup_generic_chip(sd->gc, IRQ_MSK(SDV_NUM_PUB_GPIOS),
+                        IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST,
+                        IRQ_LEVEL | IRQ_NOPROBE);
+
+        irq_domain_add(&sd->id);
+        return 0;
+out_free_irq:
+        free_irq(pdev->irq, sd);
+out_free_desc:
+        irq_free_descs(sd->irq_base, SDV_NUM_PUB_GPIOS);
+        return ret;
+}
+
+static int __devinit sdv_gpio_probe(struct pci_dev *pdev,
+                                        const struct pci_device_id *pci_id)
+{
+        struct sdv_gpio_chip_data *sd;
+        unsigned long addr;
+        const void *prop;
+        int len;
+        int ret;
+        u32 mux_val;
+
+        sd = kzalloc(sizeof(struct sdv_gpio_chip_data), GFP_KERNEL);
+        if (!sd)
+                return -ENOMEM;
+        ret = pci_enable_device(pdev);
+        if (ret) {
+                dev_err(&pdev->dev, "can't enable device.\n");
+                goto done;
+        }
+
+        ret = pci_request_region(pdev, GPIO_BAR, DRV_NAME);
+        if (ret) {
+                dev_err(&pdev->dev, "can't alloc PCI BAR #%d\n", GPIO_BAR);
+                goto disable_pci;
+        }
+
+        addr = pci_resource_start(pdev, GPIO_BAR);
+        if (!addr)
+                goto release_reg;
+        sd->gpio_pub_base = ioremap(addr, pci_resource_len(pdev, GPIO_BAR));
+
+        prop = of_get_property(pdev->dev.of_node, "intel,muxctl", &len);
+        if (prop && len == 4) {
+                mux_val = of_read_number(prop, 1);
+                writel(mux_val, sd->gpio_pub_base + GPMUXCTL);
+        }
+
+        ret = bgpio_init(&sd->bgpio, &pdev->dev, 4,
+                        sd->gpio_pub_base + GPINR, sd->gpio_pub_base + GPOUTR,
+                        NULL, sd->gpio_pub_base + GPOER, NULL, false);
+        if (ret)
+                goto unmap;
+        sd->bgpio.gc.ngpio = SDV_NUM_PUB_GPIOS;
+
+        ret = gpiochip_add(&sd->bgpio.gc);
+        if (ret < 0) {
+                dev_err(&pdev->dev, "gpiochip_add() failed.\n");
+                goto unmap;
+        }
+
+        ret = sdv_register_irqsupport(sd, pdev);
+        if (ret)
+                goto unmap;
+
+        pci_set_drvdata(pdev, sd);
+        dev_info(&pdev->dev, "Sodaville GPIO driver registered.\n");
+        return 0;
+
+unmap:
+        iounmap(sd->gpio_pub_base);
+release_reg:
+        pci_release_region(pdev, GPIO_BAR);
+disable_pci:
+        pci_disable_device(pdev);
+done:
+        kfree(sd);
+        return ret;
+}
+
+static void sdv_gpio_remove(struct pci_dev *pdev)
+{
+        struct sdv_gpio_chip_data *sd = pci_get_drvdata(pdev);
+
+        irq_domain_del(&sd->id);
+        free_irq(pdev->irq, sd);
+        irq_free_descs(sd->irq_base, SDV_NUM_PUB_GPIOS);
+
+        if (gpiochip_remove(&sd->bgpio.gc))
+                dev_err(&pdev->dev, "gpiochip_remove() failed.\n");
+
+        pci_release_region(pdev, GPIO_BAR);
+        iounmap(sd->gpio_pub_base);
+        pci_disable_device(pdev);
+        kfree(sd);
+}
+
+static struct pci_device_id sdv_gpio_pci_ids[] __devinitdata = {
+        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_SDV_GPIO) },
+        { 0, },
+};
+
+static struct pci_driver sdv_gpio_driver = {
+        .name = DRV_NAME,
+        .id_table = sdv_gpio_pci_ids,
+        .probe = sdv_gpio_probe,
+        .remove = sdv_gpio_remove,
+};
+
+static int __init sdv_gpio_init(void)
+{
+        return pci_register_driver(&sdv_gpio_driver);
+}
+module_init(sdv_gpio_init);
+
+static void __exit sdv_gpio_exit(void)
+{
+        pci_unregister_driver(&sdv_gpio_driver);
+}
+module_exit(sdv_gpio_exit);
+
+MODULE_AUTHOR("Hans J. Koch <hjk@linutronix.de>");
+MODULE_DESCRIPTION("GPIO interface for Intel Sodaville SoCs");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpio/gpio-tps65910.c b/drivers/gpio/gpio-tps65910.c
index 91f45b965d1e..7eef648a3351 100644
--- a/drivers/gpio/gpio-tps65910.c
+++ b/drivers/gpio/gpio-tps65910.c
@@ -69,6 +69,7 @@ static int tps65910_gpio_input(struct gpio_chip *gc, unsigned offset)
 void tps65910_gpio_init(struct tps65910 *tps65910, int gpio_base)
 {
         int ret;
+        struct tps65910_board *board_data;
 
         if (!gpio_base)
                 return;
@@ -80,10 +81,10 @@ void tps65910_gpio_init(struct tps65910 *tps65910, int gpio_base)
 
         switch(tps65910_chip_id(tps65910)) {
         case TPS65910:
-                tps65910->gpio.ngpio    = 6;
+                tps65910->gpio.ngpio    = TPS65910_NUM_GPIO;
                 break;
         case TPS65911:
-                tps65910->gpio.ngpio    = 9;
+                tps65910->gpio.ngpio    = TPS65911_NUM_GPIO;
                 break;
         default:
                 return;
@@ -95,6 +96,21 @@ void tps65910_gpio_init(struct tps65910 *tps65910, int gpio_base)
         tps65910->gpio.set              = tps65910_gpio_set;
         tps65910->gpio.get              = tps65910_gpio_get;
 
+        /* Configure sleep control for gpios */
+        board_data = dev_get_platdata(tps65910->dev);
+        if (board_data) {
+                int i;
+                for (i = 0; i < tps65910->gpio.ngpio; ++i) {
+                        if (board_data->en_gpio_sleep[i]) {
+                                ret = tps65910_set_bits(tps65910,
+                                        TPS65910_GPIO0 + i, GPIO_SLEEP_MASK);
+                                if (ret < 0)
+                                        dev_warn(tps65910->dev,
+                                                "GPIO Sleep setting failed\n");
+                        }
+                }
+        }
+
         ret = gpiochip_add(&tps65910->gpio);
 
         if (ret)
diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
index 17fdf4b6af93..d77354068b90 100644
--- a/drivers/gpio/gpiolib.c
+++ b/drivers/gpio/gpiolib.c
@@ -873,6 +873,7 @@ void gpio_unexport(unsigned gpio)
 {
         struct gpio_desc        *desc;
         int                     status = 0;
+        struct device           *dev = NULL;
 
         if (!gpio_is_valid(gpio)) {
                 status = -EINVAL;
@@ -884,19 +885,20 @@ void gpio_unexport(unsigned gpio)
         desc = &gpio_desc[gpio];
 
         if (test_bit(FLAG_EXPORT, &desc->flags)) {
-                struct device   *dev = NULL;
 
                 dev = class_find_device(&gpio_class, NULL, desc, match_export);
                 if (dev) {
                         gpio_setup_irq(desc, dev, 0);
                         clear_bit(FLAG_EXPORT, &desc->flags);
-                        put_device(dev);
-                        device_unregister(dev);
                 } else
                         status = -ENODEV;
         }
 
         mutex_unlock(&sysfs_lock);
+        if (dev) {
+                device_unregister(dev);
+                put_device(dev);
+        }
 done:
         if (status)
                 pr_debug("%s: gpio%d status %d\n", __func__, gpio, status);
diff --git a/drivers/of/gpio.c b/drivers/of/gpio.c
index 7e62d15d60f6..e034b38590a8 100644
--- a/drivers/of/gpio.c
+++ b/drivers/of/gpio.c
@@ -78,8 +78,9 @@ err0:
 EXPORT_SYMBOL(of_get_named_gpio_flags);
 
 /**
- * of_gpio_count - Count GPIOs for a device
+ * of_gpio_named_count - Count GPIOs for a device
  * @np:         device node to count GPIOs for
+ * @propname:   property name containing gpio specifier(s)
  *
  * The function returns the count of GPIOs specified for a node.
  *
@@ -93,14 +94,14 @@ EXPORT_SYMBOL(of_get_named_gpio_flags);
  * defines four GPIOs (so this function will return 4), two of which
  * are not specified.
  */
-unsigned int of_gpio_count(struct device_node *np)
+unsigned int of_gpio_named_count(struct device_node *np, const char* propname)
 {
         unsigned int cnt = 0;
 
         do {
                 int ret;
 
-                ret = of_parse_phandle_with_args(np, "gpios", "#gpio-cells",
+                ret = of_parse_phandle_with_args(np, propname, "#gpio-cells",
                                                  cnt, NULL);
                 /* A hole in the gpios = <> counts anyway. */
                 if (ret < 0 && ret != -EEXIST)
@@ -109,7 +110,7 @@ unsigned int of_gpio_count(struct device_node *np)
 
         return cnt;
 }
-EXPORT_SYMBOL(of_gpio_count);
+EXPORT_SYMBOL(of_gpio_named_count);
 
 /**
  * of_gpio_simple_xlate - translate gpio_spec to the GPIO number and flags
diff --git a/include/linux/mfd/tps65910.h b/include/linux/mfd/tps65910.h
index d0cb12eba402..9071902bd222 100644
--- a/include/linux/mfd/tps65910.h
+++ b/include/linux/mfd/tps65910.h
@@ -657,6 +657,8 @@
 
 
 /*Register GPIO  (0x80) register.RegisterDescription */
+#define GPIO_SLEEP_MASK                         0x80
+#define GPIO_SLEEP_SHIFT                        7
 #define GPIO_DEB_MASK                           0x10
 #define GPIO_DEB_SHIFT                          4
 #define GPIO_PUEN_MASK                          0x08
@@ -740,6 +742,11 @@
 #define TPS65910_GPIO_STS                               BIT(1)
 #define TPS65910_GPIO_SET                               BIT(0)
 
+/* Max number of TPS65910/11 GPIOs */
+#define TPS65910_NUM_GPIO                               6
+#define TPS65911_NUM_GPIO                               9
+#define TPS6591X_MAX_NUM_GPIO                           9
+
 /* Regulator Index Definitions */
 #define TPS65910_REG_VRTC                               0
 #define TPS65910_REG_VIO                                1
@@ -779,6 +786,7 @@ struct tps65910_board {
         int irq_base;
         int vmbch_threshold;
         int vmbch2_threshold;
+        bool en_gpio_sleep[TPS6591X_MAX_NUM_GPIO];
         struct regulator_init_data *tps65910_pmic_init_data[TPS65910_NUM_REGS];
 };
 
diff --git a/include/linux/of_gpio.h b/include/linux/of_gpio.h
index b254052a49d7..81733d12cbea 100644
--- a/include/linux/of_gpio.h
+++ b/include/linux/of_gpio.h
@@ -50,7 +50,8 @@ static inline struct of_mm_gpio_chip *to_of_mm_gpio_chip(struct gpio_chip *gc)
 extern int of_get_named_gpio_flags(struct device_node *np,
                 const char *list_name, int index, enum of_gpio_flags *flags);
 
-extern unsigned int of_gpio_count(struct device_node *np);
+extern unsigned int of_gpio_named_count(struct device_node *np,
+                                        const char* propname);
 
 extern int of_mm_gpiochip_add(struct device_node *np,
                               struct of_mm_gpio_chip *mm_gc);
@@ -71,7 +72,8 @@ static inline int of_get_named_gpio_flags(struct device_node *np,
         return -ENOSYS;
 }
 
-static inline unsigned int of_gpio_count(struct device_node *np)
+static inline unsigned int of_gpio_named_count(struct device_node *np,
+                                        const char* propname)
 {
         return 0;
 }
@@ -89,6 +91,27 @@ static inline void of_gpiochip_remove(struct gpio_chip *gc) { }
 #endif /* CONFIG_OF_GPIO */
 
 /**
+ * of_gpio_count - Count GPIOs for a device
+ * @np:         device node to count GPIOs for
+ *
+ * The function returns the count of GPIOs specified for a node.
+ *
+ * Note that the empty GPIO specifiers counts too. For example,
+ *
+ * gpios = <0
+ *          &pio1 1 2
+ *          0
+ *          &pio2 3 4>;
+ *
+ * defines four GPIOs (so this function will return 4), two of which
+ * are not specified.
+ */
+static inline unsigned int of_gpio_count(struct device_node *np)
+{
+        return of_gpio_named_count(np, "gpios");
+}
+
+/**
  * of_get_gpio_flags() - Get a GPIO number and flags to use with GPIO API
  * @np:         device node to get GPIO from
  * @index:      index of the GPIO