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-rw-r--r--arch/arm/boot/dts/versatile-pb.dts37
1 files changed, 37 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/versatile-pb.dts b/arch/arm/boot/dts/versatile-pb.dts
index e36c1e82fea7..b83137f66034 100644
--- a/arch/arm/boot/dts/versatile-pb.dts
+++ b/arch/arm/boot/dts/versatile-pb.dts
@@ -29,6 +29,43 @@
29 clock-names = "apb_pclk"; 29 clock-names = "apb_pclk";
30 }; 30 };
31 31
32 pci-controller@10001000 {
33 compatible = "arm,versatile-pci";
34 device_type = "pci";
35 reg = <0x10001000 0x1000
36 0x41000000 0x10000
37 0x42000000 0x100000>;
38 bus-range = <0 0xff>;
39 #address-cells = <3>;
40 #size-cells = <2>;
41 #interrupt-cells = <1>;
42
43 ranges = <0x01000000 0 0x00000000 0x43000000 0 0x00010000 /* downstream I/O */
44 0x02000000 0 0x50000000 0x50000000 0 0x10000000 /* non-prefetchable memory */
45 0x42000000 0 0x60000000 0x60000000 0 0x10000000>; /* prefetchable memory */
46
47 interrupt-map-mask = <0x1800 0 0 7>;
48 interrupt-map = <0x1800 0 0 1 &sic 28
49 0x1800 0 0 2 &sic 29
50 0x1800 0 0 3 &sic 30
51 0x1800 0 0 4 &sic 27
52
53 0x1000 0 0 1 &sic 27
54 0x1000 0 0 2 &sic 28
55 0x1000 0 0 3 &sic 29
56 0x1000 0 0 4 &sic 30
57
58 0x0800 0 0 1 &sic 30
59 0x0800 0 0 2 &sic 27
60 0x0800 0 0 3 &sic 28
61 0x0800 0 0 4 &sic 29
62
63 0x0000 0 0 1 &sic 29
64 0x0000 0 0 2 &sic 30
65 0x0000 0 0 3 &sic 27
66 0x0000 0 0 4 &sic 28>;
67 };
68
32 fpga { 69 fpga {
33 uart@9000 { 70 uart@9000 {
34 compatible = "arm,pl011", "arm,primecell"; 71 compatible = "arm,pl011", "arm,primecell";