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-rw-r--r--arch/arm/boot/dts/sun4i-a10.dtsi72
-rw-r--r--arch/arm/boot/dts/sun5i-a10s.dtsi54
-rw-r--r--arch/arm/boot/dts/sun5i-a13.dtsi44
-rw-r--r--arch/arm/boot/dts/sun6i-a31.dtsi72
-rw-r--r--arch/arm/boot/dts/sun7i-a20.dtsi72
-rw-r--r--arch/arm/boot/dts/sun8i-a23.dtsi54
6 files changed, 265 insertions, 103 deletions
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 7b4099fcf817..bb6b6ae95d82 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -226,35 +226,43 @@
226 }; 226 };
227 227
228 mmc0_clk: clk@01c20088 { 228 mmc0_clk: clk@01c20088 {
229 #clock-cells = <0>; 229 #clock-cells = <1>;
230 compatible = "allwinner,sun4i-a10-mod0-clk"; 230 compatible = "allwinner,sun4i-a10-mmc-clk";
231 reg = <0x01c20088 0x4>; 231 reg = <0x01c20088 0x4>;
232 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 232 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
233 clock-output-names = "mmc0"; 233 clock-output-names = "mmc0",
234 "mmc0_output",
235 "mmc0_sample";
234 }; 236 };
235 237
236 mmc1_clk: clk@01c2008c { 238 mmc1_clk: clk@01c2008c {
237 #clock-cells = <0>; 239 #clock-cells = <1>;
238 compatible = "allwinner,sun4i-a10-mod0-clk"; 240 compatible = "allwinner,sun4i-a10-mmc-clk";
239 reg = <0x01c2008c 0x4>; 241 reg = <0x01c2008c 0x4>;
240 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 242 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
241 clock-output-names = "mmc1"; 243 clock-output-names = "mmc1",
244 "mmc1_output",
245 "mmc1_sample";
242 }; 246 };
243 247
244 mmc2_clk: clk@01c20090 { 248 mmc2_clk: clk@01c20090 {
245 #clock-cells = <0>; 249 #clock-cells = <1>;
246 compatible = "allwinner,sun4i-a10-mod0-clk"; 250 compatible = "allwinner,sun4i-a10-mmc-clk";
247 reg = <0x01c20090 0x4>; 251 reg = <0x01c20090 0x4>;
248 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 252 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
249 clock-output-names = "mmc2"; 253 clock-output-names = "mmc2",
254 "mmc2_output",
255 "mmc2_sample";
250 }; 256 };
251 257
252 mmc3_clk: clk@01c20094 { 258 mmc3_clk: clk@01c20094 {
253 #clock-cells = <0>; 259 #clock-cells = <1>;
254 compatible = "allwinner,sun4i-a10-mod0-clk"; 260 compatible = "allwinner,sun4i-a10-mmc-clk";
255 reg = <0x01c20094 0x4>; 261 reg = <0x01c20094 0x4>;
256 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 262 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
257 clock-output-names = "mmc3"; 263 clock-output-names = "mmc3",
264 "mmc3_output",
265 "mmc3_sample";
258 }; 266 };
259 267
260 ts_clk: clk@01c20098 { 268 ts_clk: clk@01c20098 {
@@ -398,8 +406,14 @@
398 mmc0: mmc@01c0f000 { 406 mmc0: mmc@01c0f000 {
399 compatible = "allwinner,sun4i-a10-mmc"; 407 compatible = "allwinner,sun4i-a10-mmc";
400 reg = <0x01c0f000 0x1000>; 408 reg = <0x01c0f000 0x1000>;
401 clocks = <&ahb_gates 8>, <&mmc0_clk>; 409 clocks = <&ahb_gates 8>,
402 clock-names = "ahb", "mmc"; 410 <&mmc0_clk 0>,
411 <&mmc0_clk 1>,
412 <&mmc0_clk 2>;
413 clock-names = "ahb",
414 "mmc",
415 "output",
416 "sample";
403 interrupts = <32>; 417 interrupts = <32>;
404 status = "disabled"; 418 status = "disabled";
405 }; 419 };
@@ -407,8 +421,14 @@
407 mmc1: mmc@01c10000 { 421 mmc1: mmc@01c10000 {
408 compatible = "allwinner,sun4i-a10-mmc"; 422 compatible = "allwinner,sun4i-a10-mmc";
409 reg = <0x01c10000 0x1000>; 423 reg = <0x01c10000 0x1000>;
410 clocks = <&ahb_gates 9>, <&mmc1_clk>; 424 clocks = <&ahb_gates 9>,
411 clock-names = "ahb", "mmc"; 425 <&mmc1_clk 0>,
426 <&mmc1_clk 1>,
427 <&mmc1_clk 2>;
428 clock-names = "ahb",
429 "mmc",
430 "output",
431 "sample";
412 interrupts = <33>; 432 interrupts = <33>;
413 status = "disabled"; 433 status = "disabled";
414 }; 434 };
@@ -416,8 +436,14 @@
416 mmc2: mmc@01c11000 { 436 mmc2: mmc@01c11000 {
417 compatible = "allwinner,sun4i-a10-mmc"; 437 compatible = "allwinner,sun4i-a10-mmc";
418 reg = <0x01c11000 0x1000>; 438 reg = <0x01c11000 0x1000>;
419 clocks = <&ahb_gates 10>, <&mmc2_clk>; 439 clocks = <&ahb_gates 10>,
420 clock-names = "ahb", "mmc"; 440 <&mmc2_clk 0>,
441 <&mmc2_clk 1>,
442 <&mmc2_clk 2>;
443 clock-names = "ahb",
444 "mmc",
445 "output",
446 "sample";
421 interrupts = <34>; 447 interrupts = <34>;
422 status = "disabled"; 448 status = "disabled";
423 }; 449 };
@@ -425,8 +451,14 @@
425 mmc3: mmc@01c12000 { 451 mmc3: mmc@01c12000 {
426 compatible = "allwinner,sun4i-a10-mmc"; 452 compatible = "allwinner,sun4i-a10-mmc";
427 reg = <0x01c12000 0x1000>; 453 reg = <0x01c12000 0x1000>;
428 clocks = <&ahb_gates 11>, <&mmc3_clk>; 454 clocks = <&ahb_gates 11>,
429 clock-names = "ahb", "mmc"; 455 <&mmc3_clk 0>,
456 <&mmc3_clk 1>,
457 <&mmc3_clk 2>;
458 clock-names = "ahb",
459 "mmc",
460 "output",
461 "sample";
430 interrupts = <35>; 462 interrupts = <35>;
431 status = "disabled"; 463 status = "disabled";
432 }; 464 };
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index 1b76667f3182..0e011427615f 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -211,27 +211,33 @@
211 }; 211 };
212 212
213 mmc0_clk: clk@01c20088 { 213 mmc0_clk: clk@01c20088 {
214 #clock-cells = <0>; 214 #clock-cells = <1>;
215 compatible = "allwinner,sun4i-a10-mod0-clk"; 215 compatible = "allwinner,sun4i-a10-mmc-clk";
216 reg = <0x01c20088 0x4>; 216 reg = <0x01c20088 0x4>;
217 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 217 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
218 clock-output-names = "mmc0"; 218 clock-output-names = "mmc0",
219 "mmc0_output",
220 "mmc0_sample";
219 }; 221 };
220 222
221 mmc1_clk: clk@01c2008c { 223 mmc1_clk: clk@01c2008c {
222 #clock-cells = <0>; 224 #clock-cells = <1>;
223 compatible = "allwinner,sun4i-a10-mod0-clk"; 225 compatible = "allwinner,sun4i-a10-mmc-clk";
224 reg = <0x01c2008c 0x4>; 226 reg = <0x01c2008c 0x4>;
225 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 227 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
226 clock-output-names = "mmc1"; 228 clock-output-names = "mmc1",
229 "mmc1_output",
230 "mmc1_sample";
227 }; 231 };
228 232
229 mmc2_clk: clk@01c20090 { 233 mmc2_clk: clk@01c20090 {
230 #clock-cells = <0>; 234 #clock-cells = <1>;
231 compatible = "allwinner,sun4i-a10-mod0-clk"; 235 compatible = "allwinner,sun4i-a10-mmc-clk";
232 reg = <0x01c20090 0x4>; 236 reg = <0x01c20090 0x4>;
233 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 237 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
234 clock-output-names = "mmc2"; 238 clock-output-names = "mmc2",
239 "mmc2_output",
240 "mmc2_sample";
235 }; 241 };
236 242
237 ts_clk: clk@01c20098 { 243 ts_clk: clk@01c20098 {
@@ -359,8 +365,14 @@
359 mmc0: mmc@01c0f000 { 365 mmc0: mmc@01c0f000 {
360 compatible = "allwinner,sun5i-a13-mmc"; 366 compatible = "allwinner,sun5i-a13-mmc";
361 reg = <0x01c0f000 0x1000>; 367 reg = <0x01c0f000 0x1000>;
362 clocks = <&ahb_gates 8>, <&mmc0_clk>; 368 clocks = <&ahb_gates 8>,
363 clock-names = "ahb", "mmc"; 369 <&mmc0_clk 0>,
370 <&mmc0_clk 1>,
371 <&mmc0_clk 2>;
372 clock-names = "ahb",
373 "mmc",
374 "output",
375 "sample";
364 interrupts = <32>; 376 interrupts = <32>;
365 status = "disabled"; 377 status = "disabled";
366 }; 378 };
@@ -368,8 +380,14 @@
368 mmc1: mmc@01c10000 { 380 mmc1: mmc@01c10000 {
369 compatible = "allwinner,sun5i-a13-mmc"; 381 compatible = "allwinner,sun5i-a13-mmc";
370 reg = <0x01c10000 0x1000>; 382 reg = <0x01c10000 0x1000>;
371 clocks = <&ahb_gates 9>, <&mmc1_clk>; 383 clocks = <&ahb_gates 9>,
372 clock-names = "ahb", "mmc"; 384 <&mmc1_clk 0>,
385 <&mmc1_clk 1>,
386 <&mmc1_clk 2>;
387 clock-names = "ahb",
388 "mmc",
389 "output",
390 "sample";
373 interrupts = <33>; 391 interrupts = <33>;
374 status = "disabled"; 392 status = "disabled";
375 }; 393 };
@@ -377,8 +395,14 @@
377 mmc2: mmc@01c11000 { 395 mmc2: mmc@01c11000 {
378 compatible = "allwinner,sun5i-a13-mmc"; 396 compatible = "allwinner,sun5i-a13-mmc";
379 reg = <0x01c11000 0x1000>; 397 reg = <0x01c11000 0x1000>;
380 clocks = <&ahb_gates 10>, <&mmc2_clk>; 398 clocks = <&ahb_gates 10>,
381 clock-names = "ahb", "mmc"; 399 <&mmc2_clk 0>,
400 <&mmc2_clk 1>,
401 <&mmc2_clk 2>;
402 clock-names = "ahb",
403 "mmc",
404 "output",
405 "sample";
382 interrupts = <34>; 406 interrupts = <34>;
383 status = "disabled"; 407 status = "disabled";
384 }; 408 };
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index c35217ea1f64..cbb63b750e08 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -195,27 +195,33 @@
195 }; 195 };
196 196
197 mmc0_clk: clk@01c20088 { 197 mmc0_clk: clk@01c20088 {
198 #clock-cells = <0>; 198 #clock-cells = <1>;
199 compatible = "allwinner,sun4i-a10-mod0-clk"; 199 compatible = "allwinner,sun4i-a10-mmc-clk";
200 reg = <0x01c20088 0x4>; 200 reg = <0x01c20088 0x4>;
201 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 201 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
202 clock-output-names = "mmc0"; 202 clock-output-names = "mmc0",
203 "mmc0_output",
204 "mmc0_sample";
203 }; 205 };
204 206
205 mmc1_clk: clk@01c2008c { 207 mmc1_clk: clk@01c2008c {
206 #clock-cells = <0>; 208 #clock-cells = <1>;
207 compatible = "allwinner,sun4i-a10-mod0-clk"; 209 compatible = "allwinner,sun4i-a10-mmc-clk";
208 reg = <0x01c2008c 0x4>; 210 reg = <0x01c2008c 0x4>;
209 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 211 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
210 clock-output-names = "mmc1"; 212 clock-output-names = "mmc1",
213 "mmc1_output",
214 "mmc1_sample";
211 }; 215 };
212 216
213 mmc2_clk: clk@01c20090 { 217 mmc2_clk: clk@01c20090 {
214 #clock-cells = <0>; 218 #clock-cells = <1>;
215 compatible = "allwinner,sun4i-a10-mod0-clk"; 219 compatible = "allwinner,sun4i-a10-mmc-clk";
216 reg = <0x01c20090 0x4>; 220 reg = <0x01c20090 0x4>;
217 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 221 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
218 clock-output-names = "mmc2"; 222 clock-output-names = "mmc2",
223 "mmc2_output",
224 "mmc2_sample";
219 }; 225 };
220 226
221 ts_clk: clk@01c20098 { 227 ts_clk: clk@01c20098 {
@@ -327,8 +333,14 @@
327 mmc0: mmc@01c0f000 { 333 mmc0: mmc@01c0f000 {
328 compatible = "allwinner,sun5i-a13-mmc"; 334 compatible = "allwinner,sun5i-a13-mmc";
329 reg = <0x01c0f000 0x1000>; 335 reg = <0x01c0f000 0x1000>;
330 clocks = <&ahb_gates 8>, <&mmc0_clk>; 336 clocks = <&ahb_gates 8>,
331 clock-names = "ahb", "mmc"; 337 <&mmc0_clk 0>,
338 <&mmc0_clk 1>,
339 <&mmc0_clk 2>;
340 clock-names = "ahb",
341 "mmc",
342 "output",
343 "sample";
332 interrupts = <32>; 344 interrupts = <32>;
333 status = "disabled"; 345 status = "disabled";
334 }; 346 };
@@ -336,8 +348,14 @@
336 mmc2: mmc@01c11000 { 348 mmc2: mmc@01c11000 {
337 compatible = "allwinner,sun5i-a13-mmc"; 349 compatible = "allwinner,sun5i-a13-mmc";
338 reg = <0x01c11000 0x1000>; 350 reg = <0x01c11000 0x1000>;
339 clocks = <&ahb_gates 10>, <&mmc2_clk>; 351 clocks = <&ahb_gates 10>,
340 clock-names = "ahb", "mmc"; 352 <&mmc2_clk 0>,
353 <&mmc2_clk 1>,
354 <&mmc2_clk 2>;
355 clock-names = "ahb",
356 "mmc",
357 "output",
358 "sample";
341 interrupts = <34>; 359 interrupts = <34>;
342 status = "disabled"; 360 status = "disabled";
343 }; 361 };
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 62d932e9b7d1..3e7db5191516 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -241,35 +241,43 @@
241 }; 241 };
242 242
243 mmc0_clk: clk@01c20088 { 243 mmc0_clk: clk@01c20088 {
244 #clock-cells = <0>; 244 #clock-cells = <1>;
245 compatible = "allwinner,sun4i-a10-mod0-clk"; 245 compatible = "allwinner,sun4i-a10-mmc-clk";
246 reg = <0x01c20088 0x4>; 246 reg = <0x01c20088 0x4>;
247 clocks = <&osc24M>, <&pll6 0>; 247 clocks = <&osc24M>, <&pll6 0>;
248 clock-output-names = "mmc0"; 248 clock-output-names = "mmc0",
249 "mmc0_output",
250 "mmc0_sample";
249 }; 251 };
250 252
251 mmc1_clk: clk@01c2008c { 253 mmc1_clk: clk@01c2008c {
252 #clock-cells = <0>; 254 #clock-cells = <1>;
253 compatible = "allwinner,sun4i-a10-mod0-clk"; 255 compatible = "allwinner,sun4i-a10-mmc-clk";
254 reg = <0x01c2008c 0x4>; 256 reg = <0x01c2008c 0x4>;
255 clocks = <&osc24M>, <&pll6 0>; 257 clocks = <&osc24M>, <&pll6 0>;
256 clock-output-names = "mmc1"; 258 clock-output-names = "mmc1",
259 "mmc1_output",
260 "mmc1_sample";
257 }; 261 };
258 262
259 mmc2_clk: clk@01c20090 { 263 mmc2_clk: clk@01c20090 {
260 #clock-cells = <0>; 264 #clock-cells = <1>;
261 compatible = "allwinner,sun4i-a10-mod0-clk"; 265 compatible = "allwinner,sun4i-a10-mmc-clk";
262 reg = <0x01c20090 0x4>; 266 reg = <0x01c20090 0x4>;
263 clocks = <&osc24M>, <&pll6 0>; 267 clocks = <&osc24M>, <&pll6 0>;
264 clock-output-names = "mmc2"; 268 clock-output-names = "mmc2",
269 "mmc2_output",
270 "mmc2_sample";
265 }; 271 };
266 272
267 mmc3_clk: clk@01c20094 { 273 mmc3_clk: clk@01c20094 {
268 #clock-cells = <0>; 274 #clock-cells = <1>;
269 compatible = "allwinner,sun4i-a10-mod0-clk"; 275 compatible = "allwinner,sun4i-a10-mmc-clk";
270 reg = <0x01c20094 0x4>; 276 reg = <0x01c20094 0x4>;
271 clocks = <&osc24M>, <&pll6 0>; 277 clocks = <&osc24M>, <&pll6 0>;
272 clock-output-names = "mmc3"; 278 clock-output-names = "mmc3",
279 "mmc3_output",
280 "mmc3_sample";
273 }; 281 };
274 282
275 spi0_clk: clk@01c200a0 { 283 spi0_clk: clk@01c200a0 {
@@ -366,8 +374,14 @@
366 mmc0: mmc@01c0f000 { 374 mmc0: mmc@01c0f000 {
367 compatible = "allwinner,sun5i-a13-mmc"; 375 compatible = "allwinner,sun5i-a13-mmc";
368 reg = <0x01c0f000 0x1000>; 376 reg = <0x01c0f000 0x1000>;
369 clocks = <&ahb1_gates 8>, <&mmc0_clk>; 377 clocks = <&ahb1_gates 8>,
370 clock-names = "ahb", "mmc"; 378 <&mmc0_clk 0>,
379 <&mmc0_clk 1>,
380 <&mmc0_clk 2>;
381 clock-names = "ahb",
382 "mmc",
383 "output",
384 "sample";
371 resets = <&ahb1_rst 8>; 385 resets = <&ahb1_rst 8>;
372 reset-names = "ahb"; 386 reset-names = "ahb";
373 interrupts = <0 60 4>; 387 interrupts = <0 60 4>;
@@ -377,8 +391,14 @@
377 mmc1: mmc@01c10000 { 391 mmc1: mmc@01c10000 {
378 compatible = "allwinner,sun5i-a13-mmc"; 392 compatible = "allwinner,sun5i-a13-mmc";
379 reg = <0x01c10000 0x1000>; 393 reg = <0x01c10000 0x1000>;
380 clocks = <&ahb1_gates 9>, <&mmc1_clk>; 394 clocks = <&ahb1_gates 9>,
381 clock-names = "ahb", "mmc"; 395 <&mmc1_clk 0>,
396 <&mmc1_clk 1>,
397 <&mmc1_clk 2>;
398 clock-names = "ahb",
399 "mmc",
400 "output",
401 "sample";
382 resets = <&ahb1_rst 9>; 402 resets = <&ahb1_rst 9>;
383 reset-names = "ahb"; 403 reset-names = "ahb";
384 interrupts = <0 61 4>; 404 interrupts = <0 61 4>;
@@ -388,8 +408,14 @@
388 mmc2: mmc@01c11000 { 408 mmc2: mmc@01c11000 {
389 compatible = "allwinner,sun5i-a13-mmc"; 409 compatible = "allwinner,sun5i-a13-mmc";
390 reg = <0x01c11000 0x1000>; 410 reg = <0x01c11000 0x1000>;
391 clocks = <&ahb1_gates 10>, <&mmc2_clk>; 411 clocks = <&ahb1_gates 10>,
392 clock-names = "ahb", "mmc"; 412 <&mmc2_clk 0>,
413 <&mmc2_clk 1>,
414 <&mmc2_clk 2>;
415 clock-names = "ahb",
416 "mmc",
417 "output",
418 "sample";
393 resets = <&ahb1_rst 10>; 419 resets = <&ahb1_rst 10>;
394 reset-names = "ahb"; 420 reset-names = "ahb";
395 interrupts = <0 62 4>; 421 interrupts = <0 62 4>;
@@ -399,8 +425,14 @@
399 mmc3: mmc@01c12000 { 425 mmc3: mmc@01c12000 {
400 compatible = "allwinner,sun5i-a13-mmc"; 426 compatible = "allwinner,sun5i-a13-mmc";
401 reg = <0x01c12000 0x1000>; 427 reg = <0x01c12000 0x1000>;
402 clocks = <&ahb1_gates 11>, <&mmc3_clk>; 428 clocks = <&ahb1_gates 11>,
403 clock-names = "ahb", "mmc"; 429 <&mmc3_clk 0>,
430 <&mmc3_clk 1>,
431 <&mmc3_clk 2>;
432 clock-names = "ahb",
433 "mmc",
434 "output",
435 "sample";
404 resets = <&ahb1_rst 11>; 436 resets = <&ahb1_rst 11>;
405 reset-names = "ahb"; 437 reset-names = "ahb";
406 interrupts = <0 63 4>; 438 interrupts = <0 63 4>;
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index e21ce5992d56..fa51bffcaf1d 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -274,35 +274,43 @@
274 }; 274 };
275 275
276 mmc0_clk: clk@01c20088 { 276 mmc0_clk: clk@01c20088 {
277 #clock-cells = <0>; 277 #clock-cells = <1>;
278 compatible = "allwinner,sun4i-a10-mod0-clk"; 278 compatible = "allwinner,sun4i-a10-mmc-clk";
279 reg = <0x01c20088 0x4>; 279 reg = <0x01c20088 0x4>;
280 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 280 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
281 clock-output-names = "mmc0"; 281 clock-output-names = "mmc0",
282 "mmc0_output",
283 "mmc0_sample";
282 }; 284 };
283 285
284 mmc1_clk: clk@01c2008c { 286 mmc1_clk: clk@01c2008c {
285 #clock-cells = <0>; 287 #clock-cells = <1>;
286 compatible = "allwinner,sun4i-a10-mod0-clk"; 288 compatible = "allwinner,sun4i-a10-mmc-clk";
287 reg = <0x01c2008c 0x4>; 289 reg = <0x01c2008c 0x4>;
288 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 290 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
289 clock-output-names = "mmc1"; 291 clock-output-names = "mmc1",
292 "mmc1_output",
293 "mmc1_sample";
290 }; 294 };
291 295
292 mmc2_clk: clk@01c20090 { 296 mmc2_clk: clk@01c20090 {
293 #clock-cells = <0>; 297 #clock-cells = <1>;
294 compatible = "allwinner,sun4i-a10-mod0-clk"; 298 compatible = "allwinner,sun4i-a10-mmc-clk";
295 reg = <0x01c20090 0x4>; 299 reg = <0x01c20090 0x4>;
296 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 300 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
297 clock-output-names = "mmc2"; 301 clock-output-names = "mmc2",
302 "mmc2_output",
303 "mmc2_sample";
298 }; 304 };
299 305
300 mmc3_clk: clk@01c20094 { 306 mmc3_clk: clk@01c20094 {
301 #clock-cells = <0>; 307 #clock-cells = <1>;
302 compatible = "allwinner,sun4i-a10-mod0-clk"; 308 compatible = "allwinner,sun4i-a10-mmc-clk";
303 reg = <0x01c20094 0x4>; 309 reg = <0x01c20094 0x4>;
304 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; 310 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
305 clock-output-names = "mmc3"; 311 clock-output-names = "mmc3",
312 "mmc3_output",
313 "mmc3_sample";
306 }; 314 };
307 315
308 ts_clk: clk@01c20098 { 316 ts_clk: clk@01c20098 {
@@ -518,8 +526,14 @@
518 mmc0: mmc@01c0f000 { 526 mmc0: mmc@01c0f000 {
519 compatible = "allwinner,sun5i-a13-mmc"; 527 compatible = "allwinner,sun5i-a13-mmc";
520 reg = <0x01c0f000 0x1000>; 528 reg = <0x01c0f000 0x1000>;
521 clocks = <&ahb_gates 8>, <&mmc0_clk>; 529 clocks = <&ahb_gates 8>,
522 clock-names = "ahb", "mmc"; 530 <&mmc0_clk 0>,
531 <&mmc0_clk 1>,
532 <&mmc0_clk 2>;
533 clock-names = "ahb",
534 "mmc",
535 "output",
536 "sample";
523 interrupts = <0 32 4>; 537 interrupts = <0 32 4>;
524 status = "disabled"; 538 status = "disabled";
525 }; 539 };
@@ -527,8 +541,14 @@
527 mmc1: mmc@01c10000 { 541 mmc1: mmc@01c10000 {
528 compatible = "allwinner,sun5i-a13-mmc"; 542 compatible = "allwinner,sun5i-a13-mmc";
529 reg = <0x01c10000 0x1000>; 543 reg = <0x01c10000 0x1000>;
530 clocks = <&ahb_gates 9>, <&mmc1_clk>; 544 clocks = <&ahb_gates 9>,
531 clock-names = "ahb", "mmc"; 545 <&mmc1_clk 0>,
546 <&mmc1_clk 1>,
547 <&mmc1_clk 2>;
548 clock-names = "ahb",
549 "mmc",
550 "output",
551 "sample";
532 interrupts = <0 33 4>; 552 interrupts = <0 33 4>;
533 status = "disabled"; 553 status = "disabled";
534 }; 554 };
@@ -536,8 +556,14 @@
536 mmc2: mmc@01c11000 { 556 mmc2: mmc@01c11000 {
537 compatible = "allwinner,sun5i-a13-mmc"; 557 compatible = "allwinner,sun5i-a13-mmc";
538 reg = <0x01c11000 0x1000>; 558 reg = <0x01c11000 0x1000>;
539 clocks = <&ahb_gates 10>, <&mmc2_clk>; 559 clocks = <&ahb_gates 10>,
540 clock-names = "ahb", "mmc"; 560 <&mmc2_clk 0>,
561 <&mmc2_clk 1>,
562 <&mmc2_clk 2>;
563 clock-names = "ahb",
564 "mmc",
565 "output",
566 "sample";
541 interrupts = <0 34 4>; 567 interrupts = <0 34 4>;
542 status = "disabled"; 568 status = "disabled";
543 }; 569 };
@@ -545,8 +571,14 @@
545 mmc3: mmc@01c12000 { 571 mmc3: mmc@01c12000 {
546 compatible = "allwinner,sun5i-a13-mmc"; 572 compatible = "allwinner,sun5i-a13-mmc";
547 reg = <0x01c12000 0x1000>; 573 reg = <0x01c12000 0x1000>;
548 clocks = <&ahb_gates 11>, <&mmc3_clk>; 574 clocks = <&ahb_gates 11>,
549 clock-names = "ahb", "mmc"; 575 <&mmc3_clk 0>,
576 <&mmc3_clk 1>,
577 <&mmc3_clk 2>;
578 clock-names = "ahb",
579 "mmc",
580 "output",
581 "sample";
550 interrupts = <0 35 4>; 582 interrupts = <0 35 4>;
551 status = "disabled"; 583 status = "disabled";
552 }; 584 };
diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi
index 2fcccf0cbcee..43a0688fffa0 100644
--- a/arch/arm/boot/dts/sun8i-a23.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23.dtsi
@@ -209,27 +209,33 @@
209 }; 209 };
210 210
211 mmc0_clk: clk@01c20088 { 211 mmc0_clk: clk@01c20088 {
212 #clock-cells = <0>; 212 #clock-cells = <1>;
213 compatible = "allwinner,sun4i-a10-mod0-clk"; 213 compatible = "allwinner,sun4i-a10-mmc-clk";
214 reg = <0x01c20088 0x4>; 214 reg = <0x01c20088 0x4>;
215 clocks = <&osc24M>, <&pll6 0>; 215 clocks = <&osc24M>, <&pll6 0>;
216 clock-output-names = "mmc0"; 216 clock-output-names = "mmc0",
217 "mmc0_output",
218 "mmc0_sample";
217 }; 219 };
218 220
219 mmc1_clk: clk@01c2008c { 221 mmc1_clk: clk@01c2008c {
220 #clock-cells = <0>; 222 #clock-cells = <1>;
221 compatible = "allwinner,sun4i-a10-mod0-clk"; 223 compatible = "allwinner,sun4i-a10-mmc-clk";
222 reg = <0x01c2008c 0x4>; 224 reg = <0x01c2008c 0x4>;
223 clocks = <&osc24M>, <&pll6 0>; 225 clocks = <&osc24M>, <&pll6 0>;
224 clock-output-names = "mmc1"; 226 clock-output-names = "mmc1",
227 "mmc1_output",
228 "mmc1_sample";
225 }; 229 };
226 230
227 mmc2_clk: clk@01c20090 { 231 mmc2_clk: clk@01c20090 {
228 #clock-cells = <0>; 232 #clock-cells = <1>;
229 compatible = "allwinner,sun4i-a10-mod0-clk"; 233 compatible = "allwinner,sun4i-a10-mmc-clk";
230 reg = <0x01c20090 0x4>; 234 reg = <0x01c20090 0x4>;
231 clocks = <&osc24M>, <&pll6 0>; 235 clocks = <&osc24M>, <&pll6 0>;
232 clock-output-names = "mmc2"; 236 clock-output-names = "mmc2",
237 "mmc2_output",
238 "mmc2_sample";
233 }; 239 };
234 240
235 mbus_clk: clk@01c2015c { 241 mbus_clk: clk@01c2015c {
@@ -259,8 +265,14 @@
259 mmc0: mmc@01c0f000 { 265 mmc0: mmc@01c0f000 {
260 compatible = "allwinner,sun5i-a13-mmc"; 266 compatible = "allwinner,sun5i-a13-mmc";
261 reg = <0x01c0f000 0x1000>; 267 reg = <0x01c0f000 0x1000>;
262 clocks = <&ahb1_gates 8>, <&mmc0_clk>; 268 clocks = <&ahb1_gates 8>,
263 clock-names = "ahb", "mmc"; 269 <&mmc0_clk 0>,
270 <&mmc0_clk 1>,
271 <&mmc0_clk 2>;
272 clock-names = "ahb",
273 "mmc",
274 "output",
275 "sample";
264 resets = <&ahb1_rst 8>; 276 resets = <&ahb1_rst 8>;
265 reset-names = "ahb"; 277 reset-names = "ahb";
266 interrupts = <0 60 4>; 278 interrupts = <0 60 4>;
@@ -270,8 +282,14 @@
270 mmc1: mmc@01c10000 { 282 mmc1: mmc@01c10000 {
271 compatible = "allwinner,sun5i-a13-mmc"; 283 compatible = "allwinner,sun5i-a13-mmc";
272 reg = <0x01c10000 0x1000>; 284 reg = <0x01c10000 0x1000>;
273 clocks = <&ahb1_gates 9>, <&mmc1_clk>; 285 clocks = <&ahb1_gates 9>,
274 clock-names = "ahb", "mmc"; 286 <&mmc1_clk 0>,
287 <&mmc1_clk 1>,
288 <&mmc1_clk 2>;
289 clock-names = "ahb",
290 "mmc",
291 "output",
292 "sample";
275 resets = <&ahb1_rst 9>; 293 resets = <&ahb1_rst 9>;
276 reset-names = "ahb"; 294 reset-names = "ahb";
277 interrupts = <0 61 4>; 295 interrupts = <0 61 4>;
@@ -281,8 +299,14 @@
281 mmc2: mmc@01c11000 { 299 mmc2: mmc@01c11000 {
282 compatible = "allwinner,sun5i-a13-mmc"; 300 compatible = "allwinner,sun5i-a13-mmc";
283 reg = <0x01c11000 0x1000>; 301 reg = <0x01c11000 0x1000>;
284 clocks = <&ahb1_gates 10>, <&mmc2_clk>; 302 clocks = <&ahb1_gates 10>,
285 clock-names = "ahb", "mmc"; 303 <&mmc2_clk 0>,
304 <&mmc2_clk 1>,
305 <&mmc2_clk 2>;
306 clock-names = "ahb",
307 "mmc",
308 "output",
309 "sample";
286 resets = <&ahb1_rst 10>; 310 resets = <&ahb1_rst 10>;
287 reset-names = "ahb"; 311 reset-names = "ahb";
288 interrupts = <0 62 4>; 312 interrupts = <0 62 4>;
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 05:43:44 -0500