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-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c62
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc57
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h87
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc63
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h1065
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c252
6 files changed, 1042 insertions, 544 deletions
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
index 31a84162632b..416dc9b16978 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
@@ -1325,6 +1325,7 @@ nvc0_grctx_generate_9097(struct nvc0_graph_priv *priv)
1325 nv_mthd(priv, 0x9097, 0x0214, 0x00000000); 1325 nv_mthd(priv, 0x9097, 0x0214, 0x00000000);
1326 1326
1327 switch (nv_device(priv)->chipset) { 1327 switch (nv_device(priv)->chipset) {
1328 case 0xc0:
1328 case 0xd9: 1329 case 0xd9:
1329 case 0xd7: 1330 case 0xd7:
1330 break; 1331 break;
@@ -1471,6 +1472,7 @@ nvc0_grctx_generate_dispatch(struct nvc0_graph_priv *priv)
1471 case 0xd7: 1472 case 0xd7:
1472 nv_wr32(priv, 0x40402c, 0x00000000); 1473 nv_wr32(priv, 0x40402c, 0x00000000);
1473 break; 1474 break;
1475 case 0xc0:
1474 default: 1476 default:
1475 break; 1477 break;
1476 } 1478 }
@@ -1490,6 +1492,7 @@ nvc0_grctx_generate_dispatch(struct nvc0_graph_priv *priv)
1490 nv_wr32(priv, 0x4040c4, 0x00000000); 1492 nv_wr32(priv, 0x4040c4, 0x00000000);
1491 nv_wr32(priv, 0x4040c8, 0xf0000087); 1493 nv_wr32(priv, 0x4040c8, 0xf0000087);
1492 switch (nv_device(priv)->chipset) { 1494 switch (nv_device(priv)->chipset) {
1495 case 0xc0:
1493 case 0xd9: 1496 case 0xd9:
1494 case 0xd7: 1497 case 0xd7:
1495 nv_wr32(priv, 0x4040d0, 0x00000000); 1498 nv_wr32(priv, 0x4040d0, 0x00000000);
@@ -1516,6 +1519,7 @@ nvc0_grctx_generate_dispatch(struct nvc0_graph_priv *priv)
1516 case 0xd9: 1519 case 0xd9:
1517 case 0xd7: 1520 case 0xd7:
1518 break; 1521 break;
1522 case 0xc0:
1519 default: 1523 default:
1520 nv_wr32(priv, 0x404174, 0x00000000); 1524 nv_wr32(priv, 0x404174, 0x00000000);
1521 break; 1525 break;
@@ -1645,20 +1649,24 @@ nvc0_grctx_generate_unk47xx(struct nvc0_graph_priv *priv)
1645static void 1649static void
1646nvc0_grctx_generate_shaders(struct nvc0_graph_priv *priv) 1650nvc0_grctx_generate_shaders(struct nvc0_graph_priv *priv)
1647{ 1651{
1648 1652 switch (nv_device(priv)->chipset) {
1649 if (nv_device(priv)->chipset >= 0xd0) { 1653 case 0xc1:
1650 nv_wr32(priv, 0x405800, 0x0f8000bf); 1654 nv_wr32(priv, 0x405800, 0x0f8000bf);
1651 nv_wr32(priv, 0x405830, 0x02180218); 1655 nv_wr32(priv, 0x405830, 0x02180218);
1652 nv_wr32(priv, 0x405834, 0x08000000); 1656 nv_wr32(priv, 0x405834, 0x00000000);
1653 } else 1657 break;
1654 if (nv_device(priv)->chipset == 0xc1) { 1658 case 0xd9:
1659 case 0xd7:
1655 nv_wr32(priv, 0x405800, 0x0f8000bf); 1660 nv_wr32(priv, 0x405800, 0x0f8000bf);
1656 nv_wr32(priv, 0x405830, 0x02180218); 1661 nv_wr32(priv, 0x405830, 0x02180218);
1657 nv_wr32(priv, 0x405834, 0x00000000); 1662 nv_wr32(priv, 0x405834, 0x08000000);
1658 } else { 1663 break;
1664 case 0xc0:
1665 default:
1659 nv_wr32(priv, 0x405800, 0x078000bf); 1666 nv_wr32(priv, 0x405800, 0x078000bf);
1660 nv_wr32(priv, 0x405830, 0x02180000); 1667 nv_wr32(priv, 0x405830, 0x02180000);
1661 nv_wr32(priv, 0x405834, 0x00000000); 1668 nv_wr32(priv, 0x405834, 0x00000000);
1669 break;
1662 } 1670 }
1663 nv_wr32(priv, 0x405838, 0x00000000); 1671 nv_wr32(priv, 0x405838, 0x00000000);
1664 nv_wr32(priv, 0x405854, 0x00000000); 1672 nv_wr32(priv, 0x405854, 0x00000000);
@@ -1694,6 +1702,7 @@ nvc0_grctx_generate_unk64xx(struct nvc0_graph_priv *priv)
1694 case 0xd7: 1702 case 0xd7:
1695 nv_wr32(priv, 0x4064bc, 0x00000000); 1703 nv_wr32(priv, 0x4064bc, 0x00000000);
1696 break; 1704 break;
1705 case 0xc0:
1697 default: 1706 default:
1698 break; 1707 break;
1699 } 1708 }
@@ -1704,6 +1713,7 @@ nvc0_grctx_generate_unk64xx(struct nvc0_graph_priv *priv)
1704 nv_wr32(priv, 0x4064c0, 0x80140078); 1713 nv_wr32(priv, 0x4064c0, 0x80140078);
1705 nv_wr32(priv, 0x4064c4, 0x0086ffff); 1714 nv_wr32(priv, 0x4064c4, 0x0086ffff);
1706 break; 1715 break;
1716 case 0xc0:
1707 default: 1717 default:
1708 break; 1718 break;
1709 } 1719 }
@@ -1742,6 +1752,12 @@ nvc0_grctx_generate_rop(struct nvc0_graph_priv *priv)
1742 nv_wr32(priv, 0x408800, 0x02802a3c); 1752 nv_wr32(priv, 0x408800, 0x02802a3c);
1743 nv_wr32(priv, 0x408804, 0x00000040); 1753 nv_wr32(priv, 0x408804, 0x00000040);
1744 switch (nv_device(priv)->chipset) { 1754 switch (nv_device(priv)->chipset) {
1755 case 0xc0:
1756 nv_wr32(priv, 0x408808, 0x0003e00d);
1757 nv_wr32(priv, 0x408900, 0x3080b801);
1758 nv_wr32(priv, 0x408904, 0x02000001);
1759 nv_wr32(priv, 0x408908, 0x00c80929);
1760 break;
1745 case 0xc1: 1761 case 0xc1:
1746 nv_wr32(priv, 0x408808, 0x1003e005); 1762 nv_wr32(priv, 0x408808, 0x1003e005);
1747 nv_wr32(priv, 0x408900, 0x3080b801); 1763 nv_wr32(priv, 0x408900, 0x3080b801);
@@ -1780,6 +1796,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
1780 case 0xd9: 1796 case 0xd9:
1781 case 0xd7: 1797 case 0xd7:
1782 break; 1798 break;
1799 case 0xc0:
1783 default: 1800 default:
1784 nv_wr32(priv, 0x418408, 0x00000000); 1801 nv_wr32(priv, 0x418408, 0x00000000);
1785 break; 1802 break;
@@ -1791,6 +1808,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
1791 case 0xd7: 1808 case 0xd7:
1792 nv_wr32(priv, 0x418414, 0x02200fff); 1809 nv_wr32(priv, 0x418414, 0x02200fff);
1793 break; 1810 break;
1811 case 0xc0:
1794 default: 1812 default:
1795 nv_wr32(priv, 0x418414, 0x00200fff); 1813 nv_wr32(priv, 0x418414, 0x00200fff);
1796 break; 1814 break;
@@ -1814,6 +1832,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
1814 case 0xd7: 1832 case 0xd7:
1815 nv_wr32(priv, 0x41870c, 0x00000000); 1833 nv_wr32(priv, 0x41870c, 0x00000000);
1816 break; 1834 break;
1835 case 0xc0:
1817 default: 1836 default:
1818 nv_wr32(priv, 0x41870c, 0x07c80000); 1837 nv_wr32(priv, 0x41870c, 0x07c80000);
1819 break; 1838 break;
@@ -1824,6 +1843,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
1824 case 0xd7: 1843 case 0xd7:
1825 nv_wr32(priv, 0x418800, 0x7006860a); 1844 nv_wr32(priv, 0x418800, 0x7006860a);
1826 break; 1845 break;
1846 case 0xc0:
1827 default: 1847 default:
1828 nv_wr32(priv, 0x418800, 0x0006860a); 1848 nv_wr32(priv, 0x418800, 0x0006860a);
1829 break; 1849 break;
@@ -1838,6 +1858,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
1838 case 0xd7: 1858 case 0xd7:
1839 nv_wr32(priv, 0x418830, 0x10000001); 1859 nv_wr32(priv, 0x418830, 0x10000001);
1840 break; 1860 break;
1861 case 0xc0:
1841 default: 1862 default:
1842 nv_wr32(priv, 0x418830, 0x00000001); 1863 nv_wr32(priv, 0x418830, 0x00000001);
1843 break; 1864 break;
@@ -1857,6 +1878,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
1857 case 0xd7: 1878 case 0xd7:
1858 nv_wr32(priv, 0x4188fc, 0x20100008); 1879 nv_wr32(priv, 0x4188fc, 0x20100008);
1859 break; 1880 break;
1881 case 0xc0:
1860 default: 1882 default:
1861 nv_wr32(priv, 0x4188fc, 0x00100000); 1883 nv_wr32(priv, 0x4188fc, 0x00100000);
1862 break; 1884 break;
@@ -1879,6 +1901,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
1879 case 0xd7: 1901 case 0xd7:
1880 nv_wr32(priv, 0x418b00, 0x00000006); 1902 nv_wr32(priv, 0x418b00, 0x00000006);
1881 break; 1903 break;
1904 case 0xc0:
1882 default: 1905 default:
1883 nv_wr32(priv, 0x418b00, 0x00000000); 1906 nv_wr32(priv, 0x418b00, 0x00000000);
1884 break; 1907 break;
@@ -1905,6 +1928,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
1905 case 0xd7: 1928 case 0xd7:
1906 nv_wr32(priv, 0x418c6c, 0x00000001); 1929 nv_wr32(priv, 0x418c6c, 0x00000001);
1907 break; 1930 break;
1931 case 0xc0:
1908 default: 1932 default:
1909 break; 1933 break;
1910 } 1934 }
@@ -1929,6 +1953,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
1929 case 0xd7: 1953 case 0xd7:
1930 nv_wr32(priv, 0x419864, 0x00000129); 1954 nv_wr32(priv, 0x419864, 0x00000129);
1931 break; 1955 break;
1956 case 0xc0:
1932 default: 1957 default:
1933 nv_wr32(priv, 0x419864, 0x0000012a); 1958 nv_wr32(priv, 0x419864, 0x0000012a);
1934 break; 1959 break;
@@ -1940,8 +1965,14 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
1940 nv_wr32(priv, 0x419a0c, 0x00020000); 1965 nv_wr32(priv, 0x419a0c, 0x00020000);
1941 nv_wr32(priv, 0x419a10, 0x00000000); 1966 nv_wr32(priv, 0x419a10, 0x00000000);
1942 nv_wr32(priv, 0x419a14, 0x00000200); 1967 nv_wr32(priv, 0x419a14, 0x00000200);
1943 nv_wr32(priv, 0x419a1c, 0x00000000); 1968 switch (nv_device(priv)->chipset) {
1944 nv_wr32(priv, 0x419a20, 0x00000800); 1969 case 0xc0:
1970 break;
1971 default:
1972 nv_wr32(priv, 0x419a1c, 0x00000000);
1973 nv_wr32(priv, 0x419a20, 0x00000800);
1974 break;
1975 }
1945 switch (nv_device(priv)->chipset) { 1976 switch (nv_device(priv)->chipset) {
1946 case 0xc0: 1977 case 0xc0:
1947 case 0xc8: 1978 case 0xc8:
@@ -1967,6 +1998,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
1967 case 0xd7: 1998 case 0xd7:
1968 nv_wr32(priv, 0x419be0, 0x00400001); 1999 nv_wr32(priv, 0x419be0, 0x00400001);
1969 break; 2000 break;
2001 case 0xc0:
1970 default: 2002 default:
1971 nv_wr32(priv, 0x419be0, 0x00000001); 2003 nv_wr32(priv, 0x419be0, 0x00000001);
1972 break; 2004 break;
@@ -1977,6 +2009,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
1977 case 0xd7: 2009 case 0xd7:
1978 nv_wr32(priv, 0x419c00, 0x0000000a); 2010 nv_wr32(priv, 0x419c00, 0x0000000a);
1979 break; 2011 break;
2012 case 0xc0:
1980 default: 2013 default:
1981 nv_wr32(priv, 0x419c00, 0x00000002); 2014 nv_wr32(priv, 0x419c00, 0x00000002);
1982 break; 2015 break;
@@ -1995,6 +2028,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
1995 nv_wr32(priv, 0x419c28, 0x3cf3cf3c); 2028 nv_wr32(priv, 0x419c28, 0x3cf3cf3c);
1996 nv_wr32(priv, 0x419cb0, 0x00020048); 2029 nv_wr32(priv, 0x419cb0, 0x00020048);
1997 break; 2030 break;
2031 case 0xc0:
1998 default: 2032 default:
1999 nv_wr32(priv, 0x419cb0, 0x00060048); 2033 nv_wr32(priv, 0x419cb0, 0x00060048);
2000 break; 2034 break;
@@ -2007,6 +2041,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
2007 case 0xd7: 2041 case 0xd7:
2008 nv_wr32(priv, 0x419d20, 0x12180000); 2042 nv_wr32(priv, 0x419d20, 0x12180000);
2009 break; 2043 break;
2044 case 0xc0:
2010 default: 2045 default:
2011 nv_wr32(priv, 0x419d20, 0x02180000); 2046 nv_wr32(priv, 0x419d20, 0x02180000);
2012 break; 2047 break;
@@ -2018,6 +2053,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
2018 case 0xd7: 2053 case 0xd7:
2019 nv_wr32(priv, 0x419d44, 0x02180218); 2054 nv_wr32(priv, 0x419d44, 0x02180218);
2020 break; 2055 break;
2056 case 0xc0:
2021 default: 2057 default:
2022 break; 2058 break;
2023 } 2059 }
@@ -2399,6 +2435,7 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv)
2399 for (i = 0x400; i <= 0x417; i++) 2435 for (i = 0x400; i <= 0x417; i++)
2400 nv_icmd(priv, i, 0x00000040); 2436 nv_icmd(priv, i, 0x00000040);
2401 break; 2437 break;
2438 case 0xc0:
2402 default: 2439 default:
2403 break; 2440 break;
2404 } 2441 }
@@ -2416,6 +2453,8 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv)
2416 for (i = 0x440; i <= 0x457; i++) 2453 for (i = 0x440; i <= 0x457; i++)
2417 nv_icmd(priv, i, 0x0000c080); 2454 nv_icmd(priv, i, 0x0000c080);
2418 break; 2455 break;
2456 case 0xc0:
2457 break;
2419 default: 2458 default:
2420 break; 2459 break;
2421 } 2460 }
@@ -2986,6 +3025,7 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv)
2986 case 0xd7: 3025 case 0xd7:
2987 nv_icmd(priv, 0x0000057b, 0x00000059); 3026 nv_icmd(priv, 0x0000057b, 0x00000059);
2988 break; 3027 break;
3028 case 0xc0:
2989 default: 3029 default:
2990 break; 3030 break;
2991 } 3031 }
@@ -3094,6 +3134,7 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv)
3094 case 0xd7: 3134 case 0xd7:
3095 nv_icmd(priv, 0x0000097d, 0x00000020); 3135 nv_icmd(priv, 0x0000097d, 0x00000020);
3096 break; 3136 break;
3137 case 0xc0:
3097 default: 3138 default:
3098 break; 3139 break;
3099 } 3140 }
@@ -3240,6 +3281,9 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv)
3240 nvc0_grctx_generate_90c0(priv); 3281 nvc0_grctx_generate_90c0(priv);
3241 3282
3242 switch (nv_device(priv)->chipset) { 3283 switch (nv_device(priv)->chipset) {
3284 case 0xc0:
3285 nv_mthd(priv, 0x902d, 0x3410, 0x00000000);
3286 break;
3243 case 0xd9: 3287 case 0xd9:
3244 case 0xd7: 3288 case 0xd7:
3245 nv_mthd(priv, 0x902d, 0x3410, 0x80002006); 3289 nv_mthd(priv, 0x902d, 0x3410, 0x80002006);
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc
index a9f499c6729b..1034ff15b032 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc
@@ -48,10 +48,10 @@ cmd_queue: queue_init
48// chipset descriptions 48// chipset descriptions
49chipsets: 49chipsets:
50.b8 0xc0 0 0 0 50.b8 0xc0 0 0 0
51.b16 #nvc0_gpc_mmio_head 51.b16 #nnvc0_gpc_mmio_head
52.b16 #nvc0_gpc_mmio_tail 52.b16 #nnvc0_gpc_mmio_tail
53.b16 #nvc0_tpc_mmio_head 53.b16 #nnvc0_tpc_mmio_head
54.b16 #nvc0_tpc_mmio_tail 54.b16 #nnvc0_tpc_mmio_tail
55.b8 0xc1 0 0 0 55.b8 0xc1 0 0 0
56.b16 #nvc0_gpc_mmio_head 56.b16 #nvc0_gpc_mmio_head
57.b16 #nvc1_gpc_mmio_tail 57.b16 #nvc1_gpc_mmio_tail
@@ -124,6 +124,33 @@ nvc0_gpc_mmio_tail:
124mmctx_data(0x000c6c, 1); 124mmctx_data(0x000c6c, 1);
125nvc1_gpc_mmio_tail: 125nvc1_gpc_mmio_tail:
126 126
127nnvc0_gpc_mmio_head:
128mmctx_data(0x000380, 1)
129mmctx_data(0x000400, 6)
130mmctx_data(0x000450, 9)
131mmctx_data(0x000600, 1)
132mmctx_data(0x000684, 1)
133mmctx_data(0x000700, 5)
134mmctx_data(0x000800, 1)
135mmctx_data(0x000808, 3)
136mmctx_data(0x000828, 1)
137mmctx_data(0x000830, 1)
138mmctx_data(0x0008d8, 1)
139mmctx_data(0x0008e0, 1)
140mmctx_data(0x0008e8, 6)
141mmctx_data(0x00091c, 1)
142mmctx_data(0x000924, 3)
143mmctx_data(0x000b00, 1)
144mmctx_data(0x000b08, 6)
145mmctx_data(0x000bb8, 1)
146mmctx_data(0x000c08, 1)
147mmctx_data(0x000c10, 8)
148mmctx_data(0x000c80, 1)
149mmctx_data(0x000c8c, 1)
150mmctx_data(0x001000, 3)
151mmctx_data(0x001014, 1)
152nnvc0_gpc_mmio_tail:
153
127nvd9_gpc_mmio_head: 154nvd9_gpc_mmio_head:
128mmctx_data(0x000380, 1) 155mmctx_data(0x000380, 1)
129mmctx_data(0x000400, 2) 156mmctx_data(0x000400, 2)
@@ -185,6 +212,28 @@ nvc3_tpc_mmio_tail:
185mmctx_data(0x000544, 1) 212mmctx_data(0x000544, 1)
186nvc1_tpc_mmio_tail: 213nvc1_tpc_mmio_tail:
187 214
215nnvc0_tpc_mmio_head:
216mmctx_data(0x000018, 1)
217mmctx_data(0x00003c, 1)
218mmctx_data(0x000048, 1)
219mmctx_data(0x000064, 1)
220mmctx_data(0x000088, 1)
221mmctx_data(0x000200, 6)
222mmctx_data(0x000300, 6)
223mmctx_data(0x0003d0, 1)
224mmctx_data(0x0003e0, 2)
225mmctx_data(0x000400, 3)
226mmctx_data(0x000420, 1)
227mmctx_data(0x0004b0, 1)
228mmctx_data(0x0004e8, 1)
229mmctx_data(0x0004f4, 1)
230mmctx_data(0x000520, 2)
231mmctx_data(0x000604, 4)
232mmctx_data(0x000644, 20)
233mmctx_data(0x000698, 1)
234mmctx_data(0x000750, 2)
235nnvc0_tpc_mmio_tail:
236
188nvd9_tpc_mmio_head: 237nvd9_tpc_mmio_head:
189mmctx_data(0x000018, 1) 238mmctx_data(0x000018, 1)
190mmctx_data(0x00003c, 1) 239mmctx_data(0x00003c, 1)
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h
index b8c9fc3b32bd..427ddf06316c 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h
@@ -34,32 +34,32 @@ uint32_t nvc0_grgpc_data[] = {
34 0x00000000, 34 0x00000000,
35/* 0x0064: chipsets */ 35/* 0x0064: chipsets */
36 0x000000c0, 36 0x000000c0,
37 0x013400d4, 37 0x01980138,
38 0x01f001a0, 38 0x02b00264,
39 0x000000c1, 39 0x000000c1,
40 0x013800d4, 40 0x013800d4,
41 0x020401a0, 41 0x02640200,
42 0x000000c3, 42 0x000000c3,
43 0x013400d4, 43 0x013400d4,
44 0x020001a0, 44 0x02600200,
45 0x000000c4, 45 0x000000c4,
46 0x013400d4, 46 0x013400d4,
47 0x020001a0, 47 0x02600200,
48 0x000000c8, 48 0x000000c8,
49 0x013400d4, 49 0x013400d4,
50 0x01f001a0, 50 0x02500200,
51 0x000000ce, 51 0x000000ce,
52 0x013400d4, 52 0x013400d4,
53 0x020001a0, 53 0x02600200,
54 0x000000cf, 54 0x000000cf,
55 0x013400d4, 55 0x013400d4,
56 0x01fc01a0, 56 0x025c0200,
57 0x000000d9, 57 0x000000d9,
58 0x01a00138, 58 0x02000198,
59 0x02600204, 59 0x030c02b0,
60 0x000000d7, 60 0x000000d7,
61 0x01a00138, 61 0x02000198,
62 0x02600204, 62 0x030c02b0,
63 0x00000000, 63 0x00000000,
64/* 0x00d4: nvc0_gpc_mmio_head */ 64/* 0x00d4: nvc0_gpc_mmio_head */
65 0x00000380, 65 0x00000380,
@@ -89,7 +89,33 @@ uint32_t nvc0_grgpc_data[] = {
89/* 0x0134: nvc0_gpc_mmio_tail */ 89/* 0x0134: nvc0_gpc_mmio_tail */
90 0x00000c6c, 90 0x00000c6c,
91/* 0x0138: nvc1_gpc_mmio_tail */ 91/* 0x0138: nvc1_gpc_mmio_tail */
92/* 0x0138: nvd9_gpc_mmio_head */ 92/* 0x0138: nnvc0_gpc_mmio_head */
93 0x00000380,
94 0x14000400,
95 0x20000450,
96 0x00000600,
97 0x00000684,
98 0x10000700,
99 0x00000800,
100 0x08000808,
101 0x00000828,
102 0x00000830,
103 0x000008d8,
104 0x000008e0,
105 0x140008e8,
106 0x0000091c,
107 0x08000924,
108 0x00000b00,
109 0x14000b08,
110 0x00000bb8,
111 0x00000c08,
112 0x1c000c10,
113 0x00000c80,
114 0x00000c8c,
115 0x08001000,
116 0x00001014,
117/* 0x0198: nnvc0_gpc_mmio_tail */
118/* 0x0198: nvd9_gpc_mmio_head */
93 0x00000380, 119 0x00000380,
94 0x04000400, 120 0x04000400,
95 0x0800040c, 121 0x0800040c,
@@ -116,8 +142,8 @@ uint32_t nvc0_grgpc_data[] = {
116 0x00000c8c, 142 0x00000c8c,
117 0x08001000, 143 0x08001000,
118 0x00001014, 144 0x00001014,
119/* 0x01a0: nvd9_gpc_mmio_tail */ 145/* 0x0200: nvd9_gpc_mmio_tail */
120/* 0x01a0: nvc0_tpc_mmio_head */ 146/* 0x0200: nvc0_tpc_mmio_head */
121 0x00000018, 147 0x00000018,
122 0x0000003c, 148 0x0000003c,
123 0x00000048, 149 0x00000048,
@@ -138,16 +164,37 @@ uint32_t nvc0_grgpc_data[] = {
138 0x4c000644, 164 0x4c000644,
139 0x00000698, 165 0x00000698,
140 0x04000750, 166 0x04000750,
141/* 0x01f0: nvc0_tpc_mmio_tail */ 167/* 0x0250: nvc0_tpc_mmio_tail */
142 0x00000758, 168 0x00000758,
143 0x000002c4, 169 0x000002c4,
144 0x000006e0, 170 0x000006e0,
145/* 0x01fc: nvcf_tpc_mmio_tail */ 171/* 0x025c: nvcf_tpc_mmio_tail */
146 0x000004bc, 172 0x000004bc,
147/* 0x0200: nvc3_tpc_mmio_tail */ 173/* 0x0260: nvc3_tpc_mmio_tail */
148 0x00000544, 174 0x00000544,
149/* 0x0204: nvc1_tpc_mmio_tail */ 175/* 0x0264: nvc1_tpc_mmio_tail */
150/* 0x0204: nvd9_tpc_mmio_head */ 176/* 0x0264: nnvc0_tpc_mmio_head */
177 0x00000018,
178 0x0000003c,
179 0x00000048,
180 0x00000064,
181 0x00000088,
182 0x14000200,
183 0x14000300,
184 0x000003d0,
185 0x040003e0,
186 0x08000400,
187 0x00000420,
188 0x000004b0,
189 0x000004e8,
190 0x000004f4,
191 0x04000520,
192 0x0c000604,
193 0x4c000644,
194 0x00000698,
195 0x04000750,
196/* 0x02b0: nnvc0_tpc_mmio_tail */
197/* 0x02b0: nvd9_tpc_mmio_head */
151 0x00000018, 198 0x00000018,
152 0x0000003c, 199 0x0000003c,
153 0x00000048, 200 0x00000048,
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc
index 56735d0654bf..9f0768e2719d 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc
@@ -37,10 +37,19 @@ hub_mmio_list_tail: .b32 0
37 37
38ctx_current: .b32 0 38ctx_current: .b32 0
39 39
40.align 256
41chan_data:
42chan_mmio_count: .b32 0
43chan_mmio_address: .b32 0
44
45.align 256
46xfer_data: .b32 0
47
48.align 256
40chipsets: 49chipsets:
41.b8 0xc0 0 0 0 50.b8 0xc0 0 0 0
42.b16 #nvc0_hub_mmio_head 51.b16 #nnvc0_hub_mmio_head
43.b16 #nvc0_hub_mmio_tail 52.b16 #nnvc0_hub_mmio_tail
44.b8 0xc1 0 0 0 53.b8 0xc1 0 0 0
45.b16 #nvc0_hub_mmio_head 54.b16 #nvc0_hub_mmio_head
46.b16 #nvc1_hub_mmio_tail 55.b16 #nvc1_hub_mmio_tail
@@ -111,6 +120,48 @@ nvc0_hub_mmio_tail:
111mmctx_data(0x4064c0, 2) 120mmctx_data(0x4064c0, 2)
112nvc1_hub_mmio_tail: 121nvc1_hub_mmio_tail:
113 122
123nnvc0_hub_mmio_head:
124mmctx_data(0x17e91c, 2)
125mmctx_data(0x400204, 2)
126mmctx_data(0x404004, 11)
127mmctx_data(0x404044, 1)
128mmctx_data(0x404094, 14)
129mmctx_data(0x4040d0, 7)
130mmctx_data(0x4040f8, 1)
131mmctx_data(0x404130, 3)
132mmctx_data(0x404150, 3)
133mmctx_data(0x404164, 2)
134mmctx_data(0x404174, 3)
135mmctx_data(0x404200, 8)
136mmctx_data(0x404404, 14)
137mmctx_data(0x404460, 4)
138mmctx_data(0x404480, 1)
139mmctx_data(0x404498, 1)
140mmctx_data(0x404604, 4)
141mmctx_data(0x404618, 32)
142mmctx_data(0x404698, 21)
143mmctx_data(0x4046f0, 2)
144mmctx_data(0x404700, 22)
145mmctx_data(0x405800, 1)
146mmctx_data(0x405830, 3)
147mmctx_data(0x405854, 1)
148mmctx_data(0x405870, 4)
149mmctx_data(0x405a00, 2)
150mmctx_data(0x405a18, 1)
151mmctx_data(0x406020, 1)
152mmctx_data(0x406028, 4)
153mmctx_data(0x4064a8, 2)
154mmctx_data(0x4064b4, 2)
155mmctx_data(0x407804, 1)
156mmctx_data(0x40780c, 6)
157mmctx_data(0x4078bc, 1)
158mmctx_data(0x408000, 7)
159mmctx_data(0x408064, 1)
160mmctx_data(0x408800, 3)
161mmctx_data(0x408900, 3)
162mmctx_data(0x408980, 1)
163nnvc0_hub_mmio_tail:
164
114nvd9_hub_mmio_head: 165nvd9_hub_mmio_head:
115mmctx_data(0x17e91c, 2) 166mmctx_data(0x17e91c, 2)
116mmctx_data(0x400204, 2) 167mmctx_data(0x400204, 2)
@@ -153,14 +204,6 @@ mmctx_data(0x408900, 3)
153mmctx_data(0x408980, 1) 204mmctx_data(0x408980, 1)
154nvd9_hub_mmio_tail: 205nvd9_hub_mmio_tail:
155 206
156.align 256
157chan_data:
158chan_mmio_count: .b32 0
159chan_mmio_address: .b32 0
160
161.align 256
162xfer_data: .b32 0
163
164.section #nvc0_grhub_code 207.section #nvc0_grhub_code
165bra #init 208bra #init
166define(`include_code') 209define(`include_code')
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h
index eb59892bc488..fc5f9727ae76 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h
@@ -28,27 +28,200 @@ uint32_t nvc0_grhub_data[] = {
28 0x00000000, 28 0x00000000,
29/* 0x0058: ctx_current */ 29/* 0x0058: ctx_current */
30 0x00000000, 30 0x00000000,
31/* 0x005c: chipsets */ 31 0x00000000,
32 0x00000000,
33 0x00000000,
34 0x00000000,
35 0x00000000,
36 0x00000000,
37 0x00000000,
38 0x00000000,
39 0x00000000,
40 0x00000000,
41 0x00000000,
42 0x00000000,
43 0x00000000,
44 0x00000000,
45 0x00000000,
46 0x00000000,
47 0x00000000,
48 0x00000000,
49 0x00000000,
50 0x00000000,
51 0x00000000,
52 0x00000000,
53 0x00000000,
54 0x00000000,
55 0x00000000,
56 0x00000000,
57 0x00000000,
58 0x00000000,
59 0x00000000,
60 0x00000000,
61 0x00000000,
62 0x00000000,
63 0x00000000,
64 0x00000000,
65 0x00000000,
66 0x00000000,
67 0x00000000,
68 0x00000000,
69 0x00000000,
70 0x00000000,
71 0x00000000,
72/* 0x0100: chan_data */
73/* 0x0100: chan_mmio_count */
74 0x00000000,
75/* 0x0104: chan_mmio_address */
76 0x00000000,
77 0x00000000,
78 0x00000000,
79 0x00000000,
80 0x00000000,
81 0x00000000,
82 0x00000000,
83 0x00000000,
84 0x00000000,
85 0x00000000,
86 0x00000000,
87 0x00000000,
88 0x00000000,
89 0x00000000,
90 0x00000000,
91 0x00000000,
92 0x00000000,
93 0x00000000,
94 0x00000000,
95 0x00000000,
96 0x00000000,
97 0x00000000,
98 0x00000000,
99 0x00000000,
100 0x00000000,
101 0x00000000,
102 0x00000000,
103 0x00000000,
104 0x00000000,
105 0x00000000,
106 0x00000000,
107 0x00000000,
108 0x00000000,
109 0x00000000,
110 0x00000000,
111 0x00000000,
112 0x00000000,
113 0x00000000,
114 0x00000000,
115 0x00000000,
116 0x00000000,
117 0x00000000,
118 0x00000000,
119 0x00000000,
120 0x00000000,
121 0x00000000,
122 0x00000000,
123 0x00000000,
124 0x00000000,
125 0x00000000,
126 0x00000000,
127 0x00000000,
128 0x00000000,
129 0x00000000,
130 0x00000000,
131 0x00000000,
132 0x00000000,
133 0x00000000,
134 0x00000000,
135 0x00000000,
136 0x00000000,
137 0x00000000,
138 0x00000000,
139/* 0x0200: xfer_data */
140 0x00000000,
141 0x00000000,
142 0x00000000,
143 0x00000000,
144 0x00000000,
145 0x00000000,
146 0x00000000,
147 0x00000000,
148 0x00000000,
149 0x00000000,
150 0x00000000,
151 0x00000000,
152 0x00000000,
153 0x00000000,
154 0x00000000,
155 0x00000000,
156 0x00000000,
157 0x00000000,
158 0x00000000,
159 0x00000000,
160 0x00000000,
161 0x00000000,
162 0x00000000,
163 0x00000000,
164 0x00000000,
165 0x00000000,
166 0x00000000,
167 0x00000000,
168 0x00000000,
169 0x00000000,
170 0x00000000,
171 0x00000000,
172 0x00000000,
173 0x00000000,
174 0x00000000,
175 0x00000000,
176 0x00000000,
177 0x00000000,
178 0x00000000,
179 0x00000000,
180 0x00000000,
181 0x00000000,
182 0x00000000,
183 0x00000000,
184 0x00000000,
185 0x00000000,
186 0x00000000,
187 0x00000000,
188 0x00000000,
189 0x00000000,
190 0x00000000,
191 0x00000000,
192 0x00000000,
193 0x00000000,
194 0x00000000,
195 0x00000000,
196 0x00000000,
197 0x00000000,
198 0x00000000,
199 0x00000000,
200 0x00000000,
201 0x00000000,
202 0x00000000,
203 0x00000000,
204/* 0x0300: chipsets */
32 0x000000c0, 205 0x000000c0,
33 0x014400a8, 206 0x048803ec,
34 0x000000c1, 207 0x000000c1,
35 0x014800a8, 208 0x03ec034c,
36 0x000000c3, 209 0x000000c3,
37 0x014400a8, 210 0x03e8034c,
38 0x000000c4, 211 0x000000c4,
39 0x014400a8, 212 0x03e8034c,
40 0x000000c8, 213 0x000000c8,
41 0x014400a8, 214 0x03e8034c,
42 0x000000ce, 215 0x000000ce,
43 0x014400a8, 216 0x03e8034c,
44 0x000000cf, 217 0x000000cf,
45 0x014400a8, 218 0x03e8034c,
46 0x000000d9, 219 0x000000d9,
47 0x01e40148, 220 0x05240488,
48 0x000000d7, 221 0x000000d7,
49 0x01e40148, 222 0x05240488,
50 0x00000000, 223 0x00000000,
51/* 0x00a8: nvc0_hub_mmio_head */ 224/* 0x034c: nvc0_hub_mmio_head */
52 0x0417e91c, 225 0x0417e91c,
53 0x04400204, 226 0x04400204,
54 0x28404004, 227 0x28404004,
@@ -88,10 +261,51 @@ uint32_t nvc0_grhub_data[] = {
88 0x08408800, 261 0x08408800,
89 0x0c408900, 262 0x0c408900,
90 0x00408980, 263 0x00408980,
91/* 0x0144: nvc0_hub_mmio_tail */ 264/* 0x03e8: nvc0_hub_mmio_tail */
92 0x044064c0, 265 0x044064c0,
93/* 0x0148: nvc1_hub_mmio_tail */ 266/* 0x03ec: nvc1_hub_mmio_tail */
94/* 0x0148: nvd9_hub_mmio_head */ 267/* 0x03ec: nnvc0_hub_mmio_head */
268 0x0417e91c,
269 0x04400204,
270 0x28404004,
271 0x00404044,
272 0x34404094,
273 0x184040d0,
274 0x004040f8,
275 0x08404130,
276 0x08404150,
277 0x04404164,
278 0x08404174,
279 0x1c404200,
280 0x34404404,
281 0x0c404460,
282 0x00404480,
283 0x00404498,
284 0x0c404604,
285 0x7c404618,
286 0x50404698,
287 0x044046f0,
288 0x54404700,
289 0x00405800,
290 0x08405830,
291 0x00405854,
292 0x0c405870,
293 0x04405a00,
294 0x00405a18,
295 0x00406020,
296 0x0c406028,
297 0x044064a8,
298 0x044064b4,
299 0x00407804,
300 0x1440780c,
301 0x004078bc,
302 0x18408000,
303 0x00408064,
304 0x08408800,
305 0x08408900,
306 0x00408980,
307/* 0x0488: nnvc0_hub_mmio_tail */
308/* 0x0488: nvd9_hub_mmio_head */
95 0x0417e91c, 309 0x0417e91c,
96 0x04400204, 310 0x04400204,
97 0x24404004, 311 0x24404004,
@@ -131,83 +345,6 @@ uint32_t nvc0_grhub_data[] = {
131 0x08408800, 345 0x08408800,
132 0x08408900, 346 0x08408900,
133 0x00408980, 347 0x00408980,
134/* 0x01e4: nvd9_hub_mmio_tail */
135 0x00000000,
136 0x00000000,
137 0x00000000,
138 0x00000000,
139 0x00000000,
140 0x00000000,
141 0x00000000,
142/* 0x0200: chan_data */
143/* 0x0200: chan_mmio_count */
144 0x00000000,
145/* 0x0204: chan_mmio_address */
146 0x00000000,
147 0x00000000,
148 0x00000000,
149 0x00000000,
150 0x00000000,
151 0x00000000,
152 0x00000000,
153 0x00000000,
154 0x00000000,
155 0x00000000,
156 0x00000000,
157 0x00000000,
158 0x00000000,
159 0x00000000,
160 0x00000000,
161 0x00000000,
162 0x00000000,
163 0x00000000,
164 0x00000000,
165 0x00000000,
166 0x00000000,
167 0x00000000,
168 0x00000000,
169 0x00000000,
170 0x00000000,
171 0x00000000,
172 0x00000000,
173 0x00000000,
174 0x00000000,
175 0x00000000,
176 0x00000000,
177 0x00000000,
178 0x00000000,
179 0x00000000,
180 0x00000000,
181 0x00000000,
182 0x00000000,
183 0x00000000,
184 0x00000000,
185 0x00000000,
186 0x00000000,
187 0x00000000,
188 0x00000000,
189 0x00000000,
190 0x00000000,
191 0x00000000,
192 0x00000000,
193 0x00000000,
194 0x00000000,
195 0x00000000,
196 0x00000000,
197 0x00000000,
198 0x00000000,
199 0x00000000,
200 0x00000000,
201 0x00000000,
202 0x00000000,
203 0x00000000,
204 0x00000000,
205 0x00000000,
206 0x00000000,
207 0x00000000,
208 0x00000000,
209/* 0x0300: xfer_data */
210 0x00000000,
211}; 348};
212 349
213uint32_t nvc0_grhub_code[] = { 350uint32_t nvc0_grhub_code[] = {
@@ -443,7 +580,7 @@ uint32_t nvc0_grhub_code[] = {
443 0x0017f100, 580 0x0017f100,
444 0x0227f012, 581 0x0227f012,
445 0xf10012d0, 582 0xf10012d0,
446 0xfe05b917, 583 0xfe05ba17,
447 0x17f10010, 584 0x17f10010,
448 0x10d00400, 585 0x10d00400,
449 0x0437f1c0, 586 0x0437f1c0,
@@ -477,403 +614,403 @@ uint32_t nvc0_grhub_code[] = {
477 0x4021d000, 614 0x4021d000,
478 0x080027f1, 615 0x080027f1,
479 0xcf0624b6, 616 0xcf0624b6,
480 0xf7f00022, 617 0xf7f10022,
481/* 0x03a9: init_find_chipset */ 618/* 0x03aa: init_find_chipset */
482 0x08f0b654, 619 0xf0b602f8,
483 0xb800f398, 620 0x00f39808,
484 0x0bf40432, 621 0xf40432b8,
485 0x0034b00b, 622 0x34b00b0b,
486 0xf8f11bf4, 623 0xf11bf400,
487/* 0x03bd: init_context */ 624/* 0x03be: init_context */
488 0x0017f100, 625 0x17f100f8,
489 0x02fe5801, 626 0xfe580100,
490 0xf003ff58, 627 0x03ff5802,
491 0x0e8000e3, 628 0x8000e3f0,
492 0x150f8014, 629 0x0f80140e,
493 0x013d21f5, 630 0x3d21f515,
494 0x070037f1, 631 0x0037f101,
495 0x950634b6, 632 0x0634b607,
496 0x34d00814, 633 0xd0081495,
497 0x4034d000, 634 0x34d00034,
498 0x130030b7, 635 0x0030b740,
499 0xb6001fbb, 636 0x001fbb13,
500 0x3fd002f5, 637 0xd002f5b6,
501 0x0815b600, 638 0x15b6003f,
502 0xb60110b6, 639 0x0110b608,
503 0x1fb90814, 640 0xb90814b6,
504 0x6321f502, 641 0x21f5021f,
505 0x001fbb02, 642 0x1fbb0263,
506 0xf1000398, 643 0x00039800,
507 0xf0200047, 644 0x200047f1,
508/* 0x040e: init_gpc */ 645/* 0x040f: init_gpc */
509 0x4ea05043, 646 0xa05043f0,
510 0x1fb90804, 647 0xb908044e,
511 0x8d21f402, 648 0x21f4021f,
512 0x08004ea0, 649 0x004ea08d,
513 0xf4022fb9, 650 0x022fb908,
514 0x4ea08d21,
515 0xf4bd010c,
516 0xa08d21f4, 651 0xa08d21f4,
517 0xf401044e, 652 0xbd010c4e,
518 0x4ea08d21, 653 0x8d21f4f4,
519 0xf7f00100, 654 0x01044ea0,
520 0x8d21f402, 655 0xa08d21f4,
521 0x08004ea0, 656 0xf001004e,
522/* 0x0440: init_gpc_wait */ 657 0x21f402f7,
523 0xc86821f4, 658 0x004ea08d,
524 0x0bf41fff, 659/* 0x0441: init_gpc_wait */
525 0x044ea0fa,
526 0x6821f408, 660 0x6821f408,
527 0xb7001fbb, 661 0xf41fffc8,
528 0xb6800040, 662 0x4ea0fa0b,
529 0x1bf40132, 663 0x21f40804,
530 0x0027f1b4, 664 0x001fbb68,
531 0x0624b608, 665 0x800040b7,
532 0xb74021d0, 666 0xf40132b6,
533 0xbd080020, 667 0x27f1b41b,
534 0x1f19f014, 668 0x24b60800,
535/* 0x0473: main */ 669 0x4021d006,
536 0xf40021d0, 670 0x080020b7,
537 0x28f40031, 671 0x19f014bd,
538 0x08d7f000, 672 0x0021d01f,
539 0xf43921f4, 673/* 0x0474: main */
540 0xe4b1f401, 674 0xf40031f4,
541 0x1bf54001, 675 0xd7f00028,
542 0x87f100d1, 676 0x3921f408,
543 0x84b6083c, 677 0xb1f401f4,
544 0xf094bd06, 678 0xf54001e4,
545 0x89d00499, 679 0xf100d11b,
546 0x0017f100,
547 0x0614b60b,
548 0xcf4012cf,
549 0x13c80011,
550 0x7e0bf41f,
551 0xf41f23c8,
552 0x20f95a0b,
553 0xf10212b9,
554 0xb6083c87, 680 0xb6083c87,
555 0x94bd0684, 681 0x94bd0684,
556 0xd00799f0, 682 0xd00499f0,
557 0x32f40089, 683 0x17f10089,
558 0x0231f401, 684 0x14b60b00,
559 0x082921f5, 685 0x4012cf06,
560 0x085c87f1, 686 0xc80011cf,
687 0x0bf41f13,
688 0x1f23c87e,
689 0xf95a0bf4,
690 0x0212b920,
691 0x083c87f1,
561 0xbd0684b6, 692 0xbd0684b6,
562 0x0799f094, 693 0x0799f094,
563 0xfc0089d0, 694 0xf40089d0,
564 0x3c87f120, 695 0x31f40132,
696 0x2a21f502,
697 0x5c87f108,
565 0x0684b608, 698 0x0684b608,
566 0x99f094bd, 699 0x99f094bd,
567 0x0089d006, 700 0x0089d007,
568 0xf50131f4, 701 0x87f120fc,
569 0xf1082921, 702 0x84b6083c,
570 0xb6085c87, 703 0xf094bd06,
571 0x94bd0684, 704 0x89d00699,
572 0xd00699f0, 705 0x0131f400,
573 0x0ef40089, 706 0x082a21f5,
574/* 0x0509: chsw_prev_no_next */
575 0xb920f931,
576 0x32f40212,
577 0x0232f401,
578 0x082921f5,
579 0x17f120fc,
580 0x14b60b00,
581 0x0012d006,
582/* 0x0527: chsw_no_prev */
583 0xc8130ef4,
584 0x0bf41f23,
585 0x0131f40d,
586 0xf50232f4,
587/* 0x0537: chsw_done */
588 0xf1082921,
589 0xb60b0c17,
590 0x27f00614,
591 0x0012d001,
592 0x085c87f1, 707 0x085c87f1,
593 0xbd0684b6, 708 0xbd0684b6,
594 0x0499f094, 709 0x0699f094,
595 0xf50089d0, 710 0xf40089d0,
596/* 0x0557: main_not_ctx_switch */ 711/* 0x050a: chsw_prev_no_next */
597 0xb0ff200e, 712 0x20f9310e,
598 0x1bf401e4, 713 0xf40212b9,
599 0x02f2b90d, 714 0x32f40132,
600 0x07b521f5, 715 0x2a21f502,
601/* 0x0567: main_not_ctx_chan */ 716 0xf120fc08,
602 0xb0420ef4, 717 0xb60b0017,
603 0x1bf402e4, 718 0x12d00614,
604 0x3c87f12e, 719 0x130ef400,
720/* 0x0528: chsw_no_prev */
721 0xf41f23c8,
722 0x31f40d0b,
723 0x0232f401,
724 0x082a21f5,
725/* 0x0538: chsw_done */
726 0x0b0c17f1,
727 0xf00614b6,
728 0x12d00127,
729 0x5c87f100,
605 0x0684b608, 730 0x0684b608,
606 0x99f094bd, 731 0x99f094bd,
607 0x0089d007, 732 0x0089d004,
608 0xf40132f4, 733 0xff200ef5,
609 0x21f50232, 734/* 0x0558: main_not_ctx_switch */
610 0x87f10829, 735 0xf401e4b0,
611 0x84b6085c, 736 0xf2b90d1b,
737 0xb621f502,
738 0x420ef407,
739/* 0x0568: main_not_ctx_chan */
740 0xf402e4b0,
741 0x87f12e1b,
742 0x84b6083c,
612 0xf094bd06, 743 0xf094bd06,
613 0x89d00799, 744 0x89d00799,
614 0x110ef400, 745 0x0132f400,
615/* 0x0598: main_not_ctx_save */ 746 0xf50232f4,
616 0xf010ef94, 747 0xf1082a21,
617 0x21f501f5, 748 0xb6085c87,
618 0x0ef502ec, 749 0x94bd0684,
619/* 0x05a6: main_done */ 750 0xd00799f0,
620 0x17f1fed1, 751 0x0ef40089,
621 0x14b60820, 752/* 0x0599: main_not_ctx_save */
622 0xf024bd06, 753 0x10ef9411,
623 0x12d01f29, 754 0xf501f5f0,
624 0xbe0ef500, 755 0xf502ec21,
625/* 0x05b9: ih */ 756/* 0x05a7: main_done */
626 0xfe80f9fe, 757 0xf1fed10e,
627 0x80f90188, 758 0xb6082017,
628 0xa0f990f9, 759 0x24bd0614,
629 0xd0f9b0f9, 760 0xd01f29f0,
630 0xf0f9e0f9, 761 0x0ef50012,
631 0xc4800acf, 762/* 0x05ba: ih */
632 0x0bf404ab, 763 0x80f9febe,
633 0x00b7f11d, 764 0xf90188fe,
634 0x08d7f019, 765 0xf990f980,
635 0xcf40becf, 766 0xf9b0f9a0,
636 0x21f400bf, 767 0xf9e0f9d0,
637 0x00b0b704, 768 0x800acff0,
638 0x01e7f004, 769 0xf404abc4,
639/* 0x05ef: ih_no_fifo */ 770 0xb7f11d0b,
640 0xe400bed0, 771 0xd7f01900,
641 0xf40100ab, 772 0x40becf08,
642 0xd7f00d0b, 773 0xf400bfcf,
643 0x01e7f108, 774 0xb0b70421,
644 0x0421f440, 775 0xe7f00400,
645/* 0x0600: ih_no_ctxsw */ 776 0x00bed001,
646 0x0104b7f1, 777/* 0x05f0: ih_no_fifo */
647 0xabffb0bd, 778 0x0100abe4,
648 0x0d0bf4b4, 779 0xf00d0bf4,
649 0x0c1ca7f1, 780 0xe7f108d7,
650 0xd006a4b6, 781 0x21f44001,
651/* 0x0616: ih_no_other */ 782/* 0x0601: ih_no_ctxsw */
652 0x0ad000ab, 783 0x04b7f104,
653 0xfcf0fc40, 784 0xffb0bd01,
654 0xfcd0fce0, 785 0x0bf4b4ab,
655 0xfca0fcb0, 786 0x1ca7f10d,
656 0xfe80fc90, 787 0x06a4b60c,
657 0x80fc0088, 788/* 0x0617: ih_no_other */
658 0xf80032f4, 789 0xd000abd0,
659/* 0x0631: ctx_4160s */ 790 0xf0fc400a,
660 0x60e7f101, 791 0xd0fce0fc,
661 0x40e3f041, 792 0xa0fcb0fc,
662 0xf401f7f0, 793 0x80fc90fc,
663/* 0x063e: ctx_4160s_wait */ 794 0xfc0088fe,
664 0x21f48d21, 795 0x0032f480,
665 0x04ffc868, 796/* 0x0632: ctx_4160s */
666 0xf8fa0bf4, 797 0xe7f101f8,
667/* 0x0649: ctx_4160c */ 798 0xe3f04160,
668 0x60e7f100, 799 0x01f7f040,
669 0x40e3f041, 800/* 0x063f: ctx_4160s_wait */
670 0x21f4f4bd, 801 0xf48d21f4,
671/* 0x0657: ctx_4170s */ 802 0xffc86821,
672 0xf100f88d, 803 0xfa0bf404,
673 0xf04170e7, 804/* 0x064a: ctx_4160c */
674 0xf5f040e3,
675 0x8d21f410,
676/* 0x0666: ctx_4170w */
677 0xe7f100f8, 805 0xe7f100f8,
678 0xe3f04170, 806 0xe3f04160,
679 0x6821f440, 807 0xf4f4bd40,
680 0xf410f4f0,
681 0x00f8f31b,
682/* 0x0678: ctx_redswitch */
683 0x0614e7f1,
684 0xf106e4b6,
685 0xd00270f7,
686 0xf7f000ef,
687/* 0x0689: ctx_redswitch_delay */
688 0x01f2b608,
689 0xf1fd1bf4,
690 0xd00770f7,
691 0x00f800ef,
692/* 0x0698: ctx_86c */
693 0x086ce7f1,
694 0xd006e4b6,
695 0xe7f100ef,
696 0xe3f08a14,
697 0x8d21f440,
698 0xa86ce7f1,
699 0xf441e3f0,
700 0x00f88d21, 808 0x00f88d21,
701/* 0x06b8: ctx_load */ 809/* 0x0658: ctx_4170s */
702 0x083c87f1, 810 0x4170e7f1,
703 0xbd0684b6, 811 0xf040e3f0,
704 0x0599f094, 812 0x21f410f5,
705 0xf00089d0, 813/* 0x0667: ctx_4170w */
706 0x21f40ca7, 814 0xf100f88d,
707 0x2417f1c9, 815 0xf04170e7,
708 0x0614b60a, 816 0x21f440e3,
709 0xf10010d0, 817 0x10f4f068,
710 0xb60b0037, 818 0xf8f31bf4,
711 0x32d00634, 819/* 0x0679: ctx_redswitch */
712 0x0c17f140, 820 0x14e7f100,
713 0x0614b60a, 821 0x06e4b606,
714 0xd00747f0, 822 0x0270f7f1,
715 0x14d00012, 823 0xf000efd0,
716/* 0x06f1: ctx_chan_wait_0 */ 824/* 0x068a: ctx_redswitch_delay */
717 0x4014cf40, 825 0xf2b608f7,
718 0xf41f44f0, 826 0xfd1bf401,
719 0x32d0fa1b, 827 0x0770f7f1,
720 0x000bfe00, 828 0xf800efd0,
721 0xb61f2af0, 829/* 0x0699: ctx_86c */
722 0x20b60424, 830 0x6ce7f100,
723 0x3c87f102, 831 0x06e4b608,
832 0xf100efd0,
833 0xf08a14e7,
834 0x21f440e3,
835 0x6ce7f18d,
836 0x41e3f0a8,
837 0xf88d21f4,
838/* 0x06b9: ctx_load */
839 0x3c87f100,
724 0x0684b608, 840 0x0684b608,
725 0x99f094bd, 841 0x99f094bd,
726 0x0089d008, 842 0x0089d005,
727 0x0a0417f1, 843 0xf40ca7f0,
844 0x17f1c921,
845 0x14b60a24,
846 0x0010d006,
847 0x0b0037f1,
848 0xd00634b6,
849 0x17f14032,
850 0x14b60a0c,
851 0x0747f006,
852 0xd00012d0,
853/* 0x06f2: ctx_chan_wait_0 */
854 0x14cf4014,
855 0x1f44f040,
856 0xd0fa1bf4,
857 0x0bfe0032,
858 0x1f2af000,
859 0xb60424b6,
860 0x87f10220,
861 0x84b6083c,
862 0xf094bd06,
863 0x89d00899,
864 0x0417f100,
865 0x0614b60a,
866 0xf10012d0,
867 0xb60a2017,
868 0x27f00614,
869 0x0023f102,
870 0x0012d080,
871 0xf11017f0,
872 0xf0020027,
873 0x12fa0223,
874 0xf103f805,
875 0xb6085c87,
876 0x94bd0684,
877 0xd00899f0,
878 0x01980089,
879 0x1814b681,
880 0xb6800298,
881 0x12fd0825,
882 0x16018005,
883 0x083c87f1,
884 0xbd0684b6,
885 0x0999f094,
886 0xf10089d0,
887 0xb60a0427,
888 0x21d00624,
889 0x0127f000,
890 0x0a2017f1,
728 0xd00614b6, 891 0xd00614b6,
729 0x17f10012, 892 0x17f10012,
730 0x14b60a20, 893 0x13f00100,
731 0x0227f006, 894 0x0501fa06,
732 0x800023f1,
733 0xf00012d0,
734 0x27f11017,
735 0x23f00300,
736 0x0512fa02,
737 0x87f103f8, 895 0x87f103f8,
738 0x84b6085c, 896 0x84b6085c,
739 0xf094bd06, 897 0xf094bd06,
740 0x89d00899, 898 0x89d00999,
741 0xc1019800, 899 0x5c87f100,
742 0x981814b6,
743 0x25b6c002,
744 0x0512fd08,
745 0xf1160180,
746 0xb6083c87,
747 0x94bd0684,
748 0xd00999f0,
749 0x27f10089,
750 0x24b60a04,
751 0x0021d006,
752 0xf10127f0,
753 0xb60a2017,
754 0x12d00614,
755 0x0017f100,
756 0x0613f002,
757 0xf80501fa,
758 0x5c87f103,
759 0x0684b608, 900 0x0684b608,
760 0x99f094bd, 901 0x99f094bd,
761 0x0089d009, 902 0x0089d005,
762 0x085c87f1, 903/* 0x07b6: ctx_chan */
763 0xbd0684b6, 904 0x21f500f8,
764 0x0599f094, 905 0x21f50632,
765 0xf80089d0, 906 0xa7f006b9,
766/* 0x07b5: ctx_chan */ 907 0xc921f40c,
767 0x3121f500, 908 0x0a1017f1,
768 0xb821f506, 909 0xf00614b6,
769 0x0ca7f006, 910 0x12d00527,
770 0xf1c921f4, 911/* 0x07d1: ctx_chan_wait */
771 0xb60a1017, 912 0x0012cf00,
772 0x27f00614, 913 0xf40522fd,
773 0x0012d005, 914 0x21f5fa1b,
774/* 0x07d0: ctx_chan_wait */ 915 0x00f8064a,
775 0xfd0012cf, 916/* 0x07e0: ctx_mmio_exec */
776 0x1bf40522, 917 0xf1410398,
777 0x4921f5fa, 918 0xb60a0427,
778/* 0x07df: ctx_mmio_exec */ 919 0x23d00624,
779 0x9800f806, 920/* 0x07ef: ctx_mmio_loop */
780 0x27f18103, 921 0xc434bd00,
781 0x24b60a04, 922 0x1bf4ff34,
782 0x0023d006, 923 0x0057f10f,
783/* 0x07ee: ctx_mmio_loop */ 924 0x0653f002,
784 0x34c434bd, 925 0xf80535fa,
785 0x0f1bf4ff, 926/* 0x0801: ctx_mmio_pull */
786 0x030057f1, 927 0x804e9803,
787 0xfa0653f0, 928 0xf4814f98,
788 0x03f80535, 929 0x30b68d21,
789/* 0x0800: ctx_mmio_pull */ 930 0x0112b608,
790 0x98c04e98, 931/* 0x0813: ctx_mmio_done */
791 0x21f4c14f, 932 0x98df1bf4,
792 0x0830b68d, 933 0x23d01603,
793 0xf40112b6, 934 0x40008000,
794/* 0x0812: ctx_mmio_done */ 935 0x010017f1,
795 0x0398df1b, 936 0xfa0613f0,
796 0x0023d016, 937 0x03f80601,
797 0xf1800080, 938/* 0x082a: ctx_xfer */
798 0xf0020017, 939 0xf7f100f8,
799 0x01fa0613, 940 0xf4b60c00,
800 0xf803f806, 941 0x04e7f006,
801/* 0x0829: ctx_xfer */ 942/* 0x0837: ctx_xfer_idle */
802 0x00f7f100, 943 0xcf80fed0,
803 0x06f4b60c, 944 0xe4f100fe,
804 0xd004e7f0, 945 0x1bf42000,
805/* 0x0836: ctx_xfer_idle */ 946 0x0611f4f9,
806 0xfecf80fe, 947/* 0x0847: ctx_xfer_pre */
807 0x00e4f100, 948 0xf01102f4,
808 0xf91bf420, 949 0x21f510f7,
809 0xf40611f4, 950 0x21f50699,
810/* 0x0846: ctx_xfer_pre */ 951 0x11f40632,
811 0xf7f01102, 952/* 0x0855: ctx_xfer_pre_load */
812 0x9821f510, 953 0x02f7f01c,
813 0x3121f506, 954 0x065821f5,
814 0x1c11f406, 955 0x066721f5,
815/* 0x0854: ctx_xfer_pre_load */ 956 0x067921f5,
816 0xf502f7f0, 957 0x21f5f4bd,
817 0xf5065721, 958 0x21f50658,
818 0xf5066621, 959/* 0x086e: ctx_xfer_exec */
819 0xbd067821, 960 0x019806b9,
820 0x5721f5f4, 961 0x1427f116,
821 0xb821f506, 962 0x0624b604,
822/* 0x086d: ctx_xfer_exec */ 963 0xf10020d0,
823 0x16019806, 964 0xf0a500e7,
824 0x041427f1, 965 0x1fb941e3,
825 0xd00624b6, 966 0x8d21f402,
826 0xe7f10020, 967 0xf004e0b6,
827 0xe3f0a500, 968 0x2cf001fc,
828 0x021fb941, 969 0x0124b602,
829 0xb68d21f4, 970 0xf405f2fd,
830 0xfcf004e0, 971 0x17f18d21,
831 0x022cf001, 972 0x13f04afc,
832 0xfd0124b6, 973 0x0c27f002,
833 0x21f405f2, 974 0xf50012d0,
834 0xfc17f18d, 975 0xf1020721,
835 0x0213f04a, 976 0xf047fc27,
836 0xd00c27f0, 977 0x20d00223,
837 0x21f50012, 978 0x012cf000,
838 0x27f10207, 979 0xd00320b6,
839 0x23f047fc, 980 0xacf00012,
840 0x0020d002, 981 0x06a5f001,
841 0xb6012cf0, 982 0x9800b7f0,
842 0x12d00320, 983 0x0d98140c,
843 0x01acf000, 984 0x00e7f015,
844 0xf006a5f0, 985 0x015c21f5,
845 0x0c9800b7, 986 0xf508a7f0,
846 0x150d9814, 987 0xf5010321,
847 0xf500e7f0, 988 0xf4020721,
848 0xf0015c21, 989 0xa7f02201,
849 0x21f508a7, 990 0xc921f40c,
850 0x21f50103, 991 0x0a1017f1,
851 0x01f40207, 992 0xf00614b6,
852 0x0ca7f022, 993 0x12d00527,
853 0xf1c921f4, 994/* 0x08f5: ctx_xfer_post_save_wait */
854 0xb60a1017, 995 0x0012cf00,
855 0x27f00614, 996 0xf40522fd,
856 0x0012d005, 997 0x02f4fa1b,
857/* 0x08f4: ctx_xfer_post_save_wait */ 998/* 0x0901: ctx_xfer_post */
858 0xfd0012cf, 999 0x02f7f032,
859 0x1bf40522, 1000 0x065821f5,
860 0x3202f4fa, 1001 0x21f5f4bd,
861/* 0x0900: ctx_xfer_post */ 1002 0x21f50699,
862 0xf502f7f0, 1003 0x21f50226,
863 0xbd065721, 1004 0xf4bd0667,
864 0x9821f5f4, 1005 0x065821f5,
865 0x2621f506, 1006 0x981011f4,
866 0x6621f502, 1007 0x11fd4001,
867 0xf5f4bd06, 1008 0x070bf405,
868 0xf4065721, 1009 0x07e021f5,
869 0x01981011, 1010/* 0x092c: ctx_xfer_no_post_mmio */
870 0x0511fd80, 1011 0x064a21f5,
871 0xf5070bf4, 1012/* 0x0930: ctx_xfer_done */
872/* 0x092b: ctx_xfer_no_post_mmio */ 1013 0x000000f8,
873 0xf507df21,
874/* 0x092f: ctx_xfer_done */
875 0xf8064921,
876 0x00000000,
877 0x00000000, 1014 0x00000000,
878 0x00000000, 1015 0x00000000,
879 0x00000000, 1016 0x00000000,
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
index 766870c4a27c..9d705bab9dcd 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
@@ -745,9 +745,17 @@ nvc0_graph_init_unk60xx(struct nvc0_graph_priv *priv)
745static void 745static void
746nvc0_graph_init_unk64xx(struct nvc0_graph_priv *priv) 746nvc0_graph_init_unk64xx(struct nvc0_graph_priv *priv)
747{ 747{
748 nv_wr32(priv, 0x4064f0, 0x00000000); 748 switch (nv_device(priv)->chipset) {
749 nv_wr32(priv, 0x4064f4, 0x00000000); 749 case 0xd9:
750 nv_wr32(priv, 0x4064f8, 0x00000000); 750 case 0xd7:
751 nv_wr32(priv, 0x4064f0, 0x00000000);
752 nv_wr32(priv, 0x4064f4, 0x00000000);
753 nv_wr32(priv, 0x4064f8, 0x00000000);
754 break;
755 case 0xc0:
756 default:
757 break;
758 }
751} 759}
752 760
753static void 761static void
@@ -755,10 +763,26 @@ nvc0_graph_init_unk58xx(struct nvc0_graph_priv *priv)
755{ 763{
756 nv_wr32(priv, 0x405844, 0x00ffffff); 764 nv_wr32(priv, 0x405844, 0x00ffffff);
757 nv_wr32(priv, 0x405850, 0x00000000); 765 nv_wr32(priv, 0x405850, 0x00000000);
758 nv_wr32(priv, 0x405900, 0x00002834); 766 switch (nv_device(priv)->chipset) {
767 case 0xd9:
768 case 0xd7:
769 nv_wr32(priv, 0x405900, 0x00002834);
770 break;
771 case 0xc0:
772 default:
773 break;
774 }
759 nv_wr32(priv, 0x405908, 0x00000000); 775 nv_wr32(priv, 0x405908, 0x00000000);
760 nv_wr32(priv, 0x405928, 0x00000000); 776 switch (nv_device(priv)->chipset) {
761 nv_wr32(priv, 0x40592c, 0x00000000); 777 case 0xd9:
778 case 0xd7:
779 nv_wr32(priv, 0x405928, 0x00000000);
780 nv_wr32(priv, 0x40592c, 0x00000000);
781 break;
782 case 0xc0:
783 default:
784 break;
785 }
762} 786}
763 787
764static void 788static void
@@ -770,19 +794,53 @@ nvc0_graph_init_unk80xx(struct nvc0_graph_priv *priv)
770static void 794static void
771nvc0_graph_init_gpc(struct nvc0_graph_priv *priv) 795nvc0_graph_init_gpc(struct nvc0_graph_priv *priv)
772{ 796{
773 nv_wr32(priv, 0x418408, 0x00000000); 797 switch (nv_device(priv)->chipset) {
798 case 0xd9:
799 case 0xd7:
800 nv_wr32(priv, 0x418408, 0x00000000);
801 break;
802 case 0xc0:
803 default:
804 break;
805 }
774 nv_wr32(priv, 0x4184a0, 0x00000000); 806 nv_wr32(priv, 0x4184a0, 0x00000000);
775 nv_wr32(priv, 0x4184a4, 0x00000000); 807 switch (nv_device(priv)->chipset) {
776 nv_wr32(priv, 0x4184a8, 0x00000000); 808 case 0xd9:
809 case 0xd7:
810 nv_wr32(priv, 0x4184a4, 0x00000000);
811 nv_wr32(priv, 0x4184a8, 0x00000000);
812 break;
813 case 0xc0:
814 default:
815 break;
816 }
777 nv_wr32(priv, 0x418604, 0x00000000); 817 nv_wr32(priv, 0x418604, 0x00000000);
778 nv_wr32(priv, 0x418680, 0x00000000); 818 nv_wr32(priv, 0x418680, 0x00000000);
779 nv_wr32(priv, 0x418714, 0x00000000); 819 switch (nv_device(priv)->chipset) {
820 case 0xd9:
821 case 0xd7:
822 nv_wr32(priv, 0x418714, 0x00000000);
823 break;
824 case 0xc0:
825 default:
826 nv_wr32(priv, 0x418714, 0x80000000);
827 break;
828 }
780 nv_wr32(priv, 0x418384, 0x00000000); 829 nv_wr32(priv, 0x418384, 0x00000000);
781 nv_wr32(priv, 0x418814, 0x00000000); 830 nv_wr32(priv, 0x418814, 0x00000000);
782 nv_wr32(priv, 0x418818, 0x00000000); 831 nv_wr32(priv, 0x418818, 0x00000000);
783 nv_wr32(priv, 0x41881c, 0x00000000); 832 nv_wr32(priv, 0x41881c, 0x00000000);
784 nv_wr32(priv, 0x418b04, 0x00000000); 833 nv_wr32(priv, 0x418b04, 0x00000000);
785 nv_wr32(priv, 0x4188c8, 0x00000000); 834 switch (nv_device(priv)->chipset) {
835 case 0xd9:
836 case 0xd7:
837 nv_wr32(priv, 0x4188c8, 0x00000000);
838 break;
839 case 0xc0:
840 default:
841 nv_wr32(priv, 0x4188c8, 0x80000000);
842 break;
843 }
786 nv_wr32(priv, 0x4188cc, 0x00000000); 844 nv_wr32(priv, 0x4188cc, 0x00000000);
787 nv_wr32(priv, 0x4188d0, 0x00010000); 845 nv_wr32(priv, 0x4188d0, 0x00010000);
788 nv_wr32(priv, 0x4188d4, 0x00000001); 846 nv_wr32(priv, 0x4188d4, 0x00000001);
@@ -794,22 +852,63 @@ nvc0_graph_init_gpc(struct nvc0_graph_priv *priv)
794 nv_wr32(priv, 0x418988, 0x77777777); 852 nv_wr32(priv, 0x418988, 0x77777777);
795 nv_wr32(priv, 0x41898c, 0x77777777); 853 nv_wr32(priv, 0x41898c, 0x77777777);
796 nv_wr32(priv, 0x418c04, 0x00000000); 854 nv_wr32(priv, 0x418c04, 0x00000000);
797 nv_wr32(priv, 0x418c64, 0x00000000); 855 switch (nv_device(priv)->chipset) {
798 nv_wr32(priv, 0x418c68, 0x00000000); 856 case 0xd9:
857 case 0xd7:
858 nv_wr32(priv, 0x418c64, 0x00000000);
859 nv_wr32(priv, 0x418c68, 0x00000000);
860 break;
861 case 0xc0:
862 default:
863 break;
864 }
799 nv_wr32(priv, 0x418c88, 0x00000000); 865 nv_wr32(priv, 0x418c88, 0x00000000);
800 nv_wr32(priv, 0x418cb4, 0x00000000); 866 switch (nv_device(priv)->chipset) {
801 nv_wr32(priv, 0x418cb8, 0x00000000); 867 case 0xd9:
868 case 0xd7:
869 nv_wr32(priv, 0x418cb4, 0x00000000);
870 nv_wr32(priv, 0x418cb8, 0x00000000);
871 break;
872 case 0xc0:
873 default:
874 break;
875 }
802 nv_wr32(priv, 0x418d00, 0x00000000); 876 nv_wr32(priv, 0x418d00, 0x00000000);
803 nv_wr32(priv, 0x418d28, 0x00000000); 877 switch (nv_device(priv)->chipset) {
804 nv_wr32(priv, 0x418d2c, 0x00000000); 878 case 0xd9:
805 nv_wr32(priv, 0x418f00, 0x00000000); 879 case 0xd7:
880 nv_wr32(priv, 0x418d28, 0x00000000);
881 nv_wr32(priv, 0x418d2c, 0x00000000);
882 nv_wr32(priv, 0x418f00, 0x00000000);
883 break;
884 case 0xc0:
885 default:
886 break;
887 }
806 nv_wr32(priv, 0x418f08, 0x00000000); 888 nv_wr32(priv, 0x418f08, 0x00000000);
807 nv_wr32(priv, 0x418f20, 0x00000000); 889 switch (nv_device(priv)->chipset) {
808 nv_wr32(priv, 0x418f24, 0x00000000); 890 case 0xd9:
809 nv_wr32(priv, 0x418e00, 0x00000003); 891 case 0xd7:
892 nv_wr32(priv, 0x418f20, 0x00000000);
893 nv_wr32(priv, 0x418f24, 0x00000000);
894 nv_wr32(priv, 0x418e00, 0x00000003);
895 break;
896 case 0xc0:
897 default:
898 nv_wr32(priv, 0x418e00, 0x00000050);
899 break;
900 }
810 nv_wr32(priv, 0x418e08, 0x00000000); 901 nv_wr32(priv, 0x418e08, 0x00000000);
811 nv_wr32(priv, 0x418e1c, 0x00000000); 902 switch (nv_device(priv)->chipset) {
812 nv_wr32(priv, 0x418e20, 0x00000000); 903 case 0xd9:
904 case 0xd7:
905 nv_wr32(priv, 0x418e1c, 0x00000000);
906 nv_wr32(priv, 0x418e20, 0x00000000);
907 break;
908 case 0xc0:
909 default:
910 break;
911 }
813 nv_wr32(priv, 0x41900c, 0x00000000); 912 nv_wr32(priv, 0x41900c, 0x00000000);
814 nv_wr32(priv, 0x419018, 0x00000000); 913 nv_wr32(priv, 0x419018, 0x00000000);
815} 914}
@@ -821,21 +920,64 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv)
821 nv_wr32(priv, 0x419d0c, 0x00000000); 920 nv_wr32(priv, 0x419d0c, 0x00000000);
822 nv_wr32(priv, 0x419d10, 0x00000014); 921 nv_wr32(priv, 0x419d10, 0x00000014);
823 nv_wr32(priv, 0x419ab0, 0x00000000); 922 nv_wr32(priv, 0x419ab0, 0x00000000);
824 nv_wr32(priv, 0x419ac8, 0x00000000); 923 switch (nv_device(priv)->chipset) {
924 case 0xd9:
925 case 0xd7:
926 nv_wr32(priv, 0x419ac8, 0x00000000);
927 break;
928 case 0xc0:
929 default:
930 break;
931 }
825 nv_wr32(priv, 0x419ab8, 0x000000e7); 932 nv_wr32(priv, 0x419ab8, 0x000000e7);
826 nv_wr32(priv, 0x419abc, 0x00000000); 933 nv_wr32(priv, 0x419abc, 0x00000000);
827 nv_wr32(priv, 0x419ac0, 0x00000000); 934 nv_wr32(priv, 0x419ac0, 0x00000000);
828 nv_wr32(priv, 0x419ab4, 0x00000000); 935 switch (nv_device(priv)->chipset) {
829 nv_wr32(priv, 0x41980c, 0x00000010); 936 case 0xd9:
937 case 0xd7:
938 nv_wr32(priv, 0x419ab4, 0x00000000);
939 nv_wr32(priv, 0x41980c, 0x00000010);
940 break;
941 case 0xc0:
942 default:
943 nv_wr32(priv, 0x41980c, 0x00000000);
944 break;
945 }
830 nv_wr32(priv, 0x419810, 0x00000000); 946 nv_wr32(priv, 0x419810, 0x00000000);
831 nv_wr32(priv, 0x419814, 0x00000004); 947 switch (nv_device(priv)->chipset) {
948 case 0xd9:
949 case 0xd7:
950 nv_wr32(priv, 0x419814, 0x00000004);
951 break;
952 case 0xc0:
953 default:
954 nv_wr32(priv, 0x419814, 0x00000000);
955 break;
956 }
832 nv_wr32(priv, 0x419844, 0x00000000); 957 nv_wr32(priv, 0x419844, 0x00000000);
833 nv_wr32(priv, 0x41984c, 0x0000a918); 958 switch (nv_device(priv)->chipset) {
959 case 0xd9:
960 case 0xd7:
961 nv_wr32(priv, 0x41984c, 0x0000a918);
962 break;
963 case 0xc0:
964 default:
965 nv_wr32(priv, 0x41984c, 0x00005bc5);
966 break;
967 }
834 nv_wr32(priv, 0x419850, 0x00000000); 968 nv_wr32(priv, 0x419850, 0x00000000);
835 nv_wr32(priv, 0x419854, 0x00000000); 969 nv_wr32(priv, 0x419854, 0x00000000);
836 nv_wr32(priv, 0x419858, 0x00000000); 970 nv_wr32(priv, 0x419858, 0x00000000);
837 nv_wr32(priv, 0x41985c, 0x00000000); 971 nv_wr32(priv, 0x41985c, 0x00000000);
838 nv_wr32(priv, 0x419880, 0x00000002); 972 switch (nv_device(priv)->chipset) {
973 case 0xd9:
974 case 0xd7:
975 nv_wr32(priv, 0x419880, 0x00000002);
976 break;
977 case 0xc0:
978 default:
979 break;
980 }
839 nv_wr32(priv, 0x419c98, 0x00000000); 981 nv_wr32(priv, 0x419c98, 0x00000000);
840 nv_wr32(priv, 0x419ca8, 0x80000000); 982 nv_wr32(priv, 0x419ca8, 0x80000000);
841 nv_wr32(priv, 0x419cb4, 0x00000000); 983 nv_wr32(priv, 0x419cb4, 0x00000000);
@@ -845,25 +987,60 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv)
845 nv_wr32(priv, 0x419cc4, 0x00000000); 987 nv_wr32(priv, 0x419cc4, 0x00000000);
846 nv_wr32(priv, 0x419bd4, 0x00800000); 988 nv_wr32(priv, 0x419bd4, 0x00800000);
847 nv_wr32(priv, 0x419bdc, 0x00000000); 989 nv_wr32(priv, 0x419bdc, 0x00000000);
848 nv_wr32(priv, 0x419bf8, 0x00000000); 990 switch (nv_device(priv)->chipset) {
849 nv_wr32(priv, 0x419bfc, 0x00000000); 991 case 0xd9:
992 case 0xd7:
993 nv_wr32(priv, 0x419bf8, 0x00000000);
994 nv_wr32(priv, 0x419bfc, 0x00000000);
995 break;
996 case 0xc0:
997 default:
998 break;
999 }
850 nv_wr32(priv, 0x419d2c, 0x00000000); 1000 nv_wr32(priv, 0x419d2c, 0x00000000);
851 nv_wr32(priv, 0x419d48, 0x00000000); 1001 switch (nv_device(priv)->chipset) {
852 nv_wr32(priv, 0x419d4c, 0x00000000); 1002 case 0xd9:
1003 case 0xd7:
1004 nv_wr32(priv, 0x419d48, 0x00000000);
1005 nv_wr32(priv, 0x419d4c, 0x00000000);
1006 break;
1007 case 0xc0:
1008 default:
1009 break;
1010 }
853 nv_wr32(priv, 0x419c0c, 0x00000000); 1011 nv_wr32(priv, 0x419c0c, 0x00000000);
854 nv_wr32(priv, 0x419e00, 0x00000000); 1012 nv_wr32(priv, 0x419e00, 0x00000000);
855 nv_wr32(priv, 0x419ea0, 0x00000000); 1013 nv_wr32(priv, 0x419ea0, 0x00000000);
856 nv_wr32(priv, 0x419ea4, 0x00000100); 1014 nv_wr32(priv, 0x419ea4, 0x00000100);
857 nv_wr32(priv, 0x419ea8, 0x02001100); 1015 switch (nv_device(priv)->chipset) {
1016 case 0xd9:
1017 case 0xd7:
1018 nv_wr32(priv, 0x419ea8, 0x02001100);
1019 break;
1020 case 0xc0:
1021 default:
1022 nv_wr32(priv, 0x419ea8, 0x00001100);
1023 break;
1024 }
858 nv_wr32(priv, 0x419eac, 0x11100702); 1025 nv_wr32(priv, 0x419eac, 0x11100702);
859 nv_wr32(priv, 0x419eb0, 0x00000003); 1026 nv_wr32(priv, 0x419eb0, 0x00000003);
860 nv_wr32(priv, 0x419eb4, 0x00000000); 1027 nv_wr32(priv, 0x419eb4, 0x00000000);
861 nv_wr32(priv, 0x419eb8, 0x00000000); 1028 nv_wr32(priv, 0x419eb8, 0x00000000);
862 nv_wr32(priv, 0x419ebc, 0x00000000); 1029 nv_wr32(priv, 0x419ebc, 0x00000000);
863 nv_wr32(priv, 0x419ec0, 0x00000000); 1030 nv_wr32(priv, 0x419ec0, 0x00000000);
864 nv_wr32(priv, 0x419ec8, 0x0e063818); 1031 switch (nv_device(priv)->chipset) {
865 nv_wr32(priv, 0x419ecc, 0x0e060e06); 1032 case 0xd9:
866 nv_wr32(priv, 0x419ed0, 0x00003818); 1033 case 0xd7:
1034 nv_wr32(priv, 0x419ec8, 0x0e063818);
1035 nv_wr32(priv, 0x419ecc, 0x0e060e06);
1036 nv_wr32(priv, 0x419ed0, 0x00003818);
1037 break;
1038 case 0xc0:
1039 default:
1040 nv_wr32(priv, 0x419ec8, 0x06060618);
1041 nv_wr32(priv, 0x419ed0, 0x0eff0e38);
1042 break;
1043 }
867 nv_wr32(priv, 0x419ed4, 0x011104f1); 1044 nv_wr32(priv, 0x419ed4, 0x011104f1);
868 nv_wr32(priv, 0x419edc, 0x00000000); 1045 nv_wr32(priv, 0x419edc, 0x00000000);
869 nv_wr32(priv, 0x419f00, 0x00000000); 1046 nv_wr32(priv, 0x419f00, 0x00000000);
@@ -1133,6 +1310,7 @@ nvc0_graph_init(struct nouveau_object *object)
1133 nvc0_graph_init_regs(priv); 1310 nvc0_graph_init_regs(priv);
1134 1311
1135 switch (nv_device(priv)->chipset) { 1312 switch (nv_device(priv)->chipset) {
1313 case 0xc0:
1136 case 0xd9: 1314 case 0xd9:
1137 case 0xd7: 1315 case 0xd7:
1138 nvc0_graph_init_unk40xx(priv); 1316 nvc0_graph_init_unk40xx(priv);
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-15 17:10:00 -0400