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-rw-r--r--drivers/gpu/drm/nouveau/Makefile1
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/device/base.c3
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/device/nve0.c34
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/disp/nvf0.c89
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/dmaobj/nvd0.c3
-rw-r--r--drivers/gpu/drm/nouveau/core/include/core/class.h12
-rw-r--r--drivers/gpu/drm/nouveau/core/include/engine/disp.h1
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_drm.c3
-rw-r--r--drivers/gpu/drm/nouveau/nv50_display.c1
-rw-r--r--drivers/gpu/drm/radeon/atom.c6
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c103
-rw-r--r--drivers/gpu/drm/radeon/evergreend.h2
-rw-r--r--drivers/gpu/drm/radeon/ni.c6
-rw-r--r--drivers/gpu/drm/radeon/r600d.h4
-rw-r--r--drivers/gpu/drm/radeon/radeon.h16
-rw-r--r--drivers/gpu/drm/radeon/radeon_atombios.c27
-rw-r--r--drivers/gpu/drm/radeon/radeon_device.c5
-rw-r--r--drivers/gpu/drm/radeon/radeon_fence.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_gem.c50
-rw-r--r--drivers/gpu/drm/radeon/radeon_sa.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_uvd.c137
-rw-r--r--drivers/gpu/drm/radeon/rv770.c110
-rw-r--r--drivers/gpu/drm/radeon/rv770d.h2
-rw-r--r--drivers/gpu/drm/radeon/si.c104
-rw-r--r--drivers/gpu/drm/radeon/sid.h2
-rw-r--r--drivers/video/omap2/Makefile2
-rw-r--r--drivers/video/omap2/displays/panel-tfp410.c2
-rw-r--r--drivers/video/omap2/dss/dpi.c35
-rw-r--r--drivers/video/omap2/dss/dsi.c35
-rw-r--r--drivers/video/omap2/dss/dss.h31
-rw-r--r--drivers/video/omap2/dss/hdmi.c33
-rw-r--r--drivers/video/omap2/dss/rfbi.c32
-rw-r--r--drivers/video/omap2/dss/sdi.c33
-rw-r--r--drivers/video/omap2/dss/venc.c33
-rw-r--r--drivers/video/omap2/omapfb/omapfb-main.c30
-rw-r--r--include/drm/drm_pciids.h5
36 files changed, 589 insertions, 407 deletions
diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile
index 52930a20d8f8..998e8b4444f3 100644
--- a/drivers/gpu/drm/nouveau/Makefile
+++ b/drivers/gpu/drm/nouveau/Makefile
@@ -160,6 +160,7 @@ nouveau-y += core/engine/disp/nva0.o
160nouveau-y += core/engine/disp/nva3.o 160nouveau-y += core/engine/disp/nva3.o
161nouveau-y += core/engine/disp/nvd0.o 161nouveau-y += core/engine/disp/nvd0.o
162nouveau-y += core/engine/disp/nve0.o 162nouveau-y += core/engine/disp/nve0.o
163nouveau-y += core/engine/disp/nvf0.o
163nouveau-y += core/engine/disp/dacnv50.o 164nouveau-y += core/engine/disp/dacnv50.o
164nouveau-y += core/engine/disp/dport.o 165nouveau-y += core/engine/disp/dport.o
165nouveau-y += core/engine/disp/hdanva3.o 166nouveau-y += core/engine/disp/hdanva3.o
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/base.c b/drivers/gpu/drm/nouveau/core/engine/device/base.c
index 86d24904e9d3..4c72571655ad 100644
--- a/drivers/gpu/drm/nouveau/core/engine/device/base.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/base.c
@@ -172,7 +172,8 @@ nouveau_devobj_ctor(struct nouveau_object *parent,
172 case 0xa0: device->card_type = NV_50; break; 172 case 0xa0: device->card_type = NV_50; break;
173 case 0xc0: device->card_type = NV_C0; break; 173 case 0xc0: device->card_type = NV_C0; break;
174 case 0xd0: device->card_type = NV_D0; break; 174 case 0xd0: device->card_type = NV_D0; break;
175 case 0xe0: device->card_type = NV_E0; break; 175 case 0xe0:
176 case 0xf0: device->card_type = NV_E0; break;
176 default: 177 default:
177 break; 178 break;
178 } 179 }
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c b/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
index e6a77944f43b..a354e409cdff 100644
--- a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
@@ -141,6 +141,40 @@ nve0_identify(struct nouveau_device *device)
141 device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; 141 device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
142 device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; 142 device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
143 break; 143 break;
144 case 0xf0:
145 device->cname = "GK110";
146 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
147 device->oclass[NVDEV_SUBDEV_GPIO ] = &nve0_gpio_oclass;
148 device->oclass[NVDEV_SUBDEV_I2C ] = &nvd0_i2c_oclass;
149 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
150 device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
151 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
152 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
153 device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
154 device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass;
155 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
156 device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
157 device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
158 device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
159 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
160 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
161 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
162 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
163#if 0
164 device->oclass[NVDEV_ENGINE_FIFO ] = &nve0_fifo_oclass;
165 device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
166 device->oclass[NVDEV_ENGINE_GR ] = &nve0_graph_oclass;
167#endif
168 device->oclass[NVDEV_ENGINE_DISP ] = &nvf0_disp_oclass;
169#if 0
170 device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
171 device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass;
172 device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass;
173 device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass;
174 device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
175 device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
176#endif
177 break;
144 default: 178 default:
145 nv_fatal(device, "unknown Kepler chipset\n"); 179 nv_fatal(device, "unknown Kepler chipset\n");
146 return -EINVAL; 180 return -EINVAL;
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nvf0.c b/drivers/gpu/drm/nouveau/core/engine/disp/nvf0.c
new file mode 100644
index 000000000000..a488c36e40f9
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nvf0.c
@@ -0,0 +1,89 @@
1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include <engine/software.h>
26#include <engine/disp.h>
27
28#include <core/class.h>
29
30#include "nv50.h"
31
32static struct nouveau_oclass
33nvf0_disp_sclass[] = {
34 { NVF0_DISP_MAST_CLASS, &nvd0_disp_mast_ofuncs },
35 { NVF0_DISP_SYNC_CLASS, &nvd0_disp_sync_ofuncs },
36 { NVF0_DISP_OVLY_CLASS, &nvd0_disp_ovly_ofuncs },
37 { NVF0_DISP_OIMM_CLASS, &nvd0_disp_oimm_ofuncs },
38 { NVF0_DISP_CURS_CLASS, &nvd0_disp_curs_ofuncs },
39 {}
40};
41
42static struct nouveau_oclass
43nvf0_disp_base_oclass[] = {
44 { NVF0_DISP_CLASS, &nvd0_disp_base_ofuncs, nva3_disp_base_omthds },
45 {}
46};
47
48static int
49nvf0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
50 struct nouveau_oclass *oclass, void *data, u32 size,
51 struct nouveau_object **pobject)
52{
53 struct nv50_disp_priv *priv;
54 int heads = nv_rd32(parent, 0x022448);
55 int ret;
56
57 ret = nouveau_disp_create(parent, engine, oclass, heads,
58 "PDISP", "display", &priv);
59 *pobject = nv_object(priv);
60 if (ret)
61 return ret;
62
63 nv_engine(priv)->sclass = nvf0_disp_base_oclass;
64 nv_engine(priv)->cclass = &nv50_disp_cclass;
65 nv_subdev(priv)->intr = nvd0_disp_intr;
66 INIT_WORK(&priv->supervisor, nvd0_disp_intr_supervisor);
67 priv->sclass = nvf0_disp_sclass;
68 priv->head.nr = heads;
69 priv->dac.nr = 3;
70 priv->sor.nr = 4;
71 priv->dac.power = nv50_dac_power;
72 priv->dac.sense = nv50_dac_sense;
73 priv->sor.power = nv50_sor_power;
74 priv->sor.hda_eld = nvd0_hda_eld;
75 priv->sor.hdmi = nvd0_hdmi_ctrl;
76 priv->sor.dp = &nvd0_sor_dp_func;
77 return 0;
78}
79
80struct nouveau_oclass
81nvf0_disp_oclass = {
82 .handle = NV_ENGINE(DISP, 0x92),
83 .ofuncs = &(struct nouveau_ofuncs) {
84 .ctor = nvf0_disp_ctor,
85 .dtor = _nouveau_disp_dtor,
86 .init = _nouveau_disp_init,
87 .fini = _nouveau_disp_fini,
88 },
89};
diff --git a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nvd0.c b/drivers/gpu/drm/nouveau/core/engine/dmaobj/nvd0.c
index d1528752980c..944e73ac485c 100644
--- a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nvd0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/dmaobj/nvd0.c
@@ -50,6 +50,9 @@ nvd0_dmaobj_bind(struct nouveau_dmaeng *dmaeng,
50 case NVE0_DISP_MAST_CLASS: 50 case NVE0_DISP_MAST_CLASS:
51 case NVE0_DISP_SYNC_CLASS: 51 case NVE0_DISP_SYNC_CLASS:
52 case NVE0_DISP_OVLY_CLASS: 52 case NVE0_DISP_OVLY_CLASS:
53 case NVF0_DISP_MAST_CLASS:
54 case NVF0_DISP_SYNC_CLASS:
55 case NVF0_DISP_OVLY_CLASS:
53 break; 56 break;
54 default: 57 default:
55 return -EINVAL; 58 return -EINVAL;
diff --git a/drivers/gpu/drm/nouveau/core/include/core/class.h b/drivers/gpu/drm/nouveau/core/include/core/class.h
index 92d3ab11d962..0a393f7f055f 100644
--- a/drivers/gpu/drm/nouveau/core/include/core/class.h
+++ b/drivers/gpu/drm/nouveau/core/include/core/class.h
@@ -169,6 +169,7 @@ struct nv04_display_class {
169 * 8570: NVA3_DISP 169 * 8570: NVA3_DISP
170 * 9070: NVD0_DISP 170 * 9070: NVD0_DISP
171 * 9170: NVE0_DISP 171 * 9170: NVE0_DISP
172 * 9270: NVF0_DISP
172 */ 173 */
173 174
174#define NV50_DISP_CLASS 0x00005070 175#define NV50_DISP_CLASS 0x00005070
@@ -178,6 +179,7 @@ struct nv04_display_class {
178#define NVA3_DISP_CLASS 0x00008570 179#define NVA3_DISP_CLASS 0x00008570
179#define NVD0_DISP_CLASS 0x00009070 180#define NVD0_DISP_CLASS 0x00009070
180#define NVE0_DISP_CLASS 0x00009170 181#define NVE0_DISP_CLASS 0x00009170
182#define NVF0_DISP_CLASS 0x00009270
181 183
182#define NV50_DISP_SOR_MTHD 0x00010000 184#define NV50_DISP_SOR_MTHD 0x00010000
183#define NV50_DISP_SOR_MTHD_TYPE 0x0000f000 185#define NV50_DISP_SOR_MTHD_TYPE 0x0000f000
@@ -246,6 +248,7 @@ struct nv50_display_class {
246 * 857a: NVA3_DISP_CURS 248 * 857a: NVA3_DISP_CURS
247 * 907a: NVD0_DISP_CURS 249 * 907a: NVD0_DISP_CURS
248 * 917a: NVE0_DISP_CURS 250 * 917a: NVE0_DISP_CURS
251 * 927a: NVF0_DISP_CURS
249 */ 252 */
250 253
251#define NV50_DISP_CURS_CLASS 0x0000507a 254#define NV50_DISP_CURS_CLASS 0x0000507a
@@ -255,6 +258,7 @@ struct nv50_display_class {
255#define NVA3_DISP_CURS_CLASS 0x0000857a 258#define NVA3_DISP_CURS_CLASS 0x0000857a
256#define NVD0_DISP_CURS_CLASS 0x0000907a 259#define NVD0_DISP_CURS_CLASS 0x0000907a
257#define NVE0_DISP_CURS_CLASS 0x0000917a 260#define NVE0_DISP_CURS_CLASS 0x0000917a
261#define NVF0_DISP_CURS_CLASS 0x0000927a
258 262
259struct nv50_display_curs_class { 263struct nv50_display_curs_class {
260 u32 head; 264 u32 head;
@@ -267,6 +271,7 @@ struct nv50_display_curs_class {
267 * 857b: NVA3_DISP_OIMM 271 * 857b: NVA3_DISP_OIMM
268 * 907b: NVD0_DISP_OIMM 272 * 907b: NVD0_DISP_OIMM
269 * 917b: NVE0_DISP_OIMM 273 * 917b: NVE0_DISP_OIMM
274 * 927b: NVE0_DISP_OIMM
270 */ 275 */
271 276
272#define NV50_DISP_OIMM_CLASS 0x0000507b 277#define NV50_DISP_OIMM_CLASS 0x0000507b
@@ -276,6 +281,7 @@ struct nv50_display_curs_class {
276#define NVA3_DISP_OIMM_CLASS 0x0000857b 281#define NVA3_DISP_OIMM_CLASS 0x0000857b
277#define NVD0_DISP_OIMM_CLASS 0x0000907b 282#define NVD0_DISP_OIMM_CLASS 0x0000907b
278#define NVE0_DISP_OIMM_CLASS 0x0000917b 283#define NVE0_DISP_OIMM_CLASS 0x0000917b
284#define NVF0_DISP_OIMM_CLASS 0x0000927b
279 285
280struct nv50_display_oimm_class { 286struct nv50_display_oimm_class {
281 u32 head; 287 u32 head;
@@ -288,6 +294,7 @@ struct nv50_display_oimm_class {
288 * 857c: NVA3_DISP_SYNC 294 * 857c: NVA3_DISP_SYNC
289 * 907c: NVD0_DISP_SYNC 295 * 907c: NVD0_DISP_SYNC
290 * 917c: NVE0_DISP_SYNC 296 * 917c: NVE0_DISP_SYNC
297 * 927c: NVF0_DISP_SYNC
291 */ 298 */
292 299
293#define NV50_DISP_SYNC_CLASS 0x0000507c 300#define NV50_DISP_SYNC_CLASS 0x0000507c
@@ -297,6 +304,7 @@ struct nv50_display_oimm_class {
297#define NVA3_DISP_SYNC_CLASS 0x0000857c 304#define NVA3_DISP_SYNC_CLASS 0x0000857c
298#define NVD0_DISP_SYNC_CLASS 0x0000907c 305#define NVD0_DISP_SYNC_CLASS 0x0000907c
299#define NVE0_DISP_SYNC_CLASS 0x0000917c 306#define NVE0_DISP_SYNC_CLASS 0x0000917c
307#define NVF0_DISP_SYNC_CLASS 0x0000927c
300 308
301struct nv50_display_sync_class { 309struct nv50_display_sync_class {
302 u32 pushbuf; 310 u32 pushbuf;
@@ -310,6 +318,7 @@ struct nv50_display_sync_class {
310 * 857d: NVA3_DISP_MAST 318 * 857d: NVA3_DISP_MAST
311 * 907d: NVD0_DISP_MAST 319 * 907d: NVD0_DISP_MAST
312 * 917d: NVE0_DISP_MAST 320 * 917d: NVE0_DISP_MAST
321 * 927d: NVF0_DISP_MAST
313 */ 322 */
314 323
315#define NV50_DISP_MAST_CLASS 0x0000507d 324#define NV50_DISP_MAST_CLASS 0x0000507d
@@ -319,6 +328,7 @@ struct nv50_display_sync_class {
319#define NVA3_DISP_MAST_CLASS 0x0000857d 328#define NVA3_DISP_MAST_CLASS 0x0000857d
320#define NVD0_DISP_MAST_CLASS 0x0000907d 329#define NVD0_DISP_MAST_CLASS 0x0000907d
321#define NVE0_DISP_MAST_CLASS 0x0000917d 330#define NVE0_DISP_MAST_CLASS 0x0000917d
331#define NVF0_DISP_MAST_CLASS 0x0000927d
322 332
323struct nv50_display_mast_class { 333struct nv50_display_mast_class {
324 u32 pushbuf; 334 u32 pushbuf;
@@ -331,6 +341,7 @@ struct nv50_display_mast_class {
331 * 857e: NVA3_DISP_OVLY 341 * 857e: NVA3_DISP_OVLY
332 * 907e: NVD0_DISP_OVLY 342 * 907e: NVD0_DISP_OVLY
333 * 917e: NVE0_DISP_OVLY 343 * 917e: NVE0_DISP_OVLY
344 * 927e: NVF0_DISP_OVLY
334 */ 345 */
335 346
336#define NV50_DISP_OVLY_CLASS 0x0000507e 347#define NV50_DISP_OVLY_CLASS 0x0000507e
@@ -340,6 +351,7 @@ struct nv50_display_mast_class {
340#define NVA3_DISP_OVLY_CLASS 0x0000857e 351#define NVA3_DISP_OVLY_CLASS 0x0000857e
341#define NVD0_DISP_OVLY_CLASS 0x0000907e 352#define NVD0_DISP_OVLY_CLASS 0x0000907e
342#define NVE0_DISP_OVLY_CLASS 0x0000917e 353#define NVE0_DISP_OVLY_CLASS 0x0000917e
354#define NVF0_DISP_OVLY_CLASS 0x0000927e
343 355
344struct nv50_display_ovly_class { 356struct nv50_display_ovly_class {
345 u32 pushbuf; 357 u32 pushbuf;
diff --git a/drivers/gpu/drm/nouveau/core/include/engine/disp.h b/drivers/gpu/drm/nouveau/core/include/engine/disp.h
index 28da6772c095..4b21fabfbddb 100644
--- a/drivers/gpu/drm/nouveau/core/include/engine/disp.h
+++ b/drivers/gpu/drm/nouveau/core/include/engine/disp.h
@@ -44,5 +44,6 @@ extern struct nouveau_oclass nv94_disp_oclass;
44extern struct nouveau_oclass nva3_disp_oclass; 44extern struct nouveau_oclass nva3_disp_oclass;
45extern struct nouveau_oclass nvd0_disp_oclass; 45extern struct nouveau_oclass nvd0_disp_oclass;
46extern struct nouveau_oclass nve0_disp_oclass; 46extern struct nouveau_oclass nve0_disp_oclass;
47extern struct nouveau_oclass nvf0_disp_oclass;
47 48
48#endif 49#endif
diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c
index c33b13fb18db..46c152ff0a80 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_drm.c
@@ -33,6 +33,7 @@
33 33
34#include <engine/device.h> 34#include <engine/device.h>
35#include <engine/disp.h> 35#include <engine/disp.h>
36#include <engine/fifo.h>
36 37
37#include <subdev/vm.h> 38#include <subdev/vm.h>
38 39
@@ -164,7 +165,7 @@ nouveau_accel_init(struct nouveau_drm *drm)
164 u32 arg0, arg1; 165 u32 arg0, arg1;
165 int ret; 166 int ret;
166 167
167 if (nouveau_noaccel) 168 if (nouveau_noaccel || !nouveau_fifo(device) /*XXX*/)
168 return; 169 return;
169 170
170 /* initialise synchronisation routines */ 171 /* initialise synchronisation routines */
diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c
index 7f0e6c3f37d1..325887390677 100644
--- a/drivers/gpu/drm/nouveau/nv50_display.c
+++ b/drivers/gpu/drm/nouveau/nv50_display.c
@@ -2174,6 +2174,7 @@ int
2174nv50_display_create(struct drm_device *dev) 2174nv50_display_create(struct drm_device *dev)
2175{ 2175{
2176 static const u16 oclass[] = { 2176 static const u16 oclass[] = {
2177 NVF0_DISP_CLASS,
2177 NVE0_DISP_CLASS, 2178 NVE0_DISP_CLASS,
2178 NVD0_DISP_CLASS, 2179 NVD0_DISP_CLASS,
2179 NVA3_DISP_CLASS, 2180 NVA3_DISP_CLASS,
diff --git a/drivers/gpu/drm/radeon/atom.c b/drivers/gpu/drm/radeon/atom.c
index 46a9c3772850..fb441a790f3d 100644
--- a/drivers/gpu/drm/radeon/atom.c
+++ b/drivers/gpu/drm/radeon/atom.c
@@ -1394,10 +1394,10 @@ int atom_allocate_fb_scratch(struct atom_context *ctx)
1394 firmware_usage = (struct _ATOM_VRAM_USAGE_BY_FIRMWARE *)(ctx->bios + data_offset); 1394 firmware_usage = (struct _ATOM_VRAM_USAGE_BY_FIRMWARE *)(ctx->bios + data_offset);
1395 1395
1396 DRM_DEBUG("atom firmware requested %08x %dkb\n", 1396 DRM_DEBUG("atom firmware requested %08x %dkb\n",
1397 firmware_usage->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware, 1397 le32_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware),
1398 firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb); 1398 le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb));
1399 1399
1400 usage_bytes = firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb * 1024; 1400 usage_bytes = le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb) * 1024;
1401 } 1401 }
1402 ctx->scratch_size_bytes = 0; 1402 ctx->scratch_size_bytes = 0;
1403 if (usage_bytes == 0) 1403 if (usage_bytes == 0)
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 1531f167d152..105bafb6c29d 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -989,62 +989,10 @@ done:
989 return r; 989 return r;
990} 990}
991 991
992static int evergreen_uvd_calc_post_div(unsigned target_freq,
993 unsigned vco_freq,
994 unsigned *div)
995{
996 /* target larger than vco frequency ? */
997 if (vco_freq < target_freq)
998 return -1; /* forget it */
999
1000 /* Fclk = Fvco / PDIV */
1001 *div = vco_freq / target_freq;
1002
1003 /* we alway need a frequency less than or equal the target */
1004 if ((vco_freq / *div) > target_freq)
1005 *div += 1;
1006
1007 /* dividers above 5 must be even */
1008 if (*div > 5 && *div % 2)
1009 *div += 1;
1010
1011 /* out of range ? */
1012 if (*div >= 128)
1013 return -1; /* forget it */
1014
1015 return vco_freq / *div;
1016}
1017
1018static int evergreen_uvd_send_upll_ctlreq(struct radeon_device *rdev)
1019{
1020 unsigned i;
1021
1022 /* assert UPLL_CTLREQ */
1023 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK);
1024
1025 /* wait for CTLACK and CTLACK2 to get asserted */
1026 for (i = 0; i < 100; ++i) {
1027 uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK;
1028 if ((RREG32(CG_UPLL_FUNC_CNTL) & mask) == mask)
1029 break;
1030 mdelay(10);
1031 }
1032 if (i == 100)
1033 return -ETIMEDOUT;
1034
1035 /* deassert UPLL_CTLREQ */
1036 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK);
1037
1038 return 0;
1039}
1040
1041int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) 992int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
1042{ 993{
1043 /* start off with something large */ 994 /* start off with something large */
1044 int optimal_diff_score = 0x7FFFFFF; 995 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0;
1045 unsigned optimal_fb_div = 0, optimal_vclk_div = 0;
1046 unsigned optimal_dclk_div = 0, optimal_vco_freq = 0;
1047 unsigned vco_freq;
1048 int r; 996 int r;
1049 997
1050 /* bypass vclk and dclk with bclk */ 998 /* bypass vclk and dclk with bclk */
@@ -1061,40 +1009,11 @@ int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
1061 return 0; 1009 return 0;
1062 } 1010 }
1063 1011
1064 /* loop through vco from low to high */ 1012 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 125000, 250000,
1065 for (vco_freq = 125000; vco_freq <= 250000; vco_freq += 100) { 1013 16384, 0x03FFFFFF, 0, 128, 5,
1066 unsigned fb_div = vco_freq / rdev->clock.spll.reference_freq * 16384; 1014 &fb_div, &vclk_div, &dclk_div);
1067 int calc_clk, diff_score, diff_vclk, diff_dclk; 1015 if (r)
1068 unsigned vclk_div, dclk_div; 1016 return r;
1069
1070 /* fb div out of range ? */
1071 if (fb_div > 0x03FFFFFF)
1072 break; /* it can oly get worse */
1073
1074 /* calc vclk with current vco freq. */
1075 calc_clk = evergreen_uvd_calc_post_div(vclk, vco_freq, &vclk_div);
1076 if (calc_clk == -1)
1077 break; /* vco is too big, it has to stop. */
1078 diff_vclk = vclk - calc_clk;
1079
1080 /* calc dclk with current vco freq. */
1081 calc_clk = evergreen_uvd_calc_post_div(dclk, vco_freq, &dclk_div);
1082 if (calc_clk == -1)
1083 break; /* vco is too big, it has to stop. */
1084 diff_dclk = dclk - calc_clk;
1085
1086 /* determine if this vco setting is better than current optimal settings */
1087 diff_score = abs(diff_vclk) + abs(diff_dclk);
1088 if (diff_score < optimal_diff_score) {
1089 optimal_fb_div = fb_div;
1090 optimal_vclk_div = vclk_div;
1091 optimal_dclk_div = dclk_div;
1092 optimal_vco_freq = vco_freq;
1093 optimal_diff_score = diff_score;
1094 if (optimal_diff_score == 0)
1095 break; /* it can't get better than this */
1096 }
1097 }
1098 1017
1099 /* set VCO_MODE to 1 */ 1018 /* set VCO_MODE to 1 */
1100 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK); 1019 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK);
@@ -1108,7 +1027,7 @@ int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
1108 1027
1109 mdelay(1); 1028 mdelay(1);
1110 1029
1111 r = evergreen_uvd_send_upll_ctlreq(rdev); 1030 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
1112 if (r) 1031 if (r)
1113 return r; 1032 return r;
1114 1033
@@ -1119,19 +1038,19 @@ int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
1119 WREG32_P(CG_UPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK); 1038 WREG32_P(CG_UPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK);
1120 1039
1121 /* set feedback divider */ 1040 /* set feedback divider */
1122 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(optimal_fb_div), ~UPLL_FB_DIV_MASK); 1041 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK);
1123 1042
1124 /* set ref divider to 0 */ 1043 /* set ref divider to 0 */
1125 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_REF_DIV_MASK); 1044 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_REF_DIV_MASK);
1126 1045
1127 if (optimal_vco_freq < 187500) 1046 if (fb_div < 307200)
1128 WREG32_P(CG_UPLL_FUNC_CNTL_4, 0, ~UPLL_SPARE_ISPARE9); 1047 WREG32_P(CG_UPLL_FUNC_CNTL_4, 0, ~UPLL_SPARE_ISPARE9);
1129 else 1048 else
1130 WREG32_P(CG_UPLL_FUNC_CNTL_4, UPLL_SPARE_ISPARE9, ~UPLL_SPARE_ISPARE9); 1049 WREG32_P(CG_UPLL_FUNC_CNTL_4, UPLL_SPARE_ISPARE9, ~UPLL_SPARE_ISPARE9);
1131 1050
1132 /* set PDIV_A and PDIV_B */ 1051 /* set PDIV_A and PDIV_B */
1133 WREG32_P(CG_UPLL_FUNC_CNTL_2, 1052 WREG32_P(CG_UPLL_FUNC_CNTL_2,
1134 UPLL_PDIV_A(optimal_vclk_div) | UPLL_PDIV_B(optimal_dclk_div), 1053 UPLL_PDIV_A(vclk_div) | UPLL_PDIV_B(dclk_div),
1135 ~(UPLL_PDIV_A_MASK | UPLL_PDIV_B_MASK)); 1054 ~(UPLL_PDIV_A_MASK | UPLL_PDIV_B_MASK));
1136 1055
1137 /* give the PLL some time to settle */ 1056 /* give the PLL some time to settle */
@@ -1145,7 +1064,7 @@ int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
1145 /* switch from bypass mode to normal mode */ 1064 /* switch from bypass mode to normal mode */
1146 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK); 1065 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);
1147 1066
1148 r = evergreen_uvd_send_upll_ctlreq(rdev); 1067 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
1149 if (r) 1068 if (r)
1150 return r; 1069 return r;
1151 1070
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index d9a005431087..75c05631146d 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -59,7 +59,7 @@
59# define UPLL_SLEEP_MASK 0x00000002 59# define UPLL_SLEEP_MASK 0x00000002
60# define UPLL_BYPASS_EN_MASK 0x00000004 60# define UPLL_BYPASS_EN_MASK 0x00000004
61# define UPLL_CTLREQ_MASK 0x00000008 61# define UPLL_CTLREQ_MASK 0x00000008
62# define UPLL_REF_DIV_MASK 0x001F0000 62# define UPLL_REF_DIV_MASK 0x003F0000
63# define UPLL_VCO_MODE_MASK 0x00000200 63# define UPLL_VCO_MODE_MASK 0x00000200
64# define UPLL_CTLACK_MASK 0x40000000 64# define UPLL_CTLACK_MASK 0x40000000
65# define UPLL_CTLACK2_MASK 0x80000000 65# define UPLL_CTLACK2_MASK 0x80000000
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 7436b91699d0..7969c0c8ec20 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -749,7 +749,8 @@ static void cayman_gpu_init(struct radeon_device *rdev)
749 (rdev->pdev->device == 0x990F) || 749 (rdev->pdev->device == 0x990F) ||
750 (rdev->pdev->device == 0x9910) || 750 (rdev->pdev->device == 0x9910) ||
751 (rdev->pdev->device == 0x9917) || 751 (rdev->pdev->device == 0x9917) ||
752 (rdev->pdev->device == 0x9999)) { 752 (rdev->pdev->device == 0x9999) ||
753 (rdev->pdev->device == 0x999C)) {
753 rdev->config.cayman.max_simds_per_se = 6; 754 rdev->config.cayman.max_simds_per_se = 6;
754 rdev->config.cayman.max_backends_per_se = 2; 755 rdev->config.cayman.max_backends_per_se = 2;
755 } else if ((rdev->pdev->device == 0x9903) || 756 } else if ((rdev->pdev->device == 0x9903) ||
@@ -758,7 +759,8 @@ static void cayman_gpu_init(struct radeon_device *rdev)
758 (rdev->pdev->device == 0x990D) || 759 (rdev->pdev->device == 0x990D) ||
759 (rdev->pdev->device == 0x990E) || 760 (rdev->pdev->device == 0x990E) ||
760 (rdev->pdev->device == 0x9913) || 761 (rdev->pdev->device == 0x9913) ||
761 (rdev->pdev->device == 0x9918)) { 762 (rdev->pdev->device == 0x9918) ||
763 (rdev->pdev->device == 0x999D)) {
762 rdev->config.cayman.max_simds_per_se = 4; 764 rdev->config.cayman.max_simds_per_se = 4;
763 rdev->config.cayman.max_backends_per_se = 2; 765 rdev->config.cayman.max_backends_per_se = 2;
764 } else if ((rdev->pdev->device == 0x9919) || 766 } else if ((rdev->pdev->device == 0x9919) ||
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
index 6105b25b18c3..acb146c06973 100644
--- a/drivers/gpu/drm/radeon/r600d.h
+++ b/drivers/gpu/drm/radeon/r600d.h
@@ -1208,6 +1208,10 @@
1208 1208
1209#define UVD_CONTEXT_ID 0xf6f4 1209#define UVD_CONTEXT_ID 0xf6f4
1210 1210
1211# define UPLL_CTLREQ_MASK 0x00000008
1212# define UPLL_CTLACK_MASK 0x40000000
1213# define UPLL_CTLACK2_MASK 0x80000000
1214
1211/* 1215/*
1212 * PM4 1216 * PM4
1213 */ 1217 */
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index d6c8cbaa8693..1442ce765d48 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -358,7 +358,8 @@ struct radeon_bo {
358 struct radeon_device *rdev; 358 struct radeon_device *rdev;
359 struct drm_gem_object gem_base; 359 struct drm_gem_object gem_base;
360 360
361 struct ttm_bo_kmap_obj dma_buf_vmap; 361 struct ttm_bo_kmap_obj dma_buf_vmap;
362 pid_t pid;
362}; 363};
363#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) 364#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
364 365
@@ -372,6 +373,8 @@ struct radeon_bo_list {
372 u32 tiling_flags; 373 u32 tiling_flags;
373}; 374};
374 375
376int radeon_gem_debugfs_init(struct radeon_device *rdev);
377
375/* sub-allocation manager, it has to be protected by another lock. 378/* sub-allocation manager, it has to be protected by another lock.
376 * By conception this is an helper for other part of the driver 379 * By conception this is an helper for other part of the driver
377 * like the indirect buffer or semaphore, which both have their 380 * like the indirect buffer or semaphore, which both have their
@@ -1159,6 +1162,17 @@ void radeon_uvd_free_handles(struct radeon_device *rdev,
1159 struct drm_file *filp); 1162 struct drm_file *filp);
1160int radeon_uvd_cs_parse(struct radeon_cs_parser *parser); 1163int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1161void radeon_uvd_note_usage(struct radeon_device *rdev); 1164void radeon_uvd_note_usage(struct radeon_device *rdev);
1165int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1166 unsigned vclk, unsigned dclk,
1167 unsigned vco_min, unsigned vco_max,
1168 unsigned fb_factor, unsigned fb_mask,
1169 unsigned pd_min, unsigned pd_max,
1170 unsigned pd_even,
1171 unsigned *optimal_fb_div,
1172 unsigned *optimal_vclk_div,
1173 unsigned *optimal_dclk_div);
1174int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1175 unsigned cg_upll_func_cntl);
1162 1176
1163struct r600_audio { 1177struct r600_audio {
1164 int channels; 1178 int channels;
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index 0dd87c0e0fac..dea6f63c9724 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -2028,6 +2028,8 @@ static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
2028 num_modes = power_info->info.ucNumOfPowerModeEntries; 2028 num_modes = power_info->info.ucNumOfPowerModeEntries;
2029 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK) 2029 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
2030 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK; 2030 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
2031 if (num_modes == 0)
2032 return state_index;
2031 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * num_modes, GFP_KERNEL); 2033 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * num_modes, GFP_KERNEL);
2032 if (!rdev->pm.power_state) 2034 if (!rdev->pm.power_state)
2033 return state_index; 2035 return state_index;
@@ -2307,7 +2309,7 @@ static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rde
2307 rdev->pm.default_power_state_index = state_index; 2309 rdev->pm.default_power_state_index = state_index;
2308 rdev->pm.power_state[state_index].default_clock_mode = 2310 rdev->pm.power_state[state_index].default_clock_mode =
2309 &rdev->pm.power_state[state_index].clock_info[mode_index - 1]; 2311 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2310 if (ASIC_IS_DCE5(rdev) && !(rdev->flags & RADEON_IS_IGP)) { 2312 if ((rdev->family >= CHIP_BARTS) && !(rdev->flags & RADEON_IS_IGP)) {
2311 /* NI chips post without MC ucode, so default clocks are strobe mode only */ 2313 /* NI chips post without MC ucode, so default clocks are strobe mode only */
2312 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk; 2314 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
2313 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk; 2315 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
@@ -2345,7 +2347,7 @@ static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2345 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16; 2347 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
2346 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2348 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2347 } 2349 }
2348 } else if (ASIC_IS_DCE6(rdev)) { 2350 } else if (rdev->family >= CHIP_TAHITI) {
2349 sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 2351 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
2350 sclk |= clock_info->si.ucEngineClockHigh << 16; 2352 sclk |= clock_info->si.ucEngineClockHigh << 16;
2351 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 2353 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
@@ -2358,7 +2360,7 @@ static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2358 le16_to_cpu(clock_info->si.usVDDC); 2360 le16_to_cpu(clock_info->si.usVDDC);
2359 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci = 2361 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2360 le16_to_cpu(clock_info->si.usVDDCI); 2362 le16_to_cpu(clock_info->si.usVDDCI);
2361 } else if (ASIC_IS_DCE4(rdev)) { 2363 } else if (rdev->family >= CHIP_CEDAR) {
2362 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow); 2364 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
2363 sclk |= clock_info->evergreen.ucEngineClockHigh << 16; 2365 sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
2364 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow); 2366 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
@@ -2432,6 +2434,8 @@ static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
2432 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 2434 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2433 2435
2434 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController); 2436 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2437 if (power_info->pplib.ucNumStates == 0)
2438 return state_index;
2435 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * 2439 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2436 power_info->pplib.ucNumStates, GFP_KERNEL); 2440 power_info->pplib.ucNumStates, GFP_KERNEL);
2437 if (!rdev->pm.power_state) 2441 if (!rdev->pm.power_state)
@@ -2514,6 +2518,7 @@ static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2514 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 2518 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2515 u16 data_offset; 2519 u16 data_offset;
2516 u8 frev, crev; 2520 u8 frev, crev;
2521 u8 *power_state_offset;
2517 2522
2518 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 2523 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2519 &frev, &crev, &data_offset)) 2524 &frev, &crev, &data_offset))
@@ -2530,15 +2535,17 @@ static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2530 non_clock_info_array = (struct _NonClockInfoArray *) 2535 non_clock_info_array = (struct _NonClockInfoArray *)
2531 (mode_info->atom_context->bios + data_offset + 2536 (mode_info->atom_context->bios + data_offset +
2532 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); 2537 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
2538 if (state_array->ucNumEntries == 0)
2539 return state_index;
2533 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * 2540 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2534 state_array->ucNumEntries, GFP_KERNEL); 2541 state_array->ucNumEntries, GFP_KERNEL);
2535 if (!rdev->pm.power_state) 2542 if (!rdev->pm.power_state)
2536 return state_index; 2543 return state_index;
2544 power_state_offset = (u8 *)state_array->states;
2537 for (i = 0; i < state_array->ucNumEntries; i++) { 2545 for (i = 0; i < state_array->ucNumEntries; i++) {
2538 mode_index = 0; 2546 mode_index = 0;
2539 power_state = (union pplib_power_state *)&state_array->states[i]; 2547 power_state = (union pplib_power_state *)power_state_offset;
2540 /* XXX this might be an inagua bug... */ 2548 non_clock_array_index = power_state->v2.nonClockInfoIndex;
2541 non_clock_array_index = i; /* power_state->v2.nonClockInfoIndex */
2542 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 2549 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2543 &non_clock_info_array->nonClockInfo[non_clock_array_index]; 2550 &non_clock_info_array->nonClockInfo[non_clock_array_index];
2544 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) * 2551 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
@@ -2550,9 +2557,6 @@ static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2550 if (power_state->v2.ucNumDPMLevels) { 2557 if (power_state->v2.ucNumDPMLevels) {
2551 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 2558 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2552 clock_array_index = power_state->v2.clockInfoIndex[j]; 2559 clock_array_index = power_state->v2.clockInfoIndex[j];
2553 /* XXX this might be an inagua bug... */
2554 if (clock_array_index >= clock_info_array->ucNumEntries)
2555 continue;
2556 clock_info = (union pplib_clock_info *) 2560 clock_info = (union pplib_clock_info *)
2557 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; 2561 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
2558 valid = radeon_atombios_parse_pplib_clock_info(rdev, 2562 valid = radeon_atombios_parse_pplib_clock_info(rdev,
@@ -2574,6 +2578,7 @@ static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2574 non_clock_info); 2578 non_clock_info);
2575 state_index++; 2579 state_index++;
2576 } 2580 }
2581 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
2577 } 2582 }
2578 /* if multiple clock modes, mark the lowest as no display */ 2583 /* if multiple clock modes, mark the lowest as no display */
2579 for (i = 0; i < state_index; i++) { 2584 for (i = 0; i < state_index; i++) {
@@ -2620,7 +2625,9 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2620 default: 2625 default:
2621 break; 2626 break;
2622 } 2627 }
2623 } else { 2628 }
2629
2630 if (state_index == 0) {
2624 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL); 2631 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL);
2625 if (rdev->pm.power_state) { 2632 if (rdev->pm.power_state) {
2626 rdev->pm.power_state[0].clock_info = 2633 rdev->pm.power_state[0].clock_info =
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 237b7a7549e6..a8f608903989 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -1178,6 +1178,11 @@ int radeon_device_init(struct radeon_device *rdev,
1178 if (r) 1178 if (r)
1179 DRM_ERROR("ib ring test failed (%d).\n", r); 1179 DRM_ERROR("ib ring test failed (%d).\n", r);
1180 1180
1181 r = radeon_gem_debugfs_init(rdev);
1182 if (r) {
1183 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
1184 }
1185
1181 if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) { 1186 if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
1182 /* Acceleration not working on AGP card try again 1187 /* Acceleration not working on AGP card try again
1183 * with fallback to PCI or PCIE GART 1188 * with fallback to PCI or PCIE GART
diff --git a/drivers/gpu/drm/radeon/radeon_fence.c b/drivers/gpu/drm/radeon/radeon_fence.c
index 1a699cefaac7..5b937dfe6f65 100644
--- a/drivers/gpu/drm/radeon/radeon_fence.c
+++ b/drivers/gpu/drm/radeon/radeon_fence.c
@@ -767,8 +767,8 @@ int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring)
767 767
768 radeon_scratch_free(rdev, rdev->fence_drv[ring].scratch_reg); 768 radeon_scratch_free(rdev, rdev->fence_drv[ring].scratch_reg);
769 if (rdev->wb.use_event || !radeon_ring_supports_scratch_reg(rdev, &rdev->ring[ring])) { 769 if (rdev->wb.use_event || !radeon_ring_supports_scratch_reg(rdev, &rdev->ring[ring])) {
770 rdev->fence_drv[ring].scratch_reg = 0;
770 if (ring != R600_RING_TYPE_UVD_INDEX) { 771 if (ring != R600_RING_TYPE_UVD_INDEX) {
771 rdev->fence_drv[ring].scratch_reg = 0;
772 index = R600_WB_EVENT_OFFSET + ring * 4; 772 index = R600_WB_EVENT_OFFSET + ring * 4;
773 rdev->fence_drv[ring].cpu_addr = &rdev->wb.wb[index/4]; 773 rdev->fence_drv[ring].cpu_addr = &rdev->wb.wb[index/4];
774 rdev->fence_drv[ring].gpu_addr = rdev->wb.gpu_addr + 774 rdev->fence_drv[ring].gpu_addr = rdev->wb.gpu_addr +
diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c
index fe5c1f6b7957..aa796031ab65 100644
--- a/drivers/gpu/drm/radeon/radeon_gem.c
+++ b/drivers/gpu/drm/radeon/radeon_gem.c
@@ -84,6 +84,7 @@ retry:
84 return r; 84 return r;
85 } 85 }
86 *obj = &robj->gem_base; 86 *obj = &robj->gem_base;
87 robj->pid = task_pid_nr(current);
87 88
88 mutex_lock(&rdev->gem.mutex); 89 mutex_lock(&rdev->gem.mutex);
89 list_add_tail(&robj->list, &rdev->gem.objects); 90 list_add_tail(&robj->list, &rdev->gem.objects);
@@ -575,3 +576,52 @@ int radeon_mode_dumb_destroy(struct drm_file *file_priv,
575{ 576{
576 return drm_gem_handle_delete(file_priv, handle); 577 return drm_gem_handle_delete(file_priv, handle);
577} 578}
579
580#if defined(CONFIG_DEBUG_FS)
581static int radeon_debugfs_gem_info(struct seq_file *m, void *data)
582{
583 struct drm_info_node *node = (struct drm_info_node *)m->private;
584 struct drm_device *dev = node->minor->dev;
585 struct radeon_device *rdev = dev->dev_private;
586 struct radeon_bo *rbo;
587 unsigned i = 0;
588
589 mutex_lock(&rdev->gem.mutex);
590 list_for_each_entry(rbo, &rdev->gem.objects, list) {
591 unsigned domain;
592 const char *placement;
593
594 domain = radeon_mem_type_to_domain(rbo->tbo.mem.mem_type);
595 switch (domain) {
596 case RADEON_GEM_DOMAIN_VRAM:
597 placement = "VRAM";
598 break;
599 case RADEON_GEM_DOMAIN_GTT:
600 placement = " GTT";
601 break;
602 case RADEON_GEM_DOMAIN_CPU:
603 default:
604 placement = " CPU";
605 break;
606 }
607 seq_printf(m, "bo[0x%08x] %8ldkB %8ldMB %s pid %8ld\n",
608 i, radeon_bo_size(rbo) >> 10, radeon_bo_size(rbo) >> 20,
609 placement, (unsigned long)rbo->pid);
610 i++;
611 }
612 mutex_unlock(&rdev->gem.mutex);
613 return 0;
614}
615
616static struct drm_info_list radeon_debugfs_gem_list[] = {
617 {"radeon_gem_info", &radeon_debugfs_gem_info, 0, NULL},
618};
619#endif
620
621int radeon_gem_debugfs_init(struct radeon_device *rdev)
622{
623#if defined(CONFIG_DEBUG_FS)
624 return radeon_debugfs_add_files(rdev, radeon_debugfs_gem_list, 1);
625#endif
626 return 0;
627}
diff --git a/drivers/gpu/drm/radeon/radeon_sa.c b/drivers/gpu/drm/radeon/radeon_sa.c
index cb800995d4f9..0abe5a9431bb 100644
--- a/drivers/gpu/drm/radeon/radeon_sa.c
+++ b/drivers/gpu/drm/radeon/radeon_sa.c
@@ -64,7 +64,7 @@ int radeon_sa_bo_manager_init(struct radeon_device *rdev,
64 } 64 }
65 65
66 r = radeon_bo_create(rdev, size, RADEON_GPU_PAGE_SIZE, true, 66 r = radeon_bo_create(rdev, size, RADEON_GPU_PAGE_SIZE, true,
67 RADEON_GEM_DOMAIN_CPU, NULL, &sa_manager->bo); 67 domain, NULL, &sa_manager->bo);
68 if (r) { 68 if (r) {
69 dev_err(rdev->dev, "(%d) failed to allocate bo for manager\n", r); 69 dev_err(rdev->dev, "(%d) failed to allocate bo for manager\n", r);
70 return r; 70 return r;
diff --git a/drivers/gpu/drm/radeon/radeon_uvd.c b/drivers/gpu/drm/radeon/radeon_uvd.c
index 0312a7f4d768..906e5c0ca3b9 100644
--- a/drivers/gpu/drm/radeon/radeon_uvd.c
+++ b/drivers/gpu/drm/radeon/radeon_uvd.c
@@ -692,3 +692,140 @@ void radeon_uvd_note_usage(struct radeon_device *rdev)
692 if (set_clocks) 692 if (set_clocks)
693 radeon_set_uvd_clocks(rdev, 53300, 40000); 693 radeon_set_uvd_clocks(rdev, 53300, 40000);
694} 694}
695
696static unsigned radeon_uvd_calc_upll_post_div(unsigned vco_freq,
697 unsigned target_freq,
698 unsigned pd_min,
699 unsigned pd_even)
700{
701 unsigned post_div = vco_freq / target_freq;
702
703 /* adjust to post divider minimum value */
704 if (post_div < pd_min)
705 post_div = pd_min;
706
707 /* we alway need a frequency less than or equal the target */
708 if ((vco_freq / post_div) > target_freq)
709 post_div += 1;
710
711 /* post dividers above a certain value must be even */
712 if (post_div > pd_even && post_div % 2)
713 post_div += 1;
714
715 return post_div;
716}
717
718/**
719 * radeon_uvd_calc_upll_dividers - calc UPLL clock dividers
720 *
721 * @rdev: radeon_device pointer
722 * @vclk: wanted VCLK
723 * @dclk: wanted DCLK
724 * @vco_min: minimum VCO frequency
725 * @vco_max: maximum VCO frequency
726 * @fb_factor: factor to multiply vco freq with
727 * @fb_mask: limit and bitmask for feedback divider
728 * @pd_min: post divider minimum
729 * @pd_max: post divider maximum
730 * @pd_even: post divider must be even above this value
731 * @optimal_fb_div: resulting feedback divider
732 * @optimal_vclk_div: resulting vclk post divider
733 * @optimal_dclk_div: resulting dclk post divider
734 *
735 * Calculate dividers for UVDs UPLL (R6xx-SI, except APUs).
736 * Returns zero on success -EINVAL on error.
737 */
738int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
739 unsigned vclk, unsigned dclk,
740 unsigned vco_min, unsigned vco_max,
741 unsigned fb_factor, unsigned fb_mask,
742 unsigned pd_min, unsigned pd_max,
743 unsigned pd_even,
744 unsigned *optimal_fb_div,
745 unsigned *optimal_vclk_div,
746 unsigned *optimal_dclk_div)
747{
748 unsigned vco_freq, ref_freq = rdev->clock.spll.reference_freq;
749
750 /* start off with something large */
751 unsigned optimal_score = ~0;
752
753 /* loop through vco from low to high */
754 vco_min = max(max(vco_min, vclk), dclk);
755 for (vco_freq = vco_min; vco_freq <= vco_max; vco_freq += 100) {
756
757 uint64_t fb_div = (uint64_t)vco_freq * fb_factor;
758 unsigned vclk_div, dclk_div, score;
759
760 do_div(fb_div, ref_freq);
761
762 /* fb div out of range ? */
763 if (fb_div > fb_mask)
764 break; /* it can oly get worse */
765
766 fb_div &= fb_mask;
767
768 /* calc vclk divider with current vco freq */
769 vclk_div = radeon_uvd_calc_upll_post_div(vco_freq, vclk,
770 pd_min, pd_even);
771 if (vclk_div > pd_max)
772 break; /* vco is too big, it has to stop */
773
774 /* calc dclk divider with current vco freq */
775 dclk_div = radeon_uvd_calc_upll_post_div(vco_freq, dclk,
776 pd_min, pd_even);
777 if (vclk_div > pd_max)
778 break; /* vco is too big, it has to stop */
779
780 /* calc score with current vco freq */
781 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div);
782
783 /* determine if this vco setting is better than current optimal settings */
784 if (score < optimal_score) {
785 *optimal_fb_div = fb_div;
786 *optimal_vclk_div = vclk_div;
787 *optimal_dclk_div = dclk_div;
788 optimal_score = score;
789 if (optimal_score == 0)
790 break; /* it can't get better than this */
791 }
792 }
793
794 /* did we found a valid setup ? */
795 if (optimal_score == ~0)
796 return -EINVAL;
797
798 return 0;
799}
800
801int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
802 unsigned cg_upll_func_cntl)
803{
804 unsigned i;
805
806 /* make sure UPLL_CTLREQ is deasserted */
807 WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK);
808
809 mdelay(10);
810
811 /* assert UPLL_CTLREQ */
812 WREG32_P(cg_upll_func_cntl, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK);
813
814 /* wait for CTLACK and CTLACK2 to get asserted */
815 for (i = 0; i < 100; ++i) {
816 uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK;
817 if ((RREG32(cg_upll_func_cntl) & mask) == mask)
818 break;
819 mdelay(10);
820 }
821
822 /* deassert UPLL_CTLREQ */
823 WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK);
824
825 if (i == 100) {
826 DRM_ERROR("Timeout setting UVD clocks!\n");
827 return -ETIMEDOUT;
828 }
829
830 return 0;
831}
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index 91530d4c11c4..83f612a9500b 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -44,56 +44,9 @@ void rv770_fini(struct radeon_device *rdev);
44static void rv770_pcie_gen2_enable(struct radeon_device *rdev); 44static void rv770_pcie_gen2_enable(struct radeon_device *rdev);
45int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); 45int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
46 46
47static int rv770_uvd_calc_post_div(unsigned target_freq,
48 unsigned vco_freq,
49 unsigned *div)
50{
51 /* Fclk = Fvco / PDIV */
52 *div = vco_freq / target_freq;
53
54 /* we alway need a frequency less than or equal the target */
55 if ((vco_freq / *div) > target_freq)
56 *div += 1;
57
58 /* out of range ? */
59 if (*div > 30)
60 return -1; /* forget it */
61
62 *div -= 1;
63 return vco_freq / (*div + 1);
64}
65
66static int rv770_uvd_send_upll_ctlreq(struct radeon_device *rdev)
67{
68 unsigned i;
69
70 /* assert UPLL_CTLREQ */
71 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK);
72
73 /* wait for CTLACK and CTLACK2 to get asserted */
74 for (i = 0; i < 100; ++i) {
75 uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK;
76 if ((RREG32(CG_UPLL_FUNC_CNTL) & mask) == mask)
77 break;
78 mdelay(10);
79 }
80 if (i == 100)
81 return -ETIMEDOUT;
82
83 /* deassert UPLL_CTLREQ */
84 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK);
85
86 return 0;
87}
88
89int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) 47int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
90{ 48{
91 /* start off with something large */ 49 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0;
92 int optimal_diff_score = 0x7FFFFFF;
93 unsigned optimal_fb_div = 0, optimal_vclk_div = 0;
94 unsigned optimal_dclk_div = 0, optimal_vco_freq = 0;
95 unsigned vco_freq, vco_min = 50000, vco_max = 160000;
96 unsigned ref_freq = rdev->clock.spll.reference_freq;
97 int r; 50 int r;
98 51
99 /* RV740 uses evergreen uvd clk programming */ 52 /* RV740 uses evergreen uvd clk programming */
@@ -111,44 +64,15 @@ int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
111 return 0; 64 return 0;
112 } 65 }
113 66
114 /* loop through vco from low to high */ 67 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000,
115 vco_min = max(max(vco_min, vclk), dclk); 68 43663, 0x03FFFFFE, 1, 30, ~0,
116 for (vco_freq = vco_min; vco_freq <= vco_max; vco_freq += 500) { 69 &fb_div, &vclk_div, &dclk_div);
117 uint64_t fb_div = (uint64_t)vco_freq * 43663; 70 if (r)
118 int calc_clk, diff_score, diff_vclk, diff_dclk; 71 return r;
119 unsigned vclk_div, dclk_div; 72
120 73 fb_div |= 1;
121 do_div(fb_div, ref_freq); 74 vclk_div -= 1;
122 fb_div |= 1; 75 dclk_div -= 1;
123
124 /* fb div out of range ? */
125 if (fb_div > 0x03FFFFFF)
126 break; /* it can oly get worse */
127
128 /* calc vclk with current vco freq. */
129 calc_clk = rv770_uvd_calc_post_div(vclk, vco_freq, &vclk_div);
130 if (calc_clk == -1)
131 break; /* vco is too big, it has to stop. */
132 diff_vclk = vclk - calc_clk;
133
134 /* calc dclk with current vco freq. */
135 calc_clk = rv770_uvd_calc_post_div(dclk, vco_freq, &dclk_div);
136 if (calc_clk == -1)
137 break; /* vco is too big, it has to stop. */
138 diff_dclk = dclk - calc_clk;
139
140 /* determine if this vco setting is better than current optimal settings */
141 diff_score = abs(diff_vclk) + abs(diff_dclk);
142 if (diff_score < optimal_diff_score) {
143 optimal_fb_div = fb_div;
144 optimal_vclk_div = vclk_div;
145 optimal_dclk_div = dclk_div;
146 optimal_vco_freq = vco_freq;
147 optimal_diff_score = diff_score;
148 if (optimal_diff_score == 0)
149 break; /* it can't get better than this */
150 }
151 }
152 76
153 /* set UPLL_FB_DIV to 0x50000 */ 77 /* set UPLL_FB_DIV to 0x50000 */
154 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(0x50000), ~UPLL_FB_DIV_MASK); 78 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(0x50000), ~UPLL_FB_DIV_MASK);
@@ -160,7 +84,7 @@ int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
160 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK); 84 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);
161 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(1), ~UPLL_FB_DIV(1)); 85 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(1), ~UPLL_FB_DIV(1));
162 86
163 r = rv770_uvd_send_upll_ctlreq(rdev); 87 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
164 if (r) 88 if (r)
165 return r; 89 return r;
166 90
@@ -170,13 +94,13 @@ int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
170 /* set the required FB_DIV, REF_DIV, Post divder values */ 94 /* set the required FB_DIV, REF_DIV, Post divder values */
171 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REF_DIV(1), ~UPLL_REF_DIV_MASK); 95 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REF_DIV(1), ~UPLL_REF_DIV_MASK);
172 WREG32_P(CG_UPLL_FUNC_CNTL_2, 96 WREG32_P(CG_UPLL_FUNC_CNTL_2,
173 UPLL_SW_HILEN(optimal_vclk_div >> 1) | 97 UPLL_SW_HILEN(vclk_div >> 1) |
174 UPLL_SW_LOLEN((optimal_vclk_div >> 1) + (optimal_vclk_div & 1)) | 98 UPLL_SW_LOLEN((vclk_div >> 1) + (vclk_div & 1)) |
175 UPLL_SW_HILEN2(optimal_dclk_div >> 1) | 99 UPLL_SW_HILEN2(dclk_div >> 1) |
176 UPLL_SW_LOLEN2((optimal_dclk_div >> 1) + (optimal_dclk_div & 1)), 100 UPLL_SW_LOLEN2((dclk_div >> 1) + (dclk_div & 1)),
177 ~UPLL_SW_MASK); 101 ~UPLL_SW_MASK);
178 102
179 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(optimal_fb_div), 103 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div),
180 ~UPLL_FB_DIV_MASK); 104 ~UPLL_FB_DIV_MASK);
181 105
182 /* give the PLL some time to settle */ 106 /* give the PLL some time to settle */
@@ -191,7 +115,7 @@ int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
191 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK); 115 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);
192 WREG32_P(CG_UPLL_FUNC_CNTL_3, 0, ~UPLL_FB_DIV(1)); 116 WREG32_P(CG_UPLL_FUNC_CNTL_3, 0, ~UPLL_FB_DIV(1));
193 117
194 r = rv770_uvd_send_upll_ctlreq(rdev); 118 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
195 if (r) 119 if (r)
196 return r; 120 return r;
197 121
diff --git a/drivers/gpu/drm/radeon/rv770d.h b/drivers/gpu/drm/radeon/rv770d.h
index 6a52b2054f32..85b16266f748 100644
--- a/drivers/gpu/drm/radeon/rv770d.h
+++ b/drivers/gpu/drm/radeon/rv770d.h
@@ -45,7 +45,7 @@
45# define UPLL_BYPASS_EN_MASK 0x00000004 45# define UPLL_BYPASS_EN_MASK 0x00000004
46# define UPLL_CTLREQ_MASK 0x00000008 46# define UPLL_CTLREQ_MASK 0x00000008
47# define UPLL_REF_DIV(x) ((x) << 16) 47# define UPLL_REF_DIV(x) ((x) << 16)
48# define UPLL_REF_DIV_MASK 0x001F0000 48# define UPLL_REF_DIV_MASK 0x003F0000
49# define UPLL_CTLACK_MASK 0x40000000 49# define UPLL_CTLACK_MASK 0x40000000
50# define UPLL_CTLACK2_MASK 0x80000000 50# define UPLL_CTLACK2_MASK 0x80000000
51#define CG_UPLL_FUNC_CNTL_2 0x71c 51#define CG_UPLL_FUNC_CNTL_2 0x71c
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index fe6b14e0021c..f0b6c2f87c4d 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -5415,62 +5415,9 @@ uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev)
5415 return clock; 5415 return clock;
5416} 5416}
5417 5417
5418static int si_uvd_calc_post_div(unsigned target_freq,
5419 unsigned vco_freq,
5420 unsigned *div)
5421{
5422 /* target larger than vco frequency ? */
5423 if (vco_freq < target_freq)
5424 return -1; /* forget it */
5425
5426 /* Fclk = Fvco / PDIV */
5427 *div = vco_freq / target_freq;
5428
5429 /* we alway need a frequency less than or equal the target */
5430 if ((vco_freq / *div) > target_freq)
5431 *div += 1;
5432
5433 /* dividers above 5 must be even */
5434 if (*div > 5 && *div % 2)
5435 *div += 1;
5436
5437 /* out of range ? */
5438 if (*div >= 128)
5439 return -1; /* forget it */
5440
5441 return vco_freq / *div;
5442}
5443
5444static int si_uvd_send_upll_ctlreq(struct radeon_device *rdev)
5445{
5446 unsigned i;
5447
5448 /* assert UPLL_CTLREQ */
5449 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK);
5450
5451 /* wait for CTLACK and CTLACK2 to get asserted */
5452 for (i = 0; i < 100; ++i) {
5453 uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK;
5454 if ((RREG32(CG_UPLL_FUNC_CNTL) & mask) == mask)
5455 break;
5456 mdelay(10);
5457 }
5458 if (i == 100)
5459 return -ETIMEDOUT;
5460
5461 /* deassert UPLL_CTLREQ */
5462 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK);
5463
5464 return 0;
5465}
5466
5467int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) 5418int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
5468{ 5419{
5469 /* start off with something large */ 5420 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0;
5470 int optimal_diff_score = 0x7FFFFFF;
5471 unsigned optimal_fb_div = 0, optimal_vclk_div = 0;
5472 unsigned optimal_dclk_div = 0, optimal_vco_freq = 0;
5473 unsigned vco_freq;
5474 int r; 5421 int r;
5475 5422
5476 /* bypass vclk and dclk with bclk */ 5423 /* bypass vclk and dclk with bclk */
@@ -5487,40 +5434,11 @@ int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
5487 return 0; 5434 return 0;
5488 } 5435 }
5489 5436
5490 /* loop through vco from low to high */ 5437 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 125000, 250000,
5491 for (vco_freq = 125000; vco_freq <= 250000; vco_freq += 100) { 5438 16384, 0x03FFFFFF, 0, 128, 5,
5492 unsigned fb_div = vco_freq / rdev->clock.spll.reference_freq * 16384; 5439 &fb_div, &vclk_div, &dclk_div);
5493 int calc_clk, diff_score, diff_vclk, diff_dclk; 5440 if (r)
5494 unsigned vclk_div, dclk_div; 5441 return r;
5495
5496 /* fb div out of range ? */
5497 if (fb_div > 0x03FFFFFF)
5498 break; /* it can oly get worse */
5499
5500 /* calc vclk with current vco freq. */
5501 calc_clk = si_uvd_calc_post_div(vclk, vco_freq, &vclk_div);
5502 if (calc_clk == -1)
5503 break; /* vco is too big, it has to stop. */
5504 diff_vclk = vclk - calc_clk;
5505
5506 /* calc dclk with current vco freq. */
5507 calc_clk = si_uvd_calc_post_div(dclk, vco_freq, &dclk_div);
5508 if (calc_clk == -1)
5509 break; /* vco is too big, it has to stop. */
5510 diff_dclk = dclk - calc_clk;
5511
5512 /* determine if this vco setting is better than current optimal settings */
5513 diff_score = abs(diff_vclk) + abs(diff_dclk);
5514 if (diff_score < optimal_diff_score) {
5515 optimal_fb_div = fb_div;
5516 optimal_vclk_div = vclk_div;
5517 optimal_dclk_div = dclk_div;
5518 optimal_vco_freq = vco_freq;
5519 optimal_diff_score = diff_score;
5520 if (optimal_diff_score == 0)
5521 break; /* it can't get better than this */
5522 }
5523 }
5524 5442
5525 /* set RESET_ANTI_MUX to 0 */ 5443 /* set RESET_ANTI_MUX to 0 */
5526 WREG32_P(CG_UPLL_FUNC_CNTL_5, 0, ~RESET_ANTI_MUX_MASK); 5444 WREG32_P(CG_UPLL_FUNC_CNTL_5, 0, ~RESET_ANTI_MUX_MASK);
@@ -5537,7 +5455,7 @@ int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
5537 5455
5538 mdelay(1); 5456 mdelay(1);
5539 5457
5540 r = si_uvd_send_upll_ctlreq(rdev); 5458 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
5541 if (r) 5459 if (r)
5542 return r; 5460 return r;
5543 5461
@@ -5548,19 +5466,19 @@ int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
5548 WREG32_P(CG_UPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK); 5466 WREG32_P(CG_UPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK);
5549 5467
5550 /* set feedback divider */ 5468 /* set feedback divider */
5551 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(optimal_fb_div), ~UPLL_FB_DIV_MASK); 5469 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK);
5552 5470
5553 /* set ref divider to 0 */ 5471 /* set ref divider to 0 */
5554 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_REF_DIV_MASK); 5472 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_REF_DIV_MASK);
5555 5473
5556 if (optimal_vco_freq < 187500) 5474 if (fb_div < 307200)
5557 WREG32_P(CG_UPLL_FUNC_CNTL_4, 0, ~UPLL_SPARE_ISPARE9); 5475 WREG32_P(CG_UPLL_FUNC_CNTL_4, 0, ~UPLL_SPARE_ISPARE9);
5558 else 5476 else
5559 WREG32_P(CG_UPLL_FUNC_CNTL_4, UPLL_SPARE_ISPARE9, ~UPLL_SPARE_ISPARE9); 5477 WREG32_P(CG_UPLL_FUNC_CNTL_4, UPLL_SPARE_ISPARE9, ~UPLL_SPARE_ISPARE9);
5560 5478
5561 /* set PDIV_A and PDIV_B */ 5479 /* set PDIV_A and PDIV_B */
5562 WREG32_P(CG_UPLL_FUNC_CNTL_2, 5480 WREG32_P(CG_UPLL_FUNC_CNTL_2,
5563 UPLL_PDIV_A(optimal_vclk_div) | UPLL_PDIV_B(optimal_dclk_div), 5481 UPLL_PDIV_A(vclk_div) | UPLL_PDIV_B(dclk_div),
5564 ~(UPLL_PDIV_A_MASK | UPLL_PDIV_B_MASK)); 5482 ~(UPLL_PDIV_A_MASK | UPLL_PDIV_B_MASK));
5565 5483
5566 /* give the PLL some time to settle */ 5484 /* give the PLL some time to settle */
@@ -5574,7 +5492,7 @@ int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
5574 /* switch from bypass mode to normal mode */ 5492 /* switch from bypass mode to normal mode */
5575 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK); 5493 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);
5576 5494
5577 r = si_uvd_send_upll_ctlreq(rdev); 5495 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
5578 if (r) 5496 if (r)
5579 return r; 5497 return r;
5580 5498
diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h
index 042b91d6c941..222877ba6cf5 100644
--- a/drivers/gpu/drm/radeon/sid.h
+++ b/drivers/gpu/drm/radeon/sid.h
@@ -36,7 +36,7 @@
36# define UPLL_BYPASS_EN_MASK 0x00000004 36# define UPLL_BYPASS_EN_MASK 0x00000004
37# define UPLL_CTLREQ_MASK 0x00000008 37# define UPLL_CTLREQ_MASK 0x00000008
38# define UPLL_VCO_MODE_MASK 0x00000600 38# define UPLL_VCO_MODE_MASK 0x00000600
39# define UPLL_REF_DIV_MASK 0x001F0000 39# define UPLL_REF_DIV_MASK 0x003F0000
40# define UPLL_CTLACK_MASK 0x40000000 40# define UPLL_CTLACK_MASK 0x40000000
41# define UPLL_CTLACK2_MASK 0x80000000 41# define UPLL_CTLACK2_MASK 0x80000000
42#define CG_UPLL_FUNC_CNTL_2 0x638 42#define CG_UPLL_FUNC_CNTL_2 0x638
diff --git a/drivers/video/omap2/Makefile b/drivers/video/omap2/Makefile
index 5ea7cb9aed17..296e5c5281c5 100644
--- a/drivers/video/omap2/Makefile
+++ b/drivers/video/omap2/Makefile
@@ -1,5 +1,5 @@
1obj-$(CONFIG_OMAP2_VRFB) += vrfb.o 1obj-$(CONFIG_OMAP2_VRFB) += vrfb.o
2 2
3obj-$(CONFIG_OMAP2_DSS) += dss/ 3obj-$(CONFIG_OMAP2_DSS) += dss/
4obj-$(CONFIG_FB_OMAP2) += omapfb/
5obj-y += displays/ 4obj-y += displays/
5obj-$(CONFIG_FB_OMAP2) += omapfb/
diff --git a/drivers/video/omap2/displays/panel-tfp410.c b/drivers/video/omap2/displays/panel-tfp410.c
index a1dba868cef1..46039c4bf1ed 100644
--- a/drivers/video/omap2/displays/panel-tfp410.c
+++ b/drivers/video/omap2/displays/panel-tfp410.c
@@ -135,7 +135,7 @@ static int tfp410_probe(struct omap_dss_device *dssdev)
135 if (!adapter) { 135 if (!adapter) {
136 dev_err(&dssdev->dev, "Failed to get I2C adapter, bus %d\n", 136 dev_err(&dssdev->dev, "Failed to get I2C adapter, bus %d\n",
137 i2c_bus_num); 137 i2c_bus_num);
138 return -EINVAL; 138 return -EPROBE_DEFER;
139 } 139 }
140 140
141 ddata->i2c_adapter = adapter; 141 ddata->i2c_adapter = adapter;
diff --git a/drivers/video/omap2/dss/dpi.c b/drivers/video/omap2/dss/dpi.c
index e93c4debea7f..757b57f7275a 100644
--- a/drivers/video/omap2/dss/dpi.c
+++ b/drivers/video/omap2/dss/dpi.c
@@ -520,7 +520,7 @@ void omapdss_dpi_set_data_lines(struct omap_dss_device *dssdev, int data_lines)
520} 520}
521EXPORT_SYMBOL(omapdss_dpi_set_data_lines); 521EXPORT_SYMBOL(omapdss_dpi_set_data_lines);
522 522
523static int __init dpi_verify_dsi_pll(struct platform_device *dsidev) 523static int dpi_verify_dsi_pll(struct platform_device *dsidev)
524{ 524{
525 int r; 525 int r;
526 526
@@ -572,7 +572,7 @@ static enum omap_channel dpi_get_channel(void)
572 } 572 }
573} 573}
574 574
575static int __init dpi_init_display(struct omap_dss_device *dssdev) 575static int dpi_init_display(struct omap_dss_device *dssdev)
576{ 576{
577 struct platform_device *dsidev; 577 struct platform_device *dsidev;
578 578
@@ -607,7 +607,7 @@ static int __init dpi_init_display(struct omap_dss_device *dssdev)
607 return 0; 607 return 0;
608} 608}
609 609
610static struct omap_dss_device * __init dpi_find_dssdev(struct platform_device *pdev) 610static struct omap_dss_device *dpi_find_dssdev(struct platform_device *pdev)
611{ 611{
612 struct omap_dss_board_info *pdata = pdev->dev.platform_data; 612 struct omap_dss_board_info *pdata = pdev->dev.platform_data;
613 const char *def_disp_name = omapdss_get_default_display_name(); 613 const char *def_disp_name = omapdss_get_default_display_name();
@@ -635,7 +635,7 @@ static struct omap_dss_device * __init dpi_find_dssdev(struct platform_device *p
635 return def_dssdev; 635 return def_dssdev;
636} 636}
637 637
638static void __init dpi_probe_pdata(struct platform_device *dpidev) 638static int dpi_probe_pdata(struct platform_device *dpidev)
639{ 639{
640 struct omap_dss_device *plat_dssdev; 640 struct omap_dss_device *plat_dssdev;
641 struct omap_dss_device *dssdev; 641 struct omap_dss_device *dssdev;
@@ -644,11 +644,11 @@ static void __init dpi_probe_pdata(struct platform_device *dpidev)
644 plat_dssdev = dpi_find_dssdev(dpidev); 644 plat_dssdev = dpi_find_dssdev(dpidev);
645 645
646 if (!plat_dssdev) 646 if (!plat_dssdev)
647 return; 647 return 0;
648 648
649 dssdev = dss_alloc_and_init_device(&dpidev->dev); 649 dssdev = dss_alloc_and_init_device(&dpidev->dev);
650 if (!dssdev) 650 if (!dssdev)
651 return; 651 return -ENOMEM;
652 652
653 dss_copy_device_pdata(dssdev, plat_dssdev); 653 dss_copy_device_pdata(dssdev, plat_dssdev);
654 654
@@ -656,7 +656,7 @@ static void __init dpi_probe_pdata(struct platform_device *dpidev)
656 if (r) { 656 if (r) {
657 DSSERR("device %s init failed: %d\n", dssdev->name, r); 657 DSSERR("device %s init failed: %d\n", dssdev->name, r);
658 dss_put_device(dssdev); 658 dss_put_device(dssdev);
659 return; 659 return r;
660 } 660 }
661 661
662 r = omapdss_output_set_device(&dpi.output, dssdev); 662 r = omapdss_output_set_device(&dpi.output, dssdev);
@@ -664,7 +664,7 @@ static void __init dpi_probe_pdata(struct platform_device *dpidev)
664 DSSERR("failed to connect output to new device: %s\n", 664 DSSERR("failed to connect output to new device: %s\n",
665 dssdev->name); 665 dssdev->name);
666 dss_put_device(dssdev); 666 dss_put_device(dssdev);
667 return; 667 return r;
668 } 668 }
669 669
670 r = dss_add_device(dssdev); 670 r = dss_add_device(dssdev);
@@ -672,11 +672,13 @@ static void __init dpi_probe_pdata(struct platform_device *dpidev)
672 DSSERR("device %s register failed: %d\n", dssdev->name, r); 672 DSSERR("device %s register failed: %d\n", dssdev->name, r);
673 omapdss_output_unset_device(&dpi.output); 673 omapdss_output_unset_device(&dpi.output);
674 dss_put_device(dssdev); 674 dss_put_device(dssdev);
675 return; 675 return r;
676 } 676 }
677
678 return 0;
677} 679}
678 680
679static void __init dpi_init_output(struct platform_device *pdev) 681static void dpi_init_output(struct platform_device *pdev)
680{ 682{
681 struct omap_dss_output *out = &dpi.output; 683 struct omap_dss_output *out = &dpi.output;
682 684
@@ -696,13 +698,19 @@ static void __exit dpi_uninit_output(struct platform_device *pdev)
696 dss_unregister_output(out); 698 dss_unregister_output(out);
697} 699}
698 700
699static int __init omap_dpi_probe(struct platform_device *pdev) 701static int omap_dpi_probe(struct platform_device *pdev)
700{ 702{
703 int r;
704
701 mutex_init(&dpi.lock); 705 mutex_init(&dpi.lock);
702 706
703 dpi_init_output(pdev); 707 dpi_init_output(pdev);
704 708
705 dpi_probe_pdata(pdev); 709 r = dpi_probe_pdata(pdev);
710 if (r) {
711 dpi_uninit_output(pdev);
712 return r;
713 }
706 714
707 return 0; 715 return 0;
708} 716}
@@ -717,6 +725,7 @@ static int __exit omap_dpi_remove(struct platform_device *pdev)
717} 725}
718 726
719static struct platform_driver omap_dpi_driver = { 727static struct platform_driver omap_dpi_driver = {
728 .probe = omap_dpi_probe,
720 .remove = __exit_p(omap_dpi_remove), 729 .remove = __exit_p(omap_dpi_remove),
721 .driver = { 730 .driver = {
722 .name = "omapdss_dpi", 731 .name = "omapdss_dpi",
@@ -726,7 +735,7 @@ static struct platform_driver omap_dpi_driver = {
726 735
727int __init dpi_init_platform_driver(void) 736int __init dpi_init_platform_driver(void)
728{ 737{
729 return platform_driver_probe(&omap_dpi_driver, omap_dpi_probe); 738 return platform_driver_register(&omap_dpi_driver);
730} 739}
731 740
732void __exit dpi_uninit_platform_driver(void) 741void __exit dpi_uninit_platform_driver(void)
diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c
index 9b1c5ecee115..a73dedc33101 100644
--- a/drivers/video/omap2/dss/dsi.c
+++ b/drivers/video/omap2/dss/dsi.c
@@ -5225,7 +5225,7 @@ static enum omap_channel dsi_get_channel(int module_id)
5225 } 5225 }
5226} 5226}
5227 5227
5228static int __init dsi_init_display(struct omap_dss_device *dssdev) 5228static int dsi_init_display(struct omap_dss_device *dssdev)
5229{ 5229{
5230 struct platform_device *dsidev = 5230 struct platform_device *dsidev =
5231 dsi_get_dsidev_from_id(dssdev->phy.dsi.module); 5231 dsi_get_dsidev_from_id(dssdev->phy.dsi.module);
@@ -5366,7 +5366,7 @@ static int dsi_get_clocks(struct platform_device *dsidev)
5366 return 0; 5366 return 0;
5367} 5367}
5368 5368
5369static struct omap_dss_device * __init dsi_find_dssdev(struct platform_device *pdev) 5369static struct omap_dss_device *dsi_find_dssdev(struct platform_device *pdev)
5370{ 5370{
5371 struct omap_dss_board_info *pdata = pdev->dev.platform_data; 5371 struct omap_dss_board_info *pdata = pdev->dev.platform_data;
5372 struct dsi_data *dsi = dsi_get_dsidrv_data(pdev); 5372 struct dsi_data *dsi = dsi_get_dsidrv_data(pdev);
@@ -5398,7 +5398,7 @@ static struct omap_dss_device * __init dsi_find_dssdev(struct platform_device *p
5398 return def_dssdev; 5398 return def_dssdev;
5399} 5399}
5400 5400
5401static void __init dsi_probe_pdata(struct platform_device *dsidev) 5401static int dsi_probe_pdata(struct platform_device *dsidev)
5402{ 5402{
5403 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 5403 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5404 struct omap_dss_device *plat_dssdev; 5404 struct omap_dss_device *plat_dssdev;
@@ -5408,11 +5408,11 @@ static void __init dsi_probe_pdata(struct platform_device *dsidev)
5408 plat_dssdev = dsi_find_dssdev(dsidev); 5408 plat_dssdev = dsi_find_dssdev(dsidev);
5409 5409
5410 if (!plat_dssdev) 5410 if (!plat_dssdev)
5411 return; 5411 return 0;
5412 5412
5413 dssdev = dss_alloc_and_init_device(&dsidev->dev); 5413 dssdev = dss_alloc_and_init_device(&dsidev->dev);
5414 if (!dssdev) 5414 if (!dssdev)
5415 return; 5415 return -ENOMEM;
5416 5416
5417 dss_copy_device_pdata(dssdev, plat_dssdev); 5417 dss_copy_device_pdata(dssdev, plat_dssdev);
5418 5418
@@ -5420,7 +5420,7 @@ static void __init dsi_probe_pdata(struct platform_device *dsidev)
5420 if (r) { 5420 if (r) {
5421 DSSERR("device %s init failed: %d\n", dssdev->name, r); 5421 DSSERR("device %s init failed: %d\n", dssdev->name, r);
5422 dss_put_device(dssdev); 5422 dss_put_device(dssdev);
5423 return; 5423 return r;
5424 } 5424 }
5425 5425
5426 r = omapdss_output_set_device(&dsi->output, dssdev); 5426 r = omapdss_output_set_device(&dsi->output, dssdev);
@@ -5428,7 +5428,7 @@ static void __init dsi_probe_pdata(struct platform_device *dsidev)
5428 DSSERR("failed to connect output to new device: %s\n", 5428 DSSERR("failed to connect output to new device: %s\n",
5429 dssdev->name); 5429 dssdev->name);
5430 dss_put_device(dssdev); 5430 dss_put_device(dssdev);
5431 return; 5431 return r;
5432 } 5432 }
5433 5433
5434 r = dss_add_device(dssdev); 5434 r = dss_add_device(dssdev);
@@ -5436,11 +5436,13 @@ static void __init dsi_probe_pdata(struct platform_device *dsidev)
5436 DSSERR("device %s register failed: %d\n", dssdev->name, r); 5436 DSSERR("device %s register failed: %d\n", dssdev->name, r);
5437 omapdss_output_unset_device(&dsi->output); 5437 omapdss_output_unset_device(&dsi->output);
5438 dss_put_device(dssdev); 5438 dss_put_device(dssdev);
5439 return; 5439 return r;
5440 } 5440 }
5441
5442 return 0;
5441} 5443}
5442 5444
5443static void __init dsi_init_output(struct platform_device *dsidev) 5445static void dsi_init_output(struct platform_device *dsidev)
5444{ 5446{
5445 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 5447 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5446 struct omap_dss_output *out = &dsi->output; 5448 struct omap_dss_output *out = &dsi->output;
@@ -5456,7 +5458,7 @@ static void __init dsi_init_output(struct platform_device *dsidev)
5456 dss_register_output(out); 5458 dss_register_output(out);
5457} 5459}
5458 5460
5459static void __exit dsi_uninit_output(struct platform_device *dsidev) 5461static void dsi_uninit_output(struct platform_device *dsidev)
5460{ 5462{
5461 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 5463 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5462 struct omap_dss_output *out = &dsi->output; 5464 struct omap_dss_output *out = &dsi->output;
@@ -5465,7 +5467,7 @@ static void __exit dsi_uninit_output(struct platform_device *dsidev)
5465} 5467}
5466 5468
5467/* DSI1 HW IP initialisation */ 5469/* DSI1 HW IP initialisation */
5468static int __init omap_dsihw_probe(struct platform_device *dsidev) 5470static int omap_dsihw_probe(struct platform_device *dsidev)
5469{ 5471{
5470 u32 rev; 5472 u32 rev;
5471 int r, i; 5473 int r, i;
@@ -5561,7 +5563,13 @@ static int __init omap_dsihw_probe(struct platform_device *dsidev)
5561 5563
5562 dsi_init_output(dsidev); 5564 dsi_init_output(dsidev);
5563 5565
5564 dsi_probe_pdata(dsidev); 5566 r = dsi_probe_pdata(dsidev);
5567 if (r) {
5568 dsi_runtime_put(dsidev);
5569 dsi_uninit_output(dsidev);
5570 pm_runtime_disable(&dsidev->dev);
5571 return r;
5572 }
5565 5573
5566 dsi_runtime_put(dsidev); 5574 dsi_runtime_put(dsidev);
5567 5575
@@ -5632,6 +5640,7 @@ static const struct dev_pm_ops dsi_pm_ops = {
5632}; 5640};
5633 5641
5634static struct platform_driver omap_dsihw_driver = { 5642static struct platform_driver omap_dsihw_driver = {
5643 .probe = omap_dsihw_probe,
5635 .remove = __exit_p(omap_dsihw_remove), 5644 .remove = __exit_p(omap_dsihw_remove),
5636 .driver = { 5645 .driver = {
5637 .name = "omapdss_dsi", 5646 .name = "omapdss_dsi",
@@ -5642,7 +5651,7 @@ static struct platform_driver omap_dsihw_driver = {
5642 5651
5643int __init dsi_init_platform_driver(void) 5652int __init dsi_init_platform_driver(void)
5644{ 5653{
5645 return platform_driver_probe(&omap_dsihw_driver, omap_dsihw_probe); 5654 return platform_driver_register(&omap_dsihw_driver);
5646} 5655}
5647 5656
5648void __exit dsi_uninit_platform_driver(void) 5657void __exit dsi_uninit_platform_driver(void)
diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h
index faaf35857b0e..84758936429d 100644
--- a/drivers/video/omap2/dss/dss.h
+++ b/drivers/video/omap2/dss/dss.h
@@ -277,6 +277,12 @@ int sdi_init_platform_driver(void) __init;
277void sdi_uninit_platform_driver(void) __exit; 277void sdi_uninit_platform_driver(void) __exit;
278 278
279/* DSI */ 279/* DSI */
280
281typedef bool (*dsi_pll_calc_func)(int regn, int regm, unsigned long fint,
282 unsigned long pll, void *data);
283typedef bool (*dsi_hsdiv_calc_func)(int regm_dispc, unsigned long dispc,
284 void *data);
285
280#ifdef CONFIG_OMAP2_DSS_DSI 286#ifdef CONFIG_OMAP2_DSS_DSI
281 287
282struct dentry; 288struct dentry;
@@ -295,10 +301,6 @@ u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt);
295 301
296unsigned long dsi_get_pll_clkin(struct platform_device *dsidev); 302unsigned long dsi_get_pll_clkin(struct platform_device *dsidev);
297 303
298typedef bool (*dsi_pll_calc_func)(int regn, int regm, unsigned long fint,
299 unsigned long pll, void *data);
300typedef bool (*dsi_hsdiv_calc_func)(int regm_dispc, unsigned long dispc,
301 void *data);
302bool dsi_hsdiv_calc(struct platform_device *dsidev, unsigned long pll, 304bool dsi_hsdiv_calc(struct platform_device *dsidev, unsigned long pll,
303 unsigned long out_min, dsi_hsdiv_calc_func func, void *data); 305 unsigned long out_min, dsi_hsdiv_calc_func func, void *data);
304bool dsi_pll_calc(struct platform_device *dsidev, unsigned long clkin, 306bool dsi_pll_calc(struct platform_device *dsidev, unsigned long clkin,
@@ -358,6 +360,27 @@ static inline struct platform_device *dsi_get_dsidev_from_id(int module)
358{ 360{
359 return NULL; 361 return NULL;
360} 362}
363
364static inline unsigned long dsi_get_pll_clkin(struct platform_device *dsidev)
365{
366 return 0;
367}
368
369static inline bool dsi_hsdiv_calc(struct platform_device *dsidev,
370 unsigned long pll, unsigned long out_min,
371 dsi_hsdiv_calc_func func, void *data)
372{
373 return false;
374}
375
376static inline bool dsi_pll_calc(struct platform_device *dsidev,
377 unsigned long clkin,
378 unsigned long pll_min, unsigned long pll_max,
379 dsi_pll_calc_func func, void *data)
380{
381 return false;
382}
383
361#endif 384#endif
362 385
363/* DPI */ 386/* DPI */
diff --git a/drivers/video/omap2/dss/hdmi.c b/drivers/video/omap2/dss/hdmi.c
index 79393099d505..17f4d55c621c 100644
--- a/drivers/video/omap2/dss/hdmi.c
+++ b/drivers/video/omap2/dss/hdmi.c
@@ -328,7 +328,7 @@ static void hdmi_runtime_put(void)
328 WARN_ON(r < 0 && r != -ENOSYS); 328 WARN_ON(r < 0 && r != -ENOSYS);
329} 329}
330 330
331static int __init hdmi_init_display(struct omap_dss_device *dssdev) 331static int hdmi_init_display(struct omap_dss_device *dssdev)
332{ 332{
333 int r; 333 int r;
334 334
@@ -954,7 +954,7 @@ int hdmi_audio_config(struct omap_dss_audio *audio)
954 954
955#endif 955#endif
956 956
957static struct omap_dss_device * __init hdmi_find_dssdev(struct platform_device *pdev) 957static struct omap_dss_device *hdmi_find_dssdev(struct platform_device *pdev)
958{ 958{
959 struct omap_dss_board_info *pdata = pdev->dev.platform_data; 959 struct omap_dss_board_info *pdata = pdev->dev.platform_data;
960 const char *def_disp_name = omapdss_get_default_display_name(); 960 const char *def_disp_name = omapdss_get_default_display_name();
@@ -982,7 +982,7 @@ static struct omap_dss_device * __init hdmi_find_dssdev(struct platform_device *
982 return def_dssdev; 982 return def_dssdev;
983} 983}
984 984
985static void __init hdmi_probe_pdata(struct platform_device *pdev) 985static int hdmi_probe_pdata(struct platform_device *pdev)
986{ 986{
987 struct omap_dss_device *plat_dssdev; 987 struct omap_dss_device *plat_dssdev;
988 struct omap_dss_device *dssdev; 988 struct omap_dss_device *dssdev;
@@ -992,11 +992,11 @@ static void __init hdmi_probe_pdata(struct platform_device *pdev)
992 plat_dssdev = hdmi_find_dssdev(pdev); 992 plat_dssdev = hdmi_find_dssdev(pdev);
993 993
994 if (!plat_dssdev) 994 if (!plat_dssdev)
995 return; 995 return 0;
996 996
997 dssdev = dss_alloc_and_init_device(&pdev->dev); 997 dssdev = dss_alloc_and_init_device(&pdev->dev);
998 if (!dssdev) 998 if (!dssdev)
999 return; 999 return -ENOMEM;
1000 1000
1001 dss_copy_device_pdata(dssdev, plat_dssdev); 1001 dss_copy_device_pdata(dssdev, plat_dssdev);
1002 1002
@@ -1010,7 +1010,7 @@ static void __init hdmi_probe_pdata(struct platform_device *pdev)
1010 if (r) { 1010 if (r) {
1011 DSSERR("device %s init failed: %d\n", dssdev->name, r); 1011 DSSERR("device %s init failed: %d\n", dssdev->name, r);
1012 dss_put_device(dssdev); 1012 dss_put_device(dssdev);
1013 return; 1013 return r;
1014 } 1014 }
1015 1015
1016 r = omapdss_output_set_device(&hdmi.output, dssdev); 1016 r = omapdss_output_set_device(&hdmi.output, dssdev);
@@ -1018,7 +1018,7 @@ static void __init hdmi_probe_pdata(struct platform_device *pdev)
1018 DSSERR("failed to connect output to new device: %s\n", 1018 DSSERR("failed to connect output to new device: %s\n",
1019 dssdev->name); 1019 dssdev->name);
1020 dss_put_device(dssdev); 1020 dss_put_device(dssdev);
1021 return; 1021 return r;
1022 } 1022 }
1023 1023
1024 r = dss_add_device(dssdev); 1024 r = dss_add_device(dssdev);
@@ -1027,11 +1027,13 @@ static void __init hdmi_probe_pdata(struct platform_device *pdev)
1027 omapdss_output_unset_device(&hdmi.output); 1027 omapdss_output_unset_device(&hdmi.output);
1028 hdmi_uninit_display(dssdev); 1028 hdmi_uninit_display(dssdev);
1029 dss_put_device(dssdev); 1029 dss_put_device(dssdev);
1030 return; 1030 return r;
1031 } 1031 }
1032
1033 return 0;
1032} 1034}
1033 1035
1034static void __init hdmi_init_output(struct platform_device *pdev) 1036static void hdmi_init_output(struct platform_device *pdev)
1035{ 1037{
1036 struct omap_dss_output *out = &hdmi.output; 1038 struct omap_dss_output *out = &hdmi.output;
1037 1039
@@ -1052,7 +1054,7 @@ static void __exit hdmi_uninit_output(struct platform_device *pdev)
1052} 1054}
1053 1055
1054/* HDMI HW IP initialisation */ 1056/* HDMI HW IP initialisation */
1055static int __init omapdss_hdmihw_probe(struct platform_device *pdev) 1057static int omapdss_hdmihw_probe(struct platform_device *pdev)
1056{ 1058{
1057 struct resource *res; 1059 struct resource *res;
1058 int r; 1060 int r;
@@ -1096,7 +1098,13 @@ static int __init omapdss_hdmihw_probe(struct platform_device *pdev)
1096 1098
1097 dss_debugfs_create_file("hdmi", hdmi_dump_regs); 1099 dss_debugfs_create_file("hdmi", hdmi_dump_regs);
1098 1100
1099 hdmi_probe_pdata(pdev); 1101 r = hdmi_probe_pdata(pdev);
1102 if (r) {
1103 hdmi_panel_exit();
1104 hdmi_uninit_output(pdev);
1105 pm_runtime_disable(&pdev->dev);
1106 return r;
1107 }
1100 1108
1101 return 0; 1109 return 0;
1102} 1110}
@@ -1151,6 +1159,7 @@ static const struct dev_pm_ops hdmi_pm_ops = {
1151}; 1159};
1152 1160
1153static struct platform_driver omapdss_hdmihw_driver = { 1161static struct platform_driver omapdss_hdmihw_driver = {
1162 .probe = omapdss_hdmihw_probe,
1154 .remove = __exit_p(omapdss_hdmihw_remove), 1163 .remove = __exit_p(omapdss_hdmihw_remove),
1155 .driver = { 1164 .driver = {
1156 .name = "omapdss_hdmi", 1165 .name = "omapdss_hdmi",
@@ -1161,7 +1170,7 @@ static struct platform_driver omapdss_hdmihw_driver = {
1161 1170
1162int __init hdmi_init_platform_driver(void) 1171int __init hdmi_init_platform_driver(void)
1163{ 1172{
1164 return platform_driver_probe(&omapdss_hdmihw_driver, omapdss_hdmihw_probe); 1173 return platform_driver_register(&omapdss_hdmihw_driver);
1165} 1174}
1166 1175
1167void __exit hdmi_uninit_platform_driver(void) 1176void __exit hdmi_uninit_platform_driver(void)
diff --git a/drivers/video/omap2/dss/rfbi.c b/drivers/video/omap2/dss/rfbi.c
index 1a691bb27547..1a17dd1447dc 100644
--- a/drivers/video/omap2/dss/rfbi.c
+++ b/drivers/video/omap2/dss/rfbi.c
@@ -943,13 +943,13 @@ void omapdss_rfbi_display_disable(struct omap_dss_device *dssdev)
943} 943}
944EXPORT_SYMBOL(omapdss_rfbi_display_disable); 944EXPORT_SYMBOL(omapdss_rfbi_display_disable);
945 945
946static int __init rfbi_init_display(struct omap_dss_device *dssdev) 946static int rfbi_init_display(struct omap_dss_device *dssdev)
947{ 947{
948 rfbi.dssdev[dssdev->phy.rfbi.channel] = dssdev; 948 rfbi.dssdev[dssdev->phy.rfbi.channel] = dssdev;
949 return 0; 949 return 0;
950} 950}
951 951
952static struct omap_dss_device * __init rfbi_find_dssdev(struct platform_device *pdev) 952static struct omap_dss_device *rfbi_find_dssdev(struct platform_device *pdev)
953{ 953{
954 struct omap_dss_board_info *pdata = pdev->dev.platform_data; 954 struct omap_dss_board_info *pdata = pdev->dev.platform_data;
955 const char *def_disp_name = omapdss_get_default_display_name(); 955 const char *def_disp_name = omapdss_get_default_display_name();
@@ -977,7 +977,7 @@ static struct omap_dss_device * __init rfbi_find_dssdev(struct platform_device *
977 return def_dssdev; 977 return def_dssdev;
978} 978}
979 979
980static void __init rfbi_probe_pdata(struct platform_device *rfbidev) 980static int rfbi_probe_pdata(struct platform_device *rfbidev)
981{ 981{
982 struct omap_dss_device *plat_dssdev; 982 struct omap_dss_device *plat_dssdev;
983 struct omap_dss_device *dssdev; 983 struct omap_dss_device *dssdev;
@@ -986,11 +986,11 @@ static void __init rfbi_probe_pdata(struct platform_device *rfbidev)
986 plat_dssdev = rfbi_find_dssdev(rfbidev); 986 plat_dssdev = rfbi_find_dssdev(rfbidev);
987 987
988 if (!plat_dssdev) 988 if (!plat_dssdev)
989 return; 989 return 0;
990 990
991 dssdev = dss_alloc_and_init_device(&rfbidev->dev); 991 dssdev = dss_alloc_and_init_device(&rfbidev->dev);
992 if (!dssdev) 992 if (!dssdev)
993 return; 993 return -ENOMEM;
994 994
995 dss_copy_device_pdata(dssdev, plat_dssdev); 995 dss_copy_device_pdata(dssdev, plat_dssdev);
996 996
@@ -998,7 +998,7 @@ static void __init rfbi_probe_pdata(struct platform_device *rfbidev)
998 if (r) { 998 if (r) {
999 DSSERR("device %s init failed: %d\n", dssdev->name, r); 999 DSSERR("device %s init failed: %d\n", dssdev->name, r);
1000 dss_put_device(dssdev); 1000 dss_put_device(dssdev);
1001 return; 1001 return r;
1002 } 1002 }
1003 1003
1004 r = omapdss_output_set_device(&rfbi.output, dssdev); 1004 r = omapdss_output_set_device(&rfbi.output, dssdev);
@@ -1006,7 +1006,7 @@ static void __init rfbi_probe_pdata(struct platform_device *rfbidev)
1006 DSSERR("failed to connect output to new device: %s\n", 1006 DSSERR("failed to connect output to new device: %s\n",
1007 dssdev->name); 1007 dssdev->name);
1008 dss_put_device(dssdev); 1008 dss_put_device(dssdev);
1009 return; 1009 return r;
1010 } 1010 }
1011 1011
1012 r = dss_add_device(dssdev); 1012 r = dss_add_device(dssdev);
@@ -1014,11 +1014,13 @@ static void __init rfbi_probe_pdata(struct platform_device *rfbidev)
1014 DSSERR("device %s register failed: %d\n", dssdev->name, r); 1014 DSSERR("device %s register failed: %d\n", dssdev->name, r);
1015 omapdss_output_unset_device(&rfbi.output); 1015 omapdss_output_unset_device(&rfbi.output);
1016 dss_put_device(dssdev); 1016 dss_put_device(dssdev);
1017 return; 1017 return r;
1018 } 1018 }
1019
1020 return 0;
1019} 1021}
1020 1022
1021static void __init rfbi_init_output(struct platform_device *pdev) 1023static void rfbi_init_output(struct platform_device *pdev)
1022{ 1024{
1023 struct omap_dss_output *out = &rfbi.output; 1025 struct omap_dss_output *out = &rfbi.output;
1024 1026
@@ -1039,7 +1041,7 @@ static void __exit rfbi_uninit_output(struct platform_device *pdev)
1039} 1041}
1040 1042
1041/* RFBI HW IP initialisation */ 1043/* RFBI HW IP initialisation */
1042static int __init omap_rfbihw_probe(struct platform_device *pdev) 1044static int omap_rfbihw_probe(struct platform_device *pdev)
1043{ 1045{
1044 u32 rev; 1046 u32 rev;
1045 struct resource *rfbi_mem; 1047 struct resource *rfbi_mem;
@@ -1091,7 +1093,12 @@ static int __init omap_rfbihw_probe(struct platform_device *pdev)
1091 1093
1092 rfbi_init_output(pdev); 1094 rfbi_init_output(pdev);
1093 1095
1094 rfbi_probe_pdata(pdev); 1096 r = rfbi_probe_pdata(pdev);
1097 if (r) {
1098 rfbi_uninit_output(pdev);
1099 pm_runtime_disable(&pdev->dev);
1100 return r;
1101 }
1095 1102
1096 return 0; 1103 return 0;
1097 1104
@@ -1135,6 +1142,7 @@ static const struct dev_pm_ops rfbi_pm_ops = {
1135}; 1142};
1136 1143
1137static struct platform_driver omap_rfbihw_driver = { 1144static struct platform_driver omap_rfbihw_driver = {
1145 .probe = omap_rfbihw_probe,
1138 .remove = __exit_p(omap_rfbihw_remove), 1146 .remove = __exit_p(omap_rfbihw_remove),
1139 .driver = { 1147 .driver = {
1140 .name = "omapdss_rfbi", 1148 .name = "omapdss_rfbi",
@@ -1145,7 +1153,7 @@ static struct platform_driver omap_rfbihw_driver = {
1145 1153
1146int __init rfbi_init_platform_driver(void) 1154int __init rfbi_init_platform_driver(void)
1147{ 1155{
1148 return platform_driver_probe(&omap_rfbihw_driver, omap_rfbihw_probe); 1156 return platform_driver_register(&omap_rfbihw_driver);
1149} 1157}
1150 1158
1151void __exit rfbi_uninit_platform_driver(void) 1159void __exit rfbi_uninit_platform_driver(void)
diff --git a/drivers/video/omap2/dss/sdi.c b/drivers/video/omap2/dss/sdi.c
index e6baee2e84f8..0bcd30272f69 100644
--- a/drivers/video/omap2/dss/sdi.c
+++ b/drivers/video/omap2/dss/sdi.c
@@ -248,7 +248,7 @@ void omapdss_sdi_set_datapairs(struct omap_dss_device *dssdev, int datapairs)
248} 248}
249EXPORT_SYMBOL(omapdss_sdi_set_datapairs); 249EXPORT_SYMBOL(omapdss_sdi_set_datapairs);
250 250
251static int __init sdi_init_display(struct omap_dss_device *dssdev) 251static int sdi_init_display(struct omap_dss_device *dssdev)
252{ 252{
253 DSSDBG("SDI init\n"); 253 DSSDBG("SDI init\n");
254 254
@@ -268,7 +268,7 @@ static int __init sdi_init_display(struct omap_dss_device *dssdev)
268 return 0; 268 return 0;
269} 269}
270 270
271static struct omap_dss_device * __init sdi_find_dssdev(struct platform_device *pdev) 271static struct omap_dss_device *sdi_find_dssdev(struct platform_device *pdev)
272{ 272{
273 struct omap_dss_board_info *pdata = pdev->dev.platform_data; 273 struct omap_dss_board_info *pdata = pdev->dev.platform_data;
274 const char *def_disp_name = omapdss_get_default_display_name(); 274 const char *def_disp_name = omapdss_get_default_display_name();
@@ -296,7 +296,7 @@ static struct omap_dss_device * __init sdi_find_dssdev(struct platform_device *p
296 return def_dssdev; 296 return def_dssdev;
297} 297}
298 298
299static void __init sdi_probe_pdata(struct platform_device *sdidev) 299static int sdi_probe_pdata(struct platform_device *sdidev)
300{ 300{
301 struct omap_dss_device *plat_dssdev; 301 struct omap_dss_device *plat_dssdev;
302 struct omap_dss_device *dssdev; 302 struct omap_dss_device *dssdev;
@@ -305,11 +305,11 @@ static void __init sdi_probe_pdata(struct platform_device *sdidev)
305 plat_dssdev = sdi_find_dssdev(sdidev); 305 plat_dssdev = sdi_find_dssdev(sdidev);
306 306
307 if (!plat_dssdev) 307 if (!plat_dssdev)
308 return; 308 return 0;
309 309
310 dssdev = dss_alloc_and_init_device(&sdidev->dev); 310 dssdev = dss_alloc_and_init_device(&sdidev->dev);
311 if (!dssdev) 311 if (!dssdev)
312 return; 312 return -ENOMEM;
313 313
314 dss_copy_device_pdata(dssdev, plat_dssdev); 314 dss_copy_device_pdata(dssdev, plat_dssdev);
315 315
@@ -317,7 +317,7 @@ static void __init sdi_probe_pdata(struct platform_device *sdidev)
317 if (r) { 317 if (r) {
318 DSSERR("device %s init failed: %d\n", dssdev->name, r); 318 DSSERR("device %s init failed: %d\n", dssdev->name, r);
319 dss_put_device(dssdev); 319 dss_put_device(dssdev);
320 return; 320 return r;
321 } 321 }
322 322
323 r = omapdss_output_set_device(&sdi.output, dssdev); 323 r = omapdss_output_set_device(&sdi.output, dssdev);
@@ -325,7 +325,7 @@ static void __init sdi_probe_pdata(struct platform_device *sdidev)
325 DSSERR("failed to connect output to new device: %s\n", 325 DSSERR("failed to connect output to new device: %s\n",
326 dssdev->name); 326 dssdev->name);
327 dss_put_device(dssdev); 327 dss_put_device(dssdev);
328 return; 328 return r;
329 } 329 }
330 330
331 r = dss_add_device(dssdev); 331 r = dss_add_device(dssdev);
@@ -333,11 +333,13 @@ static void __init sdi_probe_pdata(struct platform_device *sdidev)
333 DSSERR("device %s register failed: %d\n", dssdev->name, r); 333 DSSERR("device %s register failed: %d\n", dssdev->name, r);
334 omapdss_output_unset_device(&sdi.output); 334 omapdss_output_unset_device(&sdi.output);
335 dss_put_device(dssdev); 335 dss_put_device(dssdev);
336 return; 336 return r;
337 } 337 }
338
339 return 0;
338} 340}
339 341
340static void __init sdi_init_output(struct platform_device *pdev) 342static void sdi_init_output(struct platform_device *pdev)
341{ 343{
342 struct omap_dss_output *out = &sdi.output; 344 struct omap_dss_output *out = &sdi.output;
343 345
@@ -357,11 +359,17 @@ static void __exit sdi_uninit_output(struct platform_device *pdev)
357 dss_unregister_output(out); 359 dss_unregister_output(out);
358} 360}
359 361
360static int __init omap_sdi_probe(struct platform_device *pdev) 362static int omap_sdi_probe(struct platform_device *pdev)
361{ 363{
364 int r;
365
362 sdi_init_output(pdev); 366 sdi_init_output(pdev);
363 367
364 sdi_probe_pdata(pdev); 368 r = sdi_probe_pdata(pdev);
369 if (r) {
370 sdi_uninit_output(pdev);
371 return r;
372 }
365 373
366 return 0; 374 return 0;
367} 375}
@@ -376,6 +384,7 @@ static int __exit omap_sdi_remove(struct platform_device *pdev)
376} 384}
377 385
378static struct platform_driver omap_sdi_driver = { 386static struct platform_driver omap_sdi_driver = {
387 .probe = omap_sdi_probe,
379 .remove = __exit_p(omap_sdi_remove), 388 .remove = __exit_p(omap_sdi_remove),
380 .driver = { 389 .driver = {
381 .name = "omapdss_sdi", 390 .name = "omapdss_sdi",
@@ -385,7 +394,7 @@ static struct platform_driver omap_sdi_driver = {
385 394
386int __init sdi_init_platform_driver(void) 395int __init sdi_init_platform_driver(void)
387{ 396{
388 return platform_driver_probe(&omap_sdi_driver, omap_sdi_probe); 397 return platform_driver_register(&omap_sdi_driver);
389} 398}
390 399
391void __exit sdi_uninit_platform_driver(void) 400void __exit sdi_uninit_platform_driver(void)
diff --git a/drivers/video/omap2/dss/venc.c b/drivers/video/omap2/dss/venc.c
index 17764d136398..74fdb3ee209e 100644
--- a/drivers/video/omap2/dss/venc.c
+++ b/drivers/video/omap2/dss/venc.c
@@ -633,7 +633,7 @@ void omapdss_venc_invert_vid_out_polarity(struct omap_dss_device *dssdev,
633 mutex_unlock(&venc.venc_lock); 633 mutex_unlock(&venc.venc_lock);
634} 634}
635 635
636static int __init venc_init_display(struct omap_dss_device *dssdev) 636static int venc_init_display(struct omap_dss_device *dssdev)
637{ 637{
638 DSSDBG("init_display\n"); 638 DSSDBG("init_display\n");
639 639
@@ -726,7 +726,7 @@ static int venc_get_clocks(struct platform_device *pdev)
726 return 0; 726 return 0;
727} 727}
728 728
729static struct omap_dss_device * __init venc_find_dssdev(struct platform_device *pdev) 729static struct omap_dss_device *venc_find_dssdev(struct platform_device *pdev)
730{ 730{
731 struct omap_dss_board_info *pdata = pdev->dev.platform_data; 731 struct omap_dss_board_info *pdata = pdev->dev.platform_data;
732 const char *def_disp_name = omapdss_get_default_display_name(); 732 const char *def_disp_name = omapdss_get_default_display_name();
@@ -754,7 +754,7 @@ static struct omap_dss_device * __init venc_find_dssdev(struct platform_device *
754 return def_dssdev; 754 return def_dssdev;
755} 755}
756 756
757static void __init venc_probe_pdata(struct platform_device *vencdev) 757static int venc_probe_pdata(struct platform_device *vencdev)
758{ 758{
759 struct omap_dss_device *plat_dssdev; 759 struct omap_dss_device *plat_dssdev;
760 struct omap_dss_device *dssdev; 760 struct omap_dss_device *dssdev;
@@ -763,11 +763,11 @@ static void __init venc_probe_pdata(struct platform_device *vencdev)
763 plat_dssdev = venc_find_dssdev(vencdev); 763 plat_dssdev = venc_find_dssdev(vencdev);
764 764
765 if (!plat_dssdev) 765 if (!plat_dssdev)
766 return; 766 return 0;
767 767
768 dssdev = dss_alloc_and_init_device(&vencdev->dev); 768 dssdev = dss_alloc_and_init_device(&vencdev->dev);
769 if (!dssdev) 769 if (!dssdev)
770 return; 770 return -ENOMEM;
771 771
772 dss_copy_device_pdata(dssdev, plat_dssdev); 772 dss_copy_device_pdata(dssdev, plat_dssdev);
773 773
@@ -775,7 +775,7 @@ static void __init venc_probe_pdata(struct platform_device *vencdev)
775 if (r) { 775 if (r) {
776 DSSERR("device %s init failed: %d\n", dssdev->name, r); 776 DSSERR("device %s init failed: %d\n", dssdev->name, r);
777 dss_put_device(dssdev); 777 dss_put_device(dssdev);
778 return; 778 return r;
779 } 779 }
780 780
781 r = omapdss_output_set_device(&venc.output, dssdev); 781 r = omapdss_output_set_device(&venc.output, dssdev);
@@ -783,7 +783,7 @@ static void __init venc_probe_pdata(struct platform_device *vencdev)
783 DSSERR("failed to connect output to new device: %s\n", 783 DSSERR("failed to connect output to new device: %s\n",
784 dssdev->name); 784 dssdev->name);
785 dss_put_device(dssdev); 785 dss_put_device(dssdev);
786 return; 786 return r;
787 } 787 }
788 788
789 r = dss_add_device(dssdev); 789 r = dss_add_device(dssdev);
@@ -791,11 +791,13 @@ static void __init venc_probe_pdata(struct platform_device *vencdev)
791 DSSERR("device %s register failed: %d\n", dssdev->name, r); 791 DSSERR("device %s register failed: %d\n", dssdev->name, r);
792 omapdss_output_unset_device(&venc.output); 792 omapdss_output_unset_device(&venc.output);
793 dss_put_device(dssdev); 793 dss_put_device(dssdev);
794 return; 794 return r;
795 } 795 }
796
797 return 0;
796} 798}
797 799
798static void __init venc_init_output(struct platform_device *pdev) 800static void venc_init_output(struct platform_device *pdev)
799{ 801{
800 struct omap_dss_output *out = &venc.output; 802 struct omap_dss_output *out = &venc.output;
801 803
@@ -816,7 +818,7 @@ static void __exit venc_uninit_output(struct platform_device *pdev)
816} 818}
817 819
818/* VENC HW IP initialisation */ 820/* VENC HW IP initialisation */
819static int __init omap_venchw_probe(struct platform_device *pdev) 821static int omap_venchw_probe(struct platform_device *pdev)
820{ 822{
821 u8 rev_id; 823 u8 rev_id;
822 struct resource *venc_mem; 824 struct resource *venc_mem;
@@ -864,7 +866,13 @@ static int __init omap_venchw_probe(struct platform_device *pdev)
864 866
865 venc_init_output(pdev); 867 venc_init_output(pdev);
866 868
867 venc_probe_pdata(pdev); 869 r = venc_probe_pdata(pdev);
870 if (r) {
871 venc_panel_exit();
872 venc_uninit_output(pdev);
873 pm_runtime_disable(&pdev->dev);
874 return r;
875 }
868 876
869 return 0; 877 return 0;
870 878
@@ -922,6 +930,7 @@ static const struct dev_pm_ops venc_pm_ops = {
922}; 930};
923 931
924static struct platform_driver omap_venchw_driver = { 932static struct platform_driver omap_venchw_driver = {
933 .probe = omap_venchw_probe,
925 .remove = __exit_p(omap_venchw_remove), 934 .remove = __exit_p(omap_venchw_remove),
926 .driver = { 935 .driver = {
927 .name = "omapdss_venc", 936 .name = "omapdss_venc",
@@ -932,7 +941,7 @@ static struct platform_driver omap_venchw_driver = {
932 941
933int __init venc_init_platform_driver(void) 942int __init venc_init_platform_driver(void)
934{ 943{
935 return platform_driver_probe(&omap_venchw_driver, omap_venchw_probe); 944 return platform_driver_register(&omap_venchw_driver);
936} 945}
937 946
938void __exit venc_uninit_platform_driver(void) 947void __exit venc_uninit_platform_driver(void)
diff --git a/drivers/video/omap2/omapfb/omapfb-main.c b/drivers/video/omap2/omapfb/omapfb-main.c
index f38348ea3375..ff00d1d8bd26 100644
--- a/drivers/video/omap2/omapfb/omapfb-main.c
+++ b/drivers/video/omap2/omapfb/omapfb-main.c
@@ -2422,7 +2422,7 @@ static int omapfb_init_connections(struct omapfb2_device *fbdev,
2422 return 0; 2422 return 0;
2423} 2423}
2424 2424
2425static int __init omapfb_probe(struct platform_device *pdev) 2425static int omapfb_probe(struct platform_device *pdev)
2426{ 2426{
2427 struct omapfb2_device *fbdev = NULL; 2427 struct omapfb2_device *fbdev = NULL;
2428 int r = 0; 2428 int r = 0;
@@ -2484,7 +2484,7 @@ static int __init omapfb_probe(struct platform_device *pdev)
2484 2484
2485 if (fbdev->num_displays == 0) { 2485 if (fbdev->num_displays == 0) {
2486 dev_err(&pdev->dev, "no displays\n"); 2486 dev_err(&pdev->dev, "no displays\n");
2487 r = -EINVAL; 2487 r = -EPROBE_DEFER;
2488 goto cleanup; 2488 goto cleanup;
2489 } 2489 }
2490 2490
@@ -2595,6 +2595,7 @@ static int __exit omapfb_remove(struct platform_device *pdev)
2595} 2595}
2596 2596
2597static struct platform_driver omapfb_driver = { 2597static struct platform_driver omapfb_driver = {
2598 .probe = omapfb_probe,
2598 .remove = __exit_p(omapfb_remove), 2599 .remove = __exit_p(omapfb_remove),
2599 .driver = { 2600 .driver = {
2600 .name = "omapfb", 2601 .name = "omapfb",
@@ -2602,36 +2603,13 @@ static struct platform_driver omapfb_driver = {
2602 }, 2603 },
2603}; 2604};
2604 2605
2605static int __init omapfb_init(void)
2606{
2607 DBG("omapfb_init\n");
2608
2609 if (platform_driver_probe(&omapfb_driver, omapfb_probe)) {
2610 printk(KERN_ERR "failed to register omapfb driver\n");
2611 return -ENODEV;
2612 }
2613
2614 return 0;
2615}
2616
2617static void __exit omapfb_exit(void)
2618{
2619 DBG("omapfb_exit\n");
2620 platform_driver_unregister(&omapfb_driver);
2621}
2622
2623module_param_named(mode, def_mode, charp, 0); 2606module_param_named(mode, def_mode, charp, 0);
2624module_param_named(vram, def_vram, charp, 0); 2607module_param_named(vram, def_vram, charp, 0);
2625module_param_named(rotate, def_rotate, int, 0); 2608module_param_named(rotate, def_rotate, int, 0);
2626module_param_named(vrfb, def_vrfb, bool, 0); 2609module_param_named(vrfb, def_vrfb, bool, 0);
2627module_param_named(mirror, def_mirror, bool, 0); 2610module_param_named(mirror, def_mirror, bool, 0);
2628 2611
2629/* late_initcall to let panel/ctrl drivers loaded first. 2612module_platform_driver(omapfb_driver);
2630 * I guess better option would be a more dynamic approach,
2631 * so that omapfb reacts to new panels when they are loaded */
2632late_initcall(omapfb_init);
2633/*module_init(omapfb_init);*/
2634module_exit(omapfb_exit);
2635 2613
2636MODULE_AUTHOR("Tomi Valkeinen <tomi.valkeinen@nokia.com>"); 2614MODULE_AUTHOR("Tomi Valkeinen <tomi.valkeinen@nokia.com>");
2637MODULE_DESCRIPTION("OMAP2/3 Framebuffer"); 2615MODULE_DESCRIPTION("OMAP2/3 Framebuffer");
diff --git a/include/drm/drm_pciids.h b/include/drm/drm_pciids.h
index 918e8fe2f5e9..c2af598f701d 100644
--- a/include/drm/drm_pciids.h
+++ b/include/drm/drm_pciids.h
@@ -240,6 +240,7 @@
240 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, \ 240 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, \
241 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ 241 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
242 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ 242 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
243 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
243 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ 244 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
244 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ 245 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
245 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ 246 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
@@ -247,11 +248,13 @@
247 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ 248 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
248 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_NEW_MEMMAP}, \ 249 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_NEW_MEMMAP}, \
249 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_NEW_MEMMAP}, \ 250 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_NEW_MEMMAP}, \
251 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
250 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ 252 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
251 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ 253 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
252 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ 254 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
253 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ 255 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
254 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ 256 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
257 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_NEW_MEMMAP}, \
255 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_NEW_MEMMAP}, \ 258 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_NEW_MEMMAP}, \
256 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_NEW_MEMMAP}, \ 259 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_NEW_MEMMAP}, \
257 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_NEW_MEMMAP}, \ 260 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_NEW_MEMMAP}, \
@@ -603,6 +606,8 @@
603 {0x1002, 0x9999, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ 606 {0x1002, 0x9999, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
604 {0x1002, 0x999A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ 607 {0x1002, 0x999A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
605 {0x1002, 0x999B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ 608 {0x1002, 0x999B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
609 {0x1002, 0x999C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
610 {0x1002, 0x999D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
606 {0x1002, 0x99A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ 611 {0x1002, 0x99A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
607 {0x1002, 0x99A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ 612 {0x1002, 0x99A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
608 {0x1002, 0x99A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ 613 {0x1002, 0x99A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
generated by cgit v1.2.2 (git 2.25.0) at 2025-10-03 04:34:53 -0400