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-rw-r--r--Documentation/devicetree/bindings/i2c/fsl-imx-i2c.txt25
-rw-r--r--arch/arm/plat-mxc/include/mach/i2c.h4
-rw-r--r--arch/arm/plat-omap/i2c.c27
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1xxx_psc.h13
-rw-r--r--drivers/i2c/busses/i2c-au1550.c280
-rw-r--r--drivers/i2c/busses/i2c-eg20t.c270
-rw-r--r--drivers/i2c/busses/i2c-imx.c46
-rw-r--r--drivers/i2c/busses/i2c-omap.c164
-rw-r--r--include/linux/i2c-omap.h5
9 files changed, 478 insertions, 356 deletions
diff --git a/Documentation/devicetree/bindings/i2c/fsl-imx-i2c.txt b/Documentation/devicetree/bindings/i2c/fsl-imx-i2c.txt
new file mode 100644
index 000000000000..f3cf43b66f7e
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/fsl-imx-i2c.txt
@@ -0,0 +1,25 @@
1* Freescale Inter IC (I2C) and High Speed Inter IC (HS-I2C) for i.MX
2
3Required properties:
4- compatible : Should be "fsl,<chip>-i2c"
5- reg : Should contain I2C/HS-I2C registers location and length
6- interrupts : Should contain I2C/HS-I2C interrupt
7
8Optional properties:
9- clock-frequency : Constains desired I2C/HS-I2C bus clock frequency in Hz.
10 The absence of the propoerty indicates the default frequency 100 kHz.
11
12Examples:
13
14i2c@83fc4000 { /* I2C2 on i.MX51 */
15 compatible = "fsl,imx51-i2c", "fsl,imx1-i2c";
16 reg = <0x83fc4000 0x4000>;
17 interrupts = <63>;
18};
19
20i2c@70038000 { /* HS-I2C on i.MX51 */
21 compatible = "fsl,imx51-i2c", "fsl,imx1-i2c";
22 reg = <0x70038000 0x4000>;
23 interrupts = <64>;
24 clock-frequency = <400000>;
25};
diff --git a/arch/arm/plat-mxc/include/mach/i2c.h b/arch/arm/plat-mxc/include/mach/i2c.h
index 4a5dc5c6d8e8..375cdd0cf876 100644
--- a/arch/arm/plat-mxc/include/mach/i2c.h
+++ b/arch/arm/plat-mxc/include/mach/i2c.h
@@ -11,14 +11,10 @@
11 11
12/** 12/**
13 * struct imxi2c_platform_data - structure of platform data for MXC I2C driver 13 * struct imxi2c_platform_data - structure of platform data for MXC I2C driver
14 * @init: Initialise gpio's and other board specific things
15 * @exit: Free everything initialised by @init
16 * @bitrate: Bus speed measured in Hz 14 * @bitrate: Bus speed measured in Hz
17 * 15 *
18 **/ 16 **/
19struct imxi2c_platform_data { 17struct imxi2c_platform_data {
20 int (*init)(struct device *dev);
21 void (*exit)(struct device *dev);
22 int bitrate; 18 int bitrate;
23}; 19};
24 20
diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c
index 3341ca4703e9..2388b8eebaaa 100644
--- a/arch/arm/plat-omap/i2c.c
+++ b/arch/arm/plat-omap/i2c.c
@@ -108,6 +108,22 @@ static inline int omap1_i2c_add_bus(int bus_id)
108 res[1].start = INT_I2C; 108 res[1].start = INT_I2C;
109 pdata = &i2c_pdata[bus_id - 1]; 109 pdata = &i2c_pdata[bus_id - 1];
110 110
111 /* all OMAP1 have IP version 1 register set */
112 pdata->rev = OMAP_I2C_IP_VERSION_1;
113
114 /* all OMAP1 I2C are implemented like this */
115 pdata->flags = OMAP_I2C_FLAG_NO_FIFO |
116 OMAP_I2C_FLAG_SIMPLE_CLOCK |
117 OMAP_I2C_FLAG_16BIT_DATA_REG |
118 OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK;
119
120 /* how the cpu bus is wired up differs for 7xx only */
121
122 if (cpu_is_omap7xx())
123 pdata->flags |= OMAP_I2C_FLAG_BUS_SHIFT_1;
124 else
125 pdata->flags |= OMAP_I2C_FLAG_BUS_SHIFT_2;
126
111 return platform_device_register(pdev); 127 return platform_device_register(pdev);
112} 128}
113 129
@@ -138,6 +154,7 @@ static inline int omap2_i2c_add_bus(int bus_id)
138 struct omap_device *od; 154 struct omap_device *od;
139 char oh_name[MAX_OMAP_I2C_HWMOD_NAME_LEN]; 155 char oh_name[MAX_OMAP_I2C_HWMOD_NAME_LEN];
140 struct omap_i2c_bus_platform_data *pdata; 156 struct omap_i2c_bus_platform_data *pdata;
157 struct omap_i2c_dev_attr *dev_attr;
141 158
142 omap2_i2c_mux_pins(bus_id); 159 omap2_i2c_mux_pins(bus_id);
143 160
@@ -152,6 +169,16 @@ static inline int omap2_i2c_add_bus(int bus_id)
152 169
153 pdata = &i2c_pdata[bus_id - 1]; 170 pdata = &i2c_pdata[bus_id - 1];
154 /* 171 /*
172 * pass the hwmod class's CPU-specific knowledge of I2C IP revision in
173 * use, and functionality implementation flags, up to the OMAP I2C
174 * driver via platform data
175 */
176 pdata->rev = oh->class->rev;
177
178 dev_attr = (struct omap_i2c_dev_attr *)oh->dev_attr;
179 pdata->flags = dev_attr->flags;
180
181 /*
155 * When waiting for completion of a i2c transfer, we need to 182 * When waiting for completion of a i2c transfer, we need to
156 * set a wake up latency constraint for the MPU. This is to 183 * set a wake up latency constraint for the MPU. This is to
157 * ensure quick enough wakeup from idle, when transfer 184 * ensure quick enough wakeup from idle, when transfer
diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h b/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h
index 892b7f168eb4..5a5cb7386427 100644
--- a/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h
+++ b/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h
@@ -394,19 +394,6 @@ typedef struct psc_spi {
394#define PSC_SPITXRX_LC (1 << 29) 394#define PSC_SPITXRX_LC (1 << 29)
395#define PSC_SPITXRX_SR (1 << 28) 395#define PSC_SPITXRX_SR (1 << 28)
396 396
397/* PSC in SMBus (I2C) Mode. */
398typedef struct psc_smb {
399 u32 psc_sel;
400 u32 psc_ctrl;
401 u32 psc_smbcfg;
402 u32 psc_smbmsk;
403 u32 psc_smbpcr;
404 u32 psc_smbstat;
405 u32 psc_smbevnt;
406 u32 psc_smbtxrx;
407 u32 psc_smbtmr;
408} psc_smb_t;
409
410/* SMBus Config Register. */ 397/* SMBus Config Register. */
411#define PSC_SMBCFG_RT_MASK (3 << 30) 398#define PSC_SMBCFG_RT_MASK (3 << 30)
412#define PSC_SMBCFG_RT_FIFO1 (0 << 30) 399#define PSC_SMBCFG_RT_FIFO1 (0 << 30)
diff --git a/drivers/i2c/busses/i2c-au1550.c b/drivers/i2c/busses/i2c-au1550.c
index 532828bc50e6..4f757a2da8cc 100644
--- a/drivers/i2c/busses/i2c-au1550.c
+++ b/drivers/i2c/busses/i2c-au1550.c
@@ -39,29 +39,41 @@
39#include <asm/mach-au1x00/au1xxx.h> 39#include <asm/mach-au1x00/au1xxx.h>
40#include <asm/mach-au1x00/au1xxx_psc.h> 40#include <asm/mach-au1x00/au1xxx_psc.h>
41 41
42#define PSC_SEL 0x00
43#define PSC_CTRL 0x04
44#define PSC_SMBCFG 0x08
45#define PSC_SMBMSK 0x0C
46#define PSC_SMBPCR 0x10
47#define PSC_SMBSTAT 0x14
48#define PSC_SMBEVNT 0x18
49#define PSC_SMBTXRX 0x1C
50#define PSC_SMBTMR 0x20
51
42struct i2c_au1550_data { 52struct i2c_au1550_data {
43 u32 psc_base; 53 void __iomem *psc_base;
44 int xfer_timeout; 54 int xfer_timeout;
45 int ack_timeout;
46 struct i2c_adapter adap; 55 struct i2c_adapter adap;
47 struct resource *ioarea; 56 struct resource *ioarea;
48}; 57};
49 58
50static int 59static inline void WR(struct i2c_au1550_data *a, int r, unsigned long v)
51wait_xfer_done(struct i2c_au1550_data *adap)
52{ 60{
53 u32 stat; 61 __raw_writel(v, a->psc_base + r);
54 int i; 62 wmb();
55 volatile psc_smb_t *sp; 63}
56 64
57 sp = (volatile psc_smb_t *)(adap->psc_base); 65static inline unsigned long RD(struct i2c_au1550_data *a, int r)
66{
67 return __raw_readl(a->psc_base + r);
68}
58 69
59 /* Wait for Tx Buffer Empty 70static int wait_xfer_done(struct i2c_au1550_data *adap)
60 */ 71{
72 int i;
73
74 /* Wait for Tx Buffer Empty */
61 for (i = 0; i < adap->xfer_timeout; i++) { 75 for (i = 0; i < adap->xfer_timeout; i++) {
62 stat = sp->psc_smbstat; 76 if (RD(adap, PSC_SMBSTAT) & PSC_SMBSTAT_TE)
63 au_sync();
64 if ((stat & PSC_SMBSTAT_TE) != 0)
65 return 0; 77 return 0;
66 78
67 udelay(1); 79 udelay(1);
@@ -70,41 +82,27 @@ wait_xfer_done(struct i2c_au1550_data *adap)
70 return -ETIMEDOUT; 82 return -ETIMEDOUT;
71} 83}
72 84
73static int 85static int wait_ack(struct i2c_au1550_data *adap)
74wait_ack(struct i2c_au1550_data *adap)
75{ 86{
76 u32 stat; 87 unsigned long stat;
77 volatile psc_smb_t *sp;
78 88
79 if (wait_xfer_done(adap)) 89 if (wait_xfer_done(adap))
80 return -ETIMEDOUT; 90 return -ETIMEDOUT;
81 91
82 sp = (volatile psc_smb_t *)(adap->psc_base); 92 stat = RD(adap, PSC_SMBEVNT);
83
84 stat = sp->psc_smbevnt;
85 au_sync();
86
87 if ((stat & (PSC_SMBEVNT_DN | PSC_SMBEVNT_AN | PSC_SMBEVNT_AL)) != 0) 93 if ((stat & (PSC_SMBEVNT_DN | PSC_SMBEVNT_AN | PSC_SMBEVNT_AL)) != 0)
88 return -ETIMEDOUT; 94 return -ETIMEDOUT;
89 95
90 return 0; 96 return 0;
91} 97}
92 98
93static int 99static int wait_master_done(struct i2c_au1550_data *adap)
94wait_master_done(struct i2c_au1550_data *adap)
95{ 100{
96 u32 stat; 101 int i;
97 int i;
98 volatile psc_smb_t *sp;
99 102
100 sp = (volatile psc_smb_t *)(adap->psc_base); 103 /* Wait for Master Done. */
101 104 for (i = 0; i < 2 * adap->xfer_timeout; i++) {
102 /* Wait for Master Done. 105 if ((RD(adap, PSC_SMBEVNT) & PSC_SMBEVNT_MD) != 0)
103 */
104 for (i = 0; i < adap->xfer_timeout; i++) {
105 stat = sp->psc_smbevnt;
106 au_sync();
107 if ((stat & PSC_SMBEVNT_MD) != 0)
108 return 0; 106 return 0;
109 udelay(1); 107 udelay(1);
110 } 108 }
@@ -115,29 +113,20 @@ wait_master_done(struct i2c_au1550_data *adap)
115static int 113static int
116do_address(struct i2c_au1550_data *adap, unsigned int addr, int rd, int q) 114do_address(struct i2c_au1550_data *adap, unsigned int addr, int rd, int q)
117{ 115{
118 volatile psc_smb_t *sp; 116 unsigned long stat;
119 u32 stat;
120 117
121 sp = (volatile psc_smb_t *)(adap->psc_base); 118 /* Reset the FIFOs, clear events. */
122 119 stat = RD(adap, PSC_SMBSTAT);
123 /* Reset the FIFOs, clear events. 120 WR(adap, PSC_SMBEVNT, PSC_SMBEVNT_ALLCLR);
124 */
125 stat = sp->psc_smbstat;
126 sp->psc_smbevnt = PSC_SMBEVNT_ALLCLR;
127 au_sync();
128 121
129 if (!(stat & PSC_SMBSTAT_TE) || !(stat & PSC_SMBSTAT_RE)) { 122 if (!(stat & PSC_SMBSTAT_TE) || !(stat & PSC_SMBSTAT_RE)) {
130 sp->psc_smbpcr = PSC_SMBPCR_DC; 123 WR(adap, PSC_SMBPCR, PSC_SMBPCR_DC);
131 au_sync(); 124 while ((RD(adap, PSC_SMBPCR) & PSC_SMBPCR_DC) != 0)
132 do { 125 cpu_relax();
133 stat = sp->psc_smbpcr;
134 au_sync();
135 } while ((stat & PSC_SMBPCR_DC) != 0);
136 udelay(50); 126 udelay(50);
137 } 127 }
138 128
139 /* Write out the i2c chip address and specify operation 129 /* Write out the i2c chip address and specify operation */
140 */
141 addr <<= 1; 130 addr <<= 1;
142 if (rd) 131 if (rd)
143 addr |= 1; 132 addr |= 1;
@@ -146,56 +135,42 @@ do_address(struct i2c_au1550_data *adap, unsigned int addr, int rd, int q)
146 if (q) 135 if (q)
147 addr |= PSC_SMBTXRX_STP; 136 addr |= PSC_SMBTXRX_STP;
148 137
149 /* Put byte into fifo, start up master. 138 /* Put byte into fifo, start up master. */
150 */ 139 WR(adap, PSC_SMBTXRX, addr);
151 sp->psc_smbtxrx = addr; 140 WR(adap, PSC_SMBPCR, PSC_SMBPCR_MS);
152 au_sync();
153 sp->psc_smbpcr = PSC_SMBPCR_MS;
154 au_sync();
155 if (wait_ack(adap)) 141 if (wait_ack(adap))
156 return -EIO; 142 return -EIO;
157 return (q) ? wait_master_done(adap) : 0; 143 return (q) ? wait_master_done(adap) : 0;
158} 144}
159 145
160static u32 146static int wait_for_rx_byte(struct i2c_au1550_data *adap, unsigned char *out)
161wait_for_rx_byte(struct i2c_au1550_data *adap, u32 *ret_data)
162{ 147{
163 int j; 148 int j;
164 u32 data, stat;
165 volatile psc_smb_t *sp;
166 149
167 if (wait_xfer_done(adap)) 150 if (wait_xfer_done(adap))
168 return -EIO; 151 return -EIO;
169 152
170 sp = (volatile psc_smb_t *)(adap->psc_base);
171
172 j = adap->xfer_timeout * 100; 153 j = adap->xfer_timeout * 100;
173 do { 154 do {
174 j--; 155 j--;
175 if (j <= 0) 156 if (j <= 0)
176 return -EIO; 157 return -EIO;
177 158
178 stat = sp->psc_smbstat; 159 if ((RD(adap, PSC_SMBSTAT) & PSC_SMBSTAT_RE) == 0)
179 au_sync();
180 if ((stat & PSC_SMBSTAT_RE) == 0)
181 j = 0; 160 j = 0;
182 else 161 else
183 udelay(1); 162 udelay(1);
184 } while (j > 0); 163 } while (j > 0);
185 data = sp->psc_smbtxrx; 164
186 au_sync(); 165 *out = RD(adap, PSC_SMBTXRX);
187 *ret_data = data;
188 166
189 return 0; 167 return 0;
190} 168}
191 169
192static int 170static int i2c_read(struct i2c_au1550_data *adap, unsigned char *buf,
193i2c_read(struct i2c_au1550_data *adap, unsigned char *buf,
194 unsigned int len) 171 unsigned int len)
195{ 172{
196 int i; 173 int i;
197 u32 data;
198 volatile psc_smb_t *sp;
199 174
200 if (len == 0) 175 if (len == 0)
201 return 0; 176 return 0;
@@ -204,62 +179,46 @@ i2c_read(struct i2c_au1550_data *adap, unsigned char *buf,
204 * zero bytes for timing, waiting for bytes to appear in the 179 * zero bytes for timing, waiting for bytes to appear in the
205 * receive fifo, then reading the bytes. 180 * receive fifo, then reading the bytes.
206 */ 181 */
207
208 sp = (volatile psc_smb_t *)(adap->psc_base);
209
210 i = 0; 182 i = 0;
211 while (i < (len-1)) { 183 while (i < (len - 1)) {
212 sp->psc_smbtxrx = 0; 184 WR(adap, PSC_SMBTXRX, 0);
213 au_sync(); 185 if (wait_for_rx_byte(adap, &buf[i]))
214 if (wait_for_rx_byte(adap, &data))
215 return -EIO; 186 return -EIO;
216 187
217 buf[i] = data;
218 i++; 188 i++;
219 } 189 }
220 190
221 /* The last byte has to indicate transfer done. 191 /* The last byte has to indicate transfer done. */
222 */ 192 WR(adap, PSC_SMBTXRX, PSC_SMBTXRX_STP);
223 sp->psc_smbtxrx = PSC_SMBTXRX_STP;
224 au_sync();
225 if (wait_master_done(adap)) 193 if (wait_master_done(adap))
226 return -EIO; 194 return -EIO;
227 195
228 data = sp->psc_smbtxrx; 196 buf[i] = (unsigned char)(RD(adap, PSC_SMBTXRX) & 0xff);
229 au_sync();
230 buf[i] = data;
231 return 0; 197 return 0;
232} 198}
233 199
234static int 200static int i2c_write(struct i2c_au1550_data *adap, unsigned char *buf,
235i2c_write(struct i2c_au1550_data *adap, unsigned char *buf,
236 unsigned int len) 201 unsigned int len)
237{ 202{
238 int i; 203 int i;
239 u32 data; 204 unsigned long data;
240 volatile psc_smb_t *sp;
241 205
242 if (len == 0) 206 if (len == 0)
243 return 0; 207 return 0;
244 208
245 sp = (volatile psc_smb_t *)(adap->psc_base);
246
247 i = 0; 209 i = 0;
248 while (i < (len-1)) { 210 while (i < (len-1)) {
249 data = buf[i]; 211 data = buf[i];
250 sp->psc_smbtxrx = data; 212 WR(adap, PSC_SMBTXRX, data);
251 au_sync();
252 if (wait_ack(adap)) 213 if (wait_ack(adap))
253 return -EIO; 214 return -EIO;
254 i++; 215 i++;
255 } 216 }
256 217
257 /* The last byte has to indicate transfer done. 218 /* The last byte has to indicate transfer done. */
258 */
259 data = buf[i]; 219 data = buf[i];
260 data |= PSC_SMBTXRX_STP; 220 data |= PSC_SMBTXRX_STP;
261 sp->psc_smbtxrx = data; 221 WR(adap, PSC_SMBTXRX, data);
262 au_sync();
263 if (wait_master_done(adap)) 222 if (wait_master_done(adap))
264 return -EIO; 223 return -EIO;
265 return 0; 224 return 0;
@@ -269,12 +228,10 @@ static int
269au1550_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, int num) 228au1550_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, int num)
270{ 229{
271 struct i2c_au1550_data *adap = i2c_adap->algo_data; 230 struct i2c_au1550_data *adap = i2c_adap->algo_data;
272 volatile psc_smb_t *sp = (volatile psc_smb_t *)adap->psc_base;
273 struct i2c_msg *p; 231 struct i2c_msg *p;
274 int i, err = 0; 232 int i, err = 0;
275 233
276 sp->psc_ctrl = PSC_CTRL_ENABLE; 234 WR(adap, PSC_CTRL, PSC_CTRL_ENABLE);
277 au_sync();
278 235
279 for (i = 0; !err && i < num; i++) { 236 for (i = 0; !err && i < num; i++) {
280 p = &msgs[i]; 237 p = &msgs[i];
@@ -293,14 +250,12 @@ au1550_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, int num)
293 if (err == 0) 250 if (err == 0)
294 err = num; 251 err = num;
295 252
296 sp->psc_ctrl = PSC_CTRL_SUSPEND; 253 WR(adap, PSC_CTRL, PSC_CTRL_SUSPEND);
297 au_sync();
298 254
299 return err; 255 return err;
300} 256}
301 257
302static u32 258static u32 au1550_func(struct i2c_adapter *adap)
303au1550_func(struct i2c_adapter *adap)
304{ 259{
305 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 260 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
306} 261}
@@ -312,57 +267,45 @@ static const struct i2c_algorithm au1550_algo = {
312 267
313static void i2c_au1550_setup(struct i2c_au1550_data *priv) 268static void i2c_au1550_setup(struct i2c_au1550_data *priv)
314{ 269{
315 volatile psc_smb_t *sp = (volatile psc_smb_t *)priv->psc_base; 270 unsigned long cfg;
316 u32 stat;
317
318 sp->psc_ctrl = PSC_CTRL_DISABLE;
319 au_sync();
320 sp->psc_sel = PSC_SEL_PS_SMBUSMODE;
321 sp->psc_smbcfg = 0;
322 au_sync();
323 sp->psc_ctrl = PSC_CTRL_ENABLE;
324 au_sync();
325 do {
326 stat = sp->psc_smbstat;
327 au_sync();
328 } while ((stat & PSC_SMBSTAT_SR) == 0);
329 271
330 sp->psc_smbcfg = (PSC_SMBCFG_RT_FIFO8 | PSC_SMBCFG_TT_FIFO8 | 272 WR(priv, PSC_CTRL, PSC_CTRL_DISABLE);
331 PSC_SMBCFG_DD_DISABLE); 273 WR(priv, PSC_SEL, PSC_SEL_PS_SMBUSMODE);
274 WR(priv, PSC_SMBCFG, 0);
275 WR(priv, PSC_CTRL, PSC_CTRL_ENABLE);
276 while ((RD(priv, PSC_SMBSTAT) & PSC_SMBSTAT_SR) == 0)
277 cpu_relax();
278
279 cfg = PSC_SMBCFG_RT_FIFO8 | PSC_SMBCFG_TT_FIFO8 | PSC_SMBCFG_DD_DISABLE;
280 WR(priv, PSC_SMBCFG, cfg);
332 281
333 /* Divide by 8 to get a 6.25 MHz clock. The later protocol 282 /* Divide by 8 to get a 6.25 MHz clock. The later protocol
334 * timings are based on this clock. 283 * timings are based on this clock.
335 */ 284 */
336 sp->psc_smbcfg |= PSC_SMBCFG_SET_DIV(PSC_SMBCFG_DIV8); 285 cfg |= PSC_SMBCFG_SET_DIV(PSC_SMBCFG_DIV8);
337 sp->psc_smbmsk = PSC_SMBMSK_ALLMASK; 286 WR(priv, PSC_SMBCFG, cfg);
338 au_sync(); 287 WR(priv, PSC_SMBMSK, PSC_SMBMSK_ALLMASK);
339 288
340 /* Set the protocol timer values. See Table 71 in the 289 /* Set the protocol timer values. See Table 71 in the
341 * Au1550 Data Book for standard timing values. 290 * Au1550 Data Book for standard timing values.
342 */ 291 */
343 sp->psc_smbtmr = PSC_SMBTMR_SET_TH(0) | PSC_SMBTMR_SET_PS(15) | \ 292 WR(priv, PSC_SMBTMR, PSC_SMBTMR_SET_TH(0) | PSC_SMBTMR_SET_PS(15) | \
344 PSC_SMBTMR_SET_PU(15) | PSC_SMBTMR_SET_SH(15) | \ 293 PSC_SMBTMR_SET_PU(15) | PSC_SMBTMR_SET_SH(15) | \
345 PSC_SMBTMR_SET_SU(15) | PSC_SMBTMR_SET_CL(15) | \ 294 PSC_SMBTMR_SET_SU(15) | PSC_SMBTMR_SET_CL(15) | \
346 PSC_SMBTMR_SET_CH(15); 295 PSC_SMBTMR_SET_CH(15));
347 au_sync();
348 296
349 sp->psc_smbcfg |= PSC_SMBCFG_DE_ENABLE; 297 cfg |= PSC_SMBCFG_DE_ENABLE;
350 do { 298 WR(priv, PSC_SMBCFG, cfg);
351 stat = sp->psc_smbstat; 299 while ((RD(priv, PSC_SMBSTAT) & PSC_SMBSTAT_SR) == 0)
352 au_sync(); 300 cpu_relax();
353 } while ((stat & PSC_SMBSTAT_SR) == 0);
354 301
355 sp->psc_ctrl = PSC_CTRL_SUSPEND; 302 WR(priv, PSC_CTRL, PSC_CTRL_SUSPEND);
356 au_sync();
357} 303}
358 304
359static void i2c_au1550_disable(struct i2c_au1550_data *priv) 305static void i2c_au1550_disable(struct i2c_au1550_data *priv)
360{ 306{
361 volatile psc_smb_t *sp = (volatile psc_smb_t *)priv->psc_base; 307 WR(priv, PSC_SMBCFG, 0);
362 308 WR(priv, PSC_CTRL, PSC_CTRL_DISABLE);
363 sp->psc_smbcfg = 0;
364 sp->psc_ctrl = PSC_CTRL_DISABLE;
365 au_sync();
366} 309}
367 310
368/* 311/*
@@ -396,9 +339,12 @@ i2c_au1550_probe(struct platform_device *pdev)
396 goto out_mem; 339 goto out_mem;
397 } 340 }
398 341
399 priv->psc_base = CKSEG1ADDR(r->start); 342 priv->psc_base = ioremap(r->start, resource_size(r));
343 if (!priv->psc_base) {
344 ret = -EIO;
345 goto out_map;
346 }
400 priv->xfer_timeout = 200; 347 priv->xfer_timeout = 200;
401 priv->ack_timeout = 200;
402 348
403 priv->adap.nr = pdev->id; 349 priv->adap.nr = pdev->id;
404 priv->adap.algo = &au1550_algo; 350 priv->adap.algo = &au1550_algo;
@@ -406,8 +352,7 @@ i2c_au1550_probe(struct platform_device *pdev)
406 priv->adap.dev.parent = &pdev->dev; 352 priv->adap.dev.parent = &pdev->dev;
407 strlcpy(priv->adap.name, "Au1xxx PSC I2C", sizeof(priv->adap.name)); 353 strlcpy(priv->adap.name, "Au1xxx PSC I2C", sizeof(priv->adap.name));
408 354
409 /* Now, set up the PSC for SMBus PIO mode. 355 /* Now, set up the PSC for SMBus PIO mode. */
410 */
411 i2c_au1550_setup(priv); 356 i2c_au1550_setup(priv);
412 357
413 ret = i2c_add_numbered_adapter(&priv->adap); 358 ret = i2c_add_numbered_adapter(&priv->adap);
@@ -417,7 +362,8 @@ i2c_au1550_probe(struct platform_device *pdev)
417 } 362 }
418 363
419 i2c_au1550_disable(priv); 364 i2c_au1550_disable(priv);
420 365 iounmap(priv->psc_base);
366out_map:
421 release_resource(priv->ioarea); 367 release_resource(priv->ioarea);
422 kfree(priv->ioarea); 368 kfree(priv->ioarea);
423out_mem: 369out_mem:
@@ -426,14 +372,14 @@ out:
426 return ret; 372 return ret;
427} 373}
428 374
429static int __devexit 375static int __devexit i2c_au1550_remove(struct platform_device *pdev)
430i2c_au1550_remove(struct platform_device *pdev)
431{ 376{
432 struct i2c_au1550_data *priv = platform_get_drvdata(pdev); 377 struct i2c_au1550_data *priv = platform_get_drvdata(pdev);
433 378
434 platform_set_drvdata(pdev, NULL); 379 platform_set_drvdata(pdev, NULL);
435 i2c_del_adapter(&priv->adap); 380 i2c_del_adapter(&priv->adap);
436 i2c_au1550_disable(priv); 381 i2c_au1550_disable(priv);
382 iounmap(priv->psc_base);
437 release_resource(priv->ioarea); 383 release_resource(priv->ioarea);
438 kfree(priv->ioarea); 384 kfree(priv->ioarea);
439 kfree(priv); 385 kfree(priv);
@@ -441,49 +387,51 @@ i2c_au1550_remove(struct platform_device *pdev)
441} 387}
442 388
443#ifdef CONFIG_PM 389#ifdef CONFIG_PM
444static int 390static int i2c_au1550_suspend(struct device *dev)
445i2c_au1550_suspend(struct platform_device *pdev, pm_message_t state)
446{ 391{
447 struct i2c_au1550_data *priv = platform_get_drvdata(pdev); 392 struct i2c_au1550_data *priv = dev_get_drvdata(dev);
448 393
449 i2c_au1550_disable(priv); 394 i2c_au1550_disable(priv);
450 395
451 return 0; 396 return 0;
452} 397}
453 398
454static int 399static int i2c_au1550_resume(struct device *dev)
455i2c_au1550_resume(struct platform_device *pdev)
456{ 400{
457 struct i2c_au1550_data *priv = platform_get_drvdata(pdev); 401 struct i2c_au1550_data *priv = dev_get_drvdata(dev);
458 402
459 i2c_au1550_setup(priv); 403 i2c_au1550_setup(priv);
460 404
461 return 0; 405 return 0;
462} 406}
407
408static const struct dev_pm_ops i2c_au1550_pmops = {
409 .suspend = i2c_au1550_suspend,
410 .resume = i2c_au1550_resume,
411};
412
413#define AU1XPSC_SMBUS_PMOPS (&i2c_au1550_pmops)
414
463#else 415#else
464#define i2c_au1550_suspend NULL 416#define AU1XPSC_SMBUS_PMOPS NULL
465#define i2c_au1550_resume NULL
466#endif 417#endif
467 418
468static struct platform_driver au1xpsc_smbus_driver = { 419static struct platform_driver au1xpsc_smbus_driver = {
469 .driver = { 420 .driver = {
470 .name = "au1xpsc_smbus", 421 .name = "au1xpsc_smbus",
471 .owner = THIS_MODULE, 422 .owner = THIS_MODULE,
423 .pm = AU1XPSC_SMBUS_PMOPS,
472 }, 424 },
473 .probe = i2c_au1550_probe, 425 .probe = i2c_au1550_probe,
474 .remove = __devexit_p(i2c_au1550_remove), 426 .remove = __devexit_p(i2c_au1550_remove),
475 .suspend = i2c_au1550_suspend,
476 .resume = i2c_au1550_resume,
477}; 427};
478 428
479static int __init 429static int __init i2c_au1550_init(void)
480i2c_au1550_init(void)
481{ 430{
482 return platform_driver_register(&au1xpsc_smbus_driver); 431 return platform_driver_register(&au1xpsc_smbus_driver);
483} 432}
484 433
485static void __exit 434static void __exit i2c_au1550_exit(void)
486i2c_au1550_exit(void)
487{ 435{
488 platform_driver_unregister(&au1xpsc_smbus_driver); 436 platform_driver_unregister(&au1xpsc_smbus_driver);
489} 437}
diff --git a/drivers/i2c/busses/i2c-eg20t.c b/drivers/i2c/busses/i2c-eg20t.c
index ce1a32b71e47..8cebef49aeac 100644
--- a/drivers/i2c/busses/i2c-eg20t.c
+++ b/drivers/i2c/busses/i2c-eg20t.c
@@ -64,6 +64,7 @@
64#define TEN_BIT_ADDR_DEFAULT 0xF000 64#define TEN_BIT_ADDR_DEFAULT 0xF000
65#define TEN_BIT_ADDR_MASK 0xF0 65#define TEN_BIT_ADDR_MASK 0xF0
66#define PCH_START 0x0020 66#define PCH_START 0x0020
67#define PCH_RESTART 0x0004
67#define PCH_ESR_START 0x0001 68#define PCH_ESR_START 0x0001
68#define PCH_BUFF_START 0x1 69#define PCH_BUFF_START 0x1
69#define PCH_REPSTART 0x0004 70#define PCH_REPSTART 0x0004
@@ -273,23 +274,24 @@ static s32 pch_i2c_wait_for_bus_idle(struct i2c_algo_pch_data *adap,
273 s32 timeout) 274 s32 timeout)
274{ 275{
275 void __iomem *p = adap->pch_base_address; 276 void __iomem *p = adap->pch_base_address;
277 ktime_t ns_val;
278
279 if ((ioread32(p + PCH_I2CSR) & I2CMBB_BIT) == 0)
280 return 0;
276 281
277 /* MAX timeout value is timeout*1000*1000nsec */ 282 /* MAX timeout value is timeout*1000*1000nsec */
278 ktime_t ns_val = ktime_add_ns(ktime_get(), timeout*1000*1000); 283 ns_val = ktime_add_ns(ktime_get(), timeout*1000*1000);
279 do { 284 do {
280 if ((ioread32(p + PCH_I2CSR) & I2CMBB_BIT) == 0)
281 break;
282 msleep(20); 285 msleep(20);
286 if ((ioread32(p + PCH_I2CSR) & I2CMBB_BIT) == 0)
287 return 0;
283 } while (ktime_lt(ktime_get(), ns_val)); 288 } while (ktime_lt(ktime_get(), ns_val));
284 289
285 pch_dbg(adap, "I2CSR = %x\n", ioread32(p + PCH_I2CSR)); 290 pch_dbg(adap, "I2CSR = %x\n", ioread32(p + PCH_I2CSR));
291 pch_err(adap, "%s: Timeout Error.return%d\n", __func__, -ETIME);
292 pch_i2c_init(adap);
286 293
287 if (timeout == 0) { 294 return -ETIME;
288 pch_err(adap, "%s: Timeout Error.return%d\n", __func__, -ETIME);
289 return -ETIME;
290 }
291
292 return 0;
293} 295}
294 296
295/** 297/**
@@ -311,21 +313,19 @@ static void pch_i2c_start(struct i2c_algo_pch_data *adap)
311 */ 313 */
312static s32 pch_i2c_wait_for_xfer_complete(struct i2c_algo_pch_data *adap) 314static s32 pch_i2c_wait_for_xfer_complete(struct i2c_algo_pch_data *adap)
313{ 315{
314 s32 ret; 316 long ret;
315 ret = wait_event_timeout(pch_event, 317 ret = wait_event_timeout(pch_event,
316 (adap->pch_event_flag != 0), msecs_to_jiffies(50)); 318 (adap->pch_event_flag != 0), msecs_to_jiffies(50));
317 if (ret < 0) {
318 pch_err(adap, "timeout: %x\n", adap->pch_event_flag);
319 return ret;
320 }
321 319
322 if (ret == 0) { 320 if (ret == 0) {
323 pch_err(adap, "timeout: %x\n", adap->pch_event_flag); 321 pch_err(adap, "timeout: %x\n", adap->pch_event_flag);
322 adap->pch_event_flag = 0;
324 return -ETIMEDOUT; 323 return -ETIMEDOUT;
325 } 324 }
326 325
327 if (adap->pch_event_flag & I2C_ERROR_MASK) { 326 if (adap->pch_event_flag & I2C_ERROR_MASK) {
328 pch_err(adap, "error bits set: %x\n", adap->pch_event_flag); 327 pch_err(adap, "error bits set: %x\n", adap->pch_event_flag);
328 adap->pch_event_flag = 0;
329 return -EIO; 329 return -EIO;
330 } 330 }
331 331
@@ -394,6 +394,7 @@ static s32 pch_i2c_writebytes(struct i2c_adapter *i2c_adap,
394 u32 addr_2_msb; 394 u32 addr_2_msb;
395 u32 addr_8_lsb; 395 u32 addr_8_lsb;
396 s32 wrcount; 396 s32 wrcount;
397 s32 rtn;
397 void __iomem *p = adap->pch_base_address; 398 void __iomem *p = adap->pch_base_address;
398 399
399 length = msgs->len; 400 length = msgs->len;
@@ -412,15 +413,29 @@ static s32 pch_i2c_writebytes(struct i2c_adapter *i2c_adap,
412 } 413 }
413 414
414 if (msgs->flags & I2C_M_TEN) { 415 if (msgs->flags & I2C_M_TEN) {
415 addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7); 416 addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7) & 0x06;
416 iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR); 417 iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
417 if (first) 418 if (first)
418 pch_i2c_start(adap); 419 pch_i2c_start(adap);
419 if (pch_i2c_wait_for_xfer_complete(adap) == 0 && 420
420 pch_i2c_getack(adap) == 0) { 421 rtn = pch_i2c_wait_for_xfer_complete(adap);
422 if (rtn == 0) {
423 if (pch_i2c_getack(adap)) {
424 pch_dbg(adap, "Receive NACK for slave address"
425 "setting\n");
426 return -EIO;
427 }
421 addr_8_lsb = (addr & I2C_ADDR_MSK); 428 addr_8_lsb = (addr & I2C_ADDR_MSK);
422 iowrite32(addr_8_lsb, p + PCH_I2CDR); 429 iowrite32(addr_8_lsb, p + PCH_I2CDR);
423 } else { 430 } else if (rtn == -EIO) { /* Arbitration Lost */
431 pch_err(adap, "Lost Arbitration\n");
432 pch_clrbit(adap->pch_base_address, PCH_I2CSR,
433 I2CMAL_BIT);
434 pch_clrbit(adap->pch_base_address, PCH_I2CSR,
435 I2CMIF_BIT);
436 pch_i2c_init(adap);
437 return -EAGAIN;
438 } else { /* wait-event timeout */
424 pch_i2c_stop(adap); 439 pch_i2c_stop(adap);
425 return -ETIME; 440 return -ETIME;
426 } 441 }
@@ -431,30 +446,51 @@ static s32 pch_i2c_writebytes(struct i2c_adapter *i2c_adap,
431 pch_i2c_start(adap); 446 pch_i2c_start(adap);
432 } 447 }
433 448
434 if ((pch_i2c_wait_for_xfer_complete(adap) == 0) && 449 rtn = pch_i2c_wait_for_xfer_complete(adap);
435 (pch_i2c_getack(adap) == 0)) { 450 if (rtn == 0) {
436 for (wrcount = 0; wrcount < length; ++wrcount) { 451 if (pch_i2c_getack(adap)) {
437 /* write buffer value to I2C data register */ 452 pch_dbg(adap, "Receive NACK for slave address"
438 iowrite32(buf[wrcount], p + PCH_I2CDR); 453 "setting\n");
439 pch_dbg(adap, "writing %x to Data register\n", 454 return -EIO;
440 buf[wrcount]); 455 }
456 } else if (rtn == -EIO) { /* Arbitration Lost */
457 pch_err(adap, "Lost Arbitration\n");
458 pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMAL_BIT);
459 pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMIF_BIT);
460 pch_i2c_init(adap);
461 return -EAGAIN;
462 } else { /* wait-event timeout */
463 pch_i2c_stop(adap);
464 return -ETIME;
465 }
441 466
442 if (pch_i2c_wait_for_xfer_complete(adap) != 0) 467 for (wrcount = 0; wrcount < length; ++wrcount) {
443 return -ETIME; 468 /* write buffer value to I2C data register */
469 iowrite32(buf[wrcount], p + PCH_I2CDR);
470 pch_dbg(adap, "writing %x to Data register\n", buf[wrcount]);
444 471
445 if (pch_i2c_getack(adap)) 472 rtn = pch_i2c_wait_for_xfer_complete(adap);
473 if (rtn == 0) {
474 if (pch_i2c_getack(adap)) {
475 pch_dbg(adap, "Receive NACK for slave address"
476 "setting\n");
446 return -EIO; 477 return -EIO;
478 }
479 pch_clrbit(adap->pch_base_address, PCH_I2CSR,
480 I2CMCF_BIT);
481 pch_clrbit(adap->pch_base_address, PCH_I2CSR,
482 I2CMIF_BIT);
483 } else { /* wait-event timeout */
484 pch_i2c_stop(adap);
485 return -ETIME;
447 } 486 }
487 }
448 488
449 /* check if this is the last message */ 489 /* check if this is the last message */
450 if (last) 490 if (last)
451 pch_i2c_stop(adap);
452 else
453 pch_i2c_repstart(adap);
454 } else {
455 pch_i2c_stop(adap); 491 pch_i2c_stop(adap);
456 return -EIO; 492 else
457 } 493 pch_i2c_repstart(adap);
458 494
459 pch_dbg(adap, "return=%d\n", wrcount); 495 pch_dbg(adap, "return=%d\n", wrcount);
460 496
@@ -484,6 +520,19 @@ static void pch_i2c_sendnack(struct i2c_algo_pch_data *adap)
484} 520}
485 521
486/** 522/**
523 * pch_i2c_restart() - Generate I2C restart condition in normal mode.
524 * @adap: Pointer to struct i2c_algo_pch_data.
525 *
526 * Generate I2C restart condition in normal mode by setting I2CCTL.I2CRSTA.
527 */
528static void pch_i2c_restart(struct i2c_algo_pch_data *adap)
529{
530 void __iomem *p = adap->pch_base_address;
531 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
532 pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_RESTART);
533}
534
535/**
487 * pch_i2c_readbytes() - read data from I2C bus in normal mode. 536 * pch_i2c_readbytes() - read data from I2C bus in normal mode.
488 * @i2c_adap: Pointer to the struct i2c_adapter. 537 * @i2c_adap: Pointer to the struct i2c_adapter.
489 * @msgs: Pointer to i2c_msg structure. 538 * @msgs: Pointer to i2c_msg structure.
@@ -500,7 +549,9 @@ static s32 pch_i2c_readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
500 u32 length; 549 u32 length;
501 u32 addr; 550 u32 addr;
502 u32 addr_2_msb; 551 u32 addr_2_msb;
552 u32 addr_8_lsb;
503 void __iomem *p = adap->pch_base_address; 553 void __iomem *p = adap->pch_base_address;
554 s32 rtn;
504 555
505 length = msgs->len; 556 length = msgs->len;
506 buf = msgs->buf; 557 buf = msgs->buf;
@@ -515,9 +566,55 @@ static s32 pch_i2c_readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
515 } 566 }
516 567
517 if (msgs->flags & I2C_M_TEN) { 568 if (msgs->flags & I2C_M_TEN) {
518 addr_2_msb = (((addr & I2C_MSB_2B_MSK) >> 7) | (I2C_RD)); 569 addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7);
519 iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR); 570 iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
571 if (first)
572 pch_i2c_start(adap);
520 573
574 rtn = pch_i2c_wait_for_xfer_complete(adap);
575 if (rtn == 0) {
576 if (pch_i2c_getack(adap)) {
577 pch_dbg(adap, "Receive NACK for slave address"
578 "setting\n");
579 return -EIO;
580 }
581 addr_8_lsb = (addr & I2C_ADDR_MSK);
582 iowrite32(addr_8_lsb, p + PCH_I2CDR);
583 } else if (rtn == -EIO) { /* Arbitration Lost */
584 pch_err(adap, "Lost Arbitration\n");
585 pch_clrbit(adap->pch_base_address, PCH_I2CSR,
586 I2CMAL_BIT);
587 pch_clrbit(adap->pch_base_address, PCH_I2CSR,
588 I2CMIF_BIT);
589 pch_i2c_init(adap);
590 return -EAGAIN;
591 } else { /* wait-event timeout */
592 pch_i2c_stop(adap);
593 return -ETIME;
594 }
595 pch_i2c_restart(adap);
596 rtn = pch_i2c_wait_for_xfer_complete(adap);
597 if (rtn == 0) {
598 if (pch_i2c_getack(adap)) {
599 pch_dbg(adap, "Receive NACK for slave address"
600 "setting\n");
601 return -EIO;
602 }
603 addr_2_msb |= I2C_RD;
604 iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK,
605 p + PCH_I2CDR);
606 } else if (rtn == -EIO) { /* Arbitration Lost */
607 pch_err(adap, "Lost Arbitration\n");
608 pch_clrbit(adap->pch_base_address, PCH_I2CSR,
609 I2CMAL_BIT);
610 pch_clrbit(adap->pch_base_address, PCH_I2CSR,
611 I2CMIF_BIT);
612 pch_i2c_init(adap);
613 return -EAGAIN;
614 } else { /* wait-event timeout */
615 pch_i2c_stop(adap);
616 return -ETIME;
617 }
521 } else { 618 } else {
522 /* 7 address bits + R/W bit */ 619 /* 7 address bits + R/W bit */
523 addr = (((addr) << 1) | (I2C_RD)); 620 addr = (((addr) << 1) | (I2C_RD));
@@ -528,56 +625,81 @@ static s32 pch_i2c_readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
528 if (first) 625 if (first)
529 pch_i2c_start(adap); 626 pch_i2c_start(adap);
530 627
531 if ((pch_i2c_wait_for_xfer_complete(adap) == 0) && 628 rtn = pch_i2c_wait_for_xfer_complete(adap);
532 (pch_i2c_getack(adap) == 0)) { 629 if (rtn == 0) {
533 pch_dbg(adap, "return %d\n", 0); 630 if (pch_i2c_getack(adap)) {
631 pch_dbg(adap, "Receive NACK for slave address"
632 "setting\n");
633 return -EIO;
634 }
635 } else if (rtn == -EIO) { /* Arbitration Lost */
636 pch_err(adap, "Lost Arbitration\n");
637 pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMAL_BIT);
638 pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMIF_BIT);
639 pch_i2c_init(adap);
640 return -EAGAIN;
641 } else { /* wait-event timeout */
642 pch_i2c_stop(adap);
643 return -ETIME;
644 }
534 645
535 if (length == 0) { 646 if (length == 0) {
536 pch_i2c_stop(adap); 647 pch_i2c_stop(adap);
537 ioread32(p + PCH_I2CDR); /* Dummy read needs */ 648 ioread32(p + PCH_I2CDR); /* Dummy read needs */
538 649
539 count = length; 650 count = length;
540 } else { 651 } else {
541 int read_index; 652 int read_index;
542 int loop; 653 int loop;
543 pch_i2c_sendack(adap); 654 pch_i2c_sendack(adap);
544 655
545 /* Dummy read */ 656 /* Dummy read */
546 for (loop = 1, read_index = 0; loop < length; loop++) { 657 for (loop = 1, read_index = 0; loop < length; loop++) {
547 buf[read_index] = ioread32(p + PCH_I2CDR); 658 buf[read_index] = ioread32(p + PCH_I2CDR);
548 659
549 if (loop != 1) 660 if (loop != 1)
550 read_index++; 661 read_index++;
551 662
552 if (pch_i2c_wait_for_xfer_complete(adap) != 0) { 663 rtn = pch_i2c_wait_for_xfer_complete(adap);
553 pch_i2c_stop(adap); 664 if (rtn == 0) {
554 return -ETIME; 665 if (pch_i2c_getack(adap)) {
666 pch_dbg(adap, "Receive NACK for slave"
667 "address setting\n");
668 return -EIO;
555 } 669 }
556 } /* end for */ 670 } else { /* wait-event timeout */
671 pch_i2c_stop(adap);
672 return -ETIME;
673 }
557 674
558 pch_i2c_sendnack(adap); 675 } /* end for */
559 676
560 buf[read_index] = ioread32(p + PCH_I2CDR); 677 pch_i2c_sendnack(adap);
561 678
562 if (length != 1) 679 buf[read_index] = ioread32(p + PCH_I2CDR); /* Read final - 1 */
563 read_index++;
564 680
565 if (pch_i2c_wait_for_xfer_complete(adap) == 0) { 681 if (length != 1)
566 if (last) 682 read_index++;
567 pch_i2c_stop(adap);
568 else
569 pch_i2c_repstart(adap);
570 683
571 buf[read_index++] = ioread32(p + PCH_I2CDR); 684 rtn = pch_i2c_wait_for_xfer_complete(adap);
572 count = read_index; 685 if (rtn == 0) {
573 } else { 686 if (pch_i2c_getack(adap)) {
574 count = -ETIME; 687 pch_dbg(adap, "Receive NACK for slave"
688 "address setting\n");
689 return -EIO;
575 } 690 }
576 691 } else { /* wait-event timeout */
692 pch_i2c_stop(adap);
693 return -ETIME;
577 } 694 }
578 } else { 695
579 count = -ETIME; 696 if (last)
580 pch_i2c_stop(adap); 697 pch_i2c_stop(adap);
698 else
699 pch_i2c_repstart(adap);
700
701 buf[read_index++] = ioread32(p + PCH_I2CDR); /* Read Final */
702 count = read_index;
581 } 703 }
582 704
583 return count; 705 return count;
diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c
index 4c2a62b75b5c..58832e578fff 100644
--- a/drivers/i2c/busses/i2c-imx.c
+++ b/drivers/i2c/busses/i2c-imx.c
@@ -48,6 +48,9 @@
48#include <linux/platform_device.h> 48#include <linux/platform_device.h>
49#include <linux/clk.h> 49#include <linux/clk.h>
50#include <linux/slab.h> 50#include <linux/slab.h>
51#include <linux/of.h>
52#include <linux/of_device.h>
53#include <linux/of_i2c.h>
51 54
52#include <mach/irqs.h> 55#include <mach/irqs.h>
53#include <mach/hardware.h> 56#include <mach/hardware.h>
@@ -125,6 +128,11 @@ struct imx_i2c_struct {
125 unsigned int ifdr; /* IMX_I2C_IFDR */ 128 unsigned int ifdr; /* IMX_I2C_IFDR */
126}; 129};
127 130
131static const struct of_device_id i2c_imx_dt_ids[] = {
132 { .compatible = "fsl,imx1-i2c", },
133 { /* sentinel */ }
134};
135
128/** Functions for IMX I2C adapter driver *************************************** 136/** Functions for IMX I2C adapter driver ***************************************
129*******************************************************************************/ 137*******************************************************************************/
130 138
@@ -466,10 +474,10 @@ static int __init i2c_imx_probe(struct platform_device *pdev)
466{ 474{
467 struct imx_i2c_struct *i2c_imx; 475 struct imx_i2c_struct *i2c_imx;
468 struct resource *res; 476 struct resource *res;
469 struct imxi2c_platform_data *pdata; 477 struct imxi2c_platform_data *pdata = pdev->dev.platform_data;
470 void __iomem *base; 478 void __iomem *base;
471 resource_size_t res_size; 479 resource_size_t res_size;
472 int irq; 480 int irq, bitrate;
473 int ret; 481 int ret;
474 482
475 dev_dbg(&pdev->dev, "<%s>\n", __func__); 483 dev_dbg(&pdev->dev, "<%s>\n", __func__);
@@ -485,19 +493,11 @@ static int __init i2c_imx_probe(struct platform_device *pdev)
485 return -ENOENT; 493 return -ENOENT;
486 } 494 }
487 495
488 pdata = pdev->dev.platform_data;
489
490 if (pdata && pdata->init) {
491 ret = pdata->init(&pdev->dev);
492 if (ret)
493 return ret;
494 }
495
496 res_size = resource_size(res); 496 res_size = resource_size(res);
497 497
498 if (!request_mem_region(res->start, res_size, DRIVER_NAME)) { 498 if (!request_mem_region(res->start, res_size, DRIVER_NAME)) {
499 ret = -EBUSY; 499 dev_err(&pdev->dev, "request_mem_region failed\n");
500 goto fail0; 500 return -EBUSY;
501 } 501 }
502 502
503 base = ioremap(res->start, res_size); 503 base = ioremap(res->start, res_size);
@@ -520,6 +520,7 @@ static int __init i2c_imx_probe(struct platform_device *pdev)
520 i2c_imx->adapter.algo = &i2c_imx_algo; 520 i2c_imx->adapter.algo = &i2c_imx_algo;
521 i2c_imx->adapter.dev.parent = &pdev->dev; 521 i2c_imx->adapter.dev.parent = &pdev->dev;
522 i2c_imx->adapter.nr = pdev->id; 522 i2c_imx->adapter.nr = pdev->id;
523 i2c_imx->adapter.dev.of_node = pdev->dev.of_node;
523 i2c_imx->irq = irq; 524 i2c_imx->irq = irq;
524 i2c_imx->base = base; 525 i2c_imx->base = base;
525 i2c_imx->res = res; 526 i2c_imx->res = res;
@@ -546,10 +547,12 @@ static int __init i2c_imx_probe(struct platform_device *pdev)
546 i2c_set_adapdata(&i2c_imx->adapter, i2c_imx); 547 i2c_set_adapdata(&i2c_imx->adapter, i2c_imx);
547 548
548 /* Set up clock divider */ 549 /* Set up clock divider */
549 if (pdata && pdata->bitrate) 550 bitrate = IMX_I2C_BIT_RATE;
550 i2c_imx_set_clk(i2c_imx, pdata->bitrate); 551 ret = of_property_read_u32(pdev->dev.of_node,
551 else 552 "clock-frequency", &bitrate);
552 i2c_imx_set_clk(i2c_imx, IMX_I2C_BIT_RATE); 553 if (ret < 0 && pdata && pdata->bitrate)
554 bitrate = pdata->bitrate;
555 i2c_imx_set_clk(i2c_imx, bitrate);
553 556
554 /* Set up chip registers to defaults */ 557 /* Set up chip registers to defaults */
555 writeb(0, i2c_imx->base + IMX_I2C_I2CR); 558 writeb(0, i2c_imx->base + IMX_I2C_I2CR);
@@ -562,6 +565,8 @@ static int __init i2c_imx_probe(struct platform_device *pdev)
562 goto fail5; 565 goto fail5;
563 } 566 }
564 567
568 of_i2c_register_devices(&i2c_imx->adapter);
569
565 /* Set up platform driver data */ 570 /* Set up platform driver data */
566 platform_set_drvdata(pdev, i2c_imx); 571 platform_set_drvdata(pdev, i2c_imx);
567 572
@@ -586,16 +591,12 @@ fail2:
586 iounmap(base); 591 iounmap(base);
587fail1: 592fail1:
588 release_mem_region(res->start, resource_size(res)); 593 release_mem_region(res->start, resource_size(res));
589fail0:
590 if (pdata && pdata->exit)
591 pdata->exit(&pdev->dev);
592 return ret; /* Return error number */ 594 return ret; /* Return error number */
593} 595}
594 596
595static int __exit i2c_imx_remove(struct platform_device *pdev) 597static int __exit i2c_imx_remove(struct platform_device *pdev)
596{ 598{
597 struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev); 599 struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev);
598 struct imxi2c_platform_data *pdata = pdev->dev.platform_data;
599 600
600 /* remove adapter */ 601 /* remove adapter */
601 dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n"); 602 dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n");
@@ -611,10 +612,6 @@ static int __exit i2c_imx_remove(struct platform_device *pdev)
611 writeb(0, i2c_imx->base + IMX_I2C_I2CR); 612 writeb(0, i2c_imx->base + IMX_I2C_I2CR);
612 writeb(0, i2c_imx->base + IMX_I2C_I2SR); 613 writeb(0, i2c_imx->base + IMX_I2C_I2SR);
613 614
614 /* Shut down hardware */
615 if (pdata && pdata->exit)
616 pdata->exit(&pdev->dev);
617
618 clk_put(i2c_imx->clk); 615 clk_put(i2c_imx->clk);
619 616
620 iounmap(i2c_imx->base); 617 iounmap(i2c_imx->base);
@@ -628,6 +625,7 @@ static struct platform_driver i2c_imx_driver = {
628 .driver = { 625 .driver = {
629 .name = DRIVER_NAME, 626 .name = DRIVER_NAME,
630 .owner = THIS_MODULE, 627 .owner = THIS_MODULE,
628 .of_match_table = i2c_imx_dt_ids,
631 } 629 }
632}; 630};
633 631
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 2dfb63176856..a43d0023446a 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -42,12 +42,12 @@
42#include <linux/pm_runtime.h> 42#include <linux/pm_runtime.h>
43 43
44/* I2C controller revisions */ 44/* I2C controller revisions */
45#define OMAP_I2C_REV_2 0x20 45#define OMAP_I2C_OMAP1_REV_2 0x20
46 46
47/* I2C controller revisions present on specific hardware */ 47/* I2C controller revisions present on specific hardware */
48#define OMAP_I2C_REV_ON_2430 0x36 48#define OMAP_I2C_REV_ON_2430 0x36
49#define OMAP_I2C_REV_ON_3430 0x3C 49#define OMAP_I2C_REV_ON_3430 0x3C
50#define OMAP_I2C_REV_ON_4430 0x40 50#define OMAP_I2C_REV_ON_3530_4430 0x40
51 51
52/* timeout waiting for the controller to respond */ 52/* timeout waiting for the controller to respond */
53#define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000)) 53#define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
@@ -72,11 +72,12 @@ enum {
72 OMAP_I2C_SCLH_REG, 72 OMAP_I2C_SCLH_REG,
73 OMAP_I2C_SYSTEST_REG, 73 OMAP_I2C_SYSTEST_REG,
74 OMAP_I2C_BUFSTAT_REG, 74 OMAP_I2C_BUFSTAT_REG,
75 OMAP_I2C_REVNB_LO, 75 /* only on OMAP4430 */
76 OMAP_I2C_REVNB_HI, 76 OMAP_I2C_IP_V2_REVNB_LO,
77 OMAP_I2C_IRQSTATUS_RAW, 77 OMAP_I2C_IP_V2_REVNB_HI,
78 OMAP_I2C_IRQENABLE_SET, 78 OMAP_I2C_IP_V2_IRQSTATUS_RAW,
79 OMAP_I2C_IRQENABLE_CLR, 79 OMAP_I2C_IP_V2_IRQENABLE_SET,
80 OMAP_I2C_IP_V2_IRQENABLE_CLR,
80}; 81};
81 82
82/* I2C Interrupt Enable Register (OMAP_I2C_IE): */ 83/* I2C Interrupt Enable Register (OMAP_I2C_IE): */
@@ -193,7 +194,6 @@ struct omap_i2c_dev {
193 */ 194 */
194 u8 rev; 195 u8 rev;
195 unsigned b_hw:1; /* bad h/w fixes */ 196 unsigned b_hw:1; /* bad h/w fixes */
196 unsigned idle:1;
197 u16 iestate; /* Saved interrupt register */ 197 u16 iestate; /* Saved interrupt register */
198 u16 pscstate; 198 u16 pscstate;
199 u16 scllstate; 199 u16 scllstate;
@@ -204,7 +204,7 @@ struct omap_i2c_dev {
204 u16 errata; 204 u16 errata;
205}; 205};
206 206
207static const u8 reg_map[] = { 207static const u8 reg_map_ip_v1[] = {
208 [OMAP_I2C_REV_REG] = 0x00, 208 [OMAP_I2C_REV_REG] = 0x00,
209 [OMAP_I2C_IE_REG] = 0x01, 209 [OMAP_I2C_IE_REG] = 0x01,
210 [OMAP_I2C_STAT_REG] = 0x02, 210 [OMAP_I2C_STAT_REG] = 0x02,
@@ -225,7 +225,7 @@ static const u8 reg_map[] = {
225 [OMAP_I2C_BUFSTAT_REG] = 0x10, 225 [OMAP_I2C_BUFSTAT_REG] = 0x10,
226}; 226};
227 227
228static const u8 omap4_reg_map[] = { 228static const u8 reg_map_ip_v2[] = {
229 [OMAP_I2C_REV_REG] = 0x04, 229 [OMAP_I2C_REV_REG] = 0x04,
230 [OMAP_I2C_IE_REG] = 0x2c, 230 [OMAP_I2C_IE_REG] = 0x2c,
231 [OMAP_I2C_STAT_REG] = 0x28, 231 [OMAP_I2C_STAT_REG] = 0x28,
@@ -244,11 +244,11 @@ static const u8 omap4_reg_map[] = {
244 [OMAP_I2C_SCLH_REG] = 0xb8, 244 [OMAP_I2C_SCLH_REG] = 0xb8,
245 [OMAP_I2C_SYSTEST_REG] = 0xbC, 245 [OMAP_I2C_SYSTEST_REG] = 0xbC,
246 [OMAP_I2C_BUFSTAT_REG] = 0xc0, 246 [OMAP_I2C_BUFSTAT_REG] = 0xc0,
247 [OMAP_I2C_REVNB_LO] = 0x00, 247 [OMAP_I2C_IP_V2_REVNB_LO] = 0x00,
248 [OMAP_I2C_REVNB_HI] = 0x04, 248 [OMAP_I2C_IP_V2_REVNB_HI] = 0x04,
249 [OMAP_I2C_IRQSTATUS_RAW] = 0x24, 249 [OMAP_I2C_IP_V2_IRQSTATUS_RAW] = 0x24,
250 [OMAP_I2C_IRQENABLE_SET] = 0x2c, 250 [OMAP_I2C_IP_V2_IRQENABLE_SET] = 0x2c,
251 [OMAP_I2C_IRQENABLE_CLR] = 0x30, 251 [OMAP_I2C_IP_V2_IRQENABLE_CLR] = 0x30,
252}; 252};
253 253
254static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev, 254static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
@@ -266,17 +266,11 @@ static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
266 266
267static void omap_i2c_unidle(struct omap_i2c_dev *dev) 267static void omap_i2c_unidle(struct omap_i2c_dev *dev)
268{ 268{
269 struct platform_device *pdev;
270 struct omap_i2c_bus_platform_data *pdata; 269 struct omap_i2c_bus_platform_data *pdata;
271 270
272 WARN_ON(!dev->idle); 271 pdata = dev->dev->platform_data;
273 272
274 pdev = to_platform_device(dev->dev); 273 if (pdata->flags & OMAP_I2C_FLAG_RESET_REGS_POSTIDLE) {
275 pdata = pdev->dev.platform_data;
276
277 pm_runtime_get_sync(&pdev->dev);
278
279 if (cpu_is_omap34xx()) {
280 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); 274 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
281 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, dev->pscstate); 275 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, dev->pscstate);
282 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, dev->scllstate); 276 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, dev->scllstate);
@@ -286,7 +280,6 @@ static void omap_i2c_unidle(struct omap_i2c_dev *dev)
286 omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate); 280 omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate);
287 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN); 281 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
288 } 282 }
289 dev->idle = 0;
290 283
291 /* 284 /*
292 * Don't write to this register if the IE state is 0 as it can 285 * Don't write to this register if the IE state is 0 as it can
@@ -298,32 +291,25 @@ static void omap_i2c_unidle(struct omap_i2c_dev *dev)
298 291
299static void omap_i2c_idle(struct omap_i2c_dev *dev) 292static void omap_i2c_idle(struct omap_i2c_dev *dev)
300{ 293{
301 struct platform_device *pdev;
302 struct omap_i2c_bus_platform_data *pdata; 294 struct omap_i2c_bus_platform_data *pdata;
303 u16 iv; 295 u16 iv;
304 296
305 WARN_ON(dev->idle); 297 pdata = dev->dev->platform_data;
306
307 pdev = to_platform_device(dev->dev);
308 pdata = pdev->dev.platform_data;
309 298
310 dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG); 299 dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
311 if (dev->rev >= OMAP_I2C_REV_ON_4430) 300 if (pdata->rev == OMAP_I2C_IP_VERSION_2)
312 omap_i2c_write_reg(dev, OMAP_I2C_IRQENABLE_CLR, 1); 301 omap_i2c_write_reg(dev, OMAP_I2C_IP_V2_IRQENABLE_CLR, 1);
313 else 302 else
314 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0); 303 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0);
315 304
316 if (dev->rev < OMAP_I2C_REV_2) { 305 if (dev->rev < OMAP_I2C_OMAP1_REV_2) {
317 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); /* Read clears */ 306 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); /* Read clears */
318 } else { 307 } else {
319 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, dev->iestate); 308 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, dev->iestate);
320 309
321 /* Flush posted write before the dev->idle store occurs */ 310 /* Flush posted write */
322 omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG); 311 omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
323 } 312 }
324 dev->idle = 1;
325
326 pm_runtime_put_sync(&pdev->dev);
327} 313}
328 314
329static int omap_i2c_init(struct omap_i2c_dev *dev) 315static int omap_i2c_init(struct omap_i2c_dev *dev)
@@ -334,8 +320,11 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
334 unsigned long timeout; 320 unsigned long timeout;
335 unsigned long internal_clk = 0; 321 unsigned long internal_clk = 0;
336 struct clk *fclk; 322 struct clk *fclk;
323 struct omap_i2c_bus_platform_data *pdata;
324
325 pdata = dev->dev->platform_data;
337 326
338 if (dev->rev >= OMAP_I2C_REV_2) { 327 if (dev->rev >= OMAP_I2C_OMAP1_REV_2) {
339 /* Disable I2C controller before soft reset */ 328 /* Disable I2C controller before soft reset */
340 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 329 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
341 omap_i2c_read_reg(dev, OMAP_I2C_CON_REG) & 330 omap_i2c_read_reg(dev, OMAP_I2C_CON_REG) &
@@ -378,12 +367,13 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
378 * REVISIT: Some wkup sources might not be needed. 367 * REVISIT: Some wkup sources might not be needed.
379 */ 368 */
380 dev->westate = OMAP_I2C_WE_ALL; 369 dev->westate = OMAP_I2C_WE_ALL;
381 omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate); 370 omap_i2c_write_reg(dev, OMAP_I2C_WE_REG,
371 dev->westate);
382 } 372 }
383 } 373 }
384 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); 374 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
385 375
386 if (cpu_class_is_omap1()) { 376 if (pdata->flags & OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK) {
387 /* 377 /*
388 * The I2C functional clock is the armxor_ck, so there's 378 * The I2C functional clock is the armxor_ck, so there's
389 * no need to get "armxor_ck" separately. Now, if OMAP2420 379 * no need to get "armxor_ck" separately. Now, if OMAP2420
@@ -407,7 +397,7 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
407 psc = fclk_rate / 12000000; 397 psc = fclk_rate / 12000000;
408 } 398 }
409 399
410 if (!(cpu_class_is_omap1() || cpu_is_omap2420())) { 400 if (!(pdata->flags & OMAP_I2C_FLAG_SIMPLE_CLOCK)) {
411 401
412 /* 402 /*
413 * HSI2C controller internal clk rate should be 19.2 Mhz for 403 * HSI2C controller internal clk rate should be 19.2 Mhz for
@@ -415,7 +405,8 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
415 * to get longer filter period for better noise suppression. 405 * to get longer filter period for better noise suppression.
416 * The filter is iclk (fclk for HS) period. 406 * The filter is iclk (fclk for HS) period.
417 */ 407 */
418 if (dev->speed > 400 || cpu_is_omap2430()) 408 if (dev->speed > 400 ||
409 pdata->flags & OMAP_I2C_FLAG_FORCE_19200_INT_CLK)
419 internal_clk = 19200; 410 internal_clk = 19200;
420 else if (dev->speed > 100) 411 else if (dev->speed > 100)
421 internal_clk = 9600; 412 internal_clk = 9600;
@@ -484,7 +475,7 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
484 475
485 dev->errata = 0; 476 dev->errata = 0;
486 477
487 if (cpu_is_omap2430() || cpu_is_omap34xx()) 478 if (pdata->flags & OMAP_I2C_FLAG_APPLY_ERRATA_I207)
488 dev->errata |= I2C_OMAP_ERRATA_I207; 479 dev->errata |= I2C_OMAP_ERRATA_I207;
489 480
490 /* Enable interrupts */ 481 /* Enable interrupts */
@@ -493,7 +484,7 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
493 OMAP_I2C_IE_AL) | ((dev->fifo_size) ? 484 OMAP_I2C_IE_AL) | ((dev->fifo_size) ?
494 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0); 485 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0);
495 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate); 486 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
496 if (cpu_is_omap34xx()) { 487 if (pdata->flags & OMAP_I2C_FLAG_RESET_REGS_POSTIDLE) {
497 dev->pscstate = psc; 488 dev->pscstate = psc;
498 dev->scllstate = scll; 489 dev->scllstate = scll;
499 dev->sclhstate = sclh; 490 dev->sclhstate = sclh;
@@ -642,7 +633,7 @@ omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
642 int i; 633 int i;
643 int r; 634 int r;
644 635
645 omap_i2c_unidle(dev); 636 pm_runtime_get_sync(dev->dev);
646 637
647 r = omap_i2c_wait_for_bb(dev); 638 r = omap_i2c_wait_for_bb(dev);
648 if (r < 0) 639 if (r < 0)
@@ -665,7 +656,7 @@ omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
665 656
666 omap_i2c_wait_for_bb(dev); 657 omap_i2c_wait_for_bb(dev);
667out: 658out:
668 omap_i2c_idle(dev); 659 pm_runtime_put(dev->dev);
669 return r; 660 return r;
670} 661}
671 662
@@ -720,12 +711,12 @@ static inline void i2c_omap_errata_i207(struct omap_i2c_dev *dev, u16 stat)
720#ifdef CONFIG_ARCH_OMAP15XX 711#ifdef CONFIG_ARCH_OMAP15XX
721 712
722static irqreturn_t 713static irqreturn_t
723omap_i2c_rev1_isr(int this_irq, void *dev_id) 714omap_i2c_omap1_isr(int this_irq, void *dev_id)
724{ 715{
725 struct omap_i2c_dev *dev = dev_id; 716 struct omap_i2c_dev *dev = dev_id;
726 u16 iv, w; 717 u16 iv, w;
727 718
728 if (dev->idle) 719 if (pm_runtime_suspended(dev->dev))
729 return IRQ_NONE; 720 return IRQ_NONE;
730 721
731 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); 722 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
@@ -774,7 +765,7 @@ omap_i2c_rev1_isr(int this_irq, void *dev_id)
774 return IRQ_HANDLED; 765 return IRQ_HANDLED;
775} 766}
776#else 767#else
777#define omap_i2c_rev1_isr NULL 768#define omap_i2c_omap1_isr NULL
778#endif 769#endif
779 770
780/* 771/*
@@ -813,8 +804,11 @@ omap_i2c_isr(int this_irq, void *dev_id)
813 u16 bits; 804 u16 bits;
814 u16 stat, w; 805 u16 stat, w;
815 int err, count = 0; 806 int err, count = 0;
807 struct omap_i2c_bus_platform_data *pdata;
816 808
817 if (dev->idle) 809 pdata = dev->dev->platform_data;
810
811 if (pm_runtime_suspended(dev->dev))
818 return IRQ_NONE; 812 return IRQ_NONE;
819 813
820 bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG); 814 bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
@@ -881,8 +875,8 @@ complete:
881 * Data reg in 2430, omap3 and 875 * Data reg in 2430, omap3 and
882 * omap4 is 8 bit wide 876 * omap4 is 8 bit wide
883 */ 877 */
884 if (cpu_class_is_omap1() || 878 if (pdata->flags &
885 cpu_is_omap2420()) { 879 OMAP_I2C_FLAG_16BIT_DATA_REG) {
886 if (dev->buf_len) { 880 if (dev->buf_len) {
887 *dev->buf++ = w >> 8; 881 *dev->buf++ = w >> 8;
888 dev->buf_len--; 882 dev->buf_len--;
@@ -924,8 +918,8 @@ complete:
924 * Data reg in 2430, omap3 and 918 * Data reg in 2430, omap3 and
925 * omap4 is 8 bit wide 919 * omap4 is 8 bit wide
926 */ 920 */
927 if (cpu_class_is_omap1() || 921 if (pdata->flags &
928 cpu_is_omap2420()) { 922 OMAP_I2C_FLAG_16BIT_DATA_REG) {
929 if (dev->buf_len) { 923 if (dev->buf_len) {
930 w |= *dev->buf++ << 8; 924 w |= *dev->buf++ << 8;
931 dev->buf_len--; 925 dev->buf_len--;
@@ -1016,7 +1010,6 @@ omap_i2c_probe(struct platform_device *pdev)
1016 } 1010 }
1017 1011
1018 dev->speed = speed; 1012 dev->speed = speed;
1019 dev->idle = 1;
1020 dev->dev = &pdev->dev; 1013 dev->dev = &pdev->dev;
1021 dev->irq = irq->start; 1014 dev->irq = irq->start;
1022 dev->base = ioremap(mem->start, resource_size(mem)); 1015 dev->base = ioremap(mem->start, resource_size(mem));
@@ -1027,27 +1020,22 @@ omap_i2c_probe(struct platform_device *pdev)
1027 1020
1028 platform_set_drvdata(pdev, dev); 1021 platform_set_drvdata(pdev, dev);
1029 1022
1030 if (cpu_is_omap7xx()) 1023 dev->reg_shift = (pdata->flags >> OMAP_I2C_FLAG_BUS_SHIFT__SHIFT) & 3;
1031 dev->reg_shift = 1;
1032 else if (cpu_is_omap44xx())
1033 dev->reg_shift = 0;
1034 else
1035 dev->reg_shift = 2;
1036 1024
1037 if (cpu_is_omap44xx()) 1025 if (pdata->rev == OMAP_I2C_IP_VERSION_2)
1038 dev->regs = (u8 *) omap4_reg_map; 1026 dev->regs = (u8 *)reg_map_ip_v2;
1039 else 1027 else
1040 dev->regs = (u8 *) reg_map; 1028 dev->regs = (u8 *)reg_map_ip_v1;
1041 1029
1042 pm_runtime_enable(&pdev->dev); 1030 pm_runtime_enable(dev->dev);
1043 omap_i2c_unidle(dev); 1031 pm_runtime_get_sync(dev->dev);
1044 1032
1045 dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff; 1033 dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
1046 1034
1047 if (dev->rev <= OMAP_I2C_REV_ON_3430) 1035 if (dev->rev <= OMAP_I2C_REV_ON_3430)
1048 dev->errata |= I2C_OMAP3_1P153; 1036 dev->errata |= I2C_OMAP3_1P153;
1049 1037
1050 if (!(cpu_class_is_omap1() || cpu_is_omap2420())) { 1038 if (!(pdata->flags & OMAP_I2C_FLAG_NO_FIFO)) {
1051 u16 s; 1039 u16 s;
1052 1040
1053 /* Set up the fifo size - Get total size */ 1041 /* Set up the fifo size - Get total size */
@@ -1059,7 +1047,7 @@ omap_i2c_probe(struct platform_device *pdev)
1059 * size. This is to ensure that we can handle the status on int 1047 * size. This is to ensure that we can handle the status on int
1060 * call back latencies. 1048 * call back latencies.
1061 */ 1049 */
1062 if (dev->rev >= OMAP_I2C_REV_ON_4430) { 1050 if (dev->rev >= OMAP_I2C_REV_ON_3530_4430) {
1063 dev->fifo_size = 0; 1051 dev->fifo_size = 0;
1064 dev->b_hw = 0; /* Disable hardware fixes */ 1052 dev->b_hw = 0; /* Disable hardware fixes */
1065 } else { 1053 } else {
@@ -1075,7 +1063,8 @@ omap_i2c_probe(struct platform_device *pdev)
1075 /* reset ASAP, clearing any IRQs */ 1063 /* reset ASAP, clearing any IRQs */
1076 omap_i2c_init(dev); 1064 omap_i2c_init(dev);
1077 1065
1078 isr = (dev->rev < OMAP_I2C_REV_2) ? omap_i2c_rev1_isr : omap_i2c_isr; 1066 isr = (dev->rev < OMAP_I2C_OMAP1_REV_2) ? omap_i2c_omap1_isr :
1067 omap_i2c_isr;
1079 r = request_irq(dev->irq, isr, 0, pdev->name, dev); 1068 r = request_irq(dev->irq, isr, 0, pdev->name, dev);
1080 1069
1081 if (r) { 1070 if (r) {
@@ -1083,10 +1072,10 @@ omap_i2c_probe(struct platform_device *pdev)
1083 goto err_unuse_clocks; 1072 goto err_unuse_clocks;
1084 } 1073 }
1085 1074
1086 dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n", 1075 dev_info(dev->dev, "bus %d rev%d.%d.%d at %d kHz\n", pdev->id,
1087 pdev->id, dev->rev >> 4, dev->rev & 0xf, dev->speed); 1076 pdata->rev, dev->rev >> 4, dev->rev & 0xf, dev->speed);
1088 1077
1089 omap_i2c_idle(dev); 1078 pm_runtime_put(dev->dev);
1090 1079
1091 adap = &dev->adapter; 1080 adap = &dev->adapter;
1092 i2c_set_adapdata(adap, dev); 1081 i2c_set_adapdata(adap, dev);
@@ -1110,7 +1099,7 @@ err_free_irq:
1110 free_irq(dev->irq, dev); 1099 free_irq(dev->irq, dev);
1111err_unuse_clocks: 1100err_unuse_clocks:
1112 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); 1101 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
1113 omap_i2c_idle(dev); 1102 pm_runtime_put(dev->dev);
1114 iounmap(dev->base); 1103 iounmap(dev->base);
1115err_free_mem: 1104err_free_mem:
1116 platform_set_drvdata(pdev, NULL); 1105 platform_set_drvdata(pdev, NULL);
@@ -1139,12 +1128,43 @@ omap_i2c_remove(struct platform_device *pdev)
1139 return 0; 1128 return 0;
1140} 1129}
1141 1130
1131#ifdef CONFIG_PM_RUNTIME
1132static int omap_i2c_runtime_suspend(struct device *dev)
1133{
1134 struct platform_device *pdev = to_platform_device(dev);
1135 struct omap_i2c_dev *_dev = platform_get_drvdata(pdev);
1136
1137 omap_i2c_idle(_dev);
1138
1139 return 0;
1140}
1141
1142static int omap_i2c_runtime_resume(struct device *dev)
1143{
1144 struct platform_device *pdev = to_platform_device(dev);
1145 struct omap_i2c_dev *_dev = platform_get_drvdata(pdev);
1146
1147 omap_i2c_unidle(_dev);
1148
1149 return 0;
1150}
1151
1152static struct dev_pm_ops omap_i2c_pm_ops = {
1153 .runtime_suspend = omap_i2c_runtime_suspend,
1154 .runtime_resume = omap_i2c_runtime_resume,
1155};
1156#define OMAP_I2C_PM_OPS (&omap_i2c_pm_ops)
1157#else
1158#define OMAP_I2C_PM_OPS NULL
1159#endif
1160
1142static struct platform_driver omap_i2c_driver = { 1161static struct platform_driver omap_i2c_driver = {
1143 .probe = omap_i2c_probe, 1162 .probe = omap_i2c_probe,
1144 .remove = omap_i2c_remove, 1163 .remove = omap_i2c_remove,
1145 .driver = { 1164 .driver = {
1146 .name = "omap_i2c", 1165 .name = "omap_i2c",
1147 .owner = THIS_MODULE, 1166 .owner = THIS_MODULE,
1167 .pm = OMAP_I2C_PM_OPS,
1148 }, 1168 },
1149}; 1169};
1150 1170
diff --git a/include/linux/i2c-omap.h b/include/linux/i2c-omap.h
index 0aa0cbd676f7..92a0dc75bc74 100644
--- a/include/linux/i2c-omap.h
+++ b/include/linux/i2c-omap.h
@@ -32,10 +32,9 @@
32 32
33struct omap_i2c_bus_platform_data { 33struct omap_i2c_bus_platform_data {
34 u32 clkrate; 34 u32 clkrate;
35 u32 rev;
36 u32 flags;
35 void (*set_mpu_wkup_lat)(struct device *dev, long set); 37 void (*set_mpu_wkup_lat)(struct device *dev, long set);
36 int (*device_enable) (struct platform_device *pdev);
37 int (*device_shutdown) (struct platform_device *pdev);
38 int (*device_idle) (struct platform_device *pdev);
39}; 38};
40 39
41#endif 40#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-31 21:21:52 -0500