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-rw-r--r--Documentation/devicetree/bindings/serial/renesas,sci-serial.txt46
-rw-r--r--arch/arm/Kconfig14
-rw-r--r--arch/arm/Makefile1
-rw-r--r--arch/arm/boot/compressed/Makefile2
-rw-r--r--arch/arm/boot/dts/Makefile2
-rw-r--r--arch/arm/configs/ape6evm_defconfig2
-rw-r--r--arch/arm/configs/armadillo800eva_defconfig2
-rw-r--r--arch/arm/configs/bockw_defconfig2
-rw-r--r--arch/arm/configs/koelsch_defconfig2
-rw-r--r--arch/arm/configs/kzm9d_defconfig2
-rw-r--r--arch/arm/configs/kzm9g_defconfig2
-rw-r--r--arch/arm/configs/lager_defconfig2
-rw-r--r--arch/arm/configs/mackerel_defconfig2
-rw-r--r--arch/arm/configs/marzen_defconfig2
-rw-r--r--arch/arm/mach-shmobile/Kconfig24
-rw-r--r--arch/arm/mach-shmobile/Makefile1
-rw-r--r--arch/arm/mach-shmobile/Makefile.boot1
-rw-r--r--arch/arm/mach-shmobile/board-bockw.c1
-rw-r--r--arch/arm/mach-shmobile/board-kzm9d.c92
-rw-r--r--arch/arm/mach-shmobile/clock-r7s72100.c8
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7740.c1
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7778.c31
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7779.c11
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7790.c62
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7791.c17
-rw-r--r--arch/arm/mach-shmobile/clock-sh73a0.c1
-rw-r--r--arch/arm/mach-shmobile/include/mach/emev2.h5
-rw-r--r--arch/arm/mach-shmobile/include/mach/r8a7778.h39
-rw-r--r--arch/arm/mach-shmobile/include/mach/r8a7791.h1
-rw-r--r--arch/arm/mach-shmobile/setup-emev2.c163
-rw-r--r--arch/arm/mach-shmobile/setup-r7s72100.c82
-rw-r--r--arch/arm/mach-shmobile/setup-r8a73a4.c68
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7740.c195
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7778.c166
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7779.c128
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7790.c141
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7791.c188
-rw-r--r--arch/arm/mach-shmobile/setup-rcar-gen2.c29
-rw-r--r--arch/arm/mach-shmobile/setup-sh7372.c160
-rw-r--r--arch/arm/mach-shmobile/setup-sh73a0.c191
-rw-r--r--drivers/Makefile2
-rw-r--r--drivers/tty/serial/sh-sci.c187
-rw-r--r--include/dt-bindings/clock/r8a7790-clock.h100
-rw-r--r--include/dt-bindings/clock/r8a7791-clock.h105
-rw-r--r--include/linux/serial_sci.h36
45 files changed, 1166 insertions, 1153 deletions
diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
new file mode 100644
index 000000000000..f372cf29068d
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
@@ -0,0 +1,46 @@
1* Renesas SH-Mobile Serial Communication Interface
2
3Required properties:
4
5 - compatible: Must contain one of the following:
6
7 - "renesas,scif-r8a7790" for R8A7790 (R-Car H2) SCIF compatible UART.
8 - "renesas,scifa-r8a7790" for R8A7790 (R-Car H2) SCIFA compatible UART.
9 - "renesas,scifb-r8a7790" for R8A7790 (R-Car H2) SCIFB compatible UART.
10 - "renesas,hscif-r8a7790" for R8A7790 (R-Car H2) HSCIF compatible UART.
11 - "renesas,scif-r8a7791" for R8A7791 (R-Car M2) SCIF compatible UART.
12 - "renesas,scifa-r8a7791" for R8A7791 (R-Car M2) SCIFA compatible UART.
13 - "renesas,scifb-r8a7791" for R8A7791 (R-Car M2) SCIFB compatible UART.
14 - "renesas,hscif-r8a7791" for R8A7791 (R-Car M2) HSCIF compatible UART.
15 - "renesas,scif" for generic SCIF compatible UART.
16 - "renesas,scifa" for generic SCIFA compatible UART.
17 - "renesas,scifb" for generic SCIFB compatible UART.
18 - "renesas,hscif" for generic HSCIF compatible UART.
19
20 When compatible with the generic version, nodes must list the
21 SoC-specific version corresponding to the platform first followed by the
22 generic version.
23
24 - reg: Base address and length of the I/O registers used by the UART.
25 - interrupts: Must contain an interrupt-specifier for the SCIx interrupt.
26
27 - clocks: Must contain a phandle and clock-specifier pair for each entry
28 in clock-names.
29 - clock-names: Must contain "sci_ick" for the SCIx UART interface clock.
30
31Note: Each enabled SCIx UART should have an alias correctly numbered in the
32"aliases" node.
33
34Example:
35 aliases {
36 serial0 = &scifa0;
37 };
38
39 scifa0: serial@e6c40000 {
40 compatible = "renesas,scifa-r8a7790", "renesas,scifa-generic";
41 reg = <0 0xe6c40000 0 64>;
42 interrupt-parent = <&gic>;
43 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
44 clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>;
45 clock-names = "sci_ick";
46 };
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index ab8f2eb731bb..8b768937c663 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -644,8 +644,9 @@ config ARCH_MSM
644 stack and controls some vital subsystems 644 stack and controls some vital subsystems
645 (clock and power control, etc). 645 (clock and power control, etc).
646 646
647config ARCH_SHMOBILE 647config ARCH_SHMOBILE_LEGACY
648 bool "Renesas SH-Mobile / R-Mobile" 648 bool "Renesas SH-Mobile / R-Mobile (non-multiplatform)"
649 select ARCH_SHMOBILE
649 select ARM_PATCH_PHYS_VIRT 650 select ARM_PATCH_PHYS_VIRT
650 select CLKDEV_LOOKUP 651 select CLKDEV_LOOKUP
651 select GENERIC_CLOCKEVENTS 652 select GENERIC_CLOCKEVENTS
@@ -660,7 +661,8 @@ config ARCH_SHMOBILE
660 select PM_GENERIC_DOMAINS if PM 661 select PM_GENERIC_DOMAINS if PM
661 select SPARSE_IRQ 662 select SPARSE_IRQ
662 help 663 help
663 Support for Renesas's SH-Mobile and R-Mobile ARM platforms. 664 Support for Renesas's SH-Mobile and R-Mobile ARM platforms using
665 a non-multiplatform kernel.
664 666
665config ARCH_RPC 667config ARCH_RPC
666 bool "RiscPC" 668 bool "RiscPC"
@@ -1614,7 +1616,7 @@ config HZ_FIXED
1614 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \ 1616 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1615 ARCH_S5PV210 || ARCH_EXYNOS4 1617 ARCH_S5PV210 || ARCH_EXYNOS4
1616 default AT91_TIMER_HZ if ARCH_AT91 1618 default AT91_TIMER_HZ if ARCH_AT91
1617 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE 1619 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1618 default 0 1620 default 0
1619 1621
1620choice 1622choice
@@ -1799,8 +1801,8 @@ config ARCH_WANT_GENERAL_HUGETLB
1799source "mm/Kconfig" 1801source "mm/Kconfig"
1800 1802
1801config FORCE_MAX_ZONEORDER 1803config FORCE_MAX_ZONEORDER
1802 int "Maximum zone order" if ARCH_SHMOBILE 1804 int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1803 range 11 64 if ARCH_SHMOBILE 1805 range 11 64 if ARCH_SHMOBILE_LEGACY
1804 default "12" if SOC_AM33XX 1806 default "12" if SOC_AM33XX
1805 default "9" if SA1111 1807 default "9" if SA1111
1806 default "11" 1808 default "11"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 2cb05d4e4230..aa791d17179b 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -190,7 +190,6 @@ machine-$(CONFIG_ARCH_S5PC100) += s5pc100
190machine-$(CONFIG_ARCH_S5PV210) += s5pv210 190machine-$(CONFIG_ARCH_S5PV210) += s5pv210
191machine-$(CONFIG_ARCH_SA1100) += sa1100 191machine-$(CONFIG_ARCH_SA1100) += sa1100
192machine-$(CONFIG_ARCH_SHMOBILE) += shmobile 192machine-$(CONFIG_ARCH_SHMOBILE) += shmobile
193machine-$(CONFIG_ARCH_SHMOBILE_MULTI) += shmobile
194machine-$(CONFIG_ARCH_SIRF) += prima2 193machine-$(CONFIG_ARCH_SIRF) += prima2
195machine-$(CONFIG_ARCH_SOCFPGA) += socfpga 194machine-$(CONFIG_ARCH_SOCFPGA) += socfpga
196machine-$(CONFIG_ARCH_STI) += sti 195machine-$(CONFIG_ARCH_STI) += sti
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index e7190bb5998e..f54d5a25c7ee 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -64,7 +64,7 @@ else
64endif 64endif
65endif 65endif
66 66
67ifeq ($(CONFIG_ARCH_SHMOBILE),y) 67ifeq ($(CONFIG_ARCH_SHMOBILE_LEGACY),y)
68OBJS += head-shmobile.o 68OBJS += head-shmobile.o
69endif 69endif
70 70
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 772a30e06e48..402481775bbe 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -217,7 +217,7 @@ dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \
217dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb 217dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb
218dtb-$(CONFIG_ARCH_S3C64XX) += s3c6410-mini6410.dtb \ 218dtb-$(CONFIG_ARCH_S3C64XX) += s3c6410-mini6410.dtb \
219 s3c6410-smdk6410.dtb 219 s3c6410-smdk6410.dtb
220dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \ 220dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += emev2-kzm9d.dtb \
221 r7s72100-genmai.dtb \ 221 r7s72100-genmai.dtb \
222 r8a7740-armadillo800eva.dtb \ 222 r8a7740-armadillo800eva.dtb \
223 r8a7778-bockw.dtb \ 223 r8a7778-bockw.dtb \
diff --git a/arch/arm/configs/ape6evm_defconfig b/arch/arm/configs/ape6evm_defconfig
index 1ce39940795d..cb26c62dc722 100644
--- a/arch/arm/configs/ape6evm_defconfig
+++ b/arch/arm/configs/ape6evm_defconfig
@@ -13,7 +13,7 @@ CONFIG_EMBEDDED=y
13CONFIG_PERF_EVENTS=y 13CONFIG_PERF_EVENTS=y
14CONFIG_SLAB=y 14CONFIG_SLAB=y
15# CONFIG_BLOCK is not set 15# CONFIG_BLOCK is not set
16CONFIG_ARCH_SHMOBILE=y 16CONFIG_ARCH_SHMOBILE_LEGACY=y
17CONFIG_ARCH_R8A73A4=y 17CONFIG_ARCH_R8A73A4=y
18CONFIG_MACH_APE6EVM=y 18CONFIG_MACH_APE6EVM=y
19# CONFIG_ARM_THUMB is not set 19# CONFIG_ARM_THUMB is not set
diff --git a/arch/arm/configs/armadillo800eva_defconfig b/arch/arm/configs/armadillo800eva_defconfig
index fae939d3d7f0..5abf1a2e3160 100644
--- a/arch/arm/configs/armadillo800eva_defconfig
+++ b/arch/arm/configs/armadillo800eva_defconfig
@@ -15,7 +15,7 @@ CONFIG_MODULE_FORCE_UNLOAD=y
15# CONFIG_BLK_DEV_BSG is not set 15# CONFIG_BLK_DEV_BSG is not set
16# CONFIG_IOSCHED_DEADLINE is not set 16# CONFIG_IOSCHED_DEADLINE is not set
17# CONFIG_IOSCHED_CFQ is not set 17# CONFIG_IOSCHED_CFQ is not set
18CONFIG_ARCH_SHMOBILE=y 18CONFIG_ARCH_SHMOBILE_LEGACY=y
19CONFIG_ARCH_R8A7740=y 19CONFIG_ARCH_R8A7740=y
20CONFIG_MACH_ARMADILLO800EVA=y 20CONFIG_MACH_ARMADILLO800EVA=y
21# CONFIG_SH_TIMER_TMU is not set 21# CONFIG_SH_TIMER_TMU is not set
diff --git a/arch/arm/configs/bockw_defconfig b/arch/arm/configs/bockw_defconfig
index b38cd107f82d..1dd39716d7cb 100644
--- a/arch/arm/configs/bockw_defconfig
+++ b/arch/arm/configs/bockw_defconfig
@@ -8,7 +8,7 @@ CONFIG_SYSCTL_SYSCALL=y
8CONFIG_EMBEDDED=y 8CONFIG_EMBEDDED=y
9CONFIG_SLAB=y 9CONFIG_SLAB=y
10# CONFIG_IOSCHED_CFQ is not set 10# CONFIG_IOSCHED_CFQ is not set
11CONFIG_ARCH_SHMOBILE=y 11CONFIG_ARCH_SHMOBILE_LEGACY=y
12CONFIG_ARCH_R8A7778=y 12CONFIG_ARCH_R8A7778=y
13CONFIG_MACH_BOCKW=y 13CONFIG_MACH_BOCKW=y
14CONFIG_MEMORY_START=0x60000000 14CONFIG_MEMORY_START=0x60000000
diff --git a/arch/arm/configs/koelsch_defconfig b/arch/arm/configs/koelsch_defconfig
index 825c16dee8a0..7fd65a01ec7e 100644
--- a/arch/arm/configs/koelsch_defconfig
+++ b/arch/arm/configs/koelsch_defconfig
@@ -9,7 +9,7 @@ CONFIG_EMBEDDED=y
9CONFIG_PERF_EVENTS=y 9CONFIG_PERF_EVENTS=y
10CONFIG_SLAB=y 10CONFIG_SLAB=y
11# CONFIG_BLOCK is not set 11# CONFIG_BLOCK is not set
12CONFIG_ARCH_SHMOBILE=y 12CONFIG_ARCH_SHMOBILE_LEGACY=y
13CONFIG_ARCH_R8A7791=y 13CONFIG_ARCH_R8A7791=y
14CONFIG_MACH_KOELSCH=y 14CONFIG_MACH_KOELSCH=y
15# CONFIG_SWP_EMULATE is not set 15# CONFIG_SWP_EMULATE is not set
diff --git a/arch/arm/configs/kzm9d_defconfig b/arch/arm/configs/kzm9d_defconfig
index 6c37f4a98eb8..217f1dda2965 100644
--- a/arch/arm/configs/kzm9d_defconfig
+++ b/arch/arm/configs/kzm9d_defconfig
@@ -13,7 +13,7 @@ CONFIG_SLAB=y
13# CONFIG_BLK_DEV_BSG is not set 13# CONFIG_BLK_DEV_BSG is not set
14# CONFIG_IOSCHED_DEADLINE is not set 14# CONFIG_IOSCHED_DEADLINE is not set
15# CONFIG_IOSCHED_CFQ is not set 15# CONFIG_IOSCHED_CFQ is not set
16CONFIG_ARCH_SHMOBILE=y 16CONFIG_ARCH_SHMOBILE_LEGACY=y
17CONFIG_ARCH_EMEV2=y 17CONFIG_ARCH_EMEV2=y
18CONFIG_MACH_KZM9D=y 18CONFIG_MACH_KZM9D=y
19CONFIG_MEMORY_START=0x40000000 19CONFIG_MEMORY_START=0x40000000
diff --git a/arch/arm/configs/kzm9g_defconfig b/arch/arm/configs/kzm9g_defconfig
index 1ad028023a64..9934dbc23d64 100644
--- a/arch/arm/configs/kzm9g_defconfig
+++ b/arch/arm/configs/kzm9g_defconfig
@@ -22,7 +22,7 @@ CONFIG_MODULE_UNLOAD=y
22# CONFIG_BLK_DEV_BSG is not set 22# CONFIG_BLK_DEV_BSG is not set
23# CONFIG_IOSCHED_DEADLINE is not set 23# CONFIG_IOSCHED_DEADLINE is not set
24# CONFIG_IOSCHED_CFQ is not set 24# CONFIG_IOSCHED_CFQ is not set
25CONFIG_ARCH_SHMOBILE=y 25CONFIG_ARCH_SHMOBILE_LEGACY=y
26CONFIG_ARCH_SH73A0=y 26CONFIG_ARCH_SH73A0=y
27CONFIG_MACH_KZM9G=y 27CONFIG_MACH_KZM9G=y
28CONFIG_MEMORY_START=0x41000000 28CONFIG_MEMORY_START=0x41000000
diff --git a/arch/arm/configs/lager_defconfig b/arch/arm/configs/lager_defconfig
index 35bff5e0d57a..35dc8b2be47f 100644
--- a/arch/arm/configs/lager_defconfig
+++ b/arch/arm/configs/lager_defconfig
@@ -12,7 +12,7 @@ CONFIG_SLAB=y
12# CONFIG_BLK_DEV_BSG is not set 12# CONFIG_BLK_DEV_BSG is not set
13# CONFIG_IOSCHED_DEADLINE is not set 13# CONFIG_IOSCHED_DEADLINE is not set
14# CONFIG_IOSCHED_CFQ is not set 14# CONFIG_IOSCHED_CFQ is not set
15CONFIG_ARCH_SHMOBILE=y 15CONFIG_ARCH_SHMOBILE_LEGACY=y
16CONFIG_ARCH_R8A7790=y 16CONFIG_ARCH_R8A7790=y
17CONFIG_MACH_LAGER=y 17CONFIG_MACH_LAGER=y
18# CONFIG_SH_TIMER_TMU is not set 18# CONFIG_SH_TIMER_TMU is not set
diff --git a/arch/arm/configs/mackerel_defconfig b/arch/arm/configs/mackerel_defconfig
index 9fb11895b2e2..a61e1653fc5e 100644
--- a/arch/arm/configs/mackerel_defconfig
+++ b/arch/arm/configs/mackerel_defconfig
@@ -14,7 +14,7 @@ CONFIG_MODULE_UNLOAD=y
14# CONFIG_BLK_DEV_BSG is not set 14# CONFIG_BLK_DEV_BSG is not set
15# CONFIG_IOSCHED_DEADLINE is not set 15# CONFIG_IOSCHED_DEADLINE is not set
16# CONFIG_IOSCHED_CFQ is not set 16# CONFIG_IOSCHED_CFQ is not set
17CONFIG_ARCH_SHMOBILE=y 17CONFIG_ARCH_SHMOBILE_LEGACY=y
18CONFIG_ARCH_SH7372=y 18CONFIG_ARCH_SH7372=y
19CONFIG_MACH_MACKEREL=y 19CONFIG_MACH_MACKEREL=y
20CONFIG_MEMORY_SIZE=0x10000000 20CONFIG_MEMORY_SIZE=0x10000000
diff --git a/arch/arm/configs/marzen_defconfig b/arch/arm/configs/marzen_defconfig
index 5cc6360340b1..6981338cd08d 100644
--- a/arch/arm/configs/marzen_defconfig
+++ b/arch/arm/configs/marzen_defconfig
@@ -9,7 +9,7 @@ CONFIG_SYSCTL_SYSCALL=y
9CONFIG_EMBEDDED=y 9CONFIG_EMBEDDED=y
10CONFIG_SLAB=y 10CONFIG_SLAB=y
11# CONFIG_IOSCHED_CFQ is not set 11# CONFIG_IOSCHED_CFQ is not set
12CONFIG_ARCH_SHMOBILE=y 12CONFIG_ARCH_SHMOBILE_LEGACY=y
13CONFIG_ARCH_R8A7779=y 13CONFIG_ARCH_R8A7779=y
14CONFIG_MACH_MARZEN=y 14CONFIG_MACH_MARZEN=y
15CONFIG_MEMORY_START=0x60000000 15CONFIG_MEMORY_START=0x60000000
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index a4a4b75109b2..8c8889211f6d 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -1,6 +1,10 @@
1config ARCH_SHMOBILE
2 bool
3
1config ARCH_SHMOBILE_MULTI 4config ARCH_SHMOBILE_MULTI
2 bool "SH-Mobile Series" if ARCH_MULTI_V7 5 bool "SH-Mobile Series" if ARCH_MULTI_V7
3 depends on MMU 6 depends on MMU
7 select ARCH_SHMOBILE
4 select CPU_V7 8 select CPU_V7
5 select GENERIC_CLOCKEVENTS 9 select GENERIC_CLOCKEVENTS
6 select HAVE_ARM_SCU if SMP 10 select HAVE_ARM_SCU if SMP
@@ -8,6 +12,7 @@ config ARCH_SHMOBILE_MULTI
8 select HAVE_SMP 12 select HAVE_SMP
9 select ARM_GIC 13 select ARM_GIC
10 select MIGHT_HAVE_CACHE_L2X0 14 select MIGHT_HAVE_CACHE_L2X0
15 select MIGHT_HAVE_PCI
11 select NO_IOPORT 16 select NO_IOPORT
12 select PINCTRL 17 select PINCTRL
13 select ARCH_REQUIRE_GPIOLIB 18 select ARCH_REQUIRE_GPIOLIB
@@ -30,7 +35,7 @@ config MACH_KZM9D
30comment "SH-Mobile System Configuration" 35comment "SH-Mobile System Configuration"
31endif 36endif
32 37
33if ARCH_SHMOBILE 38if ARCH_SHMOBILE_LEGACY
34 39
35comment "SH-Mobile System Type" 40comment "SH-Mobile System Type"
36 41
@@ -92,23 +97,31 @@ config ARCH_R8A7790
92 select ARCH_WANT_OPTIONAL_GPIOLIB 97 select ARCH_WANT_OPTIONAL_GPIOLIB
93 select ARM_GIC 98 select ARM_GIC
94 select CPU_V7 99 select CPU_V7
100 select MIGHT_HAVE_PCI
95 select SH_CLK_CPG 101 select SH_CLK_CPG
96 select RENESAS_IRQC 102 select RENESAS_IRQC
97 103
98config ARCH_R8A7791 104config ARCH_R8A7791
99 bool "R-Car M2 (R8A77910)" 105 bool "R-Car M2 (R8A77910)"
106 select ARCH_WANT_OPTIONAL_GPIOLIB
100 select ARM_GIC 107 select ARM_GIC
101 select CPU_V7 108 select CPU_V7
109 select MIGHT_HAVE_PCI
102 select SH_CLK_CPG 110 select SH_CLK_CPG
111 select RENESAS_IRQC
103 112
104config ARCH_EMEV2 113config ARCH_EMEV2
105 bool "Emma Mobile EV2" 114 bool "Emma Mobile EV2"
106 select ARCH_WANT_OPTIONAL_GPIOLIB 115 select ARCH_WANT_OPTIONAL_GPIOLIB
107 select ARM_GIC 116 select ARM_GIC
108 select CPU_V7 117 select CPU_V7
118 select MIGHT_HAVE_PCI
119 select USE_OF
120 select AUTO_ZRELADDR
109 121
110config ARCH_R7S72100 122config ARCH_R7S72100
111 bool "RZ/A1H (R7S72100)" 123 bool "RZ/A1H (R7S72100)"
124 select ARCH_WANT_OPTIONAL_GPIOLIB
112 select ARM_GIC 125 select ARM_GIC
113 select CPU_V7 126 select CPU_V7
114 select SH_CLK_CPG 127 select SH_CLK_CPG
@@ -230,12 +243,7 @@ config MACH_KOELSCH
230 bool "Koelsch board" 243 bool "Koelsch board"
231 depends on ARCH_R8A7791 244 depends on ARCH_R8A7791
232 select USE_OF 245 select USE_OF
233 246 select MICREL_PHY if SH_ETH
234config MACH_KZM9D
235 bool "KZM9D board"
236 depends on ARCH_EMEV2
237 select REGULATOR_FIXED_VOLTAGE if REGULATOR
238 select USE_OF
239 247
240config MACH_KZM9G 248config MACH_KZM9G
241 bool "KZM-A9-GT board" 249 bool "KZM-A9-GT board"
@@ -274,7 +282,7 @@ source "drivers/sh/Kconfig"
274 282
275endif 283endif
276 284
277if ARCH_SHMOBILE || ARCH_SHMOBILE_MULTI 285if ARCH_SHMOBILE
278 286
279menu "Timer and clock configuration" 287menu "Timer and clock configuration"
280 288
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index 51db2bcafabf..c7e877499dc2 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -71,7 +71,6 @@ obj-$(CONFIG_MACH_LAGER_REFERENCE) += board-lager-reference.o
71obj-$(CONFIG_MACH_ARMADILLO800EVA) += board-armadillo800eva.o 71obj-$(CONFIG_MACH_ARMADILLO800EVA) += board-armadillo800eva.o
72obj-$(CONFIG_MACH_ARMADILLO800EVA_REFERENCE) += board-armadillo800eva-reference.o 72obj-$(CONFIG_MACH_ARMADILLO800EVA_REFERENCE) += board-armadillo800eva-reference.o
73obj-$(CONFIG_MACH_KOELSCH) += board-koelsch.o 73obj-$(CONFIG_MACH_KOELSCH) += board-koelsch.o
74obj-$(CONFIG_MACH_KZM9D) += board-kzm9d.o
75obj-$(CONFIG_MACH_KZM9G) += board-kzm9g.o 74obj-$(CONFIG_MACH_KZM9G) += board-kzm9g.o
76obj-$(CONFIG_MACH_KZM9G_REFERENCE) += board-kzm9g-reference.o 75obj-$(CONFIG_MACH_KZM9G_REFERENCE) += board-kzm9g-reference.o
77endif 76endif
diff --git a/arch/arm/mach-shmobile/Makefile.boot b/arch/arm/mach-shmobile/Makefile.boot
index 391d72a5536c..4f30e3dc0919 100644
--- a/arch/arm/mach-shmobile/Makefile.boot
+++ b/arch/arm/mach-shmobile/Makefile.boot
@@ -8,7 +8,6 @@ loadaddr-$(CONFIG_MACH_BOCKW) += 0x60008000
8loadaddr-$(CONFIG_MACH_BOCKW_REFERENCE) += 0x60008000 8loadaddr-$(CONFIG_MACH_BOCKW_REFERENCE) += 0x60008000
9loadaddr-$(CONFIG_MACH_GENMAI) += 0x8008000 9loadaddr-$(CONFIG_MACH_GENMAI) += 0x8008000
10loadaddr-$(CONFIG_MACH_KOELSCH) += 0x40008000 10loadaddr-$(CONFIG_MACH_KOELSCH) += 0x40008000
11loadaddr-$(CONFIG_MACH_KZM9D) += 0x40008000
12loadaddr-$(CONFIG_MACH_KZM9G) += 0x41008000 11loadaddr-$(CONFIG_MACH_KZM9G) += 0x41008000
13loadaddr-$(CONFIG_MACH_KZM9G_REFERENCE) += 0x41008000 12loadaddr-$(CONFIG_MACH_KZM9G_REFERENCE) += 0x41008000
14loadaddr-$(CONFIG_MACH_LAGER) += 0x40008000 13loadaddr-$(CONFIG_MACH_LAGER) += 0x40008000
diff --git a/arch/arm/mach-shmobile/board-bockw.c b/arch/arm/mach-shmobile/board-bockw.c
index 38611526fe9a..44b55ef8857e 100644
--- a/arch/arm/mach-shmobile/board-bockw.c
+++ b/arch/arm/mach-shmobile/board-bockw.c
@@ -25,6 +25,7 @@
25#include <linux/mmc/sh_mmcif.h> 25#include <linux/mmc/sh_mmcif.h>
26#include <linux/mtd/partitions.h> 26#include <linux/mtd/partitions.h>
27#include <linux/pinctrl/machine.h> 27#include <linux/pinctrl/machine.h>
28#include <linux/platform_data/camera-rcar.h>
28#include <linux/platform_data/usb-rcar-phy.h> 29#include <linux/platform_data/usb-rcar-phy.h>
29#include <linux/platform_device.h> 30#include <linux/platform_device.h>
30#include <linux/regulator/fixed.h> 31#include <linux/regulator/fixed.h>
diff --git a/arch/arm/mach-shmobile/board-kzm9d.c b/arch/arm/mach-shmobile/board-kzm9d.c
deleted file mode 100644
index 30c2cc695b12..000000000000
--- a/arch/arm/mach-shmobile/board-kzm9d.c
+++ /dev/null
@@ -1,92 +0,0 @@
1/*
2 * kzm9d board support
3 *
4 * Copyright (C) 2012 Renesas Solutions Corp.
5 * Copyright (C) 2012 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/kernel.h>
22#include <linux/interrupt.h>
23#include <linux/platform_device.h>
24#include <linux/regulator/fixed.h>
25#include <linux/regulator/machine.h>
26#include <linux/smsc911x.h>
27#include <mach/common.h>
28#include <mach/emev2.h>
29#include <asm/mach-types.h>
30#include <asm/mach/arch.h>
31
32/* Dummy supplies, where voltage doesn't matter */
33static struct regulator_consumer_supply dummy_supplies[] = {
34 REGULATOR_SUPPLY("vddvario", "smsc911x"),
35 REGULATOR_SUPPLY("vdd33a", "smsc911x"),
36};
37
38/* Ether */
39static struct resource smsc911x_resources[] = {
40 [0] = {
41 .start = 0x20000000,
42 .end = 0x2000ffff,
43 .flags = IORESOURCE_MEM,
44 },
45 [1] = {
46 .start = EMEV2_GPIO_IRQ(1),
47 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH,
48 },
49};
50
51static struct smsc911x_platform_config smsc911x_platdata = {
52 .flags = SMSC911X_USE_32BIT,
53 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
54 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
55};
56
57static struct platform_device smsc91x_device = {
58 .name = "smsc911x",
59 .id = -1,
60 .dev = {
61 .platform_data = &smsc911x_platdata,
62 },
63 .num_resources = ARRAY_SIZE(smsc911x_resources),
64 .resource = smsc911x_resources,
65};
66
67static struct platform_device *kzm9d_devices[] __initdata = {
68 &smsc91x_device,
69};
70
71void __init kzm9d_add_standard_devices(void)
72{
73 regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
74
75 emev2_add_standard_devices();
76
77 platform_add_devices(kzm9d_devices, ARRAY_SIZE(kzm9d_devices));
78}
79
80static const char *kzm9d_boards_compat_dt[] __initdata = {
81 "renesas,kzm9d",
82 NULL,
83};
84
85DT_MACHINE_START(KZM9D_DT, "kzm9d")
86 .smp = smp_ops(emev2_smp_ops),
87 .map_io = emev2_map_io,
88 .init_early = emev2_init_delay,
89 .init_machine = kzm9d_add_standard_devices,
90 .init_late = shmobile_init_late,
91 .dt_compat = kzm9d_boards_compat_dt,
92MACHINE_END
diff --git a/arch/arm/mach-shmobile/clock-r7s72100.c b/arch/arm/mach-shmobile/clock-r7s72100.c
index 4aba20ca127e..850a8a371b43 100644
--- a/arch/arm/mach-shmobile/clock-r7s72100.c
+++ b/arch/arm/mach-shmobile/clock-r7s72100.c
@@ -27,6 +27,7 @@
27#define FRQCR2 0xfcfe0014 27#define FRQCR2 0xfcfe0014
28#define STBCR3 0xfcfe0420 28#define STBCR3 0xfcfe0420
29#define STBCR4 0xfcfe0424 29#define STBCR4 0xfcfe0424
30#define STBCR9 0xfcfe0438
30 31
31#define PLL_RATE 30 32#define PLL_RATE 30
32 33
@@ -144,10 +145,15 @@ struct clk div4_clks[DIV4_NR] = {
144 | CLK_ENABLE_ON_INIT), 145 | CLK_ENABLE_ON_INIT),
145}; 146};
146 147
147enum { MSTP47, MSTP46, MSTP45, MSTP44, MSTP43, MSTP42, MSTP41, MSTP40, 148enum { MSTP97, MSTP96, MSTP95, MSTP94,
149 MSTP47, MSTP46, MSTP45, MSTP44, MSTP43, MSTP42, MSTP41, MSTP40,
148 MSTP33, MSTP_NR }; 150 MSTP33, MSTP_NR };
149 151
150static struct clk mstp_clks[MSTP_NR] = { 152static struct clk mstp_clks[MSTP_NR] = {
153 [MSTP97] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 7, 0), /* RIIC0 */
154 [MSTP96] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 6, 0), /* RIIC1 */
155 [MSTP95] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 5, 0), /* RIIC2 */
156 [MSTP94] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 4, 0), /* RIIC3 */
151 [MSTP47] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 7, 0), /* SCIF0 */ 157 [MSTP47] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 7, 0), /* SCIF0 */
152 [MSTP46] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 6, 0), /* SCIF1 */ 158 [MSTP46] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 6, 0), /* SCIF1 */
153 [MSTP45] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 5, 0), /* SCIF2 */ 159 [MSTP45] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 5, 0), /* SCIF2 */
diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
index c826bca4024e..e9a3c6401845 100644
--- a/arch/arm/mach-shmobile/clock-r8a7740.c
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -585,6 +585,7 @@ static struct clk_lookup lookups[] = {
585 585
586 CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), 586 CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]),
587 CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), 587 CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]),
588 CLKDEV_DEV_ID("fe1f0000.sound", &mstp_clks[MSTP328]),
588 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), 589 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]),
589 CLKDEV_DEV_ID("e6c20000.i2c", &mstp_clks[MSTP323]), 590 CLKDEV_DEV_ID("e6c20000.i2c", &mstp_clks[MSTP323]),
590 CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP320]), 591 CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP320]),
diff --git a/arch/arm/mach-shmobile/clock-r8a7778.c b/arch/arm/mach-shmobile/clock-r8a7778.c
index fb6af83858e3..dfb0fff4d24c 100644
--- a/arch/arm/mach-shmobile/clock-r8a7778.c
+++ b/arch/arm/mach-shmobile/clock-r8a7778.c
@@ -115,6 +115,8 @@ static struct clk *main_clks[] = {
115}; 115};
116 116
117enum { 117enum {
118 MSTP531, MSTP530,
119 MSTP529, MSTP528, MSTP527, MSTP526, MSTP525, MSTP524, MSTP523,
118 MSTP331, 120 MSTP331,
119 MSTP323, MSTP322, MSTP321, 121 MSTP323, MSTP322, MSTP321,
120 MSTP311, MSTP310, 122 MSTP311, MSTP310,
@@ -129,6 +131,15 @@ enum {
129 MSTP_NR }; 131 MSTP_NR };
130 132
131static struct clk mstp_clks[MSTP_NR] = { 133static struct clk mstp_clks[MSTP_NR] = {
134 [MSTP531] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 31, 0), /* SCU0 */
135 [MSTP530] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 30, 0), /* SCU1 */
136 [MSTP529] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 29, 0), /* SCU2 */
137 [MSTP528] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 28, 0), /* SCU3 */
138 [MSTP527] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 27, 0), /* SCU4 */
139 [MSTP526] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 26, 0), /* SCU5 */
140 [MSTP525] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 25, 0), /* SCU6 */
141 [MSTP524] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 24, 0), /* SCU7 */
142 [MSTP523] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 23, 0), /* SCU8 */
132 [MSTP331] = SH_CLK_MSTP32(&s4_clk, MSTPCR3, 31, 0), /* MMC */ 143 [MSTP331] = SH_CLK_MSTP32(&s4_clk, MSTPCR3, 31, 0), /* MMC */
133 [MSTP323] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 23, 0), /* SDHI0 */ 144 [MSTP323] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 23, 0), /* SDHI0 */
134 [MSTP322] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 22, 0), /* SDHI1 */ 145 [MSTP322] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 22, 0), /* SDHI1 */
@@ -173,9 +184,13 @@ static struct clk_lookup lookups[] = {
173 184
174 /* MSTP32 clocks */ 185 /* MSTP32 clocks */
175 CLKDEV_DEV_ID("sh_mmcif", &mstp_clks[MSTP331]), /* MMC */ 186 CLKDEV_DEV_ID("sh_mmcif", &mstp_clks[MSTP331]), /* MMC */
187 CLKDEV_DEV_ID("ffe4e000.mmcif", &mstp_clks[MSTP331]), /* MMC */
176 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */ 188 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */
189 CLKDEV_DEV_ID("ffe4c000.sdhi", &mstp_clks[MSTP323]), /* SDHI0 */
177 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */ 190 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */
191 CLKDEV_DEV_ID("ffe4d000.sdhi", &mstp_clks[MSTP322]), /* SDHI1 */
178 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */ 192 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */
193 CLKDEV_DEV_ID("ffe4f000.sdhi", &mstp_clks[MSTP321]), /* SDHI2 */
179 CLKDEV_DEV_ID("r8a777x-ether", &mstp_clks[MSTP114]), /* Ether */ 194 CLKDEV_DEV_ID("r8a777x-ether", &mstp_clks[MSTP114]), /* Ether */
180 CLKDEV_DEV_ID("r8a7778-vin.0", &mstp_clks[MSTP110]), /* VIN0 */ 195 CLKDEV_DEV_ID("r8a7778-vin.0", &mstp_clks[MSTP110]), /* VIN0 */
181 CLKDEV_DEV_ID("r8a7778-vin.1", &mstp_clks[MSTP109]), /* VIN1 */ 196 CLKDEV_DEV_ID("r8a7778-vin.1", &mstp_clks[MSTP109]), /* VIN1 */
@@ -183,9 +198,13 @@ static struct clk_lookup lookups[] = {
183 CLKDEV_DEV_ID("ohci-platform", &mstp_clks[MSTP100]), /* USB OHCI port0/1 */ 198 CLKDEV_DEV_ID("ohci-platform", &mstp_clks[MSTP100]), /* USB OHCI port0/1 */
184 CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP100]), /* USB FUNC */ 199 CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP100]), /* USB FUNC */
185 CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP030]), /* I2C0 */ 200 CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP030]), /* I2C0 */
201 CLKDEV_DEV_ID("ffc70000.i2c", &mstp_clks[MSTP030]), /* I2C0 */
186 CLKDEV_DEV_ID("i2c-rcar.1", &mstp_clks[MSTP029]), /* I2C1 */ 202 CLKDEV_DEV_ID("i2c-rcar.1", &mstp_clks[MSTP029]), /* I2C1 */
203 CLKDEV_DEV_ID("ffc71000.i2c", &mstp_clks[MSTP029]), /* I2C1 */
187 CLKDEV_DEV_ID("i2c-rcar.2", &mstp_clks[MSTP028]), /* I2C2 */ 204 CLKDEV_DEV_ID("i2c-rcar.2", &mstp_clks[MSTP028]), /* I2C2 */
205 CLKDEV_DEV_ID("ffc72000.i2c", &mstp_clks[MSTP028]), /* I2C2 */
188 CLKDEV_DEV_ID("i2c-rcar.3", &mstp_clks[MSTP027]), /* I2C3 */ 206 CLKDEV_DEV_ID("i2c-rcar.3", &mstp_clks[MSTP027]), /* I2C3 */
207 CLKDEV_DEV_ID("ffc73000.i2c", &mstp_clks[MSTP027]), /* I2C3 */
189 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */ 208 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */
190 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */ 209 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */
191 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */ 210 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */
@@ -195,8 +214,11 @@ static struct clk_lookup lookups[] = {
195 CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP016]), /* TMU00 */ 214 CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP016]), /* TMU00 */
196 CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP015]), /* TMU01 */ 215 CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP015]), /* TMU01 */
197 CLKDEV_DEV_ID("sh-hspi.0", &mstp_clks[MSTP007]), /* HSPI0 */ 216 CLKDEV_DEV_ID("sh-hspi.0", &mstp_clks[MSTP007]), /* HSPI0 */
217 CLKDEV_DEV_ID("fffc7000.spi", &mstp_clks[MSTP007]), /* HSPI0 */
198 CLKDEV_DEV_ID("sh-hspi.1", &mstp_clks[MSTP007]), /* HSPI1 */ 218 CLKDEV_DEV_ID("sh-hspi.1", &mstp_clks[MSTP007]), /* HSPI1 */
219 CLKDEV_DEV_ID("fffc8000.spi", &mstp_clks[MSTP007]), /* HSPI1 */
199 CLKDEV_DEV_ID("sh-hspi.2", &mstp_clks[MSTP007]), /* HSPI2 */ 220 CLKDEV_DEV_ID("sh-hspi.2", &mstp_clks[MSTP007]), /* HSPI2 */
221 CLKDEV_DEV_ID("fffc6000.spi", &mstp_clks[MSTP007]), /* HSPI2 */
200 CLKDEV_DEV_ID("rcar_sound", &mstp_clks[MSTP008]), /* SRU */ 222 CLKDEV_DEV_ID("rcar_sound", &mstp_clks[MSTP008]), /* SRU */
201 223
202 CLKDEV_ICK_ID("ssi.0", "rcar_sound", &mstp_clks[MSTP012]), 224 CLKDEV_ICK_ID("ssi.0", "rcar_sound", &mstp_clks[MSTP012]),
@@ -208,6 +230,15 @@ static struct clk_lookup lookups[] = {
208 CLKDEV_ICK_ID("ssi.6", "rcar_sound", &mstp_clks[MSTP309]), 230 CLKDEV_ICK_ID("ssi.6", "rcar_sound", &mstp_clks[MSTP309]),
209 CLKDEV_ICK_ID("ssi.7", "rcar_sound", &mstp_clks[MSTP308]), 231 CLKDEV_ICK_ID("ssi.7", "rcar_sound", &mstp_clks[MSTP308]),
210 CLKDEV_ICK_ID("ssi.8", "rcar_sound", &mstp_clks[MSTP307]), 232 CLKDEV_ICK_ID("ssi.8", "rcar_sound", &mstp_clks[MSTP307]),
233 CLKDEV_ICK_ID("scu.0", "rcar_sound", &mstp_clks[MSTP531]),
234 CLKDEV_ICK_ID("scu.1", "rcar_sound", &mstp_clks[MSTP530]),
235 CLKDEV_ICK_ID("scu.2", "rcar_sound", &mstp_clks[MSTP529]),
236 CLKDEV_ICK_ID("scu.3", "rcar_sound", &mstp_clks[MSTP528]),
237 CLKDEV_ICK_ID("scu.4", "rcar_sound", &mstp_clks[MSTP527]),
238 CLKDEV_ICK_ID("scu.5", "rcar_sound", &mstp_clks[MSTP526]),
239 CLKDEV_ICK_ID("scu.6", "rcar_sound", &mstp_clks[MSTP525]),
240 CLKDEV_ICK_ID("scu.7", "rcar_sound", &mstp_clks[MSTP524]),
241 CLKDEV_ICK_ID("scu.8", "rcar_sound", &mstp_clks[MSTP523]),
211}; 242};
212 243
213void __init r8a7778_clock_init(void) 244void __init r8a7778_clock_init(void)
diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
index 1f7080fab0a5..b545c8dbb818 100644
--- a/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -184,9 +184,13 @@ static struct clk_lookup lookups[] = {
184 CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP016]), /* TMU01 */ 184 CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP016]), /* TMU01 */
185 CLKDEV_DEV_ID("sh_tmu.2", &mstp_clks[MSTP016]), /* TMU02 */ 185 CLKDEV_DEV_ID("sh_tmu.2", &mstp_clks[MSTP016]), /* TMU02 */
186 CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP030]), /* I2C0 */ 186 CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP030]), /* I2C0 */
187 CLKDEV_DEV_ID("ffc70000.i2c", &mstp_clks[MSTP030]), /* I2C0 */
187 CLKDEV_DEV_ID("i2c-rcar.1", &mstp_clks[MSTP029]), /* I2C1 */ 188 CLKDEV_DEV_ID("i2c-rcar.1", &mstp_clks[MSTP029]), /* I2C1 */
189 CLKDEV_DEV_ID("ffc71000.i2c", &mstp_clks[MSTP029]), /* I2C1 */
188 CLKDEV_DEV_ID("i2c-rcar.2", &mstp_clks[MSTP028]), /* I2C2 */ 190 CLKDEV_DEV_ID("i2c-rcar.2", &mstp_clks[MSTP028]), /* I2C2 */
191 CLKDEV_DEV_ID("ffc72000.i2c", &mstp_clks[MSTP028]), /* I2C2 */
189 CLKDEV_DEV_ID("i2c-rcar.3", &mstp_clks[MSTP027]), /* I2C3 */ 192 CLKDEV_DEV_ID("i2c-rcar.3", &mstp_clks[MSTP027]), /* I2C3 */
193 CLKDEV_DEV_ID("ffc73000.i2c", &mstp_clks[MSTP027]), /* I2C3 */
190 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */ 194 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */
191 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */ 195 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */
192 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */ 196 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */
@@ -194,12 +198,19 @@ static struct clk_lookup lookups[] = {
194 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */ 198 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */
195 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */ 199 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */
196 CLKDEV_DEV_ID("sh-hspi.0", &mstp_clks[MSTP007]), /* HSPI0 */ 200 CLKDEV_DEV_ID("sh-hspi.0", &mstp_clks[MSTP007]), /* HSPI0 */
201 CLKDEV_DEV_ID("fffc7000.spi", &mstp_clks[MSTP007]), /* HSPI0 */
197 CLKDEV_DEV_ID("sh-hspi.1", &mstp_clks[MSTP007]), /* HSPI1 */ 202 CLKDEV_DEV_ID("sh-hspi.1", &mstp_clks[MSTP007]), /* HSPI1 */
203 CLKDEV_DEV_ID("fffc8000.spi", &mstp_clks[MSTP007]), /* HSPI1 */
198 CLKDEV_DEV_ID("sh-hspi.2", &mstp_clks[MSTP007]), /* HSPI2 */ 204 CLKDEV_DEV_ID("sh-hspi.2", &mstp_clks[MSTP007]), /* HSPI2 */
205 CLKDEV_DEV_ID("fffc6000.spi", &mstp_clks[MSTP007]), /* HSPI2 */
199 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */ 206 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */
207 CLKDEV_DEV_ID("ffe4c000.sdhi", &mstp_clks[MSTP323]), /* SDHI0 */
200 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */ 208 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */
209 CLKDEV_DEV_ID("ffe4d000.sdhi", &mstp_clks[MSTP322]), /* SDHI1 */
201 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */ 210 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */
211 CLKDEV_DEV_ID("ffe4e000.sdhi", &mstp_clks[MSTP321]), /* SDHI2 */
202 CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP320]), /* SDHI3 */ 212 CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP320]), /* SDHI3 */
213 CLKDEV_DEV_ID("ffe4f000.sdhi", &mstp_clks[MSTP320]), /* SDHI3 */
203 CLKDEV_DEV_ID("rcar-du-r8a7779", &mstp_clks[MSTP103]), /* DU */ 214 CLKDEV_DEV_ID("rcar-du-r8a7779", &mstp_clks[MSTP103]), /* DU */
204}; 215};
205 216
diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
index a64f965c7da1..b6ecea3ec7d5 100644
--- a/arch/arm/mach-shmobile/clock-r8a7790.c
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -53,6 +53,7 @@
53#define SMSTPCR7 0xe615014c 53#define SMSTPCR7 0xe615014c
54#define SMSTPCR8 0xe6150990 54#define SMSTPCR8 0xe6150990
55#define SMSTPCR9 0xe6150994 55#define SMSTPCR9 0xe6150994
56#define SMSTPCR10 0xe6150998
56 57
57#define SDCKCR 0xE6150074 58#define SDCKCR 0xE6150074
58#define SD2CKCR 0xE6150078 59#define SD2CKCR 0xE6150078
@@ -182,10 +183,14 @@ static struct clk div6_clks[DIV6_NR] = {
182 183
183/* MSTP */ 184/* MSTP */
184enum { 185enum {
186 MSTP1015, MSTP1014, MSTP1013, MSTP1012, MSTP1011, MSTP1010,
187 MSTP1009, MSTP1008, MSTP1007, MSTP1006, MSTP1005,
185 MSTP931, MSTP930, MSTP929, MSTP928, 188 MSTP931, MSTP930, MSTP929, MSTP928,
189 MSTP917,
186 MSTP813, 190 MSTP813,
187 MSTP726, MSTP725, MSTP724, MSTP723, MSTP722, MSTP721, MSTP720, 191 MSTP726, MSTP725, MSTP724, MSTP723, MSTP722, MSTP721, MSTP720,
188 MSTP717, MSTP716, 192 MSTP717, MSTP716,
193 MSTP704,
189 MSTP522, 194 MSTP522,
190 MSTP315, MSTP314, MSTP313, MSTP312, MSTP311, MSTP305, MSTP304, 195 MSTP315, MSTP314, MSTP313, MSTP312, MSTP311, MSTP305, MSTP304,
191 MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, 196 MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202,
@@ -194,10 +199,22 @@ enum {
194}; 199};
195 200
196static struct clk mstp_clks[MSTP_NR] = { 201static struct clk mstp_clks[MSTP_NR] = {
197 [MSTP931] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 31, 0), /* I2C0 */ 202 [MSTP1015] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 15, 0), /* SSI0 */
198 [MSTP930] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 30, 0), /* I2C1 */ 203 [MSTP1014] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 14, 0), /* SSI1 */
199 [MSTP929] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 29, 0), /* I2C2 */ 204 [MSTP1013] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 13, 0), /* SSI2 */
200 [MSTP928] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 28, 0), /* I2C3 */ 205 [MSTP1012] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 12, 0), /* SSI3 */
206 [MSTP1011] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 11, 0), /* SSI4 */
207 [MSTP1010] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 10, 0), /* SSI5 */
208 [MSTP1009] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 9, 0), /* SSI6 */
209 [MSTP1008] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 8, 0), /* SSI7 */
210 [MSTP1007] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 7, 0), /* SSI8 */
211 [MSTP1006] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 6, 0), /* SSI9 */
212 [MSTP1005] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 5, 0), /* SSI ALL */
213 [MSTP931] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 31, 0), /* I2C0 */
214 [MSTP930] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 30, 0), /* I2C1 */
215 [MSTP929] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 29, 0), /* I2C2 */
216 [MSTP928] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 28, 0), /* I2C3 */
217 [MSTP917] = SH_CLK_MSTP32(&qspi_clk, SMSTPCR9, 17, 0), /* QSPI */
201 [MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */ 218 [MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */
202 [MSTP726] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 26, 0), /* LVDS0 */ 219 [MSTP726] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 26, 0), /* LVDS0 */
203 [MSTP725] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 25, 0), /* LVDS1 */ 220 [MSTP725] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 25, 0), /* LVDS1 */
@@ -208,6 +225,7 @@ static struct clk mstp_clks[MSTP_NR] = {
208 [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */ 225 [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
209 [MSTP717] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 17, 0), /* HSCIF0 */ 226 [MSTP717] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 17, 0), /* HSCIF0 */
210 [MSTP716] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 16, 0), /* HSCIF1 */ 227 [MSTP716] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 16, 0), /* HSCIF1 */
228 [MSTP704] = SH_CLK_MSTP32(&mp_clk, SMSTPCR7, 4, 0), /* HSUSB */
211 [MSTP522] = SH_CLK_MSTP32(&extal_clk, SMSTPCR5, 22, 0), /* Thermal */ 229 [MSTP522] = SH_CLK_MSTP32(&extal_clk, SMSTPCR5, 22, 0), /* Thermal */
212 [MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0], SMSTPCR3, 15, 0), /* MMC0 */ 230 [MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0], SMSTPCR3, 15, 0), /* MMC0 */
213 [MSTP314] = SH_CLK_MSTP32(&div4_clks[DIV4_SD0], SMSTPCR3, 14, 0), /* SDHI0 */ 231 [MSTP314] = SH_CLK_MSTP32(&div4_clks[DIV4_SD0], SMSTPCR3, 14, 0), /* SDHI0 */
@@ -262,11 +280,7 @@ static struct clk_lookup lookups[] = {
262 CLKDEV_CON_ID("ssprs", &div6_clks[DIV6_SSPRS]), 280 CLKDEV_CON_ID("ssprs", &div6_clks[DIV6_SSPRS]),
263 281
264 /* MSTP */ 282 /* MSTP */
265 CLKDEV_ICK_ID("lvds.0", "rcar-du-r8a7790", &mstp_clks[MSTP726]), 283 CLKDEV_DEV_ID("rcar_sound", &mstp_clks[MSTP1005]),
266 CLKDEV_ICK_ID("lvds.1", "rcar-du-r8a7790", &mstp_clks[MSTP725]),
267 CLKDEV_ICK_ID("du.0", "rcar-du-r8a7790", &mstp_clks[MSTP724]),
268 CLKDEV_ICK_ID("du.1", "rcar-du-r8a7790", &mstp_clks[MSTP723]),
269 CLKDEV_ICK_ID("du.2", "rcar-du-r8a7790", &mstp_clks[MSTP722]),
270 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), 284 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
271 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), 285 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
272 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]), 286 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
@@ -278,10 +292,15 @@ static struct clk_lookup lookups[] = {
278 CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP717]), 292 CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP717]),
279 CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP716]), 293 CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP716]),
280 CLKDEV_DEV_ID("e6508000.i2c", &mstp_clks[MSTP931]), 294 CLKDEV_DEV_ID("e6508000.i2c", &mstp_clks[MSTP931]),
295 CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP931]),
281 CLKDEV_DEV_ID("e6518000.i2c", &mstp_clks[MSTP930]), 296 CLKDEV_DEV_ID("e6518000.i2c", &mstp_clks[MSTP930]),
297 CLKDEV_DEV_ID("i2c-rcar.1", &mstp_clks[MSTP930]),
282 CLKDEV_DEV_ID("e6530000.i2c", &mstp_clks[MSTP929]), 298 CLKDEV_DEV_ID("e6530000.i2c", &mstp_clks[MSTP929]),
299 CLKDEV_DEV_ID("i2c-rcar.2", &mstp_clks[MSTP929]),
283 CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP928]), 300 CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP928]),
301 CLKDEV_DEV_ID("i2c-rcar.3", &mstp_clks[MSTP928]),
284 CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]), 302 CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]),
303 CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
285 CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]), 304 CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
286 CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]), 305 CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]),
287 CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]), 306 CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]),
@@ -296,6 +315,27 @@ static struct clk_lookup lookups[] = {
296 CLKDEV_DEV_ID("ee220000.mmcif", &mstp_clks[MSTP305]), 315 CLKDEV_DEV_ID("ee220000.mmcif", &mstp_clks[MSTP305]),
297 CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]), 316 CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
298 CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]), 317 CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]),
318 CLKDEV_DEV_ID("qspi.0", &mstp_clks[MSTP917]),
319 CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP704]),
320
321 /* ICK */
322 CLKDEV_ICK_ID("usbhs", "usb_phy_rcar_gen2", &mstp_clks[MSTP704]),
323 CLKDEV_ICK_ID("lvds.0", "rcar-du-r8a7790", &mstp_clks[MSTP726]),
324 CLKDEV_ICK_ID("lvds.1", "rcar-du-r8a7790", &mstp_clks[MSTP725]),
325 CLKDEV_ICK_ID("du.0", "rcar-du-r8a7790", &mstp_clks[MSTP724]),
326 CLKDEV_ICK_ID("du.1", "rcar-du-r8a7790", &mstp_clks[MSTP723]),
327 CLKDEV_ICK_ID("du.2", "rcar-du-r8a7790", &mstp_clks[MSTP722]),
328 CLKDEV_ICK_ID("ssi.0", "rcar_sound", &mstp_clks[MSTP1015]),
329 CLKDEV_ICK_ID("ssi.1", "rcar_sound", &mstp_clks[MSTP1014]),
330 CLKDEV_ICK_ID("ssi.2", "rcar_sound", &mstp_clks[MSTP1013]),
331 CLKDEV_ICK_ID("ssi.3", "rcar_sound", &mstp_clks[MSTP1012]),
332 CLKDEV_ICK_ID("ssi.4", "rcar_sound", &mstp_clks[MSTP1011]),
333 CLKDEV_ICK_ID("ssi.5", "rcar_sound", &mstp_clks[MSTP1010]),
334 CLKDEV_ICK_ID("ssi.6", "rcar_sound", &mstp_clks[MSTP1009]),
335 CLKDEV_ICK_ID("ssi.7", "rcar_sound", &mstp_clks[MSTP1008]),
336 CLKDEV_ICK_ID("ssi.8", "rcar_sound", &mstp_clks[MSTP1007]),
337 CLKDEV_ICK_ID("ssi.9", "rcar_sound", &mstp_clks[MSTP1006]),
338
299}; 339};
300 340
301#define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31) \ 341#define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31) \
@@ -321,10 +361,10 @@ void __init r8a7790_clock_init(void)
321 R8A7790_CLOCK_ROOT(20, &extal_clk, 130, 156, 80, 66); 361 R8A7790_CLOCK_ROOT(20, &extal_clk, 130, 156, 80, 66);
322 break; 362 break;
323 case MD(14): 363 case MD(14):
324 R8A7790_CLOCK_ROOT(26, &extal_div2_clk, 200, 240, 122, 102); 364 R8A7790_CLOCK_ROOT(26 / 2, &extal_div2_clk, 200, 240, 122, 102);
325 break; 365 break;
326 case MD(13) | MD(14): 366 case MD(13) | MD(14):
327 R8A7790_CLOCK_ROOT(30, &extal_div2_clk, 172, 208, 106, 88); 367 R8A7790_CLOCK_ROOT(30 / 2, &extal_div2_clk, 172, 208, 106, 88);
328 break; 368 break;
329 } 369 }
330 370
diff --git a/arch/arm/mach-shmobile/clock-r8a7791.c b/arch/arm/mach-shmobile/clock-r8a7791.c
index c9a26f16ce5b..f5461262ee25 100644
--- a/arch/arm/mach-shmobile/clock-r8a7791.c
+++ b/arch/arm/mach-shmobile/clock-r8a7791.c
@@ -103,6 +103,7 @@ SH_FIXED_RATIO_CLK_SET(hp_clk, pll1_clk, 1, 12);
103SH_FIXED_RATIO_CLK_SET(p_clk, pll1_clk, 1, 24); 103SH_FIXED_RATIO_CLK_SET(p_clk, pll1_clk, 1, 24);
104SH_FIXED_RATIO_CLK_SET(rclk_clk, pll1_clk, 1, (48 * 1024)); 104SH_FIXED_RATIO_CLK_SET(rclk_clk, pll1_clk, 1, (48 * 1024));
105SH_FIXED_RATIO_CLK_SET(mp_clk, pll1_div2_clk, 1, 15); 105SH_FIXED_RATIO_CLK_SET(mp_clk, pll1_div2_clk, 1, 15);
106SH_FIXED_RATIO_CLK_SET(zx_clk, pll1_clk, 1, 3);
106 107
107static struct clk *main_clks[] = { 108static struct clk *main_clks[] = {
108 &extal_clk, 109 &extal_clk,
@@ -116,12 +117,15 @@ static struct clk *main_clks[] = {
116 &rclk_clk, 117 &rclk_clk,
117 &mp_clk, 118 &mp_clk,
118 &cp_clk, 119 &cp_clk,
120 &zx_clk,
119}; 121};
120 122
121/* MSTP */ 123/* MSTP */
122enum { 124enum {
123 MSTP721, MSTP720, 125 MSTP813,
126 MSTP726, MSTP724, MSTP723, MSTP721, MSTP720,
124 MSTP719, MSTP718, MSTP715, MSTP714, 127 MSTP719, MSTP718, MSTP715, MSTP714,
128 MSTP522,
125 MSTP216, MSTP207, MSTP206, 129 MSTP216, MSTP207, MSTP206,
126 MSTP204, MSTP203, MSTP202, MSTP1105, MSTP1106, MSTP1107, 130 MSTP204, MSTP203, MSTP202, MSTP1105, MSTP1106, MSTP1107,
127 MSTP124, 131 MSTP124,
@@ -129,12 +133,17 @@ enum {
129}; 133};
130 134
131static struct clk mstp_clks[MSTP_NR] = { 135static struct clk mstp_clks[MSTP_NR] = {
136 [MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */
137 [MSTP726] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 26, 0), /* LVDS0 */
138 [MSTP724] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 24, 0), /* DU0 */
139 [MSTP723] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 23, 0), /* DU1 */
132 [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */ 140 [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */
133 [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */ 141 [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
134 [MSTP719] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 19, 0), /* SCIF2 */ 142 [MSTP719] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 19, 0), /* SCIF2 */
135 [MSTP718] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 18, 0), /* SCIF3 */ 143 [MSTP718] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 18, 0), /* SCIF3 */
136 [MSTP715] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 15, 0), /* SCIF4 */ 144 [MSTP715] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 15, 0), /* SCIF4 */
137 [MSTP714] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 14, 0), /* SCIF5 */ 145 [MSTP714] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 14, 0), /* SCIF5 */
146 [MSTP522] = SH_CLK_MSTP32(&extal_clk, SMSTPCR5, 22, 0), /* Thermal */
138 [MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */ 147 [MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */
139 [MSTP207] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 7, 0), /* SCIFB1 */ 148 [MSTP207] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 7, 0), /* SCIFB1 */
140 [MSTP206] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 6, 0), /* SCIFB0 */ 149 [MSTP206] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 6, 0), /* SCIFB0 */
@@ -164,6 +173,9 @@ static struct clk_lookup lookups[] = {
164 CLKDEV_CON_ID("peripheral_clk", &hp_clk), 173 CLKDEV_CON_ID("peripheral_clk", &hp_clk),
165 174
166 /* MSTP */ 175 /* MSTP */
176 CLKDEV_ICK_ID("lvds.0", "rcar-du-r8a7791", &mstp_clks[MSTP726]),
177 CLKDEV_ICK_ID("du.0", "rcar-du-r8a7791", &mstp_clks[MSTP724]),
178 CLKDEV_ICK_ID("du.1", "rcar-du-r8a7791", &mstp_clks[MSTP723]),
167 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */ 179 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
168 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */ 180 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */
169 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]), /* SCIFB0 */ 181 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]), /* SCIFB0 */
@@ -180,6 +192,9 @@ static struct clk_lookup lookups[] = {
180 CLKDEV_DEV_ID("sh-sci.13", &mstp_clks[MSTP1106]), /* SCIFA4 */ 192 CLKDEV_DEV_ID("sh-sci.13", &mstp_clks[MSTP1106]), /* SCIFA4 */
181 CLKDEV_DEV_ID("sh-sci.14", &mstp_clks[MSTP1107]), /* SCIFA5 */ 193 CLKDEV_DEV_ID("sh-sci.14", &mstp_clks[MSTP1107]), /* SCIFA5 */
182 CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]), 194 CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]),
195 CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
196 CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
197 CLKDEV_DEV_ID("r8a7791-ether", &mstp_clks[MSTP813]), /* Ether */
183}; 198};
184 199
185#define R8A7791_CLOCK_ROOT(e, m, p0, p1, p30, p31) \ 200#define R8A7791_CLOCK_ROOT(e, m, p0, p1, p30, p31) \
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index c92c023f0d27..5e6a0566f3c6 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -658,6 +658,7 @@ static struct clk_lookup lookups[] = {
658 CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP331]), /* SCIFA6 */ 658 CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP331]), /* SCIFA6 */
659 CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */ 659 CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */
660 CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), /* FSI */ 660 CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), /* FSI */
661 CLKDEV_DEV_ID("ec230000.sound", &mstp_clks[MSTP328]), /* FSI */
661 CLKDEV_DEV_ID("sh_irda.0", &mstp_clks[MSTP325]), /* IrDA */ 662 CLKDEV_DEV_ID("sh_irda.0", &mstp_clks[MSTP325]), /* IrDA */
662 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* I2C1 */ 663 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* I2C1 */
663 CLKDEV_DEV_ID("e6822000.i2c", &mstp_clks[MSTP323]), /* I2C1 */ 664 CLKDEV_DEV_ID("e6822000.i2c", &mstp_clks[MSTP323]), /* I2C1 */
diff --git a/arch/arm/mach-shmobile/include/mach/emev2.h b/arch/arm/mach-shmobile/include/mach/emev2.h
index c2eb7568d9be..fcb142a14e07 100644
--- a/arch/arm/mach-shmobile/include/mach/emev2.h
+++ b/arch/arm/mach-shmobile/include/mach/emev2.h
@@ -3,12 +3,7 @@
3 3
4extern void emev2_map_io(void); 4extern void emev2_map_io(void);
5extern void emev2_init_delay(void); 5extern void emev2_init_delay(void);
6extern void emev2_add_standard_devices(void);
7extern void emev2_clock_init(void); 6extern void emev2_clock_init(void);
8
9#define EMEV2_GPIO_BASE 200
10#define EMEV2_GPIO_IRQ(n) (EMEV2_GPIO_BASE + (n))
11
12extern struct smp_operations emev2_smp_ops; 7extern struct smp_operations emev2_smp_ops;
13 8
14#endif /* __ASM_EMEV2_H__ */ 9#endif /* __ASM_EMEV2_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7778.h b/arch/arm/mach-shmobile/include/mach/r8a7778.h
index 441886c9714b..f4076a50e970 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7778.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7778.h
@@ -20,13 +20,50 @@
20#define __ASM_R8A7778_H__ 20#define __ASM_R8A7778_H__
21 21
22#include <linux/sh_eth.h> 22#include <linux/sh_eth.h>
23#include <linux/platform_data/camera-rcar.h>
24 23
25/* HPB-DMA slave IDs */ 24/* HPB-DMA slave IDs */
26enum { 25enum {
27 HPBDMA_SLAVE_DUMMY, 26 HPBDMA_SLAVE_DUMMY,
28 HPBDMA_SLAVE_SDHI0_TX, 27 HPBDMA_SLAVE_SDHI0_TX,
29 HPBDMA_SLAVE_SDHI0_RX, 28 HPBDMA_SLAVE_SDHI0_RX,
29 HPBDMA_SLAVE_SSI0_TX,
30 HPBDMA_SLAVE_SSI0_RX,
31 HPBDMA_SLAVE_SSI1_TX,
32 HPBDMA_SLAVE_SSI1_RX,
33 HPBDMA_SLAVE_SSI2_TX,
34 HPBDMA_SLAVE_SSI2_RX,
35 HPBDMA_SLAVE_SSI3_TX,
36 HPBDMA_SLAVE_SSI3_RX,
37 HPBDMA_SLAVE_SSI4_TX,
38 HPBDMA_SLAVE_SSI4_RX,
39 HPBDMA_SLAVE_SSI5_TX,
40 HPBDMA_SLAVE_SSI5_RX,
41 HPBDMA_SLAVE_SSI6_TX,
42 HPBDMA_SLAVE_SSI6_RX,
43 HPBDMA_SLAVE_SSI7_TX,
44 HPBDMA_SLAVE_SSI7_RX,
45 HPBDMA_SLAVE_SSI8_TX,
46 HPBDMA_SLAVE_SSI8_RX,
47 HPBDMA_SLAVE_HPBIF0_TX,
48 HPBDMA_SLAVE_HPBIF0_RX,
49 HPBDMA_SLAVE_HPBIF1_TX,
50 HPBDMA_SLAVE_HPBIF1_RX,
51 HPBDMA_SLAVE_HPBIF2_TX,
52 HPBDMA_SLAVE_HPBIF2_RX,
53 HPBDMA_SLAVE_HPBIF3_TX,
54 HPBDMA_SLAVE_HPBIF3_RX,
55 HPBDMA_SLAVE_HPBIF4_TX,
56 HPBDMA_SLAVE_HPBIF4_RX,
57 HPBDMA_SLAVE_HPBIF5_TX,
58 HPBDMA_SLAVE_HPBIF5_RX,
59 HPBDMA_SLAVE_HPBIF6_TX,
60 HPBDMA_SLAVE_HPBIF6_RX,
61 HPBDMA_SLAVE_HPBIF7_TX,
62 HPBDMA_SLAVE_HPBIF7_RX,
63 HPBDMA_SLAVE_HPBIF8_TX,
64 HPBDMA_SLAVE_HPBIF8_RX,
65 HPBDMA_SLAVE_USBFUNC_TX,
66 HPBDMA_SLAVE_USBFUNC_RX,
30}; 67};
31 68
32extern void r8a7778_add_standard_devices(void); 69extern void r8a7778_add_standard_devices(void);
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7791.h b/arch/arm/mach-shmobile/include/mach/r8a7791.h
index 051ead3c286e..200fa699f730 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7791.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7791.h
@@ -4,6 +4,7 @@
4void r8a7791_add_standard_devices(void); 4void r8a7791_add_standard_devices(void);
5void r8a7791_add_dt_devices(void); 5void r8a7791_add_dt_devices(void);
6void r8a7791_clock_init(void); 6void r8a7791_clock_init(void);
7void r8a7791_pinmux_init(void);
7void r8a7791_init_early(void); 8void r8a7791_init_early(void);
8extern struct smp_operations r8a7791_smp_ops; 9extern struct smp_operations r8a7791_smp_ops;
9 10
diff --git a/arch/arm/mach-shmobile/setup-emev2.c b/arch/arm/mach-shmobile/setup-emev2.c
index 3ad531caf4f0..c8f2a1a69a52 100644
--- a/arch/arm/mach-shmobile/setup-emev2.c
+++ b/arch/arm/mach-shmobile/setup-emev2.c
@@ -16,24 +16,15 @@
16 * along with this program; if not, write to the Free Software 16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */ 18 */
19#include <linux/clk-provider.h>
19#include <linux/kernel.h> 20#include <linux/kernel.h>
20#include <linux/init.h> 21#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/platform_device.h>
24#include <linux/platform_data/gpio-em.h>
25#include <linux/of_platform.h> 22#include <linux/of_platform.h>
26#include <linux/delay.h>
27#include <linux/input.h>
28#include <linux/io.h>
29#include <linux/irqchip/arm-gic.h>
30#include <mach/common.h> 23#include <mach/common.h>
31#include <mach/emev2.h> 24#include <mach/emev2.h>
32#include <mach/irqs.h>
33#include <asm/mach-types.h> 25#include <asm/mach-types.h>
34#include <asm/mach/arch.h> 26#include <asm/mach/arch.h>
35#include <asm/mach/map.h> 27#include <asm/mach/map.h>
36#include <asm/mach/time.h>
37 28
38static struct map_desc emev2_io_desc[] __initdata = { 29static struct map_desc emev2_io_desc[] __initdata = {
39#ifdef CONFIG_SMP 30#ifdef CONFIG_SMP
@@ -52,150 +43,20 @@ void __init emev2_map_io(void)
52 iotable_init(emev2_io_desc, ARRAY_SIZE(emev2_io_desc)); 43 iotable_init(emev2_io_desc, ARRAY_SIZE(emev2_io_desc));
53} 44}
54 45
55/* UART */
56static struct resource uart0_resources[] = {
57 DEFINE_RES_MEM(0xe1020000, 0x38),
58 DEFINE_RES_IRQ(40),
59};
60
61static struct resource uart1_resources[] = {
62 DEFINE_RES_MEM(0xe1030000, 0x38),
63 DEFINE_RES_IRQ(41),
64};
65
66static struct resource uart2_resources[] = {
67 DEFINE_RES_MEM(0xe1040000, 0x38),
68 DEFINE_RES_IRQ(42),
69};
70
71static struct resource uart3_resources[] = {
72 DEFINE_RES_MEM(0xe1050000, 0x38),
73 DEFINE_RES_IRQ(43),
74};
75
76#define emev2_register_uart(idx) \
77 platform_device_register_simple("serial8250-em", idx, \
78 uart##idx##_resources, \
79 ARRAY_SIZE(uart##idx##_resources))
80
81/* STI */
82static struct resource sti_resources[] = {
83 DEFINE_RES_MEM(0xe0180000, 0x54),
84 DEFINE_RES_IRQ(157),
85};
86
87#define emev2_register_sti() \
88 platform_device_register_simple("em_sti", 0, \
89 sti_resources, \
90 ARRAY_SIZE(sti_resources))
91
92/* GIO */
93static struct gpio_em_config gio0_config = {
94 .gpio_base = 0,
95 .irq_base = EMEV2_GPIO_IRQ(0),
96 .number_of_pins = 32,
97};
98
99static struct resource gio0_resources[] = {
100 DEFINE_RES_MEM(0xe0050000, 0x2c),
101 DEFINE_RES_MEM(0xe0050040, 0x20),
102 DEFINE_RES_IRQ(99),
103 DEFINE_RES_IRQ(100),
104};
105
106static struct gpio_em_config gio1_config = {
107 .gpio_base = 32,
108 .irq_base = EMEV2_GPIO_IRQ(32),
109 .number_of_pins = 32,
110};
111
112static struct resource gio1_resources[] = {
113 DEFINE_RES_MEM(0xe0050080, 0x2c),
114 DEFINE_RES_MEM(0xe00500c0, 0x20),
115 DEFINE_RES_IRQ(101),
116 DEFINE_RES_IRQ(102),
117};
118
119static struct gpio_em_config gio2_config = {
120 .gpio_base = 64,
121 .irq_base = EMEV2_GPIO_IRQ(64),
122 .number_of_pins = 32,
123};
124
125static struct resource gio2_resources[] = {
126 DEFINE_RES_MEM(0xe0050100, 0x2c),
127 DEFINE_RES_MEM(0xe0050140, 0x20),
128 DEFINE_RES_IRQ(103),
129 DEFINE_RES_IRQ(104),
130};
131
132static struct gpio_em_config gio3_config = {
133 .gpio_base = 96,
134 .irq_base = EMEV2_GPIO_IRQ(96),
135 .number_of_pins = 32,
136};
137
138static struct resource gio3_resources[] = {
139 DEFINE_RES_MEM(0xe0050180, 0x2c),
140 DEFINE_RES_MEM(0xe00501c0, 0x20),
141 DEFINE_RES_IRQ(105),
142 DEFINE_RES_IRQ(106),
143};
144
145static struct gpio_em_config gio4_config = {
146 .gpio_base = 128,
147 .irq_base = EMEV2_GPIO_IRQ(128),
148 .number_of_pins = 31,
149};
150
151static struct resource gio4_resources[] = {
152 DEFINE_RES_MEM(0xe0050200, 0x2c),
153 DEFINE_RES_MEM(0xe0050240, 0x20),
154 DEFINE_RES_IRQ(107),
155 DEFINE_RES_IRQ(108),
156};
157
158#define emev2_register_gio(idx) \
159 platform_device_register_resndata(&platform_bus, "em_gio", \
160 idx, gio##idx##_resources, \
161 ARRAY_SIZE(gio##idx##_resources), \
162 &gio##idx##_config, \
163 sizeof(struct gpio_em_config))
164
165static struct resource pmu_resources[] = {
166 DEFINE_RES_IRQ(152),
167 DEFINE_RES_IRQ(153),
168};
169
170#define emev2_register_pmu() \
171 platform_device_register_simple("arm-pmu", -1, \
172 pmu_resources, \
173 ARRAY_SIZE(pmu_resources))
174
175void __init emev2_add_standard_devices(void)
176{
177 if (!IS_ENABLED(CONFIG_COMMON_CLK))
178 emev2_clock_init();
179
180 emev2_register_uart(0);
181 emev2_register_uart(1);
182 emev2_register_uart(2);
183 emev2_register_uart(3);
184 emev2_register_sti();
185 emev2_register_gio(0);
186 emev2_register_gio(1);
187 emev2_register_gio(2);
188 emev2_register_gio(3);
189 emev2_register_gio(4);
190 emev2_register_pmu();
191}
192
193void __init emev2_init_delay(void) 46void __init emev2_init_delay(void)
194{ 47{
195 shmobile_setup_delay(533, 1, 3); /* Cortex-A9 @ 533MHz */ 48 shmobile_setup_delay(533, 1, 3); /* Cortex-A9 @ 533MHz */
196} 49}
197 50
198#ifdef CONFIG_USE_OF 51static void __init emev2_add_standard_devices_dt(void)
52{
53#ifdef CONFIG_COMMON_CLK
54 of_clk_init(NULL);
55#else
56 emev2_clock_init();
57#endif
58 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
59}
199 60
200static const char *emev2_boards_compat_dt[] __initdata = { 61static const char *emev2_boards_compat_dt[] __initdata = {
201 "renesas,emev2", 62 "renesas,emev2",
@@ -206,7 +67,7 @@ DT_MACHINE_START(EMEV2_DT, "Generic Emma Mobile EV2 (Flattened Device Tree)")
206 .smp = smp_ops(emev2_smp_ops), 67 .smp = smp_ops(emev2_smp_ops),
207 .map_io = emev2_map_io, 68 .map_io = emev2_map_io,
208 .init_early = emev2_init_delay, 69 .init_early = emev2_init_delay,
70 .init_machine = emev2_add_standard_devices_dt,
71 .init_late = shmobile_init_late,
209 .dt_compat = emev2_boards_compat_dt, 72 .dt_compat = emev2_boards_compat_dt,
210MACHINE_END 73MACHINE_END
211
212#endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/setup-r7s72100.c b/arch/arm/mach-shmobile/setup-r7s72100.c
index d4eb509a1c87..9c0b3a9d5f7a 100644
--- a/arch/arm/mach-shmobile/setup-r7s72100.c
+++ b/arch/arm/mach-shmobile/setup-r7s72100.c
@@ -22,52 +22,76 @@
22#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <linux/of_platform.h> 23#include <linux/of_platform.h>
24#include <linux/serial_sci.h> 24#include <linux/serial_sci.h>
25#include <linux/sh_timer.h>
25#include <mach/common.h> 26#include <mach/common.h>
26#include <mach/irqs.h> 27#include <mach/irqs.h>
27#include <mach/r7s72100.h> 28#include <mach/r7s72100.h>
28#include <asm/mach/arch.h> 29#include <asm/mach/arch.h>
29 30
30#define SCIF_DATA(index, baseaddr, irq) \ 31#define R7S72100_SCIF(index, baseaddr, irq) \
31[index] = { \ 32static const struct plat_sci_port scif##index##_platform_data = { \
32 .type = PORT_SCIF, \ 33 .type = PORT_SCIF, \
33 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, \ 34 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, \
34 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ 35 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
35 .scbrr_algo_id = SCBRR_ALGO_2, \
36 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | \ 36 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | \
37 SCSCR_REIE, \ 37 SCSCR_REIE, \
38 .mapbase = baseaddr, \ 38}; \
39 .irqs = { irq + 1, irq + 2, irq + 3, irq }, \ 39 \
40} 40static struct resource scif##index##_resources[] = { \
41 DEFINE_RES_MEM(baseaddr, 0x100), \
42 DEFINE_RES_IRQ(irq + 1), \
43 DEFINE_RES_IRQ(irq + 2), \
44 DEFINE_RES_IRQ(irq + 3), \
45 DEFINE_RES_IRQ(irq), \
46} \
47
48R7S72100_SCIF(0, 0xe8007000, gic_iid(221));
49R7S72100_SCIF(1, 0xe8007800, gic_iid(225));
50R7S72100_SCIF(2, 0xe8008000, gic_iid(229));
51R7S72100_SCIF(3, 0xe8008800, gic_iid(233));
52R7S72100_SCIF(4, 0xe8009000, gic_iid(237));
53R7S72100_SCIF(5, 0xe8009800, gic_iid(241));
54R7S72100_SCIF(6, 0xe800a000, gic_iid(245));
55R7S72100_SCIF(7, 0xe800a800, gic_iid(249));
41 56
42enum { SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7 }; 57#define r7s72100_register_scif(index) \
58 platform_device_register_resndata(&platform_bus, "sh-sci", index, \
59 scif##index##_resources, \
60 ARRAY_SIZE(scif##index##_resources), \
61 &scif##index##_platform_data, \
62 sizeof(scif##index##_platform_data))
43 63
44static const struct plat_sci_port scif[] __initconst = { 64
45 SCIF_DATA(SCIF0, 0xe8007000, gic_iid(221)), /* SCIF0 */ 65static struct sh_timer_config mtu2_0_platform_data __initdata = {
46 SCIF_DATA(SCIF1, 0xe8007800, gic_iid(225)), /* SCIF1 */ 66 .name = "MTU2_0",
47 SCIF_DATA(SCIF2, 0xe8008000, gic_iid(229)), /* SCIF2 */ 67 .timer_bit = 0,
48 SCIF_DATA(SCIF3, 0xe8008800, gic_iid(233)), /* SCIF3 */ 68 .channel_offset = -0x80,
49 SCIF_DATA(SCIF4, 0xe8009000, gic_iid(237)), /* SCIF4 */ 69 .clockevent_rating = 200,
50 SCIF_DATA(SCIF5, 0xe8009800, gic_iid(241)), /* SCIF5 */
51 SCIF_DATA(SCIF6, 0xe800a000, gic_iid(245)), /* SCIF6 */
52 SCIF_DATA(SCIF7, 0xe800a800, gic_iid(249)), /* SCIF7 */
53}; 70};
54 71
55static inline void r7s72100_register_scif(int idx) 72static struct resource mtu2_0_resources[] __initdata = {
56{ 73 DEFINE_RES_MEM(0xfcff0300, 0x27),
57 platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx], 74 DEFINE_RES_IRQ(gic_iid(139)), /* MTU2 TGI0A */
58 sizeof(struct plat_sci_port)); 75};
59} 76
77#define r7s72100_register_mtu2(idx) \
78 platform_device_register_resndata(&platform_bus, "sh_mtu2", \
79 idx, mtu2_##idx##_resources, \
80 ARRAY_SIZE(mtu2_##idx##_resources), \
81 &mtu2_##idx##_platform_data, \
82 sizeof(struct sh_timer_config))
60 83
61void __init r7s72100_add_dt_devices(void) 84void __init r7s72100_add_dt_devices(void)
62{ 85{
63 r7s72100_register_scif(SCIF0); 86 r7s72100_register_scif(0);
64 r7s72100_register_scif(SCIF1); 87 r7s72100_register_scif(1);
65 r7s72100_register_scif(SCIF2); 88 r7s72100_register_scif(2);
66 r7s72100_register_scif(SCIF3); 89 r7s72100_register_scif(3);
67 r7s72100_register_scif(SCIF4); 90 r7s72100_register_scif(4);
68 r7s72100_register_scif(SCIF5); 91 r7s72100_register_scif(5);
69 r7s72100_register_scif(SCIF6); 92 r7s72100_register_scif(6);
70 r7s72100_register_scif(SCIF7); 93 r7s72100_register_scif(7);
94 r7s72100_register_mtu2(0);
71} 95}
72 96
73void __init r7s72100_init_early(void) 97void __init r7s72100_init_early(void)
diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c
index b0f2749071be..cd36f8078325 100644
--- a/arch/arm/mach-shmobile/setup-r8a73a4.c
+++ b/arch/arm/mach-shmobile/setup-r8a73a4.c
@@ -40,41 +40,39 @@ void __init r8a73a4_pinmux_init(void)
40 ARRAY_SIZE(pfc_resources)); 40 ARRAY_SIZE(pfc_resources));
41} 41}
42 42
43#define SCIF_COMMON(scif_type, baseaddr, irq) \ 43#define R8A73A4_SCIF(scif_type, _scscr, index, baseaddr, irq) \
44static struct plat_sci_port scif##index##_platform_data = { \
44 .type = scif_type, \ 45 .type = scif_type, \
45 .mapbase = baseaddr, \
46 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ 46 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
47 .scbrr_algo_id = SCBRR_ALGO_4, \ 47 .scscr = _scscr, \
48 .irqs = SCIx_IRQ_MUXED(irq) 48}; \
49 49 \
50#define SCIFA_DATA(index, baseaddr, irq) \ 50static struct resource scif##index##_resources[] = { \
51[index] = { \ 51 DEFINE_RES_MEM(baseaddr, 0x100), \
52 SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \ 52 DEFINE_RES_IRQ(irq), \
53 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \
54} 53}
55 54
56#define SCIFB_DATA(index, baseaddr, irq) \ 55#define R8A73A4_SCIFA(index, baseaddr, irq) \
57[index] = { \ 56 R8A73A4_SCIF(PORT_SCIFA, SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \
58 SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \ 57 index, baseaddr, irq)
59 .scscr = SCSCR_RE | SCSCR_TE, \
60}
61 58
62enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFB3 }; 59#define R8A73A4_SCIFB(index, baseaddr, irq) \
60 R8A73A4_SCIF(PORT_SCIFB, SCSCR_RE | SCSCR_TE, \
61 index, baseaddr, irq)
63 62
64static const struct plat_sci_port scif[] = { 63R8A73A4_SCIFA(0, 0xe6c40000, gic_spi(144)); /* SCIFA0 */
65 SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */ 64R8A73A4_SCIFA(1, 0xe6c50000, gic_spi(145)); /* SCIFA1 */
66 SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */ 65R8A73A4_SCIFB(2, 0xe6c20000, gic_spi(148)); /* SCIFB0 */
67 SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */ 66R8A73A4_SCIFB(3, 0xe6c30000, gic_spi(149)); /* SCIFB1 */
68 SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */ 67R8A73A4_SCIFB(4, 0xe6ce0000, gic_spi(150)); /* SCIFB2 */
69 SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */ 68R8A73A4_SCIFB(5, 0xe6cf0000, gic_spi(151)); /* SCIFB3 */
70 SCIFB_DATA(SCIFB3, 0xe6cf0000, gic_spi(151)), /* SCIFB3 */
71};
72 69
73static inline void r8a73a4_register_scif(int idx) 70#define r8a73a4_register_scif(index) \
74{ 71 platform_device_register_resndata(&platform_bus, "sh-sci", index, \
75 platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx], 72 scif##index##_resources, \
76 sizeof(struct plat_sci_port)); 73 ARRAY_SIZE(scif##index##_resources), \
77} 74 &scif##index##_platform_data, \
75 sizeof(scif##index##_platform_data))
78 76
79static const struct renesas_irqc_config irqc0_data = { 77static const struct renesas_irqc_config irqc0_data = {
80 .irq_base = irq_pin(0), /* IRQ0 -> IRQ31 */ 78 .irq_base = irq_pin(0), /* IRQ0 -> IRQ31 */
@@ -192,12 +190,12 @@ static struct resource cmt10_resources[] = {
192 190
193void __init r8a73a4_add_dt_devices(void) 191void __init r8a73a4_add_dt_devices(void)
194{ 192{
195 r8a73a4_register_scif(SCIFA0); 193 r8a73a4_register_scif(0);
196 r8a73a4_register_scif(SCIFA1); 194 r8a73a4_register_scif(1);
197 r8a73a4_register_scif(SCIFB0); 195 r8a73a4_register_scif(2);
198 r8a73a4_register_scif(SCIFB1); 196 r8a73a4_register_scif(3);
199 r8a73a4_register_scif(SCIFB2); 197 r8a73a4_register_scif(4);
200 r8a73a4_register_scif(SCIFB3); 198 r8a73a4_register_scif(5);
201 r8a7790_register_cmt(10); 199 r8a7790_register_cmt(10);
202} 200}
203 201
@@ -275,7 +273,7 @@ static const struct sh_dmae_pdata dma_pdata = {
275 273
276static struct resource dma_resources[] = { 274static struct resource dma_resources[] = {
277 DEFINE_RES_MEM(0xe6700020, 0x89e0), 275 DEFINE_RES_MEM(0xe6700020, 0x89e0),
278 DEFINE_RES_IRQ_NAMED(gic_spi(220), "error_irq"), 276 DEFINE_RES_IRQ(gic_spi(220)),
279 { 277 {
280 /* IRQ for channels 0-19 */ 278 /* IRQ for channels 0-19 */
281 .start = gic_spi(200), 279 .start = gic_spi(200),
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index b7d4b2c3bc29..8f3c68101d59 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -203,167 +203,38 @@ static struct platform_device irqpin3_device = {
203 }, 203 },
204}; 204};
205 205
206/* SCIFA0 */ 206/* SCIF */
207static struct plat_sci_port scif0_platform_data = { 207#define R8A7740_SCIF(scif_type, index, baseaddr, irq) \
208 .mapbase = 0xe6c40000, 208static struct plat_sci_port scif##index##_platform_data = { \
209 .flags = UPF_BOOT_AUTOCONF, 209 .type = scif_type, \
210 .scscr = SCSCR_RE | SCSCR_TE, 210 .flags = UPF_BOOT_AUTOCONF, \
211 .scbrr_algo_id = SCBRR_ALGO_4, 211 .scscr = SCSCR_RE | SCSCR_TE, \
212 .type = PORT_SCIFA, 212}; \
213 .irqs = SCIx_IRQ_MUXED(gic_spi(100)), 213 \
214}; 214static struct resource scif##index##_resources[] = { \
215 215 DEFINE_RES_MEM(baseaddr, 0x100), \
216static struct platform_device scif0_device = { 216 DEFINE_RES_IRQ(irq), \
217 .name = "sh-sci", 217}; \
218 .id = 0, 218 \
219 .dev = { 219static struct platform_device scif##index##_device = { \
220 .platform_data = &scif0_platform_data, 220 .name = "sh-sci", \
221 }, 221 .id = index, \
222}; 222 .resource = scif##index##_resources, \
223 223 .num_resources = ARRAY_SIZE(scif##index##_resources), \
224/* SCIFA1 */ 224 .dev = { \
225static struct plat_sci_port scif1_platform_data = { 225 .platform_data = &scif##index##_platform_data, \
226 .mapbase = 0xe6c50000, 226 }, \
227 .flags = UPF_BOOT_AUTOCONF, 227}
228 .scscr = SCSCR_RE | SCSCR_TE,
229 .scbrr_algo_id = SCBRR_ALGO_4,
230 .type = PORT_SCIFA,
231 .irqs = SCIx_IRQ_MUXED(gic_spi(101)),
232};
233
234static struct platform_device scif1_device = {
235 .name = "sh-sci",
236 .id = 1,
237 .dev = {
238 .platform_data = &scif1_platform_data,
239 },
240};
241
242/* SCIFA2 */
243static struct plat_sci_port scif2_platform_data = {
244 .mapbase = 0xe6c60000,
245 .flags = UPF_BOOT_AUTOCONF,
246 .scscr = SCSCR_RE | SCSCR_TE,
247 .scbrr_algo_id = SCBRR_ALGO_4,
248 .type = PORT_SCIFA,
249 .irqs = SCIx_IRQ_MUXED(gic_spi(102)),
250};
251
252static struct platform_device scif2_device = {
253 .name = "sh-sci",
254 .id = 2,
255 .dev = {
256 .platform_data = &scif2_platform_data,
257 },
258};
259
260/* SCIFA3 */
261static struct plat_sci_port scif3_platform_data = {
262 .mapbase = 0xe6c70000,
263 .flags = UPF_BOOT_AUTOCONF,
264 .scscr = SCSCR_RE | SCSCR_TE,
265 .scbrr_algo_id = SCBRR_ALGO_4,
266 .type = PORT_SCIFA,
267 .irqs = SCIx_IRQ_MUXED(gic_spi(103)),
268};
269
270static struct platform_device scif3_device = {
271 .name = "sh-sci",
272 .id = 3,
273 .dev = {
274 .platform_data = &scif3_platform_data,
275 },
276};
277
278/* SCIFA4 */
279static struct plat_sci_port scif4_platform_data = {
280 .mapbase = 0xe6c80000,
281 .flags = UPF_BOOT_AUTOCONF,
282 .scscr = SCSCR_RE | SCSCR_TE,
283 .scbrr_algo_id = SCBRR_ALGO_4,
284 .type = PORT_SCIFA,
285 .irqs = SCIx_IRQ_MUXED(gic_spi(104)),
286};
287
288static struct platform_device scif4_device = {
289 .name = "sh-sci",
290 .id = 4,
291 .dev = {
292 .platform_data = &scif4_platform_data,
293 },
294};
295
296/* SCIFA5 */
297static struct plat_sci_port scif5_platform_data = {
298 .mapbase = 0xe6cb0000,
299 .flags = UPF_BOOT_AUTOCONF,
300 .scscr = SCSCR_RE | SCSCR_TE,
301 .scbrr_algo_id = SCBRR_ALGO_4,
302 .type = PORT_SCIFA,
303 .irqs = SCIx_IRQ_MUXED(gic_spi(105)),
304};
305
306static struct platform_device scif5_device = {
307 .name = "sh-sci",
308 .id = 5,
309 .dev = {
310 .platform_data = &scif5_platform_data,
311 },
312};
313
314/* SCIFA6 */
315static struct plat_sci_port scif6_platform_data = {
316 .mapbase = 0xe6cc0000,
317 .flags = UPF_BOOT_AUTOCONF,
318 .scscr = SCSCR_RE | SCSCR_TE,
319 .scbrr_algo_id = SCBRR_ALGO_4,
320 .type = PORT_SCIFA,
321 .irqs = SCIx_IRQ_MUXED(gic_spi(106)),
322};
323
324static struct platform_device scif6_device = {
325 .name = "sh-sci",
326 .id = 6,
327 .dev = {
328 .platform_data = &scif6_platform_data,
329 },
330};
331
332/* SCIFA7 */
333static struct plat_sci_port scif7_platform_data = {
334 .mapbase = 0xe6cd0000,
335 .flags = UPF_BOOT_AUTOCONF,
336 .scscr = SCSCR_RE | SCSCR_TE,
337 .scbrr_algo_id = SCBRR_ALGO_4,
338 .type = PORT_SCIFA,
339 .irqs = SCIx_IRQ_MUXED(gic_spi(107)),
340};
341
342static struct platform_device scif7_device = {
343 .name = "sh-sci",
344 .id = 7,
345 .dev = {
346 .platform_data = &scif7_platform_data,
347 },
348};
349
350/* SCIFB */
351static struct plat_sci_port scifb_platform_data = {
352 .mapbase = 0xe6c30000,
353 .flags = UPF_BOOT_AUTOCONF,
354 .scscr = SCSCR_RE | SCSCR_TE,
355 .scbrr_algo_id = SCBRR_ALGO_4,
356 .type = PORT_SCIFB,
357 .irqs = SCIx_IRQ_MUXED(gic_spi(108)),
358};
359 228
360static struct platform_device scifb_device = { 229R8A7740_SCIF(PORT_SCIFA, 0, 0xe6c40000, gic_spi(100));
361 .name = "sh-sci", 230R8A7740_SCIF(PORT_SCIFA, 1, 0xe6c50000, gic_spi(101));
362 .id = 8, 231R8A7740_SCIF(PORT_SCIFA, 2, 0xe6c60000, gic_spi(102));
363 .dev = { 232R8A7740_SCIF(PORT_SCIFA, 3, 0xe6c70000, gic_spi(103));
364 .platform_data = &scifb_platform_data, 233R8A7740_SCIF(PORT_SCIFA, 4, 0xe6c80000, gic_spi(104));
365 }, 234R8A7740_SCIF(PORT_SCIFA, 5, 0xe6cb0000, gic_spi(105));
366}; 235R8A7740_SCIF(PORT_SCIFA, 6, 0xe6cc0000, gic_spi(106));
236R8A7740_SCIF(PORT_SCIFA, 7, 0xe6cd0000, gic_spi(107));
237R8A7740_SCIF(PORT_SCIFB, 8, 0xe6c30000, gic_spi(108));
367 238
368/* CMT */ 239/* CMT */
369static struct sh_timer_config cmt10_platform_data = { 240static struct sh_timer_config cmt10_platform_data = {
@@ -528,7 +399,7 @@ static struct platform_device *r8a7740_devices_dt[] __initdata = {
528 &scif5_device, 399 &scif5_device,
529 &scif6_device, 400 &scif6_device,
530 &scif7_device, 401 &scif7_device,
531 &scifb_device, 402 &scif8_device,
532 &cmt10_device, 403 &cmt10_device,
533}; 404};
534 405
@@ -981,7 +852,7 @@ void __init r8a7740_add_standard_devices(void)
981 rmobile_add_device_to_domain("A3SP", &scif5_device); 852 rmobile_add_device_to_domain("A3SP", &scif5_device);
982 rmobile_add_device_to_domain("A3SP", &scif6_device); 853 rmobile_add_device_to_domain("A3SP", &scif6_device);
983 rmobile_add_device_to_domain("A3SP", &scif7_device); 854 rmobile_add_device_to_domain("A3SP", &scif7_device);
984 rmobile_add_device_to_domain("A3SP", &scifb_device); 855 rmobile_add_device_to_domain("A3SP", &scif8_device);
985 rmobile_add_device_to_domain("A3SP", &i2c1_device); 856 rmobile_add_device_to_domain("A3SP", &i2c1_device);
986} 857}
987 858
diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c
index 03fcc5974ef9..6d694526e4ca 100644
--- a/arch/arm/mach-shmobile/setup-r8a7778.c
+++ b/arch/arm/mach-shmobile/setup-r8a7778.c
@@ -44,24 +44,31 @@
44#include <asm/hardware/cache-l2x0.h> 44#include <asm/hardware/cache-l2x0.h>
45 45
46/* SCIF */ 46/* SCIF */
47#define SCIF_INFO(baseaddr, irq) \ 47#define R8A7778_SCIF(index, baseaddr, irq) \
48{ \ 48static struct plat_sci_port scif##index##_platform_data = { \
49 .mapbase = baseaddr, \
50 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ 49 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
51 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \ 50 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \
52 .scbrr_algo_id = SCBRR_ALGO_2, \
53 .type = PORT_SCIF, \ 51 .type = PORT_SCIF, \
54 .irqs = SCIx_IRQ_MUXED(irq), \ 52}; \
53 \
54static struct resource scif##index##_resources[] = { \
55 DEFINE_RES_MEM(baseaddr, 0x100), \
56 DEFINE_RES_IRQ(irq), \
55} 57}
56 58
57static struct plat_sci_port scif_platform_data[] __initdata = { 59R8A7778_SCIF(0, 0xffe40000, gic_iid(0x66));
58 SCIF_INFO(0xffe40000, gic_iid(0x66)), 60R8A7778_SCIF(1, 0xffe41000, gic_iid(0x67));
59 SCIF_INFO(0xffe41000, gic_iid(0x67)), 61R8A7778_SCIF(2, 0xffe42000, gic_iid(0x68));
60 SCIF_INFO(0xffe42000, gic_iid(0x68)), 62R8A7778_SCIF(3, 0xffe43000, gic_iid(0x69));
61 SCIF_INFO(0xffe43000, gic_iid(0x69)), 63R8A7778_SCIF(4, 0xffe44000, gic_iid(0x6a));
62 SCIF_INFO(0xffe44000, gic_iid(0x6a)), 64R8A7778_SCIF(5, 0xffe45000, gic_iid(0x6b));
63 SCIF_INFO(0xffe45000, gic_iid(0x6b)), 65
64}; 66#define r8a7778_register_scif(index) \
67 platform_device_register_resndata(&platform_bus, "sh-sci", index, \
68 scif##index##_resources, \
69 ARRAY_SIZE(scif##index##_resources), \
70 &scif##index##_platform_data, \
71 sizeof(scif##index##_platform_data))
65 72
66/* TMU */ 73/* TMU */
67static struct resource sh_tmu0_resources[] __initdata = { 74static struct resource sh_tmu0_resources[] __initdata = {
@@ -287,8 +294,6 @@ static void __init r8a7778_register_hspi(int id)
287 294
288void __init r8a7778_add_dt_devices(void) 295void __init r8a7778_add_dt_devices(void)
289{ 296{
290 int i;
291
292#ifdef CONFIG_CACHE_L2X0 297#ifdef CONFIG_CACHE_L2X0
293 void __iomem *base = ioremap_nocache(0xf0100000, 0x1000); 298 void __iomem *base = ioremap_nocache(0xf0100000, 0x1000);
294 if (base) { 299 if (base) {
@@ -300,11 +305,12 @@ void __init r8a7778_add_dt_devices(void)
300 } 305 }
301#endif 306#endif
302 307
303 for (i = 0; i < ARRAY_SIZE(scif_platform_data); i++) 308 r8a7778_register_scif(0);
304 platform_device_register_data(&platform_bus, "sh-sci", i, 309 r8a7778_register_scif(1);
305 &scif_platform_data[i], 310 r8a7778_register_scif(2);
306 sizeof(struct plat_sci_port)); 311 r8a7778_register_scif(3);
307 312 r8a7778_register_scif(4);
313 r8a7778_register_scif(5);
308 r8a7778_register_tmu(0); 314 r8a7778_register_tmu(0);
309 r8a7778_register_tmu(1); 315 r8a7778_register_tmu(1);
310} 316}
@@ -319,6 +325,52 @@ void __init r8a7778_add_dt_devices(void)
319#define HPB_DMAE_ASYNCMDR_ASMD21_SINGLE BIT(1) /* SDHI0 */ 325#define HPB_DMAE_ASYNCMDR_ASMD21_SINGLE BIT(1) /* SDHI0 */
320#define HPB_DMAE_ASYNCMDR_ASMD21_MULTI 0 /* SDHI0 */ 326#define HPB_DMAE_ASYNCMDR_ASMD21_MULTI 0 /* SDHI0 */
321 327
328#define HPBDMA_SSI(_id) \
329{ \
330 .id = HPBDMA_SLAVE_SSI## _id ##_TX, \
331 .addr = 0xffd91008 + (_id * 0x40), \
332 .dcr = HPB_DMAE_DCR_CT | \
333 HPB_DMAE_DCR_DIP | \
334 HPB_DMAE_DCR_SPDS_32BIT | \
335 HPB_DMAE_DCR_DMDL | \
336 HPB_DMAE_DCR_DPDS_32BIT, \
337 .port = _id + (_id << 8), \
338 .dma_ch = (28 + _id), \
339}, { \
340 .id = HPBDMA_SLAVE_SSI## _id ##_RX, \
341 .addr = 0xffd9100c + (_id * 0x40), \
342 .dcr = HPB_DMAE_DCR_CT | \
343 HPB_DMAE_DCR_DIP | \
344 HPB_DMAE_DCR_SMDL | \
345 HPB_DMAE_DCR_SPDS_32BIT | \
346 HPB_DMAE_DCR_DPDS_32BIT, \
347 .port = _id + (_id << 8), \
348 .dma_ch = (28 + _id), \
349}
350
351#define HPBDMA_HPBIF(_id) \
352{ \
353 .id = HPBDMA_SLAVE_HPBIF## _id ##_TX, \
354 .addr = 0xffda0000 + (_id * 0x1000), \
355 .dcr = HPB_DMAE_DCR_CT | \
356 HPB_DMAE_DCR_DIP | \
357 HPB_DMAE_DCR_SPDS_32BIT | \
358 HPB_DMAE_DCR_DMDL | \
359 HPB_DMAE_DCR_DPDS_32BIT, \
360 .port = 0x1111, \
361 .dma_ch = (28 + _id), \
362}, { \
363 .id = HPBDMA_SLAVE_HPBIF## _id ##_RX, \
364 .addr = 0xffda0000 + (_id * 0x1000), \
365 .dcr = HPB_DMAE_DCR_CT | \
366 HPB_DMAE_DCR_DIP | \
367 HPB_DMAE_DCR_SMDL | \
368 HPB_DMAE_DCR_SPDS_32BIT | \
369 HPB_DMAE_DCR_DPDS_32BIT, \
370 .port = 0x1111, \
371 .dma_ch = (28 + _id), \
372}
373
322static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = { 374static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = {
323 { 375 {
324 .id = HPBDMA_SLAVE_SDHI0_TX, 376 .id = HPBDMA_SLAVE_SDHI0_TX,
@@ -348,12 +400,86 @@ static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = {
348 .port = 0x0D0C, 400 .port = 0x0D0C,
349 .flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE, 401 .flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE,
350 .dma_ch = 22, 402 .dma_ch = 22,
403 }, {
404 .id = HPBDMA_SLAVE_USBFUNC_TX, /* for D0 */
405 .addr = 0xffe60018,
406 .dcr = HPB_DMAE_DCR_SPDS_32BIT |
407 HPB_DMAE_DCR_DMDL |
408 HPB_DMAE_DCR_DPDS_32BIT,
409 .port = 0x0000,
410 .dma_ch = 14,
411 }, {
412 .id = HPBDMA_SLAVE_USBFUNC_RX, /* for D1 */
413 .addr = 0xffe6001c,
414 .dcr = HPB_DMAE_DCR_SMDL |
415 HPB_DMAE_DCR_SPDS_32BIT |
416 HPB_DMAE_DCR_DPDS_32BIT,
417 .port = 0x0101,
418 .dma_ch = 15,
351 }, 419 },
420
421 HPBDMA_SSI(0),
422 HPBDMA_SSI(1),
423 HPBDMA_SSI(2),
424 HPBDMA_SSI(3),
425 HPBDMA_SSI(4),
426 HPBDMA_SSI(5),
427 HPBDMA_SSI(6),
428 HPBDMA_SSI(7),
429 HPBDMA_SSI(8),
430
431 HPBDMA_HPBIF(0),
432 HPBDMA_HPBIF(1),
433 HPBDMA_HPBIF(2),
434 HPBDMA_HPBIF(3),
435 HPBDMA_HPBIF(4),
436 HPBDMA_HPBIF(5),
437 HPBDMA_HPBIF(6),
438 HPBDMA_HPBIF(7),
439 HPBDMA_HPBIF(8),
352}; 440};
353 441
354static const struct hpb_dmae_channel hpb_dmae_channels[] = { 442static const struct hpb_dmae_channel hpb_dmae_channels[] = {
443 HPB_DMAE_CHANNEL(0x7c, HPBDMA_SLAVE_USBFUNC_TX), /* ch. 14 */
444 HPB_DMAE_CHANNEL(0x7c, HPBDMA_SLAVE_USBFUNC_RX), /* ch. 15 */
355 HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_TX), /* ch. 21 */ 445 HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_TX), /* ch. 21 */
356 HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_RX), /* ch. 22 */ 446 HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_RX), /* ch. 22 */
447 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI0_TX), /* ch. 28 */
448 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI0_RX), /* ch. 28 */
449 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF0_TX), /* ch. 28 */
450 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF0_RX), /* ch. 28 */
451 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI1_TX), /* ch. 29 */
452 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI1_RX), /* ch. 29 */
453 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF1_TX), /* ch. 29 */
454 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF1_RX), /* ch. 29 */
455 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI2_TX), /* ch. 30 */
456 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI2_RX), /* ch. 30 */
457 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF2_TX), /* ch. 30 */
458 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF2_RX), /* ch. 30 */
459 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI3_TX), /* ch. 31 */
460 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI3_RX), /* ch. 31 */
461 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF3_TX), /* ch. 31 */
462 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF3_RX), /* ch. 31 */
463 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI4_TX), /* ch. 32 */
464 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI4_RX), /* ch. 32 */
465 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF4_TX), /* ch. 32 */
466 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF4_RX), /* ch. 32 */
467 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI5_TX), /* ch. 33 */
468 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI5_RX), /* ch. 33 */
469 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF5_TX), /* ch. 33 */
470 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF5_RX), /* ch. 33 */
471 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI6_TX), /* ch. 34 */
472 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI6_RX), /* ch. 34 */
473 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF6_TX), /* ch. 34 */
474 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF6_RX), /* ch. 34 */
475 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI7_TX), /* ch. 35 */
476 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI7_RX), /* ch. 35 */
477 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF7_TX), /* ch. 35 */
478 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF7_RX), /* ch. 35 */
479 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI8_TX), /* ch. 36 */
480 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI8_RX), /* ch. 36 */
481 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF8_TX), /* ch. 36 */
482 HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF8_RX), /* ch. 36 */
357}; 483};
358 484
359static struct hpb_dmae_pdata dma_platform_data __initdata = { 485static struct hpb_dmae_pdata dma_platform_data __initdata = {
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index 13049e9d691c..339292e85838 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -188,107 +188,35 @@ void __init r8a7779_pinmux_init(void)
188 ARRAY_SIZE(r8a7779_pinctrl_devices)); 188 ARRAY_SIZE(r8a7779_pinctrl_devices));
189} 189}
190 190
191static struct plat_sci_port scif0_platform_data = { 191/* SCIF */
192 .mapbase = 0xffe40000, 192#define R8A7779_SCIF(index, baseaddr, irq) \
193 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, 193static struct plat_sci_port scif##index##_platform_data = { \
194 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, 194 .type = PORT_SCIF, \
195 .scbrr_algo_id = SCBRR_ALGO_2, 195 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
196 .type = PORT_SCIF, 196 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \
197 .irqs = SCIx_IRQ_MUXED(gic_iid(0x78)), 197}; \
198}; 198 \
199 199static struct resource scif##index##_resources[] = { \
200static struct platform_device scif0_device = { 200 DEFINE_RES_MEM(baseaddr, 0x100), \
201 .name = "sh-sci", 201 DEFINE_RES_IRQ(irq), \
202 .id = 0, 202}; \
203 .dev = { 203 \
204 .platform_data = &scif0_platform_data, 204static struct platform_device scif##index##_device = { \
205 }, 205 .name = "sh-sci", \
206}; 206 .id = index, \
207 207 .resource = scif##index##_resources, \
208static struct plat_sci_port scif1_platform_data = { 208 .num_resources = ARRAY_SIZE(scif##index##_resources), \
209 .mapbase = 0xffe41000, 209 .dev = { \
210 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, 210 .platform_data = &scif##index##_platform_data, \
211 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, 211 }, \
212 .scbrr_algo_id = SCBRR_ALGO_2, 212}
213 .type = PORT_SCIF,
214 .irqs = SCIx_IRQ_MUXED(gic_iid(0x79)),
215};
216
217static struct platform_device scif1_device = {
218 .name = "sh-sci",
219 .id = 1,
220 .dev = {
221 .platform_data = &scif1_platform_data,
222 },
223};
224
225static struct plat_sci_port scif2_platform_data = {
226 .mapbase = 0xffe42000,
227 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
228 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
229 .scbrr_algo_id = SCBRR_ALGO_2,
230 .type = PORT_SCIF,
231 .irqs = SCIx_IRQ_MUXED(gic_iid(0x7a)),
232};
233
234static struct platform_device scif2_device = {
235 .name = "sh-sci",
236 .id = 2,
237 .dev = {
238 .platform_data = &scif2_platform_data,
239 },
240};
241
242static struct plat_sci_port scif3_platform_data = {
243 .mapbase = 0xffe43000,
244 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
245 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
246 .scbrr_algo_id = SCBRR_ALGO_2,
247 .type = PORT_SCIF,
248 .irqs = SCIx_IRQ_MUXED(gic_iid(0x7b)),
249};
250
251static struct platform_device scif3_device = {
252 .name = "sh-sci",
253 .id = 3,
254 .dev = {
255 .platform_data = &scif3_platform_data,
256 },
257};
258
259static struct plat_sci_port scif4_platform_data = {
260 .mapbase = 0xffe44000,
261 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
262 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
263 .scbrr_algo_id = SCBRR_ALGO_2,
264 .type = PORT_SCIF,
265 .irqs = SCIx_IRQ_MUXED(gic_iid(0x7c)),
266};
267
268static struct platform_device scif4_device = {
269 .name = "sh-sci",
270 .id = 4,
271 .dev = {
272 .platform_data = &scif4_platform_data,
273 },
274};
275
276static struct plat_sci_port scif5_platform_data = {
277 .mapbase = 0xffe45000,
278 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
279 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
280 .scbrr_algo_id = SCBRR_ALGO_2,
281 .type = PORT_SCIF,
282 .irqs = SCIx_IRQ_MUXED(gic_iid(0x7d)),
283};
284 213
285static struct platform_device scif5_device = { 214R8A7779_SCIF(0, 0xffe40000, gic_iid(0x78));
286 .name = "sh-sci", 215R8A7779_SCIF(1, 0xffe41000, gic_iid(0x79));
287 .id = 5, 216R8A7779_SCIF(2, 0xffe42000, gic_iid(0x7a));
288 .dev = { 217R8A7779_SCIF(3, 0xffe43000, gic_iid(0x7b));
289 .platform_data = &scif5_platform_data, 218R8A7779_SCIF(4, 0xffe44000, gic_iid(0x7c));
290 }, 219R8A7779_SCIF(5, 0xffe45000, gic_iid(0x7d));
291};
292 220
293/* TMU */ 221/* TMU */
294static struct sh_timer_config tmu00_platform_data = { 222static struct sh_timer_config tmu00_platform_data = {
diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
index c47bcebbcb00..66476d21544d 100644
--- a/arch/arm/mach-shmobile/setup-r8a7790.c
+++ b/arch/arm/mach-shmobile/setup-r8a7790.c
@@ -63,6 +63,27 @@ R8A7790_GPIO(5);
63 &r8a7790_gpio##idx##_platform_data, \ 63 &r8a7790_gpio##idx##_platform_data, \
64 sizeof(r8a7790_gpio##idx##_platform_data)) 64 sizeof(r8a7790_gpio##idx##_platform_data))
65 65
66static struct resource i2c_resources[] __initdata = {
67 /* I2C0 */
68 DEFINE_RES_MEM(0xE6508000, 0x40),
69 DEFINE_RES_IRQ(gic_spi(287)),
70 /* I2C1 */
71 DEFINE_RES_MEM(0xE6518000, 0x40),
72 DEFINE_RES_IRQ(gic_spi(288)),
73 /* I2C2 */
74 DEFINE_RES_MEM(0xE6530000, 0x40),
75 DEFINE_RES_IRQ(gic_spi(286)),
76 /* I2C3 */
77 DEFINE_RES_MEM(0xE6540000, 0x40),
78 DEFINE_RES_IRQ(gic_spi(290)),
79
80};
81
82#define r8a7790_register_i2c(idx) \
83 platform_device_register_simple( \
84 "i2c-rcar", idx, \
85 i2c_resources + (2 * idx), 2); \
86
66void __init r8a7790_pinmux_init(void) 87void __init r8a7790_pinmux_init(void)
67{ 88{
68 platform_device_register_simple("pfc-r8a7790", -1, pfc_resources, 89 platform_device_register_simple("pfc-r8a7790", -1, pfc_resources,
@@ -73,63 +94,57 @@ void __init r8a7790_pinmux_init(void)
73 r8a7790_register_gpio(3); 94 r8a7790_register_gpio(3);
74 r8a7790_register_gpio(4); 95 r8a7790_register_gpio(4);
75 r8a7790_register_gpio(5); 96 r8a7790_register_gpio(5);
97 r8a7790_register_i2c(0);
98 r8a7790_register_i2c(1);
99 r8a7790_register_i2c(2);
100 r8a7790_register_i2c(3);
76} 101}
77 102
78#define SCIF_COMMON(scif_type, baseaddr, irq) \ 103#define __R8A7790_SCIF(scif_type, _scscr, index, baseaddr, irq) \
79 .type = scif_type, \ 104static struct plat_sci_port scif##index##_platform_data = { \
80 .mapbase = baseaddr, \ 105 .type = scif_type, \
81 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ 106 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
82 .irqs = SCIx_IRQ_MUXED(irq) 107 .scscr = _scscr, \
83 108}; \
84#define SCIFA_DATA(index, baseaddr, irq) \ 109 \
85[index] = { \ 110static struct resource scif##index##_resources[] = { \
86 SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \ 111 DEFINE_RES_MEM(baseaddr, 0x100), \
87 .scbrr_algo_id = SCBRR_ALGO_4, \ 112 DEFINE_RES_IRQ(irq), \
88 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \
89}
90
91#define SCIFB_DATA(index, baseaddr, irq) \
92[index] = { \
93 SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \
94 .scbrr_algo_id = SCBRR_ALGO_4, \
95 .scscr = SCSCR_RE | SCSCR_TE, \
96}
97
98#define SCIF_DATA(index, baseaddr, irq) \
99[index] = { \
100 SCIF_COMMON(PORT_SCIF, baseaddr, irq), \
101 .scbrr_algo_id = SCBRR_ALGO_2, \
102 .scscr = SCSCR_RE | SCSCR_TE, \
103}
104
105#define HSCIF_DATA(index, baseaddr, irq) \
106[index] = { \
107 SCIF_COMMON(PORT_HSCIF, baseaddr, irq), \
108 .scbrr_algo_id = SCBRR_ALGO_6, \
109 .scscr = SCSCR_RE | SCSCR_TE, \
110} 113}
111 114
112enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1, 115#define R8A7790_SCIF(index, baseaddr, irq) \
113 HSCIF0, HSCIF1 }; 116 __R8A7790_SCIF(PORT_SCIF, SCSCR_RE | SCSCR_TE, \
114 117 index, baseaddr, irq)
115static const struct plat_sci_port scif[] __initconst = { 118
116 SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */ 119#define R8A7790_SCIFA(index, baseaddr, irq) \
117 SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */ 120 __R8A7790_SCIF(PORT_SCIFA, SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \
118 SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */ 121 index, baseaddr, irq)
119 SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */ 122
120 SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */ 123#define R8A7790_SCIFB(index, baseaddr, irq) \
121 SCIFA_DATA(SCIFA2, 0xe6c60000, gic_spi(151)), /* SCIFA2 */ 124 __R8A7790_SCIF(PORT_SCIFB, SCSCR_RE | SCSCR_TE, \
122 SCIF_DATA(SCIF0, 0xe6e60000, gic_spi(152)), /* SCIF0 */ 125 index, baseaddr, irq)
123 SCIF_DATA(SCIF1, 0xe6e68000, gic_spi(153)), /* SCIF1 */ 126
124 HSCIF_DATA(HSCIF0, 0xe62c0000, gic_spi(154)), /* HSCIF0 */ 127#define R8A7790_HSCIF(index, baseaddr, irq) \
125 HSCIF_DATA(HSCIF1, 0xe62c8000, gic_spi(155)), /* HSCIF1 */ 128 __R8A7790_SCIF(PORT_HSCIF, SCSCR_RE | SCSCR_TE, \
126}; 129 index, baseaddr, irq)
127 130
128static inline void r8a7790_register_scif(int idx) 131R8A7790_SCIFA(0, 0xe6c40000, gic_spi(144)); /* SCIFA0 */
129{ 132R8A7790_SCIFA(1, 0xe6c50000, gic_spi(145)); /* SCIFA1 */
130 platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx], 133R8A7790_SCIFB(2, 0xe6c20000, gic_spi(148)); /* SCIFB0 */
131 sizeof(struct plat_sci_port)); 134R8A7790_SCIFB(3, 0xe6c30000, gic_spi(149)); /* SCIFB1 */
132} 135R8A7790_SCIFB(4, 0xe6ce0000, gic_spi(150)); /* SCIFB2 */
136R8A7790_SCIFA(5, 0xe6c60000, gic_spi(151)); /* SCIFA2 */
137R8A7790_SCIF(6, 0xe6e60000, gic_spi(152)); /* SCIF0 */
138R8A7790_SCIF(7, 0xe6e68000, gic_spi(153)); /* SCIF1 */
139R8A7790_HSCIF(8, 0xe62c0000, gic_spi(154)); /* HSCIF0 */
140R8A7790_HSCIF(9, 0xe62c8000, gic_spi(155)); /* HSCIF1 */
141
142#define r8a7790_register_scif(index) \
143 platform_device_register_resndata(&platform_bus, "sh-sci", index, \
144 scif##index##_resources, \
145 ARRAY_SIZE(scif##index##_resources), \
146 &scif##index##_platform_data, \
147 sizeof(scif##index##_platform_data))
133 148
134static const struct renesas_irqc_config irqc0_data __initconst = { 149static const struct renesas_irqc_config irqc0_data __initconst = {
135 .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ 150 .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
@@ -182,16 +197,16 @@ static const struct resource cmt00_resources[] __initconst = {
182 197
183void __init r8a7790_add_dt_devices(void) 198void __init r8a7790_add_dt_devices(void)
184{ 199{
185 r8a7790_register_scif(SCIFA0); 200 r8a7790_register_scif(0);
186 r8a7790_register_scif(SCIFA1); 201 r8a7790_register_scif(1);
187 r8a7790_register_scif(SCIFB0); 202 r8a7790_register_scif(2);
188 r8a7790_register_scif(SCIFB1); 203 r8a7790_register_scif(3);
189 r8a7790_register_scif(SCIFB2); 204 r8a7790_register_scif(4);
190 r8a7790_register_scif(SCIFA2); 205 r8a7790_register_scif(5);
191 r8a7790_register_scif(SCIF0); 206 r8a7790_register_scif(6);
192 r8a7790_register_scif(SCIF1); 207 r8a7790_register_scif(7);
193 r8a7790_register_scif(HSCIF0); 208 r8a7790_register_scif(8);
194 r8a7790_register_scif(HSCIF1); 209 r8a7790_register_scif(9);
195 r8a7790_register_cmt(00); 210 r8a7790_register_cmt(00);
196} 211}
197 212
diff --git a/arch/arm/mach-shmobile/setup-r8a7791.c b/arch/arm/mach-shmobile/setup-r8a7791.c
index d9393d61ee27..e28404e43860 100644
--- a/arch/arm/mach-shmobile/setup-r8a7791.c
+++ b/arch/arm/mach-shmobile/setup-r8a7791.c
@@ -22,6 +22,7 @@
22#include <linux/irq.h> 22#include <linux/irq.h>
23#include <linux/kernel.h> 23#include <linux/kernel.h>
24#include <linux/of_platform.h> 24#include <linux/of_platform.h>
25#include <linux/platform_data/gpio-rcar.h>
25#include <linux/platform_data/irq-renesas-irqc.h> 26#include <linux/platform_data/irq-renesas-irqc.h>
26#include <linux/serial_sci.h> 27#include <linux/serial_sci.h>
27#include <linux/sh_timer.h> 28#include <linux/sh_timer.h>
@@ -31,66 +32,101 @@
31#include <mach/rcar-gen2.h> 32#include <mach/rcar-gen2.h>
32#include <asm/mach/arch.h> 33#include <asm/mach/arch.h>
33 34
34#define SCIF_COMMON(scif_type, baseaddr, irq) \ 35static const struct resource pfc_resources[] __initconst = {
35 .type = scif_type, \ 36 DEFINE_RES_MEM(0xe6060000, 0x250),
36 .mapbase = baseaddr, \ 37};
37 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
38 .irqs = SCIx_IRQ_MUXED(irq)
39
40#define SCIFA_DATA(index, baseaddr, irq) \
41[index] = { \
42 SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \
43 .scbrr_algo_id = SCBRR_ALGO_4, \
44 .scscr = SCSCR_RE | SCSCR_TE, \
45}
46
47#define SCIFB_DATA(index, baseaddr, irq) \
48[index] = { \
49 SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \
50 .scbrr_algo_id = SCBRR_ALGO_4, \
51 .scscr = SCSCR_RE | SCSCR_TE, \
52}
53 38
54#define SCIF_DATA(index, baseaddr, irq) \ 39#define r8a7791_register_pfc() \
55[index] = { \ 40 platform_device_register_simple("pfc-r8a7791", -1, pfc_resources, \
56 SCIF_COMMON(PORT_SCIF, baseaddr, irq), \ 41 ARRAY_SIZE(pfc_resources))
57 .scbrr_algo_id = SCBRR_ALGO_2, \ 42
58 .scscr = SCSCR_RE | SCSCR_TE, \ 43#define R8A7791_GPIO(idx, base, nr) \
44static const struct resource r8a7791_gpio##idx##_resources[] __initconst = { \
45 DEFINE_RES_MEM((base), 0x50), \
46 DEFINE_RES_IRQ(gic_spi(4 + (idx))), \
47}; \
48 \
49static const struct gpio_rcar_config \
50r8a7791_gpio##idx##_platform_data __initconst = { \
51 .gpio_base = 32 * (idx), \
52 .irq_base = 0, \
53 .number_of_pins = (nr), \
54 .pctl_name = "pfc-r8a7791", \
55 .has_both_edge_trigger = 1, \
56}; \
57
58R8A7791_GPIO(0, 0xe6050000, 32);
59R8A7791_GPIO(1, 0xe6051000, 32);
60R8A7791_GPIO(2, 0xe6052000, 32);
61R8A7791_GPIO(3, 0xe6053000, 32);
62R8A7791_GPIO(4, 0xe6054000, 32);
63R8A7791_GPIO(5, 0xe6055000, 32);
64R8A7791_GPIO(6, 0xe6055400, 32);
65R8A7791_GPIO(7, 0xe6055800, 26);
66
67#define r8a7791_register_gpio(idx) \
68 platform_device_register_resndata(&platform_bus, "gpio_rcar", idx, \
69 r8a7791_gpio##idx##_resources, \
70 ARRAY_SIZE(r8a7791_gpio##idx##_resources), \
71 &r8a7791_gpio##idx##_platform_data, \
72 sizeof(r8a7791_gpio##idx##_platform_data))
73
74void __init r8a7791_pinmux_init(void)
75{
76 r8a7791_register_pfc();
77 r8a7791_register_gpio(0);
78 r8a7791_register_gpio(1);
79 r8a7791_register_gpio(2);
80 r8a7791_register_gpio(3);
81 r8a7791_register_gpio(4);
82 r8a7791_register_gpio(5);
83 r8a7791_register_gpio(6);
84 r8a7791_register_gpio(7);
59} 85}
60 86
61#define HSCIF_DATA(index, baseaddr, irq) \ 87#define __R8A7791_SCIF(scif_type, index, baseaddr, irq) \
62[index] = { \ 88static struct plat_sci_port scif##index##_platform_data = { \
63 SCIF_COMMON(PORT_HSCIF, baseaddr, irq), \ 89 .type = scif_type, \
64 .scbrr_algo_id = SCBRR_ALGO_6, \ 90 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
65 .scscr = SCSCR_RE | SCSCR_TE, \ 91 .scscr = SCSCR_RE | SCSCR_TE, \
92}; \
93 \
94static struct resource scif##index##_resources[] = { \
95 DEFINE_RES_MEM(baseaddr, 0x100), \
96 DEFINE_RES_IRQ(irq), \
66} 97}
67 98
68enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1, 99#define R8A7791_SCIF(index, baseaddr, irq) \
69 SCIF2, SCIF3, SCIF4, SCIF5, SCIFA3, SCIFA4, SCIFA5 }; 100 __R8A7791_SCIF(PORT_SCIF, index, baseaddr, irq)
70 101
71static const struct plat_sci_port scif[] __initconst = { 102#define R8A7791_SCIFA(index, baseaddr, irq) \
72 SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */ 103 __R8A7791_SCIF(PORT_SCIFA, index, baseaddr, irq)
73 SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */ 104
74 SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */ 105#define R8A7791_SCIFB(index, baseaddr, irq) \
75 SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */ 106 __R8A7791_SCIF(PORT_SCIFB, index, baseaddr, irq)
76 SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */ 107
77 SCIFA_DATA(SCIFA2, 0xe6c60000, gic_spi(151)), /* SCIFA2 */ 108R8A7791_SCIFA(0, 0xe6c40000, gic_spi(144)); /* SCIFA0 */
78 SCIF_DATA(SCIF0, 0xe6e60000, gic_spi(152)), /* SCIF0 */ 109R8A7791_SCIFA(1, 0xe6c50000, gic_spi(145)); /* SCIFA1 */
79 SCIF_DATA(SCIF1, 0xe6e68000, gic_spi(153)), /* SCIF1 */ 110R8A7791_SCIFB(2, 0xe6c20000, gic_spi(148)); /* SCIFB0 */
80 SCIF_DATA(SCIF2, 0xe6e58000, gic_spi(22)), /* SCIF2 */ 111R8A7791_SCIFB(3, 0xe6c30000, gic_spi(149)); /* SCIFB1 */
81 SCIF_DATA(SCIF3, 0xe6ea8000, gic_spi(23)), /* SCIF3 */ 112R8A7791_SCIFB(4, 0xe6ce0000, gic_spi(150)); /* SCIFB2 */
82 SCIF_DATA(SCIF4, 0xe6ee0000, gic_spi(24)), /* SCIF4 */ 113R8A7791_SCIFA(5, 0xe6c60000, gic_spi(151)); /* SCIFA2 */
83 SCIF_DATA(SCIF5, 0xe6ee8000, gic_spi(25)), /* SCIF5 */ 114R8A7791_SCIF(6, 0xe6e60000, gic_spi(152)); /* SCIF0 */
84 SCIFA_DATA(SCIFA3, 0xe6c70000, gic_spi(29)), /* SCIFA3 */ 115R8A7791_SCIF(7, 0xe6e68000, gic_spi(153)); /* SCIF1 */
85 SCIFA_DATA(SCIFA4, 0xe6c78000, gic_spi(30)), /* SCIFA4 */ 116R8A7791_SCIF(8, 0xe6e58000, gic_spi(22)); /* SCIF2 */
86 SCIFA_DATA(SCIFA5, 0xe6c80000, gic_spi(31)), /* SCIFA5 */ 117R8A7791_SCIF(9, 0xe6ea8000, gic_spi(23)); /* SCIF3 */
87}; 118R8A7791_SCIF(10, 0xe6ee0000, gic_spi(24)); /* SCIF4 */
88 119R8A7791_SCIF(11, 0xe6ee8000, gic_spi(25)); /* SCIF5 */
89static inline void r8a7791_register_scif(int idx) 120R8A7791_SCIFA(12, 0xe6c70000, gic_spi(29)); /* SCIFA3 */
90{ 121R8A7791_SCIFA(13, 0xe6c78000, gic_spi(30)); /* SCIFA4 */
91 platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx], 122R8A7791_SCIFA(14, 0xe6c80000, gic_spi(31)); /* SCIFA5 */
92 sizeof(struct plat_sci_port)); 123
93} 124#define r8a7791_register_scif(index) \
125 platform_device_register_resndata(&platform_bus, "sh-sci", index, \
126 scif##index##_resources, \
127 ARRAY_SIZE(scif##index##_resources), \
128 &scif##index##_platform_data, \
129 sizeof(scif##index##_platform_data))
94 130
95static const struct sh_timer_config cmt00_platform_data __initconst = { 131static const struct sh_timer_config cmt00_platform_data __initconst = {
96 .name = "CMT00", 132 .name = "CMT00",
@@ -136,23 +172,34 @@ static struct resource irqc0_resources[] = {
136 &irqc##idx##_data, \ 172 &irqc##idx##_data, \
137 sizeof(struct renesas_irqc_config)) 173 sizeof(struct renesas_irqc_config))
138 174
175static const struct resource thermal_resources[] __initconst = {
176 DEFINE_RES_MEM(0xe61f0000, 0x14),
177 DEFINE_RES_MEM(0xe61f0100, 0x38),
178 DEFINE_RES_IRQ(gic_spi(69)),
179};
180
181#define r8a7791_register_thermal() \
182 platform_device_register_simple("rcar_thermal", -1, \
183 thermal_resources, \
184 ARRAY_SIZE(thermal_resources))
185
139void __init r8a7791_add_dt_devices(void) 186void __init r8a7791_add_dt_devices(void)
140{ 187{
141 r8a7791_register_scif(SCIFA0); 188 r8a7791_register_scif(0);
142 r8a7791_register_scif(SCIFA1); 189 r8a7791_register_scif(1);
143 r8a7791_register_scif(SCIFB0); 190 r8a7791_register_scif(2);
144 r8a7791_register_scif(SCIFB1); 191 r8a7791_register_scif(3);
145 r8a7791_register_scif(SCIFB2); 192 r8a7791_register_scif(4);
146 r8a7791_register_scif(SCIFA2); 193 r8a7791_register_scif(5);
147 r8a7791_register_scif(SCIF0); 194 r8a7791_register_scif(6);
148 r8a7791_register_scif(SCIF1); 195 r8a7791_register_scif(7);
149 r8a7791_register_scif(SCIF2); 196 r8a7791_register_scif(8);
150 r8a7791_register_scif(SCIF3); 197 r8a7791_register_scif(9);
151 r8a7791_register_scif(SCIF4); 198 r8a7791_register_scif(10);
152 r8a7791_register_scif(SCIF5); 199 r8a7791_register_scif(11);
153 r8a7791_register_scif(SCIFA3); 200 r8a7791_register_scif(12);
154 r8a7791_register_scif(SCIFA4); 201 r8a7791_register_scif(13);
155 r8a7791_register_scif(SCIFA5); 202 r8a7791_register_scif(14);
156 r8a7791_register_cmt(00); 203 r8a7791_register_cmt(00);
157} 204}
158 205
@@ -160,6 +207,7 @@ void __init r8a7791_add_standard_devices(void)
160{ 207{
161 r8a7791_add_dt_devices(); 208 r8a7791_add_dt_devices();
162 r8a7791_register_irqc(0); 209 r8a7791_register_irqc(0);
210 r8a7791_register_thermal();
163} 211}
164 212
165void __init r8a7791_init_early(void) 213void __init r8a7791_init_early(void)
diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c b/arch/arm/mach-shmobile/setup-rcar-gen2.c
index 5734c24bf6c7..69ccc6c6fd33 100644
--- a/arch/arm/mach-shmobile/setup-rcar-gen2.c
+++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c
@@ -18,6 +18,7 @@
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */ 19 */
20 20
21#include <linux/clk/shmobile.h>
21#include <linux/clocksource.h> 22#include <linux/clocksource.h>
22#include <linux/io.h> 23#include <linux/io.h>
23#include <linux/kernel.h> 24#include <linux/kernel.h>
@@ -44,8 +45,10 @@ u32 __init rcar_gen2_read_mode_pins(void)
44 45
45void __init rcar_gen2_timer_init(void) 46void __init rcar_gen2_timer_init(void)
46{ 47{
47#ifdef CONFIG_ARM_ARCH_TIMER 48#if defined(CONFIG_ARM_ARCH_TIMER) || defined(CONFIG_COMMON_CLK)
48 u32 mode = rcar_gen2_read_mode_pins(); 49 u32 mode = rcar_gen2_read_mode_pins();
50#endif
51#ifdef CONFIG_ARM_ARCH_TIMER
49 void __iomem *base; 52 void __iomem *base;
50 int extal_mhz = 0; 53 int extal_mhz = 0;
51 u32 freq; 54 u32 freq;
@@ -78,14 +81,28 @@ void __init rcar_gen2_timer_init(void)
78 /* Remap "armgcnt address map" space */ 81 /* Remap "armgcnt address map" space */
79 base = ioremap(0xe6080000, PAGE_SIZE); 82 base = ioremap(0xe6080000, PAGE_SIZE);
80 83
81 /* Update registers with correct frequency */ 84 /*
82 iowrite32(freq, base + CNTFID0); 85 * Update the timer if it is either not running, or is not at the
83 asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq)); 86 * right frequency. The timer is only configurable in secure mode
87 * so this avoids an abort if the loader started the timer and
88 * entered the kernel in non-secure mode.
89 */
90
91 if ((ioread32(base + CNTCR) & 1) == 0 ||
92 ioread32(base + CNTFID0) != freq) {
93 /* Update registers with correct frequency */
94 iowrite32(freq, base + CNTFID0);
95 asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
96
97 /* make sure arch timer is started by setting bit 0 of CNTCR */
98 iowrite32(1, base + CNTCR);
99 }
84 100
85 /* make sure arch timer is started by setting bit 0 of CNTCR */
86 iowrite32(1, base + CNTCR);
87 iounmap(base); 101 iounmap(base);
88#endif /* CONFIG_ARM_ARCH_TIMER */ 102#endif /* CONFIG_ARM_ARCH_TIMER */
89 103
104#ifdef CONFIG_COMMON_CLK
105 rcar_gen2_clocks_init(mode);
106#endif
90 clocksource_of_init(); 107 clocksource_of_init();
91} 108}
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
index 311878391e18..27301278c208 100644
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ b/arch/arm/mach-shmobile/setup-sh7372.c
@@ -86,138 +86,36 @@ void __init sh7372_pinmux_init(void)
86 platform_device_register(&sh7372_pfc_device); 86 platform_device_register(&sh7372_pfc_device);
87} 87}
88 88
89/* SCIFA0 */ 89/* SCIF */
90static struct plat_sci_port scif0_platform_data = { 90#define SH7372_SCIF(scif_type, index, baseaddr, irq) \
91 .mapbase = 0xe6c40000, 91static struct plat_sci_port scif##index##_platform_data = { \
92 .flags = UPF_BOOT_AUTOCONF, 92 .type = scif_type, \
93 .scscr = SCSCR_RE | SCSCR_TE, 93 .flags = UPF_BOOT_AUTOCONF, \
94 .scbrr_algo_id = SCBRR_ALGO_4, 94 .scscr = SCSCR_RE | SCSCR_TE, \
95 .type = PORT_SCIFA, 95}; \
96 .irqs = { evt2irq(0x0c00), evt2irq(0x0c00), 96 \
97 evt2irq(0x0c00), evt2irq(0x0c00) }, 97static struct resource scif##index##_resources[] = { \
98}; 98 DEFINE_RES_MEM(baseaddr, 0x100), \
99 99 DEFINE_RES_IRQ(irq), \
100static struct platform_device scif0_device = { 100}; \
101 .name = "sh-sci", 101 \
102 .id = 0, 102static struct platform_device scif##index##_device = { \
103 .dev = { 103 .name = "sh-sci", \
104 .platform_data = &scif0_platform_data, 104 .id = index, \
105 }, 105 .resource = scif##index##_resources, \
106}; 106 .num_resources = ARRAY_SIZE(scif##index##_resources), \
107 107 .dev = { \
108/* SCIFA1 */ 108 .platform_data = &scif##index##_platform_data, \
109static struct plat_sci_port scif1_platform_data = { 109 }, \
110 .mapbase = 0xe6c50000, 110}
111 .flags = UPF_BOOT_AUTOCONF,
112 .scscr = SCSCR_RE | SCSCR_TE,
113 .scbrr_algo_id = SCBRR_ALGO_4,
114 .type = PORT_SCIFA,
115 .irqs = { evt2irq(0x0c20), evt2irq(0x0c20),
116 evt2irq(0x0c20), evt2irq(0x0c20) },
117};
118
119static struct platform_device scif1_device = {
120 .name = "sh-sci",
121 .id = 1,
122 .dev = {
123 .platform_data = &scif1_platform_data,
124 },
125};
126
127/* SCIFA2 */
128static struct plat_sci_port scif2_platform_data = {
129 .mapbase = 0xe6c60000,
130 .flags = UPF_BOOT_AUTOCONF,
131 .scscr = SCSCR_RE | SCSCR_TE,
132 .scbrr_algo_id = SCBRR_ALGO_4,
133 .type = PORT_SCIFA,
134 .irqs = { evt2irq(0x0c40), evt2irq(0x0c40),
135 evt2irq(0x0c40), evt2irq(0x0c40) },
136};
137
138static struct platform_device scif2_device = {
139 .name = "sh-sci",
140 .id = 2,
141 .dev = {
142 .platform_data = &scif2_platform_data,
143 },
144};
145
146/* SCIFA3 */
147static struct plat_sci_port scif3_platform_data = {
148 .mapbase = 0xe6c70000,
149 .flags = UPF_BOOT_AUTOCONF,
150 .scscr = SCSCR_RE | SCSCR_TE,
151 .scbrr_algo_id = SCBRR_ALGO_4,
152 .type = PORT_SCIFA,
153 .irqs = { evt2irq(0x0c60), evt2irq(0x0c60),
154 evt2irq(0x0c60), evt2irq(0x0c60) },
155};
156
157static struct platform_device scif3_device = {
158 .name = "sh-sci",
159 .id = 3,
160 .dev = {
161 .platform_data = &scif3_platform_data,
162 },
163};
164
165/* SCIFA4 */
166static struct plat_sci_port scif4_platform_data = {
167 .mapbase = 0xe6c80000,
168 .flags = UPF_BOOT_AUTOCONF,
169 .scscr = SCSCR_RE | SCSCR_TE,
170 .scbrr_algo_id = SCBRR_ALGO_4,
171 .type = PORT_SCIFA,
172 .irqs = { evt2irq(0x0d20), evt2irq(0x0d20),
173 evt2irq(0x0d20), evt2irq(0x0d20) },
174};
175
176static struct platform_device scif4_device = {
177 .name = "sh-sci",
178 .id = 4,
179 .dev = {
180 .platform_data = &scif4_platform_data,
181 },
182};
183
184/* SCIFA5 */
185static struct plat_sci_port scif5_platform_data = {
186 .mapbase = 0xe6cb0000,
187 .flags = UPF_BOOT_AUTOCONF,
188 .scscr = SCSCR_RE | SCSCR_TE,
189 .scbrr_algo_id = SCBRR_ALGO_4,
190 .type = PORT_SCIFA,
191 .irqs = { evt2irq(0x0d40), evt2irq(0x0d40),
192 evt2irq(0x0d40), evt2irq(0x0d40) },
193};
194
195static struct platform_device scif5_device = {
196 .name = "sh-sci",
197 .id = 5,
198 .dev = {
199 .platform_data = &scif5_platform_data,
200 },
201};
202
203/* SCIFB */
204static struct plat_sci_port scif6_platform_data = {
205 .mapbase = 0xe6c30000,
206 .flags = UPF_BOOT_AUTOCONF,
207 .scscr = SCSCR_RE | SCSCR_TE,
208 .scbrr_algo_id = SCBRR_ALGO_4,
209 .type = PORT_SCIFB,
210 .irqs = { evt2irq(0x0d60), evt2irq(0x0d60),
211 evt2irq(0x0d60), evt2irq(0x0d60) },
212};
213 111
214static struct platform_device scif6_device = { 112SH7372_SCIF(PORT_SCIFA, 0, 0xe6c40000, evt2irq(0x0c00));
215 .name = "sh-sci", 113SH7372_SCIF(PORT_SCIFA, 1, 0xe6c50000, evt2irq(0x0c20));
216 .id = 6, 114SH7372_SCIF(PORT_SCIFA, 2, 0xe6c60000, evt2irq(0x0c40));
217 .dev = { 115SH7372_SCIF(PORT_SCIFA, 3, 0xe6c70000, evt2irq(0x0c60));
218 .platform_data = &scif6_platform_data, 116SH7372_SCIF(PORT_SCIFA, 4, 0xe6c80000, evt2irq(0x0d20));
219 }, 117SH7372_SCIF(PORT_SCIFA, 5, 0xe6cb0000, evt2irq(0x0d40));
220}; 118SH7372_SCIF(PORT_SCIFB, 6, 0xe6c30000, evt2irq(0x0d60));
221 119
222/* CMT */ 120/* CMT */
223static struct sh_timer_config cmt2_platform_data = { 121static struct sh_timer_config cmt2_platform_data = {
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index 22de17417fd7..00b348ec48b8 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -71,167 +71,38 @@ void __init sh73a0_pinmux_init(void)
71 ARRAY_SIZE(pfc_resources)); 71 ARRAY_SIZE(pfc_resources));
72} 72}
73 73
74static struct plat_sci_port scif0_platform_data = { 74/* SCIF */
75 .mapbase = 0xe6c40000, 75#define SH73A0_SCIF(scif_type, index, baseaddr, irq) \
76 .flags = UPF_BOOT_AUTOCONF, 76static struct plat_sci_port scif##index##_platform_data = { \
77 .scscr = SCSCR_RE | SCSCR_TE, 77 .type = scif_type, \
78 .scbrr_algo_id = SCBRR_ALGO_4, 78 .flags = UPF_BOOT_AUTOCONF, \
79 .type = PORT_SCIFA, 79 .scscr = SCSCR_RE | SCSCR_TE, \
80 .irqs = { gic_spi(72), gic_spi(72), 80}; \
81 gic_spi(72), gic_spi(72) }, 81 \
82}; 82static struct resource scif##index##_resources[] = { \
83 83 DEFINE_RES_MEM(baseaddr, 0x100), \
84static struct platform_device scif0_device = { 84 DEFINE_RES_IRQ(irq), \
85 .name = "sh-sci", 85}; \
86 .id = 0, 86 \
87 .dev = { 87static struct platform_device scif##index##_device = { \
88 .platform_data = &scif0_platform_data, 88 .name = "sh-sci", \
89 }, 89 .id = index, \
90}; 90 .resource = scif##index##_resources, \
91 91 .num_resources = ARRAY_SIZE(scif##index##_resources), \
92static struct plat_sci_port scif1_platform_data = { 92 .dev = { \
93 .mapbase = 0xe6c50000, 93 .platform_data = &scif##index##_platform_data, \
94 .flags = UPF_BOOT_AUTOCONF, 94 }, \
95 .scscr = SCSCR_RE | SCSCR_TE, 95}
96 .scbrr_algo_id = SCBRR_ALGO_4,
97 .type = PORT_SCIFA,
98 .irqs = { gic_spi(73), gic_spi(73),
99 gic_spi(73), gic_spi(73) },
100};
101
102static struct platform_device scif1_device = {
103 .name = "sh-sci",
104 .id = 1,
105 .dev = {
106 .platform_data = &scif1_platform_data,
107 },
108};
109
110static struct plat_sci_port scif2_platform_data = {
111 .mapbase = 0xe6c60000,
112 .flags = UPF_BOOT_AUTOCONF,
113 .scscr = SCSCR_RE | SCSCR_TE,
114 .scbrr_algo_id = SCBRR_ALGO_4,
115 .type = PORT_SCIFA,
116 .irqs = { gic_spi(74), gic_spi(74),
117 gic_spi(74), gic_spi(74) },
118};
119
120static struct platform_device scif2_device = {
121 .name = "sh-sci",
122 .id = 2,
123 .dev = {
124 .platform_data = &scif2_platform_data,
125 },
126};
127
128static struct plat_sci_port scif3_platform_data = {
129 .mapbase = 0xe6c70000,
130 .flags = UPF_BOOT_AUTOCONF,
131 .scscr = SCSCR_RE | SCSCR_TE,
132 .scbrr_algo_id = SCBRR_ALGO_4,
133 .type = PORT_SCIFA,
134 .irqs = { gic_spi(75), gic_spi(75),
135 gic_spi(75), gic_spi(75) },
136};
137
138static struct platform_device scif3_device = {
139 .name = "sh-sci",
140 .id = 3,
141 .dev = {
142 .platform_data = &scif3_platform_data,
143 },
144};
145
146static struct plat_sci_port scif4_platform_data = {
147 .mapbase = 0xe6c80000,
148 .flags = UPF_BOOT_AUTOCONF,
149 .scscr = SCSCR_RE | SCSCR_TE,
150 .scbrr_algo_id = SCBRR_ALGO_4,
151 .type = PORT_SCIFA,
152 .irqs = { gic_spi(78), gic_spi(78),
153 gic_spi(78), gic_spi(78) },
154};
155
156static struct platform_device scif4_device = {
157 .name = "sh-sci",
158 .id = 4,
159 .dev = {
160 .platform_data = &scif4_platform_data,
161 },
162};
163
164static struct plat_sci_port scif5_platform_data = {
165 .mapbase = 0xe6cb0000,
166 .flags = UPF_BOOT_AUTOCONF,
167 .scscr = SCSCR_RE | SCSCR_TE,
168 .scbrr_algo_id = SCBRR_ALGO_4,
169 .type = PORT_SCIFA,
170 .irqs = { gic_spi(79), gic_spi(79),
171 gic_spi(79), gic_spi(79) },
172};
173
174static struct platform_device scif5_device = {
175 .name = "sh-sci",
176 .id = 5,
177 .dev = {
178 .platform_data = &scif5_platform_data,
179 },
180};
181
182static struct plat_sci_port scif6_platform_data = {
183 .mapbase = 0xe6cc0000,
184 .flags = UPF_BOOT_AUTOCONF,
185 .scscr = SCSCR_RE | SCSCR_TE,
186 .scbrr_algo_id = SCBRR_ALGO_4,
187 .type = PORT_SCIFA,
188 .irqs = { gic_spi(156), gic_spi(156),
189 gic_spi(156), gic_spi(156) },
190};
191
192static struct platform_device scif6_device = {
193 .name = "sh-sci",
194 .id = 6,
195 .dev = {
196 .platform_data = &scif6_platform_data,
197 },
198};
199
200static struct plat_sci_port scif7_platform_data = {
201 .mapbase = 0xe6cd0000,
202 .flags = UPF_BOOT_AUTOCONF,
203 .scscr = SCSCR_RE | SCSCR_TE,
204 .scbrr_algo_id = SCBRR_ALGO_4,
205 .type = PORT_SCIFA,
206 .irqs = { gic_spi(143), gic_spi(143),
207 gic_spi(143), gic_spi(143) },
208};
209
210static struct platform_device scif7_device = {
211 .name = "sh-sci",
212 .id = 7,
213 .dev = {
214 .platform_data = &scif7_platform_data,
215 },
216};
217
218static struct plat_sci_port scif8_platform_data = {
219 .mapbase = 0xe6c30000,
220 .flags = UPF_BOOT_AUTOCONF,
221 .scscr = SCSCR_RE | SCSCR_TE,
222 .scbrr_algo_id = SCBRR_ALGO_4,
223 .type = PORT_SCIFB,
224 .irqs = { gic_spi(80), gic_spi(80),
225 gic_spi(80), gic_spi(80) },
226};
227 96
228static struct platform_device scif8_device = { 97SH73A0_SCIF(PORT_SCIFA, 0, 0xe6c40000, gic_spi(72));
229 .name = "sh-sci", 98SH73A0_SCIF(PORT_SCIFA, 1, 0xe6c50000, gic_spi(73));
230 .id = 8, 99SH73A0_SCIF(PORT_SCIFA, 2, 0xe6c60000, gic_spi(74));
231 .dev = { 100SH73A0_SCIF(PORT_SCIFA, 3, 0xe6c70000, gic_spi(75));
232 .platform_data = &scif8_platform_data, 101SH73A0_SCIF(PORT_SCIFA, 4, 0xe6c80000, gic_spi(78));
233 }, 102SH73A0_SCIF(PORT_SCIFA, 5, 0xe6cb0000, gic_spi(79));
234}; 103SH73A0_SCIF(PORT_SCIFA, 6, 0xe6cc0000, gic_spi(156));
104SH73A0_SCIF(PORT_SCIFA, 7, 0xe6cd0000, gic_spi(143));
105SH73A0_SCIF(PORT_SCIFB, 8, 0xe6c30000, gic_spi(80));
235 106
236static struct sh_timer_config cmt10_platform_data = { 107static struct sh_timer_config cmt10_platform_data = {
237 .name = "CMT10", 108 .name = "CMT10",
diff --git a/drivers/Makefile b/drivers/Makefile
index 3cc8214f9b26..8e3b8b06c0b2 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -118,7 +118,7 @@ obj-$(CONFIG_SGI_SN) += sn/
118obj-y += firmware/ 118obj-y += firmware/
119obj-$(CONFIG_CRYPTO) += crypto/ 119obj-$(CONFIG_CRYPTO) += crypto/
120obj-$(CONFIG_SUPERH) += sh/ 120obj-$(CONFIG_SUPERH) += sh/
121obj-$(CONFIG_ARCH_SHMOBILE) += sh/ 121obj-$(CONFIG_ARCH_SHMOBILE_LEGACY) += sh/
122ifndef CONFIG_ARCH_USES_GETTIMEOFFSET 122ifndef CONFIG_ARCH_USES_GETTIMEOFFSET
123obj-y += clocksource/ 123obj-y += clocksource/
124endif 124endif
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index e4bf0e435af6..be33d2b0613b 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -39,6 +39,7 @@
39#include <linux/module.h> 39#include <linux/module.h>
40#include <linux/mm.h> 40#include <linux/mm.h>
41#include <linux/notifier.h> 41#include <linux/notifier.h>
42#include <linux/of.h>
42#include <linux/platform_device.h> 43#include <linux/platform_device.h>
43#include <linux/pm_runtime.h> 44#include <linux/pm_runtime.h>
44#include <linux/scatterlist.h> 45#include <linux/scatterlist.h>
@@ -58,6 +59,23 @@
58 59
59#include "sh-sci.h" 60#include "sh-sci.h"
60 61
62/* Offsets into the sci_port->irqs array */
63enum {
64 SCIx_ERI_IRQ,
65 SCIx_RXI_IRQ,
66 SCIx_TXI_IRQ,
67 SCIx_BRI_IRQ,
68 SCIx_NR_IRQS,
69
70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
71};
72
73#define SCIx_IRQ_IS_MUXED(port) \
74 ((port)->irqs[SCIx_ERI_IRQ] == \
75 (port)->irqs[SCIx_RXI_IRQ]) || \
76 ((port)->irqs[SCIx_ERI_IRQ] && \
77 ((port)->irqs[SCIx_RXI_IRQ] < 0))
78
61struct sci_port { 79struct sci_port {
62 struct uart_port port; 80 struct uart_port port;
63 81
@@ -1757,17 +1775,6 @@ static unsigned int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
1757 if (s->sampling_rate) 1775 if (s->sampling_rate)
1758 return DIV_ROUND_CLOSEST(freq, s->sampling_rate * bps) - 1; 1776 return DIV_ROUND_CLOSEST(freq, s->sampling_rate * bps) - 1;
1759 1777
1760 switch (s->cfg->scbrr_algo_id) {
1761 case SCBRR_ALGO_1:
1762 return freq / (16 * bps);
1763 case SCBRR_ALGO_2:
1764 return DIV_ROUND_CLOSEST(freq, 32 * bps) - 1;
1765 case SCBRR_ALGO_3:
1766 return freq / (8 * bps);
1767 case SCBRR_ALGO_4:
1768 return DIV_ROUND_CLOSEST(freq, 16 * bps) - 1;
1769 }
1770
1771 /* Warn, but use a safe default */ 1778 /* Warn, but use a safe default */
1772 WARN_ON(1); 1779 WARN_ON(1);
1773 1780
@@ -2105,36 +2112,27 @@ static int sci_init_single(struct platform_device *dev,
2105 port->iotype = UPIO_MEM; 2112 port->iotype = UPIO_MEM;
2106 port->line = index; 2113 port->line = index;
2107 2114
2108 if (dev->num_resources) { 2115 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2109 /* Device has resources, use them. */ 2116 if (res == NULL)
2110 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 2117 return -ENOMEM;
2111 if (res == NULL)
2112 return -ENOMEM;
2113 2118
2114 port->mapbase = res->start; 2119 port->mapbase = res->start;
2115 2120
2116 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) 2121 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2117 sci_port->irqs[i] = platform_get_irq(dev, i); 2122 sci_port->irqs[i] = platform_get_irq(dev, i);
2118 2123
2119 /* The SCI generates several interrupts. They can be muxed 2124 /* The SCI generates several interrupts. They can be muxed together or
2120 * together or connected to different interrupt lines. In the 2125 * connected to different interrupt lines. In the muxed case only one
2121 * muxed case only one interrupt resource is specified. In the 2126 * interrupt resource is specified. In the non-muxed case three or four
2122 * non-muxed case three or four interrupt resources are 2127 * interrupt resources are specified, as the BRI interrupt is optional.
2123 * specified, as the BRI interrupt is optional. 2128 */
2124 */ 2129 if (sci_port->irqs[0] < 0)
2125 if (sci_port->irqs[0] < 0) 2130 return -ENXIO;
2126 return -ENXIO;
2127 2131
2128 if (sci_port->irqs[1] < 0) { 2132 if (sci_port->irqs[1] < 0) {
2129 sci_port->irqs[1] = sci_port->irqs[0]; 2133 sci_port->irqs[1] = sci_port->irqs[0];
2130 sci_port->irqs[2] = sci_port->irqs[0]; 2134 sci_port->irqs[2] = sci_port->irqs[0];
2131 sci_port->irqs[3] = sci_port->irqs[0]; 2135 sci_port->irqs[3] = sci_port->irqs[0];
2132 }
2133 } else {
2134 /* No resources, use old-style platform data. */
2135 port->mapbase = p->mapbase;
2136 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2137 sci_port->irqs[i] = p->irqs[i] ? p->irqs[i] : -ENXIO;
2138 } 2136 }
2139 2137
2140 if (p->regtype == SCIx_PROBE_REGTYPE) { 2138 if (p->regtype == SCIx_PROBE_REGTYPE) {
@@ -2176,17 +2174,12 @@ static int sci_init_single(struct platform_device *dev,
2176 break; 2174 break;
2177 } 2175 }
2178 2176
2179 /* Set the sampling rate if the baud rate calculation algorithm isn't 2177 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2180 * specified. 2178 * match the SoC datasheet, this should be investigated. Let platform
2179 * data override the sampling rate for now.
2181 */ 2180 */
2182 if (p->scbrr_algo_id == SCBRR_ALGO_NONE) { 2181 sci_port->sampling_rate = p->sampling_rate ? p->sampling_rate
2183 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that 2182 : sampling_rate;
2184 * doesn't match the SoC datasheet, this should be investigated.
2185 * Let platform data override the sampling rate for now.
2186 */
2187 sci_port->sampling_rate = p->sampling_rate ? p->sampling_rate
2188 : sampling_rate;
2189 }
2190 2183
2191 if (!early) { 2184 if (!early) {
2192 sci_port->iclk = clk_get(&dev->dev, "sci_ick"); 2185 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
@@ -2423,6 +2416,83 @@ static int sci_remove(struct platform_device *dev)
2423 return 0; 2416 return 0;
2424} 2417}
2425 2418
2419struct sci_port_info {
2420 unsigned int type;
2421 unsigned int regtype;
2422};
2423
2424static const struct of_device_id of_sci_match[] = {
2425 {
2426 .compatible = "renesas,scif",
2427 .data = (void *)&(const struct sci_port_info) {
2428 .type = PORT_SCIF,
2429 .regtype = SCIx_SH4_SCIF_REGTYPE,
2430 },
2431 }, {
2432 .compatible = "renesas,scifa",
2433 .data = (void *)&(const struct sci_port_info) {
2434 .type = PORT_SCIFA,
2435 .regtype = SCIx_SCIFA_REGTYPE,
2436 },
2437 }, {
2438 .compatible = "renesas,scifb",
2439 .data = (void *)&(const struct sci_port_info) {
2440 .type = PORT_SCIFB,
2441 .regtype = SCIx_SCIFB_REGTYPE,
2442 },
2443 }, {
2444 .compatible = "renesas,hscif",
2445 .data = (void *)&(const struct sci_port_info) {
2446 .type = PORT_HSCIF,
2447 .regtype = SCIx_HSCIF_REGTYPE,
2448 },
2449 }, {
2450 /* Terminator */
2451 },
2452};
2453MODULE_DEVICE_TABLE(of, of_sci_match);
2454
2455static struct plat_sci_port *
2456sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id)
2457{
2458 struct device_node *np = pdev->dev.of_node;
2459 const struct of_device_id *match;
2460 const struct sci_port_info *info;
2461 struct plat_sci_port *p;
2462 int id;
2463
2464 if (!IS_ENABLED(CONFIG_OF) || !np)
2465 return NULL;
2466
2467 match = of_match_node(of_sci_match, pdev->dev.of_node);
2468 if (!match)
2469 return NULL;
2470
2471 info = match->data;
2472
2473 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
2474 if (!p) {
2475 dev_err(&pdev->dev, "failed to allocate DT config data\n");
2476 return NULL;
2477 }
2478
2479 /* Get the line number for the aliases node. */
2480 id = of_alias_get_id(np, "serial");
2481 if (id < 0) {
2482 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
2483 return NULL;
2484 }
2485
2486 *dev_id = id;
2487
2488 p->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
2489 p->type = info->type;
2490 p->regtype = info->regtype;
2491 p->scscr = SCSCR_RE | SCSCR_TE;
2492
2493 return p;
2494}
2495
2426static int sci_probe_single(struct platform_device *dev, 2496static int sci_probe_single(struct platform_device *dev,
2427 unsigned int index, 2497 unsigned int index,
2428 struct plat_sci_port *p, 2498 struct plat_sci_port *p,
@@ -2455,8 +2525,9 @@ static int sci_probe_single(struct platform_device *dev,
2455 2525
2456static int sci_probe(struct platform_device *dev) 2526static int sci_probe(struct platform_device *dev)
2457{ 2527{
2458 struct plat_sci_port *p = dev_get_platdata(&dev->dev); 2528 struct plat_sci_port *p;
2459 struct sci_port *sp = &sci_ports[dev->id]; 2529 struct sci_port *sp;
2530 unsigned int dev_id;
2460 int ret; 2531 int ret;
2461 2532
2462 /* 2533 /*
@@ -2467,9 +2538,24 @@ static int sci_probe(struct platform_device *dev)
2467 if (is_early_platform_device(dev)) 2538 if (is_early_platform_device(dev))
2468 return sci_probe_earlyprintk(dev); 2539 return sci_probe_earlyprintk(dev);
2469 2540
2541 if (dev->dev.of_node) {
2542 p = sci_parse_dt(dev, &dev_id);
2543 if (p == NULL)
2544 return -EINVAL;
2545 } else {
2546 p = dev->dev.platform_data;
2547 if (p == NULL) {
2548 dev_err(&dev->dev, "no platform data supplied\n");
2549 return -EINVAL;
2550 }
2551
2552 dev_id = dev->id;
2553 }
2554
2555 sp = &sci_ports[dev_id];
2470 platform_set_drvdata(dev, sp); 2556 platform_set_drvdata(dev, sp);
2471 2557
2472 ret = sci_probe_single(dev, dev->id, p, sp); 2558 ret = sci_probe_single(dev, dev_id, p, sp);
2473 if (ret) 2559 if (ret)
2474 return ret; 2560 return ret;
2475 2561
@@ -2521,6 +2607,7 @@ static struct platform_driver sci_driver = {
2521 .name = "sh-sci", 2607 .name = "sh-sci",
2522 .owner = THIS_MODULE, 2608 .owner = THIS_MODULE,
2523 .pm = &sci_dev_pm_ops, 2609 .pm = &sci_dev_pm_ops,
2610 .of_match_table = of_match_ptr(of_sci_match),
2524 }, 2611 },
2525}; 2612};
2526 2613
diff --git a/include/dt-bindings/clock/r8a7790-clock.h b/include/dt-bindings/clock/r8a7790-clock.h
new file mode 100644
index 000000000000..420f0b00ae1e
--- /dev/null
+++ b/include/dt-bindings/clock/r8a7790-clock.h
@@ -0,0 +1,100 @@
1/*
2 * Copyright 2013 Ideas On Board SPRL
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10#ifndef __DT_BINDINGS_CLOCK_R8A7790_H__
11#define __DT_BINDINGS_CLOCK_R8A7790_H__
12
13/* CPG */
14#define R8A7790_CLK_MAIN 0
15#define R8A7790_CLK_PLL0 1
16#define R8A7790_CLK_PLL1 2
17#define R8A7790_CLK_PLL3 3
18#define R8A7790_CLK_LB 4
19#define R8A7790_CLK_QSPI 5
20#define R8A7790_CLK_SDH 6
21#define R8A7790_CLK_SD0 7
22#define R8A7790_CLK_SD1 8
23#define R8A7790_CLK_Z 9
24
25/* MSTP1 */
26#define R8A7790_CLK_TMU1 11
27#define R8A7790_CLK_TMU3 21
28#define R8A7790_CLK_TMU2 22
29#define R8A7790_CLK_CMT0 24
30#define R8A7790_CLK_TMU0 25
31#define R8A7790_CLK_VSP1_DU1 27
32#define R8A7790_CLK_VSP1_DU0 28
33#define R8A7790_CLK_VSP1_RT 30
34#define R8A7790_CLK_VSP1_SY 31
35
36/* MSTP2 */
37#define R8A7790_CLK_SCIFA2 2
38#define R8A7790_CLK_SCIFA1 3
39#define R8A7790_CLK_SCIFA0 4
40#define R8A7790_CLK_SCIFB0 6
41#define R8A7790_CLK_SCIFB1 7
42#define R8A7790_CLK_SCIFB2 16
43#define R8A7790_CLK_SYS_DMAC0 18
44#define R8A7790_CLK_SYS_DMAC1 19
45
46/* MSTP3 */
47#define R8A7790_CLK_TPU0 4
48#define R8A7790_CLK_MMCIF1 5
49#define R8A7790_CLK_SDHI3 11
50#define R8A7790_CLK_SDHI2 12
51#define R8A7790_CLK_SDHI1 13
52#define R8A7790_CLK_SDHI0 14
53#define R8A7790_CLK_MMCIF0 15
54#define R8A7790_CLK_SSUSB 28
55#define R8A7790_CLK_CMT1 29
56#define R8A7790_CLK_USBDMAC0 30
57#define R8A7790_CLK_USBDMAC1 31
58
59/* MSTP5 */
60#define R8A7790_CLK_THERMAL 22
61#define R8A7790_CLK_PWM 23
62
63/* MSTP7 */
64#define R8A7790_CLK_EHCI 3
65#define R8A7790_CLK_HSUSB 4
66#define R8A7790_CLK_HSCIF1 16
67#define R8A7790_CLK_HSCIF0 17
68#define R8A7790_CLK_SCIF1 20
69#define R8A7790_CLK_SCIF0 21
70#define R8A7790_CLK_DU2 22
71#define R8A7790_CLK_DU1 23
72#define R8A7790_CLK_DU0 24
73#define R8A7790_CLK_LVDS1 25
74#define R8A7790_CLK_LVDS0 26
75
76/* MSTP8 */
77#define R8A7790_CLK_VIN3 8
78#define R8A7790_CLK_VIN2 9
79#define R8A7790_CLK_VIN1 10
80#define R8A7790_CLK_VIN0 11
81#define R8A7790_CLK_ETHER 13
82#define R8A7790_CLK_SATA1 14
83#define R8A7790_CLK_SATA0 15
84
85/* MSTP9 */
86#define R8A7790_CLK_GPIO5 7
87#define R8A7790_CLK_GPIO4 8
88#define R8A7790_CLK_GPIO3 9
89#define R8A7790_CLK_GPIO2 10
90#define R8A7790_CLK_GPIO1 11
91#define R8A7790_CLK_GPIO0 12
92#define R8A7790_CLK_RCAN1 15
93#define R8A7790_CLK_RCAN0 16
94#define R8A7790_CLK_IICDVFS 26
95#define R8A7790_CLK_I2C3 28
96#define R8A7790_CLK_I2C2 29
97#define R8A7790_CLK_I2C1 30
98#define R8A7790_CLK_I2C0 31
99
100#endif /* __DT_BINDINGS_CLOCK_R8A7790_H__ */
diff --git a/include/dt-bindings/clock/r8a7791-clock.h b/include/dt-bindings/clock/r8a7791-clock.h
new file mode 100644
index 000000000000..df1715b77f96
--- /dev/null
+++ b/include/dt-bindings/clock/r8a7791-clock.h
@@ -0,0 +1,105 @@
1/*
2 * Copyright 2013 Ideas On Board SPRL
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10#ifndef __DT_BINDINGS_CLOCK_R8A7791_H__
11#define __DT_BINDINGS_CLOCK_R8A7791_H__
12
13/* CPG */
14#define R8A7791_CLK_MAIN 0
15#define R8A7791_CLK_PLL0 1
16#define R8A7791_CLK_PLL1 2
17#define R8A7791_CLK_PLL3 3
18#define R8A7791_CLK_LB 4
19#define R8A7791_CLK_QSPI 5
20#define R8A7791_CLK_SDH 6
21#define R8A7791_CLK_SD0 7
22#define R8A7791_CLK_Z 8
23
24/* MSTP1 */
25#define R8A7791_CLK_TMU1 11
26#define R8A7791_CLK_TMU3 21
27#define R8A7791_CLK_TMU2 22
28#define R8A7791_CLK_CMT0 24
29#define R8A7791_CLK_TMU0 25
30#define R8A7791_CLK_VSP1_DU1 27
31#define R8A7791_CLK_VSP1_DU0 28
32#define R8A7791_CLK_VSP1_SY 31
33
34/* MSTP2 */
35#define R8A7791_CLK_SCIFA2 2
36#define R8A7791_CLK_SCIFA1 3
37#define R8A7791_CLK_SCIFA0 4
38#define R8A7791_CLK_SCIFB0 6
39#define R8A7791_CLK_SCIFB1 7
40#define R8A7791_CLK_SCIFB2 16
41#define R8A7791_CLK_DMAC 18
42
43/* MSTP3 */
44#define R8A7791_CLK_TPU0 4
45#define R8A7791_CLK_SDHI2 11
46#define R8A7791_CLK_SDHI1 12
47#define R8A7791_CLK_SDHI0 14
48#define R8A7791_CLK_MMCIF0 15
49#define R8A7791_CLK_SSUSB 28
50#define R8A7791_CLK_CMT1 29
51#define R8A7791_CLK_USBDMAC0 30
52#define R8A7791_CLK_USBDMAC1 31
53
54/* MSTP5 */
55#define R8A7791_CLK_THERMAL 22
56#define R8A7791_CLK_PWM 23
57
58/* MSTP7 */
59#define R8A7791_CLK_HSUSB 4
60#define R8A7791_CLK_HSCIF2 13
61#define R8A7791_CLK_SCIF5 14
62#define R8A7791_CLK_SCIF4 15
63#define R8A7791_CLK_HSCIF1 16
64#define R8A7791_CLK_HSCIF0 17
65#define R8A7791_CLK_SCIF3 18
66#define R8A7791_CLK_SCIF2 19
67#define R8A7791_CLK_SCIF1 20
68#define R8A7791_CLK_SCIF0 21
69#define R8A7791_CLK_DU1 23
70#define R8A7791_CLK_DU0 24
71#define R8A7791_CLK_LVDS0 26
72
73/* MSTP8 */
74#define R8A7791_CLK_VIN2 9
75#define R8A7791_CLK_VIN1 10
76#define R8A7791_CLK_VIN0 11
77#define R8A7791_CLK_ETHER 13
78#define R8A7791_CLK_SATA1 14
79#define R8A7791_CLK_SATA0 15
80
81/* MSTP9 */
82#define R8A7791_CLK_GPIO7 4
83#define R8A7791_CLK_GPIO6 5
84#define R8A7791_CLK_GPIO5 7
85#define R8A7791_CLK_GPIO4 8
86#define R8A7791_CLK_GPIO3 9
87#define R8A7791_CLK_GPIO2 10
88#define R8A7791_CLK_GPIO1 11
89#define R8A7791_CLK_GPIO0 12
90#define R8A7791_CLK_RCAN1 15
91#define R8A7791_CLK_RCAN0 16
92#define R8A7791_CLK_I2C5 25
93#define R8A7791_CLK_IICDVFS 26
94#define R8A7791_CLK_I2C4 27
95#define R8A7791_CLK_I2C3 28
96#define R8A7791_CLK_I2C2 29
97#define R8A7791_CLK_I2C1 30
98#define R8A7791_CLK_I2C0 31
99
100/* MSTP11 */
101#define R8A7791_CLK_SCIFA3 6
102#define R8A7791_CLK_SCIFA4 7
103#define R8A7791_CLK_SCIFA5 8
104
105#endif /* __DT_BINDINGS_CLOCK_R8A7791_H__ */
diff --git a/include/linux/serial_sci.h b/include/linux/serial_sci.h
index af414e1895a5..22b3640c9424 100644
--- a/include/linux/serial_sci.h
+++ b/include/linux/serial_sci.h
@@ -10,15 +10,6 @@
10 10
11#define SCIx_NOT_SUPPORTED (-1) 11#define SCIx_NOT_SUPPORTED (-1)
12 12
13enum {
14 SCBRR_ALGO_NONE, /* Compute sampling rate in the driver */
15 SCBRR_ALGO_1, /* clk / (16 * bps) */
16 SCBRR_ALGO_2, /* DIV_ROUND_CLOSEST(clk, 32 * bps) - 1 */
17 SCBRR_ALGO_3, /* clk / (8 * bps) */
18 SCBRR_ALGO_4, /* DIV_ROUND_CLOSEST(clk, 16 * bps) - 1 */
19 SCBRR_ALGO_6, /* HSCIF variable sample rate algorithm */
20};
21
22#define SCSCR_TIE (1 << 7) 13#define SCSCR_TIE (1 << 7)
23#define SCSCR_RIE (1 << 6) 14#define SCSCR_RIE (1 << 6)
24#define SCSCR_TE (1 << 5) 15#define SCSCR_TE (1 << 5)
@@ -59,17 +50,6 @@ enum {
59/* HSSRR HSCIF */ 50/* HSSRR HSCIF */
60#define HSCIF_SRE 0x8000 51#define HSCIF_SRE 0x8000
61 52
62/* Offsets into the sci_port->irqs array */
63enum {
64 SCIx_ERI_IRQ,
65 SCIx_RXI_IRQ,
66 SCIx_TXI_IRQ,
67 SCIx_BRI_IRQ,
68 SCIx_NR_IRQS,
69
70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
71};
72
73enum { 53enum {
74 SCIx_PROBE_REGTYPE, 54 SCIx_PROBE_REGTYPE,
75 55
@@ -88,19 +68,6 @@ enum {
88 SCIx_NR_REGTYPES, 68 SCIx_NR_REGTYPES,
89}; 69};
90 70
91#define SCIx_IRQ_MUXED(irq) \
92{ \
93 [SCIx_ERI_IRQ] = (irq), \
94 [SCIx_RXI_IRQ] = (irq), \
95 [SCIx_TXI_IRQ] = (irq), \
96 [SCIx_BRI_IRQ] = (irq), \
97}
98
99#define SCIx_IRQ_IS_MUXED(port) \
100 ((port)->irqs[SCIx_ERI_IRQ] == \
101 (port)->irqs[SCIx_RXI_IRQ]) || \
102 ((port)->irqs[SCIx_ERI_IRQ] && \
103 ((port)->irqs[SCIx_RXI_IRQ] < 0))
104/* 71/*
105 * SCI register subset common for all port types. 72 * SCI register subset common for all port types.
106 * Not all registers will exist on all parts. 73 * Not all registers will exist on all parts.
@@ -129,14 +96,11 @@ struct plat_sci_port_ops {
129 * Platform device specific platform_data struct 96 * Platform device specific platform_data struct
130 */ 97 */
131struct plat_sci_port { 98struct plat_sci_port {
132 unsigned long mapbase; /* resource base */
133 unsigned int irqs[SCIx_NR_IRQS]; /* ERI, RXI, TXI, BRI */
134 unsigned int type; /* SCI / SCIF / IRDA / HSCIF */ 99 unsigned int type; /* SCI / SCIF / IRDA / HSCIF */
135 upf_t flags; /* UPF_* flags */ 100 upf_t flags; /* UPF_* flags */
136 unsigned long capabilities; /* Port features/capabilities */ 101 unsigned long capabilities; /* Port features/capabilities */
137 102
138 unsigned int sampling_rate; 103 unsigned int sampling_rate;
139 unsigned int scbrr_algo_id; /* SCBRR calculation algo */
140 unsigned int scscr; /* SCSCR initialization */ 104 unsigned int scscr; /* SCSCR initialization */
141 105
142 /* 106 /*
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-30 14:40:58 -0500