diff options
| -rw-r--r-- | arch/tile/include/asm/cache.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/tile/include/asm/cache.h b/arch/tile/include/asm/cache.h index ee597147e5cd..869a14f4ceae 100644 --- a/arch/tile/include/asm/cache.h +++ b/arch/tile/include/asm/cache.h | |||
| @@ -31,6 +31,14 @@ | |||
| 31 | #define L2_CACHE_BYTES (1 << L2_CACHE_SHIFT) | 31 | #define L2_CACHE_BYTES (1 << L2_CACHE_SHIFT) |
| 32 | #define L2_CACHE_ALIGN(x) (((x)+(L2_CACHE_BYTES-1)) & -L2_CACHE_BYTES) | 32 | #define L2_CACHE_ALIGN(x) (((x)+(L2_CACHE_BYTES-1)) & -L2_CACHE_BYTES) |
| 33 | 33 | ||
| 34 | /* | ||
| 35 | * TILE-Gx is fully coherents so we don't need to define | ||
| 36 | * ARCH_KMALLOC_MINALIGN. | ||
| 37 | */ | ||
| 38 | #ifndef __tilegx__ | ||
| 39 | #define ARCH_KMALLOC_MINALIGN L2_CACHE_BYTES | ||
| 40 | #endif | ||
| 41 | |||
| 34 | /* use the cache line size for the L2, which is where it counts */ | 42 | /* use the cache line size for the L2, which is where it counts */ |
| 35 | #define SMP_CACHE_BYTES_SHIFT L2_CACHE_SHIFT | 43 | #define SMP_CACHE_BYTES_SHIFT L2_CACHE_SHIFT |
| 36 | #define SMP_CACHE_BYTES L2_CACHE_BYTES | 44 | #define SMP_CACHE_BYTES L2_CACHE_BYTES |
