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-rw-r--r--MAINTAINERS1
-rw-r--r--arch/arm/plat-omap/i2c.c39
-rw-r--r--drivers/i2c/busses/i2c-bfin-twi.c168
-rw-r--r--drivers/i2c/busses/i2c-cpm.c2
-rw-r--r--drivers/i2c/busses/i2c-highlander.c5
-rw-r--r--drivers/i2c/busses/i2c-ibm_iic.c14
-rw-r--r--drivers/i2c/busses/i2c-mpc.c6
-rw-r--r--drivers/i2c/busses/i2c-nomadik.c6
-rw-r--r--drivers/i2c/busses/i2c-omap.c265
-rw-r--r--drivers/i2c/busses/i2c-pxa.c26
-rw-r--r--drivers/i2c/busses/i2c-s3c2410.c19
-rw-r--r--include/linux/i2c-omap.h9
12 files changed, 374 insertions, 186 deletions
diff --git a/MAINTAINERS b/MAINTAINERS
index f860e2ec1b71..24490426750d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2747,6 +2747,7 @@ M: "Ben Dooks (embedded platforms)" <ben-linux@fluff.org>
2747L: linux-i2c@vger.kernel.org 2747L: linux-i2c@vger.kernel.org
2748W: http://i2c.wiki.kernel.org/ 2748W: http://i2c.wiki.kernel.org/
2749T: quilt kernel.org/pub/linux/kernel/people/jdelvare/linux-2.6/jdelvare-i2c/ 2749T: quilt kernel.org/pub/linux/kernel/people/jdelvare/linux-2.6/jdelvare-i2c/
2750T: git git://git.fluff.org/bjdooks/linux.git
2750S: Maintained 2751S: Maintained
2751F: Documentation/i2c/ 2752F: Documentation/i2c/
2752F: drivers/i2c/ 2753F: drivers/i2c/
diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c
index 624e26298faa..f044b5927508 100644
--- a/arch/arm/plat-omap/i2c.c
+++ b/arch/arm/plat-omap/i2c.c
@@ -26,9 +26,12 @@
26#include <linux/kernel.h> 26#include <linux/kernel.h>
27#include <linux/platform_device.h> 27#include <linux/platform_device.h>
28#include <linux/i2c.h> 28#include <linux/i2c.h>
29#include <linux/i2c-omap.h>
30
29#include <mach/irqs.h> 31#include <mach/irqs.h>
30#include <plat/mux.h> 32#include <plat/mux.h>
31#include <plat/i2c.h> 33#include <plat/i2c.h>
34#include <plat/omap-pm.h>
32 35
33#define OMAP_I2C_SIZE 0x3f 36#define OMAP_I2C_SIZE 0x3f
34#define OMAP1_I2C_BASE 0xfffb3800 37#define OMAP1_I2C_BASE 0xfffb3800
@@ -70,14 +73,14 @@ static struct resource i2c_resources[][2] = {
70 }, \ 73 }, \
71 } 74 }
72 75
73static u32 i2c_rate[ARRAY_SIZE(i2c_resources)]; 76static struct omap_i2c_bus_platform_data i2c_pdata[ARRAY_SIZE(i2c_resources)];
74static struct platform_device omap_i2c_devices[] = { 77static struct platform_device omap_i2c_devices[] = {
75 I2C_DEV_BUILDER(1, i2c_resources[0], &i2c_rate[0]), 78 I2C_DEV_BUILDER(1, i2c_resources[0], &i2c_pdata[0]),
76#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) 79#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
77 I2C_DEV_BUILDER(2, i2c_resources[1], &i2c_rate[1]), 80 I2C_DEV_BUILDER(2, i2c_resources[1], &i2c_pdata[1]),
78#endif 81#endif
79#if defined(CONFIG_ARCH_OMAP3) 82#if defined(CONFIG_ARCH_OMAP3)
80 I2C_DEV_BUILDER(3, i2c_resources[2], &i2c_rate[2]), 83 I2C_DEV_BUILDER(3, i2c_resources[2], &i2c_pdata[2]),
81#endif 84#endif
82}; 85};
83 86
@@ -100,10 +103,12 @@ static int __init omap_i2c_nr_ports(void)
100static int __init omap_i2c_add_bus(int bus_id) 103static int __init omap_i2c_add_bus(int bus_id)
101{ 104{
102 struct platform_device *pdev; 105 struct platform_device *pdev;
106 struct omap_i2c_bus_platform_data *pd;
103 struct resource *res; 107 struct resource *res;
104 resource_size_t base, irq; 108 resource_size_t base, irq;
105 109
106 pdev = &omap_i2c_devices[bus_id - 1]; 110 pdev = &omap_i2c_devices[bus_id - 1];
111 pd = pdev->dev.platform_data;
107 if (bus_id == 1) { 112 if (bus_id == 1) {
108 res = pdev->resource; 113 res = pdev->resource;
109 if (cpu_class_is_omap1()) { 114 if (cpu_class_is_omap1()) {
@@ -123,6 +128,15 @@ static int __init omap_i2c_add_bus(int bus_id)
123 if (cpu_class_is_omap2()) 128 if (cpu_class_is_omap2())
124 omap2_i2c_mux_pins(bus_id); 129 omap2_i2c_mux_pins(bus_id);
125 130
131 /*
132 * When waiting for completion of a i2c transfer, we need to
133 * set a wake up latency constraint for the MPU. This is to
134 * ensure quick enough wakeup from idle, when transfer
135 * completes.
136 */
137 if (cpu_is_omap34xx())
138 pd->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat;
139
126 return platform_device_register(pdev); 140 return platform_device_register(pdev);
127} 141}
128 142
@@ -146,8 +160,8 @@ static int __init omap_i2c_bus_setup(char *str)
146 get_options(str, 3, ints); 160 get_options(str, 3, ints);
147 if (ints[0] < 2 || ints[1] < 1 || ints[1] > ports) 161 if (ints[0] < 2 || ints[1] < 1 || ints[1] > ports)
148 return 0; 162 return 0;
149 i2c_rate[ints[1] - 1] = ints[2]; 163 i2c_pdata[ints[1] - 1].clkrate = ints[2];
150 i2c_rate[ints[1] - 1] |= OMAP_I2C_CMDLINE_SETUP; 164 i2c_pdata[ints[1] - 1].clkrate |= OMAP_I2C_CMDLINE_SETUP;
151 165
152 return 1; 166 return 1;
153} 167}
@@ -161,9 +175,9 @@ static int __init omap_register_i2c_bus_cmdline(void)
161{ 175{
162 int i, err = 0; 176 int i, err = 0;
163 177
164 for (i = 0; i < ARRAY_SIZE(i2c_rate); i++) 178 for (i = 0; i < ARRAY_SIZE(i2c_pdata); i++)
165 if (i2c_rate[i] & OMAP_I2C_CMDLINE_SETUP) { 179 if (i2c_pdata[i].clkrate & OMAP_I2C_CMDLINE_SETUP) {
166 i2c_rate[i] &= ~OMAP_I2C_CMDLINE_SETUP; 180 i2c_pdata[i].clkrate &= ~OMAP_I2C_CMDLINE_SETUP;
167 err = omap_i2c_add_bus(i + 1); 181 err = omap_i2c_add_bus(i + 1);
168 if (err) 182 if (err)
169 goto out; 183 goto out;
@@ -197,9 +211,10 @@ int __init omap_register_i2c_bus(int bus_id, u32 clkrate,
197 return err; 211 return err;
198 } 212 }
199 213
200 if (!i2c_rate[bus_id - 1]) 214 if (!i2c_pdata[bus_id - 1].clkrate)
201 i2c_rate[bus_id - 1] = clkrate; 215 i2c_pdata[bus_id - 1].clkrate = clkrate;
202 i2c_rate[bus_id - 1] &= ~OMAP_I2C_CMDLINE_SETUP; 216
217 i2c_pdata[bus_id - 1].clkrate &= ~OMAP_I2C_CMDLINE_SETUP;
203 218
204 return omap_i2c_add_bus(bus_id); 219 return omap_i2c_add_bus(bus_id);
205} 220}
diff --git a/drivers/i2c/busses/i2c-bfin-twi.c b/drivers/i2c/busses/i2c-bfin-twi.c
index f1e14dd590c9..fb26e5c67515 100644
--- a/drivers/i2c/busses/i2c-bfin-twi.c
+++ b/drivers/i2c/busses/i2c-bfin-twi.c
@@ -25,8 +25,6 @@
25#include <asm/portmux.h> 25#include <asm/portmux.h>
26#include <asm/irq.h> 26#include <asm/irq.h>
27 27
28#define POLL_TIMEOUT (2 * HZ)
29
30/* SMBus mode*/ 28/* SMBus mode*/
31#define TWI_I2C_MODE_STANDARD 1 29#define TWI_I2C_MODE_STANDARD 1
32#define TWI_I2C_MODE_STANDARDSUB 2 30#define TWI_I2C_MODE_STANDARDSUB 2
@@ -44,8 +42,6 @@ struct bfin_twi_iface {
44 int cur_mode; 42 int cur_mode;
45 int manual_stop; 43 int manual_stop;
46 int result; 44 int result;
47 int timeout_count;
48 struct timer_list timeout_timer;
49 struct i2c_adapter adap; 45 struct i2c_adapter adap;
50 struct completion complete; 46 struct completion complete;
51 struct i2c_msg *pmsg; 47 struct i2c_msg *pmsg;
@@ -85,14 +81,15 @@ static const u16 pin_req[2][3] = {
85 {P_TWI1_SCL, P_TWI1_SDA, 0}, 81 {P_TWI1_SCL, P_TWI1_SDA, 0},
86}; 82};
87 83
88static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface) 84static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface,
85 unsigned short twi_int_status)
89{ 86{
90 unsigned short twi_int_status = read_INT_STAT(iface);
91 unsigned short mast_stat = read_MASTER_STAT(iface); 87 unsigned short mast_stat = read_MASTER_STAT(iface);
92 88
93 if (twi_int_status & XMTSERV) { 89 if (twi_int_status & XMTSERV) {
94 /* Transmit next data */ 90 /* Transmit next data */
95 if (iface->writeNum > 0) { 91 if (iface->writeNum > 0) {
92 SSYNC();
96 write_XMT_DATA8(iface, *(iface->transPtr++)); 93 write_XMT_DATA8(iface, *(iface->transPtr++));
97 iface->writeNum--; 94 iface->writeNum--;
98 } 95 }
@@ -114,10 +111,6 @@ static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface)
114 write_MASTER_CTL(iface, 111 write_MASTER_CTL(iface,
115 (read_MASTER_CTL(iface) | RSTART) & ~MDIR); 112 (read_MASTER_CTL(iface) | RSTART) & ~MDIR);
116 } 113 }
117 SSYNC();
118 /* Clear status */
119 write_INT_STAT(iface, XMTSERV);
120 SSYNC();
121 } 114 }
122 if (twi_int_status & RCVSERV) { 115 if (twi_int_status & RCVSERV) {
123 if (iface->readNum > 0) { 116 if (iface->readNum > 0) {
@@ -139,7 +132,6 @@ static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface)
139 } else if (iface->manual_stop) { 132 } else if (iface->manual_stop) {
140 write_MASTER_CTL(iface, 133 write_MASTER_CTL(iface,
141 read_MASTER_CTL(iface) | STOP); 134 read_MASTER_CTL(iface) | STOP);
142 SSYNC();
143 } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT && 135 } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
144 iface->cur_msg + 1 < iface->msg_num) { 136 iface->cur_msg + 1 < iface->msg_num) {
145 if (iface->pmsg[iface->cur_msg + 1].flags & I2C_M_RD) 137 if (iface->pmsg[iface->cur_msg + 1].flags & I2C_M_RD)
@@ -148,44 +140,37 @@ static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface)
148 else 140 else
149 write_MASTER_CTL(iface, 141 write_MASTER_CTL(iface,
150 (read_MASTER_CTL(iface) | RSTART) & ~MDIR); 142 (read_MASTER_CTL(iface) | RSTART) & ~MDIR);
151 SSYNC();
152 } 143 }
153 /* Clear interrupt source */
154 write_INT_STAT(iface, RCVSERV);
155 SSYNC();
156 } 144 }
157 if (twi_int_status & MERR) { 145 if (twi_int_status & MERR) {
158 write_INT_STAT(iface, MERR);
159 write_INT_MASK(iface, 0); 146 write_INT_MASK(iface, 0);
160 write_MASTER_STAT(iface, 0x3e); 147 write_MASTER_STAT(iface, 0x3e);
161 write_MASTER_CTL(iface, 0); 148 write_MASTER_CTL(iface, 0);
162 SSYNC();
163 iface->result = -EIO; 149 iface->result = -EIO;
164 /* if both err and complete int stats are set, return proper 150
165 * results. 151 if (mast_stat & LOSTARB)
152 dev_dbg(&iface->adap.dev, "Lost Arbitration\n");
153 if (mast_stat & ANAK)
154 dev_dbg(&iface->adap.dev, "Address Not Acknowledged\n");
155 if (mast_stat & DNAK)
156 dev_dbg(&iface->adap.dev, "Data Not Acknowledged\n");
157 if (mast_stat & BUFRDERR)
158 dev_dbg(&iface->adap.dev, "Buffer Read Error\n");
159 if (mast_stat & BUFWRERR)
160 dev_dbg(&iface->adap.dev, "Buffer Write Error\n");
161
162 /* If it is a quick transfer, only address without data,
163 * not an err, return 1.
166 */ 164 */
167 if (twi_int_status & MCOMP) { 165 if (iface->cur_mode == TWI_I2C_MODE_STANDARD &&
168 write_INT_STAT(iface, MCOMP); 166 iface->transPtr == NULL &&
169 write_INT_MASK(iface, 0); 167 (twi_int_status & MCOMP) && (mast_stat & DNAK))
170 write_MASTER_CTL(iface, 0); 168 iface->result = 1;
171 SSYNC(); 169
172 /* If it is a quick transfer, only address bug no data,
173 * not an err, return 1.
174 */
175 if (iface->writeNum == 0 && (mast_stat & BUFRDERR))
176 iface->result = 1;
177 /* If address not acknowledged return -1,
178 * else return 0.
179 */
180 else if (!(mast_stat & ANAK))
181 iface->result = 0;
182 }
183 complete(&iface->complete); 170 complete(&iface->complete);
184 return; 171 return;
185 } 172 }
186 if (twi_int_status & MCOMP) { 173 if (twi_int_status & MCOMP) {
187 write_INT_STAT(iface, MCOMP);
188 SSYNC();
189 if (iface->cur_mode == TWI_I2C_MODE_COMBINED) { 174 if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
190 if (iface->readNum == 0) { 175 if (iface->readNum == 0) {
191 /* set the read number to 1 and ask for manual 176 /* set the read number to 1 and ask for manual
@@ -207,7 +192,6 @@ static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface)
207 /* remove restart bit and enable master receive */ 192 /* remove restart bit and enable master receive */
208 write_MASTER_CTL(iface, 193 write_MASTER_CTL(iface,
209 read_MASTER_CTL(iface) & ~RSTART); 194 read_MASTER_CTL(iface) & ~RSTART);
210 SSYNC();
211 } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT && 195 } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
212 iface->cur_msg+1 < iface->msg_num) { 196 iface->cur_msg+1 < iface->msg_num) {
213 iface->cur_msg++; 197 iface->cur_msg++;
@@ -226,7 +210,6 @@ static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface)
226 write_XMT_DATA8(iface, 210 write_XMT_DATA8(iface,
227 *(iface->transPtr++)); 211 *(iface->transPtr++));
228 iface->writeNum--; 212 iface->writeNum--;
229 SSYNC();
230 } 213 }
231 } 214 }
232 215
@@ -244,15 +227,13 @@ static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface)
244 /* remove restart bit and enable master receive */ 227 /* remove restart bit and enable master receive */
245 write_MASTER_CTL(iface, 228 write_MASTER_CTL(iface,
246 read_MASTER_CTL(iface) & ~RSTART); 229 read_MASTER_CTL(iface) & ~RSTART);
247 SSYNC();
248 } else { 230 } else {
249 iface->result = 1; 231 iface->result = 1;
250 write_INT_MASK(iface, 0); 232 write_INT_MASK(iface, 0);
251 write_MASTER_CTL(iface, 0); 233 write_MASTER_CTL(iface, 0);
252 SSYNC();
253 complete(&iface->complete);
254 } 234 }
255 } 235 }
236 complete(&iface->complete);
256} 237}
257 238
258/* Interrupt handler */ 239/* Interrupt handler */
@@ -260,38 +241,26 @@ static irqreturn_t bfin_twi_interrupt_entry(int irq, void *dev_id)
260{ 241{
261 struct bfin_twi_iface *iface = dev_id; 242 struct bfin_twi_iface *iface = dev_id;
262 unsigned long flags; 243 unsigned long flags;
244 unsigned short twi_int_status;
263 245
264 spin_lock_irqsave(&iface->lock, flags); 246 spin_lock_irqsave(&iface->lock, flags);
265 del_timer(&iface->timeout_timer); 247 while (1) {
266 bfin_twi_handle_interrupt(iface); 248 twi_int_status = read_INT_STAT(iface);
267 spin_unlock_irqrestore(&iface->lock, flags); 249 if (!twi_int_status)
268 return IRQ_HANDLED; 250 break;
269} 251 /* Clear interrupt status */
270 252 write_INT_STAT(iface, twi_int_status);
271static void bfin_twi_timeout(unsigned long data) 253 bfin_twi_handle_interrupt(iface, twi_int_status);
272{ 254 SSYNC();
273 struct bfin_twi_iface *iface = (struct bfin_twi_iface *)data;
274 unsigned long flags;
275
276 spin_lock_irqsave(&iface->lock, flags);
277 bfin_twi_handle_interrupt(iface);
278 if (iface->result == 0) {
279 iface->timeout_count--;
280 if (iface->timeout_count > 0) {
281 iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
282 add_timer(&iface->timeout_timer);
283 } else {
284 iface->result = -1;
285 complete(&iface->complete);
286 }
287 } 255 }
288 spin_unlock_irqrestore(&iface->lock, flags); 256 spin_unlock_irqrestore(&iface->lock, flags);
257 return IRQ_HANDLED;
289} 258}
290 259
291/* 260/*
292 * Generic i2c master transfer entrypoint 261 * One i2c master transfer
293 */ 262 */
294static int bfin_twi_master_xfer(struct i2c_adapter *adap, 263static int bfin_twi_do_master_xfer(struct i2c_adapter *adap,
295 struct i2c_msg *msgs, int num) 264 struct i2c_msg *msgs, int num)
296{ 265{
297 struct bfin_twi_iface *iface = adap->algo_data; 266 struct bfin_twi_iface *iface = adap->algo_data;
@@ -319,7 +288,6 @@ static int bfin_twi_master_xfer(struct i2c_adapter *adap,
319 iface->transPtr = pmsg->buf; 288 iface->transPtr = pmsg->buf;
320 iface->writeNum = iface->readNum = pmsg->len; 289 iface->writeNum = iface->readNum = pmsg->len;
321 iface->result = 0; 290 iface->result = 0;
322 iface->timeout_count = 10;
323 init_completion(&(iface->complete)); 291 init_completion(&(iface->complete));
324 /* Set Transmit device address */ 292 /* Set Transmit device address */
325 write_MASTER_ADDR(iface, pmsg->addr); 293 write_MASTER_ADDR(iface, pmsg->addr);
@@ -358,30 +326,41 @@ static int bfin_twi_master_xfer(struct i2c_adapter *adap,
358 iface->manual_stop = 1; 326 iface->manual_stop = 1;
359 } 327 }
360 328
361 iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
362 add_timer(&iface->timeout_timer);
363
364 /* Master enable */ 329 /* Master enable */
365 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN | 330 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
366 ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) | 331 ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
367 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0)); 332 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
368 SSYNC(); 333 SSYNC();
369 334
370 wait_for_completion(&iface->complete); 335 while (!iface->result) {
371 336 if (!wait_for_completion_timeout(&iface->complete,
372 rc = iface->result; 337 adap->timeout)) {
338 iface->result = -1;
339 dev_err(&adap->dev, "master transfer timeout\n");
340 }
341 }
373 342
374 if (rc == 1) 343 if (iface->result == 1)
375 return num; 344 rc = iface->cur_msg + 1;
376 else 345 else
377 return rc; 346 rc = iface->result;
347
348 return rc;
378} 349}
379 350
380/* 351/*
381 * SMBus type transfer entrypoint 352 * Generic i2c master transfer entrypoint
382 */ 353 */
354static int bfin_twi_master_xfer(struct i2c_adapter *adap,
355 struct i2c_msg *msgs, int num)
356{
357 return bfin_twi_do_master_xfer(adap, msgs, num);
358}
383 359
384int bfin_twi_smbus_xfer(struct i2c_adapter *adap, u16 addr, 360/*
361 * One I2C SMBus transfer
362 */
363int bfin_twi_do_smbus_xfer(struct i2c_adapter *adap, u16 addr,
385 unsigned short flags, char read_write, 364 unsigned short flags, char read_write,
386 u8 command, int size, union i2c_smbus_data *data) 365 u8 command, int size, union i2c_smbus_data *data)
387{ 366{
@@ -469,7 +448,6 @@ int bfin_twi_smbus_xfer(struct i2c_adapter *adap, u16 addr,
469 iface->manual_stop = 0; 448 iface->manual_stop = 0;
470 iface->read_write = read_write; 449 iface->read_write = read_write;
471 iface->command = command; 450 iface->command = command;
472 iface->timeout_count = 10;
473 init_completion(&(iface->complete)); 451 init_completion(&(iface->complete));
474 452
475 /* FIFO Initiation. Data in FIFO should be discarded before 453 /* FIFO Initiation. Data in FIFO should be discarded before
@@ -486,9 +464,6 @@ int bfin_twi_smbus_xfer(struct i2c_adapter *adap, u16 addr,
486 write_MASTER_ADDR(iface, addr); 464 write_MASTER_ADDR(iface, addr);
487 SSYNC(); 465 SSYNC();
488 466
489 iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
490 add_timer(&iface->timeout_timer);
491
492 switch (iface->cur_mode) { 467 switch (iface->cur_mode) {
493 case TWI_I2C_MODE_STANDARDSUB: 468 case TWI_I2C_MODE_STANDARDSUB:
494 write_XMT_DATA8(iface, iface->command); 469 write_XMT_DATA8(iface, iface->command);
@@ -550,10 +525,8 @@ int bfin_twi_smbus_xfer(struct i2c_adapter *adap, u16 addr,
550 else if (iface->readNum > 255) { 525 else if (iface->readNum > 255) {
551 write_MASTER_CTL(iface, 0xff << 6); 526 write_MASTER_CTL(iface, 0xff << 6);
552 iface->manual_stop = 1; 527 iface->manual_stop = 1;
553 } else { 528 } else
554 del_timer(&iface->timeout_timer);
555 break; 529 break;
556 }
557 } 530 }
558 } 531 }
559 write_INT_MASK(iface, MCOMP | MERR | 532 write_INT_MASK(iface, MCOMP | MERR |
@@ -569,7 +542,13 @@ int bfin_twi_smbus_xfer(struct i2c_adapter *adap, u16 addr,
569 } 542 }
570 SSYNC(); 543 SSYNC();
571 544
572 wait_for_completion(&iface->complete); 545 while (!iface->result) {
546 if (!wait_for_completion_timeout(&iface->complete,
547 adap->timeout)) {
548 iface->result = -1;
549 dev_err(&adap->dev, "smbus transfer timeout\n");
550 }
551 }
573 552
574 rc = (iface->result >= 0) ? 0 : -1; 553 rc = (iface->result >= 0) ? 0 : -1;
575 554
@@ -577,6 +556,17 @@ int bfin_twi_smbus_xfer(struct i2c_adapter *adap, u16 addr,
577} 556}
578 557
579/* 558/*
559 * Generic I2C SMBus transfer entrypoint
560 */
561int bfin_twi_smbus_xfer(struct i2c_adapter *adap, u16 addr,
562 unsigned short flags, char read_write,
563 u8 command, int size, union i2c_smbus_data *data)
564{
565 return bfin_twi_do_smbus_xfer(adap, addr, flags,
566 read_write, command, size, data);
567}
568
569/*
580 * Return what the adapter supports 570 * Return what the adapter supports
581 */ 571 */
582static u32 bfin_twi_functionality(struct i2c_adapter *adap) 572static u32 bfin_twi_functionality(struct i2c_adapter *adap)
@@ -667,10 +657,6 @@ static int i2c_bfin_twi_probe(struct platform_device *pdev)
667 goto out_error_no_irq; 657 goto out_error_no_irq;
668 } 658 }
669 659
670 init_timer(&(iface->timeout_timer));
671 iface->timeout_timer.function = bfin_twi_timeout;
672 iface->timeout_timer.data = (unsigned long)iface;
673
674 p_adap = &iface->adap; 660 p_adap = &iface->adap;
675 p_adap->nr = pdev->id; 661 p_adap->nr = pdev->id;
676 strlcpy(p_adap->name, pdev->name, sizeof(p_adap->name)); 662 strlcpy(p_adap->name, pdev->name, sizeof(p_adap->name));
@@ -678,6 +664,8 @@ static int i2c_bfin_twi_probe(struct platform_device *pdev)
678 p_adap->algo_data = iface; 664 p_adap->algo_data = iface;
679 p_adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; 665 p_adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
680 p_adap->dev.parent = &pdev->dev; 666 p_adap->dev.parent = &pdev->dev;
667 p_adap->timeout = 5 * HZ;
668 p_adap->retries = 3;
681 669
682 rc = peripheral_request_list(pin_req[pdev->id], "i2c-bfin-twi"); 670 rc = peripheral_request_list(pin_req[pdev->id], "i2c-bfin-twi");
683 if (rc) { 671 if (rc) {
diff --git a/drivers/i2c/busses/i2c-cpm.c b/drivers/i2c/busses/i2c-cpm.c
index 9c2e10082b79..16948db38973 100644
--- a/drivers/i2c/busses/i2c-cpm.c
+++ b/drivers/i2c/busses/i2c-cpm.c
@@ -441,7 +441,7 @@ static int __devinit cpm_i2c_setup(struct cpm_i2c *cpm)
441 init_waitqueue_head(&cpm->i2c_wait); 441 init_waitqueue_head(&cpm->i2c_wait);
442 442
443 cpm->irq = of_irq_to_resource(ofdev->node, 0, NULL); 443 cpm->irq = of_irq_to_resource(ofdev->node, 0, NULL);
444 if (cpm->irq == NO_IRQ) 444 if (!cpm->irq)
445 return -EINVAL; 445 return -EINVAL;
446 446
447 /* Install interrupt handler. */ 447 /* Install interrupt handler. */
diff --git a/drivers/i2c/busses/i2c-highlander.c b/drivers/i2c/busses/i2c-highlander.c
index ce87a902c94d..3df1bc80f37a 100644
--- a/drivers/i2c/busses/i2c-highlander.c
+++ b/drivers/i2c/busses/i2c-highlander.c
@@ -282,7 +282,6 @@ static int highlander_i2c_smbus_xfer(struct i2c_adapter *adap, u16 addr,
282 union i2c_smbus_data *data) 282 union i2c_smbus_data *data)
283{ 283{
284 struct highlander_i2c_dev *dev = i2c_get_adapdata(adap); 284 struct highlander_i2c_dev *dev = i2c_get_adapdata(adap);
285 int read = read_write & I2C_SMBUS_READ;
286 u16 tmp; 285 u16 tmp;
287 286
288 init_completion(&dev->cmd_complete); 287 init_completion(&dev->cmd_complete);
@@ -337,11 +336,11 @@ static int highlander_i2c_smbus_xfer(struct i2c_adapter *adap, u16 addr,
337 highlander_i2c_done(dev); 336 highlander_i2c_done(dev);
338 337
339 /* Set slave address */ 338 /* Set slave address */
340 iowrite16((addr << 1) | read, dev->base + SMSMADR); 339 iowrite16((addr << 1) | read_write, dev->base + SMSMADR);
341 340
342 highlander_i2c_command(dev, command, dev->buf_len); 341 highlander_i2c_command(dev, command, dev->buf_len);
343 342
344 if (read) 343 if (read_write == I2C_SMBUS_READ)
345 return highlander_i2c_read(dev); 344 return highlander_i2c_read(dev);
346 else 345 else
347 return highlander_i2c_write(dev); 346 return highlander_i2c_write(dev);
diff --git a/drivers/i2c/busses/i2c-ibm_iic.c b/drivers/i2c/busses/i2c-ibm_iic.c
index b1bc6e277d2a..2bef534cbff1 100644
--- a/drivers/i2c/busses/i2c-ibm_iic.c
+++ b/drivers/i2c/busses/i2c-ibm_iic.c
@@ -668,12 +668,12 @@ static int __devinit iic_request_irq(struct of_device *ofdev,
668 int irq; 668 int irq;
669 669
670 if (iic_force_poll) 670 if (iic_force_poll)
671 return NO_IRQ; 671 return 0;
672 672
673 irq = irq_of_parse_and_map(np, 0); 673 irq = irq_of_parse_and_map(np, 0);
674 if (irq == NO_IRQ) { 674 if (!irq) {
675 dev_err(&ofdev->dev, "irq_of_parse_and_map failed\n"); 675 dev_err(&ofdev->dev, "irq_of_parse_and_map failed\n");
676 return NO_IRQ; 676 return 0;
677 } 677 }
678 678
679 /* Disable interrupts until we finish initialization, assumes 679 /* Disable interrupts until we finish initialization, assumes
@@ -683,7 +683,7 @@ static int __devinit iic_request_irq(struct of_device *ofdev,
683 if (request_irq(irq, iic_handler, 0, "IBM IIC", dev)) { 683 if (request_irq(irq, iic_handler, 0, "IBM IIC", dev)) {
684 dev_err(&ofdev->dev, "request_irq %d failed\n", irq); 684 dev_err(&ofdev->dev, "request_irq %d failed\n", irq);
685 /* Fallback to the polling mode */ 685 /* Fallback to the polling mode */
686 return NO_IRQ; 686 return 0;
687 } 687 }
688 688
689 return irq; 689 return irq;
@@ -719,7 +719,7 @@ static int __devinit iic_probe(struct of_device *ofdev,
719 init_waitqueue_head(&dev->wq); 719 init_waitqueue_head(&dev->wq);
720 720
721 dev->irq = iic_request_irq(ofdev, dev); 721 dev->irq = iic_request_irq(ofdev, dev);
722 if (dev->irq == NO_IRQ) 722 if (!dev->irq)
723 dev_warn(&ofdev->dev, "using polling mode\n"); 723 dev_warn(&ofdev->dev, "using polling mode\n");
724 724
725 /* Board specific settings */ 725 /* Board specific settings */
@@ -766,7 +766,7 @@ static int __devinit iic_probe(struct of_device *ofdev,
766 return 0; 766 return 0;
767 767
768error_cleanup: 768error_cleanup:
769 if (dev->irq != NO_IRQ) { 769 if (dev->irq) {
770 iic_interrupt_mode(dev, 0); 770 iic_interrupt_mode(dev, 0);
771 free_irq(dev->irq, dev); 771 free_irq(dev->irq, dev);
772 } 772 }
@@ -790,7 +790,7 @@ static int __devexit iic_remove(struct of_device *ofdev)
790 790
791 i2c_del_adapter(&dev->adap); 791 i2c_del_adapter(&dev->adap);
792 792
793 if (dev->irq != NO_IRQ) { 793 if (dev->irq) {
794 iic_interrupt_mode(dev, 0); 794 iic_interrupt_mode(dev, 0);
795 free_irq(dev->irq, dev); 795 free_irq(dev->irq, dev);
796 } 796 }
diff --git a/drivers/i2c/busses/i2c-mpc.c b/drivers/i2c/busses/i2c-mpc.c
index f1321f763789..e86cef300c7d 100644
--- a/drivers/i2c/busses/i2c-mpc.c
+++ b/drivers/i2c/busses/i2c-mpc.c
@@ -118,7 +118,7 @@ static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout, int writing)
118 u32 x; 118 u32 x;
119 int result = 0; 119 int result = 0;
120 120
121 if (i2c->irq == NO_IRQ) { 121 if (!i2c->irq) {
122 while (!(readb(i2c->base + MPC_I2C_SR) & CSR_MIF)) { 122 while (!(readb(i2c->base + MPC_I2C_SR) & CSR_MIF)) {
123 schedule(); 123 schedule();
124 if (time_after(jiffies, orig_jiffies + timeout)) { 124 if (time_after(jiffies, orig_jiffies + timeout)) {
@@ -568,7 +568,7 @@ static int __devinit fsl_i2c_probe(struct of_device *op,
568 } 568 }
569 569
570 i2c->irq = irq_of_parse_and_map(op->node, 0); 570 i2c->irq = irq_of_parse_and_map(op->node, 0);
571 if (i2c->irq != NO_IRQ) { /* i2c->irq = NO_IRQ implies polling */ 571 if (i2c->irq) { /* no i2c->irq implies polling */
572 result = request_irq(i2c->irq, mpc_i2c_isr, 572 result = request_irq(i2c->irq, mpc_i2c_isr,
573 IRQF_SHARED, "i2c-mpc", i2c); 573 IRQF_SHARED, "i2c-mpc", i2c);
574 if (result < 0) { 574 if (result < 0) {
@@ -627,7 +627,7 @@ static int __devexit fsl_i2c_remove(struct of_device *op)
627 i2c_del_adapter(&i2c->adap); 627 i2c_del_adapter(&i2c->adap);
628 dev_set_drvdata(&op->dev, NULL); 628 dev_set_drvdata(&op->dev, NULL);
629 629
630 if (i2c->irq != NO_IRQ) 630 if (i2c->irq)
631 free_irq(i2c->irq, i2c); 631 free_irq(i2c->irq, i2c);
632 632
633 irq_dispose_mapping(i2c->irq); 633 irq_dispose_mapping(i2c->irq);
diff --git a/drivers/i2c/busses/i2c-nomadik.c b/drivers/i2c/busses/i2c-nomadik.c
index a4f8d33fa389..73de8ade10b1 100644
--- a/drivers/i2c/busses/i2c-nomadik.c
+++ b/drivers/i2c/busses/i2c-nomadik.c
@@ -704,7 +704,8 @@ static irqreturn_t i2c_irq_handler(int irq, void *arg)
704 case I2C_IT_MTD: 704 case I2C_IT_MTD:
705 case I2C_IT_MTDWS: 705 case I2C_IT_MTDWS:
706 if (dev->cli.operation == I2C_READ) { 706 if (dev->cli.operation == I2C_READ) {
707 while (!readl(dev->virtbase + I2C_RISR) & I2C_IT_RXFE) { 707 while (!(readl(dev->virtbase + I2C_RISR)
708 & I2C_IT_RXFE)) {
708 if (dev->cli.count == 0) 709 if (dev->cli.count == 0)
709 break; 710 break;
710 *dev->cli.buffer = 711 *dev->cli.buffer =
@@ -914,6 +915,7 @@ static int __devinit nmk_i2c_probe(struct platform_device *pdev)
914 915
915static int __devexit nmk_i2c_remove(struct platform_device *pdev) 916static int __devexit nmk_i2c_remove(struct platform_device *pdev)
916{ 917{
918 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
917 struct nmk_i2c_dev *dev = platform_get_drvdata(pdev); 919 struct nmk_i2c_dev *dev = platform_get_drvdata(pdev);
918 920
919 i2c_del_adapter(&dev->adap); 921 i2c_del_adapter(&dev->adap);
@@ -924,6 +926,8 @@ static int __devexit nmk_i2c_remove(struct platform_device *pdev)
924 i2c_clr_bit(dev->virtbase + I2C_CR, I2C_CR_PE); 926 i2c_clr_bit(dev->virtbase + I2C_CR, I2C_CR_PE);
925 free_irq(dev->irq, dev); 927 free_irq(dev->irq, dev);
926 iounmap(dev->virtbase); 928 iounmap(dev->virtbase);
929 if (res)
930 release_mem_region(res->start, resource_size(res));
927 clk_disable(dev->clk); 931 clk_disable(dev->clk);
928 clk_put(dev->clk); 932 clk_put(dev->clk);
929 platform_set_drvdata(pdev, NULL); 933 platform_set_drvdata(pdev, NULL);
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 389ac6032a7b..7674efb55378 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -38,6 +38,7 @@
38#include <linux/clk.h> 38#include <linux/clk.h>
39#include <linux/io.h> 39#include <linux/io.h>
40#include <linux/slab.h> 40#include <linux/slab.h>
41#include <linux/i2c-omap.h>
41 42
42/* I2C controller revisions */ 43/* I2C controller revisions */
43#define OMAP_I2C_REV_2 0x20 44#define OMAP_I2C_REV_2 0x20
@@ -45,29 +46,37 @@
45/* I2C controller revisions present on specific hardware */ 46/* I2C controller revisions present on specific hardware */
46#define OMAP_I2C_REV_ON_2430 0x36 47#define OMAP_I2C_REV_ON_2430 0x36
47#define OMAP_I2C_REV_ON_3430 0x3C 48#define OMAP_I2C_REV_ON_3430 0x3C
49#define OMAP_I2C_REV_ON_4430 0x40
48 50
49/* timeout waiting for the controller to respond */ 51/* timeout waiting for the controller to respond */
50#define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000)) 52#define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
51 53
52#define OMAP_I2C_REV_REG 0x00
53#define OMAP_I2C_IE_REG 0x01
54#define OMAP_I2C_STAT_REG 0x02
55#define OMAP_I2C_IV_REG 0x03
56/* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */ 54/* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
57#define OMAP_I2C_WE_REG 0x03 55enum {
58#define OMAP_I2C_SYSS_REG 0x04 56 OMAP_I2C_REV_REG = 0,
59#define OMAP_I2C_BUF_REG 0x05 57 OMAP_I2C_IE_REG,
60#define OMAP_I2C_CNT_REG 0x06 58 OMAP_I2C_STAT_REG,
61#define OMAP_I2C_DATA_REG 0x07 59 OMAP_I2C_IV_REG,
62#define OMAP_I2C_SYSC_REG 0x08 60 OMAP_I2C_WE_REG,
63#define OMAP_I2C_CON_REG 0x09 61 OMAP_I2C_SYSS_REG,
64#define OMAP_I2C_OA_REG 0x0a 62 OMAP_I2C_BUF_REG,
65#define OMAP_I2C_SA_REG 0x0b 63 OMAP_I2C_CNT_REG,
66#define OMAP_I2C_PSC_REG 0x0c 64 OMAP_I2C_DATA_REG,
67#define OMAP_I2C_SCLL_REG 0x0d 65 OMAP_I2C_SYSC_REG,
68#define OMAP_I2C_SCLH_REG 0x0e 66 OMAP_I2C_CON_REG,
69#define OMAP_I2C_SYSTEST_REG 0x0f 67 OMAP_I2C_OA_REG,
70#define OMAP_I2C_BUFSTAT_REG 0x10 68 OMAP_I2C_SA_REG,
69 OMAP_I2C_PSC_REG,
70 OMAP_I2C_SCLL_REG,
71 OMAP_I2C_SCLH_REG,
72 OMAP_I2C_SYSTEST_REG,
73 OMAP_I2C_BUFSTAT_REG,
74 OMAP_I2C_REVNB_LO,
75 OMAP_I2C_REVNB_HI,
76 OMAP_I2C_IRQSTATUS_RAW,
77 OMAP_I2C_IRQENABLE_SET,
78 OMAP_I2C_IRQENABLE_CLR,
79};
71 80
72/* I2C Interrupt Enable Register (OMAP_I2C_IE): */ 81/* I2C Interrupt Enable Register (OMAP_I2C_IE): */
73#define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */ 82#define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */
@@ -157,6 +166,9 @@
157#define SYSC_IDLEMODE_SMART 0x2 166#define SYSC_IDLEMODE_SMART 0x2
158#define SYSC_CLOCKACTIVITY_FCLK 0x2 167#define SYSC_CLOCKACTIVITY_FCLK 0x2
159 168
169/* Errata definitions */
170#define I2C_OMAP_ERRATA_I207 (1 << 0)
171#define I2C_OMAP3_1P153 (1 << 1)
160 172
161struct omap_i2c_dev { 173struct omap_i2c_dev {
162 struct device *dev; 174 struct device *dev;
@@ -167,9 +179,13 @@ struct omap_i2c_dev {
167 struct clk *fclk; /* Functional clock */ 179 struct clk *fclk; /* Functional clock */
168 struct completion cmd_complete; 180 struct completion cmd_complete;
169 struct resource *ioarea; 181 struct resource *ioarea;
182 u32 latency; /* maximum mpu wkup latency */
183 void (*set_mpu_wkup_lat)(struct device *dev,
184 long latency);
170 u32 speed; /* Speed of bus in Khz */ 185 u32 speed; /* Speed of bus in Khz */
171 u16 cmd_err; 186 u16 cmd_err;
172 u8 *buf; 187 u8 *buf;
188 u8 *regs;
173 size_t buf_len; 189 size_t buf_len;
174 struct i2c_adapter adapter; 190 struct i2c_adapter adapter;
175 u8 fifo_size; /* use as flag and value 191 u8 fifo_size; /* use as flag and value
@@ -186,17 +202,67 @@ struct omap_i2c_dev {
186 u16 bufstate; 202 u16 bufstate;
187 u16 syscstate; 203 u16 syscstate;
188 u16 westate; 204 u16 westate;
205 u16 errata;
206};
207
208const static u8 reg_map[] = {
209 [OMAP_I2C_REV_REG] = 0x00,
210 [OMAP_I2C_IE_REG] = 0x01,
211 [OMAP_I2C_STAT_REG] = 0x02,
212 [OMAP_I2C_IV_REG] = 0x03,
213 [OMAP_I2C_WE_REG] = 0x03,
214 [OMAP_I2C_SYSS_REG] = 0x04,
215 [OMAP_I2C_BUF_REG] = 0x05,
216 [OMAP_I2C_CNT_REG] = 0x06,
217 [OMAP_I2C_DATA_REG] = 0x07,
218 [OMAP_I2C_SYSC_REG] = 0x08,
219 [OMAP_I2C_CON_REG] = 0x09,
220 [OMAP_I2C_OA_REG] = 0x0a,
221 [OMAP_I2C_SA_REG] = 0x0b,
222 [OMAP_I2C_PSC_REG] = 0x0c,
223 [OMAP_I2C_SCLL_REG] = 0x0d,
224 [OMAP_I2C_SCLH_REG] = 0x0e,
225 [OMAP_I2C_SYSTEST_REG] = 0x0f,
226 [OMAP_I2C_BUFSTAT_REG] = 0x10,
227};
228
229const static u8 omap4_reg_map[] = {
230 [OMAP_I2C_REV_REG] = 0x04,
231 [OMAP_I2C_IE_REG] = 0x2c,
232 [OMAP_I2C_STAT_REG] = 0x28,
233 [OMAP_I2C_IV_REG] = 0x34,
234 [OMAP_I2C_WE_REG] = 0x34,
235 [OMAP_I2C_SYSS_REG] = 0x90,
236 [OMAP_I2C_BUF_REG] = 0x94,
237 [OMAP_I2C_CNT_REG] = 0x98,
238 [OMAP_I2C_DATA_REG] = 0x9c,
239 [OMAP_I2C_SYSC_REG] = 0x20,
240 [OMAP_I2C_CON_REG] = 0xa4,
241 [OMAP_I2C_OA_REG] = 0xa8,
242 [OMAP_I2C_SA_REG] = 0xac,
243 [OMAP_I2C_PSC_REG] = 0xb0,
244 [OMAP_I2C_SCLL_REG] = 0xb4,
245 [OMAP_I2C_SCLH_REG] = 0xb8,
246 [OMAP_I2C_SYSTEST_REG] = 0xbC,
247 [OMAP_I2C_BUFSTAT_REG] = 0xc0,
248 [OMAP_I2C_REVNB_LO] = 0x00,
249 [OMAP_I2C_REVNB_HI] = 0x04,
250 [OMAP_I2C_IRQSTATUS_RAW] = 0x24,
251 [OMAP_I2C_IRQENABLE_SET] = 0x2c,
252 [OMAP_I2C_IRQENABLE_CLR] = 0x30,
189}; 253};
190 254
191static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev, 255static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
192 int reg, u16 val) 256 int reg, u16 val)
193{ 257{
194 __raw_writew(val, i2c_dev->base + (reg << i2c_dev->reg_shift)); 258 __raw_writew(val, i2c_dev->base +
259 (i2c_dev->regs[reg] << i2c_dev->reg_shift));
195} 260}
196 261
197static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg) 262static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
198{ 263{
199 return __raw_readw(i2c_dev->base + (reg << i2c_dev->reg_shift)); 264 return __raw_readw(i2c_dev->base +
265 (i2c_dev->regs[reg] << i2c_dev->reg_shift));
200} 266}
201 267
202static int __init omap_i2c_get_clocks(struct omap_i2c_dev *dev) 268static int __init omap_i2c_get_clocks(struct omap_i2c_dev *dev)
@@ -265,7 +331,11 @@ static void omap_i2c_idle(struct omap_i2c_dev *dev)
265 WARN_ON(dev->idle); 331 WARN_ON(dev->idle);
266 332
267 dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG); 333 dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
268 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0); 334 if (dev->rev >= OMAP_I2C_REV_ON_4430)
335 omap_i2c_write_reg(dev, OMAP_I2C_IRQENABLE_CLR, 1);
336 else
337 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0);
338
269 if (dev->rev < OMAP_I2C_REV_2) { 339 if (dev->rev < OMAP_I2C_REV_2) {
270 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); /* Read clears */ 340 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); /* Read clears */
271 } else { 341 } else {
@@ -330,7 +400,9 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
330 * REVISIT: Some wkup sources might not be needed. 400 * REVISIT: Some wkup sources might not be needed.
331 */ 401 */
332 dev->westate = OMAP_I2C_WE_ALL; 402 dev->westate = OMAP_I2C_WE_ALL;
333 omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate); 403 if (dev->rev < OMAP_I2C_REV_ON_4430)
404 omap_i2c_write_reg(dev, OMAP_I2C_WE_REG,
405 dev->westate);
334 } 406 }
335 } 407 }
336 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); 408 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
@@ -357,7 +429,7 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
357 psc = fclk_rate / 12000000; 429 psc = fclk_rate / 12000000;
358 } 430 }
359 431
360 if (cpu_is_omap2430() || cpu_is_omap34xx()) { 432 if (!(cpu_class_is_omap1() || cpu_is_omap2420())) {
361 433
362 /* 434 /*
363 * HSI2C controller internal clk rate should be 19.2 Mhz for 435 * HSI2C controller internal clk rate should be 19.2 Mhz for
@@ -430,6 +502,11 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
430 /* Take the I2C module out of reset: */ 502 /* Take the I2C module out of reset: */
431 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN); 503 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
432 504
505 dev->errata = 0;
506
507 if (cpu_is_omap2430() || cpu_is_omap34xx())
508 dev->errata |= I2C_OMAP_ERRATA_I207;
509
433 /* Enable interrupts */ 510 /* Enable interrupts */
434 dev->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY | 511 dev->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
435 OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK | 512 OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
@@ -539,8 +616,12 @@ static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
539 * REVISIT: We should abort the transfer on signals, but the bus goes 616 * REVISIT: We should abort the transfer on signals, but the bus goes
540 * into arbitration and we're currently unable to recover from it. 617 * into arbitration and we're currently unable to recover from it.
541 */ 618 */
619 if (dev->set_mpu_wkup_lat != NULL)
620 dev->set_mpu_wkup_lat(dev->dev, dev->latency);
542 r = wait_for_completion_timeout(&dev->cmd_complete, 621 r = wait_for_completion_timeout(&dev->cmd_complete,
543 OMAP_I2C_TIMEOUT); 622 OMAP_I2C_TIMEOUT);
623 if (dev->set_mpu_wkup_lat != NULL)
624 dev->set_mpu_wkup_lat(dev->dev, -1);
544 dev->buf_len = 0; 625 dev->buf_len = 0;
545 if (r < 0) 626 if (r < 0)
546 return r; 627 return r;
@@ -623,6 +704,34 @@ omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
623 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat); 704 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
624} 705}
625 706
707static inline void i2c_omap_errata_i207(struct omap_i2c_dev *dev, u16 stat)
708{
709 /*
710 * I2C Errata(Errata Nos. OMAP2: 1.67, OMAP3: 1.8)
711 * Not applicable for OMAP4.
712 * Under certain rare conditions, RDR could be set again
713 * when the bus is busy, then ignore the interrupt and
714 * clear the interrupt.
715 */
716 if (stat & OMAP_I2C_STAT_RDR) {
717 /* Step 1: If RDR is set, clear it */
718 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
719
720 /* Step 2: */
721 if (!(omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG)
722 & OMAP_I2C_STAT_BB)) {
723
724 /* Step 3: */
725 if (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG)
726 & OMAP_I2C_STAT_RDR) {
727 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
728 dev_dbg(dev->dev, "RDR when bus is busy.\n");
729 }
730
731 }
732 }
733}
734
626/* rev1 devices are apparently only on some 15xx */ 735/* rev1 devices are apparently only on some 15xx */
627#ifdef CONFIG_ARCH_OMAP15XX 736#ifdef CONFIG_ARCH_OMAP15XX
628 737
@@ -684,6 +793,35 @@ omap_i2c_rev1_isr(int this_irq, void *dev_id)
684#define omap_i2c_rev1_isr NULL 793#define omap_i2c_rev1_isr NULL
685#endif 794#endif
686 795
796/*
797 * OMAP3430 Errata 1.153: When an XRDY/XDR is hit, wait for XUDF before writing
798 * data to DATA_REG. Otherwise some data bytes can be lost while transferring
799 * them from the memory to the I2C interface.
800 */
801static int errata_omap3_1p153(struct omap_i2c_dev *dev, u16 *stat, int *err)
802{
803 unsigned long timeout = 10000;
804
805 while (--timeout && !(*stat & OMAP_I2C_STAT_XUDF)) {
806 if (*stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
807 omap_i2c_ack_stat(dev, *stat & (OMAP_I2C_STAT_XRDY |
808 OMAP_I2C_STAT_XDR));
809 *err |= OMAP_I2C_STAT_XUDF;
810 return -ETIMEDOUT;
811 }
812
813 cpu_relax();
814 *stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
815 }
816
817 if (!timeout) {
818 dev_err(dev->dev, "timeout waiting on XUDF bit\n");
819 return 0;
820 }
821
822 return 0;
823}
824
687static irqreturn_t 825static irqreturn_t
688omap_i2c_isr(int this_irq, void *dev_id) 826omap_i2c_isr(int this_irq, void *dev_id)
689{ 827{
@@ -733,6 +871,10 @@ complete:
733 } 871 }
734 if (stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)) { 872 if (stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)) {
735 u8 num_bytes = 1; 873 u8 num_bytes = 1;
874
875 if (dev->errata & I2C_OMAP_ERRATA_I207)
876 i2c_omap_errata_i207(dev, stat);
877
736 if (dev->fifo_size) { 878 if (dev->fifo_size) {
737 if (stat & OMAP_I2C_STAT_RRDY) 879 if (stat & OMAP_I2C_STAT_RRDY)
738 num_bytes = dev->fifo_size; 880 num_bytes = dev->fifo_size;
@@ -747,9 +889,12 @@ complete:
747 if (dev->buf_len) { 889 if (dev->buf_len) {
748 *dev->buf++ = w; 890 *dev->buf++ = w;
749 dev->buf_len--; 891 dev->buf_len--;
750 /* Data reg from 2430 is 8 bit wide */ 892 /*
751 if (!cpu_is_omap2430() && 893 * Data reg in 2430, omap3 and
752 !cpu_is_omap34xx()) { 894 * omap4 is 8 bit wide
895 */
896 if (cpu_class_is_omap1() ||
897 cpu_is_omap2420()) {
753 if (dev->buf_len) { 898 if (dev->buf_len) {
754 *dev->buf++ = w >> 8; 899 *dev->buf++ = w >> 8;
755 dev->buf_len--; 900 dev->buf_len--;
@@ -787,9 +932,12 @@ complete:
787 if (dev->buf_len) { 932 if (dev->buf_len) {
788 w = *dev->buf++; 933 w = *dev->buf++;
789 dev->buf_len--; 934 dev->buf_len--;
790 /* Data reg from 2430 is 8 bit wide */ 935 /*
791 if (!cpu_is_omap2430() && 936 * Data reg in 2430, omap3 and
792 !cpu_is_omap34xx()) { 937 * omap4 is 8 bit wide
938 */
939 if (cpu_class_is_omap1() ||
940 cpu_is_omap2420()) {
793 if (dev->buf_len) { 941 if (dev->buf_len) {
794 w |= *dev->buf++ << 8; 942 w |= *dev->buf++ << 8;
795 dev->buf_len--; 943 dev->buf_len--;
@@ -807,25 +955,9 @@ complete:
807 break; 955 break;
808 } 956 }
809 957
810 /* 958 if ((dev->errata & I2C_OMAP3_1P153) &&
811 * OMAP3430 Errata 1.153: When an XRDY/XDR 959 errata_omap3_1p153(dev, &stat, &err))
812 * is hit, wait for XUDF before writing data 960 goto complete;
813 * to DATA_REG. Otherwise some data bytes can
814 * be lost while transferring them from the
815 * memory to the I2C interface.
816 */
817
818 if (dev->rev <= OMAP_I2C_REV_ON_3430) {
819 while (!(stat & OMAP_I2C_STAT_XUDF)) {
820 if (stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
821 omap_i2c_ack_stat(dev, stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
822 err |= OMAP_I2C_STAT_XUDF;
823 goto complete;
824 }
825 cpu_relax();
826 stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
827 }
828 }
829 961
830 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w); 962 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
831 } 963 }
@@ -857,6 +989,7 @@ omap_i2c_probe(struct platform_device *pdev)
857 struct omap_i2c_dev *dev; 989 struct omap_i2c_dev *dev;
858 struct i2c_adapter *adap; 990 struct i2c_adapter *adap;
859 struct resource *mem, *irq, *ioarea; 991 struct resource *mem, *irq, *ioarea;
992 struct omap_i2c_bus_platform_data *pdata = pdev->dev.platform_data;
860 irq_handler_t isr; 993 irq_handler_t isr;
861 int r; 994 int r;
862 u32 speed = 0; 995 u32 speed = 0;
@@ -886,10 +1019,13 @@ omap_i2c_probe(struct platform_device *pdev)
886 goto err_release_region; 1019 goto err_release_region;
887 } 1020 }
888 1021
889 if (pdev->dev.platform_data != NULL) 1022 if (pdata != NULL) {
890 speed = *(u32 *)pdev->dev.platform_data; 1023 speed = pdata->clkrate;
891 else 1024 dev->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat;
892 speed = 100; /* Defualt speed */ 1025 } else {
1026 speed = 100; /* Default speed */
1027 dev->set_mpu_wkup_lat = NULL;
1028 }
893 1029
894 dev->speed = speed; 1030 dev->speed = speed;
895 dev->idle = 1; 1031 dev->idle = 1;
@@ -905,17 +1041,27 @@ omap_i2c_probe(struct platform_device *pdev)
905 1041
906 if (cpu_is_omap7xx()) 1042 if (cpu_is_omap7xx())
907 dev->reg_shift = 1; 1043 dev->reg_shift = 1;
1044 else if (cpu_is_omap44xx())
1045 dev->reg_shift = 0;
908 else 1046 else
909 dev->reg_shift = 2; 1047 dev->reg_shift = 2;
910 1048
911 if ((r = omap_i2c_get_clocks(dev)) != 0) 1049 if ((r = omap_i2c_get_clocks(dev)) != 0)
912 goto err_iounmap; 1050 goto err_iounmap;
913 1051
1052 if (cpu_is_omap44xx())
1053 dev->regs = (u8 *) omap4_reg_map;
1054 else
1055 dev->regs = (u8 *) reg_map;
1056
914 omap_i2c_unidle(dev); 1057 omap_i2c_unidle(dev);
915 1058
916 dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff; 1059 dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
917 1060
918 if (cpu_is_omap2430() || cpu_is_omap34xx()) { 1061 if (dev->rev <= OMAP_I2C_REV_ON_3430)
1062 dev->errata |= I2C_OMAP3_1P153;
1063
1064 if (!(cpu_class_is_omap1() || cpu_is_omap2420())) {
919 u16 s; 1065 u16 s;
920 1066
921 /* Set up the fifo size - Get total size */ 1067 /* Set up the fifo size - Get total size */
@@ -927,8 +1073,17 @@ omap_i2c_probe(struct platform_device *pdev)
927 * size. This is to ensure that we can handle the status on int 1073 * size. This is to ensure that we can handle the status on int
928 * call back latencies. 1074 * call back latencies.
929 */ 1075 */
930 dev->fifo_size = (dev->fifo_size / 2); 1076 if (dev->rev >= OMAP_I2C_REV_ON_4430) {
931 dev->b_hw = 1; /* Enable hardware fixes */ 1077 dev->fifo_size = 0;
1078 dev->b_hw = 0; /* Disable hardware fixes */
1079 } else {
1080 dev->fifo_size = (dev->fifo_size / 2);
1081 dev->b_hw = 1; /* Enable hardware fixes */
1082 }
1083 /* calculate wakeup latency constraint for MPU */
1084 if (dev->set_mpu_wkup_lat != NULL)
1085 dev->latency = (1000000 * dev->fifo_size) /
1086 (1000 * speed / 8);
932 } 1087 }
933 1088
934 /* reset ASAP, clearing any IRQs */ 1089 /* reset ASAP, clearing any IRQs */
diff --git a/drivers/i2c/busses/i2c-pxa.c b/drivers/i2c/busses/i2c-pxa.c
index 14d249f5ed3f..fbde6f614059 100644
--- a/drivers/i2c/busses/i2c-pxa.c
+++ b/drivers/i2c/busses/i2c-pxa.c
@@ -209,18 +209,6 @@ static void i2c_pxa_show_state(struct pxa_i2c *i2c, int lno, const char *fname)
209} 209}
210 210
211#define show_state(i2c) i2c_pxa_show_state(i2c, __LINE__, __func__) 211#define show_state(i2c) i2c_pxa_show_state(i2c, __LINE__, __func__)
212#else
213#define i2c_debug 0
214
215#define show_state(i2c) do { } while (0)
216#define decode_ISR(val) do { } while (0)
217#define decode_ICR(val) do { } while (0)
218#endif
219
220#define eedbg(lvl, x...) do { if ((lvl) < 1) { printk(KERN_DEBUG "" x); } } while(0)
221
222static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret);
223static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id);
224 212
225static void i2c_pxa_scream_blue_murder(struct pxa_i2c *i2c, const char *why) 213static void i2c_pxa_scream_blue_murder(struct pxa_i2c *i2c, const char *why)
226{ 214{
@@ -236,6 +224,20 @@ static void i2c_pxa_scream_blue_murder(struct pxa_i2c *i2c, const char *why)
236 printk("\n"); 224 printk("\n");
237} 225}
238 226
227#else /* ifdef DEBUG */
228
229#define i2c_debug 0
230
231#define show_state(i2c) do { } while (0)
232#define decode_ISR(val) do { } while (0)
233#define decode_ICR(val) do { } while (0)
234#define i2c_pxa_scream_blue_murder(i2c, why) do { } while (0)
235
236#endif /* ifdef DEBUG / else */
237
238static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret);
239static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id);
240
239static inline int i2c_pxa_is_slavemode(struct pxa_i2c *i2c) 241static inline int i2c_pxa_is_slavemode(struct pxa_i2c *i2c)
240{ 242{
241 return !(readl(_ICR(i2c)) & ICR_SCLE); 243 return !(readl(_ICR(i2c)) & ICR_SCLE);
diff --git a/drivers/i2c/busses/i2c-s3c2410.c b/drivers/i2c/busses/i2c-s3c2410.c
index d27072b2249f..ec3256cce91e 100644
--- a/drivers/i2c/busses/i2c-s3c2410.c
+++ b/drivers/i2c/busses/i2c-s3c2410.c
@@ -482,7 +482,8 @@ static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c)
482static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c, 482static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c,
483 struct i2c_msg *msgs, int num) 483 struct i2c_msg *msgs, int num)
484{ 484{
485 unsigned long timeout; 485 unsigned long iicstat, timeout;
486 int spins = 20;
486 int ret; 487 int ret;
487 488
488 if (i2c->suspended) 489 if (i2c->suspended)
@@ -521,7 +522,21 @@ static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c,
521 522
522 /* ensure the stop has been through the bus */ 523 /* ensure the stop has been through the bus */
523 524
524 msleep(1); 525 dev_dbg(i2c->dev, "waiting for bus idle\n");
526
527 /* first, try busy waiting briefly */
528 do {
529 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
530 } while ((iicstat & S3C2410_IICSTAT_START) && --spins);
531
532 /* if that timed out sleep */
533 if (!spins) {
534 msleep(1);
535 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
536 }
537
538 if (iicstat & S3C2410_IICSTAT_START)
539 dev_warn(i2c->dev, "timeout waiting for bus idle\n");
525 540
526 out: 541 out:
527 return ret; 542 return ret;
diff --git a/include/linux/i2c-omap.h b/include/linux/i2c-omap.h
new file mode 100644
index 000000000000..78ebf507ce56
--- /dev/null
+++ b/include/linux/i2c-omap.h
@@ -0,0 +1,9 @@
1#ifndef __I2C_OMAP_H__
2#define __I2C_OMAP_H__
3
4struct omap_i2c_bus_platform_data {
5 u32 clkrate;
6 void (*set_mpu_wkup_lat)(struct device *dev, long set);
7};
8
9#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-26 04:25:24 -0500