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-rw-r--r--Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt2
-rw-r--r--arch/arm/boot/dts/atlas6.dtsi12
-rw-r--r--arch/arm/boot/dts/prima2.dtsi42
-rw-r--r--arch/blackfin/Kconfig11
-rw-r--r--arch/blackfin/include/asm/gpio.h157
-rw-r--r--arch/blackfin/include/asm/portmux.h19
-rw-r--r--arch/blackfin/kernel/Makefile3
-rw-r--r--arch/blackfin/mach-bf548/include/mach/portmux.h2
-rw-r--r--arch/blackfin/mach-bf609/include/mach/portmux.h2
-rw-r--r--drivers/pinctrl/Kconfig18
-rw-r--r--drivers/pinctrl/Makefile3
-rw-r--r--drivers/pinctrl/pinctrl-adi2-bf54x.c592
-rw-r--r--drivers/pinctrl/pinctrl-adi2-bf60x.c521
-rw-r--r--drivers/pinctrl/pinctrl-adi2.c1158
-rw-r--r--drivers/pinctrl/pinctrl-adi2.h75
-rw-r--r--drivers/pinctrl/pinctrl-at91.c28
-rw-r--r--drivers/pinctrl/pinctrl-exynos5440.c2
-rw-r--r--drivers/pinctrl/pinctrl-imx35.c2
-rw-r--r--drivers/pinctrl/pinctrl-imx51.c2
-rw-r--r--drivers/pinctrl/pinctrl-imx53.c2
-rw-r--r--drivers/pinctrl/pinctrl-imx6dl.c2
-rw-r--r--drivers/pinctrl/pinctrl-imx6q.c2
-rw-r--r--drivers/pinctrl/pinctrl-imx6sl.c2
-rw-r--r--drivers/pinctrl/pinctrl-palmas.c17
-rw-r--r--drivers/pinctrl/pinctrl-samsung.c2
-rw-r--r--drivers/pinctrl/pinctrl-vf610.c2
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7778.c125
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7790.c110
-rw-r--r--drivers/pinctrl/sirf/pinctrl-atlas6.c56
-rw-r--r--drivers/pinctrl/sirf/pinctrl-prima2.c115
-rw-r--r--drivers/pinctrl/sirf/pinctrl-sirf.c8
-rw-r--r--drivers/pinctrl/sirf/pinctrl-sirf.h6
-rw-r--r--drivers/pinctrl/spear/pinctrl-plgpio.c2
-rw-r--r--include/dt-bindings/pinctrl/at91.h2
-rw-r--r--include/linux/platform_data/pinctrl-adi2.h40
35 files changed, 2955 insertions, 189 deletions
diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
index 7ccae490ff6d..02ab5ab198a4 100644
--- a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
@@ -18,7 +18,7 @@ mode) this pin can work on and the 'config' configures various pad settings
18such as pull-up, multi drive, etc. 18such as pull-up, multi drive, etc.
19 19
20Required properties for iomux controller: 20Required properties for iomux controller:
21- compatible: "atmel,at91rm9200-pinctrl" 21- compatible: "atmel,at91rm9200-pinctrl" or "atmel,at91sam9x5-pinctrl"
22- atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be 22- atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be
23 configured in this periph mode. All the periph and bank need to be describe. 23 configured in this periph mode. All the periph and bank need to be describe.
24 24
diff --git a/arch/arm/boot/dts/atlas6.dtsi b/arch/arm/boot/dts/atlas6.dtsi
index 6db4f81d4795..0600bad24c04 100644
--- a/arch/arm/boot/dts/atlas6.dtsi
+++ b/arch/arm/boot/dts/atlas6.dtsi
@@ -527,6 +527,18 @@
527 sirf,function = "usb1_utmi_drvbus"; 527 sirf,function = "usb1_utmi_drvbus";
528 }; 528 };
529 }; 529 };
530 usb1_dp_dn_pins_a: usb1_dp_dn@0 {
531 usb1_dp_dn {
532 sirf,pins = "usb1_dp_dngrp";
533 sirf,function = "usb1_dp_dn";
534 };
535 };
536 uart1_route_io_usb1_pins_a: uart1_route_io_usb1@0 {
537 uart1_route_io_usb1 {
538 sirf,pins = "uart1_route_io_usb1grp";
539 sirf,function = "uart1_route_io_usb1";
540 };
541 };
530 warm_rst_pins_a: warm_rst@0 { 542 warm_rst_pins_a: warm_rst@0 {
531 warm_rst { 543 warm_rst {
532 sirf,pins = "warm_rstgrp"; 544 sirf,pins = "warm_rstgrp";
diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi
index 27ed9f5144bc..006952da97f0 100644
--- a/arch/arm/boot/dts/prima2.dtsi
+++ b/arch/arm/boot/dts/prima2.dtsi
@@ -360,6 +360,12 @@
360 sirf,function = "uart0"; 360 sirf,function = "uart0";
361 }; 361 };
362 }; 362 };
363 uart0_noflow_pins_a: uart0@1 {
364 uart {
365 sirf,pins = "uart0_nostreamctrlgrp";
366 sirf,function = "uart0_nostreamctrl";
367 };
368 };
363 uart1_pins_a: uart1@0 { 369 uart1_pins_a: uart1@0 {
364 uart { 370 uart {
365 sirf,pins = "uart1grp"; 371 sirf,pins = "uart1grp";
@@ -498,18 +504,42 @@
498 sirf,function = "usp0"; 504 sirf,function = "usp0";
499 }; 505 };
500 }; 506 };
507 usp0_uart_nostreamctrl_pins_a: usp0@1 {
508 usp0 {
509 sirf,pins =
510 "usp0_uart_nostreamctrl_grp";
511 sirf,function =
512 "usp0_uart_nostreamctrl";
513 };
514 };
501 usp1_pins_a: usp1@0 { 515 usp1_pins_a: usp1@0 {
502 usp1 { 516 usp1 {
503 sirf,pins = "usp1grp"; 517 sirf,pins = "usp1grp";
504 sirf,function = "usp1"; 518 sirf,function = "usp1";
505 }; 519 };
506 }; 520 };
521 usp1_uart_nostreamctrl_pins_a: usp1@1 {
522 usp1 {
523 sirf,pins =
524 "usp1_uart_nostreamctrl_grp";
525 sirf,function =
526 "usp1_uart_nostreamctrl";
527 };
528 };
507 usp2_pins_a: usp2@0 { 529 usp2_pins_a: usp2@0 {
508 usp2 { 530 usp2 {
509 sirf,pins = "usp2grp"; 531 sirf,pins = "usp2grp";
510 sirf,function = "usp2"; 532 sirf,function = "usp2";
511 }; 533 };
512 }; 534 };
535 usp2_uart_nostreamctrl_pins_a: usp2@1 {
536 usp2 {
537 sirf,pins =
538 "usp2_uart_nostreamctrl_grp";
539 sirf,function =
540 "usp2_uart_nostreamctrl";
541 };
542 };
513 usb0_utmi_drvbus_pins_a: usb0_utmi_drvbus@0 { 543 usb0_utmi_drvbus_pins_a: usb0_utmi_drvbus@0 {
514 usb0_utmi_drvbus { 544 usb0_utmi_drvbus {
515 sirf,pins = "usb0_utmi_drvbusgrp"; 545 sirf,pins = "usb0_utmi_drvbusgrp";
@@ -522,6 +552,18 @@
522 sirf,function = "usb1_utmi_drvbus"; 552 sirf,function = "usb1_utmi_drvbus";
523 }; 553 };
524 }; 554 };
555 usb1_dp_dn_pins_a: usb1_dp_dn@0 {
556 usb1_dp_dn {
557 sirf,pins = "usb1_dp_dngrp";
558 sirf,function = "usb1_dp_dn";
559 };
560 };
561 uart1_route_io_usb1_pins_a: uart1_route_io_usb1@0 {
562 uart1_route_io_usb1 {
563 sirf,pins = "uart1_route_io_usb1grp";
564 sirf,function = "uart1_route_io_usb1";
565 };
566 };
525 warm_rst_pins_a: warm_rst@0 { 567 warm_rst_pins_a: warm_rst@0 {
526 warm_rst { 568 warm_rst {
527 sirf,pins = "warm_rstgrp"; 569 sirf,pins = "warm_rstgrp";
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index f78c9a2c7e28..74314bd8be39 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -52,6 +52,9 @@ config GENERIC_BUG
52config ZONE_DMA 52config ZONE_DMA
53 def_bool y 53 def_bool y
54 54
55config GENERIC_GPIO
56 def_bool y
57
55config FORCE_MAX_ZONEORDER 58config FORCE_MAX_ZONEORDER
56 int 59 int
57 default "14" 60 default "14"
@@ -317,6 +320,14 @@ config BF53x
317 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537) 320 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
318 default y 321 default y
319 322
323config GPIO_ADI
324 def_bool y
325 depends on (BF51x || BF52x || BF53x || BF538 || BF539 || BF561)
326
327config PINCTRL
328 def_bool y
329 depends on BF54x || BF60x
330
320config MEM_MT48LC64M4A2FB_7E 331config MEM_MT48LC64M4A2FB_7E
321 bool 332 bool
322 depends on (BFIN533_STAMP) 333 depends on (BFIN533_STAMP)
diff --git a/arch/blackfin/include/asm/gpio.h b/arch/blackfin/include/asm/gpio.h
index 98d0133346b5..99d338ca2ea4 100644
--- a/arch/blackfin/include/asm/gpio.h
+++ b/arch/blackfin/include/asm/gpio.h
@@ -25,8 +25,12 @@
25 25
26#ifndef __ASSEMBLY__ 26#ifndef __ASSEMBLY__
27 27
28#ifndef CONFIG_PINCTRL
29
28#include <linux/compiler.h> 30#include <linux/compiler.h>
29#include <linux/gpio.h> 31#include <asm/blackfin.h>
32#include <asm/portmux.h>
33#include <asm/irq_handler.h>
30 34
31/*********************************************************** 35/***********************************************************
32* 36*
@@ -45,7 +49,6 @@
45* MODIFICATION HISTORY : 49* MODIFICATION HISTORY :
46**************************************************************/ 50**************************************************************/
47 51
48#if !BFIN_GPIO_PINT
49void set_gpio_dir(unsigned, unsigned short); 52void set_gpio_dir(unsigned, unsigned short);
50void set_gpio_inen(unsigned, unsigned short); 53void set_gpio_inen(unsigned, unsigned short);
51void set_gpio_polar(unsigned, unsigned short); 54void set_gpio_polar(unsigned, unsigned short);
@@ -115,7 +118,6 @@ struct gpio_port_t {
115 unsigned short dummy16; 118 unsigned short dummy16;
116 unsigned short inen; 119 unsigned short inen;
117}; 120};
118#endif
119 121
120#ifdef BFIN_SPECIAL_GPIO_BANKS 122#ifdef BFIN_SPECIAL_GPIO_BANKS
121void bfin_special_gpio_free(unsigned gpio); 123void bfin_special_gpio_free(unsigned gpio);
@@ -127,25 +129,21 @@ void bfin_special_gpio_pm_hibernate_suspend(void);
127#endif 129#endif
128 130
129#ifdef CONFIG_PM 131#ifdef CONFIG_PM
130int bfin_pm_standby_ctrl(unsigned ctrl); 132void bfin_gpio_pm_hibernate_restore(void);
133void bfin_gpio_pm_hibernate_suspend(void);
134int bfin_gpio_pm_wakeup_ctrl(unsigned gpio, unsigned ctrl);
135int bfin_gpio_pm_standby_ctrl(unsigned ctrl);
131 136
132static inline int bfin_pm_standby_setup(void) 137static inline int bfin_pm_standby_setup(void)
133{ 138{
134 return bfin_pm_standby_ctrl(1); 139 return bfin_gpio_pm_standby_ctrl(1);
135} 140}
136 141
137static inline void bfin_pm_standby_restore(void) 142static inline void bfin_pm_standby_restore(void)
138{ 143{
139 bfin_pm_standby_ctrl(0); 144 bfin_gpio_pm_standby_ctrl(0);
140} 145}
141 146
142void bfin_gpio_pm_hibernate_restore(void);
143void bfin_gpio_pm_hibernate_suspend(void);
144void bfin_pint_suspend(void);
145void bfin_pint_resume(void);
146
147# if !BFIN_GPIO_PINT
148int gpio_pm_wakeup_ctrl(unsigned gpio, unsigned ctrl);
149 147
150struct gpio_port_s { 148struct gpio_port_s {
151 unsigned short data; 149 unsigned short data;
@@ -161,7 +159,6 @@ struct gpio_port_s {
161 unsigned short reserved; 159 unsigned short reserved;
162 unsigned short mux; 160 unsigned short mux;
163}; 161};
164# endif
165#endif /*CONFIG_PM*/ 162#endif /*CONFIG_PM*/
166 163
167/*********************************************************** 164/***********************************************************
@@ -178,36 +175,29 @@ struct gpio_port_s {
178************************************************************* 175*************************************************************
179* MODIFICATION HISTORY : 176* MODIFICATION HISTORY :
180**************************************************************/ 177**************************************************************/
181
182int bfin_gpio_request(unsigned gpio, const char *label);
183void bfin_gpio_free(unsigned gpio);
184int bfin_gpio_irq_request(unsigned gpio, const char *label); 178int bfin_gpio_irq_request(unsigned gpio, const char *label);
185void bfin_gpio_irq_free(unsigned gpio); 179void bfin_gpio_irq_free(unsigned gpio);
186int bfin_gpio_direction_input(unsigned gpio); 180void bfin_gpio_irq_prepare(unsigned gpio);
187int bfin_gpio_direction_output(unsigned gpio, int value); 181
188int bfin_gpio_get_value(unsigned gpio); 182static inline int irq_to_gpio(unsigned irq)
189void bfin_gpio_set_value(unsigned gpio, int value); 183{
184 return irq - GPIO_IRQ_BASE;
185}
186#endif /* CONFIG_PINCTRL */
190 187
191#include <asm/irq.h> 188#include <asm/irq.h>
192#include <asm/errno.h> 189#include <asm/errno.h>
193 190
194#ifdef CONFIG_GPIOLIB
195#include <asm-generic/gpio.h> /* cansleep wrappers */ 191#include <asm-generic/gpio.h> /* cansleep wrappers */
196 192
197static inline int gpio_get_value(unsigned int gpio) 193static inline int gpio_get_value(unsigned int gpio)
198{ 194{
199 if (gpio < MAX_BLACKFIN_GPIOS) 195 return __gpio_get_value(gpio);
200 return bfin_gpio_get_value(gpio);
201 else
202 return __gpio_get_value(gpio);
203} 196}
204 197
205static inline void gpio_set_value(unsigned int gpio, int value) 198static inline void gpio_set_value(unsigned int gpio, int value)
206{ 199{
207 if (gpio < MAX_BLACKFIN_GPIOS) 200 __gpio_set_value(gpio, value);
208 bfin_gpio_set_value(gpio, value);
209 else
210 __gpio_set_value(gpio, value);
211} 201}
212 202
213static inline int gpio_cansleep(unsigned int gpio) 203static inline int gpio_cansleep(unsigned int gpio)
@@ -219,113 +209,6 @@ static inline int gpio_to_irq(unsigned gpio)
219{ 209{
220 return __gpio_to_irq(gpio); 210 return __gpio_to_irq(gpio);
221} 211}
222
223#else /* !CONFIG_GPIOLIB */
224
225static inline int gpio_request(unsigned gpio, const char *label)
226{
227 return bfin_gpio_request(gpio, label);
228}
229
230static inline void gpio_free(unsigned gpio)
231{
232 return bfin_gpio_free(gpio);
233}
234
235static inline int gpio_direction_input(unsigned gpio)
236{
237 return bfin_gpio_direction_input(gpio);
238}
239
240static inline int gpio_direction_output(unsigned gpio, int value)
241{
242 return bfin_gpio_direction_output(gpio, value);
243}
244
245static inline int gpio_set_debounce(unsigned gpio, unsigned debounce)
246{
247 return -EINVAL;
248}
249
250static inline int gpio_request_one(unsigned gpio, unsigned long flags, const char *label)
251{
252 int err;
253
254 err = bfin_gpio_request(gpio, label);
255 if (err)
256 return err;
257
258 if (flags & GPIOF_DIR_IN)
259 err = bfin_gpio_direction_input(gpio);
260 else
261 err = bfin_gpio_direction_output(gpio,
262 (flags & GPIOF_INIT_HIGH) ? 1 : 0);
263
264 if (err)
265 bfin_gpio_free(gpio);
266
267 return err;
268}
269
270static inline int gpio_request_array(const struct gpio *array, size_t num)
271{
272 int i, err;
273
274 for (i = 0; i < num; i++, array++) {
275 err = gpio_request_one(array->gpio, array->flags, array->label);
276 if (err)
277 goto err_free;
278 }
279 return 0;
280
281err_free:
282 while (i--)
283 bfin_gpio_free((--array)->gpio);
284 return err;
285}
286
287static inline void gpio_free_array(const struct gpio *array, size_t num)
288{
289 while (num--)
290 bfin_gpio_free((array++)->gpio);
291}
292
293static inline int __gpio_get_value(unsigned gpio)
294{
295 return bfin_gpio_get_value(gpio);
296}
297
298static inline void __gpio_set_value(unsigned gpio, int value)
299{
300 return bfin_gpio_set_value(gpio, value);
301}
302
303static inline int gpio_get_value(unsigned gpio)
304{
305 return __gpio_get_value(gpio);
306}
307
308static inline void gpio_set_value(unsigned gpio, int value)
309{
310 return __gpio_set_value(gpio, value);
311}
312
313static inline int gpio_to_irq(unsigned gpio)
314{
315 if (likely(gpio < MAX_BLACKFIN_GPIOS))
316 return gpio + GPIO_IRQ_BASE;
317
318 return -EINVAL;
319}
320
321#include <asm-generic/gpio.h> /* cansleep wrappers */
322#endif /* !CONFIG_GPIOLIB */
323
324static inline int irq_to_gpio(unsigned irq)
325{
326 return (irq - GPIO_IRQ_BASE);
327}
328
329#endif /* __ASSEMBLY__ */ 212#endif /* __ASSEMBLY__ */
330 213
331#endif /* __ARCH_BLACKFIN_GPIO_H__ */ 214#endif /* __ARCH_BLACKFIN_GPIO_H__ */
diff --git a/arch/blackfin/include/asm/portmux.h b/arch/blackfin/include/asm/portmux.h
index 9b1e2c37b324..7aa20436e799 100644
--- a/arch/blackfin/include/asm/portmux.h
+++ b/arch/blackfin/include/asm/portmux.h
@@ -17,14 +17,29 @@
17#define P_MAYSHARE 0x2000 17#define P_MAYSHARE 0x2000
18#define P_DONTCARE 0x1000 18#define P_DONTCARE 0x1000
19 19
20 20#ifdef CONFIG_PINCTRL
21#include <asm/irq_handler.h>
22
23#define gpio_pint_regs bfin_pint_regs
24#define adi_internal_set_wake bfin_internal_set_wake
25
26#define peripheral_request(per, label) 0
27#define peripheral_free(per)
28#define peripheral_request_list(per, label) \
29 (pdev ? (IS_ERR(devm_pinctrl_get_select_default(&pdev->dev)) \
30 ? -EINVAL : 0) : 0)
31#define peripheral_free_list(per)
32#else
21int peripheral_request(unsigned short per, const char *label); 33int peripheral_request(unsigned short per, const char *label);
22void peripheral_free(unsigned short per); 34void peripheral_free(unsigned short per);
23int peripheral_request_list(const unsigned short per[], const char *label); 35int peripheral_request_list(const unsigned short per[], const char *label);
24void peripheral_free_list(const unsigned short per[]); 36void peripheral_free_list(const unsigned short per[]);
37#endif
25 38
26#include <asm/gpio.h> 39#include <linux/err.h>
40#include <linux/pinctrl/pinctrl.h>
27#include <mach/portmux.h> 41#include <mach/portmux.h>
42#include <linux/gpio.h>
28 43
29#ifndef P_SPORT2_TFS 44#ifndef P_SPORT2_TFS
30#define P_SPORT2_TFS P_UNDEF 45#define P_SPORT2_TFS P_UNDEF
diff --git a/arch/blackfin/kernel/Makefile b/arch/blackfin/kernel/Makefile
index 735f24e07425..703dc7cf2ecc 100644
--- a/arch/blackfin/kernel/Makefile
+++ b/arch/blackfin/kernel/Makefile
@@ -7,7 +7,7 @@ extra-y := vmlinux.lds
7obj-y := \ 7obj-y := \
8 entry.o process.o bfin_ksyms.o ptrace.o setup.o signal.o \ 8 entry.o process.o bfin_ksyms.o ptrace.o setup.o signal.o \
9 sys_bfin.o traps.o irqchip.o dma-mapping.o flat.o \ 9 sys_bfin.o traps.o irqchip.o dma-mapping.o flat.o \
10 fixed_code.o reboot.o bfin_gpio.o bfin_dma.o \ 10 fixed_code.o reboot.o bfin_dma.o \
11 exception.o dumpstack.o 11 exception.o dumpstack.o
12 12
13ifeq ($(CONFIG_GENERIC_CLOCKEVENTS),y) 13ifeq ($(CONFIG_GENERIC_CLOCKEVENTS),y)
@@ -16,6 +16,7 @@ else
16 obj-y += time.o 16 obj-y += time.o
17endif 17endif
18 18
19obj-$(CONFIG_GPIO_ADI) += bfin_gpio.o
19obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o 20obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o
20obj-$(CONFIG_FUNCTION_TRACER) += ftrace-entry.o 21obj-$(CONFIG_FUNCTION_TRACER) += ftrace-entry.o
21obj-$(CONFIG_FUNCTION_GRAPH_TRACER) += ftrace.o 22obj-$(CONFIG_FUNCTION_GRAPH_TRACER) += ftrace.o
diff --git a/arch/blackfin/mach-bf548/include/mach/portmux.h b/arch/blackfin/mach-bf548/include/mach/portmux.h
index e22246202730..d9f8632d7d09 100644
--- a/arch/blackfin/mach-bf548/include/mach/portmux.h
+++ b/arch/blackfin/mach-bf548/include/mach/portmux.h
@@ -7,8 +7,6 @@
7#ifndef _MACH_PORTMUX_H_ 7#ifndef _MACH_PORTMUX_H_
8#define _MACH_PORTMUX_H_ 8#define _MACH_PORTMUX_H_
9 9
10#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
11
12#define P_SPORT2_TFS (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0)) 10#define P_SPORT2_TFS (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0))
13#define P_SPORT2_DTSEC (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0)) 11#define P_SPORT2_DTSEC (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0))
14#define P_SPORT2_DTPRI (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(0)) 12#define P_SPORT2_DTPRI (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(0))
diff --git a/arch/blackfin/mach-bf609/include/mach/portmux.h b/arch/blackfin/mach-bf609/include/mach/portmux.h
index 2e1a51c25098..fe34191eef0b 100644
--- a/arch/blackfin/mach-bf609/include/mach/portmux.h
+++ b/arch/blackfin/mach-bf609/include/mach/portmux.h
@@ -7,8 +7,6 @@
7#ifndef _MACH_PORTMUX_H_ 7#ifndef _MACH_PORTMUX_H_
8#define _MACH_PORTMUX_H_ 8#define _MACH_PORTMUX_H_
9 9
10#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
11
12/* EMAC RMII Port Mux */ 10/* EMAC RMII Port Mux */
13#define P_MII0_MDC (P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(0)) 11#define P_MII0_MDC (P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(0))
14#define P_MII0_MDIO (P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(0)) 12#define P_MII0_MDIO (P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(0))
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index b6e864e8c9e8..21db2013543b 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -49,6 +49,24 @@ config PINCTRL_AB8505
49 bool "AB8505 pin controller driver" 49 bool "AB8505 pin controller driver"
50 depends on PINCTRL_ABX500 && ARCH_U8500 50 depends on PINCTRL_ABX500 && ARCH_U8500
51 51
52config PINCTRL_ADI2
53 bool "ADI pin controller driver"
54 depends on BLACKFIN
55 select PINMUX
56 select IRQ_DOMAIN
57 help
58 This is the pin controller and gpio driver for ADI BF54x, BF60x and
59 future processors. This option is selected automatically when specific
60 machine and arch are selected to build.
61
62config PINCTRL_BF54x
63 def_bool y if BF54x
64 select PINCTRL_ADI2
65
66config PINCTRL_BF60x
67 def_bool y if BF60x
68 select PINCTRL_ADI2
69
52config PINCTRL_AT91 70config PINCTRL_AT91
53 bool "AT91 pinctrl driver" 71 bool "AT91 pinctrl driver"
54 depends on OF 72 depends on OF
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 496d9bf9e1b9..bbeb98086495 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -14,6 +14,9 @@ obj-$(CONFIG_PINCTRL_AB8500) += pinctrl-ab8500.o
14obj-$(CONFIG_PINCTRL_AB8540) += pinctrl-ab8540.o 14obj-$(CONFIG_PINCTRL_AB8540) += pinctrl-ab8540.o
15obj-$(CONFIG_PINCTRL_AB9540) += pinctrl-ab9540.o 15obj-$(CONFIG_PINCTRL_AB9540) += pinctrl-ab9540.o
16obj-$(CONFIG_PINCTRL_AB8505) += pinctrl-ab8505.o 16obj-$(CONFIG_PINCTRL_AB8505) += pinctrl-ab8505.o
17obj-$(CONFIG_PINCTRL_ADI2) += pinctrl-adi2.o
18obj-$(CONFIG_PINCTRL_BF54x) += pinctrl-adi2-bf54x.o
19obj-$(CONFIG_PINCTRL_BF60x) += pinctrl-adi2-bf60x.o
17obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o 20obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o
18obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o 21obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o
19obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o 22obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o
diff --git a/drivers/pinctrl/pinctrl-adi2-bf54x.c b/drivers/pinctrl/pinctrl-adi2-bf54x.c
new file mode 100644
index 000000000000..ea9d9ab9cda1
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-adi2-bf54x.c
@@ -0,0 +1,592 @@
1/*
2 * Pinctrl Driver for ADI GPIO2 controller
3 *
4 * Copyright 2007-2013 Analog Devices Inc.
5 *
6 * Licensed under the GPLv2 or later
7 */
8
9#include <asm/portmux.h>
10#include "pinctrl-adi2.h"
11
12static const struct pinctrl_pin_desc adi_pads[] = {
13 PINCTRL_PIN(0, "PA0"),
14 PINCTRL_PIN(1, "PA1"),
15 PINCTRL_PIN(2, "PA2"),
16 PINCTRL_PIN(3, "PG3"),
17 PINCTRL_PIN(4, "PA4"),
18 PINCTRL_PIN(5, "PA5"),
19 PINCTRL_PIN(6, "PA6"),
20 PINCTRL_PIN(7, "PA7"),
21 PINCTRL_PIN(8, "PA8"),
22 PINCTRL_PIN(9, "PA9"),
23 PINCTRL_PIN(10, "PA10"),
24 PINCTRL_PIN(11, "PA11"),
25 PINCTRL_PIN(12, "PA12"),
26 PINCTRL_PIN(13, "PA13"),
27 PINCTRL_PIN(14, "PA14"),
28 PINCTRL_PIN(15, "PA15"),
29 PINCTRL_PIN(16, "PB0"),
30 PINCTRL_PIN(17, "PB1"),
31 PINCTRL_PIN(18, "PB2"),
32 PINCTRL_PIN(19, "PB3"),
33 PINCTRL_PIN(20, "PB4"),
34 PINCTRL_PIN(21, "PB5"),
35 PINCTRL_PIN(22, "PB6"),
36 PINCTRL_PIN(23, "PB7"),
37 PINCTRL_PIN(24, "PB8"),
38 PINCTRL_PIN(25, "PB9"),
39 PINCTRL_PIN(26, "PB10"),
40 PINCTRL_PIN(27, "PB11"),
41 PINCTRL_PIN(28, "PB12"),
42 PINCTRL_PIN(29, "PB13"),
43 PINCTRL_PIN(30, "PB14"),
44 PINCTRL_PIN(32, "PC0"),
45 PINCTRL_PIN(33, "PC1"),
46 PINCTRL_PIN(34, "PC2"),
47 PINCTRL_PIN(35, "PC3"),
48 PINCTRL_PIN(36, "PC4"),
49 PINCTRL_PIN(37, "PC5"),
50 PINCTRL_PIN(38, "PC6"),
51 PINCTRL_PIN(39, "PC7"),
52 PINCTRL_PIN(40, "PC8"),
53 PINCTRL_PIN(41, "PC9"),
54 PINCTRL_PIN(42, "PC10"),
55 PINCTRL_PIN(43, "PC11"),
56 PINCTRL_PIN(44, "PC12"),
57 PINCTRL_PIN(45, "PC13"),
58 PINCTRL_PIN(48, "PD0"),
59 PINCTRL_PIN(49, "PD1"),
60 PINCTRL_PIN(50, "PD2"),
61 PINCTRL_PIN(51, "PD3"),
62 PINCTRL_PIN(52, "PD4"),
63 PINCTRL_PIN(53, "PD5"),
64 PINCTRL_PIN(54, "PD6"),
65 PINCTRL_PIN(55, "PD7"),
66 PINCTRL_PIN(56, "PD8"),
67 PINCTRL_PIN(57, "PD9"),
68 PINCTRL_PIN(58, "PD10"),
69 PINCTRL_PIN(59, "PD11"),
70 PINCTRL_PIN(60, "PD12"),
71 PINCTRL_PIN(61, "PD13"),
72 PINCTRL_PIN(62, "PD14"),
73 PINCTRL_PIN(63, "PD15"),
74 PINCTRL_PIN(64, "PE0"),
75 PINCTRL_PIN(65, "PE1"),
76 PINCTRL_PIN(66, "PE2"),
77 PINCTRL_PIN(67, "PE3"),
78 PINCTRL_PIN(68, "PE4"),
79 PINCTRL_PIN(69, "PE5"),
80 PINCTRL_PIN(70, "PE6"),
81 PINCTRL_PIN(71, "PE7"),
82 PINCTRL_PIN(72, "PE8"),
83 PINCTRL_PIN(73, "PE9"),
84 PINCTRL_PIN(74, "PE10"),
85 PINCTRL_PIN(75, "PE11"),
86 PINCTRL_PIN(76, "PE12"),
87 PINCTRL_PIN(77, "PE13"),
88 PINCTRL_PIN(78, "PE14"),
89 PINCTRL_PIN(79, "PE15"),
90 PINCTRL_PIN(80, "PF0"),
91 PINCTRL_PIN(81, "PF1"),
92 PINCTRL_PIN(82, "PF2"),
93 PINCTRL_PIN(83, "PF3"),
94 PINCTRL_PIN(84, "PF4"),
95 PINCTRL_PIN(85, "PF5"),
96 PINCTRL_PIN(86, "PF6"),
97 PINCTRL_PIN(87, "PF7"),
98 PINCTRL_PIN(88, "PF8"),
99 PINCTRL_PIN(89, "PF9"),
100 PINCTRL_PIN(90, "PF10"),
101 PINCTRL_PIN(91, "PF11"),
102 PINCTRL_PIN(92, "PF12"),
103 PINCTRL_PIN(93, "PF13"),
104 PINCTRL_PIN(94, "PF14"),
105 PINCTRL_PIN(95, "PF15"),
106 PINCTRL_PIN(96, "PG0"),
107 PINCTRL_PIN(97, "PG1"),
108 PINCTRL_PIN(98, "PG2"),
109 PINCTRL_PIN(99, "PG3"),
110 PINCTRL_PIN(100, "PG4"),
111 PINCTRL_PIN(101, "PG5"),
112 PINCTRL_PIN(102, "PG6"),
113 PINCTRL_PIN(103, "PG7"),
114 PINCTRL_PIN(104, "PG8"),
115 PINCTRL_PIN(105, "PG9"),
116 PINCTRL_PIN(106, "PG10"),
117 PINCTRL_PIN(107, "PG11"),
118 PINCTRL_PIN(108, "PG12"),
119 PINCTRL_PIN(109, "PG13"),
120 PINCTRL_PIN(110, "PG14"),
121 PINCTRL_PIN(111, "PG15"),
122 PINCTRL_PIN(112, "PH0"),
123 PINCTRL_PIN(113, "PH1"),
124 PINCTRL_PIN(114, "PH2"),
125 PINCTRL_PIN(115, "PH3"),
126 PINCTRL_PIN(116, "PH4"),
127 PINCTRL_PIN(117, "PH5"),
128 PINCTRL_PIN(118, "PH6"),
129 PINCTRL_PIN(119, "PH7"),
130 PINCTRL_PIN(120, "PH8"),
131 PINCTRL_PIN(121, "PH9"),
132 PINCTRL_PIN(122, "PH10"),
133 PINCTRL_PIN(123, "PH11"),
134 PINCTRL_PIN(124, "PH12"),
135 PINCTRL_PIN(125, "PH13"),
136 PINCTRL_PIN(128, "PI0"),
137 PINCTRL_PIN(129, "PI1"),
138 PINCTRL_PIN(130, "PI2"),
139 PINCTRL_PIN(131, "PI3"),
140 PINCTRL_PIN(132, "PI4"),
141 PINCTRL_PIN(133, "PI5"),
142 PINCTRL_PIN(134, "PI6"),
143 PINCTRL_PIN(135, "PI7"),
144 PINCTRL_PIN(136, "PI8"),
145 PINCTRL_PIN(137, "PI9"),
146 PINCTRL_PIN(138, "PI10"),
147 PINCTRL_PIN(139, "PI11"),
148 PINCTRL_PIN(140, "PI12"),
149 PINCTRL_PIN(141, "PI13"),
150 PINCTRL_PIN(142, "PI14"),
151 PINCTRL_PIN(143, "PI15"),
152 PINCTRL_PIN(144, "PJ0"),
153 PINCTRL_PIN(145, "PJ1"),
154 PINCTRL_PIN(146, "PJ2"),
155 PINCTRL_PIN(147, "PJ3"),
156 PINCTRL_PIN(148, "PJ4"),
157 PINCTRL_PIN(149, "PJ5"),
158 PINCTRL_PIN(150, "PJ6"),
159 PINCTRL_PIN(151, "PJ7"),
160 PINCTRL_PIN(152, "PJ8"),
161 PINCTRL_PIN(153, "PJ9"),
162 PINCTRL_PIN(154, "PJ10"),
163 PINCTRL_PIN(155, "PJ11"),
164 PINCTRL_PIN(156, "PJ12"),
165 PINCTRL_PIN(157, "PJ13"),
166};
167
168static const unsigned uart0_pins[] = {
169 GPIO_PE7, GPIO_PE8,
170};
171
172static const unsigned uart1_pins[] = {
173 GPIO_PH0, GPIO_PH1,
174};
175
176static const unsigned uart1_ctsrts_pins[] = {
177 GPIO_PE9, GPIO_PE10,
178};
179
180static const unsigned uart2_pins[] = {
181 GPIO_PB4, GPIO_PB5,
182};
183
184static const unsigned uart3_pins[] = {
185 GPIO_PB6, GPIO_PB7,
186};
187
188static const unsigned uart3_ctsrts_pins[] = {
189 GPIO_PB2, GPIO_PB3,
190};
191
192static const unsigned rsi0_pins[] = {
193 GPIO_PC8, GPIO_PC9, GPIO_PC10, GPIO_PC11, GPIO_PC12, GPIO_PC13,
194};
195
196static const unsigned spi0_pins[] = {
197 GPIO_PE0, GPIO_PE1, GPIO_PE2,
198};
199
200static const unsigned spi1_pins[] = {
201 GPIO_PG8, GPIO_PG9, GPIO_PG10,
202};
203
204static const unsigned twi0_pins[] = {
205 GPIO_PE14, GPIO_PE15,
206};
207
208static const unsigned twi1_pins[] = {
209 GPIO_PB0, GPIO_PB1,
210};
211
212static const unsigned rotary_pins[] = {
213 GPIO_PH4, GPIO_PH3, GPIO_PH5,
214};
215
216static const unsigned can0_pins[] = {
217 GPIO_PG13, GPIO_PG12,
218};
219
220static const unsigned can1_pins[] = {
221 GPIO_PG14, GPIO_PG15,
222};
223
224static const unsigned smc0_pins[] = {
225 GPIO_PH8, GPIO_PH9, GPIO_PH10, GPIO_PH11, GPIO_PH12, GPIO_PH13,
226 GPIO_PI0, GPIO_PI1, GPIO_PI2, GPIO_PI3, GPIO_PI4, GPIO_PI5, GPIO_PI6,
227 GPIO_PI7, GPIO_PI8, GPIO_PI9, GPIO_PI10, GPIO_PI11,
228 GPIO_PI12, GPIO_PI13, GPIO_PI14, GPIO_PI15,
229};
230
231static const unsigned sport0_pins[] = {
232 GPIO_PC0, GPIO_PC2, GPIO_PC3, GPIO_PC4, GPIO_PC6, GPIO_PC7,
233};
234
235static const unsigned sport1_pins[] = {
236 GPIO_PD0, GPIO_PD2, GPIO_PD3, GPIO_PD4, GPIO_PD6, GPIO_PD7,
237};
238
239static const unsigned sport2_pins[] = {
240 GPIO_PA0, GPIO_PA2, GPIO_PA3, GPIO_PA4, GPIO_PA6, GPIO_PA7,
241};
242
243static const unsigned sport3_pins[] = {
244 GPIO_PA8, GPIO_PA10, GPIO_PA11, GPIO_PA12, GPIO_PA14, GPIO_PA15,
245};
246
247static const unsigned ppi0_8b_pins[] = {
248 GPIO_PF0, GPIO_PF1, GPIO_PF2, GPIO_PF3, GPIO_PF4, GPIO_PF5, GPIO_PF6,
249 GPIO_PF7, GPIO_PF13, GPIO_PG0, GPIO_PG1, GPIO_PG2,
250};
251
252static const unsigned ppi0_16b_pins[] = {
253 GPIO_PF0, GPIO_PF1, GPIO_PF2, GPIO_PF3, GPIO_PF4, GPIO_PF5, GPIO_PF6,
254 GPIO_PF7, GPIO_PF9, GPIO_PF10, GPIO_PF11, GPIO_PF12,
255 GPIO_PF13, GPIO_PF14, GPIO_PF15,
256 GPIO_PG0, GPIO_PG1, GPIO_PG2,
257};
258
259static const unsigned ppi0_24b_pins[] = {
260 GPIO_PF0, GPIO_PF1, GPIO_PF2, GPIO_PF3, GPIO_PF4, GPIO_PF5, GPIO_PF6,
261 GPIO_PF7, GPIO_PF8, GPIO_PF9, GPIO_PF10, GPIO_PF11, GPIO_PF12,
262 GPIO_PF13, GPIO_PF14, GPIO_PF15, GPIO_PD0, GPIO_PD1, GPIO_PD2,
263 GPIO_PD3, GPIO_PD4, GPIO_PD5, GPIO_PG3, GPIO_PG4,
264 GPIO_PG0, GPIO_PG1, GPIO_PG2,
265};
266
267static const unsigned ppi1_8b_pins[] = {
268 GPIO_PD0, GPIO_PD1, GPIO_PD2, GPIO_PD3, GPIO_PD4, GPIO_PD5, GPIO_PD6,
269 GPIO_PD7, GPIO_PE11, GPIO_PE12, GPIO_PE13,
270};
271
272static const unsigned ppi1_16b_pins[] = {
273 GPIO_PD0, GPIO_PD1, GPIO_PD2, GPIO_PD3, GPIO_PD4, GPIO_PD5, GPIO_PD6,
274 GPIO_PD7, GPIO_PD8, GPIO_PD9, GPIO_PD10, GPIO_PD11, GPIO_PD12,
275 GPIO_PD13, GPIO_PD14, GPIO_PD15,
276 GPIO_PE11, GPIO_PE12, GPIO_PE13,
277};
278
279static const unsigned ppi2_8b_pins[] = {
280 GPIO_PD8, GPIO_PD9, GPIO_PD10, GPIO_PD11, GPIO_PD12,
281 GPIO_PD13, GPIO_PD14, GPIO_PD15,
282 GPIO_PA7, GPIO_PB0, GPIO_PB1, GPIO_PB2, GPIO_PB3,
283};
284
285static const unsigned atapi_pins[] = {
286 GPIO_PH2, GPIO_PJ3, GPIO_PJ4, GPIO_PJ5, GPIO_PJ6,
287 GPIO_PJ7, GPIO_PJ8, GPIO_PJ9, GPIO_PJ10,
288};
289
290static const unsigned atapi_alter_pins[] = {
291 GPIO_PF0, GPIO_PF1, GPIO_PF2, GPIO_PF3, GPIO_PF4, GPIO_PF5, GPIO_PF6,
292 GPIO_PF7, GPIO_PF8, GPIO_PF9, GPIO_PF10, GPIO_PF11, GPIO_PF12,
293 GPIO_PF13, GPIO_PF14, GPIO_PF15, GPIO_PG2, GPIO_PG3, GPIO_PG4,
294};
295
296static const unsigned nfc0_pins[] = {
297 GPIO_PJ1, GPIO_PJ2,
298};
299
300static const unsigned keys_4x4_pins[] = {
301 GPIO_PD8, GPIO_PD9, GPIO_PD10, GPIO_PD11,
302 GPIO_PD12, GPIO_PD13, GPIO_PD14, GPIO_PD15,
303};
304
305static const unsigned keys_8x8_pins[] = {
306 GPIO_PD8, GPIO_PD9, GPIO_PD10, GPIO_PD11,
307 GPIO_PD12, GPIO_PD13, GPIO_PD14, GPIO_PD15,
308 GPIO_PE0, GPIO_PE1, GPIO_PE2, GPIO_PE3,
309 GPIO_PE4, GPIO_PE5, GPIO_PE6, GPIO_PE7,
310};
311
312static const struct adi_pin_group adi_pin_groups[] = {
313 ADI_PIN_GROUP("uart0grp", uart0_pins),
314 ADI_PIN_GROUP("uart1grp", uart1_pins),
315 ADI_PIN_GROUP("uart1ctsrtsgrp", uart1_ctsrts_pins),
316 ADI_PIN_GROUP("uart2grp", uart2_pins),
317 ADI_PIN_GROUP("uart3grp", uart3_pins),
318 ADI_PIN_GROUP("uart3ctsrtsgrp", uart3_ctsrts_pins),
319 ADI_PIN_GROUP("rsi0grp", rsi0_pins),
320 ADI_PIN_GROUP("spi0grp", spi0_pins),
321 ADI_PIN_GROUP("spi1grp", spi1_pins),
322 ADI_PIN_GROUP("twi0grp", twi0_pins),
323 ADI_PIN_GROUP("twi1grp", twi1_pins),
324 ADI_PIN_GROUP("rotarygrp", rotary_pins),
325 ADI_PIN_GROUP("can0grp", can0_pins),
326 ADI_PIN_GROUP("can1grp", can1_pins),
327 ADI_PIN_GROUP("smc0grp", smc0_pins),
328 ADI_PIN_GROUP("sport0grp", sport0_pins),
329 ADI_PIN_GROUP("sport1grp", sport1_pins),
330 ADI_PIN_GROUP("sport2grp", sport2_pins),
331 ADI_PIN_GROUP("sport3grp", sport3_pins),
332 ADI_PIN_GROUP("ppi0_8bgrp", ppi0_8b_pins),
333 ADI_PIN_GROUP("ppi0_16bgrp", ppi0_16b_pins),
334 ADI_PIN_GROUP("ppi0_24bgrp", ppi0_24b_pins),
335 ADI_PIN_GROUP("ppi1_8bgrp", ppi1_8b_pins),
336 ADI_PIN_GROUP("ppi1_16bgrp", ppi1_16b_pins),
337 ADI_PIN_GROUP("ppi2_8bgrp", ppi2_8b_pins),
338 ADI_PIN_GROUP("atapigrp", atapi_pins),
339 ADI_PIN_GROUP("atapialtergrp", atapi_alter_pins),
340 ADI_PIN_GROUP("nfc0grp", nfc0_pins),
341 ADI_PIN_GROUP("keys_4x4grp", keys_4x4_pins),
342 ADI_PIN_GROUP("keys_8x8grp", keys_8x8_pins),
343};
344
345static const unsigned short uart0_mux[] = {
346 P_UART0_TX, P_UART0_RX,
347 0
348};
349
350static const unsigned short uart1_mux[] = {
351 P_UART1_TX, P_UART1_RX,
352 0
353};
354
355static const unsigned short uart1_ctsrts_mux[] = {
356 P_UART1_RTS, P_UART1_CTS,
357 0
358};
359
360static const unsigned short uart2_mux[] = {
361 P_UART2_TX, P_UART2_RX,
362 0
363};
364
365static const unsigned short uart3_mux[] = {
366 P_UART3_TX, P_UART3_RX,
367 0
368};
369
370static const unsigned short uart3_ctsrts_mux[] = {
371 P_UART3_RTS, P_UART3_CTS,
372 0
373};
374
375static const unsigned short rsi0_mux[] = {
376 P_SD_D0, P_SD_D1, P_SD_D2, P_SD_D3, P_SD_CLK, P_SD_CMD,
377 0
378};
379
380static const unsigned short spi0_mux[] = {
381 P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0
382};
383
384static const unsigned short spi1_mux[] = {
385 P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0
386};
387
388static const unsigned short twi0_mux[] = {
389 P_TWI0_SCL, P_TWI0_SDA, 0
390};
391
392static const unsigned short twi1_mux[] = {
393 P_TWI1_SCL, P_TWI1_SDA, 0
394};
395
396static const unsigned short rotary_mux[] = {
397 P_CNT_CUD, P_CNT_CDG, P_CNT_CZM, 0
398};
399
400static const unsigned short sport0_mux[] = {
401 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
402 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
403};
404
405static const unsigned short sport1_mux[] = {
406 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
407 P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
408};
409
410static const unsigned short sport2_mux[] = {
411 P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS,
412 P_SPORT2_DRPRI, P_SPORT2_RSCLK, 0
413};
414
415static const unsigned short sport3_mux[] = {
416 P_SPORT3_TFS, P_SPORT3_DTPRI, P_SPORT3_TSCLK, P_SPORT3_RFS,
417 P_SPORT3_DRPRI, P_SPORT3_RSCLK, 0
418};
419
420static const unsigned short can0_mux[] = {
421 P_CAN0_RX, P_CAN0_TX, 0
422};
423
424static const unsigned short can1_mux[] = {
425 P_CAN1_RX, P_CAN1_TX, 0
426};
427
428static const unsigned short smc0_mux[] = {
429 P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12,
430 P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20, P_A21,
431 P_A22, P_A23, P_A24, P_A25, P_NOR_CLK, 0,
432};
433
434static const unsigned short ppi0_8b_mux[] = {
435 P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
436 P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
437 P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
438 0,
439};
440
441static const unsigned short ppi0_16b_mux[] = {
442 P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
443 P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
444 P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
445 P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15,
446 P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
447 0,
448};
449
450static const unsigned short ppi0_24b_mux[] = {
451 P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
452 P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
453 P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
454 P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15,
455 P_PPI0_D16, P_PPI0_D17, P_PPI0_D18, P_PPI0_D19,
456 P_PPI0_D20, P_PPI0_D21, P_PPI0_D22, P_PPI0_D23,
457 P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
458 0,
459};
460
461static const unsigned short ppi1_8b_mux[] = {
462 P_PPI1_D0, P_PPI1_D1, P_PPI1_D2, P_PPI1_D3,
463 P_PPI1_D4, P_PPI1_D5, P_PPI1_D6, P_PPI1_D7,
464 P_PPI1_CLK, P_PPI1_FS1, P_PPI1_FS2,
465 0,
466};
467
468static const unsigned short ppi1_16b_mux[] = {
469 P_PPI1_D0, P_PPI1_D1, P_PPI1_D2, P_PPI1_D3,
470 P_PPI1_D4, P_PPI1_D5, P_PPI1_D6, P_PPI1_D7,
471 P_PPI1_D8, P_PPI1_D9, P_PPI1_D10, P_PPI1_D11,
472 P_PPI1_D12, P_PPI1_D13, P_PPI1_D14, P_PPI1_D15,
473 P_PPI1_CLK, P_PPI1_FS1, P_PPI1_FS2,
474 0,
475};
476
477static const unsigned short ppi2_8b_mux[] = {
478 P_PPI2_D0, P_PPI2_D1, P_PPI2_D2, P_PPI2_D3,
479 P_PPI2_D4, P_PPI2_D5, P_PPI2_D6, P_PPI2_D7,
480 P_PPI2_CLK, P_PPI2_FS1, P_PPI2_FS2,
481 0,
482};
483
484static const unsigned short atapi_mux[] = {
485 P_ATAPI_RESET, P_ATAPI_DIOR, P_ATAPI_DIOW, P_ATAPI_CS0, P_ATAPI_CS1,
486 P_ATAPI_DMACK, P_ATAPI_DMARQ, P_ATAPI_INTRQ, P_ATAPI_IORDY,
487};
488
489static const unsigned short atapi_alter_mux[] = {
490 P_ATAPI_D0A, P_ATAPI_D1A, P_ATAPI_D2A, P_ATAPI_D3A, P_ATAPI_D4A,
491 P_ATAPI_D5A, P_ATAPI_D6A, P_ATAPI_D7A, P_ATAPI_D8A, P_ATAPI_D9A,
492 P_ATAPI_D10A, P_ATAPI_D11A, P_ATAPI_D12A, P_ATAPI_D13A, P_ATAPI_D14A,
493 P_ATAPI_D15A, P_ATAPI_A0A, P_ATAPI_A1A, P_ATAPI_A2A,
494 0
495};
496
497static const unsigned short nfc0_mux[] = {
498 P_NAND_CE, P_NAND_RB,
499 0
500};
501
502static const unsigned short keys_4x4_mux[] = {
503 P_KEY_ROW3, P_KEY_ROW2, P_KEY_ROW1, P_KEY_ROW0,
504 P_KEY_COL3, P_KEY_COL2, P_KEY_COL1, P_KEY_COL0,
505 0
506};
507
508static const unsigned short keys_8x8_mux[] = {
509 P_KEY_ROW7, P_KEY_ROW6, P_KEY_ROW5, P_KEY_ROW4,
510 P_KEY_ROW3, P_KEY_ROW2, P_KEY_ROW1, P_KEY_ROW0,
511 P_KEY_COL7, P_KEY_COL6, P_KEY_COL5, P_KEY_COL4,
512 P_KEY_COL3, P_KEY_COL2, P_KEY_COL1, P_KEY_COL0,
513 0
514};
515
516static const char * const uart0grp[] = { "uart0grp" };
517static const char * const uart1grp[] = { "uart1grp" };
518static const char * const uart1ctsrtsgrp[] = { "uart1ctsrtsgrp" };
519static const char * const uart2grp[] = { "uart2grp" };
520static const char * const uart3grp[] = { "uart3grp" };
521static const char * const uart3ctsrtsgrp[] = { "uart3ctsrtsgrp" };
522static const char * const rsi0grp[] = { "rsi0grp" };
523static const char * const spi0grp[] = { "spi0grp" };
524static const char * const spi1grp[] = { "spi1grp" };
525static const char * const twi0grp[] = { "twi0grp" };
526static const char * const twi1grp[] = { "twi1grp" };
527static const char * const rotarygrp[] = { "rotarygrp" };
528static const char * const can0grp[] = { "can0grp" };
529static const char * const can1grp[] = { "can1grp" };
530static const char * const smc0grp[] = { "smc0grp" };
531static const char * const sport0grp[] = { "sport0grp" };
532static const char * const sport1grp[] = { "sport1grp" };
533static const char * const sport2grp[] = { "sport2grp" };
534static const char * const sport3grp[] = { "sport3grp" };
535static const char * const ppi0_8bgrp[] = { "ppi0_8bgrp" };
536static const char * const ppi0_16bgrp[] = { "ppi0_16bgrp" };
537static const char * const ppi0_24bgrp[] = { "ppi0_24bgrp" };
538static const char * const ppi1_8bgrp[] = { "ppi1_8bgrp" };
539static const char * const ppi1_16bgrp[] = { "ppi1_16bgrp" };
540static const char * const ppi2_8bgrp[] = { "ppi2_8bgrp" };
541static const char * const atapigrp[] = { "atapigrp" };
542static const char * const atapialtergrp[] = { "atapialtergrp" };
543static const char * const nfc0grp[] = { "nfc0grp" };
544static const char * const keys_4x4grp[] = { "keys_4x4grp" };
545static const char * const keys_8x8grp[] = { "keys_8x8grp" };
546
547static const struct adi_pmx_func adi_pmx_functions[] = {
548 ADI_PMX_FUNCTION("uart0", uart0grp, uart0_mux),
549 ADI_PMX_FUNCTION("uart1", uart1grp, uart1_mux),
550 ADI_PMX_FUNCTION("uart1_ctsrts", uart1ctsrtsgrp, uart1_ctsrts_mux),
551 ADI_PMX_FUNCTION("uart2", uart2grp, uart2_mux),
552 ADI_PMX_FUNCTION("uart3", uart3grp, uart3_mux),
553 ADI_PMX_FUNCTION("uart3_ctsrts", uart3ctsrtsgrp, uart3_ctsrts_mux),
554 ADI_PMX_FUNCTION("rsi0", rsi0grp, rsi0_mux),
555 ADI_PMX_FUNCTION("spi0", spi0grp, spi0_mux),
556 ADI_PMX_FUNCTION("spi1", spi1grp, spi1_mux),
557 ADI_PMX_FUNCTION("twi0", twi0grp, twi0_mux),
558 ADI_PMX_FUNCTION("twi1", twi1grp, twi1_mux),
559 ADI_PMX_FUNCTION("rotary", rotarygrp, rotary_mux),
560 ADI_PMX_FUNCTION("can0", can0grp, can0_mux),
561 ADI_PMX_FUNCTION("can1", can1grp, can1_mux),
562 ADI_PMX_FUNCTION("smc0", smc0grp, smc0_mux),
563 ADI_PMX_FUNCTION("sport0", sport0grp, sport0_mux),
564 ADI_PMX_FUNCTION("sport1", sport1grp, sport1_mux),
565 ADI_PMX_FUNCTION("sport2", sport2grp, sport2_mux),
566 ADI_PMX_FUNCTION("sport3", sport3grp, sport3_mux),
567 ADI_PMX_FUNCTION("ppi0_8b", ppi0_8bgrp, ppi0_8b_mux),
568 ADI_PMX_FUNCTION("ppi0_16b", ppi0_16bgrp, ppi0_16b_mux),
569 ADI_PMX_FUNCTION("ppi0_24b", ppi0_24bgrp, ppi0_24b_mux),
570 ADI_PMX_FUNCTION("ppi1_8b", ppi1_8bgrp, ppi1_8b_mux),
571 ADI_PMX_FUNCTION("ppi1_16b", ppi1_16bgrp, ppi1_16b_mux),
572 ADI_PMX_FUNCTION("ppi2_8b", ppi2_8bgrp, ppi2_8b_mux),
573 ADI_PMX_FUNCTION("atapi", atapigrp, atapi_mux),
574 ADI_PMX_FUNCTION("atapi_alter", atapialtergrp, atapi_alter_mux),
575 ADI_PMX_FUNCTION("nfc0", nfc0grp, nfc0_mux),
576 ADI_PMX_FUNCTION("keys_4x4", keys_4x4grp, keys_4x4_mux),
577 ADI_PMX_FUNCTION("keys_8x8", keys_8x8grp, keys_8x8_mux),
578};
579
580static const struct adi_pinctrl_soc_data adi_bf54x_soc = {
581 .functions = adi_pmx_functions,
582 .nfunctions = ARRAY_SIZE(adi_pmx_functions),
583 .groups = adi_pin_groups,
584 .ngroups = ARRAY_SIZE(adi_pin_groups),
585 .pins = adi_pads,
586 .npins = ARRAY_SIZE(adi_pads),
587};
588
589void adi_pinctrl_soc_init(const struct adi_pinctrl_soc_data **soc)
590{
591 *soc = &adi_bf54x_soc;
592}
diff --git a/drivers/pinctrl/pinctrl-adi2-bf60x.c b/drivers/pinctrl/pinctrl-adi2-bf60x.c
new file mode 100644
index 000000000000..bf57aea2826c
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-adi2-bf60x.c
@@ -0,0 +1,521 @@
1/*
2 * Pinctrl Driver for ADI GPIO2 controller
3 *
4 * Copyright 2007-2013 Analog Devices Inc.
5 *
6 * Licensed under the GPLv2 or later
7 */
8
9#include <asm/portmux.h>
10#include "pinctrl-adi2.h"
11
12static const struct pinctrl_pin_desc adi_pads[] = {
13 PINCTRL_PIN(0, "PA0"),
14 PINCTRL_PIN(1, "PA1"),
15 PINCTRL_PIN(2, "PA2"),
16 PINCTRL_PIN(3, "PG3"),
17 PINCTRL_PIN(4, "PA4"),
18 PINCTRL_PIN(5, "PA5"),
19 PINCTRL_PIN(6, "PA6"),
20 PINCTRL_PIN(7, "PA7"),
21 PINCTRL_PIN(8, "PA8"),
22 PINCTRL_PIN(9, "PA9"),
23 PINCTRL_PIN(10, "PA10"),
24 PINCTRL_PIN(11, "PA11"),
25 PINCTRL_PIN(12, "PA12"),
26 PINCTRL_PIN(13, "PA13"),
27 PINCTRL_PIN(14, "PA14"),
28 PINCTRL_PIN(15, "PA15"),
29 PINCTRL_PIN(16, "PB0"),
30 PINCTRL_PIN(17, "PB1"),
31 PINCTRL_PIN(18, "PB2"),
32 PINCTRL_PIN(19, "PB3"),
33 PINCTRL_PIN(20, "PB4"),
34 PINCTRL_PIN(21, "PB5"),
35 PINCTRL_PIN(22, "PB6"),
36 PINCTRL_PIN(23, "PB7"),
37 PINCTRL_PIN(24, "PB8"),
38 PINCTRL_PIN(25, "PB9"),
39 PINCTRL_PIN(26, "PB10"),
40 PINCTRL_PIN(27, "PB11"),
41 PINCTRL_PIN(28, "PB12"),
42 PINCTRL_PIN(29, "PB13"),
43 PINCTRL_PIN(30, "PB14"),
44 PINCTRL_PIN(31, "PB15"),
45 PINCTRL_PIN(32, "PC0"),
46 PINCTRL_PIN(33, "PC1"),
47 PINCTRL_PIN(34, "PC2"),
48 PINCTRL_PIN(35, "PC3"),
49 PINCTRL_PIN(36, "PC4"),
50 PINCTRL_PIN(37, "PC5"),
51 PINCTRL_PIN(38, "PC6"),
52 PINCTRL_PIN(39, "PC7"),
53 PINCTRL_PIN(40, "PC8"),
54 PINCTRL_PIN(41, "PC9"),
55 PINCTRL_PIN(42, "PC10"),
56 PINCTRL_PIN(43, "PC11"),
57 PINCTRL_PIN(44, "PC12"),
58 PINCTRL_PIN(45, "PC13"),
59 PINCTRL_PIN(46, "PC14"),
60 PINCTRL_PIN(47, "PC15"),
61 PINCTRL_PIN(48, "PD0"),
62 PINCTRL_PIN(49, "PD1"),
63 PINCTRL_PIN(50, "PD2"),
64 PINCTRL_PIN(51, "PD3"),
65 PINCTRL_PIN(52, "PD4"),
66 PINCTRL_PIN(53, "PD5"),
67 PINCTRL_PIN(54, "PD6"),
68 PINCTRL_PIN(55, "PD7"),
69 PINCTRL_PIN(56, "PD8"),
70 PINCTRL_PIN(57, "PD9"),
71 PINCTRL_PIN(58, "PD10"),
72 PINCTRL_PIN(59, "PD11"),
73 PINCTRL_PIN(60, "PD12"),
74 PINCTRL_PIN(61, "PD13"),
75 PINCTRL_PIN(62, "PD14"),
76 PINCTRL_PIN(63, "PD15"),
77 PINCTRL_PIN(64, "PE0"),
78 PINCTRL_PIN(65, "PE1"),
79 PINCTRL_PIN(66, "PE2"),
80 PINCTRL_PIN(67, "PE3"),
81 PINCTRL_PIN(68, "PE4"),
82 PINCTRL_PIN(69, "PE5"),
83 PINCTRL_PIN(70, "PE6"),
84 PINCTRL_PIN(71, "PE7"),
85 PINCTRL_PIN(72, "PE8"),
86 PINCTRL_PIN(73, "PE9"),
87 PINCTRL_PIN(74, "PE10"),
88 PINCTRL_PIN(75, "PE11"),
89 PINCTRL_PIN(76, "PE12"),
90 PINCTRL_PIN(77, "PE13"),
91 PINCTRL_PIN(78, "PE14"),
92 PINCTRL_PIN(79, "PE15"),
93 PINCTRL_PIN(80, "PF0"),
94 PINCTRL_PIN(81, "PF1"),
95 PINCTRL_PIN(82, "PF2"),
96 PINCTRL_PIN(83, "PF3"),
97 PINCTRL_PIN(84, "PF4"),
98 PINCTRL_PIN(85, "PF5"),
99 PINCTRL_PIN(86, "PF6"),
100 PINCTRL_PIN(87, "PF7"),
101 PINCTRL_PIN(88, "PF8"),
102 PINCTRL_PIN(89, "PF9"),
103 PINCTRL_PIN(90, "PF10"),
104 PINCTRL_PIN(91, "PF11"),
105 PINCTRL_PIN(92, "PF12"),
106 PINCTRL_PIN(93, "PF13"),
107 PINCTRL_PIN(94, "PF14"),
108 PINCTRL_PIN(95, "PF15"),
109 PINCTRL_PIN(96, "PG0"),
110 PINCTRL_PIN(97, "PG1"),
111 PINCTRL_PIN(98, "PG2"),
112 PINCTRL_PIN(99, "PG3"),
113 PINCTRL_PIN(100, "PG4"),
114 PINCTRL_PIN(101, "PG5"),
115 PINCTRL_PIN(102, "PG6"),
116 PINCTRL_PIN(103, "PG7"),
117 PINCTRL_PIN(104, "PG8"),
118 PINCTRL_PIN(105, "PG9"),
119 PINCTRL_PIN(106, "PG10"),
120 PINCTRL_PIN(107, "PG11"),
121 PINCTRL_PIN(108, "PG12"),
122 PINCTRL_PIN(109, "PG13"),
123 PINCTRL_PIN(110, "PG14"),
124 PINCTRL_PIN(111, "PG15"),
125};
126
127static const unsigned uart0_pins[] = {
128 GPIO_PD7, GPIO_PD8,
129};
130
131static const unsigned uart0_ctsrts_pins[] = {
132 GPIO_PD9, GPIO_PD10,
133};
134
135static const unsigned uart1_pins[] = {
136 GPIO_PG15, GPIO_PG14,
137};
138
139static const unsigned uart1_ctsrts_pins[] = {
140 GPIO_PG10, GPIO_PG13,
141};
142
143static const unsigned rsi0_pins[] = {
144 GPIO_PG3, GPIO_PG2, GPIO_PG0, GPIO_PE15, GPIO_PG5, GPIO_PG6,
145};
146
147static const unsigned eth0_pins[] = {
148 GPIO_PC6, GPIO_PC7, GPIO_PC2, GPIO_PC0, GPIO_PC3, GPIO_PC1,
149 GPIO_PB13, GPIO_PD6, GPIO_PC5, GPIO_PC4, GPIO_PB14, GPIO_PB15,
150};
151
152static const unsigned eth1_pins[] = {
153 GPIO_PE10, GPIO_PE11, GPIO_PG3, GPIO_PG0, GPIO_PG2, GPIO_PE15,
154 GPIO_PG5, GPIO_PE12, GPIO_PE13, GPIO_PE14, GPIO_PG6, GPIO_PC9,
155};
156
157static const unsigned spi0_pins[] = {
158 GPIO_PD4, GPIO_PD2, GPIO_PD3,
159};
160
161static const unsigned spi1_pins[] = {
162 GPIO_PD5, GPIO_PD14, GPIO_PD13,
163};
164
165static const unsigned twi0_pins[] = {
166};
167
168static const unsigned twi1_pins[] = {
169};
170
171static const unsigned rotary_pins[] = {
172 GPIO_PG7, GPIO_PG11, GPIO_PG12,
173};
174
175static const unsigned can0_pins[] = {
176 GPIO_PG1, GPIO_PG4,
177};
178
179static const unsigned smc0_pins[] = {
180 GPIO_PA0, GPIO_PA1, GPIO_PA2, GPIO_PA3, GPIO_PA4, GPIO_PA5, GPIO_PA6,
181 GPIO_PA7, GPIO_PA8, GPIO_PA9, GPIO_PB2, GPIO_PA10, GPIO_PA11,
182 GPIO_PB3, GPIO_PA12, GPIO_PA13, GPIO_PA14, GPIO_PA15, GPIO_PB6,
183 GPIO_PB7, GPIO_PB8, GPIO_PB10, GPIO_PB11, GPIO_PB0,
184};
185
186static const unsigned sport0_pins[] = {
187 GPIO_PB5, GPIO_PB4, GPIO_PB9, GPIO_PB8, GPIO_PB7, GPIO_PB11,
188};
189
190static const unsigned sport1_pins[] = {
191 GPIO_PE2, GPIO_PE5, GPIO_PD15, GPIO_PE4, GPIO_PE3, GPIO_PE1,
192};
193
194static const unsigned sport2_pins[] = {
195 GPIO_PG4, GPIO_PG1, GPIO_PG9, GPIO_PG10, GPIO_PG7, GPIO_PB12,
196};
197
198static const unsigned ppi0_8b_pins[] = {
199 GPIO_PF0, GPIO_PF1, GPIO_PF2, GPIO_PF3, GPIO_PF4, GPIO_PF5, GPIO_PF6,
200 GPIO_PF7, GPIO_PF13, GPIO_PF14, GPIO_PF15,
201 GPIO_PE6, GPIO_PE7, GPIO_PE8, GPIO_PE9,
202};
203
204static const unsigned ppi0_16b_pins[] = {
205 GPIO_PF0, GPIO_PF1, GPIO_PF2, GPIO_PF3, GPIO_PF4, GPIO_PF5, GPIO_PF6,
206 GPIO_PF7, GPIO_PF9, GPIO_PF10, GPIO_PF11, GPIO_PF12,
207 GPIO_PF13, GPIO_PF14, GPIO_PF15,
208 GPIO_PE6, GPIO_PE7, GPIO_PE8, GPIO_PE9,
209};
210
211static const unsigned ppi0_24b_pins[] = {
212 GPIO_PF0, GPIO_PF1, GPIO_PF2, GPIO_PF3, GPIO_PF4, GPIO_PF5, GPIO_PF6,
213 GPIO_PF7, GPIO_PF8, GPIO_PF9, GPIO_PF10, GPIO_PF11, GPIO_PF12,
214 GPIO_PF13, GPIO_PF14, GPIO_PF15, GPIO_PE0, GPIO_PE1, GPIO_PE2,
215 GPIO_PE3, GPIO_PE4, GPIO_PE5, GPIO_PE6, GPIO_PE7, GPIO_PE8,
216 GPIO_PE9, GPIO_PD12, GPIO_PD15,
217};
218
219static const unsigned ppi1_8b_pins[] = {
220 GPIO_PC0, GPIO_PC1, GPIO_PC2, GPIO_PC3, GPIO_PC4, GPIO_PC5, GPIO_PC6,
221 GPIO_PC7, GPIO_PC8, GPIO_PB13, GPIO_PB14, GPIO_PB15, GPIO_PD6,
222};
223
224static const unsigned ppi1_16b_pins[] = {
225 GPIO_PC0, GPIO_PC1, GPIO_PC2, GPIO_PC3, GPIO_PC4, GPIO_PC5, GPIO_PC6,
226 GPIO_PC7, GPIO_PC9, GPIO_PC10, GPIO_PC11, GPIO_PC12,
227 GPIO_PC13, GPIO_PC14, GPIO_PC15,
228 GPIO_PB13, GPIO_PB14, GPIO_PB15, GPIO_PD6,
229};
230
231static const unsigned ppi2_8b_pins[] = {
232 GPIO_PA0, GPIO_PA1, GPIO_PA2, GPIO_PA3, GPIO_PA4, GPIO_PA5, GPIO_PA6,
233 GPIO_PA7, GPIO_PB0, GPIO_PB1, GPIO_PB2, GPIO_PB3,
234};
235
236static const unsigned ppi2_16b_pins[] = {
237 GPIO_PA0, GPIO_PA1, GPIO_PA2, GPIO_PA3, GPIO_PA4, GPIO_PA5, GPIO_PA6,
238 GPIO_PA7, GPIO_PA8, GPIO_PA9, GPIO_PA10, GPIO_PA11, GPIO_PA12,
239 GPIO_PA13, GPIO_PA14, GPIO_PA15, GPIO_PB0, GPIO_PB1, GPIO_PB2,
240};
241
242static const unsigned lp0_pins[] = {
243 GPIO_PB0, GPIO_PB1, GPIO_PA0, GPIO_PA1, GPIO_PA2, GPIO_PA3,
244 GPIO_PA4, GPIO_PA5, GPIO_PA6, GPIO_PA7,
245};
246
247static const unsigned lp1_pins[] = {
248 GPIO_PB3, GPIO_PB2, GPIO_PA8, GPIO_PA9, GPIO_PA10, GPIO_PA11,
249 GPIO_PA12, GPIO_PA13, GPIO_PA14, GPIO_PA15,
250};
251
252static const unsigned lp2_pins[] = {
253 GPIO_PE6, GPIO_PE7, GPIO_PF0, GPIO_PF1, GPIO_PF2, GPIO_PF3,
254 GPIO_PF4, GPIO_PF5, GPIO_PF6, GPIO_PF7,
255};
256
257static const unsigned lp3_pins[] = {
258 GPIO_PE9, GPIO_PE8, GPIO_PF8, GPIO_PF9, GPIO_PF10, GPIO_PF11,
259 GPIO_PF12, GPIO_PF13, GPIO_PF14, GPIO_PF15,
260};
261
262static const struct adi_pin_group adi_pin_groups[] = {
263 ADI_PIN_GROUP("uart0grp", uart0_pins),
264 ADI_PIN_GROUP("uart0ctsrtsgrp", uart0_ctsrts_pins),
265 ADI_PIN_GROUP("uart1grp", uart1_pins),
266 ADI_PIN_GROUP("uart1ctsrtsgrp", uart1_ctsrts_pins),
267 ADI_PIN_GROUP("rsi0grp", rsi0_pins),
268 ADI_PIN_GROUP("eth0grp", eth0_pins),
269 ADI_PIN_GROUP("eth1grp", eth1_pins),
270 ADI_PIN_GROUP("spi0grp", spi0_pins),
271 ADI_PIN_GROUP("spi1grp", spi1_pins),
272 ADI_PIN_GROUP("twi0grp", twi0_pins),
273 ADI_PIN_GROUP("twi1grp", twi1_pins),
274 ADI_PIN_GROUP("rotarygrp", rotary_pins),
275 ADI_PIN_GROUP("can0grp", can0_pins),
276 ADI_PIN_GROUP("smc0grp", smc0_pins),
277 ADI_PIN_GROUP("sport0grp", sport0_pins),
278 ADI_PIN_GROUP("sport1grp", sport1_pins),
279 ADI_PIN_GROUP("sport2grp", sport2_pins),
280 ADI_PIN_GROUP("ppi0_8bgrp", ppi0_8b_pins),
281 ADI_PIN_GROUP("ppi0_16bgrp", ppi0_16b_pins),
282 ADI_PIN_GROUP("ppi0_24bgrp", ppi0_24b_pins),
283 ADI_PIN_GROUP("ppi1_8bgrp", ppi1_8b_pins),
284 ADI_PIN_GROUP("ppi1_16bgrp", ppi1_16b_pins),
285 ADI_PIN_GROUP("ppi2_8bgrp", ppi2_8b_pins),
286 ADI_PIN_GROUP("ppi2_16bgrp", ppi2_16b_pins),
287 ADI_PIN_GROUP("lp0grp", lp0_pins),
288 ADI_PIN_GROUP("lp1grp", lp1_pins),
289 ADI_PIN_GROUP("lp2grp", lp2_pins),
290 ADI_PIN_GROUP("lp3grp", lp3_pins),
291};
292
293static const unsigned short uart0_mux[] = {
294 P_UART0_TX, P_UART0_RX,
295 0
296};
297
298static const unsigned short uart0_ctsrts_mux[] = {
299 P_UART0_RTS, P_UART0_CTS,
300 0
301};
302
303static const unsigned short uart1_mux[] = {
304 P_UART1_TX, P_UART1_RX,
305 0
306};
307
308static const unsigned short uart1_ctsrts_mux[] = {
309 P_UART1_RTS, P_UART1_CTS,
310 0
311};
312
313static const unsigned short rsi0_mux[] = {
314 P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3,
315 P_RSI_CMD, P_RSI_CLK, 0
316};
317
318static const unsigned short eth0_mux[] = P_RMII0;
319static const unsigned short eth1_mux[] = P_RMII1;
320
321static const unsigned short spi0_mux[] = {
322 P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0
323};
324
325static const unsigned short spi1_mux[] = {
326 P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0
327};
328
329static const unsigned short twi0_mux[] = {
330 P_TWI0_SCL, P_TWI0_SDA, 0
331};
332
333static const unsigned short twi1_mux[] = {
334 P_TWI1_SCL, P_TWI1_SDA, 0
335};
336
337static const unsigned short rotary_mux[] = {
338 P_CNT_CUD, P_CNT_CDG, P_CNT_CZM, 0
339};
340
341static const unsigned short sport0_mux[] = {
342 P_SPORT0_ACLK, P_SPORT0_AFS, P_SPORT0_AD0, P_SPORT0_BCLK,
343 P_SPORT0_BFS, P_SPORT0_BD0, 0,
344};
345
346static const unsigned short sport1_mux[] = {
347 P_SPORT1_ACLK, P_SPORT1_AFS, P_SPORT1_AD0, P_SPORT1_BCLK,
348 P_SPORT1_BFS, P_SPORT1_BD0, 0,
349};
350
351static const unsigned short sport2_mux[] = {
352 P_SPORT2_ACLK, P_SPORT2_AFS, P_SPORT2_AD0, P_SPORT2_BCLK,
353 P_SPORT2_BFS, P_SPORT2_BD0, 0,
354};
355
356static const unsigned short can0_mux[] = {
357 P_CAN0_RX, P_CAN0_TX, 0
358};
359
360static const unsigned short smc0_mux[] = {
361 P_A3, P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12,
362 P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20, P_A21,
363 P_A22, P_A23, P_A24, P_A25, P_NORCK, 0,
364};
365
366static const unsigned short ppi0_8b_mux[] = {
367 P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
368 P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
369 P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
370 0,
371};
372
373static const unsigned short ppi0_16b_mux[] = {
374 P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
375 P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
376 P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
377 P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15,
378 P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
379 0,
380};
381
382static const unsigned short ppi0_24b_mux[] = {
383 P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
384 P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
385 P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
386 P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15,
387 P_PPI0_D16, P_PPI0_D17, P_PPI0_D18, P_PPI0_D19,
388 P_PPI0_D20, P_PPI0_D21, P_PPI0_D22, P_PPI0_D23,
389 P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
390 0,
391};
392
393static const unsigned short ppi1_8b_mux[] = {
394 P_PPI1_D0, P_PPI1_D1, P_PPI1_D2, P_PPI1_D3,
395 P_PPI1_D4, P_PPI1_D5, P_PPI1_D6, P_PPI1_D7,
396 P_PPI1_CLK, P_PPI1_FS1, P_PPI1_FS2,
397 0,
398};
399
400static const unsigned short ppi1_16b_mux[] = {
401 P_PPI1_D0, P_PPI1_D1, P_PPI1_D2, P_PPI1_D3,
402 P_PPI1_D4, P_PPI1_D5, P_PPI1_D6, P_PPI1_D7,
403 P_PPI1_D8, P_PPI1_D9, P_PPI1_D10, P_PPI1_D11,
404 P_PPI1_D12, P_PPI1_D13, P_PPI1_D14, P_PPI1_D15,
405 P_PPI1_CLK, P_PPI1_FS1, P_PPI1_FS2,
406 0,
407};
408
409static const unsigned short ppi2_8b_mux[] = {
410 P_PPI2_D0, P_PPI2_D1, P_PPI2_D2, P_PPI2_D3,
411 P_PPI2_D4, P_PPI2_D5, P_PPI2_D6, P_PPI2_D7,
412 P_PPI2_CLK, P_PPI2_FS1, P_PPI2_FS2,
413 0,
414};
415
416static const unsigned short ppi2_16b_mux[] = {
417 P_PPI2_D0, P_PPI2_D1, P_PPI2_D2, P_PPI2_D3,
418 P_PPI2_D4, P_PPI2_D5, P_PPI2_D6, P_PPI2_D7,
419 P_PPI2_D8, P_PPI2_D9, P_PPI2_D10, P_PPI2_D11,
420 P_PPI2_D12, P_PPI2_D13, P_PPI2_D14, P_PPI2_D15,
421 P_PPI2_CLK, P_PPI2_FS1, P_PPI2_FS2,
422 0,
423};
424
425static const unsigned short lp0_mux[] = {
426 P_LP0_CLK, P_LP0_ACK, P_LP0_D0, P_LP0_D1, P_LP0_D2,
427 P_LP0_D3, P_LP0_D4, P_LP0_D5, P_LP0_D6, P_LP0_D7,
428 0
429};
430
431static const unsigned short lp1_mux[] = {
432 P_LP1_CLK, P_LP1_ACK, P_LP1_D0, P_LP1_D1, P_LP1_D2,
433 P_LP1_D3, P_LP1_D4, P_LP1_D5, P_LP1_D6, P_LP1_D7,
434 0
435};
436
437static const unsigned short lp2_mux[] = {
438 P_LP2_CLK, P_LP2_ACK, P_LP2_D0, P_LP2_D1, P_LP2_D2,
439 P_LP2_D3, P_LP2_D4, P_LP2_D5, P_LP2_D6, P_LP2_D7,
440 0
441};
442
443static const unsigned short lp3_mux[] = {
444 P_LP3_CLK, P_LP3_ACK, P_LP3_D0, P_LP3_D1, P_LP3_D2,
445 P_LP3_D3, P_LP3_D4, P_LP3_D5, P_LP3_D6, P_LP3_D7,
446 0
447};
448
449static const char * const uart0grp[] = { "uart0grp" };
450static const char * const uart0ctsrtsgrp[] = { "uart0ctsrtsgrp" };
451static const char * const uart1grp[] = { "uart1grp" };
452static const char * const uart1ctsrtsgrp[] = { "uart1ctsrtsgrp" };
453static const char * const rsi0grp[] = { "rsi0grp" };
454static const char * const eth0grp[] = { "eth0grp" };
455static const char * const eth1grp[] = { "eth1grp" };
456static const char * const spi0grp[] = { "spi0grp" };
457static const char * const spi1grp[] = { "spi1grp" };
458static const char * const twi0grp[] = { "twi0grp" };
459static const char * const twi1grp[] = { "twi1grp" };
460static const char * const rotarygrp[] = { "rotarygrp" };
461static const char * const can0grp[] = { "can0grp" };
462static const char * const smc0grp[] = { "smc0grp" };
463static const char * const sport0grp[] = { "sport0grp" };
464static const char * const sport1grp[] = { "sport1grp" };
465static const char * const sport2grp[] = { "sport2grp" };
466static const char * const ppi0_8bgrp[] = { "ppi0_8bgrp" };
467static const char * const ppi0_16bgrp[] = { "ppi0_16bgrp" };
468static const char * const ppi0_24bgrp[] = { "ppi0_24bgrp" };
469static const char * const ppi1_8bgrp[] = { "ppi1_8bgrp" };
470static const char * const ppi1_16bgrp[] = { "ppi1_16bgrp" };
471static const char * const ppi2_8bgrp[] = { "ppi2_8bgrp" };
472static const char * const ppi2_16bgrp[] = { "ppi2_16bgrp" };
473static const char * const lp0grp[] = { "lp0grp" };
474static const char * const lp1grp[] = { "lp1grp" };
475static const char * const lp2grp[] = { "lp2grp" };
476static const char * const lp3grp[] = { "lp3grp" };
477
478static const struct adi_pmx_func adi_pmx_functions[] = {
479 ADI_PMX_FUNCTION("uart0", uart0grp, uart0_mux),
480 ADI_PMX_FUNCTION("uart0_ctsrts", uart0ctsrtsgrp, uart0_ctsrts_mux),
481 ADI_PMX_FUNCTION("uart1", uart1grp, uart1_mux),
482 ADI_PMX_FUNCTION("uart1_ctsrts", uart1ctsrtsgrp, uart1_ctsrts_mux),
483 ADI_PMX_FUNCTION("rsi0", rsi0grp, rsi0_mux),
484 ADI_PMX_FUNCTION("eth0", eth0grp, eth0_mux),
485 ADI_PMX_FUNCTION("eth1", eth1grp, eth1_mux),
486 ADI_PMX_FUNCTION("spi0", spi0grp, spi0_mux),
487 ADI_PMX_FUNCTION("spi1", spi1grp, spi1_mux),
488 ADI_PMX_FUNCTION("twi0", twi0grp, twi0_mux),
489 ADI_PMX_FUNCTION("twi1", twi1grp, twi1_mux),
490 ADI_PMX_FUNCTION("rotary", rotarygrp, rotary_mux),
491 ADI_PMX_FUNCTION("can0", can0grp, can0_mux),
492 ADI_PMX_FUNCTION("smc0", smc0grp, smc0_mux),
493 ADI_PMX_FUNCTION("sport0", sport0grp, sport0_mux),
494 ADI_PMX_FUNCTION("sport1", sport1grp, sport1_mux),
495 ADI_PMX_FUNCTION("sport2", sport2grp, sport2_mux),
496 ADI_PMX_FUNCTION("ppi0_8b", ppi0_8bgrp, ppi0_8b_mux),
497 ADI_PMX_FUNCTION("ppi0_16b", ppi0_16bgrp, ppi0_16b_mux),
498 ADI_PMX_FUNCTION("ppi0_24b", ppi0_24bgrp, ppi0_24b_mux),
499 ADI_PMX_FUNCTION("ppi1_8b", ppi1_8bgrp, ppi1_8b_mux),
500 ADI_PMX_FUNCTION("ppi1_16b", ppi1_16bgrp, ppi1_16b_mux),
501 ADI_PMX_FUNCTION("ppi2_8b", ppi2_8bgrp, ppi2_8b_mux),
502 ADI_PMX_FUNCTION("ppi2_16b", ppi2_16bgrp, ppi2_16b_mux),
503 ADI_PMX_FUNCTION("lp0", lp0grp, lp0_mux),
504 ADI_PMX_FUNCTION("lp1", lp1grp, lp1_mux),
505 ADI_PMX_FUNCTION("lp2", lp2grp, lp2_mux),
506 ADI_PMX_FUNCTION("lp3", lp3grp, lp3_mux),
507};
508
509static const struct adi_pinctrl_soc_data adi_bf60x_soc = {
510 .functions = adi_pmx_functions,
511 .nfunctions = ARRAY_SIZE(adi_pmx_functions),
512 .groups = adi_pin_groups,
513 .ngroups = ARRAY_SIZE(adi_pin_groups),
514 .pins = adi_pads,
515 .npins = ARRAY_SIZE(adi_pads),
516};
517
518void adi_pinctrl_soc_init(const struct adi_pinctrl_soc_data **soc)
519{
520 *soc = &adi_bf60x_soc;
521}
diff --git a/drivers/pinctrl/pinctrl-adi2.c b/drivers/pinctrl/pinctrl-adi2.c
new file mode 100644
index 000000000000..8089fda00427
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-adi2.c
@@ -0,0 +1,1158 @@
1/*
2 * Pinctrl Driver for ADI GPIO2 controller
3 *
4 * Copyright 2007-2013 Analog Devices Inc.
5 *
6 * Licensed under the GPLv2 or later
7 */
8
9#include <linux/bitops.h>
10#include <linux/delay.h>
11#include <linux/module.h>
12#include <linux/err.h>
13#include <linux/debugfs.h>
14#include <linux/seq_file.h>
15#include <linux/irq.h>
16#include <linux/platform_data/pinctrl-adi2.h>
17#include <linux/irqdomain.h>
18#include <linux/irqchip/chained_irq.h>
19#include <linux/pinctrl/pinctrl.h>
20#include <linux/pinctrl/pinmux.h>
21#include <linux/pinctrl/consumer.h>
22#include <linux/pinctrl/machine.h>
23#include <linux/syscore_ops.h>
24#include <linux/gpio.h>
25#include <asm/portmux.h>
26#include "pinctrl-adi2.h"
27#include "core.h"
28
29/*
30According to the BF54x HRM, pint means "pin interrupt".
31http://www.analog.com/static/imported-files/processor_manuals/ADSP-BF54x_hwr_rev1.2.pdf
32
33ADSP-BF54x processor Blackfin processors have four SIC interrupt chan-
34nels dedicated to pin interrupt purposes. These channels are managed by
35four hardware blocks, called PINT0, PINT1, PINT2, and PINT3. Every PINTx
36block can sense to up to 32 pins. While PINT0 and PINT1 can sense the
37pins of port A and port B, PINT2 and PINT3 manage all the pins from port
38C to port J as shown in Figure 9-2.
39
40n BF54x HRM:
41The ten GPIO ports are subdivided into 8-bit half ports, resulting in lower and
42upper half 8-bit units. The PINTx_ASSIGN registers control the 8-bit multi-
43plexers shown in Figure 9-3. Lower half units of eight pins can be
44forwarded to either byte 0 or byte 2 of either associated PINTx block.
45Upper half units can be forwarded to either byte 1 or byte 3 of the pin
46interrupt blocks, without further restrictions.
47
48All MMR registers in the pin interrupt module are 32 bits wide. To simply the
49mapping logic, this driver only maps a 16-bit gpio port to the upper or lower
5016 bits of a PINTx block. You can find the Figure 9-3 on page 583.
51
52Each IRQ domain is binding to a GPIO bank device. 2 GPIO bank devices can map
53to one PINT device. Two in "struct gpio_pint" are used to ease the PINT
54interrupt handler.
55
56The GPIO bank mapping to the lower 16 bits of the PINT device set its IRQ
57domain pointer in domain[0]. The IRQ domain pointer of the other bank is set
58to domain[1]. PINT interrupt handler adi_gpio_handle_pint_irq() finds out
59the current domain pointer according to whether the interrupt request mask
60is in lower 16 bits (domain[0]) or upper 16bits (domain[1]).
61
62A PINT device is not part of a GPIO port device in Blackfin. Multiple GPIO
63port devices can be mapped to the same PINT device.
64
65*/
66
67static LIST_HEAD(adi_pint_list);
68static LIST_HEAD(adi_gpio_port_list);
69
70#define DRIVER_NAME "pinctrl-adi2"
71
72#define PINT_HI_OFFSET 16
73
74/**
75 * struct gpio_port_saved - GPIO port registers that should be saved between
76 * power suspend and resume operations.
77 *
78 * @fer: PORTx_FER register
79 * @data: PORTx_DATA register
80 * @dir: PORTx_DIR register
81 * @inen: PORTx_INEN register
82 * @mux: PORTx_MUX register
83 */
84struct gpio_port_saved {
85 u16 fer;
86 u16 data;
87 u16 dir;
88 u16 inen;
89 u32 mux;
90};
91
92/**
93 * struct gpio_pint - Pin interrupt controller device. Multiple ADI GPIO
94 * banks can be mapped into one Pin interrupt controller.
95 *
96 * @node: All gpio_pint instances are added to a global list.
97 * @base: PINT device register base address
98 * @irq: IRQ of the PINT device, it is the parent IRQ of all
99 * GPIO IRQs mapping to this device.
100 * @domain: [0] irq domain of the gpio port, whose hardware interrupts are
101 * mapping to the low 16-bit of the pint registers.
102 * [1] irq domain of the gpio port, whose hardware interrupts are
103 * mapping to the high 16-bit of the pint registers.
104 * @regs: address pointer to the PINT device
105 * @map_count: No more than 2 GPIO banks can be mapped to this PINT device.
106 * @lock: This lock make sure the irq_chip operations to one PINT device
107 * for different GPIO interrrupts are atomic.
108 * @pint_map_port: Set up the mapping between one PINT device and
109 * multiple GPIO banks.
110 */
111struct gpio_pint {
112 struct list_head node;
113 void __iomem *base;
114 int irq;
115 struct irq_domain *domain[2];
116 struct gpio_pint_regs *regs;
117 struct adi_pm_pint_save saved_data;
118 int map_count;
119 spinlock_t lock;
120
121 int (*pint_map_port)(struct gpio_pint *pint, bool assign,
122 u8 map, struct irq_domain *domain);
123};
124
125/**
126 * ADI pin controller
127 *
128 * @dev: a pointer back to containing device
129 * @pctl: the pinctrl device
130 * @soc: SoC data for this specific chip
131 */
132struct adi_pinctrl {
133 struct device *dev;
134 struct pinctrl_dev *pctl;
135 const struct adi_pinctrl_soc_data *soc;
136};
137
138/**
139 * struct gpio_port - GPIO bank device. Multiple ADI GPIO banks can be mapped
140 * into one pin interrupt controller.
141 *
142 * @node: All gpio_port instances are added to a list.
143 * @base: GPIO bank device register base address
144 * @irq_base: base IRQ of the GPIO bank device
145 * @width: PIN number of the GPIO bank device
146 * @regs: address pointer to the GPIO bank device
147 * @saved_data: registers that should be saved between PM operations.
148 * @dev: device structure of this GPIO bank
149 * @pint: GPIO PINT device that this GPIO bank mapped to
150 * @pint_map: GIOP bank mapping code in PINT device
151 * @pint_assign: The 32-bit PINT registers can be divided into 2 parts. A
152 * GPIO bank can be mapped into either low 16 bits[0] or high 16
153 * bits[1] of each PINT register.
154 * @lock: This lock make sure the irq_chip operations to one PINT device
155 * for different GPIO interrrupts are atomic.
156 * @chip: abstract a GPIO controller
157 * @domain: The irq domain owned by the GPIO port.
158 * @rsvmap: Reservation map array for each pin in the GPIO bank
159 */
160struct gpio_port {
161 struct list_head node;
162 void __iomem *base;
163 unsigned int irq_base;
164 unsigned int width;
165 struct gpio_port_t *regs;
166 struct gpio_port_saved saved_data;
167 struct device *dev;
168
169 struct gpio_pint *pint;
170 u8 pint_map;
171 bool pint_assign;
172
173 spinlock_t lock;
174 struct gpio_chip chip;
175 struct irq_domain *domain;
176};
177
178static inline u8 pin_to_offset(struct pinctrl_gpio_range *range, unsigned pin)
179{
180 return pin - range->pin_base;
181}
182
183static inline u32 hwirq_to_pintbit(struct gpio_port *port, int hwirq)
184{
185 return port->pint_assign ? BIT(hwirq) << PINT_HI_OFFSET : BIT(hwirq);
186}
187
188static struct gpio_pint *find_gpio_pint(unsigned id)
189{
190 struct gpio_pint *pint;
191 int i = 0;
192
193 list_for_each_entry(pint, &adi_pint_list, node) {
194 if (id == i)
195 return pint;
196 i++;
197 }
198
199 return NULL;
200}
201
202static inline void port_setup(struct gpio_port *port, unsigned offset,
203 bool use_for_gpio)
204{
205 struct gpio_port_t *regs = port->regs;
206
207 if (use_for_gpio)
208 writew(readw(&regs->port_fer) & ~BIT(offset),
209 &regs->port_fer);
210 else
211 writew(readw(&regs->port_fer) | BIT(offset), &regs->port_fer);
212}
213
214static inline void portmux_setup(struct gpio_port *port, unsigned offset,
215 unsigned short function)
216{
217 struct gpio_port_t *regs = port->regs;
218 u32 pmux;
219
220 pmux = readl(&regs->port_mux);
221
222 /* The function field of each pin has 2 consecutive bits in
223 * the mux register.
224 */
225 pmux &= ~(0x3 << (2 * offset));
226 pmux |= (function & 0x3) << (2 * offset);
227
228 writel(pmux, &regs->port_mux);
229}
230
231static inline u16 get_portmux(struct gpio_port *port, unsigned offset)
232{
233 struct gpio_port_t *regs = port->regs;
234 u32 pmux = readl(&regs->port_mux);
235
236 /* The function field of each pin has 2 consecutive bits in
237 * the mux register.
238 */
239 return pmux >> (2 * offset) & 0x3;
240}
241
242static void adi_gpio_ack_irq(struct irq_data *d)
243{
244 unsigned long flags;
245 struct gpio_port *port = irq_data_get_irq_chip_data(d);
246 struct gpio_pint_regs *regs = port->pint->regs;
247 unsigned pintbit = hwirq_to_pintbit(port, d->hwirq);
248
249 spin_lock_irqsave(&port->lock, flags);
250 spin_lock_irqsave(&port->pint->lock, flags);
251
252 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
253 if (readl(&regs->invert_set) & pintbit)
254 writel(pintbit, &regs->invert_clear);
255 else
256 writel(pintbit, &regs->invert_set);
257 }
258
259 writel(pintbit, &regs->request);
260
261 spin_unlock_irqrestore(&port->pint->lock, flags);
262 spin_unlock_irqrestore(&port->lock, flags);
263}
264
265static void adi_gpio_mask_ack_irq(struct irq_data *d)
266{
267 unsigned long flags;
268 struct gpio_port *port = irq_data_get_irq_chip_data(d);
269 struct gpio_pint_regs *regs = port->pint->regs;
270 unsigned pintbit = hwirq_to_pintbit(port, d->hwirq);
271
272 spin_lock_irqsave(&port->lock, flags);
273 spin_lock_irqsave(&port->pint->lock, flags);
274
275 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
276 if (readl(&regs->invert_set) & pintbit)
277 writel(pintbit, &regs->invert_clear);
278 else
279 writel(pintbit, &regs->invert_set);
280 }
281
282 writel(pintbit, &regs->request);
283 writel(pintbit, &regs->mask_clear);
284
285 spin_unlock_irqrestore(&port->pint->lock, flags);
286 spin_unlock_irqrestore(&port->lock, flags);
287}
288
289static void adi_gpio_mask_irq(struct irq_data *d)
290{
291 unsigned long flags;
292 struct gpio_port *port = irq_data_get_irq_chip_data(d);
293 struct gpio_pint_regs *regs = port->pint->regs;
294
295 spin_lock_irqsave(&port->lock, flags);
296 spin_lock_irqsave(&port->pint->lock, flags);
297
298 writel(hwirq_to_pintbit(port, d->hwirq), &regs->mask_clear);
299
300 spin_unlock_irqrestore(&port->pint->lock, flags);
301 spin_unlock_irqrestore(&port->lock, flags);
302}
303
304static void adi_gpio_unmask_irq(struct irq_data *d)
305{
306 unsigned long flags;
307 struct gpio_port *port = irq_data_get_irq_chip_data(d);
308 struct gpio_pint_regs *regs = port->pint->regs;
309
310 spin_lock_irqsave(&port->lock, flags);
311 spin_lock_irqsave(&port->pint->lock, flags);
312
313 writel(hwirq_to_pintbit(port, d->hwirq), &regs->mask_set);
314
315 spin_unlock_irqrestore(&port->pint->lock, flags);
316 spin_unlock_irqrestore(&port->lock, flags);
317}
318
319static unsigned int adi_gpio_irq_startup(struct irq_data *d)
320{
321 unsigned long flags;
322 struct gpio_port *port = irq_data_get_irq_chip_data(d);
323 struct gpio_pint_regs *regs = port->pint->regs;
324
325 if (!port) {
326 dev_err(port->dev, "GPIO IRQ %d :Not exist\n", d->irq);
327 return -ENODEV;
328 }
329
330 spin_lock_irqsave(&port->lock, flags);
331 spin_lock_irqsave(&port->pint->lock, flags);
332
333 port_setup(port, d->hwirq, true);
334 writew(BIT(d->hwirq), &port->regs->dir_clear);
335 writew(readw(&port->regs->inen) | BIT(d->hwirq), &port->regs->inen);
336
337 writel(hwirq_to_pintbit(port, d->hwirq), &regs->mask_set);
338
339 spin_unlock_irqrestore(&port->pint->lock, flags);
340 spin_unlock_irqrestore(&port->lock, flags);
341
342 return 0;
343}
344
345static void adi_gpio_irq_shutdown(struct irq_data *d)
346{
347 unsigned long flags;
348 struct gpio_port *port = irq_data_get_irq_chip_data(d);
349 struct gpio_pint_regs *regs = port->pint->regs;
350
351 spin_lock_irqsave(&port->lock, flags);
352 spin_lock_irqsave(&port->pint->lock, flags);
353
354 writel(hwirq_to_pintbit(port, d->hwirq), &regs->mask_clear);
355
356 spin_unlock_irqrestore(&port->pint->lock, flags);
357 spin_unlock_irqrestore(&port->lock, flags);
358}
359
360static int adi_gpio_irq_type(struct irq_data *d, unsigned int type)
361{
362 unsigned long flags;
363 struct gpio_port *port = irq_data_get_irq_chip_data(d);
364 struct gpio_pint_regs *pint_regs = port->pint->regs;
365 unsigned pintmask;
366 unsigned int irq = d->irq;
367 int ret = 0;
368 char buf[16];
369
370 if (!port) {
371 dev_err(port->dev, "GPIO IRQ %d :Not exist\n", irq);
372 return -ENODEV;
373 }
374
375 pintmask = hwirq_to_pintbit(port, d->hwirq);
376
377 spin_lock_irqsave(&port->lock, flags);
378 spin_lock_irqsave(&port->pint->lock, flags);
379
380 /* In case of interrupt autodetect, set irq type to edge sensitive. */
381 if (type == IRQ_TYPE_PROBE)
382 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
383
384 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
385 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
386 snprintf(buf, 16, "gpio-irq%d", irq);
387 port_setup(port, d->hwirq, true);
388 } else
389 goto out;
390
391 /* The GPIO interrupt is triggered only when its input value
392 * transfer from 0 to 1. So, invert the input value if the
393 * irq type is low or falling
394 */
395 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
396 writel(pintmask, &pint_regs->invert_set);
397 else
398 writel(pintmask, &pint_regs->invert_clear);
399
400 /* In edge sensitive case, if the input value of the requested irq
401 * is already 1, invert it.
402 */
403 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
404 if (gpio_get_value(port->chip.base + d->hwirq))
405 writel(pintmask, &pint_regs->invert_set);
406 else
407 writel(pintmask, &pint_regs->invert_clear);
408 }
409
410 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
411 writel(pintmask, &pint_regs->edge_set);
412 __irq_set_handler_locked(irq, handle_edge_irq);
413 } else {
414 writel(pintmask, &pint_regs->edge_clear);
415 __irq_set_handler_locked(irq, handle_level_irq);
416 }
417
418out:
419 spin_unlock_irqrestore(&port->pint->lock, flags);
420 spin_unlock_irqrestore(&port->lock, flags);
421
422 return ret;
423}
424
425#ifdef CONFIG_PM
426static int adi_gpio_set_wake(struct irq_data *d, unsigned int state)
427{
428 struct gpio_port *port = irq_data_get_irq_chip_data(d);
429
430 if (!port || !port->pint || port->pint->irq != d->irq)
431 return -EINVAL;
432
433#ifndef SEC_GCTL
434 adi_internal_set_wake(port->pint->irq, state);
435#endif
436
437 return 0;
438}
439
440static int adi_pint_suspend(void)
441{
442 struct gpio_pint *pint;
443
444 list_for_each_entry(pint, &adi_pint_list, node) {
445 writel(0xffffffff, &pint->regs->mask_clear);
446 pint->saved_data.assign = readl(&pint->regs->assign);
447 pint->saved_data.edge_set = readl(&pint->regs->edge_set);
448 pint->saved_data.invert_set = readl(&pint->regs->invert_set);
449 }
450
451 return 0;
452}
453
454static void adi_pint_resume(void)
455{
456 struct gpio_pint *pint;
457
458 list_for_each_entry(pint, &adi_pint_list, node) {
459 writel(pint->saved_data.assign, &pint->regs->assign);
460 writel(pint->saved_data.edge_set, &pint->regs->edge_set);
461 writel(pint->saved_data.invert_set, &pint->regs->invert_set);
462 }
463}
464
465static int adi_gpio_suspend(void)
466{
467 struct gpio_port *port;
468
469 list_for_each_entry(port, &adi_gpio_port_list, node) {
470 port->saved_data.fer = readw(&port->regs->port_fer);
471 port->saved_data.mux = readl(&port->regs->port_mux);
472 port->saved_data.data = readw(&port->regs->data);
473 port->saved_data.inen = readw(&port->regs->inen);
474 port->saved_data.dir = readw(&port->regs->dir_set);
475 }
476
477 return adi_pint_suspend();
478}
479
480static void adi_gpio_resume(void)
481{
482 struct gpio_port *port;
483
484 adi_pint_resume();
485
486 list_for_each_entry(port, &adi_gpio_port_list, node) {
487 writel(port->saved_data.mux, &port->regs->port_mux);
488 writew(port->saved_data.fer, &port->regs->port_fer);
489 writew(port->saved_data.inen, &port->regs->inen);
490 writew(port->saved_data.data & port->saved_data.dir,
491 &port->regs->data_set);
492 writew(port->saved_data.dir, &port->regs->dir_set);
493 }
494
495}
496
497static struct syscore_ops gpio_pm_syscore_ops = {
498 .suspend = adi_gpio_suspend,
499 .resume = adi_gpio_resume,
500};
501#else /* CONFIG_PM */
502#define adi_gpio_set_wake NULL
503#endif /* CONFIG_PM */
504
505#ifdef CONFIG_IRQ_PREFLOW_FASTEOI
506static inline void preflow_handler(struct irq_desc *desc)
507{
508 if (desc->preflow_handler)
509 desc->preflow_handler(&desc->irq_data);
510}
511#else
512static inline void preflow_handler(struct irq_desc *desc) { }
513#endif
514
515static void adi_gpio_handle_pint_irq(unsigned int inta_irq,
516 struct irq_desc *desc)
517{
518 u32 request;
519 u32 level_mask, hwirq;
520 bool umask = false;
521 struct gpio_pint *pint = irq_desc_get_handler_data(desc);
522 struct irq_chip *chip = irq_desc_get_chip(desc);
523 struct gpio_pint_regs *regs = pint->regs;
524 struct irq_domain *domain;
525
526 preflow_handler(desc);
527 chained_irq_enter(chip, desc);
528
529 request = readl(&regs->request);
530 level_mask = readl(&regs->edge_set) & request;
531
532 hwirq = 0;
533 domain = pint->domain[0];
534 while (request) {
535 /* domain pointer need to be changed only once at IRQ 16 when
536 * we go through IRQ requests from bit 0 to bit 31.
537 */
538 if (hwirq == PINT_HI_OFFSET)
539 domain = pint->domain[1];
540
541 if (request & 1) {
542 if (level_mask & BIT(hwirq)) {
543 umask = true;
544 chained_irq_exit(chip, desc);
545 }
546 generic_handle_irq(irq_find_mapping(domain,
547 hwirq % PINT_HI_OFFSET));
548 }
549
550 hwirq++;
551 request >>= 1;
552 }
553
554 if (!umask)
555 chained_irq_exit(chip, desc);
556}
557
558static struct irq_chip adi_gpio_irqchip = {
559 .name = "GPIO",
560 .irq_ack = adi_gpio_ack_irq,
561 .irq_mask = adi_gpio_mask_irq,
562 .irq_mask_ack = adi_gpio_mask_ack_irq,
563 .irq_unmask = adi_gpio_unmask_irq,
564 .irq_disable = adi_gpio_mask_irq,
565 .irq_enable = adi_gpio_unmask_irq,
566 .irq_set_type = adi_gpio_irq_type,
567 .irq_startup = adi_gpio_irq_startup,
568 .irq_shutdown = adi_gpio_irq_shutdown,
569 .irq_set_wake = adi_gpio_set_wake,
570};
571
572static int adi_get_groups_count(struct pinctrl_dev *pctldev)
573{
574 struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
575
576 return pinctrl->soc->ngroups;
577}
578
579static const char *adi_get_group_name(struct pinctrl_dev *pctldev,
580 unsigned selector)
581{
582 struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
583
584 return pinctrl->soc->groups[selector].name;
585}
586
587static int adi_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
588 const unsigned **pins,
589 unsigned *num_pins)
590{
591 struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
592
593 *pins = pinctrl->soc->groups[selector].pins;
594 *num_pins = pinctrl->soc->groups[selector].num;
595 return 0;
596}
597
598static struct pinctrl_ops adi_pctrl_ops = {
599 .get_groups_count = adi_get_groups_count,
600 .get_group_name = adi_get_group_name,
601 .get_group_pins = adi_get_group_pins,
602};
603
604static int adi_pinmux_enable(struct pinctrl_dev *pctldev, unsigned selector,
605 unsigned group)
606{
607 struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
608 struct gpio_port *port;
609 struct pinctrl_gpio_range *range;
610 unsigned long flags;
611 unsigned short *mux, pin;
612
613 mux = (unsigned short *)pinctrl->soc->functions[selector].mux;
614
615 while (*mux) {
616 pin = P_IDENT(*mux);
617
618 range = pinctrl_find_gpio_range_from_pin(pctldev, pin);
619 if (range == NULL) /* should not happen */
620 return -ENODEV;
621
622 port = container_of(range->gc, struct gpio_port, chip);
623
624 spin_lock_irqsave(&port->lock, flags);
625
626 portmux_setup(port, pin_to_offset(range, pin),
627 P_FUNCT2MUX(*mux));
628 port_setup(port, pin_to_offset(range, pin), false);
629 mux++;
630
631 spin_unlock_irqrestore(&port->lock, flags);
632 }
633
634 return 0;
635}
636
637static void adi_pinmux_disable(struct pinctrl_dev *pctldev, unsigned selector,
638 unsigned group)
639{
640 struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
641 struct gpio_port *port;
642 struct pinctrl_gpio_range *range;
643 unsigned long flags;
644 unsigned short *mux, pin;
645
646 mux = (unsigned short *)pinctrl->soc->functions[selector].mux;
647
648 while (*mux) {
649 pin = P_IDENT(*mux);
650
651 range = pinctrl_find_gpio_range_from_pin(pctldev, pin);
652 if (range == NULL) /* should not happen */
653 return;
654
655 port = container_of(range->gc, struct gpio_port, chip);
656
657 spin_lock_irqsave(&port->lock, flags);
658
659 port_setup(port, pin_to_offset(range, pin), true);
660 mux++;
661
662 spin_unlock_irqrestore(&port->lock, flags);
663 }
664}
665
666static int adi_pinmux_get_funcs_count(struct pinctrl_dev *pctldev)
667{
668 struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
669
670 return pinctrl->soc->nfunctions;
671}
672
673static const char *adi_pinmux_get_func_name(struct pinctrl_dev *pctldev,
674 unsigned selector)
675{
676 struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
677
678 return pinctrl->soc->functions[selector].name;
679}
680
681static int adi_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
682 const char * const **groups,
683 unsigned * const num_groups)
684{
685 struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
686
687 *groups = pinctrl->soc->functions[selector].groups;
688 *num_groups = pinctrl->soc->functions[selector].num_groups;
689 return 0;
690}
691
692static int adi_pinmux_request_gpio(struct pinctrl_dev *pctldev,
693 struct pinctrl_gpio_range *range, unsigned pin)
694{
695 struct gpio_port *port;
696 unsigned long flags;
697 u8 offset;
698
699 port = container_of(range->gc, struct gpio_port, chip);
700 offset = pin_to_offset(range, pin);
701
702 spin_lock_irqsave(&port->lock, flags);
703
704 port_setup(port, offset, true);
705
706 spin_unlock_irqrestore(&port->lock, flags);
707
708 return 0;
709}
710
711static struct pinmux_ops adi_pinmux_ops = {
712 .enable = adi_pinmux_enable,
713 .disable = adi_pinmux_disable,
714 .get_functions_count = adi_pinmux_get_funcs_count,
715 .get_function_name = adi_pinmux_get_func_name,
716 .get_function_groups = adi_pinmux_get_groups,
717 .gpio_request_enable = adi_pinmux_request_gpio,
718};
719
720
721static struct pinctrl_desc adi_pinmux_desc = {
722 .name = DRIVER_NAME,
723 .pctlops = &adi_pctrl_ops,
724 .pmxops = &adi_pinmux_ops,
725 .owner = THIS_MODULE,
726};
727
728static int adi_gpio_request(struct gpio_chip *chip, unsigned offset)
729{
730 return pinctrl_request_gpio(chip->base + offset);
731}
732
733static void adi_gpio_free(struct gpio_chip *chip, unsigned offset)
734{
735 pinctrl_free_gpio(chip->base + offset);
736}
737
738static int adi_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
739{
740 struct gpio_port *port;
741 unsigned long flags;
742
743 port = container_of(chip, struct gpio_port, chip);
744
745 spin_lock_irqsave(&port->lock, flags);
746
747 writew(BIT(offset), &port->regs->dir_clear);
748 writew(readw(&port->regs->inen) | BIT(offset), &port->regs->inen);
749
750 spin_unlock_irqrestore(&port->lock, flags);
751
752 return 0;
753}
754
755static void adi_gpio_set_value(struct gpio_chip *chip, unsigned offset,
756 int value)
757{
758 struct gpio_port *port = container_of(chip, struct gpio_port, chip);
759 struct gpio_port_t *regs = port->regs;
760 unsigned long flags;
761
762 spin_lock_irqsave(&port->lock, flags);
763
764 if (value)
765 writew(1 << offset, &regs->data_set);
766 else
767 writew(1 << offset, &regs->data_clear);
768
769 spin_unlock_irqrestore(&port->lock, flags);
770}
771
772static int adi_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
773 int value)
774{
775 struct gpio_port *port = container_of(chip, struct gpio_port, chip);
776 struct gpio_port_t *regs = port->regs;
777 unsigned long flags;
778
779 adi_gpio_set_value(chip, offset, value);
780
781 spin_lock_irqsave(&port->lock, flags);
782
783 writew(readw(&regs->inen) & ~(1 << offset), &regs->inen);
784 writew(1 << offset, &regs->dir_set);
785
786 spin_unlock_irqrestore(&port->lock, flags);
787
788 return 0;
789}
790
791static int adi_gpio_get_value(struct gpio_chip *chip, unsigned offset)
792{
793 struct gpio_port *port = container_of(chip, struct gpio_port, chip);
794 struct gpio_port_t *regs = port->regs;
795 unsigned long flags;
796 int ret;
797
798 spin_lock_irqsave(&port->lock, flags);
799
800 ret = !!(readw(&regs->data) & BIT(offset));
801
802 spin_unlock_irqrestore(&port->lock, flags);
803
804 return ret;
805}
806
807static int adi_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
808{
809 struct gpio_port *port = container_of(chip, struct gpio_port, chip);
810
811 if (port->irq_base >= 0)
812 return irq_find_mapping(port->domain, offset);
813 else
814 return irq_create_mapping(port->domain, offset);
815}
816
817static int adi_pint_map_port(struct gpio_pint *pint, bool assign, u8 map,
818 struct irq_domain *domain)
819{
820 struct gpio_pint_regs *regs = pint->regs;
821 u32 map_mask;
822
823 if (pint->map_count > 1)
824 return -EINVAL;
825
826 pint->map_count++;
827
828 /* The map_mask of each gpio port is a 16-bit duplicate
829 * of the 8-bit map. It can be set to either high 16 bits or low
830 * 16 bits of the pint assignment register.
831 */
832 map_mask = (map << 8) | map;
833 if (assign) {
834 map_mask <<= PINT_HI_OFFSET;
835 writel((readl(&regs->assign) & 0xFFFF) | map_mask,
836 &regs->assign);
837 } else
838 writel((readl(&regs->assign) & 0xFFFF0000) | map_mask,
839 &regs->assign);
840
841 pint->domain[assign] = domain;
842
843 return 0;
844}
845
846static int adi_gpio_pint_probe(struct platform_device *pdev)
847{
848 struct device *dev = &pdev->dev;
849 struct resource *res;
850 struct gpio_pint *pint;
851
852 pint = devm_kzalloc(dev, sizeof(struct gpio_pint), GFP_KERNEL);
853 if (!pint) {
854 dev_err(dev, "Memory alloc failed\n");
855 return -ENOMEM;
856 }
857
858 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
859 pint->base = devm_ioremap_resource(dev, res);
860 if (IS_ERR(pint->base))
861 return PTR_ERR(pint->base);
862
863 pint->regs = (struct gpio_pint_regs *)pint->base;
864
865 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
866 if (!res) {
867 dev_err(dev, "Invalid IRQ resource\n");
868 return -ENODEV;
869 }
870
871 spin_lock_init(&pint->lock);
872
873 pint->irq = res->start;
874 pint->pint_map_port = adi_pint_map_port;
875 platform_set_drvdata(pdev, pint);
876
877 irq_set_chained_handler(pint->irq, adi_gpio_handle_pint_irq);
878 irq_set_handler_data(pint->irq, pint);
879
880 list_add_tail(&pint->node, &adi_pint_list);
881
882 return 0;
883}
884
885static int adi_gpio_pint_remove(struct platform_device *pdev)
886{
887 struct gpio_pint *pint = platform_get_drvdata(pdev);
888
889 list_del(&pint->node);
890 irq_set_handler(pint->irq, handle_simple_irq);
891
892 return 0;
893}
894
895static int adi_gpio_irq_map(struct irq_domain *d, unsigned int irq,
896 irq_hw_number_t hwirq)
897{
898 struct gpio_port *port = d->host_data;
899
900 if (!port)
901 return -EINVAL;
902
903 irq_set_chip_data(irq, port);
904 irq_set_chip_and_handler(irq, &adi_gpio_irqchip,
905 handle_level_irq);
906
907 return 0;
908}
909
910const struct irq_domain_ops adi_gpio_irq_domain_ops = {
911 .map = adi_gpio_irq_map,
912 .xlate = irq_domain_xlate_onecell,
913};
914
915static int adi_gpio_init_int(struct gpio_port *port)
916{
917 struct device_node *node = port->dev->of_node;
918 struct gpio_pint *pint = port->pint;
919 int ret;
920
921 port->domain = irq_domain_add_linear(node, port->width,
922 &adi_gpio_irq_domain_ops, port);
923 if (!port->domain) {
924 dev_err(port->dev, "Failed to create irqdomain\n");
925 return -ENOSYS;
926 }
927
928 /* According to BF54x and BF60x HRM, pin interrupt devices are not
929 * part of the GPIO port device. in GPIO interrupt mode, the GPIO
930 * pins of multiple port devices can be routed into one pin interrupt
931 * device. The mapping can be configured by setting pint assignment
932 * register with the mapping value of different GPIO port. This is
933 * done via function pint_map_port().
934 */
935 ret = pint->pint_map_port(port->pint, port->pint_assign,
936 port->pint_map, port->domain);
937 if (ret)
938 return ret;
939
940 if (port->irq_base >= 0) {
941 ret = irq_create_strict_mappings(port->domain, port->irq_base,
942 0, port->width);
943 if (ret) {
944 dev_err(port->dev, "Couldn't associate to domain\n");
945 return ret;
946 }
947 }
948
949 return 0;
950}
951
952#define DEVNAME_SIZE 16
953
954static int adi_gpio_probe(struct platform_device *pdev)
955{
956 struct device *dev = &pdev->dev;
957 const struct adi_pinctrl_gpio_platform_data *pdata;
958 struct resource *res;
959 struct gpio_port *port;
960 char pinctrl_devname[DEVNAME_SIZE];
961 static int gpio;
962 int ret = 0, ret1;
963
964 pdata = dev->platform_data;
965 if (!pdata)
966 return -EINVAL;
967
968 port = devm_kzalloc(dev, sizeof(struct gpio_port), GFP_KERNEL);
969 if (!port) {
970 dev_err(dev, "Memory alloc failed\n");
971 return -ENOMEM;
972 }
973
974 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
975 port->base = devm_ioremap_resource(dev, res);
976 if (IS_ERR(port->base))
977 return PTR_ERR(port->base);
978
979 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
980 if (!res)
981 port->irq_base = -1;
982 else
983 port->irq_base = res->start;
984
985 port->width = pdata->port_width;
986 port->dev = dev;
987 port->regs = (struct gpio_port_t *)port->base;
988 port->pint_assign = pdata->pint_assign;
989 port->pint_map = pdata->pint_map;
990
991 port->pint = find_gpio_pint(pdata->pint_id);
992 if (port->pint) {
993 ret = adi_gpio_init_int(port);
994 if (ret)
995 return ret;
996 }
997
998 spin_lock_init(&port->lock);
999
1000 platform_set_drvdata(pdev, port);
1001
1002 port->chip.label = "adi-gpio";
1003 port->chip.direction_input = adi_gpio_direction_input;
1004 port->chip.get = adi_gpio_get_value;
1005 port->chip.direction_output = adi_gpio_direction_output;
1006 port->chip.set = adi_gpio_set_value;
1007 port->chip.request = adi_gpio_request;
1008 port->chip.free = adi_gpio_free;
1009 port->chip.to_irq = adi_gpio_to_irq;
1010 if (pdata->port_gpio_base > 0)
1011 port->chip.base = pdata->port_gpio_base;
1012 else
1013 port->chip.base = gpio;
1014 port->chip.ngpio = port->width;
1015 gpio = port->chip.base + port->width;
1016
1017 ret = gpiochip_add(&port->chip);
1018 if (ret) {
1019 dev_err(&pdev->dev, "Fail to add GPIO chip.\n");
1020 goto out_remove_domain;
1021 }
1022
1023 /* Add gpio pin range */
1024 snprintf(pinctrl_devname, DEVNAME_SIZE, "pinctrl-adi2.%d",
1025 pdata->pinctrl_id);
1026 pinctrl_devname[DEVNAME_SIZE - 1] = 0;
1027 ret = gpiochip_add_pin_range(&port->chip, pinctrl_devname,
1028 0, pdata->port_pin_base, port->width);
1029 if (ret) {
1030 dev_err(&pdev->dev, "Fail to add pin range to %s.\n",
1031 pinctrl_devname);
1032 goto out_remove_gpiochip;
1033 }
1034
1035 list_add_tail(&port->node, &adi_gpio_port_list);
1036
1037 return 0;
1038
1039out_remove_gpiochip:
1040 ret1 = gpiochip_remove(&port->chip);
1041out_remove_domain:
1042 if (port->pint)
1043 irq_domain_remove(port->domain);
1044
1045 return ret;
1046}
1047
1048static int adi_gpio_remove(struct platform_device *pdev)
1049{
1050 struct gpio_port *port = platform_get_drvdata(pdev);
1051 int ret;
1052 u8 offset;
1053
1054 list_del(&port->node);
1055 gpiochip_remove_pin_ranges(&port->chip);
1056 ret = gpiochip_remove(&port->chip);
1057 if (port->pint) {
1058 for (offset = 0; offset < port->width; offset++)
1059 irq_dispose_mapping(irq_find_mapping(port->domain,
1060 offset));
1061 irq_domain_remove(port->domain);
1062 }
1063
1064 return ret;
1065}
1066
1067static int adi_pinctrl_probe(struct platform_device *pdev)
1068{
1069 struct adi_pinctrl *pinctrl;
1070
1071 pinctrl = devm_kzalloc(&pdev->dev, sizeof(*pinctrl), GFP_KERNEL);
1072 if (!pinctrl)
1073 return -ENOMEM;
1074
1075 pinctrl->dev = &pdev->dev;
1076
1077 adi_pinctrl_soc_init(&pinctrl->soc);
1078
1079 adi_pinmux_desc.pins = pinctrl->soc->pins;
1080 adi_pinmux_desc.npins = pinctrl->soc->npins;
1081
1082 /* Now register the pin controller and all pins it handles */
1083 pinctrl->pctl = pinctrl_register(&adi_pinmux_desc, &pdev->dev, pinctrl);
1084 if (!pinctrl->pctl) {
1085 dev_err(&pdev->dev, "could not register pinctrl ADI2 driver\n");
1086 return -EINVAL;
1087 }
1088
1089 platform_set_drvdata(pdev, pinctrl);
1090
1091 return 0;
1092}
1093
1094static int adi_pinctrl_remove(struct platform_device *pdev)
1095{
1096 struct adi_pinctrl *pinctrl = platform_get_drvdata(pdev);
1097
1098 pinctrl_unregister(pinctrl->pctl);
1099
1100 return 0;
1101}
1102
1103static struct platform_driver adi_pinctrl_driver = {
1104 .probe = adi_pinctrl_probe,
1105 .remove = adi_pinctrl_remove,
1106 .driver = {
1107 .name = DRIVER_NAME,
1108 },
1109};
1110
1111static struct platform_driver adi_gpio_pint_driver = {
1112 .probe = adi_gpio_pint_probe,
1113 .remove = adi_gpio_pint_remove,
1114 .driver = {
1115 .name = "adi-gpio-pint",
1116 },
1117};
1118
1119static struct platform_driver adi_gpio_driver = {
1120 .probe = adi_gpio_probe,
1121 .remove = adi_gpio_remove,
1122 .driver = {
1123 .name = "adi-gpio",
1124 },
1125};
1126
1127static int __init adi_pinctrl_setup(void)
1128{
1129 int ret;
1130
1131 ret = platform_driver_register(&adi_pinctrl_driver);
1132 if (ret)
1133 return ret;
1134
1135 ret = platform_driver_register(&adi_gpio_pint_driver);
1136 if (ret)
1137 goto pint_error;
1138
1139 ret = platform_driver_register(&adi_gpio_driver);
1140 if (ret)
1141 goto gpio_error;
1142
1143#ifdef CONFIG_PM
1144 register_syscore_ops(&gpio_pm_syscore_ops);
1145#endif
1146 return ret;
1147gpio_error:
1148 platform_driver_unregister(&adi_gpio_pint_driver);
1149pint_error:
1150 platform_driver_unregister(&adi_pinctrl_driver);
1151
1152 return ret;
1153}
1154arch_initcall(adi_pinctrl_setup);
1155
1156MODULE_AUTHOR("Sonic Zhang <sonic.zhang@analog.com>");
1157MODULE_DESCRIPTION("ADI gpio2 pin control driver");
1158MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/pinctrl-adi2.h b/drivers/pinctrl/pinctrl-adi2.h
new file mode 100644
index 000000000000..1f06f8df1fa3
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-adi2.h
@@ -0,0 +1,75 @@
1/*
2 * Pinctrl Driver for ADI GPIO2 controller
3 *
4 * Copyright 2007-2013 Analog Devices Inc.
5 *
6 * Licensed under the GPLv2 or later
7 */
8
9#ifndef PINCTRL_PINCTRL_ADI2_H
10#define PINCTRL_PINCTRL_ADI2_H
11
12#include <linux/pinctrl/pinctrl.h>
13
14 /**
15 * struct adi_pin_group - describes a pin group
16 * @name: the name of this pin group
17 * @pins: an array of pins
18 * @num: the number of pins in this array
19 */
20struct adi_pin_group {
21 const char *name;
22 const unsigned *pins;
23 const unsigned num;
24};
25
26#define ADI_PIN_GROUP(n, p) \
27 { \
28 .name = n, \
29 .pins = p, \
30 .num = ARRAY_SIZE(p), \
31 }
32
33 /**
34 * struct adi_pmx_func - describes function mux setting of pin groups
35 * @name: the name of this function mux setting
36 * @groups: an array of pin groups
37 * @num_groups: the number of pin groups in this array
38 * @mux: the function mux setting array, end by zero
39 */
40struct adi_pmx_func {
41 const char *name;
42 const char * const *groups;
43 const unsigned num_groups;
44 const unsigned short *mux;
45};
46
47#define ADI_PMX_FUNCTION(n, g, m) \
48 { \
49 .name = n, \
50 .groups = g, \
51 .num_groups = ARRAY_SIZE(g), \
52 .mux = m, \
53 }
54
55/**
56 * struct adi_pinctrl_soc_data - ADI pin controller per-SoC configuration
57 * @functions: The functions supported on this SoC.
58 * @nfunction: The number of entries in @functions.
59 * @groups: An array describing all pin groups the pin SoC supports.
60 * @ngroups: The number of entries in @groups.
61 * @pins: An array describing all pins the pin controller affects.
62 * @npins: The number of entries in @pins.
63 */
64struct adi_pinctrl_soc_data {
65 const struct adi_pmx_func *functions;
66 int nfunctions;
67 const struct adi_pin_group *groups;
68 int ngroups;
69 const struct pinctrl_pin_desc *pins;
70 int npins;
71};
72
73void adi_pinctrl_soc_init(const struct adi_pinctrl_soc_data **soc);
74
75#endif /* PINCTRL_PINCTRL_ADI2_H */
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index f350fd2e170e..0c8bf9318aed 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -144,11 +144,11 @@ struct at91_pinctrl_mux_ops {
144 void (*mux_C_periph)(void __iomem *pio, unsigned mask); 144 void (*mux_C_periph)(void __iomem *pio, unsigned mask);
145 void (*mux_D_periph)(void __iomem *pio, unsigned mask); 145 void (*mux_D_periph)(void __iomem *pio, unsigned mask);
146 bool (*get_deglitch)(void __iomem *pio, unsigned pin); 146 bool (*get_deglitch)(void __iomem *pio, unsigned pin);
147 void (*set_deglitch)(void __iomem *pio, unsigned mask, bool in_on); 147 void (*set_deglitch)(void __iomem *pio, unsigned mask, bool is_on);
148 bool (*get_debounce)(void __iomem *pio, unsigned pin, u32 *div); 148 bool (*get_debounce)(void __iomem *pio, unsigned pin, u32 *div);
149 void (*set_debounce)(void __iomem *pio, unsigned mask, bool in_on, u32 div); 149 void (*set_debounce)(void __iomem *pio, unsigned mask, bool is_on, u32 div);
150 bool (*get_pulldown)(void __iomem *pio, unsigned pin); 150 bool (*get_pulldown)(void __iomem *pio, unsigned pin);
151 void (*set_pulldown)(void __iomem *pio, unsigned mask, bool in_on); 151 void (*set_pulldown)(void __iomem *pio, unsigned mask, bool is_on);
152 bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin); 152 bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin);
153 void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask); 153 void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask);
154 /* irq */ 154 /* irq */
@@ -417,6 +417,14 @@ static void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
417 __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR)); 417 __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
418} 418}
419 419
420static bool at91_mux_pio3_get_deglitch(void __iomem *pio, unsigned pin)
421{
422 if ((__raw_readl(pio + PIO_IFSR) >> pin) & 0x1)
423 return !((__raw_readl(pio + PIO_IFSCSR) >> pin) & 0x1);
424
425 return false;
426}
427
420static void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on) 428static void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
421{ 429{
422 if (is_on) 430 if (is_on)
@@ -428,7 +436,8 @@ static bool at91_mux_pio3_get_debounce(void __iomem *pio, unsigned pin, u32 *div
428{ 436{
429 *div = __raw_readl(pio + PIO_SCDR); 437 *div = __raw_readl(pio + PIO_SCDR);
430 438
431 return (__raw_readl(pio + PIO_IFSCSR) >> pin) & 0x1; 439 return ((__raw_readl(pio + PIO_IFSR) >> pin) & 0x1) &&
440 ((__raw_readl(pio + PIO_IFSCSR) >> pin) & 0x1);
432} 441}
433 442
434static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask, 443static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask,
@@ -438,9 +447,8 @@ static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask,
438 __raw_writel(mask, pio + PIO_IFSCER); 447 __raw_writel(mask, pio + PIO_IFSCER);
439 __raw_writel(div & PIO_SCDR_DIV, pio + PIO_SCDR); 448 __raw_writel(div & PIO_SCDR_DIV, pio + PIO_SCDR);
440 __raw_writel(mask, pio + PIO_IFER); 449 __raw_writel(mask, pio + PIO_IFER);
441 } else { 450 } else
442 __raw_writel(mask, pio + PIO_IFDR); 451 __raw_writel(mask, pio + PIO_IFSCDR);
443 }
444} 452}
445 453
446static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin) 454static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin)
@@ -478,7 +486,7 @@ static struct at91_pinctrl_mux_ops at91sam9x5_ops = {
478 .mux_B_periph = at91_mux_pio3_set_B_periph, 486 .mux_B_periph = at91_mux_pio3_set_B_periph,
479 .mux_C_periph = at91_mux_pio3_set_C_periph, 487 .mux_C_periph = at91_mux_pio3_set_C_periph,
480 .mux_D_periph = at91_mux_pio3_set_D_periph, 488 .mux_D_periph = at91_mux_pio3_set_D_periph,
481 .get_deglitch = at91_mux_get_deglitch, 489 .get_deglitch = at91_mux_pio3_get_deglitch,
482 .set_deglitch = at91_mux_pio3_set_deglitch, 490 .set_deglitch = at91_mux_pio3_set_deglitch,
483 .get_debounce = at91_mux_pio3_get_debounce, 491 .get_debounce = at91_mux_pio3_get_debounce,
484 .set_debounce = at91_mux_pio3_set_debounce, 492 .set_debounce = at91_mux_pio3_set_debounce,
@@ -1671,7 +1679,7 @@ static struct platform_driver at91_gpio_driver = {
1671 .driver = { 1679 .driver = {
1672 .name = "gpio-at91", 1680 .name = "gpio-at91",
1673 .owner = THIS_MODULE, 1681 .owner = THIS_MODULE,
1674 .of_match_table = of_match_ptr(at91_gpio_of_match), 1682 .of_match_table = at91_gpio_of_match,
1675 }, 1683 },
1676 .probe = at91_gpio_probe, 1684 .probe = at91_gpio_probe,
1677}; 1685};
@@ -1680,7 +1688,7 @@ static struct platform_driver at91_pinctrl_driver = {
1680 .driver = { 1688 .driver = {
1681 .name = "pinctrl-at91", 1689 .name = "pinctrl-at91",
1682 .owner = THIS_MODULE, 1690 .owner = THIS_MODULE,
1683 .of_match_table = of_match_ptr(at91_pinctrl_of_match), 1691 .of_match_table = at91_pinctrl_of_match,
1684 }, 1692 },
1685 .probe = at91_pinctrl_probe, 1693 .probe = at91_pinctrl_probe,
1686 .remove = at91_pinctrl_remove, 1694 .remove = at91_pinctrl_remove,
diff --git a/drivers/pinctrl/pinctrl-exynos5440.c b/drivers/pinctrl/pinctrl-exynos5440.c
index 544d469c5a7b..8fe2ab0a7698 100644
--- a/drivers/pinctrl/pinctrl-exynos5440.c
+++ b/drivers/pinctrl/pinctrl-exynos5440.c
@@ -1048,7 +1048,7 @@ static struct platform_driver exynos5440_pinctrl_driver = {
1048 .driver = { 1048 .driver = {
1049 .name = "exynos5440-pinctrl", 1049 .name = "exynos5440-pinctrl",
1050 .owner = THIS_MODULE, 1050 .owner = THIS_MODULE,
1051 .of_match_table = of_match_ptr(exynos5440_pinctrl_dt_match), 1051 .of_match_table = exynos5440_pinctrl_dt_match,
1052 }, 1052 },
1053}; 1053};
1054 1054
diff --git a/drivers/pinctrl/pinctrl-imx35.c b/drivers/pinctrl/pinctrl-imx35.c
index c4549829fc47..278a04ae8940 100644
--- a/drivers/pinctrl/pinctrl-imx35.c
+++ b/drivers/pinctrl/pinctrl-imx35.c
@@ -1019,7 +1019,7 @@ static struct platform_driver imx35_pinctrl_driver = {
1019 .driver = { 1019 .driver = {
1020 .name = "imx35-pinctrl", 1020 .name = "imx35-pinctrl",
1021 .owner = THIS_MODULE, 1021 .owner = THIS_MODULE,
1022 .of_match_table = of_match_ptr(imx35_pinctrl_of_match), 1022 .of_match_table = imx35_pinctrl_of_match,
1023 }, 1023 },
1024 .probe = imx35_pinctrl_probe, 1024 .probe = imx35_pinctrl_probe,
1025 .remove = imx_pinctrl_remove, 1025 .remove = imx_pinctrl_remove,
diff --git a/drivers/pinctrl/pinctrl-imx51.c b/drivers/pinctrl/pinctrl-imx51.c
index db268b920079..19ab182bef61 100644
--- a/drivers/pinctrl/pinctrl-imx51.c
+++ b/drivers/pinctrl/pinctrl-imx51.c
@@ -782,7 +782,7 @@ static struct platform_driver imx51_pinctrl_driver = {
782 .driver = { 782 .driver = {
783 .name = "imx51-pinctrl", 783 .name = "imx51-pinctrl",
784 .owner = THIS_MODULE, 784 .owner = THIS_MODULE,
785 .of_match_table = of_match_ptr(imx51_pinctrl_of_match), 785 .of_match_table = imx51_pinctrl_of_match,
786 }, 786 },
787 .probe = imx51_pinctrl_probe, 787 .probe = imx51_pinctrl_probe,
788 .remove = imx_pinctrl_remove, 788 .remove = imx_pinctrl_remove,
diff --git a/drivers/pinctrl/pinctrl-imx53.c b/drivers/pinctrl/pinctrl-imx53.c
index 17562ae9005c..f8d45c4cfde7 100644
--- a/drivers/pinctrl/pinctrl-imx53.c
+++ b/drivers/pinctrl/pinctrl-imx53.c
@@ -468,7 +468,7 @@ static struct platform_driver imx53_pinctrl_driver = {
468 .driver = { 468 .driver = {
469 .name = "imx53-pinctrl", 469 .name = "imx53-pinctrl",
470 .owner = THIS_MODULE, 470 .owner = THIS_MODULE,
471 .of_match_table = of_match_ptr(imx53_pinctrl_of_match), 471 .of_match_table = imx53_pinctrl_of_match,
472 }, 472 },
473 .probe = imx53_pinctrl_probe, 473 .probe = imx53_pinctrl_probe,
474 .remove = imx_pinctrl_remove, 474 .remove = imx_pinctrl_remove,
diff --git a/drivers/pinctrl/pinctrl-imx6dl.c b/drivers/pinctrl/pinctrl-imx6dl.c
index a76b72427936..db2a1489bd99 100644
--- a/drivers/pinctrl/pinctrl-imx6dl.c
+++ b/drivers/pinctrl/pinctrl-imx6dl.c
@@ -474,7 +474,7 @@ static struct platform_driver imx6dl_pinctrl_driver = {
474 .driver = { 474 .driver = {
475 .name = "imx6dl-pinctrl", 475 .name = "imx6dl-pinctrl",
476 .owner = THIS_MODULE, 476 .owner = THIS_MODULE,
477 .of_match_table = of_match_ptr(imx6dl_pinctrl_of_match), 477 .of_match_table = imx6dl_pinctrl_of_match,
478 }, 478 },
479 .probe = imx6dl_pinctrl_probe, 479 .probe = imx6dl_pinctrl_probe,
480 .remove = imx_pinctrl_remove, 480 .remove = imx_pinctrl_remove,
diff --git a/drivers/pinctrl/pinctrl-imx6q.c b/drivers/pinctrl/pinctrl-imx6q.c
index 76dd9c4949f4..8eb5ac1bd5f6 100644
--- a/drivers/pinctrl/pinctrl-imx6q.c
+++ b/drivers/pinctrl/pinctrl-imx6q.c
@@ -480,7 +480,7 @@ static struct platform_driver imx6q_pinctrl_driver = {
480 .driver = { 480 .driver = {
481 .name = "imx6q-pinctrl", 481 .name = "imx6q-pinctrl",
482 .owner = THIS_MODULE, 482 .owner = THIS_MODULE,
483 .of_match_table = of_match_ptr(imx6q_pinctrl_of_match), 483 .of_match_table = imx6q_pinctrl_of_match,
484 }, 484 },
485 .probe = imx6q_pinctrl_probe, 485 .probe = imx6q_pinctrl_probe,
486 .remove = imx_pinctrl_remove, 486 .remove = imx_pinctrl_remove,
diff --git a/drivers/pinctrl/pinctrl-imx6sl.c b/drivers/pinctrl/pinctrl-imx6sl.c
index 4eb7ccab5f2d..f21b7389df3c 100644
--- a/drivers/pinctrl/pinctrl-imx6sl.c
+++ b/drivers/pinctrl/pinctrl-imx6sl.c
@@ -380,7 +380,7 @@ static struct platform_driver imx6sl_pinctrl_driver = {
380 .driver = { 380 .driver = {
381 .name = "imx6sl-pinctrl", 381 .name = "imx6sl-pinctrl",
382 .owner = THIS_MODULE, 382 .owner = THIS_MODULE,
383 .of_match_table = of_match_ptr(imx6sl_pinctrl_of_match), 383 .of_match_table = imx6sl_pinctrl_of_match,
384 }, 384 },
385 .probe = imx6sl_pinctrl_probe, 385 .probe = imx6sl_pinctrl_probe,
386 .remove = imx_pinctrl_remove, 386 .remove = imx_pinctrl_remove,
diff --git a/drivers/pinctrl/pinctrl-palmas.c b/drivers/pinctrl/pinctrl-palmas.c
index 30c4d356cb33..61643815e73e 100644
--- a/drivers/pinctrl/pinctrl-palmas.c
+++ b/drivers/pinctrl/pinctrl-palmas.c
@@ -962,26 +962,9 @@ static int palmas_pinconf_set(struct pinctrl_dev *pctldev,
962 return 0; 962 return 0;
963} 963}
964 964
965static int palmas_pinconf_group_get(struct pinctrl_dev *pctldev,
966 unsigned group, unsigned long *config)
967{
968 dev_err(pctldev->dev, "palmas_pinconf_group_get op not supported\n");
969 return -ENOTSUPP;
970}
971
972static int palmas_pinconf_group_set(struct pinctrl_dev *pctldev,
973 unsigned group, unsigned long *configs,
974 unsigned num_configs)
975{
976 dev_err(pctldev->dev, "palmas_pinconf_group_set op not supported\n");
977 return -ENOTSUPP;
978}
979
980static const struct pinconf_ops palmas_pinconf_ops = { 965static const struct pinconf_ops palmas_pinconf_ops = {
981 .pin_config_get = palmas_pinconf_get, 966 .pin_config_get = palmas_pinconf_get,
982 .pin_config_set = palmas_pinconf_set, 967 .pin_config_set = palmas_pinconf_set,
983 .pin_config_group_get = palmas_pinconf_group_get,
984 .pin_config_group_set = palmas_pinconf_group_set,
985}; 968};
986 969
987static struct pinctrl_desc palmas_pinctrl_desc = { 970static struct pinctrl_desc palmas_pinctrl_desc = {
diff --git a/drivers/pinctrl/pinctrl-samsung.c b/drivers/pinctrl/pinctrl-samsung.c
index 92a9d6c8db0a..47ec2e8741e4 100644
--- a/drivers/pinctrl/pinctrl-samsung.c
+++ b/drivers/pinctrl/pinctrl-samsung.c
@@ -1148,7 +1148,7 @@ static struct platform_driver samsung_pinctrl_driver = {
1148 .driver = { 1148 .driver = {
1149 .name = "samsung-pinctrl", 1149 .name = "samsung-pinctrl",
1150 .owner = THIS_MODULE, 1150 .owner = THIS_MODULE,
1151 .of_match_table = of_match_ptr(samsung_pinctrl_dt_match), 1151 .of_match_table = samsung_pinctrl_dt_match,
1152 }, 1152 },
1153}; 1153};
1154 1154
diff --git a/drivers/pinctrl/pinctrl-vf610.c b/drivers/pinctrl/pinctrl-vf610.c
index 68a970b1dbcf..bddd913d28ba 100644
--- a/drivers/pinctrl/pinctrl-vf610.c
+++ b/drivers/pinctrl/pinctrl-vf610.c
@@ -316,7 +316,7 @@ static struct platform_driver vf610_pinctrl_driver = {
316 .driver = { 316 .driver = {
317 .name = "vf610-pinctrl", 317 .name = "vf610-pinctrl",
318 .owner = THIS_MODULE, 318 .owner = THIS_MODULE,
319 .of_match_table = of_match_ptr(vf610_pinctrl_of_match), 319 .of_match_table = vf610_pinctrl_of_match,
320 }, 320 },
321 .probe = vf610_pinctrl_probe, 321 .probe = vf610_pinctrl_probe,
322 .remove = imx_pinctrl_remove, 322 .remove = imx_pinctrl_remove,
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
index 428d2a6857ef..20b1d0d671a3 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
@@ -1288,6 +1288,22 @@ static struct sh_pfc_pin pinmux_pins[] = {
1288 arg5##_MARK, arg6##_MARK, \ 1288 arg5##_MARK, arg6##_MARK, \
1289 arg7##_MARK, arg8##_MARK, } 1289 arg7##_MARK, arg8##_MARK, }
1290 1290
1291/* - AUDIO macro -------------------------------------------------------------*/
1292#define AUDIO_PFC_PIN(name, pin) SH_PFC_PINS(name, pin)
1293#define AUDIO_PFC_DAT(name, pin) SH_PFC_MUX1(name, pin)
1294
1295/* - AUDIO clock -------------------------------------------------------------*/
1296AUDIO_PFC_PIN(audio_clk_a, RCAR_GP_PIN(2, 22));
1297AUDIO_PFC_DAT(audio_clk_a, AUDIO_CLKA);
1298AUDIO_PFC_PIN(audio_clk_b, RCAR_GP_PIN(2, 23));
1299AUDIO_PFC_DAT(audio_clk_b, AUDIO_CLKB);
1300AUDIO_PFC_PIN(audio_clk_c, RCAR_GP_PIN(2, 7));
1301AUDIO_PFC_DAT(audio_clk_c, AUDIO_CLKC);
1302AUDIO_PFC_PIN(audio_clkout_a, RCAR_GP_PIN(2, 16));
1303AUDIO_PFC_DAT(audio_clkout_a, AUDIO_CLKOUT_A);
1304AUDIO_PFC_PIN(audio_clkout_b, RCAR_GP_PIN(1, 16));
1305AUDIO_PFC_DAT(audio_clkout_b, AUDIO_CLKOUT_B);
1306
1291/* - Ether ------------------------------------------------------------------ */ 1307/* - Ether ------------------------------------------------------------------ */
1292SH_PFC_PINS(ether_rmii, RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11), 1308SH_PFC_PINS(ether_rmii, RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
1293 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 9), 1309 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 9),
@@ -1577,6 +1593,59 @@ SDHI_PFC_WPPN(sdhi2_wp_a, SD2_WP_A);
1577SDHI_PFC_PINS(sdhi2_wp_b, RCAR_GP_PIN(3, 28)); 1593SDHI_PFC_PINS(sdhi2_wp_b, RCAR_GP_PIN(3, 28));
1578SDHI_PFC_WPPN(sdhi2_wp_b, SD2_WP_B); 1594SDHI_PFC_WPPN(sdhi2_wp_b, SD2_WP_B);
1579 1595
1596/* - SSI macro -------------------------------------------------------------- */
1597#define SSI_PFC_PINS(name, args...) SH_PFC_PINS(name, args)
1598#define SSI_PFC_CTRL(name, sck, ws) SH_PFC_MUX2(name, sck, ws)
1599#define SSI_PFC_DATA(name, d) SH_PFC_MUX1(name, d)
1600
1601/* - SSI 0/1/2 -------------------------------------------------------------- */
1602SSI_PFC_PINS(ssi012_ctrl, RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7));
1603SSI_PFC_CTRL(ssi012_ctrl, SSI_SCK012, SSI_WS012);
1604SSI_PFC_PINS(ssi0_data, RCAR_GP_PIN(3, 10));
1605SSI_PFC_DATA(ssi0_data, SSI_SDATA0);
1606SSI_PFC_PINS(ssi1_a_ctrl, RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21));
1607SSI_PFC_CTRL(ssi1_a_ctrl, SSI_SCK1_A, SSI_WS1_A);
1608SSI_PFC_PINS(ssi1_b_ctrl, PIN_NUMBER(3, 20), RCAR_GP_PIN(1, 3));
1609SSI_PFC_CTRL(ssi1_b_ctrl, SSI_SCK1_B, SSI_WS1_B);
1610SSI_PFC_PINS(ssi1_data, RCAR_GP_PIN(3, 9));
1611SSI_PFC_DATA(ssi1_data, SSI_SDATA1);
1612SSI_PFC_PINS(ssi2_a_ctrl, RCAR_GP_PIN(2, 26), RCAR_GP_PIN(3, 4));
1613SSI_PFC_CTRL(ssi2_a_ctrl, SSI_SCK2_A, SSI_WS2_A);
1614SSI_PFC_PINS(ssi2_b_ctrl, RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 17));
1615SSI_PFC_CTRL(ssi2_b_ctrl, SSI_SCK2_B, SSI_WS2_B);
1616SSI_PFC_PINS(ssi2_data, RCAR_GP_PIN(3, 8));
1617SSI_PFC_DATA(ssi2_data, SSI_SDATA2);
1618
1619/* - SSI 3/4 ---------------------------------------------------------------- */
1620SSI_PFC_PINS(ssi34_ctrl, RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3));
1621SSI_PFC_CTRL(ssi34_ctrl, SSI_SCK34, SSI_WS34);
1622SSI_PFC_PINS(ssi3_data, RCAR_GP_PIN(3, 5));
1623SSI_PFC_DATA(ssi3_data, SSI_SDATA3);
1624SSI_PFC_PINS(ssi4_ctrl, RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 23));
1625SSI_PFC_CTRL(ssi4_ctrl, SSI_SCK4, SSI_WS4);
1626SSI_PFC_PINS(ssi4_data, RCAR_GP_PIN(3, 4));
1627SSI_PFC_DATA(ssi4_data, SSI_SDATA4);
1628
1629/* - SSI 5 ------------------------------------------------------------------ */
1630SSI_PFC_PINS(ssi5_ctrl, RCAR_GP_PIN(2, 31), RCAR_GP_PIN(3, 0));
1631SSI_PFC_CTRL(ssi5_ctrl, SSI_SCK5, SSI_WS5);
1632SSI_PFC_PINS(ssi5_data, RCAR_GP_PIN(3, 1));
1633SSI_PFC_DATA(ssi5_data, SSI_SDATA5);
1634
1635/* - SSI 6 ------------------------------------------------------------------ */
1636SSI_PFC_PINS(ssi6_ctrl, RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 29));
1637SSI_PFC_CTRL(ssi6_ctrl, SSI_SCK6, SSI_WS6);
1638SSI_PFC_PINS(ssi6_data, RCAR_GP_PIN(2, 30));
1639SSI_PFC_DATA(ssi6_data, SSI_SDATA6);
1640
1641/* - SSI 7/8 --------------------------------------------------------------- */
1642SSI_PFC_PINS(ssi78_ctrl, RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 25));
1643SSI_PFC_CTRL(ssi78_ctrl, SSI_SCK78, SSI_WS78);
1644SSI_PFC_PINS(ssi7_data, RCAR_GP_PIN(2, 27));
1645SSI_PFC_DATA(ssi7_data, SSI_SDATA7);
1646SSI_PFC_PINS(ssi8_data, RCAR_GP_PIN(2, 26));
1647SSI_PFC_DATA(ssi8_data, SSI_SDATA8);
1648
1580/* - USB0 ------------------------------------------------------------------- */ 1649/* - USB0 ------------------------------------------------------------------- */
1581SH_PFC_PINS(usb0, RCAR_GP_PIN(0, 1)); 1650SH_PFC_PINS(usb0, RCAR_GP_PIN(0, 1));
1582SH_PFC_MUX1(usb0, PENC0); 1651SH_PFC_MUX1(usb0, PENC0);
@@ -1624,6 +1693,11 @@ VIN_PFC_PINS(vin1_sync, RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22));
1624VIN_PFC_SYNC(vin1_sync, VI1_HSYNC, VI1_VSYNC); 1693VIN_PFC_SYNC(vin1_sync, VI1_HSYNC, VI1_VSYNC);
1625 1694
1626static const struct sh_pfc_pin_group pinmux_groups[] = { 1695static const struct sh_pfc_pin_group pinmux_groups[] = {
1696 SH_PFC_PIN_GROUP(audio_clk_a),
1697 SH_PFC_PIN_GROUP(audio_clk_b),
1698 SH_PFC_PIN_GROUP(audio_clk_c),
1699 SH_PFC_PIN_GROUP(audio_clkout_a),
1700 SH_PFC_PIN_GROUP(audio_clkout_b),
1627 SH_PFC_PIN_GROUP(ether_rmii), 1701 SH_PFC_PIN_GROUP(ether_rmii),
1628 SH_PFC_PIN_GROUP(ether_link), 1702 SH_PFC_PIN_GROUP(ether_link),
1629 SH_PFC_PIN_GROUP(ether_magic), 1703 SH_PFC_PIN_GROUP(ether_magic),
@@ -1713,6 +1787,25 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
1713 SH_PFC_PIN_GROUP(sdhi2_data4_b), 1787 SH_PFC_PIN_GROUP(sdhi2_data4_b),
1714 SH_PFC_PIN_GROUP(sdhi2_wp_a), 1788 SH_PFC_PIN_GROUP(sdhi2_wp_a),
1715 SH_PFC_PIN_GROUP(sdhi2_wp_b), 1789 SH_PFC_PIN_GROUP(sdhi2_wp_b),
1790 SH_PFC_PIN_GROUP(ssi012_ctrl),
1791 SH_PFC_PIN_GROUP(ssi0_data),
1792 SH_PFC_PIN_GROUP(ssi1_a_ctrl),
1793 SH_PFC_PIN_GROUP(ssi1_b_ctrl),
1794 SH_PFC_PIN_GROUP(ssi1_data),
1795 SH_PFC_PIN_GROUP(ssi2_a_ctrl),
1796 SH_PFC_PIN_GROUP(ssi2_b_ctrl),
1797 SH_PFC_PIN_GROUP(ssi2_data),
1798 SH_PFC_PIN_GROUP(ssi34_ctrl),
1799 SH_PFC_PIN_GROUP(ssi3_data),
1800 SH_PFC_PIN_GROUP(ssi4_ctrl),
1801 SH_PFC_PIN_GROUP(ssi4_data),
1802 SH_PFC_PIN_GROUP(ssi5_ctrl),
1803 SH_PFC_PIN_GROUP(ssi5_data),
1804 SH_PFC_PIN_GROUP(ssi6_ctrl),
1805 SH_PFC_PIN_GROUP(ssi6_data),
1806 SH_PFC_PIN_GROUP(ssi78_ctrl),
1807 SH_PFC_PIN_GROUP(ssi7_data),
1808 SH_PFC_PIN_GROUP(ssi8_data),
1716 SH_PFC_PIN_GROUP(usb0), 1809 SH_PFC_PIN_GROUP(usb0),
1717 SH_PFC_PIN_GROUP(usb0_ovc), 1810 SH_PFC_PIN_GROUP(usb0_ovc),
1718 SH_PFC_PIN_GROUP(usb1), 1811 SH_PFC_PIN_GROUP(usb1),
@@ -1725,6 +1818,14 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
1725 SH_PFC_PIN_GROUP(vin1_sync), 1818 SH_PFC_PIN_GROUP(vin1_sync),
1726}; 1819};
1727 1820
1821static const char * const audio_clk_groups[] = {
1822 "audio_clk_a",
1823 "audio_clk_b",
1824 "audio_clk_c",
1825 "audio_clkout_a",
1826 "audio_clkout_b",
1827};
1828
1728static const char * const ether_groups[] = { 1829static const char * const ether_groups[] = {
1729 "ether_rmii", 1830 "ether_rmii",
1730 "ether_link", 1831 "ether_link",
@@ -1875,6 +1976,28 @@ static const char * const sdhi2_groups[] = {
1875 "sdhi2_wp_b", 1976 "sdhi2_wp_b",
1876}; 1977};
1877 1978
1979static const char * const ssi_groups[] = {
1980 "ssi012_ctrl",
1981 "ssi0_data",
1982 "ssi1_a_ctrl",
1983 "ssi1_b_ctrl",
1984 "ssi1_data",
1985 "ssi2_a_ctrl",
1986 "ssi2_b_ctrl",
1987 "ssi2_data",
1988 "ssi34_ctrl",
1989 "ssi3_data",
1990 "ssi4_ctrl",
1991 "ssi4_data",
1992 "ssi5_ctrl",
1993 "ssi5_data",
1994 "ssi6_ctrl",
1995 "ssi6_data",
1996 "ssi78_ctrl",
1997 "ssi7_data",
1998 "ssi8_data",
1999};
2000
1878static const char * const usb0_groups[] = { 2001static const char * const usb0_groups[] = {
1879 "usb0", 2002 "usb0",
1880 "usb0_ovc", 2003 "usb0_ovc",
@@ -1898,6 +2021,7 @@ static const char * const vin1_groups[] = {
1898}; 2021};
1899 2022
1900static const struct sh_pfc_function pinmux_functions[] = { 2023static const struct sh_pfc_function pinmux_functions[] = {
2024 SH_PFC_FUNCTION(audio_clk),
1901 SH_PFC_FUNCTION(ether), 2025 SH_PFC_FUNCTION(ether),
1902 SH_PFC_FUNCTION(hscif0), 2026 SH_PFC_FUNCTION(hscif0),
1903 SH_PFC_FUNCTION(hscif1), 2027 SH_PFC_FUNCTION(hscif1),
@@ -1918,6 +2042,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
1918 SH_PFC_FUNCTION(sdhi0), 2042 SH_PFC_FUNCTION(sdhi0),
1919 SH_PFC_FUNCTION(sdhi1), 2043 SH_PFC_FUNCTION(sdhi1),
1920 SH_PFC_FUNCTION(sdhi2), 2044 SH_PFC_FUNCTION(sdhi2),
2045 SH_PFC_FUNCTION(ssi),
1921 SH_PFC_FUNCTION(usb0), 2046 SH_PFC_FUNCTION(usb0),
1922 SH_PFC_FUNCTION(usb1), 2047 SH_PFC_FUNCTION(usb1),
1923 SH_PFC_FUNCTION(vin0), 2048 SH_PFC_FUNCTION(vin0),
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
index 64fcc00693b5..72786fc93958 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
@@ -781,6 +781,8 @@ enum {
781 ADICS_SAMP_MARK, DU2_CDE_MARK, QPOLB_MARK, SCIFA2_RXD_B_MARK, 781 ADICS_SAMP_MARK, DU2_CDE_MARK, QPOLB_MARK, SCIFA2_RXD_B_MARK,
782 USB1_PWEN_MARK, AUDIO_CLKOUT_D_MARK, USB1_OVC_MARK, 782 USB1_PWEN_MARK, AUDIO_CLKOUT_D_MARK, USB1_OVC_MARK,
783 TCLK1_B_MARK, 783 TCLK1_B_MARK,
784
785 I2C3_SCL_MARK, I2C3_SDA_MARK,
784 PINMUX_MARK_END, 786 PINMUX_MARK_END,
785}; 787};
786 788
@@ -1719,10 +1721,22 @@ static const u16 pinmux_data[] = {
1719 PINMUX_IPSR_DATA(IP16_6, AUDIO_CLKOUT_D), 1721 PINMUX_IPSR_DATA(IP16_6, AUDIO_CLKOUT_D),
1720 PINMUX_IPSR_DATA(IP16_7, USB1_OVC), 1722 PINMUX_IPSR_DATA(IP16_7, USB1_OVC),
1721 PINMUX_IPSR_MODSEL_DATA(IP16_7, TCLK1_B, SEL_TMU1_1), 1723 PINMUX_IPSR_MODSEL_DATA(IP16_7, TCLK1_B, SEL_TMU1_1),
1724
1725 PINMUX_DATA(I2C3_SCL_MARK, FN_SEL_IICDVFS_1),
1726 PINMUX_DATA(I2C3_SDA_MARK, FN_SEL_IICDVFS_1),
1722}; 1727};
1723 1728
1729/* R8A7790 has 6 banks with 32 GPIOs in each = 192 GPIOs */
1730#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1731#define PIN_NUMBER(r, c) (((r) - 'A') * 31 + (c) + 200)
1732#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1733
1724static struct sh_pfc_pin pinmux_pins[] = { 1734static struct sh_pfc_pin pinmux_pins[] = {
1725 PINMUX_GPIO_GP_ALL(), 1735 PINMUX_GPIO_GP_ALL(),
1736
1737 /* Pins not associated with a GPIO port */
1738 SH_PFC_PIN_NAMED(ROW_GROUP_A('J'), 15, AJ15),
1739 SH_PFC_PIN_NAMED(ROW_GROUP_A('H'), 15, AH15),
1726}; 1740};
1727 1741
1728/* - DU RGB ----------------------------------------------------------------- */ 1742/* - DU RGB ----------------------------------------------------------------- */
@@ -1990,6 +2004,72 @@ static const unsigned int hscif1_ctrl_b_pins[] = {
1990static const unsigned int hscif1_ctrl_b_mux[] = { 2004static const unsigned int hscif1_ctrl_b_mux[] = {
1991 HRTS1_N_B_MARK, HCTS1_N_B_MARK, 2005 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
1992}; 2006};
2007/* - I2C1 ------------------------------------------------------------------- */
2008static const unsigned int i2c1_pins[] = {
2009 /* SCL, SDA */
2010 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
2011};
2012static const unsigned int i2c1_mux[] = {
2013 I2C1_SCL_MARK, I2C1_SDA_MARK,
2014};
2015static const unsigned int i2c1_b_pins[] = {
2016 /* SCL, SDA */
2017 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2018};
2019static const unsigned int i2c1_b_mux[] = {
2020 I2C1_SCL_B_MARK, I2C1_SDA_B_MARK,
2021};
2022static const unsigned int i2c1_c_pins[] = {
2023 /* SCL, SDA */
2024 RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
2025};
2026static const unsigned int i2c1_c_mux[] = {
2027 I2C1_SCL_C_MARK, I2C1_SDA_C_MARK,
2028};
2029/* - I2C2 ------------------------------------------------------------------- */
2030static const unsigned int i2c2_pins[] = {
2031 /* SCL, SDA */
2032 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2033};
2034static const unsigned int i2c2_mux[] = {
2035 I2C2_SCL_MARK, I2C2_SDA_MARK,
2036};
2037static const unsigned int i2c2_b_pins[] = {
2038 /* SCL, SDA */
2039 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
2040};
2041static const unsigned int i2c2_b_mux[] = {
2042 I2C2_SCL_B_MARK, I2C2_SDA_B_MARK,
2043};
2044static const unsigned int i2c2_c_pins[] = {
2045 /* SCL, SDA */
2046 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
2047};
2048static const unsigned int i2c2_c_mux[] = {
2049 I2C2_SCL_C_MARK, I2C2_SDA_C_MARK,
2050};
2051static const unsigned int i2c2_d_pins[] = {
2052 /* SCL, SDA */
2053 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2054};
2055static const unsigned int i2c2_d_mux[] = {
2056 I2C2_SCL_D_MARK, I2C2_SDA_D_MARK,
2057};
2058static const unsigned int i2c2_e_pins[] = {
2059 /* SCL, SDA */
2060 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
2061};
2062static const unsigned int i2c2_e_mux[] = {
2063 I2C2_SCL_E_MARK, I2C2_SDA_E_MARK,
2064};
2065/* - I2C3 ------------------------------------------------------------------- */
2066static const unsigned int i2c3_pins[] = {
2067 /* SCL, SDA */
2068 PIN_A_NUMBER('J', 15), PIN_A_NUMBER('H', 15),
2069};
2070static const unsigned int i2c3_mux[] = {
2071 I2C3_SCL_MARK, I2C3_SDA_MARK,
2072};
1993/* - INTC ------------------------------------------------------------------- */ 2073/* - INTC ------------------------------------------------------------------- */
1994static const unsigned int intc_irq0_pins[] = { 2074static const unsigned int intc_irq0_pins[] = {
1995 /* IRQ */ 2075 /* IRQ */
@@ -3047,6 +3127,15 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
3047 SH_PFC_PIN_GROUP(hscif1_data_b), 3127 SH_PFC_PIN_GROUP(hscif1_data_b),
3048 SH_PFC_PIN_GROUP(hscif1_clk_b), 3128 SH_PFC_PIN_GROUP(hscif1_clk_b),
3049 SH_PFC_PIN_GROUP(hscif1_ctrl_b), 3129 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
3130 SH_PFC_PIN_GROUP(i2c1),
3131 SH_PFC_PIN_GROUP(i2c1_b),
3132 SH_PFC_PIN_GROUP(i2c1_c),
3133 SH_PFC_PIN_GROUP(i2c2),
3134 SH_PFC_PIN_GROUP(i2c2_b),
3135 SH_PFC_PIN_GROUP(i2c2_c),
3136 SH_PFC_PIN_GROUP(i2c2_d),
3137 SH_PFC_PIN_GROUP(i2c2_e),
3138 SH_PFC_PIN_GROUP(i2c3),
3050 SH_PFC_PIN_GROUP(intc_irq0), 3139 SH_PFC_PIN_GROUP(intc_irq0),
3051 SH_PFC_PIN_GROUP(intc_irq1), 3140 SH_PFC_PIN_GROUP(intc_irq1),
3052 SH_PFC_PIN_GROUP(intc_irq2), 3141 SH_PFC_PIN_GROUP(intc_irq2),
@@ -3243,6 +3332,24 @@ static const char * const hscif1_groups[] = {
3243 "hscif1_ctrl_b", 3332 "hscif1_ctrl_b",
3244}; 3333};
3245 3334
3335static const char * const i2c1_groups[] = {
3336 "i2c1",
3337 "i2c1_b",
3338 "i2c1_c",
3339};
3340
3341static const char * const i2c2_groups[] = {
3342 "i2c2",
3343 "i2c2_b",
3344 "i2c2_c",
3345 "i2c2_d",
3346 "i2c2_e",
3347};
3348
3349static const char * const i2c3_groups[] = {
3350 "i2c3",
3351};
3352
3246static const char * const intc_groups[] = { 3353static const char * const intc_groups[] = {
3247 "intc_irq0", 3354 "intc_irq0",
3248 "intc_irq1", 3355 "intc_irq1",
@@ -3469,6 +3576,9 @@ static const struct sh_pfc_function pinmux_functions[] = {
3469 SH_PFC_FUNCTION(eth), 3576 SH_PFC_FUNCTION(eth),
3470 SH_PFC_FUNCTION(hscif0), 3577 SH_PFC_FUNCTION(hscif0),
3471 SH_PFC_FUNCTION(hscif1), 3578 SH_PFC_FUNCTION(hscif1),
3579 SH_PFC_FUNCTION(i2c1),
3580 SH_PFC_FUNCTION(i2c2),
3581 SH_PFC_FUNCTION(i2c3),
3472 SH_PFC_FUNCTION(intc), 3582 SH_PFC_FUNCTION(intc),
3473 SH_PFC_FUNCTION(mmc0), 3583 SH_PFC_FUNCTION(mmc0),
3474 SH_PFC_FUNCTION(mmc1), 3584 SH_PFC_FUNCTION(mmc1),
diff --git a/drivers/pinctrl/sirf/pinctrl-atlas6.c b/drivers/pinctrl/sirf/pinctrl-atlas6.c
index edf45a6940ca..8ab7898d21be 100644
--- a/drivers/pinctrl/sirf/pinctrl-atlas6.c
+++ b/drivers/pinctrl/sirf/pinctrl-atlas6.c
@@ -122,6 +122,9 @@ static const struct pinctrl_pin_desc sirfsoc_pads[] = {
122 PINCTRL_PIN(100, "ac97_dout"), 122 PINCTRL_PIN(100, "ac97_dout"),
123 PINCTRL_PIN(101, "ac97_din"), 123 PINCTRL_PIN(101, "ac97_din"),
124 PINCTRL_PIN(102, "x_rtc_io"), 124 PINCTRL_PIN(102, "x_rtc_io"),
125
126 PINCTRL_PIN(103, "x_usb1_dp"),
127 PINCTRL_PIN(104, "x_usb1_dn"),
125}; 128};
126 129
127static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = { 130static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = {
@@ -139,6 +142,7 @@ static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = {
139static const struct sirfsoc_padmux lcd_16bits_padmux = { 142static const struct sirfsoc_padmux lcd_16bits_padmux = {
140 .muxmask_counts = ARRAY_SIZE(lcd_16bits_sirfsoc_muxmask), 143 .muxmask_counts = ARRAY_SIZE(lcd_16bits_sirfsoc_muxmask),
141 .muxmask = lcd_16bits_sirfsoc_muxmask, 144 .muxmask = lcd_16bits_sirfsoc_muxmask,
145 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
142 .funcmask = BIT(4), 146 .funcmask = BIT(4),
143 .funcval = 0, 147 .funcval = 0,
144}; 148};
@@ -164,6 +168,7 @@ static const struct sirfsoc_muxmask lcd_18bits_muxmask[] = {
164static const struct sirfsoc_padmux lcd_18bits_padmux = { 168static const struct sirfsoc_padmux lcd_18bits_padmux = {
165 .muxmask_counts = ARRAY_SIZE(lcd_18bits_muxmask), 169 .muxmask_counts = ARRAY_SIZE(lcd_18bits_muxmask),
166 .muxmask = lcd_18bits_muxmask, 170 .muxmask = lcd_18bits_muxmask,
171 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
167 .funcmask = BIT(4) | BIT(15), 172 .funcmask = BIT(4) | BIT(15),
168 .funcval = 0, 173 .funcval = 0,
169}; 174};
@@ -189,6 +194,7 @@ static const struct sirfsoc_muxmask lcd_24bits_muxmask[] = {
189static const struct sirfsoc_padmux lcd_24bits_padmux = { 194static const struct sirfsoc_padmux lcd_24bits_padmux = {
190 .muxmask_counts = ARRAY_SIZE(lcd_24bits_muxmask), 195 .muxmask_counts = ARRAY_SIZE(lcd_24bits_muxmask),
191 .muxmask = lcd_24bits_muxmask, 196 .muxmask = lcd_24bits_muxmask,
197 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
192 .funcmask = BIT(4) | BIT(15), 198 .funcmask = BIT(4) | BIT(15),
193 .funcval = 0, 199 .funcval = 0,
194}; 200};
@@ -214,6 +220,7 @@ static const struct sirfsoc_muxmask lcdrom_muxmask[] = {
214static const struct sirfsoc_padmux lcdrom_padmux = { 220static const struct sirfsoc_padmux lcdrom_padmux = {
215 .muxmask_counts = ARRAY_SIZE(lcdrom_muxmask), 221 .muxmask_counts = ARRAY_SIZE(lcdrom_muxmask),
216 .muxmask = lcdrom_muxmask, 222 .muxmask = lcdrom_muxmask,
223 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
217 .funcmask = BIT(4), 224 .funcmask = BIT(4),
218 .funcval = BIT(4), 225 .funcval = BIT(4),
219}; 226};
@@ -237,6 +244,7 @@ static const struct sirfsoc_muxmask uart0_muxmask[] = {
237static const struct sirfsoc_padmux uart0_padmux = { 244static const struct sirfsoc_padmux uart0_padmux = {
238 .muxmask_counts = ARRAY_SIZE(uart0_muxmask), 245 .muxmask_counts = ARRAY_SIZE(uart0_muxmask),
239 .muxmask = uart0_muxmask, 246 .muxmask = uart0_muxmask,
247 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
240 .funcmask = BIT(9), 248 .funcmask = BIT(9),
241 .funcval = BIT(9), 249 .funcval = BIT(9),
242}; 250};
@@ -284,6 +292,7 @@ static const struct sirfsoc_muxmask uart2_muxmask[] = {
284static const struct sirfsoc_padmux uart2_padmux = { 292static const struct sirfsoc_padmux uart2_padmux = {
285 .muxmask_counts = ARRAY_SIZE(uart2_muxmask), 293 .muxmask_counts = ARRAY_SIZE(uart2_muxmask),
286 .muxmask = uart2_muxmask, 294 .muxmask = uart2_muxmask,
295 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
287 .funcmask = BIT(10), 296 .funcmask = BIT(10),
288 .funcval = BIT(10), 297 .funcval = BIT(10),
289}; 298};
@@ -317,6 +326,7 @@ static const struct sirfsoc_muxmask sdmmc3_muxmask[] = {
317static const struct sirfsoc_padmux sdmmc3_padmux = { 326static const struct sirfsoc_padmux sdmmc3_padmux = {
318 .muxmask_counts = ARRAY_SIZE(sdmmc3_muxmask), 327 .muxmask_counts = ARRAY_SIZE(sdmmc3_muxmask),
319 .muxmask = sdmmc3_muxmask, 328 .muxmask = sdmmc3_muxmask,
329 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
320 .funcmask = BIT(7), 330 .funcmask = BIT(7),
321 .funcval = 0, 331 .funcval = 0,
322}; 332};
@@ -336,6 +346,7 @@ static const struct sirfsoc_muxmask spi0_muxmask[] = {
336static const struct sirfsoc_padmux spi0_padmux = { 346static const struct sirfsoc_padmux spi0_padmux = {
337 .muxmask_counts = ARRAY_SIZE(spi0_muxmask), 347 .muxmask_counts = ARRAY_SIZE(spi0_muxmask),
338 .muxmask = spi0_muxmask, 348 .muxmask = spi0_muxmask,
349 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
339 .funcmask = BIT(7), 350 .funcmask = BIT(7),
340 .funcval = BIT(7), 351 .funcval = BIT(7),
341}; 352};
@@ -352,6 +363,7 @@ static const struct sirfsoc_muxmask cko1_muxmask[] = {
352static const struct sirfsoc_padmux cko1_padmux = { 363static const struct sirfsoc_padmux cko1_padmux = {
353 .muxmask_counts = ARRAY_SIZE(cko1_muxmask), 364 .muxmask_counts = ARRAY_SIZE(cko1_muxmask),
354 .muxmask = cko1_muxmask, 365 .muxmask = cko1_muxmask,
366 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
355 .funcmask = BIT(3), 367 .funcmask = BIT(3),
356 .funcval = 0, 368 .funcval = 0,
357}; 369};
@@ -371,6 +383,7 @@ static const struct sirfsoc_muxmask i2s_muxmask[] = {
371static const struct sirfsoc_padmux i2s_padmux = { 383static const struct sirfsoc_padmux i2s_padmux = {
372 .muxmask_counts = ARRAY_SIZE(i2s_muxmask), 384 .muxmask_counts = ARRAY_SIZE(i2s_muxmask),
373 .muxmask = i2s_muxmask, 385 .muxmask = i2s_muxmask,
386 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
374 .funcmask = BIT(3), 387 .funcmask = BIT(3),
375 .funcval = BIT(3), 388 .funcval = BIT(3),
376}; 389};
@@ -390,6 +403,7 @@ static const struct sirfsoc_muxmask i2s_no_din_muxmask[] = {
390static const struct sirfsoc_padmux i2s_no_din_padmux = { 403static const struct sirfsoc_padmux i2s_no_din_padmux = {
391 .muxmask_counts = ARRAY_SIZE(i2s_no_din_muxmask), 404 .muxmask_counts = ARRAY_SIZE(i2s_no_din_muxmask),
392 .muxmask = i2s_no_din_muxmask, 405 .muxmask = i2s_no_din_muxmask,
406 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
393 .funcmask = BIT(3), 407 .funcmask = BIT(3),
394 .funcval = BIT(3), 408 .funcval = BIT(3),
395}; 409};
@@ -409,6 +423,7 @@ static const struct sirfsoc_muxmask i2s_6chn_muxmask[] = {
409static const struct sirfsoc_padmux i2s_6chn_padmux = { 423static const struct sirfsoc_padmux i2s_6chn_padmux = {
410 .muxmask_counts = ARRAY_SIZE(i2s_6chn_muxmask), 424 .muxmask_counts = ARRAY_SIZE(i2s_6chn_muxmask),
411 .muxmask = i2s_6chn_muxmask, 425 .muxmask = i2s_6chn_muxmask,
426 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
412 .funcmask = BIT(1) | BIT(3) | BIT(9), 427 .funcmask = BIT(1) | BIT(3) | BIT(9),
413 .funcval = BIT(1) | BIT(3) | BIT(9), 428 .funcval = BIT(1) | BIT(3) | BIT(9),
414}; 429};
@@ -439,6 +454,7 @@ static const struct sirfsoc_muxmask spi1_muxmask[] = {
439static const struct sirfsoc_padmux spi1_padmux = { 454static const struct sirfsoc_padmux spi1_padmux = {
440 .muxmask_counts = ARRAY_SIZE(spi1_muxmask), 455 .muxmask_counts = ARRAY_SIZE(spi1_muxmask),
441 .muxmask = spi1_muxmask, 456 .muxmask = spi1_muxmask,
457 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
442 .funcmask = BIT(16), 458 .funcmask = BIT(16),
443 .funcval = 0, 459 .funcval = 0,
444}; 460};
@@ -455,6 +471,7 @@ static const struct sirfsoc_muxmask sdmmc1_muxmask[] = {
455static const struct sirfsoc_padmux sdmmc1_padmux = { 471static const struct sirfsoc_padmux sdmmc1_padmux = {
456 .muxmask_counts = ARRAY_SIZE(sdmmc1_muxmask), 472 .muxmask_counts = ARRAY_SIZE(sdmmc1_muxmask),
457 .muxmask = sdmmc1_muxmask, 473 .muxmask = sdmmc1_muxmask,
474 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
458 .funcmask = BIT(5), 475 .funcmask = BIT(5),
459 .funcval = BIT(5), 476 .funcval = BIT(5),
460}; 477};
@@ -471,6 +488,7 @@ static const struct sirfsoc_muxmask gps_muxmask[] = {
471static const struct sirfsoc_padmux gps_padmux = { 488static const struct sirfsoc_padmux gps_padmux = {
472 .muxmask_counts = ARRAY_SIZE(gps_muxmask), 489 .muxmask_counts = ARRAY_SIZE(gps_muxmask),
473 .muxmask = gps_muxmask, 490 .muxmask = gps_muxmask,
491 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
474 .funcmask = BIT(13), 492 .funcmask = BIT(13),
475 .funcval = 0, 493 .funcval = 0,
476}; 494};
@@ -487,6 +505,7 @@ static const struct sirfsoc_muxmask sdmmc5_muxmask[] = {
487static const struct sirfsoc_padmux sdmmc5_padmux = { 505static const struct sirfsoc_padmux sdmmc5_padmux = {
488 .muxmask_counts = ARRAY_SIZE(sdmmc5_muxmask), 506 .muxmask_counts = ARRAY_SIZE(sdmmc5_muxmask),
489 .muxmask = sdmmc5_muxmask, 507 .muxmask = sdmmc5_muxmask,
508 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
490 .funcmask = BIT(13), 509 .funcmask = BIT(13),
491 .funcval = BIT(13), 510 .funcval = BIT(13),
492}; 511};
@@ -503,6 +522,7 @@ static const struct sirfsoc_muxmask usp0_muxmask[] = {
503static const struct sirfsoc_padmux usp0_padmux = { 522static const struct sirfsoc_padmux usp0_padmux = {
504 .muxmask_counts = ARRAY_SIZE(usp0_muxmask), 523 .muxmask_counts = ARRAY_SIZE(usp0_muxmask),
505 .muxmask = usp0_muxmask, 524 .muxmask = usp0_muxmask,
525 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
506 .funcmask = BIT(1) | BIT(2) | BIT(9), 526 .funcmask = BIT(1) | BIT(2) | BIT(9),
507 .funcval = 0, 527 .funcval = 0,
508}; 528};
@@ -535,6 +555,7 @@ static const struct sirfsoc_muxmask usp1_muxmask[] = {
535static const struct sirfsoc_padmux usp1_padmux = { 555static const struct sirfsoc_padmux usp1_padmux = {
536 .muxmask_counts = ARRAY_SIZE(usp1_muxmask), 556 .muxmask_counts = ARRAY_SIZE(usp1_muxmask),
537 .muxmask = usp1_muxmask, 557 .muxmask = usp1_muxmask,
558 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
538 .funcmask = BIT(16), 559 .funcmask = BIT(16),
539 .funcval = BIT(16), 560 .funcval = BIT(16),
540}; 561};
@@ -554,6 +575,7 @@ static const struct sirfsoc_muxmask nand_muxmask[] = {
554static const struct sirfsoc_padmux nand_padmux = { 575static const struct sirfsoc_padmux nand_padmux = {
555 .muxmask_counts = ARRAY_SIZE(nand_muxmask), 576 .muxmask_counts = ARRAY_SIZE(nand_muxmask),
556 .muxmask = nand_muxmask, 577 .muxmask = nand_muxmask,
578 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
557 .funcmask = BIT(5) | BIT(19), 579 .funcmask = BIT(5) | BIT(19),
558 .funcval = 0, 580 .funcval = 0,
559}; 581};
@@ -570,6 +592,7 @@ static const struct sirfsoc_muxmask sdmmc0_muxmask[] = {
570static const struct sirfsoc_padmux sdmmc0_padmux = { 592static const struct sirfsoc_padmux sdmmc0_padmux = {
571 .muxmask_counts = ARRAY_SIZE(sdmmc0_muxmask), 593 .muxmask_counts = ARRAY_SIZE(sdmmc0_muxmask),
572 .muxmask = sdmmc0_muxmask, 594 .muxmask = sdmmc0_muxmask,
595 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
573 .funcmask = BIT(5) | BIT(19), 596 .funcmask = BIT(5) | BIT(19),
574 .funcval = BIT(19), 597 .funcval = BIT(19),
575}; 598};
@@ -586,6 +609,7 @@ static const struct sirfsoc_muxmask sdmmc2_muxmask[] = {
586static const struct sirfsoc_padmux sdmmc2_padmux = { 609static const struct sirfsoc_padmux sdmmc2_padmux = {
587 .muxmask_counts = ARRAY_SIZE(sdmmc2_muxmask), 610 .muxmask_counts = ARRAY_SIZE(sdmmc2_muxmask),
588 .muxmask = sdmmc2_muxmask, 611 .muxmask = sdmmc2_muxmask,
612 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
589 .funcmask = BIT(11), 613 .funcmask = BIT(11),
590 .funcval = 0, 614 .funcval = 0,
591}; 615};
@@ -602,6 +626,7 @@ static const struct sirfsoc_muxmask sdmmc2_nowp_muxmask[] = {
602static const struct sirfsoc_padmux sdmmc2_nowp_padmux = { 626static const struct sirfsoc_padmux sdmmc2_nowp_padmux = {
603 .muxmask_counts = ARRAY_SIZE(sdmmc2_nowp_muxmask), 627 .muxmask_counts = ARRAY_SIZE(sdmmc2_nowp_muxmask),
604 .muxmask = sdmmc2_nowp_muxmask, 628 .muxmask = sdmmc2_nowp_muxmask,
629 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
605 .funcmask = BIT(11), 630 .funcmask = BIT(11),
606 .funcval = 0, 631 .funcval = 0,
607}; 632};
@@ -634,6 +659,7 @@ static const struct sirfsoc_muxmask vip_muxmask[] = {
634static const struct sirfsoc_padmux vip_padmux = { 659static const struct sirfsoc_padmux vip_padmux = {
635 .muxmask_counts = ARRAY_SIZE(vip_muxmask), 660 .muxmask_counts = ARRAY_SIZE(vip_muxmask),
636 .muxmask = vip_muxmask, 661 .muxmask = vip_muxmask,
662 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
637 .funcmask = BIT(18), 663 .funcmask = BIT(18),
638 .funcval = BIT(18), 664 .funcval = BIT(18),
639}; 665};
@@ -654,6 +680,7 @@ static const struct sirfsoc_muxmask vip_noupli_muxmask[] = {
654static const struct sirfsoc_padmux vip_noupli_padmux = { 680static const struct sirfsoc_padmux vip_noupli_padmux = {
655 .muxmask_counts = ARRAY_SIZE(vip_noupli_muxmask), 681 .muxmask_counts = ARRAY_SIZE(vip_noupli_muxmask),
656 .muxmask = vip_noupli_muxmask, 682 .muxmask = vip_noupli_muxmask,
683 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
657 .funcmask = BIT(15), 684 .funcmask = BIT(15),
658 .funcval = BIT(15), 685 .funcval = BIT(15),
659}; 686};
@@ -684,6 +711,7 @@ static const struct sirfsoc_muxmask i2c1_muxmask[] = {
684static const struct sirfsoc_padmux i2c1_padmux = { 711static const struct sirfsoc_padmux i2c1_padmux = {
685 .muxmask_counts = ARRAY_SIZE(i2c1_muxmask), 712 .muxmask_counts = ARRAY_SIZE(i2c1_muxmask),
686 .muxmask = i2c1_muxmask, 713 .muxmask = i2c1_muxmask,
714 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
687 .funcmask = BIT(16), 715 .funcmask = BIT(16),
688 .funcval = 0, 716 .funcval = 0,
689}; 717};
@@ -700,6 +728,7 @@ static const struct sirfsoc_muxmask pwm0_muxmask[] = {
700static const struct sirfsoc_padmux pwm0_padmux = { 728static const struct sirfsoc_padmux pwm0_padmux = {
701 .muxmask_counts = ARRAY_SIZE(pwm0_muxmask), 729 .muxmask_counts = ARRAY_SIZE(pwm0_muxmask),
702 .muxmask = pwm0_muxmask, 730 .muxmask = pwm0_muxmask,
731 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
703 .funcmask = BIT(12), 732 .funcmask = BIT(12),
704 .funcval = 0, 733 .funcval = 0,
705}; 734};
@@ -772,6 +801,7 @@ static const struct sirfsoc_muxmask warm_rst_muxmask[] = {
772static const struct sirfsoc_padmux warm_rst_padmux = { 801static const struct sirfsoc_padmux warm_rst_padmux = {
773 .muxmask_counts = ARRAY_SIZE(warm_rst_muxmask), 802 .muxmask_counts = ARRAY_SIZE(warm_rst_muxmask),
774 .muxmask = warm_rst_muxmask, 803 .muxmask = warm_rst_muxmask,
804 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
775 .funcmask = BIT(4), 805 .funcmask = BIT(4),
776 .funcval = 0, 806 .funcval = 0,
777}; 807};
@@ -789,6 +819,7 @@ static const struct sirfsoc_muxmask usb0_upli_drvbus_muxmask[] = {
789static const struct sirfsoc_padmux usb0_upli_drvbus_padmux = { 819static const struct sirfsoc_padmux usb0_upli_drvbus_padmux = {
790 .muxmask_counts = ARRAY_SIZE(usb0_upli_drvbus_muxmask), 820 .muxmask_counts = ARRAY_SIZE(usb0_upli_drvbus_muxmask),
791 .muxmask = usb0_upli_drvbus_muxmask, 821 .muxmask = usb0_upli_drvbus_muxmask,
822 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
792 .funcmask = BIT(18), 823 .funcmask = BIT(18),
793 .funcval = 0, 824 .funcval = 0,
794}; 825};
@@ -805,12 +836,31 @@ static const struct sirfsoc_muxmask usb1_utmi_drvbus_muxmask[] = {
805static const struct sirfsoc_padmux usb1_utmi_drvbus_padmux = { 836static const struct sirfsoc_padmux usb1_utmi_drvbus_padmux = {
806 .muxmask_counts = ARRAY_SIZE(usb1_utmi_drvbus_muxmask), 837 .muxmask_counts = ARRAY_SIZE(usb1_utmi_drvbus_muxmask),
807 .muxmask = usb1_utmi_drvbus_muxmask, 838 .muxmask = usb1_utmi_drvbus_muxmask,
839 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
808 .funcmask = BIT(11), 840 .funcmask = BIT(11),
809 .funcval = BIT(11), /* refer to PAD_UTMI_DRVVBUS1_ENABLE */ 841 .funcval = BIT(11), /* refer to PAD_UTMI_DRVVBUS1_ENABLE */
810}; 842};
811 843
812static const unsigned usb1_utmi_drvbus_pins[] = { 28 }; 844static const unsigned usb1_utmi_drvbus_pins[] = { 28 };
813 845
846static const struct sirfsoc_padmux usb1_dp_dn_padmux = {
847 .muxmask_counts = 0,
848 .ctrlreg = SIRFSOC_RSC_USB_UART_SHARE,
849 .funcmask = BIT(2),
850 .funcval = BIT(2),
851};
852
853static const unsigned usb1_dp_dn_pins[] = { 103, 104 };
854
855static const struct sirfsoc_padmux uart1_route_io_usb1_padmux = {
856 .muxmask_counts = 0,
857 .ctrlreg = SIRFSOC_RSC_USB_UART_SHARE,
858 .funcmask = BIT(2),
859 .funcval = 0,
860};
861
862static const unsigned uart1_route_io_usb1_pins[] = { 103, 104 };
863
814static const struct sirfsoc_muxmask pulse_count_muxmask[] = { 864static const struct sirfsoc_muxmask pulse_count_muxmask[] = {
815 { 865 {
816 .group = 0, 866 .group = 0,
@@ -859,6 +909,8 @@ static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
859 SIRFSOC_PIN_GROUP("sdmmc5grp", sdmmc5_pins), 909 SIRFSOC_PIN_GROUP("sdmmc5grp", sdmmc5_pins),
860 SIRFSOC_PIN_GROUP("usb0_upli_drvbusgrp", usb0_upli_drvbus_pins), 910 SIRFSOC_PIN_GROUP("usb0_upli_drvbusgrp", usb0_upli_drvbus_pins),
861 SIRFSOC_PIN_GROUP("usb1_utmi_drvbusgrp", usb1_utmi_drvbus_pins), 911 SIRFSOC_PIN_GROUP("usb1_utmi_drvbusgrp", usb1_utmi_drvbus_pins),
912 SIRFSOC_PIN_GROUP("usb1_dp_dngrp", usb1_dp_dn_pins),
913 SIRFSOC_PIN_GROUP("uart1_route_io_usb1grp", uart1_route_io_usb1_pins),
862 SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins), 914 SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins),
863 SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins), 915 SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins),
864 SIRFSOC_PIN_GROUP("i2s_no_dingrp", i2s_no_din_pins), 916 SIRFSOC_PIN_GROUP("i2s_no_dingrp", i2s_no_din_pins),
@@ -903,6 +955,8 @@ static const char * const sdmmc5grp[] = { "sdmmc5grp" };
903static const char * const sdmmc2_nowpgrp[] = { "sdmmc2_nowpgrp" }; 955static const char * const sdmmc2_nowpgrp[] = { "sdmmc2_nowpgrp" };
904static const char * const usb0_upli_drvbusgrp[] = { "usb0_upli_drvbusgrp" }; 956static const char * const usb0_upli_drvbusgrp[] = { "usb0_upli_drvbusgrp" };
905static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" }; 957static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" };
958static const char * const usb1_dp_dngrp[] = { "usb1_dp_dngrp" };
959static const char * const uart1_route_io_usb1grp[] = { "uart1_route_io_usb1grp" };
906static const char * const pulse_countgrp[] = { "pulse_countgrp" }; 960static const char * const pulse_countgrp[] = { "pulse_countgrp" };
907static const char * const i2sgrp[] = { "i2sgrp" }; 961static const char * const i2sgrp[] = { "i2sgrp" };
908static const char * const i2s_no_dingrp[] = { "i2s_no_dingrp" }; 962static const char * const i2s_no_dingrp[] = { "i2s_no_dingrp" };
@@ -949,6 +1003,8 @@ static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = {
949 SIRFSOC_PMX_FUNCTION("sdmmc2_nowp", sdmmc2_nowpgrp, sdmmc2_nowp_padmux), 1003 SIRFSOC_PMX_FUNCTION("sdmmc2_nowp", sdmmc2_nowpgrp, sdmmc2_nowp_padmux),
950 SIRFSOC_PMX_FUNCTION("usb0_upli_drvbus", usb0_upli_drvbusgrp, usb0_upli_drvbus_padmux), 1004 SIRFSOC_PMX_FUNCTION("usb0_upli_drvbus", usb0_upli_drvbusgrp, usb0_upli_drvbus_padmux),
951 SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus", usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux), 1005 SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus", usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux),
1006 SIRFSOC_PMX_FUNCTION("usb1_dp_dn", usb1_dp_dngrp, usb1_dp_dn_padmux),
1007 SIRFSOC_PMX_FUNCTION("uart1_route_io_usb1", uart1_route_io_usb1grp, uart1_route_io_usb1_padmux),
952 SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux), 1008 SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux),
953 SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux), 1009 SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux),
954 SIRFSOC_PMX_FUNCTION("i2s_no_din", i2s_no_dingrp, i2s_no_din_padmux), 1010 SIRFSOC_PMX_FUNCTION("i2s_no_din", i2s_no_dingrp, i2s_no_din_padmux),
diff --git a/drivers/pinctrl/sirf/pinctrl-prima2.c b/drivers/pinctrl/sirf/pinctrl-prima2.c
index 1f0ad1ef5a3a..050777be0f1e 100644
--- a/drivers/pinctrl/sirf/pinctrl-prima2.c
+++ b/drivers/pinctrl/sirf/pinctrl-prima2.c
@@ -126,6 +126,9 @@ static const struct pinctrl_pin_desc sirfsoc_pads[] = {
126 PINCTRL_PIN(112, "x_ldd[13]"), 126 PINCTRL_PIN(112, "x_ldd[13]"),
127 PINCTRL_PIN(113, "x_ldd[14]"), 127 PINCTRL_PIN(113, "x_ldd[14]"),
128 PINCTRL_PIN(114, "x_ldd[15]"), 128 PINCTRL_PIN(114, "x_ldd[15]"),
129
130 PINCTRL_PIN(115, "x_usb1_dp"),
131 PINCTRL_PIN(116, "x_usb1_dn"),
129}; 132};
130 133
131static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = { 134static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = {
@@ -143,6 +146,7 @@ static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = {
143static const struct sirfsoc_padmux lcd_16bits_padmux = { 146static const struct sirfsoc_padmux lcd_16bits_padmux = {
144 .muxmask_counts = ARRAY_SIZE(lcd_16bits_sirfsoc_muxmask), 147 .muxmask_counts = ARRAY_SIZE(lcd_16bits_sirfsoc_muxmask),
145 .muxmask = lcd_16bits_sirfsoc_muxmask, 148 .muxmask = lcd_16bits_sirfsoc_muxmask,
149 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
146 .funcmask = BIT(4), 150 .funcmask = BIT(4),
147 .funcval = 0, 151 .funcval = 0,
148}; 152};
@@ -168,6 +172,7 @@ static const struct sirfsoc_muxmask lcd_18bits_muxmask[] = {
168static const struct sirfsoc_padmux lcd_18bits_padmux = { 172static const struct sirfsoc_padmux lcd_18bits_padmux = {
169 .muxmask_counts = ARRAY_SIZE(lcd_18bits_muxmask), 173 .muxmask_counts = ARRAY_SIZE(lcd_18bits_muxmask),
170 .muxmask = lcd_18bits_muxmask, 174 .muxmask = lcd_18bits_muxmask,
175 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
171 .funcmask = BIT(4), 176 .funcmask = BIT(4),
172 .funcval = 0, 177 .funcval = 0,
173}; 178};
@@ -193,6 +198,7 @@ static const struct sirfsoc_muxmask lcd_24bits_muxmask[] = {
193static const struct sirfsoc_padmux lcd_24bits_padmux = { 198static const struct sirfsoc_padmux lcd_24bits_padmux = {
194 .muxmask_counts = ARRAY_SIZE(lcd_24bits_muxmask), 199 .muxmask_counts = ARRAY_SIZE(lcd_24bits_muxmask),
195 .muxmask = lcd_24bits_muxmask, 200 .muxmask = lcd_24bits_muxmask,
201 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
196 .funcmask = BIT(4), 202 .funcmask = BIT(4),
197 .funcval = 0, 203 .funcval = 0,
198}; 204};
@@ -218,6 +224,7 @@ static const struct sirfsoc_muxmask lcdrom_muxmask[] = {
218static const struct sirfsoc_padmux lcdrom_padmux = { 224static const struct sirfsoc_padmux lcdrom_padmux = {
219 .muxmask_counts = ARRAY_SIZE(lcdrom_muxmask), 225 .muxmask_counts = ARRAY_SIZE(lcdrom_muxmask),
220 .muxmask = lcdrom_muxmask, 226 .muxmask = lcdrom_muxmask,
227 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
221 .funcmask = BIT(4), 228 .funcmask = BIT(4),
222 .funcval = BIT(4), 229 .funcval = BIT(4),
223}; 230};
@@ -238,6 +245,7 @@ static const struct sirfsoc_muxmask uart0_muxmask[] = {
238static const struct sirfsoc_padmux uart0_padmux = { 245static const struct sirfsoc_padmux uart0_padmux = {
239 .muxmask_counts = ARRAY_SIZE(uart0_muxmask), 246 .muxmask_counts = ARRAY_SIZE(uart0_muxmask),
240 .muxmask = uart0_muxmask, 247 .muxmask = uart0_muxmask,
248 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
241 .funcmask = BIT(9), 249 .funcmask = BIT(9),
242 .funcval = BIT(9), 250 .funcval = BIT(9),
243}; 251};
@@ -282,6 +290,7 @@ static const struct sirfsoc_muxmask uart2_muxmask[] = {
282static const struct sirfsoc_padmux uart2_padmux = { 290static const struct sirfsoc_padmux uart2_padmux = {
283 .muxmask_counts = ARRAY_SIZE(uart2_muxmask), 291 .muxmask_counts = ARRAY_SIZE(uart2_muxmask),
284 .muxmask = uart2_muxmask, 292 .muxmask = uart2_muxmask,
293 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
285 .funcmask = BIT(10), 294 .funcmask = BIT(10),
286 .funcval = BIT(10), 295 .funcval = BIT(10),
287}; 296};
@@ -315,6 +324,7 @@ static const struct sirfsoc_muxmask sdmmc3_muxmask[] = {
315static const struct sirfsoc_padmux sdmmc3_padmux = { 324static const struct sirfsoc_padmux sdmmc3_padmux = {
316 .muxmask_counts = ARRAY_SIZE(sdmmc3_muxmask), 325 .muxmask_counts = ARRAY_SIZE(sdmmc3_muxmask),
317 .muxmask = sdmmc3_muxmask, 326 .muxmask = sdmmc3_muxmask,
327 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
318 .funcmask = BIT(7), 328 .funcmask = BIT(7),
319 .funcval = 0, 329 .funcval = 0,
320}; 330};
@@ -331,6 +341,7 @@ static const struct sirfsoc_muxmask spi0_muxmask[] = {
331static const struct sirfsoc_padmux spi0_padmux = { 341static const struct sirfsoc_padmux spi0_padmux = {
332 .muxmask_counts = ARRAY_SIZE(spi0_muxmask), 342 .muxmask_counts = ARRAY_SIZE(spi0_muxmask),
333 .muxmask = spi0_muxmask, 343 .muxmask = spi0_muxmask,
344 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
334 .funcmask = BIT(7), 345 .funcmask = BIT(7),
335 .funcval = BIT(7), 346 .funcval = BIT(7),
336}; 347};
@@ -361,6 +372,7 @@ static const struct sirfsoc_muxmask cko1_muxmask[] = {
361static const struct sirfsoc_padmux cko1_padmux = { 372static const struct sirfsoc_padmux cko1_padmux = {
362 .muxmask_counts = ARRAY_SIZE(cko1_muxmask), 373 .muxmask_counts = ARRAY_SIZE(cko1_muxmask),
363 .muxmask = cko1_muxmask, 374 .muxmask = cko1_muxmask,
375 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
364 .funcmask = BIT(3), 376 .funcmask = BIT(3),
365 .funcval = 0, 377 .funcval = 0,
366}; 378};
@@ -379,6 +391,7 @@ static const struct sirfsoc_muxmask i2s_muxmask[] = {
379static const struct sirfsoc_padmux i2s_padmux = { 391static const struct sirfsoc_padmux i2s_padmux = {
380 .muxmask_counts = ARRAY_SIZE(i2s_muxmask), 392 .muxmask_counts = ARRAY_SIZE(i2s_muxmask),
381 .muxmask = i2s_muxmask, 393 .muxmask = i2s_muxmask,
394 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
382 .funcmask = BIT(3) | BIT(9), 395 .funcmask = BIT(3) | BIT(9),
383 .funcval = BIT(3), 396 .funcval = BIT(3),
384}; 397};
@@ -395,6 +408,7 @@ static const struct sirfsoc_muxmask ac97_muxmask[] = {
395static const struct sirfsoc_padmux ac97_padmux = { 408static const struct sirfsoc_padmux ac97_padmux = {
396 .muxmask_counts = ARRAY_SIZE(ac97_muxmask), 409 .muxmask_counts = ARRAY_SIZE(ac97_muxmask),
397 .muxmask = ac97_muxmask, 410 .muxmask = ac97_muxmask,
411 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
398 .funcmask = BIT(8), 412 .funcmask = BIT(8),
399 .funcval = 0, 413 .funcval = 0,
400}; 414};
@@ -411,6 +425,7 @@ static const struct sirfsoc_muxmask spi1_muxmask[] = {
411static const struct sirfsoc_padmux spi1_padmux = { 425static const struct sirfsoc_padmux spi1_padmux = {
412 .muxmask_counts = ARRAY_SIZE(spi1_muxmask), 426 .muxmask_counts = ARRAY_SIZE(spi1_muxmask),
413 .muxmask = spi1_muxmask, 427 .muxmask = spi1_muxmask,
428 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
414 .funcmask = BIT(8), 429 .funcmask = BIT(8),
415 .funcval = BIT(8), 430 .funcval = BIT(8),
416}; 431};
@@ -441,6 +456,7 @@ static const struct sirfsoc_muxmask gps_muxmask[] = {
441static const struct sirfsoc_padmux gps_padmux = { 456static const struct sirfsoc_padmux gps_padmux = {
442 .muxmask_counts = ARRAY_SIZE(gps_muxmask), 457 .muxmask_counts = ARRAY_SIZE(gps_muxmask),
443 .muxmask = gps_muxmask, 458 .muxmask = gps_muxmask,
459 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
444 .funcmask = BIT(12) | BIT(13) | BIT(14), 460 .funcmask = BIT(12) | BIT(13) | BIT(14),
445 .funcval = BIT(12), 461 .funcval = BIT(12),
446}; 462};
@@ -463,6 +479,7 @@ static const struct sirfsoc_muxmask sdmmc5_muxmask[] = {
463static const struct sirfsoc_padmux sdmmc5_padmux = { 479static const struct sirfsoc_padmux sdmmc5_padmux = {
464 .muxmask_counts = ARRAY_SIZE(sdmmc5_muxmask), 480 .muxmask_counts = ARRAY_SIZE(sdmmc5_muxmask),
465 .muxmask = sdmmc5_muxmask, 481 .muxmask = sdmmc5_muxmask,
482 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
466 .funcmask = BIT(13) | BIT(14), 483 .funcmask = BIT(13) | BIT(14),
467 .funcval = BIT(13) | BIT(14), 484 .funcval = BIT(13) | BIT(14),
468}; 485};
@@ -479,12 +496,27 @@ static const struct sirfsoc_muxmask usp0_muxmask[] = {
479static const struct sirfsoc_padmux usp0_padmux = { 496static const struct sirfsoc_padmux usp0_padmux = {
480 .muxmask_counts = ARRAY_SIZE(usp0_muxmask), 497 .muxmask_counts = ARRAY_SIZE(usp0_muxmask),
481 .muxmask = usp0_muxmask, 498 .muxmask = usp0_muxmask,
499 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
482 .funcmask = BIT(1) | BIT(2) | BIT(6) | BIT(9), 500 .funcmask = BIT(1) | BIT(2) | BIT(6) | BIT(9),
483 .funcval = 0, 501 .funcval = 0,
484}; 502};
485 503
486static const unsigned usp0_pins[] = { 51, 52, 53, 54, 55 }; 504static const unsigned usp0_pins[] = { 51, 52, 53, 54, 55 };
487 505
506static const struct sirfsoc_muxmask usp0_uart_nostreamctrl_muxmask[] = {
507 {
508 .group = 1,
509 .mask = BIT(20) | BIT(21),
510 },
511};
512
513static const struct sirfsoc_padmux usp0_uart_nostreamctrl_padmux = {
514 .muxmask_counts = ARRAY_SIZE(usp0_uart_nostreamctrl_muxmask),
515 .muxmask = usp0_uart_nostreamctrl_muxmask,
516};
517
518static const unsigned usp0_uart_nostreamctrl_pins[] = { 52, 53 };
519
488static const struct sirfsoc_muxmask usp1_muxmask[] = { 520static const struct sirfsoc_muxmask usp1_muxmask[] = {
489 { 521 {
490 .group = 1, 522 .group = 1,
@@ -495,12 +527,27 @@ static const struct sirfsoc_muxmask usp1_muxmask[] = {
495static const struct sirfsoc_padmux usp1_padmux = { 527static const struct sirfsoc_padmux usp1_padmux = {
496 .muxmask_counts = ARRAY_SIZE(usp1_muxmask), 528 .muxmask_counts = ARRAY_SIZE(usp1_muxmask),
497 .muxmask = usp1_muxmask, 529 .muxmask = usp1_muxmask,
530 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
498 .funcmask = BIT(1) | BIT(9) | BIT(10) | BIT(11), 531 .funcmask = BIT(1) | BIT(9) | BIT(10) | BIT(11),
499 .funcval = 0, 532 .funcval = 0,
500}; 533};
501 534
502static const unsigned usp1_pins[] = { 56, 57, 58, 59, 60 }; 535static const unsigned usp1_pins[] = { 56, 57, 58, 59, 60 };
503 536
537static const struct sirfsoc_muxmask usp1_uart_nostreamctrl_muxmask[] = {
538 {
539 .group = 1,
540 .mask = BIT(25) | BIT(26),
541 },
542};
543
544static const struct sirfsoc_padmux usp1_uart_nostreamctrl_padmux = {
545 .muxmask_counts = ARRAY_SIZE(usp1_uart_nostreamctrl_muxmask),
546 .muxmask = usp1_uart_nostreamctrl_muxmask,
547};
548
549static const unsigned usp1_uart_nostreamctrl_pins[] = { 57, 58 };
550
504static const struct sirfsoc_muxmask usp2_muxmask[] = { 551static const struct sirfsoc_muxmask usp2_muxmask[] = {
505 { 552 {
506 .group = 1, 553 .group = 1,
@@ -514,12 +561,27 @@ static const struct sirfsoc_muxmask usp2_muxmask[] = {
514static const struct sirfsoc_padmux usp2_padmux = { 561static const struct sirfsoc_padmux usp2_padmux = {
515 .muxmask_counts = ARRAY_SIZE(usp2_muxmask), 562 .muxmask_counts = ARRAY_SIZE(usp2_muxmask),
516 .muxmask = usp2_muxmask, 563 .muxmask = usp2_muxmask,
564 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
517 .funcmask = BIT(13) | BIT(14), 565 .funcmask = BIT(13) | BIT(14),
518 .funcval = 0, 566 .funcval = 0,
519}; 567};
520 568
521static const unsigned usp2_pins[] = { 61, 62, 63, 64, 65 }; 569static const unsigned usp2_pins[] = { 61, 62, 63, 64, 65 };
522 570
571static const struct sirfsoc_muxmask usp2_uart_nostreamctrl_muxmask[] = {
572 {
573 .group = 1,
574 .mask = BIT(30) | BIT(31),
575 },
576};
577
578static const struct sirfsoc_padmux usp2_uart_nostreamctrl_padmux = {
579 .muxmask_counts = ARRAY_SIZE(usp2_uart_nostreamctrl_muxmask),
580 .muxmask = usp2_uart_nostreamctrl_muxmask,
581};
582
583static const unsigned usp2_uart_nostreamctrl_pins[] = { 62, 63 };
584
523static const struct sirfsoc_muxmask nand_muxmask[] = { 585static const struct sirfsoc_muxmask nand_muxmask[] = {
524 { 586 {
525 .group = 2, 587 .group = 2,
@@ -530,6 +592,7 @@ static const struct sirfsoc_muxmask nand_muxmask[] = {
530static const struct sirfsoc_padmux nand_padmux = { 592static const struct sirfsoc_padmux nand_padmux = {
531 .muxmask_counts = ARRAY_SIZE(nand_muxmask), 593 .muxmask_counts = ARRAY_SIZE(nand_muxmask),
532 .muxmask = nand_muxmask, 594 .muxmask = nand_muxmask,
595 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
533 .funcmask = BIT(5), 596 .funcmask = BIT(5),
534 .funcval = 0, 597 .funcval = 0,
535}; 598};
@@ -538,6 +601,7 @@ static const unsigned nand_pins[] = { 64, 65, 92, 93, 94 };
538 601
539static const struct sirfsoc_padmux sdmmc0_padmux = { 602static const struct sirfsoc_padmux sdmmc0_padmux = {
540 .muxmask_counts = 0, 603 .muxmask_counts = 0,
604 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
541 .funcmask = BIT(5), 605 .funcmask = BIT(5),
542 .funcval = 0, 606 .funcval = 0,
543}; 607};
@@ -554,6 +618,7 @@ static const struct sirfsoc_muxmask sdmmc2_muxmask[] = {
554static const struct sirfsoc_padmux sdmmc2_padmux = { 618static const struct sirfsoc_padmux sdmmc2_padmux = {
555 .muxmask_counts = ARRAY_SIZE(sdmmc2_muxmask), 619 .muxmask_counts = ARRAY_SIZE(sdmmc2_muxmask),
556 .muxmask = sdmmc2_muxmask, 620 .muxmask = sdmmc2_muxmask,
621 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
557 .funcmask = BIT(5), 622 .funcmask = BIT(5),
558 .funcval = BIT(5), 623 .funcval = BIT(5),
559}; 624};
@@ -586,6 +651,7 @@ static const struct sirfsoc_muxmask vip_muxmask[] = {
586static const struct sirfsoc_padmux vip_padmux = { 651static const struct sirfsoc_padmux vip_padmux = {
587 .muxmask_counts = ARRAY_SIZE(vip_muxmask), 652 .muxmask_counts = ARRAY_SIZE(vip_muxmask),
588 .muxmask = vip_muxmask, 653 .muxmask = vip_muxmask,
654 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
589 .funcmask = BIT(0), 655 .funcmask = BIT(0),
590 .funcval = 0, 656 .funcval = 0,
591}; 657};
@@ -635,6 +701,7 @@ static const struct sirfsoc_muxmask viprom_muxmask[] = {
635static const struct sirfsoc_padmux viprom_padmux = { 701static const struct sirfsoc_padmux viprom_padmux = {
636 .muxmask_counts = ARRAY_SIZE(viprom_muxmask), 702 .muxmask_counts = ARRAY_SIZE(viprom_muxmask),
637 .muxmask = viprom_muxmask, 703 .muxmask = viprom_muxmask,
704 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
638 .funcmask = BIT(0), 705 .funcmask = BIT(0),
639 .funcval = BIT(0), 706 .funcval = BIT(0),
640}; 707};
@@ -651,6 +718,7 @@ static const struct sirfsoc_muxmask pwm0_muxmask[] = {
651static const struct sirfsoc_padmux pwm0_padmux = { 718static const struct sirfsoc_padmux pwm0_padmux = {
652 .muxmask_counts = ARRAY_SIZE(pwm0_muxmask), 719 .muxmask_counts = ARRAY_SIZE(pwm0_muxmask),
653 .muxmask = pwm0_muxmask, 720 .muxmask = pwm0_muxmask,
721 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
654 .funcmask = BIT(12), 722 .funcmask = BIT(12),
655 .funcval = 0, 723 .funcval = 0,
656}; 724};
@@ -722,6 +790,7 @@ static const struct sirfsoc_muxmask usb0_utmi_drvbus_muxmask[] = {
722static const struct sirfsoc_padmux usb0_utmi_drvbus_padmux = { 790static const struct sirfsoc_padmux usb0_utmi_drvbus_padmux = {
723 .muxmask_counts = ARRAY_SIZE(usb0_utmi_drvbus_muxmask), 791 .muxmask_counts = ARRAY_SIZE(usb0_utmi_drvbus_muxmask),
724 .muxmask = usb0_utmi_drvbus_muxmask, 792 .muxmask = usb0_utmi_drvbus_muxmask,
793 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
725 .funcmask = BIT(6), 794 .funcmask = BIT(6),
726 .funcval = BIT(6), /* refer to PAD_UTMI_DRVVBUS0_ENABLE */ 795 .funcval = BIT(6), /* refer to PAD_UTMI_DRVVBUS0_ENABLE */
727}; 796};
@@ -738,12 +807,31 @@ static const struct sirfsoc_muxmask usb1_utmi_drvbus_muxmask[] = {
738static const struct sirfsoc_padmux usb1_utmi_drvbus_padmux = { 807static const struct sirfsoc_padmux usb1_utmi_drvbus_padmux = {
739 .muxmask_counts = ARRAY_SIZE(usb1_utmi_drvbus_muxmask), 808 .muxmask_counts = ARRAY_SIZE(usb1_utmi_drvbus_muxmask),
740 .muxmask = usb1_utmi_drvbus_muxmask, 809 .muxmask = usb1_utmi_drvbus_muxmask,
810 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
741 .funcmask = BIT(11), 811 .funcmask = BIT(11),
742 .funcval = BIT(11), /* refer to PAD_UTMI_DRVVBUS1_ENABLE */ 812 .funcval = BIT(11), /* refer to PAD_UTMI_DRVVBUS1_ENABLE */
743}; 813};
744 814
745static const unsigned usb1_utmi_drvbus_pins[] = { 59 }; 815static const unsigned usb1_utmi_drvbus_pins[] = { 59 };
746 816
817static const struct sirfsoc_padmux usb1_dp_dn_padmux = {
818 .muxmask_counts = 0,
819 .ctrlreg = SIRFSOC_RSC_USB_UART_SHARE,
820 .funcmask = BIT(2),
821 .funcval = BIT(2),
822};
823
824static const unsigned usb1_dp_dn_pins[] = { 115, 116 };
825
826static const struct sirfsoc_padmux uart1_route_io_usb1_padmux = {
827 .muxmask_counts = 0,
828 .ctrlreg = SIRFSOC_RSC_USB_UART_SHARE,
829 .funcmask = BIT(2),
830 .funcval = 0,
831};
832
833static const unsigned uart1_route_io_usb1_pins[] = { 115, 116 };
834
747static const struct sirfsoc_muxmask pulse_count_muxmask[] = { 835static const struct sirfsoc_muxmask pulse_count_muxmask[] = {
748 { 836 {
749 .group = 0, 837 .group = 0,
@@ -764,12 +852,19 @@ static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
764 SIRFSOC_PIN_GROUP("lcd_24bitsgrp", lcd_24bits_pins), 852 SIRFSOC_PIN_GROUP("lcd_24bitsgrp", lcd_24bits_pins),
765 SIRFSOC_PIN_GROUP("lcdrom_grp", lcdrom_pins), 853 SIRFSOC_PIN_GROUP("lcdrom_grp", lcdrom_pins),
766 SIRFSOC_PIN_GROUP("uart0grp", uart0_pins), 854 SIRFSOC_PIN_GROUP("uart0grp", uart0_pins),
855 SIRFSOC_PIN_GROUP("uart0_nostreamctrlgrp", uart0_nostreamctrl_pins),
767 SIRFSOC_PIN_GROUP("uart1grp", uart1_pins), 856 SIRFSOC_PIN_GROUP("uart1grp", uart1_pins),
768 SIRFSOC_PIN_GROUP("uart2grp", uart2_pins), 857 SIRFSOC_PIN_GROUP("uart2grp", uart2_pins),
769 SIRFSOC_PIN_GROUP("uart2_nostreamctrlgrp", uart2_nostreamctrl_pins), 858 SIRFSOC_PIN_GROUP("uart2_nostreamctrlgrp", uart2_nostreamctrl_pins),
770 SIRFSOC_PIN_GROUP("usp0grp", usp0_pins), 859 SIRFSOC_PIN_GROUP("usp0grp", usp0_pins),
860 SIRFSOC_PIN_GROUP("usp0_uart_nostreamctrl_grp",
861 usp0_uart_nostreamctrl_pins),
771 SIRFSOC_PIN_GROUP("usp1grp", usp1_pins), 862 SIRFSOC_PIN_GROUP("usp1grp", usp1_pins),
863 SIRFSOC_PIN_GROUP("usp1_uart_nostreamctrl_grp",
864 usp1_uart_nostreamctrl_pins),
772 SIRFSOC_PIN_GROUP("usp2grp", usp2_pins), 865 SIRFSOC_PIN_GROUP("usp2grp", usp2_pins),
866 SIRFSOC_PIN_GROUP("usp2_uart_nostreamctrl_grp",
867 usp2_uart_nostreamctrl_pins),
773 SIRFSOC_PIN_GROUP("i2c0grp", i2c0_pins), 868 SIRFSOC_PIN_GROUP("i2c0grp", i2c0_pins),
774 SIRFSOC_PIN_GROUP("i2c1grp", i2c1_pins), 869 SIRFSOC_PIN_GROUP("i2c1grp", i2c1_pins),
775 SIRFSOC_PIN_GROUP("pwm0grp", pwm0_pins), 870 SIRFSOC_PIN_GROUP("pwm0grp", pwm0_pins),
@@ -789,6 +884,8 @@ static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
789 SIRFSOC_PIN_GROUP("sdmmc5grp", sdmmc5_pins), 884 SIRFSOC_PIN_GROUP("sdmmc5grp", sdmmc5_pins),
790 SIRFSOC_PIN_GROUP("usb0_utmi_drvbusgrp", usb0_utmi_drvbus_pins), 885 SIRFSOC_PIN_GROUP("usb0_utmi_drvbusgrp", usb0_utmi_drvbus_pins),
791 SIRFSOC_PIN_GROUP("usb1_utmi_drvbusgrp", usb1_utmi_drvbus_pins), 886 SIRFSOC_PIN_GROUP("usb1_utmi_drvbusgrp", usb1_utmi_drvbus_pins),
887 SIRFSOC_PIN_GROUP("usb1_dp_dngrp", usb1_dp_dn_pins),
888 SIRFSOC_PIN_GROUP("uart1_route_io_usb1grp", uart1_route_io_usb1_pins),
792 SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins), 889 SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins),
793 SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins), 890 SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins),
794 SIRFSOC_PIN_GROUP("ac97grp", ac97_pins), 891 SIRFSOC_PIN_GROUP("ac97grp", ac97_pins),
@@ -803,12 +900,19 @@ static const char * const lcd_18bitsgrp[] = { "lcd_18bitsgrp" };
803static const char * const lcd_24bitsgrp[] = { "lcd_24bitsgrp" }; 900static const char * const lcd_24bitsgrp[] = { "lcd_24bitsgrp" };
804static const char * const lcdromgrp[] = { "lcdromgrp" }; 901static const char * const lcdromgrp[] = { "lcdromgrp" };
805static const char * const uart0grp[] = { "uart0grp" }; 902static const char * const uart0grp[] = { "uart0grp" };
903static const char * const uart0_nostreamctrlgrp[] = { "uart0_nostreamctrlgrp" };
806static const char * const uart1grp[] = { "uart1grp" }; 904static const char * const uart1grp[] = { "uart1grp" };
807static const char * const uart2grp[] = { "uart2grp" }; 905static const char * const uart2grp[] = { "uart2grp" };
808static const char * const uart2_nostreamctrlgrp[] = { "uart2_nostreamctrlgrp" }; 906static const char * const uart2_nostreamctrlgrp[] = { "uart2_nostreamctrlgrp" };
809static const char * const usp0grp[] = { "usp0grp" }; 907static const char * const usp0grp[] = { "usp0grp" };
908static const char * const usp0_uart_nostreamctrl_grp[] =
909 { "usp0_uart_nostreamctrl_grp" };
810static const char * const usp1grp[] = { "usp1grp" }; 910static const char * const usp1grp[] = { "usp1grp" };
911static const char * const usp1_uart_nostreamctrl_grp[] =
912 { "usp1_uart_nostreamctrl_grp" };
811static const char * const usp2grp[] = { "usp2grp" }; 913static const char * const usp2grp[] = { "usp2grp" };
914static const char * const usp2_uart_nostreamctrl_grp[] =
915 { "usp2_uart_nostreamctrl_grp" };
812static const char * const i2c0grp[] = { "i2c0grp" }; 916static const char * const i2c0grp[] = { "i2c0grp" };
813static const char * const i2c1grp[] = { "i2c1grp" }; 917static const char * const i2c1grp[] = { "i2c1grp" };
814static const char * const pwm0grp[] = { "pwm0grp" }; 918static const char * const pwm0grp[] = { "pwm0grp" };
@@ -828,6 +932,8 @@ static const char * const sdmmc4grp[] = { "sdmmc4grp" };
828static const char * const sdmmc5grp[] = { "sdmmc5grp" }; 932static const char * const sdmmc5grp[] = { "sdmmc5grp" };
829static const char * const usb0_utmi_drvbusgrp[] = { "usb0_utmi_drvbusgrp" }; 933static const char * const usb0_utmi_drvbusgrp[] = { "usb0_utmi_drvbusgrp" };
830static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" }; 934static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" };
935static const char * const usb1_dp_dngrp[] = { "usb1_dp_dngrp" };
936static const char * const uart1_route_io_usb1grp[] = { "uart1_route_io_usb1grp" };
831static const char * const pulse_countgrp[] = { "pulse_countgrp" }; 937static const char * const pulse_countgrp[] = { "pulse_countgrp" };
832static const char * const i2sgrp[] = { "i2sgrp" }; 938static const char * const i2sgrp[] = { "i2sgrp" };
833static const char * const ac97grp[] = { "ac97grp" }; 939static const char * const ac97grp[] = { "ac97grp" };
@@ -842,12 +948,19 @@ static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = {
842 SIRFSOC_PMX_FUNCTION("lcd_24bits", lcd_24bitsgrp, lcd_24bits_padmux), 948 SIRFSOC_PMX_FUNCTION("lcd_24bits", lcd_24bitsgrp, lcd_24bits_padmux),
843 SIRFSOC_PMX_FUNCTION("lcdrom", lcdromgrp, lcdrom_padmux), 949 SIRFSOC_PMX_FUNCTION("lcdrom", lcdromgrp, lcdrom_padmux),
844 SIRFSOC_PMX_FUNCTION("uart0", uart0grp, uart0_padmux), 950 SIRFSOC_PMX_FUNCTION("uart0", uart0grp, uart0_padmux),
951 SIRFSOC_PMX_FUNCTION("uart0_nostreamctrl", uart0_nostreamctrlgrp, uart0_nostreamctrl_padmux),
845 SIRFSOC_PMX_FUNCTION("uart1", uart1grp, uart1_padmux), 952 SIRFSOC_PMX_FUNCTION("uart1", uart1grp, uart1_padmux),
846 SIRFSOC_PMX_FUNCTION("uart2", uart2grp, uart2_padmux), 953 SIRFSOC_PMX_FUNCTION("uart2", uart2grp, uart2_padmux),
847 SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl", uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux), 954 SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl", uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux),
848 SIRFSOC_PMX_FUNCTION("usp0", usp0grp, usp0_padmux), 955 SIRFSOC_PMX_FUNCTION("usp0", usp0grp, usp0_padmux),
956 SIRFSOC_PMX_FUNCTION("usp0_uart_nostreamctrl",
957 usp0_uart_nostreamctrl_grp, usp0_uart_nostreamctrl_padmux),
849 SIRFSOC_PMX_FUNCTION("usp1", usp1grp, usp1_padmux), 958 SIRFSOC_PMX_FUNCTION("usp1", usp1grp, usp1_padmux),
959 SIRFSOC_PMX_FUNCTION("usp1_uart_nostreamctrl",
960 usp1_uart_nostreamctrl_grp, usp1_uart_nostreamctrl_padmux),
850 SIRFSOC_PMX_FUNCTION("usp2", usp2grp, usp2_padmux), 961 SIRFSOC_PMX_FUNCTION("usp2", usp2grp, usp2_padmux),
962 SIRFSOC_PMX_FUNCTION("usp2_uart_nostreamctrl",
963 usp2_uart_nostreamctrl_grp, usp2_uart_nostreamctrl_padmux),
851 SIRFSOC_PMX_FUNCTION("i2c0", i2c0grp, i2c0_padmux), 964 SIRFSOC_PMX_FUNCTION("i2c0", i2c0grp, i2c0_padmux),
852 SIRFSOC_PMX_FUNCTION("i2c1", i2c1grp, i2c1_padmux), 965 SIRFSOC_PMX_FUNCTION("i2c1", i2c1grp, i2c1_padmux),
853 SIRFSOC_PMX_FUNCTION("pwm0", pwm0grp, pwm0_padmux), 966 SIRFSOC_PMX_FUNCTION("pwm0", pwm0grp, pwm0_padmux),
@@ -867,6 +980,8 @@ static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = {
867 SIRFSOC_PMX_FUNCTION("sdmmc5", sdmmc5grp, sdmmc5_padmux), 980 SIRFSOC_PMX_FUNCTION("sdmmc5", sdmmc5grp, sdmmc5_padmux),
868 SIRFSOC_PMX_FUNCTION("usb0_utmi_drvbus", usb0_utmi_drvbusgrp, usb0_utmi_drvbus_padmux), 981 SIRFSOC_PMX_FUNCTION("usb0_utmi_drvbus", usb0_utmi_drvbusgrp, usb0_utmi_drvbus_padmux),
869 SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus", usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux), 982 SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus", usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux),
983 SIRFSOC_PMX_FUNCTION("usb1_dp_dn", usb1_dp_dngrp, usb1_dp_dn_padmux),
984 SIRFSOC_PMX_FUNCTION("uart1_route_io_usb1", uart1_route_io_usb1grp, uart1_route_io_usb1_padmux),
870 SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux), 985 SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux),
871 SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux), 986 SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux),
872 SIRFSOC_PMX_FUNCTION("ac97", ac97grp, ac97_padmux), 987 SIRFSOC_PMX_FUNCTION("ac97", ac97grp, ac97_padmux),
diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.c b/drivers/pinctrl/sirf/pinctrl-sirf.c
index 26f946af7933..b81e388c50de 100644
--- a/drivers/pinctrl/sirf/pinctrl-sirf.c
+++ b/drivers/pinctrl/sirf/pinctrl-sirf.c
@@ -166,12 +166,12 @@ static void sirfsoc_pinmux_endisable(struct sirfsoc_pmx *spmx, unsigned selector
166 166
167 if (mux->funcmask && enable) { 167 if (mux->funcmask && enable) {
168 u32 func_en_val; 168 u32 func_en_val;
169
169 func_en_val = 170 func_en_val =
170 readl(spmx->rsc_virtbase + SIRFSOC_RSC_PIN_MUX); 171 readl(spmx->rsc_virtbase + mux->ctrlreg);
171 func_en_val = 172 func_en_val =
172 (func_en_val & ~mux->funcmask) | (mux-> 173 (func_en_val & ~mux->funcmask) | (mux->funcval);
173 funcval); 174 writel(func_en_val, spmx->rsc_virtbase + mux->ctrlreg);
174 writel(func_en_val, spmx->rsc_virtbase + SIRFSOC_RSC_PIN_MUX);
175 } 175 }
176} 176}
177 177
diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.h b/drivers/pinctrl/sirf/pinctrl-sirf.h
index 17cc108510ba..d7f16b499ad9 100644
--- a/drivers/pinctrl/sirf/pinctrl-sirf.h
+++ b/drivers/pinctrl/sirf/pinctrl-sirf.h
@@ -9,8 +9,9 @@
9#ifndef __PINMUX_SIRF_H__ 9#ifndef __PINMUX_SIRF_H__
10#define __PINMUX_SIRF_H__ 10#define __PINMUX_SIRF_H__
11 11
12#define SIRFSOC_NUM_PADS 622 12#define SIRFSOC_NUM_PADS 622
13#define SIRFSOC_RSC_PIN_MUX 0x4 13#define SIRFSOC_RSC_USB_UART_SHARE 0
14#define SIRFSOC_RSC_PIN_MUX 0x4
14 15
15#define SIRFSOC_GPIO_PAD_EN(g) ((g)*0x100 + 0x84) 16#define SIRFSOC_GPIO_PAD_EN(g) ((g)*0x100 + 0x84)
16#define SIRFSOC_GPIO_PAD_EN_CLR(g) ((g)*0x100 + 0x90) 17#define SIRFSOC_GPIO_PAD_EN_CLR(g) ((g)*0x100 + 0x90)
@@ -61,6 +62,7 @@ struct sirfsoc_padmux {
61 unsigned long muxmask_counts; 62 unsigned long muxmask_counts;
62 const struct sirfsoc_muxmask *muxmask; 63 const struct sirfsoc_muxmask *muxmask;
63 /* RSC_PIN_MUX set */ 64 /* RSC_PIN_MUX set */
65 unsigned long ctrlreg;
64 unsigned long funcmask; 66 unsigned long funcmask;
65 unsigned long funcval; 67 unsigned long funcval;
66}; 68};
diff --git a/drivers/pinctrl/spear/pinctrl-plgpio.c b/drivers/pinctrl/spear/pinctrl-plgpio.c
index 0a7f0bdbaa7d..ff2940e9f2a7 100644
--- a/drivers/pinctrl/spear/pinctrl-plgpio.c
+++ b/drivers/pinctrl/spear/pinctrl-plgpio.c
@@ -735,7 +735,7 @@ static struct platform_driver plgpio_driver = {
735 .owner = THIS_MODULE, 735 .owner = THIS_MODULE,
736 .name = "spear-plgpio", 736 .name = "spear-plgpio",
737 .pm = &plgpio_dev_pm_ops, 737 .pm = &plgpio_dev_pm_ops,
738 .of_match_table = of_match_ptr(plgpio_of_match), 738 .of_match_table = plgpio_of_match,
739 }, 739 },
740}; 740};
741 741
diff --git a/include/dt-bindings/pinctrl/at91.h b/include/dt-bindings/pinctrl/at91.h
index d7988b4d8af9..0fee6ff77ffc 100644
--- a/include/dt-bindings/pinctrl/at91.h
+++ b/include/dt-bindings/pinctrl/at91.h
@@ -16,7 +16,7 @@
16#define AT91_PINCTRL_PULL_DOWN (1 << 3) 16#define AT91_PINCTRL_PULL_DOWN (1 << 3)
17#define AT91_PINCTRL_DIS_SCHMIT (1 << 4) 17#define AT91_PINCTRL_DIS_SCHMIT (1 << 4)
18#define AT91_PINCTRL_DEBOUNCE (1 << 16) 18#define AT91_PINCTRL_DEBOUNCE (1 << 16)
19#define AT91_PINCTRL_DEBOUNCE_VA(x) (x << 17) 19#define AT91_PINCTRL_DEBOUNCE_VAL(x) (x << 17)
20 20
21#define AT91_PINCTRL_PULL_UP_DEGLITCH (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DEGLITCH) 21#define AT91_PINCTRL_PULL_UP_DEGLITCH (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DEGLITCH)
22 22
diff --git a/include/linux/platform_data/pinctrl-adi2.h b/include/linux/platform_data/pinctrl-adi2.h
new file mode 100644
index 000000000000..8f91300617ec
--- /dev/null
+++ b/include/linux/platform_data/pinctrl-adi2.h
@@ -0,0 +1,40 @@
1/*
2 * Pinctrl Driver for ADI GPIO2 controller
3 *
4 * Copyright 2007-2013 Analog Devices Inc.
5 *
6 * Licensed under the GPLv2 or later
7 */
8
9
10#ifndef PINCTRL_ADI2_H
11#define PINCTRL_ADI2_H
12
13#include <linux/io.h>
14#include <linux/platform_device.h>
15
16/**
17 * struct adi_pinctrl_gpio_platform_data - Pinctrl gpio platform data
18 * for ADI GPIO2 device.
19 *
20 * @port_gpio_base: Optional global GPIO index of the GPIO bank.
21 * 0 means driver decides.
22 * @port_pin_base: Pin index of the pin controller device.
23 * @port_width: PIN number of the GPIO bank device
24 * @pint_id: GPIO PINT device id that this GPIO bank should map to.
25 * @pint_assign: The 32-bit GPIO PINT registers can be divided into 2 parts. A
26 * GPIO bank can be mapped into either low 16 bits[0] or high 16
27 * bits[1] of each PINT register.
28 * @pint_map: GIOP bank mapping code in PINT device
29 */
30struct adi_pinctrl_gpio_platform_data {
31 unsigned int port_gpio_base;
32 unsigned int port_pin_base;
33 unsigned int port_width;
34 u8 pinctrl_id;
35 u8 pint_id;
36 bool pint_assign;
37 u8 pint_map;
38};
39
40#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-14 10:18:47 -0400