3 files changed, 43 insertions, 3 deletions
diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index ad9c2db59670..8b11fbd58071 100644
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -26,11 +26,21 @@
                #size-cells = <0>;
                enable-method = "rockchip,rk3066-smp";
-                cpu@0 {
+                cpu0: cpu@0 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
                        next-level-cache = <&L2>;
                        reg = <0x0>;
+                        operating-points = <
+                                /* kHz    uV */
+                                1008000 1075000
+                                 816000 1025000
+                                 600000 1025000
+                                 504000 1000000
+                                 312000  975000
+                        >;
+                        clock-latency = <40000>;
+                        clocks = <&cru ARMCLK>;
                };
                cpu@1 {
                        device_type = "cpu";
diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi
index ddaada788b45..ae4f04984d86 100644
--- a/arch/arm/boot/dts/rk3188.dtsi
+++ b/arch/arm/boot/dts/rk3188.dtsi
@@ -26,11 +26,24 @@
                #size-cells = <0>;
                enable-method = "rockchip,rk3066-smp";
-                cpu@0 {
+                cpu0: cpu@0 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
                        next-level-cache = <&L2>;
                        reg = <0x0>;
+                        operating-points = <
+                                /* kHz    uV */
+                                1608000 1350000
+                                1416000 1250000
+                                1200000 1150000
+                                1008000 1075000
+                                 816000  975000
+                                 600000  950000
+                                 504000  925000
+                                 312000  875000
+                        >;
+                        clock-latency = <40000>;
+                        clocks = <&cru ARMCLK>;
                };
                cpu@1 {
                        device_type = "cpu";
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 874e66dbb93b..cb18bb457568 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -47,10 +47,27 @@
                #address-cells = <1>;
                #size-cells = <0>;
-                cpu@500 {
+                cpu0: cpu@500 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a12";
                        reg = <0x500>;
+                        operating-points = <
+                                /* KHz    uV */
+                                1608000 1350000
+                                1512000 1300000
+                                1416000 1200000
+                                1200000 1100000
+                                1008000 1050000
+                                 816000 1000000
+                                 696000  950000
+                                 600000  900000
+                                 408000  900000
+                                 312000  900000
+                                 216000  900000
+                                 126000  900000
+                        >;
+                        clock-latency = <40000>;
+                        clocks = <&cru ARMCLK>;
                };
                cpu@501 {
                        device_type = "cpu";

diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index ad9c2db59670..8b11fbd58071 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -26,11 +26,21 @@
26	#size-cells = <0>;	26	#size-cells = <0>;
27	enable-method = "rockchip,rk3066-smp";	27	enable-method = "rockchip,rk3066-smp";
28		28
29	cpu@0 {	29	cpu0: cpu@0 {
30	device_type = "cpu";	30	device_type = "cpu";
31	compatible = "arm,cortex-a9";	31	compatible = "arm,cortex-a9";
32	next-level-cache = <&L2>;	32	next-level-cache = <&L2>;
33	reg = <0x0>;	33	reg = <0x0>;
		34	operating-points = <
		35	/* kHz uV */
		36	1008000 1075000
		37	816000 1025000
		38	600000 1025000
		39	504000 1000000
		40	312000 975000
		41	>;
		42	clock-latency = <40000>;
		43	clocks = <&cru ARMCLK>;
34	};	44	};
35	cpu@1 {	45	cpu@1 {
36	device_type = "cpu";	46	device_type = "cpu";


diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index ddaada788b45..ae4f04984d86 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi
@@ -26,11 +26,24 @@
26	#size-cells = <0>;	26	#size-cells = <0>;
27	enable-method = "rockchip,rk3066-smp";	27	enable-method = "rockchip,rk3066-smp";
28		28
29	cpu@0 {	29	cpu0: cpu@0 {
30	device_type = "cpu";	30	device_type = "cpu";
31	compatible = "arm,cortex-a9";	31	compatible = "arm,cortex-a9";
32	next-level-cache = <&L2>;	32	next-level-cache = <&L2>;
33	reg = <0x0>;	33	reg = <0x0>;
		34	operating-points = <
		35	/* kHz uV */
		36	1608000 1350000
		37	1416000 1250000
		38	1200000 1150000
		39	1008000 1075000
		40	816000 975000
		41	600000 950000
		42	504000 925000
		43	312000 875000
		44	>;
		45	clock-latency = <40000>;
		46	clocks = <&cru ARMCLK>;
34	};	47	};
35	cpu@1 {	48	cpu@1 {
36	device_type = "cpu";	49	device_type = "cpu";


diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 874e66dbb93b..cb18bb457568 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -47,10 +47,27 @@
47	#address-cells = <1>;	47	#address-cells = <1>;
48	#size-cells = <0>;	48	#size-cells = <0>;
49		49
50	cpu@500 {	50	cpu0: cpu@500 {
51	device_type = "cpu";	51	device_type = "cpu";
52	compatible = "arm,cortex-a12";	52	compatible = "arm,cortex-a12";
53	reg = <0x500>;	53	reg = <0x500>;
		54	operating-points = <
		55	/* KHz uV */
		56	1608000 1350000
		57	1512000 1300000
		58	1416000 1200000
		59	1200000 1100000
		60	1008000 1050000
		61	816000 1000000
		62	696000 950000
		63	600000 900000
		64	408000 900000
		65	312000 900000
		66	216000 900000
		67	126000 900000
		68	>;
		69	clock-latency = <40000>;
		70	clocks = <&cru ARMCLK>;
54	};	71	};
55	cpu@501 {	72	cpu@501 {
56	device_type = "cpu";	73	device_type = "cpu";