diff options
-rw-r--r-- | arch/mips/alchemy/devboards/pb1000/board_setup.c | 2 | ||||
-rw-r--r-- | arch/mips/alchemy/devboards/pb1500/board_setup.c | 2 | ||||
-rw-r--r-- | arch/mips/alchemy/mtx-1/board_setup.c | 2 | ||||
-rw-r--r-- | arch/mips/alchemy/mtx-1/platform.c | 4 | ||||
-rw-r--r-- | arch/mips/include/asm/mach-au1x00/au1000.h | 27 | ||||
-rw-r--r-- | arch/mips/include/asm/mach-au1x00/gpio-au1000.h | 71 | ||||
-rw-r--r-- | drivers/mtd/nand/au1550nd.c | 3 | ||||
-rw-r--r-- | drivers/watchdog/mtx-1_wdt.c | 21 |
8 files changed, 70 insertions, 62 deletions
diff --git a/arch/mips/alchemy/devboards/pb1000/board_setup.c b/arch/mips/alchemy/devboards/pb1000/board_setup.c index 2d85c4b5be09..e64fdcbf75d0 100644 --- a/arch/mips/alchemy/devboards/pb1000/board_setup.c +++ b/arch/mips/alchemy/devboards/pb1000/board_setup.c | |||
@@ -65,7 +65,7 @@ void __init board_setup(void) | |||
65 | 65 | ||
66 | /* Set AUX clock to 12 MHz * 8 = 96 MHz */ | 66 | /* Set AUX clock to 12 MHz * 8 = 96 MHz */ |
67 | au_writel(8, SYS_AUXPLL); | 67 | au_writel(8, SYS_AUXPLL); |
68 | au_writel(0, SYS_PINSTATERD); | 68 | alchemy_gpio1_input_enable(); |
69 | udelay(100); | 69 | udelay(100); |
70 | 70 | ||
71 | #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) | 71 | #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) |
diff --git a/arch/mips/alchemy/devboards/pb1500/board_setup.c b/arch/mips/alchemy/devboards/pb1500/board_setup.c index 83f46215eb0c..3b4fa3206969 100644 --- a/arch/mips/alchemy/devboards/pb1500/board_setup.c +++ b/arch/mips/alchemy/devboards/pb1500/board_setup.c | |||
@@ -56,7 +56,7 @@ void __init board_setup(void) | |||
56 | sys_clksrc = sys_freqctrl = pin_func = 0; | 56 | sys_clksrc = sys_freqctrl = pin_func = 0; |
57 | /* Set AUX clock to 12 MHz * 8 = 96 MHz */ | 57 | /* Set AUX clock to 12 MHz * 8 = 96 MHz */ |
58 | au_writel(8, SYS_AUXPLL); | 58 | au_writel(8, SYS_AUXPLL); |
59 | au_writel(0, SYS_PINSTATERD); | 59 | alchemy_gpio1_input_enable(); |
60 | udelay(100); | 60 | udelay(100); |
61 | 61 | ||
62 | /* GPIO201 is input for PCMCIA card detect */ | 62 | /* GPIO201 is input for PCMCIA card detect */ |
diff --git a/arch/mips/alchemy/mtx-1/board_setup.c b/arch/mips/alchemy/mtx-1/board_setup.c index cf436ab679ae..3ae984cf98cf 100644 --- a/arch/mips/alchemy/mtx-1/board_setup.c +++ b/arch/mips/alchemy/mtx-1/board_setup.c | |||
@@ -87,7 +87,7 @@ void __init board_setup(void) | |||
87 | au_writel(SYS_PF_NI2, SYS_PINFUNC); | 87 | au_writel(SYS_PF_NI2, SYS_PINFUNC); |
88 | 88 | ||
89 | /* Initialize GPIO */ | 89 | /* Initialize GPIO */ |
90 | au_writel(0xFFFFFFFF, SYS_TRIOUTCLR); | 90 | au_writel(~0, KSEG1ADDR(AU1000_SYS_PHYS_ADDR) + SYS_TRIOUTCLR); |
91 | alchemy_gpio_direction_output(0, 0); /* Disable M66EN (PCI 66MHz) */ | 91 | alchemy_gpio_direction_output(0, 0); /* Disable M66EN (PCI 66MHz) */ |
92 | alchemy_gpio_direction_output(3, 1); /* Disable PCI CLKRUN# */ | 92 | alchemy_gpio_direction_output(3, 1); /* Disable PCI CLKRUN# */ |
93 | alchemy_gpio_direction_output(1, 1); /* Enable EXT_IO3 */ | 93 | alchemy_gpio_direction_output(1, 1); /* Enable EXT_IO3 */ |
diff --git a/arch/mips/alchemy/mtx-1/platform.c b/arch/mips/alchemy/mtx-1/platform.c index 956f946218c5..55628e390fd7 100644 --- a/arch/mips/alchemy/mtx-1/platform.c +++ b/arch/mips/alchemy/mtx-1/platform.c | |||
@@ -53,8 +53,8 @@ static struct platform_device mtx1_button = { | |||
53 | 53 | ||
54 | static struct resource mtx1_wdt_res[] = { | 54 | static struct resource mtx1_wdt_res[] = { |
55 | [0] = { | 55 | [0] = { |
56 | .start = 15, | 56 | .start = 215, |
57 | .end = 15, | 57 | .end = 215, |
58 | .name = "mtx1-wdt-gpio", | 58 | .name = "mtx1-wdt-gpio", |
59 | .flags = IORESOURCE_IRQ, | 59 | .flags = IORESOURCE_IRQ, |
60 | } | 60 | } |
diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index 2dfff4f26512..f260ebed713b 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h | |||
@@ -702,7 +702,9 @@ enum soc_au1200_ints { | |||
702 | #define AU1000_UART1_PHYS_ADDR 0x11200000 /* 0234 */ | 702 | #define AU1000_UART1_PHYS_ADDR 0x11200000 /* 0234 */ |
703 | #define AU1000_UART2_PHYS_ADDR 0x11300000 /* 0 */ | 703 | #define AU1000_UART2_PHYS_ADDR 0x11300000 /* 0 */ |
704 | #define AU1000_UART3_PHYS_ADDR 0x11400000 /* 0123 */ | 704 | #define AU1000_UART3_PHYS_ADDR 0x11400000 /* 0123 */ |
705 | #define AU1500_GPIO2_PHYS_ADDR 0x11700000 /* 1234 */ | ||
705 | #define AU1000_IC1_PHYS_ADDR 0x11800000 /* 01234 */ | 706 | #define AU1000_IC1_PHYS_ADDR 0x11800000 /* 01234 */ |
707 | #define AU1000_SYS_PHYS_ADDR 0x11900000 /* 01234 */ | ||
706 | #define AU1000_DMA_PHYS_ADDR 0x14002000 /* 012 */ | 708 | #define AU1000_DMA_PHYS_ADDR 0x14002000 /* 012 */ |
707 | #define AU1550_DBDMA_PHYS_ADDR 0x14002000 /* 34 */ | 709 | #define AU1550_DBDMA_PHYS_ADDR 0x14002000 /* 34 */ |
708 | #define AU1550_DBDMA_CONF_PHYS_ADDR 0x14003000 /* 34 */ | 710 | #define AU1550_DBDMA_CONF_PHYS_ADDR 0x14003000 /* 34 */ |
@@ -717,7 +719,6 @@ enum soc_au1200_ints { | |||
717 | #define IRDA_PHYS_ADDR 0x10300000 | 719 | #define IRDA_PHYS_ADDR 0x10300000 |
718 | #define SSI0_PHYS_ADDR 0x11600000 | 720 | #define SSI0_PHYS_ADDR 0x11600000 |
719 | #define SSI1_PHYS_ADDR 0x11680000 | 721 | #define SSI1_PHYS_ADDR 0x11680000 |
720 | #define SYS_PHYS_ADDR 0x11900000 | ||
721 | #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL | 722 | #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL |
722 | #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL | 723 | #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL |
723 | #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL | 724 | #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL |
@@ -730,8 +731,6 @@ enum soc_au1200_ints { | |||
730 | #define STATIC_MEM_PHYS_ADDR 0x14001000 | 731 | #define STATIC_MEM_PHYS_ADDR 0x14001000 |
731 | #define USBH_PHYS_ADDR 0x10100000 | 732 | #define USBH_PHYS_ADDR 0x10100000 |
732 | #define PCI_PHYS_ADDR 0x14005000 | 733 | #define PCI_PHYS_ADDR 0x14005000 |
733 | #define GPIO2_PHYS_ADDR 0x11700000 | ||
734 | #define SYS_PHYS_ADDR 0x11900000 | ||
735 | #define PCI_MEM_PHYS_ADDR 0x400000000ULL | 734 | #define PCI_MEM_PHYS_ADDR 0x400000000ULL |
736 | #define PCI_IO_PHYS_ADDR 0x500000000ULL | 735 | #define PCI_IO_PHYS_ADDR 0x500000000ULL |
737 | #define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL | 736 | #define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL |
@@ -750,8 +749,6 @@ enum soc_au1200_ints { | |||
750 | #define IRDA_PHYS_ADDR 0x10300000 | 749 | #define IRDA_PHYS_ADDR 0x10300000 |
751 | #define SSI0_PHYS_ADDR 0x11600000 | 750 | #define SSI0_PHYS_ADDR 0x11600000 |
752 | #define SSI1_PHYS_ADDR 0x11680000 | 751 | #define SSI1_PHYS_ADDR 0x11680000 |
753 | #define GPIO2_PHYS_ADDR 0x11700000 | ||
754 | #define SYS_PHYS_ADDR 0x11900000 | ||
755 | #define LCD_PHYS_ADDR 0x15000000 | 752 | #define LCD_PHYS_ADDR 0x15000000 |
756 | #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL | 753 | #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL |
757 | #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL | 754 | #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL |
@@ -765,8 +762,6 @@ enum soc_au1200_ints { | |||
765 | #define STATIC_MEM_PHYS_ADDR 0x14001000 | 762 | #define STATIC_MEM_PHYS_ADDR 0x14001000 |
766 | #define USBH_PHYS_ADDR 0x14020000 | 763 | #define USBH_PHYS_ADDR 0x14020000 |
767 | #define PCI_PHYS_ADDR 0x14005000 | 764 | #define PCI_PHYS_ADDR 0x14005000 |
768 | #define GPIO2_PHYS_ADDR 0x11700000 | ||
769 | #define SYS_PHYS_ADDR 0x11900000 | ||
770 | #define PE_PHYS_ADDR 0x14008000 | 765 | #define PE_PHYS_ADDR 0x14008000 |
771 | #define PSC0_PHYS_ADDR 0x11A00000 | 766 | #define PSC0_PHYS_ADDR 0x11A00000 |
772 | #define PSC1_PHYS_ADDR 0x11B00000 | 767 | #define PSC1_PHYS_ADDR 0x11B00000 |
@@ -790,8 +785,6 @@ enum soc_au1200_ints { | |||
790 | #define CIM_PHYS_ADDR 0x14004000 | 785 | #define CIM_PHYS_ADDR 0x14004000 |
791 | #define USBM_PHYS_ADDR 0x14020000 | 786 | #define USBM_PHYS_ADDR 0x14020000 |
792 | #define USBH_PHYS_ADDR 0x14020100 | 787 | #define USBH_PHYS_ADDR 0x14020100 |
793 | #define GPIO2_PHYS_ADDR 0x11700000 | ||
794 | #define SYS_PHYS_ADDR 0x11900000 | ||
795 | #define PSC0_PHYS_ADDR 0x11A00000 | 788 | #define PSC0_PHYS_ADDR 0x11A00000 |
796 | #define PSC1_PHYS_ADDR 0x11B00000 | 789 | #define PSC1_PHYS_ADDR 0x11B00000 |
797 | #define LCD_PHYS_ADDR 0x15000000 | 790 | #define LCD_PHYS_ADDR 0x15000000 |
@@ -1359,22 +1352,6 @@ enum soc_au1200_ints { | |||
1359 | #define SYS_PINFUNC_S1B (1 << 2) | 1352 | #define SYS_PINFUNC_S1B (1 << 2) |
1360 | #endif | 1353 | #endif |
1361 | 1354 | ||
1362 | #define SYS_TRIOUTRD 0xB1900100 | ||
1363 | #define SYS_TRIOUTCLR 0xB1900100 | ||
1364 | #define SYS_OUTPUTRD 0xB1900108 | ||
1365 | #define SYS_OUTPUTSET 0xB1900108 | ||
1366 | #define SYS_OUTPUTCLR 0xB190010C | ||
1367 | #define SYS_PINSTATERD 0xB1900110 | ||
1368 | #define SYS_PININPUTEN 0xB1900110 | ||
1369 | |||
1370 | /* GPIO2, Au1500, Au1550 only */ | ||
1371 | #define GPIO2_BASE 0xB1700000 | ||
1372 | #define GPIO2_DIR (GPIO2_BASE + 0) | ||
1373 | #define GPIO2_OUTPUT (GPIO2_BASE + 8) | ||
1374 | #define GPIO2_PINSTATE (GPIO2_BASE + 0xC) | ||
1375 | #define GPIO2_INTENABLE (GPIO2_BASE + 0x10) | ||
1376 | #define GPIO2_ENABLE (GPIO2_BASE + 0x14) | ||
1377 | |||
1378 | /* Power Management */ | 1355 | /* Power Management */ |
1379 | #define SYS_SCRATCH0 0xB1900018 | 1356 | #define SYS_SCRATCH0 0xB1900018 |
1380 | #define SYS_SCRATCH1 0xB190001C | 1357 | #define SYS_SCRATCH1 0xB190001C |
diff --git a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h index 8f8c1c55593a..1f41a522906d 100644 --- a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h +++ b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h | |||
@@ -24,6 +24,22 @@ | |||
24 | 24 | ||
25 | #define MAKE_IRQ(intc, off) (AU1000_INTC##intc##_INT_BASE + (off)) | 25 | #define MAKE_IRQ(intc, off) (AU1000_INTC##intc##_INT_BASE + (off)) |
26 | 26 | ||
27 | /* GPIO1 registers within SYS_ area */ | ||
28 | #define SYS_TRIOUTRD 0x100 | ||
29 | #define SYS_TRIOUTCLR 0x100 | ||
30 | #define SYS_OUTPUTRD 0x108 | ||
31 | #define SYS_OUTPUTSET 0x108 | ||
32 | #define SYS_OUTPUTCLR 0x10C | ||
33 | #define SYS_PINSTATERD 0x110 | ||
34 | #define SYS_PININPUTEN 0x110 | ||
35 | |||
36 | /* register offsets within GPIO2 block */ | ||
37 | #define GPIO2_DIR 0x00 | ||
38 | #define GPIO2_OUTPUT 0x08 | ||
39 | #define GPIO2_PINSTATE 0x0C | ||
40 | #define GPIO2_INTENABLE 0x10 | ||
41 | #define GPIO2_ENABLE 0x14 | ||
42 | |||
27 | struct gpio; | 43 | struct gpio; |
28 | 44 | ||
29 | static inline int au1000_gpio1_to_irq(int gpio) | 45 | static inline int au1000_gpio1_to_irq(int gpio) |
@@ -201,23 +217,26 @@ static inline int au1200_irq_to_gpio(int irq) | |||
201 | */ | 217 | */ |
202 | static inline void alchemy_gpio1_set_value(int gpio, int v) | 218 | static inline void alchemy_gpio1_set_value(int gpio, int v) |
203 | { | 219 | { |
220 | void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR); | ||
204 | unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE); | 221 | unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE); |
205 | unsigned long r = v ? SYS_OUTPUTSET : SYS_OUTPUTCLR; | 222 | unsigned long r = v ? SYS_OUTPUTSET : SYS_OUTPUTCLR; |
206 | au_writel(mask, r); | 223 | __raw_writel(mask, base + r); |
207 | au_sync(); | 224 | wmb(); |
208 | } | 225 | } |
209 | 226 | ||
210 | static inline int alchemy_gpio1_get_value(int gpio) | 227 | static inline int alchemy_gpio1_get_value(int gpio) |
211 | { | 228 | { |
229 | void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR); | ||
212 | unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE); | 230 | unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE); |
213 | return au_readl(SYS_PINSTATERD) & mask; | 231 | return __raw_readl(base + SYS_PINSTATERD) & mask; |
214 | } | 232 | } |
215 | 233 | ||
216 | static inline int alchemy_gpio1_direction_input(int gpio) | 234 | static inline int alchemy_gpio1_direction_input(int gpio) |
217 | { | 235 | { |
236 | void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR); | ||
218 | unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE); | 237 | unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE); |
219 | au_writel(mask, SYS_TRIOUTCLR); | 238 | __raw_writel(mask, base + SYS_TRIOUTCLR); |
220 | au_sync(); | 239 | wmb(); |
221 | return 0; | 240 | return 0; |
222 | } | 241 | } |
223 | 242 | ||
@@ -258,27 +277,31 @@ static inline int alchemy_gpio1_to_irq(int gpio) | |||
258 | */ | 277 | */ |
259 | static inline void __alchemy_gpio2_mod_dir(int gpio, int to_out) | 278 | static inline void __alchemy_gpio2_mod_dir(int gpio, int to_out) |
260 | { | 279 | { |
280 | void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); | ||
261 | unsigned long mask = 1 << (gpio - ALCHEMY_GPIO2_BASE); | 281 | unsigned long mask = 1 << (gpio - ALCHEMY_GPIO2_BASE); |
262 | unsigned long d = au_readl(GPIO2_DIR); | 282 | unsigned long d = __raw_readl(base + GPIO2_DIR); |
283 | |||
263 | if (to_out) | 284 | if (to_out) |
264 | d |= mask; | 285 | d |= mask; |
265 | else | 286 | else |
266 | d &= ~mask; | 287 | d &= ~mask; |
267 | au_writel(d, GPIO2_DIR); | 288 | __raw_writel(d, base + GPIO2_DIR); |
268 | au_sync(); | 289 | wmb(); |
269 | } | 290 | } |
270 | 291 | ||
271 | static inline void alchemy_gpio2_set_value(int gpio, int v) | 292 | static inline void alchemy_gpio2_set_value(int gpio, int v) |
272 | { | 293 | { |
294 | void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); | ||
273 | unsigned long mask; | 295 | unsigned long mask; |
274 | mask = ((v) ? 0x00010001 : 0x00010000) << (gpio - ALCHEMY_GPIO2_BASE); | 296 | mask = ((v) ? 0x00010001 : 0x00010000) << (gpio - ALCHEMY_GPIO2_BASE); |
275 | au_writel(mask, GPIO2_OUTPUT); | 297 | __raw_writel(mask, base + GPIO2_OUTPUT); |
276 | au_sync(); | 298 | wmb(); |
277 | } | 299 | } |
278 | 300 | ||
279 | static inline int alchemy_gpio2_get_value(int gpio) | 301 | static inline int alchemy_gpio2_get_value(int gpio) |
280 | { | 302 | { |
281 | return au_readl(GPIO2_PINSTATE) & (1 << (gpio - ALCHEMY_GPIO2_BASE)); | 303 | void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); |
304 | return __raw_readl(base + GPIO2_PINSTATE) & (1 << (gpio - ALCHEMY_GPIO2_BASE)); | ||
282 | } | 305 | } |
283 | 306 | ||
284 | static inline int alchemy_gpio2_direction_input(int gpio) | 307 | static inline int alchemy_gpio2_direction_input(int gpio) |
@@ -330,21 +353,23 @@ static inline int alchemy_gpio2_to_irq(int gpio) | |||
330 | */ | 353 | */ |
331 | static inline void alchemy_gpio1_input_enable(void) | 354 | static inline void alchemy_gpio1_input_enable(void) |
332 | { | 355 | { |
333 | au_writel(0, SYS_PININPUTEN); /* the write op is key */ | 356 | void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR); |
334 | au_sync(); | 357 | __raw_writel(0, base + SYS_PININPUTEN); /* the write op is key */ |
358 | wmb(); | ||
335 | } | 359 | } |
336 | 360 | ||
337 | /* GPIO2 shared interrupts and control */ | 361 | /* GPIO2 shared interrupts and control */ |
338 | 362 | ||
339 | static inline void __alchemy_gpio2_mod_int(int gpio2, int en) | 363 | static inline void __alchemy_gpio2_mod_int(int gpio2, int en) |
340 | { | 364 | { |
341 | unsigned long r = au_readl(GPIO2_INTENABLE); | 365 | void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); |
366 | unsigned long r = __raw_readl(base + GPIO2_INTENABLE); | ||
342 | if (en) | 367 | if (en) |
343 | r |= 1 << gpio2; | 368 | r |= 1 << gpio2; |
344 | else | 369 | else |
345 | r &= ~(1 << gpio2); | 370 | r &= ~(1 << gpio2); |
346 | au_writel(r, GPIO2_INTENABLE); | 371 | __raw_writel(r, base + GPIO2_INTENABLE); |
347 | au_sync(); | 372 | wmb(); |
348 | } | 373 | } |
349 | 374 | ||
350 | /** | 375 | /** |
@@ -419,10 +444,11 @@ static inline void alchemy_gpio2_disable_int(int gpio2) | |||
419 | */ | 444 | */ |
420 | static inline void alchemy_gpio2_enable(void) | 445 | static inline void alchemy_gpio2_enable(void) |
421 | { | 446 | { |
422 | au_writel(3, GPIO2_ENABLE); /* reset, clock enabled */ | 447 | void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); |
423 | au_sync(); | 448 | __raw_writel(3, base + GPIO2_ENABLE); /* reset, clock enabled */ |
424 | au_writel(1, GPIO2_ENABLE); /* clock enabled */ | 449 | wmb(); |
425 | au_sync(); | 450 | __raw_writel(1, base + GPIO2_ENABLE); /* clock enabled */ |
451 | wmb(); | ||
426 | } | 452 | } |
427 | 453 | ||
428 | /** | 454 | /** |
@@ -432,8 +458,9 @@ static inline void alchemy_gpio2_enable(void) | |||
432 | */ | 458 | */ |
433 | static inline void alchemy_gpio2_disable(void) | 459 | static inline void alchemy_gpio2_disable(void) |
434 | { | 460 | { |
435 | au_writel(2, GPIO2_ENABLE); /* reset, clock disabled */ | 461 | void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); |
436 | au_sync(); | 462 | __raw_writel(2, base + GPIO2_ENABLE); /* reset, clock disabled */ |
463 | wmb(); | ||
437 | } | 464 | } |
438 | 465 | ||
439 | /**********************************************************************/ | 466 | /**********************************************************************/ |
diff --git a/drivers/mtd/nand/au1550nd.c b/drivers/mtd/nand/au1550nd.c index 3ffe05db4923..5d513b54a7d7 100644 --- a/drivers/mtd/nand/au1550nd.c +++ b/drivers/mtd/nand/au1550nd.c | |||
@@ -10,6 +10,7 @@ | |||
10 | */ | 10 | */ |
11 | 11 | ||
12 | #include <linux/slab.h> | 12 | #include <linux/slab.h> |
13 | #include <linux/gpio.h> | ||
13 | #include <linux/init.h> | 14 | #include <linux/init.h> |
14 | #include <linux/module.h> | 15 | #include <linux/module.h> |
15 | #include <linux/interrupt.h> | 16 | #include <linux/interrupt.h> |
@@ -470,7 +471,7 @@ static int __init au1xxx_nand_init(void) | |||
470 | 471 | ||
471 | #ifdef CONFIG_MIPS_PB1550 | 472 | #ifdef CONFIG_MIPS_PB1550 |
472 | /* set gpio206 high */ | 473 | /* set gpio206 high */ |
473 | au_writel(au_readl(GPIO2_DIR) & ~(1 << 6), GPIO2_DIR); | 474 | gpio_direction_input(206); |
474 | 475 | ||
475 | boot_swapboot = (au_readl(MEM_STSTAT) & (0x7 << 1)) | ((bcsr_read(BCSR_STATUS) >> 6) & 0x1); | 476 | boot_swapboot = (au_readl(MEM_STSTAT) & (0x7 << 1)) | ((bcsr_read(BCSR_STATUS) >> 6) & 0x1); |
476 | 477 | ||
diff --git a/drivers/watchdog/mtx-1_wdt.c b/drivers/watchdog/mtx-1_wdt.c index 5ec5ac1f7878..1479dc4d6129 100644 --- a/drivers/watchdog/mtx-1_wdt.c +++ b/drivers/watchdog/mtx-1_wdt.c | |||
@@ -66,6 +66,7 @@ static struct { | |||
66 | int default_ticks; | 66 | int default_ticks; |
67 | unsigned long inuse; | 67 | unsigned long inuse; |
68 | unsigned gpio; | 68 | unsigned gpio; |
69 | int gstate; | ||
69 | } mtx1_wdt_device; | 70 | } mtx1_wdt_device; |
70 | 71 | ||
71 | static void mtx1_wdt_trigger(unsigned long unused) | 72 | static void mtx1_wdt_trigger(unsigned long unused) |
@@ -75,13 +76,13 @@ static void mtx1_wdt_trigger(unsigned long unused) | |||
75 | spin_lock(&mtx1_wdt_device.lock); | 76 | spin_lock(&mtx1_wdt_device.lock); |
76 | if (mtx1_wdt_device.running) | 77 | if (mtx1_wdt_device.running) |
77 | ticks--; | 78 | ticks--; |
78 | /* | 79 | |
79 | * toggle GPIO2_15 | 80 | /* toggle wdt gpio */ |
80 | */ | 81 | mtx1_wdt_device.gstate = ~mtx1_wdt_device.gstate; |
81 | tmp = au_readl(GPIO2_DIR); | 82 | if (mtx1_wdt_device.gstate) |
82 | tmp = (tmp & ~(1 << mtx1_wdt_device.gpio)) | | 83 | gpio_direction_output(mtx1_wdt_device.gpio, 1); |
83 | ((~tmp) & (1 << mtx1_wdt_device.gpio)); | 84 | else |
84 | au_writel(tmp, GPIO2_DIR); | 85 | gpio_direction_input(mtx1_wdt_device.gpio); |
85 | 86 | ||
86 | if (mtx1_wdt_device.queue && ticks) | 87 | if (mtx1_wdt_device.queue && ticks) |
87 | mod_timer(&mtx1_wdt_device.timer, jiffies + MTX1_WDT_INTERVAL); | 88 | mod_timer(&mtx1_wdt_device.timer, jiffies + MTX1_WDT_INTERVAL); |
@@ -103,7 +104,8 @@ static void mtx1_wdt_start(void) | |||
103 | spin_lock_irqsave(&mtx1_wdt_device.lock, flags); | 104 | spin_lock_irqsave(&mtx1_wdt_device.lock, flags); |
104 | if (!mtx1_wdt_device.queue) { | 105 | if (!mtx1_wdt_device.queue) { |
105 | mtx1_wdt_device.queue = 1; | 106 | mtx1_wdt_device.queue = 1; |
106 | gpio_set_value(mtx1_wdt_device.gpio, 1); | 107 | mtx1_wdt_device.gstate = 1; |
108 | gpio_direction_output(mtx1_wdt_device.gpio, 1); | ||
107 | mod_timer(&mtx1_wdt_device.timer, jiffies + MTX1_WDT_INTERVAL); | 109 | mod_timer(&mtx1_wdt_device.timer, jiffies + MTX1_WDT_INTERVAL); |
108 | } | 110 | } |
109 | mtx1_wdt_device.running++; | 111 | mtx1_wdt_device.running++; |
@@ -117,7 +119,8 @@ static int mtx1_wdt_stop(void) | |||
117 | spin_lock_irqsave(&mtx1_wdt_device.lock, flags); | 119 | spin_lock_irqsave(&mtx1_wdt_device.lock, flags); |
118 | if (mtx1_wdt_device.queue) { | 120 | if (mtx1_wdt_device.queue) { |
119 | mtx1_wdt_device.queue = 0; | 121 | mtx1_wdt_device.queue = 0; |
120 | gpio_set_value(mtx1_wdt_device.gpio, 0); | 122 | mtx1_wdt_device.gstate = 0; |
123 | gpio_direction_output(mtx1_wdt_device.gpio, 0); | ||
121 | } | 124 | } |
122 | ticks = mtx1_wdt_device.default_ticks; | 125 | ticks = mtx1_wdt_device.default_ticks; |
123 | spin_unlock_irqrestore(&mtx1_wdt_device.lock, flags); | 126 | spin_unlock_irqrestore(&mtx1_wdt_device.lock, flags); |