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-rw-r--r--arch/arm/boot/dts/armada-370-db.dts17
-rw-r--r--arch/arm/boot/dts/armada-370-mirabox.dts66
-rw-r--r--arch/arm/boot/dts/armada-370-rd.dts11
-rw-r--r--arch/arm/boot/dts/armada-370-xp.dtsi45
-rw-r--r--arch/arm/boot/dts/armada-370.dtsi64
-rw-r--r--arch/arm/boot/dts/armada-xp-db.dts33
-rw-r--r--arch/arm/boot/dts/armada-xp-gp.dts50
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78230.dtsi104
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78260.dtsi122
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78460.dtsi188
-rw-r--r--arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts38
-rw-r--r--arch/arm/boot/dts/armada-xp.dtsi6
-rw-r--r--arch/arm/boot/dts/dove.dtsi5
-rw-r--r--arch/arm/boot/dts/kirkwood-6282.dtsi6
-rw-r--r--arch/arm/boot/dts/kirkwood-goflexnet.dts1
-rw-r--r--arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts4
-rw-r--r--arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts14
-rw-r--r--arch/arm/boot/dts/orion5x.dtsi42
-rw-r--r--arch/arm/boot/dts/skeleton64.dtsi13
-rw-r--r--arch/arm/configs/dove_defconfig2
-rw-r--r--arch/arm/configs/kirkwood_defconfig2
-rw-r--r--arch/arm/configs/mvebu_defconfig9
-rw-r--r--arch/arm/mach-kirkwood/board-guruplug.c6
-rw-r--r--arch/arm/mach-kirkwood/board-iomega_ix2_200.c7
-rw-r--r--arch/arm/mach-kirkwood/guruplug-setup.c2
-rw-r--r--arch/arm/mach-kirkwood/openrd-setup.c1
-rw-r--r--arch/arm/mach-kirkwood/rd88f6281-setup.c1
-rw-r--r--arch/arm/mach-mvebu/irq-armada-370-xp.c24
28 files changed, 852 insertions, 31 deletions
diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
index e34b280ce6ec..6403acdbb75f 100644
--- a/arch/arm/boot/dts/armada-370-db.dts
+++ b/arch/arm/boot/dts/armada-370-db.dts
@@ -94,5 +94,22 @@
94 spi-max-frequency = <50000000>; 94 spi-max-frequency = <50000000>;
95 }; 95 };
96 }; 96 };
97
98 pcie-controller {
99 status = "okay";
100 /*
101 * The two PCIe units are accessible through
102 * both standard PCIe slots and mini-PCIe
103 * slots on the board.
104 */
105 pcie@1,0 {
106 /* Port 0, Lane 0 */
107 status = "okay";
108 };
109 pcie@2,0 {
110 /* Port 1, Lane 0 */
111 status = "okay";
112 };
113 };
97 }; 114 };
98}; 115};
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts
index dd0c57dd9f30..58ee79372206 100644
--- a/arch/arm/boot/dts/armada-370-mirabox.dts
+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
@@ -33,6 +33,43 @@
33 clock-frequency = <600000000>; 33 clock-frequency = <600000000>;
34 status = "okay"; 34 status = "okay";
35 }; 35 };
36
37 pinctrl {
38 pwr_led_pin: pwr-led-pin {
39 marvell,pins = "mpp63";
40 marvell,function = "gpo";
41 };
42
43 stat_led_pins: stat-led-pins {
44 marvell,pins = "mpp64", "mpp65";
45 marvell,function = "gpio";
46 };
47 };
48
49 gpio_leds {
50 compatible = "gpio-leds";
51 pinctrl-names = "default";
52 pinctrl-0 = <&pwr_led_pin &stat_led_pins>;
53
54 green_pwr_led {
55 label = "mirabox:green:pwr";
56 gpios = <&gpio1 31 1>;
57 linux,default-trigger = "heartbeat";
58 };
59
60 blue_stat_led {
61 label = "mirabox:blue:stat";
62 gpios = <&gpio2 0 1>;
63 linux,default-trigger = "cpu0";
64 };
65
66 green_stat_led {
67 label = "mirabox:green:stat";
68 gpios = <&gpio2 1 1>;
69 default-state = "off";
70 };
71 };
72
36 mdio { 73 mdio {
37 phy0: ethernet-phy@0 { 74 phy0: ethernet-phy@0 {
38 reg = <0>; 75 reg = <0>;
@@ -54,7 +91,7 @@
54 }; 91 };
55 92
56 mvsdio@d00d4000 { 93 mvsdio@d00d4000 {
57 pinctrl-0 = <&sdio_pins2>; 94 pinctrl-0 = <&sdio_pins3>;
58 pinctrl-names = "default"; 95 pinctrl-names = "default";
59 status = "okay"; 96 status = "okay";
60 /* 97 /*
@@ -70,5 +107,32 @@
70 usb@d0051000 { 107 usb@d0051000 {
71 status = "okay"; 108 status = "okay";
72 }; 109 };
110
111 i2c@d0011000 {
112 status = "okay";
113 clock-frequency = <100000>;
114 pca9505: pca9505@25 {
115 compatible = "nxp,pca9505";
116 gpio-controller;
117 #gpio-cells = <2>;
118 reg = <0x25>;
119 };
120 };
121
122 pcie-controller {
123 status = "okay";
124
125 /* Internal mini-PCIe connector */
126 pcie@1,0 {
127 /* Port 0, Lane 0 */
128 status = "okay";
129 };
130
131 /* Connected on the PCB to a USB 3.0 XHCI controller */
132 pcie@2,0 {
133 /* Port 1, Lane 0 */
134 status = "okay";
135 };
136 };
73 }; 137 };
74}; 138};
diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts
index 070bba4f2585..516dec31b469 100644
--- a/arch/arm/boot/dts/armada-370-rd.dts
+++ b/arch/arm/boot/dts/armada-370-rd.dts
@@ -73,4 +73,15 @@
73 status = "okay"; 73 status = "okay";
74 }; 74 };
75 }; 75 };
76
77 gpio-keys {
78 compatible = "gpio-keys";
79 #address-cells = <1>;
80 #size-cells = <0>;
81 button@1 {
82 label = "Software Button";
83 linux,code = <116>;
84 gpios = <&gpio0 6 1>;
85 };
86 };
76}; 87};
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 7704829a12c0..9693f796bcfe 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -176,6 +176,51 @@
176 clocks = <&coreclk 0>; 176 clocks = <&coreclk 0>;
177 status = "disabled"; 177 status = "disabled";
178 }; 178 };
179
180 devbus-bootcs@d0010400 {
181 compatible = "marvell,mvebu-devbus";
182 reg = <0xd0010400 0x8>;
183 #address-cells = <1>;
184 #size-cells = <1>;
185 clocks = <&coreclk 0>;
186 status = "disabled";
187 };
188
189 devbus-cs0@d0010408 {
190 compatible = "marvell,mvebu-devbus";
191 reg = <0xd0010408 0x8>;
192 #address-cells = <1>;
193 #size-cells = <1>;
194 clocks = <&coreclk 0>;
195 status = "disabled";
196 };
197
198 devbus-cs1@d0010410 {
199 compatible = "marvell,mvebu-devbus";
200 reg = <0xd0010410 0x8>;
201 #address-cells = <1>;
202 #size-cells = <1>;
203 clocks = <&coreclk 0>;
204 status = "disabled";
205 };
206
207 devbus-cs2@d0010418 {
208 compatible = "marvell,mvebu-devbus";
209 reg = <0xd0010418 0x8>;
210 #address-cells = <1>;
211 #size-cells = <1>;
212 clocks = <&coreclk 0>;
213 status = "disabled";
214 };
215
216 devbus-cs3@d0010420 {
217 compatible = "marvell,mvebu-devbus";
218 reg = <0xd0010420 0x8>;
219 #address-cells = <1>;
220 #size-cells = <1>;
221 clocks = <&coreclk 0>;
222 status = "disabled";
223 };
179 }; 224 };
180}; 225};
181 226
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index 8188d138020e..18f6eb47cc50 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -59,6 +59,12 @@
59 "mpp50", "mpp51", "mpp52"; 59 "mpp50", "mpp51", "mpp52";
60 marvell,function = "sd0"; 60 marvell,function = "sd0";
61 }; 61 };
62
63 sdio_pins3: sdio-pins3 {
64 marvell,pins = "mpp48", "mpp49", "mpp50",
65 "mpp51", "mpp52", "mpp53";
66 marvell,function = "sd0";
67 };
62 }; 68 };
63 69
64 gpio0: gpio@d0018100 { 70 gpio0: gpio@d0018100 {
@@ -153,5 +159,63 @@
153 clocks = <&coreclk 0>; 159 clocks = <&coreclk 0>;
154 }; 160 };
155 161
162 thermal@d0018300 {
163 compatible = "marvell,armada370-thermal";
164 reg = <0xd0018300 0x4
165 0xd0018304 0x4>;
166 status = "okay";
167 };
168
169 pcie-controller {
170 compatible = "marvell,armada-370-pcie";
171 status = "disabled";
172 device_type = "pci";
173
174 #address-cells = <3>;
175 #size-cells = <2>;
176
177 bus-range = <0x00 0xff>;
178
179 reg = <0xd0040000 0x2000>, <0xd0080000 0x2000>;
180
181 reg-names = "pcie0.0", "pcie1.0";
182
183 ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000 /* Port 0.0 registers */
184 0x82000000 0 0xd0080000 0xd0080000 0 0x00002000 /* Port 1.0 registers */
185 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
186 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
187
188 pcie@1,0 {
189 device_type = "pci";
190 assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>;
191 reg = <0x0800 0 0 0 0>;
192 #address-cells = <3>;
193 #size-cells = <2>;
194 #interrupt-cells = <1>;
195 ranges;
196 interrupt-map-mask = <0 0 0 0>;
197 interrupt-map = <0 0 0 0 &mpic 58>;
198 marvell,pcie-port = <0>;
199 marvell,pcie-lane = <0>;
200 clocks = <&gateclk 5>;
201 status = "disabled";
202 };
203
204 pcie@2,0 {
205 device_type = "pci";
206 assigned-addresses = <0x82002800 0 0xd0080000 0 0x2000>;
207 reg = <0x1000 0 0 0 0>;
208 #address-cells = <3>;
209 #size-cells = <2>;
210 #interrupt-cells = <1>;
211 ranges;
212 interrupt-map-mask = <0 0 0 0>;
213 interrupt-map = <0 0 0 0 &mpic 62>;
214 marvell,pcie-port = <1>;
215 marvell,pcie-lane = <0>;
216 clocks = <&gateclk 9>;
217 status = "disabled";
218 };
219 };
156 }; 220 };
157}; 221};
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index e83505e4c236..54cc5bb705fb 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -121,5 +121,38 @@
121 spi-max-frequency = <20000000>; 121 spi-max-frequency = <20000000>;
122 }; 122 };
123 }; 123 };
124
125 pcie-controller {
126 status = "okay";
127
128 /*
129 * All 6 slots are physically present as
130 * standard PCIe slots on the board.
131 */
132 pcie@1,0 {
133 /* Port 0, Lane 0 */
134 status = "okay";
135 };
136 pcie@2,0 {
137 /* Port 0, Lane 1 */
138 status = "okay";
139 };
140 pcie@3,0 {
141 /* Port 0, Lane 2 */
142 status = "okay";
143 };
144 pcie@4,0 {
145 /* Port 0, Lane 3 */
146 status = "okay";
147 };
148 pcie@9,0 {
149 /* Port 2, Lane 0 */
150 status = "okay";
151 };
152 pcie@10,0 {
153 /* Port 3, Lane 0 */
154 status = "okay";
155 };
156 };
124 }; 157 };
125}; 158};
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
index 1c8afe2ffebc..04f28a712b98 100644
--- a/arch/arm/boot/dts/armada-xp-gp.dts
+++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -109,5 +109,55 @@
109 spi-max-frequency = <108000000>; 109 spi-max-frequency = <108000000>;
110 }; 110 };
111 }; 111 };
112
113 devbus-bootcs@d0010400 {
114 status = "okay";
115 ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf000000, size 0x1000000 */
116
117 /* Device Bus parameters are required */
118
119 /* Read parameters */
120 devbus,bus-width = <8>;
121 devbus,turn-off-ps = <60000>;
122 devbus,badr-skew-ps = <0>;
123 devbus,acc-first-ps = <124000>;
124 devbus,acc-next-ps = <248000>;
125 devbus,rd-setup-ps = <0>;
126 devbus,rd-hold-ps = <0>;
127
128 /* Write parameters */
129 devbus,sync-enable = <0>;
130 devbus,wr-high-ps = <60000>;
131 devbus,wr-low-ps = <60000>;
132 devbus,ale-wr-ps = <60000>;
133
134 /* NOR 16 MiB */
135 nor@0 {
136 compatible = "cfi-flash";
137 reg = <0 0x1000000>;
138 bank-width = <2>;
139 };
140 };
141
142 pcie-controller {
143 status = "okay";
144
145 /*
146 * The 3 slots are physically present as
147 * standard PCIe slots on the board.
148 */
149 pcie@1,0 {
150 /* Port 0, Lane 0 */
151 status = "okay";
152 };
153 pcie@9,0 {
154 /* Port 2, Lane 0 */
155 status = "okay";
156 };
157 pcie@10,0 {
158 /* Port 3, Lane 0 */
159 status = "okay";
160 };
161 };
112 }; 162 };
113}; 163};
diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
index f56c40599f5b..c2c78459a4d4 100644
--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
@@ -76,5 +76,109 @@
76 #interrupts-cells = <2>; 76 #interrupts-cells = <2>;
77 interrupts = <87>, <88>, <89>; 77 interrupts = <87>, <88>, <89>;
78 }; 78 };
79
80 /*
81 * MV78230 has 2 PCIe units Gen2.0: One unit can be
82 * configured as x4 or quad x1 lanes. One unit is
83 * x4/x1.
84 */
85 pcie-controller {
86 compatible = "marvell,armada-xp-pcie";
87 status = "disabled";
88 device_type = "pci";
89
90 #address-cells = <3>;
91 #size-cells = <2>;
92
93 bus-range = <0x00 0xff>;
94
95 ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000 /* Port 0.0 registers */
96 0x82000000 0 0xd0042000 0xd0042000 0 0x00002000 /* Port 2.0 registers */
97 0x82000000 0 0xd0044000 0xd0044000 0 0x00002000 /* Port 0.1 registers */
98 0x82000000 0 0xd0048000 0xd0048000 0 0x00002000 /* Port 0.2 registers */
99 0x82000000 0 0xd004c000 0xd004c000 0 0x00002000 /* Port 0.3 registers */
100 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
101 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
102
103 pcie@1,0 {
104 device_type = "pci";
105 assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>;
106 reg = <0x0800 0 0 0 0>;
107 #address-cells = <3>;
108 #size-cells = <2>;
109 #interrupt-cells = <1>;
110 ranges;
111 interrupt-map-mask = <0 0 0 0>;
112 interrupt-map = <0 0 0 0 &mpic 58>;
113 marvell,pcie-port = <0>;
114 marvell,pcie-lane = <0>;
115 clocks = <&gateclk 5>;
116 status = "disabled";
117 };
118
119 pcie@2,0 {
120 device_type = "pci";
121 assigned-addresses = <0x82000800 0 0xd0044000 0 0x2000>;
122 reg = <0x1000 0 0 0 0>;
123 #address-cells = <3>;
124 #size-cells = <2>;
125 #interrupt-cells = <1>;
126 ranges;
127 interrupt-map-mask = <0 0 0 0>;
128 interrupt-map = <0 0 0 0 &mpic 59>;
129 marvell,pcie-port = <0>;
130 marvell,pcie-lane = <1>;
131 clocks = <&gateclk 6>;
132 status = "disabled";
133 };
134
135 pcie@3,0 {
136 device_type = "pci";
137 assigned-addresses = <0x82000800 0 0xd0048000 0 0x2000>;
138 reg = <0x1800 0 0 0 0>;
139 #address-cells = <3>;
140 #size-cells = <2>;
141 #interrupt-cells = <1>;
142 ranges;
143 interrupt-map-mask = <0 0 0 0>;
144 interrupt-map = <0 0 0 0 &mpic 60>;
145 marvell,pcie-port = <0>;
146 marvell,pcie-lane = <2>;
147 clocks = <&gateclk 7>;
148 status = "disabled";
149 };
150
151 pcie@4,0 {
152 device_type = "pci";
153 assigned-addresses = <0x82000800 0 0xd004c000 0 0x2000>;
154 reg = <0x2000 0 0 0 0>;
155 #address-cells = <3>;
156 #size-cells = <2>;
157 #interrupt-cells = <1>;
158 ranges;
159 interrupt-map-mask = <0 0 0 0>;
160 interrupt-map = <0 0 0 0 &mpic 61>;
161 marvell,pcie-port = <0>;
162 marvell,pcie-lane = <3>;
163 clocks = <&gateclk 8>;
164 status = "disabled";
165 };
166
167 pcie@9,0 {
168 device_type = "pci";
169 assigned-addresses = <0x82000800 0 0xd0042000 0 0x2000>;
170 reg = <0x4800 0 0 0 0>;
171 #address-cells = <3>;
172 #size-cells = <2>;
173 #interrupt-cells = <1>;
174 ranges;
175 interrupt-map-mask = <0 0 0 0>;
176 interrupt-map = <0 0 0 0 &mpic 99>;
177 marvell,pcie-port = <2>;
178 marvell,pcie-lane = <0>;
179 clocks = <&gateclk 26>;
180 status = "disabled";
181 };
182 };
79 }; 183 };
80}; 184};
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
index f8f2b787d2b0..885bf229eef7 100644
--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -96,5 +96,127 @@
96 clocks = <&gateclk 1>; 96 clocks = <&gateclk 1>;
97 status = "disabled"; 97 status = "disabled";
98 }; 98 };
99
100 /*
101 * MV78260 has 3 PCIe units Gen2.0: Two units can be
102 * configured as x4 or quad x1 lanes. One unit is
103 * x4/x1.
104 */
105 pcie-controller {
106 compatible = "marvell,armada-xp-pcie";
107 status = "disabled";
108 device_type = "pci";
109
110 #address-cells = <3>;
111 #size-cells = <2>;
112
113 bus-range = <0x00 0xff>;
114
115 ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000 /* Port 0.0 registers */
116 0x82000000 0 0xd0042000 0xd0042000 0 0x00002000 /* Port 2.0 registers */
117 0x82000000 0 0xd0044000 0xd0044000 0 0x00002000 /* Port 0.1 registers */
118 0x82000000 0 0xd0048000 0xd0048000 0 0x00002000 /* Port 0.2 registers */
119 0x82000000 0 0xd004c000 0xd004c000 0 0x00002000 /* Port 0.3 registers */
120 0x82000000 0 0xd0080000 0xd0080000 0 0x00002000 /* Port 1.0 registers */
121 0x82000000 0 0xd0082000 0xd0082000 0 0x00002000 /* Port 3.0 registers */
122 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
123 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
124
125 pcie@1,0 {
126 device_type = "pci";
127 assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>;
128 reg = <0x0800 0 0 0 0>;
129 #address-cells = <3>;
130 #size-cells = <2>;
131 #interrupt-cells = <1>;
132 ranges;
133 interrupt-map-mask = <0 0 0 0>;
134 interrupt-map = <0 0 0 0 &mpic 58>;
135 marvell,pcie-port = <0>;
136 marvell,pcie-lane = <0>;
137 clocks = <&gateclk 5>;
138 status = "disabled";
139 };
140
141 pcie@2,0 {
142 device_type = "pci";
143 assigned-addresses = <0x82000800 0 0xd0044000 0 0x2000>;
144 reg = <0x1000 0 0 0 0>;
145 #address-cells = <3>;
146 #size-cells = <2>;
147 #interrupt-cells = <1>;
148 ranges;
149 interrupt-map-mask = <0 0 0 0>;
150 interrupt-map = <0 0 0 0 &mpic 59>;
151 marvell,pcie-port = <0>;
152 marvell,pcie-lane = <1>;
153 clocks = <&gateclk 6>;
154 status = "disabled";
155 };
156
157 pcie@3,0 {
158 device_type = "pci";
159 assigned-addresses = <0x82000800 0 0xd0048000 0 0x2000>;
160 reg = <0x1800 0 0 0 0>;
161 #address-cells = <3>;
162 #size-cells = <2>;
163 #interrupt-cells = <1>;
164 ranges;
165 interrupt-map-mask = <0 0 0 0>;
166 interrupt-map = <0 0 0 0 &mpic 60>;
167 marvell,pcie-port = <0>;
168 marvell,pcie-lane = <2>;
169 clocks = <&gateclk 7>;
170 status = "disabled";
171 };
172
173 pcie@4,0 {
174 device_type = "pci";
175 assigned-addresses = <0x82000800 0 0xd004c000 0 0x2000>;
176 reg = <0x2000 0 0 0 0>;
177 #address-cells = <3>;
178 #size-cells = <2>;
179 #interrupt-cells = <1>;
180 ranges;
181 interrupt-map-mask = <0 0 0 0>;
182 interrupt-map = <0 0 0 0 &mpic 61>;
183 marvell,pcie-port = <0>;
184 marvell,pcie-lane = <3>;
185 clocks = <&gateclk 8>;
186 status = "disabled";
187 };
188
189 pcie@9,0 {
190 device_type = "pci";
191 assigned-addresses = <0x82000800 0 0xd0042000 0 0x2000>;
192 reg = <0x4800 0 0 0 0>;
193 #address-cells = <3>;
194 #size-cells = <2>;
195 #interrupt-cells = <1>;
196 ranges;
197 interrupt-map-mask = <0 0 0 0>;
198 interrupt-map = <0 0 0 0 &mpic 99>;
199 marvell,pcie-port = <2>;
200 marvell,pcie-lane = <0>;
201 clocks = <&gateclk 26>;
202 status = "disabled";
203 };
204
205 pcie@10,0 {
206 device_type = "pci";
207 assigned-addresses = <0x82000800 0 0xd0082000 0 0x2000>;
208 reg = <0x5000 0 0 0 0>;
209 #address-cells = <3>;
210 #size-cells = <2>;
211 #interrupt-cells = <1>;
212 ranges;
213 interrupt-map-mask = <0 0 0 0>;
214 interrupt-map = <0 0 0 0 &mpic 103>;
215 marvell,pcie-port = <3>;
216 marvell,pcie-lane = <0>;
217 clocks = <&gateclk 27>;
218 status = "disabled";
219 };
220 };
99 }; 221 };
100}; 222};
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
index 936c25dc32b0..23a5ac4490a8 100644
--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -111,5 +111,193 @@
111 clocks = <&gateclk 1>; 111 clocks = <&gateclk 1>;
112 status = "disabled"; 112 status = "disabled";
113 }; 113 };
114
115 /*
116 * MV78460 has 4 PCIe units Gen2.0: Two units can be
117 * configured as x4 or quad x1 lanes. Two units are
118 * x4/x1.
119 */
120 pcie-controller {
121 compatible = "marvell,armada-xp-pcie";
122 status = "disabled";
123 device_type = "pci";
124
125 #address-cells = <3>;
126 #size-cells = <2>;
127
128 bus-range = <0x00 0xff>;
129
130 ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000 /* Port 0.0 registers */
131 0x82000000 0 0xd0042000 0xd0042000 0 0x00002000 /* Port 2.0 registers */
132 0x82000000 0 0xd0044000 0xd0044000 0 0x00002000 /* Port 0.1 registers */
133 0x82000000 0 0xd0048000 0xd0048000 0 0x00002000 /* Port 0.2 registers */
134 0x82000000 0 0xd004c000 0xd004c000 0 0x00002000 /* Port 0.3 registers */
135 0x82000000 0 0xd0080000 0xd0080000 0 0x00002000 /* Port 1.0 registers */
136 0x82000000 0 0xd0082000 0xd0082000 0 0x00002000 /* Port 3.0 registers */
137 0x82000000 0 0xd0084000 0xd0084000 0 0x00002000 /* Port 1.1 registers */
138 0x82000000 0 0xd0088000 0xd0088000 0 0x00002000 /* Port 1.2 registers */
139 0x82000000 0 0xd008c000 0xd008c000 0 0x00002000 /* Port 1.3 registers */
140 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
141 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
142
143 pcie@1,0 {
144 device_type = "pci";
145 assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>;
146 reg = <0x0800 0 0 0 0>;
147 #address-cells = <3>;
148 #size-cells = <2>;
149 #interrupt-cells = <1>;
150 ranges;
151 interrupt-map-mask = <0 0 0 0>;
152 interrupt-map = <0 0 0 0 &mpic 58>;
153 marvell,pcie-port = <0>;
154 marvell,pcie-lane = <0>;
155 clocks = <&gateclk 5>;
156 status = "disabled";
157 };
158
159 pcie@2,0 {
160 device_type = "pci";
161 assigned-addresses = <0x82001000 0 0xd0044000 0 0x2000>;
162 reg = <0x1000 0 0 0 0>;
163 #address-cells = <3>;
164 #size-cells = <2>;
165 #interrupt-cells = <1>;
166 ranges;
167 interrupt-map-mask = <0 0 0 0>;
168 interrupt-map = <0 0 0 0 &mpic 59>;
169 marvell,pcie-port = <0>;
170 marvell,pcie-lane = <1>;
171 clocks = <&gateclk 6>;
172 status = "disabled";
173 };
174
175 pcie@3,0 {
176 device_type = "pci";
177 assigned-addresses = <0x82001800 0 0xd0048000 0 0x2000>;
178 reg = <0x1800 0 0 0 0>;
179 #address-cells = <3>;
180 #size-cells = <2>;
181 #interrupt-cells = <1>;
182 ranges;
183 interrupt-map-mask = <0 0 0 0>;
184 interrupt-map = <0 0 0 0 &mpic 60>;
185 marvell,pcie-port = <0>;
186 marvell,pcie-lane = <2>;
187 clocks = <&gateclk 7>;
188 status = "disabled";
189 };
190
191 pcie@4,0 {
192 device_type = "pci";
193 assigned-addresses = <0x82002000 0 0xd004c000 0 0x2000>;
194 reg = <0x2000 0 0 0 0>;
195 #address-cells = <3>;
196 #size-cells = <2>;
197 #interrupt-cells = <1>;
198 ranges;
199 interrupt-map-mask = <0 0 0 0>;
200 interrupt-map = <0 0 0 0 &mpic 61>;
201 marvell,pcie-port = <0>;
202 marvell,pcie-lane = <3>;
203 clocks = <&gateclk 8>;
204 status = "disabled";
205 };
206
207 pcie@5,0 {
208 device_type = "pci";
209 assigned-addresses = <0x82002800 0 0xd0080000 0 0x2000>;
210 reg = <0x2800 0 0 0 0>;
211 #address-cells = <3>;
212 #size-cells = <2>;
213 #interrupt-cells = <1>;
214 ranges;
215 interrupt-map-mask = <0 0 0 0>;
216 interrupt-map = <0 0 0 0 &mpic 62>;
217 marvell,pcie-port = <1>;
218 marvell,pcie-lane = <0>;
219 clocks = <&gateclk 9>;
220 status = "disabled";
221 };
222
223 pcie@6,0 {
224 device_type = "pci";
225 assigned-addresses = <0x82003000 0 0xd0084000 0 0x2000>;
226 reg = <0x3000 0 0 0 0>;
227 #address-cells = <3>;
228 #size-cells = <2>;
229 #interrupt-cells = <1>;
230 ranges;
231 interrupt-map-mask = <0 0 0 0>;
232 interrupt-map = <0 0 0 0 &mpic 63>;
233 marvell,pcie-port = <1>;
234 marvell,pcie-lane = <1>;
235 clocks = <&gateclk 10>;
236 status = "disabled";
237 };
238
239 pcie@7,0 {
240 device_type = "pci";
241 assigned-addresses = <0x82003800 0 0xd0088000 0 0x2000>;
242 reg = <0x3800 0 0 0 0>;
243 #address-cells = <3>;
244 #size-cells = <2>;
245 #interrupt-cells = <1>;
246 ranges;
247 interrupt-map-mask = <0 0 0 0>;
248 interrupt-map = <0 0 0 0 &mpic 64>;
249 marvell,pcie-port = <1>;
250 marvell,pcie-lane = <2>;
251 clocks = <&gateclk 11>;
252 status = "disabled";
253 };
254
255 pcie@8,0 {
256 device_type = "pci";
257 assigned-addresses = <0x82004000 0 0xd008c000 0 0x2000>;
258 reg = <0x4000 0 0 0 0>;
259 #address-cells = <3>;
260 #size-cells = <2>;
261 #interrupt-cells = <1>;
262 ranges;
263 interrupt-map-mask = <0 0 0 0>;
264 interrupt-map = <0 0 0 0 &mpic 65>;
265 marvell,pcie-port = <1>;
266 marvell,pcie-lane = <3>;
267 clocks = <&gateclk 12>;
268 status = "disabled";
269 };
270 pcie@9,0 {
271 device_type = "pci";
272 assigned-addresses = <0x82004800 0 0xd0042000 0 0x2000>;
273 reg = <0x4800 0 0 0 0>;
274 #address-cells = <3>;
275 #size-cells = <2>;
276 #interrupt-cells = <1>;
277 ranges;
278 interrupt-map-mask = <0 0 0 0>;
279 interrupt-map = <0 0 0 0 &mpic 99>;
280 marvell,pcie-port = <2>;
281 marvell,pcie-lane = <0>;
282 clocks = <&gateclk 26>;
283 status = "disabled";
284 };
285
286 pcie@10,0 {
287 device_type = "pci";
288 assigned-addresses = <0x82005000 0 0xd0082000 0 0x2000>;
289 reg = <0x5000 0 0 0 0>;
290 #address-cells = <3>;
291 #size-cells = <2>;
292 #interrupt-cells = <1>;
293 ranges;
294 interrupt-map-mask = <0 0 0 0>;
295 interrupt-map = <0 0 0 0 &mpic 103>;
296 marvell,pcie-port = <3>;
297 marvell,pcie-lane = <0>;
298 clocks = <&gateclk 27>;
299 status = "disabled";
300 };
301 };
114 }; 302 };
115 }; 303 };
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
index 3818a82176a2..9d04f04d4e39 100644
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -139,5 +139,43 @@
139 usb@d0051000 { 139 usb@d0051000 {
140 status = "okay"; 140 status = "okay";
141 }; 141 };
142
143 devbus-bootcs@d0010400 {
144 status = "okay";
145 ranges = <0 0xf0000000 0x8000000>; /* @addr 0xf000000, size 0x8000000 */
146
147 /* Device Bus parameters are required */
148
149 /* Read parameters */
150 devbus,bus-width = <8>;
151 devbus,turn-off-ps = <60000>;
152 devbus,badr-skew-ps = <0>;
153 devbus,acc-first-ps = <124000>;
154 devbus,acc-next-ps = <248000>;
155 devbus,rd-setup-ps = <0>;
156 devbus,rd-hold-ps = <0>;
157
158 /* Write parameters */
159 devbus,sync-enable = <0>;
160 devbus,wr-high-ps = <60000>;
161 devbus,wr-low-ps = <60000>;
162 devbus,ale-wr-ps = <60000>;
163
164 /* NOR 128 MiB */
165 nor@0 {
166 compatible = "cfi-flash";
167 reg = <0 0x8000000>;
168 bank-width = <2>;
169 };
170 };
171
172 pcie-controller {
173 status = "okay";
174 /* Internal mini-PCIe connector */
175 pcie@1,0 {
176 /* Port 0, Lane 0 */
177 status = "okay";
178 };
179 };
142 }; 180 };
143}; 181};
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index ca00d8326c87..29dfeb6d4a26 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -151,5 +151,11 @@
151 status = "disabled"; 151 status = "disabled";
152 }; 152 };
153 153
154 thermal@d00182b0 {
155 compatible = "marvell,armadaxp-thermal";
156 reg = <0xd00182b0 0x4
157 0xd00184d0 0x4>;
158 status = "okay";
159 };
154 }; 160 };
155}; 161};
diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
index f7509cafc377..6cab46849cdb 100644
--- a/arch/arm/boot/dts/dove.dtsi
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -50,6 +50,11 @@
50 #clock-cells = <1>; 50 #clock-cells = <1>;
51 }; 51 };
52 52
53 thermal: thermal@d001c {
54 compatible = "marvell,dove-thermal";
55 reg = <0xd001c 0x0c>, <0xd005c 0x08>;
56 };
57
53 uart0: serial@12000 { 58 uart0: serial@12000 {
54 compatible = "ns16550a"; 59 compatible = "ns16550a";
55 reg = <0x12000 0x100>; 60 reg = <0x12000 0x100>;
diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi
index 192cf76fbf93..23991e45bc55 100644
--- a/arch/arm/boot/dts/kirkwood-6282.dtsi
+++ b/arch/arm/boot/dts/kirkwood-6282.dtsi
@@ -49,6 +49,12 @@
49 }; 49 };
50 }; 50 };
51 51
52 thermal@10078 {
53 compatible = "marvell,kirkwood-thermal";
54 reg = <0x10078 0x4>;
55 status = "okay";
56 };
57
52 i2c@11100 { 58 i2c@11100 {
53 compatible = "marvell,mv64xxx-i2c"; 59 compatible = "marvell,mv64xxx-i2c";
54 reg = <0x11100 0x20>; 60 reg = <0x11100 0x20>;
diff --git a/arch/arm/boot/dts/kirkwood-goflexnet.dts b/arch/arm/boot/dts/kirkwood-goflexnet.dts
index bd83b8fc7c83..c3573be7b92c 100644
--- a/arch/arm/boot/dts/kirkwood-goflexnet.dts
+++ b/arch/arm/boot/dts/kirkwood-goflexnet.dts
@@ -77,6 +77,7 @@
77 }; 77 };
78 78
79 nand@3000000 { 79 nand@3000000 {
80 chip-delay = <40>;
80 status = "okay"; 81 status = "okay";
81 82
82 partition@0 { 83 partition@0 {
diff --git a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
index 9555a86297c2..44fd97dfc1f3 100644
--- a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
+++ b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
@@ -69,6 +69,10 @@
69 status = "okay"; 69 status = "okay";
70 nr-ports = <1>; 70 nr-ports = <1>;
71 }; 71 };
72
73 mvsdio@90000 {
74 status = "okay";
75 };
72 }; 76 };
73 77
74 gpio-leds { 78 gpio-leds {
diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
index 93c3afbef9ee..3694e94f6e99 100644
--- a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
+++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
@@ -96,11 +96,11 @@
96 marvell,function = "gpio"; 96 marvell,function = "gpio";
97 }; 97 };
98 pmx_led_rebuild_brt_ctrl_1: pmx-led-rebuild-brt-ctrl-1 { 98 pmx_led_rebuild_brt_ctrl_1: pmx-led-rebuild-brt-ctrl-1 {
99 marvell,pins = "mpp44"; 99 marvell,pins = "mpp46";
100 marvell,function = "gpio"; 100 marvell,function = "gpio";
101 }; 101 };
102 pmx_led_rebuild_brt_ctrl_2: pmx-led-rebuild-brt-ctrl-2 { 102 pmx_led_rebuild_brt_ctrl_2: pmx-led-rebuild-brt-ctrl-2 {
103 marvell,pins = "mpp45"; 103 marvell,pins = "mpp47";
104 marvell,function = "gpio"; 104 marvell,function = "gpio";
105 }; 105 };
106 106
@@ -157,14 +157,14 @@
157 gpios = <&gpio0 16 0>; 157 gpios = <&gpio0 16 0>;
158 linux,default-trigger = "default-on"; 158 linux,default-trigger = "default-on";
159 }; 159 };
160 health_led1 { 160 rebuild_led {
161 label = "status:white:rebuild_led";
162 gpios = <&gpio1 4 0>;
163 };
164 health_led {
161 label = "status:red:health_led"; 165 label = "status:red:health_led";
162 gpios = <&gpio1 5 0>; 166 gpios = <&gpio1 5 0>;
163 }; 167 };
164 health_led2 {
165 label = "status:white:health_led";
166 gpios = <&gpio1 4 0>;
167 };
168 backup_led { 168 backup_led {
169 label = "status:blue:backup_led"; 169 label = "status:blue:backup_led";
170 gpios = <&gpio0 15 0>; 170 gpios = <&gpio0 15 0>;
diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi
index 8aad00f81ed9..892c64e3f1e1 100644
--- a/arch/arm/boot/dts/orion5x.dtsi
+++ b/arch/arm/boot/dts/orion5x.dtsi
@@ -13,6 +13,9 @@
13 compatible = "marvell,orion5x"; 13 compatible = "marvell,orion5x";
14 interrupt-parent = <&intc>; 14 interrupt-parent = <&intc>;
15 15
16 aliases {
17 gpio0 = &gpio0;
18 };
16 intc: interrupt-controller { 19 intc: interrupt-controller {
17 compatible = "marvell,orion-intc", "marvell,intc"; 20 compatible = "marvell,orion-intc", "marvell,intc";
18 interrupt-controller; 21 interrupt-controller;
@@ -32,7 +35,9 @@
32 #gpio-cells = <2>; 35 #gpio-cells = <2>;
33 gpio-controller; 36 gpio-controller;
34 reg = <0x10100 0x40>; 37 reg = <0x10100 0x40>;
35 ngpio = <32>; 38 ngpios = <32>;
39 interrupt-controller;
40 #interrupt-cells = <2>;
36 interrupts = <6>, <7>, <8>, <9>; 41 interrupts = <6>, <7>, <8>, <9>;
37 }; 42 };
38 43
@@ -69,6 +74,20 @@
69 status = "okay"; 74 status = "okay";
70 }; 75 };
71 76
77 ehci@50000 {
78 compatible = "marvell,orion-ehci";
79 reg = <0x50000 0x1000>;
80 interrupts = <17>;
81 status = "disabled";
82 };
83
84 ehci@a0000 {
85 compatible = "marvell,orion-ehci";
86 reg = <0xa0000 0x1000>;
87 interrupts = <12>;
88 status = "disabled";
89 };
90
72 sata@80000 { 91 sata@80000 {
73 compatible = "marvell,orion-sata"; 92 compatible = "marvell,orion-sata";
74 reg = <0x80000 0x5000>; 93 reg = <0x80000 0x5000>;
@@ -86,12 +105,31 @@
86 status = "disabled"; 105 status = "disabled";
87 }; 106 };
88 107
108 xor@60900 {
109 compatible = "marvell,orion-xor";
110 reg = <0x60900 0x100
111 0x60b00 0x100>;
112 status = "okay";
113
114 xor00 {
115 interrupts = <30>;
116 dmacap,memcpy;
117 dmacap,xor;
118 };
119 xor01 {
120 interrupts = <31>;
121 dmacap,memcpy;
122 dmacap,xor;
123 dmacap,memset;
124 };
125 };
126
89 crypto@90000 { 127 crypto@90000 {
90 compatible = "marvell,orion-crypto"; 128 compatible = "marvell,orion-crypto";
91 reg = <0x90000 0x10000>, 129 reg = <0x90000 0x10000>,
92 <0xf2200000 0x800>; 130 <0xf2200000 0x800>;
93 reg-names = "regs", "sram"; 131 reg-names = "regs", "sram";
94 interrupts = <22>; 132 interrupts = <28>;
95 status = "okay"; 133 status = "okay";
96 }; 134 };
97 }; 135 };
diff --git a/arch/arm/boot/dts/skeleton64.dtsi b/arch/arm/boot/dts/skeleton64.dtsi
new file mode 100644
index 000000000000..15994158a998
--- /dev/null
+++ b/arch/arm/boot/dts/skeleton64.dtsi
@@ -0,0 +1,13 @@
1/*
2 * Skeleton device tree in the 64 bits version; the bare minimum
3 * needed to boot; just include and add a compatible value. The
4 * bootloader will typically populate the memory node.
5 */
6
7/ {
8 #address-cells = <2>;
9 #size-cells = <2>;
10 chosen { };
11 aliases { };
12 memory { device_type = "memory"; reg = <0 0>; };
13};
diff --git a/arch/arm/configs/dove_defconfig b/arch/arm/configs/dove_defconfig
index 3fe8dae8d32d..4364eff5b01e 100644
--- a/arch/arm/configs/dove_defconfig
+++ b/arch/arm/configs/dove_defconfig
@@ -75,6 +75,8 @@ CONFIG_I2C_MV64XXX=y
75CONFIG_SPI=y 75CONFIG_SPI=y
76CONFIG_SPI_ORION=y 76CONFIG_SPI_ORION=y
77# CONFIG_HWMON is not set 77# CONFIG_HWMON is not set
78CONFIG_THERMAL=y
79CONFIG_DOVE_THERMAL=y
78CONFIG_USB=y 80CONFIG_USB=y
79CONFIG_USB_EHCI_HCD=y 81CONFIG_USB_EHCI_HCD=y
80CONFIG_USB_EHCI_ROOT_HUB_TT=y 82CONFIG_USB_EHCI_ROOT_HUB_TT=y
diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig
index 13482ea58b09..8f0065bb6f39 100644
--- a/arch/arm/configs/kirkwood_defconfig
+++ b/arch/arm/configs/kirkwood_defconfig
@@ -119,6 +119,8 @@ CONFIG_SPI=y
119CONFIG_SPI_ORION=y 119CONFIG_SPI_ORION=y
120CONFIG_GPIO_SYSFS=y 120CONFIG_GPIO_SYSFS=y
121# CONFIG_HWMON is not set 121# CONFIG_HWMON is not set
122CONFIG_THERMAL=y
123CONFIG_KIRKWOOD_THERMAL=y
122CONFIG_WATCHDOG=y 124CONFIG_WATCHDOG=y
123CONFIG_ORION_WATCHDOG=y 125CONFIG_ORION_WATCHDOG=y
124CONFIG_HID_DRAGONRISE=y 126CONFIG_HID_DRAGONRISE=y
diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig
index 2ec8119cff73..f3e8ae001ff1 100644
--- a/arch/arm/configs/mvebu_defconfig
+++ b/arch/arm/configs/mvebu_defconfig
@@ -46,9 +46,16 @@ CONFIG_I2C_MV64XXX=y
46CONFIG_MTD=y 46CONFIG_MTD=y
47CONFIG_MTD_CHAR=y 47CONFIG_MTD_CHAR=y
48CONFIG_MTD_M25P80=y 48CONFIG_MTD_M25P80=y
49CONFIG_MTD_CFI=y
50CONFIG_MTD_CFI_INTELEXT=y
51CONFIG_MTD_CFI_AMDSTD=y
52CONFIG_MTD_CFI_STAA=y
53CONFIG_MTD_PHYSMAP_OF=y
49CONFIG_SERIAL_8250_DW=y 54CONFIG_SERIAL_8250_DW=y
50CONFIG_GPIOLIB=y 55CONFIG_GPIOLIB=y
51CONFIG_GPIO_SYSFS=y 56CONFIG_GPIO_SYSFS=y
57CONFIG_THERMAL=y
58CONFIG_ARMADA_THERMAL=y
52CONFIG_USB_SUPPORT=y 59CONFIG_USB_SUPPORT=y
53CONFIG_USB=y 60CONFIG_USB=y
54CONFIG_USB_EHCI_HCD=y 61CONFIG_USB_EHCI_HCD=y
@@ -65,6 +72,8 @@ CONFIG_RTC_DRV_S35390A=y
65CONFIG_RTC_DRV_MV=y 72CONFIG_RTC_DRV_MV=y
66CONFIG_DMADEVICES=y 73CONFIG_DMADEVICES=y
67CONFIG_MV_XOR=y 74CONFIG_MV_XOR=y
75CONFIG_MEMORY=y
76CONFIG_MVEBU_DEVBUS=y
68# CONFIG_IOMMU_SUPPORT is not set 77# CONFIG_IOMMU_SUPPORT is not set
69CONFIG_EXT2_FS=y 78CONFIG_EXT2_FS=y
70CONFIG_EXT3_FS=y 79CONFIG_EXT3_FS=y
diff --git a/arch/arm/mach-kirkwood/board-guruplug.c b/arch/arm/mach-kirkwood/board-guruplug.c
index 0a0df4554d8b..a857163954a5 100644
--- a/arch/arm/mach-kirkwood/board-guruplug.c
+++ b/arch/arm/mach-kirkwood/board-guruplug.c
@@ -13,7 +13,6 @@
13#include <linux/init.h> 13#include <linux/init.h>
14#include <linux/mv643xx_eth.h> 14#include <linux/mv643xx_eth.h>
15#include <linux/gpio.h> 15#include <linux/gpio.h>
16#include <linux/platform_data/mmc-mvsdio.h>
17#include "common.h" 16#include "common.h"
18 17
19static struct mv643xx_eth_platform_data guruplug_ge00_data = { 18static struct mv643xx_eth_platform_data guruplug_ge00_data = {
@@ -24,10 +23,6 @@ static struct mv643xx_eth_platform_data guruplug_ge01_data = {
24 .phy_addr = MV643XX_ETH_PHY_ADDR(1), 23 .phy_addr = MV643XX_ETH_PHY_ADDR(1),
25}; 24};
26 25
27static struct mvsdio_platform_data guruplug_mvsdio_data = {
28 /* unfortunately the CD signal has not been connected */
29};
30
31void __init guruplug_dt_init(void) 26void __init guruplug_dt_init(void)
32{ 27{
33 /* 28 /*
@@ -35,5 +30,4 @@ void __init guruplug_dt_init(void)
35 */ 30 */
36 kirkwood_ge00_init(&guruplug_ge00_data); 31 kirkwood_ge00_init(&guruplug_ge00_data);
37 kirkwood_ge01_init(&guruplug_ge01_data); 32 kirkwood_ge01_init(&guruplug_ge01_data);
38 kirkwood_sdio_init(&guruplug_mvsdio_data);
39} 33}
diff --git a/arch/arm/mach-kirkwood/board-iomega_ix2_200.c b/arch/arm/mach-kirkwood/board-iomega_ix2_200.c
index f655b2637b0e..e5f70415905a 100644
--- a/arch/arm/mach-kirkwood/board-iomega_ix2_200.c
+++ b/arch/arm/mach-kirkwood/board-iomega_ix2_200.c
@@ -20,10 +20,15 @@ static struct mv643xx_eth_platform_data iomega_ix2_200_ge00_data = {
20 .duplex = DUPLEX_FULL, 20 .duplex = DUPLEX_FULL,
21}; 21};
22 22
23static struct mv643xx_eth_platform_data iomega_ix2_200_ge01_data = {
24 .phy_addr = MV643XX_ETH_PHY_ADDR(11),
25};
26
23void __init iomega_ix2_200_init(void) 27void __init iomega_ix2_200_init(void)
24{ 28{
25 /* 29 /*
26 * Basic setup. Needs to be called early. 30 * Basic setup. Needs to be called early.
27 */ 31 */
28 kirkwood_ge01_init(&iomega_ix2_200_ge00_data); 32 kirkwood_ge00_init(&iomega_ix2_200_ge00_data);
33 kirkwood_ge01_init(&iomega_ix2_200_ge01_data);
29} 34}
diff --git a/arch/arm/mach-kirkwood/guruplug-setup.c b/arch/arm/mach-kirkwood/guruplug-setup.c
index 1c6e736cbbf8..08dd739aa709 100644
--- a/arch/arm/mach-kirkwood/guruplug-setup.c
+++ b/arch/arm/mach-kirkwood/guruplug-setup.c
@@ -53,6 +53,8 @@ static struct mv_sata_platform_data guruplug_sata_data = {
53 53
54static struct mvsdio_platform_data guruplug_mvsdio_data = { 54static struct mvsdio_platform_data guruplug_mvsdio_data = {
55 /* unfortunately the CD signal has not been connected */ 55 /* unfortunately the CD signal has not been connected */
56 .gpio_card_detect = -1,
57 .gpio_write_protect = -1,
56}; 58};
57 59
58static struct gpio_led guruplug_led_pins[] = { 60static struct gpio_led guruplug_led_pins[] = {
diff --git a/arch/arm/mach-kirkwood/openrd-setup.c b/arch/arm/mach-kirkwood/openrd-setup.c
index 8ddd69fdc937..6a6eb548307d 100644
--- a/arch/arm/mach-kirkwood/openrd-setup.c
+++ b/arch/arm/mach-kirkwood/openrd-setup.c
@@ -55,6 +55,7 @@ static struct mv_sata_platform_data openrd_sata_data = {
55 55
56static struct mvsdio_platform_data openrd_mvsdio_data = { 56static struct mvsdio_platform_data openrd_mvsdio_data = {
57 .gpio_card_detect = 29, /* MPP29 used as SD card detect */ 57 .gpio_card_detect = 29, /* MPP29 used as SD card detect */
58 .gpio_write_protect = -1,
58}; 59};
59 60
60static unsigned int openrd_mpp_config[] __initdata = { 61static unsigned int openrd_mpp_config[] __initdata = {
diff --git a/arch/arm/mach-kirkwood/rd88f6281-setup.c b/arch/arm/mach-kirkwood/rd88f6281-setup.c
index c7d93b48926b..d24223166e06 100644
--- a/arch/arm/mach-kirkwood/rd88f6281-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6281-setup.c
@@ -69,6 +69,7 @@ static struct mv_sata_platform_data rd88f6281_sata_data = {
69 69
70static struct mvsdio_platform_data rd88f6281_mvsdio_data = { 70static struct mvsdio_platform_data rd88f6281_mvsdio_data = {
71 .gpio_card_detect = 28, 71 .gpio_card_detect = 28,
72 .gpio_write_protect = -1,
72}; 73};
73 74
74static unsigned int rd88f6281_mpp_config[] __initdata = { 75static unsigned int rd88f6281_mpp_config[] __initdata = {
diff --git a/arch/arm/mach-mvebu/irq-armada-370-xp.c b/arch/arm/mach-mvebu/irq-armada-370-xp.c
index 274ff58271de..d5970f5a1e8d 100644
--- a/arch/arm/mach-mvebu/irq-armada-370-xp.c
+++ b/arch/arm/mach-mvebu/irq-armada-370-xp.c
@@ -44,6 +44,8 @@
44 44
45#define ARMADA_370_XP_MAX_PER_CPU_IRQS (28) 45#define ARMADA_370_XP_MAX_PER_CPU_IRQS (28)
46 46
47#define ARMADA_370_XP_TIMER0_PER_CPU_IRQ (5)
48
47#define ACTIVE_DOORBELLS (8) 49#define ACTIVE_DOORBELLS (8)
48 50
49static DEFINE_RAW_SPINLOCK(irq_controller_lock); 51static DEFINE_RAW_SPINLOCK(irq_controller_lock);
@@ -59,36 +61,26 @@ static struct irq_domain *armada_370_xp_mpic_domain;
59 */ 61 */
60static void armada_370_xp_irq_mask(struct irq_data *d) 62static void armada_370_xp_irq_mask(struct irq_data *d)
61{ 63{
62#ifdef CONFIG_SMP
63 irq_hw_number_t hwirq = irqd_to_hwirq(d); 64 irq_hw_number_t hwirq = irqd_to_hwirq(d);
64 65
65 if (hwirq > ARMADA_370_XP_MAX_PER_CPU_IRQS) 66 if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
66 writel(hwirq, main_int_base + 67 writel(hwirq, main_int_base +
67 ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS); 68 ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
68 else 69 else
69 writel(hwirq, per_cpu_int_base + 70 writel(hwirq, per_cpu_int_base +
70 ARMADA_370_XP_INT_SET_MASK_OFFS); 71 ARMADA_370_XP_INT_SET_MASK_OFFS);
71#else
72 writel(irqd_to_hwirq(d),
73 per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS);
74#endif
75} 72}
76 73
77static void armada_370_xp_irq_unmask(struct irq_data *d) 74static void armada_370_xp_irq_unmask(struct irq_data *d)
78{ 75{
79#ifdef CONFIG_SMP
80 irq_hw_number_t hwirq = irqd_to_hwirq(d); 76 irq_hw_number_t hwirq = irqd_to_hwirq(d);
81 77
82 if (hwirq > ARMADA_370_XP_MAX_PER_CPU_IRQS) 78 if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
83 writel(hwirq, main_int_base + 79 writel(hwirq, main_int_base +
84 ARMADA_370_XP_INT_SET_ENABLE_OFFS); 80 ARMADA_370_XP_INT_SET_ENABLE_OFFS);
85 else 81 else
86 writel(hwirq, per_cpu_int_base + 82 writel(hwirq, per_cpu_int_base +
87 ARMADA_370_XP_INT_CLEAR_MASK_OFFS); 83 ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
88#else
89 writel(irqd_to_hwirq(d),
90 per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
91#endif
92} 84}
93 85
94#ifdef CONFIG_SMP 86#ifdef CONFIG_SMP
@@ -144,10 +136,14 @@ static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
144 unsigned int virq, irq_hw_number_t hw) 136 unsigned int virq, irq_hw_number_t hw)
145{ 137{
146 armada_370_xp_irq_mask(irq_get_irq_data(virq)); 138 armada_370_xp_irq_mask(irq_get_irq_data(virq));
147 writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS); 139 if (hw != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
140 writel(hw, per_cpu_int_base +
141 ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
142 else
143 writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
148 irq_set_status_flags(virq, IRQ_LEVEL); 144 irq_set_status_flags(virq, IRQ_LEVEL);
149 145
150 if (hw < ARMADA_370_XP_MAX_PER_CPU_IRQS) { 146 if (hw == ARMADA_370_XP_TIMER0_PER_CPU_IRQ) {
151 irq_set_percpu_devid(virq); 147 irq_set_percpu_devid(virq);
152 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip, 148 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
153 handle_percpu_devid_irq); 149 handle_percpu_devid_irq);
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-18 17:26:36 -0500