288 files changed, 12546 insertions, 6424 deletions

diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt b/Documentation/devicetree/bindings/arm/omap/omap.txt
index 6d498c758b45..91b7049affa1 100644
--- a/Documentation/devicetree/bindings/arm/omap/omap.txt
+++ b/Documentation/devicetree/bindings/arm/omap/omap.txt
@@ -59,3 +59,6 @@ Boards:
 
 - AM43x EPOS EVM
   compatible = "ti,am43x-epos-evm", "ti,am4372", "ti,am43"
+
+- DRA7 EVM:  Software Developement Board for DRA7XX
+  compatible = "ti,dra7-evm", "ti,dra7"
diff --git a/Documentation/devicetree/bindings/arm/vexpress-scc.txt b/Documentation/devicetree/bindings/arm/vexpress-scc.txt
new file mode 100644
index 000000000000..ae5043e42e5d
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/vexpress-scc.txt
@@ -0,0 +1,33 @@
+ARM Versatile Express Serial Configuration Controller
+-----------------------------------------------------
+
+Test chips for ARM Versatile Express platform implement SCC (Serial
+Configuration Controller) interface, used to set initial conditions
+for the test chip.
+
+In some cases its registers are also mapped in normal address space
+and can be used to obtain runtime information about the chip internals
+(like silicon temperature sensors) and as interface to other subsystems
+like platform configuration control and power management.
+
+Required properties:
+
+- compatible value: "arm,vexpress-scc,<model>", "arm,vexpress-scc";
+                    where <model> is the full tile model name (as used
+                    in the tile's Technical Reference Manual),
+                    eg. for Coretile Express A15x2 A7x3 (V2P-CA15_A7):
+        compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc";
+
+Optional properties:
+
+- reg: when the SCC is memory mapped, physical address and size of the
+       registers window
+- interrupts: when the SCC can generate a system-level interrupt
+
+Example:
+
+        scc@7fff0000 {
+                compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc";
+                reg = <0 0x7fff0000 0 0x1000>;
+                interrupts = <0 95 4>;
+        };
diff --git a/Documentation/devicetree/bindings/bus/imx-weim.txt b/Documentation/devicetree/bindings/bus/imx-weim.txt
index cedc2a9c4785..0fd76c405208 100644
--- a/Documentation/devicetree/bindings/bus/imx-weim.txt
+++ b/Documentation/devicetree/bindings/bus/imx-weim.txt
@@ -8,7 +8,7 @@ The actual devices are instantiated from the child nodes of a WEIM node.
 
 Required properties:
 
- - compatible:          Should be set to "fsl,imx6q-weim"
+ - compatible:          Should be set to "fsl,<soc>-weim"
  - reg:                 A resource specifier for the register space
                         (see the example below)
  - clocks:              the clock, see the example below.
@@ -21,11 +21,18 @@ Required properties:
 
 Timing property for child nodes. It is mandatory, not optional.
 
- - fsl,weim-cs-timing:  The timing array, contains 6 timing values for the
+ - fsl,weim-cs-timing:  The timing array, contains timing values for the
                         child node. We can get the CS index from the child
-                        node's "reg" property. This property contains the values
-                        for the registers EIM_CSnGCR1, EIM_CSnGCR2, EIM_CSnRCR1,
-                        EIM_CSnRCR2, EIM_CSnWCR1, EIM_CSnWCR2 in this order.
+                        node's "reg" property. The number of registers depends
+                        on the selected chip.
+                        For i.MX1, i.MX21 ("fsl,imx1-weim") there are two
+                        registers: CSxU, CSxL.
+                        For i.MX25, i.MX27, i.MX31 and i.MX35 ("fsl,imx27-weim")
+                        there are three registers: CSCRxU, CSCRxL, CSCRxA.
+                        For i.MX50, i.MX53 ("fsl,imx50-weim"),
+                        i.MX51 ("fsl,imx51-weim") and i.MX6Q ("fsl,imx6q-weim")
+                        there are six registers: CSxGCR1, CSxGCR2, CSxRCR1,
+                        CSxRCR2, CSxWCR1, CSxWCR2.
 
 Example for an imx6q-sabreauto board, the NOR flash connected to the WEIM:
 
diff --git a/Documentation/devicetree/bindings/bus/mvebu-mbus.txt b/Documentation/devicetree/bindings/bus/mvebu-mbus.txt
new file mode 100644
index 000000000000..7586fb68c072
--- /dev/null
+++ b/Documentation/devicetree/bindings/bus/mvebu-mbus.txt
@@ -0,0 +1,276 @@
+
+* Marvell MBus
+
+Required properties:
+
+- compatible:    Should be set to one of the following:
+                 marvell,armada370-mbus
+                 marvell,armadaxp-mbus
+                 marvell,armada370-mbus
+                 marvell,armadaxp-mbus
+                 marvell,kirkwood-mbus
+                 marvell,dove-mbus
+                 marvell,orion5x-88f5281-mbus
+                 marvell,orion5x-88f5182-mbus
+                 marvell,orion5x-88f5181-mbus
+                 marvell,orion5x-88f6183-mbus
+                 marvell,mv78xx0-mbus
+
+- address-cells: Must be '2'. The first cell for the MBus ID encoding,
+                 the second cell for the address offset within the window.
+
+- size-cells:    Must be '1'.
+
+- ranges:        Must be set up to provide a proper translation for each child.
+                 See the examples below.
+
+- controller:    Contains a single phandle referring to the MBus controller
+                 node. This allows to specify the node that contains the
+                 registers that control the MBus, which is typically contained
+                 within the internal register window (see below).
+
+Optional properties:
+
+- pcie-mem-aperture:    This optional property contains the aperture for
+                        the memory region of the PCIe driver.
+                        If it's defined, it must encode the base address and
+                        size for the address decoding windows allocated for
+                        the PCIe memory region.
+
+- pcie-io-aperture:     Just as explained for the above property, this
+                        optional property contains the aperture for the
+                        I/O region of the PCIe driver.
+
+* Marvell MBus controller
+
+Required properties:
+
+- compatible:   Should be set to "marvell,mbus-controller".
+
+- reg:          Device's register space.
+                Two entries are expected (see the examples below):
+                the first one controls the devices decoding window and
+                the second one controls the SDRAM decoding window.
+
+Example:
+
+        soc {
+                compatible = "marvell,armada370-mbus", "simple-bus";
+                #address-cells = <2>;
+                #size-cells = <1>;
+                controller = <&mbusc>;
+                pcie-mem-aperture = <0xe0000000 0x8000000>;
+                pcie-io-aperture  = <0xe8000000 0x100000>;
+
+                internal-regs {
+                        compatible = "simple-bus";
+
+                        mbusc: mbus-controller@20000 {
+                                compatible = "marvell,mbus-controller";
+                                reg = <0x20000 0x100>, <0x20180 0x20>;
+                        };
+
+                        /* more children ...*/
+                };
+        };
+
+** MBus address decoding window specification
+
+The MBus children address space is comprised of two cells: the first one for
+the window ID and the second one for the offset within the window.
+In order to allow to describe valid and non-valid window entries, the
+following encoding is used:
+
+  0xSIAA0000 0x00oooooo
+
+Where:
+
+  S = 0x0 for a MBus valid window
+  S = 0xf for a non-valid window (see below)
+
+If S = 0x0, then:
+
+   I = 4-bit window target ID
+  AA = windpw attribute
+
+If S = 0xf, then:
+
+   I = don't care
+   AA = 1 for internal register
+
+Following the above encoding, for each ranges entry for a MBus valid window
+(S = 0x0), an address decoding window is allocated. On the other side,
+entries for translation that do not correspond to valid windows (S = 0xf)
+are skipped.
+
+        soc {
+                compatible = "marvell,armada370-mbus", "simple-bus";
+                #address-cells = <2>;
+                #size-cells = <1>;
+                controller = <&mbusc>;
+
+                ranges = <0xf0010000 0 0 0xd0000000 0x100000
+                          0x01e00000 0 0 0xfff00000 0x100000>;
+
+                bootrom {
+                        compatible = "marvell,bootrom";
+                        reg = <0x01e00000 0 0x100000>;
+                };
+
+                /* other children */
+                ...
+
+                internal-regs {
+                        compatible = "simple-bus";
+                        ranges = <0 0xf0010000 0 0x100000>;
+
+                        mbusc: mbus-controller@20000 {
+                                compatible = "marvell,mbus-controller";
+                                reg = <0x20000 0x100>, <0x20180 0x20>;
+                        };
+
+                        /* more children ...*/
+                };
+        };
+
+In the shown example, the translation entry in the 'ranges' property is what
+makes the MBus driver create a static decoding window for the corresponding
+given child device. Note that the binding does not require child nodes to be
+present. Of course, child nodes are needed to probe the devices.
+
+Since each window is identified by its target ID and attribute ID there's
+a special macro that can be use to simplify the translation entries:
+
+#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
+
+Using this macro, the above example would be:
+
+        soc {
+                compatible = "marvell,armada370-mbus", "simple-bus";
+                #address-cells = <2>;
+                #size-cells = <1>;
+                controller = <&mbusc>;
+
+                ranges = < MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
+                           MBUS_ID(0x01, 0xe0) 0 0 0xfff00000 0x100000>;
+
+                bootrom {
+                        compatible = "marvell,bootrom";
+                        reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
+                };
+
+                /* other children */
+                ...
+
+                internal-regs {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
+
+                        mbusc: mbus-controller@20000 {
+                                compatible = "marvell,mbus-controller";
+                                reg = <0x20000 0x100>, <0x20180 0x20>;
+                        };
+
+                        /* other children */
+                        ...
+                };
+        };
+
+
+** About the window base address
+
+Remember the MBus controller allows a great deal of flexibility for choosing
+the decoding window base address. When planning the device tree layout it's
+possible to choose any address as the base address, provided of course there's
+a region large enough available, and with the required alignment.
+
+Yet in other words: there's nothing preventing us from setting a base address
+of 0xf0000000, or 0xd0000000 for the NOR device shown above, if such region is
+unused.
+
+** Window allocation policy
+
+The mbus-node ranges property defines a set of mbus windows that are expected
+to be set by the operating system and that are guaranteed to be free of overlaps
+with one another or with the system memory ranges.
+
+Each entry in the property refers to exactly one window. If the operating system
+choses to use a different set of mbus windows, it must ensure that any address
+translations performed from downstream devices are adapted accordingly.
+
+The operating system may insert additional mbus windows that do not conflict
+with the ones listed in the ranges, e.g. for mapping PCIe devices.
+As a special case, the internal register window must be set up by the boot
+loader at the address listed in the ranges property, since access to that region
+is needed to set up the other windows.
+
+** Example
+
+See the example below, where a more complete device tree is shown:
+
+        soc {
+                compatible = "marvell,armadaxp-mbus", "simple-bus";
+                controller = <&mbusc>;
+
+                ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000   /* internal-regs */
+                          MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
+                          MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x8000000>;
+
+                bootrom {
+                        compatible = "marvell,bootrom";
+                        reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
+                };
+
+                devbus-bootcs {
+                        status = "okay";
+                        ranges = <0 MBUS_ID(0x01, 0x2f) 0 0x8000000>;
+
+                        /* NOR */
+                        nor {
+                                compatible = "cfi-flash";
+                                reg = <0 0x8000000>;
+                                bank-width = <2>;
+                        };
+                };
+
+                pcie-controller {
+                        compatible = "marvell,armada-xp-pcie";
+                        status = "okay";
+                        device_type = "pci";
+
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+
+                        ranges =
+                               <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000   /* Port 0.0 registers */
+                                0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000   /* Port 2.0 registers */
+                                0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000   /* Port 0.1 registers */
+                                0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000   /* Port 0.2 registers */
+                                0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000   /* Port 0.3 registers */
+                                0x82000800 0 0xe0000000 MBUS_ID(0x04, 0xe8) 0xe0000000 0 0x08000000 /* Port 0.0 MEM */
+                                0x81000800 0 0          MBUS_ID(0x04, 0xe0) 0xe8000000 0 0x00100000 /* Port 0.0 IO */>;
+
+
+                        pcie@1,0 {
+                                /* Port 0, Lane 0 */
+                                status = "okay";
+                        };
+                };
+
+                internal-regs {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
+
+                        mbusc: mbus-controller@20000 {
+                                reg = <0x20000 0x100>, <0x20180 0x20>;
+                        };
+
+                        interrupt-controller@20000 {
+                              reg = <0x20a00 0x2d0>, <0x21070 0x58>;
+                        };
+                };
+        };
diff --git a/Documentation/devicetree/bindings/clock/imx5-clock.txt b/Documentation/devicetree/bindings/clock/imx5-clock.txt
index f46f5625d8ad..4c029a8739d3 100644
--- a/Documentation/devicetree/bindings/clock/imx5-clock.txt
+++ b/Documentation/devicetree/bindings/clock/imx5-clock.txt
@@ -197,6 +197,7 @@ clocks and IDs.
         spdif0_gate             183
         spdif1_gate             184
         spdif_ipg_gate          185
+        ocram                   186
 
 Examples (for mx53):
 
diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.txt b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
index a0e104f0527e..5a90a724b520 100644
--- a/Documentation/devicetree/bindings/clock/imx6q-clock.txt
+++ b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
@@ -209,6 +209,12 @@ clocks and IDs.
         pll5_post_div           194
         pll5_video_div          195
         eim_slow                196
+        spdif                   197
+        cko2_sel                198
+        cko2_podf               199
+        cko2                    200
+        cko                     201
+        vdoa                    202
 
 Examples:
 
diff --git a/Documentation/devicetree/bindings/pci/mvebu-pci.txt b/Documentation/devicetree/bindings/pci/mvebu-pci.txt
index f8d405897a94..9556e2fedf6d 100644
--- a/Documentation/devicetree/bindings/pci/mvebu-pci.txt
+++ b/Documentation/devicetree/bindings/pci/mvebu-pci.txt
@@ -1,6 +1,7 @@
 * Marvell EBU PCIe interfaces
 
 Mandatory properties:
+
 - compatible: one of the following values:
     marvell,armada-370-pcie
     marvell,armada-xp-pcie
@@ -10,11 +11,49 @@ Mandatory properties:
 - #interrupt-cells, set to <1>
 - bus-range: PCI bus numbers covered
 - device_type, set to "pci"
-- ranges: ranges for the PCI memory and I/O regions, as well as the
-  MMIO registers to control the PCIe interfaces.
+- ranges: ranges describing the MMIO registers to control the PCIe
+  interfaces, and ranges describing the MBus windows needed to access
+  the memory and I/O regions of each PCIe interface.
+
+The ranges describing the MMIO registers have the following layout:
+
+    0x82000000 0 r MBUS_ID(0xf0, 0x01) r 0 s
+
+where:
+
+  * r is a 32-bits value that gives the offset of the MMIO
+  registers of this PCIe interface, from the base of the internal
+  registers.
+
+  * s is a 32-bits value that give the size of this MMIO
+  registers area. This range entry translates the '0x82000000 0 r' PCI
+  address into the 'MBUS_ID(0xf0, 0x01) r' CPU address, which is part
+  of the internal register window (as identified by MBUS_ID(0xf0,
+  0x01)).
+
+The ranges describing the MBus windows have the following layout:
+
+    0x8t000000 s 0     MBUS_ID(w, a) 0 1 0
+
+where:
+
+   * t is the type of the MBus window (as defined by the standard PCI DT
+   bindings), 1 for I/O and 2 for memory.
 
-In addition, the Device Tree node must have sub-nodes describing each
+   * s is the PCI slot that corresponds to this PCIe interface
+
+   * w is the 'target ID' value for the MBus window
+
+   * a the 'attribute' value for the MBus window.
+
+Since the location and size of the different MBus windows is not fixed in
+hardware, and only determined in runtime, those ranges cover the full first
+4 GB of the physical address space, and do not translate into a valid CPU
+address.
+
+In addition, the device tree node must have sub-nodes describing each
 PCIe interface, having the following mandatory properties:
+
 - reg: used only for interrupt mapping, so only the first four bytes
   are used to refer to the correct bus number and device number.
 - assigned-addresses: reference to the MMIO registers used to control
@@ -26,7 +65,8 @@ PCIe interface, having the following mandatory properties:
 - #address-cells, set to <3>
 - #size-cells, set to <2>
 - #interrupt-cells, set to <1>
-- ranges, empty property.
+- ranges, translating the MBus windows ranges of the parent node into
+  standard PCI addresses.
 - interrupt-map-mask and interrupt-map, standard PCI properties to
   define the mapping of the PCIe interface to interrupt numbers.
 
@@ -47,27 +87,50 @@ pcie-controller {
 
         bus-range = <0x00 0xff>;
 
-        ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000   /* Port 0.0 registers */
-                  0x82000000 0 0xd0042000 0xd0042000 0 0x00002000   /* Port 2.0 registers */
-                  0x82000000 0 0xd0044000 0xd0044000 0 0x00002000   /* Port 0.1 registers */
-                  0x82000000 0 0xd0048000 0xd0048000 0 0x00002000   /* Port 0.2 registers */
-                  0x82000000 0 0xd004c000 0xd004c000 0 0x00002000   /* Port 0.3 registers */
-                  0x82000000 0 0xd0080000 0xd0080000 0 0x00002000   /* Port 1.0 registers */
-                  0x82000000 0 0xd0082000 0xd0082000 0 0x00002000   /* Port 3.0 registers */
-                  0x82000000 0 0xd0084000 0xd0084000 0 0x00002000   /* Port 1.1 registers */
-                  0x82000000 0 0xd0088000 0xd0088000 0 0x00002000   /* Port 1.2 registers */
-                  0x82000000 0 0xd008c000 0xd008c000 0 0x00002000   /* Port 1.3 registers */
-                  0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
-                  0x81000000 0 0          0xe8000000 0 0x00100000>; /* downstream I/O */
+        ranges =
+               <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000   /* Port 0.0 registers */
+                0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000   /* Port 2.0 registers */
+                0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000   /* Port 0.1 registers */
+                0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000   /* Port 0.2 registers */
+                0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000   /* Port 0.3 registers */
+                0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000   /* Port 1.0 registers */
+                0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000   /* Port 3.0 registers */
+                0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000   /* Port 1.1 registers */
+                0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000   /* Port 1.2 registers */
+                0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000   /* Port 1.3 registers */
+                0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
+                0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO  */
+                0x82000000 0x2 0     MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
+                0x81000000 0x2 0     MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO  */
+                0x82000000 0x3 0     MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
+                0x81000000 0x3 0     MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO  */
+                0x82000000 0x4 0     MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
+                0x81000000 0x4 0     MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO  */
+
+                0x82000000 0x5 0     MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
+                0x81000000 0x5 0     MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO  */
+                0x82000000 0x6 0     MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
+                0x81000000 0x6 0     MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO  */
+                0x82000000 0x7 0     MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
+                0x81000000 0x7 0     MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO  */
+                0x82000000 0x8 0     MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
+                0x81000000 0x8 0     MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO  */
+
+                0x82000000 0x9 0     MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
+                0x81000000 0x9 0     MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO  */
+
+                0x82000000 0xa 0     MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
+                0x81000000 0xa 0     MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO  */>;
 
         pcie@1,0 {
                 device_type = "pci";
-                assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>;
+                assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
                 reg = <0x0800 0 0 0 0>;
                 #address-cells = <3>;
                 #size-cells = <2>;
                 #interrupt-cells = <1>;
-                ranges;
+                ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
+                          0x81000000 0 0 0x81000000 0x1 0 1 0>;
                 interrupt-map-mask = <0 0 0 0>;
                 interrupt-map = <0 0 0 0 &mpic 58>;
                 marvell,pcie-port = <0>;
@@ -78,12 +141,13 @@ pcie-controller {
 
         pcie@2,0 {
                 device_type = "pci";
-                assigned-addresses = <0x82001000 0 0xd0044000 0 0x2000>;
+                assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
                 reg = <0x1000 0 0 0 0>;
                 #address-cells = <3>;
                 #size-cells = <2>;
                 #interrupt-cells = <1>;
-                ranges;
+                ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
+                          0x81000000 0 0 0x81000000 0x2 0 1 0>;
                 interrupt-map-mask = <0 0 0 0>;
                 interrupt-map = <0 0 0 0 &mpic 59>;
                 marvell,pcie-port = <0>;
@@ -94,12 +158,13 @@ pcie-controller {
 
         pcie@3,0 {
                 device_type = "pci";
-                assigned-addresses = <0x82001800 0 0xd0048000 0 0x2000>;
+                assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
                 reg = <0x1800 0 0 0 0>;
                 #address-cells = <3>;
                 #size-cells = <2>;
                 #interrupt-cells = <1>;
-                ranges;
+                ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
+                          0x81000000 0 0 0x81000000 0x3 0 1 0>;
                 interrupt-map-mask = <0 0 0 0>;
                 interrupt-map = <0 0 0 0 &mpic 60>;
                 marvell,pcie-port = <0>;
@@ -110,12 +175,13 @@ pcie-controller {
 
         pcie@4,0 {
                 device_type = "pci";
-                assigned-addresses = <0x82002000 0 0xd004c000 0 0x2000>;
+                assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
                 reg = <0x2000 0 0 0 0>;
                 #address-cells = <3>;
                 #size-cells = <2>;
                 #interrupt-cells = <1>;
-                ranges;
+                ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
+                          0x81000000 0 0 0x81000000 0x4 0 1 0>;
                 interrupt-map-mask = <0 0 0 0>;
                 interrupt-map = <0 0 0 0 &mpic 61>;
                 marvell,pcie-port = <0>;
@@ -126,12 +192,13 @@ pcie-controller {
 
         pcie@5,0 {
                 device_type = "pci";
-                assigned-addresses = <0x82002800 0 0xd0080000 0 0x2000>;
+                assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
                 reg = <0x2800 0 0 0 0>;
                 #address-cells = <3>;
                 #size-cells = <2>;
                 #interrupt-cells = <1>;
-                ranges;
+                ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
+                          0x81000000 0 0 0x81000000 0x5 0 1 0>;
                 interrupt-map-mask = <0 0 0 0>;
                 interrupt-map = <0 0 0 0 &mpic 62>;
                 marvell,pcie-port = <1>;
@@ -142,12 +209,13 @@ pcie-controller {
 
         pcie@6,0 {
                 device_type = "pci";
-                assigned-addresses = <0x82003000 0 0xd0084000 0 0x2000>;
+                assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
                 reg = <0x3000 0 0 0 0>;
                 #address-cells = <3>;
                 #size-cells = <2>;
                 #interrupt-cells = <1>;
-                ranges;
+                ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
+                          0x81000000 0 0 0x81000000 0x6 0 1 0>;
                 interrupt-map-mask = <0 0 0 0>;
                 interrupt-map = <0 0 0 0 &mpic 63>;
                 marvell,pcie-port = <1>;
@@ -158,12 +226,13 @@ pcie-controller {
 
         pcie@7,0 {
                 device_type = "pci";
-                assigned-addresses = <0x82003800 0 0xd0088000 0 0x2000>;
+                assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
                 reg = <0x3800 0 0 0 0>;
                 #address-cells = <3>;
                 #size-cells = <2>;
                 #interrupt-cells = <1>;
-                ranges;
+                ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
+                          0x81000000 0 0 0x81000000 0x7 0 1 0>;
                 interrupt-map-mask = <0 0 0 0>;
                 interrupt-map = <0 0 0 0 &mpic 64>;
                 marvell,pcie-port = <1>;
@@ -174,12 +243,13 @@ pcie-controller {
 
         pcie@8,0 {
                 device_type = "pci";
-                assigned-addresses = <0x82004000 0 0xd008c000 0 0x2000>;
+                assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
                 reg = <0x4000 0 0 0 0>;
                 #address-cells = <3>;
                 #size-cells = <2>;
                 #interrupt-cells = <1>;
-                ranges;
+                ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
+                          0x81000000 0 0 0x81000000 0x8 0 1 0>;
                 interrupt-map-mask = <0 0 0 0>;
                 interrupt-map = <0 0 0 0 &mpic 65>;
                 marvell,pcie-port = <1>;
@@ -187,14 +257,16 @@ pcie-controller {
                 clocks = <&gateclk 12>;
                 status = "disabled";
         };
+
         pcie@9,0 {
                 device_type = "pci";
-                assigned-addresses = <0x82004800 0 0xd0042000 0 0x2000>;
+                assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
                 reg = <0x4800 0 0 0 0>;
                 #address-cells = <3>;
                 #size-cells = <2>;
                 #interrupt-cells = <1>;
-                ranges;
+                ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
+                          0x81000000 0 0 0x81000000 0x9 0 1 0>;
                 interrupt-map-mask = <0 0 0 0>;
                 interrupt-map = <0 0 0 0 &mpic 99>;
                 marvell,pcie-port = <2>;
@@ -205,12 +277,13 @@ pcie-controller {
 
         pcie@10,0 {
                 device_type = "pci";
-                assigned-addresses = <0x82005000 0 0xd0082000 0 0x2000>;
+                assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
                 reg = <0x5000 0 0 0 0>;
                 #address-cells = <3>;
                 #size-cells = <2>;
                 #interrupt-cells = <1>;
-                ranges;
+                ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
+                          0x81000000 0 0 0x81000000 0xa 0 1 0>;
                 interrupt-map-mask = <0 0 0 0>;
                 interrupt-map = <0 0 0 0 &mpic 103>;
                 marvell,pcie-port = <3>;
diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
new file mode 100644
index 000000000000..6b7510775c50
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
@@ -0,0 +1,163 @@
+NVIDIA Tegra PCIe controller
+
+Required properties:
+- compatible: "nvidia,tegra20-pcie" or "nvidia,tegra30-pcie"
+- device_type: Must be "pci"
+- reg: A list of physical base address and length for each set of controller
+  registers. Must contain an entry for each entry in the reg-names property.
+- reg-names: Must include the following entries:
+  "pads": PADS registers
+  "afi": AFI registers
+  "cs": configuration space region
+- interrupts: A list of interrupt outputs of the controller. Must contain an
+  entry for each entry in the interrupt-names property.
+- interrupt-names: Must include the following entries:
+  "intr": The Tegra interrupt that is asserted for controller interrupts
+  "msi": The Tegra interrupt that is asserted when an MSI is received
+- pex-clk-supply: Supply voltage for internal reference clock
+- vdd-supply: Power supply for controller (1.05V)
+- avdd-supply: Power supply for controller (1.05V) (not required for Tegra20)
+- bus-range: Range of bus numbers associated with this controller
+- #address-cells: Address representation for root ports (must be 3)
+  - cell 0 specifies the bus and device numbers of the root port:
+    [23:16]: bus number
+    [15:11]: device number
+  - cell 1 denotes the upper 32 address bits and should be 0
+  - cell 2 contains the lower 32 address bits and is used to translate to the
+    CPU address space
+- #size-cells: Size representation for root ports (must be 2)
+- ranges: Describes the translation of addresses for root ports and standard
+  PCI regions. The entries must be 6 cells each, where the first three cells
+  correspond to the address as described for the #address-cells property
+  above, the fourth cell is the physical CPU address to translate to and the
+  fifth and six cells are as described for the #size-cells property above.
+  - The first two entries are expected to translate the addresses for the root
+    port registers, which are referenced by the assigned-addresses property of
+    the root port nodes (see below).
+  - The remaining entries setup the mapping for the standard I/O, memory and
+    prefetchable PCI regions. The first cell determines the type of region
+    that is setup:
+    - 0x81000000: I/O memory region
+    - 0x82000000: non-prefetchable memory region
+    - 0xc2000000: prefetchable memory region
+  Please refer to the standard PCI bus binding document for a more detailed
+  explanation.
+- clocks: List of clock inputs of the controller. Must contain an entry for
+  each entry in the clock-names property.
+- clock-names: Must include the following entries:
+  "pex": The Tegra clock of that name
+  "afi": The Tegra clock of that name
+  "pcie_xclk": The Tegra clock of that name
+  "pll_e": The Tegra clock of that name
+  "cml": The Tegra clock of that name (not required for Tegra20)
+
+Root ports are defined as subnodes of the PCIe controller node.
+
+Required properties:
+- device_type: Must be "pci"
+- assigned-addresses: Address and size of the port configuration registers
+- reg: PCI bus address of the root port
+- #address-cells: Must be 3
+- #size-cells: Must be 2
+- ranges: Sub-ranges distributed from the PCIe controller node. An empty
+  property is sufficient.
+- nvidia,num-lanes: Number of lanes to use for this port. Valid combinations
+  are:
+  - Root port 0 uses 4 lanes, root port 1 is unused.
+  - Both root ports use 2 lanes.
+
+Example:
+
+SoC DTSI:
+
+        pcie-controller {
+                compatible = "nvidia,tegra20-pcie";
+                device_type = "pci";
+                reg = <0x80003000 0x00000800   /* PADS registers */
+                       0x80003800 0x00000200   /* AFI registers */
+                       0x90000000 0x10000000>; /* configuration space */
+                reg-names = "pads", "afi", "cs";
+                interrupts = <0 98 0x04   /* controller interrupt */
+                              0 99 0x04>; /* MSI interrupt */
+                interrupt-names = "intr", "msi";
+
+                bus-range = <0x00 0xff>;
+                #address-cells = <3>;
+                #size-cells = <2>;
+
+                ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000   /* port 0 registers */
+                          0x82000000 0 0x80001000 0x80001000 0 0x00001000   /* port 1 registers */
+                          0x81000000 0 0          0x82000000 0 0x00010000   /* downstream I/O */
+                          0x82000000 0 0xa0000000 0xa0000000 0 0x10000000   /* non-prefetchable memory */
+                          0xc2000000 0 0xb0000000 0xb0000000 0 0x10000000>; /* prefetchable memory */
+
+                clocks = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 74>,
+                         <&tegra_car 118>;
+                clock-names = "pex", "afi", "pcie_xclk", "pll_e";
+                status = "disabled";
+
+                pci@1,0 {
+                        device_type = "pci";
+                        assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
+                        reg = <0x000800 0 0 0 0>;
+                        status = "disabled";
+
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+
+                        ranges;
+
+                        nvidia,num-lanes = <2>;
+                };
+
+                pci@2,0 {
+                        device_type = "pci";
+                        assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
+                        reg = <0x001000 0 0 0 0>;
+                        status = "disabled";
+
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+
+                        ranges;
+
+                        nvidia,num-lanes = <2>;
+                };
+        };
+
+
+Board DTS:
+
+        pcie-controller {
+                status = "okay";
+
+                vdd-supply = <&pci_vdd_reg>;
+                pex-clk-supply = <&pci_clk_reg>;
+
+                /* root port 00:01.0 */
+                pci@1,0 {
+                        status = "okay";
+
+                        /* bridge 01:00.0 (optional) */
+                        pci@0,0 {
+                                reg = <0x010000 0 0 0 0>;
+
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+
+                                device_type = "pci";
+
+                                /* endpoint 02:00.0 */
+                                pci@0,0 {
+                                        reg = <0x020000 0 0 0 0>;
+                                };
+                        };
+                };
+        };
+
+Note that devices on the PCI bus are dynamically discovered using PCI's bus
+enumeration and therefore don't need corresponding device nodes in DT. However
+if a device on the PCI bus provides a non-probeable bus such as I2C or SPI,
+device nodes need to be added in order to allow the bus' children to be
+instantiated at the proper location in the operating system's device tree (as
+illustrated by the optional nodes in the example above).
diff --git a/Documentation/devicetree/bindings/watchdog/sun4i-wdt.txt b/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt
index ecd650adff31..e39cb266c8f4 100644
--- a/Documentation/devicetree/bindings/watchdog/sun4i-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt
@@ -1,8 +1,9 @@
-Allwinner sun4i Watchdog timer
+Allwinner SoCs Watchdog timer
 
 Required properties:
 
-- compatible : should be "allwinner,sun4i-wdt"
+- compatible : should be "allwinner,<soc-family>-wdt", the currently supported
+  SoC families being sun4i and sun6i
 - reg : Specifies base physical address and size of the registers.
 
 Example:
diff --git a/MAINTAINERS b/MAINTAINERS
index 6bc2d87b042f..10533173e153 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6315,6 +6315,13 @@ F:	Documentation/PCI/
 F:      drivers/pci/
 F:      include/linux/pci*
 
+PCI DRIVER FOR NVIDIA TEGRA
+M:      Thierry Reding <thierry.reding@gmail.com>
+L:      linux-tegra@vger.kernel.org
+S:      Supported
+F:      Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
+F:      drivers/pci/host/pci-tegra.c
+
 PCMCIA SUBSYSTEM
 P:      Linux PCMCIA Team
 L:      linux-pcmcia@lists.infradead.org
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index bf7976439c39..a00f4c1c7d71 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -442,7 +442,6 @@ config ARCH_NETX
 config ARCH_IOP13XX
         bool "IOP13xx-based"
         depends on MMU
-        select ARCH_SUPPORTS_MSI
         select CPU_XSC3
         select NEED_MACH_MEMORY_H
         select NEED_RET_TO_USER
@@ -1600,7 +1599,7 @@ config ARM_PSCI
 config ARCH_NR_GPIO
         int
         default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
-        default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5
+        default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX
         default 392 if ARCH_U8500
         default 352 if ARCH_VT8500
         default 288 if ARCH_SUNXI
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 454288db3180..f9f4c4d9c704 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -91,6 +91,7 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \
         kirkwood-ns2max.dtb \
         kirkwood-ns2mini.dtb \
         kirkwood-nsa310.dtb \
+        kirkwood-nsa310a.dtb \
         kirkwood-sheevaplug.dtb \
         kirkwood-sheevaplug-esata.dtb \
         kirkwood-topkick.dtb \
@@ -102,7 +103,9 @@ dtb-$(CONFIG_ARCH_MSM) += msm8660-surf.dtb \
         msm8960-cdp.dtb
 dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \
         armada-370-mirabox.dtb \
+        armada-370-netgear-rn102.dtb \
         armada-370-rd.dtb \
+        armada-xp-axpwifiap.dtb \
         armada-xp-db.dtb \
         armada-xp-gp.dtb \
         armada-xp-openblocks-ax3-4.dtb
@@ -114,6 +117,8 @@ dtb-$(CONFIG_ARCH_MXC) += \
         imx27-pdk.dtb \
         imx27-phytec-phycore-som.dtb \
         imx27-phytec-phycore-rdk.dtb \
+        imx27-phytec-phycard-s-som.dtb \
+        imx27-phytec-phycard-s-rdk.dtb \
         imx31-bug.dtb \
         imx51-apf51.dtb \
         imx51-apf51dev.dtb \
@@ -133,6 +138,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
         imx6q-sabrelite.dtb \
         imx6q-sabresd.dtb \
         imx6q-sbc6x.dtb \
+        imx6q-wandboard.dtb \
         imx6sl-evk.dtb \
         vf610-twr.dtb
 dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
index beee1699d49e..90ce29dbe119 100644
--- a/arch/arm/boot/dts/armada-370-db.dts
+++ b/arch/arm/boot/dts/armada-370-db.dts
@@ -14,7 +14,7 @@
  */
 
 /dts-v1/;
-/include/ "armada-370.dtsi"
+#include "armada-370.dtsi"
 
 / {
         model = "Marvell Armada 370 Evaluation Board";
@@ -30,6 +30,9 @@
         };
 
         soc {
+                ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
+                          MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
+
                 internal-regs {
                         serial@12000 {
                                 clock-frequency = <200000000>;
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts
index 45b107763e3b..2471d9da767b 100644
--- a/arch/arm/boot/dts/armada-370-mirabox.dts
+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
@@ -9,7 +9,7 @@
  */
 
 /dts-v1/;
-/include/ "armada-370.dtsi"
+#include "armada-370.dtsi"
 
 / {
         model = "Globalscale Mirabox";
@@ -25,6 +25,25 @@
         };
 
         soc {
+                ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
+                          MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
+
+                pcie-controller {
+                        status = "okay";
+
+                        /* Internal mini-PCIe connector */
+                        pcie@1,0 {
+                                /* Port 0, Lane 0 */
+                                status = "okay";
+                        };
+
+                        /* Connected on the PCB to a USB 3.0 XHCI controller */
+                        pcie@2,0 {
+                                /* Port 1, Lane 0 */
+                                status = "okay";
+                        };
+                };
+
                 internal-regs {
                         serial@12000 {
                                 clock-frequency = <200000000>;
@@ -120,22 +139,6 @@
                                         reg = <0x25>;
                                 };
                         };
-
-                        pcie-controller {
-                                status = "okay";
-
-                                /* Internal mini-PCIe connector */
-                                pcie@1,0 {
-                                        /* Port 0, Lane 0 */
-                                        status = "okay";
-                                };
-
-                                /* Connected on the PCB to a USB 3.0 XHCI controller */
-                                pcie@2,0 {
-                                        /* Port 1, Lane 0 */
-                                        status = "okay";
-                                };
-                        };
                 };
         };
 };
diff --git a/arch/arm/boot/dts/armada-370-netgear-rn102.dts b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
new file mode 100644
index 000000000000..05e4485a8225
--- /dev/null
+++ b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
@@ -0,0 +1,179 @@
+/*
+ * Device Tree file for NETGEAR ReadyNAS 102
+ *
+ * Copyright (C) 2013, Arnaud EBALARD <arno@natisbad.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+/dts-v1/;
+
+#include "armada-370.dtsi"
+
+/ {
+        model = "NETGEAR ReadyNAS 102";
+        compatible = "netgear,readynas-102", "marvell,armada370", "marvell,armada-370-xp";
+
+        chosen {
+                bootargs = "console=ttyS0,115200 earlyprintk";
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x20000000>; /* 512 MB */
+        };
+
+        soc {
+                internal-regs {
+                        serial@12000 {
+                                clock-frequency = <200000000>;
+                                status = "okay";
+                        };
+
+                        sata@a0000 {
+                                nr-ports = <2>;
+                                status = "okay";
+                        };
+
+                        pinctrl {
+                                power_led_pin: power-led-pin {
+                                        marvell,pins = "mpp57";
+                                        marvell,function = "gpio";
+                                };
+                                sata1_led_pin: sata1-led-pin {
+                                        marvell,pins = "mpp15";
+                                        marvell,function = "gpio";
+                                };
+
+                                sata2_led_pin: sata2-led-pin {
+                                        marvell,pins = "mpp14";
+                                        marvell,function = "gpio";
+                                };
+
+                                backup_led_pin: backup-led-pin {
+                                        marvell,pins = "mpp56";
+                                        marvell,function = "gpio";
+                                };
+                        };
+
+                        mdio {
+                                phy0: ethernet-phy@0 {
+                                        reg = <0>;
+                                };
+                        };
+
+                        ethernet@74000 {
+                                status = "okay";
+                                phy = <&phy0>;
+                                phy-mode = "rgmii-id";
+                        };
+
+                        usb@50000 {
+                                status = "okay";
+                        };
+
+                        i2c@11000 {
+                                compatible = "marvell,mv64xxx-i2c";
+                                clock-frequency = <100000>;
+                                status = "okay";
+
+                                g762: g762@3e {
+                                        compatible = "gmt,g762";
+                                        reg = <0x3e>;
+                                        clocks = <&g762_clk>; /* input clock */
+                                        fan_gear_mode = <0>;
+                                        fan_startv = <1>;
+                                        pwm_polarity = <0>;
+                                };
+                        };
+
+                        pcie-controller {
+                                status = "okay";
+
+                                /* Connected to Marvell SATA controller */
+                                pcie@1,0 {
+                                        /* Port 0, Lane 0 */
+                                        status = "okay";
+                                };
+
+                                /* Connected to FL1009 USB 3.0 controller */
+                                pcie@2,0 {
+                                        /* Port 1, Lane 0 */
+                                        status = "okay";
+                                };
+                        };
+                };
+        };
+
+        clocks {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               g762_clk: fixedclk {
+                         compatible = "fixed-clock";
+                         #clock-cells = <0>;
+                         clock-frequency = <8192>;
+               };
+        };
+
+        gpio_leds {
+                compatible = "gpio-leds";
+                pinctrl-0 = < &power_led_pin
+                              &sata1_led_pin
+                              &sata2_led_pin
+                              &backup_led_pin >;
+                pinctrl-names = "default";
+
+                blue_power_led {
+                        label = "rn102:blue:pwr";
+                        gpios = <&gpio1 25 1>;  /* GPIO 57 Active Low */
+                        linux,default-trigger = "heartbeat";
+                };
+
+                green_sata1_led {
+                        label = "rn102:green:sata1";
+                        gpios = <&gpio0 15 1>;  /* GPIO 15 Active Low */
+                        default-state = "on";
+                };
+
+                green_sata2_led {
+                        label = "rn102:green:sata2";
+                        gpios = <&gpio0 14 1>;   /* GPIO 14 Active Low */
+                        default-state = "on";
+                };
+
+                green_backup_led {
+                        label = "rn102:green:backup";
+                        gpios = <&gpio1 24 1>;   /* GPIO 56 Active Low */
+                        default-state = "on";
+                };
+        };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                button@1 {
+                        label = "Power Button";
+                        linux,code = <116>;     /* KEY_POWER */
+                        gpios = <&gpio1 30 1>;
+                };
+
+                button@2 {
+                        label = "Reset Button";
+                        linux,code = <0x198>;   /* KEY_RESTART */
+                        gpios = <&gpio0 6 1>;
+                };
+
+                button@3 {
+                        label = "Backup Button";
+                        linux,code = <133>;     /* KEY_COPY */
+                        gpios = <&gpio1 26 1>;
+                };
+        };
+
+};
diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts
index a3a2fedb8726..f81810a59629 100644
--- a/arch/arm/boot/dts/armada-370-rd.dts
+++ b/arch/arm/boot/dts/armada-370-rd.dts
@@ -12,7 +12,7 @@
  */
 
 /dts-v1/;
-/include/ "armada-370.dtsi"
+#include "armada-370.dtsi"
 
 / {
         model = "Marvell Armada 370 Reference Design";
@@ -28,6 +28,25 @@
         };
 
         soc {
+                ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
+                          MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
+
+                pcie-controller {
+                        status = "okay";
+
+                        /* Internal mini-PCIe connector */
+                        pcie@1,0 {
+                                /* Port 0, Lane 0 */
+                                status = "okay";
+                        };
+
+                        /* Internal mini-PCIe connector */
+                        pcie@2,0 {
+                                /* Port 1, Lane 0 */
+                                status = "okay";
+                        };
+                };
+
                 internal-regs {
                         serial@12000 {
                                 clock-frequency = <200000000>;
@@ -85,22 +104,6 @@
                                         gpios = <&gpio0 6 1>;
                                 };
                         };
-
-                        pcie-controller {
-                                status = "okay";
-
-                                /* Internal mini-PCIe connector */
-                                pcie@1,0 {
-                                        /* Port 0, Lane 0 */
-                                        status = "okay";
-                                };
-
-                                /* Internal mini-PCIe connector */
-                                pcie@2,0 {
-                                        /* Port 1, Lane 0 */
-                                        status = "okay";
-                                };
-                        };
                 };
         };
  };
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 90b117624abb..1de2dae0fdae 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -18,6 +18,8 @@
 
 /include/ "skeleton64.dtsi"
 
+#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
+
 / {
         model = "Marvell Armada 370 and XP SoC";
         compatible = "marvell,armada-370-xp";
@@ -38,18 +40,73 @@
         };
 
         soc {
-                #address-cells = <1>;
+                #address-cells = <2>;
                 #size-cells = <1>;
-                compatible = "simple-bus";
+                controller = <&mbusc>;
                 interrupt-parent = <&mpic>;
-                ranges = <0          0 0xd0000000 0x0100000 /* internal registers */
-                          0xe0000000 0 0xe0000000 0x8100000 /* PCIe */>;
+                pcie-mem-aperture = <0xe0000000 0x8000000>;
+                pcie-io-aperture  = <0xe8000000 0x100000>;
+
+                devbus-bootcs {
+                        compatible = "marvell,mvebu-devbus";
+                        reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
+                        ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        clocks = <&coreclk 0>;
+                        status = "disabled";
+                };
+
+                devbus-cs0 {
+                        compatible = "marvell,mvebu-devbus";
+                        reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
+                        ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        clocks = <&coreclk 0>;
+                        status = "disabled";
+                };
+
+                devbus-cs1 {
+                        compatible = "marvell,mvebu-devbus";
+                        reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
+                        ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        clocks = <&coreclk 0>;
+                        status = "disabled";
+                };
+
+                devbus-cs2 {
+                        compatible = "marvell,mvebu-devbus";
+                        reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
+                        ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        clocks = <&coreclk 0>;
+                        status = "disabled";
+                };
+
+                devbus-cs3 {
+                        compatible = "marvell,mvebu-devbus";
+                        reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
+                        ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        clocks = <&coreclk 0>;
+                        status = "disabled";
+                };
 
                 internal-regs {
                         compatible = "simple-bus";
                         #address-cells = <1>;
                         #size-cells = <1>;
-                        ranges;
+                        ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
+
+                        mbusc: mbus-controller@20000 {
+                                compatible = "marvell,mbus-controller";
+                                reg = <0x20000 0x100>, <0x20180 0x20>;
+                        };
 
                         mpic: interrupt-controller@20000 {
                                 compatible = "marvell,mpic";
@@ -81,10 +138,8 @@
                         };
 
                         timer@20300 {
-                                compatible = "marvell,armada-370-xp-timer";
                                 reg = <0x20300 0x30>, <0x21040 0x30>;
                                 interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
-                                clocks = <&coreclk 2>;
                         };
 
                         sata@a0000 {
@@ -195,50 +250,6 @@
                                 status = "disabled";
                         };
 
-                        devbus-bootcs@10400 {
-                                compatible = "marvell,mvebu-devbus";
-                                reg = <0x10400 0x8>;
-                                #address-cells = <1>;
-                                #size-cells = <1>;
-                                clocks = <&coreclk 0>;
-                                status = "disabled";
-                        };
-
-                        devbus-cs0@10408 {
-                                compatible = "marvell,mvebu-devbus";
-                                reg = <0x10408 0x8>;
-                                #address-cells = <1>;
-                                #size-cells = <1>;
-                                clocks = <&coreclk 0>;
-                                status = "disabled";
-                        };
-
-                        devbus-cs1@10410 {
-                                compatible = "marvell,mvebu-devbus";
-                                reg = <0x10410 0x8>;
-                                #address-cells = <1>;
-                                #size-cells = <1>;
-                                clocks = <&coreclk 0>;
-                                status = "disabled";
-                        };
-
-                        devbus-cs2@10418 {
-                                compatible = "marvell,mvebu-devbus";
-                                reg = <0x10418 0x8>;
-                                #address-cells = <1>;
-                                #size-cells = <1>;
-                                clocks = <&coreclk 0>;
-                                status = "disabled";
-                        };
-
-                        devbus-cs3@10420 {
-                                compatible = "marvell,mvebu-devbus";
-                                reg = <0x10420 0x8>;
-                                #address-cells = <1>;
-                                #size-cells = <1>;
-                                clocks = <&coreclk 0>;
-                                status = "disabled";
-                        };
                 };
         };
  };
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index fa3dfc6b4c6a..e134d7a90c9a 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -15,7 +15,7 @@
  * common to all Armada SoCs.
  */
 
-/include/ "armada-370-xp.dtsi"
+#include "armada-370-xp.dtsi"
 /include/ "skeleton.dtsi"
 
 / {
@@ -29,8 +29,66 @@
         };
 
         soc {
-                ranges = <0          0xd0000000 0x0100000 /* internal registers */
-                          0xe0000000 0xe0000000 0x8100000 /* PCIe */>;
+                compatible = "marvell,armada370-mbus", "simple-bus";
+
+                bootrom {
+                        compatible = "marvell,bootrom";
+                        reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
+                };
+
+                pcie-controller {
+                        compatible = "marvell,armada-370-pcie";
+                        status = "disabled";
+                        device_type = "pci";
+
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+
+                        bus-range = <0x00 0xff>;
+
+                        ranges =
+                               <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
+                                0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
+                                0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0       1 0 /* Port 0.0 MEM */
+                                0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0       1 0 /* Port 0.0 IO  */
+                                0x82000000 0x2 0     MBUS_ID(0x08, 0xe8) 0       1 0 /* Port 1.0 MEM */
+                                0x81000000 0x2 0     MBUS_ID(0x08, 0xe0) 0       1 0 /* Port 1.0 IO  */>;
+
+                        pcie@1,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
+                                reg = <0x0800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
+                                          0x81000000 0 0 0x81000000 0x1 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 58>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 5>;
+                                status = "disabled";
+                        };
+
+                        pcie@2,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
+                                reg = <0x1000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
+                                          0x81000000 0 0 0x81000000 0x2 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 62>;
+                                marvell,pcie-port = <1>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 9>;
+                                status = "disabled";
+                        };
+                };
+
                 internal-regs {
                         system-controller@18200 {
                                 compatible = "marvell,armada-370-xp-system-controller";
@@ -78,7 +136,7 @@
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
-                                #interrupts-cells = <2>;
+                                #interrupt-cells = <2>;
                                 interrupts = <82>, <83>, <84>, <85>;
                         };
 
@@ -89,7 +147,7 @@
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
-                                #interrupts-cells = <2>;
+                                #interrupt-cells = <2>;
                                 interrupts = <87>, <88>, <89>, <90>;
                         };
 
@@ -100,10 +158,15 @@
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
-                                #interrupts-cells = <2>;
+                                #interrupt-cells = <2>;
                                 interrupts = <91>;
                         };
 
+                        timer@20300 {
+                                compatible = "marvell,armada-370-timer";
+                                clocks = <&coreclk 2>;
+                        };
+
                         coreclk: mvebu-sar@18230 {
                                 compatible = "marvell,armada-370-core-clock";
                                 reg = <0x18230 0x08>;
@@ -169,54 +232,6 @@
                                         0x18304 0x4>;
                                 status = "okay";
                         };
-
-                        pcie-controller {
-                                compatible = "marvell,armada-370-pcie";
-                                status = "disabled";
-                                device_type = "pci";
-
-                                #address-cells = <3>;
-                                #size-cells = <2>;
-
-                                bus-range = <0x00 0xff>;
-
-                                ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000   /* Port 0.0 registers */
-                                        0x82000000 0 0x80000 0x80000 0 0x00002000   /* Port 1.0 registers */
-                                        0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
-                                        0x81000000 0 0          0xe8000000 0 0x00100000>; /* downstream I/O */
-
-                                pcie@1,0 {
-                                        device_type = "pci";
-                                        assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
-                                        reg = <0x0800 0 0 0 0>;
-                                        #address-cells = <3>;
-                                        #size-cells = <2>;
-                                        #interrupt-cells = <1>;
-                                        ranges;
-                                        interrupt-map-mask = <0 0 0 0>;
-                                        interrupt-map = <0 0 0 0 &mpic 58>;
-                                        marvell,pcie-port = <0>;
-                                        marvell,pcie-lane = <0>;
-                                        clocks = <&gateclk 5>;
-                                        status = "disabled";
-                                };
-
-                                pcie@2,0 {
-                                        device_type = "pci";
-                                        assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
-                                        reg = <0x1000 0 0 0 0>;
-                                        #address-cells = <3>;
-                                        #size-cells = <2>;
-                                        #interrupt-cells = <1>;
-                                        ranges;
-                                        interrupt-map-mask = <0 0 0 0>;
-                                        interrupt-map = <0 0 0 0 &mpic 62>;
-                                        marvell,pcie-port = <1>;
-                                        marvell,pcie-lane = <0>;
-                                        clocks = <&gateclk 9>;
-                                        status = "disabled";
-                                };
-                        };
                 };
         };
 };
diff --git a/arch/arm/boot/dts/armada-xp-axpwifiap.dts b/arch/arm/boot/dts/armada-xp-axpwifiap.dts
new file mode 100644
index 000000000000..c5fe57269f5a
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-axpwifiap.dts
@@ -0,0 +1,164 @@
+/*
+ * Device Tree file for Marvell RD-AXPWiFiAP.
+ *
+ * Note: this board is shipped with a new generation boot loader that
+ * remaps internal registers at 0xf1000000. Therefore, if earlyprintk
+ * is used, the CONFIG_DEBUG_MVEBU_UART_ALTERNATE option should be
+ * used.
+ *
+ * Copyright (C) 2013 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+#include "armada-xp-mv78230.dtsi"
+
+/ {
+        model = "Marvell RD-AXPWiFiAP";
+        compatible = "marvell,rd-axpwifiap", "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
+
+        chosen {
+                bootargs = "console=ttyS0,115200 earlyprintk";
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x00000000 0x00000000 0x40000000>; /* 1GB */
+        };
+
+        soc {
+                ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
+                          MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
+
+                pcie-controller {
+                        status = "okay";
+
+                        /* First mini-PCIe port */
+                        pcie@1,0 {
+                                /* Port 0, Lane 0 */
+                                status = "okay";
+                        };
+
+                        /* Second mini-PCIe port */
+                        pcie@2,0 {
+                                /* Port 0, Lane 1 */
+                                status = "okay";
+                        };
+
+                        /* Renesas uPD720202 USB 3.0 controller */
+                        pcie@3,0 {
+                                /* Port 0, Lane 3 */
+                                status = "okay";
+                        };
+                };
+
+                internal-regs {
+                        pinctrl {
+                                pinctrl-0 = <&pmx_phy_int>;
+                                pinctrl-names = "default";
+
+                                pmx_ge0: pmx-ge0 {
+                                        marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3",
+                                                       "mpp4", "mpp5", "mpp6", "mpp7",
+                                                       "mpp8", "mpp9", "mpp10", "mpp11";
+                                        marvell,function = "ge0";
+                                };
+
+                                pmx_ge1: pmx-ge1 {
+                                        marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15",
+                                                       "mpp16", "mpp17", "mpp18", "mpp19",
+                                                       "mpp20", "mpp21", "mpp22", "mpp23";
+                                        marvell,function = "ge1";
+                                };
+
+                                pmx_keys: pmx-keys {
+                                        marvell,pins = "mpp33";
+                                        marvell,function = "gpio";
+                                };
+
+                                pmx_spi: pmx-spi {
+                                        marvell,pins = "mpp36", "mpp37", "mpp38", "mpp39";
+                                        marvell,function = "spi";
+                                };
+
+                                pmx_phy_int: pmx-phy-int {
+                                        marvell,pins = "mpp32";
+                                        marvell,function = "gpio";
+                                };
+                        };
+
+                        serial@12000 {
+                                clock-frequency = <250000000>;
+                                status = "okay";
+                        };
+
+                        serial@12100 {
+                                clock-frequency = <250000000>;
+                                status = "okay";
+                        };
+
+                        sata@a0000 {
+                                nr-ports = <1>;
+                                status = "okay";
+                        };
+
+                        mdio {
+                                phy0: ethernet-phy@0 {
+                                        reg = <0>;
+                                };
+
+                                phy1: ethernet-phy@1 {
+                                        reg = <1>;
+                                };
+                        };
+
+                        ethernet@70000 {
+                                pinctrl-0 = <&pmx_ge0>;
+                                pinctrl-names = "default";
+                                status = "okay";
+                                phy = <&phy0>;
+                                phy-mode = "rgmii-id";
+                        };
+                        ethernet@74000 {
+                                pinctrl-0 = <&pmx_ge1>;
+                                pinctrl-names = "default";
+                                status = "okay";
+                                phy = <&phy1>;
+                                phy-mode = "rgmii-id";
+                        };
+
+                        spi0: spi@10600 {
+                                status = "okay";
+                                pinctrl-0 = <&pmx_spi>;
+                                pinctrl-names = "default";
+
+                                spi-flash@0 {
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+                                        compatible = "n25q128a13";
+                                        reg = <0>; /* Chip select 0 */
+                                        spi-max-frequency = <108000000>;
+                                };
+                        };
+                };
+        };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-0 = <&pmx_keys>;
+                pinctrl-names = "default";
+
+                button@1 {
+                        label = "Factory Reset Button";
+                        linux,code = <141>; /* KEY_SETUP */
+                        gpios = <&gpio1 1 1>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index e28e68ff864d..bcf6d79a57ec 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -14,7 +14,7 @@
  */
 
 /dts-v1/;
-/include/ "armada-xp-mv78460.dtsi"
+#include "armada-xp-mv78460.dtsi"
 
 / {
         model = "Marvell Armada XP Evaluation Board";
@@ -30,9 +30,70 @@
         };
 
         soc {
-                ranges = <0          0 0xd0000000 0x100000      /* Internal registers 1MiB */
-                          0xe0000000 0 0xe0000000 0x8100000     /* PCIe */
-                          0xf0000000 0 0xf0000000 0x1000000>;   /* Device Bus, NOR 16MiB   */
+                ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
+                          MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
+                          MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
+
+                devbus-bootcs {
+                        status = "okay";
+
+                        /* Device Bus parameters are required */
+
+                        /* Read parameters */
+                        devbus,bus-width    = <8>;
+                        devbus,turn-off-ps  = <60000>;
+                        devbus,badr-skew-ps = <0>;
+                        devbus,acc-first-ps = <124000>;
+                        devbus,acc-next-ps  = <248000>;
+                        devbus,rd-setup-ps  = <0>;
+                        devbus,rd-hold-ps   = <0>;
+
+                        /* Write parameters */
+                        devbus,sync-enable = <0>;
+                        devbus,wr-high-ps  = <60000>;
+                        devbus,wr-low-ps   = <60000>;
+                        devbus,ale-wr-ps   = <60000>;
+
+                        /* NOR 16 MiB */
+                        nor@0 {
+                                compatible = "cfi-flash";
+                                reg = <0 0x1000000>;
+                                bank-width = <2>;
+                        };
+                };
+
+                pcie-controller {
+                        status = "okay";
+
+                        /*
+                         * All 6 slots are physically present as
+                         * standard PCIe slots on the board.
+                         */
+                        pcie@1,0 {
+                                /* Port 0, Lane 0 */
+                                status = "okay";
+                        };
+                        pcie@2,0 {
+                                /* Port 0, Lane 1 */
+                                status = "okay";
+                        };
+                        pcie@3,0 {
+                                /* Port 0, Lane 2 */
+                                status = "okay";
+                        };
+                        pcie@4,0 {
+                                /* Port 0, Lane 3 */
+                                status = "okay";
+                        };
+                        pcie@9,0 {
+                                /* Port 2, Lane 0 */
+                                status = "okay";
+                        };
+                        pcie@10,0 {
+                                /* Port 3, Lane 0 */
+                                status = "okay";
+                        };
+                };
 
                 internal-regs {
                         serial@12000 {
@@ -127,68 +188,6 @@
                                         spi-max-frequency = <20000000>;
                                 };
                         };
-
-                        pcie-controller {
-                                status = "okay";
-
-                                /*
-                                 * All 6 slots are physically present as
-                                 * standard PCIe slots on the board.
-                                 */
-                                pcie@1,0 {
-                                        /* Port 0, Lane 0 */
-                                        status = "okay";
-                                };
-                                pcie@2,0 {
-                                        /* Port 0, Lane 1 */
-                                        status = "okay";
-                                };
-                                pcie@3,0 {
-                                        /* Port 0, Lane 2 */
-                                        status = "okay";
-                                };
-                                pcie@4,0 {
-                                        /* Port 0, Lane 3 */
-                                        status = "okay";
-                                };
-                                pcie@9,0 {
-                                        /* Port 2, Lane 0 */
-                                        status = "okay";
-                                };
-                                pcie@10,0 {
-                                        /* Port 3, Lane 0 */
-                                        status = "okay";
-                                };
-                        };
-
-                        devbus-bootcs@10400 {
-                                status = "okay";
-                                ranges = <0 0xf0000000 0x1000000>;
-
-                                /* Device Bus parameters are required */
-
-                                /* Read parameters */
-                                devbus,bus-width    = <8>;
-                                devbus,turn-off-ps  = <60000>;
-                                devbus,badr-skew-ps = <0>;
-                                devbus,acc-first-ps = <124000>;
-                                devbus,acc-next-ps  = <248000>;
-                                devbus,rd-setup-ps  = <0>;
-                                devbus,rd-hold-ps   = <0>;
-
-                                /* Write parameters */
-                                devbus,sync-enable = <0>;
-                                devbus,wr-high-ps  = <60000>;
-                                devbus,wr-low-ps   = <60000>;
-                                devbus,ale-wr-ps   = <60000>;
-
-                                /* NOR 16 MiB */
-                                nor@0 {
-                                        compatible = "cfi-flash";
-                                        reg = <0 0x1000000>;
-                                        bank-width = <2>;
-                                };
-                        };
                 };
         };
 };
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
index c87b2de29c30..2298e4a910e2 100644
--- a/arch/arm/boot/dts/armada-xp-gp.dts
+++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -14,7 +14,7 @@
  */
 
 /dts-v1/;
-/include/ "armada-xp-mv78460.dtsi"
+#include "armada-xp-mv78460.dtsi"
 
 / {
         model = "Marvell Armada XP Development Board DB-MV784MP-GP";
@@ -39,9 +39,58 @@
         };
 
         soc {
-                ranges = <0          0 0xd0000000 0x100000  /* Internal registers 1MiB */
-                          0xe0000000 0 0xe0000000 0x8100000 /* PCIe */
-                          0xf0000000 0 0xf0000000 0x1000000 /* Device Bus, NOR 16MiB  */>;
+                ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
+                          MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
+                          MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
+
+                devbus-bootcs {
+                        status = "okay";
+
+                        /* Device Bus parameters are required */
+
+                        /* Read parameters */
+                        devbus,bus-width    = <8>;
+                        devbus,turn-off-ps  = <60000>;
+                        devbus,badr-skew-ps = <0>;
+                        devbus,acc-first-ps = <124000>;
+                        devbus,acc-next-ps  = <248000>;
+                        devbus,rd-setup-ps  = <0>;
+                        devbus,rd-hold-ps   = <0>;
+
+                        /* Write parameters */
+                        devbus,sync-enable = <0>;
+                        devbus,wr-high-ps  = <60000>;
+                        devbus,wr-low-ps   = <60000>;
+                        devbus,ale-wr-ps   = <60000>;
+
+                        /* NOR 16 MiB */
+                        nor@0 {
+                                compatible = "cfi-flash";
+                                reg = <0 0x1000000>;
+                                bank-width = <2>;
+                        };
+                };
+
+                pcie-controller {
+                        status = "okay";
+
+                        /*
+                         * The 3 slots are physically present as
+                         * standard PCIe slots on the board.
+                         */
+                        pcie@1,0 {
+                                /* Port 0, Lane 0 */
+                                status = "okay";
+                        };
+                        pcie@9,0 {
+                                /* Port 2, Lane 0 */
+                                status = "okay";
+                        };
+                        pcie@10,0 {
+                                /* Port 3, Lane 0 */
+                                status = "okay";
+                        };
+                };
 
                 internal-regs {
                         serial@12000 {
@@ -126,56 +175,6 @@
                                         spi-max-frequency = <108000000>;
                                 };
                         };
-
-                        devbus-bootcs@10400 {
-                                status = "okay";
-                                ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf000000, size 0x1000000 */
-
-                                /* Device Bus parameters are required */
-
-                                /* Read parameters */
-                                devbus,bus-width    = <8>;
-                                devbus,turn-off-ps  = <60000>;
-                                devbus,badr-skew-ps = <0>;
-                                devbus,acc-first-ps = <124000>;
-                                devbus,acc-next-ps  = <248000>;
-                                devbus,rd-setup-ps  = <0>;
-                                devbus,rd-hold-ps   = <0>;
-
-                                /* Write parameters */
-                                devbus,sync-enable = <0>;
-                                devbus,wr-high-ps  = <60000>;
-                                devbus,wr-low-ps   = <60000>;
-                                devbus,ale-wr-ps   = <60000>;
-
-                                /* NOR 16 MiB */
-                                nor@0 {
-                                        compatible = "cfi-flash";
-                                        reg = <0 0x1000000>;
-                                        bank-width = <2>;
-                                };
-                        };
-
-                        pcie-controller {
-                                status = "okay";
-
-                                /*
-                                 * The 3 slots are physically present as
-                                 * standard PCIe slots on the board.
-                                 */
-                                pcie@1,0 {
-                                        /* Port 0, Lane 0 */
-                                        status = "okay";
-                                };
-                                pcie@9,0 {
-                                        /* Port 2, Lane 0 */
-                                        status = "okay";
-                                };
-                                pcie@10,0 {
-                                        /* Port 3, Lane 0 */
-                                        status = "okay";
-                                };
-                        };
                 };
         };
 };
diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
index f8eaa383e07f..0358a33cba48 100644
--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
@@ -13,7 +13,7 @@
  * common to all Armada XP SoCs.
  */
 
-/include/ "armada-xp.dtsi"
+#include "armada-xp.dtsi"
 
 / {
         model = "Marvell Armada XP MV78230 SoC";
@@ -44,6 +44,124 @@
         };
 
         soc {
+                /*
+                 * MV78230 has 2 PCIe units Gen2.0: One unit can be
+                 * configured as x4 or quad x1 lanes. One unit is
+                 * x4/x1.
+                 */
+                pcie-controller {
+                        compatible = "marvell,armada-xp-pcie";
+                        status = "disabled";
+                        device_type = "pci";
+
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+
+                        bus-range = <0x00 0xff>;
+
+                        ranges =
+                               <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000   /* Port 0.0 registers */
+                                0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000   /* Port 2.0 registers */
+                                0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000   /* Port 0.1 registers */
+                                0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000   /* Port 0.2 registers */
+                                0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000   /* Port 0.3 registers */
+                                0x82000000 0x1 0       MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
+                                0x81000000 0x1 0       MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO  */
+                                0x82000000 0x2 0       MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
+                                0x81000000 0x2 0       MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO  */
+                                0x82000000 0x3 0       MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
+                                0x81000000 0x3 0       MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO  */
+                                0x82000000 0x4 0       MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
+                                0x81000000 0x4 0       MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO  */
+                                0x82000000 0x9 0       MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
+                                0x81000000 0x9 0       MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO  */>;
+
+                        pcie@1,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
+                                reg = <0x0800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
+                                          0x81000000 0 0 0x81000000 0x1 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 58>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 5>;
+                                status = "disabled";
+                        };
+
+                        pcie@2,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
+                                reg = <0x1000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
+                                          0x81000000 0 0 0x81000000 0x2 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 59>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <1>;
+                                clocks = <&gateclk 6>;
+                                status = "disabled";
+                        };
+
+                        pcie@3,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
+                                reg = <0x1800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
+                                          0x81000000 0 0 0x81000000 0x3 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 60>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <2>;
+                                clocks = <&gateclk 7>;
+                                status = "disabled";
+                        };
+
+                        pcie@4,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
+                                reg = <0x2000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
+                                          0x81000000 0 0 0x81000000 0x4 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 61>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <3>;
+                                clocks = <&gateclk 8>;
+                                status = "disabled";
+                        };
+
+                        pcie@9,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
+                                reg = <0x4800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
+                                          0x81000000 0 0 0x81000000 0x9 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 99>;
+                                marvell,pcie-port = <2>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 26>;
+                                status = "disabled";
+                        };
+                };
+
                 internal-regs {
                         pinctrl {
                                 compatible = "marvell,mv78230-pinctrl";
@@ -63,7 +181,7 @@
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
-                                #interrupts-cells = <2>;
+                                #interrupt-cells = <2>;
                                 interrupts = <82>, <83>, <84>, <85>;
                         };
 
@@ -74,113 +192,9 @@
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
-                                #interrupts-cells = <2>;
+                                #interrupt-cells = <2>;
                                 interrupts = <87>, <88>, <89>;
                         };
-
-                        /*
-                         * MV78230 has 2 PCIe units Gen2.0: One unit can be
-                         * configured as x4 or quad x1 lanes. One unit is
-                         * x4/x1.
-                         */
-                        pcie-controller {
-                                compatible = "marvell,armada-xp-pcie";
-                                status = "disabled";
-                                device_type = "pci";
-
-#address-cells = <3>;
-#size-cells = <2>;
-
-                                bus-range = <0x00 0xff>;
-
-                                ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000   /* Port 0.0 registers */
-                                        0x82000000 0 0x42000 0x42000 0 0x00002000   /* Port 2.0 registers */
-                                        0x82000000 0 0x44000 0x44000 0 0x00002000   /* Port 0.1 registers */
-                                        0x82000000 0 0x48000 0x48000 0 0x00002000   /* Port 0.2 registers */
-                                        0x82000000 0 0x4c000 0x4c000 0 0x00002000   /* Port 0.3 registers */
-                                        0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
-                                        0x81000000 0 0    0xe8000000 0 0x00100000>; /* downstream I/O */
-
-                                pcie@1,0 {
-                                        device_type = "pci";
-                                        assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
-                                        reg = <0x0800 0 0 0 0>;
-                                        #address-cells = <3>;
-                                        #size-cells = <2>;
-                                        #interrupt-cells = <1>;
-                                        ranges;
-                                        interrupt-map-mask = <0 0 0 0>;
-                                        interrupt-map = <0 0 0 0 &mpic 58>;
-                                        marvell,pcie-port = <0>;
-                                        marvell,pcie-lane = <0>;
-                                        clocks = <&gateclk 5>;
-                                        status = "disabled";
-                                };
-
-                                pcie@2,0 {
-                                        device_type = "pci";
-                                        assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
-                                        reg = <0x1000 0 0 0 0>;
-                                        #address-cells = <3>;
-                                        #size-cells = <2>;
-                                        #interrupt-cells = <1>;
-                                        ranges;
-                                        interrupt-map-mask = <0 0 0 0>;
-                                        interrupt-map = <0 0 0 0 &mpic 59>;
-                                        marvell,pcie-port = <0>;
-                                        marvell,pcie-lane = <1>;
-                                        clocks = <&gateclk 6>;
-                                        status = "disabled";
-                                };
-
-                                pcie@3,0 {
-                                        device_type = "pci";
-                                        assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
-                                        reg = <0x1800 0 0 0 0>;
-                                        #address-cells = <3>;
-                                        #size-cells = <2>;
-                                        #interrupt-cells = <1>;
-                                        ranges;
-                                        interrupt-map-mask = <0 0 0 0>;
-                                        interrupt-map = <0 0 0 0 &mpic 60>;
-                                        marvell,pcie-port = <0>;
-                                        marvell,pcie-lane = <2>;
-                                        clocks = <&gateclk 7>;
-                                        status = "disabled";
-                                };
-
-                                pcie@4,0 {
-                                        device_type = "pci";
-                                        assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
-                                        reg = <0x2000 0 0 0 0>;
-                                        #address-cells = <3>;
-                                        #size-cells = <2>;
-                                        #interrupt-cells = <1>;
-                                        ranges;
-                                        interrupt-map-mask = <0 0 0 0>;
-                                        interrupt-map = <0 0 0 0 &mpic 61>;
-                                        marvell,pcie-port = <0>;
-                                        marvell,pcie-lane = <3>;
-                                        clocks = <&gateclk 8>;
-                                        status = "disabled";
-                                };
-
-                                pcie@9,0 {
-                                        device_type = "pci";
-                                        assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
-                                        reg = <0x4800 0 0 0 0>;
-                                        #address-cells = <3>;
-                                        #size-cells = <2>;
-                                        #interrupt-cells = <1>;
-                                        ranges;
-                                        interrupt-map-mask = <0 0 0 0>;
-                                        interrupt-map = <0 0 0 0 &mpic 99>;
-                                        marvell,pcie-port = <2>;
-                                        marvell,pcie-lane = <0>;
-                                        clocks = <&gateclk 26>;
-                                        status = "disabled";
-                                };
-                        };
                 };
         };
 };
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
index 2d9335da210c..0e82c5062243 100644
--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -13,7 +13,7 @@
  * common to all Armada XP SoCs.
  */
 
-/include/ "armada-xp.dtsi"
+#include "armada-xp.dtsi"
 
 / {
         model = "Marvell Armada XP MV78260 SoC";
@@ -45,6 +45,145 @@
         };
 
         soc {
+                /*
+                 * MV78260 has 3 PCIe units Gen2.0: Two units can be
+                 * configured as x4 or quad x1 lanes. One unit is
+                 * x4/x1.
+                 */
+                pcie-controller {
+                        compatible = "marvell,armada-xp-pcie";
+                        status = "disabled";
+                        device_type = "pci";
+
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+
+                        bus-range = <0x00 0xff>;
+
+                        ranges =
+                               <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000   /* Port 0.0 registers */
+                                0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000   /* Port 2.0 registers */
+                                0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000   /* Port 0.1 registers */
+                                0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000   /* Port 0.2 registers */
+                                0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000   /* Port 0.3 registers */
+                                0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000   /* Port 1.0 registers */
+                                0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000   /* Port 3.0 registers */
+                                0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
+                                0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO  */
+                                0x82000000 0x2 0     MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
+                                0x81000000 0x2 0     MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO  */
+                                0x82000000 0x3 0     MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
+                                0x81000000 0x3 0     MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO  */
+                                0x82000000 0x4 0     MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
+                                0x81000000 0x4 0     MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO  */
+                                0x82000000 0x9 0     MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
+                                0x81000000 0x9 0     MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO  */
+                                0x82000000 0xa 0     MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
+                                0x81000000 0xa 0     MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO  */>;
+
+                        pcie@1,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
+                                reg = <0x0800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
+                                          0x81000000 0 0 0x81000000 0x1 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 58>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 5>;
+                                status = "disabled";
+                        };
+
+                        pcie@2,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
+                                reg = <0x1000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
+                                          0x81000000 0 0 0x81000000 0x2 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 59>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <1>;
+                                clocks = <&gateclk 6>;
+                                status = "disabled";
+                        };
+
+                        pcie@3,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
+                                reg = <0x1800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
+                                          0x81000000 0 0 0x81000000 0x3 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 60>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <2>;
+                                clocks = <&gateclk 7>;
+                                status = "disabled";
+                        };
+
+                        pcie@4,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
+                                reg = <0x2000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
+                                          0x81000000 0 0 0x81000000 0x4 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 61>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <3>;
+                                clocks = <&gateclk 8>;
+                                status = "disabled";
+                        };
+
+                        pcie@9,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
+                                reg = <0x4800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
+                                          0x81000000 0 0 0x81000000 0x9 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 99>;
+                                marvell,pcie-port = <2>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 26>;
+                                status = "disabled";
+                        };
+
+                        pcie@10,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0x82000 0 0x2000>;
+                                reg = <0x5000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
+                                          0x81000000 0 0 0x81000000 0xa 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 103>;
+                                marvell,pcie-port = <3>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 27>;
+                                status = "disabled";
+                        };
+                };
+
                 internal-regs {
                         pinctrl {
                                 compatible = "marvell,mv78260-pinctrl";
@@ -64,7 +203,7 @@
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
-                                #interrupts-cells = <2>;
+                                #interrupt-cells = <2>;
                                 interrupts = <82>, <83>, <84>, <85>;
                         };
 
@@ -75,7 +214,7 @@
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
-                                #interrupts-cells = <2>;
+                                #interrupt-cells = <2>;
                                 interrupts = <87>, <88>, <89>, <90>;
                         };
 
@@ -86,7 +225,7 @@
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
-                                #interrupts-cells = <2>;
+                                #interrupt-cells = <2>;
                                 interrupts = <91>;
                         };
 
@@ -97,128 +236,6 @@
                                 clocks = <&gateclk 1>;
                                 status = "disabled";
                         };
-
-                        /*
-                         * MV78260 has 3 PCIe units Gen2.0: Two units can be
-                         * configured as x4 or quad x1 lanes. One unit is
-                         * x4/x1.
-                         */
-                        pcie-controller {
-                                compatible = "marvell,armada-xp-pcie";
-                                status = "disabled";
-                                device_type = "pci";
-
-                                #address-cells = <3>;
-                                #size-cells = <2>;
-
-                                bus-range = <0x00 0xff>;
-
-                                ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000   /* Port 0.0 registers */
-                                        0x82000000 0 0x42000 0x42000 0 0x00002000   /* Port 2.0 registers */
-                                        0x82000000 0 0x44000 0x44000 0 0x00002000   /* Port 0.1 registers */
-                                        0x82000000 0 0x48000 0x48000 0 0x00002000   /* Port 0.2 registers */
-                                        0x82000000 0 0x4c000 0x4c000 0 0x00002000   /* Port 0.3 registers */
-                                        0x82000000 0 0x80000 0x80000 0 0x00002000   /* Port 1.0 registers */
-                                        0x82000000 0 0x82000 0x82000 0 0x00002000   /* Port 3.0 registers */
-                                        0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
-                                        0x81000000 0 0    0xe8000000 0 0x00100000>; /* downstream I/O */
-
-                                pcie@1,0 {
-                                        device_type = "pci";
-                                        assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
-                                        reg = <0x0800 0 0 0 0>;
-                                        #address-cells = <3>;
-                                        #size-cells = <2>;
-                                        #interrupt-cells = <1>;
-                                        ranges;
-                                        interrupt-map-mask = <0 0 0 0>;
-                                        interrupt-map = <0 0 0 0 &mpic 58>;
-                                        marvell,pcie-port = <0>;
-                                        marvell,pcie-lane = <0>;
-                                        clocks = <&gateclk 5>;
-                                        status = "disabled";
-                                };
-
-                                pcie@2,0 {
-                                        device_type = "pci";
-                                        assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
-                                        reg = <0x1000 0 0 0 0>;
-                                        #address-cells = <3>;
-                                        #size-cells = <2>;
-                                        #interrupt-cells = <1>;
-                                        ranges;
-                                        interrupt-map-mask = <0 0 0 0>;
-                                        interrupt-map = <0 0 0 0 &mpic 59>;
-                                        marvell,pcie-port = <0>;
-                                        marvell,pcie-lane = <1>;
-                                        clocks = <&gateclk 6>;
-                                        status = "disabled";
-                                };
-
-                                pcie@3,0 {
-                                        device_type = "pci";
-                                        assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
-                                        reg = <0x1800 0 0 0 0>;
-                                        #address-cells = <3>;
-                                        #size-cells = <2>;
-                                        #interrupt-cells = <1>;
-                                        ranges;
-                                        interrupt-map-mask = <0 0 0 0>;
-                                        interrupt-map = <0 0 0 0 &mpic 60>;
-                                        marvell,pcie-port = <0>;
-                                        marvell,pcie-lane = <2>;
-                                        clocks = <&gateclk 7>;
-                                        status = "disabled";
-                                };
-
-                                pcie@4,0 {
-                                        device_type = "pci";
-                                        assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
-                                        reg = <0x2000 0 0 0 0>;
-                                        #address-cells = <3>;
-                                        #size-cells = <2>;
-                                        #interrupt-cells = <1>;
-                                        ranges;
-                                        interrupt-map-mask = <0 0 0 0>;
-                                        interrupt-map = <0 0 0 0 &mpic 61>;
-                                        marvell,pcie-port = <0>;
-                                        marvell,pcie-lane = <3>;
-                                        clocks = <&gateclk 8>;
-                                        status = "disabled";
-                                };
-
-                                pcie@9,0 {
-                                        device_type = "pci";
-                                        assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
-                                        reg = <0x4800 0 0 0 0>;
-                                        #address-cells = <3>;
-                                        #size-cells = <2>;
-                                        #interrupt-cells = <1>;
-                                        ranges;
-                                        interrupt-map-mask = <0 0 0 0>;
-                                        interrupt-map = <0 0 0 0 &mpic 99>;
-                                        marvell,pcie-port = <2>;
-                                        marvell,pcie-lane = <0>;
-                                        clocks = <&gateclk 26>;
-                                        status = "disabled";
-                                };
-
-                                pcie@10,0 {
-                                        device_type = "pci";
-                                        assigned-addresses = <0x82000800 0 0x82000 0 0x2000>;
-                                        reg = <0x5000 0 0 0 0>;
-                                        #address-cells = <3>;
-                                        #size-cells = <2>;
-                                        #interrupt-cells = <1>;
-                                        ranges;
-                                        interrupt-map-mask = <0 0 0 0>;
-                                        interrupt-map = <0 0 0 0 &mpic 103>;
-                                        marvell,pcie-port = <3>;
-                                        marvell,pcie-lane = <0>;
-                                        clocks = <&gateclk 27>;
-                                        status = "disabled";
-                                };
-                        };
                 };
         };
 };
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
index c7b1f4d5c1c7..e82c1b80af17 100644
--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -13,7 +13,7 @@
  * common to all Armada XP SoCs.
  */
 
-/include/ "armada-xp.dtsi"
+#include "armada-xp.dtsi"
 
 / {
         model = "Marvell Armada XP MV78460 SoC";
@@ -61,6 +61,227 @@
         };
 
         soc {
+                /*
+                 * MV78460 has 4 PCIe units Gen2.0: Two units can be
+                 * configured as x4 or quad x1 lanes. Two units are
+                 * x4/x1.
+                 */
+                pcie-controller {
+                        compatible = "marvell,armada-xp-pcie";
+                        status = "disabled";
+                        device_type = "pci";
+
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+
+                        bus-range = <0x00 0xff>;
+
+                        ranges =
+                               <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000   /* Port 0.0 registers */
+                                0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000   /* Port 2.0 registers */
+                                0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000   /* Port 0.1 registers */
+                                0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000   /* Port 0.2 registers */
+                                0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000   /* Port 0.3 registers */
+                                0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000   /* Port 1.0 registers */
+                                0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000   /* Port 3.0 registers */
+                                0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000   /* Port 1.1 registers */
+                                0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000   /* Port 1.2 registers */
+                                0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000   /* Port 1.3 registers */
+                                0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
+                                0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO  */
+                                0x82000000 0x2 0     MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
+                                0x81000000 0x2 0     MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO  */
+                                0x82000000 0x3 0     MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
+                                0x81000000 0x3 0     MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO  */
+                                0x82000000 0x4 0     MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
+                                0x81000000 0x4 0     MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO  */
+
+                                0x82000000 0x5 0     MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
+                                0x81000000 0x5 0     MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO  */
+                                0x82000000 0x6 0     MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
+                                0x81000000 0x6 0     MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO  */
+                                0x82000000 0x7 0     MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
+                                0x81000000 0x7 0     MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO  */
+                                0x82000000 0x8 0     MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
+                                0x81000000 0x8 0     MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO  */
+
+                                0x82000000 0x9 0     MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
+                                0x81000000 0x9 0     MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO  */
+
+                                0x82000000 0xa 0     MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
+                                0x81000000 0xa 0     MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO  */>;
+
+                        pcie@1,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
+                                reg = <0x0800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
+                                          0x81000000 0 0 0x81000000 0x1 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 58>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 5>;
+                                status = "disabled";
+                        };
+
+                        pcie@2,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
+                                reg = <0x1000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
+                                          0x81000000 0 0 0x81000000 0x2 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 59>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <1>;
+                                clocks = <&gateclk 6>;
+                                status = "disabled";
+                        };
+
+                        pcie@3,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
+                                reg = <0x1800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
+                                          0x81000000 0 0 0x81000000 0x3 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 60>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <2>;
+                                clocks = <&gateclk 7>;
+                                status = "disabled";
+                        };
+
+                        pcie@4,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
+                                reg = <0x2000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
+                                          0x81000000 0 0 0x81000000 0x4 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 61>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <3>;
+                                clocks = <&gateclk 8>;
+                                status = "disabled";
+                        };
+
+                        pcie@5,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
+                                reg = <0x2800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
+                                          0x81000000 0 0 0x81000000 0x5 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 62>;
+                                marvell,pcie-port = <1>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 9>;
+                                status = "disabled";
+                        };
+
+                        pcie@6,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
+                                reg = <0x3000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
+                                          0x81000000 0 0 0x81000000 0x6 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 63>;
+                                marvell,pcie-port = <1>;
+                                marvell,pcie-lane = <1>;
+                                clocks = <&gateclk 10>;
+                                status = "disabled";
+                        };
+
+                        pcie@7,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
+                                reg = <0x3800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
+                                          0x81000000 0 0 0x81000000 0x7 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 64>;
+                                marvell,pcie-port = <1>;
+                                marvell,pcie-lane = <2>;
+                                clocks = <&gateclk 11>;
+                                status = "disabled";
+                        };
+
+                        pcie@8,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
+                                reg = <0x4000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
+                                          0x81000000 0 0 0x81000000 0x8 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 65>;
+                                marvell,pcie-port = <1>;
+                                marvell,pcie-lane = <3>;
+                                clocks = <&gateclk 12>;
+                                status = "disabled";
+                        };
+
+                        pcie@9,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
+                                reg = <0x4800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
+                                          0x81000000 0 0 0x81000000 0x9 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 99>;
+                                marvell,pcie-port = <2>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 26>;
+                                status = "disabled";
+                        };
+
+                        pcie@10,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
+                                reg = <0x5000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
+                                          0x81000000 0 0 0x81000000 0xa 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &mpic 103>;
+                                marvell,pcie-port = <3>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gateclk 27>;
+                                status = "disabled";
+                        };
+                };
+
                 internal-regs {
                         pinctrl {
                                 compatible = "marvell,mv78460-pinctrl";
@@ -80,7 +301,7 @@
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
-                                #interrupts-cells = <2>;
+                                #interrupt-cells = <2>;
                                 interrupts = <82>, <83>, <84>, <85>;
                         };
 
@@ -91,7 +312,7 @@
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
-                                #interrupts-cells = <2>;
+                                #interrupt-cells = <2>;
                                 interrupts = <87>, <88>, <89>, <90>;
                         };
 
@@ -102,7 +323,7 @@
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
-                                #interrupts-cells = <2>;
+                                #interrupt-cells = <2>;
                                 interrupts = <91>;
                         };
 
@@ -113,194 +334,6 @@
                                 clocks = <&gateclk 1>;
                                 status = "disabled";
                         };
-
-                        /*
-                         * MV78460 has 4 PCIe units Gen2.0: Two units can be
-                         * configured as x4 or quad x1 lanes. Two units are
-                         * x4/x1.
-                         */
-                        pcie-controller {
-                                compatible = "marvell,armada-xp-pcie";
-                                status = "disabled";
-                                device_type = "pci";
-
-                                #address-cells = <3>;
-                                #size-cells = <2>;
-
-                                bus-range = <0x00 0xff>;
-
-                                ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000   /* Port 0.0 registers */
-                                        0x82000000 0 0x42000 0x42000 0 0x00002000   /* Port 2.0 registers */
-                                        0x82000000 0 0x44000 0x44000 0 0x00002000   /* Port 0.1 registers */
-                                        0x82000000 0 0x48000 0x48000 0 0x00002000   /* Port 0.2 registers */
-                                        0x82000000 0 0x4c000 0x4c000 0 0x00002000   /* Port 0.3 registers */
-                                        0x82000000 0 0x80000 0x80000 0 0x00002000   /* Port 1.0 registers */
-                                        0x82000000 0 0x82000 0x82000 0 0x00002000   /* Port 3.0 registers */
-                                        0x82000000 0 0x84000 0x84000 0 0x00002000   /* Port 1.1 registers */
-                                        0x82000000 0 0x88000 0x88000 0 0x00002000   /* Port 1.2 registers */
-                                        0x82000000 0 0x8c000 0x8c000 0 0x00002000   /* Port 1.3 registers */
-                                        0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
-                                        0x81000000 0 0    0xe8000000 0 0x00100000>; /* downstream I/O */
-
-                                pcie@1,0 {
-                                        device_type = "pci";
-                                        assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
-                                        reg = <0x0800 0 0 0 0>;
-                                        #address-cells = <3>;
-                                        #size-cells = <2>;
-                                        #interrupt-cells = <1>;
-                                        ranges;
-                                        interrupt-map-mask = <0 0 0 0>;
-                                        interrupt-map = <0 0 0 0 &mpic 58>;
-                                        marvell,pcie-port = <0>;
-                                        marvell,pcie-lane = <0>;
-                                        clocks = <&gateclk 5>;
-                                        status = "disabled";
-                                };
-
-                                pcie@2,0 {
-                                        device_type = "pci";
-                                        assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
-                                        reg = <0x1000 0 0 0 0>;
-                                        #address-cells = <3>;
-                                        #size-cells = <2>;
-                                        #interrupt-cells = <1>;
-                                        ranges;
-                                        interrupt-map-mask = <0 0 0 0>;
-                                        interrupt-map = <0 0 0 0 &mpic 59>;
-                                        marvell,pcie-port = <0>;
-                                        marvell,pcie-lane = <1>;
-                                        clocks = <&gateclk 6>;
-                                        status = "disabled";
-                                };
-
-                                pcie@3,0 {
-                                        device_type = "pci";
-                                        assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
-                                        reg = <0x1800 0 0 0 0>;
-                                        #address-cells = <3>;
-                                        #size-cells = <2>;
-                                        #interrupt-cells = <1>;
-                                        ranges;
-                                        interrupt-map-mask = <0 0 0 0>;
-                                        interrupt-map = <0 0 0 0 &mpic 60>;
-                                        marvell,pcie-port = <0>;
-                                        marvell,pcie-lane = <2>;
-                                        clocks = <&gateclk 7>;
-                                        status = "disabled";
-                                };
-
-                                pcie@4,0 {
-                                        device_type = "pci";
-                                        assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
-                                        reg = <0x2000 0 0 0 0>;
-                                        #address-cells = <3>;
-                                        #size-cells = <2>;
-                                        #interrupt-cells = <1>;
-                                        ranges;
-                                        interrupt-map-mask = <0 0 0 0>;
-                                        interrupt-map = <0 0 0 0 &mpic 61>;
-                                        marvell,pcie-port = <0>;
-                                        marvell,pcie-lane = <3>;
-                                        clocks = <&gateclk 8>;
-                                        status = "disabled";
-                                };
-
-                                pcie@5,0 {
-                                        device_type = "pci";
-                                        assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
-                                        reg = <0x2800 0 0 0 0>;
-                                        #address-cells = <3>;
-                                        #size-cells = <2>;
-                                        #interrupt-cells = <1>;
-                                        ranges;
-                                        interrupt-map-mask = <0 0 0 0>;
-                                        interrupt-map = <0 0 0 0 &mpic 62>;
-                                        marvell,pcie-port = <1>;
-                                        marvell,pcie-lane = <0>;
-                                        clocks = <&gateclk 9>;
-                                        status = "disabled";
-                                };
-
-                                pcie@6,0 {
-                                        device_type = "pci";
-                                        assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
-                                        reg = <0x3000 0 0 0 0>;
-                                        #address-cells = <3>;
-                                        #size-cells = <2>;
-                                        #interrupt-cells = <1>;
-                                        ranges;
-                                        interrupt-map-mask = <0 0 0 0>;
-                                        interrupt-map = <0 0 0 0 &mpic 63>;
-                                        marvell,pcie-port = <1>;
-                                        marvell,pcie-lane = <1>;
-                                        clocks = <&gateclk 10>;
-                                        status = "disabled";
-                                };
-
-                                pcie@7,0 {
-                                        device_type = "pci";
-                                        assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
-                                        reg = <0x3800 0 0 0 0>;
-                                        #address-cells = <3>;
-                                        #size-cells = <2>;
-                                        #interrupt-cells = <1>;
-                                        ranges;
-                                        interrupt-map-mask = <0 0 0 0>;
-                                        interrupt-map = <0 0 0 0 &mpic 64>;
-                                        marvell,pcie-port = <1>;
-                                        marvell,pcie-lane = <2>;
-                                        clocks = <&gateclk 11>;
-                                        status = "disabled";
-                                };
-
-                                pcie@8,0 {
-                                        device_type = "pci";
-                                        assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
-                                        reg = <0x4000 0 0 0 0>;
-                                        #address-cells = <3>;
-                                        #size-cells = <2>;
-                                        #interrupt-cells = <1>;
-                                        ranges;
-                                        interrupt-map-mask = <0 0 0 0>;
-                                        interrupt-map = <0 0 0 0 &mpic 65>;
-                                        marvell,pcie-port = <1>;
-                                        marvell,pcie-lane = <3>;
-                                        clocks = <&gateclk 12>;
-                                        status = "disabled";
-                                };
-                                pcie@9,0 {
-                                        device_type = "pci";
-                                        assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
-                                        reg = <0x4800 0 0 0 0>;
-                                        #address-cells = <3>;
-                                        #size-cells = <2>;
-                                        #interrupt-cells = <1>;
-                                        ranges;
-                                        interrupt-map-mask = <0 0 0 0>;
-                                        interrupt-map = <0 0 0 0 &mpic 99>;
-                                        marvell,pcie-port = <2>;
-                                        marvell,pcie-lane = <0>;
-                                        clocks = <&gateclk 26>;
-                                        status = "disabled";
-                                };
-
-                                pcie@10,0 {
-                                        device_type = "pci";
-                                        assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
-                                        reg = <0x5000 0 0 0 0>;
-                                        #address-cells = <3>;
-                                        #size-cells = <2>;
-                                        #interrupt-cells = <1>;
-                                        ranges;
-                                        interrupt-map-mask = <0 0 0 0>;
-                                        interrupt-map = <0 0 0 0 &mpic 103>;
-                                        marvell,pcie-port = <3>;
-                                        marvell,pcie-lane = <0>;
-                                        clocks = <&gateclk 27>;
-                                        status = "disabled";
-                                };
-                        };
                 };
         };
 };
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
index 8f510458ea86..5695afcc04bf 100644
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -11,7 +11,7 @@
  */
 
 /dts-v1/;
-/include/ "armada-xp-mv78260.dtsi"
+#include "armada-xp-mv78260.dtsi"
 
 / {
         model = "PlatHome OpenBlocks AX3-4 board";
@@ -27,9 +27,46 @@
         };
 
         soc {
-                ranges = <0          0 0xd0000000 0x100000      /* Internal registers 1MiB */
-                          0xe0000000 0 0xe0000000 0x8100000     /* PCIe */
-                          0xf0000000 0 0xf0000000 0x8000000     /* Device Bus, NOR 128MiB   */>;
+                ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
+                          MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
+                          MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x8000000>;
+
+                devbus-bootcs {
+                        status = "okay";
+
+                        /* Device Bus parameters are required */
+
+                        /* Read parameters */
+                        devbus,bus-width    = <8>;
+                        devbus,turn-off-ps  = <60000>;
+                        devbus,badr-skew-ps = <0>;
+                        devbus,acc-first-ps = <124000>;
+                        devbus,acc-next-ps  = <248000>;
+                        devbus,rd-setup-ps  = <0>;
+                        devbus,rd-hold-ps   = <0>;
+
+                        /* Write parameters */
+                        devbus,sync-enable = <0>;
+                        devbus,wr-high-ps  = <60000>;
+                        devbus,wr-low-ps   = <60000>;
+                        devbus,ale-wr-ps   = <60000>;
+
+                        /* NOR 128 MiB */
+                        nor@0 {
+                                compatible = "cfi-flash";
+                                reg = <0 0x8000000>;
+                                bank-width = <2>;
+                        };
+                };
+
+                pcie-controller {
+                        status = "okay";
+                        /* Internal mini-PCIe connector */
+                        pcie@1,0 {
+                                /* Port 0, Lane 0 */
+                                status = "okay";
+                        };
+                };
 
                 internal-regs {
                         serial@12000 {
@@ -148,49 +185,6 @@
                         usb@51000 {
                                 status = "okay";
                         };
-
-                        /* USB interface in the mini-PCIe connector */
-                        usb@52000 {
-                                status = "okay";
-                        };
-
-                        devbus-bootcs@10400 {
-                                status = "okay";
-                                ranges = <0 0xf0000000 0x8000000>; /* @addr 0xf000000, size 0x8000000 */
-
-                                /* Device Bus parameters are required */
-
-                                /* Read parameters */
-                                devbus,bus-width    = <8>;
-                                devbus,turn-off-ps  = <60000>;
-                                devbus,badr-skew-ps = <0>;
-                                devbus,acc-first-ps = <124000>;
-                                devbus,acc-next-ps  = <248000>;
-                                devbus,rd-setup-ps  = <0>;
-                                devbus,rd-hold-ps   = <0>;
-
-                                /* Write parameters */
-                                devbus,sync-enable = <0>;
-                                devbus,wr-high-ps  = <60000>;
-                                devbus,wr-low-ps   = <60000>;
-                                devbus,ale-wr-ps   = <60000>;
-
-                                /* NOR 128 MiB */
-                                nor@0 {
-                                        compatible = "cfi-flash";
-                                        reg = <0 0x8000000>;
-                                        bank-width = <2>;
-                                };
-                        };
-
-                        pcie-controller {
-                                status = "okay";
-                                /* Internal mini-PCIe connector */
-                                pcie@1,0 {
-                                        /* Port 0, Lane 0 */
-                                        status = "okay";
-                                };
-                        };
                 };
         };
 };
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index 416eb9481844..def125c0eeaa 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -16,7 +16,7 @@
  * common to all Armada SoCs.
  */
 
-/include/ "armada-370-xp.dtsi"
+#include "armada-370-xp.dtsi"
 
 / {
         model = "Marvell Armada XP family SoC";
@@ -27,6 +27,13 @@
         };
 
         soc {
+                compatible = "marvell,armadaxp-mbus", "simple-bus";
+
+                bootrom {
+                        compatible = "marvell,bootrom";
+                        reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
+                };
+
                 internal-regs {
                         L2: l2-cache {
                                 compatible = "marvell,aurora-system-cache";
@@ -62,7 +69,7 @@
                         };
 
                         timer@20300 {
-                                marvell,timer-25Mhz;
+                                compatible = "marvell,armada-xp-timer";
                         };
 
                         coreclk: mvebu-sar@18230 {
diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts
index 5bce7cc55cf3..588ce58a2959 100644
--- a/arch/arm/boot/dts/da850-evm.dts
+++ b/arch/arm/boot/dts/da850-evm.dts
@@ -90,6 +90,17 @@
                                 };
                         };
                 };
+                mdio: mdio@1e24000 {
+                        status = "okay";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mdio_pins>;
+                        bus_freq = <2200000>;
+                };
+                eth0: ethernet@1e20000 {
+                        status = "okay";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mii_pins>;
+                };
         };
         nand_cs3@62000000 {
                 status = "okay";
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index d70ba5504481..8d17346f9702 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -125,11 +125,33 @@
                                         0x14 0x00000010 0x000000f0
                                 >;
                         };
+                        mdio_pins: pinmux_mdio_pins {
+                                pinctrl-single,bits = <
+                                        /* MDIO_CLK, MDIO_D */
+                                        0x10 0x00000088 0x000000ff
+                                >;
+                        };
+                        mii_pins: pinmux_mii_pins {
+                                pinctrl-single,bits = <
+                                        /*
+                                         * MII_TXEN, MII_TXCLK, MII_COL
+                                         * MII_TXD_3, MII_TXD_2, MII_TXD_1
+                                         * MII_TXD_0
+                                         */
+                                        0x8 0x88888880 0xfffffff0
+                                        /*
+                                         * MII_RXER, MII_CRS, MII_RXCLK
+                                         * MII_RXDV, MII_RXD_3, MII_RXD_2
+                                         * MII_RXD_1, MII_RXD_0
+                                         */
+                                        0xc 0x88888888 0xffffffff
+                                >;
+                        };
+
                 };
                 serial0: serial@1c42000 {
                         compatible = "ns16550a";
                         reg = <0x42000 0x100>;
-                        clock-frequency = <150000000>;
                         reg-shift = <2>;
                         interrupts = <25>;
                         status = "disabled";
@@ -137,7 +159,6 @@
                 serial1: serial@1d0c000 {
                         compatible = "ns16550a";
                         reg = <0x10c000 0x100>;
-                        clock-frequency = <150000000>;
                         reg-shift = <2>;
                         interrupts = <53>;
                         status = "disabled";
@@ -145,7 +166,6 @@
                 serial2: serial@1d0d000 {
                         compatible = "ns16550a";
                         reg = <0x10d000 0x100>;
-                        clock-frequency = <150000000>;
                         reg-shift = <2>;
                         interrupts = <61>;
                         status = "disabled";
@@ -216,6 +236,26 @@
                         interrupts = <56>;
                         status = "disabled";
                 };
+                mdio: mdio@1e24000 {
+                        compatible = "ti,davinci_mdio";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x224000 0x1000>;
+                };
+                eth0: ethernet@1e20000 {
+                        compatible = "ti,davinci-dm6467-emac";
+                        reg = <0x220000 0x4000>;
+                        ti,davinci-ctrl-reg-offset = <0x3000>;
+                        ti,davinci-ctrl-mod-reg-offset = <0x2000>;
+                        ti,davinci-ctrl-ram-offset = <0>;
+                        ti,davinci-ctrl-ram-size = <0x2000>;
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        interrupts = <33
+                                        34
+                                        35
+                                        36
+                                        >;
+                };
         };
         nand_cs3@62000000 {
                 compatible = "ti,davinci-nand";
diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
index 701153992c69..737ed5da8f71 100644
--- a/arch/arm/boot/dts/imx25.dtsi
+++ b/arch/arm/boot/dts/imx25.dtsi
@@ -13,19 +13,35 @@
 
 / {
         aliases {
+                gpio0 = &gpio1;
+                gpio1 = &gpio2;
+                gpio2 = &gpio3;
+                gpio3 = &gpio4;
+                i2c0 = &i2c1;
+                i2c1 = &i2c2;
+                i2c2 = &i2c3;
                 serial0 = &uart1;
                 serial1 = &uart2;
                 serial2 = &uart3;
                 serial3 = &uart4;
                 serial4 = &uart5;
-                gpio0 = &gpio1;
-                gpio1 = &gpio2;
-                gpio2 = &gpio3;
-                gpio3 = &gpio4;
+                spi0 = &spi1;
+                spi1 = &spi2;
+                spi2 = &spi3;
                 usb0 = &usbotg;
                 usb1 = &usbhost1;
         };
 
+        cpus {
+                #address-cells = <0>;
+                #size-cells = <0>;
+
+                cpu {
+                        compatible = "arm,arm926ej-s";
+                        device_type = "cpu";
+                };
+        };
+
         asic: asic-interrupt-controller@68000000 {
                 compatible = "fsl,imx25-asic", "fsl,avic";
                 interrupt-controller;
@@ -377,7 +393,8 @@
                                 status = "disabled";
                         };
 
-                        lcdc@53fbc000 {
+                        lcdc: lcdc@53fbc000 {
+                                compatible = "fsl,imx25-fb", "fsl,imx21-fb";
                                 reg = <0x53fbc000 0x4000>;
                                 interrupts = <39>;
                                 clocks = <&clks 103>, <&clks 66>, <&clks 49>;
@@ -424,6 +441,7 @@
                                 reg = <0x53fd4000 0x4000>;
                                 clocks = <&clks 112>, <&clks 68>;
                                 clock-names = "ipg", "ahb";
+                                #dma-cells = <3>;
                                 interrupts = <34>;
                         };
 
@@ -444,6 +462,13 @@
                                 interrupts = <26>;
                         };
 
+                        iim: iim@53ff0000 {
+                                compatible = "fsl,imx25-iim", "fsl,imx27-iim";
+                                reg = <0x53ff0000 0x4000>;
+                                interrupts = <19>;
+                                clocks = <&clks 99>;
+                        };
+
                         usbphy1: usbphy@1 {
                                 compatible = "nop-usbphy";
                                 status = "disabled";
diff --git a/arch/arm/boot/dts/imx27-apf27dev.dts b/arch/arm/boot/dts/imx27-apf27dev.dts
index 66b8e1c1b0be..2a377ca1881a 100644
--- a/arch/arm/boot/dts/imx27-apf27dev.dts
+++ b/arch/arm/boot/dts/imx27-apf27dev.dts
@@ -53,6 +53,11 @@
 &i2c1 {
         clock-frequency = <400000>;
         status = "okay";
+
+        rtc@68 {
+                compatible = "dallas,ds1374";
+                reg = <0x68>;
+        };
 };
 
 &i2c2 {
diff --git a/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts
new file mode 100644
index 000000000000..5a31c776513f
--- /dev/null
+++ b/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts
@@ -0,0 +1,93 @@
+/*
+ * Copyright 2012 Markus Pargmann, Pengutronix
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include "imx27-phytec-phycard-s-som.dts"
+
+/ {
+        model = "Phytec pca100 rapid development kit";
+        compatible = "phytec,imx27-pca100-rdk", "phytec,imx27-pca100", "fsl,imx27";
+
+        display: display {
+                model = "Primeview-PD050VL1";
+                native-mode = <&timing0>;
+                bits-per-pixel = <16>;  /* non-standard but required */
+                fsl,pcr = <0xf0c88080>; /* non-standard but required */
+                display-timings {
+                        timing0: 640x480 {
+                                hactive = <640>;
+                                vactive = <480>;
+                                hback-porch = <112>;
+                                hfront-porch = <36>;
+                                hsync-len = <32>;
+                                vback-porch = <33>;
+                                vfront-porch = <33>;
+                                vsync-len = <2>;
+                                clock-frequency = <25000000>;
+                        };
+                };
+        };
+
+        regulators {
+                compatible = "simple-bus";
+
+                reg_3v3: 3v3 {
+                        compatible = "regulator-fixed";
+                        regulator-name = "3V3";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                };
+        };
+};
+
+&fb {
+        display = <&display>;
+        status = "okay";
+};
+
+&i2c1 {
+        status = "okay";
+
+        rtc@51 {
+                compatible = "nxp,pcf8563";
+                reg = <0x51>;
+        };
+
+        adc@64 {
+                compatible = "maxim,max1037";
+                vcc-supply = <&reg_3v3>;
+                reg = <0x64>;
+        };
+};
+
+&owire {
+        status = "okay";
+};
+
+&sdhci2 {
+        cd-gpios = <&gpio3 29 0>;
+        status = "okay";
+};
+
+&uart1 {
+        fsl,uart-has-rtscts;
+        status = "okay";
+};
+
+&uart2 {
+        fsl,uart-has-rtscts;
+        status = "okay";
+};
+
+&uart3 {
+        fsl,uart-has-rtscts;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts b/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts
new file mode 100644
index 000000000000..c8d57d1d0743
--- /dev/null
+++ b/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts
@@ -0,0 +1,44 @@
+/*
+ * Copyright 2012 Sascha Hauer, Uwe Kleine-König, Steffen Trumtrar
+ * and Markus Pargmann, Pengutronix
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+#include "imx27.dtsi"
+
+/ {
+        model = "Phytec pca100";
+        compatible = "phytec,imx27-pca100", "fsl,imx27";
+
+        memory {
+                reg = <0xa0000000 0x08000000>; /* 128MB */
+        };
+};
+
+&cspi1 {
+        fsl,spi-num-chipselects = <2>;
+        cs-gpios = <&gpio4 28 0>,
+                <&gpio4 27 0>;
+        status = "okay";
+};
+
+&fec {
+        status = "okay";
+};
+
+&i2c2 {
+        status = "okay";
+
+        at24@52 {
+                compatible = "at,24c32";
+                pagesize = <32>;
+                reg = <0x52>;
+        };
+};
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
index e7ed9786920a..0fc6551786c6 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
@@ -35,3 +35,16 @@
         fsl,uart-has-rtscts;
         status = "okay";
 };
+
+&weim {
+        can@d4000000 {
+                compatible = "nxp,sja1000";
+                reg = <4 0x00000000 0x00000100>;
+                interrupt-parent = <&gpio5>;
+                interrupts = <19 0x2>;
+                nxp,external-clock-frequency = <16000000>;
+                nxp,tx-output-config = <0x16>;
+                nxp,no-comparator-bypass;
+                fsl,weim-cs-timing = <0x0000dcf6 0x444a0301 0x44443302>;
+        };
+};
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-som.dts b/arch/arm/boot/dts/imx27-phytec-phycore-som.dts
index f0105651869d..4ec402c38945 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore-som.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycore-som.dts
@@ -17,49 +17,22 @@
         compatible = "phytec,imx27-pcm038", "fsl,imx27";
 
         memory {
-                reg = <0x0 0x0>;
+                reg = <0xa0000000 0x08000000>;
         };
+};
 
-        soc {
-                aipi@10000000 { /* aipi1 */
-                        serial@1000a000 {
-                                status = "okay";
-                        };
-
-                        i2c@1001d000 {
-                                clock-frequency = <400000>;
-                                status = "okay";
-                                at24@52 {
-                                        compatible = "at,24c32";
-                                        pagesize = <32>;
-                                        reg = <0x52>;
-                                };
-                                pcf8563@51 {
-                                        compatible = "nxp,pcf8563";
-                                        reg = <0x51>;
-                                };
-                                lm75@4a {
-                                        compatible = "national,lm75";
-                                        reg = <0x4a>;
-                                };
-                        };
-                };
+&audmux {
+        status = "okay";
 
-                aipi@10020000 { /* aipi2 */
-                        ethernet@1002b000 {
-                                phy-reset-gpios = <&gpio3 30 0>;
-                                status = "okay";
-                        };
-                };
+        /* SSI0 <=> PINS_4 (MC13783 Audio) */
+        ssi0 {
+                fsl,audmux-port = <0>;
+                fsl,port-config = <0xcb205000>;
         };
 
-        nor_flash@c0000000 {
-                compatible = "cfi-flash";
-                bank-width = <2>;
-                reg = <0xc0000000 0x02000000>;
-                linux,mtd-name = "physmap-flash.0";
-                #address-cells = <1>;
-                #size-cells = <1>;
+        pins4 {
+                fsl,audmux-port = <2>;
+                fsl,port-config = <0x00001000>;
         };
 };
 
@@ -80,28 +53,16 @@
                 fsl,mc13xxx-uses-rtc;
 
                 regulators {
-                        sw1a_reg: sw1a {
+                        /* SW1A and SW1B joined operation */
+                        sw1_reg: sw1a {
                                 regulator-min-microvolt = <1200000>;
-                                regulator-max-microvolt = <1200000>;
+                                regulator-max-microvolt = <1520000>;
                                 regulator-always-on;
                                 regulator-boot-on;
                         };
 
-                        sw1b_reg: sw1b {
-                                regulator-min-microvolt = <1200000>;
-                                regulator-max-microvolt = <1200000>;
-                                regulator-always-on;
-                                regulator-boot-on;
-                        };
-
-                        sw2a_reg: sw2a {
-                                regulator-min-microvolt = <1800000>;
-                                regulator-max-microvolt = <1800000>;
-                                regulator-always-on;
-                                regulator-boot-on;
-                        };
-
-                        sw2b_reg: sw2b {
+                        /* SW2A and SW2B joined operation */
+                        sw2_reg: sw2a {
                                 regulator-min-microvolt = <1800000>;
                                 regulator-max-microvolt = <1800000>;
                                 regulator-always-on;
@@ -172,8 +133,62 @@
         };
 };
 
+&fec {
+        phy-reset-gpios = <&gpio3 30 0>;
+        status = "okay";
+};
+
+&i2c2 {
+        clock-frequency = <400000>;
+        status = "okay";
+
+        at24@52 {
+                compatible = "at,24c32";
+                pagesize = <32>;
+                reg = <0x52>;
+        };
+
+        pcf8563@51 {
+                compatible = "nxp,pcf8563";
+                reg = <0x51>;
+        };
+
+        lm75@4a {
+                compatible = "national,lm75";
+                reg = <0x4a>;
+        };
+};
+
 &nfc {
         nand-bus-width = <8>;
         nand-ecc-mode = "hw";
         status = "okay";
 };
+
+&uart1 {
+        status = "okay";
+};
+
+&weim {
+        status = "okay";
+
+        nor: nor@c0000000 {
+                compatible = "cfi-flash";
+                reg = <0 0x00000000 0x02000000>;
+                bank-width = <2>;
+                linux,mtd-name = "physmap-flash.0";
+                fsl,weim-cs-timing = <0x22c2cf00 0x75000d01 0x00000900>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+        };
+
+        sram: sram@c8000000 {
+                compatible = "mtd-ram";
+                reg = <1 0x00000000 0x00800000>;
+                bank-width = <2>;
+                linux,mtd-name = "mtd-ram.0";
+                fsl,weim-cs-timing = <0x0000d843 0x22252521 0x22220a00>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+        };
+};
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index 0695264ddf1b..c037c223619a 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -13,25 +13,27 @@
 
 / {
         aliases {
-                serial0 = &uart1;
-                serial1 = &uart2;
-                serial2 = &uart3;
-                serial3 = &uart4;
-                serial4 = &uart5;
-                serial5 = &uart6;
                 gpio0 = &gpio1;
                 gpio1 = &gpio2;
                 gpio2 = &gpio3;
                 gpio3 = &gpio4;
                 gpio4 = &gpio5;
                 gpio5 = &gpio6;
+                i2c0 = &i2c1;
+                i2c1 = &i2c2;
+                serial0 = &uart1;
+                serial1 = &uart2;
+                serial2 = &uart3;
+                serial3 = &uart4;
+                serial4 = &uart5;
+                serial5 = &uart6;
                 spi0 = &cspi1;
                 spi1 = &cspi2;
                 spi2 = &cspi3;
         };
 
-        avic: avic-interrupt-controller@e0000000 {
-                compatible = "fsl,imx27-avic", "fsl,avic";
+        aitc: aitc-interrupt-controller@e0000000 {
+                compatible = "fsl,imx27-aitc", "fsl,avic";
                 interrupt-controller;
                 #interrupt-cells = <1>;
                 reg = <0x10040000 0x1000>;
@@ -47,11 +49,29 @@
                 };
         };
 
+        cpus {
+                #size-cells = <0>;
+                #address-cells = <1>;
+
+                cpu: cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,arm926ej-s";
+                        operating-points = <
+                                /* kHz uV */
+                                266000 1300000
+                                399000 1450000
+                        >;
+                        clock-latency = <62500>;
+                        clocks = <&clks 18>;
+                        voltage-tolerance = <5>;
+                };
+        };
+
         soc {
                 #address-cells = <1>;
                 #size-cells = <1>;
                 compatible = "simple-bus";
-                interrupt-parent = <&avic>;
+                interrupt-parent = <&aitc>;
                 ranges;
 
                 aipi@10000000 { /* AIPI1 */
@@ -75,7 +95,7 @@
                                 compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
                                 reg = <0x10002000 0x1000>;
                                 interrupts = <27>;
-                                clocks = <&clks 0>;
+                                clocks = <&clks 74>;
                         };
 
                         gpt1: timer@10003000 {
@@ -102,7 +122,7 @@
                                 clock-names = "ipg", "per";
                         };
 
-                        pwm0: pwm@10006000 {
+                        pwm: pwm@10006000 {
                                 compatible = "fsl,imx27-pwm";
                                 reg = <0x10006000 0x1000>;
                                 interrupts = <23>;
@@ -110,6 +130,21 @@
                                 clock-names = "ipg", "per";
                         };
 
+                        kpp: kpp@10008000 {
+                                compatible = "fsl,imx27-kpp", "fsl,imx21-kpp";
+                                reg = <0x10008000 0x1000>;
+                                interrupts = <21>;
+                                clocks = <&clks 37>;
+                                status = "disabled";
+                        };
+
+                        owire: owire@10009000 {
+                                compatible = "fsl,imx27-owire", "fsl,imx21-owire";
+                                reg = <0x10009000 0x1000>;
+                                clocks = <&clks 35>;
+                                status = "disabled";
+                        };
+
                         uart1: serial@1000a000 {
                                 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
                                 reg = <0x1000a000 0x1000>;
@@ -260,6 +295,14 @@
                                 #interrupt-cells = <2>;
                         };
 
+                        audmux: audmux@10016000 {
+                                compatible = "fsl,imx27-audmux", "fsl,imx21-audmux";
+                                reg = <0x10016000 0x1000>;
+                                clocks = <&clks 0>;
+                                clock-names = "audmux";
+                                status = "disabled";
+                        };
+
                         cspi3: cspi@10017000 {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
@@ -342,6 +385,15 @@
                         reg = <0x10020000 0x20000>;
                         ranges;
 
+                        fb: fb@10021000 {
+                                compatible = "fsl,imx27-fb", "fsl,imx21-fb";
+                                interrupts = <61>;
+                                reg = <0x10021000 0x1000>;
+                                clocks = <&clks 36>, <&clks 65>, <&clks 59>;
+                                clock-names = "ipg", "ahb", "per";
+                                status = "disabled";
+                        };
+
                         coda: coda@10023000 {
                                 compatible = "fsl,imx27-vpu";
                                 reg = <0x10023000 0x0200>;
@@ -351,27 +403,37 @@
                                 iram = <&iram>;
                         };
 
+                        sahara2: sahara@10025000 {
+                                compatible = "fsl,imx27-sahara";
+                                reg = <0x10025000 0x1000>;
+                                interrupts = <59>;
+                                clocks = <&clks 32>, <&clks 64>;
+                                clock-names = "ipg", "ahb";
+                        };
+
                         clks: ccm@10027000{
                                 compatible = "fsl,imx27-ccm";
                                 reg = <0x10027000 0x1000>;
                                 #clock-cells = <1>;
                         };
 
+                        iim: iim@10028000 {
+                                compatible = "fsl,imx27-iim";
+                                reg = <0x10028000 0x1000>;
+                                interrupts = <62>;
+                                clocks = <&clks 38>;
+                        };
+
                         fec: ethernet@1002b000 {
                                 compatible = "fsl,imx27-fec";
                                 reg = <0x1002b000 0x4000>;
                                 interrupts = <50>;
-                                clocks = <&clks 48>, <&clks 67>, <&clks 0>;
-                                clock-names = "ipg", "ahb", "ptp";
+                                clocks = <&clks 48>, <&clks 67>;
+                                clock-names = "ipg", "ahb";
                                 status = "disabled";
                         };
                 };
 
-                iram: iram@ffff4c00 {
-                        compatible = "mmio-sram";
-                        reg = <0xffff4c00 0xb400>;
-                };
-
                 nfc: nand@d8000000 {
                         #address-cells = <1>;
                         #size-cells = <1>;
@@ -381,5 +443,27 @@
                         clocks = <&clks 54>;
                         status = "disabled";
                 };
+
+                weim: weim@d8002000 {
+                        #address-cells = <2>;
+                        #size-cells = <1>;
+                        compatible = "fsl,imx27-weim";
+                        reg = <0xd8002000 0x1000>;
+                        clocks = <&clks 0>;
+                        ranges = <
+                                0 0 0xc0000000 0x08000000
+                                1 0 0xc8000000 0x08000000
+                                2 0 0xd0000000 0x02000000
+                                3 0 0xd2000000 0x02000000
+                                4 0 0xd4000000 0x02000000
+                                5 0 0xd6000000 0x02000000
+                        >;
+                        status = "disabled";
+                };
+
+                iram: iram@ffff4c00 {
+                        compatible = "mmio-sram";
+                        reg = <0xffff4c00 0xb400>;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/imx31.dtsi b/arch/arm/boot/dts/imx31.dtsi
index c5449257ad9a..c34f82581248 100644
--- a/arch/arm/boot/dts/imx31.dtsi
+++ b/arch/arm/boot/dts/imx31.dtsi
@@ -20,6 +20,16 @@
                 serial4 = &uart5;
         };
 
+        cpus {
+                #address-cells = <0>;
+                #size-cells = <0>;
+
+                cpu {
+                        compatible = "arm,arm1136";
+                        device_type = "cpu";
+                };
+        };
+
         avic: avic-interrupt-controller@60000000 {
                 compatible = "fsl,imx31-avic", "fsl,avic";
                 interrupt-controller;
@@ -94,6 +104,13 @@
                                 status = "disabled";
                         };
 
+                        iim: iim@5001c000 {
+                                compatible = "fsl,imx31-iim", "fsl,imx27-iim";
+                                reg = <0x5001c000 0x1000>;
+                                interrupts = <19>;
+                                clocks = <&clks 25>;
+                        };
+
                         clks: ccm@53f80000{
                                 compatible = "fsl,imx31-ccm";
                                 reg = <0x53f80000 0x4000>;
diff --git a/arch/arm/boot/dts/imx51-apf51.dts b/arch/arm/boot/dts/imx51-apf51.dts
index 8f7f9ac0b989..b3606993f2e8 100644
--- a/arch/arm/boot/dts/imx51-apf51.dts
+++ b/arch/arm/boot/dts/imx51-apf51.dts
@@ -26,10 +26,6 @@
         };
 
         clocks {
-                ckih1 {
-                        clock-frequency = <0>;
-                };
-
                 osc {
                         clock-frequency = <33554432>;
                 };
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index ad3471ca17c7..1d337d99ecd5 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -63,6 +63,10 @@
         };
 
         clocks {
+                ckih1 {
+                        clock-frequency = <22579200>;
+                };
+
                 clk_26M: codec_clock {
                         compatible = "fixed-clock";
                         reg=<0>;
@@ -108,6 +112,7 @@
                 #size-cells = <0>;
                 compatible = "fsl,mc13892";
                 spi-max-frequency = <6000000>;
+                spi-cs-high;
                 reg = <0>;
                 interrupt-parent = <&gpio1>;
                 interrupts = <8 0x4>;
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index 25764b505a61..a85abb424c34 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -15,13 +15,18 @@
 
 / {
         aliases {
-                serial0 = &uart1;
-                serial1 = &uart2;
-                serial2 = &uart3;
                 gpio0 = &gpio1;
                 gpio1 = &gpio2;
                 gpio2 = &gpio3;
                 gpio3 = &gpio4;
+                i2c0 = &i2c1;
+                i2c1 = &i2c2;
+                serial0 = &uart1;
+                serial1 = &uart2;
+                serial2 = &uart3;
+                spi0 = &ecspi1;
+                spi1 = &ecspi2;
+                spi2 = &cspi;
         };
 
         tzic: tz-interrupt-controller@e0000000 {
@@ -42,7 +47,7 @@
 
                 ckih1 {
                         compatible = "fsl,imx-ckih1", "fixed-clock";
-                        clock-frequency = <22579200>;
+                        clock-frequency = <0>;
                 };
 
                 ckih2 {
@@ -149,6 +154,9 @@
                                         reg = <0x70014000 0x4000>;
                                         interrupts = <30>;
                                         clocks = <&clks 49>;
+                                        dmas = <&sdma 24 1 0>,
+                                               <&sdma 25 1 0>;
+                                        dma-names = "rx", "tx";
                                         fsl,fifo-depth = <15>;
                                         fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
                                         status = "disabled";
@@ -300,275 +308,6 @@
                         iomuxc: iomuxc@73fa8000 {
                                 compatible = "fsl,imx51-iomuxc";
                                 reg = <0x73fa8000 0x4000>;
-
-                                audmux {
-                                        pinctrl_audmux_1: audmuxgrp-1 {
-                                                fsl,pins = <
-                                                        MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
-                                                        MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
-                                                        MX51_PAD_AUD3_BB_CK__AUD3_TXC  0x80000000
-                                                        MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
-                                                >;
-                                        };
-                                };
-
-                                fec {
-                                        pinctrl_fec_1: fecgrp-1 {
-                                                fsl,pins = <
-                                                        MX51_PAD_EIM_EB2__FEC_MDIO         0x80000000
-                                                        MX51_PAD_EIM_EB3__FEC_RDATA1       0x80000000
-                                                        MX51_PAD_EIM_CS2__FEC_RDATA2       0x80000000
-                                                        MX51_PAD_EIM_CS3__FEC_RDATA3       0x80000000
-                                                        MX51_PAD_EIM_CS4__FEC_RX_ER        0x80000000
-                                                        MX51_PAD_EIM_CS5__FEC_CRS          0x80000000
-                                                        MX51_PAD_NANDF_RB2__FEC_COL        0x80000000
-                                                        MX51_PAD_NANDF_RB3__FEC_RX_CLK     0x80000000
-                                                        MX51_PAD_NANDF_D9__FEC_RDATA0      0x80000000
-                                                        MX51_PAD_NANDF_D8__FEC_TDATA0      0x80000000
-                                                        MX51_PAD_NANDF_CS2__FEC_TX_ER      0x80000000
-                                                        MX51_PAD_NANDF_CS3__FEC_MDC        0x80000000
-                                                        MX51_PAD_NANDF_CS4__FEC_TDATA1     0x80000000
-                                                        MX51_PAD_NANDF_CS5__FEC_TDATA2     0x80000000
-                                                        MX51_PAD_NANDF_CS6__FEC_TDATA3     0x80000000
-                                                        MX51_PAD_NANDF_CS7__FEC_TX_EN      0x80000000
-                                                        MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000
-                                                >;
-                                        };
-
-                                        pinctrl_fec_2: fecgrp-2 {
-                                                fsl,pins = <
-                                                        MX51_PAD_DI_GP3__FEC_TX_ER        0x80000000
-                                                        MX51_PAD_DI2_PIN4__FEC_CRS        0x80000000
-                                                        MX51_PAD_DI2_PIN2__FEC_MDC        0x80000000
-                                                        MX51_PAD_DI2_PIN3__FEC_MDIO       0x80000000
-                                                        MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
-                                                        MX51_PAD_DI_GP4__FEC_RDATA2       0x80000000
-                                                        MX51_PAD_DISP2_DAT0__FEC_RDATA3   0x80000000
-                                                        MX51_PAD_DISP2_DAT1__FEC_RX_ER    0x80000000
-                                                        MX51_PAD_DISP2_DAT6__FEC_TDATA1   0x80000000
-                                                        MX51_PAD_DISP2_DAT7__FEC_TDATA2   0x80000000
-                                                        MX51_PAD_DISP2_DAT8__FEC_TDATA3   0x80000000
-                                                        MX51_PAD_DISP2_DAT9__FEC_TX_EN    0x80000000
-                                                        MX51_PAD_DISP2_DAT10__FEC_COL     0x80000000
-                                                        MX51_PAD_DISP2_DAT11__FEC_RX_CLK  0x80000000
-                                                        MX51_PAD_DISP2_DAT12__FEC_RX_DV   0x80000000
-                                                        MX51_PAD_DISP2_DAT13__FEC_TX_CLK  0x80000000
-                                                        MX51_PAD_DISP2_DAT14__FEC_RDATA0  0x80000000
-                                                        MX51_PAD_DISP2_DAT15__FEC_TDATA0  0x80000000
-                                                >;
-                                        };
-                                };
-
-                                ecspi1 {
-                                        pinctrl_ecspi1_1: ecspi1grp-1 {
-                                                fsl,pins = <
-                                                        MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
-                                                        MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
-                                                        MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
-                                                >;
-                                        };
-                                };
-
-                                ecspi2 {
-                                        pinctrl_ecspi2_1: ecspi2grp-1 {
-                                                fsl,pins = <
-                                                        MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185
-                                                        MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185
-                                                        MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185
-                                                >;
-                                        };
-                                };
-
-                                esdhc1 {
-                                        pinctrl_esdhc1_1: esdhc1grp-1 {
-                                                fsl,pins = <
-                                                        MX51_PAD_SD1_CMD__SD1_CMD     0x400020d5
-                                                        MX51_PAD_SD1_CLK__SD1_CLK     0x20d5
-                                                        MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
-                                                        MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
-                                                        MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
-                                                        MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
-                                                >;
-                                        };
-                                };
-
-                                esdhc2 {
-                                        pinctrl_esdhc2_1: esdhc2grp-1 {
-                                                fsl,pins = <
-                                                        MX51_PAD_SD2_CMD__SD2_CMD     0x400020d5
-                                                        MX51_PAD_SD2_CLK__SD2_CLK     0x20d5
-                                                        MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
-                                                        MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
-                                                        MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
-                                                        MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
-                                                >;
-                                        };
-                                };
-
-                                i2c2 {
-                                        pinctrl_i2c2_1: i2c2grp-1 {
-                                                fsl,pins = <
-                                                        MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
-                                                        MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
-                                                >;
-                                        };
-
-                                        pinctrl_i2c2_2: i2c2grp-2 {
-                                                fsl,pins = <
-                                                        MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed
-                                                        MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed
-                                                >;
-                                        };
-                                };
-
-                                ipu_disp1 {
-                                        pinctrl_ipu_disp1_1: ipudisp1grp-1 {
-                                                fsl,pins = <
-                                                        MX51_PAD_DISP1_DAT0__DISP1_DAT0   0x5
-                                                        MX51_PAD_DISP1_DAT1__DISP1_DAT1   0x5
-                                                        MX51_PAD_DISP1_DAT2__DISP1_DAT2   0x5
-                                                        MX51_PAD_DISP1_DAT3__DISP1_DAT3   0x5
-                                                        MX51_PAD_DISP1_DAT4__DISP1_DAT4   0x5
-                                                        MX51_PAD_DISP1_DAT5__DISP1_DAT5   0x5
-                                                        MX51_PAD_DISP1_DAT6__DISP1_DAT6   0x5
-                                                        MX51_PAD_DISP1_DAT7__DISP1_DAT7   0x5
-                                                        MX51_PAD_DISP1_DAT8__DISP1_DAT8   0x5
-                                                        MX51_PAD_DISP1_DAT9__DISP1_DAT9   0x5
-                                                        MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
-                                                        MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
-                                                        MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
-                                                        MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
-                                                        MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
-                                                        MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
-                                                        MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
-                                                        MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
-                                                        MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
-                                                        MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
-                                                        MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
-                                                        MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
-                                                        MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
-                                                        MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
-                                                        MX51_PAD_DI1_PIN2__DI1_PIN2       0x5 /* hsync */
-                                                        MX51_PAD_DI1_PIN3__DI1_PIN3       0x5 /* vsync */
-                                                >;
-                                        };
-                                };
-
-                                ipu_disp2 {
-                                        pinctrl_ipu_disp2_1: ipudisp2grp-1 {
-                                                fsl,pins = <
-                                                        MX51_PAD_DISP2_DAT0__DISP2_DAT0     0x5
-                                                        MX51_PAD_DISP2_DAT1__DISP2_DAT1     0x5
-                                                        MX51_PAD_DISP2_DAT2__DISP2_DAT2     0x5
-                                                        MX51_PAD_DISP2_DAT3__DISP2_DAT3     0x5
-                                                        MX51_PAD_DISP2_DAT4__DISP2_DAT4     0x5
-                                                        MX51_PAD_DISP2_DAT5__DISP2_DAT5     0x5
-                                                        MX51_PAD_DISP2_DAT6__DISP2_DAT6     0x5
-                                                        MX51_PAD_DISP2_DAT7__DISP2_DAT7     0x5
-                                                        MX51_PAD_DISP2_DAT8__DISP2_DAT8     0x5
-                                                        MX51_PAD_DISP2_DAT9__DISP2_DAT9     0x5
-                                                        MX51_PAD_DISP2_DAT10__DISP2_DAT10   0x5
-                                                        MX51_PAD_DISP2_DAT11__DISP2_DAT11   0x5
-                                                        MX51_PAD_DISP2_DAT12__DISP2_DAT12   0x5
-                                                        MX51_PAD_DISP2_DAT13__DISP2_DAT13   0x5
-                                                        MX51_PAD_DISP2_DAT14__DISP2_DAT14   0x5
-                                                        MX51_PAD_DISP2_DAT15__DISP2_DAT15   0x5
-                                                        MX51_PAD_DI2_PIN2__DI2_PIN2         0x5 /* hsync */
-                                                        MX51_PAD_DI2_PIN3__DI2_PIN3         0x5 /* vsync */
-                                                        MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5
-                                                        MX51_PAD_DI_GP4__DI2_PIN15          0x5
-                                                >;
-                                        };
-                                };
-
-                                pata {
-                                        pinctrl_pata_1: patagrp-1 {
-                                                fsl,pins = <
-                                                        MX51_PAD_NANDF_WE_B__PATA_DIOW          0x2004
-                                                        MX51_PAD_NANDF_RE_B__PATA_DIOR          0x2004
-                                                        MX51_PAD_NANDF_ALE__PATA_BUFFER_EN      0x2004
-                                                        MX51_PAD_NANDF_CLE__PATA_RESET_B        0x2004
-                                                        MX51_PAD_NANDF_WP_B__PATA_DMACK         0x2004
-                                                        MX51_PAD_NANDF_RB0__PATA_DMARQ          0x2004
-                                                        MX51_PAD_NANDF_RB1__PATA_IORDY          0x2004
-                                                        MX51_PAD_GPIO_NAND__PATA_INTRQ          0x2004
-                                                        MX51_PAD_NANDF_CS2__PATA_CS_0           0x2004
-                                                        MX51_PAD_NANDF_CS3__PATA_CS_1           0x2004
-                                                        MX51_PAD_NANDF_CS4__PATA_DA_0           0x2004
-                                                        MX51_PAD_NANDF_CS5__PATA_DA_1           0x2004
-                                                        MX51_PAD_NANDF_CS6__PATA_DA_2           0x2004
-                                                        MX51_PAD_NANDF_D15__PATA_DATA15         0x2004
-                                                        MX51_PAD_NANDF_D14__PATA_DATA14         0x2004
-                                                        MX51_PAD_NANDF_D13__PATA_DATA13         0x2004
-                                                        MX51_PAD_NANDF_D12__PATA_DATA12         0x2004
-                                                        MX51_PAD_NANDF_D11__PATA_DATA11         0x2004
-                                                        MX51_PAD_NANDF_D10__PATA_DATA10         0x2004
-                                                        MX51_PAD_NANDF_D9__PATA_DATA9           0x2004
-                                                        MX51_PAD_NANDF_D8__PATA_DATA8           0x2004
-                                                        MX51_PAD_NANDF_D7__PATA_DATA7           0x2004
-                                                        MX51_PAD_NANDF_D6__PATA_DATA6           0x2004
-                                                        MX51_PAD_NANDF_D5__PATA_DATA5           0x2004
-                                                        MX51_PAD_NANDF_D4__PATA_DATA4           0x2004
-                                                        MX51_PAD_NANDF_D3__PATA_DATA3           0x2004
-                                                        MX51_PAD_NANDF_D2__PATA_DATA2           0x2004
-                                                        MX51_PAD_NANDF_D1__PATA_DATA1           0x2004
-                                                        MX51_PAD_NANDF_D0__PATA_DATA0           0x2004
-                                                >;
-                                        };
-                                };
-
-                                uart1 {
-                                        pinctrl_uart1_1: uart1grp-1 {
-                                                fsl,pins = <
-                                                        MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
-                                                        MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
-                                                        MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
-                                                        MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
-                                                >;
-                                        };
-                                };
-
-                                uart2 {
-                                        pinctrl_uart2_1: uart2grp-1 {
-                                                fsl,pins = <
-                                                        MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
-                                                        MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
-                                                >;
-                                        };
-                                };
-
-                                uart3 {
-                                        pinctrl_uart3_1: uart3grp-1 {
-                                                fsl,pins = <
-                                                        MX51_PAD_EIM_D25__UART3_RXD 0x1c5
-                                                        MX51_PAD_EIM_D26__UART3_TXD 0x1c5
-                                                        MX51_PAD_EIM_D27__UART3_RTS 0x1c5
-                                                        MX51_PAD_EIM_D24__UART3_CTS 0x1c5
-                                                >;
-                                        };
-
-                                        pinctrl_uart3_2: uart3grp-2 {
-                                                fsl,pins = <
-                                                        MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
-                                                        MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
-                                                >;
-                                        };
-                                };
-
-                                kpp {
-                                        pinctrl_kpp_1: kppgrp-1 {
-                                                fsl,pins = <
-                                                        MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0
-                                                        MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0
-                                                        MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0
-                                                        MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0
-                                                        MX51_PAD_KEY_COL0__KEY_COL0 0xe8
-                                                        MX51_PAD_KEY_COL1__KEY_COL1 0xe8
-                                                        MX51_PAD_KEY_COL2__KEY_COL2 0xe8
-                                                        MX51_PAD_KEY_COL3__KEY_COL3 0xe8
-                                                >;
-                                        };
-                                };
                         };
 
                         pwm1: pwm@73fb4000 {
@@ -628,6 +367,13 @@
                         reg = <0x80000000 0x10000000>;
                         ranges;
 
+                        iim: iim@83f98000 {
+                                compatible = "fsl,imx51-iim", "fsl,imx27-iim";
+                                reg = <0x83f98000 0x4000>;
+                                interrupts = <69>;
+                                clocks = <&clks 107>;
+                        };
+
                         ecspi2: ecspi@83fac000 {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
@@ -645,6 +391,7 @@
                                 interrupts = <6>;
                                 clocks = <&clks 56>, <&clks 56>;
                                 clock-names = "ipg", "ahb";
+                                #dma-cells = <3>;
                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
                         };
 
@@ -684,6 +431,9 @@
                                 reg = <0x83fcc000 0x4000>;
                                 interrupts = <29>;
                                 clocks = <&clks 48>;
+                                dmas = <&sdma 28 0 0>,
+                                       <&sdma 29 0 0>;
+                                dma-names = "rx", "tx";
                                 fsl,fifo-depth = <15>;
                                 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
                                 status = "disabled";
@@ -695,6 +445,23 @@
                                 status = "disabled";
                         };
 
+                        weim: weim@83fda000 {
+                                #address-cells = <2>;
+                                #size-cells = <1>;
+                                compatible = "fsl,imx51-weim";
+                                reg = <0x83fda000 0x1000>;
+                                clocks = <&clks 57>;
+                                ranges = <
+                                        0 0 0xb0000000 0x08000000
+                                        1 0 0xb8000000 0x08000000
+                                        2 0 0xc0000000 0x08000000
+                                        3 0 0xc8000000 0x04000000
+                                        4 0 0xcc000000 0x02000000
+                                        5 0 0xce000000 0x02000000
+                                >;
+                                status = "disabled";
+                        };
+
                         nfc: nand@83fdb000 {
                                 compatible = "fsl,imx51-nand";
                                 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
@@ -716,6 +483,9 @@
                                 reg = <0x83fe8000 0x4000>;
                                 interrupts = <96>;
                                 clocks = <&clks 50>;
+                                dmas = <&sdma 46 0 0>,
+                                       <&sdma 47 0 0>;
+                                dma-names = "rx", "tx";
                                 fsl,fifo-depth = <15>;
                                 fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */
                                 status = "disabled";
@@ -732,3 +502,319 @@
                 };
         };
 };
+
+&iomuxc {
+        audmux {
+                pinctrl_audmux_1: audmuxgrp-1 {
+                        fsl,pins = <
+                                MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
+                                MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
+                                MX51_PAD_AUD3_BB_CK__AUD3_TXC  0x80000000
+                                MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
+                        >;
+                };
+        };
+
+        fec {
+                pinctrl_fec_1: fecgrp-1 {
+                        fsl,pins = <
+                                MX51_PAD_EIM_EB2__FEC_MDIO         0x80000000
+                                MX51_PAD_EIM_EB3__FEC_RDATA1       0x80000000
+                                MX51_PAD_EIM_CS2__FEC_RDATA2       0x80000000
+                                MX51_PAD_EIM_CS3__FEC_RDATA3       0x80000000
+                                MX51_PAD_EIM_CS4__FEC_RX_ER        0x80000000
+                                MX51_PAD_EIM_CS5__FEC_CRS          0x80000000
+                                MX51_PAD_NANDF_RB2__FEC_COL        0x80000000
+                                MX51_PAD_NANDF_RB3__FEC_RX_CLK     0x80000000
+                                MX51_PAD_NANDF_D9__FEC_RDATA0      0x80000000
+                                MX51_PAD_NANDF_D8__FEC_TDATA0      0x80000000
+                                MX51_PAD_NANDF_CS2__FEC_TX_ER      0x80000000
+                                MX51_PAD_NANDF_CS3__FEC_MDC        0x80000000
+                                MX51_PAD_NANDF_CS4__FEC_TDATA1     0x80000000
+                                MX51_PAD_NANDF_CS5__FEC_TDATA2     0x80000000
+                                MX51_PAD_NANDF_CS6__FEC_TDATA3     0x80000000
+                                MX51_PAD_NANDF_CS7__FEC_TX_EN      0x80000000
+                                MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000
+                        >;
+                };
+
+                pinctrl_fec_2: fecgrp-2 {
+                        fsl,pins = <
+                                MX51_PAD_DI_GP3__FEC_TX_ER        0x80000000
+                                MX51_PAD_DI2_PIN4__FEC_CRS        0x80000000
+                                MX51_PAD_DI2_PIN2__FEC_MDC        0x80000000
+                                MX51_PAD_DI2_PIN3__FEC_MDIO       0x80000000
+                                MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
+                                MX51_PAD_DI_GP4__FEC_RDATA2       0x80000000
+                                MX51_PAD_DISP2_DAT0__FEC_RDATA3   0x80000000
+                                MX51_PAD_DISP2_DAT1__FEC_RX_ER    0x80000000
+                                MX51_PAD_DISP2_DAT6__FEC_TDATA1   0x80000000
+                                MX51_PAD_DISP2_DAT7__FEC_TDATA2   0x80000000
+                                MX51_PAD_DISP2_DAT8__FEC_TDATA3   0x80000000
+                                MX51_PAD_DISP2_DAT9__FEC_TX_EN    0x80000000
+                                MX51_PAD_DISP2_DAT10__FEC_COL     0x80000000
+                                MX51_PAD_DISP2_DAT11__FEC_RX_CLK  0x80000000
+                                MX51_PAD_DISP2_DAT12__FEC_RX_DV   0x80000000
+                                MX51_PAD_DISP2_DAT13__FEC_TX_CLK  0x80000000
+                                MX51_PAD_DISP2_DAT14__FEC_RDATA0  0x80000000
+                                MX51_PAD_DISP2_DAT15__FEC_TDATA0  0x80000000
+                        >;
+                };
+        };
+
+        ecspi1 {
+                pinctrl_ecspi1_1: ecspi1grp-1 {
+                        fsl,pins = <
+                                MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
+                                MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
+                                MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
+                        >;
+                };
+        };
+
+        ecspi2 {
+                pinctrl_ecspi2_1: ecspi2grp-1 {
+                        fsl,pins = <
+                                MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185
+                                MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185
+                                MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185
+                        >;
+                };
+        };
+
+        esdhc1 {
+                pinctrl_esdhc1_1: esdhc1grp-1 {
+                        fsl,pins = <
+                                MX51_PAD_SD1_CMD__SD1_CMD     0x400020d5
+                                MX51_PAD_SD1_CLK__SD1_CLK     0x20d5
+                                MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
+                                MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
+                                MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
+                                MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
+                        >;
+                };
+        };
+
+        esdhc2 {
+                pinctrl_esdhc2_1: esdhc2grp-1 {
+                        fsl,pins = <
+                                MX51_PAD_SD2_CMD__SD2_CMD     0x400020d5
+                                MX51_PAD_SD2_CLK__SD2_CLK     0x20d5
+                                MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
+                                MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
+                                MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
+                                MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
+                        >;
+                };
+        };
+
+        i2c2 {
+                pinctrl_i2c2_1: i2c2grp-1 {
+                        fsl,pins = <
+                                MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
+                                MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
+                        >;
+                };
+
+                pinctrl_i2c2_2: i2c2grp-2 {
+                        fsl,pins = <
+                                MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed
+                                MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed
+                        >;
+                };
+
+                pinctrl_i2c2_3: i2c2grp-3 {
+                        fsl,pins = <
+                                MX51_PAD_GPIO1_2__I2C2_SCL 0x400001ed
+                                MX51_PAD_GPIO1_3__I2C2_SDA 0x400001ed
+                        >;
+                };
+        };
+
+        ipu_disp1 {
+                pinctrl_ipu_disp1_1: ipudisp1grp-1 {
+                        fsl,pins = <
+                                MX51_PAD_DISP1_DAT0__DISP1_DAT0   0x5
+                                MX51_PAD_DISP1_DAT1__DISP1_DAT1   0x5
+                                MX51_PAD_DISP1_DAT2__DISP1_DAT2   0x5
+                                MX51_PAD_DISP1_DAT3__DISP1_DAT3   0x5
+                                MX51_PAD_DISP1_DAT4__DISP1_DAT4   0x5
+                                MX51_PAD_DISP1_DAT5__DISP1_DAT5   0x5
+                                MX51_PAD_DISP1_DAT6__DISP1_DAT6   0x5
+                                MX51_PAD_DISP1_DAT7__DISP1_DAT7   0x5
+                                MX51_PAD_DISP1_DAT8__DISP1_DAT8   0x5
+                                MX51_PAD_DISP1_DAT9__DISP1_DAT9   0x5
+                                MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
+                                MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
+                                MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
+                                MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
+                                MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
+                                MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
+                                MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
+                                MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
+                                MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
+                                MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
+                                MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
+                                MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
+                                MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
+                                MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
+                                MX51_PAD_DI1_PIN2__DI1_PIN2       0x5 /* hsync */
+                                MX51_PAD_DI1_PIN3__DI1_PIN3       0x5 /* vsync */
+                        >;
+                };
+        };
+
+        ipu_disp2 {
+                pinctrl_ipu_disp2_1: ipudisp2grp-1 {
+                        fsl,pins = <
+                                MX51_PAD_DISP2_DAT0__DISP2_DAT0     0x5
+                                MX51_PAD_DISP2_DAT1__DISP2_DAT1     0x5
+                                MX51_PAD_DISP2_DAT2__DISP2_DAT2     0x5
+                                MX51_PAD_DISP2_DAT3__DISP2_DAT3     0x5
+                                MX51_PAD_DISP2_DAT4__DISP2_DAT4     0x5
+                                MX51_PAD_DISP2_DAT5__DISP2_DAT5     0x5
+                                MX51_PAD_DISP2_DAT6__DISP2_DAT6     0x5
+                                MX51_PAD_DISP2_DAT7__DISP2_DAT7     0x5
+                                MX51_PAD_DISP2_DAT8__DISP2_DAT8     0x5
+                                MX51_PAD_DISP2_DAT9__DISP2_DAT9     0x5
+                                MX51_PAD_DISP2_DAT10__DISP2_DAT10   0x5
+                                MX51_PAD_DISP2_DAT11__DISP2_DAT11   0x5
+                                MX51_PAD_DISP2_DAT12__DISP2_DAT12   0x5
+                                MX51_PAD_DISP2_DAT13__DISP2_DAT13   0x5
+                                MX51_PAD_DISP2_DAT14__DISP2_DAT14   0x5
+                                MX51_PAD_DISP2_DAT15__DISP2_DAT15   0x5
+                                MX51_PAD_DI2_PIN2__DI2_PIN2         0x5 /* hsync */
+                                MX51_PAD_DI2_PIN3__DI2_PIN3         0x5 /* vsync */
+                                MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5 /* CLK */
+                                MX51_PAD_DI_GP4__DI2_PIN15          0x5 /* DE */
+                        >;
+                };
+        };
+
+        kpp {
+                pinctrl_kpp_1: kppgrp-1 {
+                        fsl,pins = <
+                                MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0
+                                MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0
+                                MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0
+                                MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0
+                                MX51_PAD_KEY_COL0__KEY_COL0 0xe8
+                                MX51_PAD_KEY_COL1__KEY_COL1 0xe8
+                                MX51_PAD_KEY_COL2__KEY_COL2 0xe8
+                                MX51_PAD_KEY_COL3__KEY_COL3 0xe8
+                        >;
+                };
+        };
+
+        pata {
+                pinctrl_pata_1: patagrp-1 {
+                        fsl,pins = <
+                                MX51_PAD_NANDF_WE_B__PATA_DIOW     0x2004
+                                MX51_PAD_NANDF_RE_B__PATA_DIOR     0x2004
+                                MX51_PAD_NANDF_ALE__PATA_BUFFER_EN 0x2004
+                                MX51_PAD_NANDF_CLE__PATA_RESET_B   0x2004
+                                MX51_PAD_NANDF_WP_B__PATA_DMACK    0x2004
+                                MX51_PAD_NANDF_RB0__PATA_DMARQ     0x2004
+                                MX51_PAD_NANDF_RB1__PATA_IORDY     0x2004
+                                MX51_PAD_GPIO_NAND__PATA_INTRQ     0x2004
+                                MX51_PAD_NANDF_CS2__PATA_CS_0      0x2004
+                                MX51_PAD_NANDF_CS3__PATA_CS_1      0x2004
+                                MX51_PAD_NANDF_CS4__PATA_DA_0      0x2004
+                                MX51_PAD_NANDF_CS5__PATA_DA_1      0x2004
+                                MX51_PAD_NANDF_CS6__PATA_DA_2      0x2004
+                                MX51_PAD_NANDF_D15__PATA_DATA15    0x2004
+                                MX51_PAD_NANDF_D14__PATA_DATA14    0x2004
+                                MX51_PAD_NANDF_D13__PATA_DATA13    0x2004
+                                MX51_PAD_NANDF_D12__PATA_DATA12    0x2004
+                                MX51_PAD_NANDF_D11__PATA_DATA11    0x2004
+                                MX51_PAD_NANDF_D10__PATA_DATA10    0x2004
+                                MX51_PAD_NANDF_D9__PATA_DATA9      0x2004
+                                MX51_PAD_NANDF_D8__PATA_DATA8      0x2004
+                                MX51_PAD_NANDF_D7__PATA_DATA7      0x2004
+                                MX51_PAD_NANDF_D6__PATA_DATA6     0x2004
+                                MX51_PAD_NANDF_D5__PATA_DATA5     0x2004
+                                MX51_PAD_NANDF_D4__PATA_DATA4     0x2004
+                                MX51_PAD_NANDF_D3__PATA_DATA3     0x2004
+                                MX51_PAD_NANDF_D2__PATA_DATA2     0x2004
+                                MX51_PAD_NANDF_D1__PATA_DATA1     0x2004
+                                MX51_PAD_NANDF_D0__PATA_DATA0     0x2004
+                        >;
+                };
+        };
+
+        uart1 {
+                pinctrl_uart1_1: uart1grp-1 {
+                        fsl,pins = <
+                                MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
+                                MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
+                                MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
+                                MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
+                        >;
+                };
+        };
+
+        uart2 {
+                pinctrl_uart2_1: uart2grp-1 {
+                        fsl,pins = <
+                                MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
+                                MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
+                        >;
+                };
+        };
+
+        uart3 {
+                pinctrl_uart3_1: uart3grp-1 {
+                        fsl,pins = <
+                                MX51_PAD_EIM_D25__UART3_RXD 0x1c5
+                                MX51_PAD_EIM_D26__UART3_TXD 0x1c5
+                                MX51_PAD_EIM_D27__UART3_RTS 0x1c5
+                                MX51_PAD_EIM_D24__UART3_CTS 0x1c5
+                        >;
+                };
+
+                pinctrl_uart3_2: uart3grp-2 {
+                        fsl,pins = <
+                                MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
+                                MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
+                        >;
+                };
+        };
+
+        usbh1 {
+                pinctrl_usbh1_1: usbh1grp-1 {
+                        fsl,pins = <
+                                MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5
+                                MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5
+                                MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5
+                                MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5
+                                MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5
+                                MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5
+                                MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5
+                                MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5
+                                MX51_PAD_USBH1_CLK__USBH1_CLK     0x1e5
+                                MX51_PAD_USBH1_DIR__USBH1_DIR     0x1e5
+                                MX51_PAD_USBH1_NXT__USBH1_NXT     0x1e5
+                                MX51_PAD_USBH1_STP__USBH1_STP     0x1e5
+                        >;
+                };
+        };
+
+        usbh2 {
+                pinctrl_usbh2_1: usbh2grp-1 {
+                        fsl,pins = <
+                                MX51_PAD_EIM_D16__USBH2_DATA0 0x1e5
+                                MX51_PAD_EIM_D17__USBH2_DATA1 0x1e5
+                                MX51_PAD_EIM_D18__USBH2_DATA2 0x1e5
+                                MX51_PAD_EIM_D19__USBH2_DATA3 0x1e5
+                                MX51_PAD_EIM_D20__USBH2_DATA4 0x1e5
+                                MX51_PAD_EIM_D21__USBH2_DATA5 0x1e5
+                                MX51_PAD_EIM_D22__USBH2_DATA6 0x1e5
+                                MX51_PAD_EIM_D23__USBH2_DATA7 0x1e5
+                                MX51_PAD_EIM_A24__USBH2_CLK   0x1e5
+                                MX51_PAD_EIM_A25__USBH2_DIR   0x1e5
+                                MX51_PAD_EIM_A27__USBH2_NXT   0x1e5
+                                MX51_PAD_EIM_A26__USBH2_STP   0x1e5
+                        >;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts
index 512a1f608253..e97ddae09d74 100644
--- a/arch/arm/boot/dts/imx53-qsb.dts
+++ b/arch/arm/boot/dts/imx53-qsb.dts
@@ -93,6 +93,15 @@
                         regulator-max-microvolt = <3200000>;
                         regulator-always-on;
                 };
+
+                reg_usb_vbus: usb_vbus {
+                        compatible = "regulator-fixed";
+                        regulator-name = "usb_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio7 8 0>;
+                        enable-active-high;
+                };
         };
 
         sound {
@@ -145,6 +154,7 @@
                                 MX53_PAD_EIM_DA12__GPIO3_12       0x80000000
                                 MX53_PAD_EIM_DA13__GPIO3_13       0x80000000
                                 MX53_PAD_PATA_DA_0__GPIO7_6       0x80000000
+                                MX53_PAD_PATA_DA_2__GPIO7_8       0x80000000
                                 MX53_PAD_GPIO_16__GPIO7_11        0x80000000
                         >;
                 };
@@ -297,8 +307,14 @@
         status = "okay";
 };
 
+&vpu {
+        status = "okay";
+};
+
 &usbh1 {
-       status = "okay";
+        vbus-supply = <&reg_usb_vbus>;
+        phy_type = "utmi";
+        status = "okay";
 };
 
 &usbotg {
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index 569aa9f2c4ed..4307e80b2d2e 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -15,11 +15,6 @@
 
 / {
         aliases {
-                serial0 = &uart1;
-                serial1 = &uart2;
-                serial2 = &uart3;
-                serial3 = &uart4;
-                serial4 = &uart5;
                 gpio0 = &gpio1;
                 gpio1 = &gpio2;
                 gpio2 = &gpio3;
@@ -30,6 +25,24 @@
                 i2c0 = &i2c1;
                 i2c1 = &i2c2;
                 i2c2 = &i2c3;
+                serial0 = &uart1;
+                serial1 = &uart2;
+                serial2 = &uart3;
+                serial3 = &uart4;
+                serial4 = &uart5;
+                spi0 = &ecspi1;
+                spi1 = &ecspi2;
+                spi2 = &cspi;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a8";
+                        reg = <0x0>;
+                };
         };
 
         tzic: tz-interrupt-controller@0fffc000 {
@@ -140,6 +153,9 @@
                                         reg = <0x50014000 0x4000>;
                                         interrupts = <30>;
                                         clocks = <&clks 49>;
+                                        dmas = <&sdma 24 1 0>,
+                                               <&sdma 25 1 0>;
+                                        dma-names = "rx", "tx";
                                         fsl,fifo-depth = <15>;
                                         fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
                                         status = "disabled";
@@ -957,6 +973,13 @@
                         reg = <0x60000000 0x10000000>;
                         ranges;
 
+                        iim: iim@63f98000 {
+                                compatible = "fsl,imx53-iim", "fsl,imx27-iim";
+                                reg = <0x63f98000 0x4000>;
+                                interrupts = <69>;
+                                clocks = <&clks 107>;
+                        };
+
                         uart5: serial@63f90000 {
                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
                                 reg = <0x63f90000 0x4000>;
@@ -990,6 +1013,7 @@
                                 interrupts = <6>;
                                 clocks = <&clks 56>, <&clks 56>;
                                 clock-names = "ipg", "ahb";
+                                #dma-cells = <3>;
                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
                         };
 
@@ -1029,6 +1053,9 @@
                                 reg = <0x63fcc000 0x4000>;
                                 interrupts = <29>;
                                 clocks = <&clks 48>;
+                                dmas = <&sdma 28 0 0>,
+                                       <&sdma 29 0 0>;
+                                dma-names = "rx", "tx";
                                 fsl,fifo-depth = <15>;
                                 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
                                 status = "disabled";
@@ -1053,6 +1080,9 @@
                                 reg = <0x63fe8000 0x4000>;
                                 interrupts = <96>;
                                 clocks = <&clks 50>;
+                                dmas = <&sdma 46 0 0>,
+                                       <&sdma 47 0 0>;
+                                dma-names = "rx", "tx";
                                 fsl,fifo-depth = <15>;
                                 fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
                                 status = "disabled";
@@ -1076,6 +1106,22 @@
                                 crtcs = <&ipu 1>;
                                 status = "disabled";
                         };
+
+                        vpu: vpu@63ff4000 {
+                                compatible = "fsl,imx53-vpu";
+                                reg = <0x63ff4000 0x1000>;
+                                interrupts = <9>;
+                                clocks = <&clks 63>, <&clks 63>;
+                                clock-names = "per", "ahb";
+                                iram = <&ocram>;
+                                status = "disabled";
+                        };
+                };
+
+                ocram: sram@f8000000 {
+                        compatible = "mmio-sram";
+                        reg = <0xf8000000 0x20000>;
+                        clocks = <&clks 186>;
                 };
         };
 };
diff --git a/arch/arm/boot/dts/imx6dl-pinfunc.h b/arch/arm/boot/dts/imx6dl-pinfunc.h
index 9aab950ec269..b81a7a4ebab6 100644
--- a/arch/arm/boot/dts/imx6dl-pinfunc.h
+++ b/arch/arm/boot/dts/imx6dl-pinfunc.h
@@ -14,1072 +14,1076 @@
  * The pin function ID is a tuple of
  * <mux_reg conf_reg input_reg mux_mode input_val>
  */
-#define MX6DL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10     0x04c 0x360 0x000 0x0 0x0
-#define MX6DL_PAD_CSI0_DAT10__AUD3_RXC             0x04c 0x360 0x000 0x1 0x0
-#define MX6DL_PAD_CSI0_DAT10__ECSPI2_MISO          0x04c 0x360 0x7f8 0x2 0x0
-#define MX6DL_PAD_CSI0_DAT10__UART1_TX_DATA        0x04c 0x360 0x000 0x3 0x0
-#define MX6DL_PAD_CSI0_DAT10__UART1_RX_DATA        0x04c 0x360 0x8fc 0x3 0x0
-#define MX6DL_PAD_CSI0_DAT10__GPIO5_IO28           0x04c 0x360 0x000 0x5 0x0
-#define MX6DL_PAD_CSI0_DAT10__ARM_TRACE07          0x04c 0x360 0x000 0x7 0x0
-#define MX6DL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11     0x050 0x364 0x000 0x0 0x0
-#define MX6DL_PAD_CSI0_DAT11__AUD3_RXFS            0x050 0x364 0x000 0x1 0x0
-#define MX6DL_PAD_CSI0_DAT11__ECSPI2_SS0           0x050 0x364 0x800 0x2 0x0
-#define MX6DL_PAD_CSI0_DAT11__UART1_RX_DATA        0x050 0x364 0x8fc 0x3 0x1
-#define MX6DL_PAD_CSI0_DAT11__UART1_TX_DATA        0x050 0x364 0x000 0x3 0x0
-#define MX6DL_PAD_CSI0_DAT11__GPIO5_IO29           0x050 0x364 0x000 0x5 0x0
-#define MX6DL_PAD_CSI0_DAT11__ARM_TRACE08          0x050 0x364 0x000 0x7 0x0
-#define MX6DL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12     0x054 0x368 0x000 0x0 0x0
-#define MX6DL_PAD_CSI0_DAT12__EIM_DATA08           0x054 0x368 0x000 0x1 0x0
-#define MX6DL_PAD_CSI0_DAT12__UART4_TX_DATA        0x054 0x368 0x000 0x3 0x0
-#define MX6DL_PAD_CSI0_DAT12__UART4_RX_DATA        0x054 0x368 0x914 0x3 0x0
-#define MX6DL_PAD_CSI0_DAT12__GPIO5_IO30           0x054 0x368 0x000 0x5 0x0
-#define MX6DL_PAD_CSI0_DAT12__ARM_TRACE09          0x054 0x368 0x000 0x7 0x0
-#define MX6DL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13     0x058 0x36c 0x000 0x0 0x0
-#define MX6DL_PAD_CSI0_DAT13__EIM_DATA09           0x058 0x36c 0x000 0x1 0x0
-#define MX6DL_PAD_CSI0_DAT13__UART4_RX_DATA        0x058 0x36c 0x914 0x3 0x1
-#define MX6DL_PAD_CSI0_DAT13__UART4_TX_DATA        0x058 0x36c 0x000 0x3 0x0
-#define MX6DL_PAD_CSI0_DAT13__GPIO5_IO31           0x058 0x36c 0x000 0x5 0x0
-#define MX6DL_PAD_CSI0_DAT13__ARM_TRACE10          0x058 0x36c 0x000 0x7 0x0
-#define MX6DL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14     0x05c 0x370 0x000 0x0 0x0
-#define MX6DL_PAD_CSI0_DAT14__EIM_DATA10           0x05c 0x370 0x000 0x1 0x0
-#define MX6DL_PAD_CSI0_DAT14__UART5_TX_DATA        0x05c 0x370 0x000 0x3 0x0
-#define MX6DL_PAD_CSI0_DAT14__UART5_RX_DATA        0x05c 0x370 0x91c 0x3 0x0
-#define MX6DL_PAD_CSI0_DAT14__GPIO6_IO00           0x05c 0x370 0x000 0x5 0x0
-#define MX6DL_PAD_CSI0_DAT14__ARM_TRACE11          0x05c 0x370 0x000 0x7 0x0
-#define MX6DL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15     0x060 0x374 0x000 0x0 0x0
-#define MX6DL_PAD_CSI0_DAT15__EIM_DATA11           0x060 0x374 0x000 0x1 0x0
-#define MX6DL_PAD_CSI0_DAT15__UART5_RX_DATA        0x060 0x374 0x91c 0x3 0x1
-#define MX6DL_PAD_CSI0_DAT15__UART5_TX_DATA        0x060 0x374 0x000 0x3 0x0
-#define MX6DL_PAD_CSI0_DAT15__GPIO6_IO01           0x060 0x374 0x000 0x5 0x0
-#define MX6DL_PAD_CSI0_DAT15__ARM_TRACE12          0x060 0x374 0x000 0x7 0x0
-#define MX6DL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16     0x064 0x378 0x000 0x0 0x0
-#define MX6DL_PAD_CSI0_DAT16__EIM_DATA12           0x064 0x378 0x000 0x1 0x0
-#define MX6DL_PAD_CSI0_DAT16__UART4_RTS_B          0x064 0x378 0x910 0x3 0x0
-#define MX6DL_PAD_CSI0_DAT16__UART4_CTS_B          0x064 0x378 0x000 0x3 0x0
-#define MX6DL_PAD_CSI0_DAT16__GPIO6_IO02           0x064 0x378 0x000 0x5 0x0
-#define MX6DL_PAD_CSI0_DAT16__ARM_TRACE13          0x064 0x378 0x000 0x7 0x0
-#define MX6DL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17     0x068 0x37c 0x000 0x0 0x0
-#define MX6DL_PAD_CSI0_DAT17__EIM_DATA13           0x068 0x37c 0x000 0x1 0x0
-#define MX6DL_PAD_CSI0_DAT17__UART4_CTS_B          0x068 0x37c 0x000 0x3 0x0
-#define MX6DL_PAD_CSI0_DAT17__UART4_RTS_B          0x068 0x37c 0x910 0x3 0x1
-#define MX6DL_PAD_CSI0_DAT17__GPIO6_IO03           0x068 0x37c 0x000 0x5 0x0
-#define MX6DL_PAD_CSI0_DAT17__ARM_TRACE14          0x068 0x37c 0x000 0x7 0x0
-#define MX6DL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18     0x06c 0x380 0x000 0x0 0x0
-#define MX6DL_PAD_CSI0_DAT18__EIM_DATA14           0x06c 0x380 0x000 0x1 0x0
-#define MX6DL_PAD_CSI0_DAT18__UART5_RTS_B          0x06c 0x380 0x918 0x3 0x0
-#define MX6DL_PAD_CSI0_DAT18__UART5_CTS_B          0x06c 0x380 0x000 0x3 0x0
-#define MX6DL_PAD_CSI0_DAT18__GPIO6_IO04           0x06c 0x380 0x000 0x5 0x0
-#define MX6DL_PAD_CSI0_DAT18__ARM_TRACE15          0x06c 0x380 0x000 0x7 0x0
-#define MX6DL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19     0x070 0x384 0x000 0x0 0x0
-#define MX6DL_PAD_CSI0_DAT19__EIM_DATA15           0x070 0x384 0x000 0x1 0x0
-#define MX6DL_PAD_CSI0_DAT19__UART5_CTS_B          0x070 0x384 0x000 0x3 0x0
-#define MX6DL_PAD_CSI0_DAT19__UART5_RTS_B          0x070 0x384 0x918 0x3 0x1
-#define MX6DL_PAD_CSI0_DAT19__GPIO6_IO05           0x070 0x384 0x000 0x5 0x0
-#define MX6DL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04      0x074 0x388 0x000 0x0 0x0
-#define MX6DL_PAD_CSI0_DAT4__EIM_DATA02            0x074 0x388 0x000 0x1 0x0
-#define MX6DL_PAD_CSI0_DAT4__ECSPI1_SCLK           0x074 0x388 0x7d8 0x2 0x0
-#define MX6DL_PAD_CSI0_DAT4__KEY_COL5              0x074 0x388 0x8c0 0x3 0x0
-#define MX6DL_PAD_CSI0_DAT4__AUD3_TXC              0x074 0x388 0x000 0x4 0x0
-#define MX6DL_PAD_CSI0_DAT4__GPIO5_IO22            0x074 0x388 0x000 0x5 0x0
-#define MX6DL_PAD_CSI0_DAT4__ARM_TRACE01           0x074 0x388 0x000 0x7 0x0
-#define MX6DL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05      0x078 0x38c 0x000 0x0 0x0
-#define MX6DL_PAD_CSI0_DAT5__EIM_DATA03            0x078 0x38c 0x000 0x1 0x0
-#define MX6DL_PAD_CSI0_DAT5__ECSPI1_MOSI           0x078 0x38c 0x7e0 0x2 0x0
-#define MX6DL_PAD_CSI0_DAT5__KEY_ROW5              0x078 0x38c 0x8cc 0x3 0x0
-#define MX6DL_PAD_CSI0_DAT5__AUD3_TXD              0x078 0x38c 0x000 0x4 0x0
-#define MX6DL_PAD_CSI0_DAT5__GPIO5_IO23            0x078 0x38c 0x000 0x5 0x0
-#define MX6DL_PAD_CSI0_DAT5__ARM_TRACE02           0x078 0x38c 0x000 0x7 0x0
-#define MX6DL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06      0x07c 0x390 0x000 0x0 0x0
-#define MX6DL_PAD_CSI0_DAT6__EIM_DATA04            0x07c 0x390 0x000 0x1 0x0
-#define MX6DL_PAD_CSI0_DAT6__ECSPI1_MISO           0x07c 0x390 0x7dc 0x2 0x0
-#define MX6DL_PAD_CSI0_DAT6__KEY_COL6              0x07c 0x390 0x8c4 0x3 0x0
-#define MX6DL_PAD_CSI0_DAT6__AUD3_TXFS             0x07c 0x390 0x000 0x4 0x0
-#define MX6DL_PAD_CSI0_DAT6__GPIO5_IO24            0x07c 0x390 0x000 0x5 0x0
-#define MX6DL_PAD_CSI0_DAT6__ARM_TRACE03           0x07c 0x390 0x000 0x7 0x0
-#define MX6DL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07      0x080 0x394 0x000 0x0 0x0
-#define MX6DL_PAD_CSI0_DAT7__EIM_DATA05            0x080 0x394 0x000 0x1 0x0
-#define MX6DL_PAD_CSI0_DAT7__ECSPI1_SS0            0x080 0x394 0x7e4 0x2 0x0
-#define MX6DL_PAD_CSI0_DAT7__KEY_ROW6              0x080 0x394 0x8d0 0x3 0x0
-#define MX6DL_PAD_CSI0_DAT7__AUD3_RXD              0x080 0x394 0x000 0x4 0x0
-#define MX6DL_PAD_CSI0_DAT7__GPIO5_IO25            0x080 0x394 0x000 0x5 0x0
-#define MX6DL_PAD_CSI0_DAT7__ARM_TRACE04           0x080 0x394 0x000 0x7 0x0
-#define MX6DL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08      0x084 0x398 0x000 0x0 0x0
-#define MX6DL_PAD_CSI0_DAT8__EIM_DATA06            0x084 0x398 0x000 0x1 0x0
-#define MX6DL_PAD_CSI0_DAT8__ECSPI2_SCLK           0x084 0x398 0x7f4 0x2 0x0
-#define MX6DL_PAD_CSI0_DAT8__KEY_COL7              0x084 0x398 0x8c8 0x3 0x0
-#define MX6DL_PAD_CSI0_DAT8__I2C1_SDA              0x084 0x398 0x86c 0x4 0x0
-#define MX6DL_PAD_CSI0_DAT8__GPIO5_IO26            0x084 0x398 0x000 0x5 0x0
-#define MX6DL_PAD_CSI0_DAT8__ARM_TRACE05           0x084 0x398 0x000 0x7 0x0
-#define MX6DL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09      0x088 0x39c 0x000 0x0 0x0
-#define MX6DL_PAD_CSI0_DAT9__EIM_DATA07            0x088 0x39c 0x000 0x1 0x0
-#define MX6DL_PAD_CSI0_DAT9__ECSPI2_MOSI           0x088 0x39c 0x7fc 0x2 0x0
-#define MX6DL_PAD_CSI0_DAT9__KEY_ROW7              0x088 0x39c 0x8d4 0x3 0x0
-#define MX6DL_PAD_CSI0_DAT9__I2C1_SCL              0x088 0x39c 0x868 0x4 0x0
-#define MX6DL_PAD_CSI0_DAT9__GPIO5_IO27            0x088 0x39c 0x000 0x5 0x0
-#define MX6DL_PAD_CSI0_DAT9__ARM_TRACE06           0x088 0x39c 0x000 0x7 0x0
-#define MX6DL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN  0x08c 0x3a0 0x000 0x0 0x0
-#define MX6DL_PAD_CSI0_DATA_EN__EIM_DATA00         0x08c 0x3a0 0x000 0x1 0x0
-#define MX6DL_PAD_CSI0_DATA_EN__GPIO5_IO20         0x08c 0x3a0 0x000 0x5 0x0
-#define MX6DL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK      0x08c 0x3a0 0x000 0x7 0x0
-#define MX6DL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC       0x090 0x3a4 0x000 0x0 0x0
-#define MX6DL_PAD_CSI0_MCLK__CCM_CLKO1             0x090 0x3a4 0x000 0x3 0x0
-#define MX6DL_PAD_CSI0_MCLK__GPIO5_IO19            0x090 0x3a4 0x000 0x5 0x0
-#define MX6DL_PAD_CSI0_MCLK__ARM_TRACE_CTL         0x090 0x3a4 0x000 0x7 0x0
-#define MX6DL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK    0x094 0x3a8 0x000 0x0 0x0
-#define MX6DL_PAD_CSI0_PIXCLK__GPIO5_IO18          0x094 0x3a8 0x000 0x5 0x0
-#define MX6DL_PAD_CSI0_PIXCLK__ARM_EVENTO          0x094 0x3a8 0x000 0x7 0x0
-#define MX6DL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC      0x098 0x3ac 0x000 0x0 0x0
-#define MX6DL_PAD_CSI0_VSYNC__EIM_DATA01           0x098 0x3ac 0x000 0x1 0x0
-#define MX6DL_PAD_CSI0_VSYNC__GPIO5_IO21           0x098 0x3ac 0x000 0x5 0x0
-#define MX6DL_PAD_CSI0_VSYNC__ARM_TRACE00          0x098 0x3ac 0x000 0x7 0x0
-#define MX6DL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK  0x09c 0x3b0 0x000 0x0 0x0
-#define MX6DL_PAD_DI0_DISP_CLK__LCD_CLK            0x09c 0x3b0 0x000 0x1 0x0
-#define MX6DL_PAD_DI0_DISP_CLK__GPIO4_IO16         0x09c 0x3b0 0x000 0x5 0x0
-#define MX6DL_PAD_DI0_DISP_CLK__LCD_WR_RWN         0x09c 0x3b0 0x000 0x8 0x0
-#define MX6DL_PAD_DI0_PIN15__IPU1_DI0_PIN15        0x0a0 0x3b4 0x000 0x0 0x0
-#define MX6DL_PAD_DI0_PIN15__LCD_ENABLE            0x0a0 0x3b4 0x000 0x1 0x0
-#define MX6DL_PAD_DI0_PIN15__AUD6_TXC              0x0a0 0x3b4 0x000 0x2 0x0
-#define MX6DL_PAD_DI0_PIN15__GPIO4_IO17            0x0a0 0x3b4 0x000 0x5 0x0
-#define MX6DL_PAD_DI0_PIN15__LCD_RD_E              0x0a0 0x3b4 0x000 0x8 0x0
-#define MX6DL_PAD_DI0_PIN2__IPU1_DI0_PIN02         0x0a4 0x3b8 0x000 0x0 0x0
-#define MX6DL_PAD_DI0_PIN2__LCD_HSYNC              0x0a4 0x3b8 0x8d8 0x1 0x0
-#define MX6DL_PAD_DI0_PIN2__AUD6_TXD               0x0a4 0x3b8 0x000 0x2 0x0
-#define MX6DL_PAD_DI0_PIN2__GPIO4_IO18             0x0a4 0x3b8 0x000 0x5 0x0
-#define MX6DL_PAD_DI0_PIN2__LCD_RS                 0x0a4 0x3b8 0x000 0x8 0x0
-#define MX6DL_PAD_DI0_PIN3__IPU1_DI0_PIN03         0x0a8 0x3bc 0x000 0x0 0x0
-#define MX6DL_PAD_DI0_PIN3__LCD_VSYNC              0x0a8 0x3bc 0x000 0x1 0x0
-#define MX6DL_PAD_DI0_PIN3__AUD6_TXFS              0x0a8 0x3bc 0x000 0x2 0x0
-#define MX6DL_PAD_DI0_PIN3__GPIO4_IO19             0x0a8 0x3bc 0x000 0x5 0x0
-#define MX6DL_PAD_DI0_PIN3__LCD_CS                 0x0a8 0x3bc 0x000 0x8 0x0
-#define MX6DL_PAD_DI0_PIN4__IPU1_DI0_PIN04         0x0ac 0x3c0 0x000 0x0 0x0
-#define MX6DL_PAD_DI0_PIN4__LCD_BUSY               0x0ac 0x3c0 0x8d8 0x1 0x1
-#define MX6DL_PAD_DI0_PIN4__AUD6_RXD               0x0ac 0x3c0 0x000 0x2 0x0
-#define MX6DL_PAD_DI0_PIN4__SD1_WP                 0x0ac 0x3c0 0x92c 0x3 0x0
-#define MX6DL_PAD_DI0_PIN4__GPIO4_IO20             0x0ac 0x3c0 0x000 0x5 0x0
-#define MX6DL_PAD_DI0_PIN4__LCD_RESET              0x0ac 0x3c0 0x000 0x8 0x0
-#define MX6DL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00    0x0b0 0x3c4 0x000 0x0 0x0
-#define MX6DL_PAD_DISP0_DAT0__LCD_DATA00           0x0b0 0x3c4 0x000 0x1 0x0
-#define MX6DL_PAD_DISP0_DAT0__ECSPI3_SCLK          0x0b0 0x3c4 0x000 0x2 0x0
-#define MX6DL_PAD_DISP0_DAT0__GPIO4_IO21           0x0b0 0x3c4 0x000 0x5 0x0
-#define MX6DL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01    0x0b4 0x3c8 0x000 0x0 0x0
-#define MX6DL_PAD_DISP0_DAT1__LCD_DATA01           0x0b4 0x3c8 0x000 0x1 0x0
-#define MX6DL_PAD_DISP0_DAT1__ECSPI3_MOSI          0x0b4 0x3c8 0x000 0x2 0x0
-#define MX6DL_PAD_DISP0_DAT1__GPIO4_IO22           0x0b4 0x3c8 0x000 0x5 0x0
-#define MX6DL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10   0x0b8 0x3cc 0x000 0x0 0x0
-#define MX6DL_PAD_DISP0_DAT10__LCD_DATA10          0x0b8 0x3cc 0x000 0x1 0x0
-#define MX6DL_PAD_DISP0_DAT10__GPIO4_IO31          0x0b8 0x3cc 0x000 0x5 0x0
-#define MX6DL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11   0x0bc 0x3d0 0x000 0x0 0x0
-#define MX6DL_PAD_DISP0_DAT11__LCD_DATA11          0x0bc 0x3d0 0x000 0x1 0x0
-#define MX6DL_PAD_DISP0_DAT11__GPIO5_IO05          0x0bc 0x3d0 0x000 0x5 0x0
-#define MX6DL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12   0x0c0 0x3d4 0x000 0x0 0x0
-#define MX6DL_PAD_DISP0_DAT12__LCD_DATA12          0x0c0 0x3d4 0x000 0x1 0x0
-#define MX6DL_PAD_DISP0_DAT12__GPIO5_IO06          0x0c0 0x3d4 0x000 0x5 0x0
-#define MX6DL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13   0x0c4 0x3d8 0x000 0x0 0x0
-#define MX6DL_PAD_DISP0_DAT13__LCD_DATA13          0x0c4 0x3d8 0x000 0x1 0x0
-#define MX6DL_PAD_DISP0_DAT13__AUD5_RXFS           0x0c4 0x3d8 0x7bc 0x3 0x0
-#define MX6DL_PAD_DISP0_DAT13__GPIO5_IO07          0x0c4 0x3d8 0x000 0x5 0x0
-#define MX6DL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14   0x0c8 0x3dc 0x000 0x0 0x0
-#define MX6DL_PAD_DISP0_DAT14__LCD_DATA14          0x0c8 0x3dc 0x000 0x1 0x0
-#define MX6DL_PAD_DISP0_DAT14__AUD5_RXC            0x0c8 0x3dc 0x7b8 0x3 0x0
-#define MX6DL_PAD_DISP0_DAT14__GPIO5_IO08          0x0c8 0x3dc 0x000 0x5 0x0
-#define MX6DL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15   0x0cc 0x3e0 0x000 0x0 0x0
-#define MX6DL_PAD_DISP0_DAT15__LCD_DATA15          0x0cc 0x3e0 0x000 0x1 0x0
-#define MX6DL_PAD_DISP0_DAT15__ECSPI1_SS1          0x0cc 0x3e0 0x7e8 0x2 0x0
-#define MX6DL_PAD_DISP0_DAT15__ECSPI2_SS1          0x0cc 0x3e0 0x804 0x3 0x0
-#define MX6DL_PAD_DISP0_DAT15__GPIO5_IO09          0x0cc 0x3e0 0x000 0x5 0x0
-#define MX6DL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16   0x0d0 0x3e4 0x000 0x0 0x0
-#define MX6DL_PAD_DISP0_DAT16__LCD_DATA16          0x0d0 0x3e4 0x000 0x1 0x0
-#define MX6DL_PAD_DISP0_DAT16__ECSPI2_MOSI         0x0d0 0x3e4 0x7fc 0x2 0x1
-#define MX6DL_PAD_DISP0_DAT16__AUD5_TXC            0x0d0 0x3e4 0x7c0 0x3 0x0
-#define MX6DL_PAD_DISP0_DAT16__SDMA_EXT_EVENT0     0x0d0 0x3e4 0x8e8 0x4 0x0
-#define MX6DL_PAD_DISP0_DAT16__GPIO5_IO10          0x0d0 0x3e4 0x000 0x5 0x0
-#define MX6DL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17   0x0d4 0x3e8 0x000 0x0 0x0
-#define MX6DL_PAD_DISP0_DAT17__LCD_DATA17          0x0d4 0x3e8 0x000 0x1 0x0
-#define MX6DL_PAD_DISP0_DAT17__ECSPI2_MISO         0x0d4 0x3e8 0x7f8 0x2 0x1
-#define MX6DL_PAD_DISP0_DAT17__AUD5_TXD            0x0d4 0x3e8 0x7b4 0x3 0x0
-#define MX6DL_PAD_DISP0_DAT17__SDMA_EXT_EVENT1     0x0d4 0x3e8 0x8ec 0x4 0x0
-#define MX6DL_PAD_DISP0_DAT17__GPIO5_IO11          0x0d4 0x3e8 0x000 0x5 0x0
-#define MX6DL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18   0x0d8 0x3ec 0x000 0x0 0x0
-#define MX6DL_PAD_DISP0_DAT18__LCD_DATA18          0x0d8 0x3ec 0x000 0x1 0x0
-#define MX6DL_PAD_DISP0_DAT18__ECSPI2_SS0          0x0d8 0x3ec 0x800 0x2 0x1
-#define MX6DL_PAD_DISP0_DAT18__AUD5_TXFS           0x0d8 0x3ec 0x7c4 0x3 0x0
-#define MX6DL_PAD_DISP0_DAT18__AUD4_RXFS           0x0d8 0x3ec 0x7a4 0x4 0x0
-#define MX6DL_PAD_DISP0_DAT18__GPIO5_IO12          0x0d8 0x3ec 0x000 0x5 0x0
-#define MX6DL_PAD_DISP0_DAT18__EIM_CS2_B           0x0d8 0x3ec 0x000 0x7 0x0
-#define MX6DL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19   0x0dc 0x3f0 0x000 0x0 0x0
-#define MX6DL_PAD_DISP0_DAT19__LCD_DATA19          0x0dc 0x3f0 0x000 0x1 0x0
-#define MX6DL_PAD_DISP0_DAT19__ECSPI2_SCLK         0x0dc 0x3f0 0x7f4 0x2 0x1
-#define MX6DL_PAD_DISP0_DAT19__AUD5_RXD            0x0dc 0x3f0 0x7b0 0x3 0x0
-#define MX6DL_PAD_DISP0_DAT19__AUD4_RXC            0x0dc 0x3f0 0x7a0 0x4 0x0
-#define MX6DL_PAD_DISP0_DAT19__GPIO5_IO13          0x0dc 0x3f0 0x000 0x5 0x0
-#define MX6DL_PAD_DISP0_DAT19__EIM_CS3_B           0x0dc 0x3f0 0x000 0x7 0x0
-#define MX6DL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02    0x0e0 0x3f4 0x000 0x0 0x0
-#define MX6DL_PAD_DISP0_DAT2__LCD_DATA02           0x0e0 0x3f4 0x000 0x1 0x0
-#define MX6DL_PAD_DISP0_DAT2__ECSPI3_MISO          0x0e0 0x3f4 0x000 0x2 0x0
-#define MX6DL_PAD_DISP0_DAT2__GPIO4_IO23           0x0e0 0x3f4 0x000 0x5 0x0
-#define MX6DL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20   0x0e4 0x3f8 0x000 0x0 0x0
-#define MX6DL_PAD_DISP0_DAT20__LCD_DATA20          0x0e4 0x3f8 0x000 0x1 0x0
-#define MX6DL_PAD_DISP0_DAT20__ECSPI1_SCLK         0x0e4 0x3f8 0x7d8 0x2 0x1
-#define MX6DL_PAD_DISP0_DAT20__AUD4_TXC            0x0e4 0x3f8 0x7a8 0x3 0x0
-#define MX6DL_PAD_DISP0_DAT20__GPIO5_IO14          0x0e4 0x3f8 0x000 0x5 0x0
-#define MX6DL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21   0x0e8 0x3fc 0x000 0x0 0x0
-#define MX6DL_PAD_DISP0_DAT21__LCD_DATA21          0x0e8 0x3fc 0x000 0x1 0x0
-#define MX6DL_PAD_DISP0_DAT21__ECSPI1_MOSI         0x0e8 0x3fc 0x7e0 0x2 0x1
-#define MX6DL_PAD_DISP0_DAT21__AUD4_TXD            0x0e8 0x3fc 0x79c 0x3 0x0
-#define MX6DL_PAD_DISP0_DAT21__GPIO5_IO15          0x0e8 0x3fc 0x000 0x5 0x0
-#define MX6DL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22   0x0ec 0x400 0x000 0x0 0x0
-#define MX6DL_PAD_DISP0_DAT22__LCD_DATA22          0x0ec 0x400 0x000 0x1 0x0
-#define MX6DL_PAD_DISP0_DAT22__ECSPI1_MISO         0x0ec 0x400 0x7dc 0x2 0x1
-#define MX6DL_PAD_DISP0_DAT22__AUD4_TXFS           0x0ec 0x400 0x7ac 0x3 0x0
-#define MX6DL_PAD_DISP0_DAT22__GPIO5_IO16          0x0ec 0x400 0x000 0x5 0x0
-#define MX6DL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23   0x0f0 0x404 0x000 0x0 0x0
-#define MX6DL_PAD_DISP0_DAT23__LCD_DATA23          0x0f0 0x404 0x000 0x1 0x0
-#define MX6DL_PAD_DISP0_DAT23__ECSPI1_SS0          0x0f0 0x404 0x7e4 0x2 0x1
-#define MX6DL_PAD_DISP0_DAT23__AUD4_RXD            0x0f0 0x404 0x798 0x3 0x0
-#define MX6DL_PAD_DISP0_DAT23__GPIO5_IO17          0x0f0 0x404 0x000 0x5 0x0
-#define MX6DL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03    0x0f4 0x408 0x000 0x0 0x0
-#define MX6DL_PAD_DISP0_DAT3__LCD_DATA03           0x0f4 0x408 0x000 0x1 0x0
-#define MX6DL_PAD_DISP0_DAT3__ECSPI3_SS0           0x0f4 0x408 0x000 0x2 0x0
-#define MX6DL_PAD_DISP0_DAT3__GPIO4_IO24           0x0f4 0x408 0x000 0x5 0x0
-#define MX6DL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04    0x0f8 0x40c 0x000 0x0 0x0
-#define MX6DL_PAD_DISP0_DAT4__LCD_DATA04           0x0f8 0x40c 0x000 0x1 0x0
-#define MX6DL_PAD_DISP0_DAT4__ECSPI3_SS1           0x0f8 0x40c 0x000 0x2 0x0
-#define MX6DL_PAD_DISP0_DAT4__GPIO4_IO25           0x0f8 0x40c 0x000 0x5 0x0
-#define MX6DL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05    0x0fc 0x410 0x000 0x0 0x0
-#define MX6DL_PAD_DISP0_DAT5__LCD_DATA05           0x0fc 0x410 0x000 0x1 0x0
-#define MX6DL_PAD_DISP0_DAT5__ECSPI3_SS2           0x0fc 0x410 0x000 0x2 0x0
-#define MX6DL_PAD_DISP0_DAT5__AUD6_RXFS            0x0fc 0x410 0x000 0x3 0x0
-#define MX6DL_PAD_DISP0_DAT5__GPIO4_IO26           0x0fc 0x410 0x000 0x5 0x0
-#define MX6DL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06    0x100 0x414 0x000 0x0 0x0
-#define MX6DL_PAD_DISP0_DAT6__LCD_DATA06           0x100 0x414 0x000 0x1 0x0
-#define MX6DL_PAD_DISP0_DAT6__ECSPI3_SS3           0x100 0x414 0x000 0x2 0x0
-#define MX6DL_PAD_DISP0_DAT6__AUD6_RXC             0x100 0x414 0x000 0x3 0x0
-#define MX6DL_PAD_DISP0_DAT6__GPIO4_IO27           0x100 0x414 0x000 0x5 0x0
-#define MX6DL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07    0x104 0x418 0x000 0x0 0x0
-#define MX6DL_PAD_DISP0_DAT7__LCD_DATA07           0x104 0x418 0x000 0x1 0x0
-#define MX6DL_PAD_DISP0_DAT7__ECSPI3_RDY           0x104 0x418 0x000 0x2 0x0
-#define MX6DL_PAD_DISP0_DAT7__GPIO4_IO28           0x104 0x418 0x000 0x5 0x0
-#define MX6DL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08    0x108 0x41c 0x000 0x0 0x0
-#define MX6DL_PAD_DISP0_DAT8__LCD_DATA08           0x108 0x41c 0x000 0x1 0x0
-#define MX6DL_PAD_DISP0_DAT8__PWM1_OUT             0x108 0x41c 0x000 0x2 0x0
-#define MX6DL_PAD_DISP0_DAT8__WDOG1_B              0x108 0x41c 0x000 0x3 0x0
-#define MX6DL_PAD_DISP0_DAT8__GPIO4_IO29           0x108 0x41c 0x000 0x5 0x0
-#define MX6DL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09    0x10c 0x420 0x000 0x0 0x0
-#define MX6DL_PAD_DISP0_DAT9__LCD_DATA09           0x10c 0x420 0x000 0x1 0x0
-#define MX6DL_PAD_DISP0_DAT9__PWM2_OUT             0x10c 0x420 0x000 0x2 0x0
-#define MX6DL_PAD_DISP0_DAT9__WDOG2_B              0x10c 0x420 0x000 0x3 0x0
-#define MX6DL_PAD_DISP0_DAT9__GPIO4_IO30           0x10c 0x420 0x000 0x5 0x0
-#define MX6DL_PAD_EIM_A16__EIM_ADDR16              0x110 0x4e0 0x000 0x0 0x0
-#define MX6DL_PAD_EIM_A16__IPU1_DI1_DISP_CLK       0x110 0x4e0 0x000 0x1 0x0
-#define MX6DL_PAD_EIM_A16__IPU1_CSI1_PIXCLK        0x110 0x4e0 0x8b8 0x2 0x0
-#define MX6DL_PAD_EIM_A16__GPIO2_IO22              0x110 0x4e0 0x000 0x5 0x0
-#define MX6DL_PAD_EIM_A16__SRC_BOOT_CFG16          0x110 0x4e0 0x000 0x7 0x0
-#define MX6DL_PAD_EIM_A16__EPDC_DATA00             0x110 0x4e0 0x000 0x8 0x0
-#define MX6DL_PAD_EIM_A17__EIM_ADDR17              0x114 0x4e4 0x000 0x0 0x0
-#define MX6DL_PAD_EIM_A17__IPU1_DISP1_DATA12       0x114 0x4e4 0x000 0x1 0x0
-#define MX6DL_PAD_EIM_A17__IPU1_CSI1_DATA12        0x114 0x4e4 0x890 0x2 0x0
-#define MX6DL_PAD_EIM_A17__GPIO2_IO21              0x114 0x4e4 0x000 0x5 0x0
-#define MX6DL_PAD_EIM_A17__SRC_BOOT_CFG17          0x114 0x4e4 0x000 0x7 0x0
-#define MX6DL_PAD_EIM_A17__EPDC_PWR_STAT           0x114 0x4e4 0x000 0x8 0x0
-#define MX6DL_PAD_EIM_A18__EIM_ADDR18              0x118 0x4e8 0x000 0x0 0x0
-#define MX6DL_PAD_EIM_A18__IPU1_DISP1_DATA13       0x118 0x4e8 0x000 0x1 0x0
-#define MX6DL_PAD_EIM_A18__IPU1_CSI1_DATA13        0x118 0x4e8 0x894 0x2 0x0
-#define MX6DL_PAD_EIM_A18__GPIO2_IO20              0x118 0x4e8 0x000 0x5 0x0
-#define MX6DL_PAD_EIM_A18__SRC_BOOT_CFG18          0x118 0x4e8 0x000 0x7 0x0
-#define MX6DL_PAD_EIM_A18__EPDC_PWR_CTRL0          0x118 0x4e8 0x000 0x8 0x0
-#define MX6DL_PAD_EIM_A19__EIM_ADDR19              0x11c 0x4ec 0x000 0x0 0x0
-#define MX6DL_PAD_EIM_A19__IPU1_DISP1_DATA14       0x11c 0x4ec 0x000 0x1 0x0
-#define MX6DL_PAD_EIM_A19__IPU1_CSI1_DATA14        0x11c 0x4ec 0x898 0x2 0x0
-#define MX6DL_PAD_EIM_A19__GPIO2_IO19              0x11c 0x4ec 0x000 0x5 0x0
-#define MX6DL_PAD_EIM_A19__SRC_BOOT_CFG19          0x11c 0x4ec 0x000 0x7 0x0
-#define MX6DL_PAD_EIM_A19__EPDC_PWR_CTRL1          0x11c 0x4ec 0x000 0x8 0x0
-#define MX6DL_PAD_EIM_A20__EIM_ADDR20              0x120 0x4f0 0x000 0x0 0x0
-#define MX6DL_PAD_EIM_A20__IPU1_DISP1_DATA15       0x120 0x4f0 0x000 0x1 0x0
-#define MX6DL_PAD_EIM_A20__IPU1_CSI1_DATA15        0x120 0x4f0 0x89c 0x2 0x0
-#define MX6DL_PAD_EIM_A20__GPIO2_IO18              0x120 0x4f0 0x000 0x5 0x0
-#define MX6DL_PAD_EIM_A20__SRC_BOOT_CFG20          0x120 0x4f0 0x000 0x7 0x0
-#define MX6DL_PAD_EIM_A20__EPDC_PWR_CTRL2          0x120 0x4f0 0x000 0x8 0x0
-#define MX6DL_PAD_EIM_A21__EIM_ADDR21              0x124 0x4f4 0x000 0x0 0x0
-#define MX6DL_PAD_EIM_A21__IPU1_DISP1_DATA16       0x124 0x4f4 0x000 0x1 0x0
-#define MX6DL_PAD_EIM_A21__IPU1_CSI1_DATA16        0x124 0x4f4 0x8a0 0x2 0x0
-#define MX6DL_PAD_EIM_A21__GPIO2_IO17              0x124 0x4f4 0x000 0x5 0x0
-#define MX6DL_PAD_EIM_A21__SRC_BOOT_CFG21          0x124 0x4f4 0x000 0x7 0x0
-#define MX6DL_PAD_EIM_A21__EPDC_GDCLK              0x124 0x4f4 0x000 0x8 0x0
-#define MX6DL_PAD_EIM_A22__EIM_ADDR22              0x128 0x4f8 0x000 0x0 0x0
-#define MX6DL_PAD_EIM_A22__IPU1_DISP1_DATA17       0x128 0x4f8 0x000 0x1 0x0
-#define MX6DL_PAD_EIM_A22__IPU1_CSI1_DATA17        0x128 0x4f8 0x8a4 0x2 0x0
-#define MX6DL_PAD_EIM_A22__GPIO2_IO16              0x128 0x4f8 0x000 0x5 0x0
-#define MX6DL_PAD_EIM_A22__SRC_BOOT_CFG22          0x128 0x4f8 0x000 0x7 0x0
-#define MX6DL_PAD_EIM_A22__EPDC_GDSP               0x128 0x4f8 0x000 0x8 0x0
-#define MX6DL_PAD_EIM_A23__EIM_ADDR23              0x12c 0x4fc 0x000 0x0 0x0
-#define MX6DL_PAD_EIM_A23__IPU1_DISP1_DATA18       0x12c 0x4fc 0x000 0x1 0x0
-#define MX6DL_PAD_EIM_A23__IPU1_CSI1_DATA18        0x12c 0x4fc 0x8a8 0x2 0x0
-#define MX6DL_PAD_EIM_A23__IPU1_SISG3              0x12c 0x4fc 0x000 0x4 0x0
-#define MX6DL_PAD_EIM_A23__GPIO6_IO06              0x12c 0x4fc 0x000 0x5 0x0
-#define MX6DL_PAD_EIM_A23__SRC_BOOT_CFG23          0x12c 0x4fc 0x000 0x7 0x0
-#define MX6DL_PAD_EIM_A23__EPDC_GDOE               0x12c 0x4fc 0x000 0x8 0x0
-#define MX6DL_PAD_EIM_A24__EIM_ADDR24              0x130 0x500 0x000 0x0 0x0
-#define MX6DL_PAD_EIM_A24__IPU1_DISP1_DATA19       0x130 0x500 0x000 0x1 0x0
-#define MX6DL_PAD_EIM_A24__IPU1_CSI1_DATA19        0x130 0x500 0x8ac 0x2 0x0
-#define MX6DL_PAD_EIM_A24__IPU1_SISG2              0x130 0x500 0x000 0x4 0x0
-#define MX6DL_PAD_EIM_A24__GPIO5_IO04              0x130 0x500 0x000 0x5 0x0
-#define MX6DL_PAD_EIM_A24__SRC_BOOT_CFG24          0x130 0x500 0x000 0x7 0x0
-#define MX6DL_PAD_EIM_A24__EPDC_GDRL               0x130 0x500 0x000 0x8 0x0
-#define MX6DL_PAD_EIM_A25__EIM_ADDR25              0x134 0x504 0x000 0x0 0x0
-#define MX6DL_PAD_EIM_A25__ECSPI4_SS1              0x134 0x504 0x000 0x1 0x0
-#define MX6DL_PAD_EIM_A25__ECSPI2_RDY              0x134 0x504 0x000 0x2 0x0
-#define MX6DL_PAD_EIM_A25__IPU1_DI1_PIN12          0x134 0x504 0x000 0x3 0x0
-#define MX6DL_PAD_EIM_A25__IPU1_DI0_D1_CS          0x134 0x504 0x000 0x4 0x0
-#define MX6DL_PAD_EIM_A25__GPIO5_IO02              0x134 0x504 0x000 0x5 0x0
-#define MX6DL_PAD_EIM_A25__HDMI_TX_CEC_LINE        0x134 0x504 0x85c 0x6 0x0
-#define MX6DL_PAD_EIM_A25__EPDC_DATA15             0x134 0x504 0x000 0x8 0x0
-#define MX6DL_PAD_EIM_A25__EIM_ACLK_FREERUN        0x134 0x504 0x000 0x9 0x0
-#define MX6DL_PAD_EIM_BCLK__EIM_BCLK               0x138 0x508 0x000 0x0 0x0
-#define MX6DL_PAD_EIM_BCLK__IPU1_DI1_PIN16         0x138 0x508 0x000 0x1 0x0
-#define MX6DL_PAD_EIM_BCLK__GPIO6_IO31             0x138 0x508 0x000 0x5 0x0
-#define MX6DL_PAD_EIM_BCLK__EPDC_SDCE9             0x138 0x508 0x000 0x8 0x0
-#define MX6DL_PAD_EIM_CS0__EIM_CS0_B               0x13c 0x50c 0x000 0x0 0x0
-#define MX6DL_PAD_EIM_CS0__IPU1_DI1_PIN05          0x13c 0x50c 0x000 0x1 0x0
-#define MX6DL_PAD_EIM_CS0__ECSPI2_SCLK             0x13c 0x50c 0x7f4 0x2 0x2
-#define MX6DL_PAD_EIM_CS0__GPIO2_IO23              0x13c 0x50c 0x000 0x5 0x0
-#define MX6DL_PAD_EIM_CS0__EPDC_DATA06             0x13c 0x50c 0x000 0x8 0x0
-#define MX6DL_PAD_EIM_CS1__EIM_CS1_B               0x140 0x510 0x000 0x0 0x0
-#define MX6DL_PAD_EIM_CS1__IPU1_DI1_PIN06          0x140 0x510 0x000 0x1 0x0
-#define MX6DL_PAD_EIM_CS1__ECSPI2_MOSI             0x140 0x510 0x7fc 0x2 0x2
-#define MX6DL_PAD_EIM_CS1__GPIO2_IO24              0x140 0x510 0x000 0x5 0x0
-#define MX6DL_PAD_EIM_CS1__EPDC_DATA08             0x140 0x510 0x000 0x8 0x0
-#define MX6DL_PAD_EIM_D16__EIM_DATA16              0x144 0x514 0x000 0x0 0x0
-#define MX6DL_PAD_EIM_D16__ECSPI1_SCLK             0x144 0x514 0x7d8 0x1 0x2
-#define MX6DL_PAD_EIM_D16__IPU1_DI0_PIN05          0x144 0x514 0x000 0x2 0x0
-#define MX6DL_PAD_EIM_D16__IPU1_CSI1_DATA18        0x144 0x514 0x8a8 0x3 0x1
-#define MX6DL_PAD_EIM_D16__HDMI_TX_DDC_SDA         0x144 0x514 0x864 0x4 0x0
-#define MX6DL_PAD_EIM_D16__GPIO3_IO16              0x144 0x514 0x000 0x5 0x0
-#define MX6DL_PAD_EIM_D16__I2C2_SDA                0x144 0x514 0x874 0x6 0x0
-#define MX6DL_PAD_EIM_D16__EPDC_DATA10             0x144 0x514 0x000 0x8 0x0
-#define MX6DL_PAD_EIM_D17__EIM_DATA17              0x148 0x518 0x000 0x0 0x0
-#define MX6DL_PAD_EIM_D17__ECSPI1_MISO             0x148 0x518 0x7dc 0x1 0x2
-#define MX6DL_PAD_EIM_D17__IPU1_DI0_PIN06          0x148 0x518 0x000 0x2 0x0
-#define MX6DL_PAD_EIM_D17__IPU1_CSI1_PIXCLK        0x148 0x518 0x8b8 0x3 0x1
-#define MX6DL_PAD_EIM_D17__DCIC1_OUT               0x148 0x518 0x000 0x4 0x0
-#define MX6DL_PAD_EIM_D17__GPIO3_IO17              0x148 0x518 0x000 0x5 0x0
-#define MX6DL_PAD_EIM_D17__I2C3_SCL                0x148 0x518 0x878 0x6 0x0
-#define MX6DL_PAD_EIM_D17__EPDC_VCOM0              0x148 0x518 0x000 0x8 0x0
-#define MX6DL_PAD_EIM_D18__EIM_DATA18              0x14c 0x51c 0x000 0x0 0x0
-#define MX6DL_PAD_EIM_D18__ECSPI1_MOSI             0x14c 0x51c 0x7e0 0x1 0x2
-#define MX6DL_PAD_EIM_D18__IPU1_DI0_PIN07          0x14c 0x51c 0x000 0x2 0x0
-#define MX6DL_PAD_EIM_D18__IPU1_CSI1_DATA17        0x14c 0x51c 0x8a4 0x3 0x1
-#define MX6DL_PAD_EIM_D18__IPU1_DI1_D0_CS          0x14c 0x51c 0x000 0x4 0x0
-#define MX6DL_PAD_EIM_D18__GPIO3_IO18              0x14c 0x51c 0x000 0x5 0x0
-#define MX6DL_PAD_EIM_D18__I2C3_SDA                0x14c 0x51c 0x87c 0x6 0x0
-#define MX6DL_PAD_EIM_D18__EPDC_VCOM1              0x14c 0x51c 0x000 0x8 0x0
-#define MX6DL_PAD_EIM_D19__EIM_DATA19              0x150 0x520 0x000 0x0 0x0
-#define MX6DL_PAD_EIM_D19__ECSPI1_SS1              0x150 0x520 0x7e8 0x1 0x1
-#define MX6DL_PAD_EIM_D19__IPU1_DI0_PIN08          0x150 0x520 0x000 0x2 0x0
-#define MX6DL_PAD_EIM_D19__IPU1_CSI1_DATA16        0x150 0x520 0x8a0 0x3 0x1
-#define MX6DL_PAD_EIM_D19__UART1_CTS_B             0x150 0x520 0x000 0x4 0x0
-#define MX6DL_PAD_EIM_D19__UART1_RTS_B             0x150 0x520 0x8f8 0x4 0x0
-#define MX6DL_PAD_EIM_D19__GPIO3_IO19              0x150 0x520 0x000 0x5 0x0
-#define MX6DL_PAD_EIM_D19__EPIT1_OUT               0x150 0x520 0x000 0x6 0x0
-#define MX6DL_PAD_EIM_D19__EPDC_DATA12             0x150 0x520 0x000 0x8 0x0
-#define MX6DL_PAD_EIM_D20__EIM_DATA20              0x154 0x524 0x000 0x0 0x0
-#define MX6DL_PAD_EIM_D20__ECSPI4_SS0              0x154 0x524 0x808 0x1 0x0
-#define MX6DL_PAD_EIM_D20__IPU1_DI0_PIN16          0x154 0x524 0x000 0x2 0x0
-#define MX6DL_PAD_EIM_D20__IPU1_CSI1_DATA15        0x154 0x524 0x89c 0x3 0x1
-#define MX6DL_PAD_EIM_D20__UART1_RTS_B             0x154 0x524 0x8f8 0x4 0x1
-#define MX6DL_PAD_EIM_D20__UART1_CTS_B             0x154 0x524 0x000 0x4 0x0
-#define MX6DL_PAD_EIM_D20__GPIO3_IO20              0x154 0x524 0x000 0x5 0x0
-#define MX6DL_PAD_EIM_D20__EPIT2_OUT               0x154 0x524 0x000 0x6 0x0
-#define MX6DL_PAD_EIM_D21__EIM_DATA21              0x158 0x528 0x000 0x0 0x0
-#define MX6DL_PAD_EIM_D21__ECSPI4_SCLK             0x158 0x528 0x000 0x1 0x0
-#define MX6DL_PAD_EIM_D21__IPU1_DI0_PIN17          0x158 0x528 0x000 0x2 0x0
-#define MX6DL_PAD_EIM_D21__IPU1_CSI1_DATA11        0x158 0x528 0x88c 0x3 0x0
-#define MX6DL_PAD_EIM_D21__USB_OTG_OC              0x158 0x528 0x920 0x4 0x0
-#define MX6DL_PAD_EIM_D21__GPIO3_IO21              0x158 0x528 0x000 0x5 0x0
-#define MX6DL_PAD_EIM_D21__I2C1_SCL                0x158 0x528 0x868 0x6 0x1
-#define MX6DL_PAD_EIM_D21__SPDIF_IN                0x158 0x528 0x8f0 0x7 0x0
-#define MX6DL_PAD_EIM_D22__EIM_DATA22              0x15c 0x52c 0x000 0x0 0x0
-#define MX6DL_PAD_EIM_D22__ECSPI4_MISO             0x15c 0x52c 0x000 0x1 0x0
-#define MX6DL_PAD_EIM_D22__IPU1_DI0_PIN01          0x15c 0x52c 0x000 0x2 0x0
-#define MX6DL_PAD_EIM_D22__IPU1_CSI1_DATA10        0x15c 0x52c 0x888 0x3 0x0
-#define MX6DL_PAD_EIM_D22__USB_OTG_PWR             0x15c 0x52c 0x000 0x4 0x0
-#define MX6DL_PAD_EIM_D22__GPIO3_IO22              0x15c 0x52c 0x000 0x5 0x0
-#define MX6DL_PAD_EIM_D22__SPDIF_OUT               0x15c 0x52c 0x000 0x6 0x0
-#define MX6DL_PAD_EIM_D22__EPDC_SDCE6              0x15c 0x52c 0x000 0x8 0x0
-#define MX6DL_PAD_EIM_D23__EIM_DATA23              0x160 0x530 0x000 0x0 0x0
-#define MX6DL_PAD_EIM_D23__IPU1_DI0_D0_CS          0x160 0x530 0x000 0x1 0x0
-#define MX6DL_PAD_EIM_D23__UART3_CTS_B             0x160 0x530 0x000 0x2 0x0
-#define MX6DL_PAD_EIM_D23__UART3_RTS_B             0x160 0x530 0x908 0x2 0x0
-#define MX6DL_PAD_EIM_D23__UART1_DCD_B             0x160 0x530 0x000 0x3 0x0
-#define MX6DL_PAD_EIM_D23__IPU1_CSI1_DATA_EN       0x160 0x530 0x8b0 0x4 0x0
-#define MX6DL_PAD_EIM_D23__GPIO3_IO23              0x160 0x530 0x000 0x5 0x0
-#define MX6DL_PAD_EIM_D23__IPU1_DI1_PIN02          0x160 0x530 0x000 0x6 0x0
-#define MX6DL_PAD_EIM_D23__IPU1_DI1_PIN14          0x160 0x530 0x000 0x7 0x0
-#define MX6DL_PAD_EIM_D23__EPDC_DATA11             0x160 0x530 0x000 0x8 0x0
-#define MX6DL_PAD_EIM_D24__EIM_DATA24              0x164 0x534 0x000 0x0 0x0
-#define MX6DL_PAD_EIM_D24__ECSPI4_SS2              0x164 0x534 0x000 0x1 0x0
-#define MX6DL_PAD_EIM_D24__UART3_TX_DATA           0x164 0x534 0x000 0x2 0x0
-#define MX6DL_PAD_EIM_D24__UART3_RX_DATA           0x164 0x534 0x90c 0x2 0x0
-#define MX6DL_PAD_EIM_D24__ECSPI1_SS2              0x164 0x534 0x7ec 0x3 0x0
-#define MX6DL_PAD_EIM_D24__ECSPI2_SS2              0x164 0x534 0x000 0x4 0x0
-#define MX6DL_PAD_EIM_D24__GPIO3_IO24              0x164 0x534 0x000 0x5 0x0
-#define MX6DL_PAD_EIM_D24__AUD5_RXFS               0x164 0x534 0x7bc 0x6 0x1
-#define MX6DL_PAD_EIM_D24__UART1_DTR_B             0x164 0x534 0x000 0x7 0x0
-#define MX6DL_PAD_EIM_D24__EPDC_SDCE7              0x164 0x534 0x000 0x8 0x0
-#define MX6DL_PAD_EIM_D25__EIM_DATA25              0x168 0x538 0x000 0x0 0x0
-#define MX6DL_PAD_EIM_D25__ECSPI4_SS3              0x168 0x538 0x000 0x1 0x0
-#define MX6DL_PAD_EIM_D25__UART3_RX_DATA           0x168 0x538 0x90c 0x2 0x1
-#define MX6DL_PAD_EIM_D25__UART3_TX_DATA           0x168 0x538 0x000 0x2 0x0
-#define MX6DL_PAD_EIM_D25__ECSPI1_SS3              0x168 0x538 0x7f0 0x3 0x0
-#define MX6DL_PAD_EIM_D25__ECSPI2_SS3              0x168 0x538 0x000 0x4 0x0
-#define MX6DL_PAD_EIM_D25__GPIO3_IO25              0x168 0x538 0x000 0x5 0x0
-#define MX6DL_PAD_EIM_D25__AUD5_RXC                0x168 0x538 0x7b8 0x6 0x1
-#define MX6DL_PAD_EIM_D25__UART1_DSR_B             0x168 0x538 0x000 0x7 0x0
-#define MX6DL_PAD_EIM_D25__EPDC_SDCE8              0x168 0x538 0x000 0x8 0x0
-#define MX6DL_PAD_EIM_D26__EIM_DATA26              0x16c 0x53c 0x000 0x0 0x0
-#define MX6DL_PAD_EIM_D26__IPU1_DI1_PIN11          0x16c 0x53c 0x000 0x1 0x0
-#define MX6DL_PAD_EIM_D26__IPU1_CSI0_DATA01        0x16c 0x53c 0x000 0x2 0x0
-#define MX6DL_PAD_EIM_D26__IPU1_CSI1_DATA14        0x16c 0x53c 0x898 0x3 0x1
-#define MX6DL_PAD_EIM_D26__UART2_TX_DATA           0x16c 0x53c 0x000 0x4 0x0
-#define MX6DL_PAD_EIM_D26__UART2_RX_DATA           0x16c 0x53c 0x904 0x4 0x0
-#define MX6DL_PAD_EIM_D26__GPIO3_IO26              0x16c 0x53c 0x000 0x5 0x0
-#define MX6DL_PAD_EIM_D26__IPU1_SISG2              0x16c 0x53c 0x000 0x6 0x0
-#define MX6DL_PAD_EIM_D26__IPU1_DISP1_DATA22       0x16c 0x53c 0x000 0x7 0x0
-#define MX6DL_PAD_EIM_D26__EPDC_SDOED              0x16c 0x53c 0x000 0x8 0x0
-#define MX6DL_PAD_EIM_D27__EIM_DATA27              0x170 0x540 0x000 0x0 0x0
-#define MX6DL_PAD_EIM_D27__IPU1_DI1_PIN13          0x170 0x540 0x000 0x1 0x0
-#define MX6DL_PAD_EIM_D27__IPU1_CSI0_DATA00        0x170 0x540 0x000 0x2 0x0
-#define MX6DL_PAD_EIM_D27__IPU1_CSI1_DATA13        0x170 0x540 0x894 0x3 0x1
-#define MX6DL_PAD_EIM_D27__UART2_RX_DATA           0x170 0x540 0x904 0x4 0x1
-#define MX6DL_PAD_EIM_D27__UART2_TX_DATA           0x170 0x540 0x000 0x4 0x0
-#define MX6DL_PAD_EIM_D27__GPIO3_IO27              0x170 0x540 0x000 0x5 0x0
-#define MX6DL_PAD_EIM_D27__IPU1_SISG3              0x170 0x540 0x000 0x6 0x0
-#define MX6DL_PAD_EIM_D27__IPU1_DISP1_DATA23       0x170 0x540 0x000 0x7 0x0
-#define MX6DL_PAD_EIM_D27__EPDC_SDOE               0x170 0x540 0x000 0x8 0x0
-#define MX6DL_PAD_EIM_D28__EIM_DATA28              0x174 0x544 0x000 0x0 0x0
-#define MX6DL_PAD_EIM_D28__I2C1_SDA                0x174 0x544 0x86c 0x1 0x1
-#define MX6DL_PAD_EIM_D28__ECSPI4_MOSI             0x174 0x544 0x000 0x2 0x0
-#define MX6DL_PAD_EIM_D28__IPU1_CSI1_DATA12        0x174 0x544 0x890 0x3 0x1
-#define MX6DL_PAD_EIM_D28__UART2_CTS_B             0x174 0x544 0x000 0x4 0x0
-#define MX6DL_PAD_EIM_D28__UART2_RTS_B             0x174 0x544 0x900 0x4 0x0
-#define MX6DL_PAD_EIM_D28__GPIO3_IO28              0x174 0x544 0x000 0x5 0x0
-#define MX6DL_PAD_EIM_D28__IPU1_EXT_TRIG           0x174 0x544 0x000 0x6 0x0
-#define MX6DL_PAD_EIM_D28__IPU1_DI0_PIN13          0x174 0x544 0x000 0x7 0x0
-#define MX6DL_PAD_EIM_D28__EPDC_PWR_CTRL3          0x174 0x544 0x000 0x8 0x0
-#define MX6DL_PAD_EIM_D29__EIM_DATA29              0x178 0x548 0x000 0x0 0x0
-#define MX6DL_PAD_EIM_D29__IPU1_DI1_PIN15          0x178 0x548 0x000 0x1 0x0
-#define MX6DL_PAD_EIM_D29__ECSPI4_SS0              0x178 0x548 0x808 0x2 0x1
-#define MX6DL_PAD_EIM_D29__UART2_RTS_B             0x178 0x548 0x900 0x4 0x1
-#define MX6DL_PAD_EIM_D29__UART2_CTS_B             0x178 0x548 0x000 0x4 0x0
-#define MX6DL_PAD_EIM_D29__GPIO3_IO29              0x178 0x548 0x000 0x5 0x0
-#define MX6DL_PAD_EIM_D29__IPU1_CSI1_VSYNC         0x178 0x548 0x8bc 0x6 0x0
-#define MX6DL_PAD_EIM_D29__IPU1_DI0_PIN14          0x178 0x548 0x000 0x7 0x0
-#define MX6DL_PAD_EIM_D29__EPDC_PWR_WAKE           0x178 0x548 0x000 0x8 0x0
-#define MX6DL_PAD_EIM_D30__EIM_DATA30              0x17c 0x54c 0x000 0x0 0x0
-#define MX6DL_PAD_EIM_D30__IPU1_DISP1_DATA21       0x17c 0x54c 0x000 0x1 0x0
-#define MX6DL_PAD_EIM_D30__IPU1_DI0_PIN11          0x17c 0x54c 0x000 0x2 0x0
-#define MX6DL_PAD_EIM_D30__IPU1_CSI0_DATA03        0x17c 0x54c 0x000 0x3 0x0
-#define MX6DL_PAD_EIM_D30__UART3_CTS_B             0x17c 0x54c 0x000 0x4 0x0
-#define MX6DL_PAD_EIM_D30__UART3_RTS_B             0x17c 0x54c 0x908 0x4 0x1
-#define MX6DL_PAD_EIM_D30__GPIO3_IO30              0x17c 0x54c 0x000 0x5 0x0
-#define MX6DL_PAD_EIM_D30__USB_H1_OC               0x17c 0x54c 0x924 0x6 0x0
-#define MX6DL_PAD_EIM_D30__EPDC_SDOEZ              0x17c 0x54c 0x000 0x8 0x0
-#define MX6DL_PAD_EIM_D31__EIM_DATA31              0x180 0x550 0x000 0x0 0x0
-#define MX6DL_PAD_EIM_D31__IPU1_DISP1_DATA20       0x180 0x550 0x000 0x1 0x0
-#define MX6DL_PAD_EIM_D31__IPU1_DI0_PIN12          0x180 0x550 0x000 0x2 0x0
-#define MX6DL_PAD_EIM_D31__IPU1_CSI0_DATA02        0x180 0x550 0x000 0x3 0x0
-#define MX6DL_PAD_EIM_D31__UART3_RTS_B             0x180 0x550 0x908 0x4 0x2
-#define MX6DL_PAD_EIM_D31__UART3_CTS_B             0x180 0x550 0x000 0x4 0x0
-#define MX6DL_PAD_EIM_D31__GPIO3_IO31              0x180 0x550 0x000 0x5 0x0
-#define MX6DL_PAD_EIM_D31__USB_H1_PWR              0x180 0x550 0x000 0x6 0x0
-#define MX6DL_PAD_EIM_D31__EPDC_SDCLK_P            0x180 0x550 0x000 0x8 0x0
-#define MX6DL_PAD_EIM_D31__EIM_ACLK_FREERUN        0x180 0x550 0x000 0x9 0x0
-#define MX6DL_PAD_EIM_DA0__EIM_AD00                0x184 0x554 0x000 0x0 0x0
-#define MX6DL_PAD_EIM_DA0__IPU1_DISP1_DATA09       0x184 0x554 0x000 0x1 0x0
-#define MX6DL_PAD_EIM_DA0__IPU1_CSI1_DATA09        0x184 0x554 0x000 0x2 0x0
-#define MX6DL_PAD_EIM_DA0__GPIO3_IO00              0x184 0x554 0x000 0x5 0x0
-#define MX6DL_PAD_EIM_DA0__SRC_BOOT_CFG00          0x184 0x554 0x000 0x7 0x0
-#define MX6DL_PAD_EIM_DA0__EPDC_SDCLK_N            0x184 0x554 0x000 0x8 0x0
-#define MX6DL_PAD_EIM_DA1__EIM_AD01                0x188 0x558 0x000 0x0 0x0
-#define MX6DL_PAD_EIM_DA1__IPU1_DISP1_DATA08       0x188 0x558 0x000 0x1 0x0
-#define MX6DL_PAD_EIM_DA1__IPU1_CSI1_DATA08        0x188 0x558 0x000 0x2 0x0
-#define MX6DL_PAD_EIM_DA1__GPIO3_IO01              0x188 0x558 0x000 0x5 0x0
-#define MX6DL_PAD_EIM_DA1__SRC_BOOT_CFG01          0x188 0x558 0x000 0x7 0x0
-#define MX6DL_PAD_EIM_DA1__EPDC_SDLE               0x188 0x558 0x000 0x8 0x0
-#define MX6DL_PAD_EIM_DA10__EIM_AD10               0x18c 0x55c 0x000 0x0 0x0
-#define MX6DL_PAD_EIM_DA10__IPU1_DI1_PIN15         0x18c 0x55c 0x000 0x1 0x0
-#define MX6DL_PAD_EIM_DA10__IPU1_CSI1_DATA_EN      0x18c 0x55c 0x8b0 0x2 0x1
-#define MX6DL_PAD_EIM_DA10__GPIO3_IO10             0x18c 0x55c 0x000 0x5 0x0
-#define MX6DL_PAD_EIM_DA10__SRC_BOOT_CFG10         0x18c 0x55c 0x000 0x7 0x0
-#define MX6DL_PAD_EIM_DA10__EPDC_DATA01            0x18c 0x55c 0x000 0x8 0x0
-#define MX6DL_PAD_EIM_DA11__EIM_AD11               0x190 0x560 0x000 0x0 0x0
-#define MX6DL_PAD_EIM_DA11__IPU1_DI1_PIN02         0x190 0x560 0x000 0x1 0x0
-#define MX6DL_PAD_EIM_DA11__IPU1_CSI1_HSYNC        0x190 0x560 0x8b4 0x2 0x0
-#define MX6DL_PAD_EIM_DA11__GPIO3_IO11             0x190 0x560 0x000 0x5 0x0
-#define MX6DL_PAD_EIM_DA11__SRC_BOOT_CFG11         0x190 0x560 0x000 0x7 0x0
-#define MX6DL_PAD_EIM_DA11__EPDC_DATA03            0x190 0x560 0x000 0x8 0x0
-#define MX6DL_PAD_EIM_DA12__EIM_AD12               0x194 0x564 0x000 0x0 0x0
-#define MX6DL_PAD_EIM_DA12__IPU1_DI1_PIN03         0x194 0x564 0x000 0x1 0x0
-#define MX6DL_PAD_EIM_DA12__IPU1_CSI1_VSYNC        0x194 0x564 0x8bc 0x2 0x1
-#define MX6DL_PAD_EIM_DA12__GPIO3_IO12             0x194 0x564 0x000 0x5 0x0
-#define MX6DL_PAD_EIM_DA12__SRC_BOOT_CFG12         0x194 0x564 0x000 0x7 0x0
-#define MX6DL_PAD_EIM_DA12__EPDC_DATA02            0x194 0x564 0x000 0x8 0x0
-#define MX6DL_PAD_EIM_DA13__EIM_AD13               0x198 0x568 0x000 0x0 0x0
-#define MX6DL_PAD_EIM_DA13__IPU1_DI1_D0_CS         0x198 0x568 0x000 0x1 0x0
-#define MX6DL_PAD_EIM_DA13__GPIO3_IO13             0x198 0x568 0x000 0x5 0x0
-#define MX6DL_PAD_EIM_DA13__SRC_BOOT_CFG13         0x198 0x568 0x000 0x7 0x0
-#define MX6DL_PAD_EIM_DA13__EPDC_DATA13            0x198 0x568 0x000 0x8 0x0
-#define MX6DL_PAD_EIM_DA14__EIM_AD14               0x19c 0x56c 0x000 0x0 0x0
-#define MX6DL_PAD_EIM_DA14__IPU1_DI1_D1_CS         0x19c 0x56c 0x000 0x1 0x0
-#define MX6DL_PAD_EIM_DA14__GPIO3_IO14             0x19c 0x56c 0x000 0x5 0x0
-#define MX6DL_PAD_EIM_DA14__SRC_BOOT_CFG14         0x19c 0x56c 0x000 0x7 0x0
-#define MX6DL_PAD_EIM_DA14__EPDC_DATA14            0x19c 0x56c 0x000 0x8 0x0
-#define MX6DL_PAD_EIM_DA15__EIM_AD15               0x1a0 0x570 0x000 0x0 0x0
-#define MX6DL_PAD_EIM_DA15__IPU1_DI1_PIN01         0x1a0 0x570 0x000 0x1 0x0
-#define MX6DL_PAD_EIM_DA15__IPU1_DI1_PIN04         0x1a0 0x570 0x000 0x2 0x0
-#define MX6DL_PAD_EIM_DA15__GPIO3_IO15             0x1a0 0x570 0x000 0x5 0x0
-#define MX6DL_PAD_EIM_DA15__SRC_BOOT_CFG15         0x1a0 0x570 0x000 0x7 0x0
-#define MX6DL_PAD_EIM_DA15__EPDC_DATA09            0x1a0 0x570 0x000 0x8 0x0
-#define MX6DL_PAD_EIM_DA2__EIM_AD02                0x1a4 0x574 0x000 0x0 0x0
-#define MX6DL_PAD_EIM_DA2__IPU1_DISP1_DATA07       0x1a4 0x574 0x000 0x1 0x0
-#define MX6DL_PAD_EIM_DA2__IPU1_CSI1_DATA07        0x1a4 0x574 0x000 0x2 0x0
-#define MX6DL_PAD_EIM_DA2__GPIO3_IO02              0x1a4 0x574 0x000 0x5 0x0
-#define MX6DL_PAD_EIM_DA2__SRC_BOOT_CFG02          0x1a4 0x574 0x000 0x7 0x0
-#define MX6DL_PAD_EIM_DA2__EPDC_BDR0               0x1a4 0x574 0x000 0x8 0x0
-#define MX6DL_PAD_EIM_DA3__EIM_AD03                0x1a8 0x578 0x000 0x0 0x0
-#define MX6DL_PAD_EIM_DA3__IPU1_DISP1_DATA06       0x1a8 0x578 0x000 0x1 0x0
-#define MX6DL_PAD_EIM_DA3__IPU1_CSI1_DATA06        0x1a8 0x578 0x000 0x2 0x0
-#define MX6DL_PAD_EIM_DA3__GPIO3_IO03              0x1a8 0x578 0x000 0x5 0x0
-#define MX6DL_PAD_EIM_DA3__SRC_BOOT_CFG03          0x1a8 0x578 0x000 0x7 0x0
-#define MX6DL_PAD_EIM_DA3__EPDC_BDR1               0x1a8 0x578 0x000 0x8 0x0
-#define MX6DL_PAD_EIM_DA4__EIM_AD04                0x1ac 0x57c 0x000 0x0 0x0
-#define MX6DL_PAD_EIM_DA4__IPU1_DISP1_DATA05       0x1ac 0x57c 0x000 0x1 0x0
-#define MX6DL_PAD_EIM_DA4__IPU1_CSI1_DATA05        0x1ac 0x57c 0x000 0x2 0x0
-#define MX6DL_PAD_EIM_DA4__GPIO3_IO04              0x1ac 0x57c 0x000 0x5 0x0
-#define MX6DL_PAD_EIM_DA4__SRC_BOOT_CFG04          0x1ac 0x57c 0x000 0x7 0x0
-#define MX6DL_PAD_EIM_DA4__EPDC_SDCE0              0x1ac 0x57c 0x000 0x8 0x0
-#define MX6DL_PAD_EIM_DA5__EIM_AD05                0x1b0 0x580 0x000 0x0 0x0
-#define MX6DL_PAD_EIM_DA5__IPU1_DISP1_DATA04       0x1b0 0x580 0x000 0x1 0x0
-#define MX6DL_PAD_EIM_DA5__IPU1_CSI1_DATA04        0x1b0 0x580 0x000 0x2 0x0
-#define MX6DL_PAD_EIM_DA5__GPIO3_IO05              0x1b0 0x580 0x000 0x5 0x0
-#define MX6DL_PAD_EIM_DA5__SRC_BOOT_CFG05          0x1b0 0x580 0x000 0x7 0x0
-#define MX6DL_PAD_EIM_DA5__EPDC_SDCE1              0x1b0 0x580 0x000 0x8 0x0
-#define MX6DL_PAD_EIM_DA6__EIM_AD06                0x1b4 0x584 0x000 0x0 0x0
-#define MX6DL_PAD_EIM_DA6__IPU1_DISP1_DATA03       0x1b4 0x584 0x000 0x1 0x0
-#define MX6DL_PAD_EIM_DA6__IPU1_CSI1_DATA03        0x1b4 0x584 0x000 0x2 0x0
-#define MX6DL_PAD_EIM_DA6__GPIO3_IO06              0x1b4 0x584 0x000 0x5 0x0
-#define MX6DL_PAD_EIM_DA6__SRC_BOOT_CFG06          0x1b4 0x584 0x000 0x7 0x0
-#define MX6DL_PAD_EIM_DA6__EPDC_SDCE2              0x1b4 0x584 0x000 0x8 0x0
-#define MX6DL_PAD_EIM_DA7__EIM_AD07                0x1b8 0x588 0x000 0x0 0x0
-#define MX6DL_PAD_EIM_DA7__IPU1_DISP1_DATA02       0x1b8 0x588 0x000 0x1 0x0
-#define MX6DL_PAD_EIM_DA7__IPU1_CSI1_DATA02        0x1b8 0x588 0x000 0x2 0x0
-#define MX6DL_PAD_EIM_DA7__GPIO3_IO07              0x1b8 0x588 0x000 0x5 0x0
-#define MX6DL_PAD_EIM_DA7__SRC_BOOT_CFG07          0x1b8 0x588 0x000 0x7 0x0
-#define MX6DL_PAD_EIM_DA7__EPDC_SDCE3              0x1b8 0x588 0x000 0x8 0x0
-#define MX6DL_PAD_EIM_DA8__EIM_AD08                0x1bc 0x58c 0x000 0x0 0x0
-#define MX6DL_PAD_EIM_DA8__IPU1_DISP1_DATA01       0x1bc 0x58c 0x000 0x1 0x0
-#define MX6DL_PAD_EIM_DA8__IPU1_CSI1_DATA01        0x1bc 0x58c 0x000 0x2 0x0
-#define MX6DL_PAD_EIM_DA8__GPIO3_IO08              0x1bc 0x58c 0x000 0x5 0x0
-#define MX6DL_PAD_EIM_DA8__SRC_BOOT_CFG08          0x1bc 0x58c 0x000 0x7 0x0
-#define MX6DL_PAD_EIM_DA8__EPDC_SDCE4              0x1bc 0x58c 0x000 0x8 0x0
-#define MX6DL_PAD_EIM_DA9__EIM_AD09                0x1c0 0x590 0x000 0x0 0x0
-#define MX6DL_PAD_EIM_DA9__IPU1_DISP1_DATA00       0x1c0 0x590 0x000 0x1 0x0
-#define MX6DL_PAD_EIM_DA9__IPU1_CSI1_DATA00        0x1c0 0x590 0x000 0x2 0x0
-#define MX6DL_PAD_EIM_DA9__GPIO3_IO09              0x1c0 0x590 0x000 0x5 0x0
-#define MX6DL_PAD_EIM_DA9__SRC_BOOT_CFG09          0x1c0 0x590 0x000 0x7 0x0
-#define MX6DL_PAD_EIM_DA9__EPDC_SDCE5              0x1c0 0x590 0x000 0x8 0x0
-#define MX6DL_PAD_EIM_EB0__EIM_EB0_B               0x1c4 0x594 0x000 0x0 0x0
-#define MX6DL_PAD_EIM_EB0__IPU1_DISP1_DATA11       0x1c4 0x594 0x000 0x1 0x0
-#define MX6DL_PAD_EIM_EB0__IPU1_CSI1_DATA11        0x1c4 0x594 0x88c 0x2 0x1
-#define MX6DL_PAD_EIM_EB0__CCM_PMIC_READY          0x1c4 0x594 0x7d4 0x4 0x0
-#define MX6DL_PAD_EIM_EB0__GPIO2_IO28              0x1c4 0x594 0x000 0x5 0x0
-#define MX6DL_PAD_EIM_EB0__SRC_BOOT_CFG27          0x1c4 0x594 0x000 0x7 0x0
-#define MX6DL_PAD_EIM_EB0__EPDC_PWR_COM            0x1c4 0x594 0x000 0x8 0x0
-#define MX6DL_PAD_EIM_EB1__EIM_EB1_B               0x1c8 0x598 0x000 0x0 0x0
-#define MX6DL_PAD_EIM_EB1__IPU1_DISP1_DATA10       0x1c8 0x598 0x000 0x1 0x0
-#define MX6DL_PAD_EIM_EB1__IPU1_CSI1_DATA10        0x1c8 0x598 0x888 0x2 0x1
-#define MX6DL_PAD_EIM_EB1__GPIO2_IO29              0x1c8 0x598 0x000 0x5 0x0
-#define MX6DL_PAD_EIM_EB1__SRC_BOOT_CFG28          0x1c8 0x598 0x000 0x7 0x0
-#define MX6DL_PAD_EIM_EB1__EPDC_SDSHR              0x1c8 0x598 0x000 0x8 0x0
-#define MX6DL_PAD_EIM_EB2__EIM_EB2_B               0x1cc 0x59c 0x000 0x0 0x0
-#define MX6DL_PAD_EIM_EB2__ECSPI1_SS0              0x1cc 0x59c 0x7e4 0x1 0x2
-#define MX6DL_PAD_EIM_EB2__IPU1_CSI1_DATA19        0x1cc 0x59c 0x8ac 0x3 0x1
-#define MX6DL_PAD_EIM_EB2__HDMI_TX_DDC_SCL         0x1cc 0x59c 0x860 0x4 0x0
-#define MX6DL_PAD_EIM_EB2__GPIO2_IO30              0x1cc 0x59c 0x000 0x5 0x0
-#define MX6DL_PAD_EIM_EB2__I2C2_SCL                0x1cc 0x59c 0x870 0x6 0x0
-#define MX6DL_PAD_EIM_EB2__SRC_BOOT_CFG30          0x1cc 0x59c 0x000 0x7 0x0
-#define MX6DL_PAD_EIM_EB2__EPDC_DATA05             0x1cc 0x59c 0x000 0x8 0x0
-#define MX6DL_PAD_EIM_EB3__EIM_EB3_B               0x1d0 0x5a0 0x000 0x0 0x0
-#define MX6DL_PAD_EIM_EB3__ECSPI4_RDY              0x1d0 0x5a0 0x000 0x1 0x0
-#define MX6DL_PAD_EIM_EB3__UART3_RTS_B             0x1d0 0x5a0 0x908 0x2 0x3
-#define MX6DL_PAD_EIM_EB3__UART3_CTS_B             0x1d0 0x5a0 0x000 0x2 0x0
-#define MX6DL_PAD_EIM_EB3__UART1_RI_B              0x1d0 0x5a0 0x000 0x3 0x0
-#define MX6DL_PAD_EIM_EB3__IPU1_CSI1_HSYNC         0x1d0 0x5a0 0x8b4 0x4 0x1
-#define MX6DL_PAD_EIM_EB3__GPIO2_IO31              0x1d0 0x5a0 0x000 0x5 0x0
-#define MX6DL_PAD_EIM_EB3__IPU1_DI1_PIN03          0x1d0 0x5a0 0x000 0x6 0x0
-#define MX6DL_PAD_EIM_EB3__SRC_BOOT_CFG31          0x1d0 0x5a0 0x000 0x7 0x0
-#define MX6DL_PAD_EIM_EB3__EPDC_SDCE0              0x1d0 0x5a0 0x000 0x8 0x0
-#define MX6DL_PAD_EIM_EB3__EIM_ACLK_FREERUN        0x1d0 0x5a0 0x000 0x9 0x0
-#define MX6DL_PAD_EIM_LBA__EIM_LBA_B               0x1d4 0x5a4 0x000 0x0 0x0
-#define MX6DL_PAD_EIM_LBA__IPU1_DI1_PIN17          0x1d4 0x5a4 0x000 0x1 0x0
-#define MX6DL_PAD_EIM_LBA__ECSPI2_SS1              0x1d4 0x5a4 0x804 0x2 0x1
-#define MX6DL_PAD_EIM_LBA__GPIO2_IO27              0x1d4 0x5a4 0x000 0x5 0x0
-#define MX6DL_PAD_EIM_LBA__SRC_BOOT_CFG26          0x1d4 0x5a4 0x000 0x7 0x0
-#define MX6DL_PAD_EIM_LBA__EPDC_DATA04             0x1d4 0x5a4 0x000 0x8 0x0
-#define MX6DL_PAD_EIM_OE__EIM_OE_B                 0x1d8 0x5a8 0x000 0x0 0x0
-#define MX6DL_PAD_EIM_OE__IPU1_DI1_PIN07           0x1d8 0x5a8 0x000 0x1 0x0
-#define MX6DL_PAD_EIM_OE__ECSPI2_MISO              0x1d8 0x5a8 0x7f8 0x2 0x2
-#define MX6DL_PAD_EIM_OE__GPIO2_IO25               0x1d8 0x5a8 0x000 0x5 0x0
-#define MX6DL_PAD_EIM_OE__EPDC_PWR_IRQ             0x1d8 0x5a8 0x000 0x8 0x0
-#define MX6DL_PAD_EIM_RW__EIM_RW                   0x1dc 0x5ac 0x000 0x0 0x0
-#define MX6DL_PAD_EIM_RW__IPU1_DI1_PIN08           0x1dc 0x5ac 0x000 0x1 0x0
-#define MX6DL_PAD_EIM_RW__ECSPI2_SS0               0x1dc 0x5ac 0x800 0x2 0x2
-#define MX6DL_PAD_EIM_RW__GPIO2_IO26               0x1dc 0x5ac 0x000 0x5 0x0
-#define MX6DL_PAD_EIM_RW__SRC_BOOT_CFG29           0x1dc 0x5ac 0x000 0x7 0x0
-#define MX6DL_PAD_EIM_RW__EPDC_DATA07              0x1dc 0x5ac 0x000 0x8 0x0
-#define MX6DL_PAD_EIM_WAIT__EIM_WAIT_B             0x1e0 0x5b0 0x000 0x0 0x0
-#define MX6DL_PAD_EIM_WAIT__EIM_DTACK_B            0x1e0 0x5b0 0x000 0x1 0x0
-#define MX6DL_PAD_EIM_WAIT__GPIO5_IO00             0x1e0 0x5b0 0x000 0x5 0x0
-#define MX6DL_PAD_EIM_WAIT__SRC_BOOT_CFG25         0x1e0 0x5b0 0x000 0x7 0x0
-#define MX6DL_PAD_ENET_CRS_DV__ENET_RX_EN          0x1e4 0x5b4 0x828 0x1 0x0
-#define MX6DL_PAD_ENET_CRS_DV__ESAI_TX_CLK         0x1e4 0x5b4 0x840 0x2 0x0
-#define MX6DL_PAD_ENET_CRS_DV__SPDIF_EXT_CLK       0x1e4 0x5b4 0x8f4 0x3 0x0
-#define MX6DL_PAD_ENET_CRS_DV__GPIO1_IO25          0x1e4 0x5b4 0x000 0x5 0x0
-#define MX6DL_PAD_ENET_MDC__MLB_DATA               0x1e8 0x5b8 0x8e0 0x0 0x0
-#define MX6DL_PAD_ENET_MDC__ENET_MDC               0x1e8 0x5b8 0x000 0x1 0x0
-#define MX6DL_PAD_ENET_MDC__ESAI_TX5_RX0           0x1e8 0x5b8 0x858 0x2 0x0
-#define MX6DL_PAD_ENET_MDC__ENET_1588_EVENT1_IN    0x1e8 0x5b8 0x000 0x4 0x0
-#define MX6DL_PAD_ENET_MDC__GPIO1_IO31             0x1e8 0x5b8 0x000 0x5 0x0
-#define MX6DL_PAD_ENET_MDIO__ENET_MDIO             0x1ec 0x5bc 0x810 0x1 0x0
-#define MX6DL_PAD_ENET_MDIO__ESAI_RX_CLK           0x1ec 0x5bc 0x83c 0x2 0x0
-#define MX6DL_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT  0x1ec 0x5bc 0x000 0x4 0x0
-#define MX6DL_PAD_ENET_MDIO__GPIO1_IO22            0x1ec 0x5bc 0x000 0x5 0x0
-#define MX6DL_PAD_ENET_MDIO__SPDIF_LOCK            0x1ec 0x5bc 0x000 0x6 0x0
-#define MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK        0x1f0 0x5c0 0x000 0x1 0x0
-#define MX6DL_PAD_ENET_REF_CLK__ESAI_RX_FS         0x1f0 0x5c0 0x82c 0x2 0x0
-#define MX6DL_PAD_ENET_REF_CLK__GPIO1_IO23         0x1f0 0x5c0 0x000 0x5 0x0
-#define MX6DL_PAD_ENET_REF_CLK__SPDIF_SR_CLK       0x1f0 0x5c0 0x000 0x6 0x0
-#define MX6DL_PAD_ENET_RX_ER__USB_OTG_ID           0x1f4 0x5c4 0x790 0x0 0x0
-#define MX6DL_PAD_ENET_RX_ER__ENET_RX_ER           0x1f4 0x5c4 0x000 0x1 0x0
-#define MX6DL_PAD_ENET_RX_ER__ESAI_RX_HF_CLK       0x1f4 0x5c4 0x834 0x2 0x0
-#define MX6DL_PAD_ENET_RX_ER__SPDIF_IN             0x1f4 0x5c4 0x8f0 0x3 0x1
-#define MX6DL_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT 0x1f4 0x5c4 0x000 0x4 0x0
-#define MX6DL_PAD_ENET_RX_ER__GPIO1_IO24           0x1f4 0x5c4 0x000 0x5 0x0
-#define MX6DL_PAD_ENET_RXD0__ENET_RX_DATA0         0x1f8 0x5c8 0x818 0x1 0x0
-#define MX6DL_PAD_ENET_RXD0__ESAI_TX_HF_CLK        0x1f8 0x5c8 0x838 0x2 0x0
-#define MX6DL_PAD_ENET_RXD0__SPDIF_OUT             0x1f8 0x5c8 0x000 0x3 0x0
-#define MX6DL_PAD_ENET_RXD0__GPIO1_IO27            0x1f8 0x5c8 0x000 0x5 0x0
-#define MX6DL_PAD_ENET_RXD1__MLB_SIG               0x1fc 0x5cc 0x8e4 0x0 0x0
-#define MX6DL_PAD_ENET_RXD1__ENET_RX_DATA1         0x1fc 0x5cc 0x81c 0x1 0x0
-#define MX6DL_PAD_ENET_RXD1__ESAI_TX_FS            0x1fc 0x5cc 0x830 0x2 0x0
-#define MX6DL_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT  0x1fc 0x5cc 0x000 0x4 0x0
-#define MX6DL_PAD_ENET_RXD1__GPIO1_IO26            0x1fc 0x5cc 0x000 0x5 0x0
-#define MX6DL_PAD_ENET_TX_EN__ENET_TX_EN           0x200 0x5d0 0x000 0x1 0x0
-#define MX6DL_PAD_ENET_TX_EN__ESAI_TX3_RX2         0x200 0x5d0 0x850 0x2 0x0
-#define MX6DL_PAD_ENET_TX_EN__GPIO1_IO28           0x200 0x5d0 0x000 0x5 0x0
-#define MX6DL_PAD_ENET_TX_EN__I2C4_SCL             0x200 0x5d0 0x880 0x9 0x0
-#define MX6DL_PAD_ENET_TXD0__ENET_TX_DATA0         0x204 0x5d4 0x000 0x1 0x0
-#define MX6DL_PAD_ENET_TXD0__ESAI_TX4_RX1          0x204 0x5d4 0x854 0x2 0x0
-#define MX6DL_PAD_ENET_TXD0__GPIO1_IO30            0x204 0x5d4 0x000 0x5 0x0
-#define MX6DL_PAD_ENET_TXD1__MLB_CLK               0x208 0x5d8 0x8dc 0x0 0x0
-#define MX6DL_PAD_ENET_TXD1__ENET_TX_DATA1         0x208 0x5d8 0x000 0x1 0x0
-#define MX6DL_PAD_ENET_TXD1__ESAI_TX2_RX3          0x208 0x5d8 0x84c 0x2 0x0
-#define MX6DL_PAD_ENET_TXD1__ENET_1588_EVENT0_IN   0x208 0x5d8 0x000 0x4 0x0
-#define MX6DL_PAD_ENET_TXD1__GPIO1_IO29            0x208 0x5d8 0x000 0x5 0x0
-#define MX6DL_PAD_ENET_TXD1__I2C4_SDA              0x208 0x5d8 0x884 0x9 0x0
-#define MX6DL_PAD_GPIO_0__CCM_CLKO1                0x20c 0x5dc 0x000 0x0 0x0
-#define MX6DL_PAD_GPIO_0__KEY_COL5                 0x20c 0x5dc 0x8c0 0x2 0x1
-#define MX6DL_PAD_GPIO_0__ASRC_EXT_CLK             0x20c 0x5dc 0x794 0x3 0x0
-#define MX6DL_PAD_GPIO_0__EPIT1_OUT                0x20c 0x5dc 0x000 0x4 0x0
-#define MX6DL_PAD_GPIO_0__GPIO1_IO00               0x20c 0x5dc 0x000 0x5 0x0
-#define MX6DL_PAD_GPIO_0__USB_H1_PWR               0x20c 0x5dc 0x000 0x6 0x0
-#define MX6DL_PAD_GPIO_0__SNVS_VIO_5               0x20c 0x5dc 0x000 0x7 0x0
-#define MX6DL_PAD_GPIO_1__ESAI_RX_CLK              0x210 0x5e0 0x83c 0x0 0x1
-#define MX6DL_PAD_GPIO_1__WDOG2_B                  0x210 0x5e0 0x000 0x1 0x0
-#define MX6DL_PAD_GPIO_1__KEY_ROW5                 0x210 0x5e0 0x8cc 0x2 0x1
-#define MX6DL_PAD_GPIO_1__USB_OTG_ID               0x210 0x5e0 0x790 0x3 0x1
-#define MX6DL_PAD_GPIO_1__PWM2_OUT                 0x210 0x5e0 0x000 0x4 0x0
-#define MX6DL_PAD_GPIO_1__GPIO1_IO01               0x210 0x5e0 0x000 0x5 0x0
-#define MX6DL_PAD_GPIO_1__SD1_CD_B                 0x210 0x5e0 0x000 0x6 0x0
-#define MX6DL_PAD_GPIO_16__ESAI_TX3_RX2            0x214 0x5e4 0x850 0x0 0x1
-#define MX6DL_PAD_GPIO_16__ENET_1588_EVENT2_IN     0x214 0x5e4 0x000 0x1 0x0
-#define MX6DL_PAD_GPIO_16__ENET_REF_CLK            0x214 0x5e4 0x80c 0x2 0x0
-#define MX6DL_PAD_GPIO_16__SD1_LCTL                0x214 0x5e4 0x000 0x3 0x0
-#define MX6DL_PAD_GPIO_16__SPDIF_IN                0x214 0x5e4 0x8f0 0x4 0x2
-#define MX6DL_PAD_GPIO_16__GPIO7_IO11              0x214 0x5e4 0x000 0x5 0x0
-#define MX6DL_PAD_GPIO_16__I2C3_SDA                0x214 0x5e4 0x87c 0x6 0x1
-#define MX6DL_PAD_GPIO_16__JTAG_DE_B               0x214 0x5e4 0x000 0x7 0x0
-#define MX6DL_PAD_GPIO_17__ESAI_TX0                0x218 0x5e8 0x844 0x0 0x0
-#define MX6DL_PAD_GPIO_17__ENET_1588_EVENT3_IN     0x218 0x5e8 0x000 0x1 0x0
-#define MX6DL_PAD_GPIO_17__CCM_PMIC_READY          0x218 0x5e8 0x7d4 0x2 0x1
-#define MX6DL_PAD_GPIO_17__SDMA_EXT_EVENT0         0x218 0x5e8 0x8e8 0x3 0x1
-#define MX6DL_PAD_GPIO_17__SPDIF_OUT               0x218 0x5e8 0x000 0x4 0x0
-#define MX6DL_PAD_GPIO_17__GPIO7_IO12              0x218 0x5e8 0x000 0x5 0x0
-#define MX6DL_PAD_GPIO_18__ESAI_TX1                0x21c 0x5ec 0x848 0x0 0x0
-#define MX6DL_PAD_GPIO_18__ENET_RX_CLK             0x21c 0x5ec 0x814 0x1 0x0
-#define MX6DL_PAD_GPIO_18__SD3_VSELECT             0x21c 0x5ec 0x000 0x2 0x0
-#define MX6DL_PAD_GPIO_18__SDMA_EXT_EVENT1         0x21c 0x5ec 0x8ec 0x3 0x1
-#define MX6DL_PAD_GPIO_18__ASRC_EXT_CLK            0x21c 0x5ec 0x794 0x4 0x1
-#define MX6DL_PAD_GPIO_18__GPIO7_IO13              0x21c 0x5ec 0x000 0x5 0x0
-#define MX6DL_PAD_GPIO_18__SNVS_VIO_5_CTL          0x21c 0x5ec 0x000 0x6 0x0
-#define MX6DL_PAD_GPIO_19__KEY_COL5                0x220 0x5f0 0x8c0 0x0 0x2
-#define MX6DL_PAD_GPIO_19__ENET_1588_EVENT0_OUT    0x220 0x5f0 0x000 0x1 0x0
-#define MX6DL_PAD_GPIO_19__SPDIF_OUT               0x220 0x5f0 0x000 0x2 0x0
-#define MX6DL_PAD_GPIO_19__CCM_CLKO1               0x220 0x5f0 0x000 0x3 0x0
-#define MX6DL_PAD_GPIO_19__ECSPI1_RDY              0x220 0x5f0 0x000 0x4 0x0
-#define MX6DL_PAD_GPIO_19__GPIO4_IO05              0x220 0x5f0 0x000 0x5 0x0
-#define MX6DL_PAD_GPIO_19__ENET_TX_ER              0x220 0x5f0 0x000 0x6 0x0
-#define MX6DL_PAD_GPIO_2__ESAI_TX_FS               0x224 0x5f4 0x830 0x0 0x1
-#define MX6DL_PAD_GPIO_2__KEY_ROW6                 0x224 0x5f4 0x8d0 0x2 0x1
-#define MX6DL_PAD_GPIO_2__GPIO1_IO02               0x224 0x5f4 0x000 0x5 0x0
-#define MX6DL_PAD_GPIO_2__SD2_WP                   0x224 0x5f4 0x000 0x6 0x0
-#define MX6DL_PAD_GPIO_2__MLB_DATA                 0x224 0x5f4 0x8e0 0x7 0x1
-#define MX6DL_PAD_GPIO_3__ESAI_RX_HF_CLK           0x228 0x5f8 0x834 0x0 0x1
-#define MX6DL_PAD_GPIO_3__I2C3_SCL                 0x228 0x5f8 0x878 0x2 0x1
-#define MX6DL_PAD_GPIO_3__XTALOSC_REF_CLK_24M      0x228 0x5f8 0x000 0x3 0x0
-#define MX6DL_PAD_GPIO_3__CCM_CLKO2                0x228 0x5f8 0x000 0x4 0x0
-#define MX6DL_PAD_GPIO_3__GPIO1_IO03               0x228 0x5f8 0x000 0x5 0x0
-#define MX6DL_PAD_GPIO_3__USB_H1_OC                0x228 0x5f8 0x924 0x6 0x1
-#define MX6DL_PAD_GPIO_3__MLB_CLK                  0x228 0x5f8 0x8dc 0x7 0x1
-#define MX6DL_PAD_GPIO_4__ESAI_TX_HF_CLK           0x22c 0x5fc 0x838 0x0 0x1
-#define MX6DL_PAD_GPIO_4__KEY_COL7                 0x22c 0x5fc 0x8c8 0x2 0x1
-#define MX6DL_PAD_GPIO_4__GPIO1_IO04               0x22c 0x5fc 0x000 0x5 0x0
-#define MX6DL_PAD_GPIO_4__SD2_CD_B                 0x22c 0x5fc 0x000 0x6 0x0
-#define MX6DL_PAD_GPIO_5__ESAI_TX2_RX3             0x230 0x600 0x84c 0x0 0x1
-#define MX6DL_PAD_GPIO_5__KEY_ROW7                 0x230 0x600 0x8d4 0x2 0x1
-#define MX6DL_PAD_GPIO_5__CCM_CLKO1                0x230 0x600 0x000 0x3 0x0
-#define MX6DL_PAD_GPIO_5__GPIO1_IO05               0x230 0x600 0x000 0x5 0x0
-#define MX6DL_PAD_GPIO_5__I2C3_SCL                 0x230 0x600 0x878 0x6 0x2
-#define MX6DL_PAD_GPIO_5__ARM_EVENTI               0x230 0x600 0x000 0x7 0x0
-#define MX6DL_PAD_GPIO_6__ESAI_TX_CLK              0x234 0x604 0x840 0x0 0x1
-#define MX6DL_PAD_GPIO_6__I2C3_SDA                 0x234 0x604 0x87c 0x2 0x2
-#define MX6DL_PAD_GPIO_6__GPIO1_IO06               0x234 0x604 0x000 0x5 0x0
-#define MX6DL_PAD_GPIO_6__SD2_LCTL                 0x234 0x604 0x000 0x6 0x0
-#define MX6DL_PAD_GPIO_6__MLB_SIG                  0x234 0x604 0x8e4 0x7 0x1
-#define MX6DL_PAD_GPIO_7__ESAI_TX4_RX1             0x238 0x608 0x854 0x0 0x1
-#define MX6DL_PAD_GPIO_7__EPIT1_OUT                0x238 0x608 0x000 0x2 0x0
-#define MX6DL_PAD_GPIO_7__FLEXCAN1_TX              0x238 0x608 0x000 0x3 0x0
-#define MX6DL_PAD_GPIO_7__UART2_TX_DATA            0x238 0x608 0x000 0x4 0x0
-#define MX6DL_PAD_GPIO_7__UART2_RX_DATA            0x238 0x608 0x904 0x4 0x2
-#define MX6DL_PAD_GPIO_7__GPIO1_IO07               0x238 0x608 0x000 0x5 0x0
-#define MX6DL_PAD_GPIO_7__SPDIF_LOCK               0x238 0x608 0x000 0x6 0x0
-#define MX6DL_PAD_GPIO_7__USB_OTG_HOST_MODE        0x238 0x608 0x000 0x7 0x0
-#define MX6DL_PAD_GPIO_7__I2C4_SCL                 0x238 0x608 0x880 0x8 0x1
-#define MX6DL_PAD_GPIO_8__ESAI_TX5_RX0             0x23c 0x60c 0x858 0x0 0x1
-#define MX6DL_PAD_GPIO_8__XTALOSC_REF_CLK_32K      0x23c 0x60c 0x000 0x1 0x0
-#define MX6DL_PAD_GPIO_8__EPIT2_OUT                0x23c 0x60c 0x000 0x2 0x0
-#define MX6DL_PAD_GPIO_8__FLEXCAN1_RX              0x23c 0x60c 0x7c8 0x3 0x0
-#define MX6DL_PAD_GPIO_8__UART2_RX_DATA            0x23c 0x60c 0x904 0x4 0x3
-#define MX6DL_PAD_GPIO_8__UART2_TX_DATA            0x23c 0x60c 0x000 0x4 0x0
-#define MX6DL_PAD_GPIO_8__GPIO1_IO08               0x23c 0x60c 0x000 0x5 0x0
-#define MX6DL_PAD_GPIO_8__SPDIF_SR_CLK             0x23c 0x60c 0x000 0x6 0x0
-#define MX6DL_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE     0x23c 0x60c 0x000 0x7 0x0
-#define MX6DL_PAD_GPIO_8__I2C4_SDA                 0x23c 0x60c 0x884 0x8 0x1
-#define MX6DL_PAD_GPIO_9__ESAI_RX_FS               0x240 0x610 0x82c 0x0 0x1
-#define MX6DL_PAD_GPIO_9__WDOG1_B                  0x240 0x610 0x000 0x1 0x0
-#define MX6DL_PAD_GPIO_9__KEY_COL6                 0x240 0x610 0x8c4 0x2 0x1
-#define MX6DL_PAD_GPIO_9__CCM_REF_EN_B             0x240 0x610 0x000 0x3 0x0
-#define MX6DL_PAD_GPIO_9__PWM1_OUT                 0x240 0x610 0x000 0x4 0x0
-#define MX6DL_PAD_GPIO_9__GPIO1_IO09               0x240 0x610 0x000 0x5 0x0
-#define MX6DL_PAD_GPIO_9__SD1_WP                   0x240 0x610 0x92c 0x6 0x1
-#define MX6DL_PAD_KEY_COL0__ECSPI1_SCLK            0x244 0x62c 0x7d8 0x0 0x3
-#define MX6DL_PAD_KEY_COL0__ENET_RX_DATA3          0x244 0x62c 0x824 0x1 0x0
-#define MX6DL_PAD_KEY_COL0__AUD5_TXC               0x244 0x62c 0x7c0 0x2 0x1
-#define MX6DL_PAD_KEY_COL0__KEY_COL0               0x244 0x62c 0x000 0x3 0x0
-#define MX6DL_PAD_KEY_COL0__UART4_TX_DATA          0x244 0x62c 0x000 0x4 0x0
-#define MX6DL_PAD_KEY_COL0__UART4_RX_DATA          0x244 0x62c 0x914 0x4 0x2
-#define MX6DL_PAD_KEY_COL0__GPIO4_IO06             0x244 0x62c 0x000 0x5 0x0
-#define MX6DL_PAD_KEY_COL0__DCIC1_OUT              0x244 0x62c 0x000 0x6 0x0
-#define MX6DL_PAD_KEY_COL1__ECSPI1_MISO            0x248 0x630 0x7dc 0x0 0x3
-#define MX6DL_PAD_KEY_COL1__ENET_MDIO              0x248 0x630 0x810 0x1 0x1
-#define MX6DL_PAD_KEY_COL1__AUD5_TXFS              0x248 0x630 0x7c4 0x2 0x1
-#define MX6DL_PAD_KEY_COL1__KEY_COL1               0x248 0x630 0x000 0x3 0x0
-#define MX6DL_PAD_KEY_COL1__UART5_TX_DATA          0x248 0x630 0x000 0x4 0x0
-#define MX6DL_PAD_KEY_COL1__UART5_RX_DATA          0x248 0x630 0x91c 0x4 0x2
-#define MX6DL_PAD_KEY_COL1__GPIO4_IO08             0x248 0x630 0x000 0x5 0x0
-#define MX6DL_PAD_KEY_COL1__SD1_VSELECT            0x248 0x630 0x000 0x6 0x0
-#define MX6DL_PAD_KEY_COL2__ECSPI1_SS1             0x24c 0x634 0x7e8 0x0 0x2
-#define MX6DL_PAD_KEY_COL2__ENET_RX_DATA2          0x24c 0x634 0x820 0x1 0x0
-#define MX6DL_PAD_KEY_COL2__FLEXCAN1_TX            0x24c 0x634 0x000 0x2 0x0
-#define MX6DL_PAD_KEY_COL2__KEY_COL2               0x24c 0x634 0x000 0x3 0x0
-#define MX6DL_PAD_KEY_COL2__ENET_MDC               0x24c 0x634 0x000 0x4 0x0
-#define MX6DL_PAD_KEY_COL2__GPIO4_IO10             0x24c 0x634 0x000 0x5 0x0
-#define MX6DL_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE    0x24c 0x634 0x000 0x6 0x0
-#define MX6DL_PAD_KEY_COL3__ECSPI1_SS3             0x250 0x638 0x7f0 0x0 0x1
-#define MX6DL_PAD_KEY_COL3__ENET_CRS               0x250 0x638 0x000 0x1 0x0
-#define MX6DL_PAD_KEY_COL3__HDMI_TX_DDC_SCL        0x250 0x638 0x860 0x2 0x1
-#define MX6DL_PAD_KEY_COL3__KEY_COL3               0x250 0x638 0x000 0x3 0x0
-#define MX6DL_PAD_KEY_COL3__I2C2_SCL               0x250 0x638 0x870 0x4 0x1
-#define MX6DL_PAD_KEY_COL3__GPIO4_IO12             0x250 0x638 0x000 0x5 0x0
-#define MX6DL_PAD_KEY_COL3__SPDIF_IN               0x250 0x638 0x8f0 0x6 0x3
-#define MX6DL_PAD_KEY_COL4__FLEXCAN2_TX            0x254 0x63c 0x000 0x0 0x0
-#define MX6DL_PAD_KEY_COL4__IPU1_SISG4             0x254 0x63c 0x000 0x1 0x0
-#define MX6DL_PAD_KEY_COL4__USB_OTG_OC             0x254 0x63c 0x920 0x2 0x1
-#define MX6DL_PAD_KEY_COL4__KEY_COL4               0x254 0x63c 0x000 0x3 0x0
-#define MX6DL_PAD_KEY_COL4__UART5_RTS_B            0x254 0x63c 0x918 0x4 0x2
-#define MX6DL_PAD_KEY_COL4__UART5_CTS_B            0x254 0x63c 0x000 0x4 0x0
-#define MX6DL_PAD_KEY_COL4__GPIO4_IO14             0x254 0x63c 0x000 0x5 0x0
-#define MX6DL_PAD_KEY_ROW0__ECSPI1_MOSI            0x258 0x640 0x7e0 0x0 0x3
-#define MX6DL_PAD_KEY_ROW0__ENET_TX_DATA3          0x258 0x640 0x000 0x1 0x0
-#define MX6DL_PAD_KEY_ROW0__AUD5_TXD               0x258 0x640 0x7b4 0x2 0x1
-#define MX6DL_PAD_KEY_ROW0__KEY_ROW0               0x258 0x640 0x000 0x3 0x0
-#define MX6DL_PAD_KEY_ROW0__UART4_RX_DATA          0x258 0x640 0x914 0x4 0x3
-#define MX6DL_PAD_KEY_ROW0__UART4_TX_DATA          0x258 0x640 0x000 0x4 0x0
-#define MX6DL_PAD_KEY_ROW0__GPIO4_IO07             0x258 0x640 0x000 0x5 0x0
-#define MX6DL_PAD_KEY_ROW0__DCIC2_OUT              0x258 0x640 0x000 0x6 0x0
-#define MX6DL_PAD_KEY_ROW1__ECSPI1_SS0             0x25c 0x644 0x7e4 0x0 0x3
-#define MX6DL_PAD_KEY_ROW1__ENET_COL               0x25c 0x644 0x000 0x1 0x0
-#define MX6DL_PAD_KEY_ROW1__AUD5_RXD               0x25c 0x644 0x7b0 0x2 0x1
-#define MX6DL_PAD_KEY_ROW1__KEY_ROW1               0x25c 0x644 0x000 0x3 0x0
-#define MX6DL_PAD_KEY_ROW1__UART5_RX_DATA          0x25c 0x644 0x91c 0x4 0x3
-#define MX6DL_PAD_KEY_ROW1__UART5_TX_DATA          0x25c 0x644 0x000 0x4 0x0
-#define MX6DL_PAD_KEY_ROW1__GPIO4_IO09             0x25c 0x644 0x000 0x5 0x0
-#define MX6DL_PAD_KEY_ROW1__SD2_VSELECT            0x25c 0x644 0x000 0x6 0x0
-#define MX6DL_PAD_KEY_ROW2__ECSPI1_SS2             0x260 0x648 0x7ec 0x0 0x1
-#define MX6DL_PAD_KEY_ROW2__ENET_TX_DATA2          0x260 0x648 0x000 0x1 0x0
-#define MX6DL_PAD_KEY_ROW2__FLEXCAN1_RX            0x260 0x648 0x7c8 0x2 0x1
-#define MX6DL_PAD_KEY_ROW2__KEY_ROW2               0x260 0x648 0x000 0x3 0x0
-#define MX6DL_PAD_KEY_ROW2__SD2_VSELECT            0x260 0x648 0x000 0x4 0x0
-#define MX6DL_PAD_KEY_ROW2__GPIO4_IO11             0x260 0x648 0x000 0x5 0x0
-#define MX6DL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE       0x260 0x648 0x85c 0x6 0x1
-#define MX6DL_PAD_KEY_ROW3__ASRC_EXT_CLK           0x264 0x64c 0x794 0x1 0x2
-#define MX6DL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA        0x264 0x64c 0x864 0x2 0x1
-#define MX6DL_PAD_KEY_ROW3__KEY_ROW3               0x264 0x64c 0x000 0x3 0x0
-#define MX6DL_PAD_KEY_ROW3__I2C2_SDA               0x264 0x64c 0x874 0x4 0x1
-#define MX6DL_PAD_KEY_ROW3__GPIO4_IO13             0x264 0x64c 0x000 0x5 0x0
-#define MX6DL_PAD_KEY_ROW3__SD1_VSELECT            0x264 0x64c 0x000 0x6 0x0
-#define MX6DL_PAD_KEY_ROW4__FLEXCAN2_RX            0x268 0x650 0x7cc 0x0 0x0
-#define MX6DL_PAD_KEY_ROW4__IPU1_SISG5             0x268 0x650 0x000 0x1 0x0
-#define MX6DL_PAD_KEY_ROW4__USB_OTG_PWR            0x268 0x650 0x000 0x2 0x0
-#define MX6DL_PAD_KEY_ROW4__KEY_ROW4               0x268 0x650 0x000 0x3 0x0
-#define MX6DL_PAD_KEY_ROW4__UART5_CTS_B            0x268 0x650 0x000 0x4 0x0
-#define MX6DL_PAD_KEY_ROW4__UART5_RTS_B            0x268 0x650 0x918 0x4 0x3
-#define MX6DL_PAD_KEY_ROW4__GPIO4_IO15             0x268 0x650 0x000 0x5 0x0
-#define MX6DL_PAD_NANDF_ALE__NAND_ALE              0x26c 0x654 0x000 0x0 0x0
-#define MX6DL_PAD_NANDF_ALE__SD4_RESET             0x26c 0x654 0x000 0x1 0x0
-#define MX6DL_PAD_NANDF_ALE__GPIO6_IO08            0x26c 0x654 0x000 0x5 0x0
-#define MX6DL_PAD_NANDF_CLE__NAND_CLE              0x270 0x658 0x000 0x0 0x0
-#define MX6DL_PAD_NANDF_CLE__GPIO6_IO07            0x270 0x658 0x000 0x5 0x0
-#define MX6DL_PAD_NANDF_CS0__NAND_CE0_B            0x274 0x65c 0x000 0x0 0x0
-#define MX6DL_PAD_NANDF_CS0__GPIO6_IO11            0x274 0x65c 0x000 0x5 0x0
-#define MX6DL_PAD_NANDF_CS1__NAND_CE1_B            0x278 0x660 0x000 0x0 0x0
-#define MX6DL_PAD_NANDF_CS1__SD4_VSELECT           0x278 0x660 0x000 0x1 0x0
-#define MX6DL_PAD_NANDF_CS1__SD3_VSELECT           0x278 0x660 0x000 0x2 0x0
-#define MX6DL_PAD_NANDF_CS1__GPIO6_IO14            0x278 0x660 0x000 0x5 0x0
-#define MX6DL_PAD_NANDF_CS2__NAND_CE2_B            0x27c 0x664 0x000 0x0 0x0
-#define MX6DL_PAD_NANDF_CS2__IPU1_SISG0            0x27c 0x664 0x000 0x1 0x0
-#define MX6DL_PAD_NANDF_CS2__ESAI_TX0              0x27c 0x664 0x844 0x2 0x1
-#define MX6DL_PAD_NANDF_CS2__EIM_CRE               0x27c 0x664 0x000 0x3 0x0
-#define MX6DL_PAD_NANDF_CS2__CCM_CLKO2             0x27c 0x664 0x000 0x4 0x0
-#define MX6DL_PAD_NANDF_CS2__GPIO6_IO15            0x27c 0x664 0x000 0x5 0x0
-#define MX6DL_PAD_NANDF_CS3__NAND_CE3_B            0x280 0x668 0x000 0x0 0x0
-#define MX6DL_PAD_NANDF_CS3__IPU1_SISG1            0x280 0x668 0x000 0x1 0x0
-#define MX6DL_PAD_NANDF_CS3__ESAI_TX1              0x280 0x668 0x848 0x2 0x1
-#define MX6DL_PAD_NANDF_CS3__EIM_ADDR26            0x280 0x668 0x000 0x3 0x0
-#define MX6DL_PAD_NANDF_CS3__GPIO6_IO16            0x280 0x668 0x000 0x5 0x0
-#define MX6DL_PAD_NANDF_CS3__I2C4_SDA              0x280 0x668 0x884 0x9 0x2
-#define MX6DL_PAD_NANDF_D0__NAND_DATA00            0x284 0x66c 0x000 0x0 0x0
-#define MX6DL_PAD_NANDF_D0__SD1_DATA4              0x284 0x66c 0x000 0x1 0x0
-#define MX6DL_PAD_NANDF_D0__GPIO2_IO00             0x284 0x66c 0x000 0x5 0x0
-#define MX6DL_PAD_NANDF_D1__NAND_DATA01            0x288 0x670 0x000 0x0 0x0
-#define MX6DL_PAD_NANDF_D1__SD1_DATA5              0x288 0x670 0x000 0x1 0x0
-#define MX6DL_PAD_NANDF_D1__GPIO2_IO01             0x288 0x670 0x000 0x5 0x0
-#define MX6DL_PAD_NANDF_D2__NAND_DATA02            0x28c 0x674 0x000 0x0 0x0
-#define MX6DL_PAD_NANDF_D2__SD1_DATA6              0x28c 0x674 0x000 0x1 0x0
-#define MX6DL_PAD_NANDF_D2__GPIO2_IO02             0x28c 0x674 0x000 0x5 0x0
-#define MX6DL_PAD_NANDF_D3__NAND_DATA03            0x290 0x678 0x000 0x0 0x0
-#define MX6DL_PAD_NANDF_D3__SD1_DATA7              0x290 0x678 0x000 0x1 0x0
-#define MX6DL_PAD_NANDF_D3__GPIO2_IO03             0x290 0x678 0x000 0x5 0x0
-#define MX6DL_PAD_NANDF_D4__NAND_DATA04            0x294 0x67c 0x000 0x0 0x0
-#define MX6DL_PAD_NANDF_D4__SD2_DATA4              0x294 0x67c 0x000 0x1 0x0
-#define MX6DL_PAD_NANDF_D4__GPIO2_IO04             0x294 0x67c 0x000 0x5 0x0
-#define MX6DL_PAD_NANDF_D5__NAND_DATA05            0x298 0x680 0x000 0x0 0x0
-#define MX6DL_PAD_NANDF_D5__SD2_DATA5              0x298 0x680 0x000 0x1 0x0
-#define MX6DL_PAD_NANDF_D5__GPIO2_IO05             0x298 0x680 0x000 0x5 0x0
-#define MX6DL_PAD_NANDF_D6__NAND_DATA06            0x29c 0x684 0x000 0x0 0x0
-#define MX6DL_PAD_NANDF_D6__SD2_DATA6              0x29c 0x684 0x000 0x1 0x0
-#define MX6DL_PAD_NANDF_D6__GPIO2_IO06             0x29c 0x684 0x000 0x5 0x0
-#define MX6DL_PAD_NANDF_D7__NAND_DATA07            0x2a0 0x688 0x000 0x0 0x0
-#define MX6DL_PAD_NANDF_D7__SD2_DATA7              0x2a0 0x688 0x000 0x1 0x0
-#define MX6DL_PAD_NANDF_D7__GPIO2_IO07             0x2a0 0x688 0x000 0x5 0x0
-#define MX6DL_PAD_NANDF_RB0__NAND_READY_B          0x2a4 0x68c 0x000 0x0 0x0
-#define MX6DL_PAD_NANDF_RB0__GPIO6_IO10            0x2a4 0x68c 0x000 0x5 0x0
-#define MX6DL_PAD_NANDF_WP_B__NAND_WP_B            0x2a8 0x690 0x000 0x0 0x0
-#define MX6DL_PAD_NANDF_WP_B__GPIO6_IO09           0x2a8 0x690 0x000 0x5 0x0
-#define MX6DL_PAD_NANDF_WP_B__I2C4_SCL             0x2a8 0x690 0x880 0x9 0x2
-#define MX6DL_PAD_RGMII_RD0__HSI_RX_READY          0x2ac 0x694 0x000 0x0 0x0
-#define MX6DL_PAD_RGMII_RD0__RGMII_RD0             0x2ac 0x694 0x818 0x1 0x1
-#define MX6DL_PAD_RGMII_RD0__GPIO6_IO25            0x2ac 0x694 0x000 0x5 0x0
-#define MX6DL_PAD_RGMII_RD1__HSI_TX_FLAG           0x2b0 0x698 0x000 0x0 0x0
-#define MX6DL_PAD_RGMII_RD1__RGMII_RD1             0x2b0 0x698 0x81c 0x1 0x1
-#define MX6DL_PAD_RGMII_RD1__GPIO6_IO27            0x2b0 0x698 0x000 0x5 0x0
-#define MX6DL_PAD_RGMII_RD2__HSI_TX_DATA           0x2b4 0x69c 0x000 0x0 0x0
-#define MX6DL_PAD_RGMII_RD2__RGMII_RD2             0x2b4 0x69c 0x820 0x1 0x1
-#define MX6DL_PAD_RGMII_RD2__GPIO6_IO28            0x2b4 0x69c 0x000 0x5 0x0
-#define MX6DL_PAD_RGMII_RD3__HSI_TX_WAKE           0x2b8 0x6a0 0x000 0x0 0x0
-#define MX6DL_PAD_RGMII_RD3__RGMII_RD3             0x2b8 0x6a0 0x824 0x1 0x1
-#define MX6DL_PAD_RGMII_RD3__GPIO6_IO29            0x2b8 0x6a0 0x000 0x5 0x0
-#define MX6DL_PAD_RGMII_RX_CTL__USB_H3_DATA        0x2bc 0x6a4 0x000 0x0 0x0
-#define MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL       0x2bc 0x6a4 0x828 0x1 0x1
-#define MX6DL_PAD_RGMII_RX_CTL__GPIO6_IO24         0x2bc 0x6a4 0x000 0x5 0x0
-#define MX6DL_PAD_RGMII_RXC__USB_H3_STROBE         0x2c0 0x6a8 0x000 0x0 0x0
-#define MX6DL_PAD_RGMII_RXC__RGMII_RXC             0x2c0 0x6a8 0x814 0x1 0x1
-#define MX6DL_PAD_RGMII_RXC__GPIO6_IO30            0x2c0 0x6a8 0x000 0x5 0x0
-#define MX6DL_PAD_RGMII_TD0__HSI_TX_READY          0x2c4 0x6ac 0x000 0x0 0x0
-#define MX6DL_PAD_RGMII_TD0__RGMII_TD0             0x2c4 0x6ac 0x000 0x1 0x0
-#define MX6DL_PAD_RGMII_TD0__GPIO6_IO20            0x2c4 0x6ac 0x000 0x5 0x0
-#define MX6DL_PAD_RGMII_TD1__HSI_RX_FLAG           0x2c8 0x6b0 0x000 0x0 0x0
-#define MX6DL_PAD_RGMII_TD1__RGMII_TD1             0x2c8 0x6b0 0x000 0x1 0x0
-#define MX6DL_PAD_RGMII_TD1__GPIO6_IO21            0x2c8 0x6b0 0x000 0x5 0x0
-#define MX6DL_PAD_RGMII_TD2__HSI_RX_DATA           0x2cc 0x6b4 0x000 0x0 0x0
-#define MX6DL_PAD_RGMII_TD2__RGMII_TD2             0x2cc 0x6b4 0x000 0x1 0x0
-#define MX6DL_PAD_RGMII_TD2__GPIO6_IO22            0x2cc 0x6b4 0x000 0x5 0x0
-#define MX6DL_PAD_RGMII_TD3__HSI_RX_WAKE           0x2d0 0x6b8 0x000 0x0 0x0
-#define MX6DL_PAD_RGMII_TD3__RGMII_TD3             0x2d0 0x6b8 0x000 0x1 0x0
-#define MX6DL_PAD_RGMII_TD3__GPIO6_IO23            0x2d0 0x6b8 0x000 0x5 0x0
-#define MX6DL_PAD_RGMII_TX_CTL__USB_H2_STROBE      0x2d4 0x6bc 0x000 0x0 0x0
-#define MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL       0x2d4 0x6bc 0x000 0x1 0x0
-#define MX6DL_PAD_RGMII_TX_CTL__GPIO6_IO26         0x2d4 0x6bc 0x000 0x5 0x0
-#define MX6DL_PAD_RGMII_TX_CTL__ENET_REF_CLK       0x2d4 0x6bc 0x80c 0x7 0x1
-#define MX6DL_PAD_RGMII_TXC__USB_H2_DATA           0x2d8 0x6c0 0x000 0x0 0x0
-#define MX6DL_PAD_RGMII_TXC__RGMII_TXC             0x2d8 0x6c0 0x000 0x1 0x0
-#define MX6DL_PAD_RGMII_TXC__SPDIF_EXT_CLK         0x2d8 0x6c0 0x8f4 0x2 0x1
-#define MX6DL_PAD_RGMII_TXC__GPIO6_IO19            0x2d8 0x6c0 0x000 0x5 0x0
-#define MX6DL_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M   0x2d8 0x6c0 0x000 0x7 0x0
-#define MX6DL_PAD_SD1_CLK__SD1_CLK                 0x2dc 0x6c4 0x928 0x0 0x1
-#define MX6DL_PAD_SD1_CLK__GPT_CLKIN               0x2dc 0x6c4 0x000 0x3 0x0
-#define MX6DL_PAD_SD1_CLK__GPIO1_IO20              0x2dc 0x6c4 0x000 0x5 0x0
-#define MX6DL_PAD_SD1_CMD__SD1_CMD                 0x2e0 0x6c8 0x000 0x0 0x0
-#define MX6DL_PAD_SD1_CMD__PWM4_OUT                0x2e0 0x6c8 0x000 0x2 0x0
-#define MX6DL_PAD_SD1_CMD__GPT_COMPARE1            0x2e0 0x6c8 0x000 0x3 0x0
-#define MX6DL_PAD_SD1_CMD__GPIO1_IO18              0x2e0 0x6c8 0x000 0x5 0x0
-#define MX6DL_PAD_SD1_DAT0__SD1_DATA0              0x2e4 0x6cc 0x000 0x0 0x0
-#define MX6DL_PAD_SD1_DAT0__GPT_CAPTURE1           0x2e4 0x6cc 0x000 0x3 0x0
-#define MX6DL_PAD_SD1_DAT0__GPIO1_IO16             0x2e4 0x6cc 0x000 0x5 0x0
-#define MX6DL_PAD_SD1_DAT1__SD1_DATA1              0x2e8 0x6d0 0x000 0x0 0x0
-#define MX6DL_PAD_SD1_DAT1__PWM3_OUT               0x2e8 0x6d0 0x000 0x2 0x0
-#define MX6DL_PAD_SD1_DAT1__GPT_CAPTURE2           0x2e8 0x6d0 0x000 0x3 0x0
-#define MX6DL_PAD_SD1_DAT1__GPIO1_IO17             0x2e8 0x6d0 0x000 0x5 0x0
-#define MX6DL_PAD_SD1_DAT2__SD1_DATA2              0x2ec 0x6d4 0x000 0x0 0x0
-#define MX6DL_PAD_SD1_DAT2__GPT_COMPARE2           0x2ec 0x6d4 0x000 0x2 0x0
-#define MX6DL_PAD_SD1_DAT2__PWM2_OUT               0x2ec 0x6d4 0x000 0x3 0x0
-#define MX6DL_PAD_SD1_DAT2__WDOG1_B                0x2ec 0x6d4 0x000 0x4 0x0
-#define MX6DL_PAD_SD1_DAT2__GPIO1_IO19             0x2ec 0x6d4 0x000 0x5 0x0
-#define MX6DL_PAD_SD1_DAT2__WDOG1_RESET_B_DEB      0x2ec 0x6d4 0x000 0x6 0x0
-#define MX6DL_PAD_SD1_DAT3__SD1_DATA3              0x2f0 0x6d8 0x000 0x0 0x0
-#define MX6DL_PAD_SD1_DAT3__GPT_COMPARE3           0x2f0 0x6d8 0x000 0x2 0x0
-#define MX6DL_PAD_SD1_DAT3__PWM1_OUT               0x2f0 0x6d8 0x000 0x3 0x0
-#define MX6DL_PAD_SD1_DAT3__WDOG2_B                0x2f0 0x6d8 0x000 0x4 0x0
-#define MX6DL_PAD_SD1_DAT3__GPIO1_IO21             0x2f0 0x6d8 0x000 0x5 0x0
-#define MX6DL_PAD_SD1_DAT3__WDOG2_RESET_B_DEB      0x2f0 0x6d8 0x000 0x6 0x0
-#define MX6DL_PAD_SD2_CLK__SD2_CLK                 0x2f4 0x6dc 0x930 0x0 0x1
-#define MX6DL_PAD_SD2_CLK__KEY_COL5                0x2f4 0x6dc 0x8c0 0x2 0x3
-#define MX6DL_PAD_SD2_CLK__AUD4_RXFS               0x2f4 0x6dc 0x7a4 0x3 0x1
-#define MX6DL_PAD_SD2_CLK__GPIO1_IO10              0x2f4 0x6dc 0x000 0x5 0x0
-#define MX6DL_PAD_SD2_CMD__SD2_CMD                 0x2f8 0x6e0 0x000 0x0 0x0
-#define MX6DL_PAD_SD2_CMD__KEY_ROW5                0x2f8 0x6e0 0x8cc 0x2 0x2
-#define MX6DL_PAD_SD2_CMD__AUD4_RXC                0x2f8 0x6e0 0x7a0 0x3 0x1
-#define MX6DL_PAD_SD2_CMD__GPIO1_IO11              0x2f8 0x6e0 0x000 0x5 0x0
-#define MX6DL_PAD_SD2_DAT0__SD2_DATA0              0x2fc 0x6e4 0x000 0x0 0x0
-#define MX6DL_PAD_SD2_DAT0__AUD4_RXD               0x2fc 0x6e4 0x798 0x3 0x1
-#define MX6DL_PAD_SD2_DAT0__KEY_ROW7               0x2fc 0x6e4 0x8d4 0x4 0x2
-#define MX6DL_PAD_SD2_DAT0__GPIO1_IO15             0x2fc 0x6e4 0x000 0x5 0x0
-#define MX6DL_PAD_SD2_DAT0__DCIC2_OUT              0x2fc 0x6e4 0x000 0x6 0x0
-#define MX6DL_PAD_SD2_DAT1__SD2_DATA1              0x300 0x6e8 0x000 0x0 0x0
-#define MX6DL_PAD_SD2_DAT1__EIM_CS2_B              0x300 0x6e8 0x000 0x2 0x0
-#define MX6DL_PAD_SD2_DAT1__AUD4_TXFS              0x300 0x6e8 0x7ac 0x3 0x1
-#define MX6DL_PAD_SD2_DAT1__KEY_COL7               0x300 0x6e8 0x8c8 0x4 0x2
-#define MX6DL_PAD_SD2_DAT1__GPIO1_IO14             0x300 0x6e8 0x000 0x5 0x0
-#define MX6DL_PAD_SD2_DAT2__SD2_DATA2              0x304 0x6ec 0x000 0x0 0x0
-#define MX6DL_PAD_SD2_DAT2__EIM_CS3_B              0x304 0x6ec 0x000 0x2 0x0
-#define MX6DL_PAD_SD2_DAT2__AUD4_TXD               0x304 0x6ec 0x79c 0x3 0x1
-#define MX6DL_PAD_SD2_DAT2__KEY_ROW6               0x304 0x6ec 0x8d0 0x4 0x2
-#define MX6DL_PAD_SD2_DAT2__GPIO1_IO13             0x304 0x6ec 0x000 0x5 0x0
-#define MX6DL_PAD_SD2_DAT3__SD2_DATA3              0x308 0x6f0 0x000 0x0 0x0
-#define MX6DL_PAD_SD2_DAT3__KEY_COL6               0x308 0x6f0 0x8c4 0x2 0x2
-#define MX6DL_PAD_SD2_DAT3__AUD4_TXC               0x308 0x6f0 0x7a8 0x3 0x1
-#define MX6DL_PAD_SD2_DAT3__GPIO1_IO12             0x308 0x6f0 0x000 0x5 0x0
-#define MX6DL_PAD_SD3_CLK__SD3_CLK                 0x30c 0x6f4 0x934 0x0 0x1
-#define MX6DL_PAD_SD3_CLK__UART2_RTS_B             0x30c 0x6f4 0x900 0x1 0x2
-#define MX6DL_PAD_SD3_CLK__UART2_CTS_B             0x30c 0x6f4 0x000 0x1 0x0
-#define MX6DL_PAD_SD3_CLK__FLEXCAN1_RX             0x30c 0x6f4 0x7c8 0x2 0x2
-#define MX6DL_PAD_SD3_CLK__GPIO7_IO03              0x30c 0x6f4 0x000 0x5 0x0
-#define MX6DL_PAD_SD3_CMD__SD3_CMD                 0x310 0x6f8 0x000 0x0 0x0
-#define MX6DL_PAD_SD3_CMD__UART2_CTS_B             0x310 0x6f8 0x000 0x1 0x0
-#define MX6DL_PAD_SD3_CMD__UART2_RTS_B             0x310 0x6f8 0x900 0x1 0x3
-#define MX6DL_PAD_SD3_CMD__FLEXCAN1_TX             0x310 0x6f8 0x000 0x2 0x0
-#define MX6DL_PAD_SD3_CMD__GPIO7_IO02              0x310 0x6f8 0x000 0x5 0x0
-#define MX6DL_PAD_SD3_DAT0__SD3_DATA0              0x314 0x6fc 0x000 0x0 0x0
-#define MX6DL_PAD_SD3_DAT0__UART1_CTS_B            0x314 0x6fc 0x000 0x1 0x0
-#define MX6DL_PAD_SD3_DAT0__UART1_RTS_B            0x314 0x6fc 0x8f8 0x1 0x2
-#define MX6DL_PAD_SD3_DAT0__FLEXCAN2_TX            0x314 0x6fc 0x000 0x2 0x0
-#define MX6DL_PAD_SD3_DAT0__GPIO7_IO04             0x314 0x6fc 0x000 0x5 0x0
-#define MX6DL_PAD_SD3_DAT1__SD3_DATA1              0x318 0x700 0x000 0x0 0x0
-#define MX6DL_PAD_SD3_DAT1__UART1_RTS_B            0x318 0x700 0x8f8 0x1 0x3
-#define MX6DL_PAD_SD3_DAT1__UART1_CTS_B            0x318 0x700 0x000 0x1 0x0
-#define MX6DL_PAD_SD3_DAT1__FLEXCAN2_RX            0x318 0x700 0x7cc 0x2 0x1
-#define MX6DL_PAD_SD3_DAT1__GPIO7_IO05             0x318 0x700 0x000 0x5 0x0
-#define MX6DL_PAD_SD3_DAT2__SD3_DATA2              0x31c 0x704 0x000 0x0 0x0
-#define MX6DL_PAD_SD3_DAT2__GPIO7_IO06             0x31c 0x704 0x000 0x5 0x0
-#define MX6DL_PAD_SD3_DAT3__SD3_DATA3              0x320 0x708 0x000 0x0 0x0
-#define MX6DL_PAD_SD3_DAT3__UART3_CTS_B            0x320 0x708 0x000 0x1 0x0
-#define MX6DL_PAD_SD3_DAT3__UART3_RTS_B            0x320 0x708 0x908 0x1 0x4
-#define MX6DL_PAD_SD3_DAT3__GPIO7_IO07             0x320 0x708 0x000 0x5 0x0
-#define MX6DL_PAD_SD3_DAT4__SD3_DATA4              0x324 0x70c 0x000 0x0 0x0
-#define MX6DL_PAD_SD3_DAT4__UART2_RX_DATA          0x324 0x70c 0x904 0x1 0x4
-#define MX6DL_PAD_SD3_DAT4__UART2_TX_DATA          0x324 0x70c 0x000 0x1 0x0
-#define MX6DL_PAD_SD3_DAT4__GPIO7_IO01             0x324 0x70c 0x000 0x5 0x0
-#define MX6DL_PAD_SD3_DAT5__SD3_DATA5              0x328 0x710 0x000 0x0 0x0
-#define MX6DL_PAD_SD3_DAT5__UART2_TX_DATA          0x328 0x710 0x000 0x1 0x0
-#define MX6DL_PAD_SD3_DAT5__UART2_RX_DATA          0x328 0x710 0x904 0x1 0x5
-#define MX6DL_PAD_SD3_DAT5__GPIO7_IO00             0x328 0x710 0x000 0x5 0x0
-#define MX6DL_PAD_SD3_DAT6__SD3_DATA6              0x32c 0x714 0x000 0x0 0x0
-#define MX6DL_PAD_SD3_DAT6__UART1_RX_DATA          0x32c 0x714 0x8fc 0x1 0x2
-#define MX6DL_PAD_SD3_DAT6__UART1_TX_DATA          0x32c 0x714 0x000 0x1 0x0
-#define MX6DL_PAD_SD3_DAT6__GPIO6_IO18             0x32c 0x714 0x000 0x5 0x0
-#define MX6DL_PAD_SD3_DAT7__SD3_DATA7              0x330 0x718 0x000 0x0 0x0
-#define MX6DL_PAD_SD3_DAT7__UART1_TX_DATA          0x330 0x718 0x000 0x1 0x0
-#define MX6DL_PAD_SD3_DAT7__UART1_RX_DATA          0x330 0x718 0x8fc 0x1 0x3
-#define MX6DL_PAD_SD3_DAT7__GPIO6_IO17             0x330 0x718 0x000 0x5 0x0
-#define MX6DL_PAD_SD3_RST__SD3_RESET               0x334 0x71c 0x000 0x0 0x0
-#define MX6DL_PAD_SD3_RST__UART3_RTS_B             0x334 0x71c 0x908 0x1 0x5
-#define MX6DL_PAD_SD3_RST__UART3_CTS_B             0x334 0x71c 0x000 0x1 0x0
-#define MX6DL_PAD_SD3_RST__GPIO7_IO08              0x334 0x71c 0x000 0x5 0x0
-#define MX6DL_PAD_SD4_CLK__SD4_CLK                 0x338 0x720 0x938 0x0 0x1
-#define MX6DL_PAD_SD4_CLK__NAND_WE_B               0x338 0x720 0x000 0x1 0x0
-#define MX6DL_PAD_SD4_CLK__UART3_RX_DATA           0x338 0x720 0x90c 0x2 0x2
-#define MX6DL_PAD_SD4_CLK__UART3_TX_DATA           0x338 0x720 0x000 0x2 0x0
-#define MX6DL_PAD_SD4_CLK__GPIO7_IO10              0x338 0x720 0x000 0x5 0x0
-#define MX6DL_PAD_SD4_CMD__SD4_CMD                 0x33c 0x724 0x000 0x0 0x0
-#define MX6DL_PAD_SD4_CMD__NAND_RE_B               0x33c 0x724 0x000 0x1 0x0
-#define MX6DL_PAD_SD4_CMD__UART3_TX_DATA           0x33c 0x724 0x000 0x2 0x0
-#define MX6DL_PAD_SD4_CMD__UART3_RX_DATA           0x33c 0x724 0x90c 0x2 0x3
-#define MX6DL_PAD_SD4_CMD__GPIO7_IO09              0x33c 0x724 0x000 0x5 0x0
-#define MX6DL_PAD_SD4_DAT0__SD4_DATA0              0x340 0x728 0x000 0x1 0x0
-#define MX6DL_PAD_SD4_DAT0__NAND_DQS               0x340 0x728 0x000 0x2 0x0
-#define MX6DL_PAD_SD4_DAT0__GPIO2_IO08             0x340 0x728 0x000 0x5 0x0
-#define MX6DL_PAD_SD4_DAT1__SD4_DATA1              0x344 0x72c 0x000 0x1 0x0
-#define MX6DL_PAD_SD4_DAT1__PWM3_OUT               0x344 0x72c 0x000 0x2 0x0
-#define MX6DL_PAD_SD4_DAT1__GPIO2_IO09             0x344 0x72c 0x000 0x5 0x0
-#define MX6DL_PAD_SD4_DAT2__SD4_DATA2              0x348 0x730 0x000 0x1 0x0
-#define MX6DL_PAD_SD4_DAT2__PWM4_OUT               0x348 0x730 0x000 0x2 0x0
-#define MX6DL_PAD_SD4_DAT2__GPIO2_IO10             0x348 0x730 0x000 0x5 0x0
-#define MX6DL_PAD_SD4_DAT3__SD4_DATA3              0x34c 0x734 0x000 0x1 0x0
-#define MX6DL_PAD_SD4_DAT3__GPIO2_IO11             0x34c 0x734 0x000 0x5 0x0
-#define MX6DL_PAD_SD4_DAT4__SD4_DATA4              0x350 0x738 0x000 0x1 0x0
-#define MX6DL_PAD_SD4_DAT4__UART2_RX_DATA          0x350 0x738 0x904 0x2 0x6
-#define MX6DL_PAD_SD4_DAT4__UART2_TX_DATA          0x350 0x738 0x000 0x2 0x0
-#define MX6DL_PAD_SD4_DAT4__GPIO2_IO12             0x350 0x738 0x000 0x5 0x0
-#define MX6DL_PAD_SD4_DAT5__SD4_DATA5              0x354 0x73c 0x000 0x1 0x0
-#define MX6DL_PAD_SD4_DAT5__UART2_RTS_B            0x354 0x73c 0x900 0x2 0x4
-#define MX6DL_PAD_SD4_DAT5__UART2_CTS_B            0x354 0x73c 0x000 0x2 0x0
-#define MX6DL_PAD_SD4_DAT5__GPIO2_IO13             0x354 0x73c 0x000 0x5 0x0
-#define MX6DL_PAD_SD4_DAT6__SD4_DATA6              0x358 0x740 0x000 0x1 0x0
-#define MX6DL_PAD_SD4_DAT6__UART2_CTS_B            0x358 0x740 0x000 0x2 0x0
-#define MX6DL_PAD_SD4_DAT6__UART2_RTS_B            0x358 0x740 0x900 0x2 0x5
-#define MX6DL_PAD_SD4_DAT6__GPIO2_IO14             0x358 0x740 0x000 0x5 0x0
-#define MX6DL_PAD_SD4_DAT7__SD4_DATA7              0x35c 0x744 0x000 0x1 0x0
-#define MX6DL_PAD_SD4_DAT7__UART2_TX_DATA          0x35c 0x744 0x000 0x2 0x0
-#define MX6DL_PAD_SD4_DAT7__UART2_RX_DATA          0x35c 0x744 0x904 0x2 0x7
-#define MX6DL_PAD_SD4_DAT7__GPIO2_IO15             0x35c 0x744 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10     0x04c 0x360 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC             0x04c 0x360 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO          0x04c 0x360 0x7f8 0x2 0x0
+#define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA        0x04c 0x360 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA        0x04c 0x360 0x8fc 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28           0x04c 0x360 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07          0x04c 0x360 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11     0x050 0x364 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS            0x050 0x364 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0           0x050 0x364 0x800 0x2 0x0
+#define MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA        0x050 0x364 0x8fc 0x3 0x1
+#define MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA        0x050 0x364 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29           0x050 0x364 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT11__ARM_TRACE08          0x050 0x364 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12     0x054 0x368 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT12__EIM_DATA08           0x054 0x368 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA        0x054 0x368 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT12__UART4_RX_DATA        0x054 0x368 0x914 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30           0x054 0x368 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT12__ARM_TRACE09          0x054 0x368 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13     0x058 0x36c 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT13__EIM_DATA09           0x058 0x36c 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA        0x058 0x36c 0x914 0x3 0x1
+#define MX6QDL_PAD_CSI0_DAT13__UART4_TX_DATA        0x058 0x36c 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31           0x058 0x36c 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT13__ARM_TRACE10          0x058 0x36c 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14     0x05c 0x370 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT14__EIM_DATA10           0x05c 0x370 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA        0x05c 0x370 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT14__UART5_RX_DATA        0x05c 0x370 0x91c 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00           0x05c 0x370 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT14__ARM_TRACE11          0x05c 0x370 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15     0x060 0x374 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT15__EIM_DATA11           0x060 0x374 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA        0x060 0x374 0x91c 0x3 0x1
+#define MX6QDL_PAD_CSI0_DAT15__UART5_TX_DATA        0x060 0x374 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01           0x060 0x374 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT15__ARM_TRACE12          0x060 0x374 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16     0x064 0x378 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT16__EIM_DATA12           0x064 0x378 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B          0x064 0x378 0x910 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT16__UART4_CTS_B          0x064 0x378 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02           0x064 0x378 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT16__ARM_TRACE13          0x064 0x378 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17     0x068 0x37c 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT17__EIM_DATA13           0x068 0x37c 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B          0x068 0x37c 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT17__UART4_RTS_B          0x068 0x37c 0x910 0x3 0x1
+#define MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03           0x068 0x37c 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT17__ARM_TRACE14          0x068 0x37c 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18     0x06c 0x380 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT18__EIM_DATA14           0x06c 0x380 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B          0x06c 0x380 0x918 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT18__UART5_CTS_B          0x06c 0x380 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04           0x06c 0x380 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT18__ARM_TRACE15          0x06c 0x380 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19     0x070 0x384 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT19__EIM_DATA15           0x070 0x384 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B          0x070 0x384 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT19__UART5_RTS_B          0x070 0x384 0x918 0x3 0x1
+#define MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05           0x070 0x384 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04      0x074 0x388 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT4__EIM_DATA02            0x074 0x388 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK           0x074 0x388 0x7d8 0x2 0x0
+#define MX6QDL_PAD_CSI0_DAT4__KEY_COL5              0x074 0x388 0x8c0 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT4__AUD3_TXC              0x074 0x388 0x000 0x4 0x0
+#define MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22            0x074 0x388 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT4__ARM_TRACE01           0x074 0x388 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05      0x078 0x38c 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT5__EIM_DATA03            0x078 0x38c 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI           0x078 0x38c 0x7e0 0x2 0x0
+#define MX6QDL_PAD_CSI0_DAT5__KEY_ROW5              0x078 0x38c 0x8cc 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT5__AUD3_TXD              0x078 0x38c 0x000 0x4 0x0
+#define MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23            0x078 0x38c 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT5__ARM_TRACE02           0x078 0x38c 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06      0x07c 0x390 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT6__EIM_DATA04            0x07c 0x390 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO           0x07c 0x390 0x7dc 0x2 0x0
+#define MX6QDL_PAD_CSI0_DAT6__KEY_COL6              0x07c 0x390 0x8c4 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS             0x07c 0x390 0x000 0x4 0x0
+#define MX6QDL_PAD_CSI0_DAT6__GPIO5_IO24            0x07c 0x390 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT6__ARM_TRACE03           0x07c 0x390 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07      0x080 0x394 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT7__EIM_DATA05            0x080 0x394 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT7__ECSPI1_SS0            0x080 0x394 0x7e4 0x2 0x0
+#define MX6QDL_PAD_CSI0_DAT7__KEY_ROW6              0x080 0x394 0x8d0 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT7__AUD3_RXD              0x080 0x394 0x000 0x4 0x0
+#define MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25            0x080 0x394 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT7__ARM_TRACE04           0x080 0x394 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08      0x084 0x398 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT8__EIM_DATA06            0x084 0x398 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK           0x084 0x398 0x7f4 0x2 0x0
+#define MX6QDL_PAD_CSI0_DAT8__KEY_COL7              0x084 0x398 0x8c8 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT8__I2C1_SDA              0x084 0x398 0x86c 0x4 0x0
+#define MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26            0x084 0x398 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT8__ARM_TRACE05           0x084 0x398 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09      0x088 0x39c 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT9__EIM_DATA07            0x088 0x39c 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI           0x088 0x39c 0x7fc 0x2 0x0
+#define MX6QDL_PAD_CSI0_DAT9__KEY_ROW7              0x088 0x39c 0x8d4 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT9__I2C1_SCL              0x088 0x39c 0x868 0x4 0x0
+#define MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27            0x088 0x39c 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT9__ARM_TRACE06           0x088 0x39c 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN  0x08c 0x3a0 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00         0x08c 0x3a0 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20         0x08c 0x3a0 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK      0x08c 0x3a0 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC       0x090 0x3a4 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1             0x090 0x3a4 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19            0x090 0x3a4 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL         0x090 0x3a4 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK    0x094 0x3a8 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18          0x094 0x3a8 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_PIXCLK__ARM_EVENTO          0x094 0x3a8 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC      0x098 0x3ac 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01           0x098 0x3ac 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21           0x098 0x3ac 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_VSYNC__ARM_TRACE00          0x098 0x3ac 0x000 0x7 0x0
+#define MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK  0x09c 0x3b0 0x000 0x0 0x0
+#define MX6QDL_PAD_DI0_DISP_CLK__LCD_CLK            0x09c 0x3b0 0x000 0x1 0x0
+#define MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16         0x09c 0x3b0 0x000 0x5 0x0
+#define MX6QDL_PAD_DI0_DISP_CLK__LCD_WR_RWN         0x09c 0x3b0 0x000 0x8 0x0
+#define MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15        0x0a0 0x3b4 0x000 0x0 0x0
+#define MX6QDL_PAD_DI0_PIN15__LCD_ENABLE            0x0a0 0x3b4 0x000 0x1 0x0
+#define MX6QDL_PAD_DI0_PIN15__AUD6_TXC              0x0a0 0x3b4 0x000 0x2 0x0
+#define MX6QDL_PAD_DI0_PIN15__GPIO4_IO17            0x0a0 0x3b4 0x000 0x5 0x0
+#define MX6QDL_PAD_DI0_PIN15__LCD_RD_E              0x0a0 0x3b4 0x000 0x8 0x0
+#define MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02         0x0a4 0x3b8 0x000 0x0 0x0
+#define MX6QDL_PAD_DI0_PIN2__LCD_HSYNC              0x0a4 0x3b8 0x8d8 0x1 0x0
+#define MX6QDL_PAD_DI0_PIN2__AUD6_TXD               0x0a4 0x3b8 0x000 0x2 0x0
+#define MX6QDL_PAD_DI0_PIN2__GPIO4_IO18             0x0a4 0x3b8 0x000 0x5 0x0
+#define MX6QDL_PAD_DI0_PIN2__LCD_RS                 0x0a4 0x3b8 0x000 0x8 0x0
+#define MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03         0x0a8 0x3bc 0x000 0x0 0x0
+#define MX6QDL_PAD_DI0_PIN3__LCD_VSYNC              0x0a8 0x3bc 0x000 0x1 0x0
+#define MX6QDL_PAD_DI0_PIN3__AUD6_TXFS              0x0a8 0x3bc 0x000 0x2 0x0
+#define MX6QDL_PAD_DI0_PIN3__GPIO4_IO19             0x0a8 0x3bc 0x000 0x5 0x0
+#define MX6QDL_PAD_DI0_PIN3__LCD_CS                 0x0a8 0x3bc 0x000 0x8 0x0
+#define MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04         0x0ac 0x3c0 0x000 0x0 0x0
+#define MX6QDL_PAD_DI0_PIN4__LCD_BUSY               0x0ac 0x3c0 0x8d8 0x1 0x1
+#define MX6QDL_PAD_DI0_PIN4__AUD6_RXD               0x0ac 0x3c0 0x000 0x2 0x0
+#define MX6QDL_PAD_DI0_PIN4__SD1_WP                 0x0ac 0x3c0 0x92c 0x3 0x0
+#define MX6QDL_PAD_DI0_PIN4__GPIO4_IO20             0x0ac 0x3c0 0x000 0x5 0x0
+#define MX6QDL_PAD_DI0_PIN4__LCD_RESET              0x0ac 0x3c0 0x000 0x8 0x0
+#define MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00    0x0b0 0x3c4 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT0__LCD_DATA00           0x0b0 0x3c4 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK          0x0b0 0x3c4 0x000 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21           0x0b0 0x3c4 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01    0x0b4 0x3c8 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT1__LCD_DATA01           0x0b4 0x3c8 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI          0x0b4 0x3c8 0x000 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22           0x0b4 0x3c8 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10   0x0b8 0x3cc 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT10__LCD_DATA10          0x0b8 0x3cc 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31          0x0b8 0x3cc 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11   0x0bc 0x3d0 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT11__LCD_DATA11          0x0bc 0x3d0 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05          0x0bc 0x3d0 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12   0x0c0 0x3d4 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT12__LCD_DATA12          0x0c0 0x3d4 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06          0x0c0 0x3d4 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13   0x0c4 0x3d8 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT13__LCD_DATA13          0x0c4 0x3d8 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT13__AUD5_RXFS           0x0c4 0x3d8 0x7bc 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07          0x0c4 0x3d8 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14   0x0c8 0x3dc 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT14__LCD_DATA14          0x0c8 0x3dc 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT14__AUD5_RXC            0x0c8 0x3dc 0x7b8 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08          0x0c8 0x3dc 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15   0x0cc 0x3e0 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT15__LCD_DATA15          0x0cc 0x3e0 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT15__ECSPI1_SS1          0x0cc 0x3e0 0x7e8 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT15__ECSPI2_SS1          0x0cc 0x3e0 0x804 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09          0x0cc 0x3e0 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16   0x0d0 0x3e4 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT16__LCD_DATA16          0x0d0 0x3e4 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI         0x0d0 0x3e4 0x7fc 0x2 0x1
+#define MX6QDL_PAD_DISP0_DAT16__AUD5_TXC            0x0d0 0x3e4 0x7c0 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT16__SDMA_EXT_EVENT0     0x0d0 0x3e4 0x8e8 0x4 0x0
+#define MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10          0x0d0 0x3e4 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17   0x0d4 0x3e8 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT17__LCD_DATA17          0x0d4 0x3e8 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO         0x0d4 0x3e8 0x7f8 0x2 0x1
+#define MX6QDL_PAD_DISP0_DAT17__AUD5_TXD            0x0d4 0x3e8 0x7b4 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT17__SDMA_EXT_EVENT1     0x0d4 0x3e8 0x8ec 0x4 0x0
+#define MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11          0x0d4 0x3e8 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18   0x0d8 0x3ec 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT18__LCD_DATA18          0x0d8 0x3ec 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT18__ECSPI2_SS0          0x0d8 0x3ec 0x800 0x2 0x1
+#define MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS           0x0d8 0x3ec 0x7c4 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT18__AUD4_RXFS           0x0d8 0x3ec 0x7a4 0x4 0x0
+#define MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12          0x0d8 0x3ec 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT18__EIM_CS2_B           0x0d8 0x3ec 0x000 0x7 0x0
+#define MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19   0x0dc 0x3f0 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT19__LCD_DATA19          0x0dc 0x3f0 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK         0x0dc 0x3f0 0x7f4 0x2 0x1
+#define MX6QDL_PAD_DISP0_DAT19__AUD5_RXD            0x0dc 0x3f0 0x7b0 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT19__AUD4_RXC            0x0dc 0x3f0 0x7a0 0x4 0x0
+#define MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13          0x0dc 0x3f0 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT19__EIM_CS3_B           0x0dc 0x3f0 0x000 0x7 0x0
+#define MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02    0x0e0 0x3f4 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT2__LCD_DATA02           0x0e0 0x3f4 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO          0x0e0 0x3f4 0x000 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT2__GPIO4_IO23           0x0e0 0x3f4 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20   0x0e4 0x3f8 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT20__LCD_DATA20          0x0e4 0x3f8 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT20__ECSPI1_SCLK         0x0e4 0x3f8 0x7d8 0x2 0x1
+#define MX6QDL_PAD_DISP0_DAT20__AUD4_TXC            0x0e4 0x3f8 0x7a8 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14          0x0e4 0x3f8 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21   0x0e8 0x3fc 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT21__LCD_DATA21          0x0e8 0x3fc 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT21__ECSPI1_MOSI         0x0e8 0x3fc 0x7e0 0x2 0x1
+#define MX6QDL_PAD_DISP0_DAT21__AUD4_TXD            0x0e8 0x3fc 0x79c 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15          0x0e8 0x3fc 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22   0x0ec 0x400 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT22__LCD_DATA22          0x0ec 0x400 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT22__ECSPI1_MISO         0x0ec 0x400 0x7dc 0x2 0x1
+#define MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS           0x0ec 0x400 0x7ac 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16          0x0ec 0x400 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23   0x0f0 0x404 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT23__LCD_DATA23          0x0f0 0x404 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT23__ECSPI1_SS0          0x0f0 0x404 0x7e4 0x2 0x1
+#define MX6QDL_PAD_DISP0_DAT23__AUD4_RXD            0x0f0 0x404 0x798 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17          0x0f0 0x404 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03    0x0f4 0x408 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT3__LCD_DATA03           0x0f4 0x408 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT3__ECSPI3_SS0           0x0f4 0x408 0x000 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24           0x0f4 0x408 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04    0x0f8 0x40c 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT4__LCD_DATA04           0x0f8 0x40c 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT4__ECSPI3_SS1           0x0f8 0x40c 0x000 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25           0x0f8 0x40c 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05    0x0fc 0x410 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT5__LCD_DATA05           0x0fc 0x410 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT5__ECSPI3_SS2           0x0fc 0x410 0x000 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT5__AUD6_RXFS            0x0fc 0x410 0x000 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26           0x0fc 0x410 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06    0x100 0x414 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT6__LCD_DATA06           0x100 0x414 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT6__ECSPI3_SS3           0x100 0x414 0x000 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT6__AUD6_RXC             0x100 0x414 0x000 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27           0x100 0x414 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07    0x104 0x418 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT7__LCD_DATA07           0x104 0x418 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT7__ECSPI3_RDY           0x104 0x418 0x000 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28           0x104 0x418 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08    0x108 0x41c 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT8__LCD_DATA08           0x108 0x41c 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT8__PWM1_OUT             0x108 0x41c 0x000 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT8__WDOG1_B              0x108 0x41c 0x000 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29           0x108 0x41c 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09    0x10c 0x420 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT9__LCD_DATA09           0x10c 0x420 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT9__PWM2_OUT             0x10c 0x420 0x000 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT9__WDOG2_B              0x10c 0x420 0x000 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30           0x10c 0x420 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A16__EIM_ADDR16              0x110 0x4e0 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK       0x110 0x4e0 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_A16__IPU1_CSI1_PIXCLK        0x110 0x4e0 0x8b8 0x2 0x0
+#define MX6QDL_PAD_EIM_A16__GPIO2_IO22              0x110 0x4e0 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A16__SRC_BOOT_CFG16          0x110 0x4e0 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_A16__EPDC_DATA00             0x110 0x4e0 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_A17__EIM_ADDR17              0x114 0x4e4 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12       0x114 0x4e4 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12        0x114 0x4e4 0x890 0x2 0x0
+#define MX6QDL_PAD_EIM_A17__GPIO2_IO21              0x114 0x4e4 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A17__SRC_BOOT_CFG17          0x114 0x4e4 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_A17__EPDC_PWR_STAT           0x114 0x4e4 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_A18__EIM_ADDR18              0x118 0x4e8 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13       0x118 0x4e8 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_A18__IPU1_CSI1_DATA13        0x118 0x4e8 0x894 0x2 0x0
+#define MX6QDL_PAD_EIM_A18__GPIO2_IO20              0x118 0x4e8 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A18__SRC_BOOT_CFG18          0x118 0x4e8 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_A18__EPDC_PWR_CTRL0          0x118 0x4e8 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_A19__EIM_ADDR19              0x11c 0x4ec 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14       0x11c 0x4ec 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_A19__IPU1_CSI1_DATA14        0x11c 0x4ec 0x898 0x2 0x0
+#define MX6QDL_PAD_EIM_A19__GPIO2_IO19              0x11c 0x4ec 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A19__SRC_BOOT_CFG19          0x11c 0x4ec 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_A19__EPDC_PWR_CTRL1          0x11c 0x4ec 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_A20__EIM_ADDR20              0x120 0x4f0 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15       0x120 0x4f0 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_A20__IPU1_CSI1_DATA15        0x120 0x4f0 0x89c 0x2 0x0
+#define MX6QDL_PAD_EIM_A20__GPIO2_IO18              0x120 0x4f0 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A20__SRC_BOOT_CFG20          0x120 0x4f0 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_A20__EPDC_PWR_CTRL2          0x120 0x4f0 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_A21__EIM_ADDR21              0x124 0x4f4 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16       0x124 0x4f4 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_A21__IPU1_CSI1_DATA16        0x124 0x4f4 0x8a0 0x2 0x0
+#define MX6QDL_PAD_EIM_A21__GPIO2_IO17              0x124 0x4f4 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A21__SRC_BOOT_CFG21          0x124 0x4f4 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_A21__EPDC_GDCLK              0x124 0x4f4 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_A22__EIM_ADDR22              0x128 0x4f8 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17       0x128 0x4f8 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_A22__IPU1_CSI1_DATA17        0x128 0x4f8 0x8a4 0x2 0x0
+#define MX6QDL_PAD_EIM_A22__GPIO2_IO16              0x128 0x4f8 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A22__SRC_BOOT_CFG22          0x128 0x4f8 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_A22__EPDC_GDSP               0x128 0x4f8 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_A23__EIM_ADDR23              0x12c 0x4fc 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18       0x12c 0x4fc 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_A23__IPU1_CSI1_DATA18        0x12c 0x4fc 0x8a8 0x2 0x0
+#define MX6QDL_PAD_EIM_A23__IPU1_SISG3              0x12c 0x4fc 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_A23__GPIO6_IO06              0x12c 0x4fc 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A23__SRC_BOOT_CFG23          0x12c 0x4fc 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_A23__EPDC_GDOE               0x12c 0x4fc 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_A24__EIM_ADDR24              0x130 0x500 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19       0x130 0x500 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_A24__IPU1_CSI1_DATA19        0x130 0x500 0x8ac 0x2 0x0
+#define MX6QDL_PAD_EIM_A24__IPU1_SISG2              0x130 0x500 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_A24__GPIO5_IO04              0x130 0x500 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A24__SRC_BOOT_CFG24          0x130 0x500 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_A24__EPDC_GDRL               0x130 0x500 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_A25__EIM_ADDR25              0x134 0x504 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_A25__ECSPI4_SS1              0x134 0x504 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_A25__ECSPI2_RDY              0x134 0x504 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_A25__IPU1_DI1_PIN12          0x134 0x504 0x000 0x3 0x0
+#define MX6QDL_PAD_EIM_A25__IPU1_DI0_D1_CS          0x134 0x504 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_A25__GPIO5_IO02              0x134 0x504 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE        0x134 0x504 0x85c 0x6 0x0
+#define MX6QDL_PAD_EIM_A25__EPDC_DATA15             0x134 0x504 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_A25__EIM_ACLK_FREERUN        0x134 0x504 0x000 0x9 0x0
+#define MX6QDL_PAD_EIM_BCLK__EIM_BCLK               0x138 0x508 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_BCLK__IPU1_DI1_PIN16         0x138 0x508 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_BCLK__GPIO6_IO31             0x138 0x508 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_BCLK__EPDC_SDCE9             0x138 0x508 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_CS0__EIM_CS0_B               0x13c 0x50c 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_CS0__IPU1_DI1_PIN05          0x13c 0x50c 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK             0x13c 0x50c 0x7f4 0x2 0x2
+#define MX6QDL_PAD_EIM_CS0__GPIO2_IO23              0x13c 0x50c 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_CS0__EPDC_DATA06             0x13c 0x50c 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_CS1__EIM_CS1_B               0x140 0x510 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_CS1__IPU1_DI1_PIN06          0x140 0x510 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI             0x140 0x510 0x7fc 0x2 0x2
+#define MX6QDL_PAD_EIM_CS1__GPIO2_IO24              0x140 0x510 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_CS1__EPDC_DATA08             0x140 0x510 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_D16__EIM_DATA16              0x144 0x514 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D16__ECSPI1_SCLK             0x144 0x514 0x7d8 0x1 0x2
+#define MX6QDL_PAD_EIM_D16__IPU1_DI0_PIN05          0x144 0x514 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D16__IPU1_CSI1_DATA18        0x144 0x514 0x8a8 0x3 0x1
+#define MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA         0x144 0x514 0x864 0x4 0x0
+#define MX6QDL_PAD_EIM_D16__GPIO3_IO16              0x144 0x514 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D16__I2C2_SDA                0x144 0x514 0x874 0x6 0x0
+#define MX6QDL_PAD_EIM_D16__EPDC_DATA10             0x144 0x514 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_D17__EIM_DATA17              0x148 0x518 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D17__ECSPI1_MISO             0x148 0x518 0x7dc 0x1 0x2
+#define MX6QDL_PAD_EIM_D17__IPU1_DI0_PIN06          0x148 0x518 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK        0x148 0x518 0x8b8 0x3 0x1
+#define MX6QDL_PAD_EIM_D17__DCIC1_OUT               0x148 0x518 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D17__GPIO3_IO17              0x148 0x518 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D17__I2C3_SCL                0x148 0x518 0x878 0x6 0x0
+#define MX6QDL_PAD_EIM_D17__EPDC_VCOM0              0x148 0x518 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_D18__EIM_DATA18              0x14c 0x51c 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D18__ECSPI1_MOSI             0x14c 0x51c 0x7e0 0x1 0x2
+#define MX6QDL_PAD_EIM_D18__IPU1_DI0_PIN07          0x14c 0x51c 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D18__IPU1_CSI1_DATA17        0x14c 0x51c 0x8a4 0x3 0x1
+#define MX6QDL_PAD_EIM_D18__IPU1_DI1_D0_CS          0x14c 0x51c 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D18__GPIO3_IO18              0x14c 0x51c 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D18__I2C3_SDA                0x14c 0x51c 0x87c 0x6 0x0
+#define MX6QDL_PAD_EIM_D18__EPDC_VCOM1              0x14c 0x51c 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_D19__EIM_DATA19              0x150 0x520 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D19__ECSPI1_SS1              0x150 0x520 0x7e8 0x1 0x1
+#define MX6QDL_PAD_EIM_D19__IPU1_DI0_PIN08          0x150 0x520 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D19__IPU1_CSI1_DATA16        0x150 0x520 0x8a0 0x3 0x1
+#define MX6QDL_PAD_EIM_D19__UART1_CTS_B             0x150 0x520 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D19__UART1_RTS_B             0x150 0x520 0x8f8 0x4 0x0
+#define MX6QDL_PAD_EIM_D19__GPIO3_IO19              0x150 0x520 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D19__EPIT1_OUT               0x150 0x520 0x000 0x6 0x0
+#define MX6QDL_PAD_EIM_D19__EPDC_DATA12             0x150 0x520 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_D20__EIM_DATA20              0x154 0x524 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D20__ECSPI4_SS0              0x154 0x524 0x808 0x1 0x0
+#define MX6QDL_PAD_EIM_D20__IPU1_DI0_PIN16          0x154 0x524 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D20__IPU1_CSI1_DATA15        0x154 0x524 0x89c 0x3 0x1
+#define MX6QDL_PAD_EIM_D20__UART1_RTS_B             0x154 0x524 0x8f8 0x4 0x1
+#define MX6QDL_PAD_EIM_D20__UART1_CTS_B             0x154 0x524 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D20__GPIO3_IO20              0x154 0x524 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D20__EPIT2_OUT               0x154 0x524 0x000 0x6 0x0
+#define MX6QDL_PAD_EIM_D21__EIM_DATA21              0x158 0x528 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D21__ECSPI4_SCLK             0x158 0x528 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_D21__IPU1_DI0_PIN17          0x158 0x528 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D21__IPU1_CSI1_DATA11        0x158 0x528 0x88c 0x3 0x0
+#define MX6QDL_PAD_EIM_D21__USB_OTG_OC              0x158 0x528 0x920 0x4 0x0
+#define MX6QDL_PAD_EIM_D21__GPIO3_IO21              0x158 0x528 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D21__I2C1_SCL                0x158 0x528 0x868 0x6 0x1
+#define MX6QDL_PAD_EIM_D21__SPDIF_IN                0x158 0x528 0x8f0 0x7 0x0
+#define MX6QDL_PAD_EIM_D22__EIM_DATA22              0x15c 0x52c 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D22__ECSPI4_MISO             0x15c 0x52c 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_D22__IPU1_DI0_PIN01          0x15c 0x52c 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D22__IPU1_CSI1_DATA10        0x15c 0x52c 0x888 0x3 0x0
+#define MX6QDL_PAD_EIM_D22__USB_OTG_PWR             0x15c 0x52c 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D22__GPIO3_IO22              0x15c 0x52c 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D22__SPDIF_OUT               0x15c 0x52c 0x000 0x6 0x0
+#define MX6QDL_PAD_EIM_D22__EPDC_SDCE6              0x15c 0x52c 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_D23__EIM_DATA23              0x160 0x530 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D23__IPU1_DI0_D0_CS          0x160 0x530 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_D23__UART3_CTS_B             0x160 0x530 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D23__UART3_RTS_B             0x160 0x530 0x908 0x2 0x0
+#define MX6QDL_PAD_EIM_D23__UART1_DCD_B             0x160 0x530 0x000 0x3 0x0
+#define MX6QDL_PAD_EIM_D23__IPU1_CSI1_DATA_EN       0x160 0x530 0x8b0 0x4 0x0
+#define MX6QDL_PAD_EIM_D23__GPIO3_IO23              0x160 0x530 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN02          0x160 0x530 0x000 0x6 0x0
+#define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN14          0x160 0x530 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_D23__EPDC_DATA11             0x160 0x530 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_D24__EIM_DATA24              0x164 0x534 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D24__ECSPI4_SS2              0x164 0x534 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_D24__UART3_TX_DATA           0x164 0x534 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D24__UART3_RX_DATA           0x164 0x534 0x90c 0x2 0x0
+#define MX6QDL_PAD_EIM_D24__ECSPI1_SS2              0x164 0x534 0x7ec 0x3 0x0
+#define MX6QDL_PAD_EIM_D24__ECSPI2_SS2              0x164 0x534 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D24__GPIO3_IO24              0x164 0x534 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D24__AUD5_RXFS               0x164 0x534 0x7bc 0x6 0x1
+#define MX6QDL_PAD_EIM_D24__UART1_DTR_B             0x164 0x534 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_D24__EPDC_SDCE7              0x164 0x534 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_D25__EIM_DATA25              0x168 0x538 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D25__ECSPI4_SS3              0x168 0x538 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_D25__UART3_RX_DATA           0x168 0x538 0x90c 0x2 0x1
+#define MX6QDL_PAD_EIM_D25__UART3_TX_DATA           0x168 0x538 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D25__ECSPI1_SS3              0x168 0x538 0x7f0 0x3 0x0
+#define MX6QDL_PAD_EIM_D25__ECSPI2_SS3              0x168 0x538 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D25__GPIO3_IO25              0x168 0x538 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D25__AUD5_RXC                0x168 0x538 0x7b8 0x6 0x1
+#define MX6QDL_PAD_EIM_D25__UART1_DSR_B             0x168 0x538 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_D25__EPDC_SDCE8              0x168 0x538 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_D26__EIM_DATA26              0x16c 0x53c 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D26__IPU1_DI1_PIN11          0x16c 0x53c 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_D26__IPU1_CSI0_DATA01        0x16c 0x53c 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D26__IPU1_CSI1_DATA14        0x16c 0x53c 0x898 0x3 0x1
+#define MX6QDL_PAD_EIM_D26__UART2_TX_DATA           0x16c 0x53c 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D26__UART2_RX_DATA           0x16c 0x53c 0x904 0x4 0x0
+#define MX6QDL_PAD_EIM_D26__GPIO3_IO26              0x16c 0x53c 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D26__IPU1_SISG2              0x16c 0x53c 0x000 0x6 0x0
+#define MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22       0x16c 0x53c 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_D26__EPDC_SDOED              0x16c 0x53c 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_D27__EIM_DATA27              0x170 0x540 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D27__IPU1_DI1_PIN13          0x170 0x540 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_D27__IPU1_CSI0_DATA00        0x170 0x540 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D27__IPU1_CSI1_DATA13        0x170 0x540 0x894 0x3 0x1
+#define MX6QDL_PAD_EIM_D27__UART2_RX_DATA           0x170 0x540 0x904 0x4 0x1
+#define MX6QDL_PAD_EIM_D27__UART2_TX_DATA           0x170 0x540 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D27__GPIO3_IO27              0x170 0x540 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D27__IPU1_SISG3              0x170 0x540 0x000 0x6 0x0
+#define MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23       0x170 0x540 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_D27__EPDC_SDOE               0x170 0x540 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_D28__EIM_DATA28              0x174 0x544 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D28__I2C1_SDA                0x174 0x544 0x86c 0x1 0x1
+#define MX6QDL_PAD_EIM_D28__ECSPI4_MOSI             0x174 0x544 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D28__IPU1_CSI1_DATA12        0x174 0x544 0x890 0x3 0x1
+#define MX6QDL_PAD_EIM_D28__UART2_CTS_B             0x174 0x544 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D28__UART2_RTS_B             0x174 0x544 0x900 0x4 0x0
+#define MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B         0x174 0x544 0x900 0x4 0x0
+#define MX6QDL_PAD_EIM_D28__UART2_DTE_RTS_B         0x174 0x544 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D28__GPIO3_IO28              0x174 0x544 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D28__IPU1_EXT_TRIG           0x174 0x544 0x000 0x6 0x0
+#define MX6QDL_PAD_EIM_D28__IPU1_DI0_PIN13          0x174 0x544 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_D28__EPDC_PWR_CTRL3          0x174 0x544 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_D29__EIM_DATA29              0x178 0x548 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D29__IPU1_DI1_PIN15          0x178 0x548 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_D29__ECSPI4_SS0              0x178 0x548 0x808 0x2 0x1
+#define MX6QDL_PAD_EIM_D29__UART2_RTS_B             0x178 0x548 0x900 0x4 0x1
+#define MX6QDL_PAD_EIM_D29__UART2_CTS_B             0x178 0x548 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B         0x178 0x548 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D29__UART2_DTE_CTS_B         0x178 0x548 0x900 0x4 0x1
+#define MX6QDL_PAD_EIM_D29__GPIO3_IO29              0x178 0x548 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC         0x178 0x548 0x8bc 0x6 0x0
+#define MX6QDL_PAD_EIM_D29__IPU1_DI0_PIN14          0x178 0x548 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_D29__EPDC_PWR_WAKE           0x178 0x548 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_D30__EIM_DATA30              0x17c 0x54c 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21       0x17c 0x54c 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_D30__IPU1_DI0_PIN11          0x17c 0x54c 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D30__IPU1_CSI0_DATA03        0x17c 0x54c 0x000 0x3 0x0
+#define MX6QDL_PAD_EIM_D30__UART3_CTS_B             0x17c 0x54c 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D30__UART3_RTS_B             0x17c 0x54c 0x908 0x4 0x1
+#define MX6QDL_PAD_EIM_D30__GPIO3_IO30              0x17c 0x54c 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D30__USB_H1_OC               0x17c 0x54c 0x924 0x6 0x0
+#define MX6QDL_PAD_EIM_D30__EPDC_SDOEZ              0x17c 0x54c 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_D31__EIM_DATA31              0x180 0x550 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20       0x180 0x550 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_D31__IPU1_DI0_PIN12          0x180 0x550 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D31__IPU1_CSI0_DATA02        0x180 0x550 0x000 0x3 0x0
+#define MX6QDL_PAD_EIM_D31__UART3_RTS_B             0x180 0x550 0x908 0x4 0x2
+#define MX6QDL_PAD_EIM_D31__UART3_CTS_B             0x180 0x550 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D31__GPIO3_IO31              0x180 0x550 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D31__USB_H1_PWR              0x180 0x550 0x000 0x6 0x0
+#define MX6QDL_PAD_EIM_D31__EPDC_SDCLK_P            0x180 0x550 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_D31__EIM_ACLK_FREERUN        0x180 0x550 0x000 0x9 0x0
+#define MX6QDL_PAD_EIM_DA0__EIM_AD00                0x184 0x554 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09       0x184 0x554 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA0__IPU1_CSI1_DATA09        0x184 0x554 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA0__GPIO3_IO00              0x184 0x554 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA0__SRC_BOOT_CFG00          0x184 0x554 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA0__EPDC_SDCLK_N            0x184 0x554 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_DA1__EIM_AD01                0x188 0x558 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08       0x188 0x558 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA1__IPU1_CSI1_DATA08        0x188 0x558 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA1__GPIO3_IO01              0x188 0x558 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA1__SRC_BOOT_CFG01          0x188 0x558 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA1__EPDC_SDLE               0x188 0x558 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_DA10__EIM_AD10               0x18c 0x55c 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15         0x18c 0x55c 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA10__IPU1_CSI1_DATA_EN      0x18c 0x55c 0x8b0 0x2 0x1
+#define MX6QDL_PAD_EIM_DA10__GPIO3_IO10             0x18c 0x55c 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA10__SRC_BOOT_CFG10         0x18c 0x55c 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA10__EPDC_DATA01            0x18c 0x55c 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_DA11__EIM_AD11               0x190 0x560 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02         0x190 0x560 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA11__IPU1_CSI1_HSYNC        0x190 0x560 0x8b4 0x2 0x0
+#define MX6QDL_PAD_EIM_DA11__GPIO3_IO11             0x190 0x560 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA11__SRC_BOOT_CFG11         0x190 0x560 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA11__EPDC_DATA03            0x190 0x560 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_DA12__EIM_AD12               0x194 0x564 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03         0x194 0x564 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA12__IPU1_CSI1_VSYNC        0x194 0x564 0x8bc 0x2 0x1
+#define MX6QDL_PAD_EIM_DA12__GPIO3_IO12             0x194 0x564 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA12__SRC_BOOT_CFG12         0x194 0x564 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA12__EPDC_DATA02            0x194 0x564 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_DA13__EIM_AD13               0x198 0x568 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA13__IPU1_DI1_D0_CS         0x198 0x568 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA13__GPIO3_IO13             0x198 0x568 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA13__SRC_BOOT_CFG13         0x198 0x568 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA13__EPDC_DATA13            0x198 0x568 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_DA14__EIM_AD14               0x19c 0x56c 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA14__IPU1_DI1_D1_CS         0x19c 0x56c 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA14__GPIO3_IO14             0x19c 0x56c 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA14__SRC_BOOT_CFG14         0x19c 0x56c 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA14__EPDC_DATA14            0x19c 0x56c 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_DA15__EIM_AD15               0x1a0 0x570 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN01         0x1a0 0x570 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN04         0x1a0 0x570 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA15__GPIO3_IO15             0x1a0 0x570 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA15__SRC_BOOT_CFG15         0x1a0 0x570 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA15__EPDC_DATA09            0x1a0 0x570 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_DA2__EIM_AD02                0x1a4 0x574 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07       0x1a4 0x574 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA2__IPU1_CSI1_DATA07        0x1a4 0x574 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA2__GPIO3_IO02              0x1a4 0x574 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA2__SRC_BOOT_CFG02          0x1a4 0x574 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA2__EPDC_BDR0               0x1a4 0x574 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_DA3__EIM_AD03                0x1a8 0x578 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06       0x1a8 0x578 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA3__IPU1_CSI1_DATA06        0x1a8 0x578 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA3__GPIO3_IO03              0x1a8 0x578 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA3__SRC_BOOT_CFG03          0x1a8 0x578 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA3__EPDC_BDR1               0x1a8 0x578 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_DA4__EIM_AD04                0x1ac 0x57c 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05       0x1ac 0x57c 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA4__IPU1_CSI1_DATA05        0x1ac 0x57c 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA4__GPIO3_IO04              0x1ac 0x57c 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA4__SRC_BOOT_CFG04          0x1ac 0x57c 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA4__EPDC_SDCE0              0x1ac 0x57c 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_DA5__EIM_AD05                0x1b0 0x580 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04       0x1b0 0x580 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA5__IPU1_CSI1_DATA04        0x1b0 0x580 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA5__GPIO3_IO05              0x1b0 0x580 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA5__SRC_BOOT_CFG05          0x1b0 0x580 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA5__EPDC_SDCE1              0x1b0 0x580 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_DA6__EIM_AD06                0x1b4 0x584 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03       0x1b4 0x584 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA6__IPU1_CSI1_DATA03        0x1b4 0x584 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA6__GPIO3_IO06              0x1b4 0x584 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA6__SRC_BOOT_CFG06          0x1b4 0x584 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA6__EPDC_SDCE2              0x1b4 0x584 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_DA7__EIM_AD07                0x1b8 0x588 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02       0x1b8 0x588 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA7__IPU1_CSI1_DATA02        0x1b8 0x588 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA7__GPIO3_IO07              0x1b8 0x588 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA7__SRC_BOOT_CFG07          0x1b8 0x588 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA7__EPDC_SDCE3              0x1b8 0x588 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_DA8__EIM_AD08                0x1bc 0x58c 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01       0x1bc 0x58c 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA8__IPU1_CSI1_DATA01        0x1bc 0x58c 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA8__GPIO3_IO08              0x1bc 0x58c 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA8__SRC_BOOT_CFG08          0x1bc 0x58c 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA8__EPDC_SDCE4              0x1bc 0x58c 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_DA9__EIM_AD09                0x1c0 0x590 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00       0x1c0 0x590 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA9__IPU1_CSI1_DATA00        0x1c0 0x590 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA9__GPIO3_IO09              0x1c0 0x590 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA9__SRC_BOOT_CFG09          0x1c0 0x590 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA9__EPDC_SDCE5              0x1c0 0x590 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_EB0__EIM_EB0_B               0x1c4 0x594 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11       0x1c4 0x594 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_EB0__IPU1_CSI1_DATA11        0x1c4 0x594 0x88c 0x2 0x1
+#define MX6QDL_PAD_EIM_EB0__CCM_PMIC_READY          0x1c4 0x594 0x7d4 0x4 0x0
+#define MX6QDL_PAD_EIM_EB0__GPIO2_IO28              0x1c4 0x594 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_EB0__SRC_BOOT_CFG27          0x1c4 0x594 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_EB0__EPDC_PWR_COM            0x1c4 0x594 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_EB1__EIM_EB1_B               0x1c8 0x598 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10       0x1c8 0x598 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_EB1__IPU1_CSI1_DATA10        0x1c8 0x598 0x888 0x2 0x1
+#define MX6QDL_PAD_EIM_EB1__GPIO2_IO29              0x1c8 0x598 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_EB1__SRC_BOOT_CFG28          0x1c8 0x598 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_EB1__EPDC_SDSHR              0x1c8 0x598 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_EB2__EIM_EB2_B               0x1cc 0x59c 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_EB2__ECSPI1_SS0              0x1cc 0x59c 0x7e4 0x1 0x2
+#define MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19        0x1cc 0x59c 0x8ac 0x3 0x1
+#define MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL         0x1cc 0x59c 0x860 0x4 0x0
+#define MX6QDL_PAD_EIM_EB2__GPIO2_IO30              0x1cc 0x59c 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_EB2__I2C2_SCL                0x1cc 0x59c 0x870 0x6 0x0
+#define MX6QDL_PAD_EIM_EB2__SRC_BOOT_CFG30          0x1cc 0x59c 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_EB2__EPDC_DATA05             0x1cc 0x59c 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_EB3__EIM_EB3_B               0x1d0 0x5a0 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_EB3__ECSPI4_RDY              0x1d0 0x5a0 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_EB3__UART3_RTS_B             0x1d0 0x5a0 0x908 0x2 0x3
+#define MX6QDL_PAD_EIM_EB3__UART3_CTS_B             0x1d0 0x5a0 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_EB3__UART1_RI_B              0x1d0 0x5a0 0x000 0x3 0x0
+#define MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC         0x1d0 0x5a0 0x8b4 0x4 0x1
+#define MX6QDL_PAD_EIM_EB3__GPIO2_IO31              0x1d0 0x5a0 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_EB3__IPU1_DI1_PIN03          0x1d0 0x5a0 0x000 0x6 0x0
+#define MX6QDL_PAD_EIM_EB3__SRC_BOOT_CFG31          0x1d0 0x5a0 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_EB3__EPDC_SDCE0              0x1d0 0x5a0 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_EB3__EIM_ACLK_FREERUN        0x1d0 0x5a0 0x000 0x9 0x0
+#define MX6QDL_PAD_EIM_LBA__EIM_LBA_B               0x1d4 0x5a4 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_LBA__IPU1_DI1_PIN17          0x1d4 0x5a4 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_LBA__ECSPI2_SS1              0x1d4 0x5a4 0x804 0x2 0x1
+#define MX6QDL_PAD_EIM_LBA__GPIO2_IO27              0x1d4 0x5a4 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_LBA__SRC_BOOT_CFG26          0x1d4 0x5a4 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_LBA__EPDC_DATA04             0x1d4 0x5a4 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_OE__EIM_OE_B                 0x1d8 0x5a8 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_OE__IPU1_DI1_PIN07           0x1d8 0x5a8 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_OE__ECSPI2_MISO              0x1d8 0x5a8 0x7f8 0x2 0x2
+#define MX6QDL_PAD_EIM_OE__GPIO2_IO25               0x1d8 0x5a8 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_OE__EPDC_PWR_IRQ             0x1d8 0x5a8 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_RW__EIM_RW                   0x1dc 0x5ac 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_RW__IPU1_DI1_PIN08           0x1dc 0x5ac 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_RW__ECSPI2_SS0               0x1dc 0x5ac 0x800 0x2 0x2
+#define MX6QDL_PAD_EIM_RW__GPIO2_IO26               0x1dc 0x5ac 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_RW__SRC_BOOT_CFG29           0x1dc 0x5ac 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_RW__EPDC_DATA07              0x1dc 0x5ac 0x000 0x8 0x0
+#define MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B             0x1e0 0x5b0 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_WAIT__EIM_DTACK_B            0x1e0 0x5b0 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_WAIT__GPIO5_IO00             0x1e0 0x5b0 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_WAIT__SRC_BOOT_CFG25         0x1e0 0x5b0 0x000 0x7 0x0
+#define MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN          0x1e4 0x5b4 0x828 0x1 0x0
+#define MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK         0x1e4 0x5b4 0x840 0x2 0x0
+#define MX6QDL_PAD_ENET_CRS_DV__SPDIF_EXT_CLK       0x1e4 0x5b4 0x8f4 0x3 0x0
+#define MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25          0x1e4 0x5b4 0x000 0x5 0x0
+#define MX6QDL_PAD_ENET_MDC__MLB_DATA               0x1e8 0x5b8 0x8e0 0x0 0x0
+#define MX6QDL_PAD_ENET_MDC__ENET_MDC               0x1e8 0x5b8 0x000 0x1 0x0
+#define MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0           0x1e8 0x5b8 0x858 0x2 0x0
+#define MX6QDL_PAD_ENET_MDC__ENET_1588_EVENT1_IN    0x1e8 0x5b8 0x000 0x4 0x0
+#define MX6QDL_PAD_ENET_MDC__GPIO1_IO31             0x1e8 0x5b8 0x000 0x5 0x0
+#define MX6QDL_PAD_ENET_MDIO__ENET_MDIO             0x1ec 0x5bc 0x810 0x1 0x0
+#define MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK           0x1ec 0x5bc 0x83c 0x2 0x0
+#define MX6QDL_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT  0x1ec 0x5bc 0x000 0x4 0x0
+#define MX6QDL_PAD_ENET_MDIO__GPIO1_IO22            0x1ec 0x5bc 0x000 0x5 0x0
+#define MX6QDL_PAD_ENET_MDIO__SPDIF_LOCK            0x1ec 0x5bc 0x000 0x6 0x0
+#define MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK        0x1f0 0x5c0 0x000 0x1 0x0
+#define MX6QDL_PAD_ENET_REF_CLK__ESAI_RX_FS         0x1f0 0x5c0 0x82c 0x2 0x0
+#define MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23         0x1f0 0x5c0 0x000 0x5 0x0
+#define MX6QDL_PAD_ENET_REF_CLK__SPDIF_SR_CLK       0x1f0 0x5c0 0x000 0x6 0x0
+#define MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID           0x1f4 0x5c4 0x790 0x0 0x0
+#define MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER           0x1f4 0x5c4 0x000 0x1 0x0
+#define MX6QDL_PAD_ENET_RX_ER__ESAI_RX_HF_CLK       0x1f4 0x5c4 0x834 0x2 0x0
+#define MX6QDL_PAD_ENET_RX_ER__SPDIF_IN             0x1f4 0x5c4 0x8f0 0x3 0x1
+#define MX6QDL_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT 0x1f4 0x5c4 0x000 0x4 0x0
+#define MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24           0x1f4 0x5c4 0x000 0x5 0x0
+#define MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0         0x1f8 0x5c8 0x818 0x1 0x0
+#define MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK        0x1f8 0x5c8 0x838 0x2 0x0
+#define MX6QDL_PAD_ENET_RXD0__SPDIF_OUT             0x1f8 0x5c8 0x000 0x3 0x0
+#define MX6QDL_PAD_ENET_RXD0__GPIO1_IO27            0x1f8 0x5c8 0x000 0x5 0x0
+#define MX6QDL_PAD_ENET_RXD1__MLB_SIG               0x1fc 0x5cc 0x8e4 0x0 0x0
+#define MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1         0x1fc 0x5cc 0x81c 0x1 0x0
+#define MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS            0x1fc 0x5cc 0x830 0x2 0x0
+#define MX6QDL_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT  0x1fc 0x5cc 0x000 0x4 0x0
+#define MX6QDL_PAD_ENET_RXD1__GPIO1_IO26            0x1fc 0x5cc 0x000 0x5 0x0
+#define MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN           0x200 0x5d0 0x000 0x1 0x0
+#define MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2         0x200 0x5d0 0x850 0x2 0x0
+#define MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28           0x200 0x5d0 0x000 0x5 0x0
+#define MX6QDL_PAD_ENET_TX_EN__I2C4_SCL             0x200 0x5d0 0x880 0x9 0x0
+#define MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0         0x204 0x5d4 0x000 0x1 0x0
+#define MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1          0x204 0x5d4 0x854 0x2 0x0
+#define MX6QDL_PAD_ENET_TXD0__GPIO1_IO30            0x204 0x5d4 0x000 0x5 0x0
+#define MX6QDL_PAD_ENET_TXD1__MLB_CLK               0x208 0x5d8 0x8dc 0x0 0x0
+#define MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1         0x208 0x5d8 0x000 0x1 0x0
+#define MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3          0x208 0x5d8 0x84c 0x2 0x0
+#define MX6QDL_PAD_ENET_TXD1__ENET_1588_EVENT0_IN   0x208 0x5d8 0x000 0x4 0x0
+#define MX6QDL_PAD_ENET_TXD1__GPIO1_IO29            0x208 0x5d8 0x000 0x5 0x0
+#define MX6QDL_PAD_ENET_TXD1__I2C4_SDA              0x208 0x5d8 0x884 0x9 0x0
+#define MX6QDL_PAD_GPIO_0__CCM_CLKO1                0x20c 0x5dc 0x000 0x0 0x0
+#define MX6QDL_PAD_GPIO_0__KEY_COL5                 0x20c 0x5dc 0x8c0 0x2 0x1
+#define MX6QDL_PAD_GPIO_0__ASRC_EXT_CLK             0x20c 0x5dc 0x794 0x3 0x0
+#define MX6QDL_PAD_GPIO_0__EPIT1_OUT                0x20c 0x5dc 0x000 0x4 0x0
+#define MX6QDL_PAD_GPIO_0__GPIO1_IO00               0x20c 0x5dc 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_0__USB_H1_PWR               0x20c 0x5dc 0x000 0x6 0x0
+#define MX6QDL_PAD_GPIO_0__SNVS_VIO_5               0x20c 0x5dc 0x000 0x7 0x0
+#define MX6QDL_PAD_GPIO_1__ESAI_RX_CLK              0x210 0x5e0 0x83c 0x0 0x1
+#define MX6QDL_PAD_GPIO_1__WDOG2_B                  0x210 0x5e0 0x000 0x1 0x0
+#define MX6QDL_PAD_GPIO_1__KEY_ROW5                 0x210 0x5e0 0x8cc 0x2 0x1
+#define MX6QDL_PAD_GPIO_1__USB_OTG_ID               0x210 0x5e0 0x790 0x3 0x1
+#define MX6QDL_PAD_GPIO_1__PWM2_OUT                 0x210 0x5e0 0x000 0x4 0x0
+#define MX6QDL_PAD_GPIO_1__GPIO1_IO01               0x210 0x5e0 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_1__SD1_CD_B                 0x210 0x5e0 0x000 0x6 0x0
+#define MX6QDL_PAD_GPIO_16__ESAI_TX3_RX2            0x214 0x5e4 0x850 0x0 0x1
+#define MX6QDL_PAD_GPIO_16__ENET_1588_EVENT2_IN     0x214 0x5e4 0x000 0x1 0x0
+#define MX6QDL_PAD_GPIO_16__ENET_REF_CLK            0x214 0x5e4 0x80c 0x2 0x0
+#define MX6QDL_PAD_GPIO_16__SD1_LCTL                0x214 0x5e4 0x000 0x3 0x0
+#define MX6QDL_PAD_GPIO_16__SPDIF_IN                0x214 0x5e4 0x8f0 0x4 0x2
+#define MX6QDL_PAD_GPIO_16__GPIO7_IO11              0x214 0x5e4 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_16__I2C3_SDA                0x214 0x5e4 0x87c 0x6 0x1
+#define MX6QDL_PAD_GPIO_16__JTAG_DE_B               0x214 0x5e4 0x000 0x7 0x0
+#define MX6QDL_PAD_GPIO_17__ESAI_TX0                0x218 0x5e8 0x844 0x0 0x0
+#define MX6QDL_PAD_GPIO_17__ENET_1588_EVENT3_IN     0x218 0x5e8 0x000 0x1 0x0
+#define MX6QDL_PAD_GPIO_17__CCM_PMIC_READY          0x218 0x5e8 0x7d4 0x2 0x1
+#define MX6QDL_PAD_GPIO_17__SDMA_EXT_EVENT0         0x218 0x5e8 0x8e8 0x3 0x1
+#define MX6QDL_PAD_GPIO_17__SPDIF_OUT               0x218 0x5e8 0x000 0x4 0x0
+#define MX6QDL_PAD_GPIO_17__GPIO7_IO12              0x218 0x5e8 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_18__ESAI_TX1                0x21c 0x5ec 0x848 0x0 0x0
+#define MX6QDL_PAD_GPIO_18__ENET_RX_CLK             0x21c 0x5ec 0x814 0x1 0x0
+#define MX6QDL_PAD_GPIO_18__SD3_VSELECT             0x21c 0x5ec 0x000 0x2 0x0
+#define MX6QDL_PAD_GPIO_18__SDMA_EXT_EVENT1         0x21c 0x5ec 0x8ec 0x3 0x1
+#define MX6QDL_PAD_GPIO_18__ASRC_EXT_CLK            0x21c 0x5ec 0x794 0x4 0x1
+#define MX6QDL_PAD_GPIO_18__GPIO7_IO13              0x21c 0x5ec 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_18__SNVS_VIO_5_CTL          0x21c 0x5ec 0x000 0x6 0x0
+#define MX6QDL_PAD_GPIO_19__KEY_COL5                0x220 0x5f0 0x8c0 0x0 0x2
+#define MX6QDL_PAD_GPIO_19__ENET_1588_EVENT0_OUT    0x220 0x5f0 0x000 0x1 0x0
+#define MX6QDL_PAD_GPIO_19__SPDIF_OUT               0x220 0x5f0 0x000 0x2 0x0
+#define MX6QDL_PAD_GPIO_19__CCM_CLKO1               0x220 0x5f0 0x000 0x3 0x0
+#define MX6QDL_PAD_GPIO_19__ECSPI1_RDY              0x220 0x5f0 0x000 0x4 0x0
+#define MX6QDL_PAD_GPIO_19__GPIO4_IO05              0x220 0x5f0 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_19__ENET_TX_ER              0x220 0x5f0 0x000 0x6 0x0
+#define MX6QDL_PAD_GPIO_2__ESAI_TX_FS               0x224 0x5f4 0x830 0x0 0x1
+#define MX6QDL_PAD_GPIO_2__KEY_ROW6                 0x224 0x5f4 0x8d0 0x2 0x1
+#define MX6QDL_PAD_GPIO_2__GPIO1_IO02               0x224 0x5f4 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_2__SD2_WP                   0x224 0x5f4 0x000 0x6 0x0
+#define MX6QDL_PAD_GPIO_2__MLB_DATA                 0x224 0x5f4 0x8e0 0x7 0x1
+#define MX6QDL_PAD_GPIO_3__ESAI_RX_HF_CLK           0x228 0x5f8 0x834 0x0 0x1
+#define MX6QDL_PAD_GPIO_3__I2C3_SCL                 0x228 0x5f8 0x878 0x2 0x1
+#define MX6QDL_PAD_GPIO_3__XTALOSC_REF_CLK_24M      0x228 0x5f8 0x000 0x3 0x0
+#define MX6QDL_PAD_GPIO_3__CCM_CLKO2                0x228 0x5f8 0x000 0x4 0x0
+#define MX6QDL_PAD_GPIO_3__GPIO1_IO03               0x228 0x5f8 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_3__USB_H1_OC                0x228 0x5f8 0x924 0x6 0x1
+#define MX6QDL_PAD_GPIO_3__MLB_CLK                  0x228 0x5f8 0x8dc 0x7 0x1
+#define MX6QDL_PAD_GPIO_4__ESAI_TX_HF_CLK           0x22c 0x5fc 0x838 0x0 0x1
+#define MX6QDL_PAD_GPIO_4__KEY_COL7                 0x22c 0x5fc 0x8c8 0x2 0x1
+#define MX6QDL_PAD_GPIO_4__GPIO1_IO04               0x22c 0x5fc 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_4__SD2_CD_B                 0x22c 0x5fc 0x000 0x6 0x0
+#define MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3             0x230 0x600 0x84c 0x0 0x1
+#define MX6QDL_PAD_GPIO_5__KEY_ROW7                 0x230 0x600 0x8d4 0x2 0x1
+#define MX6QDL_PAD_GPIO_5__CCM_CLKO1                0x230 0x600 0x000 0x3 0x0
+#define MX6QDL_PAD_GPIO_5__GPIO1_IO05               0x230 0x600 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_5__I2C3_SCL                 0x230 0x600 0x878 0x6 0x2
+#define MX6QDL_PAD_GPIO_5__ARM_EVENTI               0x230 0x600 0x000 0x7 0x0
+#define MX6QDL_PAD_GPIO_6__ESAI_TX_CLK              0x234 0x604 0x840 0x0 0x1
+#define MX6QDL_PAD_GPIO_6__I2C3_SDA                 0x234 0x604 0x87c 0x2 0x2
+#define MX6QDL_PAD_GPIO_6__GPIO1_IO06               0x234 0x604 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_6__SD2_LCTL                 0x234 0x604 0x000 0x6 0x0
+#define MX6QDL_PAD_GPIO_6__MLB_SIG                  0x234 0x604 0x8e4 0x7 0x1
+#define MX6QDL_PAD_GPIO_7__ESAI_TX4_RX1             0x238 0x608 0x854 0x0 0x1
+#define MX6QDL_PAD_GPIO_7__EPIT1_OUT                0x238 0x608 0x000 0x2 0x0
+#define MX6QDL_PAD_GPIO_7__FLEXCAN1_TX              0x238 0x608 0x000 0x3 0x0
+#define MX6QDL_PAD_GPIO_7__UART2_TX_DATA            0x238 0x608 0x000 0x4 0x0
+#define MX6QDL_PAD_GPIO_7__UART2_RX_DATA            0x238 0x608 0x904 0x4 0x2
+#define MX6QDL_PAD_GPIO_7__GPIO1_IO07               0x238 0x608 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_7__SPDIF_LOCK               0x238 0x608 0x000 0x6 0x0
+#define MX6QDL_PAD_GPIO_7__USB_OTG_HOST_MODE        0x238 0x608 0x000 0x7 0x0
+#define MX6QDL_PAD_GPIO_7__I2C4_SCL                 0x238 0x608 0x880 0x8 0x1
+#define MX6QDL_PAD_GPIO_8__ESAI_TX5_RX0             0x23c 0x60c 0x858 0x0 0x1
+#define MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K      0x23c 0x60c 0x000 0x1 0x0
+#define MX6QDL_PAD_GPIO_8__EPIT2_OUT                0x23c 0x60c 0x000 0x2 0x0
+#define MX6QDL_PAD_GPIO_8__FLEXCAN1_RX              0x23c 0x60c 0x7c8 0x3 0x0
+#define MX6QDL_PAD_GPIO_8__UART2_RX_DATA            0x23c 0x60c 0x904 0x4 0x3
+#define MX6QDL_PAD_GPIO_8__UART2_TX_DATA            0x23c 0x60c 0x000 0x4 0x0
+#define MX6QDL_PAD_GPIO_8__GPIO1_IO08               0x23c 0x60c 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_8__SPDIF_SR_CLK             0x23c 0x60c 0x000 0x6 0x0
+#define MX6QDL_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE     0x23c 0x60c 0x000 0x7 0x0
+#define MX6QDL_PAD_GPIO_8__I2C4_SDA                 0x23c 0x60c 0x884 0x8 0x1
+#define MX6QDL_PAD_GPIO_9__ESAI_RX_FS               0x240 0x610 0x82c 0x0 0x1
+#define MX6QDL_PAD_GPIO_9__WDOG1_B                  0x240 0x610 0x000 0x1 0x0
+#define MX6QDL_PAD_GPIO_9__KEY_COL6                 0x240 0x610 0x8c4 0x2 0x1
+#define MX6QDL_PAD_GPIO_9__CCM_REF_EN_B             0x240 0x610 0x000 0x3 0x0
+#define MX6QDL_PAD_GPIO_9__PWM1_OUT                 0x240 0x610 0x000 0x4 0x0
+#define MX6QDL_PAD_GPIO_9__GPIO1_IO09               0x240 0x610 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_9__SD1_WP                   0x240 0x610 0x92c 0x6 0x1
+#define MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK            0x244 0x62c 0x7d8 0x0 0x3
+#define MX6QDL_PAD_KEY_COL0__ENET_RX_DATA3          0x244 0x62c 0x824 0x1 0x0
+#define MX6QDL_PAD_KEY_COL0__AUD5_TXC               0x244 0x62c 0x7c0 0x2 0x1
+#define MX6QDL_PAD_KEY_COL0__KEY_COL0               0x244 0x62c 0x000 0x3 0x0
+#define MX6QDL_PAD_KEY_COL0__UART4_TX_DATA          0x244 0x62c 0x000 0x4 0x0
+#define MX6QDL_PAD_KEY_COL0__UART4_RX_DATA          0x244 0x62c 0x914 0x4 0x2
+#define MX6QDL_PAD_KEY_COL0__GPIO4_IO06             0x244 0x62c 0x000 0x5 0x0
+#define MX6QDL_PAD_KEY_COL0__DCIC1_OUT              0x244 0x62c 0x000 0x6 0x0
+#define MX6QDL_PAD_KEY_COL1__ECSPI1_MISO            0x248 0x630 0x7dc 0x0 0x3
+#define MX6QDL_PAD_KEY_COL1__ENET_MDIO              0x248 0x630 0x810 0x1 0x1
+#define MX6QDL_PAD_KEY_COL1__AUD5_TXFS              0x248 0x630 0x7c4 0x2 0x1
+#define MX6QDL_PAD_KEY_COL1__KEY_COL1               0x248 0x630 0x000 0x3 0x0
+#define MX6QDL_PAD_KEY_COL1__UART5_TX_DATA          0x248 0x630 0x000 0x4 0x0
+#define MX6QDL_PAD_KEY_COL1__UART5_RX_DATA          0x248 0x630 0x91c 0x4 0x2
+#define MX6QDL_PAD_KEY_COL1__GPIO4_IO08             0x248 0x630 0x000 0x5 0x0
+#define MX6QDL_PAD_KEY_COL1__SD1_VSELECT            0x248 0x630 0x000 0x6 0x0
+#define MX6QDL_PAD_KEY_COL2__ECSPI1_SS1             0x24c 0x634 0x7e8 0x0 0x2
+#define MX6QDL_PAD_KEY_COL2__ENET_RX_DATA2          0x24c 0x634 0x820 0x1 0x0
+#define MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX            0x24c 0x634 0x000 0x2 0x0
+#define MX6QDL_PAD_KEY_COL2__KEY_COL2               0x24c 0x634 0x000 0x3 0x0
+#define MX6QDL_PAD_KEY_COL2__ENET_MDC               0x24c 0x634 0x000 0x4 0x0
+#define MX6QDL_PAD_KEY_COL2__GPIO4_IO10             0x24c 0x634 0x000 0x5 0x0
+#define MX6QDL_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE    0x24c 0x634 0x000 0x6 0x0
+#define MX6QDL_PAD_KEY_COL3__ECSPI1_SS3             0x250 0x638 0x7f0 0x0 0x1
+#define MX6QDL_PAD_KEY_COL3__ENET_CRS               0x250 0x638 0x000 0x1 0x0
+#define MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL        0x250 0x638 0x860 0x2 0x1
+#define MX6QDL_PAD_KEY_COL3__KEY_COL3               0x250 0x638 0x000 0x3 0x0
+#define MX6QDL_PAD_KEY_COL3__I2C2_SCL               0x250 0x638 0x870 0x4 0x1
+#define MX6QDL_PAD_KEY_COL3__GPIO4_IO12             0x250 0x638 0x000 0x5 0x0
+#define MX6QDL_PAD_KEY_COL3__SPDIF_IN               0x250 0x638 0x8f0 0x6 0x3
+#define MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX            0x254 0x63c 0x000 0x0 0x0
+#define MX6QDL_PAD_KEY_COL4__IPU1_SISG4             0x254 0x63c 0x000 0x1 0x0
+#define MX6QDL_PAD_KEY_COL4__USB_OTG_OC             0x254 0x63c 0x920 0x2 0x1
+#define MX6QDL_PAD_KEY_COL4__KEY_COL4               0x254 0x63c 0x000 0x3 0x0
+#define MX6QDL_PAD_KEY_COL4__UART5_RTS_B            0x254 0x63c 0x918 0x4 0x2
+#define MX6QDL_PAD_KEY_COL4__UART5_CTS_B            0x254 0x63c 0x000 0x4 0x0
+#define MX6QDL_PAD_KEY_COL4__GPIO4_IO14             0x254 0x63c 0x000 0x5 0x0
+#define MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI            0x258 0x640 0x7e0 0x0 0x3
+#define MX6QDL_PAD_KEY_ROW0__ENET_TX_DATA3          0x258 0x640 0x000 0x1 0x0
+#define MX6QDL_PAD_KEY_ROW0__AUD5_TXD               0x258 0x640 0x7b4 0x2 0x1
+#define MX6QDL_PAD_KEY_ROW0__KEY_ROW0               0x258 0x640 0x000 0x3 0x0
+#define MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA          0x258 0x640 0x914 0x4 0x3
+#define MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA          0x258 0x640 0x000 0x4 0x0
+#define MX6QDL_PAD_KEY_ROW0__GPIO4_IO07             0x258 0x640 0x000 0x5 0x0
+#define MX6QDL_PAD_KEY_ROW0__DCIC2_OUT              0x258 0x640 0x000 0x6 0x0
+#define MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0             0x25c 0x644 0x7e4 0x0 0x3
+#define MX6QDL_PAD_KEY_ROW1__ENET_COL               0x25c 0x644 0x000 0x1 0x0
+#define MX6QDL_PAD_KEY_ROW1__AUD5_RXD               0x25c 0x644 0x7b0 0x2 0x1
+#define MX6QDL_PAD_KEY_ROW1__KEY_ROW1               0x25c 0x644 0x000 0x3 0x0
+#define MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA          0x25c 0x644 0x91c 0x4 0x3
+#define MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA          0x25c 0x644 0x000 0x4 0x0
+#define MX6QDL_PAD_KEY_ROW1__GPIO4_IO09             0x25c 0x644 0x000 0x5 0x0
+#define MX6QDL_PAD_KEY_ROW1__SD2_VSELECT            0x25c 0x644 0x000 0x6 0x0
+#define MX6QDL_PAD_KEY_ROW2__ECSPI1_SS2             0x260 0x648 0x7ec 0x0 0x1
+#define MX6QDL_PAD_KEY_ROW2__ENET_TX_DATA2          0x260 0x648 0x000 0x1 0x0
+#define MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX            0x260 0x648 0x7c8 0x2 0x1
+#define MX6QDL_PAD_KEY_ROW2__KEY_ROW2               0x260 0x648 0x000 0x3 0x0
+#define MX6QDL_PAD_KEY_ROW2__SD2_VSELECT            0x260 0x648 0x000 0x4 0x0
+#define MX6QDL_PAD_KEY_ROW2__GPIO4_IO11             0x260 0x648 0x000 0x5 0x0
+#define MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE       0x260 0x648 0x85c 0x6 0x1
+#define MX6QDL_PAD_KEY_ROW3__ASRC_EXT_CLK           0x264 0x64c 0x794 0x1 0x2
+#define MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA        0x264 0x64c 0x864 0x2 0x1
+#define MX6QDL_PAD_KEY_ROW3__KEY_ROW3               0x264 0x64c 0x000 0x3 0x0
+#define MX6QDL_PAD_KEY_ROW3__I2C2_SDA               0x264 0x64c 0x874 0x4 0x1
+#define MX6QDL_PAD_KEY_ROW3__GPIO4_IO13             0x264 0x64c 0x000 0x5 0x0
+#define MX6QDL_PAD_KEY_ROW3__SD1_VSELECT            0x264 0x64c 0x000 0x6 0x0
+#define MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX            0x268 0x650 0x7cc 0x0 0x0
+#define MX6QDL_PAD_KEY_ROW4__IPU1_SISG5             0x268 0x650 0x000 0x1 0x0
+#define MX6QDL_PAD_KEY_ROW4__USB_OTG_PWR            0x268 0x650 0x000 0x2 0x0
+#define MX6QDL_PAD_KEY_ROW4__KEY_ROW4               0x268 0x650 0x000 0x3 0x0
+#define MX6QDL_PAD_KEY_ROW4__UART5_CTS_B            0x268 0x650 0x000 0x4 0x0
+#define MX6QDL_PAD_KEY_ROW4__UART5_RTS_B            0x268 0x650 0x918 0x4 0x3
+#define MX6QDL_PAD_KEY_ROW4__GPIO4_IO15             0x268 0x650 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_ALE__NAND_ALE              0x26c 0x654 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_ALE__SD4_RESET             0x26c 0x654 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_ALE__GPIO6_IO08            0x26c 0x654 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_CLE__NAND_CLE              0x270 0x658 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_CLE__GPIO6_IO07            0x270 0x658 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_CS0__NAND_CE0_B            0x274 0x65c 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_CS0__GPIO6_IO11            0x274 0x65c 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_CS1__NAND_CE1_B            0x278 0x660 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_CS1__SD4_VSELECT           0x278 0x660 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_CS1__SD3_VSELECT           0x278 0x660 0x000 0x2 0x0
+#define MX6QDL_PAD_NANDF_CS1__GPIO6_IO14            0x278 0x660 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_CS2__NAND_CE2_B            0x27c 0x664 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_CS2__IPU1_SISG0            0x27c 0x664 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_CS2__ESAI_TX0              0x27c 0x664 0x844 0x2 0x1
+#define MX6QDL_PAD_NANDF_CS2__EIM_CRE               0x27c 0x664 0x000 0x3 0x0
+#define MX6QDL_PAD_NANDF_CS2__CCM_CLKO2             0x27c 0x664 0x000 0x4 0x0
+#define MX6QDL_PAD_NANDF_CS2__GPIO6_IO15            0x27c 0x664 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_CS3__NAND_CE3_B            0x280 0x668 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_CS3__IPU1_SISG1            0x280 0x668 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_CS3__ESAI_TX1              0x280 0x668 0x848 0x2 0x1
+#define MX6QDL_PAD_NANDF_CS3__EIM_ADDR26            0x280 0x668 0x000 0x3 0x0
+#define MX6QDL_PAD_NANDF_CS3__GPIO6_IO16            0x280 0x668 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_CS3__I2C4_SDA              0x280 0x668 0x884 0x9 0x2
+#define MX6QDL_PAD_NANDF_D0__NAND_DATA00            0x284 0x66c 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_D0__SD1_DATA4              0x284 0x66c 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_D0__GPIO2_IO00             0x284 0x66c 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_D1__NAND_DATA01            0x288 0x670 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_D1__SD1_DATA5              0x288 0x670 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_D1__GPIO2_IO01             0x288 0x670 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_D2__NAND_DATA02            0x28c 0x674 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_D2__SD1_DATA6              0x28c 0x674 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_D2__GPIO2_IO02             0x28c 0x674 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_D3__NAND_DATA03            0x290 0x678 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_D3__SD1_DATA7              0x290 0x678 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_D3__GPIO2_IO03             0x290 0x678 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_D4__NAND_DATA04            0x294 0x67c 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_D4__SD2_DATA4              0x294 0x67c 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_D4__GPIO2_IO04             0x294 0x67c 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_D5__NAND_DATA05            0x298 0x680 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_D5__SD2_DATA5              0x298 0x680 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_D5__GPIO2_IO05             0x298 0x680 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_D6__NAND_DATA06            0x29c 0x684 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_D6__SD2_DATA6              0x29c 0x684 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_D6__GPIO2_IO06             0x29c 0x684 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_D7__NAND_DATA07            0x2a0 0x688 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_D7__SD2_DATA7              0x2a0 0x688 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_D7__GPIO2_IO07             0x2a0 0x688 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_RB0__NAND_READY_B          0x2a4 0x68c 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_RB0__GPIO6_IO10            0x2a4 0x68c 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_WP_B__NAND_WP_B            0x2a8 0x690 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09           0x2a8 0x690 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_WP_B__I2C4_SCL             0x2a8 0x690 0x880 0x9 0x2
+#define MX6QDL_PAD_RGMII_RD0__HSI_RX_READY          0x2ac 0x694 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_RD0__RGMII_RD0             0x2ac 0x694 0x818 0x1 0x1
+#define MX6QDL_PAD_RGMII_RD0__GPIO6_IO25            0x2ac 0x694 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_RD1__HSI_TX_FLAG           0x2b0 0x698 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_RD1__RGMII_RD1             0x2b0 0x698 0x81c 0x1 0x1
+#define MX6QDL_PAD_RGMII_RD1__GPIO6_IO27            0x2b0 0x698 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_RD2__HSI_TX_DATA           0x2b4 0x69c 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_RD2__RGMII_RD2             0x2b4 0x69c 0x820 0x1 0x1
+#define MX6QDL_PAD_RGMII_RD2__GPIO6_IO28            0x2b4 0x69c 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_RD3__HSI_TX_WAKE           0x2b8 0x6a0 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_RD3__RGMII_RD3             0x2b8 0x6a0 0x824 0x1 0x1
+#define MX6QDL_PAD_RGMII_RD3__GPIO6_IO29            0x2b8 0x6a0 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA        0x2bc 0x6a4 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL       0x2bc 0x6a4 0x828 0x1 0x1
+#define MX6QDL_PAD_RGMII_RX_CTL__GPIO6_IO24         0x2bc 0x6a4 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE         0x2c0 0x6a8 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_RXC__RGMII_RXC             0x2c0 0x6a8 0x814 0x1 0x1
+#define MX6QDL_PAD_RGMII_RXC__GPIO6_IO30            0x2c0 0x6a8 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_TD0__HSI_TX_READY          0x2c4 0x6ac 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_TD0__RGMII_TD0             0x2c4 0x6ac 0x000 0x1 0x0
+#define MX6QDL_PAD_RGMII_TD0__GPIO6_IO20            0x2c4 0x6ac 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_TD1__HSI_RX_FLAG           0x2c8 0x6b0 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_TD1__RGMII_TD1             0x2c8 0x6b0 0x000 0x1 0x0
+#define MX6QDL_PAD_RGMII_TD1__GPIO6_IO21            0x2c8 0x6b0 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_TD2__HSI_RX_DATA           0x2cc 0x6b4 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_TD2__RGMII_TD2             0x2cc 0x6b4 0x000 0x1 0x0
+#define MX6QDL_PAD_RGMII_TD2__GPIO6_IO22            0x2cc 0x6b4 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_TD3__HSI_RX_WAKE           0x2d0 0x6b8 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_TD3__RGMII_TD3             0x2d0 0x6b8 0x000 0x1 0x0
+#define MX6QDL_PAD_RGMII_TD3__GPIO6_IO23            0x2d0 0x6b8 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE      0x2d4 0x6bc 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL       0x2d4 0x6bc 0x000 0x1 0x0
+#define MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26         0x2d4 0x6bc 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_TX_CTL__ENET_REF_CLK       0x2d4 0x6bc 0x80c 0x7 0x1
+#define MX6QDL_PAD_RGMII_TXC__USB_H2_DATA           0x2d8 0x6c0 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_TXC__RGMII_TXC             0x2d8 0x6c0 0x000 0x1 0x0
+#define MX6QDL_PAD_RGMII_TXC__SPDIF_EXT_CLK         0x2d8 0x6c0 0x8f4 0x2 0x1
+#define MX6QDL_PAD_RGMII_TXC__GPIO6_IO19            0x2d8 0x6c0 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M   0x2d8 0x6c0 0x000 0x7 0x0
+#define MX6QDL_PAD_SD1_CLK__SD1_CLK                 0x2dc 0x6c4 0x928 0x0 0x1
+#define MX6QDL_PAD_SD1_CLK__GPT_CLKIN               0x2dc 0x6c4 0x000 0x3 0x0
+#define MX6QDL_PAD_SD1_CLK__GPIO1_IO20              0x2dc 0x6c4 0x000 0x5 0x0
+#define MX6QDL_PAD_SD1_CMD__SD1_CMD                 0x2e0 0x6c8 0x000 0x0 0x0
+#define MX6QDL_PAD_SD1_CMD__PWM4_OUT                0x2e0 0x6c8 0x000 0x2 0x0
+#define MX6QDL_PAD_SD1_CMD__GPT_COMPARE1            0x2e0 0x6c8 0x000 0x3 0x0
+#define MX6QDL_PAD_SD1_CMD__GPIO1_IO18              0x2e0 0x6c8 0x000 0x5 0x0
+#define MX6QDL_PAD_SD1_DAT0__SD1_DATA0              0x2e4 0x6cc 0x000 0x0 0x0
+#define MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1           0x2e4 0x6cc 0x000 0x3 0x0
+#define MX6QDL_PAD_SD1_DAT0__GPIO1_IO16             0x2e4 0x6cc 0x000 0x5 0x0
+#define MX6QDL_PAD_SD1_DAT1__SD1_DATA1              0x2e8 0x6d0 0x000 0x0 0x0
+#define MX6QDL_PAD_SD1_DAT1__PWM3_OUT               0x2e8 0x6d0 0x000 0x2 0x0
+#define MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2           0x2e8 0x6d0 0x000 0x3 0x0
+#define MX6QDL_PAD_SD1_DAT1__GPIO1_IO17             0x2e8 0x6d0 0x000 0x5 0x0
+#define MX6QDL_PAD_SD1_DAT2__SD1_DATA2              0x2ec 0x6d4 0x000 0x0 0x0
+#define MX6QDL_PAD_SD1_DAT2__GPT_COMPARE2           0x2ec 0x6d4 0x000 0x2 0x0
+#define MX6QDL_PAD_SD1_DAT2__PWM2_OUT               0x2ec 0x6d4 0x000 0x3 0x0
+#define MX6QDL_PAD_SD1_DAT2__WDOG1_B                0x2ec 0x6d4 0x000 0x4 0x0
+#define MX6QDL_PAD_SD1_DAT2__GPIO1_IO19             0x2ec 0x6d4 0x000 0x5 0x0
+#define MX6QDL_PAD_SD1_DAT2__WDOG1_RESET_B_DEB      0x2ec 0x6d4 0x000 0x6 0x0
+#define MX6QDL_PAD_SD1_DAT3__SD1_DATA3              0x2f0 0x6d8 0x000 0x0 0x0
+#define MX6QDL_PAD_SD1_DAT3__GPT_COMPARE3           0x2f0 0x6d8 0x000 0x2 0x0
+#define MX6QDL_PAD_SD1_DAT3__PWM1_OUT               0x2f0 0x6d8 0x000 0x3 0x0
+#define MX6QDL_PAD_SD1_DAT3__WDOG2_B                0x2f0 0x6d8 0x000 0x4 0x0
+#define MX6QDL_PAD_SD1_DAT3__GPIO1_IO21             0x2f0 0x6d8 0x000 0x5 0x0
+#define MX6QDL_PAD_SD1_DAT3__WDOG2_RESET_B_DEB      0x2f0 0x6d8 0x000 0x6 0x0
+#define MX6QDL_PAD_SD2_CLK__SD2_CLK                 0x2f4 0x6dc 0x930 0x0 0x1
+#define MX6QDL_PAD_SD2_CLK__KEY_COL5                0x2f4 0x6dc 0x8c0 0x2 0x3
+#define MX6QDL_PAD_SD2_CLK__AUD4_RXFS               0x2f4 0x6dc 0x7a4 0x3 0x1
+#define MX6QDL_PAD_SD2_CLK__GPIO1_IO10              0x2f4 0x6dc 0x000 0x5 0x0
+#define MX6QDL_PAD_SD2_CMD__SD2_CMD                 0x2f8 0x6e0 0x000 0x0 0x0
+#define MX6QDL_PAD_SD2_CMD__KEY_ROW5                0x2f8 0x6e0 0x8cc 0x2 0x2
+#define MX6QDL_PAD_SD2_CMD__AUD4_RXC                0x2f8 0x6e0 0x7a0 0x3 0x1
+#define MX6QDL_PAD_SD2_CMD__GPIO1_IO11              0x2f8 0x6e0 0x000 0x5 0x0
+#define MX6QDL_PAD_SD2_DAT0__SD2_DATA0              0x2fc 0x6e4 0x000 0x0 0x0
+#define MX6QDL_PAD_SD2_DAT0__AUD4_RXD               0x2fc 0x6e4 0x798 0x3 0x1
+#define MX6QDL_PAD_SD2_DAT0__KEY_ROW7               0x2fc 0x6e4 0x8d4 0x4 0x2
+#define MX6QDL_PAD_SD2_DAT0__GPIO1_IO15             0x2fc 0x6e4 0x000 0x5 0x0
+#define MX6QDL_PAD_SD2_DAT0__DCIC2_OUT              0x2fc 0x6e4 0x000 0x6 0x0
+#define MX6QDL_PAD_SD2_DAT1__SD2_DATA1              0x300 0x6e8 0x000 0x0 0x0
+#define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B              0x300 0x6e8 0x000 0x2 0x0
+#define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS              0x300 0x6e8 0x7ac 0x3 0x1
+#define MX6QDL_PAD_SD2_DAT1__KEY_COL7               0x300 0x6e8 0x8c8 0x4 0x2
+#define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14             0x300 0x6e8 0x000 0x5 0x0
+#define MX6QDL_PAD_SD2_DAT2__SD2_DATA2              0x304 0x6ec 0x000 0x0 0x0
+#define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B              0x304 0x6ec 0x000 0x2 0x0
+#define MX6QDL_PAD_SD2_DAT2__AUD4_TXD               0x304 0x6ec 0x79c 0x3 0x1
+#define MX6QDL_PAD_SD2_DAT2__KEY_ROW6               0x304 0x6ec 0x8d0 0x4 0x2
+#define MX6QDL_PAD_SD2_DAT2__GPIO1_IO13             0x304 0x6ec 0x000 0x5 0x0
+#define MX6QDL_PAD_SD2_DAT3__SD2_DATA3              0x308 0x6f0 0x000 0x0 0x0
+#define MX6QDL_PAD_SD2_DAT3__KEY_COL6               0x308 0x6f0 0x8c4 0x2 0x2
+#define MX6QDL_PAD_SD2_DAT3__AUD4_TXC               0x308 0x6f0 0x7a8 0x3 0x1
+#define MX6QDL_PAD_SD2_DAT3__GPIO1_IO12             0x308 0x6f0 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_CLK__SD3_CLK                 0x30c 0x6f4 0x934 0x0 0x1
+#define MX6QDL_PAD_SD3_CLK__UART2_RTS_B             0x30c 0x6f4 0x900 0x1 0x2
+#define MX6QDL_PAD_SD3_CLK__UART2_CTS_B             0x30c 0x6f4 0x000 0x1 0x0
+#define MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX             0x30c 0x6f4 0x7c8 0x2 0x2
+#define MX6QDL_PAD_SD3_CLK__GPIO7_IO03              0x30c 0x6f4 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_CMD__SD3_CMD                 0x310 0x6f8 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_CMD__UART2_CTS_B             0x310 0x6f8 0x000 0x1 0x0
+#define MX6QDL_PAD_SD3_CMD__UART2_RTS_B             0x310 0x6f8 0x900 0x1 0x3
+#define MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX             0x310 0x6f8 0x000 0x2 0x0
+#define MX6QDL_PAD_SD3_CMD__GPIO7_IO02              0x310 0x6f8 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_DAT0__SD3_DATA0              0x314 0x6fc 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_DAT0__UART1_CTS_B            0x314 0x6fc 0x000 0x1 0x0
+#define MX6QDL_PAD_SD3_DAT0__UART1_RTS_B            0x314 0x6fc 0x8f8 0x1 0x2
+#define MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX            0x314 0x6fc 0x000 0x2 0x0
+#define MX6QDL_PAD_SD3_DAT0__GPIO7_IO04             0x314 0x6fc 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_DAT1__SD3_DATA1              0x318 0x700 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_DAT1__UART1_RTS_B            0x318 0x700 0x8f8 0x1 0x3
+#define MX6QDL_PAD_SD3_DAT1__UART1_CTS_B            0x318 0x700 0x000 0x1 0x0
+#define MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX            0x318 0x700 0x7cc 0x2 0x1
+#define MX6QDL_PAD_SD3_DAT1__GPIO7_IO05             0x318 0x700 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_DAT2__SD3_DATA2              0x31c 0x704 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_DAT2__GPIO7_IO06             0x31c 0x704 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_DAT3__SD3_DATA3              0x320 0x708 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_DAT3__UART3_CTS_B            0x320 0x708 0x000 0x1 0x0
+#define MX6QDL_PAD_SD3_DAT3__UART3_RTS_B            0x320 0x708 0x908 0x1 0x4
+#define MX6QDL_PAD_SD3_DAT3__GPIO7_IO07             0x320 0x708 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_DAT4__SD3_DATA4              0x324 0x70c 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA          0x324 0x70c 0x904 0x1 0x4
+#define MX6QDL_PAD_SD3_DAT4__UART2_TX_DATA          0x324 0x70c 0x000 0x1 0x0
+#define MX6QDL_PAD_SD3_DAT4__GPIO7_IO01             0x324 0x70c 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_DAT5__SD3_DATA5              0x328 0x710 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA          0x328 0x710 0x000 0x1 0x0
+#define MX6QDL_PAD_SD3_DAT5__UART2_RX_DATA          0x328 0x710 0x904 0x1 0x5
+#define MX6QDL_PAD_SD3_DAT5__GPIO7_IO00             0x328 0x710 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_DAT6__SD3_DATA6              0x32c 0x714 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA          0x32c 0x714 0x8fc 0x1 0x2
+#define MX6QDL_PAD_SD3_DAT6__UART1_TX_DATA          0x32c 0x714 0x000 0x1 0x0
+#define MX6QDL_PAD_SD3_DAT6__GPIO6_IO18             0x32c 0x714 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_DAT7__SD3_DATA7              0x330 0x718 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA          0x330 0x718 0x000 0x1 0x0
+#define MX6QDL_PAD_SD3_DAT7__UART1_RX_DATA          0x330 0x718 0x8fc 0x1 0x3
+#define MX6QDL_PAD_SD3_DAT7__GPIO6_IO17             0x330 0x718 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_RST__SD3_RESET               0x334 0x71c 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_RST__UART3_RTS_B             0x334 0x71c 0x908 0x1 0x5
+#define MX6QDL_PAD_SD3_RST__UART3_CTS_B             0x334 0x71c 0x000 0x1 0x0
+#define MX6QDL_PAD_SD3_RST__GPIO7_IO08              0x334 0x71c 0x000 0x5 0x0
+#define MX6QDL_PAD_SD4_CLK__SD4_CLK                 0x338 0x720 0x938 0x0 0x1
+#define MX6QDL_PAD_SD4_CLK__NAND_WE_B               0x338 0x720 0x000 0x1 0x0
+#define MX6QDL_PAD_SD4_CLK__UART3_RX_DATA           0x338 0x720 0x90c 0x2 0x2
+#define MX6QDL_PAD_SD4_CLK__UART3_TX_DATA           0x338 0x720 0x000 0x2 0x0
+#define MX6QDL_PAD_SD4_CLK__GPIO7_IO10              0x338 0x720 0x000 0x5 0x0
+#define MX6QDL_PAD_SD4_CMD__SD4_CMD                 0x33c 0x724 0x000 0x0 0x0
+#define MX6QDL_PAD_SD4_CMD__NAND_RE_B               0x33c 0x724 0x000 0x1 0x0
+#define MX6QDL_PAD_SD4_CMD__UART3_TX_DATA           0x33c 0x724 0x000 0x2 0x0
+#define MX6QDL_PAD_SD4_CMD__UART3_RX_DATA           0x33c 0x724 0x90c 0x2 0x3
+#define MX6QDL_PAD_SD4_CMD__GPIO7_IO09              0x33c 0x724 0x000 0x5 0x0
+#define MX6QDL_PAD_SD4_DAT0__SD4_DATA0              0x340 0x728 0x000 0x1 0x0
+#define MX6QDL_PAD_SD4_DAT0__NAND_DQS               0x340 0x728 0x000 0x2 0x0
+#define MX6QDL_PAD_SD4_DAT0__GPIO2_IO08             0x340 0x728 0x000 0x5 0x0
+#define MX6QDL_PAD_SD4_DAT1__SD4_DATA1              0x344 0x72c 0x000 0x1 0x0
+#define MX6QDL_PAD_SD4_DAT1__PWM3_OUT               0x344 0x72c 0x000 0x2 0x0
+#define MX6QDL_PAD_SD4_DAT1__GPIO2_IO09             0x344 0x72c 0x000 0x5 0x0
+#define MX6QDL_PAD_SD4_DAT2__SD4_DATA2              0x348 0x730 0x000 0x1 0x0
+#define MX6QDL_PAD_SD4_DAT2__PWM4_OUT               0x348 0x730 0x000 0x2 0x0
+#define MX6QDL_PAD_SD4_DAT2__GPIO2_IO10             0x348 0x730 0x000 0x5 0x0
+#define MX6QDL_PAD_SD4_DAT3__SD4_DATA3              0x34c 0x734 0x000 0x1 0x0
+#define MX6QDL_PAD_SD4_DAT3__GPIO2_IO11             0x34c 0x734 0x000 0x5 0x0
+#define MX6QDL_PAD_SD4_DAT4__SD4_DATA4              0x350 0x738 0x000 0x1 0x0
+#define MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA          0x350 0x738 0x904 0x2 0x6
+#define MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA          0x350 0x738 0x000 0x2 0x0
+#define MX6QDL_PAD_SD4_DAT4__GPIO2_IO12             0x350 0x738 0x000 0x5 0x0
+#define MX6QDL_PAD_SD4_DAT5__SD4_DATA5              0x354 0x73c 0x000 0x1 0x0
+#define MX6QDL_PAD_SD4_DAT5__UART2_RTS_B            0x354 0x73c 0x900 0x2 0x4
+#define MX6QDL_PAD_SD4_DAT5__UART2_CTS_B            0x354 0x73c 0x000 0x2 0x0
+#define MX6QDL_PAD_SD4_DAT5__GPIO2_IO13             0x354 0x73c 0x000 0x5 0x0
+#define MX6QDL_PAD_SD4_DAT6__SD4_DATA6              0x358 0x740 0x000 0x1 0x0
+#define MX6QDL_PAD_SD4_DAT6__UART2_CTS_B            0x358 0x740 0x000 0x2 0x0
+#define MX6QDL_PAD_SD4_DAT6__UART2_RTS_B            0x358 0x740 0x900 0x2 0x5
+#define MX6QDL_PAD_SD4_DAT6__GPIO2_IO14             0x358 0x740 0x000 0x5 0x0
+#define MX6QDL_PAD_SD4_DAT7__SD4_DATA7              0x35c 0x744 0x000 0x1 0x0
+#define MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA          0x35c 0x744 0x000 0x2 0x0
+#define MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA          0x35c 0x744 0x904 0x2 0x7
+#define MX6QDL_PAD_SD4_DAT7__GPIO2_IO15             0x35c 0x744 0x000 0x5 0x0
 
 #endif /* __DTS_IMX6DL_PINFUNC_H */
diff --git a/arch/arm/boot/dts/imx6dl-sabreauto.dts b/arch/arm/boot/dts/imx6dl-sabreauto.dts
index 95da71185a4a..a6ce7b487ad7 100644
--- a/arch/arm/boot/dts/imx6dl-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6dl-sabreauto.dts
@@ -15,25 +15,3 @@
         model = "Freescale i.MX6 DualLite/Solo SABRE Automotive Board";
         compatible = "fsl,imx6dl-sabreauto", "fsl,imx6dl";
 };
-
-&iomuxc {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_hog>;
-
-        hog {
-                pinctrl_hog: hoggrp {
-                        fsl,pins = <
-                                MX6DL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
-                                MX6DL_PAD_SD2_DAT2__GPIO1_IO13  0x80000000
-                        >;
-                };
-        };
-
-        ecspi1 {
-                pinctrl_ecspi1_sabreauto: ecspi1-sabreauto {
-                        fsl,pins = <
-                                MX6DL_PAD_EIM_D19__GPIO3_IO19  0x80000000
-                        >;
-                };
-        };
-};
diff --git a/arch/arm/boot/dts/imx6dl-sabresd.dts b/arch/arm/boot/dts/imx6dl-sabresd.dts
index 8989df2b89e5..1e45f2f9d0b6 100644
--- a/arch/arm/boot/dts/imx6dl-sabresd.dts
+++ b/arch/arm/boot/dts/imx6dl-sabresd.dts
@@ -15,22 +15,3 @@
         model = "Freescale i.MX6 DualLite SABRE Smart Device Board";
         compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl";
 };
-
-&iomuxc {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_hog>;
-
-        hog {
-                pinctrl_hog: hoggrp {
-                        fsl,pins = <
-                                MX6DL_PAD_GPIO_4__GPIO1_IO04   0x80000000
-                                MX6DL_PAD_GPIO_5__GPIO1_IO05   0x80000000
-                                MX6DL_PAD_NANDF_D0__GPIO2_IO00 0x80000000
-                                MX6DL_PAD_NANDF_D1__GPIO2_IO01 0x80000000
-                                MX6DL_PAD_NANDF_D2__GPIO2_IO02 0x80000000
-                                MX6DL_PAD_NANDF_D3__GPIO2_IO03 0x80000000
-                                MX6DL_PAD_GPIO_0__CCM_CLKO1    0x130b0
-                        >;
-                };
-        };
-};
diff --git a/arch/arm/boot/dts/imx6dl-wandboard.dts b/arch/arm/boot/dts/imx6dl-wandboard.dts
index bfc59c3566a4..e672891c1626 100644
--- a/arch/arm/boot/dts/imx6dl-wandboard.dts
+++ b/arch/arm/boot/dts/imx6dl-wandboard.dts
@@ -10,6 +10,7 @@
  */
 /dts-v1/;
 #include "imx6dl.dtsi"
+#include "imx6qdl-wandboard.dtsi"
 
 / {
         model = "Wandboard i.MX6 Dual Lite Board";
@@ -19,26 +20,3 @@
                 reg = <0x10000000 0x40000000>;
         };
 };
-
-&fec {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_enet_1>;
-        phy-mode = "rgmii";
-        status = "okay";
-};
-
-&uart1 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart1_1>;
-        status = "okay";
-};
-
-&usbh1 {
-        status = "okay";
-};
-
-&usdhc3 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_usdhc3_2>;
-        status = "okay";
-};
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index 2b3ecd679350..9e8ae118fdd4 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -8,8 +8,8 @@
  *
  */
 
-#include "imx6qdl.dtsi"
 #include "imx6dl-pinfunc.h"
+#include "imx6qdl.dtsi"
 
 / {
         cpus {
@@ -32,238 +32,15 @@
         };
 
         soc {
+                ocram: sram@00900000 {
+                        compatible = "mmio-sram";
+                        reg = <0x00900000 0x20000>;
+                        clocks = <&clks 142>;
+                };
+
                 aips1: aips-bus@02000000 {
                         iomuxc: iomuxc@020e0000 {
                                 compatible = "fsl,imx6dl-iomuxc";
-                                reg = <0x020e0000 0x4000>;
-
-                                audmux {
-                                        pinctrl_audmux_2: audmux-2 {
-                                                fsl,pins = <
-                                                        MX6DL_PAD_CSI0_DAT7__AUD3_RXD  0x80000000
-                                                        MX6DL_PAD_CSI0_DAT4__AUD3_TXC  0x80000000
-                                                        MX6DL_PAD_CSI0_DAT5__AUD3_TXD  0x80000000
-                                                        MX6DL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
-                                                >;
-                                        };
-                                };
-
-                                ecspi1 {
-                                        pinctrl_ecspi1_1: ecspi1grp-1 {
-                                                fsl,pins = <
-                                                        MX6DL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
-                                                        MX6DL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
-                                                        MX6DL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
-                                                >;
-                                        };
-                                };
-
-                                enet {
-                                        pinctrl_enet_1: enetgrp-1 {
-                                                fsl,pins = <
-                                                        MX6DL_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
-                                                        MX6DL_PAD_ENET_MDC__ENET_MDC         0x1b0b0
-                                                        MX6DL_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
-                                                        MX6DL_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
-                                                        MX6DL_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
-                                                        MX6DL_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
-                                                        MX6DL_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
-                                                        MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
-                                                        MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
-                                                        MX6DL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
-                                                        MX6DL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
-                                                        MX6DL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
-                                                        MX6DL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
-                                                        MX6DL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
-                                                        MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
-                                                        MX6DL_PAD_GPIO_16__ENET_REF_CLK      0x4001b0a8
-                                                >;
-                                        };
-
-                                        pinctrl_enet_2: enetgrp-2 {
-                                                fsl,pins = <
-                                                        MX6DL_PAD_KEY_COL1__ENET_MDIO        0x1b0b0
-                                                        MX6DL_PAD_KEY_COL2__ENET_MDC         0x1b0b0
-                                                        MX6DL_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
-                                                        MX6DL_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
-                                                        MX6DL_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
-                                                        MX6DL_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
-                                                        MX6DL_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
-                                                        MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
-                                                        MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
-                                                        MX6DL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
-                                                        MX6DL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
-                                                        MX6DL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
-                                                        MX6DL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
-                                                        MX6DL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
-                                                        MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
-                                                >;
-                                        };
-                                };
-
-                                gpmi-nand {
-                                        pinctrl_gpmi_nand_1: gpmi-nand-1 {
-                                                fsl,pins = <
-                                                        MX6DL_PAD_NANDF_CLE__NAND_CLE     0xb0b1
-                                                        MX6DL_PAD_NANDF_ALE__NAND_ALE     0xb0b1
-                                                        MX6DL_PAD_NANDF_WP_B__NAND_WP_B   0xb0b1
-                                                        MX6DL_PAD_NANDF_RB0__NAND_READY_B 0xb000
-                                                        MX6DL_PAD_NANDF_CS0__NAND_CE0_B   0xb0b1
-                                                        MX6DL_PAD_NANDF_CS1__NAND_CE1_B   0xb0b1
-                                                        MX6DL_PAD_SD4_CMD__NAND_RE_B      0xb0b1
-                                                        MX6DL_PAD_SD4_CLK__NAND_WE_B      0xb0b1
-                                                        MX6DL_PAD_NANDF_D0__NAND_DATA00   0xb0b1
-                                                        MX6DL_PAD_NANDF_D1__NAND_DATA01   0xb0b1
-                                                        MX6DL_PAD_NANDF_D2__NAND_DATA02   0xb0b1
-                                                        MX6DL_PAD_NANDF_D3__NAND_DATA03   0xb0b1
-                                                        MX6DL_PAD_NANDF_D4__NAND_DATA04   0xb0b1
-                                                        MX6DL_PAD_NANDF_D5__NAND_DATA05   0xb0b1
-                                                        MX6DL_PAD_NANDF_D6__NAND_DATA06   0xb0b1
-                                                        MX6DL_PAD_NANDF_D7__NAND_DATA07   0xb0b1
-                                                        MX6DL_PAD_SD4_DAT0__NAND_DQS      0x00b1
-                                                >;
-                                        };
-                                };
-
-                                i2c1 {
-                                        pinctrl_i2c1_2: i2c1grp-2 {
-                                                fsl,pins = <
-                                                        MX6DL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
-                                                        MX6DL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
-                                                >;
-                                        };
-                                };
-
-                                uart1 {
-                                        pinctrl_uart1_1: uart1grp-1 {
-                                                fsl,pins = <
-                                                        MX6DL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
-                                                        MX6DL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
-                                                >;
-                                        };
-                                };
-
-                                uart4 {
-                                        pinctrl_uart4_1: uart4grp-1 {
-                                                fsl,pins = <
-                                                        MX6DL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
-                                                        MX6DL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
-                                                >;
-                                        };
-                                };
-
-                                usbotg {
-                                        pinctrl_usbotg_2: usbotggrp-2 {
-                                                fsl,pins = <
-                                                        MX6DL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
-                                                >;
-                                        };
-                                };
-
-                                usdhc2 {
-                                        pinctrl_usdhc2_1: usdhc2grp-1 {
-                                                fsl,pins = <
-                                                        MX6DL_PAD_SD2_CMD__SD2_CMD    0x17059
-                                                        MX6DL_PAD_SD2_CLK__SD2_CLK    0x10059
-                                                        MX6DL_PAD_SD2_DAT0__SD2_DATA0 0x17059
-                                                        MX6DL_PAD_SD2_DAT1__SD2_DATA1 0x17059
-                                                        MX6DL_PAD_SD2_DAT2__SD2_DATA2 0x17059
-                                                        MX6DL_PAD_SD2_DAT3__SD2_DATA3 0x17059
-                                                        MX6DL_PAD_NANDF_D4__SD2_DATA4 0x17059
-                                                        MX6DL_PAD_NANDF_D5__SD2_DATA5 0x17059
-                                                        MX6DL_PAD_NANDF_D6__SD2_DATA6 0x17059
-                                                        MX6DL_PAD_NANDF_D7__SD2_DATA7 0x17059
-                                                >;
-                                        };
-                                };
-
-                                usdhc3 {
-                                        pinctrl_usdhc3_1: usdhc3grp-1 {
-                                                fsl,pins = <
-                                                        MX6DL_PAD_SD3_CMD__SD3_CMD    0x17059
-                                                        MX6DL_PAD_SD3_CLK__SD3_CLK    0x10059
-                                                        MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059
-                                                        MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059
-                                                        MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059
-                                                        MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059
-                                                        MX6DL_PAD_SD3_DAT4__SD3_DATA4 0x17059
-                                                        MX6DL_PAD_SD3_DAT5__SD3_DATA5 0x17059
-                                                        MX6DL_PAD_SD3_DAT6__SD3_DATA6 0x17059
-                                                        MX6DL_PAD_SD3_DAT7__SD3_DATA7 0x17059
-                                                >;
-                                        };
-
-                                        pinctrl_usdhc3_2: usdhc3grp_2 {
-                                                fsl,pins = <
-                                                        MX6DL_PAD_SD3_CMD__SD3_CMD    0x17059
-                                                        MX6DL_PAD_SD3_CLK__SD3_CLK    0x10059
-                                                        MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059
-                                                        MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059
-                                                        MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059
-                                                        MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059
-                                                >;
-                                        };
-                                };
-
-                                weim {
-                                        pinctrl_weim_cs0_1: weim_cs0grp-1 {
-                                                fsl,pins = <
-                                                        MX6DL_PAD_EIM_CS0__EIM_CS0_B   0xb0b1
-                                                >;
-                                        };
-
-                                        pinctrl_weim_nor_1: weim_norgrp-1 {
-                                                fsl,pins = <
-                                                        MX6DL_PAD_EIM_OE__EIM_OE_B     0xb0b1
-                                                        MX6DL_PAD_EIM_RW__EIM_RW       0xb0b1
-                                                        MX6DL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
-                                                        /* data */
-                                                        MX6DL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
-                                                        MX6DL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
-                                                        MX6DL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
-                                                        MX6DL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
-                                                        MX6DL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
-                                                        MX6DL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
-                                                        MX6DL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
-                                                        MX6DL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
-                                                        MX6DL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
-                                                        MX6DL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
-                                                        MX6DL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
-                                                        MX6DL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
-                                                        MX6DL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
-                                                        MX6DL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
-                                                        MX6DL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
-                                                        MX6DL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
-                                                        /* address */
-                                                        MX6DL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
-                                                        MX6DL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
-                                                        MX6DL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
-                                                        MX6DL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
-                                                        MX6DL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
-                                                        MX6DL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
-                                                        MX6DL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
-                                                        MX6DL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
-                                                        MX6DL_PAD_EIM_DA15__EIM_AD15  0xb0b1
-                                                        MX6DL_PAD_EIM_DA14__EIM_AD14  0xb0b1
-                                                        MX6DL_PAD_EIM_DA13__EIM_AD13  0xb0b1
-                                                        MX6DL_PAD_EIM_DA12__EIM_AD12  0xb0b1
-                                                        MX6DL_PAD_EIM_DA11__EIM_AD11  0xb0b1
-                                                        MX6DL_PAD_EIM_DA10__EIM_AD10  0xb0b1
-                                                        MX6DL_PAD_EIM_DA9__EIM_AD09   0xb0b1
-                                                        MX6DL_PAD_EIM_DA8__EIM_AD08   0xb0b1
-                                                        MX6DL_PAD_EIM_DA7__EIM_AD07   0xb0b1
-                                                        MX6DL_PAD_EIM_DA6__EIM_AD06   0xb0b1
-                                                        MX6DL_PAD_EIM_DA5__EIM_AD05   0xb0b1
-                                                        MX6DL_PAD_EIM_DA4__EIM_AD04   0xb0b1
-                                                        MX6DL_PAD_EIM_DA3__EIM_AD03   0xb0b1
-                                                        MX6DL_PAD_EIM_DA2__EIM_AD02   0xb0b1
-                                                        MX6DL_PAD_EIM_DA1__EIM_AD01   0xb0b1
-                                                        MX6DL_PAD_EIM_DA0__EIM_AD00   0xb0b1
-                                                >;
-                                        };
-
-                                };
-
                         };
 
                         pxp: pxp@020f0000 {
@@ -294,3 +71,20 @@
                 };
         };
 };
+
+&ldb {
+        clocks = <&clks 33>, <&clks 34>,
+                 <&clks 39>, <&clks 40>,
+                 <&clks 135>, <&clks 136>;
+        clock-names = "di0_pll", "di1_pll",
+                      "di0_sel", "di1_sel",
+                      "di0", "di1";
+
+        lvds-channel@0 {
+                crtcs = <&ipu1 0>, <&ipu1 1>;
+        };
+
+        lvds-channel@1 {
+                crtcs = <&ipu1 0>, <&ipu1 1>;
+        };
+};
diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts
index 4e54fde591bd..edf1bd967164 100644
--- a/arch/arm/boot/dts/imx6q-arm2.dts
+++ b/arch/arm/boot/dts/imx6q-arm2.dts
@@ -57,7 +57,7 @@
         hog {
                 pinctrl_hog: hoggrp {
                         fsl,pins = <
-                                MX6Q_PAD_EIM_D25__GPIO3_IO25 0x80000000
+                                MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x80000000
                         >;
                 };
         };
@@ -65,8 +65,8 @@
         arm2 {
                 pinctrl_usdhc3_arm2: usdhc3grp-arm2 {
                         fsl,pins = <
-                                MX6Q_PAD_NANDF_CS0__GPIO6_IO11 0x80000000
-                                MX6Q_PAD_NANDF_CS1__GPIO6_IO14 0x80000000
+                                MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000
+                                MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000
                         >;
                 };
         };
@@ -97,6 +97,14 @@
         status = "okay";
 };
 
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart2_2>;
+        fsl,dte-mode;
+        fsl,uart-has-rtscts;
+        status = "okay";
+};
+
 &uart4 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart4_1>;
diff --git a/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi
index f5e1981025ed..1a3b50d4d8fa 100644
--- a/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi
+++ b/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi
@@ -20,6 +20,110 @@
         };
 };
 
+&ecspi3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_ecspi3_1>;
+        status = "okay";
+        fsl,spi-num-chipselects = <1>;
+        cs-gpios = <&gpio4 24 0>;
+
+        flash@0 {
+                compatible = "m25p80";
+                spi-max-frequency = <20000000>;
+                reg = <0>;
+        };
+};
+
+&i2c1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c1_1>;
+        status = "okay";
+
+        eeprom@50 {
+                compatible = "atmel,24c32";
+                reg = <0x50>;
+        };
+
+        pmic@58 {
+                compatible = "dialog,da9063";
+                reg = <0x58>;
+                interrupt-parent = <&gpio4>;
+                interrupts = <17 0x8>; /* active-low GPIO4_17 */
+
+                regulators {
+                        vddcore_reg: bcore1 {
+                                regulator-min-microvolt = <730000>;
+                                regulator-max-microvolt = <1380000>;
+                                regulator-always-on;
+                        };
+
+                        vddsoc_reg: bcore2 {
+                                regulator-min-microvolt = <730000>;
+                                regulator-max-microvolt = <1380000>;
+                                regulator-always-on;
+                        };
+
+                        vdd_ddr3_reg: bpro {
+                                regulator-min-microvolt = <1500000>;
+                                regulator-max-microvolt = <1500000>;
+                                regulator-always-on;
+                        };
+
+                        vdd_3v3_reg: bperi {
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                        };
+
+                        vdd_buckmem_reg: bmem {
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                        };
+
+                        vdd_eth_reg: bio {
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <1200000>;
+                                regulator-always-on;
+                        };
+
+                        vdd_eth_io_reg: ldo4 {
+                                regulator-min-microvolt = <2500000>;
+                                regulator-max-microvolt = <2500000>;
+                                regulator-always-on;
+                        };
+
+                        vdd_mx6_snvs_reg: ldo5 {
+                                regulator-min-microvolt = <3000000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-always-on;
+                        };
+
+                        vdd_3v3_pmic_io_reg: ldo6 {
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                        };
+
+                        vdd_sd0_reg: ldo9 {
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                        };
+
+                        vdd_sd1_reg: ldo10 {
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                        };
+
+                        vdd_mx6_high_reg: ldo11 {
+                                regulator-min-microvolt = <3000000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-always-on;
+                        };
+                };
+        };
+};
+
 &iomuxc {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_hog>;
@@ -27,7 +131,9 @@
         hog {
                 pinctrl_hog: hoggrp {
                         fsl,pins = <
-                                MX6Q_PAD_EIM_D23__GPIO3_IO23    0x80000000
+                                MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
+                                MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */
+                                MX6QDL_PAD_DI0_PIN15__GPIO4_IO17  0x80000000 /* PMIC interrupt */
                         >;
                 };
         };
@@ -35,8 +141,8 @@
         pfla02 {
                 pinctrl_usdhc3_pfla02: usdhc3grp-pfla02 {
                         fsl,pins = <
-                                MX6Q_PAD_ENET_RXD0__GPIO1_IO27  0x80000000
-                                MX6Q_PAD_ENET_TXD1__GPIO1_IO29  0x80000000
+                                MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
+                                MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
                         >;
                 };
         };
diff --git a/arch/arm/boot/dts/imx6q-pinfunc.h b/arch/arm/boot/dts/imx6q-pinfunc.h
index faea6e1ada00..c0e38a45e4bb 100644
--- a/arch/arm/boot/dts/imx6q-pinfunc.h
+++ b/arch/arm/boot/dts/imx6q-pinfunc.h
@@ -14,1028 +14,1032 @@
  * The pin function ID is a tuple of
  * <mux_reg conf_reg input_reg mux_mode input_val>
  */
-#define MX6Q_PAD_SD2_DAT1__SD2_DATA1              0x04c 0x360 0x000 0x0 0x0
-#define MX6Q_PAD_SD2_DAT1__ECSPI5_SS0             0x04c 0x360 0x834 0x1 0x0
-#define MX6Q_PAD_SD2_DAT1__EIM_CS2_B              0x04c 0x360 0x000 0x2 0x0
-#define MX6Q_PAD_SD2_DAT1__AUD4_TXFS              0x04c 0x360 0x7c8 0x3 0x0
-#define MX6Q_PAD_SD2_DAT1__KEY_COL7               0x04c 0x360 0x8f0 0x4 0x0
-#define MX6Q_PAD_SD2_DAT1__GPIO1_IO14             0x04c 0x360 0x000 0x5 0x0
-#define MX6Q_PAD_SD2_DAT2__SD2_DATA2              0x050 0x364 0x000 0x0 0x0
-#define MX6Q_PAD_SD2_DAT2__ECSPI5_SS1             0x050 0x364 0x838 0x1 0x0
-#define MX6Q_PAD_SD2_DAT2__EIM_CS3_B              0x050 0x364 0x000 0x2 0x0
-#define MX6Q_PAD_SD2_DAT2__AUD4_TXD               0x050 0x364 0x7b8 0x3 0x0
-#define MX6Q_PAD_SD2_DAT2__KEY_ROW6               0x050 0x364 0x8f8 0x4 0x0
-#define MX6Q_PAD_SD2_DAT2__GPIO1_IO13             0x050 0x364 0x000 0x5 0x0
-#define MX6Q_PAD_SD2_DAT0__SD2_DATA0              0x054 0x368 0x000 0x0 0x0
-#define MX6Q_PAD_SD2_DAT0__ECSPI5_MISO            0x054 0x368 0x82c 0x1 0x0
-#define MX6Q_PAD_SD2_DAT0__AUD4_RXD               0x054 0x368 0x7b4 0x3 0x0
-#define MX6Q_PAD_SD2_DAT0__KEY_ROW7               0x054 0x368 0x8fc 0x4 0x0
-#define MX6Q_PAD_SD2_DAT0__GPIO1_IO15             0x054 0x368 0x000 0x5 0x0
-#define MX6Q_PAD_SD2_DAT0__DCIC2_OUT              0x054 0x368 0x000 0x6 0x0
-#define MX6Q_PAD_RGMII_TXC__USB_H2_DATA           0x058 0x36c 0x000 0x0 0x0
-#define MX6Q_PAD_RGMII_TXC__RGMII_TXC             0x058 0x36c 0x000 0x1 0x0
-#define MX6Q_PAD_RGMII_TXC__SPDIF_EXT_CLK         0x058 0x36c 0x918 0x2 0x0
-#define MX6Q_PAD_RGMII_TXC__GPIO6_IO19            0x058 0x36c 0x000 0x5 0x0
-#define MX6Q_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M   0x058 0x36c 0x000 0x7 0x0
-#define MX6Q_PAD_RGMII_TD0__HSI_TX_READY          0x05c 0x370 0x000 0x0 0x0
-#define MX6Q_PAD_RGMII_TD0__RGMII_TD0             0x05c 0x370 0x000 0x1 0x0
-#define MX6Q_PAD_RGMII_TD0__GPIO6_IO20            0x05c 0x370 0x000 0x5 0x0
-#define MX6Q_PAD_RGMII_TD1__HSI_RX_FLAG           0x060 0x374 0x000 0x0 0x0
-#define MX6Q_PAD_RGMII_TD1__RGMII_TD1             0x060 0x374 0x000 0x1 0x0
-#define MX6Q_PAD_RGMII_TD1__GPIO6_IO21            0x060 0x374 0x000 0x5 0x0
-#define MX6Q_PAD_RGMII_TD2__HSI_RX_DATA           0x064 0x378 0x000 0x0 0x0
-#define MX6Q_PAD_RGMII_TD2__RGMII_TD2             0x064 0x378 0x000 0x1 0x0
-#define MX6Q_PAD_RGMII_TD2__GPIO6_IO22            0x064 0x378 0x000 0x5 0x0
-#define MX6Q_PAD_RGMII_TD3__HSI_RX_WAKE           0x068 0x37c 0x000 0x0 0x0
-#define MX6Q_PAD_RGMII_TD3__RGMII_TD3             0x068 0x37c 0x000 0x1 0x0
-#define MX6Q_PAD_RGMII_TD3__GPIO6_IO23            0x068 0x37c 0x000 0x5 0x0
-#define MX6Q_PAD_RGMII_RX_CTL__USB_H3_DATA        0x06c 0x380 0x000 0x0 0x0
-#define MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL       0x06c 0x380 0x858 0x1 0x0
-#define MX6Q_PAD_RGMII_RX_CTL__GPIO6_IO24         0x06c 0x380 0x000 0x5 0x0
-#define MX6Q_PAD_RGMII_RD0__HSI_RX_READY          0x070 0x384 0x000 0x0 0x0
-#define MX6Q_PAD_RGMII_RD0__RGMII_RD0             0x070 0x384 0x848 0x1 0x0
-#define MX6Q_PAD_RGMII_RD0__GPIO6_IO25            0x070 0x384 0x000 0x5 0x0
-#define MX6Q_PAD_RGMII_TX_CTL__USB_H2_STROBE      0x074 0x388 0x000 0x0 0x0
-#define MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL       0x074 0x388 0x000 0x1 0x0
-#define MX6Q_PAD_RGMII_TX_CTL__GPIO6_IO26         0x074 0x388 0x000 0x5 0x0
-#define MX6Q_PAD_RGMII_TX_CTL__ENET_REF_CLK       0x074 0x388 0x83c 0x7 0x0
-#define MX6Q_PAD_RGMII_RD1__HSI_TX_FLAG           0x078 0x38c 0x000 0x0 0x0
-#define MX6Q_PAD_RGMII_RD1__RGMII_RD1             0x078 0x38c 0x84c 0x1 0x0
-#define MX6Q_PAD_RGMII_RD1__GPIO6_IO27            0x078 0x38c 0x000 0x5 0x0
-#define MX6Q_PAD_RGMII_RD2__HSI_TX_DATA           0x07c 0x390 0x000 0x0 0x0
-#define MX6Q_PAD_RGMII_RD2__RGMII_RD2             0x07c 0x390 0x850 0x1 0x0
-#define MX6Q_PAD_RGMII_RD2__GPIO6_IO28            0x07c 0x390 0x000 0x5 0x0
-#define MX6Q_PAD_RGMII_RD3__HSI_TX_WAKE           0x080 0x394 0x000 0x0 0x0
-#define MX6Q_PAD_RGMII_RD3__RGMII_RD3             0x080 0x394 0x854 0x1 0x0
-#define MX6Q_PAD_RGMII_RD3__GPIO6_IO29            0x080 0x394 0x000 0x5 0x0
-#define MX6Q_PAD_RGMII_RXC__USB_H3_STROBE         0x084 0x398 0x000 0x0 0x0
-#define MX6Q_PAD_RGMII_RXC__RGMII_RXC             0x084 0x398 0x844 0x1 0x0
-#define MX6Q_PAD_RGMII_RXC__GPIO6_IO30            0x084 0x398 0x000 0x5 0x0
-#define MX6Q_PAD_EIM_A25__EIM_ADDR25              0x088 0x39c 0x000 0x0 0x0
-#define MX6Q_PAD_EIM_A25__ECSPI4_SS1              0x088 0x39c 0x000 0x1 0x0
-#define MX6Q_PAD_EIM_A25__ECSPI2_RDY              0x088 0x39c 0x000 0x2 0x0
-#define MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12          0x088 0x39c 0x000 0x3 0x0
-#define MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS          0x088 0x39c 0x000 0x4 0x0
-#define MX6Q_PAD_EIM_A25__GPIO5_IO02              0x088 0x39c 0x000 0x5 0x0
-#define MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE        0x088 0x39c 0x88c 0x6 0x0
-#define MX6Q_PAD_EIM_EB2__EIM_EB2_B               0x08c 0x3a0 0x000 0x0 0x0
-#define MX6Q_PAD_EIM_EB2__ECSPI1_SS0              0x08c 0x3a0 0x800 0x1 0x0
-#define MX6Q_PAD_EIM_EB2__IPU2_CSI1_DATA19        0x08c 0x3a0 0x8d4 0x3 0x0
-#define MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL         0x08c 0x3a0 0x890 0x4 0x0
-#define MX6Q_PAD_EIM_EB2__GPIO2_IO30              0x08c 0x3a0 0x000 0x5 0x0
-#define MX6Q_PAD_EIM_EB2__I2C2_SCL                0x08c 0x3a0 0x8a0 0x6 0x0
-#define MX6Q_PAD_EIM_EB2__SRC_BOOT_CFG30          0x08c 0x3a0 0x000 0x7 0x0
-#define MX6Q_PAD_EIM_D16__EIM_DATA16              0x090 0x3a4 0x000 0x0 0x0
-#define MX6Q_PAD_EIM_D16__ECSPI1_SCLK             0x090 0x3a4 0x7f4 0x1 0x0
-#define MX6Q_PAD_EIM_D16__IPU1_DI0_PIN05          0x090 0x3a4 0x000 0x2 0x0
-#define MX6Q_PAD_EIM_D16__IPU2_CSI1_DATA18        0x090 0x3a4 0x8d0 0x3 0x0
-#define MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA         0x090 0x3a4 0x894 0x4 0x0
-#define MX6Q_PAD_EIM_D16__GPIO3_IO16              0x090 0x3a4 0x000 0x5 0x0
-#define MX6Q_PAD_EIM_D16__I2C2_SDA                0x090 0x3a4 0x8a4 0x6 0x0
-#define MX6Q_PAD_EIM_D17__EIM_DATA17              0x094 0x3a8 0x000 0x0 0x0
-#define MX6Q_PAD_EIM_D17__ECSPI1_MISO             0x094 0x3a8 0x7f8 0x1 0x0
-#define MX6Q_PAD_EIM_D17__IPU1_DI0_PIN06          0x094 0x3a8 0x000 0x2 0x0
-#define MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK        0x094 0x3a8 0x8e0 0x3 0x0
-#define MX6Q_PAD_EIM_D17__DCIC1_OUT               0x094 0x3a8 0x000 0x4 0x0
-#define MX6Q_PAD_EIM_D17__GPIO3_IO17              0x094 0x3a8 0x000 0x5 0x0
-#define MX6Q_PAD_EIM_D17__I2C3_SCL                0x094 0x3a8 0x8a8 0x6 0x0
-#define MX6Q_PAD_EIM_D18__EIM_DATA18              0x098 0x3ac 0x000 0x0 0x0
-#define MX6Q_PAD_EIM_D18__ECSPI1_MOSI             0x098 0x3ac 0x7fc 0x1 0x0
-#define MX6Q_PAD_EIM_D18__IPU1_DI0_PIN07          0x098 0x3ac 0x000 0x2 0x0
-#define MX6Q_PAD_EIM_D18__IPU2_CSI1_DATA17        0x098 0x3ac 0x8cc 0x3 0x0
-#define MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS          0x098 0x3ac 0x000 0x4 0x0
-#define MX6Q_PAD_EIM_D18__GPIO3_IO18              0x098 0x3ac 0x000 0x5 0x0
-#define MX6Q_PAD_EIM_D18__I2C3_SDA                0x098 0x3ac 0x8ac 0x6 0x0
-#define MX6Q_PAD_EIM_D19__EIM_DATA19              0x09c 0x3b0 0x000 0x0 0x0
-#define MX6Q_PAD_EIM_D19__ECSPI1_SS1              0x09c 0x3b0 0x804 0x1 0x0
-#define MX6Q_PAD_EIM_D19__IPU1_DI0_PIN08          0x09c 0x3b0 0x000 0x2 0x0
-#define MX6Q_PAD_EIM_D19__IPU2_CSI1_DATA16        0x09c 0x3b0 0x8c8 0x3 0x0
-#define MX6Q_PAD_EIM_D19__UART1_CTS_B             0x09c 0x3b0 0x000 0x4 0x0
-#define MX6Q_PAD_EIM_D19__UART1_RTS_B             0x09c 0x3b0 0x91c 0x4 0x0
-#define MX6Q_PAD_EIM_D19__GPIO3_IO19              0x09c 0x3b0 0x000 0x5 0x0
-#define MX6Q_PAD_EIM_D19__EPIT1_OUT               0x09c 0x3b0 0x000 0x6 0x0
-#define MX6Q_PAD_EIM_D20__EIM_DATA20              0x0a0 0x3b4 0x000 0x0 0x0
-#define MX6Q_PAD_EIM_D20__ECSPI4_SS0              0x0a0 0x3b4 0x824 0x1 0x0
-#define MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16          0x0a0 0x3b4 0x000 0x2 0x0
-#define MX6Q_PAD_EIM_D20__IPU2_CSI1_DATA15        0x0a0 0x3b4 0x8c4 0x3 0x0
-#define MX6Q_PAD_EIM_D20__UART1_RTS_B             0x0a0 0x3b4 0x91c 0x4 0x1
-#define MX6Q_PAD_EIM_D20__UART1_CTS_B             0x0a0 0x3b4 0x000 0x4 0x0
-#define MX6Q_PAD_EIM_D20__GPIO3_IO20              0x0a0 0x3b4 0x000 0x5 0x0
-#define MX6Q_PAD_EIM_D20__EPIT2_OUT               0x0a0 0x3b4 0x000 0x6 0x0
-#define MX6Q_PAD_EIM_D21__EIM_DATA21              0x0a4 0x3b8 0x000 0x0 0x0
-#define MX6Q_PAD_EIM_D21__ECSPI4_SCLK             0x0a4 0x3b8 0x000 0x1 0x0
-#define MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17          0x0a4 0x3b8 0x000 0x2 0x0
-#define MX6Q_PAD_EIM_D21__IPU2_CSI1_DATA11        0x0a4 0x3b8 0x8b4 0x3 0x0
-#define MX6Q_PAD_EIM_D21__USB_OTG_OC              0x0a4 0x3b8 0x944 0x4 0x0
-#define MX6Q_PAD_EIM_D21__GPIO3_IO21              0x0a4 0x3b8 0x000 0x5 0x0
-#define MX6Q_PAD_EIM_D21__I2C1_SCL                0x0a4 0x3b8 0x898 0x6 0x0
-#define MX6Q_PAD_EIM_D21__SPDIF_IN                0x0a4 0x3b8 0x914 0x7 0x0
-#define MX6Q_PAD_EIM_D22__EIM_DATA22              0x0a8 0x3bc 0x000 0x0 0x0
-#define MX6Q_PAD_EIM_D22__ECSPI4_MISO             0x0a8 0x3bc 0x000 0x1 0x0
-#define MX6Q_PAD_EIM_D22__IPU1_DI0_PIN01          0x0a8 0x3bc 0x000 0x2 0x0
-#define MX6Q_PAD_EIM_D22__IPU2_CSI1_DATA10        0x0a8 0x3bc 0x8b0 0x3 0x0
-#define MX6Q_PAD_EIM_D22__USB_OTG_PWR             0x0a8 0x3bc 0x000 0x4 0x0
-#define MX6Q_PAD_EIM_D22__GPIO3_IO22              0x0a8 0x3bc 0x000 0x5 0x0
-#define MX6Q_PAD_EIM_D22__SPDIF_OUT               0x0a8 0x3bc 0x000 0x6 0x0
-#define MX6Q_PAD_EIM_D23__EIM_DATA23              0x0ac 0x3c0 0x000 0x0 0x0
-#define MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS          0x0ac 0x3c0 0x000 0x1 0x0
-#define MX6Q_PAD_EIM_D23__UART3_CTS_B             0x0ac 0x3c0 0x000 0x2 0x0
-#define MX6Q_PAD_EIM_D23__UART3_RTS_B             0x0ac 0x3c0 0x92c 0x2 0x0
-#define MX6Q_PAD_EIM_D23__UART1_DCD_B             0x0ac 0x3c0 0x000 0x3 0x0
-#define MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN       0x0ac 0x3c0 0x8d8 0x4 0x0
-#define MX6Q_PAD_EIM_D23__GPIO3_IO23              0x0ac 0x3c0 0x000 0x5 0x0
-#define MX6Q_PAD_EIM_D23__IPU1_DI1_PIN02          0x0ac 0x3c0 0x000 0x6 0x0
-#define MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14          0x0ac 0x3c0 0x000 0x7 0x0
-#define MX6Q_PAD_EIM_EB3__EIM_EB3_B               0x0b0 0x3c4 0x000 0x0 0x0
-#define MX6Q_PAD_EIM_EB3__ECSPI4_RDY              0x0b0 0x3c4 0x000 0x1 0x0
-#define MX6Q_PAD_EIM_EB3__UART3_RTS_B             0x0b0 0x3c4 0x92c 0x2 0x1
-#define MX6Q_PAD_EIM_EB3__UART3_CTS_B             0x0b0 0x3c4 0x000 0x2 0x0
-#define MX6Q_PAD_EIM_EB3__UART1_RI_B              0x0b0 0x3c4 0x000 0x3 0x0
-#define MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC         0x0b0 0x3c4 0x8dc 0x4 0x0
-#define MX6Q_PAD_EIM_EB3__GPIO2_IO31              0x0b0 0x3c4 0x000 0x5 0x0
-#define MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN03          0x0b0 0x3c4 0x000 0x6 0x0
-#define MX6Q_PAD_EIM_EB3__SRC_BOOT_CFG31          0x0b0 0x3c4 0x000 0x7 0x0
-#define MX6Q_PAD_EIM_D24__EIM_DATA24              0x0b4 0x3c8 0x000 0x0 0x0
-#define MX6Q_PAD_EIM_D24__ECSPI4_SS2              0x0b4 0x3c8 0x000 0x1 0x0
-#define MX6Q_PAD_EIM_D24__UART3_TX_DATA           0x0b4 0x3c8 0x000 0x2 0x0
-#define MX6Q_PAD_EIM_D24__UART3_RX_DATA           0x0b4 0x3c8 0x930 0x2 0x0
-#define MX6Q_PAD_EIM_D24__ECSPI1_SS2              0x0b4 0x3c8 0x808 0x3 0x0
-#define MX6Q_PAD_EIM_D24__ECSPI2_SS2              0x0b4 0x3c8 0x000 0x4 0x0
-#define MX6Q_PAD_EIM_D24__GPIO3_IO24              0x0b4 0x3c8 0x000 0x5 0x0
-#define MX6Q_PAD_EIM_D24__AUD5_RXFS               0x0b4 0x3c8 0x7d8 0x6 0x0
-#define MX6Q_PAD_EIM_D24__UART1_DTR_B             0x0b4 0x3c8 0x000 0x7 0x0
-#define MX6Q_PAD_EIM_D25__EIM_DATA25              0x0b8 0x3cc 0x000 0x0 0x0
-#define MX6Q_PAD_EIM_D25__ECSPI4_SS3              0x0b8 0x3cc 0x000 0x1 0x0
-#define MX6Q_PAD_EIM_D25__UART3_RX_DATA           0x0b8 0x3cc 0x930 0x2 0x1
-#define MX6Q_PAD_EIM_D25__UART3_TX_DATA           0x0b8 0x3cc 0x000 0x2 0x0
-#define MX6Q_PAD_EIM_D25__ECSPI1_SS3              0x0b8 0x3cc 0x80c 0x3 0x0
-#define MX6Q_PAD_EIM_D25__ECSPI2_SS3              0x0b8 0x3cc 0x000 0x4 0x0
-#define MX6Q_PAD_EIM_D25__GPIO3_IO25              0x0b8 0x3cc 0x000 0x5 0x0
-#define MX6Q_PAD_EIM_D25__AUD5_RXC                0x0b8 0x3cc 0x7d4 0x6 0x0
-#define MX6Q_PAD_EIM_D25__UART1_DSR_B             0x0b8 0x3cc 0x000 0x7 0x0
-#define MX6Q_PAD_EIM_D26__EIM_DATA26              0x0bc 0x3d0 0x000 0x0 0x0
-#define MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11          0x0bc 0x3d0 0x000 0x1 0x0
-#define MX6Q_PAD_EIM_D26__IPU1_CSI0_DATA01        0x0bc 0x3d0 0x000 0x2 0x0
-#define MX6Q_PAD_EIM_D26__IPU2_CSI1_DATA14        0x0bc 0x3d0 0x8c0 0x3 0x0
-#define MX6Q_PAD_EIM_D26__UART2_TX_DATA           0x0bc 0x3d0 0x000 0x4 0x0
-#define MX6Q_PAD_EIM_D26__UART2_RX_DATA           0x0bc 0x3d0 0x928 0x4 0x0
-#define MX6Q_PAD_EIM_D26__GPIO3_IO26              0x0bc 0x3d0 0x000 0x5 0x0
-#define MX6Q_PAD_EIM_D26__IPU1_SISG2              0x0bc 0x3d0 0x000 0x6 0x0
-#define MX6Q_PAD_EIM_D26__IPU1_DISP1_DATA22       0x0bc 0x3d0 0x000 0x7 0x0
-#define MX6Q_PAD_EIM_D27__EIM_DATA27              0x0c0 0x3d4 0x000 0x0 0x0
-#define MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13          0x0c0 0x3d4 0x000 0x1 0x0
-#define MX6Q_PAD_EIM_D27__IPU1_CSI0_DATA00        0x0c0 0x3d4 0x000 0x2 0x0
-#define MX6Q_PAD_EIM_D27__IPU2_CSI1_DATA13        0x0c0 0x3d4 0x8bc 0x3 0x0
-#define MX6Q_PAD_EIM_D27__UART2_RX_DATA           0x0c0 0x3d4 0x928 0x4 0x1
-#define MX6Q_PAD_EIM_D27__UART2_TX_DATA           0x0c0 0x3d4 0x000 0x4 0x0
-#define MX6Q_PAD_EIM_D27__GPIO3_IO27              0x0c0 0x3d4 0x000 0x5 0x0
-#define MX6Q_PAD_EIM_D27__IPU1_SISG3              0x0c0 0x3d4 0x000 0x6 0x0
-#define MX6Q_PAD_EIM_D27__IPU1_DISP1_DATA23       0x0c0 0x3d4 0x000 0x7 0x0
-#define MX6Q_PAD_EIM_D28__EIM_DATA28              0x0c4 0x3d8 0x000 0x0 0x0
-#define MX6Q_PAD_EIM_D28__I2C1_SDA                0x0c4 0x3d8 0x89c 0x1 0x0
-#define MX6Q_PAD_EIM_D28__ECSPI4_MOSI             0x0c4 0x3d8 0x000 0x2 0x0
-#define MX6Q_PAD_EIM_D28__IPU2_CSI1_DATA12        0x0c4 0x3d8 0x8b8 0x3 0x0
-#define MX6Q_PAD_EIM_D28__UART2_CTS_B             0x0c4 0x3d8 0x000 0x4 0x0
-#define MX6Q_PAD_EIM_D28__UART2_RTS_B             0x0c4 0x3d8 0x924 0x4 0x0
-#define MX6Q_PAD_EIM_D28__GPIO3_IO28              0x0c4 0x3d8 0x000 0x5 0x0
-#define MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG           0x0c4 0x3d8 0x000 0x6 0x0
-#define MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13          0x0c4 0x3d8 0x000 0x7 0x0
-#define MX6Q_PAD_EIM_D29__EIM_DATA29              0x0c8 0x3dc 0x000 0x0 0x0
-#define MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15          0x0c8 0x3dc 0x000 0x1 0x0
-#define MX6Q_PAD_EIM_D29__ECSPI4_SS0              0x0c8 0x3dc 0x824 0x2 0x1
-#define MX6Q_PAD_EIM_D29__UART2_RTS_B             0x0c8 0x3dc 0x924 0x4 0x1
-#define MX6Q_PAD_EIM_D29__UART2_CTS_B             0x0c8 0x3dc 0x000 0x4 0x0
-#define MX6Q_PAD_EIM_D29__GPIO3_IO29              0x0c8 0x3dc 0x000 0x5 0x0
-#define MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC         0x0c8 0x3dc 0x8e4 0x6 0x0
-#define MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14          0x0c8 0x3dc 0x000 0x7 0x0
-#define MX6Q_PAD_EIM_D30__EIM_DATA30              0x0cc 0x3e0 0x000 0x0 0x0
-#define MX6Q_PAD_EIM_D30__IPU1_DISP1_DATA21       0x0cc 0x3e0 0x000 0x1 0x0
-#define MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11          0x0cc 0x3e0 0x000 0x2 0x0
-#define MX6Q_PAD_EIM_D30__IPU1_CSI0_DATA03        0x0cc 0x3e0 0x000 0x3 0x0
-#define MX6Q_PAD_EIM_D30__UART3_CTS_B             0x0cc 0x3e0 0x000 0x4 0x0
-#define MX6Q_PAD_EIM_D30__UART3_RTS_B             0x0cc 0x3e0 0x92c 0x4 0x2
-#define MX6Q_PAD_EIM_D30__GPIO3_IO30              0x0cc 0x3e0 0x000 0x5 0x0
-#define MX6Q_PAD_EIM_D30__USB_H1_OC               0x0cc 0x3e0 0x948 0x6 0x0
-#define MX6Q_PAD_EIM_D31__EIM_DATA31              0x0d0 0x3e4 0x000 0x0 0x0
-#define MX6Q_PAD_EIM_D31__IPU1_DISP1_DATA20       0x0d0 0x3e4 0x000 0x1 0x0
-#define MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12          0x0d0 0x3e4 0x000 0x2 0x0
-#define MX6Q_PAD_EIM_D31__IPU1_CSI0_DATA02        0x0d0 0x3e4 0x000 0x3 0x0
-#define MX6Q_PAD_EIM_D31__UART3_RTS_B             0x0d0 0x3e4 0x92c 0x4 0x3
-#define MX6Q_PAD_EIM_D31__UART3_CTS_B             0x0d0 0x3e4 0x000 0x4 0x0
-#define MX6Q_PAD_EIM_D31__GPIO3_IO31              0x0d0 0x3e4 0x000 0x5 0x0
-#define MX6Q_PAD_EIM_D31__USB_H1_PWR              0x0d0 0x3e4 0x000 0x6 0x0
-#define MX6Q_PAD_EIM_A24__EIM_ADDR24              0x0d4 0x3e8 0x000 0x0 0x0
-#define MX6Q_PAD_EIM_A24__IPU1_DISP1_DATA19       0x0d4 0x3e8 0x000 0x1 0x0
-#define MX6Q_PAD_EIM_A24__IPU2_CSI1_DATA19        0x0d4 0x3e8 0x8d4 0x2 0x1
-#define MX6Q_PAD_EIM_A24__IPU2_SISG2              0x0d4 0x3e8 0x000 0x3 0x0
-#define MX6Q_PAD_EIM_A24__IPU1_SISG2              0x0d4 0x3e8 0x000 0x4 0x0
-#define MX6Q_PAD_EIM_A24__GPIO5_IO04              0x0d4 0x3e8 0x000 0x5 0x0
-#define MX6Q_PAD_EIM_A24__SRC_BOOT_CFG24          0x0d4 0x3e8 0x000 0x7 0x0
-#define MX6Q_PAD_EIM_A23__EIM_ADDR23              0x0d8 0x3ec 0x000 0x0 0x0
-#define MX6Q_PAD_EIM_A23__IPU1_DISP1_DATA18       0x0d8 0x3ec 0x000 0x1 0x0
-#define MX6Q_PAD_EIM_A23__IPU2_CSI1_DATA18        0x0d8 0x3ec 0x8d0 0x2 0x1
-#define MX6Q_PAD_EIM_A23__IPU2_SISG3              0x0d8 0x3ec 0x000 0x3 0x0
-#define MX6Q_PAD_EIM_A23__IPU1_SISG3              0x0d8 0x3ec 0x000 0x4 0x0
-#define MX6Q_PAD_EIM_A23__GPIO6_IO06              0x0d8 0x3ec 0x000 0x5 0x0
-#define MX6Q_PAD_EIM_A23__SRC_BOOT_CFG23          0x0d8 0x3ec 0x000 0x7 0x0
-#define MX6Q_PAD_EIM_A22__EIM_ADDR22              0x0dc 0x3f0 0x000 0x0 0x0
-#define MX6Q_PAD_EIM_A22__IPU1_DISP1_DATA17       0x0dc 0x3f0 0x000 0x1 0x0
-#define MX6Q_PAD_EIM_A22__IPU2_CSI1_DATA17        0x0dc 0x3f0 0x8cc 0x2 0x1
-#define MX6Q_PAD_EIM_A22__GPIO2_IO16              0x0dc 0x3f0 0x000 0x5 0x0
-#define MX6Q_PAD_EIM_A22__SRC_BOOT_CFG22          0x0dc 0x3f0 0x000 0x7 0x0
-#define MX6Q_PAD_EIM_A21__EIM_ADDR21              0x0e0 0x3f4 0x000 0x0 0x0
-#define MX6Q_PAD_EIM_A21__IPU1_DISP1_DATA16       0x0e0 0x3f4 0x000 0x1 0x0
-#define MX6Q_PAD_EIM_A21__IPU2_CSI1_DATA16        0x0e0 0x3f4 0x8c8 0x2 0x1
-#define MX6Q_PAD_EIM_A21__GPIO2_IO17              0x0e0 0x3f4 0x000 0x5 0x0
-#define MX6Q_PAD_EIM_A21__SRC_BOOT_CFG21          0x0e0 0x3f4 0x000 0x7 0x0
-#define MX6Q_PAD_EIM_A20__EIM_ADDR20              0x0e4 0x3f8 0x000 0x0 0x0
-#define MX6Q_PAD_EIM_A20__IPU1_DISP1_DATA15       0x0e4 0x3f8 0x000 0x1 0x0
-#define MX6Q_PAD_EIM_A20__IPU2_CSI1_DATA15        0x0e4 0x3f8 0x8c4 0x2 0x1
-#define MX6Q_PAD_EIM_A20__GPIO2_IO18              0x0e4 0x3f8 0x000 0x5 0x0
-#define MX6Q_PAD_EIM_A20__SRC_BOOT_CFG20          0x0e4 0x3f8 0x000 0x7 0x0
-#define MX6Q_PAD_EIM_A19__EIM_ADDR19              0x0e8 0x3fc 0x000 0x0 0x0
-#define MX6Q_PAD_EIM_A19__IPU1_DISP1_DATA14       0x0e8 0x3fc 0x000 0x1 0x0
-#define MX6Q_PAD_EIM_A19__IPU2_CSI1_DATA14        0x0e8 0x3fc 0x8c0 0x2 0x1
-#define MX6Q_PAD_EIM_A19__GPIO2_IO19              0x0e8 0x3fc 0x000 0x5 0x0
-#define MX6Q_PAD_EIM_A19__SRC_BOOT_CFG19          0x0e8 0x3fc 0x000 0x7 0x0
-#define MX6Q_PAD_EIM_A18__EIM_ADDR18              0x0ec 0x400 0x000 0x0 0x0
-#define MX6Q_PAD_EIM_A18__IPU1_DISP1_DATA13       0x0ec 0x400 0x000 0x1 0x0
-#define MX6Q_PAD_EIM_A18__IPU2_CSI1_DATA13        0x0ec 0x400 0x8bc 0x2 0x1
-#define MX6Q_PAD_EIM_A18__GPIO2_IO20              0x0ec 0x400 0x000 0x5 0x0
-#define MX6Q_PAD_EIM_A18__SRC_BOOT_CFG18          0x0ec 0x400 0x000 0x7 0x0
-#define MX6Q_PAD_EIM_A17__EIM_ADDR17              0x0f0 0x404 0x000 0x0 0x0
-#define MX6Q_PAD_EIM_A17__IPU1_DISP1_DATA12       0x0f0 0x404 0x000 0x1 0x0
-#define MX6Q_PAD_EIM_A17__IPU2_CSI1_DATA12        0x0f0 0x404 0x8b8 0x2 0x1
-#define MX6Q_PAD_EIM_A17__GPIO2_IO21              0x0f0 0x404 0x000 0x5 0x0
-#define MX6Q_PAD_EIM_A17__SRC_BOOT_CFG17          0x0f0 0x404 0x000 0x7 0x0
-#define MX6Q_PAD_EIM_A16__EIM_ADDR16              0x0f4 0x408 0x000 0x0 0x0
-#define MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK       0x0f4 0x408 0x000 0x1 0x0
-#define MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK        0x0f4 0x408 0x8e0 0x2 0x1
-#define MX6Q_PAD_EIM_A16__GPIO2_IO22              0x0f4 0x408 0x000 0x5 0x0
-#define MX6Q_PAD_EIM_A16__SRC_BOOT_CFG16          0x0f4 0x408 0x000 0x7 0x0
-#define MX6Q_PAD_EIM_CS0__EIM_CS0_B               0x0f8 0x40c 0x000 0x0 0x0
-#define MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN05          0x0f8 0x40c 0x000 0x1 0x0
-#define MX6Q_PAD_EIM_CS0__ECSPI2_SCLK             0x0f8 0x40c 0x810 0x2 0x0
-#define MX6Q_PAD_EIM_CS0__GPIO2_IO23              0x0f8 0x40c 0x000 0x5 0x0
-#define MX6Q_PAD_EIM_CS1__EIM_CS1_B               0x0fc 0x410 0x000 0x0 0x0
-#define MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN06          0x0fc 0x410 0x000 0x1 0x0
-#define MX6Q_PAD_EIM_CS1__ECSPI2_MOSI             0x0fc 0x410 0x818 0x2 0x0
-#define MX6Q_PAD_EIM_CS1__GPIO2_IO24              0x0fc 0x410 0x000 0x5 0x0
-#define MX6Q_PAD_EIM_OE__EIM_OE_B                 0x100 0x414 0x000 0x0 0x0
-#define MX6Q_PAD_EIM_OE__IPU1_DI1_PIN07           0x100 0x414 0x000 0x1 0x0
-#define MX6Q_PAD_EIM_OE__ECSPI2_MISO              0x100 0x414 0x814 0x2 0x0
-#define MX6Q_PAD_EIM_OE__GPIO2_IO25               0x100 0x414 0x000 0x5 0x0
-#define MX6Q_PAD_EIM_RW__EIM_RW                   0x104 0x418 0x000 0x0 0x0
-#define MX6Q_PAD_EIM_RW__IPU1_DI1_PIN08           0x104 0x418 0x000 0x1 0x0
-#define MX6Q_PAD_EIM_RW__ECSPI2_SS0               0x104 0x418 0x81c 0x2 0x0
-#define MX6Q_PAD_EIM_RW__GPIO2_IO26               0x104 0x418 0x000 0x5 0x0
-#define MX6Q_PAD_EIM_RW__SRC_BOOT_CFG29           0x104 0x418 0x000 0x7 0x0
-#define MX6Q_PAD_EIM_LBA__EIM_LBA_B               0x108 0x41c 0x000 0x0 0x0
-#define MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17          0x108 0x41c 0x000 0x1 0x0
-#define MX6Q_PAD_EIM_LBA__ECSPI2_SS1              0x108 0x41c 0x820 0x2 0x0
-#define MX6Q_PAD_EIM_LBA__GPIO2_IO27              0x108 0x41c 0x000 0x5 0x0
-#define MX6Q_PAD_EIM_LBA__SRC_BOOT_CFG26          0x108 0x41c 0x000 0x7 0x0
-#define MX6Q_PAD_EIM_EB0__EIM_EB0_B               0x10c 0x420 0x000 0x0 0x0
-#define MX6Q_PAD_EIM_EB0__IPU1_DISP1_DATA11       0x10c 0x420 0x000 0x1 0x0
-#define MX6Q_PAD_EIM_EB0__IPU2_CSI1_DATA11        0x10c 0x420 0x8b4 0x2 0x1
-#define MX6Q_PAD_EIM_EB0__CCM_PMIC_READY          0x10c 0x420 0x7f0 0x4 0x0
-#define MX6Q_PAD_EIM_EB0__GPIO2_IO28              0x10c 0x420 0x000 0x5 0x0
-#define MX6Q_PAD_EIM_EB0__SRC_BOOT_CFG27          0x10c 0x420 0x000 0x7 0x0
-#define MX6Q_PAD_EIM_EB1__EIM_EB1_B               0x110 0x424 0x000 0x0 0x0
-#define MX6Q_PAD_EIM_EB1__IPU1_DISP1_DATA10       0x110 0x424 0x000 0x1 0x0
-#define MX6Q_PAD_EIM_EB1__IPU2_CSI1_DATA10        0x110 0x424 0x8b0 0x2 0x1
-#define MX6Q_PAD_EIM_EB1__GPIO2_IO29              0x110 0x424 0x000 0x5 0x0
-#define MX6Q_PAD_EIM_EB1__SRC_BOOT_CFG28          0x110 0x424 0x000 0x7 0x0
-#define MX6Q_PAD_EIM_DA0__EIM_AD00                0x114 0x428 0x000 0x0 0x0
-#define MX6Q_PAD_EIM_DA0__IPU1_DISP1_DATA09       0x114 0x428 0x000 0x1 0x0
-#define MX6Q_PAD_EIM_DA0__IPU2_CSI1_DATA09        0x114 0x428 0x000 0x2 0x0
-#define MX6Q_PAD_EIM_DA0__GPIO3_IO00              0x114 0x428 0x000 0x5 0x0
-#define MX6Q_PAD_EIM_DA0__SRC_BOOT_CFG00          0x114 0x428 0x000 0x7 0x0
-#define MX6Q_PAD_EIM_DA1__EIM_AD01                0x118 0x42c 0x000 0x0 0x0
-#define MX6Q_PAD_EIM_DA1__IPU1_DISP1_DATA08       0x118 0x42c 0x000 0x1 0x0
-#define MX6Q_PAD_EIM_DA1__IPU2_CSI1_DATA08        0x118 0x42c 0x000 0x2 0x0
-#define MX6Q_PAD_EIM_DA1__GPIO3_IO01              0x118 0x42c 0x000 0x5 0x0
-#define MX6Q_PAD_EIM_DA1__SRC_BOOT_CFG01          0x118 0x42c 0x000 0x7 0x0
-#define MX6Q_PAD_EIM_DA2__EIM_AD02                0x11c 0x430 0x000 0x0 0x0
-#define MX6Q_PAD_EIM_DA2__IPU1_DISP1_DATA07       0x11c 0x430 0x000 0x1 0x0
-#define MX6Q_PAD_EIM_DA2__IPU2_CSI1_DATA07        0x11c 0x430 0x000 0x2 0x0
-#define MX6Q_PAD_EIM_DA2__GPIO3_IO02              0x11c 0x430 0x000 0x5 0x0
-#define MX6Q_PAD_EIM_DA2__SRC_BOOT_CFG02          0x11c 0x430 0x000 0x7 0x0
-#define MX6Q_PAD_EIM_DA3__EIM_AD03                0x120 0x434 0x000 0x0 0x0
-#define MX6Q_PAD_EIM_DA3__IPU1_DISP1_DATA06       0x120 0x434 0x000 0x1 0x0
-#define MX6Q_PAD_EIM_DA3__IPU2_CSI1_DATA06        0x120 0x434 0x000 0x2 0x0
-#define MX6Q_PAD_EIM_DA3__GPIO3_IO03              0x120 0x434 0x000 0x5 0x0
-#define MX6Q_PAD_EIM_DA3__SRC_BOOT_CFG03          0x120 0x434 0x000 0x7 0x0
-#define MX6Q_PAD_EIM_DA4__EIM_AD04                0x124 0x438 0x000 0x0 0x0
-#define MX6Q_PAD_EIM_DA4__IPU1_DISP1_DATA05       0x124 0x438 0x000 0x1 0x0
-#define MX6Q_PAD_EIM_DA4__IPU2_CSI1_DATA05        0x124 0x438 0x000 0x2 0x0
-#define MX6Q_PAD_EIM_DA4__GPIO3_IO04              0x124 0x438 0x000 0x5 0x0
-#define MX6Q_PAD_EIM_DA4__SRC_BOOT_CFG04          0x124 0x438 0x000 0x7 0x0
-#define MX6Q_PAD_EIM_DA5__EIM_AD05                0x128 0x43c 0x000 0x0 0x0
-#define MX6Q_PAD_EIM_DA5__IPU1_DISP1_DATA04       0x128 0x43c 0x000 0x1 0x0
-#define MX6Q_PAD_EIM_DA5__IPU2_CSI1_DATA04        0x128 0x43c 0x000 0x2 0x0
-#define MX6Q_PAD_EIM_DA5__GPIO3_IO05              0x128 0x43c 0x000 0x5 0x0
-#define MX6Q_PAD_EIM_DA5__SRC_BOOT_CFG05          0x128 0x43c 0x000 0x7 0x0
-#define MX6Q_PAD_EIM_DA6__EIM_AD06                0x12c 0x440 0x000 0x0 0x0
-#define MX6Q_PAD_EIM_DA6__IPU1_DISP1_DATA03       0x12c 0x440 0x000 0x1 0x0
-#define MX6Q_PAD_EIM_DA6__IPU2_CSI1_DATA03        0x12c 0x440 0x000 0x2 0x0
-#define MX6Q_PAD_EIM_DA6__GPIO3_IO06              0x12c 0x440 0x000 0x5 0x0
-#define MX6Q_PAD_EIM_DA6__SRC_BOOT_CFG06          0x12c 0x440 0x000 0x7 0x0
-#define MX6Q_PAD_EIM_DA7__EIM_AD07                0x130 0x444 0x000 0x0 0x0
-#define MX6Q_PAD_EIM_DA7__IPU1_DISP1_DATA02       0x130 0x444 0x000 0x1 0x0
-#define MX6Q_PAD_EIM_DA7__IPU2_CSI1_DATA02        0x130 0x444 0x000 0x2 0x0
-#define MX6Q_PAD_EIM_DA7__GPIO3_IO07              0x130 0x444 0x000 0x5 0x0
-#define MX6Q_PAD_EIM_DA7__SRC_BOOT_CFG07          0x130 0x444 0x000 0x7 0x0
-#define MX6Q_PAD_EIM_DA8__EIM_AD08                0x134 0x448 0x000 0x0 0x0
-#define MX6Q_PAD_EIM_DA8__IPU1_DISP1_DATA01       0x134 0x448 0x000 0x1 0x0
-#define MX6Q_PAD_EIM_DA8__IPU2_CSI1_DATA01        0x134 0x448 0x000 0x2 0x0
-#define MX6Q_PAD_EIM_DA8__GPIO3_IO08              0x134 0x448 0x000 0x5 0x0
-#define MX6Q_PAD_EIM_DA8__SRC_BOOT_CFG08          0x134 0x448 0x000 0x7 0x0
-#define MX6Q_PAD_EIM_DA9__EIM_AD09                0x138 0x44c 0x000 0x0 0x0
-#define MX6Q_PAD_EIM_DA9__IPU1_DISP1_DATA00       0x138 0x44c 0x000 0x1 0x0
-#define MX6Q_PAD_EIM_DA9__IPU2_CSI1_DATA00        0x138 0x44c 0x000 0x2 0x0
-#define MX6Q_PAD_EIM_DA9__GPIO3_IO09              0x138 0x44c 0x000 0x5 0x0
-#define MX6Q_PAD_EIM_DA9__SRC_BOOT_CFG09          0x138 0x44c 0x000 0x7 0x0
-#define MX6Q_PAD_EIM_DA10__EIM_AD10               0x13c 0x450 0x000 0x0 0x0
-#define MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15         0x13c 0x450 0x000 0x1 0x0
-#define MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN      0x13c 0x450 0x8d8 0x2 0x1
-#define MX6Q_PAD_EIM_DA10__GPIO3_IO10             0x13c 0x450 0x000 0x5 0x0
-#define MX6Q_PAD_EIM_DA10__SRC_BOOT_CFG10         0x13c 0x450 0x000 0x7 0x0
-#define MX6Q_PAD_EIM_DA11__EIM_AD11               0x140 0x454 0x000 0x0 0x0
-#define MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN02         0x140 0x454 0x000 0x1 0x0
-#define MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC        0x140 0x454 0x8dc 0x2 0x1
-#define MX6Q_PAD_EIM_DA11__GPIO3_IO11             0x140 0x454 0x000 0x5 0x0
-#define MX6Q_PAD_EIM_DA11__SRC_BOOT_CFG11         0x140 0x454 0x000 0x7 0x0
-#define MX6Q_PAD_EIM_DA12__EIM_AD12               0x144 0x458 0x000 0x0 0x0
-#define MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN03         0x144 0x458 0x000 0x1 0x0
-#define MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC        0x144 0x458 0x8e4 0x2 0x1
-#define MX6Q_PAD_EIM_DA12__GPIO3_IO12             0x144 0x458 0x000 0x5 0x0
-#define MX6Q_PAD_EIM_DA12__SRC_BOOT_CFG12         0x144 0x458 0x000 0x7 0x0
-#define MX6Q_PAD_EIM_DA13__EIM_AD13               0x148 0x45c 0x000 0x0 0x0
-#define MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS         0x148 0x45c 0x000 0x1 0x0
-#define MX6Q_PAD_EIM_DA13__GPIO3_IO13             0x148 0x45c 0x000 0x5 0x0
-#define MX6Q_PAD_EIM_DA13__SRC_BOOT_CFG13         0x148 0x45c 0x000 0x7 0x0
-#define MX6Q_PAD_EIM_DA14__EIM_AD14               0x14c 0x460 0x000 0x0 0x0
-#define MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS         0x14c 0x460 0x000 0x1 0x0
-#define MX6Q_PAD_EIM_DA14__GPIO3_IO14             0x14c 0x460 0x000 0x5 0x0
-#define MX6Q_PAD_EIM_DA14__SRC_BOOT_CFG14         0x14c 0x460 0x000 0x7 0x0
-#define MX6Q_PAD_EIM_DA15__EIM_AD15               0x150 0x464 0x000 0x0 0x0
-#define MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN01         0x150 0x464 0x000 0x1 0x0
-#define MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN04         0x150 0x464 0x000 0x2 0x0
-#define MX6Q_PAD_EIM_DA15__GPIO3_IO15             0x150 0x464 0x000 0x5 0x0
-#define MX6Q_PAD_EIM_DA15__SRC_BOOT_CFG15         0x150 0x464 0x000 0x7 0x0
-#define MX6Q_PAD_EIM_WAIT__EIM_WAIT_B             0x154 0x468 0x000 0x0 0x0
-#define MX6Q_PAD_EIM_WAIT__EIM_DTACK_B            0x154 0x468 0x000 0x1 0x0
-#define MX6Q_PAD_EIM_WAIT__GPIO5_IO00             0x154 0x468 0x000 0x5 0x0
-#define MX6Q_PAD_EIM_WAIT__SRC_BOOT_CFG25         0x154 0x468 0x000 0x7 0x0
-#define MX6Q_PAD_EIM_BCLK__EIM_BCLK               0x158 0x46c 0x000 0x0 0x0
-#define MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16         0x158 0x46c 0x000 0x1 0x0
-#define MX6Q_PAD_EIM_BCLK__GPIO6_IO31             0x158 0x46c 0x000 0x5 0x0
-#define MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK  0x15c 0x470 0x000 0x0 0x0
-#define MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK  0x15c 0x470 0x000 0x1 0x0
-#define MX6Q_PAD_DI0_DISP_CLK__GPIO4_IO16         0x15c 0x470 0x000 0x5 0x0
-#define MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15        0x160 0x474 0x000 0x0 0x0
-#define MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15        0x160 0x474 0x000 0x1 0x0
-#define MX6Q_PAD_DI0_PIN15__AUD6_TXC              0x160 0x474 0x000 0x2 0x0
-#define MX6Q_PAD_DI0_PIN15__GPIO4_IO17            0x160 0x474 0x000 0x5 0x0
-#define MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN02         0x164 0x478 0x000 0x0 0x0
-#define MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN02         0x164 0x478 0x000 0x1 0x0
-#define MX6Q_PAD_DI0_PIN2__AUD6_TXD               0x164 0x478 0x000 0x2 0x0
-#define MX6Q_PAD_DI0_PIN2__GPIO4_IO18             0x164 0x478 0x000 0x5 0x0
-#define MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN03         0x168 0x47c 0x000 0x0 0x0
-#define MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN03         0x168 0x47c 0x000 0x1 0x0
-#define MX6Q_PAD_DI0_PIN3__AUD6_TXFS              0x168 0x47c 0x000 0x2 0x0
-#define MX6Q_PAD_DI0_PIN3__GPIO4_IO19             0x168 0x47c 0x000 0x5 0x0
-#define MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN04         0x16c 0x480 0x000 0x0 0x0
-#define MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN04         0x16c 0x480 0x000 0x1 0x0
-#define MX6Q_PAD_DI0_PIN4__AUD6_RXD               0x16c 0x480 0x000 0x2 0x0
-#define MX6Q_PAD_DI0_PIN4__SD1_WP                 0x16c 0x480 0x94c 0x3 0x0
-#define MX6Q_PAD_DI0_PIN4__GPIO4_IO20             0x16c 0x480 0x000 0x5 0x0
-#define MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DATA00    0x170 0x484 0x000 0x0 0x0
-#define MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DATA00    0x170 0x484 0x000 0x1 0x0
-#define MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK          0x170 0x484 0x000 0x2 0x0
-#define MX6Q_PAD_DISP0_DAT0__GPIO4_IO21           0x170 0x484 0x000 0x5 0x0
-#define MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DATA01    0x174 0x488 0x000 0x0 0x0
-#define MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DATA01    0x174 0x488 0x000 0x1 0x0
-#define MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI          0x174 0x488 0x000 0x2 0x0
-#define MX6Q_PAD_DISP0_DAT1__GPIO4_IO22           0x174 0x488 0x000 0x5 0x0
-#define MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DATA02    0x178 0x48c 0x000 0x0 0x0
-#define MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DATA02    0x178 0x48c 0x000 0x1 0x0
-#define MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO          0x178 0x48c 0x000 0x2 0x0
-#define MX6Q_PAD_DISP0_DAT2__GPIO4_IO23           0x178 0x48c 0x000 0x5 0x0
-#define MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DATA03    0x17c 0x490 0x000 0x0 0x0
-#define MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DATA03    0x17c 0x490 0x000 0x1 0x0
-#define MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0           0x17c 0x490 0x000 0x2 0x0
-#define MX6Q_PAD_DISP0_DAT3__GPIO4_IO24           0x17c 0x490 0x000 0x5 0x0
-#define MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DATA04    0x180 0x494 0x000 0x0 0x0
-#define MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DATA04    0x180 0x494 0x000 0x1 0x0
-#define MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1           0x180 0x494 0x000 0x2 0x0
-#define MX6Q_PAD_DISP0_DAT4__GPIO4_IO25           0x180 0x494 0x000 0x5 0x0
-#define MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DATA05    0x184 0x498 0x000 0x0 0x0
-#define MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DATA05    0x184 0x498 0x000 0x1 0x0
-#define MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2           0x184 0x498 0x000 0x2 0x0
-#define MX6Q_PAD_DISP0_DAT5__AUD6_RXFS            0x184 0x498 0x000 0x3 0x0
-#define MX6Q_PAD_DISP0_DAT5__GPIO4_IO26           0x184 0x498 0x000 0x5 0x0
-#define MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DATA06    0x188 0x49c 0x000 0x0 0x0
-#define MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DATA06    0x188 0x49c 0x000 0x1 0x0
-#define MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3           0x188 0x49c 0x000 0x2 0x0
-#define MX6Q_PAD_DISP0_DAT6__AUD6_RXC             0x188 0x49c 0x000 0x3 0x0
-#define MX6Q_PAD_DISP0_DAT6__GPIO4_IO27           0x188 0x49c 0x000 0x5 0x0
-#define MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DATA07    0x18c 0x4a0 0x000 0x0 0x0
-#define MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DATA07    0x18c 0x4a0 0x000 0x1 0x0
-#define MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY           0x18c 0x4a0 0x000 0x2 0x0
-#define MX6Q_PAD_DISP0_DAT7__GPIO4_IO28           0x18c 0x4a0 0x000 0x5 0x0
-#define MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DATA08    0x190 0x4a4 0x000 0x0 0x0
-#define MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DATA08    0x190 0x4a4 0x000 0x1 0x0
-#define MX6Q_PAD_DISP0_DAT8__PWM1_OUT             0x190 0x4a4 0x000 0x2 0x0
-#define MX6Q_PAD_DISP0_DAT8__WDOG1_B              0x190 0x4a4 0x000 0x3 0x0
-#define MX6Q_PAD_DISP0_DAT8__GPIO4_IO29           0x190 0x4a4 0x000 0x5 0x0
-#define MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DATA09    0x194 0x4a8 0x000 0x0 0x0
-#define MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DATA09    0x194 0x4a8 0x000 0x1 0x0
-#define MX6Q_PAD_DISP0_DAT9__PWM2_OUT             0x194 0x4a8 0x000 0x2 0x0
-#define MX6Q_PAD_DISP0_DAT9__WDOG2_B              0x194 0x4a8 0x000 0x3 0x0
-#define MX6Q_PAD_DISP0_DAT9__GPIO4_IO30           0x194 0x4a8 0x000 0x5 0x0
-#define MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DATA10   0x198 0x4ac 0x000 0x0 0x0
-#define MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DATA10   0x198 0x4ac 0x000 0x1 0x0
-#define MX6Q_PAD_DISP0_DAT10__GPIO4_IO31          0x198 0x4ac 0x000 0x5 0x0
-#define MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DATA11   0x19c 0x4b0 0x000 0x0 0x0
-#define MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DATA11   0x19c 0x4b0 0x000 0x1 0x0
-#define MX6Q_PAD_DISP0_DAT11__GPIO5_IO05          0x19c 0x4b0 0x000 0x5 0x0
-#define MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DATA12   0x1a0 0x4b4 0x000 0x0 0x0
-#define MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DATA12   0x1a0 0x4b4 0x000 0x1 0x0
-#define MX6Q_PAD_DISP0_DAT12__GPIO5_IO06          0x1a0 0x4b4 0x000 0x5 0x0
-#define MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DATA13   0x1a4 0x4b8 0x000 0x0 0x0
-#define MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DATA13   0x1a4 0x4b8 0x000 0x1 0x0
-#define MX6Q_PAD_DISP0_DAT13__AUD5_RXFS           0x1a4 0x4b8 0x7d8 0x3 0x1
-#define MX6Q_PAD_DISP0_DAT13__GPIO5_IO07          0x1a4 0x4b8 0x000 0x5 0x0
-#define MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DATA14   0x1a8 0x4bc 0x000 0x0 0x0
-#define MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DATA14   0x1a8 0x4bc 0x000 0x1 0x0
-#define MX6Q_PAD_DISP0_DAT14__AUD5_RXC            0x1a8 0x4bc 0x7d4 0x3 0x1
-#define MX6Q_PAD_DISP0_DAT14__GPIO5_IO08          0x1a8 0x4bc 0x000 0x5 0x0
-#define MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DATA15   0x1ac 0x4c0 0x000 0x0 0x0
-#define MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DATA15   0x1ac 0x4c0 0x000 0x1 0x0
-#define MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1          0x1ac 0x4c0 0x804 0x2 0x1
-#define MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1          0x1ac 0x4c0 0x820 0x3 0x1
-#define MX6Q_PAD_DISP0_DAT15__GPIO5_IO09          0x1ac 0x4c0 0x000 0x5 0x0
-#define MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DATA16   0x1b0 0x4c4 0x000 0x0 0x0
-#define MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DATA16   0x1b0 0x4c4 0x000 0x1 0x0
-#define MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI         0x1b0 0x4c4 0x818 0x2 0x1
-#define MX6Q_PAD_DISP0_DAT16__AUD5_TXC            0x1b0 0x4c4 0x7dc 0x3 0x0
-#define MX6Q_PAD_DISP0_DAT16__SDMA_EXT_EVENT0     0x1b0 0x4c4 0x90c 0x4 0x0
-#define MX6Q_PAD_DISP0_DAT16__GPIO5_IO10          0x1b0 0x4c4 0x000 0x5 0x0
-#define MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DATA17   0x1b4 0x4c8 0x000 0x0 0x0
-#define MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DATA17   0x1b4 0x4c8 0x000 0x1 0x0
-#define MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO         0x1b4 0x4c8 0x814 0x2 0x1
-#define MX6Q_PAD_DISP0_DAT17__AUD5_TXD            0x1b4 0x4c8 0x7d0 0x3 0x0
-#define MX6Q_PAD_DISP0_DAT17__SDMA_EXT_EVENT1     0x1b4 0x4c8 0x910 0x4 0x0
-#define MX6Q_PAD_DISP0_DAT17__GPIO5_IO11          0x1b4 0x4c8 0x000 0x5 0x0
-#define MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DATA18   0x1b8 0x4cc 0x000 0x0 0x0
-#define MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DATA18   0x1b8 0x4cc 0x000 0x1 0x0
-#define MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0          0x1b8 0x4cc 0x81c 0x2 0x1
-#define MX6Q_PAD_DISP0_DAT18__AUD5_TXFS           0x1b8 0x4cc 0x7e0 0x3 0x0
-#define MX6Q_PAD_DISP0_DAT18__AUD4_RXFS           0x1b8 0x4cc 0x7c0 0x4 0x0
-#define MX6Q_PAD_DISP0_DAT18__GPIO5_IO12          0x1b8 0x4cc 0x000 0x5 0x0
-#define MX6Q_PAD_DISP0_DAT18__EIM_CS2_B           0x1b8 0x4cc 0x000 0x7 0x0
-#define MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DATA19   0x1bc 0x4d0 0x000 0x0 0x0
-#define MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DATA19   0x1bc 0x4d0 0x000 0x1 0x0
-#define MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK         0x1bc 0x4d0 0x810 0x2 0x1
-#define MX6Q_PAD_DISP0_DAT19__AUD5_RXD            0x1bc 0x4d0 0x7cc 0x3 0x0
-#define MX6Q_PAD_DISP0_DAT19__AUD4_RXC            0x1bc 0x4d0 0x7bc 0x4 0x0
-#define MX6Q_PAD_DISP0_DAT19__GPIO5_IO13          0x1bc 0x4d0 0x000 0x5 0x0
-#define MX6Q_PAD_DISP0_DAT19__EIM_CS3_B           0x1bc 0x4d0 0x000 0x7 0x0
-#define MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DATA20   0x1c0 0x4d4 0x000 0x0 0x0
-#define MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DATA20   0x1c0 0x4d4 0x000 0x1 0x0
-#define MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK         0x1c0 0x4d4 0x7f4 0x2 0x1
-#define MX6Q_PAD_DISP0_DAT20__AUD4_TXC            0x1c0 0x4d4 0x7c4 0x3 0x0
-#define MX6Q_PAD_DISP0_DAT20__GPIO5_IO14          0x1c0 0x4d4 0x000 0x5 0x0
-#define MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DATA21   0x1c4 0x4d8 0x000 0x0 0x0
-#define MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DATA21   0x1c4 0x4d8 0x000 0x1 0x0
-#define MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI         0x1c4 0x4d8 0x7fc 0x2 0x1
-#define MX6Q_PAD_DISP0_DAT21__AUD4_TXD            0x1c4 0x4d8 0x7b8 0x3 0x1
-#define MX6Q_PAD_DISP0_DAT21__GPIO5_IO15          0x1c4 0x4d8 0x000 0x5 0x0
-#define MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DATA22   0x1c8 0x4dc 0x000 0x0 0x0
-#define MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DATA22   0x1c8 0x4dc 0x000 0x1 0x0
-#define MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO         0x1c8 0x4dc 0x7f8 0x2 0x1
-#define MX6Q_PAD_DISP0_DAT22__AUD4_TXFS           0x1c8 0x4dc 0x7c8 0x3 0x1
-#define MX6Q_PAD_DISP0_DAT22__GPIO5_IO16          0x1c8 0x4dc 0x000 0x5 0x0
-#define MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DATA23   0x1cc 0x4e0 0x000 0x0 0x0
-#define MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DATA23   0x1cc 0x4e0 0x000 0x1 0x0
-#define MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0          0x1cc 0x4e0 0x800 0x2 0x1
-#define MX6Q_PAD_DISP0_DAT23__AUD4_RXD            0x1cc 0x4e0 0x7b4 0x3 0x1
-#define MX6Q_PAD_DISP0_DAT23__GPIO5_IO17          0x1cc 0x4e0 0x000 0x5 0x0
-#define MX6Q_PAD_ENET_MDIO__ENET_MDIO             0x1d0 0x4e4 0x840 0x1 0x0
-#define MX6Q_PAD_ENET_MDIO__ESAI_RX_CLK           0x1d0 0x4e4 0x86c 0x2 0x0
-#define MX6Q_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT  0x1d0 0x4e4 0x000 0x4 0x0
-#define MX6Q_PAD_ENET_MDIO__GPIO1_IO22            0x1d0 0x4e4 0x000 0x5 0x0
-#define MX6Q_PAD_ENET_MDIO__SPDIF_LOCK            0x1d0 0x4e4 0x000 0x6 0x0
-#define MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK        0x1d4 0x4e8 0x000 0x1 0x0
-#define MX6Q_PAD_ENET_REF_CLK__ESAI_RX_FS         0x1d4 0x4e8 0x85c 0x2 0x0
-#define MX6Q_PAD_ENET_REF_CLK__GPIO1_IO23         0x1d4 0x4e8 0x000 0x5 0x0
-#define MX6Q_PAD_ENET_REF_CLK__SPDIF_SR_CLK       0x1d4 0x4e8 0x000 0x6 0x0
-#define MX6Q_PAD_ENET_RX_ER__USB_OTG_ID           0x1d8 0x4ec 0x000 0x0 0x0
-#define MX6Q_PAD_ENET_RX_ER__ENET_RX_ER           0x1d8 0x4ec 0x000 0x1 0x0
-#define MX6Q_PAD_ENET_RX_ER__ESAI_RX_HF_CLK       0x1d8 0x4ec 0x864 0x2 0x0
-#define MX6Q_PAD_ENET_RX_ER__SPDIF_IN             0x1d8 0x4ec 0x914 0x3 0x1
-#define MX6Q_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT 0x1d8 0x4ec 0x000 0x4 0x0
-#define MX6Q_PAD_ENET_RX_ER__GPIO1_IO24           0x1d8 0x4ec 0x000 0x5 0x0
-#define MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN          0x1dc 0x4f0 0x858 0x1 0x1
-#define MX6Q_PAD_ENET_CRS_DV__ESAI_TX_CLK         0x1dc 0x4f0 0x870 0x2 0x0
-#define MX6Q_PAD_ENET_CRS_DV__SPDIF_EXT_CLK       0x1dc 0x4f0 0x918 0x3 0x1
-#define MX6Q_PAD_ENET_CRS_DV__GPIO1_IO25          0x1dc 0x4f0 0x000 0x5 0x0
-#define MX6Q_PAD_ENET_RXD1__MLB_SIG               0x1e0 0x4f4 0x908 0x0 0x0
-#define MX6Q_PAD_ENET_RXD1__ENET_RX_DATA1         0x1e0 0x4f4 0x84c 0x1 0x1
-#define MX6Q_PAD_ENET_RXD1__ESAI_TX_FS            0x1e0 0x4f4 0x860 0x2 0x0
-#define MX6Q_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT  0x1e0 0x4f4 0x000 0x4 0x0
-#define MX6Q_PAD_ENET_RXD1__GPIO1_IO26            0x1e0 0x4f4 0x000 0x5 0x0
-#define MX6Q_PAD_ENET_RXD0__ENET_RX_DATA0         0x1e4 0x4f8 0x848 0x1 0x1
-#define MX6Q_PAD_ENET_RXD0__ESAI_TX_HF_CLK        0x1e4 0x4f8 0x868 0x2 0x0
-#define MX6Q_PAD_ENET_RXD0__SPDIF_OUT             0x1e4 0x4f8 0x000 0x3 0x0
-#define MX6Q_PAD_ENET_RXD0__GPIO1_IO27            0x1e4 0x4f8 0x000 0x5 0x0
-#define MX6Q_PAD_ENET_TX_EN__ENET_TX_EN           0x1e8 0x4fc 0x000 0x1 0x0
-#define MX6Q_PAD_ENET_TX_EN__ESAI_TX3_RX2         0x1e8 0x4fc 0x880 0x2 0x0
-#define MX6Q_PAD_ENET_TX_EN__GPIO1_IO28           0x1e8 0x4fc 0x000 0x5 0x0
-#define MX6Q_PAD_ENET_TXD1__MLB_CLK               0x1ec 0x500 0x900 0x0 0x0
-#define MX6Q_PAD_ENET_TXD1__ENET_TX_DATA1         0x1ec 0x500 0x000 0x1 0x0
-#define MX6Q_PAD_ENET_TXD1__ESAI_TX2_RX3          0x1ec 0x500 0x87c 0x2 0x0
-#define MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN   0x1ec 0x500 0x000 0x4 0x0
-#define MX6Q_PAD_ENET_TXD1__GPIO1_IO29            0x1ec 0x500 0x000 0x5 0x0
-#define MX6Q_PAD_ENET_TXD0__ENET_TX_DATA0         0x1f0 0x504 0x000 0x1 0x0
-#define MX6Q_PAD_ENET_TXD0__ESAI_TX4_RX1          0x1f0 0x504 0x884 0x2 0x0
-#define MX6Q_PAD_ENET_TXD0__GPIO1_IO30            0x1f0 0x504 0x000 0x5 0x0
-#define MX6Q_PAD_ENET_MDC__MLB_DATA               0x1f4 0x508 0x904 0x0 0x0
-#define MX6Q_PAD_ENET_MDC__ENET_MDC               0x1f4 0x508 0x000 0x1 0x0
-#define MX6Q_PAD_ENET_MDC__ESAI_TX5_RX0           0x1f4 0x508 0x888 0x2 0x0
-#define MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN    0x1f4 0x508 0x000 0x4 0x0
-#define MX6Q_PAD_ENET_MDC__GPIO1_IO31             0x1f4 0x508 0x000 0x5 0x0
-#define MX6Q_PAD_KEY_COL0__ECSPI1_SCLK            0x1f8 0x5c8 0x7f4 0x0 0x2
-#define MX6Q_PAD_KEY_COL0__ENET_RX_DATA3          0x1f8 0x5c8 0x854 0x1 0x1
-#define MX6Q_PAD_KEY_COL0__AUD5_TXC               0x1f8 0x5c8 0x7dc 0x2 0x1
-#define MX6Q_PAD_KEY_COL0__KEY_COL0               0x1f8 0x5c8 0x000 0x3 0x0
-#define MX6Q_PAD_KEY_COL0__UART4_TX_DATA          0x1f8 0x5c8 0x000 0x4 0x0
-#define MX6Q_PAD_KEY_COL0__UART4_RX_DATA          0x1f8 0x5c8 0x938 0x4 0x0
-#define MX6Q_PAD_KEY_COL0__GPIO4_IO06             0x1f8 0x5c8 0x000 0x5 0x0
-#define MX6Q_PAD_KEY_COL0__DCIC1_OUT              0x1f8 0x5c8 0x000 0x6 0x0
-#define MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI            0x1fc 0x5cc 0x7fc 0x0 0x2
-#define MX6Q_PAD_KEY_ROW0__ENET_TX_DATA3          0x1fc 0x5cc 0x000 0x1 0x0
-#define MX6Q_PAD_KEY_ROW0__AUD5_TXD               0x1fc 0x5cc 0x7d0 0x2 0x1
-#define MX6Q_PAD_KEY_ROW0__KEY_ROW0               0x1fc 0x5cc 0x000 0x3 0x0
-#define MX6Q_PAD_KEY_ROW0__UART4_RX_DATA          0x1fc 0x5cc 0x938 0x4 0x1
-#define MX6Q_PAD_KEY_ROW0__UART4_TX_DATA          0x1fc 0x5cc 0x000 0x4 0x0
-#define MX6Q_PAD_KEY_ROW0__GPIO4_IO07             0x1fc 0x5cc 0x000 0x5 0x0
-#define MX6Q_PAD_KEY_ROW0__DCIC2_OUT              0x1fc 0x5cc 0x000 0x6 0x0
-#define MX6Q_PAD_KEY_COL1__ECSPI1_MISO            0x200 0x5d0 0x7f8 0x0 0x2
-#define MX6Q_PAD_KEY_COL1__ENET_MDIO              0x200 0x5d0 0x840 0x1 0x1
-#define MX6Q_PAD_KEY_COL1__AUD5_TXFS              0x200 0x5d0 0x7e0 0x2 0x1
-#define MX6Q_PAD_KEY_COL1__KEY_COL1               0x200 0x5d0 0x000 0x3 0x0
-#define MX6Q_PAD_KEY_COL1__UART5_TX_DATA          0x200 0x5d0 0x000 0x4 0x0
-#define MX6Q_PAD_KEY_COL1__UART5_RX_DATA          0x200 0x5d0 0x940 0x4 0x0
-#define MX6Q_PAD_KEY_COL1__GPIO4_IO08             0x200 0x5d0 0x000 0x5 0x0
-#define MX6Q_PAD_KEY_COL1__SD1_VSELECT            0x200 0x5d0 0x000 0x6 0x0
-#define MX6Q_PAD_KEY_ROW1__ECSPI1_SS0             0x204 0x5d4 0x800 0x0 0x2
-#define MX6Q_PAD_KEY_ROW1__ENET_COL               0x204 0x5d4 0x000 0x1 0x0
-#define MX6Q_PAD_KEY_ROW1__AUD5_RXD               0x204 0x5d4 0x7cc 0x2 0x1
-#define MX6Q_PAD_KEY_ROW1__KEY_ROW1               0x204 0x5d4 0x000 0x3 0x0
-#define MX6Q_PAD_KEY_ROW1__UART5_RX_DATA          0x204 0x5d4 0x940 0x4 0x1
-#define MX6Q_PAD_KEY_ROW1__UART5_TX_DATA          0x204 0x5d4 0x000 0x4 0x0
-#define MX6Q_PAD_KEY_ROW1__GPIO4_IO09             0x204 0x5d4 0x000 0x5 0x0
-#define MX6Q_PAD_KEY_ROW1__SD2_VSELECT            0x204 0x5d4 0x000 0x6 0x0
-#define MX6Q_PAD_KEY_COL2__ECSPI1_SS1             0x208 0x5d8 0x804 0x0 0x2
-#define MX6Q_PAD_KEY_COL2__ENET_RX_DATA2          0x208 0x5d8 0x850 0x1 0x1
-#define MX6Q_PAD_KEY_COL2__FLEXCAN1_TX            0x208 0x5d8 0x000 0x2 0x0
-#define MX6Q_PAD_KEY_COL2__KEY_COL2               0x208 0x5d8 0x000 0x3 0x0
-#define MX6Q_PAD_KEY_COL2__ENET_MDC               0x208 0x5d8 0x000 0x4 0x0
-#define MX6Q_PAD_KEY_COL2__GPIO4_IO10             0x208 0x5d8 0x000 0x5 0x0
-#define MX6Q_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE    0x208 0x5d8 0x000 0x6 0x0
-#define MX6Q_PAD_KEY_ROW2__ECSPI1_SS2             0x20c 0x5dc 0x808 0x0 0x1
-#define MX6Q_PAD_KEY_ROW2__ENET_TX_DATA2          0x20c 0x5dc 0x000 0x1 0x0
-#define MX6Q_PAD_KEY_ROW2__FLEXCAN1_RX            0x20c 0x5dc 0x7e4 0x2 0x0
-#define MX6Q_PAD_KEY_ROW2__KEY_ROW2               0x20c 0x5dc 0x000 0x3 0x0
-#define MX6Q_PAD_KEY_ROW2__SD2_VSELECT            0x20c 0x5dc 0x000 0x4 0x0
-#define MX6Q_PAD_KEY_ROW2__GPIO4_IO11             0x20c 0x5dc 0x000 0x5 0x0
-#define MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE       0x20c 0x5dc 0x88c 0x6 0x1
-#define MX6Q_PAD_KEY_COL3__ECSPI1_SS3             0x210 0x5e0 0x80c 0x0 0x1
-#define MX6Q_PAD_KEY_COL3__ENET_CRS               0x210 0x5e0 0x000 0x1 0x0
-#define MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL        0x210 0x5e0 0x890 0x2 0x1
-#define MX6Q_PAD_KEY_COL3__KEY_COL3               0x210 0x5e0 0x000 0x3 0x0
-#define MX6Q_PAD_KEY_COL3__I2C2_SCL               0x210 0x5e0 0x8a0 0x4 0x1
-#define MX6Q_PAD_KEY_COL3__GPIO4_IO12             0x210 0x5e0 0x000 0x5 0x0
-#define MX6Q_PAD_KEY_COL3__SPDIF_IN               0x210 0x5e0 0x914 0x6 0x2
-#define MX6Q_PAD_KEY_ROW3__ASRC_EXT_CLK           0x214 0x5e4 0x7b0 0x1 0x0
-#define MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA        0x214 0x5e4 0x894 0x2 0x1
-#define MX6Q_PAD_KEY_ROW3__KEY_ROW3               0x214 0x5e4 0x000 0x3 0x0
-#define MX6Q_PAD_KEY_ROW3__I2C2_SDA               0x214 0x5e4 0x8a4 0x4 0x1
-#define MX6Q_PAD_KEY_ROW3__GPIO4_IO13             0x214 0x5e4 0x000 0x5 0x0
-#define MX6Q_PAD_KEY_ROW3__SD1_VSELECT            0x214 0x5e4 0x000 0x6 0x0
-#define MX6Q_PAD_KEY_COL4__FLEXCAN2_TX            0x218 0x5e8 0x000 0x0 0x0
-#define MX6Q_PAD_KEY_COL4__IPU1_SISG4             0x218 0x5e8 0x000 0x1 0x0
-#define MX6Q_PAD_KEY_COL4__USB_OTG_OC             0x218 0x5e8 0x944 0x2 0x1
-#define MX6Q_PAD_KEY_COL4__KEY_COL4               0x218 0x5e8 0x000 0x3 0x0
-#define MX6Q_PAD_KEY_COL4__UART5_RTS_B            0x218 0x5e8 0x93c 0x4 0x0
-#define MX6Q_PAD_KEY_COL4__UART5_CTS_B            0x218 0x5e8 0x000 0x4 0x0
-#define MX6Q_PAD_KEY_COL4__GPIO4_IO14             0x218 0x5e8 0x000 0x5 0x0
-#define MX6Q_PAD_KEY_ROW4__FLEXCAN2_RX            0x21c 0x5ec 0x7e8 0x0 0x0
-#define MX6Q_PAD_KEY_ROW4__IPU1_SISG5             0x21c 0x5ec 0x000 0x1 0x0
-#define MX6Q_PAD_KEY_ROW4__USB_OTG_PWR            0x21c 0x5ec 0x000 0x2 0x0
-#define MX6Q_PAD_KEY_ROW4__KEY_ROW4               0x21c 0x5ec 0x000 0x3 0x0
-#define MX6Q_PAD_KEY_ROW4__UART5_CTS_B            0x21c 0x5ec 0x000 0x4 0x0
-#define MX6Q_PAD_KEY_ROW4__UART5_RTS_B            0x21c 0x5ec 0x93c 0x4 0x1
-#define MX6Q_PAD_KEY_ROW4__GPIO4_IO15             0x21c 0x5ec 0x000 0x5 0x0
-#define MX6Q_PAD_GPIO_0__CCM_CLKO1                0x220 0x5f0 0x000 0x0 0x0
-#define MX6Q_PAD_GPIO_0__KEY_COL5                 0x220 0x5f0 0x8e8 0x2 0x0
-#define MX6Q_PAD_GPIO_0__ASRC_EXT_CLK             0x220 0x5f0 0x7b0 0x3 0x1
-#define MX6Q_PAD_GPIO_0__EPIT1_OUT                0x220 0x5f0 0x000 0x4 0x0
-#define MX6Q_PAD_GPIO_0__GPIO1_IO00               0x220 0x5f0 0x000 0x5 0x0
-#define MX6Q_PAD_GPIO_0__USB_H1_PWR               0x220 0x5f0 0x000 0x6 0x0
-#define MX6Q_PAD_GPIO_0__SNVS_VIO_5               0x220 0x5f0 0x000 0x7 0x0
-#define MX6Q_PAD_GPIO_1__ESAI_RX_CLK              0x224 0x5f4 0x86c 0x0 0x1
-#define MX6Q_PAD_GPIO_1__WDOG2_B                  0x224 0x5f4 0x000 0x1 0x0
-#define MX6Q_PAD_GPIO_1__KEY_ROW5                 0x224 0x5f4 0x8f4 0x2 0x0
-#define MX6Q_PAD_GPIO_1__USB_OTG_ID               0x224 0x5f4 0x000 0x3 0x0
-#define MX6Q_PAD_GPIO_1__PWM2_OUT                 0x224 0x5f4 0x000 0x4 0x0
-#define MX6Q_PAD_GPIO_1__GPIO1_IO01               0x224 0x5f4 0x000 0x5 0x0
-#define MX6Q_PAD_GPIO_1__SD1_CD_B                 0x224 0x5f4 0x000 0x6 0x0
-#define MX6Q_PAD_GPIO_9__ESAI_RX_FS               0x228 0x5f8 0x85c 0x0 0x1
-#define MX6Q_PAD_GPIO_9__WDOG1_B                  0x228 0x5f8 0x000 0x1 0x0
-#define MX6Q_PAD_GPIO_9__KEY_COL6                 0x228 0x5f8 0x8ec 0x2 0x0
-#define MX6Q_PAD_GPIO_9__CCM_REF_EN_B             0x228 0x5f8 0x000 0x3 0x0
-#define MX6Q_PAD_GPIO_9__PWM1_OUT                 0x228 0x5f8 0x000 0x4 0x0
-#define MX6Q_PAD_GPIO_9__GPIO1_IO09               0x228 0x5f8 0x000 0x5 0x0
-#define MX6Q_PAD_GPIO_9__SD1_WP                   0x228 0x5f8 0x94c 0x6 0x1
-#define MX6Q_PAD_GPIO_3__ESAI_RX_HF_CLK           0x22c 0x5fc 0x864 0x0 0x1
-#define MX6Q_PAD_GPIO_3__I2C3_SCL                 0x22c 0x5fc 0x8a8 0x2 0x1
-#define MX6Q_PAD_GPIO_3__XTALOSC_REF_CLK_24M      0x22c 0x5fc 0x000 0x3 0x0
-#define MX6Q_PAD_GPIO_3__CCM_CLKO2                0x22c 0x5fc 0x000 0x4 0x0
-#define MX6Q_PAD_GPIO_3__GPIO1_IO03               0x22c 0x5fc 0x000 0x5 0x0
-#define MX6Q_PAD_GPIO_3__USB_H1_OC                0x22c 0x5fc 0x948 0x6 0x1
-#define MX6Q_PAD_GPIO_3__MLB_CLK                  0x22c 0x5fc 0x900 0x7 0x1
-#define MX6Q_PAD_GPIO_6__ESAI_TX_CLK              0x230 0x600 0x870 0x0 0x1
-#define MX6Q_PAD_GPIO_6__I2C3_SDA                 0x230 0x600 0x8ac 0x2 0x1
-#define MX6Q_PAD_GPIO_6__GPIO1_IO06               0x230 0x600 0x000 0x5 0x0
-#define MX6Q_PAD_GPIO_6__SD2_LCTL                 0x230 0x600 0x000 0x6 0x0
-#define MX6Q_PAD_GPIO_6__MLB_SIG                  0x230 0x600 0x908 0x7 0x1
-#define MX6Q_PAD_GPIO_2__ESAI_TX_FS               0x234 0x604 0x860 0x0 0x1
-#define MX6Q_PAD_GPIO_2__KEY_ROW6                 0x234 0x604 0x8f8 0x2 0x1
-#define MX6Q_PAD_GPIO_2__GPIO1_IO02               0x234 0x604 0x000 0x5 0x0
-#define MX6Q_PAD_GPIO_2__SD2_WP                   0x234 0x604 0x000 0x6 0x0
-#define MX6Q_PAD_GPIO_2__MLB_DATA                 0x234 0x604 0x904 0x7 0x1
-#define MX6Q_PAD_GPIO_4__ESAI_TX_HF_CLK           0x238 0x608 0x868 0x0 0x1
-#define MX6Q_PAD_GPIO_4__KEY_COL7                 0x238 0x608 0x8f0 0x2 0x1
-#define MX6Q_PAD_GPIO_4__GPIO1_IO04               0x238 0x608 0x000 0x5 0x0
-#define MX6Q_PAD_GPIO_4__SD2_CD_B                 0x238 0x608 0x000 0x6 0x0
-#define MX6Q_PAD_GPIO_5__ESAI_TX2_RX3             0x23c 0x60c 0x87c 0x0 0x1
-#define MX6Q_PAD_GPIO_5__KEY_ROW7                 0x23c 0x60c 0x8fc 0x2 0x1
-#define MX6Q_PAD_GPIO_5__CCM_CLKO1                0x23c 0x60c 0x000 0x3 0x0
-#define MX6Q_PAD_GPIO_5__GPIO1_IO05               0x23c 0x60c 0x000 0x5 0x0
-#define MX6Q_PAD_GPIO_5__I2C3_SCL                 0x23c 0x60c 0x8a8 0x6 0x2
-#define MX6Q_PAD_GPIO_5__ARM_EVENTI               0x23c 0x60c 0x000 0x7 0x0
-#define MX6Q_PAD_GPIO_7__ESAI_TX4_RX1             0x240 0x610 0x884 0x0 0x1
-#define MX6Q_PAD_GPIO_7__ECSPI5_RDY               0x240 0x610 0x000 0x1 0x0
-#define MX6Q_PAD_GPIO_7__EPIT1_OUT                0x240 0x610 0x000 0x2 0x0
-#define MX6Q_PAD_GPIO_7__FLEXCAN1_TX              0x240 0x610 0x000 0x3 0x0
-#define MX6Q_PAD_GPIO_7__UART2_TX_DATA            0x240 0x610 0x000 0x4 0x0
-#define MX6Q_PAD_GPIO_7__UART2_RX_DATA            0x240 0x610 0x928 0x4 0x2
-#define MX6Q_PAD_GPIO_7__GPIO1_IO07               0x240 0x610 0x000 0x5 0x0
-#define MX6Q_PAD_GPIO_7__SPDIF_LOCK               0x240 0x610 0x000 0x6 0x0
-#define MX6Q_PAD_GPIO_7__USB_OTG_HOST_MODE        0x240 0x610 0x000 0x7 0x0
-#define MX6Q_PAD_GPIO_8__ESAI_TX5_RX0             0x244 0x614 0x888 0x0 0x1
-#define MX6Q_PAD_GPIO_8__XTALOSC_REF_CLK_32K      0x244 0x614 0x000 0x1 0x0
-#define MX6Q_PAD_GPIO_8__EPIT2_OUT                0x244 0x614 0x000 0x2 0x0
-#define MX6Q_PAD_GPIO_8__FLEXCAN1_RX              0x244 0x614 0x7e4 0x3 0x1
-#define MX6Q_PAD_GPIO_8__UART2_RX_DATA            0x244 0x614 0x928 0x4 0x3
-#define MX6Q_PAD_GPIO_8__UART2_TX_DATA            0x244 0x614 0x000 0x4 0x0
-#define MX6Q_PAD_GPIO_8__GPIO1_IO08               0x244 0x614 0x000 0x5 0x0
-#define MX6Q_PAD_GPIO_8__SPDIF_SR_CLK             0x244 0x614 0x000 0x6 0x0
-#define MX6Q_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE     0x244 0x614 0x000 0x7 0x0
-#define MX6Q_PAD_GPIO_16__ESAI_TX3_RX2            0x248 0x618 0x880 0x0 0x1
-#define MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN     0x248 0x618 0x000 0x1 0x0
-#define MX6Q_PAD_GPIO_16__ENET_REF_CLK            0x248 0x618 0x83c 0x2 0x1
-#define MX6Q_PAD_GPIO_16__SD1_LCTL                0x248 0x618 0x000 0x3 0x0
-#define MX6Q_PAD_GPIO_16__SPDIF_IN                0x248 0x618 0x914 0x4 0x3
-#define MX6Q_PAD_GPIO_16__GPIO7_IO11              0x248 0x618 0x000 0x5 0x0
-#define MX6Q_PAD_GPIO_16__I2C3_SDA                0x248 0x618 0x8ac 0x6 0x2
-#define MX6Q_PAD_GPIO_16__JTAG_DE_B               0x248 0x618 0x000 0x7 0x0
-#define MX6Q_PAD_GPIO_17__ESAI_TX0                0x24c 0x61c 0x874 0x0 0x0
-#define MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN     0x24c 0x61c 0x000 0x1 0x0
-#define MX6Q_PAD_GPIO_17__CCM_PMIC_READY          0x24c 0x61c 0x7f0 0x2 0x1
-#define MX6Q_PAD_GPIO_17__SDMA_EXT_EVENT0         0x24c 0x61c 0x90c 0x3 0x1
-#define MX6Q_PAD_GPIO_17__SPDIF_OUT               0x24c 0x61c 0x000 0x4 0x0
-#define MX6Q_PAD_GPIO_17__GPIO7_IO12              0x24c 0x61c 0x000 0x5 0x0
-#define MX6Q_PAD_GPIO_18__ESAI_TX1                0x250 0x620 0x878 0x0 0x0
-#define MX6Q_PAD_GPIO_18__ENET_RX_CLK             0x250 0x620 0x844 0x1 0x1
-#define MX6Q_PAD_GPIO_18__SD3_VSELECT             0x250 0x620 0x000 0x2 0x0
-#define MX6Q_PAD_GPIO_18__SDMA_EXT_EVENT1         0x250 0x620 0x910 0x3 0x1
-#define MX6Q_PAD_GPIO_18__ASRC_EXT_CLK            0x250 0x620 0x7b0 0x4 0x2
-#define MX6Q_PAD_GPIO_18__GPIO7_IO13              0x250 0x620 0x000 0x5 0x0
-#define MX6Q_PAD_GPIO_18__SNVS_VIO_5_CTL          0x250 0x620 0x000 0x6 0x0
-#define MX6Q_PAD_GPIO_19__KEY_COL5                0x254 0x624 0x8e8 0x0 0x1
-#define MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT    0x254 0x624 0x000 0x1 0x0
-#define MX6Q_PAD_GPIO_19__SPDIF_OUT               0x254 0x624 0x000 0x2 0x0
-#define MX6Q_PAD_GPIO_19__CCM_CLKO1               0x254 0x624 0x000 0x3 0x0
-#define MX6Q_PAD_GPIO_19__ECSPI1_RDY              0x254 0x624 0x000 0x4 0x0
-#define MX6Q_PAD_GPIO_19__GPIO4_IO05              0x254 0x624 0x000 0x5 0x0
-#define MX6Q_PAD_GPIO_19__ENET_TX_ER              0x254 0x624 0x000 0x6 0x0
-#define MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK    0x258 0x628 0x000 0x0 0x0
-#define MX6Q_PAD_CSI0_PIXCLK__GPIO5_IO18          0x258 0x628 0x000 0x5 0x0
-#define MX6Q_PAD_CSI0_PIXCLK__ARM_EVENTO          0x258 0x628 0x000 0x7 0x0
-#define MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC       0x25c 0x62c 0x000 0x0 0x0
-#define MX6Q_PAD_CSI0_MCLK__CCM_CLKO1             0x25c 0x62c 0x000 0x3 0x0
-#define MX6Q_PAD_CSI0_MCLK__GPIO5_IO19            0x25c 0x62c 0x000 0x5 0x0
-#define MX6Q_PAD_CSI0_MCLK__ARM_TRACE_CTL         0x25c 0x62c 0x000 0x7 0x0
-#define MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN  0x260 0x630 0x000 0x0 0x0
-#define MX6Q_PAD_CSI0_DATA_EN__EIM_DATA00         0x260 0x630 0x000 0x1 0x0
-#define MX6Q_PAD_CSI0_DATA_EN__GPIO5_IO20         0x260 0x630 0x000 0x5 0x0
-#define MX6Q_PAD_CSI0_DATA_EN__ARM_TRACE_CLK      0x260 0x630 0x000 0x7 0x0
-#define MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC      0x264 0x634 0x000 0x0 0x0
-#define MX6Q_PAD_CSI0_VSYNC__EIM_DATA01           0x264 0x634 0x000 0x1 0x0
-#define MX6Q_PAD_CSI0_VSYNC__GPIO5_IO21           0x264 0x634 0x000 0x5 0x0
-#define MX6Q_PAD_CSI0_VSYNC__ARM_TRACE00          0x264 0x634 0x000 0x7 0x0
-#define MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_DATA04      0x268 0x638 0x000 0x0 0x0
-#define MX6Q_PAD_CSI0_DAT4__EIM_DATA02            0x268 0x638 0x000 0x1 0x0
-#define MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK           0x268 0x638 0x7f4 0x2 0x3
-#define MX6Q_PAD_CSI0_DAT4__KEY_COL5              0x268 0x638 0x8e8 0x3 0x2
-#define MX6Q_PAD_CSI0_DAT4__AUD3_TXC              0x268 0x638 0x000 0x4 0x0
-#define MX6Q_PAD_CSI0_DAT4__GPIO5_IO22            0x268 0x638 0x000 0x5 0x0
-#define MX6Q_PAD_CSI0_DAT4__ARM_TRACE01           0x268 0x638 0x000 0x7 0x0
-#define MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_DATA05      0x26c 0x63c 0x000 0x0 0x0
-#define MX6Q_PAD_CSI0_DAT5__EIM_DATA03            0x26c 0x63c 0x000 0x1 0x0
-#define MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI           0x26c 0x63c 0x7fc 0x2 0x3
-#define MX6Q_PAD_CSI0_DAT5__KEY_ROW5              0x26c 0x63c 0x8f4 0x3 0x1
-#define MX6Q_PAD_CSI0_DAT5__AUD3_TXD              0x26c 0x63c 0x000 0x4 0x0
-#define MX6Q_PAD_CSI0_DAT5__GPIO5_IO23            0x26c 0x63c 0x000 0x5 0x0
-#define MX6Q_PAD_CSI0_DAT5__ARM_TRACE02           0x26c 0x63c 0x000 0x7 0x0
-#define MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_DATA06      0x270 0x640 0x000 0x0 0x0
-#define MX6Q_PAD_CSI0_DAT6__EIM_DATA04            0x270 0x640 0x000 0x1 0x0
-#define MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO           0x270 0x640 0x7f8 0x2 0x3
-#define MX6Q_PAD_CSI0_DAT6__KEY_COL6              0x270 0x640 0x8ec 0x3 0x1
-#define MX6Q_PAD_CSI0_DAT6__AUD3_TXFS             0x270 0x640 0x000 0x4 0x0
-#define MX6Q_PAD_CSI0_DAT6__GPIO5_IO24            0x270 0x640 0x000 0x5 0x0
-#define MX6Q_PAD_CSI0_DAT6__ARM_TRACE03           0x270 0x640 0x000 0x7 0x0
-#define MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_DATA07      0x274 0x644 0x000 0x0 0x0
-#define MX6Q_PAD_CSI0_DAT7__EIM_DATA05            0x274 0x644 0x000 0x1 0x0
-#define MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0            0x274 0x644 0x800 0x2 0x3
-#define MX6Q_PAD_CSI0_DAT7__KEY_ROW6              0x274 0x644 0x8f8 0x3 0x2
-#define MX6Q_PAD_CSI0_DAT7__AUD3_RXD              0x274 0x644 0x000 0x4 0x0
-#define MX6Q_PAD_CSI0_DAT7__GPIO5_IO25            0x274 0x644 0x000 0x5 0x0
-#define MX6Q_PAD_CSI0_DAT7__ARM_TRACE04           0x274 0x644 0x000 0x7 0x0
-#define MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_DATA08      0x278 0x648 0x000 0x0 0x0
-#define MX6Q_PAD_CSI0_DAT8__EIM_DATA06            0x278 0x648 0x000 0x1 0x0
-#define MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK           0x278 0x648 0x810 0x2 0x2
-#define MX6Q_PAD_CSI0_DAT8__KEY_COL7              0x278 0x648 0x8f0 0x3 0x2
-#define MX6Q_PAD_CSI0_DAT8__I2C1_SDA              0x278 0x648 0x89c 0x4 0x1
-#define MX6Q_PAD_CSI0_DAT8__GPIO5_IO26            0x278 0x648 0x000 0x5 0x0
-#define MX6Q_PAD_CSI0_DAT8__ARM_TRACE05           0x278 0x648 0x000 0x7 0x0
-#define MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_DATA09      0x27c 0x64c 0x000 0x0 0x0
-#define MX6Q_PAD_CSI0_DAT9__EIM_DATA07            0x27c 0x64c 0x000 0x1 0x0
-#define MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI           0x27c 0x64c 0x818 0x2 0x2
-#define MX6Q_PAD_CSI0_DAT9__KEY_ROW7              0x27c 0x64c 0x8fc 0x3 0x2
-#define MX6Q_PAD_CSI0_DAT9__I2C1_SCL              0x27c 0x64c 0x898 0x4 0x1
-#define MX6Q_PAD_CSI0_DAT9__GPIO5_IO27            0x27c 0x64c 0x000 0x5 0x0
-#define MX6Q_PAD_CSI0_DAT9__ARM_TRACE06           0x27c 0x64c 0x000 0x7 0x0
-#define MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_DATA10     0x280 0x650 0x000 0x0 0x0
-#define MX6Q_PAD_CSI0_DAT10__AUD3_RXC             0x280 0x650 0x000 0x1 0x0
-#define MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO          0x280 0x650 0x814 0x2 0x2
-#define MX6Q_PAD_CSI0_DAT10__UART1_TX_DATA        0x280 0x650 0x000 0x3 0x0
-#define MX6Q_PAD_CSI0_DAT10__UART1_RX_DATA        0x280 0x650 0x920 0x3 0x0
-#define MX6Q_PAD_CSI0_DAT10__GPIO5_IO28           0x280 0x650 0x000 0x5 0x0
-#define MX6Q_PAD_CSI0_DAT10__ARM_TRACE07          0x280 0x650 0x000 0x7 0x0
-#define MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_DATA11     0x284 0x654 0x000 0x0 0x0
-#define MX6Q_PAD_CSI0_DAT11__AUD3_RXFS            0x284 0x654 0x000 0x1 0x0
-#define MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0           0x284 0x654 0x81c 0x2 0x2
-#define MX6Q_PAD_CSI0_DAT11__UART1_RX_DATA        0x284 0x654 0x920 0x3 0x1
-#define MX6Q_PAD_CSI0_DAT11__UART1_TX_DATA        0x284 0x654 0x000 0x3 0x0
-#define MX6Q_PAD_CSI0_DAT11__GPIO5_IO29           0x284 0x654 0x000 0x5 0x0
-#define MX6Q_PAD_CSI0_DAT11__ARM_TRACE08          0x284 0x654 0x000 0x7 0x0
-#define MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_DATA12     0x288 0x658 0x000 0x0 0x0
-#define MX6Q_PAD_CSI0_DAT12__EIM_DATA08           0x288 0x658 0x000 0x1 0x0
-#define MX6Q_PAD_CSI0_DAT12__UART4_TX_DATA        0x288 0x658 0x000 0x3 0x0
-#define MX6Q_PAD_CSI0_DAT12__UART4_RX_DATA        0x288 0x658 0x938 0x3 0x2
-#define MX6Q_PAD_CSI0_DAT12__GPIO5_IO30           0x288 0x658 0x000 0x5 0x0
-#define MX6Q_PAD_CSI0_DAT12__ARM_TRACE09          0x288 0x658 0x000 0x7 0x0
-#define MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_DATA13     0x28c 0x65c 0x000 0x0 0x0
-#define MX6Q_PAD_CSI0_DAT13__EIM_DATA09           0x28c 0x65c 0x000 0x1 0x0
-#define MX6Q_PAD_CSI0_DAT13__UART4_RX_DATA        0x28c 0x65c 0x938 0x3 0x3
-#define MX6Q_PAD_CSI0_DAT13__UART4_TX_DATA        0x28c 0x65c 0x000 0x3 0x0
-#define MX6Q_PAD_CSI0_DAT13__GPIO5_IO31           0x28c 0x65c 0x000 0x5 0x0
-#define MX6Q_PAD_CSI0_DAT13__ARM_TRACE10          0x28c 0x65c 0x000 0x7 0x0
-#define MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_DATA14     0x290 0x660 0x000 0x0 0x0
-#define MX6Q_PAD_CSI0_DAT14__EIM_DATA10           0x290 0x660 0x000 0x1 0x0
-#define MX6Q_PAD_CSI0_DAT14__UART5_TX_DATA        0x290 0x660 0x000 0x3 0x0
-#define MX6Q_PAD_CSI0_DAT14__UART5_RX_DATA        0x290 0x660 0x940 0x3 0x2
-#define MX6Q_PAD_CSI0_DAT14__GPIO6_IO00           0x290 0x660 0x000 0x5 0x0
-#define MX6Q_PAD_CSI0_DAT14__ARM_TRACE11          0x290 0x660 0x000 0x7 0x0
-#define MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_DATA15     0x294 0x664 0x000 0x0 0x0
-#define MX6Q_PAD_CSI0_DAT15__EIM_DATA11           0x294 0x664 0x000 0x1 0x0
-#define MX6Q_PAD_CSI0_DAT15__UART5_RX_DATA        0x294 0x664 0x940 0x3 0x3
-#define MX6Q_PAD_CSI0_DAT15__UART5_TX_DATA        0x294 0x664 0x000 0x3 0x0
-#define MX6Q_PAD_CSI0_DAT15__GPIO6_IO01           0x294 0x664 0x000 0x5 0x0
-#define MX6Q_PAD_CSI0_DAT15__ARM_TRACE12          0x294 0x664 0x000 0x7 0x0
-#define MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_DATA16     0x298 0x668 0x000 0x0 0x0
-#define MX6Q_PAD_CSI0_DAT16__EIM_DATA12           0x298 0x668 0x000 0x1 0x0
-#define MX6Q_PAD_CSI0_DAT16__UART4_RTS_B          0x298 0x668 0x934 0x3 0x0
-#define MX6Q_PAD_CSI0_DAT16__UART4_CTS_B          0x298 0x668 0x000 0x3 0x0
-#define MX6Q_PAD_CSI0_DAT16__GPIO6_IO02           0x298 0x668 0x000 0x5 0x0
-#define MX6Q_PAD_CSI0_DAT16__ARM_TRACE13          0x298 0x668 0x000 0x7 0x0
-#define MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_DATA17     0x29c 0x66c 0x000 0x0 0x0
-#define MX6Q_PAD_CSI0_DAT17__EIM_DATA13           0x29c 0x66c 0x000 0x1 0x0
-#define MX6Q_PAD_CSI0_DAT17__UART4_CTS_B          0x29c 0x66c 0x000 0x3 0x0
-#define MX6Q_PAD_CSI0_DAT17__UART4_RTS_B          0x29c 0x66c 0x934 0x3 0x1
-#define MX6Q_PAD_CSI0_DAT17__GPIO6_IO03           0x29c 0x66c 0x000 0x5 0x0
-#define MX6Q_PAD_CSI0_DAT17__ARM_TRACE14          0x29c 0x66c 0x000 0x7 0x0
-#define MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_DATA18     0x2a0 0x670 0x000 0x0 0x0
-#define MX6Q_PAD_CSI0_DAT18__EIM_DATA14           0x2a0 0x670 0x000 0x1 0x0
-#define MX6Q_PAD_CSI0_DAT18__UART5_RTS_B          0x2a0 0x670 0x93c 0x3 0x2
-#define MX6Q_PAD_CSI0_DAT18__UART5_CTS_B          0x2a0 0x670 0x000 0x3 0x0
-#define MX6Q_PAD_CSI0_DAT18__GPIO6_IO04           0x2a0 0x670 0x000 0x5 0x0
-#define MX6Q_PAD_CSI0_DAT18__ARM_TRACE15          0x2a0 0x670 0x000 0x7 0x0
-#define MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_DATA19     0x2a4 0x674 0x000 0x0 0x0
-#define MX6Q_PAD_CSI0_DAT19__EIM_DATA15           0x2a4 0x674 0x000 0x1 0x0
-#define MX6Q_PAD_CSI0_DAT19__UART5_CTS_B          0x2a4 0x674 0x000 0x3 0x0
-#define MX6Q_PAD_CSI0_DAT19__UART5_RTS_B          0x2a4 0x674 0x93c 0x3 0x3
-#define MX6Q_PAD_CSI0_DAT19__GPIO6_IO05           0x2a4 0x674 0x000 0x5 0x0
-#define MX6Q_PAD_SD3_DAT7__SD3_DATA7              0x2a8 0x690 0x000 0x0 0x0
-#define MX6Q_PAD_SD3_DAT7__UART1_TX_DATA          0x2a8 0x690 0x000 0x1 0x0
-#define MX6Q_PAD_SD3_DAT7__UART1_RX_DATA          0x2a8 0x690 0x920 0x1 0x2
-#define MX6Q_PAD_SD3_DAT7__GPIO6_IO17             0x2a8 0x690 0x000 0x5 0x0
-#define MX6Q_PAD_SD3_DAT6__SD3_DATA6              0x2ac 0x694 0x000 0x0 0x0
-#define MX6Q_PAD_SD3_DAT6__UART1_RX_DATA          0x2ac 0x694 0x920 0x1 0x3
-#define MX6Q_PAD_SD3_DAT6__UART1_TX_DATA          0x2ac 0x694 0x000 0x1 0x0
-#define MX6Q_PAD_SD3_DAT6__GPIO6_IO18             0x2ac 0x694 0x000 0x5 0x0
-#define MX6Q_PAD_SD3_DAT5__SD3_DATA5              0x2b0 0x698 0x000 0x0 0x0
-#define MX6Q_PAD_SD3_DAT5__UART2_TX_DATA          0x2b0 0x698 0x000 0x1 0x0
-#define MX6Q_PAD_SD3_DAT5__UART2_RX_DATA          0x2b0 0x698 0x928 0x1 0x4
-#define MX6Q_PAD_SD3_DAT5__GPIO7_IO00             0x2b0 0x698 0x000 0x5 0x0
-#define MX6Q_PAD_SD3_DAT4__SD3_DATA4              0x2b4 0x69c 0x000 0x0 0x0
-#define MX6Q_PAD_SD3_DAT4__UART2_RX_DATA          0x2b4 0x69c 0x928 0x1 0x5
-#define MX6Q_PAD_SD3_DAT4__UART2_TX_DATA          0x2b4 0x69c 0x000 0x1 0x0
-#define MX6Q_PAD_SD3_DAT4__GPIO7_IO01             0x2b4 0x69c 0x000 0x5 0x0
-#define MX6Q_PAD_SD3_CMD__SD3_CMD                 0x2b8 0x6a0 0x000 0x0 0x0
-#define MX6Q_PAD_SD3_CMD__UART2_CTS_B             0x2b8 0x6a0 0x000 0x1 0x0
-#define MX6Q_PAD_SD3_CMD__UART2_RTS_B             0x2b8 0x6a0 0x924 0x1 0x2
-#define MX6Q_PAD_SD3_CMD__FLEXCAN1_TX             0x2b8 0x6a0 0x000 0x2 0x0
-#define MX6Q_PAD_SD3_CMD__GPIO7_IO02              0x2b8 0x6a0 0x000 0x5 0x0
-#define MX6Q_PAD_SD3_CLK__SD3_CLK                 0x2bc 0x6a4 0x000 0x0 0x0
-#define MX6Q_PAD_SD3_CLK__UART2_RTS_B             0x2bc 0x6a4 0x924 0x1 0x3
-#define MX6Q_PAD_SD3_CLK__UART2_CTS_B             0x2bc 0x6a4 0x000 0x1 0x0
-#define MX6Q_PAD_SD3_CLK__FLEXCAN1_RX             0x2bc 0x6a4 0x7e4 0x2 0x2
-#define MX6Q_PAD_SD3_CLK__GPIO7_IO03              0x2bc 0x6a4 0x000 0x5 0x0
-#define MX6Q_PAD_SD3_DAT0__SD3_DATA0              0x2c0 0x6a8 0x000 0x0 0x0
-#define MX6Q_PAD_SD3_DAT0__UART1_CTS_B            0x2c0 0x6a8 0x000 0x1 0x0
-#define MX6Q_PAD_SD3_DAT0__UART1_RTS_B            0x2c0 0x6a8 0x91c 0x1 0x2
-#define MX6Q_PAD_SD3_DAT0__FLEXCAN2_TX            0x2c0 0x6a8 0x000 0x2 0x0
-#define MX6Q_PAD_SD3_DAT0__GPIO7_IO04             0x2c0 0x6a8 0x000 0x5 0x0
-#define MX6Q_PAD_SD3_DAT1__SD3_DATA1              0x2c4 0x6ac 0x000 0x0 0x0
-#define MX6Q_PAD_SD3_DAT1__UART1_RTS_B            0x2c4 0x6ac 0x91c 0x1 0x3
-#define MX6Q_PAD_SD3_DAT1__UART1_CTS_B            0x2c4 0x6ac 0x000 0x1 0x0
-#define MX6Q_PAD_SD3_DAT1__FLEXCAN2_RX            0x2c4 0x6ac 0x7e8 0x2 0x1
-#define MX6Q_PAD_SD3_DAT1__GPIO7_IO05             0x2c4 0x6ac 0x000 0x5 0x0
-#define MX6Q_PAD_SD3_DAT2__SD3_DATA2              0x2c8 0x6b0 0x000 0x0 0x0
-#define MX6Q_PAD_SD3_DAT2__GPIO7_IO06             0x2c8 0x6b0 0x000 0x5 0x0
-#define MX6Q_PAD_SD3_DAT3__SD3_DATA3              0x2cc 0x6b4 0x000 0x0 0x0
-#define MX6Q_PAD_SD3_DAT3__UART3_CTS_B            0x2cc 0x6b4 0x000 0x1 0x0
-#define MX6Q_PAD_SD3_DAT3__UART3_RTS_B            0x2cc 0x6b4 0x92c 0x1 0x4
-#define MX6Q_PAD_SD3_DAT3__GPIO7_IO07             0x2cc 0x6b4 0x000 0x5 0x0
-#define MX6Q_PAD_SD3_RST__SD3_RESET               0x2d0 0x6b8 0x000 0x0 0x0
-#define MX6Q_PAD_SD3_RST__UART3_RTS_B             0x2d0 0x6b8 0x92c 0x1 0x5
-#define MX6Q_PAD_SD3_RST__UART3_CTS_B             0x2d0 0x6b8 0x000 0x1 0x0
-#define MX6Q_PAD_SD3_RST__GPIO7_IO08              0x2d0 0x6b8 0x000 0x5 0x0
-#define MX6Q_PAD_NANDF_CLE__NAND_CLE              0x2d4 0x6bc 0x000 0x0 0x0
-#define MX6Q_PAD_NANDF_CLE__IPU2_SISG4            0x2d4 0x6bc 0x000 0x1 0x0
-#define MX6Q_PAD_NANDF_CLE__GPIO6_IO07            0x2d4 0x6bc 0x000 0x5 0x0
-#define MX6Q_PAD_NANDF_ALE__NAND_ALE              0x2d8 0x6c0 0x000 0x0 0x0
-#define MX6Q_PAD_NANDF_ALE__SD4_RESET             0x2d8 0x6c0 0x000 0x1 0x0
-#define MX6Q_PAD_NANDF_ALE__GPIO6_IO08            0x2d8 0x6c0 0x000 0x5 0x0
-#define MX6Q_PAD_NANDF_WP_B__NAND_WP_B            0x2dc 0x6c4 0x000 0x0 0x0
-#define MX6Q_PAD_NANDF_WP_B__IPU2_SISG5           0x2dc 0x6c4 0x000 0x1 0x0
-#define MX6Q_PAD_NANDF_WP_B__GPIO6_IO09           0x2dc 0x6c4 0x000 0x5 0x0
-#define MX6Q_PAD_NANDF_RB0__NAND_READY_B          0x2e0 0x6c8 0x000 0x0 0x0
-#define MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN01        0x2e0 0x6c8 0x000 0x1 0x0
-#define MX6Q_PAD_NANDF_RB0__GPIO6_IO10            0x2e0 0x6c8 0x000 0x5 0x0
-#define MX6Q_PAD_NANDF_CS0__NAND_CE0_B            0x2e4 0x6cc 0x000 0x0 0x0
-#define MX6Q_PAD_NANDF_CS0__GPIO6_IO11            0x2e4 0x6cc 0x000 0x5 0x0
-#define MX6Q_PAD_NANDF_CS1__NAND_CE1_B            0x2e8 0x6d0 0x000 0x0 0x0
-#define MX6Q_PAD_NANDF_CS1__SD4_VSELECT           0x2e8 0x6d0 0x000 0x1 0x0
-#define MX6Q_PAD_NANDF_CS1__SD3_VSELECT           0x2e8 0x6d0 0x000 0x2 0x0
-#define MX6Q_PAD_NANDF_CS1__GPIO6_IO14            0x2e8 0x6d0 0x000 0x5 0x0
-#define MX6Q_PAD_NANDF_CS2__NAND_CE2_B            0x2ec 0x6d4 0x000 0x0 0x0
-#define MX6Q_PAD_NANDF_CS2__IPU1_SISG0            0x2ec 0x6d4 0x000 0x1 0x0
-#define MX6Q_PAD_NANDF_CS2__ESAI_TX0              0x2ec 0x6d4 0x874 0x2 0x1
-#define MX6Q_PAD_NANDF_CS2__EIM_CRE               0x2ec 0x6d4 0x000 0x3 0x0
-#define MX6Q_PAD_NANDF_CS2__CCM_CLKO2             0x2ec 0x6d4 0x000 0x4 0x0
-#define MX6Q_PAD_NANDF_CS2__GPIO6_IO15            0x2ec 0x6d4 0x000 0x5 0x0
-#define MX6Q_PAD_NANDF_CS2__IPU2_SISG0            0x2ec 0x6d4 0x000 0x6 0x0
-#define MX6Q_PAD_NANDF_CS3__NAND_CE3_B            0x2f0 0x6d8 0x000 0x0 0x0
-#define MX6Q_PAD_NANDF_CS3__IPU1_SISG1            0x2f0 0x6d8 0x000 0x1 0x0
-#define MX6Q_PAD_NANDF_CS3__ESAI_TX1              0x2f0 0x6d8 0x878 0x2 0x1
-#define MX6Q_PAD_NANDF_CS3__EIM_ADDR26            0x2f0 0x6d8 0x000 0x3 0x0
-#define MX6Q_PAD_NANDF_CS3__GPIO6_IO16            0x2f0 0x6d8 0x000 0x5 0x0
-#define MX6Q_PAD_NANDF_CS3__IPU2_SISG1            0x2f0 0x6d8 0x000 0x6 0x0
-#define MX6Q_PAD_SD4_CMD__SD4_CMD                 0x2f4 0x6dc 0x000 0x0 0x0
-#define MX6Q_PAD_SD4_CMD__NAND_RE_B               0x2f4 0x6dc 0x000 0x1 0x0
-#define MX6Q_PAD_SD4_CMD__UART3_TX_DATA           0x2f4 0x6dc 0x000 0x2 0x0
-#define MX6Q_PAD_SD4_CMD__UART3_RX_DATA           0x2f4 0x6dc 0x930 0x2 0x2
-#define MX6Q_PAD_SD4_CMD__GPIO7_IO09              0x2f4 0x6dc 0x000 0x5 0x0
-#define MX6Q_PAD_SD4_CLK__SD4_CLK                 0x2f8 0x6e0 0x000 0x0 0x0
-#define MX6Q_PAD_SD4_CLK__NAND_WE_B               0x2f8 0x6e0 0x000 0x1 0x0
-#define MX6Q_PAD_SD4_CLK__UART3_RX_DATA           0x2f8 0x6e0 0x930 0x2 0x3
-#define MX6Q_PAD_SD4_CLK__UART3_TX_DATA           0x2f8 0x6e0 0x000 0x2 0x0
-#define MX6Q_PAD_SD4_CLK__GPIO7_IO10              0x2f8 0x6e0 0x000 0x5 0x0
-#define MX6Q_PAD_NANDF_D0__NAND_DATA00            0x2fc 0x6e4 0x000 0x0 0x0
-#define MX6Q_PAD_NANDF_D0__SD1_DATA4              0x2fc 0x6e4 0x000 0x1 0x0
-#define MX6Q_PAD_NANDF_D0__GPIO2_IO00             0x2fc 0x6e4 0x000 0x5 0x0
-#define MX6Q_PAD_NANDF_D1__NAND_DATA01            0x300 0x6e8 0x000 0x0 0x0
-#define MX6Q_PAD_NANDF_D1__SD1_DATA5              0x300 0x6e8 0x000 0x1 0x0
-#define MX6Q_PAD_NANDF_D1__GPIO2_IO01             0x300 0x6e8 0x000 0x5 0x0
-#define MX6Q_PAD_NANDF_D2__NAND_DATA02            0x304 0x6ec 0x000 0x0 0x0
-#define MX6Q_PAD_NANDF_D2__SD1_DATA6              0x304 0x6ec 0x000 0x1 0x0
-#define MX6Q_PAD_NANDF_D2__GPIO2_IO02             0x304 0x6ec 0x000 0x5 0x0
-#define MX6Q_PAD_NANDF_D3__NAND_DATA03            0x308 0x6f0 0x000 0x0 0x0
-#define MX6Q_PAD_NANDF_D3__SD1_DATA7              0x308 0x6f0 0x000 0x1 0x0
-#define MX6Q_PAD_NANDF_D3__GPIO2_IO03             0x308 0x6f0 0x000 0x5 0x0
-#define MX6Q_PAD_NANDF_D4__NAND_DATA04            0x30c 0x6f4 0x000 0x0 0x0
-#define MX6Q_PAD_NANDF_D4__SD2_DATA4              0x30c 0x6f4 0x000 0x1 0x0
-#define MX6Q_PAD_NANDF_D4__GPIO2_IO04             0x30c 0x6f4 0x000 0x5 0x0
-#define MX6Q_PAD_NANDF_D5__NAND_DATA05            0x310 0x6f8 0x000 0x0 0x0
-#define MX6Q_PAD_NANDF_D5__SD2_DATA5              0x310 0x6f8 0x000 0x1 0x0
-#define MX6Q_PAD_NANDF_D5__GPIO2_IO05             0x310 0x6f8 0x000 0x5 0x0
-#define MX6Q_PAD_NANDF_D6__NAND_DATA06            0x314 0x6fc 0x000 0x0 0x0
-#define MX6Q_PAD_NANDF_D6__SD2_DATA6              0x314 0x6fc 0x000 0x1 0x0
-#define MX6Q_PAD_NANDF_D6__GPIO2_IO06             0x314 0x6fc 0x000 0x5 0x0
-#define MX6Q_PAD_NANDF_D7__NAND_DATA07            0x318 0x700 0x000 0x0 0x0
-#define MX6Q_PAD_NANDF_D7__SD2_DATA7              0x318 0x700 0x000 0x1 0x0
-#define MX6Q_PAD_NANDF_D7__GPIO2_IO07             0x318 0x700 0x000 0x5 0x0
-#define MX6Q_PAD_SD4_DAT0__SD4_DATA0              0x31c 0x704 0x000 0x1 0x0
-#define MX6Q_PAD_SD4_DAT0__NAND_DQS               0x31c 0x704 0x000 0x2 0x0
-#define MX6Q_PAD_SD4_DAT0__GPIO2_IO08             0x31c 0x704 0x000 0x5 0x0
-#define MX6Q_PAD_SD4_DAT1__SD4_DATA1              0x320 0x708 0x000 0x1 0x0
-#define MX6Q_PAD_SD4_DAT1__PWM3_OUT               0x320 0x708 0x000 0x2 0x0
-#define MX6Q_PAD_SD4_DAT1__GPIO2_IO09             0x320 0x708 0x000 0x5 0x0
-#define MX6Q_PAD_SD4_DAT2__SD4_DATA2              0x324 0x70c 0x000 0x1 0x0
-#define MX6Q_PAD_SD4_DAT2__PWM4_OUT               0x324 0x70c 0x000 0x2 0x0
-#define MX6Q_PAD_SD4_DAT2__GPIO2_IO10             0x324 0x70c 0x000 0x5 0x0
-#define MX6Q_PAD_SD4_DAT3__SD4_DATA3              0x328 0x710 0x000 0x1 0x0
-#define MX6Q_PAD_SD4_DAT3__GPIO2_IO11             0x328 0x710 0x000 0x5 0x0
-#define MX6Q_PAD_SD4_DAT4__SD4_DATA4              0x32c 0x714 0x000 0x1 0x0
-#define MX6Q_PAD_SD4_DAT4__UART2_RX_DATA          0x32c 0x714 0x928 0x2 0x6
-#define MX6Q_PAD_SD4_DAT4__UART2_TX_DATA          0x32c 0x714 0x000 0x2 0x0
-#define MX6Q_PAD_SD4_DAT4__GPIO2_IO12             0x32c 0x714 0x000 0x5 0x0
-#define MX6Q_PAD_SD4_DAT5__SD4_DATA5              0x330 0x718 0x000 0x1 0x0
-#define MX6Q_PAD_SD4_DAT5__UART2_RTS_B            0x330 0x718 0x924 0x2 0x4
-#define MX6Q_PAD_SD4_DAT5__UART2_CTS_B            0x330 0x718 0x000 0x2 0x0
-#define MX6Q_PAD_SD4_DAT5__GPIO2_IO13             0x330 0x718 0x000 0x5 0x0
-#define MX6Q_PAD_SD4_DAT6__SD4_DATA6              0x334 0x71c 0x000 0x1 0x0
-#define MX6Q_PAD_SD4_DAT6__UART2_CTS_B            0x334 0x71c 0x000 0x2 0x0
-#define MX6Q_PAD_SD4_DAT6__UART2_RTS_B            0x334 0x71c 0x924 0x2 0x5
-#define MX6Q_PAD_SD4_DAT6__GPIO2_IO14             0x334 0x71c 0x000 0x5 0x0
-#define MX6Q_PAD_SD4_DAT7__SD4_DATA7              0x338 0x720 0x000 0x1 0x0
-#define MX6Q_PAD_SD4_DAT7__UART2_TX_DATA          0x338 0x720 0x000 0x2 0x0
-#define MX6Q_PAD_SD4_DAT7__UART2_RX_DATA          0x338 0x720 0x928 0x2 0x7
-#define MX6Q_PAD_SD4_DAT7__GPIO2_IO15             0x338 0x720 0x000 0x5 0x0
-#define MX6Q_PAD_SD1_DAT1__SD1_DATA1              0x33c 0x724 0x000 0x0 0x0
-#define MX6Q_PAD_SD1_DAT1__ECSPI5_SS0             0x33c 0x724 0x834 0x1 0x1
-#define MX6Q_PAD_SD1_DAT1__PWM3_OUT               0x33c 0x724 0x000 0x2 0x0
-#define MX6Q_PAD_SD1_DAT1__GPT_CAPTURE2           0x33c 0x724 0x000 0x3 0x0
-#define MX6Q_PAD_SD1_DAT1__GPIO1_IO17             0x33c 0x724 0x000 0x5 0x0
-#define MX6Q_PAD_SD1_DAT0__SD1_DATA0              0x340 0x728 0x000 0x0 0x0
-#define MX6Q_PAD_SD1_DAT0__ECSPI5_MISO            0x340 0x728 0x82c 0x1 0x1
-#define MX6Q_PAD_SD1_DAT0__GPT_CAPTURE1           0x340 0x728 0x000 0x3 0x0
-#define MX6Q_PAD_SD1_DAT0__GPIO1_IO16             0x340 0x728 0x000 0x5 0x0
-#define MX6Q_PAD_SD1_DAT3__SD1_DATA3              0x344 0x72c 0x000 0x0 0x0
-#define MX6Q_PAD_SD1_DAT3__ECSPI5_SS2             0x344 0x72c 0x000 0x1 0x0
-#define MX6Q_PAD_SD1_DAT3__GPT_COMPARE3           0x344 0x72c 0x000 0x2 0x0
-#define MX6Q_PAD_SD1_DAT3__PWM1_OUT               0x344 0x72c 0x000 0x3 0x0
-#define MX6Q_PAD_SD1_DAT3__WDOG2_B                0x344 0x72c 0x000 0x4 0x0
-#define MX6Q_PAD_SD1_DAT3__GPIO1_IO21             0x344 0x72c 0x000 0x5 0x0
-#define MX6Q_PAD_SD1_DAT3__WDOG2_RESET_B_DEB      0x344 0x72c 0x000 0x6 0x0
-#define MX6Q_PAD_SD1_CMD__SD1_CMD                 0x348 0x730 0x000 0x0 0x0
-#define MX6Q_PAD_SD1_CMD__ECSPI5_MOSI             0x348 0x730 0x830 0x1 0x0
-#define MX6Q_PAD_SD1_CMD__PWM4_OUT                0x348 0x730 0x000 0x2 0x0
-#define MX6Q_PAD_SD1_CMD__GPT_COMPARE1            0x348 0x730 0x000 0x3 0x0
-#define MX6Q_PAD_SD1_CMD__GPIO1_IO18              0x348 0x730 0x000 0x5 0x0
-#define MX6Q_PAD_SD1_DAT2__SD1_DATA2              0x34c 0x734 0x000 0x0 0x0
-#define MX6Q_PAD_SD1_DAT2__ECSPI5_SS1             0x34c 0x734 0x838 0x1 0x1
-#define MX6Q_PAD_SD1_DAT2__GPT_COMPARE2           0x34c 0x734 0x000 0x2 0x0
-#define MX6Q_PAD_SD1_DAT2__PWM2_OUT               0x34c 0x734 0x000 0x3 0x0
-#define MX6Q_PAD_SD1_DAT2__WDOG1_B                0x34c 0x734 0x000 0x4 0x0
-#define MX6Q_PAD_SD1_DAT2__GPIO1_IO19             0x34c 0x734 0x000 0x5 0x0
-#define MX6Q_PAD_SD1_DAT2__WDOG1_RESET_B_DEB      0x34c 0x734 0x000 0x6 0x0
-#define MX6Q_PAD_SD1_CLK__SD1_CLK                 0x350 0x738 0x000 0x0 0x0
-#define MX6Q_PAD_SD1_CLK__ECSPI5_SCLK             0x350 0x738 0x828 0x1 0x0
-#define MX6Q_PAD_SD1_CLK__GPT_CLKIN               0x350 0x738 0x000 0x3 0x0
-#define MX6Q_PAD_SD1_CLK__GPIO1_IO20              0x350 0x738 0x000 0x5 0x0
-#define MX6Q_PAD_SD2_CLK__SD2_CLK                 0x354 0x73c 0x000 0x0 0x0
-#define MX6Q_PAD_SD2_CLK__ECSPI5_SCLK             0x354 0x73c 0x828 0x1 0x1
-#define MX6Q_PAD_SD2_CLK__KEY_COL5                0x354 0x73c 0x8e8 0x2 0x3
-#define MX6Q_PAD_SD2_CLK__AUD4_RXFS               0x354 0x73c 0x7c0 0x3 0x1
-#define MX6Q_PAD_SD2_CLK__GPIO1_IO10              0x354 0x73c 0x000 0x5 0x0
-#define MX6Q_PAD_SD2_CMD__SD2_CMD                 0x358 0x740 0x000 0x0 0x0
-#define MX6Q_PAD_SD2_CMD__ECSPI5_MOSI             0x358 0x740 0x830 0x1 0x1
-#define MX6Q_PAD_SD2_CMD__KEY_ROW5                0x358 0x740 0x8f4 0x2 0x2
-#define MX6Q_PAD_SD2_CMD__AUD4_RXC                0x358 0x740 0x7bc 0x3 0x1
-#define MX6Q_PAD_SD2_CMD__GPIO1_IO11              0x358 0x740 0x000 0x5 0x0
-#define MX6Q_PAD_SD2_DAT3__SD2_DATA3              0x35c 0x744 0x000 0x0 0x0
-#define MX6Q_PAD_SD2_DAT3__ECSPI5_SS3             0x35c 0x744 0x000 0x1 0x0
-#define MX6Q_PAD_SD2_DAT3__KEY_COL6               0x35c 0x744 0x8ec 0x2 0x2
-#define MX6Q_PAD_SD2_DAT3__AUD4_TXC               0x35c 0x744 0x7c4 0x3 0x1
-#define MX6Q_PAD_SD2_DAT3__GPIO1_IO12             0x35c 0x744 0x000 0x5 0x0
+#define MX6QDL_PAD_SD2_DAT1__SD2_DATA1              0x04c 0x360 0x000 0x0 0x0
+#define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0             0x04c 0x360 0x834 0x1 0x0
+#define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B              0x04c 0x360 0x000 0x2 0x0
+#define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS              0x04c 0x360 0x7c8 0x3 0x0
+#define MX6QDL_PAD_SD2_DAT1__KEY_COL7               0x04c 0x360 0x8f0 0x4 0x0
+#define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14             0x04c 0x360 0x000 0x5 0x0
+#define MX6QDL_PAD_SD2_DAT2__SD2_DATA2              0x050 0x364 0x000 0x0 0x0
+#define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1             0x050 0x364 0x838 0x1 0x0
+#define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B              0x050 0x364 0x000 0x2 0x0
+#define MX6QDL_PAD_SD2_DAT2__AUD4_TXD               0x050 0x364 0x7b8 0x3 0x0
+#define MX6QDL_PAD_SD2_DAT2__KEY_ROW6               0x050 0x364 0x8f8 0x4 0x0
+#define MX6QDL_PAD_SD2_DAT2__GPIO1_IO13             0x050 0x364 0x000 0x5 0x0
+#define MX6QDL_PAD_SD2_DAT0__SD2_DATA0              0x054 0x368 0x000 0x0 0x0
+#define MX6QDL_PAD_SD2_DAT0__ECSPI5_MISO            0x054 0x368 0x82c 0x1 0x0
+#define MX6QDL_PAD_SD2_DAT0__AUD4_RXD               0x054 0x368 0x7b4 0x3 0x0
+#define MX6QDL_PAD_SD2_DAT0__KEY_ROW7               0x054 0x368 0x8fc 0x4 0x0
+#define MX6QDL_PAD_SD2_DAT0__GPIO1_IO15             0x054 0x368 0x000 0x5 0x0
+#define MX6QDL_PAD_SD2_DAT0__DCIC2_OUT              0x054 0x368 0x000 0x6 0x0
+#define MX6QDL_PAD_RGMII_TXC__USB_H2_DATA           0x058 0x36c 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_TXC__RGMII_TXC             0x058 0x36c 0x000 0x1 0x0
+#define MX6QDL_PAD_RGMII_TXC__SPDIF_EXT_CLK         0x058 0x36c 0x918 0x2 0x0
+#define MX6QDL_PAD_RGMII_TXC__GPIO6_IO19            0x058 0x36c 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M   0x058 0x36c 0x000 0x7 0x0
+#define MX6QDL_PAD_RGMII_TD0__HSI_TX_READY          0x05c 0x370 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_TD0__RGMII_TD0             0x05c 0x370 0x000 0x1 0x0
+#define MX6QDL_PAD_RGMII_TD0__GPIO6_IO20            0x05c 0x370 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_TD1__HSI_RX_FLAG           0x060 0x374 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_TD1__RGMII_TD1             0x060 0x374 0x000 0x1 0x0
+#define MX6QDL_PAD_RGMII_TD1__GPIO6_IO21            0x060 0x374 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_TD2__HSI_RX_DATA           0x064 0x378 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_TD2__RGMII_TD2             0x064 0x378 0x000 0x1 0x0
+#define MX6QDL_PAD_RGMII_TD2__GPIO6_IO22            0x064 0x378 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_TD3__HSI_RX_WAKE           0x068 0x37c 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_TD3__RGMII_TD3             0x068 0x37c 0x000 0x1 0x0
+#define MX6QDL_PAD_RGMII_TD3__GPIO6_IO23            0x068 0x37c 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA        0x06c 0x380 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL       0x06c 0x380 0x858 0x1 0x0
+#define MX6QDL_PAD_RGMII_RX_CTL__GPIO6_IO24         0x06c 0x380 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_RD0__HSI_RX_READY          0x070 0x384 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_RD0__RGMII_RD0             0x070 0x384 0x848 0x1 0x0
+#define MX6QDL_PAD_RGMII_RD0__GPIO6_IO25            0x070 0x384 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE      0x074 0x388 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL       0x074 0x388 0x000 0x1 0x0
+#define MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26         0x074 0x388 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_TX_CTL__ENET_REF_CLK       0x074 0x388 0x83c 0x7 0x0
+#define MX6QDL_PAD_RGMII_RD1__HSI_TX_FLAG           0x078 0x38c 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_RD1__RGMII_RD1             0x078 0x38c 0x84c 0x1 0x0
+#define MX6QDL_PAD_RGMII_RD1__GPIO6_IO27            0x078 0x38c 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_RD2__HSI_TX_DATA           0x07c 0x390 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_RD2__RGMII_RD2             0x07c 0x390 0x850 0x1 0x0
+#define MX6QDL_PAD_RGMII_RD2__GPIO6_IO28            0x07c 0x390 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_RD3__HSI_TX_WAKE           0x080 0x394 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_RD3__RGMII_RD3             0x080 0x394 0x854 0x1 0x0
+#define MX6QDL_PAD_RGMII_RD3__GPIO6_IO29            0x080 0x394 0x000 0x5 0x0
+#define MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE         0x084 0x398 0x000 0x0 0x0
+#define MX6QDL_PAD_RGMII_RXC__RGMII_RXC             0x084 0x398 0x844 0x1 0x0
+#define MX6QDL_PAD_RGMII_RXC__GPIO6_IO30            0x084 0x398 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A25__EIM_ADDR25              0x088 0x39c 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_A25__ECSPI4_SS1              0x088 0x39c 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_A25__ECSPI2_RDY              0x088 0x39c 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_A25__IPU1_DI1_PIN12          0x088 0x39c 0x000 0x3 0x0
+#define MX6QDL_PAD_EIM_A25__IPU1_DI0_D1_CS          0x088 0x39c 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_A25__GPIO5_IO02              0x088 0x39c 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE        0x088 0x39c 0x88c 0x6 0x0
+#define MX6QDL_PAD_EIM_EB2__EIM_EB2_B               0x08c 0x3a0 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_EB2__ECSPI1_SS0              0x08c 0x3a0 0x800 0x1 0x0
+#define MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19        0x08c 0x3a0 0x8d4 0x3 0x0
+#define MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL         0x08c 0x3a0 0x890 0x4 0x0
+#define MX6QDL_PAD_EIM_EB2__GPIO2_IO30              0x08c 0x3a0 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_EB2__I2C2_SCL                0x08c 0x3a0 0x8a0 0x6 0x0
+#define MX6QDL_PAD_EIM_EB2__SRC_BOOT_CFG30          0x08c 0x3a0 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_D16__EIM_DATA16              0x090 0x3a4 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D16__ECSPI1_SCLK             0x090 0x3a4 0x7f4 0x1 0x0
+#define MX6QDL_PAD_EIM_D16__IPU1_DI0_PIN05          0x090 0x3a4 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18        0x090 0x3a4 0x8d0 0x3 0x0
+#define MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA         0x090 0x3a4 0x894 0x4 0x0
+#define MX6QDL_PAD_EIM_D16__GPIO3_IO16              0x090 0x3a4 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D16__I2C2_SDA                0x090 0x3a4 0x8a4 0x6 0x0
+#define MX6QDL_PAD_EIM_D17__EIM_DATA17              0x094 0x3a8 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D17__ECSPI1_MISO             0x094 0x3a8 0x7f8 0x1 0x0
+#define MX6QDL_PAD_EIM_D17__IPU1_DI0_PIN06          0x094 0x3a8 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D17__IPU2_CSI1_PIXCLK        0x094 0x3a8 0x8e0 0x3 0x0
+#define MX6QDL_PAD_EIM_D17__DCIC1_OUT               0x094 0x3a8 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D17__GPIO3_IO17              0x094 0x3a8 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D17__I2C3_SCL                0x094 0x3a8 0x8a8 0x6 0x0
+#define MX6QDL_PAD_EIM_D18__EIM_DATA18              0x098 0x3ac 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D18__ECSPI1_MOSI             0x098 0x3ac 0x7fc 0x1 0x0
+#define MX6QDL_PAD_EIM_D18__IPU1_DI0_PIN07          0x098 0x3ac 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17        0x098 0x3ac 0x8cc 0x3 0x0
+#define MX6QDL_PAD_EIM_D18__IPU1_DI1_D0_CS          0x098 0x3ac 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D18__GPIO3_IO18              0x098 0x3ac 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D18__I2C3_SDA                0x098 0x3ac 0x8ac 0x6 0x0
+#define MX6QDL_PAD_EIM_D19__EIM_DATA19              0x09c 0x3b0 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D19__ECSPI1_SS1              0x09c 0x3b0 0x804 0x1 0x0
+#define MX6QDL_PAD_EIM_D19__IPU1_DI0_PIN08          0x09c 0x3b0 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16        0x09c 0x3b0 0x8c8 0x3 0x0
+#define MX6QDL_PAD_EIM_D19__UART1_CTS_B             0x09c 0x3b0 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D19__UART1_RTS_B             0x09c 0x3b0 0x91c 0x4 0x0
+#define MX6QDL_PAD_EIM_D19__GPIO3_IO19              0x09c 0x3b0 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D19__EPIT1_OUT               0x09c 0x3b0 0x000 0x6 0x0
+#define MX6QDL_PAD_EIM_D20__EIM_DATA20              0x0a0 0x3b4 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D20__ECSPI4_SS0              0x0a0 0x3b4 0x824 0x1 0x0
+#define MX6QDL_PAD_EIM_D20__IPU1_DI0_PIN16          0x0a0 0x3b4 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15        0x0a0 0x3b4 0x8c4 0x3 0x0
+#define MX6QDL_PAD_EIM_D20__UART1_RTS_B             0x0a0 0x3b4 0x91c 0x4 0x1
+#define MX6QDL_PAD_EIM_D20__UART1_CTS_B             0x0a0 0x3b4 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D20__GPIO3_IO20              0x0a0 0x3b4 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D20__EPIT2_OUT               0x0a0 0x3b4 0x000 0x6 0x0
+#define MX6QDL_PAD_EIM_D21__EIM_DATA21              0x0a4 0x3b8 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D21__ECSPI4_SCLK             0x0a4 0x3b8 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_D21__IPU1_DI0_PIN17          0x0a4 0x3b8 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D21__IPU2_CSI1_DATA11        0x0a4 0x3b8 0x8b4 0x3 0x0
+#define MX6QDL_PAD_EIM_D21__USB_OTG_OC              0x0a4 0x3b8 0x944 0x4 0x0
+#define MX6QDL_PAD_EIM_D21__GPIO3_IO21              0x0a4 0x3b8 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D21__I2C1_SCL                0x0a4 0x3b8 0x898 0x6 0x0
+#define MX6QDL_PAD_EIM_D21__SPDIF_IN                0x0a4 0x3b8 0x914 0x7 0x0
+#define MX6QDL_PAD_EIM_D22__EIM_DATA22              0x0a8 0x3bc 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D22__ECSPI4_MISO             0x0a8 0x3bc 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_D22__IPU1_DI0_PIN01          0x0a8 0x3bc 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D22__IPU2_CSI1_DATA10        0x0a8 0x3bc 0x8b0 0x3 0x0
+#define MX6QDL_PAD_EIM_D22__USB_OTG_PWR             0x0a8 0x3bc 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D22__GPIO3_IO22              0x0a8 0x3bc 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D22__SPDIF_OUT               0x0a8 0x3bc 0x000 0x6 0x0
+#define MX6QDL_PAD_EIM_D23__EIM_DATA23              0x0ac 0x3c0 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D23__IPU1_DI0_D0_CS          0x0ac 0x3c0 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_D23__UART3_CTS_B             0x0ac 0x3c0 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D23__UART3_RTS_B             0x0ac 0x3c0 0x92c 0x2 0x0
+#define MX6QDL_PAD_EIM_D23__UART1_DCD_B             0x0ac 0x3c0 0x000 0x3 0x0
+#define MX6QDL_PAD_EIM_D23__IPU2_CSI1_DATA_EN       0x0ac 0x3c0 0x8d8 0x4 0x0
+#define MX6QDL_PAD_EIM_D23__GPIO3_IO23              0x0ac 0x3c0 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN02          0x0ac 0x3c0 0x000 0x6 0x0
+#define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN14          0x0ac 0x3c0 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_EB3__EIM_EB3_B               0x0b0 0x3c4 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_EB3__ECSPI4_RDY              0x0b0 0x3c4 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_EB3__UART3_RTS_B             0x0b0 0x3c4 0x92c 0x2 0x1
+#define MX6QDL_PAD_EIM_EB3__UART3_CTS_B             0x0b0 0x3c4 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_EB3__UART1_RI_B              0x0b0 0x3c4 0x000 0x3 0x0
+#define MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC         0x0b0 0x3c4 0x8dc 0x4 0x0
+#define MX6QDL_PAD_EIM_EB3__GPIO2_IO31              0x0b0 0x3c4 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_EB3__IPU1_DI1_PIN03          0x0b0 0x3c4 0x000 0x6 0x0
+#define MX6QDL_PAD_EIM_EB3__SRC_BOOT_CFG31          0x0b0 0x3c4 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_D24__EIM_DATA24              0x0b4 0x3c8 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D24__ECSPI4_SS2              0x0b4 0x3c8 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_D24__UART3_TX_DATA           0x0b4 0x3c8 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D24__UART3_RX_DATA           0x0b4 0x3c8 0x930 0x2 0x0
+#define MX6QDL_PAD_EIM_D24__ECSPI1_SS2              0x0b4 0x3c8 0x808 0x3 0x0
+#define MX6QDL_PAD_EIM_D24__ECSPI2_SS2              0x0b4 0x3c8 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D24__GPIO3_IO24              0x0b4 0x3c8 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D24__AUD5_RXFS               0x0b4 0x3c8 0x7d8 0x6 0x0
+#define MX6QDL_PAD_EIM_D24__UART1_DTR_B             0x0b4 0x3c8 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_D25__EIM_DATA25              0x0b8 0x3cc 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D25__ECSPI4_SS3              0x0b8 0x3cc 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_D25__UART3_RX_DATA           0x0b8 0x3cc 0x930 0x2 0x1
+#define MX6QDL_PAD_EIM_D25__UART3_TX_DATA           0x0b8 0x3cc 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D25__ECSPI1_SS3              0x0b8 0x3cc 0x80c 0x3 0x0
+#define MX6QDL_PAD_EIM_D25__ECSPI2_SS3              0x0b8 0x3cc 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D25__GPIO3_IO25              0x0b8 0x3cc 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D25__AUD5_RXC                0x0b8 0x3cc 0x7d4 0x6 0x0
+#define MX6QDL_PAD_EIM_D25__UART1_DSR_B             0x0b8 0x3cc 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_D26__EIM_DATA26              0x0bc 0x3d0 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D26__IPU1_DI1_PIN11          0x0bc 0x3d0 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_D26__IPU1_CSI0_DATA01        0x0bc 0x3d0 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14        0x0bc 0x3d0 0x8c0 0x3 0x0
+#define MX6QDL_PAD_EIM_D26__UART2_TX_DATA           0x0bc 0x3d0 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D26__UART2_RX_DATA           0x0bc 0x3d0 0x928 0x4 0x0
+#define MX6QDL_PAD_EIM_D26__GPIO3_IO26              0x0bc 0x3d0 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D26__IPU1_SISG2              0x0bc 0x3d0 0x000 0x6 0x0
+#define MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22       0x0bc 0x3d0 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_D27__EIM_DATA27              0x0c0 0x3d4 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D27__IPU1_DI1_PIN13          0x0c0 0x3d4 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_D27__IPU1_CSI0_DATA00        0x0c0 0x3d4 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13        0x0c0 0x3d4 0x8bc 0x3 0x0
+#define MX6QDL_PAD_EIM_D27__UART2_RX_DATA           0x0c0 0x3d4 0x928 0x4 0x1
+#define MX6QDL_PAD_EIM_D27__UART2_TX_DATA           0x0c0 0x3d4 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D27__GPIO3_IO27              0x0c0 0x3d4 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D27__IPU1_SISG3              0x0c0 0x3d4 0x000 0x6 0x0
+#define MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23       0x0c0 0x3d4 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_D28__EIM_DATA28              0x0c4 0x3d8 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D28__I2C1_SDA                0x0c4 0x3d8 0x89c 0x1 0x0
+#define MX6QDL_PAD_EIM_D28__ECSPI4_MOSI             0x0c4 0x3d8 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D28__IPU2_CSI1_DATA12        0x0c4 0x3d8 0x8b8 0x3 0x0
+#define MX6QDL_PAD_EIM_D28__UART2_CTS_B             0x0c4 0x3d8 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D28__UART2_RTS_B             0x0c4 0x3d8 0x924 0x4 0x0
+#define MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B         0x0c4 0x3d8 0x924 0x4 0x0
+#define MX6QDL_PAD_EIM_D28__UART2_DTE_RTS_B         0x0c4 0x3d8 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D28__GPIO3_IO28              0x0c4 0x3d8 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D28__IPU1_EXT_TRIG           0x0c4 0x3d8 0x000 0x6 0x0
+#define MX6QDL_PAD_EIM_D28__IPU1_DI0_PIN13          0x0c4 0x3d8 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_D29__EIM_DATA29              0x0c8 0x3dc 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D29__IPU1_DI1_PIN15          0x0c8 0x3dc 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_D29__ECSPI4_SS0              0x0c8 0x3dc 0x824 0x2 0x1
+#define MX6QDL_PAD_EIM_D29__UART2_RTS_B             0x0c8 0x3dc 0x924 0x4 0x1
+#define MX6QDL_PAD_EIM_D29__UART2_CTS_B             0x0c8 0x3dc 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B         0x0c4 0x3dc 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D29__UART2_DTE_CTS_B         0x0c4 0x3dc 0x924 0x4 0x1
+#define MX6QDL_PAD_EIM_D29__GPIO3_IO29              0x0c8 0x3dc 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC         0x0c8 0x3dc 0x8e4 0x6 0x0
+#define MX6QDL_PAD_EIM_D29__IPU1_DI0_PIN14          0x0c8 0x3dc 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_D30__EIM_DATA30              0x0cc 0x3e0 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21       0x0cc 0x3e0 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_D30__IPU1_DI0_PIN11          0x0cc 0x3e0 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D30__IPU1_CSI0_DATA03        0x0cc 0x3e0 0x000 0x3 0x0
+#define MX6QDL_PAD_EIM_D30__UART3_CTS_B             0x0cc 0x3e0 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D30__UART3_RTS_B             0x0cc 0x3e0 0x92c 0x4 0x2
+#define MX6QDL_PAD_EIM_D30__GPIO3_IO30              0x0cc 0x3e0 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D30__USB_H1_OC               0x0cc 0x3e0 0x948 0x6 0x0
+#define MX6QDL_PAD_EIM_D31__EIM_DATA31              0x0d0 0x3e4 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20       0x0d0 0x3e4 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_D31__IPU1_DI0_PIN12          0x0d0 0x3e4 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_D31__IPU1_CSI0_DATA02        0x0d0 0x3e4 0x000 0x3 0x0
+#define MX6QDL_PAD_EIM_D31__UART3_RTS_B             0x0d0 0x3e4 0x92c 0x4 0x3
+#define MX6QDL_PAD_EIM_D31__UART3_CTS_B             0x0d0 0x3e4 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_D31__GPIO3_IO31              0x0d0 0x3e4 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_D31__USB_H1_PWR              0x0d0 0x3e4 0x000 0x6 0x0
+#define MX6QDL_PAD_EIM_A24__EIM_ADDR24              0x0d4 0x3e8 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19       0x0d4 0x3e8 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_A24__IPU2_CSI1_DATA19        0x0d4 0x3e8 0x8d4 0x2 0x1
+#define MX6QDL_PAD_EIM_A24__IPU2_SISG2              0x0d4 0x3e8 0x000 0x3 0x0
+#define MX6QDL_PAD_EIM_A24__IPU1_SISG2              0x0d4 0x3e8 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_A24__GPIO5_IO04              0x0d4 0x3e8 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A24__SRC_BOOT_CFG24          0x0d4 0x3e8 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_A23__EIM_ADDR23              0x0d8 0x3ec 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18       0x0d8 0x3ec 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_A23__IPU2_CSI1_DATA18        0x0d8 0x3ec 0x8d0 0x2 0x1
+#define MX6QDL_PAD_EIM_A23__IPU2_SISG3              0x0d8 0x3ec 0x000 0x3 0x0
+#define MX6QDL_PAD_EIM_A23__IPU1_SISG3              0x0d8 0x3ec 0x000 0x4 0x0
+#define MX6QDL_PAD_EIM_A23__GPIO6_IO06              0x0d8 0x3ec 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A23__SRC_BOOT_CFG23          0x0d8 0x3ec 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_A22__EIM_ADDR22              0x0dc 0x3f0 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17       0x0dc 0x3f0 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_A22__IPU2_CSI1_DATA17        0x0dc 0x3f0 0x8cc 0x2 0x1
+#define MX6QDL_PAD_EIM_A22__GPIO2_IO16              0x0dc 0x3f0 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A22__SRC_BOOT_CFG22          0x0dc 0x3f0 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_A21__EIM_ADDR21              0x0e0 0x3f4 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16       0x0e0 0x3f4 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_A21__IPU2_CSI1_DATA16        0x0e0 0x3f4 0x8c8 0x2 0x1
+#define MX6QDL_PAD_EIM_A21__GPIO2_IO17              0x0e0 0x3f4 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A21__SRC_BOOT_CFG21          0x0e0 0x3f4 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_A20__EIM_ADDR20              0x0e4 0x3f8 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15       0x0e4 0x3f8 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_A20__IPU2_CSI1_DATA15        0x0e4 0x3f8 0x8c4 0x2 0x1
+#define MX6QDL_PAD_EIM_A20__GPIO2_IO18              0x0e4 0x3f8 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A20__SRC_BOOT_CFG20          0x0e4 0x3f8 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_A19__EIM_ADDR19              0x0e8 0x3fc 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14       0x0e8 0x3fc 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_A19__IPU2_CSI1_DATA14        0x0e8 0x3fc 0x8c0 0x2 0x1
+#define MX6QDL_PAD_EIM_A19__GPIO2_IO19              0x0e8 0x3fc 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A19__SRC_BOOT_CFG19          0x0e8 0x3fc 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_A18__EIM_ADDR18              0x0ec 0x400 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13       0x0ec 0x400 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_A18__IPU2_CSI1_DATA13        0x0ec 0x400 0x8bc 0x2 0x1
+#define MX6QDL_PAD_EIM_A18__GPIO2_IO20              0x0ec 0x400 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A18__SRC_BOOT_CFG18          0x0ec 0x400 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_A17__EIM_ADDR17              0x0f0 0x404 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12       0x0f0 0x404 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12        0x0f0 0x404 0x8b8 0x2 0x1
+#define MX6QDL_PAD_EIM_A17__GPIO2_IO21              0x0f0 0x404 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A17__SRC_BOOT_CFG17          0x0f0 0x404 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_A16__EIM_ADDR16              0x0f4 0x408 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK       0x0f4 0x408 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK        0x0f4 0x408 0x8e0 0x2 0x1
+#define MX6QDL_PAD_EIM_A16__GPIO2_IO22              0x0f4 0x408 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_A16__SRC_BOOT_CFG16          0x0f4 0x408 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_CS0__EIM_CS0_B               0x0f8 0x40c 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_CS0__IPU1_DI1_PIN05          0x0f8 0x40c 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK             0x0f8 0x40c 0x810 0x2 0x0
+#define MX6QDL_PAD_EIM_CS0__GPIO2_IO23              0x0f8 0x40c 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_CS1__EIM_CS1_B               0x0fc 0x410 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_CS1__IPU1_DI1_PIN06          0x0fc 0x410 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI             0x0fc 0x410 0x818 0x2 0x0
+#define MX6QDL_PAD_EIM_CS1__GPIO2_IO24              0x0fc 0x410 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_OE__EIM_OE_B                 0x100 0x414 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_OE__IPU1_DI1_PIN07           0x100 0x414 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_OE__ECSPI2_MISO              0x100 0x414 0x814 0x2 0x0
+#define MX6QDL_PAD_EIM_OE__GPIO2_IO25               0x100 0x414 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_RW__EIM_RW                   0x104 0x418 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_RW__IPU1_DI1_PIN08           0x104 0x418 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_RW__ECSPI2_SS0               0x104 0x418 0x81c 0x2 0x0
+#define MX6QDL_PAD_EIM_RW__GPIO2_IO26               0x104 0x418 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_RW__SRC_BOOT_CFG29           0x104 0x418 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_LBA__EIM_LBA_B               0x108 0x41c 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_LBA__IPU1_DI1_PIN17          0x108 0x41c 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_LBA__ECSPI2_SS1              0x108 0x41c 0x820 0x2 0x0
+#define MX6QDL_PAD_EIM_LBA__GPIO2_IO27              0x108 0x41c 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_LBA__SRC_BOOT_CFG26          0x108 0x41c 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_EB0__EIM_EB0_B               0x10c 0x420 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11       0x10c 0x420 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_EB0__IPU2_CSI1_DATA11        0x10c 0x420 0x8b4 0x2 0x1
+#define MX6QDL_PAD_EIM_EB0__CCM_PMIC_READY          0x10c 0x420 0x7f0 0x4 0x0
+#define MX6QDL_PAD_EIM_EB0__GPIO2_IO28              0x10c 0x420 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_EB0__SRC_BOOT_CFG27          0x10c 0x420 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_EB1__EIM_EB1_B               0x110 0x424 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10       0x110 0x424 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_EB1__IPU2_CSI1_DATA10        0x110 0x424 0x8b0 0x2 0x1
+#define MX6QDL_PAD_EIM_EB1__GPIO2_IO29              0x110 0x424 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_EB1__SRC_BOOT_CFG28          0x110 0x424 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA0__EIM_AD00                0x114 0x428 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09       0x114 0x428 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA0__IPU2_CSI1_DATA09        0x114 0x428 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA0__GPIO3_IO00              0x114 0x428 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA0__SRC_BOOT_CFG00          0x114 0x428 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA1__EIM_AD01                0x118 0x42c 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08       0x118 0x42c 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA1__IPU2_CSI1_DATA08        0x118 0x42c 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA1__GPIO3_IO01              0x118 0x42c 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA1__SRC_BOOT_CFG01          0x118 0x42c 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA2__EIM_AD02                0x11c 0x430 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07       0x11c 0x430 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA2__IPU2_CSI1_DATA07        0x11c 0x430 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA2__GPIO3_IO02              0x11c 0x430 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA2__SRC_BOOT_CFG02          0x11c 0x430 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA3__EIM_AD03                0x120 0x434 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06       0x120 0x434 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA3__IPU2_CSI1_DATA06        0x120 0x434 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA3__GPIO3_IO03              0x120 0x434 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA3__SRC_BOOT_CFG03          0x120 0x434 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA4__EIM_AD04                0x124 0x438 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05       0x124 0x438 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA4__IPU2_CSI1_DATA05        0x124 0x438 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA4__GPIO3_IO04              0x124 0x438 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA4__SRC_BOOT_CFG04          0x124 0x438 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA5__EIM_AD05                0x128 0x43c 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04       0x128 0x43c 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA5__IPU2_CSI1_DATA04        0x128 0x43c 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA5__GPIO3_IO05              0x128 0x43c 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA5__SRC_BOOT_CFG05          0x128 0x43c 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA6__EIM_AD06                0x12c 0x440 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03       0x12c 0x440 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA6__IPU2_CSI1_DATA03        0x12c 0x440 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA6__GPIO3_IO06              0x12c 0x440 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA6__SRC_BOOT_CFG06          0x12c 0x440 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA7__EIM_AD07                0x130 0x444 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02       0x130 0x444 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA7__IPU2_CSI1_DATA02        0x130 0x444 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA7__GPIO3_IO07              0x130 0x444 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA7__SRC_BOOT_CFG07          0x130 0x444 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA8__EIM_AD08                0x134 0x448 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01       0x134 0x448 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA8__IPU2_CSI1_DATA01        0x134 0x448 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA8__GPIO3_IO08              0x134 0x448 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA8__SRC_BOOT_CFG08          0x134 0x448 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA9__EIM_AD09                0x138 0x44c 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00       0x138 0x44c 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA9__IPU2_CSI1_DATA00        0x138 0x44c 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA9__GPIO3_IO09              0x138 0x44c 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA9__SRC_BOOT_CFG09          0x138 0x44c 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA10__EIM_AD10               0x13c 0x450 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15         0x13c 0x450 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA10__IPU2_CSI1_DATA_EN      0x13c 0x450 0x8d8 0x2 0x1
+#define MX6QDL_PAD_EIM_DA10__GPIO3_IO10             0x13c 0x450 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA10__SRC_BOOT_CFG10         0x13c 0x450 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA11__EIM_AD11               0x140 0x454 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02         0x140 0x454 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA11__IPU2_CSI1_HSYNC        0x140 0x454 0x8dc 0x2 0x1
+#define MX6QDL_PAD_EIM_DA11__GPIO3_IO11             0x140 0x454 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA11__SRC_BOOT_CFG11         0x140 0x454 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA12__EIM_AD12               0x144 0x458 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03         0x144 0x458 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA12__IPU2_CSI1_VSYNC        0x144 0x458 0x8e4 0x2 0x1
+#define MX6QDL_PAD_EIM_DA12__GPIO3_IO12             0x144 0x458 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA12__SRC_BOOT_CFG12         0x144 0x458 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA13__EIM_AD13               0x148 0x45c 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA13__IPU1_DI1_D0_CS         0x148 0x45c 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA13__GPIO3_IO13             0x148 0x45c 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA13__SRC_BOOT_CFG13         0x148 0x45c 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA14__EIM_AD14               0x14c 0x460 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA14__IPU1_DI1_D1_CS         0x14c 0x460 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA14__GPIO3_IO14             0x14c 0x460 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA14__SRC_BOOT_CFG14         0x14c 0x460 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_DA15__EIM_AD15               0x150 0x464 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN01         0x150 0x464 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN04         0x150 0x464 0x000 0x2 0x0
+#define MX6QDL_PAD_EIM_DA15__GPIO3_IO15             0x150 0x464 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_DA15__SRC_BOOT_CFG15         0x150 0x464 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B             0x154 0x468 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_WAIT__EIM_DTACK_B            0x154 0x468 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_WAIT__GPIO5_IO00             0x154 0x468 0x000 0x5 0x0
+#define MX6QDL_PAD_EIM_WAIT__SRC_BOOT_CFG25         0x154 0x468 0x000 0x7 0x0
+#define MX6QDL_PAD_EIM_BCLK__EIM_BCLK               0x158 0x46c 0x000 0x0 0x0
+#define MX6QDL_PAD_EIM_BCLK__IPU1_DI1_PIN16         0x158 0x46c 0x000 0x1 0x0
+#define MX6QDL_PAD_EIM_BCLK__GPIO6_IO31             0x158 0x46c 0x000 0x5 0x0
+#define MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK  0x15c 0x470 0x000 0x0 0x0
+#define MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK  0x15c 0x470 0x000 0x1 0x0
+#define MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16         0x15c 0x470 0x000 0x5 0x0
+#define MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15        0x160 0x474 0x000 0x0 0x0
+#define MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15        0x160 0x474 0x000 0x1 0x0
+#define MX6QDL_PAD_DI0_PIN15__AUD6_TXC              0x160 0x474 0x000 0x2 0x0
+#define MX6QDL_PAD_DI0_PIN15__GPIO4_IO17            0x160 0x474 0x000 0x5 0x0
+#define MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02         0x164 0x478 0x000 0x0 0x0
+#define MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02         0x164 0x478 0x000 0x1 0x0
+#define MX6QDL_PAD_DI0_PIN2__AUD6_TXD               0x164 0x478 0x000 0x2 0x0
+#define MX6QDL_PAD_DI0_PIN2__GPIO4_IO18             0x164 0x478 0x000 0x5 0x0
+#define MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03         0x168 0x47c 0x000 0x0 0x0
+#define MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03         0x168 0x47c 0x000 0x1 0x0
+#define MX6QDL_PAD_DI0_PIN3__AUD6_TXFS              0x168 0x47c 0x000 0x2 0x0
+#define MX6QDL_PAD_DI0_PIN3__GPIO4_IO19             0x168 0x47c 0x000 0x5 0x0
+#define MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04         0x16c 0x480 0x000 0x0 0x0
+#define MX6QDL_PAD_DI0_PIN4__IPU2_DI0_PIN04         0x16c 0x480 0x000 0x1 0x0
+#define MX6QDL_PAD_DI0_PIN4__AUD6_RXD               0x16c 0x480 0x000 0x2 0x0
+#define MX6QDL_PAD_DI0_PIN4__SD1_WP                 0x16c 0x480 0x94c 0x3 0x0
+#define MX6QDL_PAD_DI0_PIN4__GPIO4_IO20             0x16c 0x480 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00    0x170 0x484 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00    0x170 0x484 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK          0x170 0x484 0x000 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21           0x170 0x484 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01    0x174 0x488 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01    0x174 0x488 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI          0x174 0x488 0x000 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22           0x174 0x488 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02    0x178 0x48c 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02    0x178 0x48c 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO          0x178 0x48c 0x000 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT2__GPIO4_IO23           0x178 0x48c 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03    0x17c 0x490 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03    0x17c 0x490 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT3__ECSPI3_SS0           0x17c 0x490 0x000 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24           0x17c 0x490 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04    0x180 0x494 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04    0x180 0x494 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT4__ECSPI3_SS1           0x180 0x494 0x000 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25           0x180 0x494 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05    0x184 0x498 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05    0x184 0x498 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT5__ECSPI3_SS2           0x184 0x498 0x000 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT5__AUD6_RXFS            0x184 0x498 0x000 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26           0x184 0x498 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06    0x188 0x49c 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06    0x188 0x49c 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT6__ECSPI3_SS3           0x188 0x49c 0x000 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT6__AUD6_RXC             0x188 0x49c 0x000 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27           0x188 0x49c 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07    0x18c 0x4a0 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07    0x18c 0x4a0 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT7__ECSPI3_RDY           0x18c 0x4a0 0x000 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28           0x18c 0x4a0 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08    0x190 0x4a4 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08    0x190 0x4a4 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT8__PWM1_OUT             0x190 0x4a4 0x000 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT8__WDOG1_B              0x190 0x4a4 0x000 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29           0x190 0x4a4 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09    0x194 0x4a8 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09    0x194 0x4a8 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT9__PWM2_OUT             0x194 0x4a8 0x000 0x2 0x0
+#define MX6QDL_PAD_DISP0_DAT9__WDOG2_B              0x194 0x4a8 0x000 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30           0x194 0x4a8 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10   0x198 0x4ac 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10   0x198 0x4ac 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31          0x198 0x4ac 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11   0x19c 0x4b0 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11   0x19c 0x4b0 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05          0x19c 0x4b0 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12   0x1a0 0x4b4 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12   0x1a0 0x4b4 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06          0x1a0 0x4b4 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13   0x1a4 0x4b8 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13   0x1a4 0x4b8 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT13__AUD5_RXFS           0x1a4 0x4b8 0x7d8 0x3 0x1
+#define MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07          0x1a4 0x4b8 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14   0x1a8 0x4bc 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14   0x1a8 0x4bc 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT14__AUD5_RXC            0x1a8 0x4bc 0x7d4 0x3 0x1
+#define MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08          0x1a8 0x4bc 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15   0x1ac 0x4c0 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15   0x1ac 0x4c0 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT15__ECSPI1_SS1          0x1ac 0x4c0 0x804 0x2 0x1
+#define MX6QDL_PAD_DISP0_DAT15__ECSPI2_SS1          0x1ac 0x4c0 0x820 0x3 0x1
+#define MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09          0x1ac 0x4c0 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16   0x1b0 0x4c4 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT16__IPU2_DISP0_DATA16   0x1b0 0x4c4 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI         0x1b0 0x4c4 0x818 0x2 0x1
+#define MX6QDL_PAD_DISP0_DAT16__AUD5_TXC            0x1b0 0x4c4 0x7dc 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT16__SDMA_EXT_EVENT0     0x1b0 0x4c4 0x90c 0x4 0x0
+#define MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10          0x1b0 0x4c4 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17   0x1b4 0x4c8 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT17__IPU2_DISP0_DATA17   0x1b4 0x4c8 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO         0x1b4 0x4c8 0x814 0x2 0x1
+#define MX6QDL_PAD_DISP0_DAT17__AUD5_TXD            0x1b4 0x4c8 0x7d0 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT17__SDMA_EXT_EVENT1     0x1b4 0x4c8 0x910 0x4 0x0
+#define MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11          0x1b4 0x4c8 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18   0x1b8 0x4cc 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT18__IPU2_DISP0_DATA18   0x1b8 0x4cc 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT18__ECSPI2_SS0          0x1b8 0x4cc 0x81c 0x2 0x1
+#define MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS           0x1b8 0x4cc 0x7e0 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT18__AUD4_RXFS           0x1b8 0x4cc 0x7c0 0x4 0x0
+#define MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12          0x1b8 0x4cc 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT18__EIM_CS2_B           0x1b8 0x4cc 0x000 0x7 0x0
+#define MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19   0x1bc 0x4d0 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT19__IPU2_DISP0_DATA19   0x1bc 0x4d0 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK         0x1bc 0x4d0 0x810 0x2 0x1
+#define MX6QDL_PAD_DISP0_DAT19__AUD5_RXD            0x1bc 0x4d0 0x7cc 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT19__AUD4_RXC            0x1bc 0x4d0 0x7bc 0x4 0x0
+#define MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13          0x1bc 0x4d0 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT19__EIM_CS3_B           0x1bc 0x4d0 0x000 0x7 0x0
+#define MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20   0x1c0 0x4d4 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT20__IPU2_DISP0_DATA20   0x1c0 0x4d4 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT20__ECSPI1_SCLK         0x1c0 0x4d4 0x7f4 0x2 0x1
+#define MX6QDL_PAD_DISP0_DAT20__AUD4_TXC            0x1c0 0x4d4 0x7c4 0x3 0x0
+#define MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14          0x1c0 0x4d4 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21   0x1c4 0x4d8 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT21__IPU2_DISP0_DATA21   0x1c4 0x4d8 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT21__ECSPI1_MOSI         0x1c4 0x4d8 0x7fc 0x2 0x1
+#define MX6QDL_PAD_DISP0_DAT21__AUD4_TXD            0x1c4 0x4d8 0x7b8 0x3 0x1
+#define MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15          0x1c4 0x4d8 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22   0x1c8 0x4dc 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT22__IPU2_DISP0_DATA22   0x1c8 0x4dc 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT22__ECSPI1_MISO         0x1c8 0x4dc 0x7f8 0x2 0x1
+#define MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS           0x1c8 0x4dc 0x7c8 0x3 0x1
+#define MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16          0x1c8 0x4dc 0x000 0x5 0x0
+#define MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23   0x1cc 0x4e0 0x000 0x0 0x0
+#define MX6QDL_PAD_DISP0_DAT23__IPU2_DISP0_DATA23   0x1cc 0x4e0 0x000 0x1 0x0
+#define MX6QDL_PAD_DISP0_DAT23__ECSPI1_SS0          0x1cc 0x4e0 0x800 0x2 0x1
+#define MX6QDL_PAD_DISP0_DAT23__AUD4_RXD            0x1cc 0x4e0 0x7b4 0x3 0x1
+#define MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17          0x1cc 0x4e0 0x000 0x5 0x0
+#define MX6QDL_PAD_ENET_MDIO__ENET_MDIO             0x1d0 0x4e4 0x840 0x1 0x0
+#define MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK           0x1d0 0x4e4 0x86c 0x2 0x0
+#define MX6QDL_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT  0x1d0 0x4e4 0x000 0x4 0x0
+#define MX6QDL_PAD_ENET_MDIO__GPIO1_IO22            0x1d0 0x4e4 0x000 0x5 0x0
+#define MX6QDL_PAD_ENET_MDIO__SPDIF_LOCK            0x1d0 0x4e4 0x000 0x6 0x0
+#define MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK        0x1d4 0x4e8 0x000 0x1 0x0
+#define MX6QDL_PAD_ENET_REF_CLK__ESAI_RX_FS         0x1d4 0x4e8 0x85c 0x2 0x0
+#define MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23         0x1d4 0x4e8 0x000 0x5 0x0
+#define MX6QDL_PAD_ENET_REF_CLK__SPDIF_SR_CLK       0x1d4 0x4e8 0x000 0x6 0x0
+#define MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID           0x1d8 0x4ec 0x000 0x0 0x0
+#define MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER           0x1d8 0x4ec 0x000 0x1 0x0
+#define MX6QDL_PAD_ENET_RX_ER__ESAI_RX_HF_CLK       0x1d8 0x4ec 0x864 0x2 0x0
+#define MX6QDL_PAD_ENET_RX_ER__SPDIF_IN             0x1d8 0x4ec 0x914 0x3 0x1
+#define MX6QDL_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT 0x1d8 0x4ec 0x000 0x4 0x0
+#define MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24           0x1d8 0x4ec 0x000 0x5 0x0
+#define MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN          0x1dc 0x4f0 0x858 0x1 0x1
+#define MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK         0x1dc 0x4f0 0x870 0x2 0x0
+#define MX6QDL_PAD_ENET_CRS_DV__SPDIF_EXT_CLK       0x1dc 0x4f0 0x918 0x3 0x1
+#define MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25          0x1dc 0x4f0 0x000 0x5 0x0
+#define MX6QDL_PAD_ENET_RXD1__MLB_SIG               0x1e0 0x4f4 0x908 0x0 0x0
+#define MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1         0x1e0 0x4f4 0x84c 0x1 0x1
+#define MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS            0x1e0 0x4f4 0x860 0x2 0x0
+#define MX6QDL_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT  0x1e0 0x4f4 0x000 0x4 0x0
+#define MX6QDL_PAD_ENET_RXD1__GPIO1_IO26            0x1e0 0x4f4 0x000 0x5 0x0
+#define MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0         0x1e4 0x4f8 0x848 0x1 0x1
+#define MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK        0x1e4 0x4f8 0x868 0x2 0x0
+#define MX6QDL_PAD_ENET_RXD0__SPDIF_OUT             0x1e4 0x4f8 0x000 0x3 0x0
+#define MX6QDL_PAD_ENET_RXD0__GPIO1_IO27            0x1e4 0x4f8 0x000 0x5 0x0
+#define MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN           0x1e8 0x4fc 0x000 0x1 0x0
+#define MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2         0x1e8 0x4fc 0x880 0x2 0x0
+#define MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28           0x1e8 0x4fc 0x000 0x5 0x0
+#define MX6QDL_PAD_ENET_TXD1__MLB_CLK               0x1ec 0x500 0x900 0x0 0x0
+#define MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1         0x1ec 0x500 0x000 0x1 0x0
+#define MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3          0x1ec 0x500 0x87c 0x2 0x0
+#define MX6QDL_PAD_ENET_TXD1__ENET_1588_EVENT0_IN   0x1ec 0x500 0x000 0x4 0x0
+#define MX6QDL_PAD_ENET_TXD1__GPIO1_IO29            0x1ec 0x500 0x000 0x5 0x0
+#define MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0         0x1f0 0x504 0x000 0x1 0x0
+#define MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1          0x1f0 0x504 0x884 0x2 0x0
+#define MX6QDL_PAD_ENET_TXD0__GPIO1_IO30            0x1f0 0x504 0x000 0x5 0x0
+#define MX6QDL_PAD_ENET_MDC__MLB_DATA               0x1f4 0x508 0x904 0x0 0x0
+#define MX6QDL_PAD_ENET_MDC__ENET_MDC               0x1f4 0x508 0x000 0x1 0x0
+#define MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0           0x1f4 0x508 0x888 0x2 0x0
+#define MX6QDL_PAD_ENET_MDC__ENET_1588_EVENT1_IN    0x1f4 0x508 0x000 0x4 0x0
+#define MX6QDL_PAD_ENET_MDC__GPIO1_IO31             0x1f4 0x508 0x000 0x5 0x0
+#define MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK            0x1f8 0x5c8 0x7f4 0x0 0x2
+#define MX6QDL_PAD_KEY_COL0__ENET_RX_DATA3          0x1f8 0x5c8 0x854 0x1 0x1
+#define MX6QDL_PAD_KEY_COL0__AUD5_TXC               0x1f8 0x5c8 0x7dc 0x2 0x1
+#define MX6QDL_PAD_KEY_COL0__KEY_COL0               0x1f8 0x5c8 0x000 0x3 0x0
+#define MX6QDL_PAD_KEY_COL0__UART4_TX_DATA          0x1f8 0x5c8 0x000 0x4 0x0
+#define MX6QDL_PAD_KEY_COL0__UART4_RX_DATA          0x1f8 0x5c8 0x938 0x4 0x0
+#define MX6QDL_PAD_KEY_COL0__GPIO4_IO06             0x1f8 0x5c8 0x000 0x5 0x0
+#define MX6QDL_PAD_KEY_COL0__DCIC1_OUT              0x1f8 0x5c8 0x000 0x6 0x0
+#define MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI            0x1fc 0x5cc 0x7fc 0x0 0x2
+#define MX6QDL_PAD_KEY_ROW0__ENET_TX_DATA3          0x1fc 0x5cc 0x000 0x1 0x0
+#define MX6QDL_PAD_KEY_ROW0__AUD5_TXD               0x1fc 0x5cc 0x7d0 0x2 0x1
+#define MX6QDL_PAD_KEY_ROW0__KEY_ROW0               0x1fc 0x5cc 0x000 0x3 0x0
+#define MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA          0x1fc 0x5cc 0x938 0x4 0x1
+#define MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA          0x1fc 0x5cc 0x000 0x4 0x0
+#define MX6QDL_PAD_KEY_ROW0__GPIO4_IO07             0x1fc 0x5cc 0x000 0x5 0x0
+#define MX6QDL_PAD_KEY_ROW0__DCIC2_OUT              0x1fc 0x5cc 0x000 0x6 0x0
+#define MX6QDL_PAD_KEY_COL1__ECSPI1_MISO            0x200 0x5d0 0x7f8 0x0 0x2
+#define MX6QDL_PAD_KEY_COL1__ENET_MDIO              0x200 0x5d0 0x840 0x1 0x1
+#define MX6QDL_PAD_KEY_COL1__AUD5_TXFS              0x200 0x5d0 0x7e0 0x2 0x1
+#define MX6QDL_PAD_KEY_COL1__KEY_COL1               0x200 0x5d0 0x000 0x3 0x0
+#define MX6QDL_PAD_KEY_COL1__UART5_TX_DATA          0x200 0x5d0 0x000 0x4 0x0
+#define MX6QDL_PAD_KEY_COL1__UART5_RX_DATA          0x200 0x5d0 0x940 0x4 0x0
+#define MX6QDL_PAD_KEY_COL1__GPIO4_IO08             0x200 0x5d0 0x000 0x5 0x0
+#define MX6QDL_PAD_KEY_COL1__SD1_VSELECT            0x200 0x5d0 0x000 0x6 0x0
+#define MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0             0x204 0x5d4 0x800 0x0 0x2
+#define MX6QDL_PAD_KEY_ROW1__ENET_COL               0x204 0x5d4 0x000 0x1 0x0
+#define MX6QDL_PAD_KEY_ROW1__AUD5_RXD               0x204 0x5d4 0x7cc 0x2 0x1
+#define MX6QDL_PAD_KEY_ROW1__KEY_ROW1               0x204 0x5d4 0x000 0x3 0x0
+#define MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA          0x204 0x5d4 0x940 0x4 0x1
+#define MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA          0x204 0x5d4 0x000 0x4 0x0
+#define MX6QDL_PAD_KEY_ROW1__GPIO4_IO09             0x204 0x5d4 0x000 0x5 0x0
+#define MX6QDL_PAD_KEY_ROW1__SD2_VSELECT            0x204 0x5d4 0x000 0x6 0x0
+#define MX6QDL_PAD_KEY_COL2__ECSPI1_SS1             0x208 0x5d8 0x804 0x0 0x2
+#define MX6QDL_PAD_KEY_COL2__ENET_RX_DATA2          0x208 0x5d8 0x850 0x1 0x1
+#define MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX            0x208 0x5d8 0x000 0x2 0x0
+#define MX6QDL_PAD_KEY_COL2__KEY_COL2               0x208 0x5d8 0x000 0x3 0x0
+#define MX6QDL_PAD_KEY_COL2__ENET_MDC               0x208 0x5d8 0x000 0x4 0x0
+#define MX6QDL_PAD_KEY_COL2__GPIO4_IO10             0x208 0x5d8 0x000 0x5 0x0
+#define MX6QDL_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE    0x208 0x5d8 0x000 0x6 0x0
+#define MX6QDL_PAD_KEY_ROW2__ECSPI1_SS2             0x20c 0x5dc 0x808 0x0 0x1
+#define MX6QDL_PAD_KEY_ROW2__ENET_TX_DATA2          0x20c 0x5dc 0x000 0x1 0x0
+#define MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX            0x20c 0x5dc 0x7e4 0x2 0x0
+#define MX6QDL_PAD_KEY_ROW2__KEY_ROW2               0x20c 0x5dc 0x000 0x3 0x0
+#define MX6QDL_PAD_KEY_ROW2__SD2_VSELECT            0x20c 0x5dc 0x000 0x4 0x0
+#define MX6QDL_PAD_KEY_ROW2__GPIO4_IO11             0x20c 0x5dc 0x000 0x5 0x0
+#define MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE       0x20c 0x5dc 0x88c 0x6 0x1
+#define MX6QDL_PAD_KEY_COL3__ECSPI1_SS3             0x210 0x5e0 0x80c 0x0 0x1
+#define MX6QDL_PAD_KEY_COL3__ENET_CRS               0x210 0x5e0 0x000 0x1 0x0
+#define MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL        0x210 0x5e0 0x890 0x2 0x1
+#define MX6QDL_PAD_KEY_COL3__KEY_COL3               0x210 0x5e0 0x000 0x3 0x0
+#define MX6QDL_PAD_KEY_COL3__I2C2_SCL               0x210 0x5e0 0x8a0 0x4 0x1
+#define MX6QDL_PAD_KEY_COL3__GPIO4_IO12             0x210 0x5e0 0x000 0x5 0x0
+#define MX6QDL_PAD_KEY_COL3__SPDIF_IN               0x210 0x5e0 0x914 0x6 0x2
+#define MX6QDL_PAD_KEY_ROW3__ASRC_EXT_CLK           0x214 0x5e4 0x7b0 0x1 0x0
+#define MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA        0x214 0x5e4 0x894 0x2 0x1
+#define MX6QDL_PAD_KEY_ROW3__KEY_ROW3               0x214 0x5e4 0x000 0x3 0x0
+#define MX6QDL_PAD_KEY_ROW3__I2C2_SDA               0x214 0x5e4 0x8a4 0x4 0x1
+#define MX6QDL_PAD_KEY_ROW3__GPIO4_IO13             0x214 0x5e4 0x000 0x5 0x0
+#define MX6QDL_PAD_KEY_ROW3__SD1_VSELECT            0x214 0x5e4 0x000 0x6 0x0
+#define MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX            0x218 0x5e8 0x000 0x0 0x0
+#define MX6QDL_PAD_KEY_COL4__IPU1_SISG4             0x218 0x5e8 0x000 0x1 0x0
+#define MX6QDL_PAD_KEY_COL4__USB_OTG_OC             0x218 0x5e8 0x944 0x2 0x1
+#define MX6QDL_PAD_KEY_COL4__KEY_COL4               0x218 0x5e8 0x000 0x3 0x0
+#define MX6QDL_PAD_KEY_COL4__UART5_RTS_B            0x218 0x5e8 0x93c 0x4 0x0
+#define MX6QDL_PAD_KEY_COL4__UART5_CTS_B            0x218 0x5e8 0x000 0x4 0x0
+#define MX6QDL_PAD_KEY_COL4__GPIO4_IO14             0x218 0x5e8 0x000 0x5 0x0
+#define MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX            0x21c 0x5ec 0x7e8 0x0 0x0
+#define MX6QDL_PAD_KEY_ROW4__IPU1_SISG5             0x21c 0x5ec 0x000 0x1 0x0
+#define MX6QDL_PAD_KEY_ROW4__USB_OTG_PWR            0x21c 0x5ec 0x000 0x2 0x0
+#define MX6QDL_PAD_KEY_ROW4__KEY_ROW4               0x21c 0x5ec 0x000 0x3 0x0
+#define MX6QDL_PAD_KEY_ROW4__UART5_CTS_B            0x21c 0x5ec 0x000 0x4 0x0
+#define MX6QDL_PAD_KEY_ROW4__UART5_RTS_B            0x21c 0x5ec 0x93c 0x4 0x1
+#define MX6QDL_PAD_KEY_ROW4__GPIO4_IO15             0x21c 0x5ec 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_0__CCM_CLKO1                0x220 0x5f0 0x000 0x0 0x0
+#define MX6QDL_PAD_GPIO_0__KEY_COL5                 0x220 0x5f0 0x8e8 0x2 0x0
+#define MX6QDL_PAD_GPIO_0__ASRC_EXT_CLK             0x220 0x5f0 0x7b0 0x3 0x1
+#define MX6QDL_PAD_GPIO_0__EPIT1_OUT                0x220 0x5f0 0x000 0x4 0x0
+#define MX6QDL_PAD_GPIO_0__GPIO1_IO00               0x220 0x5f0 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_0__USB_H1_PWR               0x220 0x5f0 0x000 0x6 0x0
+#define MX6QDL_PAD_GPIO_0__SNVS_VIO_5               0x220 0x5f0 0x000 0x7 0x0
+#define MX6QDL_PAD_GPIO_1__ESAI_RX_CLK              0x224 0x5f4 0x86c 0x0 0x1
+#define MX6QDL_PAD_GPIO_1__WDOG2_B                  0x224 0x5f4 0x000 0x1 0x0
+#define MX6QDL_PAD_GPIO_1__KEY_ROW5                 0x224 0x5f4 0x8f4 0x2 0x0
+#define MX6QDL_PAD_GPIO_1__USB_OTG_ID               0x224 0x5f4 0x000 0x3 0x0
+#define MX6QDL_PAD_GPIO_1__PWM2_OUT                 0x224 0x5f4 0x000 0x4 0x0
+#define MX6QDL_PAD_GPIO_1__GPIO1_IO01               0x224 0x5f4 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_1__SD1_CD_B                 0x224 0x5f4 0x000 0x6 0x0
+#define MX6QDL_PAD_GPIO_9__ESAI_RX_FS               0x228 0x5f8 0x85c 0x0 0x1
+#define MX6QDL_PAD_GPIO_9__WDOG1_B                  0x228 0x5f8 0x000 0x1 0x0
+#define MX6QDL_PAD_GPIO_9__KEY_COL6                 0x228 0x5f8 0x8ec 0x2 0x0
+#define MX6QDL_PAD_GPIO_9__CCM_REF_EN_B             0x228 0x5f8 0x000 0x3 0x0
+#define MX6QDL_PAD_GPIO_9__PWM1_OUT                 0x228 0x5f8 0x000 0x4 0x0
+#define MX6QDL_PAD_GPIO_9__GPIO1_IO09               0x228 0x5f8 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_9__SD1_WP                   0x228 0x5f8 0x94c 0x6 0x1
+#define MX6QDL_PAD_GPIO_3__ESAI_RX_HF_CLK           0x22c 0x5fc 0x864 0x0 0x1
+#define MX6QDL_PAD_GPIO_3__I2C3_SCL                 0x22c 0x5fc 0x8a8 0x2 0x1
+#define MX6QDL_PAD_GPIO_3__XTALOSC_REF_CLK_24M      0x22c 0x5fc 0x000 0x3 0x0
+#define MX6QDL_PAD_GPIO_3__CCM_CLKO2                0x22c 0x5fc 0x000 0x4 0x0
+#define MX6QDL_PAD_GPIO_3__GPIO1_IO03               0x22c 0x5fc 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_3__USB_H1_OC                0x22c 0x5fc 0x948 0x6 0x1
+#define MX6QDL_PAD_GPIO_3__MLB_CLK                  0x22c 0x5fc 0x900 0x7 0x1
+#define MX6QDL_PAD_GPIO_6__ESAI_TX_CLK              0x230 0x600 0x870 0x0 0x1
+#define MX6QDL_PAD_GPIO_6__I2C3_SDA                 0x230 0x600 0x8ac 0x2 0x1
+#define MX6QDL_PAD_GPIO_6__GPIO1_IO06               0x230 0x600 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_6__SD2_LCTL                 0x230 0x600 0x000 0x6 0x0
+#define MX6QDL_PAD_GPIO_6__MLB_SIG                  0x230 0x600 0x908 0x7 0x1
+#define MX6QDL_PAD_GPIO_2__ESAI_TX_FS               0x234 0x604 0x860 0x0 0x1
+#define MX6QDL_PAD_GPIO_2__KEY_ROW6                 0x234 0x604 0x8f8 0x2 0x1
+#define MX6QDL_PAD_GPIO_2__GPIO1_IO02               0x234 0x604 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_2__SD2_WP                   0x234 0x604 0x000 0x6 0x0
+#define MX6QDL_PAD_GPIO_2__MLB_DATA                 0x234 0x604 0x904 0x7 0x1
+#define MX6QDL_PAD_GPIO_4__ESAI_TX_HF_CLK           0x238 0x608 0x868 0x0 0x1
+#define MX6QDL_PAD_GPIO_4__KEY_COL7                 0x238 0x608 0x8f0 0x2 0x1
+#define MX6QDL_PAD_GPIO_4__GPIO1_IO04               0x238 0x608 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_4__SD2_CD_B                 0x238 0x608 0x000 0x6 0x0
+#define MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3             0x23c 0x60c 0x87c 0x0 0x1
+#define MX6QDL_PAD_GPIO_5__KEY_ROW7                 0x23c 0x60c 0x8fc 0x2 0x1
+#define MX6QDL_PAD_GPIO_5__CCM_CLKO1                0x23c 0x60c 0x000 0x3 0x0
+#define MX6QDL_PAD_GPIO_5__GPIO1_IO05               0x23c 0x60c 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_5__I2C3_SCL                 0x23c 0x60c 0x8a8 0x6 0x2
+#define MX6QDL_PAD_GPIO_5__ARM_EVENTI               0x23c 0x60c 0x000 0x7 0x0
+#define MX6QDL_PAD_GPIO_7__ESAI_TX4_RX1             0x240 0x610 0x884 0x0 0x1
+#define MX6QDL_PAD_GPIO_7__ECSPI5_RDY               0x240 0x610 0x000 0x1 0x0
+#define MX6QDL_PAD_GPIO_7__EPIT1_OUT                0x240 0x610 0x000 0x2 0x0
+#define MX6QDL_PAD_GPIO_7__FLEXCAN1_TX              0x240 0x610 0x000 0x3 0x0
+#define MX6QDL_PAD_GPIO_7__UART2_TX_DATA            0x240 0x610 0x000 0x4 0x0
+#define MX6QDL_PAD_GPIO_7__UART2_RX_DATA            0x240 0x610 0x928 0x4 0x2
+#define MX6QDL_PAD_GPIO_7__GPIO1_IO07               0x240 0x610 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_7__SPDIF_LOCK               0x240 0x610 0x000 0x6 0x0
+#define MX6QDL_PAD_GPIO_7__USB_OTG_HOST_MODE        0x240 0x610 0x000 0x7 0x0
+#define MX6QDL_PAD_GPIO_8__ESAI_TX5_RX0             0x244 0x614 0x888 0x0 0x1
+#define MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K      0x244 0x614 0x000 0x1 0x0
+#define MX6QDL_PAD_GPIO_8__EPIT2_OUT                0x244 0x614 0x000 0x2 0x0
+#define MX6QDL_PAD_GPIO_8__FLEXCAN1_RX              0x244 0x614 0x7e4 0x3 0x1
+#define MX6QDL_PAD_GPIO_8__UART2_RX_DATA            0x244 0x614 0x928 0x4 0x3
+#define MX6QDL_PAD_GPIO_8__UART2_TX_DATA            0x244 0x614 0x000 0x4 0x0
+#define MX6QDL_PAD_GPIO_8__GPIO1_IO08               0x244 0x614 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_8__SPDIF_SR_CLK             0x244 0x614 0x000 0x6 0x0
+#define MX6QDL_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE     0x244 0x614 0x000 0x7 0x0
+#define MX6QDL_PAD_GPIO_16__ESAI_TX3_RX2            0x248 0x618 0x880 0x0 0x1
+#define MX6QDL_PAD_GPIO_16__ENET_1588_EVENT2_IN     0x248 0x618 0x000 0x1 0x0
+#define MX6QDL_PAD_GPIO_16__ENET_REF_CLK            0x248 0x618 0x83c 0x2 0x1
+#define MX6QDL_PAD_GPIO_16__SD1_LCTL                0x248 0x618 0x000 0x3 0x0
+#define MX6QDL_PAD_GPIO_16__SPDIF_IN                0x248 0x618 0x914 0x4 0x3
+#define MX6QDL_PAD_GPIO_16__GPIO7_IO11              0x248 0x618 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_16__I2C3_SDA                0x248 0x618 0x8ac 0x6 0x2
+#define MX6QDL_PAD_GPIO_16__JTAG_DE_B               0x248 0x618 0x000 0x7 0x0
+#define MX6QDL_PAD_GPIO_17__ESAI_TX0                0x24c 0x61c 0x874 0x0 0x0
+#define MX6QDL_PAD_GPIO_17__ENET_1588_EVENT3_IN     0x24c 0x61c 0x000 0x1 0x0
+#define MX6QDL_PAD_GPIO_17__CCM_PMIC_READY          0x24c 0x61c 0x7f0 0x2 0x1
+#define MX6QDL_PAD_GPIO_17__SDMA_EXT_EVENT0         0x24c 0x61c 0x90c 0x3 0x1
+#define MX6QDL_PAD_GPIO_17__SPDIF_OUT               0x24c 0x61c 0x000 0x4 0x0
+#define MX6QDL_PAD_GPIO_17__GPIO7_IO12              0x24c 0x61c 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_18__ESAI_TX1                0x250 0x620 0x878 0x0 0x0
+#define MX6QDL_PAD_GPIO_18__ENET_RX_CLK             0x250 0x620 0x844 0x1 0x1
+#define MX6QDL_PAD_GPIO_18__SD3_VSELECT             0x250 0x620 0x000 0x2 0x0
+#define MX6QDL_PAD_GPIO_18__SDMA_EXT_EVENT1         0x250 0x620 0x910 0x3 0x1
+#define MX6QDL_PAD_GPIO_18__ASRC_EXT_CLK            0x250 0x620 0x7b0 0x4 0x2
+#define MX6QDL_PAD_GPIO_18__GPIO7_IO13              0x250 0x620 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_18__SNVS_VIO_5_CTL          0x250 0x620 0x000 0x6 0x0
+#define MX6QDL_PAD_GPIO_19__KEY_COL5                0x254 0x624 0x8e8 0x0 0x1
+#define MX6QDL_PAD_GPIO_19__ENET_1588_EVENT0_OUT    0x254 0x624 0x000 0x1 0x0
+#define MX6QDL_PAD_GPIO_19__SPDIF_OUT               0x254 0x624 0x000 0x2 0x0
+#define MX6QDL_PAD_GPIO_19__CCM_CLKO1               0x254 0x624 0x000 0x3 0x0
+#define MX6QDL_PAD_GPIO_19__ECSPI1_RDY              0x254 0x624 0x000 0x4 0x0
+#define MX6QDL_PAD_GPIO_19__GPIO4_IO05              0x254 0x624 0x000 0x5 0x0
+#define MX6QDL_PAD_GPIO_19__ENET_TX_ER              0x254 0x624 0x000 0x6 0x0
+#define MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK    0x258 0x628 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18          0x258 0x628 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_PIXCLK__ARM_EVENTO          0x258 0x628 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC       0x25c 0x62c 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1             0x25c 0x62c 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19            0x25c 0x62c 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL         0x25c 0x62c 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN  0x260 0x630 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00         0x260 0x630 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20         0x260 0x630 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK      0x260 0x630 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC      0x264 0x634 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01           0x264 0x634 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21           0x264 0x634 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_VSYNC__ARM_TRACE00          0x264 0x634 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04      0x268 0x638 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT4__EIM_DATA02            0x268 0x638 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK           0x268 0x638 0x7f4 0x2 0x3
+#define MX6QDL_PAD_CSI0_DAT4__KEY_COL5              0x268 0x638 0x8e8 0x3 0x2
+#define MX6QDL_PAD_CSI0_DAT4__AUD3_TXC              0x268 0x638 0x000 0x4 0x0
+#define MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22            0x268 0x638 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT4__ARM_TRACE01           0x268 0x638 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05      0x26c 0x63c 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT5__EIM_DATA03            0x26c 0x63c 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI           0x26c 0x63c 0x7fc 0x2 0x3
+#define MX6QDL_PAD_CSI0_DAT5__KEY_ROW5              0x26c 0x63c 0x8f4 0x3 0x1
+#define MX6QDL_PAD_CSI0_DAT5__AUD3_TXD              0x26c 0x63c 0x000 0x4 0x0
+#define MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23            0x26c 0x63c 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT5__ARM_TRACE02           0x26c 0x63c 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06      0x270 0x640 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT6__EIM_DATA04            0x270 0x640 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO           0x270 0x640 0x7f8 0x2 0x3
+#define MX6QDL_PAD_CSI0_DAT6__KEY_COL6              0x270 0x640 0x8ec 0x3 0x1
+#define MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS             0x270 0x640 0x000 0x4 0x0
+#define MX6QDL_PAD_CSI0_DAT6__GPIO5_IO24            0x270 0x640 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT6__ARM_TRACE03           0x270 0x640 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07      0x274 0x644 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT7__EIM_DATA05            0x274 0x644 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT7__ECSPI1_SS0            0x274 0x644 0x800 0x2 0x3
+#define MX6QDL_PAD_CSI0_DAT7__KEY_ROW6              0x274 0x644 0x8f8 0x3 0x2
+#define MX6QDL_PAD_CSI0_DAT7__AUD3_RXD              0x274 0x644 0x000 0x4 0x0
+#define MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25            0x274 0x644 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT7__ARM_TRACE04           0x274 0x644 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08      0x278 0x648 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT8__EIM_DATA06            0x278 0x648 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK           0x278 0x648 0x810 0x2 0x2
+#define MX6QDL_PAD_CSI0_DAT8__KEY_COL7              0x278 0x648 0x8f0 0x3 0x2
+#define MX6QDL_PAD_CSI0_DAT8__I2C1_SDA              0x278 0x648 0x89c 0x4 0x1
+#define MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26            0x278 0x648 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT8__ARM_TRACE05           0x278 0x648 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09      0x27c 0x64c 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT9__EIM_DATA07            0x27c 0x64c 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI           0x27c 0x64c 0x818 0x2 0x2
+#define MX6QDL_PAD_CSI0_DAT9__KEY_ROW7              0x27c 0x64c 0x8fc 0x3 0x2
+#define MX6QDL_PAD_CSI0_DAT9__I2C1_SCL              0x27c 0x64c 0x898 0x4 0x1
+#define MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27            0x27c 0x64c 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT9__ARM_TRACE06           0x27c 0x64c 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10     0x280 0x650 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC             0x280 0x650 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO          0x280 0x650 0x814 0x2 0x2
+#define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA        0x280 0x650 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA        0x280 0x650 0x920 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28           0x280 0x650 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07          0x280 0x650 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11     0x284 0x654 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS            0x284 0x654 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0           0x284 0x654 0x81c 0x2 0x2
+#define MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA        0x284 0x654 0x920 0x3 0x1
+#define MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA        0x284 0x654 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29           0x284 0x654 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT11__ARM_TRACE08          0x284 0x654 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12     0x288 0x658 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT12__EIM_DATA08           0x288 0x658 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA        0x288 0x658 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT12__UART4_RX_DATA        0x288 0x658 0x938 0x3 0x2
+#define MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30           0x288 0x658 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT12__ARM_TRACE09          0x288 0x658 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13     0x28c 0x65c 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT13__EIM_DATA09           0x28c 0x65c 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA        0x28c 0x65c 0x938 0x3 0x3
+#define MX6QDL_PAD_CSI0_DAT13__UART4_TX_DATA        0x28c 0x65c 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31           0x28c 0x65c 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT13__ARM_TRACE10          0x28c 0x65c 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14     0x290 0x660 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT14__EIM_DATA10           0x290 0x660 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA        0x290 0x660 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT14__UART5_RX_DATA        0x290 0x660 0x940 0x3 0x2
+#define MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00           0x290 0x660 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT14__ARM_TRACE11          0x290 0x660 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15     0x294 0x664 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT15__EIM_DATA11           0x294 0x664 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA        0x294 0x664 0x940 0x3 0x3
+#define MX6QDL_PAD_CSI0_DAT15__UART5_TX_DATA        0x294 0x664 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01           0x294 0x664 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT15__ARM_TRACE12          0x294 0x664 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16     0x298 0x668 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT16__EIM_DATA12           0x298 0x668 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B          0x298 0x668 0x934 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT16__UART4_CTS_B          0x298 0x668 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02           0x298 0x668 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT16__ARM_TRACE13          0x298 0x668 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17     0x29c 0x66c 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT17__EIM_DATA13           0x29c 0x66c 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B          0x29c 0x66c 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT17__UART4_RTS_B          0x29c 0x66c 0x934 0x3 0x1
+#define MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03           0x29c 0x66c 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT17__ARM_TRACE14          0x29c 0x66c 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18     0x2a0 0x670 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT18__EIM_DATA14           0x2a0 0x670 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B          0x2a0 0x670 0x93c 0x3 0x2
+#define MX6QDL_PAD_CSI0_DAT18__UART5_CTS_B          0x2a0 0x670 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04           0x2a0 0x670 0x000 0x5 0x0
+#define MX6QDL_PAD_CSI0_DAT18__ARM_TRACE15          0x2a0 0x670 0x000 0x7 0x0
+#define MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19     0x2a4 0x674 0x000 0x0 0x0
+#define MX6QDL_PAD_CSI0_DAT19__EIM_DATA15           0x2a4 0x674 0x000 0x1 0x0
+#define MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B          0x2a4 0x674 0x000 0x3 0x0
+#define MX6QDL_PAD_CSI0_DAT19__UART5_RTS_B          0x2a4 0x674 0x93c 0x3 0x3
+#define MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05           0x2a4 0x674 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_DAT7__SD3_DATA7              0x2a8 0x690 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA          0x2a8 0x690 0x000 0x1 0x0
+#define MX6QDL_PAD_SD3_DAT7__UART1_RX_DATA          0x2a8 0x690 0x920 0x1 0x2
+#define MX6QDL_PAD_SD3_DAT7__GPIO6_IO17             0x2a8 0x690 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_DAT6__SD3_DATA6              0x2ac 0x694 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA          0x2ac 0x694 0x920 0x1 0x3
+#define MX6QDL_PAD_SD3_DAT6__UART1_TX_DATA          0x2ac 0x694 0x000 0x1 0x0
+#define MX6QDL_PAD_SD3_DAT6__GPIO6_IO18             0x2ac 0x694 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_DAT5__SD3_DATA5              0x2b0 0x698 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA          0x2b0 0x698 0x000 0x1 0x0
+#define MX6QDL_PAD_SD3_DAT5__UART2_RX_DATA          0x2b0 0x698 0x928 0x1 0x4
+#define MX6QDL_PAD_SD3_DAT5__GPIO7_IO00             0x2b0 0x698 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_DAT4__SD3_DATA4              0x2b4 0x69c 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA          0x2b4 0x69c 0x928 0x1 0x5
+#define MX6QDL_PAD_SD3_DAT4__UART2_TX_DATA          0x2b4 0x69c 0x000 0x1 0x0
+#define MX6QDL_PAD_SD3_DAT4__GPIO7_IO01             0x2b4 0x69c 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_CMD__SD3_CMD                 0x2b8 0x6a0 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_CMD__UART2_CTS_B             0x2b8 0x6a0 0x000 0x1 0x0
+#define MX6QDL_PAD_SD3_CMD__UART2_RTS_B             0x2b8 0x6a0 0x924 0x1 0x2
+#define MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX             0x2b8 0x6a0 0x000 0x2 0x0
+#define MX6QDL_PAD_SD3_CMD__GPIO7_IO02              0x2b8 0x6a0 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_CLK__SD3_CLK                 0x2bc 0x6a4 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_CLK__UART2_RTS_B             0x2bc 0x6a4 0x924 0x1 0x3
+#define MX6QDL_PAD_SD3_CLK__UART2_CTS_B             0x2bc 0x6a4 0x000 0x1 0x0
+#define MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX             0x2bc 0x6a4 0x7e4 0x2 0x2
+#define MX6QDL_PAD_SD3_CLK__GPIO7_IO03              0x2bc 0x6a4 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_DAT0__SD3_DATA0              0x2c0 0x6a8 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_DAT0__UART1_CTS_B            0x2c0 0x6a8 0x000 0x1 0x0
+#define MX6QDL_PAD_SD3_DAT0__UART1_RTS_B            0x2c0 0x6a8 0x91c 0x1 0x2
+#define MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX            0x2c0 0x6a8 0x000 0x2 0x0
+#define MX6QDL_PAD_SD3_DAT0__GPIO7_IO04             0x2c0 0x6a8 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_DAT1__SD3_DATA1              0x2c4 0x6ac 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_DAT1__UART1_RTS_B            0x2c4 0x6ac 0x91c 0x1 0x3
+#define MX6QDL_PAD_SD3_DAT1__UART1_CTS_B            0x2c4 0x6ac 0x000 0x1 0x0
+#define MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX            0x2c4 0x6ac 0x7e8 0x2 0x1
+#define MX6QDL_PAD_SD3_DAT1__GPIO7_IO05             0x2c4 0x6ac 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_DAT2__SD3_DATA2              0x2c8 0x6b0 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_DAT2__GPIO7_IO06             0x2c8 0x6b0 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_DAT3__SD3_DATA3              0x2cc 0x6b4 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_DAT3__UART3_CTS_B            0x2cc 0x6b4 0x000 0x1 0x0
+#define MX6QDL_PAD_SD3_DAT3__UART3_RTS_B            0x2cc 0x6b4 0x92c 0x1 0x4
+#define MX6QDL_PAD_SD3_DAT3__GPIO7_IO07             0x2cc 0x6b4 0x000 0x5 0x0
+#define MX6QDL_PAD_SD3_RST__SD3_RESET               0x2d0 0x6b8 0x000 0x0 0x0
+#define MX6QDL_PAD_SD3_RST__UART3_RTS_B             0x2d0 0x6b8 0x92c 0x1 0x5
+#define MX6QDL_PAD_SD3_RST__UART3_CTS_B             0x2d0 0x6b8 0x000 0x1 0x0
+#define MX6QDL_PAD_SD3_RST__GPIO7_IO08              0x2d0 0x6b8 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_CLE__NAND_CLE              0x2d4 0x6bc 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_CLE__IPU2_SISG4            0x2d4 0x6bc 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_CLE__GPIO6_IO07            0x2d4 0x6bc 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_ALE__NAND_ALE              0x2d8 0x6c0 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_ALE__SD4_RESET             0x2d8 0x6c0 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_ALE__GPIO6_IO08            0x2d8 0x6c0 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_WP_B__NAND_WP_B            0x2dc 0x6c4 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_WP_B__IPU2_SISG5           0x2dc 0x6c4 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09           0x2dc 0x6c4 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_RB0__NAND_READY_B          0x2e0 0x6c8 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_RB0__IPU2_DI0_PIN01        0x2e0 0x6c8 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_RB0__GPIO6_IO10            0x2e0 0x6c8 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_CS0__NAND_CE0_B            0x2e4 0x6cc 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_CS0__GPIO6_IO11            0x2e4 0x6cc 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_CS1__NAND_CE1_B            0x2e8 0x6d0 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_CS1__SD4_VSELECT           0x2e8 0x6d0 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_CS1__SD3_VSELECT           0x2e8 0x6d0 0x000 0x2 0x0
+#define MX6QDL_PAD_NANDF_CS1__GPIO6_IO14            0x2e8 0x6d0 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_CS2__NAND_CE2_B            0x2ec 0x6d4 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_CS2__IPU1_SISG0            0x2ec 0x6d4 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_CS2__ESAI_TX0              0x2ec 0x6d4 0x874 0x2 0x1
+#define MX6QDL_PAD_NANDF_CS2__EIM_CRE               0x2ec 0x6d4 0x000 0x3 0x0
+#define MX6QDL_PAD_NANDF_CS2__CCM_CLKO2             0x2ec 0x6d4 0x000 0x4 0x0
+#define MX6QDL_PAD_NANDF_CS2__GPIO6_IO15            0x2ec 0x6d4 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_CS2__IPU2_SISG0            0x2ec 0x6d4 0x000 0x6 0x0
+#define MX6QDL_PAD_NANDF_CS3__NAND_CE3_B            0x2f0 0x6d8 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_CS3__IPU1_SISG1            0x2f0 0x6d8 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_CS3__ESAI_TX1              0x2f0 0x6d8 0x878 0x2 0x1
+#define MX6QDL_PAD_NANDF_CS3__EIM_ADDR26            0x2f0 0x6d8 0x000 0x3 0x0
+#define MX6QDL_PAD_NANDF_CS3__GPIO6_IO16            0x2f0 0x6d8 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_CS3__IPU2_SISG1            0x2f0 0x6d8 0x000 0x6 0x0
+#define MX6QDL_PAD_SD4_CMD__SD4_CMD                 0x2f4 0x6dc 0x000 0x0 0x0
+#define MX6QDL_PAD_SD4_CMD__NAND_RE_B               0x2f4 0x6dc 0x000 0x1 0x0
+#define MX6QDL_PAD_SD4_CMD__UART3_TX_DATA           0x2f4 0x6dc 0x000 0x2 0x0
+#define MX6QDL_PAD_SD4_CMD__UART3_RX_DATA           0x2f4 0x6dc 0x930 0x2 0x2
+#define MX6QDL_PAD_SD4_CMD__GPIO7_IO09              0x2f4 0x6dc 0x000 0x5 0x0
+#define MX6QDL_PAD_SD4_CLK__SD4_CLK                 0x2f8 0x6e0 0x000 0x0 0x0
+#define MX6QDL_PAD_SD4_CLK__NAND_WE_B               0x2f8 0x6e0 0x000 0x1 0x0
+#define MX6QDL_PAD_SD4_CLK__UART3_RX_DATA           0x2f8 0x6e0 0x930 0x2 0x3
+#define MX6QDL_PAD_SD4_CLK__UART3_TX_DATA           0x2f8 0x6e0 0x000 0x2 0x0
+#define MX6QDL_PAD_SD4_CLK__GPIO7_IO10              0x2f8 0x6e0 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_D0__NAND_DATA00            0x2fc 0x6e4 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_D0__SD1_DATA4              0x2fc 0x6e4 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_D0__GPIO2_IO00             0x2fc 0x6e4 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_D1__NAND_DATA01            0x300 0x6e8 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_D1__SD1_DATA5              0x300 0x6e8 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_D1__GPIO2_IO01             0x300 0x6e8 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_D2__NAND_DATA02            0x304 0x6ec 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_D2__SD1_DATA6              0x304 0x6ec 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_D2__GPIO2_IO02             0x304 0x6ec 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_D3__NAND_DATA03            0x308 0x6f0 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_D3__SD1_DATA7              0x308 0x6f0 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_D3__GPIO2_IO03             0x308 0x6f0 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_D4__NAND_DATA04            0x30c 0x6f4 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_D4__SD2_DATA4              0x30c 0x6f4 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_D4__GPIO2_IO04             0x30c 0x6f4 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_D5__NAND_DATA05            0x310 0x6f8 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_D5__SD2_DATA5              0x310 0x6f8 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_D5__GPIO2_IO05             0x310 0x6f8 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_D6__NAND_DATA06            0x314 0x6fc 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_D6__SD2_DATA6              0x314 0x6fc 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_D6__GPIO2_IO06             0x314 0x6fc 0x000 0x5 0x0
+#define MX6QDL_PAD_NANDF_D7__NAND_DATA07            0x318 0x700 0x000 0x0 0x0
+#define MX6QDL_PAD_NANDF_D7__SD2_DATA7              0x318 0x700 0x000 0x1 0x0
+#define MX6QDL_PAD_NANDF_D7__GPIO2_IO07             0x318 0x700 0x000 0x5 0x0
+#define MX6QDL_PAD_SD4_DAT0__SD4_DATA0              0x31c 0x704 0x000 0x1 0x0
+#define MX6QDL_PAD_SD4_DAT0__NAND_DQS               0x31c 0x704 0x000 0x2 0x0
+#define MX6QDL_PAD_SD4_DAT0__GPIO2_IO08             0x31c 0x704 0x000 0x5 0x0
+#define MX6QDL_PAD_SD4_DAT1__SD4_DATA1              0x320 0x708 0x000 0x1 0x0
+#define MX6QDL_PAD_SD4_DAT1__PWM3_OUT               0x320 0x708 0x000 0x2 0x0
+#define MX6QDL_PAD_SD4_DAT1__GPIO2_IO09             0x320 0x708 0x000 0x5 0x0
+#define MX6QDL_PAD_SD4_DAT2__SD4_DATA2              0x324 0x70c 0x000 0x1 0x0
+#define MX6QDL_PAD_SD4_DAT2__PWM4_OUT               0x324 0x70c 0x000 0x2 0x0
+#define MX6QDL_PAD_SD4_DAT2__GPIO2_IO10             0x324 0x70c 0x000 0x5 0x0
+#define MX6QDL_PAD_SD4_DAT3__SD4_DATA3              0x328 0x710 0x000 0x1 0x0
+#define MX6QDL_PAD_SD4_DAT3__GPIO2_IO11             0x328 0x710 0x000 0x5 0x0
+#define MX6QDL_PAD_SD4_DAT4__SD4_DATA4              0x32c 0x714 0x000 0x1 0x0
+#define MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA          0x32c 0x714 0x928 0x2 0x6
+#define MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA          0x32c 0x714 0x000 0x2 0x0
+#define MX6QDL_PAD_SD4_DAT4__GPIO2_IO12             0x32c 0x714 0x000 0x5 0x0
+#define MX6QDL_PAD_SD4_DAT5__SD4_DATA5              0x330 0x718 0x000 0x1 0x0
+#define MX6QDL_PAD_SD4_DAT5__UART2_RTS_B            0x330 0x718 0x924 0x2 0x4
+#define MX6QDL_PAD_SD4_DAT5__UART2_CTS_B            0x330 0x718 0x000 0x2 0x0
+#define MX6QDL_PAD_SD4_DAT5__GPIO2_IO13             0x330 0x718 0x000 0x5 0x0
+#define MX6QDL_PAD_SD4_DAT6__SD4_DATA6              0x334 0x71c 0x000 0x1 0x0
+#define MX6QDL_PAD_SD4_DAT6__UART2_CTS_B            0x334 0x71c 0x000 0x2 0x0
+#define MX6QDL_PAD_SD4_DAT6__UART2_RTS_B            0x334 0x71c 0x924 0x2 0x5
+#define MX6QDL_PAD_SD4_DAT6__GPIO2_IO14             0x334 0x71c 0x000 0x5 0x0
+#define MX6QDL_PAD_SD4_DAT7__SD4_DATA7              0x338 0x720 0x000 0x1 0x0
+#define MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA          0x338 0x720 0x000 0x2 0x0
+#define MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA          0x338 0x720 0x928 0x2 0x7
+#define MX6QDL_PAD_SD4_DAT7__GPIO2_IO15             0x338 0x720 0x000 0x5 0x0
+#define MX6QDL_PAD_SD1_DAT1__SD1_DATA1              0x33c 0x724 0x000 0x0 0x0
+#define MX6QDL_PAD_SD1_DAT1__ECSPI5_SS0             0x33c 0x724 0x834 0x1 0x1
+#define MX6QDL_PAD_SD1_DAT1__PWM3_OUT               0x33c 0x724 0x000 0x2 0x0
+#define MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2           0x33c 0x724 0x000 0x3 0x0
+#define MX6QDL_PAD_SD1_DAT1__GPIO1_IO17             0x33c 0x724 0x000 0x5 0x0
+#define MX6QDL_PAD_SD1_DAT0__SD1_DATA0              0x340 0x728 0x000 0x0 0x0
+#define MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO            0x340 0x728 0x82c 0x1 0x1
+#define MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1           0x340 0x728 0x000 0x3 0x0
+#define MX6QDL_PAD_SD1_DAT0__GPIO1_IO16             0x340 0x728 0x000 0x5 0x0
+#define MX6QDL_PAD_SD1_DAT3__SD1_DATA3              0x344 0x72c 0x000 0x0 0x0
+#define MX6QDL_PAD_SD1_DAT3__ECSPI5_SS2             0x344 0x72c 0x000 0x1 0x0
+#define MX6QDL_PAD_SD1_DAT3__GPT_COMPARE3           0x344 0x72c 0x000 0x2 0x0
+#define MX6QDL_PAD_SD1_DAT3__PWM1_OUT               0x344 0x72c 0x000 0x3 0x0
+#define MX6QDL_PAD_SD1_DAT3__WDOG2_B                0x344 0x72c 0x000 0x4 0x0
+#define MX6QDL_PAD_SD1_DAT3__GPIO1_IO21             0x344 0x72c 0x000 0x5 0x0
+#define MX6QDL_PAD_SD1_DAT3__WDOG2_RESET_B_DEB      0x344 0x72c 0x000 0x6 0x0
+#define MX6QDL_PAD_SD1_CMD__SD1_CMD                 0x348 0x730 0x000 0x0 0x0
+#define MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI             0x348 0x730 0x830 0x1 0x0
+#define MX6QDL_PAD_SD1_CMD__PWM4_OUT                0x348 0x730 0x000 0x2 0x0
+#define MX6QDL_PAD_SD1_CMD__GPT_COMPARE1            0x348 0x730 0x000 0x3 0x0
+#define MX6QDL_PAD_SD1_CMD__GPIO1_IO18              0x348 0x730 0x000 0x5 0x0
+#define MX6QDL_PAD_SD1_DAT2__SD1_DATA2              0x34c 0x734 0x000 0x0 0x0
+#define MX6QDL_PAD_SD1_DAT2__ECSPI5_SS1             0x34c 0x734 0x838 0x1 0x1
+#define MX6QDL_PAD_SD1_DAT2__GPT_COMPARE2           0x34c 0x734 0x000 0x2 0x0
+#define MX6QDL_PAD_SD1_DAT2__PWM2_OUT               0x34c 0x734 0x000 0x3 0x0
+#define MX6QDL_PAD_SD1_DAT2__WDOG1_B                0x34c 0x734 0x000 0x4 0x0
+#define MX6QDL_PAD_SD1_DAT2__GPIO1_IO19             0x34c 0x734 0x000 0x5 0x0
+#define MX6QDL_PAD_SD1_DAT2__WDOG1_RESET_B_DEB      0x34c 0x734 0x000 0x6 0x0
+#define MX6QDL_PAD_SD1_CLK__SD1_CLK                 0x350 0x738 0x000 0x0 0x0
+#define MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK             0x350 0x738 0x828 0x1 0x0
+#define MX6QDL_PAD_SD1_CLK__GPT_CLKIN               0x350 0x738 0x000 0x3 0x0
+#define MX6QDL_PAD_SD1_CLK__GPIO1_IO20              0x350 0x738 0x000 0x5 0x0
+#define MX6QDL_PAD_SD2_CLK__SD2_CLK                 0x354 0x73c 0x000 0x0 0x0
+#define MX6QDL_PAD_SD2_CLK__ECSPI5_SCLK             0x354 0x73c 0x828 0x1 0x1
+#define MX6QDL_PAD_SD2_CLK__KEY_COL5                0x354 0x73c 0x8e8 0x2 0x3
+#define MX6QDL_PAD_SD2_CLK__AUD4_RXFS               0x354 0x73c 0x7c0 0x3 0x1
+#define MX6QDL_PAD_SD2_CLK__GPIO1_IO10              0x354 0x73c 0x000 0x5 0x0
+#define MX6QDL_PAD_SD2_CMD__SD2_CMD                 0x358 0x740 0x000 0x0 0x0
+#define MX6QDL_PAD_SD2_CMD__ECSPI5_MOSI             0x358 0x740 0x830 0x1 0x1
+#define MX6QDL_PAD_SD2_CMD__KEY_ROW5                0x358 0x740 0x8f4 0x2 0x2
+#define MX6QDL_PAD_SD2_CMD__AUD4_RXC                0x358 0x740 0x7bc 0x3 0x1
+#define MX6QDL_PAD_SD2_CMD__GPIO1_IO11              0x358 0x740 0x000 0x5 0x0
+#define MX6QDL_PAD_SD2_DAT3__SD2_DATA3              0x35c 0x744 0x000 0x0 0x0
+#define MX6QDL_PAD_SD2_DAT3__ECSPI5_SS3             0x35c 0x744 0x000 0x1 0x0
+#define MX6QDL_PAD_SD2_DAT3__KEY_COL6               0x35c 0x744 0x8ec 0x2 0x2
+#define MX6QDL_PAD_SD2_DAT3__AUD4_TXC               0x35c 0x744 0x7c4 0x3 0x1
+#define MX6QDL_PAD_SD2_DAT3__GPIO1_IO12             0x35c 0x744 0x000 0x5 0x0
 
 #endif /* __DTS_IMX6Q_PINFUNC_H */
diff --git a/arch/arm/boot/dts/imx6q-sabreauto.dts b/arch/arm/boot/dts/imx6q-sabreauto.dts
index 09a75807bc6d..334b9247e78c 100644
--- a/arch/arm/boot/dts/imx6q-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6q-sabreauto.dts
@@ -20,24 +20,6 @@
         compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
 };
 
-&iomuxc {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_hog>;
-
-        hog {
-                pinctrl_hog: hoggrp {
-                        fsl,pins = <
-                                MX6Q_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
-                                MX6Q_PAD_SD2_DAT2__GPIO1_IO13  0x80000000
-                        >;
-                };
-        };
-
-        ecspi1 {
-                pinctrl_ecspi1_sabreauto: ecspi1-sabreauto {
-                        fsl,pins = <
-                                MX6Q_PAD_EIM_D19__GPIO3_IO19  0x80000000
-                        >;
-                };
-        };
+&sata {
+        status = "okay";
 };
diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
index 6a000666c147..3530280f5150 100644
--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -65,6 +65,10 @@
         };
 };
 
+&sata {
+        status = "okay";
+};
+
 &ecspi1 {
         fsl,spi-num-chipselects = <1>;
         cs-gpios = <&gpio3 19 0>;
@@ -91,14 +95,14 @@
         hog {
                 pinctrl_hog: hoggrp {
                         fsl,pins = <
-                                MX6Q_PAD_NANDF_D6__GPIO2_IO06 0x80000000
-                                MX6Q_PAD_NANDF_D7__GPIO2_IO07 0x80000000
-                                MX6Q_PAD_EIM_D19__GPIO3_IO19  0x80000000
-                                MX6Q_PAD_EIM_D22__GPIO3_IO22  0x80000000
-                                MX6Q_PAD_EIM_D23__GPIO3_IO23  0x80000000
-                                MX6Q_PAD_SD3_DAT5__GPIO7_IO00 0x80000000
-                                MX6Q_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0
-                                MX6Q_PAD_GPIO_0__CCM_CLKO1    0x80000000
+                                MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000
+                                MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x80000000
+                                MX6QDL_PAD_EIM_D19__GPIO3_IO19  0x80000000
+                                MX6QDL_PAD_EIM_D22__GPIO3_IO22  0x80000000
+                                MX6QDL_PAD_EIM_D23__GPIO3_IO23  0x80000000
+                                MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000
+                                MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0
+                                MX6QDL_PAD_GPIO_0__CCM_CLKO1    0x80000000
                         >;
                 };
         };
@@ -163,7 +167,7 @@
         codec: sgtl5000@0a {
                 compatible = "fsl,sgtl5000";
                 reg = <0x0a>;
-                clocks = <&clks 169>;
+                clocks = <&clks 201>;
                 VDDA-supply = <&reg_2p5v>;
                 VDDIO-supply = <&reg_3p3v>;
         };
diff --git a/arch/arm/boot/dts/imx6q-sabresd.dts b/arch/arm/boot/dts/imx6q-sabresd.dts
index 0038228c508c..9cbdfe7a0931 100644
--- a/arch/arm/boot/dts/imx6q-sabresd.dts
+++ b/arch/arm/boot/dts/imx6q-sabresd.dts
@@ -20,21 +20,6 @@
         compatible = "fsl,imx6q-sabresd", "fsl,imx6q";
 };
 
-&iomuxc {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_hog>;
-
-        hog {
-                pinctrl_hog: hoggrp {
-                        fsl,pins = <
-                                MX6Q_PAD_GPIO_4__GPIO1_IO04   0x80000000
-                                MX6Q_PAD_GPIO_5__GPIO1_IO05   0x80000000
-                                MX6Q_PAD_NANDF_D0__GPIO2_IO00 0x80000000
-                                MX6Q_PAD_NANDF_D1__GPIO2_IO01 0x80000000
-                                MX6Q_PAD_NANDF_D2__GPIO2_IO02 0x80000000
-                                MX6Q_PAD_NANDF_D3__GPIO2_IO03 0x80000000
-                                MX6Q_PAD_GPIO_0__CCM_CLKO1    0x130b0
-                        >;
-                };
-        };
+&sata {
+        status = "okay";
 };
diff --git a/arch/arm/boot/dts/imx6q-wandboard.dts b/arch/arm/boot/dts/imx6q-wandboard.dts
new file mode 100644
index 000000000000..36be17f207b1
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-wandboard.dts
@@ -0,0 +1,26 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+/dts-v1/;
+#include "imx6q.dtsi"
+#include "imx6qdl-wandboard.dtsi"
+
+/ {
+        model = "Wandboard i.MX6 Quad Board";
+        compatible = "wand,imx6q-wandboard", "fsl,imx6q";
+
+        memory {
+                reg = <0x10000000 0x80000000>;
+        };
+};
+
+&sata {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index ba09dc32324e..f024ef28b34b 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -8,8 +8,8 @@
  *
  */
 
-#include "imx6qdl.dtsi"
 #include "imx6q-pinfunc.h"
+#include "imx6qdl.dtsi"
 
 / {
         cpus {
@@ -61,6 +61,12 @@
         };
 
         soc {
+                ocram: sram@00900000 {
+                        compatible = "mmio-sram";
+                        reg = <0x00900000 0x40000>;
+                        clocks = <&clks 142>;
+                };
+
                 aips-bus@02000000 { /* AIPS1 */
                         spba-bus@02000000 {
                                 ecspi5: ecspi@02018000 {
@@ -77,357 +83,54 @@
 
                         iomuxc: iomuxc@020e0000 {
                                 compatible = "fsl,imx6q-iomuxc";
-                                reg = <0x020e0000 0x4000>;
-
-                                /* shared pinctrl settings */
-                                audmux {
-                                        pinctrl_audmux_1: audmux-1 {
-                                                fsl,pins = <
-                                                        MX6Q_PAD_SD2_DAT0__AUD4_RXD  0x80000000
-                                                        MX6Q_PAD_SD2_DAT3__AUD4_TXC  0x80000000
-                                                        MX6Q_PAD_SD2_DAT2__AUD4_TXD  0x80000000
-                                                        MX6Q_PAD_SD2_DAT1__AUD4_TXFS 0x80000000
-                                                >;
-                                        };
-
-                                        pinctrl_audmux_2: audmux-2 {
-                                                fsl,pins = <
-                                                        MX6Q_PAD_CSI0_DAT7__AUD3_RXD  0x80000000
-                                                        MX6Q_PAD_CSI0_DAT4__AUD3_TXC  0x80000000
-                                                        MX6Q_PAD_CSI0_DAT5__AUD3_TXD  0x80000000
-                                                        MX6Q_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
-                                                >;
-                                        };
-                                };
-
-                                ecspi1 {
-                                        pinctrl_ecspi1_1: ecspi1grp-1 {
-                                                fsl,pins = <
-                                                        MX6Q_PAD_EIM_D17__ECSPI1_MISO 0x100b1
-                                                        MX6Q_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
-                                                        MX6Q_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
-                                                >;
-                                        };
-                                };
-
-                                ecspi3 {
-                                        pinctrl_ecspi3_1: ecspi3grp-1 {
-                                                fsl,pins = <
-                                                        MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
-                                                        MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
-                                                        MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
-                                                >;
-                                        };
-                                };
-
-                                enet {
-                                        pinctrl_enet_1: enetgrp-1 {
-                                                fsl,pins = <
-                                                        MX6Q_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
-                                                        MX6Q_PAD_ENET_MDC__ENET_MDC         0x1b0b0
-                                                        MX6Q_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
-                                                        MX6Q_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
-                                                        MX6Q_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
-                                                        MX6Q_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
-                                                        MX6Q_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
-                                                        MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
-                                                        MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
-                                                        MX6Q_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
-                                                        MX6Q_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
-                                                        MX6Q_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
-                                                        MX6Q_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
-                                                        MX6Q_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
-                                                        MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
-                                                        MX6Q_PAD_GPIO_16__ENET_REF_CLK      0x4001b0a8
-                                                >;
-                                        };
-
-                                        pinctrl_enet_2: enetgrp-2 {
-                                                fsl,pins = <
-                                                        MX6Q_PAD_KEY_COL1__ENET_MDIO        0x1b0b0
-                                                        MX6Q_PAD_KEY_COL2__ENET_MDC         0x1b0b0
-                                                        MX6Q_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
-                                                        MX6Q_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
-                                                        MX6Q_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
-                                                        MX6Q_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
-                                                        MX6Q_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
-                                                        MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
-                                                        MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
-                                                        MX6Q_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
-                                                        MX6Q_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
-                                                        MX6Q_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
-                                                        MX6Q_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
-                                                        MX6Q_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
-                                                        MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
-                                                >;
-                                        };
-
-                                        pinctrl_enet_3: enetgrp-3 {
-                                                fsl,pins = <
-                                                        MX6Q_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
-                                                        MX6Q_PAD_ENET_MDC__ENET_MDC         0x1b0b0
-                                                        MX6Q_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
-                                                        MX6Q_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
-                                                        MX6Q_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
-                                                        MX6Q_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
-                                                        MX6Q_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
-                                                        MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
-                                                        MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
-                                                        MX6Q_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
-                                                        MX6Q_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
-                                                        MX6Q_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
-                                                        MX6Q_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
-                                                        MX6Q_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
-                                                        MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
-                                                        MX6Q_PAD_ENET_TX_EN__ENET_TX_EN     0x1b0b0
-                                                >;
-                                        };
-                                };
-
-                                gpmi-nand {
-                                        pinctrl_gpmi_nand_1: gpmi-nand-1 {
-                                                fsl,pins = <
-                                                        MX6Q_PAD_NANDF_CLE__NAND_CLE     0xb0b1
-                                                        MX6Q_PAD_NANDF_ALE__NAND_ALE     0xb0b1
-                                                        MX6Q_PAD_NANDF_WP_B__NAND_WP_B   0xb0b1
-                                                        MX6Q_PAD_NANDF_RB0__NAND_READY_B 0xb000
-                                                        MX6Q_PAD_NANDF_CS0__NAND_CE0_B   0xb0b1
-                                                        MX6Q_PAD_NANDF_CS1__NAND_CE1_B   0xb0b1
-                                                        MX6Q_PAD_SD4_CMD__NAND_RE_B      0xb0b1
-                                                        MX6Q_PAD_SD4_CLK__NAND_WE_B      0xb0b1
-                                                        MX6Q_PAD_NANDF_D0__NAND_DATA00   0xb0b1
-                                                        MX6Q_PAD_NANDF_D1__NAND_DATA01   0xb0b1
-                                                        MX6Q_PAD_NANDF_D2__NAND_DATA02   0xb0b1
-                                                        MX6Q_PAD_NANDF_D3__NAND_DATA03   0xb0b1
-                                                        MX6Q_PAD_NANDF_D4__NAND_DATA04   0xb0b1
-                                                        MX6Q_PAD_NANDF_D5__NAND_DATA05   0xb0b1
-                                                        MX6Q_PAD_NANDF_D6__NAND_DATA06   0xb0b1
-                                                        MX6Q_PAD_NANDF_D7__NAND_DATA07   0xb0b1
-                                                        MX6Q_PAD_SD4_DAT0__NAND_DQS      0x00b1
-                                                >;
-                                        };
-                                };
-
-                                i2c1 {
-                                        pinctrl_i2c1_1: i2c1grp-1 {
-                                                fsl,pins = <
-                                                        MX6Q_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
-                                                        MX6Q_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
-                                                >;
-                                        };
 
-                                        pinctrl_i2c1_2: i2c1grp-2 {
-                                                fsl,pins = <
-                                                        MX6Q_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
-                                                        MX6Q_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
-                                                >;
-                                        };
-                                };
-
-                                i2c2 {
-                                        pinctrl_i2c2_1: i2c2grp-1 {
-                                                fsl,pins = <
-                                                        MX6Q_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
-                                                        MX6Q_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
+                                ipu2 {
+                                        pinctrl_ipu2_1: ipu2grp-1 {
+                                                fsl,pins = <
+                                                        MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x10
+                                                        MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15       0x10
+                                                        MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02        0x10
+                                                        MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03        0x10
+                                                        MX6QDL_PAD_DI0_PIN4__IPU2_DI0_PIN04        0x80000000
+                                                        MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00   0x10
+                                                        MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01   0x10
+                                                        MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02   0x10
+                                                        MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03   0x10
+                                                        MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04   0x10
+                                                        MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05   0x10
+                                                        MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06   0x10
+                                                        MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07   0x10
+                                                        MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08   0x10
+                                                        MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09   0x10
+                                                        MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10  0x10
+                                                        MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11  0x10
+                                                        MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12  0x10
+                                                        MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13  0x10
+                                                        MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14  0x10
+                                                        MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15  0x10
+                                                        MX6QDL_PAD_DISP0_DAT16__IPU2_DISP0_DATA16  0x10
+                                                        MX6QDL_PAD_DISP0_DAT17__IPU2_DISP0_DATA17  0x10
+                                                        MX6QDL_PAD_DISP0_DAT18__IPU2_DISP0_DATA18  0x10
+                                                        MX6QDL_PAD_DISP0_DAT19__IPU2_DISP0_DATA19  0x10
+                                                        MX6QDL_PAD_DISP0_DAT20__IPU2_DISP0_DATA20  0x10
+                                                        MX6QDL_PAD_DISP0_DAT21__IPU2_DISP0_DATA21  0x10
+                                                        MX6QDL_PAD_DISP0_DAT22__IPU2_DISP0_DATA22  0x10
+                                                        MX6QDL_PAD_DISP0_DAT23__IPU2_DISP0_DATA23  0x10
                                                 >;
                                         };
                                 };
-
-                                i2c3 {
-                                        pinctrl_i2c3_1: i2c3grp-1 {
-                                                fsl,pins = <
-                                                        MX6Q_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
-                                                        MX6Q_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
-                                                >;
-                                        };
-                                };
-
-                                uart1 {
-                                        pinctrl_uart1_1: uart1grp-1 {
-                                                fsl,pins = <
-                                                        MX6Q_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
-                                                        MX6Q_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
-                                                >;
-                                        };
-                                };
-
-                                uart2 {
-                                        pinctrl_uart2_1: uart2grp-1 {
-                                                fsl,pins = <
-                                                        MX6Q_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
-                                                        MX6Q_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
-                                                >;
-                                        };
-                                };
-
-                                uart4 {
-                                        pinctrl_uart4_1: uart4grp-1 {
-                                                fsl,pins = <
-                                                        MX6Q_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
-                                                        MX6Q_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
-                                                >;
-                                        };
-                                };
-
-                                usbotg {
-                                        pinctrl_usbotg_1: usbotggrp-1 {
-                                                fsl,pins = <
-                                                        MX6Q_PAD_GPIO_1__USB_OTG_ID 0x17059
-                                                >;
-                                        };
-
-                                        pinctrl_usbotg_2: usbotggrp-2 {
-                                                fsl,pins = <
-                                                        MX6Q_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
-                                                >;
-                                        };
-                                };
-
-                                usdhc2 {
-                                        pinctrl_usdhc2_1: usdhc2grp-1 {
-                                                fsl,pins = <
-                                                        MX6Q_PAD_SD2_CMD__SD2_CMD    0x17059
-                                                        MX6Q_PAD_SD2_CLK__SD2_CLK    0x10059
-                                                        MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x17059
-                                                        MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x17059
-                                                        MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x17059
-                                                        MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x17059
-                                                        MX6Q_PAD_NANDF_D4__SD2_DATA4 0x17059
-                                                        MX6Q_PAD_NANDF_D5__SD2_DATA5 0x17059
-                                                        MX6Q_PAD_NANDF_D6__SD2_DATA6 0x17059
-                                                        MX6Q_PAD_NANDF_D7__SD2_DATA7 0x17059
-                                                >;
-                                        };
-
-                                        pinctrl_usdhc2_2: usdhc2grp-2 {
-                                                fsl,pins = <
-                                                        MX6Q_PAD_SD2_CMD__SD2_CMD    0x17059
-                                                        MX6Q_PAD_SD2_CLK__SD2_CLK    0x10059
-                                                        MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x17059
-                                                        MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x17059
-                                                        MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x17059
-                                                        MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x17059
-                                                >;
-                                        };
-                                };
-
-                                usdhc3 {
-                                        pinctrl_usdhc3_1: usdhc3grp-1 {
-                                                fsl,pins = <
-                                                        MX6Q_PAD_SD3_CMD__SD3_CMD    0x17059
-                                                        MX6Q_PAD_SD3_CLK__SD3_CLK    0x10059
-                                                        MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x17059
-                                                        MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x17059
-                                                        MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x17059
-                                                        MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x17059
-                                                        MX6Q_PAD_SD3_DAT4__SD3_DATA4 0x17059
-                                                        MX6Q_PAD_SD3_DAT5__SD3_DATA5 0x17059
-                                                        MX6Q_PAD_SD3_DAT6__SD3_DATA6 0x17059
-                                                        MX6Q_PAD_SD3_DAT7__SD3_DATA7 0x17059
-                                                >;
-                                        };
-
-                                        pinctrl_usdhc3_2: usdhc3grp-2 {
-                                                fsl,pins = <
-                                                        MX6Q_PAD_SD3_CMD__SD3_CMD    0x17059
-                                                        MX6Q_PAD_SD3_CLK__SD3_CLK    0x10059
-                                                        MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x17059
-                                                        MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x17059
-                                                        MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x17059
-                                                        MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x17059
-                                                >;
-                                        };
-                                };
-
-                                usdhc4 {
-                                        pinctrl_usdhc4_1: usdhc4grp-1 {
-                                                fsl,pins = <
-                                                        MX6Q_PAD_SD4_CMD__SD4_CMD    0x17059
-                                                        MX6Q_PAD_SD4_CLK__SD4_CLK    0x10059
-                                                        MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x17059
-                                                        MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x17059
-                                                        MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x17059
-                                                        MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x17059
-                                                        MX6Q_PAD_SD4_DAT4__SD4_DATA4 0x17059
-                                                        MX6Q_PAD_SD4_DAT5__SD4_DATA5 0x17059
-                                                        MX6Q_PAD_SD4_DAT6__SD4_DATA6 0x17059
-                                                        MX6Q_PAD_SD4_DAT7__SD4_DATA7 0x17059
-                                                >;
-                                        };
-
-                                        pinctrl_usdhc4_2: usdhc4grp-2 {
-                                                fsl,pins = <
-                                                        MX6Q_PAD_SD4_CMD__SD4_CMD    0x17059
-                                                        MX6Q_PAD_SD4_CLK__SD4_CLK    0x10059
-                                                        MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x17059
-                                                        MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x17059
-                                                        MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x17059
-                                                        MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x17059
-                                                >;
-                                        };
-                                };
-
-                                weim {
-                                        pinctrl_weim_cs0_1: weim_cs0grp-1 {
-                                                fsl,pins = <
-                                                        MX6Q_PAD_EIM_CS0__EIM_CS0_B   0xb0b1
-                                                >;
-                                        };
-
-                                        pinctrl_weim_nor_1: weimnorgrp-1 {
-                                                fsl,pins = <
-                                                        MX6Q_PAD_EIM_OE__EIM_OE_B     0xb0b1
-                                                        MX6Q_PAD_EIM_RW__EIM_RW       0xb0b1
-                                                        MX6Q_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
-                                                        /* data */
-                                                        MX6Q_PAD_EIM_D16__EIM_DATA16 0x1b0b0
-                                                        MX6Q_PAD_EIM_D17__EIM_DATA17 0x1b0b0
-                                                        MX6Q_PAD_EIM_D18__EIM_DATA18 0x1b0b0
-                                                        MX6Q_PAD_EIM_D19__EIM_DATA19 0x1b0b0
-                                                        MX6Q_PAD_EIM_D20__EIM_DATA20 0x1b0b0
-                                                        MX6Q_PAD_EIM_D21__EIM_DATA21 0x1b0b0
-                                                        MX6Q_PAD_EIM_D22__EIM_DATA22 0x1b0b0
-                                                        MX6Q_PAD_EIM_D23__EIM_DATA23 0x1b0b0
-                                                        MX6Q_PAD_EIM_D24__EIM_DATA24 0x1b0b0
-                                                        MX6Q_PAD_EIM_D25__EIM_DATA25 0x1b0b0
-                                                        MX6Q_PAD_EIM_D26__EIM_DATA26 0x1b0b0
-                                                        MX6Q_PAD_EIM_D27__EIM_DATA27 0x1b0b0
-                                                        MX6Q_PAD_EIM_D28__EIM_DATA28 0x1b0b0
-                                                        MX6Q_PAD_EIM_D29__EIM_DATA29 0x1b0b0
-                                                        MX6Q_PAD_EIM_D30__EIM_DATA30 0x1b0b0
-                                                        MX6Q_PAD_EIM_D31__EIM_DATA31 0x1b0b0
-                                                        /* address */
-                                                        MX6Q_PAD_EIM_A23__EIM_ADDR23 0xb0b1
-                                                        MX6Q_PAD_EIM_A22__EIM_ADDR22 0xb0b1
-                                                        MX6Q_PAD_EIM_A21__EIM_ADDR21 0xb0b1
-                                                        MX6Q_PAD_EIM_A20__EIM_ADDR20 0xb0b1
-                                                        MX6Q_PAD_EIM_A19__EIM_ADDR19 0xb0b1
-                                                        MX6Q_PAD_EIM_A18__EIM_ADDR18 0xb0b1
-                                                        MX6Q_PAD_EIM_A17__EIM_ADDR17 0xb0b1
-                                                        MX6Q_PAD_EIM_A16__EIM_ADDR16 0xb0b1
-                                                        MX6Q_PAD_EIM_DA15__EIM_AD15  0xb0b1
-                                                        MX6Q_PAD_EIM_DA14__EIM_AD14  0xb0b1
-                                                        MX6Q_PAD_EIM_DA13__EIM_AD13  0xb0b1
-                                                        MX6Q_PAD_EIM_DA12__EIM_AD12  0xb0b1
-                                                        MX6Q_PAD_EIM_DA11__EIM_AD11  0xb0b1
-                                                        MX6Q_PAD_EIM_DA10__EIM_AD10  0xb0b1
-                                                        MX6Q_PAD_EIM_DA9__EIM_AD09   0xb0b1
-                                                        MX6Q_PAD_EIM_DA8__EIM_AD08   0xb0b1
-                                                        MX6Q_PAD_EIM_DA7__EIM_AD07   0xb0b1
-                                                        MX6Q_PAD_EIM_DA6__EIM_AD06   0xb0b1
-                                                        MX6Q_PAD_EIM_DA5__EIM_AD05   0xb0b1
-                                                        MX6Q_PAD_EIM_DA4__EIM_AD04   0xb0b1
-                                                        MX6Q_PAD_EIM_DA3__EIM_AD03   0xb0b1
-                                                        MX6Q_PAD_EIM_DA2__EIM_AD02   0xb0b1
-                                                        MX6Q_PAD_EIM_DA1__EIM_AD01   0xb0b1
-                                                        MX6Q_PAD_EIM_DA0__EIM_AD00   0xb0b1
-                                                >;
-                                        };
-
-                                };
                         };
                 };
 
+                sata: sata@02200000 {
+                        compatible = "fsl,imx6q-ahci";
+                        reg = <0x02200000 0x4000>;
+                        interrupts = <0 39 0x04>;
+                        clocks =  <&clks 154>, <&clks 187>, <&clks 105>;
+                        clock-names = "sata", "sata_ref", "ahb";
+                        status = "disabled";
+                };
+
                 ipu2: ipu@02800000 {
                         #crtc-cells = <1>;
                         compatible = "fsl,imx6q-ipu";
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index e994011220e7..1cbbc5160d27 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -45,6 +45,28 @@
         status = "okay";
 };
 
+&iomuxc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_hog>;
+
+        hog {
+                pinctrl_hog: hoggrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
+                                MX6QDL_PAD_SD2_DAT2__GPIO1_IO13  0x80000000
+                        >;
+                };
+        };
+
+        ecspi1 {
+                pinctrl_ecspi1_sabreauto: ecspi1-sabreauto {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
+                        >;
+                };
+        };
+};
+
 &uart4 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart4_1>;
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index 6e5dfdb32416..39eafc222a2e 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -27,6 +27,15 @@
                         enable-active-high;
                 };
 
+                reg_usb_h1_vbus: usb_h1_vbus {
+                        compatible = "regulator-fixed";
+                        regulator-name = "usb_h1_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio1 29 0>;
+                        enable-active-high;
+                };
+
                 reg_audio: wm8962_supply {
                         compatible = "regulator-fixed";
                         regulator-name = "wm8962-supply";
@@ -41,12 +50,14 @@
                 volume-up {
                         label = "Volume Up";
                         gpios = <&gpio1 4 0>;
+                        gpio-key,wakeup;
                         linux,code = <115>; /* KEY_VOLUMEUP */
                 };
 
                 volume-down {
                         label = "Volume Down";
                         gpios = <&gpio1 5 0>;
+                        gpio-key,wakeup;
                         linux,code = <114>; /* KEY_VOLUMEDOWN */
                 };
         };
@@ -77,6 +88,22 @@
         status = "okay";
 };
 
+&ecspi1 {
+        fsl,spi-num-chipselects = <1>;
+        cs-gpios = <&gpio4 9 0>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_ecspi1_2>;
+        status = "okay";
+
+        flash: m25p80@0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "st,m25p32";
+                spi-max-frequency = <20000000>;
+                reg = <0>;
+        };
+};
+
 &fec {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_enet_1>;
@@ -93,7 +120,7 @@
         codec: wm8962@1a {
                 compatible = "wlf,wm8962";
                 reg = <0x1a>;
-                clocks = <&clks 169>;
+                clocks = <&clks 201>;
                 DCVDD-supply = <&reg_audio>;
                 DBVDD-supply = <&reg_audio>;
                 AVDD-supply = <&reg_audio>;
@@ -113,6 +140,68 @@
        };
 };
 
+&i2c3 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c3_2>;
+        status = "okay";
+
+        egalax_ts@04 {
+                compatible = "eeti,egalax_ts";
+                reg = <0x04>;
+                interrupt-parent = <&gpio6>;
+                interrupts = <7 2>;
+                wakeup-gpios = <&gpio6 7 0>;
+        };
+};
+
+&iomuxc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_hog>;
+
+        hog {
+                pinctrl_hog: hoggrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_GPIO_4__GPIO1_IO04   0x80000000
+                                MX6QDL_PAD_GPIO_5__GPIO1_IO05   0x80000000
+                                MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000
+                                MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000
+                                MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000
+                                MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000
+                                MX6QDL_PAD_GPIO_0__CCM_CLKO1    0x130b0
+                                MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000
+                                MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
+                                MX6QDL_PAD_EIM_D22__GPIO3_IO22  0x80000000
+                        >;
+                };
+        };
+};
+
+&ldb {
+        status = "okay";
+
+        lvds-channel@1 {
+                fsl,data-mapping = "spwg";
+                fsl,data-width = <18>;
+                status = "okay";
+
+                display-timings {
+                        native-mode = <&timing0>;
+                        timing0: hsd100pxn1 {
+                                clock-frequency = <65000000>;
+                                hactive = <1024>;
+                                vactive = <768>;
+                                hback-porch = <220>;
+                                hfront-porch = <40>;
+                                vback-porch = <21>;
+                                vfront-porch = <7>;
+                                hsync-len = <60>;
+                                vsync-len = <10>;
+                        };
+                };
+        };
+};
+
 &ssi2 {
         fsl,mode = "i2s-slave";
         status = "okay";
@@ -125,6 +214,7 @@
 };
 
 &usbh1 {
+        vbus-supply = <&reg_usb_h1_vbus>;
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
new file mode 100644
index 000000000000..a55113e65bcb
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
@@ -0,0 +1,137 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+/ {
+        regulators {
+                compatible = "simple-bus";
+
+                reg_2p5v: 2p5v {
+                        compatible = "regulator-fixed";
+                        regulator-name = "2P5V";
+                        regulator-min-microvolt = <2500000>;
+                        regulator-max-microvolt = <2500000>;
+                        regulator-always-on;
+                };
+
+                reg_3p3v: 3p3v {
+                        compatible = "regulator-fixed";
+                        regulator-name = "3P3V";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                };
+        };
+
+        sound {
+                compatible = "fsl,imx6-wandboard-sgtl5000",
+                             "fsl,imx-audio-sgtl5000";
+                model = "imx6-wandboard-sgtl5000";
+                ssi-controller = <&ssi1>;
+                audio-codec = <&codec>;
+                audio-routing =
+                        "MIC_IN", "Mic Jack",
+                        "Mic Jack", "Mic Bias",
+                        "Headphone Jack", "HP_OUT";
+                mux-int-port = <1>;
+                mux-ext-port = <3>;
+        };
+};
+
+&audmux {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audmux_2>;
+        status = "okay";
+};
+
+&i2c2 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c2_2>;
+        status = "okay";
+
+        codec: sgtl5000@0a {
+                compatible = "fsl,sgtl5000";
+                reg = <0x0a>;
+                clocks = <&clks 201>;
+                VDDA-supply = <&reg_2p5v>;
+                VDDIO-supply = <&reg_3p3v>;
+        };
+};
+
+&iomuxc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_hog>;
+
+        hog {
+                pinctrl_hog: hoggrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_GPIO_0__CCM_CLKO1     0x130b0
+                                MX6QDL_PAD_GPIO_2__GPIO1_IO02    0x80000000
+                                MX6QDL_PAD_EIM_DA9__GPIO3_IO09   0x80000000
+                                MX6QDL_PAD_EIM_EB1__GPIO2_IO29   0x80000000 /* WL_REF_ON */
+                                MX6QDL_PAD_EIM_A25__GPIO5_IO02   0x80000000 /* WL_RST_N */
+                                MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* WL_REG_ON */
+                                MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* WL_HOST_WAKE */
+                                MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* WL_WAKE */
+                        >;
+                };
+        };
+};
+
+&fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_enet_1>;
+        phy-mode = "rgmii";
+        status = "okay";
+};
+
+&ssi1 {
+        fsl,mode = "i2s-slave";
+        status = "okay";
+};
+
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1_1>;
+        status = "okay";
+};
+
+&uart3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart3_2>;
+        fsl,uart-has-rtscts;
+        status = "okay";
+};
+
+&usbh1 {
+        status = "okay";
+};
+
+&usdhc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc1_2>;
+        cd-gpios = <&gpio1 2 0>;
+        status = "okay";
+};
+
+&usdhc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc2_2>;
+        non-removable;
+        status = "okay";
+};
+
+&usdhc3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc3_2>;
+        cd-gpios = <&gpio3 9 0>;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index f21d259080fd..ccd55c2fdb67 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -14,11 +14,6 @@
 
 / {
         aliases {
-                serial0 = &uart1;
-                serial1 = &uart2;
-                serial2 = &uart3;
-                serial3 = &uart4;
-                serial4 = &uart5;
                 gpio0 = &gpio1;
                 gpio1 = &gpio2;
                 gpio2 = &gpio3;
@@ -26,6 +21,18 @@
                 gpio4 = &gpio5;
                 gpio5 = &gpio6;
                 gpio6 = &gpio7;
+                i2c0 = &i2c1;
+                i2c1 = &i2c2;
+                i2c2 = &i2c3;
+                serial0 = &uart1;
+                serial1 = &uart2;
+                serial2 = &uart3;
+                serial3 = &uart4;
+                serial4 = &uart5;
+                spi0 = &ecspi1;
+                spi1 = &ecspi2;
+                spi2 = &ecspi3;
+                spi3 = &ecspi4;
         };
 
         intc: interrupt-controller@00a01000 {
@@ -81,15 +88,14 @@
                         #size-cells = <1>;
                         reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
                         reg-names = "gpmi-nand", "bch";
-                        interrupts = <0 13 0x04>, <0 15 0x04>;
-                        interrupt-names = "gpmi-dma", "bch";
+                        interrupts = <0 15 0x04>;
+                        interrupt-names = "bch";
                         clocks = <&clks 152>, <&clks 153>, <&clks 151>,
                                  <&clks 150>, <&clks 149>;
                         clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
                                       "gpmi_bch_apb", "per1_bch";
                         dmas = <&dma_apbh 0>;
                         dma-names = "rx-tx";
-                        fsl,gpmi-dma-channel = <0>;
                         status = "disabled";
                 };
 
@@ -184,6 +190,8 @@
                                         interrupts = <0 26 0x04>;
                                         clocks = <&clks 160>, <&clks 161>;
                                         clock-names = "ipg", "per";
+                                        dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
+                                        dma-names = "rx", "tx";
                                         status = "disabled";
                                 };
 
@@ -197,6 +205,9 @@
                                         reg = <0x02028000 0x4000>;
                                         interrupts = <0 46 0x04>;
                                         clocks = <&clks 178>;
+                                        dmas = <&sdma 37 1 0>,
+                                               <&sdma 38 1 0>;
+                                        dma-names = "rx", "tx";
                                         fsl,fifo-depth = <15>;
                                         fsl,ssi-dma-events = <38 37>;
                                         status = "disabled";
@@ -207,6 +218,9 @@
                                         reg = <0x0202c000 0x4000>;
                                         interrupts = <0 47 0x04>;
                                         clocks = <&clks 179>;
+                                        dmas = <&sdma 41 1 0>,
+                                               <&sdma 42 1 0>;
+                                        dma-names = "rx", "tx";
                                         fsl,fifo-depth = <15>;
                                         fsl,ssi-dma-events = <42 41>;
                                         status = "disabled";
@@ -217,6 +231,9 @@
                                         reg = <0x02030000 0x4000>;
                                         interrupts = <0 48 0x04>;
                                         clocks = <&clks 180>;
+                                        dmas = <&sdma 45 1 0>,
+                                               <&sdma 46 1 0>;
+                                        dma-names = "rx", "tx";
                                         fsl,fifo-depth = <15>;
                                         fsl,ssi-dma-events = <46 45>;
                                         status = "disabled";
@@ -278,17 +295,23 @@
                         };
 
                         can1: flexcan@02090000 {
+                                compatible = "fsl,imx6q-flexcan";
                                 reg = <0x02090000 0x4000>;
                                 interrupts = <0 110 0x04>;
+                                clocks = <&clks 108>, <&clks 109>;
+                                clock-names = "ipg", "per";
                         };
 
                         can2: flexcan@02094000 {
+                                compatible = "fsl,imx6q-flexcan";
                                 reg = <0x02094000 0x4000>;
                                 interrupts = <0 111 0x04>;
+                                clocks = <&clks 110>, <&clks 111>;
+                                clock-names = "ipg", "per";
                         };
 
                         gpt: gpt@02098000 {
-                                compatible = "fsl,imx6q-gpt";
+                                compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
                                 reg = <0x02098000 0x4000>;
                                 interrupts = <0 55 0x04>;
                                 clocks = <&clks 119>, <&clks 120>;
@@ -491,6 +514,13 @@
                                 };
                         };
 
+                        tempmon: tempmon {
+                                compatible = "fsl,imx6q-tempmon";
+                                interrupts = <0 49 0x04>;
+                                fsl,tempmon = <&anatop>;
+                                fsl,tempmon-data = <&ocotp>;
+                        };
+
                         usbphy1: usbphy@020c9000 {
                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
                                 reg = <0x020c9000 0x1000>;
@@ -546,6 +576,713 @@
                                 reg = <0x020e0000 0x38>;
                         };
 
+                        iomuxc: iomuxc@020e0000 {
+                                compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
+                                reg = <0x020e0000 0x4000>;
+
+                                audmux {
+                                        pinctrl_audmux_1: audmux-1 {
+                                                fsl,pins = <
+                                                        MX6QDL_PAD_SD2_DAT0__AUD4_RXD  0x80000000
+                                                        MX6QDL_PAD_SD2_DAT3__AUD4_TXC  0x80000000
+                                                        MX6QDL_PAD_SD2_DAT2__AUD4_TXD  0x80000000
+                                                        MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x80000000
+                                                >;
+                                        };
+
+                                        pinctrl_audmux_2: audmux-2 {
+                                                fsl,pins = <
+                                                        MX6QDL_PAD_CSI0_DAT7__AUD3_RXD  0x80000000
+                                                        MX6QDL_PAD_CSI0_DAT4__AUD3_TXC  0x80000000
+                                                        MX6QDL_PAD_CSI0_DAT5__AUD3_TXD  0x80000000
+                                                        MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
+                                                >;
+                                        };
+
+                                        pinctrl_audmux_3: audmux-3 {
+                                                fsl,pins = <
+                                                        MX6QDL_PAD_DISP0_DAT16__AUD5_TXC  0x80000000
+                                                        MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x80000000
+                                                        MX6QDL_PAD_DISP0_DAT19__AUD5_RXD  0x80000000
+                                                >;
+                                        };
+                                };
+
+                                ecspi1 {
+                                        pinctrl_ecspi1_1: ecspi1grp-1 {
+                                                fsl,pins = <
+                                                        MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
+                                                        MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
+                                                        MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
+                                                >;
+                                        };
+
+                                        pinctrl_ecspi1_2: ecspi1grp-2 {
+                                                fsl,pins = <
+                                                        MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
+                                                        MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
+                                                        MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
+                                                >;
+                                        };
+                                };
+
+                                ecspi3 {
+                                        pinctrl_ecspi3_1: ecspi3grp-1 {
+                                                fsl,pins = <
+                                                        MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
+                                                        MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
+                                                        MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
+                                                >;
+                                        };
+                                };
+
+                                enet {
+                                        pinctrl_enet_1: enetgrp-1 {
+                                                fsl,pins = <
+                                                        MX6QDL_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
+                                                        MX6QDL_PAD_ENET_MDC__ENET_MDC         0x1b0b0
+                                                        MX6QDL_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
+                                                        MX6QDL_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
+                                                        MX6QDL_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
+                                                        MX6QDL_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
+                                                        MX6QDL_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
+                                                        MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+                                                        MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
+                                                        MX6QDL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
+                                                        MX6QDL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
+                                                        MX6QDL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
+                                                        MX6QDL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
+                                                        MX6QDL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
+                                                        MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+                                                        MX6QDL_PAD_GPIO_16__ENET_REF_CLK      0x4001b0a8
+                                                >;
+                                        };
+
+                                        pinctrl_enet_2: enetgrp-2 {
+                                                fsl,pins = <
+                                                        MX6QDL_PAD_KEY_COL1__ENET_MDIO        0x1b0b0
+                                                        MX6QDL_PAD_KEY_COL2__ENET_MDC         0x1b0b0
+                                                        MX6QDL_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
+                                                        MX6QDL_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
+                                                        MX6QDL_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
+                                                        MX6QDL_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
+                                                        MX6QDL_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
+                                                        MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+                                                        MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
+                                                        MX6QDL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
+                                                        MX6QDL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
+                                                        MX6QDL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
+                                                        MX6QDL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
+                                                        MX6QDL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
+                                                        MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+                                                >;
+                                        };
+
+                                        pinctrl_enet_3: enetgrp-3 {
+                                                fsl,pins = <
+                                                        MX6QDL_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
+                                                        MX6QDL_PAD_ENET_MDC__ENET_MDC         0x1b0b0
+                                                        MX6QDL_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
+                                                        MX6QDL_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
+                                                        MX6QDL_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
+                                                        MX6QDL_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
+                                                        MX6QDL_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
+                                                        MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+                                                        MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
+                                                        MX6QDL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
+                                                        MX6QDL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
+                                                        MX6QDL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
+                                                        MX6QDL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
+                                                        MX6QDL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
+                                                        MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+                                                        MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN     0x1b0b0
+                                                >;
+                                        };
+                                };
+
+                                esai {
+                                        pinctrl_esai_1: esaigrp-1 {
+                                                fsl,pins = <
+                                                        MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1b030
+                                                        MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK  0x1b030
+                                                        MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS     0x1b030
+                                                        MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2  0x1b030
+                                                        MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3   0x1b030
+                                                        MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1   0x1b030
+                                                        MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0    0x1b030
+                                                        MX6QDL_PAD_NANDF_CS2__ESAI_TX0       0x1b030
+                                                        MX6QDL_PAD_NANDF_CS3__ESAI_TX1       0x1b030
+                                                >;
+                                        };
+
+                                        pinctrl_esai_2: esaigrp-2 {
+                                                fsl,pins = <
+                                                        MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
+                                                        MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS    0x1b030
+                                                        MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
+                                                        MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3     0x1b030
+                                                        MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1  0x1b030
+                                                        MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0   0x1b030
+                                                        MX6QDL_PAD_GPIO_17__ESAI_TX0        0x1b030
+                                                        MX6QDL_PAD_NANDF_CS3__ESAI_TX1      0x1b030
+                                                        MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK   0x1b030
+                                                        MX6QDL_PAD_GPIO_9__ESAI_RX_FS       0x1b030
+                                                >;
+                                        };
+                                };
+
+                                flexcan1 {
+                                        pinctrl_flexcan1_1: flexcan1grp-1 {
+                                                fsl,pins = <
+                                                        MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
+                                                        MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000
+                                                >;
+                                        };
+
+                                        pinctrl_flexcan1_2: flexcan1grp-2 {
+                                                fsl,pins = <
+                                                        MX6QDL_PAD_GPIO_7__FLEXCAN1_TX   0x80000000
+                                                        MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
+                                                >;
+                                        };
+                                };
+
+                                flexcan2 {
+                                        pinctrl_flexcan2_1: flexcan2grp-1 {
+                                                fsl,pins = <
+                                                        MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000
+                                                        MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000
+                                                >;
+                                        };
+                                };
+
+                                gpmi-nand {
+                                        pinctrl_gpmi_nand_1: gpmi-nand-1 {
+                                                fsl,pins = <
+                                                        MX6QDL_PAD_NANDF_CLE__NAND_CLE     0xb0b1
+                                                        MX6QDL_PAD_NANDF_ALE__NAND_ALE     0xb0b1
+                                                        MX6QDL_PAD_NANDF_WP_B__NAND_WP_B   0xb0b1
+                                                        MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
+                                                        MX6QDL_PAD_NANDF_CS0__NAND_CE0_B   0xb0b1
+                                                        MX6QDL_PAD_NANDF_CS1__NAND_CE1_B   0xb0b1
+                                                        MX6QDL_PAD_SD4_CMD__NAND_RE_B      0xb0b1
+                                                        MX6QDL_PAD_SD4_CLK__NAND_WE_B      0xb0b1
+                                                        MX6QDL_PAD_NANDF_D0__NAND_DATA00   0xb0b1
+                                                        MX6QDL_PAD_NANDF_D1__NAND_DATA01   0xb0b1
+                                                        MX6QDL_PAD_NANDF_D2__NAND_DATA02   0xb0b1
+                                                        MX6QDL_PAD_NANDF_D3__NAND_DATA03   0xb0b1
+                                                        MX6QDL_PAD_NANDF_D4__NAND_DATA04   0xb0b1
+                                                        MX6QDL_PAD_NANDF_D5__NAND_DATA05   0xb0b1
+                                                        MX6QDL_PAD_NANDF_D6__NAND_DATA06   0xb0b1
+                                                        MX6QDL_PAD_NANDF_D7__NAND_DATA07   0xb0b1
+                                                        MX6QDL_PAD_SD4_DAT0__NAND_DQS      0x00b1
+                                                >;
+                                        };
+                                };
+
+                                hdmi_hdcp {
+                                        pinctrl_hdmi_hdcp_1: hdmihdcpgrp-1 {
+                                                fsl,pins = <
+                                                        MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1
+                                                        MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
+                                                >;
+                                        };
+
+                                        pinctrl_hdmi_hdcp_2: hdmihdcpgrp-2 {
+                                                fsl,pins = <
+                                                        MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1
+                                                        MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1
+                                                >;
+                                        };
+
+                                        pinctrl_hdmi_hdcp_3: hdmihdcpgrp-3 {
+                                                fsl,pins = <
+                                                        MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL  0x4001b8b1
+                                                        MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
+                                                >;
+                                        };
+                                };
+
+                                hdmi_cec {
+                                        pinctrl_hdmi_cec_1: hdmicecgrp-1 {
+                                                fsl,pins = <
+                                                        MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
+                                                >;
+                                        };
+
+                                        pinctrl_hdmi_cec_2: hdmicecgrp-2 {
+                                                fsl,pins = <
+                                                        MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
+                                                >;
+                                        };
+                                };
+
+                                i2c1 {
+                                        pinctrl_i2c1_1: i2c1grp-1 {
+                                                fsl,pins = <
+                                                        MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
+                                                        MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+                                                >;
+                                        };
+
+                                        pinctrl_i2c1_2: i2c1grp-2 {
+                                                fsl,pins = <
+                                                        MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
+                                                        MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
+                                                >;
+                                        };
+                                };
+
+                                i2c2 {
+                                        pinctrl_i2c2_1: i2c2grp-1 {
+                                                fsl,pins = <
+                                                        MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
+                                                        MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
+                                                >;
+                                        };
+
+                                        pinctrl_i2c2_2: i2c2grp-2 {
+                                                fsl,pins = <
+                                                        MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
+                                                        MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+                                                >;
+                                        };
+
+                                        pinctrl_i2c2_3: i2c2grp-3 {
+                                                fsl,pins = <
+                                                        MX6QDL_PAD_EIM_EB2__I2C2_SCL  0x4001b8b1
+                                                        MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+                                                >;
+                                        };
+                                };
+
+                                i2c3 {
+                                        pinctrl_i2c3_1: i2c3grp-1 {
+                                                fsl,pins = <
+                                                        MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
+                                                        MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
+                                                >;
+                                        };
+
+                                        pinctrl_i2c3_2: i2c3grp-2 {
+                                                fsl,pins = <
+                                                        MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
+                                                        MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
+                                                >;
+                                        };
+
+                                        pinctrl_i2c3_3: i2c3grp-3 {
+                                                fsl,pins = <
+                                                        MX6QDL_PAD_GPIO_5__I2C3_SCL  0x4001b8b1
+                                                        MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
+                                                >;
+                                        };
+
+                                        pinctrl_i2c3_4: i2c3grp-4 {
+                                                fsl,pins = <
+                                                        MX6QDL_PAD_GPIO_3__I2C3_SCL  0x4001b8b1
+                                                        MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
+                                                >;
+                                        };
+                                };
+
+                                ipu1 {
+                                        pinctrl_ipu1_1: ipu1grp-1 {
+                                                fsl,pins = <
+                                                        MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
+                                                        MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
+                                                        MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
+                                                        MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
+                                                        MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04        0x80000000
+                                                        MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0x10
+                                                        MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
+                                                        MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
+                                                        MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
+                                                        MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
+                                                        MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
+                                                        MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
+                                                        MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
+                                                        MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
+                                                        MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
+                                                        MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10
+                                                        MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10
+                                                        MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10
+                                                        MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10
+                                                        MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10
+                                                        MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10
+                                                        MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10
+                                                        MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x10
+                                                        MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x10
+                                                        MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x10
+                                                        MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x10
+                                                        MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x10
+                                                        MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x10
+                                                        MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x10
+                                                >;
+                                        };
+
+                                        pinctrl_ipu1_2: ipu1grp-2 { /* parallel camera */
+                                                fsl,pins = <
+                                                        MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12    0x80000000
+                                                        MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13    0x80000000
+                                                        MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14    0x80000000
+                                                        MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15    0x80000000
+                                                        MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16    0x80000000
+                                                        MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17    0x80000000
+                                                        MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18    0x80000000
+                                                        MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19    0x80000000
+                                                        MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000
+                                                        MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK   0x80000000
+                                                        MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC      0x80000000
+                                                        MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC     0x80000000
+                                                >;
+                                        };
+
+                                        pinctrl_ipu1_3: ipu1grp-3 { /* parallel port 16-bit */
+                                                fsl,pins = <
+                                                        MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04   0x80000000
+                                                        MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05   0x80000000
+                                                        MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06   0x80000000
+                                                        MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07   0x80000000
+                                                        MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08   0x80000000
+                                                        MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09   0x80000000
+                                                        MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10  0x80000000
+                                                        MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11  0x80000000
+                                                        MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12  0x80000000
+                                                        MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13  0x80000000
+                                                        MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14  0x80000000
+                                                        MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15  0x80000000
+                                                        MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16  0x80000000
+                                                        MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17  0x80000000
+                                                        MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18  0x80000000
+                                                        MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19  0x80000000
+                                                        MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
+                                                        MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC    0x80000000
+                                                        MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC   0x80000000
+                                                >;
+                                        };
+                                };
+
+                                mlb {
+                                        pinctrl_mlb_1: mlbgrp-1 {
+                                                fsl,pins = <
+                                                        MX6QDL_PAD_GPIO_3__MLB_CLK  0x71
+                                                        MX6QDL_PAD_GPIO_6__MLB_SIG  0x71
+                                                        MX6QDL_PAD_GPIO_2__MLB_DATA 0x71
+                                                >;
+                                        };
+
+                                        pinctrl_mlb_2: mlbgrp-2 {
+                                                fsl,pins = <
+                                                        MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x71
+                                                        MX6QDL_PAD_GPIO_6__MLB_SIG    0x71
+                                                        MX6QDL_PAD_GPIO_2__MLB_DATA   0x71
+                                                >;
+                                        };
+                                };
+
+                                pwm0 {
+                                        pinctrl_pwm0_1: pwm0grp-1 {
+                                                fsl,pins = <
+                                                        MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
+                                                >;
+                                        };
+                                };
+
+                                pwm3 {
+                                        pinctrl_pwm3_1: pwm3grp-1 {
+                                                fsl,pins = <
+                                                        MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
+                                                >;
+                                        };
+                                };
+
+                                spdif {
+                                        pinctrl_spdif_1: spdifgrp-1 {
+                                                fsl,pins = <
+                                                        MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
+                                                >;
+                                        };
+
+                                        pinctrl_spdif_2: spdifgrp-2 {
+                                                fsl,pins = <
+                                                        MX6QDL_PAD_GPIO_16__SPDIF_IN  0x1b0b0
+                                                        MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
+                                                >;
+                                        };
+                                };
+
+                                uart1 {
+                                        pinctrl_uart1_1: uart1grp-1 {
+                                                fsl,pins = <
+                                                        MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
+                                                        MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
+                                                >;
+                                        };
+                                };
+
+                                uart2 {
+                                        pinctrl_uart2_1: uart2grp-1 {
+                                                fsl,pins = <
+                                                        MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
+                                                        MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
+                                                >;
+                                        };
+
+                                        pinctrl_uart2_2: uart2grp-2 { /* DTE mode */
+                                                fsl,pins = <
+                                                        MX6QDL_PAD_EIM_D26__UART2_RX_DATA   0x1b0b1
+                                                        MX6QDL_PAD_EIM_D27__UART2_TX_DATA   0x1b0b1
+                                                        MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1
+                                                        MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1
+                                                >;
+                                        };
+                                };
+
+                                uart3 {
+                                        pinctrl_uart3_1: uart3grp-1 {
+                                                fsl,pins = <
+                                                        MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1
+                                                        MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1
+                                                        MX6QDL_PAD_EIM_D30__UART3_CTS_B   0x1b0b1
+                                                        MX6QDL_PAD_EIM_EB3__UART3_RTS_B   0x1b0b1
+                                                >;
+                                        };
+
+                                        pinctrl_uart3_2: uart3grp-2 {
+                                                fsl,pins = <
+                                                        MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
+                                                        MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
+                                                        MX6QDL_PAD_EIM_D23__UART3_CTS_B   0x1b0b1
+                                                        MX6QDL_PAD_EIM_EB3__UART3_RTS_B   0x1b0b1
+                                                >;
+                                        };
+                                };
+
+                                uart4 {
+                                        pinctrl_uart4_1: uart4grp-1 {
+                                                fsl,pins = <
+                                                        MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
+                                                        MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
+                                                >;
+                                        };
+                                };
+
+                                usbotg {
+                                        pinctrl_usbotg_1: usbotggrp-1 {
+                                                fsl,pins = <
+                                                        MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
+                                                >;
+                                        };
+
+                                        pinctrl_usbotg_2: usbotggrp-2 {
+                                                fsl,pins = <
+                                                        MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
+                                                >;
+                                        };
+                                };
+
+                                usbh2 {
+                                        pinctrl_usbh2_1: usbh2grp-1 {
+                                                fsl,pins = <
+                                                        MX6QDL_PAD_RGMII_TXC__USB_H2_DATA      0x40013030
+                                                        MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40013030
+                                                >;
+                                        };
+
+                                        pinctrl_usbh2_2: usbh2grp-2 {
+                                                fsl,pins = <
+                                                        MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40017030
+                                                >;
+                                        };
+                                };
+
+                                usbh3 {
+                                        pinctrl_usbh3_1: usbh3grp-1 {
+                                                fsl,pins = <
+                                                        MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x40013030
+                                                        MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE  0x40013030
+                                                >;
+                                        };
+
+                                        pinctrl_usbh3_2: usbh3grp-2 {
+                                                fsl,pins = <
+                                                        MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40017030
+                                                >;
+                                        };
+                                };
+
+                                usdhc1 {
+                                        pinctrl_usdhc1_1: usdhc1grp-1 {
+                                                fsl,pins = <
+                                                        MX6QDL_PAD_SD1_CMD__SD1_CMD    0x17059
+                                                        MX6QDL_PAD_SD1_CLK__SD1_CLK    0x10059
+                                                        MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
+                                                        MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
+                                                        MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
+                                                        MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
+                                                        MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17059
+                                                        MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17059
+                                                        MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17059
+                                                        MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17059
+                                                >;
+                                        };
+
+                                        pinctrl_usdhc1_2: usdhc1grp-2 {
+                                                fsl,pins = <
+                                                        MX6QDL_PAD_SD1_CMD__SD1_CMD    0x17059
+                                                        MX6QDL_PAD_SD1_CLK__SD1_CLK    0x10059
+                                                        MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
+                                                        MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
+                                                        MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
+                                                        MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
+                                                >;
+                                        };
+                                };
+
+                                usdhc2 {
+                                        pinctrl_usdhc2_1: usdhc2grp-1 {
+                                                fsl,pins = <
+                                                        MX6QDL_PAD_SD2_CMD__SD2_CMD    0x17059
+                                                        MX6QDL_PAD_SD2_CLK__SD2_CLK    0x10059
+                                                        MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+                                                        MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+                                                        MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+                                                        MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+                                                        MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
+                                                        MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
+                                                        MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
+                                                        MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
+                                                >;
+                                        };
+
+                                        pinctrl_usdhc2_2: usdhc2grp-2 {
+                                                fsl,pins = <
+                                                        MX6QDL_PAD_SD2_CMD__SD2_CMD    0x17059
+                                                        MX6QDL_PAD_SD2_CLK__SD2_CLK    0x10059
+                                                        MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+                                                        MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+                                                        MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+                                                        MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+                                                >;
+                                        };
+                                };
+
+                                usdhc3 {
+                                        pinctrl_usdhc3_1: usdhc3grp-1 {
+                                                fsl,pins = <
+                                                        MX6QDL_PAD_SD3_CMD__SD3_CMD    0x17059
+                                                        MX6QDL_PAD_SD3_CLK__SD3_CLK    0x10059
+                                                        MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+                                                        MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+                                                        MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+                                                        MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+                                                        MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
+                                                        MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
+                                                        MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
+                                                        MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
+                                                >;
+                                        };
+
+                                        pinctrl_usdhc3_2: usdhc3grp-2 {
+                                                fsl,pins = <
+                                                        MX6QDL_PAD_SD3_CMD__SD3_CMD    0x17059
+                                                        MX6QDL_PAD_SD3_CLK__SD3_CLK    0x10059
+                                                        MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+                                                        MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+                                                        MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+                                                        MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+                                                >;
+                                        };
+                                };
+
+                                usdhc4 {
+                                        pinctrl_usdhc4_1: usdhc4grp-1 {
+                                                fsl,pins = <
+                                                        MX6QDL_PAD_SD4_CMD__SD4_CMD    0x17059
+                                                        MX6QDL_PAD_SD4_CLK__SD4_CLK    0x10059
+                                                        MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
+                                                        MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
+                                                        MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
+                                                        MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
+                                                        MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
+                                                        MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
+                                                        MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
+                                                        MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
+                                                >;
+                                        };
+
+                                        pinctrl_usdhc4_2: usdhc4grp-2 {
+                                                fsl,pins = <
+                                                        MX6QDL_PAD_SD4_CMD__SD4_CMD    0x17059
+                                                        MX6QDL_PAD_SD4_CLK__SD4_CLK    0x10059
+                                                        MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
+                                                        MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
+                                                        MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
+                                                        MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
+                                                >;
+                                        };
+                                };
+
+                                weim {
+                                        pinctrl_weim_cs0_1: weim_cs0grp-1 {
+                                                fsl,pins = <
+                                                        MX6QDL_PAD_EIM_CS0__EIM_CS0_B   0xb0b1
+                                                >;
+                                        };
+
+                                        pinctrl_weim_nor_1: weim_norgrp-1 {
+                                                fsl,pins = <
+                                                        MX6QDL_PAD_EIM_OE__EIM_OE_B     0xb0b1
+                                                        MX6QDL_PAD_EIM_RW__EIM_RW       0xb0b1
+                                                        MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
+                                                        /* data */
+                                                        MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
+                                                        MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
+                                                        MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
+                                                        MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
+                                                        MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
+                                                        MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
+                                                        MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
+                                                        MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
+                                                        MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
+                                                        MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
+                                                        MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
+                                                        MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
+                                                        MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
+                                                        MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
+                                                        MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
+                                                        MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
+                                                        /* address */
+                                                        MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
+                                                        MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
+                                                        MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
+                                                        MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
+                                                        MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
+                                                        MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
+                                                        MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
+                                                        MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
+                                                        MX6QDL_PAD_EIM_DA15__EIM_AD15  0xb0b1
+                                                        MX6QDL_PAD_EIM_DA14__EIM_AD14  0xb0b1
+                                                        MX6QDL_PAD_EIM_DA13__EIM_AD13  0xb0b1
+                                                        MX6QDL_PAD_EIM_DA12__EIM_AD12  0xb0b1
+                                                        MX6QDL_PAD_EIM_DA11__EIM_AD11  0xb0b1
+                                                        MX6QDL_PAD_EIM_DA10__EIM_AD10  0xb0b1
+                                                        MX6QDL_PAD_EIM_DA9__EIM_AD09   0xb0b1
+                                                        MX6QDL_PAD_EIM_DA8__EIM_AD08   0xb0b1
+                                                        MX6QDL_PAD_EIM_DA7__EIM_AD07   0xb0b1
+                                                        MX6QDL_PAD_EIM_DA6__EIM_AD06   0xb0b1
+                                                        MX6QDL_PAD_EIM_DA5__EIM_AD05   0xb0b1
+                                                        MX6QDL_PAD_EIM_DA4__EIM_AD04   0xb0b1
+                                                        MX6QDL_PAD_EIM_DA3__EIM_AD03   0xb0b1
+                                                        MX6QDL_PAD_EIM_DA2__EIM_AD02   0xb0b1
+                                                        MX6QDL_PAD_EIM_DA1__EIM_AD01   0xb0b1
+                                                        MX6QDL_PAD_EIM_DA0__EIM_AD00   0xb0b1
+                                                >;
+                                        };
+                                };
+                        };
+
                         ldb: ldb@020e0008 {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
@@ -555,13 +1292,11 @@
 
                                 lvds-channel@0 {
                                         reg = <0>;
-                                        crtcs = <&ipu1 0>;
                                         status = "disabled";
                                 };
 
                                 lvds-channel@1 {
                                         reg = <1>;
-                                        crtcs = <&ipu1 1>;
                                         status = "disabled";
                                 };
                         };
@@ -582,6 +1317,7 @@
                                 interrupts = <0 2 0x04>;
                                 clocks = <&clks 155>, <&clks 155>;
                                 clock-names = "ipg", "ahb";
+                                #dma-cells = <3>;
                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
                         };
                 };
@@ -751,8 +1487,8 @@
                                 clocks = <&clks 196>;
                         };
 
-                        ocotp@021bc000 {
-                                compatible = "fsl,imx6q-ocotp";
+                        ocotp: ocotp@021bc000 {
+                                compatible = "fsl,imx6q-ocotp", "syscon";
                                 reg = <0x021bc000 0x4000>;
                         };
 
@@ -791,6 +1527,8 @@
                                 interrupts = <0 27 0x04>;
                                 clocks = <&clks 160>, <&clks 161>;
                                 clock-names = "ipg", "per";
+                                dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
+                                dma-names = "rx", "tx";
                                 status = "disabled";
                         };
 
@@ -800,6 +1538,8 @@
                                 interrupts = <0 28 0x04>;
                                 clocks = <&clks 160>, <&clks 161>;
                                 clock-names = "ipg", "per";
+                                dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
+                                dma-names = "rx", "tx";
                                 status = "disabled";
                         };
 
@@ -809,6 +1549,8 @@
                                 interrupts = <0 29 0x04>;
                                 clocks = <&clks 160>, <&clks 161>;
                                 clock-names = "ipg", "per";
+                                dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
+                                dma-names = "rx", "tx";
                                 status = "disabled";
                         };
 
@@ -818,6 +1560,8 @@
                                 interrupts = <0 30 0x04>;
                                 clocks = <&clks 160>, <&clks 161>;
                                 clock-names = "ipg", "per";
+                                dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
+                                dma-names = "rx", "tx";
                                 status = "disabled";
                         };
                 };
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index c5e5da02d7e3..c46651e4d966 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -152,32 +152,41 @@
                                 };
 
                                 uart5: serial@02018000 {
-                                        compatible = "fsl,imx6sl-uart", "fsl,imx21-uart";
+                                        compatible = "fsl,imx6sl-uart",
+                                                   "fsl,imx6q-uart", "fsl,imx21-uart";
                                         reg = <0x02018000 0x4000>;
                                         interrupts = <0 30 0x04>;
                                         clocks = <&clks IMX6SL_CLK_UART>,
                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
                                         clock-names = "ipg", "per";
+                                        dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
+                                        dma-names = "rx", "tx";
                                         status = "disabled";
                                 };
 
                                 uart1: serial@02020000 {
-                                        compatible = "fsl,imx6sl-uart", "fsl,imx21-uart";
+                                        compatible = "fsl,imx6sl-uart",
+                                                   "fsl,imx6q-uart", "fsl,imx21-uart";
                                         reg = <0x02020000 0x4000>;
                                         interrupts = <0 26 0x04>;
                                         clocks = <&clks IMX6SL_CLK_UART>,
                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
                                         clock-names = "ipg", "per";
+                                        dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
+                                        dma-names = "rx", "tx";
                                         status = "disabled";
                                 };
 
                                 uart2: serial@02024000 {
-                                        compatible = "fsl,imx6sl-uart", "fsl,imx21-uart";
+                                        compatible = "fsl,imx6sl-uart",
+                                                   "fsl,imx6q-uart", "fsl,imx21-uart";
                                         reg = <0x02024000 0x4000>;
                                         interrupts = <0 27 0x04>;
                                         clocks = <&clks IMX6SL_CLK_UART>,
                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
                                         clock-names = "ipg", "per";
+                                        dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
+                                        dma-names = "rx", "tx";
                                         status = "disabled";
                                 };
 
@@ -186,6 +195,9 @@
                                         reg = <0x02028000 0x4000>;
                                         interrupts = <0 46 0x04>;
                                         clocks = <&clks IMX6SL_CLK_SSI1>;
+                                        dmas = <&sdma 37 1 0>,
+                                               <&sdma 38 1 0>;
+                                        dma-names = "rx", "tx";
                                         fsl,fifo-depth = <15>;
                                         status = "disabled";
                                 };
@@ -195,6 +207,9 @@
                                         reg = <0x0202c000 0x4000>;
                                         interrupts = <0 47 0x04>;
                                         clocks = <&clks IMX6SL_CLK_SSI2>;
+                                        dmas = <&sdma 41 1 0>,
+                                               <&sdma 42 1 0>;
+                                        dma-names = "rx", "tx";
                                         fsl,fifo-depth = <15>;
                                         status = "disabled";
                                 };
@@ -204,27 +219,36 @@
                                         reg = <0x02030000 0x4000>;
                                         interrupts = <0 48 0x04>;
                                         clocks = <&clks IMX6SL_CLK_SSI3>;
+                                        dmas = <&sdma 45 1 0>,
+                                               <&sdma 46 1 0>;
+                                        dma-names = "rx", "tx";
                                         fsl,fifo-depth = <15>;
                                         status = "disabled";
                                 };
 
                                 uart3: serial@02034000 {
-                                        compatible = "fsl,imx6sl-uart", "fsl,imx21-uart";
+                                        compatible = "fsl,imx6sl-uart",
+                                                   "fsl,imx6q-uart", "fsl,imx21-uart";
                                         reg = <0x02034000 0x4000>;
                                         interrupts = <0 28 0x04>;
                                         clocks = <&clks IMX6SL_CLK_UART>,
                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
                                         clock-names = "ipg", "per";
+                                        dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
+                                        dma-names = "rx", "tx";
                                         status = "disabled";
                                 };
 
                                 uart4: serial@02038000 {
-                                        compatible = "fsl,imx6sl-uart", "fsl,imx21-uart";
+                                        compatible = "fsl,imx6sl-uart",
+                                                   "fsl,imx6q-uart", "fsl,imx21-uart";
                                         reg = <0x02038000 0x4000>;
                                         interrupts = <0 29 0x04>;
                                         clocks = <&clks IMX6SL_CLK_UART>,
                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
                                         clock-names = "ipg", "per";
+                                        dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
+                                        dma-names = "rx", "tx";
                                         status = "disabled";
                                 };
                         };
@@ -594,6 +618,7 @@
                                 clocks = <&clks IMX6SL_CLK_SDMA>,
                                          <&clks IMX6SL_CLK_SDMA>;
                                 clock-names = "ipg", "ahb";
+                                #dma-cells = <3>;
                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6sl.bin";
                         };
 
diff --git a/arch/arm/boot/dts/kirkwood-6281.dtsi b/arch/arm/boot/dts/kirkwood-6281.dtsi
index 1e5bef0bead7..650ef30e1856 100644
--- a/arch/arm/boot/dts/kirkwood-6281.dtsi
+++ b/arch/arm/boot/dts/kirkwood-6281.dtsi
@@ -1,4 +1,39 @@
 / {
+        mbus {
+                pcie-controller {
+                        compatible = "marvell,kirkwood-pcie";
+                        status = "disabled";
+                        device_type = "pci";
+
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+
+                        bus-range = <0x00 0xff>;
+
+                        ranges =
+                               <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
+                                0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0       1 0 /* Port 0.0 MEM */
+                                0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0       1 0 /* Port 0.0 IO  */>;
+
+                        pcie@1,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
+                                reg = <0x0800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
+                                          0x81000000 0 0 0x81000000 0x1 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &intc 9>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gate_clk 2>;
+                                status = "disabled";
+                        };
+                };
+        };
+
         ocp@f1000000 {
                 pinctrl: pinctrl@10000 {
                         compatible = "marvell,88f6281-pinctrl";
@@ -41,37 +76,6 @@
                         };
                 };
 
-                pcie-controller {
-                        compatible = "marvell,kirkwood-pcie";
-                        status = "disabled";
-                        device_type = "pci";
-
-                        #address-cells = <3>;
-                        #size-cells = <2>;
-
-                        bus-range = <0x00 0xff>;
-
-                        ranges = <0x82000000 0 0x00040000 0x00040000 0 0x00002000   /* Port 0.0 registers */
-                                  0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
-                                  0x81000000 0 0          0xe8000000 0 0x00100000>; /* downstream I/O */
-
-                        pcie@1,0 {
-                                device_type = "pci";
-                                assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
-                                reg = <0x0800 0 0 0 0>;
-                                #address-cells = <3>;
-                                #size-cells = <2>;
-                                #interrupt-cells = <1>;
-                                ranges;
-                                interrupt-map-mask = <0 0 0 0>;
-                                interrupt-map = <0 0 0 0 &intc 9>;
-                                marvell,pcie-port = <0>;
-                                marvell,pcie-lane = <0>;
-                                clocks = <&gate_clk 2>;
-                                status = "disabled";
-                        };
-                };
-
                 rtc@10300 {
                         compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
                         reg = <0x10300 0x20>;
diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi
index a63a11137262..3933a331ddc2 100644
--- a/arch/arm/boot/dts/kirkwood-6282.dtsi
+++ b/arch/arm/boot/dts/kirkwood-6282.dtsi
@@ -1,4 +1,59 @@
 / {
+        mbus {
+                pcie-controller {
+                        compatible = "marvell,kirkwood-pcie";
+                        status = "disabled";
+                        device_type = "pci";
+
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+
+                        bus-range = <0x00 0xff>;
+
+                        ranges =
+                               <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
+                                0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
+                                0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
+                                0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0       1 0 /* Port 0.0 MEM */
+                                0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0       1 0 /* Port 0.0 IO  */
+                                0x82000000 0x2 0     MBUS_ID(0x04, 0xd8) 0       1 0 /* Port 1.0 MEM */
+                                0x81000000 0x2 0     MBUS_ID(0x04, 0xd0) 0       1 0 /* Port 1.0 IO  */>;
+
+                        pcie@1,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
+                                reg = <0x0800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
+                                          0x81000000 0 0 0x81000000 0x1 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &intc 9>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gate_clk 2>;
+                                status = "disabled";
+                        };
+
+                        pcie@2,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>;
+                                reg = <0x1000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
+                                          0x81000000 0 0 0x81000000 0x2 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &intc 10>;
+                                marvell,pcie-port = <1>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gate_clk 18>;
+                                status = "disabled";
+                        };
+                };
+        };
         ocp@f1000000 {
 
                 pinctrl: pinctrl@10000 {
@@ -94,52 +149,5 @@
                         status = "disabled";
                 };
 
-                pcie-controller {
-                        compatible = "marvell,kirkwood-pcie";
-                        status = "disabled";
-                        device_type = "pci";
-
-                        #address-cells = <3>;
-                        #size-cells = <2>;
-
-                        bus-range = <0x00 0xff>;
-
-                        ranges = <0x82000000 0 0x00040000 0x00040000 0 0x00002000   /* Port 0.0 registers */
-                                  0x82000000 0 0x00044000 0x00044000 0 0x00002000   /* Port 1.0 registers */
-                                  0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
-                                  0x81000000 0 0          0xe8000000 0 0x00100000>; /* downstream I/O */
-
-                        pcie@1,0 {
-                                device_type = "pci";
-                                assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
-                                reg = <0x0800 0 0 0 0>;
-                                #address-cells = <3>;
-                                #size-cells = <2>;
-                                #interrupt-cells = <1>;
-                                ranges;
-                                interrupt-map-mask = <0 0 0 0>;
-                                interrupt-map = <0 0 0 0 &intc 9>;
-                                marvell,pcie-port = <0>;
-                                marvell,pcie-lane = <0>;
-                                clocks = <&gate_clk 2>;
-                                status = "disabled";
-                        };
-
-                        pcie@2,0 {
-                                device_type = "pci";
-                                assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>;
-                                reg = <0x1000 0 0 0 0>;
-                                #address-cells = <3>;
-                                #size-cells = <2>;
-                                #interrupt-cells = <1>;
-                                ranges;
-                                interrupt-map-mask = <0 0 0 0>;
-                                interrupt-map = <0 0 0 0 &intc 10>;
-                                marvell,pcie-port = <1>;
-                                marvell,pcie-lane = <0>;
-                                clocks = <&gate_clk 18>;
-                                status = "disabled";
-                        };
-                };
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood-cloudbox.dts b/arch/arm/boot/dts/kirkwood-cloudbox.dts
index 00c48d26de68..9bf139c5a34d 100644
--- a/arch/arm/boot/dts/kirkwood-cloudbox.dts
+++ b/arch/arm/boot/dts/kirkwood-cloudbox.dts
@@ -1,7 +1,7 @@
 /dts-v1/;
 
-/include/ "kirkwood.dtsi"
-/include/ "kirkwood-6281.dtsi"
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
 
 / {
         model = "LaCie CloudBox";
diff --git a/arch/arm/boot/dts/kirkwood-db-88f6281.dts b/arch/arm/boot/dts/kirkwood-db-88f6281.dts
index 9d777edd1f36..72c4b0a0366f 100644
--- a/arch/arm/boot/dts/kirkwood-db-88f6281.dts
+++ b/arch/arm/boot/dts/kirkwood-db-88f6281.dts
@@ -11,14 +11,15 @@
 
 /dts-v1/;
 
-/include/ "kirkwood-db.dtsi"
-/include/ "kirkwood-6281.dtsi"
+#include "kirkwood-db.dtsi"
+#include "kirkwood-6281.dtsi"
 
 / {
         model = "Marvell DB-88F6281-BP Development Board";
         compatible = "marvell,db-88f6281-bp", "marvell,kirkwood-88f6281", "marvell,kirkwood";
 
-        ocp@f1000000 {
+        mbus {
+                ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>;
                 pcie-controller {
                         status = "okay";
 
diff --git a/arch/arm/boot/dts/kirkwood-db-88f6282.dts b/arch/arm/boot/dts/kirkwood-db-88f6282.dts
index f4c852886d23..36c411d34926 100644
--- a/arch/arm/boot/dts/kirkwood-db-88f6282.dts
+++ b/arch/arm/boot/dts/kirkwood-db-88f6282.dts
@@ -11,14 +11,15 @@
 
 /dts-v1/;
 
-/include/ "kirkwood-db.dtsi"
-/include/ "kirkwood-6282.dtsi"
+#include "kirkwood-db.dtsi"
+#include "kirkwood-6282.dtsi"
 
 / {
         model = "Marvell DB-88F6282-BP Development Board";
         compatible = "marvell,db-88f6282-bp", "marvell,kirkwood-88f6282", "marvell,kirkwood";
 
-        ocp@f1000000 {
+        mbus {
+                ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>;
                 pcie-controller {
                         status = "okay";
 
diff --git a/arch/arm/boot/dts/kirkwood-db.dtsi b/arch/arm/boot/dts/kirkwood-db.dtsi
index c87cfb816120..45c1bf74ac00 100644
--- a/arch/arm/boot/dts/kirkwood-db.dtsi
+++ b/arch/arm/boot/dts/kirkwood-db.dtsi
@@ -12,7 +12,7 @@
  * and 6282 variants of the Marvell Kirkwood Development Board.
  */
 
-/include/ "kirkwood.dtsi"
+#include "kirkwood.dtsi"
 
 / {
         memory {
@@ -77,13 +77,5 @@
                         cd-gpios = <&gpio1 6 0>;
                         status = "okay";
                 };
-
-                pcie-controller {
-                        status = "okay";
-
-                        pcie@1,0 {
-                                status = "okay";
-                        };
-                };
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood-dns320.dts b/arch/arm/boot/dts/kirkwood-dns320.dts
index 14d4ceea3057..e112ca62d978 100644
--- a/arch/arm/boot/dts/kirkwood-dns320.dts
+++ b/arch/arm/boot/dts/kirkwood-dns320.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "kirkwood-dnskw.dtsi"
+#include "kirkwood-dnskw.dtsi"
 
 / {
         model = "D-Link DNS-320 NAS (Rev A1)";
diff --git a/arch/arm/boot/dts/kirkwood-dns325.dts b/arch/arm/boot/dts/kirkwood-dns325.dts
index 63872570e6ce..5119fb8a8eb6 100644
--- a/arch/arm/boot/dts/kirkwood-dns325.dts
+++ b/arch/arm/boot/dts/kirkwood-dns325.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "kirkwood-dnskw.dtsi"
+#include "kirkwood-dnskw.dtsi"
 
 / {
         model = "D-Link DNS-325 NAS (Rev A1)";
diff --git a/arch/arm/boot/dts/kirkwood-dnskw.dtsi b/arch/arm/boot/dts/kirkwood-dnskw.dtsi
index 0afe1d07c803..2e04284846a0 100644
--- a/arch/arm/boot/dts/kirkwood-dnskw.dtsi
+++ b/arch/arm/boot/dts/kirkwood-dnskw.dtsi
@@ -1,5 +1,5 @@
-/include/ "kirkwood.dtsi"
-/include/ "kirkwood-6281.dtsi"
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
 
 / {
         model = "D-Link DNS NASes (kirkwood-based)";
diff --git a/arch/arm/boot/dts/kirkwood-dockstar.dts b/arch/arm/boot/dts/kirkwood-dockstar.dts
index 7714742bb8d8..4387ae8e93fe 100644
--- a/arch/arm/boot/dts/kirkwood-dockstar.dts
+++ b/arch/arm/boot/dts/kirkwood-dockstar.dts
@@ -1,7 +1,7 @@
 /dts-v1/;
 
-/include/ "kirkwood.dtsi"
-/include/ "kirkwood-6281.dtsi"
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
 
 / {
         model = "Seagate FreeAgent Dockstar";
diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/kirkwood-dreamplug.dts
index 36c7ba38d500..c62837837246 100644
--- a/arch/arm/boot/dts/kirkwood-dreamplug.dts
+++ b/arch/arm/boot/dts/kirkwood-dreamplug.dts
@@ -1,7 +1,7 @@
 /dts-v1/;
 
-/include/ "kirkwood.dtsi"
-/include/ "kirkwood-6281.dtsi"
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
 
 / {
         model = "Globalscale Technologies Dreamplug";
diff --git a/arch/arm/boot/dts/kirkwood-goflexnet.dts b/arch/arm/boot/dts/kirkwood-goflexnet.dts
index 31caa6405065..e57118039277 100644
--- a/arch/arm/boot/dts/kirkwood-goflexnet.dts
+++ b/arch/arm/boot/dts/kirkwood-goflexnet.dts
@@ -1,7 +1,7 @@
 /dts-v1/;
 
-/include/ "kirkwood.dtsi"
-/include/ "kirkwood-6281.dtsi"
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
 
 / {
         model = "Seagate GoFlex Net";
diff --git a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
index 1e642f39b154..2c5673adb4bd 100644
--- a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
+++ b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
@@ -1,7 +1,7 @@
 /dts-v1/;
 
-/include/ "kirkwood.dtsi"
-/include/ "kirkwood-6281.dtsi"
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
 
 / {
         model = "Globalscale Technologies Guruplug Server Plus";
diff --git a/arch/arm/boot/dts/kirkwood-ib62x0.dts b/arch/arm/boot/dts/kirkwood-ib62x0.dts
index 20c4b081f420..158161ff6826 100644
--- a/arch/arm/boot/dts/kirkwood-ib62x0.dts
+++ b/arch/arm/boot/dts/kirkwood-ib62x0.dts
@@ -1,7 +1,7 @@
 /dts-v1/;
 
-/include/ "kirkwood.dtsi"
-/include/ "kirkwood-6281.dtsi"
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
 
 / {
         model = "RaidSonic ICY BOX IB-NAS62x0 (Rev B)";
diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts
index 441204e8abc6..8314118b6b8a 100644
--- a/arch/arm/boot/dts/kirkwood-iconnect.dts
+++ b/arch/arm/boot/dts/kirkwood-iconnect.dts
@@ -1,7 +1,7 @@
 /dts-v1/;
 
-/include/ "kirkwood.dtsi"
-/include/ "kirkwood-6281.dtsi"
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
 
 / {
         model = "Iomega Iconnect";
@@ -18,6 +18,17 @@
                 linux,initrd-end   = <0x4800000>;
         };
 
+        mbus {
+                ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>;
+                pcie-controller {
+                        status = "okay";
+
+                        pcie@1,0 {
+                                status = "okay";
+                        };
+                };
+        };
+
         ocp@f1000000 {
                 pinctrl: pinctrl@10000 {
                         pmx_button_reset: pmx-button-reset {
@@ -101,14 +112,6 @@
                                 reg = <0x980000 0x1f400000>;
                         };
                 };
-
-                pcie-controller {
-                        status = "okay";
-
-                        pcie@1,0 {
-                                status = "okay";
-                        };
-                };
         };
 
         gpio-leds {
diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
index 00a7bfe5e83b..fd7f053e9c96 100644
--- a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
+++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
@@ -1,7 +1,7 @@
 /dts-v1/;
 
-/include/ "kirkwood.dtsi"
-/include/ "kirkwood-6281.dtsi"
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
 
 / {
         model = "Iomega StorCenter ix2-200";
diff --git a/arch/arm/boot/dts/kirkwood-is2.dts b/arch/arm/boot/dts/kirkwood-is2.dts
index c3f036b86cca..bd88a236f729 100644
--- a/arch/arm/boot/dts/kirkwood-is2.dts
+++ b/arch/arm/boot/dts/kirkwood-is2.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "kirkwood-ns2-common.dtsi"
+#include "kirkwood-ns2-common.dtsi"
 
 / {
         model = "LaCie Internet Space v2";
diff --git a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
index 5d9f5ea78700..b071d37cc291 100644
--- a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
+++ b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
@@ -1,7 +1,7 @@
 /dts-v1/;
 
-/include/ "kirkwood.dtsi"
-/include/ "kirkwood-98dx4122.dtsi"
+#include "kirkwood.dtsi"
+#include "kirkwood-98dx4122.dtsi"
 
 / {
         model = "Keymile Kirkwood Reference Design";
diff --git a/arch/arm/boot/dts/kirkwood-lschlv2.dts b/arch/arm/boot/dts/kirkwood-lschlv2.dts
index 9f55d95f35f5..e2fa368aef25 100644
--- a/arch/arm/boot/dts/kirkwood-lschlv2.dts
+++ b/arch/arm/boot/dts/kirkwood-lschlv2.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "kirkwood-lsxl.dtsi"
+#include "kirkwood-lsxl.dtsi"
 
 / {
         model = "Buffalo Linkstation LS-CHLv2";
diff --git a/arch/arm/boot/dts/kirkwood-lsxhl.dts b/arch/arm/boot/dts/kirkwood-lsxhl.dts
index 5c84c118ed8d..8d89cdf8d6bf 100644
--- a/arch/arm/boot/dts/kirkwood-lsxhl.dts
+++ b/arch/arm/boot/dts/kirkwood-lsxhl.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "kirkwood-lsxl.dtsi"
+#include "kirkwood-lsxl.dtsi"
 
 / {
         model = "Buffalo Linkstation LS-XHL";
diff --git a/arch/arm/boot/dts/kirkwood-lsxl.dtsi b/arch/arm/boot/dts/kirkwood-lsxl.dtsi
index 31b17f5b9d28..f7e247cc925a 100644
--- a/arch/arm/boot/dts/kirkwood-lsxl.dtsi
+++ b/arch/arm/boot/dts/kirkwood-lsxl.dtsi
@@ -1,5 +1,5 @@
-/include/ "kirkwood.dtsi"
-/include/ "kirkwood-6281.dtsi"
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
 
 / {
         chosen {
diff --git a/arch/arm/boot/dts/kirkwood-mplcec4.dts b/arch/arm/boot/dts/kirkwood-mplcec4.dts
index 6179333fd71f..21f1954c9e54 100644
--- a/arch/arm/boot/dts/kirkwood-mplcec4.dts
+++ b/arch/arm/boot/dts/kirkwood-mplcec4.dts
@@ -1,7 +1,7 @@
 /dts-v1/;
 
-/include/ "kirkwood.dtsi"
-/include/ "kirkwood-6281.dtsi"
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
 
 / {
         model = "MPL CEC4";
@@ -16,6 +16,17 @@
                 bootargs = "console=ttyS0,115200n8 earlyprintk";
         };
 
+        mbus {
+                ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>;
+                pcie-controller {
+                        status = "okay";
+
+                        pcie@1,0 {
+                                status = "okay";
+                        };
+                };
+        };
+
         ocp@f1000000 {
                 pinctrl: pinctrl@10000 {
                         pmx_led_health: pmx-led-health {
@@ -134,14 +145,6 @@
                         cd-gpios = <&gpio1 15 1>;
                         /* No WP GPIO */
                 };
-
-                pcie-controller {
-                        status = "okay";
-
-                        pcie@1,0 {
-                                status = "okay";
-                        };
-                };
         };
 
         gpio-leds {
diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
index ad6ade7d9191..cc40f19ae3fc 100644
--- a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
+++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
@@ -1,7 +1,7 @@
 /dts-v1/;
 
-/include/ "kirkwood.dtsi"
-/include/ "kirkwood-6282.dtsi"
+#include "kirkwood.dtsi"
+#include "kirkwood-6282.dtsi"
 
 / {
         model = "NETGEAR ReadyNAS Duo v2";
@@ -16,6 +16,17 @@
                 bootargs = "console=ttyS0,115200n8 earlyprintk";
         };
 
+        mbus {
+                ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>;
+                pcie-controller {
+                        status = "okay";
+
+                        pcie@1,0 {
+                                status = "okay";
+                        };
+                };
+        };
+
         ocp@f1000000 {
                 pinctrl: pinctrl@10000 {
                         pmx_button_power: pmx-button-power {
@@ -52,6 +63,17 @@
                         };
                 };
 
+                clocks {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       g762_clk: fixedclk {
+                                 compatible = "fixed-clock";
+                                 #clock-cells = <0>;
+                                 clock-frequency = <8192>;
+                       };
+                };
+
                 i2c@11000 {
                         status = "okay";
 
@@ -59,6 +81,15 @@
                                 compatible = "ricoh,rs5c372a";
                                 reg = <0x32>;
                         };
+
+                        g762: g762@3e {
+                                compatible = "gmt,g762";
+                                reg = <0x3e>;
+                                clocks = <&g762_clk>; /* input clock */
+                                fan_gear_mode = <0>;
+                                fan_startv = <1>;
+                                pwm_polarity = <0>;
+                        };
                 };
 
                 serial@12000 {
@@ -101,14 +132,6 @@
                         status = "okay";
                         nr-ports = <2>;
                 };
-
-                pcie-controller {
-                        status = "okay";
-
-                        pcie@1,0 {
-                                status = "okay";
-                        };
-                };
         };
 
         gpio-leds {
diff --git a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi
index 2afac0405816..d0fb34dc1667 100644
--- a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi
+++ b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi
@@ -1,5 +1,5 @@
-/include/ "kirkwood.dtsi"
-/include/ "kirkwood-6281.dtsi"
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
 
 / {
         chosen {
diff --git a/arch/arm/boot/dts/kirkwood-ns2.dts b/arch/arm/boot/dts/kirkwood-ns2.dts
index b50e93d7796c..0599f3cb844e 100644
--- a/arch/arm/boot/dts/kirkwood-ns2.dts
+++ b/arch/arm/boot/dts/kirkwood-ns2.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "kirkwood-ns2-common.dtsi"
+#include "kirkwood-ns2-common.dtsi"
 
 / {
         model = "LaCie Network Space v2";
diff --git a/arch/arm/boot/dts/kirkwood-ns2lite.dts b/arch/arm/boot/dts/kirkwood-ns2lite.dts
index af8259fe8955..b0e17984aea0 100644
--- a/arch/arm/boot/dts/kirkwood-ns2lite.dts
+++ b/arch/arm/boot/dts/kirkwood-ns2lite.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "kirkwood-ns2-common.dtsi"
+#include "kirkwood-ns2-common.dtsi"
 
 / {
         model = "LaCie Network Space Lite v2";
diff --git a/arch/arm/boot/dts/kirkwood-ns2max.dts b/arch/arm/boot/dts/kirkwood-ns2max.dts
index 85f24d227e17..d4f6a586d553 100644
--- a/arch/arm/boot/dts/kirkwood-ns2max.dts
+++ b/arch/arm/boot/dts/kirkwood-ns2max.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "kirkwood-ns2-common.dtsi"
+#include "kirkwood-ns2-common.dtsi"
 
 / {
         model = "LaCie Network Space Max v2";
diff --git a/arch/arm/boot/dts/kirkwood-ns2mini.dts b/arch/arm/boot/dts/kirkwood-ns2mini.dts
index 329e530bffe7..f30e05af6473 100644
--- a/arch/arm/boot/dts/kirkwood-ns2mini.dts
+++ b/arch/arm/boot/dts/kirkwood-ns2mini.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "kirkwood-ns2-common.dtsi"
+#include "kirkwood-ns2-common.dtsi"
 
 / {
         /* This machine is embedded in the first LaCie CloudBox product. */
diff --git a/arch/arm/boot/dts/kirkwood-nsa310-common.dtsi b/arch/arm/boot/dts/kirkwood-nsa310-common.dtsi
new file mode 100644
index 000000000000..06267a91de38
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-nsa310-common.dtsi
@@ -0,0 +1,107 @@
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
+
+/ {
+        model = "ZyXEL NSA310";
+
+        ocp@f1000000 {
+                pinctrl: pinctrl@10000 {
+
+                        pmx_usb_power_off: pmx-usb-power-off {
+                                marvell,pins = "mpp21";
+                                marvell,function = "gpio";
+                        };
+                        pmx_pwr_off: pmx-pwr-off {
+                                marvell,pins = "mpp48";
+                                marvell,function = "gpio";
+                        };
+
+                };
+
+                serial@12000 {
+                        status = "ok";
+                };
+
+                sata@80000 {
+                        status = "okay";
+                        nr-ports = <2>;
+                };
+
+                nand@3000000 {
+                        status = "okay";
+                        chip-delay = <35>;
+
+                        partition@0 {
+                                label = "uboot";
+                                reg = <0x0000000 0x0100000>;
+                                read-only;
+                        };
+                        partition@100000 {
+                                label = "uboot_env";
+                                reg = <0x0100000 0x0080000>;
+                        };
+                        partition@180000 {
+                                label = "key_store";
+                                reg = <0x0180000 0x0080000>;
+                        };
+                        partition@200000 {
+                                label = "info";
+                                reg = <0x0200000 0x0080000>;
+                        };
+                        partition@280000 {
+                                label = "etc";
+                                reg = <0x0280000 0x0a00000>;
+                        };
+                        partition@c80000 {
+                                label = "kernel_1";
+                                reg = <0x0c80000 0x0a00000>;
+                        };
+                        partition@1680000 {
+                                label = "rootfs1";
+                                reg = <0x1680000 0x2fc0000>;
+                        };
+                        partition@4640000 {
+                                label = "kernel_2";
+                                reg = <0x4640000 0x0a00000>;
+                        };
+                        partition@5040000 {
+                                label = "rootfs2";
+                                reg = <0x5040000 0x2fc0000>;
+                        };
+                };
+
+                pcie-controller {
+                        status = "okay";
+
+                        pcie@1,0 {
+                                status = "okay";
+                        };
+                };
+        };
+
+        gpio_poweroff {
+                compatible = "gpio-poweroff";
+                pinctrl-0 = <&pmx_pwr_off>;
+                pinctrl-names = "default";
+                gpios = <&gpio1 16 0>;
+        };
+
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-0 = <&pmx_usb_power_off>;
+                pinctrl-names = "default";
+
+                usb0_power_off: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "USB Power Off";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        gpio = <&gpio0 21 0>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-nsa310.dts b/arch/arm/boot/dts/kirkwood-nsa310.dts
index 69003598f5fa..7aeae0c2c1f4 100644
--- a/arch/arm/boot/dts/kirkwood-nsa310.dts
+++ b/arch/arm/boot/dts/kirkwood-nsa310.dts
@@ -1,10 +1,8 @@
 /dts-v1/;
 
-/include/ "kirkwood.dtsi"
-/include/ "kirkwood-6281.dtsi"
+#include "kirkwood-nsa310-common.dtsi"
 
 / {
-        model = "ZyXEL NSA310";
         compatible = "zyxel,nsa310", "marvell,kirkwood-88f6281", "marvell,kirkwood";
 
         memory {
@@ -16,6 +14,17 @@
                 bootargs = "console=ttyS0,115200";
         };
 
+        mbus {
+                ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>;
+                pcie-controller {
+                        status = "okay";
+
+                        pcie@1,0 {
+                                status = "okay";
+                        };
+                };
+        };
+
         ocp@f1000000 {
                 pinctrl: pinctrl@10000 {
                         pinctrl-0 = <&pmx_unknown>;
@@ -41,11 +50,6 @@
                                 marvell,function = "gpio";
                         };
 
-                        pmx_usb_power_off: pmx-usb-power-off {
-                                marvell,pins = "mpp21";
-                                marvell,function = "gpio";
-                        };
-
                         pmx_led_sys_green: pmx-led-sys-green {
                                 marvell,pins = "mpp28";
                                 marvell,function = "gpio";
@@ -95,20 +99,6 @@
                                 marvell,pins = "mpp46";
                                 marvell,function = "gpio";
                         };
-
-                        pmx_pwr_off: pmx-pwr-off {
-                                marvell,pins = "mpp48";
-                                marvell,function = "gpio";
-                        };
-                };
-
-                serial@12000 {
-                        status = "ok";
-                };
-
-                sata@80000 {
-                        status = "okay";
-                        nr-ports = <2>;
                 };
 
                 i2c@11000 {
@@ -119,57 +109,6 @@
                                 reg = <0x2e>;
                         };
                 };
-
-                nand@3000000 {
-                        status = "okay";
-                        chip-delay = <35>;
-
-                        partition@0 {
-                                label = "uboot";
-                                reg = <0x0000000 0x0100000>;
-                                read-only;
-                        };
-                        partition@100000 {
-                                label = "uboot_env";
-                                reg = <0x0100000 0x0080000>;
-                        };
-                        partition@180000 {
-                                label = "key_store";
-                                reg = <0x0180000 0x0080000>;
-                        };
-                        partition@200000 {
-                                label = "info";
-                                reg = <0x0200000 0x0080000>;
-                        };
-                        partition@280000 {
-                                label = "etc";
-                                reg = <0x0280000 0x0a00000>;
-                        };
-                        partition@c80000 {
-                                label = "kernel_1";
-                                reg = <0x0c80000 0x0a00000>;
-                        };
-                        partition@1680000 {
-                                label = "rootfs1";
-                                reg = <0x1680000 0x2fc0000>;
-                        };
-                        partition@4640000 {
-                                label = "kernel_2";
-                                reg = <0x4640000 0x0a00000>;
-                        };
-                        partition@5040000 {
-                                label = "rootfs2";
-                                reg = <0x5040000 0x2fc0000>;
-                        };
-                };
-
-                pcie-controller {
-                        status = "okay";
-
-                        pcie@1,0 {
-                                status = "okay";
-                        };
-                };
         };
 
         gpio_keys {
@@ -246,30 +185,4 @@
                         gpios = <&gpio1 8 0>;
                 };
         };
-
-        gpio_poweroff {
-                compatible = "gpio-poweroff";
-                pinctrl-0 = <&pmx_pwr_off>;
-                pinctrl-names = "default";
-                gpios = <&gpio1 16 0>;
-        };
-
-        regulators {
-                compatible = "simple-bus";
-                #address-cells = <1>;
-                #size-cells = <0>;
-                pinctrl-0 = <&pmx_usb_power_off>;
-                pinctrl-names = "default";
-
-                usb0_power_off: regulator@1 {
-                        compatible = "regulator-fixed";
-                        reg = <1>;
-                        regulator-name = "USB Power Off";
-                        regulator-min-microvolt = <5000000>;
-                        regulator-max-microvolt = <5000000>;
-                        regulator-always-on;
-                        regulator-boot-on;
-                        gpio = <&gpio0 21 0>;
-                };
-        };
 };
diff --git a/arch/arm/boot/dts/kirkwood-nsa310a.dts b/arch/arm/boot/dts/kirkwood-nsa310a.dts
new file mode 100644
index 000000000000..ab0212b0e6f5
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-nsa310a.dts
@@ -0,0 +1,165 @@
+/dts-v1/;
+
+#include "kirkwood-nsa310-common.dtsi"
+
+/*
+ * There are at least two different NSA310 designs. This variant does
+ * not have the red USB Led.
+ */
+
+/ {
+        compatible = "zyxel,nsa310a", "zyxel,nsa310", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x10000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200";
+        };
+
+        ocp@f1000000 {
+                pinctrl: pinctrl@10000 {
+                        pinctrl-names = "default";
+
+                        pmx_led_esata_green: pmx-led-esata-green {
+                                marvell,pins = "mpp12";
+                                marvell,function = "gpio";
+                        };
+
+                        pmx_led_esata_red: pmx-led-esata-red {
+                                marvell,pins = "mpp13";
+                                marvell,function = "gpio";
+                        };
+
+                        pmx_led_usb_green: pmx-led-usb-green {
+                                marvell,pins = "mpp15";
+                                marvell,function = "gpio";
+                        };
+
+                        pmx_usb_power_off: pmx-usb-power-off {
+                                marvell,pins = "mpp21";
+                                marvell,function = "gpio";
+                        };
+
+                        pmx_led_sys_green: pmx-led-sys-green {
+                                marvell,pins = "mpp28";
+                                marvell,function = "gpio";
+                        };
+
+                        pmx_led_sys_red: pmx-led-sys-red {
+                                marvell,pins = "mpp29";
+                                marvell,function = "gpio";
+                        };
+
+                        pmx_btn_reset: pmx-btn-reset {
+                                marvell,pins = "mpp36";
+                                marvell,function = "gpio";
+                        };
+
+                        pmx_btn_copy: pmx-btn-copy {
+                                marvell,pins = "mpp37";
+                                marvell,function = "gpio";
+                        };
+
+                        pmx_led_copy_green: pmx-led-copy-green {
+                                marvell,pins = "mpp39";
+                                marvell,function = "gpio";
+                        };
+
+                        pmx_led_copy_red: pmx-led-copy-red {
+                                marvell,pins = "mpp40";
+                                marvell,function = "gpio";
+                        };
+
+                        pmx_led_hdd_green: pmx-led-hdd-green {
+                                marvell,pins = "mpp41";
+                                marvell,function = "gpio";
+                        };
+
+                        pmx_led_hdd_red: pmx-led-hdd-red {
+                                marvell,pins = "mpp42";
+                                marvell,function = "gpio";
+                        };
+
+                        pmx_btn_power: pmx-btn-power {
+                                marvell,pins = "mpp46";
+                                marvell,function = "gpio";
+                        };
+
+                };
+
+                i2c@11000 {
+                        status = "okay";
+
+                        lm85: lm85@2e {
+                                compatible = "lm85";
+                                reg = <0x2e>;
+                        };
+                };
+        };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                button@1 {
+                        label = "Power Button";
+                        linux,code = <116>;
+                        gpios = <&gpio1 14 0>;
+                };
+                button@2 {
+                        label = "Copy Button";
+                        linux,code = <133>;
+                        gpios = <&gpio1 5 1>;
+                };
+                button@3 {
+                        label = "Reset Button";
+                        linux,code = <0x198>;
+                        gpios = <&gpio1 4 1>;
+                };
+        };
+
+        gpio-leds {
+                compatible = "gpio-leds";
+
+                green-sys {
+                        label = "nsa310:green:sys";
+                        gpios = <&gpio0 28 0>;
+                };
+                red-sys {
+                        label = "nsa310:red:sys";
+                        gpios = <&gpio0 29 0>;
+                };
+                green-hdd {
+                        label = "nsa310:green:hdd";
+                        gpios = <&gpio1 9 0>;
+                };
+                red-hdd {
+                        label = "nsa310:red:hdd";
+                        gpios = <&gpio1 10 0>;
+                };
+                green-esata {
+                        label = "nsa310:green:esata";
+                        gpios = <&gpio0 12 0>;
+                };
+                red-esata {
+                        label = "nsa310:red:esata";
+                        gpios = <&gpio0 13 0>;
+                };
+                green-usb {
+                        label = "nsa310:green:usb";
+                        gpios = <&gpio0 15 0>;
+                };
+                green-copy {
+                        label = "nsa310:green:copy";
+                        gpios = <&gpio1 7 0>;
+                };
+                red-copy {
+                        label = "nsa310:red:copy";
+                        gpios = <&gpio1 8 0>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
index 38dc8517d777..365b792b23a7 100644
--- a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
+++ b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
@@ -1,7 +1,7 @@
 /dts-v1/;
 
-/include/ "kirkwood.dtsi"
-/include/ "kirkwood-6282.dtsi"
+#include "kirkwood.dtsi"
+#include "kirkwood-6282.dtsi"
 
 / {
         model = "Plat'Home OpenBlocksA6";
diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi
index f7143f128504..0cc5f26bbbb6 100644
--- a/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi
+++ b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi
@@ -6,8 +6,8 @@
  * Licensed under GPLv2
  */
 
-/include/ "kirkwood.dtsi"
-/include/ "kirkwood-6281.dtsi"
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
 
 / {
         memory {
diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts b/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts
index f620ce48de97..eac6a21f3b1f 100644
--- a/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts
+++ b/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts
@@ -8,7 +8,7 @@
 
 /dts-v1/;
 
-/include/ "kirkwood-sheevaplug-common.dtsi"
+#include "kirkwood-sheevaplug-common.dtsi"
 
 / {
         model = "Globalscale Technologies eSATA SheevaPlug";
diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug.dts b/arch/arm/boot/dts/kirkwood-sheevaplug.dts
index bf1dff251432..bb61918313db 100644
--- a/arch/arm/boot/dts/kirkwood-sheevaplug.dts
+++ b/arch/arm/boot/dts/kirkwood-sheevaplug.dts
@@ -8,7 +8,7 @@
 
 /dts-v1/;
 
-/include/ "kirkwood-sheevaplug-common.dtsi"
+#include "kirkwood-sheevaplug-common.dtsi"
 
 / {
         model = "Globalscale Technologies SheevaPlug";
diff --git a/arch/arm/boot/dts/kirkwood-topkick.dts b/arch/arm/boot/dts/kirkwood-topkick.dts
index f2052d7bc10f..974f1e0f09b2 100644
--- a/arch/arm/boot/dts/kirkwood-topkick.dts
+++ b/arch/arm/boot/dts/kirkwood-topkick.dts
@@ -1,7 +1,7 @@
 /dts-v1/;
 
-/include/ "kirkwood.dtsi"
-/include/ "kirkwood-6282.dtsi"
+#include "kirkwood.dtsi"
+#include "kirkwood-6282.dtsi"
 
 / {
         model = "Univeral Scientific Industrial Co. Topkick-1281P2";
diff --git a/arch/arm/boot/dts/kirkwood-ts219-6281.dts b/arch/arm/boot/dts/kirkwood-ts219-6281.dts
index 6dd1038e4de4..3867ae3030be 100644
--- a/arch/arm/boot/dts/kirkwood-ts219-6281.dts
+++ b/arch/arm/boot/dts/kirkwood-ts219-6281.dts
@@ -1,8 +1,8 @@
 /dts-v1/;
 
-/include/ "kirkwood.dtsi"
-/include/ "kirkwood-6281.dtsi"
-/include/ "kirkwood-ts219.dtsi"
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
+#include "kirkwood-ts219.dtsi"
 
 / {
         ocp@f1000000 {
diff --git a/arch/arm/boot/dts/kirkwood-ts219-6282.dts b/arch/arm/boot/dts/kirkwood-ts219-6282.dts
index 6fdc5ffcaae5..04f6fe106bb5 100644
--- a/arch/arm/boot/dts/kirkwood-ts219-6282.dts
+++ b/arch/arm/boot/dts/kirkwood-ts219-6282.dts
@@ -1,10 +1,21 @@
 /dts-v1/;
 
-/include/ "kirkwood.dtsi"
-/include/ "kirkwood-6282.dtsi"
-/include/ "kirkwood-ts219.dtsi"
+#include "kirkwood.dtsi"
+#include "kirkwood-6282.dtsi"
+#include "kirkwood-ts219.dtsi"
 
 / {
+        mbus {
+                ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>;
+                pcie-controller {
+                        status = "okay";
+
+                        pcie@2,0 {
+                                status = "okay";
+                        };
+                };
+        };
+
         ocp@f1000000 {
                 pinctrl: pinctrl@10000 {
 
@@ -30,14 +41,6 @@
                                 marvell,function = "gpio";
                         };
                 };
-                pcie-controller {
-                        status = "okay";
-
-                        pcie@2,0 {
-                                status = "okay";
-                        };
-                };
-
         };
 
         gpio_keys {
diff --git a/arch/arm/boot/dts/kirkwood-ts219.dtsi b/arch/arm/boot/dts/kirkwood-ts219.dtsi
index 0c9a94cd666c..7019cf675df2 100644
--- a/arch/arm/boot/dts/kirkwood-ts219.dtsi
+++ b/arch/arm/boot/dts/kirkwood-ts219.dtsi
@@ -11,6 +11,16 @@
                 bootargs = "console=ttyS0,115200n8";
         };
 
+        mbus {
+                pcie-controller {
+                        status = "okay";
+
+                        pcie@1,0 {
+                                status = "okay";
+                        };
+                };
+        };
+
         ocp@f1000000 {
                 i2c@11000 {
                         status = "okay";
@@ -87,12 +97,5 @@
                         status = "okay";
                         nr-ports = <2>;
                 };
-                pcie-controller {
-                        status = "okay";
-
-                        pcie@1,0 {
-                                status = "okay";
-                        };
-                };
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index 9809fc1f105c..70f414d9bd9a 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -1,5 +1,7 @@
 /include/ "skeleton.dtsi"
 
+#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
+
 / {
         compatible = "marvell,kirkwood";
         interrupt-parent = <&intc>;
@@ -28,15 +30,28 @@
                       <0xf1020214 0x04>;
         };
 
+        mbus {
+                compatible = "marvell,kirkwood-mbus", "simple-bus";
+                #address-cells = <2>;
+                #size-cells = <1>;
+                controller = <&mbusc>;
+                pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256 MiB memory space */
+                pcie-io-aperture  = <0xf2000000 0x100000>;   /*   1 MiB    I/O space */
+        };
+
         ocp@f1000000 {
                 compatible = "simple-bus";
                 ranges = <0x00000000 0xf1000000 0x0100000
-                          0xe0000000 0xe0000000 0x8100000 /* PCIE */
                           0xf4000000 0xf4000000 0x0000400
                           0xf5000000 0xf5000000 0x0000400>;
                 #address-cells = <1>;
                 #size-cells = <1>;
 
+                mbusc: mbus-controller@20000 {
+                        compatible = "marvell,mbus-controller";
+                        reg = <0x20000 0x80>, <0x1500 0x20>;
+                };
+
                 core_clk: core-clocks@10030 {
                         compatible = "marvell,kirkwood-core-clock";
                         reg = <0x10030 0x4>;
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
index d2803be4e1a8..759b0cd20013 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
@@ -125,6 +125,12 @@
                 clock-names = "apb_pclk";
         };
 
+        scc@7fff0000 {
+                compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc";
+                reg = <0 0x7fff0000 0 0x1000>;
+                interrupts = <0 95 4>;
+        };
+
         timer {
                 compatible = "arm,armv7-timer";
                 interrupts = <1 13 0xf08>,
diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts
index b3905f5bcaf9..1a58678b93fa 100644
--- a/arch/arm/boot/dts/vf610-twr.dts
+++ b/arch/arm/boot/dts/vf610-twr.dts
@@ -50,6 +50,13 @@
         status = "okay";
 };
 
+&i2c0 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c0_1>;
+        status = "okay";
+};
+
 &uart1 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart1_1>;
diff --git a/arch/arm/configs/imx_v4_v5_defconfig b/arch/arm/configs/imx_v4_v5_defconfig
index f07a847b00c9..e958ebe79779 100644
--- a/arch/arm/configs/imx_v4_v5_defconfig
+++ b/arch/arm/configs/imx_v4_v5_defconfig
@@ -1,4 +1,3 @@
-CONFIG_EXPERIMENTAL=y
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
@@ -17,16 +16,18 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_MXC=y
 CONFIG_ARCH_MULTI_V4T=y
 CONFIG_ARCH_MULTI_V5=y
 # CONFIG_ARCH_MULTI_V7 is not set
+CONFIG_ARCH_MXC=y
+CONFIG_MXC_IRQ_PRIOR=y
 CONFIG_ARCH_MX1ADS=y
 CONFIG_MACH_SCB9328=y
 CONFIG_MACH_APF9328=y
 CONFIG_MACH_MX21ADS=y
 CONFIG_MACH_MX25_3DS=y
 CONFIG_MACH_EUKREA_CPUIMX25SD=y
+CONFIG_MACH_IMX25_DT=y
 CONFIG_MACH_MX27ADS=y
 CONFIG_MACH_PCM038=y
 CONFIG_MACH_CPUIMX27=y
@@ -39,8 +40,6 @@ CONFIG_MACH_PCA100=y
 CONFIG_MACH_MXT_TD60=y
 CONFIG_MACH_IMX27IPCAM=y
 CONFIG_MACH_IMX27_DT=y
-CONFIG_MXC_IRQ_PRIOR=y
-CONFIG_MXC_PWM=y
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
@@ -67,7 +66,6 @@ CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
 CONFIG_MTD=y
 CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_CFI=y
 CONFIG_MTD_CFI_ADV_OPTIONS=y
@@ -123,24 +121,20 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_REGULATOR_MC13783=y
 CONFIG_REGULATOR_MC13892=y
 CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-CONFIG_V4L_PLATFORM_DRIVERS=y
 CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_V4L_PLATFORM_DRIVERS=y
 CONFIG_SOC_CAMERA=y
-CONFIG_SOC_CAMERA_OV2640=y
 CONFIG_VIDEO_MX2=y
 CONFIG_V4L_MEM2MEM_DRIVERS=y
 CONFIG_VIDEO_CODA=y
+CONFIG_SOC_CAMERA_OV2640=y
 CONFIG_FB=y
 CONFIG_FB_IMX=y
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
 CONFIG_LCD_CLASS_DEVICE=y
 CONFIG_LCD_L4F00242T03=y
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_PWM=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FONTS=y
-CONFIG_FONT_8x8=y
 CONFIG_LOGO=y
 CONFIG_SOUND=y
 CONFIG_SND=y
@@ -157,7 +151,6 @@ CONFIG_USB_HID=m
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_MXC=y
-CONFIG_USB_ULPI=y
 CONFIG_MMC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_PLTFM=y
@@ -198,3 +191,5 @@ CONFIG_NLS_CODEPAGE_850=m
 CONFIG_NLS_ISO8859_1=y
 CONFIG_NLS_ISO8859_15=m
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_FONTS=y
+CONFIG_FONT_8x8=y
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index 06686e7303a9..5d488c24b132 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -1,4 +1,3 @@
-CONFIG_EXPERIMENTAL=y
 # CONFIG_LOCALVERSION_AUTO is not set
 CONFIG_KERNEL_LZO=y
 CONFIG_SYSVIPC=y
@@ -17,10 +16,8 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_MODVERSIONS=y
 CONFIG_MODULE_SRCVERSION_ALL=y
 # CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_MXC=y
 CONFIG_ARCH_MULTI_V6=y
-CONFIG_ARCH_MULTI_V7=y
-CONFIG_MACH_IMX31_DT=y
+CONFIG_ARCH_MXC=y
 CONFIG_MACH_MX31LILLY=y
 CONFIG_MACH_MX31LITE=y
 CONFIG_MACH_PCM037=y
@@ -30,6 +27,7 @@ CONFIG_MACH_MX31MOBOARD=y
 CONFIG_MACH_QONG=y
 CONFIG_MACH_ARMADILLO5X0=y
 CONFIG_MACH_KZM_ARM11_01=y
+CONFIG_MACH_IMX31_DT=y
 CONFIG_MACH_PCM043=y
 CONFIG_MACH_MX35_3DS=y
 CONFIG_MACH_VPR200=y
@@ -39,7 +37,6 @@ CONFIG_SOC_IMX53=y
 CONFIG_SOC_IMX6Q=y
 CONFIG_SOC_IMX6SL=y
 CONFIG_SOC_VF610=y
-CONFIG_MXC_PWM=y
 CONFIG_SMP=y
 CONFIG_VMSPLIT_2G=y
 CONFIG_PREEMPT_VOLUNTARY=y
@@ -64,20 +61,24 @@ CONFIG_IP_PNP_DHCP=y
 # CONFIG_INET_LRO is not set
 CONFIG_IPV6=y
 CONFIG_NETFILTER=y
-# CONFIG_WIRELESS is not set
+CONFIG_CFG80211=y
+CONFIG_MAC80211=y
+CONFIG_RFKILL=y
+CONFIG_RFKILL_INPUT=y
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
 # CONFIG_STANDALONE is not set
+CONFIG_IMX_WEIM=y
 CONFIG_CONNECTOR=y
 CONFIG_MTD=y
 CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_CFI=y
 CONFIG_MTD_JEDECPROBE=y
 CONFIG_MTD_CFI_INTELEXT=y
 CONFIG_MTD_CFI_AMDSTD=y
 CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_PHYSMAP_OF=y
 CONFIG_MTD_DATAFLASH=y
 CONFIG_MTD_M25P80=y
 CONFIG_MTD_SST25L=y
@@ -88,6 +89,7 @@ CONFIG_MTD_UBI=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=65536
+CONFIG_SRAM=y
 CONFIG_EEPROM_AT24=y
 CONFIG_EEPROM_AT25=y
 # CONFIG_SCSI_PROC_FS is not set
@@ -98,10 +100,11 @@ CONFIG_SCSI_LOGGING=y
 CONFIG_SCSI_SCAN_ASYNC=y
 # CONFIG_SCSI_LOWLEVEL is not set
 CONFIG_ATA=y
+CONFIG_SATA_AHCI_PLATFORM=y
+CONFIG_AHCI_IMX=y
 CONFIG_PATA_IMX=y
 CONFIG_NETDEVICES=y
 # CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CHELSIO is not set
 CONFIG_CS89x0=y
 CONFIG_CS89x0_PLATFORM=y
 # CONFIG_NET_VENDOR_FARADAY is not set
@@ -115,7 +118,7 @@ CONFIG_SMC91X=y
 CONFIG_SMC911X=y
 CONFIG_SMSC911X=y
 # CONFIG_NET_VENDOR_STMICRO is not set
-# CONFIG_WLAN is not set
+CONFIG_BRCMFMAC=m
 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
 CONFIG_INPUT_EVDEV=y
 CONFIG_INPUT_EVBUG=m
@@ -124,6 +127,7 @@ CONFIG_KEYBOARD_IMX=y
 CONFIG_MOUSE_PS2=m
 CONFIG_MOUSE_PS2_ELANTECH=y
 CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_EGALAX=y
 CONFIG_TOUCHSCREEN_MC13783=y
 CONFIG_INPUT_MISC=y
 CONFIG_INPUT_MMA8450=y
@@ -133,13 +137,13 @@ CONFIG_VT_HW_CONSOLE_BINDING=y
 # CONFIG_DEVKMEM is not set
 CONFIG_SERIAL_IMX=y
 CONFIG_SERIAL_IMX_CONSOLE=y
+CONFIG_SERIAL_FSL_LPUART=y
+CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
 CONFIG_HW_RANDOM=y
 CONFIG_HW_RANDOM_MXC_RNGA=y
-CONFIG_I2C=y
 # CONFIG_I2C_COMPAT is not set
 CONFIG_I2C_CHARDEV=y
 # CONFIG_I2C_HELPER_AUTO is not set
-CONFIG_I2C_ALGOBIT=m
 CONFIG_I2C_ALGOPCF=m
 CONFIG_I2C_ALGOPCA=m
 CONFIG_I2C_IMX=y
@@ -155,30 +159,26 @@ CONFIG_MFD_MC13XXX_SPI=y
 CONFIG_MFD_MC13XXX_I2C=y
 CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_REGULATOR_DA9052=y
 CONFIG_REGULATOR_ANATOP=y
+CONFIG_REGULATOR_DA9052=y
 CONFIG_REGULATOR_MC13783=y
 CONFIG_REGULATOR_MC13892=y
 CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-CONFIG_V4L_PLATFORM_DRIVERS=y
 CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_V4L_PLATFORM_DRIVERS=y
 CONFIG_SOC_CAMERA=y
+CONFIG_VIDEO_MX3=y
+CONFIG_V4L_MEM2MEM_DRIVERS=y
+CONFIG_VIDEO_CODA=y
 CONFIG_SOC_CAMERA_OV2640=y
 CONFIG_DRM=y
-CONFIG_VIDEO_MX3=y
-CONFIG_FB=y
-CONFIG_LCD_PLATFORM=y
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
 CONFIG_LCD_CLASS_DEVICE=y
 CONFIG_LCD_L4F00242T03=y
+CONFIG_LCD_PLATFORM=y
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
 CONFIG_BACKLIGHT_PWM=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
-CONFIG_FONTS=y
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
 CONFIG_LOGO=y
 CONFIG_SOUND=y
 CONFIG_SND=y
@@ -192,11 +192,12 @@ CONFIG_SND_SOC_IMX_MC13783=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_MXC=y
+CONFIG_USB_STORAGE=y
 CONFIG_USB_CHIPIDEA=y
 CONFIG_USB_CHIPIDEA_HOST=y
 CONFIG_USB_PHY=y
+CONFIG_NOP_USB_XCEIV=y
 CONFIG_USB_MXS_PHY=y
-CONFIG_USB_STORAGE=y
 CONFIG_MMC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_PLTFM=y
@@ -213,9 +214,10 @@ CONFIG_IMX_SDMA=y
 CONFIG_MXS_DMA=y
 CONFIG_STAGING=y
 CONFIG_DRM_IMX=y
-CONFIG_DRM_IMX_TVE=y
 CONFIG_DRM_IMX_FB_HELPER=y
 CONFIG_DRM_IMX_PARALLEL_DISPLAY=y
+CONFIG_DRM_IMX_TVE=y
+CONFIG_DRM_IMX_LDB=y
 CONFIG_DRM_IMX_IPUV3_CORE=y
 CONFIG_DRM_IMX_IPUV3=y
 CONFIG_COMMON_CLK_DEBUG=y
@@ -269,3 +271,6 @@ CONFIG_CRC_CCITT=m
 CONFIG_CRC_T10DIF=y
 CONFIG_CRC7=m
 CONFIG_LIBCRC32C=m
+CONFIG_FONTS=y
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig
index 1d6d8fb7f4a1..4555c025629a 100644
--- a/arch/arm/configs/mxs_defconfig
+++ b/arch/arm/configs/mxs_defconfig
@@ -1,4 +1,3 @@
-CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
@@ -27,7 +26,6 @@ CONFIG_ARCH_MXS=y
 # CONFIG_ARM_THUMB is not set
 CONFIG_PREEMPT_VOLUNTARY=y
 CONFIG_AEABI=y
-CONFIG_AUTO_ZRELADDR=y
 CONFIG_FPE_NWFPE=y
 CONFIG_NET=y
 CONFIG_PACKET=y
@@ -43,8 +41,6 @@ CONFIG_SYN_COOKIES=y
 # CONFIG_INET_DIAG is not set
 # CONFIG_IPV6 is not set
 CONFIG_CAN=m
-CONFIG_CAN_RAW=m
-CONFIG_CAN_BCM=m
 CONFIG_CAN_FLEXCAN=m
 # CONFIG_WIRELESS is not set
 CONFIG_DEVTMPFS=y
@@ -52,7 +48,6 @@ CONFIG_DEVTMPFS_MOUNT=y
 # CONFIG_FIRMWARE_IN_KERNEL is not set
 CONFIG_MTD=y
 CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_DATAFLASH=y
 CONFIG_MTD_M25P80=y
@@ -67,12 +62,12 @@ CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_NETDEVICES=y
 CONFIG_ENC28J60=y
-CONFIG_USB_USBNET=y
-CONFIG_USB_NET_SMSC95XX=y
 CONFIG_SMSC_PHY=y
 CONFIG_ICPLUS_PHY=y
 CONFIG_REALTEK_PHY=y
 CONFIG_MICREL_PHY=y
+CONFIG_USB_USBNET=y
+CONFIG_USB_NET_SMSC95XX=y
 # CONFIG_WLAN is not set
 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
 CONFIG_INPUT_EVDEV=y
@@ -110,7 +105,6 @@ CONFIG_LCD_CLASS_DEVICE=y
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
 CONFIG_BACKLIGHT_PWM=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FONTS=y
 CONFIG_LOGO=y
 CONFIG_SOUND=y
 CONFIG_SND=y
@@ -119,9 +113,9 @@ CONFIG_SND_MXS_SOC=y
 CONFIG_SND_SOC_MXS_SGTL5000=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
 CONFIG_USB_CHIPIDEA=y
 CONFIG_USB_CHIPIDEA_HOST=y
-CONFIG_USB_STORAGE=y
 CONFIG_USB_PHY=y
 CONFIG_USB_MXS_PHY=y
 CONFIG_MMC=y
@@ -143,9 +137,9 @@ CONFIG_DMADEVICES=y
 CONFIG_MXS_DMA=y
 CONFIG_STAGING=y
 CONFIG_MXS_LRADC=y
-CONFIG_IIO_SYSFS_TRIGGER=y
 CONFIG_COMMON_CLK_DEBUG=y
 CONFIG_IIO=y
+CONFIG_IIO_SYSFS_TRIGGER=y
 CONFIG_PWM=y
 CONFIG_PWM_MXS=y
 CONFIG_EXT2_FS=y
@@ -173,14 +167,14 @@ CONFIG_NLS_CODEPAGE_850=y
 CONFIG_NLS_ISO8859_1=y
 CONFIG_NLS_ISO8859_15=y
 CONFIG_PRINTK_TIME=y
+CONFIG_DEBUG_INFO=y
 CONFIG_FRAME_WARN=2048
-CONFIG_MAGIC_SYSRQ=y
 CONFIG_UNUSED_SYMBOLS=y
+CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_KERNEL=y
 CONFIG_LOCKUP_DETECTOR=y
 CONFIG_TIMER_STATS=y
 CONFIG_PROVE_LOCKING=y
-CONFIG_DEBUG_INFO=y
 CONFIG_BLK_DEV_IO_TRACE=y
 CONFIG_STRICT_DEVMEM=y
 CONFIG_DEBUG_USER=y
@@ -188,3 +182,4 @@ CONFIG_DEBUG_USER=y
 # CONFIG_CRYPTO_HW is not set
 CONFIG_CRC_ITU_T=m
 CONFIG_CRC7=m
+CONFIG_FONTS=y
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index 056b27aafbe6..254cf0539439 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -305,3 +305,4 @@ CONFIG_TI_DAVINCI_MDIO=y
 CONFIG_TI_DAVINCI_CPDMA=y
 CONFIG_TI_CPSW=y
 CONFIG_AT803X_PHY=y
+CONFIG_SOC_DRA7XX=y
diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h
index a1c90d7feb0e..454d642a4070 100644
--- a/arch/arm/include/asm/mach/pci.h
+++ b/arch/arm/include/asm/mach/pci.h
@@ -36,6 +36,8 @@ struct hw_pci {
                                           resource_size_t start,
                                           resource_size_t size,
                                           resource_size_t align);
+        void            (*add_bus)(struct pci_bus *bus);
+        void            (*remove_bus)(struct pci_bus *bus);
 };
 
 /*
@@ -63,6 +65,8 @@ struct pci_sys_data {
                                           resource_size_t start,
                                           resource_size_t size,
                                           resource_size_t align);
+        void            (*add_bus)(struct pci_bus *bus);
+        void            (*remove_bus)(struct pci_bus *bus);
         void            *private_data;  /* platform controller private data     */
 };
 
diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
index 88e14d74b6de..317da88ae65b 100644
--- a/arch/arm/kernel/bios32.c
+++ b/arch/arm/kernel/bios32.c
@@ -363,6 +363,20 @@ void pcibios_fixup_bus(struct pci_bus *bus)
 }
 EXPORT_SYMBOL(pcibios_fixup_bus);
 
+void pcibios_add_bus(struct pci_bus *bus)
+{
+        struct pci_sys_data *sys = bus->sysdata;
+        if (sys->add_bus)
+                sys->add_bus(bus);
+}
+
+void pcibios_remove_bus(struct pci_bus *bus)
+{
+        struct pci_sys_data *sys = bus->sysdata;
+        if (sys->remove_bus)
+                sys->remove_bus(bus);
+}
+
 /*
  * Swizzle the device pin each time we cross a bridge.  If a platform does
  * not provide a swizzle function, we perform the standard PCI swizzling.
@@ -464,6 +478,8 @@ static void pcibios_init_hw(struct device *parent, struct hw_pci *hw,
                 sys->swizzle = hw->swizzle;
                 sys->map_irq = hw->map_irq;
                 sys->align_resource = hw->align_resource;
+                sys->add_bus = hw->add_bus;
+                sys->remove_bus = hw->remove_bus;
                 INIT_LIST_HEAD(&sys->resources);
 
                 if (hw->private_data)
diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c
index ad95f6a23a28..bf00d15d954d 100644
--- a/arch/arm/mach-at91/board-dt-sama5.c
+++ b/arch/arm/mach-at91/board-dt-sama5.c
@@ -42,20 +42,15 @@ static int ksz9021rn_phy_fixup(struct phy_device *phy)
 {
         int value;
 
-#define GMII_RCCPSR     260
-#define GMII_RRDPSR     261
-#define GMII_ERCR       11
-#define GMII_ERDWR      12
-
         /* Set delay values */
-        value = GMII_RCCPSR | 0x8000;
-        phy_write(phy, GMII_ERCR, value);
+        value = MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW | 0x8000;
+        phy_write(phy, MICREL_KSZ9021_EXTREG_CTRL, value);
         value = 0xF2F4;
-        phy_write(phy, GMII_ERDWR, value);
-        value = GMII_RRDPSR | 0x8000;
-        phy_write(phy, GMII_ERCR, value);
+        phy_write(phy, MICREL_KSZ9021_EXTREG_DATA_WRITE, value);
+        value = MICREL_KSZ9021_RGMII_RX_DATA_PAD_SCEW | 0x8000;
+        phy_write(phy, MICREL_KSZ9021_EXTREG_CTRL, value);
         value = 0x2222;
-        phy_write(phy, GMII_ERDWR, value);
+        phy_write(phy, MICREL_KSZ9021_EXTREG_DATA_WRITE, value);
 
         return 0;
 }
diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
index 1332de8c52c9..c4bdc0a1c36e 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -185,10 +185,6 @@ static __init void da830_evm_usb_init(void)
                            __func__, ret);
 }
 
-static struct davinci_uart_config da830_evm_uart_config __initdata = {
-        .enabled_uarts = 0x7,
-};
-
 static const short da830_evm_mcasp1_pins[] = {
         DA830_AHCLKX1, DA830_ACLKX1, DA830_AFSX1, DA830_AHCLKR1, DA830_AFSR1,
         DA830_AMUTE1, DA830_AXR1_0, DA830_AXR1_1, DA830_AXR1_2, DA830_AXR1_5,
@@ -630,7 +626,7 @@ static __init void da830_evm_init(void)
                 pr_warning("da830_evm_init: watchdog registration failed: %d\n",
                                 ret);
 
-        davinci_serial_init(&da830_evm_uart_config);
+        davinci_serial_init(da8xx_serial_device);
         i2c_register_board_info(1, da830_evm_i2c_devices,
                         ARRAY_SIZE(da830_evm_i2c_devices));
 
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index f5c228190fdd..dd1fb24521aa 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -746,10 +746,6 @@ static struct davinci_i2c_platform_data da850_evm_i2c_0_pdata = {
         .bus_delay      = 0,    /* usec */
 };
 
-static struct davinci_uart_config da850_evm_uart_config __initdata = {
-        .enabled_uarts = 0x7,
-};
-
 /* davinci da850 evm audio machine driver */
 static u8 da850_iis_serializer_direction[] = {
         INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,
@@ -1492,7 +1488,7 @@ static __init void da850_evm_init(void)
                                 __func__, ret);
         }
 
-        davinci_serial_init(&da850_evm_uart_config);
+        davinci_serial_init(da8xx_serial_device);
 
         i2c_register_board_info(1, da850_evm_i2c_devices,
                         ARRAY_SIZE(da850_evm_i2c_devices));
diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c
index c2a0a67d09e0..42b23a3194a0 100644
--- a/arch/arm/mach-davinci/board-dm355-evm.c
+++ b/arch/arm/mach-davinci/board-dm355-evm.c
@@ -314,10 +314,6 @@ static struct platform_device *davinci_evm_devices[] __initdata = {
         &davinci_nand_device,
 };
 
-static struct davinci_uart_config uart_config __initdata = {
-        .enabled_uarts = (1 << 0),
-};
-
 static void __init dm355_evm_map_io(void)
 {
         dm355_init();
@@ -393,7 +389,7 @@ static __init void dm355_evm_init(void)
         platform_add_devices(davinci_evm_devices,
                              ARRAY_SIZE(davinci_evm_devices));
         evm_init_i2c();
-        davinci_serial_init(&uart_config);
+        davinci_serial_init(dm355_serial_device);
 
         /* NOTE:  NAND flash timings set by the UBL are slower than
          * needed by MT29F16G08FAA chips ... EMIF.A1CR is 0x40400204
diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c
index 139e42da25f0..65a984c52df6 100644
--- a/arch/arm/mach-davinci/board-dm355-leopard.c
+++ b/arch/arm/mach-davinci/board-dm355-leopard.c
@@ -173,10 +173,6 @@ static struct platform_device *davinci_leopard_devices[] __initdata = {
         &davinci_nand_device,
 };
 
-static struct davinci_uart_config uart_config __initdata = {
-        .enabled_uarts = (1 << 0),
-};
-
 static void __init dm355_leopard_map_io(void)
 {
         dm355_init();
@@ -252,7 +248,7 @@ static __init void dm355_leopard_init(void)
         platform_add_devices(davinci_leopard_devices,
                              ARRAY_SIZE(davinci_leopard_devices));
         leopard_init_i2c();
-        davinci_serial_init(&uart_config);
+        davinci_serial_init(dm355_serial_device);
 
         /* NOTE:  NAND flash timings set by the UBL are slower than
          * needed by MT29F16G08FAA chips ... EMIF.A1CR is 0x40400204
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
index 4cdb61c54459..92b7f770615a 100644
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -718,10 +718,6 @@ fail:
         /* REVISIT export switches: NTSC/PAL (SW5.6), EXTRA1 (SW5.2), etc */
 }
 
-static struct davinci_uart_config uart_config __initdata = {
-        .enabled_uarts = (1 << 0),
-};
-
 static void __init dm365_evm_map_io(void)
 {
         dm365_init();
@@ -748,7 +744,7 @@ static struct spi_board_info dm365_evm_spi_info[] __initconst = {
 static __init void dm365_evm_init(void)
 {
         evm_init_i2c();
-        davinci_serial_init(&uart_config);
+        davinci_serial_init(dm365_serial_device);
 
         dm365evm_emac_configure();
         dm365evm_mmc_configure();
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index fa4bfaf952d8..40bb9b5b87e8 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -727,10 +727,6 @@ static struct platform_device *davinci_evm_devices[] __initdata = {
         &rtc_dev,
 };
 
-static struct davinci_uart_config uart_config __initdata = {
-        .enabled_uarts = (1 << 0),
-};
-
 static void __init
 davinci_evm_map_io(void)
 {
@@ -792,7 +788,7 @@ static __init void davinci_evm_init(void)
         davinci_setup_mmc(0, &dm6446evm_mmc_config);
         dm644x_init_video(&dm644xevm_capture_cfg, &dm644xevm_display_cfg);
 
-        davinci_serial_init(&uart_config);
+        davinci_serial_init(dm644x_serial_device);
         dm644x_init_asp(&dm644x_evm_snd_data);
 
         /* irlml6401 switches over 1A, in under 8 msec */
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
index 0c005e876cac..2bc3651d56cc 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -750,10 +750,6 @@ static void __init davinci_map_io(void)
         cdce_clk_init();
 }
 
-static struct davinci_uart_config uart_config __initdata = {
-        .enabled_uarts = (1 << 0),
-};
-
 #define DM646X_EVM_PHY_ID               "davinci_mdio-0:01"
 /*
  * The following EDMA channels/slots are not being used by drivers (for
@@ -793,7 +789,7 @@ static __init void evm_init(void)
         struct davinci_soc_info *soc_info = &davinci_soc_info;
 
         evm_init_i2c();
-        davinci_serial_init(&uart_config);
+        davinci_serial_init(dm646x_serial_device);
         dm646x_init_mcasp0(&dm646x_evm_snd_data[0]);
         dm646x_init_mcasp1(&dm646x_evm_snd_data[1]);
 
diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c
index 9549d53aa63f..cd0f58730c2b 100644
--- a/arch/arm/mach-davinci/board-mityomapl138.c
+++ b/arch/arm/mach-davinci/board-mityomapl138.c
@@ -434,10 +434,6 @@ static void __init mityomapl138_setup_nand(void)
                                  ARRAY_SIZE(mityomapl138_devices));
 }
 
-static struct davinci_uart_config mityomapl138_uart_config __initdata = {
-        .enabled_uarts = 0x7,
-};
-
 static const short mityomap_mii_pins[] = {
         DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
         DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
@@ -517,7 +513,7 @@ static void __init mityomapl138_init(void)
         if (ret)
                 pr_warning("watchdog registration failed: %d\n", ret);
 
-        davinci_serial_init(&mityomapl138_uart_config);
+        davinci_serial_init(da8xx_serial_device);
 
         ret = da8xx_register_i2c(0, &mityomap_i2c_0_pdata);
         if (ret)
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
index 808233b60e3d..46f336fca803 100644
--- a/arch/arm/mach-davinci/board-neuros-osd2.c
+++ b/arch/arm/mach-davinci/board-neuros-osd2.c
@@ -154,10 +154,6 @@ static struct platform_device *davinci_ntosd2_devices[] __initdata = {
         &ntosd2_leds_dev,
 };
 
-static struct davinci_uart_config uart_config __initdata = {
-        .enabled_uarts = (1 << 0),
-};
-
 static void __init davinci_ntosd2_map_io(void)
 {
         dm644x_init();
@@ -198,7 +194,7 @@ static __init void davinci_ntosd2_init(void)
         platform_add_devices(davinci_ntosd2_devices,
                                 ARRAY_SIZE(davinci_ntosd2_devices));
 
-        davinci_serial_init(&uart_config);
+        davinci_serial_init(dm644x_serial_device);
         dm644x_init_asp(&dm644x_ntosd2_snd_data);
 
         soc_info->emac_pdata->phy_id = NEUROS_OSD2_PHY_ID;
diff --git a/arch/arm/mach-davinci/board-omapl138-hawk.c b/arch/arm/mach-davinci/board-omapl138-hawk.c
index b8c20de10ca2..ab98c75cabb4 100644
--- a/arch/arm/mach-davinci/board-omapl138-hawk.c
+++ b/arch/arm/mach-davinci/board-omapl138-hawk.c
@@ -286,15 +286,11 @@ usb11_setup_oc_fail:
         gpio_free(DA850_USB1_VBUS_PIN);
 }
 
-static struct davinci_uart_config omapl138_hawk_uart_config __initdata = {
-        .enabled_uarts = 0x7,
-};
-
 static __init void omapl138_hawk_init(void)
 {
         int ret;
 
-        davinci_serial_init(&omapl138_hawk_uart_config);
+        davinci_serial_init(da8xx_serial_device);
 
         omapl138_hawk_config_emac();
 
diff --git a/arch/arm/mach-davinci/board-sffsdr.c b/arch/arm/mach-davinci/board-sffsdr.c
index 513eee14f77d..d84360148100 100644
--- a/arch/arm/mach-davinci/board-sffsdr.c
+++ b/arch/arm/mach-davinci/board-sffsdr.c
@@ -125,10 +125,6 @@ static struct platform_device *davinci_sffsdr_devices[] __initdata = {
         &davinci_sffsdr_nandflash_device,
 };
 
-static struct davinci_uart_config uart_config __initdata = {
-        .enabled_uarts = (1 << 0),
-};
-
 static void __init davinci_sffsdr_map_io(void)
 {
         dm644x_init();
@@ -141,7 +137,7 @@ static __init void davinci_sffsdr_init(void)
         platform_add_devices(davinci_sffsdr_devices,
                              ARRAY_SIZE(davinci_sffsdr_devices));
         sffsdr_init_i2c();
-        davinci_serial_init(&uart_config);
+        davinci_serial_init(dm644x_serial_device);
         soc_info->emac_pdata->phy_id = SFFSDR_PHY_ID;
         davinci_setup_usb(0, 0); /* We support only peripheral mode. */
 
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index abbaf0270be6..d6c746e35ad9 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -395,9 +395,9 @@ static struct clk_lookup da830_clks[] = {
         CLK(NULL,               "tptc0",        &tptc0_clk),
         CLK(NULL,               "tptc1",        &tptc1_clk),
         CLK("da830-mmc.0",      NULL,           &mmcsd_clk),
-        CLK(NULL,               "uart0",        &uart0_clk),
-        CLK(NULL,               "uart1",        &uart1_clk),
-        CLK(NULL,               "uart2",        &uart2_clk),
+        CLK("serial8250.0",     NULL,           &uart0_clk),
+        CLK("serial8250.1",     NULL,           &uart1_clk),
+        CLK("serial8250.2",     NULL,           &uart2_clk),
         CLK("spi_davinci.0",    NULL,           &spi0_clk),
         CLK("spi_davinci.1",    NULL,           &spi1_clk),
         CLK(NULL,               "ecap0",        &ecap0_clk),
@@ -417,6 +417,7 @@ static struct clk_lookup da830_clks[] = {
         CLK(NULL,               "aintc",        &aintc_clk),
         CLK(NULL,               "secu_mgr",     &secu_mgr_clk),
         CLK("davinci_emac.1",   NULL,           &emac_clk),
+        CLK("davinci_mdio.0",   "fck",          &emac_clk),
         CLK(NULL,               "gpio",         &gpio_clk),
         CLK("i2c_davinci.2",    NULL,           &i2c1_clk),
         CLK(NULL,               "usb11",        &usb11_clk),
@@ -1199,7 +1200,6 @@ static struct davinci_soc_info davinci_soc_info_da830 = {
         .gpio_base              = DA8XX_GPIO_BASE,
         .gpio_num               = 128,
         .gpio_irq               = IRQ_DA8XX_GPIO0,
-        .serial_dev             = &da8xx_serial_device,
         .emac_pdata             = &da8xx_emac_pdata,
 };
 
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index a0d4f6038b60..f56e5fbfa2fd 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -451,9 +451,9 @@ static struct clk_lookup da850_clks[] = {
         CLK(NULL,               "tpcc1",        &tpcc1_clk),
         CLK(NULL,               "tptc2",        &tptc2_clk),
         CLK("pruss_uio",        "pruss",        &pruss_clk),
-        CLK(NULL,               "uart0",        &uart0_clk),
-        CLK(NULL,               "uart1",        &uart1_clk),
-        CLK(NULL,               "uart2",        &uart2_clk),
+        CLK("serial8250.0",     NULL,           &uart0_clk),
+        CLK("serial8250.1",     NULL,           &uart1_clk),
+        CLK("serial8250.2",     NULL,           &uart2_clk),
         CLK(NULL,               "aintc",        &aintc_clk),
         CLK(NULL,               "gpio",         &gpio_clk),
         CLK("i2c_davinci.2",    NULL,           &i2c1_clk),
@@ -461,6 +461,7 @@ static struct clk_lookup da850_clks[] = {
         CLK(NULL,               "arm",          &arm_clk),
         CLK(NULL,               "rmii",         &rmii_clk),
         CLK("davinci_emac.1",   NULL,           &emac_clk),
+        CLK("davinci_mdio.0",   "fck",          &emac_clk),
         CLK("davinci-mcasp.0",  NULL,           &mcasp_clk),
         CLK("da8xx_lcdc.0",     "fck",          &lcdc_clk),
         CLK("da830-mmc.0",      NULL,           &mmcsd0_clk),
@@ -1301,7 +1302,6 @@ static struct davinci_soc_info davinci_soc_info_da850 = {
         .gpio_base              = DA8XX_GPIO_BASE,
         .gpio_num               = 144,
         .gpio_irq               = IRQ_DA8XX_GPIO0,
-        .serial_dev             = &da8xx_serial_device,
         .emac_pdata             = &da8xx_emac_pdata,
         .sram_dma               = DA8XX_SHARED_RAM_BASE,
         .sram_len               = SZ_128K,
diff --git a/arch/arm/mach-davinci/da8xx-dt.c b/arch/arm/mach-davinci/da8xx-dt.c
index 961aea8bbad5..d2bc574ae172 100644
--- a/arch/arm/mach-davinci/da8xx-dt.c
+++ b/arch/arm/mach-davinci/da8xx-dt.c
@@ -20,13 +20,6 @@
 
 #define DA8XX_NUM_UARTS 3
 
-static void __init da8xx_uart_clk_enable(void)
-{
-        int i;
-        for (i = 0; i < DA8XX_NUM_UARTS; i++)
-                davinci_serial_setup_clk(i, NULL);
-}
-
 static struct of_device_id da8xx_irq_match[] __initdata = {
         { .compatible = "ti,cp-intc", .data = cp_intc_of_init, },
         { }
@@ -47,6 +40,12 @@ static struct of_dev_auxdata da850_auxdata_lookup[] __initdata = {
         OF_DEV_AUXDATA("ti,da850-ecap", 0x01f07000, "ecap", NULL),
         OF_DEV_AUXDATA("ti,da850-ecap", 0x01f08000, "ecap", NULL),
         OF_DEV_AUXDATA("ti,da830-spi", 0x01f0e000, "spi_davinci.1", NULL),
+        OF_DEV_AUXDATA("ns16550a", 0x01c42000, "serial8250.0", NULL),
+        OF_DEV_AUXDATA("ns16550a", 0x01d0c000, "serial8250.1", NULL),
+        OF_DEV_AUXDATA("ns16550a", 0x01d0d000, "serial8250.2", NULL),
+        OF_DEV_AUXDATA("ti,davinci_mdio", 0x01e24000, "davinci_mdio.0", NULL),
+        OF_DEV_AUXDATA("ti,davinci-dm6467-emac", 0x01e20000, "davinci_emac.1",
+                       NULL),
         {}
 };
 
@@ -57,7 +56,6 @@ static void __init da850_init_machine(void)
         of_platform_populate(NULL, of_default_bus_match_table,
                              da850_auxdata_lookup, NULL);
 
-        da8xx_uart_clk_enable();
 }
 
 static const char *da850_boards_compat[] __initdata = {
diff --git a/arch/arm/mach-davinci/davinci.h b/arch/arm/mach-davinci/davinci.h
index a883043d0820..2ab5d577186f 100644
--- a/arch/arm/mach-davinci/davinci.h
+++ b/arch/arm/mach-davinci/davinci.h
@@ -106,4 +106,9 @@ int dm646x_init_edma(struct edma_rsv_info *rsv);
 void dm646x_video_init(void);
 void dm646x_setup_vpif(struct vpif_display_config *,
                        struct vpif_capture_config *);
+
+extern struct platform_device dm365_serial_device[];
+extern struct platform_device dm355_serial_device[];
+extern struct platform_device dm644x_serial_device[];
+extern struct platform_device dm646x_serial_device[];
 #endif /*__DAVINCI_H */
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index 71a46a348761..2e473fefd71e 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -68,7 +68,7 @@
 void __iomem *da8xx_syscfg0_base;
 void __iomem *da8xx_syscfg1_base;
 
-static struct plat_serial8250_port da8xx_serial_pdata[] = {
+static struct plat_serial8250_port da8xx_serial0_pdata[] = {
         {
                 .mapbase        = DA8XX_UART0_BASE,
                 .irq            = IRQ_DA8XX_UARTINT0,
@@ -78,6 +78,11 @@ static struct plat_serial8250_port da8xx_serial_pdata[] = {
                 .regshift       = 2,
         },
         {
+                .flags  = 0,
+        }
+};
+static struct plat_serial8250_port da8xx_serial1_pdata[] = {
+        {
                 .mapbase        = DA8XX_UART1_BASE,
                 .irq            = IRQ_DA8XX_UARTINT1,
                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
@@ -86,6 +91,11 @@ static struct plat_serial8250_port da8xx_serial_pdata[] = {
                 .regshift       = 2,
         },
         {
+                .flags  = 0,
+        }
+};
+static struct plat_serial8250_port da8xx_serial2_pdata[] = {
+        {
                 .mapbase        = DA8XX_UART2_BASE,
                 .irq            = IRQ_DA8XX_UARTINT2,
                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
@@ -95,15 +105,33 @@ static struct plat_serial8250_port da8xx_serial_pdata[] = {
         },
         {
                 .flags  = 0,
-        },
+        }
 };
 
-struct platform_device da8xx_serial_device = {
-        .name   = "serial8250",
-        .id     = PLAT8250_DEV_PLATFORM,
-        .dev    = {
-                .platform_data  = da8xx_serial_pdata,
+struct platform_device da8xx_serial_device[] = {
+        {
+                .name   = "serial8250",
+                .id     = PLAT8250_DEV_PLATFORM,
+                .dev    = {
+                        .platform_data  = da8xx_serial0_pdata,
+                }
+        },
+        {
+                .name   = "serial8250",
+                .id     = PLAT8250_DEV_PLATFORM1,
+                .dev    = {
+                        .platform_data  = da8xx_serial1_pdata,
+                }
+        },
+        {
+                .name   = "serial8250",
+                .id     = PLAT8250_DEV_PLATFORM2,
+                .dev    = {
+                        .platform_data  = da8xx_serial2_pdata,
+                }
         },
+        {
+        }
 };
 
 static s8 da8xx_queue_tc_mapping[][2] = {
@@ -453,12 +481,8 @@ int __init da8xx_register_emac(void)
         ret = platform_device_register(&da8xx_mdio_device);
         if (ret < 0)
                 return ret;
-        ret = platform_device_register(&da8xx_emac_device);
-        if (ret < 0)
-                return ret;
-        ret = clk_add_alias(NULL, dev_name(&da8xx_mdio_device.dev),
-                            NULL, &da8xx_emac_device.dev);
-        return ret;
+
+        return platform_device_register(&da8xx_emac_device);
 }
 
 static struct resource da830_mcasp1_resources[] = {
@@ -828,14 +852,7 @@ static struct platform_device da8xx_rtc_device = {
 
 int da8xx_register_rtc(void)
 {
-        int ret;
-
-        ret = platform_device_register(&da8xx_rtc_device);
-        if (!ret)
-                /* Atleast on DA850, RTC is a wakeup source */
-                device_init_wakeup(&da8xx_rtc_device.dev, true);
-
-        return ret;
+        return platform_device_register(&da8xx_rtc_device);
 }
 
 static void __iomem *da8xx_ddr2_ctlr_base;
diff --git a/arch/arm/mach-davinci/devices-tnetv107x.c b/arch/arm/mach-davinci/devices-tnetv107x.c
index 128cb9ae80f4..01d8686e553c 100644
--- a/arch/arm/mach-davinci/devices-tnetv107x.c
+++ b/arch/arm/mach-davinci/devices-tnetv107x.c
@@ -126,7 +126,7 @@ static struct platform_device edma_device = {
         .dev.platform_data = tnetv107x_edma_info,
 };
 
-static struct plat_serial8250_port serial_data[] = {
+static struct plat_serial8250_port serial0_platform_data[] = {
         {
                 .mapbase        = TNETV107X_UART0_BASE,
                 .irq            = IRQ_TNETV107X_UART0,
@@ -137,6 +137,11 @@ static struct plat_serial8250_port serial_data[] = {
                 .regshift       = 2,
         },
         {
+                .flags  = 0,
+        }
+};
+static struct plat_serial8250_port serial1_platform_data[] = {
+        {
                 .mapbase        = TNETV107X_UART1_BASE,
                 .irq            = IRQ_TNETV107X_UART1,
                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
@@ -146,6 +151,11 @@ static struct plat_serial8250_port serial_data[] = {
                 .regshift       = 2,
         },
         {
+                .flags  = 0,
+        }
+};
+static struct plat_serial8250_port serial2_platform_data[] = {
+        {
                 .mapbase        = TNETV107X_UART2_BASE,
                 .irq            = IRQ_TNETV107X_UART2,
                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
@@ -156,13 +166,28 @@ static struct plat_serial8250_port serial_data[] = {
         },
         {
                 .flags  = 0,
-        },
+        }
 };
 
-struct platform_device tnetv107x_serial_device = {
-        .name                   = "serial8250",
-        .id                     = PLAT8250_DEV_PLATFORM,
-        .dev.platform_data      = serial_data,
+
+struct platform_device tnetv107x_serial_device[] = {
+        {
+                .name                   = "serial8250",
+                .id                     = PLAT8250_DEV_PLATFORM,
+                .dev.platform_data      = serial0_platform_data,
+        },
+        {
+                .name                   = "serial8250",
+                .id                     = PLAT8250_DEV_PLATFORM1,
+                .dev.platform_data      = serial1_platform_data,
+        },
+        {
+                .name                   = "serial8250",
+                .id                     = PLAT8250_DEV_PLATFORM2,
+                .dev.platform_data      = serial2_platform_data,
+        },
+        {
+        }
 };
 
 static struct resource mmc0_resources[] = {
@@ -385,7 +410,7 @@ void __init tnetv107x_devices_init(struct tnetv107x_device_info *info)
         platform_device_register(&tsc_device);
 
         if (info->serial_config)
-                davinci_serial_init(info->serial_config);
+                davinci_serial_init(tnetv107x_serial_device);
 
         for (i = 0; i < 2; i++)
                 if (info->mmc_config[i]) {
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 86100d179694..3eaa5f6b2160 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -357,9 +357,9 @@ static struct clk_lookup dm355_clks[] = {
         CLK(NULL, "clkout3", &clkout3_clk),
         CLK(NULL, "arm", &arm_clk),
         CLK(NULL, "mjcp", &mjcp_clk),
-        CLK(NULL, "uart0", &uart0_clk),
-        CLK(NULL, "uart1", &uart1_clk),
-        CLK(NULL, "uart2", &uart2_clk),
+        CLK("serial8250.0", NULL, &uart0_clk),
+        CLK("serial8250.1", NULL, &uart1_clk),
+        CLK("serial8250.2", NULL, &uart2_clk),
         CLK("i2c_davinci.1", NULL, &i2c_clk),
         CLK("davinci-mcbsp.0", NULL, &asp0_clk),
         CLK("davinci-mcbsp.1", NULL, &asp1_clk),
@@ -922,7 +922,7 @@ static struct davinci_timer_info dm355_timer_info = {
         .clocksource_id = T0_TOP,
 };
 
-static struct plat_serial8250_port dm355_serial_platform_data[] = {
+static struct plat_serial8250_port dm355_serial0_platform_data[] = {
         {
                 .mapbase        = DAVINCI_UART0_BASE,
                 .irq            = IRQ_UARTINT0,
@@ -932,6 +932,11 @@ static struct plat_serial8250_port dm355_serial_platform_data[] = {
                 .regshift       = 2,
         },
         {
+                .flags  = 0,
+        }
+};
+static struct plat_serial8250_port dm355_serial1_platform_data[] = {
+        {
                 .mapbase        = DAVINCI_UART1_BASE,
                 .irq            = IRQ_UARTINT1,
                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
@@ -940,6 +945,11 @@ static struct plat_serial8250_port dm355_serial_platform_data[] = {
                 .regshift       = 2,
         },
         {
+                .flags  = 0,
+        }
+};
+static struct plat_serial8250_port dm355_serial2_platform_data[] = {
+        {
                 .mapbase        = DM355_UART2_BASE,
                 .irq            = IRQ_DM355_UARTINT2,
                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
@@ -948,16 +958,34 @@ static struct plat_serial8250_port dm355_serial_platform_data[] = {
                 .regshift       = 2,
         },
         {
-                .flags          = 0
-        },
+                .flags  = 0,
+        }
 };
 
-static struct platform_device dm355_serial_device = {
-        .name                   = "serial8250",
-        .id                     = PLAT8250_DEV_PLATFORM,
-        .dev                    = {
-                .platform_data  = dm355_serial_platform_data,
+struct platform_device dm355_serial_device[] = {
+        {
+                .name                   = "serial8250",
+                .id                     = PLAT8250_DEV_PLATFORM,
+                .dev                    = {
+                        .platform_data  = dm355_serial0_platform_data,
+                }
+        },
+        {
+                .name                   = "serial8250",
+                .id                     = PLAT8250_DEV_PLATFORM1,
+                .dev                    = {
+                        .platform_data  = dm355_serial1_platform_data,
+                }
         },
+        {
+                .name                   = "serial8250",
+                .id                     = PLAT8250_DEV_PLATFORM2,
+                .dev                    = {
+                        .platform_data  = dm355_serial2_platform_data,
+                }
+        },
+        {
+        }
 };
 
 static struct davinci_soc_info davinci_soc_info_dm355 = {
@@ -981,7 +1009,6 @@ static struct davinci_soc_info davinci_soc_info_dm355 = {
         .gpio_base              = DAVINCI_GPIO_BASE,
         .gpio_num               = 104,
         .gpio_irq               = IRQ_DM355_GPIOBNK0,
-        .serial_dev             = &dm355_serial_device,
         .sram_dma               = 0x00010000,
         .sram_len               = SZ_32K,
 };
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index dad28029ba9b..c29e324eb0bb 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -455,8 +455,8 @@ static struct clk_lookup dm365_clks[] = {
         CLK("vpss", "master", &vpss_master_clk),
         CLK("vpss", "slave", &vpss_slave_clk),
         CLK(NULL, "arm", &arm_clk),
-        CLK(NULL, "uart0", &uart0_clk),
-        CLK(NULL, "uart1", &uart1_clk),
+        CLK("serial8250.0", NULL, &uart0_clk),
+        CLK("serial8250.1", NULL, &uart1_clk),
         CLK("i2c_davinci.1", NULL, &i2c_clk),
         CLK("da830-mmc.0", NULL, &mmcsd0_clk),
         CLK("da830-mmc.1", NULL, &mmcsd1_clk),
@@ -477,6 +477,7 @@ static struct clk_lookup dm365_clks[] = {
         CLK(NULL, "timer3", &timer3_clk),
         CLK(NULL, "usb", &usb_clk),
         CLK("davinci_emac.1", NULL, &emac_clk),
+        CLK("davinci_mdio.0", "fck", &emac_clk),
         CLK("davinci_voicecodec", NULL, &voicecodec_clk),
         CLK("davinci-mcbsp", NULL, &asp0_clk),
         CLK(NULL, "rto", &rto_clk),
@@ -1041,7 +1042,7 @@ static struct davinci_timer_info dm365_timer_info = {
 
 #define DM365_UART1_BASE        (IO_PHYS + 0x106000)
 
-static struct plat_serial8250_port dm365_serial_platform_data[] = {
+static struct plat_serial8250_port dm365_serial0_platform_data[] = {
         {
                 .mapbase        = DAVINCI_UART0_BASE,
                 .irq            = IRQ_UARTINT0,
@@ -1051,6 +1052,11 @@ static struct plat_serial8250_port dm365_serial_platform_data[] = {
                 .regshift       = 2,
         },
         {
+                .flags  = 0,
+        }
+};
+static struct plat_serial8250_port dm365_serial1_platform_data[] = {
+        {
                 .mapbase        = DM365_UART1_BASE,
                 .irq            = IRQ_UARTINT1,
                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
@@ -1059,16 +1065,27 @@ static struct plat_serial8250_port dm365_serial_platform_data[] = {
                 .regshift       = 2,
         },
         {
-                .flags          = 0
-        },
+                .flags  = 0,
+        }
 };
 
-static struct platform_device dm365_serial_device = {
-        .name                   = "serial8250",
-        .id                     = PLAT8250_DEV_PLATFORM,
-        .dev                    = {
-                .platform_data  = dm365_serial_platform_data,
+struct platform_device dm365_serial_device[] = {
+        {
+                .name                   = "serial8250",
+                .id                     = PLAT8250_DEV_PLATFORM,
+                .dev                    = {
+                        .platform_data  = dm365_serial0_platform_data,
+                }
+        },
+        {
+                .name                   = "serial8250",
+                .id                     = PLAT8250_DEV_PLATFORM1,
+                .dev                    = {
+                        .platform_data  = dm365_serial1_platform_data,
+                }
         },
+        {
+        }
 };
 
 static struct davinci_soc_info davinci_soc_info_dm365 = {
@@ -1093,7 +1110,6 @@ static struct davinci_soc_info davinci_soc_info_dm365 = {
         .gpio_num               = 104,
         .gpio_irq               = IRQ_DM365_GPIO0,
         .gpio_unbanked          = 8,    /* really 16 ... skip muxed GPIOs */
-        .serial_dev             = &dm365_serial_device,
         .emac_pdata             = &dm365_emac_pdata,
         .sram_dma               = 0x00010000,
         .sram_len               = SZ_32K,
@@ -1407,8 +1423,6 @@ static int __init dm365_init_devices(void)
 
         platform_device_register(&dm365_mdio_device);
         platform_device_register(&dm365_emac_device);
-        clk_add_alias(NULL, dev_name(&dm365_mdio_device.dev),
-                      NULL, &dm365_emac_device.dev);
 
         return 0;
 }
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index a49d18246fe9..4f74682293d6 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -303,10 +303,11 @@ static struct clk_lookup dm644x_clks[] = {
         CLK("vpss", "master", &vpss_master_clk),
         CLK("vpss", "slave", &vpss_slave_clk),
         CLK(NULL, "arm", &arm_clk),
-        CLK(NULL, "uart0", &uart0_clk),
-        CLK(NULL, "uart1", &uart1_clk),
-        CLK(NULL, "uart2", &uart2_clk),
+        CLK("serial8250.0", NULL, &uart0_clk),
+        CLK("serial8250.1", NULL, &uart1_clk),
+        CLK("serial8250.2", NULL, &uart2_clk),
         CLK("davinci_emac.1", NULL, &emac_clk),
+        CLK("davinci_mdio.0", "fck", &emac_clk),
         CLK("i2c_davinci.1", NULL, &i2c_clk),
         CLK("palm_bk3710", NULL, &ide_clk),
         CLK("davinci-mcbsp", NULL, &asp_clk),
@@ -813,7 +814,7 @@ static struct davinci_timer_info dm644x_timer_info = {
         .clocksource_id = T0_TOP,
 };
 
-static struct plat_serial8250_port dm644x_serial_platform_data[] = {
+static struct plat_serial8250_port dm644x_serial0_platform_data[] = {
         {
                 .mapbase        = DAVINCI_UART0_BASE,
                 .irq            = IRQ_UARTINT0,
@@ -823,6 +824,11 @@ static struct plat_serial8250_port dm644x_serial_platform_data[] = {
                 .regshift       = 2,
         },
         {
+                .flags  = 0,
+        }
+};
+static struct plat_serial8250_port dm644x_serial1_platform_data[] = {
+        {
                 .mapbase        = DAVINCI_UART1_BASE,
                 .irq            = IRQ_UARTINT1,
                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
@@ -831,6 +837,11 @@ static struct plat_serial8250_port dm644x_serial_platform_data[] = {
                 .regshift       = 2,
         },
         {
+                .flags  = 0,
+        }
+};
+static struct plat_serial8250_port dm644x_serial2_platform_data[] = {
+        {
                 .mapbase        = DAVINCI_UART2_BASE,
                 .irq            = IRQ_UARTINT2,
                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
@@ -839,16 +850,34 @@ static struct plat_serial8250_port dm644x_serial_platform_data[] = {
                 .regshift       = 2,
         },
         {
-                .flags          = 0
-        },
+                .flags  = 0,
+        }
 };
 
-static struct platform_device dm644x_serial_device = {
-        .name                   = "serial8250",
-        .id                     = PLAT8250_DEV_PLATFORM,
-        .dev                    = {
-                .platform_data  = dm644x_serial_platform_data,
+struct platform_device dm644x_serial_device[] = {
+        {
+                .name                   = "serial8250",
+                .id                     = PLAT8250_DEV_PLATFORM,
+                .dev                    = {
+                        .platform_data  = dm644x_serial0_platform_data,
+                }
         },
+        {
+                .name                   = "serial8250",
+                .id                     = PLAT8250_DEV_PLATFORM1,
+                .dev                    = {
+                        .platform_data  = dm644x_serial1_platform_data,
+                }
+        },
+        {
+                .name                   = "serial8250",
+                .id                     = PLAT8250_DEV_PLATFORM2,
+                .dev                    = {
+                        .platform_data  = dm644x_serial2_platform_data,
+                }
+        },
+        {
+        }
 };
 
 static struct davinci_soc_info davinci_soc_info_dm644x = {
@@ -872,7 +901,6 @@ static struct davinci_soc_info davinci_soc_info_dm644x = {
         .gpio_base              = DAVINCI_GPIO_BASE,
         .gpio_num               = 71,
         .gpio_irq               = IRQ_GPIOBNK0,
-        .serial_dev             = &dm644x_serial_device,
         .emac_pdata             = &dm644x_emac_pdata,
         .sram_dma               = 0x00008000,
         .sram_len               = SZ_16K,
@@ -923,8 +951,6 @@ static int __init dm644x_init_devices(void)
 
         platform_device_register(&dm644x_mdio_device);
         platform_device_register(&dm644x_emac_device);
-        clk_add_alias(NULL, dev_name(&dm644x_mdio_device.dev),
-                      NULL, &dm644x_emac_device.dev);
 
         return 0;
 }
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index d1259e80141b..68f8d1f1aca1 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -342,15 +342,16 @@ static struct clk_lookup dm646x_clks[] = {
         CLK(NULL, "edma_tc1", &edma_tc1_clk),
         CLK(NULL, "edma_tc2", &edma_tc2_clk),
         CLK(NULL, "edma_tc3", &edma_tc3_clk),
-        CLK(NULL, "uart0", &uart0_clk),
-        CLK(NULL, "uart1", &uart1_clk),
-        CLK(NULL, "uart2", &uart2_clk),
+        CLK("serial8250.0", NULL, &uart0_clk),
+        CLK("serial8250.1", NULL, &uart1_clk),
+        CLK("serial8250.2", NULL, &uart2_clk),
         CLK("i2c_davinci.1", NULL, &i2c_clk),
         CLK(NULL, "gpio", &gpio_clk),
         CLK("davinci-mcasp.0", NULL, &mcasp0_clk),
         CLK("davinci-mcasp.1", NULL, &mcasp1_clk),
         CLK(NULL, "aemif", &aemif_clk),
         CLK("davinci_emac.1", NULL, &emac_clk),
+        CLK("davinci_mdio.0", "fck", &emac_clk),
         CLK(NULL, "pwm0", &pwm0_clk),
         CLK(NULL, "pwm1", &pwm1_clk),
         CLK(NULL, "timer0", &timer0_clk),
@@ -790,7 +791,7 @@ static struct davinci_timer_info dm646x_timer_info = {
         .clocksource_id = T0_TOP,
 };
 
-static struct plat_serial8250_port dm646x_serial_platform_data[] = {
+static struct plat_serial8250_port dm646x_serial0_platform_data[] = {
         {
                 .mapbase        = DAVINCI_UART0_BASE,
                 .irq            = IRQ_UARTINT0,
@@ -800,6 +801,11 @@ static struct plat_serial8250_port dm646x_serial_platform_data[] = {
                 .regshift       = 2,
         },
         {
+                .flags  = 0,
+        }
+};
+static struct plat_serial8250_port dm646x_serial1_platform_data[] = {
+        {
                 .mapbase        = DAVINCI_UART1_BASE,
                 .irq            = IRQ_UARTINT1,
                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
@@ -808,6 +814,11 @@ static struct plat_serial8250_port dm646x_serial_platform_data[] = {
                 .regshift       = 2,
         },
         {
+                .flags  = 0,
+        }
+};
+static struct plat_serial8250_port dm646x_serial2_platform_data[] = {
+        {
                 .mapbase        = DAVINCI_UART2_BASE,
                 .irq            = IRQ_DM646X_UARTINT2,
                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
@@ -816,16 +827,34 @@ static struct plat_serial8250_port dm646x_serial_platform_data[] = {
                 .regshift       = 2,
         },
         {
-                .flags          = 0
-        },
+                .flags  = 0,
+        }
 };
 
-static struct platform_device dm646x_serial_device = {
-        .name                   = "serial8250",
-        .id                     = PLAT8250_DEV_PLATFORM,
-        .dev                    = {
-                .platform_data  = dm646x_serial_platform_data,
+struct platform_device dm646x_serial_device[] = {
+        {
+                .name                   = "serial8250",
+                .id                     = PLAT8250_DEV_PLATFORM,
+                .dev                    = {
+                        .platform_data  = dm646x_serial0_platform_data,
+                }
+        },
+        {
+                .name                   = "serial8250",
+                .id                     = PLAT8250_DEV_PLATFORM1,
+                .dev                    = {
+                        .platform_data  = dm646x_serial1_platform_data,
+                }
         },
+        {
+                .name                   = "serial8250",
+                .id                     = PLAT8250_DEV_PLATFORM2,
+                .dev                    = {
+                        .platform_data  = dm646x_serial2_platform_data,
+                }
+        },
+        {
+        }
 };
 
 static struct davinci_soc_info davinci_soc_info_dm646x = {
@@ -849,7 +878,6 @@ static struct davinci_soc_info davinci_soc_info_dm646x = {
         .gpio_base              = DAVINCI_GPIO_BASE,
         .gpio_num               = 43, /* Only 33 usable */
         .gpio_irq               = IRQ_DM646X_GPIOBNK0,
-        .serial_dev             = &dm646x_serial_device,
         .emac_pdata             = &dm646x_emac_pdata,
         .sram_dma               = 0x10010000,
         .sram_len               = SZ_32K,
@@ -913,8 +941,6 @@ static int __init dm646x_init_devices(void)
 
         platform_device_register(&dm646x_mdio_device);
         platform_device_register(&dm646x_emac_device);
-        clk_add_alias(NULL, dev_name(&dm646x_mdio_device.dev),
-                      NULL, &dm646x_emac_device.dev);
 
         return 0;
 }
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index cce316b92c06..0b3c169758ed 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -72,7 +72,6 @@ struct davinci_soc_info {
         unsigned                        gpio_unbanked;
         struct davinci_gpio_controller  *gpio_ctlrs;
         int                             gpio_ctlrs_num;
-        struct platform_device          *serial_dev;
         struct emac_platform_data       *emac_pdata;
         dma_addr_t                      sram_dma;
         unsigned                        sram_len;
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index 7b41a5e9bc31..aae53072c0eb 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -111,7 +111,7 @@ void da8xx_restart(enum reboot_mode mode, const char *cmd);
 void da8xx_rproc_reserve_cma(void);
 int da8xx_register_rproc(void);
 
-extern struct platform_device da8xx_serial_device;
+extern struct platform_device da8xx_serial_device[];
 extern struct emac_platform_data da8xx_emac_pdata;
 extern struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata;
 extern struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata;
diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h
index 62ad300440f5..52b8571b2e70 100644
--- a/arch/arm/mach-davinci/include/mach/serial.h
+++ b/arch/arm/mach-davinci/include/mach/serial.h
@@ -15,6 +15,8 @@
 
 #include <mach/hardware.h>
 
+#include <linux/platform_device.h>
+
 #define DAVINCI_UART0_BASE      (IO_PHYS + 0x20000)
 #define DAVINCI_UART1_BASE      (IO_PHYS + 0x20400)
 #define DAVINCI_UART2_BASE      (IO_PHYS + 0x20800)
@@ -37,13 +39,7 @@
 #define UART_DM646X_SCR_TX_WATERMARK    0x08
 
 #ifndef __ASSEMBLY__
-struct davinci_uart_config {
-        /* Bit field of UARTs present; bit 0 --> UART0 */
-        unsigned int enabled_uarts;
-};
-
-extern int davinci_serial_init(struct davinci_uart_config *);
-extern int davinci_serial_setup_clk(unsigned instance, unsigned int *rate);
+extern int davinci_serial_init(struct platform_device *);
 #endif
 
 #endif /* __ASM_ARCH_SERIAL_H */
diff --git a/arch/arm/mach-davinci/include/mach/tnetv107x.h b/arch/arm/mach-davinci/include/mach/tnetv107x.h
index 16314c64f755..494fcf5ccfe1 100644
--- a/arch/arm/mach-davinci/include/mach/tnetv107x.h
+++ b/arch/arm/mach-davinci/include/mach/tnetv107x.h
@@ -42,7 +42,6 @@
 #include <mach/serial.h>
 
 struct tnetv107x_device_info {
-        struct davinci_uart_config      *serial_config;
         struct davinci_mmc_config       *mmc_config[2];  /* 2 controllers */
         struct davinci_nand_pdata       *nand_config[4]; /* 4 chipsels */
         struct matrix_keypad_platform_data *keypad_config;
@@ -50,7 +49,7 @@ struct tnetv107x_device_info {
 };
 
 extern struct platform_device tnetv107x_wdt_device;
-extern struct platform_device tnetv107x_serial_device;
+extern struct platform_device tnetv107x_serial_device[];
 
 extern void tnetv107x_init(void);
 extern void tnetv107x_devices_init(struct tnetv107x_device_info *);
diff --git a/arch/arm/mach-davinci/serial.c b/arch/arm/mach-davinci/serial.c
index f2625814c3c9..5e93a734c858 100644
--- a/arch/arm/mach-davinci/serial.c
+++ b/arch/arm/mach-davinci/serial.c
@@ -70,49 +70,36 @@ static void __init davinci_serial_reset(struct plat_serial8250_port *p)
                                  UART_DM646X_SCR_TX_WATERMARK);
 }
 
-/* Enable UART clock and obtain its rate */
-int __init davinci_serial_setup_clk(unsigned instance, unsigned int *rate)
+int __init davinci_serial_init(struct platform_device *serial_dev)
 {
-        char name[16];
+        int i, ret = 0;
+        struct device *dev;
+        struct plat_serial8250_port *p;
         struct clk *clk;
-        struct davinci_soc_info *soc_info = &davinci_soc_info;
-        struct device *dev = &soc_info->serial_dev->dev;
-
-        sprintf(name, "uart%d", instance);
-        clk = clk_get(dev, name);
-        if (IS_ERR(clk)) {
-                pr_err("%s:%d: failed to get UART%d clock\n",
-                                        __func__, __LINE__, instance);
-                return PTR_ERR(clk);
-        }
-
-        clk_prepare_enable(clk);
-
-        if (rate)
-                *rate = clk_get_rate(clk);
-
-        return 0;
-}
-
-int __init davinci_serial_init(struct davinci_uart_config *info)
-{
-        int i, ret;
-        struct davinci_soc_info *soc_info = &davinci_soc_info;
-        struct device *dev = &soc_info->serial_dev->dev;
-        struct plat_serial8250_port *p = dev->platform_data;
 
         /*
          * Make sure the serial ports are muxed on at this point.
          * You have to mux them off in device drivers later on if not needed.
          */
-        for (i = 0; p->flags; i++, p++) {
-                if (!(info->enabled_uarts & (1 << i)))
-                        continue;
+        for (i = 0; serial_dev[i].dev.platform_data != NULL; i++) {
+                dev = &serial_dev[i].dev;
+                p = dev->platform_data;
 
-                ret = davinci_serial_setup_clk(i, &p->uartclk);
+                ret = platform_device_register(&serial_dev[i]);
                 if (ret)
                         continue;
 
+                clk = clk_get(dev, NULL);
+                if (IS_ERR(clk)) {
+                        pr_err("%s:%d: failed to get UART%d clock\n",
+                               __func__, __LINE__, i);
+                        continue;
+                }
+
+                clk_prepare_enable(clk);
+
+                p->uartclk = clk_get_rate(clk);
+
                 if (!p->membase && p->mapbase) {
                         p->membase = ioremap(p->mapbase, SZ_4K);
 
@@ -125,6 +112,5 @@ int __init davinci_serial_init(struct davinci_uart_config *info)
                 if (p->membase && p->type != PORT_AR7)
                         davinci_serial_reset(p);
         }
-
-        return platform_device_register(soc_info->serial_dev);
+        return ret;
 }
diff --git a/arch/arm/mach-davinci/tnetv107x.c b/arch/arm/mach-davinci/tnetv107x.c
index 4545667ecd3c..f4d7fbb24b3b 100644
--- a/arch/arm/mach-davinci/tnetv107x.c
+++ b/arch/arm/mach-davinci/tnetv107x.c
@@ -264,7 +264,7 @@ static struct clk_lookup clks[] = {
         CLK(NULL,               "clk_chipcfg",          &clk_chipcfg),
         CLK("tnetv107x-ts.0",   NULL,                   &clk_tsc),
         CLK(NULL,               "clk_rom",              &clk_rom),
-        CLK(NULL,               "uart2",                &clk_uart2),
+        CLK("serial8250.2",     NULL,                   &clk_uart2),
         CLK(NULL,               "clk_pktsec",           &clk_pktsec),
         CLK("tnetv107x-rng.0",  NULL,                   &clk_rng),
         CLK("tnetv107x-pka.0",  NULL,                   &clk_pka),
@@ -274,8 +274,8 @@ static struct clk_lookup clks[] = {
         CLK(NULL,               "clk_gpio",             &clk_gpio),
         CLK(NULL,               "clk_mdio",             &clk_mdio),
         CLK("dm6441-mmc.0",     NULL,                   &clk_sdio0),
-        CLK(NULL,               "uart0",                &clk_uart0),
-        CLK(NULL,               "uart1",                &clk_uart1),
+        CLK("serial8250.0",     NULL,                   &clk_uart0),
+        CLK("serial8250.1",     NULL,                   &clk_uart1),
         CLK(NULL,               "timer0",               &clk_timer0),
         CLK(NULL,               "timer1",               &clk_timer1),
         CLK("tnetv107x_wdt.0",  NULL,                   &clk_wdt_arm),
@@ -757,7 +757,7 @@ static struct davinci_soc_info tnetv107x_soc_info = {
         .gpio_type              = GPIO_TYPE_TNETV107X,
         .gpio_num               = TNETV107X_N_GPIO,
         .timer_info             = &timer_info,
-        .serial_dev             = &tnetv107x_serial_device,
+        .serial_dev             = tnetv107x_serial_device,
 };
 
 void __init tnetv107x_init(void)
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index 304f069ebf50..c122bcff9f7c 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -27,6 +27,22 @@
 #include <plat/time.h>
 #include "common.h"
 
+/* These can go away once Dove uses the mvebu-mbus DT binding */
+#define DOVE_MBUS_PCIE0_MEM_TARGET    0x4
+#define DOVE_MBUS_PCIE0_MEM_ATTR      0xe8
+#define DOVE_MBUS_PCIE0_IO_TARGET     0x4
+#define DOVE_MBUS_PCIE0_IO_ATTR       0xe0
+#define DOVE_MBUS_PCIE1_MEM_TARGET    0x8
+#define DOVE_MBUS_PCIE1_MEM_ATTR      0xe8
+#define DOVE_MBUS_PCIE1_IO_TARGET     0x8
+#define DOVE_MBUS_PCIE1_IO_ATTR       0xe0
+#define DOVE_MBUS_CESA_TARGET         0x3
+#define DOVE_MBUS_CESA_ATTR           0x1
+#define DOVE_MBUS_BOOTROM_TARGET      0x1
+#define DOVE_MBUS_BOOTROM_ATTR        0xfd
+#define DOVE_MBUS_SCRATCHPAD_TARGET   0xd
+#define DOVE_MBUS_SCRATCHPAD_ATTR     0x0
+
 /*****************************************************************************
  * I/O Address Mapping
  ****************************************************************************/
@@ -332,34 +348,40 @@ void __init dove_setup_cpu_wins(void)
 {
         /*
          * The PCIe windows will no longer be statically allocated
-         * here once Dove is migrated to the pci-mvebu driver.
+         * here once Dove is migrated to the pci-mvebu driver. The
+         * non-PCIe windows will no longer be created here once Dove
+         * fully moves to DT.
          */
-        mvebu_mbus_add_window_remap_flags("pcie0.0",
+        mvebu_mbus_add_window_remap_by_id(DOVE_MBUS_PCIE0_IO_TARGET,
+                                          DOVE_MBUS_PCIE0_IO_ATTR,
                                           DOVE_PCIE0_IO_PHYS_BASE,
                                           DOVE_PCIE0_IO_SIZE,
-                                          DOVE_PCIE0_IO_BUS_BASE,
-                                          MVEBU_MBUS_PCI_IO);
-        mvebu_mbus_add_window_remap_flags("pcie1.0",
+                                          DOVE_PCIE0_IO_BUS_BASE);
+        mvebu_mbus_add_window_remap_by_id(DOVE_MBUS_PCIE1_IO_TARGET,
+                                          DOVE_MBUS_PCIE1_IO_ATTR,
                                           DOVE_PCIE1_IO_PHYS_BASE,
                                           DOVE_PCIE1_IO_SIZE,
-                                          DOVE_PCIE1_IO_BUS_BASE,
-                                          MVEBU_MBUS_PCI_IO);
-        mvebu_mbus_add_window_remap_flags("pcie0.0",
-                                          DOVE_PCIE0_MEM_PHYS_BASE,
-                                          DOVE_PCIE0_MEM_SIZE,
-                                          MVEBU_MBUS_NO_REMAP,
-                                          MVEBU_MBUS_PCI_MEM);
-        mvebu_mbus_add_window_remap_flags("pcie1.0",
-                                          DOVE_PCIE1_MEM_PHYS_BASE,
-                                          DOVE_PCIE1_MEM_SIZE,
-                                          MVEBU_MBUS_NO_REMAP,
-                                          MVEBU_MBUS_PCI_MEM);
-        mvebu_mbus_add_window("cesa", DOVE_CESA_PHYS_BASE,
-                              DOVE_CESA_SIZE);
-        mvebu_mbus_add_window("bootrom", DOVE_BOOTROM_PHYS_BASE,
-                              DOVE_BOOTROM_SIZE);
-        mvebu_mbus_add_window("scratchpad", DOVE_SCRATCHPAD_PHYS_BASE,
-                              DOVE_SCRATCHPAD_SIZE);
+                                          DOVE_PCIE1_IO_BUS_BASE);
+        mvebu_mbus_add_window_by_id(DOVE_MBUS_PCIE0_MEM_TARGET,
+                                    DOVE_MBUS_PCIE0_MEM_ATTR,
+                                    DOVE_PCIE0_MEM_PHYS_BASE,
+                                    DOVE_PCIE0_MEM_SIZE);
+        mvebu_mbus_add_window_by_id(DOVE_MBUS_PCIE1_MEM_TARGET,
+                                    DOVE_MBUS_PCIE1_MEM_ATTR,
+                                    DOVE_PCIE1_MEM_PHYS_BASE,
+                                    DOVE_PCIE1_MEM_SIZE);
+        mvebu_mbus_add_window_by_id(DOVE_MBUS_CESA_TARGET,
+                                    DOVE_MBUS_CESA_ATTR,
+                                    DOVE_CESA_PHYS_BASE,
+                                    DOVE_CESA_SIZE);
+        mvebu_mbus_add_window_by_id(DOVE_MBUS_BOOTROM_TARGET,
+                                    DOVE_MBUS_BOOTROM_ATTR,
+                                    DOVE_BOOTROM_PHYS_BASE,
+                                    DOVE_BOOTROM_SIZE);
+        mvebu_mbus_add_window_by_id(DOVE_MBUS_SCRATCHPAD_TARGET,
+                                    DOVE_MBUS_SCRATCHPAD_ATTR,
+                                    DOVE_SCRATCHPAD_PHYS_BASE,
+                                    DOVE_SCRATCHPAD_SIZE);
 }
 
 void __init dove_init(void)
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 1303e334c343..29a8af6922a8 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -1,6 +1,7 @@
 config ARCH_MXC
         bool "Freescale i.MX family" if ARCH_MULTI_V4_V5 || ARCH_MULTI_V6_V7
         select ARCH_REQUIRE_GPIOLIB
+        select ARM_CPU_SUSPEND if PM
         select ARM_PATCH_PHYS_VIRT
         select AUTO_ZRELADDR if !ZBOOT_ROM
         select CLKDEV_LOOKUP
@@ -8,6 +9,7 @@ config ARCH_MXC
         select GENERIC_ALLOCATOR
         select GENERIC_CLOCKEVENTS
         select GENERIC_IRQ_CHIP
+        select MIGHT_HAVE_CACHE_L2X0 if ARCH_MULTI_V6_V7
         select MULTI_IRQ_HANDLER
         select SPARSE_IRQ
         select USE_OF
@@ -785,7 +787,6 @@ config SOC_IMX6Q
         bool "i.MX6 Quad/DualLite support"
         select ARCH_HAS_CPUFREQ
         select ARCH_HAS_OPP
-        select ARM_CPU_SUSPEND if PM
         select ARM_ERRATA_754322
         select ARM_ERRATA_764369 if SMP
         select ARM_ERRATA_775420
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index e20f22d58fd8..5383c589ad71 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -15,7 +15,8 @@ imx5-pm-$(CONFIG_PM) += pm-imx5.o
 obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o $(imx5-pm-y)
 
 obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \
-                            clk-pfd.o clk-busy.o clk.o
+                            clk-pfd.o clk-busy.o clk.o \
+                            clk-fixup-div.o clk-fixup-mux.o
 
 obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o
 obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
diff --git a/arch/arm/mach-imx/anatop.c b/arch/arm/mach-imx/anatop.c
index 0cfa07dd9aa4..ad3b755abb78 100644
--- a/arch/arm/mach-imx/anatop.c
+++ b/arch/arm/mach-imx/anatop.c
@@ -66,7 +66,7 @@ void imx_anatop_post_resume(void)
         imx_anatop_enable_weak2p5(false);
 }
 
-void imx_anatop_usb_chrg_detect_disable(void)
+static void imx_anatop_usb_chrg_detect_disable(void)
 {
         regmap_write(anatop, ANADIG_USB1_CHRG_DETECT,
                 BM_ANADIG_USB_CHRG_DETECT_EN_B
@@ -100,4 +100,6 @@ void __init imx_anatop_init(void)
                 pr_err("%s: failed to find imx6q-anatop regmap!\n", __func__);
                 return;
         }
+
+        imx_anatop_usb_chrg_detect_disable();
 }
diff --git a/arch/arm/mach-imx/clk-fixup-div.c b/arch/arm/mach-imx/clk-fixup-div.c
new file mode 100644
index 000000000000..21db020b1f2d
--- /dev/null
+++ b/arch/arm/mach-imx/clk-fixup-div.c
@@ -0,0 +1,129 @@
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include "clk.h"
+
+#define to_clk_div(_hw) container_of(_hw, struct clk_divider, hw)
+#define div_mask(d)     ((1 << (d->width)) - 1)
+
+/**
+ * struct clk_fixup_div - imx integer fixup divider clock
+ * @divider: the parent class
+ * @ops: pointer to clk_ops of parent class
+ * @fixup: a hook to fixup the write value
+ *
+ * The imx fixup divider clock is a subclass of basic clk_divider
+ * with an addtional fixup hook.
+ */
+struct clk_fixup_div {
+        struct clk_divider divider;
+        const struct clk_ops *ops;
+        void (*fixup)(u32 *val);
+};
+
+static inline struct clk_fixup_div *to_clk_fixup_div(struct clk_hw *hw)
+{
+        struct clk_divider *divider = to_clk_div(hw);
+
+        return container_of(divider, struct clk_fixup_div, divider);
+}
+
+static unsigned long clk_fixup_div_recalc_rate(struct clk_hw *hw,
+                                         unsigned long parent_rate)
+{
+        struct clk_fixup_div *fixup_div = to_clk_fixup_div(hw);
+
+        return fixup_div->ops->recalc_rate(&fixup_div->divider.hw, parent_rate);
+}
+
+static long clk_fixup_div_round_rate(struct clk_hw *hw, unsigned long rate,
+                               unsigned long *prate)
+{
+        struct clk_fixup_div *fixup_div = to_clk_fixup_div(hw);
+
+        return fixup_div->ops->round_rate(&fixup_div->divider.hw, rate, prate);
+}
+
+static int clk_fixup_div_set_rate(struct clk_hw *hw, unsigned long rate,
+                            unsigned long parent_rate)
+{
+        struct clk_fixup_div *fixup_div = to_clk_fixup_div(hw);
+        struct clk_divider *div = to_clk_div(hw);
+        unsigned int divider, value;
+        unsigned long flags = 0;
+        u32 val;
+
+        divider = parent_rate / rate;
+
+        /* Zero based divider */
+        value = divider - 1;
+
+        if (value > div_mask(div))
+                value = div_mask(div);
+
+        spin_lock_irqsave(div->lock, flags);
+
+        val = readl(div->reg);
+        val &= ~(div_mask(div) << div->shift);
+        val |= value << div->shift;
+        fixup_div->fixup(&val);
+        writel(val, div->reg);
+
+        spin_unlock_irqrestore(div->lock, flags);
+
+        return 0;
+}
+
+static const struct clk_ops clk_fixup_div_ops = {
+        .recalc_rate = clk_fixup_div_recalc_rate,
+        .round_rate = clk_fixup_div_round_rate,
+        .set_rate = clk_fixup_div_set_rate,
+};
+
+struct clk *imx_clk_fixup_divider(const char *name, const char *parent,
+                                  void __iomem *reg, u8 shift, u8 width,
+                                  void (*fixup)(u32 *val))
+{
+        struct clk_fixup_div *fixup_div;
+        struct clk *clk;
+        struct clk_init_data init;
+
+        if (!fixup)
+                return ERR_PTR(-EINVAL);
+
+        fixup_div = kzalloc(sizeof(*fixup_div), GFP_KERNEL);
+        if (!fixup_div)
+                return ERR_PTR(-ENOMEM);
+
+        init.name = name;
+        init.ops = &clk_fixup_div_ops;
+        init.flags = CLK_SET_RATE_PARENT;
+        init.parent_names = parent ? &parent : NULL;
+        init.num_parents = parent ? 1 : 0;
+
+        fixup_div->divider.reg = reg;
+        fixup_div->divider.shift = shift;
+        fixup_div->divider.width = width;
+        fixup_div->divider.lock = &imx_ccm_lock;
+        fixup_div->divider.hw.init = &init;
+        fixup_div->ops = &clk_divider_ops;
+        fixup_div->fixup = fixup;
+
+        clk = clk_register(NULL, &fixup_div->divider.hw);
+        if (IS_ERR(clk))
+                kfree(fixup_div);
+
+        return clk;
+}
diff --git a/arch/arm/mach-imx/clk-fixup-mux.c b/arch/arm/mach-imx/clk-fixup-mux.c
new file mode 100644
index 000000000000..deb4b8093b30
--- /dev/null
+++ b/arch/arm/mach-imx/clk-fixup-mux.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include "clk.h"
+
+#define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
+
+/**
+ * struct clk_fixup_mux - imx integer fixup multiplexer clock
+ * @mux: the parent class
+ * @ops: pointer to clk_ops of parent class
+ * @fixup: a hook to fixup the write value
+ *
+ * The imx fixup multiplexer clock is a subclass of basic clk_mux
+ * with an addtional fixup hook.
+ */
+struct clk_fixup_mux {
+        struct clk_mux mux;
+        const struct clk_ops *ops;
+        void (*fixup)(u32 *val);
+};
+
+static inline struct clk_fixup_mux *to_clk_fixup_mux(struct clk_hw *hw)
+{
+        struct clk_mux *mux = to_clk_mux(hw);
+
+        return container_of(mux, struct clk_fixup_mux, mux);
+}
+
+static u8 clk_fixup_mux_get_parent(struct clk_hw *hw)
+{
+        struct clk_fixup_mux *fixup_mux = to_clk_fixup_mux(hw);
+
+        return fixup_mux->ops->get_parent(&fixup_mux->mux.hw);
+}
+
+static int clk_fixup_mux_set_parent(struct clk_hw *hw, u8 index)
+{
+        struct clk_fixup_mux *fixup_mux = to_clk_fixup_mux(hw);
+        struct clk_mux *mux = to_clk_mux(hw);
+        unsigned long flags = 0;
+        u32 val;
+
+        spin_lock_irqsave(mux->lock, flags);
+
+        val = readl(mux->reg);
+        val &= ~(mux->mask << mux->shift);
+        val |= index << mux->shift;
+        fixup_mux->fixup(&val);
+        writel(val, mux->reg);
+
+        spin_unlock_irqrestore(mux->lock, flags);
+
+        return 0;
+}
+
+static const struct clk_ops clk_fixup_mux_ops = {
+        .get_parent = clk_fixup_mux_get_parent,
+        .set_parent = clk_fixup_mux_set_parent,
+};
+
+struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg,
+                              u8 shift, u8 width, const char **parents,
+                              int num_parents, void (*fixup)(u32 *val))
+{
+        struct clk_fixup_mux *fixup_mux;
+        struct clk *clk;
+        struct clk_init_data init;
+
+        if (!fixup)
+                return ERR_PTR(-EINVAL);
+
+        fixup_mux = kzalloc(sizeof(*fixup_mux), GFP_KERNEL);
+        if (!fixup_mux)
+                return ERR_PTR(-ENOMEM);
+
+        init.name = name;
+        init.ops = &clk_fixup_mux_ops;
+        init.parent_names = parents;
+        init.num_parents = num_parents;
+
+        fixup_mux->mux.reg = reg;
+        fixup_mux->mux.shift = shift;
+        fixup_mux->mux.mask = BIT(width) - 1;
+        fixup_mux->mux.lock = &imx_ccm_lock;
+        fixup_mux->mux.hw.init = &init;
+        fixup_mux->ops = &clk_mux_ops;
+        fixup_mux->fixup = fixup;
+
+        clk = clk_register(NULL, &fixup_mux->mux.hw);
+        if (IS_ERR(clk))
+                kfree(fixup_mux);
+
+        return clk;
+}
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index 9afac26fa1cc..1a56a3319997 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -119,7 +119,7 @@ enum imx5_clks {
         srtc_gate, pata_gate, sata_gate, spdif_xtal_sel, spdif0_sel,
         spdif1_sel, spdif0_pred, spdif0_podf, spdif1_pred, spdif1_podf,
         spdif0_com_s, spdif1_com_sel, spdif0_gate, spdif1_gate, spdif_ipg_gate,
-        clk_max
+        ocram, clk_max
 };
 
 static struct clk *clk[clk_max];
@@ -506,6 +506,7 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
                                 mx53_can_sel, ARRAY_SIZE(mx53_can_sel));
         clk[can1_serial_gate] = imx_clk_gate2("can1_serial_gate", "can_sel", MXC_CCM_CCGR6, 22);
         clk[can1_ipg_gate] = imx_clk_gate2("can1_ipg_gate", "ipg", MXC_CCM_CCGR6, 20);
+        clk[ocram] = imx_clk_gate2("ocram", "ahb", MXC_CCM_CCGR6, 2);
         clk[can2_serial_gate] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8);
         clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6);
         clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 86567d980b07..9181a241d3a8 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -206,6 +206,17 @@ static const char *vpu_axi_sels[]	= { "axi", "pll2_pfd2_396m", "pll2_pfd0_352m",
 static const char *cko1_sels[]  = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div",
                                     "dummy", "axi", "enfc", "ipu1_di0", "ipu1_di1", "ipu2_di0",
                                     "ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_post_div", };
+static const char *cko2_sels[] = {
+        "mmdc_ch0_axi", "mmdc_ch1_axi", "usdhc4", "usdhc1",
+        "gpu2d_axi", "dummy", "ecspi_root", "gpu3d_axi",
+        "usdhc3", "dummy", "arm", "ipu1",
+        "ipu2", "vdo_axi", "osc", "gpu2d_core",
+        "gpu3d_core", "usdhc2", "ssi1", "ssi2",
+        "ssi3", "gpu3d_shader", "vpu_axi", "can_root",
+        "ldb_di0", "ldb_di1", "esai", "eim_slow",
+        "uart_serial", "spdif", "asrc", "hsi_tx",
+};
+static const char *cko_sels[] = { "cko1", "cko2", };
 
 enum mx6q_clks {
         dummy, ckil, ckih, osc, pll2_pfd0_352m, pll2_pfd1_594m, pll2_pfd2_396m,
@@ -239,7 +250,8 @@ enum mx6q_clks {
         pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg,
         ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5,
         sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate,
-        usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow, clk_max
+        usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow,
+        spdif, cko2_sel, cko2_podf, cko2, cko, vdoa, clk_max
 };
 
 static struct clk *clk[clk_max];
@@ -276,6 +288,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
         struct device_node *np;
         void __iomem *base;
         int i, irq;
+        int ret;
 
         clk[dummy] = imx_clk_fixed("dummy", 0);
         clk[ckil] = imx_obtain_fixed_clock("ckil", 0);
@@ -384,19 +397,21 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
         clk[ipu2_di1_sel]     = imx_clk_mux("ipu2_di1_sel",     base + 0x38, 9,  3, ipu2_di1_sels,     ARRAY_SIZE(ipu2_di1_sels));
         clk[hsi_tx_sel]       = imx_clk_mux("hsi_tx_sel",       base + 0x30, 28, 1, hsi_tx_sels,       ARRAY_SIZE(hsi_tx_sels));
         clk[pcie_axi_sel]     = imx_clk_mux("pcie_axi_sel",     base + 0x18, 10, 1, pcie_axi_sels,     ARRAY_SIZE(pcie_axi_sels));
-        clk[ssi1_sel]         = imx_clk_mux("ssi1_sel",         base + 0x1c, 10, 2, ssi_sels,          ARRAY_SIZE(ssi_sels));
-        clk[ssi2_sel]         = imx_clk_mux("ssi2_sel",         base + 0x1c, 12, 2, ssi_sels,          ARRAY_SIZE(ssi_sels));
-        clk[ssi3_sel]         = imx_clk_mux("ssi3_sel",         base + 0x1c, 14, 2, ssi_sels,          ARRAY_SIZE(ssi_sels));
-        clk[usdhc1_sel]       = imx_clk_mux("usdhc1_sel",       base + 0x1c, 16, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels));
-        clk[usdhc2_sel]       = imx_clk_mux("usdhc2_sel",       base + 0x1c, 17, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels));
-        clk[usdhc3_sel]       = imx_clk_mux("usdhc3_sel",       base + 0x1c, 18, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels));
-        clk[usdhc4_sel]       = imx_clk_mux("usdhc4_sel",       base + 0x1c, 19, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels));
+        clk[ssi1_sel]         = imx_clk_fixup_mux("ssi1_sel",   base + 0x1c, 10, 2, ssi_sels,          ARRAY_SIZE(ssi_sels),          imx_cscmr1_fixup);
+        clk[ssi2_sel]         = imx_clk_fixup_mux("ssi2_sel",   base + 0x1c, 12, 2, ssi_sels,          ARRAY_SIZE(ssi_sels),          imx_cscmr1_fixup);
+        clk[ssi3_sel]         = imx_clk_fixup_mux("ssi3_sel",   base + 0x1c, 14, 2, ssi_sels,          ARRAY_SIZE(ssi_sels),          imx_cscmr1_fixup);
+        clk[usdhc1_sel]       = imx_clk_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels),        imx_cscmr1_fixup);
+        clk[usdhc2_sel]       = imx_clk_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels),        imx_cscmr1_fixup);
+        clk[usdhc3_sel]       = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels),        imx_cscmr1_fixup);
+        clk[usdhc4_sel]       = imx_clk_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels),        imx_cscmr1_fixup);
         clk[enfc_sel]         = imx_clk_mux("enfc_sel",         base + 0x2c, 16, 2, enfc_sels,         ARRAY_SIZE(enfc_sels));
-        clk[emi_sel]          = imx_clk_mux("emi_sel",          base + 0x1c, 27, 2, emi_sels,          ARRAY_SIZE(emi_sels));
-        clk[emi_slow_sel]     = imx_clk_mux("emi_slow_sel",     base + 0x1c, 29, 2, emi_slow_sels,     ARRAY_SIZE(emi_slow_sels));
+        clk[emi_sel]          = imx_clk_fixup_mux("emi_sel",      base + 0x1c, 27, 2, emi_sels,        ARRAY_SIZE(emi_sels),          imx_cscmr1_fixup);
+        clk[emi_slow_sel]     = imx_clk_fixup_mux("emi_slow_sel", base + 0x1c, 29, 2, emi_slow_sels,   ARRAY_SIZE(emi_slow_sels),     imx_cscmr1_fixup);
         clk[vdo_axi_sel]      = imx_clk_mux("vdo_axi_sel",      base + 0x18, 11, 1, vdo_axi_sels,      ARRAY_SIZE(vdo_axi_sels));
         clk[vpu_axi_sel]      = imx_clk_mux("vpu_axi_sel",      base + 0x18, 14, 2, vpu_axi_sels,      ARRAY_SIZE(vpu_axi_sels));
         clk[cko1_sel]         = imx_clk_mux("cko1_sel",         base + 0x60, 0,  4, cko1_sels,         ARRAY_SIZE(cko1_sels));
+        clk[cko2_sel]         = imx_clk_mux("cko2_sel",         base + 0x60, 16, 5, cko2_sels,         ARRAY_SIZE(cko2_sels));
+        clk[cko]              = imx_clk_mux("cko",              base + 0x60, 8, 1,  cko_sels,          ARRAY_SIZE(cko_sels));
 
         /*                              name         reg      shift width busy: reg, shift parent_names  num_parents */
         clk[periph]  = imx_clk_busy_mux("periph",  base + 0x14, 25,  1,   base + 0x48, 5,  periph_sels,  ARRAY_SIZE(periph_sels));
@@ -406,7 +421,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
         clk[periph_clk2]      = imx_clk_divider("periph_clk2",      "periph_clk2_sel",   base + 0x14, 27, 3);
         clk[periph2_clk2]     = imx_clk_divider("periph2_clk2",     "periph2_clk2_sel",  base + 0x14, 0,  3);
         clk[ipg]              = imx_clk_divider("ipg",              "ahb",               base + 0x14, 8,  2);
-        clk[ipg_per]          = imx_clk_divider("ipg_per",          "ipg",               base + 0x1c, 0,  6);
+        clk[ipg_per]          = imx_clk_fixup_divider("ipg_per",    "ipg",               base + 0x1c, 0,  6, imx_cscmr1_fixup);
         clk[esai_pred]        = imx_clk_divider("esai_pred",        "esai_sel",          base + 0x28, 9,  3);
         clk[esai_podf]        = imx_clk_divider("esai_podf",        "esai_pred",         base + 0x28, 25, 3);
         clk[asrc_pred]        = imx_clk_divider("asrc_pred",        "asrc_sel",          base + 0x30, 12, 3);
@@ -442,10 +457,11 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
         clk[usdhc4_podf]      = imx_clk_divider("usdhc4_podf",      "usdhc4_sel",        base + 0x24, 22, 3);
         clk[enfc_pred]        = imx_clk_divider("enfc_pred",        "enfc_sel",          base + 0x2c, 18, 3);
         clk[enfc_podf]        = imx_clk_divider("enfc_podf",        "enfc_pred",         base + 0x2c, 21, 6);
-        clk[emi_podf]         = imx_clk_divider("emi_podf",         "emi_sel",           base + 0x1c, 20, 3);
-        clk[emi_slow_podf]    = imx_clk_divider("emi_slow_podf",    "emi_slow_sel",      base + 0x1c, 23, 3);
+        clk[emi_podf]         = imx_clk_fixup_divider("emi_podf",   "emi_sel",           base + 0x1c, 20, 3, imx_cscmr1_fixup);
+        clk[emi_slow_podf]    = imx_clk_fixup_divider("emi_slow_podf", "emi_slow_sel",   base + 0x1c, 23, 3, imx_cscmr1_fixup);
         clk[vpu_axi_podf]     = imx_clk_divider("vpu_axi_podf",     "vpu_axi_sel",       base + 0x24, 25, 3);
         clk[cko1_podf]        = imx_clk_divider("cko1_podf",        "cko1_sel",          base + 0x60, 4,  3);
+        clk[cko2_podf]        = imx_clk_divider("cko2_podf",        "cko2_sel",          base + 0x60, 21, 3);
 
         /*                                            name                 parent_name    reg        shift width busy: reg, shift */
         clk[axi]               = imx_clk_busy_divider("axi",               "axi_sel",     base + 0x14, 16,  3,   base + 0x48, 0);
@@ -486,6 +502,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
         clk[i2c3]         = imx_clk_gate2("i2c3",          "ipg_per",           base + 0x70, 10);
         clk[iim]          = imx_clk_gate2("iim",           "ipg",               base + 0x70, 12);
         clk[enfc]         = imx_clk_gate2("enfc",          "enfc_podf",         base + 0x70, 14);
+        clk[vdoa]         = imx_clk_gate2("vdoa",          "vdo_axi",           base + 0x70, 26);
         clk[ipu1]         = imx_clk_gate2("ipu1",          "ipu1_podf",         base + 0x74, 0);
         clk[ipu1_di0]     = imx_clk_gate2("ipu1_di0",      "ipu1_di0_sel",      base + 0x74, 2);
         clk[ipu1_di1]     = imx_clk_gate2("ipu1_di1",      "ipu1_di1_sel",      base + 0x74, 4);
@@ -521,6 +538,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
         clk[sata]         = imx_clk_gate2("sata",          "ipg",               base + 0x7c, 4);
         clk[sdma]         = imx_clk_gate2("sdma",          "ahb",               base + 0x7c, 6);
         clk[spba]         = imx_clk_gate2("spba",          "ipg",               base + 0x7c, 12);
+        clk[spdif]        = imx_clk_gate2("spdif",         "spdif_podf",        base + 0x7c, 14);
         clk[ssi1_ipg]     = imx_clk_gate2("ssi1_ipg",      "ipg",               base + 0x7c, 18);
         clk[ssi2_ipg]     = imx_clk_gate2("ssi2_ipg",      "ipg",               base + 0x7c, 20);
         clk[ssi3_ipg]     = imx_clk_gate2("ssi3_ipg",      "ipg",               base + 0x7c, 22);
@@ -535,6 +553,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
         clk[vdo_axi]      = imx_clk_gate2("vdo_axi",       "vdo_axi_sel",       base + 0x80, 12);
         clk[vpu_axi]      = imx_clk_gate2("vpu_axi",       "vpu_axi_podf",      base + 0x80, 14);
         clk[cko1]         = imx_clk_gate("cko1",           "cko1_podf",         base + 0x60, 7);
+        clk[cko2]         = imx_clk_gate("cko2",           "cko2_podf",         base + 0x60, 24);
 
         for (i = 0; i < ARRAY_SIZE(clk); i++)
                 if (IS_ERR(clk[i]))
@@ -554,7 +573,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
         clk_register_clkdev(clk[pll4_post_div], "pll4_post_div", NULL);
         clk_register_clkdev(clk[pll4_audio], "pll4_audio", NULL);
 
-        if (imx6q_revision() != IMX_CHIP_REVISION_1_0) {
+        if ((imx6q_revision() != IMX_CHIP_REVISION_1_0) || cpu_is_imx6dl()) {
                 clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]);
                 clk_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]);
         }
@@ -574,6 +593,16 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
                 clk_prepare_enable(clk[usbphy2_gate]);
         }
 
+        /*
+         * Let's initially set up CLKO with OSC24M, since this configuration
+         * is widely used by imx6q board designs to clock audio codec.
+         */
+        ret = clk_set_parent(clk[cko2_sel], clk[osc]);
+        if (!ret)
+                ret = clk_set_parent(clk[cko], clk[cko2]);
+        if (ret)
+                pr_warn("failed to set up CLKO: %d\n", ret);
+
         /* Set initial power mode */
         imx6q_set_lpm(WAIT_CLOCKED);
 
diff --git a/arch/arm/mach-imx/clk-imx6sl.c b/arch/arm/mach-imx/clk-imx6sl.c
index a307ac22dffe..a5c3c5d21aee 100644
--- a/arch/arm/mach-imx/clk-imx6sl.c
+++ b/arch/arm/mach-imx/clk-imx6sl.c
@@ -138,14 +138,14 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
         clks[IMX6SL_CLK_PERIPH_CLK2_SEL]  = imx_clk_mux("periph_clk2_sel",  base + 0x18, 12, 2, periph_clk2_sels,  ARRAY_SIZE(periph_clk2_sels));
         clks[IMX6SL_CLK_CSI_SEL]          = imx_clk_mux("csi_sel",          base + 0x3c, 9,  2, csi_lcdif_sels,    ARRAY_SIZE(csi_lcdif_sels));
         clks[IMX6SL_CLK_LCDIF_AXI_SEL]    = imx_clk_mux("lcdif_axi_sel",    base + 0x3c, 14, 2, csi_lcdif_sels,    ARRAY_SIZE(csi_lcdif_sels));
-        clks[IMX6SL_CLK_USDHC1_SEL]       = imx_clk_mux("usdhc1_sel",       base + 0x1c, 16, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels));
-        clks[IMX6SL_CLK_USDHC2_SEL]       = imx_clk_mux("usdhc2_sel",       base + 0x1c, 17, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels));
-        clks[IMX6SL_CLK_USDHC3_SEL]       = imx_clk_mux("usdhc3_sel",       base + 0x1c, 18, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels));
-        clks[IMX6SL_CLK_USDHC4_SEL]       = imx_clk_mux("usdhc4_sel",       base + 0x1c, 19, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels));
-        clks[IMX6SL_CLK_SSI1_SEL]         = imx_clk_mux("ssi1_sel",         base + 0x1c, 10, 2, ssi_sels,          ARRAY_SIZE(ssi_sels));
-        clks[IMX6SL_CLK_SSI2_SEL]         = imx_clk_mux("ssi2_sel",         base + 0x1c, 12, 2, ssi_sels,          ARRAY_SIZE(ssi_sels));
-        clks[IMX6SL_CLK_SSI3_SEL]         = imx_clk_mux("ssi3_sel",         base + 0x1c, 14, 2, ssi_sels,          ARRAY_SIZE(ssi_sels));
-        clks[IMX6SL_CLK_PERCLK_SEL]       = imx_clk_mux("perclk_sel",       base + 0x1c, 6,  1, perclk_sels,       ARRAY_SIZE(perclk_sels));
+        clks[IMX6SL_CLK_USDHC1_SEL]       = imx_clk_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels),  imx_cscmr1_fixup);
+        clks[IMX6SL_CLK_USDHC2_SEL]       = imx_clk_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels),  imx_cscmr1_fixup);
+        clks[IMX6SL_CLK_USDHC3_SEL]       = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels),  imx_cscmr1_fixup);
+        clks[IMX6SL_CLK_USDHC4_SEL]       = imx_clk_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels),  imx_cscmr1_fixup);
+        clks[IMX6SL_CLK_SSI1_SEL]         = imx_clk_fixup_mux("ssi1_sel",   base + 0x1c, 10, 2, ssi_sels,          ARRAY_SIZE(ssi_sels),    imx_cscmr1_fixup);
+        clks[IMX6SL_CLK_SSI2_SEL]         = imx_clk_fixup_mux("ssi2_sel",   base + 0x1c, 12, 2, ssi_sels,          ARRAY_SIZE(ssi_sels),    imx_cscmr1_fixup);
+        clks[IMX6SL_CLK_SSI3_SEL]         = imx_clk_fixup_mux("ssi3_sel",   base + 0x1c, 14, 2, ssi_sels,          ARRAY_SIZE(ssi_sels),    imx_cscmr1_fixup);
+        clks[IMX6SL_CLK_PERCLK_SEL]       = imx_clk_fixup_mux("perclk_sel", base + 0x1c, 6,  1, perclk_sels,       ARRAY_SIZE(perclk_sels), imx_cscmr1_fixup);
         clks[IMX6SL_CLK_PXP_AXI_SEL]      = imx_clk_mux("pxp_axi_sel",      base + 0x34, 6,  3, epdc_pxp_sels,     ARRAY_SIZE(epdc_pxp_sels));
         clks[IMX6SL_CLK_EPDC_AXI_SEL]     = imx_clk_mux("epdc_axi_sel",     base + 0x34, 15, 3, epdc_pxp_sels,     ARRAY_SIZE(epdc_pxp_sels));
         clks[IMX6SL_CLK_GPU2D_OVG_SEL]    = imx_clk_mux("gpu2d_ovg_sel",    base + 0x18, 4,  2, gpu2d_ovg_sels,    ARRAY_SIZE(gpu2d_ovg_sels));
@@ -179,14 +179,14 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
         clks[IMX6SL_CLK_SSI2_PODF]         = imx_clk_divider("ssi2_podf",         "ssi2_pred",         base + 0x2c, 0,  6);
         clks[IMX6SL_CLK_SSI3_PRED]         = imx_clk_divider("ssi3_pred",         "ssi3_sel",          base + 0x28, 22, 3);
         clks[IMX6SL_CLK_SSI3_PODF]         = imx_clk_divider("ssi3_podf",         "ssi3_pred",         base + 0x28, 16, 6);
-        clks[IMX6SL_CLK_PERCLK]            = imx_clk_divider("perclk",            "perclk_sel",        base + 0x1c, 0,  6);
+        clks[IMX6SL_CLK_PERCLK]            = imx_clk_fixup_divider("perclk",      "perclk_sel",        base + 0x1c, 0,  6, imx_cscmr1_fixup);
         clks[IMX6SL_CLK_PXP_AXI_PODF]      = imx_clk_divider("pxp_axi_podf",      "pxp_axi_sel",       base + 0x34, 3,  3);
         clks[IMX6SL_CLK_EPDC_AXI_PODF]     = imx_clk_divider("epdc_axi_podf",     "epdc_axi_sel",      base + 0x34, 12, 3);
         clks[IMX6SL_CLK_GPU2D_OVG_PODF]    = imx_clk_divider("gpu2d_ovg_podf",    "gpu2d_ovg_sel",     base + 0x18, 26, 3);
         clks[IMX6SL_CLK_GPU2D_PODF]        = imx_clk_divider("gpu2d_podf",        "gpu2d_sel",         base + 0x18, 29, 3);
         clks[IMX6SL_CLK_LCDIF_PIX_PRED]    = imx_clk_divider("lcdif_pix_pred",    "lcdif_pix_sel",     base + 0x38, 3,  3);
         clks[IMX6SL_CLK_EPDC_PIX_PRED]     = imx_clk_divider("epdc_pix_pred",     "epdc_pix_sel",      base + 0x38, 12, 3);
-        clks[IMX6SL_CLK_LCDIF_PIX_PODF]    = imx_clk_divider("lcdif_pix_podf",    "lcdif_pix_pred",    base + 0x1c, 20, 3);
+        clks[IMX6SL_CLK_LCDIF_PIX_PODF]    = imx_clk_fixup_divider("lcdif_pix_podf", "lcdif_pix_pred", base + 0x1c, 20, 3, imx_cscmr1_fixup);
         clks[IMX6SL_CLK_EPDC_PIX_PODF]     = imx_clk_divider("epdc_pix_podf",     "epdc_pix_pred",     base + 0x18, 23, 3);
         clks[IMX6SL_CLK_SPDIF0_PRED]       = imx_clk_divider("spdif0_pred",       "spdif0_sel",        base + 0x30, 25, 3);
         clks[IMX6SL_CLK_SPDIF0_PODF]       = imx_clk_divider("spdif0_podf",       "spdif0_pred",       base + 0x30, 22, 3);
diff --git a/arch/arm/mach-imx/clk-pllv3.c b/arch/arm/mach-imx/clk-pllv3.c
index a9fad5f8d340..f6640b6a7b31 100644
--- a/arch/arm/mach-imx/clk-pllv3.c
+++ b/arch/arm/mach-imx/clk-pllv3.c
@@ -48,7 +48,7 @@ struct clk_pllv3 {
 static int clk_pllv3_prepare(struct clk_hw *hw)
 {
         struct clk_pllv3 *pll = to_clk_pllv3(hw);
-        unsigned long timeout = jiffies + msecs_to_jiffies(10);
+        unsigned long timeout;
         u32 val;
 
         val = readl_relaxed(pll->base);
@@ -59,12 +59,19 @@ static int clk_pllv3_prepare(struct clk_hw *hw)
                 val &= ~BM_PLL_POWER;
         writel_relaxed(val, pll->base);
 
+        timeout = jiffies + msecs_to_jiffies(10);
         /* Wait for PLL to lock */
-        while (!(readl_relaxed(pll->base) & BM_PLL_LOCK))
+        do {
+                if (readl_relaxed(pll->base) & BM_PLL_LOCK)
+                        break;
                 if (time_after(jiffies, timeout))
-                        return -ETIMEDOUT;
+                        break;
+        } while (1);
 
-        return 0;
+        if (readl_relaxed(pll->base) & BM_PLL_LOCK)
+                return 0;
+        else
+                return -ETIMEDOUT;
 }
 
 static void clk_pllv3_unprepare(struct clk_hw *hw)
diff --git a/arch/arm/mach-imx/clk.c b/arch/arm/mach-imx/clk.c
index 55bc80a00666..edc35df7bed4 100644
--- a/arch/arm/mach-imx/clk.c
+++ b/arch/arm/mach-imx/clk.c
@@ -37,3 +37,29 @@ struct clk * __init imx_obtain_fixed_clock(
                 clk = imx_clk_fixed(name, rate);
         return clk;
 }
+
+/*
+ * This fixups the register CCM_CSCMR1 write value.
+ * The write/read/divider values of the aclk_podf field
+ * of that register have the relationship described by
+ * the following table:
+ *
+ * write value       read value        divider
+ * 3b'000            3b'110            7
+ * 3b'001            3b'111            8
+ * 3b'010            3b'100            5
+ * 3b'011            3b'101            6
+ * 3b'100            3b'010            3
+ * 3b'101            3b'011            4
+ * 3b'110            3b'000            1
+ * 3b'111            3b'001            2(default)
+ *
+ * That's why we do the xor operation below.
+ */
+#define CSCMR1_FIXUP    0x00600000
+
+void imx_cscmr1_fixup(u32 *val)
+{
+        *val ^= CSCMR1_FIXUP;
+        return;
+}
diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h
index 0e4e8bb261b9..3451f1f8ba1f 100644
--- a/arch/arm/mach-imx/clk.h
+++ b/arch/arm/mach-imx/clk.h
@@ -6,6 +6,8 @@
 
 extern spinlock_t imx_ccm_lock;
 
+extern void imx_cscmr1_fixup(u32 *val);
+
 struct clk *imx_clk_pllv1(const char *name, const char *parent,
                 void __iomem *base);
 
@@ -49,6 +51,14 @@ struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift,
                              u8 width, void __iomem *busy_reg, u8 busy_shift,
                              const char **parent_names, int num_parents);
 
+struct clk *imx_clk_fixup_divider(const char *name, const char *parent,
+                                  void __iomem *reg, u8 shift, u8 width,
+                                  void (*fixup)(u32 *val));
+
+struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg,
+                              u8 shift, u8 width, const char **parents,
+                              int num_parents, void (*fixup)(u32 *val));
+
 static inline struct clk *imx_clk_fixed(const char *name, int rate)
 {
         return clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate);
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index cb6c838b63ed..4517fd760bfc 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -137,7 +137,6 @@ extern void imx_gpc_restore_all(void);
 extern void imx_anatop_init(void);
 extern void imx_anatop_pre_suspend(void);
 extern void imx_anatop_post_resume(void);
-extern void imx_anatop_usb_chrg_detect_disable(void);
 extern u32 imx_anatop_get_digprog(void);
 extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
 extern void imx6q_set_chicken_bit(void);
@@ -147,12 +146,10 @@ extern int imx_cpu_kill(unsigned int cpu);
 
 #ifdef CONFIG_PM
 extern void imx6q_pm_init(void);
-extern void imx51_pm_init(void);
-extern void imx53_pm_init(void);
+extern void imx5_pm_init(void);
 #else
 static inline void imx6q_pm_init(void) {}
-static inline void imx51_pm_init(void) {}
-static inline void imx53_pm_init(void) {}
+static inline void imx5_pm_init(void) {}
 #endif
 
 #ifdef CONFIG_NEON
@@ -161,6 +158,12 @@ extern int mx51_neon_fixup(void);
 static inline int mx51_neon_fixup(void) { return 0; }
 #endif
 
+#ifdef CONFIG_CACHE_L2X0
+extern void imx_init_l2cache(void);
+#else
+static inline void imx_init_l2cache(void) {}
+#endif
+
 extern struct smp_operations imx_smp_ops;
 
 #endif
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index a02f275a198d..85a1b51346c8 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -31,7 +31,7 @@
 #include <linux/regmap.h>
 #include <linux/micrel_phy.h>
 #include <linux/mfd/syscon.h>
-#include <asm/hardware/cache-l2x0.h>
+#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/system_misc.h>
@@ -103,87 +103,77 @@ static int ksz9021rn_phy_fixup(struct phy_device *phydev)
 {
         if (IS_BUILTIN(CONFIG_PHYLIB)) {
                 /* min rx data delay */
-                phy_write(phydev, 0x0b, 0x8105);
-                phy_write(phydev, 0x0c, 0x0000);
+                phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
+                        0x8000 | MICREL_KSZ9021_RGMII_RX_DATA_PAD_SCEW);
+                phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0x0000);
 
                 /* max rx/tx clock delay, min rx/tx control delay */
-                phy_write(phydev, 0x0b, 0x8104);
-                phy_write(phydev, 0x0c, 0xf0f0);
-                phy_write(phydev, 0x0b, 0x104);
+                phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
+                        0x8000 | MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW);
+                phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0xf0f0);
+                phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
+                        MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW);
         }
 
         return 0;
 }
 
-static void __init imx6q_sabrelite_cko1_setup(void)
+static void mmd_write_reg(struct phy_device *dev, int device, int reg, int val)
 {
-        struct clk *cko1_sel, *ahb, *cko1;
-        unsigned long rate;
-
-        cko1_sel = clk_get_sys(NULL, "cko1_sel");
-        ahb = clk_get_sys(NULL, "ahb");
-        cko1 = clk_get_sys(NULL, "cko1");
-        if (IS_ERR(cko1_sel) || IS_ERR(ahb) || IS_ERR(cko1)) {
-                pr_err("cko1 setup failed!\n");
-                goto put_clk;
-        }
-        clk_set_parent(cko1_sel, ahb);
-        rate = clk_round_rate(cko1, 16000000);
-        clk_set_rate(cko1, rate);
-put_clk:
-        if (!IS_ERR(cko1_sel))
-                clk_put(cko1_sel);
-        if (!IS_ERR(ahb))
-                clk_put(ahb);
-        if (!IS_ERR(cko1))
-                clk_put(cko1);
+        phy_write(dev, 0x0d, device);
+        phy_write(dev, 0x0e, reg);
+        phy_write(dev, 0x0d, (1 << 14) | device);
+        phy_write(dev, 0x0e, val);
 }
 
-static void __init imx6q_sabrelite_init(void)
+static int ksz9031rn_phy_fixup(struct phy_device *dev)
 {
-        if (IS_BUILTIN(CONFIG_PHYLIB))
-                phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
-                                ksz9021rn_phy_fixup);
-        imx6q_sabrelite_cko1_setup();
+        /*
+         * min rx data delay, max rx/tx clock delay,
+         * min rx/tx control delay
+         */
+        mmd_write_reg(dev, 2, 4, 0);
+        mmd_write_reg(dev, 2, 5, 0);
+        mmd_write_reg(dev, 2, 8, 0x003ff);
+
+        return 0;
 }
 
-static void __init imx6q_sabresd_cko1_setup(void)
+static int ar8031_phy_fixup(struct phy_device *dev)
 {
-        struct clk *cko1_sel, *pll4, *pll4_post, *cko1;
-        unsigned long rate;
-
-        cko1_sel = clk_get_sys(NULL, "cko1_sel");
-        pll4 = clk_get_sys(NULL, "pll4_audio");
-        pll4_post = clk_get_sys(NULL, "pll4_post_div");
-        cko1 = clk_get_sys(NULL, "cko1");
-        if (IS_ERR(cko1_sel) || IS_ERR(pll4)
-                        || IS_ERR(pll4_post) || IS_ERR(cko1)) {
-                pr_err("cko1 setup failed!\n");
-                goto put_clk;
-        }
-        /*
-         * Setting pll4 at 768MHz (24MHz * 32)
-         * So its child clock can get 24MHz easily
-         */
-        clk_set_rate(pll4, 768000000);
-
-        clk_set_parent(cko1_sel, pll4_post);
-        rate = clk_round_rate(cko1, 24000000);
-        clk_set_rate(cko1, rate);
-put_clk:
-        if (!IS_ERR(cko1_sel))
-                clk_put(cko1_sel);
-        if (!IS_ERR(pll4_post))
-                clk_put(pll4_post);
-        if (!IS_ERR(pll4))
-                clk_put(pll4);
-        if (!IS_ERR(cko1))
-                clk_put(cko1);
+        u16 val;
+
+        /* To enable AR8031 output a 125MHz clk from CLK_25M */
+        phy_write(dev, 0xd, 0x7);
+        phy_write(dev, 0xe, 0x8016);
+        phy_write(dev, 0xd, 0x4007);
+
+        val = phy_read(dev, 0xe);
+        val &= 0xffe3;
+        val |= 0x18;
+        phy_write(dev, 0xe, val);
+
+        /* introduce tx clock delay */
+        phy_write(dev, 0x1d, 0x5);
+        val = phy_read(dev, 0x1e);
+        val |= 0x0100;
+        phy_write(dev, 0x1e, val);
+
+        return 0;
 }
 
-static void __init imx6q_sabresd_init(void)
+#define PHY_ID_AR8031   0x004dd074
+
+static void __init imx6q_enet_phy_init(void)
 {
-        imx6q_sabresd_cko1_setup();
+        if (IS_BUILTIN(CONFIG_PHYLIB)) {
+                phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
+                                ksz9021rn_phy_fixup);
+                phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK,
+                                ksz9031rn_phy_fixup);
+                phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff,
+                                ar8031_phy_fixup);
+        }
 }
 
 static void __init imx6q_1588_init(void)
@@ -192,29 +182,22 @@ static void __init imx6q_1588_init(void)
 
         gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
         if (!IS_ERR(gpr))
-                regmap_update_bits(gpr, 0x4, 1 << 21, 1 << 21);
+                regmap_update_bits(gpr, IOMUXC_GPR1,
+                                IMX6Q_GPR1_ENET_CLK_SEL_MASK,
+                                IMX6Q_GPR1_ENET_CLK_SEL_ANATOP);
         else
                 pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n");
 
 }
-static void __init imx6q_usb_init(void)
-{
-        imx_anatop_usb_chrg_detect_disable();
-}
 
 static void __init imx6q_init_machine(void)
 {
-        if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
-                imx6q_sabrelite_init();
-        else if (of_machine_is_compatible("fsl,imx6q-sabresd") ||
-                        of_machine_is_compatible("fsl,imx6dl-sabresd"))
-                imx6q_sabresd_init();
+        imx6q_enet_phy_init();
 
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 
         imx_anatop_init();
         imx6q_pm_init();
-        imx6q_usb_init();
         imx6q_1588_init();
 }
 
@@ -296,44 +279,10 @@ static void __init imx6q_map_io(void)
         imx_scu_map_io();
 }
 
-#ifdef CONFIG_CACHE_L2X0
-static void __init imx6q_init_l2cache(void)
-{
-        void __iomem *l2x0_base;
-        struct device_node *np;
-        unsigned int val;
-
-        np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache");
-        if (!np)
-                goto out;
-
-        l2x0_base = of_iomap(np, 0);
-        if (!l2x0_base) {
-                of_node_put(np);
-                goto out;
-        }
-
-        /* Configure the L2 PREFETCH and POWER registers */
-        val = readl_relaxed(l2x0_base + L2X0_PREFETCH_CTRL);
-        val |= 0x70800000;
-        writel_relaxed(val, l2x0_base + L2X0_PREFETCH_CTRL);
-        val = L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN;
-        writel_relaxed(val, l2x0_base + L2X0_POWER_CTRL);
-
-        iounmap(l2x0_base);
-        of_node_put(np);
-
-out:
-        l2x0_of_init(0, ~0UL);
-}
-#else
-static inline void imx6q_init_l2cache(void) {}
-#endif
-
 static void __init imx6q_init_irq(void)
 {
         imx6q_init_revision();
-        imx6q_init_l2cache();
+        imx_init_l2cache();
         imx_src_init();
         imx_gpc_init();
         irqchip_init();
diff --git a/arch/arm/mach-imx/mach-imx6sl.c b/arch/arm/mach-imx/mach-imx6sl.c
index 132db2609507..0d75dc54f715 100644
--- a/arch/arm/mach-imx/mach-imx6sl.c
+++ b/arch/arm/mach-imx/mach-imx6sl.c
@@ -11,7 +11,6 @@
 #include <linux/irqchip.h>
 #include <linux/of.h>
 #include <linux/of_platform.h>
-#include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
@@ -26,7 +25,7 @@ static void __init imx6sl_init_machine(void)
 
 static void __init imx6sl_init_irq(void)
 {
-        l2x0_of_init(0, ~0UL);
+        imx_init_l2cache();
         imx_src_init();
         imx_gpc_init();
         irqchip_init();
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c
index cf193d87274a..a8229b7f10bf 100644
--- a/arch/arm/mach-imx/mm-imx5.c
+++ b/arch/arm/mach-imx/mm-imx5.c
@@ -153,10 +153,10 @@ void __init imx51_soc_init(void)
 void __init imx51_init_late(void)
 {
         mx51_neon_fixup();
-        imx51_pm_init();
+        imx5_pm_init();
 }
 
 void __init imx53_init_late(void)
 {
-        imx53_pm_init();
+        imx5_pm_init();
 }
diff --git a/arch/arm/mach-imx/pm-imx5.c b/arch/arm/mach-imx/pm-imx5.c
index 82e79c658eb2..58aeaf5baaf6 100644
--- a/arch/arm/mach-imx/pm-imx5.c
+++ b/arch/arm/mach-imx/pm-imx5.c
@@ -169,14 +169,9 @@ static int __init imx5_pm_common_init(void)
         return imx5_cpuidle_init();
 }
 
-void __init imx51_pm_init(void)
+void __init imx5_pm_init(void)
 {
         int ret = imx5_pm_common_init();
         if (!ret)
                 suspend_set_ops(&mx5_suspend_ops);
 }
-
-void __init imx53_pm_init(void)
-{
-        imx5_pm_common_init();
-}
diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c
index 6fe81bb4d3c9..64ff37ea72b1 100644
--- a/arch/arm/mach-imx/system.c
+++ b/arch/arm/mach-imx/system.c
@@ -27,6 +27,7 @@
 #include <asm/system_misc.h>
 #include <asm/proc-fns.h>
 #include <asm/mach-types.h>
+#include <asm/hardware/cache-l2x0.h>
 
 #include "common.h"
 #include "hardware.h"
@@ -95,3 +96,35 @@ void __init mxc_arch_reset_init_dt(void)
 
         clk_prepare(wdog_clk);
 }
+
+#ifdef CONFIG_CACHE_L2X0
+void __init imx_init_l2cache(void)
+{
+        void __iomem *l2x0_base;
+        struct device_node *np;
+        unsigned int val;
+
+        np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache");
+        if (!np)
+                goto out;
+
+        l2x0_base = of_iomap(np, 0);
+        if (!l2x0_base) {
+                of_node_put(np);
+                goto out;
+        }
+
+        /* Configure the L2 PREFETCH and POWER registers */
+        val = readl_relaxed(l2x0_base + L2X0_PREFETCH_CTRL);
+        val |= 0x70800000;
+        writel_relaxed(val, l2x0_base + L2X0_PREFETCH_CTRL);
+        val = L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN;
+        writel_relaxed(val, l2x0_base + L2X0_POWER_CTRL);
+
+        iounmap(l2x0_base);
+        of_node_put(np);
+
+out:
+        l2x0_of_init(0, ~0UL);
+}
+#endif
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index 6e122ed3282f..682b7ac8deb8 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -87,6 +87,7 @@ static void __init kirkwood_dt_init(void)
          */
         writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG);
 
+        BUG_ON(mvebu_mbus_dt_init());
         kirkwood_setup_wins();
 
         kirkwood_l2_init();
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 1663de090984..176761134a66 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -37,6 +37,12 @@
 #include <linux/platform_data/dma-mv_xor.h>
 #include "common.h"
 
+/* These can go away once Kirkwood uses the mvebu-mbus DT binding */
+#define KIRKWOOD_MBUS_NAND_TARGET 0x01
+#define KIRKWOOD_MBUS_NAND_ATTR   0x2f
+#define KIRKWOOD_MBUS_SRAM_TARGET 0x03
+#define KIRKWOOD_MBUS_SRAM_ATTR   0x01
+
 /*****************************************************************************
  * I/O Address Mapping
  ****************************************************************************/
@@ -528,10 +534,6 @@ void __init kirkwood_cpuidle_init(void)
 void __init kirkwood_init_early(void)
 {
         orion_time_set_base(TIMER_VIRT_BASE);
-
-        mvebu_mbus_init("marvell,kirkwood-mbus",
-                        BRIDGE_WINS_BASE, BRIDGE_WINS_SZ,
-                        DDR_WINDOW_CPU_BASE, DDR_WINDOW_CPU_SZ);
 }
 
 int kirkwood_tclk;
@@ -666,10 +668,14 @@ char * __init kirkwood_id(void)
 
 void __init kirkwood_setup_wins(void)
 {
-        mvebu_mbus_add_window("nand", KIRKWOOD_NAND_MEM_PHYS_BASE,
-                              KIRKWOOD_NAND_MEM_SIZE);
-        mvebu_mbus_add_window("sram", KIRKWOOD_SRAM_PHYS_BASE,
-                              KIRKWOOD_SRAM_SIZE);
+        mvebu_mbus_add_window_by_id(KIRKWOOD_MBUS_NAND_TARGET,
+                                    KIRKWOOD_MBUS_NAND_ATTR,
+                                    KIRKWOOD_NAND_MEM_PHYS_BASE,
+                                    KIRKWOOD_NAND_MEM_SIZE);
+        mvebu_mbus_add_window_by_id(KIRKWOOD_MBUS_SRAM_TARGET,
+                                    KIRKWOOD_MBUS_SRAM_ATTR,
+                                    KIRKWOOD_SRAM_PHYS_BASE,
+                                    KIRKWOOD_SRAM_SIZE);
 }
 
 void __init kirkwood_l2_init(void)
@@ -697,6 +703,10 @@ void __init kirkwood_init(void)
          */
         writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG);
 
+        BUG_ON(mvebu_mbus_init("marvell,kirkwood-mbus",
+                        BRIDGE_WINS_BASE, BRIDGE_WINS_SZ,
+                        DDR_WINDOW_CPU_BASE, DDR_WINDOW_CPU_SZ));
+
         kirkwood_setup_wins();
 
         kirkwood_l2_init();
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
index ddcb09f5bdd3..12d86f39f380 100644
--- a/arch/arm/mach-kirkwood/pcie.c
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -20,6 +20,16 @@
 #include <mach/bridge-regs.h>
 #include "common.h"
 
+/* These can go away once Kirkwood uses the mvebu-mbus DT binding */
+#define KIRKWOOD_MBUS_PCIE0_MEM_TARGET    0x4
+#define KIRKWOOD_MBUS_PCIE0_MEM_ATTR      0xe8
+#define KIRKWOOD_MBUS_PCIE0_IO_TARGET     0x4
+#define KIRKWOOD_MBUS_PCIE0_IO_ATTR       0xe0
+#define KIRKWOOD_MBUS_PCIE1_MEM_TARGET    0x4
+#define KIRKWOOD_MBUS_PCIE1_MEM_ATTR      0xd8
+#define KIRKWOOD_MBUS_PCIE1_IO_TARGET     0x4
+#define KIRKWOOD_MBUS_PCIE1_IO_ATTR       0xd0
+
 static void kirkwood_enable_pcie_clk(const char *port)
 {
         struct clk *clk;
@@ -254,26 +264,24 @@ static void __init add_pcie_port(int index, void __iomem *base)
 
 void __init kirkwood_pcie_init(unsigned int portmask)
 {
-        mvebu_mbus_add_window_remap_flags("pcie0.0",
+        mvebu_mbus_add_window_remap_by_id(KIRKWOOD_MBUS_PCIE0_IO_TARGET,
+                                          KIRKWOOD_MBUS_PCIE0_IO_ATTR,
                                           KIRKWOOD_PCIE_IO_PHYS_BASE,
                                           KIRKWOOD_PCIE_IO_SIZE,
-                                          KIRKWOOD_PCIE_IO_BUS_BASE,
-                                          MVEBU_MBUS_PCI_IO);
-        mvebu_mbus_add_window_remap_flags("pcie0.0",
-                                          KIRKWOOD_PCIE_MEM_PHYS_BASE,
-                                          KIRKWOOD_PCIE_MEM_SIZE,
-                                          MVEBU_MBUS_NO_REMAP,
-                                          MVEBU_MBUS_PCI_MEM);
-        mvebu_mbus_add_window_remap_flags("pcie1.0",
+                                          KIRKWOOD_PCIE_IO_BUS_BASE);
+        mvebu_mbus_add_window_by_id(KIRKWOOD_MBUS_PCIE0_MEM_TARGET,
+                                    KIRKWOOD_MBUS_PCIE0_MEM_ATTR,
+                                    KIRKWOOD_PCIE_MEM_PHYS_BASE,
+                                    KIRKWOOD_PCIE_MEM_SIZE);
+        mvebu_mbus_add_window_remap_by_id(KIRKWOOD_MBUS_PCIE1_IO_TARGET,
+                                          KIRKWOOD_MBUS_PCIE1_IO_ATTR,
                                           KIRKWOOD_PCIE1_IO_PHYS_BASE,
                                           KIRKWOOD_PCIE1_IO_SIZE,
-                                          KIRKWOOD_PCIE1_IO_BUS_BASE,
-                                          MVEBU_MBUS_PCI_IO);
-        mvebu_mbus_add_window_remap_flags("pcie1.0",
-                                          KIRKWOOD_PCIE1_MEM_PHYS_BASE,
-                                          KIRKWOOD_PCIE1_MEM_SIZE,
-                                          MVEBU_MBUS_NO_REMAP,
-                                          MVEBU_MBUS_PCI_MEM);
+                                          KIRKWOOD_PCIE1_IO_BUS_BASE);
+        mvebu_mbus_add_window_by_id(KIRKWOOD_MBUS_PCIE1_MEM_TARGET,
+                                    KIRKWOOD_MBUS_PCIE1_MEM_ATTR,
+                                    KIRKWOOD_PCIE1_MEM_PHYS_BASE,
+                                    KIRKWOOD_PCIE1_MEM_SIZE);
 
         vga_base = KIRKWOOD_PCIE_MEM_PHYS_BASE;
 
diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c
index dc26a654c496..445e553f4a28 100644
--- a/arch/arm/mach-mv78xx0/pcie.c
+++ b/arch/arm/mach-mv78xx0/pcie.c
@@ -18,6 +18,11 @@
 #include <mach/mv78xx0.h>
 #include "common.h"
 
+#define MV78XX0_MBUS_PCIE_MEM_TARGET(port, lane) ((port) ? 8 : 4)
+#define MV78XX0_MBUS_PCIE_MEM_ATTR(port, lane)   (0xf8 & ~(0x10 << (lane)))
+#define MV78XX0_MBUS_PCIE_IO_TARGET(port, lane)  ((port) ? 8 : 4)
+#define MV78XX0_MBUS_PCIE_IO_ATTR(port, lane)    (0xf0 & ~(0x10 << (lane)))
+
 struct pcie_port {
         u8                      maj;
         u8                      min;
@@ -71,7 +76,6 @@ static void __init mv78xx0_pcie_preinit(void)
         start = MV78XX0_PCIE_MEM_PHYS_BASE;
         for (i = 0; i < num_pcie_ports; i++) {
                 struct pcie_port *pp = pcie_port + i;
-                char winname[MVEBU_MBUS_MAX_WINNAME_SZ];
 
                 snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
                         "PCIe %d.%d MEM", pp->maj, pp->min);
@@ -85,17 +89,12 @@ static void __init mv78xx0_pcie_preinit(void)
                 if (request_resource(&iomem_resource, &pp->res))
                         panic("can't allocate PCIe MEM sub-space");
 
-                snprintf(winname, sizeof(winname), "pcie%d.%d",
-                         pp->maj, pp->min);
-
-                mvebu_mbus_add_window_remap_flags(winname,
-                                                  pp->res.start,
-                                                  resource_size(&pp->res),
-                                                  MVEBU_MBUS_NO_REMAP,
-                                                  MVEBU_MBUS_PCI_MEM);
-                mvebu_mbus_add_window_remap_flags(winname,
-                                                  i * SZ_64K, SZ_64K,
-                                                  0, MVEBU_MBUS_PCI_IO);
+                mvebu_mbus_add_window_by_id(MV78XX0_MBUS_PCIE_MEM_TARGET(pp->maj, pp->min),
+                                            MV78XX0_MBUS_PCIE_MEM_ATTR(pp->maj, pp->min),
+                                            pp->res.start, resource_size(&pp->res));
+                mvebu_mbus_add_window_remap_by_id(MV78XX0_MBUS_PCIE_IO_TARGET(pp->maj, pp->min),
+                                                  MV78XX0_MBUS_PCIE_IO_ATTR(pp->maj, pp->min),
+                                                  i * SZ_64K, SZ_64K, 0);
         }
 }
 
diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
index 97cbb8021919..829b57306328 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.c
+++ b/arch/arm/mach-mvebu/armada-370-xp.c
@@ -34,44 +34,12 @@ static void __init armada_370_xp_map_io(void)
         debug_ll_io_init();
 }
 
-/*
- * This initialization will be replaced by a DT-based
- * initialization once the mvebu-mbus driver gains DT support.
- */
-
-#define ARMADA_370_XP_MBUS_WINS_OFFS   0x20000
-#define ARMADA_370_XP_MBUS_WINS_SIZE   0x100
-#define ARMADA_370_XP_SDRAM_WINS_OFFS  0x20180
-#define ARMADA_370_XP_SDRAM_WINS_SIZE  0x20
-
-static void __init armada_370_xp_mbus_init(void)
-{
-        char *mbus_soc_name;
-        struct device_node *dn;
-        const __be32 mbus_wins_offs = cpu_to_be32(ARMADA_370_XP_MBUS_WINS_OFFS);
-        const __be32 sdram_wins_offs = cpu_to_be32(ARMADA_370_XP_SDRAM_WINS_OFFS);
-
-        if (of_machine_is_compatible("marvell,armada370"))
-                mbus_soc_name = "marvell,armada370-mbus";
-        else
-                mbus_soc_name = "marvell,armadaxp-mbus";
-
-        dn = of_find_node_by_name(NULL, "internal-regs");
-        BUG_ON(!dn);
-
-        mvebu_mbus_init(mbus_soc_name,
-                        of_translate_address(dn, &mbus_wins_offs),
-                        ARMADA_370_XP_MBUS_WINS_SIZE,
-                        of_translate_address(dn, &sdram_wins_offs),
-                        ARMADA_370_XP_SDRAM_WINS_SIZE);
-}
-
 static void __init armada_370_xp_timer_and_clk_init(void)
 {
         of_clk_init(NULL);
         armada_370_xp_timer_init();
         coherency_init();
-        armada_370_xp_mbus_init();
+        BUG_ON(mvebu_mbus_dt_init());
 #ifdef CONFIG_CACHE_L2X0
         l2x0_of_init(0, ~0UL);
 #endif
diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c
index f9c09b75d4d7..ff69c2df298b 100644
--- a/arch/arm/mach-mvebu/platsmp.c
+++ b/arch/arm/mach-mvebu/platsmp.c
@@ -21,6 +21,7 @@
 #include <linux/smp.h>
 #include <linux/clk.h>
 #include <linux/of.h>
+#include <linux/of_address.h>
 #include <linux/mbus.h>
 #include <asm/cacheflush.h>
 #include <asm/smp_plat.h>
@@ -29,6 +30,9 @@
 #include "pmsu.h"
 #include "coherency.h"
 
+#define AXP_BOOTROM_BASE 0xfff00000
+#define AXP_BOOTROM_SIZE 0x100000
+
 static struct clk *__init get_cpu_clk(int cpu)
 {
         struct clk *cpu_clk;
@@ -92,10 +96,29 @@ static void __init armada_xp_smp_init_cpus(void)
 
 void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus)
 {
+        struct device_node *node;
+        struct resource res;
+        int err;
+
         set_secondary_cpus_clock();
         flush_cache_all();
         set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0);
-        mvebu_mbus_add_window("bootrom", 0xfff00000, SZ_1M);
+
+        /*
+         * In order to boot the secondary CPUs we need to ensure
+         * the bootROM is mapped at the correct address.
+         */
+        node = of_find_compatible_node(NULL, NULL, "marvell,bootrom");
+        if (!node)
+                panic("Cannot find 'marvell,bootrom' compatible node");
+
+        err = of_address_to_resource(node, 0, &res);
+        if (err < 0)
+                panic("Cannot get 'bootrom' node address");
+
+        if (res.start != AXP_BOOTROM_BASE ||
+            resource_size(&res) != AXP_BOOTROM_SIZE)
+                panic("The address for the BootROM is incorrect");
 }
 
 struct smp_operations armada_xp_smp_ops __initdata = {
diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
index 4ce27b536dc9..98f6e2adb53e 100644
--- a/arch/arm/mach-mxs/mach-mxs.c
+++ b/arch/arm/mach-mxs/mach-mxs.c
@@ -14,6 +14,7 @@
 #include <linux/clk/mxs.h>
 #include <linux/clkdev.h>
 #include <linux/clocksource.h>
+#include <linux/clk-provider.h>
 #include <linux/delay.h>
 #include <linux/err.h>
 #include <linux/gpio.h>
@@ -61,6 +62,8 @@
 static u32 chipid;
 static u32 socid;
 
+static void __iomem *reset_addr;
+
 static inline void __mxs_setl(u32 mask, void __iomem *reg)
 {
         __raw_writel(mask, reg + MXS_SET_ADDR);
@@ -393,12 +396,33 @@ static const char __init *mxs_get_revision(void)
         u32 rev = mxs_get_cpu_rev();
 
         if (rev != MXS_CHIP_REV_UNKNOWN)
-                return kasprintf(GFP_KERNEL, "TO%d.%d", (rev >> 4) & 0xf,
+                return kasprintf(GFP_KERNEL, "%d.%d", (rev >> 4) & 0xf,
                                 rev & 0xf);
         else
                 return kasprintf(GFP_KERNEL, "%s", "Unknown");
 }
 
+#define MX23_CLKCTRL_RESET_OFFSET       0x120
+#define MX28_CLKCTRL_RESET_OFFSET       0x1e0
+
+static int __init mxs_restart_init(void)
+{
+        struct device_node *np;
+
+        np = of_find_compatible_node(NULL, NULL, "fsl,clkctrl");
+        reset_addr = of_iomap(np, 0);
+        if (!reset_addr)
+                return -ENODEV;
+
+        if (of_device_is_compatible(np, "fsl,imx23-clkctrl"))
+                reset_addr += MX23_CLKCTRL_RESET_OFFSET;
+        else
+                reset_addr += MX28_CLKCTRL_RESET_OFFSET;
+        of_node_put(np);
+
+        return 0;
+}
+
 static void __init mxs_machine_init(void)
 {
         struct device_node *root;
@@ -433,21 +457,18 @@ static void __init mxs_machine_init(void)
                 imx28_evk_init();
         else if (of_machine_is_compatible("bluegiga,apx4devkit"))
                 apx4devkit_init();
-        else if (of_machine_is_compatible("crystalfontz,cfa10037") ||
-                 of_machine_is_compatible("crystalfontz,cfa10049") ||
-                 of_machine_is_compatible("crystalfontz,cfa10055") ||
-                 of_machine_is_compatible("crystalfontz,cfa10057"))
+        else if (of_machine_is_compatible("crystalfontz,cfa10036"))
                 crystalfontz_init();
 
         of_platform_populate(NULL, of_default_bus_match_table,
                              NULL, parent);
 
+        mxs_restart_init();
+
         if (of_machine_is_compatible("karo,tx28"))
                 tx28_post_init();
 }
 
-#define MX23_CLKCTRL_RESET_OFFSET       0x120
-#define MX28_CLKCTRL_RESET_OFFSET       0x1e0
 #define MXS_CLKCTRL_RESET_CHIP          (1 << 1)
 
 /*
@@ -455,28 +476,16 @@ static void __init mxs_machine_init(void)
  */
 static void mxs_restart(enum reboot_mode mode, const char *cmd)
 {
-        struct device_node *np;
-        void __iomem *reset_addr;
+        if (reset_addr) {
+                /* reset the chip */
+                __mxs_setl(MXS_CLKCTRL_RESET_CHIP, reset_addr);
 
-        np = of_find_compatible_node(NULL, NULL, "fsl,clkctrl");
-        reset_addr = of_iomap(np, 0);
-        if (!reset_addr)
-                goto soft;
+                pr_err("Failed to assert the chip reset\n");
 
-        if (of_device_is_compatible(np, "fsl,imx23-clkctrl"))
-                reset_addr += MX23_CLKCTRL_RESET_OFFSET;
-        else
-                reset_addr += MX28_CLKCTRL_RESET_OFFSET;
-
-        /* reset the chip */
-        __mxs_setl(MXS_CLKCTRL_RESET_CHIP, reset_addr);
-
-        pr_err("Failed to assert the chip reset\n");
-
-        /* Delay to allow the serial port to show the message */
-        mdelay(50);
+                /* Delay to allow the serial port to show the message */
+                mdelay(50);
+        }
 
-soft:
         /* We'll take a jump through zero as a poor second */
         soft_restart(0);
 }
@@ -487,6 +496,7 @@ static void __init mxs_timer_init(void)
                 mx23_clocks_init();
         else
                 mx28_clocks_init();
+        of_clk_init(NULL);
         clocksource_of_init();
 }
 
diff --git a/arch/arm/mach-mxs/pm.c b/arch/arm/mach-mxs/pm.c
index b2494d2db2c4..0170e99fd70f 100644
--- a/arch/arm/mach-mxs/pm.c
+++ b/arch/arm/mach-mxs/pm.c
@@ -15,6 +15,7 @@
 #include <linux/kernel.h>
 #include <linux/suspend.h>
 #include <linux/io.h>
+#include "pm.h"
 
 static int mxs_suspend_enter(suspend_state_t state)
 {
diff --git a/arch/arm/mach-omap1/include/mach/soc.h b/arch/arm/mach-omap1/include/mach/soc.h
index 6cf9c1cc2bef..612bd1cc257c 100644
--- a/arch/arm/mach-omap1/include/mach/soc.h
+++ b/arch/arm/mach-omap1/include/mach/soc.h
@@ -195,6 +195,7 @@ IS_OMAP_TYPE(1710, 0x1710)
 #define cpu_is_omap34xx()               0
 #define cpu_is_omap44xx()               0
 #define soc_is_omap54xx()               0
+#define soc_is_dra7xx()                 0
 #define soc_is_am33xx()                 0
 #define cpu_class_is_omap1()            1
 #define cpu_class_is_omap2()            0
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 56021c67c89c..b5fb5f7992df 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -117,7 +117,7 @@ config ARCH_OMAP2PLUS_TYPICAL
         select I2C
         select I2C_OMAP
         select MENELAUS if ARCH_OMAP2
-        select NEON if ARCH_OMAP3 || ARCH_OMAP4 || SOC_OMAP5
+        select NEON if CPU_V7
         select PM_RUNTIME
         select REGULATOR
         select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4
@@ -131,9 +131,17 @@ config SOC_HAS_OMAP2_SDRC
 
 config SOC_HAS_REALTIME_COUNTER
         bool "Real time free running counter"
-        depends on SOC_OMAP5
+        depends on SOC_OMAP5 || SOC_DRA7XX
         default y
 
+config SOC_DRA7XX
+        bool "TI DRA7XX"
+        select ARM_ARCH_TIMER
+        select CPU_V7
+        select ARM_GIC
+        select HAVE_SMP
+        select COMMON_CLK
+
 comment "OMAP Core Type"
         depends on ARCH_OMAP2
 
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index d4f671547c37..cc36bfe104fe 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -23,6 +23,7 @@ obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common)
 obj-$(CONFIG_SOC_AM33XX) += irq.o $(hwmod-common)
 obj-$(CONFIG_SOC_OMAP5)  += prm44xx.o $(hwmod-common) $(secure-common)
 obj-$(CONFIG_SOC_AM43XX) += $(hwmod-common) $(secure-common)
+obj-$(CONFIG_SOC_DRA7XX) += prm44xx.o $(hwmod-common) $(secure-common)
 
 ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),)
 obj-y += mcbsp.o
@@ -39,6 +40,7 @@ omap-4-5-common				=  omap4-common.o omap-wakeupgen.o
 obj-$(CONFIG_ARCH_OMAP4)                += $(omap-4-5-common) $(smp-y) sleep44xx.o
 obj-$(CONFIG_SOC_OMAP5)                 += $(omap-4-5-common) $(smp-y) sleep44xx.o
 obj-$(CONFIG_SOC_AM43XX)                += $(omap-4-5-common)
+obj-$(CONFIG_SOC_DRA7XX)                += $(omap-4-5-common) $(smp-y)
 
 plus_sec := $(call as-instr,.arch_extension sec,+sec)
 AFLAGS_omap-headsmp.o                   :=-Wa,-march=armv7-a$(plus_sec)
@@ -87,6 +89,7 @@ obj-$(CONFIG_ARCH_OMAP2)		+= sleep24xx.o
 obj-$(CONFIG_ARCH_OMAP3)                += pm34xx.o sleep34xx.o
 obj-$(CONFIG_ARCH_OMAP4)                += pm44xx.o omap-mpuss-lowpower.o
 obj-$(CONFIG_SOC_OMAP5)                 += omap-mpuss-lowpower.o
+obj-$(CONFIG_SOC_DRA7XX)                += omap-mpuss-lowpower.o
 obj-$(CONFIG_PM_DEBUG)                  += pm-debug.o
 
 obj-$(CONFIG_POWER_AVS_OMAP)            += sr_device.o
@@ -114,6 +117,7 @@ omap-prcm-4-5-common			=  cminst44xx.o cm44xx.o prm44xx.o \
                                            vc44xx_data.o vp44xx_data.o
 obj-$(CONFIG_ARCH_OMAP4)                += $(omap-prcm-4-5-common)
 obj-$(CONFIG_SOC_OMAP5)                 += $(omap-prcm-4-5-common)
+obj-$(CONFIG_SOC_DRA7XX)                += $(omap-prcm-4-5-common)
 
 # OMAP voltage domains
 voltagedomain-common                    := voltage.o vc.o vp.o
@@ -143,6 +147,7 @@ obj-$(CONFIG_SOC_AM33XX)		+= powerdomains33xx_data.o
 obj-$(CONFIG_SOC_AM43XX)                += $(powerdomain-common)
 obj-$(CONFIG_SOC_OMAP5)                 += $(powerdomain-common)
 obj-$(CONFIG_SOC_OMAP5)                 += powerdomains54xx_data.o
+obj-$(CONFIG_SOC_DRA7XX)                += $(powerdomain-common)
 
 # PRCM clockdomain control
 clockdomain-common                      += clockdomain.o
@@ -160,6 +165,7 @@ obj-$(CONFIG_SOC_AM33XX)		+= clockdomains33xx_data.o
 obj-$(CONFIG_SOC_AM43XX)                += $(clockdomain-common)
 obj-$(CONFIG_SOC_OMAP5)                 += $(clockdomain-common)
 obj-$(CONFIG_SOC_OMAP5)                 += clockdomains54xx_data.o
+obj-$(CONFIG_SOC_DRA7XX)                += $(clockdomain-common)
 
 # Clock framework
 obj-$(CONFIG_ARCH_OMAP2)                += $(clock-common) clock2xxx.o
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index be5d005ebad2..b89e55ba2c13 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -222,3 +222,21 @@ DT_MACHINE_START(AM43_DT, "Generic AM43 (Flattened Device Tree)")
         .dt_compat      = am43_boards_compat,
 MACHINE_END
 #endif
+
+#ifdef CONFIG_SOC_DRA7XX
+static const char *dra7xx_boards_compat[] __initdata = {
+        "ti,dra7",
+        NULL,
+};
+
+DT_MACHINE_START(DRA7XX_DT, "Generic DRA7XX (Flattened Device Tree)")
+        .reserve        = omap_reserve,
+        .smp            = smp_ops(omap4_smp_ops),
+        .map_io         = omap5_map_io,
+        .init_early     = dra7xx_init_early,
+        .init_irq       = omap_gic_of_init,
+        .init_machine   = omap_generic_init,
+        .init_time      = omap5_realtime_timer_init,
+        .dt_compat      = dra7xx_boards_compat,
+MACHINE_END
+#endif
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index dfcc182ecff9..4a5684b96492 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -110,6 +110,7 @@ void omap3630_init_late(void);
 void am35xx_init_late(void);
 void ti81xx_init_late(void);
 int omap2_common_pm_late_init(void);
+void dra7xx_init_early(void);
 
 #ifdef CONFIG_SOC_BUS
 void omap_soc_device_init(void);
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 2dc62a25f2c3..0289adcb6efb 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -61,7 +61,7 @@ int omap_type(void)
                 val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
         } else if (cpu_is_omap44xx()) {
                 val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
-        } else if (soc_is_omap54xx()) {
+        } else if (soc_is_omap54xx() || soc_is_dra7xx()) {
                 val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS);
                 val &= OMAP5_DEVICETYPE_MASK;
                 val >>= 6;
@@ -116,7 +116,7 @@ static u16 tap_prod_id;
 
 void omap_get_die_id(struct omap_die_id *odi)
 {
-        if (cpu_is_omap44xx() || soc_is_omap54xx()) {
+        if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) {
                 odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0);
                 odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1);
                 odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2);
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 4a3f06f02859..3656b8009a1c 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -251,7 +251,7 @@ static struct map_desc omap44xx_io_desc[] __initdata = {
 };
 #endif
 
-#ifdef  CONFIG_SOC_OMAP5
+#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
 static struct map_desc omap54xx_io_desc[] __initdata = {
         {
                 .virtual        = L3_54XX_VIRT,
@@ -333,7 +333,7 @@ void __init omap4_map_io(void)
 }
 #endif
 
-#ifdef CONFIG_SOC_OMAP5
+#if defined(CONFIG_SOC_OMAP5) ||  defined(CONFIG_SOC_DRA7XX)
 void __init omap5_map_io(void)
 {
         iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
@@ -653,6 +653,22 @@ void __init omap5_init_early(void)
 }
 #endif
 
+#ifdef CONFIG_SOC_DRA7XX
+void __init dra7xx_init_early(void)
+{
+        omap2_set_globals_tap(-1, OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
+        omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
+                                  OMAP2_L4_IO_ADDRESS(DRA7XX_CTRL_BASE));
+        omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE));
+        omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE),
+                             OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
+        omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
+        omap_prm_base_init();
+        omap_cm_base_init();
+}
+#endif
+
+
 void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
                                       struct omap_sdrc_params *sdrc_cs1)
 {
diff --git a/arch/arm/mach-omap2/omap54xx.h b/arch/arm/mach-omap2/omap54xx.h
index a086ba15868b..2d35c5709408 100644
--- a/arch/arm/mach-omap2/omap54xx.h
+++ b/arch/arm/mach-omap2/omap54xx.h
@@ -30,4 +30,8 @@
 #define OMAP54XX_CTRL_BASE              0x4a002800
 #define OMAP54XX_SAR_RAM_BASE           0x4ae26000
 
+#define DRA7XX_CM_CORE_AON_BASE         0x4a005000
+#define DRA7XX_CTRL_BASE                0x4a003400
+#define DRA7XX_TAP_BASE                 0x4ae0c000
+
 #endif /* __ASM_SOC_OMAP555554XX_H */
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 7f4db12b1459..b4ecd2c7db8e 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -4113,7 +4113,7 @@ void __init omap_hwmod_init(void)
                 soc_ops.assert_hardreset = _omap2_assert_hardreset;
                 soc_ops.deassert_hardreset = _omap2_deassert_hardreset;
                 soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted;
-        } else if (cpu_is_omap44xx() || soc_is_omap54xx()) {
+        } else if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) {
                 soc_ops.enable_module = _omap4_enable_module;
                 soc_ops.disable_module = _omap4_disable_module;
                 soc_ops.wait_target_ready = _omap4_wait_target_ready;
diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h
index 8c616e436bc7..4588df1447ed 100644
--- a/arch/arm/mach-omap2/soc.h
+++ b/arch/arm/mach-omap2/soc.h
@@ -8,6 +8,7 @@
  * Written by Tony Lindgren <tony.lindgren@nokia.com>
  *
  * Added OMAP4/5 specific defines - Santosh Shilimkar<santosh.shilimkar@ti.com>
+ * Added DRA7xxx specific defines - Sricharan R<r.sricharan@ti.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -35,6 +36,7 @@
 #ifndef __ASSEMBLY__
 
 #include <linux/bitops.h>
+#include <linux/of.h>
 
 /*
  * Test if multicore OMAP support is needed
@@ -105,6 +107,15 @@
 # endif
 #endif
 
+#ifdef CONFIG_SOC_DRA7XX
+# ifdef OMAP_NAME
+#  undef MULTI_OMAP2
+#  define MULTI_OMAP2
+# else
+#  define OMAP_NAME DRA7XX
+# endif
+#endif
+
 /*
  * Omap device type i.e. EMU/HS/TST/GP/BAD
  */
@@ -233,6 +244,7 @@ IS_AM_SUBCLASS(437x, 0x437)
 #define cpu_is_omap447x()               0
 #define soc_is_omap54xx()               0
 #define soc_is_omap543x()               0
+#define soc_is_dra7xx()                 0
 
 #if defined(MULTI_OMAP2)
 # if defined(CONFIG_ARCH_OMAP2)
@@ -379,6 +391,11 @@ IS_OMAP_TYPE(3430, 0x3430)
 # define soc_is_omap543x()              is_omap543x()
 #endif
 
+#if defined(CONFIG_SOC_DRA7XX)
+#undef soc_is_dra7xx
+#define soc_is_dra7xx() (of_machine_is_compatible("ti,dra7"))
+#endif
+
 /* Various silicon revisions for omap2 */
 #define OMAP242X_CLASS          0x24200024
 #define OMAP2420_REV_ES1_0      OMAP242X_CLASS
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 801287ee4d98..fa74a0625da1 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -594,7 +594,8 @@ OMAP_SYS_GP_TIMER_INIT(3, 2, "timer_sys_ck", NULL,
                        1, "timer_sys_ck", "ti,timer-alwon");
 #endif
 
-#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
+#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
+        defined(CONFIG_SOC_DRA7XX)
 static OMAP_SYS_32K_TIMER_INIT(4, 1, "timer_32k_ck", "ti,timer-alwon",
                                2, "sys_clkin_ck", NULL);
 #endif
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index b41599f98a8e..91a5852b44f3 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -174,8 +174,10 @@ void __init orion5x_xor_init(void)
  ****************************************************************************/
 static void __init orion5x_crypto_init(void)
 {
-        mvebu_mbus_add_window("sram", ORION5X_SRAM_PHYS_BASE,
-                              ORION5X_SRAM_SIZE);
+        mvebu_mbus_add_window_by_id(ORION_MBUS_SRAM_TARGET,
+                                    ORION_MBUS_SRAM_ATTR,
+                                    ORION5X_SRAM_PHYS_BASE,
+                                    ORION5X_SRAM_SIZE);
         orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE,
                           SZ_8K, IRQ_ORION5X_CESA);
 }
@@ -222,22 +224,24 @@ void orion5x_setup_wins(void)
          * The PCIe windows will no longer be statically allocated
          * here once Orion5x is migrated to the pci-mvebu driver.
          */
-        mvebu_mbus_add_window_remap_flags("pcie0.0", ORION5X_PCIE_IO_PHYS_BASE,
+        mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCIE_IO_TARGET,
+                                          ORION_MBUS_PCIE_IO_ATTR,
+                                          ORION5X_PCIE_IO_PHYS_BASE,
                                           ORION5X_PCIE_IO_SIZE,
-                                          ORION5X_PCIE_IO_BUS_BASE,
-                                          MVEBU_MBUS_PCI_IO);
-        mvebu_mbus_add_window_remap_flags("pcie0.0", ORION5X_PCIE_MEM_PHYS_BASE,
-                                          ORION5X_PCIE_MEM_SIZE,
-                                          MVEBU_MBUS_NO_REMAP,
-                                          MVEBU_MBUS_PCI_MEM);
-        mvebu_mbus_add_window_remap_flags("pci0.0", ORION5X_PCI_IO_PHYS_BASE,
+                                          ORION5X_PCIE_IO_BUS_BASE);
+        mvebu_mbus_add_window_by_id(ORION_MBUS_PCIE_MEM_TARGET,
+                                    ORION_MBUS_PCIE_MEM_ATTR,
+                                    ORION5X_PCIE_MEM_PHYS_BASE,
+                                    ORION5X_PCIE_MEM_SIZE);
+        mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCI_IO_TARGET,
+                                          ORION_MBUS_PCI_IO_ATTR,
+                                          ORION5X_PCI_IO_PHYS_BASE,
                                           ORION5X_PCI_IO_SIZE,
-                                          ORION5X_PCI_IO_BUS_BASE,
-                                          MVEBU_MBUS_PCI_IO);
-        mvebu_mbus_add_window_remap_flags("pci0.0", ORION5X_PCI_MEM_PHYS_BASE,
-                                          ORION5X_PCI_MEM_SIZE,
-                                          MVEBU_MBUS_NO_REMAP,
-                                          MVEBU_MBUS_PCI_MEM);
+                                          ORION5X_PCI_IO_BUS_BASE);
+        mvebu_mbus_add_window_by_id(ORION_MBUS_PCI_MEM_TARGET,
+                                    ORION_MBUS_PCI_MEM_ATTR,
+                                    ORION5X_PCI_MEM_PHYS_BASE,
+                                    ORION5X_PCI_MEM_SIZE);
 }
 
 int orion5x_tclk;
diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h
index a909afb384fb..f565f9944af2 100644
--- a/arch/arm/mach-orion5x/common.h
+++ b/arch/arm/mach-orion5x/common.h
@@ -7,6 +7,23 @@ struct dsa_platform_data;
 struct mv643xx_eth_platform_data;
 struct mv_sata_platform_data;
 
+#define ORION_MBUS_PCIE_MEM_TARGET    0x04
+#define ORION_MBUS_PCIE_MEM_ATTR      0x59
+#define ORION_MBUS_PCIE_IO_TARGET     0x04
+#define ORION_MBUS_PCIE_IO_ATTR       0x51
+#define ORION_MBUS_PCIE_WA_TARGET     0x04
+#define ORION_MBUS_PCIE_WA_ATTR       0x79
+#define ORION_MBUS_PCI_MEM_TARGET     0x03
+#define ORION_MBUS_PCI_MEM_ATTR       0x59
+#define ORION_MBUS_PCI_IO_TARGET      0x03
+#define ORION_MBUS_PCI_IO_ATTR        0x51
+#define ORION_MBUS_DEVBUS_BOOT_TARGET 0x01
+#define ORION_MBUS_DEVBUS_BOOT_ATTR   0x0f
+#define ORION_MBUS_DEVBUS_TARGET(cs)  0x01
+#define ORION_MBUS_DEVBUS_ATTR(cs)    (~(1 << cs))
+#define ORION_MBUS_SRAM_TARGET        0x00
+#define ORION_MBUS_SRAM_ATTR          0x00
+
 /*
  * Basic Orion init functions used early by machine-setup.
  */
diff --git a/arch/arm/mach-orion5x/d2net-setup.c b/arch/arm/mach-orion5x/d2net-setup.c
index 16c88bbabc98..8f68b745c1d5 100644
--- a/arch/arm/mach-orion5x/d2net-setup.c
+++ b/arch/arm/mach-orion5x/d2net-setup.c
@@ -317,8 +317,10 @@ static void __init d2net_init(void)
         d2net_sata_power_init();
         orion5x_sata_init(&d2net_sata_data);
 
-        mvebu_mbus_add_window("devbus-boot", D2NET_NOR_BOOT_BASE,
-                              D2NET_NOR_BOOT_SIZE);
+        mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+                                    ORION_MBUS_DEVBUS_BOOT_ATTR,
+                                    D2NET_NOR_BOOT_BASE,
+                                    D2NET_NOR_BOOT_SIZE);
         platform_device_register(&d2net_nor_flash);
 
         platform_device_register(&d2net_gpio_buttons);
diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c
index 4e1263da38bb..4b2aefd1d961 100644
--- a/arch/arm/mach-orion5x/db88f5281-setup.c
+++ b/arch/arm/mach-orion5x/db88f5281-setup.c
@@ -340,19 +340,27 @@ static void __init db88f5281_init(void)
         orion5x_uart0_init();
         orion5x_uart1_init();
 
-        mvebu_mbus_add_window("devbus-boot", DB88F5281_NOR_BOOT_BASE,
-                              DB88F5281_NOR_BOOT_SIZE);
+        mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+                                    ORION_MBUS_DEVBUS_BOOT_ATTR,
+                                    DB88F5281_NOR_BOOT_BASE,
+                                    DB88F5281_NOR_BOOT_SIZE);
         platform_device_register(&db88f5281_boot_flash);
 
-        mvebu_mbus_add_window("devbus-cs0", DB88F5281_7SEG_BASE,
-                              DB88F5281_7SEG_SIZE);
+        mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(0),
+                                    ORION_MBUS_DEVBUS_ATTR(0),
+                                    DB88F5281_7SEG_BASE,
+                                    DB88F5281_7SEG_SIZE);
 
-        mvebu_mbus_add_window("devbus-cs1", DB88F5281_NOR_BASE,
-                              DB88F5281_NOR_SIZE);
+        mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(1),
+                                    ORION_MBUS_DEVBUS_ATTR(1),
+                                    DB88F5281_NOR_BASE,
+                                    DB88F5281_NOR_SIZE);
         platform_device_register(&db88f5281_nor_flash);
 
-        mvebu_mbus_add_window("devbus-cs2", DB88F5281_NAND_BASE,
-                              DB88F5281_NAND_SIZE);
+        mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(2),
+                                    ORION_MBUS_DEVBUS_ATTR(2),
+                                    DB88F5281_NAND_BASE,
+                                    DB88F5281_NAND_SIZE);
         platform_device_register(&db88f5281_nand_flash);
 
         i2c_register_board_info(0, &db88f5281_i2c_rtc, 1);
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
index 9e6baf581ed3..70974732cbf0 100644
--- a/arch/arm/mach-orion5x/dns323-setup.c
+++ b/arch/arm/mach-orion5x/dns323-setup.c
@@ -611,8 +611,10 @@ static void __init dns323_init(void)
         /* setup flash mapping
          * CS3 holds a 8 MB Spansion S29GL064M90TFIR4
          */
-        mvebu_mbus_add_window("devbus-boot", DNS323_NOR_BOOT_BASE,
-                              DNS323_NOR_BOOT_SIZE);
+        mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+                                    ORION_MBUS_DEVBUS_BOOT_ATTR,
+                                    DNS323_NOR_BOOT_BASE,
+                                    DNS323_NOR_BOOT_SIZE);
         platform_device_register(&dns323_nor_flash);
 
         /* Sort out LEDs, Buttons and i2c devices */
diff --git a/arch/arm/mach-orion5x/edmini_v2-setup.c b/arch/arm/mach-orion5x/edmini_v2-setup.c
index 147615510dd0..0fc33c56cbb7 100644
--- a/arch/arm/mach-orion5x/edmini_v2-setup.c
+++ b/arch/arm/mach-orion5x/edmini_v2-setup.c
@@ -154,8 +154,10 @@ void __init edmini_v2_init(void)
         orion5x_ehci0_init();
         orion5x_eth_init(&edmini_v2_eth_data);
 
-        mvebu_mbus_add_window("devbus-boot", EDMINI_V2_NOR_BOOT_BASE,
-                              EDMINI_V2_NOR_BOOT_SIZE);
+        mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+                                    ORION_MBUS_DEVBUS_BOOT_ATTR,
+                                    EDMINI_V2_NOR_BOOT_BASE,
+                                    EDMINI_V2_NOR_BOOT_SIZE);
         platform_device_register(&edmini_v2_nor_flash);
 
         pr_notice("edmini_v2: USB device port, flash write and power-off "
diff --git a/arch/arm/mach-orion5x/kurobox_pro-setup.c b/arch/arm/mach-orion5x/kurobox_pro-setup.c
index aae10e4a917c..fe6a48a325e8 100644
--- a/arch/arm/mach-orion5x/kurobox_pro-setup.c
+++ b/arch/arm/mach-orion5x/kurobox_pro-setup.c
@@ -359,13 +359,17 @@ static void __init kurobox_pro_init(void)
         orion5x_uart1_init();
         orion5x_xor_init();
 
-        mvebu_mbus_add_window("devbus-boot", KUROBOX_PRO_NOR_BOOT_BASE,
-                              KUROBOX_PRO_NOR_BOOT_SIZE);
+        mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+                                    ORION_MBUS_DEVBUS_BOOT_ATTR,
+                                    KUROBOX_PRO_NOR_BOOT_BASE,
+                                    KUROBOX_PRO_NOR_BOOT_SIZE);
         platform_device_register(&kurobox_pro_nor_flash);
 
         if (machine_is_kurobox_pro()) {
-                mvebu_mbus_add_window("devbus-cs0", KUROBOX_PRO_NAND_BASE,
-                                      KUROBOX_PRO_NAND_SIZE);
+                mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(0),
+                                            ORION_MBUS_DEVBUS_ATTR(0),
+                                            KUROBOX_PRO_NAND_BASE,
+                                            KUROBOX_PRO_NAND_SIZE);
                 platform_device_register(&kurobox_pro_nand_flash);
         }
 
diff --git a/arch/arm/mach-orion5x/ls-chl-setup.c b/arch/arm/mach-orion5x/ls-chl-setup.c
index 6234977b5aea..028ea038d404 100644
--- a/arch/arm/mach-orion5x/ls-chl-setup.c
+++ b/arch/arm/mach-orion5x/ls-chl-setup.c
@@ -294,8 +294,10 @@ static void __init lschl_init(void)
         orion5x_uart0_init();
         orion5x_xor_init();
 
-        mvebu_mbus_add_window("devbus-boot", LSCHL_NOR_BOOT_BASE,
-                              LSCHL_NOR_BOOT_SIZE);
+        mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+                                    ORION_MBUS_DEVBUS_BOOT_ATTR,
+                                    LSCHL_NOR_BOOT_BASE,
+                                    LSCHL_NOR_BOOT_SIZE);
         platform_device_register(&lschl_nor_flash);
 
         platform_device_register(&lschl_leds);
diff --git a/arch/arm/mach-orion5x/ls_hgl-setup.c b/arch/arm/mach-orion5x/ls_hgl-setup.c
index fe04c4b64569..32b7129b767d 100644
--- a/arch/arm/mach-orion5x/ls_hgl-setup.c
+++ b/arch/arm/mach-orion5x/ls_hgl-setup.c
@@ -243,8 +243,10 @@ static void __init ls_hgl_init(void)
         orion5x_uart0_init();
         orion5x_xor_init();
 
-        mvebu_mbus_add_window("devbus-boot", LS_HGL_NOR_BOOT_BASE,
-                              LS_HGL_NOR_BOOT_SIZE);
+        mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+                                    ORION_MBUS_DEVBUS_BOOT_ATTR,
+                                    LS_HGL_NOR_BOOT_BASE,
+                                    LS_HGL_NOR_BOOT_SIZE);
         platform_device_register(&ls_hgl_nor_flash);
 
         platform_device_register(&ls_hgl_button_device);
diff --git a/arch/arm/mach-orion5x/lsmini-setup.c b/arch/arm/mach-orion5x/lsmini-setup.c
index ca4dbe973daf..a6493e76f96d 100644
--- a/arch/arm/mach-orion5x/lsmini-setup.c
+++ b/arch/arm/mach-orion5x/lsmini-setup.c
@@ -244,8 +244,10 @@ static void __init lsmini_init(void)
         orion5x_uart0_init();
         orion5x_xor_init();
 
-        mvebu_mbus_add_window("devbus-boot", LSMINI_NOR_BOOT_BASE,
-                              LSMINI_NOR_BOOT_SIZE);
+        mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+                                    ORION_MBUS_DEVBUS_BOOT_ATTR,
+                                    LSMINI_NOR_BOOT_BASE,
+                                    LSMINI_NOR_BOOT_SIZE);
         platform_device_register(&lsmini_nor_flash);
 
         platform_device_register(&lsmini_button_device);
diff --git a/arch/arm/mach-orion5x/mss2-setup.c b/arch/arm/mach-orion5x/mss2-setup.c
index 827acbafc9dc..e105130ba51c 100644
--- a/arch/arm/mach-orion5x/mss2-setup.c
+++ b/arch/arm/mach-orion5x/mss2-setup.c
@@ -241,8 +241,10 @@ static void __init mss2_init(void)
         orion5x_uart0_init();
         orion5x_xor_init();
 
-        mvebu_mbus_add_window("devbus-boot", MSS2_NOR_BOOT_BASE,
-                              MSS2_NOR_BOOT_SIZE);
+        mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+                                    ORION_MBUS_DEVBUS_BOOT_ATTR,
+                                    MSS2_NOR_BOOT_BASE,
+                                    MSS2_NOR_BOOT_SIZE);
         platform_device_register(&mss2_nor_flash);
 
         platform_device_register(&mss2_button_device);
diff --git a/arch/arm/mach-orion5x/mv2120-setup.c b/arch/arm/mach-orion5x/mv2120-setup.c
index 92600ae2b4b6..e032f01da49e 100644
--- a/arch/arm/mach-orion5x/mv2120-setup.c
+++ b/arch/arm/mach-orion5x/mv2120-setup.c
@@ -204,8 +204,10 @@ static void __init mv2120_init(void)
         orion5x_uart0_init();
         orion5x_xor_init();
 
-        mvebu_mbus_add_window("devbus-boot", MV2120_NOR_BOOT_BASE,
-                              MV2120_NOR_BOOT_SIZE);
+        mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+                                    ORION_MBUS_DEVBUS_BOOT_ATTR,
+                                    MV2120_NOR_BOOT_BASE,
+                                    MV2120_NOR_BOOT_SIZE);
         platform_device_register(&mv2120_nor_flash);
 
         platform_device_register(&mv2120_button_device);
diff --git a/arch/arm/mach-orion5x/net2big-setup.c b/arch/arm/mach-orion5x/net2big-setup.c
index dd0641a0d074..ba73dc7ffb9e 100644
--- a/arch/arm/mach-orion5x/net2big-setup.c
+++ b/arch/arm/mach-orion5x/net2big-setup.c
@@ -397,8 +397,10 @@ static void __init net2big_init(void)
         net2big_sata_power_init();
         orion5x_sata_init(&net2big_sata_data);
 
-        mvebu_mbus_add_window("devbus-boot", NET2BIG_NOR_BOOT_BASE,
-                              NET2BIG_NOR_BOOT_SIZE);
+        mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+                                    ORION_MBUS_DEVBUS_BOOT_ATTR,
+                                    NET2BIG_NOR_BOOT_BASE,
+                                    NET2BIG_NOR_BOOT_SIZE);
         platform_device_register(&net2big_nor_flash);
 
         platform_device_register(&net2big_gpio_buttons);
diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c
index 503368023bb1..7fab67053030 100644
--- a/arch/arm/mach-orion5x/pci.c
+++ b/arch/arm/mach-orion5x/pci.c
@@ -157,11 +157,10 @@ static int __init pcie_setup(struct pci_sys_data *sys)
         if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) {
                 printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config "
                                    "read transaction workaround\n");
-                mvebu_mbus_add_window_remap_flags("pcie0.0",
-                                                  ORION5X_PCIE_WA_PHYS_BASE,
-                                                  ORION5X_PCIE_WA_SIZE,
-                                                  MVEBU_MBUS_NO_REMAP,
-                                                  MVEBU_MBUS_PCI_WA);
+                mvebu_mbus_add_window_by_id(ORION_MBUS_PCIE_WA_TARGET,
+                                            ORION_MBUS_PCIE_WA_ATTR,
+                                            ORION5X_PCIE_WA_PHYS_BASE,
+                                            ORION5X_PCIE_WA_SIZE);
                 pcie_ops.read = pcie_rd_conf_wa;
         }
 
diff --git a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
index 1c4498bf650a..213b3e143c57 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
@@ -123,8 +123,10 @@ static void __init rd88f5181l_fxo_init(void)
         orion5x_eth_switch_init(&rd88f5181l_fxo_switch_plat_data, NO_IRQ);
         orion5x_uart0_init();
 
-        mvebu_mbus_add_window("devbus-boot", RD88F5181L_FXO_NOR_BOOT_BASE,
-                              RD88F5181L_FXO_NOR_BOOT_SIZE);
+        mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+                                    ORION_MBUS_DEVBUS_BOOT_ATTR,
+                                    RD88F5181L_FXO_NOR_BOOT_BASE,
+                                    RD88F5181L_FXO_NOR_BOOT_SIZE);
         platform_device_register(&rd88f5181l_fxo_nor_boot_flash);
 }
 
diff --git a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
index adabe34c4fc6..594800e1d691 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
@@ -130,8 +130,10 @@ static void __init rd88f5181l_ge_init(void)
         orion5x_i2c_init();
         orion5x_uart0_init();
 
-        mvebu_mbus_add_window("devbus-boot", RD88F5181L_GE_NOR_BOOT_BASE,
-                              RD88F5181L_GE_NOR_BOOT_SIZE);
+        mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+                                    ORION_MBUS_DEVBUS_BOOT_ATTR,
+                                    RD88F5181L_GE_NOR_BOOT_BASE,
+                                    RD88F5181L_GE_NOR_BOOT_SIZE);
         platform_device_register(&rd88f5181l_ge_nor_boot_flash);
 
         i2c_register_board_info(0, &rd88f5181l_ge_i2c_rtc, 1);
diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c
index 66e77ec91532..b1cf68493ffc 100644
--- a/arch/arm/mach-orion5x/rd88f5182-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5182-setup.c
@@ -264,11 +264,14 @@ static void __init rd88f5182_init(void)
         orion5x_uart0_init();
         orion5x_xor_init();
 
-        mvebu_mbus_add_window("devbus-boot", RD88F5182_NOR_BOOT_BASE,
-                              RD88F5182_NOR_BOOT_SIZE);
-
-        mvebu_mbus_add_window("devbus-cs1", RD88F5182_NOR_BASE,
-                              RD88F5182_NOR_SIZE);
+        mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+                                    ORION_MBUS_DEVBUS_BOOT_ATTR,
+                                    RD88F5182_NOR_BOOT_BASE,
+                                    RD88F5182_NOR_BOOT_SIZE);
+        mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(1),
+                                    ORION_MBUS_DEVBUS_ATTR(1),
+                                    RD88F5182_NOR_BASE,
+                                    RD88F5182_NOR_SIZE);
         platform_device_register(&rd88f5182_nor_flash);
         platform_device_register(&rd88f5182_gpio_leds);
 
diff --git a/arch/arm/mach-orion5x/terastation_pro2-setup.c b/arch/arm/mach-orion5x/terastation_pro2-setup.c
index a0bfa53e7556..7e9064844698 100644
--- a/arch/arm/mach-orion5x/terastation_pro2-setup.c
+++ b/arch/arm/mach-orion5x/terastation_pro2-setup.c
@@ -329,8 +329,10 @@ static void __init tsp2_init(void)
         /*
          * Configure peripherals.
          */
-        mvebu_mbus_add_window("devbus-boot", TSP2_NOR_BOOT_BASE,
-                              TSP2_NOR_BOOT_SIZE);
+        mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+                                    ORION_MBUS_DEVBUS_BOOT_ATTR,
+                                    TSP2_NOR_BOOT_BASE,
+                                    TSP2_NOR_BOOT_SIZE);
         platform_device_register(&tsp2_nor_flash);
 
         orion5x_ehci0_init();
diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c
index 80174f0f168e..e90c0618fdad 100644
--- a/arch/arm/mach-orion5x/ts209-setup.c
+++ b/arch/arm/mach-orion5x/ts209-setup.c
@@ -286,8 +286,10 @@ static void __init qnap_ts209_init(void)
         /*
          * Configure peripherals.
          */
-        mvebu_mbus_add_window("devbus-boot", QNAP_TS209_NOR_BOOT_BASE,
-                              QNAP_TS209_NOR_BOOT_SIZE);
+        mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+                                    ORION_MBUS_DEVBUS_BOOT_ATTR,
+                                    QNAP_TS209_NOR_BOOT_BASE,
+                                    QNAP_TS209_NOR_BOOT_SIZE);
         platform_device_register(&qnap_ts209_nor_flash);
 
         orion5x_ehci0_init();
diff --git a/arch/arm/mach-orion5x/ts409-setup.c b/arch/arm/mach-orion5x/ts409-setup.c
index 92592790d6da..5c079d312015 100644
--- a/arch/arm/mach-orion5x/ts409-setup.c
+++ b/arch/arm/mach-orion5x/ts409-setup.c
@@ -277,8 +277,10 @@ static void __init qnap_ts409_init(void)
         /*
          * Configure peripherals.
          */
-        mvebu_mbus_add_window("devbus-boot", QNAP_TS409_NOR_BOOT_BASE,
-                              QNAP_TS409_NOR_BOOT_SIZE);
+        mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+                                    ORION_MBUS_DEVBUS_BOOT_ATTR,
+                                    QNAP_TS409_NOR_BOOT_BASE,
+                                    QNAP_TS409_NOR_BOOT_SIZE);
         platform_device_register(&qnap_ts409_nor_flash);
 
         orion5x_ehci0_init();
diff --git a/arch/arm/mach-orion5x/wnr854t-setup.c b/arch/arm/mach-orion5x/wnr854t-setup.c
index 6b84863c018d..80a56ee245b3 100644
--- a/arch/arm/mach-orion5x/wnr854t-setup.c
+++ b/arch/arm/mach-orion5x/wnr854t-setup.c
@@ -127,8 +127,10 @@ static void __init wnr854t_init(void)
         orion5x_eth_switch_init(&wnr854t_switch_plat_data, NO_IRQ);
         orion5x_uart0_init();
 
-        mvebu_mbus_add_window("devbus-boot", WNR854T_NOR_BOOT_BASE,
-                              WNR854T_NOR_BOOT_SIZE);
+        mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+                                    ORION_MBUS_DEVBUS_BOOT_ATTR,
+                                    WNR854T_NOR_BOOT_BASE,
+                                    WNR854T_NOR_BOOT_SIZE);
         platform_device_register(&wnr854t_nor_flash);
 }
 
diff --git a/arch/arm/mach-orion5x/wrt350n-v2-setup.c b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
index fae684bc54f2..670e30dc0d1b 100644
--- a/arch/arm/mach-orion5x/wrt350n-v2-setup.c
+++ b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
@@ -213,8 +213,10 @@ static void __init wrt350n_v2_init(void)
         orion5x_eth_switch_init(&wrt350n_v2_switch_plat_data, NO_IRQ);
         orion5x_uart0_init();
 
-        mvebu_mbus_add_window("devbus-boot", WRT350N_V2_NOR_BOOT_BASE,
-                              WRT350N_V2_NOR_BOOT_SIZE);
+        mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
+                                    ORION_MBUS_DEVBUS_BOOT_ATTR,
+                                    WRT350N_V2_NOR_BOOT_BASE,
+                                    WRT350N_V2_NOR_BOOT_SIZE);
         platform_device_register(&wrt350n_v2_nor_flash);
         platform_device_register(&wrt350n_v2_leds);
         platform_device_register(&wrt350n_v2_button_device);
diff --git a/arch/arm/mach-prima2/pm.c b/arch/arm/mach-prima2/pm.c
index 02cc34388b05..c4525a88e5da 100644
--- a/arch/arm/mach-prima2/pm.c
+++ b/arch/arm/mach-prima2/pm.c
@@ -34,7 +34,10 @@ static void sirfsoc_set_wakeup_source(void)
         pwr_trigger_en_reg = sirfsoc_rtc_iobrg_readl(sirfsoc_pwrc_base +
                 SIRFSOC_PWRC_TRIGGER_EN);
 #define X_ON_KEY_B (1 << 0)
-        sirfsoc_rtc_iobrg_writel(pwr_trigger_en_reg | X_ON_KEY_B,
+#define RTC_ALARM0_B (1 << 2)
+#define RTC_ALARM1_B (1 << 3)
+        sirfsoc_rtc_iobrg_writel(pwr_trigger_en_reg | X_ON_KEY_B |
+                RTC_ALARM0_B | RTC_ALARM1_B,
                 sirfsoc_pwrc_base + SIRFSOC_PWRC_TRIGGER_EN);
 }
 
@@ -85,12 +88,6 @@ static const struct platform_suspend_ops sirfsoc_pm_ops = {
         .valid = suspend_valid_only_mem,
 };
 
-int __init sirfsoc_pm_init(void)
-{
-        suspend_set_ops(&sirfsoc_pm_ops);
-        return 0;
-}
-
 static const struct of_device_id pwrc_ids[] = {
         { .compatible = "sirf,prima2-pwrc" },
         {}
@@ -118,7 +115,6 @@ static int __init sirfsoc_of_pwrc_init(void)
 
         return 0;
 }
-postcore_initcall(sirfsoc_of_pwrc_init);
 
 static const struct of_device_id memc_ids[] = {
         { .compatible = "sirf,prima2-memc" },
@@ -149,4 +145,11 @@ static int __init sirfsoc_memc_init(void)
 {
         return platform_driver_register(&sirfsoc_memc_driver);
 }
-postcore_initcall(sirfsoc_memc_init);
+
+int __init sirfsoc_pm_init(void)
+{
+        sirfsoc_of_pwrc_init();
+        sirfsoc_memc_init();
+        suspend_set_ops(&sirfsoc_pm_ops);
+        return 0;
+}
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index cdefd7dcca79..403c939ddf99 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -61,9 +61,10 @@ config ARCH_R8A73A4
         select ARCH_WANT_OPTIONAL_GPIOLIB
         select ARM_GIC
         select CPU_V7
-        select HAVE_ARM_ARCH_TIMER
         select SH_CLK_CPG
         select RENESAS_IRQC
+        select ARCH_HAS_CPUFREQ
+        select ARCH_HAS_OPP
 
 config ARCH_R8A7740
         bool "R-Mobile A1 (R8A77400)"
@@ -97,7 +98,6 @@ config ARCH_R8A7790
         select ARCH_WANT_OPTIONAL_GPIOLIB
         select ARM_GIC
         select CPU_V7
-        select HAVE_ARM_ARCH_TIMER
         select SH_CLK_CPG
         select RENESAS_IRQC
 
diff --git a/arch/arm/mach-shmobile/board-ape6evm.c b/arch/arm/mach-shmobile/board-ape6evm.c
index 1fbc39a14e25..af6dd39d3758 100644
--- a/arch/arm/mach-shmobile/board-ape6evm.c
+++ b/arch/arm/mach-shmobile/board-ape6evm.c
@@ -101,6 +101,7 @@ static const char *ape6evm_boards_compat_dt[] __initdata = {
 };
 
 DT_MACHINE_START(APE6EVM_DT, "ape6evm")
+        .init_early     = r8a73a4_init_delay,
         .init_time      = shmobile_timer_init,
         .init_machine   = ape6evm_add_standard_devices,
         .dt_compat      = ape6evm_boards_compat_dt,
diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c
index 78d92d34665d..f89f16650731 100644
--- a/arch/arm/mach-shmobile/board-lager.c
+++ b/arch/arm/mach-shmobile/board-lager.c
@@ -102,6 +102,7 @@ static const char *lager_boards_compat_dt[] __initdata = {
 };
 
 DT_MACHINE_START(LAGER_DT, "lager")
+        .init_early     = r8a7790_init_delay,
         .init_time      = r8a7790_timer_init,
         .init_machine   = lager_add_standard_devices,
         .dt_compat      = lager_boards_compat_dt,
diff --git a/arch/arm/mach-shmobile/clock-emev2.c b/arch/arm/mach-shmobile/clock-emev2.c
index 56dd0cfcddc7..5ac13ba71d54 100644
--- a/arch/arm/mach-shmobile/clock-emev2.c
+++ b/arch/arm/mach-shmobile/clock-emev2.c
@@ -40,7 +40,6 @@
 #define USIB2SCLKDIV 0x65c
 #define USIB3SCLKDIV 0x660
 #define STI_CLKSEL 0x688
-#define SMU_GENERAL_REG0 0x7c0
 
 /* not pretty, but hey */
 static void __iomem *smu_base;
@@ -51,11 +50,6 @@ static void emev2_smu_write(unsigned long value, int offs)
         iowrite32(value, smu_base + offs);
 }
 
-void emev2_set_boot_vector(unsigned long value)
-{
-        emev2_smu_write(value, SMU_GENERAL_REG0);
-}
-
 static struct clk_mapping smu_mapping = {
         .phys   = EMEV2_SMU_BASE,
         .len    = PAGE_SIZE,
@@ -205,18 +199,6 @@ static struct clk_lookup lookups[] = {
 void __init emev2_clock_init(void)
 {
         int k, ret = 0;
-        static int is_setup;
-
-        /* yuck, this is ugly as hell, but the non-smp case of clocks
-         * code is now designed to rely on ioremap() instead of static
-         * entity maps. in the case of smp we need access to the SMU
-         * register earlier than ioremap() is actually working without
-         * any static maps. to enable SMP in ugly but with dynamic
-         * mappings we have to call emev2_clock_init() from different
-         * places depending on UP and SMP...
-         */
-        if (is_setup++)
-                return;
 
         smu_base = ioremap(EMEV2_SMU_BASE, PAGE_SIZE);
         BUG_ON(!smu_base);
diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c
index 5f7fe628b8a1..8ea5ef6c79cc 100644
--- a/arch/arm/mach-shmobile/clock-r8a73a4.c
+++ b/arch/arm/mach-shmobile/clock-r8a73a4.c
@@ -30,10 +30,12 @@
 
 #define SMSTPCR2 0xe6150138
 #define SMSTPCR3 0xe615013c
+#define SMSTPCR4 0xe6150140
 #define SMSTPCR5 0xe6150144
 
 #define FRQCRA          0xE6150000
 #define FRQCRB          0xE6150004
+#define FRQCRC          0xE61500E0
 #define VCLKCR1         0xE6150008
 #define VCLKCR2         0xE615000C
 #define VCLKCR3         0xE615001C
@@ -52,6 +54,7 @@
 #define HSICKCR         0xE615026C
 #define M4CKCR          0xE6150098
 #define PLLECR          0xE61500D0
+#define PLL0CR          0xE61500D8
 #define PLL1CR          0xE6150028
 #define PLL2CR          0xE615002C
 #define PLL2SCR         0xE61501F4
@@ -177,6 +180,7 @@ static struct sh_clk_ops pll_clk_ops = {
                 .mapping        = &cpg_mapping,         \
         }
 
+PLL_CLOCK(pll0_clk,  &main_clk,      pll_parent_main,      1, 20, PLL0CR,  0);
 PLL_CLOCK(pll1_clk,  &main_clk,      pll_parent_main,       1, 7, PLL1CR,  1);
 PLL_CLOCK(pll2_clk,  &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2CR,  2);
 PLL_CLOCK(pll2s_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2SCR, 4);
@@ -184,6 +188,157 @@ PLL_CLOCK(pll2h_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2HCR, 5);
 
 SH_FIXED_RATIO_CLK(pll1_div2_clk,       pll1_clk,       div2);
 
+static atomic_t frqcr_lock;
+
+/* Several clocks need to access FRQCRB, have to lock */
+static bool frqcr_kick_check(struct clk *clk)
+{
+        return !(ioread32(CPG_MAP(FRQCRB)) & BIT(31));
+}
+
+static int frqcr_kick_do(struct clk *clk)
+{
+        int i;
+
+        /* set KICK bit in FRQCRB to update hardware setting, check success */
+        iowrite32(ioread32(CPG_MAP(FRQCRB)) | BIT(31), CPG_MAP(FRQCRB));
+        for (i = 1000; i; i--)
+                if (ioread32(CPG_MAP(FRQCRB)) & BIT(31))
+                        cpu_relax();
+                else
+                        return 0;
+
+        return -ETIMEDOUT;
+}
+
+static int zclk_set_rate(struct clk *clk, unsigned long rate)
+{
+        void __iomem *frqcrc;
+        int ret;
+        unsigned long step, p_rate;
+        u32 val;
+
+        if (!clk->parent || !__clk_get(clk->parent))
+                return -ENODEV;
+
+        if (!atomic_inc_and_test(&frqcr_lock) || !frqcr_kick_check(clk)) {
+                ret = -EBUSY;
+                goto done;
+        }
+
+        /*
+         * Users are supposed to first call clk_set_rate() only with
+         * clk_round_rate() results. So, we don't fix wrong rates here, but
+         * guard against them anyway
+         */
+
+        p_rate = clk_get_rate(clk->parent);
+        if (rate == p_rate) {
+                val = 0;
+        } else {
+                step = DIV_ROUND_CLOSEST(p_rate, 32);
+
+                if (rate > p_rate || rate < step) {
+                        ret = -EINVAL;
+                        goto done;
+                }
+
+                val = 32 - rate / step;
+        }
+
+        frqcrc = clk->mapped_reg + (FRQCRC - (u32)clk->enable_reg);
+
+        iowrite32((ioread32(frqcrc) & ~(clk->div_mask << clk->enable_bit)) |
+                  (val << clk->enable_bit), frqcrc);
+
+        ret = frqcr_kick_do(clk);
+
+done:
+        atomic_dec(&frqcr_lock);
+        __clk_put(clk->parent);
+        return ret;
+}
+
+static long zclk_round_rate(struct clk *clk, unsigned long rate)
+{
+        /*
+         * theoretical rate = parent rate * multiplier / 32,
+         * where 1 <= multiplier <= 32. Therefore we should do
+         * multiplier = rate * 32 / parent rate
+         * rounded rate = parent rate * multiplier / 32.
+         * However, multiplication before division won't fit in 32 bits, so
+         * we sacrifice some precision by first dividing and then multiplying.
+         * To find the nearest divisor we calculate both and pick up the best
+         * one. This avoids 64-bit arithmetics.
+         */
+        unsigned long step, mul_min, mul_max, rate_min, rate_max;
+
+        rate_max = clk_get_rate(clk->parent);
+
+        /* output freq <= parent */
+        if (rate >= rate_max)
+                return rate_max;
+
+        step = DIV_ROUND_CLOSEST(rate_max, 32);
+        /* output freq >= parent / 32 */
+        if (step >= rate)
+                return step;
+
+        mul_min = rate / step;
+        mul_max = DIV_ROUND_UP(rate, step);
+        rate_min = step * mul_min;
+        if (mul_max == mul_min)
+                return rate_min;
+
+        rate_max = step * mul_max;
+
+        if (rate_max - rate <  rate - rate_min)
+                return rate_max;
+
+        return rate_min;
+}
+
+static unsigned long zclk_recalc(struct clk *clk)
+{
+        void __iomem *frqcrc = FRQCRC - (u32)clk->enable_reg + clk->mapped_reg;
+        unsigned int max = clk->div_mask + 1;
+        unsigned long val = ((ioread32(frqcrc) >> clk->enable_bit) &
+                             clk->div_mask);
+
+        return DIV_ROUND_CLOSEST(clk_get_rate(clk->parent), max) *
+                (max - val);
+}
+
+static struct sh_clk_ops zclk_ops = {
+        .recalc = zclk_recalc,
+        .set_rate = zclk_set_rate,
+        .round_rate = zclk_round_rate,
+};
+
+static struct clk z_clk = {
+        .parent = &pll0_clk,
+        .div_mask = 0x1f,
+        .enable_bit = 8,
+        /* We'll need to access FRQCRB and FRQCRC */
+        .enable_reg = (void __iomem *)FRQCRB,
+        .ops = &zclk_ops,
+};
+
+/*
+ * It seems only 1/2 divider is usable in manual mode. 1/2 / 2/3
+ * switching is only available in auto-DVFS mode
+ */
+SH_FIXED_RATIO_CLK(pll0_div2_clk,       pll0_clk,               div2);
+
+static struct clk z2_clk = {
+        .parent = &pll0_div2_clk,
+        .div_mask = 0x1f,
+        .enable_bit = 0,
+        /* We'll need to access FRQCRB and FRQCRC */
+        .enable_reg = (void __iomem *)FRQCRB,
+        .ops = &zclk_ops,
+};
+
 static struct clk *main_clks[] = {
         &extalr_clk,
         &extal1_clk,
@@ -195,22 +350,23 @@ static struct clk *main_clks[] = {
         &main_div2_clk,
         &fsiack_clk,
         &fsibck_clk,
+        &pll0_clk,
         &pll1_clk,
         &pll1_div2_clk,
         &pll2_clk,
         &pll2s_clk,
         &pll2h_clk,
+        &z_clk,
+        &pll0_div2_clk,
+        &z2_clk,
 };
 
 /* DIV4 */
 static void div4_kick(struct clk *clk)
 {
-        unsigned long value;
-
-        /* set KICK bit in FRQCRB to update hardware setting */
-        value = ioread32(CPG_MAP(FRQCRB));
-        value |= (1 << 31);
-        iowrite32(value, CPG_MAP(FRQCRB));
+        if (!WARN(!atomic_inc_and_test(&frqcr_lock), "FRQCR* lock broken!\n"))
+                frqcr_kick_do(clk);
+        atomic_dec(&frqcr_lock);
 }
 
 static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10};
@@ -349,8 +505,10 @@ static struct clk div6_clks[DIV6_NR] = {
 /* MSTP */
 enum {
         MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203,
-        MSTP315, MSTP314, MSTP313, MSTP312, MSTP305,
-        MSTP522,
+        MSTP329, MSTP323, MSTP318, MSTP317, MSTP316,
+        MSTP315, MSTP314, MSTP313, MSTP312, MSTP305, MSTP300,
+        MSTP411, MSTP410, MSTP409,
+        MSTP522, MSTP515,
         MSTP_NR
 };
 
@@ -361,12 +519,22 @@ static struct clk mstp_clks[MSTP_NR] = {
         [MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],  SMSTPCR2, 7, 0), /* SCIFB1 */
         [MSTP216] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],  SMSTPCR2, 16, 0), /* SCIFB2 */
         [MSTP217] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],  SMSTPCR2, 17, 0), /* SCIFB3 */
+        [MSTP300] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR3, 0, 0), /* IIC2 */
         [MSTP305] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC1],SMSTPCR3, 5, 0), /* MMCIF1 */
         [MSTP312] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI2],SMSTPCR3, 12, 0), /* SDHI2 */
         [MSTP313] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI1],SMSTPCR3, 13, 0), /* SDHI1 */
         [MSTP314] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI0],SMSTPCR3, 14, 0), /* SDHI0 */
         [MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0],SMSTPCR3, 15, 0), /* MMCIF0 */
+        [MSTP316] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR3, 16, 0), /* IIC6 */
+        [MSTP317] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR3, 17, 0), /* IIC7 */
+        [MSTP318] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR3, 18, 0), /* IIC0 */
+        [MSTP323] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR3, 23, 0), /* IIC1 */
+        [MSTP329] = SH_CLK_MSTP32(&extalr_clk, SMSTPCR3, 29, 0), /* CMT10 */
+        [MSTP409] = SH_CLK_MSTP32(&main_div2_clk,       SMSTPCR4, 9, 0), /* IIC5 */
+        [MSTP410] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR4, 10, 0), /* IIC4 */
+        [MSTP411] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR4, 11, 0), /* IIC3 */
         [MSTP522] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR5, 22, 0), /* Thermal */
+        [MSTP515] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR5, 15, 0), /* IIC8 */
 };
 
 static struct clk_lookup lookups[] = {
@@ -386,6 +554,9 @@ static struct clk_lookup lookups[] = {
         CLKDEV_CON_ID("pll2s",                  &pll2s_clk),
         CLKDEV_CON_ID("pll2h",                  &pll2h_clk),
 
+        /* CPU clock */
+        CLKDEV_DEV_ID("cpufreq-cpu0",           &z_clk),
+
         /* DIV6 */
         CLKDEV_CON_ID("zb",                     &div6_clks[DIV6_ZB]),
         CLKDEV_CON_ID("vck1",                   &div6_clks[DIV6_VCK1]),
@@ -408,6 +579,7 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]),
         CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP217]),
         CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
+        CLKDEV_DEV_ID("e6520000.i2c", &mstp_clks[MSTP300]),
         CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
         CLKDEV_DEV_ID("ee220000.mmcif", &mstp_clks[MSTP305]),
         CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]),
@@ -418,6 +590,15 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]),
         CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]),
         CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]),
+        CLKDEV_DEV_ID("e6550000.i2c", &mstp_clks[MSTP316]),
+        CLKDEV_DEV_ID("e6560000.i2c", &mstp_clks[MSTP317]),
+        CLKDEV_DEV_ID("e6500000.i2c", &mstp_clks[MSTP318]),
+        CLKDEV_DEV_ID("e6510000.i2c", &mstp_clks[MSTP323]),
+        CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]),
+        CLKDEV_DEV_ID("e60b0000.i2c", &mstp_clks[MSTP409]),
+        CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP410]),
+        CLKDEV_DEV_ID("e6530000.i2c", &mstp_clks[MSTP411]),
+        CLKDEV_DEV_ID("e6570000.i2c", &mstp_clks[MSTP515]),
 
         /* for DT */
         CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
@@ -429,6 +610,8 @@ void __init r8a73a4_clock_init(void)
         int k, ret = 0;
         u32 ckscr;
 
+        atomic_set(&frqcr_lock, -1);
+
         reg = ioremap_nocache(CKSCR, PAGE_SIZE);
         BUG_ON(!reg);
         ckscr = ioread32(reg);
diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
index f4265e52432c..c826bca4024e 100644
--- a/arch/arm/mach-shmobile/clock-r8a7740.c
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -597,6 +597,7 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("r8a7740-gether",         &mstp_clks[MSTP309]),
         CLKDEV_DEV_ID("e9a00000.sh-eth",        &mstp_clks[MSTP309]),
         CLKDEV_DEV_ID("renesas-tpu-pwm",        &mstp_clks[MSTP304]),
+        CLKDEV_DEV_ID("e6600000.pwm",           &mstp_clks[MSTP304]),
 
         CLKDEV_DEV_ID("sh_mobile_sdhi.2",       &mstp_clks[MSTP415]),
         CLKDEV_DEV_ID("e6870000.sdhi",          &mstp_clks[MSTP415]),
diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
index 5d71313df52d..fc36d3db0b4d 100644
--- a/arch/arm/mach-shmobile/clock-r8a7790.c
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -24,6 +24,7 @@
 #include <linux/clkdev.h>
 #include <mach/clock.h>
 #include <mach/common.h>
+#include <mach/r8a7790.h>
 
 /*
  *   MD         EXTAL           PLL0    PLL1    PLL3
@@ -42,16 +43,16 @@
  *      see "p1 / 2" on R8A7790_CLOCK_ROOT() below
  */
 
-#define MD(nr)  (1 << nr)
-
 #define CPG_BASE 0xe6150000
 #define CPG_LEN 0x1000
 
+#define SMSTPCR1 0xe6150134
 #define SMSTPCR2 0xe6150138
 #define SMSTPCR3 0xe615013c
+#define SMSTPCR5 0xe6150144
 #define SMSTPCR7 0xe615014c
+#define SMSTPCR8 0xe6150990
 
-#define MODEMR          0xE6160060
 #define SDCKCR          0xE6150074
 #define SD2CKCR         0xE6150078
 #define SD3CKCR         0xE615007C
@@ -180,16 +181,23 @@ static struct clk div6_clks[DIV6_NR] = {
 
 /* MSTP */
 enum {
+        MSTP813,
         MSTP721, MSTP720,
         MSTP717, MSTP716,
+        MSTP522,
         MSTP315, MSTP314, MSTP313, MSTP312, MSTP311, MSTP305, MSTP304,
         MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202,
+        MSTP124,
         MSTP_NR
 };
 
 static struct clk mstp_clks[MSTP_NR] = {
+        [MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */
         [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */
         [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
+        [MSTP717] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 17, 0), /* HSCIF0 */
+        [MSTP716] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 16, 0), /* HSCIF1 */
+        [MSTP522] = SH_CLK_MSTP32(&extal_clk, SMSTPCR5, 22, 0), /* Thermal */
         [MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0], SMSTPCR3, 15, 0), /* MMC0 */
         [MSTP314] = SH_CLK_MSTP32(&div4_clks[DIV4_SD0], SMSTPCR3, 14, 0), /* SDHI0 */
         [MSTP313] = SH_CLK_MSTP32(&div4_clks[DIV4_SD1], SMSTPCR3, 13, 0), /* SDHI1 */
@@ -203,8 +211,7 @@ static struct clk mstp_clks[MSTP_NR] = {
         [MSTP204] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 4, 0), /* SCIFA0 */
         [MSTP203] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 3, 0), /* SCIFA1 */
         [MSTP202] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 2, 0), /* SCIFA2 */
-        [MSTP717] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 17, 0), /* HSCIF0 */
-        [MSTP716] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 16, 0), /* HSCIF1 */
+        [MSTP124] = SH_CLK_MSTP32(&rclk_clk, SMSTPCR1, 24, 0), /* CMT0 */
 };
 
 static struct clk_lookup lookups[] = {
@@ -254,6 +261,8 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]),
         CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP717]),
         CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP716]),
+        CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]),
+        CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
         CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]),
         CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]),
         CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]),
@@ -266,6 +275,7 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP311]),
         CLKDEV_DEV_ID("ee220000.mmcif", &mstp_clks[MSTP305]),
         CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
+        CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]),
 };
 
 #define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31)              \
@@ -280,14 +290,9 @@ static struct clk_lookup lookups[] = {
 
 void __init r8a7790_clock_init(void)
 {
-        void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
-        u32 mode;
+        u32 mode = r8a7790_read_mode_pins();
         int k, ret = 0;
 
-        BUG_ON(!modemr);
-        mode = ioread32(modemr);
-        iounmap(modemr);
-
         switch (mode & (MD(14) | MD(13))) {
         case 0:
                 R8A7790_CLOCK_ROOT(15, &extal_clk, 172, 208, 106, 88);
diff --git a/arch/arm/mach-shmobile/include/mach/emev2.h b/arch/arm/mach-shmobile/include/mach/emev2.h
index b0ab4b72770a..c2eb7568d9be 100644
--- a/arch/arm/mach-shmobile/include/mach/emev2.h
+++ b/arch/arm/mach-shmobile/include/mach/emev2.h
@@ -5,7 +5,6 @@ extern void emev2_map_io(void);
 extern void emev2_init_delay(void);
 extern void emev2_add_standard_devices(void);
 extern void emev2_clock_init(void);
-extern void emev2_set_boot_vector(unsigned long value);
 
 #define EMEV2_GPIO_BASE 200
 #define EMEV2_GPIO_IRQ(n) (EMEV2_GPIO_BASE + (n))
diff --git a/arch/arm/mach-shmobile/include/mach/r8a73a4.h b/arch/arm/mach-shmobile/include/mach/r8a73a4.h
index f043103e32c9..144a85e29245 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a73a4.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a73a4.h
@@ -4,5 +4,6 @@
 void r8a73a4_add_standard_devices(void);
 void r8a73a4_clock_init(void);
 void r8a73a4_pinmux_init(void);
+void r8a73a4_init_delay(void);
 
 #endif /* __ASM_R8A73A4_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h
index b34d19b5ca5c..56f375005fcd 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7740.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h
@@ -42,6 +42,8 @@ enum {
         SHDMA_SLAVE_FSIB_TX,
         SHDMA_SLAVE_USBHS_TX,
         SHDMA_SLAVE_USBHS_RX,
+        SHDMA_SLAVE_MMCIF_TX,
+        SHDMA_SLAVE_MMCIF_RX,
 };
 
 extern void r8a7740_meram_workaround(void);
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7790.h b/arch/arm/mach-shmobile/include/mach/r8a7790.h
index 2e919e61fa0d..7aaef409a059 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7790.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7790.h
@@ -4,6 +4,10 @@
 void r8a7790_add_standard_devices(void);
 void r8a7790_clock_init(void);
 void r8a7790_pinmux_init(void);
+void r8a7790_init_delay(void);
 void r8a7790_timer_init(void);
 
+#define MD(nr) BIT(nr)
+u32 r8a7790_read_mode_pins(void);
+
 #endif /* __ASM_R8A7790_H__ */
diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c
index a8c4e41bf27a..d533bd23865c 100644
--- a/arch/arm/mach-shmobile/setup-r8a73a4.c
+++ b/arch/arm/mach-shmobile/setup-r8a73a4.c
@@ -22,6 +22,7 @@
 #include <linux/of_platform.h>
 #include <linux/platform_data/irq-renesas-irqc.h>
 #include <linux/serial_sci.h>
+#include <linux/sh_timer.h>
 #include <mach/common.h>
 #include <mach/irqs.h>
 #include <mach/r8a73a4.h>
@@ -168,6 +169,25 @@ static const struct resource thermal0_resources[] = {
                                         thermal0_resources,             \
                                         ARRAY_SIZE(thermal0_resources))
 
+static struct sh_timer_config cmt10_platform_data = {
+        .name = "CMT10",
+        .timer_bit = 0,
+        .clockevent_rating = 80,
+};
+
+static struct resource cmt10_resources[] = {
+        DEFINE_RES_MEM(0xe6130010, 0x0c),
+        DEFINE_RES_MEM(0xe6130000, 0x04),
+        DEFINE_RES_IRQ(gic_spi(120)), /* CMT1_0 */
+};
+
+#define r8a7790_register_cmt(idx)                                       \
+        platform_device_register_resndata(&platform_bus, "sh_cmt",      \
+                                          idx, cmt##idx##_resources,    \
+                                          ARRAY_SIZE(cmt##idx##_resources), \
+                                          &cmt##idx##_platform_data,    \
+                                          sizeof(struct sh_timer_config))
+
 void __init r8a73a4_add_standard_devices(void)
 {
         r8a73a4_register_scif(SCIFA0);
@@ -179,11 +199,20 @@ void __init r8a73a4_add_standard_devices(void)
         r8a73a4_register_irqc(0);
         r8a73a4_register_irqc(1);
         r8a73a4_register_thermal();
+        r8a7790_register_cmt(10);
+}
+
+void __init r8a73a4_init_delay(void)
+{
+#ifndef CONFIG_ARM_ARCH_TIMER
+        shmobile_setup_delay(1500, 2, 4); /* Cortex-A15 @ 1500MHz */
+#endif
 }
 
 #ifdef CONFIG_USE_OF
 void __init r8a73a4_add_standard_devices_dt(void)
 {
+        platform_device_register_simple("cpufreq-cpu0", -1, NULL, 0);
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
@@ -193,6 +222,7 @@ static const char *r8a73a4_boards_compat_dt[] __initdata = {
 };
 
 DT_MACHINE_START(R8A73A4_DT, "Generic R8A73A4 (Flattened Device Tree)")
+        .init_early     = r8a73a4_init_delay,
         .init_machine   = r8a73a4_add_standard_devices_dt,
         .init_time      = shmobile_timer_init,
         .dt_compat      = r8a73a4_boards_compat_dt,
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index ac29c2ee011f..84c5bb6d9725 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -588,6 +588,16 @@ static const struct sh_dmae_slave_config r8a7740_dmae_slaves[] = {
                 .addr           = 0xfe1f0064,
                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
                 .mid_rid        = 0xb5,
+        }, {
+                .slave_id       = SHDMA_SLAVE_MMCIF_TX,
+                .addr           = 0xe6bd0034,
+                .chcr           = CHCR_TX(XMIT_SZ_32BIT),
+                .mid_rid        = 0xd1,
+        }, {
+                .slave_id       = SHDMA_SLAVE_MMCIF_RX,
+                .addr           = 0xe6bd0034,
+                .chcr           = CHCR_RX(XMIT_SZ_32BIT),
+                .mid_rid        = 0xd2,
         },
 };
 
diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
index b7e78b9a7fdf..4c96dad21195 100644
--- a/arch/arm/mach-shmobile/setup-r8a7790.c
+++ b/arch/arm/mach-shmobile/setup-r8a7790.c
@@ -21,9 +21,10 @@
 #include <linux/irq.h>
 #include <linux/kernel.h>
 #include <linux/of_platform.h>
-#include <linux/serial_sci.h>
 #include <linux/platform_data/gpio-rcar.h>
 #include <linux/platform_data/irq-renesas-irqc.h>
+#include <linux/serial_sci.h>
+#include <linux/sh_timer.h>
 #include <mach/common.h>
 #include <mach/irqs.h>
 #include <mach/r8a7790.h>
@@ -148,6 +149,36 @@ static struct resource irqc0_resources[] __initdata = {
                                           &irqc##idx##_data,            \
                                           sizeof(struct renesas_irqc_config))
 
+static struct resource thermal_resources[] __initdata = {
+        DEFINE_RES_MEM(0xe61f0000, 0x14),
+        DEFINE_RES_MEM(0xe61f0100, 0x38),
+        DEFINE_RES_IRQ(gic_spi(69)),
+};
+
+#define r8a7790_register_thermal()                                      \
+        platform_device_register_simple("rcar_thermal", -1,             \
+                                        thermal_resources,              \
+                                        ARRAY_SIZE(thermal_resources))
+
+static struct sh_timer_config cmt00_platform_data = {
+        .name = "CMT00",
+        .timer_bit = 0,
+        .clockevent_rating = 80,
+};
+
+static struct resource cmt00_resources[] = {
+        DEFINE_RES_MEM(0xffca0510, 0x0c),
+        DEFINE_RES_MEM(0xffca0500, 0x04),
+        DEFINE_RES_IRQ(gic_spi(142)), /* CMT0_0 */
+};
+
+#define r8a7790_register_cmt(idx)                                       \
+        platform_device_register_resndata(&platform_bus, "sh_cmt",      \
+                                          idx, cmt##idx##_resources,    \
+                                          ARRAY_SIZE(cmt##idx##_resources), \
+                                          &cmt##idx##_platform_data,    \
+                                          sizeof(struct sh_timer_config))
+
 void __init r8a7790_add_standard_devices(void)
 {
         r8a7790_register_scif(SCIFA0);
@@ -161,20 +192,82 @@ void __init r8a7790_add_standard_devices(void)
         r8a7790_register_scif(HSCIF0);
         r8a7790_register_scif(HSCIF1);
         r8a7790_register_irqc(0);
+        r8a7790_register_thermal();
+        r8a7790_register_cmt(00);
 }
 
+#define MODEMR 0xe6160060
+
+u32 __init r8a7790_read_mode_pins(void)
+{
+        void __iomem *modemr = ioremap_nocache(MODEMR, 4);
+        u32 mode;
+
+        BUG_ON(!modemr);
+        mode = ioread32(modemr);
+        iounmap(modemr);
+
+        return mode;
+}
+
+#define CNTCR 0
+#define CNTFID0 0x20
+
 void __init r8a7790_timer_init(void)
 {
-        void __iomem *cntcr;
+#ifdef CONFIG_ARM_ARCH_TIMER
+        u32 mode = r8a7790_read_mode_pins();
+        void __iomem *base;
+        int extal_mhz = 0;
+        u32 freq;
+
+        /* At Linux boot time the r8a7790 arch timer comes up
+         * with the counter disabled. Moreover, it may also report
+         * a potentially incorrect fixed 13 MHz frequency. To be
+         * correct these registers need to be updated to use the
+         * frequency EXTAL / 2 which can be determined by the MD pins.
+         */
+
+        switch (mode & (MD(14) | MD(13))) {
+        case 0:
+                extal_mhz = 15;
+                break;
+        case MD(13):
+                extal_mhz = 20;
+                break;
+        case MD(14):
+                extal_mhz = 26;
+                break;
+        case MD(13) | MD(14):
+                extal_mhz = 30;
+                break;
+        }
 
-        /* make sure arch timer is started by setting bit 0 of CNTCT */
-        cntcr = ioremap(0xe6080000, PAGE_SIZE);
-        iowrite32(1, cntcr);
-        iounmap(cntcr);
+        /* The arch timer frequency equals EXTAL / 2 */
+        freq = extal_mhz * (1000000 / 2);
+
+        /* Remap "armgcnt address map" space */
+        base = ioremap(0xe6080000, PAGE_SIZE);
+
+        /* Update registers with correct frequency */
+        iowrite32(freq, base + CNTFID0);
+        asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
+
+        /* make sure arch timer is started by setting bit 0 of CNTCR */
+        iowrite32(1, base + CNTCR);
+        iounmap(base);
+#endif /* CONFIG_ARM_ARCH_TIMER */
 
         shmobile_timer_init();
 }
 
+void __init r8a7790_init_delay(void)
+{
+#ifndef CONFIG_ARM_ARCH_TIMER
+        shmobile_setup_delay(1300, 2, 4); /* Cortex-A15 @ 1300MHz */
+#endif
+}
+
 #ifdef CONFIG_USE_OF
 
 static const char *r8a7790_boards_compat_dt[] __initdata = {
@@ -183,6 +276,7 @@ static const char *r8a7790_boards_compat_dt[] __initdata = {
 };
 
 DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)")
+        .init_early     = r8a7790_init_delay,
         .init_time      = r8a7790_timer_init,
         .dt_compat      = r8a7790_boards_compat_dt,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c
index 1fcd607d64ad..78e84c582453 100644
--- a/arch/arm/mach-shmobile/smp-emev2.c
+++ b/arch/arm/mach-shmobile/smp-emev2.c
@@ -29,6 +29,8 @@
 #include <asm/smp_scu.h>
 
 #define EMEV2_SCU_BASE 0x1e000000
+#define EMEV2_SMU_BASE 0xe0110000
+#define SMU_GENERAL_REG0 0x7c0
 
 static int emev2_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
@@ -38,13 +40,18 @@ static int emev2_boot_secondary(unsigned int cpu, struct task_struct *idle)
 
 static void __init emev2_smp_prepare_cpus(unsigned int max_cpus)
 {
+        void __iomem *smu;
+
         /* setup EMEV2 specific SCU base, enable */
         shmobile_scu_base = ioremap(EMEV2_SCU_BASE, PAGE_SIZE);
         scu_enable(shmobile_scu_base);
 
         /* Tell ROM loader about our vector (in headsmp-scu.S, headsmp.S) */
-        emev2_clock_init(); /* need ioremapped SMU */
-        emev2_set_boot_vector(__pa(shmobile_boot_vector));
+        smu = ioremap(EMEV2_SMU_BASE, PAGE_SIZE);
+        if (smu) {
+                iowrite32(__pa(shmobile_boot_vector), smu + SMU_GENERAL_REG0);
+                iounmap(smu);
+        }
         shmobile_boot_fn = virt_to_phys(shmobile_boot_scu);
         shmobile_boot_arg = (unsigned long)shmobile_scu_base;
 
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 5b045e302b43..3ab2f65f8a50 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -10,3 +10,5 @@ config ARCH_SUNXI
         select SPARSE_IRQ
         select SUN4I_TIMER
         select PINCTRL_SUNXI
+        select ARM_GIC
+        select HAVE_SMP
diff --git a/arch/arm/mach-sunxi/Makefile.boot b/arch/arm/mach-sunxi/Makefile.boot
deleted file mode 100644
index 46d4cf0841c0..000000000000
--- a/arch/arm/mach-sunxi/Makefile.boot
+++ /dev/null
@@ -1 +0,0 @@
-zreladdr-$(CONFIG_ARCH_SUNXI)   += 0x40008000
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index 38a3c55527c8..e79fb3469341 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -27,10 +27,19 @@
 #include <asm/system_misc.h>
 
 #define SUN4I_WATCHDOG_CTRL_REG         0x00
-#define SUN4I_WATCHDOG_CTRL_RESTART             (1 << 0)
+#define SUN4I_WATCHDOG_CTRL_RESTART             BIT(0)
 #define SUN4I_WATCHDOG_MODE_REG         0x04
-#define SUN4I_WATCHDOG_MODE_ENABLE              (1 << 0)
-#define SUN4I_WATCHDOG_MODE_RESET_ENABLE        (1 << 1)
+#define SUN4I_WATCHDOG_MODE_ENABLE              BIT(0)
+#define SUN4I_WATCHDOG_MODE_RESET_ENABLE        BIT(1)
+
+#define SUN6I_WATCHDOG1_IRQ_REG         0x00
+#define SUN6I_WATCHDOG1_CTRL_REG        0x10
+#define SUN6I_WATCHDOG1_CTRL_RESTART            BIT(0)
+#define SUN6I_WATCHDOG1_CONFIG_REG      0x14
+#define SUN6I_WATCHDOG1_CONFIG_RESTART          BIT(0)
+#define SUN6I_WATCHDOG1_CONFIG_IRQ              BIT(1)
+#define SUN6I_WATCHDOG1_MODE_REG        0x18
+#define SUN6I_WATCHDOG1_MODE_ENABLE             BIT(0)
 
 static void __iomem *wdt_base;
 
@@ -56,8 +65,36 @@ static void sun4i_restart(enum reboot_mode mode, const char *cmd)
         }
 }
 
+static void sun6i_restart(enum reboot_mode mode, const char *cmd)
+{
+        if (!wdt_base)
+                return;
+
+        /* Disable interrupts */
+        writel(0, wdt_base + SUN6I_WATCHDOG1_IRQ_REG);
+
+        /* We want to disable the IRQ and just reset the whole system */
+        writel(SUN6I_WATCHDOG1_CONFIG_RESTART,
+                wdt_base + SUN6I_WATCHDOG1_CONFIG_REG);
+
+        /* Enable timer. The default and lowest interval value is 0.5s */
+        writel(SUN6I_WATCHDOG1_MODE_ENABLE,
+                wdt_base + SUN6I_WATCHDOG1_MODE_REG);
+
+        /* Restart the watchdog. */
+        writel(SUN6I_WATCHDOG1_CTRL_RESTART,
+                wdt_base + SUN6I_WATCHDOG1_CTRL_REG);
+
+        while (1) {
+                mdelay(5);
+                writel(SUN6I_WATCHDOG1_MODE_ENABLE,
+                        wdt_base + SUN6I_WATCHDOG1_MODE_REG);
+        }
+}
+
 static struct of_device_id sunxi_restart_ids[] = {
         { .compatible = "allwinner,sun4i-wdt", .data = sun4i_restart },
+        { .compatible = "allwinner,sun6i-wdt", .data = sun6i_restart },
         { /*sentinel*/ }
 };
 
@@ -96,6 +133,8 @@ static const char * const sunxi_board_dt_compat[] = {
         "allwinner,sun4i-a10",
         "allwinner,sun5i-a10s",
         "allwinner,sun5i-a13",
+        "allwinner,sun6i-a31",
+        "allwinner,sun7i-a20",
         NULL,
 };
 
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 59925cc896fb..67a76f2dfb9f 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -2,18 +2,25 @@ config ARCH_TEGRA
         bool "NVIDIA Tegra" if ARCH_MULTI_V7
         select ARCH_HAS_CPUFREQ
         select ARCH_REQUIRE_GPIOLIB
+        select ARM_GIC
         select CLKDEV_LOOKUP
         select CLKSRC_MMIO
         select CLKSRC_OF
         select COMMON_CLK
+        select CPU_V7
         select GENERIC_CLOCKEVENTS
         select HAVE_ARM_SCU if SMP
         select HAVE_ARM_TWD if SMP
         select HAVE_CLK
         select HAVE_SMP
         select MIGHT_HAVE_CACHE_L2X0
+        select MIGHT_HAVE_PCI
+        select PINCTRL
         select SOC_BUS
         select SPARSE_IRQ
+        select USB_ARCH_HAS_EHCI if USB_SUPPORT
+        select USB_ULPI if USB_PHY
+        select USB_ULPI_VIEWPORT if USB_PHY
         select USE_OF
         help
           This enables support for NVIDIA Tegra based systems.
@@ -27,15 +34,9 @@ config ARCH_TEGRA_2x_SOC
         select ARM_ERRATA_720789
         select ARM_ERRATA_754327 if SMP
         select ARM_ERRATA_764369 if SMP
-        select ARM_GIC
-        select CPU_V7
-        select PINCTRL
         select PINCTRL_TEGRA20
         select PL310_ERRATA_727915 if CACHE_L2X0
         select PL310_ERRATA_769419 if CACHE_L2X0
-        select USB_ARCH_HAS_EHCI if USB_SUPPORT
-        select USB_ULPI if USB_PHY
-        select USB_ULPI_VIEWPORT if USB_PHY
         help
           Support for NVIDIA Tegra AP20 and T20 processors, based on the
           ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
@@ -44,14 +45,8 @@ config ARCH_TEGRA_3x_SOC
         bool "Enable support for Tegra30 family"
         select ARM_ERRATA_754322
         select ARM_ERRATA_764369 if SMP
-        select ARM_GIC
-        select CPU_V7
-        select PINCTRL
         select PINCTRL_TEGRA30
         select PL310_ERRATA_769419 if CACHE_L2X0
-        select USB_ARCH_HAS_EHCI if USB_SUPPORT
-        select USB_ULPI if USB_PHY
-        select USB_ULPI_VIEWPORT if USB_PHY
         help
           Support for NVIDIA Tegra T30 processor family, based on the
           ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
@@ -59,20 +54,13 @@ config ARCH_TEGRA_3x_SOC
 config ARCH_TEGRA_114_SOC
         bool "Enable support for Tegra114 family"
         select HAVE_ARM_ARCH_TIMER
-        select ARM_GIC
+        select ARM_ERRATA_798181
         select ARM_L1_CACHE_SHIFT_6
-        select CPU_V7
-        select PINCTRL
         select PINCTRL_TEGRA114
         help
           Support for NVIDIA Tegra T114 processor family, based on the
           ARM CortexA15MP CPU
 
-config TEGRA_PCI
-        bool "PCI Express support"
-        depends on ARCH_TEGRA_2x_SOC
-        select PCI
-
 config TEGRA_AHB
         bool "Enable AHB driver for NVIDIA Tegra SoCs"
         default y
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 98b184efc110..e7e5f45c6558 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -17,24 +17,24 @@ obj-$(CONFIG_CPU_IDLE)			+= cpuidle.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra20_speedo.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_emc.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += sleep-tegra20.o
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += pm-tegra20.o
 ifeq ($(CONFIG_CPU_IDLE),y)
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += cpuidle-tegra20.o
 endif
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += tegra30_speedo.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += sleep-tegra30.o
+obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += pm-tegra30.o
 ifeq ($(CONFIG_CPU_IDLE),y)
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += cpuidle-tegra30.o
 endif
 obj-$(CONFIG_SMP)                       += platsmp.o headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
-obj-$(CONFIG_TEGRA_PCI)                 += pcie.o
 
 obj-$(CONFIG_ARCH_TEGRA_114_SOC)        += tegra114_speedo.o
 obj-$(CONFIG_ARCH_TEGRA_114_SOC)        += sleep-tegra30.o
+obj-$(CONFIG_ARCH_TEGRA_114_SOC)        += pm-tegra30.o
 ifeq ($(CONFIG_CPU_IDLE),y)
 obj-$(CONFIG_ARCH_TEGRA_114_SOC)        += cpuidle-tegra114.o
 endif
 
-obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += board-harmony-pcie.o
-
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += board-paz00.o
diff --git a/arch/arm/mach-tegra/board-harmony-pcie.c b/arch/arm/mach-tegra/board-harmony-pcie.c
deleted file mode 100644
index 035b240b9e15..000000000000
--- a/arch/arm/mach-tegra/board-harmony-pcie.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * arch/arm/mach-tegra/board-harmony-pcie.c
- *
- * Copyright (C) 2010 CompuLab, Ltd.
- * Mike Rapoport <mike@compulab.co.il>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/gpio.h>
-#include <linux/err.h>
-#include <linux/of_gpio.h>
-#include <linux/regulator/consumer.h>
-
-#include <asm/mach-types.h>
-
-#include "board.h"
-
-#ifdef CONFIG_TEGRA_PCI
-
-int __init harmony_pcie_init(void)
-{
-        struct device_node *np;
-        int en_vdd_1v05;
-        struct regulator *regulator = NULL;
-        int err;
-
-        np = of_find_node_by_path("/regulators/regulator@3");
-        if (!np) {
-                pr_err("%s: of_find_node_by_path failed\n", __func__);
-                return -ENODEV;
-        }
-
-        en_vdd_1v05 = of_get_named_gpio(np, "gpio", 0);
-        if (en_vdd_1v05 < 0) {
-                pr_err("%s: of_get_named_gpio failed: %d\n", __func__,
-                       en_vdd_1v05);
-                return en_vdd_1v05;
-        }
-
-        err = gpio_request(en_vdd_1v05, "EN_VDD_1V05");
-        if (err) {
-                pr_err("%s: gpio_request failed: %d\n", __func__, err);
-                return err;
-        }
-
-        gpio_direction_output(en_vdd_1v05, 1);
-
-        regulator = regulator_get(NULL, "vdd_ldo0,vddio_pex_clk");
-        if (IS_ERR(regulator)) {
-                err = PTR_ERR(regulator);
-                pr_err("%s: regulator_get failed: %d\n", __func__, err);
-                goto err_reg;
-        }
-
-        err = regulator_enable(regulator);
-        if (err) {
-                pr_err("%s: regulator_enable failed: %d\n", __func__, err);
-                goto err_en;
-        }
-
-        err = tegra_pcie_init(true, true);
-        if (err) {
-                pr_err("%s: tegra_pcie_init failed: %d\n", __func__, err);
-                goto err_pcie;
-        }
-
-        return 0;
-
-err_pcie:
-        regulator_disable(regulator);
-err_en:
-        regulator_put(regulator);
-err_reg:
-        gpio_free(en_vdd_1v05);
-
-        return err;
-}
-
-#endif
diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h
index 9a6659fe2dc2..db6810dc0b3d 100644
--- a/arch/arm/mach-tegra/board.h
+++ b/arch/arm/mach-tegra/board.h
@@ -31,7 +31,6 @@ void __init tegra_init_early(void);
 void __init tegra_map_common_io(void);
 void __init tegra_init_irq(void);
 void __init tegra_dt_init_irq(void);
-int __init tegra_pcie_init(bool init_port0, bool init_port1);
 
 void tegra_init_late(void);
 
@@ -48,13 +47,6 @@ int __init tegra_powergate_debugfs_init(void);
 static inline int tegra_powergate_debugfs_init(void) { return 0; }
 #endif
 
-int __init harmony_regulator_init(void);
-#ifdef CONFIG_TEGRA_PCI
-int __init harmony_pcie_init(void);
-#else
-static inline int harmony_pcie_init(void) { return 0; }
-#endif
-
 void __init tegra_paz00_wifikill_init(void);
 
 #endif
diff --git a/arch/arm/mach-tegra/common.h b/arch/arm/mach-tegra/common.h
index 32f8eb3fe344..5900cc44f780 100644
--- a/arch/arm/mach-tegra/common.h
+++ b/arch/arm/mach-tegra/common.h
@@ -2,4 +2,3 @@ extern struct smp_operations tegra_smp_ops;
 
 extern int tegra_cpu_kill(unsigned int cpu);
 extern void tegra_cpu_die(unsigned int cpu);
-extern int tegra_cpu_disable(unsigned int cpu);
diff --git a/arch/arm/mach-tegra/cpuidle-tegra114.c b/arch/arm/mach-tegra/cpuidle-tegra114.c
index 1d1c6023f4a2..e0b87300243d 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra114.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra114.c
@@ -17,15 +17,64 @@
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/cpuidle.h>
+#include <linux/cpu_pm.h>
+#include <linux/clockchips.h>
 
 #include <asm/cpuidle.h>
+#include <asm/suspend.h>
+#include <asm/smp_plat.h>
+
+#include "pm.h"
+#include "sleep.h"
+
+#ifdef CONFIG_PM_SLEEP
+#define TEGRA114_MAX_STATES 2
+#else
+#define TEGRA114_MAX_STATES 1
+#endif
+
+#ifdef CONFIG_PM_SLEEP
+static int tegra114_idle_power_down(struct cpuidle_device *dev,
+                                    struct cpuidle_driver *drv,
+                                    int index)
+{
+        local_fiq_disable();
+
+        tegra_set_cpu_in_lp2();
+        cpu_pm_enter();
+
+        clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
+
+        cpu_suspend(0, tegra30_sleep_cpu_secondary_finish);
+
+        clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
+
+        cpu_pm_exit();
+        tegra_clear_cpu_in_lp2();
+
+        local_fiq_enable();
+
+        return index;
+}
+#endif
 
 static struct cpuidle_driver tegra_idle_driver = {
         .name = "tegra_idle",
         .owner = THIS_MODULE,
-        .state_count = 1,
+        .state_count = TEGRA114_MAX_STATES,
         .states = {
                 [0] = ARM_CPUIDLE_WFI_STATE_PWR(600),
+#ifdef CONFIG_PM_SLEEP
+                [1] = {
+                        .enter                  = tegra114_idle_power_down,
+                        .exit_latency           = 500,
+                        .target_residency       = 1000,
+                        .power_usage            = 0,
+                        .flags                  = CPUIDLE_FLAG_TIME_VALID,
+                        .name                   = "powered-down",
+                        .desc                   = "CPU power gated",
+                },
+#endif
         },
 };
 
diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c
index 706aa4215c36..b82dcaee2ef4 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra20.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra20.c
@@ -211,6 +211,18 @@ static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev,
 }
 #endif
 
+/*
+ * Tegra20 HW appears to have a bug such that PCIe device interrupts, whether
+ * they are legacy IRQs or MSI, are lost when LP2 is enabled. To work around
+ * this, simply disable LP2 if the PCI driver and DT node are both enabled.
+ */
+void tegra20_cpuidle_pcie_irqs_in_use(void)
+{
+        pr_info_once(
+                "Disabling cpuidle LP2 state, since PCIe IRQs are in use\n");
+        tegra_idle_driver.states[1].disabled = true;
+}
+
 int __init tegra20_cpuidle_init(void)
 {
         return cpuidle_register(&tegra_idle_driver, cpu_possible_mask);
diff --git a/arch/arm/mach-tegra/cpuidle.c b/arch/arm/mach-tegra/cpuidle.c
index e85973cef037..0961dfcf83a4 100644
--- a/arch/arm/mach-tegra/cpuidle.c
+++ b/arch/arm/mach-tegra/cpuidle.c
@@ -44,3 +44,13 @@ void __init tegra_cpuidle_init(void)
                 break;
         }
 }
+
+void tegra_cpuidle_pcie_irqs_in_use(void)
+{
+        switch (tegra_chip_id) {
+        case TEGRA20:
+                if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
+                        tegra20_cpuidle_pcie_irqs_in_use();
+                break;
+        }
+}
diff --git a/arch/arm/mach-tegra/cpuidle.h b/arch/arm/mach-tegra/cpuidle.h
index 9ec2c1ab0fa4..c017dab60ffa 100644
--- a/arch/arm/mach-tegra/cpuidle.h
+++ b/arch/arm/mach-tegra/cpuidle.h
@@ -19,6 +19,7 @@
 
 #ifdef CONFIG_CPU_IDLE
 int tegra20_cpuidle_init(void);
+void tegra20_cpuidle_pcie_irqs_in_use(void);
 int tegra30_cpuidle_init(void);
 int tegra114_cpuidle_init(void);
 void tegra_cpuidle_init(void);
diff --git a/arch/arm/mach-tegra/flowctrl.c b/arch/arm/mach-tegra/flowctrl.c
index b477ef310dcd..5348543382bf 100644
--- a/arch/arm/mach-tegra/flowctrl.c
+++ b/arch/arm/mach-tegra/flowctrl.c
@@ -86,6 +86,7 @@ void flowctrl_cpu_suspend_enter(unsigned int cpuid)
                 reg |= TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 << cpuid;
                 break;
         case TEGRA30:
+        case TEGRA114:
                 /* clear wfe bitmap */
                 reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;
                 /* clear wfi bitmap */
@@ -123,6 +124,7 @@ void flowctrl_cpu_suspend_exit(unsigned int cpuid)
                 reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP;
                 break;
         case TEGRA30:
+        case TEGRA114:
                 /* clear wfe bitmap */
                 reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;
                 /* clear wfi bitmap */
diff --git a/arch/arm/mach-tegra/flowctrl.h b/arch/arm/mach-tegra/flowctrl.h
index 7a29bae799a7..c89aac60a143 100644
--- a/arch/arm/mach-tegra/flowctrl.h
+++ b/arch/arm/mach-tegra/flowctrl.h
@@ -28,9 +28,18 @@
 #define FLOW_CTRL_SCLK_RESUME           (1 << 27)
 #define FLOW_CTRL_HALT_CPU_IRQ          (1 << 10)
 #define FLOW_CTRL_HALT_CPU_FIQ          (1 << 8)
+#define FLOW_CTRL_HALT_LIC_IRQ          (1 << 11)
+#define FLOW_CTRL_HALT_LIC_FIQ          (1 << 10)
+#define FLOW_CTRL_HALT_GIC_IRQ          (1 << 9)
+#define FLOW_CTRL_HALT_GIC_FIQ          (1 << 8)
 #define FLOW_CTRL_CPU0_CSR              0x8
 #define FLOW_CTRL_CSR_INTR_FLAG         (1 << 15)
 #define FLOW_CTRL_CSR_EVENT_FLAG        (1 << 14)
+#define FLOW_CTRL_CSR_ENABLE_EXT_CRAIL  (1 << 13)
+#define FLOW_CTRL_CSR_ENABLE_EXT_NCPU   (1 << 12)
+#define FLOW_CTRL_CSR_ENABLE_EXT_MASK ( \
+                FLOW_CTRL_CSR_ENABLE_EXT_NCPU | \
+                FLOW_CTRL_CSR_ENABLE_EXT_CRAIL)
 #define FLOW_CTRL_CSR_ENABLE            (1 << 0)
 #define FLOW_CTRL_HALT_CPU1_EVENTS      0x14
 #define FLOW_CTRL_CPU1_CSR              0x18
diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S
index 045c16f2dd51..2072e7322c39 100644
--- a/arch/arm/mach-tegra/headsmp.S
+++ b/arch/arm/mach-tegra/headsmp.S
@@ -6,6 +6,7 @@
         .section ".text.head", "ax"
 
 ENTRY(tegra_secondary_startup)
-        bl      v7_invalidate_l1
+        check_cpu_part_num 0xc09, r8, r9
+        bleq    v7_invalidate_l1
         b       secondary_startup
 ENDPROC(tegra_secondary_startup)
diff --git a/arch/arm/mach-tegra/hotplug.c b/arch/arm/mach-tegra/hotplug.c
index a52c10e0a857..04de2e860923 100644
--- a/arch/arm/mach-tegra/hotplug.c
+++ b/arch/arm/mach-tegra/hotplug.c
@@ -37,7 +37,7 @@ int tegra_cpu_kill(unsigned cpu)
 void __ref tegra_cpu_die(unsigned int cpu)
 {
         /* Clean L1 data cache */
-        tegra_disable_clean_inv_dcache();
+        tegra_disable_clean_inv_dcache(TEGRA_FLUSH_CACHE_LOUIS);
 
         /* Shut down the current CPU. */
         tegra_hotplug_shutdown();
@@ -46,17 +46,6 @@ void __ref tegra_cpu_die(unsigned int cpu)
         BUG();
 }
 
-int tegra_cpu_disable(unsigned int cpu)
-{
-        switch (tegra_chip_id) {
-        case TEGRA20:
-        case TEGRA30:
-                return cpu == 0 ? -EPERM : 0;
-        default:
-                return 0;
-        }
-}
-
 void __init tegra_hotplug_init(void)
 {
         if (!IS_ENABLED(CONFIG_HOTPLUG_CPU))
diff --git a/arch/arm/mach-tegra/iomap.h b/arch/arm/mach-tegra/iomap.h
index 399fbca27102..3f5fa0749bde 100644
--- a/arch/arm/mach-tegra/iomap.h
+++ b/arch/arm/mach-tegra/iomap.h
@@ -24,6 +24,8 @@
 #define TEGRA_IRAM_BASE                 0x40000000
 #define TEGRA_IRAM_SIZE                 SZ_256K
 
+#define TEGRA_IRAM_CODE_AREA            (TEGRA_IRAM_BASE + SZ_4K)
+
 #define TEGRA_HOST1X_BASE               0x50000000
 #define TEGRA_HOST1X_SIZE               0x24000
 
@@ -237,6 +239,12 @@
 #define TEGRA_KFUSE_BASE                0x7000FC00
 #define TEGRA_KFUSE_SIZE                SZ_1K
 
+#define TEGRA_EMC0_BASE                 0x7001A000
+#define TEGRA_EMC0_SIZE                 SZ_2K
+
+#define TEGRA_EMC1_BASE                 0x7001A800
+#define TEGRA_EMC1_SIZE                 SZ_2K
+
 #define TEGRA_CSITE_BASE                0x70040000
 #define TEGRA_CSITE_SIZE                SZ_256K
 
@@ -278,9 +286,6 @@
 #define IO_APB_VIRT     IOMEM(0xFE300000)
 #define IO_APB_SIZE     SZ_1M
 
-#define TEGRA_PCIE_BASE         0x80000000
-#define TEGRA_PCIE_IO_BASE      (TEGRA_PCIE_BASE + SZ_4M)
-
 #define IO_TO_VIRT_BETWEEN(p, st, sz)   ((p) >= (st) && (p) < ((st) + (sz)))
 #define IO_TO_VIRT_XLATE(p, pst, vst)   (((p) - (pst) + (vst)))
 
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index 0de4eed1493d..1a74d562dca1 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -18,10 +18,12 @@
  */
 
 #include <linux/kernel.h>
+#include <linux/cpu_pm.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/io.h>
 #include <linux/of.h>
+#include <linux/of_address.h>
 #include <linux/irqchip/arm-gic.h>
 #include <linux/syscore_ops.h>
 
@@ -65,6 +67,7 @@ static u32 cpu_ier[TEGRA_MAX_NUM_ICTLRS];
 static u32 cpu_iep[TEGRA_MAX_NUM_ICTLRS];
 
 static u32 ictlr_wake_mask[TEGRA_MAX_NUM_ICTLRS];
+static void __iomem *tegra_gic_cpu_base;
 #endif
 
 bool tegra_pending_sgi(void)
@@ -213,8 +216,43 @@ int tegra_legacy_irq_syscore_init(void)
 
         return 0;
 }
+
+static int tegra_gic_notifier(struct notifier_block *self,
+                              unsigned long cmd, void *v)
+{
+        switch (cmd) {
+        case CPU_PM_ENTER:
+                writel_relaxed(0x1E0, tegra_gic_cpu_base + GIC_CPU_CTRL);
+                break;
+        }
+
+        return NOTIFY_OK;
+}
+
+static struct notifier_block tegra_gic_notifier_block = {
+        .notifier_call = tegra_gic_notifier,
+};
+
+static const struct of_device_id tegra114_dt_gic_match[] __initconst = {
+        { .compatible = "arm,cortex-a15-gic" },
+        { }
+};
+
+static void tegra114_gic_cpu_pm_registration(void)
+{
+        struct device_node *dn;
+
+        dn = of_find_matching_node(NULL, tegra114_dt_gic_match);
+        if (!dn)
+                return;
+
+        tegra_gic_cpu_base = of_iomap(dn, 1);
+
+        cpu_pm_register_notifier(&tegra_gic_notifier_block);
+}
 #else
 #define tegra_set_wake NULL
+static void tegra114_gic_cpu_pm_registration(void) { }
 #endif
 
 void __init tegra_init_irq(void)
@@ -252,4 +290,6 @@ void __init tegra_init_irq(void)
         if (!of_have_populated_dt())
                 gic_init(0, 29, distbase,
                         IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100));
+
+        tegra114_gic_cpu_pm_registration();
 }
diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
deleted file mode 100644
index 46144a19a7e7..000000000000
--- a/arch/arm/mach-tegra/pcie.c
+++ /dev/null
@@ -1,886 +0,0 @@
-/*
- * arch/arm/mach-tegra/pci.c
- *
- * PCIe host controller driver for TEGRA(2) SOCs
- *
- * Copyright (c) 2010, CompuLab, Ltd.
- * Author: Mike Rapoport <mike@compulab.co.il>
- *
- * Based on NVIDIA PCIe driver
- * Copyright (c) 2008-2009, NVIDIA Corporation.
- *
- * Bits taken from arch/arm/mach-dove/pcie.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
- */
-
-#include <linux/kernel.h>
-#include <linux/pci.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/export.h>
-#include <linux/clk/tegra.h>
-#include <linux/tegra-powergate.h>
-
-#include <asm/sizes.h>
-#include <asm/mach/pci.h>
-
-#include "board.h"
-#include "iomap.h"
-
-/* Hack - need to parse this from DT */
-#define INT_PCIE_INTR 130
-
-/* register definitions */
-#define AFI_OFFSET      0x3800
-#define PADS_OFFSET     0x3000
-#define RP0_OFFSET      0x0000
-#define RP1_OFFSET      0x1000
-
-#define AFI_AXI_BAR0_SZ 0x00
-#define AFI_AXI_BAR1_SZ 0x04
-#define AFI_AXI_BAR2_SZ 0x08
-#define AFI_AXI_BAR3_SZ 0x0c
-#define AFI_AXI_BAR4_SZ 0x10
-#define AFI_AXI_BAR5_SZ 0x14
-
-#define AFI_AXI_BAR0_START      0x18
-#define AFI_AXI_BAR1_START      0x1c
-#define AFI_AXI_BAR2_START      0x20
-#define AFI_AXI_BAR3_START      0x24
-#define AFI_AXI_BAR4_START      0x28
-#define AFI_AXI_BAR5_START      0x2c
-
-#define AFI_FPCI_BAR0   0x30
-#define AFI_FPCI_BAR1   0x34
-#define AFI_FPCI_BAR2   0x38
-#define AFI_FPCI_BAR3   0x3c
-#define AFI_FPCI_BAR4   0x40
-#define AFI_FPCI_BAR5   0x44
-
-#define AFI_CACHE_BAR0_SZ       0x48
-#define AFI_CACHE_BAR0_ST       0x4c
-#define AFI_CACHE_BAR1_SZ       0x50
-#define AFI_CACHE_BAR1_ST       0x54
-
-#define AFI_MSI_BAR_SZ          0x60
-#define AFI_MSI_FPCI_BAR_ST     0x64
-#define AFI_MSI_AXI_BAR_ST      0x68
-
-#define AFI_CONFIGURATION               0xac
-#define  AFI_CONFIGURATION_EN_FPCI      (1 << 0)
-
-#define AFI_FPCI_ERROR_MASKS    0xb0
-
-#define AFI_INTR_MASK           0xb4
-#define  AFI_INTR_MASK_INT_MASK (1 << 0)
-#define  AFI_INTR_MASK_MSI_MASK (1 << 8)
-
-#define AFI_INTR_CODE           0xb8
-#define  AFI_INTR_CODE_MASK     0xf
-#define  AFI_INTR_MASTER_ABORT  4
-#define  AFI_INTR_LEGACY        6
-
-#define AFI_INTR_SIGNATURE      0xbc
-#define AFI_SM_INTR_ENABLE      0xc4
-
-#define AFI_AFI_INTR_ENABLE             0xc8
-#define  AFI_INTR_EN_INI_SLVERR         (1 << 0)
-#define  AFI_INTR_EN_INI_DECERR         (1 << 1)
-#define  AFI_INTR_EN_TGT_SLVERR         (1 << 2)
-#define  AFI_INTR_EN_TGT_DECERR         (1 << 3)
-#define  AFI_INTR_EN_TGT_WRERR          (1 << 4)
-#define  AFI_INTR_EN_DFPCI_DECERR       (1 << 5)
-#define  AFI_INTR_EN_AXI_DECERR         (1 << 6)
-#define  AFI_INTR_EN_FPCI_TIMEOUT       (1 << 7)
-
-#define AFI_PCIE_CONFIG                                 0x0f8
-#define  AFI_PCIE_CONFIG_PCIEC0_DISABLE_DEVICE          (1 << 1)
-#define  AFI_PCIE_CONFIG_PCIEC1_DISABLE_DEVICE          (1 << 2)
-#define  AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK       (0xf << 20)
-#define  AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE     (0x0 << 20)
-#define  AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL       (0x1 << 20)
-
-#define AFI_FUSE                        0x104
-#define  AFI_FUSE_PCIE_T0_GEN2_DIS      (1 << 2)
-
-#define AFI_PEX0_CTRL                   0x110
-#define AFI_PEX1_CTRL                   0x118
-#define  AFI_PEX_CTRL_RST               (1 << 0)
-#define  AFI_PEX_CTRL_REFCLK_EN         (1 << 3)
-
-#define RP_VEND_XP      0x00000F00
-#define  RP_VEND_XP_DL_UP       (1 << 30)
-
-#define RP_LINK_CONTROL_STATUS                  0x00000090
-#define  RP_LINK_CONTROL_STATUS_LINKSTAT_MASK   0x3fff0000
-
-#define PADS_CTL_SEL            0x0000009C
-
-#define PADS_CTL                0x000000A0
-#define  PADS_CTL_IDDQ_1L       (1 << 0)
-#define  PADS_CTL_TX_DATA_EN_1L (1 << 6)
-#define  PADS_CTL_RX_DATA_EN_1L (1 << 10)
-
-#define PADS_PLL_CTL                            0x000000B8
-#define  PADS_PLL_CTL_RST_B4SM                  (1 << 1)
-#define  PADS_PLL_CTL_LOCKDET                   (1 << 8)
-#define  PADS_PLL_CTL_REFCLK_MASK               (0x3 << 16)
-#define  PADS_PLL_CTL_REFCLK_INTERNAL_CML       (0 << 16)
-#define  PADS_PLL_CTL_REFCLK_INTERNAL_CMOS      (1 << 16)
-#define  PADS_PLL_CTL_REFCLK_EXTERNAL           (2 << 16)
-#define  PADS_PLL_CTL_TXCLKREF_MASK             (0x1 << 20)
-#define  PADS_PLL_CTL_TXCLKREF_DIV10            (0 << 20)
-#define  PADS_PLL_CTL_TXCLKREF_DIV5             (1 << 20)
-
-/* PMC access is required for PCIE xclk (un)clamping */
-#define PMC_SCRATCH42           0x144
-#define PMC_SCRATCH42_PCX_CLAMP (1 << 0)
-
-static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
-
-#define pmc_writel(value, reg) \
-        __raw_writel(value, reg_pmc_base + (reg))
-#define pmc_readl(reg) \
-        __raw_readl(reg_pmc_base + (reg))
-
-/*
- * Tegra2 defines 1GB in the AXI address map for PCIe.
- *
- * That address space is split into different regions, with sizes and
- * offsets as follows:
- *
- * 0x80000000 - 0x80003fff - PCI controller registers
- * 0x80004000 - 0x80103fff - PCI configuration space
- * 0x80104000 - 0x80203fff - PCI extended configuration space
- * 0x80203fff - 0x803fffff - unused
- * 0x80400000 - 0x8040ffff - downstream IO
- * 0x80410000 - 0x8fffffff - unused
- * 0x90000000 - 0x9fffffff - non-prefetchable memory
- * 0xa0000000 - 0xbfffffff - prefetchable memory
- */
-#define PCIE_REGS_SZ            SZ_16K
-#define PCIE_CFG_OFF            PCIE_REGS_SZ
-#define PCIE_CFG_SZ             SZ_1M
-#define PCIE_EXT_CFG_OFF        (PCIE_CFG_SZ + PCIE_CFG_OFF)
-#define PCIE_EXT_CFG_SZ         SZ_1M
-#define PCIE_IOMAP_SZ           (PCIE_REGS_SZ + PCIE_CFG_SZ + PCIE_EXT_CFG_SZ)
-
-#define MEM_BASE_0              (TEGRA_PCIE_BASE + SZ_256M)
-#define MEM_SIZE_0              SZ_128M
-#define MEM_BASE_1              (MEM_BASE_0 + MEM_SIZE_0)
-#define MEM_SIZE_1              SZ_128M
-#define PREFETCH_MEM_BASE_0     (MEM_BASE_1 + MEM_SIZE_1)
-#define PREFETCH_MEM_SIZE_0     SZ_128M
-#define PREFETCH_MEM_BASE_1     (PREFETCH_MEM_BASE_0 + PREFETCH_MEM_SIZE_0)
-#define PREFETCH_MEM_SIZE_1     SZ_128M
-
-#define  PCIE_CONF_BUS(b)       ((b) << 16)
-#define  PCIE_CONF_DEV(d)       ((d) << 11)
-#define  PCIE_CONF_FUNC(f)      ((f) << 8)
-#define  PCIE_CONF_REG(r)       \
-        (((r) & ~0x3) | (((r) < 256) ? PCIE_CFG_OFF : PCIE_EXT_CFG_OFF))
-
-struct tegra_pcie_port {
-        int                     index;
-        u8                      root_bus_nr;
-        void __iomem            *base;
-
-        bool                    link_up;
-
-        char                    mem_space_name[16];
-        char                    prefetch_space_name[20];
-        struct resource         res[2];
-};
-
-struct tegra_pcie_info {
-        struct tegra_pcie_port  port[2];
-        int                     num_ports;
-
-        void __iomem            *regs;
-        struct resource         res_mmio;
-
-        struct clk              *pex_clk;
-        struct clk              *afi_clk;
-        struct clk              *pcie_xclk;
-        struct clk              *pll_e;
-};
-
-static struct tegra_pcie_info tegra_pcie;
-
-static inline void afi_writel(u32 value, unsigned long offset)
-{
-        writel(value, offset + AFI_OFFSET + tegra_pcie.regs);
-}
-
-static inline u32 afi_readl(unsigned long offset)
-{
-        return readl(offset + AFI_OFFSET + tegra_pcie.regs);
-}
-
-static inline void pads_writel(u32 value, unsigned long offset)
-{
-        writel(value, offset + PADS_OFFSET + tegra_pcie.regs);
-}
-
-static inline u32 pads_readl(unsigned long offset)
-{
-        return readl(offset + PADS_OFFSET + tegra_pcie.regs);
-}
-
-static struct tegra_pcie_port *bus_to_port(int bus)
-{
-        int i;
-
-        for (i = tegra_pcie.num_ports - 1; i >= 0; i--) {
-                int rbus = tegra_pcie.port[i].root_bus_nr;
-                if (rbus != -1 && rbus == bus)
-                        break;
-        }
-
-        return i >= 0 ? tegra_pcie.port + i : NULL;
-}
-
-static int tegra_pcie_read_conf(struct pci_bus *bus, unsigned int devfn,
-                                int where, int size, u32 *val)
-{
-        struct tegra_pcie_port *pp = bus_to_port(bus->number);
-        void __iomem *addr;
-
-        if (pp) {
-                if (devfn != 0) {
-                        *val = 0xffffffff;
-                        return PCIBIOS_DEVICE_NOT_FOUND;
-                }
-
-                addr = pp->base + (where & ~0x3);
-        } else {
-                addr = tegra_pcie.regs + (PCIE_CONF_BUS(bus->number) +
-                                          PCIE_CONF_DEV(PCI_SLOT(devfn)) +
-                                          PCIE_CONF_FUNC(PCI_FUNC(devfn)) +
-                                          PCIE_CONF_REG(where));
-        }
-
-        *val = readl(addr);
-
-        if (size == 1)
-                *val = (*val >> (8 * (where & 3))) & 0xff;
-        else if (size == 2)
-                *val = (*val >> (8 * (where & 3))) & 0xffff;
-
-        return PCIBIOS_SUCCESSFUL;
-}
-
-static int tegra_pcie_write_conf(struct pci_bus *bus, unsigned int devfn,
-                                 int where, int size, u32 val)
-{
-        struct tegra_pcie_port *pp = bus_to_port(bus->number);
-        void __iomem *addr;
-
-        u32 mask;
-        u32 tmp;
-
-        if (pp) {
-                if (devfn != 0)
-                        return PCIBIOS_DEVICE_NOT_FOUND;
-
-                addr = pp->base + (where & ~0x3);
-        } else {
-                addr = tegra_pcie.regs + (PCIE_CONF_BUS(bus->number) +
-                                          PCIE_CONF_DEV(PCI_SLOT(devfn)) +
-                                          PCIE_CONF_FUNC(PCI_FUNC(devfn)) +
-                                          PCIE_CONF_REG(where));
-        }
-
-        if (size == 4) {
-                writel(val, addr);
-                return PCIBIOS_SUCCESSFUL;
-        }
-
-        if (size == 2)
-                mask = ~(0xffff << ((where & 0x3) * 8));
-        else if (size == 1)
-                mask = ~(0xff << ((where & 0x3) * 8));
-        else
-                return PCIBIOS_BAD_REGISTER_NUMBER;
-
-        tmp = readl(addr) & mask;
-        tmp |= val << ((where & 0x3) * 8);
-        writel(tmp, addr);
-
-        return PCIBIOS_SUCCESSFUL;
-}
-
-static struct pci_ops tegra_pcie_ops = {
-        .read   = tegra_pcie_read_conf,
-        .write  = tegra_pcie_write_conf,
-};
-
-static void tegra_pcie_fixup_bridge(struct pci_dev *dev)
-{
-        u16 reg;
-
-        if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE) {
-                pci_read_config_word(dev, PCI_COMMAND, &reg);
-                reg |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
-                        PCI_COMMAND_MASTER | PCI_COMMAND_SERR);
-                pci_write_config_word(dev, PCI_COMMAND, reg);
-        }
-}
-DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_fixup_bridge);
-
-/* Tegra PCIE root complex wrongly reports device class */
-static void tegra_pcie_fixup_class(struct pci_dev *dev)
-{
-        dev->class = PCI_CLASS_BRIDGE_PCI << 8;
-}
-DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0, tegra_pcie_fixup_class);
-DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1, tegra_pcie_fixup_class);
-
-/* Tegra PCIE requires relaxed ordering */
-static void tegra_pcie_relax_enable(struct pci_dev *dev)
-{
-        pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN);
-}
-DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_relax_enable);
-
-static int tegra_pcie_setup(int nr, struct pci_sys_data *sys)
-{
-        struct tegra_pcie_port *pp;
-
-        if (nr >= tegra_pcie.num_ports)
-                return 0;
-
-        pp = tegra_pcie.port + nr;
-        pp->root_bus_nr = sys->busnr;
-
-        pci_ioremap_io(nr * SZ_64K, TEGRA_PCIE_IO_BASE);
-
-        /*
-         * IORESOURCE_MEM
-         */
-        snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
-                 "PCIe %d MEM", pp->index);
-        pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
-        pp->res[0].name = pp->mem_space_name;
-        if (pp->index == 0) {
-                pp->res[0].start = MEM_BASE_0;
-                pp->res[0].end = pp->res[0].start + MEM_SIZE_0 - 1;
-        } else {
-                pp->res[0].start = MEM_BASE_1;
-                pp->res[0].end = pp->res[0].start + MEM_SIZE_1 - 1;
-        }
-        pp->res[0].flags = IORESOURCE_MEM;
-        if (request_resource(&iomem_resource, &pp->res[0]))
-                panic("Request PCIe Memory resource failed\n");
-        pci_add_resource_offset(&sys->resources, &pp->res[0], sys->mem_offset);
-
-        /*
-         * IORESOURCE_MEM | IORESOURCE_PREFETCH
-         */
-        snprintf(pp->prefetch_space_name, sizeof(pp->prefetch_space_name),
-                 "PCIe %d PREFETCH MEM", pp->index);
-        pp->prefetch_space_name[sizeof(pp->prefetch_space_name) - 1] = 0;
-        pp->res[1].name = pp->prefetch_space_name;
-        if (pp->index == 0) {
-                pp->res[1].start = PREFETCH_MEM_BASE_0;
-                pp->res[1].end = pp->res[1].start + PREFETCH_MEM_SIZE_0 - 1;
-        } else {
-                pp->res[1].start = PREFETCH_MEM_BASE_1;
-                pp->res[1].end = pp->res[1].start + PREFETCH_MEM_SIZE_1 - 1;
-        }
-        pp->res[1].flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
-        if (request_resource(&iomem_resource, &pp->res[1]))
-                panic("Request PCIe Prefetch Memory resource failed\n");
-        pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset);
-
-        return 1;
-}
-
-static int tegra_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
-        return INT_PCIE_INTR;
-}
-
-static struct pci_bus __init *tegra_pcie_scan_bus(int nr,
-                                                  struct pci_sys_data *sys)
-{
-        struct tegra_pcie_port *pp;
-
-        if (nr >= tegra_pcie.num_ports)
-                return NULL;
-
-        pp = tegra_pcie.port + nr;
-        pp->root_bus_nr = sys->busnr;
-
-        return pci_scan_root_bus(NULL, sys->busnr, &tegra_pcie_ops, sys,
-                                 &sys->resources);
-}
-
-static struct hw_pci tegra_pcie_hw __initdata = {
-        .nr_controllers = 2,
-        .setup          = tegra_pcie_setup,
-        .scan           = tegra_pcie_scan_bus,
-        .map_irq        = tegra_pcie_map_irq,
-};
-
-
-static irqreturn_t tegra_pcie_isr(int irq, void *arg)
-{
-        const char *err_msg[] = {
-                "Unknown",
-                "AXI slave error",
-                "AXI decode error",
-                "Target abort",
-                "Master abort",
-                "Invalid write",
-                "Response decoding error",
-                "AXI response decoding error",
-                "Transcation timeout",
-        };
-
-        u32 code, signature;
-
-        code = afi_readl(AFI_INTR_CODE) & AFI_INTR_CODE_MASK;
-        signature = afi_readl(AFI_INTR_SIGNATURE);
-        afi_writel(0, AFI_INTR_CODE);
-
-        if (code == AFI_INTR_LEGACY)
-                return IRQ_NONE;
-
-        if (code >= ARRAY_SIZE(err_msg))
-                code = 0;
-
-        /*
-         * do not pollute kernel log with master abort reports since they
-         * happen a lot during enumeration
-         */
-        if (code == AFI_INTR_MASTER_ABORT)
-                pr_debug("PCIE: %s, signature: %08x\n", err_msg[code], signature);
-        else
-                pr_err("PCIE: %s, signature: %08x\n", err_msg[code], signature);
-
-        return IRQ_HANDLED;
-}
-
-static void tegra_pcie_setup_translations(void)
-{
-        u32 fpci_bar;
-        u32 size;
-        u32 axi_address;
-
-        /* Bar 0: config Bar */
-        fpci_bar = ((u32)0xfdff << 16);
-        size = PCIE_CFG_SZ;
-        axi_address = TEGRA_PCIE_BASE + PCIE_CFG_OFF;
-        afi_writel(axi_address, AFI_AXI_BAR0_START);
-        afi_writel(size >> 12, AFI_AXI_BAR0_SZ);
-        afi_writel(fpci_bar, AFI_FPCI_BAR0);
-
-        /* Bar 1: extended config Bar */
-        fpci_bar = ((u32)0xfe1 << 20);
-        size = PCIE_EXT_CFG_SZ;
-        axi_address = TEGRA_PCIE_BASE + PCIE_EXT_CFG_OFF;
-        afi_writel(axi_address, AFI_AXI_BAR1_START);
-        afi_writel(size >> 12, AFI_AXI_BAR1_SZ);
-        afi_writel(fpci_bar, AFI_FPCI_BAR1);
-
-        /* Bar 2: downstream IO bar */
-        fpci_bar = ((__u32)0xfdfc << 16);
-        size = SZ_128K;
-        axi_address = TEGRA_PCIE_IO_BASE;
-        afi_writel(axi_address, AFI_AXI_BAR2_START);
-        afi_writel(size >> 12, AFI_AXI_BAR2_SZ);
-        afi_writel(fpci_bar, AFI_FPCI_BAR2);
-
-        /* Bar 3: prefetchable memory BAR */
-        fpci_bar = (((PREFETCH_MEM_BASE_0 >> 12) & 0x0fffffff) << 4) | 0x1;
-        size =  PREFETCH_MEM_SIZE_0 +  PREFETCH_MEM_SIZE_1;
-        axi_address = PREFETCH_MEM_BASE_0;
-        afi_writel(axi_address, AFI_AXI_BAR3_START);
-        afi_writel(size >> 12, AFI_AXI_BAR3_SZ);
-        afi_writel(fpci_bar, AFI_FPCI_BAR3);
-
-        /* Bar 4: non prefetchable memory BAR */
-        fpci_bar = (((MEM_BASE_0 >> 12) & 0x0FFFFFFF) << 4) | 0x1;
-        size = MEM_SIZE_0 + MEM_SIZE_1;
-        axi_address = MEM_BASE_0;
-        afi_writel(axi_address, AFI_AXI_BAR4_START);
-        afi_writel(size >> 12, AFI_AXI_BAR4_SZ);
-        afi_writel(fpci_bar, AFI_FPCI_BAR4);
-
-        /* Bar 5: NULL out the remaining BAR as it is not used */
-        fpci_bar = 0;
-        size = 0;
-        axi_address = 0;
-        afi_writel(axi_address, AFI_AXI_BAR5_START);
-        afi_writel(size >> 12, AFI_AXI_BAR5_SZ);
-        afi_writel(fpci_bar, AFI_FPCI_BAR5);
-
-        /* map all upstream transactions as uncached */
-        afi_writel(PHYS_OFFSET, AFI_CACHE_BAR0_ST);
-        afi_writel(0, AFI_CACHE_BAR0_SZ);
-        afi_writel(0, AFI_CACHE_BAR1_ST);
-        afi_writel(0, AFI_CACHE_BAR1_SZ);
-
-        /* No MSI */
-        afi_writel(0, AFI_MSI_FPCI_BAR_ST);
-        afi_writel(0, AFI_MSI_BAR_SZ);
-        afi_writel(0, AFI_MSI_AXI_BAR_ST);
-        afi_writel(0, AFI_MSI_BAR_SZ);
-}
-
-static int tegra_pcie_enable_controller(void)
-{
-        u32 val, reg;
-        int i, timeout;
-
-        /* Enable slot clock and pulse the reset signals */
-        for (i = 0, reg = AFI_PEX0_CTRL; i < 2; i++, reg += 0x8) {
-                val = afi_readl(reg) |  AFI_PEX_CTRL_REFCLK_EN;
-                afi_writel(val, reg);
-                val &= ~AFI_PEX_CTRL_RST;
-                afi_writel(val, reg);
-
-                val = afi_readl(reg) | AFI_PEX_CTRL_RST;
-                afi_writel(val, reg);
-        }
-
-        /* Enable dual controller and both ports */
-        val = afi_readl(AFI_PCIE_CONFIG);
-        val &= ~(AFI_PCIE_CONFIG_PCIEC0_DISABLE_DEVICE |
-                 AFI_PCIE_CONFIG_PCIEC1_DISABLE_DEVICE |
-                 AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK);
-        val |= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL;
-        afi_writel(val, AFI_PCIE_CONFIG);
-
-        val = afi_readl(AFI_FUSE) & ~AFI_FUSE_PCIE_T0_GEN2_DIS;
-        afi_writel(val, AFI_FUSE);
-
-        /* Initialze internal PHY, enable up to 16 PCIE lanes */
-        pads_writel(0x0, PADS_CTL_SEL);
-
-        /* override IDDQ to 1 on all 4 lanes */
-        val = pads_readl(PADS_CTL) | PADS_CTL_IDDQ_1L;
-        pads_writel(val, PADS_CTL);
-
-        /*
-         * set up PHY PLL inputs select PLLE output as refclock,
-         * set TX ref sel to div10 (not div5)
-         */
-        val = pads_readl(PADS_PLL_CTL);
-        val &= ~(PADS_PLL_CTL_REFCLK_MASK | PADS_PLL_CTL_TXCLKREF_MASK);
-        val |= (PADS_PLL_CTL_REFCLK_INTERNAL_CML | PADS_PLL_CTL_TXCLKREF_DIV10);
-        pads_writel(val, PADS_PLL_CTL);
-
-        /* take PLL out of reset  */
-        val = pads_readl(PADS_PLL_CTL) | PADS_PLL_CTL_RST_B4SM;
-        pads_writel(val, PADS_PLL_CTL);
-
-        /*
-         * Hack, set the clock voltage to the DEFAULT provided by hw folks.
-         * This doesn't exist in the documentation
-         */
-        pads_writel(0xfa5cfa5c, 0xc8);
-
-        /* Wait for the PLL to lock */
-        timeout = 300;
-        do {
-                val = pads_readl(PADS_PLL_CTL);
-                usleep_range(1000, 1000);
-                if (--timeout == 0) {
-                        pr_err("Tegra PCIe error: timeout waiting for PLL\n");
-                        return -EBUSY;
-                }
-        } while (!(val & PADS_PLL_CTL_LOCKDET));
-
-        /* turn off IDDQ override */
-        val = pads_readl(PADS_CTL) & ~PADS_CTL_IDDQ_1L;
-        pads_writel(val, PADS_CTL);
-
-        /* enable TX/RX data */
-        val = pads_readl(PADS_CTL);
-        val |= (PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L);
-        pads_writel(val, PADS_CTL);
-
-        /* Take the PCIe interface module out of reset */
-        tegra_periph_reset_deassert(tegra_pcie.pcie_xclk);
-
-        /* Finally enable PCIe */
-        val = afi_readl(AFI_CONFIGURATION) | AFI_CONFIGURATION_EN_FPCI;
-        afi_writel(val, AFI_CONFIGURATION);
-
-        val = (AFI_INTR_EN_INI_SLVERR | AFI_INTR_EN_INI_DECERR |
-               AFI_INTR_EN_TGT_SLVERR | AFI_INTR_EN_TGT_DECERR |
-               AFI_INTR_EN_TGT_WRERR | AFI_INTR_EN_DFPCI_DECERR);
-        afi_writel(val, AFI_AFI_INTR_ENABLE);
-        afi_writel(0xffffffff, AFI_SM_INTR_ENABLE);
-
-        /* FIXME: No MSI for now, only INT */
-        afi_writel(AFI_INTR_MASK_INT_MASK, AFI_INTR_MASK);
-
-        /* Disable all execptions */
-        afi_writel(0, AFI_FPCI_ERROR_MASKS);
-
-        return 0;
-}
-
-static void tegra_pcie_xclk_clamp(bool clamp)
-{
-        u32 reg;
-
-        reg = pmc_readl(PMC_SCRATCH42) & ~PMC_SCRATCH42_PCX_CLAMP;
-
-        if (clamp)
-                reg |= PMC_SCRATCH42_PCX_CLAMP;
-
-        pmc_writel(reg, PMC_SCRATCH42);
-}
-
-static void tegra_pcie_power_off(void)
-{
-        tegra_periph_reset_assert(tegra_pcie.pcie_xclk);
-        tegra_periph_reset_assert(tegra_pcie.afi_clk);
-        tegra_periph_reset_assert(tegra_pcie.pex_clk);
-
-        tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
-        tegra_pcie_xclk_clamp(true);
-}
-
-static int tegra_pcie_power_regate(void)
-{
-        int err;
-
-        tegra_pcie_power_off();
-
-        tegra_pcie_xclk_clamp(true);
-
-        tegra_periph_reset_assert(tegra_pcie.pcie_xclk);
-        tegra_periph_reset_assert(tegra_pcie.afi_clk);
-
-        err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE,
-                                                tegra_pcie.pex_clk);
-        if (err) {
-                pr_err("PCIE: powerup sequence failed: %d\n", err);
-                return err;
-        }
-
-        tegra_periph_reset_deassert(tegra_pcie.afi_clk);
-
-        tegra_pcie_xclk_clamp(false);
-
-        clk_prepare_enable(tegra_pcie.afi_clk);
-        clk_prepare_enable(tegra_pcie.pex_clk);
-        return clk_prepare_enable(tegra_pcie.pll_e);
-}
-
-static int tegra_pcie_clocks_get(void)
-{
-        int err;
-
-        tegra_pcie.pex_clk = clk_get(NULL, "pex");
-        if (IS_ERR(tegra_pcie.pex_clk))
-                return PTR_ERR(tegra_pcie.pex_clk);
-
-        tegra_pcie.afi_clk = clk_get(NULL, "afi");
-        if (IS_ERR(tegra_pcie.afi_clk)) {
-                err = PTR_ERR(tegra_pcie.afi_clk);
-                goto err_afi_clk;
-        }
-
-        tegra_pcie.pcie_xclk = clk_get(NULL, "pcie_xclk");
-        if (IS_ERR(tegra_pcie.pcie_xclk)) {
-                err =  PTR_ERR(tegra_pcie.pcie_xclk);
-                goto err_pcie_xclk;
-        }
-
-        tegra_pcie.pll_e = clk_get_sys(NULL, "pll_e");
-        if (IS_ERR(tegra_pcie.pll_e)) {
-                err = PTR_ERR(tegra_pcie.pll_e);
-                goto err_pll_e;
-        }
-
-        return 0;
-
-err_pll_e:
-        clk_put(tegra_pcie.pcie_xclk);
-err_pcie_xclk:
-        clk_put(tegra_pcie.afi_clk);
-err_afi_clk:
-        clk_put(tegra_pcie.pex_clk);
-
-        return err;
-}
-
-static void tegra_pcie_clocks_put(void)
-{
-        clk_put(tegra_pcie.pll_e);
-        clk_put(tegra_pcie.pcie_xclk);
-        clk_put(tegra_pcie.afi_clk);
-        clk_put(tegra_pcie.pex_clk);
-}
-
-static int __init tegra_pcie_get_resources(void)
-{
-        int err;
-
-        err = tegra_pcie_clocks_get();
-        if (err) {
-                pr_err("PCIE: failed to get clocks: %d\n", err);
-                return err;
-        }
-
-        err = tegra_pcie_power_regate();
-        if (err) {
-                pr_err("PCIE: failed to power up: %d\n", err);
-                goto err_pwr_on;
-        }
-
-        tegra_pcie.regs = ioremap_nocache(TEGRA_PCIE_BASE, PCIE_IOMAP_SZ);
-        if (tegra_pcie.regs == NULL) {
-                pr_err("PCIE: Failed to map PCI/AFI registers\n");
-                err = -ENOMEM;
-                goto err_map_reg;
-        }
-
-        err = request_irq(INT_PCIE_INTR, tegra_pcie_isr,
-                          IRQF_SHARED, "PCIE", &tegra_pcie);
-        if (err) {
-                pr_err("PCIE: Failed to register IRQ: %d\n", err);
-                goto err_req_io;
-        }
-        set_irq_flags(INT_PCIE_INTR, IRQF_VALID);
-
-        return 0;
-
-err_req_io:
-        iounmap(tegra_pcie.regs);
-err_map_reg:
-        tegra_pcie_power_off();
-err_pwr_on:
-        tegra_pcie_clocks_put();
-
-        return err;
-}
-
-/*
- * FIXME: If there are no PCIe cards attached, then calling this function
- * can result in the increase of the bootup time as there are big timeout
- * loops.
- */
-#define TEGRA_PCIE_LINKUP_TIMEOUT       200     /* up to 1.2 seconds */
-static bool tegra_pcie_check_link(struct tegra_pcie_port *pp, int idx,
-                                  u32 reset_reg)
-{
-        u32 reg;
-        int retries = 3;
-        int timeout;
-
-        do {
-                timeout = TEGRA_PCIE_LINKUP_TIMEOUT;
-                while (timeout) {
-                        reg = readl(pp->base + RP_VEND_XP);
-
-                        if (reg & RP_VEND_XP_DL_UP)
-                                break;
-
-                        mdelay(1);
-                        timeout--;
-                }
-
-                if (!timeout)  {
-                        pr_err("PCIE: port %d: link down, retrying\n", idx);
-                        goto retry;
-                }
-
-                timeout = TEGRA_PCIE_LINKUP_TIMEOUT;
-                while (timeout) {
-                        reg = readl(pp->base + RP_LINK_CONTROL_STATUS);
-
-                        if (reg & 0x20000000)
-                                return true;
-
-                        mdelay(1);
-                        timeout--;
-                }
-
-retry:
-                /* Pulse the PEX reset */
-                reg = afi_readl(reset_reg) | AFI_PEX_CTRL_RST;
-                afi_writel(reg, reset_reg);
-                mdelay(1);
-                reg = afi_readl(reset_reg) & ~AFI_PEX_CTRL_RST;
-                afi_writel(reg, reset_reg);
-
-                retries--;
-        } while (retries);
-
-        return false;
-}
-
-static void __init tegra_pcie_add_port(int index, u32 offset, u32 reset_reg)
-{
-        struct tegra_pcie_port *pp;
-
-        pp = tegra_pcie.port + tegra_pcie.num_ports;
-
-        pp->index = -1;
-        pp->base = tegra_pcie.regs + offset;
-        pp->link_up = tegra_pcie_check_link(pp, index, reset_reg);
-
-        if (!pp->link_up) {
-                pp->base = NULL;
-                printk(KERN_INFO "PCIE: port %d: link down, ignoring\n", index);
-                return;
-        }
-
-        tegra_pcie.num_ports++;
-        pp->index = index;
-        pp->root_bus_nr = -1;
-        memset(pp->res, 0, sizeof(pp->res));
-}
-
-int __init tegra_pcie_init(bool init_port0, bool init_port1)
-{
-        int err;
-
-        if (!(init_port0 || init_port1))
-                return -ENODEV;
-
-        pcibios_min_mem = 0;
-
-        err = tegra_pcie_get_resources();
-        if (err)
-                return err;
-
-        err = tegra_pcie_enable_controller();
-        if (err)
-                return err;
-
-        /* setup the AFI address translations */
-        tegra_pcie_setup_translations();
-
-        if (init_port0)
-                tegra_pcie_add_port(0, RP0_OFFSET, AFI_PEX0_CTRL);
-
-        if (init_port1)
-                tegra_pcie_add_port(1, RP1_OFFSET, AFI_PEX1_CTRL);
-
-        pci_common_init(&tegra_pcie_hw);
-
-        return 0;
-}
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index 97b33a2a2d75..2d0203627fbb 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -196,6 +196,5 @@ struct smp_operations tegra_smp_ops __initdata = {
 #ifdef CONFIG_HOTPLUG_CPU
         .cpu_kill               = tegra_cpu_kill,
         .cpu_die                = tegra_cpu_die,
-        .cpu_disable            = tegra_cpu_disable,
 #endif
 };
diff --git a/arch/arm/mach-tegra/pm-tegra20.c b/arch/arm/mach-tegra/pm-tegra20.c
new file mode 100644
index 000000000000..d65e1d786400
--- /dev/null
+++ b/arch/arm/mach-tegra/pm-tegra20.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2013, NVIDIA Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/kernel.h>
+
+#include "pm.h"
+
+#ifdef CONFIG_PM_SLEEP
+extern u32 tegra20_iram_start, tegra20_iram_end;
+extern void tegra20_sleep_core_finish(unsigned long);
+
+void tegra20_lp1_iram_hook(void)
+{
+        tegra_lp1_iram.start_addr = &tegra20_iram_start;
+        tegra_lp1_iram.end_addr = &tegra20_iram_end;
+}
+
+void tegra20_sleep_core_init(void)
+{
+        tegra_sleep_core_finish = tegra20_sleep_core_finish;
+}
+#endif
diff --git a/arch/arm/mach-tegra/pm-tegra30.c b/arch/arm/mach-tegra/pm-tegra30.c
new file mode 100644
index 000000000000..8fa326d6ff1a
--- /dev/null
+++ b/arch/arm/mach-tegra/pm-tegra30.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2013, NVIDIA Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/kernel.h>
+
+#include "pm.h"
+
+#ifdef CONFIG_PM_SLEEP
+extern u32 tegra30_iram_start, tegra30_iram_end;
+extern void tegra30_sleep_core_finish(unsigned long);
+
+void tegra30_lp1_iram_hook(void)
+{
+        tegra_lp1_iram.start_addr = &tegra30_iram_start;
+        tegra_lp1_iram.end_addr = &tegra30_iram_end;
+}
+
+void tegra30_sleep_core_init(void)
+{
+        tegra_sleep_core_finish = tegra30_sleep_core_finish;
+}
+#endif
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c
index 261fec140c06..ed294a04e1d3 100644
--- a/arch/arm/mach-tegra/pm.c
+++ b/arch/arm/mach-tegra/pm.c
@@ -37,12 +37,18 @@
 #include "reset.h"
 #include "flowctrl.h"
 #include "fuse.h"
+#include "pm.h"
 #include "pmc.h"
 #include "sleep.h"
 
 #ifdef CONFIG_PM_SLEEP
 static DEFINE_SPINLOCK(tegra_lp2_lock);
+static u32 iram_save_size;
+static void *iram_save_addr;
+struct tegra_lp1_iram tegra_lp1_iram;
 void (*tegra_tear_down_cpu)(void);
+void (*tegra_sleep_core_finish)(unsigned long v2p);
+static int (*tegra_sleep_func)(unsigned long v2p);
 
 static void tegra_tear_down_cpu_init(void)
 {
@@ -52,7 +58,9 @@ static void tegra_tear_down_cpu_init(void)
                         tegra_tear_down_cpu = tegra20_tear_down_cpu;
                 break;
         case TEGRA30:
-                if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC))
+        case TEGRA114:
+                if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) ||
+                    IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC))
                         tegra_tear_down_cpu = tegra30_tear_down_cpu;
                 break;
         }
@@ -171,19 +179,109 @@ void tegra_idle_lp2_last(void)
 enum tegra_suspend_mode tegra_pm_validate_suspend_mode(
                                 enum tegra_suspend_mode mode)
 {
-        /* Tegra114 didn't support any suspending mode yet. */
-        if (tegra_chip_id == TEGRA114)
-                return TEGRA_SUSPEND_NONE;
-
         /*
-         * The Tegra devices only support suspending to LP2 currently.
+         * The Tegra devices support suspending to LP1 or lower currently.
          */
-        if (mode > TEGRA_SUSPEND_LP2)
-                return TEGRA_SUSPEND_LP2;
+        if (mode > TEGRA_SUSPEND_LP1)
+                return TEGRA_SUSPEND_LP1;
 
         return mode;
 }
 
+static int tegra_sleep_core(unsigned long v2p)
+{
+        setup_mm_for_reboot();
+        tegra_sleep_core_finish(v2p);
+
+        /* should never here */
+        BUG();
+
+        return 0;
+}
+
+/*
+ * tegra_lp1_iram_hook
+ *
+ * Hooking the address of LP1 reset vector and SDRAM self-refresh code in
+ * SDRAM. These codes not be copied to IRAM in this fuction. We need to
+ * copy these code to IRAM before LP0/LP1 suspend and restore the content
+ * of IRAM after resume.
+ */
+static bool tegra_lp1_iram_hook(void)
+{
+        switch (tegra_chip_id) {
+        case TEGRA20:
+                if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
+                        tegra20_lp1_iram_hook();
+                break;
+        case TEGRA30:
+        case TEGRA114:
+                if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) ||
+                    IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC))
+                        tegra30_lp1_iram_hook();
+                break;
+        default:
+                break;
+        }
+
+        if (!tegra_lp1_iram.start_addr || !tegra_lp1_iram.end_addr)
+                return false;
+
+        iram_save_size = tegra_lp1_iram.end_addr - tegra_lp1_iram.start_addr;
+        iram_save_addr = kmalloc(iram_save_size, GFP_KERNEL);
+        if (!iram_save_addr)
+                return false;
+
+        return true;
+}
+
+static bool tegra_sleep_core_init(void)
+{
+        switch (tegra_chip_id) {
+        case TEGRA20:
+                if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
+                        tegra20_sleep_core_init();
+                break;
+        case TEGRA30:
+        case TEGRA114:
+                if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) ||
+                    IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC))
+                        tegra30_sleep_core_init();
+                break;
+        default:
+                break;
+        }
+
+        if (!tegra_sleep_core_finish)
+                return false;
+
+        return true;
+}
+
+static void tegra_suspend_enter_lp1(void)
+{
+        tegra_pmc_suspend();
+
+        /* copy the reset vector & SDRAM shutdown code into IRAM */
+        memcpy(iram_save_addr, IO_ADDRESS(TEGRA_IRAM_CODE_AREA),
+                iram_save_size);
+        memcpy(IO_ADDRESS(TEGRA_IRAM_CODE_AREA), tegra_lp1_iram.start_addr,
+                iram_save_size);
+
+        *((u32 *)tegra_cpu_lp1_mask) = 1;
+}
+
+static void tegra_suspend_exit_lp1(void)
+{
+        tegra_pmc_resume();
+
+        /* restore IRAM */
+        memcpy(IO_ADDRESS(TEGRA_IRAM_CODE_AREA), iram_save_addr,
+                iram_save_size);
+
+        *(u32 *)tegra_cpu_lp1_mask = 0;
+}
+
 static const char *lp_state[TEGRA_MAX_SUSPEND_MODE] = {
         [TEGRA_SUSPEND_NONE] = "none",
         [TEGRA_SUSPEND_LP2] = "LP2",
@@ -207,6 +305,9 @@ static int tegra_suspend_enter(suspend_state_t state)
 
         suspend_cpu_complex();
         switch (mode) {
+        case TEGRA_SUSPEND_LP1:
+                tegra_suspend_enter_lp1();
+                break;
         case TEGRA_SUSPEND_LP2:
                 tegra_set_cpu_in_lp2();
                 break;
@@ -214,9 +315,12 @@ static int tegra_suspend_enter(suspend_state_t state)
                 break;
         }
 
-        cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu);
+        cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, tegra_sleep_func);
 
         switch (mode) {
+        case TEGRA_SUSPEND_LP1:
+                tegra_suspend_exit_lp1();
+                break;
         case TEGRA_SUSPEND_LP2:
                 tegra_clear_cpu_in_lp2();
                 break;
@@ -237,12 +341,36 @@ static const struct platform_suspend_ops tegra_suspend_ops = {
 
 void __init tegra_init_suspend(void)
 {
-        if (tegra_pmc_get_suspend_mode() == TEGRA_SUSPEND_NONE)
+        enum tegra_suspend_mode mode = tegra_pmc_get_suspend_mode();
+
+        if (mode == TEGRA_SUSPEND_NONE)
                 return;
 
         tegra_tear_down_cpu_init();
         tegra_pmc_suspend_init();
 
+        if (mode >= TEGRA_SUSPEND_LP1) {
+                if (!tegra_lp1_iram_hook() || !tegra_sleep_core_init()) {
+                        pr_err("%s: unable to allocate memory for SDRAM"
+                               "self-refresh -- LP0/LP1 unavailable\n",
+                               __func__);
+                        tegra_pmc_set_suspend_mode(TEGRA_SUSPEND_LP2);
+                        mode = TEGRA_SUSPEND_LP2;
+                }
+        }
+
+        /* set up sleep function for cpu_suspend */
+        switch (mode) {
+        case TEGRA_SUSPEND_LP1:
+                tegra_sleep_func = tegra_sleep_core;
+                break;
+        case TEGRA_SUSPEND_LP2:
+                tegra_sleep_func = tegra_sleep_cpu;
+                break;
+        default:
+                break;
+        }
+
         suspend_set_ops(&tegra_suspend_ops);
 }
 #endif
diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h
index 94c4b9d9077c..fe204e5256e7 100644
--- a/arch/arm/mach-tegra/pm.h
+++ b/arch/arm/mach-tegra/pm.h
@@ -23,6 +23,18 @@
 
 #include "pmc.h"
 
+struct tegra_lp1_iram {
+        void    *start_addr;
+        void    *end_addr;
+};
+extern struct tegra_lp1_iram tegra_lp1_iram;
+extern void (*tegra_sleep_core_finish)(unsigned long v2p);
+
+void tegra20_lp1_iram_hook(void);
+void tegra20_sleep_core_init(void);
+void tegra30_lp1_iram_hook(void);
+void tegra30_sleep_core_init(void);
+
 extern unsigned long l2x0_saved_regs_addr;
 
 void save_cpu_arch_register(void);
diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c
index eb3fa4aee0e4..8acb881f7cfe 100644
--- a/arch/arm/mach-tegra/pmc.c
+++ b/arch/arm/mach-tegra/pmc.c
@@ -21,11 +21,14 @@
 #include <linux/of.h>
 #include <linux/of_address.h>
 
+#include "flowctrl.h"
 #include "fuse.h"
 #include "pm.h"
 #include "pmc.h"
 #include "sleep.h"
 
+#define TEGRA_POWER_SYSCLK_POLARITY     (1 << 10)  /* sys clk polarity */
+#define TEGRA_POWER_SYSCLK_OE           (1 << 11)  /* system clock enable */
 #define TEGRA_POWER_EFFECT_LP0          (1 << 14)  /* LP0 when CPU pwr gated */
 #define TEGRA_POWER_CPU_PWRREQ_POLARITY (1 << 15)  /* CPU pwr req polarity */
 #define TEGRA_POWER_CPU_PWRREQ_OE       (1 << 16)  /* CPU pwr req enable */
@@ -193,16 +196,50 @@ enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
         return pmc_pm_data.suspend_mode;
 }
 
+void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode)
+{
+        if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE)
+                return;
+
+        pmc_pm_data.suspend_mode = mode;
+}
+
+void tegra_pmc_suspend(void)
+{
+        tegra_pmc_writel(virt_to_phys(tegra_resume), PMC_SCRATCH41);
+}
+
+void tegra_pmc_resume(void)
+{
+        tegra_pmc_writel(0x0, PMC_SCRATCH41);
+}
+
 void tegra_pmc_pm_set(enum tegra_suspend_mode mode)
 {
-        u32 reg;
+        u32 reg, csr_reg;
         unsigned long rate = 0;
 
         reg = tegra_pmc_readl(PMC_CTRL);
         reg |= TEGRA_POWER_CPU_PWRREQ_OE;
         reg &= ~TEGRA_POWER_EFFECT_LP0;
 
+        switch (tegra_chip_id) {
+        case TEGRA20:
+        case TEGRA30:
+                break;
+        default:
+                /* Turn off CRAIL */
+                csr_reg = flowctrl_read_cpu_csr(0);
+                csr_reg &= ~FLOW_CTRL_CSR_ENABLE_EXT_MASK;
+                csr_reg |= FLOW_CTRL_CSR_ENABLE_EXT_CRAIL;
+                flowctrl_write_cpu_csr(0, csr_reg);
+                break;
+        }
+
         switch (mode) {
+        case TEGRA_SUSPEND_LP1:
+                rate = 32768;
+                break;
         case TEGRA_SUSPEND_LP2:
                 rate = clk_get_rate(tegra_pclk);
                 break;
@@ -224,6 +261,20 @@ void tegra_pmc_suspend_init(void)
         reg = tegra_pmc_readl(PMC_CTRL);
         reg |= TEGRA_POWER_CPU_PWRREQ_OE;
         tegra_pmc_writel(reg, PMC_CTRL);
+
+        reg = tegra_pmc_readl(PMC_CTRL);
+
+        if (!pmc_pm_data.sysclkreq_high)
+                reg |= TEGRA_POWER_SYSCLK_POLARITY;
+        else
+                reg &= ~TEGRA_POWER_SYSCLK_POLARITY;
+
+        /* configure the output polarity while the request is tristated */
+        tegra_pmc_writel(reg, PMC_CTRL);
+
+        /* now enable the request */
+        reg |= TEGRA_POWER_SYSCLK_OE;
+        tegra_pmc_writel(reg, PMC_CTRL);
 }
 #endif
 
diff --git a/arch/arm/mach-tegra/pmc.h b/arch/arm/mach-tegra/pmc.h
index e1c2df272f7d..549f8c7b762c 100644
--- a/arch/arm/mach-tegra/pmc.h
+++ b/arch/arm/mach-tegra/pmc.h
@@ -28,6 +28,9 @@ enum tegra_suspend_mode {
 
 #ifdef CONFIG_PM_SLEEP
 enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void);
+void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode);
+void tegra_pmc_suspend(void);
+void tegra_pmc_resume(void);
 void tegra_pmc_pm_set(enum tegra_suspend_mode mode);
 void tegra_pmc_suspend_init(void);
 #endif
diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S
index 39dc9e7834f3..f527b2c2dea7 100644
--- a/arch/arm/mach-tegra/reset-handler.S
+++ b/arch/arm/mach-tegra/reset-handler.S
@@ -40,9 +40,12 @@
  *        re-enabling sdram.
  *
  *      r6: SoC ID
+ *      r8: CPU part number
  */
 ENTRY(tegra_resume)
-        bl      v7_invalidate_l1
+        check_cpu_part_num 0xc09, r8, r9
+        bleq    v7_invalidate_l1
+        blne    tegra_init_l2_for_a15
 
         cpu_id  r0
         tegra_get_soc_id TEGRA_APB_MISC_BASE, r6
@@ -70,7 +73,8 @@ no_cpu0_chk:
         str     r1, [r2]
 1:
 
-        check_cpu_part_num 0xc09, r8, r9
+        mov32   r9, 0xc09
+        cmp     r8, r9
         bne     not_ca9
 #ifdef CONFIG_HAVE_ARM_SCU
         /* enable SCU */
@@ -178,6 +182,19 @@ after_errata:
 1:
 #endif
 
+        /* Waking up from LP1? */
+        ldr     r8, [r12, #RESET_DATA(MASK_LP1)]
+        tst     r8, r11                         @ if in_lp1
+        beq     __is_not_lp1
+        cmp     r10, #0
+        bne     __die                           @ only CPU0 can be here
+        ldr     lr, [r12, #RESET_DATA(STARTUP_LP1)]
+        cmp     lr, #0
+        bleq    __die                           @ no LP1 startup handler
+ THUMB( add     lr, lr, #1 )                    @ switch to Thumb mode
+        bx      lr
+__is_not_lp1:
+
         /* Waking up from LP2? */
         ldr     r9, [r12, #RESET_DATA(MASK_LP2)]
         tst     r9, r11                         @ if in_lp2
diff --git a/arch/arm/mach-tegra/reset.c b/arch/arm/mach-tegra/reset.c
index 1ac434e0068f..fd0bbf8a6c94 100644
--- a/arch/arm/mach-tegra/reset.c
+++ b/arch/arm/mach-tegra/reset.c
@@ -81,6 +81,8 @@ void __init tegra_cpu_reset_handler_init(void)
 #endif
 
 #ifdef CONFIG_PM_SLEEP
+        __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP1] =
+                TEGRA_IRAM_CODE_AREA;
         __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP2] =
                 virt_to_phys((void *)tegra_resume);
 #endif
diff --git a/arch/arm/mach-tegra/reset.h b/arch/arm/mach-tegra/reset.h
index c90d8e9c4ad2..76a93434c6ee 100644
--- a/arch/arm/mach-tegra/reset.h
+++ b/arch/arm/mach-tegra/reset.h
@@ -39,6 +39,10 @@ void __tegra_cpu_reset_handler_end(void);
 void tegra_secondary_startup(void);
 
 #ifdef CONFIG_PM_SLEEP
+#define tegra_cpu_lp1_mask \
+        (IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \
+        ((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_LP1] - \
+         (u32)__tegra_cpu_reset_handler_start)))
 #define tegra_cpu_lp2_mask \
         (IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \
         ((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_LP2] - \
diff --git a/arch/arm/mach-tegra/sleep-tegra20.S b/arch/arm/mach-tegra/sleep-tegra20.S
index e3f2417c420e..5c3bd11c9838 100644
--- a/arch/arm/mach-tegra/sleep-tegra20.S
+++ b/arch/arm/mach-tegra/sleep-tegra20.S
@@ -23,10 +23,49 @@
 #include <asm/assembler.h>
 #include <asm/proc-fns.h>
 #include <asm/cp15.h>
+#include <asm/cache.h>
 
 #include "sleep.h"
 #include "flowctrl.h"
 
+#define EMC_CFG                         0xc
+#define EMC_ADR_CFG                     0x10
+#define EMC_REFRESH                     0x70
+#define EMC_NOP                         0xdc
+#define EMC_SELF_REF                    0xe0
+#define EMC_REQ_CTRL                    0x2b0
+#define EMC_EMC_STATUS                  0x2b4
+
+#define CLK_RESET_CCLK_BURST            0x20
+#define CLK_RESET_CCLK_DIVIDER          0x24
+#define CLK_RESET_SCLK_BURST            0x28
+#define CLK_RESET_SCLK_DIVIDER          0x2c
+#define CLK_RESET_PLLC_BASE             0x80
+#define CLK_RESET_PLLM_BASE             0x90
+#define CLK_RESET_PLLP_BASE             0xa0
+
+#define APB_MISC_XM2CFGCPADCTRL         0x8c8
+#define APB_MISC_XM2CFGDPADCTRL         0x8cc
+#define APB_MISC_XM2CLKCFGPADCTRL       0x8d0
+#define APB_MISC_XM2COMPPADCTRL         0x8d4
+#define APB_MISC_XM2VTTGENPADCTRL       0x8d8
+#define APB_MISC_XM2CFGCPADCTRL2        0x8e4
+#define APB_MISC_XM2CFGDPADCTRL2        0x8e8
+
+.macro pll_enable, rd, r_car_base, pll_base
+        ldr     \rd, [\r_car_base, #\pll_base]
+        tst     \rd, #(1 << 30)
+        orreq   \rd, \rd, #(1 << 30)
+        streq   \rd, [\r_car_base, #\pll_base]
+.endm
+
+.macro emc_device_mask, rd, base
+        ldr     \rd, [\base, #EMC_ADR_CFG]
+        tst     \rd, #(0x3 << 24)
+        moveq   \rd, #(0x1 << 8)                @ just 1 device
+        movne   \rd, #(0x3 << 8)                @ 2 devices
+.endm
+
 #if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP)
 /*
  * tegra20_hotplug_shutdown(void)
@@ -181,6 +220,28 @@ ENTRY(tegra20_cpu_is_resettable_soon)
 ENDPROC(tegra20_cpu_is_resettable_soon)
 
 /*
+ * tegra20_sleep_core_finish(unsigned long v2p)
+ *
+ * Enters suspend in LP0 or LP1 by turning off the mmu and jumping to
+ * tegra20_tear_down_core in IRAM
+ */
+ENTRY(tegra20_sleep_core_finish)
+        /* Flush, disable the L1 data cache and exit SMP */
+        bl      tegra_disable_clean_inv_dcache
+
+        mov32   r3, tegra_shut_off_mmu
+        add     r3, r3, r0
+
+        mov32   r0, tegra20_tear_down_core
+        mov32   r1, tegra20_iram_start
+        sub     r0, r0, r1
+        mov32   r1, TEGRA_IRAM_CODE_AREA
+        add     r0, r0, r1
+
+        mov     pc, r3
+ENDPROC(tegra20_sleep_core_finish)
+
+/*
  * tegra20_sleep_cpu_secondary_finish(unsigned long v2p)
  *
  * Enters WFI on secondary CPU by exiting coherency.
@@ -191,6 +252,7 @@ ENTRY(tegra20_sleep_cpu_secondary_finish)
         mrc     p15, 0, r11, c1, c0, 1  @ save actlr before exiting coherency
 
         /* Flush and disable the L1 data cache */
+        mov     r0, #TEGRA_FLUSH_CACHE_LOUIS
         bl      tegra_disable_clean_inv_dcache
 
         mov32   r0, TEGRA_PMC_VIRT + PMC_SCRATCH41
@@ -250,6 +312,150 @@ ENTRY(tegra20_tear_down_cpu)
         b       tegra20_enter_sleep
 ENDPROC(tegra20_tear_down_cpu)
 
+/* START OF ROUTINES COPIED TO IRAM */
+        .align L1_CACHE_SHIFT
+        .globl tegra20_iram_start
+tegra20_iram_start:
+
+/*
+ * tegra20_lp1_reset
+ *
+ * reset vector for LP1 restore; copied into IRAM during suspend.
+ * Brings the system back up to a safe staring point (SDRAM out of
+ * self-refresh, PLLC, PLLM and PLLP reenabled, CPU running on PLLP,
+ * system clock running on the same PLL that it suspended at), and
+ * jumps to tegra_resume to restore virtual addressing and PLLX.
+ * The physical address of tegra_resume expected to be stored in
+ * PMC_SCRATCH41.
+ *
+ * NOTE: THIS *MUST* BE RELOCATED TO TEGRA_IRAM_CODE_AREA.
+ */
+ENTRY(tegra20_lp1_reset)
+        /*
+         * The CPU and system bus are running at 32KHz and executing from
+         * IRAM when this code is executed; immediately switch to CLKM and
+         * enable PLLM, PLLP, PLLC.
+         */
+        mov32   r0, TEGRA_CLK_RESET_BASE
+
+        mov     r1, #(1 << 28)
+        str     r1, [r0, #CLK_RESET_SCLK_BURST]
+        str     r1, [r0, #CLK_RESET_CCLK_BURST]
+        mov     r1, #0
+        str     r1, [r0, #CLK_RESET_CCLK_DIVIDER]
+        str     r1, [r0, #CLK_RESET_SCLK_DIVIDER]
+
+        pll_enable r1, r0, CLK_RESET_PLLM_BASE
+        pll_enable r1, r0, CLK_RESET_PLLP_BASE
+        pll_enable r1, r0, CLK_RESET_PLLC_BASE
+
+        adr     r2, tegra20_sdram_pad_address
+        adr     r4, tegra20_sdram_pad_save
+        mov     r5, #0
+
+        ldr     r6, tegra20_sdram_pad_size
+padload:
+        ldr     r7, [r2, r5]            @ r7 is the addr in the pad_address
+
+        ldr     r1, [r4, r5]
+        str     r1, [r7]                @ restore the value in pad_save
+
+        add     r5, r5, #4
+        cmp     r6, r5
+        bne     padload
+
+padload_done:
+        /* 255uS delay for PLL stabilization */
+        mov32   r7, TEGRA_TMRUS_BASE
+        ldr     r1, [r7]
+        add     r1, r1, #0xff
+        wait_until r1, r7, r9
+
+        adr     r4, tegra20_sclk_save
+        ldr     r4, [r4]
+        str     r4, [r0, #CLK_RESET_SCLK_BURST]
+        mov32   r4, ((1 << 28) | (4))   @ burst policy is PLLP
+        str     r4, [r0, #CLK_RESET_CCLK_BURST]
+
+        mov32   r0, TEGRA_EMC_BASE
+        ldr     r1, [r0, #EMC_CFG]
+        bic     r1, r1, #(1 << 31)      @ disable DRAM_CLK_STOP
+        str     r1, [r0, #EMC_CFG]
+
+        mov     r1, #0
+        str     r1, [r0, #EMC_SELF_REF] @ take DRAM out of self refresh
+        mov     r1, #1
+        str     r1, [r0, #EMC_NOP]
+        str     r1, [r0, #EMC_NOP]
+        str     r1, [r0, #EMC_REFRESH]
+
+        emc_device_mask r1, r0
+
+exit_selfrefresh_loop:
+        ldr     r2, [r0, #EMC_EMC_STATUS]
+        ands    r2, r2, r1
+        bne     exit_selfrefresh_loop
+
+        mov     r1, #0                  @ unstall all transactions
+        str     r1, [r0, #EMC_REQ_CTRL]
+
+        mov32   r0, TEGRA_PMC_BASE
+        ldr     r0, [r0, #PMC_SCRATCH41]
+        mov     pc, r0                  @ jump to tegra_resume
+ENDPROC(tegra20_lp1_reset)
+
+/*
+ * tegra20_tear_down_core
+ *
+ * copied into and executed from IRAM
+ * puts memory in self-refresh for LP0 and LP1
+ */
+tegra20_tear_down_core:
+        bl      tegra20_sdram_self_refresh
+        bl      tegra20_switch_cpu_to_clk32k
+        b       tegra20_enter_sleep
+
+/*
+ * tegra20_switch_cpu_to_clk32k
+ *
+ * In LP0 and LP1 all PLLs will be turned off. Switch the CPU and system clock
+ * to the 32KHz clock.
+ */
+tegra20_switch_cpu_to_clk32k:
+        /*
+         * start by switching to CLKM to safely disable PLLs, then switch to
+         * CLKS.
+         */
+        mov     r0, #(1 << 28)
+        str     r0, [r5, #CLK_RESET_SCLK_BURST]
+        str     r0, [r5, #CLK_RESET_CCLK_BURST]
+        mov     r0, #0
+        str     r0, [r5, #CLK_RESET_CCLK_DIVIDER]
+        str     r0, [r5, #CLK_RESET_SCLK_DIVIDER]
+
+        /* 2uS delay delay between changing SCLK and disabling PLLs */
+        mov32   r7, TEGRA_TMRUS_BASE
+        ldr     r1, [r7]
+        add     r1, r1, #2
+        wait_until r1, r7, r9
+
+        /* disable PLLM, PLLP and PLLC */
+        ldr     r0, [r5, #CLK_RESET_PLLM_BASE]
+        bic     r0, r0, #(1 << 30)
+        str     r0, [r5, #CLK_RESET_PLLM_BASE]
+        ldr     r0, [r5, #CLK_RESET_PLLP_BASE]
+        bic     r0, r0, #(1 << 30)
+        str     r0, [r5, #CLK_RESET_PLLP_BASE]
+        ldr     r0, [r5, #CLK_RESET_PLLC_BASE]
+        bic     r0, r0, #(1 << 30)
+        str     r0, [r5, #CLK_RESET_PLLC_BASE]
+
+        /* switch to CLKS */
+        mov     r0, #0  /* brust policy = 32KHz */
+        str     r0, [r5, #CLK_RESET_SCLK_BURST]
+
+        mov     pc, lr
+
 /*
  * tegra20_enter_sleep
  *
@@ -274,4 +480,95 @@ halted:
         isb
         b       halted
 
+/*
+ * tegra20_sdram_self_refresh
+ *
+ * called with MMU off and caches disabled
+ * puts sdram in self refresh
+ * must be executed from IRAM
+ */
+tegra20_sdram_self_refresh:
+        mov32   r1, TEGRA_EMC_BASE      @ r1 reserved for emc base addr
+
+        mov     r2, #3
+        str     r2, [r1, #EMC_REQ_CTRL] @ stall incoming DRAM requests
+
+emcidle:
+        ldr     r2, [r1, #EMC_EMC_STATUS]
+        tst     r2, #4
+        beq     emcidle
+
+        mov     r2, #1
+        str     r2, [r1, #EMC_SELF_REF]
+
+        emc_device_mask r2, r1
+
+emcself:
+        ldr     r3, [r1, #EMC_EMC_STATUS]
+        and     r3, r3, r2
+        cmp     r3, r2
+        bne     emcself                 @ loop until DDR in self-refresh
+
+        adr     r2, tegra20_sdram_pad_address
+        adr     r3, tegra20_sdram_pad_safe
+        adr     r4, tegra20_sdram_pad_save
+        mov     r5, #0
+
+        ldr     r6, tegra20_sdram_pad_size
+padsave:
+        ldr     r0, [r2, r5]            @ r0 is the addr in the pad_address
+
+        ldr     r1, [r0]
+        str     r1, [r4, r5]            @ save the content of the addr
+
+        ldr     r1, [r3, r5]
+        str     r1, [r0]                @ set the save val to the addr
+
+        add     r5, r5, #4
+        cmp     r6, r5
+        bne     padsave
+padsave_done:
+
+        mov32   r5, TEGRA_CLK_RESET_BASE
+        ldr     r0, [r5, #CLK_RESET_SCLK_BURST]
+        adr     r2, tegra20_sclk_save
+        str     r0, [r2]
+        dsb
+        mov     pc, lr
+
+tegra20_sdram_pad_address:
+        .word   TEGRA_APB_MISC_BASE + APB_MISC_XM2CFGCPADCTRL
+        .word   TEGRA_APB_MISC_BASE + APB_MISC_XM2CFGDPADCTRL
+        .word   TEGRA_APB_MISC_BASE + APB_MISC_XM2CLKCFGPADCTRL
+        .word   TEGRA_APB_MISC_BASE + APB_MISC_XM2COMPPADCTRL
+        .word   TEGRA_APB_MISC_BASE + APB_MISC_XM2VTTGENPADCTRL
+        .word   TEGRA_APB_MISC_BASE + APB_MISC_XM2CFGCPADCTRL2
+        .word   TEGRA_APB_MISC_BASE + APB_MISC_XM2CFGDPADCTRL2
+
+tegra20_sdram_pad_size:
+        .word   tegra20_sdram_pad_size - tegra20_sdram_pad_address
+
+tegra20_sdram_pad_safe:
+        .word   0x8
+        .word   0x8
+        .word   0x0
+        .word   0x8
+        .word   0x5500
+        .word   0x08080040
+        .word   0x0
+
+tegra20_sclk_save:
+        .word   0x0
+
+tegra20_sdram_pad_save:
+        .rept (tegra20_sdram_pad_size - tegra20_sdram_pad_address) / 4
+        .long   0
+        .endr
+
+        .ltorg
+/* dummy symbol for end of IRAM */
+        .align L1_CACHE_SHIFT
+        .globl tegra20_iram_end
+tegra20_iram_end:
+        b       .
 #endif
diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S
index ada8821b48be..63fa91b5fafb 100644
--- a/arch/arm/mach-tegra/sleep-tegra30.S
+++ b/arch/arm/mach-tegra/sleep-tegra30.S
@@ -18,13 +18,118 @@
 
 #include <asm/assembler.h>
 #include <asm/asm-offsets.h>
+#include <asm/cache.h>
 
 #include "fuse.h"
 #include "sleep.h"
 #include "flowctrl.h"
 
+#define EMC_CFG                         0xc
+#define EMC_ADR_CFG                     0x10
+#define EMC_TIMING_CONTROL              0x28
+#define EMC_REFRESH                     0x70
+#define EMC_NOP                         0xdc
+#define EMC_SELF_REF                    0xe0
+#define EMC_MRW                         0xe8
+#define EMC_FBIO_CFG5                   0x104
+#define EMC_AUTO_CAL_CONFIG             0x2a4
+#define EMC_AUTO_CAL_INTERVAL           0x2a8
+#define EMC_AUTO_CAL_STATUS             0x2ac
+#define EMC_REQ_CTRL                    0x2b0
+#define EMC_CFG_DIG_DLL                 0x2bc
+#define EMC_EMC_STATUS                  0x2b4
+#define EMC_ZCAL_INTERVAL               0x2e0
+#define EMC_ZQ_CAL                      0x2ec
+#define EMC_XM2VTTGENPADCTRL            0x310
+#define EMC_XM2VTTGENPADCTRL2           0x314
+
+#define PMC_CTRL                        0x0
+#define PMC_CTRL_SIDE_EFFECT_LP0 (1 << 14) /* enter LP0 when CPU pwr gated */
+
+#define PMC_PLLP_WB0_OVERRIDE           0xf8
+#define PMC_IO_DPD_REQ                  0x1b8
+#define PMC_IO_DPD_STATUS               0x1bc
+
+#define CLK_RESET_CCLK_BURST            0x20
+#define CLK_RESET_CCLK_DIVIDER          0x24
+#define CLK_RESET_SCLK_BURST            0x28
+#define CLK_RESET_SCLK_DIVIDER          0x2c
+
+#define CLK_RESET_PLLC_BASE             0x80
+#define CLK_RESET_PLLC_MISC             0x8c
+#define CLK_RESET_PLLM_BASE             0x90
+#define CLK_RESET_PLLM_MISC             0x9c
+#define CLK_RESET_PLLP_BASE             0xa0
+#define CLK_RESET_PLLP_MISC             0xac
+#define CLK_RESET_PLLA_BASE             0xb0
+#define CLK_RESET_PLLA_MISC             0xbc
+#define CLK_RESET_PLLX_BASE             0xe0
+#define CLK_RESET_PLLX_MISC             0xe4
+#define CLK_RESET_PLLX_MISC3            0x518
+#define CLK_RESET_PLLX_MISC3_IDDQ       3
+#define CLK_RESET_PLLM_MISC_IDDQ        5
+#define CLK_RESET_PLLC_MISC_IDDQ        26
+
+#define CLK_RESET_CLK_SOURCE_MSELECT    0x3b4
+
+#define MSELECT_CLKM                    (0x3 << 30)
+
+#define LOCK_DELAY 50 /* safety delay after lock is detected */
+
 #define TEGRA30_POWER_HOTPLUG_SHUTDOWN  (1 << 27) /* Hotplug shutdown */
 
+.macro emc_device_mask, rd, base
+        ldr     \rd, [\base, #EMC_ADR_CFG]
+        tst     \rd, #0x1
+        moveq   \rd, #(0x1 << 8)                @ just 1 device
+        movne   \rd, #(0x3 << 8)                @ 2 devices
+.endm
+
+.macro emc_timing_update, rd, base
+        mov     \rd, #1
+        str     \rd, [\base, #EMC_TIMING_CONTROL]
+1001:
+        ldr     \rd, [\base, #EMC_EMC_STATUS]
+        tst     \rd, #(0x1<<23) @ wait EMC_STATUS_TIMING_UPDATE_STALLED is clear
+        bne     1001b
+.endm
+
+.macro pll_enable, rd, r_car_base, pll_base, pll_misc
+        ldr     \rd, [\r_car_base, #\pll_base]
+        tst     \rd, #(1 << 30)
+        orreq   \rd, \rd, #(1 << 30)
+        streq   \rd, [\r_car_base, #\pll_base]
+        /* Enable lock detector */
+        .if     \pll_misc
+        ldr     \rd, [\r_car_base, #\pll_misc]
+        bic     \rd, \rd, #(1 << 18)
+        str     \rd, [\r_car_base, #\pll_misc]
+        ldr     \rd, [\r_car_base, #\pll_misc]
+        ldr     \rd, [\r_car_base, #\pll_misc]
+        orr     \rd, \rd, #(1 << 18)
+        str     \rd, [\r_car_base, #\pll_misc]
+        .endif
+.endm
+
+.macro pll_locked, rd, r_car_base, pll_base
+1:
+        ldr     \rd, [\r_car_base, #\pll_base]
+        tst     \rd, #(1 << 27)
+        beq     1b
+.endm
+
+.macro pll_iddq_exit, rd, car, iddq, iddq_bit
+        ldr     \rd, [\car, #\iddq]
+        bic     \rd, \rd, #(1<<\iddq_bit)
+        str     \rd, [\car, #\iddq]
+.endm
+
+.macro pll_iddq_entry, rd, car, iddq, iddq_bit
+        ldr     \rd, [\car, #\iddq]
+        orr     \rd, \rd, #(1<<\iddq_bit)
+        str     \rd, [\car, #\iddq]
+.endm
+
 #if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP)
 /*
  * tegra30_hotplug_shutdown(void)
@@ -99,6 +204,8 @@ flow_ctrl_setting_for_lp2:
         cmp     r10, #TEGRA30
         moveq   r3, #FLOW_CTRL_WAIT_FOR_INTERRUPT       @ For LP2
         movne   r3, #FLOW_CTRL_WAITEVENT
+        orrne   r3, r3, #FLOW_CTRL_HALT_GIC_IRQ
+        orrne   r3, r3, #FLOW_CTRL_HALT_GIC_FIQ
 flow_ctrl_done:
         cmp     r10, #TEGRA30
         str     r3, [r2]
@@ -127,6 +234,41 @@ ENDPROC(tegra30_cpu_shutdown)
 
 #ifdef CONFIG_PM_SLEEP
 /*
+ * tegra30_sleep_core_finish(unsigned long v2p)
+ *
+ * Enters suspend in LP0 or LP1 by turning off the MMU and jumping to
+ * tegra30_tear_down_core in IRAM
+ */
+ENTRY(tegra30_sleep_core_finish)
+        /* Flush, disable the L1 data cache and exit SMP */
+        bl      tegra_disable_clean_inv_dcache
+
+        /*
+         * Preload all the address literals that are needed for the
+         * CPU power-gating process, to avoid loading from SDRAM which
+         * are not supported once SDRAM is put into self-refresh.
+         * LP0 / LP1 use physical address, since the MMU needs to be
+         * disabled before putting SDRAM into self-refresh to avoid
+         * memory access due to page table walks.
+         */
+        mov32   r4, TEGRA_PMC_BASE
+        mov32   r5, TEGRA_CLK_RESET_BASE
+        mov32   r6, TEGRA_FLOW_CTRL_BASE
+        mov32   r7, TEGRA_TMRUS_BASE
+
+        mov32   r3, tegra_shut_off_mmu
+        add     r3, r3, r0
+
+        mov32   r0, tegra30_tear_down_core
+        mov32   r1, tegra30_iram_start
+        sub     r0, r0, r1
+        mov32   r1, TEGRA_IRAM_CODE_AREA
+        add     r0, r0, r1
+
+        mov     pc, r3
+ENDPROC(tegra30_sleep_core_finish)
+
+/*
  * tegra30_sleep_cpu_secondary_finish(unsigned long v2p)
  *
  * Enters LP2 on secondary CPU by exiting coherency and powergating the CPU.
@@ -135,6 +277,7 @@ ENTRY(tegra30_sleep_cpu_secondary_finish)
         mov     r7, lr
 
         /* Flush and disable the L1 data cache */
+        mov     r0, #TEGRA_FLUSH_CACHE_LOUIS
         bl      tegra_disable_clean_inv_dcache
 
         /* Powergate this CPU. */
@@ -155,6 +298,351 @@ ENTRY(tegra30_tear_down_cpu)
         b       tegra30_enter_sleep
 ENDPROC(tegra30_tear_down_cpu)
 
+/* START OF ROUTINES COPIED TO IRAM */
+        .align L1_CACHE_SHIFT
+        .globl tegra30_iram_start
+tegra30_iram_start:
+
+/*
+ * tegra30_lp1_reset
+ *
+ * reset vector for LP1 restore; copied into IRAM during suspend.
+ * Brings the system back up to a safe staring point (SDRAM out of
+ * self-refresh, PLLC, PLLM and PLLP reenabled, CPU running on PLLX,
+ * system clock running on the same PLL that it suspended at), and
+ * jumps to tegra_resume to restore virtual addressing.
+ * The physical address of tegra_resume expected to be stored in
+ * PMC_SCRATCH41.
+ *
+ * NOTE: THIS *MUST* BE RELOCATED TO TEGRA_IRAM_CODE_AREA.
+ */
+ENTRY(tegra30_lp1_reset)
+        /*
+         * The CPU and system bus are running at 32KHz and executing from
+         * IRAM when this code is executed; immediately switch to CLKM and
+         * enable PLLP, PLLM, PLLC, PLLA and PLLX.
+         */
+        mov32   r0, TEGRA_CLK_RESET_BASE
+
+        mov     r1, #(1 << 28)
+        str     r1, [r0, #CLK_RESET_SCLK_BURST]
+        str     r1, [r0, #CLK_RESET_CCLK_BURST]
+        mov     r1, #0
+        str     r1, [r0, #CLK_RESET_CCLK_DIVIDER]
+        str     r1, [r0, #CLK_RESET_SCLK_DIVIDER]
+
+        tegra_get_soc_id TEGRA_APB_MISC_BASE, r10
+        cmp     r10, #TEGRA30
+        beq     _no_pll_iddq_exit
+
+        pll_iddq_exit r1, r0, CLK_RESET_PLLM_MISC, CLK_RESET_PLLM_MISC_IDDQ
+        pll_iddq_exit r1, r0, CLK_RESET_PLLC_MISC, CLK_RESET_PLLC_MISC_IDDQ
+        pll_iddq_exit r1, r0, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ
+
+        mov32   r7, TEGRA_TMRUS_BASE
+        ldr     r1, [r7]
+        add     r1, r1, #2
+        wait_until r1, r7, r3
+
+        /* enable PLLM via PMC */
+        mov32   r2, TEGRA_PMC_BASE
+        ldr     r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
+        orr     r1, r1, #(1 << 12)
+        str     r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
+
+        pll_enable r1, r0, CLK_RESET_PLLM_BASE, 0
+        pll_enable r1, r0, CLK_RESET_PLLC_BASE, 0
+        pll_enable r1, r0, CLK_RESET_PLLX_BASE, 0
+
+        b       _pll_m_c_x_done
+
+_no_pll_iddq_exit:
+        /* enable PLLM via PMC */
+        mov32   r2, TEGRA_PMC_BASE
+        ldr     r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
+        orr     r1, r1, #(1 << 12)
+        str     r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
+
+        pll_enable r1, r0, CLK_RESET_PLLM_BASE, CLK_RESET_PLLM_MISC
+        pll_enable r1, r0, CLK_RESET_PLLC_BASE, CLK_RESET_PLLC_MISC
+        pll_enable r1, r0, CLK_RESET_PLLX_BASE, CLK_RESET_PLLX_MISC
+
+_pll_m_c_x_done:
+        pll_enable r1, r0, CLK_RESET_PLLP_BASE, CLK_RESET_PLLP_MISC
+        pll_enable r1, r0, CLK_RESET_PLLA_BASE, CLK_RESET_PLLA_MISC
+
+        pll_locked r1, r0, CLK_RESET_PLLM_BASE
+        pll_locked r1, r0, CLK_RESET_PLLP_BASE
+        pll_locked r1, r0, CLK_RESET_PLLA_BASE
+        pll_locked r1, r0, CLK_RESET_PLLC_BASE
+        pll_locked r1, r0, CLK_RESET_PLLX_BASE
+
+        mov32   r7, TEGRA_TMRUS_BASE
+        ldr     r1, [r7]
+        add     r1, r1, #LOCK_DELAY
+        wait_until r1, r7, r3
+
+        adr     r5, tegra30_sdram_pad_save
+
+        ldr     r4, [r5, #0x18]         @ restore CLK_SOURCE_MSELECT
+        str     r4, [r0, #CLK_RESET_CLK_SOURCE_MSELECT]
+
+        ldr     r4, [r5, #0x1C]         @ restore SCLK_BURST
+        str     r4, [r0, #CLK_RESET_SCLK_BURST]
+
+        cmp     r10, #TEGRA30
+        movweq  r4, #:lower16:((1 << 28) | (0x8))       @ burst policy is PLLX
+        movteq  r4, #:upper16:((1 << 28) | (0x8))
+        movwne  r4, #:lower16:((1 << 28) | (0xe))
+        movtne  r4, #:upper16:((1 << 28) | (0xe))
+        str     r4, [r0, #CLK_RESET_CCLK_BURST]
+
+        /* Restore pad power state to normal */
+        ldr     r1, [r5, #0x14]         @ PMC_IO_DPD_STATUS
+        mvn     r1, r1
+        bic     r1, r1, #(1 << 31)
+        orr     r1, r1, #(1 << 30)
+        str     r1, [r2, #PMC_IO_DPD_REQ]       @ DPD_OFF
+
+        cmp     r10, #TEGRA30
+        movweq  r0, #:lower16:TEGRA_EMC_BASE    @ r0 reserved for emc base
+        movteq  r0, #:upper16:TEGRA_EMC_BASE
+        movwne  r0, #:lower16:TEGRA_EMC0_BASE
+        movtne  r0, #:upper16:TEGRA_EMC0_BASE
+
+exit_self_refresh:
+        ldr     r1, [r5, #0xC]          @ restore EMC_XM2VTTGENPADCTRL
+        str     r1, [r0, #EMC_XM2VTTGENPADCTRL]
+        ldr     r1, [r5, #0x10]         @ restore EMC_XM2VTTGENPADCTRL2
+        str     r1, [r0, #EMC_XM2VTTGENPADCTRL2]
+        ldr     r1, [r5, #0x8]          @ restore EMC_AUTO_CAL_INTERVAL
+        str     r1, [r0, #EMC_AUTO_CAL_INTERVAL]
+
+        /* Relock DLL */
+        ldr     r1, [r0, #EMC_CFG_DIG_DLL]
+        orr     r1, r1, #(1 << 30)      @ set DLL_RESET
+        str     r1, [r0, #EMC_CFG_DIG_DLL]
+
+        emc_timing_update r1, r0
+
+        cmp     r10, #TEGRA114
+        movweq  r1, #:lower16:TEGRA_EMC1_BASE
+        movteq  r1, #:upper16:TEGRA_EMC1_BASE
+        cmpeq   r0, r1
+
+        ldr     r1, [r0, #EMC_AUTO_CAL_CONFIG]
+        orr     r1, r1, #(1 << 31)      @ set AUTO_CAL_ACTIVE
+        orreq   r1, r1, #(1 << 27)      @ set slave mode for channel 1
+        str     r1, [r0, #EMC_AUTO_CAL_CONFIG]
+
+emc_wait_auto_cal_onetime:
+        ldr     r1, [r0, #EMC_AUTO_CAL_STATUS]
+        tst     r1, #(1 << 31)          @ wait until AUTO_CAL_ACTIVE is cleared
+        bne     emc_wait_auto_cal_onetime
+
+        ldr     r1, [r0, #EMC_CFG]
+        bic     r1, r1, #(1 << 31)      @ disable DRAM_CLK_STOP_PD
+        str     r1, [r0, #EMC_CFG]
+
+        mov     r1, #0
+        str     r1, [r0, #EMC_SELF_REF] @ take DRAM out of self refresh
+        mov     r1, #1
+        cmp     r10, #TEGRA30
+        streq   r1, [r0, #EMC_NOP]
+        streq   r1, [r0, #EMC_NOP]
+        streq   r1, [r0, #EMC_REFRESH]
+
+        emc_device_mask r1, r0
+
+exit_selfrefresh_loop:
+        ldr     r2, [r0, #EMC_EMC_STATUS]
+        ands    r2, r2, r1
+        bne     exit_selfrefresh_loop
+
+        lsr     r1, r1, #8              @ devSel, bit0:dev0, bit1:dev1
+
+        mov32   r7, TEGRA_TMRUS_BASE
+        ldr     r2, [r0, #EMC_FBIO_CFG5]
+
+        and     r2, r2, #3              @ check DRAM_TYPE
+        cmp     r2, #2
+        beq     emc_lpddr2
+
+        /* Issue a ZQ_CAL for dev0 - DDR3 */
+        mov32   r2, 0x80000011          @ DEV_SELECTION=2, LENGTH=LONG, CMD=1
+        str     r2, [r0, #EMC_ZQ_CAL]
+        ldr     r2, [r7]
+        add     r2, r2, #10
+        wait_until r2, r7, r3
+
+        tst     r1, #2
+        beq     zcal_done
+
+        /* Issue a ZQ_CAL for dev1 - DDR3 */
+        mov32   r2, 0x40000011          @ DEV_SELECTION=1, LENGTH=LONG, CMD=1
+        str     r2, [r0, #EMC_ZQ_CAL]
+        ldr     r2, [r7]
+        add     r2, r2, #10
+        wait_until r2, r7, r3
+        b       zcal_done
+
+emc_lpddr2:
+        /* Issue a ZQ_CAL for dev0 - LPDDR2 */
+        mov32   r2, 0x800A00AB          @ DEV_SELECTION=2, MA=10, OP=0xAB
+        str     r2, [r0, #EMC_MRW]
+        ldr     r2, [r7]
+        add     r2, r2, #1
+        wait_until r2, r7, r3
+
+        tst     r1, #2
+        beq     zcal_done
+
+        /* Issue a ZQ_CAL for dev0 - LPDDR2 */
+        mov32   r2, 0x400A00AB          @ DEV_SELECTION=1, MA=10, OP=0xAB
+        str     r2, [r0, #EMC_MRW]
+        ldr     r2, [r7]
+        add     r2, r2, #1
+        wait_until r2, r7, r3
+
+zcal_done:
+        mov     r1, #0                  @ unstall all transactions
+        str     r1, [r0, #EMC_REQ_CTRL]
+        ldr     r1, [r5, #0x4]          @ restore EMC_ZCAL_INTERVAL
+        str     r1, [r0, #EMC_ZCAL_INTERVAL]
+        ldr     r1, [r5, #0x0]          @ restore EMC_CFG
+        str     r1, [r0, #EMC_CFG]
+
+        /* Tegra114 had dual EMC channel, now config the other one */
+        cmp     r10, #TEGRA114
+        bne     __no_dual_emc_chanl
+        mov32   r1, TEGRA_EMC1_BASE
+        cmp     r0, r1
+        movne   r0, r1
+        addne   r5, r5, #0x20
+        bne     exit_self_refresh
+__no_dual_emc_chanl:
+
+        mov32   r0, TEGRA_PMC_BASE
+        ldr     r0, [r0, #PMC_SCRATCH41]
+        mov     pc, r0                  @ jump to tegra_resume
+ENDPROC(tegra30_lp1_reset)
+
+        .align  L1_CACHE_SHIFT
+tegra30_sdram_pad_address:
+        .word   TEGRA_EMC_BASE + EMC_CFG                                @0x0
+        .word   TEGRA_EMC_BASE + EMC_ZCAL_INTERVAL                      @0x4
+        .word   TEGRA_EMC_BASE + EMC_AUTO_CAL_INTERVAL                  @0x8
+        .word   TEGRA_EMC_BASE + EMC_XM2VTTGENPADCTRL                   @0xc
+        .word   TEGRA_EMC_BASE + EMC_XM2VTTGENPADCTRL2                  @0x10
+        .word   TEGRA_PMC_BASE + PMC_IO_DPD_STATUS                      @0x14
+        .word   TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT     @0x18
+        .word   TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST             @0x1c
+
+tegra114_sdram_pad_address:
+        .word   TEGRA_EMC0_BASE + EMC_CFG                               @0x0
+        .word   TEGRA_EMC0_BASE + EMC_ZCAL_INTERVAL                     @0x4
+        .word   TEGRA_EMC0_BASE + EMC_AUTO_CAL_INTERVAL                 @0x8
+        .word   TEGRA_EMC0_BASE + EMC_XM2VTTGENPADCTRL                  @0xc
+        .word   TEGRA_EMC0_BASE + EMC_XM2VTTGENPADCTRL2                 @0x10
+        .word   TEGRA_PMC_BASE + PMC_IO_DPD_STATUS                      @0x14
+        .word   TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT     @0x18
+        .word   TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST             @0x1c
+        .word   TEGRA_EMC1_BASE + EMC_CFG                               @0x20
+        .word   TEGRA_EMC1_BASE + EMC_ZCAL_INTERVAL                     @0x24
+        .word   TEGRA_EMC1_BASE + EMC_AUTO_CAL_INTERVAL                 @0x28
+        .word   TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL                  @0x2c
+        .word   TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL2                 @0x30
+
+tegra30_sdram_pad_size:
+        .word   tegra114_sdram_pad_address - tegra30_sdram_pad_address
+
+tegra114_sdram_pad_size:
+        .word   tegra30_sdram_pad_size - tegra114_sdram_pad_address
+
+        .type   tegra30_sdram_pad_save, %object
+tegra30_sdram_pad_save:
+        .rept (tegra30_sdram_pad_size - tegra114_sdram_pad_address) / 4
+        .long   0
+        .endr
+
+/*
+ * tegra30_tear_down_core
+ *
+ * copied into and executed from IRAM
+ * puts memory in self-refresh for LP0 and LP1
+ */
+tegra30_tear_down_core:
+        bl      tegra30_sdram_self_refresh
+        bl      tegra30_switch_cpu_to_clk32k
+        b       tegra30_enter_sleep
+
+/*
+ * tegra30_switch_cpu_to_clk32k
+ *
+ * In LP0 and LP1 all PLLs will be turned off. Switching the CPU and System CLK
+ * to the 32KHz clock.
+ * r4 = TEGRA_PMC_BASE
+ * r5 = TEGRA_CLK_RESET_BASE
+ * r6 = TEGRA_FLOW_CTRL_BASE
+ * r7 = TEGRA_TMRUS_BASE
+ * r10= SoC ID
+ */
+tegra30_switch_cpu_to_clk32k:
+        /*
+         * start by jumping to CLKM to safely disable PLLs, then jump to
+         * CLKS.
+         */
+        mov     r0, #(1 << 28)
+        str     r0, [r5, #CLK_RESET_SCLK_BURST]
+        /* 2uS delay delay between changing SCLK and CCLK */
+        ldr     r1, [r7]
+        add     r1, r1, #2
+        wait_until r1, r7, r9
+        str     r0, [r5, #CLK_RESET_CCLK_BURST]
+        mov     r0, #0
+        str     r0, [r5, #CLK_RESET_CCLK_DIVIDER]
+        str     r0, [r5, #CLK_RESET_SCLK_DIVIDER]
+
+        /* switch the clock source of mselect to be CLK_M */
+        ldr     r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT]
+        orr     r0, r0, #MSELECT_CLKM
+        str     r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT]
+
+        /* 2uS delay delay between changing SCLK and disabling PLLs */
+        ldr     r1, [r7]
+        add     r1, r1, #2
+        wait_until r1, r7, r9
+
+        /* disable PLLM via PMC in LP1 */
+        ldr     r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
+        bic     r0, r0, #(1 << 12)
+        str     r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
+
+        /* disable PLLP, PLLA, PLLC and PLLX */
+        ldr     r0, [r5, #CLK_RESET_PLLP_BASE]
+        bic     r0, r0, #(1 << 30)
+        str     r0, [r5, #CLK_RESET_PLLP_BASE]
+        ldr     r0, [r5, #CLK_RESET_PLLA_BASE]
+        bic     r0, r0, #(1 << 30)
+        str     r0, [r5, #CLK_RESET_PLLA_BASE]
+        ldr     r0, [r5, #CLK_RESET_PLLC_BASE]
+        bic     r0, r0, #(1 << 30)
+        str     r0, [r5, #CLK_RESET_PLLC_BASE]
+        ldr     r0, [r5, #CLK_RESET_PLLX_BASE]
+        bic     r0, r0, #(1 << 30)
+        str     r0, [r5, #CLK_RESET_PLLX_BASE]
+
+        cmp     r10, #TEGRA30
+        beq     _no_pll_in_iddq
+        pll_iddq_entry r1, r5, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ
+_no_pll_in_iddq:
+
+        /* switch to CLKS */
+        mov     r0, #0  /* brust policy = 32KHz */
+        str     r0, [r5, #CLK_RESET_SCLK_BURST]
+
+        mov     pc, lr
+
 /*
  * tegra30_enter_sleep
  *
@@ -172,8 +660,12 @@ tegra30_enter_sleep:
         orr     r0, r0, #FLOW_CTRL_CSR_ENABLE
         str     r0, [r6, r2]
 
+        tegra_get_soc_id TEGRA_APB_MISC_BASE, r10
+        cmp     r10, #TEGRA30
         mov     r0, #FLOW_CTRL_WAIT_FOR_INTERRUPT
-        orr     r0, r0, #FLOW_CTRL_HALT_CPU_IRQ | FLOW_CTRL_HALT_CPU_FIQ
+        orreq   r0, r0, #FLOW_CTRL_HALT_CPU_IRQ | FLOW_CTRL_HALT_CPU_FIQ
+        orrne   r0, r0, #FLOW_CTRL_HALT_LIC_IRQ | FLOW_CTRL_HALT_LIC_FIQ
+
         cpu_to_halt_reg r2, r1
         str     r0, [r6, r2]
         dsb
@@ -187,4 +679,126 @@ halted:
         /* !!!FIXME!!! Implement halt failure handler */
         b       halted
 
+/*
+ * tegra30_sdram_self_refresh
+ *
+ * called with MMU off and caches disabled
+ * must be executed from IRAM
+ * r4 = TEGRA_PMC_BASE
+ * r5 = TEGRA_CLK_RESET_BASE
+ * r6 = TEGRA_FLOW_CTRL_BASE
+ * r7 = TEGRA_TMRUS_BASE
+ * r10= SoC ID
+ */
+tegra30_sdram_self_refresh:
+
+        adr     r8, tegra30_sdram_pad_save
+        tegra_get_soc_id TEGRA_APB_MISC_BASE, r10
+        cmp     r10, #TEGRA30
+        adreq   r2, tegra30_sdram_pad_address
+        ldreq   r3, tegra30_sdram_pad_size
+        adrne   r2, tegra114_sdram_pad_address
+        ldrne   r3, tegra114_sdram_pad_size
+        mov     r9, #0
+
+padsave:
+        ldr     r0, [r2, r9]            @ r0 is the addr in the pad_address
+
+        ldr     r1, [r0]
+        str     r1, [r8, r9]            @ save the content of the addr
+
+        add     r9, r9, #4
+        cmp     r3, r9
+        bne     padsave
+padsave_done:
+
+        dsb
+
+        cmp     r10, #TEGRA30
+        ldreq   r0, =TEGRA_EMC_BASE     @ r0 reserved for emc base addr
+        ldrne   r0, =TEGRA_EMC0_BASE
+
+enter_self_refresh:
+        cmp     r10, #TEGRA30
+        mov     r1, #0
+        str     r1, [r0, #EMC_ZCAL_INTERVAL]
+        str     r1, [r0, #EMC_AUTO_CAL_INTERVAL]
+        ldr     r1, [r0, #EMC_CFG]
+        bic     r1, r1, #(1 << 28)
+        bicne   r1, r1, #(1 << 29)
+        str     r1, [r0, #EMC_CFG]      @ disable DYN_SELF_REF
+
+        emc_timing_update r1, r0
+
+        ldr     r1, [r7]
+        add     r1, r1, #5
+        wait_until r1, r7, r2
+
+emc_wait_auto_cal:
+        ldr     r1, [r0, #EMC_AUTO_CAL_STATUS]
+        tst     r1, #(1 << 31)          @ wait until AUTO_CAL_ACTIVE is cleared
+        bne     emc_wait_auto_cal
+
+        mov     r1, #3
+        str     r1, [r0, #EMC_REQ_CTRL] @ stall incoming DRAM requests
+
+emcidle:
+        ldr     r1, [r0, #EMC_EMC_STATUS]
+        tst     r1, #4
+        beq     emcidle
+
+        mov     r1, #1
+        str     r1, [r0, #EMC_SELF_REF]
+
+        emc_device_mask r1, r0
+
+emcself:
+        ldr     r2, [r0, #EMC_EMC_STATUS]
+        and     r2, r2, r1
+        cmp     r2, r1
+        bne     emcself                 @ loop until DDR in self-refresh
+
+        /* Put VTTGEN in the lowest power mode */
+        ldr     r1, [r0, #EMC_XM2VTTGENPADCTRL]
+        mov32   r2, 0xF8F8FFFF  @ clear XM2VTTGEN_DRVUP and XM2VTTGEN_DRVDN
+        and     r1, r1, r2
+        str     r1, [r0, #EMC_XM2VTTGENPADCTRL]
+        ldr     r1, [r0, #EMC_XM2VTTGENPADCTRL2]
+        cmp     r10, #TEGRA30
+        orreq   r1, r1, #7              @ set E_NO_VTTGEN
+        orrne   r1, r1, #0x3f
+        str     r1, [r0, #EMC_XM2VTTGENPADCTRL2]
+
+        emc_timing_update r1, r0
+
+        /* Tegra114 had dual EMC channel, now config the other one */
+        cmp     r10, #TEGRA114
+        bne     no_dual_emc_chanl
+        mov32   r1, TEGRA_EMC1_BASE
+        cmp     r0, r1
+        movne   r0, r1
+        bne     enter_self_refresh
+no_dual_emc_chanl:
+
+        ldr     r1, [r4, #PMC_CTRL]
+        tst     r1, #PMC_CTRL_SIDE_EFFECT_LP0
+        bne     pmc_io_dpd_skip
+        /*
+         * Put DDR_DATA, DISC_ADDR_CMD, DDR_ADDR_CMD, POP_ADDR_CMD, POP_CLK
+         * and COMP in the lowest power mode when LP1.
+         */
+        mov32   r1, 0x8EC00000
+        str     r1, [r4, #PMC_IO_DPD_REQ]
+pmc_io_dpd_skip:
+
+        dsb
+
+        mov     pc, lr
+
+        .ltorg
+/* dummy symbol for end of IRAM */
+        .align L1_CACHE_SHIFT
+        .global tegra30_iram_end
+tegra30_iram_end:
+        b       .
 #endif
diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S
index 9daaef26b0f6..8d06213fbc47 100644
--- a/arch/arm/mach-tegra/sleep.S
+++ b/arch/arm/mach-tegra/sleep.S
@@ -56,7 +56,9 @@ ENTRY(tegra_disable_clean_inv_dcache)
         isb
 
         /* Flush the D-cache */
-        bl      v7_flush_dcache_louis
+        cmp     r0, #TEGRA_FLUSH_CACHE_ALL
+        blne    v7_flush_dcache_louis
+        bleq    v7_flush_dcache_all
 
         /* Trun off coherency */
         exit_smp r4, r5
@@ -67,15 +69,40 @@ ENDPROC(tegra_disable_clean_inv_dcache)
 
 #ifdef CONFIG_PM_SLEEP
 /*
+ * tegra_init_l2_for_a15
+ *
+ * set up the correct L2 cache data RAM latency
+ */
+ENTRY(tegra_init_l2_for_a15)
+        mrc     p15, 0, r0, c0, c0, 5
+        ubfx    r0, r0, #8, #4
+        tst     r0, #1                          @ only need for cluster 0
+        bne     _exit_init_l2_a15
+
+        mrc     p15, 0x1, r0, c9, c0, 2
+        and     r0, r0, #7
+        cmp     r0, #2
+        bicne   r0, r0, #7
+        orrne   r0, r0, #2
+        mcrne   p15, 0x1, r0, c9, c0, 2
+_exit_init_l2_a15:
+
+        mov     pc, lr
+ENDPROC(tegra_init_l2_for_a15)
+
+/*
  * tegra_sleep_cpu_finish(unsigned long v2p)
  *
  * enters suspend in LP2 by turning off the mmu and jumping to
  * tegra?_tear_down_cpu
  */
 ENTRY(tegra_sleep_cpu_finish)
+        mov     r4, r0
         /* Flush and disable the L1 data cache */
+        mov     r0, #TEGRA_FLUSH_CACHE_ALL
         bl      tegra_disable_clean_inv_dcache
 
+        mov     r0, r4
         mov32   r6, tegra_tear_down_cpu
         ldr     r1, [r6]
         add     r1, r1, r0
@@ -107,10 +134,10 @@ ENTRY(tegra_shut_off_mmu)
 #ifdef CONFIG_CACHE_L2X0
         /* Disable L2 cache */
         check_cpu_part_num 0xc09, r9, r10
-        movweq  r4, #:lower16:(TEGRA_ARM_PERIF_BASE + 0x3000)
-        movteq  r4, #:upper16:(TEGRA_ARM_PERIF_BASE + 0x3000)
-        moveq   r5, #0
-        streq   r5, [r4, #L2X0_CTRL]
+        movweq  r2, #:lower16:(TEGRA_ARM_PERIF_BASE + 0x3000)
+        movteq  r2, #:upper16:(TEGRA_ARM_PERIF_BASE + 0x3000)
+        moveq   r3, #0
+        streq   r3, [r2, #L2X0_CTRL]
 #endif
         mov     pc, r0
 ENDPROC(tegra_shut_off_mmu)
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
index 98b7da698f2b..a4edbb3abd3d 100644
--- a/arch/arm/mach-tegra/sleep.h
+++ b/arch/arm/mach-tegra/sleep.h
@@ -41,7 +41,19 @@
 #define CPU_NOT_RESETTABLE      0
 #endif
 
+/* flag of tegra_disable_clean_inv_dcache to do LoUIS or all */
+#define TEGRA_FLUSH_CACHE_LOUIS 0
+#define TEGRA_FLUSH_CACHE_ALL   1
+
 #ifdef __ASSEMBLY__
+/* waits until the microsecond counter (base) is > rn */
+.macro wait_until, rn, base, tmp
+        add     \rn, \rn, #1
+1001:   ldr     \tmp, [\base]
+        cmp     \tmp, \rn
+        bmi     1001b
+.endm
+
 /* returns the offset of the flow controller halt register for a cpu */
 .macro cpu_to_halt_reg rd, rcpu
         cmp     \rcpu, #0
@@ -144,7 +156,7 @@ void tegra_pen_lock(void);
 void tegra_pen_unlock(void);
 void tegra_resume(void);
 int tegra_sleep_cpu_finish(unsigned long);
-void tegra_disable_clean_inv_dcache(void);
+void tegra_disable_clean_inv_dcache(u32 flag);
 
 #ifdef CONFIG_HOTPLUG_CPU
 void tegra20_hotplug_shutdown(void);
diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c
index fc97cfd52769..5b8605547a09 100644
--- a/arch/arm/mach-tegra/tegra.c
+++ b/arch/arm/mach-tegra/tegra.c
@@ -80,28 +80,6 @@ out:
         of_platform_populate(NULL, of_default_bus_match_table, NULL, parent);
 }
 
-static void __init trimslice_init(void)
-{
-#ifdef CONFIG_TEGRA_PCI
-        int ret;
-
-        ret = tegra_pcie_init(true, true);
-        if (ret)
-                pr_err("tegra_pci_init() failed: %d\n", ret);
-#endif
-}
-
-static void __init harmony_init(void)
-{
-#ifdef CONFIG_TEGRA_PCI
-        int ret;
-
-        ret = harmony_pcie_init();
-        if (ret)
-                pr_err("harmony_pcie_init() failed: %d\n", ret);
-#endif
-}
-
 static void __init paz00_init(void)
 {
         if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
@@ -112,8 +90,6 @@ static struct {
         char *machine;
         void (*init)(void);
 } board_init_funcs[] = {
-        { "compulab,trimslice", trimslice_init },
-        { "nvidia,harmony", harmony_init },
         { "compal,paz00", paz00_init },
 };
 
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index df5d27a532e9..4e7ab3a0dd60 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -42,7 +42,6 @@
 #include <linux/platform_data/dma-ste-dma40.h>
 
 #include <asm/mach-types.h>
-#include <asm/mach/arch.h>
 
 #include "setup.h"
 #include "devices.h"
@@ -686,6 +685,7 @@ MACHINE_START(U8500, "ST-Ericsson MOP500 platform")
         .init_time      = ux500_timer_init,
         .init_machine   = mop500_init_machine,
         .init_late      = ux500_init_late,
+        .restart        = ux500_restart,
 MACHINE_END
 
 MACHINE_START(U8520, "ST-Ericsson U8520 Platform HREFP520")
@@ -695,6 +695,7 @@ MACHINE_START(U8520, "ST-Ericsson U8520 Platform HREFP520")
         .init_time      = ux500_timer_init,
         .init_machine   = mop500_init_machine,
         .init_late      = ux500_init_late,
+        .restart        = ux500_restart,
 MACHINE_END
 
 MACHINE_START(HREFV60, "ST-Ericsson U8500 Platform HREFv60+")
@@ -705,6 +706,7 @@ MACHINE_START(HREFV60, "ST-Ericsson U8500 Platform HREFv60+")
         .init_time      = ux500_timer_init,
         .init_machine   = hrefv60_init_machine,
         .init_late      = ux500_init_late,
+        .restart        = ux500_restart,
 MACHINE_END
 
 MACHINE_START(SNOWBALL, "Calao Systems Snowball platform")
@@ -716,4 +718,5 @@ MACHINE_START(SNOWBALL, "Calao Systems Snowball platform")
         .init_time      = ux500_timer_init,
         .init_machine   = snowball_init_machine,
         .init_late      = NULL,
+        .restart        = ux500_restart,
 MACHINE_END
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 2061b6a2a766..bfaf95d22cbb 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -26,7 +26,6 @@
 
 #include <asm/pmu.h>
 #include <asm/mach/map.h>
-#include <asm/mach/arch.h>
 
 #include "setup.h"
 #include "devices.h"
@@ -325,6 +324,7 @@ DT_MACHINE_START(U8500_DT, "ST-Ericsson Ux5x0 platform (Device Tree Support)")
         .init_machine   = u8500_init_machine,
         .init_late      = NULL,
         .dt_compat      = stericsson_dt_platform_compat,
+        .restart        = ux500_restart,
 MACHINE_END
 
 #endif
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index e6fb0239151b..5d7eebcabc63 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -31,6 +31,14 @@
 #include "db8500-regs.h"
 #include "id.h"
 
+void ux500_restart(enum reboot_mode mode, const char *cmd)
+{
+        local_irq_disable();
+        local_fiq_disable();
+
+        prcmu_system_reset(0);
+}
+
 /*
  * FIXME: Should we set up the GPIO domain here?
  *
diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c
index 516a6f57d159..bc316062e0c2 100644
--- a/arch/arm/mach-ux500/devices-db8500.c
+++ b/arch/arm/mach-ux500/devices-db8500.c
@@ -49,6 +49,7 @@ struct stedma40_platform_data dma40_plat_data = {
 struct platform_device u8500_dma40_device = {
         .dev = {
                 .platform_data = &dma40_plat_data,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
         },
         .name = "dma40",
         .id = 0,
diff --git a/arch/arm/mach-ux500/headsmp.S b/arch/arm/mach-ux500/headsmp.S
index 08da5589bcd8..9cdea049485d 100644
--- a/arch/arm/mach-ux500/headsmp.S
+++ b/arch/arm/mach-ux500/headsmp.S
@@ -11,8 +11,6 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
 
-        __INIT
-
 /*
  * U8500 specific entry point for secondary CPUs.
  */
diff --git a/arch/arm/mach-ux500/setup.h b/arch/arm/mach-ux500/setup.h
index cad3ca86c540..656324aad18e 100644
--- a/arch/arm/mach-ux500/setup.h
+++ b/arch/arm/mach-ux500/setup.h
@@ -11,10 +11,13 @@
 #ifndef __ASM_ARCH_SETUP_H
 #define __ASM_ARCH_SETUP_H
 
+#include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <linux/init.h>
 #include <linux/mfd/abx500/ab8500.h>
 
+void ux500_restart(enum reboot_mode mode, const char *cmd);
+
 void __init ux500_map_io(void);
 extern void __init u8500_map_io(void);
 
diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
index 83c8677bb181..365795447804 100644
--- a/arch/arm/mach-vexpress/Kconfig
+++ b/arch/arm/mach-vexpress/Kconfig
@@ -66,4 +66,12 @@ config ARCH_VEXPRESS_DCSCB
           This is needed to provide CPU and cluster power management
           on RTSM implementing big.LITTLE.
 
+config ARCH_VEXPRESS_TC2_PM
+        bool "Versatile Express TC2 power management"
+        depends on MCPM
+        select ARM_CCI
+        help
+          Support for CPU and cluster power management on Versatile Express
+          with a TC2 (A15x2 A7x3) big.LITTLE core tile.
+
 endmenu
diff --git a/arch/arm/mach-vexpress/Makefile b/arch/arm/mach-vexpress/Makefile
index 48ba89a8149f..36ea8247123a 100644
--- a/arch/arm/mach-vexpress/Makefile
+++ b/arch/arm/mach-vexpress/Makefile
@@ -7,5 +7,6 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
 obj-y                                   := v2m.o
 obj-$(CONFIG_ARCH_VEXPRESS_CA9X4)       += ct-ca9x4.o
 obj-$(CONFIG_ARCH_VEXPRESS_DCSCB)       += dcscb.o      dcscb_setup.o
+obj-$(CONFIG_ARCH_VEXPRESS_TC2_PM)      += tc2_pm.o spc.o
 obj-$(CONFIG_SMP)                       += platsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
diff --git a/arch/arm/mach-vexpress/dcscb.c b/arch/arm/mach-vexpress/dcscb.c
index 16d57a8a9d5a..3a6384c6c435 100644
--- a/arch/arm/mach-vexpress/dcscb.c
+++ b/arch/arm/mach-vexpress/dcscb.c
@@ -136,14 +136,35 @@ static void dcscb_power_down(void)
                 /*
                  * Flush all cache levels for this cluster.
                  *
-                 * A15/A7 can hit in the cache with SCTLR.C=0, so we don't need
-                 * a preliminary flush here for those CPUs.  At least, that's
-                 * the theory -- without the extra flush, Linux explodes on
-                 * RTSM (to be investigated).
+                 * To do so we do:
+                 * - Clear the SCTLR.C bit to prevent further cache allocations
+                 * - Flush the whole cache
+                 * - Clear the ACTLR "SMP" bit to disable local coherency
+                 *
+                 * Let's do it in the safest possible way i.e. with
+                 * no memory access within the following sequence
+                 * including to the stack.
+                 *
+                 * Note: fp is preserved to the stack explicitly prior doing
+                 * this since adding it to the clobber list is incompatible
+                 * with having CONFIG_FRAME_POINTER=y.
                  */
-                flush_cache_all();
-                set_cr(get_cr() & ~CR_C);
-                flush_cache_all();
+                asm volatile(
+                "str    fp, [sp, #-4]! \n\t"
+                "mrc    p15, 0, r0, c1, c0, 0   @ get CR \n\t"
+                "bic    r0, r0, #"__stringify(CR_C)" \n\t"
+                "mcr    p15, 0, r0, c1, c0, 0   @ set CR \n\t"
+                "isb    \n\t"
+                "bl     v7_flush_dcache_all \n\t"
+                "clrex  \n\t"
+                "mrc    p15, 0, r0, c1, c0, 1   @ get AUXCR \n\t"
+                "bic    r0, r0, #(1 << 6)       @ disable local coherency \n\t"
+                "mcr    p15, 0, r0, c1, c0, 1   @ set AUXCR \n\t"
+                "isb    \n\t"
+                "dsb    \n\t"
+                "ldr    fp, [sp], #4"
+                : : : "r0","r1","r2","r3","r4","r5","r6","r7",
+                      "r9","r10","lr","memory");
 
                 /*
                  * This is a harmless no-op.  On platforms with a real
@@ -152,9 +173,6 @@ static void dcscb_power_down(void)
                  */
                 outer_flush_all();
 
-                /* Disable local coherency by clearing the ACTLR "SMP" bit: */
-                set_auxcr(get_auxcr() & ~(1 << 6));
-
                 /*
                  * Disable cluster-level coherency by masking
                  * incoming snoops and DVM messages:
@@ -167,18 +185,24 @@ static void dcscb_power_down(void)
 
                 /*
                  * Flush the local CPU cache.
-                 *
-                 * A15/A7 can hit in the cache with SCTLR.C=0, so we don't need
-                 * a preliminary flush here for those CPUs.  At least, that's
-                 * the theory -- without the extra flush, Linux explodes on
-                 * RTSM (to be investigated).
+                 * Let's do it in the safest possible way as above.
                  */
-                flush_cache_louis();
-                set_cr(get_cr() & ~CR_C);
-                flush_cache_louis();
-
-                /* Disable local coherency by clearing the ACTLR "SMP" bit: */
-                set_auxcr(get_auxcr() & ~(1 << 6));
+                asm volatile(
+                "str    fp, [sp, #-4]! \n\t"
+                "mrc    p15, 0, r0, c1, c0, 0   @ get CR \n\t"
+                "bic    r0, r0, #"__stringify(CR_C)" \n\t"
+                "mcr    p15, 0, r0, c1, c0, 0   @ set CR \n\t"
+                "isb    \n\t"
+                "bl     v7_flush_dcache_louis \n\t"
+                "clrex  \n\t"
+                "mrc    p15, 0, r0, c1, c0, 1   @ get AUXCR \n\t"
+                "bic    r0, r0, #(1 << 6)       @ disable local coherency \n\t"
+                "mcr    p15, 0, r0, c1, c0, 1   @ set AUXCR \n\t"
+                "isb    \n\t"
+                "dsb    \n\t"
+                "ldr    fp, [sp], #4"
+                : : : "r0","r1","r2","r3","r4","r5","r6","r7",
+                      "r9","r10","lr","memory");
         }
 
         __mcpm_cpu_down(cpu, cluster);
diff --git a/arch/arm/mach-vexpress/spc.c b/arch/arm/mach-vexpress/spc.c
new file mode 100644
index 000000000000..eefb029197ca
--- /dev/null
+++ b/arch/arm/mach-vexpress/spc.c
@@ -0,0 +1,180 @@
+/*
+ * Versatile Express Serial Power Controller (SPC) support
+ *
+ * Copyright (C) 2013 ARM Ltd.
+ *
+ * Authors: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
+ *          Achin Gupta           <achin.gupta@arm.com>
+ *          Lorenzo Pieralisi     <lorenzo.pieralisi@arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+
+#include <asm/cacheflush.h>
+
+#define SPCLOG "vexpress-spc: "
+
+/* SPC wake-up IRQs status and mask */
+#define WAKE_INT_MASK           0x24
+#define WAKE_INT_RAW            0x28
+#define WAKE_INT_STAT           0x2c
+/* SPC power down registers */
+#define A15_PWRDN_EN            0x30
+#define A7_PWRDN_EN             0x34
+/* SPC per-CPU mailboxes */
+#define A15_BX_ADDR0            0x68
+#define A7_BX_ADDR0             0x78
+
+/* wake-up interrupt masks */
+#define GBL_WAKEUP_INT_MSK      (0x3 << 10)
+
+/* TC2 static dual-cluster configuration */
+#define MAX_CLUSTERS            2
+
+struct ve_spc_drvdata {
+        void __iomem *baseaddr;
+        /*
+         * A15s cluster identifier
+         * It corresponds to A15 processors MPIDR[15:8] bitfield
+         */
+        u32 a15_clusid;
+};
+
+static struct ve_spc_drvdata *info;
+
+static inline bool cluster_is_a15(u32 cluster)
+{
+        return cluster == info->a15_clusid;
+}
+
+/**
+ * ve_spc_global_wakeup_irq()
+ *
+ * Function to set/clear global wakeup IRQs. Not protected by locking since
+ * it might be used in code paths where normal cacheable locks are not
+ * working. Locking must be provided by the caller to ensure atomicity.
+ *
+ * @set: if true, global wake-up IRQs are set, if false they are cleared
+ */
+void ve_spc_global_wakeup_irq(bool set)
+{
+        u32 reg;
+
+        reg = readl_relaxed(info->baseaddr + WAKE_INT_MASK);
+
+        if (set)
+                reg |= GBL_WAKEUP_INT_MSK;
+        else
+                reg &= ~GBL_WAKEUP_INT_MSK;
+
+        writel_relaxed(reg, info->baseaddr + WAKE_INT_MASK);
+}
+
+/**
+ * ve_spc_cpu_wakeup_irq()
+ *
+ * Function to set/clear per-CPU wake-up IRQs. Not protected by locking since
+ * it might be used in code paths where normal cacheable locks are not
+ * working. Locking must be provided by the caller to ensure atomicity.
+ *
+ * @cluster: mpidr[15:8] bitfield describing cluster affinity level
+ * @cpu: mpidr[7:0] bitfield describing cpu affinity level
+ * @set: if true, wake-up IRQs are set, if false they are cleared
+ */
+void ve_spc_cpu_wakeup_irq(u32 cluster, u32 cpu, bool set)
+{
+        u32 mask, reg;
+
+        if (cluster >= MAX_CLUSTERS)
+                return;
+
+        mask = 1 << cpu;
+
+        if (!cluster_is_a15(cluster))
+                mask <<= 4;
+
+        reg = readl_relaxed(info->baseaddr + WAKE_INT_MASK);
+
+        if (set)
+                reg |= mask;
+        else
+                reg &= ~mask;
+
+        writel_relaxed(reg, info->baseaddr + WAKE_INT_MASK);
+}
+
+/**
+ * ve_spc_set_resume_addr() - set the jump address used for warm boot
+ *
+ * @cluster: mpidr[15:8] bitfield describing cluster affinity level
+ * @cpu: mpidr[7:0] bitfield describing cpu affinity level
+ * @addr: physical resume address
+ */
+void ve_spc_set_resume_addr(u32 cluster, u32 cpu, u32 addr)
+{
+        void __iomem *baseaddr;
+
+        if (cluster >= MAX_CLUSTERS)
+                return;
+
+        if (cluster_is_a15(cluster))
+                baseaddr = info->baseaddr + A15_BX_ADDR0 + (cpu << 2);
+        else
+                baseaddr = info->baseaddr + A7_BX_ADDR0 + (cpu << 2);
+
+        writel_relaxed(addr, baseaddr);
+}
+
+/**
+ * ve_spc_powerdown()
+ *
+ * Function to enable/disable cluster powerdown. Not protected by locking
+ * since it might be used in code paths where normal cacheable locks are not
+ * working. Locking must be provided by the caller to ensure atomicity.
+ *
+ * @cluster: mpidr[15:8] bitfield describing cluster affinity level
+ * @enable: if true enables powerdown, if false disables it
+ */
+void ve_spc_powerdown(u32 cluster, bool enable)
+{
+        u32 pwdrn_reg;
+
+        if (cluster >= MAX_CLUSTERS)
+                return;
+
+        pwdrn_reg = cluster_is_a15(cluster) ? A15_PWRDN_EN : A7_PWRDN_EN;
+        writel_relaxed(enable, info->baseaddr + pwdrn_reg);
+}
+
+int __init ve_spc_init(void __iomem *baseaddr, u32 a15_clusid)
+{
+        info = kzalloc(sizeof(*info), GFP_KERNEL);
+        if (!info) {
+                pr_err(SPCLOG "unable to allocate mem\n");
+                return -ENOMEM;
+        }
+
+        info->baseaddr = baseaddr;
+        info->a15_clusid = a15_clusid;
+
+        /*
+         * Multi-cluster systems may need this data when non-coherent, during
+         * cluster power-up/power-down. Make sure driver info reaches main
+         * memory.
+         */
+        sync_cache_w(info);
+        sync_cache_w(&info);
+
+        return 0;
+}
diff --git a/arch/arm/mach-vexpress/spc.h b/arch/arm/mach-vexpress/spc.h
new file mode 100644
index 000000000000..5f7e4a446a17
--- /dev/null
+++ b/arch/arm/mach-vexpress/spc.h
@@ -0,0 +1,24 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Copyright (C) 2012 ARM Limited
+ */
+
+
+#ifndef __SPC_H_
+#define __SPC_H_
+
+int __init ve_spc_init(void __iomem *base, u32 a15_clusid);
+void ve_spc_global_wakeup_irq(bool set);
+void ve_spc_cpu_wakeup_irq(u32 cluster, u32 cpu, bool set);
+void ve_spc_set_resume_addr(u32 cluster, u32 cpu, u32 addr);
+void ve_spc_powerdown(u32 cluster, bool enable);
+
+#endif
diff --git a/arch/arm/mach-vexpress/tc2_pm.c b/arch/arm/mach-vexpress/tc2_pm.c
new file mode 100644
index 000000000000..2b7c93a724ed
--- /dev/null
+++ b/arch/arm/mach-vexpress/tc2_pm.c
@@ -0,0 +1,352 @@
+/*
+ * arch/arm/mach-vexpress/tc2_pm.c - TC2 power management support
+ *
+ * Created by:  Nicolas Pitre, October 2012
+ * Copyright:   (C) 2012-2013  Linaro Limited
+ *
+ * Some portions of this file were originally written by Achin Gupta
+ * Copyright:   (C) 2012  ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/of_address.h>
+#include <linux/spinlock.h>
+#include <linux/errno.h>
+
+#include <asm/mcpm.h>
+#include <asm/proc-fns.h>
+#include <asm/cacheflush.h>
+#include <asm/cputype.h>
+#include <asm/cp15.h>
+
+#include <linux/arm-cci.h>
+
+#include "spc.h"
+
+/* SCC conf registers */
+#define A15_CONF                0x400
+#define A7_CONF                 0x500
+#define SYS_INFO                0x700
+#define SPC_BASE                0xb00
+
+/*
+ * We can't use regular spinlocks. In the switcher case, it is possible
+ * for an outbound CPU to call power_down() after its inbound counterpart
+ * is already live using the same logical CPU number which trips lockdep
+ * debugging.
+ */
+static arch_spinlock_t tc2_pm_lock = __ARCH_SPIN_LOCK_UNLOCKED;
+
+#define TC2_CLUSTERS                    2
+#define TC2_MAX_CPUS_PER_CLUSTER        3
+
+static unsigned int tc2_nr_cpus[TC2_CLUSTERS];
+
+/* Keep per-cpu usage count to cope with unordered up/down requests */
+static int tc2_pm_use_count[TC2_MAX_CPUS_PER_CLUSTER][TC2_CLUSTERS];
+
+#define tc2_cluster_unused(cluster) \
+        (!tc2_pm_use_count[0][cluster] && \
+         !tc2_pm_use_count[1][cluster] && \
+         !tc2_pm_use_count[2][cluster])
+
+static int tc2_pm_power_up(unsigned int cpu, unsigned int cluster)
+{
+        pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+        if (cluster >= TC2_CLUSTERS || cpu >= tc2_nr_cpus[cluster])
+                return -EINVAL;
+
+        /*
+         * Since this is called with IRQs enabled, and no arch_spin_lock_irq
+         * variant exists, we need to disable IRQs manually here.
+         */
+        local_irq_disable();
+        arch_spin_lock(&tc2_pm_lock);
+
+        if (tc2_cluster_unused(cluster))
+                ve_spc_powerdown(cluster, false);
+
+        tc2_pm_use_count[cpu][cluster]++;
+        if (tc2_pm_use_count[cpu][cluster] == 1) {
+                ve_spc_set_resume_addr(cluster, cpu,
+                                       virt_to_phys(mcpm_entry_point));
+                ve_spc_cpu_wakeup_irq(cluster, cpu, true);
+        } else if (tc2_pm_use_count[cpu][cluster] != 2) {
+                /*
+                 * The only possible values are:
+                 * 0 = CPU down
+                 * 1 = CPU (still) up
+                 * 2 = CPU requested to be up before it had a chance
+                 *     to actually make itself down.
+                 * Any other value is a bug.
+                 */
+                BUG();
+        }
+
+        arch_spin_unlock(&tc2_pm_lock);
+        local_irq_enable();
+
+        return 0;
+}
+
+static void tc2_pm_down(u64 residency)
+{
+        unsigned int mpidr, cpu, cluster;
+        bool last_man = false, skip_wfi = false;
+
+        mpidr = read_cpuid_mpidr();
+        cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+        cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+        pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+        BUG_ON(cluster >= TC2_CLUSTERS || cpu >= TC2_MAX_CPUS_PER_CLUSTER);
+
+        __mcpm_cpu_going_down(cpu, cluster);
+
+        arch_spin_lock(&tc2_pm_lock);
+        BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP);
+        tc2_pm_use_count[cpu][cluster]--;
+        if (tc2_pm_use_count[cpu][cluster] == 0) {
+                ve_spc_cpu_wakeup_irq(cluster, cpu, true);
+                if (tc2_cluster_unused(cluster)) {
+                        ve_spc_powerdown(cluster, true);
+                        ve_spc_global_wakeup_irq(true);
+                        last_man = true;
+                }
+        } else if (tc2_pm_use_count[cpu][cluster] == 1) {
+                /*
+                 * A power_up request went ahead of us.
+                 * Even if we do not want to shut this CPU down,
+                 * the caller expects a certain state as if the WFI
+                 * was aborted.  So let's continue with cache cleaning.
+                 */
+                skip_wfi = true;
+        } else
+                BUG();
+
+        if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) {
+                arch_spin_unlock(&tc2_pm_lock);
+
+                if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A15) {
+                        /*
+                         * On the Cortex-A15 we need to disable
+                         * L2 prefetching before flushing the cache.
+                         */
+                        asm volatile(
+                        "mcr    p15, 1, %0, c15, c0, 3 \n\t"
+                        "isb    \n\t"
+                        "dsb    "
+                        : : "r" (0x400) );
+                }
+
+                /*
+                 * We need to disable and flush the whole (L1 and L2) cache.
+                 * Let's do it in the safest possible way i.e. with
+                 * no memory access within the following sequence
+                 * including the stack.
+                 *
+                 * Note: fp is preserved to the stack explicitly prior doing
+                 * this since adding it to the clobber list is incompatible
+                 * with having CONFIG_FRAME_POINTER=y.
+                 */
+                asm volatile(
+                "str    fp, [sp, #-4]! \n\t"
+                "mrc    p15, 0, r0, c1, c0, 0   @ get CR \n\t"
+                "bic    r0, r0, #"__stringify(CR_C)" \n\t"
+                "mcr    p15, 0, r0, c1, c0, 0   @ set CR \n\t"
+                "isb    \n\t"
+                "bl     v7_flush_dcache_all \n\t"
+                "clrex  \n\t"
+                "mrc    p15, 0, r0, c1, c0, 1   @ get AUXCR \n\t"
+                "bic    r0, r0, #(1 << 6)       @ disable local coherency \n\t"
+                "mcr    p15, 0, r0, c1, c0, 1   @ set AUXCR \n\t"
+                "isb    \n\t"
+                "dsb    \n\t"
+                "ldr    fp, [sp], #4"
+                : : : "r0","r1","r2","r3","r4","r5","r6","r7",
+                      "r9","r10","lr","memory");
+
+                cci_disable_port_by_cpu(mpidr);
+
+                __mcpm_outbound_leave_critical(cluster, CLUSTER_DOWN);
+        } else {
+                /*
+                 * If last man then undo any setup done previously.
+                 */
+                if (last_man) {
+                        ve_spc_powerdown(cluster, false);
+                        ve_spc_global_wakeup_irq(false);
+                }
+
+                arch_spin_unlock(&tc2_pm_lock);
+
+                /*
+                 * We need to disable and flush only the L1 cache.
+                 * Let's do it in the safest possible way as above.
+                 */
+                asm volatile(
+                "str    fp, [sp, #-4]! \n\t"
+                "mrc    p15, 0, r0, c1, c0, 0   @ get CR \n\t"
+                "bic    r0, r0, #"__stringify(CR_C)" \n\t"
+                "mcr    p15, 0, r0, c1, c0, 0   @ set CR \n\t"
+                "isb    \n\t"
+                "bl     v7_flush_dcache_louis \n\t"
+                "clrex  \n\t"
+                "mrc    p15, 0, r0, c1, c0, 1   @ get AUXCR \n\t"
+                "bic    r0, r0, #(1 << 6)       @ disable local coherency \n\t"
+                "mcr    p15, 0, r0, c1, c0, 1   @ set AUXCR \n\t"
+                "isb    \n\t"
+                "dsb    \n\t"
+                "ldr    fp, [sp], #4"
+                : : : "r0","r1","r2","r3","r4","r5","r6","r7",
+                      "r9","r10","lr","memory");
+        }
+
+        __mcpm_cpu_down(cpu, cluster);
+
+        /* Now we are prepared for power-down, do it: */
+        if (!skip_wfi)
+                wfi();
+
+        /* Not dead at this point?  Let our caller cope. */
+}
+
+static void tc2_pm_power_down(void)
+{
+        tc2_pm_down(0);
+}
+
+static void tc2_pm_suspend(u64 residency)
+{
+        unsigned int mpidr, cpu, cluster;
+
+        mpidr = read_cpuid_mpidr();
+        cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+        cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+        ve_spc_set_resume_addr(cluster, cpu, virt_to_phys(mcpm_entry_point));
+        tc2_pm_down(residency);
+}
+
+static void tc2_pm_powered_up(void)
+{
+        unsigned int mpidr, cpu, cluster;
+        unsigned long flags;
+
+        mpidr = read_cpuid_mpidr();
+        cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+        cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+        pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+        BUG_ON(cluster >= TC2_CLUSTERS || cpu >= TC2_MAX_CPUS_PER_CLUSTER);
+
+        local_irq_save(flags);
+        arch_spin_lock(&tc2_pm_lock);
+
+        if (tc2_cluster_unused(cluster)) {
+                ve_spc_powerdown(cluster, false);
+                ve_spc_global_wakeup_irq(false);
+        }
+
+        if (!tc2_pm_use_count[cpu][cluster])
+                tc2_pm_use_count[cpu][cluster] = 1;
+
+        ve_spc_cpu_wakeup_irq(cluster, cpu, false);
+        ve_spc_set_resume_addr(cluster, cpu, 0);
+
+        arch_spin_unlock(&tc2_pm_lock);
+        local_irq_restore(flags);
+}
+
+static const struct mcpm_platform_ops tc2_pm_power_ops = {
+        .power_up       = tc2_pm_power_up,
+        .power_down     = tc2_pm_power_down,
+        .suspend        = tc2_pm_suspend,
+        .powered_up     = tc2_pm_powered_up,
+};
+
+static bool __init tc2_pm_usage_count_init(void)
+{
+        unsigned int mpidr, cpu, cluster;
+
+        mpidr = read_cpuid_mpidr();
+        cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+        cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+        pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+        if (cluster >= TC2_CLUSTERS || cpu >= tc2_nr_cpus[cluster]) {
+                pr_err("%s: boot CPU is out of bound!\n", __func__);
+                return false;
+        }
+        tc2_pm_use_count[cpu][cluster] = 1;
+        return true;
+}
+
+/*
+ * Enable cluster-level coherency, in preparation for turning on the MMU.
+ */
+static void __naked tc2_pm_power_up_setup(unsigned int affinity_level)
+{
+        asm volatile (" \n"
+"       cmp     r0, #1 \n"
+"       bxne    lr \n"
+"       b       cci_enable_port_for_self ");
+}
+
+static int __init tc2_pm_init(void)
+{
+        int ret;
+        void __iomem *scc;
+        u32 a15_cluster_id, a7_cluster_id, sys_info;
+        struct device_node *np;
+
+        /*
+         * The power management-related features are hidden behind
+         * SCC registers. We need to extract runtime information like
+         * cluster ids and number of CPUs really available in clusters.
+         */
+        np = of_find_compatible_node(NULL, NULL,
+                        "arm,vexpress-scc,v2p-ca15_a7");
+        scc = of_iomap(np, 0);
+        if (!scc)
+                return -ENODEV;
+
+        a15_cluster_id = readl_relaxed(scc + A15_CONF) & 0xf;
+        a7_cluster_id = readl_relaxed(scc + A7_CONF) & 0xf;
+        if (a15_cluster_id >= TC2_CLUSTERS || a7_cluster_id >= TC2_CLUSTERS)
+                return -EINVAL;
+
+        sys_info = readl_relaxed(scc + SYS_INFO);
+        tc2_nr_cpus[a15_cluster_id] = (sys_info >> 16) & 0xf;
+        tc2_nr_cpus[a7_cluster_id] = (sys_info >> 20) & 0xf;
+
+        /*
+         * A subset of the SCC registers is also used to communicate
+         * with the SPC (power controller). We need to be able to
+         * drive it very early in the boot process to power up
+         * processors, so we initialize the SPC driver here.
+         */
+        ret = ve_spc_init(scc + SPC_BASE, a15_cluster_id);
+        if (ret)
+                return ret;
+
+        if (!cci_probed())
+                return -ENODEV;
+
+        if (!tc2_pm_usage_count_init())
+                return -EINVAL;
+
+        ret = mcpm_platform_register(&tc2_pm_power_ops);
+        if (!ret) {
+                mcpm_sync_init(tc2_pm_power_up_setup);
+                pr_info("TC2 power management initialized\n");
+        }
+        return ret;
+}
+
+early_initcall(tc2_pm_init);
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index f82bae2171eb..436ea97074cd 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -106,7 +106,7 @@ config OMAP_32K_TIMER
           This timer saves power compared to the OMAP_MPU_TIMER, and has
           support for no tick during idle. The 32KHz timer provides less
           intra-tick resolution than OMAP_MPU_TIMER. The 32KHz timer is
-          currently only available for OMAP16XX, 24XX, 34XX and OMAP4/5.
+          currently only available for OMAP16XX, 24XX, 34XX, OMAP4/5 and DRA7XX.
 
           On OMAP2PLUS this value is only used for CONFIG_HZ and
           CLOCK_TICK_RATE compile time calculation.
diff --git a/arch/ia64/Kconfig b/arch/ia64/Kconfig
index 566642266324..a86a56d9e73f 100644
--- a/arch/ia64/Kconfig
+++ b/arch/ia64/Kconfig
@@ -9,7 +9,6 @@ config IA64
         select PCI if (!IA64_HP_SIM)
         select ACPI if (!IA64_HP_SIM)
         select PM if (!IA64_HP_SIM)
-        select ARCH_SUPPORTS_MSI
         select HAVE_UNSTABLE_SCHED_CLOCK
         select HAVE_IDE
         select HAVE_OPROFILE
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index dccd7cec442d..71f15e73bc89 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -727,7 +727,6 @@ config CAVIUM_OCTEON_SOC
         select SYS_HAS_CPU_CAVIUM_OCTEON
         select SWAP_IO_SPACE
         select HW_HAS_PCI
-        select ARCH_SUPPORTS_MSI
         select ZONE_DMA32
         select USB_ARCH_HAS_OHCI
         select USB_ARCH_HAS_EHCI
@@ -763,7 +762,6 @@ config NLM_XLR_BOARD
         select CEVT_R4K
         select CSRC_R4K
         select IRQ_CPU
-        select ARCH_SUPPORTS_MSI
         select ZONE_DMA32 if 64BIT
         select SYNC_R4K
         select SYS_HAS_EARLY_PRINTK
diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h
index fa8e0aa250ca..f194c08bd057 100644
--- a/arch/mips/include/asm/pci.h
+++ b/arch/mips/include/asm/pci.h
@@ -136,11 +136,6 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
         return channel ? 15 : 14;
 }
 
-#ifdef CONFIG_CPU_CAVIUM_OCTEON
-/* MSI arch hook for OCTEON */
-#define arch_setup_msi_irqs arch_setup_msi_irqs
-#endif
-
 extern char * (*pcibios_plat_setup)(char *str);
 
 #ifdef CONFIG_OF
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index a4e3a93bf2d4..6b7530f8183c 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -747,7 +747,6 @@ config PCI
         default y if !40x && !CPM2 && !8xx && !PPC_83xx \
                 && !PPC_85xx && !PPC_86xx && !GAMECUBE_COMMON
         default PCI_QSPAN if !4xx && !CPM2 && 8xx
-        select ARCH_SUPPORTS_MSI
         select GENERIC_PCI_IOMAP
         help
           Find out whether your system includes a PCI bus. PCI is the name of
diff --git a/arch/powerpc/include/asm/pci.h b/arch/powerpc/include/asm/pci.h
index 6653f2743c4e..95145a15c708 100644
--- a/arch/powerpc/include/asm/pci.h
+++ b/arch/powerpc/include/asm/pci.h
@@ -113,11 +113,6 @@ extern int pci_domain_nr(struct pci_bus *bus);
 /* Decide whether to display the domain number in /proc */
 extern int pci_proc_domain(struct pci_bus *bus);
 
-/* MSI arch hooks */
-#define arch_setup_msi_irqs arch_setup_msi_irqs
-#define arch_teardown_msi_irqs arch_teardown_msi_irqs
-#define arch_msi_check_device arch_msi_check_device
-
 struct vm_area_struct;
 /* Map a range of PCI memory or I/O space for a device into user space */
 int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma,
diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig
index 8b7892bf6d8b..c696ad7d3439 100644
--- a/arch/s390/Kconfig
+++ b/arch/s390/Kconfig
@@ -431,7 +431,6 @@ menuconfig PCI
         bool "PCI support"
         default n
         depends on 64BIT
-        select ARCH_SUPPORTS_MSI
         select PCI_MSI
         help
           Enable PCI support.
diff --git a/arch/s390/include/asm/pci.h b/arch/s390/include/asm/pci.h
index c290f13d1c47..1cc185da9d38 100644
--- a/arch/s390/include/asm/pci.h
+++ b/arch/s390/include/asm/pci.h
@@ -22,10 +22,6 @@ void pci_iounmap(struct pci_dev *, void __iomem *);
 int pci_domain_nr(struct pci_bus *);
 int pci_proc_domain(struct pci_bus *);
 
-/* MSI arch hooks */
-#define arch_setup_msi_irqs     arch_setup_msi_irqs
-#define arch_teardown_msi_irqs  arch_teardown_msi_irqs
-
 #define ZPCI_BUS_NR                     0       /* default bus number */
 #define ZPCI_DEVFN                      0       /* default device number */
 
diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig
index a00cbd356db5..1570ad2802b3 100644
--- a/arch/sparc/Kconfig
+++ b/arch/sparc/Kconfig
@@ -52,7 +52,6 @@ config SPARC32
 
 config SPARC64
         def_bool 64BIT
-        select ARCH_SUPPORTS_MSI
         select HAVE_FUNCTION_TRACER
         select HAVE_FUNCTION_GRAPH_TRACER
         select HAVE_FUNCTION_GRAPH_FP_TEST
diff --git a/arch/tile/Kconfig b/arch/tile/Kconfig
index 6e1ed55f6cfc..932fa14de5fe 100644
--- a/arch/tile/Kconfig
+++ b/arch/tile/Kconfig
@@ -395,7 +395,6 @@ config PCI
         select PCI_DOMAINS
         select GENERIC_PCI_IOMAP
         select TILE_GXIO_TRIO if TILEGX
-        select ARCH_SUPPORTS_MSI if TILEGX
         select PCI_MSI if TILEGX
         ---help---
           Enable PCI root complex support, so PCIe endpoint devices can
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 5c0ed72c02a2..30c40f08a3d4 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -2032,7 +2032,6 @@ menu "Bus options (PCI etc.)"
 config PCI
         bool "PCI support"
         default y
-        select ARCH_SUPPORTS_MSI if (X86_LOCAL_APIC && X86_IO_APIC)
         ---help---
           Find out whether you have a PCI motherboard. PCI is the name of a
           bus system, i.e. the way the CPU talks to the other stuff inside
diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h
index d9e9e6c7ed32..7d7443283a9d 100644
--- a/arch/x86/include/asm/pci.h
+++ b/arch/x86/include/asm/pci.h
@@ -100,29 +100,6 @@ static inline void early_quirks(void) { }
 extern void pci_iommu_alloc(void);
 
 #ifdef CONFIG_PCI_MSI
-/* MSI arch specific hooks */
-static inline int x86_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
-{
-        return x86_msi.setup_msi_irqs(dev, nvec, type);
-}
-
-static inline void x86_teardown_msi_irqs(struct pci_dev *dev)
-{
-        x86_msi.teardown_msi_irqs(dev);
-}
-
-static inline void x86_teardown_msi_irq(unsigned int irq)
-{
-        x86_msi.teardown_msi_irq(irq);
-}
-static inline void x86_restore_msi_irqs(struct pci_dev *dev, int irq)
-{
-        x86_msi.restore_msi_irqs(dev, irq);
-}
-#define arch_setup_msi_irqs x86_setup_msi_irqs
-#define arch_teardown_msi_irqs x86_teardown_msi_irqs
-#define arch_teardown_msi_irq x86_teardown_msi_irq
-#define arch_restore_msi_irqs x86_restore_msi_irqs
 /* implemented in arch/x86/kernel/apic/io_apic. */
 struct msi_desc;
 int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type);
@@ -130,16 +107,9 @@ void native_teardown_msi_irq(unsigned int irq);
 void native_restore_msi_irqs(struct pci_dev *dev, int irq);
 int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc,
                   unsigned int irq_base, unsigned int irq_offset);
-/* default to the implementation in drivers/lib/msi.c */
-#define HAVE_DEFAULT_MSI_TEARDOWN_IRQS
-#define HAVE_DEFAULT_MSI_RESTORE_IRQS
-void default_teardown_msi_irqs(struct pci_dev *dev);
-void default_restore_msi_irqs(struct pci_dev *dev, int irq);
 #else
 #define native_setup_msi_irqs           NULL
 #define native_teardown_msi_irq         NULL
-#define default_teardown_msi_irqs       NULL
-#define default_restore_msi_irqs        NULL
 #endif
 
 #define PCI_DMA_BUS_IS_PHYS (dma_ops->is_phys)
diff --git a/arch/x86/kernel/x86_init.c b/arch/x86/kernel/x86_init.c
index 5f24c71accaa..8ce0072cd700 100644
--- a/arch/x86/kernel/x86_init.c
+++ b/arch/x86/kernel/x86_init.c
@@ -107,6 +107,8 @@ struct x86_platform_ops x86_platform = {
 };
 
 EXPORT_SYMBOL_GPL(x86_platform);
+
+#if defined(CONFIG_PCI_MSI)
 struct x86_msi_ops x86_msi = {
         .setup_msi_irqs         = native_setup_msi_irqs,
         .compose_msi_msg        = native_compose_msi_msg,
@@ -116,6 +118,28 @@ struct x86_msi_ops x86_msi = {
         .setup_hpet_msi         = default_setup_hpet_msi,
 };
 
+/* MSI arch specific hooks */
+int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
+{
+        return x86_msi.setup_msi_irqs(dev, nvec, type);
+}
+
+void arch_teardown_msi_irqs(struct pci_dev *dev)
+{
+        x86_msi.teardown_msi_irqs(dev);
+}
+
+void arch_teardown_msi_irq(unsigned int irq)
+{
+        x86_msi.teardown_msi_irq(irq);
+}
+
+void arch_restore_msi_irqs(struct pci_dev *dev, int irq)
+{
+        x86_msi.restore_msi_irqs(dev, irq);
+}
+#endif
+
 struct x86_io_apic_ops x86_io_apic_ops = {
         .init                   = native_io_apic_init_mappings,
         .read                   = native_io_apic_read,
diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig
index 1f70e84b442c..552373c4e362 100644
--- a/drivers/bus/Kconfig
+++ b/drivers/bus/Kconfig
@@ -8,10 +8,9 @@ config IMX_WEIM
         bool "Freescale EIM DRIVER"
         depends on ARCH_MXC
         help
-          Driver for i.MX6 WEIM controller.
+          Driver for i.MX WEIM controller.
           The WEIM(Wireless External Interface Module) works like a bus.
           You can attach many different devices on it, such as NOR, onenand.
-          But now, we only support the Parallel NOR.
 
 config MVEBU_MBUS
         bool
diff --git a/drivers/bus/imx-weim.c b/drivers/bus/imx-weim.c
index 349f14e886b7..3ef58c8dbf11 100644
--- a/drivers/bus/imx-weim.c
+++ b/drivers/bus/imx-weim.c
@@ -12,52 +12,83 @@
 #include <linux/io.h>
 #include <linux/of_device.h>
 
-struct imx_weim {
-        void __iomem *base;
-        struct clk *clk;
+struct imx_weim_devtype {
+        unsigned int    cs_count;
+        unsigned int    cs_regs_count;
+        unsigned int    cs_stride;
+};
+
+static const struct imx_weim_devtype imx1_weim_devtype = {
+        .cs_count       = 6,
+        .cs_regs_count  = 2,
+        .cs_stride      = 0x08,
+};
+
+static const struct imx_weim_devtype imx27_weim_devtype = {
+        .cs_count       = 6,
+        .cs_regs_count  = 3,
+        .cs_stride      = 0x10,
+};
+
+static const struct imx_weim_devtype imx50_weim_devtype = {
+        .cs_count       = 4,
+        .cs_regs_count  = 6,
+        .cs_stride      = 0x18,
+};
+
+static const struct imx_weim_devtype imx51_weim_devtype = {
+        .cs_count       = 6,
+        .cs_regs_count  = 6,
+        .cs_stride      = 0x18,
 };
 
 static const struct of_device_id weim_id_table[] = {
-        { .compatible = "fsl,imx6q-weim", },
-        {}
+        /* i.MX1/21 */
+        { .compatible = "fsl,imx1-weim", .data = &imx1_weim_devtype, },
+        /* i.MX25/27/31/35 */
+        { .compatible = "fsl,imx27-weim", .data = &imx27_weim_devtype, },
+        /* i.MX50/53/6Q */
+        { .compatible = "fsl,imx50-weim", .data = &imx50_weim_devtype, },
+        { .compatible = "fsl,imx6q-weim", .data = &imx50_weim_devtype, },
+        /* i.MX51 */
+        { .compatible = "fsl,imx51-weim", .data = &imx51_weim_devtype, },
+        { }
 };
 MODULE_DEVICE_TABLE(of, weim_id_table);
 
-#define CS_TIMING_LEN 6
-#define CS_REG_RANGE  0x18
-
 /* Parse and set the timing for this device. */
-static int
-weim_timing_setup(struct platform_device *pdev, struct device_node *np)
+static int __init weim_timing_setup(struct device_node *np, void __iomem *base,
+                                    const struct imx_weim_devtype *devtype)
 {
-        struct imx_weim *weim = platform_get_drvdata(pdev);
-        u32 value[CS_TIMING_LEN];
-        u32 cs_idx;
-        int ret;
-        int i;
+        u32 cs_idx, value[devtype->cs_regs_count];
+        int i, ret;
 
         /* get the CS index from this child node's "reg" property. */
         ret = of_property_read_u32(np, "reg", &cs_idx);
         if (ret)
                 return ret;
 
-        /* The weim has four chip selects. */
-        if (cs_idx > 3)
+        if (cs_idx >= devtype->cs_count)
                 return -EINVAL;
 
         ret = of_property_read_u32_array(np, "fsl,weim-cs-timing",
-                                        value, CS_TIMING_LEN);
+                                         value, devtype->cs_regs_count);
         if (ret)
                 return ret;
 
         /* set the timing for WEIM */
-        for (i = 0; i < CS_TIMING_LEN; i++)
-                writel(value[i], weim->base + cs_idx * CS_REG_RANGE + i * 4);
+        for (i = 0; i < devtype->cs_regs_count; i++)
+                writel(value[i], base + cs_idx * devtype->cs_stride + i * 4);
+
         return 0;
 }
 
-static int weim_parse_dt(struct platform_device *pdev)
+static int __init weim_parse_dt(struct platform_device *pdev,
+                                void __iomem *base)
 {
+        const struct of_device_id *of_id = of_match_device(weim_id_table,
+                                                           &pdev->dev);
+        const struct imx_weim_devtype *devtype = of_id->data;
         struct device_node *child;
         int ret;
 
@@ -65,7 +96,7 @@ static int weim_parse_dt(struct platform_device *pdev)
                 if (!child->name)
                         continue;
 
-                ret = weim_timing_setup(pdev, child);
+                ret = weim_timing_setup(child, base, devtype);
                 if (ret) {
                         dev_err(&pdev->dev, "%s set timing failed.\n",
                                 child->full_name);
@@ -80,59 +111,47 @@ static int weim_parse_dt(struct platform_device *pdev)
         return ret;
 }
 
-static int weim_probe(struct platform_device *pdev)
+static int __init weim_probe(struct platform_device *pdev)
 {
-        struct imx_weim *weim;
         struct resource *res;
-        int ret = -EINVAL;
-
-        weim = devm_kzalloc(&pdev->dev, sizeof(*weim), GFP_KERNEL);
-        if (!weim) {
-                ret = -ENOMEM;
-                goto weim_err;
-        }
-        platform_set_drvdata(pdev, weim);
+        struct clk *clk;
+        void __iomem *base;
+        int ret;
 
         /* get the resource */
         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        weim->base = devm_ioremap_resource(&pdev->dev, res);
-        if (IS_ERR(weim->base)) {
-                ret = PTR_ERR(weim->base);
-                goto weim_err;
-        }
+        base = devm_ioremap_resource(&pdev->dev, res);
+        if (IS_ERR(base))
+                return PTR_ERR(base);
 
         /* get the clock */
-        weim->clk = devm_clk_get(&pdev->dev, NULL);
-        if (IS_ERR(weim->clk))
-                goto weim_err;
+        clk = devm_clk_get(&pdev->dev, NULL);
+        if (IS_ERR(clk))
+                return PTR_ERR(clk);
 
-        ret = clk_prepare_enable(weim->clk);
+        ret = clk_prepare_enable(clk);
         if (ret)
-                goto weim_err;
+                return ret;
 
         /* parse the device node */
-        ret = weim_parse_dt(pdev);
-        if (ret) {
-                clk_disable_unprepare(weim->clk);
-                goto weim_err;
-        }
-
-        dev_info(&pdev->dev, "WEIM driver registered.\n");
-        return 0;
+        ret = weim_parse_dt(pdev, base);
+        if (ret)
+                clk_disable_unprepare(clk);
+        else
+                dev_info(&pdev->dev, "Driver registered.\n");
 
-weim_err:
         return ret;
 }
 
 static struct platform_driver weim_driver = {
         .driver = {
-                .name = "imx-weim",
-                .of_match_table = weim_id_table,
+                .name           = "imx-weim",
+                .owner          = THIS_MODULE,
+                .of_match_table = weim_id_table,
         },
-        .probe   = weim_probe,
 };
+module_platform_driver_probe(weim_driver, weim_probe);
 
-module_platform_driver(weim_driver);
 MODULE_AUTHOR("Freescale Semiconductor Inc.");
 MODULE_DESCRIPTION("i.MX EIM Controller Driver");
 MODULE_LICENSE("GPL");
diff --git a/drivers/bus/mvebu-mbus.c b/drivers/bus/mvebu-mbus.c
index 33c6947eebec..19ab6ff53d59 100644
--- a/drivers/bus/mvebu-mbus.c
+++ b/drivers/bus/mvebu-mbus.c
@@ -35,13 +35,9 @@
  *
  * - Provides an API for platform code or device drivers to
  *   dynamically add or remove address decoding windows for the CPU ->
- *   device accesses. This API is mvebu_mbus_add_window(),
- *   mvebu_mbus_add_window_remap_flags() and
- *   mvebu_mbus_del_window(). Since the (target, attribute) values
- *   differ from one SoC family to another, the API uses a 'const char
- *   *' string to identify devices, and this driver is responsible for
- *   knowing the mapping between the name of a device and its
- *   corresponding (target, attribute) in the current SoC family.
+ *   device accesses. This API is mvebu_mbus_add_window_by_id(),
+ *   mvebu_mbus_add_window_remap_by_id() and
+ *   mvebu_mbus_del_window().
  *
  * - Provides a debugfs interface in /sys/kernel/debug/mvebu-mbus/ to
  *   see the list of CPU -> SDRAM windows and their configuration
@@ -97,33 +93,6 @@
 
 #define DOVE_DDR_BASE_CS_OFF(n) ((n) << 4)
 
-struct mvebu_mbus_mapping {
-        const char *name;
-        u8 target;
-        u8 attr;
-        u8 attrmask;
-};
-
-/*
- * Masks used for the 'attrmask' field of mvebu_mbus_mapping. They
- * allow to get the real attribute value, discarding the special bits
- * used to select a PCI MEM region or a PCI WA region. This allows the
- * debugfs code to reverse-match the name of a device from its
- * target/attr values.
- *
- * For all devices except PCI, all bits of 'attr' must be
- * considered. For most SoCs, only bit 3 should be ignored (it allows
- * to select between PCI MEM and PCI I/O). On Orion5x however, there
- * is the special bit 5 to select a PCI WA region.
- */
-#define MAPDEF_NOMASK       0xff
-#define MAPDEF_PCIMASK      0xf7
-#define MAPDEF_ORIONPCIMASK 0xd7
-
-/* Macro used to define one mvebu_mbus_mapping entry */
-#define MAPDEF(__n, __t, __a, __m) \
-        { .name = __n, .target = __t, .attr = __a, .attrmask = __m }
-
 struct mvebu_mbus_state;
 
 struct mvebu_mbus_soc_data {
@@ -133,7 +102,6 @@ struct mvebu_mbus_soc_data {
         void (*setup_cpu_target)(struct mvebu_mbus_state *s);
         int (*show_cpu_target)(struct mvebu_mbus_state *s,
                                struct seq_file *seq, void *v);
-        const struct mvebu_mbus_mapping *map;
 };
 
 struct mvebu_mbus_state {
@@ -142,6 +110,8 @@ struct mvebu_mbus_state {
         struct dentry *debugfs_root;
         struct dentry *debugfs_sdram;
         struct dentry *debugfs_devs;
+        struct resource pcie_mem_aperture;
+        struct resource pcie_io_aperture;
         const struct mvebu_mbus_soc_data *soc;
         int hw_io_coherency;
 };
@@ -428,8 +398,7 @@ static int mvebu_devs_debug_show(struct seq_file *seq, void *v)
                 u64 wbase, wremap;
                 u32 wsize;
                 u8 wtarget, wattr;
-                int enabled, i;
-                const char *name;
+                int enabled;
 
                 mvebu_mbus_read_window(mbus, win,
                                        &enabled, &wbase, &wsize,
@@ -440,18 +409,9 @@ static int mvebu_devs_debug_show(struct seq_file *seq, void *v)
                         continue;
                 }
 
-
-                for (i = 0; mbus->soc->map[i].name; i++)
-                        if (mbus->soc->map[i].target == wtarget &&
-                            mbus->soc->map[i].attr ==
-                            (wattr & mbus->soc->map[i].attrmask))
-                                break;
-
-                name = mbus->soc->map[i].name ?: "unknown";
-
-                seq_printf(seq, "[%02d] %016llx - %016llx : %s",
+                seq_printf(seq, "[%02d] %016llx - %016llx : %04x:%04x",
                            win, (unsigned long long)wbase,
-                           (unsigned long long)(wbase + wsize), name);
+                           (unsigned long long)(wbase + wsize), wtarget, wattr);
 
                 if (win < mbus->soc->num_remappable_wins) {
                         seq_printf(seq, " (remap %016llx)\n",
@@ -576,62 +536,12 @@ mvebu_mbus_dove_setup_cpu_target(struct mvebu_mbus_state *mbus)
         mvebu_mbus_dram_info.num_cs = cs;
 }
 
-static const struct mvebu_mbus_mapping armada_370_map[] = {
-        MAPDEF("bootrom",     1, 0xe0, MAPDEF_NOMASK),
-        MAPDEF("devbus-boot", 1, 0x2f, MAPDEF_NOMASK),
-        MAPDEF("devbus-cs0",  1, 0x3e, MAPDEF_NOMASK),
-        MAPDEF("devbus-cs1",  1, 0x3d, MAPDEF_NOMASK),
-        MAPDEF("devbus-cs2",  1, 0x3b, MAPDEF_NOMASK),
-        MAPDEF("devbus-cs3",  1, 0x37, MAPDEF_NOMASK),
-        MAPDEF("pcie0.0",     4, 0xe0, MAPDEF_PCIMASK),
-        MAPDEF("pcie1.0",     8, 0xe0, MAPDEF_PCIMASK),
-        {},
-};
-
-static const struct mvebu_mbus_soc_data armada_370_mbus_data = {
+static const struct mvebu_mbus_soc_data armada_370_xp_mbus_data = {
         .num_wins            = 20,
         .num_remappable_wins = 8,
         .win_cfg_offset      = armada_370_xp_mbus_win_offset,
         .setup_cpu_target    = mvebu_mbus_default_setup_cpu_target,
         .show_cpu_target     = mvebu_sdram_debug_show_orion,
-        .map                 = armada_370_map,
-};
-
-static const struct mvebu_mbus_mapping armada_xp_map[] = {
-        MAPDEF("bootrom",     1, 0x1d, MAPDEF_NOMASK),
-        MAPDEF("devbus-boot", 1, 0x2f, MAPDEF_NOMASK),
-        MAPDEF("devbus-cs0",  1, 0x3e, MAPDEF_NOMASK),
-        MAPDEF("devbus-cs1",  1, 0x3d, MAPDEF_NOMASK),
-        MAPDEF("devbus-cs2",  1, 0x3b, MAPDEF_NOMASK),
-        MAPDEF("devbus-cs3",  1, 0x37, MAPDEF_NOMASK),
-        MAPDEF("pcie0.0",     4, 0xe0, MAPDEF_PCIMASK),
-        MAPDEF("pcie0.1",     4, 0xd0, MAPDEF_PCIMASK),
-        MAPDEF("pcie0.2",     4, 0xb0, MAPDEF_PCIMASK),
-        MAPDEF("pcie0.3",     4, 0x70, MAPDEF_PCIMASK),
-        MAPDEF("pcie1.0",     8, 0xe0, MAPDEF_PCIMASK),
-        MAPDEF("pcie1.1",     8, 0xd0, MAPDEF_PCIMASK),
-        MAPDEF("pcie1.2",     8, 0xb0, MAPDEF_PCIMASK),
-        MAPDEF("pcie1.3",     8, 0x70, MAPDEF_PCIMASK),
-        MAPDEF("pcie2.0",     4, 0xf0, MAPDEF_PCIMASK),
-        MAPDEF("pcie3.0",     8, 0xf0, MAPDEF_PCIMASK),
-        {},
-};
-
-static const struct mvebu_mbus_soc_data armada_xp_mbus_data = {
-        .num_wins            = 20,
-        .num_remappable_wins = 8,
-        .win_cfg_offset      = armada_370_xp_mbus_win_offset,
-        .setup_cpu_target    = mvebu_mbus_default_setup_cpu_target,
-        .show_cpu_target     = mvebu_sdram_debug_show_orion,
-        .map                 = armada_xp_map,
-};
-
-static const struct mvebu_mbus_mapping kirkwood_map[] = {
-        MAPDEF("pcie0.0", 4, 0xe0, MAPDEF_PCIMASK),
-        MAPDEF("pcie1.0", 4, 0xd0, MAPDEF_PCIMASK),
-        MAPDEF("sram",    3, 0x01, MAPDEF_NOMASK),
-        MAPDEF("nand",    1, 0x2f, MAPDEF_NOMASK),
-        {},
 };
 
 static const struct mvebu_mbus_soc_data kirkwood_mbus_data = {
@@ -640,16 +550,6 @@ static const struct mvebu_mbus_soc_data kirkwood_mbus_data = {
         .win_cfg_offset      = orion_mbus_win_offset,
         .setup_cpu_target    = mvebu_mbus_default_setup_cpu_target,
         .show_cpu_target     = mvebu_sdram_debug_show_orion,
-        .map                 = kirkwood_map,
-};
-
-static const struct mvebu_mbus_mapping dove_map[] = {
-        MAPDEF("pcie0.0",    0x4, 0xe0, MAPDEF_PCIMASK),
-        MAPDEF("pcie1.0",    0x8, 0xe0, MAPDEF_PCIMASK),
-        MAPDEF("cesa",       0x3, 0x01, MAPDEF_NOMASK),
-        MAPDEF("bootrom",    0x1, 0xfd, MAPDEF_NOMASK),
-        MAPDEF("scratchpad", 0xd, 0x0, MAPDEF_NOMASK),
-        {},
 };
 
 static const struct mvebu_mbus_soc_data dove_mbus_data = {
@@ -658,18 +558,6 @@ static const struct mvebu_mbus_soc_data dove_mbus_data = {
         .win_cfg_offset      = orion_mbus_win_offset,
         .setup_cpu_target    = mvebu_mbus_dove_setup_cpu_target,
         .show_cpu_target     = mvebu_sdram_debug_show_dove,
-        .map                 = dove_map,
-};
-
-static const struct mvebu_mbus_mapping orion5x_map[] = {
-        MAPDEF("pcie0.0",     4, 0x51, MAPDEF_ORIONPCIMASK),
-        MAPDEF("pci0.0",      3, 0x51, MAPDEF_ORIONPCIMASK),
-        MAPDEF("devbus-boot", 1, 0x0f, MAPDEF_NOMASK),
-        MAPDEF("devbus-cs0",  1, 0x1e, MAPDEF_NOMASK),
-        MAPDEF("devbus-cs1",  1, 0x1d, MAPDEF_NOMASK),
-        MAPDEF("devbus-cs2",  1, 0x1b, MAPDEF_NOMASK),
-        MAPDEF("sram",        0, 0x00, MAPDEF_NOMASK),
-        {},
 };
 
 /*
@@ -682,7 +570,6 @@ static const struct mvebu_mbus_soc_data orion5x_4win_mbus_data = {
         .win_cfg_offset      = orion_mbus_win_offset,
         .setup_cpu_target    = mvebu_mbus_default_setup_cpu_target,
         .show_cpu_target     = mvebu_sdram_debug_show_orion,
-        .map                 = orion5x_map,
 };
 
 static const struct mvebu_mbus_soc_data orion5x_2win_mbus_data = {
@@ -691,21 +578,6 @@ static const struct mvebu_mbus_soc_data orion5x_2win_mbus_data = {
         .win_cfg_offset      = orion_mbus_win_offset,
         .setup_cpu_target    = mvebu_mbus_default_setup_cpu_target,
         .show_cpu_target     = mvebu_sdram_debug_show_orion,
-        .map                 = orion5x_map,
-};
-
-static const struct mvebu_mbus_mapping mv78xx0_map[] = {
-        MAPDEF("pcie0.0", 4, 0xe0, MAPDEF_PCIMASK),
-        MAPDEF("pcie0.1", 4, 0xd0, MAPDEF_PCIMASK),
-        MAPDEF("pcie0.2", 4, 0xb0, MAPDEF_PCIMASK),
-        MAPDEF("pcie0.3", 4, 0x70, MAPDEF_PCIMASK),
-        MAPDEF("pcie1.0", 8, 0xe0, MAPDEF_PCIMASK),
-        MAPDEF("pcie1.1", 8, 0xd0, MAPDEF_PCIMASK),
-        MAPDEF("pcie1.2", 8, 0xb0, MAPDEF_PCIMASK),
-        MAPDEF("pcie1.3", 8, 0x70, MAPDEF_PCIMASK),
-        MAPDEF("pcie2.0", 4, 0xf0, MAPDEF_PCIMASK),
-        MAPDEF("pcie3.0", 8, 0xf0, MAPDEF_PCIMASK),
-        {},
 };
 
 static const struct mvebu_mbus_soc_data mv78xx0_mbus_data = {
@@ -714,7 +586,6 @@ static const struct mvebu_mbus_soc_data mv78xx0_mbus_data = {
         .win_cfg_offset      = mv78xx0_mbus_win_offset,
         .setup_cpu_target    = mvebu_mbus_default_setup_cpu_target,
         .show_cpu_target     = mvebu_sdram_debug_show_orion,
-        .map                 = mv78xx0_map,
 };
 
 /*
@@ -725,9 +596,9 @@ static const struct mvebu_mbus_soc_data mv78xx0_mbus_data = {
  */
 static const struct of_device_id of_mvebu_mbus_ids[] = {
         { .compatible = "marvell,armada370-mbus",
-          .data = &armada_370_mbus_data, },
+          .data = &armada_370_xp_mbus_data, },
         { .compatible = "marvell,armadaxp-mbus",
-          .data = &armada_xp_mbus_data, },
+          .data = &armada_370_xp_mbus_data, },
         { .compatible = "marvell,kirkwood-mbus",
           .data = &kirkwood_mbus_data, },
         { .compatible = "marvell,dove-mbus",
@@ -748,48 +619,27 @@ static const struct of_device_id of_mvebu_mbus_ids[] = {
 /*
  * Public API of the driver
  */
-int mvebu_mbus_add_window_remap_flags(const char *devname, phys_addr_t base,
-                                      size_t size, phys_addr_t remap,
-                                      unsigned int flags)
+int mvebu_mbus_add_window_remap_by_id(unsigned int target,
+                                      unsigned int attribute,
+                                      phys_addr_t base, size_t size,
+                                      phys_addr_t remap)
 {
         struct mvebu_mbus_state *s = &mbus_state;
-        u8 target, attr;
-        int i;
-
-        if (!s->soc->map)
-                return -ENODEV;
-
-        for (i = 0; s->soc->map[i].name; i++)
-                if (!strcmp(s->soc->map[i].name, devname))
-                        break;
-
-        if (!s->soc->map[i].name) {
-                pr_err("unknown device '%s'\n", devname);
-                return -ENODEV;
-        }
-
-        target = s->soc->map[i].target;
-        attr   = s->soc->map[i].attr;
-
-        if (flags == MVEBU_MBUS_PCI_MEM)
-                attr |= 0x8;
-        else if (flags == MVEBU_MBUS_PCI_WA)
-                attr |= 0x28;
 
-        if (!mvebu_mbus_window_conflicts(s, base, size, target, attr)) {
-                pr_err("cannot add window '%s', conflicts with another window\n",
-                       devname);
+        if (!mvebu_mbus_window_conflicts(s, base, size, target, attribute)) {
+                pr_err("cannot add window '%x:%x', conflicts with another window\n",
+                       target, attribute);
                 return -EINVAL;
         }
 
-        return mvebu_mbus_alloc_window(s, base, size, remap, target, attr);
-
+        return mvebu_mbus_alloc_window(s, base, size, remap, target, attribute);
 }
 
-int mvebu_mbus_add_window(const char *devname, phys_addr_t base, size_t size)
+int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
+                                phys_addr_t base, size_t size)
 {
-        return mvebu_mbus_add_window_remap_flags(devname, base, size,
-                                                 MVEBU_MBUS_NO_REMAP, 0);
+        return mvebu_mbus_add_window_remap_by_id(target, attribute, base,
+                                                 size, MVEBU_MBUS_NO_REMAP);
 }
 
 int mvebu_mbus_del_window(phys_addr_t base, size_t size)
@@ -804,6 +654,20 @@ int mvebu_mbus_del_window(phys_addr_t base, size_t size)
         return 0;
 }
 
+void mvebu_mbus_get_pcie_mem_aperture(struct resource *res)
+{
+        if (!res)
+                return;
+        *res = mbus_state.pcie_mem_aperture;
+}
+
+void mvebu_mbus_get_pcie_io_aperture(struct resource *res)
+{
+        if (!res)
+                return;
+        *res = mbus_state.pcie_io_aperture;
+}
+
 static __init int mvebu_mbus_debugfs_init(void)
 {
         struct mvebu_mbus_state *s = &mbus_state;
@@ -830,14 +694,41 @@ static __init int mvebu_mbus_debugfs_init(void)
 }
 fs_initcall(mvebu_mbus_debugfs_init);
 
+static int __init mvebu_mbus_common_init(struct mvebu_mbus_state *mbus,
+                                         phys_addr_t mbuswins_phys_base,
+                                         size_t mbuswins_size,
+                                         phys_addr_t sdramwins_phys_base,
+                                         size_t sdramwins_size)
+{
+        int win;
+
+        mbus->mbuswins_base = ioremap(mbuswins_phys_base, mbuswins_size);
+        if (!mbus->mbuswins_base)
+                return -ENOMEM;
+
+        mbus->sdramwins_base = ioremap(sdramwins_phys_base, sdramwins_size);
+        if (!mbus->sdramwins_base) {
+                iounmap(mbus_state.mbuswins_base);
+                return -ENOMEM;
+        }
+
+        if (of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric"))
+                mbus->hw_io_coherency = 1;
+
+        for (win = 0; win < mbus->soc->num_wins; win++)
+                mvebu_mbus_disable_window(mbus, win);
+
+        mbus->soc->setup_cpu_target(mbus);
+
+        return 0;
+}
+
 int __init mvebu_mbus_init(const char *soc, phys_addr_t mbuswins_phys_base,
                            size_t mbuswins_size,
                            phys_addr_t sdramwins_phys_base,
                            size_t sdramwins_size)
 {
-        struct mvebu_mbus_state *mbus = &mbus_state;
         const struct of_device_id *of_id;
-        int win;
 
         for (of_id = of_mvebu_mbus_ids; of_id->compatible; of_id++)
                 if (!strcmp(of_id->compatible, soc))
@@ -848,25 +739,201 @@ int __init mvebu_mbus_init(const char *soc, phys_addr_t mbuswins_phys_base,
                 return -ENODEV;
         }
 
-        mbus->soc = of_id->data;
+        mbus_state.soc = of_id->data;
 
-        mbus->mbuswins_base = ioremap(mbuswins_phys_base, mbuswins_size);
-        if (!mbus->mbuswins_base)
-                return -ENOMEM;
+        return mvebu_mbus_common_init(&mbus_state,
+                        mbuswins_phys_base,
+                        mbuswins_size,
+                        sdramwins_phys_base,
+                        sdramwins_size);
+}
 
-        mbus->sdramwins_base = ioremap(sdramwins_phys_base, sdramwins_size);
-        if (!mbus->sdramwins_base) {
-                iounmap(mbus_state.mbuswins_base);
+#ifdef CONFIG_OF
+/*
+ * The window IDs in the ranges DT property have the following format:
+ *  - bits 28 to 31: MBus custom field
+ *  - bits 24 to 27: window target ID
+ *  - bits 16 to 23: window attribute ID
+ *  - bits  0 to 15: unused
+ */
+#define CUSTOM(id) (((id) & 0xF0000000) >> 24)
+#define TARGET(id) (((id) & 0x0F000000) >> 24)
+#define ATTR(id)   (((id) & 0x00FF0000) >> 16)
+
+static int __init mbus_dt_setup_win(struct mvebu_mbus_state *mbus,
+                                    u32 base, u32 size,
+                                    u8 target, u8 attr)
+{
+        if (!mvebu_mbus_window_conflicts(mbus, base, size, target, attr)) {
+                pr_err("cannot add window '%04x:%04x', conflicts with another window\n",
+                       target, attr);
+                return -EBUSY;
+        }
+
+        if (mvebu_mbus_alloc_window(mbus, base, size, MVEBU_MBUS_NO_REMAP,
+                                    target, attr)) {
+                pr_err("cannot add window '%04x:%04x', too many windows\n",
+                       target, attr);
                 return -ENOMEM;
         }
+        return 0;
+}
 
-        if (of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric"))
-                mbus->hw_io_coherency = 1;
+static int __init
+mbus_parse_ranges(struct device_node *node,
+                  int *addr_cells, int *c_addr_cells, int *c_size_cells,
+                  int *cell_count, const __be32 **ranges_start,
+                  const __be32 **ranges_end)
+{
+        const __be32 *prop;
+        int ranges_len, tuple_len;
+
+        /* Allow a node with no 'ranges' property */
+        *ranges_start = of_get_property(node, "ranges", &ranges_len);
+        if (*ranges_start == NULL) {
+                *addr_cells = *c_addr_cells = *c_size_cells = *cell_count = 0;
+                *ranges_start = *ranges_end = NULL;
+                return 0;
+        }
+        *ranges_end = *ranges_start + ranges_len / sizeof(__be32);
 
-        for (win = 0; win < mbus->soc->num_wins; win++)
-                mvebu_mbus_disable_window(mbus, win);
+        *addr_cells = of_n_addr_cells(node);
 
-        mbus->soc->setup_cpu_target(mbus);
+        prop = of_get_property(node, "#address-cells", NULL);
+        *c_addr_cells = be32_to_cpup(prop);
+
+        prop = of_get_property(node, "#size-cells", NULL);
+        *c_size_cells = be32_to_cpup(prop);
+
+        *cell_count = *addr_cells + *c_addr_cells + *c_size_cells;
+        tuple_len = (*cell_count) * sizeof(__be32);
+
+        if (ranges_len % tuple_len) {
+                pr_warn("malformed ranges entry '%s'\n", node->name);
+                return -EINVAL;
+        }
+        return 0;
+}
+
+static int __init mbus_dt_setup(struct mvebu_mbus_state *mbus,
+                                struct device_node *np)
+{
+        int addr_cells, c_addr_cells, c_size_cells;
+        int i, ret, cell_count;
+        const __be32 *r, *ranges_start, *ranges_end;
+
+        ret = mbus_parse_ranges(np, &addr_cells, &c_addr_cells,
+                                &c_size_cells, &cell_count,
+                                &ranges_start, &ranges_end);
+        if (ret < 0)
+                return ret;
+
+        for (i = 0, r = ranges_start; r < ranges_end; r += cell_count, i++) {
+                u32 windowid, base, size;
+                u8 target, attr;
+
+                /*
+                 * An entry with a non-zero custom field do not
+                 * correspond to a static window, so skip it.
+                 */
+                windowid = of_read_number(r, 1);
+                if (CUSTOM(windowid))
+                        continue;
+
+                target = TARGET(windowid);
+                attr = ATTR(windowid);
 
+                base = of_read_number(r + c_addr_cells, addr_cells);
+                size = of_read_number(r + c_addr_cells + addr_cells,
+                                      c_size_cells);
+                ret = mbus_dt_setup_win(mbus, base, size, target, attr);
+                if (ret < 0)
+                        return ret;
+        }
         return 0;
 }
+
+static void __init mvebu_mbus_get_pcie_resources(struct device_node *np,
+                                                 struct resource *mem,
+                                                 struct resource *io)
+{
+        u32 reg[2];
+        int ret;
+
+        /*
+         * These are optional, so we clear them and they'll
+         * be zero if they are missing from the DT.
+         */
+        memset(mem, 0, sizeof(struct resource));
+        memset(io, 0, sizeof(struct resource));
+
+        ret = of_property_read_u32_array(np, "pcie-mem-aperture", reg, ARRAY_SIZE(reg));
+        if (!ret) {
+                mem->start = reg[0];
+                mem->end = mem->start + reg[1];
+                mem->flags = IORESOURCE_MEM;
+        }
+
+        ret = of_property_read_u32_array(np, "pcie-io-aperture", reg, ARRAY_SIZE(reg));
+        if (!ret) {
+                io->start = reg[0];
+                io->end = io->start + reg[1];
+                io->flags = IORESOURCE_IO;
+        }
+}
+
+int __init mvebu_mbus_dt_init(void)
+{
+        struct resource mbuswins_res, sdramwins_res;
+        struct device_node *np, *controller;
+        const struct of_device_id *of_id;
+        const __be32 *prop;
+        int ret;
+
+        np = of_find_matching_node(NULL, of_mvebu_mbus_ids);
+        if (!np) {
+                pr_err("could not find a matching SoC family\n");
+                return -ENODEV;
+        }
+
+        of_id = of_match_node(of_mvebu_mbus_ids, np);
+        mbus_state.soc = of_id->data;
+
+        prop = of_get_property(np, "controller", NULL);
+        if (!prop) {
+                pr_err("required 'controller' property missing\n");
+                return -EINVAL;
+        }
+
+        controller = of_find_node_by_phandle(be32_to_cpup(prop));
+        if (!controller) {
+                pr_err("could not find an 'mbus-controller' node\n");
+                return -ENODEV;
+        }
+
+        if (of_address_to_resource(controller, 0, &mbuswins_res)) {
+                pr_err("cannot get MBUS register address\n");
+                return -EINVAL;
+        }
+
+        if (of_address_to_resource(controller, 1, &sdramwins_res)) {
+                pr_err("cannot get SDRAM register address\n");
+                return -EINVAL;
+        }
+
+        /* Get optional pcie-{mem,io}-aperture properties */
+        mvebu_mbus_get_pcie_resources(np, &mbus_state.pcie_mem_aperture,
+                                          &mbus_state.pcie_io_aperture);
+
+        ret = mvebu_mbus_common_init(&mbus_state,
+                                     mbuswins_res.start,
+                                     resource_size(&mbuswins_res),
+                                     sdramwins_res.start,
+                                     resource_size(&sdramwins_res));
+        if (ret)
+                return ret;
+
+        /* Setup statically declared windows in the DT */
+        return mbus_dt_setup(&mbus_state, np);
+}
+#endif
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index b6015cb4fc01..806d80366c54 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -290,6 +290,14 @@
 /* Tegra CPU clock and reset control regs */
 #define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS     0x470
 
+#ifdef CONFIG_PM_SLEEP
+static struct cpu_clk_suspend_context {
+        u32 clk_csite_src;
+        u32 cclkg_burst;
+        u32 cclkg_divider;
+} tegra114_cpu_clk_sctx;
+#endif
+
 static int periph_clk_enb_refcnt[CLK_OUT_ENB_NUM * 32];
 
 static void __iomem *clk_base;
@@ -2142,9 +2150,39 @@ static void tegra114_disable_cpu_clock(u32 cpu)
         /* flow controller would take care in the power sequence. */
 }
 
+#ifdef CONFIG_PM_SLEEP
+static void tegra114_cpu_clock_suspend(void)
+{
+        /* switch coresite to clk_m, save off original source */
+        tegra114_cpu_clk_sctx.clk_csite_src =
+                                readl(clk_base + CLK_SOURCE_CSITE);
+        writel(3 << 30, clk_base + CLK_SOURCE_CSITE);
+
+        tegra114_cpu_clk_sctx.cclkg_burst =
+                                readl(clk_base + CCLKG_BURST_POLICY);
+        tegra114_cpu_clk_sctx.cclkg_divider =
+                                readl(clk_base + CCLKG_BURST_POLICY + 4);
+}
+
+static void tegra114_cpu_clock_resume(void)
+{
+        writel(tegra114_cpu_clk_sctx.clk_csite_src,
+                                        clk_base + CLK_SOURCE_CSITE);
+
+        writel(tegra114_cpu_clk_sctx.cclkg_burst,
+                                        clk_base + CCLKG_BURST_POLICY);
+        writel(tegra114_cpu_clk_sctx.cclkg_divider,
+                                        clk_base + CCLKG_BURST_POLICY + 4);
+}
+#endif
+
 static struct tegra_cpu_car_ops tegra114_cpu_car_ops = {
         .wait_for_reset = tegra114_wait_cpu_in_reset,
         .disable_clock  = tegra114_disable_cpu_clock,
+#ifdef CONFIG_PM_SLEEP
+        .suspend        = tegra114_cpu_clock_suspend,
+        .resume         = tegra114_cpu_clock_resume,
+#endif
 };
 
 static const struct of_device_id pmc_match[] __initconst = {
diff --git a/drivers/memory/mvebu-devbus.c b/drivers/memory/mvebu-devbus.c
index 978e8e3abc5c..110c03627051 100644
--- a/drivers/memory/mvebu-devbus.c
+++ b/drivers/memory/mvebu-devbus.c
@@ -44,14 +44,6 @@
 #define READ_PARAM_OFFSET       0x0
 #define WRITE_PARAM_OFFSET      0x4
 
-static const char * const devbus_wins[] = {
-        "devbus-boot",
-        "devbus-cs0",
-        "devbus-cs1",
-        "devbus-cs2",
-        "devbus-cs3",
-};
-
 struct devbus_read_params {
         u32 bus_width;
         u32 badr_skew;
@@ -208,16 +200,11 @@ static int mvebu_devbus_probe(struct platform_device *pdev)
 {
         struct device *dev = &pdev->dev;
         struct device_node *node = pdev->dev.of_node;
-        struct device_node *parent;
         struct devbus *devbus;
         struct resource *res;
         struct clk *clk;
         unsigned long rate;
-        const __be32 *ranges;
-        int err, cs;
-        int addr_cells, p_addr_cells, size_cells;
-        int ranges_len, tuple_len;
-        u32 base, size;
+        int err;
 
         devbus = devm_kzalloc(&pdev->dev, sizeof(struct devbus), GFP_KERNEL);
         if (!devbus)
@@ -248,68 +235,13 @@ static int mvebu_devbus_probe(struct platform_device *pdev)
                 return err;
 
         /*
-         * Allocate an address window for this device.
-         * If the device probing fails, then we won't be able to
-         * remove the allocated address decoding window.
-         *
-         * FIXME: This is only a temporary hack! We need to do this here
-         * because we still don't have device tree bindings for mbus.
-         * Once that support is added, we will declare these address windows
-         * statically in the device tree, and remove the window configuration
-         * from here.
-         */
-
-        /*
-         * Get the CS to choose the window string.
-         * This is a bit hacky, but it will be removed once the
-         * address windows are declared in the device tree.
-         */
-        cs = (((unsigned long)devbus->base) % 0x400) / 8;
-
-        /*
-         * Parse 'ranges' property to obtain a (base,size) window tuple.
-         * This will be removed once the address windows
-         * are declared in the device tree.
-         */
-        parent = of_get_parent(node);
-        if (!parent)
-                return -EINVAL;
-
-        p_addr_cells = of_n_addr_cells(parent);
-        of_node_put(parent);
-
-        addr_cells = of_n_addr_cells(node);
-        size_cells = of_n_size_cells(node);
-        tuple_len = (p_addr_cells + addr_cells + size_cells) * sizeof(__be32);
-
-        ranges = of_get_property(node, "ranges", &ranges_len);
-        if (ranges == NULL || ranges_len != tuple_len)
-                return -EINVAL;
-
-        base = of_translate_address(node, ranges + addr_cells);
-        if (base == OF_BAD_ADDR)
-                return -EINVAL;
-        size = of_read_number(ranges + addr_cells + p_addr_cells, size_cells);
-
-        /*
-         * Create an mbus address windows.
-         * FIXME: Remove this, together with the above code, once the
-         * address windows are declared in the device tree.
-         */
-        err = mvebu_mbus_add_window(devbus_wins[cs], base, size);
-        if (err < 0)
-                return err;
-
-        /*
          * We need to create a child device explicitly from here to
          * guarantee that the child will be probed after the timing
          * parameters for the bus are written.
          */
         err = of_platform_populate(node, NULL, NULL, dev);
-        if (err < 0) {
-                mvebu_mbus_del_window(base, size);
+        if (err < 0)
                 return err;
-        }
 
         return 0;
 }
diff --git a/drivers/of/of_pci.c b/drivers/of/of_pci.c
index 42c687a820ac..e5ca00893c0c 100644
--- a/drivers/of/of_pci.c
+++ b/drivers/of/of_pci.c
@@ -89,3 +89,48 @@ int of_pci_parse_bus_range(struct device_node *node, struct resource *res)
         return 0;
 }
 EXPORT_SYMBOL_GPL(of_pci_parse_bus_range);
+
+#ifdef CONFIG_PCI_MSI
+
+static LIST_HEAD(of_pci_msi_chip_list);
+static DEFINE_MUTEX(of_pci_msi_chip_mutex);
+
+int of_pci_msi_chip_add(struct msi_chip *chip)
+{
+        if (!of_property_read_bool(chip->of_node, "msi-controller"))
+                return -EINVAL;
+
+        mutex_lock(&of_pci_msi_chip_mutex);
+        list_add(&chip->list, &of_pci_msi_chip_list);
+        mutex_unlock(&of_pci_msi_chip_mutex);
+
+        return 0;
+}
+EXPORT_SYMBOL_GPL(of_pci_msi_chip_add);
+
+void of_pci_msi_chip_remove(struct msi_chip *chip)
+{
+        mutex_lock(&of_pci_msi_chip_mutex);
+        list_del(&chip->list);
+        mutex_unlock(&of_pci_msi_chip_mutex);
+}
+EXPORT_SYMBOL_GPL(of_pci_msi_chip_remove);
+
+struct msi_chip *of_pci_find_msi_chip_by_node(struct device_node *of_node)
+{
+        struct msi_chip *c;
+
+        mutex_lock(&of_pci_msi_chip_mutex);
+        list_for_each_entry(c, &of_pci_msi_chip_list, list) {
+                if (c->of_node == of_node) {
+                        mutex_unlock(&of_pci_msi_chip_mutex);
+                        return c;
+                }
+        }
+        mutex_unlock(&of_pci_msi_chip_mutex);
+
+        return NULL;
+}
+EXPORT_SYMBOL_GPL(of_pci_find_msi_chip_by_node);
+
+#endif /* CONFIG_PCI_MSI */
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 81944fb73116..b6a99f7a9b20 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -1,13 +1,9 @@
 #
 # PCI configuration
 #
-config ARCH_SUPPORTS_MSI
-        bool
-
 config PCI_MSI
         bool "Message Signaled Interrupts (MSI and MSI-X)"
         depends on PCI
-        depends on ARCH_SUPPORTS_MSI
         help
            This allows device drivers to enable MSI (Message Signaled
            Interrupts).  Message Signaled Interrupts enable a device to
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index e5ba4eb4e5b3..3d9504811126 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -15,4 +15,8 @@ config PCI_EXYNOS
         select PCIEPORTBUS
         select PCIE_DW
 
+config PCI_TEGRA
+        bool "NVIDIA Tegra PCIe controller"
+        depends on ARCH_TEGRA
+
 endmenu
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index ab79ccb5bbff..c9a997b2690d 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -1,3 +1,4 @@
 obj-$(CONFIG_PCIE_DW) += pcie-designware.o
 obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
 obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
+obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o
diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c
index ce1543a584a3..729d5a101d62 100644
--- a/drivers/pci/host/pci-mvebu.c
+++ b/drivers/pci/host/pci-mvebu.c
@@ -119,6 +119,10 @@ struct mvebu_pcie_port {
         u32 port;
         u32 lane;
         int devfn;
+        unsigned int mem_target;
+        unsigned int mem_attr;
+        unsigned int io_target;
+        unsigned int io_attr;
         struct clk *clk;
         struct mvebu_sw_pci_bridge bridge;
         struct device_node *dn;
@@ -303,10 +307,9 @@ static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)
                             (port->bridge.iolimitupper << 16)) -
                             iobase);
 
-        mvebu_mbus_add_window_remap_flags(port->name, port->iowin_base,
-                                          port->iowin_size,
-                                          iobase,
-                                          MVEBU_MBUS_PCI_IO);
+        mvebu_mbus_add_window_remap_by_id(port->io_target, port->io_attr,
+                                          port->iowin_base, port->iowin_size,
+                                          iobase);
 
         pci_ioremap_io(iobase, port->iowin_base);
 }
@@ -338,10 +341,8 @@ static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
                 (((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) -
                 port->memwin_base;
 
-        mvebu_mbus_add_window_remap_flags(port->name, port->memwin_base,
-                                          port->memwin_size,
-                                          MVEBU_MBUS_NO_REMAP,
-                                          MVEBU_MBUS_PCI_MEM);
+        mvebu_mbus_add_window_by_id(port->mem_target, port->mem_attr,
+                                    port->memwin_base, port->memwin_size);
 }
 
 /*
@@ -636,6 +637,8 @@ static int __init mvebu_pcie_setup(int nr, struct pci_sys_data *sys)
 
         for (i = 0; i < pcie->nports; i++) {
                 struct mvebu_pcie_port *port = &pcie->ports[i];
+                if (!port->base)
+                        continue;
                 mvebu_pcie_setup_hw(port);
         }
 
@@ -730,12 +733,54 @@ mvebu_pcie_map_registers(struct platform_device *pdev,
         return devm_ioremap_resource(&pdev->dev, &regs);
 }
 
+#define DT_FLAGS_TO_TYPE(flags)       (((flags) >> 24) & 0x03)
+#define    DT_TYPE_IO                 0x1
+#define    DT_TYPE_MEM32              0x2
+#define DT_CPUADDR_TO_TARGET(cpuaddr) (((cpuaddr) >> 56) & 0xFF)
+#define DT_CPUADDR_TO_ATTR(cpuaddr)   (((cpuaddr) >> 48) & 0xFF)
+
+static int mvebu_get_tgt_attr(struct device_node *np, int devfn,
+                              unsigned long type, int *tgt, int *attr)
+{
+        const int na = 3, ns = 2;
+        const __be32 *range;
+        int rlen, nranges, rangesz, pna, i;
+
+        range = of_get_property(np, "ranges", &rlen);
+        if (!range)
+                return -EINVAL;
+
+        pna = of_n_addr_cells(np);
+        rangesz = pna + na + ns;
+        nranges = rlen / sizeof(__be32) / rangesz;
+
+        for (i = 0; i < nranges; i++) {
+                u32 flags = of_read_number(range, 1);
+                u32 slot = of_read_number(range, 2);
+                u64 cpuaddr = of_read_number(range + na, pna);
+                unsigned long rtype;
+
+                if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_IO)
+                        rtype = IORESOURCE_IO;
+                else if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_MEM32)
+                        rtype = IORESOURCE_MEM;
+
+                if (slot == PCI_SLOT(devfn) && type == rtype) {
+                        *tgt = DT_CPUADDR_TO_TARGET(cpuaddr);
+                        *attr = DT_CPUADDR_TO_ATTR(cpuaddr);
+                        return 0;
+                }
+
+                range += rangesz;
+        }
+
+        return -ENOENT;
+}
+
 static int __init mvebu_pcie_probe(struct platform_device *pdev)
 {
         struct mvebu_pcie *pcie;
         struct device_node *np = pdev->dev.of_node;
-        struct of_pci_range range;
-        struct of_pci_range_parser parser;
         struct device_node *child;
         int i, ret;
 
@@ -746,29 +791,25 @@ static int __init mvebu_pcie_probe(struct platform_device *pdev)
 
         pcie->pdev = pdev;
 
-        if (of_pci_range_parser_init(&parser, np))
+        /* Get the PCIe memory and I/O aperture */
+        mvebu_mbus_get_pcie_mem_aperture(&pcie->mem);
+        if (resource_size(&pcie->mem) == 0) {
+                dev_err(&pdev->dev, "invalid memory aperture size\n");
                 return -EINVAL;
+        }
 
-        /* Get the I/O and memory ranges from DT */
-        for_each_of_pci_range(&parser, &range) {
-                unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
-                if (restype == IORESOURCE_IO) {
-                        of_pci_range_to_resource(&range, np, &pcie->io);
-                        of_pci_range_to_resource(&range, np, &pcie->realio);
-                        pcie->io.name = "I/O";
-                        pcie->realio.start = max_t(resource_size_t,
-                                                   PCIBIOS_MIN_IO,
-                                                   range.pci_addr);
-                        pcie->realio.end = min_t(resource_size_t,
-                                                 IO_SPACE_LIMIT,
-                                                 range.pci_addr + range.size);
-                }
-                if (restype == IORESOURCE_MEM) {
-                        of_pci_range_to_resource(&range, np, &pcie->mem);
-                        pcie->mem.name = "MEM";
-                }
+        mvebu_mbus_get_pcie_io_aperture(&pcie->io);
+        if (resource_size(&pcie->io) == 0) {
+                dev_err(&pdev->dev, "invalid I/O aperture size\n");
+                return -EINVAL;
         }
 
+        pcie->realio.flags = pcie->io.flags;
+        pcie->realio.start = PCIBIOS_MIN_IO;
+        pcie->realio.end = min_t(resource_size_t,
+                                  IO_SPACE_LIMIT,
+                                  resource_size(&pcie->io));
+
         /* Get the bus range */
         ret = of_pci_parse_bus_range(np, &pcie->busn);
         if (ret) {
@@ -816,6 +857,22 @@ static int __init mvebu_pcie_probe(struct platform_device *pdev)
                 if (port->devfn < 0)
                         continue;
 
+                ret = mvebu_get_tgt_attr(np, port->devfn, IORESOURCE_MEM,
+                                         &port->mem_target, &port->mem_attr);
+                if (ret < 0) {
+                        dev_err(&pdev->dev, "PCIe%d.%d: cannot get tgt/attr for mem window\n",
+                                port->port, port->lane);
+                        continue;
+                }
+
+                ret = mvebu_get_tgt_attr(np, port->devfn, IORESOURCE_IO,
+                                         &port->io_target, &port->io_attr);
+                if (ret < 0) {
+                        dev_err(&pdev->dev, "PCIe%d.%d: cannot get tgt/attr for io window\n",
+                                port->port, port->lane);
+                        continue;
+                }
+
                 port->base = mvebu_pcie_map_registers(pdev, child, port);
                 if (IS_ERR(port->base)) {
                         dev_err(&pdev->dev, "PCIe%d.%d: cannot map registers\n",
diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
new file mode 100644
index 000000000000..2e9888a0635a
--- /dev/null
+++ b/drivers/pci/host/pci-tegra.c
@@ -0,0 +1,1691 @@
+/*
+ * PCIe host controller driver for Tegra SoCs
+ *
+ * Copyright (c) 2010, CompuLab, Ltd.
+ * Author: Mike Rapoport <mike@compulab.co.il>
+ *
+ * Based on NVIDIA PCIe driver
+ * Copyright (c) 2008-2009, NVIDIA Corporation.
+ *
+ * Bits taken from arch/arm/mach-dove/pcie.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/clk.h>
+#include <linux/clk/tegra.h>
+#include <linux/delay.h>
+#include <linux/export.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/msi.h>
+#include <linux/of_address.h>
+#include <linux/of_pci.h>
+#include <linux/of_platform.h>
+#include <linux/pci.h>
+#include <linux/platform_device.h>
+#include <linux/sizes.h>
+#include <linux/slab.h>
+#include <linux/tegra-cpuidle.h>
+#include <linux/tegra-powergate.h>
+#include <linux/vmalloc.h>
+#include <linux/regulator/consumer.h>
+
+#include <asm/mach/irq.h>
+#include <asm/mach/map.h>
+#include <asm/mach/pci.h>
+
+#define INT_PCI_MSI_NR (8 * 32)
+
+/* register definitions */
+
+#define AFI_AXI_BAR0_SZ 0x00
+#define AFI_AXI_BAR1_SZ 0x04
+#define AFI_AXI_BAR2_SZ 0x08
+#define AFI_AXI_BAR3_SZ 0x0c
+#define AFI_AXI_BAR4_SZ 0x10
+#define AFI_AXI_BAR5_SZ 0x14
+
+#define AFI_AXI_BAR0_START      0x18
+#define AFI_AXI_BAR1_START      0x1c
+#define AFI_AXI_BAR2_START      0x20
+#define AFI_AXI_BAR3_START      0x24
+#define AFI_AXI_BAR4_START      0x28
+#define AFI_AXI_BAR5_START      0x2c
+
+#define AFI_FPCI_BAR0   0x30
+#define AFI_FPCI_BAR1   0x34
+#define AFI_FPCI_BAR2   0x38
+#define AFI_FPCI_BAR3   0x3c
+#define AFI_FPCI_BAR4   0x40
+#define AFI_FPCI_BAR5   0x44
+
+#define AFI_CACHE_BAR0_SZ       0x48
+#define AFI_CACHE_BAR0_ST       0x4c
+#define AFI_CACHE_BAR1_SZ       0x50
+#define AFI_CACHE_BAR1_ST       0x54
+
+#define AFI_MSI_BAR_SZ          0x60
+#define AFI_MSI_FPCI_BAR_ST     0x64
+#define AFI_MSI_AXI_BAR_ST      0x68
+
+#define AFI_MSI_VEC0            0x6c
+#define AFI_MSI_VEC1            0x70
+#define AFI_MSI_VEC2            0x74
+#define AFI_MSI_VEC3            0x78
+#define AFI_MSI_VEC4            0x7c
+#define AFI_MSI_VEC5            0x80
+#define AFI_MSI_VEC6            0x84
+#define AFI_MSI_VEC7            0x88
+
+#define AFI_MSI_EN_VEC0         0x8c
+#define AFI_MSI_EN_VEC1         0x90
+#define AFI_MSI_EN_VEC2         0x94
+#define AFI_MSI_EN_VEC3         0x98
+#define AFI_MSI_EN_VEC4         0x9c
+#define AFI_MSI_EN_VEC5         0xa0
+#define AFI_MSI_EN_VEC6         0xa4
+#define AFI_MSI_EN_VEC7         0xa8
+
+#define AFI_CONFIGURATION               0xac
+#define  AFI_CONFIGURATION_EN_FPCI      (1 << 0)
+
+#define AFI_FPCI_ERROR_MASKS    0xb0
+
+#define AFI_INTR_MASK           0xb4
+#define  AFI_INTR_MASK_INT_MASK (1 << 0)
+#define  AFI_INTR_MASK_MSI_MASK (1 << 8)
+
+#define AFI_INTR_CODE                   0xb8
+#define  AFI_INTR_CODE_MASK             0xf
+#define  AFI_INTR_AXI_SLAVE_ERROR       1
+#define  AFI_INTR_AXI_DECODE_ERROR      2
+#define  AFI_INTR_TARGET_ABORT          3
+#define  AFI_INTR_MASTER_ABORT          4
+#define  AFI_INTR_INVALID_WRITE         5
+#define  AFI_INTR_LEGACY                6
+#define  AFI_INTR_FPCI_DECODE_ERROR     7
+
+#define AFI_INTR_SIGNATURE      0xbc
+#define AFI_UPPER_FPCI_ADDRESS  0xc0
+#define AFI_SM_INTR_ENABLE      0xc4
+#define  AFI_SM_INTR_INTA_ASSERT        (1 << 0)
+#define  AFI_SM_INTR_INTB_ASSERT        (1 << 1)
+#define  AFI_SM_INTR_INTC_ASSERT        (1 << 2)
+#define  AFI_SM_INTR_INTD_ASSERT        (1 << 3)
+#define  AFI_SM_INTR_INTA_DEASSERT      (1 << 4)
+#define  AFI_SM_INTR_INTB_DEASSERT      (1 << 5)
+#define  AFI_SM_INTR_INTC_DEASSERT      (1 << 6)
+#define  AFI_SM_INTR_INTD_DEASSERT      (1 << 7)
+
+#define AFI_AFI_INTR_ENABLE             0xc8
+#define  AFI_INTR_EN_INI_SLVERR         (1 << 0)
+#define  AFI_INTR_EN_INI_DECERR         (1 << 1)
+#define  AFI_INTR_EN_TGT_SLVERR         (1 << 2)
+#define  AFI_INTR_EN_TGT_DECERR         (1 << 3)
+#define  AFI_INTR_EN_TGT_WRERR          (1 << 4)
+#define  AFI_INTR_EN_DFPCI_DECERR       (1 << 5)
+#define  AFI_INTR_EN_AXI_DECERR         (1 << 6)
+#define  AFI_INTR_EN_FPCI_TIMEOUT       (1 << 7)
+#define  AFI_INTR_EN_PRSNT_SENSE        (1 << 8)
+
+#define AFI_PCIE_CONFIG                                 0x0f8
+#define  AFI_PCIE_CONFIG_PCIE_DISABLE(x)                (1 << ((x) + 1))
+#define  AFI_PCIE_CONFIG_PCIE_DISABLE_ALL               0xe
+#define  AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK       (0xf << 20)
+#define  AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE     (0x0 << 20)
+#define  AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420        (0x0 << 20)
+#define  AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL       (0x1 << 20)
+#define  AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222        (0x1 << 20)
+#define  AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411        (0x2 << 20)
+
+#define AFI_FUSE                        0x104
+#define  AFI_FUSE_PCIE_T0_GEN2_DIS      (1 << 2)
+
+#define AFI_PEX0_CTRL                   0x110
+#define AFI_PEX1_CTRL                   0x118
+#define AFI_PEX2_CTRL                   0x128
+#define  AFI_PEX_CTRL_RST               (1 << 0)
+#define  AFI_PEX_CTRL_CLKREQ_EN         (1 << 1)
+#define  AFI_PEX_CTRL_REFCLK_EN         (1 << 3)
+
+#define AFI_PEXBIAS_CTRL_0              0x168
+
+#define RP_VEND_XP      0x00000F00
+#define  RP_VEND_XP_DL_UP       (1 << 30)
+
+#define RP_LINK_CONTROL_STATUS                  0x00000090
+#define  RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE  0x20000000
+#define  RP_LINK_CONTROL_STATUS_LINKSTAT_MASK   0x3fff0000
+
+#define PADS_CTL_SEL            0x0000009C
+
+#define PADS_CTL                0x000000A0
+#define  PADS_CTL_IDDQ_1L       (1 << 0)
+#define  PADS_CTL_TX_DATA_EN_1L (1 << 6)
+#define  PADS_CTL_RX_DATA_EN_1L (1 << 10)
+
+#define PADS_PLL_CTL_TEGRA20                    0x000000B8
+#define PADS_PLL_CTL_TEGRA30                    0x000000B4
+#define  PADS_PLL_CTL_RST_B4SM                  (1 << 1)
+#define  PADS_PLL_CTL_LOCKDET                   (1 << 8)
+#define  PADS_PLL_CTL_REFCLK_MASK               (0x3 << 16)
+#define  PADS_PLL_CTL_REFCLK_INTERNAL_CML       (0 << 16)
+#define  PADS_PLL_CTL_REFCLK_INTERNAL_CMOS      (1 << 16)
+#define  PADS_PLL_CTL_REFCLK_EXTERNAL           (2 << 16)
+#define  PADS_PLL_CTL_TXCLKREF_MASK             (0x1 << 20)
+#define  PADS_PLL_CTL_TXCLKREF_DIV10            (0 << 20)
+#define  PADS_PLL_CTL_TXCLKREF_DIV5             (1 << 20)
+#define  PADS_PLL_CTL_TXCLKREF_BUF_EN           (1 << 22)
+
+#define PADS_REFCLK_CFG0                        0x000000C8
+#define PADS_REFCLK_CFG1                        0x000000CC
+
+/*
+ * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit
+ * entries, one entry per PCIe port. These field definitions and desired
+ * values aren't in the TRM, but do come from NVIDIA.
+ */
+#define PADS_REFCLK_CFG_TERM_SHIFT              2  /* 6:2 */
+#define PADS_REFCLK_CFG_E_TERM_SHIFT            7
+#define PADS_REFCLK_CFG_PREDI_SHIFT             8  /* 11:8 */
+#define PADS_REFCLK_CFG_DRVI_SHIFT              12 /* 15:12 */
+
+/* Default value provided by HW engineering is 0xfa5c */
+#define PADS_REFCLK_CFG_VALUE \
+        ( \
+                (0x17 << PADS_REFCLK_CFG_TERM_SHIFT)   | \
+                (0    << PADS_REFCLK_CFG_E_TERM_SHIFT) | \
+                (0xa  << PADS_REFCLK_CFG_PREDI_SHIFT)  | \
+                (0xf  << PADS_REFCLK_CFG_DRVI_SHIFT)     \
+        )
+
+struct tegra_msi {
+        struct msi_chip chip;
+        DECLARE_BITMAP(used, INT_PCI_MSI_NR);
+        struct irq_domain *domain;
+        unsigned long pages;
+        struct mutex lock;
+        int irq;
+};
+
+/* used to differentiate between Tegra SoC generations */
+struct tegra_pcie_soc_data {
+        unsigned int num_ports;
+        unsigned int msi_base_shift;
+        u32 pads_pll_ctl;
+        u32 tx_ref_sel;
+        bool has_pex_clkreq_en;
+        bool has_pex_bias_ctrl;
+        bool has_intr_prsnt_sense;
+        bool has_avdd_supply;
+        bool has_cml_clk;
+};
+
+static inline struct tegra_msi *to_tegra_msi(struct msi_chip *chip)
+{
+        return container_of(chip, struct tegra_msi, chip);
+}
+
+struct tegra_pcie {
+        struct device *dev;
+
+        void __iomem *pads;
+        void __iomem *afi;
+        int irq;
+
+        struct list_head busses;
+        struct resource *cs;
+
+        struct resource io;
+        struct resource mem;
+        struct resource prefetch;
+        struct resource busn;
+
+        struct clk *pex_clk;
+        struct clk *afi_clk;
+        struct clk *pcie_xclk;
+        struct clk *pll_e;
+        struct clk *cml_clk;
+
+        struct tegra_msi msi;
+
+        struct list_head ports;
+        unsigned int num_ports;
+        u32 xbar_config;
+
+        struct regulator *pex_clk_supply;
+        struct regulator *vdd_supply;
+        struct regulator *avdd_supply;
+
+        const struct tegra_pcie_soc_data *soc_data;
+};
+
+struct tegra_pcie_port {
+        struct tegra_pcie *pcie;
+        struct list_head list;
+        struct resource regs;
+        void __iomem *base;
+        unsigned int index;
+        unsigned int lanes;
+};
+
+struct tegra_pcie_bus {
+        struct vm_struct *area;
+        struct list_head list;
+        unsigned int nr;
+};
+
+static inline struct tegra_pcie *sys_to_pcie(struct pci_sys_data *sys)
+{
+        return sys->private_data;
+}
+
+static inline void afi_writel(struct tegra_pcie *pcie, u32 value,
+                              unsigned long offset)
+{
+        writel(value, pcie->afi + offset);
+}
+
+static inline u32 afi_readl(struct tegra_pcie *pcie, unsigned long offset)
+{
+        return readl(pcie->afi + offset);
+}
+
+static inline void pads_writel(struct tegra_pcie *pcie, u32 value,
+                               unsigned long offset)
+{
+        writel(value, pcie->pads + offset);
+}
+
+static inline u32 pads_readl(struct tegra_pcie *pcie, unsigned long offset)
+{
+        return readl(pcie->pads + offset);
+}
+
+/*
+ * The configuration space mapping on Tegra is somewhat similar to the ECAM
+ * defined by PCIe. However it deviates a bit in how the 4 bits for extended
+ * register accesses are mapped:
+ *
+ *    [27:24] extended register number
+ *    [23:16] bus number
+ *    [15:11] device number
+ *    [10: 8] function number
+ *    [ 7: 0] register number
+ *
+ * Mapping the whole extended configuration space would require 256 MiB of
+ * virtual address space, only a small part of which will actually be used.
+ * To work around this, a 1 MiB of virtual addresses are allocated per bus
+ * when the bus is first accessed. When the physical range is mapped, the
+ * the bus number bits are hidden so that the extended register number bits
+ * appear as bits [19:16]. Therefore the virtual mapping looks like this:
+ *
+ *    [19:16] extended register number
+ *    [15:11] device number
+ *    [10: 8] function number
+ *    [ 7: 0] register number
+ *
+ * This is achieved by stitching together 16 chunks of 64 KiB of physical
+ * address space via the MMU.
+ */
+static unsigned long tegra_pcie_conf_offset(unsigned int devfn, int where)
+{
+        return ((where & 0xf00) << 8) | (PCI_SLOT(devfn) << 11) |
+               (PCI_FUNC(devfn) << 8) | (where & 0xfc);
+}
+
+static struct tegra_pcie_bus *tegra_pcie_bus_alloc(struct tegra_pcie *pcie,
+                                                   unsigned int busnr)
+{
+        pgprot_t prot = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | L_PTE_XN |
+                        L_PTE_MT_DEV_SHARED | L_PTE_SHARED;
+        phys_addr_t cs = pcie->cs->start;
+        struct tegra_pcie_bus *bus;
+        unsigned int i;
+        int err;
+
+        bus = kzalloc(sizeof(*bus), GFP_KERNEL);
+        if (!bus)
+                return ERR_PTR(-ENOMEM);
+
+        INIT_LIST_HEAD(&bus->list);
+        bus->nr = busnr;
+
+        /* allocate 1 MiB of virtual addresses */
+        bus->area = get_vm_area(SZ_1M, VM_IOREMAP);
+        if (!bus->area) {
+                err = -ENOMEM;
+                goto free;
+        }
+
+        /* map each of the 16 chunks of 64 KiB each */
+        for (i = 0; i < 16; i++) {
+                unsigned long virt = (unsigned long)bus->area->addr +
+                                     i * SZ_64K;
+                phys_addr_t phys = cs + i * SZ_1M + busnr * SZ_64K;
+
+                err = ioremap_page_range(virt, virt + SZ_64K, phys, prot);
+                if (err < 0) {
+                        dev_err(pcie->dev, "ioremap_page_range() failed: %d\n",
+                                err);
+                        goto unmap;
+                }
+        }
+
+        return bus;
+
+unmap:
+        vunmap(bus->area->addr);
+free:
+        kfree(bus);
+        return ERR_PTR(err);
+}
+
+/*
+ * Look up a virtual address mapping for the specified bus number. If no such
+ * mapping existis, try to create one.
+ */
+static void __iomem *tegra_pcie_bus_map(struct tegra_pcie *pcie,
+                                        unsigned int busnr)
+{
+        struct tegra_pcie_bus *bus;
+
+        list_for_each_entry(bus, &pcie->busses, list)
+                if (bus->nr == busnr)
+                        return bus->area->addr;
+
+        bus = tegra_pcie_bus_alloc(pcie, busnr);
+        if (IS_ERR(bus))
+                return NULL;
+
+        list_add_tail(&bus->list, &pcie->busses);
+
+        return bus->area->addr;
+}
+
+static void __iomem *tegra_pcie_conf_address(struct pci_bus *bus,
+                                             unsigned int devfn,
+                                             int where)
+{
+        struct tegra_pcie *pcie = sys_to_pcie(bus->sysdata);
+        void __iomem *addr = NULL;
+
+        if (bus->number == 0) {
+                unsigned int slot = PCI_SLOT(devfn);
+                struct tegra_pcie_port *port;
+
+                list_for_each_entry(port, &pcie->ports, list) {
+                        if (port->index + 1 == slot) {
+                                addr = port->base + (where & ~3);
+                                break;
+                        }
+                }
+        } else {
+                addr = tegra_pcie_bus_map(pcie, bus->number);
+                if (!addr) {
+                        dev_err(pcie->dev,
+                                "failed to map cfg. space for bus %u\n",
+                                bus->number);
+                        return NULL;
+                }
+
+                addr += tegra_pcie_conf_offset(devfn, where);
+        }
+
+        return addr;
+}
+
+static int tegra_pcie_read_conf(struct pci_bus *bus, unsigned int devfn,
+                                int where, int size, u32 *value)
+{
+        void __iomem *addr;
+
+        addr = tegra_pcie_conf_address(bus, devfn, where);
+        if (!addr) {
+                *value = 0xffffffff;
+                return PCIBIOS_DEVICE_NOT_FOUND;
+        }
+
+        *value = readl(addr);
+
+        if (size == 1)
+                *value = (*value >> (8 * (where & 3))) & 0xff;
+        else if (size == 2)
+                *value = (*value >> (8 * (where & 3))) & 0xffff;
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+static int tegra_pcie_write_conf(struct pci_bus *bus, unsigned int devfn,
+                                 int where, int size, u32 value)
+{
+        void __iomem *addr;
+        u32 mask, tmp;
+
+        addr = tegra_pcie_conf_address(bus, devfn, where);
+        if (!addr)
+                return PCIBIOS_DEVICE_NOT_FOUND;
+
+        if (size == 4) {
+                writel(value, addr);
+                return PCIBIOS_SUCCESSFUL;
+        }
+
+        if (size == 2)
+                mask = ~(0xffff << ((where & 0x3) * 8));
+        else if (size == 1)
+                mask = ~(0xff << ((where & 0x3) * 8));
+        else
+                return PCIBIOS_BAD_REGISTER_NUMBER;
+
+        tmp = readl(addr) & mask;
+        tmp |= value << ((where & 0x3) * 8);
+        writel(tmp, addr);
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+static struct pci_ops tegra_pcie_ops = {
+        .read = tegra_pcie_read_conf,
+        .write = tegra_pcie_write_conf,
+};
+
+static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port)
+{
+        unsigned long ret = 0;
+
+        switch (port->index) {
+        case 0:
+                ret = AFI_PEX0_CTRL;
+                break;
+
+        case 1:
+                ret = AFI_PEX1_CTRL;
+                break;
+
+        case 2:
+                ret = AFI_PEX2_CTRL;
+                break;
+        }
+
+        return ret;
+}
+
+static void tegra_pcie_port_reset(struct tegra_pcie_port *port)
+{
+        unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
+        unsigned long value;
+
+        /* pulse reset signal */
+        value = afi_readl(port->pcie, ctrl);
+        value &= ~AFI_PEX_CTRL_RST;
+        afi_writel(port->pcie, value, ctrl);
+
+        usleep_range(1000, 2000);
+
+        value = afi_readl(port->pcie, ctrl);
+        value |= AFI_PEX_CTRL_RST;
+        afi_writel(port->pcie, value, ctrl);
+}
+
+static void tegra_pcie_port_enable(struct tegra_pcie_port *port)
+{
+        const struct tegra_pcie_soc_data *soc = port->pcie->soc_data;
+        unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
+        unsigned long value;
+
+        /* enable reference clock */
+        value = afi_readl(port->pcie, ctrl);
+        value |= AFI_PEX_CTRL_REFCLK_EN;
+
+        if (soc->has_pex_clkreq_en)
+                value |= AFI_PEX_CTRL_CLKREQ_EN;
+
+        afi_writel(port->pcie, value, ctrl);
+
+        tegra_pcie_port_reset(port);
+}
+
+static void tegra_pcie_port_disable(struct tegra_pcie_port *port)
+{
+        unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
+        unsigned long value;
+
+        /* assert port reset */
+        value = afi_readl(port->pcie, ctrl);
+        value &= ~AFI_PEX_CTRL_RST;
+        afi_writel(port->pcie, value, ctrl);
+
+        /* disable reference clock */
+        value = afi_readl(port->pcie, ctrl);
+        value &= ~AFI_PEX_CTRL_REFCLK_EN;
+        afi_writel(port->pcie, value, ctrl);
+}
+
+static void tegra_pcie_port_free(struct tegra_pcie_port *port)
+{
+        struct tegra_pcie *pcie = port->pcie;
+
+        devm_iounmap(pcie->dev, port->base);
+        devm_release_mem_region(pcie->dev, port->regs.start,
+                                resource_size(&port->regs));
+        list_del(&port->list);
+        devm_kfree(pcie->dev, port);
+}
+
+static void tegra_pcie_fixup_bridge(struct pci_dev *dev)
+{
+        u16 reg;
+
+        if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE) {
+                pci_read_config_word(dev, PCI_COMMAND, &reg);
+                reg |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
+                        PCI_COMMAND_MASTER | PCI_COMMAND_SERR);
+                pci_write_config_word(dev, PCI_COMMAND, reg);
+        }
+}
+DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_fixup_bridge);
+
+/* Tegra PCIE root complex wrongly reports device class */
+static void tegra_pcie_fixup_class(struct pci_dev *dev)
+{
+        dev->class = PCI_CLASS_BRIDGE_PCI << 8;
+}
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0, tegra_pcie_fixup_class);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1, tegra_pcie_fixup_class);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1c, tegra_pcie_fixup_class);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1d, tegra_pcie_fixup_class);
+
+/* Tegra PCIE requires relaxed ordering */
+static void tegra_pcie_relax_enable(struct pci_dev *dev)
+{
+        pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN);
+}
+DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_relax_enable);
+
+static int tegra_pcie_setup(int nr, struct pci_sys_data *sys)
+{
+        struct tegra_pcie *pcie = sys_to_pcie(sys);
+
+        pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset);
+        pci_add_resource_offset(&sys->resources, &pcie->prefetch,
+                                sys->mem_offset);
+        pci_add_resource(&sys->resources, &pcie->busn);
+
+        pci_ioremap_io(nr * SZ_64K, pcie->io.start);
+
+        return 1;
+}
+
+static int tegra_pcie_map_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
+{
+        struct tegra_pcie *pcie = sys_to_pcie(pdev->bus->sysdata);
+
+        tegra_cpuidle_pcie_irqs_in_use();
+
+        return pcie->irq;
+}
+
+static void tegra_pcie_add_bus(struct pci_bus *bus)
+{
+        if (IS_ENABLED(CONFIG_PCI_MSI)) {
+                struct tegra_pcie *pcie = sys_to_pcie(bus->sysdata);
+
+                bus->msi = &pcie->msi.chip;
+        }
+}
+
+static struct pci_bus *tegra_pcie_scan_bus(int nr, struct pci_sys_data *sys)
+{
+        struct tegra_pcie *pcie = sys_to_pcie(sys);
+        struct pci_bus *bus;
+
+        bus = pci_create_root_bus(pcie->dev, sys->busnr, &tegra_pcie_ops, sys,
+                                  &sys->resources);
+        if (!bus)
+                return NULL;
+
+        pci_scan_child_bus(bus);
+
+        return bus;
+}
+
+static irqreturn_t tegra_pcie_isr(int irq, void *arg)
+{
+        const char *err_msg[] = {
+                "Unknown",
+                "AXI slave error",
+                "AXI decode error",
+                "Target abort",
+                "Master abort",
+                "Invalid write",
+                "Response decoding error",
+                "AXI response decoding error",
+                "Transaction timeout",
+        };
+        struct tegra_pcie *pcie = arg;
+        u32 code, signature;
+
+        code = afi_readl(pcie, AFI_INTR_CODE) & AFI_INTR_CODE_MASK;
+        signature = afi_readl(pcie, AFI_INTR_SIGNATURE);
+        afi_writel(pcie, 0, AFI_INTR_CODE);
+
+        if (code == AFI_INTR_LEGACY)
+                return IRQ_NONE;
+
+        if (code >= ARRAY_SIZE(err_msg))
+                code = 0;
+
+        /*
+         * do not pollute kernel log with master abort reports since they
+         * happen a lot during enumeration
+         */
+        if (code == AFI_INTR_MASTER_ABORT)
+                dev_dbg(pcie->dev, "%s, signature: %08x\n", err_msg[code],
+                        signature);
+        else
+                dev_err(pcie->dev, "%s, signature: %08x\n", err_msg[code],
+                        signature);
+
+        if (code == AFI_INTR_TARGET_ABORT || code == AFI_INTR_MASTER_ABORT ||
+            code == AFI_INTR_FPCI_DECODE_ERROR) {
+                u32 fpci = afi_readl(pcie, AFI_UPPER_FPCI_ADDRESS) & 0xff;
+                u64 address = (u64)fpci << 32 | (signature & 0xfffffffc);
+
+                if (code == AFI_INTR_MASTER_ABORT)
+                        dev_dbg(pcie->dev, "  FPCI address: %10llx\n", address);
+                else
+                        dev_err(pcie->dev, "  FPCI address: %10llx\n", address);
+        }
+
+        return IRQ_HANDLED;
+}
+
+/*
+ * FPCI map is as follows:
+ * - 0xfdfc000000: I/O space
+ * - 0xfdfe000000: type 0 configuration space
+ * - 0xfdff000000: type 1 configuration space
+ * - 0xfe00000000: type 0 extended configuration space
+ * - 0xfe10000000: type 1 extended configuration space
+ */
+static void tegra_pcie_setup_translations(struct tegra_pcie *pcie)
+{
+        u32 fpci_bar, size, axi_address;
+
+        /* Bar 0: type 1 extended configuration space */
+        fpci_bar = 0xfe100000;
+        size = resource_size(pcie->cs);
+        axi_address = pcie->cs->start;
+        afi_writel(pcie, axi_address, AFI_AXI_BAR0_START);
+        afi_writel(pcie, size >> 12, AFI_AXI_BAR0_SZ);
+        afi_writel(pcie, fpci_bar, AFI_FPCI_BAR0);
+
+        /* Bar 1: downstream IO bar */
+        fpci_bar = 0xfdfc0000;
+        size = resource_size(&pcie->io);
+        axi_address = pcie->io.start;
+        afi_writel(pcie, axi_address, AFI_AXI_BAR1_START);
+        afi_writel(pcie, size >> 12, AFI_AXI_BAR1_SZ);
+        afi_writel(pcie, fpci_bar, AFI_FPCI_BAR1);
+
+        /* Bar 2: prefetchable memory BAR */
+        fpci_bar = (((pcie->prefetch.start >> 12) & 0x0fffffff) << 4) | 0x1;
+        size = resource_size(&pcie->prefetch);
+        axi_address = pcie->prefetch.start;
+        afi_writel(pcie, axi_address, AFI_AXI_BAR2_START);
+        afi_writel(pcie, size >> 12, AFI_AXI_BAR2_SZ);
+        afi_writel(pcie, fpci_bar, AFI_FPCI_BAR2);
+
+        /* Bar 3: non prefetchable memory BAR */
+        fpci_bar = (((pcie->mem.start >> 12) & 0x0fffffff) << 4) | 0x1;
+        size = resource_size(&pcie->mem);
+        axi_address = pcie->mem.start;
+        afi_writel(pcie, axi_address, AFI_AXI_BAR3_START);
+        afi_writel(pcie, size >> 12, AFI_AXI_BAR3_SZ);
+        afi_writel(pcie, fpci_bar, AFI_FPCI_BAR3);
+
+        /* NULL out the remaining BARs as they are not used */
+        afi_writel(pcie, 0, AFI_AXI_BAR4_START);
+        afi_writel(pcie, 0, AFI_AXI_BAR4_SZ);
+        afi_writel(pcie, 0, AFI_FPCI_BAR4);
+
+        afi_writel(pcie, 0, AFI_AXI_BAR5_START);
+        afi_writel(pcie, 0, AFI_AXI_BAR5_SZ);
+        afi_writel(pcie, 0, AFI_FPCI_BAR5);
+
+        /* map all upstream transactions as uncached */
+        afi_writel(pcie, PHYS_OFFSET, AFI_CACHE_BAR0_ST);
+        afi_writel(pcie, 0, AFI_CACHE_BAR0_SZ);
+        afi_writel(pcie, 0, AFI_CACHE_BAR1_ST);
+        afi_writel(pcie, 0, AFI_CACHE_BAR1_SZ);
+
+        /* MSI translations are setup only when needed */
+        afi_writel(pcie, 0, AFI_MSI_FPCI_BAR_ST);
+        afi_writel(pcie, 0, AFI_MSI_BAR_SZ);
+        afi_writel(pcie, 0, AFI_MSI_AXI_BAR_ST);
+        afi_writel(pcie, 0, AFI_MSI_BAR_SZ);
+}
+
+static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
+{
+        const struct tegra_pcie_soc_data *soc = pcie->soc_data;
+        struct tegra_pcie_port *port;
+        unsigned int timeout;
+        unsigned long value;
+
+        /* power down PCIe slot clock bias pad */
+        if (soc->has_pex_bias_ctrl)
+                afi_writel(pcie, 0, AFI_PEXBIAS_CTRL_0);
+
+        /* configure mode and disable all ports */
+        value = afi_readl(pcie, AFI_PCIE_CONFIG);
+        value &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK;
+        value |= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL | pcie->xbar_config;
+
+        list_for_each_entry(port, &pcie->ports, list)
+                value &= ~AFI_PCIE_CONFIG_PCIE_DISABLE(port->index);
+
+        afi_writel(pcie, value, AFI_PCIE_CONFIG);
+
+        value = afi_readl(pcie, AFI_FUSE);
+        value &= ~AFI_FUSE_PCIE_T0_GEN2_DIS;
+        afi_writel(pcie, value, AFI_FUSE);
+
+        /* initialze internal PHY, enable up to 16 PCIE lanes */
+        pads_writel(pcie, 0x0, PADS_CTL_SEL);
+
+        /* override IDDQ to 1 on all 4 lanes */
+        value = pads_readl(pcie, PADS_CTL);
+        value |= PADS_CTL_IDDQ_1L;
+        pads_writel(pcie, value, PADS_CTL);
+
+        /*
+         * Set up PHY PLL inputs select PLLE output as refclock,
+         * set TX ref sel to div10 (not div5).
+         */
+        value = pads_readl(pcie, soc->pads_pll_ctl);
+        value &= ~(PADS_PLL_CTL_REFCLK_MASK | PADS_PLL_CTL_TXCLKREF_MASK);
+        value |= PADS_PLL_CTL_REFCLK_INTERNAL_CML | soc->tx_ref_sel;
+        pads_writel(pcie, value, soc->pads_pll_ctl);
+
+        /* take PLL out of reset  */
+        value = pads_readl(pcie, soc->pads_pll_ctl);
+        value |= PADS_PLL_CTL_RST_B4SM;
+        pads_writel(pcie, value, soc->pads_pll_ctl);
+
+        /* Configure the reference clock driver */
+        value = PADS_REFCLK_CFG_VALUE | (PADS_REFCLK_CFG_VALUE << 16);
+        pads_writel(pcie, value, PADS_REFCLK_CFG0);
+        if (soc->num_ports > 2)
+                pads_writel(pcie, PADS_REFCLK_CFG_VALUE, PADS_REFCLK_CFG1);
+
+        /* wait for the PLL to lock */
+        timeout = 300;
+        do {
+                value = pads_readl(pcie, soc->pads_pll_ctl);
+                usleep_range(1000, 2000);
+                if (--timeout == 0) {
+                        pr_err("Tegra PCIe error: timeout waiting for PLL\n");
+                        return -EBUSY;
+                }
+        } while (!(value & PADS_PLL_CTL_LOCKDET));
+
+        /* turn off IDDQ override */
+        value = pads_readl(pcie, PADS_CTL);
+        value &= ~PADS_CTL_IDDQ_1L;
+        pads_writel(pcie, value, PADS_CTL);
+
+        /* enable TX/RX data */
+        value = pads_readl(pcie, PADS_CTL);
+        value |= PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L;
+        pads_writel(pcie, value, PADS_CTL);
+
+        /* take the PCIe interface module out of reset */
+        tegra_periph_reset_deassert(pcie->pcie_xclk);
+
+        /* finally enable PCIe */
+        value = afi_readl(pcie, AFI_CONFIGURATION);
+        value |= AFI_CONFIGURATION_EN_FPCI;
+        afi_writel(pcie, value, AFI_CONFIGURATION);
+
+        value = AFI_INTR_EN_INI_SLVERR | AFI_INTR_EN_INI_DECERR |
+                AFI_INTR_EN_TGT_SLVERR | AFI_INTR_EN_TGT_DECERR |
+                AFI_INTR_EN_TGT_WRERR | AFI_INTR_EN_DFPCI_DECERR;
+
+        if (soc->has_intr_prsnt_sense)
+                value |= AFI_INTR_EN_PRSNT_SENSE;
+
+        afi_writel(pcie, value, AFI_AFI_INTR_ENABLE);
+        afi_writel(pcie, 0xffffffff, AFI_SM_INTR_ENABLE);
+
+        /* don't enable MSI for now, only when needed */
+        afi_writel(pcie, AFI_INTR_MASK_INT_MASK, AFI_INTR_MASK);
+
+        /* disable all exceptions */
+        afi_writel(pcie, 0, AFI_FPCI_ERROR_MASKS);
+
+        return 0;
+}
+
+static void tegra_pcie_power_off(struct tegra_pcie *pcie)
+{
+        const struct tegra_pcie_soc_data *soc = pcie->soc_data;
+        int err;
+
+        /* TODO: disable and unprepare clocks? */
+
+        tegra_periph_reset_assert(pcie->pcie_xclk);
+        tegra_periph_reset_assert(pcie->afi_clk);
+        tegra_periph_reset_assert(pcie->pex_clk);
+
+        tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
+
+        if (soc->has_avdd_supply) {
+                err = regulator_disable(pcie->avdd_supply);
+                if (err < 0)
+                        dev_warn(pcie->dev,
+                                 "failed to disable AVDD regulator: %d\n",
+                                 err);
+        }
+
+        err = regulator_disable(pcie->pex_clk_supply);
+        if (err < 0)
+                dev_warn(pcie->dev, "failed to disable pex-clk regulator: %d\n",
+                         err);
+
+        err = regulator_disable(pcie->vdd_supply);
+        if (err < 0)
+                dev_warn(pcie->dev, "failed to disable VDD regulator: %d\n",
+                         err);
+}
+
+static int tegra_pcie_power_on(struct tegra_pcie *pcie)
+{
+        const struct tegra_pcie_soc_data *soc = pcie->soc_data;
+        int err;
+
+        tegra_periph_reset_assert(pcie->pcie_xclk);
+        tegra_periph_reset_assert(pcie->afi_clk);
+        tegra_periph_reset_assert(pcie->pex_clk);
+
+        tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
+
+        /* enable regulators */
+        err = regulator_enable(pcie->vdd_supply);
+        if (err < 0) {
+                dev_err(pcie->dev, "failed to enable VDD regulator: %d\n", err);
+                return err;
+        }
+
+        err = regulator_enable(pcie->pex_clk_supply);
+        if (err < 0) {
+                dev_err(pcie->dev, "failed to enable pex-clk regulator: %d\n",
+                        err);
+                return err;
+        }
+
+        if (soc->has_avdd_supply) {
+                err = regulator_enable(pcie->avdd_supply);
+                if (err < 0) {
+                        dev_err(pcie->dev,
+                                "failed to enable AVDD regulator: %d\n",
+                                err);
+                        return err;
+                }
+        }
+
+        err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE,
+                                                pcie->pex_clk);
+        if (err) {
+                dev_err(pcie->dev, "powerup sequence failed: %d\n", err);
+                return err;
+        }
+
+        tegra_periph_reset_deassert(pcie->afi_clk);
+
+        err = clk_prepare_enable(pcie->afi_clk);
+        if (err < 0) {
+                dev_err(pcie->dev, "failed to enable AFI clock: %d\n", err);
+                return err;
+        }
+
+        if (soc->has_cml_clk) {
+                err = clk_prepare_enable(pcie->cml_clk);
+                if (err < 0) {
+                        dev_err(pcie->dev, "failed to enable CML clock: %d\n",
+                                err);
+                        return err;
+                }
+        }
+
+        err = clk_prepare_enable(pcie->pll_e);
+        if (err < 0) {
+                dev_err(pcie->dev, "failed to enable PLLE clock: %d\n", err);
+                return err;
+        }
+
+        return 0;
+}
+
+static int tegra_pcie_clocks_get(struct tegra_pcie *pcie)
+{
+        const struct tegra_pcie_soc_data *soc = pcie->soc_data;
+
+        pcie->pex_clk = devm_clk_get(pcie->dev, "pex");
+        if (IS_ERR(pcie->pex_clk))
+                return PTR_ERR(pcie->pex_clk);
+
+        pcie->afi_clk = devm_clk_get(pcie->dev, "afi");
+        if (IS_ERR(pcie->afi_clk))
+                return PTR_ERR(pcie->afi_clk);
+
+        pcie->pcie_xclk = devm_clk_get(pcie->dev, "pcie_xclk");
+        if (IS_ERR(pcie->pcie_xclk))
+                return PTR_ERR(pcie->pcie_xclk);
+
+        pcie->pll_e = devm_clk_get(pcie->dev, "pll_e");
+        if (IS_ERR(pcie->pll_e))
+                return PTR_ERR(pcie->pll_e);
+
+        if (soc->has_cml_clk) {
+                pcie->cml_clk = devm_clk_get(pcie->dev, "cml");
+                if (IS_ERR(pcie->cml_clk))
+                        return PTR_ERR(pcie->cml_clk);
+        }
+
+        return 0;
+}
+
+static int tegra_pcie_get_resources(struct tegra_pcie *pcie)
+{
+        struct platform_device *pdev = to_platform_device(pcie->dev);
+        struct resource *pads, *afi, *res;
+        int err;
+
+        err = tegra_pcie_clocks_get(pcie);
+        if (err) {
+                dev_err(&pdev->dev, "failed to get clocks: %d\n", err);
+                return err;
+        }
+
+        err = tegra_pcie_power_on(pcie);
+        if (err) {
+                dev_err(&pdev->dev, "failed to power up: %d\n", err);
+                return err;
+        }
+
+        pads = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pads");
+        pcie->pads = devm_ioremap_resource(&pdev->dev, pads);
+        if (IS_ERR(pcie->pads)) {
+                err = PTR_ERR(pcie->pads);
+                goto poweroff;
+        }
+
+        afi = platform_get_resource_byname(pdev, IORESOURCE_MEM, "afi");
+        pcie->afi = devm_ioremap_resource(&pdev->dev, afi);
+        if (IS_ERR(pcie->afi)) {
+                err = PTR_ERR(pcie->afi);
+                goto poweroff;
+        }
+
+        /* request configuration space, but remap later, on demand */
+        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cs");
+        if (!res) {
+                err = -EADDRNOTAVAIL;
+                goto poweroff;
+        }
+
+        pcie->cs = devm_request_mem_region(pcie->dev, res->start,
+                                           resource_size(res), res->name);
+        if (!pcie->cs) {
+                err = -EADDRNOTAVAIL;
+                goto poweroff;
+        }
+
+        /* request interrupt */
+        err = platform_get_irq_byname(pdev, "intr");
+        if (err < 0) {
+                dev_err(&pdev->dev, "failed to get IRQ: %d\n", err);
+                goto poweroff;
+        }
+
+        pcie->irq = err;
+
+        err = request_irq(pcie->irq, tegra_pcie_isr, IRQF_SHARED, "PCIE", pcie);
+        if (err) {
+                dev_err(&pdev->dev, "failed to register IRQ: %d\n", err);
+                goto poweroff;
+        }
+
+        return 0;
+
+poweroff:
+        tegra_pcie_power_off(pcie);
+        return err;
+}
+
+static int tegra_pcie_put_resources(struct tegra_pcie *pcie)
+{
+        if (pcie->irq > 0)
+                free_irq(pcie->irq, pcie);
+
+        tegra_pcie_power_off(pcie);
+        return 0;
+}
+
+static int tegra_msi_alloc(struct tegra_msi *chip)
+{
+        int msi;
+
+        mutex_lock(&chip->lock);
+
+        msi = find_first_zero_bit(chip->used, INT_PCI_MSI_NR);
+        if (msi < INT_PCI_MSI_NR)
+                set_bit(msi, chip->used);
+        else
+                msi = -ENOSPC;
+
+        mutex_unlock(&chip->lock);
+
+        return msi;
+}
+
+static void tegra_msi_free(struct tegra_msi *chip, unsigned long irq)
+{
+        struct device *dev = chip->chip.dev;
+
+        mutex_lock(&chip->lock);
+
+        if (!test_bit(irq, chip->used))
+                dev_err(dev, "trying to free unused MSI#%lu\n", irq);
+        else
+                clear_bit(irq, chip->used);
+
+        mutex_unlock(&chip->lock);
+}
+
+static irqreturn_t tegra_pcie_msi_irq(int irq, void *data)
+{
+        struct tegra_pcie *pcie = data;
+        struct tegra_msi *msi = &pcie->msi;
+        unsigned int i, processed = 0;
+
+        for (i = 0; i < 8; i++) {
+                unsigned long reg = afi_readl(pcie, AFI_MSI_VEC0 + i * 4);
+
+                while (reg) {
+                        unsigned int offset = find_first_bit(&reg, 32);
+                        unsigned int index = i * 32 + offset;
+                        unsigned int irq;
+
+                        /* clear the interrupt */
+                        afi_writel(pcie, 1 << offset, AFI_MSI_VEC0 + i * 4);
+
+                        irq = irq_find_mapping(msi->domain, index);
+                        if (irq) {
+                                if (test_bit(index, msi->used))
+                                        generic_handle_irq(irq);
+                                else
+                                        dev_info(pcie->dev, "unhandled MSI\n");
+                        } else {
+                                /*
+                                 * that's weird who triggered this?
+                                 * just clear it
+                                 */
+                                dev_info(pcie->dev, "unexpected MSI\n");
+                        }
+
+                        /* see if there's any more pending in this vector */
+                        reg = afi_readl(pcie, AFI_MSI_VEC0 + i * 4);
+
+                        processed++;
+                }
+        }
+
+        return processed > 0 ? IRQ_HANDLED : IRQ_NONE;
+}
+
+static int tegra_msi_setup_irq(struct msi_chip *chip, struct pci_dev *pdev,
+                               struct msi_desc *desc)
+{
+        struct tegra_msi *msi = to_tegra_msi(chip);
+        struct msi_msg msg;
+        unsigned int irq;
+        int hwirq;
+
+        hwirq = tegra_msi_alloc(msi);
+        if (hwirq < 0)
+                return hwirq;
+
+        irq = irq_create_mapping(msi->domain, hwirq);
+        if (!irq)
+                return -EINVAL;
+
+        irq_set_msi_desc(irq, desc);
+
+        msg.address_lo = virt_to_phys((void *)msi->pages);
+        /* 32 bit address only */
+        msg.address_hi = 0;
+        msg.data = hwirq;
+
+        write_msi_msg(irq, &msg);
+
+        return 0;
+}
+
+static void tegra_msi_teardown_irq(struct msi_chip *chip, unsigned int irq)
+{
+        struct tegra_msi *msi = to_tegra_msi(chip);
+        struct irq_data *d = irq_get_irq_data(irq);
+
+        tegra_msi_free(msi, d->hwirq);
+}
+
+static struct irq_chip tegra_msi_irq_chip = {
+        .name = "Tegra PCIe MSI",
+        .irq_enable = unmask_msi_irq,
+        .irq_disable = mask_msi_irq,
+        .irq_mask = mask_msi_irq,
+        .irq_unmask = unmask_msi_irq,
+};
+
+static int tegra_msi_map(struct irq_domain *domain, unsigned int irq,
+                         irq_hw_number_t hwirq)
+{
+        irq_set_chip_and_handler(irq, &tegra_msi_irq_chip, handle_simple_irq);
+        irq_set_chip_data(irq, domain->host_data);
+        set_irq_flags(irq, IRQF_VALID);
+
+        tegra_cpuidle_pcie_irqs_in_use();
+
+        return 0;
+}
+
+static const struct irq_domain_ops msi_domain_ops = {
+        .map = tegra_msi_map,
+};
+
+static int tegra_pcie_enable_msi(struct tegra_pcie *pcie)
+{
+        struct platform_device *pdev = to_platform_device(pcie->dev);
+        const struct tegra_pcie_soc_data *soc = pcie->soc_data;
+        struct tegra_msi *msi = &pcie->msi;
+        unsigned long base;
+        int err;
+        u32 reg;
+
+        mutex_init(&msi->lock);
+
+        msi->chip.dev = pcie->dev;
+        msi->chip.setup_irq = tegra_msi_setup_irq;
+        msi->chip.teardown_irq = tegra_msi_teardown_irq;
+
+        msi->domain = irq_domain_add_linear(pcie->dev->of_node, INT_PCI_MSI_NR,
+                                            &msi_domain_ops, &msi->chip);
+        if (!msi->domain) {
+                dev_err(&pdev->dev, "failed to create IRQ domain\n");
+                return -ENOMEM;
+        }
+
+        err = platform_get_irq_byname(pdev, "msi");
+        if (err < 0) {
+                dev_err(&pdev->dev, "failed to get IRQ: %d\n", err);
+                goto err;
+        }
+
+        msi->irq = err;
+
+        err = request_irq(msi->irq, tegra_pcie_msi_irq, 0,
+                          tegra_msi_irq_chip.name, pcie);
+        if (err < 0) {
+                dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
+                goto err;
+        }
+
+        /* setup AFI/FPCI range */
+        msi->pages = __get_free_pages(GFP_KERNEL, 0);
+        base = virt_to_phys((void *)msi->pages);
+
+        afi_writel(pcie, base >> soc->msi_base_shift, AFI_MSI_FPCI_BAR_ST);
+        afi_writel(pcie, base, AFI_MSI_AXI_BAR_ST);
+        /* this register is in 4K increments */
+        afi_writel(pcie, 1, AFI_MSI_BAR_SZ);
+
+        /* enable all MSI vectors */
+        afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC0);
+        afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC1);
+        afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC2);
+        afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC3);
+        afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC4);
+        afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC5);
+        afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC6);
+        afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC7);
+
+        /* and unmask the MSI interrupt */
+        reg = afi_readl(pcie, AFI_INTR_MASK);
+        reg |= AFI_INTR_MASK_MSI_MASK;
+        afi_writel(pcie, reg, AFI_INTR_MASK);
+
+        return 0;
+
+err:
+        irq_domain_remove(msi->domain);
+        return err;
+}
+
+static int tegra_pcie_disable_msi(struct tegra_pcie *pcie)
+{
+        struct tegra_msi *msi = &pcie->msi;
+        unsigned int i, irq;
+        u32 value;
+
+        /* mask the MSI interrupt */
+        value = afi_readl(pcie, AFI_INTR_MASK);
+        value &= ~AFI_INTR_MASK_MSI_MASK;
+        afi_writel(pcie, value, AFI_INTR_MASK);
+
+        /* disable all MSI vectors */
+        afi_writel(pcie, 0, AFI_MSI_EN_VEC0);
+        afi_writel(pcie, 0, AFI_MSI_EN_VEC1);
+        afi_writel(pcie, 0, AFI_MSI_EN_VEC2);
+        afi_writel(pcie, 0, AFI_MSI_EN_VEC3);
+        afi_writel(pcie, 0, AFI_MSI_EN_VEC4);
+        afi_writel(pcie, 0, AFI_MSI_EN_VEC5);
+        afi_writel(pcie, 0, AFI_MSI_EN_VEC6);
+        afi_writel(pcie, 0, AFI_MSI_EN_VEC7);
+
+        free_pages(msi->pages, 0);
+
+        if (msi->irq > 0)
+                free_irq(msi->irq, pcie);
+
+        for (i = 0; i < INT_PCI_MSI_NR; i++) {
+                irq = irq_find_mapping(msi->domain, i);
+                if (irq > 0)
+                        irq_dispose_mapping(irq);
+        }
+
+        irq_domain_remove(msi->domain);
+
+        return 0;
+}
+
+static int tegra_pcie_get_xbar_config(struct tegra_pcie *pcie, u32 lanes,
+                                      u32 *xbar)
+{
+        struct device_node *np = pcie->dev->of_node;
+
+        if (of_device_is_compatible(np, "nvidia,tegra30-pcie")) {
+                switch (lanes) {
+                case 0x00000204:
+                        dev_info(pcie->dev, "4x1, 2x1 configuration\n");
+                        *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420;
+                        return 0;
+
+                case 0x00020202:
+                        dev_info(pcie->dev, "2x3 configuration\n");
+                        *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222;
+                        return 0;
+
+                case 0x00010104:
+                        dev_info(pcie->dev, "4x1, 1x2 configuration\n");
+                        *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411;
+                        return 0;
+                }
+        } else if (of_device_is_compatible(np, "nvidia,tegra20-pcie")) {
+                switch (lanes) {
+                case 0x00000004:
+                        dev_info(pcie->dev, "single-mode configuration\n");
+                        *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE;
+                        return 0;
+
+                case 0x00000202:
+                        dev_info(pcie->dev, "dual-mode configuration\n");
+                        *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL;
+                        return 0;
+                }
+        }
+
+        return -EINVAL;
+}
+
+static int tegra_pcie_parse_dt(struct tegra_pcie *pcie)
+{
+        const struct tegra_pcie_soc_data *soc = pcie->soc_data;
+        struct device_node *np = pcie->dev->of_node, *port;
+        struct of_pci_range_parser parser;
+        struct of_pci_range range;
+        struct resource res;
+        u32 lanes = 0;
+        int err;
+
+        if (of_pci_range_parser_init(&parser, np)) {
+                dev_err(pcie->dev, "missing \"ranges\" property\n");
+                return -EINVAL;
+        }
+
+        pcie->vdd_supply = devm_regulator_get(pcie->dev, "vdd");
+        if (IS_ERR(pcie->vdd_supply))
+                return PTR_ERR(pcie->vdd_supply);
+
+        pcie->pex_clk_supply = devm_regulator_get(pcie->dev, "pex-clk");
+        if (IS_ERR(pcie->pex_clk_supply))
+                return PTR_ERR(pcie->pex_clk_supply);
+
+        if (soc->has_avdd_supply) {
+                pcie->avdd_supply = devm_regulator_get(pcie->dev, "avdd");
+                if (IS_ERR(pcie->avdd_supply))
+                        return PTR_ERR(pcie->avdd_supply);
+        }
+
+        for_each_of_pci_range(&parser, &range) {
+                of_pci_range_to_resource(&range, np, &res);
+
+                switch (res.flags & IORESOURCE_TYPE_BITS) {
+                case IORESOURCE_IO:
+                        memcpy(&pcie->io, &res, sizeof(res));
+                        pcie->io.name = "I/O";
+                        break;
+
+                case IORESOURCE_MEM:
+                        if (res.flags & IORESOURCE_PREFETCH) {
+                                memcpy(&pcie->prefetch, &res, sizeof(res));
+                                pcie->prefetch.name = "PREFETCH";
+                        } else {
+                                memcpy(&pcie->mem, &res, sizeof(res));
+                                pcie->mem.name = "MEM";
+                        }
+                        break;
+                }
+        }
+
+        err = of_pci_parse_bus_range(np, &pcie->busn);
+        if (err < 0) {
+                dev_err(pcie->dev, "failed to parse ranges property: %d\n",
+                        err);
+                pcie->busn.name = np->name;
+                pcie->busn.start = 0;
+                pcie->busn.end = 0xff;
+                pcie->busn.flags = IORESOURCE_BUS;
+        }
+
+        /* parse root ports */
+        for_each_child_of_node(np, port) {
+                struct tegra_pcie_port *rp;
+                unsigned int index;
+                u32 value;
+
+                err = of_pci_get_devfn(port);
+                if (err < 0) {
+                        dev_err(pcie->dev, "failed to parse address: %d\n",
+                                err);
+                        return err;
+                }
+
+                index = PCI_SLOT(err);
+
+                if (index < 1 || index > soc->num_ports) {
+                        dev_err(pcie->dev, "invalid port number: %d\n", index);
+                        return -EINVAL;
+                }
+
+                index--;
+
+                err = of_property_read_u32(port, "nvidia,num-lanes", &value);
+                if (err < 0) {
+                        dev_err(pcie->dev, "failed to parse # of lanes: %d\n",
+                                err);
+                        return err;
+                }
+
+                if (value > 16) {
+                        dev_err(pcie->dev, "invalid # of lanes: %u\n", value);
+                        return -EINVAL;
+                }
+
+                lanes |= value << (index << 3);
+
+                if (!of_device_is_available(port))
+                        continue;
+
+                rp = devm_kzalloc(pcie->dev, sizeof(*rp), GFP_KERNEL);
+                if (!rp)
+                        return -ENOMEM;
+
+                err = of_address_to_resource(port, 0, &rp->regs);
+                if (err < 0) {
+                        dev_err(pcie->dev, "failed to parse address: %d\n",
+                                err);
+                        return err;
+                }
+
+                INIT_LIST_HEAD(&rp->list);
+                rp->index = index;
+                rp->lanes = value;
+                rp->pcie = pcie;
+
+                rp->base = devm_ioremap_resource(pcie->dev, &rp->regs);
+                if (IS_ERR(rp->base))
+                        return PTR_ERR(rp->base);
+
+                list_add_tail(&rp->list, &pcie->ports);
+        }
+
+        err = tegra_pcie_get_xbar_config(pcie, lanes, &pcie->xbar_config);
+        if (err < 0) {
+                dev_err(pcie->dev, "invalid lane configuration\n");
+                return err;
+        }
+
+        return 0;
+}
+
+/*
+ * FIXME: If there are no PCIe cards attached, then calling this function
+ * can result in the increase of the bootup time as there are big timeout
+ * loops.
+ */
+#define TEGRA_PCIE_LINKUP_TIMEOUT       200     /* up to 1.2 seconds */
+static bool tegra_pcie_port_check_link(struct tegra_pcie_port *port)
+{
+        unsigned int retries = 3;
+        unsigned long value;
+
+        do {
+                unsigned int timeout = TEGRA_PCIE_LINKUP_TIMEOUT;
+
+                do {
+                        value = readl(port->base + RP_VEND_XP);
+
+                        if (value & RP_VEND_XP_DL_UP)
+                                break;
+
+                        usleep_range(1000, 2000);
+                } while (--timeout);
+
+                if (!timeout) {
+                        dev_err(port->pcie->dev, "link %u down, retrying\n",
+                                port->index);
+                        goto retry;
+                }
+
+                timeout = TEGRA_PCIE_LINKUP_TIMEOUT;
+
+                do {
+                        value = readl(port->base + RP_LINK_CONTROL_STATUS);
+
+                        if (value & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE)
+                                return true;
+
+                        usleep_range(1000, 2000);
+                } while (--timeout);
+
+retry:
+                tegra_pcie_port_reset(port);
+        } while (--retries);
+
+        return false;
+}
+
+static int tegra_pcie_enable(struct tegra_pcie *pcie)
+{
+        struct tegra_pcie_port *port, *tmp;
+        struct hw_pci hw;
+
+        list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
+                dev_info(pcie->dev, "probing port %u, using %u lanes\n",
+                         port->index, port->lanes);
+
+                tegra_pcie_port_enable(port);
+
+                if (tegra_pcie_port_check_link(port))
+                        continue;
+
+                dev_info(pcie->dev, "link %u down, ignoring\n", port->index);
+
+                tegra_pcie_port_disable(port);
+                tegra_pcie_port_free(port);
+        }
+
+        memset(&hw, 0, sizeof(hw));
+
+        hw.nr_controllers = 1;
+        hw.private_data = (void **)&pcie;
+        hw.setup = tegra_pcie_setup;
+        hw.map_irq = tegra_pcie_map_irq;
+        hw.add_bus = tegra_pcie_add_bus;
+        hw.scan = tegra_pcie_scan_bus;
+        hw.ops = &tegra_pcie_ops;
+
+        pci_common_init_dev(pcie->dev, &hw);
+
+        return 0;
+}
+
+static const struct tegra_pcie_soc_data tegra20_pcie_data = {
+        .num_ports = 2,
+        .msi_base_shift = 0,
+        .pads_pll_ctl = PADS_PLL_CTL_TEGRA20,
+        .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10,
+        .has_pex_clkreq_en = false,
+        .has_pex_bias_ctrl = false,
+        .has_intr_prsnt_sense = false,
+        .has_avdd_supply = false,
+        .has_cml_clk = false,
+};
+
+static const struct tegra_pcie_soc_data tegra30_pcie_data = {
+        .num_ports = 3,
+        .msi_base_shift = 8,
+        .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
+        .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
+        .has_pex_clkreq_en = true,
+        .has_pex_bias_ctrl = true,
+        .has_intr_prsnt_sense = true,
+        .has_avdd_supply = true,
+        .has_cml_clk = true,
+};
+
+static const struct of_device_id tegra_pcie_of_match[] = {
+        { .compatible = "nvidia,tegra30-pcie", .data = &tegra30_pcie_data },
+        { .compatible = "nvidia,tegra20-pcie", .data = &tegra20_pcie_data },
+        { },
+};
+MODULE_DEVICE_TABLE(of, tegra_pcie_of_match);
+
+static int tegra_pcie_probe(struct platform_device *pdev)
+{
+        const struct of_device_id *match;
+        struct tegra_pcie *pcie;
+        int err;
+
+        match = of_match_device(tegra_pcie_of_match, &pdev->dev);
+        if (!match)
+                return -ENODEV;
+
+        pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
+        if (!pcie)
+                return -ENOMEM;
+
+        INIT_LIST_HEAD(&pcie->busses);
+        INIT_LIST_HEAD(&pcie->ports);
+        pcie->soc_data = match->data;
+        pcie->dev = &pdev->dev;
+
+        err = tegra_pcie_parse_dt(pcie);
+        if (err < 0)
+                return err;
+
+        pcibios_min_mem = 0;
+
+        err = tegra_pcie_get_resources(pcie);
+        if (err < 0) {
+                dev_err(&pdev->dev, "failed to request resources: %d\n", err);
+                return err;
+        }
+
+        err = tegra_pcie_enable_controller(pcie);
+        if (err)
+                goto put_resources;
+
+        /* setup the AFI address translations */
+        tegra_pcie_setup_translations(pcie);
+
+        if (IS_ENABLED(CONFIG_PCI_MSI)) {
+                err = tegra_pcie_enable_msi(pcie);
+                if (err < 0) {
+                        dev_err(&pdev->dev,
+                                "failed to enable MSI support: %d\n",
+                                err);
+                        goto put_resources;
+                }
+        }
+
+        err = tegra_pcie_enable(pcie);
+        if (err < 0) {
+                dev_err(&pdev->dev, "failed to enable PCIe ports: %d\n", err);
+                goto disable_msi;
+        }
+
+        platform_set_drvdata(pdev, pcie);
+        return 0;
+
+disable_msi:
+        if (IS_ENABLED(CONFIG_PCI_MSI))
+                tegra_pcie_disable_msi(pcie);
+put_resources:
+        tegra_pcie_put_resources(pcie);
+        return err;
+}
+
+static struct platform_driver tegra_pcie_driver = {
+        .driver = {
+                .name = "tegra-pcie",
+                .owner = THIS_MODULE,
+                .of_match_table = tegra_pcie_of_match,
+                .suppress_bind_attrs = true,
+        },
+        .probe = tegra_pcie_probe,
+};
+module_platform_driver(tegra_pcie_driver);
+
+MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
+MODULE_DESCRIPTION("NVIDIA Tegra PCIe driver");
+MODULE_LICENSE("GPLv2");
diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c
index aca7578b05e5..b35f93c232cf 100644
--- a/drivers/pci/msi.c
+++ b/drivers/pci/msi.c
@@ -30,20 +30,60 @@ static int pci_msi_enable = 1;
 
 /* Arch hooks */
 
-#ifndef arch_msi_check_device
-int arch_msi_check_device(struct pci_dev *dev, int nvec, int type)
+#if defined(CONFIG_GENERIC_HARDIRQS)
+int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
 {
+        struct msi_chip *chip = dev->bus->msi;
+        int err;
+
+        if (!chip || !chip->setup_irq)
+                return -EINVAL;
+
+        err = chip->setup_irq(chip, dev, desc);
+        if (err < 0)
+                return err;
+
+        irq_set_chip_data(desc->irq, chip);
+
         return 0;
 }
-#endif
 
-#ifndef arch_setup_msi_irqs
-# define arch_setup_msi_irqs default_setup_msi_irqs
-# define HAVE_DEFAULT_MSI_SETUP_IRQS
-#endif
+void __weak arch_teardown_msi_irq(unsigned int irq)
+{
+        struct msi_chip *chip = irq_get_chip_data(irq);
 
-#ifdef HAVE_DEFAULT_MSI_SETUP_IRQS
-int default_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
+        if (!chip || !chip->teardown_irq)
+                return;
+
+        chip->teardown_irq(chip, irq);
+}
+
+int __weak arch_msi_check_device(struct pci_dev *dev, int nvec, int type)
+{
+        struct msi_chip *chip = dev->bus->msi;
+
+        if (!chip || !chip->check_device)
+                return 0;
+
+        return chip->check_device(chip, dev, nvec, type);
+}
+#else
+int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
+{
+        return -ENOSYS;
+}
+
+void __weak arch_teardown_msi_irq(unsigned int irq)
+{
+}
+
+int __weak arch_msi_check_device(struct pci_dev *dev, int nvec, int type)
+{
+        return 0;
+}
+#endif /* CONFIG_GENERIC_HARDIRQS */
+
+int __weak arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
 {
         struct msi_desc *entry;
         int ret;
@@ -65,14 +105,11 @@ int default_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
 
         return 0;
 }
-#endif
-
-#ifndef arch_teardown_msi_irqs
-# define arch_teardown_msi_irqs default_teardown_msi_irqs
-# define HAVE_DEFAULT_MSI_TEARDOWN_IRQS
-#endif
 
-#ifdef HAVE_DEFAULT_MSI_TEARDOWN_IRQS
+/*
+ * We have a default implementation available as a separate non-weak
+ * function, as it is used by the Xen x86 PCI code
+ */
 void default_teardown_msi_irqs(struct pci_dev *dev)
 {
         struct msi_desc *entry;
@@ -89,14 +126,12 @@ void default_teardown_msi_irqs(struct pci_dev *dev)
                         arch_teardown_msi_irq(entry->irq + i);
         }
 }
-#endif
 
-#ifndef arch_restore_msi_irqs
-# define arch_restore_msi_irqs default_restore_msi_irqs
-# define HAVE_DEFAULT_MSI_RESTORE_IRQS
-#endif
+void __weak arch_teardown_msi_irqs(struct pci_dev *dev)
+{
+        return default_teardown_msi_irqs(dev);
+}
 
-#ifdef HAVE_DEFAULT_MSI_RESTORE_IRQS
 void default_restore_msi_irqs(struct pci_dev *dev, int irq)
 {
         struct msi_desc *entry;
@@ -114,7 +149,11 @@ void default_restore_msi_irqs(struct pci_dev *dev, int irq)
         if (entry)
                 write_msi_msg(irq, &entry->msg);
 }
-#endif
+
+void __weak arch_restore_msi_irqs(struct pci_dev *dev, int irq)
+{
+        return default_restore_msi_irqs(dev, irq);
+}
 
 static void msi_set_enable(struct pci_dev *dev, int enable)
 {
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 4f9cc93c3b59..7ef0f868b3e0 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -671,6 +671,7 @@ static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
 
         child->parent = parent;
         child->ops = parent->ops;
+        child->msi = parent->msi;
         child->sysdata = parent->sysdata;
         child->bus_flags = parent->bus_flags;
 
diff --git a/include/linux/mbus.h b/include/linux/mbus.h
index dba482e31a13..345b8c53b897 100644
--- a/include/linux/mbus.h
+++ b/include/linux/mbus.h
@@ -11,6 +11,8 @@
 #ifndef __LINUX_MBUS_H
 #define __LINUX_MBUS_H
 
+struct resource;
+
 struct mbus_dram_target_info
 {
         /*
@@ -59,14 +61,18 @@ static inline const struct mbus_dram_target_info *mv_mbus_dram_info(void)
 }
 #endif
 
-int mvebu_mbus_add_window_remap_flags(const char *devname, phys_addr_t base,
-                                      size_t size, phys_addr_t remap,
-                                      unsigned int flags);
-int mvebu_mbus_add_window(const char *devname, phys_addr_t base,
-                          size_t size);
+void mvebu_mbus_get_pcie_mem_aperture(struct resource *res);
+void mvebu_mbus_get_pcie_io_aperture(struct resource *res);
+int mvebu_mbus_add_window_remap_by_id(unsigned int target,
+                                      unsigned int attribute,
+                                      phys_addr_t base, size_t size,
+                                      phys_addr_t remap);
+int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
+                                phys_addr_t base, size_t size);
 int mvebu_mbus_del_window(phys_addr_t base, size_t size);
 int mvebu_mbus_init(const char *soc, phys_addr_t mbus_phys_base,
                     size_t mbus_size, phys_addr_t sdram_phys_base,
                     size_t sdram_size);
+int mvebu_mbus_dt_init(void);
 
 #endif /* __LINUX_MBUS_H */
diff --git a/include/linux/micrel_phy.h b/include/linux/micrel_phy.h
index 8752dbbc6135..ad05ce60c1c9 100644
--- a/include/linux/micrel_phy.h
+++ b/include/linux/micrel_phy.h
@@ -17,6 +17,7 @@
 
 #define PHY_ID_KSZ8873MLL       0x000e7237
 #define PHY_ID_KSZ9021          0x00221610
+#define PHY_ID_KSZ9021RLRN      0x00221611
 #define PHY_ID_KS8737           0x00221720
 #define PHY_ID_KSZ8021          0x00221555
 #define PHY_ID_KSZ8031          0x00221556
@@ -35,4 +36,9 @@
 /* struct phy_device dev_flags definitions */
 #define MICREL_PHY_50MHZ_CLK    0x00000001
 
+#define MICREL_KSZ9021_EXTREG_CTRL      0xB
+#define MICREL_KSZ9021_EXTREG_DATA_WRITE        0xC
+#define MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW  0x104
+#define MICREL_KSZ9021_RGMII_RX_DATA_PAD_SCEW   0x105
+
 #endif /* _MICREL_PHY_H */
diff --git a/include/linux/msi.h b/include/linux/msi.h
index ee66f3a12fb6..b17ead818aec 100644
--- a/include/linux/msi.h
+++ b/include/linux/msi.h
@@ -51,12 +51,31 @@ struct msi_desc {
 };
 
 /*
- * The arch hook for setup up msi irqs
+ * The arch hooks to setup up msi irqs. Those functions are
+ * implemented as weak symbols so that they /can/ be overriden by
+ * architecture specific code if needed.
  */
 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc);
 void arch_teardown_msi_irq(unsigned int irq);
 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type);
 void arch_teardown_msi_irqs(struct pci_dev *dev);
 int arch_msi_check_device(struct pci_dev* dev, int nvec, int type);
+void arch_restore_msi_irqs(struct pci_dev *dev, int irq);
+
+void default_teardown_msi_irqs(struct pci_dev *dev);
+void default_restore_msi_irqs(struct pci_dev *dev, int irq);
+
+struct msi_chip {
+        struct module *owner;
+        struct device *dev;
+        struct device_node *of_node;
+        struct list_head list;
+
+        int (*setup_irq)(struct msi_chip *chip, struct pci_dev *dev,
+                         struct msi_desc *desc);
+        void (*teardown_irq)(struct msi_chip *chip, unsigned int irq);
+        int (*check_device)(struct msi_chip *chip, struct pci_dev *dev,
+                            int nvec, int type);
+};
 
 #endif /* LINUX_MSI_H */
diff --git a/include/linux/of_pci.h b/include/linux/of_pci.h
index 7a04826018c0..fd9c408631a0 100644
--- a/include/linux/of_pci.h
+++ b/include/linux/of_pci.h
@@ -2,6 +2,7 @@
 #define __OF_PCI_H
 
 #include <linux/pci.h>
+#include <linux/msi.h>
 
 struct pci_dev;
 struct of_irq;
@@ -13,4 +14,15 @@ struct device_node *of_pci_find_child_device(struct device_node *parent,
 int of_pci_get_devfn(struct device_node *np);
 int of_pci_parse_bus_range(struct device_node *node, struct resource *res);
 
+#if defined(CONFIG_OF) && defined(CONFIG_PCI_MSI)
+int of_pci_msi_chip_add(struct msi_chip *chip);
+void of_pci_msi_chip_remove(struct msi_chip *chip);
+struct msi_chip *of_pci_find_msi_chip_by_node(struct device_node *of_node);
+#else
+static inline int of_pci_msi_chip_add(struct msi_chip *chip) { return -EINVAL; }
+static inline void of_pci_msi_chip_remove(struct msi_chip *chip) { }
+static inline struct msi_chip *
+of_pci_find_msi_chip_by_node(struct device_node *of_node) { return NULL; }
+#endif
+
 #endif
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 20888589c09e..da172f956ad6 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -446,6 +446,7 @@ struct pci_bus {
         struct resource busn_res;       /* bus numbers routed to this bus */
 
         struct pci_ops  *ops;           /* configuration access functions */
+        struct msi_chip *msi;           /* MSI controller */
         void            *sysdata;       /* hook for sys-specific extension */
         struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
 
diff --git a/include/linux/tegra-cpuidle.h b/include/linux/tegra-cpuidle.h
new file mode 100644
index 000000000000..9c6286bbf662
--- /dev/null
+++ b/include/linux/tegra-cpuidle.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef __LINUX_TEGRA_CPUIDLE_H__
+#define __LINUX_TEGRA_CPUIDLE_H__
+
+#ifdef CONFIG_CPU_IDLE
+void tegra_cpuidle_pcie_irqs_in_use(void);
+#else
+static inline void tegra_cpuidle_pcie_irqs_in_use(void)
+{
+}
+#endif
+
+#endif