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-rw-r--r--Documentation/devicetree/bindings/gpio/sodaville.txt48
-rw-r--r--arch/arm/mach-omap1/gpio15xx.c7
-rw-r--r--arch/arm/mach-omap1/gpio16xx.c47
-rw-r--r--arch/arm/mach-omap1/gpio7xx.c14
-rw-r--r--arch/arm/mach-omap2/gpio.c36
-rw-r--r--arch/arm/mach-omap2/pm34xx.c14
-rw-r--r--arch/arm/plat-omap/include/plat/gpio.h29
-rw-r--r--arch/x86/platform/ce4100/falconfalls.dts7
-rw-r--r--drivers/gpio/Kconfig14
-rw-r--r--drivers/gpio/Makefile2
-rw-r--r--drivers/gpio/gpio-mc9s08dz60.c161
-rw-r--r--drivers/gpio/gpio-omap.c1106
-rw-r--r--drivers/gpio/gpio-pl061.c7
-rw-r--r--drivers/gpio/gpio-sodaville.c302
-rw-r--r--drivers/gpio/gpio-tps65910.c20
-rw-r--r--drivers/gpio/gpiolib.c8
-rw-r--r--drivers/of/gpio.c9
-rw-r--r--include/linux/mfd/tps65910.h8
-rw-r--r--include/linux/of_gpio.h27
19 files changed, 1154 insertions, 712 deletions
diff --git a/Documentation/devicetree/bindings/gpio/sodaville.txt b/Documentation/devicetree/bindings/gpio/sodaville.txt
new file mode 100644
index 000000000000..563eff22b975
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/sodaville.txt
@@ -0,0 +1,48 @@
1GPIO controller on CE4100 / Sodaville SoCs
2==========================================
3
4The bindings for CE4100's GPIO controller match the generic description
5which is covered by the gpio.txt file in this folder.
6
7The only additional property is the intel,muxctl property which holds the
8value which is written into the MUXCNTL register.
9
10There is no compatible property for now because the driver is probed via
11PCI id (vendor 0x8086 device 0x2e67).
12
13The interrupt specifier consists of two cells encoded as follows:
14 - <1st cell>: The interrupt-number that identifies the interrupt source.
15 - <2nd cell>: The level-sense information, encoded as follows:
16 4 - active high level-sensitive
17 8 - active low level-sensitive
18
19Example of the GPIO device and one user:
20
21 pcigpio: gpio@b,1 {
22 /* two cells for GPIO and interrupt */
23 #gpio-cells = <2>;
24 #interrupt-cells = <2>;
25 compatible = "pci8086,2e67.2",
26 "pci8086,2e67",
27 "pciclassff0000",
28 "pciclassff00";
29
30 reg = <0x15900 0x0 0x0 0x0 0x0>;
31 /* Interrupt line of the gpio device */
32 interrupts = <15 1>;
33 /* It is an interrupt and GPIO controller itself */
34 interrupt-controller;
35 gpio-controller;
36 intel,muxctl = <0>;
37 };
38
39 testuser@20 {
40 compatible = "example,testuser";
41 /* User the 11th GPIO line as an active high triggered
42 * level interrupt
43 */
44 interrupts = <11 8>;
45 interrupt-parent = <&pcigpio>;
46 /* Use this GPIO also with the gpio functions */
47 gpios = <&pcigpio 11 0>;
48 };
diff --git a/arch/arm/mach-omap1/gpio15xx.c b/arch/arm/mach-omap1/gpio15xx.c
index 399da4ce017b..634903ef8292 100644
--- a/arch/arm/mach-omap1/gpio15xx.c
+++ b/arch/arm/mach-omap1/gpio15xx.c
@@ -42,11 +42,12 @@ static struct omap_gpio_reg_offs omap15xx_mpuio_regs = {
42 .irqstatus = OMAP_MPUIO_GPIO_INT, 42 .irqstatus = OMAP_MPUIO_GPIO_INT,
43 .irqenable = OMAP_MPUIO_GPIO_MASKIT, 43 .irqenable = OMAP_MPUIO_GPIO_MASKIT,
44 .irqenable_inv = true, 44 .irqenable_inv = true,
45 .irqctrl = OMAP_MPUIO_GPIO_INT_EDGE,
45}; 46};
46 47
47static struct __initdata omap_gpio_platform_data omap15xx_mpu_gpio_config = { 48static struct __initdata omap_gpio_platform_data omap15xx_mpu_gpio_config = {
48 .virtual_irq_start = IH_MPUIO_BASE, 49 .virtual_irq_start = IH_MPUIO_BASE,
49 .bank_type = METHOD_MPUIO, 50 .is_mpuio = true,
50 .bank_width = 16, 51 .bank_width = 16,
51 .bank_stride = 1, 52 .bank_stride = 1,
52 .regs = &omap15xx_mpuio_regs, 53 .regs = &omap15xx_mpuio_regs,
@@ -83,11 +84,12 @@ static struct omap_gpio_reg_offs omap15xx_gpio_regs = {
83 .irqstatus = OMAP1510_GPIO_INT_STATUS, 84 .irqstatus = OMAP1510_GPIO_INT_STATUS,
84 .irqenable = OMAP1510_GPIO_INT_MASK, 85 .irqenable = OMAP1510_GPIO_INT_MASK,
85 .irqenable_inv = true, 86 .irqenable_inv = true,
87 .irqctrl = OMAP1510_GPIO_INT_CONTROL,
88 .pinctrl = OMAP1510_GPIO_PIN_CONTROL,
86}; 89};
87 90
88static struct __initdata omap_gpio_platform_data omap15xx_gpio_config = { 91static struct __initdata omap_gpio_platform_data omap15xx_gpio_config = {
89 .virtual_irq_start = IH_GPIO_BASE, 92 .virtual_irq_start = IH_GPIO_BASE,
90 .bank_type = METHOD_GPIO_1510,
91 .bank_width = 16, 93 .bank_width = 16,
92 .regs = &omap15xx_gpio_regs, 94 .regs = &omap15xx_gpio_regs,
93}; 95};
@@ -115,7 +117,6 @@ static int __init omap15xx_gpio_init(void)
115 platform_device_register(&omap15xx_mpu_gpio); 117 platform_device_register(&omap15xx_mpu_gpio);
116 platform_device_register(&omap15xx_gpio); 118 platform_device_register(&omap15xx_gpio);
117 119
118 gpio_bank_count = 2;
119 return 0; 120 return 0;
120} 121}
121postcore_initcall(omap15xx_gpio_init); 122postcore_initcall(omap15xx_gpio_init);
diff --git a/arch/arm/mach-omap1/gpio16xx.c b/arch/arm/mach-omap1/gpio16xx.c
index 0f399bd0e70e..1c5f90e17427 100644
--- a/arch/arm/mach-omap1/gpio16xx.c
+++ b/arch/arm/mach-omap1/gpio16xx.c
@@ -24,6 +24,9 @@
24#define OMAP1610_GPIO4_BASE 0xfffbbc00 24#define OMAP1610_GPIO4_BASE 0xfffbbc00
25#define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE 25#define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE
26 26
27/* smart idle, enable wakeup */
28#define SYSCONFIG_WORD 0x14
29
27/* mpu gpio */ 30/* mpu gpio */
28static struct __initdata resource omap16xx_mpu_gpio_resources[] = { 31static struct __initdata resource omap16xx_mpu_gpio_resources[] = {
29 { 32 {
@@ -45,11 +48,12 @@ static struct omap_gpio_reg_offs omap16xx_mpuio_regs = {
45 .irqstatus = OMAP_MPUIO_GPIO_INT, 48 .irqstatus = OMAP_MPUIO_GPIO_INT,
46 .irqenable = OMAP_MPUIO_GPIO_MASKIT, 49 .irqenable = OMAP_MPUIO_GPIO_MASKIT,
47 .irqenable_inv = true, 50 .irqenable_inv = true,
51 .irqctrl = OMAP_MPUIO_GPIO_INT_EDGE,
48}; 52};
49 53
50static struct __initdata omap_gpio_platform_data omap16xx_mpu_gpio_config = { 54static struct __initdata omap_gpio_platform_data omap16xx_mpu_gpio_config = {
51 .virtual_irq_start = IH_MPUIO_BASE, 55 .virtual_irq_start = IH_MPUIO_BASE,
52 .bank_type = METHOD_MPUIO, 56 .is_mpuio = true,
53 .bank_width = 16, 57 .bank_width = 16,
54 .bank_stride = 1, 58 .bank_stride = 1,
55 .regs = &omap16xx_mpuio_regs, 59 .regs = &omap16xx_mpuio_regs,
@@ -89,11 +93,13 @@ static struct omap_gpio_reg_offs omap16xx_gpio_regs = {
89 .irqenable = OMAP1610_GPIO_IRQENABLE1, 93 .irqenable = OMAP1610_GPIO_IRQENABLE1,
90 .set_irqenable = OMAP1610_GPIO_SET_IRQENABLE1, 94 .set_irqenable = OMAP1610_GPIO_SET_IRQENABLE1,
91 .clr_irqenable = OMAP1610_GPIO_CLEAR_IRQENABLE1, 95 .clr_irqenable = OMAP1610_GPIO_CLEAR_IRQENABLE1,
96 .wkup_en = OMAP1610_GPIO_WAKEUPENABLE,
97 .edgectrl1 = OMAP1610_GPIO_EDGE_CTRL1,
98 .edgectrl2 = OMAP1610_GPIO_EDGE_CTRL2,
92}; 99};
93 100
94static struct __initdata omap_gpio_platform_data omap16xx_gpio1_config = { 101static struct __initdata omap_gpio_platform_data omap16xx_gpio1_config = {
95 .virtual_irq_start = IH_GPIO_BASE, 102 .virtual_irq_start = IH_GPIO_BASE,
96 .bank_type = METHOD_GPIO_1610,
97 .bank_width = 16, 103 .bank_width = 16,
98 .regs = &omap16xx_gpio_regs, 104 .regs = &omap16xx_gpio_regs,
99}; 105};
@@ -123,7 +129,6 @@ static struct __initdata resource omap16xx_gpio2_resources[] = {
123 129
124static struct __initdata omap_gpio_platform_data omap16xx_gpio2_config = { 130static struct __initdata omap_gpio_platform_data omap16xx_gpio2_config = {
125 .virtual_irq_start = IH_GPIO_BASE + 16, 131 .virtual_irq_start = IH_GPIO_BASE + 16,
126 .bank_type = METHOD_GPIO_1610,
127 .bank_width = 16, 132 .bank_width = 16,
128 .regs = &omap16xx_gpio_regs, 133 .regs = &omap16xx_gpio_regs,
129}; 134};
@@ -153,7 +158,6 @@ static struct __initdata resource omap16xx_gpio3_resources[] = {
153 158
154static struct __initdata omap_gpio_platform_data omap16xx_gpio3_config = { 159static struct __initdata omap_gpio_platform_data omap16xx_gpio3_config = {
155 .virtual_irq_start = IH_GPIO_BASE + 32, 160 .virtual_irq_start = IH_GPIO_BASE + 32,
156 .bank_type = METHOD_GPIO_1610,
157 .bank_width = 16, 161 .bank_width = 16,
158 .regs = &omap16xx_gpio_regs, 162 .regs = &omap16xx_gpio_regs,
159}; 163};
@@ -183,7 +187,6 @@ static struct __initdata resource omap16xx_gpio4_resources[] = {
183 187
184static struct __initdata omap_gpio_platform_data omap16xx_gpio4_config = { 188static struct __initdata omap_gpio_platform_data omap16xx_gpio4_config = {
185 .virtual_irq_start = IH_GPIO_BASE + 48, 189 .virtual_irq_start = IH_GPIO_BASE + 48,
186 .bank_type = METHOD_GPIO_1610,
187 .bank_width = 16, 190 .bank_width = 16,
188 .regs = &omap16xx_gpio_regs, 191 .regs = &omap16xx_gpio_regs,
189}; 192};
@@ -214,14 +217,42 @@ static struct __initdata platform_device * omap16xx_gpio_dev[] = {
214static int __init omap16xx_gpio_init(void) 217static int __init omap16xx_gpio_init(void)
215{ 218{
216 int i; 219 int i;
220 void __iomem *base;
221 struct resource *res;
222 struct platform_device *pdev;
223 struct omap_gpio_platform_data *pdata;
217 224
218 if (!cpu_is_omap16xx()) 225 if (!cpu_is_omap16xx())
219 return -EINVAL; 226 return -EINVAL;
220 227
221 for (i = 0; i < ARRAY_SIZE(omap16xx_gpio_dev); i++) 228 for (i = 0; i < ARRAY_SIZE(omap16xx_gpio_dev); i++) {
222 platform_device_register(omap16xx_gpio_dev[i]); 229 pdev = omap16xx_gpio_dev[i];
230 pdata = pdev->dev.platform_data;
231
232 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
233 if (unlikely(!res)) {
234 dev_err(&pdev->dev, "Invalid mem resource.\n");
235 return -ENODEV;
236 }
237
238 base = ioremap(res->start, resource_size(res));
239 if (unlikely(!base)) {
240 dev_err(&pdev->dev, "ioremap failed.\n");
241 return -ENOMEM;
242 }
223 243
224 gpio_bank_count = ARRAY_SIZE(omap16xx_gpio_dev); 244 __raw_writel(SYSCONFIG_WORD, base + OMAP1610_GPIO_SYSCONFIG);
245 iounmap(base);
246
247 /*
248 * Enable system clock for GPIO module.
249 * The CAM_CLK_CTRL *is* really the right place.
250 */
251 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
252 ULPD_CAM_CLK_CTRL);
253
254 platform_device_register(omap16xx_gpio_dev[i]);
255 }
225 256
226 return 0; 257 return 0;
227} 258}
diff --git a/arch/arm/mach-omap1/gpio7xx.c b/arch/arm/mach-omap1/gpio7xx.c
index 5ab63eab0ff5..4771d6b68b96 100644
--- a/arch/arm/mach-omap1/gpio7xx.c
+++ b/arch/arm/mach-omap1/gpio7xx.c
@@ -47,12 +47,13 @@ static struct omap_gpio_reg_offs omap7xx_mpuio_regs = {
47 .irqstatus = OMAP_MPUIO_GPIO_INT / 2, 47 .irqstatus = OMAP_MPUIO_GPIO_INT / 2,
48 .irqenable = OMAP_MPUIO_GPIO_MASKIT / 2, 48 .irqenable = OMAP_MPUIO_GPIO_MASKIT / 2,
49 .irqenable_inv = true, 49 .irqenable_inv = true,
50 .irqctrl = OMAP_MPUIO_GPIO_INT_EDGE >> 1,
50}; 51};
51 52
52static struct __initdata omap_gpio_platform_data omap7xx_mpu_gpio_config = { 53static struct __initdata omap_gpio_platform_data omap7xx_mpu_gpio_config = {
53 .virtual_irq_start = IH_MPUIO_BASE, 54 .virtual_irq_start = IH_MPUIO_BASE,
54 .bank_type = METHOD_MPUIO, 55 .is_mpuio = true,
55 .bank_width = 32, 56 .bank_width = 16,
56 .bank_stride = 2, 57 .bank_stride = 2,
57 .regs = &omap7xx_mpuio_regs, 58 .regs = &omap7xx_mpuio_regs,
58}; 59};
@@ -88,11 +89,11 @@ static struct omap_gpio_reg_offs omap7xx_gpio_regs = {
88 .irqstatus = OMAP7XX_GPIO_INT_STATUS, 89 .irqstatus = OMAP7XX_GPIO_INT_STATUS,
89 .irqenable = OMAP7XX_GPIO_INT_MASK, 90 .irqenable = OMAP7XX_GPIO_INT_MASK,
90 .irqenable_inv = true, 91 .irqenable_inv = true,
92 .irqctrl = OMAP7XX_GPIO_INT_CONTROL,
91}; 93};
92 94
93static struct __initdata omap_gpio_platform_data omap7xx_gpio1_config = { 95static struct __initdata omap_gpio_platform_data omap7xx_gpio1_config = {
94 .virtual_irq_start = IH_GPIO_BASE, 96 .virtual_irq_start = IH_GPIO_BASE,
95 .bank_type = METHOD_GPIO_7XX,
96 .bank_width = 32, 97 .bank_width = 32,
97 .regs = &omap7xx_gpio_regs, 98 .regs = &omap7xx_gpio_regs,
98}; 99};
@@ -122,7 +123,6 @@ static struct __initdata resource omap7xx_gpio2_resources[] = {
122 123
123static struct __initdata omap_gpio_platform_data omap7xx_gpio2_config = { 124static struct __initdata omap_gpio_platform_data omap7xx_gpio2_config = {
124 .virtual_irq_start = IH_GPIO_BASE + 32, 125 .virtual_irq_start = IH_GPIO_BASE + 32,
125 .bank_type = METHOD_GPIO_7XX,
126 .bank_width = 32, 126 .bank_width = 32,
127 .regs = &omap7xx_gpio_regs, 127 .regs = &omap7xx_gpio_regs,
128}; 128};
@@ -152,7 +152,6 @@ static struct __initdata resource omap7xx_gpio3_resources[] = {
152 152
153static struct __initdata omap_gpio_platform_data omap7xx_gpio3_config = { 153static struct __initdata omap_gpio_platform_data omap7xx_gpio3_config = {
154 .virtual_irq_start = IH_GPIO_BASE + 64, 154 .virtual_irq_start = IH_GPIO_BASE + 64,
155 .bank_type = METHOD_GPIO_7XX,
156 .bank_width = 32, 155 .bank_width = 32,
157 .regs = &omap7xx_gpio_regs, 156 .regs = &omap7xx_gpio_regs,
158}; 157};
@@ -182,7 +181,6 @@ static struct __initdata resource omap7xx_gpio4_resources[] = {
182 181
183static struct __initdata omap_gpio_platform_data omap7xx_gpio4_config = { 182static struct __initdata omap_gpio_platform_data omap7xx_gpio4_config = {
184 .virtual_irq_start = IH_GPIO_BASE + 96, 183 .virtual_irq_start = IH_GPIO_BASE + 96,
185 .bank_type = METHOD_GPIO_7XX,
186 .bank_width = 32, 184 .bank_width = 32,
187 .regs = &omap7xx_gpio_regs, 185 .regs = &omap7xx_gpio_regs,
188}; 186};
@@ -212,7 +210,6 @@ static struct __initdata resource omap7xx_gpio5_resources[] = {
212 210
213static struct __initdata omap_gpio_platform_data omap7xx_gpio5_config = { 211static struct __initdata omap_gpio_platform_data omap7xx_gpio5_config = {
214 .virtual_irq_start = IH_GPIO_BASE + 128, 212 .virtual_irq_start = IH_GPIO_BASE + 128,
215 .bank_type = METHOD_GPIO_7XX,
216 .bank_width = 32, 213 .bank_width = 32,
217 .regs = &omap7xx_gpio_regs, 214 .regs = &omap7xx_gpio_regs,
218}; 215};
@@ -242,7 +239,6 @@ static struct __initdata resource omap7xx_gpio6_resources[] = {
242 239
243static struct __initdata omap_gpio_platform_data omap7xx_gpio6_config = { 240static struct __initdata omap_gpio_platform_data omap7xx_gpio6_config = {
244 .virtual_irq_start = IH_GPIO_BASE + 160, 241 .virtual_irq_start = IH_GPIO_BASE + 160,
245 .bank_type = METHOD_GPIO_7XX,
246 .bank_width = 32, 242 .bank_width = 32,
247 .regs = &omap7xx_gpio_regs, 243 .regs = &omap7xx_gpio_regs,
248}; 244};
@@ -282,8 +278,6 @@ static int __init omap7xx_gpio_init(void)
282 for (i = 0; i < ARRAY_SIZE(omap7xx_gpio_dev); i++) 278 for (i = 0; i < ARRAY_SIZE(omap7xx_gpio_dev); i++)
283 platform_device_register(omap7xx_gpio_dev[i]); 279 platform_device_register(omap7xx_gpio_dev[i]);
284 280
285 gpio_bank_count = ARRAY_SIZE(omap7xx_gpio_dev);
286
287 return 0; 281 return 0;
288} 282}
289postcore_initcall(omap7xx_gpio_init); 283postcore_initcall(omap7xx_gpio_init);
diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
index 8cbfbc2918ce..1e0b750afcaa 100644
--- a/arch/arm/mach-omap2/gpio.c
+++ b/arch/arm/mach-omap2/gpio.c
@@ -23,6 +23,9 @@
23 23
24#include <plat/omap_hwmod.h> 24#include <plat/omap_hwmod.h>
25#include <plat/omap_device.h> 25#include <plat/omap_device.h>
26#include <plat/omap-pm.h>
27
28#include "powerdomain.h"
26 29
27static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused) 30static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
28{ 31{
@@ -31,6 +34,7 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
31 struct omap_gpio_dev_attr *dev_attr; 34 struct omap_gpio_dev_attr *dev_attr;
32 char *name = "omap_gpio"; 35 char *name = "omap_gpio";
33 int id; 36 int id;
37 struct powerdomain *pwrdm;
34 38
35 /* 39 /*
36 * extract the device id from name field available in the 40 * extract the device id from name field available in the
@@ -52,7 +56,7 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
52 pdata->bank_width = dev_attr->bank_width; 56 pdata->bank_width = dev_attr->bank_width;
53 pdata->dbck_flag = dev_attr->dbck_flag; 57 pdata->dbck_flag = dev_attr->dbck_flag;
54 pdata->virtual_irq_start = IH_GPIO_BASE + 32 * (id - 1); 58 pdata->virtual_irq_start = IH_GPIO_BASE + 32 * (id - 1);
55 59 pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count;
56 pdata->regs = kzalloc(sizeof(struct omap_gpio_reg_offs), GFP_KERNEL); 60 pdata->regs = kzalloc(sizeof(struct omap_gpio_reg_offs), GFP_KERNEL);
57 if (!pdata) { 61 if (!pdata) {
58 pr_err("gpio%d: Memory allocation failed\n", id); 62 pr_err("gpio%d: Memory allocation failed\n", id);
@@ -61,8 +65,15 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
61 65
62 switch (oh->class->rev) { 66 switch (oh->class->rev) {
63 case 0: 67 case 0:
68 if (id == 1)
69 /* non-wakeup GPIO pins for OMAP2 Bank1 */
70 pdata->non_wakeup_gpios = 0xe203ffc0;
71 else if (id == 2)
72 /* non-wakeup GPIO pins for OMAP2 Bank2 */
73 pdata->non_wakeup_gpios = 0x08700040;
74 /* fall through */
75
64 case 1: 76 case 1:
65 pdata->bank_type = METHOD_GPIO_24XX;
66 pdata->regs->revision = OMAP24XX_GPIO_REVISION; 77 pdata->regs->revision = OMAP24XX_GPIO_REVISION;
67 pdata->regs->direction = OMAP24XX_GPIO_OE; 78 pdata->regs->direction = OMAP24XX_GPIO_OE;
68 pdata->regs->datain = OMAP24XX_GPIO_DATAIN; 79 pdata->regs->datain = OMAP24XX_GPIO_DATAIN;
@@ -72,13 +83,19 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
72 pdata->regs->irqstatus = OMAP24XX_GPIO_IRQSTATUS1; 83 pdata->regs->irqstatus = OMAP24XX_GPIO_IRQSTATUS1;
73 pdata->regs->irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2; 84 pdata->regs->irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2;
74 pdata->regs->irqenable = OMAP24XX_GPIO_IRQENABLE1; 85 pdata->regs->irqenable = OMAP24XX_GPIO_IRQENABLE1;
86 pdata->regs->irqenable2 = OMAP24XX_GPIO_IRQENABLE2;
75 pdata->regs->set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1; 87 pdata->regs->set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1;
76 pdata->regs->clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1; 88 pdata->regs->clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1;
77 pdata->regs->debounce = OMAP24XX_GPIO_DEBOUNCE_VAL; 89 pdata->regs->debounce = OMAP24XX_GPIO_DEBOUNCE_VAL;
78 pdata->regs->debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN; 90 pdata->regs->debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN;
91 pdata->regs->ctrl = OMAP24XX_GPIO_CTRL;
92 pdata->regs->wkup_en = OMAP24XX_GPIO_WAKE_EN;
93 pdata->regs->leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0;
94 pdata->regs->leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1;
95 pdata->regs->risingdetect = OMAP24XX_GPIO_RISINGDETECT;
96 pdata->regs->fallingdetect = OMAP24XX_GPIO_FALLINGDETECT;
79 break; 97 break;
80 case 2: 98 case 2:
81 pdata->bank_type = METHOD_GPIO_44XX;
82 pdata->regs->revision = OMAP4_GPIO_REVISION; 99 pdata->regs->revision = OMAP4_GPIO_REVISION;
83 pdata->regs->direction = OMAP4_GPIO_OE; 100 pdata->regs->direction = OMAP4_GPIO_OE;
84 pdata->regs->datain = OMAP4_GPIO_DATAIN; 101 pdata->regs->datain = OMAP4_GPIO_DATAIN;
@@ -88,10 +105,17 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
88 pdata->regs->irqstatus = OMAP4_GPIO_IRQSTATUS0; 105 pdata->regs->irqstatus = OMAP4_GPIO_IRQSTATUS0;
89 pdata->regs->irqstatus2 = OMAP4_GPIO_IRQSTATUS1; 106 pdata->regs->irqstatus2 = OMAP4_GPIO_IRQSTATUS1;
90 pdata->regs->irqenable = OMAP4_GPIO_IRQSTATUSSET0; 107 pdata->regs->irqenable = OMAP4_GPIO_IRQSTATUSSET0;
108 pdata->regs->irqenable2 = OMAP4_GPIO_IRQSTATUSSET1;
91 pdata->regs->set_irqenable = OMAP4_GPIO_IRQSTATUSSET0; 109 pdata->regs->set_irqenable = OMAP4_GPIO_IRQSTATUSSET0;
92 pdata->regs->clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0; 110 pdata->regs->clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0;
93 pdata->regs->debounce = OMAP4_GPIO_DEBOUNCINGTIME; 111 pdata->regs->debounce = OMAP4_GPIO_DEBOUNCINGTIME;
94 pdata->regs->debounce_en = OMAP4_GPIO_DEBOUNCENABLE; 112 pdata->regs->debounce_en = OMAP4_GPIO_DEBOUNCENABLE;
113 pdata->regs->ctrl = OMAP4_GPIO_CTRL;
114 pdata->regs->wkup_en = OMAP4_GPIO_IRQWAKEN0;
115 pdata->regs->leveldetect0 = OMAP4_GPIO_LEVELDETECT0;
116 pdata->regs->leveldetect1 = OMAP4_GPIO_LEVELDETECT1;
117 pdata->regs->risingdetect = OMAP4_GPIO_RISINGDETECT;
118 pdata->regs->fallingdetect = OMAP4_GPIO_FALLINGDETECT;
95 break; 119 break;
96 default: 120 default:
97 WARN(1, "Invalid gpio bank_type\n"); 121 WARN(1, "Invalid gpio bank_type\n");
@@ -99,6 +123,9 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
99 return -EINVAL; 123 return -EINVAL;
100 } 124 }
101 125
126 pwrdm = omap_hwmod_get_pwrdm(oh);
127 pdata->loses_context = pwrdm_can_ever_lose_context(pwrdm);
128
102 pdev = omap_device_build(name, id - 1, oh, pdata, 129 pdev = omap_device_build(name, id - 1, oh, pdata,
103 sizeof(*pdata), NULL, 0, false); 130 sizeof(*pdata), NULL, 0, false);
104 kfree(pdata); 131 kfree(pdata);
@@ -109,9 +136,6 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
109 return PTR_ERR(pdev); 136 return PTR_ERR(pdev);
110 } 137 }
111 138
112 omap_device_disable_idle_on_suspend(pdev);
113
114 gpio_bank_count++;
115 return 0; 139 return 0;
116} 140}
117 141
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index fc6987578920..59c6dc16dd1d 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -75,16 +75,6 @@ static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
75static struct powerdomain *core_pwrdm, *per_pwrdm; 75static struct powerdomain *core_pwrdm, *per_pwrdm;
76static struct powerdomain *cam_pwrdm; 76static struct powerdomain *cam_pwrdm;
77 77
78static inline void omap3_per_save_context(void)
79{
80 omap_gpio_save_context();
81}
82
83static inline void omap3_per_restore_context(void)
84{
85 omap_gpio_restore_context();
86}
87
88static void omap3_enable_io_chain(void) 78static void omap3_enable_io_chain(void)
89{ 79{
90 int timeout = 0; 80 int timeout = 0;
@@ -332,8 +322,6 @@ void omap_sram_idle(void)
332 if (per_next_state < PWRDM_POWER_ON) { 322 if (per_next_state < PWRDM_POWER_ON) {
333 per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0; 323 per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
334 omap2_gpio_prepare_for_idle(per_going_off); 324 omap2_gpio_prepare_for_idle(per_going_off);
335 if (per_next_state == PWRDM_POWER_OFF)
336 omap3_per_save_context();
337 } 325 }
338 326
339 /* CORE */ 327 /* CORE */
@@ -399,8 +387,6 @@ void omap_sram_idle(void)
399 if (per_next_state < PWRDM_POWER_ON) { 387 if (per_next_state < PWRDM_POWER_ON) {
400 per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm); 388 per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);
401 omap2_gpio_resume_after_idle(); 389 omap2_gpio_resume_after_idle();
402 if (per_prev_state == PWRDM_POWER_OFF)
403 omap3_per_restore_context();
404 } 390 }
405 391
406 /* Disable IO-PAD and IO-CHAIN wakeup */ 392 /* Disable IO-PAD and IO-CHAIN wakeup */
diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h
index 9e86ee0aed0a..cb75b657b04b 100644
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -162,13 +162,6 @@
162 IH_MPUIO_BASE + ((nr) & 0x0f) : \ 162 IH_MPUIO_BASE + ((nr) & 0x0f) : \
163 IH_GPIO_BASE + (nr)) 163 IH_GPIO_BASE + (nr))
164 164
165#define METHOD_MPUIO 0
166#define METHOD_GPIO_1510 1
167#define METHOD_GPIO_1610 2
168#define METHOD_GPIO_7XX 3
169#define METHOD_GPIO_24XX 5
170#define METHOD_GPIO_44XX 6
171
172struct omap_gpio_dev_attr { 165struct omap_gpio_dev_attr {
173 int bank_width; /* GPIO bank width */ 166 int bank_width; /* GPIO bank width */
174 bool dbck_flag; /* dbck required or not - True for OMAP3&4 */ 167 bool dbck_flag; /* dbck required or not - True for OMAP3&4 */
@@ -184,10 +177,21 @@ struct omap_gpio_reg_offs {
184 u16 irqstatus; 177 u16 irqstatus;
185 u16 irqstatus2; 178 u16 irqstatus2;
186 u16 irqenable; 179 u16 irqenable;
180 u16 irqenable2;
187 u16 set_irqenable; 181 u16 set_irqenable;
188 u16 clr_irqenable; 182 u16 clr_irqenable;
189 u16 debounce; 183 u16 debounce;
190 u16 debounce_en; 184 u16 debounce_en;
185 u16 ctrl;
186 u16 wkup_en;
187 u16 leveldetect0;
188 u16 leveldetect1;
189 u16 risingdetect;
190 u16 fallingdetect;
191 u16 irqctrl;
192 u16 edgectrl1;
193 u16 edgectrl2;
194 u16 pinctrl;
191 195
192 bool irqenable_inv; 196 bool irqenable_inv;
193}; 197};
@@ -198,19 +202,20 @@ struct omap_gpio_platform_data {
198 int bank_width; /* GPIO bank width */ 202 int bank_width; /* GPIO bank width */
199 int bank_stride; /* Only needed for omap1 MPUIO */ 203 int bank_stride; /* Only needed for omap1 MPUIO */
200 bool dbck_flag; /* dbck required or not - True for OMAP3&4 */ 204 bool dbck_flag; /* dbck required or not - True for OMAP3&4 */
205 bool loses_context; /* whether the bank would ever lose context */
206 bool is_mpuio; /* whether the bank is of type MPUIO */
207 u32 non_wakeup_gpios;
201 208
202 struct omap_gpio_reg_offs *regs; 209 struct omap_gpio_reg_offs *regs;
203};
204 210
205/* TODO: Analyze removing gpio_bank_count usage from driver code */ 211 /* Return context loss count due to PM states changing */
206extern int gpio_bank_count; 212 int (*get_context_loss_count)(struct device *dev);
213};
207 214
208extern void omap2_gpio_prepare_for_idle(int off_mode); 215extern void omap2_gpio_prepare_for_idle(int off_mode);
209extern void omap2_gpio_resume_after_idle(void); 216extern void omap2_gpio_resume_after_idle(void);
210extern void omap_set_gpio_debounce(int gpio, int enable); 217extern void omap_set_gpio_debounce(int gpio, int enable);
211extern void omap_set_gpio_debounce_time(int gpio, int enable); 218extern void omap_set_gpio_debounce_time(int gpio, int enable);
212extern void omap_gpio_save_context(void);
213extern void omap_gpio_restore_context(void);
214/*-------------------------------------------------------------------------*/ 219/*-------------------------------------------------------------------------*/
215 220
216/* Wrappers for "new style" GPIO calls, using the new infrastructure 221/* Wrappers for "new style" GPIO calls, using the new infrastructure
diff --git a/arch/x86/platform/ce4100/falconfalls.dts b/arch/x86/platform/ce4100/falconfalls.dts
index e70be38ce039..ce874f872cc6 100644
--- a/arch/x86/platform/ce4100/falconfalls.dts
+++ b/arch/x86/platform/ce4100/falconfalls.dts
@@ -208,16 +208,19 @@
208 interrupts = <14 1>; 208 interrupts = <14 1>;
209 }; 209 };
210 210
211 gpio@b,1 { 211 pcigpio: gpio@b,1 {
212 #gpio-cells = <2>;
213 #interrupt-cells = <2>;
212 compatible = "pci8086,2e67.2", 214 compatible = "pci8086,2e67.2",
213 "pci8086,2e67", 215 "pci8086,2e67",
214 "pciclassff0000", 216 "pciclassff0000",
215 "pciclassff00"; 217 "pciclassff00";
216 218
217 #gpio-cells = <2>;
218 reg = <0x15900 0x0 0x0 0x0 0x0>; 219 reg = <0x15900 0x0 0x0 0x0 0x0>;
219 interrupts = <15 1>; 220 interrupts = <15 1>;
221 interrupt-controller;
220 gpio-controller; 222 gpio-controller;
223 intel,muxctl = <0>;
221 }; 224 };
222 225
223 i2c-controller@b,2 { 226 i2c-controller@b,2 {
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index d0c41188d4e5..dbb1909ca0a2 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -225,6 +225,12 @@ config GPIO_MAX732X_IRQ
225 Say yes here to enable the max732x to be used as an interrupt 225 Say yes here to enable the max732x to be used as an interrupt
226 controller. It requires the driver to be built in the kernel. 226 controller. It requires the driver to be built in the kernel.
227 227
228config GPIO_MC9S08DZ60
229 bool "MX35 3DS BOARD MC9S08DZ60 GPIO functions"
230 depends on I2C && MACH_MX35_3DS
231 help
232 Select this to enable the MC9S08DZ60 GPIO driver
233
228config GPIO_PCA953X 234config GPIO_PCA953X
229 tristate "PCA953x, PCA955x, TCA64xx, and MAX7310 I/O ports" 235 tristate "PCA953x, PCA955x, TCA64xx, and MAX7310 I/O ports"
230 depends on I2C 236 depends on I2C
@@ -411,6 +417,14 @@ config GPIO_ML_IOH
411 Hub) which is for IVI(In-Vehicle Infotainment) use. 417 Hub) which is for IVI(In-Vehicle Infotainment) use.
412 This driver can access the IOH's GPIO device. 418 This driver can access the IOH's GPIO device.
413 419
420config GPIO_SODAVILLE
421 bool "Intel Sodaville GPIO support"
422 depends on X86 && PCI && OF
423 select GPIO_GENERIC
424 select GENERIC_IRQ_CHIP
425 help
426 Say Y here to support Intel Sodaville GPIO.
427
414config GPIO_TIMBERDALE 428config GPIO_TIMBERDALE
415 bool "Support for timberdale GPIO IP" 429 bool "Support for timberdale GPIO IP"
416 depends on MFD_TIMBERDALE && HAS_IOMEM 430 depends on MFD_TIMBERDALE && HAS_IOMEM
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index fa10df604c01..593bdcd1976e 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_GPIO_MAX7300) += gpio-max7300.o
26obj-$(CONFIG_GPIO_MAX7301) += gpio-max7301.o 26obj-$(CONFIG_GPIO_MAX7301) += gpio-max7301.o
27obj-$(CONFIG_GPIO_MAX732X) += gpio-max732x.o 27obj-$(CONFIG_GPIO_MAX732X) += gpio-max732x.o
28obj-$(CONFIG_GPIO_MC33880) += gpio-mc33880.o 28obj-$(CONFIG_GPIO_MC33880) += gpio-mc33880.o
29obj-$(CONFIG_GPIO_MC9S08DZ60) += gpio-mc9s08dz60.o
29obj-$(CONFIG_GPIO_MCP23S08) += gpio-mcp23s08.o 30obj-$(CONFIG_GPIO_MCP23S08) += gpio-mcp23s08.o
30obj-$(CONFIG_GPIO_ML_IOH) += gpio-ml-ioh.o 31obj-$(CONFIG_GPIO_ML_IOH) += gpio-ml-ioh.o
31obj-$(CONFIG_GPIO_MPC5200) += gpio-mpc5200.o 32obj-$(CONFIG_GPIO_MPC5200) += gpio-mpc5200.o
@@ -45,6 +46,7 @@ obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o
45obj-$(CONFIG_PLAT_SAMSUNG) += gpio-samsung.o 46obj-$(CONFIG_PLAT_SAMSUNG) += gpio-samsung.o
46obj-$(CONFIG_ARCH_SA1100) += gpio-sa1100.o 47obj-$(CONFIG_ARCH_SA1100) += gpio-sa1100.o
47obj-$(CONFIG_GPIO_SCH) += gpio-sch.o 48obj-$(CONFIG_GPIO_SCH) += gpio-sch.o
49obj-$(CONFIG_GPIO_SODAVILLE) += gpio-sodaville.o
48obj-$(CONFIG_GPIO_STMPE) += gpio-stmpe.o 50obj-$(CONFIG_GPIO_STMPE) += gpio-stmpe.o
49obj-$(CONFIG_GPIO_SX150X) += gpio-sx150x.o 51obj-$(CONFIG_GPIO_SX150X) += gpio-sx150x.o
50obj-$(CONFIG_GPIO_TC3589X) += gpio-tc3589x.o 52obj-$(CONFIG_GPIO_TC3589X) += gpio-tc3589x.o
diff --git a/drivers/gpio/gpio-mc9s08dz60.c b/drivers/gpio/gpio-mc9s08dz60.c
new file mode 100644
index 000000000000..2738cc44d636
--- /dev/null
+++ b/drivers/gpio/gpio-mc9s08dz60.c
@@ -0,0 +1,161 @@
1/*
2 * Copyright 2009-2012 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * Author: Wu Guoxing <b39297@freescale.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/slab.h>
20#include <linux/i2c.h>
21#include <linux/gpio.h>
22
23#define GPIO_GROUP_NUM 2
24#define GPIO_NUM_PER_GROUP 8
25#define GPIO_NUM (GPIO_GROUP_NUM*GPIO_NUM_PER_GROUP)
26
27struct mc9s08dz60 {
28 struct i2c_client *client;
29 struct gpio_chip chip;
30};
31
32static inline struct mc9s08dz60 *to_mc9s08dz60(struct gpio_chip *gc)
33{
34 return container_of(gc, struct mc9s08dz60, chip);
35}
36
37
38static void mc9s_gpio_to_reg_and_bit(int offset, u8 *reg, u8 *bit)
39{
40 *reg = 0x20 + offset / GPIO_NUM_PER_GROUP;
41 *bit = offset % GPIO_NUM_PER_GROUP;
42}
43
44static int mc9s08dz60_get_value(struct gpio_chip *gc, unsigned offset)
45{
46 u8 reg, bit;
47 s32 value;
48 struct mc9s08dz60 *mc9s = to_mc9s08dz60(gc);
49
50 mc9s_gpio_to_reg_and_bit(offset, &reg, &bit);
51 value = i2c_smbus_read_byte_data(mc9s->client, reg);
52
53 return (value >= 0) ? (value >> bit) & 0x1 : 0;
54}
55
56static int mc9s08dz60_set(struct mc9s08dz60 *mc9s, unsigned offset, int val)
57{
58 u8 reg, bit;
59 s32 value;
60
61 mc9s_gpio_to_reg_and_bit(offset, &reg, &bit);
62 value = i2c_smbus_read_byte_data(mc9s->client, reg);
63 if (value >= 0) {
64 if (val)
65 value |= 1 << bit;
66 else
67 value &= ~(1 << bit);
68
69 return i2c_smbus_write_byte_data(mc9s->client, reg, value);
70 } else
71 return value;
72
73}
74
75
76static void mc9s08dz60_set_value(struct gpio_chip *gc, unsigned offset, int val)
77{
78 struct mc9s08dz60 *mc9s = to_mc9s08dz60(gc);
79
80 mc9s08dz60_set(mc9s, offset, val);
81}
82
83static int mc9s08dz60_direction_output(struct gpio_chip *gc,
84 unsigned offset, int val)
85{
86 struct mc9s08dz60 *mc9s = to_mc9s08dz60(gc);
87
88 return mc9s08dz60_set(mc9s, offset, val);
89}
90
91static int mc9s08dz60_probe(struct i2c_client *client,
92 const struct i2c_device_id *id)
93{
94 int ret = 0;
95 struct mc9s08dz60 *mc9s;
96
97 mc9s = kzalloc(sizeof(*mc9s), GFP_KERNEL);
98 if (!mc9s)
99 return -ENOMEM;
100
101 mc9s->chip.label = client->name;
102 mc9s->chip.base = -1;
103 mc9s->chip.dev = &client->dev;
104 mc9s->chip.owner = THIS_MODULE;
105 mc9s->chip.ngpio = GPIO_NUM;
106 mc9s->chip.can_sleep = 1;
107 mc9s->chip.get = mc9s08dz60_get_value;
108 mc9s->chip.set = mc9s08dz60_set_value;
109 mc9s->chip.direction_output = mc9s08dz60_direction_output;
110 mc9s->client = client;
111 i2c_set_clientdata(client, mc9s);
112
113 ret = gpiochip_add(&mc9s->chip);
114 if (ret)
115 goto error;
116
117 return 0;
118
119 error:
120 kfree(mc9s);
121 return ret;
122}
123
124static int mc9s08dz60_remove(struct i2c_client *client)
125{
126 struct mc9s08dz60 *mc9s;
127 int ret;
128
129 mc9s = i2c_get_clientdata(client);
130
131 ret = gpiochip_remove(&mc9s->chip);
132 if (!ret)
133 kfree(mc9s);
134
135 return ret;
136
137}
138
139static const struct i2c_device_id mc9s08dz60_id[] = {
140 {"mc9s08dz60", 0},
141 {},
142};
143
144MODULE_DEVICE_TABLE(i2c, mc9s08dz60_id);
145
146static struct i2c_driver mc9s08dz60_i2c_driver = {
147 .driver = {
148 .owner = THIS_MODULE,
149 .name = "mc9s08dz60",
150 },
151 .probe = mc9s08dz60_probe,
152 .remove = mc9s08dz60_remove,
153 .id_table = mc9s08dz60_id,
154};
155
156module_i2c_driver(mc9s08dz60_i2c_driver);
157
158MODULE_AUTHOR("Freescale Semiconductor, Inc. "
159 "Wu Guoxing <b39297@freescale.com>");
160MODULE_DESCRIPTION("mc9s08dz60 gpio function on mx35 3ds board");
161MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 0b0562979171..f49bd6f47a50 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -21,6 +21,7 @@
21#include <linux/io.h> 21#include <linux/io.h>
22#include <linux/slab.h> 22#include <linux/slab.h>
23#include <linux/pm_runtime.h> 23#include <linux/pm_runtime.h>
24#include <linux/pm.h>
24 25
25#include <mach/hardware.h> 26#include <mach/hardware.h>
26#include <asm/irq.h> 27#include <asm/irq.h>
@@ -28,19 +29,36 @@
28#include <asm/gpio.h> 29#include <asm/gpio.h>
29#include <asm/mach/irq.h> 30#include <asm/mach/irq.h>
30 31
32#define OFF_MODE 1
33
34static LIST_HEAD(omap_gpio_list);
35
36struct gpio_regs {
37 u32 irqenable1;
38 u32 irqenable2;
39 u32 wake_en;
40 u32 ctrl;
41 u32 oe;
42 u32 leveldetect0;
43 u32 leveldetect1;
44 u32 risingdetect;
45 u32 fallingdetect;
46 u32 dataout;
47 u32 debounce;
48 u32 debounce_en;
49};
50
31struct gpio_bank { 51struct gpio_bank {
52 struct list_head node;
32 unsigned long pbase; 53 unsigned long pbase;
33 void __iomem *base; 54 void __iomem *base;
34 u16 irq; 55 u16 irq;
35 u16 virtual_irq_start; 56 u16 virtual_irq_start;
36 int method;
37 u32 suspend_wakeup; 57 u32 suspend_wakeup;
38#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
39 u32 saved_wakeup; 58 u32 saved_wakeup;
40#endif
41 u32 non_wakeup_gpios; 59 u32 non_wakeup_gpios;
42 u32 enabled_non_wakeup_gpios; 60 u32 enabled_non_wakeup_gpios;
43 61 struct gpio_regs context;
44 u32 saved_datain; 62 u32 saved_datain;
45 u32 saved_fallingdetect; 63 u32 saved_fallingdetect;
46 u32 saved_risingdetect; 64 u32 saved_risingdetect;
@@ -51,44 +69,27 @@ struct gpio_bank {
51 struct clk *dbck; 69 struct clk *dbck;
52 u32 mod_usage; 70 u32 mod_usage;
53 u32 dbck_enable_mask; 71 u32 dbck_enable_mask;
72 bool dbck_enabled;
54 struct device *dev; 73 struct device *dev;
74 bool is_mpuio;
55 bool dbck_flag; 75 bool dbck_flag;
76 bool loses_context;
56 int stride; 77 int stride;
57 u32 width; 78 u32 width;
79 int context_loss_count;
80 u16 id;
81 int power_mode;
82 bool workaround_enabled;
58 83
59 void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable); 84 void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable);
85 int (*get_context_loss_count)(struct device *dev);
60 86
61 struct omap_gpio_reg_offs *regs; 87 struct omap_gpio_reg_offs *regs;
62}; 88};
63 89
64#ifdef CONFIG_ARCH_OMAP3
65struct omap3_gpio_regs {
66 u32 irqenable1;
67 u32 irqenable2;
68 u32 wake_en;
69 u32 ctrl;
70 u32 oe;
71 u32 leveldetect0;
72 u32 leveldetect1;
73 u32 risingdetect;
74 u32 fallingdetect;
75 u32 dataout;
76};
77
78static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
79#endif
80
81/*
82 * TODO: Cleanup gpio_bank usage as it is having information
83 * related to all instances of the device
84 */
85static struct gpio_bank *gpio_bank;
86
87/* TODO: Analyze removing gpio_bank_count usage from driver code */
88int gpio_bank_count;
89
90#define GPIO_INDEX(bank, gpio) (gpio % bank->width) 90#define GPIO_INDEX(bank, gpio) (gpio % bank->width)
91#define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio)) 91#define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
92#define GPIO_MOD_CTRL_BIT BIT(0)
92 93
93static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input) 94static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
94{ 95{
@@ -102,6 +103,7 @@ static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
102 else 103 else
103 l &= ~(1 << gpio); 104 l &= ~(1 << gpio);
104 __raw_writel(l, reg); 105 __raw_writel(l, reg);
106 bank->context.oe = l;
105} 107}
106 108
107 109
@@ -132,6 +134,7 @@ static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable)
132 else 134 else
133 l &= ~gpio_bit; 135 l &= ~gpio_bit;
134 __raw_writel(l, reg); 136 __raw_writel(l, reg);
137 bank->context.dataout = l;
135} 138}
136 139
137static int _get_gpio_datain(struct gpio_bank *bank, int gpio) 140static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
@@ -160,6 +163,22 @@ static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
160 __raw_writel(l, base + reg); 163 __raw_writel(l, base + reg);
161} 164}
162 165
166static inline void _gpio_dbck_enable(struct gpio_bank *bank)
167{
168 if (bank->dbck_enable_mask && !bank->dbck_enabled) {
169 clk_enable(bank->dbck);
170 bank->dbck_enabled = true;
171 }
172}
173
174static inline void _gpio_dbck_disable(struct gpio_bank *bank)
175{
176 if (bank->dbck_enable_mask && bank->dbck_enabled) {
177 clk_disable(bank->dbck);
178 bank->dbck_enabled = false;
179 }
180}
181
163/** 182/**
164 * _set_gpio_debounce - low level gpio debounce time 183 * _set_gpio_debounce - low level gpio debounce time
165 * @bank: the gpio bank we're acting upon 184 * @bank: the gpio bank we're acting upon
@@ -188,70 +207,74 @@ static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
188 207
189 l = GPIO_BIT(bank, gpio); 208 l = GPIO_BIT(bank, gpio);
190 209
210 clk_enable(bank->dbck);
191 reg = bank->base + bank->regs->debounce; 211 reg = bank->base + bank->regs->debounce;
192 __raw_writel(debounce, reg); 212 __raw_writel(debounce, reg);
193 213
194 reg = bank->base + bank->regs->debounce_en; 214 reg = bank->base + bank->regs->debounce_en;
195 val = __raw_readl(reg); 215 val = __raw_readl(reg);
196 216
197 if (debounce) { 217 if (debounce)
198 val |= l; 218 val |= l;
199 clk_enable(bank->dbck); 219 else
200 } else {
201 val &= ~l; 220 val &= ~l;
202 clk_disable(bank->dbck);
203 }
204 bank->dbck_enable_mask = val; 221 bank->dbck_enable_mask = val;
205 222
206 __raw_writel(val, reg); 223 __raw_writel(val, reg);
224 clk_disable(bank->dbck);
225 /*
226 * Enable debounce clock per module.
227 * This call is mandatory because in omap_gpio_request() when
228 * *_runtime_get_sync() is called, _gpio_dbck_enable() within
229 * runtime callbck fails to turn on dbck because dbck_enable_mask
230 * used within _gpio_dbck_enable() is still not initialized at
231 * that point. Therefore we have to enable dbck here.
232 */
233 _gpio_dbck_enable(bank);
234 if (bank->dbck_enable_mask) {
235 bank->context.debounce = debounce;
236 bank->context.debounce_en = val;
237 }
207} 238}
208 239
209#ifdef CONFIG_ARCH_OMAP2PLUS 240static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio,
210static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
211 int trigger) 241 int trigger)
212{ 242{
213 void __iomem *base = bank->base; 243 void __iomem *base = bank->base;
214 u32 gpio_bit = 1 << gpio; 244 u32 gpio_bit = 1 << gpio;
215 245
216 if (cpu_is_omap44xx()) { 246 _gpio_rmw(base, bank->regs->leveldetect0, gpio_bit,
217 _gpio_rmw(base, OMAP4_GPIO_LEVELDETECT0, gpio_bit, 247 trigger & IRQ_TYPE_LEVEL_LOW);
218 trigger & IRQ_TYPE_LEVEL_LOW); 248 _gpio_rmw(base, bank->regs->leveldetect1, gpio_bit,
219 _gpio_rmw(base, OMAP4_GPIO_LEVELDETECT1, gpio_bit, 249 trigger & IRQ_TYPE_LEVEL_HIGH);
220 trigger & IRQ_TYPE_LEVEL_HIGH); 250 _gpio_rmw(base, bank->regs->risingdetect, gpio_bit,
221 _gpio_rmw(base, OMAP4_GPIO_RISINGDETECT, gpio_bit, 251 trigger & IRQ_TYPE_EDGE_RISING);
222 trigger & IRQ_TYPE_EDGE_RISING); 252 _gpio_rmw(base, bank->regs->fallingdetect, gpio_bit,
223 _gpio_rmw(base, OMAP4_GPIO_FALLINGDETECT, gpio_bit, 253 trigger & IRQ_TYPE_EDGE_FALLING);
224 trigger & IRQ_TYPE_EDGE_FALLING); 254
225 } else { 255 bank->context.leveldetect0 =
226 _gpio_rmw(base, OMAP24XX_GPIO_LEVELDETECT0, gpio_bit, 256 __raw_readl(bank->base + bank->regs->leveldetect0);
227 trigger & IRQ_TYPE_LEVEL_LOW); 257 bank->context.leveldetect1 =
228 _gpio_rmw(base, OMAP24XX_GPIO_LEVELDETECT1, gpio_bit, 258 __raw_readl(bank->base + bank->regs->leveldetect1);
229 trigger & IRQ_TYPE_LEVEL_HIGH); 259 bank->context.risingdetect =
230 _gpio_rmw(base, OMAP24XX_GPIO_RISINGDETECT, gpio_bit, 260 __raw_readl(bank->base + bank->regs->risingdetect);
231 trigger & IRQ_TYPE_EDGE_RISING); 261 bank->context.fallingdetect =
232 _gpio_rmw(base, OMAP24XX_GPIO_FALLINGDETECT, gpio_bit, 262 __raw_readl(bank->base + bank->regs->fallingdetect);
233 trigger & IRQ_TYPE_EDGE_FALLING); 263
234 }
235 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) { 264 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
236 if (cpu_is_omap44xx()) { 265 _gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0);
237 _gpio_rmw(base, OMAP4_GPIO_IRQWAKEN0, gpio_bit, 266 bank->context.wake_en =
238 trigger != 0); 267 __raw_readl(bank->base + bank->regs->wkup_en);
239 } else {
240 /*
241 * GPIO wakeup request can only be generated on edge
242 * transitions
243 */
244 if (trigger & IRQ_TYPE_EDGE_BOTH)
245 __raw_writel(1 << gpio, bank->base
246 + OMAP24XX_GPIO_SETWKUENA);
247 else
248 __raw_writel(1 << gpio, bank->base
249 + OMAP24XX_GPIO_CLEARWKUENA);
250 }
251 } 268 }
269
252 /* This part needs to be executed always for OMAP{34xx, 44xx} */ 270 /* This part needs to be executed always for OMAP{34xx, 44xx} */
253 if (cpu_is_omap34xx() || cpu_is_omap44xx() || 271 if (!bank->regs->irqctrl) {
254 (bank->non_wakeup_gpios & gpio_bit)) { 272 /* On omap24xx proceed only when valid GPIO bit is set */
273 if (bank->non_wakeup_gpios) {
274 if (!(bank->non_wakeup_gpios & gpio_bit))
275 goto exit;
276 }
277
255 /* 278 /*
256 * Log the edge gpio and manually trigger the IRQ 279 * Log the edge gpio and manually trigger the IRQ
257 * after resume if the input level changes 280 * after resume if the input level changes
@@ -264,17 +287,11 @@ static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
264 bank->enabled_non_wakeup_gpios &= ~gpio_bit; 287 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
265 } 288 }
266 289
267 if (cpu_is_omap44xx()) { 290exit:
268 bank->level_mask = 291 bank->level_mask =
269 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) | 292 __raw_readl(bank->base + bank->regs->leveldetect0) |
270 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1); 293 __raw_readl(bank->base + bank->regs->leveldetect1);
271 } else {
272 bank->level_mask =
273 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
274 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
275 }
276} 294}
277#endif
278 295
279#ifdef CONFIG_ARCH_OMAP1 296#ifdef CONFIG_ARCH_OMAP1
280/* 297/*
@@ -286,23 +303,10 @@ static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
286 void __iomem *reg = bank->base; 303 void __iomem *reg = bank->base;
287 u32 l = 0; 304 u32 l = 0;
288 305
289 switch (bank->method) { 306 if (!bank->regs->irqctrl)
290 case METHOD_MPUIO:
291 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
292 break;
293#ifdef CONFIG_ARCH_OMAP15XX
294 case METHOD_GPIO_1510:
295 reg += OMAP1510_GPIO_INT_CONTROL;
296 break;
297#endif
298#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
299 case METHOD_GPIO_7XX:
300 reg += OMAP7XX_GPIO_INT_CONTROL;
301 break;
302#endif
303 default:
304 return; 307 return;
305 } 308
309 reg += bank->regs->irqctrl;
306 310
307 l = __raw_readl(reg); 311 l = __raw_readl(reg);
308 if ((l >> gpio) & 1) 312 if ((l >> gpio) & 1)
@@ -312,31 +316,21 @@ static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
312 316
313 __raw_writel(l, reg); 317 __raw_writel(l, reg);
314} 318}
319#else
320static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
315#endif 321#endif
316 322
317static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger) 323static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
318{ 324{
319 void __iomem *reg = bank->base; 325 void __iomem *reg = bank->base;
326 void __iomem *base = bank->base;
320 u32 l = 0; 327 u32 l = 0;
321 328
322 switch (bank->method) { 329 if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
323#ifdef CONFIG_ARCH_OMAP1 330 set_gpio_trigger(bank, gpio, trigger);
324 case METHOD_MPUIO: 331 } else if (bank->regs->irqctrl) {
325 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride; 332 reg += bank->regs->irqctrl;
326 l = __raw_readl(reg); 333
327 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
328 bank->toggle_mask |= 1 << gpio;
329 if (trigger & IRQ_TYPE_EDGE_RISING)
330 l |= 1 << gpio;
331 else if (trigger & IRQ_TYPE_EDGE_FALLING)
332 l &= ~(1 << gpio);
333 else
334 goto bad;
335 break;
336#endif
337#ifdef CONFIG_ARCH_OMAP15XX
338 case METHOD_GPIO_1510:
339 reg += OMAP1510_GPIO_INT_CONTROL;
340 l = __raw_readl(reg); 334 l = __raw_readl(reg);
341 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) 335 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
342 bank->toggle_mask |= 1 << gpio; 336 bank->toggle_mask |= 1 << gpio;
@@ -345,15 +339,15 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
345 else if (trigger & IRQ_TYPE_EDGE_FALLING) 339 else if (trigger & IRQ_TYPE_EDGE_FALLING)
346 l &= ~(1 << gpio); 340 l &= ~(1 << gpio);
347 else 341 else
348 goto bad; 342 return -EINVAL;
349 break; 343
350#endif 344 __raw_writel(l, reg);
351#ifdef CONFIG_ARCH_OMAP16XX 345 } else if (bank->regs->edgectrl1) {
352 case METHOD_GPIO_1610:
353 if (gpio & 0x08) 346 if (gpio & 0x08)
354 reg += OMAP1610_GPIO_EDGE_CTRL2; 347 reg += bank->regs->edgectrl2;
355 else 348 else
356 reg += OMAP1610_GPIO_EDGE_CTRL1; 349 reg += bank->regs->edgectrl1;
350
357 gpio &= 0x07; 351 gpio &= 0x07;
358 l = __raw_readl(reg); 352 l = __raw_readl(reg);
359 l &= ~(3 << (gpio << 1)); 353 l &= ~(3 << (gpio << 1));
@@ -361,40 +355,14 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
361 l |= 2 << (gpio << 1); 355 l |= 2 << (gpio << 1);
362 if (trigger & IRQ_TYPE_EDGE_FALLING) 356 if (trigger & IRQ_TYPE_EDGE_FALLING)
363 l |= 1 << (gpio << 1); 357 l |= 1 << (gpio << 1);
364 if (trigger) 358
365 /* Enable wake-up during idle for dynamic tick */ 359 /* Enable wake-up during idle for dynamic tick */
366 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA); 360 _gpio_rmw(base, bank->regs->wkup_en, 1 << gpio, trigger);
367 else 361 bank->context.wake_en =
368 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA); 362 __raw_readl(bank->base + bank->regs->wkup_en);
369 break; 363 __raw_writel(l, reg);
370#endif
371#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
372 case METHOD_GPIO_7XX:
373 reg += OMAP7XX_GPIO_INT_CONTROL;
374 l = __raw_readl(reg);
375 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
376 bank->toggle_mask |= 1 << gpio;
377 if (trigger & IRQ_TYPE_EDGE_RISING)
378 l |= 1 << gpio;
379 else if (trigger & IRQ_TYPE_EDGE_FALLING)
380 l &= ~(1 << gpio);
381 else
382 goto bad;
383 break;
384#endif
385#ifdef CONFIG_ARCH_OMAP2PLUS
386 case METHOD_GPIO_24XX:
387 case METHOD_GPIO_44XX:
388 set_24xx_gpio_triggering(bank, gpio, trigger);
389 return 0;
390#endif
391 default:
392 goto bad;
393 } 364 }
394 __raw_writel(l, reg);
395 return 0; 365 return 0;
396bad:
397 return -EINVAL;
398} 366}
399 367
400static int gpio_irq_type(struct irq_data *d, unsigned type) 368static int gpio_irq_type(struct irq_data *d, unsigned type)
@@ -412,12 +380,12 @@ static int gpio_irq_type(struct irq_data *d, unsigned type)
412 if (type & ~IRQ_TYPE_SENSE_MASK) 380 if (type & ~IRQ_TYPE_SENSE_MASK)
413 return -EINVAL; 381 return -EINVAL;
414 382
415 /* OMAP1 allows only only edge triggering */ 383 bank = irq_data_get_irq_chip_data(d);
416 if (!cpu_class_is_omap2() 384
417 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH))) 385 if (!bank->regs->leveldetect0 &&
386 (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
418 return -EINVAL; 387 return -EINVAL;
419 388
420 bank = irq_data_get_irq_chip_data(d);
421 spin_lock_irqsave(&bank->lock, flags); 389 spin_lock_irqsave(&bank->lock, flags);
422 retval = _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), type); 390 retval = _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), type);
423 spin_unlock_irqrestore(&bank->lock, flags); 391 spin_unlock_irqrestore(&bank->lock, flags);
@@ -484,6 +452,7 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
484 } 452 }
485 453
486 __raw_writel(l, reg); 454 __raw_writel(l, reg);
455 bank->context.irqenable1 = l;
487} 456}
488 457
489static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) 458static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
@@ -504,6 +473,7 @@ static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
504 } 473 }
505 474
506 __raw_writel(l, reg); 475 __raw_writel(l, reg);
476 bank->context.irqenable1 = l;
507} 477}
508 478
509static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable) 479static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
@@ -567,38 +537,39 @@ static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
567 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); 537 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
568 unsigned long flags; 538 unsigned long flags;
569 539
570 spin_lock_irqsave(&bank->lock, flags); 540 /*
541 * If this is the first gpio_request for the bank,
542 * enable the bank module.
543 */
544 if (!bank->mod_usage)
545 pm_runtime_get_sync(bank->dev);
571 546
547 spin_lock_irqsave(&bank->lock, flags);
572 /* Set trigger to none. You need to enable the desired trigger with 548 /* Set trigger to none. You need to enable the desired trigger with
573 * request_irq() or set_irq_type(). 549 * request_irq() or set_irq_type().
574 */ 550 */
575 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); 551 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
576 552
577#ifdef CONFIG_ARCH_OMAP15XX 553 if (bank->regs->pinctrl) {
578 if (bank->method == METHOD_GPIO_1510) { 554 void __iomem *reg = bank->base + bank->regs->pinctrl;
579 void __iomem *reg;
580 555
581 /* Claim the pin for MPU */ 556 /* Claim the pin for MPU */
582 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
583 __raw_writel(__raw_readl(reg) | (1 << offset), reg); 557 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
584 } 558 }
585#endif 559
586 if (!cpu_class_is_omap1()) { 560 if (bank->regs->ctrl && !bank->mod_usage) {
587 if (!bank->mod_usage) { 561 void __iomem *reg = bank->base + bank->regs->ctrl;
588 void __iomem *reg = bank->base; 562 u32 ctrl;
589 u32 ctrl; 563
590 564 ctrl = __raw_readl(reg);
591 if (cpu_is_omap24xx() || cpu_is_omap34xx()) 565 /* Module is enabled, clocks are not gated */
592 reg += OMAP24XX_GPIO_CTRL; 566 ctrl &= ~GPIO_MOD_CTRL_BIT;
593 else if (cpu_is_omap44xx()) 567 __raw_writel(ctrl, reg);
594 reg += OMAP4_GPIO_CTRL; 568 bank->context.ctrl = ctrl;
595 ctrl = __raw_readl(reg);
596 /* Module is enabled, clocks are not gated */
597 ctrl &= 0xFFFFFFFE;
598 __raw_writel(ctrl, reg);
599 }
600 bank->mod_usage |= 1 << offset;
601 } 569 }
570
571 bank->mod_usage |= 1 << offset;
572
602 spin_unlock_irqrestore(&bank->lock, flags); 573 spin_unlock_irqrestore(&bank->lock, flags);
603 574
604 return 0; 575 return 0;
@@ -607,48 +578,40 @@ static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
607static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) 578static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
608{ 579{
609 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); 580 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
581 void __iomem *base = bank->base;
610 unsigned long flags; 582 unsigned long flags;
611 583
612 spin_lock_irqsave(&bank->lock, flags); 584 spin_lock_irqsave(&bank->lock, flags);
613#ifdef CONFIG_ARCH_OMAP16XX 585
614 if (bank->method == METHOD_GPIO_1610) { 586 if (bank->regs->wkup_en) {
615 /* Disable wake-up during idle for dynamic tick */
616 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
617 __raw_writel(1 << offset, reg);
618 }
619#endif
620#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
621 if (bank->method == METHOD_GPIO_24XX) {
622 /* Disable wake-up during idle for dynamic tick */
623 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
624 __raw_writel(1 << offset, reg);
625 }
626#endif
627#ifdef CONFIG_ARCH_OMAP4
628 if (bank->method == METHOD_GPIO_44XX) {
629 /* Disable wake-up during idle for dynamic tick */ 587 /* Disable wake-up during idle for dynamic tick */
630 void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0; 588 _gpio_rmw(base, bank->regs->wkup_en, 1 << offset, 0);
631 __raw_writel(1 << offset, reg); 589 bank->context.wake_en =
590 __raw_readl(bank->base + bank->regs->wkup_en);
632 } 591 }
633#endif 592
634 if (!cpu_class_is_omap1()) { 593 bank->mod_usage &= ~(1 << offset);
635 bank->mod_usage &= ~(1 << offset); 594
636 if (!bank->mod_usage) { 595 if (bank->regs->ctrl && !bank->mod_usage) {
637 void __iomem *reg = bank->base; 596 void __iomem *reg = bank->base + bank->regs->ctrl;
638 u32 ctrl; 597 u32 ctrl;
639 598
640 if (cpu_is_omap24xx() || cpu_is_omap34xx()) 599 ctrl = __raw_readl(reg);
641 reg += OMAP24XX_GPIO_CTRL; 600 /* Module is disabled, clocks are gated */
642 else if (cpu_is_omap44xx()) 601 ctrl |= GPIO_MOD_CTRL_BIT;
643 reg += OMAP4_GPIO_CTRL; 602 __raw_writel(ctrl, reg);
644 ctrl = __raw_readl(reg); 603 bank->context.ctrl = ctrl;
645 /* Module is disabled, clocks are gated */
646 ctrl |= 1;
647 __raw_writel(ctrl, reg);
648 }
649 } 604 }
605
650 _reset_gpio(bank, bank->chip.base + offset); 606 _reset_gpio(bank, bank->chip.base + offset);
651 spin_unlock_irqrestore(&bank->lock, flags); 607 spin_unlock_irqrestore(&bank->lock, flags);
608
609 /*
610 * If this is the last gpio to be freed in the bank,
611 * disable the bank module.
612 */
613 if (!bank->mod_usage)
614 pm_runtime_put(bank->dev);
652} 615}
653 616
654/* 617/*
@@ -674,6 +637,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
674 637
675 bank = irq_get_handler_data(irq); 638 bank = irq_get_handler_data(irq);
676 isr_reg = bank->base + bank->regs->irqstatus; 639 isr_reg = bank->base + bank->regs->irqstatus;
640 pm_runtime_get_sync(bank->dev);
677 641
678 if (WARN_ON(!isr_reg)) 642 if (WARN_ON(!isr_reg))
679 goto exit; 643 goto exit;
@@ -685,12 +649,8 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
685 enabled = _get_gpio_irqbank_mask(bank); 649 enabled = _get_gpio_irqbank_mask(bank);
686 isr_saved = isr = __raw_readl(isr_reg) & enabled; 650 isr_saved = isr = __raw_readl(isr_reg) & enabled;
687 651
688 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO)) 652 if (bank->level_mask)
689 isr &= 0x0000ffff;
690
691 if (cpu_class_is_omap2()) {
692 level_mask = bank->level_mask & enabled; 653 level_mask = bank->level_mask & enabled;
693 }
694 654
695 /* clear edge sensitive interrupts before handler(s) are 655 /* clear edge sensitive interrupts before handler(s) are
696 called so that we don't miss any interrupt occurred while 656 called so that we don't miss any interrupt occurred while
@@ -718,7 +678,6 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
718 if (!(isr & 1)) 678 if (!(isr & 1))
719 continue; 679 continue;
720 680
721#ifdef CONFIG_ARCH_OMAP1
722 /* 681 /*
723 * Some chips can't respond to both rising and falling 682 * Some chips can't respond to both rising and falling
724 * at the same time. If this irq was requested with 683 * at the same time. If this irq was requested with
@@ -728,7 +687,6 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
728 */ 687 */
729 if (bank->toggle_mask & (1 << gpio_index)) 688 if (bank->toggle_mask & (1 << gpio_index))
730 _toggle_gpio_edge_triggering(bank, gpio_index); 689 _toggle_gpio_edge_triggering(bank, gpio_index);
731#endif
732 690
733 generic_handle_irq(gpio_irq); 691 generic_handle_irq(gpio_irq);
734 } 692 }
@@ -740,6 +698,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
740exit: 698exit:
741 if (!unmasked) 699 if (!unmasked)
742 chained_irq_exit(chip, desc); 700 chained_irq_exit(chip, desc);
701 pm_runtime_put(bank->dev);
743} 702}
744 703
745static void gpio_irq_shutdown(struct irq_data *d) 704static void gpio_irq_shutdown(struct irq_data *d)
@@ -808,14 +767,6 @@ static struct irq_chip gpio_irq_chip = {
808 767
809/*---------------------------------------------------------------------*/ 768/*---------------------------------------------------------------------*/
810 769
811#ifdef CONFIG_ARCH_OMAP1
812
813#define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
814
815#ifdef CONFIG_ARCH_OMAP16XX
816
817#include <linux/platform_device.h>
818
819static int omap_mpuio_suspend_noirq(struct device *dev) 770static int omap_mpuio_suspend_noirq(struct device *dev)
820{ 771{
821 struct platform_device *pdev = to_platform_device(dev); 772 struct platform_device *pdev = to_platform_device(dev);
@@ -869,32 +820,16 @@ static struct platform_device omap_mpuio_device = {
869 /* could list the /proc/iomem resources */ 820 /* could list the /proc/iomem resources */
870}; 821};
871 822
872static inline void mpuio_init(void) 823static inline void mpuio_init(struct gpio_bank *bank)
873{ 824{
874 struct gpio_bank *bank = &gpio_bank[0];
875 platform_set_drvdata(&omap_mpuio_device, bank); 825 platform_set_drvdata(&omap_mpuio_device, bank);
876 826
877 if (platform_driver_register(&omap_mpuio_driver) == 0) 827 if (platform_driver_register(&omap_mpuio_driver) == 0)
878 (void) platform_device_register(&omap_mpuio_device); 828 (void) platform_device_register(&omap_mpuio_device);
879} 829}
880 830
881#else
882static inline void mpuio_init(void) {}
883#endif /* 16xx */
884
885#else
886
887#define bank_is_mpuio(bank) 0
888static inline void mpuio_init(void) {}
889
890#endif
891
892/*---------------------------------------------------------------------*/ 831/*---------------------------------------------------------------------*/
893 832
894/* REVISIT these are stupid implementations! replace by ones that
895 * don't switch on METHOD_* and which mostly avoid spinlocks
896 */
897
898static int gpio_input(struct gpio_chip *chip, unsigned offset) 833static int gpio_input(struct gpio_chip *chip, unsigned offset)
899{ 834{
900 struct gpio_bank *bank; 835 struct gpio_bank *bank;
@@ -1007,78 +942,32 @@ static void __init omap_gpio_show_rev(struct gpio_bank *bank)
1007 */ 942 */
1008static struct lock_class_key gpio_lock_class; 943static struct lock_class_key gpio_lock_class;
1009 944
1010static inline int init_gpio_info(struct platform_device *pdev) 945static void omap_gpio_mod_init(struct gpio_bank *bank)
1011{ 946{
1012 /* TODO: Analyze removing gpio_bank_count usage from driver code */ 947 void __iomem *base = bank->base;
1013 gpio_bank = kzalloc(gpio_bank_count * sizeof(struct gpio_bank), 948 u32 l = 0xffffffff;
1014 GFP_KERNEL);
1015 if (!gpio_bank) {
1016 dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n");
1017 return -ENOMEM;
1018 }
1019 return 0;
1020}
1021 949
1022/* TODO: Cleanup cpu_is_* checks */ 950 if (bank->width == 16)
1023static void omap_gpio_mod_init(struct gpio_bank *bank, int id) 951 l = 0xffff;
1024{
1025 if (cpu_class_is_omap2()) {
1026 if (cpu_is_omap44xx()) {
1027 __raw_writel(0xffffffff, bank->base +
1028 OMAP4_GPIO_IRQSTATUSCLR0);
1029 __raw_writel(0x00000000, bank->base +
1030 OMAP4_GPIO_DEBOUNCENABLE);
1031 /* Initialize interface clk ungated, module enabled */
1032 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
1033 } else if (cpu_is_omap34xx()) {
1034 __raw_writel(0x00000000, bank->base +
1035 OMAP24XX_GPIO_IRQENABLE1);
1036 __raw_writel(0xffffffff, bank->base +
1037 OMAP24XX_GPIO_IRQSTATUS1);
1038 __raw_writel(0x00000000, bank->base +
1039 OMAP24XX_GPIO_DEBOUNCE_EN);
1040
1041 /* Initialize interface clk ungated, module enabled */
1042 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1043 } else if (cpu_is_omap24xx()) {
1044 static const u32 non_wakeup_gpios[] = {
1045 0xe203ffc0, 0x08700040
1046 };
1047 if (id < ARRAY_SIZE(non_wakeup_gpios))
1048 bank->non_wakeup_gpios = non_wakeup_gpios[id];
1049 }
1050 } else if (cpu_class_is_omap1()) {
1051 if (bank_is_mpuio(bank))
1052 __raw_writew(0xffff, bank->base +
1053 OMAP_MPUIO_GPIO_MASKIT / bank->stride);
1054 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1055 __raw_writew(0xffff, bank->base
1056 + OMAP1510_GPIO_INT_MASK);
1057 __raw_writew(0x0000, bank->base
1058 + OMAP1510_GPIO_INT_STATUS);
1059 }
1060 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1061 __raw_writew(0x0000, bank->base
1062 + OMAP1610_GPIO_IRQENABLE1);
1063 __raw_writew(0xffff, bank->base
1064 + OMAP1610_GPIO_IRQSTATUS1);
1065 __raw_writew(0x0014, bank->base
1066 + OMAP1610_GPIO_SYSCONFIG);
1067 952
1068 /* 953 if (bank->is_mpuio) {
1069 * Enable system clock for GPIO module. 954 __raw_writel(l, bank->base + bank->regs->irqenable);
1070 * The CAM_CLK_CTRL *is* really the right place. 955 return;
1071 */
1072 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
1073 ULPD_CAM_CLK_CTRL);
1074 }
1075 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
1076 __raw_writel(0xffffffff, bank->base
1077 + OMAP7XX_GPIO_INT_MASK);
1078 __raw_writel(0x00000000, bank->base
1079 + OMAP7XX_GPIO_INT_STATUS);
1080 }
1081 } 956 }
957
958 _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->irqenable_inv);
959 _gpio_rmw(base, bank->regs->irqstatus, l,
960 bank->regs->irqenable_inv == false);
961 _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->debounce_en != 0);
962 _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->ctrl != 0);
963 if (bank->regs->debounce_en)
964 _gpio_rmw(base, bank->regs->debounce_en, 0, 1);
965
966 /* Save OE default value (0xffffffff) in the context */
967 bank->context.oe = __raw_readl(bank->base + bank->regs->direction);
968 /* Initialize interface clk ungated, module enabled */
969 if (bank->regs->ctrl)
970 _gpio_rmw(base, bank->regs->ctrl, 0, 1);
1082} 971}
1083 972
1084static __init void 973static __init void
@@ -1101,8 +990,8 @@ omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start,
1101 ct->chip.irq_mask = irq_gc_mask_set_bit; 990 ct->chip.irq_mask = irq_gc_mask_set_bit;
1102 ct->chip.irq_unmask = irq_gc_mask_clr_bit; 991 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
1103 ct->chip.irq_set_type = gpio_irq_type; 992 ct->chip.irq_set_type = gpio_irq_type;
1104 /* REVISIT: assuming only 16xx supports MPUIO wake events */ 993
1105 if (cpu_is_omap16xx()) 994 if (bank->regs->wkup_en)
1106 ct->chip.irq_set_wake = gpio_wake_enable, 995 ct->chip.irq_set_wake = gpio_wake_enable,
1107 996
1108 ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride; 997 ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride;
@@ -1115,7 +1004,6 @@ static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
1115 int j; 1004 int j;
1116 static int gpio; 1005 static int gpio;
1117 1006
1118 bank->mod_usage = 0;
1119 /* 1007 /*
1120 * REVISIT eventually switch from OMAP-specific gpio structs 1008 * REVISIT eventually switch from OMAP-specific gpio structs
1121 * over to the generic ones 1009 * over to the generic ones
@@ -1128,11 +1016,10 @@ static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
1128 bank->chip.set_debounce = gpio_debounce; 1016 bank->chip.set_debounce = gpio_debounce;
1129 bank->chip.set = gpio_set; 1017 bank->chip.set = gpio_set;
1130 bank->chip.to_irq = gpio_2irq; 1018 bank->chip.to_irq = gpio_2irq;
1131 if (bank_is_mpuio(bank)) { 1019 if (bank->is_mpuio) {
1132 bank->chip.label = "mpuio"; 1020 bank->chip.label = "mpuio";
1133#ifdef CONFIG_ARCH_OMAP16XX 1021 if (bank->regs->wkup_en)
1134 bank->chip.dev = &omap_mpuio_device.dev; 1022 bank->chip.dev = &omap_mpuio_device.dev;
1135#endif
1136 bank->chip.base = OMAP_MPUIO(0); 1023 bank->chip.base = OMAP_MPUIO(0);
1137 } else { 1024 } else {
1138 bank->chip.label = "gpio"; 1025 bank->chip.label = "gpio";
@@ -1147,7 +1034,7 @@ static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
1147 j < bank->virtual_irq_start + bank->width; j++) { 1034 j < bank->virtual_irq_start + bank->width; j++) {
1148 irq_set_lockdep_class(j, &gpio_lock_class); 1035 irq_set_lockdep_class(j, &gpio_lock_class);
1149 irq_set_chip_data(j, bank); 1036 irq_set_chip_data(j, bank);
1150 if (bank_is_mpuio(bank)) { 1037 if (bank->is_mpuio) {
1151 omap_mpuio_alloc_gc(bank, j, bank->width); 1038 omap_mpuio_alloc_gc(bank, j, bank->width);
1152 } else { 1039 } else {
1153 irq_set_chip(j, &gpio_irq_chip); 1040 irq_set_chip(j, &gpio_irq_chip);
@@ -1161,42 +1048,44 @@ static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
1161 1048
1162static int __devinit omap_gpio_probe(struct platform_device *pdev) 1049static int __devinit omap_gpio_probe(struct platform_device *pdev)
1163{ 1050{
1164 static int gpio_init_done;
1165 struct omap_gpio_platform_data *pdata; 1051 struct omap_gpio_platform_data *pdata;
1166 struct resource *res; 1052 struct resource *res;
1167 int id;
1168 struct gpio_bank *bank; 1053 struct gpio_bank *bank;
1054 int ret = 0;
1169 1055
1170 if (!pdev->dev.platform_data) 1056 if (!pdev->dev.platform_data) {
1171 return -EINVAL; 1057 ret = -EINVAL;
1172 1058 goto err_exit;
1173 pdata = pdev->dev.platform_data;
1174
1175 if (!gpio_init_done) {
1176 int ret;
1177
1178 ret = init_gpio_info(pdev);
1179 if (ret)
1180 return ret;
1181 } 1059 }
1182 1060
1183 id = pdev->id; 1061 bank = kzalloc(sizeof(struct gpio_bank), GFP_KERNEL);
1184 bank = &gpio_bank[id]; 1062 if (!bank) {
1063 dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n");
1064 ret = -ENOMEM;
1065 goto err_exit;
1066 }
1185 1067
1186 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1068 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1187 if (unlikely(!res)) { 1069 if (unlikely(!res)) {
1188 dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n", id); 1070 dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n",
1189 return -ENODEV; 1071 pdev->id);
1072 ret = -ENODEV;
1073 goto err_free;
1190 } 1074 }
1191 1075
1192 bank->irq = res->start; 1076 bank->irq = res->start;
1077 bank->id = pdev->id;
1078
1079 pdata = pdev->dev.platform_data;
1193 bank->virtual_irq_start = pdata->virtual_irq_start; 1080 bank->virtual_irq_start = pdata->virtual_irq_start;
1194 bank->method = pdata->bank_type;
1195 bank->dev = &pdev->dev; 1081 bank->dev = &pdev->dev;
1196 bank->dbck_flag = pdata->dbck_flag; 1082 bank->dbck_flag = pdata->dbck_flag;
1197 bank->stride = pdata->bank_stride; 1083 bank->stride = pdata->bank_stride;
1198 bank->width = pdata->bank_width; 1084 bank->width = pdata->bank_width;
1199 1085 bank->is_mpuio = pdata->is_mpuio;
1086 bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
1087 bank->loses_context = pdata->loses_context;
1088 bank->get_context_loss_count = pdata->get_context_loss_count;
1200 bank->regs = pdata->regs; 1089 bank->regs = pdata->regs;
1201 1090
1202 if (bank->regs->set_dataout && bank->regs->clr_dataout) 1091 if (bank->regs->set_dataout && bank->regs->clr_dataout)
@@ -1209,369 +1098,310 @@ static int __devinit omap_gpio_probe(struct platform_device *pdev)
1209 /* Static mapping, never released */ 1098 /* Static mapping, never released */
1210 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1099 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1211 if (unlikely(!res)) { 1100 if (unlikely(!res)) {
1212 dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n", id); 1101 dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n",
1213 return -ENODEV; 1102 pdev->id);
1103 ret = -ENODEV;
1104 goto err_free;
1214 } 1105 }
1215 1106
1216 bank->base = ioremap(res->start, resource_size(res)); 1107 bank->base = ioremap(res->start, resource_size(res));
1217 if (!bank->base) { 1108 if (!bank->base) {
1218 dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n", id); 1109 dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n",
1219 return -ENOMEM; 1110 pdev->id);
1111 ret = -ENOMEM;
1112 goto err_free;
1220 } 1113 }
1221 1114
1115 platform_set_drvdata(pdev, bank);
1116
1222 pm_runtime_enable(bank->dev); 1117 pm_runtime_enable(bank->dev);
1118 pm_runtime_irq_safe(bank->dev);
1223 pm_runtime_get_sync(bank->dev); 1119 pm_runtime_get_sync(bank->dev);
1224 1120
1225 omap_gpio_mod_init(bank, id); 1121 if (bank->is_mpuio)
1122 mpuio_init(bank);
1123
1124 omap_gpio_mod_init(bank);
1226 omap_gpio_chip_init(bank); 1125 omap_gpio_chip_init(bank);
1227 omap_gpio_show_rev(bank); 1126 omap_gpio_show_rev(bank);
1228 1127
1229 if (!gpio_init_done) 1128 pm_runtime_put(bank->dev);
1230 gpio_init_done = 1;
1231 1129
1232 return 0; 1130 list_add_tail(&bank->node, &omap_gpio_list);
1131
1132 return ret;
1133
1134err_free:
1135 kfree(bank);
1136err_exit:
1137 return ret;
1233} 1138}
1234 1139
1235#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) 1140#ifdef CONFIG_ARCH_OMAP2PLUS
1236static int omap_gpio_suspend(void) 1141
1142#if defined(CONFIG_PM_SLEEP)
1143static int omap_gpio_suspend(struct device *dev)
1237{ 1144{
1238 int i; 1145 struct platform_device *pdev = to_platform_device(dev);
1146 struct gpio_bank *bank = platform_get_drvdata(pdev);
1147 void __iomem *base = bank->base;
1148 void __iomem *wakeup_enable;
1149 unsigned long flags;
1239 1150
1240 if (!cpu_class_is_omap2() && !cpu_is_omap16xx()) 1151 if (!bank->mod_usage || !bank->loses_context)
1241 return 0; 1152 return 0;
1242 1153
1243 for (i = 0; i < gpio_bank_count; i++) { 1154 if (!bank->regs->wkup_en || !bank->suspend_wakeup)
1244 struct gpio_bank *bank = &gpio_bank[i]; 1155 return 0;
1245 void __iomem *wake_status;
1246 void __iomem *wake_clear;
1247 void __iomem *wake_set;
1248 unsigned long flags;
1249
1250 switch (bank->method) {
1251#ifdef CONFIG_ARCH_OMAP16XX
1252 case METHOD_GPIO_1610:
1253 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1254 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1255 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1256 break;
1257#endif
1258#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1259 case METHOD_GPIO_24XX:
1260 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
1261 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1262 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1263 break;
1264#endif
1265#ifdef CONFIG_ARCH_OMAP4
1266 case METHOD_GPIO_44XX:
1267 wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
1268 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1269 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1270 break;
1271#endif
1272 default:
1273 continue;
1274 }
1275 1156
1276 spin_lock_irqsave(&bank->lock, flags); 1157 wakeup_enable = bank->base + bank->regs->wkup_en;
1277 bank->saved_wakeup = __raw_readl(wake_status); 1158
1278 __raw_writel(0xffffffff, wake_clear); 1159 spin_lock_irqsave(&bank->lock, flags);
1279 __raw_writel(bank->suspend_wakeup, wake_set); 1160 bank->saved_wakeup = __raw_readl(wakeup_enable);
1280 spin_unlock_irqrestore(&bank->lock, flags); 1161 _gpio_rmw(base, bank->regs->wkup_en, 0xffffffff, 0);
1281 } 1162 _gpio_rmw(base, bank->regs->wkup_en, bank->suspend_wakeup, 1);
1163 spin_unlock_irqrestore(&bank->lock, flags);
1282 1164
1283 return 0; 1165 return 0;
1284} 1166}
1285 1167
1286static void omap_gpio_resume(void) 1168static int omap_gpio_resume(struct device *dev)
1287{ 1169{
1288 int i; 1170 struct platform_device *pdev = to_platform_device(dev);
1171 struct gpio_bank *bank = platform_get_drvdata(pdev);
1172 void __iomem *base = bank->base;
1173 unsigned long flags;
1289 1174
1290 if (!cpu_class_is_omap2() && !cpu_is_omap16xx()) 1175 if (!bank->mod_usage || !bank->loses_context)
1291 return; 1176 return 0;
1292 1177
1293 for (i = 0; i < gpio_bank_count; i++) { 1178 if (!bank->regs->wkup_en || !bank->saved_wakeup)
1294 struct gpio_bank *bank = &gpio_bank[i]; 1179 return 0;
1295 void __iomem *wake_clear;
1296 void __iomem *wake_set;
1297 unsigned long flags;
1298
1299 switch (bank->method) {
1300#ifdef CONFIG_ARCH_OMAP16XX
1301 case METHOD_GPIO_1610:
1302 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1303 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1304 break;
1305#endif
1306#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1307 case METHOD_GPIO_24XX:
1308 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1309 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1310 break;
1311#endif
1312#ifdef CONFIG_ARCH_OMAP4
1313 case METHOD_GPIO_44XX:
1314 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1315 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1316 break;
1317#endif
1318 default:
1319 continue;
1320 }
1321 1180
1322 spin_lock_irqsave(&bank->lock, flags); 1181 spin_lock_irqsave(&bank->lock, flags);
1323 __raw_writel(0xffffffff, wake_clear); 1182 _gpio_rmw(base, bank->regs->wkup_en, 0xffffffff, 0);
1324 __raw_writel(bank->saved_wakeup, wake_set); 1183 _gpio_rmw(base, bank->regs->wkup_en, bank->saved_wakeup, 1);
1325 spin_unlock_irqrestore(&bank->lock, flags); 1184 spin_unlock_irqrestore(&bank->lock, flags);
1326 }
1327}
1328 1185
1329static struct syscore_ops omap_gpio_syscore_ops = { 1186 return 0;
1330 .suspend = omap_gpio_suspend, 1187}
1331 .resume = omap_gpio_resume, 1188#endif /* CONFIG_PM_SLEEP */
1332};
1333 1189
1334#endif 1190#if defined(CONFIG_PM_RUNTIME)
1191static void omap_gpio_restore_context(struct gpio_bank *bank);
1335 1192
1336#ifdef CONFIG_ARCH_OMAP2PLUS 1193static int omap_gpio_runtime_suspend(struct device *dev)
1194{
1195 struct platform_device *pdev = to_platform_device(dev);
1196 struct gpio_bank *bank = platform_get_drvdata(pdev);
1197 u32 l1 = 0, l2 = 0;
1198 unsigned long flags;
1337 1199
1338static int workaround_enabled; 1200 spin_lock_irqsave(&bank->lock, flags);
1201 if (bank->power_mode != OFF_MODE) {
1202 bank->power_mode = 0;
1203 goto update_gpio_context_count;
1204 }
1205 /*
1206 * If going to OFF, remove triggering for all
1207 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1208 * generated. See OMAP2420 Errata item 1.101.
1209 */
1210 if (!(bank->enabled_non_wakeup_gpios))
1211 goto update_gpio_context_count;
1339 1212
1340void omap2_gpio_prepare_for_idle(int off_mode) 1213 bank->saved_datain = __raw_readl(bank->base +
1341{ 1214 bank->regs->datain);
1342 int i, c = 0; 1215 l1 = __raw_readl(bank->base + bank->regs->fallingdetect);
1343 int min = 0; 1216 l2 = __raw_readl(bank->base + bank->regs->risingdetect);
1344 1217
1345 if (cpu_is_omap34xx()) 1218 bank->saved_fallingdetect = l1;
1346 min = 1; 1219 bank->saved_risingdetect = l2;
1220 l1 &= ~bank->enabled_non_wakeup_gpios;
1221 l2 &= ~bank->enabled_non_wakeup_gpios;
1347 1222
1348 for (i = min; i < gpio_bank_count; i++) { 1223 __raw_writel(l1, bank->base + bank->regs->fallingdetect);
1349 struct gpio_bank *bank = &gpio_bank[i]; 1224 __raw_writel(l2, bank->base + bank->regs->risingdetect);
1350 u32 l1 = 0, l2 = 0;
1351 int j;
1352 1225
1353 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++) 1226 bank->workaround_enabled = true;
1354 clk_disable(bank->dbck);
1355 1227
1356 if (!off_mode) 1228update_gpio_context_count:
1357 continue; 1229 if (bank->get_context_loss_count)
1230 bank->context_loss_count =
1231 bank->get_context_loss_count(bank->dev);
1358 1232
1359 /* If going to OFF, remove triggering for all 1233 _gpio_dbck_disable(bank);
1360 * non-wakeup GPIOs. Otherwise spurious IRQs will be 1234 spin_unlock_irqrestore(&bank->lock, flags);
1361 * generated. See OMAP2420 Errata item 1.101. */
1362 if (!(bank->enabled_non_wakeup_gpios))
1363 continue;
1364 1235
1365 if (cpu_is_omap24xx() || cpu_is_omap34xx()) { 1236 return 0;
1366 bank->saved_datain = __raw_readl(bank->base + 1237}
1367 OMAP24XX_GPIO_DATAIN);
1368 l1 = __raw_readl(bank->base +
1369 OMAP24XX_GPIO_FALLINGDETECT);
1370 l2 = __raw_readl(bank->base +
1371 OMAP24XX_GPIO_RISINGDETECT);
1372 }
1373 1238
1374 if (cpu_is_omap44xx()) { 1239static int omap_gpio_runtime_resume(struct device *dev)
1375 bank->saved_datain = __raw_readl(bank->base + 1240{
1376 OMAP4_GPIO_DATAIN); 1241 struct platform_device *pdev = to_platform_device(dev);
1377 l1 = __raw_readl(bank->base + 1242 struct gpio_bank *bank = platform_get_drvdata(pdev);
1378 OMAP4_GPIO_FALLINGDETECT); 1243 int context_lost_cnt_after;
1379 l2 = __raw_readl(bank->base + 1244 u32 l = 0, gen, gen0, gen1;
1380 OMAP4_GPIO_RISINGDETECT); 1245 unsigned long flags;
1381 }
1382 1246
1383 bank->saved_fallingdetect = l1; 1247 spin_lock_irqsave(&bank->lock, flags);
1384 bank->saved_risingdetect = l2; 1248 _gpio_dbck_enable(bank);
1385 l1 &= ~bank->enabled_non_wakeup_gpios; 1249 if (!bank->enabled_non_wakeup_gpios || !bank->workaround_enabled) {
1386 l2 &= ~bank->enabled_non_wakeup_gpios; 1250 spin_unlock_irqrestore(&bank->lock, flags);
1251 return 0;
1252 }
1387 1253
1388 if (cpu_is_omap24xx() || cpu_is_omap34xx()) { 1254 if (bank->get_context_loss_count) {
1389 __raw_writel(l1, bank->base + 1255 context_lost_cnt_after =
1390 OMAP24XX_GPIO_FALLINGDETECT); 1256 bank->get_context_loss_count(bank->dev);
1391 __raw_writel(l2, bank->base + 1257 if (context_lost_cnt_after != bank->context_loss_count ||
1392 OMAP24XX_GPIO_RISINGDETECT); 1258 !context_lost_cnt_after) {
1259 omap_gpio_restore_context(bank);
1260 } else {
1261 spin_unlock_irqrestore(&bank->lock, flags);
1262 return 0;
1393 } 1263 }
1264 }
1394 1265
1395 if (cpu_is_omap44xx()) { 1266 __raw_writel(bank->saved_fallingdetect,
1396 __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT); 1267 bank->base + bank->regs->fallingdetect);
1397 __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT); 1268 __raw_writel(bank->saved_risingdetect,
1398 } 1269 bank->base + bank->regs->risingdetect);
1270 l = __raw_readl(bank->base + bank->regs->datain);
1399 1271
1400 c++; 1272 /*
1401 } 1273 * Check if any of the non-wakeup interrupt GPIOs have changed
1402 if (!c) { 1274 * state. If so, generate an IRQ by software. This is
1403 workaround_enabled = 0; 1275 * horribly racy, but it's the best we can do to work around
1404 return; 1276 * this silicon bug.
1405 } 1277 */
1406 workaround_enabled = 1; 1278 l ^= bank->saved_datain;
1407} 1279 l &= bank->enabled_non_wakeup_gpios;
1408 1280
1409void omap2_gpio_resume_after_idle(void) 1281 /*
1410{ 1282 * No need to generate IRQs for the rising edge for gpio IRQs
1411 int i; 1283 * configured with falling edge only; and vice versa.
1412 int min = 0; 1284 */
1285 gen0 = l & bank->saved_fallingdetect;
1286 gen0 &= bank->saved_datain;
1413 1287
1414 if (cpu_is_omap34xx()) 1288 gen1 = l & bank->saved_risingdetect;
1415 min = 1; 1289 gen1 &= ~(bank->saved_datain);
1416 for (i = min; i < gpio_bank_count; i++) {
1417 struct gpio_bank *bank = &gpio_bank[i];
1418 u32 l = 0, gen, gen0, gen1;
1419 int j;
1420 1290
1421 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++) 1291 /* FIXME: Consider GPIO IRQs with level detections properly! */
1422 clk_enable(bank->dbck); 1292 gen = l & (~(bank->saved_fallingdetect) & ~(bank->saved_risingdetect));
1293 /* Consider all GPIO IRQs needed to be updated */
1294 gen |= gen0 | gen1;
1423 1295
1424 if (!workaround_enabled) 1296 if (gen) {
1425 continue; 1297 u32 old0, old1;
1426 1298
1427 if (!(bank->enabled_non_wakeup_gpios)) 1299 old0 = __raw_readl(bank->base + bank->regs->leveldetect0);
1428 continue; 1300 old1 = __raw_readl(bank->base + bank->regs->leveldetect1);
1429 1301
1430 if (cpu_is_omap24xx() || cpu_is_omap34xx()) { 1302 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1431 __raw_writel(bank->saved_fallingdetect, 1303 __raw_writel(old0 | gen, bank->base +
1432 bank->base + OMAP24XX_GPIO_FALLINGDETECT); 1304 bank->regs->leveldetect0);
1433 __raw_writel(bank->saved_risingdetect, 1305 __raw_writel(old1 | gen, bank->base +
1434 bank->base + OMAP24XX_GPIO_RISINGDETECT); 1306 bank->regs->leveldetect1);
1435 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1436 } 1307 }
1437 1308
1438 if (cpu_is_omap44xx()) { 1309 if (cpu_is_omap44xx()) {
1439 __raw_writel(bank->saved_fallingdetect, 1310 __raw_writel(old0 | l, bank->base +
1440 bank->base + OMAP4_GPIO_FALLINGDETECT); 1311 bank->regs->leveldetect0);
1441 __raw_writel(bank->saved_risingdetect, 1312 __raw_writel(old1 | l, bank->base +
1442 bank->base + OMAP4_GPIO_RISINGDETECT); 1313 bank->regs->leveldetect1);
1443 l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
1444 }
1445
1446 /* Check if any of the non-wakeup interrupt GPIOs have changed
1447 * state. If so, generate an IRQ by software. This is
1448 * horribly racy, but it's the best we can do to work around
1449 * this silicon bug. */
1450 l ^= bank->saved_datain;
1451 l &= bank->enabled_non_wakeup_gpios;
1452
1453 /*
1454 * No need to generate IRQs for the rising edge for gpio IRQs
1455 * configured with falling edge only; and vice versa.
1456 */
1457 gen0 = l & bank->saved_fallingdetect;
1458 gen0 &= bank->saved_datain;
1459
1460 gen1 = l & bank->saved_risingdetect;
1461 gen1 &= ~(bank->saved_datain);
1462
1463 /* FIXME: Consider GPIO IRQs with level detections properly! */
1464 gen = l & (~(bank->saved_fallingdetect) &
1465 ~(bank->saved_risingdetect));
1466 /* Consider all GPIO IRQs needed to be updated */
1467 gen |= gen0 | gen1;
1468
1469 if (gen) {
1470 u32 old0, old1;
1471
1472 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1473 old0 = __raw_readl(bank->base +
1474 OMAP24XX_GPIO_LEVELDETECT0);
1475 old1 = __raw_readl(bank->base +
1476 OMAP24XX_GPIO_LEVELDETECT1);
1477 __raw_writel(old0 | gen, bank->base +
1478 OMAP24XX_GPIO_LEVELDETECT0);
1479 __raw_writel(old1 | gen, bank->base +
1480 OMAP24XX_GPIO_LEVELDETECT1);
1481 __raw_writel(old0, bank->base +
1482 OMAP24XX_GPIO_LEVELDETECT0);
1483 __raw_writel(old1, bank->base +
1484 OMAP24XX_GPIO_LEVELDETECT1);
1485 }
1486
1487 if (cpu_is_omap44xx()) {
1488 old0 = __raw_readl(bank->base +
1489 OMAP4_GPIO_LEVELDETECT0);
1490 old1 = __raw_readl(bank->base +
1491 OMAP4_GPIO_LEVELDETECT1);
1492 __raw_writel(old0 | l, bank->base +
1493 OMAP4_GPIO_LEVELDETECT0);
1494 __raw_writel(old1 | l, bank->base +
1495 OMAP4_GPIO_LEVELDETECT1);
1496 __raw_writel(old0, bank->base +
1497 OMAP4_GPIO_LEVELDETECT0);
1498 __raw_writel(old1, bank->base +
1499 OMAP4_GPIO_LEVELDETECT1);
1500 }
1501 } 1314 }
1315 __raw_writel(old0, bank->base + bank->regs->leveldetect0);
1316 __raw_writel(old1, bank->base + bank->regs->leveldetect1);
1502 } 1317 }
1503 1318
1319 bank->workaround_enabled = false;
1320 spin_unlock_irqrestore(&bank->lock, flags);
1321
1322 return 0;
1504} 1323}
1324#endif /* CONFIG_PM_RUNTIME */
1505 1325
1506#endif 1326void omap2_gpio_prepare_for_idle(int pwr_mode)
1327{
1328 struct gpio_bank *bank;
1329
1330 list_for_each_entry(bank, &omap_gpio_list, node) {
1331 if (!bank->mod_usage || !bank->loses_context)
1332 continue;
1333
1334 bank->power_mode = pwr_mode;
1335
1336 pm_runtime_put_sync_suspend(bank->dev);
1337 }
1338}
1507 1339
1508#ifdef CONFIG_ARCH_OMAP3 1340void omap2_gpio_resume_after_idle(void)
1509/* save the registers of bank 2-6 */
1510void omap_gpio_save_context(void)
1511{ 1341{
1512 int i; 1342 struct gpio_bank *bank;
1513 1343
1514 /* saving banks from 2-6 only since GPIO1 is in WKUP */ 1344 list_for_each_entry(bank, &omap_gpio_list, node) {
1515 for (i = 1; i < gpio_bank_count; i++) { 1345 if (!bank->mod_usage || !bank->loses_context)
1516 struct gpio_bank *bank = &gpio_bank[i]; 1346 continue;
1517 gpio_context[i].irqenable1 = 1347
1518 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1); 1348 pm_runtime_get_sync(bank->dev);
1519 gpio_context[i].irqenable2 =
1520 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
1521 gpio_context[i].wake_en =
1522 __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
1523 gpio_context[i].ctrl =
1524 __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
1525 gpio_context[i].oe =
1526 __raw_readl(bank->base + OMAP24XX_GPIO_OE);
1527 gpio_context[i].leveldetect0 =
1528 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1529 gpio_context[i].leveldetect1 =
1530 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1531 gpio_context[i].risingdetect =
1532 __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1533 gpio_context[i].fallingdetect =
1534 __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1535 gpio_context[i].dataout =
1536 __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
1537 } 1349 }
1538} 1350}
1539 1351
1540/* restore the required registers of bank 2-6 */ 1352#if defined(CONFIG_PM_RUNTIME)
1541void omap_gpio_restore_context(void) 1353static void omap_gpio_restore_context(struct gpio_bank *bank)
1542{ 1354{
1543 int i; 1355 __raw_writel(bank->context.wake_en,
1544 1356 bank->base + bank->regs->wkup_en);
1545 for (i = 1; i < gpio_bank_count; i++) { 1357 __raw_writel(bank->context.ctrl, bank->base + bank->regs->ctrl);
1546 struct gpio_bank *bank = &gpio_bank[i]; 1358 __raw_writel(bank->context.leveldetect0,
1547 __raw_writel(gpio_context[i].irqenable1, 1359 bank->base + bank->regs->leveldetect0);
1548 bank->base + OMAP24XX_GPIO_IRQENABLE1); 1360 __raw_writel(bank->context.leveldetect1,
1549 __raw_writel(gpio_context[i].irqenable2, 1361 bank->base + bank->regs->leveldetect1);
1550 bank->base + OMAP24XX_GPIO_IRQENABLE2); 1362 __raw_writel(bank->context.risingdetect,
1551 __raw_writel(gpio_context[i].wake_en, 1363 bank->base + bank->regs->risingdetect);
1552 bank->base + OMAP24XX_GPIO_WAKE_EN); 1364 __raw_writel(bank->context.fallingdetect,
1553 __raw_writel(gpio_context[i].ctrl, 1365 bank->base + bank->regs->fallingdetect);
1554 bank->base + OMAP24XX_GPIO_CTRL); 1366 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1555 __raw_writel(gpio_context[i].oe, 1367 __raw_writel(bank->context.dataout,
1556 bank->base + OMAP24XX_GPIO_OE); 1368 bank->base + bank->regs->set_dataout);
1557 __raw_writel(gpio_context[i].leveldetect0, 1369 else
1558 bank->base + OMAP24XX_GPIO_LEVELDETECT0); 1370 __raw_writel(bank->context.dataout,
1559 __raw_writel(gpio_context[i].leveldetect1, 1371 bank->base + bank->regs->dataout);
1560 bank->base + OMAP24XX_GPIO_LEVELDETECT1); 1372 __raw_writel(bank->context.oe, bank->base + bank->regs->direction);
1561 __raw_writel(gpio_context[i].risingdetect, 1373
1562 bank->base + OMAP24XX_GPIO_RISINGDETECT); 1374 if (bank->dbck_enable_mask) {
1563 __raw_writel(gpio_context[i].fallingdetect, 1375 __raw_writel(bank->context.debounce, bank->base +
1564 bank->base + OMAP24XX_GPIO_FALLINGDETECT); 1376 bank->regs->debounce);
1565 __raw_writel(gpio_context[i].dataout, 1377 __raw_writel(bank->context.debounce_en,
1566 bank->base + OMAP24XX_GPIO_DATAOUT); 1378 bank->base + bank->regs->debounce_en);
1567 } 1379 }
1380
1381 __raw_writel(bank->context.irqenable1,
1382 bank->base + bank->regs->irqenable);
1383 __raw_writel(bank->context.irqenable2,
1384 bank->base + bank->regs->irqenable2);
1568} 1385}
1386#endif /* CONFIG_PM_RUNTIME */
1387#else
1388#define omap_gpio_suspend NULL
1389#define omap_gpio_resume NULL
1390#define omap_gpio_runtime_suspend NULL
1391#define omap_gpio_runtime_resume NULL
1569#endif 1392#endif
1570 1393
1394static const struct dev_pm_ops gpio_pm_ops = {
1395 SET_SYSTEM_SLEEP_PM_OPS(omap_gpio_suspend, omap_gpio_resume)
1396 SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
1397 NULL)
1398};
1399
1571static struct platform_driver omap_gpio_driver = { 1400static struct platform_driver omap_gpio_driver = {
1572 .probe = omap_gpio_probe, 1401 .probe = omap_gpio_probe,
1573 .driver = { 1402 .driver = {
1574 .name = "omap_gpio", 1403 .name = "omap_gpio",
1404 .pm = &gpio_pm_ops,
1575 }, 1405 },
1576}; 1406};
1577 1407
@@ -1585,17 +1415,3 @@ static int __init omap_gpio_drv_reg(void)
1585 return platform_driver_register(&omap_gpio_driver); 1415 return platform_driver_register(&omap_gpio_driver);
1586} 1416}
1587postcore_initcall(omap_gpio_drv_reg); 1417postcore_initcall(omap_gpio_drv_reg);
1588
1589static int __init omap_gpio_sysinit(void)
1590{
1591 mpuio_init();
1592
1593#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
1594 if (cpu_is_omap16xx() || cpu_class_is_omap2())
1595 register_syscore_ops(&omap_gpio_syscore_ops);
1596#endif
1597
1598 return 0;
1599}
1600
1601arch_initcall(omap_gpio_sysinit);
diff --git a/drivers/gpio/gpio-pl061.c b/drivers/gpio/gpio-pl061.c
index 77c9cc70fa77..b4b5da4fd2cc 100644
--- a/drivers/gpio/gpio-pl061.c
+++ b/drivers/gpio/gpio-pl061.c
@@ -352,7 +352,12 @@ static int pl061_resume(struct device *dev)
352 return 0; 352 return 0;
353} 353}
354 354
355static SIMPLE_DEV_PM_OPS(pl061_dev_pm_ops, pl061_suspend, pl061_resume); 355static const struct dev_pm_ops pl061_dev_pm_ops = {
356 .suspend = pl061_suspend,
357 .resume = pl061_resume,
358 .freeze = pl061_suspend,
359 .restore = pl061_resume,
360};
356#endif 361#endif
357 362
358static struct amba_id pl061_ids[] = { 363static struct amba_id pl061_ids[] = {
diff --git a/drivers/gpio/gpio-sodaville.c b/drivers/gpio/gpio-sodaville.c
new file mode 100644
index 000000000000..9ba15d31d242
--- /dev/null
+++ b/drivers/gpio/gpio-sodaville.c
@@ -0,0 +1,302 @@
1/*
2 * GPIO interface for Intel Sodaville SoCs.
3 *
4 * Copyright (c) 2010, 2011 Intel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License 2 as published
8 * by the Free Software Foundation.
9 *
10 */
11
12#include <linux/errno.h>
13#include <linux/gpio.h>
14#include <linux/init.h>
15#include <linux/io.h>
16#include <linux/irq.h>
17#include <linux/interrupt.h>
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/pci.h>
21#include <linux/platform_device.h>
22#include <linux/of_irq.h>
23#include <linux/basic_mmio_gpio.h>
24
25#define DRV_NAME "sdv_gpio"
26#define SDV_NUM_PUB_GPIOS 12
27#define PCI_DEVICE_ID_SDV_GPIO 0x2e67
28#define GPIO_BAR 0
29
30#define GPOUTR 0x00
31#define GPOER 0x04
32#define GPINR 0x08
33
34#define GPSTR 0x0c
35#define GPIT1R0 0x10
36#define GPIO_INT 0x14
37#define GPIT1R1 0x18
38
39#define GPMUXCTL 0x1c
40
41struct sdv_gpio_chip_data {
42 int irq_base;
43 void __iomem *gpio_pub_base;
44 struct irq_domain id;
45 struct irq_chip_generic *gc;
46 struct bgpio_chip bgpio;
47};
48
49static int sdv_gpio_pub_set_type(struct irq_data *d, unsigned int type)
50{
51 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
52 struct sdv_gpio_chip_data *sd = gc->private;
53 void __iomem *type_reg;
54 u32 irq_offs = d->irq - sd->irq_base;
55 u32 reg;
56
57 if (irq_offs < 8)
58 type_reg = sd->gpio_pub_base + GPIT1R0;
59 else
60 type_reg = sd->gpio_pub_base + GPIT1R1;
61
62 reg = readl(type_reg);
63
64 switch (type) {
65 case IRQ_TYPE_LEVEL_HIGH:
66 reg &= ~BIT(4 * (irq_offs % 8));
67 break;
68
69 case IRQ_TYPE_LEVEL_LOW:
70 reg |= BIT(4 * (irq_offs % 8));
71 break;
72
73 default:
74 return -EINVAL;
75 }
76
77 writel(reg, type_reg);
78 return 0;
79}
80
81static irqreturn_t sdv_gpio_pub_irq_handler(int irq, void *data)
82{
83 struct sdv_gpio_chip_data *sd = data;
84 u32 irq_stat = readl(sd->gpio_pub_base + GPSTR);
85
86 irq_stat &= readl(sd->gpio_pub_base + GPIO_INT);
87 if (!irq_stat)
88 return IRQ_NONE;
89
90 while (irq_stat) {
91 u32 irq_bit = __fls(irq_stat);
92
93 irq_stat &= ~BIT(irq_bit);
94 generic_handle_irq(sd->irq_base + irq_bit);
95 }
96
97 return IRQ_HANDLED;
98}
99
100static int sdv_xlate(struct irq_domain *h, struct device_node *node,
101 const u32 *intspec, u32 intsize, irq_hw_number_t *out_hwirq,
102 u32 *out_type)
103{
104 u32 line, type;
105
106 if (node != h->of_node)
107 return -EINVAL;
108
109 if (intsize < 2)
110 return -EINVAL;
111
112 line = *intspec;
113 *out_hwirq = line;
114
115 intspec++;
116 type = *intspec;
117
118 switch (type) {
119 case IRQ_TYPE_LEVEL_LOW:
120 case IRQ_TYPE_LEVEL_HIGH:
121 *out_type = type;
122 break;
123 default:
124 return -EINVAL;
125 }
126 return 0;
127}
128
129static struct irq_domain_ops irq_domain_sdv_ops = {
130 .dt_translate = sdv_xlate,
131};
132
133static __devinit int sdv_register_irqsupport(struct sdv_gpio_chip_data *sd,
134 struct pci_dev *pdev)
135{
136 struct irq_chip_type *ct;
137 int ret;
138
139 sd->irq_base = irq_alloc_descs(-1, 0, SDV_NUM_PUB_GPIOS, -1);
140 if (sd->irq_base < 0)
141 return sd->irq_base;
142
143 /* mask + ACK all interrupt sources */
144 writel(0, sd->gpio_pub_base + GPIO_INT);
145 writel((1 << 11) - 1, sd->gpio_pub_base + GPSTR);
146
147 ret = request_irq(pdev->irq, sdv_gpio_pub_irq_handler, IRQF_SHARED,
148 "sdv_gpio", sd);
149 if (ret)
150 goto out_free_desc;
151
152 sd->id.irq_base = sd->irq_base;
153 sd->id.of_node = of_node_get(pdev->dev.of_node);
154 sd->id.ops = &irq_domain_sdv_ops;
155
156 /*
157 * This gpio irq controller latches level irqs. Testing shows that if
158 * we unmask & ACK the IRQ before the source of the interrupt is gone
159 * then the interrupt is active again.
160 */
161 sd->gc = irq_alloc_generic_chip("sdv-gpio", 1, sd->irq_base,
162 sd->gpio_pub_base, handle_fasteoi_irq);
163 if (!sd->gc) {
164 ret = -ENOMEM;
165 goto out_free_irq;
166 }
167
168 sd->gc->private = sd;
169 ct = sd->gc->chip_types;
170 ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
171 ct->regs.eoi = GPSTR;
172 ct->regs.mask = GPIO_INT;
173 ct->chip.irq_mask = irq_gc_mask_clr_bit;
174 ct->chip.irq_unmask = irq_gc_mask_set_bit;
175 ct->chip.irq_eoi = irq_gc_eoi;
176 ct->chip.irq_set_type = sdv_gpio_pub_set_type;
177
178 irq_setup_generic_chip(sd->gc, IRQ_MSK(SDV_NUM_PUB_GPIOS),
179 IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST,
180 IRQ_LEVEL | IRQ_NOPROBE);
181
182 irq_domain_add(&sd->id);
183 return 0;
184out_free_irq:
185 free_irq(pdev->irq, sd);
186out_free_desc:
187 irq_free_descs(sd->irq_base, SDV_NUM_PUB_GPIOS);
188 return ret;
189}
190
191static int __devinit sdv_gpio_probe(struct pci_dev *pdev,
192 const struct pci_device_id *pci_id)
193{
194 struct sdv_gpio_chip_data *sd;
195 unsigned long addr;
196 const void *prop;
197 int len;
198 int ret;
199 u32 mux_val;
200
201 sd = kzalloc(sizeof(struct sdv_gpio_chip_data), GFP_KERNEL);
202 if (!sd)
203 return -ENOMEM;
204 ret = pci_enable_device(pdev);
205 if (ret) {
206 dev_err(&pdev->dev, "can't enable device.\n");
207 goto done;
208 }
209
210 ret = pci_request_region(pdev, GPIO_BAR, DRV_NAME);
211 if (ret) {
212 dev_err(&pdev->dev, "can't alloc PCI BAR #%d\n", GPIO_BAR);
213 goto disable_pci;
214 }
215
216 addr = pci_resource_start(pdev, GPIO_BAR);
217 if (!addr)
218 goto release_reg;
219 sd->gpio_pub_base = ioremap(addr, pci_resource_len(pdev, GPIO_BAR));
220
221 prop = of_get_property(pdev->dev.of_node, "intel,muxctl", &len);
222 if (prop && len == 4) {
223 mux_val = of_read_number(prop, 1);
224 writel(mux_val, sd->gpio_pub_base + GPMUXCTL);
225 }
226
227 ret = bgpio_init(&sd->bgpio, &pdev->dev, 4,
228 sd->gpio_pub_base + GPINR, sd->gpio_pub_base + GPOUTR,
229 NULL, sd->gpio_pub_base + GPOER, NULL, false);
230 if (ret)
231 goto unmap;
232 sd->bgpio.gc.ngpio = SDV_NUM_PUB_GPIOS;
233
234 ret = gpiochip_add(&sd->bgpio.gc);
235 if (ret < 0) {
236 dev_err(&pdev->dev, "gpiochip_add() failed.\n");
237 goto unmap;
238 }
239
240 ret = sdv_register_irqsupport(sd, pdev);
241 if (ret)
242 goto unmap;
243
244 pci_set_drvdata(pdev, sd);
245 dev_info(&pdev->dev, "Sodaville GPIO driver registered.\n");
246 return 0;
247
248unmap:
249 iounmap(sd->gpio_pub_base);
250release_reg:
251 pci_release_region(pdev, GPIO_BAR);
252disable_pci:
253 pci_disable_device(pdev);
254done:
255 kfree(sd);
256 return ret;
257}
258
259static void sdv_gpio_remove(struct pci_dev *pdev)
260{
261 struct sdv_gpio_chip_data *sd = pci_get_drvdata(pdev);
262
263 irq_domain_del(&sd->id);
264 free_irq(pdev->irq, sd);
265 irq_free_descs(sd->irq_base, SDV_NUM_PUB_GPIOS);
266
267 if (gpiochip_remove(&sd->bgpio.gc))
268 dev_err(&pdev->dev, "gpiochip_remove() failed.\n");
269
270 pci_release_region(pdev, GPIO_BAR);
271 iounmap(sd->gpio_pub_base);
272 pci_disable_device(pdev);
273 kfree(sd);
274}
275
276static struct pci_device_id sdv_gpio_pci_ids[] __devinitdata = {
277 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_SDV_GPIO) },
278 { 0, },
279};
280
281static struct pci_driver sdv_gpio_driver = {
282 .name = DRV_NAME,
283 .id_table = sdv_gpio_pci_ids,
284 .probe = sdv_gpio_probe,
285 .remove = sdv_gpio_remove,
286};
287
288static int __init sdv_gpio_init(void)
289{
290 return pci_register_driver(&sdv_gpio_driver);
291}
292module_init(sdv_gpio_init);
293
294static void __exit sdv_gpio_exit(void)
295{
296 pci_unregister_driver(&sdv_gpio_driver);
297}
298module_exit(sdv_gpio_exit);
299
300MODULE_AUTHOR("Hans J. Koch <hjk@linutronix.de>");
301MODULE_DESCRIPTION("GPIO interface for Intel Sodaville SoCs");
302MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpio/gpio-tps65910.c b/drivers/gpio/gpio-tps65910.c
index 91f45b965d1e..7eef648a3351 100644
--- a/drivers/gpio/gpio-tps65910.c
+++ b/drivers/gpio/gpio-tps65910.c
@@ -69,6 +69,7 @@ static int tps65910_gpio_input(struct gpio_chip *gc, unsigned offset)
69void tps65910_gpio_init(struct tps65910 *tps65910, int gpio_base) 69void tps65910_gpio_init(struct tps65910 *tps65910, int gpio_base)
70{ 70{
71 int ret; 71 int ret;
72 struct tps65910_board *board_data;
72 73
73 if (!gpio_base) 74 if (!gpio_base)
74 return; 75 return;
@@ -80,10 +81,10 @@ void tps65910_gpio_init(struct tps65910 *tps65910, int gpio_base)
80 81
81 switch(tps65910_chip_id(tps65910)) { 82 switch(tps65910_chip_id(tps65910)) {
82 case TPS65910: 83 case TPS65910:
83 tps65910->gpio.ngpio = 6; 84 tps65910->gpio.ngpio = TPS65910_NUM_GPIO;
84 break; 85 break;
85 case TPS65911: 86 case TPS65911:
86 tps65910->gpio.ngpio = 9; 87 tps65910->gpio.ngpio = TPS65911_NUM_GPIO;
87 break; 88 break;
88 default: 89 default:
89 return; 90 return;
@@ -95,6 +96,21 @@ void tps65910_gpio_init(struct tps65910 *tps65910, int gpio_base)
95 tps65910->gpio.set = tps65910_gpio_set; 96 tps65910->gpio.set = tps65910_gpio_set;
96 tps65910->gpio.get = tps65910_gpio_get; 97 tps65910->gpio.get = tps65910_gpio_get;
97 98
99 /* Configure sleep control for gpios */
100 board_data = dev_get_platdata(tps65910->dev);
101 if (board_data) {
102 int i;
103 for (i = 0; i < tps65910->gpio.ngpio; ++i) {
104 if (board_data->en_gpio_sleep[i]) {
105 ret = tps65910_set_bits(tps65910,
106 TPS65910_GPIO0 + i, GPIO_SLEEP_MASK);
107 if (ret < 0)
108 dev_warn(tps65910->dev,
109 "GPIO Sleep setting failed\n");
110 }
111 }
112 }
113
98 ret = gpiochip_add(&tps65910->gpio); 114 ret = gpiochip_add(&tps65910->gpio);
99 115
100 if (ret) 116 if (ret)
diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
index 17fdf4b6af93..d77354068b90 100644
--- a/drivers/gpio/gpiolib.c
+++ b/drivers/gpio/gpiolib.c
@@ -873,6 +873,7 @@ void gpio_unexport(unsigned gpio)
873{ 873{
874 struct gpio_desc *desc; 874 struct gpio_desc *desc;
875 int status = 0; 875 int status = 0;
876 struct device *dev = NULL;
876 877
877 if (!gpio_is_valid(gpio)) { 878 if (!gpio_is_valid(gpio)) {
878 status = -EINVAL; 879 status = -EINVAL;
@@ -884,19 +885,20 @@ void gpio_unexport(unsigned gpio)
884 desc = &gpio_desc[gpio]; 885 desc = &gpio_desc[gpio];
885 886
886 if (test_bit(FLAG_EXPORT, &desc->flags)) { 887 if (test_bit(FLAG_EXPORT, &desc->flags)) {
887 struct device *dev = NULL;
888 888
889 dev = class_find_device(&gpio_class, NULL, desc, match_export); 889 dev = class_find_device(&gpio_class, NULL, desc, match_export);
890 if (dev) { 890 if (dev) {
891 gpio_setup_irq(desc, dev, 0); 891 gpio_setup_irq(desc, dev, 0);
892 clear_bit(FLAG_EXPORT, &desc->flags); 892 clear_bit(FLAG_EXPORT, &desc->flags);
893 put_device(dev);
894 device_unregister(dev);
895 } else 893 } else
896 status = -ENODEV; 894 status = -ENODEV;
897 } 895 }
898 896
899 mutex_unlock(&sysfs_lock); 897 mutex_unlock(&sysfs_lock);
898 if (dev) {
899 device_unregister(dev);
900 put_device(dev);
901 }
900done: 902done:
901 if (status) 903 if (status)
902 pr_debug("%s: gpio%d status %d\n", __func__, gpio, status); 904 pr_debug("%s: gpio%d status %d\n", __func__, gpio, status);
diff --git a/drivers/of/gpio.c b/drivers/of/gpio.c
index 7e62d15d60f6..e034b38590a8 100644
--- a/drivers/of/gpio.c
+++ b/drivers/of/gpio.c
@@ -78,8 +78,9 @@ err0:
78EXPORT_SYMBOL(of_get_named_gpio_flags); 78EXPORT_SYMBOL(of_get_named_gpio_flags);
79 79
80/** 80/**
81 * of_gpio_count - Count GPIOs for a device 81 * of_gpio_named_count - Count GPIOs for a device
82 * @np: device node to count GPIOs for 82 * @np: device node to count GPIOs for
83 * @propname: property name containing gpio specifier(s)
83 * 84 *
84 * The function returns the count of GPIOs specified for a node. 85 * The function returns the count of GPIOs specified for a node.
85 * 86 *
@@ -93,14 +94,14 @@ EXPORT_SYMBOL(of_get_named_gpio_flags);
93 * defines four GPIOs (so this function will return 4), two of which 94 * defines four GPIOs (so this function will return 4), two of which
94 * are not specified. 95 * are not specified.
95 */ 96 */
96unsigned int of_gpio_count(struct device_node *np) 97unsigned int of_gpio_named_count(struct device_node *np, const char* propname)
97{ 98{
98 unsigned int cnt = 0; 99 unsigned int cnt = 0;
99 100
100 do { 101 do {
101 int ret; 102 int ret;
102 103
103 ret = of_parse_phandle_with_args(np, "gpios", "#gpio-cells", 104 ret = of_parse_phandle_with_args(np, propname, "#gpio-cells",
104 cnt, NULL); 105 cnt, NULL);
105 /* A hole in the gpios = <> counts anyway. */ 106 /* A hole in the gpios = <> counts anyway. */
106 if (ret < 0 && ret != -EEXIST) 107 if (ret < 0 && ret != -EEXIST)
@@ -109,7 +110,7 @@ unsigned int of_gpio_count(struct device_node *np)
109 110
110 return cnt; 111 return cnt;
111} 112}
112EXPORT_SYMBOL(of_gpio_count); 113EXPORT_SYMBOL(of_gpio_named_count);
113 114
114/** 115/**
115 * of_gpio_simple_xlate - translate gpio_spec to the GPIO number and flags 116 * of_gpio_simple_xlate - translate gpio_spec to the GPIO number and flags
diff --git a/include/linux/mfd/tps65910.h b/include/linux/mfd/tps65910.h
index d0cb12eba402..9071902bd222 100644
--- a/include/linux/mfd/tps65910.h
+++ b/include/linux/mfd/tps65910.h
@@ -657,6 +657,8 @@
657 657
658 658
659/*Register GPIO (0x80) register.RegisterDescription */ 659/*Register GPIO (0x80) register.RegisterDescription */
660#define GPIO_SLEEP_MASK 0x80
661#define GPIO_SLEEP_SHIFT 7
660#define GPIO_DEB_MASK 0x10 662#define GPIO_DEB_MASK 0x10
661#define GPIO_DEB_SHIFT 4 663#define GPIO_DEB_SHIFT 4
662#define GPIO_PUEN_MASK 0x08 664#define GPIO_PUEN_MASK 0x08
@@ -740,6 +742,11 @@
740#define TPS65910_GPIO_STS BIT(1) 742#define TPS65910_GPIO_STS BIT(1)
741#define TPS65910_GPIO_SET BIT(0) 743#define TPS65910_GPIO_SET BIT(0)
742 744
745/* Max number of TPS65910/11 GPIOs */
746#define TPS65910_NUM_GPIO 6
747#define TPS65911_NUM_GPIO 9
748#define TPS6591X_MAX_NUM_GPIO 9
749
743/* Regulator Index Definitions */ 750/* Regulator Index Definitions */
744#define TPS65910_REG_VRTC 0 751#define TPS65910_REG_VRTC 0
745#define TPS65910_REG_VIO 1 752#define TPS65910_REG_VIO 1
@@ -779,6 +786,7 @@ struct tps65910_board {
779 int irq_base; 786 int irq_base;
780 int vmbch_threshold; 787 int vmbch_threshold;
781 int vmbch2_threshold; 788 int vmbch2_threshold;
789 bool en_gpio_sleep[TPS6591X_MAX_NUM_GPIO];
782 struct regulator_init_data *tps65910_pmic_init_data[TPS65910_NUM_REGS]; 790 struct regulator_init_data *tps65910_pmic_init_data[TPS65910_NUM_REGS];
783}; 791};
784 792
diff --git a/include/linux/of_gpio.h b/include/linux/of_gpio.h
index b254052a49d7..81733d12cbea 100644
--- a/include/linux/of_gpio.h
+++ b/include/linux/of_gpio.h
@@ -50,7 +50,8 @@ static inline struct of_mm_gpio_chip *to_of_mm_gpio_chip(struct gpio_chip *gc)
50extern int of_get_named_gpio_flags(struct device_node *np, 50extern int of_get_named_gpio_flags(struct device_node *np,
51 const char *list_name, int index, enum of_gpio_flags *flags); 51 const char *list_name, int index, enum of_gpio_flags *flags);
52 52
53extern unsigned int of_gpio_count(struct device_node *np); 53extern unsigned int of_gpio_named_count(struct device_node *np,
54 const char* propname);
54 55
55extern int of_mm_gpiochip_add(struct device_node *np, 56extern int of_mm_gpiochip_add(struct device_node *np,
56 struct of_mm_gpio_chip *mm_gc); 57 struct of_mm_gpio_chip *mm_gc);
@@ -71,7 +72,8 @@ static inline int of_get_named_gpio_flags(struct device_node *np,
71 return -ENOSYS; 72 return -ENOSYS;
72} 73}
73 74
74static inline unsigned int of_gpio_count(struct device_node *np) 75static inline unsigned int of_gpio_named_count(struct device_node *np,
76 const char* propname)
75{ 77{
76 return 0; 78 return 0;
77} 79}
@@ -89,6 +91,27 @@ static inline void of_gpiochip_remove(struct gpio_chip *gc) { }
89#endif /* CONFIG_OF_GPIO */ 91#endif /* CONFIG_OF_GPIO */
90 92
91/** 93/**
94 * of_gpio_count - Count GPIOs for a device
95 * @np: device node to count GPIOs for
96 *
97 * The function returns the count of GPIOs specified for a node.
98 *
99 * Note that the empty GPIO specifiers counts too. For example,
100 *
101 * gpios = <0
102 * &pio1 1 2
103 * 0
104 * &pio2 3 4>;
105 *
106 * defines four GPIOs (so this function will return 4), two of which
107 * are not specified.
108 */
109static inline unsigned int of_gpio_count(struct device_node *np)
110{
111 return of_gpio_named_count(np, "gpios");
112}
113
114/**
92 * of_get_gpio_flags() - Get a GPIO number and flags to use with GPIO API 115 * of_get_gpio_flags() - Get a GPIO number and flags to use with GPIO API
93 * @np: device node to get GPIO from 116 * @np: device node to get GPIO from
94 * @index: index of the GPIO 117 * @index: index of the GPIO
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-16 01:09:53 -0500