62 files changed, 11902 insertions, 2987 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 49d993cee512..dfb4fee1f552 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -645,7 +645,7 @@ config ARCH_SHMOBILE
         select MULTI_IRQ_HANDLER
         select NEED_MACH_MEMORY_H
         select NO_IOPORT
-        select PINCTRL if ARCH_WANT_OPTIONAL_GPIOLIB
+        select PINCTRL
         select PM_GENERIC_DOMAINS if PM
         select SPARSE_IRQ
         help
diff --git a/arch/arm/boot/dts/kirkwood-lsxl.dtsi b/arch/arm/boot/dts/kirkwood-lsxl.dtsi
index 37d45c4f88fb..996c7fefd253 100644
--- a/arch/arm/boot/dts/kirkwood-lsxl.dtsi
+++ b/arch/arm/boot/dts/kirkwood-lsxl.dtsi
@@ -172,6 +172,10 @@
                 alarm-gpios = <&gpio1 8 0>;
         };
 
+        restart_poweroff {
+                compatible = "restart-poweroff";
+        };
+
         regulators {
                 compatible = "simple-bus";
                 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/kirkwood-ts219.dtsi b/arch/arm/boot/dts/kirkwood-ts219.dtsi
index 64ea27cb3298..4e29460baf04 100644
--- a/arch/arm/boot/dts/kirkwood-ts219.dtsi
+++ b/arch/arm/boot/dts/kirkwood-ts219.dtsi
@@ -31,6 +31,11 @@
                         clock-frequency = <200000000>;
                         status = "okay";
                 };
+                poweroff@12100 {
+                        compatible = "qnap,power-off";
+                        reg = <0x12000 0x100>;
+                        clocks = <&gate_clk 7>;
+                };
                 spi@10600 {
                         status = "okay";
 
diff --git a/arch/arm/configs/armadillo800eva_defconfig b/arch/arm/configs/armadillo800eva_defconfig
index 0f2d80da7378..fae939d3d7f0 100644
--- a/arch/arm/configs/armadillo800eva_defconfig
+++ b/arch/arm/configs/armadillo800eva_defconfig
@@ -86,7 +86,7 @@ CONFIG_TOUCHSCREEN_ST1232=y
 # CONFIG_SERIO is not set
 # CONFIG_LEGACY_PTYS is not set
 CONFIG_SERIAL_SH_SCI=y
-CONFIG_SERIAL_SH_SCI_NR_UARTS=8
+CONFIG_SERIAL_SH_SCI_NR_UARTS=9
 CONFIG_SERIAL_SH_SCI_CONSOLE=y
 # CONFIG_HW_RANDOM is not set
 CONFIG_I2C=y
diff --git a/arch/arm/configs/bcm2835_defconfig b/arch/arm/configs/bcm2835_defconfig
index ce987211a609..34e9780e63ba 100644
--- a/arch/arm/configs/bcm2835_defconfig
+++ b/arch/arm/configs/bcm2835_defconfig
@@ -55,14 +55,11 @@ CONFIG_DEVTMPFS_MOUNT=y
 # CONFIG_INPUT_KEYBOARD is not set
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_SERIO is not set
-# CONFIG_VT is not set
 # CONFIG_LEGACY_PTYS is not set
 # CONFIG_DEVKMEM is not set
 CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
 CONFIG_TTY_PRINTK=y
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_BCM2835=y
 CONFIG_I2C=y
 CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_BCM2835=y
@@ -70,11 +67,27 @@ CONFIG_SPI=y
 CONFIG_SPI_BCM2835=y
 CONFIG_GPIO_SYSFS=y
 # CONFIG_HWMON is not set
+CONFIG_FB=y
+CONFIG_FB_SIMPLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
 # CONFIG_USB_SUPPORT is not set
 CONFIG_MMC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MMC_SDHCI_BCM2835=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_ONESHOT=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+CONFIG_LEDS_TRIGGER_TRANSIENT=y
+CONFIG_LEDS_TRIGGER_CAMERA=y
 # CONFIG_IOMMU_SUPPORT is not set
 CONFIG_EXT2_FS=y
 CONFIG_EXT2_FS_XATTR=y
diff --git a/arch/arm/configs/bockw_defconfig b/arch/arm/configs/bockw_defconfig
index 6524cdf3b08d..845f5cdf62b5 100644
--- a/arch/arm/configs/bockw_defconfig
+++ b/arch/arm/configs/bockw_defconfig
@@ -31,6 +31,7 @@ CONFIG_CMDLINE="console=ttySC0,115200 ignore_loglevel root=/dev/nfs ip=dhcp"
 CONFIG_CMDLINE_FORCE=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
 # CONFIG_SUSPEND is not set
+CONFIG_PM_RUNTIME=y
 CONFIG_NET=y
 CONFIG_UNIX=y
 CONFIG_INET=y
@@ -48,6 +49,14 @@ CONFIG_DEVTMPFS_MOUNT=y
 # CONFIG_STANDALONE is not set
 # CONFIG_PREVENT_FIRMWARE_BUILD is not set
 # CONFIG_FW_LOADER is not set
+CONFIG_MTD=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_M25P80=y
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
 CONFIG_NETDEVICES=y
 # CONFIG_NET_CADENCE is not set
 # CONFIG_NET_VENDOR_BROADCOM is not set
@@ -71,7 +80,23 @@ CONFIG_SERIAL_SH_SCI_NR_UARTS=6
 CONFIG_SERIAL_SH_SCI_CONSOLE=y
 # CONFIG_HW_RANDOM is not set
 # CONFIG_HWMON is not set
-# CONFIG_USB_SUPPORT is not set
+CONFIG_I2C=y
+CONFIG_I2C_RCAR=y
+CONFIG_SPI=y
+CONFIG_SPI_SH_HSPI=y
+CONFIG_USB=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_RCAR_PHY=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHI=y
+CONFIG_MMC_SH_MMCIF=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_RX8581=y
 CONFIG_UIO=y
 CONFIG_UIO_PDRV_GENIRQ=y
 # CONFIG_IOMMU_SUPPORT is not set
diff --git a/arch/arm/configs/kzm9g_defconfig b/arch/arm/configs/kzm9g_defconfig
index f6e585b353a4..1ad028023a64 100644
--- a/arch/arm/configs/kzm9g_defconfig
+++ b/arch/arm/configs/kzm9g_defconfig
@@ -84,9 +84,12 @@ CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_SH_MOBILE=y
 CONFIG_GPIO_PCF857X=y
 # CONFIG_HWMON is not set
+CONFIG_MFD_AS3711=y
 CONFIG_REGULATOR=y
+CONFIG_REGULATOR_AS3711=y
 CONFIG_FB=y
 CONFIG_FB_SH_MOBILE_LCDC=y
+CONFIG_BACKLIGHT_AS3711=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_LOGO=y
 CONFIG_FB_SH_MOBILE_MERAM=y
diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index f7ba316164d4..1effb43dab80 100644
--- a/arch/arm/configs/tegra_defconfig
+++ b/arch/arm/configs/tegra_defconfig
@@ -21,8 +21,8 @@ CONFIG_MODULE_FORCE_UNLOAD=y
 CONFIG_PARTITION_ADVANCED=y
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_TEGRA=y
 CONFIG_GPIO_PCA953X=y
+CONFIG_ARCH_TEGRA=y
 CONFIG_ARCH_TEGRA_2x_SOC=y
 CONFIG_ARCH_TEGRA_3x_SOC=y
 CONFIG_ARCH_TEGRA_114_SOC=y
@@ -36,7 +36,6 @@ CONFIG_HIGHMEM=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_KEXEC=y
-CONFIG_AUTO_ZRELADDR=y
 CONFIG_CPU_FREQ=y
 CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
 CONFIG_CPU_IDLE=y
@@ -81,7 +80,6 @@ CONFIG_DEVTMPFS_MOUNT=y
 # CONFIG_FIRMWARE_IN_KERNEL is not set
 CONFIG_CMA=y
 CONFIG_MTD=y
-CONFIG_MTD_CHAR=y
 CONFIG_MTD_M25P80=y
 CONFIG_PROC_DEVICETREE=y
 CONFIG_BLK_DEV_LOOP=y
@@ -105,8 +103,8 @@ CONFIG_BRCMFMAC=m
 CONFIG_RT2X00=y
 CONFIG_RT2800USB=m
 CONFIG_INPUT_EVDEV=y
-CONFIG_KEYBOARD_TEGRA=y
 CONFIG_KEYBOARD_GPIO=y
+CONFIG_KEYBOARD_TEGRA=y
 CONFIG_INPUT_MISC=y
 CONFIG_INPUT_MPU3050=y
 # CONFIG_LEGACY_PTYS is not set
@@ -121,6 +119,7 @@ CONFIG_I2C_MUX=y
 CONFIG_I2C_MUX_PINCTRL=y
 CONFIG_I2C_TEGRA=y
 CONFIG_SPI=y
+CONFIG_SPI_TEGRA114=y
 CONFIG_SPI_TEGRA20_SFLASH=y
 CONFIG_SPI_TEGRA20_SLINK=y
 CONFIG_GPIO_PCA953X_IRQ=y
@@ -129,14 +128,15 @@ CONFIG_GPIO_TPS6586X=y
 CONFIG_GPIO_TPS65910=y
 CONFIG_POWER_SUPPLY=y
 CONFIG_BATTERY_SBS=y
+CONFIG_CHARGER_TPS65090=y
 CONFIG_POWER_RESET=y
 CONFIG_POWER_RESET_GPIO=y
 CONFIG_SENSORS_LM90=y
-CONFIG_MFD_TPS6586X=y
-CONFIG_MFD_TPS65910=y
 CONFIG_MFD_MAX8907=y
-CONFIG_MFD_TPS65090=y
 CONFIG_MFD_PALMAS=y
+CONFIG_MFD_TPS65090=y
+CONFIG_MFD_TPS6586X=y
+CONFIG_MFD_TPS65910=y
 CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
@@ -171,6 +171,7 @@ CONFIG_SND=y
 # CONFIG_SND_USB is not set
 CONFIG_SND_SOC=y
 CONFIG_SND_SOC_TEGRA=y
+CONFIG_SND_SOC_TEGRA_RT5640=y
 CONFIG_SND_SOC_TEGRA_WM8753=y
 CONFIG_SND_SOC_TEGRA_WM8903=y
 CONFIG_SND_SOC_TEGRA_TRIMSLICE=y
@@ -190,7 +191,13 @@ CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_GPIO=y
 CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_ONESHOT=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+CONFIG_LEDS_TRIGGER_TRANSIENT=y
+CONFIG_LEDS_TRIGGER_CAMERA=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_MAX8907=y
 CONFIG_RTC_DRV_PALMAS=y
@@ -203,7 +210,6 @@ CONFIG_TEGRA20_APB_DMA=y
 CONFIG_STAGING=y
 CONFIG_SENSORS_ISL29018=y
 CONFIG_SENSORS_ISL29028=y
-CONFIG_AK8975=y
 CONFIG_MFD_NVEC=y
 CONFIG_KEYBOARD_NVEC=y
 CONFIG_SERIO_NVEC_PS2=y
@@ -213,6 +219,7 @@ CONFIG_TEGRA_IOMMU_GART=y
 CONFIG_TEGRA_IOMMU_SMMU=y
 CONFIG_MEMORY=y
 CONFIG_IIO=y
+CONFIG_AK8975=y
 CONFIG_PWM=y
 CONFIG_PWM_TEGRA=y
 CONFIG_EXT2_FS=y
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 7509a89af967..1f7078e453b0 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -227,6 +227,7 @@ config MACH_KM_KIRKWOOD_DT
 config MACH_LSXL_DT
         bool "Buffalo Linkstation LS-XHL, LS-CHLv2 (Flattened Device Tree)"
         select ARCH_KIRKWOOD_DT
+        select POWER_RESET_RESTART
         help
           Say 'Y' here if you want your kernel to support the
           Buffalo Linkstation LS-XHL & LS-CHLv2 devices, using
@@ -296,6 +297,13 @@ config MACH_READYNAS_DT
           Say 'Y' here if you want your kernel to support the
           NETGEAR ReadyNAS Duo v2 using Fattened Device Tree.
 
+config MACH_SHEEVAPLUG_DT
+        bool "Marvell (eSATA) SheevaPlug (Flattened Device Tree)"
+        select ARCH_KIRKWOOD_DT
+        help
+          Say 'Y' here if you want your kernel to support the
+          Marvell (eSATA) SheevaPlug (Flattened Device Tree).
+
 config MACH_TOPKICK_DT
         bool "USI Topkick (Flattened Device Tree)"
         select ARCH_KIRKWOOD_DT
@@ -308,6 +316,7 @@ config MACH_TS219_DT
         select ARCH_KIRKWOOD_DT
         select ARM_APPENDED_DTB
         select ARM_ATAG_DTB_COMPAT
+        select POWER_RESET_QNAP
         help
           Say 'Y' here if you want your kernel to support the QNAP
           TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index e1f3735d3415..8846abf8fc73 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -40,5 +40,6 @@ obj-$(CONFIG_MACH_NETSPACE_V2_DT)	+= board-ns2.o
 obj-$(CONFIG_MACH_NSA310_DT)            += board-nsa310.o
 obj-$(CONFIG_MACH_OPENBLOCKS_A6_DT)     += board-openblocks_a6.o
 obj-$(CONFIG_MACH_READYNAS_DT)          += board-readynas.o
+obj-$(CONFIG_MACH_SHEEVAPLUG_DT)        += board-sheevaplug.o
 obj-$(CONFIG_MACH_TOPKICK_DT)           += board-usi_topkick.o
 obj-$(CONFIG_MACH_TS219_DT)             += board-ts219.o tsx1x-common.o
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index e9647b80cb59..a09dbac61efa 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -112,6 +112,9 @@ static void __init kirkwood_dt_init(void)
         if (of_machine_is_compatible("globalscale,guruplug"))
                 guruplug_dt_init();
 
+        if (of_machine_is_compatible("globalscale,sheevaplug"))
+                sheevaplug_dt_init();
+
         if (of_machine_is_compatible("dlink,dns-kirkwood"))
                 dnskw_init();
 
@@ -165,6 +168,7 @@ static void __init kirkwood_dt_init(void)
 static const char * const kirkwood_dt_board_compat[] = {
         "globalscale,dreamplug",
         "globalscale,guruplug",
+        "globalscale,sheevaplug",
         "dlink,dns-320",
         "dlink,dns-325",
         "iom,iconnect",
diff --git a/arch/arm/mach-kirkwood/board-lsxl.c b/arch/arm/mach-kirkwood/board-lsxl.c
index 4ec8b7ae784a..348395238df6 100644
--- a/arch/arm/mach-kirkwood/board-lsxl.c
+++ b/arch/arm/mach-kirkwood/board-lsxl.c
@@ -25,19 +25,6 @@ static struct mv643xx_eth_platform_data lsxl_ge01_data = {
         .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
 };
 
-/*
- * On the LS-XHL/LS-CHLv2, the shutdown process is following:
- * - Userland monitors key events until the power switch goes to off position
- * - The board reboots
- * - U-boot starts and goes into an idle mode waiting for the user
- *   to move the switch to ON position
- *
- */
-static void lsxl_power_off(void)
-{
-        kirkwood_restart('h', NULL);
-}
-
 void __init lsxl_init(void)
 {
         /*
@@ -46,7 +33,4 @@ void __init lsxl_init(void)
 
         kirkwood_ge00_init(&lsxl_ge00_data);
         kirkwood_ge01_init(&lsxl_ge01_data);
-
-        /* register power-off method */
-        pm_power_off = lsxl_power_off;
 }
diff --git a/arch/arm/mach-kirkwood/board-sheevaplug.c b/arch/arm/mach-kirkwood/board-sheevaplug.c
new file mode 100644
index 000000000000..fa389373ca74
--- /dev/null
+++ b/arch/arm/mach-kirkwood/board-sheevaplug.c
@@ -0,0 +1,27 @@
+/*
+ * arch/arm/mach-kirkwood/board-sheevaplug.c
+ *
+ * Marvell Sheevaplug Reference Board Init for drivers not converted to
+ * flattened device tree yet.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mv643xx_eth.h>
+#include "common.h"
+
+static struct mv643xx_eth_platform_data sheevaplug_ge00_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(0),
+};
+
+void __init sheevaplug_dt_init(void)
+{
+        /*
+         * Basic setup. Needs to be called early.
+         */
+        kirkwood_ge00_init(&sheevaplug_ge00_data);
+}
diff --git a/arch/arm/mach-kirkwood/board-ts219.c b/arch/arm/mach-kirkwood/board-ts219.c
index 4695d5f35fc9..860f44ab457d 100644
--- a/arch/arm/mach-kirkwood/board-ts219.c
+++ b/arch/arm/mach-kirkwood/board-ts219.c
@@ -23,7 +23,6 @@
 #include <asm/mach/arch.h>
 #include <mach/kirkwood.h>
 #include "common.h"
-#include "tsx1x-common.h"
 
 static struct mv643xx_eth_platform_data qnap_ts219_ge00_data = {
         .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
@@ -38,6 +37,4 @@ void __init qnap_dt_ts219_init(void)
                 qnap_ts219_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0);
 
         kirkwood_ge00_init(&qnap_ts219_ge00_data);
-
-        pm_power_off = qnap_tsx1x_power_off;
 }
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 21da3b1ebd7b..974442eca0c8 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -65,6 +65,11 @@ void guruplug_dt_init(void);
 #else
 static inline void guruplug_dt_init(void) {};
 #endif
+#ifdef CONFIG_MACH_SHEEVAPLUG_DT
+void sheevaplug_dt_init(void);
+#else
+static inline void sheevaplug_dt_init(void) {};
+#endif
 #ifdef CONFIG_MACH_TS219_DT
 void qnap_dt_ts219_init(void);
 #else
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 1a517e2fe449..5414402938a5 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -36,7 +36,8 @@ config ARCH_R8A7740
         select RENESAS_INTC_IRQPIN
 
 config ARCH_R8A7778
-        bool "R-Car M1 (R8A77780)"
+        bool "R-Car M1A (R8A77781)"
+        select ARCH_WANT_OPTIONAL_GPIOLIB
         select CPU_V7
         select SH_CLK_CPG
         select ARM_GIC
@@ -169,6 +170,8 @@ config MACH_KZM9D
 config MACH_KZM9G
         bool "KZM-A9-GT board"
         depends on ARCH_SH73A0
+        select ARCH_HAS_CPUFREQ
+        select ARCH_HAS_OPP
         select ARCH_REQUIRE_GPIOLIB
         select REGULATOR_FIXED_VOLTAGE if REGULATOR
         select SND_SOC_AK4642 if SND_SIMPLE_CARD
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index 45f78cadec1d..297bf5eec5ab 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -1026,10 +1026,8 @@ out:
 
 /* TouchScreen */
 #ifdef CONFIG_AP4EVB_QHD
-# define GPIO_TSC_IRQ   GPIO_FN_IRQ28_123
 # define GPIO_TSC_PORT  123
 #else /* WVGA */
-# define GPIO_TSC_IRQ   GPIO_FN_IRQ7_40
 # define GPIO_TSC_PORT  40
 #endif
 
@@ -1037,22 +1035,12 @@ out:
 #define IRQ7    evt2irq(0x02e0) /* IRQ7A */
 static int ts_get_pendown_state(void)
 {
-        int val;
-
-        gpio_free(GPIO_TSC_IRQ);
-
-        gpio_request_one(GPIO_TSC_PORT, GPIOF_IN, NULL);
-
-        val = gpio_get_value(GPIO_TSC_PORT);
-
-        gpio_request(GPIO_TSC_IRQ, NULL);
-
-        return !val;
+        return !gpio_get_value(GPIO_TSC_PORT);
 }
 
 static int ts_init(void)
 {
-        gpio_request(GPIO_TSC_IRQ, NULL);
+        gpio_request_one(GPIO_TSC_PORT, GPIOF_IN, NULL);
 
         return 0;
 }
@@ -1086,11 +1074,42 @@ static struct i2c_board_info i2c1_devices[] = {
 
 
 static const struct pinctrl_map ap4evb_pinctrl_map[] = {
+        /* CEU */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372",
+                                  "ceu_clk_0", "ceu"),
+        /* FSIA (AK4643) */
+        PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372",
+                                  "fsia_sclk_in", "fsia"),
+        PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372",
+                                  "fsia_data_in", "fsia"),
+        PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372",
+                                  "fsia_data_out", "fsia"),
+        /* FSIB (HDMI) */
+        PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.1", "pfc-sh7372",
+                                  "fsib_mclk_in", "fsib"),
+        /* HDMI */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-mobile-hdmi", "pfc-sh7372",
+                                  "hdmi", "hdmi"),
+        /* KEYSC */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc", "pfc-sh7372",
+                                  "keysc_in04_0", "keysc"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc", "pfc-sh7372",
+                                  "keysc_out5", "keysc"),
+#ifndef CONFIG_AP4EVB_QHD
+        /* LCDC */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh7372",
+                                  "lcd_data18", "lcd"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh7372",
+                                  "lcd_sync", "lcd"),
+#endif
         /* MMCIF */
         PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
                                   "mmc0_data8_0", "mmc0"),
         PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
                                   "mmc0_ctrl_0", "mmc0"),
+        /* SCIFA0 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-sh7372",
+                                  "scifa0_data", "scifa0"),
         /* SDHI0 */
         PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
                                   "sdhi0_data4", "sdhi0"),
@@ -1105,6 +1124,26 @@ static const struct pinctrl_map ap4evb_pinctrl_map[] = {
                                   "sdhi1_data4", "sdhi1"),
         PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372",
                                   "sdhi1_ctrl", "sdhi1"),
+        /* SMSC911X */
+        PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-sh7372",
+                                  "bsc_cs5a", "bsc"),
+        PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-sh7372",
+                                  "intc_irq6_0", "intc"),
+        /* TSC2007 */
+#ifdef CONFIG_AP4EVB_QHD
+        PIN_MAP_MUX_GROUP_DEFAULT("1-0048", "pfc-sh7372",
+                                  "intc_irq28_0", "intc"),
+#else /* WVGA */
+        PIN_MAP_MUX_GROUP_DEFAULT("1-0048", "pfc-sh7372",
+                                  "intc_irq7_0", "intc"),
+#endif
+        /* USBHS1 */
+        PIN_MAP_MUX_GROUP_DEFAULT("r8a66597_hcd.1", "pfc-sh7372",
+                                  "usb1_vbus", "usb1"),
+        PIN_MAP_MUX_GROUP_DEFAULT("r8a66597_hcd.1", "pfc-sh7372",
+                                  "usb1_otg_id_0", "usb1"),
+        PIN_MAP_MUX_GROUP_DEFAULT("r8a66597_hcd.1", "pfc-sh7372",
+                                  "usb1_otg_ctrl_0", "usb1"),
 };
 
 #define GPIO_PORT9CR    IOMEM(0xE6051009)
@@ -1137,36 +1176,16 @@ static void __init ap4evb_init(void)
                                   ARRAY_SIZE(ap4evb_pinctrl_map));
         sh7372_pinmux_init();
 
-        /* enable SCIFA0 */
-        gpio_request(GPIO_FN_SCIFA0_TXD, NULL);
-        gpio_request(GPIO_FN_SCIFA0_RXD, NULL);
-
-        /* enable SMSC911X */
-        gpio_request(GPIO_FN_CS5A,      NULL);
-        gpio_request(GPIO_FN_IRQ6_39,   NULL);
-
         /* enable Debug switch (S6) */
         gpio_request_one(32, GPIOF_IN | GPIOF_EXPORT, NULL);
         gpio_request_one(33, GPIOF_IN | GPIOF_EXPORT, NULL);
         gpio_request_one(34, GPIOF_IN | GPIOF_EXPORT, NULL);
         gpio_request_one(35, GPIOF_IN | GPIOF_EXPORT, NULL);
 
-        /* USB enable */
-        gpio_request(GPIO_FN_VBUS0_1,    NULL);
-        gpio_request(GPIO_FN_IDIN_1_18,  NULL);
-        gpio_request(GPIO_FN_PWEN_1_115, NULL);
-        gpio_request(GPIO_FN_OVCN_1_114, NULL);
-        gpio_request(GPIO_FN_EXTLP_1,    NULL);
-        gpio_request(GPIO_FN_OVCN2_1,    NULL);
-
         /* setup USB phy */
         __raw_writew(0x8a0a, IOMEM(0xE6058130));        /* USBCR4 */
 
-        /* enable FSI2 port A (ak4643) */
-        gpio_request(GPIO_FN_FSIAIBT,   NULL);
-        gpio_request(GPIO_FN_FSIAILR,   NULL);
-        gpio_request(GPIO_FN_FSIAISLD,  NULL);
-        gpio_request(GPIO_FN_FSIAOSLD,  NULL);
+        /* FSI2 port A (ak4643) */
         gpio_request_one(161, GPIOF_OUT_INIT_LOW, NULL); /* slave */
 
         gpio_request(9, NULL);
@@ -1177,8 +1196,7 @@ static void __init ap4evb_init(void)
         /* card detect pin for MMC slot (CN7) */
         gpio_request_one(41, GPIOF_IN, NULL);
 
-        /* setup FSI2 port B (HDMI) */
-        gpio_request(GPIO_FN_FSIBCK, NULL);
+        /* FSI2 port B (HDMI) */
         __raw_writew(__raw_readw(USCCR1) & ~(1 << 6), USCCR1); /* use SPDIF */
 
         /* set SPU2 clock to 119.6 MHz */
@@ -1208,18 +1226,6 @@ static void __init ap4evb_init(void)
          * IRQ28 for Touch Panel, set dip switches S3, S43 as OFF, ON.
          */
 
-        /* enable KEYSC */
-        gpio_request(GPIO_FN_KEYOUT0, NULL);
-        gpio_request(GPIO_FN_KEYOUT1, NULL);
-        gpio_request(GPIO_FN_KEYOUT2, NULL);
-        gpio_request(GPIO_FN_KEYOUT3, NULL);
-        gpio_request(GPIO_FN_KEYOUT4, NULL);
-        gpio_request(GPIO_FN_KEYIN0_136, NULL);
-        gpio_request(GPIO_FN_KEYIN1_135, NULL);
-        gpio_request(GPIO_FN_KEYIN2_134, NULL);
-        gpio_request(GPIO_FN_KEYIN3_133, NULL);
-        gpio_request(GPIO_FN_KEYIN4,     NULL);
-
         /* enable TouchScreen */
         irq_set_irq_type(IRQ28, IRQ_TYPE_LEVEL_LOW);
 
@@ -1241,28 +1247,6 @@ static void __init ap4evb_init(void)
          * For WVGA Panel (18-bit RGB, CONFIG_AP4EVB_WVGA=y) and
          * IRQ7 for Touch Panel, set dip switches S3, S43 to ON, OFF.
          */
-
-        gpio_request(GPIO_FN_LCDD17,   NULL);
-        gpio_request(GPIO_FN_LCDD16,   NULL);
-        gpio_request(GPIO_FN_LCDD15,   NULL);
-        gpio_request(GPIO_FN_LCDD14,   NULL);
-        gpio_request(GPIO_FN_LCDD13,   NULL);
-        gpio_request(GPIO_FN_LCDD12,   NULL);
-        gpio_request(GPIO_FN_LCDD11,   NULL);
-        gpio_request(GPIO_FN_LCDD10,   NULL);
-        gpio_request(GPIO_FN_LCDD9,    NULL);
-        gpio_request(GPIO_FN_LCDD8,    NULL);
-        gpio_request(GPIO_FN_LCDD7,    NULL);
-        gpio_request(GPIO_FN_LCDD6,    NULL);
-        gpio_request(GPIO_FN_LCDD5,    NULL);
-        gpio_request(GPIO_FN_LCDD4,    NULL);
-        gpio_request(GPIO_FN_LCDD3,    NULL);
-        gpio_request(GPIO_FN_LCDD2,    NULL);
-        gpio_request(GPIO_FN_LCDD1,    NULL);
-        gpio_request(GPIO_FN_LCDD0,    NULL);
-        gpio_request(GPIO_FN_LCDDISP,  NULL);
-        gpio_request(GPIO_FN_LCDDCK,   NULL);
-
         gpio_request_one(189, GPIOF_OUT_INIT_HIGH, NULL); /* backlight */
         gpio_request_one(151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
 
@@ -1288,8 +1272,6 @@ static void __init ap4evb_init(void)
          */
 
         /* MIPI-CSI stuff */
-        gpio_request(GPIO_FN_VIO_CKO, NULL);
-
         clk = clk_get(NULL, "vck1_clk");
         if (!IS_ERR(clk)) {
                 clk_set_rate(clk, clk_round_rate(clk, 13000000));
@@ -1299,10 +1281,6 @@ static void __init ap4evb_init(void)
 
         sh7372_add_standard_devices();
 
-        /* HDMI */
-        gpio_request(GPIO_FN_HDMI_HPD, NULL);
-        gpio_request(GPIO_FN_HDMI_CEC, NULL);
-
         /* Reset HDMI, must be held at least one EXTALR (32768Hz) period */
 #define SRCR4 IOMEM(0xe61580bc)
         srcr4 = __raw_readl(SRCR4);
diff --git a/arch/arm/mach-shmobile/board-ape6evm.c b/arch/arm/mach-shmobile/board-ape6evm.c
index 55b8c9fef954..5eb0caa6a7d0 100644
--- a/arch/arm/mach-shmobile/board-ape6evm.c
+++ b/arch/arm/mach-shmobile/board-ape6evm.c
@@ -26,6 +26,7 @@
 #include <linux/platform_device.h>
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
+#include <linux/sh_clk.h>
 #include <linux/smsc911x.h>
 #include <mach/common.h>
 #include <mach/irqs.h>
@@ -65,7 +66,21 @@ static const struct pinctrl_map ape6evm_pinctrl_map[] = {
 
 static void __init ape6evm_add_standard_devices(void)
 {
+
+        struct clk *parent;
+        struct clk *mp;
+
         r8a73a4_clock_init();
+
+        /* MP clock parent = extal2 */
+        parent      = clk_get(NULL, "extal2");
+        mp          = clk_get(NULL, "mp");
+        BUG_ON(IS_ERR(parent) || IS_ERR(mp));
+
+        clk_set_parent(mp, parent);
+        clk_put(parent);
+        clk_put(mp);
+
         pinctrl_register_mappings(ape6evm_pinctrl_map,
                                   ARRAY_SIZE(ape6evm_pinctrl_map));
         r8a73a4_pinmux_init();
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index b85b2882dbd0..44a621505eeb 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -584,7 +584,7 @@ static struct regulator_init_data vcc_sdhi0_init_data = {
 static struct fixed_voltage_config vcc_sdhi0_info = {
         .supply_name = "SDHI0 Vcc",
         .microvolts = 3300000,
-        .gpio = GPIO_PORT75,
+        .gpio = 75,
         .enable_high = 1,
         .init_data = &vcc_sdhi0_init_data,
 };
@@ -615,7 +615,7 @@ static struct regulator_init_data vccq_sdhi0_init_data = {
 };
 
 static struct gpio vccq_sdhi0_gpios[] = {
-        {GPIO_PORT17, GPIOF_OUT_INIT_LOW, "vccq-sdhi0" },
+        {17, GPIOF_OUT_INIT_LOW, "vccq-sdhi0" },
 };
 
 static struct gpio_regulator_state vccq_sdhi0_states[] = {
@@ -626,7 +626,7 @@ static struct gpio_regulator_state vccq_sdhi0_states[] = {
 static struct gpio_regulator_config vccq_sdhi0_info = {
         .supply_name = "vqmmc",
 
-        .enable_gpio = GPIO_PORT74,
+        .enable_gpio = 74,
         .enable_high = 1,
         .enabled_at_boot = 0,
 
@@ -664,7 +664,7 @@ static struct regulator_init_data vcc_sdhi1_init_data = {
 static struct fixed_voltage_config vcc_sdhi1_info = {
         .supply_name = "SDHI1 Vcc",
         .microvolts = 3300000,
-        .gpio = GPIO_PORT16,
+        .gpio = 16,
         .enable_high = 1,
         .init_data = &vcc_sdhi1_init_data,
 };
@@ -693,7 +693,7 @@ static struct sh_mobile_sdhi_info sdhi0_info = {
         .tmio_caps      = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
                           MMC_CAP_POWER_OFF_CARD,
         .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD,
-        .cd_gpio        = GPIO_PORT167,
+        .cd_gpio        = 167,
 };
 
 static struct resource sdhi0_resources[] = {
@@ -736,7 +736,7 @@ static struct sh_mobile_sdhi_info sdhi1_info = {
                           MMC_CAP_POWER_OFF_CARD,
         .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD,
         /* Port72 cannot generate IRQs, will be used in polling mode. */
-        .cd_gpio        = GPIO_PORT72,
+        .cd_gpio        = 72,
 };
 
 static struct resource sdhi1_resources[] = {
@@ -1046,6 +1046,35 @@ static struct platform_device *eva_devices[] __initdata = {
 };
 
 static const struct pinctrl_map eva_pinctrl_map[] = {
+        /* CEU0 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-r8a7740",
+                                  "ceu0_data_0_7", "ceu0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-r8a7740",
+                                  "ceu0_clk_0", "ceu0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-r8a7740",
+                                  "ceu0_sync", "ceu0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-r8a7740",
+                                  "ceu0_field", "ceu0"),
+        /* FSIA */
+        PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-r8a7740",
+                                  "fsia_sclk_in", "fsia"),
+        PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-r8a7740",
+                                  "fsia_mclk_out", "fsia"),
+        PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-r8a7740",
+                                  "fsia_data_in_1", "fsia"),
+        PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-r8a7740",
+                                  "fsia_data_out_0", "fsia"),
+        /* FSIB */
+        PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.1", "pfc-r8a7740",
+                                  "fsib_mclk_in", "fsib"),
+        /* GETHER */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7740",
+                                  "gether_mii", "gether"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7740",
+                                  "gether_int", "gether"),
+        /* HDMI */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-mobile-hdmi", "pfc-r8a7740",
+                                  "hdmi", "hdmi"),
         /* LCD0 */
         PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
                                   "lcd0_data24_0", "lcd0"),
@@ -1058,6 +1087,9 @@ static const struct pinctrl_map eva_pinctrl_map[] = {
                                   "mmc0_data8_1", "mmc0"),
         PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-r8a7740",
                                   "mmc0_ctrl_1", "mmc0"),
+        /* SCIFA1 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.1", "pfc-r8a7740",
+                                  "scifa1_data", "scifa1"),
         /* SDHI0 */
         PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7740",
                                   "sdhi0_data4", "sdhi0"),
@@ -1065,6 +1097,12 @@ static const struct pinctrl_map eva_pinctrl_map[] = {
                                   "sdhi0_ctrl", "sdhi0"),
         PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7740",
                                   "sdhi0_wp", "sdhi0"),
+        /* ST1232 */
+        PIN_MAP_MUX_GROUP_DEFAULT("0-0055", "pfc-r8a7740",
+                                  "intc_irq10", "intc"),
+        /* USBHS */
+        PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs", "pfc-r8a7740",
+                                  "intc_irq7_1", "intc"),
 };
 
 static void __init eva_clock_init(void)
@@ -1119,40 +1157,14 @@ static void __init eva_init(void)
         r8a7740_pinmux_init();
         r8a7740_meram_workaround();
 
-        /* SCIFA1 */
-        gpio_request(GPIO_FN_SCIFA1_RXD, NULL);
-        gpio_request(GPIO_FN_SCIFA1_TXD, NULL);
-
         /* LCDC0 */
-        gpio_request(GPIO_FN_LCDC0_SELECT,      NULL);
-
         gpio_request_one(61, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
         gpio_request_one(202, GPIOF_OUT_INIT_LOW, NULL); /* LCD0_LED_CONT */
 
         /* Touchscreen */
-        gpio_request(GPIO_FN_IRQ10,     NULL); /* TP_INT */
+        gpio_request_one(166, GPIOF_OUT_INIT_HIGH, NULL); /* TP_RST_B */
 
         /* GETHER */
-        gpio_request(GPIO_FN_ET_CRS,            NULL);
-        gpio_request(GPIO_FN_ET_MDC,            NULL);
-        gpio_request(GPIO_FN_ET_MDIO,           NULL);
-        gpio_request(GPIO_FN_ET_TX_ER,          NULL);
-        gpio_request(GPIO_FN_ET_RX_ER,          NULL);
-        gpio_request(GPIO_FN_ET_ERXD0,          NULL);
-        gpio_request(GPIO_FN_ET_ERXD1,          NULL);
-        gpio_request(GPIO_FN_ET_ERXD2,          NULL);
-        gpio_request(GPIO_FN_ET_ERXD3,          NULL);
-        gpio_request(GPIO_FN_ET_TX_CLK,         NULL);
-        gpio_request(GPIO_FN_ET_TX_EN,          NULL);
-        gpio_request(GPIO_FN_ET_ETXD0,          NULL);
-        gpio_request(GPIO_FN_ET_ETXD1,          NULL);
-        gpio_request(GPIO_FN_ET_ETXD2,          NULL);
-        gpio_request(GPIO_FN_ET_ETXD3,          NULL);
-        gpio_request(GPIO_FN_ET_PHY_INT,        NULL);
-        gpio_request(GPIO_FN_ET_COL,            NULL);
-        gpio_request(GPIO_FN_ET_RX_DV,          NULL);
-        gpio_request(GPIO_FN_ET_RX_CLK,         NULL);
-
         gpio_request_one(18, GPIOF_OUT_INIT_HIGH, NULL); /* PHY_RST */
 
         /* USB */
@@ -1163,34 +1175,17 @@ static void __init eva_init(void)
         } else {
                 /* USB Func */
                 /*
-                 * A1 chip has 2 IRQ7 pin and it was controled by MSEL register.
-                 * OTOH, usbhs interrupt needs its value (HI/LOW) to decide
-                 * USB connection/disconnection (usbhsf_get_vbus()).
-                 * This means we needs to select GPIO_FN_IRQ7_PORT209 first,
-                 * and select GPIO 209 here
+                 * The USBHS interrupt handlers needs to read the IRQ pin value
+                 * (HI/LOW) to diffentiate USB connection and disconnection
+                 * events (usbhsf_get_vbus()). We thus need to select both the
+                 * intc_irq7_1 pin group and GPIO 209 here.
                  */
-                gpio_request(GPIO_FN_IRQ7_PORT209, NULL);
                 gpio_request_one(209, GPIOF_IN, NULL);
 
                 platform_device_register(&usbhsf_device);
                 usb = &usbhsf_device;
         }
 
-        /* CEU0 */
-        gpio_request(GPIO_FN_VIO0_D7,           NULL);
-        gpio_request(GPIO_FN_VIO0_D6,           NULL);
-        gpio_request(GPIO_FN_VIO0_D5,           NULL);
-        gpio_request(GPIO_FN_VIO0_D4,           NULL);
-        gpio_request(GPIO_FN_VIO0_D3,           NULL);
-        gpio_request(GPIO_FN_VIO0_D2,           NULL);
-        gpio_request(GPIO_FN_VIO0_D1,           NULL);
-        gpio_request(GPIO_FN_VIO0_D0,           NULL);
-        gpio_request(GPIO_FN_VIO0_CLK,          NULL);
-        gpio_request(GPIO_FN_VIO0_HD,           NULL);
-        gpio_request(GPIO_FN_VIO0_VD,           NULL);
-        gpio_request(GPIO_FN_VIO0_FIELD,        NULL);
-        gpio_request(GPIO_FN_VIO_CKO,           NULL);
-
         /* CON1/CON15 Camera */
         gpio_request_one(173, GPIOF_OUT_INIT_LOW, NULL);  /* STANDBY */
         gpio_request_one(172, GPIOF_OUT_INIT_HIGH, NULL); /* RST */
@@ -1198,24 +1193,11 @@ static void __init eva_init(void)
         gpio_request_one(158, GPIOF_OUT_INIT_LOW, NULL);  /* CAM_PON */
 
         /* FSI-WM8978 */
-        gpio_request(GPIO_FN_FSIAIBT,           NULL);
-        gpio_request(GPIO_FN_FSIAILR,           NULL);
-        gpio_request(GPIO_FN_FSIAOMC,           NULL);
-        gpio_request(GPIO_FN_FSIAOSLD,          NULL);
-        gpio_request(GPIO_FN_FSIAISLD_PORT5,    NULL);
-
         gpio_request(7, NULL);
         gpio_request(8, NULL);
         gpio_direction_none(GPIO_PORT7CR); /* FSIAOBT needs no direction */
         gpio_direction_none(GPIO_PORT8CR); /* FSIAOLR needs no direction */
 
-        /* FSI-HDMI */
-        gpio_request(GPIO_FN_FSIBCK,            NULL);
-
-        /* HDMI */
-        gpio_request(GPIO_FN_HDMI_HPD,          NULL);
-        gpio_request(GPIO_FN_HDMI_CEC,          NULL);
-
         /*
          * CAUTION
          *
diff --git a/arch/arm/mach-shmobile/board-bockw.c b/arch/arm/mach-shmobile/board-bockw.c
index 38e5e50fb318..2b6103e55c34 100644
--- a/arch/arm/mach-shmobile/board-bockw.c
+++ b/arch/arm/mach-shmobile/board-bockw.c
@@ -18,13 +18,32 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
 
+#include <linux/mfd/tmio.h>
+#include <linux/mmc/host.h>
+#include <linux/pinctrl/machine.h>
 #include <linux/platform_device.h>
+#include <linux/regulator/fixed.h>
+#include <linux/regulator/machine.h>
 #include <linux/smsc911x.h>
 #include <mach/common.h>
 #include <mach/irqs.h>
 #include <mach/r8a7778.h>
 #include <asm/mach/arch.h>
 
+/*
+ *      CN9(Upper side) SCIF/RCAN selection
+ *
+ *              1,4     3,6
+ * SW40         SCIF    RCAN
+ * SW41         SCIF    RCAN
+ */
+
+/* Dummy supplies, where voltage doesn't matter */
+static struct regulator_consumer_supply dummy_supplies[] = {
+        REGULATOR_SUPPLY("vddvario", "smsc911x"),
+        REGULATOR_SUPPLY("vdd33a", "smsc911x"),
+};
+
 static struct smsc911x_platform_config smsc911x_data = {
         .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
         .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
@@ -37,17 +56,43 @@ static struct resource smsc911x_resources[] = {
         DEFINE_RES_IRQ(irq_pin(0)), /* IRQ 0 */
 };
 
+/* SDHI */
+static struct sh_mobile_sdhi_info sdhi0_info = {
+        .tmio_caps      = MMC_CAP_SD_HIGHSPEED,
+        .tmio_ocr_mask  = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
+        .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT,
+};
+
+static const struct pinctrl_map bockw_pinctrl_map[] = {
+        /* SCIF0 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778",
+                                  "scif0_data_a", "scif0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778",
+                                  "scif0_ctrl", "scif0"),
+        /* SDHI0 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7778",
+                                  "sdhi0", "sdhi0"),
+};
+
+#define FPGA    0x18200000
 #define IRQ0MR  0x30
+#define PFC     0xfffc0000
+#define PUPR4   0x110
 static void __init bockw_init(void)
 {
-        void __iomem *fpga;
+        void __iomem *base;
 
         r8a7778_clock_init();
         r8a7778_init_irq_extpin(1);
         r8a7778_add_standard_devices();
 
-        fpga = ioremap_nocache(0x18200000, SZ_1M);
-        if (fpga) {
+        pinctrl_register_mappings(bockw_pinctrl_map,
+                                  ARRAY_SIZE(bockw_pinctrl_map));
+        r8a7778_pinmux_init();
+
+        /* for SMSC */
+        base = ioremap_nocache(FPGA, SZ_1M);
+        if (base) {
                 /*
                  * CAUTION
                  *
@@ -55,16 +100,33 @@ static void __init bockw_init(void)
                  * it should be cared in the future
                  * Now, it is assuming IRQ0 was used only from SMSC.
                  */
-                u16 val = ioread16(fpga + IRQ0MR);
+                u16 val = ioread16(base + IRQ0MR);
                 val &= ~(1 << 4); /* enable SMSC911x */
-                iowrite16(val, fpga + IRQ0MR);
-                iounmap(fpga);
+                iowrite16(val, base + IRQ0MR);
+                iounmap(base);
+
+                regulator_register_fixed(0, dummy_supplies,
+                                         ARRAY_SIZE(dummy_supplies));
 
                 platform_device_register_resndata(
                         &platform_bus, "smsc911x", -1,
                         smsc911x_resources, ARRAY_SIZE(smsc911x_resources),
                         &smsc911x_data, sizeof(smsc911x_data));
         }
+
+        /* for SDHI */
+        base = ioremap_nocache(PFC, 0x200);
+        if (base) {
+                /*
+                 * FIXME
+                 *
+                 * SDHI CD/WP pin needs pull-up
+                 */
+                iowrite32(ioread32(base + PUPR4) | (3 << 26), base + PUPR4);
+                iounmap(base);
+
+                r8a7778_sdhi_init(0, &sdhi0_info);
+        }
 }
 
 static const char *bockw_boards_compat_dt[] __initdata = {
diff --git a/arch/arm/mach-shmobile/board-bonito.c b/arch/arm/mach-shmobile/board-bonito.c
index 70d992c540ae..b373e9ced573 100644
--- a/arch/arm/mach-shmobile/board-bonito.c
+++ b/arch/arm/mach-shmobile/board-bonito.c
@@ -331,12 +331,6 @@ static struct platform_device smsc_device = {
 };
 
 /*
- * core board devices
- */
-static struct platform_device *bonito_core_devices[] __initdata = {
-};
-
-/*
  * base board devices
  */
 static struct platform_device *bonito_base_devices[] __initdata = {
@@ -375,12 +369,37 @@ static void __init bonito_map_io(void)
 #define VCCQ1CR         IOMEM(0xE6058140)
 #define VCCQ1LCDCR      IOMEM(0xE6058186)
 
+/*
+ * HACK: The FPGA mappings should be associated with the FPGA device, but we
+ * don't have one at the moment. Associate them with the PFC device to make
+ * sure they will be applied.
+ */
+static const struct pinctrl_map fpga_pinctrl_map[] = {
+        /* FPGA */
+        PIN_MAP_MUX_GROUP_DEFAULT("pfc-r8a7740", "pfc-r8a7740",
+                                  "bsc_cs5a_0", "bsc"),
+        PIN_MAP_MUX_GROUP_DEFAULT("pfc-r8a7740", "pfc-r8a7740",
+                                  "bsc_cs5b", "bsc"),
+        PIN_MAP_MUX_GROUP_DEFAULT("pfc-r8a7740", "pfc-r8a7740",
+                                  "bsc_cs6a", "bsc"),
+        PIN_MAP_MUX_GROUP_DEFAULT("pfc-r8a7740", "pfc-r8a7740",
+                                  "intc_irq10", "intc"),
+};
+
+static const struct pinctrl_map scifa5_pinctrl_map[] = {
+        /* SCIFA5 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.5", "pfc-r8a7740",
+                                  "scifa5_data_2", "scifa5"),
+};
+
 static void __init bonito_init(void)
 {
         u16 val;
 
         regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
 
+        pinctrl_register_mappings(fpga_pinctrl_map,
+                                  ARRAY_SIZE(fpga_pinctrl_map));
         r8a7740_pinmux_init();
         bonito_fpga_init();
 
@@ -397,9 +416,6 @@ static void __init bonito_init(void)
 
         r8a7740_add_standard_devices();
 
-        platform_add_devices(bonito_core_devices,
-                             ARRAY_SIZE(bonito_core_devices));
-
         /*
          * base board settings
          */
@@ -409,14 +425,6 @@ static void __init bonito_init(void)
                 u16 bsw3;
                 u16 bsw4;
 
-                /*
-                 * FPGA
-                 */
-                gpio_request(GPIO_FN_CS5B,              NULL);
-                gpio_request(GPIO_FN_CS6A,              NULL);
-                gpio_request(GPIO_FN_CS5A_PORT105,      NULL);
-                gpio_request(GPIO_FN_IRQ10,             NULL);
-
                 val = bonito_fpga_read(BVERR);
                 pr_info("bonito version: cpu %02x, base %02x\n",
                         ((val >> 8) & 0xFF),
@@ -432,8 +440,8 @@ static void __init bonito_init(void)
                 if (BIT_OFF(bsw2, 1) && /* S38.3 = ON */
                     BIT_OFF(bsw3, 9) && /* S39.6 = ON */
                     BIT_OFF(bsw4, 4)) { /* S43.1 = ON */
-                        gpio_request(GPIO_FN_SCIFA5_TXD_PORT91, NULL);
-                        gpio_request(GPIO_FN_SCIFA5_RXD_PORT92, NULL);
+                        pinctrl_register_mappings(scifa5_pinctrl_map,
+                                                  ARRAY_SIZE(scifa5_pinctrl_map));
                 }
 
                 /*
@@ -443,7 +451,6 @@ static void __init bonito_init(void)
                     BIT_ON(bsw2, 2)) {  /* S38.2 = OFF */
                         pinctrl_register_mappings(lcdc0_pinctrl_map,
                                                   ARRAY_SIZE(lcdc0_pinctrl_map));
-                        gpio_request(GPIO_FN_LCDC0_SELECT, NULL);
 
                         gpio_request_one(61, GPIOF_OUT_INIT_HIGH,
                                          NULL); /* LCDDON */
diff --git a/arch/arm/mach-shmobile/board-kzm9d.c b/arch/arm/mach-shmobile/board-kzm9d.c
index c016ccd92433..4368000e1127 100644
--- a/arch/arm/mach-shmobile/board-kzm9d.c
+++ b/arch/arm/mach-shmobile/board-kzm9d.c
@@ -56,7 +56,7 @@ static struct smsc911x_platform_config smsc911x_platdata = {
 
 static struct platform_device smsc91x_device = {
         .name   = "smsc911x",
-        .id     = 0,
+        .id     = -1,
         .dev    = {
                   .platform_data = &smsc911x_platdata,
                 },
diff --git a/arch/arm/mach-shmobile/board-kzm9g-reference.c b/arch/arm/mach-shmobile/board-kzm9g-reference.c
index aefa50d385b7..44055fe8a45c 100644
--- a/arch/arm/mach-shmobile/board-kzm9g-reference.c
+++ b/arch/arm/mach-shmobile/board-kzm9g-reference.c
@@ -79,7 +79,6 @@ static void __init kzm_init(void)
         sh73a0_pinmux_init();
 
         /* enable SD */
-        gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL);
         gpio_request_one(15, GPIOF_OUT_INIT_HIGH, NULL); /* power */
 
         gpio_request_one(14, GPIOF_OUT_INIT_HIGH, NULL); /* power */
diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c
index e6b775a10aad..165483c9bee2 100644
--- a/arch/arm/mach-shmobile/board-kzm9g.c
+++ b/arch/arm/mach-shmobile/board-kzm9g.c
@@ -29,6 +29,7 @@
 #include <linux/mmc/host.h>
 #include <linux/mmc/sh_mmcif.h>
 #include <linux/mmc/sh_mobile_sdhi.h>
+#include <linux/mfd/as3711.h>
 #include <linux/mfd/tmio.h>
 #include <linux/pinctrl/machine.h>
 #include <linux/pinctrl/pinconf-generic.h>
@@ -606,6 +607,140 @@ static struct platform_device fsi_ak4648_device = {
 };
 
 /* I2C */
+
+/* StepDown1 is used to supply 1.315V to the CPU */
+static struct regulator_init_data as3711_sd1 = {
+        .constraints = {
+                .name = "1.315V CPU",
+                .boot_on = 1,
+                .always_on = 1,
+                .min_uV = 1315000,
+                .max_uV = 1335000,
+        },
+};
+
+/* StepDown2 is used to supply 1.8V to the CPU and to the board */
+static struct regulator_init_data as3711_sd2 = {
+        .constraints = {
+                .name = "1.8V",
+                .boot_on = 1,
+                .always_on = 1,
+                .min_uV = 1800000,
+                .max_uV = 1800000,
+        },
+};
+
+/*
+ * StepDown3 is switched in parallel with StepDown2, seems to be off,
+ * according to read-back pre-set register values
+ */
+
+/* StepDown4 is used to supply 1.215V to the CPU and to the board */
+static struct regulator_init_data as3711_sd4 = {
+        .constraints = {
+                .name = "1.215V",
+                .boot_on = 1,
+                .always_on = 1,
+                .min_uV = 1215000,
+                .max_uV = 1235000,
+        },
+};
+
+/* LDO1 is unused and unconnected */
+
+/* LDO2 is used to supply 2.8V to the CPU */
+static struct regulator_init_data as3711_ldo2 = {
+        .constraints = {
+                .name = "2.8V CPU",
+                .boot_on = 1,
+                .always_on = 1,
+                .min_uV = 2800000,
+                .max_uV = 2800000,
+        },
+};
+
+/* LDO3 is used to supply 3.0V to the CPU */
+static struct regulator_init_data as3711_ldo3 = {
+        .constraints = {
+                .name = "3.0V CPU",
+                .boot_on = 1,
+                .always_on = 1,
+                .min_uV = 3000000,
+                .max_uV = 3000000,
+        },
+};
+
+/* LDO4 is used to supply 2.8V to the board */
+static struct regulator_init_data as3711_ldo4 = {
+        .constraints = {
+                .name = "2.8V",
+                .boot_on = 1,
+                .always_on = 1,
+                .min_uV = 2800000,
+                .max_uV = 2800000,
+        },
+};
+
+/* LDO5 is switched parallel to LDO4, also set to 2.8V */
+static struct regulator_init_data as3711_ldo5 = {
+        .constraints = {
+                .name = "2.8V #2",
+                .boot_on = 1,
+                .always_on = 1,
+                .min_uV = 2800000,
+                .max_uV = 2800000,
+        },
+};
+
+/* LDO6 is unused and unconnected */
+
+/* LDO7 is used to supply 1.15V to the CPU */
+static struct regulator_init_data as3711_ldo7 = {
+        .constraints = {
+                .name = "1.15V CPU",
+                .boot_on = 1,
+                .always_on = 1,
+                .min_uV = 1150000,
+                .max_uV = 1150000,
+        },
+};
+
+/* LDO8 is switched parallel to LDO7, also set to 1.15V */
+static struct regulator_init_data as3711_ldo8 = {
+        .constraints = {
+                .name = "1.15V CPU #2",
+                .boot_on = 1,
+                .always_on = 1,
+                .min_uV = 1150000,
+                .max_uV = 1150000,
+        },
+};
+
+static struct as3711_platform_data as3711_pdata = {
+        .regulator      = {
+                .init_data      = {
+                        [AS3711_REGULATOR_SD_1] = &as3711_sd1,
+                        [AS3711_REGULATOR_SD_2] = &as3711_sd2,
+                        [AS3711_REGULATOR_SD_4] = &as3711_sd4,
+                        [AS3711_REGULATOR_LDO_2] = &as3711_ldo2,
+                        [AS3711_REGULATOR_LDO_3] = &as3711_ldo3,
+                        [AS3711_REGULATOR_LDO_4] = &as3711_ldo4,
+                        [AS3711_REGULATOR_LDO_5] = &as3711_ldo5,
+                        [AS3711_REGULATOR_LDO_7] = &as3711_ldo7,
+                        [AS3711_REGULATOR_LDO_8] = &as3711_ldo8,
+                },
+        },
+        .backlight      = {
+                .su2_fb = "sh_mobile_lcdc_fb.0",
+                .su2_max_uA = 36000,
+                .su2_feedback = AS3711_SU2_CURR_AUTO,
+                .su2_fbprot = AS3711_SU2_GPIO4,
+                .su2_auto_curr1 = true,
+                .su2_auto_curr2 = true,
+                .su2_auto_curr3 = true,
+        },
+};
+
 static struct pcf857x_platform_data pcf8575_pdata = {
         .gpio_base      = GPIO_PCF8575_BASE,
 };
@@ -625,6 +760,11 @@ static struct i2c_board_info i2c0_devices[] = {
                 I2C_BOARD_INFO("adxl34x", 0x1d),
                 .irq = irq_pin(26), /* IRQ26 */
         },
+        {
+                I2C_BOARD_INFO("as3711", 0x40),
+                .irq = intcs_evt2irq(0x3300), /* IRQ24 */
+                .platform_data = &as3711_pdata,
+        },
 };
 
 static struct i2c_board_info i2c1_devices[] = {
@@ -663,13 +803,13 @@ static unsigned long pin_pullup_conf[] = {
 
 static const struct pinctrl_map kzm_pinctrl_map[] = {
         /* FSIA (AK4648) */
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2", "pfc-sh73a0",
                                   "fsia_mclk_in", "fsia"),
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2", "pfc-sh73a0",
                                   "fsia_sclk_in", "fsia"),
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2", "pfc-sh73a0",
                                   "fsia_data_in", "fsia"),
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2", "pfc-sh73a0",
                                   "fsia_data_out", "fsia"),
         /* I2C3 */
         PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.3", "pfc-sh73a0",
@@ -715,59 +855,6 @@ static const struct pinctrl_map kzm_pinctrl_map[] = {
                                   "usb_vbus", "usb"),
 };
 
-/*
- * FIXME
- *
- * This is quick hack for enabling LCDC backlight
- */
-static int __init as3711_enable_lcdc_backlight(void)
-{
-        struct i2c_adapter *a = i2c_get_adapter(0);
-        struct i2c_msg msg;
-        int i, ret;
-        __u8 magic[] = {
-                0x40, 0x2a,
-                0x43, 0x3c,
-                0x44, 0x3c,
-                0x45, 0x3c,
-                0x54, 0x03,
-                0x51, 0x00,
-                0x51, 0x01,
-                0xff, 0x00, /* wait */
-                0x43, 0xf0,
-                0x44, 0xf0,
-                0x45, 0xf0,
-        };
-
-        if (!of_machine_is_compatible("renesas,kzm9g"))
-                return 0;
-
-        if (!a)
-                return 0;
-
-        msg.addr        = 0x40;
-        msg.len         = 2;
-        msg.flags       = 0;
-
-        for (i = 0; i < ARRAY_SIZE(magic); i += 2) {
-                msg.buf = magic + i;
-
-                if (0xff == msg.buf[0]) {
-                        udelay(500);
-                        continue;
-                }
-
-                ret = i2c_transfer(a, &msg, 1);
-                if (ret < 0) {
-                        pr_err("i2c transfer fail\n");
-                        break;
-                }
-        }
-
-        return 0;
-}
-device_initcall(as3711_enable_lcdc_backlight);
-
 static void __init kzm_init(void)
 {
         regulator_register_always_on(2, "fixed-1.8V", fixed1v8_power_consumers,
@@ -788,9 +875,6 @@ static void __init kzm_init(void)
         /* Touchscreen */
         gpio_request_one(223, GPIOF_IN, NULL); /* IRQ8 */
 
-        /* enable SD */
-        gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL);
-
 #ifdef CONFIG_CACHE_L2X0
         /* Early BRESP enable, Shared attribute override enable, 64K*8way */
         l2x0_init(IOMEM(0xf0100000), 0x40460000, 0x82000fff);
diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c
index f587187a8603..d73e21d3ea8a 100644
--- a/arch/arm/mach-shmobile/board-lager.c
+++ b/arch/arm/mach-shmobile/board-lager.c
@@ -18,19 +18,83 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
 
+#include <linux/gpio.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
 #include <linux/interrupt.h>
 #include <linux/irqchip.h>
 #include <linux/kernel.h>
+#include <linux/leds.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/platform_data/gpio-rcar.h>
 #include <linux/platform_device.h>
 #include <mach/common.h>
 #include <mach/r8a7790.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
+/* LEDS */
+static struct gpio_led lager_leds[] = {
+        {
+                .name           = "led8",
+                .gpio           = RCAR_GP_PIN(5, 17),
+                .default_state  = LEDS_GPIO_DEFSTATE_ON,
+        }, {
+                .name           = "led7",
+                .gpio           = RCAR_GP_PIN(4, 23),
+                .default_state  = LEDS_GPIO_DEFSTATE_ON,
+        }, {
+                .name           = "led6",
+                .gpio           = RCAR_GP_PIN(4, 22),
+                .default_state  = LEDS_GPIO_DEFSTATE_ON,
+        },
+};
+
+static __initdata struct gpio_led_platform_data lager_leds_pdata = {
+        .leds           = lager_leds,
+        .num_leds       = ARRAY_SIZE(lager_leds),
+};
+
+/* GPIO KEY */
+#define GPIO_KEY(c, g, d, ...) \
+        { .code = c, .gpio = g, .desc = d, .active_low = 1 }
+
+static __initdata struct gpio_keys_button gpio_buttons[] = {
+        GPIO_KEY(KEY_4,         RCAR_GP_PIN(1, 28),     "SW2-pin4"),
+        GPIO_KEY(KEY_3,         RCAR_GP_PIN(1, 26),     "SW2-pin3"),
+        GPIO_KEY(KEY_2,         RCAR_GP_PIN(1, 24),     "SW2-pin2"),
+        GPIO_KEY(KEY_1,         RCAR_GP_PIN(1, 14),     "SW2-pin1"),
+};
+
+static __initdata struct gpio_keys_platform_data lager_keys_pdata = {
+        .buttons        = gpio_buttons,
+        .nbuttons       = ARRAY_SIZE(gpio_buttons),
+};
+
+static const struct pinctrl_map lager_pinctrl_map[] = {
+        /* SCIF0 (CN19: DEBUG SERIAL0) */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.6", "pfc-r8a7790",
+                                  "scif0_data", "scif0"),
+        /* SCIF1 (CN20: DEBUG SERIAL1) */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.7", "pfc-r8a7790",
+                                  "scif1_data", "scif1"),
+};
+
 static void __init lager_add_standard_devices(void)
 {
         r8a7790_clock_init();
+
+        pinctrl_register_mappings(lager_pinctrl_map,
+                                  ARRAY_SIZE(lager_pinctrl_map));
+        r8a7790_pinmux_init();
+
         r8a7790_add_standard_devices();
+        platform_device_register_data(&platform_bus, "leds-gpio", -1,
+                                      &lager_leds_pdata,
+                                      sizeof(lager_leds_pdata));
+        platform_device_register_data(&platform_bus, "gpio-keys", -1,
+                                      &lager_keys_pdata,
+                                      sizeof(lager_keys_pdata));
 }
 
 static const char *lager_boards_compat_dt[] __initdata = {
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index fa3407da682a..85f51a849a50 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -1309,6 +1309,49 @@ static struct i2c_board_info i2c1_devices[] = {
 };
 
 static const struct pinctrl_map mackerel_pinctrl_map[] = {
+        /* ADXL34X */
+        PIN_MAP_MUX_GROUP_DEFAULT("1-0053", "pfc-sh7372",
+                                  "intc_irq21", "intc"),
+        /* CEU */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372",
+                                  "ceu_data_0_7", "ceu"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372",
+                                  "ceu_clk_0", "ceu"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372",
+                                  "ceu_sync", "ceu"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372",
+                                  "ceu_field", "ceu"),
+        /* FLCTL */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_flctl.0", "pfc-sh7372",
+                                  "flctl_data", "flctl"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_flctl.0", "pfc-sh7372",
+                                  "flctl_ce0", "flctl"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_flctl.0", "pfc-sh7372",
+                                  "flctl_ctrl", "flctl"),
+        /* FSIA (AK4643) */
+        PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372",
+                                  "fsia_sclk_in", "fsia"),
+        PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372",
+                                  "fsia_data_in", "fsia"),
+        PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372",
+                                  "fsia_data_out", "fsia"),
+        /* FSIB (HDMI) */
+        PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.1", "pfc-sh7372",
+                                  "fsib_mclk_in", "fsib"),
+        /* HDMI */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-mobile-hdmi", "pfc-sh7372",
+                                  "hdmi", "hdmi"),
+        /* LCDC */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh7372",
+                                  "lcd_data24", "lcd"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh7372",
+                                  "lcd_sync", "lcd"),
+        /* SCIFA0 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-sh7372",
+                                  "scifa0_data", "scifa0"),
+        /* SCIFA2 (GT-720F GPS module) */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh7372",
+                                  "scifa2_data", "scifa2"),
         /* SDHI0 */
         PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
                                   "sdhi0_data4", "sdhi0"),
@@ -1316,6 +1359,8 @@ static const struct pinctrl_map mackerel_pinctrl_map[] = {
                                   "sdhi0_ctrl", "sdhi0"),
         PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
                                   "sdhi0_wp", "sdhi0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
+                                  "intc_irq26_1", "intc"),
         /* SDHI1 */
 #if !IS_ENABLED(CONFIG_MMC_SH_MMCIF)
         PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372",
@@ -1334,6 +1379,25 @@ static const struct pinctrl_map mackerel_pinctrl_map[] = {
                                   "sdhi2_data4", "sdhi2"),
         PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh7372",
                                   "sdhi2_ctrl", "sdhi2"),
+        /* SMSC911X */
+        PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-sh7372",
+                                  "bsc_cs5a", "bsc"),
+        PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-sh7372",
+                                  "intc_irq6_0", "intc"),
+        /* ST1232 */
+        PIN_MAP_MUX_GROUP_DEFAULT("0-0055", "pfc-sh7372",
+                                  "intc_irq7_0", "intc"),
+        /* TCA6416 */
+        PIN_MAP_MUX_GROUP_DEFAULT("0-0020", "pfc-sh7372",
+                                  "intc_irq9_0", "intc"),
+        /* USBHS0 */
+        PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs.0", "pfc-sh7372",
+                                  "usb0_vbus", "usb0"),
+        /* USBHS1 */
+        PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs.1", "pfc-sh7372",
+                                  "usb1_vbus", "usb1"),
+        PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs.1", "pfc-sh7372",
+                                  "usb1_otg_id_0", "usb1"),
 };
 
 #define GPIO_PORT9CR    IOMEM(0xE6051009)
@@ -1377,61 +1441,18 @@ static void __init mackerel_init(void)
                                   ARRAY_SIZE(mackerel_pinctrl_map));
         sh7372_pinmux_init();
 
-        /* enable SCIFA0 */
-        gpio_request(GPIO_FN_SCIFA0_TXD, NULL);
-        gpio_request(GPIO_FN_SCIFA0_RXD, NULL);
-
-        /* enable SMSC911X */
-        gpio_request(GPIO_FN_CS5A,      NULL);
-        gpio_request(GPIO_FN_IRQ6_39,   NULL);
-
-        /* LCDC */
-        gpio_request(GPIO_FN_LCDD23,   NULL);
-        gpio_request(GPIO_FN_LCDD22,   NULL);
-        gpio_request(GPIO_FN_LCDD21,   NULL);
-        gpio_request(GPIO_FN_LCDD20,   NULL);
-        gpio_request(GPIO_FN_LCDD19,   NULL);
-        gpio_request(GPIO_FN_LCDD18,   NULL);
-        gpio_request(GPIO_FN_LCDD17,   NULL);
-        gpio_request(GPIO_FN_LCDD16,   NULL);
-        gpio_request(GPIO_FN_LCDD15,   NULL);
-        gpio_request(GPIO_FN_LCDD14,   NULL);
-        gpio_request(GPIO_FN_LCDD13,   NULL);
-        gpio_request(GPIO_FN_LCDD12,   NULL);
-        gpio_request(GPIO_FN_LCDD11,   NULL);
-        gpio_request(GPIO_FN_LCDD10,   NULL);
-        gpio_request(GPIO_FN_LCDD9,    NULL);
-        gpio_request(GPIO_FN_LCDD8,    NULL);
-        gpio_request(GPIO_FN_LCDD7,    NULL);
-        gpio_request(GPIO_FN_LCDD6,    NULL);
-        gpio_request(GPIO_FN_LCDD5,    NULL);
-        gpio_request(GPIO_FN_LCDD4,    NULL);
-        gpio_request(GPIO_FN_LCDD3,    NULL);
-        gpio_request(GPIO_FN_LCDD2,    NULL);
-        gpio_request(GPIO_FN_LCDD1,    NULL);
-        gpio_request(GPIO_FN_LCDD0,    NULL);
-        gpio_request(GPIO_FN_LCDDISP,  NULL);
-        gpio_request(GPIO_FN_LCDDCK,   NULL);
-
         /* backlight, off by default */
         gpio_request_one(31, GPIOF_OUT_INIT_LOW, NULL);
 
         gpio_request_one(151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
 
         /* USBHS0 */
-        gpio_request(GPIO_FN_VBUS0_0, NULL);
         gpio_request_pulldown(GPIO_PORT168CR); /* VBUS0_0 pull down */
 
         /* USBHS1 */
-        gpio_request(GPIO_FN_VBUS0_1, NULL);
         gpio_request_pulldown(GPIO_PORT167CR); /* VBUS0_1 pull down */
-        gpio_request(GPIO_FN_IDIN_1_113, NULL);
 
-        /* enable FSI2 port A (ak4643) */
-        gpio_request(GPIO_FN_FSIAIBT,   NULL);
-        gpio_request(GPIO_FN_FSIAILR,   NULL);
-        gpio_request(GPIO_FN_FSIAISLD,  NULL);
-        gpio_request(GPIO_FN_FSIAOSLD,  NULL);
+        /* FSI2 port A (ak4643) */
         gpio_request_one(161, GPIOF_OUT_INIT_LOW, NULL); /* slave */
 
         gpio_request(9,  NULL);
@@ -1441,8 +1462,7 @@ static void __init mackerel_init(void)
 
         intc_set_priority(IRQ_FSI, 3); /* irq priority FSI(3) > SMSC911X(2) */
 
-        /* setup FSI2 port B (HDMI) */
-        gpio_request(GPIO_FN_FSIBCK, NULL);
+        /* FSI2 port B (HDMI) */
         __raw_writew(__raw_readw(USCCR1) & ~(1 << 6), USCCR1); /* use SPDIF */
 
         /* set SPU2 clock to 119.6 MHz */
@@ -1452,68 +1472,15 @@ static void __init mackerel_init(void)
                 clk_put(clk);
         }
 
-        /* enable Keypad */
-        gpio_request(GPIO_FN_IRQ9_42,   NULL);
+        /* Keypad */
         irq_set_irq_type(IRQ9, IRQ_TYPE_LEVEL_HIGH);
 
-        /* enable Touchscreen */
-        gpio_request(GPIO_FN_IRQ7_40,   NULL);
+        /* Touchscreen */
         irq_set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW);
 
-        /* enable Accelerometer */
-        gpio_request(GPIO_FN_IRQ21,     NULL);
+        /* Accelerometer */
         irq_set_irq_type(IRQ21, IRQ_TYPE_LEVEL_HIGH);
 
-        /* SDHI0 PORT172 card-detect IRQ26 */
-        gpio_request(GPIO_FN_IRQ26_172, NULL);
-
-        /* FLCTL */
-        gpio_request(GPIO_FN_D0_NAF0, NULL);
-        gpio_request(GPIO_FN_D1_NAF1, NULL);
-        gpio_request(GPIO_FN_D2_NAF2, NULL);
-        gpio_request(GPIO_FN_D3_NAF3, NULL);
-        gpio_request(GPIO_FN_D4_NAF4, NULL);
-        gpio_request(GPIO_FN_D5_NAF5, NULL);
-        gpio_request(GPIO_FN_D6_NAF6, NULL);
-        gpio_request(GPIO_FN_D7_NAF7, NULL);
-        gpio_request(GPIO_FN_D8_NAF8, NULL);
-        gpio_request(GPIO_FN_D9_NAF9, NULL);
-        gpio_request(GPIO_FN_D10_NAF10, NULL);
-        gpio_request(GPIO_FN_D11_NAF11, NULL);
-        gpio_request(GPIO_FN_D12_NAF12, NULL);
-        gpio_request(GPIO_FN_D13_NAF13, NULL);
-        gpio_request(GPIO_FN_D14_NAF14, NULL);
-        gpio_request(GPIO_FN_D15_NAF15, NULL);
-        gpio_request(GPIO_FN_FCE0, NULL);
-        gpio_request(GPIO_FN_WE0_FWE, NULL);
-        gpio_request(GPIO_FN_FRB, NULL);
-        gpio_request(GPIO_FN_A4_FOE, NULL);
-        gpio_request(GPIO_FN_A5_FCDE, NULL);
-        gpio_request(GPIO_FN_RD_FSC, NULL);
-
-        /* enable GPS module (GT-720F) */
-        gpio_request(GPIO_FN_SCIFA2_TXD1, NULL);
-        gpio_request(GPIO_FN_SCIFA2_RXD1, NULL);
-
-        /* CEU */
-        gpio_request(GPIO_FN_VIO_CLK, NULL);
-        gpio_request(GPIO_FN_VIO_VD, NULL);
-        gpio_request(GPIO_FN_VIO_HD, NULL);
-        gpio_request(GPIO_FN_VIO_FIELD, NULL);
-        gpio_request(GPIO_FN_VIO_CKO, NULL);
-        gpio_request(GPIO_FN_VIO_D7, NULL);
-        gpio_request(GPIO_FN_VIO_D6, NULL);
-        gpio_request(GPIO_FN_VIO_D5, NULL);
-        gpio_request(GPIO_FN_VIO_D4, NULL);
-        gpio_request(GPIO_FN_VIO_D3, NULL);
-        gpio_request(GPIO_FN_VIO_D2, NULL);
-        gpio_request(GPIO_FN_VIO_D1, NULL);
-        gpio_request(GPIO_FN_VIO_D0, NULL);
-
-        /* HDMI */
-        gpio_request(GPIO_FN_HDMI_HPD, NULL);
-        gpio_request(GPIO_FN_HDMI_CEC, NULL);
-
         /* Reset HDMI, must be held at least one EXTALR (32768Hz) period */
         srcr4 = __raw_readl(SRCR4);
         __raw_writel(srcr4 | (1 << 13), SRCR4);
diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
index b9594e911ce7..a3810b03297c 100644
--- a/arch/arm/mach-shmobile/board-marzen.c
+++ b/arch/arm/mach-shmobile/board-marzen.c
@@ -28,6 +28,7 @@
 #include <linux/leds.h>
 #include <linux/dma-mapping.h>
 #include <linux/pinctrl/machine.h>
+#include <linux/platform_data/gpio-rcar.h>
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
 #include <linux/smsc911x.h>
@@ -68,7 +69,7 @@ static struct resource smsc911x_resources[] = {
                 .flags          = IORESOURCE_MEM,
         },
         [1] = {
-                .start          = gic_iid(0x3c), /* IRQ 1 */
+                .start          = irq_pin(1), /* IRQ 1 */
                 .flags          = IORESOURCE_IRQ,
         },
 };
@@ -173,15 +174,15 @@ static struct platform_device usb_phy_device = {
 static struct gpio_led marzen_leds[] = {
         {
                 .name           = "led2",
-                .gpio           = 157,
+                .gpio           = RCAR_GP_PIN(4, 29),
                 .default_state  = LEDS_GPIO_DEFSTATE_ON,
         }, {
                 .name           = "led3",
-                .gpio           = 158,
+                .gpio           = RCAR_GP_PIN(4, 30),
                 .default_state  = LEDS_GPIO_DEFSTATE_ON,
         }, {
                 .name           = "led4",
-                .gpio           = 159,
+                .gpio           = RCAR_GP_PIN(4, 31),
                 .default_state  = LEDS_GPIO_DEFSTATE_ON,
         },
 };
@@ -349,7 +350,7 @@ static struct platform_device *marzen_late_devices[] __initdata = {
         &ohci1_device,
 };
 
-void __init marzen_init_late(void)
+static void __init marzen_init_late(void)
 {
         /* get usb phy */
         phy = usb_get_phy(USB_PHY_TYPE_USB2);
@@ -404,6 +405,7 @@ static void __init marzen_init(void)
         pinctrl_register_mappings(marzen_pinctrl_map,
                                   ARRAY_SIZE(marzen_pinctrl_map));
         r8a7779_pinmux_init();
+        r8a7779_init_irq_extpin(1); /* IRQ1 as individual interrupt */
 
         r8a7779_add_standard_devices();
         platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices));
diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c
index e710c00c3822..f6227bb10aca 100644
--- a/arch/arm/mach-shmobile/clock-r8a73a4.c
+++ b/arch/arm/mach-shmobile/clock-r8a73a4.c
@@ -22,15 +22,43 @@
 #include <linux/kernel.h>
 #include <linux/sh_clk.h>
 #include <linux/clkdev.h>
+#include <mach/clock.h>
 #include <mach/common.h>
 
 #define CPG_BASE 0xe6150000
 #define CPG_LEN 0x270
 
-#define MPCKCR 0xe6150080
 #define SMSTPCR2 0xe6150138
 #define SMSTPCR5 0xe6150144
 
+#define FRQCRA          0xE6150000
+#define FRQCRB          0xE6150004
+#define VCLKCR1         0xE6150008
+#define VCLKCR2         0xE615000C
+#define VCLKCR3         0xE615001C
+#define VCLKCR4         0xE6150014
+#define VCLKCR5         0xE6150034
+#define ZBCKCR          0xE6150010
+#define SD0CKCR         0xE6150074
+#define SD1CKCR         0xE6150078
+#define SD2CKCR         0xE615007C
+#define MMC0CKCR        0xE6150240
+#define MMC1CKCR        0xE6150244
+#define FSIACKCR        0xE6150018
+#define FSIBCKCR        0xE6150090
+#define MPCKCR          0xe6150080
+#define SPUVCKCR        0xE6150094
+#define HSICKCR         0xE615026C
+#define M4CKCR          0xE6150098
+#define PLLECR          0xE61500D0
+#define PLL1CR          0xE6150028
+#define PLL2CR          0xE615002C
+#define PLL2SCR         0xE61501F4
+#define PLL2HCR         0xE61501E4
+#define CKSCR           0xE61500C0
+
+#define CPG_MAP(o) ((o - CPG_BASE) + cpg_mapping.base)
+
 static struct clk_mapping cpg_mapping = {
         .phys   = CPG_BASE,
         .len    = CPG_LEN,
@@ -51,29 +79,326 @@ static struct clk extal2_clk = {
         .mapping        = &cpg_mapping,
 };
 
+static struct sh_clk_ops followparent_clk_ops = {
+        .recalc = followparent_recalc,
+};
+
+static struct clk main_clk = {
+        /* .parent will be set r8a73a4_clock_init */
+        .ops    = &followparent_clk_ops,
+};
+
+SH_CLK_RATIO(div2,      1, 2);
+SH_CLK_RATIO(div4,      1, 4);
+
+SH_FIXED_RATIO_CLK(main_div2_clk,       main_clk,               div2);
+SH_FIXED_RATIO_CLK(extal1_div2_clk,     extal1_clk,             div2);
+SH_FIXED_RATIO_CLK(extal2_div2_clk,     extal2_clk,             div2);
+SH_FIXED_RATIO_CLK(extal2_div4_clk,     extal2_clk,             div4);
+
+/* External FSIACK/FSIBCK clock */
+static struct clk fsiack_clk = {
+};
+
+static struct clk fsibck_clk = {
+};
+
+/*
+ *              PLL clocks
+ */
+static struct clk *pll_parent_main[] = {
+        [0] = &main_clk,
+        [1] = &main_div2_clk
+};
+
+static struct clk *pll_parent_main_extal[8] = {
+        [0] = &main_div2_clk,
+        [1] = &extal2_div2_clk,
+        [3] = &extal2_div4_clk,
+        [4] = &main_clk,
+        [5] = &extal2_clk,
+};
+
+static unsigned long pll_recalc(struct clk *clk)
+{
+        unsigned long mult = 1;
+
+        if (ioread32(CPG_MAP(PLLECR)) & (1 << clk->enable_bit))
+                mult = (((ioread32(clk->mapped_reg) >> 24) & 0x7f) + 1);
+
+        return clk->parent->rate * mult;
+}
+
+static int pll_set_parent(struct clk *clk, struct clk *parent)
+{
+        u32 val;
+        int i, ret;
+
+        if (!clk->parent_table || !clk->parent_num)
+                return -EINVAL;
+
+        /* Search the parent */
+        for (i = 0; i < clk->parent_num; i++)
+                if (clk->parent_table[i] == parent)
+                        break;
+
+        if (i == clk->parent_num)
+                return -ENODEV;
+
+        ret = clk_reparent(clk, parent);
+        if (ret < 0)
+                return ret;
+
+        val = ioread32(clk->mapped_reg) &
+                ~(((1 << clk->src_width) - 1) << clk->src_shift);
+
+        iowrite32(val | i << clk->src_shift, clk->mapped_reg);
+
+        return 0;
+}
+
+static struct sh_clk_ops pll_clk_ops = {
+        .recalc         = pll_recalc,
+        .set_parent     = pll_set_parent,
+};
+
+#define PLL_CLOCK(name, p, pt, w, s, reg, e)            \
+        static struct clk name = {                      \
+                .ops            = &pll_clk_ops,         \
+                .flags          = CLK_ENABLE_ON_INIT,   \
+                .parent         = p,                    \
+                .parent_table   = pt,                   \
+                .parent_num     = ARRAY_SIZE(pt),       \
+                .src_width      = w,                    \
+                .src_shift      = s,                    \
+                .enable_reg     = (void __iomem *)reg,  \
+                .enable_bit     = e,                    \
+                .mapping        = &cpg_mapping,         \
+        }
+
+PLL_CLOCK(pll1_clk,  &main_clk,      pll_parent_main,       1, 7, PLL1CR,  1);
+PLL_CLOCK(pll2_clk,  &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2CR,  2);
+PLL_CLOCK(pll2s_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2SCR, 4);
+PLL_CLOCK(pll2h_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2HCR, 5);
+
+SH_FIXED_RATIO_CLK(pll1_div2_clk,       pll1_clk,       div2);
+
 static struct clk *main_clks[] = {
         &extalr_clk,
         &extal1_clk,
+        &extal1_div2_clk,
         &extal2_clk,
+        &extal2_div2_clk,
+        &extal2_div4_clk,
+        &main_clk,
+        &main_div2_clk,
+        &fsiack_clk,
+        &fsibck_clk,
+        &pll1_clk,
+        &pll1_div2_clk,
+        &pll2_clk,
+        &pll2s_clk,
+        &pll2h_clk,
+};
+
+/* DIV4 */
+static void div4_kick(struct clk *clk)
+{
+        unsigned long value;
+
+        /* set KICK bit in FRQCRB to update hardware setting */
+        value = ioread32(CPG_MAP(FRQCRB));
+        value |= (1 << 31);
+        iowrite32(value, CPG_MAP(FRQCRB));
+}
+
+static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10};
+
+static struct clk_div_mult_table div4_div_mult_table = {
+        .divisors       = divisors,
+        .nr_divisors    = ARRAY_SIZE(divisors),
+};
+
+static struct clk_div4_table div4_table = {
+        .div_mult_table = &div4_div_mult_table,
+        .kick           = div4_kick,
+};
+
+enum {
+        DIV4_I, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2,
+        DIV4_ZX, DIV4_ZS, DIV4_HP,
+        DIV4_NR };
+
+static struct clk div4_clks[DIV4_NR] = {
+        [DIV4_I]        = SH_CLK_DIV4(&pll1_clk, FRQCRA, 20, 0x0dff, CLK_ENABLE_ON_INIT),
+        [DIV4_M3]       = SH_CLK_DIV4(&pll1_clk, FRQCRA, 12, 0x1dff, CLK_ENABLE_ON_INIT),
+        [DIV4_B]        = SH_CLK_DIV4(&pll1_clk, FRQCRA,  8, 0x0dff, CLK_ENABLE_ON_INIT),
+        [DIV4_M1]       = SH_CLK_DIV4(&pll1_clk, FRQCRA,  4, 0x1dff, 0),
+        [DIV4_M2]       = SH_CLK_DIV4(&pll1_clk, FRQCRA,  0, 0x1dff, 0),
+        [DIV4_ZX]       = SH_CLK_DIV4(&pll1_clk, FRQCRB, 12, 0x0dff, 0),
+        [DIV4_ZS]       = SH_CLK_DIV4(&pll1_clk, FRQCRB,  8, 0x0dff, 0),
+        [DIV4_HP]       = SH_CLK_DIV4(&pll1_clk, FRQCRB,  4, 0x0dff, 0),
 };
 
 enum {
+        DIV6_ZB,
+        DIV6_SDHI0, DIV6_SDHI1, DIV6_SDHI2,
+        DIV6_MMC0, DIV6_MMC1,
+        DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_VCK4, DIV6_VCK5,
+        DIV6_FSIA, DIV6_FSIB,
+        DIV6_MP, DIV6_M4, DIV6_HSI, DIV6_SPUV,
+        DIV6_NR };
+
+static struct clk *div6_parents[8] = {
+        [0] = &pll1_div2_clk,
+        [1] = &pll2s_clk,
+        [3] = &extal2_clk,
+        [4] = &main_div2_clk,
+        [6] = &extalr_clk,
+};
+
+static struct clk *fsia_parents[4] = {
+        [0] = &pll1_div2_clk,
+        [1] = &pll2s_clk,
+        [2] = &fsiack_clk,
+};
+
+static struct clk *fsib_parents[4] = {
+        [0] = &pll1_div2_clk,
+        [1] = &pll2s_clk,
+        [2] = &fsibck_clk,
+};
+
+static struct clk *mp_parents[4] = {
+        [0] = &pll1_div2_clk,
+        [1] = &pll2s_clk,
+        [2] = &extal2_clk,
+        [3] = &extal2_clk,
+};
+
+static struct clk *m4_parents[2] = {
+        [0] = &pll2s_clk,
+};
+
+static struct clk *hsi_parents[4] = {
+        [0] = &pll2h_clk,
+        [1] = &pll1_div2_clk,
+        [3] = &pll2s_clk,
+};
+
+/*** FIXME ***
+ * SH_CLK_DIV6_EXT() macro doesn't care .mapping
+ * but, it is necessary on R-Car (= ioremap() base CPG)
+ * The difference between
+ * SH_CLK_DIV6_EXT() <--> SH_CLK_MAP_DIV6_EXT()
+ * is only .mapping
+ */
+#define SH_CLK_MAP_DIV6_EXT(_reg, _flags, _parents,                     \
+                            _num_parents, _src_shift, _src_width)       \
+{                                                                       \
+        .enable_reg     = (void __iomem *)_reg,                         \
+        .enable_bit     = 0, /* unused */                               \
+        .flags          = _flags | CLK_MASK_DIV_ON_DISABLE,             \
+        .div_mask       = SH_CLK_DIV6_MSK,                              \
+        .parent_table   = _parents,                                     \
+        .parent_num     = _num_parents,                                 \
+        .src_shift      = _src_shift,                                   \
+        .src_width      = _src_width,                                   \
+        .mapping        = &cpg_mapping,                                 \
+}
+
+static struct clk div6_clks[DIV6_NR] = {
+        [DIV6_ZB] = SH_CLK_MAP_DIV6_EXT(ZBCKCR, CLK_ENABLE_ON_INIT,
+                                div6_parents, 2, 7, 1),
+        [DIV6_SDHI0] = SH_CLK_MAP_DIV6_EXT(SD0CKCR, 0,
+                                div6_parents, 2, 6, 2),
+        [DIV6_SDHI1] = SH_CLK_MAP_DIV6_EXT(SD1CKCR, 0,
+                                div6_parents, 2, 6, 2),
+        [DIV6_SDHI2] = SH_CLK_MAP_DIV6_EXT(SD2CKCR, 0,
+                                div6_parents, 2, 6, 2),
+        [DIV6_MMC0] = SH_CLK_MAP_DIV6_EXT(MMC0CKCR, 0,
+                                div6_parents, 2, 6, 2),
+        [DIV6_MMC1] = SH_CLK_MAP_DIV6_EXT(MMC1CKCR, 0,
+                                div6_parents, 2, 6, 2),
+        [DIV6_VCK1] = SH_CLK_MAP_DIV6_EXT(VCLKCR1, 0, /* didn't care bit[6-7] */
+                                div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
+        [DIV6_VCK2] = SH_CLK_MAP_DIV6_EXT(VCLKCR2, 0, /* didn't care bit[6-7] */
+                                div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
+        [DIV6_VCK3] = SH_CLK_MAP_DIV6_EXT(VCLKCR3, 0, /* didn't care bit[6-7] */
+                                div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
+        [DIV6_VCK4] = SH_CLK_MAP_DIV6_EXT(VCLKCR4, 0, /* didn't care bit[6-7] */
+                                div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
+        [DIV6_VCK5] = SH_CLK_MAP_DIV6_EXT(VCLKCR5, 0, /* didn't care bit[6-7] */
+                                div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
+        [DIV6_FSIA] = SH_CLK_MAP_DIV6_EXT(FSIACKCR, 0,
+                                fsia_parents, ARRAY_SIZE(fsia_parents), 6, 2),
+        [DIV6_FSIB] = SH_CLK_MAP_DIV6_EXT(FSIBCKCR, 0,
+                                fsib_parents, ARRAY_SIZE(fsib_parents), 6, 2),
+        [DIV6_MP] = SH_CLK_MAP_DIV6_EXT(MPCKCR, 0, /* it needs bit[9-11] control */
+                                mp_parents, ARRAY_SIZE(mp_parents), 6, 2),
+        /* pll2s will be selected always for M4 */
+        [DIV6_M4] = SH_CLK_MAP_DIV6_EXT(M4CKCR, 0, /* it needs bit[9] control */
+                                m4_parents, ARRAY_SIZE(m4_parents), 6, 1),
+        [DIV6_HSI] = SH_CLK_MAP_DIV6_EXT(HSICKCR, 0, /* it needs bit[9] control */
+                                hsi_parents, ARRAY_SIZE(hsi_parents), 6, 2),
+        [DIV6_SPUV] = SH_CLK_MAP_DIV6_EXT(SPUVCKCR, 0,
+                                mp_parents, ARRAY_SIZE(mp_parents), 6, 2),
+};
+
+/* MSTP */
+enum {
         MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203,
         MSTP522,
         MSTP_NR
 };
 
 static struct clk mstp_clks[MSTP_NR] = {
-        [MSTP204] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 4, 0), /* SCIFA0 */
-        [MSTP203] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 3, 0), /* SCIFA1 */
-        [MSTP206] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 6, 0), /* SCIFB0 */
-        [MSTP207] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 7, 0), /* SCIFB1 */
-        [MSTP216] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 16, 0), /* SCIFB2 */
-        [MSTP217] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 17, 0), /* SCIFB3 */
+        [MSTP204] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],  SMSTPCR2, 4, 0), /* SCIFA0 */
+        [MSTP203] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],  SMSTPCR2, 3, 0), /* SCIFA1 */
+        [MSTP206] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],  SMSTPCR2, 6, 0), /* SCIFB0 */
+        [MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],  SMSTPCR2, 7, 0), /* SCIFB1 */
+        [MSTP216] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],  SMSTPCR2, 16, 0), /* SCIFB2 */
+        [MSTP217] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],  SMSTPCR2, 17, 0), /* SCIFB3 */
         [MSTP522] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR5, 22, 0), /* Thermal */
 };
 
 static struct clk_lookup lookups[] = {
+        /* main clock */
+        CLKDEV_CON_ID("extal1",                 &extal1_clk),
+        CLKDEV_CON_ID("extal1_div2",            &extal1_div2_clk),
+        CLKDEV_CON_ID("extal2",                 &extal2_clk),
+        CLKDEV_CON_ID("extal2_div2",            &extal2_div2_clk),
+        CLKDEV_CON_ID("extal2_div4",            &extal2_div4_clk),
+        CLKDEV_CON_ID("fsiack",                 &fsiack_clk),
+        CLKDEV_CON_ID("fsibck",                 &fsibck_clk),
+
+        /* pll clock */
+        CLKDEV_CON_ID("pll1",                   &pll1_clk),
+        CLKDEV_CON_ID("pll1_div2",              &pll1_div2_clk),
+        CLKDEV_CON_ID("pll2",                   &pll2_clk),
+        CLKDEV_CON_ID("pll2s",                  &pll2s_clk),
+        CLKDEV_CON_ID("pll2h",                  &pll2h_clk),
+
+        /* DIV6 */
+        CLKDEV_CON_ID("zb",                     &div6_clks[DIV6_ZB]),
+        CLKDEV_CON_ID("sdhi0",                  &div6_clks[DIV6_SDHI0]),
+        CLKDEV_CON_ID("sdhi1",                  &div6_clks[DIV6_SDHI1]),
+        CLKDEV_CON_ID("sdhi2",                  &div6_clks[DIV6_SDHI2]),
+        CLKDEV_CON_ID("mmc0",                   &div6_clks[DIV6_MMC0]),
+        CLKDEV_CON_ID("mmc1",                   &div6_clks[DIV6_MMC1]),
+        CLKDEV_CON_ID("vck1",                   &div6_clks[DIV6_VCK1]),
+        CLKDEV_CON_ID("vck2",                   &div6_clks[DIV6_VCK2]),
+        CLKDEV_CON_ID("vck3",                   &div6_clks[DIV6_VCK3]),
+        CLKDEV_CON_ID("vck4",                   &div6_clks[DIV6_VCK4]),
+        CLKDEV_CON_ID("vck5",                   &div6_clks[DIV6_VCK5]),
+        CLKDEV_CON_ID("fsia",                   &div6_clks[DIV6_FSIA]),
+        CLKDEV_CON_ID("fsib",                   &div6_clks[DIV6_FSIB]),
+        CLKDEV_CON_ID("mp",                     &div6_clks[DIV6_MP]),
+        CLKDEV_CON_ID("m4",                     &div6_clks[DIV6_M4]),
+        CLKDEV_CON_ID("hsi",                    &div6_clks[DIV6_HSI]),
+        CLKDEV_CON_ID("spuv",                   &div6_clks[DIV6_SPUV]),
+
+        /* MSTP */
         CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
         CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
         CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
@@ -88,22 +413,40 @@ static struct clk_lookup lookups[] = {
 
 void __init r8a73a4_clock_init(void)
 {
-        void __iomem *cpg_base, *reg;
+        void __iomem *reg;
         int k, ret = 0;
+        u32 ckscr;
+
+        reg = ioremap_nocache(CKSCR, PAGE_SIZE);
+        BUG_ON(!reg);
+        ckscr = ioread32(reg);
+        iounmap(reg);
 
-        /* fix MPCLK to EXTAL2 for now.
-         * this is needed until more detailed clock topology is supported
-         */
-        cpg_base = ioremap_nocache(CPG_BASE, CPG_LEN);
-        BUG_ON(!cpg_base);
-        reg = cpg_base + (MPCKCR - CPG_BASE);
-        iowrite32(ioread32(reg) | 1 << 7 | 0x0c, reg); /* set CKSEL */
-        iounmap(cpg_base);
+        switch ((ckscr >> 28) & 0x3) {
+        case 0:
+                main_clk.parent = &extal1_clk;
+                break;
+        case 1:
+                main_clk.parent = &extal1_div2_clk;
+                break;
+        case 2:
+                main_clk.parent = &extal2_clk;
+                break;
+        case 3:
+                main_clk.parent = &extal2_div2_clk;
+                break;
+        }
 
         for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
                 ret = clk_register(main_clks[k]);
 
         if (!ret)
+                ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
+
+        if (!ret)
+                ret = sh_clk_div6_reparent_register(div6_clks, DIV6_NR);
+
+        if (!ret)
                 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
 
         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
index c0d39aa6de50..7fd32d604e34 100644
--- a/arch/arm/mach-shmobile/clock-r8a7740.c
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -266,7 +266,7 @@ static struct clk fsiack_clk = {
 static struct clk fsibck_clk = {
 };
 
-struct clk *main_clks[] = {
+static struct clk *main_clks[] = {
         &extalr_clk,
         &extal1_clk,
         &extal2_clk,
@@ -317,7 +317,7 @@ enum {
         DIV4_NR
 };
 
-struct clk div4_clks[DIV4_NR] = {
+static struct clk div4_clks[DIV4_NR] = {
         [DIV4_I]        = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT),
         [DIV4_ZG]       = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT),
         [DIV4_B]        = SH_CLK_DIV4(&pllc1_clk, FRQCRA,  8, 0x6fff, CLK_ENABLE_ON_INIT),
@@ -461,7 +461,7 @@ enum {
 
         MSTP329, MSTP328, MSTP323, MSTP320,
         MSTP314, MSTP313, MSTP312,
-        MSTP309,
+        MSTP309, MSTP304,
 
         MSTP416, MSTP415, MSTP407, MSTP406,
 
@@ -499,6 +499,7 @@ static struct clk mstp_clks[MSTP_NR] = {
         [MSTP313] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR3, 13, 0), /* SDHI1 */
         [MSTP312] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR3, 12, 0), /* MMC */
         [MSTP309] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR3,  9, 0), /* GEther */
+        [MSTP304] = SH_CLK_MSTP32(&div4_clks[DIV4_CP],  SMSTPCR3,  4, 0), /* TPU0 */
 
         [MSTP416] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR4, 16, 0), /* USBHOST */
         [MSTP415] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR4, 15, 0), /* SDHI2 */
@@ -551,6 +552,7 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh_tmu.4",               &mstp_clks[MSTP111]),
         CLKDEV_DEV_ID("sh_tmu.5",               &mstp_clks[MSTP111]),
         CLKDEV_DEV_ID("i2c-sh_mobile.0",        &mstp_clks[MSTP116]),
+        CLKDEV_DEV_ID("fff20000.i2c",           &mstp_clks[MSTP116]),
         CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1",    &mstp_clks[MSTP117]),
         CLKDEV_DEV_ID("sh_tmu.0",               &mstp_clks[MSTP125]),
         CLKDEV_DEV_ID("sh_tmu.1",               &mstp_clks[MSTP125]),
@@ -584,6 +586,7 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh_cmt.10",              &mstp_clks[MSTP329]),
         CLKDEV_DEV_ID("sh_fsi2",                &mstp_clks[MSTP328]),
         CLKDEV_DEV_ID("i2c-sh_mobile.1",        &mstp_clks[MSTP323]),
+        CLKDEV_DEV_ID("e6c20000.i2c",           &mstp_clks[MSTP323]),
         CLKDEV_DEV_ID("renesas_usbhs",          &mstp_clks[MSTP320]),
         CLKDEV_DEV_ID("sh_mobile_sdhi.0",       &mstp_clks[MSTP314]),
         CLKDEV_DEV_ID("e6850000.sdhi",          &mstp_clks[MSTP314]),
@@ -592,6 +595,8 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh_mmcif",               &mstp_clks[MSTP312]),
         CLKDEV_DEV_ID("e6bd0000.mmcif",         &mstp_clks[MSTP312]),
         CLKDEV_DEV_ID("sh-eth",                 &mstp_clks[MSTP309]),
+        CLKDEV_DEV_ID("e9a00000.sh-eth",        &mstp_clks[MSTP309]),
+        CLKDEV_DEV_ID("renesas_tpu_pwm",        &mstp_clks[MSTP304]),
 
         CLKDEV_DEV_ID("sh_mobile_sdhi.2",       &mstp_clks[MSTP415]),
         CLKDEV_DEV_ID("e6870000.sdhi",          &mstp_clks[MSTP415]),
diff --git a/arch/arm/mach-shmobile/clock-r8a7778.c b/arch/arm/mach-shmobile/clock-r8a7778.c
index cd6855290b1f..b251e4d0924d 100644
--- a/arch/arm/mach-shmobile/clock-r8a7778.c
+++ b/arch/arm/mach-shmobile/clock-r8a7778.c
@@ -23,9 +23,23 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
+/*
+ *     MD      MD      MD      MD       PLLA   PLLB    EXTAL   clki    clkz
+ *     19      18      12      11                      (HMz)   (MHz)   (MHz)
+ *----------------------------------------------------------------------------
+ *     1       0       0       0       x21     x21     38.00   800     800
+ *     1       0       0       1       x24     x24     33.33   800     800
+ *     1       0       1       0       x28     x28     28.50   800     800
+ *     1       0       1       1       x32     x32     25.00   800     800
+ *     1       1       0       1       x24     x21     33.33   800     700
+ *     1       1       1       0       x28     x21     28.50   800     600
+ *     1       1       1       1       x32     x24     25.00   800     600
+ */
+
 #include <linux/io.h>
 #include <linux/sh_clk.h>
 #include <linux/clkdev.h>
+#include <mach/clock.h>
 #include <mach/common.h>
 
 #define MSTPCR0         IOMEM(0xffc80030)
@@ -37,6 +51,9 @@
 #define MSTPCR4         IOMEM(0xffc80050)
 #define MSTPCR5         IOMEM(0xffc80054)
 #define MSTPCR6         IOMEM(0xffc80058)
+#define MODEMR          0xFFCC0020
+
+#define MD(nr)  BIT(nr)
 
 /* ioremap() through clock mapping mandatory to avoid
  * collision with ARM coherent DMA virtual memory range.
@@ -47,36 +64,71 @@ static struct clk_mapping cpg_mapping = {
         .len    = 0x80,
 };
 
-static struct clk clkp = {
-        .rate   = 62500000, /* FIXME: shortcut */
-        .flags  = CLK_ENABLE_ON_INIT,
+static struct clk extal_clk = {
+        /* .rate will be updated on r8a7778_clock_init() */
         .mapping = &cpg_mapping,
 };
 
+/*
+ * clock ratio of these clock will be updated
+ * on r8a7778_clock_init()
+ */
+SH_FIXED_RATIO_CLK_SET(plla_clk,        extal_clk, 1, 1);
+SH_FIXED_RATIO_CLK_SET(pllb_clk,        extal_clk, 1, 1);
+SH_FIXED_RATIO_CLK_SET(i_clk,           plla_clk,  1, 1);
+SH_FIXED_RATIO_CLK_SET(s_clk,           plla_clk,  1, 1);
+SH_FIXED_RATIO_CLK_SET(s1_clk,          plla_clk,  1, 1);
+SH_FIXED_RATIO_CLK_SET(s3_clk,          plla_clk,  1, 1);
+SH_FIXED_RATIO_CLK_SET(s4_clk,          plla_clk,  1, 1);
+SH_FIXED_RATIO_CLK_SET(b_clk,           plla_clk,  1, 1);
+SH_FIXED_RATIO_CLK_SET(out_clk,         plla_clk,  1, 1);
+SH_FIXED_RATIO_CLK_SET(p_clk,           plla_clk,  1, 1);
+SH_FIXED_RATIO_CLK_SET(g_clk,           plla_clk,  1, 1);
+SH_FIXED_RATIO_CLK_SET(z_clk,           pllb_clk,  1, 1);
+
 static struct clk *main_clks[] = {
-        &clkp,
+        &extal_clk,
+        &plla_clk,
+        &pllb_clk,
+        &i_clk,
+        &s_clk,
+        &s1_clk,
+        &s3_clk,
+        &s4_clk,
+        &b_clk,
+        &out_clk,
+        &p_clk,
+        &g_clk,
+        &z_clk,
 };
 
 enum {
+        MSTP323, MSTP322, MSTP321,
         MSTP114,
         MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
         MSTP016, MSTP015,
         MSTP_NR };
 
 static struct clk mstp_clks[MSTP_NR] = {
-        [MSTP114] = SH_CLK_MSTP32(&clkp, MSTPCR1, 14, 0), /* Ether */
-        [MSTP026] = SH_CLK_MSTP32(&clkp, MSTPCR0, 26, 0), /* SCIF0 */
-        [MSTP025] = SH_CLK_MSTP32(&clkp, MSTPCR0, 25, 0), /* SCIF1 */
-        [MSTP024] = SH_CLK_MSTP32(&clkp, MSTPCR0, 24, 0), /* SCIF2 */
-        [MSTP023] = SH_CLK_MSTP32(&clkp, MSTPCR0, 23, 0), /* SCIF3 */
-        [MSTP022] = SH_CLK_MSTP32(&clkp, MSTPCR0, 22, 0), /* SCIF4 */
-        [MSTP021] = SH_CLK_MSTP32(&clkp, MSTPCR0, 21, 0), /* SCIF5 */
-        [MSTP016] = SH_CLK_MSTP32(&clkp, MSTPCR0, 16, 0), /* TMU0 */
-        [MSTP015] = SH_CLK_MSTP32(&clkp, MSTPCR0, 15, 0), /* TMU1 */
+        [MSTP323] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 23, 0), /* SDHI0 */
+        [MSTP322] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 22, 0), /* SDHI1 */
+        [MSTP321] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 21, 0), /* SDHI2 */
+        [MSTP114] = SH_CLK_MSTP32(&p_clk, MSTPCR1, 14, 0), /* Ether */
+        [MSTP026] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 26, 0), /* SCIF0 */
+        [MSTP025] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 25, 0), /* SCIF1 */
+        [MSTP024] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 24, 0), /* SCIF2 */
+        [MSTP023] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 23, 0), /* SCIF3 */
+        [MSTP022] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 22, 0), /* SCIF4 */
+        [MSTP021] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 21, 0), /* SCIF5 */
+        [MSTP016] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 16, 0), /* TMU0 */
+        [MSTP015] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 15, 0), /* TMU1 */
 };
 
 static struct clk_lookup lookups[] = {
         /* MSTP32 clocks */
+        CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */
+        CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */
+        CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */
         CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP114]), /* Ether */
         CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */
         CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */
@@ -90,8 +142,86 @@ static struct clk_lookup lookups[] = {
 
 void __init r8a7778_clock_init(void)
 {
+        void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
+        u32 mode;
         int k, ret = 0;
 
+        BUG_ON(!modemr);
+        mode = ioread32(modemr);
+        iounmap(modemr);
+
+        switch (mode & (MD(19) | MD(18) | MD(12) | MD(11))) {
+        case MD(19):
+                extal_clk.rate = 38000000;
+                SH_CLK_SET_RATIO(&plla_clk_ratio,       21, 1);
+                SH_CLK_SET_RATIO(&pllb_clk_ratio,       21, 1);
+                break;
+        case MD(19) | MD(11):
+                extal_clk.rate = 33333333;
+                SH_CLK_SET_RATIO(&plla_clk_ratio,       24, 1);
+                SH_CLK_SET_RATIO(&pllb_clk_ratio,       24, 1);
+                break;
+        case MD(19) | MD(12):
+                extal_clk.rate = 28500000;
+                SH_CLK_SET_RATIO(&plla_clk_ratio,       28, 1);
+                SH_CLK_SET_RATIO(&pllb_clk_ratio,       28, 1);
+                break;
+        case MD(19) | MD(12) | MD(11):
+                extal_clk.rate = 25000000;
+                SH_CLK_SET_RATIO(&plla_clk_ratio,       32, 1);
+                SH_CLK_SET_RATIO(&pllb_clk_ratio,       32, 1);
+                break;
+        case MD(19) | MD(18) | MD(11):
+                extal_clk.rate = 33333333;
+                SH_CLK_SET_RATIO(&plla_clk_ratio,       24, 1);
+                SH_CLK_SET_RATIO(&pllb_clk_ratio,       21, 1);
+                break;
+        case MD(19) | MD(18) | MD(12):
+                extal_clk.rate = 28500000;
+                SH_CLK_SET_RATIO(&plla_clk_ratio,       28, 1);
+                SH_CLK_SET_RATIO(&pllb_clk_ratio,       21, 1);
+                break;
+        case MD(19) | MD(18) | MD(12) | MD(11):
+                extal_clk.rate = 25000000;
+                SH_CLK_SET_RATIO(&plla_clk_ratio,       32, 1);
+                SH_CLK_SET_RATIO(&pllb_clk_ratio,       24, 1);
+                break;
+        default:
+                BUG();
+        }
+
+        if (mode & MD(1)) {
+                SH_CLK_SET_RATIO(&i_clk_ratio,  1, 1);
+                SH_CLK_SET_RATIO(&s_clk_ratio,  1, 3);
+                SH_CLK_SET_RATIO(&s1_clk_ratio, 1, 6);
+                SH_CLK_SET_RATIO(&s3_clk_ratio, 1, 4);
+                SH_CLK_SET_RATIO(&s4_clk_ratio, 1, 8);
+                SH_CLK_SET_RATIO(&p_clk_ratio,  1, 12);
+                SH_CLK_SET_RATIO(&g_clk_ratio,  1, 12);
+                if (mode & MD(2)) {
+                        SH_CLK_SET_RATIO(&b_clk_ratio,          1, 18);
+                        SH_CLK_SET_RATIO(&out_clk_ratio,        1, 18);
+                } else {
+                        SH_CLK_SET_RATIO(&b_clk_ratio,          1, 12);
+                        SH_CLK_SET_RATIO(&out_clk_ratio,        1, 12);
+                }
+        } else {
+                SH_CLK_SET_RATIO(&i_clk_ratio,  1, 1);
+                SH_CLK_SET_RATIO(&s_clk_ratio,  1, 4);
+                SH_CLK_SET_RATIO(&s1_clk_ratio, 1, 8);
+                SH_CLK_SET_RATIO(&s3_clk_ratio, 1, 4);
+                SH_CLK_SET_RATIO(&s4_clk_ratio, 1, 8);
+                SH_CLK_SET_RATIO(&p_clk_ratio,  1, 16);
+                SH_CLK_SET_RATIO(&g_clk_ratio,  1, 12);
+                if (mode & MD(2)) {
+                        SH_CLK_SET_RATIO(&b_clk_ratio,          1, 16);
+                        SH_CLK_SET_RATIO(&out_clk_ratio,        1, 16);
+                } else {
+                        SH_CLK_SET_RATIO(&b_clk_ratio,          1, 12);
+                        SH_CLK_SET_RATIO(&out_clk_ratio,        1, 12);
+                }
+        }
+
         for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
                 ret = clk_register(main_clks[k]);
 
diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
index 31d5cd4d9787..9daeb8c37483 100644
--- a/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -112,7 +112,7 @@ static struct clk *main_clks[] = {
 };
 
 enum { MSTP323, MSTP322, MSTP321, MSTP320,
-        MSTP115, MSTP114,
+        MSTP116, MSTP115, MSTP114,
         MSTP103, MSTP101, MSTP100,
         MSTP030,
         MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
@@ -125,6 +125,7 @@ static struct clk mstp_clks[MSTP_NR] = {
         [MSTP322] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 22, 0), /* SDHI1 */
         [MSTP321] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 21, 0), /* SDHI2 */
         [MSTP320] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 20, 0), /* SDHI3 */
+        [MSTP116] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 16, 0), /* PCIe */
         [MSTP115] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 15, 0), /* SATA */
         [MSTP114] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 14, 0), /* Ether */
         [MSTP103] = SH_CLK_MSTP32(&clks_clk, MSTPCR1,  3, 0), /* DU */
@@ -161,6 +162,7 @@ static struct clk_lookup lookups[] = {
         CLKDEV_CON_ID("peripheral_clk", &clkp_clk),
 
         /* MSTP32 clocks */
+        CLKDEV_DEV_ID("rcar-pcie", &mstp_clks[MSTP116]), /* PCIe */
         CLKDEV_DEV_ID("sata_rcar", &mstp_clks[MSTP115]), /* SATA */
         CLKDEV_DEV_ID("fc600000.sata", &mstp_clks[MSTP115]), /* SATA w/DT */
         CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP114]), /* Ether */
diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
index bad9bf2e34d6..b393592edc83 100644
--- a/arch/arm/mach-shmobile/clock-r8a7790.c
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -22,39 +22,174 @@
 #include <linux/kernel.h>
 #include <linux/sh_clk.h>
 #include <linux/clkdev.h>
+#include <mach/clock.h>
 #include <mach/common.h>
 
+/*
+ *   MD         EXTAL           PLL0    PLL1    PLL3
+ * 14 13 19     (MHz)           *1      *1
+ *---------------------------------------------------
+ * 0  0  0      15 x 1          x172/2  x208/2  x106
+ * 0  0  1      15 x 1          x172/2  x208/2  x88
+ * 0  1  0      20 x 1          x130/2  x156/2  x80
+ * 0  1  1      20 x 1          x130/2  x156/2  x66
+ * 1  0  0      26 / 2          x200/2  x240/2  x122
+ * 1  0  1      26 / 2          x200/2  x240/2  x102
+ * 1  1  0      30 / 2          x172/2  x208/2  x106
+ * 1  1  1      30 / 2          x172/2  x208/2  x88
+ *
+ * *1 : Table 7.6 indicates VCO ouput (PLLx = VCO/2)
+ *      see "p1 / 2" on R8A7790_CLOCK_ROOT() below
+ */
+
+#define MD(nr)  (1 << nr)
+
 #define CPG_BASE 0xe6150000
 #define CPG_LEN 0x1000
 
 #define SMSTPCR2 0xe6150138
+#define SMSTPCR3 0xe615013c
 #define SMSTPCR7 0xe615014c
 
+#define MODEMR          0xE6160060
+#define SDCKCR          0xE6150074
+#define SD2CKCR         0xE6150078
+#define SD3CKCR         0xE615007C
+#define MMC0CKCR        0xE6150240
+#define MMC1CKCR        0xE6150244
+#define SSPCKCR         0xE6150248
+#define SSPRSCKCR       0xE615024C
+
 static struct clk_mapping cpg_mapping = {
         .phys   = CPG_BASE,
         .len    = CPG_LEN,
 };
 
-static struct clk p_clk = {
-        .rate   = 65000000, /* shortcut for now */
+static struct clk extal_clk = {
+        /* .rate will be updated on r8a7790_clock_init() */
         .mapping        = &cpg_mapping,
 };
 
-static struct clk mp_clk = {
-        .rate   = 52000000,  /* shortcut for now */
-        .mapping        = &cpg_mapping,
+static struct sh_clk_ops followparent_clk_ops = {
+        .recalc = followparent_recalc,
+};
+
+static struct clk main_clk = {
+        /* .parent will be set r8a73a4_clock_init */
+        .ops    = &followparent_clk_ops,
 };
 
+/*
+ * clock ratio of these clock will be updated
+ * on r8a7790_clock_init()
+ */
+SH_FIXED_RATIO_CLK_SET(pll1_clk,                main_clk,       1, 1);
+SH_FIXED_RATIO_CLK_SET(pll3_clk,                main_clk,       1, 1);
+SH_FIXED_RATIO_CLK_SET(lb_clk,                  pll1_clk,       1, 1);
+SH_FIXED_RATIO_CLK_SET(qspi_clk,                pll1_clk,       1, 1);
+
+/* fixed ratio clock */
+SH_FIXED_RATIO_CLK_SET(extal_div2_clk,          extal_clk,      1, 2);
+SH_FIXED_RATIO_CLK_SET(cp_clk,                  extal_clk,      1, 2);
+
+SH_FIXED_RATIO_CLK_SET(pll1_div2_clk,           pll1_clk,       1, 2);
+SH_FIXED_RATIO_CLK_SET(zg_clk,                  pll1_clk,       1, 3);
+SH_FIXED_RATIO_CLK_SET(zx_clk,                  pll1_clk,       1, 3);
+SH_FIXED_RATIO_CLK_SET(zs_clk,                  pll1_clk,       1, 6);
+SH_FIXED_RATIO_CLK_SET(hp_clk,                  pll1_clk,       1, 12);
+SH_FIXED_RATIO_CLK_SET(i_clk,                   pll1_clk,       1, 2);
+SH_FIXED_RATIO_CLK_SET(b_clk,                   pll1_clk,       1, 12);
+SH_FIXED_RATIO_CLK_SET(p_clk,                   pll1_clk,       1, 24);
+SH_FIXED_RATIO_CLK_SET(cl_clk,                  pll1_clk,       1, 48);
+SH_FIXED_RATIO_CLK_SET(m2_clk,                  pll1_clk,       1, 8);
+SH_FIXED_RATIO_CLK_SET(imp_clk,                 pll1_clk,       1, 4);
+SH_FIXED_RATIO_CLK_SET(rclk_clk,                pll1_clk,       1, (48 * 1024));
+SH_FIXED_RATIO_CLK_SET(oscclk_clk,              pll1_clk,       1, (12 * 1024));
+
+SH_FIXED_RATIO_CLK_SET(zb3_clk,                 pll3_clk,       1, 4);
+SH_FIXED_RATIO_CLK_SET(zb3d2_clk,               pll3_clk,       1, 8);
+SH_FIXED_RATIO_CLK_SET(ddr_clk,                 pll3_clk,       1, 8);
+SH_FIXED_RATIO_CLK_SET(mp_clk,                  pll1_div2_clk,  1, 15);
+
 static struct clk *main_clks[] = {
+        &extal_clk,
+        &extal_div2_clk,
+        &main_clk,
+        &pll1_clk,
+        &pll1_div2_clk,
+        &pll3_clk,
+        &lb_clk,
+        &qspi_clk,
+        &zg_clk,
+        &zx_clk,
+        &zs_clk,
+        &hp_clk,
+        &i_clk,
+        &b_clk,
         &p_clk,
+        &cl_clk,
+        &m2_clk,
+        &imp_clk,
+        &rclk_clk,
+        &oscclk_clk,
+        &zb3_clk,
+        &zb3d2_clk,
+        &ddr_clk,
         &mp_clk,
+        &cp_clk,
+};
+
+/* SDHI (DIV4) clock */
+static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10 };
+
+static struct clk_div_mult_table div4_div_mult_table = {
+        .divisors = divisors,
+        .nr_divisors = ARRAY_SIZE(divisors),
+};
+
+static struct clk_div4_table div4_table = {
+        .div_mult_table = &div4_div_mult_table,
+};
+
+enum {
+        DIV4_SDH, DIV4_SD0, DIV4_SD1, DIV4_NR
+};
+
+static struct clk div4_clks[DIV4_NR] = {
+        [DIV4_SDH] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 8, 0x0dff, CLK_ENABLE_ON_INIT),
+        [DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1de0, CLK_ENABLE_ON_INIT),
+        [DIV4_SD1] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 0, 0x1de0, CLK_ENABLE_ON_INIT),
+};
+
+/* DIV6 clocks */
+enum {
+        DIV6_SD2, DIV6_SD3,
+        DIV6_MMC0, DIV6_MMC1,
+        DIV6_SSP, DIV6_SSPRS,
+        DIV6_NR
+};
+
+static struct clk div6_clks[DIV6_NR] = {
+        [DIV6_SD2]      = SH_CLK_DIV6(&pll1_div2_clk, SD2CKCR, 0),
+        [DIV6_SD3]      = SH_CLK_DIV6(&pll1_div2_clk, SD3CKCR, 0),
+        [DIV6_MMC0]     = SH_CLK_DIV6(&pll1_div2_clk, MMC0CKCR, 0),
+        [DIV6_MMC1]     = SH_CLK_DIV6(&pll1_div2_clk, MMC1CKCR, 0),
+        [DIV6_SSP]      = SH_CLK_DIV6(&pll1_div2_clk, SSPCKCR, 0),
+        [DIV6_SSPRS]    = SH_CLK_DIV6(&pll1_div2_clk, SSPRSCKCR, 0),
+};
+
+/* MSTP */
+enum {
+        MSTP721, MSTP720,
+        MSTP304,
+        MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202,
+        MSTP_NR
 };
 
-enum { MSTP721, MSTP720,
-        MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP_NR };
 static struct clk mstp_clks[MSTP_NR] = {
         [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */
         [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
+        [MSTP304] = SH_CLK_MSTP32(&cp_clk, SMSTPCR3, 4, 0), /* TPU0 */
         [MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */
         [MSTP207] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 7, 0), /* SCIFB1 */
         [MSTP206] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 6, 0), /* SCIFB0 */
@@ -64,6 +199,48 @@ static struct clk mstp_clks[MSTP_NR] = {
 };
 
 static struct clk_lookup lookups[] = {
+
+        /* main clocks */
+        CLKDEV_CON_ID("extal",          &extal_clk),
+        CLKDEV_CON_ID("extal_div2",     &extal_div2_clk),
+        CLKDEV_CON_ID("main",           &main_clk),
+        CLKDEV_CON_ID("pll1",           &pll1_clk),
+        CLKDEV_CON_ID("pll1_div2",      &pll1_div2_clk),
+        CLKDEV_CON_ID("pll3",           &pll3_clk),
+        CLKDEV_CON_ID("zg",             &zg_clk),
+        CLKDEV_CON_ID("zx",             &zx_clk),
+        CLKDEV_CON_ID("zs",             &zs_clk),
+        CLKDEV_CON_ID("hp",             &hp_clk),
+        CLKDEV_CON_ID("i",              &i_clk),
+        CLKDEV_CON_ID("b",              &b_clk),
+        CLKDEV_CON_ID("lb",             &lb_clk),
+        CLKDEV_CON_ID("p",              &p_clk),
+        CLKDEV_CON_ID("cl",             &cl_clk),
+        CLKDEV_CON_ID("m2",             &m2_clk),
+        CLKDEV_CON_ID("imp",            &imp_clk),
+        CLKDEV_CON_ID("rclk",           &rclk_clk),
+        CLKDEV_CON_ID("oscclk",         &oscclk_clk),
+        CLKDEV_CON_ID("zb3",            &zb3_clk),
+        CLKDEV_CON_ID("zb3d2",          &zb3d2_clk),
+        CLKDEV_CON_ID("ddr",            &ddr_clk),
+        CLKDEV_CON_ID("mp",             &mp_clk),
+        CLKDEV_CON_ID("qspi",           &qspi_clk),
+        CLKDEV_CON_ID("cp",             &cp_clk),
+
+        /* DIV4 */
+        CLKDEV_CON_ID("sdh",            &div4_clks[DIV4_SDH]),
+        CLKDEV_CON_ID("sd0",            &div4_clks[DIV4_SD0]),
+        CLKDEV_CON_ID("sd1",            &div4_clks[DIV4_SD1]),
+
+        /* DIV6 */
+        CLKDEV_CON_ID("sd2",            &div6_clks[DIV6_SD2]),
+        CLKDEV_CON_ID("sd3",            &div6_clks[DIV6_SD3]),
+        CLKDEV_CON_ID("mmc0",           &div6_clks[DIV6_MMC0]),
+        CLKDEV_CON_ID("mmc1",           &div6_clks[DIV6_MMC1]),
+        CLKDEV_CON_ID("ssp",            &div6_clks[DIV6_SSP]),
+        CLKDEV_CON_ID("ssprs",          &div6_clks[DIV6_SSPRS]),
+
+        /* MSTP */
         CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
         CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
         CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
@@ -74,14 +251,61 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]),
 };
 
+#define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31)              \
+        extal_clk.rate  = e * 1000 * 1000;                      \
+        main_clk.parent = m;                                    \
+        SH_CLK_SET_RATIO(&pll1_clk_ratio, p1 / 2, 1);           \
+        if (mode & MD(19))                                      \
+                SH_CLK_SET_RATIO(&pll3_clk_ratio, p31, 1);      \
+        else                                                    \
+                SH_CLK_SET_RATIO(&pll3_clk_ratio, p30, 1)
+
+
 void __init r8a7790_clock_init(void)
 {
+        void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
+        u32 mode;
         int k, ret = 0;
 
+        BUG_ON(!modemr);
+        mode = ioread32(modemr);
+        iounmap(modemr);
+
+        switch (mode & (MD(14) | MD(13))) {
+        case 0:
+                R8A7790_CLOCK_ROOT(15, &extal_clk, 172, 208, 106, 88);
+                break;
+        case MD(13):
+                R8A7790_CLOCK_ROOT(20, &extal_clk, 130, 156, 80, 66);
+                break;
+        case MD(14):
+                R8A7790_CLOCK_ROOT(26, &extal_div2_clk, 200, 240, 122, 102);
+                break;
+        case MD(13) | MD(14):
+                R8A7790_CLOCK_ROOT(30, &extal_div2_clk, 172, 208, 106, 88);
+                break;
+        }
+
+        if (mode & (MD(18)))
+                SH_CLK_SET_RATIO(&lb_clk_ratio, 1, 36);
+        else
+                SH_CLK_SET_RATIO(&lb_clk_ratio, 1, 24);
+
+        if ((mode & (MD(3) | MD(2) | MD(1))) == MD(2))
+                SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 16);
+        else
+                SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 20);
+
         for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
                 ret = clk_register(main_clks[k]);
 
         if (!ret)
+                ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
+
+        if (!ret)
+                ret = sh_clk_div6_register(div6_clks, DIV6_NR);
+
+        if (!ret)
                 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
 
         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index 784fbaa4cc55..d9fd0336b910 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -228,6 +228,11 @@ enum { DIV4_I, DIV4_ZG, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2,
 
 static struct clk div4_clks[DIV4_NR] = {
         [DIV4_I] = DIV4(FRQCRA, 20, 0xdff, CLK_ENABLE_ON_INIT),
+        /*
+         * ZG clock is dividing PLL0 frequency to supply SGX. Make sure not to
+         * exceed maximum frequencies of 201.5MHz for VDD_DVFS=1.175 and
+         * 239.2MHz for VDD_DVFS=1.315V.
+         */
         [DIV4_ZG] = SH_CLK_DIV4(&pll0_clk, FRQCRA, 16, 0xd7f, CLK_ENABLE_ON_INIT),
         [DIV4_M3] = DIV4(FRQCRA, 12, 0x1dff, CLK_ENABLE_ON_INIT),
         [DIV4_B] = DIV4(FRQCRA, 8, 0xdff, CLK_ENABLE_ON_INIT),
@@ -252,6 +257,101 @@ static struct clk twd_clk = {
         .ops = &twd_clk_ops,
 };
 
+static struct sh_clk_ops zclk_ops, kicker_ops;
+static const struct sh_clk_ops *div4_clk_ops;
+
+static int zclk_set_rate(struct clk *clk, unsigned long rate)
+{
+        int ret;
+
+        if (!clk->parent || !__clk_get(clk->parent))
+                return -ENODEV;
+
+        if (readl(FRQCRB) & (1 << 31))
+                return -EBUSY;
+
+        if (rate == clk_get_rate(clk->parent)) {
+                /* 1:1 - switch off divider */
+                __raw_writel(__raw_readl(FRQCRB) & ~(1 << 28), FRQCRB);
+                /* nullify the divider to prepare for the next time */
+                ret = div4_clk_ops->set_rate(clk, rate / 2);
+                if (!ret)
+                        ret = frqcr_kick();
+                if (ret > 0)
+                        ret = 0;
+        } else {
+                /* Enable the divider */
+                __raw_writel(__raw_readl(FRQCRB) | (1 << 28), FRQCRB);
+
+                ret = frqcr_kick();
+                if (ret >= 0)
+                        /*
+                         * set the divider - call the DIV4 method, it will kick
+                         * FRQCRB too
+                         */
+                        ret = div4_clk_ops->set_rate(clk, rate);
+                if (ret < 0)
+                        goto esetrate;
+        }
+
+esetrate:
+        __clk_put(clk->parent);
+        return ret;
+}
+
+static long zclk_round_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned long div_freq = div4_clk_ops->round_rate(clk, rate),
+                parent_freq = clk_get_rate(clk->parent);
+
+        if (rate > div_freq && abs(parent_freq - rate) < rate - div_freq)
+                return parent_freq;
+
+        return div_freq;
+}
+
+static unsigned long zclk_recalc(struct clk *clk)
+{
+        /*
+         * Must recalculate frequencies in case PLL0 has been changed, even if
+         * the divisor is unused ATM!
+         */
+        unsigned long div_freq = div4_clk_ops->recalc(clk);
+
+        if (__raw_readl(FRQCRB) & (1 << 28))
+                return div_freq;
+
+        return clk_get_rate(clk->parent);
+}
+
+static int kicker_set_rate(struct clk *clk, unsigned long rate)
+{
+        if (__raw_readl(FRQCRB) & (1 << 31))
+                return -EBUSY;
+
+        return div4_clk_ops->set_rate(clk, rate);
+}
+
+static void div4_clk_extend(void)
+{
+        int i;
+
+        div4_clk_ops = div4_clks[0].ops;
+
+        /* Add a kicker-busy check before changing the rate */
+        kicker_ops = *div4_clk_ops;
+        /* We extend the DIV4 clock with a 1:1 pass-through case */
+        zclk_ops = *div4_clk_ops;
+
+        kicker_ops.set_rate = kicker_set_rate;
+        zclk_ops.set_rate = zclk_set_rate;
+        zclk_ops.round_rate = zclk_round_rate;
+        zclk_ops.recalc = zclk_recalc;
+
+        for (i = 0; i < DIV4_NR; i++)
+                div4_clks[i].ops = i == DIV4_Z ? &zclk_ops : &kicker_ops;
+}
+
 enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_ZB1,
         DIV6_FLCTL, DIV6_SDHI0, DIV6_SDHI1, DIV6_SDHI2,
         DIV6_FSIA, DIV6_FSIB, DIV6_SUB,
@@ -450,7 +550,7 @@ static struct clk *late_main_clks[] = {
 };
 
 enum { MSTP001,
-        MSTP129, MSTP128, MSTP127, MSTP126, MSTP125, MSTP118, MSTP116, MSTP100,
+        MSTP129, MSTP128, MSTP127, MSTP126, MSTP125, MSTP118, MSTP116, MSTP112, MSTP100,
         MSTP219, MSTP218, MSTP217,
         MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
         MSTP331, MSTP329, MSTP328, MSTP325, MSTP323, MSTP322,
@@ -471,6 +571,7 @@ static struct clk mstp_clks[MSTP_NR] = {
         [MSTP125] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */
         [MSTP118] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 18, 0), /* DSITX0 */
         [MSTP116] = MSTP(&div4_clks[DIV4_HP], SMSTPCR1, 16, 0), /* IIC0 */
+        [MSTP112] = MSTP(&div4_clks[DIV4_ZG], SMSTPCR1, 12, 0), /* SGX */
         [MSTP100] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */
         [MSTP219] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 19, 0), /* SCIFA7 */
         [MSTP218] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* SY-DMAC */
@@ -513,6 +614,9 @@ static struct clk_lookup lookups[] = {
         CLKDEV_CON_ID("r_clk", &r_clk),
         CLKDEV_DEV_ID("smp_twd", &twd_clk), /* smp_twd */
 
+        /* DIV4 clocks */
+        CLKDEV_DEV_ID("cpufreq-cpu0", &div4_clks[DIV4_Z]),
+
         /* DIV6 clocks */
         CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
         CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]),
@@ -604,8 +708,11 @@ void __init sh73a0_clock_init(void)
         for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
                 ret = clk_register(main_clks[k]);
 
-        if (!ret)
+        if (!ret) {
                 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
+                if (!ret)
+                        div4_clk_extend();
+        }
 
         if (!ret)
                 ret = sh_clk_div6_reparent_register(div6_clks, DIV6_NR);
diff --git a/arch/arm/mach-shmobile/include/mach/clock.h b/arch/arm/mach-shmobile/include/mach/clock.h
index 76ac61292e48..03e56074928c 100644
--- a/arch/arm/mach-shmobile/include/mach/clock.h
+++ b/arch/arm/mach-shmobile/include/mach/clock.h
@@ -24,16 +24,16 @@ struct clk name = {			\
 }
 
 #define SH_FIXED_RATIO_CLK(name, p, r)          \
-static SH_FIXED_RATIO_CLKg(name, p, r);
+static SH_FIXED_RATIO_CLKg(name, p, r)
 
 #define SH_FIXED_RATIO_CLK_SET(name, p, m, d)   \
         SH_CLK_RATIO(name, m, d);               \
-        SH_FIXED_RATIO_CLK(name, p, name);
+        SH_FIXED_RATIO_CLK(name, p, name)
 
 #define SH_CLK_SET_RATIO(p, m, d)       \
-{                       \
+do {                    \
         (p)->mul = m;   \
         (p)->div = d;   \
-}
+} while (0)
 
 #endif
diff --git a/arch/arm/mach-shmobile/include/mach/irqs.h b/arch/arm/mach-shmobile/include/mach/irqs.h
index b2074e2acb15..d241bfd6926d 100644
--- a/arch/arm/mach-shmobile/include/mach/irqs.h
+++ b/arch/arm/mach-shmobile/include/mach/irqs.h
@@ -16,4 +16,9 @@
 #define IRQPIN_BASE             2000
 #define irq_pin(nr)             ((nr) + IRQPIN_BASE)
 
+/* GPIO IRQ */
+#define _GPIO_IRQ_BASE          2500
+#define GPIO_IRQ_BASE(x)        (_GPIO_IRQ_BASE + (32 * x))
+#define GPIO_IRQ(x, y)          (_GPIO_IRQ_BASE + (32 * x) + y)
+
 #endif /* __ASM_MACH_IRQS_H */
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h
index abdc4d4efa28..9c9a66ccaf6f 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7740.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h
@@ -28,494 +28,6 @@
 #define MD_CK1  (1 << 1)
 #define MD_CK0  (1 << 0)
 
-/*
- * Pin Function Controller:
- *      GPIO_FN_xx - GPIO used to select pin function
- *      GPIO_PORTxx - GPIO mapped to real I/O pin on CPU
- */
-enum {
-        /* PORT */
-        GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4,
-        GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9,
-
-        GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14,
-        GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19,
-
-        GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24,
-        GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29,
-
-        GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34,
-        GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39,
-
-        GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44,
-        GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49,
-
-        GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54,
-        GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59,
-
-        GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64,
-        GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69,
-
-        GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74,
-        GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79,
-
-        GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84,
-        GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89,
-
-        GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94,
-        GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99,
-
-        GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104,
-        GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109,
-
-        GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114,
-        GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, GPIO_PORT119,
-
-        GPIO_PORT120, GPIO_PORT121, GPIO_PORT122, GPIO_PORT123, GPIO_PORT124,
-        GPIO_PORT125, GPIO_PORT126, GPIO_PORT127, GPIO_PORT128, GPIO_PORT129,
-
-        GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134,
-        GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139,
-
-        GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144,
-        GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149,
-
-        GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154,
-        GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159,
-
-        GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164,
-        GPIO_PORT165, GPIO_PORT166, GPIO_PORT167, GPIO_PORT168, GPIO_PORT169,
-
-        GPIO_PORT170, GPIO_PORT171, GPIO_PORT172, GPIO_PORT173, GPIO_PORT174,
-        GPIO_PORT175, GPIO_PORT176, GPIO_PORT177, GPIO_PORT178, GPIO_PORT179,
-
-        GPIO_PORT180, GPIO_PORT181, GPIO_PORT182, GPIO_PORT183, GPIO_PORT184,
-        GPIO_PORT185, GPIO_PORT186, GPIO_PORT187, GPIO_PORT188, GPIO_PORT189,
-
-        GPIO_PORT190, GPIO_PORT191, GPIO_PORT192, GPIO_PORT193, GPIO_PORT194,
-        GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199,
-
-        GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204,
-        GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209,
-
-        GPIO_PORT210, GPIO_PORT211,
-
-        /* IRQ */
-        GPIO_FN_IRQ0_PORT2,     GPIO_FN_IRQ0_PORT13,
-        GPIO_FN_IRQ1,
-        GPIO_FN_IRQ2_PORT11,    GPIO_FN_IRQ2_PORT12,
-        GPIO_FN_IRQ3_PORT10,    GPIO_FN_IRQ3_PORT14,
-        GPIO_FN_IRQ4_PORT15,    GPIO_FN_IRQ4_PORT172,
-        GPIO_FN_IRQ5_PORT0,     GPIO_FN_IRQ5_PORT1,
-        GPIO_FN_IRQ6_PORT121,   GPIO_FN_IRQ6_PORT173,
-        GPIO_FN_IRQ7_PORT120,   GPIO_FN_IRQ7_PORT209,
-        GPIO_FN_IRQ8,
-        GPIO_FN_IRQ9_PORT118,   GPIO_FN_IRQ9_PORT210,
-        GPIO_FN_IRQ10,
-        GPIO_FN_IRQ11,
-        GPIO_FN_IRQ12_PORT42,   GPIO_FN_IRQ12_PORT97,
-        GPIO_FN_IRQ13_PORT64,   GPIO_FN_IRQ13_PORT98,
-        GPIO_FN_IRQ14_PORT63,   GPIO_FN_IRQ14_PORT99,
-        GPIO_FN_IRQ15_PORT62,   GPIO_FN_IRQ15_PORT100,
-        GPIO_FN_IRQ16_PORT68,   GPIO_FN_IRQ16_PORT211,
-        GPIO_FN_IRQ17,
-        GPIO_FN_IRQ18,
-        GPIO_FN_IRQ19,
-        GPIO_FN_IRQ20,
-        GPIO_FN_IRQ21,
-        GPIO_FN_IRQ22,
-        GPIO_FN_IRQ23,
-        GPIO_FN_IRQ24,
-        GPIO_FN_IRQ25,
-        GPIO_FN_IRQ26_PORT58,   GPIO_FN_IRQ26_PORT81,
-        GPIO_FN_IRQ27_PORT57,   GPIO_FN_IRQ27_PORT168,
-        GPIO_FN_IRQ28_PORT56,   GPIO_FN_IRQ28_PORT169,
-        GPIO_FN_IRQ29_PORT50,   GPIO_FN_IRQ29_PORT170,
-        GPIO_FN_IRQ30_PORT49,   GPIO_FN_IRQ30_PORT171,
-        GPIO_FN_IRQ31_PORT41,   GPIO_FN_IRQ31_PORT167,
-
-        /* Function */
-
-        /* DBGT */
-        GPIO_FN_DBGMDT2,        GPIO_FN_DBGMDT1,        GPIO_FN_DBGMDT0,
-        GPIO_FN_DBGMD10,        GPIO_FN_DBGMD11,        GPIO_FN_DBGMD20,
-        GPIO_FN_DBGMD21,
-
-        /* FSI-A */
-        GPIO_FN_FSIAISLD_PORT0,         /* FSIAISLD Port 0/5 */
-        GPIO_FN_FSIAISLD_PORT5,
-        GPIO_FN_FSIASPDIF_PORT9,        /* FSIASPDIF Port 9/18 */
-        GPIO_FN_FSIASPDIF_PORT18,
-        GPIO_FN_FSIAOSLD1,      GPIO_FN_FSIAOSLD2,
-        GPIO_FN_FSIAOLR,        GPIO_FN_FSIAOBT,
-        GPIO_FN_FSIAOSLD,       GPIO_FN_FSIAOMC,
-        GPIO_FN_FSIACK,         GPIO_FN_FSIAILR,
-        GPIO_FN_FSIAIBT,
-
-        /* FSI-B */
-        GPIO_FN_FSIBCK,
-
-        /* FMSI */
-        GPIO_FN_FMSISLD_PORT1, /* FMSISLD Port 1/6 */
-        GPIO_FN_FMSISLD_PORT6,
-        GPIO_FN_FMSIILR,        GPIO_FN_FMSIIBT,
-        GPIO_FN_FMSIOLR,        GPIO_FN_FMSIOBT,
-        GPIO_FN_FMSICK,         GPIO_FN_FMSOILR,
-        GPIO_FN_FMSOIBT,        GPIO_FN_FMSOOLR,
-        GPIO_FN_FMSOOBT,        GPIO_FN_FMSOSLD,
-        GPIO_FN_FMSOCK,
-
-        /* SCIFA0 */
-        GPIO_FN_SCIFA0_SCK,     GPIO_FN_SCIFA0_CTS,
-        GPIO_FN_SCIFA0_RTS,     GPIO_FN_SCIFA0_RXD,
-        GPIO_FN_SCIFA0_TXD,
-
-        /* SCIFA1 */
-        GPIO_FN_SCIFA1_CTS,     GPIO_FN_SCIFA1_SCK,
-        GPIO_FN_SCIFA1_RXD,     GPIO_FN_SCIFA1_TXD,
-        GPIO_FN_SCIFA1_RTS,
-
-        /* SCIFA2 */
-        GPIO_FN_SCIFA2_SCK_PORT22, /* SCIFA2_SCK Port 22/199 */
-        GPIO_FN_SCIFA2_SCK_PORT199,
-        GPIO_FN_SCIFA2_RXD,     GPIO_FN_SCIFA2_TXD,
-        GPIO_FN_SCIFA2_CTS,     GPIO_FN_SCIFA2_RTS,
-
-        /* SCIFA3 */
-        GPIO_FN_SCIFA3_RTS_PORT105, /* MSEL5CR_8_0 */
-        GPIO_FN_SCIFA3_SCK_PORT116,
-        GPIO_FN_SCIFA3_CTS_PORT117,
-        GPIO_FN_SCIFA3_RXD_PORT174,
-        GPIO_FN_SCIFA3_TXD_PORT175,
-
-        GPIO_FN_SCIFA3_RTS_PORT161, /* MSEL5CR_8_1 */
-        GPIO_FN_SCIFA3_SCK_PORT158,
-        GPIO_FN_SCIFA3_CTS_PORT162,
-        GPIO_FN_SCIFA3_RXD_PORT159,
-        GPIO_FN_SCIFA3_TXD_PORT160,
-
-        /* SCIFA4 */
-        GPIO_FN_SCIFA4_RXD_PORT12, /* MSEL5CR[12:11] = 00 */
-        GPIO_FN_SCIFA4_TXD_PORT13,
-
-        GPIO_FN_SCIFA4_RXD_PORT204, /* MSEL5CR[12:11] = 01 */
-        GPIO_FN_SCIFA4_TXD_PORT203,
-
-        GPIO_FN_SCIFA4_RXD_PORT94, /* MSEL5CR[12:11] = 10 */
-        GPIO_FN_SCIFA4_TXD_PORT93,
-
-        GPIO_FN_SCIFA4_SCK_PORT21, /* SCIFA4_SCK Port 21/205 */
-        GPIO_FN_SCIFA4_SCK_PORT205,
-
-        /* SCIFA5 */
-        GPIO_FN_SCIFA5_TXD_PORT20, /* MSEL5CR[15:14] = 00 */
-        GPIO_FN_SCIFA5_RXD_PORT10,
-
-        GPIO_FN_SCIFA5_RXD_PORT207, /* MSEL5CR[15:14] = 01 */
-        GPIO_FN_SCIFA5_TXD_PORT208,
-
-        GPIO_FN_SCIFA5_TXD_PORT91, /* MSEL5CR[15:14] = 10 */
-        GPIO_FN_SCIFA5_RXD_PORT92,
-
-        GPIO_FN_SCIFA5_SCK_PORT23, /* SCIFA5_SCK Port 23/206 */
-        GPIO_FN_SCIFA5_SCK_PORT206,
-
-        /* SCIFA6 */
-        GPIO_FN_SCIFA6_SCK,     GPIO_FN_SCIFA6_RXD,     GPIO_FN_SCIFA6_TXD,
-
-        /* SCIFA7 */
-        GPIO_FN_SCIFA7_TXD,     GPIO_FN_SCIFA7_RXD,
-
-        /* SCIFAB */
-        GPIO_FN_SCIFB_SCK_PORT190, /* MSEL5CR_17_0 */
-        GPIO_FN_SCIFB_RXD_PORT191,
-        GPIO_FN_SCIFB_TXD_PORT192,
-        GPIO_FN_SCIFB_RTS_PORT186,
-        GPIO_FN_SCIFB_CTS_PORT187,
-
-        GPIO_FN_SCIFB_SCK_PORT2, /* MSEL5CR_17_1 */
-        GPIO_FN_SCIFB_RXD_PORT3,
-        GPIO_FN_SCIFB_TXD_PORT4,
-        GPIO_FN_SCIFB_RTS_PORT172,
-        GPIO_FN_SCIFB_CTS_PORT173,
-
-        /* LCD0 */
-        GPIO_FN_LCDC0_SELECT,
-
-        /* LCD1 */
-        GPIO_FN_LCDC1_SELECT,
-
-        /* RSPI */
-        GPIO_FN_RSPI_SSL0_A,    GPIO_FN_RSPI_SSL1_A,
-        GPIO_FN_RSPI_SSL2_A,    GPIO_FN_RSPI_SSL3_A,
-        GPIO_FN_RSPI_MOSI_A,    GPIO_FN_RSPI_MISO_A,
-        GPIO_FN_RSPI_CK_A,
-
-        /* VIO CKO */
-        GPIO_FN_VIO_CKO1,
-        GPIO_FN_VIO_CKO2,
-        GPIO_FN_VIO_CKO_1,
-        GPIO_FN_VIO_CKO,
-
-        /* VIO0 */
-        GPIO_FN_VIO0_D0,        GPIO_FN_VIO0_D1,        GPIO_FN_VIO0_D2,
-        GPIO_FN_VIO0_D3,        GPIO_FN_VIO0_D4,        GPIO_FN_VIO0_D5,
-        GPIO_FN_VIO0_D6,        GPIO_FN_VIO0_D7,        GPIO_FN_VIO0_D8,
-        GPIO_FN_VIO0_D9,        GPIO_FN_VIO0_D10,       GPIO_FN_VIO0_D11,
-        GPIO_FN_VIO0_D12,       GPIO_FN_VIO0_VD,        GPIO_FN_VIO0_HD,
-        GPIO_FN_VIO0_CLK,       GPIO_FN_VIO0_FIELD,
-
-        GPIO_FN_VIO0_D13_PORT26, /* MSEL5CR_27_0 */
-        GPIO_FN_VIO0_D14_PORT25,
-        GPIO_FN_VIO0_D15_PORT24,
-
-        GPIO_FN_VIO0_D13_PORT22, /* MSEL5CR_27_1 */
-        GPIO_FN_VIO0_D14_PORT95,
-        GPIO_FN_VIO0_D15_PORT96,
-
-        /* VIO1 */
-        GPIO_FN_VIO1_D0,        GPIO_FN_VIO1_D1,        GPIO_FN_VIO1_D2,
-        GPIO_FN_VIO1_D3,        GPIO_FN_VIO1_D4,        GPIO_FN_VIO1_D5,
-        GPIO_FN_VIO1_D6,        GPIO_FN_VIO1_D7,        GPIO_FN_VIO1_VD,
-        GPIO_FN_VIO1_HD,        GPIO_FN_VIO1_CLK,       GPIO_FN_VIO1_FIELD,
-
-        /* TPU0 */
-        GPIO_FN_TPU0TO0,        GPIO_FN_TPU0TO1,
-        GPIO_FN_TPU0TO3,
-        GPIO_FN_TPU0TO2_PORT66, /* TPU0TO2 Port 66/202 */
-        GPIO_FN_TPU0TO2_PORT202,
-
-        /* SSP1 0 */
-        GPIO_FN_STP0_IPD0,      GPIO_FN_STP0_IPD1,      GPIO_FN_STP0_IPD2,
-        GPIO_FN_STP0_IPD3,      GPIO_FN_STP0_IPD4,      GPIO_FN_STP0_IPD5,
-        GPIO_FN_STP0_IPD6,      GPIO_FN_STP0_IPD7,      GPIO_FN_STP0_IPEN,
-        GPIO_FN_STP0_IPCLK,     GPIO_FN_STP0_IPSYNC,
-
-        /* SSP1 1 */
-        GPIO_FN_STP1_IPD1,      GPIO_FN_STP1_IPD2,      GPIO_FN_STP1_IPD3,
-        GPIO_FN_STP1_IPD4,      GPIO_FN_STP1_IPD5,      GPIO_FN_STP1_IPD6,
-        GPIO_FN_STP1_IPD7,      GPIO_FN_STP1_IPCLK,     GPIO_FN_STP1_IPSYNC,
-
-        GPIO_FN_STP1_IPD0_PORT186, /* MSEL5CR_23_0 */
-        GPIO_FN_STP1_IPEN_PORT187,
-
-        GPIO_FN_STP1_IPD0_PORT194, /* MSEL5CR_23_1 */
-        GPIO_FN_STP1_IPEN_PORT193,
-
-        /* SIM */
-        GPIO_FN_SIM_RST,        GPIO_FN_SIM_CLK,
-        GPIO_FN_SIM_D_PORT22, /* SIM_D  Port 22/199 */
-        GPIO_FN_SIM_D_PORT199,
-
-        /* MSIOF2 */
-        GPIO_FN_MSIOF2_TXD,     GPIO_FN_MSIOF2_RXD,     GPIO_FN_MSIOF2_TSCK,
-        GPIO_FN_MSIOF2_SS2,     GPIO_FN_MSIOF2_TSYNC,   GPIO_FN_MSIOF2_SS1,
-        GPIO_FN_MSIOF2_MCK1,    GPIO_FN_MSIOF2_MCK0,    GPIO_FN_MSIOF2_RSYNC,
-        GPIO_FN_MSIOF2_RSCK,
-
-        /* KEYSC */
-        GPIO_FN_KEYIN4,         GPIO_FN_KEYIN5,
-        GPIO_FN_KEYIN6,         GPIO_FN_KEYIN7,
-        GPIO_FN_KEYOUT0,        GPIO_FN_KEYOUT1,        GPIO_FN_KEYOUT2,
-        GPIO_FN_KEYOUT3,        GPIO_FN_KEYOUT4,        GPIO_FN_KEYOUT5,
-        GPIO_FN_KEYOUT6,        GPIO_FN_KEYOUT7,
-
-        GPIO_FN_KEYIN0_PORT43, /* MSEL4CR_18_0 */
-        GPIO_FN_KEYIN1_PORT44,
-        GPIO_FN_KEYIN2_PORT45,
-        GPIO_FN_KEYIN3_PORT46,
-
-        GPIO_FN_KEYIN0_PORT58, /* MSEL4CR_18_1 */
-        GPIO_FN_KEYIN1_PORT57,
-        GPIO_FN_KEYIN2_PORT56,
-        GPIO_FN_KEYIN3_PORT55,
-
-        /* VOU */
-        GPIO_FN_DV_D0,  GPIO_FN_DV_D1,  GPIO_FN_DV_D2,  GPIO_FN_DV_D3,
-        GPIO_FN_DV_D4,  GPIO_FN_DV_D5,  GPIO_FN_DV_D6,  GPIO_FN_DV_D7,
-        GPIO_FN_DV_D8,  GPIO_FN_DV_D9,  GPIO_FN_DV_D10, GPIO_FN_DV_D11,
-        GPIO_FN_DV_D12, GPIO_FN_DV_D13, GPIO_FN_DV_D14, GPIO_FN_DV_D15,
-        GPIO_FN_DV_CLK,
-        GPIO_FN_DV_VSYNC,
-        GPIO_FN_DV_HSYNC,
-
-        /* MEMC */
-        GPIO_FN_MEMC_AD0,       GPIO_FN_MEMC_AD1,       GPIO_FN_MEMC_AD2,
-        GPIO_FN_MEMC_AD3,       GPIO_FN_MEMC_AD4,       GPIO_FN_MEMC_AD5,
-        GPIO_FN_MEMC_AD6,       GPIO_FN_MEMC_AD7,       GPIO_FN_MEMC_AD8,
-        GPIO_FN_MEMC_AD9,       GPIO_FN_MEMC_AD10,      GPIO_FN_MEMC_AD11,
-        GPIO_FN_MEMC_AD12,      GPIO_FN_MEMC_AD13,      GPIO_FN_MEMC_AD14,
-        GPIO_FN_MEMC_AD15,      GPIO_FN_MEMC_CS0,       GPIO_FN_MEMC_INT,
-        GPIO_FN_MEMC_NWE,       GPIO_FN_MEMC_NOE,
-
-        GPIO_FN_MEMC_CS1, /* MSEL4CR_6_0 */
-        GPIO_FN_MEMC_ADV,
-        GPIO_FN_MEMC_WAIT,
-        GPIO_FN_MEMC_BUSCLK,
-
-        GPIO_FN_MEMC_A1, /* MSEL4CR_6_1 */
-        GPIO_FN_MEMC_DREQ0,
-        GPIO_FN_MEMC_DREQ1,
-        GPIO_FN_MEMC_A0,
-
-        /* MSIOF0 */
-        GPIO_FN_MSIOF0_SS1,     GPIO_FN_MSIOF0_SS2,
-        GPIO_FN_MSIOF0_RXD,     GPIO_FN_MSIOF0_TXD,
-        GPIO_FN_MSIOF0_MCK0,    GPIO_FN_MSIOF0_MCK1,
-        GPIO_FN_MSIOF0_RSYNC,   GPIO_FN_MSIOF0_RSCK,
-        GPIO_FN_MSIOF0_TSCK,    GPIO_FN_MSIOF0_TSYNC,
-
-        /* MSIOF1 */
-        GPIO_FN_MSIOF1_RSCK,    GPIO_FN_MSIOF1_RSYNC,
-        GPIO_FN_MSIOF1_MCK0,    GPIO_FN_MSIOF1_MCK1,
-
-        GPIO_FN_MSIOF1_SS2_PORT116,     GPIO_FN_MSIOF1_SS1_PORT117,
-        GPIO_FN_MSIOF1_RXD_PORT118,     GPIO_FN_MSIOF1_TXD_PORT119,
-        GPIO_FN_MSIOF1_TSYNC_PORT120,
-        GPIO_FN_MSIOF1_TSCK_PORT121,    /* MSEL4CR_10_0 */
-
-        GPIO_FN_MSIOF1_SS1_PORT67,      GPIO_FN_MSIOF1_TSCK_PORT72,
-        GPIO_FN_MSIOF1_TSYNC_PORT73,    GPIO_FN_MSIOF1_TXD_PORT74,
-        GPIO_FN_MSIOF1_RXD_PORT75,
-        GPIO_FN_MSIOF1_SS2_PORT202,     /* MSEL4CR_10_1 */
-
-        /* GPIO */
-        GPIO_FN_GPO0,   GPIO_FN_GPI0,
-        GPIO_FN_GPO1,   GPIO_FN_GPI1,
-
-        /* USB0 */
-        GPIO_FN_USB0_OCI,       GPIO_FN_USB0_PPON,      GPIO_FN_VBUS,
-
-        /* USB1 */
-        GPIO_FN_USB1_OCI,       GPIO_FN_USB1_PPON,
-
-        /* BBIF1 */
-        GPIO_FN_BBIF1_RXD,      GPIO_FN_BBIF1_TXD,      GPIO_FN_BBIF1_TSYNC,
-        GPIO_FN_BBIF1_TSCK,     GPIO_FN_BBIF1_RSCK,     GPIO_FN_BBIF1_RSYNC,
-        GPIO_FN_BBIF1_FLOW,     GPIO_FN_BBIF1_RX_FLOW_N,
-
-        /* BBIF2 */
-        GPIO_FN_BBIF2_TXD2_PORT5, /* MSEL5CR_0_0 */
-        GPIO_FN_BBIF2_RXD2_PORT60,
-        GPIO_FN_BBIF2_TSYNC2_PORT6,
-        GPIO_FN_BBIF2_TSCK2_PORT59,
-
-        GPIO_FN_BBIF2_RXD2_PORT90, /* MSEL5CR_0_1 */
-        GPIO_FN_BBIF2_TXD2_PORT183,
-        GPIO_FN_BBIF2_TSCK2_PORT89,
-        GPIO_FN_BBIF2_TSYNC2_PORT184,
-
-        /* BSC / FLCTL / PCMCIA */
-        GPIO_FN_CS0,    GPIO_FN_CS2,    GPIO_FN_CS4,
-        GPIO_FN_CS5B,   GPIO_FN_CS6A,
-        GPIO_FN_CS5A_PORT105, /* CS5A PORT 19/105 */
-        GPIO_FN_CS5A_PORT19,
-        GPIO_FN_IOIS16, /* ? */
-
-        GPIO_FN_A0,     GPIO_FN_A1,     GPIO_FN_A2,     GPIO_FN_A3,
-        GPIO_FN_A4_FOE,         /* share with FLCTL */
-        GPIO_FN_A5_FCDE,        /* share with FLCTL */
-        GPIO_FN_A6,     GPIO_FN_A7,     GPIO_FN_A8,     GPIO_FN_A9,
-        GPIO_FN_A10,    GPIO_FN_A11,    GPIO_FN_A12,    GPIO_FN_A13,
-        GPIO_FN_A14,    GPIO_FN_A15,    GPIO_FN_A16,    GPIO_FN_A17,
-        GPIO_FN_A18,    GPIO_FN_A19,    GPIO_FN_A20,    GPIO_FN_A21,
-        GPIO_FN_A22,    GPIO_FN_A23,    GPIO_FN_A24,    GPIO_FN_A25,
-        GPIO_FN_A26,
-
-        GPIO_FN_D0_NAF0,        GPIO_FN_D1_NAF1,        /* share with FLCTL */
-        GPIO_FN_D2_NAF2,        GPIO_FN_D3_NAF3,        /* share with FLCTL */
-        GPIO_FN_D4_NAF4,        GPIO_FN_D5_NAF5,        /* share with FLCTL */
-        GPIO_FN_D6_NAF6,        GPIO_FN_D7_NAF7,        /* share with FLCTL */
-        GPIO_FN_D8_NAF8,        GPIO_FN_D9_NAF9,        /* share with FLCTL */
-        GPIO_FN_D10_NAF10,      GPIO_FN_D11_NAF11,      /* share with FLCTL */
-        GPIO_FN_D12_NAF12,      GPIO_FN_D13_NAF13,      /* share with FLCTL */
-        GPIO_FN_D14_NAF14,      GPIO_FN_D15_NAF15,      /* share with FLCTL */
-
-        GPIO_FN_D16,    GPIO_FN_D17,    GPIO_FN_D18,    GPIO_FN_D19,
-        GPIO_FN_D20,    GPIO_FN_D21,    GPIO_FN_D22,    GPIO_FN_D23,
-        GPIO_FN_D24,    GPIO_FN_D25,    GPIO_FN_D26,    GPIO_FN_D27,
-        GPIO_FN_D28,    GPIO_FN_D29,    GPIO_FN_D30,    GPIO_FN_D31,
-
-        GPIO_FN_WE0_FWE,        /* share with FLCTL */
-        GPIO_FN_WE1,
-        GPIO_FN_WE2_ICIORD,     /* share with PCMCIA */
-        GPIO_FN_WE3_ICIOWR,     /* share with PCMCIA */
-        GPIO_FN_CKO,    GPIO_FN_BS,     GPIO_FN_RDWR,
-        GPIO_FN_RD_FSC,         /* share with FLCTL */
-        GPIO_FN_WAIT_PORT177,   /* WAIT Port 90/177 */
-        GPIO_FN_WAIT_PORT90,
-
-        GPIO_FN_FCE0,   GPIO_FN_FCE1,   GPIO_FN_FRB, /* FLCTL */
-
-        /* IRDA */
-        GPIO_FN_IRDA_FIRSEL,    GPIO_FN_IRDA_IN,        GPIO_FN_IRDA_OUT,
-
-        /* ATAPI */
-        GPIO_FN_IDE_D0,         GPIO_FN_IDE_D1,         GPIO_FN_IDE_D2,
-        GPIO_FN_IDE_D3,         GPIO_FN_IDE_D4,         GPIO_FN_IDE_D5,
-        GPIO_FN_IDE_D6,         GPIO_FN_IDE_D7,         GPIO_FN_IDE_D8,
-        GPIO_FN_IDE_D9,         GPIO_FN_IDE_D10,        GPIO_FN_IDE_D11,
-        GPIO_FN_IDE_D12,        GPIO_FN_IDE_D13,        GPIO_FN_IDE_D14,
-        GPIO_FN_IDE_D15,        GPIO_FN_IDE_A0,         GPIO_FN_IDE_A1,
-        GPIO_FN_IDE_A2,         GPIO_FN_IDE_CS0,        GPIO_FN_IDE_CS1,
-        GPIO_FN_IDE_IOWR,       GPIO_FN_IDE_IORD,       GPIO_FN_IDE_IORDY,
-        GPIO_FN_IDE_INT,        GPIO_FN_IDE_RST,        GPIO_FN_IDE_DIRECTION,
-        GPIO_FN_IDE_EXBUF_ENB,  GPIO_FN_IDE_IODACK,     GPIO_FN_IDE_IODREQ,
-
-        /* RMII */
-        GPIO_FN_RMII_CRS_DV,    GPIO_FN_RMII_RX_ER,     GPIO_FN_RMII_RXD0,
-        GPIO_FN_RMII_RXD1,      GPIO_FN_RMII_TX_EN,     GPIO_FN_RMII_TXD0,
-        GPIO_FN_RMII_MDC,       GPIO_FN_RMII_TXD1,      GPIO_FN_RMII_MDIO,
-        GPIO_FN_RMII_REF50CK,   /* for RMII */
-        GPIO_FN_RMII_REF125CK,  /* for GMII */
-
-        /* GEther */
-        GPIO_FN_ET_TX_CLK,      GPIO_FN_ET_TX_EN,       GPIO_FN_ET_ETXD0,
-        GPIO_FN_ET_ETXD1,       GPIO_FN_ET_ETXD2,       GPIO_FN_ET_ETXD3,
-        GPIO_FN_ET_ETXD4,       GPIO_FN_ET_ETXD5, /* for GEther */
-        GPIO_FN_ET_ETXD6,       GPIO_FN_ET_ETXD7, /* for GEther */
-        GPIO_FN_ET_COL,         GPIO_FN_ET_TX_ER,
-        GPIO_FN_ET_RX_CLK,      GPIO_FN_ET_RX_DV,
-        GPIO_FN_ET_ERXD0,       GPIO_FN_ET_ERXD1,
-        GPIO_FN_ET_ERXD2,       GPIO_FN_ET_ERXD3,
-        GPIO_FN_ET_ERXD4,       GPIO_FN_ET_ERXD5, /* for GEther */
-        GPIO_FN_ET_ERXD6,       GPIO_FN_ET_ERXD7, /* for GEther */
-        GPIO_FN_ET_RX_ER,       GPIO_FN_ET_CRS,
-        GPIO_FN_ET_MDC,         GPIO_FN_ET_MDIO,
-        GPIO_FN_ET_LINK,        GPIO_FN_ET_PHY_INT,
-        GPIO_FN_ET_WOL,         GPIO_FN_ET_GTX_CLK,
-
-        /* DMA0 */
-        GPIO_FN_DREQ0,          GPIO_FN_DACK0,
-
-        /* DMA1 */
-        GPIO_FN_DREQ1,          GPIO_FN_DACK1,
-
-        /* SYSC */
-        GPIO_FN_RESETOUTS,
-        GPIO_FN_RESETP_PULLUP,
-        GPIO_FN_RESETP_PLAIN,
-
-        /* HDMI */
-        GPIO_FN_HDMI_HPD,
-        GPIO_FN_HDMI_CEC,
-
-        /* SDENC */
-        GPIO_FN_SDENC_CPG,
-        GPIO_FN_SDENC_DV_CLKI,
-
-        /* IRREM */
-        GPIO_FN_IROUT,
-
-        /* DEBUG */
-        GPIO_FN_EDEBGREQ_PULLDOWN,
-        GPIO_FN_EDEBGREQ_PULLUP,
-
-        GPIO_FN_TRACEAUD_FROM_VIO,
-        GPIO_FN_TRACEAUD_FROM_LCDC0,
-        GPIO_FN_TRACEAUD_FROM_MEMC,
-};
-
 /* DMA slave IDs */
 enum {
         SHDMA_SLAVE_INVALID,
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7778.h b/arch/arm/mach-shmobile/include/mach/r8a7778.h
index 951149e6bcca..ae65b459483f 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7778.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7778.h
@@ -18,6 +18,7 @@
 #ifndef __ASM_R8A7778_H__
 #define __ASM_R8A7778_H__
 
+#include <linux/mmc/sh_mobile_sdhi.h>
 #include <linux/sh_eth.h>
 
 extern void r8a7778_add_standard_devices(void);
@@ -28,5 +29,7 @@ extern void r8a7778_init_irq(void);
 extern void r8a7778_init_irq_dt(void);
 extern void r8a7778_clock_init(void);
 extern void r8a7778_init_irq_extpin(int irlm);
+extern void r8a7778_pinmux_init(void);
+extern void r8a7778_sdhi_init(int id, struct sh_mobile_sdhi_info *info);
 
 #endif /* __ASM_R8A7778_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/sh7372.h b/arch/arm/mach-shmobile/include/mach/sh7372.h
index fd7cba024c39..e882717ca97f 100644
--- a/arch/arm/mach-shmobile/include/mach/sh7372.h
+++ b/arch/arm/mach-shmobile/include/mach/sh7372.h
@@ -15,397 +15,6 @@
 #include <linux/pm_domain.h>
 #include <mach/pm-rmobile.h>
 
-/*
- * Pin Function Controller:
- *      GPIO_FN_xx - GPIO used to select pin function
- *      GPIO_PORTxx - GPIO mapped to real I/O pin on CPU
- */
-enum {
-        /* PORT */
-        GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4,
-        GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9,
-
-        GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14,
-        GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19,
-
-        GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24,
-        GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29,
-
-        GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34,
-        GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39,
-
-        GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44,
-        GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49,
-
-        GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54,
-        GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59,
-
-        GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64,
-        GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69,
-
-        GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74,
-        GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79,
-
-        GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84,
-        GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89,
-
-        GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94,
-        GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99,
-
-        GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104,
-        GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109,
-
-        GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114,
-        GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, GPIO_PORT119,
-
-        GPIO_PORT120, GPIO_PORT121, GPIO_PORT122, GPIO_PORT123, GPIO_PORT124,
-        GPIO_PORT125, GPIO_PORT126, GPIO_PORT127, GPIO_PORT128, GPIO_PORT129,
-
-        GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134,
-        GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139,
-
-        GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144,
-        GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149,
-
-        GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154,
-        GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159,
-
-        GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164,
-        GPIO_PORT165, GPIO_PORT166, GPIO_PORT167, GPIO_PORT168, GPIO_PORT169,
-
-        GPIO_PORT170, GPIO_PORT171, GPIO_PORT172, GPIO_PORT173, GPIO_PORT174,
-        GPIO_PORT175, GPIO_PORT176, GPIO_PORT177, GPIO_PORT178, GPIO_PORT179,
-
-        GPIO_PORT180, GPIO_PORT181, GPIO_PORT182, GPIO_PORT183, GPIO_PORT184,
-        GPIO_PORT185, GPIO_PORT186, GPIO_PORT187, GPIO_PORT188, GPIO_PORT189,
-
-        GPIO_PORT190,
-
-        /* IRQ */
-        GPIO_FN_IRQ0_6,         /* PORT   6 */
-        GPIO_FN_IRQ0_162,       /* PORT 162 */
-        GPIO_FN_IRQ1,           /* PORT  12 */
-        GPIO_FN_IRQ2_4,         /* PORT   4 */
-        GPIO_FN_IRQ2_5,         /* PORT   5 */
-        GPIO_FN_IRQ3_8,         /* PORT   8 */
-        GPIO_FN_IRQ3_16,        /* PORT  16 */
-        GPIO_FN_IRQ4_17,        /* PORT  17 */
-        GPIO_FN_IRQ4_163,       /* PORT 163 */
-        GPIO_FN_IRQ5,           /* PORT  18 */
-        GPIO_FN_IRQ6_39,        /* PORT  39 */
-        GPIO_FN_IRQ6_164,       /* PORT 164 */
-        GPIO_FN_IRQ7_40,        /* PORT  40 */
-        GPIO_FN_IRQ7_167,       /* PORT 167 */
-        GPIO_FN_IRQ8_41,        /* PORT  41 */
-        GPIO_FN_IRQ8_168,       /* PORT 168 */
-        GPIO_FN_IRQ9_42,        /* PORT  42 */
-        GPIO_FN_IRQ9_169,       /* PORT 169 */
-        GPIO_FN_IRQ10,          /* PORT  65 */
-        GPIO_FN_IRQ11,          /* PORT  67 */
-        GPIO_FN_IRQ12_80,       /* PORT  80 */
-        GPIO_FN_IRQ12_137,      /* PORT 137 */
-        GPIO_FN_IRQ13_81,       /* PORT  81 */
-        GPIO_FN_IRQ13_145,      /* PORT 145 */
-        GPIO_FN_IRQ14_82,       /* PORT  82 */
-        GPIO_FN_IRQ14_146,      /* PORT 146 */
-        GPIO_FN_IRQ15_83,       /* PORT  83 */
-        GPIO_FN_IRQ15_147,      /* PORT 147 */
-        GPIO_FN_IRQ16_84,       /* PORT  84 */
-        GPIO_FN_IRQ16_170,      /* PORT 170 */
-        GPIO_FN_IRQ17,          /* PORT  85 */
-        GPIO_FN_IRQ18,          /* PORT  86 */
-        GPIO_FN_IRQ19,          /* PORT  87 */
-        GPIO_FN_IRQ20,          /* PORT  92 */
-        GPIO_FN_IRQ21,          /* PORT  93 */
-        GPIO_FN_IRQ22,          /* PORT  94 */
-        GPIO_FN_IRQ23,          /* PORT  95 */
-        GPIO_FN_IRQ24,          /* PORT 112 */
-        GPIO_FN_IRQ25,          /* PORT 119 */
-        GPIO_FN_IRQ26_121,      /* PORT 121 */
-        GPIO_FN_IRQ26_172,      /* PORT 172 */
-        GPIO_FN_IRQ27_122,      /* PORT 122 */
-        GPIO_FN_IRQ27_180,      /* PORT 180 */
-        GPIO_FN_IRQ28_123,      /* PORT 123 */
-        GPIO_FN_IRQ28_181,      /* PORT 181 */
-        GPIO_FN_IRQ29_129,      /* PORT 129 */
-        GPIO_FN_IRQ29_182,      /* PORT 182 */
-        GPIO_FN_IRQ30_130,      /* PORT 130 */
-        GPIO_FN_IRQ30_183,      /* PORT 183 */
-        GPIO_FN_IRQ31_138,      /* PORT 138 */
-        GPIO_FN_IRQ31_184,      /* PORT 184 */
-
-        /*
-         * MSIOF0       (PORT 36, 37, 38, 39
-         *                    40, 41, 42, 43, 44, 45)
-         */
-        GPIO_FN_MSIOF0_TSYNC,   GPIO_FN_MSIOF0_TSCK,
-        GPIO_FN_MSIOF0_RXD,     GPIO_FN_MSIOF0_RSCK,
-        GPIO_FN_MSIOF0_RSYNC,   GPIO_FN_MSIOF0_MCK0,
-        GPIO_FN_MSIOF0_MCK1,    GPIO_FN_MSIOF0_SS1,
-        GPIO_FN_MSIOF0_SS2,     GPIO_FN_MSIOF0_TXD,
-
-        /*
-         * MSIOF1       (PORT 39, 40, 41, 42, 43, 44
-         *                    84, 85, 86, 87, 88, 89, 90, 91, 92, 93)
-         */
-        GPIO_FN_MSIOF1_TSCK_39, GPIO_FN_MSIOF1_TSYNC_40,
-        GPIO_FN_MSIOF1_TSCK_88, GPIO_FN_MSIOF1_TSYNC_89,
-        GPIO_FN_MSIOF1_TXD_41,  GPIO_FN_MSIOF1_RXD_42,
-        GPIO_FN_MSIOF1_TXD_90,  GPIO_FN_MSIOF1_RXD_91,
-        GPIO_FN_MSIOF1_SS1_43,  GPIO_FN_MSIOF1_SS2_44,
-        GPIO_FN_MSIOF1_SS1_92,  GPIO_FN_MSIOF1_SS2_93,
-        GPIO_FN_MSIOF1_RSCK,    GPIO_FN_MSIOF1_RSYNC,
-        GPIO_FN_MSIOF1_MCK0,    GPIO_FN_MSIOF1_MCK1,
-
-        /*
-         * MSIOF2       (PORT 134, 135, 136, 137, 138, 139
-         *                    148, 149, 150, 151)
-         */
-        GPIO_FN_MSIOF2_RSCK,    GPIO_FN_MSIOF2_RSYNC,
-        GPIO_FN_MSIOF2_MCK0,    GPIO_FN_MSIOF2_MCK1,
-        GPIO_FN_MSIOF2_SS1,     GPIO_FN_MSIOF2_SS2,
-        GPIO_FN_MSIOF2_TSYNC,   GPIO_FN_MSIOF2_TSCK,
-        GPIO_FN_MSIOF2_RXD,     GPIO_FN_MSIOF2_TXD,
-
-        /* MSIOF3       (PORT 76, 77, 78, 79, 80, 81, 82, 83) */
-        GPIO_FN_BBIF1_RXD,      GPIO_FN_BBIF1_TSYNC,
-        GPIO_FN_BBIF1_TSCK,     GPIO_FN_BBIF1_TXD,
-        GPIO_FN_BBIF1_RSCK,     GPIO_FN_BBIF1_RSYNC,
-        GPIO_FN_BBIF1_FLOW,     GPIO_FN_BB_RX_FLOW_N,
-
-        /* MSIOF4       (PORT 0, 1, 2, 3) */
-        GPIO_FN_BBIF2_TSCK1,    GPIO_FN_BBIF2_TSYNC1,
-        GPIO_FN_BBIF2_TXD1,     GPIO_FN_BBIF2_RXD,
-
-        /* FSI          (PORT 4, 5, 6, 7, 8, 9, 10, 11, 15) */
-        GPIO_FN_FSIACK,         GPIO_FN_FSIBCK,
-        GPIO_FN_FSIAILR,        GPIO_FN_FSIAIBT,
-        GPIO_FN_FSIAISLD,       GPIO_FN_FSIAOMC,
-        GPIO_FN_FSIAOLR,        GPIO_FN_FSIAOBT,
-        GPIO_FN_FSIAOSLD,       GPIO_FN_FSIASPDIF_11,
-        GPIO_FN_FSIASPDIF_15,
-
-        /* FMSI         (PORT 12, 13, 14, 15, 16, 17, 18, 65) */
-        GPIO_FN_FMSOCK,         GPIO_FN_FMSOOLR,
-        GPIO_FN_FMSIOLR,        GPIO_FN_FMSOOBT,
-        GPIO_FN_FMSIOBT,        GPIO_FN_FMSOSLD,
-        GPIO_FN_FMSOILR,        GPIO_FN_FMSIILR,
-        GPIO_FN_FMSOIBT,        GPIO_FN_FMSIIBT,
-        GPIO_FN_FMSISLD,        GPIO_FN_FMSICK,
-
-        /* SCIFA0       (PORT 152, 153, 156, 157, 158) */
-        GPIO_FN_SCIFA0_TXD,     GPIO_FN_SCIFA0_RXD,
-        GPIO_FN_SCIFA0_SCK,     GPIO_FN_SCIFA0_RTS,
-        GPIO_FN_SCIFA0_CTS,
-
-        /* SCIFA1       (PORT 154, 155, 159, 160, 161) */
-        GPIO_FN_SCIFA1_TXD,     GPIO_FN_SCIFA1_RXD,
-        GPIO_FN_SCIFA1_SCK,     GPIO_FN_SCIFA1_RTS,
-        GPIO_FN_SCIFA1_CTS,
-
-        /* SCIFA2       (PORT 94, 95, 96, 97, 98) */
-        GPIO_FN_SCIFA2_CTS1,    GPIO_FN_SCIFA2_RTS1,
-        GPIO_FN_SCIFA2_TXD1,    GPIO_FN_SCIFA2_RXD1,
-        GPIO_FN_SCIFA2_SCK1,
-
-        /* SCIFA3       (PORT 43, 44,
-                             140, 141, 142, 143, 144) */
-        GPIO_FN_SCIFA3_CTS_43,  GPIO_FN_SCIFA3_CTS_140,
-        GPIO_FN_SCIFA3_RTS_44,  GPIO_FN_SCIFA3_RTS_141,
-        GPIO_FN_SCIFA3_SCK,     GPIO_FN_SCIFA3_TXD,
-        GPIO_FN_SCIFA3_RXD,
-
-        /* SCIFA4       (PORT 5, 6) */
-        GPIO_FN_SCIFA4_RXD,     GPIO_FN_SCIFA4_TXD,
-
-        /* SCIFA5       (PORT 8, 12) */
-        GPIO_FN_SCIFA5_RXD,     GPIO_FN_SCIFA5_TXD,
-
-        /* SCIFB        (PORT 162, 163, 164, 165, 166) */
-        GPIO_FN_SCIFB_SCK,      GPIO_FN_SCIFB_RTS,
-        GPIO_FN_SCIFB_CTS,      GPIO_FN_SCIFB_TXD,
-        GPIO_FN_SCIFB_RXD,
-
-        /*
-         * CEU          (PORT 16, 17,
-         *                    100, 101, 102, 103, 104, 105, 106, 107, 108, 109,
-         *                    110, 111, 112, 113, 114, 115, 116, 117, 118, 119,
-         *                    120)
-         */
-        GPIO_FN_VIO_HD,         GPIO_FN_VIO_CKO1,       GPIO_FN_VIO_CKO2,
-        GPIO_FN_VIO_VD,         GPIO_FN_VIO_CLK,        GPIO_FN_VIO_FIELD,
-        GPIO_FN_VIO_CKO,
-        GPIO_FN_VIO_D0,         GPIO_FN_VIO_D1,         GPIO_FN_VIO_D2,
-        GPIO_FN_VIO_D3,         GPIO_FN_VIO_D4,         GPIO_FN_VIO_D5,
-        GPIO_FN_VIO_D6,         GPIO_FN_VIO_D7,         GPIO_FN_VIO_D8,
-        GPIO_FN_VIO_D9,         GPIO_FN_VIO_D10,        GPIO_FN_VIO_D11,
-        GPIO_FN_VIO_D12,        GPIO_FN_VIO_D13,        GPIO_FN_VIO_D14,
-        GPIO_FN_VIO_D15,
-
-        /* USB0         (PORT 113, 114, 115, 116, 117, 167) */
-        GPIO_FN_IDIN_0,         GPIO_FN_EXTLP_0,
-        GPIO_FN_OVCN2_0,        GPIO_FN_PWEN_0,
-        GPIO_FN_OVCN_0,         GPIO_FN_VBUS0_0,
-
-        /* USB1         (PORT 18, 113, 114, 115, 116, 117, 138, 162, 168) */
-        GPIO_FN_IDIN_1_18,      GPIO_FN_IDIN_1_113,
-        GPIO_FN_PWEN_1_115,     GPIO_FN_PWEN_1_138,
-        GPIO_FN_OVCN_1_114,     GPIO_FN_OVCN_1_162,
-        GPIO_FN_EXTLP_1,        GPIO_FN_OVCN2_1,
-        GPIO_FN_VBUS0_1,
-
-        /* GPIO         (PORT 41, 42, 43, 44) */
-        GPIO_FN_GPI0,   GPIO_FN_GPI1,   GPIO_FN_GPO0,   GPIO_FN_GPO1,
-
-        /*
-         * BSC          (PORT 19,
-         *                    20, 21, 22, 25, 26, 27, 28, 29,
-         *                    30, 31, 32, 33, 34, 35, 36, 37, 38, 39,
-         *                    40, 41, 42, 43, 44, 45,
-         *                    62, 63, 64, 65, 66, 67,
-         *                    71, 72, 74, 75)
-         */
-        GPIO_FN_BS,     GPIO_FN_WE1,
-        GPIO_FN_CKO,    GPIO_FN_WAIT,   GPIO_FN_RDWR,
-
-        GPIO_FN_A0,     GPIO_FN_A1,     GPIO_FN_A2,     GPIO_FN_A3,
-        GPIO_FN_A6,     GPIO_FN_A7,     GPIO_FN_A8,     GPIO_FN_A9,
-        GPIO_FN_A10,    GPIO_FN_A11,    GPIO_FN_A12,    GPIO_FN_A13,
-        GPIO_FN_A14,    GPIO_FN_A15,    GPIO_FN_A16,    GPIO_FN_A17,
-        GPIO_FN_A18,    GPIO_FN_A19,    GPIO_FN_A20,    GPIO_FN_A21,
-        GPIO_FN_A22,    GPIO_FN_A23,    GPIO_FN_A24,    GPIO_FN_A25,
-        GPIO_FN_A26,
-
-        GPIO_FN_CS0,    GPIO_FN_CS2,    GPIO_FN_CS4,
-        GPIO_FN_CS5A,   GPIO_FN_CS5B,   GPIO_FN_CS6A,
-
-        /*
-         * BSC/FLCTL            (PORT 23, 24,
-         *                            46, 47, 48, 49,
-         *                            50, 51, 52, 53, 54, 55, 56, 57, 58, 59,
-         *                            60, 61, 69, 70)
-         */
-        GPIO_FN_RD_FSC,         GPIO_FN_WE0_FWE,
-        GPIO_FN_A4_FOE,         GPIO_FN_A5_FCDE,
-        GPIO_FN_D0_NAF0,        GPIO_FN_D1_NAF1,        GPIO_FN_D2_NAF2,
-        GPIO_FN_D3_NAF3,        GPIO_FN_D4_NAF4,        GPIO_FN_D5_NAF5,
-        GPIO_FN_D6_NAF6,        GPIO_FN_D7_NAF7,        GPIO_FN_D8_NAF8,
-        GPIO_FN_D9_NAF9,        GPIO_FN_D10_NAF10,      GPIO_FN_D11_NAF11,
-        GPIO_FN_D12_NAF12,      GPIO_FN_D13_NAF13,      GPIO_FN_D14_NAF14,
-        GPIO_FN_D15_NAF15,
-
-        /* SPU2         (PORT 65) */
-        GPIO_FN_VINT_I,
-
-        /* FLCTL        (PORT 66, 68, 73) */
-        GPIO_FN_FCE1,   GPIO_FN_FCE0,   GPIO_FN_FRB,
-
-        /* HSI          (PORT 76, 77, 78, 79, 80, 81, 82, 83) */
-        GPIO_FN_GP_RX_FLAG,     GPIO_FN_GP_RX_DATA,     GPIO_FN_GP_TX_READY,
-        GPIO_FN_GP_RX_WAKE,     GPIO_FN_MP_TX_FLAG,     GPIO_FN_MP_TX_DATA,
-        GPIO_FN_MP_RX_READY,    GPIO_FN_MP_TX_WAKE,
-
-        /*
-         * MFI          (PORT 76, 77, 78, 79,
-         *                    80, 81, 82, 83, 84, 85, 86, 87, 88, 89,
-         *                    90, 91, 92, 93, 94, 95, 96, 97, 98, 99)
-         */
-        GPIO_FN_MFIv6,  /* see MSEL4CR 6 */
-        GPIO_FN_MFIv4,  /* see MSEL4CR 6 */
-
-        GPIO_FN_MEMC_CS0,               GPIO_FN_MEMC_BUSCLK_MEMC_A0,
-        GPIO_FN_MEMC_CS1_MEMC_A1,       GPIO_FN_MEMC_ADV_MEMC_DREQ0,
-        GPIO_FN_MEMC_WAIT_MEMC_DREQ1,   GPIO_FN_MEMC_NOE,
-        GPIO_FN_MEMC_NWE,               GPIO_FN_MEMC_INT,
-
-        GPIO_FN_MEMC_AD0,       GPIO_FN_MEMC_AD1,       GPIO_FN_MEMC_AD2,
-        GPIO_FN_MEMC_AD3,       GPIO_FN_MEMC_AD4,       GPIO_FN_MEMC_AD5,
-        GPIO_FN_MEMC_AD6,       GPIO_FN_MEMC_AD7,       GPIO_FN_MEMC_AD8,
-        GPIO_FN_MEMC_AD9,       GPIO_FN_MEMC_AD10,      GPIO_FN_MEMC_AD11,
-        GPIO_FN_MEMC_AD12,      GPIO_FN_MEMC_AD13,      GPIO_FN_MEMC_AD14,
-        GPIO_FN_MEMC_AD15,
-
-        /* SIM          (PORT 94, 95, 98) */
-        GPIO_FN_SIM_RST,        GPIO_FN_SIM_CLK,        GPIO_FN_SIM_D,
-
-        /* TPU          (PORT 93, 99, 112, 160, 161) */
-        GPIO_FN_TPU0TO0,        GPIO_FN_TPU0TO1,
-        GPIO_FN_TPU0TO2_93,     GPIO_FN_TPU0TO2_99,
-        GPIO_FN_TPU0TO3,
-
-        /* I2C2         (PORT 110, 111) */
-        GPIO_FN_I2C_SCL2,       GPIO_FN_I2C_SDA2,
-
-        /* I2C3(1)      (PORT 114, 115) */
-        GPIO_FN_I2C_SCL3,       GPIO_FN_I2C_SDA3,
-
-        /* I2C3(2)      (PORT 137, 145) */
-        GPIO_FN_I2C_SCL3S,      GPIO_FN_I2C_SDA3S,
-
-        /* I2C4(2)      (PORT 116, 117) */
-        GPIO_FN_I2C_SCL4,       GPIO_FN_I2C_SDA4,
-
-        /* I2C4(2)      (PORT 146, 147) */
-        GPIO_FN_I2C_SCL4S,      GPIO_FN_I2C_SDA4S,
-
-        /*
-         * KEYSC        (PORT 121, 122, 123, 124, 125, 126, 127, 128, 129,
-         *                    130, 131, 132, 133, 134, 135, 136)
-         */
-        GPIO_FN_KEYOUT0,        GPIO_FN_KEYIN0_121,     GPIO_FN_KEYIN0_136,
-        GPIO_FN_KEYOUT1,        GPIO_FN_KEYIN1_122,     GPIO_FN_KEYIN1_135,
-        GPIO_FN_KEYOUT2,        GPIO_FN_KEYIN2_123,     GPIO_FN_KEYIN2_134,
-        GPIO_FN_KEYOUT3,        GPIO_FN_KEYIN3_124,     GPIO_FN_KEYIN3_133,
-        GPIO_FN_KEYOUT4,        GPIO_FN_KEYIN4,
-        GPIO_FN_KEYOUT5,        GPIO_FN_KEYIN5,
-        GPIO_FN_KEYOUT6,        GPIO_FN_KEYIN6,
-        GPIO_FN_KEYOUT7,        GPIO_FN_KEYIN7,
-
-        /*
-         * LCDC         (PORT      121, 122, 123, 124, 125, 126, 127, 128, 129,
-         *                    130, 131, 132, 133, 134, 135, 136, 137, 138, 139,
-         *                    140, 141, 142, 143, 144, 145, 146, 147, 148, 149,
-         *                    150, 151)
-         */
-        GPIO_FN_LCDC0_SELECT, /* LCDC 0 */
-        GPIO_FN_LCDC1_SELECT, /* LCDC 1 */
-        GPIO_FN_LCDHSYN,        GPIO_FN_LCDCS,  GPIO_FN_LCDVSYN,
-        GPIO_FN_LCDDCK,         GPIO_FN_LCDWR,  GPIO_FN_LCDRD,
-        GPIO_FN_LCDDISP,        GPIO_FN_LCDRS,  GPIO_FN_LCDLCLK,
-        GPIO_FN_LCDDON,
-
-        GPIO_FN_LCDD0,  GPIO_FN_LCDD1,  GPIO_FN_LCDD2,  GPIO_FN_LCDD3,
-        GPIO_FN_LCDD4,  GPIO_FN_LCDD5,  GPIO_FN_LCDD6,  GPIO_FN_LCDD7,
-        GPIO_FN_LCDD8,  GPIO_FN_LCDD9,  GPIO_FN_LCDD10, GPIO_FN_LCDD11,
-        GPIO_FN_LCDD12, GPIO_FN_LCDD13, GPIO_FN_LCDD14, GPIO_FN_LCDD15,
-        GPIO_FN_LCDD16, GPIO_FN_LCDD17, GPIO_FN_LCDD18, GPIO_FN_LCDD19,
-        GPIO_FN_LCDD20, GPIO_FN_LCDD21, GPIO_FN_LCDD22, GPIO_FN_LCDD23,
-
-        /* IRDA         (PORT 139, 140, 141, 142) */
-        GPIO_FN_IRDA_OUT,       GPIO_FN_IRDA_IN,        GPIO_FN_IRDA_FIRSEL,
-        GPIO_FN_IROUT_139,      GPIO_FN_IROUT_140,
-
-        /* TSIF1        (PORT 156, 157, 158, 159) */
-        GPIO_FN_TS0_1SELECT, /* TSIF0 - 1 select */
-        GPIO_FN_TS0_2SELECT, /* TSIF0 - 2 select */
-        GPIO_FN_TS1_1SELECT, /* TSIF1 - 1 select */
-        GPIO_FN_TS1_2SELECT, /* TSIF1 - 2 select */
-
-        GPIO_FN_TS_SPSYNC1,     GPIO_FN_TS_SDAT1,
-        GPIO_FN_TS_SDEN1,       GPIO_FN_TS_SCK1,
-
-        /* TSIF2        (PORT 137, 145, 146, 147) */
-        GPIO_FN_TS_SPSYNC2,     GPIO_FN_TS_SDAT2,
-        GPIO_FN_TS_SDEN2,       GPIO_FN_TS_SCK2,
-
-        /* HDMI         (PORT 169, 170) */
-        GPIO_FN_HDMI_HPD,       GPIO_FN_HDMI_CEC,
-
-        /* SDENC        see MSEL4CR 19 */
-        GPIO_FN_SDENC_CPG,
-        GPIO_FN_SDENC_DV_CLKI,
-};
-
 /* DMA slave IDs */
 enum {
         SHDMA_SLAVE_INVALID,
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index 326a4ab0bd5f..3a6b6fe7b6c0 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -70,29 +70,15 @@ void __init r8a7740_map_io(void)
 }
 
 /* PFC */
-static struct resource r8a7740_pfc_resources[] = {
-        [0] = {
-                .start  = 0xe6050000,
-                .end    = 0xe6057fff,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = 0xe605800c,
-                .end    = 0xe605802b,
-                .flags  = IORESOURCE_MEM,
-        }
-};
-
-static struct platform_device r8a7740_pfc_device = {
-        .name           = "pfc-r8a7740",
-        .id             = -1,
-        .resource       = r8a7740_pfc_resources,
-        .num_resources  = ARRAY_SIZE(r8a7740_pfc_resources),
+static const struct resource pfc_resources[] = {
+        DEFINE_RES_MEM(0xe6050000, 0x8000),
+        DEFINE_RES_MEM(0xe605800c, 0x0020),
 };
 
 void __init r8a7740_pinmux_init(void)
 {
-        platform_device_register(&r8a7740_pfc_device);
+        platform_device_register_simple("pfc-r8a7740", -1, pfc_resources,
+                                        ARRAY_SIZE(pfc_resources));
 }
 
 static struct renesas_intc_irqpin_config irqpin0_platform_data = {
diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c
index 30b4a336308f..1b9b7f2a5016 100644
--- a/arch/arm/mach-shmobile/setup-r8a7778.c
+++ b/arch/arm/mach-shmobile/setup-r8a7778.c
@@ -24,6 +24,7 @@
 #include <linux/irqchip/arm-gic.h>
 #include <linux/of.h>
 #include <linux/of_platform.h>
+#include <linux/platform_data/gpio-rcar.h>
 #include <linux/platform_data/irq-renesas-intc-irqpin.h>
 #include <linux/platform_device.h>
 #include <linux/irqchip.h>
@@ -80,12 +81,6 @@ static struct sh_timer_config sh_tmu1_platform_data = {
         .clocksource_rating     = 200,
 };
 
-/* Ether */
-static struct resource ether_resources[] = {
-        DEFINE_RES_MEM(0xfde00000, 0x400),
-        DEFINE_RES_IRQ(gic_iid(0x89)),
-};
-
 #define r8a7778_register_tmu(idx)                       \
         platform_device_register_resndata(              \
                 &platform_bus, "sh_tmu", idx,           \
@@ -94,6 +89,90 @@ static struct resource ether_resources[] = {
                 &sh_tmu##idx##_platform_data,           \
                 sizeof(sh_tmu##idx##_platform_data))
 
+/* Ether */
+static struct resource ether_resources[] = {
+        DEFINE_RES_MEM(0xfde00000, 0x400),
+        DEFINE_RES_IRQ(gic_iid(0x89)),
+};
+
+void __init r8a7778_add_ether_device(struct sh_eth_plat_data *pdata)
+{
+        platform_device_register_resndata(&platform_bus, "sh_eth", -1,
+                                          ether_resources,
+                                          ARRAY_SIZE(ether_resources),
+                                          pdata, sizeof(*pdata));
+}
+
+/* PFC/GPIO */
+static struct resource pfc_resources[] = {
+        DEFINE_RES_MEM(0xfffc0000, 0x118),
+};
+
+#define R8A7778_GPIO(idx)                                               \
+static struct resource r8a7778_gpio##idx##_resources[] = {              \
+        DEFINE_RES_MEM(0xffc40000 + 0x1000 * (idx), 0x30),              \
+        DEFINE_RES_IRQ(gic_iid(0x87)),                                  \
+};                                                                      \
+                                                                        \
+static struct gpio_rcar_config r8a7778_gpio##idx##_platform_data = {    \
+        .gpio_base      = 32 * (idx),                                   \
+        .irq_base       = GPIO_IRQ_BASE(idx),                           \
+        .number_of_pins = 32,                                           \
+        .pctl_name      = "pfc-r8a7778",                                \
+}
+
+R8A7778_GPIO(0);
+R8A7778_GPIO(1);
+R8A7778_GPIO(2);
+R8A7778_GPIO(3);
+R8A7778_GPIO(4);
+
+#define r8a7778_register_gpio(idx)                              \
+        platform_device_register_resndata(                      \
+                &platform_bus, "gpio_rcar", idx,                \
+                r8a7778_gpio##idx##_resources,                  \
+                ARRAY_SIZE(r8a7778_gpio##idx##_resources),      \
+                &r8a7778_gpio##idx##_platform_data,             \
+                sizeof(r8a7778_gpio##idx##_platform_data))
+
+void __init r8a7778_pinmux_init(void)
+{
+        platform_device_register_simple(
+                "pfc-r8a7778", -1,
+                pfc_resources,
+                ARRAY_SIZE(pfc_resources));
+
+        r8a7778_register_gpio(0);
+        r8a7778_register_gpio(1);
+        r8a7778_register_gpio(2);
+        r8a7778_register_gpio(3);
+        r8a7778_register_gpio(4);
+};
+
+/* SDHI */
+static struct resource sdhi_resources[] = {
+        /* SDHI0 */
+        DEFINE_RES_MEM(0xFFE4C000, 0x100),
+        DEFINE_RES_IRQ(gic_iid(0x77)),
+        /* SDHI1 */
+        DEFINE_RES_MEM(0xFFE4D000, 0x100),
+        DEFINE_RES_IRQ(gic_iid(0x78)),
+        /* SDHI2 */
+        DEFINE_RES_MEM(0xFFE4F000, 0x100),
+        DEFINE_RES_IRQ(gic_iid(0x76)),
+};
+
+void __init r8a7778_sdhi_init(int id,
+                              struct sh_mobile_sdhi_info *info)
+{
+        BUG_ON(id < 0 || id > 2);
+
+        platform_device_register_resndata(
+                &platform_bus, "sh_mobile_sdhi", id,
+                sdhi_resources + (2 * id), 2,
+                info, sizeof(*info));
+}
+
 void __init r8a7778_add_standard_devices(void)
 {
         int i;
@@ -118,14 +197,6 @@ void __init r8a7778_add_standard_devices(void)
         r8a7778_register_tmu(1);
 }
 
-void __init r8a7778_add_ether_device(struct sh_eth_plat_data *pdata)
-{
-        platform_device_register_resndata(&platform_bus, "sh_eth", -1,
-                                          ether_resources,
-                                          ARRAY_SIZE(ether_resources),
-                                          pdata, sizeof(*pdata));
-}
-
 static struct renesas_intc_irqpin_config irqpin_platform_data = {
         .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
         .sense_bitfield_width = 2,
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index b0b394842ea5..dbb13f289e79 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -65,11 +65,7 @@ void __init r8a7779_map_io(void)
 }
 
 static struct resource r8a7779_pfc_resources[] = {
-        [0] = {
-                .start  = 0xfffc0000,
-                .end    = 0xfffc023b,
-                .flags  = IORESOURCE_MEM,
-        },
+        DEFINE_RES_MEM(0xfffc0000, 0x023c),
 };
 
 static struct platform_device r8a7779_pfc_device = {
@@ -81,15 +77,8 @@ static struct platform_device r8a7779_pfc_device = {
 
 #define R8A7779_GPIO(idx, npins) \
 static struct resource r8a7779_gpio##idx##_resources[] = {              \
-        [0] = {                                                         \
-                .start  = 0xffc40000 + 0x1000 * (idx),                  \
-                .end    = 0xffc4002b + 0x1000 * (idx),                  \
-                .flags  = IORESOURCE_MEM,                               \
-        },                                                              \
-        [1] = {                                                         \
-                .start  = gic_iid(0xad + (idx)),                        \
-                .flags  = IORESOURCE_IRQ,                               \
-        }                                                               \
+        DEFINE_RES_MEM(0xffc40000 + (0x1000 * (idx)), 0x002c),          \
+        DEFINE_RES_IRQ(gic_iid(0xad + (idx))),                          \
 };                                                                      \
                                                                         \
 static struct gpio_rcar_config r8a7779_gpio##idx##_platform_data = {    \
diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
index 49de2d56f86d..b461d93431ed 100644
--- a/arch/arm/mach-shmobile/setup-r8a7790.c
+++ b/arch/arm/mach-shmobile/setup-r8a7790.c
@@ -23,6 +23,7 @@
 #include <linux/kernel.h>
 #include <linux/of_platform.h>
 #include <linux/serial_sci.h>
+#include <linux/platform_data/gpio-rcar.h>
 #include <linux/platform_data/irq-renesas-irqc.h>
 #include <mach/common.h>
 #include <mach/irqs.h>
@@ -31,13 +32,46 @@
 
 static const struct resource pfc_resources[] = {
         DEFINE_RES_MEM(0xe6060000, 0x250),
-        DEFINE_RES_MEM(0xe6050000, 0x5050),
 };
 
+#define R8A7790_GPIO(idx)                                               \
+static struct resource r8a7790_gpio##idx##_resources[] = {              \
+        DEFINE_RES_MEM(0xe6050000 + 0x1000 * (idx), 0x50),              \
+        DEFINE_RES_IRQ(gic_spi(4 + (idx))),                             \
+};                                                                      \
+                                                                        \
+static struct gpio_rcar_config r8a7790_gpio##idx##_platform_data = {    \
+        .gpio_base      = 32 * (idx),                                   \
+        .irq_base       = 0,                                            \
+        .number_of_pins = 32,                                           \
+        .pctl_name      = "pfc-r8a7790",                                \
+        .has_both_edge_trigger = 1,                                     \
+};                                                                      \
+
+R8A7790_GPIO(0);
+R8A7790_GPIO(1);
+R8A7790_GPIO(2);
+R8A7790_GPIO(3);
+R8A7790_GPIO(4);
+R8A7790_GPIO(5);
+
+#define r8a7790_register_gpio(idx)                                      \
+        platform_device_register_resndata(&platform_bus, "gpio_rcar", idx, \
+                r8a7790_gpio##idx##_resources,                          \
+                ARRAY_SIZE(r8a7790_gpio##idx##_resources),              \
+                &r8a7790_gpio##idx##_platform_data,                     \
+                sizeof(r8a7790_gpio##idx##_platform_data))
+
 void __init r8a7790_pinmux_init(void)
 {
         platform_device_register_simple("pfc-r8a7790", -1, pfc_resources,
                                         ARRAY_SIZE(pfc_resources));
+        r8a7790_register_gpio(0);
+        r8a7790_register_gpio(1);
+        r8a7790_register_gpio(2);
+        r8a7790_register_gpio(3);
+        r8a7790_register_gpio(4);
+        r8a7790_register_gpio(5);
 }
 
 #define SCIF_COMMON(scif_type, baseaddr, irq)                   \
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index 9696f3646864..96e7ca1e4e11 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -288,12 +288,7 @@ static struct sh_timer_config tmu00_platform_data = {
 };
 
 static struct resource tmu00_resources[] = {
-        [0] = {
-                .name   = "TMU00",
-                .start  = 0xfff60008,
-                .end    = 0xfff60013,
-                .flags  = IORESOURCE_MEM,
-        },
+        [0] = DEFINE_RES_MEM_NAMED(0xfff60008, 0xc, "TMU00"),
         [1] = {
                 .start  = intcs_evt2irq(0x0e80), /* TMU0_TUNI00 */
                 .flags  = IORESOURCE_IRQ,
@@ -318,12 +313,7 @@ static struct sh_timer_config tmu01_platform_data = {
 };
 
 static struct resource tmu01_resources[] = {
-        [0] = {
-                .name   = "TMU01",
-                .start  = 0xfff60014,
-                .end    = 0xfff6001f,
-                .flags  = IORESOURCE_MEM,
-        },
+        [0] = DEFINE_RES_MEM_NAMED(0xfff60014, 0xc, "TMU00"),
         [1] = {
                 .start  = intcs_evt2irq(0x0ea0), /* TMU0_TUNI01 */
                 .flags  = IORESOURCE_IRQ,
@@ -341,12 +331,7 @@ static struct platform_device tmu01_device = {
 };
 
 static struct resource i2c0_resources[] = {
-        [0] = {
-                .name   = "IIC0",
-                .start  = 0xe6820000,
-                .end    = 0xe6820425 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
+        [0] = DEFINE_RES_MEM_NAMED(0xe6820000, 0x426, "IIC0"),
         [1] = {
                 .start  = gic_spi(167),
                 .end    = gic_spi(170),
@@ -355,12 +340,7 @@ static struct resource i2c0_resources[] = {
 };
 
 static struct resource i2c1_resources[] = {
-        [0] = {
-                .name   = "IIC1",
-                .start  = 0xe6822000,
-                .end    = 0xe6822425 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
+        [0] = DEFINE_RES_MEM_NAMED(0xe6822000, 0x426, "IIC1"),
         [1] = {
                 .start  = gic_spi(51),
                 .end    = gic_spi(54),
@@ -369,12 +349,7 @@ static struct resource i2c1_resources[] = {
 };
 
 static struct resource i2c2_resources[] = {
-        [0] = {
-                .name   = "IIC2",
-                .start  = 0xe6824000,
-                .end    = 0xe6824425 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
+        [0] = DEFINE_RES_MEM_NAMED(0xe6824000, 0x426, "IIC2"),
         [1] = {
                 .start  = gic_spi(171),
                 .end    = gic_spi(174),
@@ -383,12 +358,7 @@ static struct resource i2c2_resources[] = {
 };
 
 static struct resource i2c3_resources[] = {
-        [0] = {
-                .name   = "IIC3",
-                .start  = 0xe6826000,
-                .end    = 0xe6826425 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
+        [0] = DEFINE_RES_MEM_NAMED(0xe6826000, 0x426, "IIC3"),
         [1] = {
                 .start  = gic_spi(183),
                 .end    = gic_spi(186),
@@ -397,12 +367,7 @@ static struct resource i2c3_resources[] = {
 };
 
 static struct resource i2c4_resources[] = {
-        [0] = {
-                .name   = "IIC4",
-                .start  = 0xe6828000,
-                .end    = 0xe6828425 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
+        [0] = DEFINE_RES_MEM_NAMED(0xe6828000, 0x426, "IIC4"),
         [1] = {
                 .start  = gic_spi(187),
                 .end    = gic_spi(190),
@@ -623,12 +588,7 @@ static struct sh_dmae_pdata sh73a0_dmae_platform_data = {
 };
 
 static struct resource sh73a0_dmae_resources[] = {
-        {
-                /* Registers including DMAOR and channels including DMARSx */
-                .start  = 0xfe000020,
-                .end    = 0xfe008a00 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
+        DEFINE_RES_MEM(0xfe000020, 0x89e0),
         {
                 .name   = "error_irq",
                 .start  = gic_spi(129),
@@ -727,18 +687,10 @@ static struct sh_dmae_pdata sh73a0_mpdma_platform_data = {
 
 /* Resource order important! */
 static struct resource sh73a0_mpdma_resources[] = {
-        {
-                /* Channel registers and DMAOR */
-                .start  = 0xec618020,
-                .end    = 0xec61828f,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                /* DMARSx */
-                .start  = 0xec619000,
-                .end    = 0xec61900b,
-                .flags  = IORESOURCE_MEM,
-        },
+        /* Channel registers and DMAOR */
+        DEFINE_RES_MEM(0xec618020, 0x270),
+        /* DMARSx */
+        DEFINE_RES_MEM(0xec619000, 0xc),
         {
                 .name   = "error_irq",
                 .start  = gic_spi(181),
@@ -785,12 +737,7 @@ static struct platform_device pmu_device = {
 
 /* an IPMMU module for ICB */
 static struct resource ipmmu_resources[] = {
-        [0] = {
-                .name   = "IPMMU",
-                .start  = 0xfe951000,
-                .end    = 0xfe9510ff,
-                .flags  = IORESOURCE_MEM,
-        },
+        DEFINE_RES_MEM_NAMED(0xfe951000, 0x100, "IPMMU"),
 };
 
 static const char * const ipmmu_dev_names[] = {
@@ -982,11 +929,17 @@ void __init sh73a0_add_standard_devices(void)
                             ARRAY_SIZE(sh73a0_late_devices));
 }
 
+void __init sh73a0_init_delay(void)
+{
+        shmobile_setup_delay(1196, 44, 46); /* Cortex-A9 @ 1196MHz */
+}
+
 /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
 void __init __weak sh73a0_register_twd(void) { }
 
 void __init sh73a0_earlytimer_init(void)
 {
+        sh73a0_init_delay();
         sh73a0_clock_init();
         shmobile_earlytimer_init();
         sh73a0_register_twd();
@@ -1005,17 +958,14 @@ void __init sh73a0_add_early_devices(void)
 
 #ifdef CONFIG_USE_OF
 
-void __init sh73a0_init_delay(void)
-{
-        shmobile_setup_delay(1196, 44, 46); /* Cortex-A9 @ 1196MHz */
-}
-
 static const struct of_dev_auxdata sh73a0_auxdata_lookup[] __initconst = {
         {},
 };
 
 void __init sh73a0_add_standard_devices_dt(void)
 {
+        struct platform_device_info devinfo = { .name = "cpufreq-cpu0", .id = -1, };
+
         /* clocks are setup late during boot in the case of DT */
         sh73a0_clock_init();
 
@@ -1023,6 +973,9 @@ void __init sh73a0_add_standard_devices_dt(void)
                              ARRAY_SIZE(sh73a0_devices_dt));
         of_platform_populate(NULL, of_default_bus_match_table,
                              sh73a0_auxdata_lookup, NULL);
+
+        /* Instantiate cpufreq-cpu0 */
+        platform_device_register_full(&devinfo);
 }
 
 static const char *sh73a0_boards_compat_dt[] __initdata = {
diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c
index 947bd9eca079..7936d40a5c37 100644
--- a/arch/arm/mach-ux500/board-mop500-pins.c
+++ b/arch/arm/mach-ux500/board-mop500-pins.c
@@ -9,6 +9,7 @@
 #include <linux/bug.h>
 #include <linux/string.h>
 #include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinconf-generic.h>
 #include <linux/platform_data/pinctrl-nomadik.h>
 
 #include <asm/mach-types.h>
@@ -34,6 +35,11 @@ BIAS(in_pd, PIN_INPUT_PULLDOWN);
 BIAS(out_hi, PIN_OUTPUT_HIGH);
 BIAS(out_lo, PIN_OUTPUT_LOW);
 BIAS(out_lo_slpm_nowkup, PIN_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE);
+
+BIAS(abx500_out_lo, PIN_CONF_PACKED(PIN_CONFIG_OUTPUT, 0));
+BIAS(abx500_in_pd, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 1));
+BIAS(abx500_in_nopull, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 0));
+
 /* These also force them into GPIO mode */
 BIAS(gpio_in_pu, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED);
 BIAS(gpio_in_pd, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED);
@@ -42,8 +48,6 @@ BIAS(gpio_in_pd_slpm_gpio_nopull, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED|PIN_SL
 BIAS(gpio_out_hi, PIN_OUTPUT_HIGH|PIN_GPIOMODE_ENABLED);
 BIAS(gpio_out_lo, PIN_OUTPUT_LOW|PIN_GPIOMODE_ENABLED);
 /* Sleep modes */
-BIAS(slpm_in_nopull_wkup, PIN_SLEEPMODE_ENABLED|
-        PIN_SLPM_DIR_INPUT|PIN_SLPM_PULL_NONE|PIN_SLPM_WAKEUP_ENABLE);
 BIAS(slpm_in_wkup_pdis, PIN_SLEEPMODE_ENABLED|
         PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
 BIAS(slpm_in_wkup_pdis_en, PIN_SLEEPMODE_ENABLED|
@@ -54,8 +58,6 @@ BIAS(slpm_wkup_pdis_en, PIN_SLEEPMODE_ENABLED|
         PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_ENABLED);
 BIAS(slpm_out_lo_pdis, PIN_SLEEPMODE_ENABLED|
         PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE|PIN_SLPM_PDIS_DISABLED);
-BIAS(slpm_out_lo_wkup, PIN_SLEEPMODE_ENABLED|
-        PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_ENABLE);
 BIAS(slpm_out_lo_wkup_pdis, PIN_SLEEPMODE_ENABLED|
         PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
 BIAS(slpm_out_hi_wkup_pdis, PIN_SLEEPMODE_ENABLED|PIN_SLPM_OUTPUT_HIGH|
@@ -97,6 +99,252 @@ BIAS(out_wkup_pdis, PIN_SLPM_DIR_OUTPUT|PIN_SLPM_WAKEUP_ENABLE|
 #define DB8500_PIN_STATE(pin, conf, dev, state) \
         PIN_MAP_CONFIGS_PIN(dev, state, "pinctrl-db8500", pin, conf)
 
+#define AB8500_MUX_HOG(group, func) \
+        PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-ab8500.0", group, func)
+#define AB8500_PIN_HOG(pin, conf) \
+        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-ab8500.0", pin, abx500_##conf)
+
+#define AB8500_MUX_STATE(group, func, dev, state) \
+        PIN_MAP_MUX_GROUP(dev, state, "pinctrl-ab8500.0", group, func)
+#define AB8500_PIN_STATE(pin, conf, dev, state) \
+        PIN_MAP_CONFIGS_PIN(dev, state, "pinctrl-ab8500.0", pin, abx500_##conf)
+
+#define AB8505_MUX_HOG(group, func) \
+        PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-ab8505.0", group, func)
+#define AB8505_PIN_HOG(pin, conf) \
+        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-ab8505.0", pin, abx500_##conf)
+
+#define AB8505_MUX_STATE(group, func, dev, state) \
+        PIN_MAP_MUX_GROUP(dev, state, "pinctrl-ab8505.0", group, func)
+#define AB8505_PIN_STATE(pin, conf, dev, state) \
+        PIN_MAP_CONFIGS_PIN(dev, state, "pinctrl-ab8505.0", pin, abx500_##conf)
+
+static struct pinctrl_map __initdata ab8500_pinmap[] = {
+        /* Sysclkreq2 */
+        AB8500_MUX_STATE("sysclkreq2_d_1", "sysclkreq", "regulator.35", PINCTRL_STATE_DEFAULT),
+        AB8500_PIN_STATE("GPIO1_T10", in_nopull, "regulator.35", PINCTRL_STATE_DEFAULT),
+        /* sysclkreq2 disable, mux in gpio configured in input pulldown */
+        AB8500_MUX_STATE("gpio1_a_1", "gpio", "regulator.35", PINCTRL_STATE_SLEEP),
+        AB8500_PIN_STATE("GPIO1_T10", in_pd, "regulator.35", PINCTRL_STATE_SLEEP),
+
+        /* pins 2 is muxed in GPIO, configured in INPUT PULL DOWN */
+        AB8500_MUX_HOG("gpio2_a_1", "gpio"),
+        AB8500_PIN_HOG("GPIO2_T9", in_pd),
+
+        /* Sysclkreq4 */
+        AB8500_MUX_STATE("sysclkreq4_d_1", "sysclkreq", "regulator.36", PINCTRL_STATE_DEFAULT),
+        AB8500_PIN_STATE("GPIO3_U9", in_nopull, "regulator.36", PINCTRL_STATE_DEFAULT),
+        /* sysclkreq4 disable, mux in gpio configured in input pulldown */
+        AB8500_MUX_STATE("gpio3_a_1", "gpio", "regulator.36", PINCTRL_STATE_SLEEP),
+        AB8500_PIN_STATE("GPIO3_U9", in_pd, "regulator.36", PINCTRL_STATE_SLEEP),
+
+        /* pins 4 is muxed in GPIO, configured in INPUT PULL DOWN */
+        AB8500_MUX_HOG("gpio4_a_1", "gpio"),
+        AB8500_PIN_HOG("GPIO4_W2", in_pd),
+
+        /*
+         * pins 6,7,8 and 9 are muxed in YCBCR0123
+         * configured in INPUT PULL UP
+         */
+        AB8500_MUX_HOG("ycbcr0123_d_1", "ycbcr"),
+        AB8500_PIN_HOG("GPIO6_Y18", in_nopull),
+        AB8500_PIN_HOG("GPIO7_AA20", in_nopull),
+        AB8500_PIN_HOG("GPIO8_W18", in_nopull),
+        AB8500_PIN_HOG("GPIO9_AA19", in_nopull),
+
+        /*
+         * pins 10,11,12 and 13 are muxed in GPIO
+         * configured in INPUT PULL DOWN
+         */
+        AB8500_MUX_HOG("gpio10_d_1", "gpio"),
+        AB8500_PIN_HOG("GPIO10_U17", in_pd),
+
+        AB8500_MUX_HOG("gpio11_d_1", "gpio"),
+        AB8500_PIN_HOG("GPIO11_AA18", in_pd),
+
+        AB8500_MUX_HOG("gpio12_d_1", "gpio"),
+        AB8500_PIN_HOG("GPIO12_U16", in_pd),
+
+        AB8500_MUX_HOG("gpio13_d_1", "gpio"),
+        AB8500_PIN_HOG("GPIO13_W17", in_pd),
+
+        /*
+         * pins 14,15 are muxed in PWM1 and PWM2
+         * configured in INPUT PULL DOWN
+         */
+        AB8500_MUX_HOG("pwmout1_d_1", "pwmout"),
+        AB8500_PIN_HOG("GPIO14_F14", in_pd),
+
+        AB8500_MUX_HOG("pwmout2_d_1", "pwmout"),
+        AB8500_PIN_HOG("GPIO15_B17", in_pd),
+
+        /*
+         * pins 16 is muxed in GPIO
+         * configured in INPUT PULL DOWN
+         */
+        AB8500_MUX_HOG("gpio16_a_1", "gpio"),
+        AB8500_PIN_HOG("GPIO14_F14", in_pd),
+
+        /*
+         * pins 17,18,19 and 20 are muxed in AUDIO interface 1
+         * configured in INPUT PULL DOWN
+         */
+        AB8500_MUX_HOG("adi1_d_1", "adi1"),
+        AB8500_PIN_HOG("GPIO17_P5", in_pd),
+        AB8500_PIN_HOG("GPIO18_R5", in_pd),
+        AB8500_PIN_HOG("GPIO19_U5", in_pd),
+        AB8500_PIN_HOG("GPIO20_T5", in_pd),
+
+        /*
+         * pins 21,22 and 23 are muxed in USB UICC
+         * configured in INPUT PULL DOWN
+         */
+        AB8500_MUX_HOG("usbuicc_d_1", "usbuicc"),
+        AB8500_PIN_HOG("GPIO21_H19", in_pd),
+        AB8500_PIN_HOG("GPIO22_G20", in_pd),
+        AB8500_PIN_HOG("GPIO23_G19", in_pd),
+
+        /*
+         * pins 24,25 are muxed in GPIO
+         * configured in INPUT PULL DOWN
+         */
+        AB8500_MUX_HOG("gpio24_a_1", "gpio"),
+        AB8500_PIN_HOG("GPIO24_T14", in_pd),
+
+        AB8500_MUX_HOG("gpio25_a_1", "gpio"),
+        AB8500_PIN_HOG("GPIO25_R16", in_pd),
+
+        /*
+         * pins 26 is muxed in GPIO
+         * configured in OUTPUT LOW
+         */
+        AB8500_MUX_HOG("gpio26_d_1", "gpio"),
+        AB8500_PIN_HOG("GPIO26_M16", out_lo),
+
+        /*
+         * pins 27,28 are muxed in DMIC12
+         * configured in INPUT PULL DOWN
+         */
+        AB8500_MUX_HOG("dmic12_d_1", "dmic"),
+        AB8500_PIN_HOG("GPIO27_J6", in_pd),
+        AB8500_PIN_HOG("GPIO28_K6", in_pd),
+
+        /*
+         * pins 29,30 are muxed in DMIC34
+         * configured in INPUT PULL DOWN
+         */
+        AB8500_MUX_HOG("dmic34_d_1", "dmic"),
+        AB8500_PIN_HOG("GPIO29_G6", in_pd),
+        AB8500_PIN_HOG("GPIO30_H6", in_pd),
+
+        /*
+         * pins 31,32 are muxed in DMIC56
+         * configured in INPUT PULL DOWN
+         */
+        AB8500_MUX_HOG("dmic56_d_1", "dmic"),
+        AB8500_PIN_HOG("GPIO31_F5", in_pd),
+        AB8500_PIN_HOG("GPIO32_G5", in_pd),
+
+        /*
+         * pins 34 is muxed in EXTCPENA
+         * configured INPUT PULL DOWN
+         */
+        AB8500_MUX_HOG("extcpena_d_1", "extcpena"),
+        AB8500_PIN_HOG("GPIO34_R17", in_pd),
+
+        /*
+         * pins 35 is muxed in GPIO
+         * configured in OUTPUT LOW
+         */
+        AB8500_MUX_HOG("gpio35_d_1", "gpio"),
+        AB8500_PIN_HOG("GPIO35_W15", in_pd),
+
+        /*
+         * pins 36,37,38 and 39 are muxed in GPIO
+         * configured in INPUT PULL DOWN
+         */
+        AB8500_MUX_HOG("gpio36_a_1", "gpio"),
+        AB8500_PIN_HOG("GPIO36_A17", in_pd),
+
+        AB8500_MUX_HOG("gpio37_a_1", "gpio"),
+        AB8500_PIN_HOG("GPIO37_E15", in_pd),
+
+        AB8500_MUX_HOG("gpio38_a_1", "gpio"),
+        AB8500_PIN_HOG("GPIO38_C17", in_pd),
+
+        AB8500_MUX_HOG("gpio39_a_1", "gpio"),
+        AB8500_PIN_HOG("GPIO39_E16", in_pd),
+
+        /*
+         * pins 40 and 41 are muxed in MODCSLSDA
+         * configured INPUT PULL DOWN
+         */
+        AB8500_MUX_HOG("modsclsda_d_1", "modsclsda"),
+        AB8500_PIN_HOG("GPIO40_T19", in_pd),
+        AB8500_PIN_HOG("GPIO41_U19", in_pd),
+
+        /*
+         * pins 42 is muxed in GPIO
+         * configured INPUT PULL DOWN
+         */
+        AB8500_MUX_HOG("gpio42_a_1", "gpio"),
+        AB8500_PIN_HOG("GPIO42_U2", in_pd),
+};
+
+static struct pinctrl_map __initdata ab8505_pinmap[] = {
+        /* Sysclkreq2 */
+        AB8505_MUX_STATE("sysclkreq2_d_1", "sysclkreq", "regulator.36", PINCTRL_STATE_DEFAULT),
+        AB8505_PIN_STATE("GPIO1_N4", in_nopull, "regulator.36", PINCTRL_STATE_DEFAULT),
+        /* sysclkreq2 disable, mux in gpio configured in input pulldown */
+        AB8505_MUX_STATE("gpio1_a_1", "gpio", "regulator.36", PINCTRL_STATE_SLEEP),
+        AB8505_PIN_STATE("GPIO1_N4", in_pd, "regulator.36", PINCTRL_STATE_SLEEP),
+
+        /* pins 2 is muxed in GPIO, configured in INPUT PULL DOWN */
+        AB8505_MUX_HOG("gpio2_a_1", "gpio"),
+        AB8505_PIN_HOG("GPIO2_R5", in_pd),
+
+        /* Sysclkreq4 */
+        AB8505_MUX_STATE("sysclkreq4_d_1", "sysclkreq", "regulator.37", PINCTRL_STATE_DEFAULT),
+        AB8505_PIN_STATE("GPIO3_P5", in_nopull, "regulator.37", PINCTRL_STATE_DEFAULT),
+        /* sysclkreq4 disable, mux in gpio configured in input pulldown */
+        AB8505_MUX_STATE("gpio3_a_1", "gpio", "regulator.37", PINCTRL_STATE_SLEEP),
+        AB8505_PIN_STATE("GPIO3_P5", in_pd, "regulator.37", PINCTRL_STATE_SLEEP),
+
+        AB8505_MUX_HOG("gpio10_d_1", "gpio"),
+        AB8505_PIN_HOG("GPIO10_B16", in_pd),
+
+        AB8505_MUX_HOG("gpio11_d_1", "gpio"),
+        AB8505_PIN_HOG("GPIO11_B17", in_pd),
+
+        AB8505_MUX_HOG("gpio13_d_1", "gpio"),
+        AB8505_PIN_HOG("GPIO13_D17", in_nopull),
+
+        AB8505_MUX_HOG("pwmout1_d_1", "pwmout"),
+        AB8505_PIN_HOG("GPIO14_C16", in_pd),
+
+        AB8505_MUX_HOG("adi2_d_1", "adi2"),
+        AB8505_PIN_HOG("GPIO17_P2", in_pd),
+        AB8505_PIN_HOG("GPIO18_N3", in_pd),
+        AB8505_PIN_HOG("GPIO19_T1", in_pd),
+        AB8505_PIN_HOG("GPIO20_P3", in_pd),
+
+        AB8505_MUX_HOG("gpio34_a_1", "gpio"),
+        AB8505_PIN_HOG("GPIO34_H14", in_pd),
+
+        AB8505_MUX_HOG("modsclsda_d_1", "modsclsda"),
+        AB8505_PIN_HOG("GPIO40_J15", in_pd),
+        AB8505_PIN_HOG("GPIO41_J14", in_pd),
+
+        AB8505_MUX_HOG("gpio50_d_1", "gpio"),
+        AB8505_PIN_HOG("GPIO50_L4", in_nopull),
+
+        AB8505_MUX_HOG("resethw_d_1", "resethw"),
+        AB8505_PIN_HOG("GPIO52_D16", in_pd),
+
+        AB8505_MUX_HOG("service_d_1", "service"),
+        AB8505_PIN_HOG("GPIO53_D15", in_pd),
+};
+
 /* Pin control settings */
 static struct pinctrl_map __initdata mop500_family_pinmap[] = {
         /*
@@ -174,17 +422,12 @@ static struct pinctrl_map __initdata mop500_family_pinmap[] = {
         DB8500_PIN_SLEEP("GPIO4_AH6", slpm_in_wkup_pdis, "uart1"),
         DB8500_PIN_SLEEP("GPIO5_AG6", slpm_out_wkup_pdis, "uart1"),
         /* MSP1 for ALSA codec */
-        DB8500_MUX("msp1txrx_a_1", "msp1", "ux500-msp-i2s.1"),
-        DB8500_MUX("msp1_a_1", "msp1", "ux500-msp-i2s.1"),
-        DB8500_PIN("GPIO33_AF2", out_lo_slpm_nowkup, "ux500-msp-i2s.1"),
-        DB8500_PIN("GPIO34_AE1", in_nopull_slpm_nowkup, "ux500-msp-i2s.1"),
-        DB8500_PIN("GPIO35_AE2", in_nopull_slpm_nowkup, "ux500-msp-i2s.1"),
-        DB8500_PIN("GPIO36_AG2", in_nopull_slpm_nowkup, "ux500-msp-i2s.1"),
-        /* MSP1 sleep state */
-        DB8500_PIN_SLEEP("GPIO33_AF2", slpm_out_lo_wkup, "ux500-msp-i2s.1"),
-        DB8500_PIN_SLEEP("GPIO34_AE1", slpm_in_nopull_wkup, "ux500-msp-i2s.1"),
-        DB8500_PIN_SLEEP("GPIO35_AE2", slpm_in_nopull_wkup, "ux500-msp-i2s.1"),
-        DB8500_PIN_SLEEP("GPIO36_AG2", slpm_in_nopull_wkup, "ux500-msp-i2s.1"),
+        DB8500_MUX_HOG("msp1txrx_a_1", "msp1"),
+        DB8500_MUX_HOG("msp1_a_1", "msp1"),
+        DB8500_PIN_HOG("GPIO33_AF2", out_lo_slpm_nowkup),
+        DB8500_PIN_HOG("GPIO34_AE1", in_nopull_slpm_nowkup),
+        DB8500_PIN_HOG("GPIO35_AE2", in_nopull_slpm_nowkup),
+        DB8500_PIN_HOG("GPIO36_AG2", in_nopull_slpm_nowkup),
         /* Mux in LCD data lines 8 thru 11 and LCDA CLK for MCDE TVOUT */
         DB8500_MUX("lcd_d8_d11_a_1", "lcd", "mcde-tvout"),
         DB8500_MUX("lcdaclk_b_1", "lcda", "mcde-tvout"),
@@ -821,6 +1064,12 @@ void __init mop500_pinmaps_init(void)
         pinctrl_register_mappings(mop500_pinmap,
                                   ARRAY_SIZE(mop500_pinmap));
         mop500_href_family_pinmaps_init();
+        if (machine_is_u8520())
+                pinctrl_register_mappings(ab8505_pinmap,
+                                          ARRAY_SIZE(ab8505_pinmap));
+        else
+                pinctrl_register_mappings(ab8500_pinmap,
+                                          ARRAY_SIZE(ab8500_pinmap));
 }
 
 void __init snowball_pinmaps_init(void)
@@ -831,6 +1080,8 @@ void __init snowball_pinmaps_init(void)
                                   ARRAY_SIZE(snowball_pinmap));
         pinctrl_register_mappings(u8500_pinmap,
                                   ARRAY_SIZE(u8500_pinmap));
+        pinctrl_register_mappings(ab8500_pinmap,
+                                  ARRAY_SIZE(ab8500_pinmap));
 }
 
 void __init hrefv60_pinmaps_init(void)
@@ -840,4 +1091,6 @@ void __init hrefv60_pinmaps_init(void)
         pinctrl_register_mappings(hrefv60_pinmap,
                                   ARRAY_SIZE(hrefv60_pinmap));
         mop500_href_family_pinmaps_init();
+        pinctrl_register_mappings(ab8500_pinmap,
+                                  ARRAY_SIZE(ab8500_pinmap));
 }
diff --git a/arch/arm/mach-ux500/board-mop500-regulators.c b/arch/arm/mach-ux500/board-mop500-regulators.c
index d6b7c8556fa1..0dc44c683427 100644
--- a/arch/arm/mach-ux500/board-mop500-regulators.c
+++ b/arch/arm/mach-ux500/board-mop500-regulators.c
@@ -999,7 +999,6 @@ struct ab8500_regulator_platform_data ab8500_regulator_plat_data = {
         .num_ext_regulator      = ARRAY_SIZE(ab8500_ext_regulators),
 };
 
-/* Use the AB8500 init settings for AB8505 as they are the same right now */
 struct ab8500_regulator_platform_data ab8505_regulator_plat_data = {
         .reg_init               = ab8505_reg_init,
         .num_reg_init           = ARRAY_SIZE(ab8505_reg_init),
diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c
index 0ef38775a0c1..43be3e0d4e30 100644
--- a/arch/arm/mach-ux500/board-mop500-sdi.c
+++ b/arch/arm/mach-ux500/board-mop500-sdi.c
@@ -52,11 +52,13 @@ static struct stedma40_chan_cfg mop500_sdi0_dma_cfg_tx = {
 #endif
 
 struct mmci_platform_data mop500_sdi0_data = {
-        .ocr_mask       = MMC_VDD_29_30,
-        .f_max          = 50000000,
+        .f_max          = 100000000,
         .capabilities   = MMC_CAP_4_BIT_DATA |
                                 MMC_CAP_SD_HIGHSPEED |
-                                MMC_CAP_MMC_HIGHSPEED,
+                                MMC_CAP_MMC_HIGHSPEED |
+                                MMC_CAP_ERASE |
+                                MMC_CAP_UHS_SDR12 |
+                                MMC_CAP_UHS_SDR25,
         .gpio_wp        = -1,
         .sigdir         = MCI_ST_FBCLKEN |
                                 MCI_ST_CMDDIREN |
@@ -106,8 +108,9 @@ static struct stedma40_chan_cfg sdi1_dma_cfg_tx = {
 
 struct mmci_platform_data mop500_sdi1_data = {
         .ocr_mask       = MMC_VDD_29_30,
-        .f_max          = 50000000,
-        .capabilities   = MMC_CAP_4_BIT_DATA,
+        .f_max          = 100000000,
+        .capabilities   = MMC_CAP_4_BIT_DATA |
+                                MMC_CAP_NONREMOVABLE,
         .gpio_cd        = -1,
         .gpio_wp        = -1,
 #ifdef CONFIG_STE_DMA40
@@ -143,9 +146,13 @@ static struct stedma40_chan_cfg mop500_sdi2_dma_cfg_tx = {
 
 struct mmci_platform_data mop500_sdi2_data = {
         .ocr_mask       = MMC_VDD_165_195,
-        .f_max          = 50000000,
-        .capabilities   = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA |
-                          MMC_CAP_MMC_HIGHSPEED,
+        .f_max          = 100000000,
+        .capabilities   = MMC_CAP_4_BIT_DATA |
+                                MMC_CAP_8_BIT_DATA |
+                                MMC_CAP_NONREMOVABLE |
+                                MMC_CAP_MMC_HIGHSPEED |
+                                MMC_CAP_ERASE |
+                                MMC_CAP_CMD23,
         .gpio_cd        = -1,
         .gpio_wp        = -1,
 #ifdef CONFIG_STE_DMA40
@@ -180,10 +187,13 @@ static struct stedma40_chan_cfg mop500_sdi4_dma_cfg_tx = {
 #endif
 
 struct mmci_platform_data mop500_sdi4_data = {
-        .ocr_mask       = MMC_VDD_29_30,
-        .f_max          = 50000000,
-        .capabilities   = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA |
-                          MMC_CAP_MMC_HIGHSPEED,
+        .f_max          = 100000000,
+        .capabilities   = MMC_CAP_4_BIT_DATA |
+                                MMC_CAP_8_BIT_DATA |
+                                MMC_CAP_NONREMOVABLE |
+                                MMC_CAP_MMC_HIGHSPEED |
+                                MMC_CAP_ERASE |
+                                MMC_CAP_CMD23,
         .gpio_cd        = -1,
         .gpio_wp        = -1,
 #ifdef CONFIG_STE_DMA40
diff --git a/arch/arm/mach-ux500/db8500-regs.h b/arch/arm/mach-ux500/db8500-regs.h
index b2d7a0b98629..27399553c841 100644
--- a/arch/arm/mach-ux500/db8500-regs.h
+++ b/arch/arm/mach-ux500/db8500-regs.h
@@ -102,7 +102,6 @@
 #define U8500_PRCMU_BASE        (U8500_PER4_BASE + 0x07000)
 #define U9540_DMC1_BASE         (U8500_PER4_BASE + 0x0A000)
 #define U8500_PRCMU_TCDM_BASE   (U8500_PER4_BASE + 0x68000)
-#define U9540_PRCMU_TCDM_BASE   (U8500_PER4_BASE + 0x6A000)
 #define U8500_PRCMU_TCPM_BASE   (U8500_PER4_BASE + 0x60000)
 #define U8500_PRCMU_TIMER_3_BASE (U8500_PER4_BASE + 0x07338)
 #define U8500_PRCMU_TIMER_4_BASE (U8500_PER4_BASE + 0x07450)
@@ -184,7 +183,7 @@
 #define U8500_IO_VIRTUAL        0xf0000000
 #define U8500_IO_PHYSICAL       0xa0000000
 /* This is where we map in the ROM to check ASIC IDs */
-#define UX500_VIRT_ROM          0xf0000000
+#define UX500_VIRT_ROM          IOMEM(0xf0000000)
 
 /* This macro is used in assembly, so no cast */
 #define IO_ADDRESS(x)           \
diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c
index 1cf94ce0feec..ddbdcda8306a 100644
--- a/arch/arm/mach-ux500/devices-db8500.c
+++ b/arch/arm/mach-ux500/devices-db8500.c
@@ -227,7 +227,7 @@ static struct resource db8500_prcmu_res[] = {
         {
                 .name  = "prcmu-tcpm",
                 .start = U8500_PRCMU_TCPM_BASE,
-                .end   = U8500_PRCMU_TCPM_BASE + SZ_4K - 1,
+                .end   = U8500_PRCMU_TCPM_BASE + SZ_32K - 1,
                 .flags = IORESOURCE_MEM,
         },
 };
diff --git a/arch/arm/mach-ux500/id.c b/arch/arm/mach-ux500/id.c
index 0d33d1a06955..392f2fdb37d0 100644
--- a/arch/arm/mach-ux500/id.c
+++ b/arch/arm/mach-ux500/id.c
@@ -21,11 +21,11 @@
 
 struct dbx500_asic_id dbx500_id;
 
-static unsigned int ux500_read_asicid(phys_addr_t addr)
+static unsigned int __init ux500_read_asicid(phys_addr_t addr)
 {
         phys_addr_t base = addr & ~0xfff;
         struct map_desc desc = {
-                .virtual        = UX500_VIRT_ROM,
+                .virtual        = (unsigned long)UX500_VIRT_ROM,
                 .pfn            = __phys_to_pfn(base),
                 .length         = SZ_16K,
                 .type           = MT_DEVICE,
@@ -37,7 +37,7 @@ static unsigned int ux500_read_asicid(phys_addr_t addr)
         local_flush_tlb_all();
         flush_cache_all();
 
-        return readl(IOMEM(UX500_VIRT_ROM + (addr & 0xfff)));
+        return readl(UX500_VIRT_ROM + (addr & 0xfff));
 }
 
 static void ux500_print_soc_info(unsigned int asicid)
diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c
index b4ca450947b8..d173d56dbb8c 100644
--- a/drivers/gpio/gpio-rcar.c
+++ b/drivers/gpio/gpio-rcar.c
@@ -49,6 +49,7 @@ struct gpio_rcar_priv {
 #define POSNEG 0x20
 #define EDGLEVEL 0x24
 #define FILONOFF 0x28
+#define BOTHEDGE 0x4c
 
 static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
 {
@@ -91,7 +92,8 @@ static void gpio_rcar_irq_enable(struct irq_data *d)
 static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
                                                   unsigned int hwirq,
                                                   bool active_high_rising_edge,
-                                                  bool level_trigger)
+                                                  bool level_trigger,
+                                                  bool both)
 {
         unsigned long flags;
 
@@ -108,6 +110,10 @@ static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
         /* Configure edge or level trigger in EDGLEVEL */
         gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);
 
+        /* Select one edge or both edges in BOTHEDGE */
+        if (p->config.has_both_edge_trigger)
+                gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);
+
         /* Select "Interrupt Input Mode" in IOINTSEL */
         gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
 
@@ -127,16 +133,26 @@ static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
 
         switch (type & IRQ_TYPE_SENSE_MASK) {
         case IRQ_TYPE_LEVEL_HIGH:
-                gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true);
+                gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true,
+                                                      false);
                 break;
         case IRQ_TYPE_LEVEL_LOW:
-                gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true);
+                gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true,
+                                                      false);
                 break;
         case IRQ_TYPE_EDGE_RISING:
-                gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false);
+                gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
+                                                      false);
                 break;
         case IRQ_TYPE_EDGE_FALLING:
-                gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false);
+                gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false,
+                                                      false);
+                break;
+        case IRQ_TYPE_EDGE_BOTH:
+                if (!p->config.has_both_edge_trigger)
+                        return -EINVAL;
+                gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
+                                                      true);
                 break;
         default:
                 return -EINVAL;
@@ -333,7 +349,7 @@ static int gpio_rcar_probe(struct platform_device *pdev)
         }
 
         if (devm_request_irq(&pdev->dev, irq->start,
-                             gpio_rcar_irq_handler, 0, name, p)) {
+                             gpio_rcar_irq_handler, IRQF_SHARED, name, p)) {
                 dev_err(&pdev->dev, "failed to request IRQ\n");
                 ret = -ENOENT;
                 goto err1;
diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig
index f8a2ae413c7f..636a882b406e 100644
--- a/drivers/pinctrl/sh-pfc/Kconfig
+++ b/drivers/pinctrl/sh-pfc/Kconfig
@@ -5,8 +5,6 @@
 if ARCH_SHMOBILE || SUPERH
 
 config PINCTRL_SH_PFC
-        # XXX move off the gpio dependency
-        depends on GPIOLIB
         select GPIO_SH_PFC if ARCH_REQUIRE_GPIOLIB
         select PINMUX
         select PINCONF
@@ -32,11 +30,21 @@ config PINCTRL_PFC_R8A7740
         depends on ARCH_R8A7740
         select PINCTRL_SH_PFC
 
+config PINCTRL_PFC_R8A7778
+        def_bool y
+        depends on ARCH_R8A7778
+        select PINCTRL_SH_PFC
+
 config PINCTRL_PFC_R8A7779
         def_bool y
         depends on ARCH_R8A7779
         select PINCTRL_SH_PFC
 
+config PINCTRL_PFC_R8A7790
+        def_bool y
+        depends on ARCH_R8A7790
+        select PINCTRL_SH_PFC
+
 config PINCTRL_PFC_SH7203
         def_bool y
         depends on CPU_SUBTYPE_SH7203
@@ -64,6 +72,7 @@ config PINCTRL_PFC_SH73A0
         def_bool y
         depends on ARCH_SH73A0
         select PINCTRL_SH_PFC
+        select REGULATOR
 
 config PINCTRL_PFC_SH7720
         def_bool y
diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile
index 211cd8e98a8a..5e0c222c12d7 100644
--- a/drivers/pinctrl/sh-pfc/Makefile
+++ b/drivers/pinctrl/sh-pfc/Makefile
@@ -5,7 +5,9 @@ endif
 obj-$(CONFIG_PINCTRL_SH_PFC)    += sh-pfc.o
 obj-$(CONFIG_PINCTRL_PFC_R8A73A4)       += pfc-r8a73a4.o
 obj-$(CONFIG_PINCTRL_PFC_R8A7740)       += pfc-r8a7740.o
+obj-$(CONFIG_PINCTRL_PFC_R8A7778)       += pfc-r8a7778.o
 obj-$(CONFIG_PINCTRL_PFC_R8A7779)       += pfc-r8a7779.o
+obj-$(CONFIG_PINCTRL_PFC_R8A7790)       += pfc-r8a7790.o
 obj-$(CONFIG_PINCTRL_PFC_SH7203)        += pfc-sh7203.o
 obj-$(CONFIG_PINCTRL_PFC_SH7264)        += pfc-sh7264.o
 obj-$(CONFIG_PINCTRL_PFC_SH7269)        += pfc-sh7269.o
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index b551336924a5..3b2fd43ff294 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -372,6 +372,12 @@ static int sh_pfc_probe(struct platform_device *pdev)
 
         spin_lock_init(&pfc->lock);
 
+        if (info->ops && info->ops->init) {
+                ret = info->ops->init(pfc);
+                if (ret < 0)
+                        return ret;
+        }
+
         pinctrl_provide_dummies();
 
         /*
@@ -379,7 +385,7 @@ static int sh_pfc_probe(struct platform_device *pdev)
          */
         ret = sh_pfc_register_pinctrl(pfc);
         if (unlikely(ret != 0))
-                return ret;
+                goto error;
 
 #ifdef CONFIG_GPIO_SH_PFC
         /*
@@ -401,6 +407,11 @@ static int sh_pfc_probe(struct platform_device *pdev)
         dev_info(pfc->dev, "%s support registered\n", info->name);
 
         return 0;
+
+error:
+        if (info->ops && info->ops->exit)
+                info->ops->exit(pfc);
+        return ret;
 }
 
 static int sh_pfc_remove(struct platform_device *pdev)
@@ -412,6 +423,9 @@ static int sh_pfc_remove(struct platform_device *pdev)
 #endif
         sh_pfc_unregister_pinctrl(pfc);
 
+        if (pfc->info->ops && pfc->info->ops->exit)
+                pfc->info->ops->exit(pfc);
+
         platform_set_drvdata(pdev, NULL);
 
         return 0;
@@ -424,9 +438,15 @@ static const struct platform_device_id sh_pfc_id_table[] = {
 #ifdef CONFIG_PINCTRL_PFC_R8A7740
         { "pfc-r8a7740", (kernel_ulong_t)&r8a7740_pinmux_info },
 #endif
+#ifdef CONFIG_PINCTRL_PFC_R8A7778
+        { "pfc-r8a7778", (kernel_ulong_t)&r8a7778_pinmux_info },
+#endif
 #ifdef CONFIG_PINCTRL_PFC_R8A7779
         { "pfc-r8a7779", (kernel_ulong_t)&r8a7779_pinmux_info },
 #endif
+#ifdef CONFIG_PINCTRL_PFC_R8A7790
+        { "pfc-r8a7790", (kernel_ulong_t)&r8a7790_pinmux_info },
+#endif
 #ifdef CONFIG_PINCTRL_PFC_SH7203
         { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
 #endif
diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h
index 89cb4289d761..f02ba1dde3a0 100644
--- a/drivers/pinctrl/sh-pfc/core.h
+++ b/drivers/pinctrl/sh-pfc/core.h
@@ -11,6 +11,7 @@
 #define __SH_PFC_CORE_H__
 
 #include <linux/compiler.h>
+#include <linux/spinlock.h>
 #include <linux/types.h>
 
 #include "sh_pfc.h"
@@ -27,6 +28,7 @@ struct sh_pfc_pinctrl;
 struct sh_pfc {
         struct device *dev;
         const struct sh_pfc_soc_info *info;
+        void *soc_data;
         spinlock_t lock;
 
         unsigned int num_windows;
@@ -56,7 +58,9 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type);
 
 extern const struct sh_pfc_soc_info r8a73a4_pinmux_info;
 extern const struct sh_pfc_soc_info r8a7740_pinmux_info;
+extern const struct sh_pfc_soc_info r8a7778_pinmux_info;
 extern const struct sh_pfc_soc_info r8a7779_pinmux_info;
+extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
 extern const struct sh_pfc_soc_info sh7203_pinmux_info;
 extern const struct sh_pfc_soc_info sh7264_pinmux_info;
 extern const struct sh_pfc_soc_info sh7269_pinmux_info;
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
index bbd87d29bfd0..f6ea47c433b3 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
@@ -18,10 +18,14 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
+#include <linux/io.h>
 #include <linux/kernel.h>
+#include <linux/pinctrl/pinconf-generic.h>
+
 #include <mach/r8a7740.h>
 #include <mach/irqs.h>
 
+#include "core.h"
 #include "sh_pfc.h"
 
 #define CPU_ALL_PORT(fn, pfx, sfx)                                      \
@@ -30,6 +34,29 @@
         PORT_10(fn, pfx##20, sfx),                                      \
         PORT_1(fn, pfx##210, sfx),      PORT_1(fn, pfx##211, sfx)
 
+#undef _GPIO_PORT
+#define _GPIO_PORT(gpio, sfx)                                           \
+        [gpio] = {                                                      \
+                .name = __stringify(PORT##gpio),                        \
+                .enum_id = PORT##gpio##_DATA,                           \
+        }
+
+#define IRQC_PIN_MUX(irq, pin)                                          \
+static const unsigned int intc_irq##irq##_pins[] = {                    \
+        pin,                                                            \
+};                                                                      \
+static const unsigned int intc_irq##irq##_mux[] = {                     \
+        IRQ##irq##_MARK,                                                \
+}
+
+#define IRQC_PINS_MUX(irq, idx, pin)                                    \
+static const unsigned int intc_irq##irq##_##idx##_pins[] = {            \
+        pin,                                                            \
+};                                                                      \
+static const unsigned int intc_irq##irq##_##idx##_mux[] = {             \
+        IRQ##irq##_PORT##pin##_MARK,                                    \
+}
+
 enum {
         PINMUX_RESERVED = 0,
 
@@ -43,16 +70,6 @@ enum {
         PORT_ALL(IN),
         PINMUX_INPUT_END,
 
-        /* PORT0_IN_PU -> PORT211_IN_PU */
-        PINMUX_INPUT_PULLUP_BEGIN,
-        PORT_ALL(IN_PU),
-        PINMUX_INPUT_PULLUP_END,
-
-        /* PORT0_IN_PD -> PORT211_IN_PD */
-        PINMUX_INPUT_PULLDOWN_BEGIN,
-        PORT_ALL(IN_PD),
-        PINMUX_INPUT_PULLDOWN_END,
-
         /* PORT0_OUT -> PORT211_OUT */
         PINMUX_OUTPUT_BEGIN,
         PORT_ALL(OUT),
@@ -261,8 +278,6 @@ enum {
         SCIFB_CTS_PORT173_MARK,
 
         /* LCD0 */
-        LCDC0_SELECT_MARK,
-
         LCD0_D0_MARK,   LCD0_D1_MARK,   LCD0_D2_MARK,   LCD0_D3_MARK,
         LCD0_D4_MARK,   LCD0_D5_MARK,   LCD0_D6_MARK,   LCD0_D7_MARK,
         LCD0_D8_MARK,   LCD0_D9_MARK,   LCD0_D10_MARK,  LCD0_D11_MARK,
@@ -285,8 +300,6 @@ enum {
         LCD0_LCLK_PORT102_MARK,
 
         /* LCD1 */
-        LCDC1_SELECT_MARK,
-
         LCD1_D0_MARK,   LCD1_D1_MARK,   LCD1_D2_MARK,   LCD1_D3_MARK,
         LCD1_D4_MARK,   LCD1_D5_MARK,   LCD1_D6_MARK,   LCD1_D7_MARK,
         LCD1_D8_MARK,   LCD1_D9_MARK,   LCD1_D10_MARK,  LCD1_D11_MARK,
@@ -577,137 +590,11 @@ enum {
         PINMUX_MARK_END,
 };
 
+#define _PORT_DATA(pfx, sfx)    PORT_DATA_IO(pfx)
+#define PINMUX_DATA_GP_ALL()    CPU_ALL_PORT(_PORT_DATA, , unused)
+
 static const pinmux_enum_t pinmux_data[] = {
-        /* specify valid pin states for each pin in GPIO mode */
-
-        /* I/O and Pull U/D */
-        PORT_DATA_IO_PD(0),             PORT_DATA_IO_PD(1),
-        PORT_DATA_IO_PD(2),             PORT_DATA_IO_PD(3),
-        PORT_DATA_IO_PD(4),             PORT_DATA_IO_PD(5),
-        PORT_DATA_IO_PD(6),             PORT_DATA_IO(7),
-        PORT_DATA_IO(8),                PORT_DATA_IO(9),
-
-        PORT_DATA_IO_PD(10),            PORT_DATA_IO_PD(11),
-        PORT_DATA_IO_PD(12),            PORT_DATA_IO_PU_PD(13),
-        PORT_DATA_IO_PD(14),            PORT_DATA_IO_PD(15),
-        PORT_DATA_IO_PD(16),            PORT_DATA_IO_PD(17),
-        PORT_DATA_IO(18),               PORT_DATA_IO_PU(19),
-
-        PORT_DATA_IO_PU_PD(20),         PORT_DATA_IO_PD(21),
-        PORT_DATA_IO_PU_PD(22),         PORT_DATA_IO(23),
-        PORT_DATA_IO_PU(24),            PORT_DATA_IO_PU(25),
-        PORT_DATA_IO_PU(26),            PORT_DATA_IO_PU(27),
-        PORT_DATA_IO_PU(28),            PORT_DATA_IO_PU(29),
-
-        PORT_DATA_IO_PU(30),            PORT_DATA_IO_PD(31),
-        PORT_DATA_IO_PD(32),            PORT_DATA_IO_PD(33),
-        PORT_DATA_IO_PD(34),            PORT_DATA_IO_PU(35),
-        PORT_DATA_IO_PU(36),            PORT_DATA_IO_PD(37),
-        PORT_DATA_IO_PU(38),            PORT_DATA_IO_PD(39),
-
-        PORT_DATA_IO_PU_PD(40),         PORT_DATA_IO_PD(41),
-        PORT_DATA_IO_PD(42),            PORT_DATA_IO_PU_PD(43),
-        PORT_DATA_IO_PU_PD(44),         PORT_DATA_IO_PU_PD(45),
-        PORT_DATA_IO_PU_PD(46),         PORT_DATA_IO_PU_PD(47),
-        PORT_DATA_IO_PU_PD(48),         PORT_DATA_IO_PU_PD(49),
-
-        PORT_DATA_IO_PU_PD(50),         PORT_DATA_IO_PD(51),
-        PORT_DATA_IO_PD(52),            PORT_DATA_IO_PD(53),
-        PORT_DATA_IO_PD(54),            PORT_DATA_IO_PU_PD(55),
-        PORT_DATA_IO_PU_PD(56),         PORT_DATA_IO_PU_PD(57),
-        PORT_DATA_IO_PU_PD(58),         PORT_DATA_IO_PU_PD(59),
-
-        PORT_DATA_IO_PU_PD(60),         PORT_DATA_IO_PD(61),
-        PORT_DATA_IO_PD(62),            PORT_DATA_IO_PD(63),
-        PORT_DATA_IO_PD(64),            PORT_DATA_IO_PD(65),
-        PORT_DATA_IO_PU_PD(66),         PORT_DATA_IO_PU_PD(67),
-        PORT_DATA_IO_PU_PD(68),         PORT_DATA_IO_PU_PD(69),
-
-        PORT_DATA_IO_PU_PD(70),         PORT_DATA_IO_PU_PD(71),
-        PORT_DATA_IO_PU_PD(72),         PORT_DATA_IO_PU_PD(73),
-        PORT_DATA_IO_PU_PD(74),         PORT_DATA_IO_PU_PD(75),
-        PORT_DATA_IO_PU_PD(76),         PORT_DATA_IO_PU_PD(77),
-        PORT_DATA_IO_PU_PD(78),         PORT_DATA_IO_PU_PD(79),
-
-        PORT_DATA_IO_PU_PD(80),         PORT_DATA_IO_PU_PD(81),
-        PORT_DATA_IO(82),               PORT_DATA_IO_PU_PD(83),
-        PORT_DATA_IO(84),               PORT_DATA_IO_PD(85),
-        PORT_DATA_IO_PD(86),            PORT_DATA_IO_PD(87),
-        PORT_DATA_IO_PD(88),            PORT_DATA_IO_PD(89),
-
-        PORT_DATA_IO_PD(90),            PORT_DATA_IO_PU_PD(91),
-        PORT_DATA_IO_PU_PD(92),         PORT_DATA_IO_PU_PD(93),
-        PORT_DATA_IO_PU_PD(94),         PORT_DATA_IO_PU_PD(95),
-        PORT_DATA_IO_PU_PD(96),         PORT_DATA_IO_PU_PD(97),
-        PORT_DATA_IO_PU_PD(98),         PORT_DATA_IO_PU_PD(99),
-
-        PORT_DATA_IO_PU_PD(100),        PORT_DATA_IO(101),
-        PORT_DATA_IO_PU(102),           PORT_DATA_IO_PU_PD(103),
-        PORT_DATA_IO_PU(104),           PORT_DATA_IO_PU(105),
-        PORT_DATA_IO_PU_PD(106),        PORT_DATA_IO(107),
-        PORT_DATA_IO(108),              PORT_DATA_IO(109),
-
-        PORT_DATA_IO(110),              PORT_DATA_IO(111),
-        PORT_DATA_IO(112),              PORT_DATA_IO(113),
-        PORT_DATA_IO_PU_PD(114),        PORT_DATA_IO(115),
-        PORT_DATA_IO_PD(116),           PORT_DATA_IO_PD(117),
-        PORT_DATA_IO_PD(118),           PORT_DATA_IO_PD(119),
-
-        PORT_DATA_IO_PD(120),           PORT_DATA_IO_PD(121),
-        PORT_DATA_IO_PD(122),           PORT_DATA_IO_PD(123),
-        PORT_DATA_IO_PD(124),           PORT_DATA_IO(125),
-        PORT_DATA_IO(126),              PORT_DATA_IO(127),
-        PORT_DATA_IO(128),              PORT_DATA_IO(129),
-
-        PORT_DATA_IO(130),              PORT_DATA_IO(131),
-        PORT_DATA_IO(132),              PORT_DATA_IO(133),
-        PORT_DATA_IO(134),              PORT_DATA_IO(135),
-        PORT_DATA_IO(136),              PORT_DATA_IO(137),
-        PORT_DATA_IO(138),              PORT_DATA_IO(139),
-
-        PORT_DATA_IO(140),              PORT_DATA_IO(141),
-        PORT_DATA_IO_PU(142),           PORT_DATA_IO_PU(143),
-        PORT_DATA_IO_PU(144),           PORT_DATA_IO_PU(145),
-        PORT_DATA_IO_PU(146),           PORT_DATA_IO_PU(147),
-        PORT_DATA_IO_PU(148),           PORT_DATA_IO_PU(149),
-
-        PORT_DATA_IO_PU(150),           PORT_DATA_IO_PU(151),
-        PORT_DATA_IO_PU(152),           PORT_DATA_IO_PU(153),
-        PORT_DATA_IO_PU(154),           PORT_DATA_IO_PU(155),
-        PORT_DATA_IO_PU(156),           PORT_DATA_IO_PU(157),
-        PORT_DATA_IO_PD(158),           PORT_DATA_IO_PD(159),
-
-        PORT_DATA_IO_PU_PD(160),        PORT_DATA_IO_PD(161),
-        PORT_DATA_IO_PD(162),           PORT_DATA_IO_PD(163),
-        PORT_DATA_IO_PD(164),           PORT_DATA_IO_PD(165),
-        PORT_DATA_IO_PU(166),           PORT_DATA_IO_PU(167),
-        PORT_DATA_IO_PU(168),           PORT_DATA_IO_PU(169),
-
-        PORT_DATA_IO_PU(170),           PORT_DATA_IO_PU(171),
-        PORT_DATA_IO_PD(172),           PORT_DATA_IO_PD(173),
-        PORT_DATA_IO_PD(174),           PORT_DATA_IO_PD(175),
-        PORT_DATA_IO_PU(176),           PORT_DATA_IO_PU_PD(177),
-        PORT_DATA_IO_PU(178),           PORT_DATA_IO_PD(179),
-
-        PORT_DATA_IO_PD(180),           PORT_DATA_IO_PU(181),
-        PORT_DATA_IO_PU(182),           PORT_DATA_IO(183),
-        PORT_DATA_IO_PD(184),           PORT_DATA_IO_PD(185),
-        PORT_DATA_IO_PD(186),           PORT_DATA_IO_PD(187),
-        PORT_DATA_IO_PD(188),           PORT_DATA_IO_PD(189),
-
-        PORT_DATA_IO_PD(190),           PORT_DATA_IO_PD(191),
-        PORT_DATA_IO_PD(192),           PORT_DATA_IO_PU_PD(193),
-        PORT_DATA_IO_PU_PD(194),        PORT_DATA_IO_PD(195),
-        PORT_DATA_IO_PU_PD(196),        PORT_DATA_IO_PD(197),
-        PORT_DATA_IO_PU_PD(198),        PORT_DATA_IO_PU_PD(199),
-
-        PORT_DATA_IO_PU_PD(200),        PORT_DATA_IO_PU(201),
-        PORT_DATA_IO_PU_PD(202),        PORT_DATA_IO(203),
-        PORT_DATA_IO_PU_PD(204),        PORT_DATA_IO_PU_PD(205),
-        PORT_DATA_IO_PU_PD(206),        PORT_DATA_IO_PU_PD(207),
-        PORT_DATA_IO_PU_PD(208),        PORT_DATA_IO_PD(209),
-
-        PORT_DATA_IO_PD(210),           PORT_DATA_IO_PD(211),
+        PINMUX_DATA_GP_ALL(),
 
         /* Port0 */
         PINMUX_DATA(DBGMDT2_MARK,               PORT0_FN1),
@@ -986,7 +873,7 @@ static const pinmux_enum_t pinmux_data[] = {
         PINMUX_DATA(IRQ27_PORT57_MARK,          PORT57_FN0,     MSEL1CR_27_1),
 
         /* Port58 */
-        PINMUX_DATA(LCD0_D0_MARK,               PORT58_FN1),
+        PINMUX_DATA(LCD0_D0_MARK,               PORT58_FN1,     MSEL3CR_6_0),
         PINMUX_DATA(KEYOUT7_MARK,               PORT58_FN3),
         PINMUX_DATA(KEYIN0_PORT58_MARK,         PORT58_FN4,     MSEL4CR_18_1),
         PINMUX_DATA(DV_D0_MARK,                 PORT58_FN6),
@@ -1633,10 +1520,6 @@ static const pinmux_enum_t pinmux_data[] = {
         PINMUX_DATA(IRQ16_PORT211_MARK,         PORT211_FN0,    MSEL1CR_16_1),
         PINMUX_DATA(HDMI_CEC_MARK,              PORT211_FN1),
 
-        /* LCDC select */
-        PINMUX_DATA(LCDC0_SELECT_MARK,                          MSEL3CR_6_0),
-        PINMUX_DATA(LCDC1_SELECT_MARK,                          MSEL3CR_6_1),
-
         /* SDENC */
         PINMUX_DATA(SDENC_CPG_MARK,                             MSEL4CR_19_0),
         PINMUX_DATA(SDENC_DV_CLKI_MARK,                         MSEL4CR_19_1),
@@ -1654,9 +1537,565 @@ static const pinmux_enum_t pinmux_data[] = {
         PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK,                    MSEL5CR_30_1,   MSEL5CR_29_0),
 };
 
+#define R8A7740_PIN(pin, cfgs)                                          \
+        {                                                               \
+                .name = __stringify(PORT##pin),                         \
+                .enum_id = PORT##pin##_DATA,                            \
+                .configs = cfgs,                                        \
+        }
+
+#define __I             (SH_PFC_PIN_CFG_INPUT)
+#define __O             (SH_PFC_PIN_CFG_OUTPUT)
+#define __IO            (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
+#define __PD            (SH_PFC_PIN_CFG_PULL_DOWN)
+#define __PU            (SH_PFC_PIN_CFG_PULL_UP)
+#define __PUD           (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
+
+#define R8A7740_PIN_I_PD(pin)           R8A7740_PIN(pin, __I | __PD)
+#define R8A7740_PIN_I_PU(pin)           R8A7740_PIN(pin, __I | __PU)
+#define R8A7740_PIN_I_PU_PD(pin)                R8A7740_PIN(pin, __I | __PUD)
+#define R8A7740_PIN_IO(pin)             R8A7740_PIN(pin, __IO)
+#define R8A7740_PIN_IO_PD(pin)          R8A7740_PIN(pin, __IO | __PD)
+#define R8A7740_PIN_IO_PU(pin)          R8A7740_PIN(pin, __IO | __PU)
+#define R8A7740_PIN_IO_PU_PD(pin)       R8A7740_PIN(pin, __IO | __PUD)
+#define R8A7740_PIN_O(pin)              R8A7740_PIN(pin, __O)
+#define R8A7740_PIN_O_PU_PD(pin)                R8A7740_PIN(pin, __O | __PUD)
+
 static struct sh_pfc_pin pinmux_pins[] = {
-        GPIO_PORT_ALL(),
+        /* Table 56-1 (I/O and Pull U/D) */
+        R8A7740_PIN_IO_PD(0),           R8A7740_PIN_IO_PD(1),
+        R8A7740_PIN_IO_PD(2),           R8A7740_PIN_IO_PD(3),
+        R8A7740_PIN_IO_PD(4),           R8A7740_PIN_IO_PD(5),
+        R8A7740_PIN_IO_PD(6),           R8A7740_PIN_IO(7),
+        R8A7740_PIN_IO(8),              R8A7740_PIN_IO(9),
+        R8A7740_PIN_IO_PD(10),          R8A7740_PIN_IO_PD(11),
+        R8A7740_PIN_IO_PD(12),          R8A7740_PIN_IO_PU_PD(13),
+        R8A7740_PIN_IO_PD(14),          R8A7740_PIN_IO_PD(15),
+        R8A7740_PIN_IO_PD(16),          R8A7740_PIN_IO_PD(17),
+        R8A7740_PIN_IO(18),             R8A7740_PIN_IO_PU(19),
+        R8A7740_PIN_IO_PU_PD(20),       R8A7740_PIN_IO_PD(21),
+        R8A7740_PIN_IO_PU_PD(22),       R8A7740_PIN_IO(23),
+        R8A7740_PIN_IO_PU(24),          R8A7740_PIN_IO_PU(25),
+        R8A7740_PIN_IO_PU(26),          R8A7740_PIN_IO_PU(27),
+        R8A7740_PIN_IO_PU(28),          R8A7740_PIN_IO_PU(29),
+        R8A7740_PIN_IO_PU(30),          R8A7740_PIN_IO_PD(31),
+        R8A7740_PIN_IO_PD(32),          R8A7740_PIN_IO_PD(33),
+        R8A7740_PIN_IO_PD(34),          R8A7740_PIN_IO_PU(35),
+        R8A7740_PIN_IO_PU(36),          R8A7740_PIN_IO_PD(37),
+        R8A7740_PIN_IO_PU(38),          R8A7740_PIN_IO_PD(39),
+        R8A7740_PIN_IO_PU_PD(40),       R8A7740_PIN_IO_PD(41),
+        R8A7740_PIN_IO_PD(42),          R8A7740_PIN_IO_PU_PD(43),
+        R8A7740_PIN_IO_PU_PD(44),       R8A7740_PIN_IO_PU_PD(45),
+        R8A7740_PIN_IO_PU_PD(46),       R8A7740_PIN_IO_PU_PD(47),
+        R8A7740_PIN_IO_PU_PD(48),       R8A7740_PIN_IO_PU_PD(49),
+        R8A7740_PIN_IO_PU_PD(50),       R8A7740_PIN_IO_PD(51),
+        R8A7740_PIN_IO_PD(52),          R8A7740_PIN_IO_PD(53),
+        R8A7740_PIN_IO_PD(54),          R8A7740_PIN_IO_PU_PD(55),
+        R8A7740_PIN_IO_PU_PD(56),       R8A7740_PIN_IO_PU_PD(57),
+        R8A7740_PIN_IO_PU_PD(58),       R8A7740_PIN_IO_PU_PD(59),
+        R8A7740_PIN_IO_PU_PD(60),       R8A7740_PIN_IO_PD(61),
+        R8A7740_PIN_IO_PD(62),          R8A7740_PIN_IO_PD(63),
+        R8A7740_PIN_IO_PD(64),          R8A7740_PIN_IO_PD(65),
+        R8A7740_PIN_IO_PU_PD(66),       R8A7740_PIN_IO_PU_PD(67),
+        R8A7740_PIN_IO_PU_PD(68),       R8A7740_PIN_IO_PU_PD(69),
+        R8A7740_PIN_IO_PU_PD(70),       R8A7740_PIN_IO_PU_PD(71),
+        R8A7740_PIN_IO_PU_PD(72),       R8A7740_PIN_IO_PU_PD(73),
+        R8A7740_PIN_IO_PU_PD(74),       R8A7740_PIN_IO_PU_PD(75),
+        R8A7740_PIN_IO_PU_PD(76),       R8A7740_PIN_IO_PU_PD(77),
+        R8A7740_PIN_IO_PU_PD(78),       R8A7740_PIN_IO_PU_PD(79),
+        R8A7740_PIN_IO_PU_PD(80),       R8A7740_PIN_IO_PU_PD(81),
+        R8A7740_PIN_IO(82),             R8A7740_PIN_IO_PU_PD(83),
+        R8A7740_PIN_IO(84),             R8A7740_PIN_IO_PD(85),
+        R8A7740_PIN_IO_PD(86),          R8A7740_PIN_IO_PD(87),
+        R8A7740_PIN_IO_PD(88),          R8A7740_PIN_IO_PD(89),
+        R8A7740_PIN_IO_PD(90),          R8A7740_PIN_IO_PU_PD(91),
+        R8A7740_PIN_IO_PU_PD(92),       R8A7740_PIN_IO_PU_PD(93),
+        R8A7740_PIN_IO_PU_PD(94),       R8A7740_PIN_IO_PU_PD(95),
+        R8A7740_PIN_IO_PU_PD(96),       R8A7740_PIN_IO_PU_PD(97),
+        R8A7740_PIN_IO_PU_PD(98),       R8A7740_PIN_IO_PU_PD(99),
+        R8A7740_PIN_IO_PU_PD(100),      R8A7740_PIN_IO(101),
+        R8A7740_PIN_IO_PU(102),         R8A7740_PIN_IO_PU_PD(103),
+        R8A7740_PIN_IO_PU(104),         R8A7740_PIN_IO_PU(105),
+        R8A7740_PIN_IO_PU_PD(106),      R8A7740_PIN_IO(107),
+        R8A7740_PIN_IO(108),            R8A7740_PIN_IO(109),
+        R8A7740_PIN_IO(110),            R8A7740_PIN_IO(111),
+        R8A7740_PIN_IO(112),            R8A7740_PIN_IO(113),
+        R8A7740_PIN_IO_PU_PD(114),      R8A7740_PIN_IO(115),
+        R8A7740_PIN_IO_PD(116),         R8A7740_PIN_IO_PD(117),
+        R8A7740_PIN_IO_PD(118),         R8A7740_PIN_IO_PD(119),
+        R8A7740_PIN_IO_PD(120),         R8A7740_PIN_IO_PD(121),
+        R8A7740_PIN_IO_PD(122),         R8A7740_PIN_IO_PD(123),
+        R8A7740_PIN_IO_PD(124),         R8A7740_PIN_IO(125),
+        R8A7740_PIN_IO(126),            R8A7740_PIN_IO(127),
+        R8A7740_PIN_IO(128),            R8A7740_PIN_IO(129),
+        R8A7740_PIN_IO(130),            R8A7740_PIN_IO(131),
+        R8A7740_PIN_IO(132),            R8A7740_PIN_IO(133),
+        R8A7740_PIN_IO(134),            R8A7740_PIN_IO(135),
+        R8A7740_PIN_IO(136),            R8A7740_PIN_IO(137),
+        R8A7740_PIN_IO(138),            R8A7740_PIN_IO(139),
+        R8A7740_PIN_IO(140),            R8A7740_PIN_IO(141),
+        R8A7740_PIN_IO_PU(142),         R8A7740_PIN_IO_PU(143),
+        R8A7740_PIN_IO_PU(144),         R8A7740_PIN_IO_PU(145),
+        R8A7740_PIN_IO_PU(146),         R8A7740_PIN_IO_PU(147),
+        R8A7740_PIN_IO_PU(148),         R8A7740_PIN_IO_PU(149),
+        R8A7740_PIN_IO_PU(150),         R8A7740_PIN_IO_PU(151),
+        R8A7740_PIN_IO_PU(152),         R8A7740_PIN_IO_PU(153),
+        R8A7740_PIN_IO_PU(154),         R8A7740_PIN_IO_PU(155),
+        R8A7740_PIN_IO_PU(156),         R8A7740_PIN_IO_PU(157),
+        R8A7740_PIN_IO_PD(158),         R8A7740_PIN_IO_PD(159),
+        R8A7740_PIN_IO_PU_PD(160),      R8A7740_PIN_IO_PD(161),
+        R8A7740_PIN_IO_PD(162),         R8A7740_PIN_IO_PD(163),
+        R8A7740_PIN_IO_PD(164),         R8A7740_PIN_IO_PD(165),
+        R8A7740_PIN_IO_PU(166),         R8A7740_PIN_IO_PU(167),
+        R8A7740_PIN_IO_PU(168),         R8A7740_PIN_IO_PU(169),
+        R8A7740_PIN_IO_PU(170),         R8A7740_PIN_IO_PU(171),
+        R8A7740_PIN_IO_PD(172),         R8A7740_PIN_IO_PD(173),
+        R8A7740_PIN_IO_PD(174),         R8A7740_PIN_IO_PD(175),
+        R8A7740_PIN_IO_PU(176),         R8A7740_PIN_IO_PU_PD(177),
+        R8A7740_PIN_IO_PU(178),         R8A7740_PIN_IO_PD(179),
+        R8A7740_PIN_IO_PD(180),         R8A7740_PIN_IO_PU(181),
+        R8A7740_PIN_IO_PU(182),         R8A7740_PIN_IO(183),
+        R8A7740_PIN_IO_PD(184),         R8A7740_PIN_IO_PD(185),
+        R8A7740_PIN_IO_PD(186),         R8A7740_PIN_IO_PD(187),
+        R8A7740_PIN_IO_PD(188),         R8A7740_PIN_IO_PD(189),
+        R8A7740_PIN_IO_PD(190),         R8A7740_PIN_IO_PD(191),
+        R8A7740_PIN_IO_PD(192),         R8A7740_PIN_IO_PU_PD(193),
+        R8A7740_PIN_IO_PU_PD(194),      R8A7740_PIN_IO_PD(195),
+        R8A7740_PIN_IO_PU_PD(196),      R8A7740_PIN_IO_PD(197),
+        R8A7740_PIN_IO_PU_PD(198),      R8A7740_PIN_IO_PU_PD(199),
+        R8A7740_PIN_IO_PU_PD(200),      R8A7740_PIN_IO_PU(201),
+        R8A7740_PIN_IO_PU_PD(202),      R8A7740_PIN_IO(203),
+        R8A7740_PIN_IO_PU_PD(204),      R8A7740_PIN_IO_PU_PD(205),
+        R8A7740_PIN_IO_PU_PD(206),      R8A7740_PIN_IO_PU_PD(207),
+        R8A7740_PIN_IO_PU_PD(208),      R8A7740_PIN_IO_PD(209),
+        R8A7740_PIN_IO_PD(210),         R8A7740_PIN_IO_PD(211),
+};
+
+/* - BSC -------------------------------------------------------------------- */
+static const unsigned int bsc_data8_pins[] = {
+        /* D[0:7] */
+        157, 156, 155, 154, 153, 152, 151, 150,
+};
+static const unsigned int bsc_data8_mux[] = {
+        D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
+        D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
+};
+static const unsigned int bsc_data16_pins[] = {
+        /* D[0:15] */
+        157, 156, 155, 154, 153, 152, 151, 150,
+        149, 148, 147, 146, 145, 144, 143, 142,
+};
+static const unsigned int bsc_data16_mux[] = {
+        D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
+        D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
+        D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
+        D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
+};
+static const unsigned int bsc_data32_pins[] = {
+        /* D[0:31] */
+        157, 156, 155, 154, 153, 152, 151, 150,
+        149, 148, 147, 146, 145, 144, 143, 142,
+        171, 170, 169, 168, 167, 166, 173, 172,
+        165, 164, 163, 162, 161, 160, 159, 158,
+};
+static const unsigned int bsc_data32_mux[] = {
+        D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
+        D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
+        D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
+        D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
+        D16_MARK, D17_MARK, D18_MARK, D19_MARK,
+        D20_MARK, D21_MARK, D22_MARK, D23_MARK,
+        D24_MARK, D25_MARK, D26_MARK, D27_MARK,
+        D28_MARK, D29_MARK, D30_MARK, D31_MARK,
+};
+static const unsigned int bsc_cs0_pins[] = {
+        /* CS */
+        109,
+};
+static const unsigned int bsc_cs0_mux[] = {
+        CS0_MARK,
+};
+static const unsigned int bsc_cs2_pins[] = {
+        /* CS */
+        110,
+};
+static const unsigned int bsc_cs2_mux[] = {
+        CS2_MARK,
+};
+static const unsigned int bsc_cs4_pins[] = {
+        /* CS */
+        111,
+};
+static const unsigned int bsc_cs4_mux[] = {
+        CS4_MARK,
+};
+static const unsigned int bsc_cs5a_0_pins[] = {
+        /* CS */
+        105,
+};
+static const unsigned int bsc_cs5a_0_mux[] = {
+        CS5A_PORT105_MARK,
+};
+static const unsigned int bsc_cs5a_1_pins[] = {
+        /* CS */
+        19,
+};
+static const unsigned int bsc_cs5a_1_mux[] = {
+        CS5A_PORT19_MARK,
+};
+static const unsigned int bsc_cs5b_pins[] = {
+        /* CS */
+        103,
+};
+static const unsigned int bsc_cs5b_mux[] = {
+        CS5B_MARK,
+};
+static const unsigned int bsc_cs6a_pins[] = {
+        /* CS */
+        104,
+};
+static const unsigned int bsc_cs6a_mux[] = {
+        CS6A_MARK,
+};
+static const unsigned int bsc_rd_we8_pins[] = {
+        /* RD, WE[0] */
+        115, 113,
+};
+static const unsigned int bsc_rd_we8_mux[] = {
+        RD_FSC_MARK, WE0_FWE_MARK,
+};
+static const unsigned int bsc_rd_we16_pins[] = {
+        /* RD, WE[0:1] */
+        115, 113, 112,
+};
+static const unsigned int bsc_rd_we16_mux[] = {
+        RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK,
+};
+static const unsigned int bsc_rd_we32_pins[] = {
+        /* RD, WE[0:3] */
+        115, 113, 112, 108, 107,
+};
+static const unsigned int bsc_rd_we32_mux[] = {
+        RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK, WE2_ICIORD_MARK, WE3_ICIOWR_MARK,
+};
+static const unsigned int bsc_bs_pins[] = {
+        /* BS */
+        175,
+};
+static const unsigned int bsc_bs_mux[] = {
+        BS_MARK,
+};
+static const unsigned int bsc_rdwr_pins[] = {
+        /* RDWR */
+        114,
+};
+static const unsigned int bsc_rdwr_mux[] = {
+        RDWR_MARK,
+};
+/* - CEU0 ------------------------------------------------------------------- */
+static const unsigned int ceu0_data_0_7_pins[] = {
+        /* D[0:7] */
+        34, 33, 32, 31, 30, 29, 28, 27,
+};
+static const unsigned int ceu0_data_0_7_mux[] = {
+        VIO0_D0_MARK, VIO0_D1_MARK, VIO0_D2_MARK, VIO0_D3_MARK,
+        VIO0_D4_MARK, VIO0_D5_MARK, VIO0_D6_MARK, VIO0_D7_MARK,
+};
+static const unsigned int ceu0_data_8_15_0_pins[] = {
+        /* D[8:15] */
+        182, 181, 180, 179, 178, 26, 25, 24,
+};
+static const unsigned int ceu0_data_8_15_0_mux[] = {
+        VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK,
+        VIO0_D12_MARK, VIO0_D13_PORT26_MARK, VIO0_D14_PORT25_MARK,
+        VIO0_D15_PORT24_MARK,
+};
+static const unsigned int ceu0_data_8_15_1_pins[] = {
+        /* D[8:15] */
+        182, 181, 180, 179, 178, 22, 95, 96,
+};
+static const unsigned int ceu0_data_8_15_1_mux[] = {
+        VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK,
+        VIO0_D12_MARK, VIO0_D13_PORT22_MARK, VIO0_D14_PORT95_MARK,
+        VIO0_D15_PORT96_MARK,
+};
+static const unsigned int ceu0_clk_0_pins[] = {
+        /* CKO */
+        36,
+};
+static const unsigned int ceu0_clk_0_mux[] = {
+        VIO_CKO_MARK,
+};
+static const unsigned int ceu0_clk_1_pins[] = {
+        /* CKO */
+        14,
+};
+static const unsigned int ceu0_clk_1_mux[] = {
+        VIO_CKO1_MARK,
+};
+static const unsigned int ceu0_clk_2_pins[] = {
+        /* CKO */
+        15,
+};
+static const unsigned int ceu0_clk_2_mux[] = {
+        VIO_CKO2_MARK,
+};
+static const unsigned int ceu0_sync_pins[] = {
+        /* CLK, VD, HD */
+        35, 39, 37,
+};
+static const unsigned int ceu0_sync_mux[] = {
+        VIO0_CLK_MARK, VIO0_VD_MARK, VIO0_HD_MARK,
+};
+static const unsigned int ceu0_field_pins[] = {
+        /* FIELD */
+        38,
+};
+static const unsigned int ceu0_field_mux[] = {
+        VIO0_FIELD_MARK,
+};
+/* - CEU1 ------------------------------------------------------------------- */
+static const unsigned int ceu1_data_pins[] = {
+        /* D[0:7] */
+        182, 181, 180, 179, 178, 26, 25, 24,
+};
+static const unsigned int ceu1_data_mux[] = {
+        VIO1_D0_MARK, VIO1_D1_MARK, VIO1_D2_MARK, VIO1_D3_MARK,
+        VIO1_D4_MARK, VIO1_D5_MARK, VIO1_D6_MARK, VIO1_D7_MARK,
+};
+static const unsigned int ceu1_clk_pins[] = {
+        /* CKO */
+        23,
+};
+static const unsigned int ceu1_clk_mux[] = {
+        VIO_CKO_1_MARK,
+};
+static const unsigned int ceu1_sync_pins[] = {
+        /* CLK, VD, HD */
+        197, 198, 160,
+};
+static const unsigned int ceu1_sync_mux[] = {
+        VIO1_CLK_MARK, VIO1_VD_MARK, VIO1_HD_MARK,
+};
+static const unsigned int ceu1_field_pins[] = {
+        /* FIELD */
+        21,
+};
+static const unsigned int ceu1_field_mux[] = {
+        VIO1_FIELD_MARK,
+};
+/* - FSIA ------------------------------------------------------------------- */
+static const unsigned int fsia_mclk_in_pins[] = {
+        /* CK */
+        11,
+};
+static const unsigned int fsia_mclk_in_mux[] = {
+        FSIACK_MARK,
+};
+static const unsigned int fsia_mclk_out_pins[] = {
+        /* OMC */
+        10,
+};
+static const unsigned int fsia_mclk_out_mux[] = {
+        FSIAOMC_MARK,
+};
+static const unsigned int fsia_sclk_in_pins[] = {
+        /* ILR, IBT */
+        12, 13,
+};
+static const unsigned int fsia_sclk_in_mux[] = {
+        FSIAILR_MARK, FSIAIBT_MARK,
+};
+static const unsigned int fsia_sclk_out_pins[] = {
+        /* OLR, OBT */
+        7, 8,
+};
+static const unsigned int fsia_sclk_out_mux[] = {
+        FSIAOLR_MARK, FSIAOBT_MARK,
+};
+static const unsigned int fsia_data_in_0_pins[] = {
+        /* ISLD */
+        0,
 };
+static const unsigned int fsia_data_in_0_mux[] = {
+        FSIAISLD_PORT0_MARK,
+};
+static const unsigned int fsia_data_in_1_pins[] = {
+        /* ISLD */
+        5,
+};
+static const unsigned int fsia_data_in_1_mux[] = {
+        FSIAISLD_PORT5_MARK,
+};
+static const unsigned int fsia_data_out_0_pins[] = {
+        /* OSLD */
+        9,
+};
+static const unsigned int fsia_data_out_0_mux[] = {
+        FSIAOSLD_MARK,
+};
+static const unsigned int fsia_data_out_1_pins[] = {
+        /* OSLD */
+        0,
+};
+static const unsigned int fsia_data_out_1_mux[] = {
+        FSIAOSLD1_MARK,
+};
+static const unsigned int fsia_data_out_2_pins[] = {
+        /* OSLD */
+        1,
+};
+static const unsigned int fsia_data_out_2_mux[] = {
+        FSIAOSLD2_MARK,
+};
+static const unsigned int fsia_spdif_0_pins[] = {
+        /* SPDIF */
+        9,
+};
+static const unsigned int fsia_spdif_0_mux[] = {
+        FSIASPDIF_PORT9_MARK,
+};
+static const unsigned int fsia_spdif_1_pins[] = {
+        /* SPDIF */
+        18,
+};
+static const unsigned int fsia_spdif_1_mux[] = {
+        FSIASPDIF_PORT18_MARK,
+};
+/* - FSIB ------------------------------------------------------------------- */
+static const unsigned int fsib_mclk_in_pins[] = {
+        /* CK */
+        11,
+};
+static const unsigned int fsib_mclk_in_mux[] = {
+        FSIBCK_MARK,
+};
+/* - GETHER ----------------------------------------------------------------- */
+static const unsigned int gether_rmii_pins[] = {
+        /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK, MDC, MDIO */
+        195, 196, 194, 193, 200, 201, 199, 159, 202, 208,
+};
+static const unsigned int gether_rmii_mux[] = {
+        RMII_RXD0_MARK, RMII_RXD1_MARK, RMII_RX_ER_MARK, RMII_CRS_DV_MARK,
+        RMII_TXD0_MARK, RMII_TXD1_MARK, RMII_TX_EN_MARK, RMII_REF50CK_MARK,
+        RMII_MDC_MARK, RMII_MDIO_MARK,
+};
+static const unsigned int gether_mii_pins[] = {
+        /* RXD[0:3], RX_CLK, RX_DV, RX_ER
+         * TXD[0:3], TX_CLK, TX_EN, TX_ER
+         * CRS, COL, MDC, MDIO,
+         */
+        185, 186, 187, 188, 174, 161, 204,
+        171, 170, 169, 168, 184, 183, 203,
+        205, 163, 206, 207,
+};
+static const unsigned int gether_mii_mux[] = {
+        ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
+        ET_RX_CLK_MARK, ET_RX_DV_MARK, ET_RX_ER_MARK,
+        ET_ETXD0_MARK, ET_ETXD1_MARK, ET_ETXD2_MARK, ET_ETXD3_MARK,
+        ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_TX_ER_MARK,
+        ET_CRS_MARK, ET_COL_MARK, ET_MDC_MARK, ET_MDIO_MARK,
+};
+static const unsigned int gether_gmii_pins[] = {
+        /* RXD[0:7], RX_CLK, RX_DV, RX_ER
+         * TXD[0:7], GTX_CLK, TX_CLK, TX_EN, TX_ER
+         * CRS, COL, MDC, MDIO, REF125CK_MARK,
+         */
+        185, 186, 187, 188, 189, 190, 191, 192, 174, 161, 204,
+        171, 170, 169, 168, 167, 166, 173, 172, 176, 184, 183, 203,
+        205, 163, 206, 207,
+};
+static const unsigned int gether_gmii_mux[] = {
+        ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
+        ET_ERXD4_MARK, ET_ERXD5_MARK, ET_ERXD6_MARK, ET_ERXD7_MARK,
+        ET_RX_CLK_MARK, ET_RX_DV_MARK, ET_RX_ER_MARK,
+        ET_ETXD0_MARK, ET_ETXD1_MARK, ET_ETXD2_MARK, ET_ETXD3_MARK,
+        ET_ETXD4_MARK, ET_ETXD5_MARK, ET_ETXD6_MARK, ET_ETXD7_MARK,
+        ET_GTX_CLK_MARK, ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_TX_ER_MARK,
+        ET_CRS_MARK, ET_COL_MARK, ET_MDC_MARK, ET_MDIO_MARK,
+        RMII_REF125CK_MARK,
+};
+static const unsigned int gether_int_pins[] = {
+        /* PHY_INT */
+        164,
+};
+static const unsigned int gether_int_mux[] = {
+        ET_PHY_INT_MARK,
+};
+static const unsigned int gether_link_pins[] = {
+        /* LINK */
+        177,
+};
+static const unsigned int gether_link_mux[] = {
+        ET_LINK_MARK,
+};
+static const unsigned int gether_wol_pins[] = {
+        /* WOL */
+        175,
+};
+static const unsigned int gether_wol_mux[] = {
+        ET_WOL_MARK,
+};
+/* - HDMI ------------------------------------------------------------------- */
+static const unsigned int hdmi_pins[] = {
+        /* HPD, CEC */
+        210, 211,
+};
+static const unsigned int hdmi_mux[] = {
+        HDMI_HPD_MARK, HDMI_CEC_MARK,
+};
+/* - INTC ------------------------------------------------------------------- */
+IRQC_PINS_MUX(0, 0, 2);
+IRQC_PINS_MUX(0, 1, 13);
+IRQC_PIN_MUX(1, 20);
+IRQC_PINS_MUX(2, 0, 11);
+IRQC_PINS_MUX(2, 1, 12);
+IRQC_PINS_MUX(3, 0, 10);
+IRQC_PINS_MUX(3, 1, 14);
+IRQC_PINS_MUX(4, 0, 15);
+IRQC_PINS_MUX(4, 1, 172);
+IRQC_PINS_MUX(5, 0, 0);
+IRQC_PINS_MUX(5, 1, 1);
+IRQC_PINS_MUX(6, 0, 121);
+IRQC_PINS_MUX(6, 1, 173);
+IRQC_PINS_MUX(7, 0, 120);
+IRQC_PINS_MUX(7, 1, 209);
+IRQC_PIN_MUX(8, 119);
+IRQC_PINS_MUX(9, 0, 118);
+IRQC_PINS_MUX(9, 1, 210);
+IRQC_PIN_MUX(10, 19);
+IRQC_PIN_MUX(11, 104);
+IRQC_PINS_MUX(12, 0, 42);
+IRQC_PINS_MUX(12, 1, 97);
+IRQC_PINS_MUX(13, 0, 64);
+IRQC_PINS_MUX(13, 1, 98);
+IRQC_PINS_MUX(14, 0, 63);
+IRQC_PINS_MUX(14, 1, 99);
+IRQC_PINS_MUX(15, 0, 62);
+IRQC_PINS_MUX(15, 1, 100);
+IRQC_PINS_MUX(16, 0, 68);
+IRQC_PINS_MUX(16, 1, 211);
+IRQC_PIN_MUX(17, 69);
+IRQC_PIN_MUX(18, 70);
+IRQC_PIN_MUX(19, 71);
+IRQC_PIN_MUX(20, 67);
+IRQC_PIN_MUX(21, 202);
+IRQC_PIN_MUX(22, 95);
+IRQC_PIN_MUX(23, 96);
+IRQC_PIN_MUX(24, 180);
+IRQC_PIN_MUX(25, 38);
+IRQC_PINS_MUX(26, 0, 58);
+IRQC_PINS_MUX(26, 1, 81);
+IRQC_PINS_MUX(27, 0, 57);
+IRQC_PINS_MUX(27, 1, 168);
+IRQC_PINS_MUX(28, 0, 56);
+IRQC_PINS_MUX(28, 1, 169);
+IRQC_PINS_MUX(29, 0, 50);
+IRQC_PINS_MUX(29, 1, 170);
+IRQC_PINS_MUX(30, 0, 49);
+IRQC_PINS_MUX(30, 1, 171);
+IRQC_PINS_MUX(31, 0, 41);
+IRQC_PINS_MUX(31, 1, 167);
 
 /* - LCD0 ------------------------------------------------------------------- */
 static const unsigned int lcd0_data8_pins[] = {
@@ -1930,6 +2369,260 @@ static const unsigned int mmc0_ctrl_1_pins[] = {
 static const unsigned int mmc0_ctrl_1_mux[] = {
         MMC1_CMD_PORT104_MARK, MMC1_CLK_PORT103_MARK,
 };
+/* - SCIFA0 ----------------------------------------------------------------- */
+static const unsigned int scifa0_data_pins[] = {
+        /* RXD, TXD */
+        197, 198,
+};
+static const unsigned int scifa0_data_mux[] = {
+        SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
+};
+static const unsigned int scifa0_clk_pins[] = {
+        /* SCK */
+        188,
+};
+static const unsigned int scifa0_clk_mux[] = {
+        SCIFA0_SCK_MARK,
+};
+static const unsigned int scifa0_ctrl_pins[] = {
+        /* RTS, CTS */
+        194, 193,
+};
+static const unsigned int scifa0_ctrl_mux[] = {
+        SCIFA0_RTS_MARK, SCIFA0_CTS_MARK,
+};
+/* - SCIFA1 ----------------------------------------------------------------- */
+static const unsigned int scifa1_data_pins[] = {
+        /* RXD, TXD */
+        195, 196,
+};
+static const unsigned int scifa1_data_mux[] = {
+        SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
+};
+static const unsigned int scifa1_clk_pins[] = {
+        /* SCK */
+        185,
+};
+static const unsigned int scifa1_clk_mux[] = {
+        SCIFA1_SCK_MARK,
+};
+static const unsigned int scifa1_ctrl_pins[] = {
+        /* RTS, CTS */
+        23, 21,
+};
+static const unsigned int scifa1_ctrl_mux[] = {
+        SCIFA1_RTS_MARK, SCIFA1_CTS_MARK,
+};
+/* - SCIFA2 ----------------------------------------------------------------- */
+static const unsigned int scifa2_data_pins[] = {
+        /* RXD, TXD */
+        200, 201,
+};
+static const unsigned int scifa2_data_mux[] = {
+        SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
+};
+static const unsigned int scifa2_clk_0_pins[] = {
+        /* SCK */
+        22,
+};
+static const unsigned int scifa2_clk_0_mux[] = {
+        SCIFA2_SCK_PORT22_MARK,
+};
+static const unsigned int scifa2_clk_1_pins[] = {
+        /* SCK */
+        199,
+};
+static const unsigned int scifa2_clk_1_mux[] = {
+        SCIFA2_SCK_PORT199_MARK,
+};
+static const unsigned int scifa2_ctrl_pins[] = {
+        /* RTS, CTS */
+        96, 95,
+};
+static const unsigned int scifa2_ctrl_mux[] = {
+        SCIFA2_RTS_MARK, SCIFA2_CTS_MARK,
+};
+/* - SCIFA3 ----------------------------------------------------------------- */
+static const unsigned int scifa3_data_0_pins[] = {
+        /* RXD, TXD */
+        174, 175,
+};
+static const unsigned int scifa3_data_0_mux[] = {
+        SCIFA3_RXD_PORT174_MARK, SCIFA3_TXD_PORT175_MARK,
+};
+static const unsigned int scifa3_clk_0_pins[] = {
+        /* SCK */
+        116,
+};
+static const unsigned int scifa3_clk_0_mux[] = {
+        SCIFA3_SCK_PORT116_MARK,
+};
+static const unsigned int scifa3_ctrl_0_pins[] = {
+        /* RTS, CTS */
+        105, 117,
+};
+static const unsigned int scifa3_ctrl_0_mux[] = {
+        SCIFA3_RTS_PORT105_MARK, SCIFA3_CTS_PORT117_MARK,
+};
+static const unsigned int scifa3_data_1_pins[] = {
+        /* RXD, TXD */
+        159, 160,
+};
+static const unsigned int scifa3_data_1_mux[] = {
+        SCIFA3_RXD_PORT159_MARK, SCIFA3_TXD_PORT160_MARK,
+};
+static const unsigned int scifa3_clk_1_pins[] = {
+        /* SCK */
+        158,
+};
+static const unsigned int scifa3_clk_1_mux[] = {
+        SCIFA3_SCK_PORT158_MARK,
+};
+static const unsigned int scifa3_ctrl_1_pins[] = {
+        /* RTS, CTS */
+        161, 162,
+};
+static const unsigned int scifa3_ctrl_1_mux[] = {
+        SCIFA3_RTS_PORT161_MARK, SCIFA3_CTS_PORT162_MARK,
+};
+/* - SCIFA4 ----------------------------------------------------------------- */
+static const unsigned int scifa4_data_0_pins[] = {
+        /* RXD, TXD */
+        12, 13,
+};
+static const unsigned int scifa4_data_0_mux[] = {
+        SCIFA4_RXD_PORT12_MARK, SCIFA4_TXD_PORT13_MARK,
+};
+static const unsigned int scifa4_data_1_pins[] = {
+        /* RXD, TXD */
+        204, 203,
+};
+static const unsigned int scifa4_data_1_mux[] = {
+        SCIFA4_RXD_PORT204_MARK, SCIFA4_TXD_PORT203_MARK,
+};
+static const unsigned int scifa4_data_2_pins[] = {
+        /* RXD, TXD */
+        94, 93,
+};
+static const unsigned int scifa4_data_2_mux[] = {
+        SCIFA4_RXD_PORT94_MARK, SCIFA4_TXD_PORT93_MARK,
+};
+static const unsigned int scifa4_clk_0_pins[] = {
+        /* SCK */
+        21,
+};
+static const unsigned int scifa4_clk_0_mux[] = {
+        SCIFA4_SCK_PORT21_MARK,
+};
+static const unsigned int scifa4_clk_1_pins[] = {
+        /* SCK */
+        205,
+};
+static const unsigned int scifa4_clk_1_mux[] = {
+        SCIFA4_SCK_PORT205_MARK,
+};
+/* - SCIFA5 ----------------------------------------------------------------- */
+static const unsigned int scifa5_data_0_pins[] = {
+        /* RXD, TXD */
+        10, 20,
+};
+static const unsigned int scifa5_data_0_mux[] = {
+        SCIFA5_RXD_PORT10_MARK, SCIFA5_TXD_PORT20_MARK,
+};
+static const unsigned int scifa5_data_1_pins[] = {
+        /* RXD, TXD */
+        207, 208,
+};
+static const unsigned int scifa5_data_1_mux[] = {
+        SCIFA5_RXD_PORT207_MARK, SCIFA5_TXD_PORT208_MARK,
+};
+static const unsigned int scifa5_data_2_pins[] = {
+        /* RXD, TXD */
+        92, 91,
+};
+static const unsigned int scifa5_data_2_mux[] = {
+        SCIFA5_RXD_PORT92_MARK, SCIFA5_TXD_PORT91_MARK,
+};
+static const unsigned int scifa5_clk_0_pins[] = {
+        /* SCK */
+        23,
+};
+static const unsigned int scifa5_clk_0_mux[] = {
+        SCIFA5_SCK_PORT23_MARK,
+};
+static const unsigned int scifa5_clk_1_pins[] = {
+        /* SCK */
+        206,
+};
+static const unsigned int scifa5_clk_1_mux[] = {
+        SCIFA5_SCK_PORT206_MARK,
+};
+/* - SCIFA6 ----------------------------------------------------------------- */
+static const unsigned int scifa6_data_pins[] = {
+        /* RXD, TXD */
+        25, 26,
+};
+static const unsigned int scifa6_data_mux[] = {
+        SCIFA6_RXD_MARK, SCIFA6_TXD_MARK,
+};
+static const unsigned int scifa6_clk_pins[] = {
+        /* SCK */
+        24,
+};
+static const unsigned int scifa6_clk_mux[] = {
+        SCIFA6_SCK_MARK,
+};
+/* - SCIFA7 ----------------------------------------------------------------- */
+static const unsigned int scifa7_data_pins[] = {
+        /* RXD, TXD */
+        0, 1,
+};
+static const unsigned int scifa7_data_mux[] = {
+        SCIFA7_RXD_MARK, SCIFA7_TXD_MARK,
+};
+/* - SCIFB ------------------------------------------------------------------ */
+static const unsigned int scifb_data_0_pins[] = {
+        /* RXD, TXD */
+        191, 192,
+};
+static const unsigned int scifb_data_0_mux[] = {
+        SCIFB_RXD_PORT191_MARK, SCIFB_TXD_PORT192_MARK,
+};
+static const unsigned int scifb_clk_0_pins[] = {
+        /* SCK */
+        190,
+};
+static const unsigned int scifb_clk_0_mux[] = {
+        SCIFB_SCK_PORT190_MARK,
+};
+static const unsigned int scifb_ctrl_0_pins[] = {
+        /* RTS, CTS */
+        186, 187,
+};
+static const unsigned int scifb_ctrl_0_mux[] = {
+        SCIFB_RTS_PORT186_MARK, SCIFB_CTS_PORT187_MARK,
+};
+static const unsigned int scifb_data_1_pins[] = {
+        /* RXD, TXD */
+        3, 4,
+};
+static const unsigned int scifb_data_1_mux[] = {
+        SCIFB_RXD_PORT3_MARK, SCIFB_TXD_PORT4_MARK,
+};
+static const unsigned int scifb_clk_1_pins[] = {
+        /* SCK */
+        2,
+};
+static const unsigned int scifb_clk_1_mux[] = {
+        SCIFB_SCK_PORT2_MARK,
+};
+static const unsigned int scifb_ctrl_1_pins[] = {
+        /* RTS, CTS */
+        172, 173,
+};
+static const unsigned int scifb_ctrl_1_mux[] = {
+        SCIFB_RTS_PORT172_MARK, SCIFB_CTS_PORT173_MARK,
+};
 /* - SDHI0 ------------------------------------------------------------------ */
 static const unsigned int sdhi0_data1_pins[] = {
         /* D0 */
@@ -2052,8 +2745,141 @@ static const unsigned int sdhi2_wp_1_pins[] = {
 static const unsigned int sdhi2_wp_1_mux[] = {
         SDHI2_WP_PORT25_MARK,
 };
+/* - TPU0 ------------------------------------------------------------------- */
+static const unsigned int tpu0_to0_pins[] = {
+        /* TO */
+        23,
+};
+static const unsigned int tpu0_to0_mux[] = {
+        TPU0TO0_MARK,
+};
+static const unsigned int tpu0_to1_pins[] = {
+        /* TO */
+        21,
+};
+static const unsigned int tpu0_to1_mux[] = {
+        TPU0TO1_MARK,
+};
+static const unsigned int tpu0_to2_0_pins[] = {
+        /* TO */
+        66,
+};
+static const unsigned int tpu0_to2_0_mux[] = {
+        TPU0TO2_PORT66_MARK,
+};
+static const unsigned int tpu0_to2_1_pins[] = {
+        /* TO */
+        202,
+};
+static const unsigned int tpu0_to2_1_mux[] = {
+        TPU0TO2_PORT202_MARK,
+};
+static const unsigned int tpu0_to3_pins[] = {
+        /* TO */
+        180,
+};
+static const unsigned int tpu0_to3_mux[] = {
+        TPU0TO3_MARK,
+};
 
 static const struct sh_pfc_pin_group pinmux_groups[] = {
+        SH_PFC_PIN_GROUP(bsc_data8),
+        SH_PFC_PIN_GROUP(bsc_data16),
+        SH_PFC_PIN_GROUP(bsc_data32),
+        SH_PFC_PIN_GROUP(bsc_cs0),
+        SH_PFC_PIN_GROUP(bsc_cs2),
+        SH_PFC_PIN_GROUP(bsc_cs4),
+        SH_PFC_PIN_GROUP(bsc_cs5a_0),
+        SH_PFC_PIN_GROUP(bsc_cs5a_1),
+        SH_PFC_PIN_GROUP(bsc_cs5b),
+        SH_PFC_PIN_GROUP(bsc_cs6a),
+        SH_PFC_PIN_GROUP(bsc_rd_we8),
+        SH_PFC_PIN_GROUP(bsc_rd_we16),
+        SH_PFC_PIN_GROUP(bsc_rd_we32),
+        SH_PFC_PIN_GROUP(bsc_bs),
+        SH_PFC_PIN_GROUP(bsc_rdwr),
+        SH_PFC_PIN_GROUP(ceu0_data_0_7),
+        SH_PFC_PIN_GROUP(ceu0_data_8_15_0),
+        SH_PFC_PIN_GROUP(ceu0_data_8_15_1),
+        SH_PFC_PIN_GROUP(ceu0_clk_0),
+        SH_PFC_PIN_GROUP(ceu0_clk_1),
+        SH_PFC_PIN_GROUP(ceu0_clk_2),
+        SH_PFC_PIN_GROUP(ceu0_sync),
+        SH_PFC_PIN_GROUP(ceu0_field),
+        SH_PFC_PIN_GROUP(ceu1_data),
+        SH_PFC_PIN_GROUP(ceu1_clk),
+        SH_PFC_PIN_GROUP(ceu1_sync),
+        SH_PFC_PIN_GROUP(ceu1_field),
+        SH_PFC_PIN_GROUP(fsia_mclk_in),
+        SH_PFC_PIN_GROUP(fsia_mclk_out),
+        SH_PFC_PIN_GROUP(fsia_sclk_in),
+        SH_PFC_PIN_GROUP(fsia_sclk_out),
+        SH_PFC_PIN_GROUP(fsia_data_in_0),
+        SH_PFC_PIN_GROUP(fsia_data_in_1),
+        SH_PFC_PIN_GROUP(fsia_data_out_0),
+        SH_PFC_PIN_GROUP(fsia_data_out_1),
+        SH_PFC_PIN_GROUP(fsia_data_out_2),
+        SH_PFC_PIN_GROUP(fsia_spdif_0),
+        SH_PFC_PIN_GROUP(fsia_spdif_1),
+        SH_PFC_PIN_GROUP(fsib_mclk_in),
+        SH_PFC_PIN_GROUP(gether_rmii),
+        SH_PFC_PIN_GROUP(gether_mii),
+        SH_PFC_PIN_GROUP(gether_gmii),
+        SH_PFC_PIN_GROUP(gether_int),
+        SH_PFC_PIN_GROUP(gether_link),
+        SH_PFC_PIN_GROUP(gether_wol),
+        SH_PFC_PIN_GROUP(hdmi),
+        SH_PFC_PIN_GROUP(intc_irq0_0),
+        SH_PFC_PIN_GROUP(intc_irq0_1),
+        SH_PFC_PIN_GROUP(intc_irq1),
+        SH_PFC_PIN_GROUP(intc_irq2_0),
+        SH_PFC_PIN_GROUP(intc_irq2_1),
+        SH_PFC_PIN_GROUP(intc_irq3_0),
+        SH_PFC_PIN_GROUP(intc_irq3_1),
+        SH_PFC_PIN_GROUP(intc_irq4_0),
+        SH_PFC_PIN_GROUP(intc_irq4_1),
+        SH_PFC_PIN_GROUP(intc_irq5_0),
+        SH_PFC_PIN_GROUP(intc_irq5_1),
+        SH_PFC_PIN_GROUP(intc_irq6_0),
+        SH_PFC_PIN_GROUP(intc_irq6_1),
+        SH_PFC_PIN_GROUP(intc_irq7_0),
+        SH_PFC_PIN_GROUP(intc_irq7_1),
+        SH_PFC_PIN_GROUP(intc_irq8),
+        SH_PFC_PIN_GROUP(intc_irq9_0),
+        SH_PFC_PIN_GROUP(intc_irq9_1),
+        SH_PFC_PIN_GROUP(intc_irq10),
+        SH_PFC_PIN_GROUP(intc_irq11),
+        SH_PFC_PIN_GROUP(intc_irq12_0),
+        SH_PFC_PIN_GROUP(intc_irq12_1),
+        SH_PFC_PIN_GROUP(intc_irq13_0),
+        SH_PFC_PIN_GROUP(intc_irq13_1),
+        SH_PFC_PIN_GROUP(intc_irq14_0),
+        SH_PFC_PIN_GROUP(intc_irq14_1),
+        SH_PFC_PIN_GROUP(intc_irq15_0),
+        SH_PFC_PIN_GROUP(intc_irq15_1),
+        SH_PFC_PIN_GROUP(intc_irq16_0),
+        SH_PFC_PIN_GROUP(intc_irq16_1),
+        SH_PFC_PIN_GROUP(intc_irq17),
+        SH_PFC_PIN_GROUP(intc_irq18),
+        SH_PFC_PIN_GROUP(intc_irq19),
+        SH_PFC_PIN_GROUP(intc_irq20),
+        SH_PFC_PIN_GROUP(intc_irq21),
+        SH_PFC_PIN_GROUP(intc_irq22),
+        SH_PFC_PIN_GROUP(intc_irq23),
+        SH_PFC_PIN_GROUP(intc_irq24),
+        SH_PFC_PIN_GROUP(intc_irq25),
+        SH_PFC_PIN_GROUP(intc_irq26_0),
+        SH_PFC_PIN_GROUP(intc_irq26_1),
+        SH_PFC_PIN_GROUP(intc_irq27_0),
+        SH_PFC_PIN_GROUP(intc_irq27_1),
+        SH_PFC_PIN_GROUP(intc_irq28_0),
+        SH_PFC_PIN_GROUP(intc_irq28_1),
+        SH_PFC_PIN_GROUP(intc_irq29_0),
+        SH_PFC_PIN_GROUP(intc_irq29_1),
+        SH_PFC_PIN_GROUP(intc_irq30_0),
+        SH_PFC_PIN_GROUP(intc_irq30_1),
+        SH_PFC_PIN_GROUP(intc_irq31_0),
+        SH_PFC_PIN_GROUP(intc_irq31_1),
         SH_PFC_PIN_GROUP(lcd0_data8),
         SH_PFC_PIN_GROUP(lcd0_data9),
         SH_PFC_PIN_GROUP(lcd0_data12),
@@ -2084,6 +2910,41 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
         SH_PFC_PIN_GROUP(mmc0_data4_1),
         SH_PFC_PIN_GROUP(mmc0_data8_1),
         SH_PFC_PIN_GROUP(mmc0_ctrl_1),
+        SH_PFC_PIN_GROUP(scifa0_data),
+        SH_PFC_PIN_GROUP(scifa0_clk),
+        SH_PFC_PIN_GROUP(scifa0_ctrl),
+        SH_PFC_PIN_GROUP(scifa1_data),
+        SH_PFC_PIN_GROUP(scifa1_clk),
+        SH_PFC_PIN_GROUP(scifa1_ctrl),
+        SH_PFC_PIN_GROUP(scifa2_data),
+        SH_PFC_PIN_GROUP(scifa2_clk_0),
+        SH_PFC_PIN_GROUP(scifa2_clk_1),
+        SH_PFC_PIN_GROUP(scifa2_ctrl),
+        SH_PFC_PIN_GROUP(scifa3_data_0),
+        SH_PFC_PIN_GROUP(scifa3_clk_0),
+        SH_PFC_PIN_GROUP(scifa3_ctrl_0),
+        SH_PFC_PIN_GROUP(scifa3_data_1),
+        SH_PFC_PIN_GROUP(scifa3_clk_1),
+        SH_PFC_PIN_GROUP(scifa3_ctrl_1),
+        SH_PFC_PIN_GROUP(scifa4_data_0),
+        SH_PFC_PIN_GROUP(scifa4_data_1),
+        SH_PFC_PIN_GROUP(scifa4_data_2),
+        SH_PFC_PIN_GROUP(scifa4_clk_0),
+        SH_PFC_PIN_GROUP(scifa4_clk_1),
+        SH_PFC_PIN_GROUP(scifa5_data_0),
+        SH_PFC_PIN_GROUP(scifa5_data_1),
+        SH_PFC_PIN_GROUP(scifa5_data_2),
+        SH_PFC_PIN_GROUP(scifa5_clk_0),
+        SH_PFC_PIN_GROUP(scifa5_clk_1),
+        SH_PFC_PIN_GROUP(scifa6_data),
+        SH_PFC_PIN_GROUP(scifa6_clk),
+        SH_PFC_PIN_GROUP(scifa7_data),
+        SH_PFC_PIN_GROUP(scifb_data_0),
+        SH_PFC_PIN_GROUP(scifb_clk_0),
+        SH_PFC_PIN_GROUP(scifb_ctrl_0),
+        SH_PFC_PIN_GROUP(scifb_data_1),
+        SH_PFC_PIN_GROUP(scifb_clk_1),
+        SH_PFC_PIN_GROUP(scifb_ctrl_1),
         SH_PFC_PIN_GROUP(sdhi0_data1),
         SH_PFC_PIN_GROUP(sdhi0_data4),
         SH_PFC_PIN_GROUP(sdhi0_ctrl),
@@ -2101,6 +2962,132 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
         SH_PFC_PIN_GROUP(sdhi2_wp_0),
         SH_PFC_PIN_GROUP(sdhi2_cd_1),
         SH_PFC_PIN_GROUP(sdhi2_wp_1),
+        SH_PFC_PIN_GROUP(tpu0_to0),
+        SH_PFC_PIN_GROUP(tpu0_to1),
+        SH_PFC_PIN_GROUP(tpu0_to2_0),
+        SH_PFC_PIN_GROUP(tpu0_to2_1),
+        SH_PFC_PIN_GROUP(tpu0_to3),
+};
+
+static const char * const bsc_groups[] = {
+        "bsc_data8",
+        "bsc_data16",
+        "bsc_data32",
+        "bsc_cs0",
+        "bsc_cs2",
+        "bsc_cs4",
+        "bsc_cs5a_0",
+        "bsc_cs5a_1",
+        "bsc_cs5b",
+        "bsc_cs6a",
+        "bsc_rd_we8",
+        "bsc_rd_we16",
+        "bsc_rd_we32",
+        "bsc_bs",
+        "bsc_rdwr",
+};
+
+static const char * const ceu0_groups[] = {
+        "ceu0_data_0_7",
+        "ceu0_data_8_15_0",
+        "ceu0_data_8_15_1",
+        "ceu0_clk_0",
+        "ceu0_clk_1",
+        "ceu0_clk_2",
+        "ceu0_sync",
+        "ceu0_field",
+};
+
+static const char * const ceu1_groups[] = {
+        "ceu1_data",
+        "ceu1_clk",
+        "ceu1_sync",
+        "ceu1_field",
+};
+
+static const char * const fsia_groups[] = {
+        "fsia_mclk_in",
+        "fsia_mclk_out",
+        "fsia_sclk_in",
+        "fsia_sclk_out",
+        "fsia_data_in_0",
+        "fsia_data_in_1",
+        "fsia_data_out_0",
+        "fsia_data_out_1",
+        "fsia_data_out_2",
+        "fsia_spdif_0",
+        "fsia_spdif_1",
+};
+
+static const char * const fsib_groups[] = {
+        "fsib_mclk_in",
+};
+
+static const char * const gether_groups[] = {
+        "gether_rmii",
+        "gether_mii",
+        "gether_gmii",
+        "gether_int",
+        "gether_link",
+        "gether_wol",
+};
+
+static const char * const hdmi_groups[] = {
+        "hdmi",
+};
+
+static const char * const intc_groups[] = {
+        "intc_irq0_0",
+        "intc_irq0_1",
+        "intc_irq1",
+        "intc_irq2_0",
+        "intc_irq2_1",
+        "intc_irq3_0",
+        "intc_irq3_1",
+        "intc_irq4_0",
+        "intc_irq4_1",
+        "intc_irq5_0",
+        "intc_irq5_1",
+        "intc_irq6_0",
+        "intc_irq6_1",
+        "intc_irq7_0",
+        "intc_irq7_1",
+        "intc_irq8",
+        "intc_irq9_0",
+        "intc_irq9_1",
+        "intc_irq10",
+        "intc_irq11",
+        "intc_irq12_0",
+        "intc_irq12_1",
+        "intc_irq13_0",
+        "intc_irq13_1",
+        "intc_irq14_0",
+        "intc_irq14_1",
+        "intc_irq15_0",
+        "intc_irq15_1",
+        "intc_irq16_0",
+        "intc_irq16_1",
+        "intc_irq17",
+        "intc_irq18",
+        "intc_irq19",
+        "intc_irq20",
+        "intc_irq21",
+        "intc_irq22",
+        "intc_irq23",
+        "intc_irq24",
+        "intc_irq25",
+        "intc_irq26_0",
+        "intc_irq26_1",
+        "intc_irq27_0",
+        "intc_irq27_1",
+        "intc_irq28_0",
+        "intc_irq28_1",
+        "intc_irq29_0",
+        "intc_irq29_1",
+        "intc_irq30_0",
+        "intc_irq30_1",
+        "intc_irq31_0",
+        "intc_irq31_1",
 };
 
 static const char * const lcd0_groups[] = {
@@ -2142,6 +3129,68 @@ static const char * const mmc0_groups[] = {
         "mmc0_ctrl_1",
 };
 
+static const char * const scifa0_groups[] = {
+        "scifa0_data",
+        "scifa0_clk",
+        "scifa0_ctrl",
+};
+
+static const char * const scifa1_groups[] = {
+        "scifa1_data",
+        "scifa1_clk",
+        "scifa1_ctrl",
+};
+
+static const char * const scifa2_groups[] = {
+        "scifa2_data",
+        "scifa2_clk_0",
+        "scifa2_clk_1",
+        "scifa2_ctrl",
+};
+
+static const char * const scifa3_groups[] = {
+        "scifa3_data_0",
+        "scifa3_clk_0",
+        "scifa3_ctrl_0",
+        "scifa3_data_1",
+        "scifa3_clk_1",
+        "scifa3_ctrl_1",
+};
+
+static const char * const scifa4_groups[] = {
+        "scifa4_data_0",
+        "scifa4_data_1",
+        "scifa4_data_2",
+        "scifa4_clk_0",
+        "scifa4_clk_1",
+};
+
+static const char * const scifa5_groups[] = {
+        "scifa5_data_0",
+        "scifa5_data_1",
+        "scifa5_data_2",
+        "scifa5_clk_0",
+        "scifa5_clk_1",
+};
+
+static const char * const scifa6_groups[] = {
+        "scifa6_data",
+        "scifa6_clk",
+};
+
+static const char * const scifa7_groups[] = {
+        "scifa7_data",
+};
+
+static const char * const scifb_groups[] = {
+        "scifb_data_0",
+        "scifb_clk_0",
+        "scifb_ctrl_0",
+        "scifb_data_1",
+        "scifb_clk_1",
+        "scifb_ctrl_1",
+};
+
 static const char * const sdhi0_groups[] = {
         "sdhi0_data1",
         "sdhi0_data4",
@@ -2168,412 +3217,51 @@ static const char * const sdhi2_groups[] = {
         "sdhi2_wp_1",
 };
 
+static const char * const tpu0_groups[] = {
+        "tpu0_to0",
+        "tpu0_to1",
+        "tpu0_to2_0",
+        "tpu0_to2_1",
+        "tpu0_to3",
+};
+
 static const struct sh_pfc_function pinmux_functions[] = {
+        SH_PFC_FUNCTION(bsc),
+        SH_PFC_FUNCTION(ceu0),
+        SH_PFC_FUNCTION(ceu1),
+        SH_PFC_FUNCTION(fsia),
+        SH_PFC_FUNCTION(fsib),
+        SH_PFC_FUNCTION(gether),
+        SH_PFC_FUNCTION(hdmi),
+        SH_PFC_FUNCTION(intc),
         SH_PFC_FUNCTION(lcd0),
         SH_PFC_FUNCTION(lcd1),
         SH_PFC_FUNCTION(mmc0),
+        SH_PFC_FUNCTION(scifa0),
+        SH_PFC_FUNCTION(scifa1),
+        SH_PFC_FUNCTION(scifa2),
+        SH_PFC_FUNCTION(scifa3),
+        SH_PFC_FUNCTION(scifa4),
+        SH_PFC_FUNCTION(scifa5),
+        SH_PFC_FUNCTION(scifa6),
+        SH_PFC_FUNCTION(scifa7),
+        SH_PFC_FUNCTION(scifb),
         SH_PFC_FUNCTION(sdhi0),
         SH_PFC_FUNCTION(sdhi1),
         SH_PFC_FUNCTION(sdhi2),
+        SH_PFC_FUNCTION(tpu0),
 };
 
-#define PINMUX_FN_BASE  ARRAY_SIZE(pinmux_pins)
-
-static const struct pinmux_func pinmux_func_gpios[] = {
-        /* IRQ */
-        GPIO_FN(IRQ0_PORT2),    GPIO_FN(IRQ0_PORT13),
-        GPIO_FN(IRQ1),
-        GPIO_FN(IRQ2_PORT11),   GPIO_FN(IRQ2_PORT12),
-        GPIO_FN(IRQ3_PORT10),   GPIO_FN(IRQ3_PORT14),
-        GPIO_FN(IRQ4_PORT15),   GPIO_FN(IRQ4_PORT172),
-        GPIO_FN(IRQ5_PORT0),    GPIO_FN(IRQ5_PORT1),
-        GPIO_FN(IRQ6_PORT121),  GPIO_FN(IRQ6_PORT173),
-        GPIO_FN(IRQ7_PORT120),  GPIO_FN(IRQ7_PORT209),
-        GPIO_FN(IRQ8),
-        GPIO_FN(IRQ9_PORT118),  GPIO_FN(IRQ9_PORT210),
-        GPIO_FN(IRQ10),
-        GPIO_FN(IRQ11),
-        GPIO_FN(IRQ12_PORT42),  GPIO_FN(IRQ12_PORT97),
-        GPIO_FN(IRQ13_PORT64),  GPIO_FN(IRQ13_PORT98),
-        GPIO_FN(IRQ14_PORT63),  GPIO_FN(IRQ14_PORT99),
-        GPIO_FN(IRQ15_PORT62),  GPIO_FN(IRQ15_PORT100),
-        GPIO_FN(IRQ16_PORT68),  GPIO_FN(IRQ16_PORT211),
-        GPIO_FN(IRQ17),
-        GPIO_FN(IRQ18),
-        GPIO_FN(IRQ19),
-        GPIO_FN(IRQ20),
-        GPIO_FN(IRQ21),
-        GPIO_FN(IRQ22),
-        GPIO_FN(IRQ23),
-        GPIO_FN(IRQ24),
-        GPIO_FN(IRQ25),
-        GPIO_FN(IRQ26_PORT58),  GPIO_FN(IRQ26_PORT81),
-        GPIO_FN(IRQ27_PORT57),  GPIO_FN(IRQ27_PORT168),
-        GPIO_FN(IRQ28_PORT56),  GPIO_FN(IRQ28_PORT169),
-        GPIO_FN(IRQ29_PORT50),  GPIO_FN(IRQ29_PORT170),
-        GPIO_FN(IRQ30_PORT49),  GPIO_FN(IRQ30_PORT171),
-        GPIO_FN(IRQ31_PORT41),  GPIO_FN(IRQ31_PORT167),
-
-        /* Function */
-
-        /* DBGT */
-        GPIO_FN(DBGMDT2),       GPIO_FN(DBGMDT1),       GPIO_FN(DBGMDT0),
-        GPIO_FN(DBGMD10),       GPIO_FN(DBGMD11),       GPIO_FN(DBGMD20),
-        GPIO_FN(DBGMD21),
-
-        /* FSI-A */
-        GPIO_FN(FSIAISLD_PORT0),        /* FSIAISLD Port 0/5 */
-        GPIO_FN(FSIAISLD_PORT5),
-        GPIO_FN(FSIASPDIF_PORT9),       /* FSIASPDIF Port 9/18 */
-        GPIO_FN(FSIASPDIF_PORT18),
-        GPIO_FN(FSIAOSLD1),     GPIO_FN(FSIAOSLD2),     GPIO_FN(FSIAOLR),
-        GPIO_FN(FSIAOBT),       GPIO_FN(FSIAOSLD),      GPIO_FN(FSIAOMC),
-        GPIO_FN(FSIACK),        GPIO_FN(FSIAILR),       GPIO_FN(FSIAIBT),
-
-        /* FSI-B */
-        GPIO_FN(FSIBCK),
-
-        /* FMSI */
-        GPIO_FN(FMSISLD_PORT1), /* FMSISLD Port 1/6 */
-        GPIO_FN(FMSISLD_PORT6),
-        GPIO_FN(FMSIILR),       GPIO_FN(FMSIIBT),       GPIO_FN(FMSIOLR),
-        GPIO_FN(FMSIOBT),       GPIO_FN(FMSICK),        GPIO_FN(FMSOILR),
-        GPIO_FN(FMSOIBT),       GPIO_FN(FMSOOLR),       GPIO_FN(FMSOOBT),
-        GPIO_FN(FMSOSLD),       GPIO_FN(FMSOCK),
-
-        /* SCIFA0 */
-        GPIO_FN(SCIFA0_SCK),    GPIO_FN(SCIFA0_CTS),    GPIO_FN(SCIFA0_RTS),
-        GPIO_FN(SCIFA0_RXD),    GPIO_FN(SCIFA0_TXD),
-
-        /* SCIFA1 */
-        GPIO_FN(SCIFA1_CTS),    GPIO_FN(SCIFA1_SCK),
-        GPIO_FN(SCIFA1_RXD),    GPIO_FN(SCIFA1_TXD),    GPIO_FN(SCIFA1_RTS),
-
-        /* SCIFA2 */
-        GPIO_FN(SCIFA2_SCK_PORT22), /* SCIFA2_SCK Port 22/199 */
-        GPIO_FN(SCIFA2_SCK_PORT199),
-        GPIO_FN(SCIFA2_RXD),    GPIO_FN(SCIFA2_TXD),
-        GPIO_FN(SCIFA2_CTS),    GPIO_FN(SCIFA2_RTS),
-
-        /* SCIFA3 */
-        GPIO_FN(SCIFA3_RTS_PORT105), /* MSEL5CR_8_0 */
-        GPIO_FN(SCIFA3_SCK_PORT116),
-        GPIO_FN(SCIFA3_CTS_PORT117),
-        GPIO_FN(SCIFA3_RXD_PORT174),
-        GPIO_FN(SCIFA3_TXD_PORT175),
-
-        GPIO_FN(SCIFA3_RTS_PORT161), /* MSEL5CR_8_1 */
-        GPIO_FN(SCIFA3_SCK_PORT158),
-        GPIO_FN(SCIFA3_CTS_PORT162),
-        GPIO_FN(SCIFA3_RXD_PORT159),
-        GPIO_FN(SCIFA3_TXD_PORT160),
-
-        /* SCIFA4 */
-        GPIO_FN(SCIFA4_RXD_PORT12), /* MSEL5CR[12:11] = 00 */
-        GPIO_FN(SCIFA4_TXD_PORT13),
-
-        GPIO_FN(SCIFA4_RXD_PORT204), /* MSEL5CR[12:11] = 01 */
-        GPIO_FN(SCIFA4_TXD_PORT203),
-
-        GPIO_FN(SCIFA4_RXD_PORT94), /* MSEL5CR[12:11] = 10 */
-        GPIO_FN(SCIFA4_TXD_PORT93),
-
-        GPIO_FN(SCIFA4_SCK_PORT21), /* SCIFA4_SCK Port 21/205 */
-        GPIO_FN(SCIFA4_SCK_PORT205),
-
-        /* SCIFA5 */
-        GPIO_FN(SCIFA5_TXD_PORT20), /* MSEL5CR[15:14] = 00 */
-        GPIO_FN(SCIFA5_RXD_PORT10),
-
-        GPIO_FN(SCIFA5_RXD_PORT207), /* MSEL5CR[15:14] = 01 */
-        GPIO_FN(SCIFA5_TXD_PORT208),
-
-        GPIO_FN(SCIFA5_TXD_PORT91), /* MSEL5CR[15:14] = 10 */
-        GPIO_FN(SCIFA5_RXD_PORT92),
-
-        GPIO_FN(SCIFA5_SCK_PORT23), /* SCIFA5_SCK Port 23/206 */
-        GPIO_FN(SCIFA5_SCK_PORT206),
-
-        /* SCIFA6 */
-        GPIO_FN(SCIFA6_SCK),    GPIO_FN(SCIFA6_RXD),    GPIO_FN(SCIFA6_TXD),
-
-        /* SCIFA7 */
-        GPIO_FN(SCIFA7_TXD),    GPIO_FN(SCIFA7_RXD),
-
-        /* SCIFAB */
-        GPIO_FN(SCIFB_SCK_PORT190), /* MSEL5CR_17_0 */
-        GPIO_FN(SCIFB_RXD_PORT191),
-        GPIO_FN(SCIFB_TXD_PORT192),
-        GPIO_FN(SCIFB_RTS_PORT186),
-        GPIO_FN(SCIFB_CTS_PORT187),
-
-        GPIO_FN(SCIFB_SCK_PORT2), /* MSEL5CR_17_1 */
-        GPIO_FN(SCIFB_RXD_PORT3),
-        GPIO_FN(SCIFB_TXD_PORT4),
-        GPIO_FN(SCIFB_RTS_PORT172),
-        GPIO_FN(SCIFB_CTS_PORT173),
-
-        /* RSPI */
-        GPIO_FN(RSPI_SSL0_A),   GPIO_FN(RSPI_SSL1_A),   GPIO_FN(RSPI_SSL2_A),
-        GPIO_FN(RSPI_SSL3_A),   GPIO_FN(RSPI_CK_A),     GPIO_FN(RSPI_MOSI_A),
-        GPIO_FN(RSPI_MISO_A),
-
-        /* VIO CKO */
-        GPIO_FN(VIO_CKO1),
-        GPIO_FN(VIO_CKO2),
-        GPIO_FN(VIO_CKO_1),
-        GPIO_FN(VIO_CKO),
-
-        /* VIO0 */
-        GPIO_FN(VIO0_D0),       GPIO_FN(VIO0_D1),       GPIO_FN(VIO0_D2),
-        GPIO_FN(VIO0_D3),       GPIO_FN(VIO0_D4),       GPIO_FN(VIO0_D5),
-        GPIO_FN(VIO0_D6),       GPIO_FN(VIO0_D7),       GPIO_FN(VIO0_D8),
-        GPIO_FN(VIO0_D9),       GPIO_FN(VIO0_D10),      GPIO_FN(VIO0_D11),
-        GPIO_FN(VIO0_D12),      GPIO_FN(VIO0_VD),       GPIO_FN(VIO0_HD),
-        GPIO_FN(VIO0_CLK),      GPIO_FN(VIO0_FIELD),
-
-        GPIO_FN(VIO0_D13_PORT26), /* MSEL5CR_27_0 */
-        GPIO_FN(VIO0_D14_PORT25),
-        GPIO_FN(VIO0_D15_PORT24),
-
-        GPIO_FN(VIO0_D13_PORT22), /* MSEL5CR_27_1 */
-        GPIO_FN(VIO0_D14_PORT95),
-        GPIO_FN(VIO0_D15_PORT96),
-
-        /* VIO1 */
-        GPIO_FN(VIO1_D0),       GPIO_FN(VIO1_D1),       GPIO_FN(VIO1_D2),
-        GPIO_FN(VIO1_D3),       GPIO_FN(VIO1_D4),       GPIO_FN(VIO1_D5),
-        GPIO_FN(VIO1_D6),       GPIO_FN(VIO1_D7),       GPIO_FN(VIO1_VD),
-        GPIO_FN(VIO1_HD),       GPIO_FN(VIO1_CLK),      GPIO_FN(VIO1_FIELD),
-
-        /* TPU0 */
-        GPIO_FN(TPU0TO0),       GPIO_FN(TPU0TO1),       GPIO_FN(TPU0TO3),
-        GPIO_FN(TPU0TO2_PORT66), /* TPU0TO2 Port 66/202 */
-        GPIO_FN(TPU0TO2_PORT202),
-
-        /* SSP1 0 */
-        GPIO_FN(STP0_IPD0),     GPIO_FN(STP0_IPD1),     GPIO_FN(STP0_IPD2),
-        GPIO_FN(STP0_IPD3),     GPIO_FN(STP0_IPD4),     GPIO_FN(STP0_IPD5),
-        GPIO_FN(STP0_IPD6),     GPIO_FN(STP0_IPD7),     GPIO_FN(STP0_IPEN),
-        GPIO_FN(STP0_IPCLK),    GPIO_FN(STP0_IPSYNC),
-
-        /* SSP1 1 */
-        GPIO_FN(STP1_IPD1),     GPIO_FN(STP1_IPD2),     GPIO_FN(STP1_IPD3),
-        GPIO_FN(STP1_IPD4),     GPIO_FN(STP1_IPD5),     GPIO_FN(STP1_IPD6),
-        GPIO_FN(STP1_IPD7),     GPIO_FN(STP1_IPCLK),    GPIO_FN(STP1_IPSYNC),
-
-        GPIO_FN(STP1_IPD0_PORT186), /* MSEL5CR_23_0 */
-        GPIO_FN(STP1_IPEN_PORT187),
-
-        GPIO_FN(STP1_IPD0_PORT194), /* MSEL5CR_23_1 */
-        GPIO_FN(STP1_IPEN_PORT193),
-
-        /* SIM */
-        GPIO_FN(SIM_RST),       GPIO_FN(SIM_CLK),
-        GPIO_FN(SIM_D_PORT22), /* SIM_D  Port 22/199 */
-        GPIO_FN(SIM_D_PORT199),
-
-        /* MSIOF2 */
-        GPIO_FN(MSIOF2_TXD),    GPIO_FN(MSIOF2_RXD),    GPIO_FN(MSIOF2_TSCK),
-        GPIO_FN(MSIOF2_SS2),    GPIO_FN(MSIOF2_TSYNC),  GPIO_FN(MSIOF2_SS1),
-        GPIO_FN(MSIOF2_MCK1),   GPIO_FN(MSIOF2_MCK0),   GPIO_FN(MSIOF2_RSYNC),
-        GPIO_FN(MSIOF2_RSCK),
-
-        /* KEYSC */
-        GPIO_FN(KEYIN4),        GPIO_FN(KEYIN5),
-        GPIO_FN(KEYIN6),        GPIO_FN(KEYIN7),
-        GPIO_FN(KEYOUT0),       GPIO_FN(KEYOUT1),       GPIO_FN(KEYOUT2),
-        GPIO_FN(KEYOUT3),       GPIO_FN(KEYOUT4),       GPIO_FN(KEYOUT5),
-        GPIO_FN(KEYOUT6),       GPIO_FN(KEYOUT7),
-
-        GPIO_FN(KEYIN0_PORT43), /* MSEL4CR_18_0 */
-        GPIO_FN(KEYIN1_PORT44),
-        GPIO_FN(KEYIN2_PORT45),
-        GPIO_FN(KEYIN3_PORT46),
-
-        GPIO_FN(KEYIN0_PORT58), /* MSEL4CR_18_1 */
-        GPIO_FN(KEYIN1_PORT57),
-        GPIO_FN(KEYIN2_PORT56),
-        GPIO_FN(KEYIN3_PORT55),
-
-        /* VOU */
-        GPIO_FN(DV_D0),         GPIO_FN(DV_D1),         GPIO_FN(DV_D2),
-        GPIO_FN(DV_D3),         GPIO_FN(DV_D4),         GPIO_FN(DV_D5),
-        GPIO_FN(DV_D6),         GPIO_FN(DV_D7),         GPIO_FN(DV_D8),
-        GPIO_FN(DV_D9),         GPIO_FN(DV_D10),        GPIO_FN(DV_D11),
-        GPIO_FN(DV_D12),        GPIO_FN(DV_D13),        GPIO_FN(DV_D14),
-        GPIO_FN(DV_D15),        GPIO_FN(DV_CLK),
-        GPIO_FN(DV_VSYNC),      GPIO_FN(DV_HSYNC),
-
-        /* MEMC */
-        GPIO_FN(MEMC_AD0),      GPIO_FN(MEMC_AD1),      GPIO_FN(MEMC_AD2),
-        GPIO_FN(MEMC_AD3),      GPIO_FN(MEMC_AD4),      GPIO_FN(MEMC_AD5),
-        GPIO_FN(MEMC_AD6),      GPIO_FN(MEMC_AD7),      GPIO_FN(MEMC_AD8),
-        GPIO_FN(MEMC_AD9),      GPIO_FN(MEMC_AD10),     GPIO_FN(MEMC_AD11),
-        GPIO_FN(MEMC_AD12),     GPIO_FN(MEMC_AD13),     GPIO_FN(MEMC_AD14),
-        GPIO_FN(MEMC_AD15),     GPIO_FN(MEMC_CS0),      GPIO_FN(MEMC_INT),
-        GPIO_FN(MEMC_NWE),      GPIO_FN(MEMC_NOE),      GPIO_FN(MEMC_CS1),
-        GPIO_FN(MEMC_A1),       GPIO_FN(MEMC_ADV),      GPIO_FN(MEMC_DREQ0),
-        GPIO_FN(MEMC_WAIT),     GPIO_FN(MEMC_DREQ1),    GPIO_FN(MEMC_BUSCLK),
-        GPIO_FN(MEMC_A0),
-
-        /* MSIOF0 */
-        GPIO_FN(MSIOF0_SS1),    GPIO_FN(MSIOF0_SS2),    GPIO_FN(MSIOF0_RXD),
-        GPIO_FN(MSIOF0_TXD),    GPIO_FN(MSIOF0_MCK0),   GPIO_FN(MSIOF0_MCK1),
-        GPIO_FN(MSIOF0_RSYNC),  GPIO_FN(MSIOF0_RSCK),   GPIO_FN(MSIOF0_TSCK),
-        GPIO_FN(MSIOF0_TSYNC),
-
-        /* MSIOF1 */
-        GPIO_FN(MSIOF1_RSCK),   GPIO_FN(MSIOF1_RSYNC),
-        GPIO_FN(MSIOF1_MCK0),   GPIO_FN(MSIOF1_MCK1),
-
-        GPIO_FN(MSIOF1_SS2_PORT116),    GPIO_FN(MSIOF1_SS1_PORT117),
-        GPIO_FN(MSIOF1_RXD_PORT118),    GPIO_FN(MSIOF1_TXD_PORT119),
-        GPIO_FN(MSIOF1_TSYNC_PORT120),
-        GPIO_FN(MSIOF1_TSCK_PORT121),   /* MSEL4CR_10_0 */
-
-        GPIO_FN(MSIOF1_SS1_PORT67),     GPIO_FN(MSIOF1_TSCK_PORT72),
-        GPIO_FN(MSIOF1_TSYNC_PORT73),   GPIO_FN(MSIOF1_TXD_PORT74),
-        GPIO_FN(MSIOF1_RXD_PORT75),
-        GPIO_FN(MSIOF1_SS2_PORT202),    /* MSEL4CR_10_1 */
-
-        /* GPIO */
-        GPIO_FN(GPO0),  GPIO_FN(GPI0),
-        GPIO_FN(GPO1),  GPIO_FN(GPI1),
-
-        /* USB0 */
-        GPIO_FN(USB0_OCI),      GPIO_FN(USB0_PPON),     GPIO_FN(VBUS),
-
-        /* USB1 */
-        GPIO_FN(USB1_OCI),      GPIO_FN(USB1_PPON),
-
-        /* BBIF1 */
-        GPIO_FN(BBIF1_RXD),     GPIO_FN(BBIF1_TXD),     GPIO_FN(BBIF1_TSYNC),
-        GPIO_FN(BBIF1_TSCK),    GPIO_FN(BBIF1_RSCK),    GPIO_FN(BBIF1_RSYNC),
-        GPIO_FN(BBIF1_FLOW),    GPIO_FN(BBIF1_RX_FLOW_N),
-
-        /* BBIF2 */
-        GPIO_FN(BBIF2_TXD2_PORT5), /* MSEL5CR_0_0 */
-        GPIO_FN(BBIF2_RXD2_PORT60),
-        GPIO_FN(BBIF2_TSYNC2_PORT6),
-        GPIO_FN(BBIF2_TSCK2_PORT59),
-
-        GPIO_FN(BBIF2_RXD2_PORT90), /* MSEL5CR_0_1 */
-        GPIO_FN(BBIF2_TXD2_PORT183),
-        GPIO_FN(BBIF2_TSCK2_PORT89),
-        GPIO_FN(BBIF2_TSYNC2_PORT184),
-
-        /* BSC / FLCTL / PCMCIA */
-        GPIO_FN(CS0),   GPIO_FN(CS2),   GPIO_FN(CS4),
-        GPIO_FN(CS5B),  GPIO_FN(CS6A),
-        GPIO_FN(CS5A_PORT105), /* CS5A PORT 19/105 */
-        GPIO_FN(CS5A_PORT19),
-        GPIO_FN(IOIS16), /* ? */
-
-        GPIO_FN(A0),    GPIO_FN(A1),    GPIO_FN(A2),    GPIO_FN(A3),
-        GPIO_FN(A4_FOE),        GPIO_FN(A5_FCDE),       /* share with FLCTL */
-        GPIO_FN(A6),    GPIO_FN(A7),    GPIO_FN(A8),    GPIO_FN(A9),
-        GPIO_FN(A10),   GPIO_FN(A11),   GPIO_FN(A12),   GPIO_FN(A13),
-        GPIO_FN(A14),   GPIO_FN(A15),   GPIO_FN(A16),   GPIO_FN(A17),
-        GPIO_FN(A18),   GPIO_FN(A19),   GPIO_FN(A20),   GPIO_FN(A21),
-        GPIO_FN(A22),   GPIO_FN(A23),   GPIO_FN(A24),   GPIO_FN(A25),
-        GPIO_FN(A26),
-
-        GPIO_FN(D0_NAF0),       GPIO_FN(D1_NAF1),       /* share with FLCTL */
-        GPIO_FN(D2_NAF2),       GPIO_FN(D3_NAF3),       /* share with FLCTL */
-        GPIO_FN(D4_NAF4),       GPIO_FN(D5_NAF5),       /* share with FLCTL */
-        GPIO_FN(D6_NAF6),       GPIO_FN(D7_NAF7),       /* share with FLCTL */
-        GPIO_FN(D8_NAF8),       GPIO_FN(D9_NAF9),       /* share with FLCTL */
-        GPIO_FN(D10_NAF10),     GPIO_FN(D11_NAF11),     /* share with FLCTL */
-        GPIO_FN(D12_NAF12),     GPIO_FN(D13_NAF13),     /* share with FLCTL */
-        GPIO_FN(D14_NAF14),     GPIO_FN(D15_NAF15),     /* share with FLCTL */
-        GPIO_FN(D16),   GPIO_FN(D17),   GPIO_FN(D18),   GPIO_FN(D19),
-        GPIO_FN(D20),   GPIO_FN(D21),   GPIO_FN(D22),   GPIO_FN(D23),
-        GPIO_FN(D24),   GPIO_FN(D25),   GPIO_FN(D26),   GPIO_FN(D27),
-        GPIO_FN(D28),   GPIO_FN(D29),   GPIO_FN(D30),   GPIO_FN(D31),
-
-        GPIO_FN(WE0_FWE),       /* share with FLCTL */
-        GPIO_FN(WE1),
-        GPIO_FN(WE2_ICIORD),    /* share with PCMCIA */
-        GPIO_FN(WE3_ICIOWR),    /* share with PCMCIA */
-        GPIO_FN(CKO),   GPIO_FN(BS),    GPIO_FN(RDWR),
-        GPIO_FN(RD_FSC),        /* share with FLCTL */
-        GPIO_FN(WAIT_PORT177), /* WAIT Port 90/177 */
-        GPIO_FN(WAIT_PORT90),
-
-        GPIO_FN(FCE0),  GPIO_FN(FCE1),  GPIO_FN(FRB), /* FLCTL */
-
-        /* IRDA */
-        GPIO_FN(IRDA_FIRSEL),   GPIO_FN(IRDA_IN),       GPIO_FN(IRDA_OUT),
-
-        /* ATAPI */
-        GPIO_FN(IDE_D0),        GPIO_FN(IDE_D1),        GPIO_FN(IDE_D2),
-        GPIO_FN(IDE_D3),        GPIO_FN(IDE_D4),        GPIO_FN(IDE_D5),
-        GPIO_FN(IDE_D6),        GPIO_FN(IDE_D7),        GPIO_FN(IDE_D8),
-        GPIO_FN(IDE_D9),        GPIO_FN(IDE_D10),       GPIO_FN(IDE_D11),
-        GPIO_FN(IDE_D12),       GPIO_FN(IDE_D13),       GPIO_FN(IDE_D14),
-        GPIO_FN(IDE_D15),       GPIO_FN(IDE_A0),        GPIO_FN(IDE_A1),
-        GPIO_FN(IDE_A2),        GPIO_FN(IDE_CS0),       GPIO_FN(IDE_CS1),
-        GPIO_FN(IDE_IOWR),      GPIO_FN(IDE_IORD),      GPIO_FN(IDE_IORDY),
-        GPIO_FN(IDE_INT),       GPIO_FN(IDE_RST),       GPIO_FN(IDE_DIRECTION),
-        GPIO_FN(IDE_EXBUF_ENB), GPIO_FN(IDE_IODACK),    GPIO_FN(IDE_IODREQ),
-
-        /* RMII */
-        GPIO_FN(RMII_CRS_DV),   GPIO_FN(RMII_RX_ER),    GPIO_FN(RMII_RXD0),
-        GPIO_FN(RMII_RXD1),     GPIO_FN(RMII_TX_EN),    GPIO_FN(RMII_TXD0),
-        GPIO_FN(RMII_MDC),      GPIO_FN(RMII_TXD1),     GPIO_FN(RMII_MDIO),
-        GPIO_FN(RMII_REF50CK),  GPIO_FN(RMII_REF125CK), /* for GMII */
-
-        /* GEther */
-        GPIO_FN(ET_TX_CLK),     GPIO_FN(ET_TX_EN),      GPIO_FN(ET_ETXD0),
-        GPIO_FN(ET_ETXD1),      GPIO_FN(ET_ETXD2),      GPIO_FN(ET_ETXD3),
-        GPIO_FN(ET_ETXD4),      GPIO_FN(ET_ETXD5), /* for GEther */
-        GPIO_FN(ET_ETXD6),      GPIO_FN(ET_ETXD7), /* for GEther */
-        GPIO_FN(ET_COL),        GPIO_FN(ET_TX_ER),      GPIO_FN(ET_RX_CLK),
-        GPIO_FN(ET_RX_DV),      GPIO_FN(ET_ERXD0),      GPIO_FN(ET_ERXD1),
-        GPIO_FN(ET_ERXD2),      GPIO_FN(ET_ERXD3),
-        GPIO_FN(ET_ERXD4),      GPIO_FN(ET_ERXD5), /* for GEther */
-        GPIO_FN(ET_ERXD6),      GPIO_FN(ET_ERXD7), /* for GEther */
-        GPIO_FN(ET_RX_ER),      GPIO_FN(ET_CRS),        GPIO_FN(ET_MDC),
-        GPIO_FN(ET_MDIO),       GPIO_FN(ET_LINK),       GPIO_FN(ET_PHY_INT),
-        GPIO_FN(ET_WOL),        GPIO_FN(ET_GTX_CLK),
-
-        /* DMA0 */
-        GPIO_FN(DREQ0), GPIO_FN(DACK0),
-
-        /* DMA1 */
-        GPIO_FN(DREQ1), GPIO_FN(DACK1),
-
-        /* SYSC */
-        GPIO_FN(RESETOUTS),
-
-        /* IRREM */
-        GPIO_FN(IROUT),
-
-        /* LCDC */
-        GPIO_FN(LCDC0_SELECT),
-        GPIO_FN(LCDC1_SELECT),
-
-        /* SDENC */
-        GPIO_FN(SDENC_CPG),
-        GPIO_FN(SDENC_DV_CLKI),
-
-        /* HDMI */
-        GPIO_FN(HDMI_HPD),
-        GPIO_FN(HDMI_CEC),
-
-        /* SYSC */
-        GPIO_FN(RESETP_PULLUP),
-        GPIO_FN(RESETP_PLAIN),
-
-        /* DEBUG */
-        GPIO_FN(EDEBGREQ_PULLDOWN),
-        GPIO_FN(EDEBGREQ_PULLUP),
-
-        GPIO_FN(TRACEAUD_FROM_VIO),
-        GPIO_FN(TRACEAUD_FROM_LCDC0),
-        GPIO_FN(TRACEAUD_FROM_MEMC),
-};
+#undef PORTCR
+#define PORTCR(nr, reg)                                                 \
+        {                                                               \
+                PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) {             \
+                        _PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT),     \
+                                PORT##nr##_FN0, PORT##nr##_FN1,         \
+                                PORT##nr##_FN2, PORT##nr##_FN3,         \
+                                PORT##nr##_FN4, PORT##nr##_FN5,         \
+                                PORT##nr##_FN6, PORT##nr##_FN7 }        \
+        }
 
 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
         PORTCR(0,       0xe6050000), /* PORT0CR */
@@ -2994,48 +3682,114 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
 };
 
 static const struct pinmux_irq pinmux_irqs[] = {
-        PINMUX_IRQ(irq_pin(0), GPIO_PORT2,   GPIO_PORT13),      /* IRQ0A */
-        PINMUX_IRQ(irq_pin(1), GPIO_PORT20),            /* IRQ1A */
-        PINMUX_IRQ(irq_pin(2), GPIO_PORT11,  GPIO_PORT12),      /* IRQ2A */
-        PINMUX_IRQ(irq_pin(3), GPIO_PORT10,  GPIO_PORT14),      /* IRQ3A */
-        PINMUX_IRQ(irq_pin(4), GPIO_PORT15,  GPIO_PORT172),/* IRQ4A */
-        PINMUX_IRQ(irq_pin(5), GPIO_PORT0,   GPIO_PORT1),       /* IRQ5A */
-        PINMUX_IRQ(irq_pin(6), GPIO_PORT121, GPIO_PORT173),/* IRQ6A */
-        PINMUX_IRQ(irq_pin(7), GPIO_PORT120, GPIO_PORT209),/* IRQ7A */
-        PINMUX_IRQ(irq_pin(8), GPIO_PORT119),           /* IRQ8A */
-        PINMUX_IRQ(irq_pin(9), GPIO_PORT118, GPIO_PORT210),/* IRQ9A */
-        PINMUX_IRQ(irq_pin(10), GPIO_PORT19),           /* IRQ10A */
-        PINMUX_IRQ(irq_pin(11), GPIO_PORT104),          /* IRQ11A */
-        PINMUX_IRQ(irq_pin(12), GPIO_PORT42,  GPIO_PORT97),     /* IRQ12A */
-        PINMUX_IRQ(irq_pin(13), GPIO_PORT64,  GPIO_PORT98),     /* IRQ13A */
-        PINMUX_IRQ(irq_pin(14), GPIO_PORT63,  GPIO_PORT99),     /* IRQ14A */
-        PINMUX_IRQ(irq_pin(15), GPIO_PORT62,  GPIO_PORT100),/* IRQ15A */
-        PINMUX_IRQ(irq_pin(16), GPIO_PORT68,  GPIO_PORT211),/* IRQ16A */
-        PINMUX_IRQ(irq_pin(17), GPIO_PORT69),           /* IRQ17A */
-        PINMUX_IRQ(irq_pin(18), GPIO_PORT70),           /* IRQ18A */
-        PINMUX_IRQ(irq_pin(19), GPIO_PORT71),           /* IRQ19A */
-        PINMUX_IRQ(irq_pin(20), GPIO_PORT67),           /* IRQ20A */
-        PINMUX_IRQ(irq_pin(21), GPIO_PORT202),          /* IRQ21A */
-        PINMUX_IRQ(irq_pin(22), GPIO_PORT95),           /* IRQ22A */
-        PINMUX_IRQ(irq_pin(23), GPIO_PORT96),           /* IRQ23A */
-        PINMUX_IRQ(irq_pin(24), GPIO_PORT180),          /* IRQ24A */
-        PINMUX_IRQ(irq_pin(25), GPIO_PORT38),           /* IRQ25A */
-        PINMUX_IRQ(irq_pin(26), GPIO_PORT58,  GPIO_PORT81),     /* IRQ26A */
-        PINMUX_IRQ(irq_pin(27), GPIO_PORT57,  GPIO_PORT168),/* IRQ27A */
-        PINMUX_IRQ(irq_pin(28), GPIO_PORT56,  GPIO_PORT169),/* IRQ28A */
-        PINMUX_IRQ(irq_pin(29), GPIO_PORT50,  GPIO_PORT170),/* IRQ29A */
-        PINMUX_IRQ(irq_pin(30), GPIO_PORT49,  GPIO_PORT171),/* IRQ30A */
-        PINMUX_IRQ(irq_pin(31), GPIO_PORT41,  GPIO_PORT167),/* IRQ31A */
+        PINMUX_IRQ(irq_pin(0), 2,   13),        /* IRQ0A */
+        PINMUX_IRQ(irq_pin(1), 20),             /* IRQ1A */
+        PINMUX_IRQ(irq_pin(2), 11,  12),        /* IRQ2A */
+        PINMUX_IRQ(irq_pin(3), 10,  14),        /* IRQ3A */
+        PINMUX_IRQ(irq_pin(4), 15,  172),       /* IRQ4A */
+        PINMUX_IRQ(irq_pin(5), 0,   1),         /* IRQ5A */
+        PINMUX_IRQ(irq_pin(6), 121, 173),       /* IRQ6A */
+        PINMUX_IRQ(irq_pin(7), 120, 209),       /* IRQ7A */
+        PINMUX_IRQ(irq_pin(8), 119),            /* IRQ8A */
+        PINMUX_IRQ(irq_pin(9), 118, 210),       /* IRQ9A */
+        PINMUX_IRQ(irq_pin(10), 19),            /* IRQ10A */
+        PINMUX_IRQ(irq_pin(11), 104),           /* IRQ11A */
+        PINMUX_IRQ(irq_pin(12), 42,  97),       /* IRQ12A */
+        PINMUX_IRQ(irq_pin(13), 64,  98),       /* IRQ13A */
+        PINMUX_IRQ(irq_pin(14), 63,  99),       /* IRQ14A */
+        PINMUX_IRQ(irq_pin(15), 62,  100),      /* IRQ15A */
+        PINMUX_IRQ(irq_pin(16), 68,  211),      /* IRQ16A */
+        PINMUX_IRQ(irq_pin(17), 69),            /* IRQ17A */
+        PINMUX_IRQ(irq_pin(18), 70),            /* IRQ18A */
+        PINMUX_IRQ(irq_pin(19), 71),            /* IRQ19A */
+        PINMUX_IRQ(irq_pin(20), 67),            /* IRQ20A */
+        PINMUX_IRQ(irq_pin(21), 202),           /* IRQ21A */
+        PINMUX_IRQ(irq_pin(22), 95),            /* IRQ22A */
+        PINMUX_IRQ(irq_pin(23), 96),            /* IRQ23A */
+        PINMUX_IRQ(irq_pin(24), 180),           /* IRQ24A */
+        PINMUX_IRQ(irq_pin(25), 38),            /* IRQ25A */
+        PINMUX_IRQ(irq_pin(26), 58,  81),       /* IRQ26A */
+        PINMUX_IRQ(irq_pin(27), 57,  168),      /* IRQ27A */
+        PINMUX_IRQ(irq_pin(28), 56,  169),      /* IRQ28A */
+        PINMUX_IRQ(irq_pin(29), 50,  170),      /* IRQ29A */
+        PINMUX_IRQ(irq_pin(30), 49,  171),      /* IRQ30A */
+        PINMUX_IRQ(irq_pin(31), 41,  167),      /* IRQ31A */
+};
+
+#define PORTnCR_PULMD_OFF       (0 << 6)
+#define PORTnCR_PULMD_DOWN      (2 << 6)
+#define PORTnCR_PULMD_UP        (3 << 6)
+#define PORTnCR_PULMD_MASK      (3 << 6)
+
+struct r8a7740_portcr_group {
+        unsigned int end_pin;
+        unsigned int offset;
+};
+
+static const struct r8a7740_portcr_group r8a7740_portcr_offsets[] = {
+        { 83, 0x0000 }, { 114, 0x1000 }, { 209, 0x2000 }, { 211, 0x3000 },
+};
+
+static void __iomem *r8a7740_pinmux_portcr(struct sh_pfc *pfc, unsigned int pin)
+{
+        unsigned int i;
+
+        for (i = 0; i < ARRAY_SIZE(r8a7740_portcr_offsets); ++i) {
+                const struct r8a7740_portcr_group *group =
+                        &r8a7740_portcr_offsets[i];
+
+                if (i <= group->end_pin)
+                        return pfc->window->virt + group->offset + pin;
+        }
+
+        return NULL;
+}
+
+static unsigned int r8a7740_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
+{
+        void __iomem *addr = r8a7740_pinmux_portcr(pfc, pin);
+        u32 value = ioread8(addr) & PORTnCR_PULMD_MASK;
+
+        switch (value) {
+        case PORTnCR_PULMD_UP:
+                return PIN_CONFIG_BIAS_PULL_UP;
+        case PORTnCR_PULMD_DOWN:
+                return PIN_CONFIG_BIAS_PULL_DOWN;
+        case PORTnCR_PULMD_OFF:
+        default:
+                return PIN_CONFIG_BIAS_DISABLE;
+        }
+}
+
+static void r8a7740_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
+                                   unsigned int bias)
+{
+        void __iomem *addr = r8a7740_pinmux_portcr(pfc, pin);
+        u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK;
+
+        switch (bias) {
+        case PIN_CONFIG_BIAS_PULL_UP:
+                value |= PORTnCR_PULMD_UP;
+                break;
+        case PIN_CONFIG_BIAS_PULL_DOWN:
+                value |= PORTnCR_PULMD_DOWN;
+                break;
+        }
+
+        iowrite8(value, addr);
+}
+
+static const struct sh_pfc_soc_operations r8a7740_pinmux_ops = {
+        .get_bias = r8a7740_pinmux_get_bias,
+        .set_bias = r8a7740_pinmux_set_bias,
 };
 
 const struct sh_pfc_soc_info r8a7740_pinmux_info = {
         .name           = "r8a7740_pfc",
+        .ops            = &r8a7740_pinmux_ops,
+
         .input          = { PINMUX_INPUT_BEGIN,
                             PINMUX_INPUT_END },
-        .input_pu       = { PINMUX_INPUT_PULLUP_BEGIN,
-                            PINMUX_INPUT_PULLUP_END },
-        .input_pd       = { PINMUX_INPUT_PULLDOWN_BEGIN,
-                            PINMUX_INPUT_PULLDOWN_END },
         .output         = { PINMUX_OUTPUT_BEGIN,
                             PINMUX_OUTPUT_END },
         .function       = { PINMUX_FUNCTION_BEGIN,
@@ -3048,9 +3802,6 @@ const struct sh_pfc_soc_info r8a7740_pinmux_info = {
         .functions      = pinmux_functions,
         .nr_functions   = ARRAY_SIZE(pinmux_functions),
 
-        .func_gpios     = pinmux_func_gpios,
-        .nr_func_gpios  = ARRAY_SIZE(pinmux_func_gpios),
-
         .cfg_regs       = pinmux_config_regs,
         .data_regs      = pinmux_data_regs,
 
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
new file mode 100644
index 000000000000..1dcbabcd7b3c
--- /dev/null
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
@@ -0,0 +1,2783 @@
+/*
+ * r8a7778 processor support - PFC hardware block
+ *
+ * Copyright (C) 2013  Renesas Solutions Corp.
+ * Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ * Copyright (C) 2013  Cogent Embedded, Inc.
+ *
+ * based on
+ * Copyright (C) 2011  Renesas Solutions Corp.
+ * Copyright (C) 2011  Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/platform_data/gpio-rcar.h>
+#include <linux/kernel.h>
+#include "sh_pfc.h"
+
+#define PORT_GP_1(bank, pin, fn, sfx) fn(bank, pin, GP_##bank##_##pin, sfx)
+
+#define PORT_GP_32(bank, fn, sfx)                                       \
+        PORT_GP_1(bank, 0,  fn, sfx), PORT_GP_1(bank, 1,  fn, sfx),     \
+        PORT_GP_1(bank, 2,  fn, sfx), PORT_GP_1(bank, 3,  fn, sfx),     \
+        PORT_GP_1(bank, 4,  fn, sfx), PORT_GP_1(bank, 5,  fn, sfx),     \
+        PORT_GP_1(bank, 6,  fn, sfx), PORT_GP_1(bank, 7,  fn, sfx),     \
+        PORT_GP_1(bank, 8,  fn, sfx), PORT_GP_1(bank, 9,  fn, sfx),     \
+        PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx),     \
+        PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx),     \
+        PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx),     \
+        PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx),     \
+        PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx),     \
+        PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx),     \
+        PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx),     \
+        PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx),     \
+        PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx),     \
+        PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx),     \
+        PORT_GP_1(bank, 30, fn, sfx), PORT_GP_1(bank, 31, fn, sfx)
+
+#define PORT_GP_27(bank, fn, sfx)                                       \
+        PORT_GP_1(bank, 0,  fn, sfx), PORT_GP_1(bank, 1,  fn, sfx),     \
+        PORT_GP_1(bank, 2,  fn, sfx), PORT_GP_1(bank, 3,  fn, sfx),     \
+        PORT_GP_1(bank, 4,  fn, sfx), PORT_GP_1(bank, 5,  fn, sfx),     \
+        PORT_GP_1(bank, 6,  fn, sfx), PORT_GP_1(bank, 7,  fn, sfx),     \
+        PORT_GP_1(bank, 8,  fn, sfx), PORT_GP_1(bank, 9,  fn, sfx),     \
+        PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx),     \
+        PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx),     \
+        PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx),     \
+        PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx),     \
+        PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx),     \
+        PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx),     \
+        PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx),     \
+        PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx),     \
+        PORT_GP_1(bank, 26, fn, sfx)
+
+#define CPU_ALL_PORT(fn, sfx)           \
+        PORT_GP_32(0, fn, sfx),         \
+        PORT_GP_32(1, fn, sfx),         \
+        PORT_GP_32(2, fn, sfx),         \
+        PORT_GP_32(3, fn, sfx),         \
+        PORT_GP_27(4, fn, sfx)
+
+#define _GP_PORT_ALL(bank, pin, name, sfx)      name##_##sfx
+
+#define _GP_GPIO(bank, pin, _name, sfx)         \
+        [RCAR_GP_PIN(bank, pin)] = {            \
+                .name = __stringify(_name),     \
+                .enum_id = _name##_DATA,        \
+        }
+
+#define _GP_DATA(bank, pin, name, sfx)          \
+        PINMUX_DATA(name##_DATA, name##_FN)
+
+#define GP_ALL(str)             CPU_ALL_PORT(_GP_PORT_ALL, str)
+#define PINMUX_GPIO_GP_ALL()    CPU_ALL_PORT(_GP_GPIO, unused)
+#define PINMUX_DATA_GP_ALL()    CPU_ALL_PORT(_GP_DATA, unused)
+
+#define PINMUX_IPSR_NOGP(ispr, fn)      PINMUX_DATA(fn##_MARK, FN_##fn)
+#define PINMUX_IPSR_DATA(ipsr, fn)      PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr)
+#define PINMUX_IPSR_MSEL(ipsr, fn, ms)  PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr, FN_##ms)
+#define PINMUX_IPSR_NOGM(ispr, fn, ms)  PINMUX_DATA(fn##_MARK, FN_##fn,            FN_##ms)
+
+enum {
+        PINMUX_RESERVED = 0,
+
+        PINMUX_DATA_BEGIN,
+        GP_ALL(DATA), /* GP_0_0_DATA -> GP_4_26_DATA */
+        PINMUX_DATA_END,
+
+        PINMUX_FUNCTION_BEGIN,
+        GP_ALL(FN), /* GP_0_0_FN -> GP_4_26_FN */
+
+        /* GPSR0 */
+        FN_IP0_1_0,     FN_PENC0,       FN_PENC1,       FN_IP0_4_2,
+        FN_IP0_7_5,     FN_IP0_11_8,    FN_IP0_14_12,   FN_A1,
+        FN_A2,          FN_A3,          FN_IP0_15,      FN_IP0_16,
+        FN_IP0_17,      FN_IP0_18,      FN_IP0_19,      FN_IP0_20,
+        FN_IP0_21,      FN_IP0_22,      FN_IP0_23,      FN_IP0_24,
+        FN_IP0_25,      FN_IP0_26,      FN_IP0_27,      FN_IP0_28,
+        FN_IP0_29,      FN_IP0_30,      FN_IP1_0,       FN_IP1_1,
+        FN_IP1_4_2,     FN_IP1_7_5,     FN_IP1_10_8,    FN_IP1_14_11,
+
+        /* GPSR1 */
+        FN_IP1_23_21,   FN_WE0,         FN_IP1_24,      FN_IP1_27_25,
+        FN_IP1_29_28,   FN_IP2_2_0,     FN_IP2_5_3,     FN_IP2_8_6,
+        FN_IP2_11_9,    FN_IP2_13_12,   FN_IP2_16_14,   FN_IP2_17,
+        FN_IP2_30,      FN_IP2_31,      FN_IP3_1_0,     FN_IP3_4_2,
+        FN_IP3_7_5,     FN_IP3_9_8,     FN_IP3_12_10,   FN_IP3_15_13,
+        FN_IP3_18_16,   FN_IP3_20_19,   FN_IP3_23_21,   FN_IP3_26_24,
+        FN_IP3_27,      FN_IP3_28,      FN_IP3_29,      FN_IP3_30,
+        FN_IP3_31,      FN_IP4_0,       FN_IP4_3_1,     FN_IP4_6_4,
+
+        /* GPSR2 */
+        FN_IP4_7,       FN_IP4_8,       FN_IP4_10_9,    FN_IP4_12_11,
+        FN_IP4_14_13,   FN_IP4_16_15,   FN_IP4_20_17,   FN_IP4_24_21,
+        FN_IP4_26_25,   FN_IP4_28_27,   FN_IP4_30_29,   FN_IP5_1_0,
+        FN_IP5_3_2,     FN_IP5_5_4,     FN_IP5_6,       FN_IP5_7,
+        FN_IP5_9_8,     FN_IP5_11_10,   FN_IP5_12,      FN_IP5_14_13,
+        FN_IP5_17_15,   FN_IP5_20_18,   FN_AUDIO_CLKA,  FN_AUDIO_CLKB,
+        FN_IP5_22_21,   FN_IP5_25_23,   FN_IP5_28_26,   FN_IP5_30_29,
+        FN_IP6_1_0,     FN_IP6_4_2,     FN_IP6_6_5,     FN_IP6_7,
+
+        /* GPSR3 */
+        FN_IP6_8,       FN_IP6_9,       FN_SSI_SCK34,   FN_IP6_10,
+        FN_IP6_12_11,   FN_IP6_13,      FN_IP6_15_14,   FN_IP6_16,
+        FN_IP6_18_17,   FN_IP6_20_19,   FN_IP6_21,      FN_IP6_23_22,
+        FN_IP6_25_24,   FN_IP6_27_26,   FN_IP6_29_28,   FN_IP6_31_30,
+        FN_IP7_1_0,     FN_IP7_3_2,     FN_IP7_5_4,     FN_IP7_8_6,
+        FN_IP7_11_9,    FN_IP7_14_12,   FN_IP7_17_15,   FN_IP7_20_18,
+        FN_IP7_21,      FN_IP7_24_22,   FN_IP7_28_25,   FN_IP7_31_29,
+        FN_IP8_2_0,     FN_IP8_5_3,     FN_IP8_8_6,     FN_IP8_10_9,
+
+        /* GPSR4 */
+        FN_IP8_13_11,   FN_IP8_15_14,   FN_IP8_18_16,   FN_IP8_21_19,
+        FN_IP8_23_22,   FN_IP8_26_24,   FN_IP8_29_27,   FN_IP9_2_0,
+        FN_IP9_5_3,     FN_IP9_8_6,     FN_IP9_11_9,    FN_IP9_14_12,
+        FN_IP9_17_15,   FN_IP9_20_18,   FN_IP9_23_21,   FN_IP9_26_24,
+        FN_IP9_29_27,   FN_IP10_2_0,    FN_IP10_5_3,    FN_IP10_8_6,
+        FN_IP10_12_9,   FN_IP10_15_13,  FN_IP10_18_16,  FN_IP10_21_19,
+        FN_IP10_24_22,  FN_AVS1,        FN_AVS2,
+
+        /* IPSR0 */
+        FN_PRESETOUT,   FN_PWM1,        FN_AUDATA0,     FN_ARM_TRACEDATA_0,
+        FN_GPSCLK_C,    FN_USB_OVC0,    FN_TX2_E,       FN_SDA2_B,
+        FN_AUDATA1,     FN_ARM_TRACEDATA_1,             FN_GPSIN_C,
+        FN_USB_OVC1,    FN_RX2_E,       FN_SCL2_B,      FN_SD1_DAT2_A,
+        FN_MMC_D2,      FN_BS,          FN_ATADIR0_A,   FN_SDSELF_A,
+        FN_PWM4_B,      FN_SD1_DAT3_A,  FN_MMC_D3,      FN_A0,
+        FN_ATAG0_A,     FN_REMOCON_B,   FN_A4,          FN_A5,
+        FN_A6,          FN_A7,          FN_A8,          FN_A9,
+        FN_A10,         FN_A11,         FN_A12,         FN_A13,
+        FN_A14,         FN_A15,         FN_A16,         FN_A17,
+        FN_A18,         FN_A19,
+
+        /* IPSR1 */
+        FN_A20,         FN_HSPI_CS1_B,  FN_A21,         FN_HSPI_CLK1_B,
+        FN_A22,         FN_HRTS0_B,     FN_RX2_B,       FN_DREQ2_A,
+        FN_A23,         FN_HTX0_B,      FN_TX2_B,       FN_DACK2_A,
+        FN_TS_SDEN0_A,  FN_SD1_CD_A,    FN_MMC_D6,      FN_A24,
+        FN_DREQ1_A,     FN_HRX0_B,      FN_TS_SPSYNC0_A,
+        FN_SD1_WP_A,    FN_MMC_D7,      FN_A25, FN_DACK1_A,
+        FN_HCTS0_B,     FN_RX3_C,       FN_TS_SDAT0_A,  FN_CLKOUT,
+        FN_HSPI_TX1_B,  FN_PWM0_B,      FN_CS0,         FN_HSPI_RX1_B,
+        FN_SSI_SCK1_B,  FN_ATAG0_B,     FN_CS1_A26,     FN_SDA2_A,
+        FN_SCK2_B,      FN_MMC_D5,      FN_ATADIR0_B,   FN_RD_WR,
+        FN_WE1,         FN_ATAWR0_B,    FN_SSI_WS1_B,   FN_EX_CS0,
+        FN_SCL2_A,      FN_TX3_C,       FN_TS_SCK0_A,   FN_EX_CS1,
+        FN_MMC_D4,
+
+        /* IPSR2 */
+        FN_SD1_CLK_A,   FN_MMC_CLK,     FN_ATACS00,     FN_EX_CS2,
+        FN_SD1_CMD_A,   FN_MMC_CMD,     FN_ATACS10,     FN_EX_CS3,
+        FN_SD1_DAT0_A,  FN_MMC_D0,      FN_ATARD0,      FN_EX_CS4,
+        FN_EX_WAIT1_A,  FN_SD1_DAT1_A,  FN_MMC_D1,      FN_ATAWR0_A,
+        FN_EX_CS5,      FN_EX_WAIT2_A,  FN_DREQ0_A,     FN_RX3_A,
+        FN_DACK0,       FN_TX3_A,       FN_DRACK0,      FN_EX_WAIT0,
+        FN_PWM0_C,      FN_D0,          FN_D1,          FN_D2,
+        FN_D3,          FN_D4,          FN_D5,          FN_D6,
+        FN_D7,          FN_D8,          FN_D9,          FN_D10,
+        FN_D11,         FN_RD_WR_B,     FN_IRQ0,        FN_MLB_CLK,
+        FN_IRQ1_A,
+
+        /* IPSR3 */
+        FN_MLB_SIG,     FN_RX5_B,       FN_SDA3_A,      FN_IRQ2_A,
+        FN_MLB_DAT,     FN_TX5_B,       FN_SCL3_A,      FN_IRQ3_A,
+        FN_SDSELF_B,    FN_SD1_CMD_B,   FN_SCIF_CLK,    FN_AUDIO_CLKOUT_B,
+        FN_CAN_CLK_B,   FN_SDA3_B,      FN_SD1_CLK_B,   FN_HTX0_A,
+        FN_TX0_A,       FN_SD1_DAT0_B,  FN_HRX0_A,      FN_RX0_A,
+        FN_SD1_DAT1_B,  FN_HSCK0,       FN_SCK0,        FN_SCL3_B,
+        FN_SD1_DAT2_B,  FN_HCTS0_A,     FN_CTS0,        FN_SD1_DAT3_B,
+        FN_HRTS0_A,     FN_RTS0,        FN_SSI_SCK4,    FN_DU0_DR0,
+        FN_LCDOUT0,     FN_AUDATA2,     FN_ARM_TRACEDATA_2,
+        FN_SDA3_C,      FN_ADICHS1,     FN_TS_SDEN0_B,  FN_SSI_WS4,
+        FN_DU0_DR1,     FN_LCDOUT1,     FN_AUDATA3,     FN_ARM_TRACEDATA_3,
+        FN_SCL3_C,      FN_ADICHS2,     FN_TS_SPSYNC0_B,
+        FN_DU0_DR2,     FN_LCDOUT2,     FN_DU0_DR3,     FN_LCDOUT3,
+        FN_DU0_DR4,     FN_LCDOUT4,     FN_DU0_DR5,     FN_LCDOUT5,
+        FN_DU0_DR6,     FN_LCDOUT6,
+
+        /* IPSR4 */
+        FN_DU0_DR7,     FN_LCDOUT7,     FN_DU0_DG0,     FN_LCDOUT8,
+        FN_AUDATA4,     FN_ARM_TRACEDATA_4,             FN_TX1_D,
+        FN_CAN0_TX_A,   FN_ADICHS0,     FN_DU0_DG1,     FN_LCDOUT9,
+        FN_AUDATA5,     FN_ARM_TRACEDATA_5,             FN_RX1_D,
+        FN_CAN0_RX_A,   FN_ADIDATA,     FN_DU0_DG2,     FN_LCDOUT10,
+        FN_DU0_DG3,     FN_LCDOUT11,    FN_DU0_DG4,     FN_LCDOUT12,
+        FN_RX0_B,       FN_DU0_DG5,     FN_LCDOUT13,    FN_TX0_B,
+        FN_DU0_DG6,     FN_LCDOUT14,    FN_RX4_A,       FN_DU0_DG7,
+        FN_LCDOUT15,    FN_TX4_A,       FN_SSI_SCK2_B,  FN_VI0_R0_B,
+        FN_DU0_DB0,     FN_LCDOUT16,    FN_AUDATA6,     FN_ARM_TRACEDATA_6,
+        FN_GPSCLK_A,    FN_PWM0_A,      FN_ADICLK,      FN_TS_SDAT0_B,
+        FN_AUDIO_CLKC,  FN_VI0_R1_B,    FN_DU0_DB1,     FN_LCDOUT17,
+        FN_AUDATA7,     FN_ARM_TRACEDATA_7,             FN_GPSIN_A,
+        FN_ADICS_SAMP,  FN_TS_SCK0_B,   FN_VI0_R2_B,    FN_DU0_DB2,
+        FN_LCDOUT18,    FN_VI0_R3_B,    FN_DU0_DB3,     FN_LCDOUT19,
+        FN_VI0_R4_B,    FN_DU0_DB4,     FN_LCDOUT20,
+
+        /* IPSR5 */
+        FN_VI0_R5_B,    FN_DU0_DB5,     FN_LCDOUT21,    FN_VI1_DATA10_B,
+        FN_DU0_DB6,     FN_LCDOUT22,    FN_VI1_DATA11_B,
+        FN_DU0_DB7,     FN_LCDOUT23,    FN_DU0_DOTCLKIN,
+        FN_QSTVA_QVS,   FN_DU0_DOTCLKO_UT0,             FN_QCLK,
+        FN_DU0_DOTCLKO_UT1,             FN_QSTVB_QVE,   FN_AUDIO_CLKOUT_A,
+        FN_REMOCON_C,   FN_SSI_WS2_B,   FN_DU0_EXHSYNC_DU0_HSYNC,
+        FN_QSTH_QHS,    FN_DU0_EXVSYNC_DU0_VSYNC,       FN_QSTB_QHE,
+        FN_DU0_EXODDF_DU0_ODDF_DISP_CDE,
+        FN_QCPV_QDE,    FN_FMCLK_D,     FN_SSI_SCK1_A,  FN_DU0_DISP,
+        FN_QPOLA,       FN_AUDCK,       FN_ARM_TRACECLK,
+        FN_BPFCLK_D,    FN_SSI_WS1_A,   FN_DU0_CDE,     FN_QPOLB,
+        FN_AUDSYNC,     FN_ARM_TRACECTL,                FN_FMIN_D,
+        FN_SD1_CD_B,    FN_SSI_SCK78,   FN_HSPI_RX0_B,  FN_TX1_B,
+        FN_SD1_WP_B,    FN_SSI_WS78,    FN_HSPI_CLK0_B, FN_RX1_B,
+        FN_CAN_CLK_D,   FN_SSI_SDATA8,  FN_SSI_SCK2_A,  FN_HSPI_CS0_B,
+        FN_TX2_A,       FN_CAN0_TX_B,   FN_SSI_SDATA7,  FN_HSPI_TX0_B,
+        FN_RX2_A,       FN_CAN0_RX_B,
+
+        /* IPSR6 */
+        FN_SSI_SCK6,    FN_HSPI_RX2_A,  FN_FMCLK_B,     FN_CAN1_TX_B,
+        FN_SSI_WS6,     FN_HSPI_CLK2_A, FN_BPFCLK_B,    FN_CAN1_RX_B,
+        FN_SSI_SDATA6,  FN_HSPI_TX2_A,  FN_FMIN_B,      FN_SSI_SCK5,
+        FN_RX4_C,       FN_SSI_WS5,     FN_TX4_C,       FN_SSI_SDATA5,
+        FN_RX0_D,       FN_SSI_WS34,    FN_ARM_TRACEDATA_8,
+        FN_SSI_SDATA4,  FN_SSI_WS2_A,   FN_ARM_TRACEDATA_9,
+        FN_SSI_SDATA3,  FN_ARM_TRACEDATA_10,
+        FN_SSI_SCK012,  FN_ARM_TRACEDATA_11,
+        FN_TX0_D,       FN_SSI_WS012,   FN_ARM_TRACEDATA_12,
+        FN_SSI_SDATA2,  FN_HSPI_CS2_A,  FN_ARM_TRACEDATA_13,
+        FN_SDA1_A,      FN_SSI_SDATA1,  FN_ARM_TRACEDATA_14,
+        FN_SCL1_A,      FN_SCK2_A,      FN_SSI_SDATA0,
+        FN_ARM_TRACEDATA_15,
+        FN_SD0_CLK,     FN_SUB_TDO,     FN_SD0_CMD,     FN_SUB_TRST,
+        FN_SD0_DAT0,    FN_SUB_TMS,     FN_SD0_DAT1,    FN_SUB_TCK,
+        FN_SD0_DAT2,    FN_SUB_TDI,
+
+        /* IPSR7 */
+        FN_SD0_DAT3,    FN_IRQ1_B,      FN_SD0_CD,      FN_TX5_A,
+        FN_SD0_WP,      FN_RX5_A,       FN_VI1_CLKENB,  FN_HSPI_CLK0_A,
+        FN_HTX1_A,      FN_RTS1_C,      FN_VI1_FIELD,   FN_HSPI_CS0_A,
+        FN_HRX1_A,      FN_SCK1_C,      FN_VI1_HSYNC,   FN_HSPI_RX0_A,
+        FN_HRTS1_A,     FN_FMCLK_A,     FN_RX1_C,       FN_VI1_VSYNC,
+        FN_HSPI_TX0,    FN_HCTS1_A,     FN_BPFCLK_A,    FN_TX1_C,
+        FN_TCLK0,       FN_HSCK1_A,     FN_FMIN_A,      FN_IRQ2_C,
+        FN_CTS1_C,      FN_SPEEDIN,     FN_VI0_CLK,     FN_CAN_CLK_A,
+        FN_VI0_CLKENB,  FN_SD2_DAT2_B,  FN_VI1_DATA0,   FN_DU1_DG6,
+        FN_HSPI_RX1_A,  FN_RX4_B,       FN_VI0_FIELD,   FN_SD2_DAT3_B,
+        FN_VI0_R3_C,    FN_VI1_DATA1,   FN_DU1_DG7,     FN_HSPI_CLK1_A,
+        FN_TX4_B,       FN_VI0_HSYNC,   FN_SD2_CD_B,    FN_VI1_DATA2,
+        FN_DU1_DR2,     FN_HSPI_CS1_A,  FN_RX3_B,
+
+        /* IPSR8 */
+        FN_VI0_VSYNC,   FN_SD2_WP_B,    FN_VI1_DATA3,   FN_DU1_DR3,
+        FN_HSPI_TX1_A,  FN_TX3_B,       FN_VI0_DATA0_VI0_B0,
+        FN_DU1_DG2,     FN_IRQ2_B,      FN_RX3_D,       FN_VI0_DATA1_VI0_B1,
+        FN_DU1_DG3,     FN_IRQ3_B,      FN_TX3_D,       FN_VI0_DATA2_VI0_B2,
+        FN_DU1_DG4,     FN_RX0_C,       FN_VI0_DATA3_VI0_B3,
+        FN_DU1_DG5,     FN_TX1_A,       FN_TX0_C,       FN_VI0_DATA4_VI0_B4,
+        FN_DU1_DB2,     FN_RX1_A,       FN_VI0_DATA5_VI0_B5,
+        FN_DU1_DB3,     FN_SCK1_A,      FN_PWM4,        FN_HSCK1_B,
+        FN_VI0_DATA6_VI0_G0,            FN_DU1_DB4,     FN_CTS1_A,
+        FN_PWM5,        FN_VI0_DATA7_VI0_G1,            FN_DU1_DB5,
+        FN_RTS1_A,      FN_VI0_G2,      FN_SD2_CLK_B,   FN_VI1_DATA4,
+        FN_DU1_DR4,     FN_HTX1_B,      FN_VI0_G3,      FN_SD2_CMD_B,
+        FN_VI1_DATA5,   FN_DU1_DR5,     FN_HRX1_B,
+
+        /* IPSR9 */
+        FN_VI0_G4,      FN_SD2_DAT0_B,  FN_VI1_DATA6,   FN_DU1_DR6,
+        FN_HRTS1_B,     FN_VI0_G5,      FN_SD2_DAT1_B,  FN_VI1_DATA7,
+        FN_DU1_DR7,     FN_HCTS1_B,     FN_VI0_R0_A,    FN_VI1_CLK,
+        FN_ETH_REF_CLK, FN_DU1_DOTCLKIN,                FN_VI0_R1_A,
+        FN_VI1_DATA8,   FN_DU1_DB6,     FN_ETH_TXD0,    FN_PWM2,
+        FN_TCLK1,       FN_VI0_R2_A,    FN_VI1_DATA9,   FN_DU1_DB7,
+        FN_ETH_TXD1,    FN_PWM3,        FN_VI0_R3_A,    FN_ETH_CRS_DV,
+        FN_IECLK,       FN_SCK2_C,      FN_VI0_R4_A,    FN_ETH_TX_EN,
+        FN_IETX,        FN_TX2_C,       FN_VI0_R5_A,    FN_ETH_RX_ER,
+        FN_FMCLK_C,     FN_IERX,        FN_RX2_C,       FN_VI1_DATA10_A,
+        FN_DU1_DOTCLKOUT,               FN_ETH_RXD0,    FN_BPFCLK_C,
+        FN_TX2_D,       FN_SDA2_C,      FN_VI1_DATA11_A,
+        FN_DU1_EXHSYNC_DU1_HSYNC,       FN_ETH_RXD1,    FN_FMIN_C,
+        FN_RX2_D,       FN_SCL2_C,
+
+        /* IPSR10 */
+        FN_SD2_CLK_A,   FN_DU1_EXVSYNC_DU1_VSYNC,       FN_ATARD1,
+        FN_ETH_MDC,     FN_SDA1_B,      FN_SD2_CMD_A,
+        FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,                FN_ATAWR1,
+        FN_ETH_MDIO,    FN_SCL1_B,      FN_SD2_DAT0_A,  FN_DU1_DISP,
+        FN_ATACS01,     FN_DREQ1_B,     FN_ETH_LINK,    FN_CAN1_RX_A,
+        FN_SD2_DAT1_A,  FN_DU1_CDE,     FN_ATACS11,     FN_DACK1_B,
+        FN_ETH_MAGIC,   FN_CAN1_TX_A,   FN_PWM6,        FN_SD2_DAT2_A,
+        FN_VI1_DATA12,  FN_DREQ2_B,     FN_ATADIR1,     FN_HSPI_CLK2_B,
+        FN_GPSCLK_B,    FN_SD2_DAT3_A,  FN_VI1_DATA13,  FN_DACK2_B,
+        FN_ATAG1,       FN_HSPI_CS2_B,  FN_GPSIN_B,     FN_SD2_CD_A,
+        FN_VI1_DATA14,  FN_EX_WAIT1_B,  FN_DREQ0_B,     FN_HSPI_RX2_B,
+        FN_REMOCON_A,   FN_SD2_WP_A,    FN_VI1_DATA15,  FN_EX_WAIT2_B,
+        FN_DACK0_B,     FN_HSPI_TX2_B,  FN_CAN_CLK_C,
+
+        /* SEL */
+        FN_SEL_SCIF5_A, FN_SEL_SCIF5_B,
+        FN_SEL_SCIF4_A, FN_SEL_SCIF4_B, FN_SEL_SCIF4_C,
+        FN_SEL_SCIF3_A, FN_SEL_SCIF3_B, FN_SEL_SCIF3_C, FN_SEL_SCIF3_D,
+        FN_SEL_SCIF2_A, FN_SEL_SCIF2_B, FN_SEL_SCIF2_C, FN_SEL_SCIF2_D, FN_SEL_SCIF2_E,
+        FN_SEL_SCIF1_A, FN_SEL_SCIF1_B, FN_SEL_SCIF1_C, FN_SEL_SCIF1_D,
+        FN_SEL_SCIF0_A, FN_SEL_SCIF0_B, FN_SEL_SCIF0_C, FN_SEL_SCIF0_D,
+        FN_SEL_SSI2_A,  FN_SEL_SSI2_B,
+        FN_SEL_SSI1_A,  FN_SEL_SSI1_B,
+        FN_SEL_VI1_A,   FN_SEL_VI1_B,
+        FN_SEL_VI0_A,   FN_SEL_VI0_B,   FN_SEL_VI0_C,   FN_SEL_VI0_D,
+        FN_SEL_SD2_A,   FN_SEL_SD2_B,
+        FN_SEL_SD1_A,   FN_SEL_SD1_B,
+        FN_SEL_IRQ3_A,  FN_SEL_IRQ3_B,
+        FN_SEL_IRQ2_A,  FN_SEL_IRQ2_B,  FN_SEL_IRQ2_C,
+        FN_SEL_IRQ1_A,  FN_SEL_IRQ1_B,
+        FN_SEL_DREQ2_A, FN_SEL_DREQ2_B,
+        FN_SEL_DREQ1_A, FN_SEL_DREQ1_B,
+        FN_SEL_DREQ0_A, FN_SEL_DREQ0_B,
+        FN_SEL_WAIT2_A, FN_SEL_WAIT2_B,
+        FN_SEL_WAIT1_A, FN_SEL_WAIT1_B,
+        FN_SEL_CAN1_A,  FN_SEL_CAN1_B,
+        FN_SEL_CAN0_A,  FN_SEL_CAN0_B,
+        FN_SEL_CANCLK_A,        FN_SEL_CANCLK_B,
+        FN_SEL_CANCLK_C,        FN_SEL_CANCLK_D,
+        FN_SEL_HSCIF1_A,        FN_SEL_HSCIF1_B,
+        FN_SEL_HSCIF0_A,        FN_SEL_HSCIF0_B,
+        FN_SEL_REMOCON_A,       FN_SEL_REMOCON_B,       FN_SEL_REMOCON_C,
+        FN_SEL_FM_A,    FN_SEL_FM_B,    FN_SEL_FM_C,    FN_SEL_FM_D,
+        FN_SEL_GPS_A,   FN_SEL_GPS_B,   FN_SEL_GPS_C,
+        FN_SEL_TSIF0_A, FN_SEL_TSIF0_B,
+        FN_SEL_HSPI2_A, FN_SEL_HSPI2_B,
+        FN_SEL_HSPI1_A, FN_SEL_HSPI1_B,
+        FN_SEL_HSPI0_A, FN_SEL_HSPI0_B,
+        FN_SEL_I2C3_A,  FN_SEL_I2C3_B,  FN_SEL_I2C3_C,
+        FN_SEL_I2C2_A,  FN_SEL_I2C2_B,  FN_SEL_I2C2_C,
+        FN_SEL_I2C1_A,  FN_SEL_I2C1_B,
+        PINMUX_FUNCTION_END,
+
+        PINMUX_MARK_BEGIN,
+
+        /* GPSR0 */
+        PENC0_MARK,     PENC1_MARK,     A1_MARK,        A2_MARK,        A3_MARK,
+
+        /* GPSR1 */
+        WE0_MARK,
+
+        /* GPSR2 */
+        AUDIO_CLKA_MARK,
+        AUDIO_CLKB_MARK,
+
+        /* GPSR3 */
+        SSI_SCK34_MARK,
+
+        /* GPSR4 */
+        AVS1_MARK,
+        AVS2_MARK,
+
+        VI0_R0_C_MARK,          /* see sel_vi0 */
+        VI0_R1_C_MARK,          /* see sel_vi0 */
+        VI0_R2_C_MARK,          /* see sel_vi0 */
+        /* VI0_R3_C_MARK, */
+        VI0_R4_C_MARK,          /* see sel_vi0 */
+        VI0_R5_C_MARK,          /* see sel_vi0 */
+
+        VI0_R0_D_MARK,          /* see sel_vi0 */
+        VI0_R1_D_MARK,          /* see sel_vi0 */
+        VI0_R2_D_MARK,          /* see sel_vi0 */
+        VI0_R3_D_MARK,          /* see sel_vi0 */
+        VI0_R4_D_MARK,          /* see sel_vi0 */
+        VI0_R5_D_MARK,          /* see sel_vi0 */
+
+        /* IPSR0 */
+        PRESETOUT_MARK, PWM1_MARK,      AUDATA0_MARK,
+        ARM_TRACEDATA_0_MARK,           GPSCLK_C_MARK,  USB_OVC0_MARK,
+        TX2_E_MARK,     SDA2_B_MARK,    AUDATA1_MARK,   ARM_TRACEDATA_1_MARK,
+        GPSIN_C_MARK,   USB_OVC1_MARK,  RX2_E_MARK,     SCL2_B_MARK,
+        SD1_DAT2_A_MARK,                MMC_D2_MARK,    BS_MARK,
+        ATADIR0_A_MARK, SDSELF_A_MARK,  PWM4_B_MARK,    SD1_DAT3_A_MARK,
+        MMC_D3_MARK,    A0_MARK,        ATAG0_A_MARK,   REMOCON_B_MARK,
+        A4_MARK,        A5_MARK,        A6_MARK,        A7_MARK,
+        A8_MARK,        A9_MARK,        A10_MARK,       A11_MARK,
+        A12_MARK,       A13_MARK,       A14_MARK,       A15_MARK,
+        A16_MARK,       A17_MARK,       A18_MARK,       A19_MARK,
+
+        /* IPSR1 */
+        A20_MARK,       HSPI_CS1_B_MARK,                A21_MARK,
+        HSPI_CLK1_B_MARK,               A22_MARK,       HRTS0_B_MARK,
+        RX2_B_MARK,     DREQ2_A_MARK,   A23_MARK,       HTX0_B_MARK,
+        TX2_B_MARK,     DACK2_A_MARK,   TS_SDEN0_A_MARK,
+        SD1_CD_A_MARK,  MMC_D6_MARK,    A24_MARK,       DREQ1_A_MARK,
+        HRX0_B_MARK,    TS_SPSYNC0_A_MARK,              SD1_WP_A_MARK,
+        MMC_D7_MARK,    A25_MARK,       DACK1_A_MARK,   HCTS0_B_MARK,
+        RX3_C_MARK,     TS_SDAT0_A_MARK,                CLKOUT_MARK,
+        HSPI_TX1_B_MARK,                PWM0_B_MARK,    CS0_MARK,
+        HSPI_RX1_B_MARK,                SSI_SCK1_B_MARK,
+        ATAG0_B_MARK,   CS1_A26_MARK,   SDA2_A_MARK,    SCK2_B_MARK,
+        MMC_D5_MARK,    ATADIR0_B_MARK, RD_WR_MARK,     WE1_MARK,
+        ATAWR0_B_MARK,  SSI_WS1_B_MARK, EX_CS0_MARK,    SCL2_A_MARK,
+        TX3_C_MARK,     TS_SCK0_A_MARK, EX_CS1_MARK,    MMC_D4_MARK,
+
+        /* IPSR2 */
+        SD1_CLK_A_MARK, MMC_CLK_MARK,   ATACS00_MARK,   EX_CS2_MARK,
+        SD1_CMD_A_MARK, MMC_CMD_MARK,   ATACS10_MARK,   EX_CS3_MARK,
+        SD1_DAT0_A_MARK,                MMC_D0_MARK,    ATARD0_MARK,
+        EX_CS4_MARK,    EX_WAIT1_A_MARK,                SD1_DAT1_A_MARK,
+        MMC_D1_MARK,    ATAWR0_A_MARK,  EX_CS5_MARK,    EX_WAIT2_A_MARK,
+        DREQ0_A_MARK,   RX3_A_MARK,     DACK0_MARK,     TX3_A_MARK,
+        DRACK0_MARK,    EX_WAIT0_MARK,  PWM0_C_MARK,    D0_MARK,
+        D1_MARK,        D2_MARK,        D3_MARK,        D4_MARK,
+        D5_MARK,        D6_MARK,        D7_MARK,        D8_MARK,
+        D9_MARK,        D10_MARK,       D11_MARK,       RD_WR_B_MARK,
+        IRQ0_MARK,      MLB_CLK_MARK,   IRQ1_A_MARK,
+
+        /* IPSR3 */
+        MLB_SIG_MARK,   RX5_B_MARK,     SDA3_A_MARK,    IRQ2_A_MARK,
+        MLB_DAT_MARK,   TX5_B_MARK,     SCL3_A_MARK,    IRQ3_A_MARK,
+        SDSELF_B_MARK,  SD1_CMD_B_MARK, SCIF_CLK_MARK,  AUDIO_CLKOUT_B_MARK,
+        CAN_CLK_B_MARK, SDA3_B_MARK,    SD1_CLK_B_MARK, HTX0_A_MARK,
+        TX0_A_MARK,     SD1_DAT0_B_MARK,                HRX0_A_MARK,
+        RX0_A_MARK,     SD1_DAT1_B_MARK,                HSCK0_MARK,
+        SCK0_MARK,      SCL3_B_MARK,    SD1_DAT2_B_MARK,
+        HCTS0_A_MARK,   CTS0_MARK,      SD1_DAT3_B_MARK,
+        HRTS0_A_MARK,   RTS0_MARK,      SSI_SCK4_MARK,
+        DU0_DR0_MARK,   LCDOUT0_MARK,   AUDATA2_MARK,   ARM_TRACEDATA_2_MARK,
+        SDA3_C_MARK,    ADICHS1_MARK,   TS_SDEN0_B_MARK,
+        SSI_WS4_MARK,   DU0_DR1_MARK,   LCDOUT1_MARK,   AUDATA3_MARK,
+        ARM_TRACEDATA_3_MARK,           SCL3_C_MARK,    ADICHS2_MARK,
+        TS_SPSYNC0_B_MARK,              DU0_DR2_MARK,   LCDOUT2_MARK,
+        DU0_DR3_MARK,   LCDOUT3_MARK,   DU0_DR4_MARK,   LCDOUT4_MARK,
+        DU0_DR5_MARK,   LCDOUT5_MARK,   DU0_DR6_MARK,   LCDOUT6_MARK,
+
+        /* IPSR4 */
+        DU0_DR7_MARK,   LCDOUT7_MARK,   DU0_DG0_MARK,   LCDOUT8_MARK,
+        AUDATA4_MARK,   ARM_TRACEDATA_4_MARK,
+        TX1_D_MARK,     CAN0_TX_A_MARK, ADICHS0_MARK,   DU0_DG1_MARK,
+        LCDOUT9_MARK,   AUDATA5_MARK,   ARM_TRACEDATA_5_MARK,
+        RX1_D_MARK,     CAN0_RX_A_MARK, ADIDATA_MARK,   DU0_DG2_MARK,
+        LCDOUT10_MARK,  DU0_DG3_MARK,   LCDOUT11_MARK,  DU0_DG4_MARK,
+        LCDOUT12_MARK,  RX0_B_MARK,     DU0_DG5_MARK,   LCDOUT13_MARK,
+        TX0_B_MARK,     DU0_DG6_MARK,   LCDOUT14_MARK,  RX4_A_MARK,
+        DU0_DG7_MARK,   LCDOUT15_MARK,  TX4_A_MARK,     SSI_SCK2_B_MARK,
+        VI0_R0_B_MARK,  DU0_DB0_MARK,   LCDOUT16_MARK,  AUDATA6_MARK,
+        ARM_TRACEDATA_6_MARK,           GPSCLK_A_MARK,  PWM0_A_MARK,
+        ADICLK_MARK,    TS_SDAT0_B_MARK,                AUDIO_CLKC_MARK,
+        VI0_R1_B_MARK,  DU0_DB1_MARK,   LCDOUT17_MARK,  AUDATA7_MARK,
+        ARM_TRACEDATA_7_MARK,           GPSIN_A_MARK,   ADICS_SAMP_MARK,
+        TS_SCK0_B_MARK, VI0_R2_B_MARK,  DU0_DB2_MARK,   LCDOUT18_MARK,
+        VI0_R3_B_MARK,  DU0_DB3_MARK,   LCDOUT19_MARK,  VI0_R4_B_MARK,
+        DU0_DB4_MARK,   LCDOUT20_MARK,
+
+        /* IPSR5 */
+        VI0_R5_B_MARK,  DU0_DB5_MARK,   LCDOUT21_MARK,  VI1_DATA10_B_MARK,
+        DU0_DB6_MARK,   LCDOUT22_MARK,  VI1_DATA11_B_MARK,
+        DU0_DB7_MARK,   LCDOUT23_MARK,  DU0_DOTCLKIN_MARK,
+        QSTVA_QVS_MARK, DU0_DOTCLKO_UT0_MARK,
+        QCLK_MARK,      DU0_DOTCLKO_UT1_MARK,           QSTVB_QVE_MARK,
+        AUDIO_CLKOUT_A_MARK,            REMOCON_C_MARK, SSI_WS2_B_MARK,
+        DU0_EXHSYNC_DU0_HSYNC_MARK,     QSTH_QHS_MARK,
+        DU0_EXVSYNC_DU0_VSYNC_MARK,     QSTB_QHE_MARK,
+        DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK,
+        QCPV_QDE_MARK,  FMCLK_D_MARK,   SSI_SCK1_A_MARK,
+        DU0_DISP_MARK,  QPOLA_MARK,     AUDCK_MARK,     ARM_TRACECLK_MARK,
+        BPFCLK_D_MARK,  SSI_WS1_A_MARK, DU0_CDE_MARK,   QPOLB_MARK,
+        AUDSYNC_MARK,   ARM_TRACECTL_MARK,              FMIN_D_MARK,
+        SD1_CD_B_MARK,  SSI_SCK78_MARK, HSPI_RX0_B_MARK,
+        TX1_B_MARK,     SD1_WP_B_MARK,  SSI_WS78_MARK,  HSPI_CLK0_B_MARK,
+        RX1_B_MARK,     CAN_CLK_D_MARK, SSI_SDATA8_MARK,
+        SSI_SCK2_A_MARK,                HSPI_CS0_B_MARK,
+        TX2_A_MARK,     CAN0_TX_B_MARK, SSI_SDATA7_MARK,
+        HSPI_TX0_B_MARK,                RX2_A_MARK,     CAN0_RX_B_MARK,
+
+        /* IPSR6 */
+        SSI_SCK6_MARK,  HSPI_RX2_A_MARK,                FMCLK_B_MARK,
+        CAN1_TX_B_MARK, SSI_WS6_MARK,   HSPI_CLK2_A_MARK,
+        BPFCLK_B_MARK,  CAN1_RX_B_MARK, SSI_SDATA6_MARK,
+        HSPI_TX2_A_MARK,                FMIN_B_MARK,    SSI_SCK5_MARK,
+        RX4_C_MARK,     SSI_WS5_MARK,   TX4_C_MARK,     SSI_SDATA5_MARK,
+        RX0_D_MARK,     SSI_WS34_MARK,  ARM_TRACEDATA_8_MARK,
+        SSI_SDATA4_MARK,                SSI_WS2_A_MARK, ARM_TRACEDATA_9_MARK,
+        SSI_SDATA3_MARK,                ARM_TRACEDATA_10_MARK,
+        SSI_SCK012_MARK,                ARM_TRACEDATA_11_MARK,
+        TX0_D_MARK,     SSI_WS012_MARK, ARM_TRACEDATA_12_MARK,
+        SSI_SDATA2_MARK,                HSPI_CS2_A_MARK,
+        ARM_TRACEDATA_13_MARK,          SDA1_A_MARK,    SSI_SDATA1_MARK,
+        ARM_TRACEDATA_14_MARK,          SCL1_A_MARK,    SCK2_A_MARK,
+        SSI_SDATA0_MARK,                ARM_TRACEDATA_15_MARK,
+        SD0_CLK_MARK,   SUB_TDO_MARK,   SD0_CMD_MARK,   SUB_TRST_MARK,
+        SD0_DAT0_MARK,  SUB_TMS_MARK,   SD0_DAT1_MARK,  SUB_TCK_MARK,
+        SD0_DAT2_MARK,  SUB_TDI_MARK,
+
+        /* IPSR7 */
+        SD0_DAT3_MARK,  IRQ1_B_MARK,    SD0_CD_MARK,    TX5_A_MARK,
+        SD0_WP_MARK,    RX5_A_MARK,     VI1_CLKENB_MARK,
+        HSPI_CLK0_A_MARK,       HTX1_A_MARK,    RTS1_C_MARK,    VI1_FIELD_MARK,
+        HSPI_CS0_A_MARK,        HRX1_A_MARK,    SCK1_C_MARK,    VI1_HSYNC_MARK,
+        HSPI_RX0_A_MARK,        HRTS1_A_MARK,   FMCLK_A_MARK,   RX1_C_MARK,
+        VI1_VSYNC_MARK, HSPI_TX0_MARK,  HCTS1_A_MARK,   BPFCLK_A_MARK,
+        TX1_C_MARK,     TCLK0_MARK,     HSCK1_A_MARK,   FMIN_A_MARK,
+        IRQ2_C_MARK,    CTS1_C_MARK,    SPEEDIN_MARK,   VI0_CLK_MARK,
+        CAN_CLK_A_MARK, VI0_CLKENB_MARK,                SD2_DAT2_B_MARK,
+        VI1_DATA0_MARK, DU1_DG6_MARK,   HSPI_RX1_A_MARK,
+        RX4_B_MARK,     VI0_FIELD_MARK, SD2_DAT3_B_MARK,
+        VI0_R3_C_MARK,  VI1_DATA1_MARK, DU1_DG7_MARK,   HSPI_CLK1_A_MARK,
+        TX4_B_MARK,     VI0_HSYNC_MARK, SD2_CD_B_MARK,  VI1_DATA2_MARK,
+        DU1_DR2_MARK,   HSPI_CS1_A_MARK,                RX3_B_MARK,
+
+        /* IPSR8 */
+        VI0_VSYNC_MARK, SD2_WP_B_MARK,  VI1_DATA3_MARK, DU1_DR3_MARK,
+        HSPI_TX1_A_MARK,                TX3_B_MARK,     VI0_DATA0_VI0_B0_MARK,
+        DU1_DG2_MARK,   IRQ2_B_MARK,    RX3_D_MARK,     VI0_DATA1_VI0_B1_MARK,
+        DU1_DG3_MARK,   IRQ3_B_MARK,    TX3_D_MARK,     VI0_DATA2_VI0_B2_MARK,
+        DU1_DG4_MARK,   RX0_C_MARK,     VI0_DATA3_VI0_B3_MARK,
+        DU1_DG5_MARK,   TX1_A_MARK,     TX0_C_MARK,     VI0_DATA4_VI0_B4_MARK,
+        DU1_DB2_MARK,   RX1_A_MARK,     VI0_DATA5_VI0_B5_MARK,
+        DU1_DB3_MARK,   SCK1_A_MARK,    PWM4_MARK,      HSCK1_B_MARK,
+        VI0_DATA6_VI0_G0_MARK,          DU1_DB4_MARK,   CTS1_A_MARK,
+        PWM5_MARK,      VI0_DATA7_VI0_G1_MARK,          DU1_DB5_MARK,
+        RTS1_A_MARK,    VI0_G2_MARK,    SD2_CLK_B_MARK, VI1_DATA4_MARK,
+        DU1_DR4_MARK,   HTX1_B_MARK,    VI0_G3_MARK,    SD2_CMD_B_MARK,
+        VI1_DATA5_MARK, DU1_DR5_MARK,   HRX1_B_MARK,
+
+        /* IPSR9 */
+        VI0_G4_MARK,    SD2_DAT0_B_MARK,                VI1_DATA6_MARK,
+        DU1_DR6_MARK,   HRTS1_B_MARK,   VI0_G5_MARK,    SD2_DAT1_B_MARK,
+        VI1_DATA7_MARK, DU1_DR7_MARK,   HCTS1_B_MARK,   VI0_R0_A_MARK,
+        VI1_CLK_MARK,   ETH_REF_CLK_MARK,               DU1_DOTCLKIN_MARK,
+        VI0_R1_A_MARK,  VI1_DATA8_MARK, DU1_DB6_MARK,   ETH_TXD0_MARK,
+        PWM2_MARK,      TCLK1_MARK,     VI0_R2_A_MARK,  VI1_DATA9_MARK,
+        DU1_DB7_MARK,   ETH_TXD1_MARK,  PWM3_MARK,      VI0_R3_A_MARK,
+        ETH_CRS_DV_MARK,                IECLK_MARK,     SCK2_C_MARK,
+        VI0_R4_A_MARK,                  ETH_TX_EN_MARK, IETX_MARK,
+        TX2_C_MARK,     VI0_R5_A_MARK,  ETH_RX_ER_MARK, FMCLK_C_MARK,
+        IERX_MARK,      RX2_C_MARK,     VI1_DATA10_A_MARK,
+        DU1_DOTCLKOUT_MARK,             ETH_RXD0_MARK,
+        BPFCLK_C_MARK,  TX2_D_MARK,     SDA2_C_MARK,    VI1_DATA11_A_MARK,
+        DU1_EXHSYNC_DU1_HSYNC_MARK,     ETH_RXD1_MARK,  FMIN_C_MARK,
+        RX2_D_MARK,     SCL2_C_MARK,
+
+        /* IPSR10 */
+        SD2_CLK_A_MARK, DU1_EXVSYNC_DU1_VSYNC_MARK,     ATARD1_MARK,
+        ETH_MDC_MARK,   SDA1_B_MARK,    SD2_CMD_A_MARK,
+        DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,              ATAWR1_MARK,
+        ETH_MDIO_MARK,  SCL1_B_MARK,    SD2_DAT0_A_MARK,
+        DU1_DISP_MARK,  ATACS01_MARK,   DREQ1_B_MARK,   ETH_LINK_MARK,
+        CAN1_RX_A_MARK, SD2_DAT1_A_MARK,                DU1_CDE_MARK,
+        ATACS11_MARK,   DACK1_B_MARK,   ETH_MAGIC_MARK, CAN1_TX_A_MARK,
+        PWM6_MARK,      SD2_DAT2_A_MARK,                VI1_DATA12_MARK,
+        DREQ2_B_MARK,   ATADIR1_MARK,   HSPI_CLK2_B_MARK,
+        GPSCLK_B_MARK,  SD2_DAT3_A_MARK,                VI1_DATA13_MARK,
+        DACK2_B_MARK,   ATAG1_MARK,     HSPI_CS2_B_MARK,
+        GPSIN_B_MARK,   SD2_CD_A_MARK,  VI1_DATA14_MARK,
+        EX_WAIT1_B_MARK,                DREQ0_B_MARK,   HSPI_RX2_B_MARK,
+        REMOCON_A_MARK, SD2_WP_A_MARK,  VI1_DATA15_MARK,
+        EX_WAIT2_B_MARK,                DACK0_B_MARK,
+        HSPI_TX2_B_MARK,                CAN_CLK_C_MARK,
+
+        PINMUX_MARK_END,
+};
+
+static const pinmux_enum_t pinmux_data[] = {
+        PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
+
+        PINMUX_DATA(PENC0_MARK,         FN_PENC0),
+        PINMUX_DATA(PENC1_MARK,         FN_PENC1),
+        PINMUX_DATA(A1_MARK,            FN_A1),
+        PINMUX_DATA(A2_MARK,            FN_A2),
+        PINMUX_DATA(A3_MARK,            FN_A3),
+        PINMUX_DATA(WE0_MARK,           FN_WE0),
+        PINMUX_DATA(AUDIO_CLKA_MARK,    FN_AUDIO_CLKA),
+        PINMUX_DATA(AUDIO_CLKB_MARK,    FN_AUDIO_CLKB),
+        PINMUX_DATA(SSI_SCK34_MARK,     FN_SSI_SCK34),
+        PINMUX_DATA(AVS1_MARK,          FN_AVS1),
+        PINMUX_DATA(AVS2_MARK,          FN_AVS2),
+
+        /* IPSR0 */
+        PINMUX_IPSR_DATA(IP0_1_0,       PRESETOUT),
+        PINMUX_IPSR_DATA(IP0_1_0,       PWM1),
+
+        PINMUX_IPSR_DATA(IP0_4_2,       AUDATA0),
+        PINMUX_IPSR_DATA(IP0_4_2,       ARM_TRACEDATA_0),
+        PINMUX_IPSR_MSEL(IP0_4_2,       GPSCLK_C,       SEL_GPS_C),
+        PINMUX_IPSR_DATA(IP0_4_2,       USB_OVC0),
+        PINMUX_IPSR_DATA(IP0_4_2,       TX2_E),
+        PINMUX_IPSR_MSEL(IP0_4_2,       SDA2_B,         SEL_I2C2_B),
+
+        PINMUX_IPSR_DATA(IP0_7_5,       AUDATA1),
+        PINMUX_IPSR_DATA(IP0_7_5,       ARM_TRACEDATA_1),
+        PINMUX_IPSR_MSEL(IP0_7_5,       GPSIN_C,        SEL_GPS_C),
+        PINMUX_IPSR_DATA(IP0_7_5,       USB_OVC1),
+        PINMUX_IPSR_MSEL(IP0_7_5,       RX2_E,          SEL_SCIF2_E),
+        PINMUX_IPSR_MSEL(IP0_7_5,       SCL2_B,         SEL_I2C2_B),
+
+        PINMUX_IPSR_MSEL(IP0_11_8,      SD1_DAT2_A,     SEL_SD1_A),
+        PINMUX_IPSR_DATA(IP0_11_8,      MMC_D2),
+        PINMUX_IPSR_DATA(IP0_11_8,      BS),
+        PINMUX_IPSR_DATA(IP0_11_8,      ATADIR0_A),
+        PINMUX_IPSR_DATA(IP0_11_8,      SDSELF_A),
+        PINMUX_IPSR_DATA(IP0_11_8,      PWM4_B),
+
+        PINMUX_IPSR_MSEL(IP0_14_12,     SD1_DAT3_A,     SEL_SD1_A),
+        PINMUX_IPSR_DATA(IP0_14_12,     MMC_D3),
+        PINMUX_IPSR_DATA(IP0_14_12,     A0),
+        PINMUX_IPSR_DATA(IP0_14_12,     ATAG0_A),
+        PINMUX_IPSR_MSEL(IP0_14_12,     REMOCON_B,      SEL_REMOCON_B),
+
+        PINMUX_IPSR_DATA(IP0_15,        A4),
+        PINMUX_IPSR_DATA(IP0_16,        A5),
+        PINMUX_IPSR_DATA(IP0_17,        A6),
+        PINMUX_IPSR_DATA(IP0_18,        A7),
+        PINMUX_IPSR_DATA(IP0_19,        A8),
+        PINMUX_IPSR_DATA(IP0_20,        A9),
+        PINMUX_IPSR_DATA(IP0_21,        A10),
+        PINMUX_IPSR_DATA(IP0_22,        A11),
+        PINMUX_IPSR_DATA(IP0_23,        A12),
+        PINMUX_IPSR_DATA(IP0_24,        A13),
+        PINMUX_IPSR_DATA(IP0_25,        A14),
+        PINMUX_IPSR_DATA(IP0_26,        A15),
+        PINMUX_IPSR_DATA(IP0_27,        A16),
+        PINMUX_IPSR_DATA(IP0_28,        A17),
+        PINMUX_IPSR_DATA(IP0_29,        A18),
+        PINMUX_IPSR_DATA(IP0_30,        A19),
+
+        /* IPSR1 */
+        PINMUX_IPSR_DATA(IP1_0,         A20),
+        PINMUX_IPSR_MSEL(IP1_0,         HSPI_CS1_B,     SEL_HSPI1_B),
+
+        PINMUX_IPSR_DATA(IP1_1,         A21),
+        PINMUX_IPSR_MSEL(IP1_1,         HSPI_CLK1_B,    SEL_HSPI1_B),
+
+        PINMUX_IPSR_DATA(IP1_4_2,       A22),
+        PINMUX_IPSR_MSEL(IP1_4_2,       HRTS0_B,        SEL_HSCIF0_B),
+        PINMUX_IPSR_MSEL(IP1_4_2,       RX2_B,          SEL_SCIF2_B),
+        PINMUX_IPSR_MSEL(IP1_4_2,       DREQ2_A,        SEL_DREQ2_A),
+
+        PINMUX_IPSR_DATA(IP1_7_5,       A23),
+        PINMUX_IPSR_DATA(IP1_7_5,       HTX0_B),
+        PINMUX_IPSR_DATA(IP1_7_5,       TX2_B),
+        PINMUX_IPSR_DATA(IP1_7_5,       DACK2_A),
+        PINMUX_IPSR_MSEL(IP1_7_5,       TS_SDEN0_A,     SEL_TSIF0_A),
+
+        PINMUX_IPSR_MSEL(IP1_10_8,      SD1_CD_A,       SEL_SD1_A),
+        PINMUX_IPSR_DATA(IP1_10_8,      MMC_D6),
+        PINMUX_IPSR_DATA(IP1_10_8,      A24),
+        PINMUX_IPSR_MSEL(IP1_10_8,      DREQ1_A,        SEL_DREQ1_A),
+        PINMUX_IPSR_MSEL(IP1_10_8,      HRX0_B,         SEL_HSCIF0_B),
+        PINMUX_IPSR_MSEL(IP1_10_8,      TS_SPSYNC0_A,   SEL_TSIF0_A),
+
+        PINMUX_IPSR_MSEL(IP1_14_11,     SD1_WP_A,       SEL_SD1_A),
+        PINMUX_IPSR_DATA(IP1_14_11,     MMC_D7),
+        PINMUX_IPSR_DATA(IP1_14_11,     A25),
+        PINMUX_IPSR_DATA(IP1_14_11,     DACK1_A),
+        PINMUX_IPSR_MSEL(IP1_14_11,     HCTS0_B,        SEL_HSCIF0_B),
+        PINMUX_IPSR_MSEL(IP1_14_11,     RX3_C,          SEL_SCIF3_C),
+        PINMUX_IPSR_MSEL(IP1_14_11,     TS_SDAT0_A,     SEL_TSIF0_A),
+
+        PINMUX_IPSR_NOGP(IP1_16_15,     CLKOUT),
+        PINMUX_IPSR_NOGP(IP1_16_15,     HSPI_TX1_B),
+        PINMUX_IPSR_NOGP(IP1_16_15,     PWM0_B),
+
+        PINMUX_IPSR_NOGP(IP1_17,        CS0),
+        PINMUX_IPSR_NOGM(IP1_17,        HSPI_RX1_B,     SEL_HSPI1_B),
+
+        PINMUX_IPSR_NOGM(IP1_20_18,     SSI_SCK1_B,     SEL_SSI1_B),
+        PINMUX_IPSR_NOGP(IP1_20_18,     ATAG0_B),
+        PINMUX_IPSR_NOGP(IP1_20_18,     CS1_A26),
+        PINMUX_IPSR_NOGM(IP1_20_18,     SDA2_A,         SEL_I2C2_A),
+        PINMUX_IPSR_NOGM(IP1_20_18,     SCK2_B,         SEL_SCIF2_B),
+
+        PINMUX_IPSR_DATA(IP1_23_21,     MMC_D5),
+        PINMUX_IPSR_DATA(IP1_23_21,     ATADIR0_B),
+        PINMUX_IPSR_DATA(IP1_23_21,     RD_WR),
+
+        PINMUX_IPSR_DATA(IP1_24,        WE1),
+        PINMUX_IPSR_DATA(IP1_24,        ATAWR0_B),
+
+        PINMUX_IPSR_MSEL(IP1_27_25,     SSI_WS1_B,      SEL_SSI1_B),
+        PINMUX_IPSR_DATA(IP1_27_25,     EX_CS0),
+        PINMUX_IPSR_MSEL(IP1_27_25,     SCL2_A,         SEL_I2C2_A),
+        PINMUX_IPSR_DATA(IP1_27_25,     TX3_C),
+        PINMUX_IPSR_MSEL(IP1_27_25,     TS_SCK0_A,      SEL_TSIF0_A),
+
+        PINMUX_IPSR_DATA(IP1_29_28,     EX_CS1),
+        PINMUX_IPSR_DATA(IP1_29_28,     MMC_D4),
+
+        /* IPSR2 */
+        PINMUX_IPSR_DATA(IP2_2_0,       SD1_CLK_A),
+        PINMUX_IPSR_DATA(IP2_2_0,       MMC_CLK),
+        PINMUX_IPSR_DATA(IP2_2_0,       ATACS00),
+        PINMUX_IPSR_DATA(IP2_2_0,       EX_CS2),
+
+        PINMUX_IPSR_MSEL(IP2_5_3,       SD1_CMD_A,      SEL_SD1_A),
+        PINMUX_IPSR_DATA(IP2_5_3,       MMC_CMD),
+        PINMUX_IPSR_DATA(IP2_5_3,       ATACS10),
+        PINMUX_IPSR_DATA(IP2_5_3,       EX_CS3),
+
+        PINMUX_IPSR_MSEL(IP2_8_6,       SD1_DAT0_A,     SEL_SD1_A),
+        PINMUX_IPSR_DATA(IP2_8_6,       MMC_D0),
+        PINMUX_IPSR_DATA(IP2_8_6,       ATARD0),
+        PINMUX_IPSR_DATA(IP2_8_6,       EX_CS4),
+        PINMUX_IPSR_MSEL(IP2_8_6,       EX_WAIT1_A,     SEL_WAIT1_A),
+
+        PINMUX_IPSR_MSEL(IP2_11_9,      SD1_DAT1_A,     SEL_SD1_A),
+        PINMUX_IPSR_DATA(IP2_11_9,      MMC_D1),
+        PINMUX_IPSR_DATA(IP2_11_9,      ATAWR0_A),
+        PINMUX_IPSR_DATA(IP2_11_9,      EX_CS5),
+        PINMUX_IPSR_MSEL(IP2_11_9,      EX_WAIT2_A,     SEL_WAIT2_A),
+
+        PINMUX_IPSR_MSEL(IP2_13_12,     DREQ0_A,        SEL_DREQ0_A),
+        PINMUX_IPSR_MSEL(IP2_13_12,     RX3_A,          SEL_SCIF3_A),
+
+        PINMUX_IPSR_DATA(IP2_16_14,     DACK0),
+        PINMUX_IPSR_DATA(IP2_16_14,     TX3_A),
+        PINMUX_IPSR_DATA(IP2_16_14,     DRACK0),
+
+        PINMUX_IPSR_DATA(IP2_17,        EX_WAIT0),
+        PINMUX_IPSR_DATA(IP2_17,        PWM0_C),
+
+        PINMUX_IPSR_NOGP(IP2_18,        D0),
+        PINMUX_IPSR_NOGP(IP2_19,        D1),
+        PINMUX_IPSR_NOGP(IP2_20,        D2),
+        PINMUX_IPSR_NOGP(IP2_21,        D3),
+        PINMUX_IPSR_NOGP(IP2_22,        D4),
+        PINMUX_IPSR_NOGP(IP2_23,        D5),
+        PINMUX_IPSR_NOGP(IP2_24,        D6),
+        PINMUX_IPSR_NOGP(IP2_25,        D7),
+        PINMUX_IPSR_NOGP(IP2_26,        D8),
+        PINMUX_IPSR_NOGP(IP2_27,        D9),
+        PINMUX_IPSR_NOGP(IP2_28,        D10),
+        PINMUX_IPSR_NOGP(IP2_29,        D11),
+
+        PINMUX_IPSR_DATA(IP2_30,        RD_WR_B),
+        PINMUX_IPSR_DATA(IP2_30,        IRQ0),
+
+        PINMUX_IPSR_DATA(IP2_31,        MLB_CLK),
+        PINMUX_IPSR_MSEL(IP2_31,        IRQ1_A,         SEL_IRQ1_A),
+
+        /* IPSR3 */
+        PINMUX_IPSR_DATA(IP3_1_0,       MLB_SIG),
+        PINMUX_IPSR_MSEL(IP3_1_0,       RX5_B,          SEL_SCIF5_B),
+        PINMUX_IPSR_MSEL(IP3_1_0,       SDA3_A,         SEL_I2C3_A),
+        PINMUX_IPSR_MSEL(IP3_1_0,       IRQ2_A,         SEL_IRQ2_A),
+
+        PINMUX_IPSR_DATA(IP3_4_2,       MLB_DAT),
+        PINMUX_IPSR_DATA(IP3_4_2,       TX5_B),
+        PINMUX_IPSR_MSEL(IP3_4_2,       SCL3_A,         SEL_I2C3_A),
+        PINMUX_IPSR_MSEL(IP3_4_2,       IRQ3_A,         SEL_IRQ3_A),
+        PINMUX_IPSR_DATA(IP3_4_2,       SDSELF_B),
+
+        PINMUX_IPSR_MSEL(IP3_7_5,       SD1_CMD_B,      SEL_SD1_B),
+        PINMUX_IPSR_DATA(IP3_7_5,       SCIF_CLK),
+        PINMUX_IPSR_DATA(IP3_7_5,       AUDIO_CLKOUT_B),
+        PINMUX_IPSR_MSEL(IP3_7_5,       CAN_CLK_B,      SEL_CANCLK_B),
+        PINMUX_IPSR_MSEL(IP3_7_5,       SDA3_B,         SEL_I2C3_B),
+
+        PINMUX_IPSR_DATA(IP3_9_8,       SD1_CLK_B),
+        PINMUX_IPSR_DATA(IP3_9_8,       HTX0_A),
+        PINMUX_IPSR_DATA(IP3_9_8,       TX0_A),
+
+        PINMUX_IPSR_MSEL(IP3_12_10,     SD1_DAT0_B,     SEL_SD1_B),
+        PINMUX_IPSR_MSEL(IP3_12_10,     HRX0_A,         SEL_HSCIF0_A),
+        PINMUX_IPSR_MSEL(IP3_12_10,     RX0_A,          SEL_SCIF0_A),
+
+        PINMUX_IPSR_MSEL(IP3_15_13,     SD1_DAT1_B,     SEL_SD1_B),
+        PINMUX_IPSR_MSEL(IP3_15_13,     HSCK0,          SEL_HSCIF0_A),
+        PINMUX_IPSR_DATA(IP3_15_13,     SCK0),
+        PINMUX_IPSR_MSEL(IP3_15_13,     SCL3_B,         SEL_I2C3_B),
+
+        PINMUX_IPSR_MSEL(IP3_18_16,     SD1_DAT2_B,     SEL_SD1_B),
+        PINMUX_IPSR_MSEL(IP3_18_16,     HCTS0_A,        SEL_HSCIF0_A),
+        PINMUX_IPSR_DATA(IP3_18_16,     CTS0),
+
+        PINMUX_IPSR_MSEL(IP3_20_19,     SD1_DAT3_B,     SEL_SD1_B),
+        PINMUX_IPSR_MSEL(IP3_20_19,     HRTS0_A,        SEL_HSCIF0_A),
+        PINMUX_IPSR_DATA(IP3_20_19,     RTS0),
+
+        PINMUX_IPSR_DATA(IP3_23_21,     SSI_SCK4),
+        PINMUX_IPSR_DATA(IP3_23_21,     DU0_DR0),
+        PINMUX_IPSR_DATA(IP3_23_21,     LCDOUT0),
+        PINMUX_IPSR_DATA(IP3_23_21,     AUDATA2),
+        PINMUX_IPSR_DATA(IP3_23_21,     ARM_TRACEDATA_2),
+        PINMUX_IPSR_MSEL(IP3_23_21,     SDA3_C,         SEL_I2C3_C),
+        PINMUX_IPSR_DATA(IP3_23_21,     ADICHS1),
+        PINMUX_IPSR_MSEL(IP3_23_21,     TS_SDEN0_B,     SEL_TSIF0_B),
+
+        PINMUX_IPSR_DATA(IP3_26_24,     SSI_WS4),
+        PINMUX_IPSR_DATA(IP3_26_24,     DU0_DR1),
+        PINMUX_IPSR_DATA(IP3_26_24,     LCDOUT1),
+        PINMUX_IPSR_DATA(IP3_26_24,     AUDATA3),
+        PINMUX_IPSR_DATA(IP3_26_24,     ARM_TRACEDATA_3),
+        PINMUX_IPSR_MSEL(IP3_26_24,     SCL3_C,         SEL_I2C3_C),
+        PINMUX_IPSR_DATA(IP3_26_24,     ADICHS2),
+        PINMUX_IPSR_MSEL(IP3_26_24,     TS_SPSYNC0_B,   SEL_TSIF0_B),
+
+        PINMUX_IPSR_DATA(IP3_27,        DU0_DR2),
+        PINMUX_IPSR_DATA(IP3_27,        LCDOUT2),
+
+        PINMUX_IPSR_DATA(IP3_28,        DU0_DR3),
+        PINMUX_IPSR_DATA(IP3_28,        LCDOUT3),
+
+        PINMUX_IPSR_DATA(IP3_29,        DU0_DR4),
+        PINMUX_IPSR_DATA(IP3_29,        LCDOUT4),
+
+        PINMUX_IPSR_DATA(IP3_30,        DU0_DR5),
+        PINMUX_IPSR_DATA(IP3_30,        LCDOUT5),
+
+        PINMUX_IPSR_DATA(IP3_31,        DU0_DR6),
+        PINMUX_IPSR_DATA(IP3_31,        LCDOUT6),
+
+        /* IPSR4 */
+        PINMUX_IPSR_DATA(IP4_0,         DU0_DR7),
+        PINMUX_IPSR_DATA(IP4_0,         LCDOUT7),
+
+        PINMUX_IPSR_DATA(IP4_3_1,       DU0_DG0),
+        PINMUX_IPSR_DATA(IP4_3_1,       LCDOUT8),
+        PINMUX_IPSR_DATA(IP4_3_1,       AUDATA4),
+        PINMUX_IPSR_DATA(IP4_3_1,       ARM_TRACEDATA_4),
+        PINMUX_IPSR_DATA(IP4_3_1,       TX1_D),
+        PINMUX_IPSR_DATA(IP4_3_1,       CAN0_TX_A),
+        PINMUX_IPSR_DATA(IP4_3_1,       ADICHS0),
+
+        PINMUX_IPSR_DATA(IP4_6_4,       DU0_DG1),
+        PINMUX_IPSR_DATA(IP4_6_4,       LCDOUT9),
+        PINMUX_IPSR_DATA(IP4_6_4,       AUDATA5),
+        PINMUX_IPSR_DATA(IP4_6_4,       ARM_TRACEDATA_5),
+        PINMUX_IPSR_MSEL(IP4_6_4,       RX1_D,          SEL_SCIF1_D),
+        PINMUX_IPSR_MSEL(IP4_6_4,       CAN0_RX_A,      SEL_CAN0_A),
+        PINMUX_IPSR_DATA(IP4_6_4,       ADIDATA),
+
+        PINMUX_IPSR_DATA(IP4_7,         DU0_DG2),
+        PINMUX_IPSR_DATA(IP4_7,         LCDOUT10),
+
+        PINMUX_IPSR_DATA(IP4_8,         DU0_DG3),
+        PINMUX_IPSR_DATA(IP4_8,         LCDOUT11),
+
+        PINMUX_IPSR_DATA(IP4_10_9,      DU0_DG4),
+        PINMUX_IPSR_DATA(IP4_10_9,      LCDOUT12),
+        PINMUX_IPSR_MSEL(IP4_10_9,      RX0_B,          SEL_SCIF0_B),
+
+        PINMUX_IPSR_DATA(IP4_12_11,     DU0_DG5),
+        PINMUX_IPSR_DATA(IP4_12_11,     LCDOUT13),
+        PINMUX_IPSR_DATA(IP4_12_11,     TX0_B),
+
+        PINMUX_IPSR_DATA(IP4_14_13,     DU0_DG6),
+        PINMUX_IPSR_DATA(IP4_14_13,     LCDOUT14),
+        PINMUX_IPSR_MSEL(IP4_14_13,     RX4_A,          SEL_SCIF4_A),
+
+        PINMUX_IPSR_DATA(IP4_16_15,     DU0_DG7),
+        PINMUX_IPSR_DATA(IP4_16_15,     LCDOUT15),
+        PINMUX_IPSR_DATA(IP4_16_15,     TX4_A),
+
+        PINMUX_IPSR_MSEL(IP4_20_17,     SSI_SCK2_B,     SEL_SSI2_B),
+        PINMUX_DATA(VI0_R0_B_MARK,      FN_IP4_20_17,   FN_VI0_R0_B,    FN_SEL_VI0_B), /* see sel_vi0 */
+        PINMUX_DATA(VI0_R0_D_MARK,      FN_IP4_20_17,   FN_VI0_R0_B,    FN_SEL_VI0_D), /* see sel_vi0 */
+        PINMUX_IPSR_DATA(IP4_20_17,     DU0_DB0),
+        PINMUX_IPSR_DATA(IP4_20_17,     LCDOUT16),
+        PINMUX_IPSR_DATA(IP4_20_17,     AUDATA6),
+        PINMUX_IPSR_DATA(IP4_20_17,     ARM_TRACEDATA_6),
+        PINMUX_IPSR_MSEL(IP4_20_17,     GPSCLK_A,       SEL_GPS_A),
+        PINMUX_IPSR_DATA(IP4_20_17,     PWM0_A),
+        PINMUX_IPSR_DATA(IP4_20_17,     ADICLK),
+        PINMUX_IPSR_MSEL(IP4_20_17,     TS_SDAT0_B,     SEL_TSIF0_B),
+
+        PINMUX_IPSR_DATA(IP4_24_21,     AUDIO_CLKC),
+        PINMUX_DATA(VI0_R1_B_MARK,      FN_IP4_24_21,   FN_VI0_R1_B,    FN_SEL_VI0_B), /* see sel_vi0 */
+        PINMUX_DATA(VI0_R1_D_MARK,      FN_IP4_24_21,   FN_VI0_R1_B,    FN_SEL_VI0_D), /* see sel_vi0 */
+        PINMUX_IPSR_DATA(IP4_24_21,     DU0_DB1),
+        PINMUX_IPSR_DATA(IP4_24_21,     LCDOUT17),
+        PINMUX_IPSR_DATA(IP4_24_21,     AUDATA7),
+        PINMUX_IPSR_DATA(IP4_24_21,     ARM_TRACEDATA_7),
+        PINMUX_IPSR_MSEL(IP4_24_21,     GPSIN_A,        SEL_GPS_A),
+        PINMUX_IPSR_DATA(IP4_24_21,     ADICS_SAMP),
+        PINMUX_IPSR_MSEL(IP4_24_21,     TS_SCK0_B,      SEL_TSIF0_B),
+
+        PINMUX_DATA(VI0_R2_B_MARK,      FN_IP4_26_25,   FN_VI0_R2_B,    FN_SEL_VI0_B), /* see sel_vi0 */
+        PINMUX_DATA(VI0_R2_D_MARK,      FN_IP4_26_25,   FN_VI0_R2_B,    FN_SEL_VI0_D), /* see sel_vi0 */
+        PINMUX_IPSR_DATA(IP4_26_25,     DU0_DB2),
+        PINMUX_IPSR_DATA(IP4_26_25,     LCDOUT18),
+
+        PINMUX_IPSR_MSEL(IP4_28_27,     VI0_R3_B,       SEL_VI0_B),
+        PINMUX_IPSR_DATA(IP4_28_27,     DU0_DB3),
+        PINMUX_IPSR_DATA(IP4_28_27,     LCDOUT19),
+
+        PINMUX_DATA(VI0_R4_B_MARK,      FN_IP4_30_29,   FN_VI0_R4_B,    FN_SEL_VI0_B), /* see sel_vi0 */
+        PINMUX_DATA(VI0_R4_D_MARK,      FN_IP4_30_29,   FN_VI0_R4_B,    FN_SEL_VI0_D), /* see sel_vi0 */
+        PINMUX_IPSR_DATA(IP4_30_29,     DU0_DB4),
+        PINMUX_IPSR_DATA(IP4_30_29,     LCDOUT20),
+
+        /* IPSR5 */
+        PINMUX_DATA(VI0_R5_B_MARK,      FN_IP5_1_0,     FN_VI0_R5_B,    FN_SEL_VI0_B), /* see sel_vi0 */
+        PINMUX_DATA(VI0_R5_D_MARK,      FN_IP5_1_0,     FN_VI0_R5_B,    FN_SEL_VI0_D), /* see sel_vi0 */
+        PINMUX_IPSR_DATA(IP5_1_0,       DU0_DB5),
+        PINMUX_IPSR_DATA(IP5_1_0,       LCDOUT21),
+
+        PINMUX_IPSR_MSEL(IP5_3_2,       VI1_DATA10_B,   SEL_VI1_B),
+        PINMUX_IPSR_DATA(IP5_3_2,       DU0_DB6),
+        PINMUX_IPSR_DATA(IP5_3_2,       LCDOUT22),
+
+        PINMUX_IPSR_MSEL(IP5_5_4,       VI1_DATA11_B,   SEL_VI1_B),
+        PINMUX_IPSR_DATA(IP5_5_4,       DU0_DB7),
+        PINMUX_IPSR_DATA(IP5_5_4,       LCDOUT23),
+
+        PINMUX_IPSR_DATA(IP5_6,         DU0_DOTCLKIN),
+        PINMUX_IPSR_DATA(IP5_6,         QSTVA_QVS),
+
+        PINMUX_IPSR_DATA(IP5_7,         DU0_DOTCLKO_UT0),
+        PINMUX_IPSR_DATA(IP5_7,         QCLK),
+
+        PINMUX_IPSR_DATA(IP5_9_8,       DU0_DOTCLKO_UT1),
+        PINMUX_IPSR_DATA(IP5_9_8,       QSTVB_QVE),
+        PINMUX_IPSR_DATA(IP5_9_8,       AUDIO_CLKOUT_A),
+        PINMUX_IPSR_MSEL(IP5_9_8,       REMOCON_C,      SEL_REMOCON_C),
+
+        PINMUX_IPSR_MSEL(IP5_11_10,     SSI_WS2_B,      SEL_SSI2_B),
+        PINMUX_IPSR_DATA(IP5_11_10,     DU0_EXHSYNC_DU0_HSYNC),
+        PINMUX_IPSR_DATA(IP5_11_10,     QSTH_QHS),
+
+        PINMUX_IPSR_DATA(IP5_12,        DU0_EXVSYNC_DU0_VSYNC),
+        PINMUX_IPSR_DATA(IP5_12,        QSTB_QHE),
+
+        PINMUX_IPSR_DATA(IP5_14_13,     DU0_EXODDF_DU0_ODDF_DISP_CDE),
+        PINMUX_IPSR_DATA(IP5_14_13,     QCPV_QDE),
+        PINMUX_IPSR_MSEL(IP5_14_13,     FMCLK_D,        SEL_FM_D),
+
+        PINMUX_IPSR_MSEL(IP5_17_15,     SSI_SCK1_A,     SEL_SSI1_A),
+        PINMUX_IPSR_DATA(IP5_17_15,     DU0_DISP),
+        PINMUX_IPSR_DATA(IP5_17_15,     QPOLA),
+        PINMUX_IPSR_DATA(IP5_17_15,     AUDCK),
+        PINMUX_IPSR_DATA(IP5_17_15,     ARM_TRACECLK),
+        PINMUX_IPSR_DATA(IP5_17_15,     BPFCLK_D),
+
+        PINMUX_IPSR_MSEL(IP5_20_18,     SSI_WS1_A,      SEL_SSI1_A),
+        PINMUX_IPSR_DATA(IP5_20_18,     DU0_CDE),
+        PINMUX_IPSR_DATA(IP5_20_18,     QPOLB),
+        PINMUX_IPSR_DATA(IP5_20_18,     AUDSYNC),
+        PINMUX_IPSR_DATA(IP5_20_18,     ARM_TRACECTL),
+        PINMUX_IPSR_MSEL(IP5_20_18,     FMIN_D,         SEL_FM_D),
+
+        PINMUX_IPSR_MSEL(IP5_22_21,     SD1_CD_B,       SEL_SD1_B),
+        PINMUX_IPSR_DATA(IP5_22_21,     SSI_SCK78),
+        PINMUX_IPSR_MSEL(IP5_22_21,     HSPI_RX0_B,     SEL_HSPI0_B),
+        PINMUX_IPSR_DATA(IP5_22_21,     TX1_B),
+
+        PINMUX_IPSR_MSEL(IP5_25_23,     SD1_WP_B,       SEL_SD1_B),
+        PINMUX_IPSR_DATA(IP5_25_23,     SSI_WS78),
+        PINMUX_IPSR_MSEL(IP5_25_23,     HSPI_CLK0_B,    SEL_HSPI0_B),
+        PINMUX_IPSR_MSEL(IP5_25_23,     RX1_B,          SEL_SCIF1_B),
+        PINMUX_IPSR_MSEL(IP5_25_23,     CAN_CLK_D,      SEL_CANCLK_D),
+
+        PINMUX_IPSR_DATA(IP5_28_26,     SSI_SDATA8),
+        PINMUX_IPSR_MSEL(IP5_28_26,     SSI_SCK2_A,     SEL_SSI2_A),
+        PINMUX_IPSR_MSEL(IP5_28_26,     HSPI_CS0_B,     SEL_HSPI0_B),
+        PINMUX_IPSR_DATA(IP5_28_26,     TX2_A),
+        PINMUX_IPSR_DATA(IP5_28_26,     CAN0_TX_B),
+
+        PINMUX_IPSR_DATA(IP5_30_29,     SSI_SDATA7),
+        PINMUX_IPSR_DATA(IP5_30_29,     HSPI_TX0_B),
+        PINMUX_IPSR_MSEL(IP5_30_29,     RX2_A,          SEL_SCIF2_A),
+        PINMUX_IPSR_MSEL(IP5_30_29,     CAN0_RX_B,      SEL_CAN0_B),
+
+        /* IPSR6 */
+        PINMUX_IPSR_DATA(IP6_1_0,       SSI_SCK6),
+        PINMUX_IPSR_MSEL(IP6_1_0,       HSPI_RX2_A,     SEL_HSPI2_A),
+        PINMUX_IPSR_MSEL(IP6_1_0,       FMCLK_B,        SEL_FM_B),
+        PINMUX_IPSR_DATA(IP6_1_0,       CAN1_TX_B),
+
+        PINMUX_IPSR_DATA(IP6_4_2,       SSI_WS6),
+        PINMUX_IPSR_MSEL(IP6_4_2,       HSPI_CLK2_A,    SEL_HSPI2_A),
+        PINMUX_IPSR_DATA(IP6_4_2,       BPFCLK_B),
+        PINMUX_IPSR_MSEL(IP6_4_2,       CAN1_RX_B,      SEL_CAN1_B),
+
+        PINMUX_IPSR_DATA(IP6_6_5,       SSI_SDATA6),
+        PINMUX_IPSR_DATA(IP6_6_5,       HSPI_TX2_A),
+        PINMUX_IPSR_MSEL(IP6_6_5,       FMIN_B,         SEL_FM_B),
+
+        PINMUX_IPSR_DATA(IP6_7,         SSI_SCK5),
+        PINMUX_IPSR_MSEL(IP6_7,         RX4_C,          SEL_SCIF4_C),
+
+        PINMUX_IPSR_DATA(IP6_8,         SSI_WS5),
+        PINMUX_IPSR_DATA(IP6_8,         TX4_C),
+
+        PINMUX_IPSR_DATA(IP6_9,         SSI_SDATA5),
+        PINMUX_IPSR_MSEL(IP6_9,         RX0_D,          SEL_SCIF0_D),
+
+        PINMUX_IPSR_DATA(IP6_10,        SSI_WS34),
+        PINMUX_IPSR_DATA(IP6_10,        ARM_TRACEDATA_8),
+
+        PINMUX_IPSR_DATA(IP6_12_11,     SSI_SDATA4),
+        PINMUX_IPSR_MSEL(IP6_12_11,     SSI_WS2_A,      SEL_SSI2_A),
+        PINMUX_IPSR_DATA(IP6_12_11,     ARM_TRACEDATA_9),
+
+        PINMUX_IPSR_DATA(IP6_13,        SSI_SDATA3),
+        PINMUX_IPSR_DATA(IP6_13,        ARM_TRACEDATA_10),
+
+        PINMUX_IPSR_DATA(IP6_15_14,     SSI_SCK012),
+        PINMUX_IPSR_DATA(IP6_15_14,     ARM_TRACEDATA_11),
+        PINMUX_IPSR_DATA(IP6_15_14,     TX0_D),
+
+        PINMUX_IPSR_DATA(IP6_16,        SSI_WS012),
+        PINMUX_IPSR_DATA(IP6_16,        ARM_TRACEDATA_12),
+
+        PINMUX_IPSR_DATA(IP6_18_17,     SSI_SDATA2),
+        PINMUX_IPSR_MSEL(IP6_18_17,     HSPI_CS2_A,     SEL_HSPI2_A),
+        PINMUX_IPSR_DATA(IP6_18_17,     ARM_TRACEDATA_13),
+        PINMUX_IPSR_MSEL(IP6_18_17,     SDA1_A,         SEL_I2C1_A),
+
+        PINMUX_IPSR_DATA(IP6_20_19,     SSI_SDATA1),
+        PINMUX_IPSR_DATA(IP6_20_19,     ARM_TRACEDATA_14),
+        PINMUX_IPSR_MSEL(IP6_20_19,     SCL1_A,         SEL_I2C1_A),
+        PINMUX_IPSR_MSEL(IP6_20_19,     SCK2_A,         SEL_SCIF2_A),
+
+        PINMUX_IPSR_DATA(IP6_21,        SSI_SDATA0),
+        PINMUX_IPSR_DATA(IP6_21,        ARM_TRACEDATA_15),
+
+        PINMUX_IPSR_DATA(IP6_23_22,     SD0_CLK),
+        PINMUX_IPSR_DATA(IP6_23_22,     SUB_TDO),
+
+        PINMUX_IPSR_DATA(IP6_25_24,     SD0_CMD),
+        PINMUX_IPSR_DATA(IP6_25_24,     SUB_TRST),
+
+        PINMUX_IPSR_DATA(IP6_27_26,     SD0_DAT0),
+        PINMUX_IPSR_DATA(IP6_27_26,     SUB_TMS),
+
+        PINMUX_IPSR_DATA(IP6_29_28,     SD0_DAT1),
+        PINMUX_IPSR_DATA(IP6_29_28,     SUB_TCK),
+
+        PINMUX_IPSR_DATA(IP6_31_30,     SD0_DAT2),
+        PINMUX_IPSR_DATA(IP6_31_30,     SUB_TDI),
+
+        /* IPSR7 */
+        PINMUX_IPSR_DATA(IP7_1_0,       SD0_DAT3),
+        PINMUX_IPSR_MSEL(IP7_1_0,       IRQ1_B,         SEL_IRQ1_B),
+
+        PINMUX_IPSR_DATA(IP7_3_2,       SD0_CD),
+        PINMUX_IPSR_DATA(IP7_3_2,       TX5_A),
+
+        PINMUX_IPSR_DATA(IP7_5_4,       SD0_WP),
+        PINMUX_IPSR_MSEL(IP7_5_4,       RX5_A,          SEL_SCIF5_A),
+
+        PINMUX_IPSR_DATA(IP7_8_6,       VI1_CLKENB),
+        PINMUX_IPSR_MSEL(IP7_8_6,       HSPI_CLK0_A,    SEL_HSPI0_A),
+        PINMUX_IPSR_DATA(IP7_8_6,       HTX1_A),
+        PINMUX_IPSR_MSEL(IP7_8_6,       RTS1_C,         SEL_SCIF1_C),
+
+        PINMUX_IPSR_DATA(IP7_11_9,      VI1_FIELD),
+        PINMUX_IPSR_MSEL(IP7_11_9,      HSPI_CS0_A,     SEL_HSPI0_A),
+        PINMUX_IPSR_MSEL(IP7_11_9,      HRX1_A,         SEL_HSCIF1_A),
+        PINMUX_IPSR_MSEL(IP7_11_9,      SCK1_C,         SEL_SCIF1_C),
+
+        PINMUX_IPSR_DATA(IP7_14_12,     VI1_HSYNC),
+        PINMUX_IPSR_MSEL(IP7_14_12,     HSPI_RX0_A,     SEL_HSPI0_A),
+        PINMUX_IPSR_MSEL(IP7_14_12,     HRTS1_A,        SEL_HSCIF1_A),
+        PINMUX_IPSR_MSEL(IP7_14_12,     FMCLK_A,        SEL_FM_A),
+        PINMUX_IPSR_MSEL(IP7_14_12,     RX1_C,          SEL_SCIF1_C),
+
+        PINMUX_IPSR_DATA(IP7_17_15,     VI1_VSYNC),
+        PINMUX_IPSR_DATA(IP7_17_15,     HSPI_TX0),
+        PINMUX_IPSR_MSEL(IP7_17_15,     HCTS1_A,        SEL_HSCIF1_A),
+        PINMUX_IPSR_DATA(IP7_17_15,     BPFCLK_A),
+        PINMUX_IPSR_DATA(IP7_17_15,     TX1_C),
+
+        PINMUX_IPSR_DATA(IP7_20_18,     TCLK0),
+        PINMUX_IPSR_MSEL(IP7_20_18,     HSCK1_A,        SEL_HSCIF1_A),
+        PINMUX_IPSR_MSEL(IP7_20_18,     FMIN_A,         SEL_FM_A),
+        PINMUX_IPSR_MSEL(IP7_20_18,     IRQ2_C,         SEL_IRQ2_C),
+        PINMUX_IPSR_MSEL(IP7_20_18,     CTS1_C,         SEL_SCIF1_C),
+        PINMUX_IPSR_DATA(IP7_20_18,     SPEEDIN),
+
+        PINMUX_IPSR_DATA(IP7_21,        VI0_CLK),
+        PINMUX_IPSR_MSEL(IP7_21,        CAN_CLK_A,      SEL_CANCLK_A),
+
+        PINMUX_IPSR_DATA(IP7_24_22,     VI0_CLKENB),
+        PINMUX_IPSR_MSEL(IP7_24_22,     SD2_DAT2_B,     SEL_SD2_B),
+        PINMUX_IPSR_DATA(IP7_24_22,     VI1_DATA0),
+        PINMUX_IPSR_DATA(IP7_24_22,     DU1_DG6),
+        PINMUX_IPSR_MSEL(IP7_24_22,     HSPI_RX1_A,     SEL_HSPI1_A),
+        PINMUX_IPSR_MSEL(IP7_24_22,     RX4_B,          SEL_SCIF4_B),
+
+        PINMUX_IPSR_DATA(IP7_28_25,     VI0_FIELD),
+        PINMUX_IPSR_MSEL(IP7_28_25,     SD2_DAT3_B,     SEL_SD2_B),
+        PINMUX_DATA(VI0_R3_C_MARK,      FN_IP7_28_25,   FN_VI0_R3_C,    FN_SEL_VI0_C), /* see sel_vi0 */
+        PINMUX_DATA(VI0_R3_D_MARK,      FN_IP7_28_25,   FN_VI0_R3_C,    FN_SEL_VI0_D), /* see sel_vi0 */
+        PINMUX_IPSR_DATA(IP7_28_25,     VI1_DATA1),
+        PINMUX_IPSR_DATA(IP7_28_25,     DU1_DG7),
+        PINMUX_IPSR_MSEL(IP7_28_25,     HSPI_CLK1_A,    SEL_HSPI1_A),
+        PINMUX_IPSR_DATA(IP7_28_25,     TX4_B),
+
+        PINMUX_IPSR_DATA(IP7_31_29,     VI0_HSYNC),
+        PINMUX_IPSR_MSEL(IP7_31_29,     SD2_CD_B,       SEL_SD2_B),
+        PINMUX_IPSR_DATA(IP7_31_29,     VI1_DATA2),
+        PINMUX_IPSR_DATA(IP7_31_29,     DU1_DR2),
+        PINMUX_IPSR_MSEL(IP7_31_29,     HSPI_CS1_A,     SEL_HSPI1_A),
+        PINMUX_IPSR_MSEL(IP7_31_29,     RX3_B,          SEL_SCIF3_B),
+
+        /* IPSR8 */
+        PINMUX_IPSR_DATA(IP8_2_0,       VI0_VSYNC),
+        PINMUX_IPSR_MSEL(IP8_2_0,       SD2_WP_B,       SEL_SD2_B),
+        PINMUX_IPSR_DATA(IP8_2_0,       VI1_DATA3),
+        PINMUX_IPSR_DATA(IP8_2_0,       DU1_DR3),
+        PINMUX_IPSR_DATA(IP8_2_0,       HSPI_TX1_A),
+        PINMUX_IPSR_DATA(IP8_2_0,       TX3_B),
+
+        PINMUX_IPSR_DATA(IP8_5_3,       VI0_DATA0_VI0_B0),
+        PINMUX_IPSR_DATA(IP8_5_3,       DU1_DG2),
+        PINMUX_IPSR_MSEL(IP8_5_3,       IRQ2_B,         SEL_IRQ2_B),
+        PINMUX_IPSR_MSEL(IP8_5_3,       RX3_D,          SEL_SCIF3_D),
+
+        PINMUX_IPSR_DATA(IP8_8_6,       VI0_DATA1_VI0_B1),
+        PINMUX_IPSR_DATA(IP8_8_6,       DU1_DG3),
+        PINMUX_IPSR_MSEL(IP8_8_6,       IRQ3_B,         SEL_IRQ3_B),
+        PINMUX_IPSR_DATA(IP8_8_6,       TX3_D),
+
+        PINMUX_IPSR_DATA(IP8_10_9,      VI0_DATA2_VI0_B2),
+        PINMUX_IPSR_DATA(IP8_10_9,      DU1_DG4),
+        PINMUX_IPSR_MSEL(IP8_10_9,      RX0_C,          SEL_SCIF0_C),
+
+        PINMUX_IPSR_DATA(IP8_13_11,     VI0_DATA3_VI0_B3),
+        PINMUX_IPSR_DATA(IP8_13_11,     DU1_DG5),
+        PINMUX_IPSR_DATA(IP8_13_11,     TX1_A),
+        PINMUX_IPSR_DATA(IP8_13_11,     TX0_C),
+
+        PINMUX_IPSR_DATA(IP8_15_14,     VI0_DATA4_VI0_B4),
+        PINMUX_IPSR_DATA(IP8_15_14,     DU1_DB2),
+        PINMUX_IPSR_MSEL(IP8_15_14,     RX1_A,          SEL_SCIF1_A),
+
+        PINMUX_IPSR_DATA(IP8_18_16,     VI0_DATA5_VI0_B5),
+        PINMUX_IPSR_DATA(IP8_18_16,     DU1_DB3),
+        PINMUX_IPSR_MSEL(IP8_18_16,     SCK1_A,         SEL_SCIF1_A),
+        PINMUX_IPSR_DATA(IP8_18_16,     PWM4),
+        PINMUX_IPSR_MSEL(IP8_18_16,     HSCK1_B,        SEL_HSCIF1_B),
+
+        PINMUX_IPSR_DATA(IP8_21_19,     VI0_DATA6_VI0_G0),
+        PINMUX_IPSR_DATA(IP8_21_19,     DU1_DB4),
+        PINMUX_IPSR_MSEL(IP8_21_19,     CTS1_A,         SEL_SCIF1_A),
+        PINMUX_IPSR_DATA(IP8_21_19,     PWM5),
+
+        PINMUX_IPSR_DATA(IP8_23_22,     VI0_DATA7_VI0_G1),
+        PINMUX_IPSR_DATA(IP8_23_22,     DU1_DB5),
+        PINMUX_IPSR_MSEL(IP8_23_22,     RTS1_A,         SEL_SCIF1_A),
+
+        PINMUX_IPSR_DATA(IP8_26_24,     VI0_G2),
+        PINMUX_IPSR_DATA(IP8_26_24,     SD2_CLK_B),
+        PINMUX_IPSR_DATA(IP8_26_24,     VI1_DATA4),
+        PINMUX_IPSR_DATA(IP8_26_24,     DU1_DR4),
+        PINMUX_IPSR_DATA(IP8_26_24,     HTX1_B),
+
+        PINMUX_IPSR_DATA(IP8_29_27,     VI0_G3),
+        PINMUX_IPSR_MSEL(IP8_29_27,     SD2_CMD_B,      SEL_SD2_B),
+        PINMUX_IPSR_DATA(IP8_29_27,     VI1_DATA5),
+        PINMUX_IPSR_DATA(IP8_29_27,     DU1_DR5),
+        PINMUX_IPSR_MSEL(IP8_29_27,     HRX1_B,         SEL_HSCIF1_B),
+
+        /* IPSR9 */
+        PINMUX_IPSR_DATA(IP9_2_0,       VI0_G4),
+        PINMUX_IPSR_MSEL(IP9_2_0,       SD2_DAT0_B,     SEL_SD2_B),
+        PINMUX_IPSR_DATA(IP9_2_0,       VI1_DATA6),
+        PINMUX_IPSR_DATA(IP9_2_0,       DU1_DR6),
+        PINMUX_IPSR_MSEL(IP9_2_0,       HRTS1_B,        SEL_HSCIF1_B),
+
+        PINMUX_IPSR_DATA(IP9_5_3,       VI0_G5),
+        PINMUX_IPSR_MSEL(IP9_5_3,       SD2_DAT1_B,     SEL_SD2_B),
+        PINMUX_IPSR_DATA(IP9_5_3,       VI1_DATA7),
+        PINMUX_IPSR_DATA(IP9_5_3,       DU1_DR7),
+        PINMUX_IPSR_MSEL(IP9_5_3,       HCTS1_B,        SEL_HSCIF1_B),
+
+        PINMUX_DATA(VI0_R0_A_MARK,      FN_IP9_8_6,     FN_VI0_R0_A,    FN_SEL_VI0_A), /* see sel_vi0 */
+        PINMUX_DATA(VI0_R0_C_MARK,      FN_IP9_8_6,     FN_VI0_R0_A,    FN_SEL_VI0_C), /* see sel_vi0 */
+        PINMUX_IPSR_DATA(IP9_8_6,       VI1_CLK),
+        PINMUX_IPSR_DATA(IP9_8_6,       ETH_REF_CLK),
+        PINMUX_IPSR_DATA(IP9_8_6,       DU1_DOTCLKIN),
+
+        PINMUX_DATA(VI0_R1_A_MARK,      FN_IP9_11_9,    FN_VI0_R1_A,    FN_SEL_VI0_A), /* see sel_vi0 */
+        PINMUX_DATA(VI0_R1_C_MARK,      FN_IP9_11_9,    FN_VI0_R1_A,    FN_SEL_VI0_C), /* see sel_vi0 */
+        PINMUX_IPSR_DATA(IP9_11_9,      VI1_DATA8),
+        PINMUX_IPSR_DATA(IP9_11_9,      DU1_DB6),
+        PINMUX_IPSR_DATA(IP9_11_9,      ETH_TXD0),
+        PINMUX_IPSR_DATA(IP9_11_9,      PWM2),
+        PINMUX_IPSR_DATA(IP9_11_9,      TCLK1),
+
+        PINMUX_DATA(VI0_R2_A_MARK,      FN_IP9_14_12,   FN_VI0_R2_A,    FN_SEL_VI0_A), /* see sel_vi0 */
+        PINMUX_DATA(VI0_R2_C_MARK,      FN_IP9_14_12,   FN_VI0_R2_A,    FN_SEL_VI0_C), /* see sel_vi0 */
+        PINMUX_IPSR_DATA(IP9_14_12,     VI1_DATA9),
+        PINMUX_IPSR_DATA(IP9_14_12,     DU1_DB7),
+        PINMUX_IPSR_DATA(IP9_14_12,     ETH_TXD1),
+        PINMUX_IPSR_DATA(IP9_14_12,     PWM3),
+
+        PINMUX_IPSR_MSEL(IP9_17_15,     VI0_R3_A,       SEL_VI0_A),
+        PINMUX_IPSR_DATA(IP9_17_15,     ETH_CRS_DV),
+        PINMUX_IPSR_DATA(IP9_17_15,     IECLK),
+        PINMUX_IPSR_MSEL(IP9_17_15,     SCK2_C,         SEL_SCIF2_C),
+
+        PINMUX_DATA(VI0_R4_A_MARK,      FN_IP9_20_18,   FN_VI0_R4_A,    FN_SEL_VI0_A), /* see sel_vi0 */
+        PINMUX_DATA(VI0_R3_C_MARK,      FN_IP9_20_18,   FN_VI0_R4_A,    FN_SEL_VI0_C), /* see sel_vi0 */
+        PINMUX_IPSR_DATA(IP9_20_18,     ETH_TX_EN),
+        PINMUX_IPSR_DATA(IP9_20_18,     IETX),
+        PINMUX_IPSR_DATA(IP9_20_18,     TX2_C),
+
+        PINMUX_DATA(VI0_R5_A_MARK,      FN_IP9_23_21,   FN_VI0_R5_A,    FN_SEL_VI0_A), /* see sel_vi0 */
+        PINMUX_DATA(VI0_R5_C_MARK,      FN_IP9_23_21,   FN_VI0_R5_A,    FN_SEL_VI0_C), /* see sel_vi0 */
+        PINMUX_IPSR_DATA(IP9_23_21,     ETH_RX_ER),
+        PINMUX_IPSR_MSEL(IP9_23_21,     FMCLK_C,        SEL_FM_C),
+        PINMUX_IPSR_DATA(IP9_23_21,     IERX),
+        PINMUX_IPSR_MSEL(IP9_23_21,     RX2_C,          SEL_SCIF2_C),
+
+        PINMUX_IPSR_MSEL(IP9_26_24,     VI1_DATA10_A,   SEL_VI1_A),
+        PINMUX_IPSR_DATA(IP9_26_24,     DU1_DOTCLKOUT),
+        PINMUX_IPSR_DATA(IP9_26_24,     ETH_RXD0),
+        PINMUX_IPSR_DATA(IP9_26_24,     BPFCLK_C),
+        PINMUX_IPSR_DATA(IP9_26_24,     TX2_D),
+        PINMUX_IPSR_MSEL(IP9_26_24,     SDA2_C,         SEL_I2C2_C),
+
+        PINMUX_IPSR_MSEL(IP9_29_27,     VI1_DATA11_A,   SEL_VI1_A),
+        PINMUX_IPSR_DATA(IP9_29_27,     DU1_EXHSYNC_DU1_HSYNC),
+        PINMUX_IPSR_DATA(IP9_29_27,     ETH_RXD1),
+        PINMUX_IPSR_MSEL(IP9_29_27,     FMIN_C,         SEL_FM_C),
+        PINMUX_IPSR_MSEL(IP9_29_27,     RX2_D,          SEL_SCIF2_D),
+        PINMUX_IPSR_MSEL(IP9_29_27,     SCL2_C,         SEL_I2C2_C),
+
+        /* IPSR10 */
+        PINMUX_IPSR_DATA(IP10_2_0,      SD2_CLK_A),
+        PINMUX_IPSR_DATA(IP10_2_0,      DU1_EXVSYNC_DU1_VSYNC),
+        PINMUX_IPSR_DATA(IP10_2_0,      ATARD1),
+        PINMUX_IPSR_DATA(IP10_2_0,      ETH_MDC),
+        PINMUX_IPSR_MSEL(IP10_2_0,      SDA1_B,         SEL_I2C1_B),
+
+        PINMUX_IPSR_MSEL(IP10_5_3,      SD2_CMD_A,      SEL_SD2_A),
+        PINMUX_IPSR_DATA(IP10_5_3,      DU1_EXODDF_DU1_ODDF_DISP_CDE),
+        PINMUX_IPSR_DATA(IP10_5_3,      ATAWR1),
+        PINMUX_IPSR_DATA(IP10_5_3,      ETH_MDIO),
+        PINMUX_IPSR_MSEL(IP10_5_3,      SCL1_B,         SEL_I2C1_B),
+
+        PINMUX_IPSR_MSEL(IP10_8_6,      SD2_DAT0_A,     SEL_SD2_A),
+        PINMUX_IPSR_DATA(IP10_8_6,      DU1_DISP),
+        PINMUX_IPSR_DATA(IP10_8_6,      ATACS01),
+        PINMUX_IPSR_MSEL(IP10_8_6,      DREQ1_B,        SEL_DREQ1_B),
+        PINMUX_IPSR_DATA(IP10_8_6,      ETH_LINK),
+        PINMUX_IPSR_MSEL(IP10_8_6,      CAN1_RX_A,      SEL_CAN1_A),
+
+        PINMUX_IPSR_MSEL(IP10_12_9,     SD2_DAT1_A,     SEL_SD2_A),
+        PINMUX_IPSR_DATA(IP10_12_9,     DU1_CDE),
+        PINMUX_IPSR_DATA(IP10_12_9,     ATACS11),
+        PINMUX_IPSR_DATA(IP10_12_9,     DACK1_B),
+        PINMUX_IPSR_DATA(IP10_12_9,     ETH_MAGIC),
+        PINMUX_IPSR_DATA(IP10_12_9,     CAN1_TX_A),
+        PINMUX_IPSR_DATA(IP10_12_9,     PWM6),
+
+        PINMUX_IPSR_MSEL(IP10_15_13,    SD2_DAT2_A,     SEL_SD2_A),
+        PINMUX_IPSR_DATA(IP10_15_13,    VI1_DATA12),
+        PINMUX_IPSR_MSEL(IP10_15_13,    DREQ2_B,        SEL_DREQ2_B),
+        PINMUX_IPSR_DATA(IP10_15_13,    ATADIR1),
+        PINMUX_IPSR_MSEL(IP10_15_13,    HSPI_CLK2_B,    SEL_HSPI2_B),
+        PINMUX_IPSR_MSEL(IP10_15_13,    GPSCLK_B,       SEL_GPS_B),
+
+        PINMUX_IPSR_MSEL(IP10_18_16,    SD2_DAT3_A,     SEL_SD2_A),
+        PINMUX_IPSR_DATA(IP10_18_16,    VI1_DATA13),
+        PINMUX_IPSR_DATA(IP10_18_16,    DACK2_B),
+        PINMUX_IPSR_DATA(IP10_18_16,    ATAG1),
+        PINMUX_IPSR_MSEL(IP10_18_16,    HSPI_CS2_B,     SEL_HSPI2_B),
+        PINMUX_IPSR_MSEL(IP10_18_16,    GPSIN_B,        SEL_GPS_B),
+
+        PINMUX_IPSR_MSEL(IP10_21_19,    SD2_CD_A,       SEL_SD2_A),
+        PINMUX_IPSR_DATA(IP10_21_19,    VI1_DATA14),
+        PINMUX_IPSR_MSEL(IP10_21_19,    EX_WAIT1_B,     SEL_WAIT1_B),
+        PINMUX_IPSR_MSEL(IP10_21_19,    DREQ0_B,        SEL_DREQ0_B),
+        PINMUX_IPSR_MSEL(IP10_21_19,    HSPI_RX2_B,     SEL_HSPI2_B),
+        PINMUX_IPSR_MSEL(IP10_21_19,    REMOCON_A,      SEL_REMOCON_A),
+
+        PINMUX_IPSR_MSEL(IP10_24_22,    SD2_WP_A,       SEL_SD2_A),
+        PINMUX_IPSR_DATA(IP10_24_22,    VI1_DATA15),
+        PINMUX_IPSR_MSEL(IP10_24_22,    EX_WAIT2_B,     SEL_WAIT2_B),
+        PINMUX_IPSR_DATA(IP10_24_22,    DACK0_B),
+        PINMUX_IPSR_DATA(IP10_24_22,    HSPI_TX2_B),
+        PINMUX_IPSR_MSEL(IP10_24_22,    CAN_CLK_C,      SEL_CANCLK_C),
+};
+
+static struct sh_pfc_pin pinmux_pins[] = {
+        PINMUX_GPIO_GP_ALL(),
+};
+
+/* Pin numbers for pins without a corresponding GPIO port number are computed
+ * from the row and column numbers with a 1000 offset to avoid collisions with
+ * GPIO port numbers.
+ */
+#define PIN_NUMBER(row, col)            (1000+((row)-1)*25+(col)-1)
+
+/* - macro */
+#define SH_PFC_PINS(name, args...) \
+        static const unsigned int name ##_pins[] = { args }
+#define SH_PFC_MUX1(name, arg1)                                 \
+        static const unsigned int name ##_mux[]  = { arg1##_MARK }
+#define SH_PFC_MUX2(name, arg1, arg2)                                   \
+        static const unsigned int name ##_mux[]  = { arg1##_MARK, arg2##_MARK, }
+#define SH_PFC_MUX3(name, arg1, arg2, arg3)                                     \
+        static const unsigned int name ##_mux[]  = { arg1##_MARK, arg2##_MARK,  \
+                                                     arg3##_MARK }
+#define SH_PFC_MUX4(name, arg1, arg2, arg3, arg4)                       \
+        static const unsigned int name ##_mux[]  = { arg1##_MARK, arg2##_MARK, \
+                                                     arg3##_MARK, arg4##_MARK }
+#define SH_PFC_MUX8(name, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8) \
+        static const unsigned int name ##_mux[]  = { arg1##_MARK, arg2##_MARK, \
+                                                     arg3##_MARK, arg4##_MARK, \
+                                                     arg5##_MARK, arg6##_MARK, \
+                                                     arg7##_MARK, arg8##_MARK, }
+
+/* - Ether ------------------------------------------------------------------ */
+SH_PFC_PINS(ether_rmii,         RCAR_GP_PIN(4, 10),     RCAR_GP_PIN(4, 11),
+                                RCAR_GP_PIN(4, 13),     RCAR_GP_PIN(4, 9),
+                                RCAR_GP_PIN(4, 15),     RCAR_GP_PIN(4, 16),
+                                RCAR_GP_PIN(4, 12),     RCAR_GP_PIN(4, 14),
+                                RCAR_GP_PIN(4, 18),     RCAR_GP_PIN(4, 17));
+static const unsigned int ether_rmii_mux[] = {
+        ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK,  ETH_REF_CLK_MARK,
+        ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_CRS_DV_MARK, ETH_RX_ER_MARK,
+        ETH_MDIO_MARK, ETH_MDC_MARK,
+};
+SH_PFC_PINS(ether_link,         RCAR_GP_PIN(4, 19));
+SH_PFC_MUX1(ether_link,         ETH_LINK);
+SH_PFC_PINS(ether_magic,        RCAR_GP_PIN(4, 20));
+SH_PFC_MUX1(ether_magic,        ETH_MAGIC);
+
+/* - SCIF macro ------------------------------------------------------------- */
+#define SCIF_PFC_PIN(name, args...)     SH_PFC_PINS(name, args)
+#define SCIF_PFC_DAT(name, tx, rx)      SH_PFC_MUX2(name, tx, rx)
+#define SCIF_PFC_CTR(name, cts, rts)    SH_PFC_MUX2(name, cts, rts)
+#define SCIF_PFC_CLK(name, sck)         SH_PFC_MUX1(name, sck)
+
+/* - HSCIF0 ----------------------------------------------------------------- */
+SCIF_PFC_PIN(hscif0_data_a,     RCAR_GP_PIN(1, 17),     RCAR_GP_PIN(1, 18));
+SCIF_PFC_DAT(hscif0_data_a,     HTX0_A,                 HRX0_A);
+SCIF_PFC_PIN(hscif0_data_b,     RCAR_GP_PIN(0, 29),     RCAR_GP_PIN(0, 30));
+SCIF_PFC_DAT(hscif0_data_b,     HTX0_B,                 HRX0_B);
+SCIF_PFC_PIN(hscif0_ctrl_a,     RCAR_GP_PIN(1, 20),     RCAR_GP_PIN(1, 21));
+SCIF_PFC_CTR(hscif0_ctrl_a,     HCTS0_A,                HRTS0_A);
+SCIF_PFC_PIN(hscif0_ctrl_b,     RCAR_GP_PIN(0, 31),     RCAR_GP_PIN(0, 28));
+SCIF_PFC_CTR(hscif0_ctrl_b,     HCTS0_B,                HRTS0_B);
+SCIF_PFC_PIN(hscif0_clk,        RCAR_GP_PIN(1, 19));
+SCIF_PFC_CLK(hscif0_clk,        HSCK0);
+
+/* - HSCIF1 ----------------------------------------------------------------- */
+SCIF_PFC_PIN(hscif1_data_a,     RCAR_GP_PIN(3, 19),     RCAR_GP_PIN(3, 20));
+SCIF_PFC_DAT(hscif1_data_a,     HTX1_A,                 HRX1_A);
+SCIF_PFC_PIN(hscif1_data_b,     RCAR_GP_PIN(4, 5),      RCAR_GP_PIN(4, 6));
+SCIF_PFC_DAT(hscif1_data_b,     HTX1_B,                 HRX1_B);
+SCIF_PFC_PIN(hscif1_ctrl_a,     RCAR_GP_PIN(3, 22),     RCAR_GP_PIN(3, 21));
+SCIF_PFC_CTR(hscif1_ctrl_a,     HCTS1_A,                HRTS1_A);
+SCIF_PFC_PIN(hscif1_ctrl_b,     RCAR_GP_PIN(4, 8),      RCAR_GP_PIN(4, 7));
+SCIF_PFC_CTR(hscif1_ctrl_b,     HCTS1_B,                HRTS1_B);
+SCIF_PFC_PIN(hscif1_clk_a,      RCAR_GP_PIN(3, 23));
+SCIF_PFC_CLK(hscif1_clk_a,      HSCK1_A);
+SCIF_PFC_PIN(hscif1_clk_b,      RCAR_GP_PIN(4, 2));
+SCIF_PFC_CLK(hscif1_clk_b,      HSCK1_B);
+
+/* - HSPI macro --------------------------------------------------------------*/
+#define HSPI_PFC_PIN(name, args...)             SH_PFC_PINS(name, args)
+#define HSPI_PFC_DAT(name, clk, cs, rx, tx)     SH_PFC_MUX4(name, clk, cs, rx, tx)
+
+/* - HSPI0 -------------------------------------------------------------------*/
+HSPI_PFC_PIN(hspi0_a,   RCAR_GP_PIN(3, 19),     RCAR_GP_PIN(3, 20),
+                        RCAR_GP_PIN(3, 21),     RCAR_GP_PIN(3, 22));
+HSPI_PFC_DAT(hspi0_a,   HSPI_CLK0_A,            HSPI_CS0_A,
+                        HSPI_RX0_A,             HSPI_TX0);
+
+HSPI_PFC_PIN(hspi0_b,   RCAR_GP_PIN(2, 25),     RCAR_GP_PIN(2, 26),
+                        RCAR_GP_PIN(2, 24),     RCAR_GP_PIN(2, 27));
+HSPI_PFC_DAT(hspi0_b,   HSPI_CLK0_B,            HSPI_CS0_B,
+                        HSPI_RX0_B,             HSPI_TX0_B);
+
+/* - HSPI1 -------------------------------------------------------------------*/
+HSPI_PFC_PIN(hspi1_a,   RCAR_GP_PIN(3, 26),     RCAR_GP_PIN(3, 27),
+                        RCAR_GP_PIN(3, 25),     RCAR_GP_PIN(3, 28));
+HSPI_PFC_DAT(hspi1_a,   HSPI_CLK1_A,            HSPI_CS1_A,
+                        HSPI_RX1_A,             HSPI_TX1_A);
+
+HSPI_PFC_PIN(hspi1_b,   RCAR_GP_PIN(0, 27),     RCAR_GP_PIN(0, 26),
+                        PIN_NUMBER(20, 1),      PIN_NUMBER(25, 2));
+HSPI_PFC_DAT(hspi1_b,   HSPI_CLK1_B,            HSPI_CS1_B,
+                        HSPI_RX1_B,             HSPI_TX1_B);
+
+/* - HSPI2 -------------------------------------------------------------------*/
+HSPI_PFC_PIN(hspi2_a,   RCAR_GP_PIN(2, 29),     RCAR_GP_PIN(3, 8),
+                        RCAR_GP_PIN(2, 28),     RCAR_GP_PIN(2, 30));
+HSPI_PFC_DAT(hspi2_a,   HSPI_CLK2_A,            HSPI_CS2_A,
+                        HSPI_RX2_A,             HSPI_TX2_A);
+
+HSPI_PFC_PIN(hspi2_b,   RCAR_GP_PIN(4, 21),     RCAR_GP_PIN(4, 22),
+                        RCAR_GP_PIN(4, 23),     RCAR_GP_PIN(4, 24));
+HSPI_PFC_DAT(hspi2_b,   HSPI_CLK2_B,            HSPI_CS2_B,
+                        HSPI_RX2_B,             HSPI_TX2_B);
+
+/* - I2C macro ------------------------------------------------------------- */
+#define I2C_PFC_PIN(name, args...)      SH_PFC_PINS(name, args)
+#define I2C_PFC_MUX(name, sda, scl)     SH_PFC_MUX2(name, sda, scl)
+
+/* - I2C1 ------------------------------------------------------------------ */
+I2C_PFC_PIN(i2c1_a,     RCAR_GP_PIN(3, 8),      RCAR_GP_PIN(3, 9));
+I2C_PFC_MUX(i2c1_a,     SDA1_A,                 SCL1_A);
+I2C_PFC_PIN(i2c1_b,     RCAR_GP_PIN(4, 17),     RCAR_GP_PIN(4, 18));
+I2C_PFC_MUX(i2c1_b,     SDA1_B,                 SCL1_B);
+
+/* - I2C2 ------------------------------------------------------------------ */
+I2C_PFC_PIN(i2c2_a,     PIN_NUMBER(3, 20),      RCAR_GP_PIN(1, 3));
+I2C_PFC_MUX(i2c2_a,     SDA2_A,                 SCL2_A);
+I2C_PFC_PIN(i2c2_b,     RCAR_GP_PIN(0, 3),      RCAR_GP_PIN(0, 4));
+I2C_PFC_MUX(i2c2_b,     SDA2_B,                 SCL2_B);
+I2C_PFC_PIN(i2c2_c,     RCAR_GP_PIN(4, 15),     RCAR_GP_PIN(4, 16));
+I2C_PFC_MUX(i2c2_c,     SDA2_C,                 SCL2_C);
+
+/* - I2C3 ------------------------------------------------------------------ */
+I2C_PFC_PIN(i2c3_a,     RCAR_GP_PIN(1, 14),     RCAR_GP_PIN(1, 15));
+I2C_PFC_MUX(i2c3_a,     SDA3_A,                 SCL3_A);
+I2C_PFC_PIN(i2c3_b,     RCAR_GP_PIN(1, 16),     RCAR_GP_PIN(1, 19));
+I2C_PFC_MUX(i2c3_b,     SDA3_B,                 SCL3_B);
+I2C_PFC_PIN(i2c3_c,     RCAR_GP_PIN(1, 22),     RCAR_GP_PIN(1, 23));
+I2C_PFC_MUX(i2c3_c,     SDA3_C,                 SCL3_C);
+
+/* - MMC macro -------------------------------------------------------------- */
+#define MMC_PFC_PINS(name, args...)             SH_PFC_PINS(name, args)
+#define MMC_PFC_CTRL(name, clk, cmd)            SH_PFC_MUX2(name, clk, cmd)
+#define MMC_PFC_DAT1(name, d0)                  SH_PFC_MUX1(name, d0)
+#define MMC_PFC_DAT4(name, d0, d1, d2, d3)      SH_PFC_MUX4(name, d0, d1, d2, d3)
+#define MMC_PFC_DAT8(name, d0, d1, d2, d3, d4, d5, d6, d7)      \
+                        SH_PFC_MUX8(name, d0, d1, d2, d3, d4, d5, d6, d7)
+
+/* - MMC -------------------------------------------------------------------- */
+MMC_PFC_PINS(mmc_ctrl,          RCAR_GP_PIN(1, 5),      RCAR_GP_PIN(1, 6));
+MMC_PFC_CTRL(mmc_ctrl,          MMC_CLK,                MMC_CMD);
+MMC_PFC_PINS(mmc_data1,         RCAR_GP_PIN(1, 7));
+MMC_PFC_DAT1(mmc_data1,         MMC_D0);
+MMC_PFC_PINS(mmc_data4,         RCAR_GP_PIN(1, 7),      RCAR_GP_PIN(2, 8),
+                                RCAR_GP_PIN(0, 5),      RCAR_GP_PIN(0, 6));
+MMC_PFC_DAT4(mmc_data4,         MMC_D0,                 MMC_D1,
+                                MMC_D2,                 MMC_D3);
+MMC_PFC_PINS(mmc_data8,         RCAR_GP_PIN(1, 7),      RCAR_GP_PIN(2, 8),
+                                RCAR_GP_PIN(0, 5),      RCAR_GP_PIN(0, 6),
+                                RCAR_GP_PIN(1, 4),      RCAR_GP_PIN(1, 0),
+                                RCAR_GP_PIN(0, 30),     RCAR_GP_PIN(0, 31));
+MMC_PFC_DAT8(mmc_data8,         MMC_D0,                 MMC_D1,
+                                MMC_D2,                 MMC_D3,
+                                MMC_D4,                 MMC_D5,
+                                MMC_D6,                 MMC_D7);
+
+/* - SCIF CLOCK ------------------------------------------------------------- */
+SCIF_PFC_PIN(scif_clk,          RCAR_GP_PIN(1, 16));
+SCIF_PFC_CLK(scif_clk,          SCIF_CLK);
+
+/* - SCIF0 ------------------------------------------------------------------ */
+SCIF_PFC_PIN(scif0_data_a,      RCAR_GP_PIN(1, 17),     RCAR_GP_PIN(1, 18));
+SCIF_PFC_DAT(scif0_data_a,      TX0_A,                  RX0_A);
+SCIF_PFC_PIN(scif0_data_b,      RCAR_GP_PIN(2, 3),      RCAR_GP_PIN(2, 2));
+SCIF_PFC_DAT(scif0_data_b,      TX0_B,                  RX0_B);
+SCIF_PFC_PIN(scif0_data_c,      RCAR_GP_PIN(4, 0),      RCAR_GP_PIN(3, 31));
+SCIF_PFC_DAT(scif0_data_c,      TX0_C,                  RX0_C);
+SCIF_PFC_PIN(scif0_data_d,      RCAR_GP_PIN(3, 6),      RCAR_GP_PIN(3, 1));
+SCIF_PFC_DAT(scif0_data_d,      TX0_D,                  RX0_D);
+SCIF_PFC_PIN(scif0_ctrl,        RCAR_GP_PIN(1, 20),     RCAR_GP_PIN(1, 21));
+SCIF_PFC_CTR(scif0_ctrl,        CTS0,                   RTS0);
+SCIF_PFC_PIN(scif0_clk,         RCAR_GP_PIN(1, 19));
+SCIF_PFC_CLK(scif0_clk,         SCK0);
+
+/* - SCIF1 ------------------------------------------------------------------ */
+SCIF_PFC_PIN(scif1_data_a,      RCAR_GP_PIN(4, 0),      RCAR_GP_PIN(4, 1));
+SCIF_PFC_DAT(scif1_data_a,      TX1_A,                  RX1_A);
+SCIF_PFC_PIN(scif1_data_b,      RCAR_GP_PIN(2, 24),     RCAR_GP_PIN(2, 25));
+SCIF_PFC_DAT(scif1_data_b,      TX1_B,                  RX1_B);
+SCIF_PFC_PIN(scif1_data_c,      RCAR_GP_PIN(3, 22),     RCAR_GP_PIN(3, 21));
+SCIF_PFC_DAT(scif1_data_c,      TX1_C,                  RX1_C);
+SCIF_PFC_PIN(scif1_data_d,      RCAR_GP_PIN(1, 30),     RCAR_GP_PIN(1, 31));
+SCIF_PFC_DAT(scif1_data_d,      TX1_D,                  RX1_D);
+SCIF_PFC_PIN(scif1_ctrl_a,      RCAR_GP_PIN(4, 3),      RCAR_GP_PIN(4, 4));
+SCIF_PFC_CTR(scif1_ctrl_a,      CTS1_A,                 RTS1_A);
+SCIF_PFC_PIN(scif1_ctrl_c,      RCAR_GP_PIN(3, 23),     RCAR_GP_PIN(3, 19));
+SCIF_PFC_CTR(scif1_ctrl_c,      CTS1_C,                 RTS1_C);
+SCIF_PFC_PIN(scif1_clk_a,       RCAR_GP_PIN(4, 2));
+SCIF_PFC_CLK(scif1_clk_a,       SCK1_A);
+SCIF_PFC_PIN(scif1_clk_c,       RCAR_GP_PIN(3, 20));
+SCIF_PFC_CLK(scif1_clk_c,       SCK1_C);
+
+/* - SCIF2 ------------------------------------------------------------------ */
+SCIF_PFC_PIN(scif2_data_a,      RCAR_GP_PIN(2, 26),     RCAR_GP_PIN(2, 27));
+SCIF_PFC_DAT(scif2_data_a,      TX2_A,                  RX2_A);
+SCIF_PFC_PIN(scif2_data_b,      RCAR_GP_PIN(0, 29),     RCAR_GP_PIN(0, 28));
+SCIF_PFC_DAT(scif2_data_b,      TX2_B,                  RX2_B);
+SCIF_PFC_PIN(scif2_data_c,      RCAR_GP_PIN(4, 13),     RCAR_GP_PIN(4, 14));
+SCIF_PFC_DAT(scif2_data_c,      TX2_C,                  RX2_C);
+SCIF_PFC_PIN(scif2_data_d,      RCAR_GP_PIN(4, 15),     RCAR_GP_PIN(4, 16));
+SCIF_PFC_DAT(scif2_data_d,      TX2_D,                  RX2_D);
+SCIF_PFC_PIN(scif2_data_e,      RCAR_GP_PIN(0, 3),      RCAR_GP_PIN(0, 4));
+SCIF_PFC_DAT(scif2_data_e,      TX2_E,                  RX2_E);
+SCIF_PFC_PIN(scif2_clk_a,       RCAR_GP_PIN(3, 9));
+SCIF_PFC_CLK(scif2_clk_a,       SCK2_A);
+SCIF_PFC_PIN(scif2_clk_b,       PIN_NUMBER(3, 20));
+SCIF_PFC_CLK(scif2_clk_b,       SCK2_B);
+SCIF_PFC_PIN(scif2_clk_c,       RCAR_GP_PIN(4, 12));
+SCIF_PFC_CLK(scif2_clk_c,       SCK2_C);
+
+/* - SCIF3 ------------------------------------------------------------------ */
+SCIF_PFC_PIN(scif3_data_a,      RCAR_GP_PIN(1, 10),     RCAR_GP_PIN(1, 9));
+SCIF_PFC_DAT(scif3_data_a,      TX3_A,                  RX3_A);
+SCIF_PFC_PIN(scif3_data_b,      RCAR_GP_PIN(3, 28),     RCAR_GP_PIN(3, 27));
+SCIF_PFC_DAT(scif3_data_b,      TX3_B,                  RX3_B);
+SCIF_PFC_PIN(scif3_data_c,      RCAR_GP_PIN(1, 3),      RCAR_GP_PIN(0, 31));
+SCIF_PFC_DAT(scif3_data_c,      TX3_C,                  RX3_C);
+SCIF_PFC_PIN(scif3_data_d,      RCAR_GP_PIN(3, 30),     RCAR_GP_PIN(3, 29));
+SCIF_PFC_DAT(scif3_data_d,      TX3_D,                  RX3_D);
+
+/* - SCIF4 ------------------------------------------------------------------ */
+SCIF_PFC_PIN(scif4_data_a,      RCAR_GP_PIN(2, 5),      RCAR_GP_PIN(2, 4));
+SCIF_PFC_DAT(scif4_data_a,      TX4_A,                  RX4_A);
+SCIF_PFC_PIN(scif4_data_b,      RCAR_GP_PIN(3, 26),     RCAR_GP_PIN(3, 25));
+SCIF_PFC_DAT(scif4_data_b,      TX4_B,                  RX4_B);
+SCIF_PFC_PIN(scif4_data_c,      RCAR_GP_PIN(3, 0),      RCAR_GP_PIN(2, 31));
+SCIF_PFC_DAT(scif4_data_c,      TX4_C,                  RX4_C);
+
+/* - SCIF5 ------------------------------------------------------------------ */
+SCIF_PFC_PIN(scif5_data_a,      RCAR_GP_PIN(3, 17),     RCAR_GP_PIN(3, 18));
+SCIF_PFC_DAT(scif5_data_a,      TX5_A,                  RX5_A);
+SCIF_PFC_PIN(scif5_data_b,      RCAR_GP_PIN(1, 15),     RCAR_GP_PIN(1, 14));
+SCIF_PFC_DAT(scif5_data_b,      TX5_B,                  RX5_B);
+
+/* - SDHI macro ------------------------------------------------------------- */
+#define SDHI_PFC_PINS(name, args...)            SH_PFC_PINS(name, args)
+#define SDHI_PFC_DAT1(name, d0)                 SH_PFC_MUX1(name, d0)
+#define SDHI_PFC_DAT4(name, d0, d1, d2, d3)     SH_PFC_MUX4(name, d0, d1, d2, d3)
+#define SDHI_PFC_CTRL(name, clk, cmd)           SH_PFC_MUX2(name, clk, cmd)
+#define SDHI_PFC_CDPN(name, cd)                 SH_PFC_MUX1(name, cd)
+#define SDHI_PFC_WPPN(name, wp)                 SH_PFC_MUX1(name, wp)
+
+/* - SDHI0 ------------------------------------------------------------------ */
+SDHI_PFC_PINS(sdhi0_cd,         RCAR_GP_PIN(3, 17));
+SDHI_PFC_CDPN(sdhi0_cd,         SD0_CD);
+SDHI_PFC_PINS(sdhi0_ctrl,       RCAR_GP_PIN(3, 11),     RCAR_GP_PIN(3, 12));
+SDHI_PFC_CTRL(sdhi0_ctrl,       SD0_CLK,                SD0_CMD);
+SDHI_PFC_PINS(sdhi0_data1,      RCAR_GP_PIN(3, 13));
+SDHI_PFC_DAT1(sdhi0_data1,      SD0_DAT0);
+SDHI_PFC_PINS(sdhi0_data4,      RCAR_GP_PIN(3, 13),     RCAR_GP_PIN(3, 14),
+                                RCAR_GP_PIN(3, 15),     RCAR_GP_PIN(3, 16));
+SDHI_PFC_DAT4(sdhi0_data4,      SD0_DAT0,               SD0_DAT1,
+                                SD0_DAT2,               SD0_DAT3);
+SDHI_PFC_PINS(sdhi0_wp,         RCAR_GP_PIN(3, 18));
+SDHI_PFC_WPPN(sdhi0_wp,         SD0_WP);
+
+/* - SDHI1 ------------------------------------------------------------------ */
+SDHI_PFC_PINS(sdhi1_cd_a,       RCAR_GP_PIN(0, 30));
+SDHI_PFC_CDPN(sdhi1_cd_a,       SD1_CD_A);
+SDHI_PFC_PINS(sdhi1_cd_b,       RCAR_GP_PIN(2, 24));
+SDHI_PFC_CDPN(sdhi1_cd_b,       SD1_CD_B);
+SDHI_PFC_PINS(sdhi1_ctrl_a,     RCAR_GP_PIN(1, 5),      RCAR_GP_PIN(1, 6));
+SDHI_PFC_CTRL(sdhi1_ctrl_a,     SD1_CLK_A,              SD1_CMD_A);
+SDHI_PFC_PINS(sdhi1_ctrl_b,     RCAR_GP_PIN(1, 17),     RCAR_GP_PIN(1, 16));
+SDHI_PFC_CTRL(sdhi1_ctrl_b,     SD1_CLK_B,              SD1_CMD_B);
+SDHI_PFC_PINS(sdhi1_data1_a,    RCAR_GP_PIN(1, 7));
+SDHI_PFC_DAT1(sdhi1_data1_a,    SD1_DAT0_A);
+SDHI_PFC_PINS(sdhi1_data1_b,    RCAR_GP_PIN(1, 18));
+SDHI_PFC_DAT1(sdhi1_data1_b,    SD1_DAT0_B);
+SDHI_PFC_PINS(sdhi1_data4_a,    RCAR_GP_PIN(1, 7),      RCAR_GP_PIN(1, 8),
+                                RCAR_GP_PIN(0, 5),      RCAR_GP_PIN(0, 6));
+SDHI_PFC_DAT4(sdhi1_data4_a,    SD1_DAT0_A,             SD1_DAT1_A,
+                                SD1_DAT2_A,             SD1_DAT3_A);
+SDHI_PFC_PINS(sdhi1_data4_b,    RCAR_GP_PIN(1, 18),     RCAR_GP_PIN(1, 19),
+                                RCAR_GP_PIN(1, 20),     RCAR_GP_PIN(1, 21));
+SDHI_PFC_DAT4(sdhi1_data4_b,    SD1_DAT0_B,             SD1_DAT1_B,
+                                SD1_DAT2_B,             SD1_DAT3_B);
+SDHI_PFC_PINS(sdhi1_wp_a,       RCAR_GP_PIN(0, 31));
+SDHI_PFC_WPPN(sdhi1_wp_a,       SD1_WP_A);
+SDHI_PFC_PINS(sdhi1_wp_b,       RCAR_GP_PIN(2, 25));
+SDHI_PFC_WPPN(sdhi1_wp_b,       SD1_WP_B);
+
+/* - SDH2 ------------------------------------------------------------------- */
+SDHI_PFC_PINS(sdhi2_cd_a,       RCAR_GP_PIN(4, 23));
+SDHI_PFC_CDPN(sdhi2_cd_a,       SD2_CD_A);
+SDHI_PFC_PINS(sdhi2_cd_b,       RCAR_GP_PIN(3, 27));
+SDHI_PFC_CDPN(sdhi2_cd_b,       SD2_CD_B);
+SDHI_PFC_PINS(sdhi2_ctrl_a,     RCAR_GP_PIN(4, 17),     RCAR_GP_PIN(4, 18));
+SDHI_PFC_CTRL(sdhi2_ctrl_a,     SD2_CLK_A,              SD2_CMD_A);
+SDHI_PFC_PINS(sdhi2_ctrl_b,     RCAR_GP_PIN(4, 5),      RCAR_GP_PIN(4, 6));
+SDHI_PFC_CTRL(sdhi2_ctrl_b,     SD2_CLK_B,              SD2_CMD_B);
+SDHI_PFC_PINS(sdhi2_data1_a,    RCAR_GP_PIN(4, 19));
+SDHI_PFC_DAT1(sdhi2_data1_a,    SD2_DAT0_A);
+SDHI_PFC_PINS(sdhi2_data1_b,    RCAR_GP_PIN(4, 7));
+SDHI_PFC_DAT1(sdhi2_data1_b,    SD2_DAT0_B);
+SDHI_PFC_PINS(sdhi2_data4_a,    RCAR_GP_PIN(4, 19),     RCAR_GP_PIN(4, 20),
+                                RCAR_GP_PIN(4, 21),     RCAR_GP_PIN(4, 22));
+SDHI_PFC_DAT4(sdhi2_data4_a,    SD2_DAT0_A,             SD2_DAT1_A,
+                                SD2_DAT2_A,             SD2_DAT3_A);
+SDHI_PFC_PINS(sdhi2_data4_b,    RCAR_GP_PIN(4, 7),      RCAR_GP_PIN(4, 8),
+                                RCAR_GP_PIN(3, 25),     RCAR_GP_PIN(3, 26));
+SDHI_PFC_DAT4(sdhi2_data4_b,    SD2_DAT0_B,             SD2_DAT1_B,
+                                SD2_DAT2_B,             SD2_DAT3_B);
+SDHI_PFC_PINS(sdhi2_wp_a,       RCAR_GP_PIN(4, 24));
+SDHI_PFC_WPPN(sdhi2_wp_a,       SD2_WP_A);
+SDHI_PFC_PINS(sdhi2_wp_b,       RCAR_GP_PIN(3, 28));
+SDHI_PFC_WPPN(sdhi2_wp_b,       SD2_WP_B);
+
+/* - USB0 ------------------------------------------------------------------- */
+SH_PFC_PINS(usb0,               RCAR_GP_PIN(0, 1));
+SH_PFC_MUX1(usb0,               PENC0);
+SH_PFC_PINS(usb0_ovc,           RCAR_GP_PIN(0, 3));
+SH_PFC_MUX1(usb0_ovc,           USB_OVC0);
+
+/* - USB1 ------------------------------------------------------------------- */
+SH_PFC_PINS(usb1,               RCAR_GP_PIN(0, 2));
+SH_PFC_MUX1(usb1,               PENC1);
+SH_PFC_PINS(usb1_ovc,           RCAR_GP_PIN(0, 4));
+SH_PFC_MUX1(usb1_ovc,           USB_OVC1);
+
+/* - VIN macros ------------------------------------------------------------- */
+#define VIN_PFC_PINS(name, args...)             SH_PFC_PINS(name, args)
+#define VIN_PFC_DAT8(name, d0, d1, d2, d3, d4, d5, d6, d7)      \
+        SH_PFC_MUX8(name, d0, d1, d2, d3, d4, d5, d6, d7)
+#define VIN_PFC_CLK(name, clk)                  SH_PFC_MUX1(name, clk)
+#define VIN_PFC_SYNC(name, hsync, vsync)        SH_PFC_MUX2(name, hsync, vsync)
+
+/* - VIN0 ------------------------------------------------------------------- */
+VIN_PFC_PINS(vin0_data8,        RCAR_GP_PIN(3, 29),     RCAR_GP_PIN(3, 30),
+                                RCAR_GP_PIN(3, 31),     RCAR_GP_PIN(4, 0),
+                                RCAR_GP_PIN(4, 1),      RCAR_GP_PIN(4, 2),
+                                RCAR_GP_PIN(4, 3),      RCAR_GP_PIN(4, 4));
+VIN_PFC_DAT8(vin0_data8,        VI0_DATA0_VI0_B0,       VI0_DATA1_VI0_B1,
+                                VI0_DATA2_VI0_B2,       VI0_DATA3_VI0_B3,
+                                VI0_DATA4_VI0_B4,       VI0_DATA5_VI0_B5,
+                                VI0_DATA6_VI0_G0,       VI0_DATA7_VI0_G1);
+VIN_PFC_PINS(vin0_clk,          RCAR_GP_PIN(3, 24));
+VIN_PFC_CLK(vin0_clk,           VI0_CLK);
+VIN_PFC_PINS(vin0_sync,         RCAR_GP_PIN(3, 27),     RCAR_GP_PIN(3, 28));
+VIN_PFC_SYNC(vin0_sync,         VI0_HSYNC,              VI0_VSYNC);
+/* - VIN1 ------------------------------------------------------------------- */
+VIN_PFC_PINS(vin1_data8,        RCAR_GP_PIN(3, 25),     RCAR_GP_PIN(3, 26),
+                                RCAR_GP_PIN(3, 27),     RCAR_GP_PIN(3, 28),
+                                RCAR_GP_PIN(4, 5),      RCAR_GP_PIN(4, 6),
+                                RCAR_GP_PIN(4, 7),      RCAR_GP_PIN(4, 8));
+VIN_PFC_DAT8(vin1_data8,        VI1_DATA0,              VI1_DATA1,
+                                VI1_DATA2,              VI1_DATA3,
+                                VI1_DATA4,              VI1_DATA5,
+                                VI1_DATA6,              VI1_DATA7);
+VIN_PFC_PINS(vin1_clk,          RCAR_GP_PIN(4, 9));
+VIN_PFC_CLK(vin1_clk,           VI1_CLK);
+VIN_PFC_PINS(vin1_sync,         RCAR_GP_PIN(3, 21),     RCAR_GP_PIN(3, 22));
+VIN_PFC_SYNC(vin1_sync,         VI1_HSYNC,              VI1_VSYNC);
+
+static const struct sh_pfc_pin_group pinmux_groups[] = {
+        SH_PFC_PIN_GROUP(ether_rmii),
+        SH_PFC_PIN_GROUP(ether_link),
+        SH_PFC_PIN_GROUP(ether_magic),
+        SH_PFC_PIN_GROUP(hscif0_data_a),
+        SH_PFC_PIN_GROUP(hscif0_data_b),
+        SH_PFC_PIN_GROUP(hscif0_ctrl_a),
+        SH_PFC_PIN_GROUP(hscif0_ctrl_b),
+        SH_PFC_PIN_GROUP(hscif0_clk),
+        SH_PFC_PIN_GROUP(hscif1_data_a),
+        SH_PFC_PIN_GROUP(hscif1_data_b),
+        SH_PFC_PIN_GROUP(hscif1_ctrl_a),
+        SH_PFC_PIN_GROUP(hscif1_ctrl_b),
+        SH_PFC_PIN_GROUP(hscif1_clk_a),
+        SH_PFC_PIN_GROUP(hscif1_clk_b),
+        SH_PFC_PIN_GROUP(hspi0_a),
+        SH_PFC_PIN_GROUP(hspi0_b),
+        SH_PFC_PIN_GROUP(hspi1_a),
+        SH_PFC_PIN_GROUP(hspi1_b),
+        SH_PFC_PIN_GROUP(hspi2_a),
+        SH_PFC_PIN_GROUP(hspi2_b),
+        SH_PFC_PIN_GROUP(i2c1_a),
+        SH_PFC_PIN_GROUP(i2c1_b),
+        SH_PFC_PIN_GROUP(i2c2_a),
+        SH_PFC_PIN_GROUP(i2c2_b),
+        SH_PFC_PIN_GROUP(i2c2_c),
+        SH_PFC_PIN_GROUP(i2c3_a),
+        SH_PFC_PIN_GROUP(i2c3_b),
+        SH_PFC_PIN_GROUP(i2c3_c),
+        SH_PFC_PIN_GROUP(mmc_ctrl),
+        SH_PFC_PIN_GROUP(mmc_data1),
+        SH_PFC_PIN_GROUP(mmc_data4),
+        SH_PFC_PIN_GROUP(mmc_data8),
+        SH_PFC_PIN_GROUP(scif_clk),
+        SH_PFC_PIN_GROUP(scif0_data_a),
+        SH_PFC_PIN_GROUP(scif0_data_b),
+        SH_PFC_PIN_GROUP(scif0_data_c),
+        SH_PFC_PIN_GROUP(scif0_data_d),
+        SH_PFC_PIN_GROUP(scif0_ctrl),
+        SH_PFC_PIN_GROUP(scif0_clk),
+        SH_PFC_PIN_GROUP(scif1_data_a),
+        SH_PFC_PIN_GROUP(scif1_data_b),
+        SH_PFC_PIN_GROUP(scif1_data_c),
+        SH_PFC_PIN_GROUP(scif1_data_d),
+        SH_PFC_PIN_GROUP(scif1_ctrl_a),
+        SH_PFC_PIN_GROUP(scif1_ctrl_c),
+        SH_PFC_PIN_GROUP(scif1_clk_a),
+        SH_PFC_PIN_GROUP(scif1_clk_c),
+        SH_PFC_PIN_GROUP(scif2_data_a),
+        SH_PFC_PIN_GROUP(scif2_data_b),
+        SH_PFC_PIN_GROUP(scif2_data_c),
+        SH_PFC_PIN_GROUP(scif2_data_d),
+        SH_PFC_PIN_GROUP(scif2_data_e),
+        SH_PFC_PIN_GROUP(scif2_clk_a),
+        SH_PFC_PIN_GROUP(scif2_clk_b),
+        SH_PFC_PIN_GROUP(scif2_clk_c),
+        SH_PFC_PIN_GROUP(scif3_data_a),
+        SH_PFC_PIN_GROUP(scif3_data_b),
+        SH_PFC_PIN_GROUP(scif3_data_c),
+        SH_PFC_PIN_GROUP(scif3_data_d),
+        SH_PFC_PIN_GROUP(scif4_data_a),
+        SH_PFC_PIN_GROUP(scif4_data_b),
+        SH_PFC_PIN_GROUP(scif4_data_c),
+        SH_PFC_PIN_GROUP(scif5_data_a),
+        SH_PFC_PIN_GROUP(scif5_data_b),
+        SH_PFC_PIN_GROUP(sdhi0_cd),
+        SH_PFC_PIN_GROUP(sdhi0_ctrl),
+        SH_PFC_PIN_GROUP(sdhi0_data1),
+        SH_PFC_PIN_GROUP(sdhi0_data4),
+        SH_PFC_PIN_GROUP(sdhi0_wp),
+        SH_PFC_PIN_GROUP(sdhi1_cd_a),
+        SH_PFC_PIN_GROUP(sdhi1_cd_b),
+        SH_PFC_PIN_GROUP(sdhi1_ctrl_a),
+        SH_PFC_PIN_GROUP(sdhi1_ctrl_b),
+        SH_PFC_PIN_GROUP(sdhi1_data1_a),
+        SH_PFC_PIN_GROUP(sdhi1_data1_b),
+        SH_PFC_PIN_GROUP(sdhi1_data4_a),
+        SH_PFC_PIN_GROUP(sdhi1_data4_b),
+        SH_PFC_PIN_GROUP(sdhi1_wp_a),
+        SH_PFC_PIN_GROUP(sdhi1_wp_b),
+        SH_PFC_PIN_GROUP(sdhi2_cd_a),
+        SH_PFC_PIN_GROUP(sdhi2_cd_b),
+        SH_PFC_PIN_GROUP(sdhi2_ctrl_a),
+        SH_PFC_PIN_GROUP(sdhi2_ctrl_b),
+        SH_PFC_PIN_GROUP(sdhi2_data1_a),
+        SH_PFC_PIN_GROUP(sdhi2_data1_b),
+        SH_PFC_PIN_GROUP(sdhi2_data4_a),
+        SH_PFC_PIN_GROUP(sdhi2_data4_b),
+        SH_PFC_PIN_GROUP(sdhi2_wp_a),
+        SH_PFC_PIN_GROUP(sdhi2_wp_b),
+        SH_PFC_PIN_GROUP(usb0),
+        SH_PFC_PIN_GROUP(usb0_ovc),
+        SH_PFC_PIN_GROUP(usb1),
+        SH_PFC_PIN_GROUP(usb1_ovc),
+        SH_PFC_PIN_GROUP(vin0_data8),
+        SH_PFC_PIN_GROUP(vin0_clk),
+        SH_PFC_PIN_GROUP(vin0_sync),
+        SH_PFC_PIN_GROUP(vin1_data8),
+        SH_PFC_PIN_GROUP(vin1_clk),
+        SH_PFC_PIN_GROUP(vin1_sync),
+};
+
+static const char * const ether_groups[] = {
+        "ether_rmii",
+        "ether_link",
+        "ether_magic",
+};
+
+static const char * const hscif0_groups[] = {
+        "hscif0_data_a",
+        "hscif0_data_b",
+        "hscif0_ctrl_a",
+        "hscif0_ctrl_b",
+        "hscif0_clk",
+};
+
+static const char * const hscif1_groups[] = {
+        "hscif1_data_a",
+        "hscif1_data_b",
+        "hscif1_ctrl_a",
+        "hscif1_ctrl_b",
+        "hscif1_clk_a",
+        "hscif1_clk_b",
+};
+
+static const char * const hspi0_groups[] = {
+        "hspi0_a",
+        "hspi0_b",
+};
+
+static const char * const hspi1_groups[] = {
+        "hspi1_a",
+        "hspi1_b",
+};
+
+static const char * const hspi2_groups[] = {
+        "hspi2_a",
+        "hspi2_b",
+};
+
+static const char * const i2c1_groups[] = {
+        "i2c1_a",
+        "i2c1_b",
+};
+
+static const char * const i2c2_groups[] = {
+        "i2c2_a",
+        "i2c2_b",
+        "i2c2_c",
+};
+
+static const char * const i2c3_groups[] = {
+        "i2c3_a",
+        "i2c3_b",
+        "i2c3_c",
+};
+
+static const char * const mmc_groups[] = {
+        "mmc_ctrl",
+        "mmc_data1",
+        "mmc_data4",
+        "mmc_data8",
+};
+
+static const char * const scif_clk_groups[] = {
+        "scif_clk",
+};
+
+static const char * const scif0_groups[] = {
+        "scif0_data_a",
+        "scif0_data_b",
+        "scif0_data_c",
+        "scif0_data_d",
+        "scif0_ctrl",
+        "scif0_clk",
+};
+
+static const char * const scif1_groups[] = {
+        "scif1_data_a",
+        "scif1_data_b",
+        "scif1_data_c",
+        "scif1_data_d",
+        "scif1_ctrl_a",
+        "scif1_ctrl_c",
+        "scif1_clk_a",
+        "scif1_clk_c",
+};
+
+static const char * const scif2_groups[] = {
+        "scif2_data_a",
+        "scif2_data_b",
+        "scif2_data_c",
+        "scif2_data_d",
+        "scif2_data_e",
+        "scif2_clk_a",
+        "scif2_clk_b",
+        "scif2_clk_c",
+};
+
+static const char * const scif3_groups[] = {
+        "scif3_data_a",
+        "scif3_data_b",
+        "scif3_data_c",
+        "scif3_data_d",
+};
+
+static const char * const scif4_groups[] = {
+        "scif4_data_a",
+        "scif4_data_b",
+        "scif4_data_c",
+};
+
+static const char * const scif5_groups[] = {
+        "scif5_data_a",
+        "scif5_data_b",
+};
+
+
+static const char * const sdhi0_groups[] = {
+        "sdhi0_cd",
+        "sdhi0_ctrl",
+        "sdhi0_data1",
+        "sdhi0_data4",
+        "sdhi0_wp",
+};
+
+static const char * const sdhi1_groups[] = {
+        "sdhi1_cd_a",
+        "sdhi1_cd_b",
+        "sdhi1_ctrl_a",
+        "sdhi1_ctrl_b",
+        "sdhi1_data1_a",
+        "sdhi1_data1_b",
+        "sdhi1_data4_a",
+        "sdhi1_data4_b",
+        "sdhi1_wp_a",
+        "sdhi1_wp_b",
+};
+
+static const char * const sdhi2_groups[] = {
+        "sdhi2_cd_a",
+        "sdhi2_cd_b",
+        "sdhi2_ctrl_a",
+        "sdhi2_ctrl_b",
+        "sdhi2_data1_a",
+        "sdhi2_data1_b",
+        "sdhi2_data4_a",
+        "sdhi2_data4_b",
+        "sdhi2_wp_a",
+        "sdhi2_wp_b",
+};
+
+static const char * const usb0_groups[] = {
+        "usb0",
+        "usb0_ovc",
+};
+
+static const char * const usb1_groups[] = {
+        "usb1",
+        "usb1_ovc",
+};
+
+static const char * const vin0_groups[] = {
+        "vin0_data8",
+        "vin0_clk",
+        "vin0_sync",
+};
+
+static const char * const vin1_groups[] = {
+        "vin1_data8",
+        "vin1_clk",
+        "vin1_sync",
+};
+
+static const struct sh_pfc_function pinmux_functions[] = {
+        SH_PFC_FUNCTION(ether),
+        SH_PFC_FUNCTION(hscif0),
+        SH_PFC_FUNCTION(hscif1),
+        SH_PFC_FUNCTION(hspi0),
+        SH_PFC_FUNCTION(hspi1),
+        SH_PFC_FUNCTION(hspi2),
+        SH_PFC_FUNCTION(i2c1),
+        SH_PFC_FUNCTION(i2c2),
+        SH_PFC_FUNCTION(i2c3),
+        SH_PFC_FUNCTION(mmc),
+        SH_PFC_FUNCTION(scif_clk),
+        SH_PFC_FUNCTION(scif0),
+        SH_PFC_FUNCTION(scif1),
+        SH_PFC_FUNCTION(scif2),
+        SH_PFC_FUNCTION(scif3),
+        SH_PFC_FUNCTION(scif4),
+        SH_PFC_FUNCTION(scif5),
+        SH_PFC_FUNCTION(sdhi0),
+        SH_PFC_FUNCTION(sdhi1),
+        SH_PFC_FUNCTION(sdhi2),
+        SH_PFC_FUNCTION(usb0),
+        SH_PFC_FUNCTION(usb1),
+        SH_PFC_FUNCTION(vin0),
+        SH_PFC_FUNCTION(vin1),
+};
+
+static struct pinmux_cfg_reg pinmux_config_regs[] = {
+        { PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1) {
+                GP_0_31_FN,     FN_IP1_14_11,
+                GP_0_30_FN,     FN_IP1_10_8,
+                GP_0_29_FN,     FN_IP1_7_5,
+                GP_0_28_FN,     FN_IP1_4_2,
+                GP_0_27_FN,     FN_IP1_1,
+                GP_0_26_FN,     FN_IP1_0,
+                GP_0_25_FN,     FN_IP0_30,
+                GP_0_24_FN,     FN_IP0_29,
+                GP_0_23_FN,     FN_IP0_28,
+                GP_0_22_FN,     FN_IP0_27,
+                GP_0_21_FN,     FN_IP0_26,
+                GP_0_20_FN,     FN_IP0_25,
+                GP_0_19_FN,     FN_IP0_24,
+                GP_0_18_FN,     FN_IP0_23,
+                GP_0_17_FN,     FN_IP0_22,
+                GP_0_16_FN,     FN_IP0_21,
+                GP_0_15_FN,     FN_IP0_20,
+                GP_0_14_FN,     FN_IP0_19,
+                GP_0_13_FN,     FN_IP0_18,
+                GP_0_12_FN,     FN_IP0_17,
+                GP_0_11_FN,     FN_IP0_16,
+                GP_0_10_FN,     FN_IP0_15,
+                GP_0_9_FN,      FN_A3,
+                GP_0_8_FN,      FN_A2,
+                GP_0_7_FN,      FN_A1,
+                GP_0_6_FN,      FN_IP0_14_12,
+                GP_0_5_FN,      FN_IP0_11_8,
+                GP_0_4_FN,      FN_IP0_7_5,
+                GP_0_3_FN,      FN_IP0_4_2,
+                GP_0_2_FN,      FN_PENC1,
+                GP_0_1_FN,      FN_PENC0,
+                GP_0_0_FN,      FN_IP0_1_0 }
+        },
+        { PINMUX_CFG_REG("GPSR1", 0xfffc0008, 32, 1) {
+                GP_1_31_FN,     FN_IP4_6_4,
+                GP_1_30_FN,     FN_IP4_3_1,
+                GP_1_29_FN,     FN_IP4_0,
+                GP_1_28_FN,     FN_IP3_31,
+                GP_1_27_FN,     FN_IP3_30,
+                GP_1_26_FN,     FN_IP3_29,
+                GP_1_25_FN,     FN_IP3_28,
+                GP_1_24_FN,     FN_IP3_27,
+                GP_1_23_FN,     FN_IP3_26_24,
+                GP_1_22_FN,     FN_IP3_23_21,
+                GP_1_21_FN,     FN_IP3_20_19,
+                GP_1_20_FN,     FN_IP3_18_16,
+                GP_1_19_FN,     FN_IP3_15_13,
+                GP_1_18_FN,     FN_IP3_12_10,
+                GP_1_17_FN,     FN_IP3_9_8,
+                GP_1_16_FN,     FN_IP3_7_5,
+                GP_1_15_FN,     FN_IP3_4_2,
+                GP_1_14_FN,     FN_IP3_1_0,
+                GP_1_13_FN,     FN_IP2_31,
+                GP_1_12_FN,     FN_IP2_30,
+                GP_1_11_FN,     FN_IP2_17,
+                GP_1_10_FN,     FN_IP2_16_14,
+                GP_1_9_FN,      FN_IP2_13_12,
+                GP_1_8_FN,      FN_IP2_11_9,
+                GP_1_7_FN,      FN_IP2_8_6,
+                GP_1_6_FN,      FN_IP2_5_3,
+                GP_1_5_FN,      FN_IP2_2_0,
+                GP_1_4_FN,      FN_IP1_29_28,
+                GP_1_3_FN,      FN_IP1_27_25,
+                GP_1_2_FN,      FN_IP1_24,
+                GP_1_1_FN,      FN_WE0,
+                GP_1_0_FN,      FN_IP1_23_21 }
+        },
+        { PINMUX_CFG_REG("GPSR2", 0xfffc000c, 32, 1) {
+                GP_2_31_FN,     FN_IP6_7,
+                GP_2_30_FN,     FN_IP6_6_5,
+                GP_2_29_FN,     FN_IP6_4_2,
+                GP_2_28_FN,     FN_IP6_1_0,
+                GP_2_27_FN,     FN_IP5_30_29,
+                GP_2_26_FN,     FN_IP5_28_26,
+                GP_2_25_FN,     FN_IP5_25_23,
+                GP_2_24_FN,     FN_IP5_22_21,
+                GP_2_23_FN,     FN_AUDIO_CLKB,
+                GP_2_22_FN,     FN_AUDIO_CLKA,
+                GP_2_21_FN,     FN_IP5_20_18,
+                GP_2_20_FN,     FN_IP5_17_15,
+                GP_2_19_FN,     FN_IP5_14_13,
+                GP_2_18_FN,     FN_IP5_12,
+                GP_2_17_FN,     FN_IP5_11_10,
+                GP_2_16_FN,     FN_IP5_9_8,
+                GP_2_15_FN,     FN_IP5_7,
+                GP_2_14_FN,     FN_IP5_6,
+                GP_2_13_FN,     FN_IP5_5_4,
+                GP_2_12_FN,     FN_IP5_3_2,
+                GP_2_11_FN,     FN_IP5_1_0,
+                GP_2_10_FN,     FN_IP4_30_29,
+                GP_2_9_FN,      FN_IP4_28_27,
+                GP_2_8_FN,      FN_IP4_26_25,
+                GP_2_7_FN,      FN_IP4_24_21,
+                GP_2_6_FN,      FN_IP4_20_17,
+                GP_2_5_FN,      FN_IP4_16_15,
+                GP_2_4_FN,      FN_IP4_14_13,
+                GP_2_3_FN,      FN_IP4_12_11,
+                GP_2_2_FN,      FN_IP4_10_9,
+                GP_2_1_FN,      FN_IP4_8,
+                GP_2_0_FN,      FN_IP4_7 }
+        },
+        { PINMUX_CFG_REG("GPSR3", 0xfffc0010, 32, 1) {
+                GP_3_31_FN,     FN_IP8_10_9,
+                GP_3_30_FN,     FN_IP8_8_6,
+                GP_3_29_FN,     FN_IP8_5_3,
+                GP_3_28_FN,     FN_IP8_2_0,
+                GP_3_27_FN,     FN_IP7_31_29,
+                GP_3_26_FN,     FN_IP7_28_25,
+                GP_3_25_FN,     FN_IP7_24_22,
+                GP_3_24_FN,     FN_IP7_21,
+                GP_3_23_FN,     FN_IP7_20_18,
+                GP_3_22_FN,     FN_IP7_17_15,
+                GP_3_21_FN,     FN_IP7_14_12,
+                GP_3_20_FN,     FN_IP7_11_9,
+                GP_3_19_FN,     FN_IP7_8_6,
+                GP_3_18_FN,     FN_IP7_5_4,
+                GP_3_17_FN,     FN_IP7_3_2,
+                GP_3_16_FN,     FN_IP7_1_0,
+                GP_3_15_FN,     FN_IP6_31_30,
+                GP_3_14_FN,     FN_IP6_29_28,
+                GP_3_13_FN,     FN_IP6_27_26,
+                GP_3_12_FN,     FN_IP6_25_24,
+                GP_3_11_FN,     FN_IP6_23_22,
+                GP_3_10_FN,     FN_IP6_21,
+                GP_3_9_FN,      FN_IP6_20_19,
+                GP_3_8_FN,      FN_IP6_18_17,
+                GP_3_7_FN,      FN_IP6_16,
+                GP_3_6_FN,      FN_IP6_15_14,
+                GP_3_5_FN,      FN_IP6_13,
+                GP_3_4_FN,      FN_IP6_12_11,
+                GP_3_3_FN,      FN_IP6_10,
+                GP_3_2_FN,      FN_SSI_SCK34,
+                GP_3_1_FN,      FN_IP6_9,
+                GP_3_0_FN,      FN_IP6_8 }
+        },
+        { PINMUX_CFG_REG("GPSR4", 0xfffc0014, 32, 1) {
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                GP_4_26_FN,     FN_AVS2,
+                GP_4_25_FN,     FN_AVS1,
+                GP_4_24_FN,     FN_IP10_24_22,
+                GP_4_23_FN,     FN_IP10_21_19,
+                GP_4_22_FN,     FN_IP10_18_16,
+                GP_4_21_FN,     FN_IP10_15_13,
+                GP_4_20_FN,     FN_IP10_12_9,
+                GP_4_19_FN,     FN_IP10_8_6,
+                GP_4_18_FN,     FN_IP10_5_3,
+                GP_4_17_FN,     FN_IP10_2_0,
+                GP_4_16_FN,     FN_IP9_29_27,
+                GP_4_15_FN,     FN_IP9_26_24,
+                GP_4_14_FN,     FN_IP9_23_21,
+                GP_4_13_FN,     FN_IP9_20_18,
+                GP_4_12_FN,     FN_IP9_17_15,
+                GP_4_11_FN,     FN_IP9_14_12,
+                GP_4_10_FN,     FN_IP9_11_9,
+                GP_4_9_FN,      FN_IP9_8_6,
+                GP_4_8_FN,      FN_IP9_5_3,
+                GP_4_7_FN,      FN_IP9_2_0,
+                GP_4_6_FN,      FN_IP8_29_27,
+                GP_4_5_FN,      FN_IP8_26_24,
+                GP_4_4_FN,      FN_IP8_23_22,
+                GP_4_3_FN,      FN_IP8_21_19,
+                GP_4_2_FN,      FN_IP8_18_16,
+                GP_4_1_FN,      FN_IP8_15_14,
+                GP_4_0_FN,      FN_IP8_13_11 }
+        },
+
+        { PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32,
+                             1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+                             1, 1, 1, 1, 1, 1, 3, 4, 3, 3, 2) {
+                /* IP0_31 [1] */
+                0,      0,
+                /* IP0_30 [1] */
+                FN_A19, 0,
+                /* IP0_29 [1] */
+                FN_A18, 0,
+                /* IP0_28 [1] */
+                FN_A17, 0,
+                /* IP0_27 [1] */
+                FN_A16, 0,
+                /* IP0_26 [1] */
+                FN_A15, 0,
+                /* IP0_25 [1] */
+                FN_A14, 0,
+                /* IP0_24 [1] */
+                FN_A13, 0,
+                /* IP0_23 [1] */
+                FN_A12, 0,
+                /* IP0_22 [1] */
+                FN_A11, 0,
+                /* IP0_21 [1] */
+                FN_A10, 0,
+                /* IP0_20 [1] */
+                FN_A9,  0,
+                /* IP0_19 [1] */
+                FN_A8,  0,
+                /* IP0_18 [1] */
+                FN_A7,  0,
+                /* IP0_17 [1] */
+                FN_A6,  0,
+                /* IP0_16 [1] */
+                FN_A5,  0,
+                /* IP0_15 [1] */
+                FN_A4,  0,
+                /* IP0_14_12 [3] */
+                FN_SD1_DAT3_A,  FN_MMC_D3,      0,              FN_A0,
+                FN_ATAG0_A,     0,              FN_REMOCON_B,   0,
+                /* IP0_11_8 [4] */
+                FN_SD1_DAT2_A,  FN_MMC_D2,      0,              FN_BS,
+                FN_ATADIR0_A,   0,              FN_SDSELF_B,    0,
+                FN_PWM4_B,      0,              0,              0,
+                0,              0,              0,              0,
+                /* IP0_7_5 [3] */
+                FN_AUDATA1,     FN_ARM_TRACEDATA_1,     FN_GPSIN_C,     FN_USB_OVC1,
+                FN_RX2_E,       FN_SCL2_B,              0,              0,
+                /* IP0_4_2 [3] */
+                FN_AUDATA0,     FN_ARM_TRACEDATA_0,     FN_GPSCLK_C,    FN_USB_OVC0,
+                FN_TX2_E,       FN_SDA2_B,              0,              0,
+                /* IP0_1_0 [2] */
+                FN_PRESETOUT,   0,      FN_PWM1,        0,
+                }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32,
+                             1, 1, 2, 3, 1, 3, 3, 1, 2, 4, 3, 3, 3, 1, 1) {
+                /* IP1_31 [1] */
+                0,      0,
+                /* IP1_30 [1] */
+                0,      0,
+                /* IP1_29_28 [2] */
+                FN_EX_CS1,      FN_MMC_D4,      0,      0,
+                /* IP1_27_25 [3] */
+                FN_SSI_WS1_B,   FN_EX_CS0,      FN_SCL2_A,      FN_TX3_C,
+                FN_TS_SCK0_A,   0,              0,              0,
+                /* IP1_24 [1] */
+                FN_WE1,         FN_ATAWR0_B,
+                /* IP1_23_21 [3] */
+                FN_MMC_D5,      FN_ATADIR0_B,   0,              FN_RD_WR,
+                0,              0,              0,              0,
+                /* IP1_20_18 [3] */
+                FN_SSI_SCK1_B,  FN_ATAG0_B,     FN_CS1_A26,     FN_SDA2_A,
+                FN_SCK2_B,      0,              0,              0,
+                /* IP1_17 [1] */
+                FN_CS0,         FN_HSPI_RX1_B,
+                /* IP1_16_15 [2] */
+                FN_CLKOUT,      FN_HSPI_TX1_B,  FN_PWM0_B,      0,
+                /* IP1_14_11 [4] */
+                FN_SD1_WP_A,    FN_MMC_D7,      0,              FN_A25,
+                FN_DACK1_A,     0,              FN_HCTS0_B,     FN_RX3_C,
+                FN_TS_SDAT0_A,  0,              0,              0,
+                0,              0,              0,              0,
+                /* IP1_10_8 [3] */
+                FN_SD1_CLK_B,   FN_MMC_D6,      0,              FN_A24,
+                FN_DREQ1_A,     0,              FN_HRX0_B,      FN_TS_SPSYNC0_A,
+                /* IP1_7_5 [3] */
+                FN_A23,         FN_HTX0_B,      FN_TX2_B,       FN_DACK2_A,
+                FN_TS_SDEN0_A,  0,              0,              0,
+                /* IP1_4_2 [3] */
+                FN_A22,         FN_HRTS0_B,     FN_RX2_B,       FN_DREQ2_A,
+                0,              0,              0,              0,
+                /* IP1_1 [1] */
+                FN_A21,         FN_HSPI_CLK1_B,
+                /* IP1_0 [1] */
+                FN_A20,         FN_HSPI_CS1_B,
+                }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32,
+                             1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+                             1, 1, 1, 1, 3, 2, 3, 3, 3, 3) {
+                /* IP2_31 [1] */
+                FN_MLB_CLK,     FN_IRQ1_A,
+                /* IP2_30 [1] */
+                FN_RD_WR_B,     FN_IRQ0,
+                /* IP2_29 [1] */
+                FN_D11,         0,
+                /* IP2_28 [1] */
+                FN_D10,         0,
+                /* IP2_27 [1] */
+                FN_D9,          0,
+                /* IP2_26 [1] */
+                FN_D8,          0,
+                /* IP2_25 [1] */
+                FN_D7,          0,
+                /* IP2_24 [1] */
+                FN_D6,          0,
+                /* IP2_23 [1] */
+                FN_D5,          0,
+                /* IP2_22 [1] */
+                FN_D4,          0,
+                /* IP2_21 [1] */
+                FN_D3,          0,
+                /* IP2_20 [1] */
+                FN_D2,          0,
+                /* IP2_19 [1] */
+                FN_D1,          0,
+                /* IP2_18 [1] */
+                FN_D0,          0,
+                /* IP2_17 [1] */
+                FN_EX_WAIT0,    FN_PWM0_C,
+                /* IP2_16_14 [3] */
+                FN_DACK0,       0,      0,      FN_TX3_A,
+                FN_DRACK0,      0,      0,      0,
+                /* IP2_13_12 [2] */
+                FN_DREQ0_A,     0,      0,      FN_RX3_A,
+                /* IP2_11_9 [3] */
+                FN_SD1_DAT1_A,  FN_MMC_D1,      0,      FN_ATAWR0_A,
+                FN_EX_CS5,      FN_EX_WAIT2_A,  0,      0,
+                /* IP2_8_6 [3] */
+                FN_SD1_DAT0_A,  FN_MMC_D0,      0,      FN_ATARD0,
+                FN_EX_CS4,      FN_EX_WAIT1_A,  0,      0,
+                /* IP2_5_3 [3] */
+                FN_SD1_CMD_A,   FN_MMC_CMD,     0,      FN_ATACS10,
+                FN_EX_CS3,      0,              0,      0,
+                /* IP2_2_0 [3] */
+                FN_SD1_CLK_A,   FN_MMC_CLK,     0,      FN_ATACS00,
+                FN_EX_CS2,      0,              0,      0,
+                }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR3", 0xfffc002c, 32,
+                             1, 1, 1, 1, 1, 3, 3, 2,
+                             3, 3, 3, 2, 3, 3, 2) {
+                /* IP3_31 [1] */
+                FN_DU0_DR6,     FN_LCDOUT6,
+                /* IP3_30 [1] */
+                FN_DU0_DR5,     FN_LCDOUT5,
+                /* IP3_29 [1] */
+                FN_DU0_DR4,     FN_LCDOUT4,
+                /* IP3_28 [1] */
+                FN_DU0_DR3,     FN_LCDOUT3,
+                /* IP3_27 [1] */
+                FN_DU0_DR2,     FN_LCDOUT2,
+                /* IP3_26_24 [3] */
+                FN_SSI_WS4,             FN_DU0_DR1,     FN_LCDOUT1,     FN_AUDATA3,
+                FN_ARM_TRACEDATA_3,     FN_SCL3_C,      FN_ADICHS2,     FN_TS_SPSYNC0_B,
+                /* IP3_23_21 [3] */
+                FN_SSI_SCK4,            FN_DU0_DR0,     FN_LCDOUT0,     FN_AUDATA2,
+                FN_ARM_TRACEDATA_2,     FN_SDA3_C,      FN_ADICHS1,     FN_TS_SDEN0_B,
+                /* IP3_20_19 [2] */
+                FN_SD1_DAT3_B,  FN_HRTS0_A,     FN_RTS0,        0,
+                /* IP3_18_16 [3] */
+                FN_SD1_DAT2_B,  FN_HCTS0_A,     FN_CTS0,        0,
+                0,              0,              0,              0,
+                /* IP3_15_13 [3] */
+                FN_SD1_DAT1_B,  FN_HSCK0,       FN_SCK0,        FN_SCL3_B,
+                0,              0,              0,              0,
+                /* IP3_12_10 [3] */
+                FN_SD1_DAT0_B,  FN_HRX0_A,      FN_RX0_A,       0,
+                0,              0,              0,              0,
+                /* IP3_9_8 [2] */
+                FN_SD1_CLK_B,   FN_HTX0_A,      FN_TX0_A,       0,
+                /* IP3_7_5 [3] */
+                FN_SD1_CMD_B,   FN_SCIF_CLK,    FN_AUDIO_CLKOUT_B,      FN_CAN_CLK_B,
+                FN_SDA3_B,      0,              0,                      0,
+                /* IP3_4_2 [3] */
+                FN_MLB_DAT,     FN_TX5_B,       FN_SCL3_A,      FN_IRQ3_A,
+                FN_SDSELF_B,    0,              0,              0,
+                /* IP3_1_0 [2] */
+                FN_MLB_SIG,     FN_RX5_B,       FN_SDA3_A,      FN_IRQ2_A,
+                }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32,
+                             1, 2, 2, 2, 4, 4, 2, 2, 2, 2, 1, 1, 3, 3, 1) {
+                /* IP4_31 [1] */
+                0,      0,
+                /* IP4_30_29 [2] */
+                FN_VI0_R4_B,    FN_DU0_DB4,     FN_LCDOUT20,    0,
+                /* IP4_28_27 [2] */
+                FN_VI0_R3_B,    FN_DU0_DB3,     FN_LCDOUT19,    0,
+                /* IP4_26_25 [2] */
+                FN_VI0_R2_B,    FN_DU0_DB2,     FN_LCDOUT18,    0,
+                /* IP4_24_21 [4] */
+                FN_AUDIO_CLKC,  FN_VI0_R1_B,            FN_DU0_DB1,     FN_LCDOUT17,
+                FN_AUDATA7,     FN_ARM_TRACEDATA_7,     FN_GPSIN_A,     0,
+                FN_ADICS_SAMP,  FN_TS_SCK0_B,           0,              0,
+                0,              0,                      0,              0,
+                /* IP4_20_17 [4] */
+                FN_SSI_SCK2_B,  FN_VI0_R0_B,            FN_DU0_DB0,     FN_LCDOUT16,
+                FN_AUDATA6,     FN_ARM_TRACEDATA_6,     FN_GPSCLK_A,    FN_PWM0_A,
+                FN_ADICLK,      FN_TS_SDAT0_B,          0,              0,
+                0,              0,                      0,              0,
+                /* IP4_16_15 [2] */
+                FN_DU0_DG7,     FN_LCDOUT15,    FN_TX4_A,       0,
+                /* IP4_14_13 [2] */
+                FN_DU0_DG6,     FN_LCDOUT14,    FN_RX4_A,       0,
+                /* IP4_12_11 [2] */
+                FN_DU0_DG5,     FN_LCDOUT13,    FN_TX0_B,       0,
+                /* IP4_10_9 [2] */
+                FN_DU0_DG4,     FN_LCDOUT12,    FN_RX0_B,       0,
+                /* IP4_8 [1] */
+                FN_DU0_DG3,     FN_LCDOUT11,
+                /* IP4_7 [1] */
+                FN_DU0_DG2,     FN_LCDOUT10,
+                /* IP4_6_4 [3] */
+                FN_DU0_DG1,     FN_LCDOUT9,     FN_AUDATA5,     FN_ARM_TRACEDATA_5,
+                FN_RX1_D,       FN_CAN0_RX_A,   FN_ADIDATA,     0,
+                /* IP4_3_1 [3] */
+                FN_DU0_DG0,     FN_LCDOUT8,     FN_AUDATA4,     FN_ARM_TRACEDATA_4,
+                FN_TX1_D,       FN_CAN0_TX_A,   FN_ADICHS0,     0,
+                /* IP4_0 [1] */
+                FN_DU0_DR7,     FN_LCDOUT7,
+                }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32,
+                             1, 2, 3, 3, 2, 3, 3, 2, 1, 2, 2, 1, 1, 2, 2, 2) {
+
+                /* IP5_31 [1] */
+                0, 0,
+                /* IP5_30_29 [2] */
+                FN_SSI_SDATA7,  FN_HSPI_TX0_B,  FN_RX2_A,       FN_CAN0_RX_B,
+                /* IP5_28_26 [3] */
+                FN_SSI_SDATA8,  FN_SSI_SCK2_A,  FN_HSPI_CS0_B,  FN_TX2_A,
+                FN_CAN0_TX_B,   0,              0,              0,
+                /* IP5_25_23 [3] */
+                FN_SD1_WP_B,    FN_SSI_WS78,    FN_HSPI_CLK0_B, FN_RX1_B,
+                FN_CAN_CLK_D,   0,              0,              0,
+                /* IP5_22_21 [2] */
+                FN_SD1_CD_B,    FN_SSI_SCK78,   FN_HSPI_RX0_B,  FN_TX1_B,
+                /* IP5_20_18 [3] */
+                FN_SSI_WS1_A,           FN_DU0_CDE,     FN_QPOLB,       FN_AUDSYNC,
+                FN_ARM_TRACECTL,        FN_FMIN_D,      0,              0,
+                /* IP5_17_15 [3] */
+                FN_SSI_SCK1_A,          FN_DU0_DISP,    FN_QPOLA,       FN_AUDCK,
+                FN_ARM_TRACECLK,        FN_BPFCLK_D,    0,              0,
+                /* IP5_14_13 [2] */
+                FN_DU0_EXODDF_DU0_ODDF_DISP_CDE,        FN_QCPV_QDE,
+                FN_FMCLK_D,                             0,
+                /* IP5_12 [1] */
+                FN_DU0_EXVSYNC_DU0_VSYNC,       FN_QSTB_QHE,
+                /* IP5_11_10 [2] */
+                FN_SSI_WS2_B,   FN_DU0_EXHSYNC_DU0_HSYNC,
+                FN_QSTH_QHS,    0,
+                /* IP5_9_8 [2] */
+                FN_DU0_DOTCLKO_UT1,     FN_QSTVB_QVE,
+                FN_AUDIO_CLKOUT_A,      FN_REMOCON_C,
+                /* IP5_7 [1] */
+                FN_DU0_DOTCLKO_UT0,     FN_QCLK,
+                /* IP5_6 [1] */
+                FN_DU0_DOTCLKIN,        FN_QSTVA_QVS,
+                /* IP5_5_4 [2] */
+                FN_VI1_DATA11_B,        FN_DU0_DB7,     FN_LCDOUT23,    0,
+                /* IP5_3_2 [2] */
+                FN_VI1_DATA10_B,        FN_DU0_DB6,     FN_LCDOUT22,    0,
+                /* IP5_1_0 [2] */
+                FN_VI0_R5_B,            FN_DU0_DB5,     FN_LCDOUT21,    0,
+                }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32,
+                             2, 2, 2, 2, 2, 1, 2, 2, 1, 2,
+                             1, 2, 1, 1, 1, 1, 2, 3, 2) {
+                /* IP6_31_30 [2] */
+                FN_SD0_DAT2,    0,      FN_SUB_TDI,     0,
+                /* IP6_29_28 [2] */
+                FN_SD0_DAT1,    0,      FN_SUB_TCK,     0,
+                /* IP6_27_26 [2] */
+                FN_SD0_DAT0,    0,      FN_SUB_TMS,     0,
+                /* IP6_25_24 [2] */
+                FN_SD0_CMD,     0,      FN_SUB_TRST,    0,
+                /* IP6_23_22 [2] */
+                FN_SD0_CLK,     0,      FN_SUB_TDO,     0,
+                /* IP6_21 [1] */
+                FN_SSI_SDATA0,          FN_ARM_TRACEDATA_15,
+                /* IP6_20_19 [2] */
+                FN_SSI_SDATA1,          FN_ARM_TRACEDATA_14,
+                FN_SCL1_A,              FN_SCK2_A,
+                /* IP6_18_17 [2] */
+                FN_SSI_SDATA2,          FN_HSPI_CS2_A,
+                FN_ARM_TRACEDATA_13,    FN_SDA1_A,
+                /* IP6_16 [1] */
+                FN_SSI_WS012,           FN_ARM_TRACEDATA_12,
+                /* IP6_15_14 [2] */
+                FN_SSI_SCK012,          FN_ARM_TRACEDATA_11,
+                FN_TX0_D,               0,
+                /* IP6_13 [1] */
+                FN_SSI_SDATA3,          FN_ARM_TRACEDATA_10,
+                /* IP6_12_11 [2] */
+                FN_SSI_SDATA4,          FN_SSI_WS2_A,
+                FN_ARM_TRACEDATA_9,     0,
+                /* IP6_10 [1] */
+                FN_SSI_WS34,            FN_ARM_TRACEDATA_8,
+                /* IP6_9 [1] */
+                FN_SSI_SDATA5,          FN_RX0_D,
+                /* IP6_8 [1] */
+                FN_SSI_WS5,             FN_TX4_C,
+                /* IP6_7 [1] */
+                FN_SSI_SCK5,            FN_RX4_C,
+                /* IP6_6_5 [2] */
+                FN_SSI_SDATA6,          FN_HSPI_TX2_A,
+                FN_FMIN_B,              0,
+                /* IP6_4_2 [3] */
+                FN_SSI_WS6,             FN_HSPI_CLK2_A,
+                FN_BPFCLK_B,            FN_CAN1_RX_B,
+                0,      0,      0,      0,
+                /* IP6_1_0 [2] */
+                FN_SSI_SCK6,            FN_HSPI_RX2_A,
+                FN_FMCLK_B,             FN_CAN1_TX_B,
+                }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32,
+                             3, 4, 3, 1, 3, 3, 3, 3, 3, 2, 2, 2) {
+
+                /* IP7_31_29 [3] */
+                FN_VI0_HSYNC,   FN_SD2_CD_B,    FN_VI1_DATA2,   FN_DU1_DR2,
+                0,              FN_HSPI_CS1_A,  FN_RX3_B,       0,
+                /* IP7_28_25 [4] */
+                FN_VI0_FIELD,   FN_SD2_DAT3_B,  FN_VI0_R3_C,    FN_VI1_DATA1,
+                FN_DU1_DG7,     0,              FN_HSPI_CLK1_A, FN_TX4_B,
+                0,      0,      0,      0,
+                0,      0,      0,      0,
+                /* IP7_24_22 [3] */
+                FN_VI0_CLKENB,  FN_SD2_DAT2_B,  FN_VI1_DATA0,   FN_DU1_DG6,
+                0,              FN_HSPI_RX1_A,  FN_RX4_B,       0,
+                /* IP7_21 [1] */
+                FN_VI0_CLK,     FN_CAN_CLK_A,
+                /* IP7_20_18 [3] */
+                FN_TCLK0,       FN_HSCK1_A,     FN_FMIN_A,      0,
+                FN_IRQ2_C,      FN_CTS1_C,      FN_SPEEDIN,     0,
+                /* IP7_17_15 [3] */
+                FN_VI1_VSYNC,   FN_HSPI_TX0,    FN_HCTS1_A,     FN_BPFCLK_A,
+                0,              FN_TX1_C,       0,              0,
+                /* IP7_14_12 [3] */
+                FN_VI1_HSYNC,   FN_HSPI_RX0_A,  FN_HRTS1_A,     FN_FMCLK_A,
+                0,              FN_RX1_C,       0,              0,
+                /* IP7_11_9 [3] */
+                FN_VI1_FIELD,   FN_HSPI_CS0_A,  FN_HRX1_A,      0,
+                FN_SCK1_C,      0,              0,              0,
+                /* IP7_8_6 [3] */
+                FN_VI1_CLKENB,  FN_HSPI_CLK0_A, FN_HTX1_A,      0,
+                FN_RTS1_C,      0,              0,              0,
+                /* IP7_5_4 [2] */
+                FN_SD0_WP,      0,              FN_RX5_A,       0,
+                /* IP7_3_2 [2] */
+                FN_SD0_CD,      0,              FN_TX5_A,       0,
+                /* IP7_1_0 [2] */
+                FN_SD0_DAT3,    0,              FN_IRQ1_B,      0,
+                }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32,
+                             1, 1, 3, 3, 2, 3, 3, 2, 3, 2, 3, 3, 3) {
+                /* IP8_31 [1] */
+                0, 0,
+                /* IP8_30 [1] */
+                0, 0,
+                /* IP8_29_27 [3] */
+                FN_VI0_G3,      FN_SD2_CMD_B,   FN_VI1_DATA5,   FN_DU1_DR5,
+                0,              FN_HRX1_B,      0,              0,
+                /* IP8_26_24 [3] */
+                FN_VI0_G2,      FN_SD2_CLK_B,   FN_VI1_DATA4,   FN_DU1_DR4,
+                0,              FN_HTX1_B,      0,              0,
+                /* IP8_23_22 [2] */
+                FN_VI0_DATA7_VI0_G1,    FN_DU1_DB5,
+                FN_RTS1_A,              0,
+                /* IP8_21_19 [3] */
+                FN_VI0_DATA6_VI0_G0,    FN_DU1_DB4,
+                FN_CTS1_A,              FN_PWM5,
+                0,      0,      0,      0,
+                /* IP8_18_16 [3] */
+                FN_VI0_DATA5_VI0_B5,    FN_DU1_DB3,     FN_SCK1_A,      FN_PWM4,
+                0,                      FN_HSCK1_B,     0,              0,
+                /* IP8_15_14 [2] */
+                FN_VI0_DATA4_VI0_B4,    FN_DU1_DB2,     FN_RX1_A,       0,
+                /* IP8_13_11 [3] */
+                FN_VI0_DATA3_VI0_B3,    FN_DU1_DG5,     FN_TX1_A,       FN_TX0_C,
+                0,                       0,             0,              0,
+                /* IP8_10_9 [2] */
+                FN_VI0_DATA2_VI0_B2,    FN_DU1_DG4,     FN_RX0_C,       0,
+                /* IP8_8_6 [3] */
+                FN_VI0_DATA1_VI0_B1,    FN_DU1_DG3,     FN_IRQ3_B,      FN_TX3_D,
+                0,                       0,             0,              0,
+                /* IP8_5_3 [3] */
+                FN_VI0_DATA0_VI0_B0,    FN_DU1_DG2,     FN_IRQ2_B,      FN_RX3_D,
+                0,                       0,             0,              0,
+                /* IP8_2_0 [3] */
+                FN_VI0_VSYNC,           FN_SD2_WP_B,    FN_VI1_DATA3,   FN_DU1_DR3,
+                0,                      FN_HSPI_TX1_A,  FN_TX3_B,       0,
+                }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32,
+                             1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
+                /* IP9_31 [1] */
+                0, 0,
+                /* IP9_30 [1] */
+                0, 0,
+                /* IP9_29_27 [3] */
+                FN_VI1_DATA11_A,        FN_DU1_EXHSYNC_DU1_HSYNC,
+                FN_ETH_RXD1,            FN_FMIN_C,
+                0,                      FN_RX2_D,
+                FN_SCL2_C,              0,
+                /* IP9_26_24 [3] */
+                FN_VI1_DATA10_A,        FN_DU1_DOTCLKOUT,
+                FN_ETH_RXD0,            FN_BPFCLK_C,
+                0,                      FN_TX2_D,
+                FN_SDA2_C,              0,
+                /* IP9_23_21 [3] */
+                FN_VI0_R5_A,    0,              FN_ETH_RX_ER,   FN_FMCLK_C,
+                FN_IERX,        FN_RX2_C,       0,              0,
+                /* IP9_20_18 [3] */
+                FN_VI0_R4_A,    FN_ETH_TX_EN,   0,              0,
+                FN_IETX,        FN_TX2_C,       0,              0,
+                /* IP9_17_15 [3] */
+                FN_VI0_R3_A,    FN_ETH_CRS_DV,  0,              FN_IECLK,
+                FN_SCK2_C,      0,              0,              0,
+                /* IP9_14_12 [3] */
+                FN_VI0_R2_A,    FN_VI1_DATA9,   FN_DU1_DB7,     FN_ETH_TXD1,
+                0,              FN_PWM3,        0,              0,
+                /* IP9_11_9 [3] */
+                FN_VI0_R1_A,    FN_VI1_DATA8,   FN_DU1_DB6,     FN_ETH_TXD0,
+                0,              FN_PWM2,        FN_TCLK1,       0,
+                /* IP9_8_6 [3] */
+                FN_VI0_R0_A,    FN_VI1_CLK,     FN_ETH_REF_CLK, FN_DU1_DOTCLKIN,
+                0,              0,              0,              0,
+                /* IP9_5_3 [3] */
+                FN_VI0_G5,      FN_SD2_DAT1_B,  FN_VI1_DATA7,   FN_DU1_DR7,
+                0,              FN_HCTS1_B,     0,              0,
+                /* IP9_2_0 [3] */
+                FN_VI0_G4,      FN_SD2_DAT0_B,  FN_VI1_DATA6,   FN_DU1_DR6,
+                0,              FN_HRTS1_B,     0,              0,
+                }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR10", 0xfffc0048, 32,
+                             1, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 4, 3, 3, 3) {
+
+                /* IP10_31 [1] */
+                0, 0,
+                /* IP10_30 [1] */
+                0, 0,
+                /* IP10_29 [1] */
+                0, 0,
+                /* IP10_28 [1] */
+                0, 0,
+                /* IP10_27 [1] */
+                0, 0,
+                /* IP10_26 [1] */
+                0, 0,
+                /* IP10_25 [1] */
+                0, 0,
+                /* IP10_24_22 [3] */
+                FN_SD2_WP_A,    FN_VI1_DATA15,  FN_EX_WAIT2_B,  FN_DACK0_B,
+                FN_HSPI_TX2_B,  FN_CAN_CLK_C,   0,              0,
+                /* IP10_21_19 [3] */
+                FN_SD2_CD_A,    FN_VI1_DATA14,  FN_EX_WAIT1_B,  FN_DREQ0_B,
+                FN_HSPI_RX2_B,  FN_REMOCON_A,   0,              0,
+                /* IP10_18_16 [3] */
+                FN_SD2_DAT3_A,  FN_VI1_DATA13,  FN_DACK2_B,     FN_ATAG1,
+                FN_HSPI_CS2_B,  FN_GPSIN_B,     0,              0,
+                /* IP10_15_13 [3] */
+                FN_SD2_DAT2_A,  FN_VI1_DATA12,  FN_DREQ2_B,     FN_ATADIR1,
+                FN_HSPI_CLK2_B, FN_GPSCLK_B,    0,              0,
+                /* IP10_12_9 [4] */
+                FN_SD2_DAT1_A,  FN_DU1_CDE,     FN_ATACS11,     FN_DACK1_B,
+                FN_ETH_MAGIC,   FN_CAN1_TX_A,   0,              FN_PWM6,
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                /* IP10_8_6 [3] */
+                FN_SD2_DAT0_A,  FN_DU1_DISP,    FN_ATACS01,     FN_DREQ1_B,
+                FN_ETH_LINK,    FN_CAN1_RX_A,   0,              0,
+                /* IP10_5_3 [3] */
+                FN_SD2_CMD_A,   FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
+                FN_ATAWR1,      FN_ETH_MDIO,
+                FN_SCL1_B,      0,
+                0,              0,
+                /* IP10_2_0 [3] */
+                FN_SD2_CLK_A,   FN_DU1_EXVSYNC_DU1_VSYNC,
+                FN_ATARD1,      FN_ETH_MDC,
+                FN_SDA1_B,      0,
+                0,              0,
+                }
+        },
+        { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xfffc0050, 32,
+                             1, 1, 2, 2, 3, 2, 2, 1, 1, 1, 1, 2,
+                             1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
+
+                /* SEL 31  [1] */
+                0, 0,
+                /* SEL_30 (SCIF5) [1] */
+                FN_SEL_SCIF5_A,         FN_SEL_SCIF5_B,
+                /* SEL_29_28 (SCIF4) [2] */
+                FN_SEL_SCIF4_A,         FN_SEL_SCIF4_B,
+                FN_SEL_SCIF4_C,         0,
+                /* SEL_27_26 (SCIF3) [2] */
+                FN_SEL_SCIF3_A,         FN_SEL_SCIF3_B,
+                FN_SEL_SCIF3_C,         FN_SEL_SCIF3_D,
+                /* SEL_25_23 (SCIF2) [3] */
+                FN_SEL_SCIF2_A,         FN_SEL_SCIF2_B,
+                FN_SEL_SCIF2_C,         FN_SEL_SCIF2_D,
+                FN_SEL_SCIF2_E,         0,
+                0,                      0,
+                /* SEL_22_21 (SCIF1) [2] */
+                FN_SEL_SCIF1_A,         FN_SEL_SCIF1_B,
+                FN_SEL_SCIF1_C,         FN_SEL_SCIF1_D,
+                /* SEL_20_19 (SCIF0) [2] */
+                FN_SEL_SCIF0_A,         FN_SEL_SCIF0_B,
+                FN_SEL_SCIF0_C,         FN_SEL_SCIF0_D,
+                /* SEL_18 [1] */
+                0, 0,
+                /* SEL_17 (SSI2) [1] */
+                FN_SEL_SSI2_A,          FN_SEL_SSI2_B,
+                /* SEL_16 (SSI1) [1] */
+                FN_SEL_SSI1_A,          FN_SEL_SSI1_B,
+                /* SEL_15 (VI1) [1] */
+                FN_SEL_VI1_A,           FN_SEL_VI1_B,
+                /* SEL_14_13 (VI0) [2] */
+                FN_SEL_VI0_A,           FN_SEL_VI0_B,
+                FN_SEL_VI0_C,           FN_SEL_VI0_D,
+                /* SEL_12 [1] */
+                0, 0,
+                /* SEL_11 (SD2) [1] */
+                FN_SEL_SD2_A,           FN_SEL_SD2_B,
+                /* SEL_10 (SD1) [1] */
+                FN_SEL_SD1_A,           FN_SEL_SD1_B,
+                /* SEL_9 (IRQ3) [1] */
+                FN_SEL_IRQ3_A,          FN_SEL_IRQ3_B,
+                /* SEL_8_7 (IRQ2) [2] */
+                FN_SEL_IRQ2_A,          FN_SEL_IRQ2_B,
+                FN_SEL_IRQ2_C,          0,
+                /* SEL_6 (IRQ1) [1] */
+                FN_SEL_IRQ1_A,          FN_SEL_IRQ1_B,
+                /* SEL_5 [1] */
+                0, 0,
+                /* SEL_4 (DREQ2) [1] */
+                FN_SEL_DREQ2_A,         FN_SEL_DREQ2_B,
+                /* SEL_3 (DREQ1) [1] */
+                FN_SEL_DREQ1_A,         FN_SEL_DREQ1_B,
+                /* SEL_2 (DREQ0) [1] */
+                FN_SEL_DREQ0_A,         FN_SEL_DREQ0_B,
+                /* SEL_1 (WAIT2) [1] */
+                FN_SEL_WAIT2_A,         FN_SEL_WAIT2_B,
+                /* SEL_0 (WAIT1) [1] */
+                FN_SEL_WAIT1_A,         FN_SEL_WAIT1_B,
+                }
+        },
+        { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xfffc0054, 32,
+                             1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1,
+                             1, 1, 1, 2, 2, 2, 1, 1, 1, 1, 2, 2, 1) {
+
+                /* SEL_31 [1] */
+                0, 0,
+                /* SEL_30 [1] */
+                0, 0,
+                /* SEL_29 [1] */
+                0, 0,
+                /* SEL_28 [1] */
+                0, 0,
+                /* SEL_27 (CAN1) [1] */
+                FN_SEL_CAN1_A,          FN_SEL_CAN1_B,
+                /* SEL_26 (CAN0) [1] */
+                FN_SEL_CAN0_A,          FN_SEL_CAN0_B,
+                /* SEL_25_24 (CANCLK) [2] */
+                FN_SEL_CANCLK_A,        FN_SEL_CANCLK_B,
+                FN_SEL_CANCLK_C,        FN_SEL_CANCLK_D,
+                /* SEL_23 (HSCIF1) [1] */
+                FN_SEL_HSCIF1_A,        FN_SEL_HSCIF1_B,
+                /* SEL_22 (HSCIF0) [1] */
+                FN_SEL_HSCIF0_A,        FN_SEL_HSCIF0_B,
+                /* SEL_21 [1] */
+                0, 0,
+                /* SEL_20 [1] */
+                0, 0,
+                /* SEL_19 [1] */
+                0, 0,
+                /* SEL_18 [1] */
+                0, 0,
+                /* SEL_17 [1] */
+                0, 0,
+                /* SEL_16 [1] */
+                0, 0,
+                /* SEL_15 [1] */
+                0, 0,
+                /* SEL_14_13 (REMOCON) [2] */
+                FN_SEL_REMOCON_A,       FN_SEL_REMOCON_B,
+                FN_SEL_REMOCON_C,       0,
+                /* SEL_12_11 (FM) [2] */
+                FN_SEL_FM_A,            FN_SEL_FM_B,
+                FN_SEL_FM_C,            FN_SEL_FM_D,
+                /* SEL_10_9 (GPS) [2] */
+                FN_SEL_GPS_A,           FN_SEL_GPS_B,
+                FN_SEL_GPS_C,           0,
+                /* SEL_8 (TSIF0) [1] */
+                FN_SEL_TSIF0_A,         FN_SEL_TSIF0_B,
+                /* SEL_7 (HSPI2) [1] */
+                FN_SEL_HSPI2_A,         FN_SEL_HSPI2_B,
+                /* SEL_6 (HSPI1) [1] */
+                FN_SEL_HSPI1_A,         FN_SEL_HSPI1_B,
+                /* SEL_5 (HSPI0) [1] */
+                FN_SEL_HSPI0_A,         FN_SEL_HSPI0_B,
+                /* SEL_4_3 (I2C3) [2] */
+                FN_SEL_I2C3_A,          FN_SEL_I2C3_B,
+                FN_SEL_I2C3_C,          0,
+                /* SEL_2_1 (I2C2) [2] */
+                FN_SEL_I2C2_A,          FN_SEL_I2C2_B,
+                FN_SEL_I2C2_C,          0,
+                /* SEL_0 (I2C1) [1] */
+                FN_SEL_I2C1_A,          FN_SEL_I2C1_B,
+                }
+        },
+        { },
+};
+
+const struct sh_pfc_soc_info r8a7778_pinmux_info = {
+        .name = "r8a7778_pfc",
+
+        .unlock_reg = 0xfffc0000, /* PMMR */
+
+        .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+        .pins = pinmux_pins,
+        .nr_pins = ARRAY_SIZE(pinmux_pins),
+
+        .groups = pinmux_groups,
+        .nr_groups = ARRAY_SIZE(pinmux_groups),
+
+        .functions = pinmux_functions,
+        .nr_functions = ARRAY_SIZE(pinmux_functions),
+
+        .cfg_regs = pinmux_config_regs,
+
+        .gpio_data = pinmux_data,
+        .gpio_data_size = ARRAY_SIZE(pinmux_data),
+};
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
index 8cd90e7e945a..8e22ca6c1044 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
@@ -1,8 +1,9 @@
 /*
  * r8a7779 processor support - PFC hardware block
  *
- * Copyright (C) 2011  Renesas Solutions Corp.
+ * Copyright (C) 2011, 2013  Renesas Solutions Corp.
  * Copyright (C) 2011  Magnus Damm
+ * Copyright (C) 2013  Cogent Embedded, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -19,6 +20,7 @@
  */
 
 #include <linux/kernel.h>
+#include <linux/platform_data/gpio-rcar.h>
 
 #include "sh_pfc.h"
 
@@ -79,7 +81,7 @@
 #define _GP_PORT_ALL(bank, pin, name, sfx)      name##_##sfx
 
 #define _GP_GPIO(bank, pin, _name, sfx)                                 \
-        [(bank * 32) + pin] = {                                         \
+        [RCAR_GP_PIN(bank, pin)] = {                                    \
                 .name = __stringify(_name),                             \
                 .enum_id = _name##_DATA,                                \
         }
@@ -1472,9 +1474,12 @@ static struct sh_pfc_pin pinmux_pins[] = {
 /* - DU0 -------------------------------------------------------------------- */
 static const unsigned int du0_rgb666_pins[] = {
         /* R[7:2], G[7:2], B[7:2] */
-        188, 187, 186, 185, 184, 183,
-        194, 193, 192, 191, 190, 189,
-        200, 199, 198, 197, 196, 195,
+        RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 27), RCAR_GP_PIN(5, 26),
+        RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
+        RCAR_GP_PIN(6, 2),  RCAR_GP_PIN(6, 1),  RCAR_GP_PIN(6, 0),
+        RCAR_GP_PIN(5, 31), RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 29),
+        RCAR_GP_PIN(6, 8),  RCAR_GP_PIN(6, 7),  RCAR_GP_PIN(6, 6),
+        RCAR_GP_PIN(6, 5),  RCAR_GP_PIN(6, 4),  RCAR_GP_PIN(6, 3),
 };
 static const unsigned int du0_rgb666_mux[] = {
         DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
@@ -1486,9 +1491,14 @@ static const unsigned int du0_rgb666_mux[] = {
 };
 static const unsigned int du0_rgb888_pins[] = {
         /* R[7:0], G[7:0], B[7:0] */
-        188, 187, 186, 185, 184, 183, 24, 23,
-        194, 193, 192, 191, 190, 189, 26, 25,
-        200, 199, 198, 197, 196, 195, 28, 27,
+        RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 27), RCAR_GP_PIN(5, 26),
+        RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
+        RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 23), RCAR_GP_PIN(6, 2),
+        RCAR_GP_PIN(6, 1),  RCAR_GP_PIN(6, 0),  RCAR_GP_PIN(5, 31),
+        RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 29), RCAR_GP_PIN(0, 26),
+        RCAR_GP_PIN(0, 25), RCAR_GP_PIN(6, 8),  RCAR_GP_PIN(6, 7),
+        RCAR_GP_PIN(6, 6),  RCAR_GP_PIN(6, 5),  RCAR_GP_PIN(6, 4),
+        RCAR_GP_PIN(6, 3),  RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 27),
 };
 static const unsigned int du0_rgb888_mux[] = {
         DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
@@ -1500,28 +1510,28 @@ static const unsigned int du0_rgb888_mux[] = {
 };
 static const unsigned int du0_clk_in_pins[] = {
         /* CLKIN */
-        29,
+        RCAR_GP_PIN(0, 29),
 };
 static const unsigned int du0_clk_in_mux[] = {
         DU0_DOTCLKIN_MARK,
 };
 static const unsigned int du0_clk_out_0_pins[] = {
         /* CLKOUT */
-        180,
+        RCAR_GP_PIN(5, 20),
 };
 static const unsigned int du0_clk_out_0_mux[] = {
         DU0_DOTCLKOUT0_MARK,
 };
 static const unsigned int du0_clk_out_1_pins[] = {
         /* CLKOUT */
-        30,
+        RCAR_GP_PIN(0, 30),
 };
 static const unsigned int du0_clk_out_1_mux[] = {
         DU0_DOTCLKOUT1_MARK,
 };
 static const unsigned int du0_sync_0_pins[] = {
         /* VSYNC, HSYNC, DISP */
-        182, 181, 31,
+        RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 21), RCAR_GP_PIN(0, 31),
 };
 static const unsigned int du0_sync_0_mux[] = {
         DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK,
@@ -1529,7 +1539,7 @@ static const unsigned int du0_sync_0_mux[] = {
 };
 static const unsigned int du0_sync_1_pins[] = {
         /* VSYNC, HSYNC, DISP */
-        182, 181, 32,
+        RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 21), RCAR_GP_PIN(1, 0),
 };
 static const unsigned int du0_sync_1_mux[] = {
         DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK,
@@ -1537,14 +1547,14 @@ static const unsigned int du0_sync_1_mux[] = {
 };
 static const unsigned int du0_oddf_pins[] = {
         /* ODDF */
-        31,
+        RCAR_GP_PIN(0, 31),
 };
 static const unsigned int du0_oddf_mux[] = {
         DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK
 };
 static const unsigned int du0_cde_pins[] = {
         /* CDE */
-        33,
+        RCAR_GP_PIN(1, 1),
 };
 static const unsigned int du0_cde_mux[] = {
         DU0_CDE_MARK
@@ -1552,9 +1562,12 @@ static const unsigned int du0_cde_mux[] = {
 /* - DU1 -------------------------------------------------------------------- */
 static const unsigned int du1_rgb666_pins[] = {
         /* R[7:2], G[7:2], B[7:2] */
-        41, 40, 39, 38, 37, 36,
-        49, 48, 47, 46, 45, 44,
-        57, 56, 55, 54, 53, 52,
+        RCAR_GP_PIN(1, 9),  RCAR_GP_PIN(1, 8),  RCAR_GP_PIN(1, 7),
+        RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),  RCAR_GP_PIN(1, 4),
+        RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15),
+        RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12),
+        RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23),
+        RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 20),
 };
 static const unsigned int du1_rgb666_mux[] = {
         DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
@@ -1566,9 +1579,14 @@ static const unsigned int du1_rgb666_mux[] = {
 };
 static const unsigned int du1_rgb888_pins[] = {
         /* R[7:0], G[7:0], B[7:0] */
-        41, 40, 39, 38, 37, 36, 35, 34,
-        49, 48, 47, 46, 45, 44, 43, 32,
-        57, 56, 55, 54, 53, 52, 51, 50,
+        RCAR_GP_PIN(1, 9),  RCAR_GP_PIN(1, 8),  RCAR_GP_PIN(1, 7),
+        RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),  RCAR_GP_PIN(1, 4),
+        RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),  RCAR_GP_PIN(1, 17),
+        RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
+        RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 11),
+        RCAR_GP_PIN(1, 0),  RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 24),
+        RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
+        RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
 };
 static const unsigned int du1_rgb888_mux[] = {
         DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
@@ -1580,21 +1598,21 @@ static const unsigned int du1_rgb888_mux[] = {
 };
 static const unsigned int du1_clk_in_pins[] = {
         /* CLKIN */
-        58,
+        RCAR_GP_PIN(1, 26),
 };
 static const unsigned int du1_clk_in_mux[] = {
         DU1_DOTCLKIN_MARK,
 };
 static const unsigned int du1_clk_out_pins[] = {
         /* CLKOUT */
-        59,
+        RCAR_GP_PIN(1, 27),
 };
 static const unsigned int du1_clk_out_mux[] = {
         DU1_DOTCLKOUT_MARK,
 };
 static const unsigned int du1_sync_0_pins[] = {
         /* VSYNC, HSYNC, DISP */
-        61, 60, 62,
+        RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 30),
 };
 static const unsigned int du1_sync_0_mux[] = {
         DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
@@ -1602,7 +1620,7 @@ static const unsigned int du1_sync_0_mux[] = {
 };
 static const unsigned int du1_sync_1_pins[] = {
         /* VSYNC, HSYNC, DISP */
-        61, 60, 63,
+        RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 31),
 };
 static const unsigned int du1_sync_1_mux[] = {
         DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
@@ -1610,22 +1628,55 @@ static const unsigned int du1_sync_1_mux[] = {
 };
 static const unsigned int du1_oddf_pins[] = {
         /* ODDF */
-        62,
+        RCAR_GP_PIN(1, 30),
 };
 static const unsigned int du1_oddf_mux[] = {
         DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK
 };
 static const unsigned int du1_cde_pins[] = {
         /* CDE */
-        64,
+        RCAR_GP_PIN(2, 0),
 };
 static const unsigned int du1_cde_mux[] = {
         DU1_CDE_MARK
 };
+/* - Ether ------------------------------------------------------------------ */
+static const unsigned int ether_rmii_pins[] = {
+        /*
+         * ETH_TXD0, ETH_TXD1, ETH_TX_EN,  ETH_REFCLK,
+         * ETH_RXD0, ETH_RXD1, ETH_CRS_DV, ETH_RX_ER,
+         * ETH_MDIO, ETH_MDC
+         */
+        RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 18),
+        RCAR_GP_PIN(2, 26),
+        RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 17),
+        RCAR_GP_PIN(2, 19),
+        RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 28),
+};
+static const unsigned int ether_rmii_mux[] = {
+        ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK,  ETH_REFCLK_MARK,
+        ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_CRS_DV_MARK, ETH_RX_ER_MARK,
+        ETH_MDIO_MARK, ETH_MDC_MARK,
+};
+static const unsigned int ether_link_pins[] = {
+        /* ETH_LINK */
+        RCAR_GP_PIN(2, 24),
+};
+static const unsigned int ether_link_mux[] = {
+        ETH_LINK_MARK,
+};
+static const unsigned int ether_magic_pins[] = {
+        /* ETH_MAGIC */
+        RCAR_GP_PIN(2, 25),
+};
+static const unsigned int ether_magic_mux[] = {
+        ETH_MAGIC_MARK,
+};
 /* - HSPI0 ------------------------------------------------------------------ */
 static const unsigned int hspi0_pins[] = {
         /* CLK, CS, RX, TX */
-        150, 151, 153, 152,
+        RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 25),
+        RCAR_GP_PIN(4, 24),
 };
 static const unsigned int hspi0_mux[] = {
         HSPI_CLK0_MARK, HSPI_CS0_MARK, HSPI_RX0_MARK, HSPI_TX0_MARK,
@@ -1633,28 +1684,32 @@ static const unsigned int hspi0_mux[] = {
 /* - HSPI1 ------------------------------------------------------------------ */
 static const unsigned int hspi1_pins[] = {
         /* CLK, CS, RX, TX */
-        63, 58, 64, 62,
+        RCAR_GP_PIN(1, 31), RCAR_GP_PIN(1, 26), RCAR_GP_PIN(2, 0),
+        RCAR_GP_PIN(1, 30),
 };
 static const unsigned int hspi1_mux[] = {
         HSPI_CLK1_MARK, HSPI_CS1_MARK, HSPI_RX1_MARK, HSPI_TX1_MARK,
 };
 static const unsigned int hspi1_b_pins[] = {
         /* CLK, CS, RX, TX */
-        90, 91, 93, 92,
+        RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 29),
+        RCAR_GP_PIN(2, 28),
 };
 static const unsigned int hspi1_b_mux[] = {
         HSPI_CLK1_B_MARK, HSPI_CS1_B_MARK, HSPI_RX1_B_MARK, HSPI_TX1_B_MARK,
 };
 static const unsigned int hspi1_c_pins[] = {
         /* CLK, CS, RX, TX */
-        141, 142, 144, 143,
+        RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 16),
+        RCAR_GP_PIN(4, 15),
 };
 static const unsigned int hspi1_c_mux[] = {
         HSPI_CLK1_C_MARK, HSPI_CS1_C_MARK, HSPI_RX1_C_MARK, HSPI_TX1_C_MARK,
 };
 static const unsigned int hspi1_d_pins[] = {
         /* CLK, CS, RX, TX */
-        101, 102, 104, 103,
+        RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 8),
+        RCAR_GP_PIN(3, 7),
 };
 static const unsigned int hspi1_d_mux[] = {
         HSPI_CLK1_D_MARK, HSPI_CS1_D_MARK, HSPI_RX1_D_MARK, HSPI_TX1_D_MARK,
@@ -1662,14 +1717,16 @@ static const unsigned int hspi1_d_mux[] = {
 /* - HSPI2 ------------------------------------------------------------------ */
 static const unsigned int hspi2_pins[] = {
         /* CLK, CS, RX, TX */
-        9, 10, 11, 14,
+        RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
+        RCAR_GP_PIN(0, 14),
 };
 static const unsigned int hspi2_mux[] = {
         HSPI_CLK2_MARK, HSPI_CS2_MARK, HSPI_RX2_MARK, HSPI_TX2_MARK,
 };
 static const unsigned int hspi2_b_pins[] = {
         /* CLK, CS, RX, TX */
-        7, 13, 8, 6,
+        RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 8),
+        RCAR_GP_PIN(0, 6),
 };
 static const unsigned int hspi2_b_mux[] = {
         HSPI_CLK2_B_MARK, HSPI_CS2_B_MARK, HSPI_RX2_B_MARK, HSPI_TX2_B_MARK,
@@ -1677,56 +1734,56 @@ static const unsigned int hspi2_b_mux[] = {
 /* - INTC ------------------------------------------------------------------- */
 static const unsigned int intc_irq0_pins[] = {
         /* IRQ */
-        78,
+        RCAR_GP_PIN(2, 14),
 };
 static const unsigned int intc_irq0_mux[] = {
         IRQ0_MARK,
 };
 static const unsigned int intc_irq0_b_pins[] = {
         /* IRQ */
-        141,
+        RCAR_GP_PIN(4, 13),
 };
 static const unsigned int intc_irq0_b_mux[] = {
         IRQ0_B_MARK,
 };
 static const unsigned int intc_irq1_pins[] = {
         /* IRQ */
-        79,
+        RCAR_GP_PIN(2, 15),
 };
 static const unsigned int intc_irq1_mux[] = {
         IRQ1_MARK,
 };
 static const unsigned int intc_irq1_b_pins[] = {
         /* IRQ */
-        142,
+        RCAR_GP_PIN(4, 14),
 };
 static const unsigned int intc_irq1_b_mux[] = {
         IRQ1_B_MARK,
 };
 static const unsigned int intc_irq2_pins[] = {
         /* IRQ */
-        88,
+        RCAR_GP_PIN(2, 24),
 };
 static const unsigned int intc_irq2_mux[] = {
         IRQ2_MARK,
 };
 static const unsigned int intc_irq2_b_pins[] = {
         /* IRQ */
-        143,
+        RCAR_GP_PIN(4, 15),
 };
 static const unsigned int intc_irq2_b_mux[] = {
         IRQ2_B_MARK,
 };
 static const unsigned int intc_irq3_pins[] = {
         /* IRQ */
-        89,
+        RCAR_GP_PIN(2, 25),
 };
 static const unsigned int intc_irq3_mux[] = {
         IRQ3_MARK,
 };
 static const unsigned int intc_irq3_b_pins[] = {
         /* IRQ */
-        144,
+        RCAR_GP_PIN(4, 16),
 };
 static const unsigned int intc_irq3_b_mux[] = {
         IRQ3_B_MARK,
@@ -1734,56 +1791,56 @@ static const unsigned int intc_irq3_b_mux[] = {
 /* - LSBC ------------------------------------------------------------------- */
 static const unsigned int lbsc_cs0_pins[] = {
         /* CS */
-        13,
+        RCAR_GP_PIN(0, 13),
 };
 static const unsigned int lbsc_cs0_mux[] = {
         CS0_MARK,
 };
 static const unsigned int lbsc_cs1_pins[] = {
         /* CS */
-        14,
+        RCAR_GP_PIN(0, 14),
 };
 static const unsigned int lbsc_cs1_mux[] = {
         CS1_A26_MARK,
 };
 static const unsigned int lbsc_ex_cs0_pins[] = {
         /* CS */
-        15,
+        RCAR_GP_PIN(0, 15),
 };
 static const unsigned int lbsc_ex_cs0_mux[] = {
         EX_CS0_MARK,
 };
 static const unsigned int lbsc_ex_cs1_pins[] = {
         /* CS */
-        16,
+        RCAR_GP_PIN(0, 16),
 };
 static const unsigned int lbsc_ex_cs1_mux[] = {
         EX_CS1_MARK,
 };
 static const unsigned int lbsc_ex_cs2_pins[] = {
         /* CS */
-        17,
+        RCAR_GP_PIN(0, 17),
 };
 static const unsigned int lbsc_ex_cs2_mux[] = {
         EX_CS2_MARK,
 };
 static const unsigned int lbsc_ex_cs3_pins[] = {
         /* CS */
-        18,
+        RCAR_GP_PIN(0, 18),
 };
 static const unsigned int lbsc_ex_cs3_mux[] = {
         EX_CS3_MARK,
 };
 static const unsigned int lbsc_ex_cs4_pins[] = {
         /* CS */
-        19,
+        RCAR_GP_PIN(0, 19),
 };
 static const unsigned int lbsc_ex_cs4_mux[] = {
         EX_CS4_MARK,
 };
 static const unsigned int lbsc_ex_cs5_pins[] = {
         /* CS */
-        20,
+        RCAR_GP_PIN(0, 20),
 };
 static const unsigned int lbsc_ex_cs5_mux[] = {
         EX_CS5_MARK,
@@ -1791,21 +1848,24 @@ static const unsigned int lbsc_ex_cs5_mux[] = {
 /* - MMCIF ------------------------------------------------------------------ */
 static const unsigned int mmc0_data1_pins[] = {
         /* D[0] */
-        19,
+        RCAR_GP_PIN(0, 19),
 };
 static const unsigned int mmc0_data1_mux[] = {
         MMC0_D0_MARK,
 };
 static const unsigned int mmc0_data4_pins[] = {
         /* D[0:3] */
-        19, 20, 21, 2,
+        RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21),
+        RCAR_GP_PIN(0, 2),
 };
 static const unsigned int mmc0_data4_mux[] = {
         MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
 };
 static const unsigned int mmc0_data8_pins[] = {
         /* D[0:7] */
-        19, 20, 21, 2, 10, 11, 15, 16,
+        RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21),
+        RCAR_GP_PIN(0, 2),  RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
+        RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16),
 };
 static const unsigned int mmc0_data8_mux[] = {
         MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
@@ -1813,28 +1873,31 @@ static const unsigned int mmc0_data8_mux[] = {
 };
 static const unsigned int mmc0_ctrl_pins[] = {
         /* CMD, CLK */
-        18, 17,
+        RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 17),
 };
 static const unsigned int mmc0_ctrl_mux[] = {
         MMC0_CMD_MARK, MMC0_CLK_MARK,
 };
 static const unsigned int mmc1_data1_pins[] = {
         /* D[0] */
-        72,
+        RCAR_GP_PIN(2, 8),
 };
 static const unsigned int mmc1_data1_mux[] = {
         MMC1_D0_MARK,
 };
 static const unsigned int mmc1_data4_pins[] = {
         /* D[0:3] */
-        72, 73, 74, 75,
+        RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
+        RCAR_GP_PIN(2, 11),
 };
 static const unsigned int mmc1_data4_mux[] = {
         MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
 };
 static const unsigned int mmc1_data8_pins[] = {
         /* D[0:7] */
-        72, 73, 74, 75, 76, 77, 80, 81,
+        RCAR_GP_PIN(2, 8),  RCAR_GP_PIN(2, 9),  RCAR_GP_PIN(2, 10),
+        RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
+        RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
 };
 static const unsigned int mmc1_data8_mux[] = {
         MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
@@ -1842,7 +1905,7 @@ static const unsigned int mmc1_data8_mux[] = {
 };
 static const unsigned int mmc1_ctrl_pins[] = {
         /* CMD, CLK */
-        68, 65,
+        RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 1),
 };
 static const unsigned int mmc1_ctrl_mux[] = {
         MMC1_CMD_MARK, MMC1_CLK_MARK,
@@ -1850,84 +1913,84 @@ static const unsigned int mmc1_ctrl_mux[] = {
 /* - SCIF0 ------------------------------------------------------------------ */
 static const unsigned int scif0_data_pins[] = {
         /* RXD, TXD */
-        153, 152,
+        RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24),
 };
 static const unsigned int scif0_data_mux[] = {
         RX0_MARK, TX0_MARK,
 };
 static const unsigned int scif0_clk_pins[] = {
         /* SCK */
-        156,
+        RCAR_GP_PIN(4, 28),
 };
 static const unsigned int scif0_clk_mux[] = {
         SCK0_MARK,
 };
 static const unsigned int scif0_ctrl_pins[] = {
         /* RTS, CTS */
-        151, 150,
+        RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 22),
 };
 static const unsigned int scif0_ctrl_mux[] = {
         RTS0_TANS_MARK, CTS0_MARK,
 };
 static const unsigned int scif0_data_b_pins[] = {
         /* RXD, TXD */
-        20, 19,
+        RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
 };
 static const unsigned int scif0_data_b_mux[] = {
         RX0_B_MARK, TX0_B_MARK,
 };
 static const unsigned int scif0_clk_b_pins[] = {
         /* SCK */
-        33,
+        RCAR_GP_PIN(1, 1),
 };
 static const unsigned int scif0_clk_b_mux[] = {
         SCK0_B_MARK,
 };
 static const unsigned int scif0_ctrl_b_pins[] = {
         /* RTS, CTS */
-        18, 11,
+        RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 11),
 };
 static const unsigned int scif0_ctrl_b_mux[] = {
         RTS0_B_TANS_B_MARK, CTS0_B_MARK,
 };
 static const unsigned int scif0_data_c_pins[] = {
         /* RXD, TXD */
-        146, 147,
+        RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 19),
 };
 static const unsigned int scif0_data_c_mux[] = {
         RX0_C_MARK, TX0_C_MARK,
 };
 static const unsigned int scif0_clk_c_pins[] = {
         /* SCK */
-        145,
+        RCAR_GP_PIN(4, 17),
 };
 static const unsigned int scif0_clk_c_mux[] = {
         SCK0_C_MARK,
 };
 static const unsigned int scif0_ctrl_c_pins[] = {
         /* RTS, CTS */
-        149, 148,
+        RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
 };
 static const unsigned int scif0_ctrl_c_mux[] = {
         RTS0_C_TANS_C_MARK, CTS0_C_MARK,
 };
 static const unsigned int scif0_data_d_pins[] = {
         /* RXD, TXD */
-        43, 42,
+        RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10),
 };
 static const unsigned int scif0_data_d_mux[] = {
         RX0_D_MARK, TX0_D_MARK,
 };
 static const unsigned int scif0_clk_d_pins[] = {
         /* SCK */
-        50,
+        RCAR_GP_PIN(1, 18),
 };
 static const unsigned int scif0_clk_d_mux[] = {
         SCK0_D_MARK,
 };
 static const unsigned int scif0_ctrl_d_pins[] = {
         /* RTS, CTS */
-        51, 35,
+        RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 3),
 };
 static const unsigned int scif0_ctrl_d_mux[] = {
         RTS0_D_TANS_D_MARK, CTS0_D_MARK,
@@ -1935,63 +1998,63 @@ static const unsigned int scif0_ctrl_d_mux[] = {
 /* - SCIF1 ------------------------------------------------------------------ */
 static const unsigned int scif1_data_pins[] = {
         /* RXD, TXD */
-        149, 148,
+        RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
 };
 static const unsigned int scif1_data_mux[] = {
         RX1_MARK, TX1_MARK,
 };
 static const unsigned int scif1_clk_pins[] = {
         /* SCK */
-        145,
+        RCAR_GP_PIN(4, 17),
 };
 static const unsigned int scif1_clk_mux[] = {
         SCK1_MARK,
 };
 static const unsigned int scif1_ctrl_pins[] = {
         /* RTS, CTS */
-        147, 146,
+        RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),
 };
 static const unsigned int scif1_ctrl_mux[] = {
         RTS1_TANS_MARK, CTS1_MARK,
 };
 static const unsigned int scif1_data_b_pins[] = {
         /* RXD, TXD */
-        117, 114,
+        RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 18),
 };
 static const unsigned int scif1_data_b_mux[] = {
         RX1_B_MARK, TX1_B_MARK,
 };
 static const unsigned int scif1_clk_b_pins[] = {
         /* SCK */
-        113,
+        RCAR_GP_PIN(3, 17),
 };
 static const unsigned int scif1_clk_b_mux[] = {
         SCK1_B_MARK,
 };
 static const unsigned int scif1_ctrl_b_pins[] = {
         /* RTS, CTS */
-        115, 116,
+        RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
 };
 static const unsigned int scif1_ctrl_b_mux[] = {
         RTS1_B_TANS_B_MARK, CTS1_B_MARK,
 };
 static const unsigned int scif1_data_c_pins[] = {
         /* RXD, TXD */
-        67, 66,
+        RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
 };
 static const unsigned int scif1_data_c_mux[] = {
         RX1_C_MARK, TX1_C_MARK,
 };
 static const unsigned int scif1_clk_c_pins[] = {
         /* SCK */
-        86,
+        RCAR_GP_PIN(2, 22),
 };
 static const unsigned int scif1_clk_c_mux[] = {
         SCK1_C_MARK,
 };
 static const unsigned int scif1_ctrl_c_pins[] = {
         /* RTS, CTS */
-        69, 68,
+        RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
 };
 static const unsigned int scif1_ctrl_c_mux[] = {
         RTS1_C_TANS_C_MARK, CTS1_C_MARK,
@@ -1999,63 +2062,63 @@ static const unsigned int scif1_ctrl_c_mux[] = {
 /* - SCIF2 ------------------------------------------------------------------ */
 static const unsigned int scif2_data_pins[] = {
         /* RXD, TXD */
-        106, 105,
+        RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 9),
 };
 static const unsigned int scif2_data_mux[] = {
         RX2_MARK, TX2_MARK,
 };
 static const unsigned int scif2_clk_pins[] = {
         /* SCK */
-        107,
+        RCAR_GP_PIN(3, 11),
 };
 static const unsigned int scif2_clk_mux[] = {
         SCK2_MARK,
 };
 static const unsigned int scif2_data_b_pins[] = {
         /* RXD, TXD */
-        120, 119,
+        RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 23),
 };
 static const unsigned int scif2_data_b_mux[] = {
         RX2_B_MARK, TX2_B_MARK,
 };
 static const unsigned int scif2_clk_b_pins[] = {
         /* SCK */
-        118,
+        RCAR_GP_PIN(3, 22),
 };
 static const unsigned int scif2_clk_b_mux[] = {
         SCK2_B_MARK,
 };
 static const unsigned int scif2_data_c_pins[] = {
         /* RXD, TXD */
-        33, 31,
+        RCAR_GP_PIN(1, 1), RCAR_GP_PIN(0, 31),
 };
 static const unsigned int scif2_data_c_mux[] = {
         RX2_C_MARK, TX2_C_MARK,
 };
 static const unsigned int scif2_clk_c_pins[] = {
         /* SCK */
-        32,
+        RCAR_GP_PIN(1, 0),
 };
 static const unsigned int scif2_clk_c_mux[] = {
         SCK2_C_MARK,
 };
 static const unsigned int scif2_data_d_pins[] = {
         /* RXD, TXD */
-        64, 62,
+        RCAR_GP_PIN(2, 0), RCAR_GP_PIN(1, 30),
 };
 static const unsigned int scif2_data_d_mux[] = {
         RX2_D_MARK, TX2_D_MARK,
 };
 static const unsigned int scif2_clk_d_pins[] = {
         /* SCK */
-        63,
+        RCAR_GP_PIN(1, 31),
 };
 static const unsigned int scif2_clk_d_mux[] = {
         SCK2_D_MARK,
 };
 static const unsigned int scif2_data_e_pins[] = {
         /* RXD, TXD */
-        20, 19,
+        RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
 };
 static const unsigned int scif2_data_e_mux[] = {
         RX2_E_MARK, TX2_E_MARK,
@@ -2063,14 +2126,14 @@ static const unsigned int scif2_data_e_mux[] = {
 /* - SCIF3 ------------------------------------------------------------------ */
 static const unsigned int scif3_data_pins[] = {
         /* RXD, TXD */
-        137, 136,
+        RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 8),
 };
 static const unsigned int scif3_data_mux[] = {
         RX3_IRDA_RX_MARK, TX3_IRDA_TX_MARK,
 };
 static const unsigned int scif3_clk_pins[] = {
         /* SCK */
-        135,
+        RCAR_GP_PIN(4, 7),
 };
 static const unsigned int scif3_clk_mux[] = {
         SCK3_MARK,
@@ -2078,35 +2141,35 @@ static const unsigned int scif3_clk_mux[] = {
 
 static const unsigned int scif3_data_b_pins[] = {
         /* RXD, TXD */
-        64, 62,
+        RCAR_GP_PIN(2, 0), RCAR_GP_PIN(1, 30),
 };
 static const unsigned int scif3_data_b_mux[] = {
         RX3_B_IRDA_RX_B_MARK, TX3_B_IRDA_TX_B_MARK,
 };
 static const unsigned int scif3_data_c_pins[] = {
         /* RXD, TXD */
-        15, 12,
+        RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 12),
 };
 static const unsigned int scif3_data_c_mux[] = {
         RX3_C_IRDA_RX_C_MARK, TX3C_IRDA_TX_C_MARK,
 };
 static const unsigned int scif3_data_d_pins[] = {
         /* RXD, TXD */
-        30, 29,
+        RCAR_GP_PIN(0, 30), RCAR_GP_PIN(0, 29),
 };
 static const unsigned int scif3_data_d_mux[] = {
         RX3_D_IRDA_RX_D_MARK, TX3_D_IRDA_TX_D_MARK,
 };
 static const unsigned int scif3_data_e_pins[] = {
         /* RXD, TXD */
-        35, 34,
+        RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
 };
 static const unsigned int scif3_data_e_mux[] = {
         RX3_E_IRDA_RX_E_MARK, TX3_E_IRDA_TX_E_MARK,
 };
 static const unsigned int scif3_clk_e_pins[] = {
         /* SCK */
-        42,
+        RCAR_GP_PIN(1, 10),
 };
 static const unsigned int scif3_clk_e_mux[] = {
         SCK3_E_MARK,
@@ -2114,42 +2177,42 @@ static const unsigned int scif3_clk_e_mux[] = {
 /* - SCIF4 ------------------------------------------------------------------ */
 static const unsigned int scif4_data_pins[] = {
         /* RXD, TXD */
-        123, 122,
+        RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 26),
 };
 static const unsigned int scif4_data_mux[] = {
         RX4_MARK, TX4_MARK,
 };
 static const unsigned int scif4_clk_pins[] = {
         /* SCK */
-        121,
+        RCAR_GP_PIN(3, 25),
 };
 static const unsigned int scif4_clk_mux[] = {
         SCK4_MARK,
 };
 static const unsigned int scif4_data_b_pins[] = {
         /* RXD, TXD */
-        111, 110,
+        RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14),
 };
 static const unsigned int scif4_data_b_mux[] = {
         RX4_B_MARK, TX4_B_MARK,
 };
 static const unsigned int scif4_clk_b_pins[] = {
         /* SCK */
-        112,
+        RCAR_GP_PIN(3, 16),
 };
 static const unsigned int scif4_clk_b_mux[] = {
         SCK4_B_MARK,
 };
 static const unsigned int scif4_data_c_pins[] = {
         /* RXD, TXD */
-        22, 21,
+        RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 21),
 };
 static const unsigned int scif4_data_c_mux[] = {
         RX4_C_MARK, TX4_C_MARK,
 };
 static const unsigned int scif4_data_d_pins[] = {
         /* RXD, TXD */
-        69, 68,
+        RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
 };
 static const unsigned int scif4_data_d_mux[] = {
         RX4_D_MARK, TX4_D_MARK,
@@ -2157,56 +2220,56 @@ static const unsigned int scif4_data_d_mux[] = {
 /* - SCIF5 ------------------------------------------------------------------ */
 static const unsigned int scif5_data_pins[] = {
         /* RXD, TXD */
-        51, 50,
+        RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
 };
 static const unsigned int scif5_data_mux[] = {
         RX5_MARK, TX5_MARK,
 };
 static const unsigned int scif5_clk_pins[] = {
         /* SCK */
-        43,
+        RCAR_GP_PIN(1, 11),
 };
 static const unsigned int scif5_clk_mux[] = {
         SCK5_MARK,
 };
 static const unsigned int scif5_data_b_pins[] = {
         /* RXD, TXD */
-        18, 11,
+        RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 11),
 };
 static const unsigned int scif5_data_b_mux[] = {
         RX5_B_MARK, TX5_B_MARK,
 };
 static const unsigned int scif5_clk_b_pins[] = {
         /* SCK */
-        19,
+        RCAR_GP_PIN(0, 19),
 };
 static const unsigned int scif5_clk_b_mux[] = {
         SCK5_B_MARK,
 };
 static const unsigned int scif5_data_c_pins[] = {
         /* RXD, TXD */
-        24, 23,
+        RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 23),
 };
 static const unsigned int scif5_data_c_mux[] = {
         RX5_C_MARK, TX5_C_MARK,
 };
 static const unsigned int scif5_clk_c_pins[] = {
         /* SCK */
-        28,
+        RCAR_GP_PIN(0, 28),
 };
 static const unsigned int scif5_clk_c_mux[] = {
         SCK5_C_MARK,
 };
 static const unsigned int scif5_data_d_pins[] = {
         /* RXD, TXD */
-        8, 6,
+        RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 6),
 };
 static const unsigned int scif5_data_d_mux[] = {
         RX5_D_MARK, TX5_D_MARK,
 };
 static const unsigned int scif5_clk_d_pins[] = {
         /* SCK */
-        7,
+        RCAR_GP_PIN(0, 7),
 };
 static const unsigned int scif5_clk_d_mux[] = {
         SCK5_D_MARK,
@@ -2214,35 +2277,36 @@ static const unsigned int scif5_clk_d_mux[] = {
 /* - SDHI0 ------------------------------------------------------------------ */
 static const unsigned int sdhi0_data1_pins[] = {
         /* D0 */
-        117,
+        RCAR_GP_PIN(3, 21),
 };
 static const unsigned int sdhi0_data1_mux[] = {
         SD0_DAT0_MARK,
 };
 static const unsigned int sdhi0_data4_pins[] = {
         /* D[0:3] */
-        117, 118, 119, 120,
+        RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
+        RCAR_GP_PIN(3, 24),
 };
 static const unsigned int sdhi0_data4_mux[] = {
         SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
 };
 static const unsigned int sdhi0_ctrl_pins[] = {
         /* CMD, CLK */
-        114, 113,
+        RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 17),
 };
 static const unsigned int sdhi0_ctrl_mux[] = {
         SD0_CMD_MARK, SD0_CLK_MARK,
 };
 static const unsigned int sdhi0_cd_pins[] = {
         /* CD */
-        115,
+        RCAR_GP_PIN(3, 19),
 };
 static const unsigned int sdhi0_cd_mux[] = {
         SD0_CD_MARK,
 };
 static const unsigned int sdhi0_wp_pins[] = {
         /* WP */
-        116,
+        RCAR_GP_PIN(3, 20),
 };
 static const unsigned int sdhi0_wp_mux[] = {
         SD0_WP_MARK,
@@ -2250,35 +2314,36 @@ static const unsigned int sdhi0_wp_mux[] = {
 /* - SDHI1 ------------------------------------------------------------------ */
 static const unsigned int sdhi1_data1_pins[] = {
         /* D0 */
-        19,
+        RCAR_GP_PIN(0, 19),
 };
 static const unsigned int sdhi1_data1_mux[] = {
         SD1_DAT0_MARK,
 };
 static const unsigned int sdhi1_data4_pins[] = {
         /* D[0:3] */
-        19, 20, 21, 2,
+        RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21),
+        RCAR_GP_PIN(0, 2),
 };
 static const unsigned int sdhi1_data4_mux[] = {
         SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK,
 };
 static const unsigned int sdhi1_ctrl_pins[] = {
         /* CMD, CLK */
-        18, 17,
+        RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 17),
 };
 static const unsigned int sdhi1_ctrl_mux[] = {
         SD1_CMD_MARK, SD1_CLK_MARK,
 };
 static const unsigned int sdhi1_cd_pins[] = {
         /* CD */
-        10,
+        RCAR_GP_PIN(0, 10),
 };
 static const unsigned int sdhi1_cd_mux[] = {
         SD1_CD_MARK,
 };
 static const unsigned int sdhi1_wp_pins[] = {
         /* WP */
-        11,
+        RCAR_GP_PIN(0, 11),
 };
 static const unsigned int sdhi1_wp_mux[] = {
         SD1_WP_MARK,
@@ -2286,35 +2351,36 @@ static const unsigned int sdhi1_wp_mux[] = {
 /* - SDHI2 ------------------------------------------------------------------ */
 static const unsigned int sdhi2_data1_pins[] = {
         /* D0 */
-        97,
+        RCAR_GP_PIN(3, 1),
 };
 static const unsigned int sdhi2_data1_mux[] = {
         SD2_DAT0_MARK,
 };
 static const unsigned int sdhi2_data4_pins[] = {
         /* D[0:3] */
-        97, 98, 99, 100,
+        RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
+        RCAR_GP_PIN(3, 4),
 };
 static const unsigned int sdhi2_data4_mux[] = {
         SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
 };
 static const unsigned int sdhi2_ctrl_pins[] = {
         /* CMD, CLK */
-        102, 101,
+        RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 5),
 };
 static const unsigned int sdhi2_ctrl_mux[] = {
         SD2_CMD_MARK, SD2_CLK_MARK,
 };
 static const unsigned int sdhi2_cd_pins[] = {
         /* CD */
-        103,
+        RCAR_GP_PIN(3, 7),
 };
 static const unsigned int sdhi2_cd_mux[] = {
         SD2_CD_MARK,
 };
 static const unsigned int sdhi2_wp_pins[] = {
         /* WP */
-        104,
+        RCAR_GP_PIN(3, 8),
 };
 static const unsigned int sdhi2_wp_mux[] = {
         SD2_WP_MARK,
@@ -2322,35 +2388,36 @@ static const unsigned int sdhi2_wp_mux[] = {
 /* - SDHI3 ------------------------------------------------------------------ */
 static const unsigned int sdhi3_data1_pins[] = {
         /* D0 */
-        50,
+        RCAR_GP_PIN(1, 18),
 };
 static const unsigned int sdhi3_data1_mux[] = {
         SD3_DAT0_MARK,
 };
 static const unsigned int sdhi3_data4_pins[] = {
         /* D[0:3] */
-        50, 51, 52, 53,
+        RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 20),
+        RCAR_GP_PIN(1, 21),
 };
 static const unsigned int sdhi3_data4_mux[] = {
         SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK,
 };
 static const unsigned int sdhi3_ctrl_pins[] = {
         /* CMD, CLK */
-        35, 34,
+        RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
 };
 static const unsigned int sdhi3_ctrl_mux[] = {
         SD3_CMD_MARK, SD3_CLK_MARK,
 };
 static const unsigned int sdhi3_cd_pins[] = {
         /* CD */
-        62,
+        RCAR_GP_PIN(1, 30),
 };
 static const unsigned int sdhi3_cd_mux[] = {
         SD3_CD_MARK,
 };
 static const unsigned int sdhi3_wp_pins[] = {
         /* WP */
-        64,
+        RCAR_GP_PIN(2, 0),
 };
 static const unsigned int sdhi3_wp_mux[] = {
         SD3_WP_MARK,
@@ -2358,14 +2425,14 @@ static const unsigned int sdhi3_wp_mux[] = {
 /* - USB0 ------------------------------------------------------------------- */
 static const unsigned int usb0_pins[] = {
         /* PENC */
-        154,
+        RCAR_GP_PIN(4, 26),
 };
 static const unsigned int usb0_mux[] = {
         USB_PENC0_MARK,
 };
 static const unsigned int usb0_ovc_pins[] = {
         /* USB_OVC */
-        150
+        RCAR_GP_PIN(4, 22),
 };
 static const unsigned int usb0_ovc_mux[] = {
         USB_OVC0_MARK,
@@ -2373,14 +2440,14 @@ static const unsigned int usb0_ovc_mux[] = {
 /* - USB1 ------------------------------------------------------------------- */
 static const unsigned int usb1_pins[] = {
         /* PENC */
-        155,
+        RCAR_GP_PIN(4, 27),
 };
 static const unsigned int usb1_mux[] = {
         USB_PENC1_MARK,
 };
 static const unsigned int usb1_ovc_pins[] = {
         /* USB_OVC */
-        152,
+        RCAR_GP_PIN(4, 24),
 };
 static const unsigned int usb1_ovc_mux[] = {
         USB_OVC1_MARK,
@@ -2388,18 +2455,122 @@ static const unsigned int usb1_ovc_mux[] = {
 /* - USB2 ------------------------------------------------------------------- */
 static const unsigned int usb2_pins[] = {
         /* PENC */
-        156,
+        RCAR_GP_PIN(4, 28),
 };
 static const unsigned int usb2_mux[] = {
         USB_PENC2_MARK,
 };
 static const unsigned int usb2_ovc_pins[] = {
         /* USB_OVC */
-        125,
+        RCAR_GP_PIN(3, 29),
 };
 static const unsigned int usb2_ovc_mux[] = {
         USB_OVC2_MARK,
 };
+/* - VIN0 ------------------------------------------------------------------- */
+static const unsigned int vin0_data8_pins[] = {
+        /* D[0:7] */
+        RCAR_GP_PIN(2, 6),  RCAR_GP_PIN(2, 7),  RCAR_GP_PIN(2, 8),
+        RCAR_GP_PIN(2, 9),  RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
+        RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
+};
+static const unsigned int vin0_data8_mux[] = {
+        VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, VI0_DATA2_VI0_B2_MARK,
+        VI0_DATA3_VI0_B3_MARK, VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
+        VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
+};
+static const unsigned int vin0_clk_pins[] = {
+        /* CLK */
+        RCAR_GP_PIN(2, 1),
+};
+static const unsigned int vin0_clk_mux[] = {
+        VI0_CLK_MARK,
+};
+static const unsigned int vin0_sync_pins[] = {
+        /* HSYNC, VSYNC */
+        RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
+};
+static const unsigned int vin0_sync_mux[] = {
+        VI0_HSYNC_MARK, VI0_VSYNC_MARK,
+};
+/* - VIN1 ------------------------------------------------------------------- */
+static const unsigned int vin1_data8_pins[] = {
+        /* D[0:7] */
+        RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
+        RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
+        RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
+};
+static const unsigned int vin1_data8_mux[] = {
+        VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK, VI1_DATA2_VI1_B2_MARK,
+        VI1_DATA3_VI1_B3_MARK, VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
+        VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
+};
+static const unsigned int vin1_clk_pins[] = {
+        /* CLK */
+        RCAR_GP_PIN(2, 30),
+};
+static const unsigned int vin1_clk_mux[] = {
+        VI1_CLK_MARK,
+};
+static const unsigned int vin1_sync_pins[] = {
+        /* HSYNC, VSYNC */
+        RCAR_GP_PIN(2, 31), RCAR_GP_PIN(3, 0),
+};
+static const unsigned int vin1_sync_mux[] = {
+        VI1_HSYNC_MARK, VI1_VSYNC_MARK,
+};
+/* - VIN2 ------------------------------------------------------------------- */
+static const unsigned int vin2_data8_pins[] = {
+        /* D[0:7] */
+        RCAR_GP_PIN(1, 2),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 10),
+        RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
+        RCAR_GP_PIN(1, 31), RCAR_GP_PIN(2, 0),
+};
+static const unsigned int vin2_data8_mux[] = {
+        VI2_DATA0_VI2_B0_MARK, VI2_DATA1_VI2_B1_MARK, VI2_DATA2_VI2_B2_MARK,
+        VI2_DATA3_VI2_B3_MARK, VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
+        VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
+};
+static const unsigned int vin2_clk_pins[] = {
+        /* CLK */
+        RCAR_GP_PIN(1, 30),
+};
+static const unsigned int vin2_clk_mux[] = {
+        VI2_CLK_MARK,
+};
+static const unsigned int vin2_sync_pins[] = {
+        /* HSYNC, VSYNC */
+        RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 29),
+};
+static const unsigned int vin2_sync_mux[] = {
+        VI2_HSYNC_MARK, VI2_VSYNC_MARK,
+};
+/* - VIN3 ------------------------------------------------------------------- */
+static const unsigned int vin3_data8_pins[] = {
+        /* D[0:7] */
+        RCAR_GP_PIN(3, 9),  RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
+        RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
+        RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
+};
+static const unsigned int vin3_data8_mux[] = {
+        VI3_DATA0_MARK, VI3_DATA1_MARK, VI3_DATA2_MARK,
+        VI3_DATA3_MARK, VI3_DATA4_MARK, VI3_DATA5_MARK,
+        VI3_DATA6_MARK, VI3_DATA7_MARK,
+};
+static const unsigned int vin3_clk_pins[] = {
+        /* CLK */
+        RCAR_GP_PIN(2, 31),
+};
+static const unsigned int vin3_clk_mux[] = {
+        VI3_CLK_MARK,
+};
+static const unsigned int vin3_sync_pins[] = {
+        /* HSYNC, VSYNC */
+        RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 29),
+};
+static const unsigned int vin3_sync_mux[] = {
+        VI3_HSYNC_MARK, VI3_VSYNC_MARK,
+};
 
 static const struct sh_pfc_pin_group pinmux_groups[] = {
         SH_PFC_PIN_GROUP(du0_rgb666),
@@ -2419,6 +2590,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
         SH_PFC_PIN_GROUP(du1_sync_1),
         SH_PFC_PIN_GROUP(du1_oddf),
         SH_PFC_PIN_GROUP(du1_cde),
+        SH_PFC_PIN_GROUP(ether_rmii),
+        SH_PFC_PIN_GROUP(ether_link),
+        SH_PFC_PIN_GROUP(ether_magic),
         SH_PFC_PIN_GROUP(hspi0),
         SH_PFC_PIN_GROUP(hspi1),
         SH_PFC_PIN_GROUP(hspi1_b),
@@ -2527,6 +2701,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
         SH_PFC_PIN_GROUP(usb1_ovc),
         SH_PFC_PIN_GROUP(usb2),
         SH_PFC_PIN_GROUP(usb2_ovc),
+        SH_PFC_PIN_GROUP(vin0_data8),
+        SH_PFC_PIN_GROUP(vin0_clk),
+        SH_PFC_PIN_GROUP(vin0_sync),
+        SH_PFC_PIN_GROUP(vin1_data8),
+        SH_PFC_PIN_GROUP(vin1_clk),
+        SH_PFC_PIN_GROUP(vin1_sync),
+        SH_PFC_PIN_GROUP(vin2_data8),
+        SH_PFC_PIN_GROUP(vin2_clk),
+        SH_PFC_PIN_GROUP(vin2_sync),
+        SH_PFC_PIN_GROUP(vin3_data8),
+        SH_PFC_PIN_GROUP(vin3_clk),
+        SH_PFC_PIN_GROUP(vin3_sync),
 };
 
 static const char * const du0_groups[] = {
@@ -2552,6 +2738,12 @@ static const char * const du1_groups[] = {
         "du1_cde",
 };
 
+static const char * const ether_groups[] = {
+        "ether_rmii",
+        "ether_link",
+        "ether_magic",
+};
+
 static const char * const hspi0_groups[] = {
         "hspi0",
 };
@@ -2720,9 +2912,34 @@ static const char * const usb2_groups[] = {
         "usb2_ovc",
 };
 
+static const char * const vin0_groups[] = {
+        "vin0_data8",
+        "vin0_clk",
+        "vin0_sync",
+};
+
+static const char * const vin1_groups[] = {
+        "vin1_data8",
+        "vin1_clk",
+        "vin1_sync",
+};
+
+static const char * const vin2_groups[] = {
+        "vin2_data8",
+        "vin2_clk",
+        "vin2_sync",
+};
+
+static const char * const vin3_groups[] = {
+        "vin3_data8",
+        "vin3_clk",
+        "vin3_sync",
+};
+
 static const struct sh_pfc_function pinmux_functions[] = {
         SH_PFC_FUNCTION(du0),
         SH_PFC_FUNCTION(du1),
+        SH_PFC_FUNCTION(ether),
         SH_PFC_FUNCTION(hspi0),
         SH_PFC_FUNCTION(hspi1),
         SH_PFC_FUNCTION(hspi2),
@@ -2743,6 +2960,10 @@ static const struct sh_pfc_function pinmux_functions[] = {
         SH_PFC_FUNCTION(usb0),
         SH_PFC_FUNCTION(usb1),
         SH_PFC_FUNCTION(usb2),
+        SH_PFC_FUNCTION(vin0),
+        SH_PFC_FUNCTION(vin1),
+        SH_PFC_FUNCTION(vin2),
+        SH_PFC_FUNCTION(vin3),
 };
 
 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
@@ -3547,7 +3768,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
             /* SEL_SCIF [2] */
             FN_SEL_SCIF_0, FN_SEL_SCIF_1, FN_SEL_SCIF_2, FN_SEL_SCIF_3,
             /* SEL_CANCLK [2] */
-            FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2,
+            FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, 0,
             /* SEL_CAN0 [1] */
             FN_SEL_CAN0_0, FN_SEL_CAN0_1,
             /* SEL_HSCIF1 [1] */
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
new file mode 100644
index 000000000000..85d77a417c0e
--- /dev/null
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
@@ -0,0 +1,3835 @@
+/*
+ * R8A7790 processor support
+ *
+ * Copyright (C) 2013  Renesas Electronics Corporation
+ * Copyright (C) 2013  Magnus Damm
+ * Copyright (C) 2012  Renesas Solutions Corp.
+ * Copyright (C) 2012  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the
+ * License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <linux/kernel.h>
+#include <linux/platform_data/gpio-rcar.h>
+
+#include "core.h"
+#include "sh_pfc.h"
+
+#define PORT_GP_1(bank, pin, fn, sfx) fn(bank, pin, GP_##bank##_##pin, sfx)
+
+#define PORT_GP_32(bank, fn, sfx)                                       \
+        PORT_GP_1(bank, 0,  fn, sfx), PORT_GP_1(bank, 1,  fn, sfx),     \
+        PORT_GP_1(bank, 2,  fn, sfx), PORT_GP_1(bank, 3,  fn, sfx),     \
+        PORT_GP_1(bank, 4,  fn, sfx), PORT_GP_1(bank, 5,  fn, sfx),     \
+        PORT_GP_1(bank, 6,  fn, sfx), PORT_GP_1(bank, 7,  fn, sfx),     \
+        PORT_GP_1(bank, 8,  fn, sfx), PORT_GP_1(bank, 9,  fn, sfx),     \
+        PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx),     \
+        PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx),     \
+        PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx),     \
+        PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx),     \
+        PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx),     \
+        PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx),     \
+        PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx),     \
+        PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx),     \
+        PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx),     \
+        PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx),     \
+        PORT_GP_1(bank, 30, fn, sfx), PORT_GP_1(bank, 31, fn, sfx)
+
+#define PORT_GP_32_REV(bank, fn, sfx)                                   \
+        PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx),     \
+        PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx),     \
+        PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx),     \
+        PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx),     \
+        PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx),     \
+        PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx),     \
+        PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx),     \
+        PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx),     \
+        PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx),     \
+        PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx),     \
+        PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx),     \
+        PORT_GP_1(bank, 9,  fn, sfx), PORT_GP_1(bank, 8,  fn, sfx),     \
+        PORT_GP_1(bank, 7,  fn, sfx), PORT_GP_1(bank, 6,  fn, sfx),     \
+        PORT_GP_1(bank, 5,  fn, sfx), PORT_GP_1(bank, 4,  fn, sfx),     \
+        PORT_GP_1(bank, 3,  fn, sfx), PORT_GP_1(bank, 2,  fn, sfx),     \
+        PORT_GP_1(bank, 1,  fn, sfx), PORT_GP_1(bank, 0,  fn, sfx)
+
+#define CPU_ALL_PORT(fn, sfx)                                           \
+        PORT_GP_32(0, fn, sfx),                                         \
+        PORT_GP_32(1, fn, sfx),                                         \
+        PORT_GP_32(2, fn, sfx),                                         \
+        PORT_GP_32(3, fn, sfx),                                         \
+        PORT_GP_32(4, fn, sfx),                                         \
+        PORT_GP_32(5, fn, sfx)
+
+#define _GP_PORT_ALL(bank, pin, name, sfx)      name##_##sfx
+
+#define _GP_GPIO(bank, pin, _name, sfx)                                 \
+        [(bank * 32) + pin] = {                                         \
+                .name = __stringify(_name),                             \
+                .enum_id = _name##_DATA,                                \
+        }
+
+#define _GP_DATA(bank, pin, name, sfx)                                  \
+        PINMUX_DATA(name##_DATA, name##_FN)
+
+#define GP_ALL(str)             CPU_ALL_PORT(_GP_PORT_ALL, str)
+#define PINMUX_GPIO_GP_ALL()    CPU_ALL_PORT(_GP_GPIO, unused)
+#define PINMUX_DATA_GP_ALL()    CPU_ALL_PORT(_GP_DATA, unused)
+
+#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
+#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
+                                                          FN_##ipsr, FN_##fn)
+
+enum {
+        PINMUX_RESERVED = 0,
+
+        PINMUX_DATA_BEGIN,
+        GP_ALL(DATA),
+        PINMUX_DATA_END,
+
+        PINMUX_FUNCTION_BEGIN,
+        GP_ALL(FN),
+
+        /* GPSR0 */
+        FN_IP0_2_0, FN_IP0_5_3, FN_IP0_8_6, FN_IP0_11_9, FN_IP0_15_12,
+        FN_IP0_19_16, FN_IP0_22_20, FN_IP0_26_23, FN_IP0_30_27,
+        FN_IP1_3_0, FN_IP1_7_4, FN_IP1_11_8, FN_IP1_14_12,
+        FN_IP1_17_15, FN_IP1_21_18, FN_IP1_25_22, FN_IP1_27_26,
+        FN_IP1_29_28, FN_IP2_2_0, FN_IP2_5_3, FN_IP2_8_6, FN_IP2_11_9,
+        FN_IP2_14_12, FN_IP2_17_15, FN_IP2_21_18, FN_IP2_25_22,
+        FN_IP2_28_26, FN_IP3_3_0, FN_IP3_7_4, FN_IP3_11_8,
+        FN_IP3_14_12, FN_IP3_17_15,
+
+        /* GPSR1 */
+        FN_IP3_19_18, FN_IP3_22_20, FN_IP3_25_23, FN_IP3_28_26,
+        FN_IP3_31_29, FN_IP4_2_0, FN_IP4_5_3, FN_IP4_8_6, FN_IP4_11_9,
+        FN_IP4_14_12, FN_IP4_17_15, FN_IP4_20_18, FN_IP4_23_21,
+        FN_IP4_26_24, FN_IP4_29_27, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_9_6,
+        FN_IP5_12_10, FN_IP5_14_13, FN_IP5_17_15, FN_IP5_20_18,
+        FN_IP5_23_21, FN_IP5_26_24, FN_IP5_29_27, FN_IP6_2_0,
+        FN_IP6_5_3, FN_IP6_8_6, FN_IP6_10_9, FN_IP6_13_11,
+
+        /* GPSR2 */
+        FN_IP7_28_27, FN_IP7_30_29, FN_IP8_1_0, FN_IP8_3_2, FN_IP8_5_4,
+        FN_IP8_7_6, FN_IP8_9_8, FN_IP8_11_10, FN_IP8_13_12, FN_IP8_15_14,
+        FN_IP8_17_16, FN_IP8_19_18, FN_IP8_21_20, FN_IP8_23_22,
+        FN_IP8_25_24, FN_IP8_26, FN_IP8_27, FN_VI1_DATA7_VI1_B7,
+        FN_IP6_16_14, FN_IP6_19_17, FN_IP6_22_20, FN_IP6_25_23,
+        FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3, FN_IP7_7_6,
+        FN_IP7_9_8, FN_IP7_12_10, FN_IP7_15_13,
+
+        /* GPSR3 */
+        FN_IP8_28, FN_IP8_30_29, FN_IP9_1_0, FN_IP9_3_2, FN_IP9_5_4,
+        FN_IP9_7_6, FN_IP9_11_8, FN_IP9_15_12, FN_IP9_17_16, FN_IP9_19_18,
+        FN_IP9_21_20, FN_IP9_23_22, FN_IP9_25_24, FN_IP9_27_26,
+        FN_IP9_31_28, FN_IP10_3_0, FN_IP10_6_4, FN_IP10_10_7, FN_IP10_14_11,
+        FN_IP10_18_15, FN_IP10_22_19, FN_IP10_25_23, FN_IP10_29_26,
+        FN_IP11_3_0, FN_IP11_4, FN_IP11_6_5, FN_IP11_8_7, FN_IP11_10_9,
+        FN_IP11_12_11, FN_IP11_14_13, FN_IP11_17_15, FN_IP11_21_18,
+
+        /* GPSR4 */
+        FN_IP11_23_22, FN_IP11_26_24, FN_IP11_29_27, FN_IP11_31_30,
+        FN_IP12_1_0, FN_IP12_3_2, FN_IP12_5_4, FN_IP12_7_6, FN_IP12_10_8,
+        FN_IP12_13_11, FN_IP12_16_14, FN_IP12_19_17, FN_IP12_22_20,
+        FN_IP12_24_23, FN_IP12_27_25, FN_IP12_30_28, FN_IP13_2_0,
+        FN_IP13_6_3, FN_IP13_9_7, FN_IP13_12_10, FN_IP13_15_13,
+        FN_IP13_18_16, FN_IP13_22_19, FN_IP13_25_23, FN_IP13_28_26,
+        FN_IP13_30_29, FN_IP14_2_0, FN_IP14_5_3, FN_IP14_8_6, FN_IP14_11_9,
+        FN_IP14_15_12, FN_IP14_18_16,
+
+        /* GPSR5 */
+        FN_IP14_21_19, FN_IP14_24_22, FN_IP14_27_25, FN_IP14_30_28,
+        FN_IP15_2_0, FN_IP15_5_3, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_13_12,
+        FN_IP15_15_14, FN_IP15_17_16, FN_IP15_19_18, FN_IP15_22_20,
+        FN_IP15_25_23, FN_IP15_27_26, FN_IP15_29_28, FN_IP16_2_0,
+        FN_IP16_5_3, FN_USB0_PWEN, FN_USB0_OVC_VBUS, FN_IP16_6, FN_IP16_7,
+        FN_USB2_PWEN, FN_USB2_OVC, FN_AVS1, FN_AVS2, FN_DU_DOTCLKIN0,
+        FN_IP7_26_25, FN_DU_DOTCLKIN2, FN_IP7_18_16, FN_IP7_21_19, FN_IP7_24_22,
+
+        /* IPSR0 */
+        FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B,
+        FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5,
+        FN_VI0_G5_B, FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2,
+        FN_VI0_G6, FN_VI0_G6_B, FN_D3, FN_MSIOF3_TXD_B,
+        FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B, FN_D4,
+        FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4,
+        FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B, FN_D5,
+        FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5,
+        FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B, FN_D6,
+        FN_SCL2_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B,
+        FN_SCL2_CIS_C, FN_D7, FN_AD_DI_B, FN_SDA2_C,
+        FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_SDA2_CIS_C,
+        FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, FN_MII_TXD0,
+        FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,
+
+        /* IPSR1 */
+        FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, FN_MII_TXD1,
+        FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, FN_D10,
+        FN_SCIFA1_TXD_C, FN_AVB_TXD2, FN_MII_TXD2,
+        FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, FN_D11,
+        FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, FN_MII_TXD3,
+        FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3,
+        FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4,
+        FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4,
+        FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N,
+        FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5, FN_D14,
+        FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B,
+        FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6,
+        FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B,
+        FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7,
+        FN_A0, FN_PWM3, FN_A1, FN_PWM4,
+
+        /* IPSR2 */
+        FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, FN_A3,
+        FN_PWM6, FN_MSIOF1_SS2_B, FN_A4, FN_MSIOF1_TXD_B,
+        FN_TPU0TO0, FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1,
+        FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, FN_A7,
+        FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3,
+        FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4,
+        FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_VI2_DATA0_VI2_B0_B,
+        FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5,
+        FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_VI2_DATA1_VI2_B1_B,
+        FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6,
+        FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B,
+
+        /* IPSR3 */
+        FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0,
+        FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B,
+        FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1,
+        FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B,
+        FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2,
+        FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2,
+        FN_VI2_DATA5_VI2_B5_B, FN_A14, FN_SCIFB2_TXD_B,
+        FN_ATACS11_N, FN_MSIOF2_SS1, FN_A15, FN_SCIFB2_SCK_B,
+        FN_ATARD1_N, FN_MSIOF2_SS2, FN_A16, FN_ATAWR1_N,
+        FN_A17, FN_AD_DO_B, FN_ATADIR1_N, FN_A18,
+        FN_AD_CLK_B, FN_ATAG1_N, FN_A19, FN_AD_NCS_N_B,
+        FN_ATACS01_N, FN_EX_WAIT0_B, FN_A20, FN_SPCLK,
+        FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4,
+
+        /* IPSR4 */
+        FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5,
+        FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B,
+        FN_VI2_G6, FN_A23, FN_IO2, FN_VI1_G7,
+        FN_VI1_G7_B, FN_VI2_G7, FN_A24, FN_IO3,
+        FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB,
+        FN_VI2_CLKENB_B, FN_A25, FN_SSL, FN_VI1_G6,
+        FN_VI1_G6_B, FN_VI2_FIELD, FN_VI2_FIELD_B, FN_CS0_N,
+        FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B,
+        FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B,
+        FN_VI2_CLK, FN_VI2_CLK_B, FN_EX_CS0_N, FN_HRX1_B,
+        FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0, FN_HTX0_B,
+        FN_MSIOF0_SS1_B, FN_EX_CS1_N, FN_GPS_CLK,
+        FN_HCTS1_N_B, FN_VI1_FIELD, FN_VI1_FIELD_B,
+        FN_VI2_R1, FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B,
+        FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2,
+
+        /* IPSR5 */
+        FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B,
+        FN_VI2_R3, FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N,
+        FN_VI2_HSYNC_N, FN_SCL1, FN_VI2_HSYNC_N_B,
+        FN_INTC_EN0_N, FN_SCL1_CIS, FN_EX_CS5_N, FN_CAN0_RX,
+        FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N, FN_VI1_G2,
+        FN_VI1_G2_B, FN_VI2_R4, FN_SDA1, FN_INTC_EN1_N,
+        FN_SDA1_CIS, FN_BS_N, FN_IETX, FN_HTX1_B,
+        FN_CAN1_TX, FN_DRACK0, FN_IETX_C, FN_RD_N,
+        FN_CAN0_TX, FN_SCIFA0_SCK_B, FN_RD_WR_N, FN_VI1_G3,
+        FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
+        FN_INTC_IRQ4_N, FN_WE0_N, FN_IECLK, FN_CAN_CLK,
+        FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B,
+        FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
+        FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B,
+        FN_IERX_C, FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N,
+        FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B,
+        FN_MSIOF0_SCK_B, FN_DREQ0_N, FN_VI1_HSYNC_N,
+        FN_VI1_HSYNC_N_B, FN_VI2_R7, FN_SSI_SCK78_C,
+        FN_SSI_WS78_B,
+
+        /* IPSR6 */
+        FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
+        FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C,
+        FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
+        FN_SSI_SDATA7_C, FN_SSI_SCK78_B, FN_DACK1, FN_IRQ1,
+        FN_INTC_IRQ1_N, FN_SSI_WS6_B, FN_SSI_SDATA8_C,
+        FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B,
+        FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
+        FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B,
+        FN_ETH_CRS_DV, FN_RMII_CRS_DV, FN_STP_ISCLK_0_B,
+        FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_SCL2_E,
+        FN_SCL2_CIS_E, FN_ETH_RX_ER, FN_RMII_RX_ER,
+        FN_STP_ISD_0_B, FN_TS_SPSYNC0_D, FN_GLO_Q1_C,
+        FN_SDA2_E, FN_SDA2_CIS_E, FN_ETH_RXD0, FN_RMII_RXD0,
+        FN_STP_ISEN_0_B, FN_TS_SDAT0_D, FN_GLO_I0_C,
+        FN_SCIFB1_SCK_G, FN_SCK1_E, FN_ETH_RXD1,
+        FN_RMII_RXD1, FN_HRX0_E, FN_STP_ISSYNC_0_B,
+        FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G,
+        FN_RX1_E, FN_ETH_LINK, FN_RMII_LINK, FN_HTX0_E,
+        FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E,
+        FN_ETH_REF_CLK, FN_RMII_REF_CLK, FN_HCTS0_N_E,
+        FN_STP_IVCXO27_1_B, FN_HRX0_F,
+
+        /* IPSR7 */
+        FN_ETH_MDIO, FN_RMII_MDIO, FN_HRTS0_N_E,
+        FN_SIM0_D_C, FN_HCTS0_N_F, FN_ETH_TXD1,
+        FN_RMII_TXD1, FN_HTX0_F, FN_BPFCLK_G, FN_RDS_CLK_F,
+        FN_ETH_TX_EN, FN_RMII_TX_EN, FN_SIM0_CLK_C,
+        FN_HRTS0_N_F, FN_ETH_MAGIC, FN_RMII_MAGIC,
+        FN_SIM0_RST_C, FN_ETH_TXD0, FN_RMII_TXD0,
+        FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, FN_GLO_SCLK_C,
+        FN_ETH_MDC, FN_RMII_MDC, FN_STP_ISD_1_B,
+        FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, FN_PWM0,
+        FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
+        FN_GLO_SS_C, FN_PWM1, FN_SCIFA2_TXD_C,
+        FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, FN_GLO_RFON_C,
+        FN_PCMOE_N, FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C,
+        FN_PCMWE_N, FN_IECLK_C, FN_DU1_DOTCLKIN,
+        FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, FN_VI0_CLK,
+        FN_ATACS00_N, FN_AVB_RXD1, FN_MII_RXD1,
+        FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2,
+        FN_MII_RXD2,
+
+        /* IPSR8 */
+        FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3,
+        FN_MII_RXD3, FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N,
+        FN_AVB_RXD4, FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N,
+        FN_AVB_RXD5, FN_VI0_DATA4_VI0_B4, FN_ATAG0_N,
+        FN_AVB_RXD6, FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1,
+        FN_AVB_RXD7, FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER,
+        FN_MII_RX_ER, FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK,
+        FN_MII_RX_CLK, FN_VI1_CLK, FN_AVB_RX_DV,
+        FN_MII_RX_DV, FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D,
+        FN_AVB_CRS, FN_MII_CRS, FN_VI1_DATA1_VI1_B1,
+        FN_SCIFA1_RXD_D, FN_AVB_MDC, FN_MII_MDC,
+        FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO,
+        FN_MII_MDIO, FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D,
+        FN_AVB_GTX_CLK, FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
+        FN_AVB_MAGIC, FN_MII_MAGIC, FN_VI1_DATA5_VI1_B5,
+        FN_AVB_PHY_INT, FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,
+        FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, FN_SD0_CMD,
+        FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B,
+
+        /* IPSR9 */
+        FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B,
+        FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B,
+        FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B,
+        FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B,
+        FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
+        FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_SCL1_B,
+        FN_SCL1_CIS_B, FN_VI2_DATA6_VI2_B6_B, FN_SD0_WP,
+        FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
+        FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_SDA1_B,
+        FN_SDA1_CIS_B, FN_VI2_DATA7_VI2_B7_B, FN_SD1_CLK,
+        FN_AVB_TX_EN, FN_MII_TX_EN, FN_SD1_CMD,
+        FN_AVB_TX_ER, FN_MII_TX_ER, FN_SCIFB0_SCK_B,
+        FN_SD1_DAT0, FN_AVB_TX_CLK, FN_MII_TX_CLK,
+        FN_SCIFB0_RXD_B, FN_SD1_DAT1, FN_AVB_LINK,
+        FN_MII_LINK, FN_SCIFB0_TXD_B, FN_SD1_DAT2,
+        FN_AVB_COL, FN_MII_COL, FN_SCIFB0_CTS_N_B,
+        FN_SD1_DAT3, FN_AVB_RXD0, FN_MII_RXD0,
+        FN_SCIFB0_RTS_N_B, FN_SD1_CD, FN_MMC1_D6,
+        FN_TS_SDEN1, FN_USB1_EXTP, FN_GLO_SS, FN_VI0_CLK_B,
+        FN_SCL2_D, FN_SCL2_CIS_D, FN_SIM0_CLK_B,
+        FN_VI3_CLK_B,
+
+        /* IPSR10 */
+        FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
+        FN_GLO_RFON, FN_VI1_CLK_B, FN_SDA2_D, FN_SDA2_CIS_D,
+        FN_SIM0_D_B, FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK,
+        FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B,
+        FN_VI3_DATA0_B, FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D,
+        FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D,
+        FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B,
+        FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B,
+        FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D,
+        FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B,
+        FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, FN_RDS_DATA,
+        FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
+        FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
+        FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, FN_RDS_CLK,
+        FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
+        FN_GLO_Q0_B, FN_VI3_DATA4_B, FN_SD2_DAT3,
+        FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
+        FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B,
+        FN_VI3_DATA5_B, FN_SD2_CD, FN_MMC0_D4,
+        FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
+        FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
+        FN_GLO_I0_B, FN_VI3_DATA6_B,
+
+        /* IPSR11 */
+        FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
+        FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
+        FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B,
+        FN_SD3_CLK, FN_MMC1_CLK, FN_SD3_CMD, FN_MMC1_CMD,
+        FN_MTS_N, FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N,
+        FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, FN_SD3_DAT2,
+        FN_MMC1_D2, FN_SDATA, FN_SD3_DAT3, FN_MMC1_D3,
+        FN_SCKZ, FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
+        FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, FN_SD3_WP,
+        FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
+        FN_RDS_DATA_B, FN_FMIN_E, FN_RDS_DATA_D, FN_FMIN_F,
+        FN_RDS_DATA_E, FN_MLB_CLK, FN_SCL2_B, FN_SCL2_CIS_B,
+        FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_SDA2_B,
+        FN_SDA2_CIS_B, FN_MLB_DAT, FN_SPV_EVEN,
+        FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
+        FN_RDS_CLK_B, FN_SSI_SCK0129, FN_CAN_CLK_B,
+        FN_MOUT0,
+
+        /* IPSR12 */
+        FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1,
+        FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2,
+        FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5,
+        FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6,
+        FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK,
+        FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, FN_SSI_WS34,
+        FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC,
+        FN_CAN_STEP0, FN_SSI_SDATA3, FN_STP_ISCLK_0,
+        FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK,
+        FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N,
+        FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0,
+        FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N,
+        FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1,
+        FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD,
+        FN_CAN_DEBUGOUT2, FN_SSI_SCK5, FN_SCIFB1_SCK,
+        FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS,
+        FN_CAN_DEBUGOUT3, FN_SSI_WS5, FN_SCIFB1_RXD,
+        FN_IECLK_B, FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE,
+        FN_CAN_DEBUGOUT4,
+
+        /* IPSR13 */
+        FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
+        FN_LCDOUT2, FN_CAN_DEBUGOUT5, FN_SSI_SCK6,
+        FN_SCIFB1_CTS_N, FN_BPFCLK_D, FN_RDS_CLK_C,
+        FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6,
+        FN_BPFCLK_F, FN_RDS_CLK_E, FN_SSI_WS6,
+        FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4,
+        FN_LCDOUT4, FN_CAN_DEBUGOUT7, FN_SSI_SDATA6,
+        FN_FMIN_D, FN_RDS_DATA_C, FN_DU2_DR5, FN_LCDOUT5,
+        FN_CAN_DEBUGOUT8, FN_SSI_SCK78, FN_STP_IVCXO27_1,
+        FN_SCK1, FN_SCIFA1_SCK, FN_DU2_DR6, FN_LCDOUT6,
+        FN_CAN_DEBUGOUT9, FN_SSI_WS78, FN_STP_ISCLK_1,
+        FN_SCIFB2_SCK, FN_SCIFA2_CTS_N, FN_DU2_DR7,
+        FN_LCDOUT7, FN_CAN_DEBUGOUT10, FN_SSI_SDATA7,
+        FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N,
+        FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11,
+        FN_BPFCLK_E, FN_RDS_CLK_D, FN_SSI_SDATA7_B,
+        FN_FMIN_G, FN_RDS_DATA_F, FN_SSI_SDATA8,
+        FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C,
+        FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, FN_SSI_SDATA9,
+        FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1,
+        FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, FN_AUDIO_CLKA,
+        FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14,
+
+        /* IPSR14 */
+        FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D,
+        FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15,
+        FN_REMOCON, FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0,
+        FN_MSIOF3_SS2, FN_DU2_DG2, FN_LCDOUT10, FN_SDA1_C,
+        FN_SDA1_CIS_C, FN_SCIFA0_RXD, FN_HRX1, FN_RX0,
+        FN_DU2_DR0, FN_LCDOUT0, FN_SCIFA0_TXD, FN_HTX1,
+        FN_TX0, FN_DU2_DR1, FN_LCDOUT1, FN_SCIFA0_CTS_N,
+        FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, FN_DU2_DG3,
+        FN_LCDOUT11, FN_PWM0_B, FN_SCL1_C, FN_SCL1_CIS_C,
+        FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N_TANS,
+        FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B,
+        FN_SCIFA1_RXD, FN_AD_DI, FN_RX1,
+        FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE,
+        FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1,
+        FN_LCDOUT9, FN_SCIFA1_CTS_N, FN_AD_CLK,
+        FN_CTS1_N, FN_MSIOF3_RXD, FN_DU0_DOTCLKOUT, FN_QCLK,
+        FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N_TANS,
+        FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE,
+        FN_HRTS0_N_C,
+
+        /* IPSR15 */
+        FN_SCIFA2_SCK, FN_FMCLK, FN_MSIOF3_SCK, FN_DU2_DG7,
+        FN_LCDOUT15, FN_SCIF_CLK_B, FN_SCIFA2_RXD, FN_FMIN,
+        FN_DU2_DB0, FN_LCDOUT16, FN_SCL2, FN_SCL2_CIS,
+        FN_SCIFA2_TXD, FN_BPFCLK, FN_DU2_DB1, FN_LCDOUT17,
+        FN_SDA2, FN_SDA2_CIS, FN_HSCK0, FN_TS_SDEN0,
+        FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C, FN_HRX0,
+        FN_DU2_DB2, FN_LCDOUT18, FN_HTX0, FN_DU2_DB3,
+        FN_LCDOUT19, FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4,
+        FN_LCDOUT20, FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5,
+        FN_LCDOUT21, FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK,
+        FN_DU2_DB6, FN_LCDOUT22, FN_MSIOF0_SYNC, FN_TS_SCK0,
+        FN_SSI_SCK2, FN_ADIDATA, FN_DU2_DB7, FN_LCDOUT23,
+        FN_SCIFA2_RXD_B, FN_MSIOF0_SS1, FN_ADICHS0,
+        FN_DU2_DG5, FN_LCDOUT13, FN_MSIOF0_TXD, FN_ADICHS1,
+        FN_DU2_DG6, FN_LCDOUT14,
+
+        /* IPSR16 */
+        FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2,
+        FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B,
+        FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2,
+        FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_HRX0_C,
+        FN_USB1_PWEN, FN_AUDIO_CLKOUT_D, FN_USB1_OVC,
+        FN_TCLK1_B,
+
+        FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
+        FN_SEL_SCIF1_4,
+        FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2,
+        FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2,
+        FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
+        FN_SEL_SCIFB1_4,
+        FN_SEL_SCIFB1_5, FN_SEL_SCIFB1_6,
+        FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA1_3,
+        FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
+        FN_SEL_SCFA_0, FN_SEL_SCFA_1,
+        FN_SEL_SOF1_0, FN_SEL_SOF1_1,
+        FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2,
+        FN_SEL_SSI6_0, FN_SEL_SSI6_1,
+        FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2,
+        FN_SEL_VI3_0, FN_SEL_VI3_1,
+        FN_SEL_VI2_0, FN_SEL_VI2_1,
+        FN_SEL_VI1_0, FN_SEL_VI1_1,
+        FN_SEL_VI0_0, FN_SEL_VI0_1,
+        FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2,
+        FN_SEL_LBS_0, FN_SEL_LBS_1,
+        FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
+        FN_SEL_SOF3_0, FN_SEL_SOF3_1,
+        FN_SEL_SOF0_0, FN_SEL_SOF0_1,
+
+        FN_SEL_TMU1_0, FN_SEL_TMU1_1,
+        FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
+        FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
+        FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
+        FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
+        FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2,
+        FN_SEL_CAN1_0, FN_SEL_CAN1_1,
+        FN_SEL_ADI_0, FN_SEL_ADI_1,
+        FN_SEL_SSP_0, FN_SEL_SSP_1,
+        FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
+        FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6,
+        FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, FN_SEL_HSCIF0_3,
+        FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5,
+        FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2,
+        FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2,
+        FN_SEL_RDS_3, FN_SEL_RDS_4, FN_SEL_RDS_5,
+        FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2,
+        FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2,
+
+        FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
+        FN_SEL_IIC0_0, FN_SEL_IIC0_1,
+        FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
+        FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
+        FN_SEL_IIC2_4,
+        FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2,
+        FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
+        FN_SEL_I2C2_4,
+        FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2,
+        PINMUX_FUNCTION_END,
+
+        PINMUX_MARK_BEGIN,
+
+        VI1_DATA7_VI1_B7_MARK,
+
+        USB0_PWEN_MARK, USB0_OVC_VBUS_MARK,
+        USB2_PWEN_MARK, USB2_OVC_MARK, AVS1_MARK, AVS2_MARK,
+        DU_DOTCLKIN0_MARK, DU_DOTCLKIN2_MARK,
+
+        D0_MARK, MSIOF3_SCK_B_MARK, VI3_DATA0_MARK, VI0_G4_MARK, VI0_G4_B_MARK,
+        D1_MARK, MSIOF3_SYNC_B_MARK, VI3_DATA1_MARK, VI0_G5_MARK,
+        VI0_G5_B_MARK, D2_MARK, MSIOF3_RXD_B_MARK, VI3_DATA2_MARK,
+        VI0_G6_MARK, VI0_G6_B_MARK, D3_MARK, MSIOF3_TXD_B_MARK,
+        VI3_DATA3_MARK, VI0_G7_MARK, VI0_G7_B_MARK, D4_MARK,
+        SCIFB1_RXD_F_MARK, SCIFB0_RXD_C_MARK, VI3_DATA4_MARK,
+        VI0_R0_MARK, VI0_R0_B_MARK, RX0_B_MARK, D5_MARK,
+        SCIFB1_TXD_F_MARK, SCIFB0_TXD_C_MARK, VI3_DATA5_MARK,
+        VI0_R1_MARK, VI0_R1_B_MARK, TX0_B_MARK, D6_MARK,
+        SCL2_C_MARK, VI3_DATA6_MARK, VI0_R2_MARK, VI0_R2_B_MARK,
+        SCL2_CIS_C_MARK, D7_MARK, AD_DI_B_MARK, SDA2_C_MARK,
+        VI3_DATA7_MARK, VI0_R3_MARK, VI0_R3_B_MARK, SDA2_CIS_C_MARK,
+        D8_MARK, SCIFA1_SCK_C_MARK, AVB_TXD0_MARK, MII_TXD0_MARK,
+        VI0_G0_MARK, VI0_G0_B_MARK, VI2_DATA0_VI2_B0_MARK,
+
+        D9_MARK, SCIFA1_RXD_C_MARK, AVB_TXD1_MARK, MII_TXD1_MARK,
+        VI0_G1_MARK, VI0_G1_B_MARK, VI2_DATA1_VI2_B1_MARK, D10_MARK,
+        SCIFA1_TXD_C_MARK, AVB_TXD2_MARK, MII_TXD2_MARK,
+        VI0_G2_MARK, VI0_G2_B_MARK, VI2_DATA2_VI2_B2_MARK, D11_MARK,
+        SCIFA1_CTS_N_C_MARK, AVB_TXD3_MARK, MII_TXD3_MARK,
+        VI0_G3_MARK, VI0_G3_B_MARK, VI2_DATA3_VI2_B3_MARK,
+        D12_MARK, SCIFA1_RTS_N_C_MARK, AVB_TXD4_MARK,
+        VI0_HSYNC_N_MARK, VI0_HSYNC_N_B_MARK, VI2_DATA4_VI2_B4_MARK,
+        D13_MARK, AVB_TXD5_MARK, VI0_VSYNC_N_MARK,
+        VI0_VSYNC_N_B_MARK, VI2_DATA5_VI2_B5_MARK, D14_MARK,
+        SCIFB1_RXD_C_MARK, AVB_TXD6_MARK, RX1_B_MARK,
+        VI0_CLKENB_MARK, VI0_CLKENB_B_MARK, VI2_DATA6_VI2_B6_MARK,
+        D15_MARK, SCIFB1_TXD_C_MARK, AVB_TXD7_MARK, TX1_B_MARK,
+        VI0_FIELD_MARK, VI0_FIELD_B_MARK, VI2_DATA7_VI2_B7_MARK,
+        A0_MARK, PWM3_MARK, A1_MARK, PWM4_MARK,
+
+        A2_MARK, PWM5_MARK, MSIOF1_SS1_B_MARK, A3_MARK,
+        PWM6_MARK, MSIOF1_SS2_B_MARK, A4_MARK, MSIOF1_TXD_B_MARK,
+        TPU0TO0_MARK, A5_MARK, SCIFA1_TXD_B_MARK, TPU0TO1_MARK,
+        A6_MARK, SCIFA1_RTS_N_B_MARK, TPU0TO2_MARK, A7_MARK,
+        SCIFA1_SCK_B_MARK, AUDIO_CLKOUT_B_MARK, TPU0TO3_MARK,
+        A8_MARK, SCIFA1_RXD_B_MARK, SSI_SCK5_B_MARK, VI0_R4_MARK,
+        VI0_R4_B_MARK, SCIFB2_RXD_C_MARK, VI2_DATA0_VI2_B0_B_MARK,
+        A9_MARK, SCIFA1_CTS_N_B_MARK, SSI_WS5_B_MARK, VI0_R5_MARK,
+        VI0_R5_B_MARK, SCIFB2_TXD_C_MARK, VI2_DATA1_VI2_B1_B_MARK,
+        A10_MARK, SSI_SDATA5_B_MARK, MSIOF2_SYNC_MARK, VI0_R6_MARK,
+        VI0_R6_B_MARK, VI2_DATA2_VI2_B2_B_MARK,
+
+        A11_MARK, SCIFB2_CTS_N_B_MARK, MSIOF2_SCK_MARK, VI1_R0_MARK,
+        VI1_R0_B_MARK, VI2_G0_MARK, VI2_DATA3_VI2_B3_B_MARK,
+        A12_MARK, SCIFB2_RXD_B_MARK, MSIOF2_TXD_MARK, VI1_R1_MARK,
+        VI1_R1_B_MARK, VI2_G1_MARK, VI2_DATA4_VI2_B4_B_MARK,
+        A13_MARK, SCIFB2_RTS_N_B_MARK, EX_WAIT2_MARK,
+        MSIOF2_RXD_MARK, VI1_R2_MARK, VI1_R2_B_MARK, VI2_G2_MARK,
+        VI2_DATA5_VI2_B5_B_MARK, A14_MARK, SCIFB2_TXD_B_MARK,
+        ATACS11_N_MARK, MSIOF2_SS1_MARK, A15_MARK, SCIFB2_SCK_B_MARK,
+        ATARD1_N_MARK, MSIOF2_SS2_MARK, A16_MARK, ATAWR1_N_MARK,
+        A17_MARK, AD_DO_B_MARK, ATADIR1_N_MARK, A18_MARK,
+        AD_CLK_B_MARK, ATAG1_N_MARK, A19_MARK, AD_NCS_N_B_MARK,
+        ATACS01_N_MARK, EX_WAIT0_B_MARK, A20_MARK, SPCLK_MARK,
+        VI1_R3_MARK, VI1_R3_B_MARK, VI2_G4_MARK,
+
+        A21_MARK, MOSI_IO0_MARK, VI1_R4_MARK, VI1_R4_B_MARK, VI2_G5_MARK,
+        A22_MARK, MISO_IO1_MARK, VI1_R5_MARK, VI1_R5_B_MARK,
+        VI2_G6_MARK, A23_MARK, IO2_MARK, VI1_G7_MARK,
+        VI1_G7_B_MARK, VI2_G7_MARK, A24_MARK, IO3_MARK,
+        VI1_R7_MARK, VI1_R7_B_MARK, VI2_CLKENB_MARK,
+        VI2_CLKENB_B_MARK, A25_MARK, SSL_MARK, VI1_G6_MARK,
+        VI1_G6_B_MARK, VI2_FIELD_MARK, VI2_FIELD_B_MARK, CS0_N_MARK,
+        VI1_R6_MARK, VI1_R6_B_MARK, VI2_G3_MARK, MSIOF0_SS2_B_MARK,
+        CS1_N_A26_MARK, SPEEDIN_MARK, VI0_R7_MARK, VI0_R7_B_MARK,
+        VI2_CLK_MARK, VI2_CLK_B_MARK, EX_CS0_N_MARK, HRX1_B_MARK,
+        VI1_G5_MARK, VI1_G5_B_MARK, VI2_R0_MARK, HTX0_B_MARK,
+        MSIOF0_SS1_B_MARK, EX_CS1_N_MARK, GPS_CLK_MARK,
+        HCTS1_N_B_MARK, VI1_FIELD_MARK, VI1_FIELD_B_MARK,
+        VI2_R1_MARK, EX_CS2_N_MARK, GPS_SIGN_MARK, HRTS1_N_B_MARK,
+        VI3_CLKENB_MARK, VI1_G0_MARK, VI1_G0_B_MARK, VI2_R2_MARK,
+
+        EX_CS3_N_MARK, GPS_MAG_MARK, VI3_FIELD_MARK,
+        VI1_G1_MARK, VI1_G1_B_MARK, VI2_R3_MARK,
+        EX_CS4_N_MARK, MSIOF1_SCK_B_MARK, VI3_HSYNC_N_MARK,
+        VI2_HSYNC_N_MARK, SCL1_MARK, VI2_HSYNC_N_B_MARK,
+        INTC_EN0_N_MARK, SCL1_CIS_MARK, EX_CS5_N_MARK, CAN0_RX_MARK,
+        MSIOF1_RXD_B_MARK, VI3_VSYNC_N_MARK, VI1_G2_MARK,
+        VI1_G2_B_MARK, VI2_R4_MARK, SDA1_MARK, INTC_EN1_N_MARK,
+        SDA1_CIS_MARK, BS_N_MARK, IETX_MARK, HTX1_B_MARK,
+        CAN1_TX_MARK, DRACK0_MARK, IETX_C_MARK, RD_N_MARK,
+        CAN0_TX_MARK, SCIFA0_SCK_B_MARK, RD_WR_N_MARK, VI1_G3_MARK,
+        VI1_G3_B_MARK, VI2_R5_MARK, SCIFA0_RXD_B_MARK,
+        INTC_IRQ4_N_MARK, WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK,
+        VI2_VSYNC_N_MARK, SCIFA0_TXD_B_MARK, VI2_VSYNC_N_B_MARK,
+        WE1_N_MARK, IERX_MARK, CAN1_RX_MARK, VI1_G4_MARK,
+        VI1_G4_B_MARK, VI2_R6_MARK, SCIFA0_CTS_N_B_MARK,
+        IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK, INTC_IRQ3_N_MARK,
+        VI3_CLK_MARK, SCIFA0_RTS_N_B_MARK, HRX0_B_MARK,
+        MSIOF0_SCK_B_MARK, DREQ0_N_MARK, VI1_HSYNC_N_MARK,
+        VI1_HSYNC_N_B_MARK, VI2_R7_MARK, SSI_SCK78_C_MARK,
+        SSI_WS78_B_MARK,
+
+        DACK0_MARK, IRQ0_MARK, INTC_IRQ0_N_MARK, SSI_SCK6_B_MARK,
+        VI1_VSYNC_N_MARK, VI1_VSYNC_N_B_MARK, SSI_WS78_C_MARK,
+        DREQ1_N_MARK, VI1_CLKENB_MARK, VI1_CLKENB_B_MARK,
+        SSI_SDATA7_C_MARK, SSI_SCK78_B_MARK, DACK1_MARK, IRQ1_MARK,
+        INTC_IRQ1_N_MARK, SSI_WS6_B_MARK, SSI_SDATA8_C_MARK,
+        DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK,
+        MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK,
+        SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK,
+        ETH_CRS_DV_MARK, RMII_CRS_DV_MARK, STP_ISCLK_0_B_MARK,
+        TS_SDEN0_D_MARK, GLO_Q0_C_MARK, SCL2_E_MARK,
+        SCL2_CIS_E_MARK, ETH_RX_ER_MARK, RMII_RX_ER_MARK,
+        STP_ISD_0_B_MARK, TS_SPSYNC0_D_MARK, GLO_Q1_C_MARK,
+        SDA2_E_MARK, SDA2_CIS_E_MARK, ETH_RXD0_MARK, RMII_RXD0_MARK,
+        STP_ISEN_0_B_MARK, TS_SDAT0_D_MARK, GLO_I0_C_MARK,
+        SCIFB1_SCK_G_MARK, SCK1_E_MARK, ETH_RXD1_MARK,
+        RMII_RXD1_MARK, HRX0_E_MARK, STP_ISSYNC_0_B_MARK,
+        TS_SCK0_D_MARK, GLO_I1_C_MARK, SCIFB1_RXD_G_MARK,
+        RX1_E_MARK, ETH_LINK_MARK, RMII_LINK_MARK, HTX0_E_MARK,
+        STP_IVCXO27_0_B_MARK, SCIFB1_TXD_G_MARK, TX1_E_MARK,
+        ETH_REF_CLK_MARK, RMII_REF_CLK_MARK, HCTS0_N_E_MARK,
+        STP_IVCXO27_1_B_MARK, HRX0_F_MARK,
+
+        ETH_MDIO_MARK, RMII_MDIO_MARK, HRTS0_N_E_MARK,
+        SIM0_D_C_MARK, HCTS0_N_F_MARK, ETH_TXD1_MARK,
+        RMII_TXD1_MARK, HTX0_F_MARK, BPFCLK_G_MARK, RDS_CLK_F_MARK,
+        ETH_TX_EN_MARK, RMII_TX_EN_MARK, SIM0_CLK_C_MARK,
+        HRTS0_N_F_MARK, ETH_MAGIC_MARK, RMII_MAGIC_MARK,
+        SIM0_RST_C_MARK, ETH_TXD0_MARK, RMII_TXD0_MARK,
+        STP_ISCLK_1_B_MARK, TS_SDEN1_C_MARK, GLO_SCLK_C_MARK,
+        ETH_MDC_MARK, RMII_MDC_MARK, STP_ISD_1_B_MARK,
+        TS_SPSYNC1_C_MARK, GLO_SDATA_C_MARK, PWM0_MARK,
+        SCIFA2_SCK_C_MARK, STP_ISEN_1_B_MARK, TS_SDAT1_C_MARK,
+        GLO_SS_C_MARK, PWM1_MARK, SCIFA2_TXD_C_MARK,
+        STP_ISSYNC_1_B_MARK, TS_SCK1_C_MARK, GLO_RFON_C_MARK,
+        PCMOE_N_MARK, PWM2_MARK, PWMFSW0_MARK, SCIFA2_RXD_C_MARK,
+        PCMWE_N_MARK, IECLK_C_MARK, DU1_DOTCLKIN_MARK,
+        AUDIO_CLKC_MARK, AUDIO_CLKOUT_C_MARK, VI0_CLK_MARK,
+        ATACS00_N_MARK, AVB_RXD1_MARK, MII_RXD1_MARK,
+        VI0_DATA0_VI0_B0_MARK, ATACS10_N_MARK, AVB_RXD2_MARK,
+        MII_RXD2_MARK,
+
+        VI0_DATA1_VI0_B1_MARK, ATARD0_N_MARK, AVB_RXD3_MARK,
+        MII_RXD3_MARK, VI0_DATA2_VI0_B2_MARK, ATAWR0_N_MARK,
+        AVB_RXD4_MARK, VI0_DATA3_VI0_B3_MARK, ATADIR0_N_MARK,
+        AVB_RXD5_MARK, VI0_DATA4_VI0_B4_MARK, ATAG0_N_MARK,
+        AVB_RXD6_MARK, VI0_DATA5_VI0_B5_MARK, EX_WAIT1_MARK,
+        AVB_RXD7_MARK, VI0_DATA6_VI0_B6_MARK, AVB_RX_ER_MARK,
+        MII_RX_ER_MARK, VI0_DATA7_VI0_B7_MARK, AVB_RX_CLK_MARK,
+        MII_RX_CLK_MARK, VI1_CLK_MARK, AVB_RX_DV_MARK,
+        MII_RX_DV_MARK, VI1_DATA0_VI1_B0_MARK, SCIFA1_SCK_D_MARK,
+        AVB_CRS_MARK, MII_CRS_MARK, VI1_DATA1_VI1_B1_MARK,
+        SCIFA1_RXD_D_MARK, AVB_MDC_MARK, MII_MDC_MARK,
+        VI1_DATA2_VI1_B2_MARK, SCIFA1_TXD_D_MARK, AVB_MDIO_MARK,
+        MII_MDIO_MARK, VI1_DATA3_VI1_B3_MARK, SCIFA1_CTS_N_D_MARK,
+        AVB_GTX_CLK_MARK, VI1_DATA4_VI1_B4_MARK, SCIFA1_RTS_N_D_MARK,
+        AVB_MAGIC_MARK, MII_MAGIC_MARK, VI1_DATA5_VI1_B5_MARK,
+        AVB_PHY_INT_MARK, VI1_DATA6_VI1_B6_MARK, AVB_GTXREFCLK_MARK,
+        SD0_CLK_MARK, VI1_DATA0_VI1_B0_B_MARK, SD0_CMD_MARK,
+        SCIFB1_SCK_B_MARK, VI1_DATA1_VI1_B1_B_MARK,
+
+        SD0_DAT0_MARK, SCIFB1_RXD_B_MARK, VI1_DATA2_VI1_B2_B_MARK,
+        SD0_DAT1_MARK, SCIFB1_TXD_B_MARK, VI1_DATA3_VI1_B3_B_MARK,
+        SD0_DAT2_MARK, SCIFB1_CTS_N_B_MARK, VI1_DATA4_VI1_B4_B_MARK,
+        SD0_DAT3_MARK, SCIFB1_RTS_N_B_MARK, VI1_DATA5_VI1_B5_B_MARK,
+        SD0_CD_MARK, MMC0_D6_MARK, TS_SDEN0_B_MARK, USB0_EXTP_MARK,
+        GLO_SCLK_MARK, VI1_DATA6_VI1_B6_B_MARK, SCL1_B_MARK,
+        SCL1_CIS_B_MARK, VI2_DATA6_VI2_B6_B_MARK, SD0_WP_MARK,
+        MMC0_D7_MARK, TS_SPSYNC0_B_MARK, USB0_IDIN_MARK,
+        GLO_SDATA_MARK, VI1_DATA7_VI1_B7_B_MARK, SDA1_B_MARK,
+        SDA1_CIS_B_MARK, VI2_DATA7_VI2_B7_B_MARK, SD1_CLK_MARK,
+        AVB_TX_EN_MARK, MII_TX_EN_MARK, SD1_CMD_MARK,
+        AVB_TX_ER_MARK, MII_TX_ER_MARK, SCIFB0_SCK_B_MARK,
+        SD1_DAT0_MARK, AVB_TX_CLK_MARK, MII_TX_CLK_MARK,
+        SCIFB0_RXD_B_MARK, SD1_DAT1_MARK, AVB_LINK_MARK,
+        MII_LINK_MARK, SCIFB0_TXD_B_MARK, SD1_DAT2_MARK,
+        AVB_COL_MARK, MII_COL_MARK, SCIFB0_CTS_N_B_MARK,
+        SD1_DAT3_MARK, AVB_RXD0_MARK, MII_RXD0_MARK,
+        SCIFB0_RTS_N_B_MARK, SD1_CD_MARK, MMC1_D6_MARK,
+        TS_SDEN1_MARK, USB1_EXTP_MARK, GLO_SS_MARK, VI0_CLK_B_MARK,
+        SCL2_D_MARK, SCL2_CIS_D_MARK, SIM0_CLK_B_MARK,
+        VI3_CLK_B_MARK,
+
+        SD1_WP_MARK, MMC1_D7_MARK, TS_SPSYNC1_MARK, USB1_IDIN_MARK,
+        GLO_RFON_MARK, VI1_CLK_B_MARK, SDA2_D_MARK, SDA2_CIS_D_MARK,
+        SIM0_D_B_MARK, SD2_CLK_MARK, MMC0_CLK_MARK, SIM0_CLK_MARK,
+        VI0_DATA0_VI0_B0_B_MARK, TS_SDEN0_C_MARK, GLO_SCLK_B_MARK,
+        VI3_DATA0_B_MARK, SD2_CMD_MARK, MMC0_CMD_MARK, SIM0_D_MARK,
+        VI0_DATA1_VI0_B1_B_MARK, SCIFB1_SCK_E_MARK, SCK1_D_MARK,
+        TS_SPSYNC0_C_MARK, GLO_SDATA_B_MARK, VI3_DATA1_B_MARK,
+        SD2_DAT0_MARK, MMC0_D0_MARK, FMCLK_B_MARK,
+        VI0_DATA2_VI0_B2_B_MARK, SCIFB1_RXD_E_MARK, RX1_D_MARK,
+        TS_SDAT0_C_MARK, GLO_SS_B_MARK, VI3_DATA2_B_MARK,
+        SD2_DAT1_MARK, MMC0_D1_MARK, FMIN_B_MARK, RDS_DATA_MARK,
+        VI0_DATA3_VI0_B3_B_MARK, SCIFB1_TXD_E_MARK, TX1_D_MARK,
+        TS_SCK0_C_MARK, GLO_RFON_B_MARK, VI3_DATA3_B_MARK,
+        SD2_DAT2_MARK, MMC0_D2_MARK, BPFCLK_B_MARK, RDS_CLK_MARK,
+        VI0_DATA4_VI0_B4_B_MARK, HRX0_D_MARK, TS_SDEN1_B_MARK,
+        GLO_Q0_B_MARK, VI3_DATA4_B_MARK, SD2_DAT3_MARK,
+        MMC0_D3_MARK, SIM0_RST_MARK, VI0_DATA5_VI0_B5_B_MARK,
+        HTX0_D_MARK, TS_SPSYNC1_B_MARK, GLO_Q1_B_MARK,
+        VI3_DATA5_B_MARK, SD2_CD_MARK, MMC0_D4_MARK,
+        TS_SDAT0_B_MARK, USB2_EXTP_MARK, GLO_I0_MARK,
+        VI0_DATA6_VI0_B6_B_MARK, HCTS0_N_D_MARK, TS_SDAT1_B_MARK,
+        GLO_I0_B_MARK, VI3_DATA6_B_MARK,
+
+        SD2_WP_MARK, MMC0_D5_MARK, TS_SCK0_B_MARK, USB2_IDIN_MARK,
+        GLO_I1_MARK, VI0_DATA7_VI0_B7_B_MARK, HRTS0_N_D_MARK,
+        TS_SCK1_B_MARK, GLO_I1_B_MARK, VI3_DATA7_B_MARK,
+        SD3_CLK_MARK, MMC1_CLK_MARK, SD3_CMD_MARK, MMC1_CMD_MARK,
+        MTS_N_MARK, SD3_DAT0_MARK, MMC1_D0_MARK, STM_N_MARK,
+        SD3_DAT1_MARK, MMC1_D1_MARK, MDATA_MARK, SD3_DAT2_MARK,
+        MMC1_D2_MARK, SDATA_MARK, SD3_DAT3_MARK, MMC1_D3_MARK,
+        SCKZ_MARK, SD3_CD_MARK, MMC1_D4_MARK, TS_SDAT1_MARK,
+        VSP_MARK, GLO_Q0_MARK, SIM0_RST_B_MARK, SD3_WP_MARK,
+        MMC1_D5_MARK, TS_SCK1_MARK, GLO_Q1_MARK, FMIN_C_MARK,
+        RDS_DATA_B_MARK, FMIN_E_MARK, RDS_DATA_D_MARK, FMIN_F_MARK,
+        RDS_DATA_E_MARK, MLB_CLK_MARK, SCL2_B_MARK, SCL2_CIS_B_MARK,
+        MLB_SIG_MARK, SCIFB1_RXD_D_MARK, RX1_C_MARK, SDA2_B_MARK,
+        SDA2_CIS_B_MARK, MLB_DAT_MARK, SPV_EVEN_MARK,
+        SCIFB1_TXD_D_MARK, TX1_C_MARK, BPFCLK_C_MARK,
+        RDS_CLK_B_MARK, SSI_SCK0129_MARK, CAN_CLK_B_MARK,
+        MOUT0_MARK,
+
+        SSI_WS0129_MARK, CAN0_TX_B_MARK, MOUT1_MARK,
+        SSI_SDATA0_MARK, CAN0_RX_B_MARK, MOUT2_MARK,
+        SSI_SDATA1_MARK, CAN1_TX_B_MARK, MOUT5_MARK,
+        SSI_SDATA2_MARK, CAN1_RX_B_MARK, SSI_SCK1_MARK, MOUT6_MARK,
+        SSI_SCK34_MARK, STP_OPWM_0_MARK, SCIFB0_SCK_MARK,
+        MSIOF1_SCK_MARK, CAN_DEBUG_HW_TRIGGER_MARK, SSI_WS34_MARK,
+        STP_IVCXO27_0_MARK, SCIFB0_RXD_MARK, MSIOF1_SYNC_MARK,
+        CAN_STEP0_MARK, SSI_SDATA3_MARK, STP_ISCLK_0_MARK,
+        SCIFB0_TXD_MARK, MSIOF1_SS1_MARK, CAN_TXCLK_MARK,
+        SSI_SCK4_MARK, STP_ISD_0_MARK, SCIFB0_CTS_N_MARK,
+        MSIOF1_SS2_MARK, SSI_SCK5_C_MARK, CAN_DEBUGOUT0_MARK,
+        SSI_WS4_MARK, STP_ISEN_0_MARK, SCIFB0_RTS_N_MARK,
+        MSIOF1_TXD_MARK, SSI_WS5_C_MARK, CAN_DEBUGOUT1_MARK,
+        SSI_SDATA4_MARK, STP_ISSYNC_0_MARK, MSIOF1_RXD_MARK,
+        CAN_DEBUGOUT2_MARK, SSI_SCK5_MARK, SCIFB1_SCK_MARK,
+        IERX_B_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK, QSTH_QHS_MARK,
+        CAN_DEBUGOUT3_MARK, SSI_WS5_MARK, SCIFB1_RXD_MARK,
+        IECLK_B_MARK, DU2_EXVSYNC_DU2_VSYNC_MARK, QSTB_QHE_MARK,
+        CAN_DEBUGOUT4_MARK,
+
+        SSI_SDATA5_MARK, SCIFB1_TXD_MARK, IETX_B_MARK, DU2_DR2_MARK,
+        LCDOUT2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK6_MARK,
+        SCIFB1_CTS_N_MARK, BPFCLK_D_MARK, RDS_CLK_C_MARK,
+        DU2_DR3_MARK, LCDOUT3_MARK, CAN_DEBUGOUT6_MARK,
+        BPFCLK_F_MARK, RDS_CLK_E_MARK, SSI_WS6_MARK,
+        SCIFB1_RTS_N_MARK, CAN0_TX_D_MARK, DU2_DR4_MARK,
+        LCDOUT4_MARK, CAN_DEBUGOUT7_MARK, SSI_SDATA6_MARK,
+        FMIN_D_MARK, RDS_DATA_C_MARK, DU2_DR5_MARK, LCDOUT5_MARK,
+        CAN_DEBUGOUT8_MARK, SSI_SCK78_MARK, STP_IVCXO27_1_MARK,
+        SCK1_MARK, SCIFA1_SCK_MARK, DU2_DR6_MARK, LCDOUT6_MARK,
+        CAN_DEBUGOUT9_MARK, SSI_WS78_MARK, STP_ISCLK_1_MARK,
+        SCIFB2_SCK_MARK, SCIFA2_CTS_N_MARK, DU2_DR7_MARK,
+        LCDOUT7_MARK, CAN_DEBUGOUT10_MARK, SSI_SDATA7_MARK,
+        STP_ISD_1_MARK, SCIFB2_RXD_MARK, SCIFA2_RTS_N_MARK,
+        TCLK2_MARK, QSTVA_QVS_MARK, CAN_DEBUGOUT11_MARK,
+        BPFCLK_E_MARK, RDS_CLK_D_MARK, SSI_SDATA7_B_MARK,
+        FMIN_G_MARK, RDS_DATA_F_MARK, SSI_SDATA8_MARK,
+        STP_ISEN_1_MARK, SCIFB2_TXD_MARK, CAN0_TX_C_MARK,
+        CAN_DEBUGOUT12_MARK, SSI_SDATA8_B_MARK, SSI_SDATA9_MARK,
+        STP_ISSYNC_1_MARK, SCIFB2_CTS_N_MARK, SSI_WS1_MARK,
+        SSI_SDATA5_C_MARK, CAN_DEBUGOUT13_MARK, AUDIO_CLKA_MARK,
+        SCIFB2_RTS_N_MARK, CAN_DEBUGOUT14_MARK,
+
+        AUDIO_CLKB_MARK, SCIF_CLK_MARK, CAN0_RX_D_MARK,
+        DVC_MUTE_MARK, CAN0_RX_C_MARK, CAN_DEBUGOUT15_MARK,
+        REMOCON_MARK, SCIFA0_SCK_MARK, HSCK1_MARK, SCK0_MARK,
+        MSIOF3_SS2_MARK, DU2_DG2_MARK, LCDOUT10_MARK, SDA1_C_MARK,
+        SDA1_CIS_C_MARK, SCIFA0_RXD_MARK, HRX1_MARK, RX0_MARK,
+        DU2_DR0_MARK, LCDOUT0_MARK, SCIFA0_TXD_MARK, HTX1_MARK,
+        TX0_MARK, DU2_DR1_MARK, LCDOUT1_MARK, SCIFA0_CTS_N_MARK,
+        HCTS1_N_MARK, CTS0_N_MARK, MSIOF3_SYNC_MARK, DU2_DG3_MARK,
+        LCDOUT11_MARK, PWM0_B_MARK, SCL1_C_MARK, SCL1_CIS_C_MARK,
+        SCIFA0_RTS_N_MARK, HRTS1_N_MARK, RTS0_N_TANS_MARK,
+        MSIOF3_SS1_MARK, DU2_DG0_MARK, LCDOUT8_MARK, PWM1_B_MARK,
+        SCIFA1_RXD_MARK, AD_DI_MARK, RX1_MARK,
+        DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
+        SCIFA1_TXD_MARK, AD_DO_MARK, TX1_MARK, DU2_DG1_MARK,
+        LCDOUT9_MARK, SCIFA1_CTS_N_MARK, AD_CLK_MARK,
+        CTS1_N_MARK, MSIOF3_RXD_MARK, DU0_DOTCLKOUT_MARK, QCLK_MARK,
+        SCIFA1_RTS_N_MARK, AD_NCS_N_MARK, RTS1_N_TANS_MARK,
+        MSIOF3_TXD_MARK, DU1_DOTCLKOUT_MARK, QSTVB_QVE_MARK,
+        HRTS0_N_C_MARK,
+
+        SCIFA2_SCK_MARK, FMCLK_MARK, MSIOF3_SCK_MARK, DU2_DG7_MARK,
+        LCDOUT15_MARK, SCIF_CLK_B_MARK, SCIFA2_RXD_MARK, FMIN_MARK,
+        DU2_DB0_MARK, LCDOUT16_MARK, SCL2_MARK, SCL2_CIS_MARK,
+        SCIFA2_TXD_MARK, BPFCLK_MARK, DU2_DB1_MARK, LCDOUT17_MARK,
+        SDA2_MARK, SDA2_CIS_MARK, HSCK0_MARK, TS_SDEN0_MARK,
+        DU2_DG4_MARK, LCDOUT12_MARK, HCTS0_N_C_MARK, HRX0_MARK,
+        DU2_DB2_MARK, LCDOUT18_MARK, HTX0_MARK, DU2_DB3_MARK,
+        LCDOUT19_MARK, HCTS0_N_MARK, SSI_SCK9_MARK, DU2_DB4_MARK,
+        LCDOUT20_MARK, HRTS0_N_MARK, SSI_WS9_MARK, DU2_DB5_MARK,
+        LCDOUT21_MARK, MSIOF0_SCK_MARK, TS_SDAT0_MARK, ADICLK_MARK,
+        DU2_DB6_MARK, LCDOUT22_MARK, MSIOF0_SYNC_MARK, TS_SCK0_MARK,
+        SSI_SCK2_MARK, ADIDATA_MARK, DU2_DB7_MARK, LCDOUT23_MARK,
+        SCIFA2_RXD_B_MARK, MSIOF0_SS1_MARK, ADICHS0_MARK,
+        DU2_DG5_MARK, LCDOUT13_MARK, MSIOF0_TXD_MARK, ADICHS1_MARK,
+        DU2_DG6_MARK, LCDOUT14_MARK,
+
+        MSIOF0_SS2_MARK, AUDIO_CLKOUT_MARK, ADICHS2_MARK,
+        DU2_DISP_MARK, QPOLA_MARK, HTX0_C_MARK, SCIFA2_TXD_B_MARK,
+        MSIOF0_RXD_MARK, TS_SPSYNC0_MARK, SSI_WS2_MARK,
+        ADICS_SAMP_MARK, DU2_CDE_MARK, QPOLB_MARK, HRX0_C_MARK,
+        USB1_PWEN_MARK, AUDIO_CLKOUT_D_MARK, USB1_OVC_MARK,
+        TCLK1_B_MARK,
+        PINMUX_MARK_END,
+};
+
+static const pinmux_enum_t pinmux_data[] = {
+        PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
+
+        PINMUX_DATA(VI1_DATA7_VI1_B7_MARK, FN_VI1_DATA7_VI1_B7),
+        PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN),
+        PINMUX_DATA(USB0_OVC_VBUS_MARK, FN_USB0_OVC_VBUS),
+        PINMUX_DATA(USB2_PWEN_MARK, FN_USB2_PWEN),
+        PINMUX_DATA(USB2_OVC_MARK, FN_USB2_OVC),
+        PINMUX_DATA(AVS1_MARK, FN_AVS1),
+        PINMUX_DATA(AVS2_MARK, FN_AVS2),
+        PINMUX_DATA(DU_DOTCLKIN0_MARK, FN_DU_DOTCLKIN0),
+        PINMUX_DATA(DU_DOTCLKIN2_MARK, FN_DU_DOTCLKIN2),
+
+        PINMUX_IPSR_DATA(IP0_2_0, D0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_2_0, MSIOF3_SCK_B, SEL_SOF3_1),
+        PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI3_DATA0, SEL_VI3_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI0_G4, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI0_G4_B, SEL_VI0_1),
+        PINMUX_IPSR_DATA(IP0_5_3, D1),
+        PINMUX_IPSR_MODSEL_DATA(IP0_5_3, MSIOF3_SYNC_B, SEL_SOF3_1),
+        PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI3_DATA1, SEL_VI3_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI0_G5, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI0_G5_B, SEL_VI0_1),
+        PINMUX_IPSR_DATA(IP0_8_6, D2),
+        PINMUX_IPSR_MODSEL_DATA(IP0_8_6, MSIOF3_RXD_B, SEL_SOF3_1),
+        PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI3_DATA2, SEL_VI3_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI0_G6, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI0_G6_B, SEL_VI0_1),
+        PINMUX_IPSR_DATA(IP0_11_9, D3),
+        PINMUX_IPSR_MODSEL_DATA(IP0_11_9, MSIOF3_TXD_B, SEL_SOF3_1),
+        PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI3_DATA3, SEL_VI3_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI0_G7, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI0_G7_B, SEL_VI0_1),
+        PINMUX_IPSR_DATA(IP0_15_12, D4),
+        PINMUX_IPSR_MODSEL_DATA(IP0_15_12, SCIFB1_RXD_F, SEL_SCIFB1_5),
+        PINMUX_IPSR_MODSEL_DATA(IP0_15_12, SCIFB0_RXD_C, SEL_SCIFB_2),
+        PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI3_DATA4, SEL_VI3_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI0_R0, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI0_R0_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP0_15_12, RX0_B, SEL_SCIF0_1),
+        PINMUX_IPSR_DATA(IP0_19_16, D5),
+        PINMUX_IPSR_MODSEL_DATA(IP0_19_16, SCIFB1_TXD_F, SEL_SCIFB1_5),
+        PINMUX_IPSR_MODSEL_DATA(IP0_19_16, SCIFB0_TXD_C, SEL_SCIFB_2),
+        PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI3_DATA5, SEL_VI3_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI0_R1, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI0_R1_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP0_19_16, TX0_B, SEL_SCIF0_1),
+        PINMUX_IPSR_DATA(IP0_22_20, D6),
+        PINMUX_IPSR_MODSEL_DATA(IP0_22_20, SCL2_C, SEL_IIC2_2),
+        PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI3_DATA6, SEL_VI3_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI0_R2, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI0_R2_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP0_22_20, SCL2_CIS_C, SEL_I2C2_2),
+        PINMUX_IPSR_DATA(IP0_26_23, D7),
+        PINMUX_IPSR_MODSEL_DATA(IP0_26_23, AD_DI_B, SEL_ADI_1),
+        PINMUX_IPSR_MODSEL_DATA(IP0_26_23, SDA2_C, SEL_IIC2_2),
+        PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI3_DATA7, SEL_VI3_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI0_R3, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI0_R3_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP0_26_23, SDA2_CIS_C, SEL_I2C2_2),
+        PINMUX_IPSR_DATA(IP0_30_27, D8),
+        PINMUX_IPSR_MODSEL_DATA(IP0_30_27, SCIFA1_SCK_C, SEL_SCIFA1_2),
+        PINMUX_IPSR_DATA(IP0_30_27, AVB_TXD0),
+        PINMUX_IPSR_DATA(IP0_30_27, MII_TXD0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI2_DATA0_VI2_B0, SEL_VI2_0),
+
+        PINMUX_IPSR_DATA(IP1_3_0, D9),
+        PINMUX_IPSR_MODSEL_DATA(IP1_3_0, SCIFA1_RXD_C, SEL_SCIFA1_2),
+        PINMUX_IPSR_DATA(IP1_3_0, AVB_TXD1),
+        PINMUX_IPSR_DATA(IP1_3_0, MII_TXD1),
+        PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI2_DATA1_VI2_B1, SEL_VI2_0),
+        PINMUX_IPSR_DATA(IP1_7_4, D10),
+        PINMUX_IPSR_MODSEL_DATA(IP1_7_4, SCIFA1_TXD_C, SEL_SCIFA1_2),
+        PINMUX_IPSR_DATA(IP1_7_4, AVB_TXD2),
+        PINMUX_IPSR_DATA(IP1_7_4, MII_TXD2),
+        PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI2_DATA2_VI2_B2, SEL_VI2_0),
+        PINMUX_IPSR_DATA(IP1_11_8, D11),
+        PINMUX_IPSR_MODSEL_DATA(IP1_11_8, SCIFA1_CTS_N_C, SEL_SCIFA1_2),
+        PINMUX_IPSR_DATA(IP1_11_8, AVB_TXD3),
+        PINMUX_IPSR_DATA(IP1_11_8, MII_TXD3),
+        PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI2_DATA3_VI2_B3, SEL_VI2_0),
+        PINMUX_IPSR_DATA(IP1_14_12, D12),
+        PINMUX_IPSR_MODSEL_DATA(IP1_14_12, SCIFA1_RTS_N_C, SEL_SCIFA1_2),
+        PINMUX_IPSR_DATA(IP1_14_12, AVB_TXD4),
+        PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI0_HSYNC_N, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI0_HSYNC_N_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI2_DATA4_VI2_B4, SEL_VI2_0),
+        PINMUX_IPSR_DATA(IP1_17_15, D13),
+        PINMUX_IPSR_MODSEL_DATA(IP1_17_15, AVB_TXD5, SEL_SCIFA1_2),
+        PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI0_VSYNC_N, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI0_VSYNC_N_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI2_DATA5_VI2_B5, SEL_VI2_0),
+        PINMUX_IPSR_DATA(IP1_21_18, D14),
+        PINMUX_IPSR_MODSEL_DATA(IP1_21_18, SCIFB1_RXD_C, SEL_SCIFB1_2),
+        PINMUX_IPSR_DATA(IP1_21_18, AVB_TXD6),
+        PINMUX_IPSR_MODSEL_DATA(IP1_21_18, RX1_B, SEL_SCIF1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI0_CLKENB, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI0_CLKENB_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI2_DATA6_VI2_B6, SEL_VI2_0),
+        PINMUX_IPSR_DATA(IP1_25_22, D15),
+        PINMUX_IPSR_MODSEL_DATA(IP1_25_22, SCIFB1_TXD_C, SEL_SCIFB1_2),
+        PINMUX_IPSR_DATA(IP1_25_22, AVB_TXD7),
+        PINMUX_IPSR_MODSEL_DATA(IP1_25_22, TX1_B, SEL_SCIF1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI0_FIELD, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI0_FIELD_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI2_DATA7_VI2_B7, SEL_VI2_0),
+        PINMUX_IPSR_DATA(IP1_27_26, A0),
+        PINMUX_IPSR_DATA(IP1_27_26, PWM3),
+        PINMUX_IPSR_DATA(IP1_29_28, A1),
+        PINMUX_IPSR_DATA(IP1_29_28, PWM4),
+
+        PINMUX_IPSR_DATA(IP2_2_0, A2),
+        PINMUX_IPSR_DATA(IP2_2_0, PWM5),
+        PINMUX_IPSR_MODSEL_DATA(IP2_2_0, MSIOF1_SS1_B, SEL_SOF1_1),
+        PINMUX_IPSR_DATA(IP2_5_3, A3),
+        PINMUX_IPSR_DATA(IP2_5_3, PWM6),
+        PINMUX_IPSR_MODSEL_DATA(IP2_5_3, MSIOF1_SS2_B, SEL_SOF1_1),
+        PINMUX_IPSR_DATA(IP2_8_6, A4),
+        PINMUX_IPSR_MODSEL_DATA(IP2_8_6, MSIOF1_TXD_B, SEL_SOF1_1),
+        PINMUX_IPSR_DATA(IP2_8_6, TPU0TO0),
+        PINMUX_IPSR_DATA(IP2_11_9, A5),
+        PINMUX_IPSR_MODSEL_DATA(IP2_11_9, SCIFA1_TXD_B, SEL_SCIFA1_1),
+        PINMUX_IPSR_DATA(IP2_11_9, TPU0TO1),
+        PINMUX_IPSR_DATA(IP2_14_12, A6),
+        PINMUX_IPSR_MODSEL_DATA(IP2_14_12, SCIFA1_RTS_N_B, SEL_SCIFA1_1),
+        PINMUX_IPSR_DATA(IP2_14_12, TPU0TO2),
+        PINMUX_IPSR_DATA(IP2_17_15, A7),
+        PINMUX_IPSR_MODSEL_DATA(IP2_17_15, SCIFA1_SCK_B, SEL_SCIFA1_1),
+        PINMUX_IPSR_DATA(IP2_17_15, AUDIO_CLKOUT_B),
+        PINMUX_IPSR_DATA(IP2_17_15, TPU0TO3),
+        PINMUX_IPSR_DATA(IP2_21_18, A8),
+        PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SCIFA1_RXD_B, SEL_SCIFA1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SSI_SCK5_B, SEL_SSI5_1),
+        PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI0_R4, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI0_R4_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SCIFB2_RXD_C, SEL_SCIFB2_2),
+        PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI2_DATA0_VI2_B0_B, SEL_VI2_1),
+        PINMUX_IPSR_DATA(IP2_25_22, A9),
+        PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SCIFA1_CTS_N_B, SEL_SCIFA1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SSI_WS5_B, SEL_SSI5_1),
+        PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI0_R5, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI0_R5_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SCIFB2_TXD_C, SEL_SCIFB2_2),
+        PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI2_DATA1_VI2_B1_B, SEL_VI2_1),
+        PINMUX_IPSR_DATA(IP2_28_26, A10),
+        PINMUX_IPSR_MODSEL_DATA(IP2_28_26, SSI_SDATA5_B, SEL_SSI5_1),
+        PINMUX_IPSR_DATA(IP2_28_26, MSIOF2_SYNC),
+        PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI0_R6, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI0_R6_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI2_DATA2_VI2_B2_B, SEL_VI2_1),
+
+        PINMUX_IPSR_DATA(IP3_3_0, A11),
+        PINMUX_IPSR_MODSEL_DATA(IP3_3_0, SCIFB2_CTS_N_B, SEL_SCIFB2_1),
+        PINMUX_IPSR_DATA(IP3_3_0, MSIOF2_SCK),
+        PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI1_R0, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI1_R0_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP3_3_0, VI2_G0),
+        PINMUX_IPSR_DATA(IP3_3_0, VI2_DATA3_VI2_B3_B),
+        PINMUX_IPSR_DATA(IP3_7_4, A12),
+        PINMUX_IPSR_MODSEL_DATA(IP3_7_4, SCIFB2_RXD_B, SEL_SCIFB2_1),
+        PINMUX_IPSR_DATA(IP3_7_4, MSIOF2_TXD),
+        PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI1_R1, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI1_R1_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP3_7_4, VI2_G1),
+        PINMUX_IPSR_DATA(IP3_7_4, VI2_DATA4_VI2_B4_B),
+        PINMUX_IPSR_DATA(IP3_11_8, A13),
+        PINMUX_IPSR_MODSEL_DATA(IP3_11_8, SCIFB2_RTS_N_B, SEL_SCIFB2_1),
+        PINMUX_IPSR_DATA(IP3_11_8, EX_WAIT2),
+        PINMUX_IPSR_DATA(IP3_11_8, MSIOF2_RXD),
+        PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI1_R2, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI1_R2_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP3_11_8, VI2_G2),
+        PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI2_DATA5_VI2_B5_B, SEL_VI2_0),
+        PINMUX_IPSR_DATA(IP3_14_12, A14),
+        PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SCIFB2_TXD_B, SEL_SCIFB2_1),
+        PINMUX_IPSR_DATA(IP3_14_12, ATACS11_N),
+        PINMUX_IPSR_DATA(IP3_14_12, MSIOF2_SS1),
+        PINMUX_IPSR_DATA(IP3_17_15, A15),
+        PINMUX_IPSR_MODSEL_DATA(IP3_17_15, SCIFB2_SCK_B, SEL_SCIFB2_1),
+        PINMUX_IPSR_DATA(IP3_17_15, ATARD1_N),
+        PINMUX_IPSR_DATA(IP3_17_15, MSIOF2_SS2),
+        PINMUX_IPSR_DATA(IP3_19_18, A16),
+        PINMUX_IPSR_DATA(IP3_19_18, ATAWR1_N),
+        PINMUX_IPSR_DATA(IP3_22_20, A17),
+        PINMUX_IPSR_MODSEL_DATA(IP3_22_20, AD_DO_B, SEL_ADI_1),
+        PINMUX_IPSR_DATA(IP3_22_20, ATADIR1_N),
+        PINMUX_IPSR_DATA(IP3_25_23, A18),
+        PINMUX_IPSR_MODSEL_DATA(IP3_25_23, AD_CLK_B, SEL_ADI_1),
+        PINMUX_IPSR_DATA(IP3_25_23, ATAG1_N),
+        PINMUX_IPSR_DATA(IP3_28_26, A19),
+        PINMUX_IPSR_MODSEL_DATA(IP3_28_26, AD_NCS_N_B, SEL_ADI_1),
+        PINMUX_IPSR_DATA(IP3_28_26, ATACS01_N),
+        PINMUX_IPSR_MODSEL_DATA(IP3_28_26, EX_WAIT0_B, SEL_LBS_1),
+        PINMUX_IPSR_DATA(IP3_31_29, A20),
+        PINMUX_IPSR_DATA(IP3_31_29, SPCLK),
+        PINMUX_IPSR_MODSEL_DATA(IP3_31_29, VI1_R3, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP3_31_29, VI1_R3_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP3_31_29, VI2_G4),
+
+        PINMUX_IPSR_DATA(IP4_2_0, A21),
+        PINMUX_IPSR_DATA(IP4_2_0, MOSI_IO0),
+        PINMUX_IPSR_MODSEL_DATA(IP4_2_0, VI1_R4, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP4_2_0, VI1_R4_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP4_2_0, VI2_G5),
+        PINMUX_IPSR_DATA(IP4_5_3, A22),
+        PINMUX_IPSR_DATA(IP4_5_3, MISO_IO1),
+        PINMUX_IPSR_MODSEL_DATA(IP4_5_3, VI1_R5, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP4_5_3, VI1_R5_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP4_5_3, VI2_G6),
+        PINMUX_IPSR_DATA(IP4_8_6, A23),
+        PINMUX_IPSR_DATA(IP4_8_6, IO2),
+        PINMUX_IPSR_MODSEL_DATA(IP4_8_6, VI1_G7, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP4_8_6, VI1_G7_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP4_8_6, VI2_G7),
+        PINMUX_IPSR_DATA(IP4_11_9, A24),
+        PINMUX_IPSR_DATA(IP4_11_9, IO3),
+        PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI1_R7, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI1_R7_B, SEL_VI1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI2_CLKENB, SEL_VI2_0),
+        PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI2_CLKENB_B, SEL_VI2_1),
+        PINMUX_IPSR_DATA(IP4_14_12, A25),
+        PINMUX_IPSR_DATA(IP4_14_12, SSL),
+        PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI1_G6, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI1_G6_B, SEL_VI1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI2_FIELD, SEL_VI2_0),
+        PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI2_FIELD_B, SEL_VI2_1),
+        PINMUX_IPSR_DATA(IP4_17_15, CS0_N),
+        PINMUX_IPSR_MODSEL_DATA(IP4_17_15, VI1_R6, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP4_17_15, VI1_R6_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP4_17_15, VI2_G3),
+        PINMUX_IPSR_MODSEL_DATA(IP4_17_15, MSIOF0_SS2_B, SEL_SOF0_1),
+        PINMUX_IPSR_DATA(IP4_20_18, CS1_N_A26),
+        PINMUX_IPSR_DATA(IP4_20_18, SPEEDIN),
+        PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI0_R7, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI0_R7_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI2_CLK, SEL_VI2_0),
+        PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI2_CLK_B, SEL_VI2_1),
+        PINMUX_IPSR_DATA(IP4_23_21, EX_CS0_N),
+        PINMUX_IPSR_MODSEL_DATA(IP4_23_21, HRX1_B, SEL_HSCIF1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP4_23_21, VI1_G5, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP4_23_21, VI1_G5_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP4_23_21, VI2_R0),
+        PINMUX_IPSR_MODSEL_DATA(IP4_23_21, HTX0_B, SEL_HSCIF0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP4_23_21, MSIOF0_SS1_B, SEL_SOF0_1),
+        PINMUX_IPSR_DATA(IP4_26_24, EX_CS1_N),
+        PINMUX_IPSR_DATA(IP4_26_24, GPS_CLK),
+        PINMUX_IPSR_MODSEL_DATA(IP4_26_24, HCTS1_N_B, SEL_HSCIF1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP4_26_24, VI1_FIELD, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP4_26_24, VI1_FIELD_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP4_26_24, VI2_R1),
+        PINMUX_IPSR_DATA(IP4_29_27, EX_CS2_N),
+        PINMUX_IPSR_DATA(IP4_29_27, GPS_SIGN),
+        PINMUX_IPSR_MODSEL_DATA(IP4_29_27, HRTS1_N_B, SEL_HSCIF1_1),
+        PINMUX_IPSR_DATA(IP4_29_27, VI3_CLKENB),
+        PINMUX_IPSR_MODSEL_DATA(IP4_29_27, VI1_G0, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP4_29_27, VI1_G0_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP4_29_27, VI2_R2),
+
+        PINMUX_IPSR_DATA(IP5_2_0, EX_CS3_N),
+        PINMUX_IPSR_DATA(IP5_2_0, GPS_MAG),
+        PINMUX_IPSR_DATA(IP5_2_0, VI3_FIELD),
+        PINMUX_IPSR_MODSEL_DATA(IP5_2_0, VI1_G1, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_2_0, VI1_G1_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP5_2_0, VI2_R3),
+        PINMUX_IPSR_MODSEL_DATA(IP5_5_3, EX_CS4_N, SEL_I2C1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_5_3, MSIOF1_SCK_B, SEL_SOF1_1),
+        PINMUX_IPSR_DATA(IP5_5_3, VI3_HSYNC_N),
+        PINMUX_IPSR_MODSEL_DATA(IP5_5_3, VI2_HSYNC_N, SEL_VI2_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_5_3, SCL1, SEL_IIC1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_5_3, VI2_HSYNC_N_B, SEL_VI2_1),
+        PINMUX_IPSR_DATA(IP5_5_3, INTC_EN0_N),
+        PINMUX_IPSR_MODSEL_DATA(IP5_5_3, SCL1_CIS, SEL_I2C1_0),
+        PINMUX_IPSR_DATA(IP5_9_6, EX_CS5_N),
+        PINMUX_IPSR_MODSEL_DATA(IP5_9_6, CAN0_RX, SEL_CAN0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_9_6, MSIOF1_RXD_B, SEL_SOF1_1),
+        PINMUX_IPSR_DATA(IP5_9_6, VI3_VSYNC_N),
+        PINMUX_IPSR_MODSEL_DATA(IP5_9_6, VI1_G2, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_9_6, VI1_G2_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP5_9_6, VI2_R4),
+        PINMUX_IPSR_MODSEL_DATA(IP5_9_6, SDA1, SEL_IIC1_0),
+        PINMUX_IPSR_DATA(IP5_9_6, INTC_EN1_N),
+        PINMUX_IPSR_MODSEL_DATA(IP5_9_6, SDA1_CIS, SEL_I2C1_0),
+        PINMUX_IPSR_DATA(IP5_12_10, BS_N),
+        PINMUX_IPSR_MODSEL_DATA(IP5_12_10, IETX, SEL_IEB_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_12_10, HTX1_B, SEL_HSCIF1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP5_12_10, CAN1_TX, SEL_CAN1_0),
+        PINMUX_IPSR_DATA(IP5_12_10, DRACK0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_12_10, IETX_C, SEL_IEB_2),
+        PINMUX_IPSR_DATA(IP5_14_13, RD_N),
+        PINMUX_IPSR_MODSEL_DATA(IP5_14_13, CAN0_TX, SEL_CAN0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_14_13, SCIFA0_SCK_B, SEL_SCFA_1),
+        PINMUX_IPSR_DATA(IP5_17_15, RD_WR_N),
+        PINMUX_IPSR_MODSEL_DATA(IP5_17_15, VI1_G3, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_17_15, VI1_G3_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP5_17_15, VI2_R5),
+        PINMUX_IPSR_MODSEL_DATA(IP5_17_15, SCIFA0_RXD_B, SEL_SCFA_1),
+        PINMUX_IPSR_DATA(IP5_17_15, INTC_IRQ4_N),
+        PINMUX_IPSR_DATA(IP5_20_18, WE0_N),
+        PINMUX_IPSR_MODSEL_DATA(IP5_20_18, IECLK, SEL_IEB_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_20_18, CAN_CLK, SEL_CANCLK_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_20_18, VI2_VSYNC_N, SEL_VI2_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_20_18, SCIFA0_TXD_B, SEL_SCFA_1),
+        PINMUX_IPSR_MODSEL_DATA(IP5_20_18, VI2_VSYNC_N_B, SEL_VI2_1),
+        PINMUX_IPSR_DATA(IP5_23_21, WE1_N),
+        PINMUX_IPSR_MODSEL_DATA(IP5_23_21, IERX, SEL_IEB_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_23_21, CAN1_RX, SEL_CAN1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_23_21, VI1_G4, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_23_21, VI1_G4_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP5_23_21, VI2_R6),
+        PINMUX_IPSR_MODSEL_DATA(IP5_23_21, SCIFA0_CTS_N_B, SEL_SCFA_1),
+        PINMUX_IPSR_MODSEL_DATA(IP5_23_21, IERX_C, SEL_IEB_2),
+        PINMUX_IPSR_DATA(IP5_26_24, EX_WAIT0),
+        PINMUX_IPSR_DATA(IP5_26_24, IRQ3),
+        PINMUX_IPSR_DATA(IP5_26_24, INTC_IRQ3_N),
+        PINMUX_IPSR_MODSEL_DATA(IP5_26_24, VI3_CLK, SEL_VI3_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_26_24, SCIFA0_RTS_N_B, SEL_SCFA_1),
+        PINMUX_IPSR_MODSEL_DATA(IP5_26_24, HRX0_B, SEL_HSCIF0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP5_26_24, MSIOF0_SCK_B, SEL_SOF0_1),
+        PINMUX_IPSR_DATA(IP5_29_27, DREQ0_N),
+        PINMUX_IPSR_MODSEL_DATA(IP5_29_27, VI1_HSYNC_N, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_29_27, VI1_HSYNC_N_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP5_29_27, VI2_R7),
+        PINMUX_IPSR_MODSEL_DATA(IP5_29_27, SSI_SCK78_C, SEL_SSI7_2),
+        PINMUX_IPSR_MODSEL_DATA(IP5_29_27, SSI_WS78_B, SEL_SSI7_1),
+
+        PINMUX_IPSR_DATA(IP6_2_0, DACK0),
+        PINMUX_IPSR_DATA(IP6_2_0, IRQ0),
+        PINMUX_IPSR_DATA(IP6_2_0, INTC_IRQ0_N),
+        PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_WS78_C, SEL_SSI7_2),
+        PINMUX_IPSR_DATA(IP6_5_3, DREQ1_N),
+        PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB_B, SEL_VI1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SDATA7_C, SEL_SSI7_2),
+        PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1),
+        PINMUX_IPSR_DATA(IP6_8_6, DACK1),
+        PINMUX_IPSR_DATA(IP6_8_6, IRQ1),
+        PINMUX_IPSR_DATA(IP6_8_6, INTC_IRQ1_N),
+        PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_WS6_B, SEL_SSI6_1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2),
+        PINMUX_IPSR_DATA(IP6_10_9, DREQ2_N),
+        PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HSCK1_B, SEL_HSCIF1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HCTS0_N_B, SEL_HSCIF0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1),
+        PINMUX_IPSR_DATA(IP6_13_11, DACK2),
+        PINMUX_IPSR_DATA(IP6_13_11, IRQ2),
+        PINMUX_IPSR_DATA(IP6_13_11, INTC_IRQ2_N),
+        PINMUX_IPSR_MODSEL_DATA(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1),
+        PINMUX_IPSR_DATA(IP6_16_14, ETH_CRS_DV),
+        PINMUX_IPSR_DATA(IP6_16_14, RMII_CRS_DV),
+        PINMUX_IPSR_MODSEL_DATA(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3),
+        PINMUX_IPSR_MODSEL_DATA(IP6_16_14, GLO_Q0_C, SEL_GPS_2),
+        PINMUX_IPSR_MODSEL_DATA(IP6_16_14, SCL2_E, SEL_IIC2_4),
+        PINMUX_IPSR_MODSEL_DATA(IP6_16_14, SCL2_CIS_E, SEL_I2C2_4),
+        PINMUX_IPSR_DATA(IP6_19_17, ETH_RX_ER),
+        PINMUX_IPSR_DATA(IP6_19_17, RMII_RX_ER),
+        PINMUX_IPSR_MODSEL_DATA(IP6_19_17, STP_ISD_0_B, SEL_SSP_1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3),
+        PINMUX_IPSR_MODSEL_DATA(IP6_19_17, GLO_Q1_C, SEL_GPS_2),
+        PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SDA2_E, SEL_IIC2_4),
+        PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SDA2_CIS_E, SEL_I2C2_4),
+        PINMUX_IPSR_DATA(IP6_22_20, ETH_RXD0),
+        PINMUX_IPSR_DATA(IP6_22_20, RMII_RXD0),
+        PINMUX_IPSR_MODSEL_DATA(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3),
+        PINMUX_IPSR_MODSEL_DATA(IP6_22_20, GLO_I0_C, SEL_GPS_2),
+        PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6),
+        PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCK1_E, SEL_SCIF1_4),
+        PINMUX_IPSR_DATA(IP6_25_23, ETH_RXD1),
+        PINMUX_IPSR_DATA(IP6_25_23, RMII_RXD1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_25_23, HRX0_E, SEL_HSCIF0_4),
+        PINMUX_IPSR_MODSEL_DATA(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3),
+        PINMUX_IPSR_MODSEL_DATA(IP6_25_23, GLO_I1_C, SEL_GPS_2),
+        PINMUX_IPSR_MODSEL_DATA(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6),
+        PINMUX_IPSR_MODSEL_DATA(IP6_25_23, RX1_E, SEL_SCIF1_4),
+        PINMUX_IPSR_DATA(IP6_28_26, ETH_LINK),
+        PINMUX_IPSR_DATA(IP6_28_26, RMII_LINK),
+        PINMUX_IPSR_MODSEL_DATA(IP6_28_26, HTX0_E, SEL_HSCIF0_4),
+        PINMUX_IPSR_MODSEL_DATA(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6),
+        PINMUX_IPSR_MODSEL_DATA(IP6_28_26, TX1_E, SEL_SCIF1_4),
+        PINMUX_IPSR_DATA(IP6_31_29, ETH_REF_CLK),
+        PINMUX_IPSR_DATA(IP6_31_29, RMII_REF_CLK),
+        PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4),
+        PINMUX_IPSR_MODSEL_DATA(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HRX0_F, SEL_HSCIF0_5),
+
+        PINMUX_IPSR_DATA(IP7_2_0, ETH_MDIO),
+        PINMUX_IPSR_DATA(IP7_2_0, RMII_MDIO),
+        PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4),
+        PINMUX_IPSR_MODSEL_DATA(IP7_2_0, SIM0_D_C, SEL_SIM_2),
+        PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5),
+        PINMUX_IPSR_DATA(IP7_5_3, ETH_TXD1),
+        PINMUX_IPSR_DATA(IP7_5_3, RMII_TXD1),
+        PINMUX_IPSR_MODSEL_DATA(IP7_5_3, HTX0_F, SEL_HSCIF0_4),
+        PINMUX_IPSR_MODSEL_DATA(IP7_5_3, BPFCLK_G, SEL_SIM_2),
+        PINMUX_IPSR_MODSEL_DATA(IP7_5_3, RDS_CLK_F, SEL_HSCIF0_5),
+        PINMUX_IPSR_DATA(IP7_7_6, ETH_TX_EN),
+        PINMUX_IPSR_DATA(IP7_7_6, RMII_TX_EN),
+        PINMUX_IPSR_MODSEL_DATA(IP7_7_6, SIM0_CLK_C, SEL_SIM_2),
+        PINMUX_IPSR_MODSEL_DATA(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5),
+        PINMUX_IPSR_DATA(IP7_9_8, ETH_MAGIC),
+        PINMUX_IPSR_DATA(IP7_9_8, RMII_MAGIC),
+        PINMUX_IPSR_MODSEL_DATA(IP7_9_8, SIM0_RST_C, SEL_SIM_2),
+        PINMUX_IPSR_DATA(IP7_12_10, ETH_TXD0),
+        PINMUX_IPSR_DATA(IP7_12_10, RMII_TXD0),
+        PINMUX_IPSR_MODSEL_DATA(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1),
+        PINMUX_IPSR_MODSEL_DATA(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2),
+        PINMUX_IPSR_MODSEL_DATA(IP7_12_10, GLO_SCLK_C, SEL_GPS_2),
+        PINMUX_IPSR_DATA(IP7_15_13, ETH_MDC),
+        PINMUX_IPSR_DATA(IP7_15_13, RMII_MDC),
+        PINMUX_IPSR_MODSEL_DATA(IP7_15_13, STP_ISD_1_B, SEL_SSP_1),
+        PINMUX_IPSR_MODSEL_DATA(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2),
+        PINMUX_IPSR_MODSEL_DATA(IP7_15_13, GLO_SDATA_C, SEL_GPS_2),
+        PINMUX_IPSR_DATA(IP7_18_16, PWM0),
+        PINMUX_IPSR_MODSEL_DATA(IP7_18_16, SCIFA2_SCK_C, SEL_SCIFA2_2),
+        PINMUX_IPSR_MODSEL_DATA(IP7_18_16, STP_ISEN_1_B, SEL_SSP_1),
+        PINMUX_IPSR_MODSEL_DATA(IP7_18_16, TS_SDAT1_C, SEL_TSIF1_2),
+        PINMUX_IPSR_MODSEL_DATA(IP7_18_16, GLO_SS_C, SEL_GPS_2),
+        PINMUX_IPSR_DATA(IP7_21_19, PWM1),
+        PINMUX_IPSR_MODSEL_DATA(IP7_21_19, SCIFA2_TXD_C, SEL_SCIFA2_2),
+        PINMUX_IPSR_MODSEL_DATA(IP7_21_19, STP_ISSYNC_1_B, SEL_SSP_1),
+        PINMUX_IPSR_MODSEL_DATA(IP7_21_19, TS_SCK1_C, SEL_TSIF1_2),
+        PINMUX_IPSR_MODSEL_DATA(IP7_21_19, GLO_RFON_C, SEL_GPS_2),
+        PINMUX_IPSR_DATA(IP7_21_19, PCMOE_N),
+        PINMUX_IPSR_DATA(IP7_24_22, PWM2),
+        PINMUX_IPSR_DATA(IP7_24_22, PWMFSW0),
+        PINMUX_IPSR_MODSEL_DATA(IP7_24_22, SCIFA2_RXD_C, SEL_SCIFA2_2),
+        PINMUX_IPSR_DATA(IP7_24_22, PCMWE_N),
+        PINMUX_IPSR_MODSEL_DATA(IP7_24_22, IECLK_C, SEL_IEB_2),
+        PINMUX_IPSR_DATA(IP7_26_25, DU1_DOTCLKIN),
+        PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKC),
+        PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKOUT_C),
+        PINMUX_IPSR_MODSEL_DATA(IP7_28_27, VI0_CLK, SEL_VI0_0),
+        PINMUX_IPSR_DATA(IP7_28_27, ATACS00_N),
+        PINMUX_IPSR_DATA(IP7_28_27, AVB_RXD1),
+        PINMUX_IPSR_DATA(IP7_28_27, MII_RXD1),
+        PINMUX_IPSR_MODSEL_DATA(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0),
+        PINMUX_IPSR_DATA(IP7_30_29, ATACS10_N),
+        PINMUX_IPSR_DATA(IP7_30_29, AVB_RXD2),
+        PINMUX_IPSR_DATA(IP7_30_29, MII_RXD2),
+
+        PINMUX_IPSR_MODSEL_DATA(IP8_1_0, VI0_DATA1_VI0_B1, SEL_VI0_0),
+        PINMUX_IPSR_DATA(IP8_1_0, ATARD0_N),
+        PINMUX_IPSR_DATA(IP8_1_0, AVB_RXD3),
+        PINMUX_IPSR_DATA(IP8_1_0, MII_RXD3),
+        PINMUX_IPSR_MODSEL_DATA(IP8_3_2, VI0_DATA2_VI0_B2, SEL_VI0_0),
+        PINMUX_IPSR_DATA(IP8_3_2, ATAWR0_N),
+        PINMUX_IPSR_DATA(IP8_3_2, AVB_RXD4),
+        PINMUX_IPSR_MODSEL_DATA(IP8_5_4, VI0_DATA3_VI0_B3, SEL_VI0_0),
+        PINMUX_IPSR_DATA(IP8_5_4, ATADIR0_N),
+        PINMUX_IPSR_DATA(IP8_5_4, AVB_RXD5),
+        PINMUX_IPSR_MODSEL_DATA(IP8_7_6, VI0_DATA4_VI0_B4, SEL_VI0_0),
+        PINMUX_IPSR_DATA(IP8_7_6, ATAG0_N),
+        PINMUX_IPSR_DATA(IP8_7_6, AVB_RXD6),
+        PINMUX_IPSR_MODSEL_DATA(IP8_9_8, VI0_DATA5_VI0_B5, SEL_VI0_0),
+        PINMUX_IPSR_DATA(IP8_9_8, EX_WAIT1),
+        PINMUX_IPSR_DATA(IP8_9_8, AVB_RXD7),
+        PINMUX_IPSR_MODSEL_DATA(IP8_11_10, VI0_DATA6_VI0_B6, SEL_VI0_0),
+        PINMUX_IPSR_DATA(IP8_11_10, AVB_RX_ER),
+        PINMUX_IPSR_DATA(IP8_11_10, MII_RX_ER),
+        PINMUX_IPSR_MODSEL_DATA(IP8_13_12, VI0_DATA7_VI0_B7, SEL_VI0_0),
+        PINMUX_IPSR_DATA(IP8_13_12, AVB_RX_CLK),
+        PINMUX_IPSR_DATA(IP8_13_12, MII_RX_CLK),
+        PINMUX_IPSR_MODSEL_DATA(IP8_15_14, VI1_CLK, SEL_VI1_0),
+        PINMUX_IPSR_DATA(IP8_15_14, AVB_RX_DV),
+        PINMUX_IPSR_DATA(IP8_15_14, MII_RX_DV),
+        PINMUX_IPSR_MODSEL_DATA(IP8_17_16, VI1_DATA0_VI1_B0, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP8_17_16, SCIFA1_SCK_D, SEL_SCIFA1_3),
+        PINMUX_IPSR_DATA(IP8_17_16, AVB_CRS),
+        PINMUX_IPSR_DATA(IP8_17_16, MII_CRS),
+        PINMUX_IPSR_MODSEL_DATA(IP8_19_18, VI1_DATA1_VI1_B1, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP8_19_18, SCIFA1_RXD_D, SEL_SCIFA1_3),
+        PINMUX_IPSR_DATA(IP8_19_18, AVB_MDC),
+        PINMUX_IPSR_DATA(IP8_19_18, MII_MDC),
+        PINMUX_IPSR_MODSEL_DATA(IP8_21_20, VI1_DATA2_VI1_B2, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP8_21_20, SCIFA1_TXD_D, SEL_SCIFA1_3),
+        PINMUX_IPSR_DATA(IP8_21_20, AVB_MDIO),
+        PINMUX_IPSR_DATA(IP8_21_20, MII_MDIO),
+        PINMUX_IPSR_MODSEL_DATA(IP8_23_22, VI1_DATA3_VI1_B3, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP8_23_22, SCIFA1_CTS_N_D, SEL_SCIFA1_3),
+        PINMUX_IPSR_DATA(IP8_23_22, AVB_GTX_CLK),
+        PINMUX_IPSR_MODSEL_DATA(IP8_25_24, VI1_DATA4_VI1_B4, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP8_25_24, SCIFA1_RTS_N_D, SEL_SCIFA1_3),
+        PINMUX_IPSR_DATA(IP8_25_24, AVB_MAGIC),
+        PINMUX_IPSR_DATA(IP8_25_24, MII_MAGIC),
+        PINMUX_IPSR_MODSEL_DATA(IP8_26, VI1_DATA5_VI1_B5, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP8_26, AVB_PHY_INT, SEL_SCIFA1_3),
+        PINMUX_IPSR_MODSEL_DATA(IP8_27, VI1_DATA6_VI1_B6, SEL_VI1_0),
+        PINMUX_IPSR_DATA(IP8_27, AVB_GTXREFCLK),
+        PINMUX_IPSR_DATA(IP8_28, SD0_CLK),
+        PINMUX_IPSR_MODSEL_DATA(IP8_28, VI1_DATA0_VI1_B0_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP8_30_29, SD0_CMD),
+        PINMUX_IPSR_MODSEL_DATA(IP8_30_29, SCIFB1_SCK_B, SEL_SCIFB1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP8_30_29, VI1_DATA1_VI1_B1_B, SEL_VI1_1),
+
+        PINMUX_IPSR_DATA(IP9_1_0, SD0_DAT0),
+        PINMUX_IPSR_MODSEL_DATA(IP9_1_0, SCIFB1_RXD_B, SEL_SCIFB1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP9_1_0, VI1_DATA2_VI1_B2_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP9_3_2, SD0_DAT1),
+        PINMUX_IPSR_MODSEL_DATA(IP9_3_2, SCIFB1_TXD_B, SEL_SCIFB1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP9_3_2, VI1_DATA3_VI1_B3_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP9_5_4, SD0_DAT2),
+        PINMUX_IPSR_MODSEL_DATA(IP9_5_4, SCIFB1_CTS_N_B, SEL_SCIFB1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP9_5_4, VI1_DATA4_VI1_B4_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP9_7_6, SD0_DAT3),
+        PINMUX_IPSR_MODSEL_DATA(IP9_7_6, SCIFB1_RTS_N_B, SEL_SCIFB1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP9_7_6, VI1_DATA5_VI1_B5_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP9_11_8, SD0_CD),
+        PINMUX_IPSR_DATA(IP9_11_8, MMC0_D6),
+        PINMUX_IPSR_MODSEL_DATA(IP9_11_8, TS_SDEN0_B, SEL_TSIF0_1),
+        PINMUX_IPSR_DATA(IP9_11_8, USB0_EXTP),
+        PINMUX_IPSR_MODSEL_DATA(IP9_11_8, GLO_SCLK, SEL_GPS_0),
+        PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI1_DATA6_VI1_B6_B, SEL_VI1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP9_11_8, SCL1_B, SEL_IIC1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP9_11_8, SCL1_CIS_B, SEL_I2C1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI2_DATA6_VI2_B6_B, SEL_VI2_1),
+        PINMUX_IPSR_DATA(IP9_15_12, SD0_WP),
+        PINMUX_IPSR_DATA(IP9_15_12, MMC0_D7),
+        PINMUX_IPSR_MODSEL_DATA(IP9_15_12, TS_SPSYNC0_B, SEL_TSIF0_1),
+        PINMUX_IPSR_DATA(IP9_15_12, USB0_IDIN),
+        PINMUX_IPSR_MODSEL_DATA(IP9_15_12, GLO_SDATA, SEL_GPS_0),
+        PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI1_DATA7_VI1_B7_B, SEL_VI1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP9_15_12, SDA1_B, SEL_IIC1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP9_15_12, SDA1_CIS_B, SEL_I2C1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI2_DATA7_VI2_B7_B, SEL_VI2_1),
+        PINMUX_IPSR_DATA(IP9_17_16, SD1_CLK),
+        PINMUX_IPSR_DATA(IP9_17_16, AVB_TX_EN),
+        PINMUX_IPSR_DATA(IP9_17_16, MII_TX_EN),
+        PINMUX_IPSR_DATA(IP9_19_18, SD1_CMD),
+        PINMUX_IPSR_DATA(IP9_19_18, AVB_TX_ER),
+        PINMUX_IPSR_DATA(IP9_19_18, MII_TX_ER),
+        PINMUX_IPSR_MODSEL_DATA(IP9_19_18, SCIFB0_SCK_B, SEL_SCIFB_1),
+        PINMUX_IPSR_DATA(IP9_21_20, SD1_DAT0),
+        PINMUX_IPSR_DATA(IP9_21_20, AVB_TX_CLK),
+        PINMUX_IPSR_DATA(IP9_21_20, MII_TX_CLK),
+        PINMUX_IPSR_MODSEL_DATA(IP9_21_20, SCIFB0_RXD_B, SEL_SCIFB_1),
+        PINMUX_IPSR_DATA(IP9_23_22, SD1_DAT1),
+        PINMUX_IPSR_DATA(IP9_23_22, AVB_LINK),
+        PINMUX_IPSR_DATA(IP9_23_22, MII_LINK),
+        PINMUX_IPSR_MODSEL_DATA(IP9_23_22, SCIFB0_TXD_B, SEL_SCIFB_1),
+        PINMUX_IPSR_DATA(IP9_25_24, SD1_DAT2),
+        PINMUX_IPSR_DATA(IP9_25_24, AVB_COL),
+        PINMUX_IPSR_DATA(IP9_25_24, MII_COL),
+        PINMUX_IPSR_MODSEL_DATA(IP9_25_24, SCIFB0_CTS_N_B, SEL_SCIFB_1),
+        PINMUX_IPSR_DATA(IP9_27_26, SD1_DAT3),
+        PINMUX_IPSR_DATA(IP9_27_26, AVB_RXD0),
+        PINMUX_IPSR_DATA(IP9_27_26, MII_RXD0),
+        PINMUX_IPSR_MODSEL_DATA(IP9_27_26, SCIFB0_RTS_N_B, SEL_SCIFB_1),
+        PINMUX_IPSR_DATA(IP9_31_28, SD1_CD),
+        PINMUX_IPSR_DATA(IP9_31_28, MMC1_D6),
+        PINMUX_IPSR_MODSEL_DATA(IP9_31_28, TS_SDEN1, SEL_TSIF1_0),
+        PINMUX_IPSR_DATA(IP9_31_28, USB1_EXTP),
+        PINMUX_IPSR_MODSEL_DATA(IP9_31_28, GLO_SS, SEL_GPS_0),
+        PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI0_CLK_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SCL2_D, SEL_IIC2_3),
+        PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SCL2_CIS_D, SEL_I2C2_3),
+        PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SIM0_CLK_B, SEL_SIM_1),
+        PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI3_CLK_B, SEL_VI3_1),
+
+        PINMUX_IPSR_DATA(IP10_3_0, SD1_WP),
+        PINMUX_IPSR_DATA(IP10_3_0, MMC1_D7),
+        PINMUX_IPSR_MODSEL_DATA(IP10_3_0, TS_SPSYNC1, SEL_TSIF1_0),
+        PINMUX_IPSR_DATA(IP10_3_0, USB1_IDIN),
+        PINMUX_IPSR_MODSEL_DATA(IP10_3_0, GLO_RFON, SEL_GPS_0),
+        PINMUX_IPSR_MODSEL_DATA(IP10_3_0, VI1_CLK_B, SEL_VI1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SDA2_D, SEL_IIC2_3),
+        PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SDA2_CIS_D, SEL_I2C2_3),
+        PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SIM0_D_B, SEL_SIM_1),
+        PINMUX_IPSR_DATA(IP10_6_4, SD2_CLK),
+        PINMUX_IPSR_DATA(IP10_6_4, MMC0_CLK),
+        PINMUX_IPSR_MODSEL_DATA(IP10_6_4, SIM0_CLK, SEL_SIM_0),
+        PINMUX_IPSR_MODSEL_DATA(IP10_6_4, VI0_DATA0_VI0_B0_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_6_4, TS_SDEN0_C, SEL_TSIF0_2),
+        PINMUX_IPSR_MODSEL_DATA(IP10_6_4, GLO_SCLK_B, SEL_GPS_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_6_4, VI3_DATA0_B, SEL_VI3_1),
+        PINMUX_IPSR_DATA(IP10_10_7, SD2_CMD),
+        PINMUX_IPSR_DATA(IP10_10_7, MMC0_CMD),
+        PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SIM0_D, SEL_SIM_0),
+        PINMUX_IPSR_MODSEL_DATA(IP10_10_7, VI0_DATA1_VI0_B1_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SCIFB1_SCK_E, SEL_SCIFB1_4),
+        PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SCK1_D, SEL_SCIF1_3),
+        PINMUX_IPSR_MODSEL_DATA(IP10_10_7, TS_SPSYNC0_C, SEL_TSIF0_2),
+        PINMUX_IPSR_MODSEL_DATA(IP10_10_7, GLO_SDATA_B, SEL_GPS_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_10_7, VI3_DATA1_B, SEL_VI3_1),
+        PINMUX_IPSR_DATA(IP10_14_11, SD2_DAT0),
+        PINMUX_IPSR_DATA(IP10_14_11, MMC0_D0),
+        PINMUX_IPSR_MODSEL_DATA(IP10_14_11, FMCLK_B, SEL_FM_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_14_11, VI0_DATA2_VI0_B2_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_14_11, SCIFB1_RXD_E, SEL_SCIFB1_4),
+        PINMUX_IPSR_MODSEL_DATA(IP10_14_11, RX1_D, SEL_SCIF1_3),
+        PINMUX_IPSR_MODSEL_DATA(IP10_14_11, TS_SDAT0_C, SEL_TSIF0_2),
+        PINMUX_IPSR_MODSEL_DATA(IP10_14_11, GLO_SS_B, SEL_GPS_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_14_11, VI3_DATA2_B, SEL_VI3_1),
+        PINMUX_IPSR_DATA(IP10_18_15, SD2_DAT1),
+        PINMUX_IPSR_DATA(IP10_18_15, MMC0_D1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_18_15, FMIN_B, SEL_FM_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_18_15, RDS_DATA, SEL_RDS_0),
+        PINMUX_IPSR_MODSEL_DATA(IP10_18_15, VI0_DATA3_VI0_B3_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_18_15, SCIFB1_TXD_E, SEL_SCIFB1_4),
+        PINMUX_IPSR_MODSEL_DATA(IP10_18_15, TX1_D, SEL_SCIF1_3),
+        PINMUX_IPSR_MODSEL_DATA(IP10_18_15, TS_SCK0_C, SEL_TSIF0_2),
+        PINMUX_IPSR_MODSEL_DATA(IP10_18_15, GLO_RFON_B, SEL_GPS_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_18_15, VI3_DATA3_B, SEL_VI3_1),
+        PINMUX_IPSR_DATA(IP10_22_19, SD2_DAT2),
+        PINMUX_IPSR_DATA(IP10_22_19, MMC0_D2),
+        PINMUX_IPSR_MODSEL_DATA(IP10_22_19, BPFCLK_B, SEL_FM_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_22_19, RDS_CLK, SEL_RDS_0),
+        PINMUX_IPSR_MODSEL_DATA(IP10_22_19, VI0_DATA4_VI0_B4_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_22_19, HRX0_D, SEL_HSCIF0_3),
+        PINMUX_IPSR_MODSEL_DATA(IP10_22_19, TS_SDEN1_B, SEL_TSIF1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_22_19, GLO_Q0_B, SEL_GPS_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_22_19, VI3_DATA4_B, SEL_VI3_1),
+        PINMUX_IPSR_DATA(IP10_25_23, SD2_DAT3),
+        PINMUX_IPSR_DATA(IP10_25_23, MMC0_D3),
+        PINMUX_IPSR_MODSEL_DATA(IP10_25_23, SIM0_RST, SEL_SIM_0),
+        PINMUX_IPSR_MODSEL_DATA(IP10_25_23, VI0_DATA5_VI0_B5_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_25_23, HTX0_D, SEL_HSCIF0_3),
+        PINMUX_IPSR_MODSEL_DATA(IP10_25_23, TS_SPSYNC1_B, SEL_TSIF1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_25_23, GLO_Q1_B, SEL_GPS_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_25_23, VI3_DATA5_B, SEL_VI3_1),
+        PINMUX_IPSR_DATA(IP10_29_26, SD2_CD),
+        PINMUX_IPSR_DATA(IP10_29_26, MMC0_D4),
+        PINMUX_IPSR_MODSEL_DATA(IP10_29_26, TS_SDAT0_B, SEL_TSIF0_1),
+        PINMUX_IPSR_DATA(IP10_29_26, USB2_EXTP),
+        PINMUX_IPSR_MODSEL_DATA(IP10_29_26, GLO_I0, SEL_GPS_0),
+        PINMUX_IPSR_MODSEL_DATA(IP10_29_26, VI0_DATA6_VI0_B6_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_29_26, HCTS0_N_D, SEL_HSCIF0_3),
+        PINMUX_IPSR_MODSEL_DATA(IP10_29_26, TS_SDAT1_B, SEL_TSIF1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_29_26, GLO_I0_B, SEL_GPS_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_29_26, VI3_DATA6_B, SEL_VI3_1),
+
+        PINMUX_IPSR_DATA(IP11_3_0, SD2_WP),
+        PINMUX_IPSR_DATA(IP11_3_0, MMC0_D5),
+        PINMUX_IPSR_MODSEL_DATA(IP11_3_0, TS_SCK0_B, SEL_TSIF0_1),
+        PINMUX_IPSR_DATA(IP11_3_0, USB2_IDIN),
+        PINMUX_IPSR_MODSEL_DATA(IP11_3_0, GLO_I1, SEL_GPS_0),
+        PINMUX_IPSR_MODSEL_DATA(IP11_3_0, VI0_DATA7_VI0_B7_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP11_3_0, HRTS0_N_D, SEL_HSCIF0_3),
+        PINMUX_IPSR_MODSEL_DATA(IP11_3_0, TS_SCK1_B, SEL_TSIF1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP11_3_0, GLO_I1_B, SEL_GPS_1),
+        PINMUX_IPSR_MODSEL_DATA(IP11_3_0, VI3_DATA7_B, SEL_VI3_1),
+        PINMUX_IPSR_DATA(IP11_4, SD3_CLK),
+        PINMUX_IPSR_DATA(IP11_4, MMC1_CLK),
+        PINMUX_IPSR_DATA(IP11_6_5, SD3_CMD),
+        PINMUX_IPSR_DATA(IP11_6_5, MMC1_CMD),
+        PINMUX_IPSR_DATA(IP11_6_5, MTS_N),
+        PINMUX_IPSR_DATA(IP11_8_7, SD3_DAT0),
+        PINMUX_IPSR_DATA(IP11_8_7, MMC1_D0),
+        PINMUX_IPSR_DATA(IP11_8_7, STM_N),
+        PINMUX_IPSR_DATA(IP11_10_9, SD3_DAT1),
+        PINMUX_IPSR_DATA(IP11_10_9, MMC1_D1),
+        PINMUX_IPSR_DATA(IP11_10_9, MDATA),
+        PINMUX_IPSR_DATA(IP11_12_11, SD3_DAT2),
+        PINMUX_IPSR_DATA(IP11_12_11, MMC1_D2),
+        PINMUX_IPSR_DATA(IP11_12_11, SDATA),
+        PINMUX_IPSR_DATA(IP11_14_13, SD3_DAT3),
+        PINMUX_IPSR_DATA(IP11_14_13, MMC1_D3),
+        PINMUX_IPSR_DATA(IP11_14_13, SCKZ),
+        PINMUX_IPSR_DATA(IP11_17_15, SD3_CD),
+        PINMUX_IPSR_DATA(IP11_17_15, MMC1_D4),
+        PINMUX_IPSR_MODSEL_DATA(IP11_17_15, TS_SDAT1, SEL_TSIF1_0),
+        PINMUX_IPSR_DATA(IP11_17_15, VSP),
+        PINMUX_IPSR_MODSEL_DATA(IP11_17_15, GLO_Q0, SEL_GPS_0),
+        PINMUX_IPSR_MODSEL_DATA(IP11_17_15, SIM0_RST_B, SEL_SIM_1),
+        PINMUX_IPSR_DATA(IP11_21_18, SD3_WP),
+        PINMUX_IPSR_DATA(IP11_21_18, MMC1_D5),
+        PINMUX_IPSR_MODSEL_DATA(IP11_21_18, TS_SCK1, SEL_TSIF1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP11_21_18, GLO_Q1, SEL_GPS_0),
+        PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_C, SEL_FM_2),
+        PINMUX_IPSR_MODSEL_DATA(IP11_21_18, RDS_DATA_B, SEL_RDS_1),
+        PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_E, SEL_FM_4),
+        PINMUX_IPSR_MODSEL_DATA(IP11_21_18, RDS_DATA_D, SEL_RDS_3),
+        PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_F, SEL_FM_5),
+        PINMUX_IPSR_MODSEL_DATA(IP11_21_18, RDS_DATA_E, SEL_RDS_4),
+        PINMUX_IPSR_DATA(IP11_23_22, MLB_CLK),
+        PINMUX_IPSR_MODSEL_DATA(IP11_23_22, SCL2_B, SEL_IIC2_1),
+        PINMUX_IPSR_MODSEL_DATA(IP11_23_22, SCL2_CIS_B, SEL_I2C2_1),
+        PINMUX_IPSR_DATA(IP11_26_24, MLB_SIG),
+        PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SCIFB1_RXD_D, SEL_SCIFB1_3),
+        PINMUX_IPSR_MODSEL_DATA(IP11_26_24, RX1_C, SEL_SCIF1_2),
+        PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SDA2_B, SEL_IIC2_1),
+        PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SDA2_CIS_B, SEL_I2C2_1),
+        PINMUX_IPSR_DATA(IP11_29_27, MLB_DAT),
+        PINMUX_IPSR_DATA(IP11_29_27, SPV_EVEN),
+        PINMUX_IPSR_MODSEL_DATA(IP11_29_27, SCIFB1_TXD_D, SEL_SCIFB1_3),
+        PINMUX_IPSR_MODSEL_DATA(IP11_29_27, TX1_C, SEL_SCIF1_2),
+        PINMUX_IPSR_MODSEL_DATA(IP11_29_27, BPFCLK_C, SEL_FM_2),
+        PINMUX_IPSR_MODSEL_DATA(IP11_29_27, RDS_CLK_B, SEL_RDS_1),
+        PINMUX_IPSR_DATA(IP11_31_30, SSI_SCK0129),
+        PINMUX_IPSR_MODSEL_DATA(IP11_31_30, CAN_CLK_B, SEL_CANCLK_1),
+        PINMUX_IPSR_DATA(IP11_31_30, MOUT0),
+
+        PINMUX_IPSR_DATA(IP12_1_0, SSI_WS0129),
+        PINMUX_IPSR_MODSEL_DATA(IP12_1_0, CAN0_TX_B, SEL_CAN0_1),
+        PINMUX_IPSR_DATA(IP12_1_0, MOUT1),
+        PINMUX_IPSR_DATA(IP12_3_2, SSI_SDATA0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_3_2, CAN0_RX_B, SEL_CAN0_1),
+        PINMUX_IPSR_DATA(IP12_3_2, MOUT2),
+        PINMUX_IPSR_DATA(IP12_5_4, SSI_SDATA1),
+        PINMUX_IPSR_MODSEL_DATA(IP12_5_4, CAN1_TX_B, SEL_CAN1_1),
+        PINMUX_IPSR_DATA(IP12_5_4, MOUT5),
+        PINMUX_IPSR_DATA(IP12_7_6, SSI_SDATA2),
+        PINMUX_IPSR_MODSEL_DATA(IP12_7_6, CAN1_RX_B, SEL_CAN1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP12_7_6, CAN1_TX_B, SEL_CAN1_1),
+        PINMUX_IPSR_DATA(IP12_7_6, MOUT6),
+        PINMUX_IPSR_DATA(IP12_10_8, SSI_SCK34),
+        PINMUX_IPSR_DATA(IP12_10_8, STP_OPWM_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_10_8, SCIFB0_SCK, SEL_SCIFB_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_10_8, MSIOF1_SCK, SEL_SOF1_0),
+        PINMUX_IPSR_DATA(IP12_10_8, CAN_DEBUG_HW_TRIGGER),
+        PINMUX_IPSR_DATA(IP12_13_11, SSI_WS34),
+        PINMUX_IPSR_MODSEL_DATA(IP12_13_11, STP_IVCXO27_0, SEL_SSP_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_13_11, SCIFB0_RXD, SEL_SCIFB_0),
+        PINMUX_IPSR_DATA(IP12_13_11, MSIOF1_SYNC),
+        PINMUX_IPSR_DATA(IP12_13_11, CAN_STEP0),
+        PINMUX_IPSR_DATA(IP12_16_14, SSI_SDATA3),
+        PINMUX_IPSR_MODSEL_DATA(IP12_16_14, STP_ISCLK_0, SEL_SSP_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_16_14, SCIFB0_TXD, SEL_SCIFB_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_16_14, MSIOF1_SS1, SEL_SOF1_0),
+        PINMUX_IPSR_DATA(IP12_16_14, CAN_TXCLK),
+        PINMUX_IPSR_DATA(IP12_19_17, SSI_SCK4),
+        PINMUX_IPSR_MODSEL_DATA(IP12_19_17, STP_ISD_0, SEL_SSP_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_19_17, SCIFB0_CTS_N, SEL_SCIFB_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_19_17, MSIOF1_SS2, SEL_SOF1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_19_17, SSI_SCK5_C, SEL_SSI5_2),
+        PINMUX_IPSR_DATA(IP12_19_17, CAN_DEBUGOUT0),
+        PINMUX_IPSR_DATA(IP12_22_20, SSI_WS4),
+        PINMUX_IPSR_MODSEL_DATA(IP12_22_20, STP_ISEN_0, SEL_SSP_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_22_20, SCIFB0_RTS_N, SEL_SCIFB_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_22_20, MSIOF1_TXD, SEL_SOF1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_22_20, SSI_WS5_C, SEL_SSI5_2),
+        PINMUX_IPSR_DATA(IP12_22_20, CAN_DEBUGOUT1),
+        PINMUX_IPSR_DATA(IP12_24_23, SSI_SDATA4),
+        PINMUX_IPSR_MODSEL_DATA(IP12_24_23, STP_ISSYNC_0, SEL_SSP_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_24_23, MSIOF1_RXD, SEL_SOF1_0),
+        PINMUX_IPSR_DATA(IP12_24_23, CAN_DEBUGOUT2),
+        PINMUX_IPSR_MODSEL_DATA(IP12_27_25, SSI_SCK5, SEL_SSI5_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_27_25, SCIFB1_SCK, SEL_SCIFB1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_27_25, IERX_B, SEL_IEB_1),
+        PINMUX_IPSR_DATA(IP12_27_25, DU2_EXHSYNC_DU2_HSYNC),
+        PINMUX_IPSR_DATA(IP12_27_25, QSTH_QHS),
+        PINMUX_IPSR_DATA(IP12_27_25, CAN_DEBUGOUT3),
+        PINMUX_IPSR_MODSEL_DATA(IP12_30_28, SSI_WS5, SEL_SSI5_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_30_28, SCIFB1_RXD, SEL_SCIFB1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_30_28, IECLK_B, SEL_IEB_1),
+        PINMUX_IPSR_DATA(IP12_30_28, DU2_EXVSYNC_DU2_VSYNC),
+        PINMUX_IPSR_DATA(IP12_30_28, QSTB_QHE),
+        PINMUX_IPSR_DATA(IP12_30_28, CAN_DEBUGOUT4),
+
+        PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SSI_SDATA5, SEL_SSI5_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SCIFB1_TXD, SEL_SCIFB1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_2_0, IETX_B, SEL_IEB_1),
+        PINMUX_IPSR_DATA(IP13_2_0, DU2_DR2),
+        PINMUX_IPSR_DATA(IP13_2_0, LCDOUT2),
+        PINMUX_IPSR_DATA(IP13_2_0, CAN_DEBUGOUT5),
+        PINMUX_IPSR_MODSEL_DATA(IP13_6_3, SSI_SCK6, SEL_SSI6_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_6_3, SCIFB1_CTS_N, SEL_SCIFB1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_6_3, BPFCLK_D, SEL_FM_3),
+        PINMUX_IPSR_MODSEL_DATA(IP13_6_3, RDS_CLK_C, SEL_RDS_2),
+        PINMUX_IPSR_DATA(IP13_6_3, DU2_DR3),
+        PINMUX_IPSR_DATA(IP13_6_3, LCDOUT3),
+        PINMUX_IPSR_DATA(IP13_6_3, CAN_DEBUGOUT6),
+        PINMUX_IPSR_MODSEL_DATA(IP13_6_3, BPFCLK_F, SEL_FM_5),
+        PINMUX_IPSR_MODSEL_DATA(IP13_6_3, RDS_CLK_E, SEL_RDS_4),
+        PINMUX_IPSR_MODSEL_DATA(IP13_9_7, SSI_WS6, SEL_SSI6_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_9_7, SCIFB1_RTS_N, SEL_SCIFB1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_9_7, CAN0_TX_D, SEL_CAN0_3),
+        PINMUX_IPSR_DATA(IP13_9_7, DU2_DR4),
+        PINMUX_IPSR_DATA(IP13_9_7, LCDOUT4),
+        PINMUX_IPSR_DATA(IP13_9_7, CAN_DEBUGOUT7),
+        PINMUX_IPSR_MODSEL_DATA(IP13_12_10, SSI_SDATA6, SEL_SSI6_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_12_10, FMIN_D, SEL_FM_3),
+        PINMUX_IPSR_MODSEL_DATA(IP13_12_10, RDS_DATA_C, SEL_RDS_2),
+        PINMUX_IPSR_DATA(IP13_12_10, DU2_DR5),
+        PINMUX_IPSR_DATA(IP13_12_10, LCDOUT5),
+        PINMUX_IPSR_DATA(IP13_12_10, CAN_DEBUGOUT8),
+        PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SSI_SCK78, SEL_SSI7_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_15_13, STP_IVCXO27_1, SEL_SSP_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SCK1, SEL_SCIF1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SCIFA1_SCK, SEL_SCIFA1_0),
+        PINMUX_IPSR_DATA(IP13_15_13, DU2_DR6),
+        PINMUX_IPSR_DATA(IP13_15_13, LCDOUT6),
+        PINMUX_IPSR_DATA(IP13_15_13, CAN_DEBUGOUT9),
+        PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SSI_WS78, SEL_SSI7_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_18_16, STP_ISCLK_1, SEL_SSP_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SCIFB2_SCK, SEL_SCIFB2_0),
+        PINMUX_IPSR_DATA(IP13_18_16, SCIFA2_CTS_N),
+        PINMUX_IPSR_DATA(IP13_18_16, DU2_DR7),
+        PINMUX_IPSR_DATA(IP13_18_16, LCDOUT7),
+        PINMUX_IPSR_DATA(IP13_18_16, CAN_DEBUGOUT10),
+        PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SSI_SDATA7, SEL_SSI7_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_22_19, STP_ISD_1, SEL_SSP_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SCIFB2_RXD, SEL_SCIFB2_0),
+        PINMUX_IPSR_DATA(IP13_22_19, SCIFA2_RTS_N),
+        PINMUX_IPSR_DATA(IP13_22_19, TCLK2),
+        PINMUX_IPSR_DATA(IP13_22_19, QSTVA_QVS),
+        PINMUX_IPSR_DATA(IP13_22_19, CAN_DEBUGOUT11),
+        PINMUX_IPSR_MODSEL_DATA(IP13_22_19, BPFCLK_E, SEL_FM_4),
+        PINMUX_IPSR_MODSEL_DATA(IP13_22_19, RDS_CLK_D, SEL_RDS_3),
+        PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SSI_SDATA7_B, SEL_SSI7_1),
+        PINMUX_IPSR_MODSEL_DATA(IP13_22_19, FMIN_G, SEL_FM_6),
+        PINMUX_IPSR_MODSEL_DATA(IP13_22_19, RDS_DATA_F, SEL_RDS_5),
+        PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SSI_SDATA8, SEL_SSI8_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_25_23, STP_ISEN_1, SEL_SSP_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SCIFB2_TXD, SEL_SCIFB2_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_25_23, CAN0_TX_C, SEL_CAN0_2),
+        PINMUX_IPSR_DATA(IP13_25_23, CAN_DEBUGOUT12),
+        PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SSI_SDATA8_B, SEL_SSI8_1),
+        PINMUX_IPSR_DATA(IP13_28_26, SSI_SDATA9),
+        PINMUX_IPSR_MODSEL_DATA(IP13_28_26, STP_ISSYNC_1, SEL_SSP_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_28_26, SCIFB2_CTS_N, SEL_SCIFB2_0),
+        PINMUX_IPSR_DATA(IP13_28_26, SSI_WS1),
+        PINMUX_IPSR_MODSEL_DATA(IP13_28_26, SSI_SDATA5_C, SEL_SSI5_2),
+        PINMUX_IPSR_DATA(IP13_28_26, CAN_DEBUGOUT13),
+        PINMUX_IPSR_DATA(IP13_30_29, AUDIO_CLKA),
+        PINMUX_IPSR_MODSEL_DATA(IP13_30_29, SCIFB2_RTS_N, SEL_SCIFB2_0),
+        PINMUX_IPSR_DATA(IP13_30_29, CAN_DEBUGOUT14),
+
+        PINMUX_IPSR_DATA(IP14_2_0, AUDIO_CLKB),
+        PINMUX_IPSR_MODSEL_DATA(IP14_2_0, SCIF_CLK, SEL_SCIFCLK_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_2_0, CAN0_RX_D, SEL_CAN0_3),
+        PINMUX_IPSR_DATA(IP14_2_0, DVC_MUTE),
+        PINMUX_IPSR_MODSEL_DATA(IP14_2_0, CAN0_RX_C, SEL_CAN0_2),
+        PINMUX_IPSR_DATA(IP14_2_0, CAN_DEBUGOUT15),
+        PINMUX_IPSR_DATA(IP14_2_0, REMOCON),
+        PINMUX_IPSR_MODSEL_DATA(IP14_5_3, SCIFA0_SCK, SEL_SCFA_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_5_3, HSCK1, SEL_HSCIF1_0),
+        PINMUX_IPSR_DATA(IP14_5_3, SCK0),
+        PINMUX_IPSR_DATA(IP14_5_3, MSIOF3_SS2),
+        PINMUX_IPSR_DATA(IP14_5_3, DU2_DG2),
+        PINMUX_IPSR_DATA(IP14_5_3, LCDOUT10),
+        PINMUX_IPSR_MODSEL_DATA(IP14_5_3, SDA1_C, SEL_IIC1_2),
+        PINMUX_IPSR_MODSEL_DATA(IP14_5_3, SDA1_CIS_C, SEL_I2C1_2),
+        PINMUX_IPSR_MODSEL_DATA(IP14_8_6, SCIFA0_RXD, SEL_SCFA_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_8_6, HRX1, SEL_HSCIF1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_8_6, RX0, SEL_SCIF0_0),
+        PINMUX_IPSR_DATA(IP14_8_6, DU2_DR0),
+        PINMUX_IPSR_DATA(IP14_8_6, LCDOUT0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_11_9, SCIFA0_TXD, SEL_SCFA_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_11_9, HTX1, SEL_HSCIF1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_11_9, TX0, SEL_SCIF0_0),
+        PINMUX_IPSR_DATA(IP14_11_9, DU2_DR1),
+        PINMUX_IPSR_DATA(IP14_11_9, LCDOUT1),
+        PINMUX_IPSR_MODSEL_DATA(IP14_15_12, SCIFA0_CTS_N, SEL_SCFA_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_15_12, HCTS1_N, SEL_HSCIF1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_15_12, CTS0_N, SEL_SCIF0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_15_12, MSIOF3_SYNC, SEL_SOF3_0),
+        PINMUX_IPSR_DATA(IP14_15_12, DU2_DG3),
+        PINMUX_IPSR_MODSEL_DATA(IP14_15_12, LCDOUT11, SEL_HSCIF1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_15_12, PWM0_B, SEL_SCIF0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_15_12, SCL1_C, SEL_IIC1_2),
+        PINMUX_IPSR_MODSEL_DATA(IP14_15_12, SCL1_CIS_C, SEL_I2C1_2),
+        PINMUX_IPSR_MODSEL_DATA(IP14_18_16, SCIFA0_RTS_N, SEL_SCFA_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_18_16, HRTS1_N, SEL_HSCIF1_0),
+        PINMUX_IPSR_DATA(IP14_18_16, RTS0_N_TANS),
+        PINMUX_IPSR_DATA(IP14_18_16, MSIOF3_SS1),
+        PINMUX_IPSR_DATA(IP14_18_16, DU2_DG0),
+        PINMUX_IPSR_DATA(IP14_18_16, LCDOUT8),
+        PINMUX_IPSR_DATA(IP14_18_16, PWM1_B),
+        PINMUX_IPSR_MODSEL_DATA(IP14_21_19, SCIFA1_RXD, SEL_SCIFA1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_21_19, AD_DI, SEL_ADI_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_21_19, RX1, SEL_SCIF1_0),
+        PINMUX_IPSR_DATA(IP14_21_19, DU2_EXODDF_DU2_ODDF_DISP_CDE),
+        PINMUX_IPSR_DATA(IP14_21_19, QCPV_QDE),
+        PINMUX_IPSR_MODSEL_DATA(IP14_24_22, SCIFA1_TXD, SEL_SCIFA1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_24_22, AD_DO, SEL_ADI_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_24_22, TX1, SEL_SCIF1_0),
+        PINMUX_IPSR_DATA(IP14_24_22, DU2_DG1),
+        PINMUX_IPSR_DATA(IP14_24_22, LCDOUT9),
+        PINMUX_IPSR_MODSEL_DATA(IP14_27_25, SCIFA1_CTS_N, SEL_SCIFA1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_27_25, AD_CLK, SEL_ADI_0),
+        PINMUX_IPSR_DATA(IP14_27_25, CTS1_N),
+        PINMUX_IPSR_MODSEL_DATA(IP14_27_25, MSIOF3_RXD, SEL_SOF3_0),
+        PINMUX_IPSR_DATA(IP14_27_25, DU0_DOTCLKOUT),
+        PINMUX_IPSR_DATA(IP14_27_25, QCLK),
+        PINMUX_IPSR_MODSEL_DATA(IP14_30_28, SCIFA1_RTS_N, SEL_SCIFA1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_30_28, AD_NCS_N, SEL_ADI_0),
+        PINMUX_IPSR_DATA(IP14_30_28, RTS1_N_TANS),
+        PINMUX_IPSR_MODSEL_DATA(IP14_30_28, MSIOF3_TXD, SEL_SOF3_0),
+        PINMUX_IPSR_DATA(IP14_30_28, DU1_DOTCLKOUT),
+        PINMUX_IPSR_DATA(IP14_30_28, QSTVB_QVE),
+        PINMUX_IPSR_MODSEL_DATA(IP14_30_28, HRTS0_N_C, SEL_HSCIF0_2),
+
+        PINMUX_IPSR_MODSEL_DATA(IP15_2_0, SCIFA2_SCK, SEL_SCIFA2_0),
+        PINMUX_IPSR_MODSEL_DATA(IP15_2_0, FMCLK, SEL_FM_0),
+        PINMUX_IPSR_MODSEL_DATA(IP15_2_0, MSIOF3_SCK, SEL_SOF3_0),
+        PINMUX_IPSR_DATA(IP15_2_0, DU2_DG7),
+        PINMUX_IPSR_DATA(IP15_2_0, LCDOUT15),
+        PINMUX_IPSR_MODSEL_DATA(IP15_2_0, SCIF_CLK_B, SEL_SCIFCLK_0),
+        PINMUX_IPSR_MODSEL_DATA(IP15_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
+        PINMUX_IPSR_MODSEL_DATA(IP15_5_3, FMIN, SEL_FM_0),
+        PINMUX_IPSR_DATA(IP15_5_3, DU2_DB0),
+        PINMUX_IPSR_DATA(IP15_5_3, LCDOUT16),
+        PINMUX_IPSR_MODSEL_DATA(IP15_5_3, SCL2, SEL_IIC2_0),
+        PINMUX_IPSR_MODSEL_DATA(IP15_5_3, SCL2_CIS, SEL_I2C2_0),
+        PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SCIFA2_TXD, SEL_SCIFA2_0),
+        PINMUX_IPSR_MODSEL_DATA(IP15_8_6, BPFCLK, SEL_FM_0),
+        PINMUX_IPSR_DATA(IP15_8_6, DU2_DB1),
+        PINMUX_IPSR_DATA(IP15_8_6, LCDOUT17),
+        PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SDA2, SEL_IIC2_0),
+        PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SDA2_CIS, SEL_I2C2_0),
+        PINMUX_IPSR_DATA(IP15_11_9, HSCK0),
+        PINMUX_IPSR_MODSEL_DATA(IP15_11_9, TS_SDEN0, SEL_TSIF0_0),
+        PINMUX_IPSR_DATA(IP15_11_9, DU2_DG4),
+        PINMUX_IPSR_DATA(IP15_11_9, LCDOUT12),
+        PINMUX_IPSR_MODSEL_DATA(IP15_11_9, HCTS0_N_C, SEL_IIC2_0),
+        PINMUX_IPSR_MODSEL_DATA(IP15_11_9, SDA2_CIS, SEL_I2C2_0),
+        PINMUX_IPSR_MODSEL_DATA(IP15_13_12, HRX0, SEL_HSCIF0_0),
+        PINMUX_IPSR_DATA(IP15_13_12, DU2_DB2),
+        PINMUX_IPSR_DATA(IP15_13_12, LCDOUT18),
+        PINMUX_IPSR_MODSEL_DATA(IP15_15_14, HTX0, SEL_HSCIF0_0),
+        PINMUX_IPSR_DATA(IP15_15_14, DU2_DB3),
+        PINMUX_IPSR_DATA(IP15_15_14, LCDOUT19),
+        PINMUX_IPSR_MODSEL_DATA(IP15_17_16, HCTS0_N, SEL_HSCIF0_0),
+        PINMUX_IPSR_DATA(IP15_17_16, SSI_SCK9),
+        PINMUX_IPSR_DATA(IP15_17_16, DU2_DB4),
+        PINMUX_IPSR_DATA(IP15_17_16, LCDOUT20),
+        PINMUX_IPSR_MODSEL_DATA(IP15_19_18, HRTS0_N, SEL_HSCIF0_0),
+        PINMUX_IPSR_DATA(IP15_19_18, SSI_WS9),
+        PINMUX_IPSR_DATA(IP15_19_18, DU2_DB5),
+        PINMUX_IPSR_DATA(IP15_19_18, LCDOUT21),
+        PINMUX_IPSR_MODSEL_DATA(IP15_22_20, MSIOF0_SCK, SEL_SOF0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP15_22_20, TS_SDAT0, SEL_TSIF0_0),
+        PINMUX_IPSR_DATA(IP15_22_20, ADICLK),
+        PINMUX_IPSR_DATA(IP15_22_20, DU2_DB6),
+        PINMUX_IPSR_DATA(IP15_22_20, LCDOUT22),
+        PINMUX_IPSR_DATA(IP15_25_23, MSIOF0_SYNC),
+        PINMUX_IPSR_MODSEL_DATA(IP15_25_23, TS_SCK0, SEL_TSIF0_0),
+        PINMUX_IPSR_DATA(IP15_25_23, SSI_SCK2),
+        PINMUX_IPSR_DATA(IP15_25_23, ADIDATA),
+        PINMUX_IPSR_DATA(IP15_25_23, DU2_DB7),
+        PINMUX_IPSR_DATA(IP15_25_23, LCDOUT23),
+        PINMUX_IPSR_MODSEL_DATA(IP15_25_23, SCIFA2_RXD_B, SEL_SCIFA2_1),
+        PINMUX_IPSR_MODSEL_DATA(IP15_27_26, MSIOF0_SS1, SEL_SOF0_0),
+        PINMUX_IPSR_DATA(IP15_27_26, ADICHS0),
+        PINMUX_IPSR_DATA(IP15_27_26, DU2_DG5),
+        PINMUX_IPSR_DATA(IP15_27_26, LCDOUT13),
+        PINMUX_IPSR_MODSEL_DATA(IP15_29_28, MSIOF0_TXD, SEL_SOF0_0),
+        PINMUX_IPSR_DATA(IP15_29_28, ADICHS1),
+        PINMUX_IPSR_DATA(IP15_29_28, DU2_DG6),
+        PINMUX_IPSR_DATA(IP15_29_28, LCDOUT14),
+
+        PINMUX_IPSR_MODSEL_DATA(IP16_2_0, MSIOF0_SS2, SEL_SOF0_0),
+        PINMUX_IPSR_DATA(IP16_2_0, AUDIO_CLKOUT),
+        PINMUX_IPSR_DATA(IP16_2_0, ADICHS2),
+        PINMUX_IPSR_DATA(IP16_2_0, DU2_DISP),
+        PINMUX_IPSR_DATA(IP16_2_0, QPOLA),
+        PINMUX_IPSR_MODSEL_DATA(IP16_2_0, HTX0_C, SEL_HSCIF0_2),
+        PINMUX_IPSR_MODSEL_DATA(IP16_2_0, SCIFA2_TXD_B, SEL_SCIFA2_1),
+        PINMUX_IPSR_MODSEL_DATA(IP16_5_3, MSIOF0_RXD, SEL_SOF0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP16_5_3, TS_SPSYNC0, SEL_TSIF0_0),
+        PINMUX_IPSR_DATA(IP16_5_3, SSI_WS2),
+        PINMUX_IPSR_DATA(IP16_5_3, ADICS_SAMP),
+        PINMUX_IPSR_DATA(IP16_5_3, DU2_CDE),
+        PINMUX_IPSR_DATA(IP16_5_3, QPOLB),
+        PINMUX_IPSR_MODSEL_DATA(IP16_5_3, HRX0_C, SEL_HSCIF0_2),
+        PINMUX_IPSR_DATA(IP16_6, USB1_PWEN),
+        PINMUX_IPSR_DATA(IP16_6, AUDIO_CLKOUT_D),
+        PINMUX_IPSR_DATA(IP16_7, USB1_OVC),
+        PINMUX_IPSR_MODSEL_DATA(IP16_7, TCLK1_B, SEL_TMU1_1),
+};
+
+static struct sh_pfc_pin pinmux_pins[] = {
+        PINMUX_GPIO_GP_ALL(),
+};
+
+/* - ETH -------------------------------------------------------------------- */
+static const unsigned int eth_link_pins[] = {
+        /* LINK */
+        RCAR_GP_PIN(2, 22),
+};
+static const unsigned int eth_link_mux[] = {
+        ETH_LINK_MARK,
+};
+static const unsigned int eth_magic_pins[] = {
+        /* MAGIC */
+        RCAR_GP_PIN(2, 27),
+};
+static const unsigned int eth_magic_mux[] = {
+        ETH_MAGIC_MARK,
+};
+static const unsigned int eth_mdio_pins[] = {
+        /* MDC, MDIO */
+        RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 24),
+};
+static const unsigned int eth_mdio_mux[] = {
+        ETH_MDC_MARK, ETH_MDIO_MARK,
+};
+static const unsigned int eth_rmii_pins[] = {
+        /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
+        RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 19),
+        RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 25),
+        RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 23),
+};
+static const unsigned int eth_rmii_mux[] = {
+        ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
+        ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REF_CLK_MARK,
+};
+/* - INTC ------------------------------------------------------------------- */
+static const unsigned int intc_irq0_pins[] = {
+        /* IRQ */
+        RCAR_GP_PIN(1, 25),
+};
+static const unsigned int intc_irq0_mux[] = {
+        IRQ0_MARK,
+};
+static const unsigned int intc_irq1_pins[] = {
+        /* IRQ */
+        RCAR_GP_PIN(1, 27),
+};
+static const unsigned int intc_irq1_mux[] = {
+        IRQ1_MARK,
+};
+static const unsigned int intc_irq2_pins[] = {
+        /* IRQ */
+        RCAR_GP_PIN(1, 29),
+};
+static const unsigned int intc_irq2_mux[] = {
+        IRQ2_MARK,
+};
+static const unsigned int intc_irq3_pins[] = {
+        /* IRQ */
+        RCAR_GP_PIN(1, 23),
+};
+static const unsigned int intc_irq3_mux[] = {
+        IRQ3_MARK,
+};
+/* - SCIF0 ----------------------------------------------------------------- */
+static const unsigned int scif0_data_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
+};
+static const unsigned int scif0_data_mux[] = {
+        RX0_MARK, TX0_MARK,
+};
+static const unsigned int scif0_clk_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(4, 27),
+};
+static const unsigned int scif0_clk_mux[] = {
+        SCK0_MARK,
+};
+static const unsigned int scif0_ctrl_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
+};
+static const unsigned int scif0_ctrl_mux[] = {
+        RTS0_N_TANS_MARK, CTS0_N_MARK,
+};
+static const unsigned int scif0_data_b_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+};
+static const unsigned int scif0_data_b_mux[] = {
+        RX0_B_MARK, TX0_B_MARK,
+};
+/* - SCIF1 ----------------------------------------------------------------- */
+static const unsigned int scif1_data_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
+};
+static const unsigned int scif1_data_mux[] = {
+        RX1_MARK, TX1_MARK,
+};
+static const unsigned int scif1_clk_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(4, 20),
+};
+static const unsigned int scif1_clk_mux[] = {
+        SCK1_MARK,
+};
+static const unsigned int scif1_ctrl_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
+};
+static const unsigned int scif1_ctrl_mux[] = {
+        RTS1_N_TANS_MARK, CTS1_N_MARK,
+};
+static const unsigned int scif1_data_b_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
+};
+static const unsigned int scif1_data_b_mux[] = {
+        RX1_B_MARK, TX1_B_MARK,
+};
+static const unsigned int scif1_data_c_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
+};
+static const unsigned int scif1_data_c_mux[] = {
+        RX1_C_MARK, TX1_C_MARK,
+};
+static const unsigned int scif1_data_d_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
+};
+static const unsigned int scif1_data_d_mux[] = {
+        RX1_D_MARK, TX1_D_MARK,
+};
+static const unsigned int scif1_clk_d_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(3, 17),
+};
+static const unsigned int scif1_clk_d_mux[] = {
+        SCK1_D_MARK,
+};
+static const unsigned int scif1_data_e_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
+};
+static const unsigned int scif1_data_e_mux[] = {
+        RX1_E_MARK, TX1_E_MARK,
+};
+static const unsigned int scif1_clk_e_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(2, 20),
+};
+static const unsigned int scif1_clk_e_mux[] = {
+        SCK1_E_MARK,
+};
+/* - SCIFA0 ----------------------------------------------------------------- */
+static const unsigned int scifa0_data_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
+};
+static const unsigned int scifa0_data_mux[] = {
+        SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
+};
+static const unsigned int scifa0_clk_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(4, 27),
+};
+static const unsigned int scifa0_clk_mux[] = {
+        SCIFA0_SCK_MARK,
+};
+static const unsigned int scifa0_ctrl_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
+};
+static const unsigned int scifa0_ctrl_mux[] = {
+        SCIFA0_RTS_N_MARK, SCIFA0_CTS_N_MARK,
+};
+static const unsigned int scifa0_data_b_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21),
+};
+static const unsigned int scifa0_data_b_mux[] = {
+        SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
+};
+static const unsigned int scifa0_clk_b_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(1, 19),
+};
+static const unsigned int scifa0_clk_b_mux[] = {
+        SCIFA0_SCK_B_MARK,
+};
+static const unsigned int scifa0_ctrl_b_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22),
+};
+static const unsigned int scifa0_ctrl_b_mux[] = {
+        SCIFA0_RTS_N_B_MARK, SCIFA0_CTS_N_B_MARK,
+};
+/* - SCIFA1 ----------------------------------------------------------------- */
+static const unsigned int scifa1_data_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
+};
+static const unsigned int scifa1_data_mux[] = {
+        SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
+};
+static const unsigned int scifa1_clk_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(4, 20),
+};
+static const unsigned int scifa1_clk_mux[] = {
+        SCIFA1_SCK_MARK,
+};
+static const unsigned int scifa1_ctrl_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
+};
+static const unsigned int scifa1_ctrl_mux[] = {
+        SCIFA1_RTS_N_MARK, SCIFA1_CTS_N_MARK,
+};
+static const unsigned int scifa1_data_b_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 21),
+};
+static const unsigned int scifa1_data_b_mux[] = {
+        SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
+};
+static const unsigned int scifa1_clk_b_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(0, 23),
+};
+static const unsigned int scifa1_clk_b_mux[] = {
+        SCIFA1_SCK_B_MARK,
+};
+static const unsigned int scifa1_ctrl_b_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 25),
+};
+static const unsigned int scifa1_ctrl_b_mux[] = {
+        SCIFA1_RTS_N_B_MARK, SCIFA1_CTS_N_B_MARK,
+};
+static const unsigned int scifa1_data_c_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
+};
+static const unsigned int scifa1_data_c_mux[] = {
+        SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
+};
+static const unsigned int scifa1_clk_c_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(0, 8),
+};
+static const unsigned int scifa1_clk_c_mux[] = {
+        SCIFA1_SCK_C_MARK,
+};
+static const unsigned int scifa1_ctrl_c_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11),
+};
+static const unsigned int scifa1_ctrl_c_mux[] = {
+        SCIFA1_RTS_N_C_MARK, SCIFA1_CTS_N_C_MARK,
+};
+static const unsigned int scifa1_data_d_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
+};
+static const unsigned int scifa1_data_d_mux[] = {
+        SCIFA1_RXD_D_MARK, SCIFA1_TXD_D_MARK,
+};
+static const unsigned int scifa1_clk_d_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(2, 10),
+};
+static const unsigned int scifa1_clk_d_mux[] = {
+        SCIFA1_SCK_D_MARK,
+};
+static const unsigned int scifa1_ctrl_d_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
+};
+static const unsigned int scifa1_ctrl_d_mux[] = {
+        SCIFA1_RTS_N_D_MARK, SCIFA1_CTS_N_D_MARK,
+};
+/* - SCIFA2 ----------------------------------------------------------------- */
+static const unsigned int scifa2_data_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
+};
+static const unsigned int scifa2_data_mux[] = {
+        SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
+};
+static const unsigned int scifa2_clk_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(5, 4),
+};
+static const unsigned int scifa2_clk_mux[] = {
+        SCIFA2_SCK_MARK,
+};
+static const unsigned int scifa2_ctrl_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21),
+};
+static const unsigned int scifa2_ctrl_mux[] = {
+        SCIFA2_RTS_N_MARK, SCIFA2_CTS_N_MARK,
+};
+static const unsigned int scifa2_data_b_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16),
+};
+static const unsigned int scifa2_data_b_mux[] = {
+        SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
+};
+static const unsigned int scifa2_data_c_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(5, 31), RCAR_GP_PIN(5, 30),
+};
+static const unsigned int scifa2_data_c_mux[] = {
+        SCIFA2_RXD_C_MARK, SCIFA2_TXD_C_MARK,
+};
+static const unsigned int scifa2_clk_c_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(5, 29),
+};
+static const unsigned int scifa2_clk_c_mux[] = {
+        SCIFA2_SCK_C_MARK,
+};
+/* - SCIFB0 ----------------------------------------------------------------- */
+static const unsigned int scifb0_data_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
+};
+static const unsigned int scifb0_data_mux[] = {
+        SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
+};
+static const unsigned int scifb0_clk_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(4, 8),
+};
+static const unsigned int scifb0_clk_mux[] = {
+        SCIFB0_SCK_MARK,
+};
+static const unsigned int scifb0_ctrl_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11),
+};
+static const unsigned int scifb0_ctrl_mux[] = {
+        SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
+};
+static const unsigned int scifb0_data_b_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
+};
+static const unsigned int scifb0_data_b_mux[] = {
+        SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK,
+};
+static const unsigned int scifb0_clk_b_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(3, 9),
+};
+static const unsigned int scifb0_clk_b_mux[] = {
+        SCIFB0_SCK_B_MARK,
+};
+static const unsigned int scifb0_ctrl_b_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
+};
+static const unsigned int scifb0_ctrl_b_mux[] = {
+        SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK,
+};
+static const unsigned int scifb0_data_c_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+};
+static const unsigned int scifb0_data_c_mux[] = {
+        SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK,
+};
+/* - SCIFB1 ----------------------------------------------------------------- */
+static const unsigned int scifb1_data_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
+};
+static const unsigned int scifb1_data_mux[] = {
+        SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
+};
+static const unsigned int scifb1_clk_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(4, 14),
+};
+static const unsigned int scifb1_clk_mux[] = {
+        SCIFB1_SCK_MARK,
+};
+static const unsigned int scifb1_ctrl_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17),
+};
+static const unsigned int scifb1_ctrl_mux[] = {
+        SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK,
+};
+static const unsigned int scifb1_data_b_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
+};
+static const unsigned int scifb1_data_b_mux[] = {
+        SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK,
+};
+static const unsigned int scifb1_clk_b_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(3, 1),
+};
+static const unsigned int scifb1_clk_b_mux[] = {
+        SCIFB1_SCK_B_MARK,
+};
+static const unsigned int scifb1_ctrl_b_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 4),
+};
+static const unsigned int scifb1_ctrl_b_mux[] = {
+        SCIFB1_RTS_N_B_MARK, SCIFB1_CTS_N_B_MARK,
+};
+static const unsigned int scifb1_data_c_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
+};
+static const unsigned int scifb1_data_c_mux[] = {
+        SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK,
+};
+static const unsigned int scifb1_data_d_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
+};
+static const unsigned int scifb1_data_d_mux[] = {
+        SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK,
+};
+static const unsigned int scifb1_data_e_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
+};
+static const unsigned int scifb1_data_e_mux[] = {
+        SCIFB1_RXD_E_MARK, SCIFB1_TXD_E_MARK,
+};
+static const unsigned int scifb1_clk_e_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(3, 17),
+};
+static const unsigned int scifb1_clk_e_mux[] = {
+        SCIFB1_SCK_E_MARK,
+};
+static const unsigned int scifb1_data_f_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+};
+static const unsigned int scifb1_data_f_mux[] = {
+        SCIFB1_RXD_F_MARK, SCIFB1_TXD_F_MARK,
+};
+static const unsigned int scifb1_data_g_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
+};
+static const unsigned int scifb1_data_g_mux[] = {
+        SCIFB1_RXD_G_MARK, SCIFB1_TXD_G_MARK,
+};
+static const unsigned int scifb1_clk_g_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(2, 20),
+};
+static const unsigned int scifb1_clk_g_mux[] = {
+        SCIFB1_SCK_G_MARK,
+};
+/* - SCIFB2 ----------------------------------------------------------------- */
+static const unsigned int scifb2_data_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
+};
+static const unsigned int scifb2_data_mux[] = {
+        SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
+};
+static const unsigned int scifb2_clk_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(4, 21),
+};
+static const unsigned int scifb2_clk_mux[] = {
+        SCIFB2_SCK_MARK,
+};
+static const unsigned int scifb2_ctrl_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24),
+};
+static const unsigned int scifb2_ctrl_mux[] = {
+        SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
+};
+static const unsigned int scifb2_data_b_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 30),
+};
+static const unsigned int scifb2_data_b_mux[] = {
+        SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK,
+};
+static const unsigned int scifb2_clk_b_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(0, 31),
+};
+static const unsigned int scifb2_clk_b_mux[] = {
+        SCIFB2_SCK_B_MARK,
+};
+static const unsigned int scifb2_ctrl_b_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 27),
+};
+static const unsigned int scifb2_ctrl_b_mux[] = {
+        SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK,
+};
+static const unsigned int scifb2_data_c_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
+};
+static const unsigned int scifb2_data_c_mux[] = {
+        SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK,
+};
+/* - TPU0 ------------------------------------------------------------------- */
+static const unsigned int tpu0_to0_pins[] = {
+        /* TO */
+        RCAR_GP_PIN(0, 20),
+};
+static const unsigned int tpu0_to0_mux[] = {
+        TPU0TO0_MARK,
+};
+static const unsigned int tpu0_to1_pins[] = {
+        /* TO */
+        RCAR_GP_PIN(0, 21),
+};
+static const unsigned int tpu0_to1_mux[] = {
+        TPU0TO1_MARK,
+};
+static const unsigned int tpu0_to2_pins[] = {
+        /* TO */
+        RCAR_GP_PIN(0, 22),
+};
+static const unsigned int tpu0_to2_mux[] = {
+        TPU0TO2_MARK,
+};
+static const unsigned int tpu0_to3_pins[] = {
+        /* TO */
+        RCAR_GP_PIN(0, 23),
+};
+static const unsigned int tpu0_to3_mux[] = {
+        TPU0TO3_MARK,
+};
+
+/* - MMCIF ------------------------------------------------------------------ */
+static const unsigned int mmc0_data1_pins[] = {
+        /* D[0] */
+        RCAR_GP_PIN(3, 18),
+};
+static const unsigned int mmc0_data1_mux[] = {
+        MMC0_D0_MARK,
+};
+static const unsigned int mmc0_data4_pins[] = {
+        /* D[0:3] */
+        RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
+        RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
+};
+static const unsigned int mmc0_data4_mux[] = {
+        MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
+};
+static const unsigned int mmc0_data8_pins[] = {
+        /* D[0:7] */
+        RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
+        RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
+        RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
+        RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
+};
+static const unsigned int mmc0_data8_mux[] = {
+        MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
+        MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK,
+};
+static const unsigned int mmc0_ctrl_pins[] = {
+        /* CLK, CMD */
+        RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
+};
+static const unsigned int mmc0_ctrl_mux[] = {
+        MMC0_CLK_MARK, MMC0_CMD_MARK,
+};
+
+static const unsigned int mmc1_data1_pins[] = {
+        /* D[0] */
+        RCAR_GP_PIN(3, 26),
+};
+static const unsigned int mmc1_data1_mux[] = {
+        MMC1_D0_MARK,
+};
+static const unsigned int mmc1_data4_pins[] = {
+        /* D[0:3] */
+        RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
+        RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
+};
+static const unsigned int mmc1_data4_mux[] = {
+        MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
+};
+static const unsigned int mmc1_data8_pins[] = {
+        /* D[0:7] */
+        RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
+        RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
+        RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
+        RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
+};
+static const unsigned int mmc1_data8_mux[] = {
+        MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
+        MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK,
+};
+static const unsigned int mmc1_ctrl_pins[] = {
+        /* CLK, CMD */
+        RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
+};
+static const unsigned int mmc1_ctrl_mux[] = {
+        MMC1_CLK_MARK, MMC1_CMD_MARK,
+};
+
+/* - SDHI ------------------------------------------------------------------- */
+static const unsigned int sdhi0_data1_pins[] = {
+        /* D0 */
+        RCAR_GP_PIN(3, 2),
+};
+static const unsigned int sdhi0_data1_mux[] = {
+        SD0_DAT0_MARK,
+};
+static const unsigned int sdhi0_data4_pins[] = {
+        /* D[0:3] */
+        RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
+};
+static const unsigned int sdhi0_data4_mux[] = {
+        SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
+};
+static const unsigned int sdhi0_ctrl_pins[] = {
+        /* CLK, CMD */
+        RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
+};
+static const unsigned int sdhi0_ctrl_mux[] = {
+        SD0_CLK_MARK, SD0_CMD_MARK,
+};
+static const unsigned int sdhi0_cd_pins[] = {
+        /* CD */
+        RCAR_GP_PIN(3, 6),
+};
+static const unsigned int sdhi0_cd_mux[] = {
+        SD0_CD_MARK,
+};
+static const unsigned int sdhi0_wp_pins[] = {
+        /* WP */
+        RCAR_GP_PIN(3, 7),
+};
+static const unsigned int sdhi0_wp_mux[] = {
+        SD0_WP_MARK,
+};
+
+static const unsigned int sdhi1_data1_pins[] = {
+        /* D0 */
+        RCAR_GP_PIN(3, 10),
+};
+static const unsigned int sdhi1_data1_mux[] = {
+        SD1_DAT0_MARK,
+};
+static const unsigned int sdhi1_data4_pins[] = {
+        /* D[0:3] */
+        RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
+};
+static const unsigned int sdhi1_data4_mux[] = {
+        SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK,
+};
+static const unsigned int sdhi1_ctrl_pins[] = {
+        /* CLK, CMD */
+        RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
+};
+static const unsigned int sdhi1_ctrl_mux[] = {
+        SD1_CLK_MARK, SD1_CMD_MARK,
+};
+static const unsigned int sdhi1_cd_pins[] = {
+        /* CD */
+        RCAR_GP_PIN(3, 14),
+};
+static const unsigned int sdhi1_cd_mux[] = {
+        SD1_CD_MARK,
+};
+static const unsigned int sdhi1_wp_pins[] = {
+        /* WP */
+        RCAR_GP_PIN(3, 15),
+};
+static const unsigned int sdhi1_wp_mux[] = {
+        SD1_WP_MARK,
+};
+
+static const unsigned int sdhi2_data1_pins[] = {
+        /* D0 */
+        RCAR_GP_PIN(3, 18),
+};
+static const unsigned int sdhi2_data1_mux[] = {
+        SD2_DAT0_MARK,
+};
+static const unsigned int sdhi2_data4_pins[] = {
+        /* D[0:3] */
+        RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
+};
+static const unsigned int sdhi2_data4_mux[] = {
+        SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
+};
+static const unsigned int sdhi2_ctrl_pins[] = {
+        /* CLK, CMD */
+        RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
+};
+static const unsigned int sdhi2_ctrl_mux[] = {
+        SD2_CLK_MARK, SD2_CMD_MARK,
+};
+static const unsigned int sdhi2_cd_pins[] = {
+        /* CD */
+        RCAR_GP_PIN(3, 22),
+};
+static const unsigned int sdhi2_cd_mux[] = {
+        SD2_CD_MARK,
+};
+static const unsigned int sdhi2_wp_pins[] = {
+        /* WP */
+        RCAR_GP_PIN(3, 23),
+};
+static const unsigned int sdhi2_wp_mux[] = {
+        SD2_WP_MARK,
+};
+
+static const unsigned int sdhi3_data1_pins[] = {
+        /* D0 */
+        RCAR_GP_PIN(3, 26),
+};
+static const unsigned int sdhi3_data1_mux[] = {
+        SD3_DAT0_MARK,
+};
+static const unsigned int sdhi3_data4_pins[] = {
+        /* D[0:3] */
+        RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
+};
+static const unsigned int sdhi3_data4_mux[] = {
+        SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK,
+};
+static const unsigned int sdhi3_ctrl_pins[] = {
+        /* CLK, CMD */
+        RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
+};
+static const unsigned int sdhi3_ctrl_mux[] = {
+        SD3_CLK_MARK, SD3_CMD_MARK,
+};
+static const unsigned int sdhi3_cd_pins[] = {
+        /* CD */
+        RCAR_GP_PIN(3, 30),
+};
+static const unsigned int sdhi3_cd_mux[] = {
+        SD3_CD_MARK,
+};
+static const unsigned int sdhi3_wp_pins[] = {
+        /* WP */
+        RCAR_GP_PIN(3, 31),
+};
+static const unsigned int sdhi3_wp_mux[] = {
+        SD3_WP_MARK,
+};
+
+static const struct sh_pfc_pin_group pinmux_groups[] = {
+        SH_PFC_PIN_GROUP(eth_link),
+        SH_PFC_PIN_GROUP(eth_magic),
+        SH_PFC_PIN_GROUP(eth_mdio),
+        SH_PFC_PIN_GROUP(eth_rmii),
+        SH_PFC_PIN_GROUP(intc_irq0),
+        SH_PFC_PIN_GROUP(intc_irq1),
+        SH_PFC_PIN_GROUP(intc_irq2),
+        SH_PFC_PIN_GROUP(intc_irq3),
+        SH_PFC_PIN_GROUP(scif0_data),
+        SH_PFC_PIN_GROUP(scif0_clk),
+        SH_PFC_PIN_GROUP(scif0_ctrl),
+        SH_PFC_PIN_GROUP(scif0_data_b),
+        SH_PFC_PIN_GROUP(scif1_data),
+        SH_PFC_PIN_GROUP(scif1_clk),
+        SH_PFC_PIN_GROUP(scif1_ctrl),
+        SH_PFC_PIN_GROUP(scif1_data_b),
+        SH_PFC_PIN_GROUP(scif1_data_c),
+        SH_PFC_PIN_GROUP(scif1_data_d),
+        SH_PFC_PIN_GROUP(scif1_clk_d),
+        SH_PFC_PIN_GROUP(scif1_data_e),
+        SH_PFC_PIN_GROUP(scif1_clk_e),
+        SH_PFC_PIN_GROUP(scifa0_data),
+        SH_PFC_PIN_GROUP(scifa0_clk),
+        SH_PFC_PIN_GROUP(scifa0_ctrl),
+        SH_PFC_PIN_GROUP(scifa0_data_b),
+        SH_PFC_PIN_GROUP(scifa0_clk_b),
+        SH_PFC_PIN_GROUP(scifa0_ctrl_b),
+        SH_PFC_PIN_GROUP(scifa1_data),
+        SH_PFC_PIN_GROUP(scifa1_clk),
+        SH_PFC_PIN_GROUP(scifa1_ctrl),
+        SH_PFC_PIN_GROUP(scifa1_data_b),
+        SH_PFC_PIN_GROUP(scifa1_clk_b),
+        SH_PFC_PIN_GROUP(scifa1_ctrl_b),
+        SH_PFC_PIN_GROUP(scifa1_data_c),
+        SH_PFC_PIN_GROUP(scifa1_clk_c),
+        SH_PFC_PIN_GROUP(scifa1_ctrl_c),
+        SH_PFC_PIN_GROUP(scifa1_data_d),
+        SH_PFC_PIN_GROUP(scifa1_clk_d),
+        SH_PFC_PIN_GROUP(scifa1_ctrl_d),
+        SH_PFC_PIN_GROUP(scifa2_data),
+        SH_PFC_PIN_GROUP(scifa2_clk),
+        SH_PFC_PIN_GROUP(scifa2_ctrl),
+        SH_PFC_PIN_GROUP(scifa2_data_b),
+        SH_PFC_PIN_GROUP(scifa2_data_c),
+        SH_PFC_PIN_GROUP(scifa2_clk_c),
+        SH_PFC_PIN_GROUP(scifb0_data),
+        SH_PFC_PIN_GROUP(scifb0_clk),
+        SH_PFC_PIN_GROUP(scifb0_ctrl),
+        SH_PFC_PIN_GROUP(scifb0_data_b),
+        SH_PFC_PIN_GROUP(scifb0_clk_b),
+        SH_PFC_PIN_GROUP(scifb0_ctrl_b),
+        SH_PFC_PIN_GROUP(scifb0_data_c),
+        SH_PFC_PIN_GROUP(scifb1_data),
+        SH_PFC_PIN_GROUP(scifb1_clk),
+        SH_PFC_PIN_GROUP(scifb1_ctrl),
+        SH_PFC_PIN_GROUP(scifb1_data_b),
+        SH_PFC_PIN_GROUP(scifb1_clk_b),
+        SH_PFC_PIN_GROUP(scifb1_ctrl_b),
+        SH_PFC_PIN_GROUP(scifb1_data_c),
+        SH_PFC_PIN_GROUP(scifb1_data_d),
+        SH_PFC_PIN_GROUP(scifb1_data_e),
+        SH_PFC_PIN_GROUP(scifb1_clk_e),
+        SH_PFC_PIN_GROUP(scifb1_data_f),
+        SH_PFC_PIN_GROUP(scifb1_data_g),
+        SH_PFC_PIN_GROUP(scifb1_clk_g),
+        SH_PFC_PIN_GROUP(scifb2_data),
+        SH_PFC_PIN_GROUP(scifb2_clk),
+        SH_PFC_PIN_GROUP(scifb2_ctrl),
+        SH_PFC_PIN_GROUP(scifb2_data_b),
+        SH_PFC_PIN_GROUP(scifb2_clk_b),
+        SH_PFC_PIN_GROUP(scifb2_ctrl_b),
+        SH_PFC_PIN_GROUP(scifb2_data_c),
+        SH_PFC_PIN_GROUP(tpu0_to0),
+        SH_PFC_PIN_GROUP(tpu0_to1),
+        SH_PFC_PIN_GROUP(tpu0_to2),
+        SH_PFC_PIN_GROUP(tpu0_to3),
+        SH_PFC_PIN_GROUP(mmc0_data1),
+        SH_PFC_PIN_GROUP(mmc0_data4),
+        SH_PFC_PIN_GROUP(mmc0_data8),
+        SH_PFC_PIN_GROUP(mmc0_ctrl),
+        SH_PFC_PIN_GROUP(mmc1_data1),
+        SH_PFC_PIN_GROUP(mmc1_data4),
+        SH_PFC_PIN_GROUP(mmc1_data8),
+        SH_PFC_PIN_GROUP(mmc1_ctrl),
+        SH_PFC_PIN_GROUP(sdhi0_data1),
+        SH_PFC_PIN_GROUP(sdhi0_data4),
+        SH_PFC_PIN_GROUP(sdhi0_ctrl),
+        SH_PFC_PIN_GROUP(sdhi0_cd),
+        SH_PFC_PIN_GROUP(sdhi0_wp),
+        SH_PFC_PIN_GROUP(sdhi1_data1),
+        SH_PFC_PIN_GROUP(sdhi1_data4),
+        SH_PFC_PIN_GROUP(sdhi1_ctrl),
+        SH_PFC_PIN_GROUP(sdhi1_cd),
+        SH_PFC_PIN_GROUP(sdhi1_wp),
+        SH_PFC_PIN_GROUP(sdhi2_data1),
+        SH_PFC_PIN_GROUP(sdhi2_data4),
+        SH_PFC_PIN_GROUP(sdhi2_ctrl),
+        SH_PFC_PIN_GROUP(sdhi2_cd),
+        SH_PFC_PIN_GROUP(sdhi2_wp),
+        SH_PFC_PIN_GROUP(sdhi3_data1),
+        SH_PFC_PIN_GROUP(sdhi3_data4),
+        SH_PFC_PIN_GROUP(sdhi3_ctrl),
+        SH_PFC_PIN_GROUP(sdhi3_cd),
+        SH_PFC_PIN_GROUP(sdhi3_wp),
+};
+
+static const char * const eth_groups[] = {
+        "eth_link",
+        "eth_magic",
+        "eth_mdio",
+        "eth_rmii",
+};
+
+static const char * const intc_groups[] = {
+        "intc_irq0",
+        "intc_irq1",
+        "intc_irq2",
+        "intc_irq3",
+};
+
+static const char * const scif0_groups[] = {
+        "scif0_data",
+        "scif0_clk",
+        "scif0_ctrl",
+        "scif0_data_b",
+};
+
+static const char * const scif1_groups[] = {
+        "scif1_data",
+        "scif1_clk",
+        "scif1_ctrl",
+        "scif1_data_b",
+        "scif1_data_c",
+        "scif1_data_d",
+        "scif1_clk_d",
+        "scif1_data_e",
+        "scif1_clk_e",
+};
+
+static const char * const scifa0_groups[] = {
+        "scifa0_data",
+        "scifa0_clk",
+        "scifa0_ctrl",
+        "scifa0_data_b",
+        "scifa0_clk_b",
+        "scifa0_ctrl_b",
+};
+
+static const char * const scifa1_groups[] = {
+        "scifa1_data",
+        "scifa1_clk",
+        "scifa1_ctrl",
+        "scifa1_data_b",
+        "scifa1_clk_b",
+        "scifa1_ctrl_b",
+        "scifa1_data_c",
+        "scifa1_clk_c",
+        "scifa1_ctrl_c",
+        "scifa1_data_d",
+        "scifa1_clk_d",
+        "scifa1_ctrl_d",
+};
+
+static const char * const scifa2_groups[] = {
+        "scifa2_data",
+        "scifa2_clk",
+        "scifa2_ctrl",
+        "scifa2_data_b",
+        "scifa2_data_c",
+        "scifa2_clk_c",
+};
+
+static const char * const scifb0_groups[] = {
+        "scifb0_data",
+        "scifb0_clk",
+        "scifb0_ctrl",
+        "scifb0_data_b",
+        "scifb0_clk_b",
+        "scifb0_ctrl_b",
+        "scifb0_data_c",
+};
+
+static const char * const scifb1_groups[] = {
+        "scifb1_data",
+        "scifb1_clk",
+        "scifb1_ctrl",
+        "scifb1_data_b",
+        "scifb1_clk_b",
+        "scifb1_ctrl_b",
+        "scifb1_data_c",
+        "scifb1_data_d",
+        "scifb1_data_e",
+        "scifb1_clk_e",
+        "scifb1_data_f",
+        "scifb1_data_g",
+        "scifb1_clk_g",
+};
+
+static const char * const scifb2_groups[] = {
+        "scifb2_data",
+        "scifb2_clk",
+        "scifb2_ctrl",
+        "scifb2_data_b",
+        "scifb2_clk_b",
+        "scifb2_ctrl_b",
+        "scifb2_data_c",
+};
+
+static const char * const tpu0_groups[] = {
+        "tpu0_to0",
+        "tpu0_to1",
+        "tpu0_to2",
+        "tpu0_to3",
+};
+
+static const char * const mmc0_groups[] = {
+        "mmc0_data1",
+        "mmc0_data4",
+        "mmc0_data8",
+        "mmc0_ctrl",
+};
+
+static const char * const mmc1_groups[] = {
+        "mmc1_data1",
+        "mmc1_data4",
+        "mmc1_data8",
+        "mmc1_ctrl",
+};
+
+static const char * const sdhi0_groups[] = {
+        "sdhi0_data1",
+        "sdhi0_data4",
+        "sdhi0_ctrl",
+        "sdhi0_cd",
+        "sdhi0_wp",
+};
+
+static const char * const sdhi1_groups[] = {
+        "sdhi1_data1",
+        "sdhi1_data4",
+        "sdhi1_ctrl",
+        "sdhi1_cd",
+        "sdhi1_wp",
+};
+
+static const char * const sdhi2_groups[] = {
+        "sdhi2_data1",
+        "sdhi2_data4",
+        "sdhi2_ctrl",
+        "sdhi2_cd",
+        "sdhi2_wp",
+};
+
+static const char * const sdhi3_groups[] = {
+        "sdhi3_data1",
+        "sdhi3_data4",
+        "sdhi3_ctrl",
+        "sdhi3_cd",
+        "sdhi3_wp",
+};
+
+static const struct sh_pfc_function pinmux_functions[] = {
+        SH_PFC_FUNCTION(eth),
+        SH_PFC_FUNCTION(intc),
+        SH_PFC_FUNCTION(scif0),
+        SH_PFC_FUNCTION(scif1),
+        SH_PFC_FUNCTION(scifa0),
+        SH_PFC_FUNCTION(scifa1),
+        SH_PFC_FUNCTION(scifa2),
+        SH_PFC_FUNCTION(scifb0),
+        SH_PFC_FUNCTION(scifb1),
+        SH_PFC_FUNCTION(scifb2),
+        SH_PFC_FUNCTION(tpu0),
+        SH_PFC_FUNCTION(mmc0),
+        SH_PFC_FUNCTION(mmc1),
+        SH_PFC_FUNCTION(sdhi0),
+        SH_PFC_FUNCTION(sdhi1),
+        SH_PFC_FUNCTION(sdhi2),
+        SH_PFC_FUNCTION(sdhi3),
+};
+
+static struct pinmux_cfg_reg pinmux_config_regs[] = {
+        { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
+                GP_0_31_FN, FN_IP3_17_15,
+                GP_0_30_FN, FN_IP3_14_12,
+                GP_0_29_FN, FN_IP3_11_8,
+                GP_0_28_FN, FN_IP3_7_4,
+                GP_0_27_FN, FN_IP3_3_0,
+                GP_0_26_FN, FN_IP2_28_26,
+                GP_0_25_FN, FN_IP2_25_22,
+                GP_0_24_FN, FN_IP2_21_18,
+                GP_0_23_FN, FN_IP2_17_15,
+                GP_0_22_FN, FN_IP2_14_12,
+                GP_0_21_FN, FN_IP2_11_9,
+                GP_0_20_FN, FN_IP2_8_6,
+                GP_0_19_FN, FN_IP2_5_3,
+                GP_0_18_FN, FN_IP2_2_0,
+                GP_0_17_FN, FN_IP1_29_28,
+                GP_0_16_FN, FN_IP1_27_26,
+                GP_0_15_FN, FN_IP1_25_22,
+                GP_0_14_FN, FN_IP1_21_18,
+                GP_0_13_FN, FN_IP1_17_15,
+                GP_0_12_FN, FN_IP1_14_12,
+                GP_0_11_FN, FN_IP1_11_8,
+                GP_0_10_FN, FN_IP1_7_4,
+                GP_0_9_FN, FN_IP1_3_0,
+                GP_0_8_FN, FN_IP0_30_27,
+                GP_0_7_FN, FN_IP0_26_23,
+                GP_0_6_FN, FN_IP0_22_20,
+                GP_0_5_FN, FN_IP0_19_16,
+                GP_0_4_FN, FN_IP0_15_12,
+                GP_0_3_FN, FN_IP0_11_9,
+                GP_0_2_FN, FN_IP0_8_6,
+                GP_0_1_FN, FN_IP0_5_3,
+                GP_0_0_FN, FN_IP0_2_0 }
+        },
+        { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
+                0, 0,
+                0, 0,
+                GP_1_29_FN, FN_IP6_13_11,
+                GP_1_28_FN, FN_IP6_10_9,
+                GP_1_27_FN, FN_IP6_8_6,
+                GP_1_26_FN, FN_IP6_5_3,
+                GP_1_25_FN, FN_IP6_2_0,
+                GP_1_24_FN, FN_IP5_29_27,
+                GP_1_23_FN, FN_IP5_26_24,
+                GP_1_22_FN, FN_IP5_23_21,
+                GP_1_21_FN, FN_IP5_20_18,
+                GP_1_20_FN, FN_IP5_17_15,
+                GP_1_19_FN, FN_IP5_14_13,
+                GP_1_18_FN, FN_IP5_12_10,
+                GP_1_17_FN, FN_IP5_9_6,
+                GP_1_16_FN, FN_IP5_5_3,
+                GP_1_15_FN, FN_IP5_2_0,
+                GP_1_14_FN, FN_IP4_29_27,
+                GP_1_13_FN, FN_IP4_26_24,
+                GP_1_12_FN, FN_IP4_23_21,
+                GP_1_11_FN, FN_IP4_20_18,
+                GP_1_10_FN, FN_IP4_17_15,
+                GP_1_9_FN, FN_IP4_14_12,
+                GP_1_8_FN, FN_IP4_11_9,
+                GP_1_7_FN, FN_IP4_8_6,
+                GP_1_6_FN, FN_IP4_5_3,
+                GP_1_5_FN, FN_IP4_2_0,
+                GP_1_4_FN, FN_IP3_31_29,
+                GP_1_3_FN, FN_IP3_28_26,
+                GP_1_2_FN, FN_IP3_25_23,
+                GP_1_1_FN, FN_IP3_22_20,
+                GP_1_0_FN, FN_IP3_19_18, }
+        },
+        { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
+                0, 0,
+                0, 0,
+                GP_2_29_FN, FN_IP7_15_13,
+                GP_2_28_FN, FN_IP7_12_10,
+                GP_2_27_FN, FN_IP7_9_8,
+                GP_2_26_FN, FN_IP7_7_6,
+                GP_2_25_FN, FN_IP7_5_3,
+                GP_2_24_FN, FN_IP7_2_0,
+                GP_2_23_FN, FN_IP6_31_29,
+                GP_2_22_FN, FN_IP6_28_26,
+                GP_2_21_FN, FN_IP6_25_23,
+                GP_2_20_FN, FN_IP6_22_20,
+                GP_2_19_FN, FN_IP6_19_17,
+                GP_2_18_FN, FN_IP6_16_14,
+                GP_2_17_FN, FN_VI1_DATA7_VI1_B7,
+                GP_2_16_FN, FN_IP8_27,
+                GP_2_15_FN, FN_IP8_26,
+                GP_2_14_FN, FN_IP8_25_24,
+                GP_2_13_FN, FN_IP8_23_22,
+                GP_2_12_FN, FN_IP8_21_20,
+                GP_2_11_FN, FN_IP8_19_18,
+                GP_2_10_FN, FN_IP8_17_16,
+                GP_2_9_FN, FN_IP8_15_14,
+                GP_2_8_FN, FN_IP8_13_12,
+                GP_2_7_FN, FN_IP8_11_10,
+                GP_2_6_FN, FN_IP8_9_8,
+                GP_2_5_FN, FN_IP8_7_6,
+                GP_2_4_FN, FN_IP8_5_4,
+                GP_2_3_FN, FN_IP8_3_2,
+                GP_2_2_FN, FN_IP8_1_0,
+                GP_2_1_FN, FN_IP7_30_29,
+                GP_2_0_FN, FN_IP7_28_27 }
+        },
+        { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
+                GP_3_31_FN, FN_IP11_21_18,
+                GP_3_30_FN, FN_IP11_17_15,
+                GP_3_29_FN, FN_IP11_14_13,
+                GP_3_28_FN, FN_IP11_12_11,
+                GP_3_27_FN, FN_IP11_10_9,
+                GP_3_26_FN, FN_IP11_8_7,
+                GP_3_25_FN, FN_IP11_6_5,
+                GP_3_24_FN, FN_IP11_4,
+                GP_3_23_FN, FN_IP11_3_0,
+                GP_3_22_FN, FN_IP10_29_26,
+                GP_3_21_FN, FN_IP10_25_23,
+                GP_3_20_FN, FN_IP10_22_19,
+                GP_3_19_FN, FN_IP10_18_15,
+                GP_3_18_FN, FN_IP10_14_11,
+                GP_3_17_FN, FN_IP10_10_7,
+                GP_3_16_FN, FN_IP10_6_4,
+                GP_3_15_FN, FN_IP10_3_0,
+                GP_3_14_FN, FN_IP9_31_28,
+                GP_3_13_FN, FN_IP9_27_26,
+                GP_3_12_FN, FN_IP9_25_24,
+                GP_3_11_FN, FN_IP9_23_22,
+                GP_3_10_FN, FN_IP9_21_20,
+                GP_3_9_FN, FN_IP9_19_18,
+                GP_3_8_FN, FN_IP9_17_16,
+                GP_3_7_FN, FN_IP9_15_12,
+                GP_3_6_FN, FN_IP9_11_8,
+                GP_3_5_FN, FN_IP9_7_6,
+                GP_3_4_FN, FN_IP9_5_4,
+                GP_3_3_FN, FN_IP9_3_2,
+                GP_3_2_FN, FN_IP9_1_0,
+                GP_3_1_FN, FN_IP8_30_29,
+                GP_3_0_FN, FN_IP8_28 }
+        },
+        { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
+                GP_4_31_FN, FN_IP14_18_16,
+                GP_4_30_FN, FN_IP14_15_12,
+                GP_4_29_FN, FN_IP14_11_9,
+                GP_4_28_FN, FN_IP14_8_6,
+                GP_4_27_FN, FN_IP14_5_3,
+                GP_4_26_FN, FN_IP14_2_0,
+                GP_4_25_FN, FN_IP13_30_29,
+                GP_4_24_FN, FN_IP13_28_26,
+                GP_4_23_FN, FN_IP13_25_23,
+                GP_4_22_FN, FN_IP13_22_19,
+                GP_4_21_FN, FN_IP13_18_16,
+                GP_4_20_FN, FN_IP13_15_13,
+                GP_4_19_FN, FN_IP13_12_10,
+                GP_4_18_FN, FN_IP13_9_7,
+                GP_4_17_FN, FN_IP13_6_3,
+                GP_4_16_FN, FN_IP13_2_0,
+                GP_4_15_FN, FN_IP12_30_28,
+                GP_4_14_FN, FN_IP12_27_25,
+                GP_4_13_FN, FN_IP12_24_23,
+                GP_4_12_FN, FN_IP12_22_20,
+                GP_4_11_FN, FN_IP12_19_17,
+                GP_4_10_FN, FN_IP12_16_14,
+                GP_4_9_FN, FN_IP12_13_11,
+                GP_4_8_FN, FN_IP12_10_8,
+                GP_4_7_FN, FN_IP12_7_6,
+                GP_4_6_FN, FN_IP12_5_4,
+                GP_4_5_FN, FN_IP12_3_2,
+                GP_4_4_FN, FN_IP12_1_0,
+                GP_4_3_FN, FN_IP11_31_30,
+                GP_4_2_FN, FN_IP11_29_27,
+                GP_4_1_FN, FN_IP11_26_24,
+                GP_4_0_FN, FN_IP11_23_22 }
+        },
+        { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
+                GP_5_31_FN, FN_IP7_24_22,
+                GP_5_30_FN, FN_IP7_21_19,
+                GP_5_29_FN, FN_IP7_18_16,
+                GP_5_28_FN, FN_DU_DOTCLKIN2,
+                GP_5_27_FN, FN_IP7_26_25,
+                GP_5_26_FN, FN_DU_DOTCLKIN0,
+                GP_5_25_FN, FN_AVS2,
+                GP_5_24_FN, FN_AVS1,
+                GP_5_23_FN, FN_USB2_OVC,
+                GP_5_22_FN, FN_USB2_PWEN,
+                GP_5_21_FN, FN_IP16_7,
+                GP_5_20_FN, FN_IP16_6,
+                GP_5_19_FN, FN_USB0_OVC_VBUS,
+                GP_5_18_FN, FN_USB0_PWEN,
+                GP_5_17_FN, FN_IP16_5_3,
+                GP_5_16_FN, FN_IP16_2_0,
+                GP_5_15_FN, FN_IP15_29_28,
+                GP_5_14_FN, FN_IP15_27_26,
+                GP_5_13_FN, FN_IP15_25_23,
+                GP_5_12_FN, FN_IP15_22_20,
+                GP_5_11_FN, FN_IP15_19_18,
+                GP_5_10_FN, FN_IP15_17_16,
+                GP_5_9_FN, FN_IP15_15_14,
+                GP_5_8_FN, FN_IP15_13_12,
+                GP_5_7_FN, FN_IP15_11_9,
+                GP_5_6_FN, FN_IP15_8_6,
+                GP_5_5_FN, FN_IP15_5_3,
+                GP_5_4_FN, FN_IP15_2_0,
+                GP_5_3_FN, FN_IP14_30_28,
+                GP_5_2_FN, FN_IP14_27_25,
+                GP_5_1_FN, FN_IP14_24_22,
+                GP_5_0_FN, FN_IP14_21_19 }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
+                             1, 4, 4, 3, 4, 4, 3, 3, 3, 3) {
+                /* IP0_31 [1] */
+                0, 0,
+                /* IP0_30_27 [4] */
+                FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, FN_MII_TXD0,
+                FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,
+                0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP0_26_23 [4] */
+                FN_D7, FN_AD_DI_B, FN_SDA2_C,
+                FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_SDA2_CIS_C,
+                0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP0_22_20 [3] */
+                FN_D6, FN_SCL2_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B,
+                FN_SCL2_CIS_C, 0, 0,
+                /* IP0_19_16 [4] */
+                FN_D5, FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5,
+                FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B,
+                0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP0_15_12 [4] */
+                FN_D4, FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4,
+                FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B,
+                0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP0_11_9 [3] */
+                FN_D3, FN_MSIOF3_TXD_B, FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B,
+                0, 0, 0,
+                /* IP0_8_6 [3] */
+                FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2, FN_VI0_G6, FN_VI0_G6_B,
+                0, 0, 0,
+                /* IP0_5_3 [3] */
+                FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5, FN_VI0_G5_B,
+                0, 0, 0,
+                /* IP0_2_0 [3] */
+                FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B,
+                0, 0, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
+                             2, 2, 2, 4, 4, 3, 3, 4, 4, 4) {
+                /* IP1_31_30 [2] */
+                0, 0, 0, 0,
+                /* IP1_29_28 [2] */
+                FN_A1, FN_PWM4, 0, 0,
+                /* IP1_27_26 [2] */
+                FN_A0, FN_PWM3, 0, 0,
+                /* IP1_25_22 [4] */
+                FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B,
+                FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7,
+                0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP1_21_18 [4] */
+                FN_D14, FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B,
+                FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6,
+                0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP1_17_15 [3] */
+                FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N,
+                FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5,
+                0, 0, 0,
+                /* IP1_14_12 [3] */
+                FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4,
+                FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4,
+                0, 0,
+                /* IP1_11_8 [4] */
+                FN_D11, FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, FN_MII_TXD3,
+                FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3,
+                0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP1_7_4 [4] */
+                FN_D10, FN_SCIFA1_TXD_C, FN_AVB_TXD2, FN_MII_TXD2,
+                FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2,
+                0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP1_3_0 [4] */
+                FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, FN_MII_TXD1,
+                FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
+                             3, 3, 4, 4, 3, 3, 3, 3, 3, 3) {
+                /* IP2_31_29 [3] */
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP2_28_26 [3] */
+                FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6,
+                FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, 0, 0,
+                /* IP2_25_22 [4] */
+                FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5,
+                FN_VI0_R5_B, FN_SCIFB2_TXD_C, 0, FN_VI2_DATA1_VI2_B1_B,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP2_21_18 [4] */
+                FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4,
+                FN_VI0_R4_B, FN_SCIFB2_RXD_C, 0, FN_VI2_DATA0_VI2_B0_B,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP2_17_15 [3] */
+                FN_A7, FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3,
+                0, 0, 0, 0,
+                /* IP2_14_12 [3] */
+                FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, 0, 0, 0, 0, 0,
+                /* IP2_11_9 [3] */
+                FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1, 0, 0, 0, 0, 0,
+                /* IP2_8_6 [3] */
+                FN_A4, FN_MSIOF1_TXD_B, FN_TPU0TO0, 0, 0, 0, 0, 0,
+                /* IP2_5_3 [3] */
+                FN_A3, FN_PWM6, FN_MSIOF1_SS2_B, 0, 0, 0, 0, 0,
+                /* IP2_2_0 [3] */
+                FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, 0, 0, 0, 0, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
+                             3, 3, 3, 3, 2, 3, 3, 4, 4, 4) {
+                /* IP3_31_29 [3] */
+                FN_A20, FN_SPCLK, FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4,
+                0, 0, 0,
+                /* IP3_28_26 [3] */
+                FN_A19, FN_AD_NCS_N_B, FN_ATACS01_N, FN_EX_WAIT0_B,
+                0, 0, 0, 0,
+                /* IP3_25_23 [3] */
+                FN_A18, FN_AD_CLK_B, FN_ATAG1_N, 0, 0, 0, 0, 0,
+                /* IP3_22_20 [3] */
+                FN_A17, FN_AD_DO_B, FN_ATADIR1_N, 0, 0, 0, 0, 0,
+                /* IP3_19_18 [2] */
+                FN_A16, FN_ATAWR1_N, 0, 0,
+                /* IP3_17_15 [3] */
+                FN_A15, FN_SCIFB2_SCK_B, FN_ATARD1_N, FN_MSIOF2_SS2,
+                0, 0, 0, 0,
+                /* IP3_14_12 [3] */
+                FN_A14, FN_SCIFB2_TXD_B, FN_ATACS11_N, FN_MSIOF2_SS1,
+                0, 0, 0, 0,
+                /* IP3_11_8 [4] */
+                FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2,
+                FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2,
+                FN_VI2_DATA5_VI2_B5_B, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP3_7_4 [4] */
+                FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1,
+                FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B,
+                0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP3_3_0 [4] */
+                FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0,
+                FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B, 0,
+                0, 0, 0, 0, 0, 0, 0, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
+                             2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
+                /* IP4_31_30 [2] */
+                0, 0, 0, 0,
+                /* IP4_29_27 [3] */
+                FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B,
+                FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2, 0,
+                /* IP4_26_24 [3] */
+                FN_EX_CS1_N, FN_GPS_CLK, FN_HCTS1_N_B, FN_VI1_FIELD,
+                FN_VI1_FIELD_B, FN_VI2_R1, 0, 0,
+                /* IP4_23_21 [3] */
+                FN_EX_CS0_N, FN_HRX1_B, FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0,
+                FN_HTX0_B, FN_MSIOF0_SS1_B, 0,
+                /* IP4_20_18 [3] */
+                FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B,
+                FN_VI2_CLK, FN_VI2_CLK_B, 0, 0,
+                /* IP4_17_15 [3] */
+                FN_CS0_N, FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B,
+                0, 0, 0,
+                /* IP4_14_12 [3] */
+                FN_A25, FN_SSL, FN_VI1_G6, FN_VI1_G6_B, FN_VI2_FIELD,
+                FN_VI2_FIELD_B, 0, 0,
+                /* IP4_11_9 [3] */
+                FN_A24, FN_IO3, FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB,
+                FN_VI2_CLKENB_B, 0, 0,
+                /* IP4_8_6 [3] */
+                FN_A23, FN_IO2, FN_VI1_G7, FN_VI1_G7_B, FN_VI2_G7, 0, 0, 0,
+                /* IP4_5_3 [3] */
+                FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B, FN_VI2_G6, 0, 0, 0,
+                /* IP4_2_0 [3] */
+                FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5, 0, 0, 0,
+                }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
+                             2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3) {
+                /* IP5_31_30 [2] */
+                0, 0, 0, 0,
+                /* IP5_29_27 [3] */
+                FN_DREQ0_N, FN_VI1_HSYNC_N, FN_VI1_HSYNC_N_B, FN_VI2_R7,
+                FN_SSI_SCK78_C, FN_SSI_WS78_B, 0, 0,
+                /* IP5_26_24 [3] */
+                FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N,
+                FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B,
+                FN_MSIOF0_SCK_B, 0,
+                /* IP5_23_21 [3] */
+                FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
+                FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B,
+                FN_IERX_C, 0,
+                /* IP5_20_18 [3] */
+                FN_WE0_N, FN_IECLK, FN_CAN_CLK,
+                FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, 0, 0,
+                /* IP5_17_15 [3] */
+                FN_RD_WR_N, FN_VI1_G3, FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
+                FN_INTC_IRQ4_N, 0, 0,
+                /* IP5_14_13 [2] */
+                FN_RD_N, FN_CAN0_TX, FN_SCIFA0_SCK_B, 0,
+                /* IP5_12_10 [3] */
+                FN_BS_N, FN_IETX, FN_HTX1_B, FN_CAN1_TX, FN_DRACK0, FN_IETX_C,
+                0, 0,
+                /* IP5_9_6 [4] */
+                FN_EX_CS5_N, FN_CAN0_RX, FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N,
+                FN_VI1_G2, FN_VI1_G2_B, FN_VI2_R4, FN_SDA1, FN_INTC_EN1_N,
+                FN_SDA1_CIS, 0, 0, 0, 0, 0, 0,
+                /* IP5_5_3 [3] */
+                FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N,
+                FN_VI2_HSYNC_N, FN_SCL1, FN_VI2_HSYNC_N_B,
+                FN_INTC_EN0_N, FN_SCL1_CIS,
+                /* IP5_2_0 [3] */
+                FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B,
+                FN_VI2_R3, 0, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
+                             3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3) {
+                /* IP6_31_29 [3] */
+                FN_ETH_REF_CLK, FN_RMII_REF_CLK, FN_HCTS0_N_E,
+                FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0,
+                /* IP6_28_26 [3] */
+                FN_ETH_LINK, FN_RMII_LINK, FN_HTX0_E,
+                FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 0, 0,
+                /* IP6_25_23 [3] */
+                FN_ETH_RXD1, FN_RMII_RXD1, FN_HRX0_E, FN_STP_ISSYNC_0_B,
+                FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, FN_RX1_E,
+                /* IP6_22_20 [3] */
+                FN_ETH_RXD0, FN_RMII_RXD0, FN_STP_ISEN_0_B, FN_TS_SDAT0_D,
+                FN_GLO_I0_C, FN_SCIFB1_SCK_G, FN_SCK1_E, 0,
+                /* IP6_19_17 [3] */
+                FN_ETH_RX_ER, FN_RMII_RX_ER, FN_STP_ISD_0_B,
+                FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_SDA2_E, FN_SDA2_CIS_E, 0,
+                /* IP6_16_14 [3] */
+                FN_ETH_CRS_DV, FN_RMII_CRS_DV, FN_STP_ISCLK_0_B,
+                FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_SCL2_E,
+                FN_SCL2_CIS_E, 0,
+                /* IP6_13_11 [3] */
+                FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
+                FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 0, 0,
+                /* IP6_10_9 [2] */
+                FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, FN_MSIOF0_TXD_B,
+                /* IP6_8_6 [3] */
+                FN_DACK1, FN_IRQ1, FN_INTC_IRQ1_N, FN_SSI_WS6_B,
+                FN_SSI_SDATA8_C, 0, 0, 0,
+                /* IP6_5_3 [3] */
+                FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
+                FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0,
+                /* IP6_2_0 [3] */
+                FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
+                FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
+                             1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3) {
+                /* IP7_31 [1] */
+                0, 0,
+                /* IP7_30_29 [2] */
+                FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2,
+                FN_MII_RXD2,
+                /* IP7_28_27 [2] */
+                FN_VI0_CLK, FN_ATACS00_N, FN_AVB_RXD1, FN_MII_RXD1,
+                /* IP7_26_25 [2] */
+                FN_DU1_DOTCLKIN, FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, 0,
+                /* IP7_24_22 [3] */
+                FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, FN_PCMWE_N, FN_IECLK_C,
+                0, 0, 0,
+                /* IP7_21_19 [3] */
+                FN_PWM1, FN_SCIFA2_TXD_C, FN_STP_ISSYNC_1_B, FN_TS_SCK1_C,
+                FN_GLO_RFON_C, FN_PCMOE_N, 0, 0,
+                /* IP7_18_16 [3] */
+                FN_PWM0, FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
+                FN_GLO_SS_C, 0, 0, 0,
+                /* IP7_15_13 [3] */
+                FN_ETH_MDC, FN_RMII_MDC, FN_STP_ISD_1_B,
+                FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, 0, 0, 0,
+                /* IP7_12_10 [3] */
+                FN_ETH_TXD0, FN_RMII_TXD0, FN_STP_ISCLK_1_B, FN_TS_SDEN1_C,
+                FN_GLO_SCLK_C, 0, 0, 0,
+                /* IP7_9_8 [2] */
+                FN_ETH_MAGIC, FN_RMII_MAGIC, FN_SIM0_RST_C, 0,
+                /* IP7_7_6 [2] */
+                FN_ETH_TX_EN, FN_RMII_TX_EN, FN_SIM0_CLK_C, FN_HRTS0_N_F,
+                /* IP7_5_3 [3] */
+                FN_ETH_TXD1, FN_RMII_TXD1, FN_HTX0_F, FN_BPFCLK_G, FN_RDS_CLK_F,
+                0, 0, 0,
+                /* IP7_2_0 [3] */
+                FN_ETH_MDIO, FN_RMII_MDIO, FN_HRTS0_N_E,
+                FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
+                             1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2,
+                             2, 2, 2, 2, 2, 2, 2) {
+                /* IP8_31 [1] */
+                0, 0,
+                /* IP8_30_29 [2] */
+                FN_SD0_CMD, FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, 0,
+                /* IP8_28 [1] */
+                FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B,
+                /* IP8_27 [1] */
+                FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,
+                /* IP8_26 [1] */
+                FN_VI1_DATA5_VI1_B5, FN_AVB_PHY_INT,
+                /* IP8_25_24 [2] */
+                FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
+                FN_AVB_MAGIC, FN_MII_MAGIC,
+                /* IP8_23_22 [2] */
+                FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, FN_AVB_GTX_CLK, 0,
+                /* IP8_21_20 [2] */
+                FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO,
+                FN_MII_MDIO,
+                /* IP8_19_18 [2] */
+                FN_VI1_DATA1_VI1_B1, FN_SCIFA1_RXD_D, FN_AVB_MDC, FN_MII_MDC,
+                /* IP8_17_16 [2] */
+                FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, FN_AVB_CRS, FN_MII_CRS,
+                /* IP8_15_14 [2] */
+                FN_VI1_CLK, FN_AVB_RX_DV, FN_MII_RX_DV, 0,
+                /* IP8_13_12 [2] */
+                FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, FN_MII_RX_CLK, 0,
+                /* IP8_11_10 [2] */
+                FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, FN_MII_RX_ER, 0,
+                /* IP8_9_8 [2] */
+                FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, FN_AVB_RXD7, 0,
+                /* IP8_7_6 [2] */
+                FN_VI0_DATA4_VI0_B4, FN_ATAG0_N, FN_AVB_RXD6, 0,
+                /* IP8_5_4 [2] */
+                FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N, FN_AVB_RXD5, 0,
+                /* IP8_3_2 [2] */
+                FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, FN_AVB_RXD4, 0,
+                /* IP8_1_0 [2] */
+                FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, FN_MII_RXD3, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
+                             4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2) {
+                /* IP9_31_28 [4] */
+                FN_SD1_CD, FN_MMC1_D6, FN_TS_SDEN1, FN_USB1_EXTP,
+                FN_GLO_SS, FN_VI0_CLK_B, FN_SCL2_D, FN_SCL2_CIS_D,
+                FN_SIM0_CLK_B, FN_VI3_CLK_B, 0, 0, 0, 0, 0, 0,
+                /* IP9_27_26 [2] */
+                FN_SD1_DAT3, FN_AVB_RXD0, FN_MII_RXD0, FN_SCIFB0_RTS_N_B,
+                /* IP9_25_24 [2] */
+                FN_SD1_DAT2, FN_AVB_COL, FN_MII_COL, FN_SCIFB0_CTS_N_B,
+                /* IP9_23_22 [2] */
+                FN_SD1_DAT1, FN_AVB_LINK, FN_MII_LINK, FN_SCIFB0_TXD_B,
+                /* IP9_21_20 [2] */
+                FN_SD1_DAT0, FN_AVB_TX_CLK, FN_MII_TX_CLK, FN_SCIFB0_RXD_B,
+                /* IP9_19_18 [2] */
+                FN_SD1_CMD, FN_AVB_TX_ER, FN_MII_TX_ER, FN_SCIFB0_SCK_B,
+                /* IP9_17_16 [2] */
+                FN_SD1_CLK, FN_AVB_TX_EN, FN_MII_TX_EN, 0,
+                /* IP9_15_12 [4] */
+                FN_SD0_WP, FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
+                FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_SDA1_B,
+                FN_SDA1_CIS_B, FN_VI2_DATA7_VI2_B7_B, 0, 0, 0, 0, 0, 0, 0,
+                /* IP9_11_8 [4] */
+                FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
+                FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_SCL1_B,
+                FN_SCL1_CIS_B, FN_VI2_DATA6_VI2_B6_B, 0, 0, 0, 0, 0, 0, 0,
+                /* IP9_7_6 [2] */
+                FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, 0,
+                /* IP9_5_4 [2] */
+                FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B, 0,
+                /* IP9_3_2 [2] */
+                FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, 0,
+                /* IP9_1_0 [2] */
+                FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
+                             2, 4, 3, 4, 4, 4, 4, 3, 4) {
+                /* IP10_31_30 [2] */
+                0, 0, 0, 0,
+                /* IP10_29_26 [4] */
+                FN_SD2_CD, FN_MMC0_D4, FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
+                FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
+                FN_GLO_I0_B, FN_VI3_DATA6_B, 0, 0, 0, 0, 0, 0,
+                /* IP10_25_23 [3] */
+                FN_SD2_DAT3, FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
+                FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B, FN_VI3_DATA5_B,
+                /* IP10_22_19 [4] */
+                FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, FN_RDS_CLK,
+                FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
+                FN_GLO_Q0_B, FN_VI3_DATA4_B, 0, 0, 0, 0, 0, 0, 0,
+                /* IP10_18_15 [4] */
+                FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, FN_RDS_DATA,
+                FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
+                FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
+                0, 0, 0, 0, 0, 0,
+                /* IP10_14_11 [4] */
+                FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B,
+                FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D,
+                FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B,
+                0, 0, 0, 0, 0, 0, 0,
+                /* IP10_10_7 [4] */
+                FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D,
+                FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D,
+                FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B,
+                0, 0, 0, 0, 0, 0, 0,
+                /* IP10_6_4 [3] */
+                FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK,
+                FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B,
+                FN_VI3_DATA0_B, 0,
+                /* IP10_3_0 [4] */
+                FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
+                FN_GLO_RFON, FN_VI1_CLK_B, FN_SDA2_D, FN_SDA2_CIS_D,
+                FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
+                             2, 3, 3, 2, 4, 3, 2, 2, 2, 2, 2, 1, 4) {
+                /* IP11_31_30 [2] */
+                FN_SSI_SCK0129, FN_CAN_CLK_B, FN_MOUT0, 0,
+                /* IP11_29_27 [3] */
+                FN_MLB_DAT, FN_SPV_EVEN, FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
+                FN_RDS_CLK_B, 0, 0,
+                /* IP11_26_24 [3] */
+                FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_SDA2_B, FN_SDA2_CIS_B,
+                0, 0, 0,
+                /* IP11_23_22 [2] */
+                FN_MLB_CLK, FN_SCL2_B, FN_SCL2_CIS_B, 0,
+                /* IP11_21_18 [4] */
+                FN_SD3_WP, FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
+                FN_RDS_DATA_B, FN_FMIN_E, FN_RDS_DATA_D, FN_FMIN_F,
+                FN_RDS_DATA_E, 0, 0, 0, 0, 0, 0,
+                /* IP11_17_15 [3] */
+                FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
+                FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, 0, 0,
+                /* IP11_14_13 [2] */
+                FN_SD3_DAT3, FN_MMC1_D3, FN_SCKZ, 0,
+                /* IP11_12_11 [2] */
+                FN_SD3_DAT2, FN_MMC1_D2, FN_SDATA, 0,
+                /* IP11_10_9 [2] */
+                FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, 0,
+                /* IP11_8_7 [2] */
+                FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N, 0,
+                /* IP11_6_5 [2] */
+                FN_SD3_CMD, FN_MMC1_CMD, FN_MTS_N, 0,
+                /* IP11_4 [1] */
+                FN_SD3_CLK, FN_MMC1_CLK,
+                /* IP11_3_0 [4] */
+                FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
+                FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
+                FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
+                             1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2) {
+                /* IP12_31 [1] */
+                0, 0,
+                /* IP12_30_28 [3] */
+                FN_SSI_WS5, FN_SCIFB1_RXD, FN_IECLK_B,
+                FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE,
+                FN_CAN_DEBUGOUT4, 0, 0,
+                /* IP12_27_25 [3] */
+                FN_SSI_SCK5, FN_SCIFB1_SCK,
+                FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS,
+                FN_CAN_DEBUGOUT3, 0, 0,
+                /* IP12_24_23 [2] */
+                FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD,
+                FN_CAN_DEBUGOUT2,
+                /* IP12_22_20 [3] */
+                FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N,
+                FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1, 0, 0,
+                /* IP12_19_17 [3] */
+                FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N,
+                FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0, 0, 0,
+                /* IP12_16_14 [3] */
+                FN_SSI_SDATA3, FN_STP_ISCLK_0,
+                FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK, 0, 0, 0,
+                /* IP12_13_11 [3] */
+                FN_SSI_WS34, FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC,
+                FN_CAN_STEP0, 0, 0, 0,
+                /* IP12_10_8 [3] */
+                FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK,
+                FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, 0, 0, 0,
+                /* IP12_7_6 [2] */
+                FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6,
+                /* IP12_5_4 [2] */
+                FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5, 0,
+                /* IP12_3_2 [2] */
+                FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2, 0,
+                /* IP12_1_0 [2] */
+                FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
+                             1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3) {
+                /* IP13_31 [1] */
+                0, 0,
+                /* IP13_30_29 [2] */
+                FN_AUDIO_CLKA, FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14, 0,
+                /* IP13_28_26 [3] */
+                FN_SSI_SDATA9, FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1,
+                FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, 0, 0,
+                /* IP13_25_23 [3] */
+                FN_SSI_SDATA8, FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C,
+                FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, 0, 0,
+                /* IP13_22_19 [4] */
+                FN_SSI_SDATA7, FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N,
+                FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11, FN_BPFCLK_E,
+                FN_RDS_CLK_D, FN_SSI_SDATA7_B, FN_FMIN_G, FN_RDS_DATA_F,
+                0, 0, 0, 0,
+                /* IP13_18_16 [3] */
+                FN_SSI_WS78, FN_STP_ISCLK_1, FN_SCIFB2_SCK, FN_SCIFA2_CTS_N,
+                FN_DU2_DR7, FN_LCDOUT7, FN_CAN_DEBUGOUT10, 0,
+                /* IP13_15_13 [3] */
+                FN_SSI_SCK78, FN_STP_IVCXO27_1, FN_SCK1, FN_SCIFA1_SCK,
+                FN_DU2_DR6, FN_LCDOUT6, FN_CAN_DEBUGOUT9, 0,
+                /* IP13_12_10 [3] */
+                FN_SSI_SDATA6, FN_FMIN_D, FN_RDS_DATA_C, FN_DU2_DR5, FN_LCDOUT5,
+                FN_CAN_DEBUGOUT8, 0, 0,
+                /* IP13_9_7 [3] */
+                FN_SSI_WS6, FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4,
+                FN_LCDOUT4, FN_CAN_DEBUGOUT7, 0, 0,
+                /* IP13_6_3 [4] */
+                FN_SSI_SCK6, FN_SCIFB1_CTS_N, FN_BPFCLK_D, FN_RDS_CLK_C,
+                FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6,
+                FN_BPFCLK_F, FN_RDS_CLK_E, 0, 0, 0, 0, 0, 0, 0,
+                /* IP13_2_0 [3] */
+                FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
+                FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
+                             1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3) {
+                /* IP14_30 [1] */
+                0, 0,
+                /* IP14_30_28 [3] */
+                FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N_TANS,
+                FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE,
+                FN_HRTS0_N_C, 0,
+                /* IP14_27_25 [3] */
+                FN_SCIFA1_CTS_N, FN_AD_CLK, FN_CTS1_N, FN_MSIOF3_RXD,
+                FN_DU0_DOTCLKOUT, FN_QCLK, 0, 0,
+                /* IP14_24_22 [3] */
+                FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1,
+                FN_LCDOUT9, 0, 0, 0,
+                /* IP14_21_19 [3] */
+                FN_SCIFA1_RXD, FN_AD_DI, FN_RX1,
+                FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE, 0, 0, 0,
+                /* IP14_18_16 [3] */
+                FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N_TANS,
+                FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, 0,
+                /* IP14_15_12 [4] */
+                FN_SCIFA0_CTS_N, FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC,
+                FN_DU2_DG3, FN_LCDOUT11, FN_PWM0_B, FN_SCL1_C, FN_SCL1_CIS_C,
+                0, 0, 0, 0, 0, 0, 0,
+                /* IP14_11_9 [3] */
+                FN_SCIFA0_TXD, FN_HTX1, FN_TX0, FN_DU2_DR1, FN_LCDOUT1,
+                0, 0, 0,
+                /* IP14_8_6 [3] */
+                FN_SCIFA0_RXD, FN_HRX1, FN_RX0, FN_DU2_DR0, FN_LCDOUT0,
+                0, 0, 0,
+                /* IP14_5_3 [3] */
+                FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0, FN_MSIOF3_SS2, FN_DU2_DG2,
+                FN_LCDOUT10, FN_SDA1_C, FN_SDA1_CIS_C,
+                /* IP14_2_0 [3] */
+                FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D,
+                FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15,
+                FN_REMOCON, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
+                             2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3) {
+                /* IP15_31_30 [2] */
+                0, 0, 0, 0,
+                /* IP15_29_28 [2] */
+                FN_MSIOF0_TXD, FN_ADICHS1, FN_DU2_DG6, FN_LCDOUT14,
+                /* IP15_27_26 [2] */
+                FN_MSIOF0_SS1, FN_ADICHS0, FN_DU2_DG5, FN_LCDOUT13,
+                /* IP15_25_23 [3] */
+                FN_MSIOF0_SYNC, FN_TS_SCK0, FN_SSI_SCK2, FN_ADIDATA,
+                FN_DU2_DB7, FN_LCDOUT23, FN_SCIFA2_RXD_B, 0,
+                /* IP15_22_20 [3] */
+                FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK,
+                FN_DU2_DB6, FN_LCDOUT22, 0, 0, 0,
+                /* IP15_19_18 [2] */
+                FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5, FN_LCDOUT21,
+                /* IP15_17_16 [2] */
+                FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4, FN_LCDOUT20,
+                /* IP15_15_14 [2] */
+                FN_HTX0, FN_DU2_DB3, FN_LCDOUT19, 0,
+                /* IP15_13_12 [2] */
+                FN_HRX0, FN_DU2_DB2, FN_LCDOUT18, 0,
+                /* IP15_11_9 [3] */
+                FN_HSCK0, FN_TS_SDEN0, FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C,
+                0, 0, 0,
+                /* IP15_8_6 [3] */
+                FN_SCIFA2_TXD, FN_BPFCLK, 0, FN_DU2_DB1, FN_LCDOUT17,
+                FN_SDA2, FN_SDA2_CIS, 0,
+                /* IP15_5_3 [3] */
+                FN_SCIFA2_RXD, FN_FMIN, 0, FN_DU2_DB0, FN_LCDOUT16,
+                FN_SCL2, FN_SCL2_CIS, 0,
+                /* IP15_2_0 [3] */
+                FN_SCIFA2_SCK, FN_FMCLK, 0, FN_MSIOF3_SCK, FN_DU2_DG7,
+                FN_LCDOUT15, FN_SCIF_CLK_B, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
+                             4, 4, 4, 4, 4, 4, 1, 1, 3, 3) {
+                /* IP16_31_28 [4] */
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP16_27_24 [4] */
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP16_23_20 [4] */
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP16_19_16 [4] */
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP16_15_12 [4] */
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP16_11_8 [4] */
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP16_7 [1] */
+                FN_USB1_OVC, FN_TCLK1_B,
+                /* IP16_6 [1] */
+                FN_USB1_PWEN, FN_AUDIO_CLKOUT_D,
+                /* IP16_5_3 [3] */
+                FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2,
+                FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_HRX0_C, 0,
+                /* IP16_2_0 [3] */
+                FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2,
+                FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
+                             3, 2, 2, 3, 2, 1, 1, 1, 2, 1,
+                             2, 1, 1, 1, 1, 2, 1, 1, 2, 1, 1) {
+                /* SEL_SCIF1 [3] */
+                FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
+                FN_SEL_SCIF1_4, 0, 0, 0,
+                /* SEL_SCIFB [2] */
+                FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, 0,
+                /* SEL_SCIFB2 [2] */
+                FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, 0,
+                /* SEL_SCIFB1 [3] */
+                FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2,
+                FN_SEL_SCIFB1_3, FN_SEL_SCIFB1_4, FN_SEL_SCIFB1_5,
+                FN_SEL_SCIFB1_6, 0,
+                /* SEL_SCIFA1 [2] */
+                FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
+                FN_SEL_SCIFA1_3,
+                /* SEL_SCIF0 [1] */
+                FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
+                /* SEL_SCIFA [1] */
+                FN_SEL_SCFA_0, FN_SEL_SCFA_1,
+                /* SEL_SOF1 [1] */
+                FN_SEL_SOF1_0, FN_SEL_SOF1_1,
+                /* SEL_SSI7 [2] */
+                FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 0,
+                /* SEL_SSI6 [1] */
+                FN_SEL_SSI6_0, FN_SEL_SSI6_1,
+                /* SEL_SSI5 [2] */
+                FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2, 0,
+                /* SEL_VI3 [1] */
+                FN_SEL_VI3_0, FN_SEL_VI3_1,
+                /* SEL_VI2 [1] */
+                FN_SEL_VI2_0, FN_SEL_VI2_1,
+                /* SEL_VI1 [1] */
+                FN_SEL_VI1_0, FN_SEL_VI1_1,
+                /* SEL_VI0 [1] */
+                FN_SEL_VI0_0, FN_SEL_VI0_1,
+                /* SEL_TSIF1 [2] */
+                FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, 0,
+                /* RESERVED [1] */
+                0, 0,
+                /* SEL_LBS [1] */
+                FN_SEL_LBS_0, FN_SEL_LBS_1,
+                /* SEL_TSIF0 [2] */
+                FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
+                /* SEL_SOF3 [1] */
+                FN_SEL_SOF3_0, FN_SEL_SOF3_1,
+                /* SEL_SOF0 [1] */
+                FN_SEL_SOF0_0, FN_SEL_SOF0_1, }
+        },
+        { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
+                             3, 1, 1, 1, 2, 1, 2, 1, 2,
+                             1, 1, 1, 3, 3, 2, 3, 2, 2) {
+                /* RESERVED [3] */
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* SEL_TMU1 [1] */
+                FN_SEL_TMU1_0, FN_SEL_TMU1_1,
+                /* SEL_HSCIF1 [1] */
+                FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
+                /* SEL_SCIFCLK [1] */
+                FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
+                /* SEL_CAN0 [2] */
+                FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
+                /* SEL_CANCLK [1] */
+                FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
+                /* SEL_SCIFA2 [2] */
+                FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, 0,
+                /* SEL_CAN1 [1] */
+                FN_SEL_CAN1_0, FN_SEL_CAN1_1,
+                /* RESERVED [2] */
+                0, 0, 0, 0,
+                /* RESERVED [1] (actually TX2, RX2 vs. TX2_B, RX2_B of SCIF2) */
+                0, 0,
+                /* SEL_ADI [1] */
+                FN_SEL_ADI_0, FN_SEL_ADI_1,
+                /* SEL_SSP [1] */
+                FN_SEL_SSP_0, FN_SEL_SSP_1,
+                /* SEL_FM [3] */
+                FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
+                FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6, 0,
+                /* SEL_HSCIF0 [3] */
+                FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
+                FN_SEL_HSCIF0_3, FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, 0, 0,
+                /* SEL_GPS [2] */
+                FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, 0,
+                /* SEL_RDS [3] */
+                FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2,
+                FN_SEL_RDS_3, FN_SEL_RDS_4, FN_SEL_RDS_5, 0, 0,
+                /* SEL_SIM [2] */
+                FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 0,
+                /* SEL_SSI8 [2] */
+                FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
+                             1, 1, 2, 4, 4, 2, 2,
+                             4, 2, 3, 2, 3, 2) {
+                /* SEL_IICDVFS [1] */
+                FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
+                /* SEL_IIC0 [1] */
+                FN_SEL_IIC0_0, FN_SEL_IIC0_1,
+                /* RESERVED [2] */
+                0, 0, 0, 0,
+                /* RESERVED [4] */
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* RESERVED [4] */
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* RESERVED [2] */
+                0, 0, 0, 0,
+                /* SEL_IEB [2] */
+                FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
+                /* RESERVED [4] */
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* RESERVED [2] */
+                0, 0, 0, 0,
+                /* SEL_IIC2 [3] */
+                FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
+                FN_SEL_IIC2_4, 0, 0, 0,
+                /* SEL_IIC1 [2] */
+                FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 0,
+                /* SEL_I2C2 [3] */
+                FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
+                FN_SEL_I2C2_4, 0, 0, 0,
+                /* SEL_I2C1 [2] */
+                FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, }
+        },
+        { },
+};
+
+const struct sh_pfc_soc_info r8a7790_pinmux_info = {
+        .name = "r8a77900_pfc",
+        .unlock_reg = 0xe6060000, /* PMMR */
+
+        .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+        .pins = pinmux_pins,
+        .nr_pins = ARRAY_SIZE(pinmux_pins),
+        .groups = pinmux_groups,
+        .nr_groups = ARRAY_SIZE(pinmux_groups),
+        .functions = pinmux_functions,
+        .nr_functions = ARRAY_SIZE(pinmux_functions),
+
+        .cfg_regs = pinmux_config_regs,
+
+        .gpio_data = pinmux_data,
+        .gpio_data_size = ARRAY_SIZE(pinmux_data),
+};
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
index df0ae21a5ac8..6dfb18772574 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
@@ -20,10 +20,14 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
+#include <linux/io.h>
 #include <linux/kernel.h>
+#include <linux/pinctrl/pinconf-generic.h>
+
 #include <mach/irqs.h>
 #include <mach/sh7372.h>
 
+#include "core.h"
 #include "sh_pfc.h"
 
 #define CPU_ALL_PORT(fn, pfx, sfx) \
@@ -34,6 +38,35 @@
         PORT_10(fn, pfx##16, sfx),      PORT_10(fn, pfx##17, sfx), \
         PORT_10(fn, pfx##18, sfx),      PORT_1(fn, pfx##190, sfx)
 
+#undef _GPIO_PORT
+#define _GPIO_PORT(gpio, sfx)                                           \
+        [gpio] = {                                                      \
+                .name = __stringify(PORT##gpio),                        \
+                .enum_id = PORT##gpio##_DATA,                           \
+        }
+
+#define IRQC_PIN_MUX(irq, pin)                                          \
+static const unsigned int intc_irq##irq##_pins[] = {                    \
+        pin,                                                            \
+};                                                                      \
+static const unsigned int intc_irq##irq##_mux[] = {                     \
+        IRQ##irq##_MARK,                                                \
+}
+
+#define IRQC_PINS_MUX(irq, pin0, pin1)                                  \
+static const unsigned int intc_irq##irq##_0_pins[] = {                  \
+        pin0,                                                           \
+};                                                                      \
+static const unsigned int intc_irq##irq##_0_mux[] = {                   \
+        IRQ##irq##_##pin0##_MARK,                                       \
+};                                                                      \
+static const unsigned int intc_irq##irq##_1_pins[] = {                  \
+        pin1,                                                           \
+};                                                                      \
+static const unsigned int intc_irq##irq##_1_mux[] = {                   \
+        IRQ##irq##_##pin1##_MARK,                                       \
+}
+
 enum {
         PINMUX_RESERVED = 0,
 
@@ -47,16 +80,6 @@ enum {
         PORT_ALL(IN),
         PINMUX_INPUT_END,
 
-        /* PORT0_IN_PU -> PORT190_IN_PU */
-        PINMUX_INPUT_PULLUP_BEGIN,
-        PORT_ALL(IN_PU),
-        PINMUX_INPUT_PULLUP_END,
-
-        /* PORT0_IN_PD -> PORT190_IN_PD */
-        PINMUX_INPUT_PULLDOWN_BEGIN,
-        PORT_ALL(IN_PD),
-        PINMUX_INPUT_PULLDOWN_END,
-
         /* PORT0_OUT -> PORT190_OUT */
         PINMUX_OUTPUT_BEGIN,
         PORT_ALL(OUT),
@@ -368,124 +391,11 @@ enum {
         PINMUX_MARK_END,
 };
 
-static const pinmux_enum_t pinmux_data[] = {
+#define _PORT_DATA(pfx, sfx)    PORT_DATA_IO(pfx)
+#define PINMUX_DATA_GP_ALL()    CPU_ALL_PORT(_PORT_DATA, , unused)
 
-        /* specify valid pin states for each pin in GPIO mode */
-        PORT_DATA_IO_PD(0),             PORT_DATA_IO_PD(1),
-        PORT_DATA_O(2),                 PORT_DATA_I_PD(3),
-        PORT_DATA_I_PD(4),              PORT_DATA_I_PD(5),
-        PORT_DATA_IO_PU_PD(6),          PORT_DATA_I_PD(7),
-        PORT_DATA_IO_PD(8),             PORT_DATA_O(9),
-
-        PORT_DATA_O(10),                PORT_DATA_O(11),
-        PORT_DATA_IO_PU_PD(12),         PORT_DATA_IO_PD(13),
-        PORT_DATA_IO_PD(14),            PORT_DATA_O(15),
-        PORT_DATA_IO_PD(16),            PORT_DATA_IO_PD(17),
-        PORT_DATA_I_PD(18),             PORT_DATA_IO(19),
-
-        PORT_DATA_IO(20),               PORT_DATA_IO(21),
-        PORT_DATA_IO(22),               PORT_DATA_IO(23),
-        PORT_DATA_IO(24),               PORT_DATA_IO(25),
-        PORT_DATA_IO(26),               PORT_DATA_IO(27),
-        PORT_DATA_IO(28),               PORT_DATA_IO(29),
-
-        PORT_DATA_IO(30),               PORT_DATA_IO(31),
-        PORT_DATA_IO(32),               PORT_DATA_IO(33),
-        PORT_DATA_IO(34),               PORT_DATA_IO(35),
-        PORT_DATA_IO(36),               PORT_DATA_IO(37),
-        PORT_DATA_IO(38),               PORT_DATA_IO(39),
-
-        PORT_DATA_IO(40),               PORT_DATA_IO(41),
-        PORT_DATA_IO(42),               PORT_DATA_IO(43),
-        PORT_DATA_IO(44),               PORT_DATA_IO(45),
-        PORT_DATA_IO_PU(46),            PORT_DATA_IO_PU(47),
-        PORT_DATA_IO_PU(48),            PORT_DATA_IO_PU(49),
-
-        PORT_DATA_IO_PU(50),            PORT_DATA_IO_PU(51),
-        PORT_DATA_IO_PU(52),            PORT_DATA_IO_PU(53),
-        PORT_DATA_IO_PU(54),            PORT_DATA_IO_PU(55),
-        PORT_DATA_IO_PU(56),            PORT_DATA_IO_PU(57),
-        PORT_DATA_IO_PU(58),            PORT_DATA_IO_PU(59),
-
-        PORT_DATA_IO_PU(60),            PORT_DATA_IO_PU(61),
-        PORT_DATA_IO(62),               PORT_DATA_O(63),
-        PORT_DATA_O(64),                PORT_DATA_IO_PU(65),
-        PORT_DATA_O(66),                PORT_DATA_IO_PU(67),  /*66?*/
-        PORT_DATA_O(68),                PORT_DATA_IO(69),
-
-        PORT_DATA_IO(70),               PORT_DATA_IO(71),
-        PORT_DATA_O(72),                PORT_DATA_I_PU(73),
-        PORT_DATA_I_PU_PD(74),          PORT_DATA_IO_PU_PD(75),
-        PORT_DATA_IO_PU_PD(76),         PORT_DATA_IO_PU_PD(77),
-        PORT_DATA_IO_PU_PD(78),         PORT_DATA_IO_PU_PD(79),
-
-        PORT_DATA_IO_PU_PD(80),         PORT_DATA_IO_PU_PD(81),
-        PORT_DATA_IO_PU_PD(82),         PORT_DATA_IO_PU_PD(83),
-        PORT_DATA_IO_PU_PD(84),         PORT_DATA_IO_PU_PD(85),
-        PORT_DATA_IO_PU_PD(86),         PORT_DATA_IO_PU_PD(87),
-        PORT_DATA_IO_PU_PD(88),         PORT_DATA_IO_PU_PD(89),
-
-        PORT_DATA_IO_PU_PD(90),         PORT_DATA_IO_PU_PD(91),
-        PORT_DATA_IO_PU_PD(92),         PORT_DATA_IO_PU_PD(93),
-        PORT_DATA_IO_PU_PD(94),         PORT_DATA_IO_PU_PD(95),
-        PORT_DATA_IO_PU(96),            PORT_DATA_IO_PU_PD(97),
-        PORT_DATA_IO_PU_PD(98),         PORT_DATA_O(99), /*99?*/
-
-        PORT_DATA_IO_PD(100),           PORT_DATA_IO_PD(101),
-        PORT_DATA_IO_PD(102),           PORT_DATA_IO_PD(103),
-        PORT_DATA_IO_PD(104),           PORT_DATA_IO_PD(105),
-        PORT_DATA_IO_PU(106),           PORT_DATA_IO_PU(107),
-        PORT_DATA_IO_PU(108),           PORT_DATA_IO_PU(109),
-
-        PORT_DATA_IO_PU(110),           PORT_DATA_IO_PU(111),
-        PORT_DATA_IO_PD(112),           PORT_DATA_IO_PD(113),
-        PORT_DATA_IO_PU(114),           PORT_DATA_IO_PU(115),
-        PORT_DATA_IO_PU(116),           PORT_DATA_IO_PU(117),
-        PORT_DATA_IO_PU(118),           PORT_DATA_IO_PU(119),
-
-        PORT_DATA_IO_PU(120),           PORT_DATA_IO_PD(121),
-        PORT_DATA_IO_PD(122),           PORT_DATA_IO_PD(123),
-        PORT_DATA_IO_PD(124),           PORT_DATA_IO_PD(125),
-        PORT_DATA_IO_PD(126),           PORT_DATA_IO_PD(127),
-        PORT_DATA_IO_PD(128),           PORT_DATA_IO_PU_PD(129),
-
-        PORT_DATA_IO_PU_PD(130),        PORT_DATA_IO_PU_PD(131),
-        PORT_DATA_IO_PU_PD(132),        PORT_DATA_IO_PU_PD(133),
-        PORT_DATA_IO_PU_PD(134),        PORT_DATA_IO_PU_PD(135),
-        PORT_DATA_IO_PD(136),           PORT_DATA_IO_PD(137),
-        PORT_DATA_IO_PD(138),           PORT_DATA_IO_PD(139),
-
-        PORT_DATA_IO_PD(140),           PORT_DATA_IO_PD(141),
-        PORT_DATA_IO_PD(142),           PORT_DATA_IO_PU_PD(143),
-        PORT_DATA_IO_PD(144),           PORT_DATA_IO_PD(145),
-        PORT_DATA_IO_PD(146),           PORT_DATA_IO_PD(147),
-        PORT_DATA_IO_PD(148),           PORT_DATA_IO_PD(149),
-
-        PORT_DATA_IO_PD(150),           PORT_DATA_IO_PD(151),
-        PORT_DATA_IO_PU_PD(152),        PORT_DATA_I_PD(153),
-        PORT_DATA_IO_PU_PD(154),        PORT_DATA_I_PD(155),
-        PORT_DATA_IO_PD(156),           PORT_DATA_IO_PD(157),
-        PORT_DATA_I_PD(158),            PORT_DATA_IO_PD(159),
-
-        PORT_DATA_O(160),               PORT_DATA_IO_PD(161),
-        PORT_DATA_IO_PD(162),           PORT_DATA_IO_PD(163),
-        PORT_DATA_I_PD(164),            PORT_DATA_IO_PD(165),
-        PORT_DATA_I_PD(166),            PORT_DATA_I_PD(167),
-        PORT_DATA_I_PD(168),            PORT_DATA_I_PD(169),
-
-        PORT_DATA_I_PD(170),            PORT_DATA_O(171),
-        PORT_DATA_IO_PU_PD(172),        PORT_DATA_IO_PU_PD(173),
-        PORT_DATA_IO_PU_PD(174),        PORT_DATA_IO_PU_PD(175),
-        PORT_DATA_IO_PU_PD(176),        PORT_DATA_IO_PU_PD(177),
-        PORT_DATA_IO_PU_PD(178),        PORT_DATA_O(179),
-
-        PORT_DATA_IO_PU_PD(180),        PORT_DATA_IO_PU_PD(181),
-        PORT_DATA_IO_PU_PD(182),        PORT_DATA_IO_PU_PD(183),
-        PORT_DATA_IO_PU_PD(184),        PORT_DATA_O(185),
-        PORT_DATA_IO_PU_PD(186),        PORT_DATA_IO_PU_PD(187),
-        PORT_DATA_IO_PU_PD(188),        PORT_DATA_IO_PU_PD(189),
-
-        PORT_DATA_IO_PU_PD(190),
+static const pinmux_enum_t pinmux_data[] = {
+        PINMUX_DATA_GP_ALL(),
 
         /* IRQ */
         PINMUX_DATA(IRQ0_6_MARK,        PORT6_FN0,      MSEL1CR_0_0),
@@ -929,10 +839,582 @@ static const pinmux_enum_t pinmux_data[] = {
         PINMUX_DATA(MFIv4_MARK,         MSEL4CR_6_1),
 };
 
+#define SH7372_PIN(pin, cfgs)                                           \
+        {                                                               \
+                .name = __stringify(PORT##pin),                         \
+                .enum_id = PORT##pin##_DATA,                            \
+                .configs = cfgs,                                        \
+        }
+
+#define __I             (SH_PFC_PIN_CFG_INPUT)
+#define __O             (SH_PFC_PIN_CFG_OUTPUT)
+#define __IO            (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
+#define __PD            (SH_PFC_PIN_CFG_PULL_DOWN)
+#define __PU            (SH_PFC_PIN_CFG_PULL_UP)
+#define __PUD           (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
+
+#define SH7372_PIN_I_PD(pin)            SH7372_PIN(pin, __I | __PD)
+#define SH7372_PIN_I_PU(pin)            SH7372_PIN(pin, __I | __PU)
+#define SH7372_PIN_I_PU_PD(pin)         SH7372_PIN(pin, __I | __PUD)
+#define SH7372_PIN_IO(pin)              SH7372_PIN(pin, __IO)
+#define SH7372_PIN_IO_PD(pin)           SH7372_PIN(pin, __IO | __PD)
+#define SH7372_PIN_IO_PU(pin)           SH7372_PIN(pin, __IO | __PU)
+#define SH7372_PIN_IO_PU_PD(pin)        SH7372_PIN(pin, __IO | __PUD)
+#define SH7372_PIN_O(pin)               SH7372_PIN(pin, __O)
+#define SH7372_PIN_O_PU_PD(pin)         SH7372_PIN(pin, __O | __PUD)
+
 static struct sh_pfc_pin pinmux_pins[] = {
-        GPIO_PORT_ALL(),
+        /* Table 57-1 (I/O and Pull U/D) */
+        SH7372_PIN_IO_PD(0),            SH7372_PIN_IO_PD(1),
+        SH7372_PIN_O(2),                SH7372_PIN_I_PD(3),
+        SH7372_PIN_I_PD(4),             SH7372_PIN_I_PD(5),
+        SH7372_PIN_IO_PU_PD(6),         SH7372_PIN_I_PD(7),
+        SH7372_PIN_IO_PD(8),            SH7372_PIN_O(9),
+        SH7372_PIN_O(10),               SH7372_PIN_O(11),
+        SH7372_PIN_IO_PU_PD(12),        SH7372_PIN_IO_PD(13),
+        SH7372_PIN_IO_PD(14),           SH7372_PIN_O(15),
+        SH7372_PIN_IO_PD(16),           SH7372_PIN_IO_PD(17),
+        SH7372_PIN_I_PD(18),            SH7372_PIN_IO(19),
+        SH7372_PIN_IO(20),              SH7372_PIN_IO(21),
+        SH7372_PIN_IO(22),              SH7372_PIN_IO(23),
+        SH7372_PIN_IO(24),              SH7372_PIN_IO(25),
+        SH7372_PIN_IO(26),              SH7372_PIN_IO(27),
+        SH7372_PIN_IO(28),              SH7372_PIN_IO(29),
+        SH7372_PIN_IO(30),              SH7372_PIN_IO(31),
+        SH7372_PIN_IO(32),              SH7372_PIN_IO(33),
+        SH7372_PIN_IO(34),              SH7372_PIN_IO(35),
+        SH7372_PIN_IO(36),              SH7372_PIN_IO(37),
+        SH7372_PIN_IO(38),              SH7372_PIN_IO(39),
+        SH7372_PIN_IO(40),              SH7372_PIN_IO(41),
+        SH7372_PIN_IO(42),              SH7372_PIN_IO(43),
+        SH7372_PIN_IO(44),              SH7372_PIN_IO(45),
+        SH7372_PIN_IO_PU(46),           SH7372_PIN_IO_PU(47),
+        SH7372_PIN_IO_PU(48),           SH7372_PIN_IO_PU(49),
+        SH7372_PIN_IO_PU(50),           SH7372_PIN_IO_PU(51),
+        SH7372_PIN_IO_PU(52),           SH7372_PIN_IO_PU(53),
+        SH7372_PIN_IO_PU(54),           SH7372_PIN_IO_PU(55),
+        SH7372_PIN_IO_PU(56),           SH7372_PIN_IO_PU(57),
+        SH7372_PIN_IO_PU(58),           SH7372_PIN_IO_PU(59),
+        SH7372_PIN_IO_PU(60),           SH7372_PIN_IO_PU(61),
+        SH7372_PIN_IO(62),              SH7372_PIN_O(63),
+        SH7372_PIN_O(64),               SH7372_PIN_IO_PU(65),
+        SH7372_PIN_O_PU_PD(66),         SH7372_PIN_IO_PU(67),
+        SH7372_PIN_O(68),               SH7372_PIN_IO(69),
+        SH7372_PIN_IO(70),              SH7372_PIN_IO(71),
+        SH7372_PIN_O(72),               SH7372_PIN_I_PU(73),
+        SH7372_PIN_I_PU_PD(74),         SH7372_PIN_IO_PU_PD(75),
+        SH7372_PIN_IO_PU_PD(76),        SH7372_PIN_IO_PU_PD(77),
+        SH7372_PIN_IO_PU_PD(78),        SH7372_PIN_IO_PU_PD(79),
+        SH7372_PIN_IO_PU_PD(80),        SH7372_PIN_IO_PU_PD(81),
+        SH7372_PIN_IO_PU_PD(82),        SH7372_PIN_IO_PU_PD(83),
+        SH7372_PIN_IO_PU_PD(84),        SH7372_PIN_IO_PU_PD(85),
+        SH7372_PIN_IO_PU_PD(86),        SH7372_PIN_IO_PU_PD(87),
+        SH7372_PIN_IO_PU_PD(88),        SH7372_PIN_IO_PU_PD(89),
+        SH7372_PIN_IO_PU_PD(90),        SH7372_PIN_IO_PU_PD(91),
+        SH7372_PIN_IO_PU_PD(92),        SH7372_PIN_IO_PU_PD(93),
+        SH7372_PIN_IO_PU_PD(94),        SH7372_PIN_IO_PU_PD(95),
+        SH7372_PIN_IO_PU(96),           SH7372_PIN_IO_PU_PD(97),
+        SH7372_PIN_IO_PU_PD(98),        SH7372_PIN_O_PU_PD(99),
+        SH7372_PIN_IO_PD(100),          SH7372_PIN_IO_PD(101),
+        SH7372_PIN_IO_PD(102),          SH7372_PIN_IO_PD(103),
+        SH7372_PIN_IO_PD(104),          SH7372_PIN_IO_PD(105),
+        SH7372_PIN_IO_PU(106),          SH7372_PIN_IO_PU(107),
+        SH7372_PIN_IO_PU(108),          SH7372_PIN_IO_PU(109),
+        SH7372_PIN_IO_PU(110),          SH7372_PIN_IO_PU(111),
+        SH7372_PIN_IO_PD(112),          SH7372_PIN_IO_PD(113),
+        SH7372_PIN_IO_PU(114),          SH7372_PIN_IO_PU(115),
+        SH7372_PIN_IO_PU(116),          SH7372_PIN_IO_PU(117),
+        SH7372_PIN_IO_PU(118),          SH7372_PIN_IO_PU(119),
+        SH7372_PIN_IO_PU(120),          SH7372_PIN_IO_PD(121),
+        SH7372_PIN_IO_PD(122),          SH7372_PIN_IO_PD(123),
+        SH7372_PIN_IO_PD(124),          SH7372_PIN_IO_PD(125),
+        SH7372_PIN_IO_PD(126),          SH7372_PIN_IO_PD(127),
+        SH7372_PIN_IO_PD(128),          SH7372_PIN_IO_PU_PD(129),
+        SH7372_PIN_IO_PU_PD(130),       SH7372_PIN_IO_PU_PD(131),
+        SH7372_PIN_IO_PU_PD(132),       SH7372_PIN_IO_PU_PD(133),
+        SH7372_PIN_IO_PU_PD(134),       SH7372_PIN_IO_PU_PD(135),
+        SH7372_PIN_IO_PD(136),          SH7372_PIN_IO_PD(137),
+        SH7372_PIN_IO_PD(138),          SH7372_PIN_IO_PD(139),
+        SH7372_PIN_IO_PD(140),          SH7372_PIN_IO_PD(141),
+        SH7372_PIN_IO_PD(142),          SH7372_PIN_IO_PU_PD(143),
+        SH7372_PIN_IO_PD(144),          SH7372_PIN_IO_PD(145),
+        SH7372_PIN_IO_PD(146),          SH7372_PIN_IO_PD(147),
+        SH7372_PIN_IO_PD(148),          SH7372_PIN_IO_PD(149),
+        SH7372_PIN_IO_PD(150),          SH7372_PIN_IO_PD(151),
+        SH7372_PIN_IO_PU_PD(152),       SH7372_PIN_I_PD(153),
+        SH7372_PIN_IO_PU_PD(154),       SH7372_PIN_I_PD(155),
+        SH7372_PIN_IO_PD(156),          SH7372_PIN_IO_PD(157),
+        SH7372_PIN_I_PD(158),           SH7372_PIN_IO_PD(159),
+        SH7372_PIN_O(160),              SH7372_PIN_IO_PD(161),
+        SH7372_PIN_IO_PD(162),          SH7372_PIN_IO_PD(163),
+        SH7372_PIN_I_PD(164),           SH7372_PIN_IO_PD(165),
+        SH7372_PIN_I_PD(166),           SH7372_PIN_I_PD(167),
+        SH7372_PIN_I_PD(168),           SH7372_PIN_I_PD(169),
+        SH7372_PIN_I_PD(170),           SH7372_PIN_O(171),
+        SH7372_PIN_IO_PU_PD(172),       SH7372_PIN_IO_PU_PD(173),
+        SH7372_PIN_IO_PU_PD(174),       SH7372_PIN_IO_PU_PD(175),
+        SH7372_PIN_IO_PU_PD(176),       SH7372_PIN_IO_PU_PD(177),
+        SH7372_PIN_IO_PU_PD(178),       SH7372_PIN_O(179),
+        SH7372_PIN_IO_PU_PD(180),       SH7372_PIN_IO_PU_PD(181),
+        SH7372_PIN_IO_PU_PD(182),       SH7372_PIN_IO_PU_PD(183),
+        SH7372_PIN_IO_PU_PD(184),       SH7372_PIN_O(185),
+        SH7372_PIN_IO_PU_PD(186),       SH7372_PIN_IO_PU_PD(187),
+        SH7372_PIN_IO_PU_PD(188),       SH7372_PIN_IO_PU_PD(189),
+        SH7372_PIN_IO_PU_PD(190),
 };
 
+/* - BSC -------------------------------------------------------------------- */
+static const unsigned int bsc_data8_pins[] = {
+        /* D[0:7] */
+        46, 47, 48, 49, 50, 51, 52, 53,
+};
+static const unsigned int bsc_data8_mux[] = {
+        D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
+        D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
+};
+static const unsigned int bsc_data16_pins[] = {
+        /* D[0:15] */
+        46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61,
+};
+static const unsigned int bsc_data16_mux[] = {
+        D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
+        D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
+        D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
+        D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
+};
+static const unsigned int bsc_cs0_pins[] = {
+        /* CS */
+        62,
+};
+static const unsigned int bsc_cs0_mux[] = {
+        CS0_MARK,
+};
+static const unsigned int bsc_cs2_pins[] = {
+        /* CS */
+        63,
+};
+static const unsigned int bsc_cs2_mux[] = {
+        CS2_MARK,
+};
+static const unsigned int bsc_cs4_pins[] = {
+        /* CS */
+        64,
+};
+static const unsigned int bsc_cs4_mux[] = {
+        CS4_MARK,
+};
+static const unsigned int bsc_cs5a_pins[] = {
+        /* CS */
+        65,
+};
+static const unsigned int bsc_cs5a_mux[] = {
+        CS5A_MARK,
+};
+static const unsigned int bsc_cs5b_pins[] = {
+        /* CS */
+        66,
+};
+static const unsigned int bsc_cs5b_mux[] = {
+        CS5B_MARK,
+};
+static const unsigned int bsc_cs6a_pins[] = {
+        /* CS */
+        67,
+};
+static const unsigned int bsc_cs6a_mux[] = {
+        CS6A_MARK,
+};
+static const unsigned int bsc_rd_we8_pins[] = {
+        /* RD, WE[0] */
+        69, 70,
+};
+static const unsigned int bsc_rd_we8_mux[] = {
+        RD_FSC_MARK, WE0_FWE_MARK,
+};
+static const unsigned int bsc_rd_we16_pins[] = {
+        /* RD, WE[0:1] */
+        69, 70, 71,
+};
+static const unsigned int bsc_rd_we16_mux[] = {
+        RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK,
+};
+static const unsigned int bsc_bs_pins[] = {
+        /* BS */
+        19,
+};
+static const unsigned int bsc_bs_mux[] = {
+        BS_MARK,
+};
+static const unsigned int bsc_rdwr_pins[] = {
+        /* RDWR */
+        75,
+};
+static const unsigned int bsc_rdwr_mux[] = {
+        RDWR_MARK,
+};
+static const unsigned int bsc_wait_pins[] = {
+        /* WAIT */
+        74,
+};
+static const unsigned int bsc_wait_mux[] = {
+        WAIT_MARK,
+};
+/* - CEU -------------------------------------------------------------------- */
+static const unsigned int ceu_data_0_7_pins[] = {
+        /* D[0:7] */
+        102, 103, 104, 105, 106, 107, 108, 109,
+};
+static const unsigned int ceu_data_0_7_mux[] = {
+        VIO_D0_MARK, VIO_D1_MARK, VIO_D2_MARK, VIO_D3_MARK,
+        VIO_D4_MARK, VIO_D5_MARK, VIO_D6_MARK, VIO_D7_MARK,
+};
+static const unsigned int ceu_data_8_15_pins[] = {
+        /* D[8:15] */
+        110, 111, 112, 113, 114, 115, 116, 117,
+};
+static const unsigned int ceu_data_8_15_mux[] = {
+        VIO_D8_MARK, VIO_D9_MARK, VIO_D10_MARK, VIO_D11_MARK,
+        VIO_D12_MARK, VIO_D13_MARK, VIO_D14_MARK, VIO_D15_MARK,
+};
+static const unsigned int ceu_clk_0_pins[] = {
+        /* CKO */
+        120,
+};
+static const unsigned int ceu_clk_0_mux[] = {
+        VIO_CKO_MARK,
+};
+static const unsigned int ceu_clk_1_pins[] = {
+        /* CKO */
+        16,
+};
+static const unsigned int ceu_clk_1_mux[] = {
+        VIO_CKO1_MARK,
+};
+static const unsigned int ceu_clk_2_pins[] = {
+        /* CKO */
+        17,
+};
+static const unsigned int ceu_clk_2_mux[] = {
+        VIO_CKO2_MARK,
+};
+static const unsigned int ceu_sync_pins[] = {
+        /* CLK, VD, HD */
+        118, 100, 101,
+};
+static const unsigned int ceu_sync_mux[] = {
+        VIO_CLK_MARK, VIO_VD_MARK, VIO_HD_MARK,
+};
+static const unsigned int ceu_field_pins[] = {
+        /* FIELD */
+        119,
+};
+static const unsigned int ceu_field_mux[] = {
+        VIO_FIELD_MARK,
+};
+/* - FLCTL ------------------------------------------------------------------ */
+static const unsigned int flctl_data_pins[] = {
+        /* NAF[0:15] */
+        46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61,
+};
+static const unsigned int flctl_data_mux[] = {
+        D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
+        D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
+        D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
+        D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
+};
+static const unsigned int flctl_ce0_pins[] = {
+        /* CE */
+        68,
+};
+static const unsigned int flctl_ce0_mux[] = {
+        FCE0_MARK,
+};
+static const unsigned int flctl_ce1_pins[] = {
+        /* CE */
+        66,
+};
+static const unsigned int flctl_ce1_mux[] = {
+        FCE1_MARK,
+};
+static const unsigned int flctl_ctrl_pins[] = {
+        /* FCDE, FOE, FSC, FWE, FRB */
+        24, 23, 69, 70, 73,
+};
+static const unsigned int flctl_ctrl_mux[] = {
+        A5_FCDE_MARK, A4_FOE_MARK, RD_FSC_MARK, WE0_FWE_MARK, FRB_MARK,
+};
+/* - FSIA ------------------------------------------------------------------- */
+static const unsigned int fsia_mclk_in_pins[] = {
+        /* CK */
+        4,
+};
+static const unsigned int fsia_mclk_in_mux[] = {
+        FSIACK_MARK,
+};
+static const unsigned int fsia_mclk_out_pins[] = {
+        /* OMC */
+        8,
+};
+static const unsigned int fsia_mclk_out_mux[] = {
+        FSIAOMC_MARK,
+};
+static const unsigned int fsia_sclk_in_pins[] = {
+        /* ILR, IBT */
+        5, 6,
+};
+static const unsigned int fsia_sclk_in_mux[] = {
+        FSIAILR_MARK, FSIAIBT_MARK,
+};
+static const unsigned int fsia_sclk_out_pins[] = {
+        /* OLR, OBT */
+        9, 10,
+};
+static const unsigned int fsia_sclk_out_mux[] = {
+        FSIAOLR_MARK, FSIAOBT_MARK,
+};
+static const unsigned int fsia_data_in_pins[] = {
+        /* ISLD */
+        7,
+};
+static const unsigned int fsia_data_in_mux[] = {
+        FSIAISLD_MARK,
+};
+static const unsigned int fsia_data_out_pins[] = {
+        /* OSLD */
+        11,
+};
+static const unsigned int fsia_data_out_mux[] = {
+        FSIAOSLD_MARK,
+};
+static const unsigned int fsia_spdif_0_pins[] = {
+        /* SPDIF */
+        11,
+};
+static const unsigned int fsia_spdif_0_mux[] = {
+        FSIASPDIF_11_MARK,
+};
+static const unsigned int fsia_spdif_1_pins[] = {
+        /* SPDIF */
+        15,
+};
+static const unsigned int fsia_spdif_1_mux[] = {
+        FSIASPDIF_15_MARK,
+};
+/* - FSIB ------------------------------------------------------------------- */
+static const unsigned int fsib_mclk_in_pins[] = {
+        /* CK */
+        4,
+};
+static const unsigned int fsib_mclk_in_mux[] = {
+        FSIBCK_MARK,
+};
+/* - HDMI ------------------------------------------------------------------- */
+static const unsigned int hdmi_pins[] = {
+        /* HPD, CEC */
+        169, 170,
+};
+static const unsigned int hdmi_mux[] = {
+        HDMI_HPD_MARK, HDMI_CEC_MARK,
+};
+/* - INTC ------------------------------------------------------------------- */
+IRQC_PINS_MUX(0, 6, 162);
+IRQC_PIN_MUX(1, 12);
+IRQC_PINS_MUX(2, 4, 5);
+IRQC_PINS_MUX(3, 8, 16);
+IRQC_PINS_MUX(4, 17, 163);
+IRQC_PIN_MUX(5, 18);
+IRQC_PINS_MUX(6, 39, 164);
+IRQC_PINS_MUX(7, 40, 167);
+IRQC_PINS_MUX(8, 41, 168);
+IRQC_PINS_MUX(9, 42, 169);
+IRQC_PIN_MUX(10, 65);
+IRQC_PIN_MUX(11, 67);
+IRQC_PINS_MUX(12, 80, 137);
+IRQC_PINS_MUX(13, 81, 145);
+IRQC_PINS_MUX(14, 82, 146);
+IRQC_PINS_MUX(15, 83, 147);
+IRQC_PINS_MUX(16, 84, 170);
+IRQC_PIN_MUX(17, 85);
+IRQC_PIN_MUX(18, 86);
+IRQC_PIN_MUX(19, 87);
+IRQC_PIN_MUX(20, 92);
+IRQC_PIN_MUX(21, 93);
+IRQC_PIN_MUX(22, 94);
+IRQC_PIN_MUX(23, 95);
+IRQC_PIN_MUX(24, 112);
+IRQC_PIN_MUX(25, 119);
+IRQC_PINS_MUX(26, 121, 172);
+IRQC_PINS_MUX(27, 122, 180);
+IRQC_PINS_MUX(28, 123, 181);
+IRQC_PINS_MUX(29, 129, 182);
+IRQC_PINS_MUX(30, 130, 183);
+IRQC_PINS_MUX(31, 138, 184);
+/* - KEYSC ------------------------------------------------------------------ */
+static const unsigned int keysc_in04_0_pins[] = {
+        /* KEYIN[0:4] */
+        136, 135, 134, 133, 132,
+};
+static const unsigned int keysc_in04_0_mux[] = {
+        KEYIN0_136_MARK, KEYIN1_135_MARK, KEYIN2_134_MARK, KEYIN3_133_MARK,
+        KEYIN4_MARK,
+};
+static const unsigned int keysc_in04_1_pins[] = {
+        /* KEYIN[0:4] */
+        121, 122, 123, 124, 132,
+};
+static const unsigned int keysc_in04_1_mux[] = {
+        KEYIN0_121_MARK, KEYIN1_122_MARK, KEYIN2_123_MARK, KEYIN3_124_MARK,
+        KEYIN4_MARK,
+};
+static const unsigned int keysc_in5_pins[] = {
+        /* KEYIN5 */
+        131,
+};
+static const unsigned int keysc_in5_mux[] = {
+        KEYIN5_MARK,
+};
+static const unsigned int keysc_in6_pins[] = {
+        /* KEYIN6 */
+        130,
+};
+static const unsigned int keysc_in6_mux[] = {
+        KEYIN6_MARK,
+};
+static const unsigned int keysc_in7_pins[] = {
+        /* KEYIN7 */
+        129,
+};
+static const unsigned int keysc_in7_mux[] = {
+        KEYIN7_MARK,
+};
+static const unsigned int keysc_out4_pins[] = {
+        /* KEYOUT[0:3] */
+        128, 127, 126, 125,
+};
+static const unsigned int keysc_out4_mux[] = {
+        KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
+};
+static const unsigned int keysc_out5_pins[] = {
+        /* KEYOUT[0:4] */
+        128, 127, 126, 125, 124,
+};
+static const unsigned int keysc_out5_mux[] = {
+        KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
+        KEYOUT4_MARK,
+};
+static const unsigned int keysc_out6_pins[] = {
+        /* KEYOUT[0:5] */
+        128, 127, 126, 125, 124, 123,
+};
+static const unsigned int keysc_out6_mux[] = {
+        KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
+        KEYOUT4_MARK, KEYOUT5_MARK,
+};
+static const unsigned int keysc_out8_pins[] = {
+        /* KEYOUT[0:7] */
+        128, 127, 126, 125, 124, 123, 122, 121,
+};
+static const unsigned int keysc_out8_mux[] = {
+        KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
+        KEYOUT4_MARK, KEYOUT5_MARK, KEYOUT6_MARK, KEYOUT7_MARK,
+};
+/* - LCD -------------------------------------------------------------------- */
+static const unsigned int lcd_data8_pins[] = {
+        /* D[0:7] */
+        121, 122, 123, 124, 125, 126, 127, 128,
+};
+static const unsigned int lcd_data8_mux[] = {
+        /* LCDC */
+        LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
+        LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
+};
+static const unsigned int lcd_data9_pins[] = {
+        /* D[0:8] */
+        121, 122, 123, 124, 125, 126, 127, 128,
+        129,
+        137, 138, 139, 140, 141, 142, 143, 144,
+};
+static const unsigned int lcd_data9_mux[] = {
+        LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
+        LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
+        LCDD8_MARK,
+};
+static const unsigned int lcd_data12_pins[] = {
+        /* D[0:11] */
+        121, 122, 123, 124, 125, 126, 127, 128,
+        129, 130, 131, 132,
+};
+static const unsigned int lcd_data12_mux[] = {
+        LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
+        LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
+        LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
+};
+static const unsigned int lcd_data16_pins[] = {
+        /* D[0:15] */
+        121, 122, 123, 124, 125, 126, 127, 128,
+        129, 130, 131, 132, 133, 134, 135, 136,
+};
+static const unsigned int lcd_data16_mux[] = {
+        LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
+        LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
+        LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
+        LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
+};
+static const unsigned int lcd_data18_pins[] = {
+        /* D[0:17] */
+        121, 122, 123, 124, 125, 126, 127, 128,
+        129, 130, 131, 132, 133, 134, 135, 136,
+        137, 138,
+};
+static const unsigned int lcd_data18_mux[] = {
+        LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
+        LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
+        LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
+        LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
+        LCDD16_MARK, LCDD17_MARK,
+};
+static const unsigned int lcd_data24_pins[] = {
+        /* D[0:23] */
+        121, 122, 123, 124, 125, 126, 127, 128,
+        129, 130, 131, 132, 133, 134, 135, 136,
+        137, 138, 139, 140, 141, 142, 143, 144,
+};
+static const unsigned int lcd_data24_mux[] = {
+        LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
+        LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
+        LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
+        LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
+        LCDD16_MARK, LCDD17_MARK, LCDD18_MARK, LCDD19_MARK,
+        LCDD20_MARK, LCDD21_MARK, LCDD22_MARK, LCDD23_MARK,
+};
+static const unsigned int lcd_display_pins[] = {
+        /* DON */
+        151,
+};
+static const unsigned int lcd_display_mux[] = {
+        LCDDON_MARK,
+};
+static const unsigned int lcd_lclk_pins[] = {
+        /* LCLK */
+        150,
+};
+static const unsigned int lcd_lclk_mux[] = {
+        LCDLCLK_MARK,
+};
+static const unsigned int lcd_sync_pins[] = {
+        /* VSYN, HSYN, DCK, DISP */
+        146, 145, 147, 149,
+};
+static const unsigned int lcd_sync_mux[] = {
+        LCDVSYN_MARK, LCDHSYN_MARK, LCDDCK_MARK, LCDDISP_MARK,
+};
+static const unsigned int lcd_sys_pins[] = {
+        /* CS, WR, RD, RS */
+        145, 147, 148, 149,
+};
+static const unsigned int lcd_sys_mux[] = {
+        LCDCS_MARK, LCDWR_MARK, LCDRD_MARK, LCDRS_MARK,
+};
 /* - MMCIF ------------------------------------------------------------------ */
 static const unsigned int mmc0_data1_0_pins[] = {
         /* D[0] */
@@ -993,6 +1475,139 @@ static const unsigned int mmc0_ctrl_1_pins[] = {
 static const unsigned int mmc0_ctrl_1_mux[] = {
         MMCCMD1_MARK, MMCCLK1_MARK,
 };
+/* - SCIFA0 ----------------------------------------------------------------- */
+static const unsigned int scifa0_data_pins[] = {
+        /* RXD, TXD */
+        153, 152,
+};
+static const unsigned int scifa0_data_mux[] = {
+        SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
+};
+static const unsigned int scifa0_clk_pins[] = {
+        /* SCK */
+        156,
+};
+static const unsigned int scifa0_clk_mux[] = {
+        SCIFA0_SCK_MARK,
+};
+static const unsigned int scifa0_ctrl_pins[] = {
+        /* RTS, CTS */
+        157, 158,
+};
+static const unsigned int scifa0_ctrl_mux[] = {
+        SCIFA0_RTS_MARK, SCIFA0_CTS_MARK,
+};
+/* - SCIFA1 ----------------------------------------------------------------- */
+static const unsigned int scifa1_data_pins[] = {
+        /* RXD, TXD */
+        155, 154,
+};
+static const unsigned int scifa1_data_mux[] = {
+        SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
+};
+static const unsigned int scifa1_clk_pins[] = {
+        /* SCK */
+        159,
+};
+static const unsigned int scifa1_clk_mux[] = {
+        SCIFA1_SCK_MARK,
+};
+static const unsigned int scifa1_ctrl_pins[] = {
+        /* RTS, CTS */
+        160, 161,
+};
+static const unsigned int scifa1_ctrl_mux[] = {
+        SCIFA1_RTS_MARK, SCIFA1_CTS_MARK,
+};
+/* - SCIFA2 ----------------------------------------------------------------- */
+static const unsigned int scifa2_data_pins[] = {
+        /* RXD, TXD */
+        97, 96,
+};
+static const unsigned int scifa2_data_mux[] = {
+        SCIFA2_RXD1_MARK, SCIFA2_TXD1_MARK,
+};
+static const unsigned int scifa2_clk_pins[] = {
+        /* SCK */
+        98,
+};
+static const unsigned int scifa2_clk_mux[] = {
+        SCIFA2_SCK1_MARK,
+};
+static const unsigned int scifa2_ctrl_pins[] = {
+        /* RTS, CTS */
+        95, 94,
+};
+static const unsigned int scifa2_ctrl_mux[] = {
+        SCIFA2_RTS1_MARK, SCIFA2_CTS1_MARK,
+};
+/* - SCIFA3 ----------------------------------------------------------------- */
+static const unsigned int scifa3_data_pins[] = {
+        /* RXD, TXD */
+        144, 143,
+};
+static const unsigned int scifa3_data_mux[] = {
+        SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
+};
+static const unsigned int scifa3_clk_pins[] = {
+        /* SCK */
+        142,
+};
+static const unsigned int scifa3_clk_mux[] = {
+        SCIFA3_SCK_MARK,
+};
+static const unsigned int scifa3_ctrl_0_pins[] = {
+        /* RTS, CTS */
+        44, 43,
+};
+static const unsigned int scifa3_ctrl_0_mux[] = {
+        SCIFA3_RTS_44_MARK, SCIFA3_CTS_43_MARK,
+};
+static const unsigned int scifa3_ctrl_1_pins[] = {
+        /* RTS, CTS */
+        141, 140,
+};
+static const unsigned int scifa3_ctrl_1_mux[] = {
+        SCIFA3_RTS_141_MARK, SCIFA3_CTS_140_MARK,
+};
+/* - SCIFA4 ----------------------------------------------------------------- */
+static const unsigned int scifa4_data_pins[] = {
+        /* RXD, TXD */
+        5, 6,
+};
+static const unsigned int scifa4_data_mux[] = {
+        SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
+};
+/* - SCIFA5 ----------------------------------------------------------------- */
+static const unsigned int scifa5_data_pins[] = {
+        /* RXD, TXD */
+        8, 12,
+};
+static const unsigned int scifa5_data_mux[] = {
+        SCIFA5_RXD_MARK, SCIFA5_TXD_MARK,
+};
+/* - SCIFB ------------------------------------------------------------------ */
+static const unsigned int scifb_data_pins[] = {
+        /* RXD, TXD */
+        166, 165,
+};
+static const unsigned int scifb_data_mux[] = {
+        SCIFB_RXD_MARK, SCIFB_TXD_MARK,
+};
+static const unsigned int scifb_clk_pins[] = {
+        /* SCK */
+        162,
+};
+static const unsigned int scifb_clk_mux[] = {
+        SCIFB_SCK_MARK,
+};
+static const unsigned int scifb_ctrl_pins[] = {
+        /* RTS, CTS */
+        163, 164,
+};
+static const unsigned int scifb_ctrl_mux[] = {
+        SCIFB_RTS_MARK, SCIFB_CTS_MARK,
+};
 /* - SDHI0 ------------------------------------------------------------------ */
 static const unsigned int sdhi0_data1_pins[] = {
         /* D0 */
@@ -1073,8 +1688,169 @@ static const unsigned int sdhi2_ctrl_pins[] = {
 static const unsigned int sdhi2_ctrl_mux[] = {
         SDHICMD2_MARK, SDHICLK2_MARK,
 };
+/* - USB0 ------------------------------------------------------------------- */
+static const unsigned int usb0_vbus_pins[] = {
+        /* VBUS */
+        167,
+};
+static const unsigned int usb0_vbus_mux[] = {
+        VBUS0_0_MARK,
+};
+static const unsigned int usb0_otg_id_pins[] = {
+        /* IDIN */
+        113,
+};
+static const unsigned int usb0_otg_id_mux[] = {
+        IDIN_0_MARK,
+};
+static const unsigned int usb0_otg_ctrl_pins[] = {
+        /* PWEN, EXTLP, OVCN, OVCN2 */
+        116, 114, 117, 115,
+};
+static const unsigned int usb0_otg_ctrl_mux[] = {
+        PWEN_0_MARK, EXTLP_0_MARK, OVCN_0_MARK, OVCN2_0_MARK,
+};
+/* - USB1 ------------------------------------------------------------------- */
+static const unsigned int usb1_vbus_pins[] = {
+        /* VBUS */
+        168,
+};
+static const unsigned int usb1_vbus_mux[] = {
+        VBUS0_1_MARK,
+};
+static const unsigned int usb1_otg_id_0_pins[] = {
+        /* IDIN */
+        113,
+};
+static const unsigned int usb1_otg_id_0_mux[] = {
+        IDIN_1_113_MARK,
+};
+static const unsigned int usb1_otg_id_1_pins[] = {
+        /* IDIN */
+        18,
+};
+static const unsigned int usb1_otg_id_1_mux[] = {
+        IDIN_1_18_MARK,
+};
+static const unsigned int usb1_otg_ctrl_0_pins[] = {
+        /* PWEN, EXTLP, OVCN, OVCN2 */
+        115, 116, 114, 117, 113,
+};
+static const unsigned int usb1_otg_ctrl_0_mux[] = {
+        PWEN_1_115_MARK, EXTLP_1_MARK, OVCN_1_114_MARK, OVCN2_1_MARK,
+};
+static const unsigned int usb1_otg_ctrl_1_pins[] = {
+        /* PWEN, EXTLP, OVCN, OVCN2 */
+        138, 116, 162, 117, 18,
+};
+static const unsigned int usb1_otg_ctrl_1_mux[] = {
+        PWEN_1_138_MARK, EXTLP_1_MARK, OVCN_1_162_MARK, OVCN2_1_MARK,
+};
 
 static const struct sh_pfc_pin_group pinmux_groups[] = {
+        SH_PFC_PIN_GROUP(bsc_data8),
+        SH_PFC_PIN_GROUP(bsc_data16),
+        SH_PFC_PIN_GROUP(bsc_cs0),
+        SH_PFC_PIN_GROUP(bsc_cs2),
+        SH_PFC_PIN_GROUP(bsc_cs4),
+        SH_PFC_PIN_GROUP(bsc_cs5a),
+        SH_PFC_PIN_GROUP(bsc_cs5b),
+        SH_PFC_PIN_GROUP(bsc_cs6a),
+        SH_PFC_PIN_GROUP(bsc_rd_we8),
+        SH_PFC_PIN_GROUP(bsc_rd_we16),
+        SH_PFC_PIN_GROUP(bsc_bs),
+        SH_PFC_PIN_GROUP(bsc_rdwr),
+        SH_PFC_PIN_GROUP(ceu_data_0_7),
+        SH_PFC_PIN_GROUP(ceu_data_8_15),
+        SH_PFC_PIN_GROUP(ceu_clk_0),
+        SH_PFC_PIN_GROUP(ceu_clk_1),
+        SH_PFC_PIN_GROUP(ceu_clk_2),
+        SH_PFC_PIN_GROUP(ceu_sync),
+        SH_PFC_PIN_GROUP(ceu_field),
+        SH_PFC_PIN_GROUP(flctl_data),
+        SH_PFC_PIN_GROUP(flctl_ce0),
+        SH_PFC_PIN_GROUP(flctl_ce1),
+        SH_PFC_PIN_GROUP(flctl_ctrl),
+        SH_PFC_PIN_GROUP(fsia_mclk_in),
+        SH_PFC_PIN_GROUP(fsia_mclk_out),
+        SH_PFC_PIN_GROUP(fsia_sclk_in),
+        SH_PFC_PIN_GROUP(fsia_sclk_out),
+        SH_PFC_PIN_GROUP(fsia_data_in),
+        SH_PFC_PIN_GROUP(fsia_data_out),
+        SH_PFC_PIN_GROUP(fsia_spdif_0),
+        SH_PFC_PIN_GROUP(fsia_spdif_1),
+        SH_PFC_PIN_GROUP(fsib_mclk_in),
+        SH_PFC_PIN_GROUP(hdmi),
+        SH_PFC_PIN_GROUP(intc_irq0_0),
+        SH_PFC_PIN_GROUP(intc_irq0_1),
+        SH_PFC_PIN_GROUP(intc_irq1),
+        SH_PFC_PIN_GROUP(intc_irq2_0),
+        SH_PFC_PIN_GROUP(intc_irq2_1),
+        SH_PFC_PIN_GROUP(intc_irq3_0),
+        SH_PFC_PIN_GROUP(intc_irq3_1),
+        SH_PFC_PIN_GROUP(intc_irq4_0),
+        SH_PFC_PIN_GROUP(intc_irq4_1),
+        SH_PFC_PIN_GROUP(intc_irq5),
+        SH_PFC_PIN_GROUP(intc_irq6_0),
+        SH_PFC_PIN_GROUP(intc_irq6_1),
+        SH_PFC_PIN_GROUP(intc_irq7_0),
+        SH_PFC_PIN_GROUP(intc_irq7_1),
+        SH_PFC_PIN_GROUP(intc_irq8_0),
+        SH_PFC_PIN_GROUP(intc_irq8_1),
+        SH_PFC_PIN_GROUP(intc_irq9_0),
+        SH_PFC_PIN_GROUP(intc_irq9_1),
+        SH_PFC_PIN_GROUP(intc_irq10),
+        SH_PFC_PIN_GROUP(intc_irq11),
+        SH_PFC_PIN_GROUP(intc_irq12_0),
+        SH_PFC_PIN_GROUP(intc_irq12_1),
+        SH_PFC_PIN_GROUP(intc_irq13_0),
+        SH_PFC_PIN_GROUP(intc_irq13_1),
+        SH_PFC_PIN_GROUP(intc_irq14_0),
+        SH_PFC_PIN_GROUP(intc_irq14_1),
+        SH_PFC_PIN_GROUP(intc_irq15_0),
+        SH_PFC_PIN_GROUP(intc_irq15_1),
+        SH_PFC_PIN_GROUP(intc_irq16_0),
+        SH_PFC_PIN_GROUP(intc_irq16_1),
+        SH_PFC_PIN_GROUP(intc_irq17),
+        SH_PFC_PIN_GROUP(intc_irq18),
+        SH_PFC_PIN_GROUP(intc_irq19),
+        SH_PFC_PIN_GROUP(intc_irq20),
+        SH_PFC_PIN_GROUP(intc_irq21),
+        SH_PFC_PIN_GROUP(intc_irq22),
+        SH_PFC_PIN_GROUP(intc_irq23),
+        SH_PFC_PIN_GROUP(intc_irq24),
+        SH_PFC_PIN_GROUP(intc_irq25),
+        SH_PFC_PIN_GROUP(intc_irq26_0),
+        SH_PFC_PIN_GROUP(intc_irq26_1),
+        SH_PFC_PIN_GROUP(intc_irq27_0),
+        SH_PFC_PIN_GROUP(intc_irq27_1),
+        SH_PFC_PIN_GROUP(intc_irq28_0),
+        SH_PFC_PIN_GROUP(intc_irq28_1),
+        SH_PFC_PIN_GROUP(intc_irq29_0),
+        SH_PFC_PIN_GROUP(intc_irq29_1),
+        SH_PFC_PIN_GROUP(intc_irq30_0),
+        SH_PFC_PIN_GROUP(intc_irq30_1),
+        SH_PFC_PIN_GROUP(intc_irq31_0),
+        SH_PFC_PIN_GROUP(intc_irq31_1),
+        SH_PFC_PIN_GROUP(keysc_in04_0),
+        SH_PFC_PIN_GROUP(keysc_in04_1),
+        SH_PFC_PIN_GROUP(keysc_in5),
+        SH_PFC_PIN_GROUP(keysc_in6),
+        SH_PFC_PIN_GROUP(keysc_in7),
+        SH_PFC_PIN_GROUP(keysc_out4),
+        SH_PFC_PIN_GROUP(keysc_out5),
+        SH_PFC_PIN_GROUP(keysc_out6),
+        SH_PFC_PIN_GROUP(keysc_out8),
+        SH_PFC_PIN_GROUP(lcd_data8),
+        SH_PFC_PIN_GROUP(lcd_data9),
+        SH_PFC_PIN_GROUP(lcd_data12),
+        SH_PFC_PIN_GROUP(lcd_data16),
+        SH_PFC_PIN_GROUP(lcd_data18),
+        SH_PFC_PIN_GROUP(lcd_data24),
+        SH_PFC_PIN_GROUP(lcd_display),
+        SH_PFC_PIN_GROUP(lcd_lclk),
+        SH_PFC_PIN_GROUP(lcd_sync),
+        SH_PFC_PIN_GROUP(lcd_sys),
         SH_PFC_PIN_GROUP(mmc0_data1_0),
         SH_PFC_PIN_GROUP(mmc0_data4_0),
         SH_PFC_PIN_GROUP(mmc0_data8_0),
@@ -1083,6 +1859,24 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
         SH_PFC_PIN_GROUP(mmc0_data4_1),
         SH_PFC_PIN_GROUP(mmc0_data8_1),
         SH_PFC_PIN_GROUP(mmc0_ctrl_1),
+        SH_PFC_PIN_GROUP(scifa0_data),
+        SH_PFC_PIN_GROUP(scifa0_clk),
+        SH_PFC_PIN_GROUP(scifa0_ctrl),
+        SH_PFC_PIN_GROUP(scifa1_data),
+        SH_PFC_PIN_GROUP(scifa1_clk),
+        SH_PFC_PIN_GROUP(scifa1_ctrl),
+        SH_PFC_PIN_GROUP(scifa2_data),
+        SH_PFC_PIN_GROUP(scifa2_clk),
+        SH_PFC_PIN_GROUP(scifa2_ctrl),
+        SH_PFC_PIN_GROUP(scifa3_data),
+        SH_PFC_PIN_GROUP(scifa3_clk),
+        SH_PFC_PIN_GROUP(scifa3_ctrl_0),
+        SH_PFC_PIN_GROUP(scifa3_ctrl_1),
+        SH_PFC_PIN_GROUP(scifa4_data),
+        SH_PFC_PIN_GROUP(scifa5_data),
+        SH_PFC_PIN_GROUP(scifb_data),
+        SH_PFC_PIN_GROUP(scifb_clk),
+        SH_PFC_PIN_GROUP(scifb_ctrl),
         SH_PFC_PIN_GROUP(sdhi0_data1),
         SH_PFC_PIN_GROUP(sdhi0_data4),
         SH_PFC_PIN_GROUP(sdhi0_ctrl),
@@ -1094,6 +1888,144 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
         SH_PFC_PIN_GROUP(sdhi2_data1),
         SH_PFC_PIN_GROUP(sdhi2_data4),
         SH_PFC_PIN_GROUP(sdhi2_ctrl),
+        SH_PFC_PIN_GROUP(usb0_vbus),
+        SH_PFC_PIN_GROUP(usb0_otg_id),
+        SH_PFC_PIN_GROUP(usb0_otg_ctrl),
+        SH_PFC_PIN_GROUP(usb1_vbus),
+        SH_PFC_PIN_GROUP(usb1_otg_id_0),
+        SH_PFC_PIN_GROUP(usb1_otg_id_1),
+        SH_PFC_PIN_GROUP(usb1_otg_ctrl_0),
+        SH_PFC_PIN_GROUP(usb1_otg_ctrl_1),
+};
+
+static const char * const bsc_groups[] = {
+        "bsc_data8",
+        "bsc_data16",
+        "bsc_cs0",
+        "bsc_cs2",
+        "bsc_cs4",
+        "bsc_cs5a",
+        "bsc_cs5b",
+        "bsc_cs6a",
+        "bsc_rd_we8",
+        "bsc_rd_we16",
+        "bsc_bs",
+        "bsc_rdwr",
+};
+
+static const char * const ceu_groups[] = {
+        "ceu_data_0_7",
+        "ceu_data_8_15",
+        "ceu_clk_0",
+        "ceu_clk_1",
+        "ceu_clk_2",
+        "ceu_sync",
+        "ceu_field",
+};
+
+static const char * const flctl_groups[] = {
+        "flctl_data",
+        "flctl_ce0",
+        "flctl_ce1",
+        "flctl_ctrl",
+};
+
+static const char * const fsia_groups[] = {
+        "fsia_mclk_in",
+        "fsia_mclk_out",
+        "fsia_sclk_in",
+        "fsia_sclk_out",
+        "fsia_data_in",
+        "fsia_data_out",
+        "fsia_spdif_0",
+        "fsia_spdif_1",
+};
+
+static const char * const fsib_groups[] = {
+        "fsib_mclk_in",
+};
+
+static const char * const hdmi_groups[] = {
+        "hdmi",
+};
+
+static const char * const intc_groups[] = {
+        "intc_irq0_0",
+        "intc_irq0_1",
+        "intc_irq1",
+        "intc_irq2_0",
+        "intc_irq2_1",
+        "intc_irq3_0",
+        "intc_irq3_1",
+        "intc_irq4_0",
+        "intc_irq4_1",
+        "intc_irq5",
+        "intc_irq6_0",
+        "intc_irq6_1",
+        "intc_irq7_0",
+        "intc_irq7_1",
+        "intc_irq8_0",
+        "intc_irq8_1",
+        "intc_irq9_0",
+        "intc_irq9_1",
+        "intc_irq10",
+        "intc_irq11",
+        "intc_irq12_0",
+        "intc_irq12_1",
+        "intc_irq13_0",
+        "intc_irq13_1",
+        "intc_irq14_0",
+        "intc_irq14_1",
+        "intc_irq15_0",
+        "intc_irq15_1",
+        "intc_irq16_0",
+        "intc_irq16_1",
+        "intc_irq17",
+        "intc_irq18",
+        "intc_irq19",
+        "intc_irq20",
+        "intc_irq21",
+        "intc_irq22",
+        "intc_irq23",
+        "intc_irq24",
+        "intc_irq25",
+        "intc_irq26_0",
+        "intc_irq26_1",
+        "intc_irq27_0",
+        "intc_irq27_1",
+        "intc_irq28_0",
+        "intc_irq28_1",
+        "intc_irq29_0",
+        "intc_irq29_1",
+        "intc_irq30_0",
+        "intc_irq30_1",
+        "intc_irq31_0",
+        "intc_irq31_1",
+};
+
+static const char * const keysc_groups[] = {
+        "keysc_in04_0",
+        "keysc_in04_1",
+        "keysc_in5",
+        "keysc_in6",
+        "keysc_in7",
+        "keysc_out4",
+        "keysc_out5",
+        "keysc_out6",
+        "keysc_out8",
+};
+
+static const char * const lcd_groups[] = {
+        "lcd_data8",
+        "lcd_data9",
+        "lcd_data12",
+        "lcd_data16",
+        "lcd_data18",
+        "lcd_data24",
+        "lcd_display",
+        "lcd_lclk",
+        "lcd_sync",
+        "lcd_sys",
 };
 
 static const char * const mmc0_groups[] = {
@@ -1107,6 +2039,45 @@ static const char * const mmc0_groups[] = {
         "mmc0_ctrl_1",
 };
 
+static const char * const scifa0_groups[] = {
+        "scifa0_data",
+        "scifa0_clk",
+        "scifa0_ctrl",
+};
+
+static const char * const scifa1_groups[] = {
+        "scifa1_data",
+        "scifa1_clk",
+        "scifa1_ctrl",
+};
+
+static const char * const scifa2_groups[] = {
+        "scifa2_data",
+        "scifa2_clk",
+        "scifa2_ctrl",
+};
+
+static const char * const scifa3_groups[] = {
+        "scifa3_data",
+        "scifa3_clk",
+        "scifa3_ctrl_0",
+        "scifa3_ctrl_1",
+};
+
+static const char * const scifa4_groups[] = {
+        "scifa4_data",
+};
+
+static const char * const scifa5_groups[] = {
+        "scifa5_data",
+};
+
+static const char * const scifb_groups[] = {
+        "scifb_data",
+        "scifb_clk",
+        "scifb_ctrl",
+};
+
 static const char * const sdhi0_groups[] = {
         "sdhi0_data1",
         "sdhi0_data4",
@@ -1127,256 +2098,55 @@ static const char * const sdhi2_groups[] = {
         "sdhi2_ctrl",
 };
 
+static const char * const usb0_groups[] = {
+        "usb0_vbus",
+        "usb0_otg_id",
+        "usb0_otg_ctrl",
+};
+
+static const char * const usb1_groups[] = {
+        "usb1_vbus",
+        "usb1_otg_id_0",
+        "usb1_otg_id_1",
+        "usb1_otg_ctrl_0",
+        "usb1_otg_ctrl_1",
+};
+
 static const struct sh_pfc_function pinmux_functions[] = {
+        SH_PFC_FUNCTION(bsc),
+        SH_PFC_FUNCTION(ceu),
+        SH_PFC_FUNCTION(flctl),
+        SH_PFC_FUNCTION(fsia),
+        SH_PFC_FUNCTION(fsib),
+        SH_PFC_FUNCTION(hdmi),
+        SH_PFC_FUNCTION(intc),
+        SH_PFC_FUNCTION(keysc),
+        SH_PFC_FUNCTION(lcd),
         SH_PFC_FUNCTION(mmc0),
+        SH_PFC_FUNCTION(scifa0),
+        SH_PFC_FUNCTION(scifa1),
+        SH_PFC_FUNCTION(scifa2),
+        SH_PFC_FUNCTION(scifa3),
+        SH_PFC_FUNCTION(scifa4),
+        SH_PFC_FUNCTION(scifa5),
+        SH_PFC_FUNCTION(scifb),
         SH_PFC_FUNCTION(sdhi0),
         SH_PFC_FUNCTION(sdhi1),
         SH_PFC_FUNCTION(sdhi2),
+        SH_PFC_FUNCTION(usb0),
+        SH_PFC_FUNCTION(usb1),
 };
 
-#define PINMUX_FN_BASE  ARRAY_SIZE(pinmux_pins)
-
-static const struct pinmux_func pinmux_func_gpios[] = {
-        /* IRQ */
-        GPIO_FN(IRQ0_6),        GPIO_FN(IRQ0_162),      GPIO_FN(IRQ1),
-        GPIO_FN(IRQ2_4),        GPIO_FN(IRQ2_5),        GPIO_FN(IRQ3_8),
-        GPIO_FN(IRQ3_16),       GPIO_FN(IRQ4_17),       GPIO_FN(IRQ4_163),
-        GPIO_FN(IRQ5),          GPIO_FN(IRQ6_39),       GPIO_FN(IRQ6_164),
-        GPIO_FN(IRQ7_40),       GPIO_FN(IRQ7_167),      GPIO_FN(IRQ8_41),
-        GPIO_FN(IRQ8_168),      GPIO_FN(IRQ9_42),       GPIO_FN(IRQ9_169),
-        GPIO_FN(IRQ10),         GPIO_FN(IRQ11),         GPIO_FN(IRQ12_80),
-        GPIO_FN(IRQ12_137),     GPIO_FN(IRQ13_81),      GPIO_FN(IRQ13_145),
-        GPIO_FN(IRQ14_82),      GPIO_FN(IRQ14_146),     GPIO_FN(IRQ15_83),
-        GPIO_FN(IRQ15_147),     GPIO_FN(IRQ16_84),      GPIO_FN(IRQ16_170),
-        GPIO_FN(IRQ17),         GPIO_FN(IRQ18),         GPIO_FN(IRQ19),
-        GPIO_FN(IRQ20),         GPIO_FN(IRQ21),         GPIO_FN(IRQ22),
-        GPIO_FN(IRQ23),         GPIO_FN(IRQ24),         GPIO_FN(IRQ25),
-        GPIO_FN(IRQ26_121),     GPIO_FN(IRQ26_172),     GPIO_FN(IRQ27_122),
-        GPIO_FN(IRQ27_180),     GPIO_FN(IRQ28_123),     GPIO_FN(IRQ28_181),
-        GPIO_FN(IRQ29_129),     GPIO_FN(IRQ29_182),     GPIO_FN(IRQ30_130),
-        GPIO_FN(IRQ30_183),     GPIO_FN(IRQ31_138),     GPIO_FN(IRQ31_184),
-
-        /* MSIOF0 */
-        GPIO_FN(MSIOF0_TSYNC),  GPIO_FN(MSIOF0_TSCK),   GPIO_FN(MSIOF0_RXD),
-        GPIO_FN(MSIOF0_RSCK),   GPIO_FN(MSIOF0_RSYNC),  GPIO_FN(MSIOF0_MCK0),
-        GPIO_FN(MSIOF0_MCK1),   GPIO_FN(MSIOF0_SS1),    GPIO_FN(MSIOF0_SS2),
-        GPIO_FN(MSIOF0_TXD),
-
-        /* MSIOF1 */
-        GPIO_FN(MSIOF1_TSCK_39),        GPIO_FN(MSIOF1_TSCK_88),
-        GPIO_FN(MSIOF1_TSYNC_40),       GPIO_FN(MSIOF1_TSYNC_89),
-        GPIO_FN(MSIOF1_TXD_41),         GPIO_FN(MSIOF1_TXD_90),
-        GPIO_FN(MSIOF1_RXD_42),         GPIO_FN(MSIOF1_RXD_91),
-        GPIO_FN(MSIOF1_SS1_43),         GPIO_FN(MSIOF1_SS1_92),
-        GPIO_FN(MSIOF1_SS2_44),         GPIO_FN(MSIOF1_SS2_93),
-        GPIO_FN(MSIOF1_RSCK),           GPIO_FN(MSIOF1_RSYNC),
-        GPIO_FN(MSIOF1_MCK0),           GPIO_FN(MSIOF1_MCK1),
-
-        /* MSIOF2 */
-        GPIO_FN(MSIOF2_RSCK),   GPIO_FN(MSIOF2_RSYNC),  GPIO_FN(MSIOF2_MCK0),
-        GPIO_FN(MSIOF2_MCK1),   GPIO_FN(MSIOF2_SS1),    GPIO_FN(MSIOF2_SS2),
-        GPIO_FN(MSIOF2_TSYNC),  GPIO_FN(MSIOF2_TSCK),   GPIO_FN(MSIOF2_RXD),
-        GPIO_FN(MSIOF2_TXD),
-
-        /* BBIF1 */
-        GPIO_FN(BBIF1_RXD),     GPIO_FN(BBIF1_TSYNC),   GPIO_FN(BBIF1_TSCK),
-        GPIO_FN(BBIF1_TXD),     GPIO_FN(BBIF1_RSCK),    GPIO_FN(BBIF1_RSYNC),
-        GPIO_FN(BBIF1_FLOW),    GPIO_FN(BB_RX_FLOW_N),
-
-        /* BBIF2 */
-        GPIO_FN(BBIF2_TSCK1),   GPIO_FN(BBIF2_TSYNC1),
-        GPIO_FN(BBIF2_TXD1),    GPIO_FN(BBIF2_RXD),
-
-        /* FSI */
-        GPIO_FN(FSIACK),        GPIO_FN(FSIBCK),        GPIO_FN(FSIAILR),
-        GPIO_FN(FSIAIBT),       GPIO_FN(FSIAISLD),      GPIO_FN(FSIAOMC),
-        GPIO_FN(FSIAOLR),       GPIO_FN(FSIAOBT),       GPIO_FN(FSIAOSLD),
-        GPIO_FN(FSIASPDIF_11),  GPIO_FN(FSIASPDIF_15),
-
-        /* FMSI */
-        GPIO_FN(FMSOCK),        GPIO_FN(FMSOOLR),       GPIO_FN(FMSIOLR),
-        GPIO_FN(FMSOOBT),       GPIO_FN(FMSIOBT),       GPIO_FN(FMSOSLD),
-        GPIO_FN(FMSOILR),       GPIO_FN(FMSIILR),       GPIO_FN(FMSOIBT),
-        GPIO_FN(FMSIIBT),       GPIO_FN(FMSISLD),       GPIO_FN(FMSICK),
-
-        /* SCIFA0 */
-        GPIO_FN(SCIFA0_TXD),    GPIO_FN(SCIFA0_RXD),    GPIO_FN(SCIFA0_SCK),
-        GPIO_FN(SCIFA0_RTS),    GPIO_FN(SCIFA0_CTS),
-
-        /* SCIFA1 */
-        GPIO_FN(SCIFA1_TXD),    GPIO_FN(SCIFA1_RXD),    GPIO_FN(SCIFA1_SCK),
-        GPIO_FN(SCIFA1_RTS),    GPIO_FN(SCIFA1_CTS),
-
-        /* SCIFA2 */
-        GPIO_FN(SCIFA2_CTS1),   GPIO_FN(SCIFA2_RTS1),   GPIO_FN(SCIFA2_TXD1),
-        GPIO_FN(SCIFA2_RXD1),   GPIO_FN(SCIFA2_SCK1),
-
-        /* SCIFA3 */
-        GPIO_FN(SCIFA3_CTS_43),         GPIO_FN(SCIFA3_CTS_140),
-        GPIO_FN(SCIFA3_RTS_44),         GPIO_FN(SCIFA3_RTS_141),
-        GPIO_FN(SCIFA3_SCK),            GPIO_FN(SCIFA3_TXD),
-        GPIO_FN(SCIFA3_RXD),
-
-        /* SCIFA4 */
-        GPIO_FN(SCIFA4_RXD),    GPIO_FN(SCIFA4_TXD),
-
-        /* SCIFA5 */
-        GPIO_FN(SCIFA5_RXD),    GPIO_FN(SCIFA5_TXD),
-
-        /* SCIFB */
-        GPIO_FN(SCIFB_SCK),     GPIO_FN(SCIFB_RTS),     GPIO_FN(SCIFB_CTS),
-        GPIO_FN(SCIFB_TXD),     GPIO_FN(SCIFB_RXD),
-
-        /* CEU */
-        GPIO_FN(VIO_HD),        GPIO_FN(VIO_CKO1),      GPIO_FN(VIO_CKO2),
-        GPIO_FN(VIO_VD),        GPIO_FN(VIO_CLK),       GPIO_FN(VIO_FIELD),
-        GPIO_FN(VIO_CKO),       GPIO_FN(VIO_D0),        GPIO_FN(VIO_D1),
-        GPIO_FN(VIO_D2),        GPIO_FN(VIO_D3),        GPIO_FN(VIO_D4),
-        GPIO_FN(VIO_D5),        GPIO_FN(VIO_D6),        GPIO_FN(VIO_D7),
-        GPIO_FN(VIO_D8),        GPIO_FN(VIO_D9),        GPIO_FN(VIO_D10),
-        GPIO_FN(VIO_D11),       GPIO_FN(VIO_D12),       GPIO_FN(VIO_D13),
-        GPIO_FN(VIO_D14),       GPIO_FN(VIO_D15),
-
-        /* USB0 */
-        GPIO_FN(IDIN_0),        GPIO_FN(EXTLP_0),       GPIO_FN(OVCN2_0),
-        GPIO_FN(PWEN_0),        GPIO_FN(OVCN_0),        GPIO_FN(VBUS0_0),
-
-        /* USB1 */
-        GPIO_FN(IDIN_1_18),     GPIO_FN(IDIN_1_113),
-        GPIO_FN(OVCN_1_114),    GPIO_FN(OVCN_1_162),
-        GPIO_FN(PWEN_1_115),    GPIO_FN(PWEN_1_138),
-        GPIO_FN(EXTLP_1),       GPIO_FN(OVCN2_1),
-        GPIO_FN(VBUS0_1),
-
-        /* GPIO */
-        GPIO_FN(GPI0),  GPIO_FN(GPI1),  GPIO_FN(GPO0),  GPIO_FN(GPO1),
-
-        /* BSC */
-        GPIO_FN(BS),    GPIO_FN(WE1),   GPIO_FN(CKO),
-        GPIO_FN(WAIT),  GPIO_FN(RDWR),
-
-        GPIO_FN(A0),    GPIO_FN(A1),    GPIO_FN(A2),
-        GPIO_FN(A3),    GPIO_FN(A6),    GPIO_FN(A7),
-        GPIO_FN(A8),    GPIO_FN(A9),    GPIO_FN(A10),
-        GPIO_FN(A11),   GPIO_FN(A12),   GPIO_FN(A13),
-        GPIO_FN(A14),   GPIO_FN(A15),   GPIO_FN(A16),
-        GPIO_FN(A17),   GPIO_FN(A18),   GPIO_FN(A19),
-        GPIO_FN(A20),   GPIO_FN(A21),   GPIO_FN(A22),
-        GPIO_FN(A23),   GPIO_FN(A24),   GPIO_FN(A25),
-        GPIO_FN(A26),
-
-        GPIO_FN(CS0),   GPIO_FN(CS2),   GPIO_FN(CS4),
-        GPIO_FN(CS5A),  GPIO_FN(CS5B),  GPIO_FN(CS6A),
-
-        /* BSC/FLCTL */
-        GPIO_FN(RD_FSC),        GPIO_FN(WE0_FWE),       GPIO_FN(A4_FOE),
-        GPIO_FN(A5_FCDE),       GPIO_FN(D0_NAF0),       GPIO_FN(D1_NAF1),
-        GPIO_FN(D2_NAF2),       GPIO_FN(D3_NAF3),       GPIO_FN(D4_NAF4),
-        GPIO_FN(D5_NAF5),       GPIO_FN(D6_NAF6),       GPIO_FN(D7_NAF7),
-        GPIO_FN(D8_NAF8),       GPIO_FN(D9_NAF9),       GPIO_FN(D10_NAF10),
-        GPIO_FN(D11_NAF11),     GPIO_FN(D12_NAF12),     GPIO_FN(D13_NAF13),
-        GPIO_FN(D14_NAF14),     GPIO_FN(D15_NAF15),
-
-        /* SPU2 */
-        GPIO_FN(VINT_I),
-
-        /* FLCTL */
-        GPIO_FN(FCE1),  GPIO_FN(FCE0),  GPIO_FN(FRB),
-
-        /* HSI */
-        GPIO_FN(GP_RX_FLAG),    GPIO_FN(GP_RX_DATA),    GPIO_FN(GP_TX_READY),
-        GPIO_FN(GP_RX_WAKE),    GPIO_FN(MP_TX_FLAG),    GPIO_FN(MP_TX_DATA),
-        GPIO_FN(MP_RX_READY),   GPIO_FN(MP_TX_WAKE),
-
-        /* MFI */
-        GPIO_FN(MFIv6),
-        GPIO_FN(MFIv4),
-
-        GPIO_FN(MEMC_BUSCLK_MEMC_A0),   GPIO_FN(MEMC_ADV_MEMC_DREQ0),
-        GPIO_FN(MEMC_WAIT_MEMC_DREQ1),  GPIO_FN(MEMC_CS1_MEMC_A1),
-        GPIO_FN(MEMC_CS0),      GPIO_FN(MEMC_NOE),
-        GPIO_FN(MEMC_NWE),      GPIO_FN(MEMC_INT),
-
-        GPIO_FN(MEMC_AD0),      GPIO_FN(MEMC_AD1),      GPIO_FN(MEMC_AD2),
-        GPIO_FN(MEMC_AD3),      GPIO_FN(MEMC_AD4),      GPIO_FN(MEMC_AD5),
-        GPIO_FN(MEMC_AD6),      GPIO_FN(MEMC_AD7),      GPIO_FN(MEMC_AD8),
-        GPIO_FN(MEMC_AD9),      GPIO_FN(MEMC_AD10),     GPIO_FN(MEMC_AD11),
-        GPIO_FN(MEMC_AD12),     GPIO_FN(MEMC_AD13),     GPIO_FN(MEMC_AD14),
-        GPIO_FN(MEMC_AD15),
-
-        /* SIM */
-        GPIO_FN(SIM_RST),       GPIO_FN(SIM_CLK),       GPIO_FN(SIM_D),
-
-        /* TPU */
-        GPIO_FN(TPU0TO0),       GPIO_FN(TPU0TO1),       GPIO_FN(TPU0TO2_93),
-        GPIO_FN(TPU0TO2_99),    GPIO_FN(TPU0TO3),
-
-        /* I2C2 */
-        GPIO_FN(I2C_SCL2),      GPIO_FN(I2C_SDA2),
-
-        /* I2C3(1) */
-        GPIO_FN(I2C_SCL3),      GPIO_FN(I2C_SDA3),
-
-        /* I2C3(2) */
-        GPIO_FN(I2C_SCL3S),     GPIO_FN(I2C_SDA3S),
-
-        /* I2C4(2) */
-        GPIO_FN(I2C_SCL4),      GPIO_FN(I2C_SDA4),
-
-        /* I2C4(2) */
-        GPIO_FN(I2C_SCL4S),     GPIO_FN(I2C_SDA4S),
-
-        /* KEYSC */
-        GPIO_FN(KEYOUT0),       GPIO_FN(KEYIN0_121),    GPIO_FN(KEYIN0_136),
-        GPIO_FN(KEYOUT1),       GPIO_FN(KEYIN1_122),    GPIO_FN(KEYIN1_135),
-        GPIO_FN(KEYOUT2),       GPIO_FN(KEYIN2_123),    GPIO_FN(KEYIN2_134),
-        GPIO_FN(KEYOUT3),       GPIO_FN(KEYIN3_124),    GPIO_FN(KEYIN3_133),
-        GPIO_FN(KEYOUT4),       GPIO_FN(KEYIN4),        GPIO_FN(KEYOUT5),
-        GPIO_FN(KEYIN5),        GPIO_FN(KEYOUT6),       GPIO_FN(KEYIN6),
-        GPIO_FN(KEYOUT7),       GPIO_FN(KEYIN7),
-
-        /* LCDC */
-        GPIO_FN(LCDHSYN),       GPIO_FN(LCDCS), GPIO_FN(LCDVSYN),
-        GPIO_FN(LCDDCK),        GPIO_FN(LCDWR), GPIO_FN(LCDRD),
-        GPIO_FN(LCDDISP),       GPIO_FN(LCDRS), GPIO_FN(LCDLCLK),
-        GPIO_FN(LCDDON),
-
-        GPIO_FN(LCDD0),         GPIO_FN(LCDD1),         GPIO_FN(LCDD2),
-        GPIO_FN(LCDD3),         GPIO_FN(LCDD4),         GPIO_FN(LCDD5),
-        GPIO_FN(LCDD6),         GPIO_FN(LCDD7),         GPIO_FN(LCDD8),
-        GPIO_FN(LCDD9),         GPIO_FN(LCDD10),        GPIO_FN(LCDD11),
-        GPIO_FN(LCDD12),        GPIO_FN(LCDD13),        GPIO_FN(LCDD14),
-        GPIO_FN(LCDD15),        GPIO_FN(LCDD16),        GPIO_FN(LCDD17),
-        GPIO_FN(LCDD18),        GPIO_FN(LCDD19),        GPIO_FN(LCDD20),
-        GPIO_FN(LCDD21),        GPIO_FN(LCDD22),        GPIO_FN(LCDD23),
-
-        GPIO_FN(LCDC0_SELECT),
-        GPIO_FN(LCDC1_SELECT),
-
-        /* IRDA */
-        GPIO_FN(IRDA_OUT),      GPIO_FN(IRDA_IN),       GPIO_FN(IRDA_FIRSEL),
-        GPIO_FN(IROUT_139),     GPIO_FN(IROUT_140),
-
-        /* TSIF1 */
-        GPIO_FN(TS0_1SELECT),
-        GPIO_FN(TS0_2SELECT),
-        GPIO_FN(TS1_1SELECT),
-        GPIO_FN(TS1_2SELECT),
-
-        GPIO_FN(TS_SPSYNC1),    GPIO_FN(TS_SDAT1),
-        GPIO_FN(TS_SDEN1),      GPIO_FN(TS_SCK1),
-
-        /* TSIF2 */
-        GPIO_FN(TS_SPSYNC2),    GPIO_FN(TS_SDAT2),
-        GPIO_FN(TS_SDEN2),      GPIO_FN(TS_SCK2),
-
-        /* HDMI */
-        GPIO_FN(HDMI_HPD),      GPIO_FN(HDMI_CEC),
-
-        /* SDENC */
-        GPIO_FN(SDENC_CPG),
-        GPIO_FN(SDENC_DV_CLKI),
-};
+#undef PORTCR
+#define PORTCR(nr, reg)                                                 \
+        {                                                               \
+                PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) {             \
+                        _PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT),     \
+                                PORT##nr##_FN0, PORT##nr##_FN1,         \
+                                PORT##nr##_FN2, PORT##nr##_FN3,         \
+                                PORT##nr##_FN4, PORT##nr##_FN5,         \
+                                PORT##nr##_FN6, PORT##nr##_FN7 }        \
+        }
 
 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
         PORTCR(0,       0xE6051000), /* PORT0CR */
@@ -1776,45 +2546,114 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
 #define EXT_IRQ16L(n) evt2irq(0x200 + ((n) << 5))
 #define EXT_IRQ16H(n) evt2irq(0x3200 + (((n) - 16) << 5))
 static const struct pinmux_irq pinmux_irqs[] = {
-        PINMUX_IRQ(EXT_IRQ16L(0), GPIO_PORT6, GPIO_PORT162),
-        PINMUX_IRQ(EXT_IRQ16L(1), GPIO_PORT12),
-        PINMUX_IRQ(EXT_IRQ16L(2), GPIO_PORT4, GPIO_PORT5),
-        PINMUX_IRQ(EXT_IRQ16L(3), GPIO_PORT8, GPIO_PORT16),
-        PINMUX_IRQ(EXT_IRQ16L(4), GPIO_PORT17, GPIO_PORT163),
-        PINMUX_IRQ(EXT_IRQ16L(5), GPIO_PORT18),
-        PINMUX_IRQ(EXT_IRQ16L(6), GPIO_PORT39, GPIO_PORT164),
-        PINMUX_IRQ(EXT_IRQ16L(7), GPIO_PORT40, GPIO_PORT167),
-        PINMUX_IRQ(EXT_IRQ16L(8), GPIO_PORT41, GPIO_PORT168),
-        PINMUX_IRQ(EXT_IRQ16L(9), GPIO_PORT42, GPIO_PORT169),
-        PINMUX_IRQ(EXT_IRQ16L(10), GPIO_PORT65),
-        PINMUX_IRQ(EXT_IRQ16L(11), GPIO_PORT67),
-        PINMUX_IRQ(EXT_IRQ16L(12), GPIO_PORT80, GPIO_PORT137),
-        PINMUX_IRQ(EXT_IRQ16L(13), GPIO_PORT81, GPIO_PORT145),
-        PINMUX_IRQ(EXT_IRQ16L(14), GPIO_PORT82, GPIO_PORT146),
-        PINMUX_IRQ(EXT_IRQ16L(15), GPIO_PORT83, GPIO_PORT147),
-        PINMUX_IRQ(EXT_IRQ16H(16), GPIO_PORT84, GPIO_PORT170),
-        PINMUX_IRQ(EXT_IRQ16H(17), GPIO_PORT85),
-        PINMUX_IRQ(EXT_IRQ16H(18), GPIO_PORT86),
-        PINMUX_IRQ(EXT_IRQ16H(19), GPIO_PORT87),
-        PINMUX_IRQ(EXT_IRQ16H(20), GPIO_PORT92),
-        PINMUX_IRQ(EXT_IRQ16H(21), GPIO_PORT93),
-        PINMUX_IRQ(EXT_IRQ16H(22), GPIO_PORT94),
-        PINMUX_IRQ(EXT_IRQ16H(23), GPIO_PORT95),
-        PINMUX_IRQ(EXT_IRQ16H(24), GPIO_PORT112),
-        PINMUX_IRQ(EXT_IRQ16H(25), GPIO_PORT119),
-        PINMUX_IRQ(EXT_IRQ16H(26), GPIO_PORT121, GPIO_PORT172),
-        PINMUX_IRQ(EXT_IRQ16H(27), GPIO_PORT122, GPIO_PORT180),
-        PINMUX_IRQ(EXT_IRQ16H(28), GPIO_PORT123, GPIO_PORT181),
-        PINMUX_IRQ(EXT_IRQ16H(29), GPIO_PORT129, GPIO_PORT182),
-        PINMUX_IRQ(EXT_IRQ16H(30), GPIO_PORT130, GPIO_PORT183),
-        PINMUX_IRQ(EXT_IRQ16H(31), GPIO_PORT138, GPIO_PORT184),
+        PINMUX_IRQ(EXT_IRQ16L(0), 6, 162),
+        PINMUX_IRQ(EXT_IRQ16L(1), 12),
+        PINMUX_IRQ(EXT_IRQ16L(2), 4, 5),
+        PINMUX_IRQ(EXT_IRQ16L(3), 8, 16),
+        PINMUX_IRQ(EXT_IRQ16L(4), 17, 163),
+        PINMUX_IRQ(EXT_IRQ16L(5), 18),
+        PINMUX_IRQ(EXT_IRQ16L(6), 39, 164),
+        PINMUX_IRQ(EXT_IRQ16L(7), 40, 167),
+        PINMUX_IRQ(EXT_IRQ16L(8), 41, 168),
+        PINMUX_IRQ(EXT_IRQ16L(9), 42, 169),
+        PINMUX_IRQ(EXT_IRQ16L(10), 65),
+        PINMUX_IRQ(EXT_IRQ16L(11), 67),
+        PINMUX_IRQ(EXT_IRQ16L(12), 80, 137),
+        PINMUX_IRQ(EXT_IRQ16L(13), 81, 145),
+        PINMUX_IRQ(EXT_IRQ16L(14), 82, 146),
+        PINMUX_IRQ(EXT_IRQ16L(15), 83, 147),
+        PINMUX_IRQ(EXT_IRQ16H(16), 84, 170),
+        PINMUX_IRQ(EXT_IRQ16H(17), 85),
+        PINMUX_IRQ(EXT_IRQ16H(18), 86),
+        PINMUX_IRQ(EXT_IRQ16H(19), 87),
+        PINMUX_IRQ(EXT_IRQ16H(20), 92),
+        PINMUX_IRQ(EXT_IRQ16H(21), 93),
+        PINMUX_IRQ(EXT_IRQ16H(22), 94),
+        PINMUX_IRQ(EXT_IRQ16H(23), 95),
+        PINMUX_IRQ(EXT_IRQ16H(24), 112),
+        PINMUX_IRQ(EXT_IRQ16H(25), 119),
+        PINMUX_IRQ(EXT_IRQ16H(26), 121, 172),
+        PINMUX_IRQ(EXT_IRQ16H(27), 122, 180),
+        PINMUX_IRQ(EXT_IRQ16H(28), 123, 181),
+        PINMUX_IRQ(EXT_IRQ16H(29), 129, 182),
+        PINMUX_IRQ(EXT_IRQ16H(30), 130, 183),
+        PINMUX_IRQ(EXT_IRQ16H(31), 138, 184),
+};
+
+#define PORTnCR_PULMD_OFF       (0 << 6)
+#define PORTnCR_PULMD_DOWN      (2 << 6)
+#define PORTnCR_PULMD_UP        (3 << 6)
+#define PORTnCR_PULMD_MASK      (3 << 6)
+
+struct sh7372_portcr_group {
+        unsigned int end_pin;
+        unsigned int offset;
+};
+
+static const struct sh7372_portcr_group sh7372_portcr_offsets[] = {
+        { 45,  0x1000 }, { 75,  0x2000 }, { 99,  0x0000 }, { 120, 0x3000 },
+        { 151, 0x0000 }, { 155, 0x3000 }, { 166, 0x0000 }, { 190, 0x2000 },
+};
+
+static void __iomem *sh7372_pinmux_portcr(struct sh_pfc *pfc, unsigned int pin)
+{
+        unsigned int i;
+
+        for (i = 0; i < ARRAY_SIZE(sh7372_portcr_offsets); ++i) {
+                const struct sh7372_portcr_group *group =
+                        &sh7372_portcr_offsets[i];
+
+                if (i <= group->end_pin)
+                        return pfc->window->virt + group->offset + pin;
+        }
+
+        return NULL;
+}
+
+static unsigned int sh7372_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
+{
+        void __iomem *addr = sh7372_pinmux_portcr(pfc, pin);
+        u32 value = ioread8(addr) & PORTnCR_PULMD_MASK;
+
+        switch (value) {
+        case PORTnCR_PULMD_UP:
+                return PIN_CONFIG_BIAS_PULL_UP;
+        case PORTnCR_PULMD_DOWN:
+                return PIN_CONFIG_BIAS_PULL_DOWN;
+        case PORTnCR_PULMD_OFF:
+        default:
+                return PIN_CONFIG_BIAS_DISABLE;
+        }
+}
+
+static void sh7372_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
+                                   unsigned int bias)
+{
+        void __iomem *addr = sh7372_pinmux_portcr(pfc, pin);
+        u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK;
+
+        switch (bias) {
+        case PIN_CONFIG_BIAS_PULL_UP:
+                value |= PORTnCR_PULMD_UP;
+                break;
+        case PIN_CONFIG_BIAS_PULL_DOWN:
+                value |= PORTnCR_PULMD_DOWN;
+                break;
+        }
+
+        iowrite8(value, addr);
+}
+
+static const struct sh_pfc_soc_operations sh7372_pinmux_ops = {
+        .get_bias = sh7372_pinmux_get_bias,
+        .set_bias = sh7372_pinmux_set_bias,
 };
 
 const struct sh_pfc_soc_info sh7372_pinmux_info = {
         .name = "sh7372_pfc",
+        .ops = &sh7372_pinmux_ops,
+
         .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
-        .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
-        .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
         .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
 
@@ -1825,9 +2664,6 @@ const struct sh_pfc_soc_info sh7372_pinmux_info = {
         .functions = pinmux_functions,
         .nr_functions = ARRAY_SIZE(pinmux_functions),
 
-        .func_gpios = pinmux_func_gpios,
-        .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
-
         .cfg_regs = pinmux_config_regs,
         .data_regs = pinmux_data_regs,
 
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
index 587f7772abf2..7956df58d751 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
@@ -20,9 +20,12 @@
  */
 #include <linux/io.h>
 #include <linux/kernel.h>
+#include <linux/module.h>
 #include <linux/pinctrl/pinconf-generic.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/machine.h>
+#include <linux/slab.h>
 
-#include <mach/sh73a0.h>
 #include <mach/irqs.h>
 
 #include "core.h"
@@ -2538,6 +2541,157 @@ static const unsigned int sdhi2_ctrl_pins[] = {
 static const unsigned int sdhi2_ctrl_mux[] = {
         SDHICMD2_MARK, SDHICLK2_MARK,
 };
+/* - TPU0 ------------------------------------------------------------------- */
+static const unsigned int tpu0_to0_pins[] = {
+        /* TO */
+        55,
+};
+static const unsigned int tpu0_to0_mux[] = {
+        TPU0TO0_MARK,
+};
+static const unsigned int tpu0_to1_pins[] = {
+        /* TO */
+        59,
+};
+static const unsigned int tpu0_to1_mux[] = {
+        TPU0TO1_MARK,
+};
+static const unsigned int tpu0_to2_pins[] = {
+        /* TO */
+        140,
+};
+static const unsigned int tpu0_to2_mux[] = {
+        TPU0TO2_MARK,
+};
+static const unsigned int tpu0_to3_pins[] = {
+        /* TO */
+        141,
+};
+static const unsigned int tpu0_to3_mux[] = {
+        TPU0TO3_MARK,
+};
+/* - TPU1 ------------------------------------------------------------------- */
+static const unsigned int tpu1_to0_pins[] = {
+        /* TO */
+        246,
+};
+static const unsigned int tpu1_to0_mux[] = {
+        TPU1TO0_MARK,
+};
+static const unsigned int tpu1_to1_0_pins[] = {
+        /* TO */
+        28,
+};
+static const unsigned int tpu1_to1_0_mux[] = {
+        PORT28_TPU1TO1_MARK,
+};
+static const unsigned int tpu1_to1_1_pins[] = {
+        /* TO */
+        29,
+};
+static const unsigned int tpu1_to1_1_mux[] = {
+        PORT29_TPU1TO1_MARK,
+};
+static const unsigned int tpu1_to2_pins[] = {
+        /* TO */
+        153,
+};
+static const unsigned int tpu1_to2_mux[] = {
+        TPU1TO2_MARK,
+};
+static const unsigned int tpu1_to3_pins[] = {
+        /* TO */
+        145,
+};
+static const unsigned int tpu1_to3_mux[] = {
+        TPU1TO3_MARK,
+};
+/* - TPU2 ------------------------------------------------------------------- */
+static const unsigned int tpu2_to0_pins[] = {
+        /* TO */
+        248,
+};
+static const unsigned int tpu2_to0_mux[] = {
+        TPU2TO0_MARK,
+};
+static const unsigned int tpu2_to1_pins[] = {
+        /* TO */
+        197,
+};
+static const unsigned int tpu2_to1_mux[] = {
+        TPU2TO1_MARK,
+};
+static const unsigned int tpu2_to2_pins[] = {
+        /* TO */
+        50,
+};
+static const unsigned int tpu2_to2_mux[] = {
+        TPU2TO2_MARK,
+};
+static const unsigned int tpu2_to3_pins[] = {
+        /* TO */
+        51,
+};
+static const unsigned int tpu2_to3_mux[] = {
+        TPU2TO3_MARK,
+};
+/* - TPU3 ------------------------------------------------------------------- */
+static const unsigned int tpu3_to0_pins[] = {
+        /* TO */
+        163,
+};
+static const unsigned int tpu3_to0_mux[] = {
+        TPU3TO0_MARK,
+};
+static const unsigned int tpu3_to1_pins[] = {
+        /* TO */
+        247,
+};
+static const unsigned int tpu3_to1_mux[] = {
+        TPU3TO1_MARK,
+};
+static const unsigned int tpu3_to2_pins[] = {
+        /* TO */
+        54,
+};
+static const unsigned int tpu3_to2_mux[] = {
+        TPU3TO2_MARK,
+};
+static const unsigned int tpu3_to3_pins[] = {
+        /* TO */
+        53,
+};
+static const unsigned int tpu3_to3_mux[] = {
+        TPU3TO3_MARK,
+};
+/* - TPU4 ------------------------------------------------------------------- */
+static const unsigned int tpu4_to0_pins[] = {
+        /* TO */
+        241,
+};
+static const unsigned int tpu4_to0_mux[] = {
+        TPU4TO0_MARK,
+};
+static const unsigned int tpu4_to1_pins[] = {
+        /* TO */
+        199,
+};
+static const unsigned int tpu4_to1_mux[] = {
+        TPU4TO1_MARK,
+};
+static const unsigned int tpu4_to2_pins[] = {
+        /* TO */
+        58,
+};
+static const unsigned int tpu4_to2_mux[] = {
+        TPU4TO2_MARK,
+};
+static const unsigned int tpu4_to3_pins[] = {
+        /* TO */
+};
+static const unsigned int tpu4_to3_mux[] = {
+        TPU4TO3_MARK,
+};
 /* - USB -------------------------------------------------------------------- */
 static const unsigned int usb_vbus_pins[] = {
         /* VBUS */
@@ -2689,6 +2843,27 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
         SH_PFC_PIN_GROUP(sdhi2_data1),
         SH_PFC_PIN_GROUP(sdhi2_data4),
         SH_PFC_PIN_GROUP(sdhi2_ctrl),
+        SH_PFC_PIN_GROUP(tpu0_to0),
+        SH_PFC_PIN_GROUP(tpu0_to1),
+        SH_PFC_PIN_GROUP(tpu0_to2),
+        SH_PFC_PIN_GROUP(tpu0_to3),
+        SH_PFC_PIN_GROUP(tpu1_to0),
+        SH_PFC_PIN_GROUP(tpu1_to1_0),
+        SH_PFC_PIN_GROUP(tpu1_to1_1),
+        SH_PFC_PIN_GROUP(tpu1_to2),
+        SH_PFC_PIN_GROUP(tpu1_to3),
+        SH_PFC_PIN_GROUP(tpu2_to0),
+        SH_PFC_PIN_GROUP(tpu2_to1),
+        SH_PFC_PIN_GROUP(tpu2_to2),
+        SH_PFC_PIN_GROUP(tpu2_to3),
+        SH_PFC_PIN_GROUP(tpu3_to0),
+        SH_PFC_PIN_GROUP(tpu3_to1),
+        SH_PFC_PIN_GROUP(tpu3_to2),
+        SH_PFC_PIN_GROUP(tpu3_to3),
+        SH_PFC_PIN_GROUP(tpu4_to0),
+        SH_PFC_PIN_GROUP(tpu4_to1),
+        SH_PFC_PIN_GROUP(tpu4_to2),
+        SH_PFC_PIN_GROUP(tpu4_to3),
         SH_PFC_PIN_GROUP(usb_vbus),
 };
 
@@ -2908,6 +3083,42 @@ static const char * const usb_groups[] = {
         "usb_vbus",
 };
 
+static const char * const tpu0_groups[] = {
+        "tpu0_to0",
+        "tpu0_to1",
+        "tpu0_to2",
+        "tpu0_to3",
+};
+
+static const char * const tpu1_groups[] = {
+        "tpu1_to0",
+        "tpu1_to1_0",
+        "tpu1_to1_1",
+        "tpu1_to2",
+        "tpu1_to3",
+};
+
+static const char * const tpu2_groups[] = {
+        "tpu2_to0",
+        "tpu2_to1",
+        "tpu2_to2",
+        "tpu2_to3",
+};
+
+static const char * const tpu3_groups[] = {
+        "tpu3_to0",
+        "tpu3_to1",
+        "tpu3_to2",
+        "tpu3_to3",
+};
+
+static const char * const tpu4_groups[] = {
+        "tpu4_to0",
+        "tpu4_to1",
+        "tpu4_to2",
+        "tpu4_to3",
+};
+
 static const struct sh_pfc_function pinmux_functions[] = {
         SH_PFC_FUNCTION(bsc),
         SH_PFC_FUNCTION(fsia),
@@ -2933,400 +3144,14 @@ static const struct sh_pfc_function pinmux_functions[] = {
         SH_PFC_FUNCTION(sdhi0),
         SH_PFC_FUNCTION(sdhi1),
         SH_PFC_FUNCTION(sdhi2),
+        SH_PFC_FUNCTION(tpu0),
+        SH_PFC_FUNCTION(tpu1),
+        SH_PFC_FUNCTION(tpu2),
+        SH_PFC_FUNCTION(tpu3),
+        SH_PFC_FUNCTION(tpu4),
         SH_PFC_FUNCTION(usb),
 };
 
-#define PINMUX_FN_BASE  GPIO_FN_GPI0
-
-static const struct pinmux_func pinmux_func_gpios[] = {
-        /* Table 25-1 (Functions 0-7) */
-        GPIO_FN(GPI0),
-        GPIO_FN(GPI1),
-        GPIO_FN(GPI2),
-        GPIO_FN(GPI3),
-        GPIO_FN(GPI4),
-        GPIO_FN(GPI5),
-        GPIO_FN(GPI6),
-        GPIO_FN(GPI7),
-        GPIO_FN(GPO7), \
-        GPIO_FN(MFG0_OUT2),
-        GPIO_FN(GPO6), \
-        GPIO_FN(MFG1_OUT2),
-        GPIO_FN(GPO5), \
-        GPIO_FN(PORT16_VIO_CKOR),
-        GPIO_FN(PORT19_VIO_CKO2),
-        GPIO_FN(GPO0),
-        GPIO_FN(GPO1),
-        GPIO_FN(GPO2), \
-        GPIO_FN(STATUS0),
-        GPIO_FN(GPO3), \
-        GPIO_FN(STATUS1),
-        GPIO_FN(GPO4), \
-        GPIO_FN(STATUS2),
-        GPIO_FN(VINT),
-        GPIO_FN(TCKON),
-        GPIO_FN(XDVFS1), \
-        GPIO_FN(MFG0_OUT1), \
-        GPIO_FN(PORT27_IROUT),
-        GPIO_FN(XDVFS2), \
-        GPIO_FN(PORT28_TPU1TO1),
-        GPIO_FN(SIM_RST), \
-        GPIO_FN(PORT29_TPU1TO1),
-        GPIO_FN(SIM_CLK), \
-        GPIO_FN(PORT30_VIO_CKOR),
-        GPIO_FN(SIM_D), \
-        GPIO_FN(PORT31_IROUT),
-        GPIO_FN(XWUP),
-        GPIO_FN(VACK),
-        GPIO_FN(XTAL1L),
-        GPIO_FN(PORT49_IROUT), \
-        GPIO_FN(BBIF2_TSYNC2), \
-        GPIO_FN(TPU2TO2), \
-
-        GPIO_FN(BBIF2_TSCK2), \
-        GPIO_FN(TPU2TO3), \
-        GPIO_FN(BBIF2_TXD2),
-        GPIO_FN(TPU3TO3), \
-        GPIO_FN(TPU3TO2), \
-        GPIO_FN(TPU0TO0),
-        GPIO_FN(A0), \
-        GPIO_FN(BS_),
-        GPIO_FN(A12), \
-        GPIO_FN(TPU4TO2),
-        GPIO_FN(A13), \
-        GPIO_FN(TPU0TO1),
-        GPIO_FN(A14), \
-        GPIO_FN(A15), \
-        GPIO_FN(A16), \
-        GPIO_FN(MSIOF0_SS1),
-        GPIO_FN(A17), \
-        GPIO_FN(MSIOF0_TSYNC),
-        GPIO_FN(A18), \
-        GPIO_FN(MSIOF0_TSCK),
-        GPIO_FN(A19), \
-        GPIO_FN(MSIOF0_TXD),
-        GPIO_FN(A20), \
-        GPIO_FN(MSIOF0_RSCK),
-        GPIO_FN(A21), \
-        GPIO_FN(MSIOF0_RSYNC),
-        GPIO_FN(A22), \
-        GPIO_FN(MSIOF0_MCK0),
-        GPIO_FN(A23), \
-        GPIO_FN(MSIOF0_MCK1),
-        GPIO_FN(A24), \
-        GPIO_FN(MSIOF0_RXD),
-        GPIO_FN(A25), \
-        GPIO_FN(MSIOF0_SS2),
-        GPIO_FN(A26), \
-        GPIO_FN(FCE1_),
-        GPIO_FN(DACK0),
-        GPIO_FN(FCE0_), \
-        GPIO_FN(WAIT_), \
-        GPIO_FN(DREQ0),
-        GPIO_FN(FRB),
-        GPIO_FN(CKO),
-        GPIO_FN(NBRSTOUT_),
-        GPIO_FN(NBRST_),
-        GPIO_FN(BBIF2_TXD),
-        GPIO_FN(BBIF2_RXD),
-        GPIO_FN(BBIF2_SYNC),
-        GPIO_FN(BBIF2_SCK),
-        GPIO_FN(MFG3_IN2),
-        GPIO_FN(MFG3_IN1),
-        GPIO_FN(BBIF1_SS2), \
-        GPIO_FN(MFG3_OUT1),
-        GPIO_FN(HSI_RX_DATA), \
-        GPIO_FN(BBIF1_RXD),
-        GPIO_FN(HSI_TX_WAKE), \
-        GPIO_FN(BBIF1_TSCK),
-        GPIO_FN(HSI_TX_DATA), \
-        GPIO_FN(BBIF1_TSYNC),
-        GPIO_FN(HSI_TX_READY), \
-        GPIO_FN(BBIF1_TXD),
-        GPIO_FN(HSI_RX_READY), \
-        GPIO_FN(BBIF1_RSCK), \
-        GPIO_FN(HSI_RX_WAKE), \
-        GPIO_FN(BBIF1_RSYNC), \
-        GPIO_FN(HSI_RX_FLAG), \
-        GPIO_FN(BBIF1_SS1), \
-        GPIO_FN(BBIF1_FLOW),
-        GPIO_FN(HSI_TX_FLAG),
-        GPIO_FN(VIO_VD), \
-        GPIO_FN(VIO2_VD), \
-
-        GPIO_FN(VIO_HD), \
-        GPIO_FN(VIO2_HD), \
-        GPIO_FN(VIO_D0), \
-        GPIO_FN(PORT130_MSIOF2_RXD), \
-        GPIO_FN(VIO_D1), \
-        GPIO_FN(PORT131_MSIOF2_SS1), \
-        GPIO_FN(VIO_D2), \
-        GPIO_FN(PORT132_MSIOF2_SS2), \
-        GPIO_FN(VIO_D3), \
-        GPIO_FN(MSIOF2_TSYNC), \
-        GPIO_FN(VIO_D4), \
-        GPIO_FN(MSIOF2_TXD), \
-        GPIO_FN(VIO_D5), \
-        GPIO_FN(MSIOF2_TSCK), \
-        GPIO_FN(VIO_D6), \
-        GPIO_FN(VIO_D7), \
-        GPIO_FN(VIO_D8), \
-        GPIO_FN(VIO2_D0), \
-        GPIO_FN(VIO_D9), \
-        GPIO_FN(VIO2_D1), \
-        GPIO_FN(VIO_D10), \
-        GPIO_FN(TPU0TO2), \
-        GPIO_FN(VIO2_D2), \
-        GPIO_FN(VIO_D11), \
-        GPIO_FN(TPU0TO3), \
-        GPIO_FN(VIO2_D3), \
-        GPIO_FN(VIO_D12), \
-        GPIO_FN(VIO2_D4), \
-        GPIO_FN(VIO_D13), \
-        GPIO_FN(VIO2_D5), \
-        GPIO_FN(VIO_D14), \
-        GPIO_FN(VIO2_D6), \
-        GPIO_FN(VIO_D15), \
-        GPIO_FN(TPU1TO3), \
-        GPIO_FN(VIO2_D7), \
-        GPIO_FN(VIO_CLK), \
-        GPIO_FN(VIO2_CLK), \
-        GPIO_FN(VIO_FIELD), \
-        GPIO_FN(VIO2_FIELD), \
-        GPIO_FN(VIO_CKO),
-        GPIO_FN(A27), \
-        GPIO_FN(MFG0_IN1), \
-        GPIO_FN(MFG0_IN2),
-        GPIO_FN(TS_SPSYNC3), \
-        GPIO_FN(MSIOF2_RSCK),
-        GPIO_FN(TS_SDAT3), \
-        GPIO_FN(MSIOF2_RSYNC),
-        GPIO_FN(TPU1TO2), \
-        GPIO_FN(TS_SDEN3), \
-        GPIO_FN(PORT153_MSIOF2_SS1),
-        GPIO_FN(MSIOF2_MCK0),
-        GPIO_FN(MSIOF2_MCK1),
-        GPIO_FN(PORT156_MSIOF2_SS2),
-        GPIO_FN(PORT157_MSIOF2_RXD),
-        GPIO_FN(DINT_), \
-        GPIO_FN(TS_SCK3),
-        GPIO_FN(NMI),
-        GPIO_FN(TPU3TO0),
-        GPIO_FN(BBIF2_TSYNC1),
-        GPIO_FN(BBIF2_TSCK1),
-        GPIO_FN(BBIF2_TXD1),
-        GPIO_FN(MFG2_OUT2), \
-        GPIO_FN(TPU2TO1),
-        GPIO_FN(TPU4TO1), \
-        GPIO_FN(MFG4_OUT2),
-        GPIO_FN(D16),
-        GPIO_FN(D17),
-        GPIO_FN(D18),
-        GPIO_FN(D19),
-        GPIO_FN(D20),
-        GPIO_FN(D21),
-        GPIO_FN(D22),
-        GPIO_FN(PORT207_MSIOF0L_SS1), \
-        GPIO_FN(D23),
-        GPIO_FN(PORT208_MSIOF0L_SS2), \
-        GPIO_FN(D24),
-        GPIO_FN(D25),
-        GPIO_FN(DREQ2), \
-        GPIO_FN(PORT210_MSIOF0L_SS1), \
-        GPIO_FN(D26),
-        GPIO_FN(PORT211_MSIOF0L_SS2), \
-        GPIO_FN(D27),
-        GPIO_FN(TS_SPSYNC1), \
-        GPIO_FN(MSIOF0L_MCK0), \
-        GPIO_FN(D28),
-        GPIO_FN(TS_SDAT1), \
-        GPIO_FN(MSIOF0L_MCK1), \
-        GPIO_FN(D29),
-        GPIO_FN(TS_SDEN1), \
-        GPIO_FN(MSIOF0L_RSCK), \
-        GPIO_FN(D30),
-        GPIO_FN(TS_SCK1), \
-        GPIO_FN(MSIOF0L_RSYNC), \
-        GPIO_FN(D31),
-        GPIO_FN(DACK2), \
-        GPIO_FN(MSIOF0L_TSYNC), \
-        GPIO_FN(VIO2_FIELD3), \
-        GPIO_FN(DACK3), \
-        GPIO_FN(PORT218_VIO_CKOR),
-        GPIO_FN(DREQ3), \
-        GPIO_FN(MSIOF0L_TSCK), \
-        GPIO_FN(VIO2_CLK3), \
-        GPIO_FN(DREQ1), \
-        GPIO_FN(PWEN), \
-        GPIO_FN(MSIOF0L_RXD), \
-        GPIO_FN(VIO2_HD3), \
-        GPIO_FN(DACK1), \
-        GPIO_FN(OVCN), \
-        GPIO_FN(MSIOF0L_TXD), \
-        GPIO_FN(VIO2_VD3), \
-
-        GPIO_FN(OVCN2),
-        GPIO_FN(EXTLP), \
-        GPIO_FN(PORT226_VIO_CKO2),
-        GPIO_FN(IDIN),
-        GPIO_FN(MFG1_IN1),
-        GPIO_FN(MSIOF1_TXD), \
-        GPIO_FN(MSIOF1_TSYNC), \
-        GPIO_FN(MSIOF1_TSCK), \
-        GPIO_FN(MSIOF1_RXD), \
-        GPIO_FN(MSIOF1_RSCK), \
-        GPIO_FN(VIO2_CLK2), \
-        GPIO_FN(MSIOF1_RSYNC), \
-        GPIO_FN(MFG1_IN2), \
-        GPIO_FN(VIO2_VD2), \
-        GPIO_FN(MSIOF1_MCK0), \
-        GPIO_FN(MSIOF1_MCK1), \
-        GPIO_FN(MSIOF1_SS1), \
-        GPIO_FN(VIO2_FIELD2), \
-        GPIO_FN(MSIOF1_SS2), \
-        GPIO_FN(VIO2_HD2), \
-        GPIO_FN(PORT241_IROUT), \
-        GPIO_FN(MFG4_OUT1), \
-        GPIO_FN(TPU4TO0),
-        GPIO_FN(MFG4_IN2),
-        GPIO_FN(PORT243_VIO_CKO2),
-        GPIO_FN(MFG2_IN1), \
-        GPIO_FN(MSIOF2R_RXD),
-        GPIO_FN(MFG2_IN2), \
-        GPIO_FN(MSIOF2R_TXD),
-        GPIO_FN(MFG1_OUT1), \
-        GPIO_FN(TPU1TO0),
-        GPIO_FN(MFG3_OUT2), \
-        GPIO_FN(TPU3TO1),
-        GPIO_FN(MFG2_OUT1), \
-        GPIO_FN(TPU2TO0), \
-        GPIO_FN(MSIOF2R_TSCK),
-        GPIO_FN(PORT249_IROUT), \
-        GPIO_FN(MFG4_IN1), \
-        GPIO_FN(MSIOF2R_TSYNC),
-        GPIO_FN(SDHICLK0),
-        GPIO_FN(SDHICD0),
-        GPIO_FN(SDHID0_0),
-        GPIO_FN(SDHID0_1),
-        GPIO_FN(SDHID0_2),
-        GPIO_FN(SDHID0_3),
-        GPIO_FN(SDHICMD0),
-        GPIO_FN(SDHIWP0),
-        GPIO_FN(SDHICLK1),
-        GPIO_FN(SDHID1_0), \
-        GPIO_FN(TS_SPSYNC2),
-        GPIO_FN(SDHID1_1), \
-        GPIO_FN(TS_SDAT2),
-        GPIO_FN(SDHID1_2), \
-        GPIO_FN(TS_SDEN2),
-        GPIO_FN(SDHID1_3), \
-        GPIO_FN(TS_SCK2),
-        GPIO_FN(SDHICMD1),
-        GPIO_FN(SDHICLK2),
-        GPIO_FN(SDHID2_0), \
-        GPIO_FN(TS_SPSYNC4),
-        GPIO_FN(SDHID2_1), \
-        GPIO_FN(TS_SDAT4),
-        GPIO_FN(SDHID2_2), \
-        GPIO_FN(TS_SDEN4),
-        GPIO_FN(SDHID2_3), \
-        GPIO_FN(TS_SCK4),
-        GPIO_FN(SDHICMD2),
-        GPIO_FN(MMCCLK0),
-        GPIO_FN(MMCD0_0),
-        GPIO_FN(MMCD0_1),
-        GPIO_FN(MMCD0_2),
-        GPIO_FN(MMCD0_3),
-        GPIO_FN(MMCD0_4), \
-        GPIO_FN(TS_SPSYNC5),
-        GPIO_FN(MMCD0_5), \
-        GPIO_FN(TS_SDAT5),
-        GPIO_FN(MMCD0_6), \
-        GPIO_FN(TS_SDEN5),
-        GPIO_FN(MMCD0_7), \
-        GPIO_FN(TS_SCK5),
-        GPIO_FN(MMCCMD0),
-        GPIO_FN(RESETOUTS_), \
-        GPIO_FN(EXTAL2OUT),
-        GPIO_FN(MCP_WAIT__MCP_FRB),
-        GPIO_FN(MCP_CKO), \
-        GPIO_FN(MMCCLK1),
-        GPIO_FN(MCP_D15_MCP_NAF15),
-        GPIO_FN(MCP_D14_MCP_NAF14),
-        GPIO_FN(MCP_D13_MCP_NAF13),
-        GPIO_FN(MCP_D12_MCP_NAF12),
-        GPIO_FN(MCP_D11_MCP_NAF11),
-        GPIO_FN(MCP_D10_MCP_NAF10),
-        GPIO_FN(MCP_D9_MCP_NAF9),
-        GPIO_FN(MCP_D8_MCP_NAF8), \
-        GPIO_FN(MMCCMD1),
-        GPIO_FN(MCP_D7_MCP_NAF7), \
-        GPIO_FN(MMCD1_7),
-
-        GPIO_FN(MCP_D6_MCP_NAF6), \
-        GPIO_FN(MMCD1_6),
-        GPIO_FN(MCP_D5_MCP_NAF5), \
-        GPIO_FN(MMCD1_5),
-        GPIO_FN(MCP_D4_MCP_NAF4), \
-        GPIO_FN(MMCD1_4),
-        GPIO_FN(MCP_D3_MCP_NAF3), \
-        GPIO_FN(MMCD1_3),
-        GPIO_FN(MCP_D2_MCP_NAF2), \
-        GPIO_FN(MMCD1_2),
-        GPIO_FN(MCP_D1_MCP_NAF1), \
-        GPIO_FN(MMCD1_1),
-        GPIO_FN(MCP_D0_MCP_NAF0), \
-        GPIO_FN(MMCD1_0),
-        GPIO_FN(MCP_NBRSTOUT_),
-        GPIO_FN(MCP_WE0__MCP_FWE), \
-        GPIO_FN(MCP_RDWR_MCP_FWE),
-
-        /* MSEL2 special cases */
-        GPIO_FN(TSIF2_TS_XX1),
-        GPIO_FN(TSIF2_TS_XX2),
-        GPIO_FN(TSIF2_TS_XX3),
-        GPIO_FN(TSIF2_TS_XX4),
-        GPIO_FN(TSIF2_TS_XX5),
-        GPIO_FN(TSIF1_TS_XX1),
-        GPIO_FN(TSIF1_TS_XX2),
-        GPIO_FN(TSIF1_TS_XX3),
-        GPIO_FN(TSIF1_TS_XX4),
-        GPIO_FN(TSIF1_TS_XX5),
-        GPIO_FN(TSIF0_TS_XX1),
-        GPIO_FN(TSIF0_TS_XX2),
-        GPIO_FN(TSIF0_TS_XX3),
-        GPIO_FN(TSIF0_TS_XX4),
-        GPIO_FN(TSIF0_TS_XX5),
-        GPIO_FN(MST1_TS_XX1),
-        GPIO_FN(MST1_TS_XX2),
-        GPIO_FN(MST1_TS_XX3),
-        GPIO_FN(MST1_TS_XX4),
-        GPIO_FN(MST1_TS_XX5),
-        GPIO_FN(MST0_TS_XX1),
-        GPIO_FN(MST0_TS_XX2),
-        GPIO_FN(MST0_TS_XX3),
-        GPIO_FN(MST0_TS_XX4),
-        GPIO_FN(MST0_TS_XX5),
-
-        /* MSEL3 special cases */
-        GPIO_FN(SDHI0_VCCQ_MC0_ON),
-        GPIO_FN(SDHI0_VCCQ_MC0_OFF),
-        GPIO_FN(DEBUG_MON_VIO),
-        GPIO_FN(DEBUG_MON_LCDD),
-        GPIO_FN(LCDC_LCDC0),
-        GPIO_FN(LCDC_LCDC1),
-
-        /* MSEL4 special cases */
-        GPIO_FN(IRQ9_MEM_INT),
-        GPIO_FN(IRQ9_MCP_INT),
-        GPIO_FN(A11),
-        GPIO_FN(TPU4TO3),
-        GPIO_FN(RESETA_N_PU_ON),
-        GPIO_FN(RESETA_N_PU_OFF),
-        GPIO_FN(EDBGREQ_PD),
-        GPIO_FN(EDBGREQ_PU),
-};
-
 #undef PORTCR
 #define PORTCR(nr, reg)                                                 \
         {                                                               \
@@ -3888,6 +3713,92 @@ static const struct pinmux_irq pinmux_irqs[] = {
         PINMUX_IRQ(EXT_IRQ16L(9), 308),
 };
 
+/* -----------------------------------------------------------------------------
+ * VCCQ MC0 regulator
+ */
+
+static void sh73a0_vccq_mc0_endisable(struct regulator_dev *reg, bool enable)
+{
+        struct sh_pfc *pfc = reg->reg_data;
+        void __iomem *addr = pfc->window[1].virt + 4;
+        unsigned long flags;
+        u32 value;
+
+        spin_lock_irqsave(&pfc->lock, flags);
+
+        value = ioread32(addr);
+
+        if (enable)
+                value |= BIT(28);
+        else
+                value &= ~BIT(28);
+
+        iowrite32(value, addr);
+
+        spin_unlock_irqrestore(&pfc->lock, flags);
+}
+
+static int sh73a0_vccq_mc0_enable(struct regulator_dev *reg)
+{
+        sh73a0_vccq_mc0_endisable(reg, true);
+        return 0;
+}
+
+static int sh73a0_vccq_mc0_disable(struct regulator_dev *reg)
+{
+        sh73a0_vccq_mc0_endisable(reg, false);
+        return 0;
+}
+
+static int sh73a0_vccq_mc0_is_enabled(struct regulator_dev *reg)
+{
+        struct sh_pfc *pfc = reg->reg_data;
+        void __iomem *addr = pfc->window[1].virt + 4;
+        unsigned long flags;
+        u32 value;
+
+        spin_lock_irqsave(&pfc->lock, flags);
+        value = ioread32(addr);
+        spin_unlock_irqrestore(&pfc->lock, flags);
+
+        return !!(value & BIT(28));
+}
+
+static int sh73a0_vccq_mc0_get_voltage(struct regulator_dev *reg)
+{
+        return 3300000;
+}
+
+static struct regulator_ops sh73a0_vccq_mc0_ops = {
+        .enable = sh73a0_vccq_mc0_enable,
+        .disable = sh73a0_vccq_mc0_disable,
+        .is_enabled = sh73a0_vccq_mc0_is_enabled,
+        .get_voltage = sh73a0_vccq_mc0_get_voltage,
+};
+
+static const struct regulator_desc sh73a0_vccq_mc0_desc = {
+        .owner = THIS_MODULE,
+        .name = "vccq_mc0",
+        .type = REGULATOR_VOLTAGE,
+        .ops = &sh73a0_vccq_mc0_ops,
+};
+
+static struct regulator_consumer_supply sh73a0_vccq_mc0_consumers[] = {
+        REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
+};
+
+static const struct regulator_init_data sh73a0_vccq_mc0_init_data = {
+        .constraints = {
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies = ARRAY_SIZE(sh73a0_vccq_mc0_consumers),
+        .consumer_supplies = sh73a0_vccq_mc0_consumers,
+};
+
+/* -----------------------------------------------------------------------------
+ * Pin bias
+ */
+
 #define PORTnCR_PULMD_OFF       (0 << 6)
 #define PORTnCR_PULMD_DOWN      (2 << 6)
 #define PORTnCR_PULMD_UP        (3 << 6)
@@ -3934,7 +3845,51 @@ static void sh73a0_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
         iowrite8(value, addr);
 }
 
+/* -----------------------------------------------------------------------------
+ * SoC information
+ */
+
+struct sh73a0_pinmux_data {
+        struct regulator_dev *vccq_mc0;
+};
+
+static int sh73a0_pinmux_soc_init(struct sh_pfc *pfc)
+{
+        struct sh73a0_pinmux_data *data;
+        struct regulator_config cfg = { };
+        int ret;
+
+        data = devm_kzalloc(pfc->dev, sizeof(*data), GFP_KERNEL);
+        if (data == NULL)
+                return -ENOMEM;
+
+        cfg.dev = pfc->dev;
+        cfg.init_data = &sh73a0_vccq_mc0_init_data;
+        cfg.driver_data = pfc;
+
+        data->vccq_mc0 = regulator_register(&sh73a0_vccq_mc0_desc, &cfg);
+        if (IS_ERR(data->vccq_mc0)) {
+                ret = PTR_ERR(data->vccq_mc0);
+                dev_err(pfc->dev, "Failed to register VCCQ MC0 regulator: %d\n",
+                        ret);
+                return ret;
+        }
+
+        pfc->soc_data = data;
+
+        return 0;
+}
+
+static void sh73a0_pinmux_soc_exit(struct sh_pfc *pfc)
+{
+        struct sh73a0_pinmux_data *data = pfc->soc_data;
+
+        regulator_unregister(data->vccq_mc0);
+}
+
 static const struct sh_pfc_soc_operations sh73a0_pinmux_ops = {
+        .init = sh73a0_pinmux_soc_init,
+        .exit = sh73a0_pinmux_soc_exit,
         .get_bias = sh73a0_pinmux_get_bias,
         .set_bias = sh73a0_pinmux_set_bias,
 };
@@ -3956,9 +3911,6 @@ const struct sh_pfc_soc_info sh73a0_pinmux_info = {
         .functions = pinmux_functions,
         .nr_functions = ARRAY_SIZE(pinmux_functions),
 
-        .func_gpios = pinmux_func_gpios,
-        .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
-
         .cfg_regs = pinmux_config_regs,
         .data_regs = pinmux_data_regs,
 
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index 3b785fc428d5..830ae1ffd0b5 100644
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -11,8 +11,8 @@
 #ifndef __SH_PFC_H
 #define __SH_PFC_H
 
+#include <linux/bug.h>
 #include <linux/stringify.h>
-#include <asm-generic/gpio.h>
 
 typedef unsigned short pinmux_enum_t;
 
@@ -129,6 +129,8 @@ struct pinmux_range {
 struct sh_pfc;
 
 struct sh_pfc_soc_operations {
+        int (*init)(struct sh_pfc *pfc);
+        void (*exit)(struct sh_pfc *pfc);
         unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin);
         void (*set_bias)(struct sh_pfc *pfc, unsigned int pin,
                          unsigned int bias);
diff --git a/include/linux/platform_data/gpio-rcar.h b/include/linux/platform_data/gpio-rcar.h
index b253f77a7ddf..2d8d69432813 100644
--- a/include/linux/platform_data/gpio-rcar.h
+++ b/include/linux/platform_data/gpio-rcar.h
@@ -17,10 +17,13 @@
 #define __GPIO_RCAR_H__
 
 struct gpio_rcar_config {
-        unsigned int gpio_base;
+        int gpio_base;
         unsigned int irq_base;
         unsigned int number_of_pins;
         const char *pctl_name;
+        unsigned has_both_edge_trigger:1;
 };
 
+#define RCAR_GP_PIN(bank, pin)          (((bank) * 32) + (pin))
+
 #endif /* __GPIO_RCAR_H__ */