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-rw-r--r--sound/pci/pcxhr/Makefile2
-rw-r--r--sound/pci/pcxhr/pcxhr.c552
-rw-r--r--sound/pci/pcxhr/pcxhr.h76
-rw-r--r--sound/pci/pcxhr/pcxhr_core.c291
-rw-r--r--sound/pci/pcxhr/pcxhr_core.h5
-rw-r--r--sound/pci/pcxhr/pcxhr_hwdep.c158
-rw-r--r--sound/pci/pcxhr/pcxhr_mix22.c820
-rw-r--r--sound/pci/pcxhr/pcxhr_mix22.h56
-rw-r--r--sound/pci/pcxhr/pcxhr_mixer.c556
9 files changed, 1995 insertions, 521 deletions
diff --git a/sound/pci/pcxhr/Makefile b/sound/pci/pcxhr/Makefile
index 10473c05918d..b06128e918ca 100644
--- a/sound/pci/pcxhr/Makefile
+++ b/sound/pci/pcxhr/Makefile
@@ -1,2 +1,2 @@
1snd-pcxhr-objs := pcxhr.o pcxhr_hwdep.o pcxhr_mixer.o pcxhr_core.o 1snd-pcxhr-objs := pcxhr.o pcxhr_hwdep.o pcxhr_mixer.o pcxhr_core.o pcxhr_mix22.o
2obj-$(CONFIG_SND_PCXHR) += snd-pcxhr.o 2obj-$(CONFIG_SND_PCXHR) += snd-pcxhr.o
diff --git a/sound/pci/pcxhr/pcxhr.c b/sound/pci/pcxhr/pcxhr.c
index 471ee27e6c8a..27cf2c28d113 100644
--- a/sound/pci/pcxhr/pcxhr.c
+++ b/sound/pci/pcxhr/pcxhr.c
@@ -40,18 +40,20 @@
40#include "pcxhr_mixer.h" 40#include "pcxhr_mixer.h"
41#include "pcxhr_hwdep.h" 41#include "pcxhr_hwdep.h"
42#include "pcxhr_core.h" 42#include "pcxhr_core.h"
43#include "pcxhr_mix22.h"
43 44
44#define DRIVER_NAME "pcxhr" 45#define DRIVER_NAME "pcxhr"
45 46
46MODULE_AUTHOR("Markus Bollinger <bollinger@digigram.com>"); 47MODULE_AUTHOR("Markus Bollinger <bollinger@digigram.com>, "
48 "Marc Titinger <titinger@digigram.com>");
47MODULE_DESCRIPTION("Digigram " DRIVER_NAME " " PCXHR_DRIVER_VERSION_STRING); 49MODULE_DESCRIPTION("Digigram " DRIVER_NAME " " PCXHR_DRIVER_VERSION_STRING);
48MODULE_LICENSE("GPL"); 50MODULE_LICENSE("GPL");
49MODULE_SUPPORTED_DEVICE("{{Digigram," DRIVER_NAME "}}"); 51MODULE_SUPPORTED_DEVICE("{{Digigram," DRIVER_NAME "}}");
50 52
51static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 53static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
52static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 54static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
53static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */ 55static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */
54static int mono[SNDRV_CARDS]; /* capture in mono only */ 56static int mono[SNDRV_CARDS]; /* capture mono only */
55 57
56module_param_array(index, int, NULL, 0444); 58module_param_array(index, int, NULL, 0444);
57MODULE_PARM_DESC(index, "Index value for Digigram " DRIVER_NAME " soundcard"); 59MODULE_PARM_DESC(index, "Index value for Digigram " DRIVER_NAME " soundcard");
@@ -67,18 +69,58 @@ enum {
67 PCI_ID_PCX882HR, 69 PCI_ID_PCX882HR,
68 PCI_ID_VX881HR, 70 PCI_ID_VX881HR,
69 PCI_ID_PCX881HR, 71 PCI_ID_PCX881HR,
72 PCI_ID_VX882E,
73 PCI_ID_PCX882E,
74 PCI_ID_VX881E,
75 PCI_ID_PCX881E,
76 PCI_ID_VX1222HR,
70 PCI_ID_PCX1222HR, 77 PCI_ID_PCX1222HR,
78 PCI_ID_VX1221HR,
71 PCI_ID_PCX1221HR, 79 PCI_ID_PCX1221HR,
80 PCI_ID_VX1222E,
81 PCI_ID_PCX1222E,
82 PCI_ID_VX1221E,
83 PCI_ID_PCX1221E,
84 PCI_ID_VX222HR,
85 PCI_ID_VX222E,
86 PCI_ID_PCX22HR,
87 PCI_ID_PCX22E,
88 PCI_ID_VX222HRMIC,
89 PCI_ID_VX222E_MIC,
90 PCI_ID_PCX924HR,
91 PCI_ID_PCX924E,
92 PCI_ID_PCX924HRMIC,
93 PCI_ID_PCX924E_MIC,
72 PCI_ID_LAST 94 PCI_ID_LAST
73}; 95};
74 96
75static struct pci_device_id pcxhr_ids[] = { 97static struct pci_device_id pcxhr_ids[] = {
76 { 0x10b5, 0x9656, 0x1369, 0xb001, 0, 0, PCI_ID_VX882HR, }, /* VX882HR */ 98 { 0x10b5, 0x9656, 0x1369, 0xb001, 0, 0, PCI_ID_VX882HR, },
77 { 0x10b5, 0x9656, 0x1369, 0xb101, 0, 0, PCI_ID_PCX882HR, }, /* PCX882HR */ 99 { 0x10b5, 0x9656, 0x1369, 0xb101, 0, 0, PCI_ID_PCX882HR, },
78 { 0x10b5, 0x9656, 0x1369, 0xb201, 0, 0, PCI_ID_VX881HR, }, /* VX881HR */ 100 { 0x10b5, 0x9656, 0x1369, 0xb201, 0, 0, PCI_ID_VX881HR, },
79 { 0x10b5, 0x9656, 0x1369, 0xb301, 0, 0, PCI_ID_PCX881HR, }, /* PCX881HR */ 101 { 0x10b5, 0x9656, 0x1369, 0xb301, 0, 0, PCI_ID_PCX881HR, },
80 { 0x10b5, 0x9656, 0x1369, 0xb501, 0, 0, PCI_ID_PCX1222HR, }, /* PCX1222HR */ 102 { 0x10b5, 0x9056, 0x1369, 0xb021, 0, 0, PCI_ID_VX882E, },
81 { 0x10b5, 0x9656, 0x1369, 0xb701, 0, 0, PCI_ID_PCX1221HR, }, /* PCX1221HR */ 103 { 0x10b5, 0x9056, 0x1369, 0xb121, 0, 0, PCI_ID_PCX882E, },
104 { 0x10b5, 0x9056, 0x1369, 0xb221, 0, 0, PCI_ID_VX881E, },
105 { 0x10b5, 0x9056, 0x1369, 0xb321, 0, 0, PCI_ID_PCX881E, },
106 { 0x10b5, 0x9656, 0x1369, 0xb401, 0, 0, PCI_ID_VX1222HR, },
107 { 0x10b5, 0x9656, 0x1369, 0xb501, 0, 0, PCI_ID_PCX1222HR, },
108 { 0x10b5, 0x9656, 0x1369, 0xb601, 0, 0, PCI_ID_VX1221HR, },
109 { 0x10b5, 0x9656, 0x1369, 0xb701, 0, 0, PCI_ID_PCX1221HR, },
110 { 0x10b5, 0x9056, 0x1369, 0xb421, 0, 0, PCI_ID_VX1222E, },
111 { 0x10b5, 0x9056, 0x1369, 0xb521, 0, 0, PCI_ID_PCX1222E, },
112 { 0x10b5, 0x9056, 0x1369, 0xb621, 0, 0, PCI_ID_VX1221E, },
113 { 0x10b5, 0x9056, 0x1369, 0xb721, 0, 0, PCI_ID_PCX1221E, },
114 { 0x10b5, 0x9056, 0x1369, 0xba01, 0, 0, PCI_ID_VX222HR, },
115 { 0x10b5, 0x9056, 0x1369, 0xba21, 0, 0, PCI_ID_VX222E, },
116 { 0x10b5, 0x9056, 0x1369, 0xbd01, 0, 0, PCI_ID_PCX22HR, },
117 { 0x10b5, 0x9056, 0x1369, 0xbd21, 0, 0, PCI_ID_PCX22E, },
118 { 0x10b5, 0x9056, 0x1369, 0xbc01, 0, 0, PCI_ID_VX222HRMIC, },
119 { 0x10b5, 0x9056, 0x1369, 0xbc21, 0, 0, PCI_ID_VX222E_MIC, },
120 { 0x10b5, 0x9056, 0x1369, 0xbb01, 0, 0, PCI_ID_PCX924HR, },
121 { 0x10b5, 0x9056, 0x1369, 0xbb21, 0, 0, PCI_ID_PCX924E, },
122 { 0x10b5, 0x9056, 0x1369, 0xbf01, 0, 0, PCI_ID_PCX924HRMIC, },
123 { 0x10b5, 0x9056, 0x1369, 0xbf21, 0, 0, PCI_ID_PCX924E_MIC, },
82 { 0, } 124 { 0, }
83}; 125};
84 126
@@ -88,27 +130,55 @@ struct board_parameters {
88 char* board_name; 130 char* board_name;
89 short playback_chips; 131 short playback_chips;
90 short capture_chips; 132 short capture_chips;
133 short fw_file_set;
91 short firmware_num; 134 short firmware_num;
92}; 135};
93static struct board_parameters pcxhr_board_params[] = { 136static struct board_parameters pcxhr_board_params[] = {
94[PCI_ID_VX882HR] = { "VX882HR", 4, 4, 41, }, 137[PCI_ID_VX882HR] = { "VX882HR", 4, 4, 0, 41 },
95[PCI_ID_PCX882HR] = { "PCX882HR", 4, 4, 41, }, 138[PCI_ID_PCX882HR] = { "PCX882HR", 4, 4, 0, 41 },
96[PCI_ID_VX881HR] = { "VX881HR", 4, 4, 41, }, 139[PCI_ID_VX881HR] = { "VX881HR", 4, 4, 0, 41 },
97[PCI_ID_PCX881HR] = { "PCX881HR", 4, 4, 41, }, 140[PCI_ID_PCX881HR] = { "PCX881HR", 4, 4, 0, 41 },
98[PCI_ID_PCX1222HR] = { "PCX1222HR", 6, 1, 42, }, 141[PCI_ID_VX882E] = { "VX882e", 4, 4, 1, 41 },
99[PCI_ID_PCX1221HR] = { "PCX1221HR", 6, 1, 42, }, 142[PCI_ID_PCX882E] = { "PCX882e", 4, 4, 1, 41 },
143[PCI_ID_VX881E] = { "VX881e", 4, 4, 1, 41 },
144[PCI_ID_PCX881E] = { "PCX881e", 4, 4, 1, 41 },
145[PCI_ID_VX1222HR] = { "VX1222HR", 6, 1, 2, 42 },
146[PCI_ID_PCX1222HR] = { "PCX1222HR", 6, 1, 2, 42 },
147[PCI_ID_VX1221HR] = { "VX1221HR", 6, 1, 2, 42 },
148[PCI_ID_PCX1221HR] = { "PCX1221HR", 6, 1, 2, 42 },
149[PCI_ID_VX1222E] = { "VX1222e", 6, 1, 3, 42 },
150[PCI_ID_PCX1222E] = { "PCX1222e", 6, 1, 3, 42 },
151[PCI_ID_VX1221E] = { "VX1221e", 6, 1, 3, 42 },
152[PCI_ID_PCX1221E] = { "PCX1221e", 6, 1, 3, 42 },
153[PCI_ID_VX222HR] = { "VX222HR", 1, 1, 4, 44 },
154[PCI_ID_VX222E] = { "VX222e", 1, 1, 4, 44 },
155[PCI_ID_PCX22HR] = { "PCX22HR", 1, 0, 4, 44 },
156[PCI_ID_PCX22E] = { "PCX22e", 1, 0, 4, 44 },
157[PCI_ID_VX222HRMIC] = { "VX222HR-Mic", 1, 1, 5, 44 },
158[PCI_ID_VX222E_MIC] = { "VX222e-Mic", 1, 1, 5, 44 },
159[PCI_ID_PCX924HR] = { "PCX924HR", 1, 1, 5, 44 },
160[PCI_ID_PCX924E] = { "PCX924e", 1, 1, 5, 44 },
161[PCI_ID_PCX924HRMIC] = { "PCX924HR-Mic", 1, 1, 5, 44 },
162[PCI_ID_PCX924E_MIC] = { "PCX924e-Mic", 1, 1, 5, 44 },
100}; 163};
101 164
165/* boards without hw AES1 and SRC onboard are all using fw_file_set==4 */
166/* VX222HR, VX222e, PCX22HR and PCX22e */
167#define PCXHR_BOARD_HAS_AES1(x) (x->fw_file_set != 4)
168/* some boards do not support 192kHz on digital AES input plugs */
169#define PCXHR_BOARD_AESIN_NO_192K(x) ((x->capture_chips == 0) || \
170 (x->fw_file_set == 0) || \
171 (x->fw_file_set == 2))
102 172
103static int pcxhr_pll_freq_register(unsigned int freq, unsigned int* pllreg, 173static int pcxhr_pll_freq_register(unsigned int freq, unsigned int* pllreg,
104 unsigned int* realfreq) 174 unsigned int* realfreq)
105{ 175{
106 unsigned int reg; 176 unsigned int reg;
107 177
108 if (freq < 6900 || freq > 110250) 178 if (freq < 6900 || freq > 110000)
109 return -EINVAL; 179 return -EINVAL;
110 reg = (28224000 * 10) / freq; 180 reg = (28224000 * 2) / freq;
111 reg = (reg + 5) / 10; 181 reg = (reg - 1) / 2;
112 if (reg < 0x200) 182 if (reg < 0x200)
113 *pllreg = reg + 0x800; 183 *pllreg = reg + 0x800;
114 else if (reg < 0x400) 184 else if (reg < 0x400)
@@ -121,7 +191,7 @@ static int pcxhr_pll_freq_register(unsigned int freq, unsigned int* pllreg,
121 reg &= ~3; 191 reg &= ~3;
122 } 192 }
123 if (realfreq) 193 if (realfreq)
124 *realfreq = ((28224000 * 10) / reg + 5) / 10; 194 *realfreq = (28224000 / (reg + 1));
125 return 0; 195 return 0;
126} 196}
127 197
@@ -151,11 +221,6 @@ static int pcxhr_pll_freq_register(unsigned int freq, unsigned int* pllreg,
151#define PCXHR_FREQ_AES_3 0x03 221#define PCXHR_FREQ_AES_3 0x03
152#define PCXHR_FREQ_AES_4 0x0d 222#define PCXHR_FREQ_AES_4 0x0d
153 223
154#define PCXHR_MODIFY_CLOCK_S_BIT 0x04
155
156#define PCXHR_IRQ_TIMER_FREQ 92000
157#define PCXHR_IRQ_TIMER_PERIOD 48
158
159static int pcxhr_get_clock_reg(struct pcxhr_mgr *mgr, unsigned int rate, 224static int pcxhr_get_clock_reg(struct pcxhr_mgr *mgr, unsigned int rate,
160 unsigned int *reg, unsigned int *freq) 225 unsigned int *reg, unsigned int *freq)
161{ 226{
@@ -196,19 +261,32 @@ static int pcxhr_get_clock_reg(struct pcxhr_mgr *mgr, unsigned int rate,
196 err = pcxhr_send_msg(mgr, &rmh); 261 err = pcxhr_send_msg(mgr, &rmh);
197 if (err < 0) { 262 if (err < 0) {
198 snd_printk(KERN_ERR 263 snd_printk(KERN_ERR
199 "error CMD_ACCESS_IO_WRITE for PLL register : %x!\n", 264 "error CMD_ACCESS_IO_WRITE "
200 err ); 265 "for PLL register : %x!\n", err);
201 return err; 266 return err;
202 } 267 }
203 } 268 }
204 break; 269 break;
205 case PCXHR_CLOCK_TYPE_WORD_CLOCK : val = PCXHR_FREQ_WORD_CLOCK; break; 270 case PCXHR_CLOCK_TYPE_WORD_CLOCK:
206 case PCXHR_CLOCK_TYPE_AES_SYNC : val = PCXHR_FREQ_SYNC_AES; break; 271 val = PCXHR_FREQ_WORD_CLOCK;
207 case PCXHR_CLOCK_TYPE_AES_1 : val = PCXHR_FREQ_AES_1; break; 272 break;
208 case PCXHR_CLOCK_TYPE_AES_2 : val = PCXHR_FREQ_AES_2; break; 273 case PCXHR_CLOCK_TYPE_AES_SYNC:
209 case PCXHR_CLOCK_TYPE_AES_3 : val = PCXHR_FREQ_AES_3; break; 274 val = PCXHR_FREQ_SYNC_AES;
210 case PCXHR_CLOCK_TYPE_AES_4 : val = PCXHR_FREQ_AES_4; break; 275 break;
211 default : return -EINVAL; 276 case PCXHR_CLOCK_TYPE_AES_1:
277 val = PCXHR_FREQ_AES_1;
278 break;
279 case PCXHR_CLOCK_TYPE_AES_2:
280 val = PCXHR_FREQ_AES_2;
281 break;
282 case PCXHR_CLOCK_TYPE_AES_3:
283 val = PCXHR_FREQ_AES_3;
284 break;
285 case PCXHR_CLOCK_TYPE_AES_4:
286 val = PCXHR_FREQ_AES_4;
287 break;
288 default:
289 return -EINVAL;
212 } 290 }
213 *reg = val; 291 *reg = val;
214 *freq = realfreq; 292 *freq = realfreq;
@@ -216,14 +294,13 @@ static int pcxhr_get_clock_reg(struct pcxhr_mgr *mgr, unsigned int rate,
216} 294}
217 295
218 296
219int pcxhr_set_clock(struct pcxhr_mgr *mgr, unsigned int rate) 297static int pcxhr_sub_set_clock(struct pcxhr_mgr *mgr,
298 unsigned int rate,
299 int *changed)
220{ 300{
221 unsigned int val, realfreq, speed; 301 unsigned int val, realfreq, speed;
222 struct pcxhr_rmh rmh; 302 struct pcxhr_rmh rmh;
223 int err, changed; 303 int err;
224
225 if (rate == 0)
226 return 0; /* nothing to do */
227 304
228 err = pcxhr_get_clock_reg(mgr, rate, &val, &realfreq); 305 err = pcxhr_get_clock_reg(mgr, rate, &val, &realfreq);
229 if (err) 306 if (err)
@@ -237,13 +314,17 @@ int pcxhr_set_clock(struct pcxhr_mgr *mgr, unsigned int rate)
237 else 314 else
238 speed = 2; /* quad speed */ 315 speed = 2; /* quad speed */
239 if (mgr->codec_speed != speed) { 316 if (mgr->codec_speed != speed) {
240 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE); /* mute outputs */ 317 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE); /* mute outputs */
241 rmh.cmd[0] |= IO_NUM_REG_MUTE_OUT; 318 rmh.cmd[0] |= IO_NUM_REG_MUTE_OUT;
319 if (DSP_EXT_CMD_SET(mgr)) {
320 rmh.cmd[1] = 1;
321 rmh.cmd_len = 2;
322 }
242 err = pcxhr_send_msg(mgr, &rmh); 323 err = pcxhr_send_msg(mgr, &rmh);
243 if (err) 324 if (err)
244 return err; 325 return err;
245 326
246 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE); /* set speed ratio */ 327 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE); /* set speed ratio */
247 rmh.cmd[0] |= IO_NUM_SPEED_RATIO; 328 rmh.cmd[0] |= IO_NUM_SPEED_RATIO;
248 rmh.cmd[1] = speed; 329 rmh.cmd[1] = speed;
249 rmh.cmd_len = 2; 330 rmh.cmd_len = 2;
@@ -253,25 +334,57 @@ int pcxhr_set_clock(struct pcxhr_mgr *mgr, unsigned int rate)
253 } 334 }
254 /* set the new frequency */ 335 /* set the new frequency */
255 snd_printdd("clock register : set %x\n", val); 336 snd_printdd("clock register : set %x\n", val);
256 err = pcxhr_write_io_num_reg_cont(mgr, PCXHR_FREQ_REG_MASK, val, &changed); 337 err = pcxhr_write_io_num_reg_cont(mgr, PCXHR_FREQ_REG_MASK,
338 val, changed);
257 if (err) 339 if (err)
258 return err; 340 return err;
341
259 mgr->sample_rate_real = realfreq; 342 mgr->sample_rate_real = realfreq;
260 mgr->cur_clock_type = mgr->use_clock_type; 343 mgr->cur_clock_type = mgr->use_clock_type;
261 344
262 /* unmute after codec speed modes */ 345 /* unmute after codec speed modes */
263 if (mgr->codec_speed != speed) { 346 if (mgr->codec_speed != speed) {
264 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_READ); /* unmute outputs */ 347 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_READ); /* unmute outputs */
265 rmh.cmd[0] |= IO_NUM_REG_MUTE_OUT; 348 rmh.cmd[0] |= IO_NUM_REG_MUTE_OUT;
349 if (DSP_EXT_CMD_SET(mgr)) {
350 rmh.cmd[1] = 1;
351 rmh.cmd_len = 2;
352 }
266 err = pcxhr_send_msg(mgr, &rmh); 353 err = pcxhr_send_msg(mgr, &rmh);
267 if (err) 354 if (err)
268 return err; 355 return err;
269 mgr->codec_speed = speed; /* save new codec speed */ 356 mgr->codec_speed = speed; /* save new codec speed */
270 } 357 }
271 358
359 snd_printdd("pcxhr_sub_set_clock to %dHz (realfreq=%d)\n",
360 rate, realfreq);
361 return 0;
362}
363
364#define PCXHR_MODIFY_CLOCK_S_BIT 0x04
365
366#define PCXHR_IRQ_TIMER_FREQ 92000
367#define PCXHR_IRQ_TIMER_PERIOD 48
368
369int pcxhr_set_clock(struct pcxhr_mgr *mgr, unsigned int rate)
370{
371 struct pcxhr_rmh rmh;
372 int err, changed;
373
374 if (rate == 0)
375 return 0; /* nothing to do */
376
377 if (mgr->is_hr_stereo)
378 err = hr222_sub_set_clock(mgr, rate, &changed);
379 else
380 err = pcxhr_sub_set_clock(mgr, rate, &changed);
381
382 if (err)
383 return err;
384
272 if (changed) { 385 if (changed) {
273 pcxhr_init_rmh(&rmh, CMD_MODIFY_CLOCK); 386 pcxhr_init_rmh(&rmh, CMD_MODIFY_CLOCK);
274 rmh.cmd[0] |= PCXHR_MODIFY_CLOCK_S_BIT; /* resync fifos */ 387 rmh.cmd[0] |= PCXHR_MODIFY_CLOCK_S_BIT; /* resync fifos */
275 if (rate < PCXHR_IRQ_TIMER_FREQ) 388 if (rate < PCXHR_IRQ_TIMER_FREQ)
276 rmh.cmd[1] = PCXHR_IRQ_TIMER_PERIOD; 389 rmh.cmd[1] = PCXHR_IRQ_TIMER_PERIOD;
277 else 390 else
@@ -282,26 +395,39 @@ int pcxhr_set_clock(struct pcxhr_mgr *mgr, unsigned int rate)
282 if (err) 395 if (err)
283 return err; 396 return err;
284 } 397 }
285 snd_printdd("pcxhr_set_clock to %dHz (realfreq=%d)\n", rate, realfreq);
286 return 0; 398 return 0;
287} 399}
288 400
289 401
290int pcxhr_get_external_clock(struct pcxhr_mgr *mgr, enum pcxhr_clock_type clock_type, 402static int pcxhr_sub_get_external_clock(struct pcxhr_mgr *mgr,
291 int *sample_rate) 403 enum pcxhr_clock_type clock_type,
404 int *sample_rate)
292{ 405{
293 struct pcxhr_rmh rmh; 406 struct pcxhr_rmh rmh;
294 unsigned char reg; 407 unsigned char reg;
295 int err, rate; 408 int err, rate;
296 409
297 switch (clock_type) { 410 switch (clock_type) {
298 case PCXHR_CLOCK_TYPE_WORD_CLOCK : reg = REG_STATUS_WORD_CLOCK; break; 411 case PCXHR_CLOCK_TYPE_WORD_CLOCK:
299 case PCXHR_CLOCK_TYPE_AES_SYNC : reg = REG_STATUS_AES_SYNC; break; 412 reg = REG_STATUS_WORD_CLOCK;
300 case PCXHR_CLOCK_TYPE_AES_1 : reg = REG_STATUS_AES_1; break; 413 break;
301 case PCXHR_CLOCK_TYPE_AES_2 : reg = REG_STATUS_AES_2; break; 414 case PCXHR_CLOCK_TYPE_AES_SYNC:
302 case PCXHR_CLOCK_TYPE_AES_3 : reg = REG_STATUS_AES_3; break; 415 reg = REG_STATUS_AES_SYNC;
303 case PCXHR_CLOCK_TYPE_AES_4 : reg = REG_STATUS_AES_4; break; 416 break;
304 default : return -EINVAL; 417 case PCXHR_CLOCK_TYPE_AES_1:
418 reg = REG_STATUS_AES_1;
419 break;
420 case PCXHR_CLOCK_TYPE_AES_2:
421 reg = REG_STATUS_AES_2;
422 break;
423 case PCXHR_CLOCK_TYPE_AES_3:
424 reg = REG_STATUS_AES_3;
425 break;
426 case PCXHR_CLOCK_TYPE_AES_4:
427 reg = REG_STATUS_AES_4;
428 break;
429 default:
430 return -EINVAL;
305 } 431 }
306 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_READ); 432 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_READ);
307 rmh.cmd_len = 2; 433 rmh.cmd_len = 2;
@@ -311,7 +437,7 @@ int pcxhr_get_external_clock(struct pcxhr_mgr *mgr, enum pcxhr_clock_type clock_
311 err = pcxhr_send_msg(mgr, &rmh); 437 err = pcxhr_send_msg(mgr, &rmh);
312 if (err) 438 if (err)
313 return err; 439 return err;
314 udelay(100); /* wait minimum 2 sample_frames at 32kHz ! */ 440 udelay(100); /* wait minimum 2 sample_frames at 32kHz ! */
315 mgr->last_reg_stat = reg; 441 mgr->last_reg_stat = reg;
316 } 442 }
317 rmh.cmd[1] = REG_STATUS_CURRENT; 443 rmh.cmd[1] = REG_STATUS_CURRENT;
@@ -336,6 +462,18 @@ int pcxhr_get_external_clock(struct pcxhr_mgr *mgr, enum pcxhr_clock_type clock_
336} 462}
337 463
338 464
465int pcxhr_get_external_clock(struct pcxhr_mgr *mgr,
466 enum pcxhr_clock_type clock_type,
467 int *sample_rate)
468{
469 if (mgr->is_hr_stereo)
470 return hr222_get_external_clock(mgr, clock_type,
471 sample_rate);
472 else
473 return pcxhr_sub_get_external_clock(mgr, clock_type,
474 sample_rate);
475}
476
339/* 477/*
340 * start or stop playback/capture substream 478 * start or stop playback/capture substream
341 */ 479 */
@@ -350,7 +488,8 @@ static int pcxhr_set_stream_state(struct pcxhr_stream *stream)
350 start = 1; 488 start = 1;
351 else { 489 else {
352 if (stream->status != PCXHR_STREAM_STATUS_SCHEDULE_STOP) { 490 if (stream->status != PCXHR_STREAM_STATUS_SCHEDULE_STOP) {
353 snd_printk(KERN_ERR "ERROR pcxhr_set_stream_state CANNOT be stopped\n"); 491 snd_printk(KERN_ERR "ERROR pcxhr_set_stream_state "
492 "CANNOT be stopped\n");
354 return -EINVAL; 493 return -EINVAL;
355 } 494 }
356 start = 0; 495 start = 0;
@@ -359,11 +498,12 @@ static int pcxhr_set_stream_state(struct pcxhr_stream *stream)
359 return -EINVAL; 498 return -EINVAL;
360 499
361 stream->timer_abs_periods = 0; 500 stream->timer_abs_periods = 0;
362 stream->timer_period_frag = 0; /* reset theoretical stream pos */ 501 stream->timer_period_frag = 0; /* reset theoretical stream pos */
363 stream->timer_buf_periods = 0; 502 stream->timer_buf_periods = 0;
364 stream->timer_is_synced = 0; 503 stream->timer_is_synced = 0;
365 504
366 stream_mask = stream->pipe->is_capture ? 1 : 1<<stream->substream->number; 505 stream_mask =
506 stream->pipe->is_capture ? 1 : 1<<stream->substream->number;
367 507
368 pcxhr_init_rmh(&rmh, start ? CMD_START_STREAM : CMD_STOP_STREAM); 508 pcxhr_init_rmh(&rmh, start ? CMD_START_STREAM : CMD_STOP_STREAM);
369 pcxhr_set_pipe_cmd_params(&rmh, stream->pipe->is_capture, 509 pcxhr_set_pipe_cmd_params(&rmh, stream->pipe->is_capture,
@@ -373,8 +513,10 @@ static int pcxhr_set_stream_state(struct pcxhr_stream *stream)
373 513
374 err = pcxhr_send_msg(chip->mgr, &rmh); 514 err = pcxhr_send_msg(chip->mgr, &rmh);
375 if (err) 515 if (err)
376 snd_printk(KERN_ERR "ERROR pcxhr_set_stream_state err=%x;\n", err); 516 snd_printk(KERN_ERR "ERROR pcxhr_set_stream_state err=%x;\n",
377 stream->status = start ? PCXHR_STREAM_STATUS_STARTED : PCXHR_STREAM_STATUS_STOPPED; 517 err);
518 stream->status =
519 start ? PCXHR_STREAM_STATUS_STARTED : PCXHR_STREAM_STATUS_STOPPED;
378 return err; 520 return err;
379} 521}
380 522
@@ -399,13 +541,15 @@ static int pcxhr_set_format(struct pcxhr_stream *stream)
399 header = HEADER_FMT_BASE_LIN; 541 header = HEADER_FMT_BASE_LIN;
400 break; 542 break;
401 case SNDRV_PCM_FORMAT_S16_LE: 543 case SNDRV_PCM_FORMAT_S16_LE:
402 header = HEADER_FMT_BASE_LIN | HEADER_FMT_16BITS | HEADER_FMT_INTEL; 544 header = HEADER_FMT_BASE_LIN |
545 HEADER_FMT_16BITS | HEADER_FMT_INTEL;
403 break; 546 break;
404 case SNDRV_PCM_FORMAT_S16_BE: 547 case SNDRV_PCM_FORMAT_S16_BE:
405 header = HEADER_FMT_BASE_LIN | HEADER_FMT_16BITS; 548 header = HEADER_FMT_BASE_LIN | HEADER_FMT_16BITS;
406 break; 549 break;
407 case SNDRV_PCM_FORMAT_S24_3LE: 550 case SNDRV_PCM_FORMAT_S24_3LE:
408 header = HEADER_FMT_BASE_LIN | HEADER_FMT_24BITS | HEADER_FMT_INTEL; 551 header = HEADER_FMT_BASE_LIN |
552 HEADER_FMT_24BITS | HEADER_FMT_INTEL;
409 break; 553 break;
410 case SNDRV_PCM_FORMAT_S24_3BE: 554 case SNDRV_PCM_FORMAT_S24_3BE:
411 header = HEADER_FMT_BASE_LIN | HEADER_FMT_24BITS; 555 header = HEADER_FMT_BASE_LIN | HEADER_FMT_24BITS;
@@ -414,7 +558,8 @@ static int pcxhr_set_format(struct pcxhr_stream *stream)
414 header = HEADER_FMT_BASE_FLOAT | HEADER_FMT_INTEL; 558 header = HEADER_FMT_BASE_FLOAT | HEADER_FMT_INTEL;
415 break; 559 break;
416 default: 560 default:
417 snd_printk(KERN_ERR "error pcxhr_set_format() : unknown format\n"); 561 snd_printk(KERN_ERR
562 "error pcxhr_set_format() : unknown format\n");
418 return -EINVAL; 563 return -EINVAL;
419 } 564 }
420 chip = snd_pcm_substream_chip(stream->substream); 565 chip = snd_pcm_substream_chip(stream->substream);
@@ -432,14 +577,31 @@ static int pcxhr_set_format(struct pcxhr_stream *stream)
432 is_capture = stream->pipe->is_capture; 577 is_capture = stream->pipe->is_capture;
433 stream_num = is_capture ? 0 : stream->substream->number; 578 stream_num = is_capture ? 0 : stream->substream->number;
434 579
435 pcxhr_init_rmh(&rmh, is_capture ? CMD_FORMAT_STREAM_IN : CMD_FORMAT_STREAM_OUT); 580 pcxhr_init_rmh(&rmh, is_capture ?
436 pcxhr_set_pipe_cmd_params(&rmh, is_capture, stream->pipe->first_audio, stream_num, 0); 581 CMD_FORMAT_STREAM_IN : CMD_FORMAT_STREAM_OUT);
437 if (is_capture) 582 pcxhr_set_pipe_cmd_params(&rmh, is_capture, stream->pipe->first_audio,
438 rmh.cmd[0] |= 1<<12; 583 stream_num, 0);
584 if (is_capture) {
585 /* bug with old dsp versions: */
586 /* bit 12 also sets the format of the playback stream */
587 if (DSP_EXT_CMD_SET(chip->mgr))
588 rmh.cmd[0] |= 1<<10;
589 else
590 rmh.cmd[0] |= 1<<12;
591 }
439 rmh.cmd[1] = 0; 592 rmh.cmd[1] = 0;
440 rmh.cmd[2] = header >> 8; 593 rmh.cmd_len = 2;
441 rmh.cmd[3] = (header & 0xff) << 16; 594 if (DSP_EXT_CMD_SET(chip->mgr)) {
442 rmh.cmd_len = 4; 595 /* add channels and set bit 19 if channels>2 */
596 rmh.cmd[1] = stream->channels;
597 if (!is_capture) {
598 /* playback : add channel mask to command */
599 rmh.cmd[2] = (stream->channels == 1) ? 0x01 : 0x03;
600 rmh.cmd_len = 3;
601 }
602 }
603 rmh.cmd[rmh.cmd_len++] = header >> 8;
604 rmh.cmd[rmh.cmd_len++] = (header & 0xff) << 16;
443 err = pcxhr_send_msg(chip->mgr, &rmh); 605 err = pcxhr_send_msg(chip->mgr, &rmh);
444 if (err) 606 if (err)
445 snd_printk(KERN_ERR "ERROR pcxhr_set_format err=%x;\n", err); 607 snd_printk(KERN_ERR "ERROR pcxhr_set_format err=%x;\n", err);
@@ -456,30 +618,38 @@ static int pcxhr_update_r_buffer(struct pcxhr_stream *stream)
456 is_capture = (subs->stream == SNDRV_PCM_STREAM_CAPTURE); 618 is_capture = (subs->stream == SNDRV_PCM_STREAM_CAPTURE);
457 stream_num = is_capture ? 0 : subs->number; 619 stream_num = is_capture ? 0 : subs->number;
458 620
459 snd_printdd("pcxhr_update_r_buffer(pcm%c%d) : addr(%p) bytes(%zx) subs(%d)\n", 621 snd_printdd("pcxhr_update_r_buffer(pcm%c%d) : "
622 "addr(%p) bytes(%zx) subs(%d)\n",
460 is_capture ? 'c' : 'p', 623 is_capture ? 'c' : 'p',
461 chip->chip_idx, (void *)(long)subs->runtime->dma_addr, 624 chip->chip_idx, (void *)(long)subs->runtime->dma_addr,
462 subs->runtime->dma_bytes, subs->number); 625 subs->runtime->dma_bytes, subs->number);
463 626
464 pcxhr_init_rmh(&rmh, CMD_UPDATE_R_BUFFERS); 627 pcxhr_init_rmh(&rmh, CMD_UPDATE_R_BUFFERS);
465 pcxhr_set_pipe_cmd_params(&rmh, is_capture, stream->pipe->first_audio, stream_num, 0); 628 pcxhr_set_pipe_cmd_params(&rmh, is_capture, stream->pipe->first_audio,
629 stream_num, 0);
466 630
467 /* max buffer size is 2 MByte */ 631 /* max buffer size is 2 MByte */
468 snd_BUG_ON(subs->runtime->dma_bytes >= 0x200000); 632 snd_BUG_ON(subs->runtime->dma_bytes >= 0x200000);
469 rmh.cmd[1] = subs->runtime->dma_bytes * 8; /* size in bits */ 633 /* size in bits */
470 rmh.cmd[2] = subs->runtime->dma_addr >> 24; /* most significant byte */ 634 rmh.cmd[1] = subs->runtime->dma_bytes * 8;
471 rmh.cmd[2] |= 1<<19; /* this is a circular buffer */ 635 /* most significant byte */
472 rmh.cmd[3] = subs->runtime->dma_addr & MASK_DSP_WORD; /* least 3 significant bytes */ 636 rmh.cmd[2] = subs->runtime->dma_addr >> 24;
637 /* this is a circular buffer */
638 rmh.cmd[2] |= 1<<19;
639 /* least 3 significant bytes */
640 rmh.cmd[3] = subs->runtime->dma_addr & MASK_DSP_WORD;
473 rmh.cmd_len = 4; 641 rmh.cmd_len = 4;
474 err = pcxhr_send_msg(chip->mgr, &rmh); 642 err = pcxhr_send_msg(chip->mgr, &rmh);
475 if (err) 643 if (err)
476 snd_printk(KERN_ERR "ERROR CMD_UPDATE_R_BUFFERS err=%x;\n", err); 644 snd_printk(KERN_ERR
645 "ERROR CMD_UPDATE_R_BUFFERS err=%x;\n", err);
477 return err; 646 return err;
478} 647}
479 648
480 649
481#if 0 650#if 0
482static int pcxhr_pipe_sample_count(struct pcxhr_stream *stream, snd_pcm_uframes_t *sample_count) 651static int pcxhr_pipe_sample_count(struct pcxhr_stream *stream,
652 snd_pcm_uframes_t *sample_count)
483{ 653{
484 struct pcxhr_rmh rmh; 654 struct pcxhr_rmh rmh;
485 int err; 655 int err;
@@ -533,8 +703,8 @@ static void pcxhr_trigger_tasklet(unsigned long arg)
533 for (j = 0; j < chip->nb_streams_play; j++) { 703 for (j = 0; j < chip->nb_streams_play; j++) {
534 if (pcxhr_stream_scheduled_get_pipe(&chip->playback_stream[j], &pipe)) { 704 if (pcxhr_stream_scheduled_get_pipe(&chip->playback_stream[j], &pipe)) {
535 playback_mask |= (1 << pipe->first_audio); 705 playback_mask |= (1 << pipe->first_audio);
536 break; /* add only once, as all playback streams of 706 break; /* add only once, as all playback
537 * one chip use the same pipe 707 * streams of one chip use the same pipe
538 */ 708 */
539 } 709 }
540 } 710 }
@@ -545,19 +715,21 @@ static void pcxhr_trigger_tasklet(unsigned long arg)
545 return; 715 return;
546 } 716 }
547 717
548 snd_printdd("pcxhr_trigger_tasklet : playback_mask=%x capture_mask=%x\n", 718 snd_printdd("pcxhr_trigger_tasklet : "
719 "playback_mask=%x capture_mask=%x\n",
549 playback_mask, capture_mask); 720 playback_mask, capture_mask);
550 721
551 /* synchronous stop of all the pipes concerned */ 722 /* synchronous stop of all the pipes concerned */
552 err = pcxhr_set_pipe_state(mgr, playback_mask, capture_mask, 0); 723 err = pcxhr_set_pipe_state(mgr, playback_mask, capture_mask, 0);
553 if (err) { 724 if (err) {
554 mutex_unlock(&mgr->setup_mutex); 725 mutex_unlock(&mgr->setup_mutex);
555 snd_printk(KERN_ERR "pcxhr_trigger_tasklet : error stop pipes (P%x C%x)\n", 726 snd_printk(KERN_ERR "pcxhr_trigger_tasklet : "
727 "error stop pipes (P%x C%x)\n",
556 playback_mask, capture_mask); 728 playback_mask, capture_mask);
557 return; 729 return;
558 } 730 }
559 731
560 /* unfortunately the dsp lost format and buffer info with the stop pipe */ 732 /* the dsp lost format and buffer info with the stop pipe */
561 for (i = 0; i < mgr->num_cards; i++) { 733 for (i = 0; i < mgr->num_cards; i++) {
562 struct pcxhr_stream *stream; 734 struct pcxhr_stream *stream;
563 chip = mgr->chip[i]; 735 chip = mgr->chip[i];
@@ -596,12 +768,15 @@ static void pcxhr_trigger_tasklet(unsigned long arg)
596 err = pcxhr_set_pipe_state(mgr, playback_mask, capture_mask, 1); 768 err = pcxhr_set_pipe_state(mgr, playback_mask, capture_mask, 1);
597 if (err) { 769 if (err) {
598 mutex_unlock(&mgr->setup_mutex); 770 mutex_unlock(&mgr->setup_mutex);
599 snd_printk(KERN_ERR "pcxhr_trigger_tasklet : error start pipes (P%x C%x)\n", 771 snd_printk(KERN_ERR "pcxhr_trigger_tasklet : "
772 "error start pipes (P%x C%x)\n",
600 playback_mask, capture_mask); 773 playback_mask, capture_mask);
601 return; 774 return;
602 } 775 }
603 776
604 /* put the streams into the running state now (increment pointer by interrupt) */ 777 /* put the streams into the running state now
778 * (increment pointer by interrupt)
779 */
605 spin_lock_irqsave(&mgr->lock, flags); 780 spin_lock_irqsave(&mgr->lock, flags);
606 for ( i =0; i < mgr->num_cards; i++) { 781 for ( i =0; i < mgr->num_cards; i++) {
607 struct pcxhr_stream *stream; 782 struct pcxhr_stream *stream;
@@ -615,7 +790,7 @@ static void pcxhr_trigger_tasklet(unsigned long arg)
615 stream = &chip->playback_stream[j]; 790 stream = &chip->playback_stream[j];
616 if (stream->status == PCXHR_STREAM_STATUS_STARTED) { 791 if (stream->status == PCXHR_STREAM_STATUS_STARTED) {
617 /* playback will already have advanced ! */ 792 /* playback will already have advanced ! */
618 stream->timer_period_frag += PCXHR_GRANULARITY; 793 stream->timer_period_frag += mgr->granularity;
619 stream->status = PCXHR_STREAM_STATUS_RUNNING; 794 stream->status = PCXHR_STREAM_STATUS_RUNNING;
620 } 795 }
621 } 796 }
@@ -697,12 +872,14 @@ static int pcxhr_hardware_timer(struct pcxhr_mgr *mgr, int start)
697 872
698 pcxhr_init_rmh(&rmh, CMD_SET_TIMER_INTERRUPT); 873 pcxhr_init_rmh(&rmh, CMD_SET_TIMER_INTERRUPT);
699 if (start) { 874 if (start) {
700 mgr->dsp_time_last = PCXHR_DSP_TIME_INVALID; /* last dsp time invalid */ 875 /* last dsp time invalid */
701 rmh.cmd[0] |= PCXHR_GRANULARITY; 876 mgr->dsp_time_last = PCXHR_DSP_TIME_INVALID;
877 rmh.cmd[0] |= mgr->granularity;
702 } 878 }
703 err = pcxhr_send_msg(mgr, &rmh); 879 err = pcxhr_send_msg(mgr, &rmh);
704 if (err < 0) 880 if (err < 0)
705 snd_printk(KERN_ERR "error pcxhr_hardware_timer err(%x)\n", err); 881 snd_printk(KERN_ERR "error pcxhr_hardware_timer err(%x)\n",
882 err);
706 return err; 883 return err;
707} 884}
708 885
@@ -713,38 +890,16 @@ static int pcxhr_prepare(struct snd_pcm_substream *subs)
713{ 890{
714 struct snd_pcxhr *chip = snd_pcm_substream_chip(subs); 891 struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
715 struct pcxhr_mgr *mgr = chip->mgr; 892 struct pcxhr_mgr *mgr = chip->mgr;
716 /*
717 struct pcxhr_stream *stream = (pcxhr_stream_t*)subs->runtime->private_data;
718 */
719 int err = 0; 893 int err = 0;
720 894
721 snd_printdd("pcxhr_prepare : period_size(%lx) periods(%x) buffer_size(%lx)\n", 895 snd_printdd("pcxhr_prepare : period_size(%lx) periods(%x) buffer_size(%lx)\n",
722 subs->runtime->period_size, subs->runtime->periods, 896 subs->runtime->period_size, subs->runtime->periods,
723 subs->runtime->buffer_size); 897 subs->runtime->buffer_size);
724 898
725 /*
726 if(subs->runtime->period_size <= PCXHR_GRANULARITY) {
727 snd_printk(KERN_ERR "pcxhr_prepare : error period_size too small (%x)\n",
728 (unsigned int)subs->runtime->period_size);
729 return -EINVAL;
730 }
731 */
732
733 mutex_lock(&mgr->setup_mutex); 899 mutex_lock(&mgr->setup_mutex);
734 900
735 do { 901 do {
736 /* if the stream was stopped before, format and buffer were reset */
737 /*
738 if(stream->status == PCXHR_STREAM_STATUS_STOPPED) {
739 err = pcxhr_set_format(stream);
740 if(err) break;
741 err = pcxhr_update_r_buffer(stream);
742 if(err) break;
743 }
744 */
745
746 /* only the first stream can choose the sample rate */ 902 /* only the first stream can choose the sample rate */
747 /* the further opened streams will be limited to its frequency (see open) */
748 /* set the clock only once (first stream) */ 903 /* set the clock only once (first stream) */
749 if (mgr->sample_rate != subs->runtime->rate) { 904 if (mgr->sample_rate != subs->runtime->rate) {
750 err = pcxhr_set_clock(mgr, subs->runtime->rate); 905 err = pcxhr_set_clock(mgr, subs->runtime->rate);
@@ -787,22 +942,9 @@ static int pcxhr_hw_params(struct snd_pcm_substream *subs,
787 stream->channels = channels; 942 stream->channels = channels;
788 stream->format = format; 943 stream->format = format;
789 944
790 /* set the format to the board */
791 /*
792 err = pcxhr_set_format(stream);
793 if(err) {
794 mutex_unlock(&mgr->setup_mutex);
795 return err;
796 }
797 */
798 /* allocate buffer */ 945 /* allocate buffer */
799 err = snd_pcm_lib_malloc_pages(subs, params_buffer_bytes(hw)); 946 err = snd_pcm_lib_malloc_pages(subs, params_buffer_bytes(hw));
800 947
801 /*
802 if (err > 0) {
803 err = pcxhr_update_r_buffer(stream);
804 }
805 */
806 mutex_unlock(&mgr->setup_mutex); 948 mutex_unlock(&mgr->setup_mutex);
807 949
808 return err; 950 return err;
@@ -820,14 +962,18 @@ static int pcxhr_hw_free(struct snd_pcm_substream *subs)
820 */ 962 */
821static struct snd_pcm_hardware pcxhr_caps = 963static struct snd_pcm_hardware pcxhr_caps =
822{ 964{
823 .info = ( SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 965 .info = (SNDRV_PCM_INFO_MMAP |
824 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START | 966 SNDRV_PCM_INFO_INTERLEAVED |
825 0 /*SNDRV_PCM_INFO_PAUSE*/), 967 SNDRV_PCM_INFO_MMAP_VALID |
826 .formats = ( SNDRV_PCM_FMTBIT_U8 | 968 SNDRV_PCM_INFO_SYNC_START),
827 SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE | 969 .formats = (SNDRV_PCM_FMTBIT_U8 |
828 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_3BE | 970 SNDRV_PCM_FMTBIT_S16_LE |
829 SNDRV_PCM_FMTBIT_FLOAT_LE ), 971 SNDRV_PCM_FMTBIT_S16_BE |
830 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_192000, 972 SNDRV_PCM_FMTBIT_S24_3LE |
973 SNDRV_PCM_FMTBIT_S24_3BE |
974 SNDRV_PCM_FMTBIT_FLOAT_LE),
975 .rates = (SNDRV_PCM_RATE_CONTINUOUS |
976 SNDRV_PCM_RATE_8000_192000),
831 .rate_min = 8000, 977 .rate_min = 8000,
832 .rate_max = 192000, 978 .rate_max = 192000,
833 .channels_min = 1, 979 .channels_min = 1,
@@ -847,6 +993,7 @@ static int pcxhr_open(struct snd_pcm_substream *subs)
847 struct pcxhr_mgr *mgr = chip->mgr; 993 struct pcxhr_mgr *mgr = chip->mgr;
848 struct snd_pcm_runtime *runtime = subs->runtime; 994 struct snd_pcm_runtime *runtime = subs->runtime;
849 struct pcxhr_stream *stream; 995 struct pcxhr_stream *stream;
996 int err;
850 997
851 mutex_lock(&mgr->setup_mutex); 998 mutex_lock(&mgr->setup_mutex);
852 999
@@ -874,6 +1021,18 @@ static int pcxhr_open(struct snd_pcm_substream *subs)
874 return -EBUSY; 1021 return -EBUSY;
875 } 1022 }
876 1023
1024 /* float format support is in some cases buggy on stereo cards */
1025 if (mgr->is_hr_stereo)
1026 runtime->hw.formats &= ~SNDRV_PCM_FMTBIT_FLOAT_LE;
1027
1028 /* buffer-size should better be multiple of period-size */
1029 err = snd_pcm_hw_constraint_integer(runtime,
1030 SNDRV_PCM_HW_PARAM_PERIODS);
1031 if (err < 0) {
1032 mutex_unlock(&mgr->setup_mutex);
1033 return err;
1034 }
1035
877 /* if a sample rate is already used or fixed by external clock, 1036 /* if a sample rate is already used or fixed by external clock,
878 * the stream cannot change 1037 * the stream cannot change
879 */ 1038 */
@@ -889,7 +1048,8 @@ static int pcxhr_open(struct snd_pcm_substream *subs)
889 mutex_unlock(&mgr->setup_mutex); 1048 mutex_unlock(&mgr->setup_mutex);
890 return -EBUSY; 1049 return -EBUSY;
891 } 1050 }
892 runtime->hw.rate_min = runtime->hw.rate_max = external_rate; 1051 runtime->hw.rate_min = external_rate;
1052 runtime->hw.rate_max = external_rate;
893 } 1053 }
894 } 1054 }
895 1055
@@ -899,9 +1059,11 @@ static int pcxhr_open(struct snd_pcm_substream *subs)
899 1059
900 runtime->private_data = stream; 1060 runtime->private_data = stream;
901 1061
902 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 4); 1062 /* better get a divisor of granularity values (96 or 192) */
903 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 4); 1063 snd_pcm_hw_constraint_step(runtime, 0,
904 1064 SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 32);
1065 snd_pcm_hw_constraint_step(runtime, 0,
1066 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 32);
905 snd_pcm_set_sync(subs); 1067 snd_pcm_set_sync(subs);
906 1068
907 mgr->ref_count_rate++; 1069 mgr->ref_count_rate++;
@@ -919,11 +1081,12 @@ static int pcxhr_close(struct snd_pcm_substream *subs)
919 1081
920 mutex_lock(&mgr->setup_mutex); 1082 mutex_lock(&mgr->setup_mutex);
921 1083
922 snd_printdd("pcxhr_close chip%d subs%d\n", chip->chip_idx, subs->number); 1084 snd_printdd("pcxhr_close chip%d subs%d\n",
1085 chip->chip_idx, subs->number);
923 1086
924 /* sample rate released */ 1087 /* sample rate released */
925 if (--mgr->ref_count_rate == 0) { 1088 if (--mgr->ref_count_rate == 0) {
926 mgr->sample_rate = 0; /* the sample rate is no more locked */ 1089 mgr->sample_rate = 0; /* the sample rate is no more locked */
927 pcxhr_hardware_timer(mgr, 0); /* stop the DSP-timer */ 1090 pcxhr_hardware_timer(mgr, 0); /* stop the DSP-timer */
928 } 1091 }
929 1092
@@ -1016,7 +1179,8 @@ static int pcxhr_chip_dev_free(struct snd_device *device)
1016 1179
1017/* 1180/*
1018 */ 1181 */
1019static int __devinit pcxhr_create(struct pcxhr_mgr *mgr, struct snd_card *card, int idx) 1182static int __devinit pcxhr_create(struct pcxhr_mgr *mgr,
1183 struct snd_card *card, int idx)
1020{ 1184{
1021 int err; 1185 int err;
1022 struct snd_pcxhr *chip; 1186 struct snd_pcxhr *chip;
@@ -1040,7 +1204,7 @@ static int __devinit pcxhr_create(struct pcxhr_mgr *mgr, struct snd_card *card,
1040 1204
1041 if (idx < mgr->capture_chips) { 1205 if (idx < mgr->capture_chips) {
1042 if (mgr->mono_capture) 1206 if (mgr->mono_capture)
1043 chip->nb_streams_capt = 2; /* 2 mono streams (left+right) */ 1207 chip->nb_streams_capt = 2; /* 2 mono streams */
1044 else 1208 else
1045 chip->nb_streams_capt = 1; /* or 1 stereo stream */ 1209 chip->nb_streams_capt = 1; /* or 1 stereo stream */
1046 } 1210 }
@@ -1057,7 +1221,8 @@ static int __devinit pcxhr_create(struct pcxhr_mgr *mgr, struct snd_card *card,
1057} 1221}
1058 1222
1059/* proc interface */ 1223/* proc interface */
1060static void pcxhr_proc_info(struct snd_info_entry *entry, struct snd_info_buffer *buffer) 1224static void pcxhr_proc_info(struct snd_info_entry *entry,
1225 struct snd_info_buffer *buffer)
1061{ 1226{
1062 struct snd_pcxhr *chip = entry->private_data; 1227 struct snd_pcxhr *chip = entry->private_data;
1063 struct pcxhr_mgr *mgr = chip->mgr; 1228 struct pcxhr_mgr *mgr = chip->mgr;
@@ -1070,8 +1235,10 @@ static void pcxhr_proc_info(struct snd_info_entry *entry, struct snd_info_buffer
1070 short ver_maj = (mgr->dsp_version >> 16) & 0xff; 1235 short ver_maj = (mgr->dsp_version >> 16) & 0xff;
1071 short ver_min = (mgr->dsp_version >> 8) & 0xff; 1236 short ver_min = (mgr->dsp_version >> 8) & 0xff;
1072 short ver_build = mgr->dsp_version & 0xff; 1237 short ver_build = mgr->dsp_version & 0xff;
1073 snd_iprintf(buffer, "module version %s\n", PCXHR_DRIVER_VERSION_STRING); 1238 snd_iprintf(buffer, "module version %s\n",
1074 snd_iprintf(buffer, "dsp version %d.%d.%d\n", ver_maj, ver_min, ver_build); 1239 PCXHR_DRIVER_VERSION_STRING);
1240 snd_iprintf(buffer, "dsp version %d.%d.%d\n",
1241 ver_maj, ver_min, ver_build);
1075 if (mgr->board_has_analog) 1242 if (mgr->board_has_analog)
1076 snd_iprintf(buffer, "analog io available\n"); 1243 snd_iprintf(buffer, "analog io available\n");
1077 else 1244 else
@@ -1085,18 +1252,22 @@ static void pcxhr_proc_info(struct snd_info_entry *entry, struct snd_info_buffer
1085 if (ref > 0) { 1252 if (ref > 0) {
1086 if (mgr->sample_rate_real != 0 && 1253 if (mgr->sample_rate_real != 0 &&
1087 mgr->sample_rate_real != 48000) { 1254 mgr->sample_rate_real != 48000) {
1088 ref = (ref * 48000) / mgr->sample_rate_real; 1255 ref = (ref * 48000) /
1089 if (mgr->sample_rate_real >= PCXHR_IRQ_TIMER_FREQ) 1256 mgr->sample_rate_real;
1257 if (mgr->sample_rate_real >=
1258 PCXHR_IRQ_TIMER_FREQ)
1090 ref *= 2; 1259 ref *= 2;
1091 } 1260 }
1092 cur = 100 - (100 * cur) / ref; 1261 cur = 100 - (100 * cur) / ref;
1093 snd_iprintf(buffer, "cpu load %d%%\n", cur); 1262 snd_iprintf(buffer, "cpu load %d%%\n", cur);
1094 snd_iprintf(buffer, "buffer pool %d/%d kWords\n", 1263 snd_iprintf(buffer, "buffer pool %d/%d\n",
1095 rmh.stat[2], rmh.stat[3]); 1264 rmh.stat[2], rmh.stat[3]);
1096 } 1265 }
1097 } 1266 }
1098 snd_iprintf(buffer, "dma granularity : %d\n", PCXHR_GRANULARITY); 1267 snd_iprintf(buffer, "dma granularity : %d\n",
1099 snd_iprintf(buffer, "dsp time errors : %d\n", mgr->dsp_time_err); 1268 mgr->granularity);
1269 snd_iprintf(buffer, "dsp time errors : %d\n",
1270 mgr->dsp_time_err);
1100 snd_iprintf(buffer, "dsp async pipe xrun errors : %d\n", 1271 snd_iprintf(buffer, "dsp async pipe xrun errors : %d\n",
1101 mgr->async_err_pipe_xrun); 1272 mgr->async_err_pipe_xrun);
1102 snd_iprintf(buffer, "dsp async stream xrun errors : %d\n", 1273 snd_iprintf(buffer, "dsp async stream xrun errors : %d\n",
@@ -1111,33 +1282,52 @@ static void pcxhr_proc_info(struct snd_info_entry *entry, struct snd_info_buffer
1111 rmh.cmd_idx = CMD_LAST_INDEX; 1282 rmh.cmd_idx = CMD_LAST_INDEX;
1112 if( ! pcxhr_send_msg(mgr, &rmh) ) { 1283 if( ! pcxhr_send_msg(mgr, &rmh) ) {
1113 int i; 1284 int i;
1285 if (rmh.stat_len > 8)
1286 rmh.stat_len = 8;
1114 for (i = 0; i < rmh.stat_len; i++) 1287 for (i = 0; i < rmh.stat_len; i++)
1115 snd_iprintf(buffer, "debug[%02d] = %06x\n", i, rmh.stat[i]); 1288 snd_iprintf(buffer, "debug[%02d] = %06x\n",
1289 i, rmh.stat[i]);
1116 } 1290 }
1117 } else 1291 } else
1118 snd_iprintf(buffer, "no firmware loaded\n"); 1292 snd_iprintf(buffer, "no firmware loaded\n");
1119 snd_iprintf(buffer, "\n"); 1293 snd_iprintf(buffer, "\n");
1120} 1294}
1121static void pcxhr_proc_sync(struct snd_info_entry *entry, struct snd_info_buffer *buffer) 1295static void pcxhr_proc_sync(struct snd_info_entry *entry,
1296 struct snd_info_buffer *buffer)
1122{ 1297{
1123 struct snd_pcxhr *chip = entry->private_data; 1298 struct snd_pcxhr *chip = entry->private_data;
1124 struct pcxhr_mgr *mgr = chip->mgr; 1299 struct pcxhr_mgr *mgr = chip->mgr;
1125 static char *texts[7] = { 1300 static const char *textsHR22[3] = {
1126 "Internal", "Word", "AES Sync", "AES 1", "AES 2", "AES 3", "AES 4" 1301 "Internal", "AES Sync", "AES 1"
1302 };
1303 static const char *textsPCXHR[7] = {
1304 "Internal", "Word", "AES Sync",
1305 "AES 1", "AES 2", "AES 3", "AES 4"
1127 }; 1306 };
1307 const char **texts;
1308 int max_clock;
1309 if (mgr->is_hr_stereo) {
1310 texts = textsHR22;
1311 max_clock = HR22_CLOCK_TYPE_MAX;
1312 } else {
1313 texts = textsPCXHR;
1314 max_clock = PCXHR_CLOCK_TYPE_MAX;
1315 }
1128 1316
1129 snd_iprintf(buffer, "\n%s\n", mgr->longname); 1317 snd_iprintf(buffer, "\n%s\n", mgr->longname);
1130 snd_iprintf(buffer, "Current Sample Clock\t: %s\n", texts[mgr->cur_clock_type]); 1318 snd_iprintf(buffer, "Current Sample Clock\t: %s\n",
1131 snd_iprintf(buffer, "Current Sample Rate\t= %d\n", mgr->sample_rate_real); 1319 texts[mgr->cur_clock_type]);
1132 1320 snd_iprintf(buffer, "Current Sample Rate\t= %d\n",
1321 mgr->sample_rate_real);
1133 /* commands available when embedded DSP is running */ 1322 /* commands available when embedded DSP is running */
1134 if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)) { 1323 if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)) {
1135 int i, err, sample_rate; 1324 int i, err, sample_rate;
1136 for (i = PCXHR_CLOCK_TYPE_WORD_CLOCK; i< (3 + mgr->capture_chips); i++) { 1325 for (i = 1; i <= max_clock; i++) {
1137 err = pcxhr_get_external_clock(mgr, i, &sample_rate); 1326 err = pcxhr_get_external_clock(mgr, i, &sample_rate);
1138 if (err) 1327 if (err)
1139 break; 1328 break;
1140 snd_iprintf(buffer, "%s Clock\t\t= %d\n", texts[i], sample_rate); 1329 snd_iprintf(buffer, "%s Clock\t\t= %d\n",
1330 texts[i], sample_rate);
1141 } 1331 }
1142 } else 1332 } else
1143 snd_iprintf(buffer, "no firmware loaded\n"); 1333 snd_iprintf(buffer, "no firmware loaded\n");
@@ -1195,7 +1385,8 @@ static int pcxhr_free(struct pcxhr_mgr *mgr)
1195/* 1385/*
1196 * probe function - creates the card manager 1386 * probe function - creates the card manager
1197 */ 1387 */
1198static int __devinit pcxhr_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) 1388static int __devinit pcxhr_probe(struct pci_dev *pci,
1389 const struct pci_device_id *pci_id)
1199{ 1390{
1200 static int dev; 1391 static int dev;
1201 struct pcxhr_mgr *mgr; 1392 struct pcxhr_mgr *mgr;
@@ -1218,7 +1409,8 @@ static int __devinit pcxhr_probe(struct pci_dev *pci, const struct pci_device_id
1218 1409
1219 /* check if we can restrict PCI DMA transfers to 32 bits */ 1410 /* check if we can restrict PCI DMA transfers to 32 bits */
1220 if (pci_set_dma_mask(pci, DMA_32BIT_MASK) < 0) { 1411 if (pci_set_dma_mask(pci, DMA_32BIT_MASK) < 0) {
1221 snd_printk(KERN_ERR "architecture does not support 32bit PCI busmaster DMA\n"); 1412 snd_printk(KERN_ERR "architecture does not support "
1413 "32bit PCI busmaster DMA\n");
1222 pci_disable_device(pci); 1414 pci_disable_device(pci);
1223 return -ENXIO; 1415 return -ENXIO;
1224 } 1416 }
@@ -1235,11 +1427,25 @@ static int __devinit pcxhr_probe(struct pci_dev *pci, const struct pci_device_id
1235 pci_disable_device(pci); 1427 pci_disable_device(pci);
1236 return -ENODEV; 1428 return -ENODEV;
1237 } 1429 }
1238 card_name = pcxhr_board_params[pci_id->driver_data].board_name; 1430 card_name =
1239 mgr->playback_chips = pcxhr_board_params[pci_id->driver_data].playback_chips; 1431 pcxhr_board_params[pci_id->driver_data].board_name;
1240 mgr->capture_chips = pcxhr_board_params[pci_id->driver_data].capture_chips; 1432 mgr->playback_chips =
1241 mgr->firmware_num = pcxhr_board_params[pci_id->driver_data].firmware_num; 1433 pcxhr_board_params[pci_id->driver_data].playback_chips;
1434 mgr->capture_chips =
1435 pcxhr_board_params[pci_id->driver_data].capture_chips;
1436 mgr->fw_file_set =
1437 pcxhr_board_params[pci_id->driver_data].fw_file_set;
1438 mgr->firmware_num =
1439 pcxhr_board_params[pci_id->driver_data].firmware_num;
1242 mgr->mono_capture = mono[dev]; 1440 mgr->mono_capture = mono[dev];
1441 mgr->is_hr_stereo = (mgr->playback_chips == 1);
1442 mgr->board_has_aes1 = PCXHR_BOARD_HAS_AES1(mgr);
1443 mgr->board_aes_in_192k = !PCXHR_BOARD_AESIN_NO_192K(mgr);
1444
1445 if (mgr->is_hr_stereo)
1446 mgr->granularity = PCXHR_GRANULARITY_HR22;
1447 else
1448 mgr->granularity = PCXHR_GRANULARITY;
1243 1449
1244 /* resource assignment */ 1450 /* resource assignment */
1245 if ((err = pci_request_regions(pci, card_name)) < 0) { 1451 if ((err = pci_request_regions(pci, card_name)) < 0) {
@@ -1262,7 +1468,8 @@ static int __devinit pcxhr_probe(struct pci_dev *pci, const struct pci_device_id
1262 mgr->irq = pci->irq; 1468 mgr->irq = pci->irq;
1263 1469
1264 sprintf(mgr->shortname, "Digigram %s", card_name); 1470 sprintf(mgr->shortname, "Digigram %s", card_name);
1265 sprintf(mgr->longname, "%s at 0x%lx & 0x%lx, 0x%lx irq %i", mgr->shortname, 1471 sprintf(mgr->longname, "%s at 0x%lx & 0x%lx, 0x%lx irq %i",
1472 mgr->shortname,
1266 mgr->port[0], mgr->port[1], mgr->port[2], mgr->irq); 1473 mgr->port[0], mgr->port[1], mgr->port[2], mgr->irq);
1267 1474
1268 /* ISR spinlock */ 1475 /* ISR spinlock */
@@ -1273,10 +1480,14 @@ static int __devinit pcxhr_probe(struct pci_dev *pci, const struct pci_device_id
1273 mutex_init(&mgr->setup_mutex); 1480 mutex_init(&mgr->setup_mutex);
1274 1481
1275 /* init taslket */ 1482 /* init taslket */
1276 tasklet_init(&mgr->msg_taskq, pcxhr_msg_tasklet, (unsigned long) mgr); 1483 tasklet_init(&mgr->msg_taskq, pcxhr_msg_tasklet,
1277 tasklet_init(&mgr->trigger_taskq, pcxhr_trigger_tasklet, (unsigned long) mgr); 1484 (unsigned long) mgr);
1485 tasklet_init(&mgr->trigger_taskq, pcxhr_trigger_tasklet,
1486 (unsigned long) mgr);
1487
1278 mgr->prmh = kmalloc(sizeof(*mgr->prmh) + 1488 mgr->prmh = kmalloc(sizeof(*mgr->prmh) +
1279 sizeof(u32) * (PCXHR_SIZE_MAX_LONG_STATUS - PCXHR_SIZE_MAX_STATUS), 1489 sizeof(u32) * (PCXHR_SIZE_MAX_LONG_STATUS -
1490 PCXHR_SIZE_MAX_STATUS),
1280 GFP_KERNEL); 1491 GFP_KERNEL);
1281 if (! mgr->prmh) { 1492 if (! mgr->prmh) {
1282 pcxhr_free(mgr); 1493 pcxhr_free(mgr);
@@ -1297,7 +1508,8 @@ static int __devinit pcxhr_probe(struct pci_dev *pci, const struct pci_device_id
1297 else 1508 else
1298 idx = index[dev] + i; 1509 idx = index[dev] + i;
1299 1510
1300 snprintf(tmpid, sizeof(tmpid), "%s-%d", id[dev] ? id[dev] : card_name, i); 1511 snprintf(tmpid, sizeof(tmpid), "%s-%d",
1512 id[dev] ? id[dev] : card_name, i);
1301 card = snd_card_new(idx, tmpid, THIS_MODULE, 0); 1513 card = snd_card_new(idx, tmpid, THIS_MODULE, 0);
1302 1514
1303 if (! card) { 1515 if (! card) {
diff --git a/sound/pci/pcxhr/pcxhr.h b/sound/pci/pcxhr/pcxhr.h
index 652064787a55..84131a916c92 100644
--- a/sound/pci/pcxhr/pcxhr.h
+++ b/sound/pci/pcxhr/pcxhr.h
@@ -27,15 +27,18 @@
27#include <linux/mutex.h> 27#include <linux/mutex.h>
28#include <sound/pcm.h> 28#include <sound/pcm.h>
29 29
30#define PCXHR_DRIVER_VERSION 0x000804 /* 0.8.4 */ 30#define PCXHR_DRIVER_VERSION 0x000905 /* 0.9.5 */
31#define PCXHR_DRIVER_VERSION_STRING "0.8.4" /* 0.8.4 */ 31#define PCXHR_DRIVER_VERSION_STRING "0.9.5" /* 0.9.5 */
32 32
33 33
34#define PCXHR_MAX_CARDS 6 34#define PCXHR_MAX_CARDS 6
35#define PCXHR_PLAYBACK_STREAMS 4 35#define PCXHR_PLAYBACK_STREAMS 4
36 36
37#define PCXHR_GRANULARITY 96 /* transfer granularity (should be min 96 and multiple of 48) */ 37#define PCXHR_GRANULARITY 96 /* min 96 and multiple of 48 */
38#define PCXHR_GRANULARITY_MIN 96 /* transfer granularity of pipes and the dsp time (MBOX4) */ 38/* transfer granularity of pipes and the dsp time (MBOX4) */
39#define PCXHR_GRANULARITY_MIN 96
40/* TODO : granularity could be 64 or 128 */
41#define PCXHR_GRANULARITY_HR22 192 /* granularity for stereo cards */
39 42
40struct snd_pcxhr; 43struct snd_pcxhr;
41struct pcxhr_mgr; 44struct pcxhr_mgr;
@@ -51,6 +54,11 @@ enum pcxhr_clock_type {
51 PCXHR_CLOCK_TYPE_AES_2, 54 PCXHR_CLOCK_TYPE_AES_2,
52 PCXHR_CLOCK_TYPE_AES_3, 55 PCXHR_CLOCK_TYPE_AES_3,
53 PCXHR_CLOCK_TYPE_AES_4, 56 PCXHR_CLOCK_TYPE_AES_4,
57 PCXHR_CLOCK_TYPE_MAX = PCXHR_CLOCK_TYPE_AES_4,
58 HR22_CLOCK_TYPE_INTERNAL = PCXHR_CLOCK_TYPE_INTERNAL,
59 HR22_CLOCK_TYPE_AES_SYNC,
60 HR22_CLOCK_TYPE_AES_1,
61 HR22_CLOCK_TYPE_MAX = HR22_CLOCK_TYPE_AES_1,
54}; 62};
55 63
56struct pcxhr_mgr { 64struct pcxhr_mgr {
@@ -61,6 +69,8 @@ struct pcxhr_mgr {
61 69
62 int irq; 70 int irq;
63 71
72 int granularity;
73
64 /* card access with 1 mem bar and 2 io bar's */ 74 /* card access with 1 mem bar and 2 io bar's */
65 unsigned long port[3]; 75 unsigned long port[3];
66 76
@@ -83,11 +93,16 @@ struct pcxhr_mgr {
83 /* hardware interface */ 93 /* hardware interface */
84 unsigned int dsp_loaded; /* bit flags of loaded dsp indices */ 94 unsigned int dsp_loaded; /* bit flags of loaded dsp indices */
85 unsigned int dsp_version; /* read from embedded once firmware is loaded */ 95 unsigned int dsp_version; /* read from embedded once firmware is loaded */
86 int board_has_analog; /* if 0 the board is digital only */ 96 int playback_chips;
87 int mono_capture; /* if 1 the board does mono capture */ 97 int capture_chips;
88 int playback_chips; /* 4 or 6 */ 98 int fw_file_set;
89 int capture_chips; /* 4 or 1 */ 99 int firmware_num;
90 int firmware_num; /* 41 or 42 */ 100 int is_hr_stereo:1;
101 int board_has_aes1:1; /* if 1 board has AES1 plug and SRC */
102 int board_has_analog:1; /* if 0 the board is digital only */
103 int board_has_mic:1; /* if 1 the board has microphone input */
104 int board_aes_in_192k:1;/* if 1 the aes input plugs do support 192kHz */
105 int mono_capture:1; /* if 1 the board does mono capture */
91 106
92 struct snd_dma_buffer hostport; 107 struct snd_dma_buffer hostport;
93 108
@@ -106,6 +121,9 @@ struct pcxhr_mgr {
106 int async_err_stream_xrun; 121 int async_err_stream_xrun;
107 int async_err_pipe_xrun; 122 int async_err_pipe_xrun;
108 int async_err_other_last; 123 int async_err_other_last;
124
125 unsigned char xlx_cfg; /* copy of PCXHR_XLX_CFG register */
126 unsigned char xlx_selmic; /* copy of PCXHR_XLX_SELMIC register */
109}; 127};
110 128
111 129
@@ -155,24 +173,30 @@ struct snd_pcxhr {
155 173
156 struct snd_pcm *pcm; /* PCM */ 174 struct snd_pcm *pcm; /* PCM */
157 175
158 struct pcxhr_pipe playback_pipe; /* 1 stereo pipe only */ 176 struct pcxhr_pipe playback_pipe; /* 1 stereo pipe only */
159 struct pcxhr_pipe capture_pipe[2]; /* 1 stereo pipe or 2 mono pipes */ 177 struct pcxhr_pipe capture_pipe[2]; /* 1 stereo or 2 mono pipes */
160 178
161 struct pcxhr_stream playback_stream[PCXHR_PLAYBACK_STREAMS]; 179 struct pcxhr_stream playback_stream[PCXHR_PLAYBACK_STREAMS];
162 struct pcxhr_stream capture_stream[2]; /* 1 stereo stream or 2 mono streams */ 180 struct pcxhr_stream capture_stream[2]; /* 1 stereo or 2 mono streams */
163 int nb_streams_play; 181 int nb_streams_play;
164 int nb_streams_capt; 182 int nb_streams_capt;
165 183
166 int analog_playback_active[2]; /* Mixer : Master Playback active (!mute) */ 184 int analog_playback_active[2]; /* Mixer : Master Playback !mute */
167 int analog_playback_volume[2]; /* Mixer : Master Playback Volume */ 185 int analog_playback_volume[2]; /* Mixer : Master Playback Volume */
168 int analog_capture_volume[2]; /* Mixer : Master Capture Volume */ 186 int analog_capture_volume[2]; /* Mixer : Master Capture Volume */
169 int digital_playback_active[PCXHR_PLAYBACK_STREAMS][2]; /* Mixer : Digital Playback Active [streams][stereo]*/ 187 int digital_playback_active[PCXHR_PLAYBACK_STREAMS][2];
170 int digital_playback_volume[PCXHR_PLAYBACK_STREAMS][2]; /* Mixer : Digital Playback Volume [streams][stereo]*/ 188 int digital_playback_volume[PCXHR_PLAYBACK_STREAMS][2];
171 int digital_capture_volume[2]; /* Mixer : Digital Capture Volume [stereo] */ 189 int digital_capture_volume[2]; /* Mixer : Digital Capture Volume */
172 int monitoring_active[2]; /* Mixer : Monitoring Active */ 190 int monitoring_active[2]; /* Mixer : Monitoring Active */
173 int monitoring_volume[2]; /* Mixer : Monitoring Volume */ 191 int monitoring_volume[2]; /* Mixer : Monitoring Volume */
174 int audio_capture_source; /* Mixer : Audio Capture Source */ 192 int audio_capture_source; /* Mixer : Audio Capture Source */
175 unsigned char aes_bits[5]; /* Mixer : IEC958_AES bits */ 193 int mic_volume; /* used by cards with MIC only */
194 int mic_boost; /* used by cards with MIC only */
195 int mic_active; /* used by cards with MIC only */
196 int analog_capture_active; /* used by cards with MIC only */
197 int phantom_power; /* used by cards with MIC only */
198
199 unsigned char aes_bits[5]; /* Mixer : IEC958_AES bits */
176}; 200};
177 201
178struct pcxhr_hostport 202struct pcxhr_hostport
@@ -184,6 +208,8 @@ struct pcxhr_hostport
184/* exported */ 208/* exported */
185int pcxhr_create_pcm(struct snd_pcxhr *chip); 209int pcxhr_create_pcm(struct snd_pcxhr *chip);
186int pcxhr_set_clock(struct pcxhr_mgr *mgr, unsigned int rate); 210int pcxhr_set_clock(struct pcxhr_mgr *mgr, unsigned int rate);
187int pcxhr_get_external_clock(struct pcxhr_mgr *mgr, enum pcxhr_clock_type clock_type, int *sample_rate); 211int pcxhr_get_external_clock(struct pcxhr_mgr *mgr,
212 enum pcxhr_clock_type clock_type,
213 int *sample_rate);
188 214
189#endif /* __SOUND_PCXHR_H */ 215#endif /* __SOUND_PCXHR_H */
diff --git a/sound/pci/pcxhr/pcxhr_core.c b/sound/pci/pcxhr/pcxhr_core.c
index 4a5481f9781f..833e7180ad2d 100644
--- a/sound/pci/pcxhr/pcxhr_core.c
+++ b/sound/pci/pcxhr/pcxhr_core.c
@@ -132,13 +132,15 @@ static int pcxhr_check_reg_bit(struct pcxhr_mgr *mgr, unsigned int reg,
132 *read = PCXHR_INPB(mgr, reg); 132 *read = PCXHR_INPB(mgr, reg);
133 if ((*read & mask) == bit) { 133 if ((*read & mask) == bit) {
134 if (i > 100) 134 if (i > 100)
135 snd_printdd("ATTENTION! check_reg(%x) loopcount=%d\n", 135 snd_printdd("ATTENTION! check_reg(%x) "
136 "loopcount=%d\n",
136 reg, i); 137 reg, i);
137 return 0; 138 return 0;
138 } 139 }
139 i++; 140 i++;
140 } while (time_after_eq(end_time, jiffies)); 141 } while (time_after_eq(end_time, jiffies));
141 snd_printk(KERN_ERR "pcxhr_check_reg_bit: timeout, reg=%x, mask=0x%x, val=0x%x\n", 142 snd_printk(KERN_ERR
143 "pcxhr_check_reg_bit: timeout, reg=%x, mask=0x%x, val=%x\n",
142 reg, mask, *read); 144 reg, mask, *read);
143 return -EIO; 145 return -EIO;
144} 146}
@@ -159,18 +161,22 @@ static int pcxhr_check_reg_bit(struct pcxhr_mgr *mgr, unsigned int reg,
159#define PCXHR_IT_TEST_XILINX (0x0000003C | PCXHR_MASK_IT_HF1 | \ 161#define PCXHR_IT_TEST_XILINX (0x0000003C | PCXHR_MASK_IT_HF1 | \
160 PCXHR_MASK_IT_MANAGE_HF5) 162 PCXHR_MASK_IT_MANAGE_HF5)
161#define PCXHR_IT_DOWNLOAD_BOOT (0x0000000C | PCXHR_MASK_IT_HF1 | \ 163#define PCXHR_IT_DOWNLOAD_BOOT (0x0000000C | PCXHR_MASK_IT_HF1 | \
162 PCXHR_MASK_IT_MANAGE_HF5 | PCXHR_MASK_IT_WAIT) 164 PCXHR_MASK_IT_MANAGE_HF5 | \
165 PCXHR_MASK_IT_WAIT)
163#define PCXHR_IT_RESET_BOARD_FUNC (0x0000000C | PCXHR_MASK_IT_HF0 | \ 166#define PCXHR_IT_RESET_BOARD_FUNC (0x0000000C | PCXHR_MASK_IT_HF0 | \
164 PCXHR_MASK_IT_MANAGE_HF5 | PCXHR_MASK_IT_WAIT_EXTRA) 167 PCXHR_MASK_IT_MANAGE_HF5 | \
168 PCXHR_MASK_IT_WAIT_EXTRA)
165#define PCXHR_IT_DOWNLOAD_DSP (0x0000000C | \ 169#define PCXHR_IT_DOWNLOAD_DSP (0x0000000C | \
166 PCXHR_MASK_IT_MANAGE_HF5 | PCXHR_MASK_IT_WAIT) 170 PCXHR_MASK_IT_MANAGE_HF5 | \
171 PCXHR_MASK_IT_WAIT)
167#define PCXHR_IT_DEBUG (0x0000005A | PCXHR_MASK_IT_NO_HF0_HF1) 172#define PCXHR_IT_DEBUG (0x0000005A | PCXHR_MASK_IT_NO_HF0_HF1)
168#define PCXHR_IT_RESET_SEMAPHORE (0x0000005C | PCXHR_MASK_IT_NO_HF0_HF1) 173#define PCXHR_IT_RESET_SEMAPHORE (0x0000005C | PCXHR_MASK_IT_NO_HF0_HF1)
169#define PCXHR_IT_MESSAGE (0x00000074 | PCXHR_MASK_IT_NO_HF0_HF1) 174#define PCXHR_IT_MESSAGE (0x00000074 | PCXHR_MASK_IT_NO_HF0_HF1)
170#define PCXHR_IT_RESET_CHK (0x00000076 | PCXHR_MASK_IT_NO_HF0_HF1) 175#define PCXHR_IT_RESET_CHK (0x00000076 | PCXHR_MASK_IT_NO_HF0_HF1)
171#define PCXHR_IT_UPDATE_RBUFFER (0x00000078 | PCXHR_MASK_IT_NO_HF0_HF1) 176#define PCXHR_IT_UPDATE_RBUFFER (0x00000078 | PCXHR_MASK_IT_NO_HF0_HF1)
172 177
173static int pcxhr_send_it_dsp(struct pcxhr_mgr *mgr, unsigned int itdsp, int atomic) 178static int pcxhr_send_it_dsp(struct pcxhr_mgr *mgr,
179 unsigned int itdsp, int atomic)
174{ 180{
175 int err; 181 int err;
176 unsigned char reg; 182 unsigned char reg;
@@ -178,17 +184,21 @@ static int pcxhr_send_it_dsp(struct pcxhr_mgr *mgr, unsigned int itdsp, int atom
178 if (itdsp & PCXHR_MASK_IT_MANAGE_HF5) { 184 if (itdsp & PCXHR_MASK_IT_MANAGE_HF5) {
179 /* clear hf5 bit */ 185 /* clear hf5 bit */
180 PCXHR_OUTPL(mgr, PCXHR_PLX_MBOX0, 186 PCXHR_OUTPL(mgr, PCXHR_PLX_MBOX0,
181 PCXHR_INPL(mgr, PCXHR_PLX_MBOX0) & ~PCXHR_MBOX0_HF5); 187 PCXHR_INPL(mgr, PCXHR_PLX_MBOX0) &
188 ~PCXHR_MBOX0_HF5);
182 } 189 }
183 if ((itdsp & PCXHR_MASK_IT_NO_HF0_HF1) == 0) { 190 if ((itdsp & PCXHR_MASK_IT_NO_HF0_HF1) == 0) {
184 reg = PCXHR_ICR_HI08_RREQ | PCXHR_ICR_HI08_TREQ | PCXHR_ICR_HI08_HDRQ; 191 reg = (PCXHR_ICR_HI08_RREQ |
192 PCXHR_ICR_HI08_TREQ |
193 PCXHR_ICR_HI08_HDRQ);
185 if (itdsp & PCXHR_MASK_IT_HF0) 194 if (itdsp & PCXHR_MASK_IT_HF0)
186 reg |= PCXHR_ICR_HI08_HF0; 195 reg |= PCXHR_ICR_HI08_HF0;
187 if (itdsp & PCXHR_MASK_IT_HF1) 196 if (itdsp & PCXHR_MASK_IT_HF1)
188 reg |= PCXHR_ICR_HI08_HF1; 197 reg |= PCXHR_ICR_HI08_HF1;
189 PCXHR_OUTPB(mgr, PCXHR_DSP_ICR, reg); 198 PCXHR_OUTPB(mgr, PCXHR_DSP_ICR, reg);
190 } 199 }
191 reg = (unsigned char)(((itdsp & PCXHR_MASK_EXTRA_INFO) >> 1) | PCXHR_CVR_HI08_HC); 200 reg = (unsigned char)(((itdsp & PCXHR_MASK_EXTRA_INFO) >> 1) |
201 PCXHR_CVR_HI08_HC);
192 PCXHR_OUTPB(mgr, PCXHR_DSP_CVR, reg); 202 PCXHR_OUTPB(mgr, PCXHR_DSP_CVR, reg);
193 if (itdsp & PCXHR_MASK_IT_WAIT) { 203 if (itdsp & PCXHR_MASK_IT_WAIT) {
194 if (atomic) 204 if (atomic)
@@ -211,10 +221,14 @@ static int pcxhr_send_it_dsp(struct pcxhr_mgr *mgr, unsigned int itdsp, int atom
211 } 221 }
212 if (itdsp & PCXHR_MASK_IT_MANAGE_HF5) { 222 if (itdsp & PCXHR_MASK_IT_MANAGE_HF5) {
213 /* wait for hf5 bit */ 223 /* wait for hf5 bit */
214 err = pcxhr_check_reg_bit(mgr, PCXHR_PLX_MBOX0, PCXHR_MBOX0_HF5, 224 err = pcxhr_check_reg_bit(mgr, PCXHR_PLX_MBOX0,
215 PCXHR_MBOX0_HF5, PCXHR_TIMEOUT_DSP, &reg); 225 PCXHR_MBOX0_HF5,
226 PCXHR_MBOX0_HF5,
227 PCXHR_TIMEOUT_DSP,
228 &reg);
216 if (err) { 229 if (err) {
217 snd_printk(KERN_ERR "pcxhr_send_it_dsp : TIMEOUT HF5\n"); 230 snd_printk(KERN_ERR
231 "pcxhr_send_it_dsp : TIMEOUT HF5\n");
218 return err; 232 return err;
219 } 233 }
220 } 234 }
@@ -263,7 +277,8 @@ void pcxhr_enable_dsp(struct pcxhr_mgr *mgr)
263/* 277/*
264 * load the xilinx image 278 * load the xilinx image
265 */ 279 */
266int pcxhr_load_xilinx_binary(struct pcxhr_mgr *mgr, const struct firmware *xilinx, int second) 280int pcxhr_load_xilinx_binary(struct pcxhr_mgr *mgr,
281 const struct firmware *xilinx, int second)
267{ 282{
268 unsigned int i; 283 unsigned int i;
269 unsigned int chipsc; 284 unsigned int chipsc;
@@ -274,7 +289,9 @@ int pcxhr_load_xilinx_binary(struct pcxhr_mgr *mgr, const struct firmware *xilin
274 /* test first xilinx */ 289 /* test first xilinx */
275 chipsc = PCXHR_INPL(mgr, PCXHR_PLX_CHIPSC); 290 chipsc = PCXHR_INPL(mgr, PCXHR_PLX_CHIPSC);
276 /* REV01 cards do not support the PCXHR_CHIPSC_GPI_USERI bit anymore */ 291 /* REV01 cards do not support the PCXHR_CHIPSC_GPI_USERI bit anymore */
277 /* this bit will always be 1; no possibility to test presence of first xilinx */ 292 /* this bit will always be 1;
293 * no possibility to test presence of first xilinx
294 */
278 if(second) { 295 if(second) {
279 if ((chipsc & PCXHR_CHIPSC_GPI_USERI) == 0) { 296 if ((chipsc & PCXHR_CHIPSC_GPI_USERI) == 0) {
280 snd_printk(KERN_ERR "error loading first xilinx\n"); 297 snd_printk(KERN_ERR "error loading first xilinx\n");
@@ -290,7 +307,8 @@ int pcxhr_load_xilinx_binary(struct pcxhr_mgr *mgr, const struct firmware *xilin
290 data = *image; 307 data = *image;
291 mask = 0x80; 308 mask = 0x80;
292 while (mask) { 309 while (mask) {
293 chipsc &= ~(PCXHR_CHIPSC_DATA_CLK | PCXHR_CHIPSC_DATA_IN); 310 chipsc &= ~(PCXHR_CHIPSC_DATA_CLK |
311 PCXHR_CHIPSC_DATA_IN);
294 if (data & mask) 312 if (data & mask)
295 chipsc |= PCXHR_CHIPSC_DATA_IN; 313 chipsc |= PCXHR_CHIPSC_DATA_IN;
296 PCXHR_OUTPL(mgr, PCXHR_PLX_CHIPSC, chipsc); 314 PCXHR_OUTPL(mgr, PCXHR_PLX_CHIPSC, chipsc);
@@ -330,15 +348,20 @@ static int pcxhr_download_dsp(struct pcxhr_mgr *mgr, const struct firmware *dsp)
330 data = dsp->data + i; 348 data = dsp->data + i;
331 if (i == 0) { 349 if (i == 0) {
332 /* test data header consistency */ 350 /* test data header consistency */
333 len = (unsigned int)((data[0]<<16) + (data[1]<<8) + data[2]); 351 len = (unsigned int)((data[0]<<16) +
334 if (len && dsp->size != (len + 2) * 3) 352 (data[1]<<8) +
353 data[2]);
354 if (len && (dsp->size != (len + 2) * 3))
335 return -EINVAL; 355 return -EINVAL;
336 } 356 }
337 /* wait DSP ready for new transfer */ 357 /* wait DSP ready for new transfer */
338 err = pcxhr_check_reg_bit(mgr, PCXHR_DSP_ISR, PCXHR_ISR_HI08_TRDY, 358 err = pcxhr_check_reg_bit(mgr, PCXHR_DSP_ISR,
339 PCXHR_ISR_HI08_TRDY, PCXHR_TIMEOUT_DSP, &dummy); 359 PCXHR_ISR_HI08_TRDY,
360 PCXHR_ISR_HI08_TRDY,
361 PCXHR_TIMEOUT_DSP, &dummy);
340 if (err) { 362 if (err) {
341 snd_printk(KERN_ERR "dsp loading error at position %d\n", i); 363 snd_printk(KERN_ERR
364 "dsp loading error at position %d\n", i);
342 return err; 365 return err;
343 } 366 }
344 /* send host data */ 367 /* send host data */
@@ -357,7 +380,8 @@ static int pcxhr_download_dsp(struct pcxhr_mgr *mgr, const struct firmware *dsp)
357/* 380/*
358 * load the eeprom image 381 * load the eeprom image
359 */ 382 */
360int pcxhr_load_eeprom_binary(struct pcxhr_mgr *mgr, const struct firmware *eeprom) 383int pcxhr_load_eeprom_binary(struct pcxhr_mgr *mgr,
384 const struct firmware *eeprom)
361{ 385{
362 int err; 386 int err;
363 unsigned char reg; 387 unsigned char reg;
@@ -365,7 +389,9 @@ int pcxhr_load_eeprom_binary(struct pcxhr_mgr *mgr, const struct firmware *eepro
365 /* init value of the ICR register */ 389 /* init value of the ICR register */
366 reg = PCXHR_ICR_HI08_RREQ | PCXHR_ICR_HI08_TREQ | PCXHR_ICR_HI08_HDRQ; 390 reg = PCXHR_ICR_HI08_RREQ | PCXHR_ICR_HI08_TREQ | PCXHR_ICR_HI08_HDRQ;
367 if (PCXHR_INPL(mgr, PCXHR_PLX_MBOX0) & PCXHR_MBOX0_BOOT_HERE) { 391 if (PCXHR_INPL(mgr, PCXHR_PLX_MBOX0) & PCXHR_MBOX0_BOOT_HERE) {
368 /* no need to load the eeprom binary, but init the HI08 interface */ 392 /* no need to load the eeprom binary,
393 * but init the HI08 interface
394 */
369 PCXHR_OUTPB(mgr, PCXHR_DSP_ICR, reg | PCXHR_ICR_HI08_INIT); 395 PCXHR_OUTPB(mgr, PCXHR_DSP_ICR, reg | PCXHR_ICR_HI08_INIT);
370 msleep(PCXHR_WAIT_DEFAULT); 396 msleep(PCXHR_WAIT_DEFAULT);
371 PCXHR_OUTPB(mgr, PCXHR_DSP_ICR, reg); 397 PCXHR_OUTPB(mgr, PCXHR_DSP_ICR, reg);
@@ -429,8 +455,10 @@ int pcxhr_load_dsp_binary(struct pcxhr_mgr *mgr, const struct firmware *dsp)
429 if (err) 455 if (err)
430 return err; 456 return err;
431 /* wait for chk bit */ 457 /* wait for chk bit */
432 return pcxhr_check_reg_bit(mgr, PCXHR_DSP_ISR, PCXHR_ISR_HI08_CHK, 458 return pcxhr_check_reg_bit(mgr, PCXHR_DSP_ISR,
433 PCXHR_ISR_HI08_CHK, PCXHR_TIMEOUT_DSP, &dummy); 459 PCXHR_ISR_HI08_CHK,
460 PCXHR_ISR_HI08_CHK,
461 PCXHR_TIMEOUT_DSP, &dummy);
434} 462}
435 463
436 464
@@ -443,8 +471,8 @@ struct pcxhr_cmd_info {
443/* RMH status type */ 471/* RMH status type */
444enum { 472enum {
445 RMH_SSIZE_FIXED = 0, /* status size fix (st_length = 0..x) */ 473 RMH_SSIZE_FIXED = 0, /* status size fix (st_length = 0..x) */
446 RMH_SSIZE_ARG = 1, /* status size given in the LSB byte (used with st_length = 1) */ 474 RMH_SSIZE_ARG = 1, /* status size given in the LSB byte */
447 RMH_SSIZE_MASK = 2, /* status size given in bitmask (used with st_length = 1) */ 475 RMH_SSIZE_MASK = 2, /* status size given in bitmask */
448}; 476};
449 477
450/* 478/*
@@ -474,7 +502,7 @@ static struct pcxhr_cmd_info pcxhr_dsp_cmds[] = {
474[CMD_UPDATE_R_BUFFERS] = { 0x840000, 0, RMH_SSIZE_FIXED }, 502[CMD_UPDATE_R_BUFFERS] = { 0x840000, 0, RMH_SSIZE_FIXED },
475[CMD_FORMAT_STREAM_OUT] = { 0x860000, 0, RMH_SSIZE_FIXED }, 503[CMD_FORMAT_STREAM_OUT] = { 0x860000, 0, RMH_SSIZE_FIXED },
476[CMD_FORMAT_STREAM_IN] = { 0x870000, 0, RMH_SSIZE_FIXED }, 504[CMD_FORMAT_STREAM_IN] = { 0x870000, 0, RMH_SSIZE_FIXED },
477[CMD_STREAM_SAMPLE_COUNT] = { 0x902000, 2, RMH_SSIZE_FIXED }, /* stat_len = nb_streams * 2 */ 505[CMD_STREAM_SAMPLE_COUNT] = { 0x902000, 2, RMH_SSIZE_FIXED },
478[CMD_AUDIO_LEVEL_ADJUST] = { 0xc22000, 0, RMH_SSIZE_FIXED }, 506[CMD_AUDIO_LEVEL_ADJUST] = { 0xc22000, 0, RMH_SSIZE_FIXED },
479}; 507};
480 508
@@ -524,10 +552,13 @@ static int pcxhr_read_rmh_status(struct pcxhr_mgr *mgr, struct pcxhr_rmh *rmh)
524 552
525 for (i = 0; i < rmh->stat_len; i++) { 553 for (i = 0; i < rmh->stat_len; i++) {
526 /* wait for receiver full */ 554 /* wait for receiver full */
527 err = pcxhr_check_reg_bit(mgr, PCXHR_DSP_ISR, PCXHR_ISR_HI08_RXDF, 555 err = pcxhr_check_reg_bit(mgr, PCXHR_DSP_ISR,
528 PCXHR_ISR_HI08_RXDF, PCXHR_TIMEOUT_DSP, &reg); 556 PCXHR_ISR_HI08_RXDF,
557 PCXHR_ISR_HI08_RXDF,
558 PCXHR_TIMEOUT_DSP, &reg);
529 if (err) { 559 if (err) {
530 snd_printk(KERN_ERR "ERROR RMH stat: ISR:RXDF=1 (ISR = %x; i=%d )\n", 560 snd_printk(KERN_ERR "ERROR RMH stat: "
561 "ISR:RXDF=1 (ISR = %x; i=%d )\n",
531 reg, i); 562 reg, i);
532 return err; 563 return err;
533 } 564 }
@@ -537,10 +568,10 @@ static int pcxhr_read_rmh_status(struct pcxhr_mgr *mgr, struct pcxhr_rmh *rmh)
537 data |= PCXHR_INPB(mgr, PCXHR_DSP_TXL); 568 data |= PCXHR_INPB(mgr, PCXHR_DSP_TXL);
538 569
539 /* need to update rmh->stat_len on the fly ?? */ 570 /* need to update rmh->stat_len on the fly ?? */
540 if (i==0) { 571 if (!i) {
541 if (rmh->dsp_stat != RMH_SSIZE_FIXED) { 572 if (rmh->dsp_stat != RMH_SSIZE_FIXED) {
542 if (rmh->dsp_stat == RMH_SSIZE_ARG) { 573 if (rmh->dsp_stat == RMH_SSIZE_ARG) {
543 rmh->stat_len = (u16)(data & 0x0000ff) + 1; 574 rmh->stat_len = (data & 0x0000ff) + 1;
544 data &= 0xffff00; 575 data &= 0xffff00;
545 } else { 576 } else {
546 /* rmh->dsp_stat == RMH_SSIZE_MASK */ 577 /* rmh->dsp_stat == RMH_SSIZE_MASK */
@@ -562,7 +593,8 @@ static int pcxhr_read_rmh_status(struct pcxhr_mgr *mgr, struct pcxhr_rmh *rmh)
562 rmh->stat[i] = data; 593 rmh->stat[i] = data;
563 } 594 }
564 if (rmh->stat_len > max_stat_len) { 595 if (rmh->stat_len > max_stat_len) {
565 snd_printdd("PCXHR : rmh->stat_len=%x too big\n", rmh->stat_len); 596 snd_printdd("PCXHR : rmh->stat_len=%x too big\n",
597 rmh->stat_len);
566 rmh->stat_len = max_stat_len; 598 rmh->stat_len = max_stat_len;
567 } 599 }
568 return 0; 600 return 0;
@@ -605,7 +637,8 @@ static int pcxhr_send_msg_nolock(struct pcxhr_mgr *mgr, struct pcxhr_rmh *rmh)
605 data &= 0xff7fff; /* MASK_1_WORD_COMMAND */ 637 data &= 0xff7fff; /* MASK_1_WORD_COMMAND */
606#ifdef CONFIG_SND_DEBUG_VERBOSE 638#ifdef CONFIG_SND_DEBUG_VERBOSE
607 if (rmh->cmd_idx < CMD_LAST_INDEX) 639 if (rmh->cmd_idx < CMD_LAST_INDEX)
608 snd_printdd("MSG cmd[0]=%x (%s)\n", data, cmd_names[rmh->cmd_idx]); 640 snd_printdd("MSG cmd[0]=%x (%s)\n",
641 data, cmd_names[rmh->cmd_idx]);
609#endif 642#endif
610 643
611 err = pcxhr_check_reg_bit(mgr, PCXHR_DSP_ISR, PCXHR_ISR_HI08_TRDY, 644 err = pcxhr_check_reg_bit(mgr, PCXHR_DSP_ISR, PCXHR_ISR_HI08_TRDY,
@@ -619,8 +652,10 @@ static int pcxhr_send_msg_nolock(struct pcxhr_mgr *mgr, struct pcxhr_rmh *rmh)
619 if (rmh->cmd_len > 1) { 652 if (rmh->cmd_len > 1) {
620 /* send length */ 653 /* send length */
621 data = rmh->cmd_len - 1; 654 data = rmh->cmd_len - 1;
622 err = pcxhr_check_reg_bit(mgr, PCXHR_DSP_ISR, PCXHR_ISR_HI08_TRDY, 655 err = pcxhr_check_reg_bit(mgr, PCXHR_DSP_ISR,
623 PCXHR_ISR_HI08_TRDY, PCXHR_TIMEOUT_DSP, &reg); 656 PCXHR_ISR_HI08_TRDY,
657 PCXHR_ISR_HI08_TRDY,
658 PCXHR_TIMEOUT_DSP, &reg);
624 if (err) 659 if (err)
625 return err; 660 return err;
626 PCXHR_OUTPB(mgr, PCXHR_DSP_TXH, (data>>16)&0xFF); 661 PCXHR_OUTPB(mgr, PCXHR_DSP_TXH, (data>>16)&0xFF);
@@ -653,8 +688,10 @@ static int pcxhr_send_msg_nolock(struct pcxhr_mgr *mgr, struct pcxhr_rmh *rmh)
653 /* test status ISR */ 688 /* test status ISR */
654 if (reg & PCXHR_ISR_HI08_ERR) { 689 if (reg & PCXHR_ISR_HI08_ERR) {
655 /* ERROR, wait for receiver full */ 690 /* ERROR, wait for receiver full */
656 err = pcxhr_check_reg_bit(mgr, PCXHR_DSP_ISR, PCXHR_ISR_HI08_RXDF, 691 err = pcxhr_check_reg_bit(mgr, PCXHR_DSP_ISR,
657 PCXHR_ISR_HI08_RXDF, PCXHR_TIMEOUT_DSP, &reg); 692 PCXHR_ISR_HI08_RXDF,
693 PCXHR_ISR_HI08_RXDF,
694 PCXHR_TIMEOUT_DSP, &reg);
658 if (err) { 695 if (err) {
659 snd_printk(KERN_ERR "ERROR RMH: ISR:RXDF=1 (ISR = %x)\n", reg); 696 snd_printk(KERN_ERR "ERROR RMH: ISR:RXDF=1 (ISR = %x)\n", reg);
660 return err; 697 return err;
@@ -663,7 +700,8 @@ static int pcxhr_send_msg_nolock(struct pcxhr_mgr *mgr, struct pcxhr_rmh *rmh)
663 data = PCXHR_INPB(mgr, PCXHR_DSP_TXH) << 16; 700 data = PCXHR_INPB(mgr, PCXHR_DSP_TXH) << 16;
664 data |= PCXHR_INPB(mgr, PCXHR_DSP_TXM) << 8; 701 data |= PCXHR_INPB(mgr, PCXHR_DSP_TXM) << 8;
665 data |= PCXHR_INPB(mgr, PCXHR_DSP_TXL); 702 data |= PCXHR_INPB(mgr, PCXHR_DSP_TXL);
666 snd_printk(KERN_ERR "ERROR RMH(%d): 0x%x\n", rmh->cmd_idx, data); 703 snd_printk(KERN_ERR "ERROR RMH(%d): 0x%x\n",
704 rmh->cmd_idx, data);
667 err = -EINVAL; 705 err = -EINVAL;
668 } else { 706 } else {
669 /* read the response data */ 707 /* read the response data */
@@ -732,8 +770,9 @@ int pcxhr_send_msg(struct pcxhr_mgr *mgr, struct pcxhr_rmh *rmh)
732static inline int pcxhr_pipes_running(struct pcxhr_mgr *mgr) 770static inline int pcxhr_pipes_running(struct pcxhr_mgr *mgr)
733{ 771{
734 int start_mask = PCXHR_INPL(mgr, PCXHR_PLX_MBOX2); 772 int start_mask = PCXHR_INPL(mgr, PCXHR_PLX_MBOX2);
735 /* least segnificant 12 bits are the pipe states for the playback audios */ 773 /* least segnificant 12 bits are the pipe states
736 /* next 12 bits are the pipe states for the capture audios 774 * for the playback audios
775 * next 12 bits are the pipe states for the capture audios
737 * (PCXHR_PIPE_STATE_CAPTURE_OFFSET) 776 * (PCXHR_PIPE_STATE_CAPTURE_OFFSET)
738 */ 777 */
739 start_mask &= 0xffffff; 778 start_mask &= 0xffffff;
@@ -744,7 +783,8 @@ static inline int pcxhr_pipes_running(struct pcxhr_mgr *mgr)
744#define PCXHR_PIPE_STATE_CAPTURE_OFFSET 12 783#define PCXHR_PIPE_STATE_CAPTURE_OFFSET 12
745#define MAX_WAIT_FOR_DSP 20 784#define MAX_WAIT_FOR_DSP 20
746 785
747static int pcxhr_prepair_pipe_start(struct pcxhr_mgr *mgr, int audio_mask, int *retry) 786static int pcxhr_prepair_pipe_start(struct pcxhr_mgr *mgr,
787 int audio_mask, int *retry)
748{ 788{
749 struct pcxhr_rmh rmh; 789 struct pcxhr_rmh rmh;
750 int err; 790 int err;
@@ -760,17 +800,20 @@ static int pcxhr_prepair_pipe_start(struct pcxhr_mgr *mgr, int audio_mask, int *
760 } else { 800 } else {
761 /* can start capture pipe */ 801 /* can start capture pipe */
762 pcxhr_set_pipe_cmd_params(&rmh, 1, audio - 802 pcxhr_set_pipe_cmd_params(&rmh, 1, audio -
763 PCXHR_PIPE_STATE_CAPTURE_OFFSET, 803 PCXHR_PIPE_STATE_CAPTURE_OFFSET,
764 0, 0); 804 0, 0);
765 } 805 }
766 err = pcxhr_send_msg(mgr, &rmh); 806 err = pcxhr_send_msg(mgr, &rmh);
767 if (err) { 807 if (err) {
768 snd_printk(KERN_ERR 808 snd_printk(KERN_ERR
769 "error pipe start (CMD_CAN_START_PIPE) err=%x!\n", 809 "error pipe start "
810 "(CMD_CAN_START_PIPE) err=%x!\n",
770 err); 811 err);
771 return err; 812 return err;
772 } 813 }
773 /* if the pipe couldn't be prepaired for start, retry it later */ 814 /* if the pipe couldn't be prepaired for start,
815 * retry it later
816 */
774 if (rmh.stat[0] == 0) 817 if (rmh.stat[0] == 0)
775 *retry |= (1<<audio); 818 *retry |= (1<<audio);
776 } 819 }
@@ -795,14 +838,14 @@ static int pcxhr_stop_pipes(struct pcxhr_mgr *mgr, int audio_mask)
795 } else { 838 } else {
796 /* stop capture pipe */ 839 /* stop capture pipe */
797 pcxhr_set_pipe_cmd_params(&rmh, 1, audio - 840 pcxhr_set_pipe_cmd_params(&rmh, 1, audio -
798 PCXHR_PIPE_STATE_CAPTURE_OFFSET, 841 PCXHR_PIPE_STATE_CAPTURE_OFFSET,
799 0, 0); 842 0, 0);
800 } 843 }
801 err = pcxhr_send_msg(mgr, &rmh); 844 err = pcxhr_send_msg(mgr, &rmh);
802 if (err) { 845 if (err) {
803 snd_printk(KERN_ERR 846 snd_printk(KERN_ERR
804 "error pipe stop (CMD_STOP_PIPE) err=%x!\n", 847 "error pipe stop "
805 err); 848 "(CMD_STOP_PIPE) err=%x!\n", err);
806 return err; 849 return err;
807 } 850 }
808 } 851 }
@@ -822,15 +865,16 @@ static int pcxhr_toggle_pipes(struct pcxhr_mgr *mgr, int audio_mask)
822 if (audio_mask & 1) { 865 if (audio_mask & 1) {
823 pcxhr_init_rmh(&rmh, CMD_CONF_PIPE); 866 pcxhr_init_rmh(&rmh, CMD_CONF_PIPE);
824 if (audio < PCXHR_PIPE_STATE_CAPTURE_OFFSET) 867 if (audio < PCXHR_PIPE_STATE_CAPTURE_OFFSET)
825 pcxhr_set_pipe_cmd_params(&rmh, 0, 0, 0, 1 << audio); 868 pcxhr_set_pipe_cmd_params(&rmh, 0, 0, 0,
869 1 << audio);
826 else 870 else
827 pcxhr_set_pipe_cmd_params(&rmh, 1, 0, 0, 871 pcxhr_set_pipe_cmd_params(&rmh, 1, 0, 0,
828 1 << (audio - PCXHR_PIPE_STATE_CAPTURE_OFFSET)); 872 1 << (audio - PCXHR_PIPE_STATE_CAPTURE_OFFSET));
829 err = pcxhr_send_msg(mgr, &rmh); 873 err = pcxhr_send_msg(mgr, &rmh);
830 if (err) { 874 if (err) {
831 snd_printk(KERN_ERR 875 snd_printk(KERN_ERR
832 "error pipe start (CMD_CONF_PIPE) err=%x!\n", 876 "error pipe start "
833 err); 877 "(CMD_CONF_PIPE) err=%x!\n", err);
834 return err; 878 return err;
835 } 879 }
836 } 880 }
@@ -841,7 +885,9 @@ static int pcxhr_toggle_pipes(struct pcxhr_mgr *mgr, int audio_mask)
841 pcxhr_init_rmh(&rmh, CMD_SEND_IRQA); 885 pcxhr_init_rmh(&rmh, CMD_SEND_IRQA);
842 err = pcxhr_send_msg(mgr, &rmh); 886 err = pcxhr_send_msg(mgr, &rmh);
843 if (err) { 887 if (err) {
844 snd_printk(KERN_ERR "error pipe start (CMD_SEND_IRQA) err=%x!\n", err ); 888 snd_printk(KERN_ERR
889 "error pipe start (CMD_SEND_IRQA) err=%x!\n",
890 err);
845 return err; 891 return err;
846 } 892 }
847 return 0; 893 return 0;
@@ -849,7 +895,8 @@ static int pcxhr_toggle_pipes(struct pcxhr_mgr *mgr, int audio_mask)
849 895
850 896
851 897
852int pcxhr_set_pipe_state(struct pcxhr_mgr *mgr, int playback_mask, int capture_mask, int start) 898int pcxhr_set_pipe_state(struct pcxhr_mgr *mgr, int playback_mask,
899 int capture_mask, int start)
853{ 900{
854 int state, i, err; 901 int state, i, err;
855 int audio_mask; 902 int audio_mask;
@@ -858,21 +905,23 @@ int pcxhr_set_pipe_state(struct pcxhr_mgr *mgr, int playback_mask, int capture_m
858 struct timeval my_tv1, my_tv2; 905 struct timeval my_tv1, my_tv2;
859 do_gettimeofday(&my_tv1); 906 do_gettimeofday(&my_tv1);
860#endif 907#endif
861 audio_mask = (playback_mask | (capture_mask << PCXHR_PIPE_STATE_CAPTURE_OFFSET)); 908 audio_mask = (playback_mask |
909 (capture_mask << PCXHR_PIPE_STATE_CAPTURE_OFFSET));
862 /* current pipe state (playback + record) */ 910 /* current pipe state (playback + record) */
863 state = pcxhr_pipes_running(mgr); 911 state = pcxhr_pipes_running(mgr);
864 snd_printdd("pcxhr_set_pipe_state %s (mask %x current %x)\n", 912 snd_printdd("pcxhr_set_pipe_state %s (mask %x current %x)\n",
865 start ? "START" : "STOP", audio_mask, state); 913 start ? "START" : "STOP", audio_mask, state);
866 if (start) { 914 if (start) {
867 audio_mask &= ~state; /* start only pipes that are not yet started */ 915 /* start only pipes that are not yet started */
916 audio_mask &= ~state;
868 state = audio_mask; 917 state = audio_mask;
869 for (i = 0; i < MAX_WAIT_FOR_DSP; i++) { 918 for (i = 0; i < MAX_WAIT_FOR_DSP; i++) {
870 err = pcxhr_prepair_pipe_start(mgr, state, &state); 919 err = pcxhr_prepair_pipe_start(mgr, state, &state);
871 if (err) 920 if (err)
872 return err; 921 return err;
873 if (state == 0) 922 if (state == 0)
874 break; /* success, all pipes prepaired for start */ 923 break; /* success, all pipes prepaired */
875 mdelay(1); /* otherwise wait 1 millisecond and retry */ 924 mdelay(1); /* wait 1 millisecond and retry */
876 } 925 }
877 } else { 926 } else {
878 audio_mask &= state; /* stop only pipes that are started */ 927 audio_mask &= state; /* stop only pipes that are started */
@@ -891,7 +940,7 @@ int pcxhr_set_pipe_state(struct pcxhr_mgr *mgr, int playback_mask, int capture_m
891 if ((state & audio_mask) == (start ? audio_mask : 0)) 940 if ((state & audio_mask) == (start ? audio_mask : 0))
892 break; 941 break;
893 if (++i >= MAX_WAIT_FOR_DSP * 100) { 942 if (++i >= MAX_WAIT_FOR_DSP * 100) {
894 snd_printk(KERN_ERR "error pipe start/stop (ED_NO_RESPONSE_AT_IRQA)\n"); 943 snd_printk(KERN_ERR "error pipe start/stop\n");
895 return -EBUSY; 944 return -EBUSY;
896 } 945 }
897 udelay(10); /* wait 10 microseconds */ 946 udelay(10); /* wait 10 microseconds */
@@ -918,7 +967,8 @@ int pcxhr_write_io_num_reg_cont(struct pcxhr_mgr *mgr, unsigned int mask,
918 967
919 spin_lock_irqsave(&mgr->msg_lock, flags); 968 spin_lock_irqsave(&mgr->msg_lock, flags);
920 if ((mgr->io_num_reg_cont & mask) == value) { 969 if ((mgr->io_num_reg_cont & mask) == value) {
921 snd_printdd("IO_NUM_REG_CONT mask %x already is set to %x\n", mask, value); 970 snd_printdd("IO_NUM_REG_CONT mask %x already is set to %x\n",
971 mask, value);
922 if (changed) 972 if (changed)
923 *changed = 0; 973 *changed = 0;
924 spin_unlock_irqrestore(&mgr->msg_lock, flags); 974 spin_unlock_irqrestore(&mgr->msg_lock, flags);
@@ -971,7 +1021,8 @@ static int pcxhr_handle_async_err(struct pcxhr_mgr *mgr, u32 err,
971 err = ((err >> 12) & 0xfff); 1021 err = ((err >> 12) & 0xfff);
972 if (!err) 1022 if (!err)
973 return 0; 1023 return 0;
974 snd_printdd("CMD_ASYNC : Error %s %s Pipe %d err=%x\n", err_src_name[err_src], 1024 snd_printdd("CMD_ASYNC : Error %s %s Pipe %d err=%x\n",
1025 err_src_name[err_src],
975 is_capture ? "Record" : "Play", pipe, err); 1026 is_capture ? "Record" : "Play", pipe, err);
976 if (err == 0xe01) 1027 if (err == 0xe01)
977 mgr->async_err_stream_xrun++; 1028 mgr->async_err_stream_xrun++;
@@ -996,6 +1047,13 @@ void pcxhr_msg_tasklet(unsigned long arg)
996 snd_printdd("TASKLET : PCXHR_IRQ_TIME_CODE event occured\n"); 1047 snd_printdd("TASKLET : PCXHR_IRQ_TIME_CODE event occured\n");
997 if (mgr->src_it_dsp & PCXHR_IRQ_NOTIFY) 1048 if (mgr->src_it_dsp & PCXHR_IRQ_NOTIFY)
998 snd_printdd("TASKLET : PCXHR_IRQ_NOTIFY event occured\n"); 1049 snd_printdd("TASKLET : PCXHR_IRQ_NOTIFY event occured\n");
1050 if (mgr->src_it_dsp & (PCXHR_IRQ_FREQ_CHANGE | PCXHR_IRQ_TIME_CODE)) {
1051 /* clear events FREQ_CHANGE and TIME_CODE */
1052 pcxhr_init_rmh(prmh, CMD_TEST_IT);
1053 err = pcxhr_send_msg(mgr, prmh);
1054 snd_printdd("CMD_TEST_IT : err=%x, stat=%x\n",
1055 err, prmh->stat[0]);
1056 }
999 if (mgr->src_it_dsp & PCXHR_IRQ_ASYNC) { 1057 if (mgr->src_it_dsp & PCXHR_IRQ_ASYNC) {
1000 snd_printdd("TASKLET : PCXHR_IRQ_ASYNC event occured\n"); 1058 snd_printdd("TASKLET : PCXHR_IRQ_ASYNC event occured\n");
1001 1059
@@ -1005,18 +1063,22 @@ void pcxhr_msg_tasklet(unsigned long arg)
1005 prmh->stat_len = PCXHR_SIZE_MAX_LONG_STATUS; 1063 prmh->stat_len = PCXHR_SIZE_MAX_LONG_STATUS;
1006 err = pcxhr_send_msg(mgr, prmh); 1064 err = pcxhr_send_msg(mgr, prmh);
1007 if (err) 1065 if (err)
1008 snd_printk(KERN_ERR "ERROR pcxhr_msg_tasklet=%x;\n", err); 1066 snd_printk(KERN_ERR "ERROR pcxhr_msg_tasklet=%x;\n",
1067 err);
1009 i = 1; 1068 i = 1;
1010 while (i < prmh->stat_len) { 1069 while (i < prmh->stat_len) {
1011 int nb_audio = (prmh->stat[i] >> FIELD_SIZE) & MASK_FIRST_FIELD; 1070 int nb_audio = ((prmh->stat[i] >> FIELD_SIZE) &
1012 int nb_stream = (prmh->stat[i] >> (2*FIELD_SIZE)) & MASK_FIRST_FIELD; 1071 MASK_FIRST_FIELD);
1072 int nb_stream = ((prmh->stat[i] >> (2*FIELD_SIZE)) &
1073 MASK_FIRST_FIELD);
1013 int pipe = prmh->stat[i] & MASK_FIRST_FIELD; 1074 int pipe = prmh->stat[i] & MASK_FIRST_FIELD;
1014 int is_capture = prmh->stat[i] & 0x400000; 1075 int is_capture = prmh->stat[i] & 0x400000;
1015 u32 err2; 1076 u32 err2;
1016 1077
1017 if (prmh->stat[i] & 0x800000) { /* if BIT_END */ 1078 if (prmh->stat[i] & 0x800000) { /* if BIT_END */
1018 snd_printdd("TASKLET : End%sPipe %d\n", 1079 snd_printdd("TASKLET : End%sPipe %d\n",
1019 is_capture ? "Record" : "Play", pipe); 1080 is_capture ? "Record" : "Play",
1081 pipe);
1020 } 1082 }
1021 i++; 1083 i++;
1022 err2 = prmh->stat[i] ? prmh->stat[i] : prmh->stat[i+1]; 1084 err2 = prmh->stat[i] ? prmh->stat[i] : prmh->stat[i+1];
@@ -1062,7 +1124,7 @@ static u_int64_t pcxhr_stream_read_position(struct pcxhr_mgr *mgr,
1062 pcxhr_init_rmh(&rmh, CMD_STREAM_SAMPLE_COUNT); 1124 pcxhr_init_rmh(&rmh, CMD_STREAM_SAMPLE_COUNT);
1063 pcxhr_set_pipe_cmd_params(&rmh, stream->pipe->is_capture, 1125 pcxhr_set_pipe_cmd_params(&rmh, stream->pipe->is_capture,
1064 stream->pipe->first_audio, 0, stream_mask); 1126 stream->pipe->first_audio, 0, stream_mask);
1065 /* rmh.stat_len = 2; */ /* 2 resp data for each stream of the pipe */ 1127 /* rmh.stat_len = 2; */ /* 2 resp data for each stream of the pipe */
1066 1128
1067 err = pcxhr_send_msg(mgr, &rmh); 1129 err = pcxhr_send_msg(mgr, &rmh);
1068 if (err) 1130 if (err)
@@ -1072,18 +1134,21 @@ static u_int64_t pcxhr_stream_read_position(struct pcxhr_mgr *mgr,
1072 hw_sample_count += (u_int64_t)rmh.stat[1]; 1134 hw_sample_count += (u_int64_t)rmh.stat[1];
1073 1135
1074 snd_printdd("stream %c%d : abs samples real(%ld) timer(%ld)\n", 1136 snd_printdd("stream %c%d : abs samples real(%ld) timer(%ld)\n",
1075 stream->pipe->is_capture ? 'C':'P', stream->substream->number, 1137 stream->pipe->is_capture ? 'C' : 'P',
1138 stream->substream->number,
1076 (long unsigned int)hw_sample_count, 1139 (long unsigned int)hw_sample_count,
1077 (long unsigned int)(stream->timer_abs_periods + 1140 (long unsigned int)(stream->timer_abs_periods +
1078 stream->timer_period_frag + PCXHR_GRANULARITY)); 1141 stream->timer_period_frag +
1079 1142 mgr->granularity));
1080 return hw_sample_count; 1143 return hw_sample_count;
1081} 1144}
1082 1145
1083static void pcxhr_update_timer_pos(struct pcxhr_mgr *mgr, 1146static void pcxhr_update_timer_pos(struct pcxhr_mgr *mgr,
1084 struct pcxhr_stream *stream, int samples_to_add) 1147 struct pcxhr_stream *stream,
1148 int samples_to_add)
1085{ 1149{
1086 if (stream->substream && (stream->status == PCXHR_STREAM_STATUS_RUNNING)) { 1150 if (stream->substream &&
1151 (stream->status == PCXHR_STREAM_STATUS_RUNNING)) {
1087 u_int64_t new_sample_count; 1152 u_int64_t new_sample_count;
1088 int elapsed = 0; 1153 int elapsed = 0;
1089 int hardware_read = 0; 1154 int hardware_read = 0;
@@ -1092,20 +1157,22 @@ static void pcxhr_update_timer_pos(struct pcxhr_mgr *mgr,
1092 if (samples_to_add < 0) { 1157 if (samples_to_add < 0) {
1093 stream->timer_is_synced = 0; 1158 stream->timer_is_synced = 0;
1094 /* add default if no hardware_read possible */ 1159 /* add default if no hardware_read possible */
1095 samples_to_add = PCXHR_GRANULARITY; 1160 samples_to_add = mgr->granularity;
1096 } 1161 }
1097 1162
1098 if (!stream->timer_is_synced) { 1163 if (!stream->timer_is_synced) {
1099 if (stream->timer_abs_periods != 0 || 1164 if ((stream->timer_abs_periods != 0) ||
1100 stream->timer_period_frag + PCXHR_GRANULARITY >= 1165 ((stream->timer_period_frag + samples_to_add) >=
1101 runtime->period_size) { 1166 runtime->period_size)) {
1102 new_sample_count = pcxhr_stream_read_position(mgr, stream); 1167 new_sample_count =
1168 pcxhr_stream_read_position(mgr, stream);
1103 hardware_read = 1; 1169 hardware_read = 1;
1104 if (new_sample_count >= PCXHR_GRANULARITY_MIN) { 1170 if (new_sample_count >= mgr->granularity) {
1105 /* sub security offset because of jitter and 1171 /* sub security offset because of
1106 * finer granularity of dsp time (MBOX4) 1172 * jitter and finer granularity of
1173 * dsp time (MBOX4)
1107 */ 1174 */
1108 new_sample_count -= PCXHR_GRANULARITY_MIN; 1175 new_sample_count -= mgr->granularity;
1109 stream->timer_is_synced = 1; 1176 stream->timer_is_synced = 1;
1110 } 1177 }
1111 } 1178 }
@@ -1128,12 +1195,15 @@ static void pcxhr_update_timer_pos(struct pcxhr_mgr *mgr,
1128 stream->timer_buf_periods = 0; 1195 stream->timer_buf_periods = 0;
1129 stream->timer_abs_periods = new_elapse_pos; 1196 stream->timer_abs_periods = new_elapse_pos;
1130 } 1197 }
1131 if (new_sample_count >= stream->timer_abs_periods) 1198 if (new_sample_count >= stream->timer_abs_periods) {
1132 stream->timer_period_frag = (u_int32_t)(new_sample_count - 1199 stream->timer_period_frag =
1133 stream->timer_abs_periods); 1200 (u_int32_t)(new_sample_count -
1134 else 1201 stream->timer_abs_periods);
1135 snd_printk(KERN_ERR "ERROR new_sample_count too small ??? %lx\n", 1202 } else {
1203 snd_printk(KERN_ERR
1204 "ERROR new_sample_count too small ??? %ld\n",
1136 (long unsigned int)new_sample_count); 1205 (long unsigned int)new_sample_count);
1206 }
1137 1207
1138 if (elapsed) { 1208 if (elapsed) {
1139 spin_unlock(&mgr->lock); 1209 spin_unlock(&mgr->lock);
@@ -1143,7 +1213,6 @@ static void pcxhr_update_timer_pos(struct pcxhr_mgr *mgr,
1143 } 1213 }
1144} 1214}
1145 1215
1146
1147irqreturn_t pcxhr_interrupt(int irq, void *dev_id) 1216irqreturn_t pcxhr_interrupt(int irq, void *dev_id)
1148{ 1217{
1149 struct pcxhr_mgr *mgr = dev_id; 1218 struct pcxhr_mgr *mgr = dev_id;
@@ -1156,7 +1225,8 @@ irqreturn_t pcxhr_interrupt(int irq, void *dev_id)
1156 reg = PCXHR_INPL(mgr, PCXHR_PLX_IRQCS); 1225 reg = PCXHR_INPL(mgr, PCXHR_PLX_IRQCS);
1157 if (! (reg & PCXHR_IRQCS_ACTIVE_PCIDB)) { 1226 if (! (reg & PCXHR_IRQCS_ACTIVE_PCIDB)) {
1158 spin_unlock(&mgr->lock); 1227 spin_unlock(&mgr->lock);
1159 return IRQ_NONE; /* this device did not cause the interrupt */ 1228 /* this device did not cause the interrupt */
1229 return IRQ_NONE;
1160 } 1230 }
1161 1231
1162 /* clear interrupt */ 1232 /* clear interrupt */
@@ -1167,10 +1237,12 @@ irqreturn_t pcxhr_interrupt(int irq, void *dev_id)
1167 if (reg & PCXHR_IRQ_TIMER) { 1237 if (reg & PCXHR_IRQ_TIMER) {
1168 int timer_toggle = reg & PCXHR_IRQ_TIMER; 1238 int timer_toggle = reg & PCXHR_IRQ_TIMER;
1169 /* is a 24 bit counter */ 1239 /* is a 24 bit counter */
1170 int dsp_time_new = PCXHR_INPL(mgr, PCXHR_PLX_MBOX4) & PCXHR_DSP_TIME_MASK; 1240 int dsp_time_new =
1241 PCXHR_INPL(mgr, PCXHR_PLX_MBOX4) & PCXHR_DSP_TIME_MASK;
1171 int dsp_time_diff = dsp_time_new - mgr->dsp_time_last; 1242 int dsp_time_diff = dsp_time_new - mgr->dsp_time_last;
1172 1243
1173 if (dsp_time_diff < 0 && mgr->dsp_time_last != PCXHR_DSP_TIME_INVALID) { 1244 if ((dsp_time_diff < 0) &&
1245 (mgr->dsp_time_last != PCXHR_DSP_TIME_INVALID)) {
1174 snd_printdd("ERROR DSP TIME old(%d) new(%d) -> " 1246 snd_printdd("ERROR DSP TIME old(%d) new(%d) -> "
1175 "resynchronize all streams\n", 1247 "resynchronize all streams\n",
1176 mgr->dsp_time_last, dsp_time_new); 1248 mgr->dsp_time_last, dsp_time_new);
@@ -1178,40 +1250,49 @@ irqreturn_t pcxhr_interrupt(int irq, void *dev_id)
1178 } 1250 }
1179#ifdef CONFIG_SND_DEBUG_VERBOSE 1251#ifdef CONFIG_SND_DEBUG_VERBOSE
1180 if (dsp_time_diff == 0) 1252 if (dsp_time_diff == 0)
1181 snd_printdd("ERROR DSP TIME NO DIFF time(%d)\n", dsp_time_new); 1253 snd_printdd("ERROR DSP TIME NO DIFF time(%d)\n",
1182 else if (dsp_time_diff >= (2*PCXHR_GRANULARITY)) 1254 dsp_time_new);
1255 else if (dsp_time_diff >= (2*mgr->granularity))
1183 snd_printdd("ERROR DSP TIME TOO BIG old(%d) add(%d)\n", 1256 snd_printdd("ERROR DSP TIME TOO BIG old(%d) add(%d)\n",
1184 mgr->dsp_time_last, dsp_time_new - mgr->dsp_time_last); 1257 mgr->dsp_time_last,
1258 dsp_time_new - mgr->dsp_time_last);
1259 else if (dsp_time_diff % mgr->granularity)
1260 snd_printdd("ERROR DSP TIME increased by %d\n",
1261 dsp_time_diff);
1185#endif 1262#endif
1186 mgr->dsp_time_last = dsp_time_new; 1263 mgr->dsp_time_last = dsp_time_new;
1187 1264
1188 if (timer_toggle == mgr->timer_toggle) 1265 if (timer_toggle == mgr->timer_toggle) {
1189 snd_printdd("ERROR TIMER TOGGLE\n"); 1266 snd_printdd("ERROR TIMER TOGGLE\n");
1267 mgr->dsp_time_err++;
1268 }
1190 mgr->timer_toggle = timer_toggle; 1269 mgr->timer_toggle = timer_toggle;
1191 1270
1192 reg &= ~PCXHR_IRQ_TIMER; 1271 reg &= ~PCXHR_IRQ_TIMER;
1193 for (i = 0; i < mgr->num_cards; i++) { 1272 for (i = 0; i < mgr->num_cards; i++) {
1194 chip = mgr->chip[i]; 1273 chip = mgr->chip[i];
1195 for (j = 0; j < chip->nb_streams_capt; j++) 1274 for (j = 0; j < chip->nb_streams_capt; j++)
1196 pcxhr_update_timer_pos(mgr, &chip->capture_stream[j], 1275 pcxhr_update_timer_pos(mgr,
1197 dsp_time_diff); 1276 &chip->capture_stream[j],
1277 dsp_time_diff);
1198 } 1278 }
1199 for (i = 0; i < mgr->num_cards; i++) { 1279 for (i = 0; i < mgr->num_cards; i++) {
1200 chip = mgr->chip[i]; 1280 chip = mgr->chip[i];
1201 for (j = 0; j < chip->nb_streams_play; j++) 1281 for (j = 0; j < chip->nb_streams_play; j++)
1202 pcxhr_update_timer_pos(mgr, &chip->playback_stream[j], 1282 pcxhr_update_timer_pos(mgr,
1203 dsp_time_diff); 1283 &chip->playback_stream[j],
1284 dsp_time_diff);
1204 } 1285 }
1205 } 1286 }
1206 /* other irq's handled in the tasklet */ 1287 /* other irq's handled in the tasklet */
1207 if (reg & PCXHR_IRQ_MASK) { 1288 if (reg & PCXHR_IRQ_MASK) {
1208 1289 if (reg & PCXHR_IRQ_ASYNC) {
1209 /* as we didn't request any notifications, some kind of xrun error 1290 /* as we didn't request any async notifications,
1210 * will probably occured 1291 * some kind of xrun error will probably occured
1211 */ 1292 */
1212 /* better resynchronize all streams next interrupt : */ 1293 /* better resynchronize all streams next interrupt : */
1213 mgr->dsp_time_last = PCXHR_DSP_TIME_INVALID; 1294 mgr->dsp_time_last = PCXHR_DSP_TIME_INVALID;
1214 1295 }
1215 mgr->src_it_dsp = reg; 1296 mgr->src_it_dsp = reg;
1216 tasklet_schedule(&mgr->msg_taskq); 1297 tasklet_schedule(&mgr->msg_taskq);
1217 } 1298 }
diff --git a/sound/pci/pcxhr/pcxhr_core.h b/sound/pci/pcxhr/pcxhr_core.h
index d9a4ab609875..bbbd66d13a64 100644
--- a/sound/pci/pcxhr/pcxhr_core.h
+++ b/sound/pci/pcxhr/pcxhr_core.h
@@ -65,7 +65,7 @@ enum {
65 CMD_RESYNC_AUDIO_INPUTS, /* cmd_len = 1 stat_len = 0 */ 65 CMD_RESYNC_AUDIO_INPUTS, /* cmd_len = 1 stat_len = 0 */
66 CMD_GET_DSP_RESOURCES, /* cmd_len = 1 stat_len = 4 */ 66 CMD_GET_DSP_RESOURCES, /* cmd_len = 1 stat_len = 4 */
67 CMD_SET_TIMER_INTERRUPT, /* cmd_len = 1 stat_len = 0 */ 67 CMD_SET_TIMER_INTERRUPT, /* cmd_len = 1 stat_len = 0 */
68 CMD_RES_PIPE, /* cmd_len = 2 stat_len = 0 */ 68 CMD_RES_PIPE, /* cmd_len >=2 stat_len = 0 */
69 CMD_FREE_PIPE, /* cmd_len = 1 stat_len = 0 */ 69 CMD_FREE_PIPE, /* cmd_len = 1 stat_len = 0 */
70 CMD_CONF_PIPE, /* cmd_len = 2 stat_len = 0 */ 70 CMD_CONF_PIPE, /* cmd_len = 2 stat_len = 0 */
71 CMD_STOP_PIPE, /* cmd_len = 1 stat_len = 0 */ 71 CMD_STOP_PIPE, /* cmd_len = 1 stat_len = 0 */
@@ -96,6 +96,8 @@ void pcxhr_init_rmh(struct pcxhr_rmh *rmh, int cmd);
96void pcxhr_set_pipe_cmd_params(struct pcxhr_rmh* rmh, int capture, unsigned int param1, 96void pcxhr_set_pipe_cmd_params(struct pcxhr_rmh* rmh, int capture, unsigned int param1,
97 unsigned int param2, unsigned int param3); 97 unsigned int param2, unsigned int param3);
98 98
99#define DSP_EXT_CMD_SET(x) (x->dsp_version > 0x012800)
100
99/* 101/*
100 send the rmh 102 send the rmh
101 */ 103 */
@@ -110,6 +112,7 @@ int pcxhr_send_msg(struct pcxhr_mgr *mgr, struct pcxhr_rmh *rmh);
110#define IO_NUM_REG_STATUS 5 112#define IO_NUM_REG_STATUS 5
111#define IO_NUM_REG_CUER 10 113#define IO_NUM_REG_CUER 10
112#define IO_NUM_UER_CHIP_REG 11 114#define IO_NUM_UER_CHIP_REG 11
115#define IO_NUM_REG_CONFIG_SRC 12
113#define IO_NUM_REG_OUT_ANA_LEVEL 20 116#define IO_NUM_REG_OUT_ANA_LEVEL 20
114#define IO_NUM_REG_IN_ANA_LEVEL 21 117#define IO_NUM_REG_IN_ANA_LEVEL 21
115 118
diff --git a/sound/pci/pcxhr/pcxhr_hwdep.c b/sound/pci/pcxhr/pcxhr_hwdep.c
index 96640d9c227d..592743a298b0 100644
--- a/sound/pci/pcxhr/pcxhr_hwdep.c
+++ b/sound/pci/pcxhr/pcxhr_hwdep.c
@@ -31,6 +31,7 @@
31#include "pcxhr_mixer.h" 31#include "pcxhr_mixer.h"
32#include "pcxhr_hwdep.h" 32#include "pcxhr_hwdep.h"
33#include "pcxhr_core.h" 33#include "pcxhr_core.h"
34#include "pcxhr_mix22.h"
34 35
35 36
36#if defined(CONFIG_FW_LOADER) || defined(CONFIG_FW_LOADER_MODULE) 37#if defined(CONFIG_FW_LOADER) || defined(CONFIG_FW_LOADER_MODULE)
@@ -40,10 +41,10 @@
40#endif 41#endif
41 42
42 43
44static int pcxhr_sub_init(struct pcxhr_mgr *mgr);
43/* 45/*
44 * get basic information and init pcxhr card 46 * get basic information and init pcxhr card
45 */ 47 */
46
47static int pcxhr_init_board(struct pcxhr_mgr *mgr) 48static int pcxhr_init_board(struct pcxhr_mgr *mgr)
48{ 49{
49 int err; 50 int err;
@@ -68,7 +69,7 @@ static int pcxhr_init_board(struct pcxhr_mgr *mgr)
68 if ((rmh.stat[0] & MASK_FIRST_FIELD) != mgr->playback_chips * 2) 69 if ((rmh.stat[0] & MASK_FIRST_FIELD) != mgr->playback_chips * 2)
69 return -EINVAL; 70 return -EINVAL;
70 /* test 8 or 2 phys in */ 71 /* test 8 or 2 phys in */
71 if (((rmh.stat[0] >> (2 * FIELD_SIZE)) & MASK_FIRST_FIELD) != 72 if (((rmh.stat[0] >> (2 * FIELD_SIZE)) & MASK_FIRST_FIELD) <
72 mgr->capture_chips * 2) 73 mgr->capture_chips * 2)
73 return -EINVAL; 74 return -EINVAL;
74 /* test max nb substream per board */ 75 /* test max nb substream per board */
@@ -77,20 +78,34 @@ static int pcxhr_init_board(struct pcxhr_mgr *mgr)
77 /* test max nb substream per pipe */ 78 /* test max nb substream per pipe */
78 if (((rmh.stat[1] >> 7) & 0x5F) < PCXHR_PLAYBACK_STREAMS) 79 if (((rmh.stat[1] >> 7) & 0x5F) < PCXHR_PLAYBACK_STREAMS)
79 return -EINVAL; 80 return -EINVAL;
81 snd_printdd("supported formats : playback=%x capture=%x\n",
82 rmh.stat[2], rmh.stat[3]);
80 83
81 pcxhr_init_rmh(&rmh, CMD_VERSION); 84 pcxhr_init_rmh(&rmh, CMD_VERSION);
82 /* firmware num for DSP */ 85 /* firmware num for DSP */
83 rmh.cmd[0] |= mgr->firmware_num; 86 rmh.cmd[0] |= mgr->firmware_num;
84 /* transfer granularity in samples (should be multiple of 48) */ 87 /* transfer granularity in samples (should be multiple of 48) */
85 rmh.cmd[1] = (1<<23) + PCXHR_GRANULARITY; 88 rmh.cmd[1] = (1<<23) + mgr->granularity;
86 rmh.cmd_len = 2; 89 rmh.cmd_len = 2;
87 err = pcxhr_send_msg(mgr, &rmh); 90 err = pcxhr_send_msg(mgr, &rmh);
88 if (err) 91 if (err)
89 return err; 92 return err;
90 snd_printdd("PCXHR DSP version is %d.%d.%d\n", 93 snd_printdd("PCXHR DSP version is %d.%d.%d\n", (rmh.stat[0]>>16)&0xff,
91 (rmh.stat[0]>>16)&0xff, (rmh.stat[0]>>8)&0xff, rmh.stat[0]&0xff); 94 (rmh.stat[0]>>8)&0xff, rmh.stat[0]&0xff);
92 mgr->dsp_version = rmh.stat[0]; 95 mgr->dsp_version = rmh.stat[0];
93 96
97 if (mgr->is_hr_stereo)
98 err = hr222_sub_init(mgr);
99 else
100 err = pcxhr_sub_init(mgr);
101 return err;
102}
103
104static int pcxhr_sub_init(struct pcxhr_mgr *mgr)
105{
106 int err;
107 struct pcxhr_rmh rmh;
108
94 /* get options */ 109 /* get options */
95 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_READ); 110 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_READ);
96 rmh.cmd[0] |= IO_NUM_REG_STATUS; 111 rmh.cmd[0] |= IO_NUM_REG_STATUS;
@@ -100,20 +115,22 @@ static int pcxhr_init_board(struct pcxhr_mgr *mgr)
100 if (err) 115 if (err)
101 return err; 116 return err;
102 117
103 if ((rmh.stat[1] & REG_STATUS_OPT_DAUGHTER_MASK) == REG_STATUS_OPT_ANALOG_BOARD) 118 if ((rmh.stat[1] & REG_STATUS_OPT_DAUGHTER_MASK) ==
104 mgr->board_has_analog = 1; /* analog addon board available */ 119 REG_STATUS_OPT_ANALOG_BOARD)
105 else 120 mgr->board_has_analog = 1; /* analog addon board found */
106 /* analog addon board not available -> no support for instance */
107 return -EINVAL;
108 121
109 /* unmute inputs */ 122 /* unmute inputs */
110 err = pcxhr_write_io_num_reg_cont(mgr, REG_CONT_UNMUTE_INPUTS, 123 err = pcxhr_write_io_num_reg_cont(mgr, REG_CONT_UNMUTE_INPUTS,
111 REG_CONT_UNMUTE_INPUTS, NULL); 124 REG_CONT_UNMUTE_INPUTS, NULL);
112 if (err) 125 if (err)
113 return err; 126 return err;
114 /* unmute outputs */ 127 /* unmute outputs (a write to IO_NUM_REG_MUTE_OUT mutes!) */
115 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_READ); /* a write to IO_NUM_REG_MUTE_OUT mutes! */ 128 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_READ);
116 rmh.cmd[0] |= IO_NUM_REG_MUTE_OUT; 129 rmh.cmd[0] |= IO_NUM_REG_MUTE_OUT;
130 if (DSP_EXT_CMD_SET(mgr)) {
131 rmh.cmd[1] = 1; /* unmute digital plugs */
132 rmh.cmd_len = 2;
133 }
117 err = pcxhr_send_msg(mgr, &rmh); 134 err = pcxhr_send_msg(mgr, &rmh);
118 return err; 135 return err;
119} 136}
@@ -124,19 +141,25 @@ void pcxhr_reset_board(struct pcxhr_mgr *mgr)
124 141
125 if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)) { 142 if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)) {
126 /* mute outputs */ 143 /* mute outputs */
144 if (!mgr->is_hr_stereo) {
127 /* a read to IO_NUM_REG_MUTE_OUT register unmutes! */ 145 /* a read to IO_NUM_REG_MUTE_OUT register unmutes! */
128 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE); 146 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE);
129 rmh.cmd[0] |= IO_NUM_REG_MUTE_OUT; 147 rmh.cmd[0] |= IO_NUM_REG_MUTE_OUT;
130 pcxhr_send_msg(mgr, &rmh); 148 pcxhr_send_msg(mgr, &rmh);
131 /* mute inputs */ 149 /* mute inputs */
132 pcxhr_write_io_num_reg_cont(mgr, REG_CONT_UNMUTE_INPUTS, 0, NULL); 150 pcxhr_write_io_num_reg_cont(mgr, REG_CONT_UNMUTE_INPUTS,
151 0, NULL);
152 }
153 /* stereo cards mute with reset of dsp */
133 } 154 }
134 /* reset pcxhr dsp */ 155 /* reset pcxhr dsp */
135 if (mgr->dsp_loaded & ( 1 << PCXHR_FIRMWARE_DSP_EPRM_INDEX)) 156 if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_EPRM_INDEX))
136 pcxhr_reset_dsp(mgr); 157 pcxhr_reset_dsp(mgr);
137 /* reset second xilinx */ 158 /* reset second xilinx */
138 if (mgr->dsp_loaded & ( 1 << PCXHR_FIRMWARE_XLX_COM_INDEX)) 159 if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_XLX_COM_INDEX)) {
139 pcxhr_reset_xilinx_com(mgr); 160 pcxhr_reset_xilinx_com(mgr);
161 mgr->dsp_loaded = 1;
162 }
140 return; 163 return;
141} 164}
142 165
@@ -144,8 +167,9 @@ void pcxhr_reset_board(struct pcxhr_mgr *mgr)
144/* 167/*
145 * allocate a playback/capture pipe (pcmp0/pcmc0) 168 * allocate a playback/capture pipe (pcmp0/pcmc0)
146 */ 169 */
147static int pcxhr_dsp_allocate_pipe( struct pcxhr_mgr *mgr, struct pcxhr_pipe *pipe, 170static int pcxhr_dsp_allocate_pipe(struct pcxhr_mgr *mgr,
148 int is_capture, int pin) 171 struct pcxhr_pipe *pipe,
172 int is_capture, int pin)
149{ 173{
150 int stream_count, audio_count; 174 int stream_count, audio_count;
151 int err; 175 int err;
@@ -161,15 +185,23 @@ static int pcxhr_dsp_allocate_pipe( struct pcxhr_mgr *mgr, struct pcxhr_pipe *pi
161 stream_count = PCXHR_PLAYBACK_STREAMS; 185 stream_count = PCXHR_PLAYBACK_STREAMS;
162 audio_count = 2; /* always stereo */ 186 audio_count = 2; /* always stereo */
163 } 187 }
164 snd_printdd("snd_add_ref_pipe pin(%d) pcm%c0\n", pin, is_capture ? 'c' : 'p'); 188 snd_printdd("snd_add_ref_pipe pin(%d) pcm%c0\n",
189 pin, is_capture ? 'c' : 'p');
165 pipe->is_capture = is_capture; 190 pipe->is_capture = is_capture;
166 pipe->first_audio = pin; 191 pipe->first_audio = pin;
167 /* define pipe (P_PCM_ONLY_MASK (0x020000) is not necessary) */ 192 /* define pipe (P_PCM_ONLY_MASK (0x020000) is not necessary) */
168 pcxhr_init_rmh(&rmh, CMD_RES_PIPE); 193 pcxhr_init_rmh(&rmh, CMD_RES_PIPE);
169 pcxhr_set_pipe_cmd_params(&rmh, is_capture, pin, audio_count, stream_count); 194 pcxhr_set_pipe_cmd_params(&rmh, is_capture, pin,
195 audio_count, stream_count);
196 rmh.cmd[1] |= 0x020000; /* add P_PCM_ONLY_MASK */
197 if (DSP_EXT_CMD_SET(mgr)) {
198 /* add channel mask to command */
199 rmh.cmd[rmh.cmd_len++] = (audio_count == 1) ? 0x01 : 0x03;
200 }
170 err = pcxhr_send_msg(mgr, &rmh); 201 err = pcxhr_send_msg(mgr, &rmh);
171 if (err < 0) { 202 if (err < 0) {
172 snd_printk(KERN_ERR "error pipe allocation (CMD_RES_PIPE) err=%x!\n", err ); 203 snd_printk(KERN_ERR "error pipe allocation "
204 "(CMD_RES_PIPE) err=%x!\n", err);
173 return err; 205 return err;
174 } 206 }
175 pipe->status = PCXHR_PIPE_DEFINED; 207 pipe->status = PCXHR_PIPE_DEFINED;
@@ -199,10 +231,12 @@ static int pcxhr_dsp_free_pipe( struct pcxhr_mgr *mgr, struct pcxhr_pipe *pipe)
199 snd_printk(KERN_ERR "error stopping pipe!\n"); 231 snd_printk(KERN_ERR "error stopping pipe!\n");
200 /* release the pipe */ 232 /* release the pipe */
201 pcxhr_init_rmh(&rmh, CMD_FREE_PIPE); 233 pcxhr_init_rmh(&rmh, CMD_FREE_PIPE);
202 pcxhr_set_pipe_cmd_params(&rmh, pipe->is_capture, pipe->first_audio, 0, 0); 234 pcxhr_set_pipe_cmd_params(&rmh, pipe->is_capture, pipe->first_audio,
235 0, 0);
203 err = pcxhr_send_msg(mgr, &rmh); 236 err = pcxhr_send_msg(mgr, &rmh);
204 if (err < 0) 237 if (err < 0)
205 snd_printk(KERN_ERR "error pipe release (CMD_FREE_PIPE) err(%x)\n", err); 238 snd_printk(KERN_ERR "error pipe release "
239 "(CMD_FREE_PIPE) err(%x)\n", err);
206 pipe->status = PCXHR_PIPE_UNDEFINED; 240 pipe->status = PCXHR_PIPE_UNDEFINED;
207 return err; 241 return err;
208} 242}
@@ -248,15 +282,16 @@ static int pcxhr_start_pipes(struct pcxhr_mgr *mgr)
248 for (i = 0; i < mgr->num_cards; i++) { 282 for (i = 0; i < mgr->num_cards; i++) {
249 chip = mgr->chip[i]; 283 chip = mgr->chip[i];
250 if (chip->nb_streams_play) 284 if (chip->nb_streams_play)
251 playback_mask |= (1 << chip->playback_pipe.first_audio); 285 playback_mask |= 1 << chip->playback_pipe.first_audio;
252 for (j = 0; j < chip->nb_streams_capt; j++) 286 for (j = 0; j < chip->nb_streams_capt; j++)
253 capture_mask |= (1 << chip->capture_pipe[j].first_audio); 287 capture_mask |= 1 << chip->capture_pipe[j].first_audio;
254 } 288 }
255 return pcxhr_set_pipe_state(mgr, playback_mask, capture_mask, 1); 289 return pcxhr_set_pipe_state(mgr, playback_mask, capture_mask, 1);
256} 290}
257 291
258 292
259static int pcxhr_dsp_load(struct pcxhr_mgr *mgr, int index, const struct firmware *dsp) 293static int pcxhr_dsp_load(struct pcxhr_mgr *mgr, int index,
294 const struct firmware *dsp)
260{ 295{
261 int err, card_index; 296 int err, card_index;
262 297
@@ -330,22 +365,33 @@ static int pcxhr_dsp_load(struct pcxhr_mgr *mgr, int index, const struct firmwar
330 365
331int pcxhr_setup_firmware(struct pcxhr_mgr *mgr) 366int pcxhr_setup_firmware(struct pcxhr_mgr *mgr)
332{ 367{
333 static char *fw_files[5] = { 368 static char *fw_files[][5] = {
334 "xi_1_882.dat", 369 [0] = { "xlxint.dat", "xlxc882hr.dat",
335 "xc_1_882.dat", 370 "dspe882.e56", "dspb882hr.b56", "dspd882.d56" },
336 "e321_512.e56", 371 [1] = { "xlxint.dat", "xlxc882e.dat",
337 "b321_512.b56", 372 "dspe882.e56", "dspb882e.b56", "dspd882.d56" },
338 "d321_512.d56" 373 [2] = { "xlxint.dat", "xlxc1222hr.dat",
374 "dspe882.e56", "dspb1222hr.b56", "dspd1222.d56" },
375 [3] = { "xlxint.dat", "xlxc1222e.dat",
376 "dspe882.e56", "dspb1222e.b56", "dspd1222.d56" },
377 [4] = { NULL, "xlxc222.dat",
378 "dspe924.e56", "dspb924.b56", "dspd222.d56" },
379 [5] = { NULL, "xlxc924.dat",
380 "dspe924.e56", "dspb924.b56", "dspd222.d56" },
339 }; 381 };
340 char path[32]; 382 char path[32];
341 383
342 const struct firmware *fw_entry; 384 const struct firmware *fw_entry;
343 int i, err; 385 int i, err;
386 int fw_set = mgr->fw_file_set;
344 387
345 for (i = 0; i < ARRAY_SIZE(fw_files); i++) { 388 for (i = 0; i < 5; i++) {
346 sprintf(path, "pcxhr/%s", fw_files[i]); 389 if (!fw_files[fw_set][i])
390 continue;
391 sprintf(path, "pcxhr/%s", fw_files[fw_set][i]);
347 if (request_firmware(&fw_entry, path, &mgr->pci->dev)) { 392 if (request_firmware(&fw_entry, path, &mgr->pci->dev)) {
348 snd_printk(KERN_ERR "pcxhr: can't load firmware %s\n", path); 393 snd_printk(KERN_ERR "pcxhr: can't load firmware %s\n",
394 path);
349 return -ENOENT; 395 return -ENOENT;
350 } 396 }
351 /* fake hwdep dsp record */ 397 /* fake hwdep dsp record */
@@ -358,11 +404,26 @@ int pcxhr_setup_firmware(struct pcxhr_mgr *mgr)
358 return 0; 404 return 0;
359} 405}
360 406
361MODULE_FIRMWARE("pcxhr/xi_1_882.dat"); 407MODULE_FIRMWARE("pcxhr/xlxint.dat");
362MODULE_FIRMWARE("pcxhr/xc_1_882.dat"); 408MODULE_FIRMWARE("pcxhr/xlxc882hr.dat");
363MODULE_FIRMWARE("pcxhr/e321_512.e56"); 409MODULE_FIRMWARE("pcxhr/xlxc882e.dat");
364MODULE_FIRMWARE("pcxhr/b321_512.b56"); 410MODULE_FIRMWARE("pcxhr/dspe882.e56");
365MODULE_FIRMWARE("pcxhr/d321_512.d56"); 411MODULE_FIRMWARE("pcxhr/dspb882hr.b56");
412MODULE_FIRMWARE("pcxhr/dspb882e.b56");
413MODULE_FIRMWARE("pcxhr/dspd882.d56");
414
415MODULE_FIRMWARE("pcxhr/xlxc1222hr.dat");
416MODULE_FIRMWARE("pcxhr/xlxc1222e.dat");
417MODULE_FIRMWARE("pcxhr/dspb1222hr.b56");
418MODULE_FIRMWARE("pcxhr/dspb1222e.b56");
419MODULE_FIRMWARE("pcxhr/dspd1222.d56");
420
421MODULE_FIRMWARE("pcxhr/xlxc222.dat");
422MODULE_FIRMWARE("pcxhr/xlxc924.dat");
423MODULE_FIRMWARE("pcxhr/dspe924.e56");
424MODULE_FIRMWARE("pcxhr/dspb924.b56");
425MODULE_FIRMWARE("pcxhr/dspd222.d56");
426
366 427
367#else /* old style firmware loading */ 428#else /* old style firmware loading */
368 429
@@ -373,7 +434,8 @@ MODULE_FIRMWARE("pcxhr/d321_512.d56");
373static int pcxhr_hwdep_dsp_status(struct snd_hwdep *hw, 434static int pcxhr_hwdep_dsp_status(struct snd_hwdep *hw,
374 struct snd_hwdep_dsp_status *info) 435 struct snd_hwdep_dsp_status *info)
375{ 436{
376 strcpy(info->id, "pcxhr"); 437 struct pcxhr_mgr *mgr = hw->private_data;
438 sprintf(info->id, "pcxhr%d", mgr->fw_file_set);
377 info->num_dsps = PCXHR_FIRMWARE_FILES_MAX_INDEX; 439 info->num_dsps = PCXHR_FIRMWARE_FILES_MAX_INDEX;
378 440
379 if (hw->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)) 441 if (hw->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX))
@@ -393,8 +455,8 @@ static int pcxhr_hwdep_dsp_load(struct snd_hwdep *hw,
393 fw.size = dsp->length; 455 fw.size = dsp->length;
394 fw.data = vmalloc(fw.size); 456 fw.data = vmalloc(fw.size);
395 if (! fw.data) { 457 if (! fw.data) {
396 snd_printk(KERN_ERR "pcxhr: cannot allocate dsp image (%lu bytes)\n", 458 snd_printk(KERN_ERR "pcxhr: cannot allocate dsp image "
397 (unsigned long)fw.size); 459 "(%lu bytes)\n", (unsigned long)fw.size);
398 return -ENOMEM; 460 return -ENOMEM;
399 } 461 }
400 if (copy_from_user((void *)fw.data, dsp->image, dsp->length)) { 462 if (copy_from_user((void *)fw.data, dsp->image, dsp->length)) {
@@ -424,8 +486,11 @@ int pcxhr_setup_firmware(struct pcxhr_mgr *mgr)
424 int err; 486 int err;
425 struct snd_hwdep *hw; 487 struct snd_hwdep *hw;
426 488
427 /* only create hwdep interface for first cardX (see "index" module parameter)*/ 489 /* only create hwdep interface for first cardX
428 if ((err = snd_hwdep_new(mgr->chip[0]->card, PCXHR_HWDEP_ID, 0, &hw)) < 0) 490 * (see "index" module parameter)
491 */
492 err = snd_hwdep_new(mgr->chip[0]->card, PCXHR_HWDEP_ID, 0, &hw);
493 if (err < 0)
429 return err; 494 return err;
430 495
431 hw->iface = SNDRV_HWDEP_IFACE_PCXHR; 496 hw->iface = SNDRV_HWDEP_IFACE_PCXHR;
@@ -435,10 +500,13 @@ int pcxhr_setup_firmware(struct pcxhr_mgr *mgr)
435 hw->ops.dsp_status = pcxhr_hwdep_dsp_status; 500 hw->ops.dsp_status = pcxhr_hwdep_dsp_status;
436 hw->ops.dsp_load = pcxhr_hwdep_dsp_load; 501 hw->ops.dsp_load = pcxhr_hwdep_dsp_load;
437 hw->exclusive = 1; 502 hw->exclusive = 1;
503 /* stereo cards don't need fw_file_0 -> dsp_loaded = 1 */
504 hw->dsp_loaded = mgr->is_hr_stereo ? 1 : 0;
438 mgr->dsp_loaded = 0; 505 mgr->dsp_loaded = 0;
439 sprintf(hw->name, PCXHR_HWDEP_ID); 506 sprintf(hw->name, PCXHR_HWDEP_ID);
440 507
441 if ((err = snd_card_register(mgr->chip[0]->card)) < 0) 508 err = snd_card_register(mgr->chip[0]->card);
509 if (err < 0)
442 return err; 510 return err;
443 return 0; 511 return 0;
444} 512}
diff --git a/sound/pci/pcxhr/pcxhr_mix22.c b/sound/pci/pcxhr/pcxhr_mix22.c
new file mode 100644
index 000000000000..ff019126b672
--- /dev/null
+++ b/sound/pci/pcxhr/pcxhr_mix22.c
@@ -0,0 +1,820 @@
1/*
2 * Driver for Digigram pcxhr compatible soundcards
3 *
4 * mixer interface for stereo cards
5 *
6 * Copyright (c) 2004 by Digigram <alsa@digigram.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#include <linux/delay.h>
24#include <linux/io.h>
25#include <sound/core.h>
26#include <sound/control.h>
27#include <sound/tlv.h>
28#include <sound/asoundef.h>
29#include "pcxhr.h"
30#include "pcxhr_core.h"
31#include "pcxhr_mix22.h"
32
33
34/* registers used on the DSP and Xilinx (port 2) : HR stereo cards only */
35#define PCXHR_DSP_RESET 0x20
36#define PCXHR_XLX_CFG 0x24
37#define PCXHR_XLX_RUER 0x28
38#define PCXHR_XLX_DATA 0x2C
39#define PCXHR_XLX_STATUS 0x30
40#define PCXHR_XLX_LOFREQ 0x34
41#define PCXHR_XLX_HIFREQ 0x38
42#define PCXHR_XLX_CSUER 0x3C
43#define PCXHR_XLX_SELMIC 0x40
44
45#define PCXHR_DSP 2
46
47/* byte access only ! */
48#define PCXHR_INPB(mgr, x) inb((mgr)->port[PCXHR_DSP] + (x))
49#define PCXHR_OUTPB(mgr, x, data) outb((data), (mgr)->port[PCXHR_DSP] + (x))
50
51
52/* values for PCHR_DSP_RESET register */
53#define PCXHR_DSP_RESET_DSP 0x01
54#define PCXHR_DSP_RESET_MUTE 0x02
55#define PCXHR_DSP_RESET_CODEC 0x08
56
57/* values for PCHR_XLX_CFG register */
58#define PCXHR_CFG_SYNCDSP_MASK 0x80
59#define PCXHR_CFG_DEPENDENCY_MASK 0x60
60#define PCXHR_CFG_INDEPENDANT_SEL 0x00
61#define PCXHR_CFG_MASTER_SEL 0x40
62#define PCXHR_CFG_SLAVE_SEL 0x20
63#define PCXHR_CFG_DATA_UER1_SEL_MASK 0x10 /* 0 (UER0), 1(UER1) */
64#define PCXHR_CFG_DATAIN_SEL_MASK 0x08 /* 0 (ana), 1 (UER) */
65#define PCXHR_CFG_SRC_MASK 0x04 /* 0 (Bypass), 1 (SRC Actif) */
66#define PCXHR_CFG_CLOCK_UER1_SEL_MASK 0x02 /* 0 (UER0), 1(UER1) */
67#define PCXHR_CFG_CLOCKIN_SEL_MASK 0x01 /* 0 (internal), 1 (AES/EBU) */
68
69/* values for PCHR_XLX_DATA register */
70#define PCXHR_DATA_CODEC 0x80
71#define AKM_POWER_CONTROL_CMD 0xA007
72#define AKM_RESET_ON_CMD 0xA100
73#define AKM_RESET_OFF_CMD 0xA103
74#define AKM_CLOCK_INF_55K_CMD 0xA240
75#define AKM_CLOCK_SUP_55K_CMD 0xA24D
76#define AKM_MUTE_CMD 0xA38D
77#define AKM_UNMUTE_CMD 0xA30D
78#define AKM_LEFT_LEVEL_CMD 0xA600
79#define AKM_RIGHT_LEVEL_CMD 0xA700
80
81/* values for PCHR_XLX_STATUS register - READ */
82#define PCXHR_STAT_SRC_LOCK 0x01
83#define PCXHR_STAT_LEVEL_IN 0x02
84#define PCXHR_STAT_MIC_CAPS 0x10
85/* values for PCHR_XLX_STATUS register - WRITE */
86#define PCXHR_STAT_FREQ_SYNC_MASK 0x01
87#define PCXHR_STAT_FREQ_UER1_MASK 0x02
88#define PCXHR_STAT_FREQ_SAVE_MASK 0x80
89
90/* values for PCHR_XLX_CSUER register */
91#define PCXHR_SUER1_BIT_U_READ_MASK 0x80
92#define PCXHR_SUER1_BIT_C_READ_MASK 0x40
93#define PCXHR_SUER1_DATA_PRESENT_MASK 0x20
94#define PCXHR_SUER1_CLOCK_PRESENT_MASK 0x10
95#define PCXHR_SUER_BIT_U_READ_MASK 0x08
96#define PCXHR_SUER_BIT_C_READ_MASK 0x04
97#define PCXHR_SUER_DATA_PRESENT_MASK 0x02
98#define PCXHR_SUER_CLOCK_PRESENT_MASK 0x01
99
100#define PCXHR_SUER_BIT_U_WRITE_MASK 0x02
101#define PCXHR_SUER_BIT_C_WRITE_MASK 0x01
102
103/* values for PCXHR_XLX_SELMIC register - WRITE */
104#define PCXHR_SELMIC_PREAMPLI_OFFSET 2
105#define PCXHR_SELMIC_PREAMPLI_MASK 0x0C
106#define PCXHR_SELMIC_PHANTOM_ALIM 0x80
107
108
109static const unsigned char g_hr222_p_level[] = {
110 0x00, /* [000] -49.5 dB: AKM[000] = -1.#INF dB (mute) */
111 0x01, /* [001] -49.0 dB: AKM[001] = -48.131 dB (diff=0.86920 dB) */
112 0x01, /* [002] -48.5 dB: AKM[001] = -48.131 dB (diff=0.36920 dB) */
113 0x01, /* [003] -48.0 dB: AKM[001] = -48.131 dB (diff=0.13080 dB) */
114 0x01, /* [004] -47.5 dB: AKM[001] = -48.131 dB (diff=0.63080 dB) */
115 0x01, /* [005] -46.5 dB: AKM[001] = -48.131 dB (diff=1.63080 dB) */
116 0x01, /* [006] -47.0 dB: AKM[001] = -48.131 dB (diff=1.13080 dB) */
117 0x01, /* [007] -46.0 dB: AKM[001] = -48.131 dB (diff=2.13080 dB) */
118 0x01, /* [008] -45.5 dB: AKM[001] = -48.131 dB (diff=2.63080 dB) */
119 0x02, /* [009] -45.0 dB: AKM[002] = -42.110 dB (diff=2.88980 dB) */
120 0x02, /* [010] -44.5 dB: AKM[002] = -42.110 dB (diff=2.38980 dB) */
121 0x02, /* [011] -44.0 dB: AKM[002] = -42.110 dB (diff=1.88980 dB) */
122 0x02, /* [012] -43.5 dB: AKM[002] = -42.110 dB (diff=1.38980 dB) */
123 0x02, /* [013] -43.0 dB: AKM[002] = -42.110 dB (diff=0.88980 dB) */
124 0x02, /* [014] -42.5 dB: AKM[002] = -42.110 dB (diff=0.38980 dB) */
125 0x02, /* [015] -42.0 dB: AKM[002] = -42.110 dB (diff=0.11020 dB) */
126 0x02, /* [016] -41.5 dB: AKM[002] = -42.110 dB (diff=0.61020 dB) */
127 0x02, /* [017] -41.0 dB: AKM[002] = -42.110 dB (diff=1.11020 dB) */
128 0x02, /* [018] -40.5 dB: AKM[002] = -42.110 dB (diff=1.61020 dB) */
129 0x03, /* [019] -40.0 dB: AKM[003] = -38.588 dB (diff=1.41162 dB) */
130 0x03, /* [020] -39.5 dB: AKM[003] = -38.588 dB (diff=0.91162 dB) */
131 0x03, /* [021] -39.0 dB: AKM[003] = -38.588 dB (diff=0.41162 dB) */
132 0x03, /* [022] -38.5 dB: AKM[003] = -38.588 dB (diff=0.08838 dB) */
133 0x03, /* [023] -38.0 dB: AKM[003] = -38.588 dB (diff=0.58838 dB) */
134 0x03, /* [024] -37.5 dB: AKM[003] = -38.588 dB (diff=1.08838 dB) */
135 0x04, /* [025] -37.0 dB: AKM[004] = -36.090 dB (diff=0.91040 dB) */
136 0x04, /* [026] -36.5 dB: AKM[004] = -36.090 dB (diff=0.41040 dB) */
137 0x04, /* [027] -36.0 dB: AKM[004] = -36.090 dB (diff=0.08960 dB) */
138 0x04, /* [028] -35.5 dB: AKM[004] = -36.090 dB (diff=0.58960 dB) */
139 0x05, /* [029] -35.0 dB: AKM[005] = -34.151 dB (diff=0.84860 dB) */
140 0x05, /* [030] -34.5 dB: AKM[005] = -34.151 dB (diff=0.34860 dB) */
141 0x05, /* [031] -34.0 dB: AKM[005] = -34.151 dB (diff=0.15140 dB) */
142 0x05, /* [032] -33.5 dB: AKM[005] = -34.151 dB (diff=0.65140 dB) */
143 0x06, /* [033] -33.0 dB: AKM[006] = -32.568 dB (diff=0.43222 dB) */
144 0x06, /* [034] -32.5 dB: AKM[006] = -32.568 dB (diff=0.06778 dB) */
145 0x06, /* [035] -32.0 dB: AKM[006] = -32.568 dB (diff=0.56778 dB) */
146 0x07, /* [036] -31.5 dB: AKM[007] = -31.229 dB (diff=0.27116 dB) */
147 0x07, /* [037] -31.0 dB: AKM[007] = -31.229 dB (diff=0.22884 dB) */
148 0x08, /* [038] -30.5 dB: AKM[008] = -30.069 dB (diff=0.43100 dB) */
149 0x08, /* [039] -30.0 dB: AKM[008] = -30.069 dB (diff=0.06900 dB) */
150 0x09, /* [040] -29.5 dB: AKM[009] = -29.046 dB (diff=0.45405 dB) */
151 0x09, /* [041] -29.0 dB: AKM[009] = -29.046 dB (diff=0.04595 dB) */
152 0x0a, /* [042] -28.5 dB: AKM[010] = -28.131 dB (diff=0.36920 dB) */
153 0x0a, /* [043] -28.0 dB: AKM[010] = -28.131 dB (diff=0.13080 dB) */
154 0x0b, /* [044] -27.5 dB: AKM[011] = -27.303 dB (diff=0.19705 dB) */
155 0x0b, /* [045] -27.0 dB: AKM[011] = -27.303 dB (diff=0.30295 dB) */
156 0x0c, /* [046] -26.5 dB: AKM[012] = -26.547 dB (diff=0.04718 dB) */
157 0x0d, /* [047] -26.0 dB: AKM[013] = -25.852 dB (diff=0.14806 dB) */
158 0x0e, /* [048] -25.5 dB: AKM[014] = -25.208 dB (diff=0.29176 dB) */
159 0x0e, /* [049] -25.0 dB: AKM[014] = -25.208 dB (diff=0.20824 dB) */
160 0x0f, /* [050] -24.5 dB: AKM[015] = -24.609 dB (diff=0.10898 dB) */
161 0x10, /* [051] -24.0 dB: AKM[016] = -24.048 dB (diff=0.04840 dB) */
162 0x11, /* [052] -23.5 dB: AKM[017] = -23.522 dB (diff=0.02183 dB) */
163 0x12, /* [053] -23.0 dB: AKM[018] = -23.025 dB (diff=0.02535 dB) */
164 0x13, /* [054] -22.5 dB: AKM[019] = -22.556 dB (diff=0.05573 dB) */
165 0x14, /* [055] -22.0 dB: AKM[020] = -22.110 dB (diff=0.11020 dB) */
166 0x15, /* [056] -21.5 dB: AKM[021] = -21.686 dB (diff=0.18642 dB) */
167 0x17, /* [057] -21.0 dB: AKM[023] = -20.896 dB (diff=0.10375 dB) */
168 0x18, /* [058] -20.5 dB: AKM[024] = -20.527 dB (diff=0.02658 dB) */
169 0x1a, /* [059] -20.0 dB: AKM[026] = -19.831 dB (diff=0.16866 dB) */
170 0x1b, /* [060] -19.5 dB: AKM[027] = -19.504 dB (diff=0.00353 dB) */
171 0x1d, /* [061] -19.0 dB: AKM[029] = -18.883 dB (diff=0.11716 dB) */
172 0x1e, /* [062] -18.5 dB: AKM[030] = -18.588 dB (diff=0.08838 dB) */
173 0x20, /* [063] -18.0 dB: AKM[032] = -18.028 dB (diff=0.02780 dB) */
174 0x22, /* [064] -17.5 dB: AKM[034] = -17.501 dB (diff=0.00123 dB) */
175 0x24, /* [065] -17.0 dB: AKM[036] = -17.005 dB (diff=0.00475 dB) */
176 0x26, /* [066] -16.5 dB: AKM[038] = -16.535 dB (diff=0.03513 dB) */
177 0x28, /* [067] -16.0 dB: AKM[040] = -16.090 dB (diff=0.08960 dB) */
178 0x2b, /* [068] -15.5 dB: AKM[043] = -15.461 dB (diff=0.03857 dB) */
179 0x2d, /* [069] -15.0 dB: AKM[045] = -15.067 dB (diff=0.06655 dB) */
180 0x30, /* [070] -14.5 dB: AKM[048] = -14.506 dB (diff=0.00598 dB) */
181 0x33, /* [071] -14.0 dB: AKM[051] = -13.979 dB (diff=0.02060 dB) */
182 0x36, /* [072] -13.5 dB: AKM[054] = -13.483 dB (diff=0.01707 dB) */
183 0x39, /* [073] -13.0 dB: AKM[057] = -13.013 dB (diff=0.01331 dB) */
184 0x3c, /* [074] -12.5 dB: AKM[060] = -12.568 dB (diff=0.06778 dB) */
185 0x40, /* [075] -12.0 dB: AKM[064] = -12.007 dB (diff=0.00720 dB) */
186 0x44, /* [076] -11.5 dB: AKM[068] = -11.481 dB (diff=0.01937 dB) */
187 0x48, /* [077] -11.0 dB: AKM[072] = -10.984 dB (diff=0.01585 dB) */
188 0x4c, /* [078] -10.5 dB: AKM[076] = -10.515 dB (diff=0.01453 dB) */
189 0x51, /* [079] -10.0 dB: AKM[081] = -9.961 dB (diff=0.03890 dB) */
190 0x55, /* [080] -9.5 dB: AKM[085] = -9.542 dB (diff=0.04243 dB) */
191 0x5a, /* [081] -9.0 dB: AKM[090] = -9.046 dB (diff=0.04595 dB) */
192 0x60, /* [082] -8.5 dB: AKM[096] = -8.485 dB (diff=0.01462 dB) */
193 0x66, /* [083] -8.0 dB: AKM[102] = -7.959 dB (diff=0.04120 dB) */
194 0x6c, /* [084] -7.5 dB: AKM[108] = -7.462 dB (diff=0.03767 dB) */
195 0x72, /* [085] -7.0 dB: AKM[114] = -6.993 dB (diff=0.00729 dB) */
196 0x79, /* [086] -6.5 dB: AKM[121] = -6.475 dB (diff=0.02490 dB) */
197 0x80, /* [087] -6.0 dB: AKM[128] = -5.987 dB (diff=0.01340 dB) */
198 0x87, /* [088] -5.5 dB: AKM[135] = -5.524 dB (diff=0.02413 dB) */
199 0x8f, /* [089] -5.0 dB: AKM[143] = -5.024 dB (diff=0.02408 dB) */
200 0x98, /* [090] -4.5 dB: AKM[152] = -4.494 dB (diff=0.00607 dB) */
201 0xa1, /* [091] -4.0 dB: AKM[161] = -3.994 dB (diff=0.00571 dB) */
202 0xaa, /* [092] -3.5 dB: AKM[170] = -3.522 dB (diff=0.02183 dB) */
203 0xb5, /* [093] -3.0 dB: AKM[181] = -2.977 dB (diff=0.02277 dB) */
204 0xbf, /* [094] -2.5 dB: AKM[191] = -2.510 dB (diff=0.01014 dB) */
205 0xcb, /* [095] -2.0 dB: AKM[203] = -1.981 dB (diff=0.01912 dB) */
206 0xd7, /* [096] -1.5 dB: AKM[215] = -1.482 dB (diff=0.01797 dB) */
207 0xe3, /* [097] -1.0 dB: AKM[227] = -1.010 dB (diff=0.01029 dB) */
208 0xf1, /* [098] -0.5 dB: AKM[241] = -0.490 dB (diff=0.00954 dB) */
209 0xff, /* [099] +0.0 dB: AKM[255] = +0.000 dB (diff=0.00000 dB) */
210};
211
212
213static void hr222_config_akm(struct pcxhr_mgr *mgr, unsigned short data)
214{
215 unsigned short mask = 0x8000;
216 /* activate access to codec registers */
217 PCXHR_INPB(mgr, PCXHR_XLX_HIFREQ);
218
219 while (mask) {
220 PCXHR_OUTPB(mgr, PCXHR_XLX_DATA,
221 data & mask ? PCXHR_DATA_CODEC : 0);
222 mask >>= 1;
223 }
224 /* termiate access to codec registers */
225 PCXHR_INPB(mgr, PCXHR_XLX_RUER);
226}
227
228
229static int hr222_set_hw_playback_level(struct pcxhr_mgr *mgr,
230 int idx, int level)
231{
232 unsigned short cmd;
233 if (idx > 1 ||
234 level < 0 ||
235 level >= ARRAY_SIZE(g_hr222_p_level))
236 return -EINVAL;
237
238 if (idx == 0)
239 cmd = AKM_LEFT_LEVEL_CMD;
240 else
241 cmd = AKM_RIGHT_LEVEL_CMD;
242
243 /* conversion from PmBoardCodedLevel to AKM nonlinear programming */
244 cmd += g_hr222_p_level[level];
245
246 hr222_config_akm(mgr, cmd);
247 return 0;
248}
249
250
251static int hr222_set_hw_capture_level(struct pcxhr_mgr *mgr,
252 int level_l, int level_r, int level_mic)
253{
254 /* program all input levels at the same time */
255 unsigned int data;
256 int i;
257
258 if (!mgr->capture_chips)
259 return -EINVAL; /* no PCX22 */
260
261 data = ((level_mic & 0xff) << 24); /* micro is mono, but apply */
262 data |= ((level_mic & 0xff) << 16); /* level on both channels */
263 data |= ((level_r & 0xff) << 8); /* line input right channel */
264 data |= (level_l & 0xff); /* line input left channel */
265
266 PCXHR_INPB(mgr, PCXHR_XLX_DATA); /* activate input codec */
267 /* send 32 bits (4 x 8 bits) */
268 for (i = 0; i < 32; i++, data <<= 1) {
269 PCXHR_OUTPB(mgr, PCXHR_XLX_DATA,
270 (data & 0x80000000) ? PCXHR_DATA_CODEC : 0);
271 }
272 PCXHR_INPB(mgr, PCXHR_XLX_RUER); /* close input level codec */
273 return 0;
274}
275
276static void hr222_micro_boost(struct pcxhr_mgr *mgr, int level);
277
278int hr222_sub_init(struct pcxhr_mgr *mgr)
279{
280 unsigned char reg;
281
282 mgr->board_has_analog = 1; /* analog always available */
283 mgr->xlx_cfg = PCXHR_CFG_SYNCDSP_MASK;
284
285 reg = PCXHR_INPB(mgr, PCXHR_XLX_STATUS);
286 if (reg & PCXHR_STAT_MIC_CAPS)
287 mgr->board_has_mic = 1; /* microphone available */
288 snd_printdd("MIC input available = %d\n", mgr->board_has_mic);
289
290 /* reset codec */
291 PCXHR_OUTPB(mgr, PCXHR_DSP_RESET,
292 PCXHR_DSP_RESET_DSP);
293 msleep(5);
294 PCXHR_OUTPB(mgr, PCXHR_DSP_RESET,
295 PCXHR_DSP_RESET_DSP |
296 PCXHR_DSP_RESET_MUTE |
297 PCXHR_DSP_RESET_CODEC);
298 msleep(5);
299
300 /* config AKM */
301 hr222_config_akm(mgr, AKM_POWER_CONTROL_CMD);
302 hr222_config_akm(mgr, AKM_CLOCK_INF_55K_CMD);
303 hr222_config_akm(mgr, AKM_UNMUTE_CMD);
304 hr222_config_akm(mgr, AKM_RESET_OFF_CMD);
305
306 /* init micro boost */
307 hr222_micro_boost(mgr, 0);
308
309 return 0;
310}
311
312
313/* calc PLL register */
314/* TODO : there is a very similar fct in pcxhr.c */
315static int hr222_pll_freq_register(unsigned int freq,
316 unsigned int *pllreg,
317 unsigned int *realfreq)
318{
319 unsigned int reg;
320
321 if (freq < 6900 || freq > 219000)
322 return -EINVAL;
323 reg = (28224000 * 2) / freq;
324 reg = (reg - 1) / 2;
325 if (reg < 0x100)
326 *pllreg = reg + 0xC00;
327 else if (reg < 0x200)
328 *pllreg = reg + 0x800;
329 else if (reg < 0x400)
330 *pllreg = reg & 0x1ff;
331 else if (reg < 0x800) {
332 *pllreg = ((reg >> 1) & 0x1ff) + 0x200;
333 reg &= ~1;
334 } else {
335 *pllreg = ((reg >> 2) & 0x1ff) + 0x400;
336 reg &= ~3;
337 }
338 if (realfreq)
339 *realfreq = (28224000 / (reg + 1));
340 return 0;
341}
342
343int hr222_sub_set_clock(struct pcxhr_mgr *mgr,
344 unsigned int rate,
345 int *changed)
346{
347 unsigned int speed, pllreg = 0;
348 int err;
349 unsigned realfreq = rate;
350
351 switch (mgr->use_clock_type) {
352 case HR22_CLOCK_TYPE_INTERNAL:
353 err = hr222_pll_freq_register(rate, &pllreg, &realfreq);
354 if (err)
355 return err;
356
357 mgr->xlx_cfg &= ~(PCXHR_CFG_CLOCKIN_SEL_MASK |
358 PCXHR_CFG_CLOCK_UER1_SEL_MASK);
359 break;
360 case HR22_CLOCK_TYPE_AES_SYNC:
361 mgr->xlx_cfg |= PCXHR_CFG_CLOCKIN_SEL_MASK;
362 mgr->xlx_cfg &= ~PCXHR_CFG_CLOCK_UER1_SEL_MASK;
363 break;
364 case HR22_CLOCK_TYPE_AES_1:
365 if (!mgr->board_has_aes1)
366 return -EINVAL;
367
368 mgr->xlx_cfg |= (PCXHR_CFG_CLOCKIN_SEL_MASK |
369 PCXHR_CFG_CLOCK_UER1_SEL_MASK);
370 break;
371 default:
372 return -EINVAL;
373 }
374 hr222_config_akm(mgr, AKM_MUTE_CMD);
375
376 if (mgr->use_clock_type == HR22_CLOCK_TYPE_INTERNAL) {
377 PCXHR_OUTPB(mgr, PCXHR_XLX_HIFREQ, pllreg >> 8);
378 PCXHR_OUTPB(mgr, PCXHR_XLX_LOFREQ, pllreg & 0xff);
379 }
380
381 /* set clock source */
382 PCXHR_OUTPB(mgr, PCXHR_XLX_CFG, mgr->xlx_cfg);
383
384 /* codec speed modes */
385 speed = rate < 55000 ? 0 : 1;
386 if (mgr->codec_speed != speed) {
387 mgr->codec_speed = speed;
388 if (speed == 0)
389 hr222_config_akm(mgr, AKM_CLOCK_INF_55K_CMD);
390 else
391 hr222_config_akm(mgr, AKM_CLOCK_SUP_55K_CMD);
392 }
393
394 mgr->sample_rate_real = realfreq;
395 mgr->cur_clock_type = mgr->use_clock_type;
396
397 if (changed)
398 *changed = 1;
399
400 hr222_config_akm(mgr, AKM_UNMUTE_CMD);
401
402 snd_printdd("set_clock to %dHz (realfreq=%d pllreg=%x)\n",
403 rate, realfreq, pllreg);
404 return 0;
405}
406
407int hr222_get_external_clock(struct pcxhr_mgr *mgr,
408 enum pcxhr_clock_type clock_type,
409 int *sample_rate)
410{
411 int rate, calc_rate = 0;
412 unsigned int ticks;
413 unsigned char mask, reg;
414
415 if (clock_type == HR22_CLOCK_TYPE_AES_SYNC) {
416
417 mask = (PCXHR_SUER_CLOCK_PRESENT_MASK |
418 PCXHR_SUER_DATA_PRESENT_MASK);
419 reg = PCXHR_STAT_FREQ_SYNC_MASK;
420
421 } else if (clock_type == HR22_CLOCK_TYPE_AES_1 && mgr->board_has_aes1) {
422
423 mask = (PCXHR_SUER1_CLOCK_PRESENT_MASK |
424 PCXHR_SUER1_DATA_PRESENT_MASK);
425 reg = PCXHR_STAT_FREQ_UER1_MASK;
426
427 } else {
428 snd_printdd("get_external_clock : type %d not supported\n",
429 clock_type);
430 return -EINVAL; /* other clocks not supported */
431 }
432
433 if ((PCXHR_INPB(mgr, PCXHR_XLX_CSUER) & mask) != mask) {
434 snd_printdd("get_external_clock(%d) = 0 Hz\n", clock_type);
435 *sample_rate = 0;
436 return 0; /* no external clock locked */
437 }
438
439 PCXHR_OUTPB(mgr, PCXHR_XLX_STATUS, reg); /* calculate freq */
440
441 /* save the measured clock frequency */
442 reg |= PCXHR_STAT_FREQ_SAVE_MASK;
443
444 if (mgr->last_reg_stat != reg) {
445 udelay(500); /* wait min 2 cycles of lowest freq (8000) */
446 mgr->last_reg_stat = reg;
447 }
448
449 PCXHR_OUTPB(mgr, PCXHR_XLX_STATUS, reg); /* save */
450
451 /* get the frequency */
452 ticks = (unsigned int)PCXHR_INPB(mgr, PCXHR_XLX_CFG);
453 ticks = (ticks & 0x03) << 8;
454 ticks |= (unsigned int)PCXHR_INPB(mgr, PCXHR_DSP_RESET);
455
456 if (ticks != 0)
457 calc_rate = 28224000 / ticks;
458 /* rounding */
459 if (calc_rate > 184200)
460 rate = 192000;
461 else if (calc_rate > 152200)
462 rate = 176400;
463 else if (calc_rate > 112000)
464 rate = 128000;
465 else if (calc_rate > 92100)
466 rate = 96000;
467 else if (calc_rate > 76100)
468 rate = 88200;
469 else if (calc_rate > 56000)
470 rate = 64000;
471 else if (calc_rate > 46050)
472 rate = 48000;
473 else if (calc_rate > 38050)
474 rate = 44100;
475 else if (calc_rate > 28000)
476 rate = 32000;
477 else if (calc_rate > 23025)
478 rate = 24000;
479 else if (calc_rate > 19025)
480 rate = 22050;
481 else if (calc_rate > 14000)
482 rate = 16000;
483 else if (calc_rate > 11512)
484 rate = 12000;
485 else if (calc_rate > 9512)
486 rate = 11025;
487 else if (calc_rate > 7000)
488 rate = 8000;
489 else
490 rate = 0;
491
492 snd_printdd("External clock is at %d Hz (measured %d Hz)\n",
493 rate, calc_rate);
494 *sample_rate = rate;
495 return 0;
496}
497
498
499int hr222_update_analog_audio_level(struct snd_pcxhr *chip,
500 int is_capture, int channel)
501{
502 snd_printdd("hr222_update_analog_audio_level(%s chan=%d)\n",
503 is_capture ? "capture" : "playback", channel);
504 if (is_capture) {
505 int level_l, level_r, level_mic;
506 /* we have to update all levels */
507 if (chip->analog_capture_active) {
508 level_l = chip->analog_capture_volume[0];
509 level_r = chip->analog_capture_volume[1];
510 } else {
511 level_l = HR222_LINE_CAPTURE_LEVEL_MIN;
512 level_r = HR222_LINE_CAPTURE_LEVEL_MIN;
513 }
514 if (chip->mic_active)
515 level_mic = chip->mic_volume;
516 else
517 level_mic = HR222_MICRO_CAPTURE_LEVEL_MIN;
518 return hr222_set_hw_capture_level(chip->mgr,
519 level_l, level_r, level_mic);
520 } else {
521 int vol;
522 if (chip->analog_playback_active[channel])
523 vol = chip->analog_playback_volume[channel];
524 else
525 vol = HR222_LINE_PLAYBACK_LEVEL_MIN;
526 return hr222_set_hw_playback_level(chip->mgr, channel, vol);
527 }
528}
529
530
531/*texts[5] = {"Line", "Digital", "Digi+SRC", "Mic", "Line+Mic"}*/
532#define SOURCE_LINE 0
533#define SOURCE_DIGITAL 1
534#define SOURCE_DIGISRC 2
535#define SOURCE_MIC 3
536#define SOURCE_LINEMIC 4
537
538int hr222_set_audio_source(struct snd_pcxhr *chip)
539{
540 int digital = 0;
541 /* default analog source */
542 chip->mgr->xlx_cfg &= ~(PCXHR_CFG_SRC_MASK |
543 PCXHR_CFG_DATAIN_SEL_MASK |
544 PCXHR_CFG_DATA_UER1_SEL_MASK);
545
546 if (chip->audio_capture_source == SOURCE_DIGISRC) {
547 chip->mgr->xlx_cfg |= PCXHR_CFG_SRC_MASK;
548 digital = 1;
549 } else {
550 if (chip->audio_capture_source == SOURCE_DIGITAL)
551 digital = 1;
552 }
553 if (digital) {
554 chip->mgr->xlx_cfg |= PCXHR_CFG_DATAIN_SEL_MASK;
555 if (chip->mgr->board_has_aes1) {
556 /* get data from the AES1 plug */
557 chip->mgr->xlx_cfg |= PCXHR_CFG_DATA_UER1_SEL_MASK;
558 }
559 /* chip->mic_active = 0; */
560 /* chip->analog_capture_active = 0; */
561 } else {
562 int update_lvl = 0;
563 chip->analog_capture_active = 0;
564 chip->mic_active = 0;
565 if (chip->audio_capture_source == SOURCE_LINE ||
566 chip->audio_capture_source == SOURCE_LINEMIC) {
567 if (chip->analog_capture_active == 0)
568 update_lvl = 1;
569 chip->analog_capture_active = 1;
570 }
571 if (chip->audio_capture_source == SOURCE_MIC ||
572 chip->audio_capture_source == SOURCE_LINEMIC) {
573 if (chip->mic_active == 0)
574 update_lvl = 1;
575 chip->mic_active = 1;
576 }
577 if (update_lvl) {
578 /* capture: update all 3 mutes/unmutes with one call */
579 hr222_update_analog_audio_level(chip, 1, 0);
580 }
581 }
582 /* set the source infos (max 3 bits modified) */
583 PCXHR_OUTPB(chip->mgr, PCXHR_XLX_CFG, chip->mgr->xlx_cfg);
584 return 0;
585}
586
587
588int hr222_iec958_capture_byte(struct snd_pcxhr *chip,
589 int aes_idx, unsigned char *aes_bits)
590{
591 unsigned char idx = (unsigned char)(aes_idx * 8);
592 unsigned char temp = 0;
593 unsigned char mask = chip->mgr->board_has_aes1 ?
594 PCXHR_SUER1_BIT_C_READ_MASK : PCXHR_SUER_BIT_C_READ_MASK;
595 int i;
596 for (i = 0; i < 8; i++) {
597 PCXHR_OUTPB(chip->mgr, PCXHR_XLX_RUER, idx++); /* idx < 192 */
598 temp <<= 1;
599 if (PCXHR_INPB(chip->mgr, PCXHR_XLX_CSUER) & mask)
600 temp |= 1;
601 }
602 snd_printdd("read iec958 AES %d byte %d = 0x%x\n",
603 chip->chip_idx, aes_idx, temp);
604 *aes_bits = temp;
605 return 0;
606}
607
608
609int hr222_iec958_update_byte(struct snd_pcxhr *chip,
610 int aes_idx, unsigned char aes_bits)
611{
612 int i;
613 unsigned char new_bits = aes_bits;
614 unsigned char old_bits = chip->aes_bits[aes_idx];
615 unsigned char idx = (unsigned char)(aes_idx * 8);
616 for (i = 0; i < 8; i++) {
617 if ((old_bits & 0x01) != (new_bits & 0x01)) {
618 /* idx < 192 */
619 PCXHR_OUTPB(chip->mgr, PCXHR_XLX_RUER, idx);
620 /* write C and U bit */
621 PCXHR_OUTPB(chip->mgr, PCXHR_XLX_CSUER, new_bits&0x01 ?
622 PCXHR_SUER_BIT_C_WRITE_MASK : 0);
623 }
624 idx++;
625 old_bits >>= 1;
626 new_bits >>= 1;
627 }
628 chip->aes_bits[aes_idx] = aes_bits;
629 return 0;
630}
631
632static void hr222_micro_boost(struct pcxhr_mgr *mgr, int level)
633{
634 unsigned char boost_mask;
635 boost_mask = (unsigned char) (level << PCXHR_SELMIC_PREAMPLI_OFFSET);
636 if (boost_mask & (~PCXHR_SELMIC_PREAMPLI_MASK))
637 return; /* only values form 0 to 3 accepted */
638
639 mgr->xlx_selmic &= ~PCXHR_SELMIC_PREAMPLI_MASK;
640 mgr->xlx_selmic |= boost_mask;
641
642 PCXHR_OUTPB(mgr, PCXHR_XLX_SELMIC, mgr->xlx_selmic);
643
644 snd_printdd("hr222_micro_boost : set %x\n", boost_mask);
645}
646
647static void hr222_phantom_power(struct pcxhr_mgr *mgr, int power)
648{
649 if (power)
650 mgr->xlx_selmic |= PCXHR_SELMIC_PHANTOM_ALIM;
651 else
652 mgr->xlx_selmic &= ~PCXHR_SELMIC_PHANTOM_ALIM;
653
654 PCXHR_OUTPB(mgr, PCXHR_XLX_SELMIC, mgr->xlx_selmic);
655
656 snd_printdd("hr222_phantom_power : set %d\n", power);
657}
658
659
660/* mic level */
661static const DECLARE_TLV_DB_SCALE(db_scale_mic_hr222, -9850, 50, 650);
662
663static int hr222_mic_vol_info(struct snd_kcontrol *kcontrol,
664 struct snd_ctl_elem_info *uinfo)
665{
666 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
667 uinfo->count = 1;
668 uinfo->value.integer.min = HR222_MICRO_CAPTURE_LEVEL_MIN; /* -98 dB */
669 /* gains from 9 dB to 31.5 dB not recommended; use micboost instead */
670 uinfo->value.integer.max = HR222_MICRO_CAPTURE_LEVEL_MAX; /* +7 dB */
671 return 0;
672}
673
674static int hr222_mic_vol_get(struct snd_kcontrol *kcontrol,
675 struct snd_ctl_elem_value *ucontrol)
676{
677 struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol);
678 mutex_lock(&chip->mgr->mixer_mutex);
679 ucontrol->value.integer.value[0] = chip->mic_volume;
680 mutex_unlock(&chip->mgr->mixer_mutex);
681 return 0;
682}
683
684static int hr222_mic_vol_put(struct snd_kcontrol *kcontrol,
685 struct snd_ctl_elem_value *ucontrol)
686{
687 struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol);
688 int changed = 0;
689 mutex_lock(&chip->mgr->mixer_mutex);
690 if (chip->mic_volume != ucontrol->value.integer.value[0]) {
691 changed = 1;
692 chip->mic_volume = ucontrol->value.integer.value[0];
693 hr222_update_analog_audio_level(chip, 1, 0);
694 }
695 mutex_unlock(&chip->mgr->mixer_mutex);
696 return changed;
697}
698
699static struct snd_kcontrol_new hr222_control_mic_level = {
700 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
701 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
702 SNDRV_CTL_ELEM_ACCESS_TLV_READ),
703 .name = "Mic Capture Volume",
704 .info = hr222_mic_vol_info,
705 .get = hr222_mic_vol_get,
706 .put = hr222_mic_vol_put,
707 .tlv = { .p = db_scale_mic_hr222 },
708};
709
710
711/* mic boost level */
712static const DECLARE_TLV_DB_SCALE(db_scale_micboost_hr222, 0, 1800, 5400);
713
714static int hr222_mic_boost_info(struct snd_kcontrol *kcontrol,
715 struct snd_ctl_elem_info *uinfo)
716{
717 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
718 uinfo->count = 1;
719 uinfo->value.integer.min = 0; /* 0 dB */
720 uinfo->value.integer.max = 3; /* 54 dB */
721 return 0;
722}
723
724static int hr222_mic_boost_get(struct snd_kcontrol *kcontrol,
725 struct snd_ctl_elem_value *ucontrol)
726{
727 struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol);
728 mutex_lock(&chip->mgr->mixer_mutex);
729 ucontrol->value.integer.value[0] = chip->mic_boost;
730 mutex_unlock(&chip->mgr->mixer_mutex);
731 return 0;
732}
733
734static int hr222_mic_boost_put(struct snd_kcontrol *kcontrol,
735 struct snd_ctl_elem_value *ucontrol)
736{
737 struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol);
738 int changed = 0;
739 mutex_lock(&chip->mgr->mixer_mutex);
740 if (chip->mic_boost != ucontrol->value.integer.value[0]) {
741 changed = 1;
742 chip->mic_boost = ucontrol->value.integer.value[0];
743 hr222_micro_boost(chip->mgr, chip->mic_boost);
744 }
745 mutex_unlock(&chip->mgr->mixer_mutex);
746 return changed;
747}
748
749static struct snd_kcontrol_new hr222_control_mic_boost = {
750 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
751 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
752 SNDRV_CTL_ELEM_ACCESS_TLV_READ),
753 .name = "MicBoost Capture Volume",
754 .info = hr222_mic_boost_info,
755 .get = hr222_mic_boost_get,
756 .put = hr222_mic_boost_put,
757 .tlv = { .p = db_scale_micboost_hr222 },
758};
759
760
761/******************* Phantom power switch *******************/
762#define hr222_phantom_power_info snd_ctl_boolean_mono_info
763
764static int hr222_phantom_power_get(struct snd_kcontrol *kcontrol,
765 struct snd_ctl_elem_value *ucontrol)
766{
767 struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol);
768 mutex_lock(&chip->mgr->mixer_mutex);
769 ucontrol->value.integer.value[0] = chip->phantom_power;
770 mutex_unlock(&chip->mgr->mixer_mutex);
771 return 0;
772}
773
774static int hr222_phantom_power_put(struct snd_kcontrol *kcontrol,
775 struct snd_ctl_elem_value *ucontrol)
776{
777 struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol);
778 int power, changed = 0;
779
780 mutex_lock(&chip->mgr->mixer_mutex);
781 power = !!ucontrol->value.integer.value[0];
782 if (chip->phantom_power != power) {
783 hr222_phantom_power(chip->mgr, power);
784 chip->phantom_power = power;
785 changed = 1;
786 }
787 mutex_unlock(&chip->mgr->mixer_mutex);
788 return changed;
789}
790
791static struct snd_kcontrol_new hr222_phantom_power_switch = {
792 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
793 .name = "Phantom Power Switch",
794 .info = hr222_phantom_power_info,
795 .get = hr222_phantom_power_get,
796 .put = hr222_phantom_power_put,
797};
798
799
800int hr222_add_mic_controls(struct snd_pcxhr *chip)
801{
802 int err;
803 if (!chip->mgr->board_has_mic)
804 return 0;
805
806 /* controls */
807 err = snd_ctl_add(chip->card, snd_ctl_new1(&hr222_control_mic_level,
808 chip));
809 if (err < 0)
810 return err;
811
812 err = snd_ctl_add(chip->card, snd_ctl_new1(&hr222_control_mic_boost,
813 chip));
814 if (err < 0)
815 return err;
816
817 err = snd_ctl_add(chip->card, snd_ctl_new1(&hr222_phantom_power_switch,
818 chip));
819 return err;
820}
diff --git a/sound/pci/pcxhr/pcxhr_mix22.h b/sound/pci/pcxhr/pcxhr_mix22.h
new file mode 100644
index 000000000000..6b318b2f0100
--- /dev/null
+++ b/sound/pci/pcxhr/pcxhr_mix22.h
@@ -0,0 +1,56 @@
1/*
2 * Driver for Digigram pcxhr compatible soundcards
3 *
4 * low level interface with interrupt ans message handling
5 *
6 * Copyright (c) 2004 by Digigram <alsa@digigram.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#ifndef __SOUND_PCXHR_MIX22_H
24#define __SOUND_PCXHR_MIX22_H
25
26struct pcxhr_mgr;
27
28int hr222_sub_init(struct pcxhr_mgr *mgr);
29int hr222_sub_set_clock(struct pcxhr_mgr *mgr, unsigned int rate,
30 int *changed);
31int hr222_get_external_clock(struct pcxhr_mgr *mgr,
32 enum pcxhr_clock_type clock_type,
33 int *sample_rate);
34
35#define HR222_LINE_PLAYBACK_LEVEL_MIN 0 /* -25.5 dB */
36#define HR222_LINE_PLAYBACK_ZERO_LEVEL 51 /* 0.0 dB */
37#define HR222_LINE_PLAYBACK_LEVEL_MAX 99 /* +24.0 dB */
38
39#define HR222_LINE_CAPTURE_LEVEL_MIN 0 /* -111.5 dB */
40#define HR222_LINE_CAPTURE_ZERO_LEVEL 223 /* 0.0 dB */
41#define HR222_LINE_CAPTURE_LEVEL_MAX 255 /* +16 dB */
42#define HR222_MICRO_CAPTURE_LEVEL_MIN 0 /* -98.5 dB */
43#define HR222_MICRO_CAPTURE_LEVEL_MAX 210 /* +6.5 dB */
44
45int hr222_update_analog_audio_level(struct snd_pcxhr *chip,
46 int is_capture,
47 int channel);
48int hr222_set_audio_source(struct snd_pcxhr *chip);
49int hr222_iec958_capture_byte(struct snd_pcxhr *chip, int aes_idx,
50 unsigned char *aes_bits);
51int hr222_iec958_update_byte(struct snd_pcxhr *chip, int aes_idx,
52 unsigned char aes_bits);
53
54int hr222_add_mic_controls(struct snd_pcxhr *chip);
55
56#endif /* __SOUND_PCXHR_MIX22_H */
diff --git a/sound/pci/pcxhr/pcxhr_mixer.c b/sound/pci/pcxhr/pcxhr_mixer.c
index aabc7bc5321e..2436e374586f 100644
--- a/sound/pci/pcxhr/pcxhr_mixer.c
+++ b/sound/pci/pcxhr/pcxhr_mixer.c
@@ -33,20 +33,24 @@
33#include <sound/tlv.h> 33#include <sound/tlv.h>
34#include <sound/asoundef.h> 34#include <sound/asoundef.h>
35#include "pcxhr_mixer.h" 35#include "pcxhr_mixer.h"
36#include "pcxhr_mix22.h"
36 37
38#define PCXHR_LINE_CAPTURE_LEVEL_MIN 0 /* -112.0 dB */
39#define PCXHR_LINE_CAPTURE_LEVEL_MAX 255 /* +15.5 dB */
40#define PCXHR_LINE_CAPTURE_ZERO_LEVEL 224 /* 0.0 dB ( 0 dBu -> 0 dBFS ) */
37 41
38#define PCXHR_ANALOG_CAPTURE_LEVEL_MIN 0 /* -96.0 dB */ 42#define PCXHR_LINE_PLAYBACK_LEVEL_MIN 0 /* -104.0 dB */
39#define PCXHR_ANALOG_CAPTURE_LEVEL_MAX 255 /* +31.5 dB */ 43#define PCXHR_LINE_PLAYBACK_LEVEL_MAX 128 /* +24.0 dB */
40#define PCXHR_ANALOG_CAPTURE_ZERO_LEVEL 224 /* +16.0 dB ( +31.5 dB - fix level +15.5 dB ) */ 44#define PCXHR_LINE_PLAYBACK_ZERO_LEVEL 104 /* 0.0 dB ( 0 dBFS -> 0 dBu ) */
41 45
42#define PCXHR_ANALOG_PLAYBACK_LEVEL_MIN 0 /* -128.0 dB */ 46static const DECLARE_TLV_DB_SCALE(db_scale_analog_capture, -11200, 50, 1550);
43#define PCXHR_ANALOG_PLAYBACK_LEVEL_MAX 128 /* 0.0 dB */
44#define PCXHR_ANALOG_PLAYBACK_ZERO_LEVEL 104 /* -24.0 dB ( 0.0 dB - fix level +24.0 dB ) */
45
46static const DECLARE_TLV_DB_SCALE(db_scale_analog_capture, -9600, 50, 3150);
47static const DECLARE_TLV_DB_SCALE(db_scale_analog_playback, -10400, 100, 2400); 47static const DECLARE_TLV_DB_SCALE(db_scale_analog_playback, -10400, 100, 2400);
48 48
49static int pcxhr_update_analog_audio_level(struct snd_pcxhr *chip, int is_capture, int channel) 49static const DECLARE_TLV_DB_SCALE(db_scale_a_hr222_capture, -11150, 50, 1600);
50static const DECLARE_TLV_DB_SCALE(db_scale_a_hr222_playback, -2550, 50, 2400);
51
52static int pcxhr_update_analog_audio_level(struct snd_pcxhr *chip,
53 int is_capture, int channel)
50{ 54{
51 int err, vol; 55 int err, vol;
52 struct pcxhr_rmh rmh; 56 struct pcxhr_rmh rmh;
@@ -60,15 +64,17 @@ static int pcxhr_update_analog_audio_level(struct snd_pcxhr *chip, int is_captur
60 if (chip->analog_playback_active[channel]) 64 if (chip->analog_playback_active[channel])
61 vol = chip->analog_playback_volume[channel]; 65 vol = chip->analog_playback_volume[channel];
62 else 66 else
63 vol = PCXHR_ANALOG_PLAYBACK_LEVEL_MIN; 67 vol = PCXHR_LINE_PLAYBACK_LEVEL_MIN;
64 rmh.cmd[2] = PCXHR_ANALOG_PLAYBACK_LEVEL_MAX - vol; /* playback analog levels are inversed */ 68 /* playback analog levels are inversed */
69 rmh.cmd[2] = PCXHR_LINE_PLAYBACK_LEVEL_MAX - vol;
65 } 70 }
66 rmh.cmd[1] = 1 << ((2 * chip->chip_idx) + channel); /* audio mask */ 71 rmh.cmd[1] = 1 << ((2 * chip->chip_idx) + channel); /* audio mask */
67 rmh.cmd_len = 3; 72 rmh.cmd_len = 3;
68 err = pcxhr_send_msg(chip->mgr, &rmh); 73 err = pcxhr_send_msg(chip->mgr, &rmh);
69 if (err < 0) { 74 if (err < 0) {
70 snd_printk(KERN_DEBUG "error update_analog_audio_level card(%d) " 75 snd_printk(KERN_DEBUG "error update_analog_audio_level card(%d)"
71 "is_capture(%d) err(%x)\n", chip->chip_idx, is_capture, err); 76 " is_capture(%d) err(%x)\n",
77 chip->chip_idx, is_capture, err);
72 return -EINVAL; 78 return -EINVAL;
73 } 79 }
74 return 0; 80 return 0;
@@ -80,14 +86,34 @@ static int pcxhr_update_analog_audio_level(struct snd_pcxhr *chip, int is_captur
80static int pcxhr_analog_vol_info(struct snd_kcontrol *kcontrol, 86static int pcxhr_analog_vol_info(struct snd_kcontrol *kcontrol,
81 struct snd_ctl_elem_info *uinfo) 87 struct snd_ctl_elem_info *uinfo)
82{ 88{
89 struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol);
90
83 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 91 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
84 uinfo->count = 2; 92 uinfo->count = 2;
85 if (kcontrol->private_value == 0) { /* playback */ 93 if (kcontrol->private_value == 0) { /* playback */
86 uinfo->value.integer.min = PCXHR_ANALOG_PLAYBACK_LEVEL_MIN; /* -128 dB */ 94 if (chip->mgr->is_hr_stereo) {
87 uinfo->value.integer.max = PCXHR_ANALOG_PLAYBACK_LEVEL_MAX; /* 0 dB */ 95 uinfo->value.integer.min =
96 HR222_LINE_PLAYBACK_LEVEL_MIN; /* -25 dB */
97 uinfo->value.integer.max =
98 HR222_LINE_PLAYBACK_LEVEL_MAX; /* +24 dB */
99 } else {
100 uinfo->value.integer.min =
101 PCXHR_LINE_PLAYBACK_LEVEL_MIN; /*-104 dB */
102 uinfo->value.integer.max =
103 PCXHR_LINE_PLAYBACK_LEVEL_MAX; /* +24 dB */
104 }
88 } else { /* capture */ 105 } else { /* capture */
89 uinfo->value.integer.min = PCXHR_ANALOG_CAPTURE_LEVEL_MIN; /* -96 dB */ 106 if (chip->mgr->is_hr_stereo) {
90 uinfo->value.integer.max = PCXHR_ANALOG_CAPTURE_LEVEL_MAX; /* 31.5 dB */ 107 uinfo->value.integer.min =
108 HR222_LINE_CAPTURE_LEVEL_MIN; /*-112 dB */
109 uinfo->value.integer.max =
110 HR222_LINE_CAPTURE_LEVEL_MAX; /* +15.5 dB */
111 } else {
112 uinfo->value.integer.min =
113 PCXHR_LINE_CAPTURE_LEVEL_MIN; /*-112 dB */
114 uinfo->value.integer.max =
115 PCXHR_LINE_CAPTURE_LEVEL_MAX; /* +15.5 dB */
116 }
91 } 117 }
92 return 0; 118 return 0;
93} 119}
@@ -98,11 +124,11 @@ static int pcxhr_analog_vol_get(struct snd_kcontrol *kcontrol,
98 struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol); 124 struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol);
99 mutex_lock(&chip->mgr->mixer_mutex); 125 mutex_lock(&chip->mgr->mixer_mutex);
100 if (kcontrol->private_value == 0) { /* playback */ 126 if (kcontrol->private_value == 0) { /* playback */
101 ucontrol->value.integer.value[0] = chip->analog_playback_volume[0]; 127 ucontrol->value.integer.value[0] = chip->analog_playback_volume[0];
102 ucontrol->value.integer.value[1] = chip->analog_playback_volume[1]; 128 ucontrol->value.integer.value[1] = chip->analog_playback_volume[1];
103 } else { /* capture */ 129 } else { /* capture */
104 ucontrol->value.integer.value[0] = chip->analog_capture_volume[0]; 130 ucontrol->value.integer.value[0] = chip->analog_capture_volume[0];
105 ucontrol->value.integer.value[1] = chip->analog_capture_volume[1]; 131 ucontrol->value.integer.value[1] = chip->analog_capture_volume[1];
106 } 132 }
107 mutex_unlock(&chip->mgr->mixer_mutex); 133 mutex_unlock(&chip->mgr->mixer_mutex);
108 return 0; 134 return 0;
@@ -123,18 +149,35 @@ static int pcxhr_analog_vol_put(struct snd_kcontrol *kcontrol,
123 &chip->analog_capture_volume[i] : 149 &chip->analog_capture_volume[i] :
124 &chip->analog_playback_volume[i]; 150 &chip->analog_playback_volume[i];
125 if (is_capture) { 151 if (is_capture) {
126 if (new_volume < PCXHR_ANALOG_CAPTURE_LEVEL_MIN || 152 if (chip->mgr->is_hr_stereo) {
127 new_volume > PCXHR_ANALOG_CAPTURE_LEVEL_MAX) 153 if (new_volume < HR222_LINE_CAPTURE_LEVEL_MIN ||
128 continue; 154 new_volume > HR222_LINE_CAPTURE_LEVEL_MAX)
155 continue;
156 } else {
157 if (new_volume < PCXHR_LINE_CAPTURE_LEVEL_MIN ||
158 new_volume > PCXHR_LINE_CAPTURE_LEVEL_MAX)
159 continue;
160 }
129 } else { 161 } else {
130 if (new_volume < PCXHR_ANALOG_PLAYBACK_LEVEL_MIN || 162 if (chip->mgr->is_hr_stereo) {
131 new_volume > PCXHR_ANALOG_PLAYBACK_LEVEL_MAX) 163 if (new_volume < HR222_LINE_PLAYBACK_LEVEL_MIN ||
132 continue; 164 new_volume > HR222_LINE_PLAYBACK_LEVEL_MAX)
165 continue;
166 } else {
167 if (new_volume < PCXHR_LINE_PLAYBACK_LEVEL_MIN ||
168 new_volume > PCXHR_LINE_PLAYBACK_LEVEL_MAX)
169 continue;
170 }
133 } 171 }
134 if (*stored_volume != new_volume) { 172 if (*stored_volume != new_volume) {
135 *stored_volume = new_volume; 173 *stored_volume = new_volume;
136 changed = 1; 174 changed = 1;
137 pcxhr_update_analog_audio_level(chip, is_capture, i); 175 if (chip->mgr->is_hr_stereo)
176 hr222_update_analog_audio_level(chip,
177 is_capture, i);
178 else
179 pcxhr_update_analog_audio_level(chip,
180 is_capture, i);
138 } 181 }
139 } 182 }
140 mutex_unlock(&chip->mgr->mixer_mutex); 183 mutex_unlock(&chip->mgr->mixer_mutex);
@@ -153,6 +196,7 @@ static struct snd_kcontrol_new pcxhr_control_analog_level = {
153}; 196};
154 197
155/* shared */ 198/* shared */
199
156#define pcxhr_sw_info snd_ctl_boolean_stereo_info 200#define pcxhr_sw_info snd_ctl_boolean_stereo_info
157 201
158static int pcxhr_audio_sw_get(struct snd_kcontrol *kcontrol, 202static int pcxhr_audio_sw_get(struct snd_kcontrol *kcontrol,
@@ -180,7 +224,10 @@ static int pcxhr_audio_sw_put(struct snd_kcontrol *kcontrol,
180 !!ucontrol->value.integer.value[i]; 224 !!ucontrol->value.integer.value[i];
181 changed = 1; 225 changed = 1;
182 /* update playback levels */ 226 /* update playback levels */
183 pcxhr_update_analog_audio_level(chip, 0, i); 227 if (chip->mgr->is_hr_stereo)
228 hr222_update_analog_audio_level(chip, 0, i);
229 else
230 pcxhr_update_analog_audio_level(chip, 0, i);
184 } 231 }
185 } 232 }
186 mutex_unlock(&chip->mgr->mixer_mutex); 233 mutex_unlock(&chip->mgr->mixer_mutex);
@@ -251,7 +298,8 @@ static int pcxhr_update_playback_stream_level(struct snd_pcxhr* chip, int idx)
251#define VALID_AUDIO_IO_MUTE_LEVEL 0x000004 298#define VALID_AUDIO_IO_MUTE_LEVEL 0x000004
252#define VALID_AUDIO_IO_MUTE_MONITOR_1 0x000008 299#define VALID_AUDIO_IO_MUTE_MONITOR_1 0x000008
253 300
254static int pcxhr_update_audio_pipe_level(struct snd_pcxhr* chip, int capture, int channel) 301static int pcxhr_update_audio_pipe_level(struct snd_pcxhr *chip,
302 int capture, int channel)
255{ 303{
256 int err; 304 int err;
257 struct pcxhr_rmh rmh; 305 struct pcxhr_rmh rmh;
@@ -264,18 +312,20 @@ static int pcxhr_update_audio_pipe_level(struct snd_pcxhr* chip, int capture, in
264 312
265 pcxhr_init_rmh(&rmh, CMD_AUDIO_LEVEL_ADJUST); 313 pcxhr_init_rmh(&rmh, CMD_AUDIO_LEVEL_ADJUST);
266 /* add channel mask */ 314 /* add channel mask */
267 pcxhr_set_pipe_cmd_params(&rmh, capture, 0, 0, 1 << (channel + pipe->first_audio)); 315 pcxhr_set_pipe_cmd_params(&rmh, capture, 0, 0,
268 /* TODO : if mask (3 << pipe->first_audio) is used, left and right channel 316 1 << (channel + pipe->first_audio));
269 * will be programmed to the same params 317 /* TODO : if mask (3 << pipe->first_audio) is used, left and right
270 */ 318 * channel will be programmed to the same params */
271 if (capture) { 319 if (capture) {
272 rmh.cmd[0] |= VALID_AUDIO_IO_DIGITAL_LEVEL; 320 rmh.cmd[0] |= VALID_AUDIO_IO_DIGITAL_LEVEL;
273 /* VALID_AUDIO_IO_MUTE_LEVEL not yet handled (capture pipe level) */ 321 /* VALID_AUDIO_IO_MUTE_LEVEL not yet handled
322 * (capture pipe level) */
274 rmh.cmd[2] = chip->digital_capture_volume[channel]; 323 rmh.cmd[2] = chip->digital_capture_volume[channel];
275 } else { 324 } else {
276 rmh.cmd[0] |= VALID_AUDIO_IO_MONITOR_LEVEL | VALID_AUDIO_IO_MUTE_MONITOR_1; 325 rmh.cmd[0] |= VALID_AUDIO_IO_MONITOR_LEVEL |
277 /* VALID_AUDIO_IO_DIGITAL_LEVEL and VALID_AUDIO_IO_MUTE_LEVEL not yet 326 VALID_AUDIO_IO_MUTE_MONITOR_1;
278 * handled (playback pipe level) 327 /* VALID_AUDIO_IO_DIGITAL_LEVEL and VALID_AUDIO_IO_MUTE_LEVEL
328 * not yet handled (playback pipe level)
279 */ 329 */
280 rmh.cmd[2] = chip->monitoring_volume[channel] << 10; 330 rmh.cmd[2] = chip->monitoring_volume[channel] << 10;
281 if (chip->monitoring_active[channel] == 0) 331 if (chip->monitoring_active[channel] == 0)
@@ -284,8 +334,8 @@ static int pcxhr_update_audio_pipe_level(struct snd_pcxhr* chip, int capture, in
284 rmh.cmd_len = 3; 334 rmh.cmd_len = 3;
285 335
286 err = pcxhr_send_msg(chip->mgr, &rmh); 336 err = pcxhr_send_msg(chip->mgr, &rmh);
287 if(err<0) { 337 if (err < 0) {
288 snd_printk(KERN_DEBUG "error update_audio_level card(%d) err(%x)\n", 338 snd_printk(KERN_DEBUG "error update_audio_level(%d) err=%x\n",
289 chip->chip_idx, err); 339 chip->chip_idx, err);
290 return -EINVAL; 340 return -EINVAL;
291 } 341 }
@@ -309,15 +359,15 @@ static int pcxhr_pcm_vol_get(struct snd_kcontrol *kcontrol,
309 struct snd_ctl_elem_value *ucontrol) 359 struct snd_ctl_elem_value *ucontrol)
310{ 360{
311 struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol); 361 struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol);
312 int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); /* index */ 362 int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); /* index */
313 int *stored_volume; 363 int *stored_volume;
314 int is_capture = kcontrol->private_value; 364 int is_capture = kcontrol->private_value;
315 365
316 mutex_lock(&chip->mgr->mixer_mutex); 366 mutex_lock(&chip->mgr->mixer_mutex);
317 if (is_capture) 367 if (is_capture) /* digital capture */
318 stored_volume = chip->digital_capture_volume; /* digital capture */ 368 stored_volume = chip->digital_capture_volume;
319 else 369 else /* digital playback */
320 stored_volume = chip->digital_playback_volume[idx]; /* digital playback */ 370 stored_volume = chip->digital_playback_volume[idx];
321 ucontrol->value.integer.value[0] = stored_volume[0]; 371 ucontrol->value.integer.value[0] = stored_volume[0];
322 ucontrol->value.integer.value[1] = stored_volume[1]; 372 ucontrol->value.integer.value[1] = stored_volume[1];
323 mutex_unlock(&chip->mgr->mixer_mutex); 373 mutex_unlock(&chip->mgr->mixer_mutex);
@@ -328,7 +378,7 @@ static int pcxhr_pcm_vol_put(struct snd_kcontrol *kcontrol,
328 struct snd_ctl_elem_value *ucontrol) 378 struct snd_ctl_elem_value *ucontrol)
329{ 379{
330 struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol); 380 struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol);
331 int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); /* index */ 381 int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); /* index */
332 int changed = 0; 382 int changed = 0;
333 int is_capture = kcontrol->private_value; 383 int is_capture = kcontrol->private_value;
334 int *stored_volume; 384 int *stored_volume;
@@ -384,7 +434,8 @@ static int pcxhr_pcm_sw_get(struct snd_kcontrol *kcontrol,
384 return 0; 434 return 0;
385} 435}
386 436
387static int pcxhr_pcm_sw_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 437static int pcxhr_pcm_sw_put(struct snd_kcontrol *kcontrol,
438 struct snd_ctl_elem_value *ucontrol)
388{ 439{
389 struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol); 440 struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol);
390 int changed = 0; 441 int changed = 0;
@@ -444,8 +495,8 @@ static int pcxhr_monitor_vol_put(struct snd_kcontrol *kcontrol,
444 if (chip->monitoring_volume[i] != 495 if (chip->monitoring_volume[i] !=
445 ucontrol->value.integer.value[i]) { 496 ucontrol->value.integer.value[i]) {
446 chip->monitoring_volume[i] = 497 chip->monitoring_volume[i] =
447 !!ucontrol->value.integer.value[i]; 498 ucontrol->value.integer.value[i];
448 if(chip->monitoring_active[i]) 499 if (chip->monitoring_active[i])
449 /* update monitoring volume and mute */ 500 /* update monitoring volume and mute */
450 /* do only when monitoring is unmuted */ 501 /* do only when monitoring is unmuted */
451 pcxhr_update_audio_pipe_level(chip, 0, i); 502 pcxhr_update_audio_pipe_level(chip, 0, i);
@@ -460,7 +511,7 @@ static struct snd_kcontrol_new pcxhr_control_monitor_vol = {
460 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 511 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
461 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE | 512 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
462 SNDRV_CTL_ELEM_ACCESS_TLV_READ), 513 SNDRV_CTL_ELEM_ACCESS_TLV_READ),
463 .name = "Monitoring Volume", 514 .name = "Monitoring Playback Volume",
464 .info = pcxhr_digital_vol_info, /* shared */ 515 .info = pcxhr_digital_vol_info, /* shared */
465 .get = pcxhr_monitor_vol_get, 516 .get = pcxhr_monitor_vol_get,
466 .put = pcxhr_monitor_vol_put, 517 .put = pcxhr_monitor_vol_put,
@@ -511,7 +562,7 @@ static int pcxhr_monitor_sw_put(struct snd_kcontrol *kcontrol,
511 562
512static struct snd_kcontrol_new pcxhr_control_monitor_sw = { 563static struct snd_kcontrol_new pcxhr_control_monitor_sw = {
513 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 564 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
514 .name = "Monitoring Switch", 565 .name = "Monitoring Playback Switch",
515 .info = pcxhr_sw_info, /* shared */ 566 .info = pcxhr_sw_info, /* shared */
516 .get = pcxhr_monitor_sw_get, 567 .get = pcxhr_monitor_sw_get,
517 .put = pcxhr_monitor_sw_put 568 .put = pcxhr_monitor_sw_put
@@ -533,7 +584,7 @@ static int pcxhr_set_audio_source(struct snd_pcxhr* chip)
533 struct pcxhr_rmh rmh; 584 struct pcxhr_rmh rmh;
534 unsigned int mask, reg; 585 unsigned int mask, reg;
535 unsigned int codec; 586 unsigned int codec;
536 int err, use_src, changed; 587 int err, changed;
537 588
538 switch (chip->chip_idx) { 589 switch (chip->chip_idx) {
539 case 0 : mask = PCXHR_SOURCE_AUDIO01_UER; codec = CS8420_01_CS; break; 590 case 0 : mask = PCXHR_SOURCE_AUDIO01_UER; codec = CS8420_01_CS; break;
@@ -542,13 +593,10 @@ static int pcxhr_set_audio_source(struct snd_pcxhr* chip)
542 case 3 : mask = PCXHR_SOURCE_AUDIO67_UER; codec = CS8420_67_CS; break; 593 case 3 : mask = PCXHR_SOURCE_AUDIO67_UER; codec = CS8420_67_CS; break;
543 default: return -EINVAL; 594 default: return -EINVAL;
544 } 595 }
545 reg = 0; /* audio source from analog plug */
546 use_src = 0; /* do not activate codec SRC */
547
548 if (chip->audio_capture_source != 0) { 596 if (chip->audio_capture_source != 0) {
549 reg = mask; /* audio source from digital plug */ 597 reg = mask; /* audio source from digital plug */
550 if (chip->audio_capture_source == 2) 598 } else {
551 use_src = 1; 599 reg = 0; /* audio source from analog plug */
552 } 600 }
553 /* set the input source */ 601 /* set the input source */
554 pcxhr_write_io_num_reg_cont(chip->mgr, mask, reg, &changed); 602 pcxhr_write_io_num_reg_cont(chip->mgr, mask, reg, &changed);
@@ -560,29 +608,61 @@ static int pcxhr_set_audio_source(struct snd_pcxhr* chip)
560 if (err) 608 if (err)
561 return err; 609 return err;
562 } 610 }
563 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE); /* set codec SRC on off */ 611 if (chip->mgr->board_aes_in_192k) {
564 rmh.cmd_len = 3; 612 int i;
565 rmh.cmd[0] |= IO_NUM_UER_CHIP_REG; 613 unsigned int src_config = 0xC0;
566 rmh.cmd[1] = codec; 614 /* update all src configs with one call */
567 rmh.cmd[2] = (CS8420_DATA_FLOW_CTL & CHIP_SIG_AND_MAP_SPI) | (use_src ? 0x41 : 0x54); 615 for (i = 0; (i < 4) && (i < chip->mgr->capture_chips); i++) {
568 err = pcxhr_send_msg(chip->mgr, &rmh); 616 if (chip->mgr->chip[i]->audio_capture_source == 2)
569 if(err) 617 src_config |= (1 << (3 - i));
570 return err; 618 }
571 rmh.cmd[2] = (CS8420_CLOCK_SRC_CTL & CHIP_SIG_AND_MAP_SPI) | (use_src ? 0x41 : 0x49); 619 /* set codec SRC on off */
572 err = pcxhr_send_msg(chip->mgr, &rmh); 620 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE);
621 rmh.cmd_len = 2;
622 rmh.cmd[0] |= IO_NUM_REG_CONFIG_SRC;
623 rmh.cmd[1] = src_config;
624 err = pcxhr_send_msg(chip->mgr, &rmh);
625 } else {
626 int use_src = 0;
627 if (chip->audio_capture_source == 2)
628 use_src = 1;
629 /* set codec SRC on off */
630 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE);
631 rmh.cmd_len = 3;
632 rmh.cmd[0] |= IO_NUM_UER_CHIP_REG;
633 rmh.cmd[1] = codec;
634 rmh.cmd[2] = ((CS8420_DATA_FLOW_CTL & CHIP_SIG_AND_MAP_SPI) |
635 (use_src ? 0x41 : 0x54));
636 err = pcxhr_send_msg(chip->mgr, &rmh);
637 if (err)
638 return err;
639 rmh.cmd[2] = ((CS8420_CLOCK_SRC_CTL & CHIP_SIG_AND_MAP_SPI) |
640 (use_src ? 0x41 : 0x49));
641 err = pcxhr_send_msg(chip->mgr, &rmh);
642 }
573 return err; 643 return err;
574} 644}
575 645
576static int pcxhr_audio_src_info(struct snd_kcontrol *kcontrol, 646static int pcxhr_audio_src_info(struct snd_kcontrol *kcontrol,
577 struct snd_ctl_elem_info *uinfo) 647 struct snd_ctl_elem_info *uinfo)
578{ 648{
579 static char *texts[3] = {"Analog", "Digital", "Digi+SRC"}; 649 static const char *texts[5] = {
650 "Line", "Digital", "Digi+SRC", "Mic", "Line+Mic"
651 };
652 int i;
653 struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol);
580 654
655 i = 2; /* no SRC, no Mic available */
656 if (chip->mgr->board_has_aes1) {
657 i = 3; /* SRC available */
658 if (chip->mgr->board_has_mic)
659 i = 5; /* Mic and MicroMix available */
660 }
581 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 661 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
582 uinfo->count = 1; 662 uinfo->count = 1;
583 uinfo->value.enumerated.items = 3; 663 uinfo->value.enumerated.items = i;
584 if (uinfo->value.enumerated.item > 2) 664 if (uinfo->value.enumerated.item > (i-1))
585 uinfo->value.enumerated.item = 2; 665 uinfo->value.enumerated.item = i-1;
586 strcpy(uinfo->value.enumerated.name, 666 strcpy(uinfo->value.enumerated.name,
587 texts[uinfo->value.enumerated.item]); 667 texts[uinfo->value.enumerated.item]);
588 return 0; 668 return 0;
@@ -601,13 +681,21 @@ static int pcxhr_audio_src_put(struct snd_kcontrol *kcontrol,
601{ 681{
602 struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol); 682 struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol);
603 int ret = 0; 683 int ret = 0;
604 684 int i = 2; /* no SRC, no Mic available */
605 if (ucontrol->value.enumerated.item[0] >= 3) 685 if (chip->mgr->board_has_aes1) {
686 i = 3; /* SRC available */
687 if (chip->mgr->board_has_mic)
688 i = 5; /* Mic and MicroMix available */
689 }
690 if (ucontrol->value.enumerated.item[0] >= i)
606 return -EINVAL; 691 return -EINVAL;
607 mutex_lock(&chip->mgr->mixer_mutex); 692 mutex_lock(&chip->mgr->mixer_mutex);
608 if (chip->audio_capture_source != ucontrol->value.enumerated.item[0]) { 693 if (chip->audio_capture_source != ucontrol->value.enumerated.item[0]) {
609 chip->audio_capture_source = ucontrol->value.enumerated.item[0]; 694 chip->audio_capture_source = ucontrol->value.enumerated.item[0];
610 pcxhr_set_audio_source(chip); 695 if (chip->mgr->is_hr_stereo)
696 hr222_set_audio_source(chip);
697 else
698 pcxhr_set_audio_source(chip);
611 ret = 1; 699 ret = 1;
612 } 700 }
613 mutex_unlock(&chip->mgr->mixer_mutex); 701 mutex_unlock(&chip->mgr->mixer_mutex);
@@ -626,25 +714,46 @@ static struct snd_kcontrol_new pcxhr_control_audio_src = {
626/* 714/*
627 * clock type selection 715 * clock type selection
628 * enum pcxhr_clock_type { 716 * enum pcxhr_clock_type {
629 * PCXHR_CLOCK_TYPE_INTERNAL = 0, 717 * PCXHR_CLOCK_TYPE_INTERNAL = 0,
630 * PCXHR_CLOCK_TYPE_WORD_CLOCK, 718 * PCXHR_CLOCK_TYPE_WORD_CLOCK,
631 * PCXHR_CLOCK_TYPE_AES_SYNC, 719 * PCXHR_CLOCK_TYPE_AES_SYNC,
632 * PCXHR_CLOCK_TYPE_AES_1, 720 * PCXHR_CLOCK_TYPE_AES_1,
633 * PCXHR_CLOCK_TYPE_AES_2, 721 * PCXHR_CLOCK_TYPE_AES_2,
634 * PCXHR_CLOCK_TYPE_AES_3, 722 * PCXHR_CLOCK_TYPE_AES_3,
635 * PCXHR_CLOCK_TYPE_AES_4, 723 * PCXHR_CLOCK_TYPE_AES_4,
636 * }; 724 * PCXHR_CLOCK_TYPE_MAX = PCXHR_CLOCK_TYPE_AES_4,
725 * HR22_CLOCK_TYPE_INTERNAL = PCXHR_CLOCK_TYPE_INTERNAL,
726 * HR22_CLOCK_TYPE_AES_SYNC,
727 * HR22_CLOCK_TYPE_AES_1,
728 * HR22_CLOCK_TYPE_MAX = HR22_CLOCK_TYPE_AES_1,
729 * };
637 */ 730 */
638 731
639static int pcxhr_clock_type_info(struct snd_kcontrol *kcontrol, 732static int pcxhr_clock_type_info(struct snd_kcontrol *kcontrol,
640 struct snd_ctl_elem_info *uinfo) 733 struct snd_ctl_elem_info *uinfo)
641{ 734{
642 static char *texts[7] = { 735 static const char *textsPCXHR[7] = {
643 "Internal", "WordClock", "AES Sync", "AES 1", "AES 2", "AES 3", "AES 4" 736 "Internal", "WordClock", "AES Sync",
737 "AES 1", "AES 2", "AES 3", "AES 4"
738 };
739 static const char *textsHR22[3] = {
740 "Internal", "AES Sync", "AES 1"
644 }; 741 };
742 const char **texts;
645 struct pcxhr_mgr *mgr = snd_kcontrol_chip(kcontrol); 743 struct pcxhr_mgr *mgr = snd_kcontrol_chip(kcontrol);
646 int clock_items = 3 + mgr->capture_chips; 744 int clock_items = 2; /* at least Internal and AES Sync clock */
647 745 if (mgr->board_has_aes1) {
746 clock_items += mgr->capture_chips; /* add AES x */
747 if (!mgr->is_hr_stereo)
748 clock_items += 1; /* add word clock */
749 }
750 if (mgr->is_hr_stereo) {
751 texts = textsHR22;
752 snd_BUG_ON(clock_items > (HR22_CLOCK_TYPE_MAX+1));
753 } else {
754 texts = textsPCXHR;
755 snd_BUG_ON(clock_items > (PCXHR_CLOCK_TYPE_MAX+1));
756 }
648 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 757 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
649 uinfo->count = 1; 758 uinfo->count = 1;
650 uinfo->value.enumerated.items = clock_items; 759 uinfo->value.enumerated.items = clock_items;
@@ -667,9 +776,13 @@ static int pcxhr_clock_type_put(struct snd_kcontrol *kcontrol,
667 struct snd_ctl_elem_value *ucontrol) 776 struct snd_ctl_elem_value *ucontrol)
668{ 777{
669 struct pcxhr_mgr *mgr = snd_kcontrol_chip(kcontrol); 778 struct pcxhr_mgr *mgr = snd_kcontrol_chip(kcontrol);
670 unsigned int clock_items = 3 + mgr->capture_chips;
671 int rate, ret = 0; 779 int rate, ret = 0;
672 780 unsigned int clock_items = 2; /* at least Internal and AES Sync clock */
781 if (mgr->board_has_aes1) {
782 clock_items += mgr->capture_chips; /* add AES x */
783 if (!mgr->is_hr_stereo)
784 clock_items += 1; /* add word clock */
785 }
673 if (ucontrol->value.enumerated.item[0] >= clock_items) 786 if (ucontrol->value.enumerated.item[0] >= clock_items)
674 return -EINVAL; 787 return -EINVAL;
675 mutex_lock(&mgr->mixer_mutex); 788 mutex_lock(&mgr->mixer_mutex);
@@ -677,7 +790,8 @@ static int pcxhr_clock_type_put(struct snd_kcontrol *kcontrol,
677 mutex_lock(&mgr->setup_mutex); 790 mutex_lock(&mgr->setup_mutex);
678 mgr->use_clock_type = ucontrol->value.enumerated.item[0]; 791 mgr->use_clock_type = ucontrol->value.enumerated.item[0];
679 if (mgr->use_clock_type) 792 if (mgr->use_clock_type)
680 pcxhr_get_external_clock(mgr, mgr->use_clock_type, &rate); 793 pcxhr_get_external_clock(mgr, mgr->use_clock_type,
794 &rate);
681 else 795 else
682 rate = mgr->sample_rate; 796 rate = mgr->sample_rate;
683 if (rate) { 797 if (rate) {
@@ -686,7 +800,7 @@ static int pcxhr_clock_type_put(struct snd_kcontrol *kcontrol,
686 mgr->sample_rate = rate; 800 mgr->sample_rate = rate;
687 } 801 }
688 mutex_unlock(&mgr->setup_mutex); 802 mutex_unlock(&mgr->setup_mutex);
689 ret = 1; /* return 1 even if the set was not done. ok ? */ 803 ret = 1; /* return 1 even if the set was not done. ok ? */
690 } 804 }
691 mutex_unlock(&mgr->mixer_mutex); 805 mutex_unlock(&mgr->mixer_mutex);
692 return ret; 806 return ret;
@@ -747,14 +861,16 @@ static struct snd_kcontrol_new pcxhr_control_clock_rate = {
747/* 861/*
748 * IEC958 status bits 862 * IEC958 status bits
749 */ 863 */
750static int pcxhr_iec958_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 864static int pcxhr_iec958_info(struct snd_kcontrol *kcontrol,
865 struct snd_ctl_elem_info *uinfo)
751{ 866{
752 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 867 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
753 uinfo->count = 1; 868 uinfo->count = 1;
754 return 0; 869 return 0;
755} 870}
756 871
757static int pcxhr_iec958_capture_byte(struct snd_pcxhr *chip, int aes_idx, unsigned char* aes_bits) 872static int pcxhr_iec958_capture_byte(struct snd_pcxhr *chip,
873 int aes_idx, unsigned char *aes_bits)
758{ 874{
759 int i, err; 875 int i, err;
760 unsigned char temp; 876 unsigned char temp;
@@ -763,39 +879,61 @@ static int pcxhr_iec958_capture_byte(struct snd_pcxhr *chip, int aes_idx, unsign
763 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_READ); 879 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_READ);
764 rmh.cmd[0] |= IO_NUM_UER_CHIP_REG; 880 rmh.cmd[0] |= IO_NUM_UER_CHIP_REG;
765 switch (chip->chip_idx) { 881 switch (chip->chip_idx) {
766 case 0: rmh.cmd[1] = CS8420_01_CS; break; /* use CS8416_01_CS for AES SYNC plug */ 882 /* instead of CS8420_01_CS use CS8416_01_CS for AES SYNC plug */
883 case 0: rmh.cmd[1] = CS8420_01_CS; break;
767 case 1: rmh.cmd[1] = CS8420_23_CS; break; 884 case 1: rmh.cmd[1] = CS8420_23_CS; break;
768 case 2: rmh.cmd[1] = CS8420_45_CS; break; 885 case 2: rmh.cmd[1] = CS8420_45_CS; break;
769 case 3: rmh.cmd[1] = CS8420_67_CS; break; 886 case 3: rmh.cmd[1] = CS8420_67_CS; break;
770 default: return -EINVAL; 887 default: return -EINVAL;
771 } 888 }
772 switch (aes_idx) { 889 if (chip->mgr->board_aes_in_192k) {
773 case 0: rmh.cmd[2] = CS8420_CSB0; break; /* use CS8416_CSBx for AES SYNC plug */ 890 switch (aes_idx) {
774 case 1: rmh.cmd[2] = CS8420_CSB1; break; 891 case 0: rmh.cmd[2] = CS8416_CSB0; break;
775 case 2: rmh.cmd[2] = CS8420_CSB2; break; 892 case 1: rmh.cmd[2] = CS8416_CSB1; break;
776 case 3: rmh.cmd[2] = CS8420_CSB3; break; 893 case 2: rmh.cmd[2] = CS8416_CSB2; break;
777 case 4: rmh.cmd[2] = CS8420_CSB4; break; 894 case 3: rmh.cmd[2] = CS8416_CSB3; break;
778 default: return -EINVAL; 895 case 4: rmh.cmd[2] = CS8416_CSB4; break;
896 default: return -EINVAL;
897 }
898 } else {
899 switch (aes_idx) {
900 /* instead of CS8420_CSB0 use CS8416_CSBx for AES SYNC plug */
901 case 0: rmh.cmd[2] = CS8420_CSB0; break;
902 case 1: rmh.cmd[2] = CS8420_CSB1; break;
903 case 2: rmh.cmd[2] = CS8420_CSB2; break;
904 case 3: rmh.cmd[2] = CS8420_CSB3; break;
905 case 4: rmh.cmd[2] = CS8420_CSB4; break;
906 default: return -EINVAL;
907 }
779 } 908 }
780 rmh.cmd[1] &= 0x0fffff; /* size and code the chip id for the fpga */ 909 /* size and code the chip id for the fpga */
781 rmh.cmd[2] &= CHIP_SIG_AND_MAP_SPI; /* chip signature + map for spi read */ 910 rmh.cmd[1] &= 0x0fffff;
911 /* chip signature + map for spi read */
912 rmh.cmd[2] &= CHIP_SIG_AND_MAP_SPI;
782 rmh.cmd_len = 3; 913 rmh.cmd_len = 3;
783 err = pcxhr_send_msg(chip->mgr, &rmh); 914 err = pcxhr_send_msg(chip->mgr, &rmh);
784 if (err) 915 if (err)
785 return err; 916 return err;
786 temp = 0; 917
787 for (i = 0; i < 8; i++) { 918 if (chip->mgr->board_aes_in_192k) {
788 /* attention : reversed bit order (not with CS8416_01_CS) */ 919 temp = (unsigned char)rmh.stat[1];
789 temp <<= 1; 920 } else {
790 if (rmh.stat[1] & (1 << i)) 921 temp = 0;
791 temp |= 1; 922 /* reversed bit order (not with CS8416_01_CS) */
923 for (i = 0; i < 8; i++) {
924 temp <<= 1;
925 if (rmh.stat[1] & (1 << i))
926 temp |= 1;
927 }
792 } 928 }
793 snd_printdd("read iec958 AES %d byte %d = 0x%x\n", chip->chip_idx, aes_idx, temp); 929 snd_printdd("read iec958 AES %d byte %d = 0x%x\n",
930 chip->chip_idx, aes_idx, temp);
794 *aes_bits = temp; 931 *aes_bits = temp;
795 return 0; 932 return 0;
796} 933}
797 934
798static int pcxhr_iec958_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 935static int pcxhr_iec958_get(struct snd_kcontrol *kcontrol,
936 struct snd_ctl_elem_value *ucontrol)
799{ 937{
800 struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol); 938 struct snd_pcxhr *chip = snd_kcontrol_chip(kcontrol);
801 unsigned char aes_bits; 939 unsigned char aes_bits;
@@ -806,7 +944,12 @@ static int pcxhr_iec958_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_v
806 if (kcontrol->private_value == 0) /* playback */ 944 if (kcontrol->private_value == 0) /* playback */
807 aes_bits = chip->aes_bits[i]; 945 aes_bits = chip->aes_bits[i];
808 else { /* capture */ 946 else { /* capture */
809 err = pcxhr_iec958_capture_byte(chip, i, &aes_bits); 947 if (chip->mgr->is_hr_stereo)
948 err = hr222_iec958_capture_byte(chip, i,
949 &aes_bits);
950 else
951 err = pcxhr_iec958_capture_byte(chip, i,
952 &aes_bits);
810 if (err) 953 if (err)
811 break; 954 break;
812 } 955 }
@@ -825,7 +968,8 @@ static int pcxhr_iec958_mask_get(struct snd_kcontrol *kcontrol,
825 return 0; 968 return 0;
826} 969}
827 970
828static int pcxhr_iec958_update_byte(struct snd_pcxhr *chip, int aes_idx, unsigned char aes_bits) 971static int pcxhr_iec958_update_byte(struct snd_pcxhr *chip,
972 int aes_idx, unsigned char aes_bits)
829{ 973{
830 int i, err, cmd; 974 int i, err, cmd;
831 unsigned char new_bits = aes_bits; 975 unsigned char new_bits = aes_bits;
@@ -834,12 +978,12 @@ static int pcxhr_iec958_update_byte(struct snd_pcxhr *chip, int aes_idx, unsigne
834 978
835 for (i = 0; i < 8; i++) { 979 for (i = 0; i < 8; i++) {
836 if ((old_bits & 0x01) != (new_bits & 0x01)) { 980 if ((old_bits & 0x01) != (new_bits & 0x01)) {
837 cmd = chip->chip_idx & 0x03; /* chip index 0..3 */ 981 cmd = chip->chip_idx & 0x03; /* chip index 0..3 */
838 if(chip->chip_idx > 3) 982 if (chip->chip_idx > 3)
839 /* new bit used if chip_idx>3 (PCX1222HR) */ 983 /* new bit used if chip_idx>3 (PCX1222HR) */
840 cmd |= 1 << 22; 984 cmd |= 1 << 22;
841 cmd |= ((aes_idx << 3) + i) << 2; /* add bit offset */ 985 cmd |= ((aes_idx << 3) + i) << 2; /* add bit offset */
842 cmd |= (new_bits & 0x01) << 23; /* add bit value */ 986 cmd |= (new_bits & 0x01) << 23; /* add bit value */
843 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE); 987 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE);
844 rmh.cmd[0] |= IO_NUM_REG_CUER; 988 rmh.cmd[0] |= IO_NUM_REG_CUER;
845 rmh.cmd[1] = cmd; 989 rmh.cmd[1] = cmd;
@@ -867,7 +1011,12 @@ static int pcxhr_iec958_put(struct snd_kcontrol *kcontrol,
867 mutex_lock(&chip->mgr->mixer_mutex); 1011 mutex_lock(&chip->mgr->mixer_mutex);
868 for (i = 0; i < 5; i++) { 1012 for (i = 0; i < 5; i++) {
869 if (ucontrol->value.iec958.status[i] != chip->aes_bits[i]) { 1013 if (ucontrol->value.iec958.status[i] != chip->aes_bits[i]) {
870 pcxhr_iec958_update_byte(chip, i, ucontrol->value.iec958.status[i]); 1014 if (chip->mgr->is_hr_stereo)
1015 hr222_iec958_update_byte(chip, i,
1016 ucontrol->value.iec958.status[i]);
1017 else
1018 pcxhr_iec958_update_byte(chip, i,
1019 ucontrol->value.iec958.status[i]);
871 changed = 1; 1020 changed = 1;
872 } 1021 }
873 } 1022 }
@@ -917,29 +1066,53 @@ static void pcxhr_init_audio_levels(struct snd_pcxhr *chip)
917 /* at boot time the digital volumes are unmuted 0dB */ 1066 /* at boot time the digital volumes are unmuted 0dB */
918 for (j = 0; j < PCXHR_PLAYBACK_STREAMS; j++) { 1067 for (j = 0; j < PCXHR_PLAYBACK_STREAMS; j++) {
919 chip->digital_playback_active[j][i] = 1; 1068 chip->digital_playback_active[j][i] = 1;
920 chip->digital_playback_volume[j][i] = PCXHR_DIGITAL_ZERO_LEVEL; 1069 chip->digital_playback_volume[j][i] =
1070 PCXHR_DIGITAL_ZERO_LEVEL;
921 } 1071 }
922 /* after boot, only two bits are set on the uer interface */ 1072 /* after boot, only two bits are set on the uer
923 chip->aes_bits[0] = IEC958_AES0_PROFESSIONAL | IEC958_AES0_PRO_FS_48000; 1073 * interface
924/* only for test purpose, remove later */ 1074 */
1075 chip->aes_bits[0] = (IEC958_AES0_PROFESSIONAL |
1076 IEC958_AES0_PRO_FS_48000);
925#ifdef CONFIG_SND_DEBUG 1077#ifdef CONFIG_SND_DEBUG
926 /* analog volumes for playback (is LEVEL_MIN after boot) */ 1078 /* analog volumes for playback
1079 * (is LEVEL_MIN after boot)
1080 */
927 chip->analog_playback_active[i] = 1; 1081 chip->analog_playback_active[i] = 1;
928 chip->analog_playback_volume[i] = PCXHR_ANALOG_PLAYBACK_ZERO_LEVEL; 1082 if (chip->mgr->is_hr_stereo)
929 pcxhr_update_analog_audio_level(chip, 0, i); 1083 chip->analog_playback_volume[i] =
1084 HR222_LINE_PLAYBACK_ZERO_LEVEL;
1085 else {
1086 chip->analog_playback_volume[i] =
1087 PCXHR_LINE_PLAYBACK_ZERO_LEVEL;
1088 pcxhr_update_analog_audio_level(chip, 0, i);
1089 }
930#endif 1090#endif
931/* test end */ 1091 /* stereo cards need to be initialised after boot */
1092 if (chip->mgr->is_hr_stereo)
1093 hr222_update_analog_audio_level(chip, 0, i);
932 } 1094 }
933 if (chip->nb_streams_capt) { 1095 if (chip->nb_streams_capt) {
934 /* at boot time the digital volumes are unmuted 0dB */ 1096 /* at boot time the digital volumes are unmuted 0dB */
935 chip->digital_capture_volume[i] = PCXHR_DIGITAL_ZERO_LEVEL; 1097 chip->digital_capture_volume[i] =
936/* only for test purpose, remove later */ 1098 PCXHR_DIGITAL_ZERO_LEVEL;
1099 chip->analog_capture_active = 1;
937#ifdef CONFIG_SND_DEBUG 1100#ifdef CONFIG_SND_DEBUG
938 /* analog volumes for playback (is LEVEL_MIN after boot) */ 1101 /* analog volumes for playback
939 chip->analog_capture_volume[i] = PCXHR_ANALOG_CAPTURE_ZERO_LEVEL; 1102 * (is LEVEL_MIN after boot)
940 pcxhr_update_analog_audio_level(chip, 1, i); 1103 */
1104 if (chip->mgr->is_hr_stereo)
1105 chip->analog_capture_volume[i] =
1106 HR222_LINE_CAPTURE_ZERO_LEVEL;
1107 else {
1108 chip->analog_capture_volume[i] =
1109 PCXHR_LINE_CAPTURE_ZERO_LEVEL;
1110 pcxhr_update_analog_audio_level(chip, 1, i);
1111 }
941#endif 1112#endif
942/* test end */ 1113 /* stereo cards need to be initialised after boot */
1114 if (chip->mgr->is_hr_stereo)
1115 hr222_update_analog_audio_level(chip, 1, i);
943 } 1116 }
944 } 1117 }
945 1118
@@ -963,90 +1136,125 @@ int pcxhr_create_mixer(struct pcxhr_mgr *mgr)
963 temp = pcxhr_control_analog_level; 1136 temp = pcxhr_control_analog_level;
964 temp.name = "Master Playback Volume"; 1137 temp.name = "Master Playback Volume";
965 temp.private_value = 0; /* playback */ 1138 temp.private_value = 0; /* playback */
966 temp.tlv.p = db_scale_analog_playback; 1139 if (mgr->is_hr_stereo)
967 if ((err = snd_ctl_add(chip->card, snd_ctl_new1(&temp, chip))) < 0) 1140 temp.tlv.p = db_scale_a_hr222_playback;
1141 else
1142 temp.tlv.p = db_scale_analog_playback;
1143 err = snd_ctl_add(chip->card,
1144 snd_ctl_new1(&temp, chip));
1145 if (err < 0)
968 return err; 1146 return err;
1147
969 /* output mute controls */ 1148 /* output mute controls */
970 if ((err = snd_ctl_add(chip->card, 1149 err = snd_ctl_add(chip->card,
971 snd_ctl_new1(&pcxhr_control_output_switch, 1150 snd_ctl_new1(&pcxhr_control_output_switch,
972 chip))) < 0) 1151 chip));
1152 if (err < 0)
973 return err; 1153 return err;
974 1154
975 temp = snd_pcxhr_pcm_vol; 1155 temp = snd_pcxhr_pcm_vol;
976 temp.name = "PCM Playback Volume"; 1156 temp.name = "PCM Playback Volume";
977 temp.count = PCXHR_PLAYBACK_STREAMS; 1157 temp.count = PCXHR_PLAYBACK_STREAMS;
978 temp.private_value = 0; /* playback */ 1158 temp.private_value = 0; /* playback */
979 if ((err = snd_ctl_add(chip->card, snd_ctl_new1(&temp, chip))) < 0) 1159 err = snd_ctl_add(chip->card,
1160 snd_ctl_new1(&temp, chip));
1161 if (err < 0)
980 return err; 1162 return err;
981 1163
982 if ((err = snd_ctl_add(chip->card, 1164 err = snd_ctl_add(chip->card,
983 snd_ctl_new1(&pcxhr_control_pcm_switch, 1165 snd_ctl_new1(&pcxhr_control_pcm_switch, chip));
984 chip))) < 0) 1166 if (err < 0)
985 return err; 1167 return err;
986 1168
987 /* IEC958 controls */ 1169 /* IEC958 controls */
988 if ((err = snd_ctl_add(chip->card, 1170 err = snd_ctl_add(chip->card,
989 snd_ctl_new1(&pcxhr_control_playback_iec958_mask, 1171 snd_ctl_new1(&pcxhr_control_playback_iec958_mask,
990 chip))) < 0) 1172 chip));
1173 if (err < 0)
991 return err; 1174 return err;
992 if ((err = snd_ctl_add(chip->card, 1175
993 snd_ctl_new1(&pcxhr_control_playback_iec958, 1176 err = snd_ctl_add(chip->card,
994 chip))) < 0) 1177 snd_ctl_new1(&pcxhr_control_playback_iec958,
1178 chip));
1179 if (err < 0)
995 return err; 1180 return err;
996 } 1181 }
997 if (chip->nb_streams_capt) { 1182 if (chip->nb_streams_capt) {
998 /* analog input level control only on first two chips !*/ 1183 /* analog input level control */
999 temp = pcxhr_control_analog_level; 1184 temp = pcxhr_control_analog_level;
1000 temp.name = "Master Capture Volume"; 1185 temp.name = "Line Capture Volume";
1001 temp.private_value = 1; /* capture */ 1186 temp.private_value = 1; /* capture */
1002 temp.tlv.p = db_scale_analog_capture; 1187 if (mgr->is_hr_stereo)
1003 if ((err = snd_ctl_add(chip->card, snd_ctl_new1(&temp, chip))) < 0) 1188 temp.tlv.p = db_scale_a_hr222_capture;
1189 else
1190 temp.tlv.p = db_scale_analog_capture;
1191
1192 err = snd_ctl_add(chip->card,
1193 snd_ctl_new1(&temp, chip));
1194 if (err < 0)
1004 return err; 1195 return err;
1005 1196
1006 temp = snd_pcxhr_pcm_vol; 1197 temp = snd_pcxhr_pcm_vol;
1007 temp.name = "PCM Capture Volume"; 1198 temp.name = "PCM Capture Volume";
1008 temp.count = 1; 1199 temp.count = 1;
1009 temp.private_value = 1; /* capture */ 1200 temp.private_value = 1; /* capture */
1010 if ((err = snd_ctl_add(chip->card, snd_ctl_new1(&temp, chip))) < 0) 1201
1202 err = snd_ctl_add(chip->card,
1203 snd_ctl_new1(&temp, chip));
1204 if (err < 0)
1011 return err; 1205 return err;
1206
1012 /* Audio source */ 1207 /* Audio source */
1013 if ((err = snd_ctl_add(chip->card, 1208 err = snd_ctl_add(chip->card,
1014 snd_ctl_new1(&pcxhr_control_audio_src, 1209 snd_ctl_new1(&pcxhr_control_audio_src, chip));
1015 chip))) < 0) 1210 if (err < 0)
1016 return err; 1211 return err;
1212
1017 /* IEC958 controls */ 1213 /* IEC958 controls */
1018 if ((err = snd_ctl_add(chip->card, 1214 err = snd_ctl_add(chip->card,
1019 snd_ctl_new1(&pcxhr_control_capture_iec958_mask, 1215 snd_ctl_new1(&pcxhr_control_capture_iec958_mask,
1020 chip))) < 0) 1216 chip));
1217 if (err < 0)
1021 return err; 1218 return err;
1022 if ((err = snd_ctl_add(chip->card, 1219
1023 snd_ctl_new1(&pcxhr_control_capture_iec958, 1220 err = snd_ctl_add(chip->card,
1024 chip))) < 0) 1221 snd_ctl_new1(&pcxhr_control_capture_iec958,
1222 chip));
1223 if (err < 0)
1025 return err; 1224 return err;
1225
1226 if (mgr->is_hr_stereo) {
1227 err = hr222_add_mic_controls(chip);
1228 if (err < 0)
1229 return err;
1230 }
1026 } 1231 }
1027 /* monitoring only if playback and capture device available */ 1232 /* monitoring only if playback and capture device available */
1028 if (chip->nb_streams_capt > 0 && chip->nb_streams_play > 0) { 1233 if (chip->nb_streams_capt > 0 && chip->nb_streams_play > 0) {
1029 /* monitoring */ 1234 /* monitoring */
1030 if ((err = snd_ctl_add(chip->card, 1235 err = snd_ctl_add(chip->card,
1031 snd_ctl_new1(&pcxhr_control_monitor_vol, 1236 snd_ctl_new1(&pcxhr_control_monitor_vol, chip));
1032 chip))) < 0) 1237 if (err < 0)
1033 return err; 1238 return err;
1034 if ((err = snd_ctl_add(chip->card, 1239
1035 snd_ctl_new1(&pcxhr_control_monitor_sw, 1240 err = snd_ctl_add(chip->card,
1036 chip))) < 0) 1241 snd_ctl_new1(&pcxhr_control_monitor_sw, chip));
1242 if (err < 0)
1037 return err; 1243 return err;
1038 } 1244 }
1039 1245
1040 if (i == 0) { 1246 if (i == 0) {
1041 /* clock mode only one control per pcxhr */ 1247 /* clock mode only one control per pcxhr */
1042 if ((err = snd_ctl_add(chip->card, 1248 err = snd_ctl_add(chip->card,
1043 snd_ctl_new1(&pcxhr_control_clock_type, 1249 snd_ctl_new1(&pcxhr_control_clock_type, mgr));
1044 mgr))) < 0) 1250 if (err < 0)
1045 return err; 1251 return err;
1046 /* non standard control used to scan the external clock presence/frequencies */ 1252 /* non standard control used to scan
1047 if ((err = snd_ctl_add(chip->card, 1253 * the external clock presence/frequencies
1048 snd_ctl_new1(&pcxhr_control_clock_rate, 1254 */
1049 mgr))) < 0) 1255 err = snd_ctl_add(chip->card,
1256 snd_ctl_new1(&pcxhr_control_clock_rate, mgr));
1257 if (err < 0)
1050 return err; 1258 return err;
1051 } 1259 }
1052 1260
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-02 08:45:25 -0500