90 files changed, 4620 insertions, 3498 deletions

diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBook/drm.tmpl
index 03f1985a4bd1..7a45775518f6 100644
--- a/Documentation/DocBook/drm.tmpl
+++ b/Documentation/DocBook/drm.tmpl
@@ -3979,6 +3979,11 @@ int num_ioctls;</synopsis>
 !Fdrivers/gpu/drm/i915/i915_irq.c intel_runtime_pm_disable_interrupts
 !Fdrivers/gpu/drm/i915/i915_irq.c intel_runtime_pm_enable_interrupts
       </sect2>
+      <sect2>
+        <title>Intel GVT-g Guest Support(vGPU)</title>
+!Pdrivers/gpu/drm/i915/i915_vgpu.c Intel GVT-g guest support
+!Idrivers/gpu/drm/i915/i915_vgpu.c
+      </sect2>
     </sect1>
     <sect1>
       <title>Display Hardware Handling</title>
@@ -4048,6 +4053,17 @@ int num_ioctls;</synopsis>
 !Idrivers/gpu/drm/i915/intel_fbc.c
       </sect2>
       <sect2>
+        <title>Display Refresh Rate Switching (DRRS)</title>
+!Pdrivers/gpu/drm/i915/intel_dp.c Display Refresh Rate Switching (DRRS)
+!Fdrivers/gpu/drm/i915/intel_dp.c intel_dp_set_drrs_state
+!Fdrivers/gpu/drm/i915/intel_dp.c intel_edp_drrs_enable
+!Fdrivers/gpu/drm/i915/intel_dp.c intel_edp_drrs_disable
+!Fdrivers/gpu/drm/i915/intel_dp.c intel_edp_drrs_invalidate
+!Fdrivers/gpu/drm/i915/intel_dp.c intel_edp_drrs_flush
+!Fdrivers/gpu/drm/i915/intel_dp.c intel_dp_drrs_init
+
+      </sect2>
+      <sect2>
         <title>DPIO</title>
 !Pdrivers/gpu/drm/i915/i915_reg.h DPIO
         <table id="dpiox2">
diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
index b3e3068c6ec0..d55c0c232e1d 100644
--- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
+++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
@@ -21,6 +21,7 @@
 #include <linux/clk.h>
 #include <linux/pm.h>
 #include <linux/pm_runtime.h>
+#include <linux/pinctrl/consumer.h>
 
 #include <drm/drm_crtc.h>
 #include <drm/drm_crtc_helper.h>
@@ -37,14 +38,14 @@
  * @hlcdc: pointer to the atmel_hlcdc structure provided by the MFD device
  * @event: pointer to the current page flip event
  * @id: CRTC id (returned by drm_crtc_index)
- * @dpms: DPMS mode
+ * @enabled: CRTC state
  */
 struct atmel_hlcdc_crtc {
         struct drm_crtc base;
         struct atmel_hlcdc_dc *dc;
         struct drm_pending_vblank_event *event;
         int id;
-        int dpms;
+        bool enabled;
 };
 
 static inline struct atmel_hlcdc_crtc *
@@ -53,86 +54,17 @@ drm_crtc_to_atmel_hlcdc_crtc(struct drm_crtc *crtc)
         return container_of(crtc, struct atmel_hlcdc_crtc, base);
 }
 
-static void atmel_hlcdc_crtc_dpms(struct drm_crtc *c, int mode)
-{
-        struct drm_device *dev = c->dev;
-        struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);
-        struct regmap *regmap = crtc->dc->hlcdc->regmap;
-        unsigned int status;
-
-        if (mode != DRM_MODE_DPMS_ON)
-                mode = DRM_MODE_DPMS_OFF;
-
-        if (crtc->dpms == mode)
-                return;
-
-        pm_runtime_get_sync(dev->dev);
-
-        if (mode != DRM_MODE_DPMS_ON) {
-                regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_HLCDC_DISP);
-                while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) &&
-                       (status & ATMEL_HLCDC_DISP))
-                        cpu_relax();
-
-                regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_HLCDC_SYNC);
-                while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) &&
-                       (status & ATMEL_HLCDC_SYNC))
-                        cpu_relax();
-
-                regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_HLCDC_PIXEL_CLK);
-                while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) &&
-                       (status & ATMEL_HLCDC_PIXEL_CLK))
-                        cpu_relax();
-
-                clk_disable_unprepare(crtc->dc->hlcdc->sys_clk);
-
-                pm_runtime_allow(dev->dev);
-        } else {
-                pm_runtime_forbid(dev->dev);
-
-                clk_prepare_enable(crtc->dc->hlcdc->sys_clk);
-
-                regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_HLCDC_PIXEL_CLK);
-                while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) &&
-                       !(status & ATMEL_HLCDC_PIXEL_CLK))
-                        cpu_relax();
-
-
-                regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_HLCDC_SYNC);
-                while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) &&
-                       !(status & ATMEL_HLCDC_SYNC))
-                        cpu_relax();
-
-                regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_HLCDC_DISP);
-                while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) &&
-                       !(status & ATMEL_HLCDC_DISP))
-                        cpu_relax();
-        }
-
-        pm_runtime_put_sync(dev->dev);
-
-        crtc->dpms = mode;
-}
-
-static int atmel_hlcdc_crtc_mode_set(struct drm_crtc *c,
-                                     struct drm_display_mode *mode,
-                                     struct drm_display_mode *adj,
-                                     int x, int y,
-                                     struct drm_framebuffer *old_fb)
+static void atmel_hlcdc_crtc_mode_set_nofb(struct drm_crtc *c)
 {
         struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);
         struct regmap *regmap = crtc->dc->hlcdc->regmap;
-        struct drm_plane *plane = c->primary;
-        struct drm_framebuffer *fb;
+        struct drm_display_mode *adj = &c->state->adjusted_mode;
         unsigned long mode_rate;
         struct videomode vm;
         unsigned long prate;
         unsigned int cfg;
         int div;
 
-        if (atmel_hlcdc_dc_mode_valid(crtc->dc, adj) != MODE_OK)
-                return -EINVAL;
-
         vm.vfront_porch = adj->crtc_vsync_start - adj->crtc_vdisplay;
         vm.vback_porch = adj->crtc_vtotal - adj->crtc_vsync_end;
         vm.vsync_len = adj->crtc_vsync_end - adj->crtc_vsync_start;
@@ -156,7 +88,7 @@ static int atmel_hlcdc_crtc_mode_set(struct drm_crtc *c,
         cfg = 0;
 
         prate = clk_get_rate(crtc->dc->hlcdc->sys_clk);
-        mode_rate = mode->crtc_clock * 1000;
+        mode_rate = adj->crtc_clock * 1000;
         if ((prate / 2) < mode_rate) {
                 prate *= 2;
                 cfg |= ATMEL_HLCDC_CLKSEL;
@@ -174,10 +106,10 @@ static int atmel_hlcdc_crtc_mode_set(struct drm_crtc *c,
 
         cfg = 0;
 
-        if (mode->flags & DRM_MODE_FLAG_NVSYNC)
+        if (adj->flags & DRM_MODE_FLAG_NVSYNC)
                 cfg |= ATMEL_HLCDC_VSPOL;
 
-        if (mode->flags & DRM_MODE_FLAG_NHSYNC)
+        if (adj->flags & DRM_MODE_FLAG_NHSYNC)
                 cfg |= ATMEL_HLCDC_HSPOL;
 
         regmap_update_bits(regmap, ATMEL_HLCDC_CFG(5),
@@ -187,77 +119,134 @@ static int atmel_hlcdc_crtc_mode_set(struct drm_crtc *c,
                            ATMEL_HLCDC_VSPSU | ATMEL_HLCDC_VSPHO |
                            ATMEL_HLCDC_GUARDTIME_MASK,
                            cfg);
-
-        fb = plane->fb;
-        plane->fb = old_fb;
-
-        return atmel_hlcdc_plane_update_with_mode(plane, c, fb, 0, 0,
-                                                  adj->hdisplay, adj->vdisplay,
-                                                  x << 16, y << 16,
-                                                  adj->hdisplay << 16,
-                                                  adj->vdisplay << 16,
-                                                  adj);
 }
 
-int atmel_hlcdc_crtc_mode_set_base(struct drm_crtc *c, int x, int y,
-                                   struct drm_framebuffer *old_fb)
+static bool atmel_hlcdc_crtc_mode_fixup(struct drm_crtc *crtc,
+                                        const struct drm_display_mode *mode,
+                                        struct drm_display_mode *adjusted_mode)
 {
-        struct drm_plane *plane = c->primary;
-        struct drm_framebuffer *fb = plane->fb;
-        struct drm_display_mode *mode = &c->hwmode;
-
-        plane->fb = old_fb;
-
-        return plane->funcs->update_plane(plane, c, fb,
-                                          0, 0,
-                                          mode->hdisplay,
-                                          mode->vdisplay,
-                                          x << 16, y << 16,
-                                          mode->hdisplay << 16,
-                                          mode->vdisplay << 16);
+        return true;
 }
 
-static void atmel_hlcdc_crtc_prepare(struct drm_crtc *crtc)
+static void atmel_hlcdc_crtc_disable(struct drm_crtc *c)
 {
-        atmel_hlcdc_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
+        struct drm_device *dev = c->dev;
+        struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);
+        struct regmap *regmap = crtc->dc->hlcdc->regmap;
+        unsigned int status;
+
+        if (!crtc->enabled)
+                return;
+
+        drm_crtc_vblank_off(c);
+
+        pm_runtime_get_sync(dev->dev);
+
+        regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_HLCDC_DISP);
+        while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) &&
+               (status & ATMEL_HLCDC_DISP))
+                cpu_relax();
+
+        regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_HLCDC_SYNC);
+        while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) &&
+               (status & ATMEL_HLCDC_SYNC))
+                cpu_relax();
+
+        regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_HLCDC_PIXEL_CLK);
+        while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) &&
+               (status & ATMEL_HLCDC_PIXEL_CLK))
+                cpu_relax();
+
+        clk_disable_unprepare(crtc->dc->hlcdc->sys_clk);
+        pinctrl_pm_select_sleep_state(dev->dev);
+
+        pm_runtime_allow(dev->dev);
+
+        pm_runtime_put_sync(dev->dev);
+
+        crtc->enabled = false;
 }
 
-static void atmel_hlcdc_crtc_commit(struct drm_crtc *crtc)
+static void atmel_hlcdc_crtc_enable(struct drm_crtc *c)
 {
-        atmel_hlcdc_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
+        struct drm_device *dev = c->dev;
+        struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);
+        struct regmap *regmap = crtc->dc->hlcdc->regmap;
+        unsigned int status;
+
+        if (crtc->enabled)
+                return;
+
+        pm_runtime_get_sync(dev->dev);
+
+        pm_runtime_forbid(dev->dev);
+
+        pinctrl_pm_select_default_state(dev->dev);
+        clk_prepare_enable(crtc->dc->hlcdc->sys_clk);
+
+        regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_HLCDC_PIXEL_CLK);
+        while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) &&
+               !(status & ATMEL_HLCDC_PIXEL_CLK))
+                cpu_relax();
+
+
+        regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_HLCDC_SYNC);
+        while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) &&
+               !(status & ATMEL_HLCDC_SYNC))
+                cpu_relax();
+
+        regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_HLCDC_DISP);
+        while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) &&
+               !(status & ATMEL_HLCDC_DISP))
+                cpu_relax();
+
+        pm_runtime_put_sync(dev->dev);
+
+        drm_crtc_vblank_on(c);
+
+        crtc->enabled = true;
 }
 
-static bool atmel_hlcdc_crtc_mode_fixup(struct drm_crtc *crtc,
-                                        const struct drm_display_mode *mode,
-                                        struct drm_display_mode *adjusted_mode)
+static int atmel_hlcdc_crtc_atomic_check(struct drm_crtc *c,
+                                         struct drm_crtc_state *s)
 {
-        return true;
+        struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);
+
+        if (atmel_hlcdc_dc_mode_valid(crtc->dc, &s->adjusted_mode) != MODE_OK)
+                return -EINVAL;
+
+        return atmel_hlcdc_plane_prepare_disc_area(s);
 }
 
-static void atmel_hlcdc_crtc_disable(struct drm_crtc *crtc)
+static void atmel_hlcdc_crtc_atomic_begin(struct drm_crtc *c)
 {
-        struct drm_plane *plane;
+        struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);
 
-        atmel_hlcdc_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
-        crtc->primary->funcs->disable_plane(crtc->primary);
+        if (c->state->event) {
+                c->state->event->pipe = drm_crtc_index(c);
 
-        drm_for_each_legacy_plane(plane, &crtc->dev->mode_config.plane_list) {
-                if (plane->crtc != crtc)
-                        continue;
+                WARN_ON(drm_crtc_vblank_get(c) != 0);
 
-                plane->funcs->disable_plane(crtc->primary);
-                plane->crtc = NULL;
+                crtc->event = c->state->event;
+                c->state->event = NULL;
         }
 }
 
+static void atmel_hlcdc_crtc_atomic_flush(struct drm_crtc *crtc)
+{
+        /* TODO: write common plane control register if available */
+}
+
 static const struct drm_crtc_helper_funcs lcdc_crtc_helper_funcs = {
         .mode_fixup = atmel_hlcdc_crtc_mode_fixup,
-        .dpms = atmel_hlcdc_crtc_dpms,
-        .mode_set = atmel_hlcdc_crtc_mode_set,
-        .mode_set_base = atmel_hlcdc_crtc_mode_set_base,
-        .prepare = atmel_hlcdc_crtc_prepare,
-        .commit = atmel_hlcdc_crtc_commit,
+        .mode_set = drm_helper_crtc_mode_set,
+        .mode_set_nofb = atmel_hlcdc_crtc_mode_set_nofb,
+        .mode_set_base = drm_helper_crtc_mode_set_base,
         .disable = atmel_hlcdc_crtc_disable,
+        .enable = atmel_hlcdc_crtc_enable,
+        .atomic_check = atmel_hlcdc_crtc_atomic_check,
+        .atomic_begin = atmel_hlcdc_crtc_atomic_begin,
+        .atomic_flush = atmel_hlcdc_crtc_atomic_flush,
 };
 
 static void atmel_hlcdc_crtc_destroy(struct drm_crtc *c)
@@ -306,61 +295,13 @@ void atmel_hlcdc_crtc_irq(struct drm_crtc *c)
         atmel_hlcdc_crtc_finish_page_flip(drm_crtc_to_atmel_hlcdc_crtc(c));
 }
 
-static int atmel_hlcdc_crtc_page_flip(struct drm_crtc *c,
-                                      struct drm_framebuffer *fb,
-                                      struct drm_pending_vblank_event *event,
-                                      uint32_t page_flip_flags)
-{
-        struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);
-        struct atmel_hlcdc_plane_update_req req;
-        struct drm_plane *plane = c->primary;
-        struct drm_device *dev = c->dev;
-        unsigned long flags;
-        int ret = 0;
-
-        spin_lock_irqsave(&dev->event_lock, flags);
-        if (crtc->event)
-                ret = -EBUSY;
-        spin_unlock_irqrestore(&dev->event_lock, flags);
-
-        if (ret)
-                return ret;
-
-        memset(&req, 0, sizeof(req));
-        req.crtc_x = 0;
-        req.crtc_y = 0;
-        req.crtc_h = c->mode.crtc_vdisplay;
-        req.crtc_w = c->mode.crtc_hdisplay;
-        req.src_x = c->x << 16;
-        req.src_y = c->y << 16;
-        req.src_w = req.crtc_w << 16;
-        req.src_h = req.crtc_h << 16;
-        req.fb = fb;
-
-        ret = atmel_hlcdc_plane_prepare_update_req(plane, &req, &c->hwmode);
-        if (ret)
-                return ret;
-
-        if (event) {
-                drm_vblank_get(c->dev, crtc->id);
-                spin_lock_irqsave(&dev->event_lock, flags);
-                crtc->event = event;
-                spin_unlock_irqrestore(&dev->event_lock, flags);
-        }
-
-        ret = atmel_hlcdc_plane_apply_update_req(plane, &req);
-        if (ret)
-                crtc->event = NULL;
-        else
-                plane->fb = fb;
-
-        return ret;
-}
-
 static const struct drm_crtc_funcs atmel_hlcdc_crtc_funcs = {
-        .page_flip = atmel_hlcdc_crtc_page_flip,
-        .set_config = drm_crtc_helper_set_config,
+        .page_flip = drm_atomic_helper_page_flip,
+        .set_config = drm_atomic_helper_set_config,
         .destroy = atmel_hlcdc_crtc_destroy,
+        .reset = drm_atomic_helper_crtc_reset,
+        .atomic_duplicate_state =  drm_atomic_helper_crtc_duplicate_state,
+        .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
 };
 
 int atmel_hlcdc_crtc_create(struct drm_device *dev)
@@ -375,7 +316,6 @@ int atmel_hlcdc_crtc_create(struct drm_device *dev)
         if (!crtc)
                 return -ENOMEM;
 
-        crtc->dpms = DRM_MODE_DPMS_OFF;
         crtc->dc = dc;
 
         ret = drm_crtc_init_with_planes(dev, &crtc->base,
diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c
index c1cb17493e0d..c4bb1f9f95c6 100644
--- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c
+++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c
@@ -222,6 +222,8 @@ static void atmel_hlcdc_fb_output_poll_changed(struct drm_device *dev)
 static const struct drm_mode_config_funcs mode_config_funcs = {
         .fb_create = atmel_hlcdc_fb_create,
         .output_poll_changed = atmel_hlcdc_fb_output_poll_changed,
+        .atomic_check = drm_atomic_helper_check,
+        .atomic_commit = drm_atomic_helper_commit,
 };
 
 static int atmel_hlcdc_dc_modeset_init(struct drm_device *dev)
@@ -317,6 +319,8 @@ static int atmel_hlcdc_dc_load(struct drm_device *dev)
                 goto err_periph_clk_disable;
         }
 
+        drm_mode_config_reset(dev);
+
         ret = drm_vblank_init(dev, 1);
         if (ret < 0) {
                 dev_err(dev->dev, "failed to initialize vblank\n");
@@ -555,6 +559,52 @@ static int atmel_hlcdc_dc_drm_remove(struct platform_device *pdev)
         return 0;
 }
 
+#ifdef CONFIG_PM
+static int atmel_hlcdc_dc_drm_suspend(struct device *dev)
+{
+        struct drm_device *drm_dev = dev_get_drvdata(dev);
+        struct drm_crtc *crtc;
+
+        if (pm_runtime_suspended(dev))
+                return 0;
+
+        drm_modeset_lock_all(drm_dev);
+        list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
+                struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
+                if (crtc->enabled) {
+                        crtc_funcs->disable(crtc);
+                        /* save enable state for resume */
+                        crtc->enabled = true;
+                }
+        }
+        drm_modeset_unlock_all(drm_dev);
+        return 0;
+}
+
+static int atmel_hlcdc_dc_drm_resume(struct device *dev)
+{
+        struct drm_device *drm_dev = dev_get_drvdata(dev);
+        struct drm_crtc *crtc;
+
+        if (pm_runtime_suspended(dev))
+                return 0;
+
+        drm_modeset_lock_all(drm_dev);
+        list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
+                struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
+                if (crtc->enabled) {
+                        crtc->enabled = false;
+                        crtc_funcs->enable(crtc);
+                }
+        }
+        drm_modeset_unlock_all(drm_dev);
+        return 0;
+}
+#endif
+
+static SIMPLE_DEV_PM_OPS(atmel_hlcdc_dc_drm_pm_ops,
+                atmel_hlcdc_dc_drm_suspend, atmel_hlcdc_dc_drm_resume);
+
 static const struct of_device_id atmel_hlcdc_dc_of_match[] = {
         { .compatible = "atmel,hlcdc-display-controller" },
         { },
@@ -565,6 +615,7 @@ static struct platform_driver atmel_hlcdc_dc_platform_driver = {
         .remove = atmel_hlcdc_dc_drm_remove,
         .driver = {
                 .name   = "atmel-hlcdc-display-controller",
+                .pm     = &atmel_hlcdc_dc_drm_pm_ops,
                 .of_match_table = atmel_hlcdc_dc_of_match,
         },
 };
diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h
index 7bc96af3397a..1ea9c2ccd8a7 100644
--- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h
+++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h
@@ -26,11 +26,14 @@
 #include <linux/irqdomain.h>
 #include <linux/pwm.h>
 
+#include <drm/drm_atomic.h>
+#include <drm/drm_atomic_helper.h>
 #include <drm/drm_crtc.h>
 #include <drm/drm_crtc_helper.h>
 #include <drm/drm_fb_cma_helper.h>
 #include <drm/drm_gem_cma_helper.h>
 #include <drm/drm_panel.h>
+#include <drm/drm_plane_helper.h>
 #include <drm/drmP.h>
 
 #include "atmel_hlcdc_layer.h"
@@ -69,7 +72,6 @@ struct atmel_hlcdc_dc_desc {
  */
 struct atmel_hlcdc_plane_properties {
         struct drm_property *alpha;
-        struct drm_property *rotation;
 };
 
 /**
@@ -84,7 +86,6 @@ struct atmel_hlcdc_plane {
         struct drm_plane base;
         struct atmel_hlcdc_layer layer;
         struct atmel_hlcdc_plane_properties *properties;
-        unsigned int rotation;
 };
 
 static inline struct atmel_hlcdc_plane *
@@ -100,43 +101,6 @@ atmel_hlcdc_layer_to_plane(struct atmel_hlcdc_layer *l)
 }
 
 /**
- * Atmel HLCDC Plane update request structure.
- *
- * @crtc_x: x position of the plane relative to the CRTC
- * @crtc_y: y position of the plane relative to the CRTC
- * @crtc_w: visible width of the plane
- * @crtc_h: visible height of the plane
- * @src_x: x buffer position
- * @src_y: y buffer position
- * @src_w: buffer width
- * @src_h: buffer height
- * @fb: framebuffer object object
- * @bpp: bytes per pixel deduced from pixel_format
- * @offsets: offsets to apply to the GEM buffers
- * @xstride: value to add to the pixel pointer between each line
- * @pstride: value to add to the pixel pointer between each pixel
- * @nplanes: number of planes (deduced from pixel_format)
- */
-struct atmel_hlcdc_plane_update_req {
-        int crtc_x;
-        int crtc_y;
-        unsigned int crtc_w;
-        unsigned int crtc_h;
-        uint32_t src_x;
-        uint32_t src_y;
-        uint32_t src_w;
-        uint32_t src_h;
-        struct drm_framebuffer *fb;
-
-        /* These fields are private and should not be touched */
-        int bpp[ATMEL_HLCDC_MAX_PLANES];
-        unsigned int offsets[ATMEL_HLCDC_MAX_PLANES];
-        int xstride[ATMEL_HLCDC_MAX_PLANES];
-        int pstride[ATMEL_HLCDC_MAX_PLANES];
-        int nplanes;
-};
-
-/**
  * Atmel HLCDC Planes.
  *
  * This structure stores the instantiated HLCDC Planes and can be accessed by
@@ -184,22 +148,7 @@ int atmel_hlcdc_dc_mode_valid(struct atmel_hlcdc_dc *dc,
 struct atmel_hlcdc_planes *
 atmel_hlcdc_create_planes(struct drm_device *dev);
 
-int atmel_hlcdc_plane_prepare_update_req(struct drm_plane *p,
-                                struct atmel_hlcdc_plane_update_req *req,
-                                const struct drm_display_mode *mode);
-
-int atmel_hlcdc_plane_apply_update_req(struct drm_plane *p,
-                                struct atmel_hlcdc_plane_update_req *req);
-
-int atmel_hlcdc_plane_update_with_mode(struct drm_plane *p,
-                                       struct drm_crtc *crtc,
-                                       struct drm_framebuffer *fb,
-                                       int crtc_x, int crtc_y,
-                                       unsigned int crtc_w,
-                                       unsigned int crtc_h,
-                                       uint32_t src_x, uint32_t src_y,
-                                       uint32_t src_w, uint32_t src_h,
-                                       const struct drm_display_mode *mode);
+int atmel_hlcdc_plane_prepare_disc_area(struct drm_crtc_state *c_state);
 
 void atmel_hlcdc_crtc_irq(struct drm_crtc *c);
 
diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_layer.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_layer.c
index e79bd9ba474b..377e43cea9dd 100644
--- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_layer.c
+++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_layer.c
@@ -298,7 +298,7 @@ void atmel_hlcdc_layer_irq(struct atmel_hlcdc_layer *layer)
         spin_unlock_irqrestore(&layer->lock, flags);
 }
 
-int atmel_hlcdc_layer_disable(struct atmel_hlcdc_layer *layer)
+void atmel_hlcdc_layer_disable(struct atmel_hlcdc_layer *layer)
 {
         struct atmel_hlcdc_layer_dma_channel *dma = &layer->dma;
         struct atmel_hlcdc_layer_update *upd = &layer->update;
@@ -341,8 +341,6 @@ int atmel_hlcdc_layer_disable(struct atmel_hlcdc_layer *layer)
         dma->status = ATMEL_HLCDC_LAYER_DISABLED;
 
         spin_unlock_irqrestore(&layer->lock, flags);
-
-        return 0;
 }
 
 int atmel_hlcdc_layer_update_start(struct atmel_hlcdc_layer *layer)
diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_layer.h b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_layer.h
index 27e56c0862ec..9beabc940bce 100644
--- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_layer.h
+++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_layer.h
@@ -120,6 +120,7 @@
 #define ATMEL_HLCDC_LAYER_DISCEN                BIT(11)
 #define ATMEL_HLCDC_LAYER_GA_SHIFT              16
 #define ATMEL_HLCDC_LAYER_GA_MASK               GENMASK(23, ATMEL_HLCDC_LAYER_GA_SHIFT)
+#define ATMEL_HLCDC_LAYER_GA(x)                 ((x) << ATMEL_HLCDC_LAYER_GA_SHIFT)
 
 #define ATMEL_HLCDC_LAYER_CSC_CFG(p, o)         ATMEL_HLCDC_LAYER_CFG(p, (p)->desc->layout.csc + o)
 
@@ -376,7 +377,7 @@ int atmel_hlcdc_layer_init(struct drm_device *dev,
 void atmel_hlcdc_layer_cleanup(struct drm_device *dev,
                                struct atmel_hlcdc_layer *layer);
 
-int atmel_hlcdc_layer_disable(struct atmel_hlcdc_layer *layer);
+void atmel_hlcdc_layer_disable(struct atmel_hlcdc_layer *layer);
 
 int atmel_hlcdc_layer_update_start(struct atmel_hlcdc_layer *layer);
 
diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_output.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_output.c
index c402192362c5..9c4513005310 100644
--- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_output.c
+++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_output.c
@@ -86,25 +86,22 @@ atmel_hlcdc_rgb_output_to_panel(struct atmel_hlcdc_rgb_output *output)
         return container_of(output, struct atmel_hlcdc_panel, base);
 }
 
-static void atmel_hlcdc_panel_encoder_dpms(struct drm_encoder *encoder,
-                                           int mode)
+static void atmel_hlcdc_panel_encoder_enable(struct drm_encoder *encoder)
 {
         struct atmel_hlcdc_rgb_output *rgb =
                         drm_encoder_to_atmel_hlcdc_rgb_output(encoder);
         struct atmel_hlcdc_panel *panel = atmel_hlcdc_rgb_output_to_panel(rgb);
 
-        if (mode != DRM_MODE_DPMS_ON)
-                mode = DRM_MODE_DPMS_OFF;
-
-        if (mode == rgb->dpms)
-                return;
+        drm_panel_enable(panel->panel);
+}
 
-        if (mode != DRM_MODE_DPMS_ON)
-                drm_panel_disable(panel->panel);
-        else
-                drm_panel_enable(panel->panel);
+static void atmel_hlcdc_panel_encoder_disable(struct drm_encoder *encoder)
+{
+        struct atmel_hlcdc_rgb_output *rgb =
+                        drm_encoder_to_atmel_hlcdc_rgb_output(encoder);
+        struct atmel_hlcdc_panel *panel = atmel_hlcdc_rgb_output_to_panel(rgb);
 
-        rgb->dpms = mode;
+        drm_panel_disable(panel->panel);
 }
 
 static bool
@@ -115,16 +112,6 @@ atmel_hlcdc_panel_encoder_mode_fixup(struct drm_encoder *encoder,
         return true;
 }
 
-static void atmel_hlcdc_panel_encoder_prepare(struct drm_encoder *encoder)
-{
-        atmel_hlcdc_panel_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
-}
-
-static void atmel_hlcdc_panel_encoder_commit(struct drm_encoder *encoder)
-{
-        atmel_hlcdc_panel_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
-}
-
 static void
 atmel_hlcdc_rgb_encoder_mode_set(struct drm_encoder *encoder,
                                  struct drm_display_mode *mode,
@@ -156,11 +143,10 @@ atmel_hlcdc_rgb_encoder_mode_set(struct drm_encoder *encoder,
 }
 
 static struct drm_encoder_helper_funcs atmel_hlcdc_panel_encoder_helper_funcs = {
-        .dpms = atmel_hlcdc_panel_encoder_dpms,
         .mode_fixup = atmel_hlcdc_panel_encoder_mode_fixup,
-        .prepare = atmel_hlcdc_panel_encoder_prepare,
-        .commit = atmel_hlcdc_panel_encoder_commit,
         .mode_set = atmel_hlcdc_rgb_encoder_mode_set,
+        .disable = atmel_hlcdc_panel_encoder_disable,
+        .enable = atmel_hlcdc_panel_encoder_enable,
 };
 
 static void atmel_hlcdc_rgb_encoder_destroy(struct drm_encoder *encoder)
@@ -226,10 +212,13 @@ atmel_hlcdc_panel_connector_destroy(struct drm_connector *connector)
 }
 
 static const struct drm_connector_funcs atmel_hlcdc_panel_connector_funcs = {
-        .dpms = drm_helper_connector_dpms,
+        .dpms = drm_atomic_helper_connector_dpms,
         .detect = atmel_hlcdc_panel_connector_detect,
         .fill_modes = drm_helper_probe_single_connector_modes,
         .destroy = atmel_hlcdc_panel_connector_destroy,
+        .reset = drm_atomic_helper_connector_reset,
+        .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
+        .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 };
 
 static int atmel_hlcdc_create_panel_output(struct drm_device *dev,
diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c
index c5892dcfd745..be9fa8220499 100644
--- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c
+++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c
@@ -19,6 +19,59 @@
 
 #include "atmel_hlcdc_dc.h"
 
+/**
+ * Atmel HLCDC Plane state structure.
+ *
+ * @base: DRM plane state
+ * @crtc_x: x position of the plane relative to the CRTC
+ * @crtc_y: y position of the plane relative to the CRTC
+ * @crtc_w: visible width of the plane
+ * @crtc_h: visible height of the plane
+ * @src_x: x buffer position
+ * @src_y: y buffer position
+ * @src_w: buffer width
+ * @src_h: buffer height
+ * @alpha: alpha blending of the plane
+ * @bpp: bytes per pixel deduced from pixel_format
+ * @offsets: offsets to apply to the GEM buffers
+ * @xstride: value to add to the pixel pointer between each line
+ * @pstride: value to add to the pixel pointer between each pixel
+ * @nplanes: number of planes (deduced from pixel_format)
+ */
+struct atmel_hlcdc_plane_state {
+        struct drm_plane_state base;
+        int crtc_x;
+        int crtc_y;
+        unsigned int crtc_w;
+        unsigned int crtc_h;
+        uint32_t src_x;
+        uint32_t src_y;
+        uint32_t src_w;
+        uint32_t src_h;
+
+        u8 alpha;
+
+        bool disc_updated;
+
+        int disc_x;
+        int disc_y;
+        int disc_w;
+        int disc_h;
+
+        /* These fields are private and should not be touched */
+        int bpp[ATMEL_HLCDC_MAX_PLANES];
+        unsigned int offsets[ATMEL_HLCDC_MAX_PLANES];
+        int xstride[ATMEL_HLCDC_MAX_PLANES];
+        int pstride[ATMEL_HLCDC_MAX_PLANES];
+        int nplanes;
+};
+
+static inline struct atmel_hlcdc_plane_state *
+drm_plane_state_to_atmel_hlcdc_plane_state(struct drm_plane_state *s)
+{
+        return container_of(s, struct atmel_hlcdc_plane_state, base);
+}
+
 #define SUBPIXEL_MASK                   0xffff
 
 static uint32_t rgb_formats[] = {
@@ -128,7 +181,7 @@ static int atmel_hlcdc_format_to_plane_mode(u32 format, u32 *mode)
         return 0;
 }
 
-static bool atmel_hlcdc_format_embedds_alpha(u32 format)
+static bool atmel_hlcdc_format_embeds_alpha(u32 format)
 {
         int i;
 
@@ -204,7 +257,7 @@ static u32 heo_upscaling_ycoef[] = {
 
 static void
 atmel_hlcdc_plane_update_pos_and_size(struct atmel_hlcdc_plane *plane,
-                                struct atmel_hlcdc_plane_update_req *req)
+                                      struct atmel_hlcdc_plane_state *state)
 {
         const struct atmel_hlcdc_layer_cfg_layout *layout =
                                                 &plane->layer.desc->layout;
@@ -213,69 +266,69 @@ atmel_hlcdc_plane_update_pos_and_size(struct atmel_hlcdc_plane *plane,
                 atmel_hlcdc_layer_update_cfg(&plane->layer,
                                              layout->size,
                                              0xffffffff,
-                                             (req->crtc_w - 1) |
-                                             ((req->crtc_h - 1) << 16));
+                                             (state->crtc_w - 1) |
+                                             ((state->crtc_h - 1) << 16));
 
         if (layout->memsize)
                 atmel_hlcdc_layer_update_cfg(&plane->layer,
                                              layout->memsize,
                                              0xffffffff,
-                                             (req->src_w - 1) |
-                                             ((req->src_h - 1) << 16));
+                                             (state->src_w - 1) |
+                                             ((state->src_h - 1) << 16));
 
         if (layout->pos)
                 atmel_hlcdc_layer_update_cfg(&plane->layer,
                                              layout->pos,
                                              0xffffffff,
-                                             req->crtc_x |
-                                             (req->crtc_y  << 16));
+                                             state->crtc_x |
+                                             (state->crtc_y  << 16));
 
         /* TODO: rework the rescaling part */
-        if (req->crtc_w != req->src_w || req->crtc_h != req->src_h) {
+        if (state->crtc_w != state->src_w || state->crtc_h != state->src_h) {
                 u32 factor_reg = 0;
 
-                if (req->crtc_w != req->src_w) {
+                if (state->crtc_w != state->src_w) {
                         int i;
                         u32 factor;
                         u32 *coeff_tab = heo_upscaling_xcoef;
                         u32 max_memsize;
 
-                        if (req->crtc_w < req->src_w)
+                        if (state->crtc_w < state->src_w)
                                 coeff_tab = heo_downscaling_xcoef;
                         for (i = 0; i < ARRAY_SIZE(heo_upscaling_xcoef); i++)
                                 atmel_hlcdc_layer_update_cfg(&plane->layer,
                                                              17 + i,
                                                              0xffffffff,
                                                              coeff_tab[i]);
-                        factor = ((8 * 256 * req->src_w) - (256 * 4)) /
-                                 req->crtc_w;
+                        factor = ((8 * 256 * state->src_w) - (256 * 4)) /
+                                 state->crtc_w;
                         factor++;
-                        max_memsize = ((factor * req->crtc_w) + (256 * 4)) /
+                        max_memsize = ((factor * state->crtc_w) + (256 * 4)) /
                                       2048;
-                        if (max_memsize > req->src_w)
+                        if (max_memsize > state->src_w)
                                 factor--;
                         factor_reg |= factor | 0x80000000;
                 }
 
-                if (req->crtc_h != req->src_h) {
+                if (state->crtc_h != state->src_h) {
                         int i;
                         u32 factor;
                         u32 *coeff_tab = heo_upscaling_ycoef;
                         u32 max_memsize;
 
-                        if (req->crtc_w < req->src_w)
+                        if (state->crtc_w < state->src_w)
                                 coeff_tab = heo_downscaling_ycoef;
                         for (i = 0; i < ARRAY_SIZE(heo_upscaling_ycoef); i++)
                                 atmel_hlcdc_layer_update_cfg(&plane->layer,
                                                              33 + i,
                                                              0xffffffff,
                                                              coeff_tab[i]);
-                        factor = ((8 * 256 * req->src_w) - (256 * 4)) /
-                                 req->crtc_w;
+                        factor = ((8 * 256 * state->src_w) - (256 * 4)) /
+                                 state->crtc_w;
                         factor++;
-                        max_memsize = ((factor * req->crtc_w) + (256 * 4)) /
+                        max_memsize = ((factor * state->crtc_w) + (256 * 4)) /
                                       2048;
-                        if (max_memsize > req->src_w)
+                        if (max_memsize > state->src_w)
                                 factor--;
                         factor_reg |= (factor << 16) | 0x80000000;
                 }
@@ -287,7 +340,7 @@ atmel_hlcdc_plane_update_pos_and_size(struct atmel_hlcdc_plane *plane,
 
 static void
 atmel_hlcdc_plane_update_general_settings(struct atmel_hlcdc_plane *plane,
-                                struct atmel_hlcdc_plane_update_req *req)
+                                        struct atmel_hlcdc_plane_state *state)
 {
         const struct atmel_hlcdc_layer_cfg_layout *layout =
                                                 &plane->layer.desc->layout;
@@ -297,10 +350,11 @@ atmel_hlcdc_plane_update_general_settings(struct atmel_hlcdc_plane *plane,
                 cfg |= ATMEL_HLCDC_LAYER_OVR | ATMEL_HLCDC_LAYER_ITER2BL |
                        ATMEL_HLCDC_LAYER_ITER;
 
-                if (atmel_hlcdc_format_embedds_alpha(req->fb->pixel_format))
+                if (atmel_hlcdc_format_embeds_alpha(state->base.fb->pixel_format))
                         cfg |= ATMEL_HLCDC_LAYER_LAEN;
                 else
-                        cfg |= ATMEL_HLCDC_LAYER_GAEN;
+                        cfg |= ATMEL_HLCDC_LAYER_GAEN |
+                               ATMEL_HLCDC_LAYER_GA(state->alpha);
         }
 
         atmel_hlcdc_layer_update_cfg(&plane->layer,
@@ -312,24 +366,26 @@ atmel_hlcdc_plane_update_general_settings(struct atmel_hlcdc_plane *plane,
                                      ATMEL_HLCDC_LAYER_ITER2BL |
                                      ATMEL_HLCDC_LAYER_ITER |
                                      ATMEL_HLCDC_LAYER_GAEN |
+                                     ATMEL_HLCDC_LAYER_GA_MASK |
                                      ATMEL_HLCDC_LAYER_LAEN |
                                      ATMEL_HLCDC_LAYER_OVR |
                                      ATMEL_HLCDC_LAYER_DMA, cfg);
 }
 
 static void atmel_hlcdc_plane_update_format(struct atmel_hlcdc_plane *plane,
-                                struct atmel_hlcdc_plane_update_req *req)
+                                        struct atmel_hlcdc_plane_state *state)
 {
         u32 cfg;
         int ret;
 
-        ret = atmel_hlcdc_format_to_plane_mode(req->fb->pixel_format, &cfg);
+        ret = atmel_hlcdc_format_to_plane_mode(state->base.fb->pixel_format,
+                                               &cfg);
         if (ret)
                 return;
 
-        if ((req->fb->pixel_format == DRM_FORMAT_YUV422 ||
-             req->fb->pixel_format == DRM_FORMAT_NV61) &&
-            (plane->rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270))))
+        if ((state->base.fb->pixel_format == DRM_FORMAT_YUV422 ||
+             state->base.fb->pixel_format == DRM_FORMAT_NV61) &&
+            (state->base.rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270))))
                 cfg |= ATMEL_HLCDC_YUV422ROT;
 
         atmel_hlcdc_layer_update_cfg(&plane->layer,
@@ -341,7 +397,7 @@ static void atmel_hlcdc_plane_update_format(struct atmel_hlcdc_plane *plane,
          * Rotation optimization is not working on RGB888 (rotation is still
          * working but without any optimization).
          */
-        if (req->fb->pixel_format == DRM_FORMAT_RGB888)
+        if (state->base.fb->pixel_format == DRM_FORMAT_RGB888)
                 cfg = ATMEL_HLCDC_LAYER_DMA_ROTDIS;
         else
                 cfg = 0;
@@ -352,73 +408,142 @@ static void atmel_hlcdc_plane_update_format(struct atmel_hlcdc_plane *plane,
 }
 
 static void atmel_hlcdc_plane_update_buffers(struct atmel_hlcdc_plane *plane,
-                                struct atmel_hlcdc_plane_update_req *req)
+                                        struct atmel_hlcdc_plane_state *state)
 {
         struct atmel_hlcdc_layer *layer = &plane->layer;
         const struct atmel_hlcdc_layer_cfg_layout *layout =
                                                         &layer->desc->layout;
         int i;
 
-        atmel_hlcdc_layer_update_set_fb(&plane->layer, req->fb, req->offsets);
+        atmel_hlcdc_layer_update_set_fb(&plane->layer, state->base.fb,
+                                        state->offsets);
 
-        for (i = 0; i < req->nplanes; i++) {
+        for (i = 0; i < state->nplanes; i++) {
                 if (layout->xstride[i]) {
                         atmel_hlcdc_layer_update_cfg(&plane->layer,
                                                 layout->xstride[i],
                                                 0xffffffff,
-                                                req->xstride[i]);
+                                                state->xstride[i]);
                 }
 
                 if (layout->pstride[i]) {
                         atmel_hlcdc_layer_update_cfg(&plane->layer,
                                                 layout->pstride[i],
                                                 0xffffffff,
-                                                req->pstride[i]);
+                                                state->pstride[i]);
                 }
         }
 }
 
-static int atmel_hlcdc_plane_check_update_req(struct drm_plane *p,
-                                struct atmel_hlcdc_plane_update_req *req,
-                                const struct drm_display_mode *mode)
+int
+atmel_hlcdc_plane_prepare_disc_area(struct drm_crtc_state *c_state)
 {
-        struct atmel_hlcdc_plane *plane = drm_plane_to_atmel_hlcdc_plane(p);
-        const struct atmel_hlcdc_layer_cfg_layout *layout =
-                                                &plane->layer.desc->layout;
+        int disc_x = 0, disc_y = 0, disc_w = 0, disc_h = 0;
+        const struct atmel_hlcdc_layer_cfg_layout *layout;
+        struct atmel_hlcdc_plane_state *primary_state;
+        struct drm_plane_state *primary_s;
+        struct atmel_hlcdc_plane *primary;
+        struct drm_plane *ovl;
+
+        primary = drm_plane_to_atmel_hlcdc_plane(c_state->crtc->primary);
+        layout = &primary->layer.desc->layout;
+        if (!layout->disc_pos || !layout->disc_size)
+                return 0;
+
+        primary_s = drm_atomic_get_plane_state(c_state->state,
+                                               &primary->base);
+        if (IS_ERR(primary_s))
+                return PTR_ERR(primary_s);
+
+        primary_state = drm_plane_state_to_atmel_hlcdc_plane_state(primary_s);
+
+        drm_atomic_crtc_state_for_each_plane(ovl, c_state) {
+                struct atmel_hlcdc_plane_state *ovl_state;
+                struct drm_plane_state *ovl_s;
+
+                if (ovl == c_state->crtc->primary)
+                        continue;
 
-        if (!layout->size &&
-            (mode->hdisplay != req->crtc_w ||
-             mode->vdisplay != req->crtc_h))
-                return -EINVAL;
+                ovl_s = drm_atomic_get_plane_state(c_state->state, ovl);
+                if (IS_ERR(ovl_s))
+                        return PTR_ERR(ovl_s);
 
-        if (plane->layer.desc->max_height &&
-            req->crtc_h > plane->layer.desc->max_height)
-                return -EINVAL;
+                ovl_state = drm_plane_state_to_atmel_hlcdc_plane_state(ovl_s);
 
-        if (plane->layer.desc->max_width &&
-            req->crtc_w > plane->layer.desc->max_width)
-                return -EINVAL;
+                if (!ovl_s->fb ||
+                    atmel_hlcdc_format_embeds_alpha(ovl_s->fb->pixel_format) ||
+                    ovl_state->alpha != 255)
+                        continue;
 
-        if ((req->crtc_h != req->src_h || req->crtc_w != req->src_w) &&
-            (!layout->memsize ||
-             atmel_hlcdc_format_embedds_alpha(req->fb->pixel_format)))
-                return -EINVAL;
+                /* TODO: implement a smarter hidden area detection */
+                if (ovl_state->crtc_h * ovl_state->crtc_w < disc_h * disc_w)
+                        continue;
 
-        if (req->crtc_x < 0 || req->crtc_y < 0)
-                return -EINVAL;
+                disc_x = ovl_state->crtc_x;
+                disc_y = ovl_state->crtc_y;
+                disc_h = ovl_state->crtc_h;
+                disc_w = ovl_state->crtc_w;
+        }
 
-        if (req->crtc_w + req->crtc_x > mode->hdisplay ||
-            req->crtc_h + req->crtc_y > mode->vdisplay)
-                return -EINVAL;
+        if (disc_x == primary_state->disc_x &&
+            disc_y == primary_state->disc_y &&
+            disc_w == primary_state->disc_w &&
+            disc_h == primary_state->disc_h)
+                return 0;
+
+
+        primary_state->disc_x = disc_x;
+        primary_state->disc_y = disc_y;
+        primary_state->disc_w = disc_w;
+        primary_state->disc_h = disc_h;
+        primary_state->disc_updated = true;
 
         return 0;
 }
 
-int atmel_hlcdc_plane_prepare_update_req(struct drm_plane *p,
-                                struct atmel_hlcdc_plane_update_req *req,
-                                const struct drm_display_mode *mode)
+static void
+atmel_hlcdc_plane_update_disc_area(struct atmel_hlcdc_plane *plane,
+                                   struct atmel_hlcdc_plane_state *state)
+{
+        const struct atmel_hlcdc_layer_cfg_layout *layout =
+                                                &plane->layer.desc->layout;
+        int disc_surface = 0;
+
+        if (!state->disc_updated)
+                return;
+
+        disc_surface = state->disc_h * state->disc_w;
+
+        atmel_hlcdc_layer_update_cfg(&plane->layer, layout->general_config,
+                                ATMEL_HLCDC_LAYER_DISCEN,
+                                disc_surface ? ATMEL_HLCDC_LAYER_DISCEN : 0);
+
+        if (!disc_surface)
+                return;
+
+        atmel_hlcdc_layer_update_cfg(&plane->layer,
+                                     layout->disc_pos,
+                                     0xffffffff,
+                                     state->disc_x | (state->disc_y << 16));
+
+        atmel_hlcdc_layer_update_cfg(&plane->layer,
+                                     layout->disc_size,
+                                     0xffffffff,
+                                     (state->disc_w - 1) |
+                                     ((state->disc_h - 1) << 16));
+}
+
+static int atmel_hlcdc_plane_atomic_check(struct drm_plane *p,
+                                          struct drm_plane_state *s)
 {
         struct atmel_hlcdc_plane *plane = drm_plane_to_atmel_hlcdc_plane(p);
+        struct atmel_hlcdc_plane_state *state =
+                                drm_plane_state_to_atmel_hlcdc_plane_state(s);
+        const struct atmel_hlcdc_layer_cfg_layout *layout =
+                                                &plane->layer.desc->layout;
+        struct drm_framebuffer *fb = state->base.fb;
+        const struct drm_display_mode *mode;
+        struct drm_crtc_state *crtc_state;
         unsigned int patched_crtc_w;
         unsigned int patched_crtc_h;
         unsigned int patched_src_w;
@@ -430,196 +555,196 @@ int atmel_hlcdc_plane_prepare_update_req(struct drm_plane *p,
         int vsub = 1;
         int i;
 
-        if ((req->src_x | req->src_y | req->src_w | req->src_h) &
+        if (!state->base.crtc || !fb)
+                return 0;
+
+        crtc_state = s->state->crtc_states[drm_crtc_index(s->crtc)];
+        mode = &crtc_state->adjusted_mode;
+
+        state->src_x = s->src_x;
+        state->src_y = s->src_y;
+        state->src_h = s->src_h;
+        state->src_w = s->src_w;
+        state->crtc_x = s->crtc_x;
+        state->crtc_y = s->crtc_y;
+        state->crtc_h = s->crtc_h;
+        state->crtc_w = s->crtc_w;
+        if ((state->src_x | state->src_y | state->src_w | state->src_h) &
             SUBPIXEL_MASK)
                 return -EINVAL;
 
-        req->src_x >>= 16;
-        req->src_y >>= 16;
-        req->src_w >>= 16;
-        req->src_h >>= 16;
+        state->src_x >>= 16;
+        state->src_y >>= 16;
+        state->src_w >>= 16;
+        state->src_h >>= 16;
 
-        req->nplanes = drm_format_num_planes(req->fb->pixel_format);
-        if (req->nplanes > ATMEL_HLCDC_MAX_PLANES)
+        state->nplanes = drm_format_num_planes(fb->pixel_format);
+        if (state->nplanes > ATMEL_HLCDC_MAX_PLANES)
                 return -EINVAL;
 
         /*
          * Swap width and size in case of 90 or 270 degrees rotation
          */
-        if (plane->rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270))) {
-                tmp = req->crtc_w;
-                req->crtc_w = req->crtc_h;
-                req->crtc_h = tmp;
-                tmp = req->src_w;
-                req->src_w = req->src_h;
-                req->src_h = tmp;
+        if (state->base.rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270))) {
+                tmp = state->crtc_w;
+                state->crtc_w = state->crtc_h;
+                state->crtc_h = tmp;
+                tmp = state->src_w;
+                state->src_w = state->src_h;
+                state->src_h = tmp;
         }
 
-        if (req->crtc_x + req->crtc_w > mode->hdisplay)
-                patched_crtc_w = mode->hdisplay - req->crtc_x;
+        if (state->crtc_x + state->crtc_w > mode->hdisplay)
+                patched_crtc_w = mode->hdisplay - state->crtc_x;
         else
-                patched_crtc_w = req->crtc_w;
+                patched_crtc_w = state->crtc_w;
 
-        if (req->crtc_x < 0) {
-                patched_crtc_w += req->crtc_x;
-                x_offset = -req->crtc_x;
-                req->crtc_x = 0;
+        if (state->crtc_x < 0) {
+                patched_crtc_w += state->crtc_x;
+                x_offset = -state->crtc_x;
+                state->crtc_x = 0;
         }
 
-        if (req->crtc_y + req->crtc_h > mode->vdisplay)
-                patched_crtc_h = mode->vdisplay - req->crtc_y;
+        if (state->crtc_y + state->crtc_h > mode->vdisplay)
+                patched_crtc_h = mode->vdisplay - state->crtc_y;
         else
-                patched_crtc_h = req->crtc_h;
+                patched_crtc_h = state->crtc_h;
 
-        if (req->crtc_y < 0) {
-                patched_crtc_h += req->crtc_y;
-                y_offset = -req->crtc_y;
-                req->crtc_y = 0;
+        if (state->crtc_y < 0) {
+                patched_crtc_h += state->crtc_y;
+                y_offset = -state->crtc_y;
+                state->crtc_y = 0;
         }
 
-        patched_src_w = DIV_ROUND_CLOSEST(patched_crtc_w * req->src_w,
-                                          req->crtc_w);
-        patched_src_h = DIV_ROUND_CLOSEST(patched_crtc_h * req->src_h,
-                                          req->crtc_h);
+        patched_src_w = DIV_ROUND_CLOSEST(patched_crtc_w * state->src_w,
+                                          state->crtc_w);
+        patched_src_h = DIV_ROUND_CLOSEST(patched_crtc_h * state->src_h,
+                                          state->crtc_h);
 
-        hsub = drm_format_horz_chroma_subsampling(req->fb->pixel_format);
-        vsub = drm_format_vert_chroma_subsampling(req->fb->pixel_format);
+        hsub = drm_format_horz_chroma_subsampling(fb->pixel_format);
+        vsub = drm_format_vert_chroma_subsampling(fb->pixel_format);
 
-        for (i = 0; i < req->nplanes; i++) {
+        for (i = 0; i < state->nplanes; i++) {
                 unsigned int offset = 0;
                 int xdiv = i ? hsub : 1;
                 int ydiv = i ? vsub : 1;
 
-                req->bpp[i] = drm_format_plane_cpp(req->fb->pixel_format, i);
-                if (!req->bpp[i])
+                state->bpp[i] = drm_format_plane_cpp(fb->pixel_format, i);
+                if (!state->bpp[i])
                         return -EINVAL;
 
-                switch (plane->rotation & 0xf) {
+                switch (state->base.rotation & 0xf) {
                 case BIT(DRM_ROTATE_90):
-                        offset = ((y_offset + req->src_y + patched_src_w - 1) /
-                                  ydiv) * req->fb->pitches[i];
-                        offset += ((x_offset + req->src_x) / xdiv) *
-                                  req->bpp[i];
-                        req->xstride[i] = ((patched_src_w - 1) / ydiv) *
-                                          req->fb->pitches[i];
-                        req->pstride[i] = -req->fb->pitches[i] - req->bpp[i];
+                        offset = ((y_offset + state->src_y + patched_src_w - 1) /
+                                  ydiv) * fb->pitches[i];
+                        offset += ((x_offset + state->src_x) / xdiv) *
+                                  state->bpp[i];
+                        state->xstride[i] = ((patched_src_w - 1) / ydiv) *
+                                          fb->pitches[i];
+                        state->pstride[i] = -fb->pitches[i] - state->bpp[i];
                         break;
                 case BIT(DRM_ROTATE_180):
-                        offset = ((y_offset + req->src_y + patched_src_h - 1) /
-                                  ydiv) * req->fb->pitches[i];
-                        offset += ((x_offset + req->src_x + patched_src_w - 1) /
-                                   xdiv) * req->bpp[i];
-                        req->xstride[i] = ((((patched_src_w - 1) / xdiv) - 1) *
-                                           req->bpp[i]) - req->fb->pitches[i];
-                        req->pstride[i] = -2 * req->bpp[i];
+                        offset = ((y_offset + state->src_y + patched_src_h - 1) /
+                                  ydiv) * fb->pitches[i];
+                        offset += ((x_offset + state->src_x + patched_src_w - 1) /
+                                   xdiv) * state->bpp[i];
+                        state->xstride[i] = ((((patched_src_w - 1) / xdiv) - 1) *
+                                           state->bpp[i]) - fb->pitches[i];
+                        state->pstride[i] = -2 * state->bpp[i];
                         break;
                 case BIT(DRM_ROTATE_270):
-                        offset = ((y_offset + req->src_y) / ydiv) *
-                                 req->fb->pitches[i];
-                        offset += ((x_offset + req->src_x + patched_src_h - 1) /
-                                   xdiv) * req->bpp[i];
-                        req->xstride[i] = -(((patched_src_w - 1) / ydiv) *
-                                            req->fb->pitches[i]) -
-                                          (2 * req->bpp[i]);
-                        req->pstride[i] = req->fb->pitches[i] - req->bpp[i];
+                        offset = ((y_offset + state->src_y) / ydiv) *
+                                 fb->pitches[i];
+                        offset += ((x_offset + state->src_x + patched_src_h - 1) /
+                                   xdiv) * state->bpp[i];
+                        state->xstride[i] = -(((patched_src_w - 1) / ydiv) *
+                                            fb->pitches[i]) -
+                                          (2 * state->bpp[i]);
+                        state->pstride[i] = fb->pitches[i] - state->bpp[i];
                         break;
                 case BIT(DRM_ROTATE_0):
                 default:
-                        offset = ((y_offset + req->src_y) / ydiv) *
-                                 req->fb->pitches[i];
-                        offset += ((x_offset + req->src_x) / xdiv) *
-                                  req->bpp[i];
-                        req->xstride[i] = req->fb->pitches[i] -
+                        offset = ((y_offset + state->src_y) / ydiv) *
+                                 fb->pitches[i];
+                        offset += ((x_offset + state->src_x) / xdiv) *
+                                  state->bpp[i];
+                        state->xstride[i] = fb->pitches[i] -
                                           ((patched_src_w / xdiv) *
-                                           req->bpp[i]);
-                        req->pstride[i] = 0;
+                                           state->bpp[i]);
+                        state->pstride[i] = 0;
                         break;
                 }
 
-                req->offsets[i] = offset + req->fb->offsets[i];
+                state->offsets[i] = offset + fb->offsets[i];
         }
 
-        req->src_w = patched_src_w;
-        req->src_h = patched_src_h;
-        req->crtc_w = patched_crtc_w;
-        req->crtc_h = patched_crtc_h;
+        state->src_w = patched_src_w;
+        state->src_h = patched_src_h;
+        state->crtc_w = patched_crtc_w;
+        state->crtc_h = patched_crtc_h;
 
-        return atmel_hlcdc_plane_check_update_req(p, req, mode);
-}
+        if (!layout->size &&
+            (mode->hdisplay != state->crtc_w ||
+             mode->vdisplay != state->crtc_h))
+                return -EINVAL;
 
-int atmel_hlcdc_plane_apply_update_req(struct drm_plane *p,
-                                struct atmel_hlcdc_plane_update_req *req)
-{
-        struct atmel_hlcdc_plane *plane = drm_plane_to_atmel_hlcdc_plane(p);
-        int ret;
+        if (plane->layer.desc->max_height &&
+            state->crtc_h > plane->layer.desc->max_height)
+                return -EINVAL;
 
-        ret = atmel_hlcdc_layer_update_start(&plane->layer);
-        if (ret)
-                return ret;
+        if (plane->layer.desc->max_width &&
+            state->crtc_w > plane->layer.desc->max_width)
+                return -EINVAL;
 
-        atmel_hlcdc_plane_update_pos_and_size(plane, req);
-        atmel_hlcdc_plane_update_general_settings(plane, req);
-        atmel_hlcdc_plane_update_format(plane, req);
-        atmel_hlcdc_plane_update_buffers(plane, req);
+        if ((state->crtc_h != state->src_h || state->crtc_w != state->src_w) &&
+            (!layout->memsize ||
+             atmel_hlcdc_format_embeds_alpha(state->base.fb->pixel_format)))
+                return -EINVAL;
 
-        atmel_hlcdc_layer_update_commit(&plane->layer);
+        if (state->crtc_x < 0 || state->crtc_y < 0)
+                return -EINVAL;
+
+        if (state->crtc_w + state->crtc_x > mode->hdisplay ||
+            state->crtc_h + state->crtc_y > mode->vdisplay)
+                return -EINVAL;
 
         return 0;
 }
 
-int atmel_hlcdc_plane_update_with_mode(struct drm_plane *p,
-                                       struct drm_crtc *crtc,
-                                       struct drm_framebuffer *fb,
-                                       int crtc_x, int crtc_y,
-                                       unsigned int crtc_w,
-                                       unsigned int crtc_h,
-                                       uint32_t src_x, uint32_t src_y,
-                                       uint32_t src_w, uint32_t src_h,
-                                       const struct drm_display_mode *mode)
+static int atmel_hlcdc_plane_prepare_fb(struct drm_plane *p,
+                                        struct drm_framebuffer *fb,
+                                        const struct drm_plane_state *new_state)
 {
         struct atmel_hlcdc_plane *plane = drm_plane_to_atmel_hlcdc_plane(p);
-        struct atmel_hlcdc_plane_update_req req;
-        int ret = 0;
-
-        memset(&req, 0, sizeof(req));
-        req.crtc_x = crtc_x;
-        req.crtc_y = crtc_y;
-        req.crtc_w = crtc_w;
-        req.crtc_h = crtc_h;
-        req.src_x = src_x;
-        req.src_y = src_y;
-        req.src_w = src_w;
-        req.src_h = src_h;
-        req.fb = fb;
-
-        ret = atmel_hlcdc_plane_prepare_update_req(&plane->base, &req, mode);
-        if (ret)
-                return ret;
 
-        if (!req.crtc_h || !req.crtc_w)
-                return atmel_hlcdc_layer_disable(&plane->layer);
-
-        return atmel_hlcdc_plane_apply_update_req(&plane->base, &req);
+        return atmel_hlcdc_layer_update_start(&plane->layer);
 }
 
-static int atmel_hlcdc_plane_update(struct drm_plane *p,
-                                    struct drm_crtc *crtc,
-                                    struct drm_framebuffer *fb,
-                                    int crtc_x, int crtc_y,
-                                    unsigned int crtc_w, unsigned int crtc_h,
-                                    uint32_t src_x, uint32_t src_y,
-                                    uint32_t src_w, uint32_t src_h)
+static void atmel_hlcdc_plane_atomic_update(struct drm_plane *p,
+                                            struct drm_plane_state *old_s)
 {
-        return atmel_hlcdc_plane_update_with_mode(p, crtc, fb, crtc_x, crtc_y,
-                                                  crtc_w, crtc_h, src_x, src_y,
-                                                  src_w, src_h, &crtc->hwmode);
+        struct atmel_hlcdc_plane *plane = drm_plane_to_atmel_hlcdc_plane(p);
+        struct atmel_hlcdc_plane_state *state =
+                        drm_plane_state_to_atmel_hlcdc_plane_state(p->state);
+
+        if (!p->state->crtc || !p->state->fb)
+                return;
+
+        atmel_hlcdc_plane_update_pos_and_size(plane, state);
+        atmel_hlcdc_plane_update_general_settings(plane, state);
+        atmel_hlcdc_plane_update_format(plane, state);
+        atmel_hlcdc_plane_update_buffers(plane, state);
+        atmel_hlcdc_plane_update_disc_area(plane, state);
+
+        atmel_hlcdc_layer_update_commit(&plane->layer);
 }
 
-static int atmel_hlcdc_plane_disable(struct drm_plane *p)
+static void atmel_hlcdc_plane_atomic_disable(struct drm_plane *p,
+                                             struct drm_plane_state *old_state)
 {
         struct atmel_hlcdc_plane *plane = drm_plane_to_atmel_hlcdc_plane(p);
 
-        return atmel_hlcdc_layer_disable(&plane->layer);
+        atmel_hlcdc_layer_disable(&plane->layer);
 }
 
 static void atmel_hlcdc_plane_destroy(struct drm_plane *p)
@@ -635,38 +760,36 @@ static void atmel_hlcdc_plane_destroy(struct drm_plane *p)
         devm_kfree(p->dev->dev, plane);
 }
 
-static int atmel_hlcdc_plane_set_alpha(struct atmel_hlcdc_plane *plane,
-                                       u8 alpha)
+static int atmel_hlcdc_plane_atomic_set_property(struct drm_plane *p,
+                                                 struct drm_plane_state *s,
+                                                 struct drm_property *property,
+                                                 uint64_t val)
 {
-        atmel_hlcdc_layer_update_start(&plane->layer);
-        atmel_hlcdc_layer_update_cfg(&plane->layer,
-                                     plane->layer.desc->layout.general_config,
-                                     ATMEL_HLCDC_LAYER_GA_MASK,
-                                     alpha << ATMEL_HLCDC_LAYER_GA_SHIFT);
-        atmel_hlcdc_layer_update_commit(&plane->layer);
-
-        return 0;
-}
+        struct atmel_hlcdc_plane *plane = drm_plane_to_atmel_hlcdc_plane(p);
+        struct atmel_hlcdc_plane_properties *props = plane->properties;
+        struct atmel_hlcdc_plane_state *state =
+                        drm_plane_state_to_atmel_hlcdc_plane_state(s);
 
-static int atmel_hlcdc_plane_set_rotation(struct atmel_hlcdc_plane *plane,
-                                          unsigned int rotation)
-{
-        plane->rotation = rotation;
+        if (property == props->alpha)
+                state->alpha = val;
+        else
+                return -EINVAL;
 
         return 0;
 }
 
-static int atmel_hlcdc_plane_set_property(struct drm_plane *p,
-                                          struct drm_property *property,
-                                          uint64_t value)
+static int atmel_hlcdc_plane_atomic_get_property(struct drm_plane *p,
+                                        const struct drm_plane_state *s,
+                                        struct drm_property *property,
+                                        uint64_t *val)
 {
         struct atmel_hlcdc_plane *plane = drm_plane_to_atmel_hlcdc_plane(p);
         struct atmel_hlcdc_plane_properties *props = plane->properties;
+        const struct atmel_hlcdc_plane_state *state =
+                container_of(s, const struct atmel_hlcdc_plane_state, base);
 
         if (property == props->alpha)
-                atmel_hlcdc_plane_set_alpha(plane, value);
-        else if (property == props->rotation)
-                atmel_hlcdc_plane_set_rotation(plane, value);
+                *val = state->alpha;
         else
                 return -EINVAL;
 
@@ -694,8 +817,8 @@ static void atmel_hlcdc_plane_init_properties(struct atmel_hlcdc_plane *plane,
 
         if (desc->layout.xstride && desc->layout.pstride)
                 drm_object_attach_property(&plane->base.base,
-                                           props->rotation,
-                                           BIT(DRM_ROTATE_0));
+                                plane->base.dev->mode_config.rotation_property,
+                                BIT(DRM_ROTATE_0));
 
         if (desc->layout.csc) {
                 /*
@@ -717,11 +840,76 @@ static void atmel_hlcdc_plane_init_properties(struct atmel_hlcdc_plane *plane,
         }
 }
 
+static struct drm_plane_helper_funcs atmel_hlcdc_layer_plane_helper_funcs = {
+        .prepare_fb = atmel_hlcdc_plane_prepare_fb,
+        .atomic_check = atmel_hlcdc_plane_atomic_check,
+        .atomic_update = atmel_hlcdc_plane_atomic_update,
+        .atomic_disable = atmel_hlcdc_plane_atomic_disable,
+};
+
+static void atmel_hlcdc_plane_reset(struct drm_plane *p)
+{
+        struct atmel_hlcdc_plane_state *state;
+
+        if (p->state) {
+                state = drm_plane_state_to_atmel_hlcdc_plane_state(p->state);
+
+                if (state->base.fb)
+                        drm_framebuffer_unreference(state->base.fb);
+
+                kfree(state);
+                p->state = NULL;
+        }
+
+        state = kzalloc(sizeof(*state), GFP_KERNEL);
+        if (state) {
+                state->alpha = 255;
+                p->state = &state->base;
+                p->state->plane = p;
+        }
+}
+
+static struct drm_plane_state *
+atmel_hlcdc_plane_atomic_duplicate_state(struct drm_plane *p)
+{
+        struct atmel_hlcdc_plane_state *state =
+                        drm_plane_state_to_atmel_hlcdc_plane_state(p->state);
+        struct atmel_hlcdc_plane_state *copy;
+
+        copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
+        if (!copy)
+                return NULL;
+
+        copy->disc_updated = false;
+
+        if (copy->base.fb)
+                drm_framebuffer_reference(copy->base.fb);
+
+        return &copy->base;
+}
+
+static void atmel_hlcdc_plane_atomic_destroy_state(struct drm_plane *plane,
+                                                   struct drm_plane_state *s)
+{
+        struct atmel_hlcdc_plane_state *state =
+                        drm_plane_state_to_atmel_hlcdc_plane_state(s);
+
+        if (s->fb)
+                drm_framebuffer_unreference(s->fb);
+
+        kfree(state);
+}
+
 static struct drm_plane_funcs layer_plane_funcs = {
-        .update_plane = atmel_hlcdc_plane_update,
-        .disable_plane = atmel_hlcdc_plane_disable,
-        .set_property = atmel_hlcdc_plane_set_property,
+        .update_plane = drm_atomic_helper_update_plane,
+        .disable_plane = drm_atomic_helper_disable_plane,
+        .set_property = drm_atomic_helper_plane_set_property,
         .destroy = atmel_hlcdc_plane_destroy,
+        .reset = atmel_hlcdc_plane_reset,
+        .atomic_duplicate_state = atmel_hlcdc_plane_atomic_duplicate_state,
+        .atomic_destroy_state = atmel_hlcdc_plane_atomic_destroy_state,
+        .atomic_set_property = atmel_hlcdc_plane_atomic_set_property,
+        .atomic_get_property = atmel_hlcdc_plane_atomic_get_property,
 };
 
 static struct atmel_hlcdc_plane *
@@ -755,6 +943,9 @@ atmel_hlcdc_plane_create(struct drm_device *dev,
         if (ret)
                 return ERR_PTR(ret);
 
+        drm_plane_helper_add(&plane->base,
+                             &atmel_hlcdc_layer_plane_helper_funcs);
+
         /* Set default property values*/
         atmel_hlcdc_plane_init_properties(plane, desc, props);
 
@@ -774,12 +965,13 @@ atmel_hlcdc_plane_create_properties(struct drm_device *dev)
         if (!props->alpha)
                 return ERR_PTR(-ENOMEM);
 
-        props->rotation = drm_mode_create_rotation_property(dev,
-                                                BIT(DRM_ROTATE_0) |
-                                                BIT(DRM_ROTATE_90) |
-                                                BIT(DRM_ROTATE_180) |
-                                                BIT(DRM_ROTATE_270));
-        if (!props->rotation)
+        dev->mode_config.rotation_property =
+                        drm_mode_create_rotation_property(dev,
+                                                          BIT(DRM_ROTATE_0) |
+                                                          BIT(DRM_ROTATE_90) |
+                                                          BIT(DRM_ROTATE_180) |
+                                                          BIT(DRM_ROTATE_270));
+        if (!dev->mode_config.rotation_property)
                 return ERR_PTR(-ENOMEM);
 
         return props;
diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index c2e9c5283136..321e098ddf04 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -92,7 +92,7 @@ drm_atomic_state_alloc(struct drm_device *dev)
 
         state->dev = dev;
 
-        DRM_DEBUG_KMS("Allocate atomic state %p\n", state);
+        DRM_DEBUG_ATOMIC("Allocate atomic state %p\n", state);
 
         return state;
 fail:
@@ -122,7 +122,7 @@ void drm_atomic_state_clear(struct drm_atomic_state *state)
         struct drm_mode_config *config = &dev->mode_config;
         int i;
 
-        DRM_DEBUG_KMS("Clearing atomic state %p\n", state);
+        DRM_DEBUG_ATOMIC("Clearing atomic state %p\n", state);
 
         for (i = 0; i < state->num_connector; i++) {
                 struct drm_connector *connector = state->connectors[i];
@@ -172,7 +172,7 @@ void drm_atomic_state_free(struct drm_atomic_state *state)
 {
         drm_atomic_state_clear(state);
 
-        DRM_DEBUG_KMS("Freeing atomic state %p\n", state);
+        DRM_DEBUG_ATOMIC("Freeing atomic state %p\n", state);
 
         kfree_state(state);
 }
@@ -217,8 +217,8 @@ drm_atomic_get_crtc_state(struct drm_atomic_state *state,
         state->crtcs[index] = crtc;
         crtc_state->state = state;
 
-        DRM_DEBUG_KMS("Added [CRTC:%d] %p state to %p\n",
-                      crtc->base.id, crtc_state, state);
+        DRM_DEBUG_ATOMIC("Added [CRTC:%d] %p state to %p\n",
+                         crtc->base.id, crtc_state, state);
 
         return crtc_state;
 }
@@ -293,8 +293,8 @@ static int drm_atomic_crtc_check(struct drm_crtc *crtc,
          */
 
         if (state->active && !state->enable) {
-                DRM_DEBUG_KMS("[CRTC:%d] active without enabled\n",
-                              crtc->base.id);
+                DRM_DEBUG_ATOMIC("[CRTC:%d] active without enabled\n",
+                                 crtc->base.id);
                 return -EINVAL;
         }
 
@@ -340,8 +340,8 @@ drm_atomic_get_plane_state(struct drm_atomic_state *state,
         state->planes[index] = plane;
         plane_state->state = state;
 
-        DRM_DEBUG_KMS("Added [PLANE:%d] %p state to %p\n",
-                      plane->base.id, plane_state, state);
+        DRM_DEBUG_ATOMIC("Added [PLANE:%d] %p state to %p\n",
+                         plane->base.id, plane_state, state);
 
         if (plane_state->crtc) {
                 struct drm_crtc_state *crtc_state;
@@ -477,10 +477,10 @@ static int drm_atomic_plane_check(struct drm_plane *plane,
 
         /* either *both* CRTC and FB must be set, or neither */
         if (WARN_ON(state->crtc && !state->fb)) {
-                DRM_DEBUG_KMS("CRTC set but no FB\n");
+                DRM_DEBUG_ATOMIC("CRTC set but no FB\n");
                 return -EINVAL;
         } else if (WARN_ON(state->fb && !state->crtc)) {
-                DRM_DEBUG_KMS("FB set but no CRTC\n");
+                DRM_DEBUG_ATOMIC("FB set but no CRTC\n");
                 return -EINVAL;
         }
 
@@ -490,7 +490,7 @@ static int drm_atomic_plane_check(struct drm_plane *plane,
 
         /* Check whether this plane is usable on this CRTC */
         if (!(plane->possible_crtcs & drm_crtc_mask(state->crtc))) {
-                DRM_DEBUG_KMS("Invalid crtc for plane\n");
+                DRM_DEBUG_ATOMIC("Invalid crtc for plane\n");
                 return -EINVAL;
         }
 
@@ -499,8 +499,8 @@ static int drm_atomic_plane_check(struct drm_plane *plane,
                 if (state->fb->pixel_format == plane->format_types[i])
                         break;
         if (i == plane->format_count) {
-                DRM_DEBUG_KMS("Invalid pixel format %s\n",
-                              drm_get_format_name(state->fb->pixel_format));
+                DRM_DEBUG_ATOMIC("Invalid pixel format %s\n",
+                                 drm_get_format_name(state->fb->pixel_format));
                 return -EINVAL;
         }
 
@@ -509,9 +509,9 @@ static int drm_atomic_plane_check(struct drm_plane *plane,
             state->crtc_x > INT_MAX - (int32_t) state->crtc_w ||
             state->crtc_h > INT_MAX ||
             state->crtc_y > INT_MAX - (int32_t) state->crtc_h) {
-                DRM_DEBUG_KMS("Invalid CRTC coordinates %ux%u+%d+%d\n",
-                              state->crtc_w, state->crtc_h,
-                              state->crtc_x, state->crtc_y);
+                DRM_DEBUG_ATOMIC("Invalid CRTC coordinates %ux%u+%d+%d\n",
+                                 state->crtc_w, state->crtc_h,
+                                 state->crtc_x, state->crtc_y);
                 return -ERANGE;
         }
 
@@ -523,12 +523,12 @@ static int drm_atomic_plane_check(struct drm_plane *plane,
             state->src_x > fb_width - state->src_w ||
             state->src_h > fb_height ||
             state->src_y > fb_height - state->src_h) {
-                DRM_DEBUG_KMS("Invalid source coordinates "
-                              "%u.%06ux%u.%06u+%u.%06u+%u.%06u\n",
-                              state->src_w >> 16, ((state->src_w & 0xffff) * 15625) >> 10,
-                              state->src_h >> 16, ((state->src_h & 0xffff) * 15625) >> 10,
-                              state->src_x >> 16, ((state->src_x & 0xffff) * 15625) >> 10,
-                              state->src_y >> 16, ((state->src_y & 0xffff) * 15625) >> 10);
+                DRM_DEBUG_ATOMIC("Invalid source coordinates "
+                                 "%u.%06ux%u.%06u+%u.%06u+%u.%06u\n",
+                                 state->src_w >> 16, ((state->src_w & 0xffff) * 15625) >> 10,
+                                 state->src_h >> 16, ((state->src_h & 0xffff) * 15625) >> 10,
+                                 state->src_x >> 16, ((state->src_x & 0xffff) * 15625) >> 10,
+                                 state->src_y >> 16, ((state->src_y & 0xffff) * 15625) >> 10);
                 return -ENOSPC;
         }
 
@@ -575,7 +575,7 @@ drm_atomic_get_connector_state(struct drm_atomic_state *state,
          * at most the array is a bit too large.
          */
         if (index >= state->num_connector) {
-                DRM_DEBUG_KMS("Hot-added connector would overflow state array, restarting\n");
+                DRM_DEBUG_ATOMIC("Hot-added connector would overflow state array, restarting\n");
                 return ERR_PTR(-EAGAIN);
         }
 
@@ -590,8 +590,8 @@ drm_atomic_get_connector_state(struct drm_atomic_state *state,
         state->connectors[index] = connector;
         connector_state->state = state;
 
-        DRM_DEBUG_KMS("Added [CONNECTOR:%d] %p state to %p\n",
-                      connector->base.id, connector_state, state);
+        DRM_DEBUG_ATOMIC("Added [CONNECTOR:%d] %p state to %p\n",
+                         connector->base.id, connector_state, state);
 
         if (connector_state->crtc) {
                 struct drm_crtc_state *crtc_state;
@@ -752,10 +752,11 @@ drm_atomic_set_crtc_for_plane(struct drm_plane_state *plane_state,
         }
 
         if (crtc)
-                DRM_DEBUG_KMS("Link plane state %p to [CRTC:%d]\n",
-                              plane_state, crtc->base.id);
+                DRM_DEBUG_ATOMIC("Link plane state %p to [CRTC:%d]\n",
+                                 plane_state, crtc->base.id);
         else
-                DRM_DEBUG_KMS("Link plane state %p to [NOCRTC]\n", plane_state);
+                DRM_DEBUG_ATOMIC("Link plane state %p to [NOCRTC]\n",
+                                 plane_state);
 
         return 0;
 }
@@ -782,10 +783,11 @@ drm_atomic_set_fb_for_plane(struct drm_plane_state *plane_state,
         plane_state->fb = fb;
 
         if (fb)
-                DRM_DEBUG_KMS("Set [FB:%d] for plane state %p\n",
-                              fb->base.id, plane_state);
+                DRM_DEBUG_ATOMIC("Set [FB:%d] for plane state %p\n",
+                                 fb->base.id, plane_state);
         else
-                DRM_DEBUG_KMS("Set [NOFB] for plane state %p\n", plane_state);
+                DRM_DEBUG_ATOMIC("Set [NOFB] for plane state %p\n",
+                                 plane_state);
 }
 EXPORT_SYMBOL(drm_atomic_set_fb_for_plane);
 
@@ -818,11 +820,11 @@ drm_atomic_set_crtc_for_connector(struct drm_connector_state *conn_state,
         conn_state->crtc = crtc;
 
         if (crtc)
-                DRM_DEBUG_KMS("Link connector state %p to [CRTC:%d]\n",
-                              conn_state, crtc->base.id);
+                DRM_DEBUG_ATOMIC("Link connector state %p to [CRTC:%d]\n",
+                                 conn_state, crtc->base.id);
         else
-                DRM_DEBUG_KMS("Link connector state %p to [NOCRTC]\n",
-                              conn_state);
+                DRM_DEBUG_ATOMIC("Link connector state %p to [NOCRTC]\n",
+                                 conn_state);
 
         return 0;
 }
@@ -858,8 +860,8 @@ drm_atomic_add_affected_connectors(struct drm_atomic_state *state,
         if (ret)
                 return ret;
 
-        DRM_DEBUG_KMS("Adding all current connectors for [CRTC:%d] to %p\n",
-                      crtc->base.id, state);
+        DRM_DEBUG_ATOMIC("Adding all current connectors for [CRTC:%d] to %p\n",
+                         crtc->base.id, state);
 
         /*
          * Changed connectors are already in @state, so only need to look at the
@@ -901,8 +903,8 @@ drm_atomic_connectors_for_crtc(struct drm_atomic_state *state,
                         num_connected_connectors++;
         }
 
-        DRM_DEBUG_KMS("State %p has %i connectors for [CRTC:%d]\n",
-                      state, num_connected_connectors, crtc->base.id);
+        DRM_DEBUG_ATOMIC("State %p has %i connectors for [CRTC:%d]\n",
+                         state, num_connected_connectors, crtc->base.id);
 
         return num_connected_connectors;
 }
@@ -953,7 +955,7 @@ int drm_atomic_check_only(struct drm_atomic_state *state)
         int ncrtcs = config->num_crtc;
         int i, ret = 0;
 
-        DRM_DEBUG_KMS("checking %p\n", state);
+        DRM_DEBUG_ATOMIC("checking %p\n", state);
 
         for (i = 0; i < nplanes; i++) {
                 struct drm_plane *plane = state->planes[i];
@@ -963,8 +965,8 @@ int drm_atomic_check_only(struct drm_atomic_state *state)
 
                 ret = drm_atomic_plane_check(plane, state->plane_states[i]);
                 if (ret) {
-                        DRM_DEBUG_KMS("[PLANE:%d] atomic core check failed\n",
-                                      plane->base.id);
+                        DRM_DEBUG_ATOMIC("[PLANE:%d] atomic core check failed\n",
+                                         plane->base.id);
                         return ret;
                 }
         }
@@ -977,8 +979,8 @@ int drm_atomic_check_only(struct drm_atomic_state *state)
 
                 ret = drm_atomic_crtc_check(crtc, state->crtc_states[i]);
                 if (ret) {
-                        DRM_DEBUG_KMS("[CRTC:%d] atomic core check failed\n",
-                                      crtc->base.id);
+                        DRM_DEBUG_ATOMIC("[CRTC:%d] atomic core check failed\n",
+                                         crtc->base.id);
                         return ret;
                 }
         }
@@ -996,8 +998,8 @@ int drm_atomic_check_only(struct drm_atomic_state *state)
 
                         if (crtc_state->mode_changed ||
                             crtc_state->active_changed) {
-                                DRM_DEBUG_KMS("[CRTC:%d] requires full modeset\n",
-                                              crtc->base.id);
+                                DRM_DEBUG_ATOMIC("[CRTC:%d] requires full modeset\n",
+                                                 crtc->base.id);
                                 return -EINVAL;
                         }
                 }
@@ -1032,7 +1034,7 @@ int drm_atomic_commit(struct drm_atomic_state *state)
         if (ret)
                 return ret;
 
-        DRM_DEBUG_KMS("commiting %p\n", state);
+        DRM_DEBUG_ATOMIC("commiting %p\n", state);
 
         return config->funcs->atomic_commit(state->dev, state, false);
 }
@@ -1063,7 +1065,7 @@ int drm_atomic_async_commit(struct drm_atomic_state *state)
         if (ret)
                 return ret;
 
-        DRM_DEBUG_KMS("commiting %p asynchronously\n", state);
+        DRM_DEBUG_ATOMIC("commiting %p asynchronously\n", state);
 
         return config->funcs->atomic_commit(state->dev, state, true);
 }
diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c
index 7e3a52b97c7d..7715c40d4e74 100644
--- a/drivers/gpu/drm/drm_atomic_helper.c
+++ b/drivers/gpu/drm/drm_atomic_helper.c
@@ -116,9 +116,9 @@ steal_encoder(struct drm_atomic_state *state,
          */
         WARN_ON(!drm_modeset_is_locked(&config->connection_mutex));
 
-        DRM_DEBUG_KMS("[ENCODER:%d:%s] in use on [CRTC:%d], stealing it\n",
-                      encoder->base.id, encoder->name,
-                      encoder_crtc->base.id);
+        DRM_DEBUG_ATOMIC("[ENCODER:%d:%s] in use on [CRTC:%d], stealing it\n",
+                         encoder->base.id, encoder->name,
+                         encoder_crtc->base.id);
 
         crtc_state = drm_atomic_get_crtc_state(state, encoder_crtc);
         if (IS_ERR(crtc_state))
@@ -130,9 +130,9 @@ steal_encoder(struct drm_atomic_state *state,
                 if (connector->state->best_encoder != encoder)
                         continue;
 
-                DRM_DEBUG_KMS("Stealing encoder from [CONNECTOR:%d:%s]\n",
-                              connector->base.id,
-                              connector->name);
+                DRM_DEBUG_ATOMIC("Stealing encoder from [CONNECTOR:%d:%s]\n",
+                                 connector->base.id,
+                                 connector->name);
 
                 connector_state = drm_atomic_get_connector_state(state,
                                                                  connector);
@@ -165,9 +165,9 @@ update_connector_routing(struct drm_atomic_state *state, int conn_idx)
         if (!connector)
                 return 0;
 
-        DRM_DEBUG_KMS("Updating routing for [CONNECTOR:%d:%s]\n",
-                        connector->base.id,
-                        connector->name);
+        DRM_DEBUG_ATOMIC("Updating routing for [CONNECTOR:%d:%s]\n",
+                         connector->base.id,
+                         connector->name);
 
         if (connector->state->crtc != connector_state->crtc) {
                 if (connector->state->crtc) {
@@ -186,7 +186,7 @@ update_connector_routing(struct drm_atomic_state *state, int conn_idx)
         }
 
         if (!connector_state->crtc) {
-                DRM_DEBUG_KMS("Disabling [CONNECTOR:%d:%s]\n",
+                DRM_DEBUG_ATOMIC("Disabling [CONNECTOR:%d:%s]\n",
                                 connector->base.id,
                                 connector->name);
 
@@ -199,19 +199,19 @@ update_connector_routing(struct drm_atomic_state *state, int conn_idx)
         new_encoder = funcs->best_encoder(connector);
 
         if (!new_encoder) {
-                DRM_DEBUG_KMS("No suitable encoder found for [CONNECTOR:%d:%s]\n",
-                              connector->base.id,
-                              connector->name);
+                DRM_DEBUG_ATOMIC("No suitable encoder found for [CONNECTOR:%d:%s]\n",
+                                 connector->base.id,
+                                 connector->name);
                 return -EINVAL;
         }
 
         if (new_encoder == connector_state->best_encoder) {
-                DRM_DEBUG_KMS("[CONNECTOR:%d:%s] keeps [ENCODER:%d:%s], now on [CRTC:%d]\n",
-                              connector->base.id,
-                              connector->name,
-                              new_encoder->base.id,
-                              new_encoder->name,
-                              connector_state->crtc->base.id);
+                DRM_DEBUG_ATOMIC("[CONNECTOR:%d:%s] keeps [ENCODER:%d:%s], now on [CRTC:%d]\n",
+                                 connector->base.id,
+                                 connector->name,
+                                 new_encoder->base.id,
+                                 new_encoder->name,
+                                 connector_state->crtc->base.id);
 
                 return 0;
         }
@@ -222,9 +222,9 @@ update_connector_routing(struct drm_atomic_state *state, int conn_idx)
         if (encoder_crtc) {
                 ret = steal_encoder(state, new_encoder, encoder_crtc);
                 if (ret) {
-                        DRM_DEBUG_KMS("Encoder stealing failed for [CONNECTOR:%d:%s]\n",
-                                      connector->base.id,
-                                      connector->name);
+                        DRM_DEBUG_ATOMIC("Encoder stealing failed for [CONNECTOR:%d:%s]\n",
+                                         connector->base.id,
+                                         connector->name);
                         return ret;
                 }
         }
@@ -235,12 +235,12 @@ update_connector_routing(struct drm_atomic_state *state, int conn_idx)
         crtc_state = state->crtc_states[idx];
         crtc_state->mode_changed = true;
 
-        DRM_DEBUG_KMS("[CONNECTOR:%d:%s] using [ENCODER:%d:%s] on [CRTC:%d]\n",
-                      connector->base.id,
-                      connector->name,
-                      new_encoder->base.id,
-                      new_encoder->name,
-                      connector_state->crtc->base.id);
+        DRM_DEBUG_ATOMIC("[CONNECTOR:%d:%s] using [ENCODER:%d:%s] on [CRTC:%d]\n",
+                         connector->base.id,
+                         connector->name,
+                         new_encoder->base.id,
+                         new_encoder->name,
+                         connector_state->crtc->base.id);
 
         return 0;
 }
@@ -292,7 +292,7 @@ mode_fixup(struct drm_atomic_state *state)
                                         encoder->bridge, &crtc_state->mode,
                                         &crtc_state->adjusted_mode);
                         if (!ret) {
-                                DRM_DEBUG_KMS("Bridge fixup failed\n");
+                                DRM_DEBUG_ATOMIC("Bridge fixup failed\n");
                                 return -EINVAL;
                         }
                 }
@@ -301,16 +301,16 @@ mode_fixup(struct drm_atomic_state *state)
                         ret = funcs->atomic_check(encoder, crtc_state,
                                                   conn_state);
                         if (ret) {
-                                DRM_DEBUG_KMS("[ENCODER:%d:%s] check failed\n",
-                                              encoder->base.id, encoder->name);
+                                DRM_DEBUG_ATOMIC("[ENCODER:%d:%s] check failed\n",
+                                                 encoder->base.id, encoder->name);
                                 return ret;
                         }
                 } else {
                         ret = funcs->mode_fixup(encoder, &crtc_state->mode,
                                                 &crtc_state->adjusted_mode);
                         if (!ret) {
-                                DRM_DEBUG_KMS("[ENCODER:%d:%s] fixup failed\n",
-                                              encoder->base.id, encoder->name);
+                                DRM_DEBUG_ATOMIC("[ENCODER:%d:%s] fixup failed\n",
+                                                 encoder->base.id, encoder->name);
                                 return -EINVAL;
                         }
                 }
@@ -330,8 +330,8 @@ mode_fixup(struct drm_atomic_state *state)
                 ret = funcs->mode_fixup(crtc, &crtc_state->mode,
                                         &crtc_state->adjusted_mode);
                 if (!ret) {
-                        DRM_DEBUG_KMS("[CRTC:%d] fixup failed\n",
-                                      crtc->base.id);
+                        DRM_DEBUG_ATOMIC("[CRTC:%d] fixup failed\n",
+                                         crtc->base.id);
                         return -EINVAL;
                 }
         }
@@ -384,14 +384,14 @@ drm_atomic_helper_check_modeset(struct drm_device *dev,
                         continue;
 
                 if (!drm_mode_equal(&crtc->state->mode, &crtc_state->mode)) {
-                        DRM_DEBUG_KMS("[CRTC:%d] mode changed\n",
-                                      crtc->base.id);
+                        DRM_DEBUG_ATOMIC("[CRTC:%d] mode changed\n",
+                                         crtc->base.id);
                         crtc_state->mode_changed = true;
                 }
 
                 if (crtc->state->enable != crtc_state->enable) {
-                        DRM_DEBUG_KMS("[CRTC:%d] enable changed\n",
-                                      crtc->base.id);
+                        DRM_DEBUG_ATOMIC("[CRTC:%d] enable changed\n",
+                                         crtc->base.id);
                         crtc_state->mode_changed = true;
                 }
         }
@@ -428,17 +428,17 @@ drm_atomic_helper_check_modeset(struct drm_device *dev,
                  * a full modeset because update_connector_routing force that.
                  */
                 if (crtc->state->active != crtc_state->active) {
-                        DRM_DEBUG_KMS("[CRTC:%d] active changed\n",
-                                      crtc->base.id);
+                        DRM_DEBUG_ATOMIC("[CRTC:%d] active changed\n",
+                                         crtc->base.id);
                         crtc_state->active_changed = true;
                 }
 
                 if (!needs_modeset(crtc_state))
                         continue;
 
-                DRM_DEBUG_KMS("[CRTC:%d] needs all connectors, enable: %c, active: %c\n",
-                              crtc->base.id,
-                              crtc_state->enable ? 'y' : 'n',
+                DRM_DEBUG_ATOMIC("[CRTC:%d] needs all connectors, enable: %c, active: %c\n",
+                                 crtc->base.id,
+                                 crtc_state->enable ? 'y' : 'n',
                               crtc_state->active ? 'y' : 'n');
 
                 ret = drm_atomic_add_affected_connectors(state, crtc);
@@ -449,8 +449,8 @@ drm_atomic_helper_check_modeset(struct drm_device *dev,
                                                                 crtc);
 
                 if (crtc_state->enable != !!num_connectors) {
-                        DRM_DEBUG_KMS("[CRTC:%d] enabled/connectors mismatch\n",
-                                      crtc->base.id);
+                        DRM_DEBUG_ATOMIC("[CRTC:%d] enabled/connectors mismatch\n",
+                                         crtc->base.id);
 
                         return -EINVAL;
                 }
@@ -497,8 +497,8 @@ drm_atomic_helper_check_planes(struct drm_device *dev,
 
                 ret = funcs->atomic_check(plane, plane_state);
                 if (ret) {
-                        DRM_DEBUG_KMS("[PLANE:%d] atomic driver check failed\n",
-                                      plane->base.id);
+                        DRM_DEBUG_ATOMIC("[PLANE:%d] atomic driver check failed\n",
+                                         plane->base.id);
                         return ret;
                 }
         }
@@ -517,8 +517,8 @@ drm_atomic_helper_check_planes(struct drm_device *dev,
 
                 ret = funcs->atomic_check(crtc, state->crtc_states[i]);
                 if (ret) {
-                        DRM_DEBUG_KMS("[CRTC:%d] atomic driver check failed\n",
-                                      crtc->base.id);
+                        DRM_DEBUG_ATOMIC("[CRTC:%d] atomic driver check failed\n",
+                                         crtc->base.id);
                         return ret;
                 }
         }
@@ -600,8 +600,8 @@ disable_outputs(struct drm_device *dev, struct drm_atomic_state *old_state)
 
                 funcs = encoder->helper_private;
 
-                DRM_DEBUG_KMS("disabling [ENCODER:%d:%s]\n",
-                              encoder->base.id, encoder->name);
+                DRM_DEBUG_ATOMIC("disabling [ENCODER:%d:%s]\n",
+                                 encoder->base.id, encoder->name);
 
                 /*
                  * Each encoder has at most one connector (since we always steal
@@ -639,8 +639,8 @@ disable_outputs(struct drm_device *dev, struct drm_atomic_state *old_state)
 
                 funcs = crtc->helper_private;
 
-                DRM_DEBUG_KMS("disabling [CRTC:%d]\n",
-                              crtc->base.id);
+                DRM_DEBUG_ATOMIC("disabling [CRTC:%d]\n",
+                                 crtc->base.id);
 
 
                 /* Right function depends upon target state. */
@@ -723,9 +723,9 @@ crtc_set_mode(struct drm_device *dev, struct drm_atomic_state *old_state)
 
                 funcs = crtc->helper_private;
 
-                if (crtc->state->enable) {
-                        DRM_DEBUG_KMS("modeset on [CRTC:%d]\n",
-                                      crtc->base.id);
+                if (crtc->state->enable && funcs->mode_set_nofb) {
+                        DRM_DEBUG_ATOMIC("modeset on [CRTC:%d]\n",
+                                         crtc->base.id);
 
                         funcs->mode_set_nofb(crtc);
                 }
@@ -752,14 +752,15 @@ crtc_set_mode(struct drm_device *dev, struct drm_atomic_state *old_state)
                 if (!new_crtc_state->mode_changed)
                         continue;
 
-                DRM_DEBUG_KMS("modeset on [ENCODER:%d:%s]\n",
-                              encoder->base.id, encoder->name);
+                DRM_DEBUG_ATOMIC("modeset on [ENCODER:%d:%s]\n",
+                                 encoder->base.id, encoder->name);
 
                 /*
                  * Each encoder has at most one connector (since we always steal
                  * it away), so we won't call call mode_set hooks twice.
                  */
-                funcs->mode_set(encoder, mode, adjusted_mode);
+                if (funcs->mode_set)
+                        funcs->mode_set(encoder, mode, adjusted_mode);
 
                 if (encoder->bridge && encoder->bridge->funcs->mode_set)
                         encoder->bridge->funcs->mode_set(encoder->bridge,
@@ -768,34 +769,44 @@ crtc_set_mode(struct drm_device *dev, struct drm_atomic_state *old_state)
 }
 
 /**
- * drm_atomic_helper_commit_pre_planes - modeset commit before plane updates
+ * drm_atomic_helper_commit_modeset_disables - modeset commit to disable outputs
  * @dev: DRM device
- * @state: atomic state
+ * @old_state: atomic state object with old state structures
  *
- * This function commits the modeset changes that need to be committed before
- * updating planes. It shuts down all the outputs that need to be shut down and
+ * This function shuts down all the outputs that need to be shut down and
  * prepares them (if required) with the new mode.
+ *
+ * For compatability with legacy crtc helpers this should be called before
+ * drm_atomic_helper_commit_planes(), which is what the default commit function
+ * does. But drivers with different needs can group the modeset commits together
+ * and do the plane commits at the end. This is useful for drivers doing runtime
+ * PM since planes updates then only happen when the CRTC is actually enabled.
  */
-void drm_atomic_helper_commit_pre_planes(struct drm_device *dev,
-                                         struct drm_atomic_state *state)
+void drm_atomic_helper_commit_modeset_disables(struct drm_device *dev,
+                                               struct drm_atomic_state *old_state)
 {
-        disable_outputs(dev, state);
-        set_routing_links(dev, state);
-        crtc_set_mode(dev, state);
+        disable_outputs(dev, old_state);
+        set_routing_links(dev, old_state);
+        crtc_set_mode(dev, old_state);
 }
-EXPORT_SYMBOL(drm_atomic_helper_commit_pre_planes);
+EXPORT_SYMBOL(drm_atomic_helper_commit_modeset_disables);
 
 /**
- * drm_atomic_helper_commit_post_planes - modeset commit after plane updates
+ * drm_atomic_helper_commit_modeset_enables - modeset commit to enable outputs
  * @dev: DRM device
  * @old_state: atomic state object with old state structures
  *
- * This function commits the modeset changes that need to be committed after
- * updating planes: It enables all the outputs with the new configuration which
- * had to be turned off for the update.
+ * This function enables all the outputs with the new configuration which had to
+ * be turned off for the update.
+ *
+ * For compatability with legacy crtc helpers this should be called after
+ * drm_atomic_helper_commit_planes(), which is what the default commit function
+ * does. But drivers with different needs can group the modeset commits together
+ * and do the plane commits at the end. This is useful for drivers doing runtime
+ * PM since planes updates then only happen when the CRTC is actually enabled.
  */
-void drm_atomic_helper_commit_post_planes(struct drm_device *dev,
-                                          struct drm_atomic_state *old_state)
+void drm_atomic_helper_commit_modeset_enables(struct drm_device *dev,
+                                              struct drm_atomic_state *old_state)
 {
         int ncrtcs = old_state->dev->mode_config.num_crtc;
         int i;
@@ -816,8 +827,8 @@ void drm_atomic_helper_commit_post_planes(struct drm_device *dev,
                 funcs = crtc->helper_private;
 
                 if (crtc->state->enable) {
-                        DRM_DEBUG_KMS("enabling [CRTC:%d]\n",
-                                      crtc->base.id);
+                        DRM_DEBUG_ATOMIC("enabling [CRTC:%d]\n",
+                                         crtc->base.id);
 
                         if (funcs->enable)
                                 funcs->enable(crtc);
@@ -842,8 +853,8 @@ void drm_atomic_helper_commit_post_planes(struct drm_device *dev,
                 encoder = connector->state->best_encoder;
                 funcs = encoder->helper_private;
 
-                DRM_DEBUG_KMS("enabling [ENCODER:%d:%s]\n",
-                              encoder->base.id, encoder->name);
+                DRM_DEBUG_ATOMIC("enabling [ENCODER:%d:%s]\n",
+                                 encoder->base.id, encoder->name);
 
                 /*
                  * Each encoder has at most one connector (since we always steal
@@ -861,7 +872,7 @@ void drm_atomic_helper_commit_post_planes(struct drm_device *dev,
                         encoder->bridge->funcs->enable(encoder->bridge);
         }
 }
-EXPORT_SYMBOL(drm_atomic_helper_commit_post_planes);
+EXPORT_SYMBOL(drm_atomic_helper_commit_modeset_enables);
 
 static void wait_for_fences(struct drm_device *dev,
                             struct drm_atomic_state *state)
@@ -1030,11 +1041,11 @@ int drm_atomic_helper_commit(struct drm_device *dev,
 
         wait_for_fences(dev, state);
 
-        drm_atomic_helper_commit_pre_planes(dev, state);
+        drm_atomic_helper_commit_modeset_disables(dev, state);
 
         drm_atomic_helper_commit_planes(dev, state);
 
-        drm_atomic_helper_commit_post_planes(dev, state);
+        drm_atomic_helper_commit_modeset_enables(dev, state);
 
         drm_atomic_helper_wait_for_vblanks(dev, state);
 
@@ -1105,6 +1116,7 @@ int drm_atomic_helper_prepare_planes(struct drm_device *dev,
         for (i = 0; i < nplanes; i++) {
                 struct drm_plane_helper_funcs *funcs;
                 struct drm_plane *plane = state->planes[i];
+                struct drm_plane_state *plane_state = state->plane_states[i];
                 struct drm_framebuffer *fb;
 
                 if (!plane)
@@ -1112,10 +1124,10 @@ int drm_atomic_helper_prepare_planes(struct drm_device *dev,
 
                 funcs = plane->helper_private;
 
-                fb = state->plane_states[i]->fb;
+                fb = plane_state->fb;
 
                 if (fb && funcs->prepare_fb) {
-                        ret = funcs->prepare_fb(plane, fb);
+                        ret = funcs->prepare_fb(plane, fb, plane_state);
                         if (ret)
                                 goto fail;
                 }
@@ -1127,6 +1139,7 @@ fail:
         for (i--; i >= 0; i--) {
                 struct drm_plane_helper_funcs *funcs;
                 struct drm_plane *plane = state->planes[i];
+                struct drm_plane_state *plane_state = state->plane_states[i];
                 struct drm_framebuffer *fb;
 
                 if (!plane)
@@ -1137,7 +1150,7 @@ fail:
                 fb = state->plane_states[i]->fb;
 
                 if (fb && funcs->cleanup_fb)
-                        funcs->cleanup_fb(plane, fb);
+                        funcs->cleanup_fb(plane, fb, plane_state);
 
         }
 
@@ -1243,6 +1256,7 @@ void drm_atomic_helper_cleanup_planes(struct drm_device *dev,
         for (i = 0; i < nplanes; i++) {
                 struct drm_plane_helper_funcs *funcs;
                 struct drm_plane *plane = old_state->planes[i];
+                struct drm_plane_state *plane_state = old_state->plane_states[i];
                 struct drm_framebuffer *old_fb;
 
                 if (!plane)
@@ -1250,10 +1264,10 @@ void drm_atomic_helper_cleanup_planes(struct drm_device *dev,
 
                 funcs = plane->helper_private;
 
-                old_fb = old_state->plane_states[i]->fb;
+                old_fb = plane_state->fb;
 
                 if (old_fb && funcs->cleanup_fb)
-                        funcs->cleanup_fb(plane, old_fb);
+                        funcs->cleanup_fb(plane, old_fb, plane_state);
         }
 }
 EXPORT_SYMBOL(drm_atomic_helper_cleanup_planes);
@@ -1678,12 +1692,13 @@ backoff:
 EXPORT_SYMBOL(drm_atomic_helper_set_config);
 
 /**
- * drm_atomic_helper_crtc_set_property - helper for crtc prorties
+ * drm_atomic_helper_crtc_set_property - helper for crtc properties
  * @crtc: DRM crtc
  * @property: DRM property
  * @val: value of property
  *
- * Provides a default plane disablle handler using the atomic driver interface.
+ * Provides a default crtc set_property handler using the atomic driver
+ * interface.
  *
  * RETURNS:
  * Zero on success, error code on failure
@@ -1737,12 +1752,13 @@ backoff:
 EXPORT_SYMBOL(drm_atomic_helper_crtc_set_property);
 
 /**
- * drm_atomic_helper_plane_set_property - helper for plane prorties
+ * drm_atomic_helper_plane_set_property - helper for plane properties
  * @plane: DRM plane
  * @property: DRM property
  * @val: value of property
  *
- * Provides a default plane disable handler using the atomic driver interface.
+ * Provides a default plane set_property handler using the atomic driver
+ * interface.
  *
  * RETURNS:
  * Zero on success, error code on failure
@@ -1796,12 +1812,13 @@ backoff:
 EXPORT_SYMBOL(drm_atomic_helper_plane_set_property);
 
 /**
- * drm_atomic_helper_connector_set_property - helper for connector prorties
+ * drm_atomic_helper_connector_set_property - helper for connector properties
  * @connector: DRM connector
  * @property: DRM property
  * @val: value of property
  *
- * Provides a default plane disablle handler using the atomic driver interface.
+ * Provides a default connector set_property handler using the atomic driver
+ * interface.
  *
  * RETURNS:
  * Zero on success, error code on failure
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 6b6b07ff720b..927f3445ff38 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -2009,21 +2009,32 @@ int drm_mode_getcrtc(struct drm_device *dev,
                 return -ENOENT;
 
         drm_modeset_lock_crtc(crtc, crtc->primary);
-        crtc_resp->x = crtc->x;
-        crtc_resp->y = crtc->y;
         crtc_resp->gamma_size = crtc->gamma_size;
         if (crtc->primary->fb)
                 crtc_resp->fb_id = crtc->primary->fb->base.id;
         else
                 crtc_resp->fb_id = 0;
 
-        if (crtc->enabled) {
-
-                drm_crtc_convert_to_umode(&crtc_resp->mode, &crtc->mode);
-                crtc_resp->mode_valid = 1;
+        if (crtc->state) {
+                crtc_resp->x = crtc->primary->state->src_x >> 16;
+                crtc_resp->y = crtc->primary->state->src_y >> 16;
+                if (crtc->state->enable) {
+                        drm_crtc_convert_to_umode(&crtc_resp->mode, &crtc->state->mode);
+                        crtc_resp->mode_valid = 1;
 
+                } else {
+                        crtc_resp->mode_valid = 0;
+                }
         } else {
-                crtc_resp->mode_valid = 0;
+                crtc_resp->x = crtc->x;
+                crtc_resp->y = crtc->y;
+                if (crtc->enabled) {
+                        drm_crtc_convert_to_umode(&crtc_resp->mode, &crtc->mode);
+                        crtc_resp->mode_valid = 1;
+
+                } else {
+                        crtc_resp->mode_valid = 0;
+                }
         }
         drm_modeset_unlock_crtc(crtc);
 
@@ -3262,6 +3273,12 @@ static int framebuffer_check(const struct drm_mode_fb_cmd2 *r)
                         DRM_DEBUG_KMS("bad pitch %u for plane %d\n", r->pitches[i], i);
                         return -EINVAL;
                 }
+
+                if (r->modifier[i] && !(r->flags & DRM_MODE_FB_MODIFIERS)) {
+                        DRM_DEBUG_KMS("bad fb modifier %llu for plane %d\n",
+                                      r->modifier[i], i);
+                        return -EINVAL;
+                }
         }
 
         return 0;
@@ -3275,7 +3292,7 @@ static struct drm_framebuffer *add_framebuffer_internal(struct drm_device *dev,
         struct drm_framebuffer *fb;
         int ret;
 
-        if (r->flags & ~DRM_MODE_FB_INTERLACED) {
+        if (r->flags & ~(DRM_MODE_FB_INTERLACED | DRM_MODE_FB_MODIFIERS)) {
                 DRM_DEBUG_KMS("bad framebuffer flags 0x%08x\n", r->flags);
                 return ERR_PTR(-EINVAL);
         }
@@ -3291,6 +3308,12 @@ static struct drm_framebuffer *add_framebuffer_internal(struct drm_device *dev,
                 return ERR_PTR(-EINVAL);
         }
 
+        if (r->flags & DRM_MODE_FB_MODIFIERS &&
+            !dev->mode_config.allow_fb_modifiers) {
+                DRM_DEBUG_KMS("driver does not support fb modifiers\n");
+                return ERR_PTR(-EINVAL);
+        }
+
         ret = framebuffer_check(r);
         if (ret)
                 return ERR_PTR(ret);
diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c
index b1979e7bdc88..3053aab968f9 100644
--- a/drivers/gpu/drm/drm_crtc_helper.c
+++ b/drivers/gpu/drm/drm_crtc_helper.c
@@ -837,6 +837,7 @@ void drm_helper_mode_fill_fb_struct(struct drm_framebuffer *fb,
         for (i = 0; i < 4; i++) {
                 fb->pitches[i] = mode_cmd->pitches[i];
                 fb->offsets[i] = mode_cmd->offsets[i];
+                fb->modifier[i] = mode_cmd->modifier[i];
         }
         drm_fb_get_bpp_depth(mode_cmd->pixel_format, &fb->depth,
                                     &fb->bits_per_pixel);
diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c
index 3785d66721f2..a6d773a61c2d 100644
--- a/drivers/gpu/drm/drm_ioctl.c
+++ b/drivers/gpu/drm/drm_ioctl.c
@@ -321,6 +321,9 @@ static int drm_getcap(struct drm_device *dev, void *data, struct drm_file *file_
                 else
                         req->value = 64;
                 break;
+        case DRM_CAP_ADDFB2_MODIFIERS:
+                req->value = dev->mode_config.allow_fb_modifiers;
+                break;
         default:
                 return -EINVAL;
         }
diff --git a/drivers/gpu/drm/drm_irq.c b/drivers/gpu/drm/drm_irq.c
index 10574a0c3a55..c8a34476570a 100644
--- a/drivers/gpu/drm/drm_irq.c
+++ b/drivers/gpu/drm/drm_irq.c
@@ -276,7 +276,6 @@ static void vblank_disable_fn(unsigned long arg)
 void drm_vblank_cleanup(struct drm_device *dev)
 {
         int crtc;
-        unsigned long irqflags;
 
         /* Bail if the driver didn't call drm_vblank_init() */
         if (dev->num_crtcs == 0)
@@ -285,11 +284,10 @@ void drm_vblank_cleanup(struct drm_device *dev)
         for (crtc = 0; crtc < dev->num_crtcs; crtc++) {
                 struct drm_vblank_crtc *vblank = &dev->vblank[crtc];
 
-                del_timer_sync(&vblank->disable_timer);
+                WARN_ON(vblank->enabled &&
+                        drm_core_check_feature(dev, DRIVER_MODESET));
 
-                spin_lock_irqsave(&dev->vbl_lock, irqflags);
-                vblank_disable_and_save(dev, crtc);
-                spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
+                del_timer_sync(&vblank->disable_timer);
         }
 
         kfree(dev->vblank);
@@ -475,17 +473,23 @@ int drm_irq_uninstall(struct drm_device *dev)
         dev->irq_enabled = false;
 
         /*
-         * Wake up any waiters so they don't hang.
+         * Wake up any waiters so they don't hang. This is just to paper over
+         * isssues for UMS drivers which aren't in full control of their
+         * vblank/irq handling. KMS drivers must ensure that vblanks are all
+         * disabled when uninstalling the irq handler.
          */
         if (dev->num_crtcs) {
                 spin_lock_irqsave(&dev->vbl_lock, irqflags);
                 for (i = 0; i < dev->num_crtcs; i++) {
                         struct drm_vblank_crtc *vblank = &dev->vblank[i];
 
+                        if (!vblank->enabled)
+                                continue;
+
+                        WARN_ON(drm_core_check_feature(dev, DRIVER_MODESET));
+
+                        vblank_disable_and_save(dev, i);
                         wake_up(&vblank->queue);
-                        vblank->enabled = false;
-                        vblank->last =
-                                dev->driver->get_vblank_counter(dev, i);
                 }
                 spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
         }
@@ -1052,7 +1056,7 @@ EXPORT_SYMBOL(drm_vblank_get);
  * Acquire a reference count on vblank events to avoid having them disabled
  * while in use.
  *
- * This is the native kms version of drm_vblank_off().
+ * This is the native kms version of drm_vblank_get().
  *
  * Returns:
  * Zero on success, nonzero on failure.
@@ -1233,6 +1237,38 @@ void drm_crtc_vblank_off(struct drm_crtc *crtc)
 EXPORT_SYMBOL(drm_crtc_vblank_off);
 
 /**
+ * drm_crtc_vblank_reset - reset vblank state to off on a CRTC
+ * @crtc: CRTC in question
+ *
+ * Drivers can use this function to reset the vblank state to off at load time.
+ * Drivers should use this together with the drm_crtc_vblank_off() and
+ * drm_crtc_vblank_on() functions. The difference compared to
+ * drm_crtc_vblank_off() is that this function doesn't save the vblank counter
+ * and hence doesn't need to call any driver hooks.
+ */
+void drm_crtc_vblank_reset(struct drm_crtc *drm_crtc)
+{
+        struct drm_device *dev = drm_crtc->dev;
+        unsigned long irqflags;
+        int crtc = drm_crtc_index(drm_crtc);
+        struct drm_vblank_crtc *vblank = &dev->vblank[crtc];
+
+        spin_lock_irqsave(&dev->vbl_lock, irqflags);
+        /*
+         * Prevent subsequent drm_vblank_get() from enabling the vblank
+         * interrupt by bumping the refcount.
+         */
+        if (!vblank->inmodeset) {
+                atomic_inc(&vblank->refcount);
+                vblank->inmodeset = 1;
+        }
+        spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
+
+        WARN_ON(!list_empty(&dev->vblank_event_list));
+}
+EXPORT_SYMBOL(drm_crtc_vblank_reset);
+
+/**
  * drm_vblank_on - enable vblank events on a CRTC
  * @dev: DRM device
  * @crtc: CRTC in question
@@ -1653,7 +1689,7 @@ bool drm_handle_vblank(struct drm_device *dev, int crtc)
         struct timeval tvblank;
         unsigned long irqflags;
 
-        if (!dev->num_crtcs)
+        if (WARN_ON_ONCE(!dev->num_crtcs))
                 return false;
 
         if (WARN_ON(crtc >= dev->num_crtcs))
diff --git a/drivers/gpu/drm/drm_plane_helper.c b/drivers/gpu/drm/drm_plane_helper.c
index 5ba5792bfdba..813a06627eb3 100644
--- a/drivers/gpu/drm/drm_plane_helper.c
+++ b/drivers/gpu/drm/drm_plane_helper.c
@@ -437,7 +437,8 @@ int drm_plane_helper_commit(struct drm_plane *plane,
 
         if (plane_funcs->prepare_fb && plane_state->fb &&
             plane_state->fb != old_fb) {
-                ret = plane_funcs->prepare_fb(plane, plane_state->fb);
+                ret = plane_funcs->prepare_fb(plane, plane_state->fb,
+                                              plane_state);
                 if (ret)
                         goto out;
         }
@@ -487,7 +488,7 @@ int drm_plane_helper_commit(struct drm_plane *plane,
         }
 
         if (plane_funcs->cleanup_fb && old_fb)
-                plane_funcs->cleanup_fb(plane, old_fb);
+                plane_funcs->cleanup_fb(plane, old_fb, plane_state);
 out:
         if (plane_state) {
                 if (plane->funcs->atomic_destroy_state)
diff --git a/drivers/gpu/drm/i2c/tda998x_drv.c b/drivers/gpu/drm/i2c/tda998x_drv.c
index a9041d1a8ff0..5febffdb027d 100644
--- a/drivers/gpu/drm/i2c/tda998x_drv.c
+++ b/drivers/gpu/drm/i2c/tda998x_drv.c
@@ -25,6 +25,7 @@
 #include <drm/drm_crtc_helper.h>
 #include <drm/drm_encoder_slave.h>
 #include <drm/drm_edid.h>
+#include <drm/drm_of.h>
 #include <drm/i2c/tda998x.h>
 
 #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
@@ -387,7 +388,7 @@ set_page(struct tda998x_priv *priv, uint16_t reg)
                 };
                 int ret = i2c_master_send(client, buf, sizeof(buf));
                 if (ret < 0) {
-                        dev_err(&client->dev, "setpage %04x err %d\n",
+                        dev_err(&client->dev, "%s %04x err %d\n", __func__,
                                         reg, ret);
                         return ret;
                 }
@@ -1035,8 +1036,9 @@ tda998x_encoder_detect(struct tda998x_priv *priv)
                         connector_status_disconnected;
 }
 
-static int read_edid_block(struct tda998x_priv *priv, uint8_t *buf, int blk)
+static int read_edid_block(void *data, u8 *buf, unsigned int blk, size_t length)
 {
+        struct tda998x_priv *priv = data;
         uint8_t offset, segptr;
         int ret, i;
 
@@ -1080,8 +1082,8 @@ static int read_edid_block(struct tda998x_priv *priv, uint8_t *buf, int blk)
                 return -ETIMEDOUT;
         }
 
-        ret = reg_read_range(priv, REG_EDID_DATA_0, buf, EDID_LENGTH);
-        if (ret != EDID_LENGTH) {
+        ret = reg_read_range(priv, REG_EDID_DATA_0, buf, length);
+        if (ret != length) {
                 dev_err(&priv->hdmi->dev, "failed to read edid block %d: %d\n",
                         blk, ret);
                 return ret;
@@ -1090,82 +1092,31 @@ static int read_edid_block(struct tda998x_priv *priv, uint8_t *buf, int blk)
         return 0;
 }
 
-static uint8_t *do_get_edid(struct tda998x_priv *priv)
+static int
+tda998x_encoder_get_modes(struct tda998x_priv *priv,
+                          struct drm_connector *connector)
 {
-        int j, valid_extensions = 0;
-        uint8_t *block, *new;
-        bool print_bad_edid = drm_debug & DRM_UT_KMS;
-
-        if ((block = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
-                return NULL;
+        struct edid *edid;
+        int n;
 
         if (priv->rev == TDA19988)
                 reg_clear(priv, REG_TX4, TX4_PD_RAM);
 
-        /* base block fetch */
-        if (read_edid_block(priv, block, 0))
-                goto fail;
-
-        if (!drm_edid_block_valid(block, 0, print_bad_edid))
-                goto fail;
-
-        /* if there's no extensions, we're done */
-        if (block[0x7e] == 0)
-                goto done;
-
-        new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, GFP_KERNEL);
-        if (!new)
-                goto fail;
-        block = new;
-
-        for (j = 1; j <= block[0x7e]; j++) {
-                uint8_t *ext_block = block + (valid_extensions + 1) * EDID_LENGTH;
-                if (read_edid_block(priv, ext_block, j))
-                        goto fail;
-
-                if (!drm_edid_block_valid(ext_block, j, print_bad_edid))
-                        goto fail;
-
-                valid_extensions++;
-        }
-
-        if (valid_extensions != block[0x7e]) {
-                block[EDID_LENGTH-1] += block[0x7e] - valid_extensions;
-                block[0x7e] = valid_extensions;
-                new = krealloc(block, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
-                if (!new)
-                        goto fail;
-                block = new;
-        }
+        edid = drm_do_get_edid(connector, read_edid_block, priv);
 
-done:
         if (priv->rev == TDA19988)
                 reg_set(priv, REG_TX4, TX4_PD_RAM);
 
-        return block;
-
-fail:
-        if (priv->rev == TDA19988)
-                reg_set(priv, REG_TX4, TX4_PD_RAM);
-        dev_warn(&priv->hdmi->dev, "failed to read EDID\n");
-        kfree(block);
-        return NULL;
-}
-
-static int
-tda998x_encoder_get_modes(struct tda998x_priv *priv,
-                          struct drm_connector *connector)
-{
-        struct edid *edid = (struct edid *)do_get_edid(priv);
-        int n = 0;
-
-        if (edid) {
-                drm_mode_connector_update_edid_property(connector, edid);
-                n = drm_add_edid_modes(connector, edid);
-                priv->is_hdmi_sink = drm_detect_hdmi_monitor(edid);
-                kfree(edid);
+        if (!edid) {
+                dev_warn(&priv->hdmi->dev, "failed to read EDID\n");
+                return 0;
         }
 
+        drm_mode_connector_update_edid_property(connector, edid);
+        n = drm_add_edid_modes(connector, edid);
+        priv->is_hdmi_sink = drm_detect_hdmi_monitor(edid);
+        kfree(edid);
+
         return n;
 }
 
@@ -1547,6 +1498,7 @@ static int tda998x_bind(struct device *dev, struct device *master, void *data)
         struct i2c_client *client = to_i2c_client(dev);
         struct drm_device *drm = data;
         struct tda998x_priv2 *priv;
+        uint32_t crtcs = 0;
         int ret;
 
         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
@@ -1555,9 +1507,18 @@ static int tda998x_bind(struct device *dev, struct device *master, void *data)
 
         dev_set_drvdata(dev, priv);
 
+        if (dev->of_node)
+                crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
+
+        /* If no CRTCs were found, fall back to our old behaviour */
+        if (crtcs == 0) {
+                dev_warn(dev, "Falling back to first CRTC\n");
+                crtcs = 1 << 0;
+        }
+
         priv->base.encoder = &priv->encoder;
         priv->connector.interlace_allowed = 1;
-        priv->encoder.possible_crtcs = 1 << 0;
+        priv->encoder.possible_crtcs = crtcs;
 
         ret = tda998x_create(client, &priv->base);
         if (ret)
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index f01922591679..d3ebaf204408 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -83,9 +83,11 @@ i915-y += dvo_ch7017.o \
           intel_sdvo.o \
           intel_tv.o
 
+# virtual gpu code
+i915-y += i915_vgpu.o
+
 # legacy horrors
-i915-y += i915_dma.o \
-          i915_ums.o
+i915-y += i915_dma.o
 
 obj-$(CONFIG_DRM_I915)  += i915.o
 
diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
index 806e812340d0..9a6da3536ae5 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -818,24 +818,26 @@ static bool valid_reg(const u32 *table, int count, u32 addr)
         return false;
 }
 
-static u32 *vmap_batch(struct drm_i915_gem_object *obj)
+static u32 *vmap_batch(struct drm_i915_gem_object *obj,
+                       unsigned start, unsigned len)
 {
         int i;
         void *addr = NULL;
         struct sg_page_iter sg_iter;
+        int first_page = start >> PAGE_SHIFT;
+        int last_page = (len + start + 4095) >> PAGE_SHIFT;
+        int npages = last_page - first_page;
         struct page **pages;
 
-        pages = drm_malloc_ab(obj->base.size >> PAGE_SHIFT, sizeof(*pages));
+        pages = drm_malloc_ab(npages, sizeof(*pages));
         if (pages == NULL) {
                 DRM_DEBUG_DRIVER("Failed to get space for pages\n");
                 goto finish;
         }
 
         i = 0;
-        for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
-                pages[i] = sg_page_iter_page(&sg_iter);
-                i++;
-        }
+        for_each_sg_page(obj->pages->sgl, &sg_iter, npages, first_page)
+                pages[i++] = sg_page_iter_page(&sg_iter);
 
         addr = vmap(pages, i, 0, PAGE_KERNEL);
         if (addr == NULL) {
@@ -855,61 +857,61 @@ static u32 *copy_batch(struct drm_i915_gem_object *dest_obj,
                        u32 batch_start_offset,
                        u32 batch_len)
 {
-        int ret = 0;
         int needs_clflush = 0;
-        u32 *src_base, *dest_base = NULL;
-        u32 *src_addr, *dest_addr;
-        u32 offset = batch_start_offset / sizeof(*dest_addr);
-        u32 end = batch_start_offset + batch_len;
+        void *src_base, *src;
+        void *dst = NULL;
+        int ret;
 
-        if (end > dest_obj->base.size || end > src_obj->base.size)
+        if (batch_len > dest_obj->base.size ||
+            batch_len + batch_start_offset > src_obj->base.size)
                 return ERR_PTR(-E2BIG);
 
         ret = i915_gem_obj_prepare_shmem_read(src_obj, &needs_clflush);
         if (ret) {
-                DRM_DEBUG_DRIVER("CMD: failed to prep read\n");
+                DRM_DEBUG_DRIVER("CMD: failed to prepare shadow batch\n");
                 return ERR_PTR(ret);
         }
 
-        src_base = vmap_batch(src_obj);
+        src_base = vmap_batch(src_obj, batch_start_offset, batch_len);
         if (!src_base) {
                 DRM_DEBUG_DRIVER("CMD: Failed to vmap batch\n");
                 ret = -ENOMEM;
                 goto unpin_src;
         }
 
-        src_addr = src_base + offset;
-
-        if (needs_clflush)
-                drm_clflush_virt_range((char *)src_addr, batch_len);
+        ret = i915_gem_object_get_pages(dest_obj);
+        if (ret) {
+                DRM_DEBUG_DRIVER("CMD: Failed to get pages for shadow batch\n");
+                goto unmap_src;
+        }
+        i915_gem_object_pin_pages(dest_obj);
 
         ret = i915_gem_object_set_to_cpu_domain(dest_obj, true);
         if (ret) {
-                DRM_DEBUG_DRIVER("CMD: Failed to set batch CPU domain\n");
+                DRM_DEBUG_DRIVER("CMD: Failed to set shadow batch to CPU\n");
                 goto unmap_src;
         }
 
-        dest_base = vmap_batch(dest_obj);
-        if (!dest_base) {
+        dst = vmap_batch(dest_obj, 0, batch_len);
+        if (!dst) {
                 DRM_DEBUG_DRIVER("CMD: Failed to vmap shadow batch\n");
+                i915_gem_object_unpin_pages(dest_obj);
                 ret = -ENOMEM;
                 goto unmap_src;
         }
 
-        dest_addr = dest_base + offset;
-
-        if (batch_start_offset != 0)
-                memset((u8 *)dest_base, 0, batch_start_offset);
+        src = src_base + offset_in_page(batch_start_offset);
+        if (needs_clflush)
+                drm_clflush_virt_range(src, batch_len);
 
-        memcpy(dest_addr, src_addr, batch_len);
-        memset((u8 *)dest_addr + batch_len, 0, dest_obj->base.size - end);
+        memcpy(dst, src, batch_len);
 
 unmap_src:
         vunmap(src_base);
 unpin_src:
         i915_gem_object_unpin_pages(src_obj);
 
-        return ret ? ERR_PTR(ret) : dest_base;
+        return ret ? ERR_PTR(ret) : dst;
 }
 
 /**
@@ -1046,34 +1048,26 @@ int i915_parse_cmds(struct intel_engine_cs *ring,
                     u32 batch_len,
                     bool is_master)
 {
-        int ret = 0;
         u32 *cmd, *batch_base, *batch_end;
         struct drm_i915_cmd_descriptor default_desc = { 0 };
         bool oacontrol_set = false; /* OACONTROL tracking. See check_cmd() */
-
-        ret = i915_gem_obj_ggtt_pin(shadow_batch_obj, 4096, 0);
-        if (ret) {
-                DRM_DEBUG_DRIVER("CMD: Failed to pin shadow batch\n");
-                return -1;
-        }
+        int ret = 0;
 
         batch_base = copy_batch(shadow_batch_obj, batch_obj,
                                 batch_start_offset, batch_len);
         if (IS_ERR(batch_base)) {
                 DRM_DEBUG_DRIVER("CMD: Failed to copy batch\n");
-                i915_gem_object_ggtt_unpin(shadow_batch_obj);
                 return PTR_ERR(batch_base);
         }
 
-        cmd = batch_base + (batch_start_offset / sizeof(*cmd));
-
         /*
          * We use the batch length as size because the shadow object is as
          * large or larger and copy_batch() will write MI_NOPs to the extra
          * space. Parsing should be faster in some cases this way.
          */
-        batch_end = cmd + (batch_len / sizeof(*batch_end));
+        batch_end = batch_base + (batch_len / sizeof(*batch_end));
 
+        cmd = batch_base;
         while (cmd < batch_end) {
                 const struct drm_i915_cmd_descriptor *desc;
                 u32 length;
@@ -1132,7 +1126,7 @@ int i915_parse_cmds(struct intel_engine_cs *ring,
         }
 
         vunmap(batch_base);
-        i915_gem_object_ggtt_unpin(shadow_batch_obj);
+        i915_gem_object_unpin_pages(shadow_batch_obj);
 
         return ret;
 }
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index e8b18e542da4..e38f45374d55 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -139,10 +139,11 @@ describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
                    obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
         if (obj->base.name)
                 seq_printf(m, " (name: %d)", obj->base.name);
-        list_for_each_entry(vma, &obj->vma_list, vma_link)
+        list_for_each_entry(vma, &obj->vma_list, vma_link) {
                 if (vma->pin_count > 0)
                         pin_count++;
-                seq_printf(m, " (pinned x %d)", pin_count);
+        }
+        seq_printf(m, " (pinned x %d)", pin_count);
         if (obj->pin_display)
                 seq_printf(m, " (display)");
         if (obj->fence_reg != I915_FENCE_REG_NONE)
@@ -580,7 +581,7 @@ static int i915_gem_pageflip_info(struct seq_file *m, void *data)
                         seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
                                    work->flip_queued_vblank,
                                    work->flip_ready_vblank,
-                                   drm_vblank_count(dev, crtc->pipe));
+                                   drm_crtc_vblank_count(&crtc->base));
                         if (work->enable_stall_check)
                                 seq_puts(m, "Stall check enabled, ");
                         else
@@ -1778,11 +1779,12 @@ static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
         ifbdev = dev_priv->fbdev;
         fb = to_intel_framebuffer(ifbdev->helper.fb);
 
-        seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
+        seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
                    fb->base.width,
                    fb->base.height,
                    fb->base.depth,
                    fb->base.bits_per_pixel,
+                   fb->base.modifier[0],
                    atomic_read(&fb->base.refcount.refcount));
         describe_obj(m, fb->obj);
         seq_putc(m, '\n');
@@ -1793,11 +1795,12 @@ static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
                 if (ifbdev && &fb->base == ifbdev->helper.fb)
                         continue;
 
-                seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
+                seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
                            fb->base.width,
                            fb->base.height,
                            fb->base.depth,
                            fb->base.bits_per_pixel,
+                           fb->base.modifier[0],
                            atomic_read(&fb->base.refcount.refcount));
                 describe_obj(m, fb->obj);
                 seq_putc(m, '\n');
@@ -2183,7 +2186,7 @@ static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
 
                 seq_puts(m, "aliasing PPGTT:\n");
-                seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
+                seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.pd_offset);
 
                 ppgtt->debug_dump(ppgtt, m);
         }
@@ -4189,7 +4192,7 @@ i915_max_freq_set(void *data, u64 val)
 {
         struct drm_device *dev = data;
         struct drm_i915_private *dev_priv = dev->dev_private;
-        u32 rp_state_cap, hw_max, hw_min;
+        u32 hw_max, hw_min;
         int ret;
 
         if (INTEL_INFO(dev)->gen < 6)
@@ -4206,18 +4209,10 @@ i915_max_freq_set(void *data, u64 val)
         /*
          * Turbo will still be enabled, but won't go above the set value.
          */
-        if (IS_VALLEYVIEW(dev)) {
-                val = intel_freq_opcode(dev_priv, val);
-
-                hw_max = dev_priv->rps.max_freq;
-                hw_min = dev_priv->rps.min_freq;
-        } else {
-                val = intel_freq_opcode(dev_priv, val);
+        val = intel_freq_opcode(dev_priv, val);
 
-                rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
-                hw_max = dev_priv->rps.max_freq;
-                hw_min = (rp_state_cap >> 16) & 0xff;
-        }
+        hw_max = dev_priv->rps.max_freq;
+        hw_min = dev_priv->rps.min_freq;
 
         if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
                 mutex_unlock(&dev_priv->rps.hw_lock);
@@ -4226,10 +4221,7 @@ i915_max_freq_set(void *data, u64 val)
 
         dev_priv->rps.max_freq_softlimit = val;
 
-        if (IS_VALLEYVIEW(dev))
-                valleyview_set_rps(dev, val);
-        else
-                gen6_set_rps(dev, val);
+        intel_set_rps(dev, val);
 
         mutex_unlock(&dev_priv->rps.hw_lock);
 
@@ -4267,7 +4259,7 @@ i915_min_freq_set(void *data, u64 val)
 {
         struct drm_device *dev = data;
         struct drm_i915_private *dev_priv = dev->dev_private;
-        u32 rp_state_cap, hw_max, hw_min;
+        u32 hw_max, hw_min;
         int ret;
 
         if (INTEL_INFO(dev)->gen < 6)
@@ -4284,18 +4276,10 @@ i915_min_freq_set(void *data, u64 val)
         /*
          * Turbo will still be enabled, but won't go below the set value.
          */
-        if (IS_VALLEYVIEW(dev)) {
-                val = intel_freq_opcode(dev_priv, val);
+        val = intel_freq_opcode(dev_priv, val);
 
-                hw_max = dev_priv->rps.max_freq;
-                hw_min = dev_priv->rps.min_freq;
-        } else {
-                val = intel_freq_opcode(dev_priv, val);
-
-                rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
-                hw_max = dev_priv->rps.max_freq;
-                hw_min = (rp_state_cap >> 16) & 0xff;
-        }
+        hw_max = dev_priv->rps.max_freq;
+        hw_min = dev_priv->rps.min_freq;
 
         if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
                 mutex_unlock(&dev_priv->rps.hw_lock);
@@ -4304,10 +4288,7 @@ i915_min_freq_set(void *data, u64 val)
 
         dev_priv->rps.min_freq_softlimit = val;
 
-        if (IS_VALLEYVIEW(dev))
-                valleyview_set_rps(dev, val);
-        else
-                gen6_set_rps(dev, val);
+        intel_set_rps(dev, val);
 
         mutex_unlock(&dev_priv->rps.hw_lock);
 
@@ -4374,6 +4355,85 @@ DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
                         i915_cache_sharing_get, i915_cache_sharing_set,
                         "%llu\n");
 
+static int i915_sseu_status(struct seq_file *m, void *unused)
+{
+        struct drm_info_node *node = (struct drm_info_node *) m->private;
+        struct drm_device *dev = node->minor->dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        unsigned int s_tot = 0, ss_tot = 0, ss_per = 0, eu_tot = 0, eu_per = 0;
+
+        if (INTEL_INFO(dev)->gen < 9)
+                return -ENODEV;
+
+        seq_puts(m, "SSEU Device Info\n");
+        seq_printf(m, "  Available Slice Total: %u\n",
+                   INTEL_INFO(dev)->slice_total);
+        seq_printf(m, "  Available Subslice Total: %u\n",
+                   INTEL_INFO(dev)->subslice_total);
+        seq_printf(m, "  Available Subslice Per Slice: %u\n",
+                   INTEL_INFO(dev)->subslice_per_slice);
+        seq_printf(m, "  Available EU Total: %u\n",
+                   INTEL_INFO(dev)->eu_total);
+        seq_printf(m, "  Available EU Per Subslice: %u\n",
+                   INTEL_INFO(dev)->eu_per_subslice);
+        seq_printf(m, "  Has Slice Power Gating: %s\n",
+                   yesno(INTEL_INFO(dev)->has_slice_pg));
+        seq_printf(m, "  Has Subslice Power Gating: %s\n",
+                   yesno(INTEL_INFO(dev)->has_subslice_pg));
+        seq_printf(m, "  Has EU Power Gating: %s\n",
+                   yesno(INTEL_INFO(dev)->has_eu_pg));
+
+        seq_puts(m, "SSEU Device Status\n");
+        if (IS_SKYLAKE(dev)) {
+                const int s_max = 3, ss_max = 4;
+                int s, ss;
+                u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
+
+                s_reg[0] = I915_READ(GEN9_SLICE0_PGCTL_ACK);
+                s_reg[1] = I915_READ(GEN9_SLICE1_PGCTL_ACK);
+                s_reg[2] = I915_READ(GEN9_SLICE2_PGCTL_ACK);
+                eu_reg[0] = I915_READ(GEN9_SLICE0_SS01_EU_PGCTL_ACK);
+                eu_reg[1] = I915_READ(GEN9_SLICE0_SS23_EU_PGCTL_ACK);
+                eu_reg[2] = I915_READ(GEN9_SLICE1_SS01_EU_PGCTL_ACK);
+                eu_reg[3] = I915_READ(GEN9_SLICE1_SS23_EU_PGCTL_ACK);
+                eu_reg[4] = I915_READ(GEN9_SLICE2_SS01_EU_PGCTL_ACK);
+                eu_reg[5] = I915_READ(GEN9_SLICE2_SS23_EU_PGCTL_ACK);
+                eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
+                             GEN9_PGCTL_SSA_EU19_ACK |
+                             GEN9_PGCTL_SSA_EU210_ACK |
+                             GEN9_PGCTL_SSA_EU311_ACK;
+                eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
+                             GEN9_PGCTL_SSB_EU19_ACK |
+                             GEN9_PGCTL_SSB_EU210_ACK |
+                             GEN9_PGCTL_SSB_EU311_ACK;
+
+                for (s = 0; s < s_max; s++) {
+                        if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
+                                /* skip disabled slice */
+                                continue;
+
+                        s_tot++;
+                        ss_per = INTEL_INFO(dev)->subslice_per_slice;
+                        ss_tot += ss_per;
+                        for (ss = 0; ss < ss_max; ss++) {
+                                unsigned int eu_cnt;
+
+                                eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
+                                                       eu_mask[ss%2]);
+                                eu_tot += eu_cnt;
+                                eu_per = max(eu_per, eu_cnt);
+                        }
+                }
+        }
+        seq_printf(m, "  Enabled Slice Total: %u\n", s_tot);
+        seq_printf(m, "  Enabled Subslice Total: %u\n", ss_tot);
+        seq_printf(m, "  Enabled Subslice Per Slice: %u\n", ss_per);
+        seq_printf(m, "  Enabled EU Total: %u\n", eu_tot);
+        seq_printf(m, "  Enabled EU Per Subslice: %u\n", eu_per);
+
+        return 0;
+}
+
 static int i915_forcewake_open(struct inode *inode, struct file *file)
 {
         struct drm_device *dev = inode->i_private;
@@ -4487,6 +4547,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
         {"i915_dp_mst_info", i915_dp_mst_info, 0},
         {"i915_wa_registers", i915_wa_registers, 0},
         {"i915_ddb_info", i915_ddb_info, 0},
+        {"i915_sseu_status", i915_sseu_status, 0},
 };
 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
 
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 1a46787129e7..053e1788f578 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -36,6 +36,7 @@
 #include "intel_drv.h"
 #include <drm/i915_drm.h>
 #include "i915_drv.h"
+#include "i915_vgpu.h"
 #include "i915_trace.h"
 #include <linux/pci.h>
 #include <linux/console.h>
@@ -605,6 +606,7 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
                 }
         }
 
+        /* Initialize slice/subslice/EU info */
         if (IS_CHERRYVIEW(dev)) {
                 u32 fuse, mask_eu;
 
@@ -614,7 +616,90 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
                                   CHV_FGT_EU_DIS_SS1_R0_MASK |
                                   CHV_FGT_EU_DIS_SS1_R1_MASK);
                 info->eu_total = 16 - hweight32(mask_eu);
+        } else if (IS_SKYLAKE(dev)) {
+                const int s_max = 3, ss_max = 4, eu_max = 8;
+                int s, ss;
+                u32 fuse2, eu_disable[s_max], s_enable, ss_disable;
+
+                fuse2 = I915_READ(GEN8_FUSE2);
+                s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >>
+                           GEN8_F2_S_ENA_SHIFT;
+                ss_disable = (fuse2 & GEN9_F2_SS_DIS_MASK) >>
+                             GEN9_F2_SS_DIS_SHIFT;
+
+                eu_disable[0] = I915_READ(GEN8_EU_DISABLE0);
+                eu_disable[1] = I915_READ(GEN8_EU_DISABLE1);
+                eu_disable[2] = I915_READ(GEN8_EU_DISABLE2);
+
+                info->slice_total = hweight32(s_enable);
+                /*
+                 * The subslice disable field is global, i.e. it applies
+                 * to each of the enabled slices.
+                */
+                info->subslice_per_slice = ss_max - hweight32(ss_disable);
+                info->subslice_total = info->slice_total *
+                                       info->subslice_per_slice;
+
+                /*
+                 * Iterate through enabled slices and subslices to
+                 * count the total enabled EU.
+                */
+                for (s = 0; s < s_max; s++) {
+                        if (!(s_enable & (0x1 << s)))
+                                /* skip disabled slice */
+                                continue;
+
+                        for (ss = 0; ss < ss_max; ss++) {
+                                u32 n_disabled;
+
+                                if (ss_disable & (0x1 << ss))
+                                        /* skip disabled subslice */
+                                        continue;
+
+                                n_disabled = hweight8(eu_disable[s] >>
+                                                      (ss * eu_max));
+
+                                /*
+                                 * Record which subslice(s) has(have) 7 EUs. we
+                                 * can tune the hash used to spread work among
+                                 * subslices if they are unbalanced.
+                                 */
+                                if (eu_max - n_disabled == 7)
+                                        info->subslice_7eu[s] |= 1 << ss;
+
+                                info->eu_total += eu_max - n_disabled;
+                        }
+                }
+
+                /*
+                 * SKL is expected to always have a uniform distribution
+                 * of EU across subslices with the exception that any one
+                 * EU in any one subslice may be fused off for die
+                 * recovery.
+                */
+                info->eu_per_subslice = info->subslice_total ?
+                                        DIV_ROUND_UP(info->eu_total,
+                                                     info->subslice_total) : 0;
+                /*
+                 * SKL supports slice power gating on devices with more than
+                 * one slice, and supports EU power gating on devices with
+                 * more than one EU pair per subslice.
+                */
+                info->has_slice_pg = (info->slice_total > 1) ? 1 : 0;
+                info->has_subslice_pg = 0;
+                info->has_eu_pg = (info->eu_per_subslice > 2) ? 1 : 0;
         }
+        DRM_DEBUG_DRIVER("slice total: %u\n", info->slice_total);
+        DRM_DEBUG_DRIVER("subslice total: %u\n", info->subslice_total);
+        DRM_DEBUG_DRIVER("subslice per slice: %u\n", info->subslice_per_slice);
+        DRM_DEBUG_DRIVER("EU total: %u\n", info->eu_total);
+        DRM_DEBUG_DRIVER("EU per subslice: %u\n", info->eu_per_subslice);
+        DRM_DEBUG_DRIVER("has slice power gating: %s\n",
+                         info->has_slice_pg ? "y" : "n");
+        DRM_DEBUG_DRIVER("has subslice power gating: %s\n",
+                         info->has_subslice_pg ? "y" : "n");
+        DRM_DEBUG_DRIVER("has EU power gating: %s\n",
+                         info->has_eu_pg ? "y" : "n");
 }
 
 /**
@@ -637,17 +722,6 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 
         info = (struct intel_device_info *) flags;
 
-        /* Refuse to load on gen6+ without kms enabled. */
-        if (info->gen >= 6 && !drm_core_check_feature(dev, DRIVER_MODESET)) {
-                DRM_INFO("Your hardware requires kernel modesetting (KMS)\n");
-                DRM_INFO("See CONFIG_DRM_I915_KMS, nomodeset, and i915.modeset parameters\n");
-                return -ENODEV;
-        }
-
-        /* UMS needs agp support. */
-        if (!drm_core_check_feature(dev, DRIVER_MODESET) && !dev->agp)
-                return -EINVAL;
-
         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
         if (dev_priv == NULL)
                 return -ENOMEM;
@@ -717,20 +791,18 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
         if (ret)
                 goto out_regs;
 
-        if (drm_core_check_feature(dev, DRIVER_MODESET)) {
-                /* WARNING: Apparently we must kick fbdev drivers before vgacon,
-                 * otherwise the vga fbdev driver falls over. */
-                ret = i915_kick_out_firmware_fb(dev_priv);
-                if (ret) {
-                        DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
-                        goto out_gtt;
-                }
+        /* WARNING: Apparently we must kick fbdev drivers before vgacon,
+         * otherwise the vga fbdev driver falls over. */
+        ret = i915_kick_out_firmware_fb(dev_priv);
+        if (ret) {
+                DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
+                goto out_gtt;
+        }
 
-                ret = i915_kick_out_vgacon(dev_priv);
-                if (ret) {
-                        DRM_ERROR("failed to remove conflicting VGA console\n");
-                        goto out_gtt;
-                }
+        ret = i915_kick_out_vgacon(dev_priv);
+        if (ret) {
+                DRM_ERROR("failed to remove conflicting VGA console\n");
+                goto out_gtt;
         }
 
         pci_set_master(dev->pdev);
@@ -834,14 +906,19 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 
         intel_power_domains_init(dev_priv);
 
-        if (drm_core_check_feature(dev, DRIVER_MODESET)) {
-                ret = i915_load_modeset_init(dev);
-                if (ret < 0) {
-                        DRM_ERROR("failed to init modeset\n");
-                        goto out_power_well;
-                }
+        ret = i915_load_modeset_init(dev);
+        if (ret < 0) {
+                DRM_ERROR("failed to init modeset\n");
+                goto out_power_well;
         }
 
+        /*
+         * Notify a valid surface after modesetting,
+         * when running inside a VM.
+         */
+        if (intel_vgpu_active(dev))
+                I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
+
         i915_setup_sysfs(dev);
 
         if (INTEL_INFO(dev)->num_pipes) {
@@ -921,28 +998,25 @@ int i915_driver_unload(struct drm_device *dev)
 
         acpi_video_unregister();
 
-        if (drm_core_check_feature(dev, DRIVER_MODESET))
-                intel_fbdev_fini(dev);
+        intel_fbdev_fini(dev);
 
         drm_vblank_cleanup(dev);
 
-        if (drm_core_check_feature(dev, DRIVER_MODESET)) {
-                intel_modeset_cleanup(dev);
-
-                /*
-                 * free the memory space allocated for the child device
-                 * config parsed from VBT
-                 */
-                if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
-                        kfree(dev_priv->vbt.child_dev);
-                        dev_priv->vbt.child_dev = NULL;
-                        dev_priv->vbt.child_dev_num = 0;
-                }
+        intel_modeset_cleanup(dev);
 
-                vga_switcheroo_unregister_client(dev->pdev);
-                vga_client_register(dev->pdev, NULL, NULL, NULL);
+        /*
+         * free the memory space allocated for the child device
+         * config parsed from VBT
+         */
+        if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
+                kfree(dev_priv->vbt.child_dev);
+                dev_priv->vbt.child_dev = NULL;
+                dev_priv->vbt.child_dev_num = 0;
         }
 
+        vga_switcheroo_unregister_client(dev->pdev);
+        vga_client_register(dev->pdev, NULL, NULL, NULL);
+
         /* Free error state after interrupts are fully disabled. */
         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
         i915_destroy_error_state(dev);
@@ -952,17 +1026,15 @@ int i915_driver_unload(struct drm_device *dev)
 
         intel_opregion_fini(dev);
 
-        if (drm_core_check_feature(dev, DRIVER_MODESET)) {
-                /* Flush any outstanding unpin_work. */
-                flush_workqueue(dev_priv->wq);
+        /* Flush any outstanding unpin_work. */
+        flush_workqueue(dev_priv->wq);
 
-                mutex_lock(&dev->struct_mutex);
-                i915_gem_cleanup_ringbuffer(dev);
-                i915_gem_batch_pool_fini(&dev_priv->mm.batch_pool);
-                i915_gem_context_fini(dev);
-                mutex_unlock(&dev->struct_mutex);
-                i915_gem_cleanup_stolen(dev);
-        }
+        mutex_lock(&dev->struct_mutex);
+        i915_gem_cleanup_ringbuffer(dev);
+        i915_gem_batch_pool_fini(&dev_priv->mm.batch_pool);
+        i915_gem_context_fini(dev);
+        mutex_unlock(&dev->struct_mutex);
+        i915_gem_cleanup_stolen(dev);
 
         intel_teardown_gmbus(dev);
         intel_teardown_mchbar(dev);
@@ -1023,8 +1095,7 @@ void i915_driver_preclose(struct drm_device *dev, struct drm_file *file)
         i915_gem_release(dev, file);
         mutex_unlock(&dev->struct_mutex);
 
-        if (drm_core_check_feature(dev, DRIVER_MODESET))
-                intel_modeset_preclose(dev, file);
+        intel_modeset_preclose(dev, file);
 }
 
 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index cc6ea53d2b81..0001642c38b4 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -369,6 +369,19 @@ static const struct intel_device_info intel_skylake_info = {
         IVB_CURSOR_OFFSETS,
 };
 
+static const struct intel_device_info intel_skylake_gt3_info = {
+        .is_preliminary = 1,
+        .is_skylake = 1,
+        .gen = 9, .num_pipes = 3,
+        .need_gfx_hws = 1, .has_hotplug = 1,
+        .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
+        .has_llc = 1,
+        .has_ddi = 1,
+        .has_fbc = 1,
+        GEN_DEFAULT_PIPEOFFSETS,
+        IVB_CURSOR_OFFSETS,
+};
+
 /*
  * Make sure any device matches here are from most specific to most
  * general.  For example, since the Quanta match is based on the subsystem
@@ -406,7 +419,9 @@ static const struct intel_device_info intel_skylake_info = {
         INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), \
         INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), \
         INTEL_CHV_IDS(&intel_cherryview_info),  \
-        INTEL_SKL_IDS(&intel_skylake_info)
+        INTEL_SKL_GT1_IDS(&intel_skylake_info), \
+        INTEL_SKL_GT2_IDS(&intel_skylake_info), \
+        INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info)      \
 
 static const struct pci_device_id pciidlist[] = {               /* aka */
         INTEL_PCI_IDS,
@@ -553,6 +568,7 @@ static int i915_drm_suspend(struct drm_device *dev)
         struct drm_i915_private *dev_priv = dev->dev_private;
         struct drm_crtc *crtc;
         pci_power_t opregion_target_state;
+        int error;
 
         /* ignore lid events during suspend */
         mutex_lock(&dev_priv->modeset_restore_lock);
@@ -567,37 +583,32 @@ static int i915_drm_suspend(struct drm_device *dev)
 
         pci_save_state(dev->pdev);
 
-        /* If KMS is active, we do the leavevt stuff here */
-        if (drm_core_check_feature(dev, DRIVER_MODESET)) {
-                int error;
-
-                error = i915_gem_suspend(dev);
-                if (error) {
-                        dev_err(&dev->pdev->dev,
-                                "GEM idle failed, resume might fail\n");
-                        return error;
-                }
+        error = i915_gem_suspend(dev);
+        if (error) {
+                dev_err(&dev->pdev->dev,
+                        "GEM idle failed, resume might fail\n");
+                return error;
+        }
 
-                intel_suspend_gt_powersave(dev);
+        intel_suspend_gt_powersave(dev);
 
-                /*
-                 * Disable CRTCs directly since we want to preserve sw state
-                 * for _thaw. Also, power gate the CRTC power wells.
-                 */
-                drm_modeset_lock_all(dev);
-                for_each_crtc(dev, crtc)
-                        intel_crtc_control(crtc, false);
-                drm_modeset_unlock_all(dev);
+        /*
+         * Disable CRTCs directly since we want to preserve sw state
+         * for _thaw. Also, power gate the CRTC power wells.
+         */
+        drm_modeset_lock_all(dev);
+        for_each_crtc(dev, crtc)
+                intel_crtc_control(crtc, false);
+        drm_modeset_unlock_all(dev);
 
-                intel_dp_mst_suspend(dev);
+        intel_dp_mst_suspend(dev);
 
-                intel_runtime_pm_disable_interrupts(dev_priv);
-                intel_hpd_cancel_work(dev_priv);
+        intel_runtime_pm_disable_interrupts(dev_priv);
+        intel_hpd_cancel_work(dev_priv);
 
-                intel_suspend_encoders(dev_priv);
+        intel_suspend_encoders(dev_priv);
 
-                intel_suspend_hw(dev);
-        }
+        intel_suspend_hw(dev);
 
         i915_gem_suspend_gtt_mappings(dev);
 
@@ -679,53 +690,48 @@ static int i915_drm_resume(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
 
-        if (drm_core_check_feature(dev, DRIVER_MODESET)) {
-                mutex_lock(&dev->struct_mutex);
-                i915_gem_restore_gtt_mappings(dev);
-                mutex_unlock(&dev->struct_mutex);
-        }
+        mutex_lock(&dev->struct_mutex);
+        i915_gem_restore_gtt_mappings(dev);
+        mutex_unlock(&dev->struct_mutex);
 
         i915_restore_state(dev);
         intel_opregion_setup(dev);
 
-        /* KMS EnterVT equivalent */
-        if (drm_core_check_feature(dev, DRIVER_MODESET)) {
-                intel_init_pch_refclk(dev);
-                drm_mode_config_reset(dev);
+        intel_init_pch_refclk(dev);
+        drm_mode_config_reset(dev);
 
-                mutex_lock(&dev->struct_mutex);
-                if (i915_gem_init_hw(dev)) {
-                        DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
-                        atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
-                }
-                mutex_unlock(&dev->struct_mutex);
+        mutex_lock(&dev->struct_mutex);
+        if (i915_gem_init_hw(dev)) {
+                DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
+                atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
+        }
+        mutex_unlock(&dev->struct_mutex);
 
-                /* We need working interrupts for modeset enabling ... */
-                intel_runtime_pm_enable_interrupts(dev_priv);
+        /* We need working interrupts for modeset enabling ... */
+        intel_runtime_pm_enable_interrupts(dev_priv);
 
-                intel_modeset_init_hw(dev);
+        intel_modeset_init_hw(dev);
 
-                spin_lock_irq(&dev_priv->irq_lock);
-                if (dev_priv->display.hpd_irq_setup)
-                        dev_priv->display.hpd_irq_setup(dev);
-                spin_unlock_irq(&dev_priv->irq_lock);
+        spin_lock_irq(&dev_priv->irq_lock);
+        if (dev_priv->display.hpd_irq_setup)
+                dev_priv->display.hpd_irq_setup(dev);
+        spin_unlock_irq(&dev_priv->irq_lock);
 
-                drm_modeset_lock_all(dev);
-                intel_modeset_setup_hw_state(dev, true);
-                drm_modeset_unlock_all(dev);
+        drm_modeset_lock_all(dev);
+        intel_modeset_setup_hw_state(dev, true);
+        drm_modeset_unlock_all(dev);
 
-                intel_dp_mst_resume(dev);
+        intel_dp_mst_resume(dev);
 
-                /*
-                 * ... but also need to make sure that hotplug processing
-                 * doesn't cause havoc. Like in the driver load code we don't
-                 * bother with the tiny race here where we might loose hotplug
-                 * notifications.
-                 * */
-                intel_hpd_init(dev_priv);
-                /* Config may have changed between suspend and resume */
-                drm_helper_hpd_irq_event(dev);
-        }
+        /*
+         * ... but also need to make sure that hotplug processing
+         * doesn't cause havoc. Like in the driver load code we don't
+         * bother with the tiny race here where we might loose hotplug
+         * notifications.
+         * */
+        intel_hpd_init(dev_priv);
+        /* Config may have changed between suspend and resume */
+        drm_helper_hpd_irq_event(dev);
 
         intel_opregion_init(dev);
 
@@ -861,38 +867,35 @@ int i915_reset(struct drm_device *dev)
          * was running at the time of the reset (i.e. we weren't VT
          * switched away).
          */
-        if (drm_core_check_feature(dev, DRIVER_MODESET)) {
-                /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
-                dev_priv->gpu_error.reload_in_reset = true;
 
-                ret = i915_gem_init_hw(dev);
+        /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
+        dev_priv->gpu_error.reload_in_reset = true;
 
-                dev_priv->gpu_error.reload_in_reset = false;
+        ret = i915_gem_init_hw(dev);
 
-                mutex_unlock(&dev->struct_mutex);
-                if (ret) {
-                        DRM_ERROR("Failed hw init on reset %d\n", ret);
-                        return ret;
-                }
-
-                /*
-                 * FIXME: This races pretty badly against concurrent holders of
-                 * ring interrupts. This is possible since we've started to drop
-                 * dev->struct_mutex in select places when waiting for the gpu.
-                 */
+        dev_priv->gpu_error.reload_in_reset = false;
 
-                /*
-                 * rps/rc6 re-init is necessary to restore state lost after the
-                 * reset and the re-install of gt irqs. Skip for ironlake per
-                 * previous concerns that it doesn't respond well to some forms
-                 * of re-init after reset.
-                 */
-                if (INTEL_INFO(dev)->gen > 5)
-                        intel_enable_gt_powersave(dev);
-        } else {
-                mutex_unlock(&dev->struct_mutex);
+        mutex_unlock(&dev->struct_mutex);
+        if (ret) {
+                DRM_ERROR("Failed hw init on reset %d\n", ret);
+                return ret;
         }
 
+        /*
+         * FIXME: This races pretty badly against concurrent holders of
+         * ring interrupts. This is possible since we've started to drop
+         * dev->struct_mutex in select places when waiting for the gpu.
+         */
+
+        /*
+         * rps/rc6 re-init is necessary to restore state lost after the
+         * reset and the re-install of gt irqs. Skip for ironlake per
+         * previous concerns that it doesn't respond well to some forms
+         * of re-init after reset.
+         */
+        if (INTEL_INFO(dev)->gen > 5)
+                intel_enable_gt_powersave(dev);
+
         return 0;
 }
 
@@ -1650,11 +1653,9 @@ static int __init i915_init(void)
 
         if (!(driver.driver_features & DRIVER_MODESET)) {
                 driver.get_vblank_timestamp = NULL;
-#ifndef CONFIG_DRM_I915_UMS
                 /* Silently fail loading to not upset userspace. */
                 DRM_DEBUG_DRIVER("KMS and UMS disabled.\n");
                 return 0;
-#endif
         }
 
         /*
@@ -1670,10 +1671,8 @@ static int __init i915_init(void)
 
 static void __exit i915_exit(void)
 {
-#ifndef CONFIG_DRM_I915_UMS
         if (!(driver.driver_features & DRIVER_MODESET))
                 return; /* Never loaded a driver. */
-#endif
 
         drm_pci_exit(&driver, &i915_pci_driver);
 }
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8727086cf48c..ee5bc43dfc0b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -31,6 +31,7 @@
 #define _I915_DRV_H_
 
 #include <uapi/drm/i915_drm.h>
+#include <uapi/drm/drm_fourcc.h>
 
 #include "i915_reg.h"
 #include "intel_bios.h"
@@ -55,7 +56,7 @@
 
 #define DRIVER_NAME             "i915"
 #define DRIVER_DESC             "Intel Graphics"
-#define DRIVER_DATE             "20150130"
+#define DRIVER_DATE             "20150227"
 
 #undef WARN_ON
 /* Many gcc seem to no see through this and fall over :( */
@@ -692,7 +693,18 @@ struct intel_device_info {
         int trans_offsets[I915_MAX_TRANSCODERS];
         int palette_offsets[I915_MAX_PIPES];
         int cursor_offsets[I915_MAX_PIPES];
-        unsigned int eu_total;
+
+        /* Slice/subslice/EU info */
+        u8 slice_total;
+        u8 subslice_total;
+        u8 subslice_per_slice;
+        u8 eu_total;
+        u8 eu_per_subslice;
+        /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
+        u8 subslice_7eu[3];
+        u8 has_slice_pg:1;
+        u8 has_subslice_pg:1;
+        u8 has_eu_pg:1;
 };
 
 #undef DEFINE_FLAG
@@ -772,10 +784,10 @@ struct intel_context {
 };
 
 struct i915_fbc {
-        unsigned long size;
+        unsigned long uncompressed_size;
         unsigned threshold;
         unsigned int fb_id;
-        enum plane plane;
+        struct intel_crtc *crtc;
         int y;
 
         struct drm_mm_node compressed_fb;
@@ -888,150 +900,21 @@ struct intel_gmbus {
 };
 
 struct i915_suspend_saved_registers {
-        u8 saveLBB;
-        u32 saveDSPACNTR;
-        u32 saveDSPBCNTR;
         u32 saveDSPARB;
-        u32 savePIPEACONF;
-        u32 savePIPEBCONF;
-        u32 savePIPEASRC;
-        u32 savePIPEBSRC;
-        u32 saveFPA0;
-        u32 saveFPA1;
-        u32 saveDPLL_A;
-        u32 saveDPLL_A_MD;
-        u32 saveHTOTAL_A;
-        u32 saveHBLANK_A;
-        u32 saveHSYNC_A;
-        u32 saveVTOTAL_A;
-        u32 saveVBLANK_A;
-        u32 saveVSYNC_A;
-        u32 saveBCLRPAT_A;
-        u32 saveTRANSACONF;
-        u32 saveTRANS_HTOTAL_A;
-        u32 saveTRANS_HBLANK_A;
-        u32 saveTRANS_HSYNC_A;
-        u32 saveTRANS_VTOTAL_A;
-        u32 saveTRANS_VBLANK_A;
-        u32 saveTRANS_VSYNC_A;
-        u32 savePIPEASTAT;
-        u32 saveDSPASTRIDE;
-        u32 saveDSPASIZE;
-        u32 saveDSPAPOS;
-        u32 saveDSPAADDR;
-        u32 saveDSPASURF;
-        u32 saveDSPATILEOFF;
-        u32 savePFIT_PGM_RATIOS;
-        u32 saveBLC_HIST_CTL;
-        u32 saveBLC_PWM_CTL;
-        u32 saveBLC_PWM_CTL2;
-        u32 saveBLC_CPU_PWM_CTL;
-        u32 saveBLC_CPU_PWM_CTL2;
-        u32 saveFPB0;
-        u32 saveFPB1;
-        u32 saveDPLL_B;
-        u32 saveDPLL_B_MD;
-        u32 saveHTOTAL_B;
-        u32 saveHBLANK_B;
-        u32 saveHSYNC_B;
-        u32 saveVTOTAL_B;
-        u32 saveVBLANK_B;
-        u32 saveVSYNC_B;
-        u32 saveBCLRPAT_B;
-        u32 saveTRANSBCONF;
-        u32 saveTRANS_HTOTAL_B;
-        u32 saveTRANS_HBLANK_B;
-        u32 saveTRANS_HSYNC_B;
-        u32 saveTRANS_VTOTAL_B;
-        u32 saveTRANS_VBLANK_B;
-        u32 saveTRANS_VSYNC_B;
-        u32 savePIPEBSTAT;
-        u32 saveDSPBSTRIDE;
-        u32 saveDSPBSIZE;
-        u32 saveDSPBPOS;
-        u32 saveDSPBADDR;
-        u32 saveDSPBSURF;
-        u32 saveDSPBTILEOFF;
-        u32 saveVGA0;
-        u32 saveVGA1;
-        u32 saveVGA_PD;
-        u32 saveVGACNTRL;
-        u32 saveADPA;
         u32 saveLVDS;
         u32 savePP_ON_DELAYS;
         u32 savePP_OFF_DELAYS;
-        u32 saveDVOA;
-        u32 saveDVOB;
-        u32 saveDVOC;
         u32 savePP_ON;
         u32 savePP_OFF;
         u32 savePP_CONTROL;
         u32 savePP_DIVISOR;
-        u32 savePFIT_CONTROL;
-        u32 save_palette_a[256];
-        u32 save_palette_b[256];
         u32 saveFBC_CONTROL;
-        u32 saveIER;
-        u32 saveIIR;
-        u32 saveIMR;
-        u32 saveDEIER;
-        u32 saveDEIMR;
-        u32 saveGTIER;
-        u32 saveGTIMR;
-        u32 saveFDI_RXA_IMR;
-        u32 saveFDI_RXB_IMR;
         u32 saveCACHE_MODE_0;
         u32 saveMI_ARB_STATE;
         u32 saveSWF0[16];
         u32 saveSWF1[16];
         u32 saveSWF2[3];
-        u8 saveMSR;
-        u8 saveSR[8];
-        u8 saveGR[25];
-        u8 saveAR_INDEX;
-        u8 saveAR[21];
-        u8 saveDACMASK;
-        u8 saveCR[37];
         uint64_t saveFENCE[I915_MAX_NUM_FENCES];
-        u32 saveCURACNTR;
-        u32 saveCURAPOS;
-        u32 saveCURABASE;
-        u32 saveCURBCNTR;
-        u32 saveCURBPOS;
-        u32 saveCURBBASE;
-        u32 saveCURSIZE;
-        u32 saveDP_B;
-        u32 saveDP_C;
-        u32 saveDP_D;
-        u32 savePIPEA_GMCH_DATA_M;
-        u32 savePIPEB_GMCH_DATA_M;
-        u32 savePIPEA_GMCH_DATA_N;
-        u32 savePIPEB_GMCH_DATA_N;
-        u32 savePIPEA_DP_LINK_M;
-        u32 savePIPEB_DP_LINK_M;
-        u32 savePIPEA_DP_LINK_N;
-        u32 savePIPEB_DP_LINK_N;
-        u32 saveFDI_RXA_CTL;
-        u32 saveFDI_TXA_CTL;
-        u32 saveFDI_RXB_CTL;
-        u32 saveFDI_TXB_CTL;
-        u32 savePFA_CTL_1;
-        u32 savePFB_CTL_1;
-        u32 savePFA_WIN_SZ;
-        u32 savePFB_WIN_SZ;
-        u32 savePFA_WIN_POS;
-        u32 savePFB_WIN_POS;
-        u32 savePCH_DREF_CONTROL;
-        u32 saveDISP_ARB_CTL;
-        u32 savePIPEA_DATA_M1;
-        u32 savePIPEA_DATA_N1;
-        u32 savePIPEA_LINK_M1;
-        u32 savePIPEA_LINK_N1;
-        u32 savePIPEB_DATA_M1;
-        u32 savePIPEB_DATA_N1;
-        u32 savePIPEB_LINK_M1;
-        u32 savePIPEB_LINK_N1;
-        u32 saveMCHBAR_RENDER_STANDBY;
         u32 savePCH_PORT_HOTPLUG;
         u16 saveGCDGMBUS;
 };
@@ -1454,6 +1337,7 @@ struct intel_vbt_data {
         bool edp_initialized;
         bool edp_support;
         int edp_bpp;
+        bool edp_low_vswing;
         struct edp_power_seq edp_pps;
 
         struct {
@@ -1640,6 +1524,10 @@ struct i915_workarounds {
         u32 count;
 };
 
+struct i915_virtual_gpu {
+        bool active;
+};
+
 struct drm_i915_private {
         struct drm_device *dev;
         struct kmem_cache *slab;
@@ -1652,6 +1540,8 @@ struct drm_i915_private {
 
         struct intel_uncore uncore;
 
+        struct i915_virtual_gpu vgpu;
+
         struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
 
 
@@ -2141,7 +2031,7 @@ struct drm_i915_gem_request {
         u32 tail;
 
         /**
-         * Context related to this request
+         * Context and ring buffer related to this request
          * Contexts are refcounted, so when this request is associated with a
          * context, we must increment the context's refcount, to guarantee that
          * it persists while any request is linked to it. Requests themselves
@@ -2151,6 +2041,7 @@ struct drm_i915_gem_request {
          * context.
          */
         struct intel_context *ctx;
+        struct intel_ringbuffer *ringbuf;
 
         /** Batch buffer related to this request if any */
         struct drm_i915_gem_object *batch_obj;
@@ -2165,6 +2056,9 @@ struct drm_i915_gem_request {
         /** file_priv list entry for this request */
         struct list_head client_list;
 
+        /** process identifier submitting this request */
+        struct pid *pid;
+
         uint32_t uniq;
 
         /**
@@ -2351,6 +2245,7 @@ struct drm_i915_cmd_table {
 })
 #define INTEL_INFO(p)   (&__I915__(p)->info)
 #define INTEL_DEVID(p)  (INTEL_INFO(p)->device_id)
+#define INTEL_REVID(p)  (__I915__(p)->dev->pdev->revision)
 
 #define IS_I830(dev)            (INTEL_DEVID(dev) == 0x3577)
 #define IS_845G(dev)            (INTEL_DEVID(dev) == 0x2562)
@@ -2373,9 +2268,6 @@ struct drm_i915_cmd_table {
 #define IS_IVB_GT1(dev)         (INTEL_DEVID(dev) == 0x0156 || \
                                  INTEL_DEVID(dev) == 0x0152 || \
                                  INTEL_DEVID(dev) == 0x015a)
-#define IS_SNB_GT1(dev)         (INTEL_DEVID(dev) == 0x0102 || \
-                                 INTEL_DEVID(dev) == 0x0106 || \
-                                 INTEL_DEVID(dev) == 0x010A)
 #define IS_VALLEYVIEW(dev)      (INTEL_INFO(dev)->is_valleyview)
 #define IS_CHERRYVIEW(dev)      (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
@@ -2399,6 +2291,12 @@ struct drm_i915_cmd_table {
                                  INTEL_DEVID(dev) == 0x0A1E)
 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
 
+#define SKL_REVID_A0            (0x0)
+#define SKL_REVID_B0            (0x1)
+#define SKL_REVID_C0            (0x2)
+#define SKL_REVID_D0            (0x3)
+#define SKL_REVID_E0            (0x4)
+
 /*
  * The genX designation typically refers to the render engine, so render
  * capability related checks should use IS_GEN, while display and other checks
@@ -2506,8 +2404,6 @@ extern int i915_max_ioctl;
 
 extern int i915_suspend_legacy(struct drm_device *dev, pm_message_t state);
 extern int i915_resume_legacy(struct drm_device *dev);
-extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
-extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
 
 /* i915_params.c */
 struct i915_params {
@@ -2590,6 +2486,10 @@ void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
                                 enum forcewake_domains domains);
 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
+static inline bool intel_vgpu_active(struct drm_device *dev)
+{
+        return to_i915(dev)->vgpu.active;
+}
 
 void
 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
@@ -3120,10 +3020,6 @@ int i915_parse_cmds(struct intel_engine_cs *ring,
 extern int i915_save_state(struct drm_device *dev);
 extern int i915_restore_state(struct drm_device *dev);
 
-/* i915_ums.c */
-void i915_save_display_reg(struct drm_device *dev);
-void i915_restore_display_reg(struct drm_device *dev);
-
 /* i915_sysfs.c */
 void i915_setup_sysfs(struct drm_device *dev_priv);
 void i915_teardown_sysfs(struct drm_device *dev_priv);
@@ -3195,8 +3091,7 @@ extern void i915_redisable_vga(struct drm_device *dev);
 extern void i915_redisable_vga_power_on(struct drm_device *dev);
 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
 extern void intel_init_pch_refclk(struct drm_device *dev);
-extern void gen6_set_rps(struct drm_device *dev, u8 val);
-extern void valleyview_set_rps(struct drm_device *dev, u8 val);
+extern void intel_set_rps(struct drm_device *dev, u8 val);
 extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
                                   bool enable);
 extern void intel_detect_pch(struct drm_device *dev);
@@ -3209,8 +3104,6 @@ int i915_reg_read_ioctl(struct drm_device *dev, void *data,
 int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
                                struct drm_file *file);
 
-void intel_notify_mmio_flip(struct intel_engine_cs *ring);
-
 /* overlay */
 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index e5daad5f75fb..0107c2ae77d0 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -29,6 +29,7 @@
 #include <drm/drm_vma_manager.h>
 #include <drm/i915_drm.h>
 #include "i915_drv.h"
+#include "i915_vgpu.h"
 #include "i915_trace.h"
 #include "intel_drv.h"
 #include <linux/oom.h>
@@ -2492,6 +2493,8 @@ int __i915_add_request(struct intel_engine_cs *ring,
                 list_add_tail(&request->client_list,
                               &file_priv->mm.request_list);
                 spin_unlock(&file_priv->mm.lock);
+
+                request->pid = get_pid(task_pid(current));
         }
 
         trace_i915_gem_request_add(request);
@@ -2572,6 +2575,8 @@ static void i915_gem_free_request(struct drm_i915_gem_request *request)
         list_del(&request->list);
         i915_gem_request_remove_from_client(request);
 
+        put_pid(request->pid);
+
         i915_gem_request_unreference(request);
 }
 
@@ -2757,7 +2762,6 @@ i915_gem_retire_requests_ring(struct intel_engine_cs *ring)
 
         while (!list_empty(&ring->request_list)) {
                 struct drm_i915_gem_request *request;
-                struct intel_ringbuffer *ringbuf;
 
                 request = list_first_entry(&ring->request_list,
                                            struct drm_i915_gem_request,
@@ -2768,23 +2772,12 @@ i915_gem_retire_requests_ring(struct intel_engine_cs *ring)
 
                 trace_i915_gem_request_retire(request);
 
-                /* This is one of the few common intersection points
-                 * between legacy ringbuffer submission and execlists:
-                 * we need to tell them apart in order to find the correct
-                 * ringbuffer to which the request belongs to.
-                 */
-                if (i915.enable_execlists) {
-                        struct intel_context *ctx = request->ctx;
-                        ringbuf = ctx->engine[ring->id].ringbuf;
-                } else
-                        ringbuf = ring->buffer;
-
                 /* We know the GPU must have read the request to have
                  * sent us the seqno + interrupt, so use the position
                  * of tail of the request to update the last known position
                  * of the GPU head.
                  */
-                ringbuf->last_retired_head = request->postfix;
+                request->ringbuf->last_retired_head = request->postfix;
 
                 i915_gem_free_request(request);
         }
@@ -4232,7 +4225,7 @@ i915_gem_object_pin_view(struct drm_i915_gem_object *obj,
                 fenceable = (vma->node.size == fence_size &&
                              (vma->node.start & (fence_alignment - 1)) == 0);
 
-                mappable = (vma->node.start + obj->base.size <=
+                mappable = (vma->node.start + fence_size <=
                             dev_priv->gtt.mappable_end);
 
                 obj->map_and_fenceable = mappable && fenceable;
@@ -4607,10 +4600,6 @@ i915_gem_suspend(struct drm_device *dev)
 
         i915_gem_retire_requests(dev);
 
-        /* Under UMS, be paranoid and evict. */
-        if (!drm_core_check_feature(dev, DRIVER_MODESET))
-                i915_gem_evict_everything(dev);
-
         i915_gem_stop_ringbuffers(dev);
         mutex_unlock(&dev->struct_mutex);
 
@@ -4967,18 +4956,8 @@ i915_gem_load(struct drm_device *dev)
                           i915_gem_idle_work_handler);
         init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
 
-        /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
-        if (!drm_core_check_feature(dev, DRIVER_MODESET) && IS_GEN3(dev)) {
-                I915_WRITE(MI_ARB_STATE,
-                           _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
-        }
-
         dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
 
-        /* Old X drivers will take 0-2 for front, back, depth buffers */
-        if (!drm_core_check_feature(dev, DRIVER_MODESET))
-                dev_priv->fence_reg_start = 3;
-
         if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
                 dev_priv->num_fence_regs = 32;
         else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
@@ -4986,6 +4965,10 @@ i915_gem_load(struct drm_device *dev)
         else
                 dev_priv->num_fence_regs = 8;
 
+        if (intel_vgpu_active(dev))
+                dev_priv->num_fence_regs =
+                                I915_READ(vgtif_reg(avail_rs.fence_num));
+
         /* Initialize fence registers to zero */
         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
         i915_gem_restore_fences(dev);
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 8603bf48d3ee..70346b0028f9 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -296,11 +296,15 @@ void i915_gem_context_reset(struct drm_device *dev)
         struct drm_i915_private *dev_priv = dev->dev_private;
         int i;
 
-        /* In execlists mode we will unreference the context when the execlist
-         * queue is cleared and the requests destroyed.
-         */
-        if (i915.enable_execlists)
+        if (i915.enable_execlists) {
+                struct intel_context *ctx;
+
+                list_for_each_entry(ctx, &dev_priv->context_list, link) {
+                        intel_lr_context_reset(dev, ctx);
+                }
+
                 return;
+        }
 
         for (i = 0; i < I915_NUM_RINGS; i++) {
                 struct intel_engine_cs *ring = &dev_priv->ring[i];
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index b773368fc62c..85a6adaba258 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1076,16 +1076,15 @@ i915_gem_execbuffer_parse(struct intel_engine_cs *ring,
                           struct drm_i915_gem_object *batch_obj,
                           u32 batch_start_offset,
                           u32 batch_len,
-                          bool is_master,
-                          u32 *flags)
+                          bool is_master)
 {
         struct drm_i915_private *dev_priv = to_i915(batch_obj->base.dev);
         struct drm_i915_gem_object *shadow_batch_obj;
-        bool need_reloc = false;
+        struct i915_vma *vma;
         int ret;
 
         shadow_batch_obj = i915_gem_batch_pool_get(&dev_priv->mm.batch_pool,
-                                                   batch_obj->base.size);
+                                                   PAGE_ALIGN(batch_len));
         if (IS_ERR(shadow_batch_obj))
                 return shadow_batch_obj;
 
@@ -1095,40 +1094,30 @@ i915_gem_execbuffer_parse(struct intel_engine_cs *ring,
                               batch_start_offset,
                               batch_len,
                               is_master);
-        if (ret) {
-                if (ret == -EACCES)
-                        return batch_obj;
-        } else {
-                struct i915_vma *vma;
+        if (ret)
+                goto err;
 
-                memset(shadow_exec_entry, 0, sizeof(*shadow_exec_entry));
+        ret = i915_gem_obj_ggtt_pin(shadow_batch_obj, 0, 0);
+        if (ret)
+                goto err;
 
-                vma = i915_gem_obj_to_ggtt(shadow_batch_obj);
-                vma->exec_entry = shadow_exec_entry;
-                vma->exec_entry->flags = __EXEC_OBJECT_PURGEABLE;
-                drm_gem_object_reference(&shadow_batch_obj->base);
-                i915_gem_execbuffer_reserve_vma(vma, ring, &need_reloc);
-                list_add_tail(&vma->exec_list, &eb->vmas);
+        memset(shadow_exec_entry, 0, sizeof(*shadow_exec_entry));
 
-                shadow_batch_obj->base.pending_read_domains =
-                        batch_obj->base.pending_read_domains;
+        vma = i915_gem_obj_to_ggtt(shadow_batch_obj);
+        vma->exec_entry = shadow_exec_entry;
+        vma->exec_entry->flags = __EXEC_OBJECT_PURGEABLE | __EXEC_OBJECT_HAS_PIN;
+        drm_gem_object_reference(&shadow_batch_obj->base);
+        list_add_tail(&vma->exec_list, &eb->vmas);
 
-                /*
-                 * Set the DISPATCH_SECURE bit to remove the NON_SECURE
-                 * bit from MI_BATCH_BUFFER_START commands issued in the
-                 * dispatch_execbuffer implementations. We specifically
-                 * don't want that set when the command parser is
-                 * enabled.
-                 *
-                 * FIXME: with aliasing ppgtt, buffers that should only
-                 * be in ggtt still end up in the aliasing ppgtt. remove
-                 * this check when that is fixed.
-                 */
-                if (USES_FULL_PPGTT(dev))
-                        *flags |= I915_DISPATCH_SECURE;
-        }
+        shadow_batch_obj->base.pending_read_domains = I915_GEM_DOMAIN_COMMAND;
+
+        return shadow_batch_obj;
 
-        return ret ? ERR_PTR(ret) : shadow_batch_obj;
+err:
+        if (ret == -EACCES) /* unhandled chained batch */
+                return batch_obj;
+        else
+                return ERR_PTR(ret);
 }
 
 int
@@ -1138,7 +1127,7 @@ i915_gem_ringbuffer_submission(struct drm_device *dev, struct drm_file *file,
                                struct drm_i915_gem_execbuffer2 *args,
                                struct list_head *vmas,
                                struct drm_i915_gem_object *batch_obj,
-                               u64 exec_start, u32 flags)
+                               u64 exec_start, u32 dispatch_flags)
 {
         struct drm_clip_rect *cliprects = NULL;
         struct drm_i915_private *dev_priv = dev->dev_private;
@@ -1266,19 +1255,19 @@ i915_gem_ringbuffer_submission(struct drm_device *dev, struct drm_file *file,
 
                         ret = ring->dispatch_execbuffer(ring,
                                                         exec_start, exec_len,
-                                                        flags);
+                                                        dispatch_flags);
                         if (ret)
                                 goto error;
                 }
         } else {
                 ret = ring->dispatch_execbuffer(ring,
                                                 exec_start, exec_len,
-                                                flags);
+                                                dispatch_flags);
                 if (ret)
                         return ret;
         }
 
-        trace_i915_gem_ring_dispatch(intel_ring_get_request(ring), flags);
+        trace_i915_gem_ring_dispatch(intel_ring_get_request(ring), dispatch_flags);
 
         i915_gem_execbuffer_move_to_active(vmas, ring);
         i915_gem_execbuffer_retire_commands(dev, file, ring, batch_obj);
@@ -1353,7 +1342,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
         struct i915_address_space *vm;
         const u32 ctx_id = i915_execbuffer2_get_context_id(*args);
         u64 exec_start = args->batch_start_offset;
-        u32 flags;
+        u32 dispatch_flags;
         int ret;
         bool need_relocs;
 
@@ -1364,15 +1353,15 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
         if (ret)
                 return ret;
 
-        flags = 0;
+        dispatch_flags = 0;
         if (args->flags & I915_EXEC_SECURE) {
                 if (!file->is_master || !capable(CAP_SYS_ADMIN))
                     return -EPERM;
 
-                flags |= I915_DISPATCH_SECURE;
+                dispatch_flags |= I915_DISPATCH_SECURE;
         }
         if (args->flags & I915_EXEC_IS_PINNED)
-                flags |= I915_DISPATCH_PINNED;
+                dispatch_flags |= I915_DISPATCH_PINNED;
 
         if ((args->flags & I915_EXEC_RING_MASK) > LAST_USER_RING) {
                 DRM_DEBUG("execbuf with unknown ring: %d\n",
@@ -1494,12 +1483,27 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
                                                       batch_obj,
                                                       args->batch_start_offset,
                                                       args->batch_len,
-                                                      file->is_master,
-                                                      &flags);
+                                                      file->is_master);
                 if (IS_ERR(batch_obj)) {
                         ret = PTR_ERR(batch_obj);
                         goto err;
                 }
+
+                /*
+                 * Set the DISPATCH_SECURE bit to remove the NON_SECURE
+                 * bit from MI_BATCH_BUFFER_START commands issued in the
+                 * dispatch_execbuffer implementations. We specifically
+                 * don't want that set when the command parser is
+                 * enabled.
+                 *
+                 * FIXME: with aliasing ppgtt, buffers that should only
+                 * be in ggtt still end up in the aliasing ppgtt. remove
+                 * this check when that is fixed.
+                 */
+                if (USES_FULL_PPGTT(dev))
+                        dispatch_flags |= I915_DISPATCH_SECURE;
+
+                exec_start = 0;
         }
 
         batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
@@ -1507,7 +1511,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
         /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
          * batch" bit. Hence we need to pin secure batches into the global gtt.
          * hsw should have this fixed, but bdw mucks it up again. */
-        if (flags & I915_DISPATCH_SECURE) {
+        if (dispatch_flags & I915_DISPATCH_SECURE) {
                 /*
                  * So on first glance it looks freaky that we pin the batch here
                  * outside of the reservation loop. But:
@@ -1527,7 +1531,8 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
                 exec_start += i915_gem_obj_offset(batch_obj, vm);
 
         ret = dev_priv->gt.do_execbuf(dev, file, ring, ctx, args,
-                                      &eb->vmas, batch_obj, exec_start, flags);
+                                      &eb->vmas, batch_obj, exec_start,
+                                      dispatch_flags);
 
         /*
          * FIXME: We crucially rely upon the active tracking for the (ppgtt)
@@ -1535,7 +1540,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
          * needs to be adjusted to also track the ggtt batch vma properly as
          * active.
          */
-        if (flags & I915_DISPATCH_SECURE)
+        if (dispatch_flags & I915_DISPATCH_SECURE)
                 i915_gem_object_ggtt_unpin(batch_obj);
 err:
         /* the request owns the ref now */
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index dccdc8aad2e2..74df3d1581dd 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -27,6 +27,7 @@
 #include <drm/drmP.h>
 #include <drm/i915_drm.h>
 #include "i915_drv.h"
+#include "i915_vgpu.h"
 #include "i915_trace.h"
 #include "intel_drv.h"
 
@@ -103,6 +104,9 @@ static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
         has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6;
         has_full_ppgtt = INTEL_INFO(dev)->gen >= 7;
 
+        if (intel_vgpu_active(dev))
+                has_full_ppgtt = false; /* emulation is too hard */
+
         /*
          * We don't allow disabling PPGTT for gen9+ as it's a requirement for
          * execlists, the sole mechanism available to submit work.
@@ -138,7 +142,6 @@ static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
                 return has_aliasing_ppgtt ? 1 : 0;
 }
 
-
 static void ppgtt_bind_vma(struct i915_vma *vma,
                            enum i915_cache_level cache_level,
                            u32 flags);
@@ -275,6 +278,100 @@ static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr,
         return pte;
 }
 
+static void unmap_and_free_pt(struct i915_page_table_entry *pt, struct drm_device *dev)
+{
+        if (WARN_ON(!pt->page))
+                return;
+        __free_page(pt->page);
+        kfree(pt);
+}
+
+static struct i915_page_table_entry *alloc_pt_single(struct drm_device *dev)
+{
+        struct i915_page_table_entry *pt;
+
+        pt = kzalloc(sizeof(*pt), GFP_KERNEL);
+        if (!pt)
+                return ERR_PTR(-ENOMEM);
+
+        pt->page = alloc_page(GFP_KERNEL | __GFP_ZERO);
+        if (!pt->page) {
+                kfree(pt);
+                return ERR_PTR(-ENOMEM);
+        }
+
+        return pt;
+}
+
+/**
+ * alloc_pt_range() - Allocate a multiple page tables
+ * @pd:         The page directory which will have at least @count entries
+ *              available to point to the allocated page tables.
+ * @pde:        First page directory entry for which we are allocating.
+ * @count:      Number of pages to allocate.
+ * @dev:        DRM device.
+ *
+ * Allocates multiple page table pages and sets the appropriate entries in the
+ * page table structure within the page directory. Function cleans up after
+ * itself on any failures.
+ *
+ * Return: 0 if allocation succeeded.
+ */
+static int alloc_pt_range(struct i915_page_directory_entry *pd, uint16_t pde, size_t count,
+                  struct drm_device *dev)
+{
+        int i, ret;
+
+        /* 512 is the max page tables per page_directory on any platform. */
+        if (WARN_ON(pde + count > GEN6_PPGTT_PD_ENTRIES))
+                return -EINVAL;
+
+        for (i = pde; i < pde + count; i++) {
+                struct i915_page_table_entry *pt = alloc_pt_single(dev);
+
+                if (IS_ERR(pt)) {
+                        ret = PTR_ERR(pt);
+                        goto err_out;
+                }
+                WARN(pd->page_table[i],
+                     "Leaking page directory entry %d (%p)\n",
+                     i, pd->page_table[i]);
+                pd->page_table[i] = pt;
+        }
+
+        return 0;
+
+err_out:
+        while (i-- > pde)
+                unmap_and_free_pt(pd->page_table[i], dev);
+        return ret;
+}
+
+static void unmap_and_free_pd(struct i915_page_directory_entry *pd)
+{
+        if (pd->page) {
+                __free_page(pd->page);
+                kfree(pd);
+        }
+}
+
+static struct i915_page_directory_entry *alloc_pd_single(void)
+{
+        struct i915_page_directory_entry *pd;
+
+        pd = kzalloc(sizeof(*pd), GFP_KERNEL);
+        if (!pd)
+                return ERR_PTR(-ENOMEM);
+
+        pd->page = alloc_page(GFP_KERNEL | __GFP_ZERO);
+        if (!pd->page) {
+                kfree(pd);
+                return ERR_PTR(-ENOMEM);
+        }
+
+        return pd;
+}
+
 /* Broadwell Page Directory Pointer Descriptors */
 static int gen8_write_pdp(struct intel_engine_cs *ring, unsigned entry,
                            uint64_t val)
@@ -307,7 +404,7 @@ static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt,
         int used_pd = ppgtt->num_pd_entries / GEN8_PDES_PER_PAGE;
 
         for (i = used_pd - 1; i >= 0; i--) {
-                dma_addr_t addr = ppgtt->pd_dma_addr[i];
+                dma_addr_t addr = ppgtt->pdp.page_directory[i]->daddr;
                 ret = gen8_write_pdp(ring, i, addr);
                 if (ret)
                         return ret;
@@ -334,7 +431,24 @@ static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
                                       I915_CACHE_LLC, use_scratch);
 
         while (num_entries) {
-                struct page *page_table = ppgtt->gen8_pt_pages[pdpe][pde];
+                struct i915_page_directory_entry *pd;
+                struct i915_page_table_entry *pt;
+                struct page *page_table;
+
+                if (WARN_ON(!ppgtt->pdp.page_directory[pdpe]))
+                        continue;
+
+                pd = ppgtt->pdp.page_directory[pdpe];
+
+                if (WARN_ON(!pd->page_table[pde]))
+                        continue;
+
+                pt = pd->page_table[pde];
+
+                if (WARN_ON(!pt->page))
+                        continue;
+
+                page_table = pt->page;
 
                 last_pte = pte + num_entries;
                 if (last_pte > GEN8_PTES_PER_PAGE)
@@ -375,11 +489,16 @@ static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
         pt_vaddr = NULL;
 
         for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
-                if (WARN_ON(pdpe >= GEN8_LEGACY_PDPS))
+                if (WARN_ON(pdpe >= GEN8_LEGACY_PDPES))
                         break;
 
-                if (pt_vaddr == NULL)
-                        pt_vaddr = kmap_atomic(ppgtt->gen8_pt_pages[pdpe][pde]);
+                if (pt_vaddr == NULL) {
+                        struct i915_page_directory_entry *pd = ppgtt->pdp.page_directory[pdpe];
+                        struct i915_page_table_entry *pt = pd->page_table[pde];
+                        struct page *page_table = pt->page;
+
+                        pt_vaddr = kmap_atomic(page_table);
+                }
 
                 pt_vaddr[pte] =
                         gen8_pte_encode(sg_page_iter_dma_address(&sg_iter),
@@ -403,29 +522,33 @@ static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
         }
 }
 
-static void gen8_free_page_tables(struct page **pt_pages)
+static void gen8_free_page_tables(struct i915_page_directory_entry *pd, struct drm_device *dev)
 {
         int i;
 
-        if (pt_pages == NULL)
+        if (!pd->page)
                 return;
 
-        for (i = 0; i < GEN8_PDES_PER_PAGE; i++)
-                if (pt_pages[i])
-                        __free_pages(pt_pages[i], 0);
+        for (i = 0; i < GEN8_PDES_PER_PAGE; i++) {
+                if (WARN_ON(!pd->page_table[i]))
+                        continue;
+
+                unmap_and_free_pt(pd->page_table[i], dev);
+                pd->page_table[i] = NULL;
+        }
 }
 
-static void gen8_ppgtt_free(const struct i915_hw_ppgtt *ppgtt)
+static void gen8_ppgtt_free(struct i915_hw_ppgtt *ppgtt)
 {
         int i;
 
         for (i = 0; i < ppgtt->num_pd_pages; i++) {
-                gen8_free_page_tables(ppgtt->gen8_pt_pages[i]);
-                kfree(ppgtt->gen8_pt_pages[i]);
-                kfree(ppgtt->gen8_pt_dma_addr[i]);
-        }
+                if (WARN_ON(!ppgtt->pdp.page_directory[i]))
+                        continue;
 
-        __free_pages(ppgtt->pd_pages, get_order(ppgtt->num_pd_pages << PAGE_SHIFT));
+                gen8_free_page_tables(ppgtt->pdp.page_directory[i], ppgtt->base.dev);
+                unmap_and_free_pd(ppgtt->pdp.page_directory[i]);
+        }
 }
 
 static void gen8_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt)
@@ -436,14 +559,23 @@ static void gen8_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt)
         for (i = 0; i < ppgtt->num_pd_pages; i++) {
                 /* TODO: In the future we'll support sparse mappings, so this
                  * will have to change. */
-                if (!ppgtt->pd_dma_addr[i])
+                if (!ppgtt->pdp.page_directory[i]->daddr)
                         continue;
 
-                pci_unmap_page(hwdev, ppgtt->pd_dma_addr[i], PAGE_SIZE,
+                pci_unmap_page(hwdev, ppgtt->pdp.page_directory[i]->daddr, PAGE_SIZE,
                                PCI_DMA_BIDIRECTIONAL);
 
                 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
-                        dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j];
+                        struct i915_page_directory_entry *pd = ppgtt->pdp.page_directory[i];
+                        struct i915_page_table_entry *pt;
+                        dma_addr_t addr;
+
+                        if (WARN_ON(!pd->page_table[j]))
+                                continue;
+
+                        pt = pd->page_table[j];
+                        addr = pt->daddr;
+
                         if (addr)
                                 pci_unmap_page(hwdev, addr, PAGE_SIZE,
                                                PCI_DMA_BIDIRECTIONAL);
@@ -460,86 +592,47 @@ static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
         gen8_ppgtt_free(ppgtt);
 }
 
-static struct page **__gen8_alloc_page_tables(void)
+static int gen8_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt)
 {
-        struct page **pt_pages;
-        int i;
-
-        pt_pages = kcalloc(GEN8_PDES_PER_PAGE, sizeof(struct page *), GFP_KERNEL);
-        if (!pt_pages)
-                return ERR_PTR(-ENOMEM);
-
-        for (i = 0; i < GEN8_PDES_PER_PAGE; i++) {
-                pt_pages[i] = alloc_page(GFP_KERNEL);
-                if (!pt_pages[i])
-                        goto bail;
-        }
-
-        return pt_pages;
-
-bail:
-        gen8_free_page_tables(pt_pages);
-        kfree(pt_pages);
-        return ERR_PTR(-ENOMEM);
-}
-
-static int gen8_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt,
-                                           const int max_pdp)
-{
-        struct page **pt_pages[GEN8_LEGACY_PDPS];
         int i, ret;
 
-        for (i = 0; i < max_pdp; i++) {
-                pt_pages[i] = __gen8_alloc_page_tables();
-                if (IS_ERR(pt_pages[i])) {
-                        ret = PTR_ERR(pt_pages[i]);
+        for (i = 0; i < ppgtt->num_pd_pages; i++) {
+                ret = alloc_pt_range(ppgtt->pdp.page_directory[i],
+                                     0, GEN8_PDES_PER_PAGE, ppgtt->base.dev);
+                if (ret)
                         goto unwind_out;
-                }
         }
 
-        /* NB: Avoid touching gen8_pt_pages until last to keep the allocation,
-         * "atomic" - for cleanup purposes.
-         */
-        for (i = 0; i < max_pdp; i++)
-                ppgtt->gen8_pt_pages[i] = pt_pages[i];
-
         return 0;
 
 unwind_out:
-        while (i--) {
-                gen8_free_page_tables(pt_pages[i]);
-                kfree(pt_pages[i]);
-        }
+        while (i--)
+                gen8_free_page_tables(ppgtt->pdp.page_directory[i], ppgtt->base.dev);
 
-        return ret;
+        return -ENOMEM;
 }
 
-static int gen8_ppgtt_allocate_dma(struct i915_hw_ppgtt *ppgtt)
+static int gen8_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt,
+                                                const int max_pdp)
 {
         int i;
 
-        for (i = 0; i < ppgtt->num_pd_pages; i++) {
-                ppgtt->gen8_pt_dma_addr[i] = kcalloc(GEN8_PDES_PER_PAGE,
-                                                     sizeof(dma_addr_t),
-                                                     GFP_KERNEL);
-                if (!ppgtt->gen8_pt_dma_addr[i])
-                        return -ENOMEM;
+        for (i = 0; i < max_pdp; i++) {
+                ppgtt->pdp.page_directory[i] = alloc_pd_single();
+                if (IS_ERR(ppgtt->pdp.page_directory[i]))
+                        goto unwind_out;
         }
 
-        return 0;
-}
+        ppgtt->num_pd_pages = max_pdp;
+        BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPES);
 
-static int gen8_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt,
-                                                const int max_pdp)
-{
-        ppgtt->pd_pages = alloc_pages(GFP_KERNEL, get_order(max_pdp << PAGE_SHIFT));
-        if (!ppgtt->pd_pages)
-                return -ENOMEM;
+        return 0;
 
-        ppgtt->num_pd_pages = 1 << get_order(max_pdp << PAGE_SHIFT);
-        BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPS);
+unwind_out:
+        while (i--)
+                unmap_and_free_pd(ppgtt->pdp.page_directory[i]);
 
-        return 0;
+        return -ENOMEM;
 }
 
 static int gen8_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt,
@@ -551,18 +644,16 @@ static int gen8_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt,
         if (ret)
                 return ret;
 
-        ret = gen8_ppgtt_allocate_page_tables(ppgtt, max_pdp);
-        if (ret) {
-                __free_pages(ppgtt->pd_pages, get_order(max_pdp << PAGE_SHIFT));
-                return ret;
-        }
+        ret = gen8_ppgtt_allocate_page_tables(ppgtt);
+        if (ret)
+                goto err_out;
 
         ppgtt->num_pd_entries = max_pdp * GEN8_PDES_PER_PAGE;
 
-        ret = gen8_ppgtt_allocate_dma(ppgtt);
-        if (ret)
-                gen8_ppgtt_free(ppgtt);
+        return 0;
 
+err_out:
+        gen8_ppgtt_free(ppgtt);
         return ret;
 }
 
@@ -573,14 +664,14 @@ static int gen8_ppgtt_setup_page_directories(struct i915_hw_ppgtt *ppgtt,
         int ret;
 
         pd_addr = pci_map_page(ppgtt->base.dev->pdev,
-                               &ppgtt->pd_pages[pd], 0,
+                               ppgtt->pdp.page_directory[pd]->page, 0,
                                PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 
         ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pd_addr);
         if (ret)
                 return ret;
 
-        ppgtt->pd_dma_addr[pd] = pd_addr;
+        ppgtt->pdp.page_directory[pd]->daddr = pd_addr;
 
         return 0;
 }
@@ -590,17 +681,18 @@ static int gen8_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt,
                                         const int pt)
 {
         dma_addr_t pt_addr;
-        struct page *p;
+        struct i915_page_directory_entry *pdir = ppgtt->pdp.page_directory[pd];
+        struct i915_page_table_entry *ptab = pdir->page_table[pt];
+        struct page *p = ptab->page;
         int ret;
 
-        p = ppgtt->gen8_pt_pages[pd][pt];
         pt_addr = pci_map_page(ppgtt->base.dev->pdev,
                                p, 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
         ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pt_addr);
         if (ret)
                 return ret;
 
-        ppgtt->gen8_pt_dma_addr[pd][pt] = pt_addr;
+        ptab->daddr = pt_addr;
 
         return 0;
 }
@@ -653,10 +745,12 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size)
          * will never need to touch the PDEs again.
          */
         for (i = 0; i < max_pdp; i++) {
+                struct i915_page_directory_entry *pd = ppgtt->pdp.page_directory[i];
                 gen8_ppgtt_pde_t *pd_vaddr;
-                pd_vaddr = kmap_atomic(&ppgtt->pd_pages[i]);
+                pd_vaddr = kmap_atomic(ppgtt->pdp.page_directory[i]->page);
                 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
-                        dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j];
+                        struct i915_page_table_entry *pt = pd->page_table[j];
+                        dma_addr_t addr = pt->daddr;
                         pd_vaddr[j] = gen8_pde_encode(ppgtt->base.dev, addr,
                                                       I915_CACHE_LLC);
                 }
@@ -699,14 +793,15 @@ static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
         scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0);
 
         pd_addr = (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm +
-                ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
+                ppgtt->pd.pd_offset / sizeof(gen6_gtt_pte_t);
 
         seq_printf(m, "  VM %p (pd_offset %x-%x):\n", vm,
-                   ppgtt->pd_offset, ppgtt->pd_offset + ppgtt->num_pd_entries);
+                   ppgtt->pd.pd_offset,
+                   ppgtt->pd.pd_offset + ppgtt->num_pd_entries);
         for (pde = 0; pde < ppgtt->num_pd_entries; pde++) {
                 u32 expected;
                 gen6_gtt_pte_t *pt_vaddr;
-                dma_addr_t pt_addr = ppgtt->pt_dma_addr[pde];
+                dma_addr_t pt_addr = ppgtt->pd.page_table[pde]->daddr;
                 pd_entry = readl(pd_addr + pde);
                 expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
 
@@ -717,7 +812,7 @@ static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
                                    expected);
                 seq_printf(m, "\tPDE: %x\n", pd_entry);
 
-                pt_vaddr = kmap_atomic(ppgtt->pt_pages[pde]);
+                pt_vaddr = kmap_atomic(ppgtt->pd.page_table[pde]->page);
                 for (pte = 0; pte < I915_PPGTT_PT_ENTRIES; pte+=4) {
                         unsigned long va =
                                 (pde * PAGE_SIZE * I915_PPGTT_PT_ENTRIES) +
@@ -750,13 +845,13 @@ static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt)
         uint32_t pd_entry;
         int i;
 
-        WARN_ON(ppgtt->pd_offset & 0x3f);
+        WARN_ON(ppgtt->pd.pd_offset & 0x3f);
         pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm +
-                ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
+                ppgtt->pd.pd_offset / sizeof(gen6_gtt_pte_t);
         for (i = 0; i < ppgtt->num_pd_entries; i++) {
                 dma_addr_t pt_addr;
 
-                pt_addr = ppgtt->pt_dma_addr[i];
+                pt_addr = ppgtt->pd.page_table[i]->daddr;
                 pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
                 pd_entry |= GEN6_PDE_VALID;
 
@@ -767,9 +862,9 @@ static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt)
 
 static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
 {
-        BUG_ON(ppgtt->pd_offset & 0x3f);
+        BUG_ON(ppgtt->pd.pd_offset & 0x3f);
 
-        return (ppgtt->pd_offset / 64) << 16;
+        return (ppgtt->pd.pd_offset / 64) << 16;
 }
 
 static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
@@ -797,6 +892,16 @@ static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
         return 0;
 }
 
+static int vgpu_mm_switch(struct i915_hw_ppgtt *ppgtt,
+                          struct intel_engine_cs *ring)
+{
+        struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev);
+
+        I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
+        I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
+        return 0;
+}
+
 static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
                           struct intel_engine_cs *ring)
 {
@@ -922,7 +1027,7 @@ static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
                 if (last_pte > I915_PPGTT_PT_ENTRIES)
                         last_pte = I915_PPGTT_PT_ENTRIES;
 
-                pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
+                pt_vaddr = kmap_atomic(ppgtt->pd.page_table[act_pt]->page);
 
                 for (i = first_pte; i < last_pte; i++)
                         pt_vaddr[i] = scratch_pte;
@@ -951,7 +1056,7 @@ static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
         pt_vaddr = NULL;
         for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
                 if (pt_vaddr == NULL)
-                        pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
+                        pt_vaddr = kmap_atomic(ppgtt->pd.page_table[act_pt]->page);
 
                 pt_vaddr[act_pte] =
                         vm->pte_encode(sg_page_iter_dma_address(&sg_iter),
@@ -972,22 +1077,20 @@ static void gen6_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt)
 {
         int i;
 
-        if (ppgtt->pt_dma_addr) {
-                for (i = 0; i < ppgtt->num_pd_entries; i++)
-                        pci_unmap_page(ppgtt->base.dev->pdev,
-                                       ppgtt->pt_dma_addr[i],
-                                       4096, PCI_DMA_BIDIRECTIONAL);
-        }
+        for (i = 0; i < ppgtt->num_pd_entries; i++)
+                pci_unmap_page(ppgtt->base.dev->pdev,
+                               ppgtt->pd.page_table[i]->daddr,
+                               4096, PCI_DMA_BIDIRECTIONAL);
 }
 
 static void gen6_ppgtt_free(struct i915_hw_ppgtt *ppgtt)
 {
         int i;
 
-        kfree(ppgtt->pt_dma_addr);
         for (i = 0; i < ppgtt->num_pd_entries; i++)
-                __free_page(ppgtt->pt_pages[i]);
-        kfree(ppgtt->pt_pages);
+                unmap_and_free_pt(ppgtt->pd.page_table[i], ppgtt->base.dev);
+
+        unmap_and_free_pd(&ppgtt->pd);
 }
 
 static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
@@ -1032,31 +1135,13 @@ alloc:
                 goto alloc;
         }
 
+        if (ret)
+                return ret;
+
         if (ppgtt->node.start < dev_priv->gtt.mappable_end)
                 DRM_DEBUG("Forced to use aperture for PDEs\n");
 
         ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES;
-        return ret;
-}
-
-static int gen6_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt)
-{
-        int i;
-
-        ppgtt->pt_pages = kcalloc(ppgtt->num_pd_entries, sizeof(struct page *),
-                                  GFP_KERNEL);
-
-        if (!ppgtt->pt_pages)
-                return -ENOMEM;
-
-        for (i = 0; i < ppgtt->num_pd_entries; i++) {
-                ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL);
-                if (!ppgtt->pt_pages[i]) {
-                        gen6_ppgtt_free(ppgtt);
-                        return -ENOMEM;
-                }
-        }
-
         return 0;
 }
 
@@ -1068,20 +1153,14 @@ static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt)
         if (ret)
                 return ret;
 
-        ret = gen6_ppgtt_allocate_page_tables(ppgtt);
+        ret = alloc_pt_range(&ppgtt->pd, 0, ppgtt->num_pd_entries,
+                        ppgtt->base.dev);
+
         if (ret) {
                 drm_mm_remove_node(&ppgtt->node);
                 return ret;
         }
 
-        ppgtt->pt_dma_addr = kcalloc(ppgtt->num_pd_entries, sizeof(dma_addr_t),
-                                     GFP_KERNEL);
-        if (!ppgtt->pt_dma_addr) {
-                drm_mm_remove_node(&ppgtt->node);
-                gen6_ppgtt_free(ppgtt);
-                return -ENOMEM;
-        }
-
         return 0;
 }
 
@@ -1091,9 +1170,11 @@ static int gen6_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt)
         int i;
 
         for (i = 0; i < ppgtt->num_pd_entries; i++) {
+                struct page *page;
                 dma_addr_t pt_addr;
 
-                pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096,
+                page = ppgtt->pd.page_table[i]->page;
+                pt_addr = pci_map_page(dev->pdev, page, 0, 4096,
                                        PCI_DMA_BIDIRECTIONAL);
 
                 if (pci_dma_mapping_error(dev->pdev, pt_addr)) {
@@ -1101,7 +1182,7 @@ static int gen6_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt)
                         return -EIO;
                 }
 
-                ppgtt->pt_dma_addr[i] = pt_addr;
+                ppgtt->pd.page_table[i]->daddr = pt_addr;
         }
 
         return 0;
@@ -1123,6 +1204,9 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
         } else
                 BUG();
 
+        if (intel_vgpu_active(dev))
+                ppgtt->switch_mm = vgpu_mm_switch;
+
         ret = gen6_ppgtt_alloc(ppgtt);
         if (ret)
                 return ret;
@@ -1137,10 +1221,10 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
         ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
         ppgtt->base.cleanup = gen6_ppgtt_cleanup;
         ppgtt->base.start = 0;
-        ppgtt->base.total =  ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES * PAGE_SIZE;
+        ppgtt->base.total = ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES * PAGE_SIZE;
         ppgtt->debug_dump = gen6_dump_ppgtt;
 
-        ppgtt->pd_offset =
+        ppgtt->pd.pd_offset =
                 ppgtt->node.start / PAGE_SIZE * sizeof(gen6_gtt_pte_t);
 
         ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true);
@@ -1151,7 +1235,7 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
 
         gen6_write_pdes(ppgtt);
         DRM_DEBUG("Adding PPGTT at offset %x\n",
-                  ppgtt->pd_offset << 10);
+                  ppgtt->pd.pd_offset << 10);
 
         return 0;
 }
@@ -1753,6 +1837,16 @@ static int i915_gem_setup_global_gtt(struct drm_device *dev,
 
         /* Subtract the guard page ... */
         drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE);
+
+        dev_priv->gtt.base.start = start;
+        dev_priv->gtt.base.total = end - start;
+
+        if (intel_vgpu_active(dev)) {
+                ret = intel_vgt_balloon(dev);
+                if (ret)
+                        return ret;
+        }
+
         if (!HAS_LLC(dev))
                 dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust;
 
@@ -1772,9 +1866,6 @@ static int i915_gem_setup_global_gtt(struct drm_device *dev,
                 vma->bound |= GLOBAL_BIND;
         }
 
-        dev_priv->gtt.base.start = start;
-        dev_priv->gtt.base.total = end - start;
-
         /* Clear any non-preallocated blocks */
         drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) {
                 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
@@ -1826,6 +1917,9 @@ void i915_global_gtt_cleanup(struct drm_device *dev)
         }
 
         if (drm_mm_initialized(&vm->mm)) {
+                if (intel_vgpu_active(dev))
+                        intel_vgt_deballoon();
+
                 drm_mm_takedown(&vm->mm);
                 list_del(&vm->global_link);
         }
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index e377c7d27bd4..c9e93f5070bc 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -88,7 +88,7 @@ typedef gen8_gtt_pte_t gen8_ppgtt_pde_t;
 #define GEN8_PDE_MASK                   0x1ff
 #define GEN8_PTE_SHIFT                  12
 #define GEN8_PTE_MASK                   0x1ff
-#define GEN8_LEGACY_PDPS                4
+#define GEN8_LEGACY_PDPES               4
 #define GEN8_PTES_PER_PAGE              (PAGE_SIZE / sizeof(gen8_gtt_pte_t))
 #define GEN8_PDES_PER_PAGE              (PAGE_SIZE / sizeof(gen8_ppgtt_pde_t))
 
@@ -187,6 +187,26 @@ struct i915_vma {
                          u32 flags);
 };
 
+struct i915_page_table_entry {
+        struct page *page;
+        dma_addr_t daddr;
+};
+
+struct i915_page_directory_entry {
+        struct page *page; /* NULL for GEN6-GEN7 */
+        union {
+                uint32_t pd_offset;
+                dma_addr_t daddr;
+        };
+
+        struct i915_page_table_entry *page_table[GEN6_PPGTT_PD_ENTRIES]; /* PDEs */
+};
+
+struct i915_page_directory_pointer_entry {
+        /* struct page *page; */
+        struct i915_page_directory_entry *page_directory[GEN8_LEGACY_PDPES];
+};
+
 struct i915_address_space {
         struct drm_mm mm;
         struct drm_device *dev;
@@ -272,17 +292,8 @@ struct i915_hw_ppgtt {
         unsigned num_pd_entries;
         unsigned num_pd_pages; /* gen8+ */
         union {
-                struct page **pt_pages;
-                struct page **gen8_pt_pages[GEN8_LEGACY_PDPS];
-        };
-        struct page *pd_pages;
-        union {
-                uint32_t pd_offset;
-                dma_addr_t pd_dma_addr[GEN8_LEGACY_PDPS];
-        };
-        union {
-                dma_addr_t *pt_dma_addr;
-                dma_addr_t *gen8_pt_dma_addr[4];
+                struct i915_page_directory_pointer_entry pdp;
+                struct i915_page_directory_entry pd;
         };
 
         struct drm_i915_file_private *file_priv;
diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c
index 9c6f93ec886b..f8da71682c96 100644
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -231,7 +231,7 @@ static int i915_setup_compression(struct drm_device *dev, int size, int fb_cpp)
                            dev_priv->mm.stolen_base + compressed_llb->start);
         }
 
-        dev_priv->fbc.size = size / dev_priv->fbc.threshold;
+        dev_priv->fbc.uncompressed_size = size;
 
         DRM_DEBUG_KMS("reserved %d bytes of contiguous stolen space for FBC\n",
                       size);
@@ -253,7 +253,7 @@ int i915_gem_stolen_setup_compression(struct drm_device *dev, int size, int fb_c
         if (!drm_mm_initialized(&dev_priv->mm.stolen))
                 return -ENODEV;
 
-        if (size < dev_priv->fbc.size)
+        if (size <= dev_priv->fbc.uncompressed_size)
                 return 0;
 
         /* Release any current block */
@@ -266,7 +266,7 @@ void i915_gem_stolen_cleanup_compression(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
 
-        if (dev_priv->fbc.size == 0)
+        if (dev_priv->fbc.uncompressed_size == 0)
                 return;
 
         drm_mm_remove_node(&dev_priv->fbc.compressed_fb);
@@ -276,7 +276,7 @@ void i915_gem_stolen_cleanup_compression(struct drm_device *dev)
                 kfree(dev_priv->fbc.compressed_llb);
         }
 
-        dev_priv->fbc.size = 0;
+        dev_priv->fbc.uncompressed_size = 0;
 }
 
 void i915_gem_cleanup_stolen(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 48ddbf44c862..a982849a5edd 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -994,12 +994,11 @@ static void i915_gem_record_rings(struct drm_device *dev,
                                         i915_error_ggtt_object_create(dev_priv,
                                                              ring->scratch.obj);
 
-                        if (request->file_priv) {
+                        if (request->pid) {
                                 struct task_struct *task;
 
                                 rcu_read_lock();
-                                task = pid_task(request->file_priv->file->pid,
-                                                PIDTYPE_PID);
+                                task = pid_task(request->pid, PIDTYPE_PID);
                                 if (task) {
                                         strcpy(error->ring[i].comm, task->comm);
                                         error->ring[i].pid = task->pid;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index ede5bbbd8a08..9baecb79de8c 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -492,31 +492,6 @@ static void i915_enable_asle_pipestat(struct drm_device *dev)
         spin_unlock_irq(&dev_priv->irq_lock);
 }
 
-/**
- * i915_pipe_enabled - check if a pipe is enabled
- * @dev: DRM device
- * @pipe: pipe to check
- *
- * Reading certain registers when the pipe is disabled can hang the chip.
- * Use this routine to make sure the PLL is running and the pipe is active
- * before reading such registers if unsure.
- */
-static int
-i915_pipe_enabled(struct drm_device *dev, int pipe)
-{
-        struct drm_i915_private *dev_priv = dev->dev_private;
-
-        if (drm_core_check_feature(dev, DRIVER_MODESET)) {
-                /* Locking is horribly broken here, but whatever. */
-                struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
-                struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-
-                return intel_crtc->active;
-        } else {
-                return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
-        }
-}
-
 /*
  * This timing diagram depicts the video signal in and
  * around the vertical blanking period.
@@ -582,34 +557,16 @@ static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
         unsigned long high_frame;
         unsigned long low_frame;
         u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
+        struct intel_crtc *intel_crtc =
+                to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
+        const struct drm_display_mode *mode =
+                &intel_crtc->config->base.adjusted_mode;
 
-        if (!i915_pipe_enabled(dev, pipe)) {
-                DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
-                                "pipe %c\n", pipe_name(pipe));
-                return 0;
-        }
-
-        if (drm_core_check_feature(dev, DRIVER_MODESET)) {
-                struct intel_crtc *intel_crtc =
-                        to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
-                const struct drm_display_mode *mode =
-                        &intel_crtc->config->base.adjusted_mode;
-
-                htotal = mode->crtc_htotal;
-                hsync_start = mode->crtc_hsync_start;
-                vbl_start = mode->crtc_vblank_start;
-                if (mode->flags & DRM_MODE_FLAG_INTERLACE)
-                        vbl_start = DIV_ROUND_UP(vbl_start, 2);
-        } else {
-                enum transcoder cpu_transcoder = (enum transcoder) pipe;
-
-                htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1;
-                hsync_start = (I915_READ(HSYNC(cpu_transcoder))  & 0x1fff) + 1;
-                vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1;
-                if ((I915_READ(PIPECONF(cpu_transcoder)) &
-                     PIPECONF_INTERLACE_MASK) != PIPECONF_PROGRESSIVE)
-                        vbl_start = DIV_ROUND_UP(vbl_start, 2);
-        }
+        htotal = mode->crtc_htotal;
+        hsync_start = mode->crtc_hsync_start;
+        vbl_start = mode->crtc_vblank_start;
+        if (mode->flags & DRM_MODE_FLAG_INTERLACE)
+                vbl_start = DIV_ROUND_UP(vbl_start, 2);
 
         /* Convert to pixel count */
         vbl_start *= htotal;
@@ -648,12 +605,6 @@ static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
         struct drm_i915_private *dev_priv = dev->dev_private;
         int reg = PIPE_FRMCOUNT_GM45(pipe);
 
-        if (!i915_pipe_enabled(dev, pipe)) {
-                DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
-                                 "pipe %c\n", pipe_name(pipe));
-                return 0;
-        }
-
         return I915_READ(reg);
 }
 
@@ -840,7 +791,7 @@ static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
                 return -EINVAL;
         }
 
-        if (!crtc->enabled) {
+        if (!crtc->state->enable) {
                 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
                 return -EBUSY;
         }
@@ -1243,10 +1194,7 @@ static void gen6_pm_rps_work(struct work_struct *work)
 
         dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_freq;
 
-        if (IS_VALLEYVIEW(dev_priv->dev))
-                valleyview_set_rps(dev_priv->dev, new_delay);
-        else
-                gen6_set_rps(dev_priv->dev, new_delay);
+        intel_set_rps(dev_priv->dev, new_delay);
 
         mutex_unlock(&dev_priv->rps.hw_lock);
 }
@@ -2662,9 +2610,6 @@ static int i915_enable_vblank(struct drm_device *dev, int pipe)
         struct drm_i915_private *dev_priv = dev->dev_private;
         unsigned long irqflags;
 
-        if (!i915_pipe_enabled(dev, pipe))
-                return -EINVAL;
-
         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
         if (INTEL_INFO(dev)->gen >= 4)
                 i915_enable_pipestat(dev_priv, pipe,
@@ -2684,9 +2629,6 @@ static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
         uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
                                                      DE_PIPE_VBLANK(pipe);
 
-        if (!i915_pipe_enabled(dev, pipe))
-                return -EINVAL;
-
         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
         ironlake_enable_display_irq(dev_priv, bit);
         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
@@ -2699,9 +2641,6 @@ static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
         struct drm_i915_private *dev_priv = dev->dev_private;
         unsigned long irqflags;
 
-        if (!i915_pipe_enabled(dev, pipe))
-                return -EINVAL;
-
         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
         i915_enable_pipestat(dev_priv, pipe,
                              PIPE_START_VBLANK_INTERRUPT_STATUS);
@@ -2715,9 +2654,6 @@ static int gen8_enable_vblank(struct drm_device *dev, int pipe)
         struct drm_i915_private *dev_priv = dev->dev_private;
         unsigned long irqflags;
 
-        if (!i915_pipe_enabled(dev, pipe))
-                return -EINVAL;
-
         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
         dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
         I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
@@ -2769,9 +2705,6 @@ static void gen8_disable_vblank(struct drm_device *dev, int pipe)
         struct drm_i915_private *dev_priv = dev->dev_private;
         unsigned long irqflags;
 
-        if (!i915_pipe_enabled(dev, pipe))
-                return;
-
         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
         dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
         I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
@@ -4392,10 +4325,8 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
         if (!IS_GEN2(dev_priv))
                 dev->vblank_disable_immediate = true;
 
-        if (drm_core_check_feature(dev, DRIVER_MODESET)) {
-                dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
-                dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
-        }
+        dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
+        dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
 
         if (IS_CHERRYVIEW(dev_priv)) {
                 dev->driver->irq_handler = cherryview_irq_handler;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 33b3d0a24071..55143cb36e74 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -139,7 +139,21 @@
 #define GEN8_RING_PDP_UDW(ring, n)      ((ring)->mmio_base+0x270 + ((n) * 8 + 4))
 #define GEN8_RING_PDP_LDW(ring, n)      ((ring)->mmio_base+0x270 + (n) * 8)
 
+#define GEN8_R_PWR_CLK_STATE            0x20C8
+#define   GEN8_RPCS_ENABLE              (1 << 31)
+#define   GEN8_RPCS_S_CNT_ENABLE        (1 << 18)
+#define   GEN8_RPCS_S_CNT_SHIFT         15
+#define   GEN8_RPCS_S_CNT_MASK          (0x7 << GEN8_RPCS_S_CNT_SHIFT)
+#define   GEN8_RPCS_SS_CNT_ENABLE       (1 << 11)
+#define   GEN8_RPCS_SS_CNT_SHIFT        8
+#define   GEN8_RPCS_SS_CNT_MASK         (0x7 << GEN8_RPCS_SS_CNT_SHIFT)
+#define   GEN8_RPCS_EU_MAX_SHIFT        4
+#define   GEN8_RPCS_EU_MAX_MASK         (0xf << GEN8_RPCS_EU_MAX_SHIFT)
+#define   GEN8_RPCS_EU_MIN_SHIFT        0
+#define   GEN8_RPCS_EU_MIN_MASK         (0xf << GEN8_RPCS_EU_MIN_SHIFT)
+
 #define GAM_ECOCHK                      0x4090
+#define   BDW_DISABLE_HDC_INVALIDATION  (1<<25)
 #define   ECOCHK_SNB_BIT                (1<<10)
 #define   HSW_ECOCHK_ARB_PRIO_SOL       (1<<6)
 #define   ECOCHK_PPGTT_CACHE64B         (0x3<<3)
@@ -586,6 +600,19 @@ enum punit_power_well {
         PUNIT_POWER_WELL_NUM,
 };
 
+enum skl_disp_power_wells {
+        SKL_DISP_PW_MISC_IO,
+        SKL_DISP_PW_DDI_A_E,
+        SKL_DISP_PW_DDI_B,
+        SKL_DISP_PW_DDI_C,
+        SKL_DISP_PW_DDI_D,
+        SKL_DISP_PW_1 = 14,
+        SKL_DISP_PW_2,
+};
+
+#define SKL_POWER_WELL_STATE(pw) (1 << ((pw) * 2))
+#define SKL_POWER_WELL_REQ(pw) (1 << (((pw) * 2) + 1))
+
 #define PUNIT_REG_PWRGT_CTRL                    0x60
 #define PUNIT_REG_PWRGT_STATUS                  0x61
 #define   PUNIT_PWRGT_MASK(power_well)          (3 << ((power_well) * 2))
@@ -1011,6 +1038,16 @@ enum punit_power_well {
 #define   DPIO_CHV_PROP_COEFF_SHIFT     0
 #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
 
+#define _CHV_PLL_DW8_CH0                0x8020
+#define _CHV_PLL_DW8_CH1                0x81A0
+#define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
+
+#define _CHV_PLL_DW9_CH0                0x8024
+#define _CHV_PLL_DW9_CH1                0x81A4
+#define  DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT              1 /* 3 bits */
+#define  DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1 /* 1: coarse & 0 : fine  */
+#define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
+
 #define _CHV_CMN_DW5_CH0               0x8114
 #define   CHV_BUFRIGHTENA1_DISABLE      (0 << 20)
 #define   CHV_BUFRIGHTENA1_NORMAL       (1 << 20)
@@ -1314,6 +1351,8 @@ enum punit_power_well {
 #define   GEN6_WIZ_HASHING_16x4                         GEN6_WIZ_HASHING(1, 0)
 #define   GEN6_WIZ_HASHING_MASK                         GEN6_WIZ_HASHING(1, 1)
 #define   GEN6_TD_FOUR_ROW_DISPATCH_DISABLE             (1 << 5)
+#define   GEN9_IZ_HASHING_MASK(slice)                   (0x3 << (slice * 2))
+#define   GEN9_IZ_HASHING(slice, val)                   ((val) << (slice * 2))
 
 #define GFX_MODE        0x02520
 #define GFX_MODE_GEN7   0x0229c
@@ -1470,6 +1509,7 @@ enum punit_power_well {
 #define CACHE_MODE_1            0x7004 /* IVB+ */
 #define   PIXEL_SUBSPAN_COLLECT_OPT_DISABLE     (1<<6)
 #define   GEN8_4x4_STC_OPTIMIZATION_DISABLE     (1<<6)
+#define   GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE    (1<<1)
 
 #define GEN6_BLITTER_ECOSKPD    0x221d0
 #define   GEN6_BLITTER_LOCK_SHIFT                       16
@@ -1491,6 +1531,17 @@ enum punit_power_well {
 #define   CHV_FGT_EU_DIS_SS1_R1_SHIFT   28
 #define   CHV_FGT_EU_DIS_SS1_R1_MASK    (0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT)
 
+#define GEN8_FUSE2                      0x9120
+#define   GEN8_F2_S_ENA_SHIFT           25
+#define   GEN8_F2_S_ENA_MASK            (0x7 << GEN8_F2_S_ENA_SHIFT)
+
+#define   GEN9_F2_SS_DIS_SHIFT          20
+#define   GEN9_F2_SS_DIS_MASK           (0xf << GEN9_F2_SS_DIS_SHIFT)
+
+#define GEN8_EU_DISABLE0                0x9134
+#define GEN8_EU_DISABLE1                0x9138
+#define GEN8_EU_DISABLE2                0x913c
+
 #define GEN6_BSD_SLEEP_PSMI_CONTROL     0x12050
 #define   GEN6_BSD_SLEEP_MSG_DISABLE    (1 << 0)
 #define   GEN6_BSD_SLEEP_FLUSH_DISABLE  (1 << 2)
@@ -3865,6 +3916,7 @@ enum punit_power_well {
 #define   PIPECONF_INTERLACE_MODE_MASK          (7 << 21)
 #define   PIPECONF_EDP_RR_MODE_SWITCH           (1 << 20)
 #define   PIPECONF_CXSR_DOWNCLOCK       (1<<16)
+#define   PIPECONF_EDP_RR_MODE_SWITCH_VLV       (1 << 14)
 #define   PIPECONF_COLOR_RANGE_SELECT   (1 << 13)
 #define   PIPECONF_BPC_MASK     (0x7 << 5)
 #define   PIPECONF_8BPC         (0<<5)
@@ -5221,14 +5273,22 @@ enum punit_power_well {
 #define HSW_NDE_RSTWRN_OPT      0x46408
 #define  RESET_PCH_HANDSHAKE_ENABLE     (1<<4)
 
+#define FF_SLICE_CS_CHICKEN2                    0x02e4
+#define  GEN9_TSG_BARRIER_ACK_DISABLE           (1<<8)
+
 /* GEN7 chicken */
 #define GEN7_COMMON_SLICE_CHICKEN1              0x7010
 # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC      ((1<<10) | (1<<26))
+# define GEN9_RHWO_OPTIMIZATION_DISABLE         (1<<14)
 #define COMMON_SLICE_CHICKEN2                   0x7014
 # define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE   (1<<0)
 
-#define HIZ_CHICKEN                             0x7018
-# define CHV_HZ_8X8_MODE_IN_1X                  (1<<15)
+#define HIZ_CHICKEN                                     0x7018
+# define CHV_HZ_8X8_MODE_IN_1X                          (1<<15)
+# define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE    (1<<3)
+
+#define GEN9_SLICE_COMMON_ECO_CHICKEN0          0x7308
+#define  DISABLE_PIXEL_MASK_CAMMING             (1<<14)
 
 #define GEN7_L3SQCREG1                          0xB010
 #define  VLV_B0_WA_L3SQCREG1_VALUE              0x00D30000
@@ -5245,11 +5305,16 @@ enum punit_power_well {
 #define GEN7_L3SQCREG4                          0xb034
 #define  L3SQ_URB_READ_CAM_MATCH_DISABLE        (1<<27)
 
+#define GEN8_L3SQCREG4                          0xb118
+#define  GEN8_LQSC_RO_PERF_DIS                  (1<<27)
+
 /* GEN8 chicken */
 #define HDC_CHICKEN0                            0x7300
-#define  HDC_FORCE_NON_COHERENT                 (1<<4)
-#define  HDC_DONOT_FETCH_MEM_WHEN_MASKED        (1<<11)
 #define  HDC_FENCE_DEST_SLM_DISABLE             (1<<14)
+#define  HDC_DONOT_FETCH_MEM_WHEN_MASKED        (1<<11)
+#define  HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT    (1<<5)
+#define  HDC_FORCE_NON_COHERENT                 (1<<4)
+#define  HDC_BARRIER_PERFORMANCE_DISABLE        (1<<10)
 
 /* WaCatErrorRejectionIssue */
 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG          0x9030
@@ -5258,6 +5323,9 @@ enum punit_power_well {
 #define HSW_SCRATCH1                            0xb038
 #define  HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE   (1<<27)
 
+#define BDW_SCRATCH1                                    0xb11c
+#define  GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE      (1<<2)
+
 /* PCH */
 
 /* south display engine interrupt: IBX */
@@ -5980,6 +6048,7 @@ enum punit_power_well {
 #define  HSW_IDICR                              0x9008
 #define    IDIHASHMSK(x)                        (((x) & 0x3f) << 16)
 #define  HSW_EDRAM_PRESENT                      0x120010
+#define    EDRAM_ENABLED                        0x1
 
 #define GEN6_UCGCTL1                            0x9400
 # define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE              (1 << 16)
@@ -6003,6 +6072,7 @@ enum punit_power_well {
 #define GEN6_RSTCTL                             0x9420
 
 #define GEN8_UCGCTL6                            0x9430
+#define   GEN8_GAPSUNIT_CLOCK_GATE_DISABLE      (1<<24)
 #define   GEN8_SDEUNIT_CLOCK_GATE_DISABLE       (1<<14)
 
 #define GEN6_GFXPAUSE                           0xA000
@@ -6155,6 +6225,26 @@ enum punit_power_well {
 #define   GEN6_RC6                      3
 #define   GEN6_RC7                      4
 
+#define GEN9_SLICE0_PGCTL_ACK           0x804c
+#define GEN9_SLICE1_PGCTL_ACK           0x8050
+#define GEN9_SLICE2_PGCTL_ACK           0x8054
+#define   GEN9_PGCTL_SLICE_ACK          (1 << 0)
+
+#define GEN9_SLICE0_SS01_EU_PGCTL_ACK   0x805c
+#define GEN9_SLICE0_SS23_EU_PGCTL_ACK   0x8060
+#define GEN9_SLICE1_SS01_EU_PGCTL_ACK   0x8064
+#define GEN9_SLICE1_SS23_EU_PGCTL_ACK   0x8068
+#define GEN9_SLICE2_SS01_EU_PGCTL_ACK   0x806c
+#define GEN9_SLICE2_SS23_EU_PGCTL_ACK   0x8070
+#define   GEN9_PGCTL_SSA_EU08_ACK       (1 << 0)
+#define   GEN9_PGCTL_SSA_EU19_ACK       (1 << 2)
+#define   GEN9_PGCTL_SSA_EU210_ACK      (1 << 4)
+#define   GEN9_PGCTL_SSA_EU311_ACK      (1 << 6)
+#define   GEN9_PGCTL_SSB_EU08_ACK       (1 << 8)
+#define   GEN9_PGCTL_SSB_EU19_ACK       (1 << 10)
+#define   GEN9_PGCTL_SSB_EU210_ACK      (1 << 12)
+#define   GEN9_PGCTL_SSB_EU311_ACK      (1 << 14)
+
 #define GEN7_MISCCPCTL                  (0x9424)
 #define   GEN7_DOP_CLOCK_GATE_ENABLE    (1<<0)
 
@@ -6185,6 +6275,7 @@ enum punit_power_well {
 
 #define GEN9_HALF_SLICE_CHICKEN5        0xe188
 #define   GEN9_DG_MIRROR_FIX_ENABLE     (1<<5)
+#define   GEN9_CCS_TLB_PREFETCH_ENABLE  (1<<3)
 
 #define GEN8_ROW_CHICKEN                0xe4f0
 #define   PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1<<8)
@@ -6200,8 +6291,12 @@ enum punit_power_well {
 #define HALF_SLICE_CHICKEN3             0xe184
 #define   HSW_SAMPLE_C_PERFORMANCE      (1<<9)
 #define   GEN8_CENTROID_PIXEL_OPT_DIS   (1<<8)
+#define   GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC   (1<<5)
 #define   GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1)
 
+#define GEN9_HALF_SLICE_CHICKEN7        0xe194
+#define   GEN9_ENABLE_YV12_BUGFIX       (1<<4)
+
 /* Audio */
 #define G4X_AUD_VID_DID                 (dev_priv->info.display_mmio_offset + 0x62020)
 #define   INTEL_AUDIO_DEVCL             0x808629FB
@@ -6351,6 +6446,13 @@ enum punit_power_well {
 #define   HSW_PWR_WELL_FORCE_ON                 (1<<19)
 #define HSW_PWR_WELL_CTL6                       0x45414
 
+/* SKL Fuse Status */
+#define SKL_FUSE_STATUS                         0x42000
+#define  SKL_FUSE_DOWNLOAD_STATUS              (1<<31)
+#define  SKL_FUSE_PG0_DIST_STATUS              (1<<27)
+#define  SKL_FUSE_PG1_DIST_STATUS              (1<<26)
+#define  SKL_FUSE_PG2_DIST_STATUS              (1<<25)
+
 /* Per-pipe DDI Function Control */
 #define TRANS_DDI_FUNC_CTL_A            0x60400
 #define TRANS_DDI_FUNC_CTL_B            0x61400
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 9f19ed38cdc3..cf67f82f7b7f 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -29,166 +29,6 @@
 #include "intel_drv.h"
 #include "i915_reg.h"
 
-static u8 i915_read_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg)
-{
-        struct drm_i915_private *dev_priv = dev->dev_private;
-
-        I915_WRITE8(index_port, reg);
-        return I915_READ8(data_port);
-}
-
-static u8 i915_read_ar(struct drm_device *dev, u16 st01, u8 reg, u16 palette_enable)
-{
-        struct drm_i915_private *dev_priv = dev->dev_private;
-
-        I915_READ8(st01);
-        I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
-        return I915_READ8(VGA_AR_DATA_READ);
-}
-
-static void i915_write_ar(struct drm_device *dev, u16 st01, u8 reg, u8 val, u16 palette_enable)
-{
-        struct drm_i915_private *dev_priv = dev->dev_private;
-
-        I915_READ8(st01);
-        I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
-        I915_WRITE8(VGA_AR_DATA_WRITE, val);
-}
-
-static void i915_write_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg, u8 val)
-{
-        struct drm_i915_private *dev_priv = dev->dev_private;
-
-        I915_WRITE8(index_port, reg);
-        I915_WRITE8(data_port, val);
-}
-
-static void i915_save_vga(struct drm_device *dev)
-{
-        struct drm_i915_private *dev_priv = dev->dev_private;
-        int i;
-        u16 cr_index, cr_data, st01;
-
-        /* VGA state */
-        dev_priv->regfile.saveVGA0 = I915_READ(VGA0);
-        dev_priv->regfile.saveVGA1 = I915_READ(VGA1);
-        dev_priv->regfile.saveVGA_PD = I915_READ(VGA_PD);
-        dev_priv->regfile.saveVGACNTRL = I915_READ(i915_vgacntrl_reg(dev));
-
-        /* VGA color palette registers */
-        dev_priv->regfile.saveDACMASK = I915_READ8(VGA_DACMASK);
-
-        /* MSR bits */
-        dev_priv->regfile.saveMSR = I915_READ8(VGA_MSR_READ);
-        if (dev_priv->regfile.saveMSR & VGA_MSR_CGA_MODE) {
-                cr_index = VGA_CR_INDEX_CGA;
-                cr_data = VGA_CR_DATA_CGA;
-                st01 = VGA_ST01_CGA;
-        } else {
-                cr_index = VGA_CR_INDEX_MDA;
-                cr_data = VGA_CR_DATA_MDA;
-                st01 = VGA_ST01_MDA;
-        }
-
-        /* CRT controller regs */
-        i915_write_indexed(dev, cr_index, cr_data, 0x11,
-                           i915_read_indexed(dev, cr_index, cr_data, 0x11) &
-                           (~0x80));
-        for (i = 0; i <= 0x24; i++)
-                dev_priv->regfile.saveCR[i] =
-                        i915_read_indexed(dev, cr_index, cr_data, i);
-        /* Make sure we don't turn off CR group 0 writes */
-        dev_priv->regfile.saveCR[0x11] &= ~0x80;
-
-        /* Attribute controller registers */
-        I915_READ8(st01);
-        dev_priv->regfile.saveAR_INDEX = I915_READ8(VGA_AR_INDEX);
-        for (i = 0; i <= 0x14; i++)
-                dev_priv->regfile.saveAR[i] = i915_read_ar(dev, st01, i, 0);
-        I915_READ8(st01);
-        I915_WRITE8(VGA_AR_INDEX, dev_priv->regfile.saveAR_INDEX);
-        I915_READ8(st01);
-
-        /* Graphics controller registers */
-        for (i = 0; i < 9; i++)
-                dev_priv->regfile.saveGR[i] =
-                        i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i);
-
-        dev_priv->regfile.saveGR[0x10] =
-                i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10);
-        dev_priv->regfile.saveGR[0x11] =
-                i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11);
-        dev_priv->regfile.saveGR[0x18] =
-                i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18);
-
-        /* Sequencer registers */
-        for (i = 0; i < 8; i++)
-                dev_priv->regfile.saveSR[i] =
-                        i915_read_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i);
-}
-
-static void i915_restore_vga(struct drm_device *dev)
-{
-        struct drm_i915_private *dev_priv = dev->dev_private;
-        int i;
-        u16 cr_index, cr_data, st01;
-
-        /* VGA state */
-        I915_WRITE(i915_vgacntrl_reg(dev), dev_priv->regfile.saveVGACNTRL);
-
-        I915_WRITE(VGA0, dev_priv->regfile.saveVGA0);
-        I915_WRITE(VGA1, dev_priv->regfile.saveVGA1);
-        I915_WRITE(VGA_PD, dev_priv->regfile.saveVGA_PD);
-        POSTING_READ(VGA_PD);
-        udelay(150);
-
-        /* MSR bits */
-        I915_WRITE8(VGA_MSR_WRITE, dev_priv->regfile.saveMSR);
-        if (dev_priv->regfile.saveMSR & VGA_MSR_CGA_MODE) {
-                cr_index = VGA_CR_INDEX_CGA;
-                cr_data = VGA_CR_DATA_CGA;
-                st01 = VGA_ST01_CGA;
-        } else {
-                cr_index = VGA_CR_INDEX_MDA;
-                cr_data = VGA_CR_DATA_MDA;
-                st01 = VGA_ST01_MDA;
-        }
-
-        /* Sequencer registers, don't write SR07 */
-        for (i = 0; i < 7; i++)
-                i915_write_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i,
-                                   dev_priv->regfile.saveSR[i]);
-
-        /* CRT controller regs */
-        /* Enable CR group 0 writes */
-        i915_write_indexed(dev, cr_index, cr_data, 0x11, dev_priv->regfile.saveCR[0x11]);
-        for (i = 0; i <= 0x24; i++)
-                i915_write_indexed(dev, cr_index, cr_data, i, dev_priv->regfile.saveCR[i]);
-
-        /* Graphics controller regs */
-        for (i = 0; i < 9; i++)
-                i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i,
-                                   dev_priv->regfile.saveGR[i]);
-
-        i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10,
-                           dev_priv->regfile.saveGR[0x10]);
-        i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11,
-                           dev_priv->regfile.saveGR[0x11]);
-        i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18,
-                           dev_priv->regfile.saveGR[0x18]);
-
-        /* Attribute controller registers */
-        I915_READ8(st01); /* switch back to index mode */
-        for (i = 0; i <= 0x14; i++)
-                i915_write_ar(dev, st01, i, dev_priv->regfile.saveAR[i], 0);
-        I915_READ8(st01); /* switch back to index mode */
-        I915_WRITE8(VGA_AR_INDEX, dev_priv->regfile.saveAR_INDEX | 0x20);
-        I915_READ8(st01);
-
-        /* VGA color palette registers */
-        I915_WRITE8(VGA_DACMASK, dev_priv->regfile.saveDACMASK);
-}
-
 static void i915_save_display(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
@@ -197,11 +37,6 @@ static void i915_save_display(struct drm_device *dev)
         if (INTEL_INFO(dev)->gen <= 4)
                 dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);
 
-        /* This is only meaningful in non-KMS mode */
-        /* Don't regfile.save them in KMS mode */
-        if (!drm_core_check_feature(dev, DRIVER_MODESET))
-                i915_save_display_reg(dev);
-
         /* LVDS state */
         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
                 dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS);
@@ -224,9 +59,6 @@ static void i915_save_display(struct drm_device *dev)
         /* save FBC interval */
         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev))
                 dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);
-
-        if (!drm_core_check_feature(dev, DRIVER_MODESET))
-                i915_save_vga(dev);
 }
 
 static void i915_restore_display(struct drm_device *dev)
@@ -238,11 +70,7 @@ static void i915_restore_display(struct drm_device *dev)
         if (INTEL_INFO(dev)->gen <= 4)
                 I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB);
 
-        if (!drm_core_check_feature(dev, DRIVER_MODESET))
-                i915_restore_display_reg(dev);
-
-        if (drm_core_check_feature(dev, DRIVER_MODESET))
-                mask = ~LVDS_PORT_EN;
+        mask = ~LVDS_PORT_EN;
 
         /* LVDS state */
         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
@@ -270,10 +98,7 @@ static void i915_restore_display(struct drm_device *dev)
         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev))
                 I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL);
 
-        if (!drm_core_check_feature(dev, DRIVER_MODESET))
-                i915_restore_vga(dev);
-        else
-                i915_redisable_vga(dev);
+        i915_redisable_vga(dev);
 }
 
 int i915_save_state(struct drm_device *dev)
@@ -285,24 +110,6 @@ int i915_save_state(struct drm_device *dev)
 
         i915_save_display(dev);
 
-        if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
-                /* Interrupt state */
-                if (HAS_PCH_SPLIT(dev)) {
-                        dev_priv->regfile.saveDEIER = I915_READ(DEIER);
-                        dev_priv->regfile.saveDEIMR = I915_READ(DEIMR);
-                        dev_priv->regfile.saveGTIER = I915_READ(GTIER);
-                        dev_priv->regfile.saveGTIMR = I915_READ(GTIMR);
-                        dev_priv->regfile.saveFDI_RXA_IMR = I915_READ(_FDI_RXA_IMR);
-                        dev_priv->regfile.saveFDI_RXB_IMR = I915_READ(_FDI_RXB_IMR);
-                        dev_priv->regfile.saveMCHBAR_RENDER_STANDBY =
-                                I915_READ(RSTDBYCTL);
-                        dev_priv->regfile.savePCH_PORT_HOTPLUG = I915_READ(PCH_PORT_HOTPLUG);
-                } else {
-                        dev_priv->regfile.saveIER = I915_READ(IER);
-                        dev_priv->regfile.saveIMR = I915_READ(IMR);
-                }
-        }
-
         if (IS_GEN4(dev))
                 pci_read_config_word(dev->pdev, GCDGMBUS,
                                      &dev_priv->regfile.saveGCDGMBUS);
@@ -341,24 +148,6 @@ int i915_restore_state(struct drm_device *dev)
                                       dev_priv->regfile.saveGCDGMBUS);
         i915_restore_display(dev);
 
-        if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
-                /* Interrupt state */
-                if (HAS_PCH_SPLIT(dev)) {
-                        I915_WRITE(DEIER, dev_priv->regfile.saveDEIER);
-                        I915_WRITE(DEIMR, dev_priv->regfile.saveDEIMR);
-                        I915_WRITE(GTIER, dev_priv->regfile.saveGTIER);
-                        I915_WRITE(GTIMR, dev_priv->regfile.saveGTIMR);
-                        I915_WRITE(_FDI_RXA_IMR, dev_priv->regfile.saveFDI_RXA_IMR);
-                        I915_WRITE(_FDI_RXB_IMR, dev_priv->regfile.saveFDI_RXB_IMR);
-                        I915_WRITE(PCH_PORT_HOTPLUG, dev_priv->regfile.savePCH_PORT_HOTPLUG);
-                        I915_WRITE(RSTDBYCTL,
-                                   dev_priv->regfile.saveMCHBAR_RENDER_STANDBY);
-                } else {
-                        I915_WRITE(IER, dev_priv->regfile.saveIER);
-                        I915_WRITE(IMR, dev_priv->regfile.saveIMR);
-                }
-        }
-
         /* Cache mode state */
         if (INTEL_INFO(dev)->gen < 7)
                 I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 |
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index 49f5ade0edb7..67bd07edcbb0 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -127,10 +127,19 @@ show_rc6pp_ms(struct device *kdev, struct device_attribute *attr, char *buf)
         return snprintf(buf, PAGE_SIZE, "%u\n", rc6pp_residency);
 }
 
+static ssize_t
+show_media_rc6_ms(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+        struct drm_minor *dminor = dev_get_drvdata(kdev);
+        u32 rc6_residency = calc_residency(dminor->dev, VLV_GT_MEDIA_RC6);
+        return snprintf(buf, PAGE_SIZE, "%u\n", rc6_residency);
+}
+
 static DEVICE_ATTR(rc6_enable, S_IRUGO, show_rc6_mask, NULL);
 static DEVICE_ATTR(rc6_residency_ms, S_IRUGO, show_rc6_ms, NULL);
 static DEVICE_ATTR(rc6p_residency_ms, S_IRUGO, show_rc6p_ms, NULL);
 static DEVICE_ATTR(rc6pp_residency_ms, S_IRUGO, show_rc6pp_ms, NULL);
+static DEVICE_ATTR(media_rc6_residency_ms, S_IRUGO, show_media_rc6_ms, NULL);
 
 static struct attribute *rc6_attrs[] = {
         &dev_attr_rc6_enable.attr,
@@ -153,6 +162,16 @@ static struct attribute_group rc6p_attr_group = {
         .name = power_group_name,
         .attrs =  rc6p_attrs
 };
+
+static struct attribute *media_rc6_attrs[] = {
+        &dev_attr_media_rc6_residency_ms.attr,
+        NULL
+};
+
+static struct attribute_group media_rc6_attr_group = {
+        .name = power_group_name,
+        .attrs =  media_rc6_attrs
+};
 #endif
 
 static int l3_access_valid(struct drm_device *dev, loff_t offset)
@@ -402,10 +421,7 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev,
         /* We still need *_set_rps to process the new max_delay and
          * update the interrupt limits and PMINTRMSK even though
          * frequency request may be unchanged. */
-        if (IS_VALLEYVIEW(dev))
-                valleyview_set_rps(dev, val);
-        else
-                gen6_set_rps(dev, val);
+        intel_set_rps(dev, val);
 
         mutex_unlock(&dev_priv->rps.hw_lock);
 
@@ -464,10 +480,7 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
         /* We still need *_set_rps to process the new min_delay and
          * update the interrupt limits and PMINTRMSK even though
          * frequency request may be unchanged. */
-        if (IS_VALLEYVIEW(dev))
-                valleyview_set_rps(dev, val);
-        else
-                gen6_set_rps(dev, val);
+        intel_set_rps(dev, val);
 
         mutex_unlock(&dev_priv->rps.hw_lock);
 
@@ -493,38 +506,17 @@ static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr
         struct drm_minor *minor = dev_to_drm_minor(kdev);
         struct drm_device *dev = minor->dev;
         struct drm_i915_private *dev_priv = dev->dev_private;
-        u32 val, rp_state_cap;
-        ssize_t ret;
-
-        ret = mutex_lock_interruptible(&dev->struct_mutex);
-        if (ret)
-                return ret;
-        intel_runtime_pm_get(dev_priv);
-        rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
-        intel_runtime_pm_put(dev_priv);
-        mutex_unlock(&dev->struct_mutex);
+        u32 val;
 
-        if (attr == &dev_attr_gt_RP0_freq_mhz) {
-                if (IS_VALLEYVIEW(dev))
-                        val = intel_gpu_freq(dev_priv, dev_priv->rps.rp0_freq);
-                else
-                        val = intel_gpu_freq(dev_priv,
-                                             ((rp_state_cap & 0x0000ff) >> 0));
-        } else if (attr == &dev_attr_gt_RP1_freq_mhz) {
-                if (IS_VALLEYVIEW(dev))
-                        val = intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq);
-                else
-                        val = intel_gpu_freq(dev_priv,
-                                             ((rp_state_cap & 0x00ff00) >> 8));
-        } else if (attr == &dev_attr_gt_RPn_freq_mhz) {
-                if (IS_VALLEYVIEW(dev))
-                        val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq);
-                else
-                        val = intel_gpu_freq(dev_priv,
-                                             ((rp_state_cap & 0xff0000) >> 16));
-        } else {
+        if (attr == &dev_attr_gt_RP0_freq_mhz)
+                val = intel_gpu_freq(dev_priv, dev_priv->rps.rp0_freq);
+        else if (attr == &dev_attr_gt_RP1_freq_mhz)
+                val = intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq);
+        else if (attr == &dev_attr_gt_RPn_freq_mhz)
+                val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq);
+        else
                 BUG();
-        }
+
         return snprintf(buf, PAGE_SIZE, "%d\n", val);
 }
 
@@ -633,6 +625,12 @@ void i915_setup_sysfs(struct drm_device *dev)
                 if (ret)
                         DRM_ERROR("RC6p residency sysfs setup failed\n");
         }
+        if (IS_VALLEYVIEW(dev)) {
+                ret = sysfs_merge_group(&dev->primary->kdev->kobj,
+                                        &media_rc6_attr_group);
+                if (ret)
+                        DRM_ERROR("Media RC6 residency sysfs setup failed\n");
+        }
 #endif
         if (HAS_L3_DPF(dev)) {
                 ret = device_create_bin_file(dev->primary->kdev, &dpf_attrs);
diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace.h
index 6058a01b4443..f004d3d89b87 100644
--- a/drivers/gpu/drm/i915/i915_trace.h
+++ b/drivers/gpu/drm/i915/i915_trace.h
@@ -115,7 +115,7 @@ TRACE_EVENT(i915_vma_bind,
             TP_STRUCT__entry(
                              __field(struct drm_i915_gem_object *, obj)
                              __field(struct i915_address_space *, vm)
-                             __field(u32, offset)
+                             __field(u64, offset)
                              __field(u32, size)
                              __field(unsigned, flags)
                              ),
@@ -128,7 +128,7 @@ TRACE_EVENT(i915_vma_bind,
                            __entry->flags = flags;
                            ),
 
-            TP_printk("obj=%p, offset=%08x size=%x%s vm=%p",
+            TP_printk("obj=%p, offset=%016llx size=%x%s vm=%p",
                       __entry->obj, __entry->offset, __entry->size,
                       __entry->flags & PIN_MAPPABLE ? ", mappable" : "",
                       __entry->vm)
@@ -141,7 +141,7 @@ TRACE_EVENT(i915_vma_unbind,
             TP_STRUCT__entry(
                              __field(struct drm_i915_gem_object *, obj)
                              __field(struct i915_address_space *, vm)
-                             __field(u32, offset)
+                             __field(u64, offset)
                              __field(u32, size)
                              ),
 
@@ -152,7 +152,7 @@ TRACE_EVENT(i915_vma_unbind,
                            __entry->size = vma->node.size;
                            ),
 
-            TP_printk("obj=%p, offset=%08x size=%x vm=%p",
+            TP_printk("obj=%p, offset=%016llx size=%x vm=%p",
                       __entry->obj, __entry->offset, __entry->size, __entry->vm)
 );
 
diff --git a/drivers/gpu/drm/i915/i915_ums.c b/drivers/gpu/drm/i915/i915_ums.c
deleted file mode 100644
index d10fe3e9c49f..000000000000
--- a/drivers/gpu/drm/i915/i915_ums.c
+++ /dev/null
@@ -1,552 +0,0 @@
-/*
- *
- * Copyright 2008 (c) Intel Corporation
- *   Jesse Barnes <jbarnes@virtuousgeek.org>
- * Copyright 2013 (c) Intel Corporation
- *   Daniel Vetter <daniel.vetter@ffwll.ch>
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sub license, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
- * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
- * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include <drm/drmP.h>
-#include <drm/i915_drm.h>
-#include "intel_drv.h"
-#include "i915_reg.h"
-
-static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
-{
-        struct drm_i915_private *dev_priv = dev->dev_private;
-        u32     dpll_reg;
-
-        /* On IVB, 3rd pipe shares PLL with another one */
-        if (pipe > 1)
-                return false;
-
-        if (HAS_PCH_SPLIT(dev))
-                dpll_reg = PCH_DPLL(pipe);
-        else
-                dpll_reg = (pipe == PIPE_A) ? _DPLL_A : _DPLL_B;
-
-        return (I915_READ(dpll_reg) & DPLL_VCO_ENABLE);
-}
-
-static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
-{
-        struct drm_i915_private *dev_priv = dev->dev_private;
-        unsigned long reg = (pipe == PIPE_A ? _PALETTE_A : _PALETTE_B);
-        u32 *array;
-        int i;
-
-        if (!i915_pipe_enabled(dev, pipe))
-                return;
-
-        if (HAS_PCH_SPLIT(dev))
-                reg = (pipe == PIPE_A) ? _LGC_PALETTE_A : _LGC_PALETTE_B;
-
-        if (pipe == PIPE_A)
-                array = dev_priv->regfile.save_palette_a;
-        else
-                array = dev_priv->regfile.save_palette_b;
-
-        for (i = 0; i < 256; i++)
-                array[i] = I915_READ(reg + (i << 2));
-}
-
-static void i915_restore_palette(struct drm_device *dev, enum pipe pipe)
-{
-        struct drm_i915_private *dev_priv = dev->dev_private;
-        unsigned long reg = (pipe == PIPE_A ? _PALETTE_A : _PALETTE_B);
-        u32 *array;
-        int i;
-
-        if (!i915_pipe_enabled(dev, pipe))
-                return;
-
-        if (HAS_PCH_SPLIT(dev))
-                reg = (pipe == PIPE_A) ? _LGC_PALETTE_A : _LGC_PALETTE_B;
-
-        if (pipe == PIPE_A)
-                array = dev_priv->regfile.save_palette_a;
-        else
-                array = dev_priv->regfile.save_palette_b;
-
-        for (i = 0; i < 256; i++)
-                I915_WRITE(reg + (i << 2), array[i]);
-}
-
-void i915_save_display_reg(struct drm_device *dev)
-{
-        struct drm_i915_private *dev_priv = dev->dev_private;
-        int i;
-
-        /* Cursor state */
-        dev_priv->regfile.saveCURACNTR = I915_READ(_CURACNTR);
-        dev_priv->regfile.saveCURAPOS = I915_READ(_CURAPOS);
-        dev_priv->regfile.saveCURABASE = I915_READ(_CURABASE);
-        dev_priv->regfile.saveCURBCNTR = I915_READ(_CURBCNTR);
-        dev_priv->regfile.saveCURBPOS = I915_READ(_CURBPOS);
-        dev_priv->regfile.saveCURBBASE = I915_READ(_CURBBASE);
-        if (IS_GEN2(dev))
-                dev_priv->regfile.saveCURSIZE = I915_READ(CURSIZE);
-
-        if (HAS_PCH_SPLIT(dev)) {
-                dev_priv->regfile.savePCH_DREF_CONTROL = I915_READ(PCH_DREF_CONTROL);
-                dev_priv->regfile.saveDISP_ARB_CTL = I915_READ(DISP_ARB_CTL);
-        }
-
-        /* Pipe & plane A info */
-        dev_priv->regfile.savePIPEACONF = I915_READ(_PIPEACONF);
-        dev_priv->regfile.savePIPEASRC = I915_READ(_PIPEASRC);
-        if (HAS_PCH_SPLIT(dev)) {
-                dev_priv->regfile.saveFPA0 = I915_READ(_PCH_FPA0);
-                dev_priv->regfile.saveFPA1 = I915_READ(_PCH_FPA1);
-                dev_priv->regfile.saveDPLL_A = I915_READ(_PCH_DPLL_A);
-        } else {
-                dev_priv->regfile.saveFPA0 = I915_READ(_FPA0);
-                dev_priv->regfile.saveFPA1 = I915_READ(_FPA1);
-                dev_priv->regfile.saveDPLL_A = I915_READ(_DPLL_A);
-        }
-        if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
-                dev_priv->regfile.saveDPLL_A_MD = I915_READ(_DPLL_A_MD);
-        dev_priv->regfile.saveHTOTAL_A = I915_READ(_HTOTAL_A);
-        dev_priv->regfile.saveHBLANK_A = I915_READ(_HBLANK_A);
-        dev_priv->regfile.saveHSYNC_A = I915_READ(_HSYNC_A);
-        dev_priv->regfile.saveVTOTAL_A = I915_READ(_VTOTAL_A);
-        dev_priv->regfile.saveVBLANK_A = I915_READ(_VBLANK_A);
-        dev_priv->regfile.saveVSYNC_A = I915_READ(_VSYNC_A);
-        if (!HAS_PCH_SPLIT(dev))
-                dev_priv->regfile.saveBCLRPAT_A = I915_READ(_BCLRPAT_A);
-
-        if (HAS_PCH_SPLIT(dev)) {
-                dev_priv->regfile.savePIPEA_DATA_M1 = I915_READ(_PIPEA_DATA_M1);
-                dev_priv->regfile.savePIPEA_DATA_N1 = I915_READ(_PIPEA_DATA_N1);
-                dev_priv->regfile.savePIPEA_LINK_M1 = I915_READ(_PIPEA_LINK_M1);
-                dev_priv->regfile.savePIPEA_LINK_N1 = I915_READ(_PIPEA_LINK_N1);
-
-                dev_priv->regfile.saveFDI_TXA_CTL = I915_READ(_FDI_TXA_CTL);
-                dev_priv->regfile.saveFDI_RXA_CTL = I915_READ(_FDI_RXA_CTL);
-
-                dev_priv->regfile.savePFA_CTL_1 = I915_READ(_PFA_CTL_1);
-                dev_priv->regfile.savePFA_WIN_SZ = I915_READ(_PFA_WIN_SZ);
-                dev_priv->regfile.savePFA_WIN_POS = I915_READ(_PFA_WIN_POS);
-
-                dev_priv->regfile.saveTRANSACONF = I915_READ(_PCH_TRANSACONF);
-                dev_priv->regfile.saveTRANS_HTOTAL_A = I915_READ(_PCH_TRANS_HTOTAL_A);
-                dev_priv->regfile.saveTRANS_HBLANK_A = I915_READ(_PCH_TRANS_HBLANK_A);
-                dev_priv->regfile.saveTRANS_HSYNC_A = I915_READ(_PCH_TRANS_HSYNC_A);
-                dev_priv->regfile.saveTRANS_VTOTAL_A = I915_READ(_PCH_TRANS_VTOTAL_A);
-                dev_priv->regfile.saveTRANS_VBLANK_A = I915_READ(_PCH_TRANS_VBLANK_A);
-                dev_priv->regfile.saveTRANS_VSYNC_A = I915_READ(_PCH_TRANS_VSYNC_A);
-        }
-
-        dev_priv->regfile.saveDSPACNTR = I915_READ(_DSPACNTR);
-        dev_priv->regfile.saveDSPASTRIDE = I915_READ(_DSPASTRIDE);
-        dev_priv->regfile.saveDSPASIZE = I915_READ(_DSPASIZE);
-        dev_priv->regfile.saveDSPAPOS = I915_READ(_DSPAPOS);
-        dev_priv->regfile.saveDSPAADDR = I915_READ(_DSPAADDR);
-        if (INTEL_INFO(dev)->gen >= 4) {
-                dev_priv->regfile.saveDSPASURF = I915_READ(_DSPASURF);
-                dev_priv->regfile.saveDSPATILEOFF = I915_READ(_DSPATILEOFF);
-        }
-        i915_save_palette(dev, PIPE_A);
-        dev_priv->regfile.savePIPEASTAT = I915_READ(_PIPEASTAT);
-
-        /* Pipe & plane B info */
-        dev_priv->regfile.savePIPEBCONF = I915_READ(_PIPEBCONF);
-        dev_priv->regfile.savePIPEBSRC = I915_READ(_PIPEBSRC);
-        if (HAS_PCH_SPLIT(dev)) {
-                dev_priv->regfile.saveFPB0 = I915_READ(_PCH_FPB0);
-                dev_priv->regfile.saveFPB1 = I915_READ(_PCH_FPB1);
-                dev_priv->regfile.saveDPLL_B = I915_READ(_PCH_DPLL_B);
-        } else {
-                dev_priv->regfile.saveFPB0 = I915_READ(_FPB0);
-                dev_priv->regfile.saveFPB1 = I915_READ(_FPB1);
-                dev_priv->regfile.saveDPLL_B = I915_READ(_DPLL_B);
-        }
-        if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
-                dev_priv->regfile.saveDPLL_B_MD = I915_READ(_DPLL_B_MD);
-        dev_priv->regfile.saveHTOTAL_B = I915_READ(_HTOTAL_B);
-        dev_priv->regfile.saveHBLANK_B = I915_READ(_HBLANK_B);
-        dev_priv->regfile.saveHSYNC_B = I915_READ(_HSYNC_B);
-        dev_priv->regfile.saveVTOTAL_B = I915_READ(_VTOTAL_B);
-        dev_priv->regfile.saveVBLANK_B = I915_READ(_VBLANK_B);
-        dev_priv->regfile.saveVSYNC_B = I915_READ(_VSYNC_B);
-        if (!HAS_PCH_SPLIT(dev))
-                dev_priv->regfile.saveBCLRPAT_B = I915_READ(_BCLRPAT_B);
-
-        if (HAS_PCH_SPLIT(dev)) {
-                dev_priv->regfile.savePIPEB_DATA_M1 = I915_READ(_PIPEB_DATA_M1);
-                dev_priv->regfile.savePIPEB_DATA_N1 = I915_READ(_PIPEB_DATA_N1);
-                dev_priv->regfile.savePIPEB_LINK_M1 = I915_READ(_PIPEB_LINK_M1);
-                dev_priv->regfile.savePIPEB_LINK_N1 = I915_READ(_PIPEB_LINK_N1);
-
-                dev_priv->regfile.saveFDI_TXB_CTL = I915_READ(_FDI_TXB_CTL);
-                dev_priv->regfile.saveFDI_RXB_CTL = I915_READ(_FDI_RXB_CTL);
-
-                dev_priv->regfile.savePFB_CTL_1 = I915_READ(_PFB_CTL_1);
-                dev_priv->regfile.savePFB_WIN_SZ = I915_READ(_PFB_WIN_SZ);
-                dev_priv->regfile.savePFB_WIN_POS = I915_READ(_PFB_WIN_POS);
-
-                dev_priv->regfile.saveTRANSBCONF = I915_READ(_PCH_TRANSBCONF);
-                dev_priv->regfile.saveTRANS_HTOTAL_B = I915_READ(_PCH_TRANS_HTOTAL_B);
-                dev_priv->regfile.saveTRANS_HBLANK_B = I915_READ(_PCH_TRANS_HBLANK_B);
-                dev_priv->regfile.saveTRANS_HSYNC_B = I915_READ(_PCH_TRANS_HSYNC_B);
-                dev_priv->regfile.saveTRANS_VTOTAL_B = I915_READ(_PCH_TRANS_VTOTAL_B);
-                dev_priv->regfile.saveTRANS_VBLANK_B = I915_READ(_PCH_TRANS_VBLANK_B);
-                dev_priv->regfile.saveTRANS_VSYNC_B = I915_READ(_PCH_TRANS_VSYNC_B);
-        }
-
-        dev_priv->regfile.saveDSPBCNTR = I915_READ(_DSPBCNTR);
-        dev_priv->regfile.saveDSPBSTRIDE = I915_READ(_DSPBSTRIDE);
-        dev_priv->regfile.saveDSPBSIZE = I915_READ(_DSPBSIZE);
-        dev_priv->regfile.saveDSPBPOS = I915_READ(_DSPBPOS);
-        dev_priv->regfile.saveDSPBADDR = I915_READ(_DSPBADDR);
-        if (INTEL_INFO(dev)->gen >= 4) {
-                dev_priv->regfile.saveDSPBSURF = I915_READ(_DSPBSURF);
-                dev_priv->regfile.saveDSPBTILEOFF = I915_READ(_DSPBTILEOFF);
-        }
-        i915_save_palette(dev, PIPE_B);
-        dev_priv->regfile.savePIPEBSTAT = I915_READ(_PIPEBSTAT);
-
-        /* Fences */
-        switch (INTEL_INFO(dev)->gen) {
-        case 7:
-        case 6:
-                for (i = 0; i < 16; i++)
-                        dev_priv->regfile.saveFENCE[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
-                break;
-        case 5:
-        case 4:
-                for (i = 0; i < 16; i++)
-                        dev_priv->regfile.saveFENCE[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
-                break;
-        case 3:
-                if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
-                        for (i = 0; i < 8; i++)
-                                dev_priv->regfile.saveFENCE[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
-        case 2:
-                for (i = 0; i < 8; i++)
-                        dev_priv->regfile.saveFENCE[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
-                break;
-        }
-
-        /* CRT state */
-        if (HAS_PCH_SPLIT(dev))
-                dev_priv->regfile.saveADPA = I915_READ(PCH_ADPA);
-        else
-                dev_priv->regfile.saveADPA = I915_READ(ADPA);
-
-        /* Display Port state */
-        if (SUPPORTS_INTEGRATED_DP(dev)) {
-                dev_priv->regfile.saveDP_B = I915_READ(DP_B);
-                dev_priv->regfile.saveDP_C = I915_READ(DP_C);
-                dev_priv->regfile.saveDP_D = I915_READ(DP_D);
-                dev_priv->regfile.savePIPEA_GMCH_DATA_M = I915_READ(_PIPEA_DATA_M_G4X);
-                dev_priv->regfile.savePIPEB_GMCH_DATA_M = I915_READ(_PIPEB_DATA_M_G4X);
-                dev_priv->regfile.savePIPEA_GMCH_DATA_N = I915_READ(_PIPEA_DATA_N_G4X);
-                dev_priv->regfile.savePIPEB_GMCH_DATA_N = I915_READ(_PIPEB_DATA_N_G4X);
-                dev_priv->regfile.savePIPEA_DP_LINK_M = I915_READ(_PIPEA_LINK_M_G4X);
-                dev_priv->regfile.savePIPEB_DP_LINK_M = I915_READ(_PIPEB_LINK_M_G4X);
-                dev_priv->regfile.savePIPEA_DP_LINK_N = I915_READ(_PIPEA_LINK_N_G4X);
-                dev_priv->regfile.savePIPEB_DP_LINK_N = I915_READ(_PIPEB_LINK_N_G4X);
-        }
-        /* FIXME: regfile.save TV & SDVO state */
-
-        /* Panel fitter */
-        if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev)) {
-                dev_priv->regfile.savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
-                dev_priv->regfile.savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
-        }
-
-        /* Backlight */
-        if (INTEL_INFO(dev)->gen <= 4)
-                pci_read_config_byte(dev->pdev, PCI_LBPC,
-                                     &dev_priv->regfile.saveLBB);
-
-        if (HAS_PCH_SPLIT(dev)) {
-                dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_PCH_CTL1);
-                dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_PCH_CTL2);
-                dev_priv->regfile.saveBLC_CPU_PWM_CTL = I915_READ(BLC_PWM_CPU_CTL);
-                dev_priv->regfile.saveBLC_CPU_PWM_CTL2 = I915_READ(BLC_PWM_CPU_CTL2);
-        } else {
-                dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
-                if (INTEL_INFO(dev)->gen >= 4)
-                        dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
-                dev_priv->regfile.saveBLC_HIST_CTL = I915_READ(BLC_HIST_CTL);
-        }
-
-        return;
-}
-
-void i915_restore_display_reg(struct drm_device *dev)
-{
-        struct drm_i915_private *dev_priv = dev->dev_private;
-        int dpll_a_reg, fpa0_reg, fpa1_reg;
-        int dpll_b_reg, fpb0_reg, fpb1_reg;
-        int i;
-
-        /* Backlight */
-        if (INTEL_INFO(dev)->gen <= 4)
-                pci_write_config_byte(dev->pdev, PCI_LBPC,
-                                      dev_priv->regfile.saveLBB);
-
-        if (HAS_PCH_SPLIT(dev)) {
-                I915_WRITE(BLC_PWM_PCH_CTL1, dev_priv->regfile.saveBLC_PWM_CTL);
-                I915_WRITE(BLC_PWM_PCH_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2);
-                /* NOTE: BLC_PWM_CPU_CTL must be written after BLC_PWM_CPU_CTL2;
-                 * otherwise we get blank eDP screen after S3 on some machines
-                 */
-                I915_WRITE(BLC_PWM_CPU_CTL2, dev_priv->regfile.saveBLC_CPU_PWM_CTL2);
-                I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->regfile.saveBLC_CPU_PWM_CTL);
-        } else {
-                if (INTEL_INFO(dev)->gen >= 4)
-                        I915_WRITE(BLC_PWM_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2);
-                I915_WRITE(BLC_PWM_CTL, dev_priv->regfile.saveBLC_PWM_CTL);
-                I915_WRITE(BLC_HIST_CTL, dev_priv->regfile.saveBLC_HIST_CTL);
-        }
-
-        /* Panel fitter */
-        if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev)) {
-                I915_WRITE(PFIT_PGM_RATIOS, dev_priv->regfile.savePFIT_PGM_RATIOS);
-                I915_WRITE(PFIT_CONTROL, dev_priv->regfile.savePFIT_CONTROL);
-        }
-
-        /* Display port ratios (must be done before clock is set) */
-        if (SUPPORTS_INTEGRATED_DP(dev)) {
-                I915_WRITE(_PIPEA_DATA_M_G4X, dev_priv->regfile.savePIPEA_GMCH_DATA_M);
-                I915_WRITE(_PIPEB_DATA_M_G4X, dev_priv->regfile.savePIPEB_GMCH_DATA_M);
-                I915_WRITE(_PIPEA_DATA_N_G4X, dev_priv->regfile.savePIPEA_GMCH_DATA_N);
-                I915_WRITE(_PIPEB_DATA_N_G4X, dev_priv->regfile.savePIPEB_GMCH_DATA_N);
-                I915_WRITE(_PIPEA_LINK_M_G4X, dev_priv->regfile.savePIPEA_DP_LINK_M);
-                I915_WRITE(_PIPEB_LINK_M_G4X, dev_priv->regfile.savePIPEB_DP_LINK_M);
-                I915_WRITE(_PIPEA_LINK_N_G4X, dev_priv->regfile.savePIPEA_DP_LINK_N);
-                I915_WRITE(_PIPEB_LINK_N_G4X, dev_priv->regfile.savePIPEB_DP_LINK_N);
-        }
-
-        /* Fences */
-        switch (INTEL_INFO(dev)->gen) {
-        case 7:
-        case 6:
-                for (i = 0; i < 16; i++)
-                        I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), dev_priv->regfile.saveFENCE[i]);
-                break;
-        case 5:
-        case 4:
-                for (i = 0; i < 16; i++)
-                        I915_WRITE64(FENCE_REG_965_0 + (i * 8), dev_priv->regfile.saveFENCE[i]);
-                break;
-        case 3:
-        case 2:
-                if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
-                        for (i = 0; i < 8; i++)
-                                I915_WRITE(FENCE_REG_945_8 + (i * 4), dev_priv->regfile.saveFENCE[i+8]);
-                for (i = 0; i < 8; i++)
-                        I915_WRITE(FENCE_REG_830_0 + (i * 4), dev_priv->regfile.saveFENCE[i]);
-                break;
-        }
-
-
-        if (HAS_PCH_SPLIT(dev)) {
-                dpll_a_reg = _PCH_DPLL_A;
-                dpll_b_reg = _PCH_DPLL_B;
-                fpa0_reg = _PCH_FPA0;
-                fpb0_reg = _PCH_FPB0;
-                fpa1_reg = _PCH_FPA1;
-                fpb1_reg = _PCH_FPB1;
-        } else {
-                dpll_a_reg = _DPLL_A;
-                dpll_b_reg = _DPLL_B;
-                fpa0_reg = _FPA0;
-                fpb0_reg = _FPB0;
-                fpa1_reg = _FPA1;
-                fpb1_reg = _FPB1;
-        }
-
-        if (HAS_PCH_SPLIT(dev)) {
-                I915_WRITE(PCH_DREF_CONTROL, dev_priv->regfile.savePCH_DREF_CONTROL);
-                I915_WRITE(DISP_ARB_CTL, dev_priv->regfile.saveDISP_ARB_CTL);
-        }
-
-        /* Pipe & plane A info */
-        /* Prime the clock */
-        if (dev_priv->regfile.saveDPLL_A & DPLL_VCO_ENABLE) {
-                I915_WRITE(dpll_a_reg, dev_priv->regfile.saveDPLL_A &
-                           ~DPLL_VCO_ENABLE);
-                POSTING_READ(dpll_a_reg);
-                udelay(150);
-        }
-        I915_WRITE(fpa0_reg, dev_priv->regfile.saveFPA0);
-        I915_WRITE(fpa1_reg, dev_priv->regfile.saveFPA1);
-        /* Actually enable it */
-        I915_WRITE(dpll_a_reg, dev_priv->regfile.saveDPLL_A);
-        POSTING_READ(dpll_a_reg);
-        udelay(150);
-        if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
-                I915_WRITE(_DPLL_A_MD, dev_priv->regfile.saveDPLL_A_MD);
-                POSTING_READ(_DPLL_A_MD);
-        }
-        udelay(150);
-
-        /* Restore mode */
-        I915_WRITE(_HTOTAL_A, dev_priv->regfile.saveHTOTAL_A);
-        I915_WRITE(_HBLANK_A, dev_priv->regfile.saveHBLANK_A);
-        I915_WRITE(_HSYNC_A, dev_priv->regfile.saveHSYNC_A);
-        I915_WRITE(_VTOTAL_A, dev_priv->regfile.saveVTOTAL_A);
-        I915_WRITE(_VBLANK_A, dev_priv->regfile.saveVBLANK_A);
-        I915_WRITE(_VSYNC_A, dev_priv->regfile.saveVSYNC_A);
-        if (!HAS_PCH_SPLIT(dev))
-                I915_WRITE(_BCLRPAT_A, dev_priv->regfile.saveBCLRPAT_A);
-
-        if (HAS_PCH_SPLIT(dev)) {
-                I915_WRITE(_PIPEA_DATA_M1, dev_priv->regfile.savePIPEA_DATA_M1);
-                I915_WRITE(_PIPEA_DATA_N1, dev_priv->regfile.savePIPEA_DATA_N1);
-                I915_WRITE(_PIPEA_LINK_M1, dev_priv->regfile.savePIPEA_LINK_M1);
-                I915_WRITE(_PIPEA_LINK_N1, dev_priv->regfile.savePIPEA_LINK_N1);
-
-                I915_WRITE(_FDI_RXA_CTL, dev_priv->regfile.saveFDI_RXA_CTL);
-                I915_WRITE(_FDI_TXA_CTL, dev_priv->regfile.saveFDI_TXA_CTL);
-
-                I915_WRITE(_PFA_CTL_1, dev_priv->regfile.savePFA_CTL_1);
-                I915_WRITE(_PFA_WIN_SZ, dev_priv->regfile.savePFA_WIN_SZ);
-                I915_WRITE(_PFA_WIN_POS, dev_priv->regfile.savePFA_WIN_POS);
-
-                I915_WRITE(_PCH_TRANSACONF, dev_priv->regfile.saveTRANSACONF);
-                I915_WRITE(_PCH_TRANS_HTOTAL_A, dev_priv->regfile.saveTRANS_HTOTAL_A);
-                I915_WRITE(_PCH_TRANS_HBLANK_A, dev_priv->regfile.saveTRANS_HBLANK_A);
-                I915_WRITE(_PCH_TRANS_HSYNC_A, dev_priv->regfile.saveTRANS_HSYNC_A);
-                I915_WRITE(_PCH_TRANS_VTOTAL_A, dev_priv->regfile.saveTRANS_VTOTAL_A);
-                I915_WRITE(_PCH_TRANS_VBLANK_A, dev_priv->regfile.saveTRANS_VBLANK_A);
-                I915_WRITE(_PCH_TRANS_VSYNC_A, dev_priv->regfile.saveTRANS_VSYNC_A);
-        }
-
-        /* Restore plane info */
-        I915_WRITE(_DSPASIZE, dev_priv->regfile.saveDSPASIZE);
-        I915_WRITE(_DSPAPOS, dev_priv->regfile.saveDSPAPOS);
-        I915_WRITE(_PIPEASRC, dev_priv->regfile.savePIPEASRC);
-        I915_WRITE(_DSPAADDR, dev_priv->regfile.saveDSPAADDR);
-        I915_WRITE(_DSPASTRIDE, dev_priv->regfile.saveDSPASTRIDE);
-        if (INTEL_INFO(dev)->gen >= 4) {
-                I915_WRITE(_DSPASURF, dev_priv->regfile.saveDSPASURF);
-                I915_WRITE(_DSPATILEOFF, dev_priv->regfile.saveDSPATILEOFF);
-        }
-
-        I915_WRITE(_PIPEACONF, dev_priv->regfile.savePIPEACONF);
-
-        i915_restore_palette(dev, PIPE_A);
-        /* Enable the plane */
-        I915_WRITE(_DSPACNTR, dev_priv->regfile.saveDSPACNTR);
-        I915_WRITE(_DSPAADDR, I915_READ(_DSPAADDR));
-
-        /* Pipe & plane B info */
-        if (dev_priv->regfile.saveDPLL_B & DPLL_VCO_ENABLE) {
-                I915_WRITE(dpll_b_reg, dev_priv->regfile.saveDPLL_B &
-                           ~DPLL_VCO_ENABLE);
-                POSTING_READ(dpll_b_reg);
-                udelay(150);
-        }
-        I915_WRITE(fpb0_reg, dev_priv->regfile.saveFPB0);
-        I915_WRITE(fpb1_reg, dev_priv->regfile.saveFPB1);
-        /* Actually enable it */
-        I915_WRITE(dpll_b_reg, dev_priv->regfile.saveDPLL_B);
-        POSTING_READ(dpll_b_reg);
-        udelay(150);
-        if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
-                I915_WRITE(_DPLL_B_MD, dev_priv->regfile.saveDPLL_B_MD);
-                POSTING_READ(_DPLL_B_MD);
-        }
-        udelay(150);
-
-        /* Restore mode */
-        I915_WRITE(_HTOTAL_B, dev_priv->regfile.saveHTOTAL_B);
-        I915_WRITE(_HBLANK_B, dev_priv->regfile.saveHBLANK_B);
-        I915_WRITE(_HSYNC_B, dev_priv->regfile.saveHSYNC_B);
-        I915_WRITE(_VTOTAL_B, dev_priv->regfile.saveVTOTAL_B);
-        I915_WRITE(_VBLANK_B, dev_priv->regfile.saveVBLANK_B);
-        I915_WRITE(_VSYNC_B, dev_priv->regfile.saveVSYNC_B);
-        if (!HAS_PCH_SPLIT(dev))
-                I915_WRITE(_BCLRPAT_B, dev_priv->regfile.saveBCLRPAT_B);
-
-        if (HAS_PCH_SPLIT(dev)) {
-                I915_WRITE(_PIPEB_DATA_M1, dev_priv->regfile.savePIPEB_DATA_M1);
-                I915_WRITE(_PIPEB_DATA_N1, dev_priv->regfile.savePIPEB_DATA_N1);
-                I915_WRITE(_PIPEB_LINK_M1, dev_priv->regfile.savePIPEB_LINK_M1);
-                I915_WRITE(_PIPEB_LINK_N1, dev_priv->regfile.savePIPEB_LINK_N1);
-
-                I915_WRITE(_FDI_RXB_CTL, dev_priv->regfile.saveFDI_RXB_CTL);
-                I915_WRITE(_FDI_TXB_CTL, dev_priv->regfile.saveFDI_TXB_CTL);
-
-                I915_WRITE(_PFB_CTL_1, dev_priv->regfile.savePFB_CTL_1);
-                I915_WRITE(_PFB_WIN_SZ, dev_priv->regfile.savePFB_WIN_SZ);
-                I915_WRITE(_PFB_WIN_POS, dev_priv->regfile.savePFB_WIN_POS);
-
-                I915_WRITE(_PCH_TRANSBCONF, dev_priv->regfile.saveTRANSBCONF);
-                I915_WRITE(_PCH_TRANS_HTOTAL_B, dev_priv->regfile.saveTRANS_HTOTAL_B);
-                I915_WRITE(_PCH_TRANS_HBLANK_B, dev_priv->regfile.saveTRANS_HBLANK_B);
-                I915_WRITE(_PCH_TRANS_HSYNC_B, dev_priv->regfile.saveTRANS_HSYNC_B);
-                I915_WRITE(_PCH_TRANS_VTOTAL_B, dev_priv->regfile.saveTRANS_VTOTAL_B);
-                I915_WRITE(_PCH_TRANS_VBLANK_B, dev_priv->regfile.saveTRANS_VBLANK_B);
-                I915_WRITE(_PCH_TRANS_VSYNC_B, dev_priv->regfile.saveTRANS_VSYNC_B);
-        }
-
-        /* Restore plane info */
-        I915_WRITE(_DSPBSIZE, dev_priv->regfile.saveDSPBSIZE);
-        I915_WRITE(_DSPBPOS, dev_priv->regfile.saveDSPBPOS);
-        I915_WRITE(_PIPEBSRC, dev_priv->regfile.savePIPEBSRC);
-        I915_WRITE(_DSPBADDR, dev_priv->regfile.saveDSPBADDR);
-        I915_WRITE(_DSPBSTRIDE, dev_priv->regfile.saveDSPBSTRIDE);
-        if (INTEL_INFO(dev)->gen >= 4) {
-                I915_WRITE(_DSPBSURF, dev_priv->regfile.saveDSPBSURF);
-                I915_WRITE(_DSPBTILEOFF, dev_priv->regfile.saveDSPBTILEOFF);
-        }
-
-        I915_WRITE(_PIPEBCONF, dev_priv->regfile.savePIPEBCONF);
-
-        i915_restore_palette(dev, PIPE_B);
-        /* Enable the plane */
-        I915_WRITE(_DSPBCNTR, dev_priv->regfile.saveDSPBCNTR);
-        I915_WRITE(_DSPBADDR, I915_READ(_DSPBADDR));
-
-        /* Cursor state */
-        I915_WRITE(_CURAPOS, dev_priv->regfile.saveCURAPOS);
-        I915_WRITE(_CURACNTR, dev_priv->regfile.saveCURACNTR);
-        I915_WRITE(_CURABASE, dev_priv->regfile.saveCURABASE);
-        I915_WRITE(_CURBPOS, dev_priv->regfile.saveCURBPOS);
-        I915_WRITE(_CURBCNTR, dev_priv->regfile.saveCURBCNTR);
-        I915_WRITE(_CURBBASE, dev_priv->regfile.saveCURBBASE);
-        if (IS_GEN2(dev))
-                I915_WRITE(CURSIZE, dev_priv->regfile.saveCURSIZE);
-
-        /* CRT state */
-        if (HAS_PCH_SPLIT(dev))
-                I915_WRITE(PCH_ADPA, dev_priv->regfile.saveADPA);
-        else
-                I915_WRITE(ADPA, dev_priv->regfile.saveADPA);
-
-        /* Display Port state */
-        if (SUPPORTS_INTEGRATED_DP(dev)) {
-                I915_WRITE(DP_B, dev_priv->regfile.saveDP_B);
-                I915_WRITE(DP_C, dev_priv->regfile.saveDP_C);
-                I915_WRITE(DP_D, dev_priv->regfile.saveDP_D);
-        }
-        /* FIXME: restore TV & SDVO state */
-
-        return;
-}
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
new file mode 100644
index 000000000000..5eee75bff170
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -0,0 +1,264 @@
+/*
+ * Copyright(c) 2011-2015 Intel Corporation. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#include "intel_drv.h"
+#include "i915_vgpu.h"
+
+/**
+ * DOC: Intel GVT-g guest support
+ *
+ * Intel GVT-g is a graphics virtualization technology which shares the
+ * GPU among multiple virtual machines on a time-sharing basis. Each
+ * virtual machine is presented a virtual GPU (vGPU), which has equivalent
+ * features as the underlying physical GPU (pGPU), so i915 driver can run
+ * seamlessly in a virtual machine. This file provides vGPU specific
+ * optimizations when running in a virtual machine, to reduce the complexity
+ * of vGPU emulation and to improve the overall performance.
+ *
+ * A primary function introduced here is so-called "address space ballooning"
+ * technique. Intel GVT-g partitions global graphics memory among multiple VMs,
+ * so each VM can directly access a portion of the memory without hypervisor's
+ * intervention, e.g. filling textures or queuing commands. However with the
+ * partitioning an unmodified i915 driver would assume a smaller graphics
+ * memory starting from address ZERO, then requires vGPU emulation module to
+ * translate the graphics address between 'guest view' and 'host view', for
+ * all registers and command opcodes which contain a graphics memory address.
+ * To reduce the complexity, Intel GVT-g introduces "address space ballooning",
+ * by telling the exact partitioning knowledge to each guest i915 driver, which
+ * then reserves and prevents non-allocated portions from allocation. Thus vGPU
+ * emulation module only needs to scan and validate graphics addresses without
+ * complexity of address translation.
+ *
+ */
+
+/**
+ * i915_check_vgpu - detect virtual GPU
+ * @dev: drm device *
+ *
+ * This function is called at the initialization stage, to detect whether
+ * running on a vGPU.
+ */
+void i915_check_vgpu(struct drm_device *dev)
+{
+        struct drm_i915_private *dev_priv = to_i915(dev);
+        uint64_t magic;
+        uint32_t version;
+
+        BUILD_BUG_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE);
+
+        if (!IS_HASWELL(dev))
+                return;
+
+        magic = readq(dev_priv->regs + vgtif_reg(magic));
+        if (magic != VGT_MAGIC)
+                return;
+
+        version = INTEL_VGT_IF_VERSION_ENCODE(
+                readw(dev_priv->regs + vgtif_reg(version_major)),
+                readw(dev_priv->regs + vgtif_reg(version_minor)));
+        if (version != INTEL_VGT_IF_VERSION) {
+                DRM_INFO("VGT interface version mismatch!\n");
+                return;
+        }
+
+        dev_priv->vgpu.active = true;
+        DRM_INFO("Virtual GPU for Intel GVT-g detected.\n");
+}
+
+struct _balloon_info_ {
+        /*
+         * There are up to 2 regions per mappable/unmappable graphic
+         * memory that might be ballooned. Here, index 0/1 is for mappable
+         * graphic memory, 2/3 for unmappable graphic memory.
+         */
+        struct drm_mm_node space[4];
+};
+
+static struct _balloon_info_ bl_info;
+
+/**
+ * intel_vgt_deballoon - deballoon reserved graphics address trunks
+ *
+ * This function is called to deallocate the ballooned-out graphic memory, when
+ * driver is unloaded or when ballooning fails.
+ */
+void intel_vgt_deballoon(void)
+{
+        int i;
+
+        DRM_DEBUG("VGT deballoon.\n");
+
+        for (i = 0; i < 4; i++) {
+                if (bl_info.space[i].allocated)
+                        drm_mm_remove_node(&bl_info.space[i]);
+        }
+
+        memset(&bl_info, 0, sizeof(bl_info));
+}
+
+static int vgt_balloon_space(struct drm_mm *mm,
+                             struct drm_mm_node *node,
+                             unsigned long start, unsigned long end)
+{
+        unsigned long size = end - start;
+
+        if (start == end)
+                return -EINVAL;
+
+        DRM_INFO("balloon space: range [ 0x%lx - 0x%lx ] %lu KiB.\n",
+                 start, end, size / 1024);
+
+        node->start = start;
+        node->size = size;
+
+        return drm_mm_reserve_node(mm, node);
+}
+
+/**
+ * intel_vgt_balloon - balloon out reserved graphics address trunks
+ * @dev: drm device
+ *
+ * This function is called at the initialization stage, to balloon out the
+ * graphic address space allocated to other vGPUs, by marking these spaces as
+ * reserved. The ballooning related knowledge(starting address and size of
+ * the mappable/unmappable graphic memory) is described in the vgt_if structure
+ * in a reserved mmio range.
+ *
+ * To give an example, the drawing below depicts one typical scenario after
+ * ballooning. Here the vGPU1 has 2 pieces of graphic address spaces ballooned
+ * out each for the mappable and the non-mappable part. From the vGPU1 point of
+ * view, the total size is the same as the physical one, with the start address
+ * of its graphic space being zero. Yet there are some portions ballooned out(
+ * the shadow part, which are marked as reserved by drm allocator). From the
+ * host point of view, the graphic address space is partitioned by multiple
+ * vGPUs in different VMs.
+ *
+ *                        vGPU1 view         Host view
+ *             0 ------> +-----------+     +-----------+
+ *               ^       |///////////|     |   vGPU3   |
+ *               |       |///////////|     +-----------+
+ *               |       |///////////|     |   vGPU2   |
+ *               |       +-----------+     +-----------+
+ *        mappable GM    | available | ==> |   vGPU1   |
+ *               |       +-----------+     +-----------+
+ *               |       |///////////|     |           |
+ *               v       |///////////|     |   Host    |
+ *               +=======+===========+     +===========+
+ *               ^       |///////////|     |   vGPU3   |
+ *               |       |///////////|     +-----------+
+ *               |       |///////////|     |   vGPU2   |
+ *               |       +-----------+     +-----------+
+ *      unmappable GM    | available | ==> |   vGPU1   |
+ *               |       +-----------+     +-----------+
+ *               |       |///////////|     |           |
+ *               |       |///////////|     |   Host    |
+ *               v       |///////////|     |           |
+ * total GM size ------> +-----------+     +-----------+
+ *
+ * Returns:
+ * zero on success, non-zero if configuration invalid or ballooning failed
+ */
+int intel_vgt_balloon(struct drm_device *dev)
+{
+        struct drm_i915_private *dev_priv = to_i915(dev);
+        struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
+        unsigned long ggtt_vm_end = ggtt_vm->start + ggtt_vm->total;
+
+        unsigned long mappable_base, mappable_size, mappable_end;
+        unsigned long unmappable_base, unmappable_size, unmappable_end;
+        int ret;
+
+        mappable_base = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.base));
+        mappable_size = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.size));
+        unmappable_base = I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.base));
+        unmappable_size = I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.size));
+
+        mappable_end = mappable_base + mappable_size;
+        unmappable_end = unmappable_base + unmappable_size;
+
+        DRM_INFO("VGT ballooning configuration:\n");
+        DRM_INFO("Mappable graphic memory: base 0x%lx size %ldKiB\n",
+                 mappable_base, mappable_size / 1024);
+        DRM_INFO("Unmappable graphic memory: base 0x%lx size %ldKiB\n",
+                 unmappable_base, unmappable_size / 1024);
+
+        if (mappable_base < ggtt_vm->start ||
+            mappable_end > dev_priv->gtt.mappable_end ||
+            unmappable_base < dev_priv->gtt.mappable_end ||
+            unmappable_end > ggtt_vm_end) {
+                DRM_ERROR("Invalid ballooning configuration!\n");
+                return -EINVAL;
+        }
+
+        /* Unmappable graphic memory ballooning */
+        if (unmappable_base > dev_priv->gtt.mappable_end) {
+                ret = vgt_balloon_space(&ggtt_vm->mm,
+                                        &bl_info.space[2],
+                                        dev_priv->gtt.mappable_end,
+                                        unmappable_base);
+
+                if (ret)
+                        goto err;
+        }
+
+        /*
+         * No need to partition out the last physical page,
+         * because it is reserved to the guard page.
+         */
+        if (unmappable_end < ggtt_vm_end - PAGE_SIZE) {
+                ret = vgt_balloon_space(&ggtt_vm->mm,
+                                        &bl_info.space[3],
+                                        unmappable_end,
+                                        ggtt_vm_end - PAGE_SIZE);
+                if (ret)
+                        goto err;
+        }
+
+        /* Mappable graphic memory ballooning */
+        if (mappable_base > ggtt_vm->start) {
+                ret = vgt_balloon_space(&ggtt_vm->mm,
+                                        &bl_info.space[0],
+                                        ggtt_vm->start, mappable_base);
+
+                if (ret)
+                        goto err;
+        }
+
+        if (mappable_end < dev_priv->gtt.mappable_end) {
+                ret = vgt_balloon_space(&ggtt_vm->mm,
+                                        &bl_info.space[1],
+                                        mappable_end,
+                                        dev_priv->gtt.mappable_end);
+
+                if (ret)
+                        goto err;
+        }
+
+        DRM_INFO("VGT balloon successfully\n");
+        return 0;
+
+err:
+        DRM_ERROR("VGT balloon fail\n");
+        intel_vgt_deballoon();
+        return ret;
+}
diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h
new file mode 100644
index 000000000000..0db9ccf32605
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_vgpu.h
@@ -0,0 +1,91 @@
+/*
+ * Copyright(c) 2011-2015 Intel Corporation. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#ifndef _I915_VGPU_H_
+#define _I915_VGPU_H_
+
+/* The MMIO offset of the shared info between guest and host emulator */
+#define VGT_PVINFO_PAGE 0x78000
+#define VGT_PVINFO_SIZE 0x1000
+
+/*
+ * The following structure pages are defined in GEN MMIO space
+ * for virtualization. (One page for now)
+ */
+#define VGT_MAGIC         0x4776544776544776    /* 'vGTvGTvG' */
+#define VGT_VERSION_MAJOR 1
+#define VGT_VERSION_MINOR 0
+
+#define INTEL_VGT_IF_VERSION_ENCODE(major, minor) ((major) << 16 | (minor))
+#define INTEL_VGT_IF_VERSION \
+        INTEL_VGT_IF_VERSION_ENCODE(VGT_VERSION_MAJOR, VGT_VERSION_MINOR)
+
+struct vgt_if {
+        uint64_t magic;         /* VGT_MAGIC */
+        uint16_t version_major;
+        uint16_t version_minor;
+        uint32_t vgt_id;        /* ID of vGT instance */
+        uint32_t rsv1[12];      /* pad to offset 0x40 */
+        /*
+         *  Data structure to describe the balooning info of resources.
+         *  Each VM can only have one portion of continuous area for now.
+         *  (May support scattered resource in future)
+         *  (starting from offset 0x40)
+         */
+        struct {
+                /* Aperture register balooning */
+                struct {
+                        uint32_t base;
+                        uint32_t size;
+                } mappable_gmadr;       /* aperture */
+                /* GMADR register balooning */
+                struct {
+                        uint32_t base;
+                        uint32_t size;
+                } nonmappable_gmadr;    /* non aperture */
+                /* allowed fence registers */
+                uint32_t fence_num;
+                uint32_t rsv2[3];
+        } avail_rs;             /* available/assigned resource */
+        uint32_t rsv3[0x200 - 24];      /* pad to half page */
+        /*
+         * The bottom half page is for response from Gfx driver to hypervisor.
+         * Set to reserved fields temporarily by now.
+         */
+        uint32_t rsv4;
+        uint32_t display_ready; /* ready for display owner switch */
+        uint32_t rsv5[0x200 - 2];       /* pad to one page */
+} __packed;
+
+#define vgtif_reg(x) \
+        (VGT_PVINFO_PAGE + (long)&((struct vgt_if *)NULL)->x)
+
+/* vGPU display status to be used by the host side */
+#define VGT_DRV_DISPLAY_NOT_READY 0
+#define VGT_DRV_DISPLAY_READY     1  /* ready for display switch */
+
+extern void i915_check_vgpu(struct drm_device *dev);
+extern int intel_vgt_balloon(struct drm_device *dev);
+extern void intel_vgt_deballoon(void);
+
+#endif /* _I915_VGPU_H_ */
diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
index 19a9dd5408f3..011b8960fd75 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -134,9 +134,9 @@ int intel_atomic_commit(struct drm_device *dev,
          * FIXME:  The proper sequence here will eventually be:
          *
          * drm_atomic_helper_swap_state(dev, state)
-         * drm_atomic_helper_commit_pre_planes(dev, state);
+         * drm_atomic_helper_commit_modeset_disables(dev, state);
          * drm_atomic_helper_commit_planes(dev, state);
-         * drm_atomic_helper_commit_post_planes(dev, state);
+         * drm_atomic_helper_commit_modeset_enables(dev, state);
          * drm_atomic_helper_wait_for_vblanks(dev, state);
          * drm_atomic_helper_cleanup_planes(dev, state);
          * drm_atomic_state_free(state);
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 3f178258d9f9..c684085cb56a 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -662,6 +662,13 @@ parse_edp(struct drm_i915_private *dev_priv, struct bdb_header *bdb)
                               edp_link_params->vswing);
                 break;
         }
+
+        if (bdb->version >= 173) {
+                uint8_t vswing;
+
+                vswing = (edp->edp_vswing_preemph >> (panel_type * 4)) & 0xF;
+                dev_priv->vbt.edp_low_vswing = vswing == 0;
+        }
 }
 
 static void
diff --git a/drivers/gpu/drm/i915/intel_bios.h b/drivers/gpu/drm/i915/intel_bios.h
index a6a8710f665f..6afd5be33367 100644
--- a/drivers/gpu/drm/i915/intel_bios.h
+++ b/drivers/gpu/drm/i915/intel_bios.h
@@ -554,6 +554,7 @@ struct bdb_edp {
         /* ith bit indicates enabled/disabled for (i+1)th panel */
         u16 edp_s3d_feature;
         u16 edp_t3_optimization;
+        u64 edp_vswing_preemph;         /* v173 */
 } __packed;
 
 struct psr_table {
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index f14e8a2a022d..985d531aaf9e 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -139,6 +139,21 @@ static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
         { 0x00004014, 0x00000087 },
 };
 
+/* eDP 1.4 low vswing translation parameters */
+static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
+        { 0x00000018, 0x000000a8 },
+        { 0x00002016, 0x000000ab },
+        { 0x00006012, 0x000000a2 },
+        { 0x00008010, 0x00000088 },
+        { 0x00000018, 0x000000ab },
+        { 0x00004014, 0x000000a2 },
+        { 0x00006012, 0x000000a6 },
+        { 0x00000018, 0x000000a2 },
+        { 0x00005013, 0x0000009c },
+        { 0x00000018, 0x00000088 },
+};
+
+
 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
                                         /* Idx  NT mV   T mV    db  */
         { 0x00000018, 0x000000a0 },     /* 0:   400     400     0   */
@@ -187,7 +202,8 @@ static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
         u32 reg;
-        int i, n_hdmi_entries, hdmi_800mV_0dB;
+        int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_800mV_0dB,
+            size;
         int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
         const struct ddi_buf_trans *ddi_translations_fdi;
         const struct ddi_buf_trans *ddi_translations_dp;
@@ -198,7 +214,15 @@ static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port)
         if (IS_SKYLAKE(dev)) {
                 ddi_translations_fdi = NULL;
                 ddi_translations_dp = skl_ddi_translations_dp;
-                ddi_translations_edp = skl_ddi_translations_dp;
+                n_dp_entries = ARRAY_SIZE(skl_ddi_translations_dp);
+                if (dev_priv->vbt.edp_low_vswing) {
+                        ddi_translations_edp = skl_ddi_translations_edp;
+                        n_edp_entries = ARRAY_SIZE(skl_ddi_translations_edp);
+                } else {
+                        ddi_translations_edp = skl_ddi_translations_dp;
+                        n_edp_entries = ARRAY_SIZE(skl_ddi_translations_dp);
+                }
+
                 ddi_translations_hdmi = skl_ddi_translations_hdmi;
                 n_hdmi_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
                 hdmi_800mV_0dB = 7;
@@ -207,6 +231,8 @@ static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port)
                 ddi_translations_dp = bdw_ddi_translations_dp;
                 ddi_translations_edp = bdw_ddi_translations_edp;
                 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
+                n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
+                n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
                 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
                 hdmi_800mV_0dB = 7;
         } else if (IS_HASWELL(dev)) {
@@ -214,6 +240,7 @@ static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port)
                 ddi_translations_dp = hsw_ddi_translations_dp;
                 ddi_translations_edp = hsw_ddi_translations_dp;
                 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
+                n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
                 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
                 hdmi_800mV_0dB = 6;
         } else {
@@ -222,6 +249,8 @@ static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port)
                 ddi_translations_fdi = bdw_ddi_translations_fdi;
                 ddi_translations_dp = bdw_ddi_translations_dp;
                 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
+                n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
+                n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
                 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
                 hdmi_800mV_0dB = 7;
         }
@@ -229,29 +258,34 @@ static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port)
         switch (port) {
         case PORT_A:
                 ddi_translations = ddi_translations_edp;
+                size = n_edp_entries;
                 break;
         case PORT_B:
         case PORT_C:
                 ddi_translations = ddi_translations_dp;
+                size = n_dp_entries;
                 break;
         case PORT_D:
-                if (intel_dp_is_edp(dev, PORT_D))
+                if (intel_dp_is_edp(dev, PORT_D)) {
                         ddi_translations = ddi_translations_edp;
-                else
+                        size = n_edp_entries;
+                } else {
                         ddi_translations = ddi_translations_dp;
+                        size = n_dp_entries;
+                }
                 break;
         case PORT_E:
                 if (ddi_translations_fdi)
                         ddi_translations = ddi_translations_fdi;
                 else
                         ddi_translations = ddi_translations_dp;
+                size = n_dp_entries;
                 break;
         default:
                 BUG();
         }
 
-        for (i = 0, reg = DDI_BUF_TRANS(port);
-             i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
+        for (i = 0, reg = DDI_BUF_TRANS(port); i < size; i++) {
                 I915_WRITE(reg, ddi_translations[i].trans1);
                 reg += 4;
                 I915_WRITE(reg, ddi_translations[i].trans2);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index e730789b53b7..31f3b11589b9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -390,7 +390,7 @@ static const intel_limit_t intel_limits_chv = {
          * them would make no difference.
          */
         .dot = { .min = 25000 * 5, .max = 540000 * 5},
-        .vco = { .min = 4860000, .max = 6700000 },
+        .vco = { .min = 4860000, .max = 6480000 },
         .n = { .min = 1, .max = 1 },
         .m1 = { .min = 2, .max = 2 },
         .m2 = { .min = 24 << 22, .max = 175 << 22 },
@@ -2190,11 +2190,50 @@ static bool need_vtd_wa(struct drm_device *dev)
 }
 
 int
-intel_fb_align_height(struct drm_device *dev, int height, unsigned int tiling)
+intel_fb_align_height(struct drm_device *dev, int height,
+                      uint32_t pixel_format,
+                      uint64_t fb_format_modifier)
 {
         int tile_height;
+        uint32_t bits_per_pixel;
+
+        switch (fb_format_modifier) {
+        case DRM_FORMAT_MOD_NONE:
+                tile_height = 1;
+                break;
+        case I915_FORMAT_MOD_X_TILED:
+                tile_height = IS_GEN2(dev) ? 16 : 8;
+                break;
+        case I915_FORMAT_MOD_Y_TILED:
+                tile_height = 32;
+                break;
+        case I915_FORMAT_MOD_Yf_TILED:
+                bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
+                switch (bits_per_pixel) {
+                default:
+                case 8:
+                        tile_height = 64;
+                        break;
+                case 16:
+                case 32:
+                        tile_height = 32;
+                        break;
+                case 64:
+                        tile_height = 16;
+                        break;
+                case 128:
+                        WARN_ONCE(1,
+                                  "128-bit pixels are not supported for display!");
+                        tile_height = 16;
+                        break;
+                }
+                break;
+        default:
+                MISSING_CASE(fb_format_modifier);
+                tile_height = 1;
+                break;
+        }
 
-        tile_height = tiling ? (IS_GEN2(dev) ? 16 : 8) : 1;
         return ALIGN(height, tile_height);
 }
 
@@ -2211,8 +2250,8 @@ intel_pin_and_fence_fb_obj(struct drm_plane *plane,
 
         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
 
-        switch (obj->tiling_mode) {
-        case I915_TILING_NONE:
+        switch (fb->modifier[0]) {
+        case DRM_FORMAT_MOD_NONE:
                 if (INTEL_INFO(dev)->gen >= 9)
                         alignment = 256 * 1024;
                 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
@@ -2222,7 +2261,7 @@ intel_pin_and_fence_fb_obj(struct drm_plane *plane,
                 else
                         alignment = 64 * 1024;
                 break;
-        case I915_TILING_X:
+        case I915_FORMAT_MOD_X_TILED:
                 if (INTEL_INFO(dev)->gen >= 9)
                         alignment = 256 * 1024;
                 else {
@@ -2230,11 +2269,16 @@ intel_pin_and_fence_fb_obj(struct drm_plane *plane,
                         alignment = 0;
                 }
                 break;
-        case I915_TILING_Y:
-                WARN(1, "Y tiled bo slipped through, driver bug!\n");
-                return -EINVAL;
+        case I915_FORMAT_MOD_Y_TILED:
+        case I915_FORMAT_MOD_Yf_TILED:
+                if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
+                          "Y tiling bo slipped through, driver bug!\n"))
+                        return -EINVAL;
+                alignment = 1 * 1024 * 1024;
+                break;
         default:
-                BUG();
+                MISSING_CASE(fb->modifier[0]);
+                return -EINVAL;
         }
 
         /* Note that the w/a also requires 64 PTE of padding following the
@@ -2282,7 +2326,7 @@ err_interruptible:
         return ret;
 }
 
-void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
+static void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
 {
         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
 
@@ -2371,6 +2415,7 @@ intel_alloc_plane_obj(struct intel_crtc *crtc,
         struct drm_device *dev = crtc->base.dev;
         struct drm_i915_gem_object *obj = NULL;
         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
+        struct drm_framebuffer *fb = &plane_config->fb->base;
         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
         u32 size_aligned = round_up(plane_config->base + plane_config->size,
                                     PAGE_SIZE);
@@ -2389,16 +2434,18 @@ intel_alloc_plane_obj(struct intel_crtc *crtc,
 
         obj->tiling_mode = plane_config->tiling;
         if (obj->tiling_mode == I915_TILING_X)
-                obj->stride = crtc->base.primary->fb->pitches[0];
+                obj->stride = fb->pitches[0];
 
-        mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
-        mode_cmd.width = crtc->base.primary->fb->width;
-        mode_cmd.height = crtc->base.primary->fb->height;
-        mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
+        mode_cmd.pixel_format = fb->pixel_format;
+        mode_cmd.width = fb->width;
+        mode_cmd.height = fb->height;
+        mode_cmd.pitches[0] = fb->pitches[0];
+        mode_cmd.modifier[0] = fb->modifier[0];
+        mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
 
         mutex_lock(&dev->struct_mutex);
 
-        if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
+        if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
                                    &mode_cmd, obj)) {
                 DRM_DEBUG_KMS("intel fb init failed\n");
                 goto out_unref_obj;
@@ -2416,6 +2463,20 @@ out_unref_obj:
         return false;
 }
 
+/* Update plane->state->fb to match plane->fb after driver-internal updates */
+static void
+update_state_fb(struct drm_plane *plane)
+{
+        if (plane->fb == plane->state->fb)
+                return;
+
+        if (plane->state->fb)
+                drm_framebuffer_unreference(plane->state->fb);
+        plane->state->fb = plane->fb;
+        if (plane->state->fb)
+                drm_framebuffer_reference(plane->state->fb);
+}
+
 static void
 intel_find_plane_obj(struct intel_crtc *intel_crtc,
                      struct intel_initial_plane_config *plane_config)
@@ -2426,14 +2487,20 @@ intel_find_plane_obj(struct intel_crtc *intel_crtc,
         struct intel_crtc *i;
         struct drm_i915_gem_object *obj;
 
-        if (!intel_crtc->base.primary->fb)
+        if (!plane_config->fb)
                 return;
 
-        if (intel_alloc_plane_obj(intel_crtc, plane_config))
+        if (intel_alloc_plane_obj(intel_crtc, plane_config)) {
+                struct drm_plane *primary = intel_crtc->base.primary;
+
+                primary->fb = &plane_config->fb->base;
+                primary->state->crtc = &intel_crtc->base;
+                update_state_fb(primary);
+
                 return;
+        }
 
-        kfree(intel_crtc->base.primary->fb);
-        intel_crtc->base.primary->fb = NULL;
+        kfree(plane_config->fb);
 
         /*
          * Failed to alloc the obj, check to see if we should share
@@ -2453,15 +2520,20 @@ intel_find_plane_obj(struct intel_crtc *intel_crtc,
                         continue;
 
                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
+                        struct drm_plane *primary = intel_crtc->base.primary;
+
                         if (obj->tiling_mode != I915_TILING_NONE)
                                 dev_priv->preserve_bios_swizzle = true;
 
                         drm_framebuffer_reference(c->primary->fb);
-                        intel_crtc->base.primary->fb = c->primary->fb;
+                        primary->fb = c->primary->fb;
+                        primary->state->crtc = &intel_crtc->base;
+                        update_state_fb(intel_crtc->base.primary);
                         obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
                         break;
                 }
         }
+
 }
 
 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
@@ -2701,6 +2773,40 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
         POSTING_READ(reg);
 }
 
+u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
+                              uint32_t pixel_format)
+{
+        u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
+
+        /*
+         * The stride is either expressed as a multiple of 64 bytes
+         * chunks for linear buffers or in number of tiles for tiled
+         * buffers.
+         */
+        switch (fb_modifier) {
+        case DRM_FORMAT_MOD_NONE:
+                return 64;
+        case I915_FORMAT_MOD_X_TILED:
+                if (INTEL_INFO(dev)->gen == 2)
+                        return 128;
+                return 512;
+        case I915_FORMAT_MOD_Y_TILED:
+                /* No need to check for old gens and Y tiling since this is
+                 * about the display engine and those will be blocked before
+                 * we get here.
+                 */
+                return 128;
+        case I915_FORMAT_MOD_Yf_TILED:
+                if (bits_per_pixel == 8)
+                        return 64;
+                else
+                        return 128;
+        default:
+                MISSING_CASE(fb_modifier);
+                return 64;
+        }
+}
+
 static void skylake_update_primary_plane(struct drm_crtc *crtc,
                                          struct drm_framebuffer *fb,
                                          int x, int y)
@@ -2708,10 +2814,9 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
         struct drm_device *dev = crtc->dev;
         struct drm_i915_private *dev_priv = dev->dev_private;
         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-        struct intel_framebuffer *intel_fb;
         struct drm_i915_gem_object *obj;
         int pipe = intel_crtc->pipe;
-        u32 plane_ctl, stride;
+        u32 plane_ctl, stride_div;
 
         if (!intel_crtc->primary_enabled) {
                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
@@ -2755,29 +2860,30 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
                 BUG();
         }
 
-        intel_fb = to_intel_framebuffer(fb);
-        obj = intel_fb->obj;
-
-        /*
-         * The stride is either expressed as a multiple of 64 bytes chunks for
-         * linear buffers or in number of tiles for tiled buffers.
-         */
-        switch (obj->tiling_mode) {
-        case I915_TILING_NONE:
-                stride = fb->pitches[0] >> 6;
+        switch (fb->modifier[0]) {
+        case DRM_FORMAT_MOD_NONE:
                 break;
-        case I915_TILING_X:
+        case I915_FORMAT_MOD_X_TILED:
                 plane_ctl |= PLANE_CTL_TILED_X;
-                stride = fb->pitches[0] >> 9;
+                break;
+        case I915_FORMAT_MOD_Y_TILED:
+                plane_ctl |= PLANE_CTL_TILED_Y;
+                break;
+        case I915_FORMAT_MOD_Yf_TILED:
+                plane_ctl |= PLANE_CTL_TILED_YF;
                 break;
         default:
-                BUG();
+                MISSING_CASE(fb->modifier[0]);
         }
 
         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180))
                 plane_ctl |= PLANE_CTL_ROTATE_180;
 
+        obj = intel_fb_obj(fb);
+        stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
+                                               fb->pixel_format);
+
         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
 
         DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
@@ -2790,7 +2896,7 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
         I915_WRITE(PLANE_SIZE(pipe, 0),
                    (intel_crtc->config->pipe_src_h - 1) << 16 |
                    (intel_crtc->config->pipe_src_w - 1));
-        I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
+        I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div);
         I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
 
         POSTING_READ(PLANE_SURF(pipe, 0));
@@ -3044,7 +3150,7 @@ static void intel_fdi_normal_train(struct drm_crtc *crtc)
 
 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
 {
-        return crtc->base.enabled && crtc->active &&
+        return crtc->base.state->enable && crtc->active &&
                 crtc->config->has_pch_encoder;
 }
 
@@ -4182,7 +4288,7 @@ static void intel_crtc_load_lut(struct drm_crtc *crtc)
         bool reenable_ips = false;
 
         /* The clocks have to be on to load the palette. */
-        if (!crtc->enabled || !intel_crtc->active)
+        if (!crtc->state->enable || !intel_crtc->active)
                 return;
 
         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
@@ -4266,11 +4372,10 @@ static void intel_crtc_disable_planes(struct drm_crtc *crtc)
         struct drm_i915_private *dev_priv = dev->dev_private;
         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
         int pipe = intel_crtc->pipe;
-        int plane = intel_crtc->plane;
 
         intel_crtc_wait_for_pending_flips(crtc);
 
-        if (dev_priv->fbc.plane == plane)
+        if (dev_priv->fbc.crtc == intel_crtc)
                 intel_fbc_disable(dev);
 
         hsw_disable_ips(intel_crtc);
@@ -4296,7 +4401,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
         struct intel_encoder *encoder;
         int pipe = intel_crtc->pipe;
 
-        WARN_ON(!crtc->enabled);
+        WARN_ON(!crtc->state->enable);
 
         if (intel_crtc->active)
                 return;
@@ -4305,7 +4410,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
                 intel_prepare_shared_dpll(intel_crtc);
 
         if (intel_crtc->config->has_dp_encoder)
-                intel_dp_set_m_n(intel_crtc);
+                intel_dp_set_m_n(intel_crtc, M1_N1);
 
         intel_set_pipe_timings(intel_crtc);
 
@@ -4404,7 +4509,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
         struct intel_encoder *encoder;
         int pipe = intel_crtc->pipe;
 
-        WARN_ON(!crtc->enabled);
+        WARN_ON(!crtc->state->enable);
 
         if (intel_crtc->active)
                 return;
@@ -4413,7 +4518,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
                 intel_enable_shared_dpll(intel_crtc);
 
         if (intel_crtc->config->has_dp_encoder)
-                intel_dp_set_m_n(intel_crtc);
+                intel_dp_set_m_n(intel_crtc, M1_N1);
 
         intel_set_pipe_timings(intel_crtc);
 
@@ -4751,7 +4856,7 @@ static void modeset_update_crtc_power_domains(struct drm_device *dev)
         for_each_intel_crtc(dev, crtc) {
                 enum intel_display_power_domain domain;
 
-                if (!crtc->base.enabled)
+                if (!crtc->base.state->enable)
                         continue;
 
                 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
@@ -4972,7 +5077,7 @@ static void valleyview_modeset_global_pipes(struct drm_device *dev,
 
         /* disable/enable all currently active pipes while we change cdclk */
         for_each_intel_crtc(dev, intel_crtc)
-                if (intel_crtc->base.enabled)
+                if (intel_crtc->base.state->enable)
                         *prepare_pipes |= (1 << intel_crtc->pipe);
 }
 
@@ -5012,7 +5117,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
         int pipe = intel_crtc->pipe;
         bool is_dsi;
 
-        WARN_ON(!crtc->enabled);
+        WARN_ON(!crtc->state->enable);
 
         if (intel_crtc->active)
                 return;
@@ -5027,7 +5132,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
         }
 
         if (intel_crtc->config->has_dp_encoder)
-                intel_dp_set_m_n(intel_crtc);
+                intel_dp_set_m_n(intel_crtc, M1_N1);
 
         intel_set_pipe_timings(intel_crtc);
 
@@ -5095,7 +5200,7 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
         struct intel_encoder *encoder;
         int pipe = intel_crtc->pipe;
 
-        WARN_ON(!crtc->enabled);
+        WARN_ON(!crtc->state->enable);
 
         if (intel_crtc->active)
                 return;
@@ -5103,7 +5208,7 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
         i9xx_set_pll_dividers(intel_crtc);
 
         if (intel_crtc->config->has_dp_encoder)
-                intel_dp_set_m_n(intel_crtc);
+                intel_dp_set_m_n(intel_crtc, M1_N1);
 
         intel_set_pipe_timings(intel_crtc);
 
@@ -5294,7 +5399,7 @@ static void intel_crtc_disable(struct drm_crtc *crtc)
         struct drm_i915_private *dev_priv = dev->dev_private;
 
         /* crtc should still be enabled when we disable it. */
-        WARN_ON(!crtc->enabled);
+        WARN_ON(!crtc->state->enable);
 
         dev_priv->display.crtc_disable(crtc);
         dev_priv->display.off(crtc);
@@ -5372,7 +5477,8 @@ static void intel_connector_check_state(struct intel_connector *connector)
 
                         crtc = encoder->base.crtc;
 
-                        I915_STATE_WARN(!crtc->enabled, "crtc not enabled\n");
+                        I915_STATE_WARN(!crtc->state->enable,
+                                        "crtc not enabled\n");
                         I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
                         I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
                              "encoder active on the wrong pipe\n");
@@ -5559,7 +5665,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
          * - LVDS dual channel mode
          * - Double wide pipe
          */
-        if ((intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
+        if ((intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
                 pipe_config->pipe_src_w &= ~1;
 
@@ -5862,7 +5968,7 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
                  * for gen < 8) and if DRRS is supported (to make sure the
                  * registers are not unnecessarily accessed).
                  */
-                if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
+                if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
                         crtc->config->has_drrs) {
                         I915_WRITE(PIPE_DATA_M2(transcoder),
                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
@@ -5878,13 +5984,29 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
         }
 }
 
-void intel_dp_set_m_n(struct intel_crtc *crtc)
+void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
 {
+        struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
+
+        if (m_n == M1_N1) {
+                dp_m_n = &crtc->config->dp_m_n;
+                dp_m2_n2 = &crtc->config->dp_m2_n2;
+        } else if (m_n == M2_N2) {
+
+                /*
+                 * M2_N2 registers are not supported. Hence m2_n2 divider value
+                 * needs to be programmed into M1_N1.
+                 */
+                dp_m_n = &crtc->config->dp_m2_n2;
+        } else {
+                DRM_ERROR("Unsupported divider value\n");
+                return;
+        }
+
         if (crtc->config->has_pch_encoder)
                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
         else
-                intel_cpu_transcoder_set_m_n(crtc, &crtc->config->dp_m_n,
-                                                   &crtc->config->dp_m2_n2);
+                intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
 }
 
 static void vlv_update_pll(struct intel_crtc *crtc,
@@ -6602,6 +6724,10 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
         struct drm_framebuffer *fb;
         struct intel_framebuffer *intel_fb;
 
+        val = I915_READ(DSPCNTR(plane));
+        if (!(val & DISPLAY_PLANE_ENABLE))
+                return;
+
         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
         if (!intel_fb) {
                 DRM_DEBUG_KMS("failed to alloc fb\n");
@@ -6610,11 +6736,12 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
 
         fb = &intel_fb->base;
 
-        val = I915_READ(DSPCNTR(plane));
-
-        if (INTEL_INFO(dev)->gen >= 4)
-                if (val & DISPPLANE_TILED)
+        if (INTEL_INFO(dev)->gen >= 4) {
+                if (val & DISPPLANE_TILED) {
                         plane_config->tiling = I915_TILING_X;
+                        fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
+                }
+        }
 
         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
         fourcc = i9xx_format_to_fourcc(pixel_format);
@@ -6640,7 +6767,8 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
         fb->pitches[0] = val & 0xffffffc0;
 
         aligned_height = intel_fb_align_height(dev, fb->height,
-                                               plane_config->tiling);
+                                               fb->pixel_format,
+                                               fb->modifier[0]);
 
         plane_config->size = fb->pitches[0] * aligned_height;
 
@@ -6649,7 +6777,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
                       fb->bits_per_pixel, base, fb->pitches[0],
                       plane_config->size);
 
-        crtc->base.primary->fb = fb;
+        plane_config->fb = intel_fb;
 }
 
 static void chv_crtc_clock_get(struct intel_crtc *crtc,
@@ -7627,7 +7755,7 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
 {
         struct drm_device *dev = crtc->base.dev;
         struct drm_i915_private *dev_priv = dev->dev_private;
-        u32 val, base, offset, stride_mult;
+        u32 val, base, offset, stride_mult, tiling;
         int pipe = crtc->pipe;
         int fourcc, pixel_format;
         int aligned_height;
@@ -7643,8 +7771,8 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
         fb = &intel_fb->base;
 
         val = I915_READ(PLANE_CTL(pipe, 0));
-        if (val & PLANE_CTL_TILED_MASK)
-                plane_config->tiling = I915_TILING_X;
+        if (!(val & PLANE_CTL_ENABLE))
+                goto error;
 
         pixel_format = val & PLANE_CTL_FORMAT_MASK;
         fourcc = skl_format_to_fourcc(pixel_format,
@@ -7653,6 +7781,26 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
         fb->pixel_format = fourcc;
         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
 
+        tiling = val & PLANE_CTL_TILED_MASK;
+        switch (tiling) {
+        case PLANE_CTL_TILED_LINEAR:
+                fb->modifier[0] = DRM_FORMAT_MOD_NONE;
+                break;
+        case PLANE_CTL_TILED_X:
+                plane_config->tiling = I915_TILING_X;
+                fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
+                break;
+        case PLANE_CTL_TILED_Y:
+                fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
+                break;
+        case PLANE_CTL_TILED_YF:
+                fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
+                break;
+        default:
+                MISSING_CASE(tiling);
+                goto error;
+        }
+
         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
         plane_config->base = base;
 
@@ -7663,21 +7811,13 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
         fb->width = ((val >> 0) & 0x1fff) + 1;
 
         val = I915_READ(PLANE_STRIDE(pipe, 0));
-        switch (plane_config->tiling) {
-        case I915_TILING_NONE:
-                stride_mult = 64;
-                break;
-        case I915_TILING_X:
-                stride_mult = 512;
-                break;
-        default:
-                MISSING_CASE(plane_config->tiling);
-                goto error;
-        }
+        stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
+                                                fb->pixel_format);
         fb->pitches[0] = (val & 0x3ff) * stride_mult;
 
         aligned_height = intel_fb_align_height(dev, fb->height,
-                                               plane_config->tiling);
+                                               fb->pixel_format,
+                                               fb->modifier[0]);
 
         plane_config->size = fb->pitches[0] * aligned_height;
 
@@ -7686,7 +7826,7 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
                       fb->bits_per_pixel, base, fb->pitches[0],
                       plane_config->size);
 
-        crtc->base.primary->fb = fb;
+        plane_config->fb = intel_fb;
         return;
 
 error:
@@ -7730,6 +7870,10 @@ ironlake_get_initial_plane_config(struct intel_crtc *crtc,
         struct drm_framebuffer *fb;
         struct intel_framebuffer *intel_fb;
 
+        val = I915_READ(DSPCNTR(pipe));
+        if (!(val & DISPLAY_PLANE_ENABLE))
+                return;
+
         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
         if (!intel_fb) {
                 DRM_DEBUG_KMS("failed to alloc fb\n");
@@ -7738,11 +7882,12 @@ ironlake_get_initial_plane_config(struct intel_crtc *crtc,
 
         fb = &intel_fb->base;
 
-        val = I915_READ(DSPCNTR(pipe));
-
-        if (INTEL_INFO(dev)->gen >= 4)
-                if (val & DISPPLANE_TILED)
+        if (INTEL_INFO(dev)->gen >= 4) {
+                if (val & DISPPLANE_TILED) {
                         plane_config->tiling = I915_TILING_X;
+                        fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
+                }
+        }
 
         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
         fourcc = i9xx_format_to_fourcc(pixel_format);
@@ -7768,7 +7913,8 @@ ironlake_get_initial_plane_config(struct intel_crtc *crtc,
         fb->pitches[0] = val & 0xffffffc0;
 
         aligned_height = intel_fb_align_height(dev, fb->height,
-                                               plane_config->tiling);
+                                               fb->pixel_format,
+                                               fb->modifier[0]);
 
         plane_config->size = fb->pitches[0] * aligned_height;
 
@@ -7777,7 +7923,7 @@ ironlake_get_initial_plane_config(struct intel_crtc *crtc,
                       fb->bits_per_pixel, base, fb->pitches[0],
                       plane_config->size);
 
-        crtc->base.primary->fb = fb;
+        plane_config->fb = intel_fb;
 }
 
 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
@@ -8651,7 +8797,7 @@ retry:
                 i++;
                 if (!(encoder->possible_crtcs & (1 << i)))
                         continue;
-                if (possible_crtc->enabled)
+                if (possible_crtc->state->enable)
                         continue;
                 /* This can occur when applying the pipe A quirk on resume. */
                 if (to_intel_crtc(possible_crtc)->new_enabled)
@@ -8720,7 +8866,7 @@ retry:
         return true;
 
  fail:
-        intel_crtc->new_enabled = crtc->enabled;
+        intel_crtc->new_enabled = crtc->state->enable;
         if (intel_crtc->new_enabled)
                 intel_crtc->new_config = intel_crtc->config;
         else
@@ -9071,9 +9217,9 @@ static void intel_unpin_work_fn(struct work_struct *__work)
         enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
 
         mutex_lock(&dev->struct_mutex);
-        intel_unpin_fb_obj(work->old_fb_obj);
+        intel_unpin_fb_obj(intel_fb_obj(work->old_fb));
         drm_gem_object_unreference(&work->pending_flip_obj->base);
-        drm_gem_object_unreference(&work->old_fb_obj->base);
+        drm_framebuffer_unreference(work->old_fb);
 
         intel_fbc_update(dev);
 
@@ -9598,69 +9744,6 @@ static int intel_queue_mmio_flip(struct drm_device *dev,
         return 0;
 }
 
-static int intel_gen9_queue_flip(struct drm_device *dev,
-                                 struct drm_crtc *crtc,
-                                 struct drm_framebuffer *fb,
-                                 struct drm_i915_gem_object *obj,
-                                 struct intel_engine_cs *ring,
-                                 uint32_t flags)
-{
-        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-        uint32_t plane = 0, stride;
-        int ret;
-
-        switch(intel_crtc->pipe) {
-        case PIPE_A:
-                plane = MI_DISPLAY_FLIP_SKL_PLANE_1_A;
-                break;
-        case PIPE_B:
-                plane = MI_DISPLAY_FLIP_SKL_PLANE_1_B;
-                break;
-        case PIPE_C:
-                plane = MI_DISPLAY_FLIP_SKL_PLANE_1_C;
-                break;
-        default:
-                WARN_ONCE(1, "unknown plane in flip command\n");
-                return -ENODEV;
-        }
-
-        switch (obj->tiling_mode) {
-        case I915_TILING_NONE:
-                stride = fb->pitches[0] >> 6;
-                break;
-        case I915_TILING_X:
-                stride = fb->pitches[0] >> 9;
-                break;
-        default:
-                WARN_ONCE(1, "unknown tiling in flip command\n");
-                return -ENODEV;
-        }
-
-        ret = intel_ring_begin(ring, 10);
-        if (ret)
-                return ret;
-
-        intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
-        intel_ring_emit(ring, DERRMR);
-        intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
-                                DERRMR_PIPEB_PRI_FLIP_DONE |
-                                DERRMR_PIPEC_PRI_FLIP_DONE));
-        intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
-                              MI_SRM_LRM_GLOBAL_GTT);
-        intel_ring_emit(ring, DERRMR);
-        intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
-        intel_ring_emit(ring, 0);
-
-        intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane);
-        intel_ring_emit(ring, stride << 6 | obj->tiling_mode);
-        intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
-
-        intel_mark_page_flip_active(intel_crtc);
-        __intel_ring_advance(ring);
-
-        return 0;
-}
-
 static int intel_default_queue_flip(struct drm_device *dev,
                                     struct drm_crtc *crtc,
                                     struct drm_framebuffer *fb,
@@ -9690,10 +9773,10 @@ static bool __intel_pageflip_stall_check(struct drm_device *dev,
                     !i915_gem_request_completed(work->flip_queued_req, true))
                         return false;
 
-                work->flip_ready_vblank = drm_vblank_count(dev, intel_crtc->pipe);
+                work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
         }
 
-        if (drm_vblank_count(dev, intel_crtc->pipe) - work->flip_ready_vblank < 3)
+        if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
                 return false;
 
         /* Potential stall - if we see that the flip has happened,
@@ -9724,7 +9807,8 @@ void intel_check_page_flip(struct drm_device *dev, int pipe)
         spin_lock(&dev->event_lock);
         if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
-                         intel_crtc->unpin_work->flip_queued_vblank, drm_vblank_count(dev, pipe));
+                         intel_crtc->unpin_work->flip_queued_vblank,
+                         drm_vblank_count(dev, pipe));
                 page_flip_completed(intel_crtc);
         }
         spin_unlock(&dev->event_lock);
@@ -9776,7 +9860,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
 
         work->event = event;
         work->crtc = crtc;
-        work->old_fb_obj = intel_fb_obj(old_fb);
+        work->old_fb = old_fb;
         INIT_WORK(&work->work, intel_unpin_work_fn);
 
         ret = drm_crtc_vblank_get(crtc);
@@ -9812,10 +9896,11 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
                 goto cleanup;
 
         /* Reference the objects for the scheduled work. */
-        drm_gem_object_reference(&work->old_fb_obj->base);
+        drm_framebuffer_reference(work->old_fb);
         drm_gem_object_reference(&obj->base);
 
         crtc->primary->fb = fb;
+        update_state_fb(crtc->primary);
 
         work->pending_flip_obj = obj;
 
@@ -9827,7 +9912,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
 
         if (IS_VALLEYVIEW(dev)) {
                 ring = &dev_priv->ring[BCS];
-                if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
+                if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
                         /* vlv: DISPLAY_FLIP fails to change tiling */
                         ring = NULL;
         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
@@ -9865,10 +9950,10 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
                                         intel_ring_get_request(ring));
         }
 
-        work->flip_queued_vblank = drm_vblank_count(dev, intel_crtc->pipe);
+        work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
         work->enable_stall_check = true;
 
-        i915_gem_track_fb(work->old_fb_obj, obj,
+        i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
                           INTEL_FRONTBUFFER_PRIMARY(pipe));
 
         intel_fbc_disable(dev);
@@ -9884,7 +9969,8 @@ cleanup_unpin:
 cleanup_pending:
         atomic_dec(&intel_crtc->unpin_work_count);
         crtc->primary->fb = old_fb;
-        drm_gem_object_unreference(&work->old_fb_obj->base);
+        update_state_fb(crtc->primary);
+        drm_framebuffer_unreference(work->old_fb);
         drm_gem_object_unreference(&obj->base);
         mutex_unlock(&dev->struct_mutex);
 
@@ -9940,7 +10026,7 @@ static void intel_modeset_update_staged_output_state(struct drm_device *dev)
         }
 
         for_each_intel_crtc(dev, crtc) {
-                crtc->new_enabled = crtc->base.enabled;
+                crtc->new_enabled = crtc->base.state->enable;
 
                 if (crtc->new_enabled)
                         crtc->new_config = crtc->config;
@@ -9970,6 +10056,7 @@ static void intel_modeset_commit_output_state(struct drm_device *dev)
         }
 
         for_each_intel_crtc(dev, crtc) {
+                crtc->base.state->enable = crtc->new_enabled;
                 crtc->base.enabled = crtc->new_enabled;
         }
 }
@@ -10233,6 +10320,7 @@ intel_modeset_pipe_config(struct drm_crtc *crtc,
         if (!pipe_config)
                 return ERR_PTR(-ENOMEM);
 
+        pipe_config->base.crtc = crtc;
         drm_mode_copy(&pipe_config->base.adjusted_mode, mode);
         drm_mode_copy(&pipe_config->base.mode, mode);
 
@@ -10381,7 +10469,7 @@ intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
 
         /* Check for pipes that will be enabled/disabled ... */
         for_each_intel_crtc(dev, intel_crtc) {
-                if (intel_crtc->base.enabled == intel_crtc->new_enabled)
+                if (intel_crtc->base.state->enable == intel_crtc->new_enabled)
                         continue;
 
                 if (!intel_crtc->new_enabled)
@@ -10456,10 +10544,10 @@ intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
 
         /* Double check state. */
         for_each_intel_crtc(dev, intel_crtc) {
-                WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
+                WARN_ON(intel_crtc->base.state->enable != intel_crtc_in_use(&intel_crtc->base));
                 WARN_ON(intel_crtc->new_config &&
                         intel_crtc->new_config != intel_crtc->config);
-                WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
+                WARN_ON(intel_crtc->base.state->enable != !!intel_crtc->new_config);
         }
 
         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
@@ -10846,7 +10934,7 @@ check_crtc_state(struct drm_device *dev)
                 DRM_DEBUG_KMS("[CRTC:%d]\n",
                               crtc->base.base.id);
 
-                I915_STATE_WARN(crtc->active && !crtc->base.enabled,
+                I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
                      "active crtc, but not enabled in sw tracking\n");
 
                 for_each_intel_encoder(dev, encoder) {
@@ -10860,9 +10948,10 @@ check_crtc_state(struct drm_device *dev)
                 I915_STATE_WARN(active != crtc->active,
                      "crtc's computed active state doesn't match tracked active state "
                      "(expected %i, found %i)\n", active, crtc->active);
-                I915_STATE_WARN(enabled != crtc->base.enabled,
+                I915_STATE_WARN(enabled != crtc->base.state->enable,
                      "crtc's computed enabled state doesn't match tracked enabled state "
-                     "(expected %i, found %i)\n", enabled, crtc->base.enabled);
+                     "(expected %i, found %i)\n", enabled,
+                                crtc->base.state->enable);
 
                 active = dev_priv->display.get_pipe_config(crtc,
                                                            &pipe_config);
@@ -10926,7 +11015,7 @@ check_shared_dpll_state(struct drm_device *dev)
                      pll->on, active);
 
                 for_each_intel_crtc(dev, crtc) {
-                        if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
+                        if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
                                 enabled_crtcs++;
                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
                                 active_crtcs++;
@@ -11112,7 +11201,7 @@ static int __intel_set_mode(struct drm_crtc *crtc,
                 intel_crtc_disable(&intel_crtc->base);
 
         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
-                if (intel_crtc->base.enabled)
+                if (intel_crtc->base.state->enable)
                         dev_priv->display.crtc_disable(&intel_crtc->base);
         }
 
@@ -11168,7 +11257,7 @@ static int __intel_set_mode(struct drm_crtc *crtc,
 
         /* FIXME: add subpixel order */
 done:
-        if (ret && crtc->enabled)
+        if (ret && crtc->state->enable)
                 crtc->mode = *saved_mode;
 
         kfree(saved_mode);
@@ -11264,7 +11353,7 @@ static int intel_set_config_save_state(struct drm_device *dev,
          */
         count = 0;
         for_each_crtc(dev, crtc) {
-                config->save_crtc_enabled[count++] = crtc->enabled;
+                config->save_crtc_enabled[count++] = crtc->state->enable;
         }
 
         count = 0;
@@ -11498,7 +11587,7 @@ intel_modeset_stage_output_state(struct drm_device *dev,
                         }
                 }
 
-                if (crtc->new_enabled != crtc->base.enabled) {
+                if (crtc->new_enabled != crtc->base.state->enable) {
                         DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
                                       crtc->new_enabled ? "en" : "dis");
                         config->mode_changed = true;
@@ -11803,7 +11892,8 @@ static void intel_shared_dpll_init(struct drm_device *dev)
  */
 int
 intel_prepare_plane_fb(struct drm_plane *plane,
-                       struct drm_framebuffer *fb)
+                       struct drm_framebuffer *fb,
+                       const struct drm_plane_state *new_state)
 {
         struct drm_device *dev = plane->dev;
         struct intel_plane *intel_plane = to_intel_plane(plane);
@@ -11857,7 +11947,8 @@ intel_prepare_plane_fb(struct drm_plane *plane,
  */
 void
 intel_cleanup_plane_fb(struct drm_plane *plane,
-                       struct drm_framebuffer *fb)
+                       struct drm_framebuffer *fb,
+                       const struct drm_plane_state *old_state)
 {
         struct drm_device *dev = plane->dev;
         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
@@ -11913,7 +12004,7 @@ intel_check_primary_plane(struct drm_plane *plane,
                  */
                 if (intel_crtc->primary_enabled &&
                     INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
-                    dev_priv->fbc.plane == intel_crtc->plane &&
+                    dev_priv->fbc.crtc == intel_crtc &&
                     state->base.rotation != BIT(DRM_ROTATE_0)) {
                         intel_crtc->atomic.disable_fbc = true;
                 }
@@ -11932,6 +12023,12 @@ intel_check_primary_plane(struct drm_plane *plane,
                         INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
 
                 intel_crtc->atomic.update_fbc = true;
+
+                /* Update watermarks on tiling changes. */
+                if (!plane->state->fb || !state->base.fb ||
+                    plane->state->fb->modifier[0] !=
+                    state->base.fb->modifier[0])
+                        intel_crtc->atomic.update_wm = true;
         }
 
         return 0;
@@ -12085,8 +12182,8 @@ void intel_plane_destroy(struct drm_plane *plane)
 }
 
 const struct drm_plane_funcs intel_plane_funcs = {
-        .update_plane = drm_plane_helper_update,
-        .disable_plane = drm_plane_helper_disable,
+        .update_plane = drm_atomic_helper_update_plane,
+        .disable_plane = drm_atomic_helper_disable_plane,
         .destroy = intel_plane_destroy,
         .set_property = drm_atomic_helper_plane_set_property,
         .atomic_get_property = intel_plane_atomic_get_property,
@@ -12204,7 +12301,6 @@ intel_check_cursor_plane(struct drm_plane *plane,
                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
                 ret = -EINVAL;
         }
-        mutex_unlock(&dev->struct_mutex);
 
 finish:
         if (intel_crtc->active) {
@@ -12322,6 +12418,7 @@ static void intel_crtc_init(struct drm_device *dev, int pipe)
         if (!crtc_state)
                 goto fail;
         intel_crtc_set_state(intel_crtc, crtc_state);
+        crtc_state->base.crtc = &intel_crtc->base;
 
         primary = intel_primary_plane_create(dev, pipe);
         if (!primary)
@@ -12399,9 +12496,6 @@ int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
         struct drm_crtc *drmmode_crtc;
         struct intel_crtc *crtc;
 
-        if (!drm_core_check_feature(dev, DRIVER_MODESET))
-                return -ENODEV;
-
         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
 
         if (!drmmode_crtc) {
@@ -12674,52 +12768,100 @@ static const struct drm_framebuffer_funcs intel_fb_funcs = {
         .create_handle = intel_user_framebuffer_create_handle,
 };
 
+static
+u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
+                         uint32_t pixel_format)
+{
+        u32 gen = INTEL_INFO(dev)->gen;
+
+        if (gen >= 9) {
+                /* "The stride in bytes must not exceed the of the size of 8K
+                 *  pixels and 32K bytes."
+                 */
+                 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
+        } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
+                return 32*1024;
+        } else if (gen >= 4) {
+                if (fb_modifier == I915_FORMAT_MOD_X_TILED)
+                        return 16*1024;
+                else
+                        return 32*1024;
+        } else if (gen >= 3) {
+                if (fb_modifier == I915_FORMAT_MOD_X_TILED)
+                        return 8*1024;
+                else
+                        return 16*1024;
+        } else {
+                /* XXX DSPC is limited to 4k tiled */
+                return 8*1024;
+        }
+}
+
 static int intel_framebuffer_init(struct drm_device *dev,
                                   struct intel_framebuffer *intel_fb,
                                   struct drm_mode_fb_cmd2 *mode_cmd,
                                   struct drm_i915_gem_object *obj)
 {
         int aligned_height;
-        int pitch_limit;
         int ret;
+        u32 pitch_limit, stride_alignment;
 
         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
 
-        if (obj->tiling_mode == I915_TILING_Y) {
-                DRM_DEBUG("hardware does not support tiling Y\n");
-                return -EINVAL;
+        if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
+                /* Enforce that fb modifier and tiling mode match, but only for
+                 * X-tiled. This is needed for FBC. */
+                if (!!(obj->tiling_mode == I915_TILING_X) !=
+                    !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
+                        DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
+                        return -EINVAL;
+                }
+        } else {
+                if (obj->tiling_mode == I915_TILING_X)
+                        mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
+                else if (obj->tiling_mode == I915_TILING_Y) {
+                        DRM_DEBUG("No Y tiling for legacy addfb\n");
+                        return -EINVAL;
+                }
         }
 
-        if (mode_cmd->pitches[0] & 63) {
-                DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
-                          mode_cmd->pitches[0]);
+        /* Passed in modifier sanity checking. */
+        switch (mode_cmd->modifier[0]) {
+        case I915_FORMAT_MOD_Y_TILED:
+        case I915_FORMAT_MOD_Yf_TILED:
+                if (INTEL_INFO(dev)->gen < 9) {
+                        DRM_DEBUG("Unsupported tiling 0x%llx!\n",
+                                  mode_cmd->modifier[0]);
+                        return -EINVAL;
+                }
+        case DRM_FORMAT_MOD_NONE:
+        case I915_FORMAT_MOD_X_TILED:
+                break;
+        default:
+                DRM_ERROR("Unsupported fb modifier 0x%llx!\n",
+                                mode_cmd->modifier[0]);
                 return -EINVAL;
         }
 
-        if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
-                pitch_limit = 32*1024;
-        } else if (INTEL_INFO(dev)->gen >= 4) {
-                if (obj->tiling_mode)
-                        pitch_limit = 16*1024;
-                else
-                        pitch_limit = 32*1024;
-        } else if (INTEL_INFO(dev)->gen >= 3) {
-                if (obj->tiling_mode)
-                        pitch_limit = 8*1024;
-                else
-                        pitch_limit = 16*1024;
-        } else
-                /* XXX DSPC is limited to 4k tiled */
-                pitch_limit = 8*1024;
+        stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
+                                                     mode_cmd->pixel_format);
+        if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
+                DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
+                          mode_cmd->pitches[0], stride_alignment);
+                return -EINVAL;
+        }
 
+        pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
+                                           mode_cmd->pixel_format);
         if (mode_cmd->pitches[0] > pitch_limit) {
-                DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
-                          obj->tiling_mode ? "tiled" : "linear",
+                DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
+                          mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
+                          "tiled" : "linear",
                           mode_cmd->pitches[0], pitch_limit);
                 return -EINVAL;
         }
 
-        if (obj->tiling_mode != I915_TILING_NONE &&
+        if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
             mode_cmd->pitches[0] != obj->stride) {
                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
                           mode_cmd->pitches[0], obj->stride);
@@ -12774,7 +12916,8 @@ static int intel_framebuffer_init(struct drm_device *dev,
                 return -EINVAL;
 
         aligned_height = intel_fb_align_height(dev, mode_cmd->height,
-                                               obj->tiling_mode);
+                                               mode_cmd->pixel_format,
+                                               mode_cmd->modifier[0]);
         /* FIXME drm helper for size checks (especially planar formats)? */
         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
                 return -EINVAL;
@@ -12936,9 +13079,6 @@ static void intel_init_display(struct drm_device *dev)
                         valleyview_modeset_global_resources;
         }
 
-        /* Default just returns -ENODEV to indicate unsupported */
-        dev_priv->display.queue_flip = intel_default_queue_flip;
-
         switch (INTEL_INFO(dev)->gen) {
         case 2:
                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
@@ -12961,8 +13101,10 @@ static void intel_init_display(struct drm_device *dev)
                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
                 break;
         case 9:
-                dev_priv->display.queue_flip = intel_gen9_queue_flip;
-                break;
+                /* Drop through - unsupported since execlist only. */
+        default:
+                /* Default just returns -ENODEV to indicate unsupported */
+                dev_priv->display.queue_flip = intel_default_queue_flip;
         }
 
         intel_panel_init_backlight_funcs(dev);
@@ -13181,6 +13323,8 @@ void intel_modeset_init(struct drm_device *dev)
         dev->mode_config.preferred_depth = 24;
         dev->mode_config.prefer_shadow = 1;
 
+        dev->mode_config.allow_fb_modifiers = true;
+
         dev->mode_config.funcs = &intel_mode_funcs;
 
         intel_init_quirks(dev);
@@ -13326,11 +13470,11 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc)
         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
 
         /* restore vblank interrupts to correct state */
+        drm_crtc_vblank_reset(&crtc->base);
         if (crtc->active) {
                 update_scanline_offset(crtc);
-                drm_vblank_on(dev, crtc->pipe);
-        } else
-                drm_vblank_off(dev, crtc->pipe);
+                drm_crtc_vblank_on(&crtc->base);
+        }
 
         /* We need to sanitize the plane -> pipe mapping first because this will
          * disable the crtc (and hence change the state) if it is wrong. Note
@@ -13370,6 +13514,7 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc)
                         }
 
                 WARN_ON(crtc->active);
+                crtc->base.state->enable = false;
                 crtc->base.enabled = false;
         }
 
@@ -13386,7 +13531,7 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc)
          * have active connectors/encoders. */
         intel_crtc_update_dpms(&crtc->base);
 
-        if (crtc->active != crtc->base.enabled) {
+        if (crtc->active != crtc->base.state->enable) {
                 struct intel_encoder *encoder;
 
                 /* This can happen either due to bugs in the get_hw_state
@@ -13394,9 +13539,10 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc)
                  * pipe A quirk. */
                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
                               crtc->base.base.id,
-                              crtc->base.enabled ? "enabled" : "disabled",
+                              crtc->base.state->enable ? "enabled" : "disabled",
                               crtc->active ? "enabled" : "disabled");
 
+                crtc->base.state->enable = crtc->active;
                 crtc->base.enabled = crtc->active;
 
                 /* Because we only establish the connector -> encoder ->
@@ -13533,6 +13679,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
                 crtc->active = dev_priv->display.get_pipe_config(crtc,
                                                                  crtc->config);
 
+                crtc->base.state->enable = crtc->active;
                 crtc->base.enabled = crtc->active;
                 crtc->primary_enabled = primary_get_hw_state(crtc);
 
@@ -13718,6 +13865,7 @@ void intel_modeset_gem_init(struct drm_device *dev)
                                   to_intel_crtc(c)->pipe);
                         drm_framebuffer_unreference(c->primary->fb);
                         c->primary->fb = NULL;
+                        update_state_fb(c->primary);
                 }
         }
         mutex_unlock(&dev->struct_mutex);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index a74aaf9242b9..d1141d37e205 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -240,7 +240,7 @@ uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
         return v;
 }
 
-void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
+static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 {
         int i;
         if (dst_bytes > 4)
@@ -2691,11 +2691,14 @@ static uint8_t
 intel_dp_voltage_max(struct intel_dp *intel_dp)
 {
         struct drm_device *dev = intel_dp_to_dev(intel_dp);
+        struct drm_i915_private *dev_priv = dev->dev_private;
         enum port port = dp_to_dig_port(intel_dp)->port;
 
-        if (INTEL_INFO(dev)->gen >= 9)
+        if (INTEL_INFO(dev)->gen >= 9) {
+                if (dev_priv->vbt.edp_low_vswing && port == PORT_A)
+                        return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
-        else if (IS_VALLEYVIEW(dev))
+        } else if (IS_VALLEYVIEW(dev))
                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
         else if (IS_GEN7(dev) && port == PORT_A)
                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
@@ -2719,6 +2722,8 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
+                case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
+                        return DP_TRAIN_PRE_EMPH_LEVEL_0;
                 default:
                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
                 }
@@ -3201,6 +3206,9 @@ intel_hsw_signal_levels(uint8_t train_set)
                 return DDI_BUF_TRANS_SELECT(7);
         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
                 return DDI_BUF_TRANS_SELECT(8);
+
+        case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
+                return DDI_BUF_TRANS_SELECT(9);
         default:
                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
                               "0x%x\n", signal_levels);
@@ -3803,7 +3811,7 @@ go_again:
  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
  *  4. Check link status on receipt of hot-plug interrupt
  */
-void
+static void
 intel_dp_check_link_status(struct intel_dp *intel_dp)
 {
         struct drm_device *dev = intel_dp_to_dev(intel_dp);
@@ -4736,6 +4744,18 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
                       I915_READ(pp_div_reg));
 }
 
+/**
+ * intel_dp_set_drrs_state - program registers for RR switch to take effect
+ * @dev: DRM device
+ * @refresh_rate: RR to be programmed
+ *
+ * This function gets called when refresh rate (RR) has to be changed from
+ * one frequency to another. Switches can be between high and low RR
+ * supported by the panel or to any other RR based on media playback (in
+ * this case, RR value needs to be passed from user space).
+ *
+ * The caller of this function needs to take a lock on dev_priv->drrs.
+ */
 static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
@@ -4793,14 +4813,32 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
                 return;
         }
 
-        if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
+        if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) {
+                switch (index) {
+                case DRRS_HIGH_RR:
+                        intel_dp_set_m_n(intel_crtc, M1_N1);
+                        break;
+                case DRRS_LOW_RR:
+                        intel_dp_set_m_n(intel_crtc, M2_N2);
+                        break;
+                case DRRS_MAX_RR:
+                default:
+                        DRM_ERROR("Unsupported refreshrate type\n");
+                }
+        } else if (INTEL_INFO(dev)->gen > 6) {
                 reg = PIPECONF(intel_crtc->config->cpu_transcoder);
                 val = I915_READ(reg);
+
                 if (index > DRRS_HIGH_RR) {
-                        val |= PIPECONF_EDP_RR_MODE_SWITCH;
-                        intel_dp_set_m_n(intel_crtc);
+                        if (IS_VALLEYVIEW(dev))
+                                val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
+                        else
+                                val |= PIPECONF_EDP_RR_MODE_SWITCH;
                 } else {
-                        val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
+                        if (IS_VALLEYVIEW(dev))
+                                val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
+                        else
+                                val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
                 }
                 I915_WRITE(reg, val);
         }
@@ -4810,6 +4848,12 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
         DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
 }
 
+/**
+ * intel_edp_drrs_enable - init drrs struct if supported
+ * @intel_dp: DP struct
+ *
+ * Initializes frontbuffer_bits and drrs.dp
+ */
 void intel_edp_drrs_enable(struct intel_dp *intel_dp)
 {
         struct drm_device *dev = intel_dp_to_dev(intel_dp);
@@ -4837,6 +4881,11 @@ unlock:
         mutex_unlock(&dev_priv->drrs.mutex);
 }
 
+/**
+ * intel_edp_drrs_disable - Disable DRRS
+ * @intel_dp: DP struct
+ *
+ */
 void intel_edp_drrs_disable(struct intel_dp *intel_dp)
 {
         struct drm_device *dev = intel_dp_to_dev(intel_dp);
@@ -4896,6 +4945,17 @@ unlock:
         mutex_unlock(&dev_priv->drrs.mutex);
 }
 
+/**
+ * intel_edp_drrs_invalidate - Invalidate DRRS
+ * @dev: DRM device
+ * @frontbuffer_bits: frontbuffer plane tracking bits
+ *
+ * When there is a disturbance on screen (due to cursor movement/time
+ * update etc), DRRS needs to be invalidated, i.e. need to switch to
+ * high RR.
+ *
+ * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
+ */
 void intel_edp_drrs_invalidate(struct drm_device *dev,
                 unsigned frontbuffer_bits)
 {
@@ -4923,6 +4983,17 @@ void intel_edp_drrs_invalidate(struct drm_device *dev,
         mutex_unlock(&dev_priv->drrs.mutex);
 }
 
+/**
+ * intel_edp_drrs_flush - Flush DRRS
+ * @dev: DRM device
+ * @frontbuffer_bits: frontbuffer plane tracking bits
+ *
+ * When there is no movement on screen, DRRS work can be scheduled.
+ * This DRRS work is responsible for setting relevant registers after a
+ * timeout of 1 second.
+ *
+ * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
+ */
 void intel_edp_drrs_flush(struct drm_device *dev,
                 unsigned frontbuffer_bits)
 {
@@ -4947,6 +5018,56 @@ void intel_edp_drrs_flush(struct drm_device *dev,
         mutex_unlock(&dev_priv->drrs.mutex);
 }
 
+/**
+ * DOC: Display Refresh Rate Switching (DRRS)
+ *
+ * Display Refresh Rate Switching (DRRS) is a power conservation feature
+ * which enables swtching between low and high refresh rates,
+ * dynamically, based on the usage scenario. This feature is applicable
+ * for internal panels.
+ *
+ * Indication that the panel supports DRRS is given by the panel EDID, which
+ * would list multiple refresh rates for one resolution.
+ *
+ * DRRS is of 2 types - static and seamless.
+ * Static DRRS involves changing refresh rate (RR) by doing a full modeset
+ * (may appear as a blink on screen) and is used in dock-undock scenario.
+ * Seamless DRRS involves changing RR without any visual effect to the user
+ * and can be used during normal system usage. This is done by programming
+ * certain registers.
+ *
+ * Support for static/seamless DRRS may be indicated in the VBT based on
+ * inputs from the panel spec.
+ *
+ * DRRS saves power by switching to low RR based on usage scenarios.
+ *
+ * eDP DRRS:-
+ *        The implementation is based on frontbuffer tracking implementation.
+ * When there is a disturbance on the screen triggered by user activity or a
+ * periodic system activity, DRRS is disabled (RR is changed to high RR).
+ * When there is no movement on screen, after a timeout of 1 second, a switch
+ * to low RR is made.
+ *        For integration with frontbuffer tracking code,
+ * intel_edp_drrs_invalidate() and intel_edp_drrs_flush() are called.
+ *
+ * DRRS can be further extended to support other internal panels and also
+ * the scenario of video playback wherein RR is set based on the rate
+ * requested by userspace.
+ */
+
+/**
+ * intel_dp_drrs_init - Init basic DRRS work and mutex.
+ * @intel_connector: eDP connector
+ * @fixed_mode: preferred mode of panel
+ *
+ * This function is  called only once at driver load to initialize basic
+ * DRRS stuff.
+ *
+ * Returns:
+ * Downclock mode if panel supports it, else return NULL.
+ * DRRS support is determined by the presence of downclock mode (apart
+ * from VBT setting).
+ */
 static struct drm_display_mode *
 intel_dp_drrs_init(struct intel_connector *intel_connector,
                 struct drm_display_mode *fixed_mode)
@@ -4970,7 +5091,7 @@ intel_dp_drrs_init(struct intel_connector *intel_connector,
                                         (dev, fixed_mode, connector);
 
         if (!downclock_mode) {
-                DRM_DEBUG_KMS("DRRS not supported\n");
+                DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
                 return NULL;
         }
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index eef79ccd0b7c..f4aa849b243e 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -258,6 +258,7 @@ struct intel_plane_state {
 };
 
 struct intel_initial_plane_config {
+        struct intel_framebuffer *fb;
         unsigned int tiling;
         int size;
         u32 base;
@@ -500,6 +501,7 @@ struct intel_plane_wm_parameters {
         uint8_t bytes_per_pixel;
         bool enabled;
         bool scaled;
+        u64 tiling;
 };
 
 struct intel_plane {
@@ -592,6 +594,26 @@ struct intel_hdmi {
 struct intel_dp_mst_encoder;
 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 
+/*
+ * enum link_m_n_set:
+ *      When platform provides two set of M_N registers for dp, we can
+ *      program them and switch between them incase of DRRS.
+ *      But When only one such register is provided, we have to program the
+ *      required divider value on that registers itself based on the DRRS state.
+ *
+ * M1_N1        : Program dp_m_n on M1_N1 registers
+ *                        dp_m2_n2 on M2_N2 registers (If supported)
+ *
+ * M2_N2        : Program dp_m2_n2 on M1_N1 registers
+ *                        M2_N2 registers are not supported
+ */
+
+enum link_m_n_set {
+        /* Sets the m1_n1 and m2_n2 */
+        M1_N1 = 0,
+        M2_N2
+};
+
 struct intel_dp {
         uint32_t output_reg;
         uint32_t aux_ch_ctl_reg;
@@ -710,7 +732,7 @@ intel_get_crtc_for_plane(struct drm_device *dev, int plane)
 struct intel_unpin_work {
         struct work_struct work;
         struct drm_crtc *crtc;
-        struct drm_i915_gem_object *old_fb_obj;
+        struct drm_framebuffer *old_fb;
         struct drm_i915_gem_object *pending_flip_obj;
         struct drm_pending_vblank_event *event;
         atomic_t pending;
@@ -878,9 +900,12 @@ void intel_frontbuffer_flip(struct drm_device *dev,
 }
 
 int intel_fb_align_height(struct drm_device *dev, int height,
-                          unsigned int tiling);
+                          uint32_t pixel_format,
+                          uint64_t fb_format_modifier);
 void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire);
 
+u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
+                              uint32_t pixel_format);
 
 /* intel_audio.c */
 void intel_init_audio(struct drm_device *dev);
@@ -932,7 +957,6 @@ void intel_release_load_detect_pipe(struct drm_connector *connector,
 int intel_pin_and_fence_fb_obj(struct drm_plane *plane,
                                struct drm_framebuffer *fb,
                                struct intel_engine_cs *pipelined);
-void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
 struct drm_framebuffer *
 __intel_framebuffer_create(struct drm_device *dev,
                            struct drm_mode_fb_cmd2 *mode_cmd,
@@ -942,9 +966,11 @@ void intel_finish_page_flip(struct drm_device *dev, int pipe);
 void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
 void intel_check_page_flip(struct drm_device *dev, int pipe);
 int intel_prepare_plane_fb(struct drm_plane *plane,
-                           struct drm_framebuffer *fb);
+                           struct drm_framebuffer *fb,
+                           const struct drm_plane_state *new_state);
 void intel_cleanup_plane_fb(struct drm_plane *plane,
-                            struct drm_framebuffer *fb);
+                            struct drm_framebuffer *fb,
+                            const struct drm_plane_state *old_state);
 int intel_plane_atomic_get_property(struct drm_plane *plane,
                                     const struct drm_plane_state *state,
                                     struct drm_property *property,
@@ -993,7 +1019,7 @@ void hsw_enable_pc8(struct drm_i915_private *dev_priv);
 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
 void intel_dp_get_m_n(struct intel_crtc *crtc,
                       struct intel_crtc_state *pipe_config);
-void intel_dp_set_m_n(struct intel_crtc *crtc);
+void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
 void
 ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
@@ -1017,7 +1043,6 @@ void intel_dp_complete_link_train(struct intel_dp *intel_dp);
 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
-void intel_dp_check_link_status(struct intel_dp *intel_dp);
 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
 bool intel_dp_compute_config(struct intel_encoder *encoder,
                              struct intel_crtc_state *pipe_config);
@@ -1036,13 +1061,6 @@ int intel_dp_max_link_bw(struct intel_dp *intel_dp);
 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
-void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes);
-int intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
-                       struct drm_framebuffer *fb, int crtc_x, int crtc_y,
-                       unsigned int crtc_w, unsigned int crtc_h,
-                       uint32_t src_x, uint32_t src_y,
-                       uint32_t src_w, uint32_t src_h);
-int intel_disable_plane(struct drm_plane *plane);
 void intel_plane_destroy(struct drm_plane *plane);
 void intel_edp_drrs_enable(struct intel_dp *intel_dp);
 void intel_edp_drrs_disable(struct intel_dp *intel_dp);
@@ -1231,9 +1249,6 @@ bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
                                enum plane plane);
-int intel_plane_set_property(struct drm_plane *plane,
-                             struct drm_property *prop,
-                             uint64_t val);
 int intel_plane_restore(struct drm_plane *plane);
 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
                               struct drm_file *file_priv);
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 10ab68457ca8..c8c8b24e300c 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -854,7 +854,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
 
 
                 /* recovery disables */
-                I915_WRITE(MIPI_EOT_DISABLE(port), val);
+                I915_WRITE(MIPI_EOT_DISABLE(port), tmp);
 
                 /* in terms of low power clock */
                 I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count);
diff --git a/drivers/gpu/drm/i915/intel_dsi_cmd.h b/drivers/gpu/drm/i915/intel_dsi_cmd.h
deleted file mode 100644
index 886779030f1a..000000000000
--- a/drivers/gpu/drm/i915/intel_dsi_cmd.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Copyright © 2013 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Author: Jani Nikula <jani.nikula@intel.com>
- */
-
-#ifndef _INTEL_DSI_DSI_H
-#define _INTEL_DSI_DSI_H
-
-#include <drm/drmP.h>
-#include <drm/drm_crtc.h>
-#include <video/mipi_display.h>
-#include "i915_drv.h"
-#include "intel_drv.h"
-#include "intel_dsi.h"
-
-void dsi_hs_mode_enable(struct intel_dsi *intel_dsi, bool enable,
-                                                enum port port);
-
-#endif /* _INTEL_DSI_DSI_H */
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index 624d1d92d284..618f7bdab0ba 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -78,7 +78,8 @@ static void i8xx_fbc_enable(struct drm_crtc *crtc)
 
         dev_priv->fbc.enabled = true;
 
-        cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
+        /* Note: fbc.threshold == 1 for i8xx */
+        cfb_pitch = dev_priv->fbc.uncompressed_size / FBC_LL_SIZE;
         if (fb->pitches[0] < cfb_pitch)
                 cfb_pitch = fb->pitches[0];
 
@@ -368,7 +369,7 @@ static void intel_fbc_work_fn(struct work_struct *__work)
                 if (work->crtc->primary->fb == work->fb) {
                         dev_priv->display.enable_fbc(work->crtc);
 
-                        dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
+                        dev_priv->fbc.crtc = to_intel_crtc(work->crtc);
                         dev_priv->fbc.fb_id = work->crtc->primary->fb->base.id;
                         dev_priv->fbc.y = work->crtc->y;
                 }
@@ -459,7 +460,7 @@ void intel_fbc_disable(struct drm_device *dev)
                 return;
 
         dev_priv->display.disable_fbc(dev);
-        dev_priv->fbc.plane = -1;
+        dev_priv->fbc.crtc = NULL;
 }
 
 static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
@@ -472,6 +473,43 @@ static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
         return true;
 }
 
+static struct drm_crtc *intel_fbc_find_crtc(struct drm_i915_private *dev_priv)
+{
+        struct drm_crtc *crtc = NULL, *tmp_crtc;
+        enum pipe pipe;
+        bool pipe_a_only = false, one_pipe_only = false;
+
+        if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)
+                pipe_a_only = true;
+        else if (INTEL_INFO(dev_priv)->gen <= 4)
+                one_pipe_only = true;
+
+        for_each_pipe(dev_priv, pipe) {
+                tmp_crtc = dev_priv->pipe_to_crtc_mapping[pipe];
+
+                if (intel_crtc_active(tmp_crtc) &&
+                    to_intel_crtc(tmp_crtc)->primary_enabled) {
+                        if (one_pipe_only && crtc) {
+                                if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
+                                        DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
+                                return NULL;
+                        }
+                        crtc = tmp_crtc;
+                }
+
+                if (pipe_a_only)
+                        break;
+        }
+
+        if (!crtc || crtc->primary->fb == NULL) {
+                if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
+                        DRM_DEBUG_KMS("no output, disabling\n");
+                return NULL;
+        }
+
+        return crtc;
+}
+
 /**
  * intel_fbc_update - enable/disable FBC as needed
  * @dev: the drm_device
@@ -494,22 +532,30 @@ static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
 void intel_fbc_update(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
-        struct drm_crtc *crtc = NULL, *tmp_crtc;
+        struct drm_crtc *crtc = NULL;
         struct intel_crtc *intel_crtc;
         struct drm_framebuffer *fb;
         struct drm_i915_gem_object *obj;
         const struct drm_display_mode *adjusted_mode;
         unsigned int max_width, max_height;
 
-        if (!HAS_FBC(dev)) {
-                set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
+        if (!HAS_FBC(dev))
                 return;
+
+        /* disable framebuffer compression in vGPU */
+        if (intel_vgpu_active(dev))
+                i915.enable_fbc = 0;
+
+        if (i915.enable_fbc < 0) {
+                if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
+                        DRM_DEBUG_KMS("disabled per chip default\n");
+                goto out_disable;
         }
 
-        if (!i915.powersave) {
+        if (!i915.enable_fbc || !i915.powersave) {
                 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
                         DRM_DEBUG_KMS("fbc disabled per module param\n");
-                return;
+                goto out_disable;
         }
 
         /*
@@ -521,39 +567,15 @@ void intel_fbc_update(struct drm_device *dev)
          *   - new fb is too large to fit in compressed buffer
          *   - going to an unsupported config (interlace, pixel multiply, etc.)
          */
-        for_each_crtc(dev, tmp_crtc) {
-                if (intel_crtc_active(tmp_crtc) &&
-                    to_intel_crtc(tmp_crtc)->primary_enabled) {
-                        if (crtc) {
-                                if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
-                                        DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
-                                goto out_disable;
-                        }
-                        crtc = tmp_crtc;
-                }
-        }
-
-        if (!crtc || crtc->primary->fb == NULL) {
-                if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
-                        DRM_DEBUG_KMS("no output, disabling\n");
+        crtc = intel_fbc_find_crtc(dev_priv);
+        if (!crtc)
                 goto out_disable;
-        }
 
         intel_crtc = to_intel_crtc(crtc);
         fb = crtc->primary->fb;
         obj = intel_fb_obj(fb);
         adjusted_mode = &intel_crtc->config->base.adjusted_mode;
 
-        if (i915.enable_fbc < 0) {
-                if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
-                        DRM_DEBUG_KMS("disabled per chip default\n");
-                goto out_disable;
-        }
-        if (!i915.enable_fbc) {
-                if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
-                        DRM_DEBUG_KMS("fbc disabled per module param\n");
-                goto out_disable;
-        }
         if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
             (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
                 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
@@ -617,7 +639,7 @@ void intel_fbc_update(struct drm_device *dev)
          * cannot be unpinned (and have its GTT offset and fence revoked)
          * without first being decoupled from the scanout and FBC disabled.
          */
-        if (dev_priv->fbc.plane == intel_crtc->plane &&
+        if (dev_priv->fbc.crtc == intel_crtc &&
             dev_priv->fbc.fb_id == fb->base.id &&
             dev_priv->fbc.y == crtc->y)
                 return;
@@ -673,6 +695,7 @@ void intel_fbc_init(struct drm_i915_private *dev_priv)
 {
         if (!HAS_FBC(dev_priv)) {
                 dev_priv->fbc.enabled = false;
+                dev_priv->fbc.no_fbc_reason = FBC_UNSUPPORTED;
                 return;
         }
 
diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c
index 3001a8674611..234a699b8219 100644
--- a/drivers/gpu/drm/i915/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/intel_fbdev.c
@@ -594,7 +594,8 @@ static bool intel_fbdev_init_bios(struct drm_device *dev,
 
                 cur_size = intel_crtc->config->base.adjusted_mode.crtc_vdisplay;
                 cur_size = intel_fb_align_height(dev, cur_size,
-                                                 plane_config->tiling);
+                                                 fb->base.pixel_format,
+                                                 fb->base.modifier[0]);
                 cur_size *= fb->base.pitches[0];
                 DRM_DEBUG_KMS("pipe %c area: %dx%d, bpp: %d, size: %d\n",
                               pipe_name(intel_crtc->pipe),
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index e8d3da9f3373..fcb074bd55dc 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -254,8 +254,10 @@ u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj)
         return lrca >> 12;
 }
 
-static uint64_t execlists_ctx_descriptor(struct drm_i915_gem_object *ctx_obj)
+static uint64_t execlists_ctx_descriptor(struct intel_engine_cs *ring,
+                                         struct drm_i915_gem_object *ctx_obj)
 {
+        struct drm_device *dev = ring->dev;
         uint64_t desc;
         uint64_t lrca = i915_gem_obj_ggtt_offset(ctx_obj);
 
@@ -272,6 +274,13 @@ static uint64_t execlists_ctx_descriptor(struct drm_i915_gem_object *ctx_obj)
          * signalling between Command Streamers */
         /* desc |= GEN8_CTX_FORCE_RESTORE; */
 
+        /* WaEnableForceRestoreInCtxtDescForVCS:skl */
+        if (IS_GEN9(dev) &&
+            INTEL_REVID(dev) <= SKL_REVID_B0 &&
+            (ring->id == BCS || ring->id == VCS ||
+            ring->id == VECS || ring->id == VCS2))
+                desc |= GEN8_CTX_FORCE_RESTORE;
+
         return desc;
 }
 
@@ -286,13 +295,13 @@ static void execlists_elsp_write(struct intel_engine_cs *ring,
 
         /* XXX: You must always write both descriptors in the order below. */
         if (ctx_obj1)
-                temp = execlists_ctx_descriptor(ctx_obj1);
+                temp = execlists_ctx_descriptor(ring, ctx_obj1);
         else
                 temp = 0;
         desc[1] = (u32)(temp >> 32);
         desc[0] = (u32)temp;
 
-        temp = execlists_ctx_descriptor(ctx_obj0);
+        temp = execlists_ctx_descriptor(ring, ctx_obj0);
         desc[3] = (u32)(temp >> 32);
         desc[2] = (u32)temp;
 
@@ -612,7 +621,7 @@ static int execlists_move_to_gpu(struct intel_ringbuffer *ringbuf,
  * @vmas: list of vmas.
  * @batch_obj: the batchbuffer to submit.
  * @exec_start: batchbuffer start virtual address pointer.
- * @flags: translated execbuffer call flags.
+ * @dispatch_flags: translated execbuffer call flags.
  *
  * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts
  * away the submission details of the execbuffer ioctl call.
@@ -625,7 +634,7 @@ int intel_execlists_submission(struct drm_device *dev, struct drm_file *file,
                                struct drm_i915_gem_execbuffer2 *args,
                                struct list_head *vmas,
                                struct drm_i915_gem_object *batch_obj,
-                               u64 exec_start, u32 flags)
+                               u64 exec_start, u32 dispatch_flags)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
         struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
@@ -698,10 +707,12 @@ int intel_execlists_submission(struct drm_device *dev, struct drm_file *file,
                 dev_priv->relative_constants_mode = instp_mode;
         }
 
-        ret = ring->emit_bb_start(ringbuf, ctx, exec_start, flags);
+        ret = ring->emit_bb_start(ringbuf, ctx, exec_start, dispatch_flags);
         if (ret)
                 return ret;
 
+        trace_i915_gem_ring_dispatch(intel_ring_get_request(ring), dispatch_flags);
+
         i915_gem_execbuffer_move_to_active(vmas, ring);
         i915_gem_execbuffer_retire_commands(dev, file, ring, batch_obj);
 
@@ -776,7 +787,7 @@ int logical_ring_flush_all_caches(struct intel_ringbuffer *ringbuf,
         return 0;
 }
 
-/**
+/*
  * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload
  * @ringbuf: Logical Ringbuffer to advance.
  *
@@ -785,9 +796,10 @@ int logical_ring_flush_all_caches(struct intel_ringbuffer *ringbuf,
  * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
  * point, the tail *inside* the context is updated and the ELSP written to.
  */
-void intel_logical_ring_advance_and_submit(struct intel_ringbuffer *ringbuf,
-                                           struct intel_context *ctx,
-                                           struct drm_i915_gem_request *request)
+static void
+intel_logical_ring_advance_and_submit(struct intel_ringbuffer *ringbuf,
+                                      struct intel_context *ctx,
+                                      struct drm_i915_gem_request *request)
 {
         struct intel_engine_cs *ring = ringbuf->ring;
 
@@ -876,12 +888,9 @@ static int logical_ring_alloc_request(struct intel_engine_cs *ring,
                 return ret;
         }
 
-        /* Hold a reference to the context this request belongs to
-         * (we will need it when the time comes to emit/retire the
-         * request).
-         */
         request->ctx = ctx;
         i915_gem_context_reference(request->ctx);
+        request->ringbuf = ctx->engine[ring->id].ringbuf;
 
         ring->outstanding_lazy_request = request;
         return 0;
@@ -1140,11 +1149,22 @@ static int gen8_init_render_ring(struct intel_engine_cs *ring)
         return init_workarounds_ring(ring);
 }
 
+static int gen9_init_render_ring(struct intel_engine_cs *ring)
+{
+        int ret;
+
+        ret = gen8_init_common_ring(ring);
+        if (ret)
+                return ret;
+
+        return init_workarounds_ring(ring);
+}
+
 static int gen8_emit_bb_start(struct intel_ringbuffer *ringbuf,
                               struct intel_context *ctx,
-                              u64 offset, unsigned flags)
+                              u64 offset, unsigned dispatch_flags)
 {
-        bool ppgtt = !(flags & I915_DISPATCH_SECURE);
+        bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE);
         int ret;
 
         ret = intel_logical_ring_begin(ringbuf, ctx, 4);
@@ -1316,6 +1336,39 @@ static int gen8_emit_request(struct intel_ringbuffer *ringbuf,
         return 0;
 }
 
+static int intel_lr_context_render_state_init(struct intel_engine_cs *ring,
+                                              struct intel_context *ctx)
+{
+        struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
+        struct render_state so;
+        struct drm_i915_file_private *file_priv = ctx->file_priv;
+        struct drm_file *file = file_priv ? file_priv->file : NULL;
+        int ret;
+
+        ret = i915_gem_render_state_prepare(ring, &so);
+        if (ret)
+                return ret;
+
+        if (so.rodata == NULL)
+                return 0;
+
+        ret = ring->emit_bb_start(ringbuf,
+                        ctx,
+                        so.ggtt_offset,
+                        I915_DISPATCH_SECURE);
+        if (ret)
+                goto out;
+
+        i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), ring);
+
+        ret = __i915_add_request(ring, file, so.obj);
+        /* intel_logical_ring_add_request moves object to inactive if it
+         * fails */
+out:
+        i915_gem_render_state_fini(&so);
+        return ret;
+}
+
 static int gen8_init_rcs_context(struct intel_engine_cs *ring,
                        struct intel_context *ctx)
 {
@@ -1399,7 +1452,10 @@ static int logical_render_ring_init(struct drm_device *dev)
         if (HAS_L3_DPF(dev))
                 ring->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
 
-        ring->init_hw = gen8_init_render_ring;
+        if (INTEL_INFO(dev)->gen >= 9)
+                ring->init_hw = gen9_init_render_ring;
+        else
+                ring->init_hw = gen8_init_render_ring;
         ring->init_context = gen8_init_rcs_context;
         ring->cleanup = intel_fini_pipe_control;
         ring->get_seqno = gen8_get_seqno;
@@ -1581,37 +1637,47 @@ cleanup_render_ring:
         return ret;
 }
 
-int intel_lr_context_render_state_init(struct intel_engine_cs *ring,
-                                       struct intel_context *ctx)
+static u32
+make_rpcs(struct drm_device *dev)
 {
-        struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
-        struct render_state so;
-        struct drm_i915_file_private *file_priv = ctx->file_priv;
-        struct drm_file *file = file_priv ? file_priv->file : NULL;
-        int ret;
-
-        ret = i915_gem_render_state_prepare(ring, &so);
-        if (ret)
-                return ret;
+        u32 rpcs = 0;
 
-        if (so.rodata == NULL)
+        /*
+         * No explicit RPCS request is needed to ensure full
+         * slice/subslice/EU enablement prior to Gen9.
+        */
+        if (INTEL_INFO(dev)->gen < 9)
                 return 0;
 
-        ret = ring->emit_bb_start(ringbuf,
-                        ctx,
-                        so.ggtt_offset,
-                        I915_DISPATCH_SECURE);
-        if (ret)
-                goto out;
+        /*
+         * Starting in Gen9, render power gating can leave
+         * slice/subslice/EU in a partially enabled state. We
+         * must make an explicit request through RPCS for full
+         * enablement.
+        */
+        if (INTEL_INFO(dev)->has_slice_pg) {
+                rpcs |= GEN8_RPCS_S_CNT_ENABLE;
+                rpcs |= INTEL_INFO(dev)->slice_total <<
+                        GEN8_RPCS_S_CNT_SHIFT;
+                rpcs |= GEN8_RPCS_ENABLE;
+        }
 
-        i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), ring);
+        if (INTEL_INFO(dev)->has_subslice_pg) {
+                rpcs |= GEN8_RPCS_SS_CNT_ENABLE;
+                rpcs |= INTEL_INFO(dev)->subslice_per_slice <<
+                        GEN8_RPCS_SS_CNT_SHIFT;
+                rpcs |= GEN8_RPCS_ENABLE;
+        }
 
-        ret = __i915_add_request(ring, file, so.obj);
-        /* intel_logical_ring_add_request moves object to inactive if it
-         * fails */
-out:
-        i915_gem_render_state_fini(&so);
-        return ret;
+        if (INTEL_INFO(dev)->has_eu_pg) {
+                rpcs |= INTEL_INFO(dev)->eu_per_subslice <<
+                        GEN8_RPCS_EU_MIN_SHIFT;
+                rpcs |= INTEL_INFO(dev)->eu_per_subslice <<
+                        GEN8_RPCS_EU_MAX_SHIFT;
+                rpcs |= GEN8_RPCS_ENABLE;
+        }
+
+        return rpcs;
 }
 
 static int
@@ -1659,7 +1725,8 @@ populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_o
         reg_state[CTX_LRI_HEADER_0] |= MI_LRI_FORCE_POSTED;
         reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring);
         reg_state[CTX_CONTEXT_CONTROL+1] =
-                        _MASKED_BIT_ENABLE((1<<3) | MI_RESTORE_INHIBIT);
+                _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
+                                CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
         reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base);
         reg_state[CTX_RING_HEAD+1] = 0;
         reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base);
@@ -1706,18 +1773,18 @@ populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_o
         reg_state[CTX_PDP1_LDW] = GEN8_RING_PDP_LDW(ring, 1);
         reg_state[CTX_PDP0_UDW] = GEN8_RING_PDP_UDW(ring, 0);
         reg_state[CTX_PDP0_LDW] = GEN8_RING_PDP_LDW(ring, 0);
-        reg_state[CTX_PDP3_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[3]);
-        reg_state[CTX_PDP3_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[3]);
-        reg_state[CTX_PDP2_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[2]);
-        reg_state[CTX_PDP2_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[2]);
-        reg_state[CTX_PDP1_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[1]);
-        reg_state[CTX_PDP1_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[1]);
-        reg_state[CTX_PDP0_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[0]);
-        reg_state[CTX_PDP0_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[0]);
+        reg_state[CTX_PDP3_UDW+1] = upper_32_bits(ppgtt->pdp.page_directory[3]->daddr);
+        reg_state[CTX_PDP3_LDW+1] = lower_32_bits(ppgtt->pdp.page_directory[3]->daddr);
+        reg_state[CTX_PDP2_UDW+1] = upper_32_bits(ppgtt->pdp.page_directory[2]->daddr);
+        reg_state[CTX_PDP2_LDW+1] = lower_32_bits(ppgtt->pdp.page_directory[2]->daddr);
+        reg_state[CTX_PDP1_UDW+1] = upper_32_bits(ppgtt->pdp.page_directory[1]->daddr);
+        reg_state[CTX_PDP1_LDW+1] = lower_32_bits(ppgtt->pdp.page_directory[1]->daddr);
+        reg_state[CTX_PDP0_UDW+1] = upper_32_bits(ppgtt->pdp.page_directory[0]->daddr);
+        reg_state[CTX_PDP0_LDW+1] = lower_32_bits(ppgtt->pdp.page_directory[0]->daddr);
         if (ring->id == RCS) {
                 reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
-                reg_state[CTX_R_PWR_CLK_STATE] = 0x20c8;
-                reg_state[CTX_R_PWR_CLK_STATE+1] = 0;
+                reg_state[CTX_R_PWR_CLK_STATE] = GEN8_R_PWR_CLK_STATE;
+                reg_state[CTX_R_PWR_CLK_STATE+1] = make_rpcs(dev);
         }
 
         kunmap_atomic(reg_state);
@@ -1925,3 +1992,38 @@ error_unpin_ctx:
         drm_gem_object_unreference(&ctx_obj->base);
         return ret;
 }
+
+void intel_lr_context_reset(struct drm_device *dev,
+                        struct intel_context *ctx)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        struct intel_engine_cs *ring;
+        int i;
+
+        for_each_ring(ring, dev_priv, i) {
+                struct drm_i915_gem_object *ctx_obj =
+                                ctx->engine[ring->id].state;
+                struct intel_ringbuffer *ringbuf =
+                                ctx->engine[ring->id].ringbuf;
+                uint32_t *reg_state;
+                struct page *page;
+
+                if (!ctx_obj)
+                        continue;
+
+                if (i915_gem_object_get_pages(ctx_obj)) {
+                        WARN(1, "Failed get_pages for context obj\n");
+                        continue;
+                }
+                page = i915_gem_object_get_page(ctx_obj, 1);
+                reg_state = kmap_atomic(page);
+
+                reg_state[CTX_RING_HEAD+1] = 0;
+                reg_state[CTX_RING_TAIL+1] = 0;
+
+                kunmap_atomic(reg_state);
+
+                ringbuf->head = 0;
+                ringbuf->tail = 0;
+        }
+}
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index 6f2d7da594f6..adb731e49c57 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -30,6 +30,8 @@
 #define RING_ELSP(ring)                 ((ring)->mmio_base+0x230)
 #define RING_EXECLIST_STATUS(ring)      ((ring)->mmio_base+0x234)
 #define RING_CONTEXT_CONTROL(ring)      ((ring)->mmio_base+0x244)
+#define   CTX_CTRL_INHIBIT_SYN_CTX_SWITCH       (1 << 3)
+#define   CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT   (1 << 0)
 #define RING_CONTEXT_STATUS_BUF(ring)   ((ring)->mmio_base+0x370)
 #define RING_CONTEXT_STATUS_PTR(ring)   ((ring)->mmio_base+0x3a0)
 
@@ -40,10 +42,6 @@ int intel_logical_rings_init(struct drm_device *dev);
 
 int logical_ring_flush_all_caches(struct intel_ringbuffer *ringbuf,
                                   struct intel_context *ctx);
-void intel_logical_ring_advance_and_submit(
-                                struct intel_ringbuffer *ringbuf,
-                                struct intel_context *ctx,
-                                struct drm_i915_gem_request *request);
 /**
  * intel_logical_ring_advance() - advance the ringbuffer tail
  * @ringbuf: Ringbuffer to advance.
@@ -70,13 +68,13 @@ int intel_logical_ring_begin(struct intel_ringbuffer *ringbuf,
                              int num_dwords);
 
 /* Logical Ring Contexts */
-int intel_lr_context_render_state_init(struct intel_engine_cs *ring,
-                                       struct intel_context *ctx);
 void intel_lr_context_free(struct intel_context *ctx);
 int intel_lr_context_deferred_create(struct intel_context *ctx,
                                      struct intel_engine_cs *ring);
 void intel_lr_context_unpin(struct intel_engine_cs *ring,
                 struct intel_context *ctx);
+void intel_lr_context_reset(struct drm_device *dev,
+                        struct intel_context *ctx);
 
 /* Execlists */
 int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists);
@@ -86,7 +84,7 @@ int intel_execlists_submission(struct drm_device *dev, struct drm_file *file,
                                struct drm_i915_gem_execbuffer2 *args,
                                struct list_head *vmas,
                                struct drm_i915_gem_object *batch_obj,
-                               u64 exec_start, u32 flags);
+                               u64 exec_start, u32 dispatch_flags);
 u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj);
 
 void intel_lrc_irq_handler(struct intel_engine_cs *ring);
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 071b96d6e146..24e8730dc189 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -509,7 +509,7 @@ static int intel_lvds_set_property(struct drm_connector *connector,
                 intel_connector->panel.fitting_mode = value;
 
                 crtc = intel_attached_encoder(connector)->base.crtc;
-                if (crtc && crtc->enabled) {
+                if (crtc && crtc->state->enable) {
                         /*
                          * If the CRTC is enabled, the display will be changed
                          * according to the new panel fitting mode.
diff --git a/drivers/gpu/drm/i915/intel_opregion.c b/drivers/gpu/drm/i915/intel_opregion.c
index d8de1d5140a7..71e87abdcae7 100644
--- a/drivers/gpu/drm/i915/intel_opregion.c
+++ b/drivers/gpu/drm/i915/intel_opregion.c
@@ -744,10 +744,8 @@ void intel_opregion_init(struct drm_device *dev)
                 return;
 
         if (opregion->acpi) {
-                if (drm_core_check_feature(dev, DRIVER_MODESET)) {
-                        intel_didl_outputs(dev);
-                        intel_setup_cadls(dev);
-                }
+                intel_didl_outputs(dev);
+                intel_setup_cadls(dev);
 
                 /* Notify BIOS we are ready to handle ACPI video ext notifs.
                  * Right now, all the events are handled by the ACPI video module.
diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
index f93dfc174495..823d1d97a000 100644
--- a/drivers/gpu/drm/i915/intel_overlay.c
+++ b/drivers/gpu/drm/i915/intel_overlay.c
@@ -1065,7 +1065,6 @@ int intel_overlay_put_image(struct drm_device *dev, void *data,
         struct put_image_params *params;
         int ret;
 
-        /* No need to check for DRIVER_MODESET - we don't set it up then. */
         overlay = dev_priv->overlay;
         if (!overlay) {
                 DRM_DEBUG("userspace bug: no overlay\n");
@@ -1261,7 +1260,6 @@ int intel_overlay_attrs(struct drm_device *dev, void *data,
         struct overlay_registers __iomem *regs;
         int ret;
 
-        /* No need to check for DRIVER_MODESET - we don't set it up then. */
         overlay = dev_priv->overlay;
         if (!overlay) {
                 DRM_DEBUG("userspace bug: no overlay\n");
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 24d77ddcc5f4..542cf6844dc3 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -56,24 +56,42 @@ static void gen9_init_clock_gating(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
 
-        /*
-         * WaDisableSDEUnitClockGating:skl
-         * This seems to be a pre-production w/a.
-         */
-        I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
-                   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
+        /* WaEnableLbsSlaRetryTimerDecrement:skl */
+        I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
+                   GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
+}
 
-        /*
-         * WaDisableDgMirrorFixInHalfSliceChicken5:skl
-         * This is a pre-production w/a.
-         */
-        I915_WRITE(GEN9_HALF_SLICE_CHICKEN5,
-                   I915_READ(GEN9_HALF_SLICE_CHICKEN5) &
-                   ~GEN9_DG_MIRROR_FIX_ENABLE);
+static void skl_init_clock_gating(struct drm_device *dev)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
 
-        /* Wa4x4STCOptimizationDisable:skl */
-        I915_WRITE(CACHE_MODE_1,
-                   _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));
+        gen9_init_clock_gating(dev);
+
+        if (INTEL_REVID(dev) == SKL_REVID_A0) {
+                /*
+                 * WaDisableSDEUnitClockGating:skl
+                 * WaSetGAPSunitClckGateDisable:skl
+                 */
+                I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
+                           GEN8_GAPSUNIT_CLOCK_GATE_DISABLE |
+                           GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
+        }
+
+        if (INTEL_REVID(dev) <= SKL_REVID_D0) {
+                /* WaDisableHDCInvalidation:skl */
+                I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
+                           BDW_DISABLE_HDC_INVALIDATION);
+
+                /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
+                I915_WRITE(FF_SLICE_CS_CHICKEN2,
+                           I915_READ(FF_SLICE_CS_CHICKEN2) |
+                           GEN9_TSG_BARRIER_ACK_DISABLE);
+        }
+
+        if (INTEL_REVID(dev) <= SKL_REVID_E0)
+                /* WaDisableLSQCROPERFforOCL:skl */
+                I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
+                           GEN8_LQSC_RO_PERF_DIS);
 }
 
 static void i915_pineview_get_mem_freq(struct drm_device *dev)
@@ -1711,6 +1729,8 @@ static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
                                 GEN9_MEM_LATENCY_LEVEL_MASK;
 
                 /*
+                 * WaWmMemoryReadLatency:skl
+                 *
                  * punit doesn't take into account the read latency so we need
                  * to add 2us to the various latency levels we retrieve from
                  * the punit.
@@ -2502,6 +2522,7 @@ skl_allocate_pipe_ddb(struct drm_crtc *crtc,
         enum pipe pipe = intel_crtc->pipe;
         struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
         uint16_t alloc_size, start, cursor_blocks;
+        uint16_t minimum[I915_MAX_PLANES];
         unsigned int total_data_rate;
         int plane;
 
@@ -2520,9 +2541,21 @@ skl_allocate_pipe_ddb(struct drm_crtc *crtc,
         alloc_size -= cursor_blocks;
         alloc->end -= cursor_blocks;
 
+        /* 1. Allocate the mininum required blocks for each active plane */
+        for_each_plane(pipe, plane) {
+                const struct intel_plane_wm_parameters *p;
+
+                p = &params->plane[plane];
+                if (!p->enabled)
+                        continue;
+
+                minimum[plane] = 8;
+                alloc_size -= minimum[plane];
+        }
+
         /*
-         * Each active plane get a portion of the remaining space, in
-         * proportion to the amount of data they need to fetch from memory.
+         * 2. Distribute the remaining space in proportion to the amount of
+         * data each plane needs to fetch from memory.
          *
          * FIXME: we may not allocate every single block here.
          */
@@ -2544,8 +2577,9 @@ skl_allocate_pipe_ddb(struct drm_crtc *crtc,
                  * promote the expression to 64 bits to avoid overflowing, the
                  * result is < available as data_rate / total_data_rate < 1
                  */
-                plane_blocks = div_u64((uint64_t)alloc_size * data_rate,
-                                       total_data_rate);
+                plane_blocks = minimum[plane];
+                plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
+                                        total_data_rate);
 
                 ddb->plane[pipe][plane].start = start;
                 ddb->plane[pipe][plane].end = start + plane_blocks;
@@ -2575,7 +2609,7 @@ static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
         if (latency == 0)
                 return UINT_MAX;
 
-        wm_intermediate_val = latency * pixel_rate * bytes_per_pixel;
+        wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512;
         ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
 
         return ret;
@@ -2583,17 +2617,29 @@ static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
 
 static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
                                uint32_t horiz_pixels, uint8_t bytes_per_pixel,
-                               uint32_t latency)
+                               uint64_t tiling, uint32_t latency)
 {
-        uint32_t ret, plane_bytes_per_line, wm_intermediate_val;
+        uint32_t ret;
+        uint32_t plane_bytes_per_line, plane_blocks_per_line;
+        uint32_t wm_intermediate_val;
 
         if (latency == 0)
                 return UINT_MAX;
 
         plane_bytes_per_line = horiz_pixels * bytes_per_pixel;
+
+        if (tiling == I915_FORMAT_MOD_Y_TILED ||
+            tiling == I915_FORMAT_MOD_Yf_TILED) {
+                plane_bytes_per_line *= 4;
+                plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
+                plane_blocks_per_line /= 4;
+        } else {
+                plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
+        }
+
         wm_intermediate_val = latency * pixel_rate;
         ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
-                                plane_bytes_per_line;
+                                plane_blocks_per_line;
 
         return ret;
 }
@@ -2642,6 +2688,7 @@ static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
         enum pipe pipe = intel_crtc->pipe;
         struct drm_plane *plane;
+        struct drm_framebuffer *fb;
         int i = 1; /* Index for sprite planes start */
 
         p->active = intel_crtc_active(crtc);
@@ -2657,6 +2704,14 @@ static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
                         crtc->primary->fb->bits_per_pixel / 8;
                 p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w;
                 p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h;
+                p->plane[0].tiling = DRM_FORMAT_MOD_NONE;
+                fb = crtc->primary->state->fb;
+                /*
+                 * Framebuffer can be NULL on plane disable, but it does not
+                 * matter for watermarks if we assume no tiling in that case.
+                 */
+                if (fb)
+                        p->plane[0].tiling = fb->modifier[0];
 
                 p->cursor.enabled = true;
                 p->cursor.bytes_per_pixel = 4;
@@ -2673,41 +2728,60 @@ static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
         }
 }
 
-static bool skl_compute_plane_wm(struct skl_pipe_wm_parameters *p,
+static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
+                                 struct skl_pipe_wm_parameters *p,
                                  struct intel_plane_wm_parameters *p_params,
                                  uint16_t ddb_allocation,
-                                 uint32_t mem_value,
+                                 int level,
                                  uint16_t *out_blocks, /* out */
                                  uint8_t *out_lines /* out */)
 {
-        uint32_t method1, method2, plane_bytes_per_line, res_blocks, res_lines;
-        uint32_t result_bytes;
+        uint32_t latency = dev_priv->wm.skl_latency[level];
+        uint32_t method1, method2;
+        uint32_t plane_bytes_per_line, plane_blocks_per_line;
+        uint32_t res_blocks, res_lines;
+        uint32_t selected_result;
 
-        if (mem_value == 0 || !p->active || !p_params->enabled)
+        if (latency == 0 || !p->active || !p_params->enabled)
                 return false;
 
         method1 = skl_wm_method1(p->pixel_rate,
                                  p_params->bytes_per_pixel,
-                                 mem_value);
+                                 latency);
         method2 = skl_wm_method2(p->pixel_rate,
                                  p->pipe_htotal,
                                  p_params->horiz_pixels,
                                  p_params->bytes_per_pixel,
-                                 mem_value);
+                                 p_params->tiling,
+                                 latency);
 
         plane_bytes_per_line = p_params->horiz_pixels *
                                         p_params->bytes_per_pixel;
+        plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
 
-        /* For now xtile and linear */
-        if (((ddb_allocation * 512) / plane_bytes_per_line) >= 1)
-                result_bytes = min(method1, method2);
-        else
-                result_bytes = method1;
+        if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
+            p_params->tiling == I915_FORMAT_MOD_Yf_TILED) {
+                uint32_t y_tile_minimum = plane_blocks_per_line * 4;
+                selected_result = max(method2, y_tile_minimum);
+        } else {
+                if ((ddb_allocation / plane_blocks_per_line) >= 1)
+                        selected_result = min(method1, method2);
+                else
+                        selected_result = method1;
+        }
 
-        res_blocks = DIV_ROUND_UP(result_bytes, 512) + 1;
-        res_lines = DIV_ROUND_UP(result_bytes, plane_bytes_per_line);
+        res_blocks = selected_result + 1;
+        res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
+
+        if (level >= 1 && level <= 7) {
+                if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
+                    p_params->tiling == I915_FORMAT_MOD_Yf_TILED)
+                        res_lines += 4;
+                else
+                        res_blocks++;
+        }
 
-        if (res_blocks > ddb_allocation || res_lines > 31)
+        if (res_blocks >= ddb_allocation || res_lines > 31)
                 return false;
 
         *out_blocks = res_blocks;
@@ -2724,23 +2798,24 @@ static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
                                  int num_planes,
                                  struct skl_wm_level *result)
 {
-        uint16_t latency = dev_priv->wm.skl_latency[level];
         uint16_t ddb_blocks;
         int i;
 
         for (i = 0; i < num_planes; i++) {
                 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
 
-                result->plane_en[i] = skl_compute_plane_wm(p, &p->plane[i],
+                result->plane_en[i] = skl_compute_plane_wm(dev_priv,
+                                                p, &p->plane[i],
                                                 ddb_blocks,
-                                                latency,
+                                                level,
                                                 &result->plane_res_b[i],
                                                 &result->plane_res_l[i]);
         }
 
         ddb_blocks = skl_ddb_entry_size(&ddb->cursor[pipe]);
-        result->cursor_en = skl_compute_plane_wm(p, &p->cursor, ddb_blocks,
-                                                 latency, &result->cursor_res_b,
+        result->cursor_en = skl_compute_plane_wm(dev_priv, p, &p->cursor,
+                                                 ddb_blocks, level,
+                                                 &result->cursor_res_b,
                                                  &result->cursor_res_l);
 }
 
@@ -3133,12 +3208,20 @@ skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc,
                      int pixel_size, bool enabled, bool scaled)
 {
         struct intel_plane *intel_plane = to_intel_plane(plane);
+        struct drm_framebuffer *fb = plane->state->fb;
 
         intel_plane->wm.enabled = enabled;
         intel_plane->wm.scaled = scaled;
         intel_plane->wm.horiz_pixels = sprite_width;
         intel_plane->wm.vert_pixels = sprite_height;
         intel_plane->wm.bytes_per_pixel = pixel_size;
+        intel_plane->wm.tiling = DRM_FORMAT_MOD_NONE;
+        /*
+         * Framebuffer can be NULL on plane disable, but it does not
+         * matter for watermarks if we assume no tiling in that case.
+         */
+        if (fb)
+                intel_plane->wm.tiling = fb->modifier[0];
 
         skl_update_wm(crtc);
 }
@@ -3750,7 +3833,7 @@ static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
 /* gen6_set_rps is called to update the frequency request, but should also be
  * called when the range (min_delay and max_delay) is modified so that we can
  * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
-void gen6_set_rps(struct drm_device *dev, u8 val)
+static void gen6_set_rps(struct drm_device *dev, u8 val)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
 
@@ -3786,6 +3869,27 @@ void gen6_set_rps(struct drm_device *dev, u8 val)
         trace_intel_gpu_freq_change(val * 50);
 }
 
+static void valleyview_set_rps(struct drm_device *dev, u8 val)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+
+        WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
+        WARN_ON(val > dev_priv->rps.max_freq_softlimit);
+        WARN_ON(val < dev_priv->rps.min_freq_softlimit);
+
+        if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
+                      "Odd GPU freq value\n"))
+                val &= ~1;
+
+        if (val != dev_priv->rps.cur_freq)
+                vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
+
+        I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
+
+        dev_priv->rps.cur_freq = val;
+        trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
+}
+
 /* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
  *
  * * If Gfx is Idle, then
@@ -3850,38 +3954,20 @@ void gen6_rps_idle(struct drm_i915_private *dev_priv)
 
 void gen6_rps_boost(struct drm_i915_private *dev_priv)
 {
-        struct drm_device *dev = dev_priv->dev;
-
         mutex_lock(&dev_priv->rps.hw_lock);
         if (dev_priv->rps.enabled) {
-                if (IS_VALLEYVIEW(dev))
-                        valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
-                else
-                        gen6_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
+                intel_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
                 dev_priv->rps.last_adj = 0;
         }
         mutex_unlock(&dev_priv->rps.hw_lock);
 }
 
-void valleyview_set_rps(struct drm_device *dev, u8 val)
+void intel_set_rps(struct drm_device *dev, u8 val)
 {
-        struct drm_i915_private *dev_priv = dev->dev_private;
-
-        WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
-        WARN_ON(val > dev_priv->rps.max_freq_softlimit);
-        WARN_ON(val < dev_priv->rps.min_freq_softlimit);
-
-        if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
-                      "Odd GPU freq value\n"))
-                val &= ~1;
-
-        if (val != dev_priv->rps.cur_freq)
-                vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
-
-        I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
-
-        dev_priv->rps.cur_freq = val;
-        trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
+        if (IS_VALLEYVIEW(dev))
+                valleyview_set_rps(dev, val);
+        else
+                gen6_set_rps(dev, val);
 }
 
 static void gen9_disable_rps(struct drm_device *dev)
@@ -5633,6 +5719,10 @@ void intel_enable_gt_powersave(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
 
+        /* Powersaving is controlled by the host when inside a VM */
+        if (intel_vgpu_active(dev))
+                return;
+
         if (IS_IRONLAKE_M(dev)) {
                 mutex_lock(&dev->struct_mutex);
                 ironlake_enable_drps(dev);
@@ -6396,7 +6486,8 @@ void intel_init_clock_gating(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
 
-        dev_priv->display.init_clock_gating(dev);
+        if (dev_priv->display.init_clock_gating)
+                dev_priv->display.init_clock_gating(dev);
 }
 
 void intel_suspend_hw(struct drm_device *dev)
@@ -6422,7 +6513,7 @@ void intel_init_pm(struct drm_device *dev)
         if (INTEL_INFO(dev)->gen >= 9) {
                 skl_setup_wm_latency(dev);
 
-                dev_priv->display.init_clock_gating = gen9_init_clock_gating;
+                dev_priv->display.init_clock_gating = skl_init_clock_gating;
                 dev_priv->display.update_wm = skl_update_wm;
                 dev_priv->display.update_sprite_wm = skl_update_sprite_wm;
         } else if (HAS_PCH_SPLIT(dev)) {
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index e5b3c6dbd467..cd79c3843452 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -502,6 +502,68 @@ static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
         I915_WRITE(HWS_PGA, addr);
 }
 
+static void intel_ring_setup_status_page(struct intel_engine_cs *ring)
+{
+        struct drm_device *dev = ring->dev;
+        struct drm_i915_private *dev_priv = ring->dev->dev_private;
+        u32 mmio = 0;
+
+        /* The ring status page addresses are no longer next to the rest of
+         * the ring registers as of gen7.
+         */
+        if (IS_GEN7(dev)) {
+                switch (ring->id) {
+                case RCS:
+                        mmio = RENDER_HWS_PGA_GEN7;
+                        break;
+                case BCS:
+                        mmio = BLT_HWS_PGA_GEN7;
+                        break;
+                /*
+                 * VCS2 actually doesn't exist on Gen7. Only shut up
+                 * gcc switch check warning
+                 */
+                case VCS2:
+                case VCS:
+                        mmio = BSD_HWS_PGA_GEN7;
+                        break;
+                case VECS:
+                        mmio = VEBOX_HWS_PGA_GEN7;
+                        break;
+                }
+        } else if (IS_GEN6(ring->dev)) {
+                mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
+        } else {
+                /* XXX: gen8 returns to sanity */
+                mmio = RING_HWS_PGA(ring->mmio_base);
+        }
+
+        I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
+        POSTING_READ(mmio);
+
+        /*
+         * Flush the TLB for this page
+         *
+         * FIXME: These two bits have disappeared on gen8, so a question
+         * arises: do we still need this and if so how should we go about
+         * invalidating the TLB?
+         */
+        if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
+                u32 reg = RING_INSTPM(ring->mmio_base);
+
+                /* ring should be idle before issuing a sync flush*/
+                WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
+
+                I915_WRITE(reg,
+                           _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
+                                              INSTPM_SYNC_FLUSH));
+                if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
+                             1000))
+                        DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
+                                  ring->name);
+        }
+}
+
 static bool stop_ring(struct intel_engine_cs *ring)
 {
         struct drm_i915_private *dev_priv = to_i915(ring->dev);
@@ -788,12 +850,14 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
          * workaround for for a possible hang in the unlikely event a TLB
          * invalidation occurs during a PSD flush.
          */
-        /* WaForceEnableNonCoherent:bdw */
-        /* WaHdcDisableFetchWhenMasked:bdw */
-        /* WaDisableFenceDestinationToSLM:bdw (GT3 pre-production) */
         WA_SET_BIT_MASKED(HDC_CHICKEN0,
+                          /* WaForceEnableNonCoherent:bdw */
                           HDC_FORCE_NON_COHERENT |
+                          /* WaForceContextSaveRestoreNonCoherent:bdw */
+                          HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
+                          /* WaHdcDisableFetchWhenMasked:bdw */
                           HDC_DONOT_FETCH_MEM_WHEN_MASKED |
+                          /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
                           (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
 
         /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
@@ -870,9 +934,132 @@ static int chv_init_workarounds(struct intel_engine_cs *ring)
                             GEN6_WIZ_HASHING_MASK,
                             GEN6_WIZ_HASHING_16x4);
 
+        if (INTEL_REVID(dev) == SKL_REVID_C0 ||
+            INTEL_REVID(dev) == SKL_REVID_D0)
+                /* WaBarrierPerformanceFixDisable:skl */
+                WA_SET_BIT_MASKED(HDC_CHICKEN0,
+                                  HDC_FENCE_DEST_SLM_DISABLE |
+                                  HDC_BARRIER_PERFORMANCE_DISABLE);
+
+        return 0;
+}
+
+static int gen9_init_workarounds(struct intel_engine_cs *ring)
+{
+        struct drm_device *dev = ring->dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+
+        /* WaDisablePartialInstShootdown:skl */
+        WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
+                          PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
+
+        /* Syncing dependencies between camera and graphics */
+        WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
+                          GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
+
+        if (INTEL_REVID(dev) == SKL_REVID_A0 ||
+            INTEL_REVID(dev) == SKL_REVID_B0) {
+                /* WaDisableDgMirrorFixInHalfSliceChicken5:skl */
+                WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
+                                  GEN9_DG_MIRROR_FIX_ENABLE);
+        }
+
+        if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) {
+                /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl */
+                WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
+                                  GEN9_RHWO_OPTIMIZATION_DISABLE);
+                WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN0,
+                                  DISABLE_PIXEL_MASK_CAMMING);
+        }
+
+        if (INTEL_REVID(dev) >= SKL_REVID_C0) {
+                /* WaEnableYV12BugFixInHalfSliceChicken7:skl */
+                WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
+                                  GEN9_ENABLE_YV12_BUGFIX);
+        }
+
+        if (INTEL_REVID(dev) <= SKL_REVID_D0) {
+                /*
+                 *Use Force Non-Coherent whenever executing a 3D context. This
+                 * is a workaround for a possible hang in the unlikely event
+                 * a TLB invalidation occurs during a PSD flush.
+                 */
+                /* WaForceEnableNonCoherent:skl */
+                WA_SET_BIT_MASKED(HDC_CHICKEN0,
+                                  HDC_FORCE_NON_COHERENT);
+        }
+
+        /* Wa4x4STCOptimizationDisable:skl */
+        WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
+
+        /* WaDisablePartialResolveInVc:skl */
+        WA_SET_BIT_MASKED(CACHE_MODE_1, GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE);
+
+        /* WaCcsTlbPrefetchDisable:skl */
+        WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
+                          GEN9_CCS_TLB_PREFETCH_ENABLE);
+
+        return 0;
+}
+
+static int skl_tune_iz_hashing(struct intel_engine_cs *ring)
+{
+        struct drm_device *dev = ring->dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        u8 vals[3] = { 0, 0, 0 };
+        unsigned int i;
+
+        for (i = 0; i < 3; i++) {
+                u8 ss;
+
+                /*
+                 * Only consider slices where one, and only one, subslice has 7
+                 * EUs
+                 */
+                if (hweight8(dev_priv->info.subslice_7eu[i]) != 1)
+                        continue;
+
+                /*
+                 * subslice_7eu[i] != 0 (because of the check above) and
+                 * ss_max == 4 (maximum number of subslices possible per slice)
+                 *
+                 * ->    0 <= ss <= 3;
+                 */
+                ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
+                vals[i] = 3 - ss;
+        }
+
+        if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
+                return 0;
+
+        /* Tune IZ hashing. See intel_device_info_runtime_init() */
+        WA_SET_FIELD_MASKED(GEN7_GT_MODE,
+                            GEN9_IZ_HASHING_MASK(2) |
+                            GEN9_IZ_HASHING_MASK(1) |
+                            GEN9_IZ_HASHING_MASK(0),
+                            GEN9_IZ_HASHING(2, vals[2]) |
+                            GEN9_IZ_HASHING(1, vals[1]) |
+                            GEN9_IZ_HASHING(0, vals[0]));
+
         return 0;
 }
 
+
+static int skl_init_workarounds(struct intel_engine_cs *ring)
+{
+        struct drm_device *dev = ring->dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+
+        gen9_init_workarounds(ring);
+
+        /* WaDisablePowerCompilerClockGating:skl */
+        if (INTEL_REVID(dev) == SKL_REVID_B0)
+                WA_SET_BIT_MASKED(HIZ_CHICKEN,
+                                  BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
+
+        return skl_tune_iz_hashing(ring);
+}
+
 int init_workarounds_ring(struct intel_engine_cs *ring)
 {
         struct drm_device *dev = ring->dev;
@@ -888,6 +1075,11 @@ int init_workarounds_ring(struct intel_engine_cs *ring)
         if (IS_CHERRYVIEW(dev))
                 return chv_init_workarounds(ring);
 
+        if (IS_SKYLAKE(dev))
+                return skl_init_workarounds(ring);
+        else if (IS_GEN9(dev))
+                return gen9_init_workarounds(ring);
+
         return 0;
 }
 
@@ -1386,68 +1578,6 @@ i8xx_ring_put_irq(struct intel_engine_cs *ring)
         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 }
 
-void intel_ring_setup_status_page(struct intel_engine_cs *ring)
-{
-        struct drm_device *dev = ring->dev;
-        struct drm_i915_private *dev_priv = ring->dev->dev_private;
-        u32 mmio = 0;
-
-        /* The ring status page addresses are no longer next to the rest of
-         * the ring registers as of gen7.
-         */
-        if (IS_GEN7(dev)) {
-                switch (ring->id) {
-                case RCS:
-                        mmio = RENDER_HWS_PGA_GEN7;
-                        break;
-                case BCS:
-                        mmio = BLT_HWS_PGA_GEN7;
-                        break;
-                /*
-                 * VCS2 actually doesn't exist on Gen7. Only shut up
-                 * gcc switch check warning
-                 */
-                case VCS2:
-                case VCS:
-                        mmio = BSD_HWS_PGA_GEN7;
-                        break;
-                case VECS:
-                        mmio = VEBOX_HWS_PGA_GEN7;
-                        break;
-                }
-        } else if (IS_GEN6(ring->dev)) {
-                mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
-        } else {
-                /* XXX: gen8 returns to sanity */
-                mmio = RING_HWS_PGA(ring->mmio_base);
-        }
-
-        I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
-        POSTING_READ(mmio);
-
-        /*
-         * Flush the TLB for this page
-         *
-         * FIXME: These two bits have disappeared on gen8, so a question
-         * arises: do we still need this and if so how should we go about
-         * invalidating the TLB?
-         */
-        if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
-                u32 reg = RING_INSTPM(ring->mmio_base);
-
-                /* ring should be idle before issuing a sync flush*/
-                WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
-
-                I915_WRITE(reg,
-                           _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
-                                              INSTPM_SYNC_FLUSH));
-                if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
-                             1000))
-                        DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
-                                  ring->name);
-        }
-}
-
 static int
 bsd_ring_flush(struct intel_engine_cs *ring,
                u32     invalidate_domains,
@@ -1611,7 +1741,7 @@ gen8_ring_put_irq(struct intel_engine_cs *ring)
 static int
 i965_dispatch_execbuffer(struct intel_engine_cs *ring,
                          u64 offset, u32 length,
-                         unsigned flags)
+                         unsigned dispatch_flags)
 {
         int ret;
 
@@ -1622,7 +1752,8 @@ i965_dispatch_execbuffer(struct intel_engine_cs *ring,
         intel_ring_emit(ring,
                         MI_BATCH_BUFFER_START |
                         MI_BATCH_GTT |
-                        (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
+                        (dispatch_flags & I915_DISPATCH_SECURE ?
+                         0 : MI_BATCH_NON_SECURE_I965));
         intel_ring_emit(ring, offset);
         intel_ring_advance(ring);
 
@@ -1635,8 +1766,8 @@ i965_dispatch_execbuffer(struct intel_engine_cs *ring,
 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
 static int
 i830_dispatch_execbuffer(struct intel_engine_cs *ring,
-                                u64 offset, u32 len,
-                                unsigned flags)
+                         u64 offset, u32 len,
+                         unsigned dispatch_flags)
 {
         u32 cs_offset = ring->scratch.gtt_offset;
         int ret;
@@ -1654,7 +1785,7 @@ i830_dispatch_execbuffer(struct intel_engine_cs *ring,
         intel_ring_emit(ring, MI_NOOP);
         intel_ring_advance(ring);
 
-        if ((flags & I915_DISPATCH_PINNED) == 0) {
+        if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
                 if (len > I830_BATCH_LIMIT)
                         return -ENOSPC;
 
@@ -1686,7 +1817,8 @@ i830_dispatch_execbuffer(struct intel_engine_cs *ring,
                 return ret;
 
         intel_ring_emit(ring, MI_BATCH_BUFFER);
-        intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
+        intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
+                                        0 : MI_BATCH_NON_SECURE));
         intel_ring_emit(ring, offset + len - 8);
         intel_ring_emit(ring, MI_NOOP);
         intel_ring_advance(ring);
@@ -1697,7 +1829,7 @@ i830_dispatch_execbuffer(struct intel_engine_cs *ring,
 static int
 i915_dispatch_execbuffer(struct intel_engine_cs *ring,
                          u64 offset, u32 len,
-                         unsigned flags)
+                         unsigned dispatch_flags)
 {
         int ret;
 
@@ -1706,7 +1838,8 @@ i915_dispatch_execbuffer(struct intel_engine_cs *ring,
                 return ret;
 
         intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
-        intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
+        intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
+                                        0 : MI_BATCH_NON_SECURE));
         intel_ring_advance(ring);
 
         return 0;
@@ -2097,6 +2230,7 @@ intel_ring_alloc_request(struct intel_engine_cs *ring)
 
         kref_init(&request->ref);
         request->ring = ring;
+        request->ringbuf = ring->buffer;
         request->uniq = dev_private->request_uniq++;
 
         ret = i915_gem_get_seqno(ring->dev, &request->seqno);
@@ -2273,9 +2407,10 @@ static int gen6_bsd_ring_flush(struct intel_engine_cs *ring,
 static int
 gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
                               u64 offset, u32 len,
-                              unsigned flags)
+                              unsigned dispatch_flags)
 {
-        bool ppgtt = USES_PPGTT(ring->dev) && !(flags & I915_DISPATCH_SECURE);
+        bool ppgtt = USES_PPGTT(ring->dev) &&
+                        !(dispatch_flags & I915_DISPATCH_SECURE);
         int ret;
 
         ret = intel_ring_begin(ring, 4);
@@ -2294,8 +2429,8 @@ gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
 
 static int
 hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
-                              u64 offset, u32 len,
-                              unsigned flags)
+                             u64 offset, u32 len,
+                             unsigned dispatch_flags)
 {
         int ret;
 
@@ -2305,7 +2440,7 @@ hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
 
         intel_ring_emit(ring,
                         MI_BATCH_BUFFER_START |
-                        (flags & I915_DISPATCH_SECURE ?
+                        (dispatch_flags & I915_DISPATCH_SECURE ?
                          0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW));
         /* bit0-7 is the length on GEN6+ */
         intel_ring_emit(ring, offset);
@@ -2317,7 +2452,7 @@ hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
 static int
 gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
                               u64 offset, u32 len,
-                              unsigned flags)
+                              unsigned dispatch_flags)
 {
         int ret;
 
@@ -2327,7 +2462,8 @@ gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
 
         intel_ring_emit(ring,
                         MI_BATCH_BUFFER_START |
-                        (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
+                        (dispatch_flags & I915_DISPATCH_SECURE ?
+                         0 : MI_BATCH_NON_SECURE_I965));
         /* bit0-7 is the length on GEN6+ */
         intel_ring_emit(ring, offset);
         intel_ring_advance(ring);
@@ -2612,19 +2748,13 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
 }
 
 /**
- * Initialize the second BSD ring for Broadwell GT3.
- * It is noted that this only exists on Broadwell GT3.
+ * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
  */
 int intel_init_bsd2_ring_buffer(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
         struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
 
-        if ((INTEL_INFO(dev)->gen != 8)) {
-                DRM_ERROR("No dual-BSD ring on non-BDW machine\n");
-                return -EINVAL;
-        }
-
         ring->name = "bsd2 ring";
         ring->id = VCS2;
 
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 714f3fdd57d2..8f3b49a23ccf 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -164,7 +164,7 @@ struct  intel_engine_cs {
                                      u32 seqno);
         int             (*dispatch_execbuffer)(struct intel_engine_cs *ring,
                                                u64 offset, u32 length,
-                                               unsigned flags);
+                                               unsigned dispatch_flags);
 #define I915_DISPATCH_SECURE 0x1
 #define I915_DISPATCH_PINNED 0x2
         void            (*cleanup)(struct intel_engine_cs *ring);
@@ -242,7 +242,7 @@ struct  intel_engine_cs {
                                       u32 flush_domains);
         int             (*emit_bb_start)(struct intel_ringbuffer *ringbuf,
                                          struct intel_context *ctx,
-                                         u64 offset, unsigned flags);
+                                         u64 offset, unsigned dispatch_flags);
 
         /**
          * List of objects currently involved in rendering from the
@@ -373,11 +373,12 @@ intel_write_status_page(struct intel_engine_cs *ring,
  * 0x06: ring 2 head pointer (915-class)
  * 0x10-0x1b: Context status DWords (GM45)
  * 0x1f: Last written status offset. (GM45)
+ * 0x20-0x2f: Reserved (Gen6+)
  *
- * The area from dword 0x20 to 0x3ff is available for driver usage.
+ * The area from dword 0x30 to 0x3ff is available for driver usage.
  */
-#define I915_GEM_HWS_INDEX              0x20
-#define I915_GEM_HWS_SCRATCH_INDEX      0x30
+#define I915_GEM_HWS_INDEX              0x30
+#define I915_GEM_HWS_SCRATCH_INDEX      0x40
 #define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
 
 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf);
@@ -425,7 +426,6 @@ int intel_init_blt_ring_buffer(struct drm_device *dev);
 int intel_init_vebox_ring_buffer(struct drm_device *dev);
 
 u64 intel_ring_get_active_head(struct intel_engine_cs *ring);
-void intel_ring_setup_status_page(struct intel_engine_cs *ring);
 
 int init_workarounds_ring(struct intel_engine_cs *ring);
 
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 49695d7d51e3..6d8e29abbc33 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -230,6 +230,136 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv,
         }
 }
 
+#define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS (         \
+        BIT(POWER_DOMAIN_TRANSCODER_A) |                \
+        BIT(POWER_DOMAIN_PIPE_B) |                      \
+        BIT(POWER_DOMAIN_TRANSCODER_B) |                \
+        BIT(POWER_DOMAIN_PIPE_C) |                      \
+        BIT(POWER_DOMAIN_TRANSCODER_C) |                \
+        BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
+        BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
+        BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |          \
+        BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |          \
+        BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |          \
+        BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |          \
+        BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) |          \
+        BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |          \
+        BIT(POWER_DOMAIN_AUX_B) |                       \
+        BIT(POWER_DOMAIN_AUX_C) |                       \
+        BIT(POWER_DOMAIN_AUX_D) |                       \
+        BIT(POWER_DOMAIN_AUDIO) |                       \
+        BIT(POWER_DOMAIN_VGA) |                         \
+        BIT(POWER_DOMAIN_INIT))
+#define SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS (         \
+        SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
+        BIT(POWER_DOMAIN_PLLS) |                        \
+        BIT(POWER_DOMAIN_PIPE_A) |                      \
+        BIT(POWER_DOMAIN_TRANSCODER_EDP) |              \
+        BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) |         \
+        BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) |          \
+        BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) |          \
+        BIT(POWER_DOMAIN_AUX_A) |                       \
+        BIT(POWER_DOMAIN_INIT))
+#define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS (             \
+        BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) |          \
+        BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) |          \
+        BIT(POWER_DOMAIN_INIT))
+#define SKL_DISPLAY_DDI_B_POWER_DOMAINS (               \
+        BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |          \
+        BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |          \
+        BIT(POWER_DOMAIN_INIT))
+#define SKL_DISPLAY_DDI_C_POWER_DOMAINS (               \
+        BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |          \
+        BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |          \
+        BIT(POWER_DOMAIN_INIT))
+#define SKL_DISPLAY_DDI_D_POWER_DOMAINS (               \
+        BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) |          \
+        BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |          \
+        BIT(POWER_DOMAIN_INIT))
+#define SKL_DISPLAY_MISC_IO_POWER_DOMAINS (             \
+        SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS)
+#define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS (           \
+        (POWER_DOMAIN_MASK & ~(SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS |  \
+        SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
+        SKL_DISPLAY_DDI_A_E_POWER_DOMAINS |             \
+        SKL_DISPLAY_DDI_B_POWER_DOMAINS |               \
+        SKL_DISPLAY_DDI_C_POWER_DOMAINS |               \
+        SKL_DISPLAY_DDI_D_POWER_DOMAINS |               \
+        SKL_DISPLAY_MISC_IO_POWER_DOMAINS)) |           \
+        BIT(POWER_DOMAIN_INIT))
+
+static void skl_set_power_well(struct drm_i915_private *dev_priv,
+                        struct i915_power_well *power_well, bool enable)
+{
+        uint32_t tmp, fuse_status;
+        uint32_t req_mask, state_mask;
+        bool check_fuse_status = false;
+
+        tmp = I915_READ(HSW_PWR_WELL_DRIVER);
+        fuse_status = I915_READ(SKL_FUSE_STATUS);
+
+        switch (power_well->data) {
+        case SKL_DISP_PW_1:
+                if (wait_for((I915_READ(SKL_FUSE_STATUS) &
+                        SKL_FUSE_PG0_DIST_STATUS), 1)) {
+                        DRM_ERROR("PG0 not enabled\n");
+                        return;
+                }
+                break;
+        case SKL_DISP_PW_2:
+                if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) {
+                        DRM_ERROR("PG1 in disabled state\n");
+                        return;
+                }
+                break;
+        case SKL_DISP_PW_DDI_A_E:
+        case SKL_DISP_PW_DDI_B:
+        case SKL_DISP_PW_DDI_C:
+        case SKL_DISP_PW_DDI_D:
+        case SKL_DISP_PW_MISC_IO:
+                break;
+        default:
+                WARN(1, "Unknown power well %lu\n", power_well->data);
+                return;
+        }
+
+        req_mask = SKL_POWER_WELL_REQ(power_well->data);
+        state_mask = SKL_POWER_WELL_STATE(power_well->data);
+
+        if (enable) {
+                if (!(tmp & req_mask)) {
+                        I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);
+                        DRM_DEBUG_KMS("Enabling %s\n", power_well->name);
+                }
+
+                if (!(tmp & state_mask)) {
+                        if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
+                                state_mask), 1))
+                                DRM_ERROR("%s enable timeout\n",
+                                        power_well->name);
+                        check_fuse_status = true;
+                }
+        } else {
+                if (tmp & req_mask) {
+                        I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask);
+                        POSTING_READ(HSW_PWR_WELL_DRIVER);
+                        DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
+                }
+        }
+
+        if (check_fuse_status) {
+                if (power_well->data == SKL_DISP_PW_1) {
+                        if (wait_for((I915_READ(SKL_FUSE_STATUS) &
+                                SKL_FUSE_PG1_DIST_STATUS), 1))
+                                DRM_ERROR("PG1 distributing status timeout\n");
+                } else if (power_well->data == SKL_DISP_PW_2) {
+                        if (wait_for((I915_READ(SKL_FUSE_STATUS) &
+                                SKL_FUSE_PG2_DIST_STATUS), 1))
+                                DRM_ERROR("PG2 distributing status timeout\n");
+                }
+        }
+}
+
 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
                                    struct i915_power_well *power_well)
 {
@@ -255,6 +385,36 @@ static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
         hsw_set_power_well(dev_priv, power_well, false);
 }
 
+static bool skl_power_well_enabled(struct drm_i915_private *dev_priv,
+                                        struct i915_power_well *power_well)
+{
+        uint32_t mask = SKL_POWER_WELL_REQ(power_well->data) |
+                SKL_POWER_WELL_STATE(power_well->data);
+
+        return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask;
+}
+
+static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv,
+                                struct i915_power_well *power_well)
+{
+        skl_set_power_well(dev_priv, power_well, power_well->count > 0);
+
+        /* Clear any request made by BIOS as driver is taking over */
+        I915_WRITE(HSW_PWR_WELL_BIOS, 0);
+}
+
+static void skl_power_well_enable(struct drm_i915_private *dev_priv,
+                                struct i915_power_well *power_well)
+{
+        skl_set_power_well(dev_priv, power_well, true);
+}
+
+static void skl_power_well_disable(struct drm_i915_private *dev_priv,
+                                struct i915_power_well *power_well)
+{
+        skl_set_power_well(dev_priv, power_well, false);
+}
+
 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
                                            struct i915_power_well *power_well)
 {
@@ -829,6 +989,13 @@ static const struct i915_power_well_ops hsw_power_well_ops = {
         .is_enabled = hsw_power_well_enabled,
 };
 
+static const struct i915_power_well_ops skl_power_well_ops = {
+        .sync_hw = skl_power_well_sync_hw,
+        .enable = skl_power_well_enable,
+        .disable = skl_power_well_disable,
+        .is_enabled = skl_power_well_enabled,
+};
+
 static struct i915_power_well hsw_power_wells[] = {
         {
                 .name = "always-on",
@@ -1059,6 +1226,57 @@ static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_pr
         return NULL;
 }
 
+static struct i915_power_well skl_power_wells[] = {
+        {
+                .name = "always-on",
+                .always_on = 1,
+                .domains = SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS,
+                .ops = &i9xx_always_on_power_well_ops,
+        },
+        {
+                .name = "power well 1",
+                .domains = SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS,
+                .ops = &skl_power_well_ops,
+                .data = SKL_DISP_PW_1,
+        },
+        {
+                .name = "MISC IO power well",
+                .domains = SKL_DISPLAY_MISC_IO_POWER_DOMAINS,
+                .ops = &skl_power_well_ops,
+                .data = SKL_DISP_PW_MISC_IO,
+        },
+        {
+                .name = "power well 2",
+                .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
+                .ops = &skl_power_well_ops,
+                .data = SKL_DISP_PW_2,
+        },
+        {
+                .name = "DDI A/E power well",
+                .domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS,
+                .ops = &skl_power_well_ops,
+                .data = SKL_DISP_PW_DDI_A_E,
+        },
+        {
+                .name = "DDI B power well",
+                .domains = SKL_DISPLAY_DDI_B_POWER_DOMAINS,
+                .ops = &skl_power_well_ops,
+                .data = SKL_DISP_PW_DDI_B,
+        },
+        {
+                .name = "DDI C power well",
+                .domains = SKL_DISPLAY_DDI_C_POWER_DOMAINS,
+                .ops = &skl_power_well_ops,
+                .data = SKL_DISP_PW_DDI_C,
+        },
+        {
+                .name = "DDI D power well",
+                .domains = SKL_DISPLAY_DDI_D_POWER_DOMAINS,
+                .ops = &skl_power_well_ops,
+                .data = SKL_DISP_PW_DDI_D,
+        },
+};
+
 #define set_power_wells(power_domains, __power_wells) ({                \
         (power_domains)->power_wells = (__power_wells);                 \
         (power_domains)->power_well_count = ARRAY_SIZE(__power_wells);  \
@@ -1085,6 +1303,8 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
                 set_power_wells(power_domains, hsw_power_wells);
         } else if (IS_BROADWELL(dev_priv->dev)) {
                 set_power_wells(power_domains, bdw_power_wells);
+        } else if (IS_SKYLAKE(dev_priv->dev)) {
+                set_power_wells(power_domains, skl_power_wells);
         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
                 set_power_wells(power_domains, chv_power_wells);
         } else if (IS_VALLEYVIEW(dev_priv->dev)) {
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 0a52c44ad03d..7051da7015d3 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -98,7 +98,7 @@ bool intel_pipe_update_start(struct intel_crtc *crtc, uint32_t *start_vbl_count)
         if (min <= 0 || max <= 0)
                 return false;
 
-        if (WARN_ON(drm_vblank_get(dev, pipe)))
+        if (WARN_ON(drm_crtc_vblank_get(&crtc->base)))
                 return false;
 
         local_irq_disable();
@@ -132,7 +132,7 @@ bool intel_pipe_update_start(struct intel_crtc *crtc, uint32_t *start_vbl_count)
 
         finish_wait(wq, &wait);
 
-        drm_vblank_put(dev, pipe);
+        drm_crtc_vblank_put(&crtc->base);
 
         *start_vbl_count = dev->driver->get_vblank_counter(dev, pipe);
 
@@ -189,7 +189,7 @@ skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc,
         struct intel_plane *intel_plane = to_intel_plane(drm_plane);
         const int pipe = intel_plane->pipe;
         const int plane = intel_plane->plane + 1;
-        u32 plane_ctl, stride;
+        u32 plane_ctl, stride_div;
         int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
 
         plane_ctl = I915_READ(PLANE_CTL(pipe, plane));
@@ -245,17 +245,22 @@ skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc,
                 BUG();
         }
 
-        switch (obj->tiling_mode) {
-        case I915_TILING_NONE:
-                stride = fb->pitches[0] >> 6;
+        switch (fb->modifier[0]) {
+        case DRM_FORMAT_MOD_NONE:
                 break;
-        case I915_TILING_X:
+        case I915_FORMAT_MOD_X_TILED:
                 plane_ctl |= PLANE_CTL_TILED_X;
-                stride = fb->pitches[0] >> 9;
+                break;
+        case I915_FORMAT_MOD_Y_TILED:
+                plane_ctl |= PLANE_CTL_TILED_Y;
+                break;
+        case I915_FORMAT_MOD_Yf_TILED:
+                plane_ctl |= PLANE_CTL_TILED_YF;
                 break;
         default:
-                BUG();
+                MISSING_CASE(fb->modifier[0]);
         }
+
         if (drm_plane->state->rotation == BIT(DRM_ROTATE_180))
                 plane_ctl |= PLANE_CTL_ROTATE_180;
 
@@ -266,6 +271,9 @@ skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc,
                                        pixel_size, true,
                                        src_w != crtc_w || src_h != crtc_h);
 
+        stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
+                                               fb->pixel_format);
+
         /* Sizes are 0 based */
         src_w--;
         src_h--;
@@ -273,7 +281,7 @@ skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc,
         crtc_h--;
 
         I915_WRITE(PLANE_OFFSET(pipe, plane), (y << 16) | x);
-        I915_WRITE(PLANE_STRIDE(pipe, plane), stride);
+        I915_WRITE(PLANE_STRIDE(pipe, plane), fb->pitches[0] / stride_div);
         I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x);
         I915_WRITE(PLANE_SIZE(pipe, plane), (crtc_h << 16) | crtc_w);
         I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl);
@@ -993,7 +1001,7 @@ intel_pre_disable_primary(struct drm_crtc *crtc)
         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 
         mutex_lock(&dev->struct_mutex);
-        if (dev_priv->fbc.plane == intel_crtc->plane)
+        if (dev_priv->fbc.crtc == intel_crtc)
                 intel_fbc_disable(dev);
         mutex_unlock(&dev->struct_mutex);
 
@@ -1076,7 +1084,6 @@ intel_check_sprite_plane(struct drm_plane *plane,
         struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
         struct intel_plane *intel_plane = to_intel_plane(plane);
         struct drm_framebuffer *fb = state->base.fb;
-        struct drm_i915_gem_object *obj = intel_fb_obj(fb);
         int crtc_x, crtc_y;
         unsigned int crtc_w, crtc_h;
         uint32_t src_x, src_y, src_w, src_h;
@@ -1106,16 +1113,6 @@ intel_check_sprite_plane(struct drm_plane *plane,
                 return -EINVAL;
         }
 
-        /* Sprite planes can be linear or x-tiled surfaces */
-        switch (obj->tiling_mode) {
-                case I915_TILING_NONE:
-                case I915_TILING_X:
-                        break;
-                default:
-                        DRM_DEBUG_KMS("Unsupported tiling mode\n");
-                        return -EINVAL;
-        }
-
         /*
          * FIXME the following code does a bunch of fuzzy adjustments to the
          * coordinates and sizes. We probably need some way to decide whether
@@ -1259,6 +1256,12 @@ finish:
 
                 if (!intel_crtc->primary_enabled && !state->hides_primary)
                         intel_crtc->atomic.post_enable_primary = true;
+
+                /* Update watermarks on tiling changes. */
+                if (!plane->state->fb || !state->base.fb ||
+                    plane->state->fb->modifier[0] !=
+                    state->base.fb->modifier[0])
+                        intel_crtc->atomic.update_wm = true;
         }
 
         return 0;
@@ -1312,9 +1315,6 @@ int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
         struct intel_plane *intel_plane;
         int ret = 0;
 
-        if (!drm_core_check_feature(dev, DRIVER_MODESET))
-                return -ENODEV;
-
         /* Make sure we don't try to enable both src & dest simultaneously */
         if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
                 return -EINVAL;
@@ -1343,9 +1343,6 @@ int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
         struct intel_plane *intel_plane;
         int ret = 0;
 
-        if (!drm_core_check_feature(dev, DRIVER_MODESET))
-                return -ENODEV;
-
         drm_modeset_lock_all(dev);
 
         plane = drm_plane_find(dev, get->plane_id);
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index c47a3baa53d5..8879f17770aa 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -23,6 +23,7 @@
 
 #include "i915_drv.h"
 #include "intel_drv.h"
+#include "i915_vgpu.h"
 
 #include <linux/pm_runtime.h>
 
@@ -210,6 +211,13 @@ static void fw_domains_put_with_fifo(struct drm_i915_private *dev_priv,
         gen6_gt_check_fifodbg(dev_priv);
 }
 
+static inline u32 fifo_free_entries(struct drm_i915_private *dev_priv)
+{
+        u32 count = __raw_i915_read32(dev_priv, GTFIFOCTL);
+
+        return count & GT_FIFO_FREE_ENTRIES_MASK;
+}
+
 static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
 {
         int ret = 0;
@@ -217,16 +225,15 @@ static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
         /* On VLV, FIFO will be shared by both SW and HW.
          * So, we need to read the FREE_ENTRIES everytime */
         if (IS_VALLEYVIEW(dev_priv->dev))
-                dev_priv->uncore.fifo_count =
-                        __raw_i915_read32(dev_priv, GTFIFOCTL) &
-                                                GT_FIFO_FREE_ENTRIES_MASK;
+                dev_priv->uncore.fifo_count = fifo_free_entries(dev_priv);
 
         if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
                 int loop = 500;
-                u32 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
+                u32 fifo = fifo_free_entries(dev_priv);
+
                 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
                         udelay(10);
-                        fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
+                        fifo = fifo_free_entries(dev_priv);
                 }
                 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
                         ++ret;
@@ -314,8 +321,7 @@ void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore)
 
                 if (IS_GEN6(dev) || IS_GEN7(dev))
                         dev_priv->uncore.fifo_count =
-                                __raw_i915_read32(dev_priv, GTFIFOCTL) &
-                                GT_FIFO_FREE_ENTRIES_MASK;
+                                fifo_free_entries(dev_priv);
         }
 
         if (!restore)
@@ -328,8 +334,9 @@ static void intel_uncore_ellc_detect(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
 
-        if ((IS_HASWELL(dev) || IS_BROADWELL(dev)) &&
-            (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) == 1)) {
+        if ((IS_HASWELL(dev) || IS_BROADWELL(dev) ||
+             INTEL_INFO(dev)->gen >= 9) &&
+            (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) & EDRAM_ENABLED)) {
                 /* The docs do not explain exactly how the calculation can be
                  * made. It is somewhat guessable, but for now, it's always
                  * 128MB.
@@ -640,6 +647,14 @@ static inline void __force_wake_get(struct drm_i915_private *dev_priv,
                 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
 }
 
+#define __vgpu_read(x) \
+static u##x \
+vgpu_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
+        GEN6_READ_HEADER(x); \
+        val = __raw_i915_read##x(dev_priv, reg); \
+        GEN6_READ_FOOTER; \
+}
+
 #define __gen6_read(x) \
 static u##x \
 gen6_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
@@ -703,6 +718,10 @@ gen9_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
         GEN6_READ_FOOTER; \
 }
 
+__vgpu_read(8)
+__vgpu_read(16)
+__vgpu_read(32)
+__vgpu_read(64)
 __gen9_read(8)
 __gen9_read(16)
 __gen9_read(32)
@@ -724,6 +743,7 @@ __gen6_read(64)
 #undef __chv_read
 #undef __vlv_read
 #undef __gen6_read
+#undef __vgpu_read
 #undef GEN6_READ_FOOTER
 #undef GEN6_READ_HEADER
 
@@ -807,6 +827,14 @@ hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace)
         GEN6_WRITE_FOOTER; \
 }
 
+#define __vgpu_write(x) \
+static void vgpu_write##x(struct drm_i915_private *dev_priv, \
+                          off_t reg, u##x val, bool trace) { \
+        GEN6_WRITE_HEADER; \
+        __raw_i915_write##x(dev_priv, reg, val); \
+        GEN6_WRITE_FOOTER; \
+}
+
 static const u32 gen8_shadowed_regs[] = {
         FORCEWAKE_MT,
         GEN6_RPNSWREQ,
@@ -924,12 +952,17 @@ __gen6_write(8)
 __gen6_write(16)
 __gen6_write(32)
 __gen6_write(64)
+__vgpu_write(8)
+__vgpu_write(16)
+__vgpu_write(32)
+__vgpu_write(64)
 
 #undef __gen9_write
 #undef __chv_write
 #undef __gen8_write
 #undef __hsw_write
 #undef __gen6_write
+#undef __vgpu_write
 #undef GEN6_WRITE_FOOTER
 #undef GEN6_WRITE_HEADER
 
@@ -972,6 +1005,7 @@ static void fw_domain_init(struct drm_i915_private *dev_priv,
                 d->val_set = FORCEWAKE_KERNEL;
                 d->val_clear = 0;
         } else {
+                /* WaRsClearFWBitsAtReset:bdw,skl */
                 d->val_reset = _MASKED_BIT_DISABLE(0xffff);
                 d->val_set = _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL);
                 d->val_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL);
@@ -1082,6 +1116,8 @@ void intel_uncore_init(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
 
+        i915_check_vgpu(dev);
+
         intel_uncore_ellc_detect(dev);
         intel_uncore_fw_domains_init(dev);
         __intel_uncore_early_sanitize(dev, false);
@@ -1130,6 +1166,11 @@ void intel_uncore_init(struct drm_device *dev)
                 break;
         }
 
+        if (intel_vgpu_active(dev)) {
+                ASSIGN_WRITE_MMIO_VFUNCS(vgpu);
+                ASSIGN_READ_MMIO_VFUNCS(vgpu);
+        }
+
         i915_check_and_clear_faults(dev);
 }
 #undef ASSIGN_WRITE_MMIO_VFUNCS
diff --git a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_plane.c b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_plane.c
index cde25009203a..dbc068988377 100644
--- a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_plane.c
+++ b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_plane.c
@@ -83,7 +83,8 @@ static const struct drm_plane_funcs mdp4_plane_funcs = {
 };
 
 static int mdp4_plane_prepare_fb(struct drm_plane *plane,
-                struct drm_framebuffer *fb)
+                struct drm_framebuffer *fb,
+                const struct drm_plane_state *new_state)
 {
         struct mdp4_plane *mdp4_plane = to_mdp4_plane(plane);
         struct mdp4_kms *mdp4_kms = get_kms(plane);
@@ -93,7 +94,8 @@ static int mdp4_plane_prepare_fb(struct drm_plane *plane,
 }
 
 static void mdp4_plane_cleanup_fb(struct drm_plane *plane,
-                struct drm_framebuffer *fb)
+                struct drm_framebuffer *fb,
+                const struct drm_plane_state *old_state)
 {
         struct mdp4_plane *mdp4_plane = to_mdp4_plane(plane);
         struct mdp4_kms *mdp4_kms = get_kms(plane);
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c
index 05cf9ab2a876..6bd48e246283 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c
@@ -156,7 +156,8 @@ static const struct drm_plane_funcs mdp5_plane_funcs = {
 };
 
 static int mdp5_plane_prepare_fb(struct drm_plane *plane,
-                struct drm_framebuffer *fb)
+                struct drm_framebuffer *fb,
+                const struct drm_plane_state *new_state)
 {
         struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
         struct mdp5_kms *mdp5_kms = get_kms(plane);
@@ -166,7 +167,8 @@ static int mdp5_plane_prepare_fb(struct drm_plane *plane,
 }
 
 static void mdp5_plane_cleanup_fb(struct drm_plane *plane,
-                struct drm_framebuffer *fb)
+                struct drm_framebuffer *fb,
+                const struct drm_plane_state *old_state)
 {
         struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
         struct mdp5_kms *mdp5_kms = get_kms(plane);
diff --git a/drivers/gpu/drm/msm/msm_atomic.c b/drivers/gpu/drm/msm/msm_atomic.c
index 18fd643b6e69..5b192128cda2 100644
--- a/drivers/gpu/drm/msm/msm_atomic.c
+++ b/drivers/gpu/drm/msm/msm_atomic.c
@@ -96,11 +96,11 @@ static void complete_commit(struct msm_commit *c)
 
         kms->funcs->prepare_commit(kms, state);
 
-        drm_atomic_helper_commit_pre_planes(dev, state);
+        drm_atomic_helper_commit_modeset_disables(dev, state);
 
         drm_atomic_helper_commit_planes(dev, state);
 
-        drm_atomic_helper_commit_post_planes(dev, state);
+        drm_atomic_helper_commit_modeset_enables(dev, state);
 
         /* NOTE: _wait_for_vblanks() only waits for vblank on
          * enabled CRTCs.  So we end up faulting when disabling
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
index 25c7a998fc2c..9e72133bb64b 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
@@ -15,6 +15,8 @@
 #include <linux/mutex.h>
 
 #include <drm/drmP.h>
+#include <drm/drm_atomic.h>
+#include <drm/drm_atomic_helper.h>
 #include <drm/drm_crtc.h>
 #include <drm/drm_crtc_helper.h>
 #include <drm/drm_fb_cma_helper.h>
@@ -99,9 +101,13 @@ static void rcar_du_crtc_put(struct rcar_du_crtc *rcrtc)
         clk_disable_unprepare(rcrtc->clock);
 }
 
+/* -----------------------------------------------------------------------------
+ * Hardware Setup
+ */
+
 static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
 {
-        const struct drm_display_mode *mode = &rcrtc->crtc.mode;
+        const struct drm_display_mode *mode = &rcrtc->crtc.state->adjusted_mode;
         unsigned long mode_clock = mode->clock * 1000;
         unsigned long clk;
         u32 value;
@@ -187,9 +193,19 @@ void rcar_du_crtc_route_output(struct drm_crtc *crtc,
                 rcdu->dpad0_source = rcrtc->index;
 }
 
-void rcar_du_crtc_update_planes(struct drm_crtc *crtc)
+static unsigned int plane_zpos(struct rcar_du_plane *plane)
+{
+        return to_rcar_du_plane_state(plane->plane.state)->zpos;
+}
+
+static const struct rcar_du_format_info *
+plane_format(struct rcar_du_plane *plane)
+{
+        return to_rcar_du_plane_state(plane->plane.state)->format;
+}
+
+static void rcar_du_crtc_update_planes(struct rcar_du_crtc *rcrtc)
 {
-        struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
         struct rcar_du_plane *planes[RCAR_DU_NUM_HW_PLANES];
         unsigned int num_planes = 0;
         unsigned int prio = 0;
@@ -201,29 +217,30 @@ void rcar_du_crtc_update_planes(struct drm_crtc *crtc)
                 struct rcar_du_plane *plane = &rcrtc->group->planes.planes[i];
                 unsigned int j;
 
-                if (plane->crtc != &rcrtc->crtc || !plane->enabled)
+                if (plane->plane.state->crtc != &rcrtc->crtc)
                         continue;
 
                 /* Insert the plane in the sorted planes array. */
                 for (j = num_planes++; j > 0; --j) {
-                        if (planes[j-1]->zpos <= plane->zpos)
+                        if (plane_zpos(planes[j-1]) <= plane_zpos(plane))
                                 break;
                         planes[j] = planes[j-1];
                 }
 
                 planes[j] = plane;
-                prio += plane->format->planes * 4;
+                prio += plane_format(plane)->planes * 4;
         }
 
         for (i = 0; i < num_planes; ++i) {
                 struct rcar_du_plane *plane = planes[i];
-                unsigned int index = plane->hwindex;
+                struct drm_plane_state *state = plane->plane.state;
+                unsigned int index = to_rcar_du_plane_state(state)->hwindex;
 
                 prio -= 4;
                 dspr |= (index + 1) << prio;
                 dptsr |= DPTSR_PnDK(index) |  DPTSR_PnTS(index);
 
-                if (plane->format->planes == 2) {
+                if (plane_format(plane)->planes == 2) {
                         index = (index + 1) % 8;
 
                         prio -= 4;
@@ -236,8 +253,6 @@ void rcar_du_crtc_update_planes(struct drm_crtc *crtc)
          * with superposition controller 2.
          */
         if (rcrtc->index % 2) {
-                u32 value = rcar_du_group_read(rcrtc->group, DPTSR);
-
                 /* The DPTSR register is updated when the display controller is
                  * stopped. We thus need to restart the DU. Once again, sorry
                  * for the flicker. One way to mitigate the issue would be to
@@ -245,29 +260,104 @@ void rcar_du_crtc_update_planes(struct drm_crtc *crtc)
                  * split, or through a module parameter). Flicker would then
                  * occur only if we need to break the pre-association.
                  */
-                if (value != dptsr) {
+                mutex_lock(&rcrtc->group->lock);
+                if (rcar_du_group_read(rcrtc->group, DPTSR) != dptsr) {
                         rcar_du_group_write(rcrtc->group, DPTSR, dptsr);
                         if (rcrtc->group->used_crtcs)
                                 rcar_du_group_restart(rcrtc->group);
                 }
+                mutex_unlock(&rcrtc->group->lock);
         }
 
         rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR,
                             dspr);
 }
 
+/* -----------------------------------------------------------------------------
+ * Page Flip
+ */
+
+void rcar_du_crtc_cancel_page_flip(struct rcar_du_crtc *rcrtc,
+                                   struct drm_file *file)
+{
+        struct drm_pending_vblank_event *event;
+        struct drm_device *dev = rcrtc->crtc.dev;
+        unsigned long flags;
+
+        /* Destroy the pending vertical blanking event associated with the
+         * pending page flip, if any, and disable vertical blanking interrupts.
+         */
+        spin_lock_irqsave(&dev->event_lock, flags);
+        event = rcrtc->event;
+        if (event && event->base.file_priv == file) {
+                rcrtc->event = NULL;
+                event->base.destroy(&event->base);
+                drm_crtc_vblank_put(&rcrtc->crtc);
+        }
+        spin_unlock_irqrestore(&dev->event_lock, flags);
+}
+
+static void rcar_du_crtc_finish_page_flip(struct rcar_du_crtc *rcrtc)
+{
+        struct drm_pending_vblank_event *event;
+        struct drm_device *dev = rcrtc->crtc.dev;
+        unsigned long flags;
+
+        spin_lock_irqsave(&dev->event_lock, flags);
+        event = rcrtc->event;
+        rcrtc->event = NULL;
+        spin_unlock_irqrestore(&dev->event_lock, flags);
+
+        if (event == NULL)
+                return;
+
+        spin_lock_irqsave(&dev->event_lock, flags);
+        drm_send_vblank_event(dev, rcrtc->index, event);
+        wake_up(&rcrtc->flip_wait);
+        spin_unlock_irqrestore(&dev->event_lock, flags);
+
+        drm_crtc_vblank_put(&rcrtc->crtc);
+}
+
+static bool rcar_du_crtc_page_flip_pending(struct rcar_du_crtc *rcrtc)
+{
+        struct drm_device *dev = rcrtc->crtc.dev;
+        unsigned long flags;
+        bool pending;
+
+        spin_lock_irqsave(&dev->event_lock, flags);
+        pending = rcrtc->event != NULL;
+        spin_unlock_irqrestore(&dev->event_lock, flags);
+
+        return pending;
+}
+
+static void rcar_du_crtc_wait_page_flip(struct rcar_du_crtc *rcrtc)
+{
+        struct rcar_du_device *rcdu = rcrtc->group->dev;
+
+        if (wait_event_timeout(rcrtc->flip_wait,
+                               !rcar_du_crtc_page_flip_pending(rcrtc),
+                               msecs_to_jiffies(50)))
+                return;
+
+        dev_warn(rcdu->dev, "page flip timeout\n");
+
+        rcar_du_crtc_finish_page_flip(rcrtc);
+}
+
+/* -----------------------------------------------------------------------------
+ * Start/Stop and Suspend/Resume
+ */
+
 static void rcar_du_crtc_start(struct rcar_du_crtc *rcrtc)
 {
         struct drm_crtc *crtc = &rcrtc->crtc;
         bool interlaced;
-        unsigned int i;
 
         if (rcrtc->started)
                 return;
 
-        if (WARN_ON(rcrtc->plane->format == NULL))
-                return;
-
         /* Set display off and background to black */
         rcar_du_crtc_write(rcrtc, DOOR, DOOR_RGB(0, 0, 0));
         rcar_du_crtc_write(rcrtc, BPOR, BPOR_RGB(0, 0, 0));
@@ -276,20 +366,8 @@ static void rcar_du_crtc_start(struct rcar_du_crtc *rcrtc)
         rcar_du_crtc_set_display_timing(rcrtc);
         rcar_du_group_set_routing(rcrtc->group);
 
-        mutex_lock(&rcrtc->group->planes.lock);
-        rcrtc->plane->enabled = true;
-        rcar_du_crtc_update_planes(crtc);
-        mutex_unlock(&rcrtc->group->planes.lock);
-
-        /* Setup planes. */
-        for (i = 0; i < ARRAY_SIZE(rcrtc->group->planes.planes); ++i) {
-                struct rcar_du_plane *plane = &rcrtc->group->planes.planes[i];
-
-                if (plane->crtc != crtc || !plane->enabled)
-                        continue;
-
-                rcar_du_plane_setup(plane);
-        }
+        /* Start with all planes disabled. */
+        rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR, 0);
 
         /* Select master sync mode. This enables display operation in master
          * sync mode (with the HSYNC and VSYNC signals configured as outputs and
@@ -302,6 +380,9 @@ static void rcar_du_crtc_start(struct rcar_du_crtc *rcrtc)
 
         rcar_du_group_start_stop(rcrtc->group, true);
 
+        /* Turn vertical blanking interrupt reporting back on. */
+        drm_crtc_vblank_on(crtc);
+
         rcrtc->started = true;
 }
 
@@ -312,10 +393,12 @@ static void rcar_du_crtc_stop(struct rcar_du_crtc *rcrtc)
         if (!rcrtc->started)
                 return;
 
-        mutex_lock(&rcrtc->group->planes.lock);
-        rcrtc->plane->enabled = false;
-        rcar_du_crtc_update_planes(crtc);
-        mutex_unlock(&rcrtc->group->planes.lock);
+        /* Disable vertical blanking interrupt reporting. We first need to wait
+         * for page flip completion before stopping the CRTC as userspace
+         * expects page flips to eventually complete.
+         */
+        rcar_du_crtc_wait_page_flip(rcrtc);
+        drm_crtc_vblank_off(crtc);
 
         /* Select switch sync mode. This stops display operation and configures
          * the HSYNC and VSYNC signals as inputs.
@@ -335,196 +418,111 @@ void rcar_du_crtc_suspend(struct rcar_du_crtc *rcrtc)
 
 void rcar_du_crtc_resume(struct rcar_du_crtc *rcrtc)
 {
-        if (rcrtc->dpms != DRM_MODE_DPMS_ON)
+        unsigned int i;
+
+        if (!rcrtc->enabled)
                 return;
 
         rcar_du_crtc_get(rcrtc);
         rcar_du_crtc_start(rcrtc);
-}
-
-static void rcar_du_crtc_update_base(struct rcar_du_crtc *rcrtc)
-{
-        struct drm_crtc *crtc = &rcrtc->crtc;
-
-        rcar_du_plane_compute_base(rcrtc->plane, crtc->primary->fb);
-        rcar_du_plane_update_base(rcrtc->plane);
-}
-
-static void rcar_du_crtc_dpms(struct drm_crtc *crtc, int mode)
-{
-        struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 
-        if (mode != DRM_MODE_DPMS_ON)
-                mode = DRM_MODE_DPMS_OFF;
+        /* Commit the planes state. */
+        for (i = 0; i < ARRAY_SIZE(rcrtc->group->planes.planes); ++i) {
+                struct rcar_du_plane *plane = &rcrtc->group->planes.planes[i];
 
-        if (rcrtc->dpms == mode)
-                return;
+                if (plane->plane.state->crtc != &rcrtc->crtc)
+                        continue;
 
-        if (mode == DRM_MODE_DPMS_ON) {
-                rcar_du_crtc_get(rcrtc);
-                rcar_du_crtc_start(rcrtc);
-        } else {
-                rcar_du_crtc_stop(rcrtc);
-                rcar_du_crtc_put(rcrtc);
+                rcar_du_plane_setup(plane);
         }
 
-        rcrtc->dpms = mode;
+        rcar_du_crtc_update_planes(rcrtc);
 }
 
-static bool rcar_du_crtc_mode_fixup(struct drm_crtc *crtc,
-                                    const struct drm_display_mode *mode,
-                                    struct drm_display_mode *adjusted_mode)
-{
-        /* TODO Fixup modes */
-        return true;
-}
+/* -----------------------------------------------------------------------------
+ * CRTC Functions
+ */
 
-static void rcar_du_crtc_mode_prepare(struct drm_crtc *crtc)
+static void rcar_du_crtc_enable(struct drm_crtc *crtc)
 {
         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 
-        /* We need to access the hardware during mode set, acquire a reference
-         * to the CRTC.
-         */
-        rcar_du_crtc_get(rcrtc);
+        if (rcrtc->enabled)
+                return;
 
-        /* Stop the CRTC and release the plane. Force the DPMS mode to off as a
-         * result.
-         */
-        rcar_du_crtc_stop(rcrtc);
-        rcar_du_plane_release(rcrtc->plane);
+        rcar_du_crtc_get(rcrtc);
+        rcar_du_crtc_start(rcrtc);
 
-        rcrtc->dpms = DRM_MODE_DPMS_OFF;
+        rcrtc->enabled = true;
 }
 
-static int rcar_du_crtc_mode_set(struct drm_crtc *crtc,
-                                 struct drm_display_mode *mode,
-                                 struct drm_display_mode *adjusted_mode,
-                                 int x, int y,
-                                 struct drm_framebuffer *old_fb)
+static void rcar_du_crtc_disable(struct drm_crtc *crtc)
 {
         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
-        struct rcar_du_device *rcdu = rcrtc->group->dev;
-        const struct rcar_du_format_info *format;
-        int ret;
-
-        format = rcar_du_format_info(crtc->primary->fb->pixel_format);
-        if (format == NULL) {
-                dev_dbg(rcdu->dev, "mode_set: unsupported format %08x\n",
-                        crtc->primary->fb->pixel_format);
-                ret = -EINVAL;
-                goto error;
-        }
 
-        ret = rcar_du_plane_reserve(rcrtc->plane, format);
-        if (ret < 0)
-                goto error;
-
-        rcrtc->plane->format = format;
-
-        rcrtc->plane->src_x = x;
-        rcrtc->plane->src_y = y;
-        rcrtc->plane->width = mode->hdisplay;
-        rcrtc->plane->height = mode->vdisplay;
+        if (!rcrtc->enabled)
+                return;
 
-        rcar_du_plane_compute_base(rcrtc->plane, crtc->primary->fb);
+        rcar_du_crtc_stop(rcrtc);
+        rcar_du_crtc_put(rcrtc);
 
+        rcrtc->enabled = false;
         rcrtc->outputs = 0;
-
-        return 0;
-
-error:
-        /* There's no rollback/abort operation to clean up in case of error. We
-         * thus need to release the reference to the CRTC acquired in prepare()
-         * here.
-         */
-        rcar_du_crtc_put(rcrtc);
-        return ret;
 }
 
-static void rcar_du_crtc_mode_commit(struct drm_crtc *crtc)
+static bool rcar_du_crtc_mode_fixup(struct drm_crtc *crtc,
+                                    const struct drm_display_mode *mode,
+                                    struct drm_display_mode *adjusted_mode)
 {
-        struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
-
-        /* We're done, restart the CRTC and set the DPMS mode to on. The
-         * reference to the DU acquired at prepare() time will thus be released
-         * by the DPMS handler (possibly called by the disable() handler).
-         */
-        rcar_du_crtc_start(rcrtc);
-        rcrtc->dpms = DRM_MODE_DPMS_ON;
+        /* TODO Fixup modes */
+        return true;
 }
 
-static int rcar_du_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
-                                      struct drm_framebuffer *old_fb)
+static void rcar_du_crtc_atomic_begin(struct drm_crtc *crtc)
 {
+        struct drm_pending_vblank_event *event = crtc->state->event;
         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
+        struct drm_device *dev = rcrtc->crtc.dev;
+        unsigned long flags;
 
-        rcrtc->plane->src_x = x;
-        rcrtc->plane->src_y = y;
+        if (event) {
+                event->pipe = rcrtc->index;
 
-        rcar_du_crtc_update_base(rcrtc);
+                WARN_ON(drm_crtc_vblank_get(crtc) != 0);
 
-        return 0;
+                spin_lock_irqsave(&dev->event_lock, flags);
+                rcrtc->event = event;
+                spin_unlock_irqrestore(&dev->event_lock, flags);
+        }
 }
 
-static void rcar_du_crtc_disable(struct drm_crtc *crtc)
+static void rcar_du_crtc_atomic_flush(struct drm_crtc *crtc)
 {
         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 
-        rcar_du_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
-        rcar_du_plane_release(rcrtc->plane);
+        rcar_du_crtc_update_planes(rcrtc);
 }
 
 static const struct drm_crtc_helper_funcs crtc_helper_funcs = {
-        .dpms = rcar_du_crtc_dpms,
         .mode_fixup = rcar_du_crtc_mode_fixup,
-        .prepare = rcar_du_crtc_mode_prepare,
-        .commit = rcar_du_crtc_mode_commit,
-        .mode_set = rcar_du_crtc_mode_set,
-        .mode_set_base = rcar_du_crtc_mode_set_base,
         .disable = rcar_du_crtc_disable,
+        .enable = rcar_du_crtc_enable,
+        .atomic_begin = rcar_du_crtc_atomic_begin,
+        .atomic_flush = rcar_du_crtc_atomic_flush,
 };
 
-void rcar_du_crtc_cancel_page_flip(struct rcar_du_crtc *rcrtc,
-                                   struct drm_file *file)
-{
-        struct drm_pending_vblank_event *event;
-        struct drm_device *dev = rcrtc->crtc.dev;
-        unsigned long flags;
-
-        /* Destroy the pending vertical blanking event associated with the
-         * pending page flip, if any, and disable vertical blanking interrupts.
-         */
-        spin_lock_irqsave(&dev->event_lock, flags);
-        event = rcrtc->event;
-        if (event && event->base.file_priv == file) {
-                rcrtc->event = NULL;
-                event->base.destroy(&event->base);
-                drm_vblank_put(dev, rcrtc->index);
-        }
-        spin_unlock_irqrestore(&dev->event_lock, flags);
-}
-
-static void rcar_du_crtc_finish_page_flip(struct rcar_du_crtc *rcrtc)
-{
-        struct drm_pending_vblank_event *event;
-        struct drm_device *dev = rcrtc->crtc.dev;
-        unsigned long flags;
-
-        spin_lock_irqsave(&dev->event_lock, flags);
-        event = rcrtc->event;
-        rcrtc->event = NULL;
-        spin_unlock_irqrestore(&dev->event_lock, flags);
-
-        if (event == NULL)
-                return;
-
-        spin_lock_irqsave(&dev->event_lock, flags);
-        drm_send_vblank_event(dev, rcrtc->index, event);
-        spin_unlock_irqrestore(&dev->event_lock, flags);
+static const struct drm_crtc_funcs crtc_funcs = {
+        .reset = drm_atomic_helper_crtc_reset,
+        .destroy = drm_crtc_cleanup,
+        .set_config = drm_atomic_helper_set_config,
+        .page_flip = drm_atomic_helper_page_flip,
+        .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
+        .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
+};
 
-        drm_vblank_put(dev, rcrtc->index);
-}
+/* -----------------------------------------------------------------------------
+ * Interrupt Handling
+ */
 
 static irqreturn_t rcar_du_crtc_irq(int irq, void *arg)
 {
@@ -544,41 +542,9 @@ static irqreturn_t rcar_du_crtc_irq(int irq, void *arg)
         return ret;
 }
 
-static int rcar_du_crtc_page_flip(struct drm_crtc *crtc,
-                                  struct drm_framebuffer *fb,
-                                  struct drm_pending_vblank_event *event,
-                                  uint32_t page_flip_flags)
-{
-        struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
-        struct drm_device *dev = rcrtc->crtc.dev;
-        unsigned long flags;
-
-        spin_lock_irqsave(&dev->event_lock, flags);
-        if (rcrtc->event != NULL) {
-                spin_unlock_irqrestore(&dev->event_lock, flags);
-                return -EBUSY;
-        }
-        spin_unlock_irqrestore(&dev->event_lock, flags);
-
-        crtc->primary->fb = fb;
-        rcar_du_crtc_update_base(rcrtc);
-
-        if (event) {
-                event->pipe = rcrtc->index;
-                drm_vblank_get(dev, rcrtc->index);
-                spin_lock_irqsave(&dev->event_lock, flags);
-                rcrtc->event = event;
-                spin_unlock_irqrestore(&dev->event_lock, flags);
-        }
-
-        return 0;
-}
-
-static const struct drm_crtc_funcs crtc_funcs = {
-        .destroy = drm_crtc_cleanup,
-        .set_config = drm_crtc_helper_set_config,
-        .page_flip = rcar_du_crtc_page_flip,
-};
+/* -----------------------------------------------------------------------------
+ * Initialization
+ */
 
 int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int index)
 {
@@ -620,20 +586,24 @@ int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int index)
                 return -EPROBE_DEFER;
         }
 
+        init_waitqueue_head(&rcrtc->flip_wait);
+
         rcrtc->group = rgrp;
         rcrtc->mmio_offset = mmio_offsets[index];
         rcrtc->index = index;
-        rcrtc->dpms = DRM_MODE_DPMS_OFF;
-        rcrtc->plane = &rgrp->planes.planes[index % 2];
-
-        rcrtc->plane->crtc = crtc;
+        rcrtc->enabled = false;
 
-        ret = drm_crtc_init(rcdu->ddev, crtc, &crtc_funcs);
+        ret = drm_crtc_init_with_planes(rcdu->ddev, crtc,
+                                        &rgrp->planes.planes[index % 2].plane,
+                                        NULL, &crtc_funcs);
         if (ret < 0)
                 return ret;
 
         drm_crtc_helper_add(crtc, &crtc_helper_funcs);
 
+        /* Start with vertical blanking interrupt reporting disabled. */
+        drm_crtc_vblank_off(crtc);
+
         /* Register the interrupt handler. */
         if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) {
                 irq = platform_get_irq(pdev, index);
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.h b/drivers/gpu/drm/rcar-du/rcar_du_crtc.h
index d2f89f7d2e5e..5d9aa9b33769 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.h
+++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.h
@@ -15,12 +15,12 @@
 #define __RCAR_DU_CRTC_H__
 
 #include <linux/mutex.h>
+#include <linux/wait.h>
 
 #include <drm/drmP.h>
 #include <drm/drm_crtc.h>
 
 struct rcar_du_group;
-struct rcar_du_plane;
 
 struct rcar_du_crtc {
         struct drm_crtc crtc;
@@ -32,11 +32,12 @@ struct rcar_du_crtc {
         bool started;
 
         struct drm_pending_vblank_event *event;
+        wait_queue_head_t flip_wait;
+
         unsigned int outputs;
-        int dpms;
+        bool enabled;
 
         struct rcar_du_group *group;
-        struct rcar_du_plane *plane;
 };
 
 #define to_rcar_crtc(c) container_of(c, struct rcar_du_crtc, crtc)
@@ -59,6 +60,5 @@ void rcar_du_crtc_resume(struct rcar_du_crtc *rcrtc);
 
 void rcar_du_crtc_route_output(struct drm_crtc *crtc,
                                enum rcar_du_output output);
-void rcar_du_crtc_update_planes(struct drm_crtc *crtc);
 
 #endif /* __RCAR_DU_CRTC_H__ */
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
index e0d74f821416..1d9e4f8568ae 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
@@ -19,6 +19,7 @@
 #include <linux/platform_device.h>
 #include <linux/pm.h>
 #include <linux/slab.h>
+#include <linux/wait.h>
 
 #include <drm/drmP.h>
 #include <drm/drm_crtc_helper.h>
@@ -163,6 +164,8 @@ static int rcar_du_load(struct drm_device *dev, unsigned long flags)
                 return -ENOMEM;
         }
 
+        init_waitqueue_head(&rcdu->commit.wait);
+
         rcdu->dev = &pdev->dev;
         rcdu->info = np ? of_match_device(rcar_du_of_table, rcdu->dev)->data
                    : (void *)platform_get_device_id(pdev)->driver_data;
@@ -175,17 +178,19 @@ static int rcar_du_load(struct drm_device *dev, unsigned long flags)
         if (IS_ERR(rcdu->mmio))
                 return PTR_ERR(rcdu->mmio);
 
-        /* DRM/KMS objects */
-        ret = rcar_du_modeset_init(rcdu);
+        /* Initialize vertical blanking interrupts handling. Start with vblank
+         * disabled for all CRTCs.
+         */
+        ret = drm_vblank_init(dev, (1 << rcdu->info->num_crtcs) - 1);
         if (ret < 0) {
-                dev_err(&pdev->dev, "failed to initialize DRM/KMS\n");
+                dev_err(&pdev->dev, "failed to initialize vblank\n");
                 goto done;
         }
 
-        /* vblank handling */
-        ret = drm_vblank_init(dev, (1 << rcdu->num_crtcs) - 1);
+        /* DRM/KMS objects */
+        ret = rcar_du_modeset_init(rcdu);
         if (ret < 0) {
-                dev_err(&pdev->dev, "failed to initialize vblank\n");
+                dev_err(&pdev->dev, "failed to initialize DRM/KMS\n");
                 goto done;
         }
 
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.h b/drivers/gpu/drm/rcar-du/rcar_du_drv.h
index c5b9ea6a7eaa..c7c538dd2e68 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_drv.h
+++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.h
@@ -15,6 +15,7 @@
 #define __RCAR_DU_DRV_H__
 
 #include <linux/kernel.h>
+#include <linux/wait.h>
 
 #include "rcar_du_crtc.h"
 #include "rcar_du_group.h"
@@ -64,6 +65,10 @@ struct rcar_du_device_info {
         unsigned int num_lvds;
 };
 
+#define RCAR_DU_MAX_CRTCS               3
+#define RCAR_DU_MAX_GROUPS              DIV_ROUND_UP(RCAR_DU_MAX_CRTCS, 2)
+#define RCAR_DU_MAX_LVDS                2
+
 struct rcar_du_device {
         struct device *dev;
         const struct rcar_du_device_info *info;
@@ -73,13 +78,18 @@ struct rcar_du_device {
         struct drm_device *ddev;
         struct drm_fbdev_cma *fbdev;
 
-        struct rcar_du_crtc crtcs[3];
+        struct rcar_du_crtc crtcs[RCAR_DU_MAX_CRTCS];
         unsigned int num_crtcs;
 
-        struct rcar_du_group groups[2];
+        struct rcar_du_group groups[RCAR_DU_MAX_GROUPS];
 
         unsigned int dpad0_source;
-        struct rcar_du_lvdsenc *lvds[2];
+        struct rcar_du_lvdsenc *lvds[RCAR_DU_MAX_LVDS];
+
+        struct {
+                wait_queue_head_t wait;
+                u32 pending;
+        } commit;
 };
 
 static inline bool rcar_du_has(struct rcar_du_device *rcdu,
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_encoder.c b/drivers/gpu/drm/rcar-du/rcar_du_encoder.c
index 279167f783f6..d0ae1e8009c6 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_encoder.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_encoder.c
@@ -42,46 +42,40 @@ rcar_du_connector_best_encoder(struct drm_connector *connector)
  * Encoder
  */
 
-static void rcar_du_encoder_dpms(struct drm_encoder *encoder, int mode)
+static void rcar_du_encoder_disable(struct drm_encoder *encoder)
 {
         struct rcar_du_encoder *renc = to_rcar_encoder(encoder);
 
-        if (mode != DRM_MODE_DPMS_ON)
-                mode = DRM_MODE_DPMS_OFF;
+        if (renc->lvds)
+                rcar_du_lvdsenc_enable(renc->lvds, encoder->crtc, false);
+}
+
+static void rcar_du_encoder_enable(struct drm_encoder *encoder)
+{
+        struct rcar_du_encoder *renc = to_rcar_encoder(encoder);
 
         if (renc->lvds)
-                rcar_du_lvdsenc_dpms(renc->lvds, encoder->crtc, mode);
+                rcar_du_lvdsenc_enable(renc->lvds, encoder->crtc, true);
 }
 
-static bool rcar_du_encoder_mode_fixup(struct drm_encoder *encoder,
-                                       const struct drm_display_mode *mode,
-                                       struct drm_display_mode *adjusted_mode)
+static int rcar_du_encoder_atomic_check(struct drm_encoder *encoder,
+                                        struct drm_crtc_state *crtc_state,
+                                        struct drm_connector_state *conn_state)
 {
         struct rcar_du_encoder *renc = to_rcar_encoder(encoder);
+        struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
+        const struct drm_display_mode *mode = &crtc_state->mode;
         const struct drm_display_mode *panel_mode;
+        struct drm_connector *connector = conn_state->connector;
         struct drm_device *dev = encoder->dev;
-        struct drm_connector *connector;
-        bool found = false;
 
         /* DAC encoders have currently no restriction on the mode. */
         if (encoder->encoder_type == DRM_MODE_ENCODER_DAC)
-                return true;
-
-        list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
-                if (connector->encoder == encoder) {
-                        found = true;
-                        break;
-                }
-        }
-
-        if (!found) {
-                dev_dbg(dev->dev, "mode_fixup: no connector found\n");
-                return false;
-        }
+                return 0;
 
         if (list_empty(&connector->modes)) {
-                dev_dbg(dev->dev, "mode_fixup: empty modes list\n");
-                return false;
+                dev_dbg(dev->dev, "encoder: empty modes list\n");
+                return -EINVAL;
         }
 
         panel_mode = list_first_entry(&connector->modes,
@@ -90,7 +84,7 @@ static bool rcar_du_encoder_mode_fixup(struct drm_encoder *encoder,
         /* We're not allowed to modify the resolution. */
         if (mode->hdisplay != panel_mode->hdisplay ||
             mode->vdisplay != panel_mode->vdisplay)
-                return false;
+                return -EINVAL;
 
         /* The flat panel mode is fixed, just copy it to the adjusted mode. */
         drm_mode_copy(adjusted_mode, panel_mode);
@@ -102,25 +96,7 @@ static bool rcar_du_encoder_mode_fixup(struct drm_encoder *encoder,
                 adjusted_mode->clock = clamp(adjusted_mode->clock,
                                              30000, 150000);
 
-        return true;
-}
-
-static void rcar_du_encoder_mode_prepare(struct drm_encoder *encoder)
-{
-        struct rcar_du_encoder *renc = to_rcar_encoder(encoder);
-
-        if (renc->lvds)
-                rcar_du_lvdsenc_dpms(renc->lvds, encoder->crtc,
-                                     DRM_MODE_DPMS_OFF);
-}
-
-static void rcar_du_encoder_mode_commit(struct drm_encoder *encoder)
-{
-        struct rcar_du_encoder *renc = to_rcar_encoder(encoder);
-
-        if (renc->lvds)
-                rcar_du_lvdsenc_dpms(renc->lvds, encoder->crtc,
-                                     DRM_MODE_DPMS_ON);
+        return 0;
 }
 
 static void rcar_du_encoder_mode_set(struct drm_encoder *encoder,
@@ -133,11 +109,10 @@ static void rcar_du_encoder_mode_set(struct drm_encoder *encoder,
 }
 
 static const struct drm_encoder_helper_funcs encoder_helper_funcs = {
-        .dpms = rcar_du_encoder_dpms,
-        .mode_fixup = rcar_du_encoder_mode_fixup,
-        .prepare = rcar_du_encoder_mode_prepare,
-        .commit = rcar_du_encoder_mode_commit,
         .mode_set = rcar_du_encoder_mode_set,
+        .disable = rcar_du_encoder_disable,
+        .enable = rcar_du_encoder_enable,
+        .atomic_check = rcar_du_encoder_atomic_check,
 };
 
 static const struct drm_encoder_funcs encoder_funcs = {
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.h b/drivers/gpu/drm/rcar-du/rcar_du_group.h
index 0c38cdcda4ca..ed36433fbe84 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_group.h
+++ b/drivers/gpu/drm/rcar-du/rcar_du_group.h
@@ -14,6 +14,8 @@
 #ifndef __RCAR_DU_GROUP_H__
 #define __RCAR_DU_GROUP_H__
 
+#include <linux/mutex.h>
+
 #include "rcar_du_plane.h"
 
 struct rcar_du_device;
@@ -25,6 +27,7 @@ struct rcar_du_device;
  * @index: group index
  * @use_count: number of users of the group (rcar_du_group_(get|put))
  * @used_crtcs: number of CRTCs currently in use
+ * @lock: protects the DPTSR register
  * @planes: planes handled by the group
  */
 struct rcar_du_group {
@@ -35,6 +38,8 @@ struct rcar_du_group {
         unsigned int use_count;
         unsigned int used_crtcs;
 
+        struct mutex lock;
+
         struct rcar_du_planes planes;
 };
 
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_hdmicon.c b/drivers/gpu/drm/rcar-du/rcar_du_hdmicon.c
index ca94b029ac80..96f2eb43713c 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_hdmicon.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_hdmicon.c
@@ -12,6 +12,7 @@
  */
 
 #include <drm/drmP.h>
+#include <drm/drm_atomic_helper.h>
 #include <drm/drm_crtc.h>
 #include <drm/drm_crtc_helper.h>
 #include <drm/drm_encoder_slave.h>
@@ -74,10 +75,13 @@ rcar_du_hdmi_connector_detect(struct drm_connector *connector, bool force)
 }
 
 static const struct drm_connector_funcs connector_funcs = {
-        .dpms = drm_helper_connector_dpms,
+        .dpms = drm_atomic_helper_connector_dpms,
+        .reset = drm_atomic_helper_connector_reset,
         .detect = rcar_du_hdmi_connector_detect,
         .fill_modes = drm_helper_probe_single_connector_modes,
         .destroy = rcar_du_hdmi_connector_destroy,
+        .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
+        .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 };
 
 int rcar_du_hdmi_connector_init(struct rcar_du_device *rcdu,
@@ -108,7 +112,7 @@ int rcar_du_hdmi_connector_init(struct rcar_du_device *rcdu,
         if (ret < 0)
                 return ret;
 
-        drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
+        connector->dpms = DRM_MODE_DPMS_OFF;
         drm_object_property_set_value(&connector->base,
                 rcdu->ddev->mode_config.dpms_property, DRM_MODE_DPMS_OFF);
 
@@ -116,7 +120,6 @@ int rcar_du_hdmi_connector_init(struct rcar_du_device *rcdu,
         if (ret < 0)
                 return ret;
 
-        connector->encoder = encoder;
         rcon->encoder = renc;
 
         return 0;
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_hdmienc.c b/drivers/gpu/drm/rcar-du/rcar_du_hdmienc.c
index 221f0a17fd6a..81da8419282b 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_hdmienc.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_hdmienc.c
@@ -26,41 +26,50 @@
 struct rcar_du_hdmienc {
         struct rcar_du_encoder *renc;
         struct device *dev;
-        int dpms;
+        bool enabled;
 };
 
 #define to_rcar_hdmienc(e)      (to_rcar_encoder(e)->hdmi)
 #define to_slave_funcs(e)       (to_rcar_encoder(e)->slave.slave_funcs)
 
-static void rcar_du_hdmienc_dpms(struct drm_encoder *encoder, int mode)
+static void rcar_du_hdmienc_disable(struct drm_encoder *encoder)
 {
         struct rcar_du_hdmienc *hdmienc = to_rcar_hdmienc(encoder);
         struct drm_encoder_slave_funcs *sfuncs = to_slave_funcs(encoder);
 
-        if (mode != DRM_MODE_DPMS_ON)
-                mode = DRM_MODE_DPMS_OFF;
+        if (sfuncs->dpms)
+                sfuncs->dpms(encoder, DRM_MODE_DPMS_OFF);
 
-        if (hdmienc->dpms == mode)
-                return;
+        if (hdmienc->renc->lvds)
+                rcar_du_lvdsenc_enable(hdmienc->renc->lvds, encoder->crtc,
+                                       false);
 
-        if (mode == DRM_MODE_DPMS_ON && hdmienc->renc->lvds)
-                rcar_du_lvdsenc_dpms(hdmienc->renc->lvds, encoder->crtc, mode);
+        hdmienc->enabled = false;
+}
 
-        if (sfuncs->dpms)
-                sfuncs->dpms(encoder, mode);
+static void rcar_du_hdmienc_enable(struct drm_encoder *encoder)
+{
+        struct rcar_du_hdmienc *hdmienc = to_rcar_hdmienc(encoder);
+        struct drm_encoder_slave_funcs *sfuncs = to_slave_funcs(encoder);
+
+        if (hdmienc->renc->lvds)
+                rcar_du_lvdsenc_enable(hdmienc->renc->lvds, encoder->crtc,
+                                       true);
 
-        if (mode != DRM_MODE_DPMS_ON && hdmienc->renc->lvds)
-                rcar_du_lvdsenc_dpms(hdmienc->renc->lvds, encoder->crtc, mode);
+        if (sfuncs->dpms)
+                sfuncs->dpms(encoder, DRM_MODE_DPMS_ON);
 
-        hdmienc->dpms = mode;
+        hdmienc->enabled = true;
 }
 
-static bool rcar_du_hdmienc_mode_fixup(struct drm_encoder *encoder,
-                                       const struct drm_display_mode *mode,
-                                       struct drm_display_mode *adjusted_mode)
+static int rcar_du_hdmienc_atomic_check(struct drm_encoder *encoder,
+                                        struct drm_crtc_state *crtc_state,
+                                        struct drm_connector_state *conn_state)
 {
         struct rcar_du_hdmienc *hdmienc = to_rcar_hdmienc(encoder);
         struct drm_encoder_slave_funcs *sfuncs = to_slave_funcs(encoder);
+        struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
+        const struct drm_display_mode *mode = &crtc_state->mode;
 
         /* The internal LVDS encoder has a clock frequency operating range of
          * 30MHz to 150MHz. Clamp the clock accordingly.
@@ -70,19 +79,9 @@ static bool rcar_du_hdmienc_mode_fixup(struct drm_encoder *encoder,
                                              30000, 150000);
 
         if (sfuncs->mode_fixup == NULL)
-                return true;
-
-        return sfuncs->mode_fixup(encoder, mode, adjusted_mode);
-}
+                return 0;
 
-static void rcar_du_hdmienc_mode_prepare(struct drm_encoder *encoder)
-{
-        rcar_du_hdmienc_dpms(encoder, DRM_MODE_DPMS_OFF);
-}
-
-static void rcar_du_hdmienc_mode_commit(struct drm_encoder *encoder)
-{
-        rcar_du_hdmienc_dpms(encoder, DRM_MODE_DPMS_ON);
+        return sfuncs->mode_fixup(encoder, mode, adjusted_mode) ? 0 : -EINVAL;
 }
 
 static void rcar_du_hdmienc_mode_set(struct drm_encoder *encoder,
@@ -99,18 +98,18 @@ static void rcar_du_hdmienc_mode_set(struct drm_encoder *encoder,
 }
 
 static const struct drm_encoder_helper_funcs encoder_helper_funcs = {
-        .dpms = rcar_du_hdmienc_dpms,
-        .mode_fixup = rcar_du_hdmienc_mode_fixup,
-        .prepare = rcar_du_hdmienc_mode_prepare,
-        .commit = rcar_du_hdmienc_mode_commit,
         .mode_set = rcar_du_hdmienc_mode_set,
+        .disable = rcar_du_hdmienc_disable,
+        .enable = rcar_du_hdmienc_enable,
+        .atomic_check = rcar_du_hdmienc_atomic_check,
 };
 
 static void rcar_du_hdmienc_cleanup(struct drm_encoder *encoder)
 {
         struct rcar_du_hdmienc *hdmienc = to_rcar_hdmienc(encoder);
 
-        rcar_du_hdmienc_dpms(encoder, DRM_MODE_DPMS_OFF);
+        if (hdmienc->enabled)
+                rcar_du_hdmienc_disable(encoder);
 
         drm_encoder_cleanup(encoder);
         put_device(hdmienc->dev);
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.c b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
index cc9136e8ee9c..fb052bca574f 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_kms.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
@@ -12,12 +12,15 @@
  */
 
 #include <drm/drmP.h>
+#include <drm/drm_atomic.h>
+#include <drm/drm_atomic_helper.h>
 #include <drm/drm_crtc.h>
 #include <drm/drm_crtc_helper.h>
 #include <drm/drm_fb_cma_helper.h>
 #include <drm/drm_gem_cma_helper.h>
 
 #include <linux/of_graph.h>
+#include <linux/wait.h>
 
 #include "rcar_du_crtc.h"
 #include "rcar_du_drv.h"
@@ -185,9 +188,309 @@ static void rcar_du_output_poll_changed(struct drm_device *dev)
         drm_fbdev_cma_hotplug_event(rcdu->fbdev);
 }
 
+/* -----------------------------------------------------------------------------
+ * Atomic Check and Update
+ */
+
+/*
+ * Atomic hardware plane allocator
+ *
+ * The hardware plane allocator is solely based on the atomic plane states
+ * without keeping any external state to avoid races between .atomic_check()
+ * and .atomic_commit().
+ *
+ * The core idea is to avoid using a free planes bitmask that would need to be
+ * shared between check and commit handlers with a collective knowledge based on
+ * the allocated hardware plane(s) for each KMS plane. The allocator then loops
+ * over all plane states to compute the free planes bitmask, allocates hardware
+ * planes based on that bitmask, and stores the result back in the plane states.
+ *
+ * For this to work we need to access the current state of planes not touched by
+ * the atomic update. To ensure that it won't be modified, we need to lock all
+ * planes using drm_atomic_get_plane_state(). This effectively serializes atomic
+ * updates from .atomic_check() up to completion (when swapping the states if
+ * the check step has succeeded) or rollback (when freeing the states if the
+ * check step has failed).
+ *
+ * Allocation is performed in the .atomic_check() handler and applied
+ * automatically when the core swaps the old and new states.
+ */
+
+static bool rcar_du_plane_needs_realloc(struct rcar_du_plane *plane,
+                                        struct rcar_du_plane_state *state)
+{
+        const struct rcar_du_format_info *cur_format;
+
+        cur_format = to_rcar_du_plane_state(plane->plane.state)->format;
+
+        /* Lowering the number of planes doesn't strictly require reallocation
+         * as the extra hardware plane will be freed when committing, but doing
+         * so could lead to more fragmentation.
+         */
+        return !cur_format || cur_format->planes != state->format->planes;
+}
+
+static unsigned int rcar_du_plane_hwmask(struct rcar_du_plane_state *state)
+{
+        unsigned int mask;
+
+        if (state->hwindex == -1)
+                return 0;
+
+        mask = 1 << state->hwindex;
+        if (state->format->planes == 2)
+                mask |= 1 << ((state->hwindex + 1) % 8);
+
+        return mask;
+}
+
+static int rcar_du_plane_hwalloc(unsigned int num_planes, unsigned int free)
+{
+        unsigned int i;
+
+        for (i = 0; i < RCAR_DU_NUM_HW_PLANES; ++i) {
+                if (!(free & (1 << i)))
+                        continue;
+
+                if (num_planes == 1 || free & (1 << ((i + 1) % 8)))
+                        break;
+        }
+
+        return i == RCAR_DU_NUM_HW_PLANES ? -EBUSY : i;
+}
+
+static int rcar_du_atomic_check(struct drm_device *dev,
+                                struct drm_atomic_state *state)
+{
+        struct rcar_du_device *rcdu = dev->dev_private;
+        unsigned int group_freed_planes[RCAR_DU_MAX_GROUPS] = { 0, };
+        unsigned int group_free_planes[RCAR_DU_MAX_GROUPS] = { 0, };
+        bool needs_realloc = false;
+        unsigned int groups = 0;
+        unsigned int i;
+        int ret;
+
+        ret = drm_atomic_helper_check(dev, state);
+        if (ret < 0)
+                return ret;
+
+        /* Check if hardware planes need to be reallocated. */
+        for (i = 0; i < dev->mode_config.num_total_plane; ++i) {
+                struct rcar_du_plane_state *plane_state;
+                struct rcar_du_plane *plane;
+                unsigned int index;
+
+                if (!state->planes[i])
+                        continue;
+
+                plane = to_rcar_plane(state->planes[i]);
+                plane_state = to_rcar_du_plane_state(state->plane_states[i]);
+
+                /* If the plane is being disabled we don't need to go through
+                 * the full reallocation procedure. Just mark the hardware
+                 * plane(s) as freed.
+                 */
+                if (!plane_state->format) {
+                        index = plane - plane->group->planes.planes;
+                        group_freed_planes[plane->group->index] |= 1 << index;
+                        plane_state->hwindex = -1;
+                        continue;
+                }
+
+                /* If the plane needs to be reallocated mark it as such, and
+                 * mark the hardware plane(s) as free.
+                 */
+                if (rcar_du_plane_needs_realloc(plane, plane_state)) {
+                        groups |= 1 << plane->group->index;
+                        needs_realloc = true;
+
+                        index = plane - plane->group->planes.planes;
+                        group_freed_planes[plane->group->index] |= 1 << index;
+                        plane_state->hwindex = -1;
+                }
+        }
+
+        if (!needs_realloc)
+                return 0;
+
+        /* Grab all plane states for the groups that need reallocation to ensure
+         * locking and avoid racy updates. This serializes the update operation,
+         * but there's not much we can do about it as that's the hardware
+         * design.
+         *
+         * Compute the used planes mask for each group at the same time to avoid
+         * looping over the planes separately later.
+         */
+        while (groups) {
+                unsigned int index = ffs(groups) - 1;
+                struct rcar_du_group *group = &rcdu->groups[index];
+                unsigned int used_planes = 0;
+
+                for (i = 0; i < RCAR_DU_NUM_KMS_PLANES; ++i) {
+                        struct rcar_du_plane *plane = &group->planes.planes[i];
+                        struct rcar_du_plane_state *plane_state;
+                        struct drm_plane_state *s;
+
+                        s = drm_atomic_get_plane_state(state, &plane->plane);
+                        if (IS_ERR(s))
+                                return PTR_ERR(s);
+
+                        /* If the plane has been freed in the above loop its
+                         * hardware planes must not be added to the used planes
+                         * bitmask. However, the current state doesn't reflect
+                         * the free state yet, as we've modified the new state
+                         * above. Use the local freed planes list to check for
+                         * that condition instead.
+                         */
+                        if (group_freed_planes[index] & (1 << i))
+                                continue;
+
+                        plane_state = to_rcar_du_plane_state(plane->plane.state);
+                        used_planes |= rcar_du_plane_hwmask(plane_state);
+                }
+
+                group_free_planes[index] = 0xff & ~used_planes;
+                groups &= ~(1 << index);
+        }
+
+        /* Reallocate hardware planes for each plane that needs it. */
+        for (i = 0; i < dev->mode_config.num_total_plane; ++i) {
+                struct rcar_du_plane_state *plane_state;
+                struct rcar_du_plane *plane;
+                int idx;
+
+                if (!state->planes[i])
+                        continue;
+
+                plane = to_rcar_plane(state->planes[i]);
+                plane_state = to_rcar_du_plane_state(state->plane_states[i]);
+
+                /* Skip planes that are being disabled or don't need to be
+                 * reallocated.
+                 */
+                if (!plane_state->format ||
+                    !rcar_du_plane_needs_realloc(plane, plane_state))
+                        continue;
+
+                idx = rcar_du_plane_hwalloc(plane_state->format->planes,
+                                        group_free_planes[plane->group->index]);
+                if (idx < 0) {
+                        dev_dbg(rcdu->dev, "%s: no available hardware plane\n",
+                                __func__);
+                        return idx;
+                }
+
+                plane_state->hwindex = idx;
+
+                group_free_planes[plane->group->index] &=
+                        ~rcar_du_plane_hwmask(plane_state);
+        }
+
+        return 0;
+}
+
+struct rcar_du_commit {
+        struct work_struct work;
+        struct drm_device *dev;
+        struct drm_atomic_state *state;
+        u32 crtcs;
+};
+
+static void rcar_du_atomic_complete(struct rcar_du_commit *commit)
+{
+        struct drm_device *dev = commit->dev;
+        struct rcar_du_device *rcdu = dev->dev_private;
+        struct drm_atomic_state *old_state = commit->state;
+
+        /* Apply the atomic update. */
+        drm_atomic_helper_commit_modeset_disables(dev, old_state);
+        drm_atomic_helper_commit_modeset_enables(dev, old_state);
+        drm_atomic_helper_commit_planes(dev, old_state);
+
+        drm_atomic_helper_wait_for_vblanks(dev, old_state);
+
+        drm_atomic_helper_cleanup_planes(dev, old_state);
+
+        drm_atomic_state_free(old_state);
+
+        /* Complete the commit, wake up any waiter. */
+        spin_lock(&rcdu->commit.wait.lock);
+        rcdu->commit.pending &= ~commit->crtcs;
+        wake_up_all_locked(&rcdu->commit.wait);
+        spin_unlock(&rcdu->commit.wait.lock);
+
+        kfree(commit);
+}
+
+static void rcar_du_atomic_work(struct work_struct *work)
+{
+        struct rcar_du_commit *commit =
+                container_of(work, struct rcar_du_commit, work);
+
+        rcar_du_atomic_complete(commit);
+}
+
+static int rcar_du_atomic_commit(struct drm_device *dev,
+                                 struct drm_atomic_state *state, bool async)
+{
+        struct rcar_du_device *rcdu = dev->dev_private;
+        struct rcar_du_commit *commit;
+        unsigned int i;
+        int ret;
+
+        ret = drm_atomic_helper_prepare_planes(dev, state);
+        if (ret)
+                return ret;
+
+        /* Allocate the commit object. */
+        commit = kzalloc(sizeof(*commit), GFP_KERNEL);
+        if (commit == NULL)
+                return -ENOMEM;
+
+        INIT_WORK(&commit->work, rcar_du_atomic_work);
+        commit->dev = dev;
+        commit->state = state;
+
+        /* Wait until all affected CRTCs have completed previous commits and
+         * mark them as pending.
+         */
+        for (i = 0; i < dev->mode_config.num_crtc; ++i) {
+                if (state->crtcs[i])
+                        commit->crtcs |= 1 << drm_crtc_index(state->crtcs[i]);
+        }
+
+        spin_lock(&rcdu->commit.wait.lock);
+        ret = wait_event_interruptible_locked(rcdu->commit.wait,
+                        !(rcdu->commit.pending & commit->crtcs));
+        if (ret == 0)
+                rcdu->commit.pending |= commit->crtcs;
+        spin_unlock(&rcdu->commit.wait.lock);
+
+        if (ret) {
+                kfree(commit);
+                return ret;
+        }
+
+        /* Swap the state, this is the point of no return. */
+        drm_atomic_helper_swap_state(dev, state);
+
+        if (async)
+                schedule_work(&commit->work);
+        else
+                rcar_du_atomic_complete(commit);
+
+        return 0;
+}
+
+/* -----------------------------------------------------------------------------
+ * Initialization
+ */
+
 static const struct drm_mode_config_funcs rcar_du_mode_config_funcs = {
         .fb_create = rcar_du_fb_create,
         .output_poll_changed = rcar_du_output_poll_changed,
+        .atomic_check = rcar_du_atomic_check,
+        .atomic_commit = rcar_du_atomic_commit,
 };
 
 static int rcar_du_encoders_init_one(struct rcar_du_device *rcdu,
@@ -392,6 +695,8 @@ int rcar_du_modeset_init(struct rcar_du_device *rcdu)
         for (i = 0; i < num_groups; ++i) {
                 struct rcar_du_group *rgrp = &rcdu->groups[i];
 
+                mutex_init(&rgrp->lock);
+
                 rgrp->dev = rcdu;
                 rgrp->mmio_offset = mmio_offsets[i];
                 rgrp->index = i;
@@ -439,27 +744,21 @@ int rcar_du_modeset_init(struct rcar_du_device *rcdu)
                 encoder->possible_clones = (1 << num_encoders) - 1;
         }
 
-        /* Now that the CRTCs have been initialized register the planes. */
-        for (i = 0; i < num_groups; ++i) {
-                ret = rcar_du_planes_register(&rcdu->groups[i]);
-                if (ret < 0)
-                        return ret;
-        }
+        drm_mode_config_reset(dev);
 
         drm_kms_helper_poll_init(dev);
 
-        drm_helper_disable_unused_functions(dev);
-
-        fbdev = drm_fbdev_cma_init(dev, 32, dev->mode_config.num_crtc,
-                                   dev->mode_config.num_connector);
-        if (IS_ERR(fbdev))
-                return PTR_ERR(fbdev);
+        if (dev->mode_config.num_connector) {
+                fbdev = drm_fbdev_cma_init(dev, 32, dev->mode_config.num_crtc,
+                                           dev->mode_config.num_connector);
+                if (IS_ERR(fbdev))
+                        return PTR_ERR(fbdev);
 
-#ifndef CONFIG_FRAMEBUFFER_CONSOLE
-        drm_fbdev_cma_restore_mode(fbdev);
-#endif
-
-        rcdu->fbdev = fbdev;
+                rcdu->fbdev = fbdev;
+        } else {
+                dev_info(rcdu->dev,
+                         "no connector found, disabling fbdev emulation\n");
+        }
 
         return 0;
 }
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_lvdscon.c b/drivers/gpu/drm/rcar-du/rcar_du_lvdscon.c
index 6d9811c052c4..0c43032fc693 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_lvdscon.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_lvdscon.c
@@ -12,6 +12,7 @@
  */
 
 #include <drm/drmP.h>
+#include <drm/drm_atomic_helper.h>
 #include <drm/drm_crtc.h>
 #include <drm/drm_crtc_helper.h>
 
@@ -74,10 +75,13 @@ rcar_du_lvds_connector_detect(struct drm_connector *connector, bool force)
 }
 
 static const struct drm_connector_funcs connector_funcs = {
-        .dpms = drm_helper_connector_dpms,
+        .dpms = drm_atomic_helper_connector_dpms,
+        .reset = drm_atomic_helper_connector_reset,
         .detect = rcar_du_lvds_connector_detect,
         .fill_modes = drm_helper_probe_single_connector_modes,
         .destroy = rcar_du_lvds_connector_destroy,
+        .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
+        .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 };
 
 int rcar_du_lvds_connector_init(struct rcar_du_device *rcdu,
@@ -117,7 +121,7 @@ int rcar_du_lvds_connector_init(struct rcar_du_device *rcdu,
         if (ret < 0)
                 return ret;
 
-        drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
+        connector->dpms = DRM_MODE_DPMS_OFF;
         drm_object_property_set_value(&connector->base,
                 rcdu->ddev->mode_config.dpms_property, DRM_MODE_DPMS_OFF);
 
@@ -125,7 +129,6 @@ int rcar_du_lvds_connector_init(struct rcar_du_device *rcdu,
         if (ret < 0)
                 return ret;
 
-        connector->encoder = encoder;
         lvdscon->connector.encoder = renc;
 
         return 0;
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c b/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c
index 7cfb48ce1791..85043c5bad03 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c
@@ -28,7 +28,7 @@ struct rcar_du_lvdsenc {
         unsigned int index;
         void __iomem *mmio;
         struct clk *clock;
-        int dpms;
+        bool enabled;
 
         enum rcar_lvds_input input;
 };
@@ -48,7 +48,7 @@ static int rcar_du_lvdsenc_start(struct rcar_du_lvdsenc *lvds,
         u32 pllcr;
         int ret;
 
-        if (lvds->dpms == DRM_MODE_DPMS_ON)
+        if (lvds->enabled)
                 return 0;
 
         ret = clk_prepare_enable(lvds->clock);
@@ -110,13 +110,13 @@ static int rcar_du_lvdsenc_start(struct rcar_du_lvdsenc *lvds,
         lvdcr0 |= LVDCR0_LVRES;
         rcar_lvds_write(lvds, LVDCR0, lvdcr0);
 
-        lvds->dpms = DRM_MODE_DPMS_ON;
+        lvds->enabled = true;
         return 0;
 }
 
 static void rcar_du_lvdsenc_stop(struct rcar_du_lvdsenc *lvds)
 {
-        if (lvds->dpms == DRM_MODE_DPMS_OFF)
+        if (!lvds->enabled)
                 return;
 
         rcar_lvds_write(lvds, LVDCR0, 0);
@@ -124,13 +124,13 @@ static void rcar_du_lvdsenc_stop(struct rcar_du_lvdsenc *lvds)
 
         clk_disable_unprepare(lvds->clock);
 
-        lvds->dpms = DRM_MODE_DPMS_OFF;
+        lvds->enabled = false;
 }
 
-int rcar_du_lvdsenc_dpms(struct rcar_du_lvdsenc *lvds,
-                         struct drm_crtc *crtc, int mode)
+int rcar_du_lvdsenc_enable(struct rcar_du_lvdsenc *lvds, struct drm_crtc *crtc,
+                           bool enable)
 {
-        if (mode == DRM_MODE_DPMS_OFF) {
+        if (!enable) {
                 rcar_du_lvdsenc_stop(lvds);
                 return 0;
         } else if (crtc) {
@@ -179,7 +179,7 @@ int rcar_du_lvdsenc_init(struct rcar_du_device *rcdu)
                 lvds->dev = rcdu;
                 lvds->index = i;
                 lvds->input = i ? RCAR_LVDS_INPUT_DU1 : RCAR_LVDS_INPUT_DU0;
-                lvds->dpms = DRM_MODE_DPMS_OFF;
+                lvds->enabled = false;
 
                 ret = rcar_du_lvdsenc_get_resources(lvds, pdev);
                 if (ret < 0)
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.h b/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.h
index f65aabda0796..9a6001c07303 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.h
+++ b/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.h
@@ -28,15 +28,15 @@ enum rcar_lvds_input {
 
 #if IS_ENABLED(CONFIG_DRM_RCAR_LVDS)
 int rcar_du_lvdsenc_init(struct rcar_du_device *rcdu);
-int rcar_du_lvdsenc_dpms(struct rcar_du_lvdsenc *lvds,
-                         struct drm_crtc *crtc, int mode);
+int rcar_du_lvdsenc_enable(struct rcar_du_lvdsenc *lvds,
+                           struct drm_crtc *crtc, bool enable);
 #else
 static inline int rcar_du_lvdsenc_init(struct rcar_du_device *rcdu)
 {
         return 0;
 }
-static inline int rcar_du_lvdsenc_dpms(struct rcar_du_lvdsenc *lvds,
-                                       struct drm_crtc *crtc, int mode)
+static inline int rcar_du_lvdsenc_enable(struct rcar_du_lvdsenc *lvds,
+                                         struct drm_crtc *crtc, bool enable)
 {
         return 0;
 }
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_plane.c b/drivers/gpu/drm/rcar-du/rcar_du_plane.c
index 50f2f2b20d39..35a2f04ab799 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_plane.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_plane.c
@@ -12,10 +12,12 @@
  */
 
 #include <drm/drmP.h>
+#include <drm/drm_atomic_helper.h>
 #include <drm/drm_crtc.h>
 #include <drm/drm_crtc_helper.h>
 #include <drm/drm_fb_cma_helper.h>
 #include <drm/drm_gem_cma_helper.h>
+#include <drm/drm_plane_helper.h>
 
 #include "rcar_du_drv.h"
 #include "rcar_du_kms.h"
@@ -26,16 +28,6 @@
 #define RCAR_DU_COLORKEY_SOURCE         (1 << 24)
 #define RCAR_DU_COLORKEY_MASK           (1 << 24)
 
-struct rcar_du_kms_plane {
-        struct drm_plane plane;
-        struct rcar_du_plane *hwplane;
-};
-
-static inline struct rcar_du_plane *to_rcar_plane(struct drm_plane *plane)
-{
-        return container_of(plane, struct rcar_du_kms_plane, plane)->hwplane;
-}
-
 static u32 rcar_du_plane_read(struct rcar_du_group *rgrp,
                               unsigned int index, u32 reg)
 {
@@ -50,74 +42,31 @@ static void rcar_du_plane_write(struct rcar_du_group *rgrp,
                       data);
 }
 
-int rcar_du_plane_reserve(struct rcar_du_plane *plane,
-                          const struct rcar_du_format_info *format)
-{
-        struct rcar_du_group *rgrp = plane->group;
-        unsigned int i;
-        int ret = -EBUSY;
-
-        mutex_lock(&rgrp->planes.lock);
-
-        for (i = 0; i < ARRAY_SIZE(rgrp->planes.planes); ++i) {
-                if (!(rgrp->planes.free & (1 << i)))
-                        continue;
-
-                if (format->planes == 1 ||
-                    rgrp->planes.free & (1 << ((i + 1) % 8)))
-                        break;
-        }
-
-        if (i == ARRAY_SIZE(rgrp->planes.planes))
-                goto done;
-
-        rgrp->planes.free &= ~(1 << i);
-        if (format->planes == 2)
-                rgrp->planes.free &= ~(1 << ((i + 1) % 8));
-
-        plane->hwindex = i;
-
-        ret = 0;
-
-done:
-        mutex_unlock(&rgrp->planes.lock);
-        return ret;
-}
-
-void rcar_du_plane_release(struct rcar_du_plane *plane)
-{
-        struct rcar_du_group *rgrp = plane->group;
-
-        if (plane->hwindex == -1)
-                return;
-
-        mutex_lock(&rgrp->planes.lock);
-        rgrp->planes.free |= 1 << plane->hwindex;
-        if (plane->format->planes == 2)
-                rgrp->planes.free |= 1 << ((plane->hwindex + 1) % 8);
-        mutex_unlock(&rgrp->planes.lock);
-
-        plane->hwindex = -1;
-}
-
-void rcar_du_plane_update_base(struct rcar_du_plane *plane)
+static void rcar_du_plane_setup_fb(struct rcar_du_plane *plane)
 {
+        struct rcar_du_plane_state *state =
+                to_rcar_du_plane_state(plane->plane.state);
+        struct drm_framebuffer *fb = plane->plane.state->fb;
         struct rcar_du_group *rgrp = plane->group;
-        unsigned int index = plane->hwindex;
+        unsigned int src_x = state->state.src_x >> 16;
+        unsigned int src_y = state->state.src_y >> 16;
+        unsigned int index = state->hwindex;
+        struct drm_gem_cma_object *gem;
         bool interlaced;
         u32 mwr;
 
-        interlaced = plane->crtc->mode.flags & DRM_MODE_FLAG_INTERLACE;
+        interlaced = state->state.crtc->state->adjusted_mode.flags
+                   & DRM_MODE_FLAG_INTERLACE;
 
         /* Memory pitch (expressed in pixels). Must be doubled for interlaced
          * operation with 32bpp formats.
          */
-        if (plane->format->planes == 2)
-                mwr = plane->pitch;
+        if (state->format->planes == 2)
+                mwr = fb->pitches[0];
         else
-                mwr = plane->pitch * 8 / plane->format->bpp;
+                mwr = fb->pitches[0] * 8 / state->format->bpp;
 
-        if (interlaced && plane->format->bpp == 32)
+        if (interlaced && state->format->bpp == 32)
                 mwr *= 2;
 
         rcar_du_plane_write(rgrp, index, PnMWR, mwr);
@@ -134,42 +83,33 @@ void rcar_du_plane_update_base(struct rcar_du_plane *plane)
          * require a halved Y position value, in both progressive and interlaced
          * modes.
          */
-        rcar_du_plane_write(rgrp, index, PnSPXR, plane->src_x);
-        rcar_du_plane_write(rgrp, index, PnSPYR, plane->src_y *
-                            (!interlaced && plane->format->bpp == 32 ? 2 : 1));
-        rcar_du_plane_write(rgrp, index, PnDSA0R, plane->dma[0]);
+        rcar_du_plane_write(rgrp, index, PnSPXR, src_x);
+        rcar_du_plane_write(rgrp, index, PnSPYR, src_y *
+                            (!interlaced && state->format->bpp == 32 ? 2 : 1));
 
-        if (plane->format->planes == 2) {
-                index = (index + 1) % 8;
-
-                rcar_du_plane_write(rgrp, index, PnMWR, plane->pitch);
+        gem = drm_fb_cma_get_gem_obj(fb, 0);
+        rcar_du_plane_write(rgrp, index, PnDSA0R, gem->paddr + fb->offsets[0]);
 
-                rcar_du_plane_write(rgrp, index, PnSPXR, plane->src_x);
-                rcar_du_plane_write(rgrp, index, PnSPYR, plane->src_y *
-                                    (plane->format->bpp == 16 ? 2 : 1) / 2);
-                rcar_du_plane_write(rgrp, index, PnDSA0R, plane->dma[1]);
-        }
-}
+        if (state->format->planes == 2) {
+                index = (index + 1) % 8;
 
-void rcar_du_plane_compute_base(struct rcar_du_plane *plane,
-                                struct drm_framebuffer *fb)
-{
-        struct drm_gem_cma_object *gem;
+                rcar_du_plane_write(rgrp, index, PnMWR, fb->pitches[0]);
 
-        plane->pitch = fb->pitches[0];
+                rcar_du_plane_write(rgrp, index, PnSPXR, src_x);
+                rcar_du_plane_write(rgrp, index, PnSPYR, src_y *
+                                    (state->format->bpp == 16 ? 2 : 1) / 2);
 
-        gem = drm_fb_cma_get_gem_obj(fb, 0);
-        plane->dma[0] = gem->paddr + fb->offsets[0];
-
-        if (plane->format->planes == 2) {
                 gem = drm_fb_cma_get_gem_obj(fb, 1);
-                plane->dma[1] = gem->paddr + fb->offsets[1];
+                rcar_du_plane_write(rgrp, index, PnDSA0R,
+                                    gem->paddr + fb->offsets[1]);
         }
 }
 
 static void rcar_du_plane_setup_mode(struct rcar_du_plane *plane,
                                      unsigned int index)
 {
+        struct rcar_du_plane_state *state =
+                to_rcar_du_plane_state(plane->plane.state);
         struct rcar_du_group *rgrp = plane->group;
         u32 colorkey;
         u32 pnmr;
@@ -183,47 +123,47 @@ static void rcar_du_plane_setup_mode(struct rcar_du_plane *plane,
          * For XRGB, set the alpha value to the plane-wide alpha value and
          * enable alpha-blending regardless of the X bit value.
          */
-        if (plane->format->fourcc != DRM_FORMAT_XRGB1555)
+        if (state->format->fourcc != DRM_FORMAT_XRGB1555)
                 rcar_du_plane_write(rgrp, index, PnALPHAR, PnALPHAR_ABIT_0);
         else
                 rcar_du_plane_write(rgrp, index, PnALPHAR,
-                                    PnALPHAR_ABIT_X | plane->alpha);
+                                    PnALPHAR_ABIT_X | state->alpha);
 
-        pnmr = PnMR_BM_MD | plane->format->pnmr;
+        pnmr = PnMR_BM_MD | state->format->pnmr;
 
         /* Disable color keying when requested. YUV formats have the
          * PnMR_SPIM_TP_OFF bit set in their pnmr field, disabling color keying
          * automatically.
          */
-        if ((plane->colorkey & RCAR_DU_COLORKEY_MASK) == RCAR_DU_COLORKEY_NONE)
+        if ((state->colorkey & RCAR_DU_COLORKEY_MASK) == RCAR_DU_COLORKEY_NONE)
                 pnmr |= PnMR_SPIM_TP_OFF;
 
         /* For packed YUV formats we need to select the U/V order. */
-        if (plane->format->fourcc == DRM_FORMAT_YUYV)
+        if (state->format->fourcc == DRM_FORMAT_YUYV)
                 pnmr |= PnMR_YCDF_YUYV;
 
         rcar_du_plane_write(rgrp, index, PnMR, pnmr);
 
-        switch (plane->format->fourcc) {
+        switch (state->format->fourcc) {
         case DRM_FORMAT_RGB565:
-                colorkey = ((plane->colorkey & 0xf80000) >> 8)
-                         | ((plane->colorkey & 0x00fc00) >> 5)
-                         | ((plane->colorkey & 0x0000f8) >> 3);
+                colorkey = ((state->colorkey & 0xf80000) >> 8)
+                         | ((state->colorkey & 0x00fc00) >> 5)
+                         | ((state->colorkey & 0x0000f8) >> 3);
                 rcar_du_plane_write(rgrp, index, PnTC2R, colorkey);
                 break;
 
         case DRM_FORMAT_ARGB1555:
         case DRM_FORMAT_XRGB1555:
-                colorkey = ((plane->colorkey & 0xf80000) >> 9)
-                         | ((plane->colorkey & 0x00f800) >> 6)
-                         | ((plane->colorkey & 0x0000f8) >> 3);
+                colorkey = ((state->colorkey & 0xf80000) >> 9)
+                         | ((state->colorkey & 0x00f800) >> 6)
+                         | ((state->colorkey & 0x0000f8) >> 3);
                 rcar_du_plane_write(rgrp, index, PnTC2R, colorkey);
                 break;
 
         case DRM_FORMAT_XRGB8888:
         case DRM_FORMAT_ARGB8888:
                 rcar_du_plane_write(rgrp, index, PnTC3R,
-                                    PnTC3R_CODE | (plane->colorkey & 0xffffff));
+                                    PnTC3R_CODE | (state->colorkey & 0xffffff));
                 break;
         }
 }
@@ -231,6 +171,8 @@ static void rcar_du_plane_setup_mode(struct rcar_du_plane *plane,
 static void __rcar_du_plane_setup(struct rcar_du_plane *plane,
                                   unsigned int index)
 {
+        struct rcar_du_plane_state *state =
+                to_rcar_du_plane_state(plane->plane.state);
         struct rcar_du_group *rgrp = plane->group;
         u32 ddcr2 = PnDDCR2_CODE;
         u32 ddcr4;
@@ -242,17 +184,17 @@ static void __rcar_du_plane_setup(struct rcar_du_plane *plane,
          */
         ddcr4 = rcar_du_plane_read(rgrp, index, PnDDCR4);
         ddcr4 &= ~PnDDCR4_EDF_MASK;
-        ddcr4 |= plane->format->edf | PnDDCR4_CODE;
+        ddcr4 |= state->format->edf | PnDDCR4_CODE;
 
         rcar_du_plane_setup_mode(plane, index);
 
-        if (plane->format->planes == 2) {
-                if (plane->hwindex != index) {
-                        if (plane->format->fourcc == DRM_FORMAT_NV12 ||
-                            plane->format->fourcc == DRM_FORMAT_NV21)
+        if (state->format->planes == 2) {
+                if (state->hwindex != index) {
+                        if (state->format->fourcc == DRM_FORMAT_NV12 ||
+                            state->format->fourcc == DRM_FORMAT_NV21)
                                 ddcr2 |= PnDDCR2_Y420;
 
-                        if (plane->format->fourcc == DRM_FORMAT_NV21)
+                        if (state->format->fourcc == DRM_FORMAT_NV21)
                                 ddcr2 |= PnDDCR2_NV21;
 
                         ddcr2 |= PnDDCR2_DIVU;
@@ -265,10 +207,10 @@ static void __rcar_du_plane_setup(struct rcar_du_plane *plane,
         rcar_du_plane_write(rgrp, index, PnDDCR4, ddcr4);
 
         /* Destination position and size */
-        rcar_du_plane_write(rgrp, index, PnDSXR, plane->width);
-        rcar_du_plane_write(rgrp, index, PnDSYR, plane->height);
-        rcar_du_plane_write(rgrp, index, PnDPXR, plane->dst_x);
-        rcar_du_plane_write(rgrp, index, PnDPYR, plane->dst_y);
+        rcar_du_plane_write(rgrp, index, PnDSXR, plane->plane.state->crtc_w);
+        rcar_du_plane_write(rgrp, index, PnDSYR, plane->plane.state->crtc_h);
+        rcar_du_plane_write(rgrp, index, PnDPXR, plane->plane.state->crtc_x);
+        rcar_du_plane_write(rgrp, index, PnDPYR, plane->plane.state->crtc_y);
 
         /* Wrap-around and blinking, disabled */
         rcar_du_plane_write(rgrp, index, PnWASPR, 0);
@@ -279,150 +221,140 @@ static void __rcar_du_plane_setup(struct rcar_du_plane *plane,
 
 void rcar_du_plane_setup(struct rcar_du_plane *plane)
 {
-        __rcar_du_plane_setup(plane, plane->hwindex);
-        if (plane->format->planes == 2)
-                __rcar_du_plane_setup(plane, (plane->hwindex + 1) % 8);
+        struct rcar_du_plane_state *state =
+                to_rcar_du_plane_state(plane->plane.state);
+
+        __rcar_du_plane_setup(plane, state->hwindex);
+        if (state->format->planes == 2)
+                __rcar_du_plane_setup(plane, (state->hwindex + 1) % 8);
 
-        rcar_du_plane_update_base(plane);
+        rcar_du_plane_setup_fb(plane);
 }
 
-static int
-rcar_du_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
-                       struct drm_framebuffer *fb, int crtc_x, int crtc_y,
-                       unsigned int crtc_w, unsigned int crtc_h,
-                       uint32_t src_x, uint32_t src_y,
-                       uint32_t src_w, uint32_t src_h)
+static int rcar_du_plane_atomic_check(struct drm_plane *plane,
+                                      struct drm_plane_state *state)
 {
+        struct rcar_du_plane_state *rstate = to_rcar_du_plane_state(state);
         struct rcar_du_plane *rplane = to_rcar_plane(plane);
         struct rcar_du_device *rcdu = rplane->group->dev;
-        const struct rcar_du_format_info *format;
-        unsigned int nplanes;
-        int ret;
 
-        format = rcar_du_format_info(fb->pixel_format);
-        if (format == NULL) {
-                dev_dbg(rcdu->dev, "%s: unsupported format %08x\n", __func__,
-                        fb->pixel_format);
-                return -EINVAL;
+        if (!state->fb || !state->crtc) {
+                rstate->format = NULL;
+                return 0;
         }
 
-        if (src_w >> 16 != crtc_w || src_h >> 16 != crtc_h) {
+        if (state->src_w >> 16 != state->crtc_w ||
+            state->src_h >> 16 != state->crtc_h) {
                 dev_dbg(rcdu->dev, "%s: scaling not supported\n", __func__);
                 return -EINVAL;
         }
 
-        nplanes = rplane->format ? rplane->format->planes : 0;
-
-        /* Reallocate hardware planes if the number of required planes has
-         * changed.
-         */
-        if (format->planes != nplanes) {
-                rcar_du_plane_release(rplane);
-                ret = rcar_du_plane_reserve(rplane, format);
-                if (ret < 0)
-                        return ret;
+        rstate->format = rcar_du_format_info(state->fb->pixel_format);
+        if (rstate->format == NULL) {
+                dev_dbg(rcdu->dev, "%s: unsupported format %08x\n", __func__,
+                        state->fb->pixel_format);
+                return -EINVAL;
         }
 
-        rplane->crtc = crtc;
-        rplane->format = format;
-
-        rplane->src_x = src_x >> 16;
-        rplane->src_y = src_y >> 16;
-        rplane->dst_x = crtc_x;
-        rplane->dst_y = crtc_y;
-        rplane->width = crtc_w;
-        rplane->height = crtc_h;
-
-        rcar_du_plane_compute_base(rplane, fb);
-        rcar_du_plane_setup(rplane);
-
-        mutex_lock(&rplane->group->planes.lock);
-        rplane->enabled = true;
-        rcar_du_crtc_update_planes(rplane->crtc);
-        mutex_unlock(&rplane->group->planes.lock);
-
         return 0;
 }
 
-static int rcar_du_plane_disable(struct drm_plane *plane)
+static void rcar_du_plane_atomic_update(struct drm_plane *plane,
+                                        struct drm_plane_state *old_state)
 {
         struct rcar_du_plane *rplane = to_rcar_plane(plane);
 
-        if (!rplane->enabled)
-                return 0;
+        if (plane->state->crtc)
+                rcar_du_plane_setup(rplane);
+}
 
-        mutex_lock(&rplane->group->planes.lock);
-        rplane->enabled = false;
-        rcar_du_crtc_update_planes(rplane->crtc);
-        mutex_unlock(&rplane->group->planes.lock);
+static const struct drm_plane_helper_funcs rcar_du_plane_helper_funcs = {
+        .atomic_check = rcar_du_plane_atomic_check,
+        .atomic_update = rcar_du_plane_atomic_update,
+};
 
-        rcar_du_plane_release(rplane);
+static void rcar_du_plane_reset(struct drm_plane *plane)
+{
+        struct rcar_du_plane_state *state;
 
-        rplane->crtc = NULL;
-        rplane->format = NULL;
+        if (plane->state && plane->state->fb)
+                drm_framebuffer_unreference(plane->state->fb);
 
-        return 0;
-}
+        kfree(plane->state);
+        plane->state = NULL;
 
-/* Both the .set_property and the .update_plane operations are called with the
- * mode_config lock held. There is this no need to explicitly protect access to
- * the alpha and colorkey fields and the mode register.
- */
-static void rcar_du_plane_set_alpha(struct rcar_du_plane *plane, u32 alpha)
-{
-        if (plane->alpha == alpha)
+        state = kzalloc(sizeof(*state), GFP_KERNEL);
+        if (state == NULL)
                 return;
 
-        plane->alpha = alpha;
-        if (!plane->enabled || plane->format->fourcc != DRM_FORMAT_XRGB1555)
-                return;
+        state->hwindex = -1;
+        state->alpha = 255;
+        state->colorkey = RCAR_DU_COLORKEY_NONE;
+        state->zpos = plane->type == DRM_PLANE_TYPE_PRIMARY ? 0 : 1;
 
-        rcar_du_plane_setup_mode(plane, plane->hwindex);
+        plane->state = &state->state;
+        plane->state->plane = plane;
 }
 
-static void rcar_du_plane_set_colorkey(struct rcar_du_plane *plane,
-                                       u32 colorkey)
+static struct drm_plane_state *
+rcar_du_plane_atomic_duplicate_state(struct drm_plane *plane)
 {
-        if (plane->colorkey == colorkey)
-                return;
+        struct rcar_du_plane_state *state;
+        struct rcar_du_plane_state *copy;
 
-        plane->colorkey = colorkey;
-        if (!plane->enabled)
-                return;
+        state = to_rcar_du_plane_state(plane->state);
+        copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
+        if (copy == NULL)
+                return NULL;
+
+        if (copy->state.fb)
+                drm_framebuffer_reference(copy->state.fb);
 
-        rcar_du_plane_setup_mode(plane, plane->hwindex);
+        return &copy->state;
 }
 
-static void rcar_du_plane_set_zpos(struct rcar_du_plane *plane,
-                                   unsigned int zpos)
+static void rcar_du_plane_atomic_destroy_state(struct drm_plane *plane,
+                                               struct drm_plane_state *state)
 {
-        mutex_lock(&plane->group->planes.lock);
-        if (plane->zpos == zpos)
-                goto done;
+        kfree(to_rcar_du_plane_state(state));
+}
 
-        plane->zpos = zpos;
-        if (!plane->enabled)
-                goto done;
+static int rcar_du_plane_atomic_set_property(struct drm_plane *plane,
+                                             struct drm_plane_state *state,
+                                             struct drm_property *property,
+                                             uint64_t val)
+{
+        struct rcar_du_plane_state *rstate = to_rcar_du_plane_state(state);
+        struct rcar_du_plane *rplane = to_rcar_plane(plane);
+        struct rcar_du_group *rgrp = rplane->group;
 
-        rcar_du_crtc_update_planes(plane->crtc);
+        if (property == rgrp->planes.alpha)
+                rstate->alpha = val;
+        else if (property == rgrp->planes.colorkey)
+                rstate->colorkey = val;
+        else if (property == rgrp->planes.zpos)
+                rstate->zpos = val;
+        else
+                return -EINVAL;
 
-done:
-        mutex_unlock(&plane->group->planes.lock);
+        return 0;
 }
 
-static int rcar_du_plane_set_property(struct drm_plane *plane,
-                                      struct drm_property *property,
-                                      uint64_t value)
+static int rcar_du_plane_atomic_get_property(struct drm_plane *plane,
+        const struct drm_plane_state *state, struct drm_property *property,
+        uint64_t *val)
 {
+        const struct rcar_du_plane_state *rstate =
+                container_of(state, const struct rcar_du_plane_state, state);
         struct rcar_du_plane *rplane = to_rcar_plane(plane);
         struct rcar_du_group *rgrp = rplane->group;
 
         if (property == rgrp->planes.alpha)
-                rcar_du_plane_set_alpha(rplane, value);
+                *val = rstate->alpha;
         else if (property == rgrp->planes.colorkey)
-                rcar_du_plane_set_colorkey(rplane, value);
+                *val = rstate->colorkey;
         else if (property == rgrp->planes.zpos)
-                rcar_du_plane_set_zpos(rplane, value);
+                *val = rstate->zpos;
         else
                 return -EINVAL;
 
@@ -430,10 +362,15 @@ static int rcar_du_plane_set_property(struct drm_plane *plane,
 }
 
 static const struct drm_plane_funcs rcar_du_plane_funcs = {
-        .update_plane = rcar_du_plane_update,
-        .disable_plane = rcar_du_plane_disable,
-        .set_property = rcar_du_plane_set_property,
+        .update_plane = drm_atomic_helper_update_plane,
+        .disable_plane = drm_atomic_helper_disable_plane,
+        .reset = rcar_du_plane_reset,
+        .set_property = drm_atomic_helper_plane_set_property,
         .destroy = drm_plane_cleanup,
+        .atomic_duplicate_state = rcar_du_plane_atomic_duplicate_state,
+        .atomic_destroy_state = rcar_du_plane_atomic_destroy_state,
+        .atomic_set_property = rcar_du_plane_atomic_set_property,
+        .atomic_get_property = rcar_du_plane_atomic_get_property,
 };
 
 static const uint32_t formats[] = {
@@ -453,10 +390,11 @@ int rcar_du_planes_init(struct rcar_du_group *rgrp)
 {
         struct rcar_du_planes *planes = &rgrp->planes;
         struct rcar_du_device *rcdu = rgrp->dev;
+        unsigned int num_planes;
+        unsigned int num_crtcs;
+        unsigned int crtcs;
         unsigned int i;
-
-        mutex_init(&planes->lock);
-        planes->free = 0xff;
+        int ret;
 
         planes->alpha =
                 drm_property_create_range(rcdu->ddev, 0, "alpha", 0, 255);
@@ -478,45 +416,34 @@ int rcar_du_planes_init(struct rcar_du_group *rgrp)
         if (planes->zpos == NULL)
                 return -ENOMEM;
 
-        for (i = 0; i < ARRAY_SIZE(planes->planes); ++i) {
-                struct rcar_du_plane *plane = &planes->planes[i];
-
-                plane->group = rgrp;
-                plane->hwindex = -1;
-                plane->alpha = 255;
-                plane->colorkey = RCAR_DU_COLORKEY_NONE;
-                plane->zpos = 0;
-        }
-
-        return 0;
-}
-
-int rcar_du_planes_register(struct rcar_du_group *rgrp)
-{
-        struct rcar_du_planes *planes = &rgrp->planes;
-        struct rcar_du_device *rcdu = rgrp->dev;
-        unsigned int crtcs;
-        unsigned int i;
-        int ret;
+         /* Create one primary plane per in this group CRTC and seven overlay
+          * planes.
+          */
+        num_crtcs = min(rcdu->num_crtcs - 2 * rgrp->index, 2U);
+        num_planes = num_crtcs + 7;
 
         crtcs = ((1 << rcdu->num_crtcs) - 1) & (3 << (2 * rgrp->index));
 
-        for (i = 0; i < RCAR_DU_NUM_KMS_PLANES; ++i) {
-                struct rcar_du_kms_plane *plane;
-
-                plane = devm_kzalloc(rcdu->dev, sizeof(*plane), GFP_KERNEL);
-                if (plane == NULL)
-                        return -ENOMEM;
+        for (i = 0; i < num_planes; ++i) {
+                enum drm_plane_type type = i < num_crtcs
+                                         ? DRM_PLANE_TYPE_PRIMARY
+                                         : DRM_PLANE_TYPE_OVERLAY;
+                struct rcar_du_plane *plane = &planes->planes[i];
 
-                plane->hwplane = &planes->planes[i + 2];
-                plane->hwplane->zpos = 1;
+                plane->group = rgrp;
 
-                ret = drm_plane_init(rcdu->ddev, &plane->plane, crtcs,
-                                     &rcar_du_plane_funcs, formats,
-                                     ARRAY_SIZE(formats), false);
+                ret = drm_universal_plane_init(rcdu->ddev, &plane->plane, crtcs,
+                                               &rcar_du_plane_funcs, formats,
+                                               ARRAY_SIZE(formats), type);
                 if (ret < 0)
                         return ret;
 
+                drm_plane_helper_add(&plane->plane,
+                                     &rcar_du_plane_helper_funcs);
+
+                if (type == DRM_PLANE_TYPE_PRIMARY)
+                        continue;
+
                 drm_object_attach_property(&plane->plane.base,
                                            planes->alpha, 255);
                 drm_object_attach_property(&plane->plane.base,
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_plane.h b/drivers/gpu/drm/rcar-du/rcar_du_plane.h
index 3021288b1a89..abff0ebeb195 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_plane.h
+++ b/drivers/gpu/drm/rcar-du/rcar_du_plane.h
@@ -14,68 +14,57 @@
 #ifndef __RCAR_DU_PLANE_H__
 #define __RCAR_DU_PLANE_H__
 
-#include <linux/mutex.h>
-
 #include <drm/drmP.h>
 #include <drm/drm_crtc.h>
 
 struct rcar_du_format_info;
 struct rcar_du_group;
 
-/* The RCAR DU has 8 hardware planes, shared between KMS planes and CRTCs. As
- * using KMS planes requires at least one of the CRTCs being enabled, no more
- * than 7 KMS planes can be available. We thus create 7 KMS planes and
- * 9 software planes (one for each KMS planes and one for each CRTC).
+/* The RCAR DU has 8 hardware planes, shared between primary and overlay planes.
+ * As using overlay planes requires at least one of the CRTCs being enabled, no
+ * more than 7 overlay planes can be available. We thus create 1 primary plane
+ * per CRTC and 7 overlay planes, for a total of up to 9 KMS planes.
  */
-
-#define RCAR_DU_NUM_KMS_PLANES          7
+#define RCAR_DU_NUM_KMS_PLANES          9
 #define RCAR_DU_NUM_HW_PLANES           8
-#define RCAR_DU_NUM_SW_PLANES           9
 
 struct rcar_du_plane {
+        struct drm_plane plane;
         struct rcar_du_group *group;
-        struct drm_crtc *crtc;
-
-        bool enabled;
-
-        int hwindex;            /* 0-based, -1 means unused */
-        unsigned int alpha;
-        unsigned int colorkey;
-        unsigned int zpos;
-
-        const struct rcar_du_format_info *format;
-
-        unsigned long dma[2];
-        unsigned int pitch;
-
-        unsigned int width;
-        unsigned int height;
-
-        unsigned int src_x;
-        unsigned int src_y;
-        unsigned int dst_x;
-        unsigned int dst_y;
 };
 
+static inline struct rcar_du_plane *to_rcar_plane(struct drm_plane *plane)
+{
+        return container_of(plane, struct rcar_du_plane, plane);
+}
+
 struct rcar_du_planes {
-        struct rcar_du_plane planes[RCAR_DU_NUM_SW_PLANES];
-        unsigned int free;
-        struct mutex lock;
+        struct rcar_du_plane planes[RCAR_DU_NUM_KMS_PLANES];
 
         struct drm_property *alpha;
         struct drm_property *colorkey;
         struct drm_property *zpos;
 };
 
+struct rcar_du_plane_state {
+        struct drm_plane_state state;
+
+        const struct rcar_du_format_info *format;
+        int hwindex;            /* 0-based, -1 means unused */
+
+        unsigned int alpha;
+        unsigned int colorkey;
+        unsigned int zpos;
+};
+
+static inline struct rcar_du_plane_state *
+to_rcar_du_plane_state(struct drm_plane_state *state)
+{
+        return container_of(state, struct rcar_du_plane_state, state);
+}
+
 int rcar_du_planes_init(struct rcar_du_group *rgrp);
-int rcar_du_planes_register(struct rcar_du_group *rgrp);
 
 void rcar_du_plane_setup(struct rcar_du_plane *plane);
-void rcar_du_plane_update_base(struct rcar_du_plane *plane);
-void rcar_du_plane_compute_base(struct rcar_du_plane *plane,
-                                struct drm_framebuffer *fb);
-int rcar_du_plane_reserve(struct rcar_du_plane *plane,
-                          const struct rcar_du_format_info *format);
-void rcar_du_plane_release(struct rcar_du_plane *plane);
 
 #endif /* __RCAR_DU_PLANE_H__ */
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vgacon.c b/drivers/gpu/drm/rcar-du/rcar_du_vgacon.c
index 9d4879921cc7..e0a5d8f93963 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_vgacon.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_vgacon.c
@@ -12,6 +12,7 @@
  */
 
 #include <drm/drmP.h>
+#include <drm/drm_atomic_helper.h>
 #include <drm/drm_crtc.h>
 #include <drm/drm_crtc_helper.h>
 
@@ -43,10 +44,13 @@ rcar_du_vga_connector_detect(struct drm_connector *connector, bool force)
 }
 
 static const struct drm_connector_funcs connector_funcs = {
-        .dpms = drm_helper_connector_dpms,
+        .dpms = drm_atomic_helper_connector_dpms,
+        .reset = drm_atomic_helper_connector_reset,
         .detect = rcar_du_vga_connector_detect,
         .fill_modes = drm_helper_probe_single_connector_modes,
         .destroy = rcar_du_vga_connector_destroy,
+        .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
+        .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 };
 
 int rcar_du_vga_connector_init(struct rcar_du_device *rcdu,
@@ -76,7 +80,7 @@ int rcar_du_vga_connector_init(struct rcar_du_device *rcdu,
         if (ret < 0)
                 return ret;
 
-        drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
+        connector->dpms = DRM_MODE_DPMS_OFF;
         drm_object_property_set_value(&connector->base,
                 rcdu->ddev->mode_config.dpms_property, DRM_MODE_DPMS_OFF);
 
@@ -84,7 +88,6 @@ int rcar_du_vga_connector_init(struct rcar_du_device *rcdu,
         if (ret < 0)
                 return ret;
 
-        connector->encoder = encoder;
         rcon->encoder = renc;
 
         return 0;
diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c
index 1a52522f5da7..b7f781573b15 100644
--- a/drivers/gpu/drm/tegra/dc.c
+++ b/drivers/gpu/drm/tegra/dc.c
@@ -472,13 +472,15 @@ static const struct drm_plane_funcs tegra_primary_plane_funcs = {
 };
 
 static int tegra_plane_prepare_fb(struct drm_plane *plane,
-                                  struct drm_framebuffer *fb)
+                                  struct drm_framebuffer *fb,
+                                  const struct drm_plane_state *new_state)
 {
         return 0;
 }
 
 static void tegra_plane_cleanup_fb(struct drm_plane *plane,
-                                   struct drm_framebuffer *fb)
+                                   struct drm_framebuffer *fb,
+                                   const struct drm_plane_state *old_fb)
 {
 }
 
diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c
index 7dd328d77996..5f1880766110 100644
--- a/drivers/gpu/drm/tegra/drm.c
+++ b/drivers/gpu/drm/tegra/drm.c
@@ -55,9 +55,9 @@ static void tegra_atomic_complete(struct tegra_drm *tegra,
          * current layout.
          */
 
-        drm_atomic_helper_commit_pre_planes(drm, state);
+        drm_atomic_helper_commit_modeset_disables(drm, state);
         drm_atomic_helper_commit_planes(drm, state);
-        drm_atomic_helper_commit_post_planes(drm, state);
+        drm_atomic_helper_commit_modeset_enables(drm, state);
 
         drm_atomic_helper_wait_for_vblanks(drm, state);
 
diff --git a/include/drm/drmP.h b/include/drm/drmP.h
index e928625a9da0..63c0b0131f61 100644
--- a/include/drm/drmP.h
+++ b/include/drm/drmP.h
@@ -104,6 +104,9 @@ struct dma_buf_attachment;
  * PRIME: used in the prime code.
  *        This is the category used by the DRM_DEBUG_PRIME() macro.
  *
+ * ATOMIC: used in the atomic code.
+ *        This is the category used by the DRM_DEBUG_ATOMIC() macro.
+ *
  * Enabling verbose debug messages is done through the drm.debug parameter,
  * each category being enabled by a bit.
  *
@@ -121,6 +124,7 @@ struct dma_buf_attachment;
 #define DRM_UT_DRIVER           0x02
 #define DRM_UT_KMS              0x04
 #define DRM_UT_PRIME            0x08
+#define DRM_UT_ATOMIC           0x10
 
 extern __printf(2, 3)
 void drm_ut_debug_printk(const char *function_name,
@@ -207,6 +211,11 @@ void drm_err(const char *format, ...);
                 if (unlikely(drm_debug & DRM_UT_PRIME))                 \
                         drm_ut_debug_printk(__func__, fmt, ##args);     \
         } while (0)
+#define DRM_DEBUG_ATOMIC(fmt, args...)                                  \
+        do {                                                            \
+                if (unlikely(drm_debug & DRM_UT_ATOMIC))                \
+                        drm_ut_debug_printk(__func__, fmt, ##args);     \
+        } while (0)
 
 /*@}*/
 
@@ -922,6 +931,7 @@ extern void drm_crtc_wait_one_vblank(struct drm_crtc *crtc);
 extern void drm_vblank_off(struct drm_device *dev, int crtc);
 extern void drm_vblank_on(struct drm_device *dev, int crtc);
 extern void drm_crtc_vblank_off(struct drm_crtc *crtc);
+extern void drm_crtc_vblank_reset(struct drm_crtc *crtc);
 extern void drm_crtc_vblank_on(struct drm_crtc *crtc);
 extern void drm_vblank_cleanup(struct drm_device *dev);
 
diff --git a/include/drm/drm_atomic_helper.h b/include/drm/drm_atomic_helper.h
index 8039d54a7441..829280b56874 100644
--- a/include/drm/drm_atomic_helper.h
+++ b/include/drm/drm_atomic_helper.h
@@ -43,9 +43,9 @@ int drm_atomic_helper_commit(struct drm_device *dev,
 void drm_atomic_helper_wait_for_vblanks(struct drm_device *dev,
                                         struct drm_atomic_state *old_state);
 
-void drm_atomic_helper_commit_pre_planes(struct drm_device *dev,
-                                         struct drm_atomic_state *state);
-void drm_atomic_helper_commit_post_planes(struct drm_device *dev,
+void drm_atomic_helper_commit_modeset_disables(struct drm_device *dev,
+                                               struct drm_atomic_state *state);
+void drm_atomic_helper_commit_modeset_enables(struct drm_device *dev,
                                           struct drm_atomic_state *old_state);
 
 int drm_atomic_helper_prepare_planes(struct drm_device *dev,
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 920e21a8f3fd..b1465d6fbe94 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -202,6 +202,7 @@ struct drm_framebuffer {
         const struct drm_framebuffer_funcs *funcs;
         unsigned int pitches[4];
         unsigned int offsets[4];
+        uint64_t modifier[4];
         unsigned int width;
         unsigned int height;
         /* depth can be 15 or 16 */
@@ -1155,6 +1156,9 @@ struct drm_mode_config {
         /* whether async page flip is supported or not */
         bool async_page_flip;
 
+        /* whether the driver supports fb modifiers */
+        bool allow_fb_modifiers;
+
         /* cursor size */
         uint32_t cursor_width, cursor_height;
 };
diff --git a/include/drm/drm_crtc_helper.h b/include/drm/drm_crtc_helper.h
index c250a22b39ab..92d5135b55d2 100644
--- a/include/drm/drm_crtc_helper.h
+++ b/include/drm/drm_crtc_helper.h
@@ -89,6 +89,7 @@ struct drm_crtc_helper_funcs {
         int (*mode_set)(struct drm_crtc *crtc, struct drm_display_mode *mode,
                         struct drm_display_mode *adjusted_mode, int x, int y,
                         struct drm_framebuffer *old_fb);
+        /* Actually set the mode for atomic helpers, optional */
         void (*mode_set_nofb)(struct drm_crtc *crtc);
 
         /* Move the crtc on the current fb to the given position *optional* */
@@ -119,7 +120,7 @@ struct drm_crtc_helper_funcs {
  * @mode_fixup: try to fixup proposed mode for this connector
  * @prepare: part of the disable sequence, called before the CRTC modeset
  * @commit: called after the CRTC modeset
- * @mode_set: set this mode
+ * @mode_set: set this mode, optional for atomic helpers
  * @get_crtc: return CRTC that the encoder is currently attached to
  * @detect: connection status detection
  * @disable: disable encoder when not in use (overrides DPMS off)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 7e25030a6aa2..d4803224028f 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -92,6 +92,9 @@
 # define DP_MSA_TIMING_PAR_IGNORED          (1 << 6) /* eDP */
 # define DP_OUI_SUPPORT                     (1 << 7)
 
+#define DP_SUPPORTED_LINK_RATES                 0x010 /*eDP 1.4*/
+#define DP_MAX_SUPPORTED_RATES                  0x8
+
 #define DP_I2C_SPEED_CAP                    0x00c    /* DPI */
 # define DP_I2C_SPEED_1K                    0x01
 # define DP_I2C_SPEED_5K                    0x02
@@ -101,6 +104,7 @@
 # define DP_I2C_SPEED_1M                    0x20
 
 #define DP_EDP_CONFIGURATION_CAP            0x00d   /* XXX 1.2? */
+# define DP_DPCD_DISPLAY_CONTROL_CAPABLE     (1 << 3) /* edp v1.2 or higher */
 #define DP_TRAINING_AUX_RD_INTERVAL         0x00e   /* XXX 1.2? */
 
 /* Multiple stream transport */
@@ -221,6 +225,8 @@
 # define DP_UP_REQ_EN                       (1 << 1)
 # define DP_UPSTREAM_IS_SRC                 (1 << 2)
 
+#define DP_LINK_RATE_SET                        0x115
+
 #define DP_PSR_EN_CFG                       0x170   /* XXX 1.2? */
 # define DP_PSR_ENABLE                      (1 << 0)
 # define DP_PSR_MAIN_LINK_ACTIVE            (1 << 1)
@@ -332,6 +338,8 @@
 # define DP_SET_POWER_D3                    0x2
 # define DP_SET_POWER_MASK                  0x3
 
+#define DP_EDP_DPCD_REV                          0x700
+
 #define DP_SIDEBAND_MSG_DOWN_REQ_BASE       0x1000   /* 1.2 MST */
 #define DP_SIDEBAND_MSG_UP_REP_BASE         0x1200   /* 1.2 MST */
 #define DP_SIDEBAND_MSG_DOWN_REP_BASE       0x1400   /* 1.2 MST */
diff --git a/include/drm/drm_modes.h b/include/drm/drm_modes.h
index d92f6dd1fb11..0616188c7801 100644
--- a/include/drm/drm_modes.h
+++ b/include/drm/drm_modes.h
@@ -92,7 +92,7 @@ enum drm_mode_status {
 #define CRTC_STEREO_DOUBLE      (1 << 1) /* adjust timings for stereo modes */
 #define CRTC_NO_DBLSCAN         (1 << 2) /* don't adjust doublescan */
 #define CRTC_NO_VSCAN           (1 << 3) /* don't adjust doublescan */
-#define CRTC_STEREO_DOUBLE_ONLY (CRTC_NO_DBLSCAN | CRTC_NO_VSCAN)
+#define CRTC_STEREO_DOUBLE_ONLY (CRTC_STEREO_DOUBLE | CRTC_NO_DBLSCAN | CRTC_NO_VSCAN)
 
 #define DRM_MODE_FLAG_3D_MAX    DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF
 
diff --git a/include/drm/drm_plane_helper.h b/include/drm/drm_plane_helper.h
index 31c11d36fae6..72ddab02ebd9 100644
--- a/include/drm/drm_plane_helper.h
+++ b/include/drm/drm_plane_helper.h
@@ -59,9 +59,11 @@ extern int drm_crtc_init(struct drm_device *dev,
  */
 struct drm_plane_helper_funcs {
         int (*prepare_fb)(struct drm_plane *plane,
-                          struct drm_framebuffer *fb);
+                          struct drm_framebuffer *fb,
+                          const struct drm_plane_state *new_state);
         void (*cleanup_fb)(struct drm_plane *plane,
-                           struct drm_framebuffer *fb);
+                           struct drm_framebuffer *fb,
+                           const struct drm_plane_state *old_state);
 
         int (*atomic_check)(struct drm_plane *plane,
                             struct drm_plane_state *state);
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index d016dc57f007..f2e47fd56751 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -259,21 +259,31 @@
         INTEL_VGA_DEVICE(0x22b2, info), \
         INTEL_VGA_DEVICE(0x22b3, info)
 
-#define INTEL_SKL_IDS(info) \
-        INTEL_VGA_DEVICE(0x1916, info), /* ULT GT2 */ \
+#define INTEL_SKL_GT1_IDS(info) \
         INTEL_VGA_DEVICE(0x1906, info), /* ULT GT1 */ \
-        INTEL_VGA_DEVICE(0x1926, info), /* ULT GT3 */ \
-        INTEL_VGA_DEVICE(0x1921, info), /* ULT GT2F */ \
         INTEL_VGA_DEVICE(0x190E, info), /* ULX GT1 */ \
+        INTEL_VGA_DEVICE(0x1902, info), /* DT  GT1 */ \
+        INTEL_VGA_DEVICE(0x190B, info), /* Halo GT1 */ \
+        INTEL_VGA_DEVICE(0x190A, info) /* SRV GT1 */
+
+#define INTEL_SKL_GT2_IDS(info) \
+        INTEL_VGA_DEVICE(0x1916, info), /* ULT GT2 */ \
+        INTEL_VGA_DEVICE(0x1921, info), /* ULT GT2F */ \
         INTEL_VGA_DEVICE(0x191E, info), /* ULX GT2 */ \
         INTEL_VGA_DEVICE(0x1912, info), /* DT  GT2 */ \
-        INTEL_VGA_DEVICE(0x1902, info), /* DT  GT1 */ \
         INTEL_VGA_DEVICE(0x191B, info), /* Halo GT2 */ \
-        INTEL_VGA_DEVICE(0x192B, info), /* Halo GT3 */ \
-        INTEL_VGA_DEVICE(0x190B, info), /* Halo GT1 */ \
         INTEL_VGA_DEVICE(0x191A, info), /* SRV GT2 */ \
-        INTEL_VGA_DEVICE(0x192A, info), /* SRV GT3 */ \
-        INTEL_VGA_DEVICE(0x190A, info), /* SRV GT1 */ \
         INTEL_VGA_DEVICE(0x191D, info)  /* WKS GT2 */
 
+#define INTEL_SKL_GT3_IDS(info) \
+        INTEL_VGA_DEVICE(0x1926, info), /* ULT GT3 */ \
+        INTEL_VGA_DEVICE(0x192B, info), /* Halo GT3 */ \
+        INTEL_VGA_DEVICE(0x192A, info) /* SRV GT3 */ \
+
+#define INTEL_SKL_IDS(info) \
+        INTEL_SKL_GT1_IDS(info), \
+        INTEL_SKL_GT2_IDS(info), \
+        INTEL_SKL_GT3_IDS(info)
+
+
 #endif /* _I915_PCIIDS_H */
diff --git a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h
index 01b2d6d0e355..ff6ef62d084b 100644
--- a/include/uapi/drm/drm.h
+++ b/include/uapi/drm/drm.h
@@ -630,6 +630,7 @@ struct drm_gem_open {
  */
 #define DRM_CAP_CURSOR_WIDTH            0x8
 #define DRM_CAP_CURSOR_HEIGHT           0x9
+#define DRM_CAP_ADDFB2_MODIFIERS        0x10
 
 /** DRM_IOCTL_GET_CAP ioctl argument type */
 struct drm_get_cap {
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index a284f11a8ef5..e6efac23c7ea 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -129,4 +129,82 @@
 #define DRM_FORMAT_YUV444       fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */
 #define DRM_FORMAT_YVU444       fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */
 
+
+/*
+ * Format Modifiers:
+ *
+ * Format modifiers describe, typically, a re-ordering or modification
+ * of the data in a plane of an FB.  This can be used to express tiled/
+ * swizzled formats, or compression, or a combination of the two.
+ *
+ * The upper 8 bits of the format modifier are a vendor-id as assigned
+ * below.  The lower 56 bits are assigned as vendor sees fit.
+ */
+
+/* Vendor Ids: */
+#define DRM_FORMAT_MOD_NONE           0
+#define DRM_FORMAT_MOD_VENDOR_INTEL   0x01
+#define DRM_FORMAT_MOD_VENDOR_AMD     0x02
+#define DRM_FORMAT_MOD_VENDOR_NV      0x03
+#define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04
+#define DRM_FORMAT_MOD_VENDOR_QCOM    0x05
+/* add more to the end as needed */
+
+#define fourcc_mod_code(vendor, val) \
+        ((((u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | (val & 0x00ffffffffffffffL))
+
+/*
+ * Format Modifier tokens:
+ *
+ * When adding a new token please document the layout with a code comment,
+ * similar to the fourcc codes above. drm_fourcc.h is considered the
+ * authoritative source for all of these.
+ */
+
+/* Intel framebuffer modifiers */
+
+/*
+ * Intel X-tiling layout
+ *
+ * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
+ * in row-major layout. Within the tile bytes are laid out row-major, with
+ * a platform-dependent stride. On top of that the memory can apply
+ * platform-depending swizzling of some higher address bits into bit6.
+ *
+ * This format is highly platforms specific and not useful for cross-driver
+ * sharing. It exists since on a given platform it does uniquely identify the
+ * layout in a simple way for i915-specific userspace.
+ */
+#define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1)
+
+/*
+ * Intel Y-tiling layout
+ *
+ * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
+ * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes)
+ * chunks column-major, with a platform-dependent height. On top of that the
+ * memory can apply platform-depending swizzling of some higher address bits
+ * into bit6.
+ *
+ * This format is highly platforms specific and not useful for cross-driver
+ * sharing. It exists since on a given platform it does uniquely identify the
+ * layout in a simple way for i915-specific userspace.
+ */
+#define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2)
+
+/*
+ * Intel Yf-tiling layout
+ *
+ * This is a tiled layout using 4Kb tiles in row-major layout.
+ * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which
+ * are arranged in four groups (two wide, two high) with column-major layout.
+ * Each group therefore consits out of four 256 byte units, which are also laid
+ * out as 2x2 column-major.
+ * 256 byte units are made out of four 64 byte blocks of pixels, producing
+ * either a square block or a 2:1 unit.
+ * 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width
+ * in pixel depends on the pixel depth.
+ */
+#define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3)
+
 #endif /* DRM_FOURCC_H */
diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index ca788e01dab2..dbeba949462a 100644
--- a/include/uapi/drm/drm_mode.h
+++ b/include/uapi/drm/drm_mode.h
@@ -336,6 +336,7 @@ struct drm_mode_fb_cmd {
 };
 
 #define DRM_MODE_FB_INTERLACED  (1<<0) /* for interlaced framebuffers */
+#define DRM_MODE_FB_MODIFIERS   (1<<1) /* enables ->modifer[] */
 
 struct drm_mode_fb_cmd2 {
         __u32 fb_id;
@@ -356,10 +357,18 @@ struct drm_mode_fb_cmd2 {
          * So it would consist of Y as offsets[0] and UV as
          * offsets[1].  Note that offsets[0] will generally
          * be 0 (but this is not required).
+         *
+         * To accommodate tiled, compressed, etc formats, a per-plane
+         * modifier can be specified.  The default value of zero
+         * indicates "native" format as specified by the fourcc.
+         * Vendor specific modifier token.  This allows, for example,
+         * different tiling/swizzling pattern on different planes.
+         * See discussion above of DRM_FORMAT_MOD_xxx.
          */
         __u32 handles[4];
         __u32 pitches[4]; /* pitch for each plane */
         __u32 offsets[4]; /* offset of each plane */
+        __u64 modifier[4]; /* ie, tiling, compressed (per plane) */
 };
 
 #define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01