diff options
169 files changed, 8814 insertions, 3129 deletions
diff --git a/Documentation/devicetree/bindings/arm/atmel-aic.txt b/Documentation/devicetree/bindings/arm/atmel-aic.txt index ad031211b5b8..2742e9cfd6b1 100644 --- a/Documentation/devicetree/bindings/arm/atmel-aic.txt +++ b/Documentation/devicetree/bindings/arm/atmel-aic.txt | |||
| @@ -2,6 +2,7 @@ | |||
| 2 | 2 | ||
| 3 | Required properties: | 3 | Required properties: |
| 4 | - compatible: Should be "atmel,<chip>-aic" | 4 | - compatible: Should be "atmel,<chip>-aic" |
| 5 | <chip> can be "at91rm9200" or "sama5d3" | ||
| 5 | - interrupt-controller: Identifies the node as an interrupt controller. | 6 | - interrupt-controller: Identifies the node as an interrupt controller. |
| 6 | - interrupt-parent: For single AIC system, it is an empty property. | 7 | - interrupt-parent: For single AIC system, it is an empty property. |
| 7 | - #interrupt-cells: The number of cells to define the interrupts. It should be 3. | 8 | - #interrupt-cells: The number of cells to define the interrupts. It should be 3. |
diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.txt b/Documentation/devicetree/bindings/arm/atmel-at91.txt index 1196290082d1..d2170e780f0b 100644 --- a/Documentation/devicetree/bindings/arm/atmel-at91.txt +++ b/Documentation/devicetree/bindings/arm/atmel-at91.txt | |||
| @@ -50,7 +50,8 @@ Example: | |||
| 50 | }; | 50 | }; |
| 51 | 51 | ||
| 52 | RAMC SDRAM/DDR Controller required properties: | 52 | RAMC SDRAM/DDR Controller required properties: |
| 53 | - compatible: Should be "atmel,at91sam9260-sdramc", | 53 | - compatible: Should be "atmel,at91rm9200-sdramc", |
| 54 | "atmel,at91sam9260-sdramc", | ||
| 54 | "atmel,at91sam9g45-ddramc", | 55 | "atmel,at91sam9g45-ddramc", |
| 55 | - reg: Should contain registers location and length | 56 | - reg: Should contain registers location and length |
| 56 | For at91sam9263 and at91sam9g45 you must specify 2 entries. | 57 | For at91sam9263 and at91sam9g45 you must specify 2 entries. |
diff --git a/Documentation/devicetree/bindings/arm/firmware/tlm,trusted-foundations.txt b/Documentation/devicetree/bindings/arm/firmware/tlm,trusted-foundations.txt new file mode 100644 index 000000000000..780d0392a66b --- /dev/null +++ b/Documentation/devicetree/bindings/arm/firmware/tlm,trusted-foundations.txt | |||
| @@ -0,0 +1,20 @@ | |||
| 1 | Trusted Foundations | ||
| 2 | ------------------- | ||
| 3 | |||
| 4 | Boards that use the Trusted Foundations secure monitor can signal its | ||
| 5 | presence by declaring a node compatible with "tlm,trusted-foundations" | ||
| 6 | under the /firmware/ node | ||
| 7 | |||
| 8 | Required properties: | ||
| 9 | - compatible: "tlm,trusted-foundations" | ||
| 10 | - tlm,version-major: major version number of Trusted Foundations firmware | ||
| 11 | - tlm,version-minor: minor version number of Trusted Foundations firmware | ||
| 12 | |||
| 13 | Example: | ||
| 14 | firmware { | ||
| 15 | trusted-foundations { | ||
| 16 | compatible = "tlm,trusted-foundations"; | ||
| 17 | tlm,version-major = <2>; | ||
| 18 | tlm,version-minor = <8>; | ||
| 19 | }; | ||
| 20 | }; | ||
diff --git a/Documentation/devicetree/bindings/arm/tegra.txt b/Documentation/devicetree/bindings/arm/tegra.txt index ed9c85334436..558ed4b4ef39 100644 --- a/Documentation/devicetree/bindings/arm/tegra.txt +++ b/Documentation/devicetree/bindings/arm/tegra.txt | |||
| @@ -32,3 +32,8 @@ board-specific compatible values: | |||
| 32 | nvidia,whistler | 32 | nvidia,whistler |
| 33 | toradex,colibri_t20-512 | 33 | toradex,colibri_t20-512 |
| 34 | toradex,iris | 34 | toradex,iris |
| 35 | |||
| 36 | Trusted Foundations | ||
| 37 | ------------------------------------------- | ||
| 38 | Tegra supports the Trusted Foundation secure monitor. See the | ||
| 39 | "tlm,trusted-foundations" binding's documentation for more details. | ||
diff --git a/Documentation/devicetree/bindings/clock/at91-clock.txt b/Documentation/devicetree/bindings/clock/at91-clock.txt new file mode 100644 index 000000000000..cd5e23912888 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/at91-clock.txt | |||
| @@ -0,0 +1,339 @@ | |||
| 1 | Device Tree Clock bindings for arch-at91 | ||
| 2 | |||
| 3 | This binding uses the common clock binding[1]. | ||
| 4 | |||
| 5 | [1] Documentation/devicetree/bindings/clock/clock-bindings.txt | ||
| 6 | |||
| 7 | Required properties: | ||
| 8 | - compatible : shall be one of the following: | ||
| 9 | "atmel,at91rm9200-pmc" or | ||
| 10 | "atmel,at91sam9g45-pmc" or | ||
| 11 | "atmel,at91sam9n12-pmc" or | ||
| 12 | "atmel,at91sam9x5-pmc" or | ||
| 13 | "atmel,sama5d3-pmc": | ||
| 14 | at91 PMC (Power Management Controller) | ||
| 15 | All at91 specific clocks (clocks defined below) must be child | ||
| 16 | node of the PMC node. | ||
| 17 | |||
| 18 | "atmel,at91rm9200-clk-main": | ||
| 19 | at91 main oscillator | ||
| 20 | |||
| 21 | "atmel,at91rm9200-clk-master" or | ||
| 22 | "atmel,at91sam9x5-clk-master": | ||
| 23 | at91 master clock | ||
| 24 | |||
| 25 | "atmel,at91sam9x5-clk-peripheral" or | ||
| 26 | "atmel,at91rm9200-clk-peripheral": | ||
| 27 | at91 peripheral clocks | ||
| 28 | |||
| 29 | "atmel,at91rm9200-clk-pll" or | ||
| 30 | "atmel,at91sam9g45-clk-pll" or | ||
| 31 | "atmel,at91sam9g20-clk-pllb" or | ||
| 32 | "atmel,sama5d3-clk-pll": | ||
| 33 | at91 pll clocks | ||
| 34 | |||
| 35 | "atmel,at91sam9x5-clk-plldiv": | ||
| 36 | at91 plla divisor | ||
| 37 | |||
| 38 | "atmel,at91rm9200-clk-programmable" or | ||
| 39 | "atmel,at91sam9g45-clk-programmable" or | ||
| 40 | "atmel,at91sam9x5-clk-programmable": | ||
| 41 | at91 programmable clocks | ||
| 42 | |||
| 43 | "atmel,at91sam9x5-clk-smd": | ||
| 44 | at91 SMD (Soft Modem) clock | ||
| 45 | |||
| 46 | "atmel,at91rm9200-clk-system": | ||
| 47 | at91 system clocks | ||
| 48 | |||
| 49 | "atmel,at91rm9200-clk-usb" or | ||
| 50 | "atmel,at91sam9x5-clk-usb" or | ||
| 51 | "atmel,at91sam9n12-clk-usb": | ||
| 52 | at91 usb clock | ||
| 53 | |||
| 54 | "atmel,at91sam9x5-clk-utmi": | ||
| 55 | at91 utmi clock | ||
| 56 | |||
| 57 | Required properties for PMC node: | ||
| 58 | - reg : defines the IO memory reserved for the PMC. | ||
| 59 | - #size-cells : shall be 0 (reg is used to encode clk id). | ||
| 60 | - #address-cells : shall be 1 (reg is used to encode clk id). | ||
| 61 | - interrupts : shall be set to PMC interrupt line. | ||
| 62 | - interrupt-controller : tell that the PMC is an interrupt controller. | ||
| 63 | - #interrupt-cells : must be set to 1. The first cell encodes the interrupt id, | ||
| 64 | and reflect the bit position in the PMC_ER/DR/SR registers. | ||
| 65 | You can use the dt macros defined in dt-bindings/clk/at91.h. | ||
| 66 | 0 (AT91_PMC_MOSCS) -> main oscillator ready | ||
| 67 | 1 (AT91_PMC_LOCKA) -> PLL A ready | ||
| 68 | 2 (AT91_PMC_LOCKB) -> PLL B ready | ||
| 69 | 3 (AT91_PMC_MCKRDY) -> master clock ready | ||
| 70 | 6 (AT91_PMC_LOCKU) -> UTMI PLL clock ready | ||
| 71 | 8 .. 15 (AT91_PMC_PCKRDY(id)) -> programmable clock ready | ||
| 72 | 16 (AT91_PMC_MOSCSELS) -> main oscillator selected | ||
| 73 | 17 (AT91_PMC_MOSCRCS) -> RC main oscillator stabilized | ||
| 74 | 18 (AT91_PMC_CFDEV) -> clock failure detected | ||
| 75 | |||
| 76 | For example: | ||
| 77 | pmc: pmc@fffffc00 { | ||
| 78 | compatible = "atmel,sama5d3-pmc"; | ||
| 79 | interrupts = <1 4 7>; | ||
| 80 | interrupt-controller; | ||
| 81 | #interrupt-cells = <2>; | ||
| 82 | #size-cells = <0>; | ||
| 83 | #address-cells = <1>; | ||
| 84 | |||
| 85 | /* put at91 clocks here */ | ||
| 86 | }; | ||
| 87 | |||
| 88 | Required properties for main clock: | ||
| 89 | - interrupt-parent : must reference the PMC node. | ||
| 90 | - interrupts : shall be set to "<0>". | ||
| 91 | - #clock-cells : from common clock binding; shall be set to 0. | ||
| 92 | - clocks (optional if clock-frequency is provided) : shall be the slow clock | ||
| 93 | phandle. This clock is used to calculate the main clock rate if | ||
| 94 | "clock-frequency" is not provided. | ||
| 95 | - clock-frequency : the main oscillator frequency.Prefer the use of | ||
| 96 | "clock-frequency" over automatic clock rate calculation. | ||
| 97 | |||
| 98 | For example: | ||
| 99 | main: mainck { | ||
| 100 | compatible = "atmel,at91rm9200-clk-main"; | ||
| 101 | interrupt-parent = <&pmc>; | ||
| 102 | interrupts = <0>; | ||
| 103 | #clock-cells = <0>; | ||
| 104 | clocks = <&ck32k>; | ||
| 105 | clock-frequency = <18432000>; | ||
| 106 | }; | ||
| 107 | |||
| 108 | Required properties for master clock: | ||
| 109 | - interrupt-parent : must reference the PMC node. | ||
| 110 | - interrupts : shall be set to "<3>". | ||
| 111 | - #clock-cells : from common clock binding; shall be set to 0. | ||
| 112 | - clocks : shall be the master clock sources (see atmel datasheet) phandles. | ||
| 113 | e.g. "<&ck32k>, <&main>, <&plla>, <&pllb>". | ||
| 114 | - atmel,clk-output-range : minimum and maximum clock frequency (two u32 | ||
| 115 | fields). | ||
| 116 | e.g. output = <0 133000000>; <=> 0 to 133MHz. | ||
| 117 | - atmel,clk-divisors : master clock divisors table (four u32 fields). | ||
| 118 | 0 <=> reserved value. | ||
| 119 | e.g. divisors = <1 2 4 6>; | ||
| 120 | - atmel,master-clk-have-div3-pres : some SoC use the reserved value 7 in the | ||
| 121 | PRES field as CLOCK_DIV3 (e.g sam9x5). | ||
| 122 | |||
| 123 | For example: | ||
| 124 | mck: mck { | ||
| 125 | compatible = "atmel,at91rm9200-clk-master"; | ||
| 126 | interrupt-parent = <&pmc>; | ||
| 127 | interrupts = <3>; | ||
| 128 | #clock-cells = <0>; | ||
| 129 | atmel,clk-output-range = <0 133000000>; | ||
| 130 | atmel,clk-divisors = <1 2 4 0>; | ||
| 131 | }; | ||
| 132 | |||
| 133 | Required properties for peripheral clocks: | ||
| 134 | - #size-cells : shall be 0 (reg is used to encode clk id). | ||
| 135 | - #address-cells : shall be 1 (reg is used to encode clk id). | ||
| 136 | - clocks : shall be the master clock phandle. | ||
| 137 | e.g. clocks = <&mck>; | ||
| 138 | - name: device tree node describing a specific system clock. | ||
| 139 | * #clock-cells : from common clock binding; shall be set to 0. | ||
| 140 | * reg: peripheral id. See Atmel's datasheets to get a full | ||
| 141 | list of peripheral ids. | ||
| 142 | * atmel,clk-output-range : minimum and maximum clock frequency | ||
| 143 | (two u32 fields). Only valid on at91sam9x5-clk-peripheral | ||
| 144 | compatible IPs. | ||
| 145 | |||
| 146 | For example: | ||
| 147 | periph: periphck { | ||
| 148 | compatible = "atmel,at91sam9x5-clk-peripheral"; | ||
| 149 | #size-cells = <0>; | ||
| 150 | #address-cells = <1>; | ||
| 151 | clocks = <&mck>; | ||
| 152 | |||
| 153 | ssc0_clk { | ||
| 154 | #clock-cells = <0>; | ||
| 155 | reg = <2>; | ||
| 156 | atmel,clk-output-range = <0 133000000>; | ||
| 157 | }; | ||
| 158 | |||
| 159 | usart0_clk { | ||
| 160 | #clock-cells = <0>; | ||
| 161 | reg = <3>; | ||
| 162 | atmel,clk-output-range = <0 66000000>; | ||
| 163 | }; | ||
| 164 | }; | ||
| 165 | |||
| 166 | |||
| 167 | Required properties for pll clocks: | ||
| 168 | - interrupt-parent : must reference the PMC node. | ||
| 169 | - interrupts : shall be set to "<1>". | ||
| 170 | - #clock-cells : from common clock binding; shall be set to 0. | ||
| 171 | - clocks : shall be the main clock phandle. | ||
| 172 | - reg : pll id. | ||
| 173 | 0 -> PLL A | ||
| 174 | 1 -> PLL B | ||
| 175 | - atmel,clk-input-range : minimum and maximum source clock frequency (two u32 | ||
| 176 | fields). | ||
| 177 | e.g. input = <1 32000000>; <=> 1 to 32MHz. | ||
| 178 | - #atmel,pll-clk-output-range-cells : number of cells reserved for pll output | ||
| 179 | range description. Sould be set to 2, 3 | ||
| 180 | or 4. | ||
| 181 | * 1st and 2nd cells represent the frequency range (min-max). | ||
| 182 | * 3rd cell is optional and represents the OUT field value for the given | ||
| 183 | range. | ||
| 184 | * 4th cell is optional and represents the ICPLL field (PLLICPR | ||
| 185 | register) | ||
| 186 | - atmel,pll-clk-output-ranges : pll output frequency ranges + optional parameter | ||
| 187 | depending on #atmel,pll-output-range-cells | ||
| 188 | property value. | ||
| 189 | |||
| 190 | For example: | ||
| 191 | plla: pllack { | ||
| 192 | compatible = "atmel,at91sam9g45-clk-pll"; | ||
| 193 | interrupt-parent = <&pmc>; | ||
| 194 | interrupts = <1>; | ||
| 195 | #clock-cells = <0>; | ||
| 196 | clocks = <&main>; | ||
| 197 | reg = <0>; | ||
| 198 | atmel,clk-input-range = <2000000 32000000>; | ||
| 199 | #atmel,pll-clk-output-range-cells = <4>; | ||
| 200 | atmel,pll-clk-output-ranges = <74500000 800000000 0 0 | ||
| 201 | 69500000 750000000 1 0 | ||
| 202 | 64500000 700000000 2 0 | ||
| 203 | 59500000 650000000 3 0 | ||
| 204 | 54500000 600000000 0 1 | ||
| 205 | 49500000 550000000 1 1 | ||
| 206 | 44500000 500000000 2 1 | ||
| 207 | 40000000 450000000 3 1>; | ||
| 208 | }; | ||
| 209 | |||
| 210 | Required properties for plldiv clocks (plldiv = pll / 2): | ||
| 211 | - #clock-cells : from common clock binding; shall be set to 0. | ||
| 212 | - clocks : shall be the plla clock phandle. | ||
| 213 | |||
| 214 | The pll divisor is equal to 2 and cannot be changed. | ||
| 215 | |||
| 216 | For example: | ||
| 217 | plladiv: plladivck { | ||
| 218 | compatible = "atmel,at91sam9x5-clk-plldiv"; | ||
| 219 | #clock-cells = <0>; | ||
| 220 | clocks = <&plla>; | ||
| 221 | }; | ||
| 222 | |||
| 223 | Required properties for programmable clocks: | ||
| 224 | - interrupt-parent : must reference the PMC node. | ||
| 225 | - #size-cells : shall be 0 (reg is used to encode clk id). | ||
| 226 | - #address-cells : shall be 1 (reg is used to encode clk id). | ||
| 227 | - clocks : shall be the programmable clock source phandles. | ||
| 228 | e.g. clocks = <&clk32k>, <&main>, <&plla>, <&pllb>; | ||
| 229 | - name: device tree node describing a specific prog clock. | ||
| 230 | * #clock-cells : from common clock binding; shall be set to 0. | ||
| 231 | * reg : programmable clock id (register offset from PCKx | ||
| 232 | register). | ||
| 233 | * interrupts : shall be set to "<(8 + id)>". | ||
| 234 | |||
| 235 | For example: | ||
| 236 | prog: progck { | ||
| 237 | compatible = "atmel,at91sam9g45-clk-programmable"; | ||
| 238 | #size-cells = <0>; | ||
| 239 | #address-cells = <1>; | ||
| 240 | interrupt-parent = <&pmc>; | ||
| 241 | clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; | ||
| 242 | |||
| 243 | prog0 { | ||
| 244 | #clock-cells = <0>; | ||
| 245 | reg = <0>; | ||
| 246 | interrupts = <8>; | ||
| 247 | }; | ||
| 248 | |||
| 249 | prog1 { | ||
| 250 | #clock-cells = <0>; | ||
| 251 | reg = <1>; | ||
| 252 | interrupts = <9>; | ||
| 253 | }; | ||
| 254 | }; | ||
| 255 | |||
| 256 | |||
| 257 | Required properties for smd clock: | ||
| 258 | - #clock-cells : from common clock binding; shall be set to 0. | ||
| 259 | - clocks : shall be the smd clock source phandles. | ||
| 260 | e.g. clocks = <&plladiv>, <&utmi>; | ||
| 261 | |||
| 262 | For example: | ||
| 263 | smd: smdck { | ||
| 264 | compatible = "atmel,at91sam9x5-clk-smd"; | ||
| 265 | #clock-cells = <0>; | ||
| 266 | clocks = <&plladiv>, <&utmi>; | ||
| 267 | }; | ||
| 268 | |||
| 269 | Required properties for system clocks: | ||
| 270 | - #size-cells : shall be 0 (reg is used to encode clk id). | ||
| 271 | - #address-cells : shall be 1 (reg is used to encode clk id). | ||
| 272 | - name: device tree node describing a specific system clock. | ||
| 273 | * #clock-cells : from common clock binding; shall be set to 0. | ||
| 274 | * reg: system clock id (bit position in SCER/SCDR/SCSR registers). | ||
| 275 | See Atmel's datasheet to get a full list of system clock ids. | ||
| 276 | |||
| 277 | For example: | ||
| 278 | system: systemck { | ||
| 279 | compatible = "atmel,at91rm9200-clk-system"; | ||
| 280 | #address-cells = <1>; | ||
| 281 | #size-cells = <0>; | ||
| 282 | |||
| 283 | ddrck { | ||
| 284 | #clock-cells = <0>; | ||
| 285 | reg = <2>; | ||
| 286 | clocks = <&mck>; | ||
| 287 | }; | ||
| 288 | |||
| 289 | uhpck { | ||
| 290 | #clock-cells = <0>; | ||
| 291 | reg = <6>; | ||
| 292 | clocks = <&usb>; | ||
| 293 | }; | ||
| 294 | |||
| 295 | udpck { | ||
| 296 | #clock-cells = <0>; | ||
| 297 | reg = <7>; | ||
| 298 | clocks = <&usb>; | ||
| 299 | }; | ||
| 300 | }; | ||
| 301 | |||
| 302 | |||
| 303 | Required properties for usb clock: | ||
| 304 | - #clock-cells : from common clock binding; shall be set to 0. | ||
| 305 | - clocks : shall be the smd clock source phandles. | ||
| 306 | e.g. clocks = <&pllb>; | ||
| 307 | - atmel,clk-divisors (only available for "atmel,at91rm9200-clk-usb"): | ||
| 308 | usb clock divisor table. | ||
| 309 | e.g. divisors = <1 2 4 0>; | ||
| 310 | |||
| 311 | For example: | ||
| 312 | usb: usbck { | ||
| 313 | compatible = "atmel,at91sam9x5-clk-usb"; | ||
| 314 | #clock-cells = <0>; | ||
| 315 | clocks = <&plladiv>, <&utmi>; | ||
| 316 | }; | ||
| 317 | |||
| 318 | usb: usbck { | ||
| 319 | compatible = "atmel,at91rm9200-clk-usb"; | ||
| 320 | #clock-cells = <0>; | ||
| 321 | clocks = <&pllb>; | ||
| 322 | atmel,clk-divisors = <1 2 4 0>; | ||
| 323 | }; | ||
| 324 | |||
| 325 | |||
| 326 | Required properties for utmi clock: | ||
| 327 | - interrupt-parent : must reference the PMC node. | ||
| 328 | - interrupts : shall be set to "<AT91_PMC_LOCKU IRQ_TYPE_LEVEL_HIGH>". | ||
| 329 | - #clock-cells : from common clock binding; shall be set to 0. | ||
| 330 | - clocks : shall be the main clock source phandle. | ||
| 331 | |||
| 332 | For example: | ||
| 333 | utmi: utmick { | ||
| 334 | compatible = "atmel,at91sam9x5-clk-utmi"; | ||
| 335 | interrupt-parent = <&pmc>; | ||
| 336 | interrupts = <AT91_PMC_LOCKU IRQ_TYPE_LEVEL_HIGH>; | ||
| 337 | #clock-cells = <0>; | ||
| 338 | clocks = <&main>; | ||
| 339 | }; | ||
diff --git a/Documentation/devicetree/bindings/crypto/atmel-crypto.txt b/Documentation/devicetree/bindings/crypto/atmel-crypto.txt new file mode 100644 index 000000000000..f2aab3dc2b52 --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/atmel-crypto.txt | |||
| @@ -0,0 +1,68 @@ | |||
| 1 | * Atmel HW cryptographic accelerators | ||
| 2 | |||
| 3 | These are the HW cryptographic accelerators found on some Atmel products. | ||
| 4 | |||
| 5 | * Advanced Encryption Standard (AES) | ||
| 6 | |||
| 7 | Required properties: | ||
| 8 | - compatible : Should be "atmel,at91sam9g46-aes". | ||
| 9 | - reg: Should contain AES registers location and length. | ||
| 10 | - interrupts: Should contain the IRQ line for the AES. | ||
| 11 | - dmas: List of two DMA specifiers as described in | ||
| 12 | atmel-dma.txt and dma.txt files. | ||
| 13 | - dma-names: Contains one identifier string for each DMA specifier | ||
| 14 | in the dmas property. | ||
| 15 | |||
| 16 | Example: | ||
| 17 | aes@f8038000 { | ||
| 18 | compatible = "atmel,at91sam9g46-aes"; | ||
| 19 | reg = <0xf8038000 0x100>; | ||
| 20 | interrupts = <43 4 0>; | ||
| 21 | dmas = <&dma1 2 18>, | ||
| 22 | <&dma1 2 19>; | ||
| 23 | dma-names = "tx", "rx"; | ||
| 24 | |||
| 25 | * Triple Data Encryption Standard (Triple DES) | ||
| 26 | |||
| 27 | Required properties: | ||
| 28 | - compatible : Should be "atmel,at91sam9g46-tdes". | ||
| 29 | - reg: Should contain TDES registers location and length. | ||
| 30 | - interrupts: Should contain the IRQ line for the TDES. | ||
| 31 | |||
| 32 | Optional properties: | ||
| 33 | - dmas: List of two DMA specifiers as described in | ||
| 34 | atmel-dma.txt and dma.txt files. | ||
| 35 | - dma-names: Contains one identifier string for each DMA specifier | ||
| 36 | in the dmas property. | ||
| 37 | |||
| 38 | Example: | ||
| 39 | tdes@f803c000 { | ||
| 40 | compatible = "atmel,at91sam9g46-tdes"; | ||
| 41 | reg = <0xf803c000 0x100>; | ||
| 42 | interrupts = <44 4 0>; | ||
| 43 | dmas = <&dma1 2 20>, | ||
| 44 | <&dma1 2 21>; | ||
| 45 | dma-names = "tx", "rx"; | ||
| 46 | }; | ||
| 47 | |||
| 48 | * Secure Hash Algorithm (SHA) | ||
| 49 | |||
| 50 | Required properties: | ||
| 51 | - compatible : Should be "atmel,at91sam9g46-sha". | ||
| 52 | - reg: Should contain SHA registers location and length. | ||
| 53 | - interrupts: Should contain the IRQ line for the SHA. | ||
| 54 | |||
| 55 | Optional properties: | ||
| 56 | - dmas: One DMA specifiers as described in | ||
| 57 | atmel-dma.txt and dma.txt files. | ||
| 58 | - dma-names: Contains one identifier string for each DMA specifier | ||
| 59 | in the dmas property. Only one "tx" string needed. | ||
| 60 | |||
| 61 | Example: | ||
| 62 | sha@f8034000 { | ||
| 63 | compatible = "atmel,at91sam9g46-sha"; | ||
| 64 | reg = <0xf8034000 0x100>; | ||
| 65 | interrupts = <42 4 0>; | ||
| 66 | dmas = <&dma1 2 17>; | ||
| 67 | dma-names = "tx"; | ||
| 68 | }; | ||
diff --git a/Documentation/devicetree/bindings/i2c/trivial-devices.txt b/Documentation/devicetree/bindings/i2c/trivial-devices.txt index b1cb3415e6f1..cdf14308ed92 100644 --- a/Documentation/devicetree/bindings/i2c/trivial-devices.txt +++ b/Documentation/devicetree/bindings/i2c/trivial-devices.txt | |||
| @@ -39,6 +39,7 @@ fsl,sgtl5000 SGTL5000: Ultra Low-Power Audio Codec | |||
| 39 | gmt,g751 G751: Digital Temperature Sensor and Thermal Watchdog with Two-Wire Interface | 39 | gmt,g751 G751: Digital Temperature Sensor and Thermal Watchdog with Two-Wire Interface |
| 40 | infineon,slb9635tt Infineon SLB9635 (Soft-) I2C TPM (old protocol, max 100khz) | 40 | infineon,slb9635tt Infineon SLB9635 (Soft-) I2C TPM (old protocol, max 100khz) |
| 41 | infineon,slb9645tt Infineon SLB9645 I2C TPM (new protocol, max 400khz) | 41 | infineon,slb9645tt Infineon SLB9645 I2C TPM (new protocol, max 400khz) |
| 42 | isl,isl12057 Intersil ISL12057 I2C RTC Chip | ||
| 42 | maxim,ds1050 5 Bit Programmable, Pulse-Width Modulator | 43 | maxim,ds1050 5 Bit Programmable, Pulse-Width Modulator |
| 43 | maxim,max1237 Low-Power, 4-/12-Channel, 2-Wire Serial, 12-Bit ADCs | 44 | maxim,max1237 Low-Power, 4-/12-Channel, 2-Wire Serial, 12-Bit ADCs |
| 44 | maxim,max6625 9-Bit/12-Bit Temperature Sensors with I²C-Compatible Serial Interface | 45 | maxim,max6625 9-Bit/12-Bit Temperature Sensors with I²C-Compatible Serial Interface |
diff --git a/Documentation/devicetree/bindings/rtc/sunxi-rtc.txt b/Documentation/devicetree/bindings/rtc/sunxi-rtc.txt new file mode 100644 index 000000000000..7cb9dbf34878 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/sunxi-rtc.txt | |||
| @@ -0,0 +1,17 @@ | |||
| 1 | * sun4i/sun7i Real Time Clock | ||
| 2 | |||
| 3 | RTC controller for the Allwinner A10/A20 | ||
| 4 | |||
| 5 | Required properties: | ||
| 6 | - compatible : Should be "allwinner,sun4i-rtc" or "allwinner,sun7i-a20-rtc" | ||
| 7 | - reg: physical base address of the controller and length of memory mapped | ||
| 8 | region. | ||
| 9 | - interrupts: IRQ line for the RTC. | ||
| 10 | |||
| 11 | Example: | ||
| 12 | |||
| 13 | rtc: rtc@01c20d00 { | ||
| 14 | compatible = "allwinner,sun4i-rtc"; | ||
| 15 | reg = <0x01c20d00 0x20>; | ||
| 16 | interrupts = <24>; | ||
| 17 | }; | ||
diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt new file mode 100644 index 000000000000..f372cf29068d --- /dev/null +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt | |||
| @@ -0,0 +1,46 @@ | |||
| 1 | * Renesas SH-Mobile Serial Communication Interface | ||
| 2 | |||
| 3 | Required properties: | ||
| 4 | |||
| 5 | - compatible: Must contain one of the following: | ||
| 6 | |||
| 7 | - "renesas,scif-r8a7790" for R8A7790 (R-Car H2) SCIF compatible UART. | ||
| 8 | - "renesas,scifa-r8a7790" for R8A7790 (R-Car H2) SCIFA compatible UART. | ||
| 9 | - "renesas,scifb-r8a7790" for R8A7790 (R-Car H2) SCIFB compatible UART. | ||
| 10 | - "renesas,hscif-r8a7790" for R8A7790 (R-Car H2) HSCIF compatible UART. | ||
| 11 | - "renesas,scif-r8a7791" for R8A7791 (R-Car M2) SCIF compatible UART. | ||
| 12 | - "renesas,scifa-r8a7791" for R8A7791 (R-Car M2) SCIFA compatible UART. | ||
| 13 | - "renesas,scifb-r8a7791" for R8A7791 (R-Car M2) SCIFB compatible UART. | ||
| 14 | - "renesas,hscif-r8a7791" for R8A7791 (R-Car M2) HSCIF compatible UART. | ||
| 15 | - "renesas,scif" for generic SCIF compatible UART. | ||
| 16 | - "renesas,scifa" for generic SCIFA compatible UART. | ||
| 17 | - "renesas,scifb" for generic SCIFB compatible UART. | ||
| 18 | - "renesas,hscif" for generic HSCIF compatible UART. | ||
| 19 | |||
| 20 | When compatible with the generic version, nodes must list the | ||
| 21 | SoC-specific version corresponding to the platform first followed by the | ||
| 22 | generic version. | ||
| 23 | |||
| 24 | - reg: Base address and length of the I/O registers used by the UART. | ||
| 25 | - interrupts: Must contain an interrupt-specifier for the SCIx interrupt. | ||
| 26 | |||
| 27 | - clocks: Must contain a phandle and clock-specifier pair for each entry | ||
| 28 | in clock-names. | ||
| 29 | - clock-names: Must contain "sci_ick" for the SCIx UART interface clock. | ||
| 30 | |||
| 31 | Note: Each enabled SCIx UART should have an alias correctly numbered in the | ||
| 32 | "aliases" node. | ||
| 33 | |||
| 34 | Example: | ||
| 35 | aliases { | ||
| 36 | serial0 = &scifa0; | ||
| 37 | }; | ||
| 38 | |||
| 39 | scifa0: serial@e6c40000 { | ||
| 40 | compatible = "renesas,scifa-r8a7790", "renesas,scifa-generic"; | ||
| 41 | reg = <0 0xe6c40000 0 64>; | ||
| 42 | interrupt-parent = <&gic>; | ||
| 43 | interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>; | ||
| 44 | clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>; | ||
| 45 | clock-names = "sci_ick"; | ||
| 46 | }; | ||
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index edbb8d88c85e..2652b9e1ccc7 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt | |||
| @@ -39,6 +39,7 @@ ibm International Business Machines (IBM) | |||
| 39 | idt Integrated Device Technologies, Inc. | 39 | idt Integrated Device Technologies, Inc. |
| 40 | img Imagination Technologies Ltd. | 40 | img Imagination Technologies Ltd. |
| 41 | intercontrol Inter Control Group | 41 | intercontrol Inter Control Group |
| 42 | isl Intersil | ||
| 42 | lg LG Corporation | 43 | lg LG Corporation |
| 43 | linux Linux-specific binding | 44 | linux Linux-specific binding |
| 44 | lsi LSI Corp. (LSI Logic) | 45 | lsi LSI Corp. (LSI Logic) |
| @@ -73,6 +74,7 @@ st STMicroelectronics | |||
| 73 | ste ST-Ericsson | 74 | ste ST-Ericsson |
| 74 | stericsson ST-Ericsson | 75 | stericsson ST-Ericsson |
| 75 | ti Texas Instruments | 76 | ti Texas Instruments |
| 77 | tlm Trusted Logic Mobility | ||
| 76 | toshiba Toshiba Corporation | 78 | toshiba Toshiba Corporation |
| 77 | toumaz Toumaz | 79 | toumaz Toumaz |
| 78 | v3 V3 Semiconductor | 80 | v3 V3 Semiconductor |
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index c1f1a7eee953..8b768937c663 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig | |||
| @@ -644,8 +644,9 @@ config ARCH_MSM | |||
| 644 | stack and controls some vital subsystems | 644 | stack and controls some vital subsystems |
| 645 | (clock and power control, etc). | 645 | (clock and power control, etc). |
| 646 | 646 | ||
| 647 | config ARCH_SHMOBILE | 647 | config ARCH_SHMOBILE_LEGACY |
| 648 | bool "Renesas SH-Mobile / R-Mobile" | 648 | bool "Renesas SH-Mobile / R-Mobile (non-multiplatform)" |
| 649 | select ARCH_SHMOBILE | ||
| 649 | select ARM_PATCH_PHYS_VIRT | 650 | select ARM_PATCH_PHYS_VIRT |
| 650 | select CLKDEV_LOOKUP | 651 | select CLKDEV_LOOKUP |
| 651 | select GENERIC_CLOCKEVENTS | 652 | select GENERIC_CLOCKEVENTS |
| @@ -660,7 +661,8 @@ config ARCH_SHMOBILE | |||
| 660 | select PM_GENERIC_DOMAINS if PM | 661 | select PM_GENERIC_DOMAINS if PM |
| 661 | select SPARSE_IRQ | 662 | select SPARSE_IRQ |
| 662 | help | 663 | help |
| 663 | Support for Renesas's SH-Mobile and R-Mobile ARM platforms. | 664 | Support for Renesas's SH-Mobile and R-Mobile ARM platforms using |
| 665 | a non-multiplatform kernel. | ||
| 664 | 666 | ||
| 665 | config ARCH_RPC | 667 | config ARCH_RPC |
| 666 | bool "RiscPC" | 668 | bool "RiscPC" |
| @@ -723,6 +725,7 @@ config ARCH_S3C64XX | |||
| 723 | bool "Samsung S3C64XX" | 725 | bool "Samsung S3C64XX" |
| 724 | select ARCH_HAS_CPUFREQ | 726 | select ARCH_HAS_CPUFREQ |
| 725 | select ARCH_REQUIRE_GPIOLIB | 727 | select ARCH_REQUIRE_GPIOLIB |
| 728 | select ARM_AMBA | ||
| 726 | select ARM_VIC | 729 | select ARM_VIC |
| 727 | select CLKDEV_LOOKUP | 730 | select CLKDEV_LOOKUP |
| 728 | select CLKSRC_SAMSUNG_PWM | 731 | select CLKSRC_SAMSUNG_PWM |
| @@ -1053,6 +1056,8 @@ config ARM_TIMER_SP804 | |||
| 1053 | select CLKSRC_MMIO | 1056 | select CLKSRC_MMIO |
| 1054 | select CLKSRC_OF if OF | 1057 | select CLKSRC_OF if OF |
| 1055 | 1058 | ||
| 1059 | source "arch/arm/firmware/Kconfig" | ||
| 1060 | |||
| 1056 | source arch/arm/mm/Kconfig | 1061 | source arch/arm/mm/Kconfig |
| 1057 | 1062 | ||
| 1058 | config ARM_NR_BANKS | 1063 | config ARM_NR_BANKS |
| @@ -1611,7 +1616,7 @@ config HZ_FIXED | |||
| 1611 | default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \ | 1616 | default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \ |
| 1612 | ARCH_S5PV210 || ARCH_EXYNOS4 | 1617 | ARCH_S5PV210 || ARCH_EXYNOS4 |
| 1613 | default AT91_TIMER_HZ if ARCH_AT91 | 1618 | default AT91_TIMER_HZ if ARCH_AT91 |
| 1614 | default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE | 1619 | default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY |
| 1615 | default 0 | 1620 | default 0 |
| 1616 | 1621 | ||
| 1617 | choice | 1622 | choice |
| @@ -1796,8 +1801,8 @@ config ARCH_WANT_GENERAL_HUGETLB | |||
| 1796 | source "mm/Kconfig" | 1801 | source "mm/Kconfig" |
| 1797 | 1802 | ||
| 1798 | config FORCE_MAX_ZONEORDER | 1803 | config FORCE_MAX_ZONEORDER |
| 1799 | int "Maximum zone order" if ARCH_SHMOBILE | 1804 | int "Maximum zone order" if ARCH_SHMOBILE_LEGACY |
| 1800 | range 11 64 if ARCH_SHMOBILE | 1805 | range 11 64 if ARCH_SHMOBILE_LEGACY |
| 1801 | default "12" if SOC_AM33XX | 1806 | default "12" if SOC_AM33XX |
| 1802 | default "9" if SA1111 | 1807 | default "9" if SA1111 |
| 1803 | default "11" | 1808 | default "11" |
diff --git a/arch/arm/Makefile b/arch/arm/Makefile index c99b1086d83d..aa791d17179b 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile | |||
| @@ -190,7 +190,6 @@ machine-$(CONFIG_ARCH_S5PC100) += s5pc100 | |||
| 190 | machine-$(CONFIG_ARCH_S5PV210) += s5pv210 | 190 | machine-$(CONFIG_ARCH_S5PV210) += s5pv210 |
| 191 | machine-$(CONFIG_ARCH_SA1100) += sa1100 | 191 | machine-$(CONFIG_ARCH_SA1100) += sa1100 |
| 192 | machine-$(CONFIG_ARCH_SHMOBILE) += shmobile | 192 | machine-$(CONFIG_ARCH_SHMOBILE) += shmobile |
| 193 | machine-$(CONFIG_ARCH_SHMOBILE_MULTI) += shmobile | ||
| 194 | machine-$(CONFIG_ARCH_SIRF) += prima2 | 193 | machine-$(CONFIG_ARCH_SIRF) += prima2 |
| 195 | machine-$(CONFIG_ARCH_SOCFPGA) += socfpga | 194 | machine-$(CONFIG_ARCH_SOCFPGA) += socfpga |
| 196 | machine-$(CONFIG_ARCH_STI) += sti | 195 | machine-$(CONFIG_ARCH_STI) += sti |
| @@ -268,6 +267,7 @@ core-$(CONFIG_KVM_ARM_HOST) += arch/arm/kvm/ | |||
| 268 | core-y += arch/arm/kernel/ arch/arm/mm/ arch/arm/common/ | 267 | core-y += arch/arm/kernel/ arch/arm/mm/ arch/arm/common/ |
| 269 | core-y += arch/arm/net/ | 268 | core-y += arch/arm/net/ |
| 270 | core-y += arch/arm/crypto/ | 269 | core-y += arch/arm/crypto/ |
| 270 | core-y += arch/arm/firmware/ | ||
| 271 | core-y += $(machdirs) $(platdirs) | 271 | core-y += $(machdirs) $(platdirs) |
| 272 | 272 | ||
| 273 | drivers-$(CONFIG_OPROFILE) += arch/arm/oprofile/ | 273 | drivers-$(CONFIG_OPROFILE) += arch/arm/oprofile/ |
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile index e7190bb5998e..f54d5a25c7ee 100644 --- a/arch/arm/boot/compressed/Makefile +++ b/arch/arm/boot/compressed/Makefile | |||
| @@ -64,7 +64,7 @@ else | |||
| 64 | endif | 64 | endif |
| 65 | endif | 65 | endif |
| 66 | 66 | ||
| 67 | ifeq ($(CONFIG_ARCH_SHMOBILE),y) | 67 | ifeq ($(CONFIG_ARCH_SHMOBILE_LEGACY),y) |
| 68 | OBJS += head-shmobile.o | 68 | OBJS += head-shmobile.o |
| 69 | endif | 69 | endif |
| 70 | 70 | ||
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index d57c1a65b24f..402481775bbe 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile | |||
| @@ -30,6 +30,7 @@ dtb-$(CONFIG_ARCH_AT91) += pm9g45.dtb | |||
| 30 | dtb-$(CONFIG_ARCH_AT91) += at91sam9n12ek.dtb | 30 | dtb-$(CONFIG_ARCH_AT91) += at91sam9n12ek.dtb |
| 31 | # sam9x5 | 31 | # sam9x5 |
| 32 | dtb-$(CONFIG_ARCH_AT91) += at91-ariag25.dtb | 32 | dtb-$(CONFIG_ARCH_AT91) += at91-ariag25.dtb |
| 33 | dtb-$(CONFIG_ARCH_AT91) += at91-cosino_mega2560.dtb | ||
| 33 | dtb-$(CONFIG_ARCH_AT91) += at91sam9g15ek.dtb | 34 | dtb-$(CONFIG_ARCH_AT91) += at91sam9g15ek.dtb |
| 34 | dtb-$(CONFIG_ARCH_AT91) += at91sam9g25ek.dtb | 35 | dtb-$(CONFIG_ARCH_AT91) += at91sam9g25ek.dtb |
| 35 | dtb-$(CONFIG_ARCH_AT91) += at91sam9g35ek.dtb | 36 | dtb-$(CONFIG_ARCH_AT91) += at91sam9g35ek.dtb |
| @@ -216,7 +217,7 @@ dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \ | |||
| 216 | dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb | 217 | dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb |
| 217 | dtb-$(CONFIG_ARCH_S3C64XX) += s3c6410-mini6410.dtb \ | 218 | dtb-$(CONFIG_ARCH_S3C64XX) += s3c6410-mini6410.dtb \ |
| 218 | s3c6410-smdk6410.dtb | 219 | s3c6410-smdk6410.dtb |
| 219 | dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \ | 220 | dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += emev2-kzm9d.dtb \ |
| 220 | r7s72100-genmai.dtb \ | 221 | r7s72100-genmai.dtb \ |
| 221 | r8a7740-armadillo800eva.dtb \ | 222 | r8a7740-armadillo800eva.dtb \ |
| 222 | r8a7778-bockw.dtb \ | 223 | r8a7778-bockw.dtb \ |
diff --git a/arch/arm/boot/dts/animeo_ip.dts b/arch/arm/boot/dts/animeo_ip.dts index 3a1de9eb5111..3c4f6d983cbd 100644 --- a/arch/arm/boot/dts/animeo_ip.dts +++ b/arch/arm/boot/dts/animeo_ip.dts | |||
| @@ -90,34 +90,19 @@ | |||
| 90 | nand-on-flash-bbt; | 90 | nand-on-flash-bbt; |
| 91 | status = "okay"; | 91 | status = "okay"; |
| 92 | 92 | ||
| 93 | at91bootstrap@0 { | 93 | barebox@0 { |
| 94 | label = "at91bootstrap"; | ||
| 95 | reg = <0x0 0x8000>; | ||
| 96 | }; | ||
| 97 | |||
| 98 | barebox@8000 { | ||
| 99 | label = "barebox"; | 94 | label = "barebox"; |
| 100 | reg = <0x8000 0x40000>; | 95 | reg = <0x0 0x58000>; |
| 101 | }; | ||
| 102 | |||
| 103 | bareboxenv@48000 { | ||
| 104 | label = "bareboxenv"; | ||
| 105 | reg = <0x48000 0x8000>; | ||
| 106 | }; | ||
| 107 | |||
| 108 | user_block@0x50000 { | ||
| 109 | label = "user_block"; | ||
| 110 | reg = <0x50000 0xb0000>; | ||
| 111 | }; | 96 | }; |
| 112 | 97 | ||
| 113 | kernel@100000 { | 98 | u_boot_env@58000 { |
| 114 | label = "kernel"; | 99 | label = "u_boot_env"; |
| 115 | reg = <0x100000 0x1b0000>; | 100 | reg = <0x58000 0x8000>; |
| 116 | }; | 101 | }; |
| 117 | 102 | ||
| 118 | root@2b0000 { | 103 | ubi@60000 { |
| 119 | label = "root"; | 104 | label = "ubi"; |
| 120 | reg = <0x2b0000 0x1D50000>; | 105 | reg = <0x60000 0x1FA0000>; |
| 121 | }; | 106 | }; |
| 122 | }; | 107 | }; |
| 123 | 108 | ||
diff --git a/arch/arm/boot/dts/at91-cosino.dtsi b/arch/arm/boot/dts/at91-cosino.dtsi new file mode 100644 index 000000000000..2093c4d7cd6a --- /dev/null +++ b/arch/arm/boot/dts/at91-cosino.dtsi | |||
| @@ -0,0 +1,122 @@ | |||
| 1 | /* | ||
| 2 | * at91-cosino.dtsi - Device Tree file for Cosino core module | ||
| 3 | * | ||
| 4 | * Copyright (C) 2013 - Rodolfo Giometti <giometti@linux.it> | ||
| 5 | * HCE Engineering | ||
| 6 | * | ||
| 7 | * Derived from at91sam9x5ek.dtsi by: | ||
| 8 | * Copyright (C) 2012 Atmel, | ||
| 9 | * 2012 Nicolas Ferre <nicolas.ferre@atmel.com> | ||
| 10 | * | ||
| 11 | * Licensed under GPLv2 or later. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #include "at91sam9g35.dtsi" | ||
| 15 | |||
| 16 | / { | ||
| 17 | model = "HCE Cosino core module"; | ||
| 18 | compatible = "hce,cosino", "atmel,at91sam9x5", "atmel,at91sam9"; | ||
| 19 | |||
| 20 | chosen { | ||
| 21 | bootargs = "console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootfstype=ext3 rootwait"; | ||
| 22 | }; | ||
| 23 | |||
| 24 | memory { | ||
| 25 | reg = <0x20000000 0x8000000>; | ||
| 26 | }; | ||
| 27 | |||
| 28 | clocks { | ||
| 29 | #address-cells = <1>; | ||
| 30 | #size-cells = <1>; | ||
| 31 | ranges; | ||
| 32 | |||
| 33 | main_clock: clock@0 { | ||
| 34 | compatible = "atmel,osc", "fixed-clock"; | ||
| 35 | clock-frequency = <12000000>; | ||
| 36 | }; | ||
| 37 | }; | ||
| 38 | |||
| 39 | ahb { | ||
| 40 | apb { | ||
| 41 | mmc0: mmc@f0008000 { | ||
| 42 | pinctrl-0 = < | ||
| 43 | &pinctrl_board_mmc0 | ||
| 44 | &pinctrl_mmc0_slot0_clk_cmd_dat0 | ||
| 45 | &pinctrl_mmc0_slot0_dat1_3>; | ||
| 46 | status = "okay"; | ||
| 47 | slot@0 { | ||
| 48 | reg = <0>; | ||
| 49 | bus-width = <4>; | ||
| 50 | cd-gpios = <&pioD 15 GPIO_ACTIVE_HIGH>; | ||
| 51 | }; | ||
| 52 | }; | ||
| 53 | |||
| 54 | dbgu: serial@fffff200 { | ||
| 55 | status = "okay"; | ||
| 56 | }; | ||
| 57 | |||
| 58 | usart0: serial@f801c000 { | ||
| 59 | status = "okay"; | ||
| 60 | }; | ||
| 61 | |||
| 62 | i2c0: i2c@f8010000 { | ||
| 63 | status = "okay"; | ||
| 64 | }; | ||
| 65 | |||
| 66 | adc0: adc@f804c000 { | ||
| 67 | atmel,adc-clock-rate = <1000000>; | ||
| 68 | atmel,adc-ts-wires = <4>; | ||
| 69 | atmel,adc-ts-pressure-threshold = <10000>; | ||
| 70 | status = "okay"; | ||
| 71 | }; | ||
| 72 | |||
| 73 | pinctrl@fffff400 { | ||
| 74 | mmc0 { | ||
| 75 | pinctrl_board_mmc0: mmc0-board { | ||
| 76 | atmel,pins = | ||
| 77 | <AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PD15 gpio CD pin pull up and deglitch */ | ||
| 78 | }; | ||
| 79 | }; | ||
| 80 | }; | ||
| 81 | |||
| 82 | watchdog@fffffe40 { | ||
| 83 | status = "okay"; | ||
| 84 | }; | ||
| 85 | }; | ||
| 86 | |||
| 87 | nand0: nand@40000000 { | ||
| 88 | nand-bus-width = <8>; | ||
| 89 | nand-ecc-mode = "hw"; | ||
| 90 | atmel,has-pmecc; /* Enable PMECC */ | ||
| 91 | atmel,pmecc-cap = <4>; | ||
| 92 | atmel,pmecc-sector-size = <512>; | ||
| 93 | nand-on-flash-bbt; | ||
| 94 | status = "okay"; | ||
| 95 | |||
| 96 | at91bootstrap@0 { | ||
| 97 | label = "at91bootstrap"; | ||
| 98 | reg = <0x0 0x40000>; | ||
| 99 | }; | ||
| 100 | |||
| 101 | uboot@40000 { | ||
| 102 | label = "u-boot"; | ||
| 103 | reg = <0x40000 0x80000>; | ||
| 104 | }; | ||
| 105 | |||
| 106 | ubootenv@c0000 { | ||
| 107 | label = "U-Boot Env"; | ||
| 108 | reg = <0xc0000 0x140000>; | ||
| 109 | }; | ||
| 110 | |||
| 111 | kernel@200000 { | ||
| 112 | label = "kernel"; | ||
| 113 | reg = <0x200000 0x600000>; | ||
| 114 | }; | ||
| 115 | |||
| 116 | rootfs@800000 { | ||
| 117 | label = "rootfs"; | ||
| 118 | reg = <0x800000 0x0f800000>; | ||
| 119 | }; | ||
| 120 | }; | ||
| 121 | }; | ||
| 122 | }; | ||
diff --git a/arch/arm/boot/dts/at91-cosino_mega2560.dts b/arch/arm/boot/dts/at91-cosino_mega2560.dts new file mode 100644 index 000000000000..f9415dd11f17 --- /dev/null +++ b/arch/arm/boot/dts/at91-cosino_mega2560.dts | |||
| @@ -0,0 +1,84 @@ | |||
| 1 | /* | ||
| 2 | * at91-cosino_mega2560.dts - Device Tree file for Cosino board with | ||
| 3 | * Mega 2560 extension | ||
| 4 | * | ||
| 5 | * Copyright (C) 2013 - Rodolfo Giometti <giometti@linux.it> | ||
| 6 | * HCE Engineering | ||
| 7 | * | ||
| 8 | * Derived from at91sam9g35ek.dts by: | ||
| 9 | * Copyright (C) 2012 Atmel, | ||
| 10 | * 2012 Nicolas Ferre <nicolas.ferre@atmel.com> | ||
| 11 | * | ||
| 12 | * Licensed under GPLv2 or later. | ||
| 13 | */ | ||
| 14 | |||
| 15 | /dts-v1/; | ||
| 16 | #include "at91-cosino.dtsi" | ||
| 17 | |||
| 18 | / { | ||
| 19 | model = "HCE Cosino Mega 2560"; | ||
| 20 | compatible = "hce,cosino_mega2560", "atmel,at91sam9x5", "atmel,at91sam9"; | ||
| 21 | |||
| 22 | ahb { | ||
| 23 | apb { | ||
| 24 | macb0: ethernet@f802c000 { | ||
| 25 | phy-mode = "rmii"; | ||
| 26 | status = "okay"; | ||
| 27 | }; | ||
| 28 | |||
| 29 | adc0: adc@f804c000 { | ||
| 30 | atmel,adc-clock-rate = <1000000>; | ||
| 31 | atmel,adc-ts-wires = <4>; | ||
| 32 | atmel,adc-ts-pressure-threshold = <10000>; | ||
| 33 | status = "okay"; | ||
| 34 | }; | ||
| 35 | |||
| 36 | |||
| 37 | tsadcc: tsadcc@f804c000 { | ||
| 38 | status = "okay"; | ||
| 39 | }; | ||
| 40 | |||
| 41 | rtc@fffffeb0 { | ||
| 42 | status = "okay"; | ||
| 43 | }; | ||
| 44 | |||
| 45 | usart1: serial@f8020000 { | ||
| 46 | status = "okay"; | ||
| 47 | }; | ||
| 48 | |||
| 49 | usart2: serial@f8024000 { | ||
| 50 | status = "okay"; | ||
| 51 | }; | ||
| 52 | |||
| 53 | usb2: gadget@f803c000 { | ||
| 54 | atmel,vbus-gpio = <&pioB 16 GPIO_ACTIVE_HIGH>; | ||
| 55 | status = "okay"; | ||
| 56 | }; | ||
| 57 | |||
| 58 | mmc1: mmc@f000c000 { | ||
| 59 | pinctrl-0 = < | ||
| 60 | &pinctrl_mmc1_slot0_clk_cmd_dat0 | ||
| 61 | &pinctrl_mmc1_slot0_dat1_3>; | ||
| 62 | status = "okay"; | ||
| 63 | slot@0 { | ||
| 64 | reg = <0>; | ||
| 65 | bus-width = <4>; | ||
| 66 | non-removable; | ||
| 67 | }; | ||
| 68 | }; | ||
| 69 | }; | ||
| 70 | |||
| 71 | usb0: ohci@00600000 { | ||
| 72 | status = "okay"; | ||
| 73 | num-ports = <3>; | ||
| 74 | atmel,vbus-gpio = <0 /* &pioD 18 GPIO_ACTIVE_LOW */ | ||
| 75 | &pioD 19 GPIO_ACTIVE_LOW | ||
| 76 | &pioD 20 GPIO_ACTIVE_LOW | ||
| 77 | >; | ||
| 78 | }; | ||
| 79 | |||
| 80 | usb1: ehci@00700000 { | ||
| 81 | status = "okay"; | ||
| 82 | }; | ||
| 83 | }; | ||
| 84 | }; | ||
diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi index f77065506f1e..c61b16fba79b 100644 --- a/arch/arm/boot/dts/at91rm9200.dtsi +++ b/arch/arm/boot/dts/at91rm9200.dtsi | |||
| @@ -191,12 +191,12 @@ | |||
| 191 | AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA18 periph A */ | 191 | AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA18 periph A */ |
| 192 | }; | 192 | }; |
| 193 | 193 | ||
| 194 | pinctrl_uart0_rts: uart0_rts-0 { | 194 | pinctrl_uart0_cts: uart0_cts-0 { |
| 195 | atmel,pins = | 195 | atmel,pins = |
| 196 | <AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA20 periph A */ | 196 | <AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA20 periph A */ |
| 197 | }; | 197 | }; |
| 198 | 198 | ||
| 199 | pinctrl_uart0_cts: uart0_cts-0 { | 199 | pinctrl_uart0_rts: uart0_rts-0 { |
| 200 | atmel,pins = | 200 | atmel,pins = |
| 201 | <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA21 periph A */ | 201 | <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA21 periph A */ |
| 202 | }; | 202 | }; |
diff --git a/arch/arm/boot/dts/at91rm9200ek.dts b/arch/arm/boot/dts/at91rm9200ek.dts index d2d72c3b44c4..df6b0aa0e4dd 100644 --- a/arch/arm/boot/dts/at91rm9200ek.dts +++ b/arch/arm/boot/dts/at91rm9200ek.dts | |||
| @@ -29,10 +29,22 @@ | |||
| 29 | 29 | ||
| 30 | ahb { | 30 | ahb { |
| 31 | apb { | 31 | apb { |
| 32 | dbgu: serial@fffff200 { | 32 | usb1: gadget@fffb0000 { |
| 33 | atmel,vbus-gpio = <&pioD 4 GPIO_ACTIVE_HIGH>; | ||
| 34 | atmel,pullup-gpio = <&pioD 5 GPIO_ACTIVE_HIGH>; | ||
| 33 | status = "okay"; | 35 | status = "okay"; |
| 34 | }; | 36 | }; |
| 35 | 37 | ||
| 38 | macb0: ethernet@fffbc000 { | ||
| 39 | phy-mode = "rmii"; | ||
| 40 | status = "okay"; | ||
| 41 | |||
| 42 | phy0: ethernet-phy { | ||
| 43 | interrupt-parent = <&pioC>; | ||
| 44 | interrupts = <4 IRQ_TYPE_EDGE_BOTH>; | ||
| 45 | }; | ||
| 46 | }; | ||
| 47 | |||
| 36 | usart1: serial@fffc4000 { | 48 | usart1: serial@fffc4000 { |
| 37 | pinctrl-0 = | 49 | pinctrl-0 = |
| 38 | <&pinctrl_uart1 | 50 | <&pinctrl_uart1 |
| @@ -44,16 +56,6 @@ | |||
| 44 | status = "okay"; | 56 | status = "okay"; |
| 45 | }; | 57 | }; |
| 46 | 58 | ||
| 47 | macb0: ethernet@fffbc000 { | ||
| 48 | phy-mode = "rmii"; | ||
| 49 | status = "okay"; | ||
| 50 | }; | ||
| 51 | |||
| 52 | usb1: gadget@fffb0000 { | ||
| 53 | atmel,vbus-gpio = <&pioD 4 GPIO_ACTIVE_HIGH>; | ||
| 54 | status = "okay"; | ||
| 55 | }; | ||
| 56 | |||
| 57 | spi0: spi@fffe0000 { | 59 | spi0: spi@fffe0000 { |
| 58 | status = "okay"; | 60 | status = "okay"; |
| 59 | cs-gpios = <&pioA 3 0>, <0>, <0>, <0>; | 61 | cs-gpios = <&pioA 3 0>, <0>, <0>, <0>; |
| @@ -63,12 +65,45 @@ | |||
| 63 | reg = <0>; | 65 | reg = <0>; |
| 64 | }; | 66 | }; |
| 65 | }; | 67 | }; |
| 68 | |||
| 69 | dbgu: serial@fffff200 { | ||
| 70 | status = "okay"; | ||
| 71 | }; | ||
| 66 | }; | 72 | }; |
| 67 | 73 | ||
| 68 | usb0: ohci@00300000 { | 74 | usb0: ohci@00300000 { |
| 69 | num-ports = <2>; | 75 | num-ports = <2>; |
| 70 | status = "okay"; | 76 | status = "okay"; |
| 71 | }; | 77 | }; |
| 78 | |||
| 79 | nor_flash@10000000 { | ||
| 80 | compatible = "cfi-flash"; | ||
| 81 | reg = <0x10000000 0x800000>; | ||
| 82 | linux,mtd-name = "physmap-flash.0"; | ||
| 83 | bank-width = <2>; | ||
| 84 | #address-cells = <1>; | ||
| 85 | #size-cells = <1>; | ||
| 86 | |||
| 87 | barebox@0 { | ||
| 88 | label = "barebox"; | ||
| 89 | reg = <0x00000 0x40000>; | ||
| 90 | }; | ||
| 91 | |||
| 92 | bareboxenv@40000 { | ||
| 93 | label = "bareboxenv"; | ||
| 94 | reg = <0x40000 0x10000>; | ||
| 95 | }; | ||
| 96 | |||
| 97 | kernel@50000 { | ||
| 98 | label = "kernel"; | ||
| 99 | reg = <0x50000 0x300000>; | ||
| 100 | }; | ||
| 101 | |||
| 102 | root@350000 { | ||
| 103 | label = "root"; | ||
| 104 | reg = <0x350000 0x4B0000>; | ||
| 105 | }; | ||
| 106 | }; | ||
| 72 | }; | 107 | }; |
| 73 | 108 | ||
| 74 | leds { | 109 | leds { |
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi index d5bd65f74602..22e255ab6963 100644 --- a/arch/arm/boot/dts/at91sam9263.dtsi +++ b/arch/arm/boot/dts/at91sam9263.dtsi | |||
| @@ -366,6 +366,34 @@ | |||
| 366 | }; | 366 | }; |
| 367 | }; | 367 | }; |
| 368 | 368 | ||
| 369 | fb { | ||
| 370 | pinctrl_fb: fb-0 { | ||
| 371 | atmel,pins = | ||
| 372 | <AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC1 periph A */ | ||
| 373 | AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC2 periph A */ | ||
| 374 | AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC3 periph A */ | ||
| 375 | AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB9 periph B */ | ||
| 376 | AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 periph A */ | ||
| 377 | AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 periph A */ | ||
| 378 | AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 periph A */ | ||
| 379 | AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC9 periph A */ | ||
| 380 | AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC10 periph A */ | ||
| 381 | AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC11 periph A */ | ||
| 382 | AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC14 periph A */ | ||
| 383 | AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC15 periph A */ | ||
| 384 | AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC16 periph A */ | ||
| 385 | AT91_PIOC 12 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC12 periph B */ | ||
| 386 | AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC18 periph A */ | ||
| 387 | AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC19 periph A */ | ||
| 388 | AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC22 periph A */ | ||
| 389 | AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC23 periph A */ | ||
| 390 | AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC24 periph A */ | ||
| 391 | AT91_PIOC 17 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC17 periph B */ | ||
| 392 | AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC26 periph A */ | ||
| 393 | AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC27 periph A */ | ||
| 394 | }; | ||
| 395 | }; | ||
| 396 | |||
| 369 | pioA: gpio@fffff200 { | 397 | pioA: gpio@fffff200 { |
| 370 | compatible = "atmel,at91rm9200-gpio"; | 398 | compatible = "atmel,at91rm9200-gpio"; |
| 371 | reg = <0xfffff200 0x200>; | 399 | reg = <0xfffff200 0x200>; |
| @@ -549,6 +577,15 @@ | |||
| 549 | }; | 577 | }; |
| 550 | }; | 578 | }; |
| 551 | 579 | ||
| 580 | fb0: fb@0x00700000 { | ||
| 581 | compatible = "atmel,at91sam9263-lcdc"; | ||
| 582 | reg = <0x00700000 0x1000>; | ||
| 583 | interrupts = <26 IRQ_TYPE_LEVEL_HIGH 3>; | ||
| 584 | pinctrl-names = "default"; | ||
| 585 | pinctrl-0 = <&pinctrl_fb>; | ||
| 586 | status = "disabled"; | ||
| 587 | }; | ||
| 588 | |||
| 552 | nand0: nand@40000000 { | 589 | nand0: nand@40000000 { |
| 553 | compatible = "atmel,at91rm9200-nand"; | 590 | compatible = "atmel,at91rm9200-nand"; |
| 554 | #address-cells = <1>; | 591 | #address-cells = <1>; |
diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/at91sam9263ek.dts index 70f835b55c0b..15009c9f2293 100644 --- a/arch/arm/boot/dts/at91sam9263ek.dts +++ b/arch/arm/boot/dts/at91sam9263ek.dts | |||
| @@ -95,6 +95,36 @@ | |||
| 95 | }; | 95 | }; |
| 96 | }; | 96 | }; |
| 97 | 97 | ||
| 98 | fb0: fb@0x00700000 { | ||
| 99 | display = <&display0>; | ||
| 100 | status = "okay"; | ||
| 101 | |||
| 102 | display0: display { | ||
| 103 | bits-per-pixel = <16>; | ||
| 104 | atmel,lcdcon-backlight; | ||
| 105 | atmel,dmacon = <0x1>; | ||
| 106 | atmel,lcdcon2 = <0x80008002>; | ||
| 107 | atmel,guard-time = <1>; | ||
| 108 | |||
| 109 | display-timings { | ||
| 110 | native-mode = <&timing0>; | ||
| 111 | timing0: timing0 { | ||
| 112 | clock-frequency = <4965000>; | ||
| 113 | hactive = <240>; | ||
| 114 | vactive = <320>; | ||
| 115 | hback-porch = <1>; | ||
| 116 | hfront-porch = <33>; | ||
| 117 | vback-porch = <1>; | ||
| 118 | vfront-porch = <0>; | ||
| 119 | hsync-len = <5>; | ||
| 120 | vsync-len = <1>; | ||
| 121 | hsync-active = <1>; | ||
| 122 | vsync-active = <1>; | ||
| 123 | }; | ||
| 124 | }; | ||
| 125 | }; | ||
| 126 | }; | ||
| 127 | |||
| 98 | nand0: nand@40000000 { | 128 | nand0: nand@40000000 { |
| 99 | nand-bus-width = <8>; | 129 | nand-bus-width = <8>; |
| 100 | nand-ecc-mode = "soft"; | 130 | nand-ecc-mode = "soft"; |
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index c3e514837074..d7af9ecb85d2 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi | |||
| @@ -143,6 +143,22 @@ | |||
| 143 | }; | 143 | }; |
| 144 | }; | 144 | }; |
| 145 | 145 | ||
| 146 | i2c0 { | ||
| 147 | pinctrl_i2c0: i2c0-0 { | ||
| 148 | atmel,pins = | ||
| 149 | <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA21 periph A TWCK0 */ | ||
| 150 | AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA20 periph A TWD0 */ | ||
| 151 | }; | ||
| 152 | }; | ||
| 153 | |||
| 154 | i2c1 { | ||
| 155 | pinctrl_i2c1: i2c1-0 { | ||
| 156 | atmel,pins = | ||
| 157 | <AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A TWCK1 */ | ||
| 158 | AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A TWD1 */ | ||
| 159 | }; | ||
| 160 | }; | ||
| 161 | |||
| 146 | usart0 { | 162 | usart0 { |
| 147 | pinctrl_usart0: usart0-0 { | 163 | pinctrl_usart0: usart0-0 { |
| 148 | atmel,pins = | 164 | atmel,pins = |
| @@ -425,6 +441,42 @@ | |||
| 425 | }; | 441 | }; |
| 426 | }; | 442 | }; |
| 427 | 443 | ||
| 444 | fb { | ||
| 445 | pinctrl_fb: fb-0 { | ||
| 446 | atmel,pins = | ||
| 447 | <AT91_PIOE 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE0 periph A */ | ||
| 448 | AT91_PIOE 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE2 periph A */ | ||
| 449 | AT91_PIOE 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE3 periph A */ | ||
| 450 | AT91_PIOE 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE4 periph A */ | ||
| 451 | AT91_PIOE 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE5 periph A */ | ||
| 452 | AT91_PIOE 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE6 periph A */ | ||
| 453 | AT91_PIOE 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE7 periph A */ | ||
| 454 | AT91_PIOE 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE8 periph A */ | ||
| 455 | AT91_PIOE 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE9 periph A */ | ||
| 456 | AT91_PIOE 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE10 periph A */ | ||
| 457 | AT91_PIOE 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE11 periph A */ | ||
| 458 | AT91_PIOE 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE12 periph A */ | ||
| 459 | AT91_PIOE 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE13 periph A */ | ||
| 460 | AT91_PIOE 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE14 periph A */ | ||
| 461 | AT91_PIOE 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE15 periph A */ | ||
| 462 | AT91_PIOE 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE16 periph A */ | ||
| 463 | AT91_PIOE 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE17 periph A */ | ||
| 464 | AT91_PIOE 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE18 periph A */ | ||
| 465 | AT91_PIOE 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE19 periph A */ | ||
| 466 | AT91_PIOE 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE20 periph A */ | ||
| 467 | AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE21 periph A */ | ||
| 468 | AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE22 periph A */ | ||
| 469 | AT91_PIOE 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE23 periph A */ | ||
| 470 | AT91_PIOE 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE24 periph A */ | ||
| 471 | AT91_PIOE 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE25 periph A */ | ||
| 472 | AT91_PIOE 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE26 periph A */ | ||
| 473 | AT91_PIOE 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE27 periph A */ | ||
| 474 | AT91_PIOE 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE28 periph A */ | ||
| 475 | AT91_PIOE 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE29 periph A */ | ||
| 476 | AT91_PIOE 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PE30 periph A */ | ||
| 477 | }; | ||
| 478 | }; | ||
| 479 | |||
| 428 | pioA: gpio@fffff200 { | 480 | pioA: gpio@fffff200 { |
| 429 | compatible = "atmel,at91rm9200-gpio"; | 481 | compatible = "atmel,at91rm9200-gpio"; |
| 430 | reg = <0xfffff200 0x200>; | 482 | reg = <0xfffff200 0x200>; |
| @@ -542,6 +594,8 @@ | |||
| 542 | compatible = "atmel,at91sam9g10-i2c"; | 594 | compatible = "atmel,at91sam9g10-i2c"; |
| 543 | reg = <0xfff84000 0x100>; | 595 | reg = <0xfff84000 0x100>; |
| 544 | interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>; | 596 | interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>; |
| 597 | pinctrl-names = "default"; | ||
| 598 | pinctrl-0 = <&pinctrl_i2c0>; | ||
| 545 | #address-cells = <1>; | 599 | #address-cells = <1>; |
| 546 | #size-cells = <0>; | 600 | #size-cells = <0>; |
| 547 | status = "disabled"; | 601 | status = "disabled"; |
| @@ -551,6 +605,8 @@ | |||
| 551 | compatible = "atmel,at91sam9g10-i2c"; | 605 | compatible = "atmel,at91sam9g10-i2c"; |
| 552 | reg = <0xfff88000 0x100>; | 606 | reg = <0xfff88000 0x100>; |
| 553 | interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>; | 607 | interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>; |
| 608 | pinctrl-names = "default"; | ||
| 609 | pinctrl-0 = <&pinctrl_i2c1>; | ||
| 554 | #address-cells = <1>; | 610 | #address-cells = <1>; |
| 555 | #size-cells = <0>; | 611 | #size-cells = <0>; |
| 556 | status = "disabled"; | 612 | status = "disabled"; |
| @@ -618,6 +674,7 @@ | |||
| 618 | compatible = "atmel,hsmci"; | 674 | compatible = "atmel,hsmci"; |
| 619 | reg = <0xfff80000 0x600>; | 675 | reg = <0xfff80000 0x600>; |
| 620 | interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; | 676 | interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; |
| 677 | pinctrl-names = "default"; | ||
| 621 | dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>; | 678 | dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>; |
| 622 | dma-names = "rxtx"; | 679 | dma-names = "rxtx"; |
| 623 | #address-cells = <1>; | 680 | #address-cells = <1>; |
| @@ -629,6 +686,7 @@ | |||
| 629 | compatible = "atmel,hsmci"; | 686 | compatible = "atmel,hsmci"; |
| 630 | reg = <0xfffd0000 0x600>; | 687 | reg = <0xfffd0000 0x600>; |
| 631 | interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>; | 688 | interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>; |
| 689 | pinctrl-names = "default"; | ||
| 632 | dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>; | 690 | dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>; |
| 633 | dma-names = "rxtx"; | 691 | dma-names = "rxtx"; |
| 634 | #address-cells = <1>; | 692 | #address-cells = <1>; |
| @@ -727,6 +785,15 @@ | |||
| 727 | }; | 785 | }; |
| 728 | }; | 786 | }; |
| 729 | 787 | ||
| 788 | fb0: fb@0x00500000 { | ||
| 789 | compatible = "atmel,at91sam9g45-lcdc"; | ||
| 790 | reg = <0x00500000 0x1000>; | ||
| 791 | interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>; | ||
| 792 | pinctrl-names = "default"; | ||
| 793 | pinctrl-0 = <&pinctrl_fb>; | ||
| 794 | status = "disabled"; | ||
| 795 | }; | ||
| 796 | |||
| 730 | nand0: nand@40000000 { | 797 | nand0: nand@40000000 { |
| 731 | compatible = "atmel,at91rm9200-nand"; | 798 | compatible = "atmel,at91rm9200-nand"; |
| 732 | #address-cells = <1>; | 799 | #address-cells = <1>; |
diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts index a4b00e5c61c0..7b76dbde8c41 100644 --- a/arch/arm/boot/dts/at91sam9m10g45ek.dts +++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts | |||
| @@ -123,6 +123,35 @@ | |||
| 123 | }; | 123 | }; |
| 124 | }; | 124 | }; |
| 125 | 125 | ||
| 126 | fb0: fb@0x00500000 { | ||
| 127 | display = <&display0>; | ||
| 128 | status = "okay"; | ||
| 129 | |||
| 130 | display0: display { | ||
| 131 | bits-per-pixel = <32>; | ||
| 132 | atmel,lcdcon-backlight; | ||
| 133 | atmel,dmacon = <0x1>; | ||
| 134 | atmel,lcdcon2 = <0x80008002>; | ||
| 135 | atmel,guard-time = <9>; | ||
| 136 | atmel,lcd-wiring-mode = "RGB"; | ||
| 137 | |||
| 138 | display-timings { | ||
| 139 | native-mode = <&timing0>; | ||
| 140 | timing0: timing0 { | ||
| 141 | clock-frequency = <9000000>; | ||
| 142 | hactive = <480>; | ||
| 143 | vactive = <272>; | ||
| 144 | hback-porch = <1>; | ||
| 145 | hfront-porch = <1>; | ||
| 146 | vback-porch = <40>; | ||
| 147 | vfront-porch = <1>; | ||
| 148 | hsync-len = <45>; | ||
| 149 | vsync-len = <1>; | ||
| 150 | }; | ||
| 151 | }; | ||
| 152 | }; | ||
| 153 | }; | ||
| 154 | |||
| 126 | nand0: nand@40000000 { | 155 | nand0: nand@40000000 { |
| 127 | nand-bus-width = <8>; | 156 | nand-bus-width = <8>; |
| 128 | nand-ecc-mode = "soft"; | 157 | nand-ecc-mode = "soft"; |
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index 5cdaba4cea86..070c5c3a2291 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi | |||
| @@ -13,6 +13,7 @@ | |||
| 13 | #include <dt-bindings/pinctrl/at91.h> | 13 | #include <dt-bindings/pinctrl/at91.h> |
| 14 | #include <dt-bindings/interrupt-controller/irq.h> | 14 | #include <dt-bindings/interrupt-controller/irq.h> |
| 15 | #include <dt-bindings/gpio/gpio.h> | 15 | #include <dt-bindings/gpio/gpio.h> |
| 16 | #include <dt-bindings/clk/at91.h> | ||
| 16 | 17 | ||
| 17 | / { | 18 | / { |
| 18 | model = "Atmel SAMA5D3 family SoC"; | 19 | model = "Atmel SAMA5D3 family SoC"; |
| @@ -56,6 +57,14 @@ | |||
| 56 | reg = <0x20000000 0x8000000>; | 57 | reg = <0x20000000 0x8000000>; |
| 57 | }; | 58 | }; |
| 58 | 59 | ||
| 60 | clocks { | ||
| 61 | adc_op_clk: adc_op_clk{ | ||
| 62 | compatible = "fixed-clock"; | ||
| 63 | #clock-cells = <0>; | ||
| 64 | clock-frequency = <20000000>; | ||
| 65 | }; | ||
| 66 | }; | ||
| 67 | |||
| 59 | ahb { | 68 | ahb { |
| 60 | compatible = "simple-bus"; | 69 | compatible = "simple-bus"; |
| 61 | #address-cells = <1>; | 70 | #address-cells = <1>; |
| @@ -79,6 +88,8 @@ | |||
| 79 | status = "disabled"; | 88 | status = "disabled"; |
| 80 | #address-cells = <1>; | 89 | #address-cells = <1>; |
| 81 | #size-cells = <0>; | 90 | #size-cells = <0>; |
| 91 | clocks = <&mci0_clk>; | ||
| 92 | clock-names = "mci_clk"; | ||
| 82 | }; | 93 | }; |
| 83 | 94 | ||
| 84 | spi0: spi@f0004000 { | 95 | spi0: spi@f0004000 { |
| @@ -92,6 +103,8 @@ | |||
| 92 | dma-names = "tx", "rx"; | 103 | dma-names = "tx", "rx"; |
| 93 | pinctrl-names = "default"; | 104 | pinctrl-names = "default"; |
| 94 | pinctrl-0 = <&pinctrl_spi0>; | 105 | pinctrl-0 = <&pinctrl_spi0>; |
| 106 | clocks = <&spi0_clk>; | ||
| 107 | clock-names = "spi_clk"; | ||
| 95 | status = "disabled"; | 108 | status = "disabled"; |
| 96 | }; | 109 | }; |
| 97 | 110 | ||
| @@ -101,6 +114,8 @@ | |||
| 101 | interrupts = <38 IRQ_TYPE_LEVEL_HIGH 4>; | 114 | interrupts = <38 IRQ_TYPE_LEVEL_HIGH 4>; |
| 102 | pinctrl-names = "default"; | 115 | pinctrl-names = "default"; |
| 103 | pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; | 116 | pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; |
| 117 | clocks = <&ssc0_clk>; | ||
| 118 | clock-names = "pclk"; | ||
| 104 | status = "disabled"; | 119 | status = "disabled"; |
| 105 | }; | 120 | }; |
| 106 | 121 | ||
| @@ -108,6 +123,8 @@ | |||
| 108 | compatible = "atmel,at91sam9x5-tcb"; | 123 | compatible = "atmel,at91sam9x5-tcb"; |
| 109 | reg = <0xf0010000 0x100>; | 124 | reg = <0xf0010000 0x100>; |
| 110 | interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; | 125 | interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; |
| 126 | clocks = <&tcb0_clk>; | ||
| 127 | clock-names = "t0_clk"; | ||
| 111 | }; | 128 | }; |
| 112 | 129 | ||
| 113 | i2c0: i2c@f0014000 { | 130 | i2c0: i2c@f0014000 { |
| @@ -121,6 +138,7 @@ | |||
| 121 | pinctrl-0 = <&pinctrl_i2c0>; | 138 | pinctrl-0 = <&pinctrl_i2c0>; |
| 122 | #address-cells = <1>; | 139 | #address-cells = <1>; |
| 123 | #size-cells = <0>; | 140 | #size-cells = <0>; |
| 141 | clocks = <&twi0_clk>; | ||
| 124 | status = "disabled"; | 142 | status = "disabled"; |
| 125 | }; | 143 | }; |
| 126 | 144 | ||
| @@ -135,6 +153,7 @@ | |||
| 135 | pinctrl-0 = <&pinctrl_i2c1>; | 153 | pinctrl-0 = <&pinctrl_i2c1>; |
| 136 | #address-cells = <1>; | 154 | #address-cells = <1>; |
| 137 | #size-cells = <0>; | 155 | #size-cells = <0>; |
| 156 | clocks = <&twi1_clk>; | ||
| 138 | status = "disabled"; | 157 | status = "disabled"; |
| 139 | }; | 158 | }; |
| 140 | 159 | ||
| @@ -144,6 +163,8 @@ | |||
| 144 | interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>; | 163 | interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>; |
| 145 | pinctrl-names = "default"; | 164 | pinctrl-names = "default"; |
| 146 | pinctrl-0 = <&pinctrl_usart0>; | 165 | pinctrl-0 = <&pinctrl_usart0>; |
| 166 | clocks = <&usart0_clk>; | ||
| 167 | clock-names = "usart"; | ||
| 147 | status = "disabled"; | 168 | status = "disabled"; |
| 148 | }; | 169 | }; |
| 149 | 170 | ||
| @@ -153,6 +174,8 @@ | |||
| 153 | interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>; | 174 | interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>; |
| 154 | pinctrl-names = "default"; | 175 | pinctrl-names = "default"; |
| 155 | pinctrl-0 = <&pinctrl_usart1>; | 176 | pinctrl-0 = <&pinctrl_usart1>; |
| 177 | clocks = <&usart1_clk>; | ||
| 178 | clock-names = "usart"; | ||
| 156 | status = "disabled"; | 179 | status = "disabled"; |
| 157 | }; | 180 | }; |
| 158 | 181 | ||
| @@ -174,6 +197,8 @@ | |||
| 174 | status = "disabled"; | 197 | status = "disabled"; |
| 175 | #address-cells = <1>; | 198 | #address-cells = <1>; |
| 176 | #size-cells = <0>; | 199 | #size-cells = <0>; |
| 200 | clocks = <&mci1_clk>; | ||
| 201 | clock-names = "mci_clk"; | ||
| 177 | }; | 202 | }; |
| 178 | 203 | ||
| 179 | spi1: spi@f8008000 { | 204 | spi1: spi@f8008000 { |
| @@ -187,6 +212,8 @@ | |||
| 187 | dma-names = "tx", "rx"; | 212 | dma-names = "tx", "rx"; |
| 188 | pinctrl-names = "default"; | 213 | pinctrl-names = "default"; |
| 189 | pinctrl-0 = <&pinctrl_spi1>; | 214 | pinctrl-0 = <&pinctrl_spi1>; |
| 215 | clocks = <&spi1_clk>; | ||
| 216 | clock-names = "spi_clk"; | ||
| 190 | status = "disabled"; | 217 | status = "disabled"; |
| 191 | }; | 218 | }; |
| 192 | 219 | ||
| @@ -196,6 +223,8 @@ | |||
| 196 | interrupts = <39 IRQ_TYPE_LEVEL_HIGH 4>; | 223 | interrupts = <39 IRQ_TYPE_LEVEL_HIGH 4>; |
| 197 | pinctrl-names = "default"; | 224 | pinctrl-names = "default"; |
| 198 | pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; | 225 | pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; |
| 226 | clocks = <&ssc1_clk>; | ||
| 227 | clock-names = "pclk"; | ||
| 199 | status = "disabled"; | 228 | status = "disabled"; |
| 200 | }; | 229 | }; |
| 201 | 230 | ||
| @@ -219,6 +248,9 @@ | |||
| 219 | &pinctrl_adc0_ad10 | 248 | &pinctrl_adc0_ad10 |
| 220 | &pinctrl_adc0_ad11 | 249 | &pinctrl_adc0_ad11 |
| 221 | >; | 250 | >; |
| 251 | clocks = <&adc_clk>, | ||
| 252 | <&adc_op_clk>; | ||
| 253 | clock-names = "adc_clk", "adc_op_clk"; | ||
| 222 | atmel,adc-channel-base = <0x50>; | 254 | atmel,adc-channel-base = <0x50>; |
| 223 | atmel,adc-channels-used = <0xfff>; | 255 | atmel,adc-channels-used = <0xfff>; |
| 224 | atmel,adc-drdy-mask = <0x1000000>; | 256 | atmel,adc-drdy-mask = <0x1000000>; |
| @@ -272,8 +304,11 @@ | |||
| 272 | dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(11)>, | 304 | dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(11)>, |
| 273 | <&dma1 2 AT91_DMA_CFG_PER_ID(12)>; | 305 | <&dma1 2 AT91_DMA_CFG_PER_ID(12)>; |
| 274 | dma-names = "tx", "rx"; | 306 | dma-names = "tx", "rx"; |
| 307 | pinctrl-names = "default"; | ||
| 308 | pinctrl-0 = <&pinctrl_i2c2>; | ||
| 275 | #address-cells = <1>; | 309 | #address-cells = <1>; |
| 276 | #size-cells = <0>; | 310 | #size-cells = <0>; |
| 311 | clocks = <&twi2_clk>; | ||
| 277 | status = "disabled"; | 312 | status = "disabled"; |
| 278 | }; | 313 | }; |
| 279 | 314 | ||
| @@ -283,6 +318,8 @@ | |||
| 283 | interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; | 318 | interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; |
| 284 | pinctrl-names = "default"; | 319 | pinctrl-names = "default"; |
| 285 | pinctrl-0 = <&pinctrl_usart2>; | 320 | pinctrl-0 = <&pinctrl_usart2>; |
| 321 | clocks = <&usart2_clk>; | ||
| 322 | clock-names = "usart"; | ||
| 286 | status = "disabled"; | 323 | status = "disabled"; |
| 287 | }; | 324 | }; |
| 288 | 325 | ||
| @@ -292,25 +329,35 @@ | |||
| 292 | interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; | 329 | interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; |
| 293 | pinctrl-names = "default"; | 330 | pinctrl-names = "default"; |
| 294 | pinctrl-0 = <&pinctrl_usart3>; | 331 | pinctrl-0 = <&pinctrl_usart3>; |
| 332 | clocks = <&usart3_clk>; | ||
| 333 | clock-names = "usart"; | ||
| 295 | status = "disabled"; | 334 | status = "disabled"; |
| 296 | }; | 335 | }; |
| 297 | 336 | ||
| 298 | sha@f8034000 { | 337 | sha@f8034000 { |
| 299 | compatible = "atmel,sam9g46-sha"; | 338 | compatible = "atmel,at91sam9g46-sha"; |
| 300 | reg = <0xf8034000 0x100>; | 339 | reg = <0xf8034000 0x100>; |
| 301 | interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>; | 340 | interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>; |
| 341 | dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(17)>; | ||
| 342 | dma-names = "tx"; | ||
| 302 | }; | 343 | }; |
| 303 | 344 | ||
| 304 | aes@f8038000 { | 345 | aes@f8038000 { |
| 305 | compatible = "atmel,sam9g46-aes"; | 346 | compatible = "atmel,at91sam9g46-aes"; |
| 306 | reg = <0xf8038000 0x100>; | 347 | reg = <0xf8038000 0x100>; |
| 307 | interrupts = <43 4 0>; | 348 | interrupts = <43 IRQ_TYPE_LEVEL_HIGH 0>; |
| 349 | dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(18)>, | ||
| 350 | <&dma1 2 AT91_DMA_CFG_PER_ID(19)>; | ||
| 351 | dma-names = "tx", "rx"; | ||
| 308 | }; | 352 | }; |
| 309 | 353 | ||
| 310 | tdes@f803c000 { | 354 | tdes@f803c000 { |
| 311 | compatible = "atmel,sam9g46-tdes"; | 355 | compatible = "atmel,at91sam9g46-tdes"; |
| 312 | reg = <0xf803c000 0x100>; | 356 | reg = <0xf803c000 0x100>; |
| 313 | interrupts = <44 IRQ_TYPE_LEVEL_HIGH 0>; | 357 | interrupts = <44 IRQ_TYPE_LEVEL_HIGH 0>; |
| 358 | dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(20)>, | ||
| 359 | <&dma1 2 AT91_DMA_CFG_PER_ID(21)>; | ||
| 360 | dma-names = "tx", "rx"; | ||
| 314 | }; | 361 | }; |
| 315 | 362 | ||
| 316 | dma0: dma-controller@ffffe600 { | 363 | dma0: dma-controller@ffffe600 { |
| @@ -318,6 +365,8 @@ | |||
| 318 | reg = <0xffffe600 0x200>; | 365 | reg = <0xffffe600 0x200>; |
| 319 | interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>; | 366 | interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>; |
| 320 | #dma-cells = <2>; | 367 | #dma-cells = <2>; |
| 368 | clocks = <&dma0_clk>; | ||
| 369 | clock-names = "dma_clk"; | ||
| 321 | }; | 370 | }; |
| 322 | 371 | ||
| 323 | dma1: dma-controller@ffffe800 { | 372 | dma1: dma-controller@ffffe800 { |
| @@ -325,6 +374,8 @@ | |||
| 325 | reg = <0xffffe800 0x200>; | 374 | reg = <0xffffe800 0x200>; |
| 326 | interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>; | 375 | interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>; |
| 327 | #dma-cells = <2>; | 376 | #dma-cells = <2>; |
| 377 | clocks = <&dma1_clk>; | ||
| 378 | clock-names = "dma_clk"; | ||
| 328 | }; | 379 | }; |
| 329 | 380 | ||
| 330 | ramc0: ramc@ffffea00 { | 381 | ramc0: ramc@ffffea00 { |
| @@ -338,6 +389,8 @@ | |||
| 338 | interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>; | 389 | interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>; |
| 339 | pinctrl-names = "default"; | 390 | pinctrl-names = "default"; |
| 340 | pinctrl-0 = <&pinctrl_dbgu>; | 391 | pinctrl-0 = <&pinctrl_dbgu>; |
| 392 | clocks = <&dbgu_clk>; | ||
| 393 | clock-names = "usart"; | ||
| 341 | status = "disabled"; | 394 | status = "disabled"; |
| 342 | }; | 395 | }; |
| 343 | 396 | ||
| @@ -443,6 +496,14 @@ | |||
| 443 | }; | 496 | }; |
| 444 | }; | 497 | }; |
| 445 | 498 | ||
| 499 | i2c2 { | ||
| 500 | pinctrl_i2c2: i2c2-0 { | ||
| 501 | atmel,pins = | ||
| 502 | <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* TWD2 pin, conflicts with LCDDAT18, ISI_D2 */ | ||
| 503 | AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TWCK2 pin, conflicts with LCDDAT19, ISI_D3 */ | ||
| 504 | }; | ||
| 505 | }; | ||
| 506 | |||
| 446 | isi { | 507 | isi { |
| 447 | pinctrl_isi: isi-0 { | 508 | pinctrl_isi: isi-0 { |
| 448 | atmel,pins = | 509 | atmel,pins = |
| @@ -626,6 +687,7 @@ | |||
| 626 | gpio-controller; | 687 | gpio-controller; |
| 627 | interrupt-controller; | 688 | interrupt-controller; |
| 628 | #interrupt-cells = <2>; | 689 | #interrupt-cells = <2>; |
| 690 | clocks = <&pioA_clk>; | ||
| 629 | }; | 691 | }; |
| 630 | 692 | ||
| 631 | pioB: gpio@fffff400 { | 693 | pioB: gpio@fffff400 { |
| @@ -636,6 +698,7 @@ | |||
| 636 | gpio-controller; | 698 | gpio-controller; |
| 637 | interrupt-controller; | 699 | interrupt-controller; |
| 638 | #interrupt-cells = <2>; | 700 | #interrupt-cells = <2>; |
| 701 | clocks = <&pioB_clk>; | ||
| 639 | }; | 702 | }; |
| 640 | 703 | ||
| 641 | pioC: gpio@fffff600 { | 704 | pioC: gpio@fffff600 { |
| @@ -646,6 +709,7 @@ | |||
| 646 | gpio-controller; | 709 | gpio-controller; |
| 647 | interrupt-controller; | 710 | interrupt-controller; |
| 648 | #interrupt-cells = <2>; | 711 | #interrupt-cells = <2>; |
| 712 | clocks = <&pioC_clk>; | ||
| 649 | }; | 713 | }; |
| 650 | 714 | ||
| 651 | pioD: gpio@fffff800 { | 715 | pioD: gpio@fffff800 { |
| @@ -656,6 +720,7 @@ | |||
| 656 | gpio-controller; | 720 | gpio-controller; |
| 657 | interrupt-controller; | 721 | interrupt-controller; |
| 658 | #interrupt-cells = <2>; | 722 | #interrupt-cells = <2>; |
| 723 | clocks = <&pioD_clk>; | ||
| 659 | }; | 724 | }; |
| 660 | 725 | ||
| 661 | pioE: gpio@fffffa00 { | 726 | pioE: gpio@fffffa00 { |
| @@ -666,12 +731,334 @@ | |||
| 666 | gpio-controller; | 731 | gpio-controller; |
| 667 | interrupt-controller; | 732 | interrupt-controller; |
| 668 | #interrupt-cells = <2>; | 733 | #interrupt-cells = <2>; |
| 734 | clocks = <&pioE_clk>; | ||
| 669 | }; | 735 | }; |
| 670 | }; | 736 | }; |
| 671 | 737 | ||
| 672 | pmc: pmc@fffffc00 { | 738 | pmc: pmc@fffffc00 { |
| 673 | compatible = "atmel,at91rm9200-pmc"; | 739 | compatible = "atmel,sama5d3-pmc"; |
| 674 | reg = <0xfffffc00 0x120>; | 740 | reg = <0xfffffc00 0x120>; |
| 741 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; | ||
| 742 | interrupt-controller; | ||
| 743 | #address-cells = <1>; | ||
| 744 | #size-cells = <0>; | ||
| 745 | #interrupt-cells = <1>; | ||
| 746 | |||
| 747 | clk32k: slck { | ||
| 748 | compatible = "fixed-clock"; | ||
| 749 | #clock-cells = <0>; | ||
| 750 | clock-frequency = <32768>; | ||
| 751 | }; | ||
| 752 | |||
| 753 | main: mainck { | ||
| 754 | compatible = "atmel,at91rm9200-clk-main"; | ||
| 755 | #clock-cells = <0>; | ||
| 756 | interrupt-parent = <&pmc>; | ||
| 757 | interrupts = <AT91_PMC_MOSCS>; | ||
| 758 | clocks = <&clk32k>; | ||
| 759 | }; | ||
| 760 | |||
| 761 | plla: pllack { | ||
| 762 | compatible = "atmel,sama5d3-clk-pll"; | ||
| 763 | #clock-cells = <0>; | ||
| 764 | interrupt-parent = <&pmc>; | ||
| 765 | interrupts = <AT91_PMC_LOCKA>; | ||
| 766 | clocks = <&main>; | ||
| 767 | reg = <0>; | ||
| 768 | atmel,clk-input-range = <8000000 50000000>; | ||
| 769 | #atmel,pll-clk-output-range-cells = <4>; | ||
| 770 | atmel,pll-clk-output-ranges = <400000000 1000000000 0 0>; | ||
| 771 | }; | ||
| 772 | |||
| 773 | plladiv: plladivck { | ||
| 774 | compatible = "atmel,at91sam9x5-clk-plldiv"; | ||
| 775 | #clock-cells = <0>; | ||
| 776 | clocks = <&plla>; | ||
| 777 | }; | ||
| 778 | |||
| 779 | utmi: utmick { | ||
| 780 | compatible = "atmel,at91sam9x5-clk-utmi"; | ||
| 781 | #clock-cells = <0>; | ||
| 782 | interrupt-parent = <&pmc>; | ||
| 783 | interrupts = <AT91_PMC_LOCKU>; | ||
| 784 | clocks = <&main>; | ||
| 785 | }; | ||
| 786 | |||
| 787 | mck: masterck { | ||
| 788 | compatible = "atmel,at91sam9x5-clk-master"; | ||
| 789 | #clock-cells = <0>; | ||
| 790 | interrupt-parent = <&pmc>; | ||
| 791 | interrupts = <AT91_PMC_MCKRDY>; | ||
| 792 | clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>; | ||
| 793 | atmel,clk-output-range = <0 166000000>; | ||
| 794 | atmel,clk-divisors = <1 2 4 3>; | ||
| 795 | }; | ||
| 796 | |||
| 797 | usb: usbck { | ||
| 798 | compatible = "atmel,at91sam9x5-clk-usb"; | ||
| 799 | #clock-cells = <0>; | ||
| 800 | clocks = <&plladiv>, <&utmi>; | ||
| 801 | }; | ||
| 802 | |||
| 803 | prog: progck { | ||
| 804 | compatible = "atmel,at91sam9x5-clk-programmable"; | ||
| 805 | #address-cells = <1>; | ||
| 806 | #size-cells = <0>; | ||
| 807 | interrupt-parent = <&pmc>; | ||
| 808 | clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; | ||
| 809 | |||
| 810 | prog0: prog0 { | ||
| 811 | #clock-cells = <0>; | ||
| 812 | reg = <0>; | ||
| 813 | interrupts = <AT91_PMC_PCKRDY(0)>; | ||
| 814 | }; | ||
| 815 | |||
| 816 | prog1: prog1 { | ||
| 817 | #clock-cells = <0>; | ||
| 818 | reg = <1>; | ||
| 819 | interrupts = <AT91_PMC_PCKRDY(1)>; | ||
| 820 | }; | ||
| 821 | |||
| 822 | prog2: prog2 { | ||
| 823 | #clock-cells = <0>; | ||
| 824 | reg = <2>; | ||
| 825 | interrupts = <AT91_PMC_PCKRDY(2)>; | ||
| 826 | }; | ||
| 827 | }; | ||
| 828 | |||
| 829 | smd: smdclk { | ||
| 830 | compatible = "atmel,at91sam9x5-clk-smd"; | ||
| 831 | #clock-cells = <0>; | ||
| 832 | clocks = <&plladiv>, <&utmi>; | ||
| 833 | }; | ||
| 834 | |||
| 835 | systemck { | ||
| 836 | compatible = "atmel,at91rm9200-clk-system"; | ||
| 837 | #address-cells = <1>; | ||
| 838 | #size-cells = <0>; | ||
| 839 | |||
| 840 | ddrck: ddrck { | ||
| 841 | #clock-cells = <0>; | ||
| 842 | reg = <2>; | ||
| 843 | clocks = <&mck>; | ||
| 844 | }; | ||
| 845 | |||
| 846 | smdck: smdck { | ||
| 847 | #clock-cells = <0>; | ||
| 848 | reg = <4>; | ||
| 849 | clocks = <&smd>; | ||
| 850 | }; | ||
| 851 | |||
| 852 | uhpck: uhpck { | ||
| 853 | #clock-cells = <0>; | ||
| 854 | reg = <6>; | ||
| 855 | clocks = <&usb>; | ||
| 856 | }; | ||
| 857 | |||
| 858 | udpck: udpck { | ||
| 859 | #clock-cells = <0>; | ||
| 860 | reg = <7>; | ||
| 861 | clocks = <&usb>; | ||
| 862 | }; | ||
| 863 | |||
| 864 | pck0: pck0 { | ||
| 865 | #clock-cells = <0>; | ||
| 866 | reg = <8>; | ||
| 867 | clocks = <&prog0>; | ||
| 868 | }; | ||
| 869 | |||
| 870 | pck1: pck1 { | ||
| 871 | #clock-cells = <0>; | ||
| 872 | reg = <9>; | ||
| 873 | clocks = <&prog1>; | ||
| 874 | }; | ||
| 875 | |||
| 876 | pck2: pck2 { | ||
| 877 | #clock-cells = <0>; | ||
| 878 | reg = <10>; | ||
| 879 | clocks = <&prog2>; | ||
| 880 | }; | ||
| 881 | }; | ||
| 882 | |||
| 883 | periphck { | ||
| 884 | compatible = "atmel,at91sam9x5-clk-peripheral"; | ||
| 885 | #address-cells = <1>; | ||
| 886 | #size-cells = <0>; | ||
| 887 | clocks = <&mck>; | ||
| 888 | |||
| 889 | dbgu_clk: dbgu_clk { | ||
| 890 | #clock-cells = <0>; | ||
| 891 | reg = <2>; | ||
| 892 | }; | ||
| 893 | |||
| 894 | pioA_clk: pioA_clk { | ||
| 895 | #clock-cells = <0>; | ||
| 896 | reg = <6>; | ||
| 897 | }; | ||
| 898 | |||
| 899 | pioB_clk: pioB_clk { | ||
| 900 | #clock-cells = <0>; | ||
| 901 | reg = <7>; | ||
| 902 | }; | ||
| 903 | |||
| 904 | pioC_clk: pioC_clk { | ||
| 905 | #clock-cells = <0>; | ||
| 906 | reg = <8>; | ||
| 907 | }; | ||
| 908 | |||
| 909 | pioD_clk: pioD_clk { | ||
| 910 | #clock-cells = <0>; | ||
| 911 | reg = <9>; | ||
| 912 | }; | ||
| 913 | |||
| 914 | pioE_clk: pioE_clk { | ||
| 915 | #clock-cells = <0>; | ||
| 916 | reg = <10>; | ||
| 917 | }; | ||
| 918 | |||
| 919 | usart0_clk: usart0_clk { | ||
| 920 | #clock-cells = <0>; | ||
| 921 | reg = <12>; | ||
| 922 | atmel,clk-output-range = <0 66000000>; | ||
| 923 | }; | ||
| 924 | |||
| 925 | usart1_clk: usart1_clk { | ||
| 926 | #clock-cells = <0>; | ||
| 927 | reg = <13>; | ||
| 928 | atmel,clk-output-range = <0 66000000>; | ||
| 929 | }; | ||
| 930 | |||
| 931 | usart2_clk: usart2_clk { | ||
| 932 | #clock-cells = <0>; | ||
| 933 | reg = <14>; | ||
| 934 | atmel,clk-output-range = <0 66000000>; | ||
| 935 | }; | ||
| 936 | |||
| 937 | usart3_clk: usart3_clk { | ||
| 938 | #clock-cells = <0>; | ||
| 939 | reg = <15>; | ||
| 940 | atmel,clk-output-range = <0 66000000>; | ||
| 941 | }; | ||
| 942 | |||
| 943 | twi0_clk: twi0_clk { | ||
| 944 | reg = <18>; | ||
| 945 | #clock-cells = <0>; | ||
| 946 | atmel,clk-output-range = <0 16625000>; | ||
| 947 | }; | ||
| 948 | |||
| 949 | twi1_clk: twi1_clk { | ||
| 950 | #clock-cells = <0>; | ||
| 951 | reg = <19>; | ||
| 952 | atmel,clk-output-range = <0 16625000>; | ||
| 953 | }; | ||
| 954 | |||
| 955 | twi2_clk: twi2_clk { | ||
| 956 | #clock-cells = <0>; | ||
| 957 | reg = <20>; | ||
| 958 | atmel,clk-output-range = <0 16625000>; | ||
| 959 | }; | ||
| 960 | |||
| 961 | mci0_clk: mci0_clk { | ||
| 962 | #clock-cells = <0>; | ||
| 963 | reg = <21>; | ||
| 964 | }; | ||
| 965 | |||
| 966 | mci1_clk: mci1_clk { | ||
| 967 | #clock-cells = <0>; | ||
| 968 | reg = <22>; | ||
| 969 | }; | ||
| 970 | |||
| 971 | spi0_clk: spi0_clk { | ||
| 972 | #clock-cells = <0>; | ||
| 973 | reg = <24>; | ||
| 974 | atmel,clk-output-range = <0 133000000>; | ||
| 975 | }; | ||
| 976 | |||
| 977 | spi1_clk: spi1_clk { | ||
| 978 | #clock-cells = <0>; | ||
| 979 | reg = <25>; | ||
| 980 | atmel,clk-output-range = <0 133000000>; | ||
| 981 | }; | ||
| 982 | |||
| 983 | tcb0_clk: tcb0_clk { | ||
| 984 | #clock-cells = <0>; | ||
| 985 | reg = <26>; | ||
| 986 | atmel,clk-output-range = <0 133000000>; | ||
| 987 | }; | ||
| 988 | |||
| 989 | pwm_clk: pwm_clk { | ||
| 990 | #clock-cells = <0>; | ||
| 991 | reg = <28>; | ||
| 992 | }; | ||
| 993 | |||
| 994 | adc_clk: adc_clk { | ||
| 995 | #clock-cells = <0>; | ||
| 996 | reg = <29>; | ||
| 997 | atmel,clk-output-range = <0 66000000>; | ||
| 998 | }; | ||
| 999 | |||
| 1000 | dma0_clk: dma0_clk { | ||
| 1001 | #clock-cells = <0>; | ||
| 1002 | reg = <30>; | ||
| 1003 | }; | ||
| 1004 | |||
| 1005 | dma1_clk: dma1_clk { | ||
| 1006 | #clock-cells = <0>; | ||
| 1007 | reg = <31>; | ||
| 1008 | }; | ||
| 1009 | |||
| 1010 | uhphs_clk: uhphs_clk { | ||
| 1011 | #clock-cells = <0>; | ||
| 1012 | reg = <32>; | ||
| 1013 | }; | ||
| 1014 | |||
| 1015 | udphs_clk: udphs_clk { | ||
| 1016 | #clock-cells = <0>; | ||
| 1017 | reg = <33>; | ||
| 1018 | }; | ||
| 1019 | |||
| 1020 | isi_clk: isi_clk { | ||
| 1021 | #clock-cells = <0>; | ||
| 1022 | reg = <37>; | ||
| 1023 | }; | ||
| 1024 | |||
| 1025 | ssc0_clk: ssc0_clk { | ||
| 1026 | #clock-cells = <0>; | ||
| 1027 | reg = <38>; | ||
| 1028 | atmel,clk-output-range = <0 66000000>; | ||
| 1029 | }; | ||
| 1030 | |||
| 1031 | ssc1_clk: ssc1_clk { | ||
| 1032 | #clock-cells = <0>; | ||
| 1033 | reg = <39>; | ||
| 1034 | atmel,clk-output-range = <0 66000000>; | ||
| 1035 | }; | ||
| 1036 | |||
| 1037 | sha_clk: sha_clk { | ||
| 1038 | #clock-cells = <0>; | ||
| 1039 | reg = <42>; | ||
| 1040 | }; | ||
| 1041 | |||
| 1042 | aes_clk: aes_clk { | ||
| 1043 | #clock-cells = <0>; | ||
| 1044 | reg = <43>; | ||
| 1045 | }; | ||
| 1046 | |||
| 1047 | tdes_clk: tdes_clk { | ||
| 1048 | #clock-cells = <0>; | ||
| 1049 | reg = <44>; | ||
| 1050 | }; | ||
| 1051 | |||
| 1052 | trng_clk: trng_clk { | ||
| 1053 | #clock-cells = <0>; | ||
| 1054 | reg = <45>; | ||
| 1055 | }; | ||
| 1056 | |||
| 1057 | fuse_clk: fuse_clk { | ||
| 1058 | #clock-cells = <0>; | ||
| 1059 | reg = <48>; | ||
| 1060 | }; | ||
| 1061 | }; | ||
| 675 | }; | 1062 | }; |
| 676 | 1063 | ||
| 677 | rstc@fffffe00 { | 1064 | rstc@fffffe00 { |
| @@ -683,6 +1070,7 @@ | |||
| 683 | compatible = "atmel,at91sam9260-pit"; | 1070 | compatible = "atmel,at91sam9260-pit"; |
| 684 | reg = <0xfffffe30 0xf>; | 1071 | reg = <0xfffffe30 0xf>; |
| 685 | interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; | 1072 | interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; |
| 1073 | clocks = <&mck>; | ||
| 686 | }; | 1074 | }; |
| 687 | 1075 | ||
| 688 | watchdog@fffffe40 { | 1076 | watchdog@fffffe40 { |
| @@ -705,6 +1093,8 @@ | |||
| 705 | reg = <0x00500000 0x100000 | 1093 | reg = <0x00500000 0x100000 |
| 706 | 0xf8030000 0x4000>; | 1094 | 0xf8030000 0x4000>; |
| 707 | interrupts = <33 IRQ_TYPE_LEVEL_HIGH 2>; | 1095 | interrupts = <33 IRQ_TYPE_LEVEL_HIGH 2>; |
| 1096 | clocks = <&udphs_clk>, <&utmi>; | ||
| 1097 | clock-names = "pclk", "hclk"; | ||
| 708 | status = "disabled"; | 1098 | status = "disabled"; |
| 709 | 1099 | ||
| 710 | ep0 { | 1100 | ep0 { |
| @@ -817,6 +1207,9 @@ | |||
| 817 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; | 1207 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; |
| 818 | reg = <0x00600000 0x100000>; | 1208 | reg = <0x00600000 0x100000>; |
| 819 | interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; | 1209 | interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; |
| 1210 | clocks = <&usb>, <&uhphs_clk>, <&udphs_clk>, | ||
| 1211 | <&uhpck>; | ||
| 1212 | clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck"; | ||
| 820 | status = "disabled"; | 1213 | status = "disabled"; |
| 821 | }; | 1214 | }; |
| 822 | 1215 | ||
| @@ -824,6 +1217,8 @@ | |||
| 824 | compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; | 1217 | compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; |
| 825 | reg = <0x00700000 0x100000>; | 1218 | reg = <0x00700000 0x100000>; |
| 826 | interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; | 1219 | interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; |
| 1220 | clocks = <&usb>, <&uhphs_clk>, <&uhpck>; | ||
| 1221 | clock-names = "usb_clk", "ehci_clk", "uhpck"; | ||
| 827 | status = "disabled"; | 1222 | status = "disabled"; |
| 828 | }; | 1223 | }; |
| 829 | 1224 | ||
diff --git a/arch/arm/boot/dts/sama5d3_can.dtsi b/arch/arm/boot/dts/sama5d3_can.dtsi index 8ed3260cef66..a0775851cce5 100644 --- a/arch/arm/boot/dts/sama5d3_can.dtsi +++ b/arch/arm/boot/dts/sama5d3_can.dtsi | |||
| @@ -32,12 +32,30 @@ | |||
| 32 | 32 | ||
| 33 | }; | 33 | }; |
| 34 | 34 | ||
| 35 | pmc: pmc@fffffc00 { | ||
| 36 | periphck { | ||
| 37 | can0_clk: can0_clk { | ||
| 38 | #clock-cells = <0>; | ||
| 39 | reg = <40>; | ||
| 40 | atmel,clk-output-range = <0 66000000>; | ||
| 41 | }; | ||
| 42 | |||
| 43 | can1_clk: can0_clk { | ||
| 44 | #clock-cells = <0>; | ||
| 45 | reg = <41>; | ||
| 46 | atmel,clk-output-range = <0 66000000>; | ||
| 47 | }; | ||
| 48 | }; | ||
| 49 | }; | ||
| 50 | |||
| 35 | can0: can@f000c000 { | 51 | can0: can@f000c000 { |
| 36 | compatible = "atmel,at91sam9x5-can"; | 52 | compatible = "atmel,at91sam9x5-can"; |
| 37 | reg = <0xf000c000 0x300>; | 53 | reg = <0xf000c000 0x300>; |
| 38 | interrupts = <40 IRQ_TYPE_LEVEL_HIGH 3>; | 54 | interrupts = <40 IRQ_TYPE_LEVEL_HIGH 3>; |
| 39 | pinctrl-names = "default"; | 55 | pinctrl-names = "default"; |
| 40 | pinctrl-0 = <&pinctrl_can0_rx_tx>; | 56 | pinctrl-0 = <&pinctrl_can0_rx_tx>; |
| 57 | clocks = <&can0_clk>; | ||
| 58 | clock-names = "can_clk"; | ||
| 41 | status = "disabled"; | 59 | status = "disabled"; |
| 42 | }; | 60 | }; |
| 43 | 61 | ||
| @@ -47,6 +65,8 @@ | |||
| 47 | interrupts = <41 IRQ_TYPE_LEVEL_HIGH 3>; | 65 | interrupts = <41 IRQ_TYPE_LEVEL_HIGH 3>; |
| 48 | pinctrl-names = "default"; | 66 | pinctrl-names = "default"; |
| 49 | pinctrl-0 = <&pinctrl_can1_rx_tx>; | 67 | pinctrl-0 = <&pinctrl_can1_rx_tx>; |
| 68 | clocks = <&can1_clk>; | ||
| 69 | clock-names = "can_clk"; | ||
| 50 | status = "disabled"; | 70 | status = "disabled"; |
| 51 | }; | 71 | }; |
| 52 | }; | 72 | }; |
diff --git a/arch/arm/boot/dts/sama5d3_emac.dtsi b/arch/arm/boot/dts/sama5d3_emac.dtsi index 4d4f351f1f9f..fe2af9276312 100644 --- a/arch/arm/boot/dts/sama5d3_emac.dtsi +++ b/arch/arm/boot/dts/sama5d3_emac.dtsi | |||
| @@ -31,12 +31,23 @@ | |||
| 31 | }; | 31 | }; |
| 32 | }; | 32 | }; |
| 33 | 33 | ||
| 34 | pmc: pmc@fffffc00 { | ||
| 35 | periphck { | ||
| 36 | macb1_clk: macb1_clk { | ||
| 37 | #clock-cells = <0>; | ||
| 38 | reg = <35>; | ||
| 39 | }; | ||
| 40 | }; | ||
| 41 | }; | ||
| 42 | |||
| 34 | macb1: ethernet@f802c000 { | 43 | macb1: ethernet@f802c000 { |
| 35 | compatible = "cdns,at32ap7000-macb", "cdns,macb"; | 44 | compatible = "cdns,at32ap7000-macb", "cdns,macb"; |
| 36 | reg = <0xf802c000 0x100>; | 45 | reg = <0xf802c000 0x100>; |
| 37 | interrupts = <35 IRQ_TYPE_LEVEL_HIGH 3>; | 46 | interrupts = <35 IRQ_TYPE_LEVEL_HIGH 3>; |
| 38 | pinctrl-names = "default"; | 47 | pinctrl-names = "default"; |
| 39 | pinctrl-0 = <&pinctrl_macb1_rmii>; | 48 | pinctrl-0 = <&pinctrl_macb1_rmii>; |
| 49 | clocks = <&macb1_clk>, <&macb1_clk>; | ||
| 50 | clock-names = "hclk", "pclk"; | ||
| 40 | status = "disabled"; | 51 | status = "disabled"; |
| 41 | }; | 52 | }; |
| 42 | }; | 53 | }; |
diff --git a/arch/arm/boot/dts/sama5d3_gmac.dtsi b/arch/arm/boot/dts/sama5d3_gmac.dtsi index 0ba8be30ccd8..a6cb0508762f 100644 --- a/arch/arm/boot/dts/sama5d3_gmac.dtsi +++ b/arch/arm/boot/dts/sama5d3_gmac.dtsi | |||
| @@ -64,12 +64,23 @@ | |||
| 64 | }; | 64 | }; |
| 65 | }; | 65 | }; |
| 66 | 66 | ||
| 67 | pmc: pmc@fffffc00 { | ||
| 68 | periphck { | ||
| 69 | macb0_clk: macb0_clk { | ||
| 70 | #clock-cells = <0>; | ||
| 71 | reg = <34>; | ||
| 72 | }; | ||
| 73 | }; | ||
| 74 | }; | ||
| 75 | |||
| 67 | macb0: ethernet@f0028000 { | 76 | macb0: ethernet@f0028000 { |
| 68 | compatible = "cdns,pc302-gem", "cdns,gem"; | 77 | compatible = "cdns,pc302-gem", "cdns,gem"; |
| 69 | reg = <0xf0028000 0x100>; | 78 | reg = <0xf0028000 0x100>; |
| 70 | interrupts = <34 IRQ_TYPE_LEVEL_HIGH 3>; | 79 | interrupts = <34 IRQ_TYPE_LEVEL_HIGH 3>; |
| 71 | pinctrl-names = "default"; | 80 | pinctrl-names = "default"; |
| 72 | pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>; | 81 | pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>; |
| 82 | clocks = <&macb0_clk>, <&macb0_clk>; | ||
| 83 | clock-names = "hclk", "pclk"; | ||
| 73 | status = "disabled"; | 84 | status = "disabled"; |
| 74 | }; | 85 | }; |
| 75 | }; | 86 | }; |
diff --git a/arch/arm/boot/dts/sama5d3_lcd.dtsi b/arch/arm/boot/dts/sama5d3_lcd.dtsi index 01f52a79f8ba..85d302701565 100644 --- a/arch/arm/boot/dts/sama5d3_lcd.dtsi +++ b/arch/arm/boot/dts/sama5d3_lcd.dtsi | |||
| @@ -50,6 +50,23 @@ | |||
| 50 | }; | 50 | }; |
| 51 | }; | 51 | }; |
| 52 | }; | 52 | }; |
| 53 | |||
| 54 | pmc: pmc@fffffc00 { | ||
| 55 | periphck { | ||
| 56 | lcdc_clk: lcdc_clk { | ||
| 57 | #clock-cells = <0>; | ||
| 58 | reg = <36>; | ||
| 59 | }; | ||
| 60 | }; | ||
| 61 | |||
| 62 | systemck { | ||
| 63 | lcdck: lcdck { | ||
| 64 | #clock-cells = <0>; | ||
| 65 | reg = <3>; | ||
| 66 | clocks = <&mck>; | ||
| 67 | }; | ||
| 68 | }; | ||
| 69 | }; | ||
| 53 | }; | 70 | }; |
| 54 | }; | 71 | }; |
| 55 | }; | 72 | }; |
diff --git a/arch/arm/boot/dts/sama5d3_mci2.dtsi b/arch/arm/boot/dts/sama5d3_mci2.dtsi index 38e88e39e551..b029fe7ef17a 100644 --- a/arch/arm/boot/dts/sama5d3_mci2.dtsi +++ b/arch/arm/boot/dts/sama5d3_mci2.dtsi | |||
| @@ -9,6 +9,7 @@ | |||
| 9 | 9 | ||
| 10 | #include <dt-bindings/pinctrl/at91.h> | 10 | #include <dt-bindings/pinctrl/at91.h> |
| 11 | #include <dt-bindings/interrupt-controller/irq.h> | 11 | #include <dt-bindings/interrupt-controller/irq.h> |
| 12 | #include <dt-bindings/clk/at91.h> | ||
| 12 | 13 | ||
| 13 | / { | 14 | / { |
| 14 | ahb { | 15 | ahb { |
| @@ -30,6 +31,15 @@ | |||
| 30 | }; | 31 | }; |
| 31 | }; | 32 | }; |
| 32 | 33 | ||
| 34 | pmc: pmc@fffffc00 { | ||
| 35 | periphck { | ||
| 36 | mci2_clk: mci2_clk { | ||
| 37 | #clock-cells = <0>; | ||
| 38 | reg = <23>; | ||
| 39 | }; | ||
| 40 | }; | ||
| 41 | }; | ||
| 42 | |||
| 33 | mmc2: mmc@f8004000 { | 43 | mmc2: mmc@f8004000 { |
| 34 | compatible = "atmel,hsmci"; | 44 | compatible = "atmel,hsmci"; |
| 35 | reg = <0xf8004000 0x600>; | 45 | reg = <0xf8004000 0x600>; |
| @@ -38,6 +48,8 @@ | |||
| 38 | dma-names = "rxtx"; | 48 | dma-names = "rxtx"; |
| 39 | pinctrl-names = "default"; | 49 | pinctrl-names = "default"; |
| 40 | pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>; | 50 | pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>; |
| 51 | clocks = <&mci2_clk>; | ||
| 52 | clock-names = "mci_clk"; | ||
| 41 | status = "disabled"; | 53 | status = "disabled"; |
| 42 | #address-cells = <1>; | 54 | #address-cells = <1>; |
| 43 | #size-cells = <0>; | 55 | #size-cells = <0>; |
diff --git a/arch/arm/boot/dts/sama5d3_tcb1.dtsi b/arch/arm/boot/dts/sama5d3_tcb1.dtsi index 5264bb4a6998..382b04431f66 100644 --- a/arch/arm/boot/dts/sama5d3_tcb1.dtsi +++ b/arch/arm/boot/dts/sama5d3_tcb1.dtsi | |||
| @@ -9,6 +9,7 @@ | |||
| 9 | 9 | ||
| 10 | #include <dt-bindings/pinctrl/at91.h> | 10 | #include <dt-bindings/pinctrl/at91.h> |
| 11 | #include <dt-bindings/interrupt-controller/irq.h> | 11 | #include <dt-bindings/interrupt-controller/irq.h> |
| 12 | #include <dt-bindings/clk/at91.h> | ||
| 12 | 13 | ||
| 13 | / { | 14 | / { |
| 14 | aliases { | 15 | aliases { |
| @@ -17,10 +18,21 @@ | |||
| 17 | 18 | ||
| 18 | ahb { | 19 | ahb { |
| 19 | apb { | 20 | apb { |
| 21 | pmc: pmc@fffffc00 { | ||
| 22 | periphck { | ||
| 23 | tcb1_clk: tcb1_clk { | ||
| 24 | #clock-cells = <0>; | ||
| 25 | reg = <27>; | ||
| 26 | }; | ||
| 27 | }; | ||
| 28 | }; | ||
| 29 | |||
| 20 | tcb1: timer@f8014000 { | 30 | tcb1: timer@f8014000 { |
| 21 | compatible = "atmel,at91sam9x5-tcb"; | 31 | compatible = "atmel,at91sam9x5-tcb"; |
| 22 | reg = <0xf8014000 0x100>; | 32 | reg = <0xf8014000 0x100>; |
| 23 | interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>; | 33 | interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>; |
| 34 | clocks = <&tcb1_clk>; | ||
| 35 | clock-names = "t0_clk"; | ||
| 24 | }; | 36 | }; |
| 25 | }; | 37 | }; |
| 26 | }; | 38 | }; |
diff --git a/arch/arm/boot/dts/sama5d3_uart.dtsi b/arch/arm/boot/dts/sama5d3_uart.dtsi index 98fcb2d57446..a9fa75e41652 100644 --- a/arch/arm/boot/dts/sama5d3_uart.dtsi +++ b/arch/arm/boot/dts/sama5d3_uart.dtsi | |||
| @@ -9,8 +9,14 @@ | |||
| 9 | 9 | ||
| 10 | #include <dt-bindings/pinctrl/at91.h> | 10 | #include <dt-bindings/pinctrl/at91.h> |
| 11 | #include <dt-bindings/interrupt-controller/irq.h> | 11 | #include <dt-bindings/interrupt-controller/irq.h> |
| 12 | #include <dt-bindings/clk/at91.h> | ||
| 12 | 13 | ||
| 13 | / { | 14 | / { |
| 15 | aliases { | ||
| 16 | serial5 = &uart0; | ||
| 17 | serial6 = &uart1; | ||
| 18 | }; | ||
| 19 | |||
| 14 | ahb { | 20 | ahb { |
| 15 | apb { | 21 | apb { |
| 16 | pinctrl@fffff200 { | 22 | pinctrl@fffff200 { |
| @@ -31,12 +37,30 @@ | |||
| 31 | }; | 37 | }; |
| 32 | }; | 38 | }; |
| 33 | 39 | ||
| 40 | pmc: pmc@fffffc00 { | ||
| 41 | periphck { | ||
| 42 | uart0_clk: uart0_clk { | ||
| 43 | #clock-cells = <0>; | ||
| 44 | reg = <16>; | ||
| 45 | atmel,clk-output-range = <0 66000000>; | ||
| 46 | }; | ||
| 47 | |||
| 48 | uart1_clk: uart1_clk { | ||
| 49 | #clock-cells = <0>; | ||
| 50 | reg = <17>; | ||
| 51 | atmel,clk-output-range = <0 66000000>; | ||
| 52 | }; | ||
| 53 | }; | ||
| 54 | }; | ||
| 55 | |||
| 34 | uart0: serial@f0024000 { | 56 | uart0: serial@f0024000 { |
| 35 | compatible = "atmel,at91sam9260-usart"; | 57 | compatible = "atmel,at91sam9260-usart"; |
| 36 | reg = <0xf0024000 0x200>; | 58 | reg = <0xf0024000 0x200>; |
| 37 | interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; | 59 | interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; |
| 38 | pinctrl-names = "default"; | 60 | pinctrl-names = "default"; |
| 39 | pinctrl-0 = <&pinctrl_uart0>; | 61 | pinctrl-0 = <&pinctrl_uart0>; |
| 62 | clocks = <&uart0_clk>; | ||
| 63 | clock-names = "usart"; | ||
| 40 | status = "disabled"; | 64 | status = "disabled"; |
| 41 | }; | 65 | }; |
| 42 | 66 | ||
| @@ -46,6 +70,8 @@ | |||
| 46 | interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>; | 70 | interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>; |
| 47 | pinctrl-names = "default"; | 71 | pinctrl-names = "default"; |
| 48 | pinctrl-0 = <&pinctrl_uart1>; | 72 | pinctrl-0 = <&pinctrl_uart1>; |
| 73 | clocks = <&uart1_clk>; | ||
| 74 | clock-names = "usart"; | ||
| 49 | status = "disabled"; | 75 | status = "disabled"; |
| 50 | }; | 76 | }; |
| 51 | }; | 77 | }; |
diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi index 726a0f35100c..f55ed072c8e6 100644 --- a/arch/arm/boot/dts/sama5d3xcm.dtsi +++ b/arch/arm/boot/dts/sama5d3xcm.dtsi | |||
| @@ -18,17 +18,6 @@ | |||
| 18 | reg = <0x20000000 0x20000000>; | 18 | reg = <0x20000000 0x20000000>; |
| 19 | }; | 19 | }; |
| 20 | 20 | ||
| 21 | clocks { | ||
| 22 | #address-cells = <1>; | ||
| 23 | #size-cells = <1>; | ||
| 24 | ranges; | ||
| 25 | |||
| 26 | main_clock: clock@0 { | ||
| 27 | compatible = "atmel,osc", "fixed-clock"; | ||
| 28 | clock-frequency = <12000000>; | ||
| 29 | }; | ||
| 30 | }; | ||
| 31 | |||
| 32 | ahb { | 21 | ahb { |
| 33 | apb { | 22 | apb { |
| 34 | spi0: spi@f0004000 { | 23 | spi0: spi@f0004000 { |
| @@ -38,6 +27,12 @@ | |||
| 38 | macb0: ethernet@f0028000 { | 27 | macb0: ethernet@f0028000 { |
| 39 | phy-mode = "rgmii"; | 28 | phy-mode = "rgmii"; |
| 40 | }; | 29 | }; |
| 30 | |||
| 31 | pmc: pmc@fffffc00 { | ||
| 32 | main: mainck { | ||
| 33 | clock-frequency = <12000000>; | ||
| 34 | }; | ||
| 35 | }; | ||
| 41 | }; | 36 | }; |
| 42 | 37 | ||
| 43 | nand0: nand@60000000 { | 38 | nand0: nand@60000000 { |
diff --git a/arch/arm/boot/dts/sama5d3xdm.dtsi b/arch/arm/boot/dts/sama5d3xdm.dtsi index 1c296d6b2f2a..f9bdde542ced 100644 --- a/arch/arm/boot/dts/sama5d3xdm.dtsi +++ b/arch/arm/boot/dts/sama5d3xdm.dtsi | |||
| @@ -18,6 +18,7 @@ | |||
| 18 | interrupts = <31 0x0>; | 18 | interrupts = <31 0x0>; |
| 19 | pinctrl-names = "default"; | 19 | pinctrl-names = "default"; |
| 20 | pinctrl-0 = <&pinctrl_qt1070_irq>; | 20 | pinctrl-0 = <&pinctrl_qt1070_irq>; |
| 21 | wakeup-source; | ||
| 21 | }; | 22 | }; |
| 22 | }; | 23 | }; |
| 23 | 24 | ||
diff --git a/arch/arm/configs/ape6evm_defconfig b/arch/arm/configs/ape6evm_defconfig index 1ce39940795d..cb26c62dc722 100644 --- a/arch/arm/configs/ape6evm_defconfig +++ b/arch/arm/configs/ape6evm_defconfig | |||
| @@ -13,7 +13,7 @@ CONFIG_EMBEDDED=y | |||
| 13 | CONFIG_PERF_EVENTS=y | 13 | CONFIG_PERF_EVENTS=y |
| 14 | CONFIG_SLAB=y | 14 | CONFIG_SLAB=y |
| 15 | # CONFIG_BLOCK is not set | 15 | # CONFIG_BLOCK is not set |
| 16 | CONFIG_ARCH_SHMOBILE=y | 16 | CONFIG_ARCH_SHMOBILE_LEGACY=y |
| 17 | CONFIG_ARCH_R8A73A4=y | 17 | CONFIG_ARCH_R8A73A4=y |
| 18 | CONFIG_MACH_APE6EVM=y | 18 | CONFIG_MACH_APE6EVM=y |
| 19 | # CONFIG_ARM_THUMB is not set | 19 | # CONFIG_ARM_THUMB is not set |
diff --git a/arch/arm/configs/armadillo800eva_defconfig b/arch/arm/configs/armadillo800eva_defconfig index fae939d3d7f0..5abf1a2e3160 100644 --- a/arch/arm/configs/armadillo800eva_defconfig +++ b/arch/arm/configs/armadillo800eva_defconfig | |||
| @@ -15,7 +15,7 @@ CONFIG_MODULE_FORCE_UNLOAD=y | |||
| 15 | # CONFIG_BLK_DEV_BSG is not set | 15 | # CONFIG_BLK_DEV_BSG is not set |
| 16 | # CONFIG_IOSCHED_DEADLINE is not set | 16 | # CONFIG_IOSCHED_DEADLINE is not set |
| 17 | # CONFIG_IOSCHED_CFQ is not set | 17 | # CONFIG_IOSCHED_CFQ is not set |
| 18 | CONFIG_ARCH_SHMOBILE=y | 18 | CONFIG_ARCH_SHMOBILE_LEGACY=y |
| 19 | CONFIG_ARCH_R8A7740=y | 19 | CONFIG_ARCH_R8A7740=y |
| 20 | CONFIG_MACH_ARMADILLO800EVA=y | 20 | CONFIG_MACH_ARMADILLO800EVA=y |
| 21 | # CONFIG_SH_TIMER_TMU is not set | 21 | # CONFIG_SH_TIMER_TMU is not set |
diff --git a/arch/arm/configs/bockw_defconfig b/arch/arm/configs/bockw_defconfig index b38cd107f82d..1dd39716d7cb 100644 --- a/arch/arm/configs/bockw_defconfig +++ b/arch/arm/configs/bockw_defconfig | |||
| @@ -8,7 +8,7 @@ CONFIG_SYSCTL_SYSCALL=y | |||
| 8 | CONFIG_EMBEDDED=y | 8 | CONFIG_EMBEDDED=y |
| 9 | CONFIG_SLAB=y | 9 | CONFIG_SLAB=y |
| 10 | # CONFIG_IOSCHED_CFQ is not set | 10 | # CONFIG_IOSCHED_CFQ is not set |
| 11 | CONFIG_ARCH_SHMOBILE=y | 11 | CONFIG_ARCH_SHMOBILE_LEGACY=y |
| 12 | CONFIG_ARCH_R8A7778=y | 12 | CONFIG_ARCH_R8A7778=y |
| 13 | CONFIG_MACH_BOCKW=y | 13 | CONFIG_MACH_BOCKW=y |
| 14 | CONFIG_MEMORY_START=0x60000000 | 14 | CONFIG_MEMORY_START=0x60000000 |
diff --git a/arch/arm/configs/koelsch_defconfig b/arch/arm/configs/koelsch_defconfig index 825c16dee8a0..7fd65a01ec7e 100644 --- a/arch/arm/configs/koelsch_defconfig +++ b/arch/arm/configs/koelsch_defconfig | |||
| @@ -9,7 +9,7 @@ CONFIG_EMBEDDED=y | |||
| 9 | CONFIG_PERF_EVENTS=y | 9 | CONFIG_PERF_EVENTS=y |
| 10 | CONFIG_SLAB=y | 10 | CONFIG_SLAB=y |
| 11 | # CONFIG_BLOCK is not set | 11 | # CONFIG_BLOCK is not set |
| 12 | CONFIG_ARCH_SHMOBILE=y | 12 | CONFIG_ARCH_SHMOBILE_LEGACY=y |
| 13 | CONFIG_ARCH_R8A7791=y | 13 | CONFIG_ARCH_R8A7791=y |
| 14 | CONFIG_MACH_KOELSCH=y | 14 | CONFIG_MACH_KOELSCH=y |
| 15 | # CONFIG_SWP_EMULATE is not set | 15 | # CONFIG_SWP_EMULATE is not set |
diff --git a/arch/arm/configs/kzm9d_defconfig b/arch/arm/configs/kzm9d_defconfig index 6c37f4a98eb8..217f1dda2965 100644 --- a/arch/arm/configs/kzm9d_defconfig +++ b/arch/arm/configs/kzm9d_defconfig | |||
| @@ -13,7 +13,7 @@ CONFIG_SLAB=y | |||
| 13 | # CONFIG_BLK_DEV_BSG is not set | 13 | # CONFIG_BLK_DEV_BSG is not set |
| 14 | # CONFIG_IOSCHED_DEADLINE is not set | 14 | # CONFIG_IOSCHED_DEADLINE is not set |
| 15 | # CONFIG_IOSCHED_CFQ is not set | 15 | # CONFIG_IOSCHED_CFQ is not set |
| 16 | CONFIG_ARCH_SHMOBILE=y | 16 | CONFIG_ARCH_SHMOBILE_LEGACY=y |
| 17 | CONFIG_ARCH_EMEV2=y | 17 | CONFIG_ARCH_EMEV2=y |
| 18 | CONFIG_MACH_KZM9D=y | 18 | CONFIG_MACH_KZM9D=y |
| 19 | CONFIG_MEMORY_START=0x40000000 | 19 | CONFIG_MEMORY_START=0x40000000 |
diff --git a/arch/arm/configs/kzm9g_defconfig b/arch/arm/configs/kzm9g_defconfig index 1ad028023a64..9934dbc23d64 100644 --- a/arch/arm/configs/kzm9g_defconfig +++ b/arch/arm/configs/kzm9g_defconfig | |||
| @@ -22,7 +22,7 @@ CONFIG_MODULE_UNLOAD=y | |||
| 22 | # CONFIG_BLK_DEV_BSG is not set | 22 | # CONFIG_BLK_DEV_BSG is not set |
| 23 | # CONFIG_IOSCHED_DEADLINE is not set | 23 | # CONFIG_IOSCHED_DEADLINE is not set |
| 24 | # CONFIG_IOSCHED_CFQ is not set | 24 | # CONFIG_IOSCHED_CFQ is not set |
| 25 | CONFIG_ARCH_SHMOBILE=y | 25 | CONFIG_ARCH_SHMOBILE_LEGACY=y |
| 26 | CONFIG_ARCH_SH73A0=y | 26 | CONFIG_ARCH_SH73A0=y |
| 27 | CONFIG_MACH_KZM9G=y | 27 | CONFIG_MACH_KZM9G=y |
| 28 | CONFIG_MEMORY_START=0x41000000 | 28 | CONFIG_MEMORY_START=0x41000000 |
diff --git a/arch/arm/configs/lager_defconfig b/arch/arm/configs/lager_defconfig index 35bff5e0d57a..35dc8b2be47f 100644 --- a/arch/arm/configs/lager_defconfig +++ b/arch/arm/configs/lager_defconfig | |||
| @@ -12,7 +12,7 @@ CONFIG_SLAB=y | |||
| 12 | # CONFIG_BLK_DEV_BSG is not set | 12 | # CONFIG_BLK_DEV_BSG is not set |
| 13 | # CONFIG_IOSCHED_DEADLINE is not set | 13 | # CONFIG_IOSCHED_DEADLINE is not set |
| 14 | # CONFIG_IOSCHED_CFQ is not set | 14 | # CONFIG_IOSCHED_CFQ is not set |
| 15 | CONFIG_ARCH_SHMOBILE=y | 15 | CONFIG_ARCH_SHMOBILE_LEGACY=y |
| 16 | CONFIG_ARCH_R8A7790=y | 16 | CONFIG_ARCH_R8A7790=y |
| 17 | CONFIG_MACH_LAGER=y | 17 | CONFIG_MACH_LAGER=y |
| 18 | # CONFIG_SH_TIMER_TMU is not set | 18 | # CONFIG_SH_TIMER_TMU is not set |
diff --git a/arch/arm/configs/mackerel_defconfig b/arch/arm/configs/mackerel_defconfig index 9fb11895b2e2..a61e1653fc5e 100644 --- a/arch/arm/configs/mackerel_defconfig +++ b/arch/arm/configs/mackerel_defconfig | |||
| @@ -14,7 +14,7 @@ CONFIG_MODULE_UNLOAD=y | |||
| 14 | # CONFIG_BLK_DEV_BSG is not set | 14 | # CONFIG_BLK_DEV_BSG is not set |
| 15 | # CONFIG_IOSCHED_DEADLINE is not set | 15 | # CONFIG_IOSCHED_DEADLINE is not set |
| 16 | # CONFIG_IOSCHED_CFQ is not set | 16 | # CONFIG_IOSCHED_CFQ is not set |
| 17 | CONFIG_ARCH_SHMOBILE=y | 17 | CONFIG_ARCH_SHMOBILE_LEGACY=y |
| 18 | CONFIG_ARCH_SH7372=y | 18 | CONFIG_ARCH_SH7372=y |
| 19 | CONFIG_MACH_MACKEREL=y | 19 | CONFIG_MACH_MACKEREL=y |
| 20 | CONFIG_MEMORY_SIZE=0x10000000 | 20 | CONFIG_MEMORY_SIZE=0x10000000 |
diff --git a/arch/arm/configs/marzen_defconfig b/arch/arm/configs/marzen_defconfig index 5cc6360340b1..6981338cd08d 100644 --- a/arch/arm/configs/marzen_defconfig +++ b/arch/arm/configs/marzen_defconfig | |||
| @@ -9,7 +9,7 @@ CONFIG_SYSCTL_SYSCALL=y | |||
| 9 | CONFIG_EMBEDDED=y | 9 | CONFIG_EMBEDDED=y |
| 10 | CONFIG_SLAB=y | 10 | CONFIG_SLAB=y |
| 11 | # CONFIG_IOSCHED_CFQ is not set | 11 | # CONFIG_IOSCHED_CFQ is not set |
| 12 | CONFIG_ARCH_SHMOBILE=y | 12 | CONFIG_ARCH_SHMOBILE_LEGACY=y |
| 13 | CONFIG_ARCH_R8A7779=y | 13 | CONFIG_ARCH_R8A7779=y |
| 14 | CONFIG_MACH_MARZEN=y | 14 | CONFIG_MACH_MARZEN=y |
| 15 | CONFIG_MEMORY_START=0x60000000 | 15 | CONFIG_MEMORY_START=0x60000000 |
diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig index 4934295bb4f0..da753e31c850 100644 --- a/arch/arm/configs/tegra_defconfig +++ b/arch/arm/configs/tegra_defconfig | |||
| @@ -33,6 +33,7 @@ CONFIG_PCI=y | |||
| 33 | CONFIG_PCI_MSI=y | 33 | CONFIG_PCI_MSI=y |
| 34 | CONFIG_PCI_TEGRA=y | 34 | CONFIG_PCI_TEGRA=y |
| 35 | CONFIG_PCIEPORTBUS=y | 35 | CONFIG_PCIEPORTBUS=y |
| 36 | CONFIG_TRUSTED_FOUNDATIONS=y | ||
| 36 | CONFIG_SMP=y | 37 | CONFIG_SMP=y |
| 37 | CONFIG_PREEMPT=y | 38 | CONFIG_PREEMPT=y |
| 38 | CONFIG_AEABI=y | 39 | CONFIG_AEABI=y |
diff --git a/arch/arm/firmware/Kconfig b/arch/arm/firmware/Kconfig new file mode 100644 index 000000000000..bb00ccf00d66 --- /dev/null +++ b/arch/arm/firmware/Kconfig | |||
| @@ -0,0 +1,28 @@ | |||
| 1 | config ARCH_SUPPORTS_FIRMWARE | ||
| 2 | bool | ||
| 3 | |||
| 4 | config ARCH_SUPPORTS_TRUSTED_FOUNDATIONS | ||
| 5 | bool | ||
| 6 | select ARCH_SUPPORTS_FIRMWARE | ||
| 7 | |||
| 8 | menu "Firmware options" | ||
| 9 | depends on ARCH_SUPPORTS_FIRMWARE | ||
| 10 | |||
| 11 | config TRUSTED_FOUNDATIONS | ||
| 12 | bool "Trusted Foundations secure monitor support" | ||
| 13 | depends on ARCH_SUPPORTS_TRUSTED_FOUNDATIONS | ||
| 14 | help | ||
| 15 | Some devices (including most Tegra-based consumer devices on the | ||
| 16 | market) are booted with the Trusted Foundations secure monitor | ||
| 17 | active, requiring some core operations to be performed by the secure | ||
| 18 | monitor instead of the kernel. | ||
| 19 | |||
| 20 | This option allows the kernel to invoke the secure monitor whenever | ||
| 21 | required on devices using Trusted Foundations. See | ||
| 22 | arch/arm/include/asm/trusted_foundations.h or the | ||
| 23 | tl,trusted-foundations device tree binding documentation for details | ||
| 24 | on how to use it. | ||
| 25 | |||
| 26 | Say n if you don't know what this is about. | ||
| 27 | |||
| 28 | endmenu | ||
diff --git a/arch/arm/firmware/Makefile b/arch/arm/firmware/Makefile new file mode 100644 index 000000000000..a71f16536b6c --- /dev/null +++ b/arch/arm/firmware/Makefile | |||
| @@ -0,0 +1 @@ | |||
| obj-$(CONFIG_TRUSTED_FOUNDATIONS) += trusted_foundations.o | |||
diff --git a/arch/arm/firmware/trusted_foundations.c b/arch/arm/firmware/trusted_foundations.c new file mode 100644 index 000000000000..ef1e3d8f4af0 --- /dev/null +++ b/arch/arm/firmware/trusted_foundations.c | |||
| @@ -0,0 +1,81 @@ | |||
| 1 | /* | ||
| 2 | * Trusted Foundations support for ARM CPUs | ||
| 3 | * | ||
| 4 | * Copyright (c) 2013, NVIDIA Corporation. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 14 | * more details. | ||
| 15 | */ | ||
| 16 | |||
| 17 | #include <linux/kernel.h> | ||
| 18 | #include <linux/init.h> | ||
| 19 | #include <linux/of.h> | ||
| 20 | #include <asm/firmware.h> | ||
| 21 | #include <asm/trusted_foundations.h> | ||
| 22 | |||
| 23 | #define TF_SET_CPU_BOOT_ADDR_SMC 0xfffff200 | ||
| 24 | |||
| 25 | static void __naked tf_generic_smc(u32 type, u32 arg1, u32 arg2) | ||
| 26 | { | ||
| 27 | asm volatile( | ||
| 28 | ".arch_extension sec\n\t" | ||
| 29 | "stmfd sp!, {r4 - r11, lr}\n\t" | ||
| 30 | __asmeq("%0", "r0") | ||
| 31 | __asmeq("%1", "r1") | ||
| 32 | __asmeq("%2", "r2") | ||
| 33 | "mov r3, #0\n\t" | ||
| 34 | "mov r4, #0\n\t" | ||
| 35 | "smc #0\n\t" | ||
| 36 | "ldmfd sp!, {r4 - r11, pc}" | ||
| 37 | : | ||
| 38 | : "r" (type), "r" (arg1), "r" (arg2) | ||
| 39 | : "memory"); | ||
| 40 | } | ||
| 41 | |||
| 42 | static int tf_set_cpu_boot_addr(int cpu, unsigned long boot_addr) | ||
| 43 | { | ||
| 44 | tf_generic_smc(TF_SET_CPU_BOOT_ADDR_SMC, boot_addr, 0); | ||
| 45 | |||
| 46 | return 0; | ||
| 47 | } | ||
| 48 | |||
| 49 | static const struct firmware_ops trusted_foundations_ops = { | ||
| 50 | .set_cpu_boot_addr = tf_set_cpu_boot_addr, | ||
| 51 | }; | ||
| 52 | |||
| 53 | void register_trusted_foundations(struct trusted_foundations_platform_data *pd) | ||
| 54 | { | ||
| 55 | /* | ||
| 56 | * we are not using version information for now since currently | ||
| 57 | * supported SMCs are compatible with all TF releases | ||
| 58 | */ | ||
| 59 | register_firmware_ops(&trusted_foundations_ops); | ||
| 60 | } | ||
| 61 | |||
| 62 | void of_register_trusted_foundations(void) | ||
| 63 | { | ||
| 64 | struct device_node *node; | ||
| 65 | struct trusted_foundations_platform_data pdata; | ||
| 66 | int err; | ||
| 67 | |||
| 68 | node = of_find_compatible_node(NULL, NULL, "tlm,trusted-foundations"); | ||
| 69 | if (!node) | ||
| 70 | return; | ||
| 71 | |||
| 72 | err = of_property_read_u32(node, "tlm,version-major", | ||
| 73 | &pdata.version_major); | ||
| 74 | if (err != 0) | ||
| 75 | panic("Trusted Foundation: missing version-major property\n"); | ||
| 76 | err = of_property_read_u32(node, "tlm,version-minor", | ||
| 77 | &pdata.version_minor); | ||
| 78 | if (err != 0) | ||
| 79 | panic("Trusted Foundation: missing version-minor property\n"); | ||
| 80 | register_trusted_foundations(&pdata); | ||
| 81 | } | ||
diff --git a/arch/arm/include/asm/trusted_foundations.h b/arch/arm/include/asm/trusted_foundations.h new file mode 100644 index 000000000000..3bd36e2c5f2e --- /dev/null +++ b/arch/arm/include/asm/trusted_foundations.h | |||
| @@ -0,0 +1,67 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (c) 2013, NVIDIA Corporation. | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; either version 2 of the License, or | ||
| 7 | * (at your option) any later version. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | */ | ||
| 14 | |||
| 15 | /* | ||
| 16 | * Support for the Trusted Foundations secure monitor. | ||
| 17 | * | ||
| 18 | * Trusted Foundation comes active on some ARM consumer devices (most | ||
| 19 | * Tegra-based devices sold on the market are concerned). Such devices can only | ||
| 20 | * perform some basic operations, like setting the CPU reset vector, through | ||
| 21 | * SMC calls to the secure monitor. The calls are completely specific to | ||
| 22 | * Trusted Foundations, and do *not* follow the SMC calling convention or the | ||
| 23 | * PSCI standard. | ||
| 24 | */ | ||
| 25 | |||
| 26 | #ifndef __ASM_ARM_TRUSTED_FOUNDATIONS_H | ||
| 27 | #define __ASM_ARM_TRUSTED_FOUNDATIONS_H | ||
| 28 | |||
| 29 | #include <linux/kconfig.h> | ||
| 30 | #include <linux/printk.h> | ||
| 31 | #include <linux/bug.h> | ||
| 32 | #include <linux/of.h> | ||
| 33 | |||
| 34 | struct trusted_foundations_platform_data { | ||
| 35 | unsigned int version_major; | ||
| 36 | unsigned int version_minor; | ||
| 37 | }; | ||
| 38 | |||
| 39 | #if IS_ENABLED(CONFIG_TRUSTED_FOUNDATIONS) | ||
| 40 | |||
| 41 | void register_trusted_foundations(struct trusted_foundations_platform_data *pd); | ||
| 42 | void of_register_trusted_foundations(void); | ||
| 43 | |||
| 44 | #else /* CONFIG_TRUSTED_FOUNDATIONS */ | ||
| 45 | |||
| 46 | static inline void register_trusted_foundations( | ||
| 47 | struct trusted_foundations_platform_data *pd) | ||
| 48 | { | ||
| 49 | /* | ||
| 50 | * If we try to register TF, this means the system needs it to continue. | ||
| 51 | * Its absence if thus a fatal error. | ||
| 52 | */ | ||
| 53 | panic("No support for Trusted Foundations, stopping...\n"); | ||
| 54 | } | ||
| 55 | |||
| 56 | static inline void of_register_trusted_foundations(void) | ||
| 57 | { | ||
| 58 | /* | ||
| 59 | * If we find the target should enable TF but does not support it, | ||
| 60 | * fail as the system won't be able to do much anyway | ||
| 61 | */ | ||
| 62 | if (of_find_compatible_node(NULL, NULL, "tl,trusted-foundations")) | ||
| 63 | register_trusted_foundations(NULL); | ||
| 64 | } | ||
| 65 | #endif /* CONFIG_TRUSTED_FOUNDATIONS */ | ||
| 66 | |||
| 67 | #endif | ||
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 699b71e7f7ec..b4f7d6ffa30b 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig | |||
| @@ -1,15 +1,33 @@ | |||
| 1 | if ARCH_AT91 | 1 | if ARCH_AT91 |
| 2 | 2 | ||
| 3 | config HAVE_AT91_UTMI | ||
| 4 | bool | ||
| 5 | |||
| 6 | config HAVE_AT91_USB_CLK | ||
| 7 | bool | ||
| 8 | |||
| 3 | config HAVE_AT91_DBGU0 | 9 | config HAVE_AT91_DBGU0 |
| 4 | bool | 10 | bool |
| 5 | 11 | ||
| 6 | config HAVE_AT91_DBGU1 | 12 | config HAVE_AT91_DBGU1 |
| 7 | bool | 13 | bool |
| 8 | 14 | ||
| 15 | config AT91_USE_OLD_CLK | ||
| 16 | bool | ||
| 17 | |||
| 9 | config AT91_PMC_UNIT | 18 | config AT91_PMC_UNIT |
| 10 | bool | 19 | bool |
| 11 | default !ARCH_AT91X40 | 20 | default !ARCH_AT91X40 |
| 12 | 21 | ||
| 22 | config COMMON_CLK_AT91 | ||
| 23 | bool | ||
| 24 | default AT91_PMC_UNIT && USE_OF && !AT91_USE_OLD_CLK | ||
| 25 | select COMMON_CLK | ||
| 26 | |||
| 27 | config OLD_CLK_AT91 | ||
| 28 | bool | ||
| 29 | default AT91_PMC_UNIT && AT91_USE_OLD_CLK | ||
| 30 | |||
| 13 | config AT91_SAM9_ALT_RESET | 31 | config AT91_SAM9_ALT_RESET |
| 14 | bool | 32 | bool |
| 15 | default !ARCH_AT91X40 | 33 | default !ARCH_AT91X40 |
| @@ -21,6 +39,9 @@ config AT91_SAM9G45_RESET | |||
| 21 | config AT91_SAM9_TIME | 39 | config AT91_SAM9_TIME |
| 22 | bool | 40 | bool |
| 23 | 41 | ||
| 42 | config HAVE_AT91_SMD | ||
| 43 | bool | ||
| 44 | |||
| 24 | config SOC_AT91SAM9 | 45 | config SOC_AT91SAM9 |
| 25 | bool | 46 | bool |
| 26 | select AT91_SAM9_TIME | 47 | select AT91_SAM9_TIME |
| @@ -65,6 +86,9 @@ config SOC_SAMA5D3 | |||
| 65 | select SOC_SAMA5 | 86 | select SOC_SAMA5 |
| 66 | select HAVE_FB_ATMEL | 87 | select HAVE_FB_ATMEL |
| 67 | select HAVE_AT91_DBGU1 | 88 | select HAVE_AT91_DBGU1 |
| 89 | select HAVE_AT91_UTMI | ||
| 90 | select HAVE_AT91_SMD | ||
| 91 | select HAVE_AT91_USB_CLK | ||
| 68 | help | 92 | help |
| 69 | Select this if you are using one of Atmel's SAMA5D3 family SoC. | 93 | Select this if you are using one of Atmel's SAMA5D3 family SoC. |
| 70 | This support covers SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35. | 94 | This support covers SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35. |
| @@ -78,11 +102,15 @@ config SOC_AT91RM9200 | |||
| 78 | select HAVE_AT91_DBGU0 | 102 | select HAVE_AT91_DBGU0 |
| 79 | select MULTI_IRQ_HANDLER | 103 | select MULTI_IRQ_HANDLER |
| 80 | select SPARSE_IRQ | 104 | select SPARSE_IRQ |
| 105 | select AT91_USE_OLD_CLK | ||
| 106 | select HAVE_AT91_USB_CLK | ||
| 81 | 107 | ||
| 82 | config SOC_AT91SAM9260 | 108 | config SOC_AT91SAM9260 |
| 83 | bool "AT91SAM9260, AT91SAM9XE or AT91SAM9G20" | 109 | bool "AT91SAM9260, AT91SAM9XE or AT91SAM9G20" |
| 84 | select HAVE_AT91_DBGU0 | 110 | select HAVE_AT91_DBGU0 |
| 85 | select SOC_AT91SAM9 | 111 | select SOC_AT91SAM9 |
| 112 | select AT91_USE_OLD_CLK | ||
| 113 | select HAVE_AT91_USB_CLK | ||
| 86 | help | 114 | help |
| 87 | Select this if you are using one of Atmel's AT91SAM9260, AT91SAM9XE | 115 | Select this if you are using one of Atmel's AT91SAM9260, AT91SAM9XE |
| 88 | or AT91SAM9G20 SoC. | 116 | or AT91SAM9G20 SoC. |
| @@ -92,6 +120,8 @@ config SOC_AT91SAM9261 | |||
| 92 | select HAVE_AT91_DBGU0 | 120 | select HAVE_AT91_DBGU0 |
| 93 | select HAVE_FB_ATMEL | 121 | select HAVE_FB_ATMEL |
| 94 | select SOC_AT91SAM9 | 122 | select SOC_AT91SAM9 |
| 123 | select AT91_USE_OLD_CLK | ||
| 124 | select HAVE_AT91_USB_CLK | ||
| 95 | help | 125 | help |
| 96 | Select this if you are using one of Atmel's AT91SAM9261 or AT91SAM9G10 SoC. | 126 | Select this if you are using one of Atmel's AT91SAM9261 or AT91SAM9G10 SoC. |
| 97 | 127 | ||
| @@ -100,18 +130,25 @@ config SOC_AT91SAM9263 | |||
| 100 | select HAVE_AT91_DBGU1 | 130 | select HAVE_AT91_DBGU1 |
| 101 | select HAVE_FB_ATMEL | 131 | select HAVE_FB_ATMEL |
| 102 | select SOC_AT91SAM9 | 132 | select SOC_AT91SAM9 |
| 133 | select AT91_USE_OLD_CLK | ||
| 134 | select HAVE_AT91_USB_CLK | ||
| 103 | 135 | ||
| 104 | config SOC_AT91SAM9RL | 136 | config SOC_AT91SAM9RL |
| 105 | bool "AT91SAM9RL" | 137 | bool "AT91SAM9RL" |
| 106 | select HAVE_AT91_DBGU0 | 138 | select HAVE_AT91_DBGU0 |
| 107 | select HAVE_FB_ATMEL | 139 | select HAVE_FB_ATMEL |
| 108 | select SOC_AT91SAM9 | 140 | select SOC_AT91SAM9 |
| 141 | select AT91_USE_OLD_CLK | ||
| 142 | select HAVE_AT91_UTMI | ||
| 109 | 143 | ||
| 110 | config SOC_AT91SAM9G45 | 144 | config SOC_AT91SAM9G45 |
| 111 | bool "AT91SAM9G45 or AT91SAM9M10 families" | 145 | bool "AT91SAM9G45 or AT91SAM9M10 families" |
| 112 | select HAVE_AT91_DBGU1 | 146 | select HAVE_AT91_DBGU1 |
| 113 | select HAVE_FB_ATMEL | 147 | select HAVE_FB_ATMEL |
| 114 | select SOC_AT91SAM9 | 148 | select SOC_AT91SAM9 |
| 149 | select AT91_USE_OLD_CLK | ||
| 150 | select HAVE_AT91_UTMI | ||
| 151 | select HAVE_AT91_USB_CLK | ||
| 115 | help | 152 | help |
| 116 | Select this if you are using one of Atmel's AT91SAM9G45 family SoC. | 153 | Select this if you are using one of Atmel's AT91SAM9G45 family SoC. |
| 117 | This support covers AT91SAM9G45, AT91SAM9G46, AT91SAM9M10 and AT91SAM9M11. | 154 | This support covers AT91SAM9G45, AT91SAM9G46, AT91SAM9M10 and AT91SAM9M11. |
| @@ -121,6 +158,10 @@ config SOC_AT91SAM9X5 | |||
| 121 | select HAVE_AT91_DBGU0 | 158 | select HAVE_AT91_DBGU0 |
| 122 | select HAVE_FB_ATMEL | 159 | select HAVE_FB_ATMEL |
| 123 | select SOC_AT91SAM9 | 160 | select SOC_AT91SAM9 |
| 161 | select AT91_USE_OLD_CLK | ||
| 162 | select HAVE_AT91_UTMI | ||
| 163 | select HAVE_AT91_SMD | ||
| 164 | select HAVE_AT91_USB_CLK | ||
| 124 | help | 165 | help |
| 125 | Select this if you are using one of Atmel's AT91SAM9x5 family SoC. | 166 | Select this if you are using one of Atmel's AT91SAM9x5 family SoC. |
| 126 | This means that your SAM9 name finishes with a '5' (except if it is | 167 | This means that your SAM9 name finishes with a '5' (except if it is |
| @@ -133,6 +174,8 @@ config SOC_AT91SAM9N12 | |||
| 133 | select HAVE_AT91_DBGU0 | 174 | select HAVE_AT91_DBGU0 |
| 134 | select HAVE_FB_ATMEL | 175 | select HAVE_FB_ATMEL |
| 135 | select SOC_AT91SAM9 | 176 | select SOC_AT91SAM9 |
| 177 | select AT91_USE_OLD_CLK | ||
| 178 | select HAVE_AT91_USB_CLK | ||
| 136 | help | 179 | help |
| 137 | Select this if you are using Atmel's AT91SAM9N12 SoC. | 180 | Select this if you are using Atmel's AT91SAM9N12 SoC. |
| 138 | 181 | ||
diff --git a/arch/arm/mach-at91/Kconfig.non_dt b/arch/arm/mach-at91/Kconfig.non_dt index ca900be144ce..b736b571e882 100644 --- a/arch/arm/mach-at91/Kconfig.non_dt +++ b/arch/arm/mach-at91/Kconfig.non_dt | |||
| @@ -12,26 +12,32 @@ config ARCH_AT91_NONE | |||
| 12 | config ARCH_AT91RM9200 | 12 | config ARCH_AT91RM9200 |
| 13 | bool "AT91RM9200" | 13 | bool "AT91RM9200" |
| 14 | select SOC_AT91RM9200 | 14 | select SOC_AT91RM9200 |
| 15 | select AT91_USE_OLD_CLK | ||
| 15 | 16 | ||
| 16 | config ARCH_AT91SAM9260 | 17 | config ARCH_AT91SAM9260 |
| 17 | bool "AT91SAM9260 or AT91SAM9XE or AT91SAM9G20" | 18 | bool "AT91SAM9260 or AT91SAM9XE or AT91SAM9G20" |
| 18 | select SOC_AT91SAM9260 | 19 | select SOC_AT91SAM9260 |
| 20 | select AT91_USE_OLD_CLK | ||
| 19 | 21 | ||
| 20 | config ARCH_AT91SAM9261 | 22 | config ARCH_AT91SAM9261 |
| 21 | bool "AT91SAM9261 or AT91SAM9G10" | 23 | bool "AT91SAM9261 or AT91SAM9G10" |
| 22 | select SOC_AT91SAM9261 | 24 | select SOC_AT91SAM9261 |
| 25 | select AT91_USE_OLD_CLK | ||
| 23 | 26 | ||
| 24 | config ARCH_AT91SAM9263 | 27 | config ARCH_AT91SAM9263 |
| 25 | bool "AT91SAM9263" | 28 | bool "AT91SAM9263" |
| 26 | select SOC_AT91SAM9263 | 29 | select SOC_AT91SAM9263 |
| 30 | select AT91_USE_OLD_CLK | ||
| 27 | 31 | ||
| 28 | config ARCH_AT91SAM9RL | 32 | config ARCH_AT91SAM9RL |
| 29 | bool "AT91SAM9RL" | 33 | bool "AT91SAM9RL" |
| 30 | select SOC_AT91SAM9RL | 34 | select SOC_AT91SAM9RL |
| 35 | select AT91_USE_OLD_CLK | ||
| 31 | 36 | ||
| 32 | config ARCH_AT91SAM9G45 | 37 | config ARCH_AT91SAM9G45 |
| 33 | bool "AT91SAM9G45" | 38 | bool "AT91SAM9G45" |
| 34 | select SOC_AT91SAM9G45 | 39 | select SOC_AT91SAM9G45 |
| 40 | select AT91_USE_OLD_CLK | ||
| 35 | 41 | ||
| 36 | config ARCH_AT91X40 | 42 | config ARCH_AT91X40 |
| 37 | bool "AT91x40" | 43 | bool "AT91x40" |
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index 90aab2d5a07f..705b38a179ec 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile | |||
| @@ -7,7 +7,7 @@ obj-m := | |||
| 7 | obj-n := | 7 | obj-n := |
| 8 | obj- := | 8 | obj- := |
| 9 | 9 | ||
| 10 | obj-$(CONFIG_AT91_PMC_UNIT) += clock.o | 10 | obj-$(CONFIG_OLD_CLK_AT91) += clock.o |
| 11 | obj-$(CONFIG_AT91_SAM9_ALT_RESET) += at91sam9_alt_reset.o | 11 | obj-$(CONFIG_AT91_SAM9_ALT_RESET) += at91sam9_alt_reset.o |
| 12 | obj-$(CONFIG_AT91_SAM9G45_RESET) += at91sam9g45_reset.o | 12 | obj-$(CONFIG_AT91_SAM9G45_RESET) += at91sam9g45_reset.o |
| 13 | obj-$(CONFIG_AT91_SAM9_TIME) += at91sam926x_time.o | 13 | obj-$(CONFIG_AT91_SAM9_TIME) += at91sam926x_time.o |
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c index 25805f2f6010..e47f5fd232f5 100644 --- a/arch/arm/mach-at91/at91rm9200.c +++ b/arch/arm/mach-at91/at91rm9200.c | |||
| @@ -12,13 +12,13 @@ | |||
| 12 | 12 | ||
| 13 | #include <linux/module.h> | 13 | #include <linux/module.h> |
| 14 | #include <linux/reboot.h> | 14 | #include <linux/reboot.h> |
| 15 | #include <linux/clk/at91_pmc.h> | ||
| 15 | 16 | ||
| 16 | #include <asm/irq.h> | 17 | #include <asm/irq.h> |
| 17 | #include <asm/mach/arch.h> | 18 | #include <asm/mach/arch.h> |
| 18 | #include <asm/mach/map.h> | 19 | #include <asm/mach/map.h> |
| 19 | #include <asm/system_misc.h> | 20 | #include <asm/system_misc.h> |
| 20 | #include <mach/at91rm9200.h> | 21 | #include <mach/at91rm9200.h> |
| 21 | #include <mach/at91_pmc.h> | ||
| 22 | #include <mach/at91_st.h> | 22 | #include <mach/at91_st.h> |
| 23 | #include <mach/cpu.h> | 23 | #include <mach/cpu.h> |
| 24 | 24 | ||
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c index d6a1fa85371d..6c821e562159 100644 --- a/arch/arm/mach-at91/at91sam9260.c +++ b/arch/arm/mach-at91/at91sam9260.c | |||
| @@ -11,6 +11,7 @@ | |||
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| 13 | #include <linux/module.h> | 13 | #include <linux/module.h> |
| 14 | #include <linux/clk/at91_pmc.h> | ||
| 14 | 15 | ||
| 15 | #include <asm/proc-fns.h> | 16 | #include <asm/proc-fns.h> |
| 16 | #include <asm/irq.h> | 17 | #include <asm/irq.h> |
| @@ -20,7 +21,6 @@ | |||
| 20 | #include <mach/cpu.h> | 21 | #include <mach/cpu.h> |
| 21 | #include <mach/at91_dbgu.h> | 22 | #include <mach/at91_dbgu.h> |
| 22 | #include <mach/at91sam9260.h> | 23 | #include <mach/at91sam9260.h> |
| 23 | #include <mach/at91_pmc.h> | ||
| 24 | 24 | ||
| 25 | #include "at91_aic.h" | 25 | #include "at91_aic.h" |
| 26 | #include "at91_rstc.h" | 26 | #include "at91_rstc.h" |
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c index 23ba1d8a1531..6276b4c1acfe 100644 --- a/arch/arm/mach-at91/at91sam9261.c +++ b/arch/arm/mach-at91/at91sam9261.c | |||
| @@ -11,6 +11,7 @@ | |||
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| 13 | #include <linux/module.h> | 13 | #include <linux/module.h> |
| 14 | #include <linux/clk/at91_pmc.h> | ||
| 14 | 15 | ||
| 15 | #include <asm/proc-fns.h> | 16 | #include <asm/proc-fns.h> |
| 16 | #include <asm/irq.h> | 17 | #include <asm/irq.h> |
| @@ -19,7 +20,6 @@ | |||
| 19 | #include <asm/system_misc.h> | 20 | #include <asm/system_misc.h> |
| 20 | #include <mach/cpu.h> | 21 | #include <mach/cpu.h> |
| 21 | #include <mach/at91sam9261.h> | 22 | #include <mach/at91sam9261.h> |
| 22 | #include <mach/at91_pmc.h> | ||
| 23 | 23 | ||
| 24 | #include "at91_aic.h" | 24 | #include "at91_aic.h" |
| 25 | #include "at91_rstc.h" | 25 | #include "at91_rstc.h" |
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c index 7eccb0fc57bc..37b90f4b990c 100644 --- a/arch/arm/mach-at91/at91sam9263.c +++ b/arch/arm/mach-at91/at91sam9263.c | |||
| @@ -11,6 +11,7 @@ | |||
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| 13 | #include <linux/module.h> | 13 | #include <linux/module.h> |
| 14 | #include <linux/clk/at91_pmc.h> | ||
| 14 | 15 | ||
| 15 | #include <asm/proc-fns.h> | 16 | #include <asm/proc-fns.h> |
| 16 | #include <asm/irq.h> | 17 | #include <asm/irq.h> |
| @@ -18,7 +19,6 @@ | |||
| 18 | #include <asm/mach/map.h> | 19 | #include <asm/mach/map.h> |
| 19 | #include <asm/system_misc.h> | 20 | #include <asm/system_misc.h> |
| 20 | #include <mach/at91sam9263.h> | 21 | #include <mach/at91sam9263.h> |
| 21 | #include <mach/at91_pmc.h> | ||
| 22 | 22 | ||
| 23 | #include "at91_aic.h" | 23 | #include "at91_aic.h" |
| 24 | #include "at91_rstc.h" | 24 | #include "at91_rstc.h" |
diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c index bb392320a0dd..0f04ffe9c5a8 100644 --- a/arch/arm/mach-at91/at91sam926x_time.c +++ b/arch/arm/mach-at91/at91sam926x_time.c | |||
| @@ -39,6 +39,7 @@ | |||
| 39 | static u32 pit_cycle; /* write-once */ | 39 | static u32 pit_cycle; /* write-once */ |
| 40 | static u32 pit_cnt; /* access only w/system irq blocked */ | 40 | static u32 pit_cnt; /* access only w/system irq blocked */ |
| 41 | static void __iomem *pit_base_addr __read_mostly; | 41 | static void __iomem *pit_base_addr __read_mostly; |
| 42 | static struct clk *mck; | ||
| 42 | 43 | ||
| 43 | static inline unsigned int pit_read(unsigned int reg_offset) | 44 | static inline unsigned int pit_read(unsigned int reg_offset) |
| 44 | { | 45 | { |
| @@ -195,10 +196,14 @@ static int __init of_at91sam926x_pit_init(void) | |||
| 195 | if (!pit_base_addr) | 196 | if (!pit_base_addr) |
| 196 | goto node_err; | 197 | goto node_err; |
| 197 | 198 | ||
| 199 | mck = of_clk_get(np, 0); | ||
| 200 | |||
| 198 | /* Get the interrupts property */ | 201 | /* Get the interrupts property */ |
| 199 | ret = irq_of_parse_and_map(np, 0); | 202 | ret = irq_of_parse_and_map(np, 0); |
| 200 | if (!ret) { | 203 | if (!ret) { |
| 201 | pr_crit("AT91: PIT: Unable to get IRQ from DT\n"); | 204 | pr_crit("AT91: PIT: Unable to get IRQ from DT\n"); |
| 205 | if (!IS_ERR(mck)) | ||
| 206 | clk_put(mck); | ||
| 202 | goto ioremap_err; | 207 | goto ioremap_err; |
| 203 | } | 208 | } |
| 204 | at91sam926x_pit_irq.irq = ret; | 209 | at91sam926x_pit_irq.irq = ret; |
| @@ -230,6 +235,8 @@ void __init at91sam926x_pit_init(void) | |||
| 230 | unsigned bits; | 235 | unsigned bits; |
| 231 | int ret; | 236 | int ret; |
| 232 | 237 | ||
| 238 | mck = ERR_PTR(-ENOENT); | ||
| 239 | |||
| 233 | /* For device tree enabled device: initialize here */ | 240 | /* For device tree enabled device: initialize here */ |
| 234 | of_at91sam926x_pit_init(); | 241 | of_at91sam926x_pit_init(); |
| 235 | 242 | ||
| @@ -237,7 +244,12 @@ void __init at91sam926x_pit_init(void) | |||
| 237 | * Use our actual MCK to figure out how many MCK/16 ticks per | 244 | * Use our actual MCK to figure out how many MCK/16 ticks per |
| 238 | * 1/HZ period (instead of a compile-time constant LATCH). | 245 | * 1/HZ period (instead of a compile-time constant LATCH). |
| 239 | */ | 246 | */ |
| 240 | pit_rate = clk_get_rate(clk_get(NULL, "mck")) / 16; | 247 | if (IS_ERR(mck)) |
| 248 | mck = clk_get(NULL, "mck"); | ||
| 249 | |||
| 250 | if (IS_ERR(mck)) | ||
| 251 | panic("AT91: PIT: Unable to get mck clk\n"); | ||
| 252 | pit_rate = clk_get_rate(mck) / 16; | ||
| 241 | pit_cycle = (pit_rate + HZ/2) / HZ; | 253 | pit_cycle = (pit_rate + HZ/2) / HZ; |
| 242 | WARN_ON(((pit_cycle - 1) & ~AT91_PIT_PIV) != 0); | 254 | WARN_ON(((pit_cycle - 1) & ~AT91_PIT_PIV) != 0); |
| 243 | 255 | ||
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c index 9405aa08b104..2f455ce35268 100644 --- a/arch/arm/mach-at91/at91sam9g45.c +++ b/arch/arm/mach-at91/at91sam9g45.c | |||
| @@ -12,13 +12,13 @@ | |||
| 12 | 12 | ||
| 13 | #include <linux/module.h> | 13 | #include <linux/module.h> |
| 14 | #include <linux/dma-mapping.h> | 14 | #include <linux/dma-mapping.h> |
| 15 | #include <linux/clk/at91_pmc.h> | ||
| 15 | 16 | ||
| 16 | #include <asm/irq.h> | 17 | #include <asm/irq.h> |
| 17 | #include <asm/mach/arch.h> | 18 | #include <asm/mach/arch.h> |
| 18 | #include <asm/mach/map.h> | 19 | #include <asm/mach/map.h> |
| 19 | #include <asm/system_misc.h> | 20 | #include <asm/system_misc.h> |
| 20 | #include <mach/at91sam9g45.h> | 21 | #include <mach/at91sam9g45.h> |
| 21 | #include <mach/at91_pmc.h> | ||
| 22 | #include <mach/cpu.h> | 22 | #include <mach/cpu.h> |
| 23 | 23 | ||
| 24 | #include "at91_aic.h" | 24 | #include "at91_aic.h" |
diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c index 388ec3aec4b9..4ef088c62eab 100644 --- a/arch/arm/mach-at91/at91sam9n12.c +++ b/arch/arm/mach-at91/at91sam9n12.c | |||
| @@ -8,12 +8,12 @@ | |||
| 8 | 8 | ||
| 9 | #include <linux/module.h> | 9 | #include <linux/module.h> |
| 10 | #include <linux/dma-mapping.h> | 10 | #include <linux/dma-mapping.h> |
| 11 | #include <linux/clk/at91_pmc.h> | ||
| 11 | 12 | ||
| 12 | #include <asm/irq.h> | 13 | #include <asm/irq.h> |
| 13 | #include <asm/mach/arch.h> | 14 | #include <asm/mach/arch.h> |
| 14 | #include <asm/mach/map.h> | 15 | #include <asm/mach/map.h> |
| 15 | #include <mach/at91sam9n12.h> | 16 | #include <mach/at91sam9n12.h> |
| 16 | #include <mach/at91_pmc.h> | ||
| 17 | #include <mach/cpu.h> | 17 | #include <mach/cpu.h> |
| 18 | 18 | ||
| 19 | #include "board.h" | 19 | #include "board.h" |
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c index 0750ffb7e6b1..3651517abedf 100644 --- a/arch/arm/mach-at91/at91sam9rl.c +++ b/arch/arm/mach-at91/at91sam9rl.c | |||
| @@ -10,6 +10,7 @@ | |||
| 10 | */ | 10 | */ |
| 11 | 11 | ||
| 12 | #include <linux/module.h> | 12 | #include <linux/module.h> |
| 13 | #include <linux/clk/at91_pmc.h> | ||
| 13 | 14 | ||
| 14 | #include <asm/proc-fns.h> | 15 | #include <asm/proc-fns.h> |
| 15 | #include <asm/irq.h> | 16 | #include <asm/irq.h> |
| @@ -19,7 +20,6 @@ | |||
| 19 | #include <mach/cpu.h> | 20 | #include <mach/cpu.h> |
| 20 | #include <mach/at91_dbgu.h> | 21 | #include <mach/at91_dbgu.h> |
| 21 | #include <mach/at91sam9rl.h> | 22 | #include <mach/at91sam9rl.h> |
| 22 | #include <mach/at91_pmc.h> | ||
| 23 | 23 | ||
| 24 | #include "at91_aic.h" | 24 | #include "at91_aic.h" |
| 25 | #include "at91_rstc.h" | 25 | #include "at91_rstc.h" |
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c index e8a2e075a1b8..3e8ec26e39dc 100644 --- a/arch/arm/mach-at91/at91sam9x5.c +++ b/arch/arm/mach-at91/at91sam9x5.c | |||
| @@ -8,12 +8,12 @@ | |||
| 8 | 8 | ||
| 9 | #include <linux/module.h> | 9 | #include <linux/module.h> |
| 10 | #include <linux/dma-mapping.h> | 10 | #include <linux/dma-mapping.h> |
| 11 | #include <linux/clk/at91_pmc.h> | ||
| 11 | 12 | ||
| 12 | #include <asm/irq.h> | 13 | #include <asm/irq.h> |
| 13 | #include <asm/mach/arch.h> | 14 | #include <asm/mach/arch.h> |
| 14 | #include <asm/mach/map.h> | 15 | #include <asm/mach/map.h> |
| 15 | #include <mach/at91sam9x5.h> | 16 | #include <mach/at91sam9x5.h> |
| 16 | #include <mach/at91_pmc.h> | ||
| 17 | #include <mach/cpu.h> | 17 | #include <mach/cpu.h> |
| 18 | 18 | ||
| 19 | #include "board.h" | 19 | #include "board.h" |
diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c index bf00d15d954d..075ec0576ada 100644 --- a/arch/arm/mach-at91/board-dt-sama5.c +++ b/arch/arm/mach-at91/board-dt-sama5.c | |||
| @@ -16,6 +16,7 @@ | |||
| 16 | #include <linux/of_irq.h> | 16 | #include <linux/of_irq.h> |
| 17 | #include <linux/of_platform.h> | 17 | #include <linux/of_platform.h> |
| 18 | #include <linux/phy.h> | 18 | #include <linux/phy.h> |
| 19 | #include <linux/clk-provider.h> | ||
| 19 | 20 | ||
| 20 | #include <asm/setup.h> | 21 | #include <asm/setup.h> |
| 21 | #include <asm/irq.h> | 22 | #include <asm/irq.h> |
| @@ -26,6 +27,13 @@ | |||
| 26 | #include "at91_aic.h" | 27 | #include "at91_aic.h" |
| 27 | #include "generic.h" | 28 | #include "generic.h" |
| 28 | 29 | ||
| 30 | static void __init sama5_dt_timer_init(void) | ||
| 31 | { | ||
| 32 | #if defined(CONFIG_COMMON_CLK) | ||
| 33 | of_clk_init(NULL); | ||
| 34 | #endif | ||
| 35 | at91sam926x_pit_init(); | ||
| 36 | } | ||
| 29 | 37 | ||
| 30 | static const struct of_device_id irq_of_match[] __initconst = { | 38 | static const struct of_device_id irq_of_match[] __initconst = { |
| 31 | 39 | ||
| @@ -72,7 +80,7 @@ static const char *sama5_dt_board_compat[] __initdata = { | |||
| 72 | 80 | ||
| 73 | DT_MACHINE_START(sama5_dt, "Atmel SAMA5 (Device Tree)") | 81 | DT_MACHINE_START(sama5_dt, "Atmel SAMA5 (Device Tree)") |
| 74 | /* Maintainer: Atmel */ | 82 | /* Maintainer: Atmel */ |
| 75 | .init_time = at91sam926x_pit_init, | 83 | .init_time = sama5_dt_timer_init, |
| 76 | .map_io = at91_map_io, | 84 | .map_io = at91_map_io, |
| 77 | .handle_irq = at91_aic5_handle_irq, | 85 | .handle_irq = at91_aic5_handle_irq, |
| 78 | .init_early = at91_dt_initialize, | 86 | .init_early = at91_dt_initialize, |
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c index 6b2630a92f71..72b257944733 100644 --- a/arch/arm/mach-at91/clock.c +++ b/arch/arm/mach-at91/clock.c | |||
| @@ -24,9 +24,9 @@ | |||
| 24 | #include <linux/clk.h> | 24 | #include <linux/clk.h> |
| 25 | #include <linux/io.h> | 25 | #include <linux/io.h> |
| 26 | #include <linux/of_address.h> | 26 | #include <linux/of_address.h> |
| 27 | #include <linux/clk/at91_pmc.h> | ||
| 27 | 28 | ||
| 28 | #include <mach/hardware.h> | 29 | #include <mach/hardware.h> |
| 29 | #include <mach/at91_pmc.h> | ||
| 30 | #include <mach/cpu.h> | 30 | #include <mach/cpu.h> |
| 31 | 31 | ||
| 32 | #include <asm/proc-fns.h> | 32 | #include <asm/proc-fns.h> |
| @@ -884,6 +884,11 @@ static int __init at91_pmc_init(unsigned long main_clock) | |||
| 884 | #if defined(CONFIG_OF) | 884 | #if defined(CONFIG_OF) |
| 885 | static struct of_device_id pmc_ids[] = { | 885 | static struct of_device_id pmc_ids[] = { |
| 886 | { .compatible = "atmel,at91rm9200-pmc" }, | 886 | { .compatible = "atmel,at91rm9200-pmc" }, |
| 887 | { .compatible = "atmel,at91sam9260-pmc" }, | ||
| 888 | { .compatible = "atmel,at91sam9g45-pmc" }, | ||
| 889 | { .compatible = "atmel,at91sam9n12-pmc" }, | ||
| 890 | { .compatible = "atmel,at91sam9x5-pmc" }, | ||
| 891 | { .compatible = "atmel,sama5d3-pmc" }, | ||
| 887 | { /*sentinel*/ } | 892 | { /*sentinel*/ } |
| 888 | }; | 893 | }; |
| 889 | 894 | ||
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h index 26dee3ce9397..631fa3b8c16d 100644 --- a/arch/arm/mach-at91/generic.h +++ b/arch/arm/mach-at91/generic.h | |||
| @@ -46,11 +46,12 @@ extern void at91sam926x_pit_init(void); | |||
| 46 | extern void at91x40_timer_init(void); | 46 | extern void at91x40_timer_init(void); |
| 47 | 47 | ||
| 48 | /* Clocks */ | 48 | /* Clocks */ |
| 49 | #ifdef CONFIG_AT91_PMC_UNIT | 49 | #ifdef CONFIG_OLD_CLK_AT91 |
| 50 | extern int __init at91_clock_init(unsigned long main_clock); | 50 | extern int __init at91_clock_init(unsigned long main_clock); |
| 51 | extern int __init at91_dt_clock_init(void); | 51 | extern int __init at91_dt_clock_init(void); |
| 52 | #else | 52 | #else |
| 53 | static int inline at91_clock_init(unsigned long main_clock) { return 0; } | 53 | static int inline at91_clock_init(unsigned long main_clock) { return 0; } |
| 54 | static int inline at91_dt_clock_init(void) { return 0; } | ||
| 54 | #endif | 55 | #endif |
| 55 | struct device; | 56 | struct device; |
| 56 | 57 | ||
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index 9986542e8060..d43b79f56e94 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c | |||
| @@ -19,13 +19,13 @@ | |||
| 19 | #include <linux/module.h> | 19 | #include <linux/module.h> |
| 20 | #include <linux/platform_device.h> | 20 | #include <linux/platform_device.h> |
| 21 | #include <linux/io.h> | 21 | #include <linux/io.h> |
| 22 | #include <linux/clk/at91_pmc.h> | ||
| 22 | 23 | ||
| 23 | #include <asm/irq.h> | 24 | #include <asm/irq.h> |
| 24 | #include <linux/atomic.h> | 25 | #include <linux/atomic.h> |
| 25 | #include <asm/mach/time.h> | 26 | #include <asm/mach/time.h> |
| 26 | #include <asm/mach/irq.h> | 27 | #include <asm/mach/irq.h> |
| 27 | 28 | ||
| 28 | #include <mach/at91_pmc.h> | ||
| 29 | #include <mach/cpu.h> | 29 | #include <mach/cpu.h> |
| 30 | 30 | ||
| 31 | #include "at91_aic.h" | 31 | #include "at91_aic.h" |
diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S index 098c28ddf025..20018779bae7 100644 --- a/arch/arm/mach-at91/pm_slowclock.S +++ b/arch/arm/mach-at91/pm_slowclock.S | |||
| @@ -13,8 +13,8 @@ | |||
| 13 | */ | 13 | */ |
| 14 | 14 | ||
| 15 | #include <linux/linkage.h> | 15 | #include <linux/linkage.h> |
| 16 | #include <linux/clk/at91_pmc.h> | ||
| 16 | #include <mach/hardware.h> | 17 | #include <mach/hardware.h> |
| 17 | #include <mach/at91_pmc.h> | ||
| 18 | #include <mach/at91_ramc.h> | 18 | #include <mach/at91_ramc.h> |
| 19 | 19 | ||
| 20 | 20 | ||
diff --git a/arch/arm/mach-at91/sama5d3.c b/arch/arm/mach-at91/sama5d3.c index a28873fe3049..3d775d08de08 100644 --- a/arch/arm/mach-at91/sama5d3.c +++ b/arch/arm/mach-at91/sama5d3.c | |||
| @@ -9,360 +9,19 @@ | |||
| 9 | 9 | ||
| 10 | #include <linux/module.h> | 10 | #include <linux/module.h> |
| 11 | #include <linux/dma-mapping.h> | 11 | #include <linux/dma-mapping.h> |
| 12 | #include <linux/clk/at91_pmc.h> | ||
| 12 | 13 | ||
| 13 | #include <asm/irq.h> | 14 | #include <asm/irq.h> |
| 14 | #include <asm/mach/arch.h> | 15 | #include <asm/mach/arch.h> |
| 15 | #include <asm/mach/map.h> | 16 | #include <asm/mach/map.h> |
| 16 | #include <mach/sama5d3.h> | 17 | #include <mach/sama5d3.h> |
| 17 | #include <mach/at91_pmc.h> | ||
| 18 | #include <mach/cpu.h> | 18 | #include <mach/cpu.h> |
| 19 | 19 | ||
| 20 | #include "soc.h" | 20 | #include "soc.h" |
| 21 | #include "generic.h" | 21 | #include "generic.h" |
| 22 | #include "clock.h" | ||
| 23 | #include "sam9_smc.h" | 22 | #include "sam9_smc.h" |
| 24 | 23 | ||
| 25 | /* -------------------------------------------------------------------- | 24 | /* -------------------------------------------------------------------- |
| 26 | * Clocks | ||
| 27 | * -------------------------------------------------------------------- */ | ||
| 28 | |||
| 29 | /* | ||
| 30 | * The peripheral clocks. | ||
| 31 | */ | ||
| 32 | |||
| 33 | static struct clk pioA_clk = { | ||
| 34 | .name = "pioA_clk", | ||
| 35 | .pid = SAMA5D3_ID_PIOA, | ||
| 36 | .type = CLK_TYPE_PERIPHERAL, | ||
| 37 | }; | ||
| 38 | static struct clk pioB_clk = { | ||
| 39 | .name = "pioB_clk", | ||
| 40 | .pid = SAMA5D3_ID_PIOB, | ||
| 41 | .type = CLK_TYPE_PERIPHERAL, | ||
| 42 | }; | ||
| 43 | static struct clk pioC_clk = { | ||
| 44 | .name = "pioC_clk", | ||
| 45 | .pid = SAMA5D3_ID_PIOC, | ||
| 46 | .type = CLK_TYPE_PERIPHERAL, | ||
| 47 | }; | ||
| 48 | static struct clk pioD_clk = { | ||
| 49 | .name = "pioD_clk", | ||
| 50 | .pid = SAMA5D3_ID_PIOD, | ||
| 51 | .type = CLK_TYPE_PERIPHERAL, | ||
| 52 | }; | ||
| 53 | static struct clk pioE_clk = { | ||
| 54 | .name = "pioE_clk", | ||
| 55 | .pid = SAMA5D3_ID_PIOE, | ||
| 56 | .type = CLK_TYPE_PERIPHERAL, | ||
| 57 | }; | ||
| 58 | static struct clk usart0_clk = { | ||
| 59 | .name = "usart0_clk", | ||
| 60 | .pid = SAMA5D3_ID_USART0, | ||
| 61 | .type = CLK_TYPE_PERIPHERAL, | ||
| 62 | .div = AT91_PMC_PCR_DIV2, | ||
| 63 | }; | ||
| 64 | static struct clk usart1_clk = { | ||
| 65 | .name = "usart1_clk", | ||
| 66 | .pid = SAMA5D3_ID_USART1, | ||
| 67 | .type = CLK_TYPE_PERIPHERAL, | ||
| 68 | .div = AT91_PMC_PCR_DIV2, | ||
| 69 | }; | ||
| 70 | static struct clk usart2_clk = { | ||
| 71 | .name = "usart2_clk", | ||
| 72 | .pid = SAMA5D3_ID_USART2, | ||
| 73 | .type = CLK_TYPE_PERIPHERAL, | ||
| 74 | .div = AT91_PMC_PCR_DIV2, | ||
| 75 | }; | ||
| 76 | static struct clk usart3_clk = { | ||
| 77 | .name = "usart3_clk", | ||
| 78 | .pid = SAMA5D3_ID_USART3, | ||
| 79 | .type = CLK_TYPE_PERIPHERAL, | ||
| 80 | .div = AT91_PMC_PCR_DIV2, | ||
| 81 | }; | ||
| 82 | static struct clk uart0_clk = { | ||
| 83 | .name = "uart0_clk", | ||
| 84 | .pid = SAMA5D3_ID_UART0, | ||
| 85 | .type = CLK_TYPE_PERIPHERAL, | ||
| 86 | .div = AT91_PMC_PCR_DIV2, | ||
| 87 | }; | ||
| 88 | static struct clk uart1_clk = { | ||
| 89 | .name = "uart1_clk", | ||
| 90 | .pid = SAMA5D3_ID_UART1, | ||
| 91 | .type = CLK_TYPE_PERIPHERAL, | ||
| 92 | .div = AT91_PMC_PCR_DIV2, | ||
| 93 | }; | ||
| 94 | static struct clk twi0_clk = { | ||
| 95 | .name = "twi0_clk", | ||
| 96 | .pid = SAMA5D3_ID_TWI0, | ||
| 97 | .type = CLK_TYPE_PERIPHERAL, | ||
| 98 | .div = AT91_PMC_PCR_DIV8, | ||
| 99 | }; | ||
| 100 | static struct clk twi1_clk = { | ||
| 101 | .name = "twi1_clk", | ||
| 102 | .pid = SAMA5D3_ID_TWI1, | ||
| 103 | .type = CLK_TYPE_PERIPHERAL, | ||
| 104 | .div = AT91_PMC_PCR_DIV8, | ||
| 105 | }; | ||
| 106 | static struct clk twi2_clk = { | ||
| 107 | .name = "twi2_clk", | ||
| 108 | .pid = SAMA5D3_ID_TWI2, | ||
| 109 | .type = CLK_TYPE_PERIPHERAL, | ||
| 110 | .div = AT91_PMC_PCR_DIV8, | ||
| 111 | }; | ||
| 112 | static struct clk mmc0_clk = { | ||
| 113 | .name = "mci0_clk", | ||
| 114 | .pid = SAMA5D3_ID_HSMCI0, | ||
| 115 | .type = CLK_TYPE_PERIPHERAL, | ||
| 116 | }; | ||
| 117 | static struct clk mmc1_clk = { | ||
| 118 | .name = "mci1_clk", | ||
| 119 | .pid = SAMA5D3_ID_HSMCI1, | ||
| 120 | .type = CLK_TYPE_PERIPHERAL, | ||
| 121 | }; | ||
| 122 | static struct clk mmc2_clk = { | ||
| 123 | .name = "mci2_clk", | ||
| 124 | .pid = SAMA5D3_ID_HSMCI2, | ||
| 125 | .type = CLK_TYPE_PERIPHERAL, | ||
| 126 | }; | ||
| 127 | static struct clk spi0_clk = { | ||
| 128 | .name = "spi0_clk", | ||
| 129 | .pid = SAMA5D3_ID_SPI0, | ||
| 130 | .type = CLK_TYPE_PERIPHERAL, | ||
| 131 | }; | ||
| 132 | static struct clk spi1_clk = { | ||
| 133 | .name = "spi1_clk", | ||
| 134 | .pid = SAMA5D3_ID_SPI1, | ||
| 135 | .type = CLK_TYPE_PERIPHERAL, | ||
| 136 | }; | ||
| 137 | static struct clk tcb0_clk = { | ||
| 138 | .name = "tcb0_clk", | ||
| 139 | .pid = SAMA5D3_ID_TC0, | ||
| 140 | .type = CLK_TYPE_PERIPHERAL, | ||
| 141 | .div = AT91_PMC_PCR_DIV2, | ||
| 142 | }; | ||
| 143 | static struct clk tcb1_clk = { | ||
| 144 | .name = "tcb1_clk", | ||
| 145 | .pid = SAMA5D3_ID_TC1, | ||
| 146 | .type = CLK_TYPE_PERIPHERAL, | ||
| 147 | .div = AT91_PMC_PCR_DIV2, | ||
| 148 | }; | ||
| 149 | static struct clk adc_clk = { | ||
| 150 | .name = "adc_clk", | ||
| 151 | .pid = SAMA5D3_ID_ADC, | ||
| 152 | .type = CLK_TYPE_PERIPHERAL, | ||
| 153 | .div = AT91_PMC_PCR_DIV2, | ||
| 154 | }; | ||
| 155 | static struct clk adc_op_clk = { | ||
| 156 | .name = "adc_op_clk", | ||
| 157 | .type = CLK_TYPE_PERIPHERAL, | ||
| 158 | .rate_hz = 5000000, | ||
| 159 | }; | ||
| 160 | static struct clk dma0_clk = { | ||
| 161 | .name = "dma0_clk", | ||
| 162 | .pid = SAMA5D3_ID_DMA0, | ||
| 163 | .type = CLK_TYPE_PERIPHERAL, | ||
| 164 | }; | ||
| 165 | static struct clk dma1_clk = { | ||
| 166 | .name = "dma1_clk", | ||
| 167 | .pid = SAMA5D3_ID_DMA1, | ||
| 168 | .type = CLK_TYPE_PERIPHERAL, | ||
| 169 | }; | ||
| 170 | static struct clk uhphs_clk = { | ||
| 171 | .name = "uhphs", | ||
| 172 | .pid = SAMA5D3_ID_UHPHS, | ||
| 173 | .type = CLK_TYPE_PERIPHERAL, | ||
| 174 | }; | ||
| 175 | static struct clk udphs_clk = { | ||
| 176 | .name = "udphs_clk", | ||
| 177 | .pid = SAMA5D3_ID_UDPHS, | ||
| 178 | .type = CLK_TYPE_PERIPHERAL, | ||
| 179 | }; | ||
| 180 | /* gmac only for sama5d33, sama5d34, sama5d35 */ | ||
| 181 | static struct clk macb0_clk = { | ||
| 182 | .name = "macb0_clk", | ||
| 183 | .pid = SAMA5D3_ID_GMAC, | ||
| 184 | .type = CLK_TYPE_PERIPHERAL, | ||
| 185 | }; | ||
| 186 | /* emac only for sama5d31, sama5d35 */ | ||
| 187 | static struct clk macb1_clk = { | ||
| 188 | .name = "macb1_clk", | ||
| 189 | .pid = SAMA5D3_ID_EMAC, | ||
| 190 | .type = CLK_TYPE_PERIPHERAL, | ||
| 191 | }; | ||
| 192 | /* lcd only for sama5d31, sama5d33, sama5d34 */ | ||
| 193 | static struct clk lcdc_clk = { | ||
| 194 | .name = "lcdc_clk", | ||
| 195 | .pid = SAMA5D3_ID_LCDC, | ||
| 196 | .type = CLK_TYPE_PERIPHERAL, | ||
| 197 | }; | ||
| 198 | /* isi only for sama5d33, sama5d35 */ | ||
| 199 | static struct clk isi_clk = { | ||
| 200 | .name = "isi_clk", | ||
| 201 | .pid = SAMA5D3_ID_ISI, | ||
| 202 | .type = CLK_TYPE_PERIPHERAL, | ||
| 203 | }; | ||
| 204 | static struct clk can0_clk = { | ||
| 205 | .name = "can0_clk", | ||
| 206 | .pid = SAMA5D3_ID_CAN0, | ||
| 207 | .type = CLK_TYPE_PERIPHERAL, | ||
| 208 | .div = AT91_PMC_PCR_DIV2, | ||
| 209 | }; | ||
| 210 | static struct clk can1_clk = { | ||
| 211 | .name = "can1_clk", | ||
| 212 | .pid = SAMA5D3_ID_CAN1, | ||
| 213 | .type = CLK_TYPE_PERIPHERAL, | ||
| 214 | .div = AT91_PMC_PCR_DIV2, | ||
| 215 | }; | ||
| 216 | static struct clk ssc0_clk = { | ||
| 217 | .name = "ssc0_clk", | ||
| 218 | .pid = SAMA5D3_ID_SSC0, | ||
| 219 | .type = CLK_TYPE_PERIPHERAL, | ||
| 220 | .div = AT91_PMC_PCR_DIV2, | ||
| 221 | }; | ||
| 222 | static struct clk ssc1_clk = { | ||
| 223 | .name = "ssc1_clk", | ||
| 224 | .pid = SAMA5D3_ID_SSC1, | ||
| 225 | .type = CLK_TYPE_PERIPHERAL, | ||
| 226 | .div = AT91_PMC_PCR_DIV2, | ||
| 227 | }; | ||
| 228 | static struct clk sha_clk = { | ||
| 229 | .name = "sha_clk", | ||
| 230 | .pid = SAMA5D3_ID_SHA, | ||
| 231 | .type = CLK_TYPE_PERIPHERAL, | ||
| 232 | .div = AT91_PMC_PCR_DIV8, | ||
| 233 | }; | ||
| 234 | static struct clk aes_clk = { | ||
| 235 | .name = "aes_clk", | ||
| 236 | .pid = SAMA5D3_ID_AES, | ||
| 237 | .type = CLK_TYPE_PERIPHERAL, | ||
| 238 | }; | ||
| 239 | static struct clk tdes_clk = { | ||
| 240 | .name = "tdes_clk", | ||
| 241 | .pid = SAMA5D3_ID_TDES, | ||
| 242 | .type = CLK_TYPE_PERIPHERAL, | ||
| 243 | }; | ||
| 244 | |||
| 245 | static struct clk *periph_clocks[] __initdata = { | ||
| 246 | &pioA_clk, | ||
| 247 | &pioB_clk, | ||
| 248 | &pioC_clk, | ||
| 249 | &pioD_clk, | ||
| 250 | &pioE_clk, | ||
| 251 | &usart0_clk, | ||
| 252 | &usart1_clk, | ||
| 253 | &usart2_clk, | ||
| 254 | &usart3_clk, | ||
| 255 | &uart0_clk, | ||
| 256 | &uart1_clk, | ||
| 257 | &twi0_clk, | ||
| 258 | &twi1_clk, | ||
| 259 | &twi2_clk, | ||
| 260 | &mmc0_clk, | ||
| 261 | &mmc1_clk, | ||
| 262 | &mmc2_clk, | ||
| 263 | &spi0_clk, | ||
| 264 | &spi1_clk, | ||
| 265 | &tcb0_clk, | ||
| 266 | &tcb1_clk, | ||
| 267 | &adc_clk, | ||
| 268 | &adc_op_clk, | ||
| 269 | &dma0_clk, | ||
| 270 | &dma1_clk, | ||
| 271 | &uhphs_clk, | ||
| 272 | &udphs_clk, | ||
| 273 | &macb0_clk, | ||
| 274 | &macb1_clk, | ||
| 275 | &lcdc_clk, | ||
| 276 | &isi_clk, | ||
| 277 | &can0_clk, | ||
| 278 | &can1_clk, | ||
| 279 | &ssc0_clk, | ||
| 280 | &ssc1_clk, | ||
| 281 | &sha_clk, | ||
| 282 | &aes_clk, | ||
| 283 | &tdes_clk, | ||
| 284 | }; | ||
| 285 | |||
| 286 | static struct clk pck0 = { | ||
| 287 | .name = "pck0", | ||
| 288 | .pmc_mask = AT91_PMC_PCK0, | ||
| 289 | .type = CLK_TYPE_PROGRAMMABLE, | ||
| 290 | .id = 0, | ||
| 291 | }; | ||
| 292 | |||
| 293 | static struct clk pck1 = { | ||
| 294 | .name = "pck1", | ||
| 295 | .pmc_mask = AT91_PMC_PCK1, | ||
| 296 | .type = CLK_TYPE_PROGRAMMABLE, | ||
| 297 | .id = 1, | ||
| 298 | }; | ||
| 299 | |||
| 300 | static struct clk pck2 = { | ||
| 301 | .name = "pck2", | ||
| 302 | .pmc_mask = AT91_PMC_PCK2, | ||
| 303 | .type = CLK_TYPE_PROGRAMMABLE, | ||
| 304 | .id = 2, | ||
| 305 | }; | ||
| 306 | |||
| 307 | static struct clk_lookup periph_clocks_lookups[] = { | ||
| 308 | /* lookup table for DT entries */ | ||
| 309 | CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck), | ||
| 310 | CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk), | ||
| 311 | CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk), | ||
| 312 | CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioC_clk), | ||
| 313 | CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioD_clk), | ||
| 314 | CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioE_clk), | ||
| 315 | CLKDEV_CON_DEV_ID("usart", "f001c000.serial", &usart0_clk), | ||
| 316 | CLKDEV_CON_DEV_ID("usart", "f0020000.serial", &usart1_clk), | ||
| 317 | CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart2_clk), | ||
| 318 | CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart3_clk), | ||
| 319 | CLKDEV_CON_DEV_ID(NULL, "f0014000.i2c", &twi0_clk), | ||
| 320 | CLKDEV_CON_DEV_ID(NULL, "f0018000.i2c", &twi1_clk), | ||
| 321 | CLKDEV_CON_DEV_ID(NULL, "f801c000.i2c", &twi2_clk), | ||
| 322 | CLKDEV_CON_DEV_ID("mci_clk", "f0000000.mmc", &mmc0_clk), | ||
| 323 | CLKDEV_CON_DEV_ID("mci_clk", "f8000000.mmc", &mmc1_clk), | ||
| 324 | CLKDEV_CON_DEV_ID("mci_clk", "f8004000.mmc", &mmc2_clk), | ||
| 325 | CLKDEV_CON_DEV_ID("spi_clk", "f0004000.spi", &spi0_clk), | ||
| 326 | CLKDEV_CON_DEV_ID("spi_clk", "f8008000.spi", &spi1_clk), | ||
| 327 | CLKDEV_CON_DEV_ID("t0_clk", "f0010000.timer", &tcb0_clk), | ||
| 328 | CLKDEV_CON_DEV_ID("t0_clk", "f8014000.timer", &tcb1_clk), | ||
| 329 | CLKDEV_CON_DEV_ID("tsc_clk", "f8018000.tsadcc", &adc_clk), | ||
| 330 | CLKDEV_CON_DEV_ID("dma_clk", "ffffe600.dma-controller", &dma0_clk), | ||
| 331 | CLKDEV_CON_DEV_ID("dma_clk", "ffffe800.dma-controller", &dma1_clk), | ||
| 332 | CLKDEV_CON_DEV_ID("hclk", "600000.ohci", &uhphs_clk), | ||
| 333 | CLKDEV_CON_DEV_ID("ohci_clk", "600000.ohci", &uhphs_clk), | ||
| 334 | CLKDEV_CON_DEV_ID("ehci_clk", "700000.ehci", &uhphs_clk), | ||
| 335 | CLKDEV_CON_DEV_ID("pclk", "500000.gadget", &udphs_clk), | ||
| 336 | CLKDEV_CON_DEV_ID("hclk", "500000.gadget", &utmi_clk), | ||
| 337 | CLKDEV_CON_DEV_ID("hclk", "f0028000.ethernet", &macb0_clk), | ||
| 338 | CLKDEV_CON_DEV_ID("pclk", "f0028000.ethernet", &macb0_clk), | ||
| 339 | CLKDEV_CON_DEV_ID("hclk", "f802c000.ethernet", &macb1_clk), | ||
| 340 | CLKDEV_CON_DEV_ID("pclk", "f802c000.ethernet", &macb1_clk), | ||
| 341 | CLKDEV_CON_DEV_ID("pclk", "f0008000.ssc", &ssc0_clk), | ||
| 342 | CLKDEV_CON_DEV_ID("pclk", "f000c000.ssc", &ssc1_clk), | ||
| 343 | CLKDEV_CON_DEV_ID("can_clk", "f000c000.can", &can0_clk), | ||
| 344 | CLKDEV_CON_DEV_ID("can_clk", "f8010000.can", &can1_clk), | ||
| 345 | CLKDEV_CON_DEV_ID("sha_clk", "f8034000.sha", &sha_clk), | ||
| 346 | CLKDEV_CON_DEV_ID("aes_clk", "f8038000.aes", &aes_clk), | ||
| 347 | CLKDEV_CON_DEV_ID("tdes_clk", "f803c000.tdes", &tdes_clk), | ||
| 348 | }; | ||
| 349 | |||
| 350 | static void __init sama5d3_register_clocks(void) | ||
| 351 | { | ||
| 352 | int i; | ||
| 353 | |||
| 354 | for (i = 0; i < ARRAY_SIZE(periph_clocks); i++) | ||
| 355 | clk_register(periph_clocks[i]); | ||
| 356 | |||
| 357 | clkdev_add_table(periph_clocks_lookups, | ||
| 358 | ARRAY_SIZE(periph_clocks_lookups)); | ||
| 359 | |||
| 360 | clk_register(&pck0); | ||
| 361 | clk_register(&pck1); | ||
| 362 | clk_register(&pck2); | ||
| 363 | } | ||
| 364 | |||
| 365 | /* -------------------------------------------------------------------- | ||
| 366 | * AT91SAM9x5 processor initialization | 25 | * AT91SAM9x5 processor initialization |
| 367 | * -------------------------------------------------------------------- */ | 26 | * -------------------------------------------------------------------- */ |
| 368 | 27 | ||
| @@ -378,6 +37,5 @@ static void __init sama5d3_initialize(void) | |||
| 378 | 37 | ||
| 379 | AT91_SOC_START(sama5d3) | 38 | AT91_SOC_START(sama5d3) |
| 380 | .map_io = sama5d3_map_io, | 39 | .map_io = sama5d3_map_io, |
| 381 | .register_clocks = sama5d3_register_clocks, | ||
| 382 | .init = sama5d3_initialize, | 40 | .init = sama5d3_initialize, |
| 383 | AT91_SOC_END | 41 | AT91_SOC_END |
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c index 094b3459c288..7d3f7cc61081 100644 --- a/arch/arm/mach-at91/setup.c +++ b/arch/arm/mach-at91/setup.c | |||
| @@ -11,6 +11,7 @@ | |||
| 11 | #include <linux/pm.h> | 11 | #include <linux/pm.h> |
| 12 | #include <linux/of_address.h> | 12 | #include <linux/of_address.h> |
| 13 | #include <linux/pinctrl/machine.h> | 13 | #include <linux/pinctrl/machine.h> |
| 14 | #include <linux/clk/at91_pmc.h> | ||
| 14 | 15 | ||
| 15 | #include <asm/system_misc.h> | 16 | #include <asm/system_misc.h> |
| 16 | #include <asm/mach/map.h> | 17 | #include <asm/mach/map.h> |
| @@ -18,7 +19,6 @@ | |||
| 18 | #include <mach/hardware.h> | 19 | #include <mach/hardware.h> |
| 19 | #include <mach/cpu.h> | 20 | #include <mach/cpu.h> |
| 20 | #include <mach/at91_dbgu.h> | 21 | #include <mach/at91_dbgu.h> |
| 21 | #include <mach/at91_pmc.h> | ||
| 22 | 22 | ||
| 23 | #include "at91_shdwc.h" | 23 | #include "at91_shdwc.h" |
| 24 | #include "soc.h" | 24 | #include "soc.h" |
| @@ -491,7 +491,8 @@ void __init at91rm9200_dt_initialize(void) | |||
| 491 | at91_dt_clock_init(); | 491 | at91_dt_clock_init(); |
| 492 | 492 | ||
| 493 | /* Register the processor-specific clocks */ | 493 | /* Register the processor-specific clocks */ |
| 494 | at91_boot_soc.register_clocks(); | 494 | if (at91_boot_soc.register_clocks) |
| 495 | at91_boot_soc.register_clocks(); | ||
| 495 | 496 | ||
| 496 | at91_boot_soc.init(); | 497 | at91_boot_soc.init(); |
| 497 | } | 498 | } |
| @@ -506,7 +507,8 @@ void __init at91_dt_initialize(void) | |||
| 506 | at91_dt_clock_init(); | 507 | at91_dt_clock_init(); |
| 507 | 508 | ||
| 508 | /* Register the processor-specific clocks */ | 509 | /* Register the processor-specific clocks */ |
| 509 | at91_boot_soc.register_clocks(); | 510 | if (at91_boot_soc.register_clocks) |
| 511 | at91_boot_soc.register_clocks(); | ||
| 510 | 512 | ||
| 511 | if (at91_boot_soc.init) | 513 | if (at91_boot_soc.init) |
| 512 | at91_boot_soc.init(); | 514 | at91_boot_soc.init(); |
diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig index 2cb8dc55b50e..7094bccbae91 100644 --- a/arch/arm/mach-s3c64xx/Kconfig +++ b/arch/arm/mach-s3c64xx/Kconfig | |||
| @@ -17,9 +17,10 @@ config CPU_S3C6410 | |||
| 17 | help | 17 | help |
| 18 | Enable S3C6410 CPU support | 18 | Enable S3C6410 CPU support |
| 19 | 19 | ||
| 20 | config S3C64XX_DMA | 20 | config S3C64XX_PL080 |
| 21 | bool "S3C64XX DMA" | 21 | bool "S3C64XX DMA using generic PL08x driver" |
| 22 | select S3C_DMA | 22 | select AMBA_PL08X |
| 23 | select SAMSUNG_DMADEV | ||
| 23 | 24 | ||
| 24 | config S3C64XX_SETUP_SDHCI | 25 | config S3C64XX_SETUP_SDHCI |
| 25 | bool | 26 | bool |
diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile index 6faedcffce04..58069a702a43 100644 --- a/arch/arm/mach-s3c64xx/Makefile +++ b/arch/arm/mach-s3c64xx/Makefile | |||
| @@ -26,7 +26,7 @@ obj-$(CONFIG_CPU_IDLE) += cpuidle.o | |||
| 26 | 26 | ||
| 27 | # DMA support | 27 | # DMA support |
| 28 | 28 | ||
| 29 | obj-$(CONFIG_S3C64XX_DMA) += dma.o | 29 | obj-$(CONFIG_S3C64XX_PL080) += pl080.o |
| 30 | 30 | ||
| 31 | # Device support | 31 | # Device support |
| 32 | 32 | ||
diff --git a/arch/arm/mach-s3c64xx/common.h b/arch/arm/mach-s3c64xx/common.h index bd3bd562011e..7043e7a3a67e 100644 --- a/arch/arm/mach-s3c64xx/common.h +++ b/arch/arm/mach-s3c64xx/common.h | |||
| @@ -58,4 +58,9 @@ int __init s3c64xx_pm_late_initcall(void); | |||
| 58 | static inline int s3c64xx_pm_late_initcall(void) { return 0; } | 58 | static inline int s3c64xx_pm_late_initcall(void) { return 0; } |
| 59 | #endif | 59 | #endif |
| 60 | 60 | ||
| 61 | #ifdef CONFIG_S3C64XX_PL080 | ||
| 62 | extern struct pl08x_platform_data s3c64xx_dma0_plat_data; | ||
| 63 | extern struct pl08x_platform_data s3c64xx_dma1_plat_data; | ||
| 64 | #endif | ||
| 65 | |||
| 61 | #endif /* __ARCH_ARM_MACH_S3C64XX_COMMON_H */ | 66 | #endif /* __ARCH_ARM_MACH_S3C64XX_COMMON_H */ |
diff --git a/arch/arm/mach-s3c64xx/dma.c b/arch/arm/mach-s3c64xx/dma.c deleted file mode 100644 index 7e22c2113816..000000000000 --- a/arch/arm/mach-s3c64xx/dma.c +++ /dev/null | |||
| @@ -1,762 +0,0 @@ | |||
| 1 | /* linux/arch/arm/plat-s3c64xx/dma.c | ||
| 2 | * | ||
| 3 | * Copyright 2009 Openmoko, Inc. | ||
| 4 | * Copyright 2009 Simtec Electronics | ||
| 5 | * Ben Dooks <ben@simtec.co.uk> | ||
| 6 | * http://armlinux.simtec.co.uk/ | ||
| 7 | * | ||
| 8 | * S3C64XX DMA core | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | */ | ||
| 14 | |||
| 15 | /* | ||
| 16 | * NOTE: Code in this file is not used when booting with Device Tree support. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #include <linux/kernel.h> | ||
| 20 | #include <linux/module.h> | ||
| 21 | #include <linux/interrupt.h> | ||
| 22 | #include <linux/dmapool.h> | ||
| 23 | #include <linux/device.h> | ||
| 24 | #include <linux/errno.h> | ||
| 25 | #include <linux/slab.h> | ||
| 26 | #include <linux/delay.h> | ||
| 27 | #include <linux/clk.h> | ||
| 28 | #include <linux/err.h> | ||
| 29 | #include <linux/io.h> | ||
| 30 | #include <linux/amba/pl080.h> | ||
| 31 | #include <linux/of.h> | ||
| 32 | |||
| 33 | #include <mach/dma.h> | ||
| 34 | #include <mach/map.h> | ||
| 35 | #include <mach/irqs.h> | ||
| 36 | |||
| 37 | #include "regs-sys.h" | ||
| 38 | |||
| 39 | /* dma channel state information */ | ||
| 40 | |||
| 41 | struct s3c64xx_dmac { | ||
| 42 | struct device dev; | ||
| 43 | struct clk *clk; | ||
| 44 | void __iomem *regs; | ||
| 45 | struct s3c2410_dma_chan *channels; | ||
| 46 | enum dma_ch chanbase; | ||
| 47 | }; | ||
| 48 | |||
| 49 | /* pool to provide LLI buffers */ | ||
| 50 | static struct dma_pool *dma_pool; | ||
| 51 | |||
| 52 | /* Debug configuration and code */ | ||
| 53 | |||
| 54 | static unsigned char debug_show_buffs = 0; | ||
| 55 | |||
| 56 | static void dbg_showchan(struct s3c2410_dma_chan *chan) | ||
| 57 | { | ||
| 58 | pr_debug("DMA%d: %08x->%08x L %08x C %08x,%08x S %08x\n", | ||
| 59 | chan->number, | ||
| 60 | readl(chan->regs + PL080_CH_SRC_ADDR), | ||
| 61 | readl(chan->regs + PL080_CH_DST_ADDR), | ||
| 62 | readl(chan->regs + PL080_CH_LLI), | ||
| 63 | readl(chan->regs + PL080_CH_CONTROL), | ||
| 64 | readl(chan->regs + PL080S_CH_CONTROL2), | ||
| 65 | readl(chan->regs + PL080S_CH_CONFIG)); | ||
| 66 | } | ||
| 67 | |||
| 68 | static void show_lli(struct pl080s_lli *lli) | ||
| 69 | { | ||
| 70 | pr_debug("LLI[%p] %08x->%08x, NL %08x C %08x,%08x\n", | ||
| 71 | lli, lli->src_addr, lli->dst_addr, lli->next_lli, | ||
| 72 | lli->control0, lli->control1); | ||
| 73 | } | ||
| 74 | |||
| 75 | static void dbg_showbuffs(struct s3c2410_dma_chan *chan) | ||
| 76 | { | ||
| 77 | struct s3c64xx_dma_buff *ptr; | ||
| 78 | struct s3c64xx_dma_buff *end; | ||
| 79 | |||
| 80 | pr_debug("DMA%d: buffs next %p, curr %p, end %p\n", | ||
| 81 | chan->number, chan->next, chan->curr, chan->end); | ||
| 82 | |||
| 83 | ptr = chan->next; | ||
| 84 | end = chan->end; | ||
| 85 | |||
| 86 | if (debug_show_buffs) { | ||
| 87 | for (; ptr != NULL; ptr = ptr->next) { | ||
| 88 | pr_debug("DMA%d: %08x ", | ||
| 89 | chan->number, ptr->lli_dma); | ||
| 90 | show_lli(ptr->lli); | ||
| 91 | } | ||
| 92 | } | ||
| 93 | } | ||
| 94 | |||
| 95 | /* End of Debug */ | ||
| 96 | |||
| 97 | static struct s3c2410_dma_chan *s3c64xx_dma_map_channel(unsigned int channel) | ||
| 98 | { | ||
| 99 | struct s3c2410_dma_chan *chan; | ||
| 100 | unsigned int start, offs; | ||
| 101 | |||
| 102 | start = 0; | ||
| 103 | |||
| 104 | if (channel >= DMACH_PCM1_TX) | ||
| 105 | start = 8; | ||
| 106 | |||
| 107 | for (offs = 0; offs < 8; offs++) { | ||
| 108 | chan = &s3c2410_chans[start + offs]; | ||
| 109 | if (!chan->in_use) | ||
| 110 | goto found; | ||
| 111 | } | ||
| 112 | |||
| 113 | return NULL; | ||
| 114 | |||
| 115 | found: | ||
| 116 | s3c_dma_chan_map[channel] = chan; | ||
| 117 | return chan; | ||
| 118 | } | ||
| 119 | |||
| 120 | int s3c2410_dma_config(enum dma_ch channel, int xferunit) | ||
| 121 | { | ||
| 122 | struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel); | ||
| 123 | |||
| 124 | if (chan == NULL) | ||
| 125 | return -EINVAL; | ||
| 126 | |||
| 127 | switch (xferunit) { | ||
| 128 | case 1: | ||
| 129 | chan->hw_width = 0; | ||
| 130 | break; | ||
| 131 | case 2: | ||
| 132 | chan->hw_width = 1; | ||
| 133 | break; | ||
| 134 | case 4: | ||
| 135 | chan->hw_width = 2; | ||
| 136 | break; | ||
| 137 | default: | ||
| 138 | printk(KERN_ERR "%s: illegal width %d\n", __func__, xferunit); | ||
| 139 | return -EINVAL; | ||
| 140 | } | ||
| 141 | |||
| 142 | return 0; | ||
| 143 | } | ||
| 144 | EXPORT_SYMBOL(s3c2410_dma_config); | ||
| 145 | |||
| 146 | static void s3c64xx_dma_fill_lli(struct s3c2410_dma_chan *chan, | ||
| 147 | struct pl080s_lli *lli, | ||
| 148 | dma_addr_t data, int size) | ||
| 149 | { | ||
| 150 | dma_addr_t src, dst; | ||
| 151 | u32 control0, control1; | ||
| 152 | |||
| 153 | switch (chan->source) { | ||
| 154 | case DMA_FROM_DEVICE: | ||
| 155 | src = chan->dev_addr; | ||
| 156 | dst = data; | ||
| 157 | control0 = PL080_CONTROL_SRC_AHB2; | ||
| 158 | control0 |= PL080_CONTROL_DST_INCR; | ||
| 159 | break; | ||
| 160 | |||
| 161 | case DMA_TO_DEVICE: | ||
| 162 | src = data; | ||
| 163 | dst = chan->dev_addr; | ||
| 164 | control0 = PL080_CONTROL_DST_AHB2; | ||
| 165 | control0 |= PL080_CONTROL_SRC_INCR; | ||
| 166 | break; | ||
| 167 | default: | ||
| 168 | BUG(); | ||
| 169 | } | ||
| 170 | |||
| 171 | /* note, we do not currently setup any of the burst controls */ | ||
| 172 | |||
| 173 | control1 = size >> chan->hw_width; /* size in no of xfers */ | ||
| 174 | control0 |= PL080_CONTROL_PROT_SYS; /* always in priv. mode */ | ||
| 175 | control0 |= PL080_CONTROL_TC_IRQ_EN; /* always fire IRQ */ | ||
| 176 | control0 |= (u32)chan->hw_width << PL080_CONTROL_DWIDTH_SHIFT; | ||
| 177 | control0 |= (u32)chan->hw_width << PL080_CONTROL_SWIDTH_SHIFT; | ||
| 178 | |||
| 179 | lli->src_addr = src; | ||
| 180 | lli->dst_addr = dst; | ||
| 181 | lli->next_lli = 0; | ||
| 182 | lli->control0 = control0; | ||
| 183 | lli->control1 = control1; | ||
| 184 | } | ||
| 185 | |||
| 186 | static void s3c64xx_lli_to_regs(struct s3c2410_dma_chan *chan, | ||
| 187 | struct pl080s_lli *lli) | ||
| 188 | { | ||
| 189 | void __iomem *regs = chan->regs; | ||
| 190 | |||
| 191 | pr_debug("%s: LLI %p => regs\n", __func__, lli); | ||
| 192 | show_lli(lli); | ||
| 193 | |||
| 194 | writel(lli->src_addr, regs + PL080_CH_SRC_ADDR); | ||
| 195 | writel(lli->dst_addr, regs + PL080_CH_DST_ADDR); | ||
| 196 | writel(lli->next_lli, regs + PL080_CH_LLI); | ||
| 197 | writel(lli->control0, regs + PL080_CH_CONTROL); | ||
| 198 | writel(lli->control1, regs + PL080S_CH_CONTROL2); | ||
| 199 | } | ||
| 200 | |||
| 201 | static int s3c64xx_dma_start(struct s3c2410_dma_chan *chan) | ||
| 202 | { | ||
| 203 | struct s3c64xx_dmac *dmac = chan->dmac; | ||
| 204 | u32 config; | ||
| 205 | u32 bit = chan->bit; | ||
| 206 | |||
| 207 | dbg_showchan(chan); | ||
| 208 | |||
| 209 | pr_debug("%s: clearing interrupts\n", __func__); | ||
| 210 | |||
| 211 | /* clear interrupts */ | ||
| 212 | writel(bit, dmac->regs + PL080_TC_CLEAR); | ||
| 213 | writel(bit, dmac->regs + PL080_ERR_CLEAR); | ||
| 214 | |||
| 215 | pr_debug("%s: starting channel\n", __func__); | ||
| 216 | |||
| 217 | config = readl(chan->regs + PL080S_CH_CONFIG); | ||
| 218 | config |= PL080_CONFIG_ENABLE; | ||
| 219 | config &= ~PL080_CONFIG_HALT; | ||
| 220 | |||
| 221 | pr_debug("%s: writing config %08x\n", __func__, config); | ||
| 222 | writel(config, chan->regs + PL080S_CH_CONFIG); | ||
| 223 | |||
| 224 | return 0; | ||
| 225 | } | ||
| 226 | |||
| 227 | static int s3c64xx_dma_stop(struct s3c2410_dma_chan *chan) | ||
| 228 | { | ||
| 229 | u32 config; | ||
| 230 | int timeout; | ||
| 231 | |||
| 232 | pr_debug("%s: stopping channel\n", __func__); | ||
| 233 | |||
| 234 | dbg_showchan(chan); | ||
| 235 | |||
| 236 | config = readl(chan->regs + PL080S_CH_CONFIG); | ||
| 237 | config |= PL080_CONFIG_HALT; | ||
| 238 | writel(config, chan->regs + PL080S_CH_CONFIG); | ||
| 239 | |||
| 240 | timeout = 1000; | ||
| 241 | do { | ||
| 242 | config = readl(chan->regs + PL080S_CH_CONFIG); | ||
| 243 | pr_debug("%s: %d - config %08x\n", __func__, timeout, config); | ||
| 244 | if (config & PL080_CONFIG_ACTIVE) | ||
| 245 | udelay(10); | ||
| 246 | else | ||
| 247 | break; | ||
| 248 | } while (--timeout > 0); | ||
| 249 | |||
| 250 | if (config & PL080_CONFIG_ACTIVE) { | ||
| 251 | printk(KERN_ERR "%s: channel still active\n", __func__); | ||
| 252 | return -EFAULT; | ||
| 253 | } | ||
| 254 | |||
| 255 | config = readl(chan->regs + PL080S_CH_CONFIG); | ||
| 256 | config &= ~PL080_CONFIG_ENABLE; | ||
| 257 | writel(config, chan->regs + PL080S_CH_CONFIG); | ||
| 258 | |||
| 259 | return 0; | ||
| 260 | } | ||
| 261 | |||
| 262 | static inline void s3c64xx_dma_bufffdone(struct s3c2410_dma_chan *chan, | ||
| 263 | struct s3c64xx_dma_buff *buf, | ||
| 264 | enum s3c2410_dma_buffresult result) | ||
| 265 | { | ||
| 266 | if (chan->callback_fn != NULL) | ||
| 267 | (chan->callback_fn)(chan, buf->pw, 0, result); | ||
| 268 | } | ||
| 269 | |||
| 270 | static void s3c64xx_dma_freebuff(struct s3c64xx_dma_buff *buff) | ||
| 271 | { | ||
| 272 | dma_pool_free(dma_pool, buff->lli, buff->lli_dma); | ||
| 273 | kfree(buff); | ||
| 274 | } | ||
| 275 | |||
| 276 | static int s3c64xx_dma_flush(struct s3c2410_dma_chan *chan) | ||
| 277 | { | ||
| 278 | struct s3c64xx_dma_buff *buff, *next; | ||
| 279 | u32 config; | ||
| 280 | |||
| 281 | dbg_showchan(chan); | ||
| 282 | |||
| 283 | pr_debug("%s: flushing channel\n", __func__); | ||
| 284 | |||
| 285 | config = readl(chan->regs + PL080S_CH_CONFIG); | ||
| 286 | config &= ~PL080_CONFIG_ENABLE; | ||
| 287 | writel(config, chan->regs + PL080S_CH_CONFIG); | ||
| 288 | |||
| 289 | /* dump all the buffers associated with this channel */ | ||
| 290 | |||
| 291 | for (buff = chan->curr; buff != NULL; buff = next) { | ||
| 292 | next = buff->next; | ||
| 293 | pr_debug("%s: buff %p (next %p)\n", __func__, buff, buff->next); | ||
| 294 | |||
| 295 | s3c64xx_dma_bufffdone(chan, buff, S3C2410_RES_ABORT); | ||
| 296 | s3c64xx_dma_freebuff(buff); | ||
| 297 | } | ||
| 298 | |||
| 299 | chan->curr = chan->next = chan->end = NULL; | ||
| 300 | |||
| 301 | return 0; | ||
| 302 | } | ||
| 303 | |||
| 304 | int s3c2410_dma_ctrl(enum dma_ch channel, enum s3c2410_chan_op op) | ||
| 305 | { | ||
| 306 | struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel); | ||
| 307 | |||
| 308 | WARN_ON(!chan); | ||
| 309 | if (!chan) | ||
| 310 | return -EINVAL; | ||
| 311 | |||
| 312 | switch (op) { | ||
| 313 | case S3C2410_DMAOP_START: | ||
| 314 | return s3c64xx_dma_start(chan); | ||
| 315 | |||
| 316 | case S3C2410_DMAOP_STOP: | ||
| 317 | return s3c64xx_dma_stop(chan); | ||
| 318 | |||
| 319 | case S3C2410_DMAOP_FLUSH: | ||
| 320 | return s3c64xx_dma_flush(chan); | ||
| 321 | |||
| 322 | /* believe PAUSE/RESUME are no-ops */ | ||
| 323 | case S3C2410_DMAOP_PAUSE: | ||
| 324 | case S3C2410_DMAOP_RESUME: | ||
| 325 | case S3C2410_DMAOP_STARTED: | ||
| 326 | case S3C2410_DMAOP_TIMEOUT: | ||
| 327 | return 0; | ||
| 328 | } | ||
| 329 | |||
| 330 | return -ENOENT; | ||
| 331 | } | ||
| 332 | EXPORT_SYMBOL(s3c2410_dma_ctrl); | ||
| 333 | |||
| 334 | /* s3c2410_dma_enque | ||
| 335 | * | ||
| 336 | */ | ||
| 337 | |||
| 338 | int s3c2410_dma_enqueue(enum dma_ch channel, void *id, | ||
| 339 | dma_addr_t data, int size) | ||
| 340 | { | ||
| 341 | struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel); | ||
| 342 | struct s3c64xx_dma_buff *next; | ||
| 343 | struct s3c64xx_dma_buff *buff; | ||
| 344 | struct pl080s_lli *lli; | ||
| 345 | unsigned long flags; | ||
| 346 | int ret; | ||
| 347 | |||
| 348 | WARN_ON(!chan); | ||
| 349 | if (!chan) | ||
| 350 | return -EINVAL; | ||
| 351 | |||
| 352 | buff = kzalloc(sizeof(struct s3c64xx_dma_buff), GFP_ATOMIC); | ||
| 353 | if (!buff) { | ||
| 354 | printk(KERN_ERR "%s: no memory for buffer\n", __func__); | ||
| 355 | return -ENOMEM; | ||
| 356 | } | ||
| 357 | |||
| 358 | lli = dma_pool_alloc(dma_pool, GFP_ATOMIC, &buff->lli_dma); | ||
| 359 | if (!lli) { | ||
| 360 | printk(KERN_ERR "%s: no memory for lli\n", __func__); | ||
| 361 | ret = -ENOMEM; | ||
| 362 | goto err_buff; | ||
| 363 | } | ||
| 364 | |||
| 365 | pr_debug("%s: buff %p, dp %08x lli (%p, %08x) %d\n", | ||
| 366 | __func__, buff, data, lli, (u32)buff->lli_dma, size); | ||
| 367 | |||
| 368 | buff->lli = lli; | ||
| 369 | buff->pw = id; | ||
| 370 | |||
| 371 | s3c64xx_dma_fill_lli(chan, lli, data, size); | ||
| 372 | |||
| 373 | local_irq_save(flags); | ||
| 374 | |||
| 375 | if ((next = chan->next) != NULL) { | ||
| 376 | struct s3c64xx_dma_buff *end = chan->end; | ||
| 377 | struct pl080s_lli *endlli = end->lli; | ||
| 378 | |||
| 379 | pr_debug("enquing onto channel\n"); | ||
| 380 | |||
| 381 | end->next = buff; | ||
| 382 | endlli->next_lli = buff->lli_dma; | ||
| 383 | |||
| 384 | if (chan->flags & S3C2410_DMAF_CIRCULAR) { | ||
| 385 | struct s3c64xx_dma_buff *curr = chan->curr; | ||
| 386 | lli->next_lli = curr->lli_dma; | ||
| 387 | } | ||
| 388 | |||
| 389 | if (next == chan->curr) { | ||
| 390 | writel(buff->lli_dma, chan->regs + PL080_CH_LLI); | ||
| 391 | chan->next = buff; | ||
| 392 | } | ||
| 393 | |||
| 394 | show_lli(endlli); | ||
| 395 | chan->end = buff; | ||
| 396 | } else { | ||
| 397 | pr_debug("enquing onto empty channel\n"); | ||
| 398 | |||
| 399 | chan->curr = buff; | ||
| 400 | chan->next = buff; | ||
| 401 | chan->end = buff; | ||
| 402 | |||
| 403 | s3c64xx_lli_to_regs(chan, lli); | ||
| 404 | } | ||
| 405 | |||
| 406 | local_irq_restore(flags); | ||
| 407 | |||
| 408 | show_lli(lli); | ||
| 409 | |||
| 410 | dbg_showchan(chan); | ||
| 411 | dbg_showbuffs(chan); | ||
| 412 | return 0; | ||
| 413 | |||
| 414 | err_buff: | ||
| 415 | kfree(buff); | ||
| 416 | return ret; | ||
| 417 | } | ||
| 418 | |||
| 419 | EXPORT_SYMBOL(s3c2410_dma_enqueue); | ||
| 420 | |||
| 421 | |||
| 422 | int s3c2410_dma_devconfig(enum dma_ch channel, | ||
| 423 | enum dma_data_direction source, | ||
| 424 | unsigned long devaddr) | ||
| 425 | { | ||
| 426 | struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel); | ||
| 427 | u32 peripheral; | ||
| 428 | u32 config = 0; | ||
| 429 | |||
| 430 | pr_debug("%s: channel %d, source %d, dev %08lx, chan %p\n", | ||
| 431 | __func__, channel, source, devaddr, chan); | ||
| 432 | |||
| 433 | WARN_ON(!chan); | ||
| 434 | if (!chan) | ||
| 435 | return -EINVAL; | ||
| 436 | |||
| 437 | peripheral = (chan->peripheral & 0xf); | ||
| 438 | chan->source = source; | ||
| 439 | chan->dev_addr = devaddr; | ||
| 440 | |||
| 441 | pr_debug("%s: peripheral %d\n", __func__, peripheral); | ||
| 442 | |||
| 443 | switch (source) { | ||
| 444 | case DMA_FROM_DEVICE: | ||
| 445 | config = 2 << PL080_CONFIG_FLOW_CONTROL_SHIFT; | ||
| 446 | config |= peripheral << PL080_CONFIG_SRC_SEL_SHIFT; | ||
| 447 | break; | ||
| 448 | case DMA_TO_DEVICE: | ||
| 449 | config = 1 << PL080_CONFIG_FLOW_CONTROL_SHIFT; | ||
| 450 | config |= peripheral << PL080_CONFIG_DST_SEL_SHIFT; | ||
| 451 | break; | ||
| 452 | default: | ||
| 453 | printk(KERN_ERR "%s: bad source\n", __func__); | ||
| 454 | return -EINVAL; | ||
| 455 | } | ||
| 456 | |||
| 457 | /* allow TC and ERR interrupts */ | ||
| 458 | config |= PL080_CONFIG_TC_IRQ_MASK; | ||
| 459 | config |= PL080_CONFIG_ERR_IRQ_MASK; | ||
| 460 | |||
| 461 | pr_debug("%s: config %08x\n", __func__, config); | ||
| 462 | |||
| 463 | writel(config, chan->regs + PL080S_CH_CONFIG); | ||
| 464 | |||
| 465 | return 0; | ||
| 466 | } | ||
| 467 | EXPORT_SYMBOL(s3c2410_dma_devconfig); | ||
| 468 | |||
| 469 | |||
| 470 | int s3c2410_dma_getposition(enum dma_ch channel, | ||
| 471 | dma_addr_t *src, dma_addr_t *dst) | ||
| 472 | { | ||
| 473 | struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel); | ||
| 474 | |||
| 475 | WARN_ON(!chan); | ||
| 476 | if (!chan) | ||
| 477 | return -EINVAL; | ||
| 478 | |||
| 479 | if (src != NULL) | ||
| 480 | *src = readl(chan->regs + PL080_CH_SRC_ADDR); | ||
| 481 | |||
| 482 | if (dst != NULL) | ||
| 483 | *dst = readl(chan->regs + PL080_CH_DST_ADDR); | ||
| 484 | |||
| 485 | return 0; | ||
| 486 | } | ||
| 487 | EXPORT_SYMBOL(s3c2410_dma_getposition); | ||
| 488 | |||
| 489 | /* s3c2410_request_dma | ||
| 490 | * | ||
| 491 | * get control of an dma channel | ||
| 492 | */ | ||
| 493 | |||
| 494 | int s3c2410_dma_request(enum dma_ch channel, | ||
| 495 | struct s3c2410_dma_client *client, | ||
| 496 | void *dev) | ||
| 497 | { | ||
| 498 | struct s3c2410_dma_chan *chan; | ||
| 499 | unsigned long flags; | ||
| 500 | |||
| 501 | pr_debug("dma%d: s3c2410_request_dma: client=%s, dev=%p\n", | ||
| 502 | channel, client->name, dev); | ||
| 503 | |||
| 504 | local_irq_save(flags); | ||
| 505 | |||
| 506 | chan = s3c64xx_dma_map_channel(channel); | ||
| 507 | if (chan == NULL) { | ||
| 508 | local_irq_restore(flags); | ||
| 509 | return -EBUSY; | ||
| 510 | } | ||
| 511 | |||
| 512 | dbg_showchan(chan); | ||
| 513 | |||
| 514 | chan->client = client; | ||
| 515 | chan->in_use = 1; | ||
| 516 | chan->peripheral = channel; | ||
| 517 | chan->flags = 0; | ||
| 518 | |||
| 519 | local_irq_restore(flags); | ||
| 520 | |||
| 521 | /* need to setup */ | ||
| 522 | |||
| 523 | pr_debug("%s: channel initialised, %p\n", __func__, chan); | ||
| 524 | |||
| 525 | return chan->number | DMACH_LOW_LEVEL; | ||
| 526 | } | ||
| 527 | |||
| 528 | EXPORT_SYMBOL(s3c2410_dma_request); | ||
| 529 | |||
| 530 | /* s3c2410_dma_free | ||
| 531 | * | ||
| 532 | * release the given channel back to the system, will stop and flush | ||
| 533 | * any outstanding transfers, and ensure the channel is ready for the | ||
| 534 | * next claimant. | ||
| 535 | * | ||
| 536 | * Note, although a warning is currently printed if the freeing client | ||
| 537 | * info is not the same as the registrant's client info, the free is still | ||
| 538 | * allowed to go through. | ||
| 539 | */ | ||
| 540 | |||
| 541 | int s3c2410_dma_free(enum dma_ch channel, struct s3c2410_dma_client *client) | ||
| 542 | { | ||
| 543 | struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel); | ||
| 544 | unsigned long flags; | ||
| 545 | |||
| 546 | if (chan == NULL) | ||
| 547 | return -EINVAL; | ||
| 548 | |||
| 549 | local_irq_save(flags); | ||
| 550 | |||
| 551 | if (chan->client != client) { | ||
| 552 | printk(KERN_WARNING "dma%d: possible free from different client (channel %p, passed %p)\n", | ||
| 553 | channel, chan->client, client); | ||
| 554 | } | ||
| 555 | |||
| 556 | /* sort out stopping and freeing the channel */ | ||
| 557 | |||
| 558 | |||
| 559 | chan->client = NULL; | ||
| 560 | chan->in_use = 0; | ||
| 561 | |||
| 562 | if (!(channel & DMACH_LOW_LEVEL)) | ||
| 563 | s3c_dma_chan_map[channel] = NULL; | ||
| 564 | |||
| 565 | local_irq_restore(flags); | ||
| 566 | |||
| 567 | return 0; | ||
| 568 | } | ||
| 569 | |||
| 570 | EXPORT_SYMBOL(s3c2410_dma_free); | ||
| 571 | |||
| 572 | static irqreturn_t s3c64xx_dma_irq(int irq, void *pw) | ||
| 573 | { | ||
| 574 | struct s3c64xx_dmac *dmac = pw; | ||
| 575 | struct s3c2410_dma_chan *chan; | ||
| 576 | enum s3c2410_dma_buffresult res; | ||
| 577 | u32 tcstat, errstat; | ||
| 578 | u32 bit; | ||
| 579 | int offs; | ||
| 580 | |||
| 581 | tcstat = readl(dmac->regs + PL080_TC_STATUS); | ||
| 582 | errstat = readl(dmac->regs + PL080_ERR_STATUS); | ||
| 583 | |||
| 584 | for (offs = 0, bit = 1; offs < 8; offs++, bit <<= 1) { | ||
| 585 | struct s3c64xx_dma_buff *buff; | ||
| 586 | |||
| 587 | if (!(errstat & bit) && !(tcstat & bit)) | ||
| 588 | continue; | ||
| 589 | |||
| 590 | chan = dmac->channels + offs; | ||
| 591 | res = S3C2410_RES_ERR; | ||
| 592 | |||
| 593 | if (tcstat & bit) { | ||
| 594 | writel(bit, dmac->regs + PL080_TC_CLEAR); | ||
| 595 | res = S3C2410_RES_OK; | ||
| 596 | } | ||
| 597 | |||
| 598 | if (errstat & bit) | ||
| 599 | writel(bit, dmac->regs + PL080_ERR_CLEAR); | ||
| 600 | |||
| 601 | /* 'next' points to the buffer that is next to the | ||
| 602 | * currently active buffer. | ||
| 603 | * For CIRCULAR queues, 'next' will be same as 'curr' | ||
| 604 | * when 'end' is the active buffer. | ||
| 605 | */ | ||
| 606 | buff = chan->curr; | ||
| 607 | while (buff && buff != chan->next | ||
| 608 | && buff->next != chan->next) | ||
| 609 | buff = buff->next; | ||
| 610 | |||
| 611 | if (!buff) | ||
| 612 | BUG(); | ||
| 613 | |||
| 614 | if (buff == chan->next) | ||
| 615 | buff = chan->end; | ||
| 616 | |||
| 617 | s3c64xx_dma_bufffdone(chan, buff, res); | ||
| 618 | |||
| 619 | /* Free the node and update curr, if non-circular queue */ | ||
| 620 | if (!(chan->flags & S3C2410_DMAF_CIRCULAR)) { | ||
| 621 | chan->curr = buff->next; | ||
| 622 | s3c64xx_dma_freebuff(buff); | ||
| 623 | } | ||
| 624 | |||
| 625 | /* Update 'next' */ | ||
| 626 | buff = chan->next; | ||
| 627 | if (chan->next == chan->end) { | ||
| 628 | chan->next = chan->curr; | ||
| 629 | if (!(chan->flags & S3C2410_DMAF_CIRCULAR)) | ||
| 630 | chan->end = NULL; | ||
| 631 | } else { | ||
| 632 | chan->next = buff->next; | ||
| 633 | } | ||
| 634 | } | ||
| 635 | |||
| 636 | return IRQ_HANDLED; | ||
| 637 | } | ||
| 638 | |||
| 639 | static struct bus_type dma_subsys = { | ||
| 640 | .name = "s3c64xx-dma", | ||
| 641 | .dev_name = "s3c64xx-dma", | ||
| 642 | }; | ||
| 643 | |||
| 644 | static int s3c64xx_dma_init1(int chno, enum dma_ch chbase, | ||
| 645 | int irq, unsigned int base) | ||
| 646 | { | ||
| 647 | struct s3c2410_dma_chan *chptr = &s3c2410_chans[chno]; | ||
| 648 | struct s3c64xx_dmac *dmac; | ||
| 649 | char clkname[16]; | ||
| 650 | void __iomem *regs; | ||
| 651 | void __iomem *regptr; | ||
| 652 | int err, ch; | ||
| 653 | |||
| 654 | dmac = kzalloc(sizeof(struct s3c64xx_dmac), GFP_KERNEL); | ||
| 655 | if (!dmac) { | ||
| 656 | printk(KERN_ERR "%s: failed to alloc mem\n", __func__); | ||
| 657 | return -ENOMEM; | ||
| 658 | } | ||
| 659 | |||
| 660 | dmac->dev.id = chno / 8; | ||
| 661 | dmac->dev.bus = &dma_subsys; | ||
| 662 | |||
| 663 | err = device_register(&dmac->dev); | ||
| 664 | if (err) { | ||
| 665 | printk(KERN_ERR "%s: failed to register device\n", __func__); | ||
| 666 | goto err_alloc; | ||
| 667 | } | ||
| 668 | |||
| 669 | regs = ioremap(base, 0x200); | ||
| 670 | if (!regs) { | ||
| 671 | printk(KERN_ERR "%s: failed to ioremap()\n", __func__); | ||
| 672 | err = -ENXIO; | ||
| 673 | goto err_dev; | ||
| 674 | } | ||
| 675 | |||
| 676 | snprintf(clkname, sizeof(clkname), "dma%d", dmac->dev.id); | ||
| 677 | |||
| 678 | dmac->clk = clk_get(NULL, clkname); | ||
| 679 | if (IS_ERR(dmac->clk)) { | ||
| 680 | printk(KERN_ERR "%s: failed to get clock %s\n", __func__, clkname); | ||
| 681 | err = PTR_ERR(dmac->clk); | ||
| 682 | goto err_map; | ||
| 683 | } | ||
| 684 | |||
| 685 | clk_prepare_enable(dmac->clk); | ||
| 686 | |||
| 687 | dmac->regs = regs; | ||
| 688 | dmac->chanbase = chbase; | ||
| 689 | dmac->channels = chptr; | ||
| 690 | |||
| 691 | err = request_irq(irq, s3c64xx_dma_irq, 0, "DMA", dmac); | ||
| 692 | if (err < 0) { | ||
| 693 | printk(KERN_ERR "%s: failed to get irq\n", __func__); | ||
| 694 | goto err_clk; | ||
| 695 | } | ||
| 696 | |||
| 697 | regptr = regs + PL080_Cx_BASE(0); | ||
| 698 | |||
| 699 | for (ch = 0; ch < 8; ch++, chptr++) { | ||
| 700 | pr_debug("%s: registering DMA %d (%p)\n", | ||
| 701 | __func__, chno + ch, regptr); | ||
| 702 | |||
| 703 | chptr->bit = 1 << ch; | ||
| 704 | chptr->number = chno + ch; | ||
| 705 | chptr->dmac = dmac; | ||
| 706 | chptr->regs = regptr; | ||
| 707 | regptr += PL080_Cx_STRIDE; | ||
| 708 | } | ||
| 709 | |||
| 710 | /* for the moment, permanently enable the controller */ | ||
| 711 | writel(PL080_CONFIG_ENABLE, regs + PL080_CONFIG); | ||
| 712 | |||
| 713 | printk(KERN_INFO "PL080: IRQ %d, at %p, channels %d..%d\n", | ||
| 714 | irq, regs, chno, chno+8); | ||
| 715 | |||
| 716 | return 0; | ||
| 717 | |||
| 718 | err_clk: | ||
| 719 | clk_disable_unprepare(dmac->clk); | ||
| 720 | clk_put(dmac->clk); | ||
| 721 | err_map: | ||
| 722 | iounmap(regs); | ||
| 723 | err_dev: | ||
| 724 | device_unregister(&dmac->dev); | ||
| 725 | err_alloc: | ||
| 726 | kfree(dmac); | ||
| 727 | return err; | ||
| 728 | } | ||
| 729 | |||
| 730 | static int __init s3c64xx_dma_init(void) | ||
| 731 | { | ||
| 732 | int ret; | ||
| 733 | |||
| 734 | /* This driver is not supported when booting with device tree. */ | ||
| 735 | if (of_have_populated_dt()) | ||
| 736 | return -ENODEV; | ||
| 737 | |||
| 738 | printk(KERN_INFO "%s: Registering DMA channels\n", __func__); | ||
| 739 | |||
| 740 | dma_pool = dma_pool_create("DMA-LLI", NULL, sizeof(struct pl080s_lli), 16, 0); | ||
| 741 | if (!dma_pool) { | ||
| 742 | printk(KERN_ERR "%s: failed to create pool\n", __func__); | ||
| 743 | return -ENOMEM; | ||
| 744 | } | ||
| 745 | |||
| 746 | ret = subsys_system_register(&dma_subsys, NULL); | ||
| 747 | if (ret) { | ||
| 748 | printk(KERN_ERR "%s: failed to create subsys\n", __func__); | ||
| 749 | return -ENOMEM; | ||
| 750 | } | ||
| 751 | |||
| 752 | /* Set all DMA configuration to be DMA, not SDMA */ | ||
| 753 | writel(0xffffff, S3C64XX_SDMA_SEL); | ||
| 754 | |||
| 755 | /* Register standard DMA controllers */ | ||
| 756 | s3c64xx_dma_init1(0, DMACH_UART0, IRQ_DMA0, 0x75000000); | ||
| 757 | s3c64xx_dma_init1(8, DMACH_PCM1_TX, IRQ_DMA1, 0x75100000); | ||
| 758 | |||
| 759 | return 0; | ||
| 760 | } | ||
| 761 | |||
| 762 | arch_initcall(s3c64xx_dma_init); | ||
diff --git a/arch/arm/mach-s3c64xx/include/mach/dma.h b/arch/arm/mach-s3c64xx/include/mach/dma.h index fe1a98cf0e4c..059b1fc85037 100644 --- a/arch/arm/mach-s3c64xx/include/mach/dma.h +++ b/arch/arm/mach-s3c64xx/include/mach/dma.h | |||
| @@ -11,51 +11,48 @@ | |||
| 11 | #ifndef __ASM_ARCH_DMA_H | 11 | #ifndef __ASM_ARCH_DMA_H |
| 12 | #define __ASM_ARCH_DMA_H __FILE__ | 12 | #define __ASM_ARCH_DMA_H __FILE__ |
| 13 | 13 | ||
| 14 | #define S3C_DMA_CHANNELS (16) | 14 | #define S3C64XX_DMA_CHAN(name) ((unsigned long)(name)) |
| 15 | |||
| 16 | /* DMA0/SDMA0 */ | ||
| 17 | #define DMACH_UART0 S3C64XX_DMA_CHAN("uart0_tx") | ||
| 18 | #define DMACH_UART0_SRC2 S3C64XX_DMA_CHAN("uart0_rx") | ||
| 19 | #define DMACH_UART1 S3C64XX_DMA_CHAN("uart1_tx") | ||
| 20 | #define DMACH_UART1_SRC2 S3C64XX_DMA_CHAN("uart1_rx") | ||
| 21 | #define DMACH_UART2 S3C64XX_DMA_CHAN("uart2_tx") | ||
| 22 | #define DMACH_UART2_SRC2 S3C64XX_DMA_CHAN("uart2_rx") | ||
| 23 | #define DMACH_UART3 S3C64XX_DMA_CHAN("uart3_tx") | ||
| 24 | #define DMACH_UART3_SRC2 S3C64XX_DMA_CHAN("uart3_rx") | ||
| 25 | #define DMACH_PCM0_TX S3C64XX_DMA_CHAN("pcm0_tx") | ||
| 26 | #define DMACH_PCM0_RX S3C64XX_DMA_CHAN("pcm0_rx") | ||
| 27 | #define DMACH_I2S0_OUT S3C64XX_DMA_CHAN("i2s0_tx") | ||
| 28 | #define DMACH_I2S0_IN S3C64XX_DMA_CHAN("i2s0_rx") | ||
| 29 | #define DMACH_SPI0_TX S3C64XX_DMA_CHAN("spi0_tx") | ||
| 30 | #define DMACH_SPI0_RX S3C64XX_DMA_CHAN("spi0_rx") | ||
| 31 | #define DMACH_HSI_I2SV40_TX S3C64XX_DMA_CHAN("i2s2_tx") | ||
| 32 | #define DMACH_HSI_I2SV40_RX S3C64XX_DMA_CHAN("i2s2_rx") | ||
| 33 | |||
| 34 | /* DMA1/SDMA1 */ | ||
| 35 | #define DMACH_PCM1_TX S3C64XX_DMA_CHAN("pcm1_tx") | ||
| 36 | #define DMACH_PCM1_RX S3C64XX_DMA_CHAN("pcm1_rx") | ||
| 37 | #define DMACH_I2S1_OUT S3C64XX_DMA_CHAN("i2s1_tx") | ||
| 38 | #define DMACH_I2S1_IN S3C64XX_DMA_CHAN("i2s1_rx") | ||
| 39 | #define DMACH_SPI1_TX S3C64XX_DMA_CHAN("spi1_tx") | ||
| 40 | #define DMACH_SPI1_RX S3C64XX_DMA_CHAN("spi1_rx") | ||
| 41 | #define DMACH_AC97_PCMOUT S3C64XX_DMA_CHAN("ac97_out") | ||
| 42 | #define DMACH_AC97_PCMIN S3C64XX_DMA_CHAN("ac97_in") | ||
| 43 | #define DMACH_AC97_MICIN S3C64XX_DMA_CHAN("ac97_mic") | ||
| 44 | #define DMACH_PWM S3C64XX_DMA_CHAN("pwm") | ||
| 45 | #define DMACH_IRDA S3C64XX_DMA_CHAN("irda") | ||
| 46 | #define DMACH_EXTERNAL S3C64XX_DMA_CHAN("external") | ||
| 47 | #define DMACH_SECURITY_RX S3C64XX_DMA_CHAN("sec_rx") | ||
| 48 | #define DMACH_SECURITY_TX S3C64XX_DMA_CHAN("sec_tx") | ||
| 15 | 49 | ||
| 16 | /* see mach-s3c2410/dma.h for notes on dma channel numbers */ | ||
| 17 | |||
| 18 | /* Note, for the S3C64XX architecture we keep the DMACH_ | ||
| 19 | * defines in the order they are allocated to [S]DMA0/[S]DMA1 | ||
| 20 | * so that is easy to do DHACH_ -> DMA controller conversion | ||
| 21 | */ | ||
| 22 | enum dma_ch { | 50 | enum dma_ch { |
| 23 | /* DMA0/SDMA0 */ | 51 | DMACH_MAX = 32 |
| 24 | DMACH_UART0 = 0, | 52 | }; |
| 25 | DMACH_UART0_SRC2, | ||
| 26 | DMACH_UART1, | ||
| 27 | DMACH_UART1_SRC2, | ||
| 28 | DMACH_UART2, | ||
| 29 | DMACH_UART2_SRC2, | ||
| 30 | DMACH_UART3, | ||
| 31 | DMACH_UART3_SRC2, | ||
| 32 | DMACH_PCM0_TX, | ||
| 33 | DMACH_PCM0_RX, | ||
| 34 | DMACH_I2S0_OUT, | ||
| 35 | DMACH_I2S0_IN, | ||
| 36 | DMACH_SPI0_TX, | ||
| 37 | DMACH_SPI0_RX, | ||
| 38 | DMACH_HSI_I2SV40_TX, | ||
| 39 | DMACH_HSI_I2SV40_RX, | ||
| 40 | 53 | ||
| 41 | /* DMA1/SDMA1 */ | 54 | struct s3c2410_dma_client { |
| 42 | DMACH_PCM1_TX = 16, | 55 | char *name; |
| 43 | DMACH_PCM1_RX, | ||
| 44 | DMACH_I2S1_OUT, | ||
| 45 | DMACH_I2S1_IN, | ||
| 46 | DMACH_SPI1_TX, | ||
| 47 | DMACH_SPI1_RX, | ||
| 48 | DMACH_AC97_PCMOUT, | ||
| 49 | DMACH_AC97_PCMIN, | ||
| 50 | DMACH_AC97_MICIN, | ||
| 51 | DMACH_PWM, | ||
| 52 | DMACH_IRDA, | ||
| 53 | DMACH_EXTERNAL, | ||
| 54 | DMACH_RES1, | ||
| 55 | DMACH_RES2, | ||
| 56 | DMACH_SECURITY_RX, /* SDMA1 only */ | ||
| 57 | DMACH_SECURITY_TX, /* SDMA1 only */ | ||
| 58 | DMACH_MAX /* the end */ | ||
| 59 | }; | 56 | }; |
| 60 | 57 | ||
| 61 | static inline bool samsung_dma_has_circular(void) | 58 | static inline bool samsung_dma_has_circular(void) |
| @@ -65,67 +62,10 @@ static inline bool samsung_dma_has_circular(void) | |||
| 65 | 62 | ||
| 66 | static inline bool samsung_dma_is_dmadev(void) | 63 | static inline bool samsung_dma_is_dmadev(void) |
| 67 | { | 64 | { |
| 68 | return false; | 65 | return true; |
| 69 | } | 66 | } |
| 70 | #define S3C2410_DMAF_CIRCULAR (1 << 0) | ||
| 71 | |||
| 72 | #include <plat/dma.h> | ||
| 73 | |||
| 74 | #define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */ | ||
| 75 | |||
| 76 | struct s3c64xx_dma_buff; | ||
| 77 | |||
| 78 | /** s3c64xx_dma_buff - S3C64XX DMA buffer descriptor | ||
| 79 | * @next: Pointer to next buffer in queue or ring. | ||
| 80 | * @pw: Client provided identifier | ||
| 81 | * @lli: Pointer to hardware descriptor this buffer is associated with. | ||
| 82 | * @lli_dma: Hardare address of the descriptor. | ||
| 83 | */ | ||
| 84 | struct s3c64xx_dma_buff { | ||
| 85 | struct s3c64xx_dma_buff *next; | ||
| 86 | |||
| 87 | void *pw; | ||
| 88 | struct pl080s_lli *lli; | ||
| 89 | dma_addr_t lli_dma; | ||
| 90 | }; | ||
| 91 | |||
| 92 | struct s3c64xx_dmac; | ||
| 93 | |||
| 94 | struct s3c2410_dma_chan { | ||
| 95 | unsigned char number; /* number of this dma channel */ | ||
| 96 | unsigned char in_use; /* channel allocated */ | ||
| 97 | unsigned char bit; /* bit for enable/disable/etc */ | ||
| 98 | unsigned char hw_width; | ||
| 99 | unsigned char peripheral; | ||
| 100 | |||
| 101 | unsigned int flags; | ||
| 102 | enum dma_data_direction source; | ||
| 103 | |||
| 104 | |||
| 105 | dma_addr_t dev_addr; | ||
| 106 | |||
| 107 | struct s3c2410_dma_client *client; | ||
| 108 | struct s3c64xx_dmac *dmac; /* pointer to controller */ | ||
| 109 | |||
| 110 | void __iomem *regs; | ||
| 111 | |||
| 112 | /* cdriver callbacks */ | ||
| 113 | s3c2410_dma_cbfn_t callback_fn; /* buffer done callback */ | ||
| 114 | s3c2410_dma_opfn_t op_fn; /* channel op callback */ | ||
| 115 | |||
| 116 | /* buffer list and information */ | ||
| 117 | struct s3c64xx_dma_buff *curr; /* current dma buffer */ | ||
| 118 | struct s3c64xx_dma_buff *next; /* next buffer to load */ | ||
| 119 | struct s3c64xx_dma_buff *end; /* end of queue */ | ||
| 120 | |||
| 121 | /* note, when channel is running in circular mode, curr is the | ||
| 122 | * first buffer enqueued, end is the last and curr is where the | ||
| 123 | * last buffer-done event is set-at. The buffers are not freed | ||
| 124 | * and the last buffer hardware descriptor points back to the | ||
| 125 | * first. | ||
| 126 | */ | ||
| 127 | }; | ||
| 128 | 67 | ||
| 129 | #include <plat/dma-core.h> | 68 | #include <linux/amba/pl08x.h> |
| 69 | #include <plat/dma-ops.h> | ||
| 130 | 70 | ||
| 131 | #endif /* __ASM_ARCH_IRQ_H */ | 71 | #endif /* __ASM_ARCH_IRQ_H */ |
diff --git a/arch/arm/mach-s3c64xx/pl080.c b/arch/arm/mach-s3c64xx/pl080.c new file mode 100644 index 000000000000..901a984bddc2 --- /dev/null +++ b/arch/arm/mach-s3c64xx/pl080.c | |||
| @@ -0,0 +1,244 @@ | |||
| 1 | /* | ||
| 2 | * Samsung's S3C64XX generic DMA support using amba-pl08x driver. | ||
| 3 | * | ||
| 4 | * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/kernel.h> | ||
| 12 | #include <linux/amba/bus.h> | ||
| 13 | #include <linux/amba/pl080.h> | ||
| 14 | #include <linux/amba/pl08x.h> | ||
| 15 | #include <linux/of.h> | ||
| 16 | |||
| 17 | #include <mach/irqs.h> | ||
| 18 | #include <mach/map.h> | ||
| 19 | |||
| 20 | #include "regs-sys.h" | ||
| 21 | |||
| 22 | static int pl08x_get_xfer_signal(const struct pl08x_channel_data *cd) | ||
| 23 | { | ||
| 24 | return cd->min_signal; | ||
| 25 | } | ||
| 26 | |||
| 27 | static void pl08x_put_xfer_signal(const struct pl08x_channel_data *cd, int ch) | ||
| 28 | { | ||
| 29 | } | ||
| 30 | |||
| 31 | /* | ||
| 32 | * DMA0 | ||
| 33 | */ | ||
| 34 | |||
| 35 | static struct pl08x_channel_data s3c64xx_dma0_info[] = { | ||
| 36 | { | ||
| 37 | .bus_id = "uart0_tx", | ||
| 38 | .min_signal = 0, | ||
| 39 | .max_signal = 0, | ||
| 40 | .periph_buses = PL08X_AHB2, | ||
| 41 | }, { | ||
| 42 | .bus_id = "uart0_rx", | ||
| 43 | .min_signal = 1, | ||
| 44 | .max_signal = 1, | ||
| 45 | .periph_buses = PL08X_AHB2, | ||
| 46 | }, { | ||
| 47 | .bus_id = "uart1_tx", | ||
| 48 | .min_signal = 2, | ||
| 49 | .max_signal = 2, | ||
| 50 | .periph_buses = PL08X_AHB2, | ||
| 51 | }, { | ||
| 52 | .bus_id = "uart1_rx", | ||
| 53 | .min_signal = 3, | ||
| 54 | .max_signal = 3, | ||
| 55 | .periph_buses = PL08X_AHB2, | ||
| 56 | }, { | ||
| 57 | .bus_id = "uart2_tx", | ||
| 58 | .min_signal = 4, | ||
| 59 | .max_signal = 4, | ||
| 60 | .periph_buses = PL08X_AHB2, | ||
| 61 | }, { | ||
| 62 | .bus_id = "uart2_rx", | ||
| 63 | .min_signal = 5, | ||
| 64 | .max_signal = 5, | ||
| 65 | .periph_buses = PL08X_AHB2, | ||
| 66 | }, { | ||
| 67 | .bus_id = "uart3_tx", | ||
| 68 | .min_signal = 6, | ||
| 69 | .max_signal = 6, | ||
| 70 | .periph_buses = PL08X_AHB2, | ||
| 71 | }, { | ||
| 72 | .bus_id = "uart3_rx", | ||
| 73 | .min_signal = 7, | ||
| 74 | .max_signal = 7, | ||
| 75 | .periph_buses = PL08X_AHB2, | ||
| 76 | }, { | ||
| 77 | .bus_id = "pcm0_tx", | ||
| 78 | .min_signal = 8, | ||
| 79 | .max_signal = 8, | ||
| 80 | .periph_buses = PL08X_AHB2, | ||
| 81 | }, { | ||
| 82 | .bus_id = "pcm0_rx", | ||
| 83 | .min_signal = 9, | ||
| 84 | .max_signal = 9, | ||
| 85 | .periph_buses = PL08X_AHB2, | ||
| 86 | }, { | ||
| 87 | .bus_id = "i2s0_tx", | ||
| 88 | .min_signal = 10, | ||
| 89 | .max_signal = 10, | ||
| 90 | .periph_buses = PL08X_AHB2, | ||
| 91 | }, { | ||
| 92 | .bus_id = "i2s0_rx", | ||
| 93 | .min_signal = 11, | ||
| 94 | .max_signal = 11, | ||
| 95 | .periph_buses = PL08X_AHB2, | ||
| 96 | }, { | ||
| 97 | .bus_id = "spi0_tx", | ||
| 98 | .min_signal = 12, | ||
| 99 | .max_signal = 12, | ||
| 100 | .periph_buses = PL08X_AHB2, | ||
| 101 | }, { | ||
| 102 | .bus_id = "spi0_rx", | ||
| 103 | .min_signal = 13, | ||
| 104 | .max_signal = 13, | ||
| 105 | .periph_buses = PL08X_AHB2, | ||
| 106 | }, { | ||
| 107 | .bus_id = "i2s2_tx", | ||
| 108 | .min_signal = 14, | ||
| 109 | .max_signal = 14, | ||
| 110 | .periph_buses = PL08X_AHB2, | ||
| 111 | }, { | ||
| 112 | .bus_id = "i2s2_rx", | ||
| 113 | .min_signal = 15, | ||
| 114 | .max_signal = 15, | ||
| 115 | .periph_buses = PL08X_AHB2, | ||
| 116 | } | ||
| 117 | }; | ||
| 118 | |||
| 119 | struct pl08x_platform_data s3c64xx_dma0_plat_data = { | ||
| 120 | .memcpy_channel = { | ||
| 121 | .bus_id = "memcpy", | ||
| 122 | .cctl_memcpy = | ||
| 123 | (PL080_BSIZE_4 << PL080_CONTROL_SB_SIZE_SHIFT | | ||
| 124 | PL080_BSIZE_4 << PL080_CONTROL_DB_SIZE_SHIFT | | ||
| 125 | PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | | ||
| 126 | PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | | ||
| 127 | PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | | ||
| 128 | PL080_CONTROL_PROT_SYS), | ||
| 129 | }, | ||
| 130 | .lli_buses = PL08X_AHB1, | ||
| 131 | .mem_buses = PL08X_AHB1, | ||
| 132 | .get_xfer_signal = pl08x_get_xfer_signal, | ||
| 133 | .put_xfer_signal = pl08x_put_xfer_signal, | ||
| 134 | .slave_channels = s3c64xx_dma0_info, | ||
| 135 | .num_slave_channels = ARRAY_SIZE(s3c64xx_dma0_info), | ||
| 136 | }; | ||
| 137 | |||
| 138 | static AMBA_AHB_DEVICE(s3c64xx_dma0, "dma-pl080s.0", 0, | ||
| 139 | 0x75000000, {IRQ_DMA0}, &s3c64xx_dma0_plat_data); | ||
| 140 | |||
| 141 | /* | ||
| 142 | * DMA1 | ||
| 143 | */ | ||
| 144 | |||
| 145 | static struct pl08x_channel_data s3c64xx_dma1_info[] = { | ||
| 146 | { | ||
| 147 | .bus_id = "pcm1_tx", | ||
| 148 | .min_signal = 0, | ||
| 149 | .max_signal = 0, | ||
| 150 | .periph_buses = PL08X_AHB2, | ||
| 151 | }, { | ||
| 152 | .bus_id = "pcm1_rx", | ||
| 153 | .min_signal = 1, | ||
| 154 | .max_signal = 1, | ||
| 155 | .periph_buses = PL08X_AHB2, | ||
| 156 | }, { | ||
| 157 | .bus_id = "i2s1_tx", | ||
| 158 | .min_signal = 2, | ||
| 159 | .max_signal = 2, | ||
| 160 | .periph_buses = PL08X_AHB2, | ||
| 161 | }, { | ||
| 162 | .bus_id = "i2s1_rx", | ||
| 163 | .min_signal = 3, | ||
| 164 | .max_signal = 3, | ||
| 165 | .periph_buses = PL08X_AHB2, | ||
| 166 | }, { | ||
| 167 | .bus_id = "spi1_tx", | ||
| 168 | .min_signal = 4, | ||
| 169 | .max_signal = 4, | ||
| 170 | .periph_buses = PL08X_AHB2, | ||
| 171 | }, { | ||
| 172 | .bus_id = "spi1_rx", | ||
| 173 | .min_signal = 5, | ||
| 174 | .max_signal = 5, | ||
| 175 | .periph_buses = PL08X_AHB2, | ||
| 176 | }, { | ||
| 177 | .bus_id = "ac97_out", | ||
| 178 | .min_signal = 6, | ||
| 179 | .max_signal = 6, | ||
| 180 | .periph_buses = PL08X_AHB2, | ||
| 181 | }, { | ||
| 182 | .bus_id = "ac97_in", | ||
| 183 | .min_signal = 7, | ||
| 184 | .max_signal = 7, | ||
| 185 | .periph_buses = PL08X_AHB2, | ||
| 186 | }, { | ||
| 187 | .bus_id = "ac97_mic", | ||
| 188 | .min_signal = 8, | ||
| 189 | .max_signal = 8, | ||
| 190 | .periph_buses = PL08X_AHB2, | ||
| 191 | }, { | ||
| 192 | .bus_id = "pwm", | ||
| 193 | .min_signal = 9, | ||
| 194 | .max_signal = 9, | ||
| 195 | .periph_buses = PL08X_AHB2, | ||
| 196 | }, { | ||
| 197 | .bus_id = "irda", | ||
| 198 | .min_signal = 10, | ||
| 199 | .max_signal = 10, | ||
| 200 | .periph_buses = PL08X_AHB2, | ||
| 201 | }, { | ||
| 202 | .bus_id = "external", | ||
| 203 | .min_signal = 11, | ||
| 204 | .max_signal = 11, | ||
| 205 | .periph_buses = PL08X_AHB2, | ||
| 206 | }, | ||
| 207 | }; | ||
| 208 | |||
| 209 | struct pl08x_platform_data s3c64xx_dma1_plat_data = { | ||
| 210 | .memcpy_channel = { | ||
| 211 | .bus_id = "memcpy", | ||
| 212 | .cctl_memcpy = | ||
| 213 | (PL080_BSIZE_4 << PL080_CONTROL_SB_SIZE_SHIFT | | ||
| 214 | PL080_BSIZE_4 << PL080_CONTROL_DB_SIZE_SHIFT | | ||
| 215 | PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | | ||
| 216 | PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | | ||
| 217 | PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | | ||
| 218 | PL080_CONTROL_PROT_SYS), | ||
| 219 | }, | ||
| 220 | .lli_buses = PL08X_AHB1, | ||
| 221 | .mem_buses = PL08X_AHB1, | ||
| 222 | .get_xfer_signal = pl08x_get_xfer_signal, | ||
| 223 | .put_xfer_signal = pl08x_put_xfer_signal, | ||
| 224 | .slave_channels = s3c64xx_dma1_info, | ||
| 225 | .num_slave_channels = ARRAY_SIZE(s3c64xx_dma1_info), | ||
| 226 | }; | ||
| 227 | |||
| 228 | static AMBA_AHB_DEVICE(s3c64xx_dma1, "dma-pl080s.1", 0, | ||
| 229 | 0x75100000, {IRQ_DMA1}, &s3c64xx_dma1_plat_data); | ||
| 230 | |||
| 231 | static int __init s3c64xx_pl080_init(void) | ||
| 232 | { | ||
| 233 | /* Set all DMA configuration to be DMA, not SDMA */ | ||
| 234 | writel(0xffffff, S3C64XX_SDMA_SEL); | ||
| 235 | |||
| 236 | if (of_have_populated_dt()) | ||
| 237 | return 0; | ||
| 238 | |||
| 239 | amba_device_register(&s3c64xx_dma0_device, &iomem_resource); | ||
| 240 | amba_device_register(&s3c64xx_dma1_device, &iomem_resource); | ||
| 241 | |||
| 242 | return 0; | ||
| 243 | } | ||
| 244 | arch_initcall(s3c64xx_pl080_init); | ||
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index a4a4b75109b2..8c8889211f6d 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig | |||
| @@ -1,6 +1,10 @@ | |||
| 1 | config ARCH_SHMOBILE | ||
| 2 | bool | ||
| 3 | |||
| 1 | config ARCH_SHMOBILE_MULTI | 4 | config ARCH_SHMOBILE_MULTI |
| 2 | bool "SH-Mobile Series" if ARCH_MULTI_V7 | 5 | bool "SH-Mobile Series" if ARCH_MULTI_V7 |
| 3 | depends on MMU | 6 | depends on MMU |
| 7 | select ARCH_SHMOBILE | ||
| 4 | select CPU_V7 | 8 | select CPU_V7 |
| 5 | select GENERIC_CLOCKEVENTS | 9 | select GENERIC_CLOCKEVENTS |
| 6 | select HAVE_ARM_SCU if SMP | 10 | select HAVE_ARM_SCU if SMP |
| @@ -8,6 +12,7 @@ config ARCH_SHMOBILE_MULTI | |||
| 8 | select HAVE_SMP | 12 | select HAVE_SMP |
| 9 | select ARM_GIC | 13 | select ARM_GIC |
| 10 | select MIGHT_HAVE_CACHE_L2X0 | 14 | select MIGHT_HAVE_CACHE_L2X0 |
| 15 | select MIGHT_HAVE_PCI | ||
| 11 | select NO_IOPORT | 16 | select NO_IOPORT |
| 12 | select PINCTRL | 17 | select PINCTRL |
| 13 | select ARCH_REQUIRE_GPIOLIB | 18 | select ARCH_REQUIRE_GPIOLIB |
| @@ -30,7 +35,7 @@ config MACH_KZM9D | |||
| 30 | comment "SH-Mobile System Configuration" | 35 | comment "SH-Mobile System Configuration" |
| 31 | endif | 36 | endif |
| 32 | 37 | ||
| 33 | if ARCH_SHMOBILE | 38 | if ARCH_SHMOBILE_LEGACY |
| 34 | 39 | ||
| 35 | comment "SH-Mobile System Type" | 40 | comment "SH-Mobile System Type" |
| 36 | 41 | ||
| @@ -92,23 +97,31 @@ config ARCH_R8A7790 | |||
| 92 | select ARCH_WANT_OPTIONAL_GPIOLIB | 97 | select ARCH_WANT_OPTIONAL_GPIOLIB |
| 93 | select ARM_GIC | 98 | select ARM_GIC |
| 94 | select CPU_V7 | 99 | select CPU_V7 |
| 100 | select MIGHT_HAVE_PCI | ||
| 95 | select SH_CLK_CPG | 101 | select SH_CLK_CPG |
| 96 | select RENESAS_IRQC | 102 | select RENESAS_IRQC |
| 97 | 103 | ||
| 98 | config ARCH_R8A7791 | 104 | config ARCH_R8A7791 |
| 99 | bool "R-Car M2 (R8A77910)" | 105 | bool "R-Car M2 (R8A77910)" |
| 106 | select ARCH_WANT_OPTIONAL_GPIOLIB | ||
| 100 | select ARM_GIC | 107 | select ARM_GIC |
| 101 | select CPU_V7 | 108 | select CPU_V7 |
| 109 | select MIGHT_HAVE_PCI | ||
| 102 | select SH_CLK_CPG | 110 | select SH_CLK_CPG |
| 111 | select RENESAS_IRQC | ||
| 103 | 112 | ||
| 104 | config ARCH_EMEV2 | 113 | config ARCH_EMEV2 |
| 105 | bool "Emma Mobile EV2" | 114 | bool "Emma Mobile EV2" |
| 106 | select ARCH_WANT_OPTIONAL_GPIOLIB | 115 | select ARCH_WANT_OPTIONAL_GPIOLIB |
| 107 | select ARM_GIC | 116 | select ARM_GIC |
| 108 | select CPU_V7 | 117 | select CPU_V7 |
| 118 | select MIGHT_HAVE_PCI | ||
| 119 | select USE_OF | ||
| 120 | select AUTO_ZRELADDR | ||
| 109 | 121 | ||
| 110 | config ARCH_R7S72100 | 122 | config ARCH_R7S72100 |
| 111 | bool "RZ/A1H (R7S72100)" | 123 | bool "RZ/A1H (R7S72100)" |
| 124 | select ARCH_WANT_OPTIONAL_GPIOLIB | ||
| 112 | select ARM_GIC | 125 | select ARM_GIC |
| 113 | select CPU_V7 | 126 | select CPU_V7 |
| 114 | select SH_CLK_CPG | 127 | select SH_CLK_CPG |
| @@ -230,12 +243,7 @@ config MACH_KOELSCH | |||
| 230 | bool "Koelsch board" | 243 | bool "Koelsch board" |
| 231 | depends on ARCH_R8A7791 | 244 | depends on ARCH_R8A7791 |
| 232 | select USE_OF | 245 | select USE_OF |
| 233 | 246 | select MICREL_PHY if SH_ETH | |
| 234 | config MACH_KZM9D | ||
| 235 | bool "KZM9D board" | ||
| 236 | depends on ARCH_EMEV2 | ||
| 237 | select REGULATOR_FIXED_VOLTAGE if REGULATOR | ||
| 238 | select USE_OF | ||
| 239 | 247 | ||
| 240 | config MACH_KZM9G | 248 | config MACH_KZM9G |
| 241 | bool "KZM-A9-GT board" | 249 | bool "KZM-A9-GT board" |
| @@ -274,7 +282,7 @@ source "drivers/sh/Kconfig" | |||
| 274 | 282 | ||
| 275 | endif | 283 | endif |
| 276 | 284 | ||
| 277 | if ARCH_SHMOBILE || ARCH_SHMOBILE_MULTI | 285 | if ARCH_SHMOBILE |
| 278 | 286 | ||
| 279 | menu "Timer and clock configuration" | 287 | menu "Timer and clock configuration" |
| 280 | 288 | ||
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index 51db2bcafabf..c7e877499dc2 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile | |||
| @@ -71,7 +71,6 @@ obj-$(CONFIG_MACH_LAGER_REFERENCE) += board-lager-reference.o | |||
| 71 | obj-$(CONFIG_MACH_ARMADILLO800EVA) += board-armadillo800eva.o | 71 | obj-$(CONFIG_MACH_ARMADILLO800EVA) += board-armadillo800eva.o |
| 72 | obj-$(CONFIG_MACH_ARMADILLO800EVA_REFERENCE) += board-armadillo800eva-reference.o | 72 | obj-$(CONFIG_MACH_ARMADILLO800EVA_REFERENCE) += board-armadillo800eva-reference.o |
| 73 | obj-$(CONFIG_MACH_KOELSCH) += board-koelsch.o | 73 | obj-$(CONFIG_MACH_KOELSCH) += board-koelsch.o |
| 74 | obj-$(CONFIG_MACH_KZM9D) += board-kzm9d.o | ||
| 75 | obj-$(CONFIG_MACH_KZM9G) += board-kzm9g.o | 74 | obj-$(CONFIG_MACH_KZM9G) += board-kzm9g.o |
| 76 | obj-$(CONFIG_MACH_KZM9G_REFERENCE) += board-kzm9g-reference.o | 75 | obj-$(CONFIG_MACH_KZM9G_REFERENCE) += board-kzm9g-reference.o |
| 77 | endif | 76 | endif |
diff --git a/arch/arm/mach-shmobile/Makefile.boot b/arch/arm/mach-shmobile/Makefile.boot index 391d72a5536c..4f30e3dc0919 100644 --- a/arch/arm/mach-shmobile/Makefile.boot +++ b/arch/arm/mach-shmobile/Makefile.boot | |||
| @@ -8,7 +8,6 @@ loadaddr-$(CONFIG_MACH_BOCKW) += 0x60008000 | |||
| 8 | loadaddr-$(CONFIG_MACH_BOCKW_REFERENCE) += 0x60008000 | 8 | loadaddr-$(CONFIG_MACH_BOCKW_REFERENCE) += 0x60008000 |
| 9 | loadaddr-$(CONFIG_MACH_GENMAI) += 0x8008000 | 9 | loadaddr-$(CONFIG_MACH_GENMAI) += 0x8008000 |
| 10 | loadaddr-$(CONFIG_MACH_KOELSCH) += 0x40008000 | 10 | loadaddr-$(CONFIG_MACH_KOELSCH) += 0x40008000 |
| 11 | loadaddr-$(CONFIG_MACH_KZM9D) += 0x40008000 | ||
| 12 | loadaddr-$(CONFIG_MACH_KZM9G) += 0x41008000 | 11 | loadaddr-$(CONFIG_MACH_KZM9G) += 0x41008000 |
| 13 | loadaddr-$(CONFIG_MACH_KZM9G_REFERENCE) += 0x41008000 | 12 | loadaddr-$(CONFIG_MACH_KZM9G_REFERENCE) += 0x41008000 |
| 14 | loadaddr-$(CONFIG_MACH_LAGER) += 0x40008000 | 13 | loadaddr-$(CONFIG_MACH_LAGER) += 0x40008000 |
diff --git a/arch/arm/mach-shmobile/board-bockw.c b/arch/arm/mach-shmobile/board-bockw.c index 38611526fe9a..44b55ef8857e 100644 --- a/arch/arm/mach-shmobile/board-bockw.c +++ b/arch/arm/mach-shmobile/board-bockw.c | |||
| @@ -25,6 +25,7 @@ | |||
| 25 | #include <linux/mmc/sh_mmcif.h> | 25 | #include <linux/mmc/sh_mmcif.h> |
| 26 | #include <linux/mtd/partitions.h> | 26 | #include <linux/mtd/partitions.h> |
| 27 | #include <linux/pinctrl/machine.h> | 27 | #include <linux/pinctrl/machine.h> |
| 28 | #include <linux/platform_data/camera-rcar.h> | ||
| 28 | #include <linux/platform_data/usb-rcar-phy.h> | 29 | #include <linux/platform_data/usb-rcar-phy.h> |
| 29 | #include <linux/platform_device.h> | 30 | #include <linux/platform_device.h> |
| 30 | #include <linux/regulator/fixed.h> | 31 | #include <linux/regulator/fixed.h> |
diff --git a/arch/arm/mach-shmobile/board-kzm9d.c b/arch/arm/mach-shmobile/board-kzm9d.c deleted file mode 100644 index 30c2cc695b12..000000000000 --- a/arch/arm/mach-shmobile/board-kzm9d.c +++ /dev/null | |||
| @@ -1,92 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * kzm9d board support | ||
| 3 | * | ||
| 4 | * Copyright (C) 2012 Renesas Solutions Corp. | ||
| 5 | * Copyright (C) 2012 Magnus Damm | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; version 2 of the License. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 19 | */ | ||
| 20 | |||
| 21 | #include <linux/kernel.h> | ||
| 22 | #include <linux/interrupt.h> | ||
| 23 | #include <linux/platform_device.h> | ||
| 24 | #include <linux/regulator/fixed.h> | ||
| 25 | #include <linux/regulator/machine.h> | ||
| 26 | #include <linux/smsc911x.h> | ||
| 27 | #include <mach/common.h> | ||
| 28 | #include <mach/emev2.h> | ||
| 29 | #include <asm/mach-types.h> | ||
| 30 | #include <asm/mach/arch.h> | ||
| 31 | |||
| 32 | /* Dummy supplies, where voltage doesn't matter */ | ||
| 33 | static struct regulator_consumer_supply dummy_supplies[] = { | ||
| 34 | REGULATOR_SUPPLY("vddvario", "smsc911x"), | ||
| 35 | REGULATOR_SUPPLY("vdd33a", "smsc911x"), | ||
| 36 | }; | ||
| 37 | |||
| 38 | /* Ether */ | ||
| 39 | static struct resource smsc911x_resources[] = { | ||
| 40 | [0] = { | ||
| 41 | .start = 0x20000000, | ||
| 42 | .end = 0x2000ffff, | ||
| 43 | .flags = IORESOURCE_MEM, | ||
| 44 | }, | ||
| 45 | [1] = { | ||
| 46 | .start = EMEV2_GPIO_IRQ(1), | ||
| 47 | .flags = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH, | ||
| 48 | }, | ||
| 49 | }; | ||
| 50 | |||
| 51 | static struct smsc911x_platform_config smsc911x_platdata = { | ||
| 52 | .flags = SMSC911X_USE_32BIT, | ||
| 53 | .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, | ||
| 54 | .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH, | ||
| 55 | }; | ||
| 56 | |||
| 57 | static struct platform_device smsc91x_device = { | ||
| 58 | .name = "smsc911x", | ||
| 59 | .id = -1, | ||
| 60 | .dev = { | ||
| 61 | .platform_data = &smsc911x_platdata, | ||
| 62 | }, | ||
| 63 | .num_resources = ARRAY_SIZE(smsc911x_resources), | ||
| 64 | .resource = smsc911x_resources, | ||
| 65 | }; | ||
| 66 | |||
| 67 | static struct platform_device *kzm9d_devices[] __initdata = { | ||
| 68 | &smsc91x_device, | ||
| 69 | }; | ||
| 70 | |||
| 71 | void __init kzm9d_add_standard_devices(void) | ||
| 72 | { | ||
| 73 | regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); | ||
| 74 | |||
| 75 | emev2_add_standard_devices(); | ||
| 76 | |||
| 77 | platform_add_devices(kzm9d_devices, ARRAY_SIZE(kzm9d_devices)); | ||
| 78 | } | ||
| 79 | |||
| 80 | static const char *kzm9d_boards_compat_dt[] __initdata = { | ||
| 81 | "renesas,kzm9d", | ||
| 82 | NULL, | ||
| 83 | }; | ||
| 84 | |||
| 85 | DT_MACHINE_START(KZM9D_DT, "kzm9d") | ||
| 86 | .smp = smp_ops(emev2_smp_ops), | ||
| 87 | .map_io = emev2_map_io, | ||
| 88 | .init_early = emev2_init_delay, | ||
| 89 | .init_machine = kzm9d_add_standard_devices, | ||
| 90 | .init_late = shmobile_init_late, | ||
| 91 | .dt_compat = kzm9d_boards_compat_dt, | ||
| 92 | MACHINE_END | ||
diff --git a/arch/arm/mach-shmobile/clock-r7s72100.c b/arch/arm/mach-shmobile/clock-r7s72100.c index 4aba20ca127e..850a8a371b43 100644 --- a/arch/arm/mach-shmobile/clock-r7s72100.c +++ b/arch/arm/mach-shmobile/clock-r7s72100.c | |||
| @@ -27,6 +27,7 @@ | |||
| 27 | #define FRQCR2 0xfcfe0014 | 27 | #define FRQCR2 0xfcfe0014 |
| 28 | #define STBCR3 0xfcfe0420 | 28 | #define STBCR3 0xfcfe0420 |
| 29 | #define STBCR4 0xfcfe0424 | 29 | #define STBCR4 0xfcfe0424 |
| 30 | #define STBCR9 0xfcfe0438 | ||
| 30 | 31 | ||
| 31 | #define PLL_RATE 30 | 32 | #define PLL_RATE 30 |
| 32 | 33 | ||
| @@ -144,10 +145,15 @@ struct clk div4_clks[DIV4_NR] = { | |||
| 144 | | CLK_ENABLE_ON_INIT), | 145 | | CLK_ENABLE_ON_INIT), |
| 145 | }; | 146 | }; |
| 146 | 147 | ||
| 147 | enum { MSTP47, MSTP46, MSTP45, MSTP44, MSTP43, MSTP42, MSTP41, MSTP40, | 148 | enum { MSTP97, MSTP96, MSTP95, MSTP94, |
| 149 | MSTP47, MSTP46, MSTP45, MSTP44, MSTP43, MSTP42, MSTP41, MSTP40, | ||
| 148 | MSTP33, MSTP_NR }; | 150 | MSTP33, MSTP_NR }; |
| 149 | 151 | ||
| 150 | static struct clk mstp_clks[MSTP_NR] = { | 152 | static struct clk mstp_clks[MSTP_NR] = { |
| 153 | [MSTP97] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 7, 0), /* RIIC0 */ | ||
| 154 | [MSTP96] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 6, 0), /* RIIC1 */ | ||
| 155 | [MSTP95] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 5, 0), /* RIIC2 */ | ||
| 156 | [MSTP94] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 4, 0), /* RIIC3 */ | ||
| 151 | [MSTP47] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 7, 0), /* SCIF0 */ | 157 | [MSTP47] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 7, 0), /* SCIF0 */ |
| 152 | [MSTP46] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 6, 0), /* SCIF1 */ | 158 | [MSTP46] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 6, 0), /* SCIF1 */ |
| 153 | [MSTP45] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 5, 0), /* SCIF2 */ | 159 | [MSTP45] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 5, 0), /* SCIF2 */ |
diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c index c826bca4024e..e9a3c6401845 100644 --- a/arch/arm/mach-shmobile/clock-r8a7740.c +++ b/arch/arm/mach-shmobile/clock-r8a7740.c | |||
| @@ -585,6 +585,7 @@ static struct clk_lookup lookups[] = { | |||
| 585 | 585 | ||
| 586 | CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), | 586 | CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), |
| 587 | CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), | 587 | CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), |
| 588 | CLKDEV_DEV_ID("fe1f0000.sound", &mstp_clks[MSTP328]), | ||
| 588 | CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), | 589 | CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), |
| 589 | CLKDEV_DEV_ID("e6c20000.i2c", &mstp_clks[MSTP323]), | 590 | CLKDEV_DEV_ID("e6c20000.i2c", &mstp_clks[MSTP323]), |
| 590 | CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP320]), | 591 | CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP320]), |
diff --git a/arch/arm/mach-shmobile/clock-r8a7778.c b/arch/arm/mach-shmobile/clock-r8a7778.c index fb6af83858e3..dfb0fff4d24c 100644 --- a/arch/arm/mach-shmobile/clock-r8a7778.c +++ b/arch/arm/mach-shmobile/clock-r8a7778.c | |||
| @@ -115,6 +115,8 @@ static struct clk *main_clks[] = { | |||
| 115 | }; | 115 | }; |
| 116 | 116 | ||
| 117 | enum { | 117 | enum { |
| 118 | MSTP531, MSTP530, | ||
| 119 | MSTP529, MSTP528, MSTP527, MSTP526, MSTP525, MSTP524, MSTP523, | ||
| 118 | MSTP331, | 120 | MSTP331, |
| 119 | MSTP323, MSTP322, MSTP321, | 121 | MSTP323, MSTP322, MSTP321, |
| 120 | MSTP311, MSTP310, | 122 | MSTP311, MSTP310, |
| @@ -129,6 +131,15 @@ enum { | |||
| 129 | MSTP_NR }; | 131 | MSTP_NR }; |
| 130 | 132 | ||
| 131 | static struct clk mstp_clks[MSTP_NR] = { | 133 | static struct clk mstp_clks[MSTP_NR] = { |
| 134 | [MSTP531] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 31, 0), /* SCU0 */ | ||
| 135 | [MSTP530] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 30, 0), /* SCU1 */ | ||
| 136 | [MSTP529] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 29, 0), /* SCU2 */ | ||
| 137 | [MSTP528] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 28, 0), /* SCU3 */ | ||
| 138 | [MSTP527] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 27, 0), /* SCU4 */ | ||
| 139 | [MSTP526] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 26, 0), /* SCU5 */ | ||
| 140 | [MSTP525] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 25, 0), /* SCU6 */ | ||
| 141 | [MSTP524] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 24, 0), /* SCU7 */ | ||
| 142 | [MSTP523] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 23, 0), /* SCU8 */ | ||
| 132 | [MSTP331] = SH_CLK_MSTP32(&s4_clk, MSTPCR3, 31, 0), /* MMC */ | 143 | [MSTP331] = SH_CLK_MSTP32(&s4_clk, MSTPCR3, 31, 0), /* MMC */ |
| 133 | [MSTP323] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 23, 0), /* SDHI0 */ | 144 | [MSTP323] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 23, 0), /* SDHI0 */ |
| 134 | [MSTP322] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 22, 0), /* SDHI1 */ | 145 | [MSTP322] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 22, 0), /* SDHI1 */ |
| @@ -173,9 +184,13 @@ static struct clk_lookup lookups[] = { | |||
| 173 | 184 | ||
| 174 | /* MSTP32 clocks */ | 185 | /* MSTP32 clocks */ |
| 175 | CLKDEV_DEV_ID("sh_mmcif", &mstp_clks[MSTP331]), /* MMC */ | 186 | CLKDEV_DEV_ID("sh_mmcif", &mstp_clks[MSTP331]), /* MMC */ |
| 187 | CLKDEV_DEV_ID("ffe4e000.mmcif", &mstp_clks[MSTP331]), /* MMC */ | ||
| 176 | CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */ | 188 | CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */ |
| 189 | CLKDEV_DEV_ID("ffe4c000.sdhi", &mstp_clks[MSTP323]), /* SDHI0 */ | ||
| 177 | CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */ | 190 | CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */ |
| 191 | CLKDEV_DEV_ID("ffe4d000.sdhi", &mstp_clks[MSTP322]), /* SDHI1 */ | ||
| 178 | CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */ | 192 | CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */ |
| 193 | CLKDEV_DEV_ID("ffe4f000.sdhi", &mstp_clks[MSTP321]), /* SDHI2 */ | ||
| 179 | CLKDEV_DEV_ID("r8a777x-ether", &mstp_clks[MSTP114]), /* Ether */ | 194 | CLKDEV_DEV_ID("r8a777x-ether", &mstp_clks[MSTP114]), /* Ether */ |
| 180 | CLKDEV_DEV_ID("r8a7778-vin.0", &mstp_clks[MSTP110]), /* VIN0 */ | 195 | CLKDEV_DEV_ID("r8a7778-vin.0", &mstp_clks[MSTP110]), /* VIN0 */ |
| 181 | CLKDEV_DEV_ID("r8a7778-vin.1", &mstp_clks[MSTP109]), /* VIN1 */ | 196 | CLKDEV_DEV_ID("r8a7778-vin.1", &mstp_clks[MSTP109]), /* VIN1 */ |
| @@ -183,9 +198,13 @@ static struct clk_lookup lookups[] = { | |||
| 183 | CLKDEV_DEV_ID("ohci-platform", &mstp_clks[MSTP100]), /* USB OHCI port0/1 */ | 198 | CLKDEV_DEV_ID("ohci-platform", &mstp_clks[MSTP100]), /* USB OHCI port0/1 */ |
| 184 | CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP100]), /* USB FUNC */ | 199 | CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP100]), /* USB FUNC */ |
| 185 | CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP030]), /* I2C0 */ | 200 | CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP030]), /* I2C0 */ |
| 201 | CLKDEV_DEV_ID("ffc70000.i2c", &mstp_clks[MSTP030]), /* I2C0 */ | ||
| 186 | CLKDEV_DEV_ID("i2c-rcar.1", &mstp_clks[MSTP029]), /* I2C1 */ | 202 | CLKDEV_DEV_ID("i2c-rcar.1", &mstp_clks[MSTP029]), /* I2C1 */ |
| 203 | CLKDEV_DEV_ID("ffc71000.i2c", &mstp_clks[MSTP029]), /* I2C1 */ | ||
| 187 | CLKDEV_DEV_ID("i2c-rcar.2", &mstp_clks[MSTP028]), /* I2C2 */ | 204 | CLKDEV_DEV_ID("i2c-rcar.2", &mstp_clks[MSTP028]), /* I2C2 */ |
| 205 | CLKDEV_DEV_ID("ffc72000.i2c", &mstp_clks[MSTP028]), /* I2C2 */ | ||
| 188 | CLKDEV_DEV_ID("i2c-rcar.3", &mstp_clks[MSTP027]), /* I2C3 */ | 206 | CLKDEV_DEV_ID("i2c-rcar.3", &mstp_clks[MSTP027]), /* I2C3 */ |
| 207 | CLKDEV_DEV_ID("ffc73000.i2c", &mstp_clks[MSTP027]), /* I2C3 */ | ||
| 189 | CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */ | 208 | CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */ |
| 190 | CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */ | 209 | CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */ |
| 191 | CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */ | 210 | CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */ |
| @@ -195,8 +214,11 @@ static struct clk_lookup lookups[] = { | |||
| 195 | CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP016]), /* TMU00 */ | 214 | CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP016]), /* TMU00 */ |
| 196 | CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP015]), /* TMU01 */ | 215 | CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP015]), /* TMU01 */ |
| 197 | CLKDEV_DEV_ID("sh-hspi.0", &mstp_clks[MSTP007]), /* HSPI0 */ | 216 | CLKDEV_DEV_ID("sh-hspi.0", &mstp_clks[MSTP007]), /* HSPI0 */ |
| 217 | CLKDEV_DEV_ID("fffc7000.spi", &mstp_clks[MSTP007]), /* HSPI0 */ | ||
| 198 | CLKDEV_DEV_ID("sh-hspi.1", &mstp_clks[MSTP007]), /* HSPI1 */ | 218 | CLKDEV_DEV_ID("sh-hspi.1", &mstp_clks[MSTP007]), /* HSPI1 */ |
| 219 | CLKDEV_DEV_ID("fffc8000.spi", &mstp_clks[MSTP007]), /* HSPI1 */ | ||
| 199 | CLKDEV_DEV_ID("sh-hspi.2", &mstp_clks[MSTP007]), /* HSPI2 */ | 220 | CLKDEV_DEV_ID("sh-hspi.2", &mstp_clks[MSTP007]), /* HSPI2 */ |
| 221 | CLKDEV_DEV_ID("fffc6000.spi", &mstp_clks[MSTP007]), /* HSPI2 */ | ||
| 200 | CLKDEV_DEV_ID("rcar_sound", &mstp_clks[MSTP008]), /* SRU */ | 222 | CLKDEV_DEV_ID("rcar_sound", &mstp_clks[MSTP008]), /* SRU */ |
| 201 | 223 | ||
| 202 | CLKDEV_ICK_ID("ssi.0", "rcar_sound", &mstp_clks[MSTP012]), | 224 | CLKDEV_ICK_ID("ssi.0", "rcar_sound", &mstp_clks[MSTP012]), |
| @@ -208,6 +230,15 @@ static struct clk_lookup lookups[] = { | |||
| 208 | CLKDEV_ICK_ID("ssi.6", "rcar_sound", &mstp_clks[MSTP309]), | 230 | CLKDEV_ICK_ID("ssi.6", "rcar_sound", &mstp_clks[MSTP309]), |
| 209 | CLKDEV_ICK_ID("ssi.7", "rcar_sound", &mstp_clks[MSTP308]), | 231 | CLKDEV_ICK_ID("ssi.7", "rcar_sound", &mstp_clks[MSTP308]), |
| 210 | CLKDEV_ICK_ID("ssi.8", "rcar_sound", &mstp_clks[MSTP307]), | 232 | CLKDEV_ICK_ID("ssi.8", "rcar_sound", &mstp_clks[MSTP307]), |
| 233 | CLKDEV_ICK_ID("scu.0", "rcar_sound", &mstp_clks[MSTP531]), | ||
| 234 | CLKDEV_ICK_ID("scu.1", "rcar_sound", &mstp_clks[MSTP530]), | ||
| 235 | CLKDEV_ICK_ID("scu.2", "rcar_sound", &mstp_clks[MSTP529]), | ||
| 236 | CLKDEV_ICK_ID("scu.3", "rcar_sound", &mstp_clks[MSTP528]), | ||
| 237 | CLKDEV_ICK_ID("scu.4", "rcar_sound", &mstp_clks[MSTP527]), | ||
| 238 | CLKDEV_ICK_ID("scu.5", "rcar_sound", &mstp_clks[MSTP526]), | ||
| 239 | CLKDEV_ICK_ID("scu.6", "rcar_sound", &mstp_clks[MSTP525]), | ||
| 240 | CLKDEV_ICK_ID("scu.7", "rcar_sound", &mstp_clks[MSTP524]), | ||
| 241 | CLKDEV_ICK_ID("scu.8", "rcar_sound", &mstp_clks[MSTP523]), | ||
| 211 | }; | 242 | }; |
| 212 | 243 | ||
| 213 | void __init r8a7778_clock_init(void) | 244 | void __init r8a7778_clock_init(void) |
diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c index 1f7080fab0a5..b545c8dbb818 100644 --- a/arch/arm/mach-shmobile/clock-r8a7779.c +++ b/arch/arm/mach-shmobile/clock-r8a7779.c | |||
| @@ -184,9 +184,13 @@ static struct clk_lookup lookups[] = { | |||
| 184 | CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP016]), /* TMU01 */ | 184 | CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP016]), /* TMU01 */ |
| 185 | CLKDEV_DEV_ID("sh_tmu.2", &mstp_clks[MSTP016]), /* TMU02 */ | 185 | CLKDEV_DEV_ID("sh_tmu.2", &mstp_clks[MSTP016]), /* TMU02 */ |
| 186 | CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP030]), /* I2C0 */ | 186 | CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP030]), /* I2C0 */ |
| 187 | CLKDEV_DEV_ID("ffc70000.i2c", &mstp_clks[MSTP030]), /* I2C0 */ | ||
| 187 | CLKDEV_DEV_ID("i2c-rcar.1", &mstp_clks[MSTP029]), /* I2C1 */ | 188 | CLKDEV_DEV_ID("i2c-rcar.1", &mstp_clks[MSTP029]), /* I2C1 */ |
| 189 | CLKDEV_DEV_ID("ffc71000.i2c", &mstp_clks[MSTP029]), /* I2C1 */ | ||
| 188 | CLKDEV_DEV_ID("i2c-rcar.2", &mstp_clks[MSTP028]), /* I2C2 */ | 190 | CLKDEV_DEV_ID("i2c-rcar.2", &mstp_clks[MSTP028]), /* I2C2 */ |
| 191 | CLKDEV_DEV_ID("ffc72000.i2c", &mstp_clks[MSTP028]), /* I2C2 */ | ||
| 189 | CLKDEV_DEV_ID("i2c-rcar.3", &mstp_clks[MSTP027]), /* I2C3 */ | 192 | CLKDEV_DEV_ID("i2c-rcar.3", &mstp_clks[MSTP027]), /* I2C3 */ |
| 193 | CLKDEV_DEV_ID("ffc73000.i2c", &mstp_clks[MSTP027]), /* I2C3 */ | ||
| 190 | CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */ | 194 | CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */ |
| 191 | CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */ | 195 | CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */ |
| 192 | CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */ | 196 | CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */ |
| @@ -194,12 +198,19 @@ static struct clk_lookup lookups[] = { | |||
| 194 | CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */ | 198 | CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */ |
| 195 | CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */ | 199 | CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */ |
| 196 | CLKDEV_DEV_ID("sh-hspi.0", &mstp_clks[MSTP007]), /* HSPI0 */ | 200 | CLKDEV_DEV_ID("sh-hspi.0", &mstp_clks[MSTP007]), /* HSPI0 */ |
| 201 | CLKDEV_DEV_ID("fffc7000.spi", &mstp_clks[MSTP007]), /* HSPI0 */ | ||
| 197 | CLKDEV_DEV_ID("sh-hspi.1", &mstp_clks[MSTP007]), /* HSPI1 */ | 202 | CLKDEV_DEV_ID("sh-hspi.1", &mstp_clks[MSTP007]), /* HSPI1 */ |
| 203 | CLKDEV_DEV_ID("fffc8000.spi", &mstp_clks[MSTP007]), /* HSPI1 */ | ||
| 198 | CLKDEV_DEV_ID("sh-hspi.2", &mstp_clks[MSTP007]), /* HSPI2 */ | 204 | CLKDEV_DEV_ID("sh-hspi.2", &mstp_clks[MSTP007]), /* HSPI2 */ |
| 205 | CLKDEV_DEV_ID("fffc6000.spi", &mstp_clks[MSTP007]), /* HSPI2 */ | ||
| 199 | CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */ | 206 | CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */ |
| 207 | CLKDEV_DEV_ID("ffe4c000.sdhi", &mstp_clks[MSTP323]), /* SDHI0 */ | ||
| 200 | CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */ | 208 | CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */ |
| 209 | CLKDEV_DEV_ID("ffe4d000.sdhi", &mstp_clks[MSTP322]), /* SDHI1 */ | ||
| 201 | CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */ | 210 | CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */ |
| 211 | CLKDEV_DEV_ID("ffe4e000.sdhi", &mstp_clks[MSTP321]), /* SDHI2 */ | ||
| 202 | CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP320]), /* SDHI3 */ | 212 | CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP320]), /* SDHI3 */ |
| 213 | CLKDEV_DEV_ID("ffe4f000.sdhi", &mstp_clks[MSTP320]), /* SDHI3 */ | ||
| 203 | CLKDEV_DEV_ID("rcar-du-r8a7779", &mstp_clks[MSTP103]), /* DU */ | 214 | CLKDEV_DEV_ID("rcar-du-r8a7779", &mstp_clks[MSTP103]), /* DU */ |
| 204 | }; | 215 | }; |
| 205 | 216 | ||
diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c index a64f965c7da1..b6ecea3ec7d5 100644 --- a/arch/arm/mach-shmobile/clock-r8a7790.c +++ b/arch/arm/mach-shmobile/clock-r8a7790.c | |||
| @@ -53,6 +53,7 @@ | |||
| 53 | #define SMSTPCR7 0xe615014c | 53 | #define SMSTPCR7 0xe615014c |
| 54 | #define SMSTPCR8 0xe6150990 | 54 | #define SMSTPCR8 0xe6150990 |
| 55 | #define SMSTPCR9 0xe6150994 | 55 | #define SMSTPCR9 0xe6150994 |
| 56 | #define SMSTPCR10 0xe6150998 | ||
| 56 | 57 | ||
| 57 | #define SDCKCR 0xE6150074 | 58 | #define SDCKCR 0xE6150074 |
| 58 | #define SD2CKCR 0xE6150078 | 59 | #define SD2CKCR 0xE6150078 |
| @@ -182,10 +183,14 @@ static struct clk div6_clks[DIV6_NR] = { | |||
| 182 | 183 | ||
| 183 | /* MSTP */ | 184 | /* MSTP */ |
| 184 | enum { | 185 | enum { |
| 186 | MSTP1015, MSTP1014, MSTP1013, MSTP1012, MSTP1011, MSTP1010, | ||
| 187 | MSTP1009, MSTP1008, MSTP1007, MSTP1006, MSTP1005, | ||
| 185 | MSTP931, MSTP930, MSTP929, MSTP928, | 188 | MSTP931, MSTP930, MSTP929, MSTP928, |
| 189 | MSTP917, | ||
| 186 | MSTP813, | 190 | MSTP813, |
| 187 | MSTP726, MSTP725, MSTP724, MSTP723, MSTP722, MSTP721, MSTP720, | 191 | MSTP726, MSTP725, MSTP724, MSTP723, MSTP722, MSTP721, MSTP720, |
| 188 | MSTP717, MSTP716, | 192 | MSTP717, MSTP716, |
| 193 | MSTP704, | ||
| 189 | MSTP522, | 194 | MSTP522, |
| 190 | MSTP315, MSTP314, MSTP313, MSTP312, MSTP311, MSTP305, MSTP304, | 195 | MSTP315, MSTP314, MSTP313, MSTP312, MSTP311, MSTP305, MSTP304, |
| 191 | MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, | 196 | MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, |
| @@ -194,10 +199,22 @@ enum { | |||
| 194 | }; | 199 | }; |
| 195 | 200 | ||
| 196 | static struct clk mstp_clks[MSTP_NR] = { | 201 | static struct clk mstp_clks[MSTP_NR] = { |
| 197 | [MSTP931] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 31, 0), /* I2C0 */ | 202 | [MSTP1015] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 15, 0), /* SSI0 */ |
| 198 | [MSTP930] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 30, 0), /* I2C1 */ | 203 | [MSTP1014] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 14, 0), /* SSI1 */ |
| 199 | [MSTP929] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 29, 0), /* I2C2 */ | 204 | [MSTP1013] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 13, 0), /* SSI2 */ |
| 200 | [MSTP928] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 28, 0), /* I2C3 */ | 205 | [MSTP1012] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 12, 0), /* SSI3 */ |
| 206 | [MSTP1011] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 11, 0), /* SSI4 */ | ||
| 207 | [MSTP1010] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 10, 0), /* SSI5 */ | ||
| 208 | [MSTP1009] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 9, 0), /* SSI6 */ | ||
| 209 | [MSTP1008] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 8, 0), /* SSI7 */ | ||
| 210 | [MSTP1007] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 7, 0), /* SSI8 */ | ||
| 211 | [MSTP1006] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 6, 0), /* SSI9 */ | ||
| 212 | [MSTP1005] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 5, 0), /* SSI ALL */ | ||
| 213 | [MSTP931] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 31, 0), /* I2C0 */ | ||
| 214 | [MSTP930] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 30, 0), /* I2C1 */ | ||
| 215 | [MSTP929] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 29, 0), /* I2C2 */ | ||
| 216 | [MSTP928] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 28, 0), /* I2C3 */ | ||
| 217 | [MSTP917] = SH_CLK_MSTP32(&qspi_clk, SMSTPCR9, 17, 0), /* QSPI */ | ||
| 201 | [MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */ | 218 | [MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */ |
| 202 | [MSTP726] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 26, 0), /* LVDS0 */ | 219 | [MSTP726] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 26, 0), /* LVDS0 */ |
| 203 | [MSTP725] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 25, 0), /* LVDS1 */ | 220 | [MSTP725] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 25, 0), /* LVDS1 */ |
| @@ -208,6 +225,7 @@ static struct clk mstp_clks[MSTP_NR] = { | |||
| 208 | [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */ | 225 | [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */ |
| 209 | [MSTP717] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 17, 0), /* HSCIF0 */ | 226 | [MSTP717] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 17, 0), /* HSCIF0 */ |
| 210 | [MSTP716] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 16, 0), /* HSCIF1 */ | 227 | [MSTP716] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 16, 0), /* HSCIF1 */ |
| 228 | [MSTP704] = SH_CLK_MSTP32(&mp_clk, SMSTPCR7, 4, 0), /* HSUSB */ | ||
| 211 | [MSTP522] = SH_CLK_MSTP32(&extal_clk, SMSTPCR5, 22, 0), /* Thermal */ | 229 | [MSTP522] = SH_CLK_MSTP32(&extal_clk, SMSTPCR5, 22, 0), /* Thermal */ |
| 212 | [MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0], SMSTPCR3, 15, 0), /* MMC0 */ | 230 | [MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0], SMSTPCR3, 15, 0), /* MMC0 */ |
| 213 | [MSTP314] = SH_CLK_MSTP32(&div4_clks[DIV4_SD0], SMSTPCR3, 14, 0), /* SDHI0 */ | 231 | [MSTP314] = SH_CLK_MSTP32(&div4_clks[DIV4_SD0], SMSTPCR3, 14, 0), /* SDHI0 */ |
| @@ -262,11 +280,7 @@ static struct clk_lookup lookups[] = { | |||
| 262 | CLKDEV_CON_ID("ssprs", &div6_clks[DIV6_SSPRS]), | 280 | CLKDEV_CON_ID("ssprs", &div6_clks[DIV6_SSPRS]), |
| 263 | 281 | ||
| 264 | /* MSTP */ | 282 | /* MSTP */ |
| 265 | CLKDEV_ICK_ID("lvds.0", "rcar-du-r8a7790", &mstp_clks[MSTP726]), | 283 | CLKDEV_DEV_ID("rcar_sound", &mstp_clks[MSTP1005]), |
| 266 | CLKDEV_ICK_ID("lvds.1", "rcar-du-r8a7790", &mstp_clks[MSTP725]), | ||
| 267 | CLKDEV_ICK_ID("du.0", "rcar-du-r8a7790", &mstp_clks[MSTP724]), | ||
| 268 | CLKDEV_ICK_ID("du.1", "rcar-du-r8a7790", &mstp_clks[MSTP723]), | ||
| 269 | CLKDEV_ICK_ID("du.2", "rcar-du-r8a7790", &mstp_clks[MSTP722]), | ||
| 270 | CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), | 284 | CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), |
| 271 | CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), | 285 | CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), |
| 272 | CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]), | 286 | CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]), |
| @@ -278,10 +292,15 @@ static struct clk_lookup lookups[] = { | |||
| 278 | CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP717]), | 292 | CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP717]), |
| 279 | CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP716]), | 293 | CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP716]), |
| 280 | CLKDEV_DEV_ID("e6508000.i2c", &mstp_clks[MSTP931]), | 294 | CLKDEV_DEV_ID("e6508000.i2c", &mstp_clks[MSTP931]), |
| 295 | CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP931]), | ||
| 281 | CLKDEV_DEV_ID("e6518000.i2c", &mstp_clks[MSTP930]), | 296 | CLKDEV_DEV_ID("e6518000.i2c", &mstp_clks[MSTP930]), |
| 297 | CLKDEV_DEV_ID("i2c-rcar.1", &mstp_clks[MSTP930]), | ||
| 282 | CLKDEV_DEV_ID("e6530000.i2c", &mstp_clks[MSTP929]), | 298 | CLKDEV_DEV_ID("e6530000.i2c", &mstp_clks[MSTP929]), |
| 299 | CLKDEV_DEV_ID("i2c-rcar.2", &mstp_clks[MSTP929]), | ||
| 283 | CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP928]), | 300 | CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP928]), |
| 301 | CLKDEV_DEV_ID("i2c-rcar.3", &mstp_clks[MSTP928]), | ||
| 284 | CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]), | 302 | CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]), |
| 303 | CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]), | ||
| 285 | CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]), | 304 | CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]), |
| 286 | CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]), | 305 | CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]), |
| 287 | CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]), | 306 | CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]), |
| @@ -296,6 +315,27 @@ static struct clk_lookup lookups[] = { | |||
| 296 | CLKDEV_DEV_ID("ee220000.mmcif", &mstp_clks[MSTP305]), | 315 | CLKDEV_DEV_ID("ee220000.mmcif", &mstp_clks[MSTP305]), |
| 297 | CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]), | 316 | CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]), |
| 298 | CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]), | 317 | CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]), |
| 318 | CLKDEV_DEV_ID("qspi.0", &mstp_clks[MSTP917]), | ||
| 319 | CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP704]), | ||
| 320 | |||
| 321 | /* ICK */ | ||
| 322 | CLKDEV_ICK_ID("usbhs", "usb_phy_rcar_gen2", &mstp_clks[MSTP704]), | ||
| 323 | CLKDEV_ICK_ID("lvds.0", "rcar-du-r8a7790", &mstp_clks[MSTP726]), | ||
| 324 | CLKDEV_ICK_ID("lvds.1", "rcar-du-r8a7790", &mstp_clks[MSTP725]), | ||
| 325 | CLKDEV_ICK_ID("du.0", "rcar-du-r8a7790", &mstp_clks[MSTP724]), | ||
| 326 | CLKDEV_ICK_ID("du.1", "rcar-du-r8a7790", &mstp_clks[MSTP723]), | ||
| 327 | CLKDEV_ICK_ID("du.2", "rcar-du-r8a7790", &mstp_clks[MSTP722]), | ||
| 328 | CLKDEV_ICK_ID("ssi.0", "rcar_sound", &mstp_clks[MSTP1015]), | ||
| 329 | CLKDEV_ICK_ID("ssi.1", "rcar_sound", &mstp_clks[MSTP1014]), | ||
| 330 | CLKDEV_ICK_ID("ssi.2", "rcar_sound", &mstp_clks[MSTP1013]), | ||
| 331 | CLKDEV_ICK_ID("ssi.3", "rcar_sound", &mstp_clks[MSTP1012]), | ||
| 332 | CLKDEV_ICK_ID("ssi.4", "rcar_sound", &mstp_clks[MSTP1011]), | ||
| 333 | CLKDEV_ICK_ID("ssi.5", "rcar_sound", &mstp_clks[MSTP1010]), | ||
| 334 | CLKDEV_ICK_ID("ssi.6", "rcar_sound", &mstp_clks[MSTP1009]), | ||
| 335 | CLKDEV_ICK_ID("ssi.7", "rcar_sound", &mstp_clks[MSTP1008]), | ||
| 336 | CLKDEV_ICK_ID("ssi.8", "rcar_sound", &mstp_clks[MSTP1007]), | ||
| 337 | CLKDEV_ICK_ID("ssi.9", "rcar_sound", &mstp_clks[MSTP1006]), | ||
| 338 | |||
| 299 | }; | 339 | }; |
| 300 | 340 | ||
| 301 | #define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31) \ | 341 | #define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31) \ |
| @@ -321,10 +361,10 @@ void __init r8a7790_clock_init(void) | |||
| 321 | R8A7790_CLOCK_ROOT(20, &extal_clk, 130, 156, 80, 66); | 361 | R8A7790_CLOCK_ROOT(20, &extal_clk, 130, 156, 80, 66); |
| 322 | break; | 362 | break; |
| 323 | case MD(14): | 363 | case MD(14): |
| 324 | R8A7790_CLOCK_ROOT(26, &extal_div2_clk, 200, 240, 122, 102); | 364 | R8A7790_CLOCK_ROOT(26 / 2, &extal_div2_clk, 200, 240, 122, 102); |
| 325 | break; | 365 | break; |
| 326 | case MD(13) | MD(14): | 366 | case MD(13) | MD(14): |
| 327 | R8A7790_CLOCK_ROOT(30, &extal_div2_clk, 172, 208, 106, 88); | 367 | R8A7790_CLOCK_ROOT(30 / 2, &extal_div2_clk, 172, 208, 106, 88); |
| 328 | break; | 368 | break; |
| 329 | } | 369 | } |
| 330 | 370 | ||
diff --git a/arch/arm/mach-shmobile/clock-r8a7791.c b/arch/arm/mach-shmobile/clock-r8a7791.c index c9a26f16ce5b..f5461262ee25 100644 --- a/arch/arm/mach-shmobile/clock-r8a7791.c +++ b/arch/arm/mach-shmobile/clock-r8a7791.c | |||
| @@ -103,6 +103,7 @@ SH_FIXED_RATIO_CLK_SET(hp_clk, pll1_clk, 1, 12); | |||
| 103 | SH_FIXED_RATIO_CLK_SET(p_clk, pll1_clk, 1, 24); | 103 | SH_FIXED_RATIO_CLK_SET(p_clk, pll1_clk, 1, 24); |
| 104 | SH_FIXED_RATIO_CLK_SET(rclk_clk, pll1_clk, 1, (48 * 1024)); | 104 | SH_FIXED_RATIO_CLK_SET(rclk_clk, pll1_clk, 1, (48 * 1024)); |
| 105 | SH_FIXED_RATIO_CLK_SET(mp_clk, pll1_div2_clk, 1, 15); | 105 | SH_FIXED_RATIO_CLK_SET(mp_clk, pll1_div2_clk, 1, 15); |
| 106 | SH_FIXED_RATIO_CLK_SET(zx_clk, pll1_clk, 1, 3); | ||
| 106 | 107 | ||
| 107 | static struct clk *main_clks[] = { | 108 | static struct clk *main_clks[] = { |
| 108 | &extal_clk, | 109 | &extal_clk, |
| @@ -116,12 +117,15 @@ static struct clk *main_clks[] = { | |||
| 116 | &rclk_clk, | 117 | &rclk_clk, |
| 117 | &mp_clk, | 118 | &mp_clk, |
| 118 | &cp_clk, | 119 | &cp_clk, |
| 120 | &zx_clk, | ||
| 119 | }; | 121 | }; |
| 120 | 122 | ||
| 121 | /* MSTP */ | 123 | /* MSTP */ |
| 122 | enum { | 124 | enum { |
| 123 | MSTP721, MSTP720, | 125 | MSTP813, |
| 126 | MSTP726, MSTP724, MSTP723, MSTP721, MSTP720, | ||
| 124 | MSTP719, MSTP718, MSTP715, MSTP714, | 127 | MSTP719, MSTP718, MSTP715, MSTP714, |
| 128 | MSTP522, | ||
| 125 | MSTP216, MSTP207, MSTP206, | 129 | MSTP216, MSTP207, MSTP206, |
| 126 | MSTP204, MSTP203, MSTP202, MSTP1105, MSTP1106, MSTP1107, | 130 | MSTP204, MSTP203, MSTP202, MSTP1105, MSTP1106, MSTP1107, |
| 127 | MSTP124, | 131 | MSTP124, |
| @@ -129,12 +133,17 @@ enum { | |||
| 129 | }; | 133 | }; |
| 130 | 134 | ||
| 131 | static struct clk mstp_clks[MSTP_NR] = { | 135 | static struct clk mstp_clks[MSTP_NR] = { |
| 136 | [MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */ | ||
| 137 | [MSTP726] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 26, 0), /* LVDS0 */ | ||
| 138 | [MSTP724] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 24, 0), /* DU0 */ | ||
| 139 | [MSTP723] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 23, 0), /* DU1 */ | ||
| 132 | [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */ | 140 | [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */ |
| 133 | [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */ | 141 | [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */ |
| 134 | [MSTP719] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 19, 0), /* SCIF2 */ | 142 | [MSTP719] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 19, 0), /* SCIF2 */ |
| 135 | [MSTP718] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 18, 0), /* SCIF3 */ | 143 | [MSTP718] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 18, 0), /* SCIF3 */ |
| 136 | [MSTP715] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 15, 0), /* SCIF4 */ | 144 | [MSTP715] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 15, 0), /* SCIF4 */ |
| 137 | [MSTP714] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 14, 0), /* SCIF5 */ | 145 | [MSTP714] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 14, 0), /* SCIF5 */ |
| 146 | [MSTP522] = SH_CLK_MSTP32(&extal_clk, SMSTPCR5, 22, 0), /* Thermal */ | ||
| 138 | [MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */ | 147 | [MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */ |
| 139 | [MSTP207] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 7, 0), /* SCIFB1 */ | 148 | [MSTP207] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 7, 0), /* SCIFB1 */ |
| 140 | [MSTP206] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 6, 0), /* SCIFB0 */ | 149 | [MSTP206] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 6, 0), /* SCIFB0 */ |
| @@ -164,6 +173,9 @@ static struct clk_lookup lookups[] = { | |||
| 164 | CLKDEV_CON_ID("peripheral_clk", &hp_clk), | 173 | CLKDEV_CON_ID("peripheral_clk", &hp_clk), |
| 165 | 174 | ||
| 166 | /* MSTP */ | 175 | /* MSTP */ |
| 176 | CLKDEV_ICK_ID("lvds.0", "rcar-du-r8a7791", &mstp_clks[MSTP726]), | ||
| 177 | CLKDEV_ICK_ID("du.0", "rcar-du-r8a7791", &mstp_clks[MSTP724]), | ||
| 178 | CLKDEV_ICK_ID("du.1", "rcar-du-r8a7791", &mstp_clks[MSTP723]), | ||
| 167 | CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */ | 179 | CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */ |
| 168 | CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */ | 180 | CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */ |
| 169 | CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]), /* SCIFB0 */ | 181 | CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]), /* SCIFB0 */ |
| @@ -180,6 +192,9 @@ static struct clk_lookup lookups[] = { | |||
| 180 | CLKDEV_DEV_ID("sh-sci.13", &mstp_clks[MSTP1106]), /* SCIFA4 */ | 192 | CLKDEV_DEV_ID("sh-sci.13", &mstp_clks[MSTP1106]), /* SCIFA4 */ |
| 181 | CLKDEV_DEV_ID("sh-sci.14", &mstp_clks[MSTP1107]), /* SCIFA5 */ | 193 | CLKDEV_DEV_ID("sh-sci.14", &mstp_clks[MSTP1107]), /* SCIFA5 */ |
| 182 | CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]), | 194 | CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]), |
| 195 | CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]), | ||
| 196 | CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]), | ||
| 197 | CLKDEV_DEV_ID("r8a7791-ether", &mstp_clks[MSTP813]), /* Ether */ | ||
| 183 | }; | 198 | }; |
| 184 | 199 | ||
| 185 | #define R8A7791_CLOCK_ROOT(e, m, p0, p1, p30, p31) \ | 200 | #define R8A7791_CLOCK_ROOT(e, m, p0, p1, p30, p31) \ |
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c index c92c023f0d27..5e6a0566f3c6 100644 --- a/arch/arm/mach-shmobile/clock-sh73a0.c +++ b/arch/arm/mach-shmobile/clock-sh73a0.c | |||
| @@ -658,6 +658,7 @@ static struct clk_lookup lookups[] = { | |||
| 658 | CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP331]), /* SCIFA6 */ | 658 | CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP331]), /* SCIFA6 */ |
| 659 | CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */ | 659 | CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */ |
| 660 | CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), /* FSI */ | 660 | CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), /* FSI */ |
| 661 | CLKDEV_DEV_ID("ec230000.sound", &mstp_clks[MSTP328]), /* FSI */ | ||
| 661 | CLKDEV_DEV_ID("sh_irda.0", &mstp_clks[MSTP325]), /* IrDA */ | 662 | CLKDEV_DEV_ID("sh_irda.0", &mstp_clks[MSTP325]), /* IrDA */ |
| 662 | CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* I2C1 */ | 663 | CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* I2C1 */ |
| 663 | CLKDEV_DEV_ID("e6822000.i2c", &mstp_clks[MSTP323]), /* I2C1 */ | 664 | CLKDEV_DEV_ID("e6822000.i2c", &mstp_clks[MSTP323]), /* I2C1 */ |
diff --git a/arch/arm/mach-shmobile/include/mach/emev2.h b/arch/arm/mach-shmobile/include/mach/emev2.h index c2eb7568d9be..fcb142a14e07 100644 --- a/arch/arm/mach-shmobile/include/mach/emev2.h +++ b/arch/arm/mach-shmobile/include/mach/emev2.h | |||
| @@ -3,12 +3,7 @@ | |||
| 3 | 3 | ||
| 4 | extern void emev2_map_io(void); | 4 | extern void emev2_map_io(void); |
| 5 | extern void emev2_init_delay(void); | 5 | extern void emev2_init_delay(void); |
| 6 | extern void emev2_add_standard_devices(void); | ||
| 7 | extern void emev2_clock_init(void); | 6 | extern void emev2_clock_init(void); |
| 8 | |||
| 9 | #define EMEV2_GPIO_BASE 200 | ||
| 10 | #define EMEV2_GPIO_IRQ(n) (EMEV2_GPIO_BASE + (n)) | ||
| 11 | |||
| 12 | extern struct smp_operations emev2_smp_ops; | 7 | extern struct smp_operations emev2_smp_ops; |
| 13 | 8 | ||
| 14 | #endif /* __ASM_EMEV2_H__ */ | 9 | #endif /* __ASM_EMEV2_H__ */ |
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7778.h b/arch/arm/mach-shmobile/include/mach/r8a7778.h index 441886c9714b..f4076a50e970 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a7778.h +++ b/arch/arm/mach-shmobile/include/mach/r8a7778.h | |||
| @@ -20,13 +20,50 @@ | |||
| 20 | #define __ASM_R8A7778_H__ | 20 | #define __ASM_R8A7778_H__ |
| 21 | 21 | ||
| 22 | #include <linux/sh_eth.h> | 22 | #include <linux/sh_eth.h> |
| 23 | #include <linux/platform_data/camera-rcar.h> | ||
| 24 | 23 | ||
| 25 | /* HPB-DMA slave IDs */ | 24 | /* HPB-DMA slave IDs */ |
| 26 | enum { | 25 | enum { |
| 27 | HPBDMA_SLAVE_DUMMY, | 26 | HPBDMA_SLAVE_DUMMY, |
| 28 | HPBDMA_SLAVE_SDHI0_TX, | 27 | HPBDMA_SLAVE_SDHI0_TX, |
| 29 | HPBDMA_SLAVE_SDHI0_RX, | 28 | HPBDMA_SLAVE_SDHI0_RX, |
| 29 | HPBDMA_SLAVE_SSI0_TX, | ||
| 30 | HPBDMA_SLAVE_SSI0_RX, | ||
| 31 | HPBDMA_SLAVE_SSI1_TX, | ||
| 32 | HPBDMA_SLAVE_SSI1_RX, | ||
| 33 | HPBDMA_SLAVE_SSI2_TX, | ||
| 34 | HPBDMA_SLAVE_SSI2_RX, | ||
| 35 | HPBDMA_SLAVE_SSI3_TX, | ||
| 36 | HPBDMA_SLAVE_SSI3_RX, | ||
| 37 | HPBDMA_SLAVE_SSI4_TX, | ||
| 38 | HPBDMA_SLAVE_SSI4_RX, | ||
| 39 | HPBDMA_SLAVE_SSI5_TX, | ||
| 40 | HPBDMA_SLAVE_SSI5_RX, | ||
| 41 | HPBDMA_SLAVE_SSI6_TX, | ||
| 42 | HPBDMA_SLAVE_SSI6_RX, | ||
| 43 | HPBDMA_SLAVE_SSI7_TX, | ||
| 44 | HPBDMA_SLAVE_SSI7_RX, | ||
| 45 | HPBDMA_SLAVE_SSI8_TX, | ||
| 46 | HPBDMA_SLAVE_SSI8_RX, | ||
| 47 | HPBDMA_SLAVE_HPBIF0_TX, | ||
| 48 | HPBDMA_SLAVE_HPBIF0_RX, | ||
| 49 | HPBDMA_SLAVE_HPBIF1_TX, | ||
| 50 | HPBDMA_SLAVE_HPBIF1_RX, | ||
| 51 | HPBDMA_SLAVE_HPBIF2_TX, | ||
| 52 | HPBDMA_SLAVE_HPBIF2_RX, | ||
| 53 | HPBDMA_SLAVE_HPBIF3_TX, | ||
| 54 | HPBDMA_SLAVE_HPBIF3_RX, | ||
| 55 | HPBDMA_SLAVE_HPBIF4_TX, | ||
| 56 | HPBDMA_SLAVE_HPBIF4_RX, | ||
| 57 | HPBDMA_SLAVE_HPBIF5_TX, | ||
| 58 | HPBDMA_SLAVE_HPBIF5_RX, | ||
| 59 | HPBDMA_SLAVE_HPBIF6_TX, | ||
| 60 | HPBDMA_SLAVE_HPBIF6_RX, | ||
| 61 | HPBDMA_SLAVE_HPBIF7_TX, | ||
| 62 | HPBDMA_SLAVE_HPBIF7_RX, | ||
| 63 | HPBDMA_SLAVE_HPBIF8_TX, | ||
| 64 | HPBDMA_SLAVE_HPBIF8_RX, | ||
| 65 | HPBDMA_SLAVE_USBFUNC_TX, | ||
| 66 | HPBDMA_SLAVE_USBFUNC_RX, | ||
| 30 | }; | 67 | }; |
| 31 | 68 | ||
| 32 | extern void r8a7778_add_standard_devices(void); | 69 | extern void r8a7778_add_standard_devices(void); |
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7791.h b/arch/arm/mach-shmobile/include/mach/r8a7791.h index 051ead3c286e..200fa699f730 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a7791.h +++ b/arch/arm/mach-shmobile/include/mach/r8a7791.h | |||
| @@ -4,6 +4,7 @@ | |||
| 4 | void r8a7791_add_standard_devices(void); | 4 | void r8a7791_add_standard_devices(void); |
| 5 | void r8a7791_add_dt_devices(void); | 5 | void r8a7791_add_dt_devices(void); |
| 6 | void r8a7791_clock_init(void); | 6 | void r8a7791_clock_init(void); |
| 7 | void r8a7791_pinmux_init(void); | ||
| 7 | void r8a7791_init_early(void); | 8 | void r8a7791_init_early(void); |
| 8 | extern struct smp_operations r8a7791_smp_ops; | 9 | extern struct smp_operations r8a7791_smp_ops; |
| 9 | 10 | ||
diff --git a/arch/arm/mach-shmobile/setup-emev2.c b/arch/arm/mach-shmobile/setup-emev2.c index 3ad531caf4f0..c8f2a1a69a52 100644 --- a/arch/arm/mach-shmobile/setup-emev2.c +++ b/arch/arm/mach-shmobile/setup-emev2.c | |||
| @@ -16,24 +16,15 @@ | |||
| 16 | * along with this program; if not, write to the Free Software | 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ | 18 | */ |
| 19 | #include <linux/clk-provider.h> | ||
| 19 | #include <linux/kernel.h> | 20 | #include <linux/kernel.h> |
| 20 | #include <linux/init.h> | 21 | #include <linux/init.h> |
| 21 | #include <linux/interrupt.h> | ||
| 22 | #include <linux/irq.h> | ||
| 23 | #include <linux/platform_device.h> | ||
| 24 | #include <linux/platform_data/gpio-em.h> | ||
| 25 | #include <linux/of_platform.h> | 22 | #include <linux/of_platform.h> |
| 26 | #include <linux/delay.h> | ||
| 27 | #include <linux/input.h> | ||
| 28 | #include <linux/io.h> | ||
| 29 | #include <linux/irqchip/arm-gic.h> | ||
| 30 | #include <mach/common.h> | 23 | #include <mach/common.h> |
| 31 | #include <mach/emev2.h> | 24 | #include <mach/emev2.h> |
| 32 | #include <mach/irqs.h> | ||
| 33 | #include <asm/mach-types.h> | 25 | #include <asm/mach-types.h> |
| 34 | #include <asm/mach/arch.h> | 26 | #include <asm/mach/arch.h> |
| 35 | #include <asm/mach/map.h> | 27 | #include <asm/mach/map.h> |
| 36 | #include <asm/mach/time.h> | ||
| 37 | 28 | ||
| 38 | static struct map_desc emev2_io_desc[] __initdata = { | 29 | static struct map_desc emev2_io_desc[] __initdata = { |
| 39 | #ifdef CONFIG_SMP | 30 | #ifdef CONFIG_SMP |
| @@ -52,150 +43,20 @@ void __init emev2_map_io(void) | |||
| 52 | iotable_init(emev2_io_desc, ARRAY_SIZE(emev2_io_desc)); | 43 | iotable_init(emev2_io_desc, ARRAY_SIZE(emev2_io_desc)); |
| 53 | } | 44 | } |
| 54 | 45 | ||
| 55 | /* UART */ | ||
| 56 | static struct resource uart0_resources[] = { | ||
| 57 | DEFINE_RES_MEM(0xe1020000, 0x38), | ||
| 58 | DEFINE_RES_IRQ(40), | ||
| 59 | }; | ||
| 60 | |||
| 61 | static struct resource uart1_resources[] = { | ||
| 62 | DEFINE_RES_MEM(0xe1030000, 0x38), | ||
| 63 | DEFINE_RES_IRQ(41), | ||
| 64 | }; | ||
| 65 | |||
| 66 | static struct resource uart2_resources[] = { | ||
| 67 | DEFINE_RES_MEM(0xe1040000, 0x38), | ||
| 68 | DEFINE_RES_IRQ(42), | ||
| 69 | }; | ||
| 70 | |||
| 71 | static struct resource uart3_resources[] = { | ||
| 72 | DEFINE_RES_MEM(0xe1050000, 0x38), | ||
| 73 | DEFINE_RES_IRQ(43), | ||
| 74 | }; | ||
| 75 | |||
| 76 | #define emev2_register_uart(idx) \ | ||
| 77 | platform_device_register_simple("serial8250-em", idx, \ | ||
| 78 | uart##idx##_resources, \ | ||
| 79 | ARRAY_SIZE(uart##idx##_resources)) | ||
| 80 | |||
| 81 | /* STI */ | ||
| 82 | static struct resource sti_resources[] = { | ||
| 83 | DEFINE_RES_MEM(0xe0180000, 0x54), | ||
| 84 | DEFINE_RES_IRQ(157), | ||
| 85 | }; | ||
| 86 | |||
| 87 | #define emev2_register_sti() \ | ||
| 88 | platform_device_register_simple("em_sti", 0, \ | ||
| 89 | sti_resources, \ | ||
| 90 | ARRAY_SIZE(sti_resources)) | ||
| 91 | |||
| 92 | /* GIO */ | ||
| 93 | static struct gpio_em_config gio0_config = { | ||
| 94 | .gpio_base = 0, | ||
| 95 | .irq_base = EMEV2_GPIO_IRQ(0), | ||
| 96 | .number_of_pins = 32, | ||
| 97 | }; | ||
| 98 | |||
| 99 | static struct resource gio0_resources[] = { | ||
| 100 | DEFINE_RES_MEM(0xe0050000, 0x2c), | ||
| 101 | DEFINE_RES_MEM(0xe0050040, 0x20), | ||
| 102 | DEFINE_RES_IRQ(99), | ||
| 103 | DEFINE_RES_IRQ(100), | ||
| 104 | }; | ||
| 105 | |||
| 106 | static struct gpio_em_config gio1_config = { | ||
| 107 | .gpio_base = 32, | ||
| 108 | .irq_base = EMEV2_GPIO_IRQ(32), | ||
| 109 | .number_of_pins = 32, | ||
| 110 | }; | ||
| 111 | |||
| 112 | static struct resource gio1_resources[] = { | ||
| 113 | DEFINE_RES_MEM(0xe0050080, 0x2c), | ||
| 114 | DEFINE_RES_MEM(0xe00500c0, 0x20), | ||
| 115 | DEFINE_RES_IRQ(101), | ||
| 116 | DEFINE_RES_IRQ(102), | ||
| 117 | }; | ||
| 118 | |||
| 119 | static struct gpio_em_config gio2_config = { | ||
| 120 | .gpio_base = 64, | ||
| 121 | .irq_base = EMEV2_GPIO_IRQ(64), | ||
| 122 | .number_of_pins = 32, | ||
| 123 | }; | ||
| 124 | |||
| 125 | static struct resource gio2_resources[] = { | ||
| 126 | DEFINE_RES_MEM(0xe0050100, 0x2c), | ||
| 127 | DEFINE_RES_MEM(0xe0050140, 0x20), | ||
| 128 | DEFINE_RES_IRQ(103), | ||
| 129 | DEFINE_RES_IRQ(104), | ||
| 130 | }; | ||
| 131 | |||
| 132 | static struct gpio_em_config gio3_config = { | ||
| 133 | .gpio_base = 96, | ||
| 134 | .irq_base = EMEV2_GPIO_IRQ(96), | ||
| 135 | .number_of_pins = 32, | ||
| 136 | }; | ||
| 137 | |||
| 138 | static struct resource gio3_resources[] = { | ||
| 139 | DEFINE_RES_MEM(0xe0050180, 0x2c), | ||
| 140 | DEFINE_RES_MEM(0xe00501c0, 0x20), | ||
| 141 | DEFINE_RES_IRQ(105), | ||
| 142 | DEFINE_RES_IRQ(106), | ||
| 143 | }; | ||
| 144 | |||
| 145 | static struct gpio_em_config gio4_config = { | ||
| 146 | .gpio_base = 128, | ||
| 147 | .irq_base = EMEV2_GPIO_IRQ(128), | ||
| 148 | .number_of_pins = 31, | ||
| 149 | }; | ||
| 150 | |||
| 151 | static struct resource gio4_resources[] = { | ||
| 152 | DEFINE_RES_MEM(0xe0050200, 0x2c), | ||
| 153 | DEFINE_RES_MEM(0xe0050240, 0x20), | ||
| 154 | DEFINE_RES_IRQ(107), | ||
| 155 | DEFINE_RES_IRQ(108), | ||
| 156 | }; | ||
| 157 | |||
| 158 | #define emev2_register_gio(idx) \ | ||
| 159 | platform_device_register_resndata(&platform_bus, "em_gio", \ | ||
| 160 | idx, gio##idx##_resources, \ | ||
| 161 | ARRAY_SIZE(gio##idx##_resources), \ | ||
| 162 | &gio##idx##_config, \ | ||
| 163 | sizeof(struct gpio_em_config)) | ||
| 164 | |||
| 165 | static struct resource pmu_resources[] = { | ||
| 166 | DEFINE_RES_IRQ(152), | ||
| 167 | DEFINE_RES_IRQ(153), | ||
| 168 | }; | ||
| 169 | |||
| 170 | #define emev2_register_pmu() \ | ||
| 171 | platform_device_register_simple("arm-pmu", -1, \ | ||
| 172 | pmu_resources, \ | ||
| 173 | ARRAY_SIZE(pmu_resources)) | ||
| 174 | |||
| 175 | void __init emev2_add_standard_devices(void) | ||
| 176 | { | ||
| 177 | if (!IS_ENABLED(CONFIG_COMMON_CLK)) | ||
| 178 | emev2_clock_init(); | ||
| 179 | |||
| 180 | emev2_register_uart(0); | ||
| 181 | emev2_register_uart(1); | ||
| 182 | emev2_register_uart(2); | ||
| 183 | emev2_register_uart(3); | ||
| 184 | emev2_register_sti(); | ||
| 185 | emev2_register_gio(0); | ||
| 186 | emev2_register_gio(1); | ||
| 187 | emev2_register_gio(2); | ||
| 188 | emev2_register_gio(3); | ||
| 189 | emev2_register_gio(4); | ||
| 190 | emev2_register_pmu(); | ||
| 191 | } | ||
| 192 | |||
| 193 | void __init emev2_init_delay(void) | 46 | void __init emev2_init_delay(void) |
| 194 | { | 47 | { |
| 195 | shmobile_setup_delay(533, 1, 3); /* Cortex-A9 @ 533MHz */ | 48 | shmobile_setup_delay(533, 1, 3); /* Cortex-A9 @ 533MHz */ |
| 196 | } | 49 | } |
| 197 | 50 | ||
| 198 | #ifdef CONFIG_USE_OF | 51 | static void __init emev2_add_standard_devices_dt(void) |
| 52 | { | ||
| 53 | #ifdef CONFIG_COMMON_CLK | ||
| 54 | of_clk_init(NULL); | ||
| 55 | #else | ||
| 56 | emev2_clock_init(); | ||
| 57 | #endif | ||
| 58 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); | ||
| 59 | } | ||
| 199 | 60 | ||
| 200 | static const char *emev2_boards_compat_dt[] __initdata = { | 61 | static const char *emev2_boards_compat_dt[] __initdata = { |
| 201 | "renesas,emev2", | 62 | "renesas,emev2", |
| @@ -206,7 +67,7 @@ DT_MACHINE_START(EMEV2_DT, "Generic Emma Mobile EV2 (Flattened Device Tree)") | |||
| 206 | .smp = smp_ops(emev2_smp_ops), | 67 | .smp = smp_ops(emev2_smp_ops), |
| 207 | .map_io = emev2_map_io, | 68 | .map_io = emev2_map_io, |
| 208 | .init_early = emev2_init_delay, | 69 | .init_early = emev2_init_delay, |
| 70 | .init_machine = emev2_add_standard_devices_dt, | ||
| 71 | .init_late = shmobile_init_late, | ||
| 209 | .dt_compat = emev2_boards_compat_dt, | 72 | .dt_compat = emev2_boards_compat_dt, |
| 210 | MACHINE_END | 73 | MACHINE_END |
| 211 | |||
| 212 | #endif /* CONFIG_USE_OF */ | ||
diff --git a/arch/arm/mach-shmobile/setup-r7s72100.c b/arch/arm/mach-shmobile/setup-r7s72100.c index d4eb509a1c87..9c0b3a9d5f7a 100644 --- a/arch/arm/mach-shmobile/setup-r7s72100.c +++ b/arch/arm/mach-shmobile/setup-r7s72100.c | |||
| @@ -22,52 +22,76 @@ | |||
| 22 | #include <linux/kernel.h> | 22 | #include <linux/kernel.h> |
| 23 | #include <linux/of_platform.h> | 23 | #include <linux/of_platform.h> |
| 24 | #include <linux/serial_sci.h> | 24 | #include <linux/serial_sci.h> |
| 25 | #include <linux/sh_timer.h> | ||
| 25 | #include <mach/common.h> | 26 | #include <mach/common.h> |
| 26 | #include <mach/irqs.h> | 27 | #include <mach/irqs.h> |
| 27 | #include <mach/r7s72100.h> | 28 | #include <mach/r7s72100.h> |
| 28 | #include <asm/mach/arch.h> | 29 | #include <asm/mach/arch.h> |
| 29 | 30 | ||
| 30 | #define SCIF_DATA(index, baseaddr, irq) \ | 31 | #define R7S72100_SCIF(index, baseaddr, irq) \ |
| 31 | [index] = { \ | 32 | static const struct plat_sci_port scif##index##_platform_data = { \ |
| 32 | .type = PORT_SCIF, \ | 33 | .type = PORT_SCIF, \ |
| 33 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, \ | 34 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, \ |
| 34 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ | 35 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ |
| 35 | .scbrr_algo_id = SCBRR_ALGO_2, \ | ||
| 36 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | \ | 36 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | \ |
| 37 | SCSCR_REIE, \ | 37 | SCSCR_REIE, \ |
| 38 | .mapbase = baseaddr, \ | 38 | }; \ |
| 39 | .irqs = { irq + 1, irq + 2, irq + 3, irq }, \ | 39 | \ |
| 40 | } | 40 | static struct resource scif##index##_resources[] = { \ |
| 41 | DEFINE_RES_MEM(baseaddr, 0x100), \ | ||
| 42 | DEFINE_RES_IRQ(irq + 1), \ | ||
| 43 | DEFINE_RES_IRQ(irq + 2), \ | ||
| 44 | DEFINE_RES_IRQ(irq + 3), \ | ||
| 45 | DEFINE_RES_IRQ(irq), \ | ||
| 46 | } \ | ||
| 47 | |||
| 48 | R7S72100_SCIF(0, 0xe8007000, gic_iid(221)); | ||
| 49 | R7S72100_SCIF(1, 0xe8007800, gic_iid(225)); | ||
| 50 | R7S72100_SCIF(2, 0xe8008000, gic_iid(229)); | ||
| 51 | R7S72100_SCIF(3, 0xe8008800, gic_iid(233)); | ||
| 52 | R7S72100_SCIF(4, 0xe8009000, gic_iid(237)); | ||
| 53 | R7S72100_SCIF(5, 0xe8009800, gic_iid(241)); | ||
| 54 | R7S72100_SCIF(6, 0xe800a000, gic_iid(245)); | ||
| 55 | R7S72100_SCIF(7, 0xe800a800, gic_iid(249)); | ||
| 41 | 56 | ||
| 42 | enum { SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7 }; | 57 | #define r7s72100_register_scif(index) \ |
| 58 | platform_device_register_resndata(&platform_bus, "sh-sci", index, \ | ||
| 59 | scif##index##_resources, \ | ||
| 60 | ARRAY_SIZE(scif##index##_resources), \ | ||
| 61 | &scif##index##_platform_data, \ | ||
| 62 | sizeof(scif##index##_platform_data)) | ||
| 43 | 63 | ||
| 44 | static const struct plat_sci_port scif[] __initconst = { | 64 | |
| 45 | SCIF_DATA(SCIF0, 0xe8007000, gic_iid(221)), /* SCIF0 */ | 65 | static struct sh_timer_config mtu2_0_platform_data __initdata = { |
| 46 | SCIF_DATA(SCIF1, 0xe8007800, gic_iid(225)), /* SCIF1 */ | 66 | .name = "MTU2_0", |
| 47 | SCIF_DATA(SCIF2, 0xe8008000, gic_iid(229)), /* SCIF2 */ | 67 | .timer_bit = 0, |
| 48 | SCIF_DATA(SCIF3, 0xe8008800, gic_iid(233)), /* SCIF3 */ | 68 | .channel_offset = -0x80, |
| 49 | SCIF_DATA(SCIF4, 0xe8009000, gic_iid(237)), /* SCIF4 */ | 69 | .clockevent_rating = 200, |
| 50 | SCIF_DATA(SCIF5, 0xe8009800, gic_iid(241)), /* SCIF5 */ | ||
| 51 | SCIF_DATA(SCIF6, 0xe800a000, gic_iid(245)), /* SCIF6 */ | ||
| 52 | SCIF_DATA(SCIF7, 0xe800a800, gic_iid(249)), /* SCIF7 */ | ||
| 53 | }; | 70 | }; |
| 54 | 71 | ||
| 55 | static inline void r7s72100_register_scif(int idx) | 72 | static struct resource mtu2_0_resources[] __initdata = { |
| 56 | { | 73 | DEFINE_RES_MEM(0xfcff0300, 0x27), |
| 57 | platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx], | 74 | DEFINE_RES_IRQ(gic_iid(139)), /* MTU2 TGI0A */ |
| 58 | sizeof(struct plat_sci_port)); | 75 | }; |
| 59 | } | 76 | |
| 77 | #define r7s72100_register_mtu2(idx) \ | ||
| 78 | platform_device_register_resndata(&platform_bus, "sh_mtu2", \ | ||
| 79 | idx, mtu2_##idx##_resources, \ | ||
| 80 | ARRAY_SIZE(mtu2_##idx##_resources), \ | ||
| 81 | &mtu2_##idx##_platform_data, \ | ||
| 82 | sizeof(struct sh_timer_config)) | ||
| 60 | 83 | ||
| 61 | void __init r7s72100_add_dt_devices(void) | 84 | void __init r7s72100_add_dt_devices(void) |
| 62 | { | 85 | { |
| 63 | r7s72100_register_scif(SCIF0); | 86 | r7s72100_register_scif(0); |
| 64 | r7s72100_register_scif(SCIF1); | 87 | r7s72100_register_scif(1); |
| 65 | r7s72100_register_scif(SCIF2); | 88 | r7s72100_register_scif(2); |
| 66 | r7s72100_register_scif(SCIF3); | 89 | r7s72100_register_scif(3); |
| 67 | r7s72100_register_scif(SCIF4); | 90 | r7s72100_register_scif(4); |
| 68 | r7s72100_register_scif(SCIF5); | 91 | r7s72100_register_scif(5); |
| 69 | r7s72100_register_scif(SCIF6); | 92 | r7s72100_register_scif(6); |
| 70 | r7s72100_register_scif(SCIF7); | 93 | r7s72100_register_scif(7); |
| 94 | r7s72100_register_mtu2(0); | ||
| 71 | } | 95 | } |
| 72 | 96 | ||
| 73 | void __init r7s72100_init_early(void) | 97 | void __init r7s72100_init_early(void) |
diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c index b0f2749071be..cd36f8078325 100644 --- a/arch/arm/mach-shmobile/setup-r8a73a4.c +++ b/arch/arm/mach-shmobile/setup-r8a73a4.c | |||
| @@ -40,41 +40,39 @@ void __init r8a73a4_pinmux_init(void) | |||
| 40 | ARRAY_SIZE(pfc_resources)); | 40 | ARRAY_SIZE(pfc_resources)); |
| 41 | } | 41 | } |
| 42 | 42 | ||
| 43 | #define SCIF_COMMON(scif_type, baseaddr, irq) \ | 43 | #define R8A73A4_SCIF(scif_type, _scscr, index, baseaddr, irq) \ |
| 44 | static struct plat_sci_port scif##index##_platform_data = { \ | ||
| 44 | .type = scif_type, \ | 45 | .type = scif_type, \ |
| 45 | .mapbase = baseaddr, \ | ||
| 46 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ | 46 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ |
| 47 | .scbrr_algo_id = SCBRR_ALGO_4, \ | 47 | .scscr = _scscr, \ |
| 48 | .irqs = SCIx_IRQ_MUXED(irq) | 48 | }; \ |
| 49 | 49 | \ | |
| 50 | #define SCIFA_DATA(index, baseaddr, irq) \ | 50 | static struct resource scif##index##_resources[] = { \ |
| 51 | [index] = { \ | 51 | DEFINE_RES_MEM(baseaddr, 0x100), \ |
| 52 | SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \ | 52 | DEFINE_RES_IRQ(irq), \ |
| 53 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \ | ||
| 54 | } | 53 | } |
| 55 | 54 | ||
| 56 | #define SCIFB_DATA(index, baseaddr, irq) \ | 55 | #define R8A73A4_SCIFA(index, baseaddr, irq) \ |
| 57 | [index] = { \ | 56 | R8A73A4_SCIF(PORT_SCIFA, SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \ |
| 58 | SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \ | 57 | index, baseaddr, irq) |
| 59 | .scscr = SCSCR_RE | SCSCR_TE, \ | ||
| 60 | } | ||
| 61 | 58 | ||
| 62 | enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFB3 }; | 59 | #define R8A73A4_SCIFB(index, baseaddr, irq) \ |
| 60 | R8A73A4_SCIF(PORT_SCIFB, SCSCR_RE | SCSCR_TE, \ | ||
| 61 | index, baseaddr, irq) | ||
| 63 | 62 | ||
| 64 | static const struct plat_sci_port scif[] = { | 63 | R8A73A4_SCIFA(0, 0xe6c40000, gic_spi(144)); /* SCIFA0 */ |
| 65 | SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */ | 64 | R8A73A4_SCIFA(1, 0xe6c50000, gic_spi(145)); /* SCIFA1 */ |
| 66 | SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */ | 65 | R8A73A4_SCIFB(2, 0xe6c20000, gic_spi(148)); /* SCIFB0 */ |
| 67 | SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */ | 66 | R8A73A4_SCIFB(3, 0xe6c30000, gic_spi(149)); /* SCIFB1 */ |
| 68 | SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */ | 67 | R8A73A4_SCIFB(4, 0xe6ce0000, gic_spi(150)); /* SCIFB2 */ |
| 69 | SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */ | 68 | R8A73A4_SCIFB(5, 0xe6cf0000, gic_spi(151)); /* SCIFB3 */ |
| 70 | SCIFB_DATA(SCIFB3, 0xe6cf0000, gic_spi(151)), /* SCIFB3 */ | ||
| 71 | }; | ||
| 72 | 69 | ||
| 73 | static inline void r8a73a4_register_scif(int idx) | 70 | #define r8a73a4_register_scif(index) \ |
| 74 | { | 71 | platform_device_register_resndata(&platform_bus, "sh-sci", index, \ |
| 75 | platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx], | 72 | scif##index##_resources, \ |
| 76 | sizeof(struct plat_sci_port)); | 73 | ARRAY_SIZE(scif##index##_resources), \ |
| 77 | } | 74 | &scif##index##_platform_data, \ |
| 75 | sizeof(scif##index##_platform_data)) | ||
| 78 | 76 | ||
| 79 | static const struct renesas_irqc_config irqc0_data = { | 77 | static const struct renesas_irqc_config irqc0_data = { |
| 80 | .irq_base = irq_pin(0), /* IRQ0 -> IRQ31 */ | 78 | .irq_base = irq_pin(0), /* IRQ0 -> IRQ31 */ |
| @@ -192,12 +190,12 @@ static struct resource cmt10_resources[] = { | |||
| 192 | 190 | ||
| 193 | void __init r8a73a4_add_dt_devices(void) | 191 | void __init r8a73a4_add_dt_devices(void) |
| 194 | { | 192 | { |
| 195 | r8a73a4_register_scif(SCIFA0); | 193 | r8a73a4_register_scif(0); |
| 196 | r8a73a4_register_scif(SCIFA1); | 194 | r8a73a4_register_scif(1); |
| 197 | r8a73a4_register_scif(SCIFB0); | 195 | r8a73a4_register_scif(2); |
| 198 | r8a73a4_register_scif(SCIFB1); | 196 | r8a73a4_register_scif(3); |
| 199 | r8a73a4_register_scif(SCIFB2); | 197 | r8a73a4_register_scif(4); |
| 200 | r8a73a4_register_scif(SCIFB3); | 198 | r8a73a4_register_scif(5); |
| 201 | r8a7790_register_cmt(10); | 199 | r8a7790_register_cmt(10); |
| 202 | } | 200 | } |
| 203 | 201 | ||
| @@ -275,7 +273,7 @@ static const struct sh_dmae_pdata dma_pdata = { | |||
| 275 | 273 | ||
| 276 | static struct resource dma_resources[] = { | 274 | static struct resource dma_resources[] = { |
| 277 | DEFINE_RES_MEM(0xe6700020, 0x89e0), | 275 | DEFINE_RES_MEM(0xe6700020, 0x89e0), |
| 278 | DEFINE_RES_IRQ_NAMED(gic_spi(220), "error_irq"), | 276 | DEFINE_RES_IRQ(gic_spi(220)), |
| 279 | { | 277 | { |
| 280 | /* IRQ for channels 0-19 */ | 278 | /* IRQ for channels 0-19 */ |
| 281 | .start = gic_spi(200), | 279 | .start = gic_spi(200), |
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c index b7d4b2c3bc29..8f3c68101d59 100644 --- a/arch/arm/mach-shmobile/setup-r8a7740.c +++ b/arch/arm/mach-shmobile/setup-r8a7740.c | |||
| @@ -203,167 +203,38 @@ static struct platform_device irqpin3_device = { | |||
| 203 | }, | 203 | }, |
| 204 | }; | 204 | }; |
| 205 | 205 | ||
| 206 | /* SCIFA0 */ | 206 | /* SCIF */ |
| 207 | static struct plat_sci_port scif0_platform_data = { | 207 | #define R8A7740_SCIF(scif_type, index, baseaddr, irq) \ |
| 208 | .mapbase = 0xe6c40000, | 208 | static struct plat_sci_port scif##index##_platform_data = { \ |
| 209 | .flags = UPF_BOOT_AUTOCONF, | 209 | .type = scif_type, \ |
| 210 | .scscr = SCSCR_RE | SCSCR_TE, | 210 | .flags = UPF_BOOT_AUTOCONF, \ |
| 211 | .scbrr_algo_id = SCBRR_ALGO_4, | 211 | .scscr = SCSCR_RE | SCSCR_TE, \ |
| 212 | .type = PORT_SCIFA, | 212 | }; \ |
| 213 | .irqs = SCIx_IRQ_MUXED(gic_spi(100)), | 213 | \ |
| 214 | }; | 214 | static struct resource scif##index##_resources[] = { \ |
| 215 | 215 | DEFINE_RES_MEM(baseaddr, 0x100), \ | |
| 216 | static struct platform_device scif0_device = { | 216 | DEFINE_RES_IRQ(irq), \ |
| 217 | .name = "sh-sci", | 217 | }; \ |
| 218 | .id = 0, | 218 | \ |
| 219 | .dev = { | 219 | static struct platform_device scif##index##_device = { \ |
| 220 | .platform_data = &scif0_platform_data, | 220 | .name = "sh-sci", \ |
| 221 | }, | 221 | .id = index, \ |
| 222 | }; | 222 | .resource = scif##index##_resources, \ |
| 223 | 223 | .num_resources = ARRAY_SIZE(scif##index##_resources), \ | |
| 224 | /* SCIFA1 */ | 224 | .dev = { \ |
| 225 | static struct plat_sci_port scif1_platform_data = { | 225 | .platform_data = &scif##index##_platform_data, \ |
| 226 | .mapbase = 0xe6c50000, | 226 | }, \ |
| 227 | .flags = UPF_BOOT_AUTOCONF, | 227 | } |
| 228 | .scscr = SCSCR_RE | SCSCR_TE, | ||
| 229 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
| 230 | .type = PORT_SCIFA, | ||
| 231 | .irqs = SCIx_IRQ_MUXED(gic_spi(101)), | ||
| 232 | }; | ||
| 233 | |||
| 234 | static struct platform_device scif1_device = { | ||
| 235 | .name = "sh-sci", | ||
| 236 | .id = 1, | ||
| 237 | .dev = { | ||
| 238 | .platform_data = &scif1_platform_data, | ||
| 239 | }, | ||
| 240 | }; | ||
| 241 | |||
| 242 | /* SCIFA2 */ | ||
| 243 | static struct plat_sci_port scif2_platform_data = { | ||
| 244 | .mapbase = 0xe6c60000, | ||
| 245 | .flags = UPF_BOOT_AUTOCONF, | ||
| 246 | .scscr = SCSCR_RE | SCSCR_TE, | ||
| 247 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
| 248 | .type = PORT_SCIFA, | ||
| 249 | .irqs = SCIx_IRQ_MUXED(gic_spi(102)), | ||
| 250 | }; | ||
| 251 | |||
| 252 | static struct platform_device scif2_device = { | ||
| 253 | .name = "sh-sci", | ||
| 254 | .id = 2, | ||
| 255 | .dev = { | ||
| 256 | .platform_data = &scif2_platform_data, | ||
| 257 | }, | ||
| 258 | }; | ||
| 259 | |||
| 260 | /* SCIFA3 */ | ||
| 261 | static struct plat_sci_port scif3_platform_data = { | ||
| 262 | .mapbase = 0xe6c70000, | ||
| 263 | .flags = UPF_BOOT_AUTOCONF, | ||
| 264 | .scscr = SCSCR_RE | SCSCR_TE, | ||
| 265 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
| 266 | .type = PORT_SCIFA, | ||
| 267 | .irqs = SCIx_IRQ_MUXED(gic_spi(103)), | ||
| 268 | }; | ||
| 269 | |||
| 270 | static struct platform_device scif3_device = { | ||
| 271 | .name = "sh-sci", | ||
| 272 | .id = 3, | ||
| 273 | .dev = { | ||
| 274 | .platform_data = &scif3_platform_data, | ||
| 275 | }, | ||
| 276 | }; | ||
| 277 | |||
| 278 | /* SCIFA4 */ | ||
| 279 | static struct plat_sci_port scif4_platform_data = { | ||
| 280 | .mapbase = 0xe6c80000, | ||
| 281 | .flags = UPF_BOOT_AUTOCONF, | ||
| 282 | .scscr = SCSCR_RE | SCSCR_TE, | ||
| 283 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
| 284 | .type = PORT_SCIFA, | ||
| 285 | .irqs = SCIx_IRQ_MUXED(gic_spi(104)), | ||
| 286 | }; | ||
| 287 | |||
| 288 | static struct platform_device scif4_device = { | ||
| 289 | .name = "sh-sci", | ||
| 290 | .id = 4, | ||
| 291 | .dev = { | ||
| 292 | .platform_data = &scif4_platform_data, | ||
| 293 | }, | ||
| 294 | }; | ||
| 295 | |||
| 296 | /* SCIFA5 */ | ||
| 297 | static struct plat_sci_port scif5_platform_data = { | ||
| 298 | .mapbase = 0xe6cb0000, | ||
| 299 | .flags = UPF_BOOT_AUTOCONF, | ||
| 300 | .scscr = SCSCR_RE | SCSCR_TE, | ||
| 301 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
| 302 | .type = PORT_SCIFA, | ||
| 303 | .irqs = SCIx_IRQ_MUXED(gic_spi(105)), | ||
| 304 | }; | ||
| 305 | |||
| 306 | static struct platform_device scif5_device = { | ||
| 307 | .name = "sh-sci", | ||
| 308 | .id = 5, | ||
| 309 | .dev = { | ||
| 310 | .platform_data = &scif5_platform_data, | ||
| 311 | }, | ||
| 312 | }; | ||
| 313 | |||
| 314 | /* SCIFA6 */ | ||
| 315 | static struct plat_sci_port scif6_platform_data = { | ||
| 316 | .mapbase = 0xe6cc0000, | ||
| 317 | .flags = UPF_BOOT_AUTOCONF, | ||
| 318 | .scscr = SCSCR_RE | SCSCR_TE, | ||
| 319 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
| 320 | .type = PORT_SCIFA, | ||
| 321 | .irqs = SCIx_IRQ_MUXED(gic_spi(106)), | ||
| 322 | }; | ||
| 323 | |||
| 324 | static struct platform_device scif6_device = { | ||
| 325 | .name = "sh-sci", | ||
| 326 | .id = 6, | ||
| 327 | .dev = { | ||
| 328 | .platform_data = &scif6_platform_data, | ||
| 329 | }, | ||
| 330 | }; | ||
| 331 | |||
| 332 | /* SCIFA7 */ | ||
| 333 | static struct plat_sci_port scif7_platform_data = { | ||
| 334 | .mapbase = 0xe6cd0000, | ||
| 335 | .flags = UPF_BOOT_AUTOCONF, | ||
| 336 | .scscr = SCSCR_RE | SCSCR_TE, | ||
| 337 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
| 338 | .type = PORT_SCIFA, | ||
| 339 | .irqs = SCIx_IRQ_MUXED(gic_spi(107)), | ||
| 340 | }; | ||
| 341 | |||
| 342 | static struct platform_device scif7_device = { | ||
| 343 | .name = "sh-sci", | ||
| 344 | .id = 7, | ||
| 345 | .dev = { | ||
| 346 | .platform_data = &scif7_platform_data, | ||
| 347 | }, | ||
| 348 | }; | ||
| 349 | |||
| 350 | /* SCIFB */ | ||
| 351 | static struct plat_sci_port scifb_platform_data = { | ||
| 352 | .mapbase = 0xe6c30000, | ||
| 353 | .flags = UPF_BOOT_AUTOCONF, | ||
| 354 | .scscr = SCSCR_RE | SCSCR_TE, | ||
| 355 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
| 356 | .type = PORT_SCIFB, | ||
| 357 | .irqs = SCIx_IRQ_MUXED(gic_spi(108)), | ||
| 358 | }; | ||
| 359 | 228 | ||
| 360 | static struct platform_device scifb_device = { | 229 | R8A7740_SCIF(PORT_SCIFA, 0, 0xe6c40000, gic_spi(100)); |
| 361 | .name = "sh-sci", | 230 | R8A7740_SCIF(PORT_SCIFA, 1, 0xe6c50000, gic_spi(101)); |
| 362 | .id = 8, | 231 | R8A7740_SCIF(PORT_SCIFA, 2, 0xe6c60000, gic_spi(102)); |
| 363 | .dev = { | 232 | R8A7740_SCIF(PORT_SCIFA, 3, 0xe6c70000, gic_spi(103)); |
| 364 | .platform_data = &scifb_platform_data, | 233 | R8A7740_SCIF(PORT_SCIFA, 4, 0xe6c80000, gic_spi(104)); |
| 365 | }, | 234 | R8A7740_SCIF(PORT_SCIFA, 5, 0xe6cb0000, gic_spi(105)); |
| 366 | }; | 235 | R8A7740_SCIF(PORT_SCIFA, 6, 0xe6cc0000, gic_spi(106)); |
| 236 | R8A7740_SCIF(PORT_SCIFA, 7, 0xe6cd0000, gic_spi(107)); | ||
| 237 | R8A7740_SCIF(PORT_SCIFB, 8, 0xe6c30000, gic_spi(108)); | ||
| 367 | 238 | ||
| 368 | /* CMT */ | 239 | /* CMT */ |
| 369 | static struct sh_timer_config cmt10_platform_data = { | 240 | static struct sh_timer_config cmt10_platform_data = { |
| @@ -528,7 +399,7 @@ static struct platform_device *r8a7740_devices_dt[] __initdata = { | |||
| 528 | &scif5_device, | 399 | &scif5_device, |
| 529 | &scif6_device, | 400 | &scif6_device, |
| 530 | &scif7_device, | 401 | &scif7_device, |
| 531 | &scifb_device, | 402 | &scif8_device, |
| 532 | &cmt10_device, | 403 | &cmt10_device, |
| 533 | }; | 404 | }; |
| 534 | 405 | ||
| @@ -981,7 +852,7 @@ void __init r8a7740_add_standard_devices(void) | |||
| 981 | rmobile_add_device_to_domain("A3SP", &scif5_device); | 852 | rmobile_add_device_to_domain("A3SP", &scif5_device); |
| 982 | rmobile_add_device_to_domain("A3SP", &scif6_device); | 853 | rmobile_add_device_to_domain("A3SP", &scif6_device); |
| 983 | rmobile_add_device_to_domain("A3SP", &scif7_device); | 854 | rmobile_add_device_to_domain("A3SP", &scif7_device); |
| 984 | rmobile_add_device_to_domain("A3SP", &scifb_device); | 855 | rmobile_add_device_to_domain("A3SP", &scif8_device); |
| 985 | rmobile_add_device_to_domain("A3SP", &i2c1_device); | 856 | rmobile_add_device_to_domain("A3SP", &i2c1_device); |
| 986 | } | 857 | } |
| 987 | 858 | ||
diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c index 03fcc5974ef9..6d694526e4ca 100644 --- a/arch/arm/mach-shmobile/setup-r8a7778.c +++ b/arch/arm/mach-shmobile/setup-r8a7778.c | |||
| @@ -44,24 +44,31 @@ | |||
| 44 | #include <asm/hardware/cache-l2x0.h> | 44 | #include <asm/hardware/cache-l2x0.h> |
| 45 | 45 | ||
| 46 | /* SCIF */ | 46 | /* SCIF */ |
| 47 | #define SCIF_INFO(baseaddr, irq) \ | 47 | #define R8A7778_SCIF(index, baseaddr, irq) \ |
| 48 | { \ | 48 | static struct plat_sci_port scif##index##_platform_data = { \ |
| 49 | .mapbase = baseaddr, \ | ||
| 50 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ | 49 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ |
| 51 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \ | 50 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \ |
| 52 | .scbrr_algo_id = SCBRR_ALGO_2, \ | ||
| 53 | .type = PORT_SCIF, \ | 51 | .type = PORT_SCIF, \ |
| 54 | .irqs = SCIx_IRQ_MUXED(irq), \ | 52 | }; \ |
| 53 | \ | ||
| 54 | static struct resource scif##index##_resources[] = { \ | ||
| 55 | DEFINE_RES_MEM(baseaddr, 0x100), \ | ||
| 56 | DEFINE_RES_IRQ(irq), \ | ||
| 55 | } | 57 | } |
| 56 | 58 | ||
| 57 | static struct plat_sci_port scif_platform_data[] __initdata = { | 59 | R8A7778_SCIF(0, 0xffe40000, gic_iid(0x66)); |
| 58 | SCIF_INFO(0xffe40000, gic_iid(0x66)), | 60 | R8A7778_SCIF(1, 0xffe41000, gic_iid(0x67)); |
| 59 | SCIF_INFO(0xffe41000, gic_iid(0x67)), | 61 | R8A7778_SCIF(2, 0xffe42000, gic_iid(0x68)); |
| 60 | SCIF_INFO(0xffe42000, gic_iid(0x68)), | 62 | R8A7778_SCIF(3, 0xffe43000, gic_iid(0x69)); |
| 61 | SCIF_INFO(0xffe43000, gic_iid(0x69)), | 63 | R8A7778_SCIF(4, 0xffe44000, gic_iid(0x6a)); |
| 62 | SCIF_INFO(0xffe44000, gic_iid(0x6a)), | 64 | R8A7778_SCIF(5, 0xffe45000, gic_iid(0x6b)); |
| 63 | SCIF_INFO(0xffe45000, gic_iid(0x6b)), | 65 | |
| 64 | }; | 66 | #define r8a7778_register_scif(index) \ |
| 67 | platform_device_register_resndata(&platform_bus, "sh-sci", index, \ | ||
| 68 | scif##index##_resources, \ | ||
| 69 | ARRAY_SIZE(scif##index##_resources), \ | ||
| 70 | &scif##index##_platform_data, \ | ||
| 71 | sizeof(scif##index##_platform_data)) | ||
| 65 | 72 | ||
| 66 | /* TMU */ | 73 | /* TMU */ |
| 67 | static struct resource sh_tmu0_resources[] __initdata = { | 74 | static struct resource sh_tmu0_resources[] __initdata = { |
| @@ -287,8 +294,6 @@ static void __init r8a7778_register_hspi(int id) | |||
| 287 | 294 | ||
| 288 | void __init r8a7778_add_dt_devices(void) | 295 | void __init r8a7778_add_dt_devices(void) |
| 289 | { | 296 | { |
| 290 | int i; | ||
| 291 | |||
| 292 | #ifdef CONFIG_CACHE_L2X0 | 297 | #ifdef CONFIG_CACHE_L2X0 |
| 293 | void __iomem *base = ioremap_nocache(0xf0100000, 0x1000); | 298 | void __iomem *base = ioremap_nocache(0xf0100000, 0x1000); |
| 294 | if (base) { | 299 | if (base) { |
| @@ -300,11 +305,12 @@ void __init r8a7778_add_dt_devices(void) | |||
| 300 | } | 305 | } |
| 301 | #endif | 306 | #endif |
| 302 | 307 | ||
| 303 | for (i = 0; i < ARRAY_SIZE(scif_platform_data); i++) | 308 | r8a7778_register_scif(0); |
| 304 | platform_device_register_data(&platform_bus, "sh-sci", i, | 309 | r8a7778_register_scif(1); |
| 305 | &scif_platform_data[i], | 310 | r8a7778_register_scif(2); |
| 306 | sizeof(struct plat_sci_port)); | 311 | r8a7778_register_scif(3); |
| 307 | 312 | r8a7778_register_scif(4); | |
| 313 | r8a7778_register_scif(5); | ||
| 308 | r8a7778_register_tmu(0); | 314 | r8a7778_register_tmu(0); |
| 309 | r8a7778_register_tmu(1); | 315 | r8a7778_register_tmu(1); |
| 310 | } | 316 | } |
| @@ -319,6 +325,52 @@ void __init r8a7778_add_dt_devices(void) | |||
| 319 | #define HPB_DMAE_ASYNCMDR_ASMD21_SINGLE BIT(1) /* SDHI0 */ | 325 | #define HPB_DMAE_ASYNCMDR_ASMD21_SINGLE BIT(1) /* SDHI0 */ |
| 320 | #define HPB_DMAE_ASYNCMDR_ASMD21_MULTI 0 /* SDHI0 */ | 326 | #define HPB_DMAE_ASYNCMDR_ASMD21_MULTI 0 /* SDHI0 */ |
| 321 | 327 | ||
| 328 | #define HPBDMA_SSI(_id) \ | ||
| 329 | { \ | ||
| 330 | .id = HPBDMA_SLAVE_SSI## _id ##_TX, \ | ||
| 331 | .addr = 0xffd91008 + (_id * 0x40), \ | ||
| 332 | .dcr = HPB_DMAE_DCR_CT | \ | ||
| 333 | HPB_DMAE_DCR_DIP | \ | ||
| 334 | HPB_DMAE_DCR_SPDS_32BIT | \ | ||
| 335 | HPB_DMAE_DCR_DMDL | \ | ||
| 336 | HPB_DMAE_DCR_DPDS_32BIT, \ | ||
| 337 | .port = _id + (_id << 8), \ | ||
| 338 | .dma_ch = (28 + _id), \ | ||
| 339 | }, { \ | ||
| 340 | .id = HPBDMA_SLAVE_SSI## _id ##_RX, \ | ||
| 341 | .addr = 0xffd9100c + (_id * 0x40), \ | ||
| 342 | .dcr = HPB_DMAE_DCR_CT | \ | ||
| 343 | HPB_DMAE_DCR_DIP | \ | ||
| 344 | HPB_DMAE_DCR_SMDL | \ | ||
| 345 | HPB_DMAE_DCR_SPDS_32BIT | \ | ||
| 346 | HPB_DMAE_DCR_DPDS_32BIT, \ | ||
| 347 | .port = _id + (_id << 8), \ | ||
| 348 | .dma_ch = (28 + _id), \ | ||
| 349 | } | ||
| 350 | |||
| 351 | #define HPBDMA_HPBIF(_id) \ | ||
| 352 | { \ | ||
| 353 | .id = HPBDMA_SLAVE_HPBIF## _id ##_TX, \ | ||
| 354 | .addr = 0xffda0000 + (_id * 0x1000), \ | ||
| 355 | .dcr = HPB_DMAE_DCR_CT | \ | ||
| 356 | HPB_DMAE_DCR_DIP | \ | ||
| 357 | HPB_DMAE_DCR_SPDS_32BIT | \ | ||
| 358 | HPB_DMAE_DCR_DMDL | \ | ||
| 359 | HPB_DMAE_DCR_DPDS_32BIT, \ | ||
| 360 | .port = 0x1111, \ | ||
| 361 | .dma_ch = (28 + _id), \ | ||
| 362 | }, { \ | ||
| 363 | .id = HPBDMA_SLAVE_HPBIF## _id ##_RX, \ | ||
| 364 | .addr = 0xffda0000 + (_id * 0x1000), \ | ||
| 365 | .dcr = HPB_DMAE_DCR_CT | \ | ||
| 366 | HPB_DMAE_DCR_DIP | \ | ||
| 367 | HPB_DMAE_DCR_SMDL | \ | ||
| 368 | HPB_DMAE_DCR_SPDS_32BIT | \ | ||
| 369 | HPB_DMAE_DCR_DPDS_32BIT, \ | ||
| 370 | .port = 0x1111, \ | ||
| 371 | .dma_ch = (28 + _id), \ | ||
| 372 | } | ||
| 373 | |||
| 322 | static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = { | 374 | static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = { |
| 323 | { | 375 | { |
| 324 | .id = HPBDMA_SLAVE_SDHI0_TX, | 376 | .id = HPBDMA_SLAVE_SDHI0_TX, |
| @@ -348,12 +400,86 @@ static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = { | |||
| 348 | .port = 0x0D0C, | 400 | .port = 0x0D0C, |
| 349 | .flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE, | 401 | .flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE, |
| 350 | .dma_ch = 22, | 402 | .dma_ch = 22, |
| 403 | }, { | ||
| 404 | .id = HPBDMA_SLAVE_USBFUNC_TX, /* for D0 */ | ||
| 405 | .addr = 0xffe60018, | ||
| 406 | .dcr = HPB_DMAE_DCR_SPDS_32BIT | | ||
| 407 | HPB_DMAE_DCR_DMDL | | ||
| 408 | HPB_DMAE_DCR_DPDS_32BIT, | ||
| 409 | .port = 0x0000, | ||
| 410 | .dma_ch = 14, | ||
| 411 | }, { | ||
| 412 | .id = HPBDMA_SLAVE_USBFUNC_RX, /* for D1 */ | ||
| 413 | .addr = 0xffe6001c, | ||
| 414 | .dcr = HPB_DMAE_DCR_SMDL | | ||
| 415 | HPB_DMAE_DCR_SPDS_32BIT | | ||
| 416 | HPB_DMAE_DCR_DPDS_32BIT, | ||
| 417 | .port = 0x0101, | ||
| 418 | .dma_ch = 15, | ||
| 351 | }, | 419 | }, |
| 420 | |||
| 421 | HPBDMA_SSI(0), | ||
| 422 | HPBDMA_SSI(1), | ||
| 423 | HPBDMA_SSI(2), | ||
| 424 | HPBDMA_SSI(3), | ||
| 425 | HPBDMA_SSI(4), | ||
| 426 | HPBDMA_SSI(5), | ||
| 427 | HPBDMA_SSI(6), | ||
| 428 | HPBDMA_SSI(7), | ||
| 429 | HPBDMA_SSI(8), | ||
| 430 | |||
| 431 | HPBDMA_HPBIF(0), | ||
| 432 | HPBDMA_HPBIF(1), | ||
| 433 | HPBDMA_HPBIF(2), | ||
| 434 | HPBDMA_HPBIF(3), | ||
| 435 | HPBDMA_HPBIF(4), | ||
| 436 | HPBDMA_HPBIF(5), | ||
| 437 | HPBDMA_HPBIF(6), | ||
| 438 | HPBDMA_HPBIF(7), | ||
| 439 | HPBDMA_HPBIF(8), | ||
| 352 | }; | 440 | }; |
| 353 | 441 | ||
| 354 | static const struct hpb_dmae_channel hpb_dmae_channels[] = { | 442 | static const struct hpb_dmae_channel hpb_dmae_channels[] = { |
| 443 | HPB_DMAE_CHANNEL(0x7c, HPBDMA_SLAVE_USBFUNC_TX), /* ch. 14 */ | ||
| 444 | HPB_DMAE_CHANNEL(0x7c, HPBDMA_SLAVE_USBFUNC_RX), /* ch. 15 */ | ||
| 355 | HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_TX), /* ch. 21 */ | 445 | HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_TX), /* ch. 21 */ |
| 356 | HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_RX), /* ch. 22 */ | 446 | HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_RX), /* ch. 22 */ |
| 447 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI0_TX), /* ch. 28 */ | ||
| 448 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI0_RX), /* ch. 28 */ | ||
| 449 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF0_TX), /* ch. 28 */ | ||
| 450 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF0_RX), /* ch. 28 */ | ||
| 451 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI1_TX), /* ch. 29 */ | ||
| 452 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI1_RX), /* ch. 29 */ | ||
| 453 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF1_TX), /* ch. 29 */ | ||
| 454 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF1_RX), /* ch. 29 */ | ||
| 455 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI2_TX), /* ch. 30 */ | ||
| 456 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI2_RX), /* ch. 30 */ | ||
| 457 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF2_TX), /* ch. 30 */ | ||
| 458 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF2_RX), /* ch. 30 */ | ||
| 459 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI3_TX), /* ch. 31 */ | ||
| 460 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI3_RX), /* ch. 31 */ | ||
| 461 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF3_TX), /* ch. 31 */ | ||
| 462 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF3_RX), /* ch. 31 */ | ||
| 463 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI4_TX), /* ch. 32 */ | ||
| 464 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI4_RX), /* ch. 32 */ | ||
| 465 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF4_TX), /* ch. 32 */ | ||
| 466 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF4_RX), /* ch. 32 */ | ||
| 467 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI5_TX), /* ch. 33 */ | ||
| 468 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI5_RX), /* ch. 33 */ | ||
| 469 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF5_TX), /* ch. 33 */ | ||
| 470 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF5_RX), /* ch. 33 */ | ||
| 471 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI6_TX), /* ch. 34 */ | ||
| 472 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI6_RX), /* ch. 34 */ | ||
| 473 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF6_TX), /* ch. 34 */ | ||
| 474 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF6_RX), /* ch. 34 */ | ||
| 475 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI7_TX), /* ch. 35 */ | ||
| 476 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI7_RX), /* ch. 35 */ | ||
| 477 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF7_TX), /* ch. 35 */ | ||
| 478 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF7_RX), /* ch. 35 */ | ||
| 479 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI8_TX), /* ch. 36 */ | ||
| 480 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI8_RX), /* ch. 36 */ | ||
| 481 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF8_TX), /* ch. 36 */ | ||
| 482 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF8_RX), /* ch. 36 */ | ||
| 357 | }; | 483 | }; |
| 358 | 484 | ||
| 359 | static struct hpb_dmae_pdata dma_platform_data __initdata = { | 485 | static struct hpb_dmae_pdata dma_platform_data __initdata = { |
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c index 13049e9d691c..339292e85838 100644 --- a/arch/arm/mach-shmobile/setup-r8a7779.c +++ b/arch/arm/mach-shmobile/setup-r8a7779.c | |||
| @@ -188,107 +188,35 @@ void __init r8a7779_pinmux_init(void) | |||
| 188 | ARRAY_SIZE(r8a7779_pinctrl_devices)); | 188 | ARRAY_SIZE(r8a7779_pinctrl_devices)); |
| 189 | } | 189 | } |
| 190 | 190 | ||
| 191 | static struct plat_sci_port scif0_platform_data = { | 191 | /* SCIF */ |
| 192 | .mapbase = 0xffe40000, | 192 | #define R8A7779_SCIF(index, baseaddr, irq) \ |
| 193 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, | 193 | static struct plat_sci_port scif##index##_platform_data = { \ |
| 194 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, | 194 | .type = PORT_SCIF, \ |
| 195 | .scbrr_algo_id = SCBRR_ALGO_2, | 195 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ |
| 196 | .type = PORT_SCIF, | 196 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \ |
| 197 | .irqs = SCIx_IRQ_MUXED(gic_iid(0x78)), | 197 | }; \ |
| 198 | }; | 198 | \ |
| 199 | 199 | static struct resource scif##index##_resources[] = { \ | |
| 200 | static struct platform_device scif0_device = { | 200 | DEFINE_RES_MEM(baseaddr, 0x100), \ |
| 201 | .name = "sh-sci", | 201 | DEFINE_RES_IRQ(irq), \ |
| 202 | .id = 0, | 202 | }; \ |
| 203 | .dev = { | 203 | \ |
| 204 | .platform_data = &scif0_platform_data, | 204 | static struct platform_device scif##index##_device = { \ |
| 205 | }, | 205 | .name = "sh-sci", \ |
| 206 | }; | 206 | .id = index, \ |
| 207 | 207 | .resource = scif##index##_resources, \ | |
| 208 | static struct plat_sci_port scif1_platform_data = { | 208 | .num_resources = ARRAY_SIZE(scif##index##_resources), \ |
| 209 | .mapbase = 0xffe41000, | 209 | .dev = { \ |
| 210 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, | 210 | .platform_data = &scif##index##_platform_data, \ |
| 211 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, | 211 | }, \ |
| 212 | .scbrr_algo_id = SCBRR_ALGO_2, | 212 | } |
| 213 | .type = PORT_SCIF, | ||
| 214 | .irqs = SCIx_IRQ_MUXED(gic_iid(0x79)), | ||
| 215 | }; | ||
| 216 | |||
| 217 | static struct platform_device scif1_device = { | ||
| 218 | .name = "sh-sci", | ||
| 219 | .id = 1, | ||
| 220 | .dev = { | ||
| 221 | .platform_data = &scif1_platform_data, | ||
| 222 | }, | ||
| 223 | }; | ||
| 224 | |||
| 225 | static struct plat_sci_port scif2_platform_data = { | ||
| 226 | .mapbase = 0xffe42000, | ||
| 227 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, | ||
| 228 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, | ||
| 229 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 230 | .type = PORT_SCIF, | ||
| 231 | .irqs = SCIx_IRQ_MUXED(gic_iid(0x7a)), | ||
| 232 | }; | ||
| 233 | |||
| 234 | static struct platform_device scif2_device = { | ||
| 235 | .name = "sh-sci", | ||
| 236 | .id = 2, | ||
| 237 | .dev = { | ||
| 238 | .platform_data = &scif2_platform_data, | ||
| 239 | }, | ||
| 240 | }; | ||
| 241 | |||
| 242 | static struct plat_sci_port scif3_platform_data = { | ||
| 243 | .mapbase = 0xffe43000, | ||
| 244 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, | ||
| 245 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, | ||
| 246 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 247 | .type = PORT_SCIF, | ||
| 248 | .irqs = SCIx_IRQ_MUXED(gic_iid(0x7b)), | ||
| 249 | }; | ||
| 250 | |||
| 251 | static struct platform_device scif3_device = { | ||
| 252 | .name = "sh-sci", | ||
| 253 | .id = 3, | ||
| 254 | .dev = { | ||
| 255 | .platform_data = &scif3_platform_data, | ||
| 256 | }, | ||
| 257 | }; | ||
| 258 | |||
| 259 | static struct plat_sci_port scif4_platform_data = { | ||
| 260 | .mapbase = 0xffe44000, | ||
| 261 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, | ||
| 262 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, | ||
| 263 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 264 | .type = PORT_SCIF, | ||
| 265 | .irqs = SCIx_IRQ_MUXED(gic_iid(0x7c)), | ||
| 266 | }; | ||
| 267 | |||
| 268 | static struct platform_device scif4_device = { | ||
| 269 | .name = "sh-sci", | ||
| 270 | .id = 4, | ||
| 271 | .dev = { | ||
| 272 | .platform_data = &scif4_platform_data, | ||
| 273 | }, | ||
| 274 | }; | ||
| 275 | |||
| 276 | static struct plat_sci_port scif5_platform_data = { | ||
| 277 | .mapbase = 0xffe45000, | ||
| 278 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, | ||
| 279 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, | ||
| 280 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 281 | .type = PORT_SCIF, | ||
| 282 | .irqs = SCIx_IRQ_MUXED(gic_iid(0x7d)), | ||
| 283 | }; | ||
| 284 | 213 | ||
| 285 | static struct platform_device scif5_device = { | 214 | R8A7779_SCIF(0, 0xffe40000, gic_iid(0x78)); |
| 286 | .name = "sh-sci", | 215 | R8A7779_SCIF(1, 0xffe41000, gic_iid(0x79)); |
| 287 | .id = 5, | 216 | R8A7779_SCIF(2, 0xffe42000, gic_iid(0x7a)); |
| 288 | .dev = { | 217 | R8A7779_SCIF(3, 0xffe43000, gic_iid(0x7b)); |
| 289 | .platform_data = &scif5_platform_data, | 218 | R8A7779_SCIF(4, 0xffe44000, gic_iid(0x7c)); |
| 290 | }, | 219 | R8A7779_SCIF(5, 0xffe45000, gic_iid(0x7d)); |
| 291 | }; | ||
| 292 | 220 | ||
| 293 | /* TMU */ | 221 | /* TMU */ |
| 294 | static struct sh_timer_config tmu00_platform_data = { | 222 | static struct sh_timer_config tmu00_platform_data = { |
diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c index c47bcebbcb00..66476d21544d 100644 --- a/arch/arm/mach-shmobile/setup-r8a7790.c +++ b/arch/arm/mach-shmobile/setup-r8a7790.c | |||
| @@ -63,6 +63,27 @@ R8A7790_GPIO(5); | |||
| 63 | &r8a7790_gpio##idx##_platform_data, \ | 63 | &r8a7790_gpio##idx##_platform_data, \ |
| 64 | sizeof(r8a7790_gpio##idx##_platform_data)) | 64 | sizeof(r8a7790_gpio##idx##_platform_data)) |
| 65 | 65 | ||
| 66 | static struct resource i2c_resources[] __initdata = { | ||
| 67 | /* I2C0 */ | ||
| 68 | DEFINE_RES_MEM(0xE6508000, 0x40), | ||
| 69 | DEFINE_RES_IRQ(gic_spi(287)), | ||
| 70 | /* I2C1 */ | ||
| 71 | DEFINE_RES_MEM(0xE6518000, 0x40), | ||
| 72 | DEFINE_RES_IRQ(gic_spi(288)), | ||
| 73 | /* I2C2 */ | ||
| 74 | DEFINE_RES_MEM(0xE6530000, 0x40), | ||
| 75 | DEFINE_RES_IRQ(gic_spi(286)), | ||
| 76 | /* I2C3 */ | ||
| 77 | DEFINE_RES_MEM(0xE6540000, 0x40), | ||
| 78 | DEFINE_RES_IRQ(gic_spi(290)), | ||
| 79 | |||
| 80 | }; | ||
| 81 | |||
| 82 | #define r8a7790_register_i2c(idx) \ | ||
| 83 | platform_device_register_simple( \ | ||
| 84 | "i2c-rcar", idx, \ | ||
| 85 | i2c_resources + (2 * idx), 2); \ | ||
| 86 | |||
| 66 | void __init r8a7790_pinmux_init(void) | 87 | void __init r8a7790_pinmux_init(void) |
| 67 | { | 88 | { |
| 68 | platform_device_register_simple("pfc-r8a7790", -1, pfc_resources, | 89 | platform_device_register_simple("pfc-r8a7790", -1, pfc_resources, |
| @@ -73,63 +94,57 @@ void __init r8a7790_pinmux_init(void) | |||
| 73 | r8a7790_register_gpio(3); | 94 | r8a7790_register_gpio(3); |
| 74 | r8a7790_register_gpio(4); | 95 | r8a7790_register_gpio(4); |
| 75 | r8a7790_register_gpio(5); | 96 | r8a7790_register_gpio(5); |
| 97 | r8a7790_register_i2c(0); | ||
| 98 | r8a7790_register_i2c(1); | ||
| 99 | r8a7790_register_i2c(2); | ||
| 100 | r8a7790_register_i2c(3); | ||
| 76 | } | 101 | } |
| 77 | 102 | ||
| 78 | #define SCIF_COMMON(scif_type, baseaddr, irq) \ | 103 | #define __R8A7790_SCIF(scif_type, _scscr, index, baseaddr, irq) \ |
| 79 | .type = scif_type, \ | 104 | static struct plat_sci_port scif##index##_platform_data = { \ |
| 80 | .mapbase = baseaddr, \ | 105 | .type = scif_type, \ |
| 81 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ | 106 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ |
| 82 | .irqs = SCIx_IRQ_MUXED(irq) | 107 | .scscr = _scscr, \ |
| 83 | 108 | }; \ | |
| 84 | #define SCIFA_DATA(index, baseaddr, irq) \ | 109 | \ |
| 85 | [index] = { \ | 110 | static struct resource scif##index##_resources[] = { \ |
| 86 | SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \ | 111 | DEFINE_RES_MEM(baseaddr, 0x100), \ |
| 87 | .scbrr_algo_id = SCBRR_ALGO_4, \ | 112 | DEFINE_RES_IRQ(irq), \ |
| 88 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \ | ||
| 89 | } | ||
| 90 | |||
| 91 | #define SCIFB_DATA(index, baseaddr, irq) \ | ||
| 92 | [index] = { \ | ||
| 93 | SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \ | ||
| 94 | .scbrr_algo_id = SCBRR_ALGO_4, \ | ||
| 95 | .scscr = SCSCR_RE | SCSCR_TE, \ | ||
| 96 | } | ||
| 97 | |||
| 98 | #define SCIF_DATA(index, baseaddr, irq) \ | ||
| 99 | [index] = { \ | ||
| 100 | SCIF_COMMON(PORT_SCIF, baseaddr, irq), \ | ||
| 101 | .scbrr_algo_id = SCBRR_ALGO_2, \ | ||
| 102 | .scscr = SCSCR_RE | SCSCR_TE, \ | ||
| 103 | } | ||
| 104 | |||
| 105 | #define HSCIF_DATA(index, baseaddr, irq) \ | ||
| 106 | [index] = { \ | ||
| 107 | SCIF_COMMON(PORT_HSCIF, baseaddr, irq), \ | ||
| 108 | .scbrr_algo_id = SCBRR_ALGO_6, \ | ||
| 109 | .scscr = SCSCR_RE | SCSCR_TE, \ | ||
| 110 | } | 113 | } |
| 111 | 114 | ||
| 112 | enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1, | 115 | #define R8A7790_SCIF(index, baseaddr, irq) \ |
| 113 | HSCIF0, HSCIF1 }; | 116 | __R8A7790_SCIF(PORT_SCIF, SCSCR_RE | SCSCR_TE, \ |
| 114 | 117 | index, baseaddr, irq) | |
| 115 | static const struct plat_sci_port scif[] __initconst = { | 118 | |
| 116 | SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */ | 119 | #define R8A7790_SCIFA(index, baseaddr, irq) \ |
| 117 | SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */ | 120 | __R8A7790_SCIF(PORT_SCIFA, SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \ |
| 118 | SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */ | 121 | index, baseaddr, irq) |
| 119 | SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */ | 122 | |
| 120 | SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */ | 123 | #define R8A7790_SCIFB(index, baseaddr, irq) \ |
| 121 | SCIFA_DATA(SCIFA2, 0xe6c60000, gic_spi(151)), /* SCIFA2 */ | 124 | __R8A7790_SCIF(PORT_SCIFB, SCSCR_RE | SCSCR_TE, \ |
| 122 | SCIF_DATA(SCIF0, 0xe6e60000, gic_spi(152)), /* SCIF0 */ | 125 | index, baseaddr, irq) |
| 123 | SCIF_DATA(SCIF1, 0xe6e68000, gic_spi(153)), /* SCIF1 */ | 126 | |
| 124 | HSCIF_DATA(HSCIF0, 0xe62c0000, gic_spi(154)), /* HSCIF0 */ | 127 | #define R8A7790_HSCIF(index, baseaddr, irq) \ |
| 125 | HSCIF_DATA(HSCIF1, 0xe62c8000, gic_spi(155)), /* HSCIF1 */ | 128 | __R8A7790_SCIF(PORT_HSCIF, SCSCR_RE | SCSCR_TE, \ |
| 126 | }; | 129 | index, baseaddr, irq) |
| 127 | 130 | ||
| 128 | static inline void r8a7790_register_scif(int idx) | 131 | R8A7790_SCIFA(0, 0xe6c40000, gic_spi(144)); /* SCIFA0 */ |
| 129 | { | 132 | R8A7790_SCIFA(1, 0xe6c50000, gic_spi(145)); /* SCIFA1 */ |
| 130 | platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx], | 133 | R8A7790_SCIFB(2, 0xe6c20000, gic_spi(148)); /* SCIFB0 */ |
| 131 | sizeof(struct plat_sci_port)); | 134 | R8A7790_SCIFB(3, 0xe6c30000, gic_spi(149)); /* SCIFB1 */ |
| 132 | } | 135 | R8A7790_SCIFB(4, 0xe6ce0000, gic_spi(150)); /* SCIFB2 */ |
| 136 | R8A7790_SCIFA(5, 0xe6c60000, gic_spi(151)); /* SCIFA2 */ | ||
| 137 | R8A7790_SCIF(6, 0xe6e60000, gic_spi(152)); /* SCIF0 */ | ||
| 138 | R8A7790_SCIF(7, 0xe6e68000, gic_spi(153)); /* SCIF1 */ | ||
| 139 | R8A7790_HSCIF(8, 0xe62c0000, gic_spi(154)); /* HSCIF0 */ | ||
| 140 | R8A7790_HSCIF(9, 0xe62c8000, gic_spi(155)); /* HSCIF1 */ | ||
| 141 | |||
| 142 | #define r8a7790_register_scif(index) \ | ||
| 143 | platform_device_register_resndata(&platform_bus, "sh-sci", index, \ | ||
| 144 | scif##index##_resources, \ | ||
| 145 | ARRAY_SIZE(scif##index##_resources), \ | ||
| 146 | &scif##index##_platform_data, \ | ||
| 147 | sizeof(scif##index##_platform_data)) | ||
| 133 | 148 | ||
| 134 | static const struct renesas_irqc_config irqc0_data __initconst = { | 149 | static const struct renesas_irqc_config irqc0_data __initconst = { |
| 135 | .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ | 150 | .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ |
| @@ -182,16 +197,16 @@ static const struct resource cmt00_resources[] __initconst = { | |||
| 182 | 197 | ||
| 183 | void __init r8a7790_add_dt_devices(void) | 198 | void __init r8a7790_add_dt_devices(void) |
| 184 | { | 199 | { |
| 185 | r8a7790_register_scif(SCIFA0); | 200 | r8a7790_register_scif(0); |
| 186 | r8a7790_register_scif(SCIFA1); | 201 | r8a7790_register_scif(1); |
| 187 | r8a7790_register_scif(SCIFB0); | 202 | r8a7790_register_scif(2); |
| 188 | r8a7790_register_scif(SCIFB1); | 203 | r8a7790_register_scif(3); |
| 189 | r8a7790_register_scif(SCIFB2); | 204 | r8a7790_register_scif(4); |
| 190 | r8a7790_register_scif(SCIFA2); | 205 | r8a7790_register_scif(5); |
| 191 | r8a7790_register_scif(SCIF0); | 206 | r8a7790_register_scif(6); |
| 192 | r8a7790_register_scif(SCIF1); | 207 | r8a7790_register_scif(7); |
| 193 | r8a7790_register_scif(HSCIF0); | 208 | r8a7790_register_scif(8); |
| 194 | r8a7790_register_scif(HSCIF1); | 209 | r8a7790_register_scif(9); |
| 195 | r8a7790_register_cmt(00); | 210 | r8a7790_register_cmt(00); |
| 196 | } | 211 | } |
| 197 | 212 | ||
diff --git a/arch/arm/mach-shmobile/setup-r8a7791.c b/arch/arm/mach-shmobile/setup-r8a7791.c index d9393d61ee27..e28404e43860 100644 --- a/arch/arm/mach-shmobile/setup-r8a7791.c +++ b/arch/arm/mach-shmobile/setup-r8a7791.c | |||
| @@ -22,6 +22,7 @@ | |||
| 22 | #include <linux/irq.h> | 22 | #include <linux/irq.h> |
| 23 | #include <linux/kernel.h> | 23 | #include <linux/kernel.h> |
| 24 | #include <linux/of_platform.h> | 24 | #include <linux/of_platform.h> |
| 25 | #include <linux/platform_data/gpio-rcar.h> | ||
| 25 | #include <linux/platform_data/irq-renesas-irqc.h> | 26 | #include <linux/platform_data/irq-renesas-irqc.h> |
| 26 | #include <linux/serial_sci.h> | 27 | #include <linux/serial_sci.h> |
| 27 | #include <linux/sh_timer.h> | 28 | #include <linux/sh_timer.h> |
| @@ -31,66 +32,101 @@ | |||
| 31 | #include <mach/rcar-gen2.h> | 32 | #include <mach/rcar-gen2.h> |
| 32 | #include <asm/mach/arch.h> | 33 | #include <asm/mach/arch.h> |
| 33 | 34 | ||
| 34 | #define SCIF_COMMON(scif_type, baseaddr, irq) \ | 35 | static const struct resource pfc_resources[] __initconst = { |
| 35 | .type = scif_type, \ | 36 | DEFINE_RES_MEM(0xe6060000, 0x250), |
| 36 | .mapbase = baseaddr, \ | 37 | }; |
| 37 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ | ||
| 38 | .irqs = SCIx_IRQ_MUXED(irq) | ||
| 39 | |||
| 40 | #define SCIFA_DATA(index, baseaddr, irq) \ | ||
| 41 | [index] = { \ | ||
| 42 | SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \ | ||
| 43 | .scbrr_algo_id = SCBRR_ALGO_4, \ | ||
| 44 | .scscr = SCSCR_RE | SCSCR_TE, \ | ||
| 45 | } | ||
| 46 | |||
| 47 | #define SCIFB_DATA(index, baseaddr, irq) \ | ||
| 48 | [index] = { \ | ||
| 49 | SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \ | ||
| 50 | .scbrr_algo_id = SCBRR_ALGO_4, \ | ||
| 51 | .scscr = SCSCR_RE | SCSCR_TE, \ | ||
| 52 | } | ||
| 53 | 38 | ||
| 54 | #define SCIF_DATA(index, baseaddr, irq) \ | 39 | #define r8a7791_register_pfc() \ |
| 55 | [index] = { \ | 40 | platform_device_register_simple("pfc-r8a7791", -1, pfc_resources, \ |
| 56 | SCIF_COMMON(PORT_SCIF, baseaddr, irq), \ | 41 | ARRAY_SIZE(pfc_resources)) |
| 57 | .scbrr_algo_id = SCBRR_ALGO_2, \ | 42 | |
| 58 | .scscr = SCSCR_RE | SCSCR_TE, \ | 43 | #define R8A7791_GPIO(idx, base, nr) \ |
| 44 | static const struct resource r8a7791_gpio##idx##_resources[] __initconst = { \ | ||
| 45 | DEFINE_RES_MEM((base), 0x50), \ | ||
| 46 | DEFINE_RES_IRQ(gic_spi(4 + (idx))), \ | ||
| 47 | }; \ | ||
| 48 | \ | ||
| 49 | static const struct gpio_rcar_config \ | ||
| 50 | r8a7791_gpio##idx##_platform_data __initconst = { \ | ||
| 51 | .gpio_base = 32 * (idx), \ | ||
| 52 | .irq_base = 0, \ | ||
| 53 | .number_of_pins = (nr), \ | ||
| 54 | .pctl_name = "pfc-r8a7791", \ | ||
| 55 | .has_both_edge_trigger = 1, \ | ||
| 56 | }; \ | ||
| 57 | |||
| 58 | R8A7791_GPIO(0, 0xe6050000, 32); | ||
| 59 | R8A7791_GPIO(1, 0xe6051000, 32); | ||
| 60 | R8A7791_GPIO(2, 0xe6052000, 32); | ||
| 61 | R8A7791_GPIO(3, 0xe6053000, 32); | ||
| 62 | R8A7791_GPIO(4, 0xe6054000, 32); | ||
| 63 | R8A7791_GPIO(5, 0xe6055000, 32); | ||
| 64 | R8A7791_GPIO(6, 0xe6055400, 32); | ||
| 65 | R8A7791_GPIO(7, 0xe6055800, 26); | ||
| 66 | |||
| 67 | #define r8a7791_register_gpio(idx) \ | ||
| 68 | platform_device_register_resndata(&platform_bus, "gpio_rcar", idx, \ | ||
| 69 | r8a7791_gpio##idx##_resources, \ | ||
| 70 | ARRAY_SIZE(r8a7791_gpio##idx##_resources), \ | ||
| 71 | &r8a7791_gpio##idx##_platform_data, \ | ||
| 72 | sizeof(r8a7791_gpio##idx##_platform_data)) | ||
| 73 | |||
| 74 | void __init r8a7791_pinmux_init(void) | ||
| 75 | { | ||
| 76 | r8a7791_register_pfc(); | ||
| 77 | r8a7791_register_gpio(0); | ||
| 78 | r8a7791_register_gpio(1); | ||
| 79 | r8a7791_register_gpio(2); | ||
| 80 | r8a7791_register_gpio(3); | ||
| 81 | r8a7791_register_gpio(4); | ||
| 82 | r8a7791_register_gpio(5); | ||
| 83 | r8a7791_register_gpio(6); | ||
| 84 | r8a7791_register_gpio(7); | ||
| 59 | } | 85 | } |
| 60 | 86 | ||
| 61 | #define HSCIF_DATA(index, baseaddr, irq) \ | 87 | #define __R8A7791_SCIF(scif_type, index, baseaddr, irq) \ |
| 62 | [index] = { \ | 88 | static struct plat_sci_port scif##index##_platform_data = { \ |
| 63 | SCIF_COMMON(PORT_HSCIF, baseaddr, irq), \ | 89 | .type = scif_type, \ |
| 64 | .scbrr_algo_id = SCBRR_ALGO_6, \ | 90 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ |
| 65 | .scscr = SCSCR_RE | SCSCR_TE, \ | 91 | .scscr = SCSCR_RE | SCSCR_TE, \ |
| 92 | }; \ | ||
| 93 | \ | ||
| 94 | static struct resource scif##index##_resources[] = { \ | ||
| 95 | DEFINE_RES_MEM(baseaddr, 0x100), \ | ||
| 96 | DEFINE_RES_IRQ(irq), \ | ||
| 66 | } | 97 | } |
| 67 | 98 | ||
| 68 | enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1, | 99 | #define R8A7791_SCIF(index, baseaddr, irq) \ |
| 69 | SCIF2, SCIF3, SCIF4, SCIF5, SCIFA3, SCIFA4, SCIFA5 }; | 100 | __R8A7791_SCIF(PORT_SCIF, index, baseaddr, irq) |
| 70 | 101 | ||
| 71 | static const struct plat_sci_port scif[] __initconst = { | 102 | #define R8A7791_SCIFA(index, baseaddr, irq) \ |
| 72 | SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */ | 103 | __R8A7791_SCIF(PORT_SCIFA, index, baseaddr, irq) |
| 73 | SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */ | 104 | |
| 74 | SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */ | 105 | #define R8A7791_SCIFB(index, baseaddr, irq) \ |
| 75 | SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */ | 106 | __R8A7791_SCIF(PORT_SCIFB, index, baseaddr, irq) |
| 76 | SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */ | 107 | |
| 77 | SCIFA_DATA(SCIFA2, 0xe6c60000, gic_spi(151)), /* SCIFA2 */ | 108 | R8A7791_SCIFA(0, 0xe6c40000, gic_spi(144)); /* SCIFA0 */ |
| 78 | SCIF_DATA(SCIF0, 0xe6e60000, gic_spi(152)), /* SCIF0 */ | 109 | R8A7791_SCIFA(1, 0xe6c50000, gic_spi(145)); /* SCIFA1 */ |
| 79 | SCIF_DATA(SCIF1, 0xe6e68000, gic_spi(153)), /* SCIF1 */ | 110 | R8A7791_SCIFB(2, 0xe6c20000, gic_spi(148)); /* SCIFB0 */ |
| 80 | SCIF_DATA(SCIF2, 0xe6e58000, gic_spi(22)), /* SCIF2 */ | 111 | R8A7791_SCIFB(3, 0xe6c30000, gic_spi(149)); /* SCIFB1 */ |
| 81 | SCIF_DATA(SCIF3, 0xe6ea8000, gic_spi(23)), /* SCIF3 */ | 112 | R8A7791_SCIFB(4, 0xe6ce0000, gic_spi(150)); /* SCIFB2 */ |
| 82 | SCIF_DATA(SCIF4, 0xe6ee0000, gic_spi(24)), /* SCIF4 */ | 113 | R8A7791_SCIFA(5, 0xe6c60000, gic_spi(151)); /* SCIFA2 */ |
| 83 | SCIF_DATA(SCIF5, 0xe6ee8000, gic_spi(25)), /* SCIF5 */ | 114 | R8A7791_SCIF(6, 0xe6e60000, gic_spi(152)); /* SCIF0 */ |
| 84 | SCIFA_DATA(SCIFA3, 0xe6c70000, gic_spi(29)), /* SCIFA3 */ | 115 | R8A7791_SCIF(7, 0xe6e68000, gic_spi(153)); /* SCIF1 */ |
| 85 | SCIFA_DATA(SCIFA4, 0xe6c78000, gic_spi(30)), /* SCIFA4 */ | 116 | R8A7791_SCIF(8, 0xe6e58000, gic_spi(22)); /* SCIF2 */ |
| 86 | SCIFA_DATA(SCIFA5, 0xe6c80000, gic_spi(31)), /* SCIFA5 */ | 117 | R8A7791_SCIF(9, 0xe6ea8000, gic_spi(23)); /* SCIF3 */ |
| 87 | }; | 118 | R8A7791_SCIF(10, 0xe6ee0000, gic_spi(24)); /* SCIF4 */ |
| 88 | 119 | R8A7791_SCIF(11, 0xe6ee8000, gic_spi(25)); /* SCIF5 */ | |
| 89 | static inline void r8a7791_register_scif(int idx) | 120 | R8A7791_SCIFA(12, 0xe6c70000, gic_spi(29)); /* SCIFA3 */ |
| 90 | { | 121 | R8A7791_SCIFA(13, 0xe6c78000, gic_spi(30)); /* SCIFA4 */ |
| 91 | platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx], | 122 | R8A7791_SCIFA(14, 0xe6c80000, gic_spi(31)); /* SCIFA5 */ |
| 92 | sizeof(struct plat_sci_port)); | 123 | |
| 93 | } | 124 | #define r8a7791_register_scif(index) \ |
| 125 | platform_device_register_resndata(&platform_bus, "sh-sci", index, \ | ||
| 126 | scif##index##_resources, \ | ||
| 127 | ARRAY_SIZE(scif##index##_resources), \ | ||
| 128 | &scif##index##_platform_data, \ | ||
| 129 | sizeof(scif##index##_platform_data)) | ||
| 94 | 130 | ||
| 95 | static const struct sh_timer_config cmt00_platform_data __initconst = { | 131 | static const struct sh_timer_config cmt00_platform_data __initconst = { |
| 96 | .name = "CMT00", | 132 | .name = "CMT00", |
| @@ -136,23 +172,34 @@ static struct resource irqc0_resources[] = { | |||
| 136 | &irqc##idx##_data, \ | 172 | &irqc##idx##_data, \ |
| 137 | sizeof(struct renesas_irqc_config)) | 173 | sizeof(struct renesas_irqc_config)) |
| 138 | 174 | ||
| 175 | static const struct resource thermal_resources[] __initconst = { | ||
| 176 | DEFINE_RES_MEM(0xe61f0000, 0x14), | ||
| 177 | DEFINE_RES_MEM(0xe61f0100, 0x38), | ||
| 178 | DEFINE_RES_IRQ(gic_spi(69)), | ||
| 179 | }; | ||
| 180 | |||
| 181 | #define r8a7791_register_thermal() \ | ||
| 182 | platform_device_register_simple("rcar_thermal", -1, \ | ||
| 183 | thermal_resources, \ | ||
| 184 | ARRAY_SIZE(thermal_resources)) | ||
| 185 | |||
| 139 | void __init r8a7791_add_dt_devices(void) | 186 | void __init r8a7791_add_dt_devices(void) |
| 140 | { | 187 | { |
| 141 | r8a7791_register_scif(SCIFA0); | 188 | r8a7791_register_scif(0); |
| 142 | r8a7791_register_scif(SCIFA1); | 189 | r8a7791_register_scif(1); |
| 143 | r8a7791_register_scif(SCIFB0); | 190 | r8a7791_register_scif(2); |
| 144 | r8a7791_register_scif(SCIFB1); | 191 | r8a7791_register_scif(3); |
| 145 | r8a7791_register_scif(SCIFB2); | 192 | r8a7791_register_scif(4); |
| 146 | r8a7791_register_scif(SCIFA2); | 193 | r8a7791_register_scif(5); |
| 147 | r8a7791_register_scif(SCIF0); | 194 | r8a7791_register_scif(6); |
| 148 | r8a7791_register_scif(SCIF1); | 195 | r8a7791_register_scif(7); |
| 149 | r8a7791_register_scif(SCIF2); | 196 | r8a7791_register_scif(8); |
| 150 | r8a7791_register_scif(SCIF3); | 197 | r8a7791_register_scif(9); |
| 151 | r8a7791_register_scif(SCIF4); | 198 | r8a7791_register_scif(10); |
| 152 | r8a7791_register_scif(SCIF5); | 199 | r8a7791_register_scif(11); |
| 153 | r8a7791_register_scif(SCIFA3); | 200 | r8a7791_register_scif(12); |
| 154 | r8a7791_register_scif(SCIFA4); | 201 | r8a7791_register_scif(13); |
| 155 | r8a7791_register_scif(SCIFA5); | 202 | r8a7791_register_scif(14); |
| 156 | r8a7791_register_cmt(00); | 203 | r8a7791_register_cmt(00); |
| 157 | } | 204 | } |
| 158 | 205 | ||
| @@ -160,6 +207,7 @@ void __init r8a7791_add_standard_devices(void) | |||
| 160 | { | 207 | { |
| 161 | r8a7791_add_dt_devices(); | 208 | r8a7791_add_dt_devices(); |
| 162 | r8a7791_register_irqc(0); | 209 | r8a7791_register_irqc(0); |
| 210 | r8a7791_register_thermal(); | ||
| 163 | } | 211 | } |
| 164 | 212 | ||
| 165 | void __init r8a7791_init_early(void) | 213 | void __init r8a7791_init_early(void) |
diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c b/arch/arm/mach-shmobile/setup-rcar-gen2.c index 5734c24bf6c7..69ccc6c6fd33 100644 --- a/arch/arm/mach-shmobile/setup-rcar-gen2.c +++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c | |||
| @@ -18,6 +18,7 @@ | |||
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ | 19 | */ |
| 20 | 20 | ||
| 21 | #include <linux/clk/shmobile.h> | ||
| 21 | #include <linux/clocksource.h> | 22 | #include <linux/clocksource.h> |
| 22 | #include <linux/io.h> | 23 | #include <linux/io.h> |
| 23 | #include <linux/kernel.h> | 24 | #include <linux/kernel.h> |
| @@ -44,8 +45,10 @@ u32 __init rcar_gen2_read_mode_pins(void) | |||
| 44 | 45 | ||
| 45 | void __init rcar_gen2_timer_init(void) | 46 | void __init rcar_gen2_timer_init(void) |
| 46 | { | 47 | { |
| 47 | #ifdef CONFIG_ARM_ARCH_TIMER | 48 | #if defined(CONFIG_ARM_ARCH_TIMER) || defined(CONFIG_COMMON_CLK) |
| 48 | u32 mode = rcar_gen2_read_mode_pins(); | 49 | u32 mode = rcar_gen2_read_mode_pins(); |
| 50 | #endif | ||
| 51 | #ifdef CONFIG_ARM_ARCH_TIMER | ||
| 49 | void __iomem *base; | 52 | void __iomem *base; |
| 50 | int extal_mhz = 0; | 53 | int extal_mhz = 0; |
| 51 | u32 freq; | 54 | u32 freq; |
| @@ -78,14 +81,28 @@ void __init rcar_gen2_timer_init(void) | |||
| 78 | /* Remap "armgcnt address map" space */ | 81 | /* Remap "armgcnt address map" space */ |
| 79 | base = ioremap(0xe6080000, PAGE_SIZE); | 82 | base = ioremap(0xe6080000, PAGE_SIZE); |
| 80 | 83 | ||
| 81 | /* Update registers with correct frequency */ | 84 | /* |
| 82 | iowrite32(freq, base + CNTFID0); | 85 | * Update the timer if it is either not running, or is not at the |
| 83 | asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq)); | 86 | * right frequency. The timer is only configurable in secure mode |
| 87 | * so this avoids an abort if the loader started the timer and | ||
| 88 | * entered the kernel in non-secure mode. | ||
| 89 | */ | ||
| 90 | |||
| 91 | if ((ioread32(base + CNTCR) & 1) == 0 || | ||
| 92 | ioread32(base + CNTFID0) != freq) { | ||
| 93 | /* Update registers with correct frequency */ | ||
| 94 | iowrite32(freq, base + CNTFID0); | ||
| 95 | asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq)); | ||
| 96 | |||
| 97 | /* make sure arch timer is started by setting bit 0 of CNTCR */ | ||
| 98 | iowrite32(1, base + CNTCR); | ||
| 99 | } | ||
| 84 | 100 | ||
| 85 | /* make sure arch timer is started by setting bit 0 of CNTCR */ | ||
| 86 | iowrite32(1, base + CNTCR); | ||
| 87 | iounmap(base); | 101 | iounmap(base); |
| 88 | #endif /* CONFIG_ARM_ARCH_TIMER */ | 102 | #endif /* CONFIG_ARM_ARCH_TIMER */ |
| 89 | 103 | ||
| 104 | #ifdef CONFIG_COMMON_CLK | ||
| 105 | rcar_gen2_clocks_init(mode); | ||
| 106 | #endif | ||
| 90 | clocksource_of_init(); | 107 | clocksource_of_init(); |
| 91 | } | 108 | } |
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c index 311878391e18..27301278c208 100644 --- a/arch/arm/mach-shmobile/setup-sh7372.c +++ b/arch/arm/mach-shmobile/setup-sh7372.c | |||
| @@ -86,138 +86,36 @@ void __init sh7372_pinmux_init(void) | |||
| 86 | platform_device_register(&sh7372_pfc_device); | 86 | platform_device_register(&sh7372_pfc_device); |
| 87 | } | 87 | } |
| 88 | 88 | ||
| 89 | /* SCIFA0 */ | 89 | /* SCIF */ |
| 90 | static struct plat_sci_port scif0_platform_data = { | 90 | #define SH7372_SCIF(scif_type, index, baseaddr, irq) \ |
| 91 | .mapbase = 0xe6c40000, | 91 | static struct plat_sci_port scif##index##_platform_data = { \ |
| 92 | .flags = UPF_BOOT_AUTOCONF, | 92 | .type = scif_type, \ |
| 93 | .scscr = SCSCR_RE | SCSCR_TE, | 93 | .flags = UPF_BOOT_AUTOCONF, \ |
| 94 | .scbrr_algo_id = SCBRR_ALGO_4, | 94 | .scscr = SCSCR_RE | SCSCR_TE, \ |
| 95 | .type = PORT_SCIFA, | 95 | }; \ |
| 96 | .irqs = { evt2irq(0x0c00), evt2irq(0x0c00), | 96 | \ |
| 97 | evt2irq(0x0c00), evt2irq(0x0c00) }, | 97 | static struct resource scif##index##_resources[] = { \ |
| 98 | }; | 98 | DEFINE_RES_MEM(baseaddr, 0x100), \ |
| 99 | 99 | DEFINE_RES_IRQ(irq), \ | |
| 100 | static struct platform_device scif0_device = { | 100 | }; \ |
| 101 | .name = "sh-sci", | 101 | \ |
| 102 | .id = 0, | 102 | static struct platform_device scif##index##_device = { \ |
| 103 | .dev = { | 103 | .name = "sh-sci", \ |
| 104 | .platform_data = &scif0_platform_data, | 104 | .id = index, \ |
| 105 | }, | 105 | .resource = scif##index##_resources, \ |
| 106 | }; | 106 | .num_resources = ARRAY_SIZE(scif##index##_resources), \ |
| 107 | 107 | .dev = { \ | |
| 108 | /* SCIFA1 */ | 108 | .platform_data = &scif##index##_platform_data, \ |
| 109 | static struct plat_sci_port scif1_platform_data = { | 109 | }, \ |
| 110 | .mapbase = 0xe6c50000, | 110 | } |
| 111 | .flags = UPF_BOOT_AUTOCONF, | ||
| 112 | .scscr = SCSCR_RE | SCSCR_TE, | ||
| 113 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
| 114 | .type = PORT_SCIFA, | ||
| 115 | .irqs = { evt2irq(0x0c20), evt2irq(0x0c20), | ||
| 116 | evt2irq(0x0c20), evt2irq(0x0c20) }, | ||
| 117 | }; | ||
| 118 | |||
| 119 | static struct platform_device scif1_device = { | ||
| 120 | .name = "sh-sci", | ||
| 121 | .id = 1, | ||
| 122 | .dev = { | ||
| 123 | .platform_data = &scif1_platform_data, | ||
| 124 | }, | ||
| 125 | }; | ||
| 126 | |||
| 127 | /* SCIFA2 */ | ||
| 128 | static struct plat_sci_port scif2_platform_data = { | ||
| 129 | .mapbase = 0xe6c60000, | ||
| 130 | .flags = UPF_BOOT_AUTOCONF, | ||
| 131 | .scscr = SCSCR_RE | SCSCR_TE, | ||
| 132 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
| 133 | .type = PORT_SCIFA, | ||
| 134 | .irqs = { evt2irq(0x0c40), evt2irq(0x0c40), | ||
| 135 | evt2irq(0x0c40), evt2irq(0x0c40) }, | ||
| 136 | }; | ||
| 137 | |||
| 138 | static struct platform_device scif2_device = { | ||
| 139 | .name = "sh-sci", | ||
| 140 | .id = 2, | ||
| 141 | .dev = { | ||
| 142 | .platform_data = &scif2_platform_data, | ||
| 143 | }, | ||
| 144 | }; | ||
| 145 | |||
| 146 | /* SCIFA3 */ | ||
| 147 | static struct plat_sci_port scif3_platform_data = { | ||
| 148 | .mapbase = 0xe6c70000, | ||
| 149 | .flags = UPF_BOOT_AUTOCONF, | ||
| 150 | .scscr = SCSCR_RE | SCSCR_TE, | ||
| 151 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
| 152 | .type = PORT_SCIFA, | ||
| 153 | .irqs = { evt2irq(0x0c60), evt2irq(0x0c60), | ||
| 154 | evt2irq(0x0c60), evt2irq(0x0c60) }, | ||
| 155 | }; | ||
| 156 | |||
| 157 | static struct platform_device scif3_device = { | ||
| 158 | .name = "sh-sci", | ||
| 159 | .id = 3, | ||
| 160 | .dev = { | ||
| 161 | .platform_data = &scif3_platform_data, | ||
| 162 | }, | ||
| 163 | }; | ||
| 164 | |||
| 165 | /* SCIFA4 */ | ||
| 166 | static struct plat_sci_port scif4_platform_data = { | ||
| 167 | .mapbase = 0xe6c80000, | ||
| 168 | .flags = UPF_BOOT_AUTOCONF, | ||
| 169 | .scscr = SCSCR_RE | SCSCR_TE, | ||
| 170 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
| 171 | .type = PORT_SCIFA, | ||
| 172 | .irqs = { evt2irq(0x0d20), evt2irq(0x0d20), | ||
| 173 | evt2irq(0x0d20), evt2irq(0x0d20) }, | ||
| 174 | }; | ||
| 175 | |||
| 176 | static struct platform_device scif4_device = { | ||
| 177 | .name = "sh-sci", | ||
| 178 | .id = 4, | ||
| 179 | .dev = { | ||
| 180 | .platform_data = &scif4_platform_data, | ||
| 181 | }, | ||
| 182 | }; | ||
| 183 | |||
| 184 | /* SCIFA5 */ | ||
| 185 | static struct plat_sci_port scif5_platform_data = { | ||
| 186 | .mapbase = 0xe6cb0000, | ||
| 187 | .flags = UPF_BOOT_AUTOCONF, | ||
| 188 | .scscr = SCSCR_RE | SCSCR_TE, | ||
| 189 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
| 190 | .type = PORT_SCIFA, | ||
| 191 | .irqs = { evt2irq(0x0d40), evt2irq(0x0d40), | ||
| 192 | evt2irq(0x0d40), evt2irq(0x0d40) }, | ||
| 193 | }; | ||
| 194 | |||
| 195 | static struct platform_device scif5_device = { | ||
| 196 | .name = "sh-sci", | ||
| 197 | .id = 5, | ||
| 198 | .dev = { | ||
| 199 | .platform_data = &scif5_platform_data, | ||
| 200 | }, | ||
| 201 | }; | ||
| 202 | |||
| 203 | /* SCIFB */ | ||
| 204 | static struct plat_sci_port scif6_platform_data = { | ||
| 205 | .mapbase = 0xe6c30000, | ||
| 206 | .flags = UPF_BOOT_AUTOCONF, | ||
| 207 | .scscr = SCSCR_RE | SCSCR_TE, | ||
| 208 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
| 209 | .type = PORT_SCIFB, | ||
| 210 | .irqs = { evt2irq(0x0d60), evt2irq(0x0d60), | ||
| 211 | evt2irq(0x0d60), evt2irq(0x0d60) }, | ||
| 212 | }; | ||
| 213 | 111 | ||
| 214 | static struct platform_device scif6_device = { | 112 | SH7372_SCIF(PORT_SCIFA, 0, 0xe6c40000, evt2irq(0x0c00)); |
| 215 | .name = "sh-sci", | 113 | SH7372_SCIF(PORT_SCIFA, 1, 0xe6c50000, evt2irq(0x0c20)); |
| 216 | .id = 6, | 114 | SH7372_SCIF(PORT_SCIFA, 2, 0xe6c60000, evt2irq(0x0c40)); |
| 217 | .dev = { | 115 | SH7372_SCIF(PORT_SCIFA, 3, 0xe6c70000, evt2irq(0x0c60)); |
| 218 | .platform_data = &scif6_platform_data, | 116 | SH7372_SCIF(PORT_SCIFA, 4, 0xe6c80000, evt2irq(0x0d20)); |
| 219 | }, | 117 | SH7372_SCIF(PORT_SCIFA, 5, 0xe6cb0000, evt2irq(0x0d40)); |
| 220 | }; | 118 | SH7372_SCIF(PORT_SCIFB, 6, 0xe6c30000, evt2irq(0x0d60)); |
| 221 | 119 | ||
| 222 | /* CMT */ | 120 | /* CMT */ |
| 223 | static struct sh_timer_config cmt2_platform_data = { | 121 | static struct sh_timer_config cmt2_platform_data = { |
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c index 22de17417fd7..00b348ec48b8 100644 --- a/arch/arm/mach-shmobile/setup-sh73a0.c +++ b/arch/arm/mach-shmobile/setup-sh73a0.c | |||
| @@ -71,167 +71,38 @@ void __init sh73a0_pinmux_init(void) | |||
| 71 | ARRAY_SIZE(pfc_resources)); | 71 | ARRAY_SIZE(pfc_resources)); |
| 72 | } | 72 | } |
| 73 | 73 | ||
| 74 | static struct plat_sci_port scif0_platform_data = { | 74 | /* SCIF */ |
| 75 | .mapbase = 0xe6c40000, | 75 | #define SH73A0_SCIF(scif_type, index, baseaddr, irq) \ |
| 76 | .flags = UPF_BOOT_AUTOCONF, | 76 | static struct plat_sci_port scif##index##_platform_data = { \ |
| 77 | .scscr = SCSCR_RE | SCSCR_TE, | 77 | .type = scif_type, \ |
| 78 | .scbrr_algo_id = SCBRR_ALGO_4, | 78 | .flags = UPF_BOOT_AUTOCONF, \ |
| 79 | .type = PORT_SCIFA, | 79 | .scscr = SCSCR_RE | SCSCR_TE, \ |
| 80 | .irqs = { gic_spi(72), gic_spi(72), | 80 | }; \ |
| 81 | gic_spi(72), gic_spi(72) }, | 81 | \ |
| 82 | }; | 82 | static struct resource scif##index##_resources[] = { \ |
| 83 | 83 | DEFINE_RES_MEM(baseaddr, 0x100), \ | |
| 84 | static struct platform_device scif0_device = { | 84 | DEFINE_RES_IRQ(irq), \ |
| 85 | .name = "sh-sci", | 85 | }; \ |
| 86 | .id = 0, | 86 | \ |
| 87 | .dev = { | 87 | static struct platform_device scif##index##_device = { \ |
| 88 | .platform_data = &scif0_platform_data, | 88 | .name = "sh-sci", \ |
| 89 | }, | 89 | .id = index, \ |
| 90 | }; | 90 | .resource = scif##index##_resources, \ |
| 91 | 91 | .num_resources = ARRAY_SIZE(scif##index##_resources), \ | |
| 92 | static struct plat_sci_port scif1_platform_data = { | 92 | .dev = { \ |
| 93 | .mapbase = 0xe6c50000, | 93 | .platform_data = &scif##index##_platform_data, \ |
| 94 | .flags = UPF_BOOT_AUTOCONF, | 94 | }, \ |
| 95 | .scscr = SCSCR_RE | SCSCR_TE, | 95 | } |
| 96 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
| 97 | .type = PORT_SCIFA, | ||
| 98 | .irqs = { gic_spi(73), gic_spi(73), | ||
| 99 | gic_spi(73), gic_spi(73) }, | ||
| 100 | }; | ||
| 101 | |||
| 102 | static struct platform_device scif1_device = { | ||
| 103 | .name = "sh-sci", | ||
| 104 | .id = 1, | ||
| 105 | .dev = { | ||
| 106 | .platform_data = &scif1_platform_data, | ||
| 107 | }, | ||
| 108 | }; | ||
| 109 | |||
| 110 | static struct plat_sci_port scif2_platform_data = { | ||
| 111 | .mapbase = 0xe6c60000, | ||
| 112 | .flags = UPF_BOOT_AUTOCONF, | ||
| 113 | .scscr = SCSCR_RE | SCSCR_TE, | ||
| 114 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
| 115 | .type = PORT_SCIFA, | ||
| 116 | .irqs = { gic_spi(74), gic_spi(74), | ||
| 117 | gic_spi(74), gic_spi(74) }, | ||
| 118 | }; | ||
| 119 | |||
| 120 | static struct platform_device scif2_device = { | ||
| 121 | .name = "sh-sci", | ||
| 122 | .id = 2, | ||
| 123 | .dev = { | ||
| 124 | .platform_data = &scif2_platform_data, | ||
| 125 | }, | ||
| 126 | }; | ||
| 127 | |||
| 128 | static struct plat_sci_port scif3_platform_data = { | ||
| 129 | .mapbase = 0xe6c70000, | ||
| 130 | .flags = UPF_BOOT_AUTOCONF, | ||
| 131 | .scscr = SCSCR_RE | SCSCR_TE, | ||
| 132 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
| 133 | .type = PORT_SCIFA, | ||
| 134 | .irqs = { gic_spi(75), gic_spi(75), | ||
| 135 | gic_spi(75), gic_spi(75) }, | ||
| 136 | }; | ||
| 137 | |||
| 138 | static struct platform_device scif3_device = { | ||
| 139 | .name = "sh-sci", | ||
| 140 | .id = 3, | ||
| 141 | .dev = { | ||
| 142 | .platform_data = &scif3_platform_data, | ||
| 143 | }, | ||
| 144 | }; | ||
| 145 | |||
| 146 | static struct plat_sci_port scif4_platform_data = { | ||
| 147 | .mapbase = 0xe6c80000, | ||
| 148 | .flags = UPF_BOOT_AUTOCONF, | ||
| 149 | .scscr = SCSCR_RE | SCSCR_TE, | ||
| 150 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
| 151 | .type = PORT_SCIFA, | ||
| 152 | .irqs = { gic_spi(78), gic_spi(78), | ||
| 153 | gic_spi(78), gic_spi(78) }, | ||
| 154 | }; | ||
| 155 | |||
| 156 | static struct platform_device scif4_device = { | ||
| 157 | .name = "sh-sci", | ||
| 158 | .id = 4, | ||
| 159 | .dev = { | ||
| 160 | .platform_data = &scif4_platform_data, | ||
| 161 | }, | ||
| 162 | }; | ||
| 163 | |||
| 164 | static struct plat_sci_port scif5_platform_data = { | ||
| 165 | .mapbase = 0xe6cb0000, | ||
| 166 | .flags = UPF_BOOT_AUTOCONF, | ||
| 167 | .scscr = SCSCR_RE | SCSCR_TE, | ||
| 168 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
| 169 | .type = PORT_SCIFA, | ||
| 170 | .irqs = { gic_spi(79), gic_spi(79), | ||
| 171 | gic_spi(79), gic_spi(79) }, | ||
| 172 | }; | ||
| 173 | |||
| 174 | static struct platform_device scif5_device = { | ||
| 175 | .name = "sh-sci", | ||
| 176 | .id = 5, | ||
| 177 | .dev = { | ||
| 178 | .platform_data = &scif5_platform_data, | ||
| 179 | }, | ||
| 180 | }; | ||
| 181 | |||
| 182 | static struct plat_sci_port scif6_platform_data = { | ||
| 183 | .mapbase = 0xe6cc0000, | ||
| 184 | .flags = UPF_BOOT_AUTOCONF, | ||
| 185 | .scscr = SCSCR_RE | SCSCR_TE, | ||
| 186 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
| 187 | .type = PORT_SCIFA, | ||
| 188 | .irqs = { gic_spi(156), gic_spi(156), | ||
| 189 | gic_spi(156), gic_spi(156) }, | ||
| 190 | }; | ||
| 191 | |||
| 192 | static struct platform_device scif6_device = { | ||
| 193 | .name = "sh-sci", | ||
| 194 | .id = 6, | ||
| 195 | .dev = { | ||
| 196 | .platform_data = &scif6_platform_data, | ||
| 197 | }, | ||
| 198 | }; | ||
| 199 | |||
| 200 | static struct plat_sci_port scif7_platform_data = { | ||
| 201 | .mapbase = 0xe6cd0000, | ||
| 202 | .flags = UPF_BOOT_AUTOCONF, | ||
| 203 | .scscr = SCSCR_RE | SCSCR_TE, | ||
| 204 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
| 205 | .type = PORT_SCIFA, | ||
| 206 | .irqs = { gic_spi(143), gic_spi(143), | ||
| 207 | gic_spi(143), gic_spi(143) }, | ||
| 208 | }; | ||
| 209 | |||
| 210 | static struct platform_device scif7_device = { | ||
| 211 | .name = "sh-sci", | ||
| 212 | .id = 7, | ||
| 213 | .dev = { | ||
| 214 | .platform_data = &scif7_platform_data, | ||
| 215 | }, | ||
| 216 | }; | ||
| 217 | |||
| 218 | static struct plat_sci_port scif8_platform_data = { | ||
| 219 | .mapbase = 0xe6c30000, | ||
| 220 | .flags = UPF_BOOT_AUTOCONF, | ||
| 221 | .scscr = SCSCR_RE | SCSCR_TE, | ||
| 222 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
| 223 | .type = PORT_SCIFB, | ||
| 224 | .irqs = { gic_spi(80), gic_spi(80), | ||
| 225 | gic_spi(80), gic_spi(80) }, | ||
| 226 | }; | ||
| 227 | 96 | ||
| 228 | static struct platform_device scif8_device = { | 97 | SH73A0_SCIF(PORT_SCIFA, 0, 0xe6c40000, gic_spi(72)); |
| 229 | .name = "sh-sci", | 98 | SH73A0_SCIF(PORT_SCIFA, 1, 0xe6c50000, gic_spi(73)); |
| 230 | .id = 8, | 99 | SH73A0_SCIF(PORT_SCIFA, 2, 0xe6c60000, gic_spi(74)); |
| 231 | .dev = { | 100 | SH73A0_SCIF(PORT_SCIFA, 3, 0xe6c70000, gic_spi(75)); |
| 232 | .platform_data = &scif8_platform_data, | 101 | SH73A0_SCIF(PORT_SCIFA, 4, 0xe6c80000, gic_spi(78)); |
| 233 | }, | 102 | SH73A0_SCIF(PORT_SCIFA, 5, 0xe6cb0000, gic_spi(79)); |
| 234 | }; | 103 | SH73A0_SCIF(PORT_SCIFA, 6, 0xe6cc0000, gic_spi(156)); |
| 104 | SH73A0_SCIF(PORT_SCIFA, 7, 0xe6cd0000, gic_spi(143)); | ||
| 105 | SH73A0_SCIF(PORT_SCIFB, 8, 0xe6c30000, gic_spi(80)); | ||
| 235 | 106 | ||
| 236 | static struct sh_timer_config cmt10_platform_data = { | 107 | static struct sh_timer_config cmt10_platform_data = { |
| 237 | .name = "CMT10", | 108 | .name = "CMT10", |
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 09e740f58b27..00b85fd9285d 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig | |||
| @@ -2,6 +2,7 @@ config ARCH_TEGRA | |||
| 2 | bool "NVIDIA Tegra" if ARCH_MULTI_V7 | 2 | bool "NVIDIA Tegra" if ARCH_MULTI_V7 |
| 3 | select ARCH_HAS_CPUFREQ | 3 | select ARCH_HAS_CPUFREQ |
| 4 | select ARCH_REQUIRE_GPIOLIB | 4 | select ARCH_REQUIRE_GPIOLIB |
| 5 | select ARCH_SUPPORTS_TRUSTED_FOUNDATIONS | ||
| 5 | select ARM_GIC | 6 | select ARM_GIC |
| 6 | select CLKSRC_MMIO | 7 | select CLKSRC_MMIO |
| 7 | select CLKSRC_OF | 8 | select CLKSRC_OF |
diff --git a/arch/arm/mach-tegra/reset.c b/arch/arm/mach-tegra/reset.c index 568f5bbf979d..146fe8e0ae7c 100644 --- a/arch/arm/mach-tegra/reset.c +++ b/arch/arm/mach-tegra/reset.c | |||
| @@ -21,6 +21,7 @@ | |||
| 21 | 21 | ||
| 22 | #include <asm/cacheflush.h> | 22 | #include <asm/cacheflush.h> |
| 23 | #include <asm/hardware/cache-l2x0.h> | 23 | #include <asm/hardware/cache-l2x0.h> |
| 24 | #include <asm/firmware.h> | ||
| 24 | 25 | ||
| 25 | #include "iomap.h" | 26 | #include "iomap.h" |
| 26 | #include "irammap.h" | 27 | #include "irammap.h" |
| @@ -33,26 +34,18 @@ | |||
| 33 | 34 | ||
| 34 | static bool is_enabled; | 35 | static bool is_enabled; |
| 35 | 36 | ||
| 36 | static void __init tegra_cpu_reset_handler_enable(void) | 37 | static void __init tegra_cpu_reset_handler_set(const u32 reset_address) |
| 37 | { | 38 | { |
| 38 | void __iomem *iram_base = IO_ADDRESS(TEGRA_IRAM_RESET_BASE); | ||
| 39 | void __iomem *evp_cpu_reset = | 39 | void __iomem *evp_cpu_reset = |
| 40 | IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE + 0x100); | 40 | IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE + 0x100); |
| 41 | void __iomem *sb_ctrl = IO_ADDRESS(TEGRA_SB_BASE); | 41 | void __iomem *sb_ctrl = IO_ADDRESS(TEGRA_SB_BASE); |
| 42 | u32 reg; | 42 | u32 reg; |
| 43 | 43 | ||
| 44 | BUG_ON(is_enabled); | ||
| 45 | BUG_ON(tegra_cpu_reset_handler_size > TEGRA_IRAM_RESET_HANDLER_SIZE); | ||
| 46 | |||
| 47 | memcpy(iram_base, (void *)__tegra_cpu_reset_handler_start, | ||
| 48 | tegra_cpu_reset_handler_size); | ||
| 49 | |||
| 50 | /* | 44 | /* |
| 51 | * NOTE: This must be the one and only write to the EVP CPU reset | 45 | * NOTE: This must be the one and only write to the EVP CPU reset |
| 52 | * vector in the entire system. | 46 | * vector in the entire system. |
| 53 | */ | 47 | */ |
| 54 | writel(TEGRA_IRAM_RESET_BASE + tegra_cpu_reset_handler_offset, | 48 | writel(reset_address, evp_cpu_reset); |
| 55 | evp_cpu_reset); | ||
| 56 | wmb(); | 49 | wmb(); |
| 57 | reg = readl(evp_cpu_reset); | 50 | reg = readl(evp_cpu_reset); |
| 58 | 51 | ||
| @@ -66,8 +59,33 @@ static void __init tegra_cpu_reset_handler_enable(void) | |||
| 66 | writel(reg, sb_ctrl); | 59 | writel(reg, sb_ctrl); |
| 67 | wmb(); | 60 | wmb(); |
| 68 | } | 61 | } |
| 62 | } | ||
| 63 | |||
| 64 | static void __init tegra_cpu_reset_handler_enable(void) | ||
| 65 | { | ||
| 66 | void __iomem *iram_base = IO_ADDRESS(TEGRA_IRAM_RESET_BASE); | ||
| 67 | const u32 reset_address = TEGRA_IRAM_RESET_BASE + | ||
| 68 | tegra_cpu_reset_handler_offset; | ||
| 69 | int err; | ||
| 70 | |||
| 71 | BUG_ON(is_enabled); | ||
| 72 | BUG_ON(tegra_cpu_reset_handler_size > TEGRA_IRAM_RESET_HANDLER_SIZE); | ||
| 69 | 73 | ||
| 70 | is_enabled = true; | 74 | memcpy(iram_base, (void *)__tegra_cpu_reset_handler_start, |
| 75 | tegra_cpu_reset_handler_size); | ||
| 76 | |||
| 77 | err = call_firmware_op(set_cpu_boot_addr, 0, reset_address); | ||
| 78 | switch (err) { | ||
| 79 | case -ENOSYS: | ||
| 80 | tegra_cpu_reset_handler_set(reset_address); | ||
| 81 | /* pass-through */ | ||
| 82 | case 0: | ||
| 83 | is_enabled = true; | ||
| 84 | break; | ||
| 85 | default: | ||
| 86 | pr_crit("Cannot set CPU reset handler: %d\n", err); | ||
| 87 | BUG(); | ||
| 88 | } | ||
| 71 | } | 89 | } |
| 72 | 90 | ||
| 73 | void __init tegra_cpu_reset_handler_init(void) | 91 | void __init tegra_cpu_reset_handler_init(void) |
diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c index 73368176c6e8..09a1f8d98ca2 100644 --- a/arch/arm/mach-tegra/tegra.c +++ b/arch/arm/mach-tegra/tegra.c | |||
| @@ -40,6 +40,7 @@ | |||
| 40 | #include <asm/mach/arch.h> | 40 | #include <asm/mach/arch.h> |
| 41 | #include <asm/mach/time.h> | 41 | #include <asm/mach/time.h> |
| 42 | #include <asm/setup.h> | 42 | #include <asm/setup.h> |
| 43 | #include <asm/trusted_foundations.h> | ||
| 43 | 44 | ||
| 44 | #include "apbio.h" | 45 | #include "apbio.h" |
| 45 | #include "board.h" | 46 | #include "board.h" |
| @@ -90,6 +91,7 @@ static void __init tegra_init_cache(void) | |||
| 90 | 91 | ||
| 91 | static void __init tegra_init_early(void) | 92 | static void __init tegra_init_early(void) |
| 92 | { | 93 | { |
| 94 | of_register_trusted_foundations(); | ||
| 93 | tegra_apb_io_init(); | 95 | tegra_apb_io_init(); |
| 94 | tegra_init_fuse(); | 96 | tegra_init_fuse(); |
| 95 | tegra_cpu_reset_handler_init(); | 97 | tegra_cpu_reset_handler_init(); |
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c index 99a3590f0349..ac07e871f6a7 100644 --- a/arch/arm/plat-samsung/devs.c +++ b/arch/arm/plat-samsung/devs.c | |||
| @@ -1468,6 +1468,8 @@ void __init s3c64xx_spi0_set_platdata(int (*cfg_gpio)(void), int src_clk_nr, | |||
| 1468 | pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi0_cfg_gpio; | 1468 | pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi0_cfg_gpio; |
| 1469 | #if defined(CONFIG_PL330_DMA) | 1469 | #if defined(CONFIG_PL330_DMA) |
| 1470 | pd.filter = pl330_filter; | 1470 | pd.filter = pl330_filter; |
| 1471 | #elif defined(CONFIG_S3C64XX_PL080) | ||
| 1472 | pd.filter = pl08x_filter_id; | ||
| 1471 | #elif defined(CONFIG_S3C24XX_DMAC) | 1473 | #elif defined(CONFIG_S3C24XX_DMAC) |
| 1472 | pd.filter = s3c24xx_dma_filter; | 1474 | pd.filter = s3c24xx_dma_filter; |
| 1473 | #endif | 1475 | #endif |
| @@ -1509,8 +1511,10 @@ void __init s3c64xx_spi1_set_platdata(int (*cfg_gpio)(void), int src_clk_nr, | |||
| 1509 | pd.num_cs = num_cs; | 1511 | pd.num_cs = num_cs; |
| 1510 | pd.src_clk_nr = src_clk_nr; | 1512 | pd.src_clk_nr = src_clk_nr; |
| 1511 | pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi1_cfg_gpio; | 1513 | pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi1_cfg_gpio; |
| 1512 | #ifdef CONFIG_PL330_DMA | 1514 | #if defined(CONFIG_PL330_DMA) |
| 1513 | pd.filter = pl330_filter; | 1515 | pd.filter = pl330_filter; |
| 1516 | #elif defined(CONFIG_S3C64XX_PL080) | ||
| 1517 | pd.filter = pl08x_filter_id; | ||
| 1514 | #endif | 1518 | #endif |
| 1515 | 1519 | ||
| 1516 | s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi1); | 1520 | s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi1); |
| @@ -1550,8 +1554,10 @@ void __init s3c64xx_spi2_set_platdata(int (*cfg_gpio)(void), int src_clk_nr, | |||
| 1550 | pd.num_cs = num_cs; | 1554 | pd.num_cs = num_cs; |
| 1551 | pd.src_clk_nr = src_clk_nr; | 1555 | pd.src_clk_nr = src_clk_nr; |
| 1552 | pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi2_cfg_gpio; | 1556 | pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi2_cfg_gpio; |
| 1553 | #ifdef CONFIG_PL330_DMA | 1557 | #if defined(CONFIG_PL330_DMA) |
| 1554 | pd.filter = pl330_filter; | 1558 | pd.filter = pl330_filter; |
| 1559 | #elif defined(CONFIG_S3C64XX_PL080) | ||
| 1560 | pd.filter = pl08x_filter_id; | ||
| 1555 | #endif | 1561 | #endif |
| 1556 | 1562 | ||
| 1557 | s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi2); | 1563 | s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi2); |
diff --git a/arch/arm/plat-samsung/dma-ops.c b/arch/arm/plat-samsung/dma-ops.c index ec0d731b0e7b..886326ee6f6c 100644 --- a/arch/arm/plat-samsung/dma-ops.c +++ b/arch/arm/plat-samsung/dma-ops.c | |||
| @@ -18,6 +18,12 @@ | |||
| 18 | 18 | ||
| 19 | #include <mach/dma.h> | 19 | #include <mach/dma.h> |
| 20 | 20 | ||
| 21 | #if defined(CONFIG_PL330_DMA) | ||
| 22 | #define dma_filter pl330_filter | ||
| 23 | #elif defined(CONFIG_S3C64XX_PL080) | ||
| 24 | #define dma_filter pl08x_filter_id | ||
| 25 | #endif | ||
| 26 | |||
| 21 | static unsigned samsung_dmadev_request(enum dma_ch dma_ch, | 27 | static unsigned samsung_dmadev_request(enum dma_ch dma_ch, |
| 22 | struct samsung_dma_req *param, | 28 | struct samsung_dma_req *param, |
| 23 | struct device *dev, char *ch_name) | 29 | struct device *dev, char *ch_name) |
| @@ -30,7 +36,7 @@ static unsigned samsung_dmadev_request(enum dma_ch dma_ch, | |||
| 30 | if (dev->of_node) | 36 | if (dev->of_node) |
| 31 | return (unsigned)dma_request_slave_channel(dev, ch_name); | 37 | return (unsigned)dma_request_slave_channel(dev, ch_name); |
| 32 | else | 38 | else |
| 33 | return (unsigned)dma_request_channel(mask, pl330_filter, | 39 | return (unsigned)dma_request_channel(mask, dma_filter, |
| 34 | (void *)dma_ch); | 40 | (void *)dma_ch); |
| 35 | } | 41 | } |
| 36 | 42 | ||
diff --git a/arch/sh/kernel/cpu/sh2/setup-sh7619.c b/arch/sh/kernel/cpu/sh2/setup-sh7619.c index 4df4d4ffe39b..3860b0be56c7 100644 --- a/arch/sh/kernel/cpu/sh2/setup-sh7619.c +++ b/arch/sh/kernel/cpu/sh2/setup-sh7619.c | |||
| @@ -61,51 +61,63 @@ static DECLARE_INTC_DESC(intc_desc, "sh7619", vectors, NULL, | |||
| 61 | NULL, prio_registers, NULL); | 61 | NULL, prio_registers, NULL); |
| 62 | 62 | ||
| 63 | static struct plat_sci_port scif0_platform_data = { | 63 | static struct plat_sci_port scif0_platform_data = { |
| 64 | .mapbase = 0xf8400000, | ||
| 65 | .flags = UPF_BOOT_AUTOCONF, | 64 | .flags = UPF_BOOT_AUTOCONF, |
| 66 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 65 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
| 67 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 68 | .type = PORT_SCIF, | 66 | .type = PORT_SCIF, |
| 69 | .irqs = SCIx_IRQ_MUXED(88), | 67 | }; |
| 68 | |||
| 69 | static struct resource scif0_resources[] = { | ||
| 70 | DEFINE_RES_MEM(0xf8400000, 0x100), | ||
| 71 | DEFINE_RES_IRQ(88), | ||
| 70 | }; | 72 | }; |
| 71 | 73 | ||
| 72 | static struct platform_device scif0_device = { | 74 | static struct platform_device scif0_device = { |
| 73 | .name = "sh-sci", | 75 | .name = "sh-sci", |
| 74 | .id = 0, | 76 | .id = 0, |
| 77 | .resource = scif0_resources, | ||
| 78 | .num_resources = ARRAY_SIZE(scif0_resources), | ||
| 75 | .dev = { | 79 | .dev = { |
| 76 | .platform_data = &scif0_platform_data, | 80 | .platform_data = &scif0_platform_data, |
| 77 | }, | 81 | }, |
| 78 | }; | 82 | }; |
| 79 | 83 | ||
| 80 | static struct plat_sci_port scif1_platform_data = { | 84 | static struct plat_sci_port scif1_platform_data = { |
| 81 | .mapbase = 0xf8410000, | ||
| 82 | .flags = UPF_BOOT_AUTOCONF, | 85 | .flags = UPF_BOOT_AUTOCONF, |
| 83 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 86 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
| 84 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 85 | .type = PORT_SCIF, | 87 | .type = PORT_SCIF, |
| 86 | .irqs = SCIx_IRQ_MUXED(92), | 88 | }; |
| 89 | |||
| 90 | static struct resource scif1_resources[] = { | ||
| 91 | DEFINE_RES_MEM(0xf8410000, 0x100), | ||
| 92 | DEFINE_RES_IRQ(92), | ||
| 87 | }; | 93 | }; |
| 88 | 94 | ||
| 89 | static struct platform_device scif1_device = { | 95 | static struct platform_device scif1_device = { |
| 90 | .name = "sh-sci", | 96 | .name = "sh-sci", |
| 91 | .id = 1, | 97 | .id = 1, |
| 98 | .resource = scif1_resources, | ||
| 99 | .num_resources = ARRAY_SIZE(scif1_resources), | ||
| 92 | .dev = { | 100 | .dev = { |
| 93 | .platform_data = &scif1_platform_data, | 101 | .platform_data = &scif1_platform_data, |
| 94 | }, | 102 | }, |
| 95 | }; | 103 | }; |
| 96 | 104 | ||
| 97 | static struct plat_sci_port scif2_platform_data = { | 105 | static struct plat_sci_port scif2_platform_data = { |
| 98 | .mapbase = 0xf8420000, | ||
| 99 | .flags = UPF_BOOT_AUTOCONF, | 106 | .flags = UPF_BOOT_AUTOCONF, |
| 100 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 107 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
| 101 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 102 | .type = PORT_SCIF, | 108 | .type = PORT_SCIF, |
| 103 | .irqs = SCIx_IRQ_MUXED(96), | 109 | }; |
| 110 | |||
| 111 | static struct resource scif2_resources[] = { | ||
| 112 | DEFINE_RES_MEM(0xf8420000, 0x100), | ||
| 113 | DEFINE_RES_IRQ(96), | ||
| 104 | }; | 114 | }; |
| 105 | 115 | ||
| 106 | static struct platform_device scif2_device = { | 116 | static struct platform_device scif2_device = { |
| 107 | .name = "sh-sci", | 117 | .name = "sh-sci", |
| 108 | .id = 2, | 118 | .id = 2, |
| 119 | .resource = scif2_resources, | ||
| 120 | .num_resources = ARRAY_SIZE(scif2_resources), | ||
| 109 | .dev = { | 121 | .dev = { |
| 110 | .platform_data = &scif2_platform_data, | 122 | .platform_data = &scif2_platform_data, |
| 111 | }, | 123 | }, |
diff --git a/arch/sh/kernel/cpu/sh2a/setup-mxg.c b/arch/sh/kernel/cpu/sh2a/setup-mxg.c index f7f1cf2af302..63e996f9a7ed 100644 --- a/arch/sh/kernel/cpu/sh2a/setup-mxg.c +++ b/arch/sh/kernel/cpu/sh2a/setup-mxg.c | |||
| @@ -199,17 +199,21 @@ static struct platform_device mtu2_2_device = { | |||
| 199 | }; | 199 | }; |
| 200 | 200 | ||
| 201 | static struct plat_sci_port scif0_platform_data = { | 201 | static struct plat_sci_port scif0_platform_data = { |
| 202 | .mapbase = 0xff804000, | ||
| 203 | .flags = UPF_BOOT_AUTOCONF, | 202 | .flags = UPF_BOOT_AUTOCONF, |
| 204 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 203 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
| 205 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 206 | .type = PORT_SCIF, | 204 | .type = PORT_SCIF, |
| 207 | .irqs = SCIx_IRQ_MUXED(220), | 205 | }; |
| 206 | |||
| 207 | static struct resource scif0_resources[] = { | ||
| 208 | DEFINE_RES_MEM(0xff804000, 0x100), | ||
| 209 | DEFINE_RES_IRQ(220), | ||
| 208 | }; | 210 | }; |
| 209 | 211 | ||
| 210 | static struct platform_device scif0_device = { | 212 | static struct platform_device scif0_device = { |
| 211 | .name = "sh-sci", | 213 | .name = "sh-sci", |
| 212 | .id = 0, | 214 | .id = 0, |
| 215 | .resource = scif0_resources, | ||
| 216 | .num_resources = ARRAY_SIZE(scif0_resources), | ||
| 213 | .dev = { | 217 | .dev = { |
| 214 | .platform_data = &scif0_platform_data, | 218 | .platform_data = &scif0_platform_data, |
| 215 | }, | 219 | }, |
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c index 7b84785b8962..2c6874461536 100644 --- a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c +++ b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c | |||
| @@ -178,136 +178,168 @@ static DECLARE_INTC_DESC(intc_desc, "sh7201", vectors, groups, | |||
| 178 | mask_registers, prio_registers, NULL); | 178 | mask_registers, prio_registers, NULL); |
| 179 | 179 | ||
| 180 | static struct plat_sci_port scif0_platform_data = { | 180 | static struct plat_sci_port scif0_platform_data = { |
| 181 | .mapbase = 0xfffe8000, | ||
| 182 | .flags = UPF_BOOT_AUTOCONF, | 181 | .flags = UPF_BOOT_AUTOCONF, |
| 183 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 182 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
| 184 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 185 | .type = PORT_SCIF, | 183 | .type = PORT_SCIF, |
| 186 | .irqs = SCIx_IRQ_MUXED(180), | 184 | }; |
| 185 | |||
| 186 | static struct resource scif0_resources[] = { | ||
| 187 | DEFINE_RES_MEM(0xfffe8000, 0x100), | ||
| 188 | DEFINE_RES_IRQ(180), | ||
| 187 | }; | 189 | }; |
| 188 | 190 | ||
| 189 | static struct platform_device scif0_device = { | 191 | static struct platform_device scif0_device = { |
| 190 | .name = "sh-sci", | 192 | .name = "sh-sci", |
| 191 | .id = 0, | 193 | .id = 0, |
| 194 | .resource = scif0_resources, | ||
| 195 | .num_resources = ARRAY_SIZE(scif0_resources), | ||
| 192 | .dev = { | 196 | .dev = { |
| 193 | .platform_data = &scif0_platform_data, | 197 | .platform_data = &scif0_platform_data, |
| 194 | }, | 198 | }, |
| 195 | }; | 199 | }; |
| 196 | 200 | ||
| 197 | static struct plat_sci_port scif1_platform_data = { | 201 | static struct plat_sci_port scif1_platform_data = { |
| 198 | .mapbase = 0xfffe8800, | ||
| 199 | .flags = UPF_BOOT_AUTOCONF, | 202 | .flags = UPF_BOOT_AUTOCONF, |
| 200 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 203 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
| 201 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 202 | .type = PORT_SCIF, | 204 | .type = PORT_SCIF, |
| 203 | .irqs = SCIx_IRQ_MUXED(184), | 205 | }; |
| 206 | |||
| 207 | static struct resource scif1_resources[] = { | ||
| 208 | DEFINE_RES_MEM(0xfffe8800, 0x100), | ||
| 209 | DEFINE_RES_IRQ(184), | ||
| 204 | }; | 210 | }; |
| 205 | 211 | ||
| 206 | static struct platform_device scif1_device = { | 212 | static struct platform_device scif1_device = { |
| 207 | .name = "sh-sci", | 213 | .name = "sh-sci", |
| 208 | .id = 1, | 214 | .id = 1, |
| 215 | .resource = scif1_resources, | ||
| 216 | .num_resources = ARRAY_SIZE(scif1_resources), | ||
| 209 | .dev = { | 217 | .dev = { |
| 210 | .platform_data = &scif1_platform_data, | 218 | .platform_data = &scif1_platform_data, |
| 211 | }, | 219 | }, |
| 212 | }; | 220 | }; |
| 213 | 221 | ||
| 214 | static struct plat_sci_port scif2_platform_data = { | 222 | static struct plat_sci_port scif2_platform_data = { |
| 215 | .mapbase = 0xfffe9000, | ||
| 216 | .flags = UPF_BOOT_AUTOCONF, | 223 | .flags = UPF_BOOT_AUTOCONF, |
| 217 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 224 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
| 218 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 219 | .type = PORT_SCIF, | 225 | .type = PORT_SCIF, |
| 220 | .irqs = SCIx_IRQ_MUXED(188), | 226 | }; |
| 227 | |||
| 228 | static struct resource scif2_resources[] = { | ||
| 229 | DEFINE_RES_MEM(0xfffe9000, 0x100), | ||
| 230 | DEFINE_RES_IRQ(188), | ||
| 221 | }; | 231 | }; |
| 222 | 232 | ||
| 223 | static struct platform_device scif2_device = { | 233 | static struct platform_device scif2_device = { |
| 224 | .name = "sh-sci", | 234 | .name = "sh-sci", |
| 225 | .id = 2, | 235 | .id = 2, |
| 236 | .resource = scif2_resources, | ||
| 237 | .num_resources = ARRAY_SIZE(scif2_resources), | ||
| 226 | .dev = { | 238 | .dev = { |
| 227 | .platform_data = &scif2_platform_data, | 239 | .platform_data = &scif2_platform_data, |
| 228 | }, | 240 | }, |
| 229 | }; | 241 | }; |
| 230 | 242 | ||
| 231 | static struct plat_sci_port scif3_platform_data = { | 243 | static struct plat_sci_port scif3_platform_data = { |
| 232 | .mapbase = 0xfffe9800, | ||
| 233 | .flags = UPF_BOOT_AUTOCONF, | 244 | .flags = UPF_BOOT_AUTOCONF, |
| 234 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 245 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
| 235 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 236 | .type = PORT_SCIF, | 246 | .type = PORT_SCIF, |
| 237 | .irqs = SCIx_IRQ_MUXED(192), | 247 | }; |
| 248 | |||
| 249 | static struct resource scif3_resources[] = { | ||
| 250 | DEFINE_RES_MEM(0xfffe9800, 0x100), | ||
| 251 | DEFINE_RES_IRQ(192), | ||
| 238 | }; | 252 | }; |
| 239 | 253 | ||
| 240 | static struct platform_device scif3_device = { | 254 | static struct platform_device scif3_device = { |
| 241 | .name = "sh-sci", | 255 | .name = "sh-sci", |
| 242 | .id = 3, | 256 | .id = 3, |
| 257 | .resource = scif3_resources, | ||
| 258 | .num_resources = ARRAY_SIZE(scif3_resources), | ||
| 243 | .dev = { | 259 | .dev = { |
| 244 | .platform_data = &scif3_platform_data, | 260 | .platform_data = &scif3_platform_data, |
| 245 | }, | 261 | }, |
| 246 | }; | 262 | }; |
| 247 | 263 | ||
| 248 | static struct plat_sci_port scif4_platform_data = { | 264 | static struct plat_sci_port scif4_platform_data = { |
| 249 | .mapbase = 0xfffea000, | ||
| 250 | .flags = UPF_BOOT_AUTOCONF, | 265 | .flags = UPF_BOOT_AUTOCONF, |
| 251 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 266 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
| 252 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 253 | .type = PORT_SCIF, | 267 | .type = PORT_SCIF, |
| 254 | .irqs = SCIx_IRQ_MUXED(196), | 268 | }; |
| 269 | |||
| 270 | static struct resource scif4_resources[] = { | ||
| 271 | DEFINE_RES_MEM(0xfffea000, 0x100), | ||
| 272 | DEFINE_RES_IRQ(196), | ||
| 255 | }; | 273 | }; |
| 256 | 274 | ||
| 257 | static struct platform_device scif4_device = { | 275 | static struct platform_device scif4_device = { |
| 258 | .name = "sh-sci", | 276 | .name = "sh-sci", |
| 259 | .id = 4, | 277 | .id = 4, |
| 278 | .resource = scif4_resources, | ||
| 279 | .num_resources = ARRAY_SIZE(scif4_resources), | ||
| 260 | .dev = { | 280 | .dev = { |
| 261 | .platform_data = &scif4_platform_data, | 281 | .platform_data = &scif4_platform_data, |
| 262 | }, | 282 | }, |
| 263 | }; | 283 | }; |
| 264 | 284 | ||
| 265 | static struct plat_sci_port scif5_platform_data = { | 285 | static struct plat_sci_port scif5_platform_data = { |
| 266 | .mapbase = 0xfffea800, | ||
| 267 | .flags = UPF_BOOT_AUTOCONF, | 286 | .flags = UPF_BOOT_AUTOCONF, |
| 268 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 287 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
| 269 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 270 | .type = PORT_SCIF, | 288 | .type = PORT_SCIF, |
| 271 | .irqs = SCIx_IRQ_MUXED(200), | 289 | }; |
| 290 | |||
| 291 | static struct resource scif5_resources[] = { | ||
| 292 | DEFINE_RES_MEM(0xfffea800, 0x100), | ||
| 293 | DEFINE_RES_IRQ(200), | ||
| 272 | }; | 294 | }; |
| 273 | 295 | ||
| 274 | static struct platform_device scif5_device = { | 296 | static struct platform_device scif5_device = { |
| 275 | .name = "sh-sci", | 297 | .name = "sh-sci", |
| 276 | .id = 5, | 298 | .id = 5, |
| 299 | .resource = scif5_resources, | ||
| 300 | .num_resources = ARRAY_SIZE(scif5_resources), | ||
| 277 | .dev = { | 301 | .dev = { |
| 278 | .platform_data = &scif5_platform_data, | 302 | .platform_data = &scif5_platform_data, |
| 279 | }, | 303 | }, |
| 280 | }; | 304 | }; |
| 281 | 305 | ||
| 282 | static struct plat_sci_port scif6_platform_data = { | 306 | static struct plat_sci_port scif6_platform_data = { |
| 283 | .mapbase = 0xfffeb000, | ||
| 284 | .flags = UPF_BOOT_AUTOCONF, | 307 | .flags = UPF_BOOT_AUTOCONF, |
| 285 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 308 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
| 286 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 287 | .type = PORT_SCIF, | 309 | .type = PORT_SCIF, |
| 288 | .irqs = SCIx_IRQ_MUXED(204), | 310 | }; |
| 311 | |||
| 312 | static struct resource scif6_resources[] = { | ||
| 313 | DEFINE_RES_MEM(0xfffeb000, 0x100), | ||
| 314 | DEFINE_RES_IRQ(204), | ||
| 289 | }; | 315 | }; |
| 290 | 316 | ||
| 291 | static struct platform_device scif6_device = { | 317 | static struct platform_device scif6_device = { |
| 292 | .name = "sh-sci", | 318 | .name = "sh-sci", |
| 293 | .id = 6, | 319 | .id = 6, |
| 320 | .resource = scif6_resources, | ||
| 321 | .num_resources = ARRAY_SIZE(scif6_resources), | ||
| 294 | .dev = { | 322 | .dev = { |
| 295 | .platform_data = &scif6_platform_data, | 323 | .platform_data = &scif6_platform_data, |
| 296 | }, | 324 | }, |
| 297 | }; | 325 | }; |
| 298 | 326 | ||
| 299 | static struct plat_sci_port scif7_platform_data = { | 327 | static struct plat_sci_port scif7_platform_data = { |
| 300 | .mapbase = 0xfffeb800, | ||
| 301 | .flags = UPF_BOOT_AUTOCONF, | 328 | .flags = UPF_BOOT_AUTOCONF, |
| 302 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 329 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
| 303 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 304 | .type = PORT_SCIF, | 330 | .type = PORT_SCIF, |
| 305 | .irqs = SCIx_IRQ_MUXED(208), | 331 | }; |
| 332 | |||
| 333 | static struct resource scif7_resources[] = { | ||
| 334 | DEFINE_RES_MEM(0xfffeb800, 0x100), | ||
| 335 | DEFINE_RES_IRQ(208), | ||
| 306 | }; | 336 | }; |
| 307 | 337 | ||
| 308 | static struct platform_device scif7_device = { | 338 | static struct platform_device scif7_device = { |
| 309 | .name = "sh-sci", | 339 | .name = "sh-sci", |
| 310 | .id = 7, | 340 | .id = 7, |
| 341 | .resource = scif7_resources, | ||
| 342 | .num_resources = ARRAY_SIZE(scif7_resources), | ||
| 311 | .dev = { | 343 | .dev = { |
| 312 | .platform_data = &scif7_platform_data, | 344 | .platform_data = &scif7_platform_data, |
| 313 | }, | 345 | }, |
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c index bfc33f6a28c3..d55a0f30ada3 100644 --- a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c +++ b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c | |||
| @@ -174,76 +174,92 @@ static DECLARE_INTC_DESC(intc_desc, "sh7203", vectors, groups, | |||
| 174 | mask_registers, prio_registers, NULL); | 174 | mask_registers, prio_registers, NULL); |
| 175 | 175 | ||
| 176 | static struct plat_sci_port scif0_platform_data = { | 176 | static struct plat_sci_port scif0_platform_data = { |
| 177 | .mapbase = 0xfffe8000, | ||
| 178 | .flags = UPF_BOOT_AUTOCONF, | 177 | .flags = UPF_BOOT_AUTOCONF, |
| 179 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | | 178 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | |
| 180 | SCSCR_REIE, | 179 | SCSCR_REIE, |
| 181 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 182 | .type = PORT_SCIF, | 180 | .type = PORT_SCIF, |
| 183 | .irqs = SCIx_IRQ_MUXED(192), | ||
| 184 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, | 181 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, |
| 185 | }; | 182 | }; |
| 186 | 183 | ||
| 184 | static struct resource scif0_resources[] = { | ||
| 185 | DEFINE_RES_MEM(0xfffe8000, 0x100), | ||
| 186 | DEFINE_RES_IRQ(192), | ||
| 187 | }; | ||
| 188 | |||
| 187 | static struct platform_device scif0_device = { | 189 | static struct platform_device scif0_device = { |
| 188 | .name = "sh-sci", | 190 | .name = "sh-sci", |
| 189 | .id = 0, | 191 | .id = 0, |
| 192 | .resource = scif0_resources, | ||
| 193 | .num_resources = ARRAY_SIZE(scif0_resources), | ||
| 190 | .dev = { | 194 | .dev = { |
| 191 | .platform_data = &scif0_platform_data, | 195 | .platform_data = &scif0_platform_data, |
| 192 | }, | 196 | }, |
| 193 | }; | 197 | }; |
| 194 | 198 | ||
| 195 | static struct plat_sci_port scif1_platform_data = { | 199 | static struct plat_sci_port scif1_platform_data = { |
| 196 | .mapbase = 0xfffe8800, | ||
| 197 | .flags = UPF_BOOT_AUTOCONF, | 200 | .flags = UPF_BOOT_AUTOCONF, |
| 198 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | | 201 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | |
| 199 | SCSCR_REIE, | 202 | SCSCR_REIE, |
| 200 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 201 | .type = PORT_SCIF, | 203 | .type = PORT_SCIF, |
| 202 | .irqs = SCIx_IRQ_MUXED(196), | ||
| 203 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, | 204 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, |
| 204 | }; | 205 | }; |
| 205 | 206 | ||
| 207 | static struct resource scif1_resources[] = { | ||
| 208 | DEFINE_RES_MEM(0xfffe8800, 0x100), | ||
| 209 | DEFINE_RES_IRQ(196), | ||
| 210 | }; | ||
| 211 | |||
| 206 | static struct platform_device scif1_device = { | 212 | static struct platform_device scif1_device = { |
| 207 | .name = "sh-sci", | 213 | .name = "sh-sci", |
| 208 | .id = 1, | 214 | .id = 1, |
| 215 | .resource = scif1_resources, | ||
| 216 | .num_resources = ARRAY_SIZE(scif1_resources), | ||
| 209 | .dev = { | 217 | .dev = { |
| 210 | .platform_data = &scif1_platform_data, | 218 | .platform_data = &scif1_platform_data, |
| 211 | }, | 219 | }, |
| 212 | }; | 220 | }; |
| 213 | 221 | ||
| 214 | static struct plat_sci_port scif2_platform_data = { | 222 | static struct plat_sci_port scif2_platform_data = { |
| 215 | .mapbase = 0xfffe9000, | ||
| 216 | .flags = UPF_BOOT_AUTOCONF, | 223 | .flags = UPF_BOOT_AUTOCONF, |
| 217 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | | 224 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | |
| 218 | SCSCR_REIE, | 225 | SCSCR_REIE, |
| 219 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 220 | .type = PORT_SCIF, | 226 | .type = PORT_SCIF, |
| 221 | .irqs = SCIx_IRQ_MUXED(200), | ||
| 222 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, | 227 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, |
| 223 | }; | 228 | }; |
| 224 | 229 | ||
| 230 | static struct resource scif2_resources[] = { | ||
| 231 | DEFINE_RES_MEM(0xfffe9000, 0x100), | ||
| 232 | DEFINE_RES_IRQ(200), | ||
| 233 | }; | ||
| 234 | |||
| 225 | static struct platform_device scif2_device = { | 235 | static struct platform_device scif2_device = { |
| 226 | .name = "sh-sci", | 236 | .name = "sh-sci", |
| 227 | .id = 2, | 237 | .id = 2, |
| 238 | .resource = scif2_resources, | ||
| 239 | .num_resources = ARRAY_SIZE(scif2_resources), | ||
| 228 | .dev = { | 240 | .dev = { |
| 229 | .platform_data = &scif2_platform_data, | 241 | .platform_data = &scif2_platform_data, |
| 230 | }, | 242 | }, |
| 231 | }; | 243 | }; |
| 232 | 244 | ||
| 233 | static struct plat_sci_port scif3_platform_data = { | 245 | static struct plat_sci_port scif3_platform_data = { |
| 234 | .mapbase = 0xfffe9800, | ||
| 235 | .flags = UPF_BOOT_AUTOCONF, | 246 | .flags = UPF_BOOT_AUTOCONF, |
| 236 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | | 247 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | |
| 237 | SCSCR_REIE, | 248 | SCSCR_REIE, |
| 238 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 239 | .type = PORT_SCIF, | 249 | .type = PORT_SCIF, |
| 240 | .irqs = SCIx_IRQ_MUXED(204), | ||
| 241 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, | 250 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, |
| 242 | }; | 251 | }; |
| 243 | 252 | ||
| 253 | static struct resource scif3_resources[] = { | ||
| 254 | DEFINE_RES_MEM(0xfffe9800, 0x100), | ||
| 255 | DEFINE_RES_IRQ(204), | ||
| 256 | }; | ||
| 257 | |||
| 244 | static struct platform_device scif3_device = { | 258 | static struct platform_device scif3_device = { |
| 245 | .name = "sh-sci", | 259 | .name = "sh-sci", |
| 246 | .id = 3, | 260 | .id = 3, |
| 261 | .resource = scif3_resources, | ||
| 262 | .num_resources = ARRAY_SIZE(scif3_resources), | ||
| 247 | .dev = { | 263 | .dev = { |
| 248 | .platform_data = &scif3_platform_data, | 264 | .platform_data = &scif3_platform_data, |
| 249 | }, | 265 | }, |
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c index a5010741de85..241e745e3ced 100644 --- a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c +++ b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c | |||
| @@ -134,68 +134,84 @@ static DECLARE_INTC_DESC(intc_desc, "sh7206", vectors, groups, | |||
| 134 | mask_registers, prio_registers, NULL); | 134 | mask_registers, prio_registers, NULL); |
| 135 | 135 | ||
| 136 | static struct plat_sci_port scif0_platform_data = { | 136 | static struct plat_sci_port scif0_platform_data = { |
| 137 | .mapbase = 0xfffe8000, | ||
| 138 | .flags = UPF_BOOT_AUTOCONF, | 137 | .flags = UPF_BOOT_AUTOCONF, |
| 139 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 138 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
| 140 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 141 | .type = PORT_SCIF, | 139 | .type = PORT_SCIF, |
| 142 | .irqs = SCIx_IRQ_MUXED(240), | 140 | }; |
| 141 | |||
| 142 | static struct resource scif0_resources[] = { | ||
| 143 | DEFINE_RES_MEM(0xfffe8000, 0x100), | ||
| 144 | DEFINE_RES_IRQ(240), | ||
| 143 | }; | 145 | }; |
| 144 | 146 | ||
| 145 | static struct platform_device scif0_device = { | 147 | static struct platform_device scif0_device = { |
| 146 | .name = "sh-sci", | 148 | .name = "sh-sci", |
| 147 | .id = 0, | 149 | .id = 0, |
| 150 | .resource = scif0_resources, | ||
| 151 | .num_resources = ARRAY_SIZE(scif0_resources), | ||
| 148 | .dev = { | 152 | .dev = { |
| 149 | .platform_data = &scif0_platform_data, | 153 | .platform_data = &scif0_platform_data, |
| 150 | }, | 154 | }, |
| 151 | }; | 155 | }; |
| 152 | 156 | ||
| 153 | static struct plat_sci_port scif1_platform_data = { | 157 | static struct plat_sci_port scif1_platform_data = { |
| 154 | .mapbase = 0xfffe8800, | ||
| 155 | .flags = UPF_BOOT_AUTOCONF, | 158 | .flags = UPF_BOOT_AUTOCONF, |
| 156 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 159 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
| 157 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 158 | .type = PORT_SCIF, | 160 | .type = PORT_SCIF, |
| 159 | .irqs = SCIx_IRQ_MUXED(244), | 161 | }; |
| 162 | |||
| 163 | static struct resource scif1_resources[] = { | ||
| 164 | DEFINE_RES_MEM(0xfffe8800, 0x100), | ||
| 165 | DEFINE_RES_IRQ(244), | ||
| 160 | }; | 166 | }; |
| 161 | 167 | ||
| 162 | static struct platform_device scif1_device = { | 168 | static struct platform_device scif1_device = { |
| 163 | .name = "sh-sci", | 169 | .name = "sh-sci", |
| 164 | .id = 1, | 170 | .id = 1, |
| 171 | .resource = scif1_resources, | ||
| 172 | .num_resources = ARRAY_SIZE(scif1_resources), | ||
| 165 | .dev = { | 173 | .dev = { |
| 166 | .platform_data = &scif1_platform_data, | 174 | .platform_data = &scif1_platform_data, |
| 167 | }, | 175 | }, |
| 168 | }; | 176 | }; |
| 169 | 177 | ||
| 170 | static struct plat_sci_port scif2_platform_data = { | 178 | static struct plat_sci_port scif2_platform_data = { |
| 171 | .mapbase = 0xfffe9000, | ||
| 172 | .flags = UPF_BOOT_AUTOCONF, | 179 | .flags = UPF_BOOT_AUTOCONF, |
| 173 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 180 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
| 174 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 175 | .type = PORT_SCIF, | 181 | .type = PORT_SCIF, |
| 176 | .irqs = SCIx_IRQ_MUXED(248), | 182 | }; |
| 183 | |||
| 184 | static struct resource scif2_resources[] = { | ||
| 185 | DEFINE_RES_MEM(0xfffe9000, 0x100), | ||
| 186 | DEFINE_RES_IRQ(248), | ||
| 177 | }; | 187 | }; |
| 178 | 188 | ||
| 179 | static struct platform_device scif2_device = { | 189 | static struct platform_device scif2_device = { |
| 180 | .name = "sh-sci", | 190 | .name = "sh-sci", |
| 181 | .id = 2, | 191 | .id = 2, |
| 192 | .resource = scif2_resources, | ||
| 193 | .num_resources = ARRAY_SIZE(scif2_resources), | ||
| 182 | .dev = { | 194 | .dev = { |
| 183 | .platform_data = &scif2_platform_data, | 195 | .platform_data = &scif2_platform_data, |
| 184 | }, | 196 | }, |
| 185 | }; | 197 | }; |
| 186 | 198 | ||
| 187 | static struct plat_sci_port scif3_platform_data = { | 199 | static struct plat_sci_port scif3_platform_data = { |
| 188 | .mapbase = 0xfffe9800, | ||
| 189 | .flags = UPF_BOOT_AUTOCONF, | 200 | .flags = UPF_BOOT_AUTOCONF, |
| 190 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 201 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
| 191 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 192 | .type = PORT_SCIF, | 202 | .type = PORT_SCIF, |
| 193 | .irqs = SCIx_IRQ_MUXED(252), | 203 | }; |
| 204 | |||
| 205 | static struct resource scif3_resources[] = { | ||
| 206 | DEFINE_RES_MEM(0xfffe9800, 0x100), | ||
| 207 | DEFINE_RES_IRQ(252), | ||
| 194 | }; | 208 | }; |
| 195 | 209 | ||
| 196 | static struct platform_device scif3_device = { | 210 | static struct platform_device scif3_device = { |
| 197 | .name = "sh-sci", | 211 | .name = "sh-sci", |
| 198 | .id = 3, | 212 | .id = 3, |
| 213 | .resource = scif3_resources, | ||
| 214 | .num_resources = ARRAY_SIZE(scif3_resources), | ||
| 199 | .dev = { | 215 | .dev = { |
| 200 | .platform_data = &scif3_platform_data, | 216 | .platform_data = &scif3_platform_data, |
| 201 | }, | 217 | }, |
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7264.c b/arch/sh/kernel/cpu/sh2a/setup-sh7264.c index ce5c1b5aebfa..ad5b0f429882 100644 --- a/arch/sh/kernel/cpu/sh2a/setup-sh7264.c +++ b/arch/sh/kernel/cpu/sh2a/setup-sh7264.c | |||
| @@ -226,152 +226,208 @@ static DECLARE_INTC_DESC(intc_desc, "sh7264", vectors, groups, | |||
| 226 | mask_registers, prio_registers, NULL); | 226 | mask_registers, prio_registers, NULL); |
| 227 | 227 | ||
| 228 | static struct plat_sci_port scif0_platform_data = { | 228 | static struct plat_sci_port scif0_platform_data = { |
| 229 | .mapbase = 0xfffe8000, | ||
| 230 | .flags = UPF_BOOT_AUTOCONF, | 229 | .flags = UPF_BOOT_AUTOCONF, |
| 231 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | | 230 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | |
| 232 | SCSCR_REIE | SCSCR_TOIE, | 231 | SCSCR_REIE | SCSCR_TOIE, |
| 233 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 234 | .type = PORT_SCIF, | 232 | .type = PORT_SCIF, |
| 235 | .irqs = { 233, 234, 235, 232 }, | ||
| 236 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, | 233 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, |
| 237 | }; | 234 | }; |
| 238 | 235 | ||
| 236 | static struct resource scif0_resources[] = { | ||
| 237 | DEFINE_RES_MEM(0xfffe8000, 0x100), | ||
| 238 | DEFINE_RES_IRQ(233), | ||
| 239 | DEFINE_RES_IRQ(234), | ||
| 240 | DEFINE_RES_IRQ(235), | ||
| 241 | DEFINE_RES_IRQ(232), | ||
| 242 | }; | ||
| 243 | |||
| 239 | static struct platform_device scif0_device = { | 244 | static struct platform_device scif0_device = { |
| 240 | .name = "sh-sci", | 245 | .name = "sh-sci", |
| 241 | .id = 0, | 246 | .id = 0, |
| 247 | .resource = scif0_resources, | ||
| 248 | .num_resources = ARRAY_SIZE(scif0_resources), | ||
| 242 | .dev = { | 249 | .dev = { |
| 243 | .platform_data = &scif0_platform_data, | 250 | .platform_data = &scif0_platform_data, |
| 244 | }, | 251 | }, |
| 245 | }; | 252 | }; |
| 246 | 253 | ||
| 247 | static struct plat_sci_port scif1_platform_data = { | 254 | static struct plat_sci_port scif1_platform_data = { |
| 248 | .mapbase = 0xfffe8800, | ||
| 249 | .flags = UPF_BOOT_AUTOCONF, | 255 | .flags = UPF_BOOT_AUTOCONF, |
| 250 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | | 256 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | |
| 251 | SCSCR_REIE | SCSCR_TOIE, | 257 | SCSCR_REIE | SCSCR_TOIE, |
| 252 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 253 | .type = PORT_SCIF, | 258 | .type = PORT_SCIF, |
| 254 | .irqs = { 237, 238, 239, 236 }, | ||
| 255 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, | 259 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, |
| 256 | }; | 260 | }; |
| 257 | 261 | ||
| 262 | static struct resource scif1_resources[] = { | ||
| 263 | DEFINE_RES_MEM(0xfffe8800, 0x100), | ||
| 264 | DEFINE_RES_IRQ(237), | ||
| 265 | DEFINE_RES_IRQ(238), | ||
| 266 | DEFINE_RES_IRQ(239), | ||
| 267 | DEFINE_RES_IRQ(236), | ||
| 268 | }; | ||
| 269 | |||
| 258 | static struct platform_device scif1_device = { | 270 | static struct platform_device scif1_device = { |
| 259 | .name = "sh-sci", | 271 | .name = "sh-sci", |
| 260 | .id = 1, | 272 | .id = 1, |
| 273 | .resource = scif1_resources, | ||
| 274 | .num_resources = ARRAY_SIZE(scif1_resources), | ||
| 261 | .dev = { | 275 | .dev = { |
| 262 | .platform_data = &scif1_platform_data, | 276 | .platform_data = &scif1_platform_data, |
| 263 | }, | 277 | }, |
| 264 | }; | 278 | }; |
| 265 | 279 | ||
| 266 | static struct plat_sci_port scif2_platform_data = { | 280 | static struct plat_sci_port scif2_platform_data = { |
| 267 | .mapbase = 0xfffe9000, | ||
| 268 | .flags = UPF_BOOT_AUTOCONF, | 281 | .flags = UPF_BOOT_AUTOCONF, |
| 269 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | | 282 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | |
| 270 | SCSCR_REIE | SCSCR_TOIE, | 283 | SCSCR_REIE | SCSCR_TOIE, |
| 271 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 272 | .type = PORT_SCIF, | 284 | .type = PORT_SCIF, |
| 273 | .irqs = { 241, 242, 243, 240 }, | ||
| 274 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, | 285 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, |
| 275 | }; | 286 | }; |
| 276 | 287 | ||
| 288 | static struct resource scif2_resources[] = { | ||
| 289 | DEFINE_RES_MEM(0xfffe9000, 0x100), | ||
| 290 | DEFINE_RES_IRQ(241), | ||
| 291 | DEFINE_RES_IRQ(242), | ||
| 292 | DEFINE_RES_IRQ(243), | ||
| 293 | DEFINE_RES_IRQ(240), | ||
| 294 | }; | ||
| 295 | |||
| 277 | static struct platform_device scif2_device = { | 296 | static struct platform_device scif2_device = { |
| 278 | .name = "sh-sci", | 297 | .name = "sh-sci", |
| 279 | .id = 2, | 298 | .id = 2, |
| 299 | .resource = scif2_resources, | ||
| 300 | .num_resources = ARRAY_SIZE(scif2_resources), | ||
| 280 | .dev = { | 301 | .dev = { |
| 281 | .platform_data = &scif2_platform_data, | 302 | .platform_data = &scif2_platform_data, |
| 282 | }, | 303 | }, |
| 283 | }; | 304 | }; |
| 284 | 305 | ||
| 285 | static struct plat_sci_port scif3_platform_data = { | 306 | static struct plat_sci_port scif3_platform_data = { |
| 286 | .mapbase = 0xfffe9800, | ||
| 287 | .flags = UPF_BOOT_AUTOCONF, | 307 | .flags = UPF_BOOT_AUTOCONF, |
| 288 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | | 308 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | |
| 289 | SCSCR_REIE | SCSCR_TOIE, | 309 | SCSCR_REIE | SCSCR_TOIE, |
| 290 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 291 | .type = PORT_SCIF, | 310 | .type = PORT_SCIF, |
| 292 | .irqs = { 245, 246, 247, 244 }, | ||
| 293 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, | 311 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, |
| 294 | }; | 312 | }; |
| 295 | 313 | ||
| 314 | static struct resource scif3_resources[] = { | ||
| 315 | DEFINE_RES_MEM(0xfffe9800, 0x100), | ||
| 316 | DEFINE_RES_IRQ(245), | ||
| 317 | DEFINE_RES_IRQ(246), | ||
| 318 | DEFINE_RES_IRQ(247), | ||
| 319 | DEFINE_RES_IRQ(244), | ||
| 320 | }; | ||
| 321 | |||
| 296 | static struct platform_device scif3_device = { | 322 | static struct platform_device scif3_device = { |
| 297 | .name = "sh-sci", | 323 | .name = "sh-sci", |
| 298 | .id = 3, | 324 | .id = 3, |
| 325 | .resource = scif3_resources, | ||
| 326 | .num_resources = ARRAY_SIZE(scif3_resources), | ||
| 299 | .dev = { | 327 | .dev = { |
| 300 | .platform_data = &scif3_platform_data, | 328 | .platform_data = &scif3_platform_data, |
| 301 | }, | 329 | }, |
| 302 | }; | 330 | }; |
| 303 | 331 | ||
| 304 | static struct plat_sci_port scif4_platform_data = { | 332 | static struct plat_sci_port scif4_platform_data = { |
| 305 | .mapbase = 0xfffea000, | ||
| 306 | .flags = UPF_BOOT_AUTOCONF, | 333 | .flags = UPF_BOOT_AUTOCONF, |
| 307 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | | 334 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | |
| 308 | SCSCR_REIE | SCSCR_TOIE, | 335 | SCSCR_REIE | SCSCR_TOIE, |
| 309 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 310 | .type = PORT_SCIF, | 336 | .type = PORT_SCIF, |
| 311 | .irqs = { 249, 250, 251, 248 }, | ||
| 312 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, | 337 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, |
| 313 | }; | 338 | }; |
| 314 | 339 | ||
| 340 | static struct resource scif4_resources[] = { | ||
| 341 | DEFINE_RES_MEM(0xfffea000, 0x100), | ||
| 342 | DEFINE_RES_IRQ(249), | ||
| 343 | DEFINE_RES_IRQ(250), | ||
| 344 | DEFINE_RES_IRQ(251), | ||
| 345 | DEFINE_RES_IRQ(248), | ||
| 346 | }; | ||
| 347 | |||
| 315 | static struct platform_device scif4_device = { | 348 | static struct platform_device scif4_device = { |
| 316 | .name = "sh-sci", | 349 | .name = "sh-sci", |
| 317 | .id = 4, | 350 | .id = 4, |
| 351 | .resource = scif4_resources, | ||
| 352 | .num_resources = ARRAY_SIZE(scif4_resources), | ||
| 318 | .dev = { | 353 | .dev = { |
| 319 | .platform_data = &scif4_platform_data, | 354 | .platform_data = &scif4_platform_data, |
| 320 | }, | 355 | }, |
| 321 | }; | 356 | }; |
| 322 | 357 | ||
| 323 | static struct plat_sci_port scif5_platform_data = { | 358 | static struct plat_sci_port scif5_platform_data = { |
| 324 | .mapbase = 0xfffea800, | ||
| 325 | .flags = UPF_BOOT_AUTOCONF, | 359 | .flags = UPF_BOOT_AUTOCONF, |
| 326 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | | 360 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | |
| 327 | SCSCR_REIE | SCSCR_TOIE, | 361 | SCSCR_REIE | SCSCR_TOIE, |
| 328 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 329 | .type = PORT_SCIF, | 362 | .type = PORT_SCIF, |
| 330 | .irqs = { 253, 254, 255, 252 }, | ||
| 331 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, | 363 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, |
| 332 | }; | 364 | }; |
| 333 | 365 | ||
| 366 | static struct resource scif5_resources[] = { | ||
| 367 | DEFINE_RES_MEM(0xfffea800, 0x100), | ||
| 368 | DEFINE_RES_IRQ(253), | ||
| 369 | DEFINE_RES_IRQ(254), | ||
| 370 | DEFINE_RES_IRQ(255), | ||
| 371 | DEFINE_RES_IRQ(252), | ||
| 372 | }; | ||
| 373 | |||
| 334 | static struct platform_device scif5_device = { | 374 | static struct platform_device scif5_device = { |
| 335 | .name = "sh-sci", | 375 | .name = "sh-sci", |
| 336 | .id = 5, | 376 | .id = 5, |
| 377 | .resource = scif5_resources, | ||
| 378 | .num_resources = ARRAY_SIZE(scif5_resources), | ||
| 337 | .dev = { | 379 | .dev = { |
| 338 | .platform_data = &scif5_platform_data, | 380 | .platform_data = &scif5_platform_data, |
| 339 | }, | 381 | }, |
| 340 | }; | 382 | }; |
| 341 | 383 | ||
| 342 | static struct plat_sci_port scif6_platform_data = { | 384 | static struct plat_sci_port scif6_platform_data = { |
| 343 | .mapbase = 0xfffeb000, | ||
| 344 | .flags = UPF_BOOT_AUTOCONF, | 385 | .flags = UPF_BOOT_AUTOCONF, |
| 345 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | | 386 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | |
| 346 | SCSCR_REIE | SCSCR_TOIE, | 387 | SCSCR_REIE | SCSCR_TOIE, |
| 347 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 348 | .type = PORT_SCIF, | 388 | .type = PORT_SCIF, |
| 349 | .irqs = { 257, 258, 259, 256 }, | ||
| 350 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, | 389 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, |
| 351 | }; | 390 | }; |
| 352 | 391 | ||
| 392 | static struct resource scif6_resources[] = { | ||
| 393 | DEFINE_RES_MEM(0xfffeb000, 0x100), | ||
| 394 | DEFINE_RES_IRQ(257), | ||
| 395 | DEFINE_RES_IRQ(258), | ||
| 396 | DEFINE_RES_IRQ(259), | ||
| 397 | DEFINE_RES_IRQ(256), | ||
| 398 | }; | ||
| 399 | |||
| 353 | static struct platform_device scif6_device = { | 400 | static struct platform_device scif6_device = { |
| 354 | .name = "sh-sci", | 401 | .name = "sh-sci", |
| 355 | .id = 6, | 402 | .id = 6, |
| 403 | .resource = scif6_resources, | ||
| 404 | .num_resources = ARRAY_SIZE(scif6_resources), | ||
| 356 | .dev = { | 405 | .dev = { |
| 357 | .platform_data = &scif6_platform_data, | 406 | .platform_data = &scif6_platform_data, |
| 358 | }, | 407 | }, |
| 359 | }; | 408 | }; |
| 360 | 409 | ||
| 361 | static struct plat_sci_port scif7_platform_data = { | 410 | static struct plat_sci_port scif7_platform_data = { |
| 362 | .mapbase = 0xfffeb800, | ||
| 363 | .flags = UPF_BOOT_AUTOCONF, | 411 | .flags = UPF_BOOT_AUTOCONF, |
| 364 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | | 412 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | |
| 365 | SCSCR_REIE | SCSCR_TOIE, | 413 | SCSCR_REIE | SCSCR_TOIE, |
| 366 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 367 | .type = PORT_SCIF, | 414 | .type = PORT_SCIF, |
| 368 | .irqs = { 261, 262, 263, 260 }, | ||
| 369 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, | 415 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, |
| 370 | }; | 416 | }; |
| 371 | 417 | ||
| 418 | static struct resource scif7_resources[] = { | ||
| 419 | DEFINE_RES_MEM(0xfffeb800, 0x100), | ||
| 420 | DEFINE_RES_IRQ(261), | ||
| 421 | DEFINE_RES_IRQ(262), | ||
| 422 | DEFINE_RES_IRQ(263), | ||
| 423 | DEFINE_RES_IRQ(260), | ||
| 424 | }; | ||
| 425 | |||
| 372 | static struct platform_device scif7_device = { | 426 | static struct platform_device scif7_device = { |
| 373 | .name = "sh-sci", | 427 | .name = "sh-sci", |
| 374 | .id = 7, | 428 | .id = 7, |
| 429 | .resource = scif7_resources, | ||
| 430 | .num_resources = ARRAY_SIZE(scif7_resources), | ||
| 375 | .dev = { | 431 | .dev = { |
| 376 | .platform_data = &scif7_platform_data, | 432 | .platform_data = &scif7_platform_data, |
| 377 | }, | 433 | }, |
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7269.c b/arch/sh/kernel/cpu/sh2a/setup-sh7269.c index e82ae9d8d3bc..3995119f65dc 100644 --- a/arch/sh/kernel/cpu/sh2a/setup-sh7269.c +++ b/arch/sh/kernel/cpu/sh2a/setup-sh7269.c | |||
| @@ -248,152 +248,208 @@ static DECLARE_INTC_DESC(intc_desc, "sh7269", vectors, groups, | |||
| 248 | mask_registers, prio_registers, NULL); | 248 | mask_registers, prio_registers, NULL); |
| 249 | 249 | ||
| 250 | static struct plat_sci_port scif0_platform_data = { | 250 | static struct plat_sci_port scif0_platform_data = { |
| 251 | .mapbase = 0xe8007000, | ||
| 252 | .flags = UPF_BOOT_AUTOCONF, | 251 | .flags = UPF_BOOT_AUTOCONF, |
| 253 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | | 252 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | |
| 254 | SCSCR_REIE | SCSCR_TOIE, | 253 | SCSCR_REIE | SCSCR_TOIE, |
| 255 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 256 | .type = PORT_SCIF, | 254 | .type = PORT_SCIF, |
| 257 | .irqs = { 259, 260, 261, 258 }, | ||
| 258 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, | 255 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, |
| 259 | }; | 256 | }; |
| 260 | 257 | ||
| 258 | static struct resource scif0_resources[] = { | ||
| 259 | DEFINE_RES_MEM(0xe8007000, 0x100), | ||
| 260 | DEFINE_RES_IRQ(259), | ||
| 261 | DEFINE_RES_IRQ(260), | ||
| 262 | DEFINE_RES_IRQ(261), | ||
| 263 | DEFINE_RES_IRQ(258), | ||
| 264 | }; | ||
| 265 | |||
| 261 | static struct platform_device scif0_device = { | 266 | static struct platform_device scif0_device = { |
| 262 | .name = "sh-sci", | 267 | .name = "sh-sci", |
| 263 | .id = 0, | 268 | .id = 0, |
| 269 | .resource = scif0_resources, | ||
| 270 | .num_resources = ARRAY_SIZE(scif0_resources), | ||
| 264 | .dev = { | 271 | .dev = { |
| 265 | .platform_data = &scif0_platform_data, | 272 | .platform_data = &scif0_platform_data, |
| 266 | }, | 273 | }, |
| 267 | }; | 274 | }; |
| 268 | 275 | ||
| 269 | static struct plat_sci_port scif1_platform_data = { | 276 | static struct plat_sci_port scif1_platform_data = { |
| 270 | .mapbase = 0xe8007800, | ||
| 271 | .flags = UPF_BOOT_AUTOCONF, | 277 | .flags = UPF_BOOT_AUTOCONF, |
| 272 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | | 278 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | |
| 273 | SCSCR_REIE | SCSCR_TOIE, | 279 | SCSCR_REIE | SCSCR_TOIE, |
| 274 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 275 | .type = PORT_SCIF, | 280 | .type = PORT_SCIF, |
| 276 | .irqs = { 263, 264, 265, 262 }, | ||
| 277 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, | 281 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, |
| 278 | }; | 282 | }; |
| 279 | 283 | ||
| 284 | static struct resource scif1_resources[] = { | ||
| 285 | DEFINE_RES_MEM(0xe8007800, 0x100), | ||
| 286 | DEFINE_RES_IRQ(263), | ||
| 287 | DEFINE_RES_IRQ(264), | ||
| 288 | DEFINE_RES_IRQ(265), | ||
| 289 | DEFINE_RES_IRQ(262), | ||
| 290 | }; | ||
| 291 | |||
| 280 | static struct platform_device scif1_device = { | 292 | static struct platform_device scif1_device = { |
| 281 | .name = "sh-sci", | 293 | .name = "sh-sci", |
| 282 | .id = 1, | 294 | .id = 1, |
| 295 | .resource = scif1_resources, | ||
| 296 | .num_resources = ARRAY_SIZE(scif1_resources), | ||
| 283 | .dev = { | 297 | .dev = { |
| 284 | .platform_data = &scif1_platform_data, | 298 | .platform_data = &scif1_platform_data, |
| 285 | }, | 299 | }, |
| 286 | }; | 300 | }; |
| 287 | 301 | ||
| 288 | static struct plat_sci_port scif2_platform_data = { | 302 | static struct plat_sci_port scif2_platform_data = { |
| 289 | .mapbase = 0xe8008000, | ||
| 290 | .flags = UPF_BOOT_AUTOCONF, | 303 | .flags = UPF_BOOT_AUTOCONF, |
| 291 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | | 304 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | |
| 292 | SCSCR_REIE | SCSCR_TOIE, | 305 | SCSCR_REIE | SCSCR_TOIE, |
| 293 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 294 | .type = PORT_SCIF, | 306 | .type = PORT_SCIF, |
| 295 | .irqs = { 267, 268, 269, 266 }, | ||
| 296 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, | 307 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, |
| 297 | }; | 308 | }; |
| 298 | 309 | ||
| 310 | static struct resource scif2_resources[] = { | ||
| 311 | DEFINE_RES_MEM(0xe8008000, 0x100), | ||
| 312 | DEFINE_RES_IRQ(267), | ||
| 313 | DEFINE_RES_IRQ(268), | ||
| 314 | DEFINE_RES_IRQ(269), | ||
| 315 | DEFINE_RES_IRQ(266), | ||
| 316 | }; | ||
| 317 | |||
| 299 | static struct platform_device scif2_device = { | 318 | static struct platform_device scif2_device = { |
| 300 | .name = "sh-sci", | 319 | .name = "sh-sci", |
| 301 | .id = 2, | 320 | .id = 2, |
| 321 | .resource = scif2_resources, | ||
| 322 | .num_resources = ARRAY_SIZE(scif2_resources), | ||
| 302 | .dev = { | 323 | .dev = { |
| 303 | .platform_data = &scif2_platform_data, | 324 | .platform_data = &scif2_platform_data, |
| 304 | }, | 325 | }, |
| 305 | }; | 326 | }; |
| 306 | 327 | ||
| 307 | static struct plat_sci_port scif3_platform_data = { | 328 | static struct plat_sci_port scif3_platform_data = { |
| 308 | .mapbase = 0xe8008800, | ||
| 309 | .flags = UPF_BOOT_AUTOCONF, | 329 | .flags = UPF_BOOT_AUTOCONF, |
| 310 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | | 330 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | |
| 311 | SCSCR_REIE | SCSCR_TOIE, | 331 | SCSCR_REIE | SCSCR_TOIE, |
| 312 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 313 | .type = PORT_SCIF, | 332 | .type = PORT_SCIF, |
| 314 | .irqs = { 271, 272, 273, 270 }, | ||
| 315 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, | 333 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, |
| 316 | }; | 334 | }; |
| 317 | 335 | ||
| 336 | static struct resource scif3_resources[] = { | ||
| 337 | DEFINE_RES_MEM(0xe8008800, 0x100), | ||
| 338 | DEFINE_RES_IRQ(271), | ||
| 339 | DEFINE_RES_IRQ(272), | ||
| 340 | DEFINE_RES_IRQ(273), | ||
| 341 | DEFINE_RES_IRQ(270), | ||
| 342 | }; | ||
| 343 | |||
| 318 | static struct platform_device scif3_device = { | 344 | static struct platform_device scif3_device = { |
| 319 | .name = "sh-sci", | 345 | .name = "sh-sci", |
| 320 | .id = 3, | 346 | .id = 3, |
| 347 | .resource = scif3_resources, | ||
| 348 | .num_resources = ARRAY_SIZE(scif3_resources), | ||
| 321 | .dev = { | 349 | .dev = { |
| 322 | .platform_data = &scif3_platform_data, | 350 | .platform_data = &scif3_platform_data, |
| 323 | }, | 351 | }, |
| 324 | }; | 352 | }; |
| 325 | 353 | ||
| 326 | static struct plat_sci_port scif4_platform_data = { | 354 | static struct plat_sci_port scif4_platform_data = { |
| 327 | .mapbase = 0xe8009000, | ||
| 328 | .flags = UPF_BOOT_AUTOCONF, | 355 | .flags = UPF_BOOT_AUTOCONF, |
| 329 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | | 356 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | |
| 330 | SCSCR_REIE | SCSCR_TOIE, | 357 | SCSCR_REIE | SCSCR_TOIE, |
| 331 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 332 | .type = PORT_SCIF, | 358 | .type = PORT_SCIF, |
| 333 | .irqs = { 275, 276, 277, 274 }, | ||
| 334 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, | 359 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, |
| 335 | }; | 360 | }; |
| 336 | 361 | ||
| 362 | static struct resource scif4_resources[] = { | ||
| 363 | DEFINE_RES_MEM(0xe8009000, 0x100), | ||
| 364 | DEFINE_RES_IRQ(275), | ||
| 365 | DEFINE_RES_IRQ(276), | ||
| 366 | DEFINE_RES_IRQ(277), | ||
| 367 | DEFINE_RES_IRQ(274), | ||
| 368 | }; | ||
| 369 | |||
| 337 | static struct platform_device scif4_device = { | 370 | static struct platform_device scif4_device = { |
| 338 | .name = "sh-sci", | 371 | .name = "sh-sci", |
| 339 | .id = 4, | 372 | .id = 4, |
| 373 | .resource = scif4_resources, | ||
| 374 | .num_resources = ARRAY_SIZE(scif4_resources), | ||
| 340 | .dev = { | 375 | .dev = { |
| 341 | .platform_data = &scif4_platform_data, | 376 | .platform_data = &scif4_platform_data, |
| 342 | }, | 377 | }, |
| 343 | }; | 378 | }; |
| 344 | 379 | ||
| 345 | static struct plat_sci_port scif5_platform_data = { | 380 | static struct plat_sci_port scif5_platform_data = { |
| 346 | .mapbase = 0xe8009800, | ||
| 347 | .flags = UPF_BOOT_AUTOCONF, | 381 | .flags = UPF_BOOT_AUTOCONF, |
| 348 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | | 382 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | |
| 349 | SCSCR_REIE | SCSCR_TOIE, | 383 | SCSCR_REIE | SCSCR_TOIE, |
| 350 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 351 | .type = PORT_SCIF, | 384 | .type = PORT_SCIF, |
| 352 | .irqs = { 279, 280, 281, 278 }, | ||
| 353 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, | 385 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, |
| 354 | }; | 386 | }; |
| 355 | 387 | ||
| 388 | static struct resource scif5_resources[] = { | ||
| 389 | DEFINE_RES_MEM(0xe8009800, 0x100), | ||
| 390 | DEFINE_RES_IRQ(279), | ||
| 391 | DEFINE_RES_IRQ(280), | ||
| 392 | DEFINE_RES_IRQ(281), | ||
| 393 | DEFINE_RES_IRQ(278), | ||
| 394 | }; | ||
| 395 | |||
| 356 | static struct platform_device scif5_device = { | 396 | static struct platform_device scif5_device = { |
| 357 | .name = "sh-sci", | 397 | .name = "sh-sci", |
| 358 | .id = 5, | 398 | .id = 5, |
| 399 | .resource = scif5_resources, | ||
| 400 | .num_resources = ARRAY_SIZE(scif5_resources), | ||
| 359 | .dev = { | 401 | .dev = { |
| 360 | .platform_data = &scif5_platform_data, | 402 | .platform_data = &scif5_platform_data, |
| 361 | }, | 403 | }, |
| 362 | }; | 404 | }; |
| 363 | 405 | ||
| 364 | static struct plat_sci_port scif6_platform_data = { | 406 | static struct plat_sci_port scif6_platform_data = { |
| 365 | .mapbase = 0xe800a000, | ||
| 366 | .flags = UPF_BOOT_AUTOCONF, | 407 | .flags = UPF_BOOT_AUTOCONF, |
| 367 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | | 408 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | |
| 368 | SCSCR_REIE | SCSCR_TOIE, | 409 | SCSCR_REIE | SCSCR_TOIE, |
| 369 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 370 | .type = PORT_SCIF, | 410 | .type = PORT_SCIF, |
| 371 | .irqs = { 283, 284, 285, 282 }, | ||
| 372 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, | 411 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, |
| 373 | }; | 412 | }; |
| 374 | 413 | ||
| 414 | static struct resource scif6_resources[] = { | ||
| 415 | DEFINE_RES_MEM(0xe800a000, 0x100), | ||
| 416 | DEFINE_RES_IRQ(283), | ||
| 417 | DEFINE_RES_IRQ(284), | ||
| 418 | DEFINE_RES_IRQ(285), | ||
| 419 | DEFINE_RES_IRQ(282), | ||
| 420 | }; | ||
| 421 | |||
| 375 | static struct platform_device scif6_device = { | 422 | static struct platform_device scif6_device = { |
| 376 | .name = "sh-sci", | 423 | .name = "sh-sci", |
| 377 | .id = 6, | 424 | .id = 6, |
| 425 | .resource = scif6_resources, | ||
| 426 | .num_resources = ARRAY_SIZE(scif6_resources), | ||
| 378 | .dev = { | 427 | .dev = { |
| 379 | .platform_data = &scif6_platform_data, | 428 | .platform_data = &scif6_platform_data, |
| 380 | }, | 429 | }, |
| 381 | }; | 430 | }; |
| 382 | 431 | ||
| 383 | static struct plat_sci_port scif7_platform_data = { | 432 | static struct plat_sci_port scif7_platform_data = { |
| 384 | .mapbase = 0xe800a800, | ||
| 385 | .flags = UPF_BOOT_AUTOCONF, | 433 | .flags = UPF_BOOT_AUTOCONF, |
| 386 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | | 434 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | |
| 387 | SCSCR_REIE | SCSCR_TOIE, | 435 | SCSCR_REIE | SCSCR_TOIE, |
| 388 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 389 | .type = PORT_SCIF, | 436 | .type = PORT_SCIF, |
| 390 | .irqs = { 287, 288, 289, 286 }, | ||
| 391 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, | 437 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, |
| 392 | }; | 438 | }; |
| 393 | 439 | ||
| 440 | static struct resource scif7_resources[] = { | ||
| 441 | DEFINE_RES_MEM(0xe800a800, 0x100), | ||
| 442 | DEFINE_RES_IRQ(287), | ||
| 443 | DEFINE_RES_IRQ(288), | ||
| 444 | DEFINE_RES_IRQ(289), | ||
| 445 | DEFINE_RES_IRQ(286), | ||
| 446 | }; | ||
| 447 | |||
| 394 | static struct platform_device scif7_device = { | 448 | static struct platform_device scif7_device = { |
| 395 | .name = "sh-sci", | 449 | .name = "sh-sci", |
| 396 | .id = 7, | 450 | .id = 7, |
| 451 | .resource = scif7_resources, | ||
| 452 | .num_resources = ARRAY_SIZE(scif7_resources), | ||
| 397 | .dev = { | 453 | .dev = { |
| 398 | .platform_data = &scif7_platform_data, | 454 | .platform_data = &scif7_platform_data, |
| 399 | }, | 455 | }, |
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7705.c b/arch/sh/kernel/cpu/sh3/setup-sh7705.c index 03e4c96f2b11..c76b2543b85f 100644 --- a/arch/sh/kernel/cpu/sh3/setup-sh7705.c +++ b/arch/sh/kernel/cpu/sh3/setup-sh7705.c | |||
| @@ -70,39 +70,47 @@ static DECLARE_INTC_DESC(intc_desc, "sh7705", vectors, NULL, | |||
| 70 | NULL, prio_registers, NULL); | 70 | NULL, prio_registers, NULL); |
| 71 | 71 | ||
| 72 | static struct plat_sci_port scif0_platform_data = { | 72 | static struct plat_sci_port scif0_platform_data = { |
| 73 | .mapbase = 0xa4410000, | ||
| 74 | .flags = UPF_BOOT_AUTOCONF, | 73 | .flags = UPF_BOOT_AUTOCONF, |
| 75 | .scscr = SCSCR_TIE | SCSCR_RIE | SCSCR_TE | | 74 | .scscr = SCSCR_TIE | SCSCR_RIE | SCSCR_TE | |
| 76 | SCSCR_RE | SCSCR_CKE1 | SCSCR_CKE0, | 75 | SCSCR_RE | SCSCR_CKE1 | SCSCR_CKE0, |
| 77 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
| 78 | .type = PORT_SCIF, | 76 | .type = PORT_SCIF, |
| 79 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)), | ||
| 80 | .ops = &sh770x_sci_port_ops, | 77 | .ops = &sh770x_sci_port_ops, |
| 81 | .regtype = SCIx_SH7705_SCIF_REGTYPE, | 78 | .regtype = SCIx_SH7705_SCIF_REGTYPE, |
| 82 | }; | 79 | }; |
| 83 | 80 | ||
| 81 | static struct resource scif0_resources[] = { | ||
| 82 | DEFINE_RES_MEM(0xa4410000, 0x100), | ||
| 83 | DEFINE_RES_IRQ(evt2irq(0x900)), | ||
| 84 | }; | ||
| 85 | |||
| 84 | static struct platform_device scif0_device = { | 86 | static struct platform_device scif0_device = { |
| 85 | .name = "sh-sci", | 87 | .name = "sh-sci", |
| 86 | .id = 0, | 88 | .id = 0, |
| 89 | .resource = scif0_resources, | ||
| 90 | .num_resources = ARRAY_SIZE(scif0_resources), | ||
| 87 | .dev = { | 91 | .dev = { |
| 88 | .platform_data = &scif0_platform_data, | 92 | .platform_data = &scif0_platform_data, |
| 89 | }, | 93 | }, |
| 90 | }; | 94 | }; |
| 91 | 95 | ||
| 92 | static struct plat_sci_port scif1_platform_data = { | 96 | static struct plat_sci_port scif1_platform_data = { |
| 93 | .mapbase = 0xa4400000, | ||
| 94 | .flags = UPF_BOOT_AUTOCONF, | 97 | .flags = UPF_BOOT_AUTOCONF, |
| 95 | .scscr = SCSCR_TIE | SCSCR_RIE | SCSCR_TE | SCSCR_RE, | 98 | .scscr = SCSCR_TIE | SCSCR_RIE | SCSCR_TE | SCSCR_RE, |
| 96 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
| 97 | .type = PORT_SCIF, | 99 | .type = PORT_SCIF, |
| 98 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x880)), | ||
| 99 | .ops = &sh770x_sci_port_ops, | 100 | .ops = &sh770x_sci_port_ops, |
| 100 | .regtype = SCIx_SH7705_SCIF_REGTYPE, | 101 | .regtype = SCIx_SH7705_SCIF_REGTYPE, |
| 101 | }; | 102 | }; |
| 102 | 103 | ||
| 104 | static struct resource scif1_resources[] = { | ||
| 105 | DEFINE_RES_MEM(0xa4400000, 0x100), | ||
| 106 | DEFINE_RES_IRQ(evt2irq(0x880)), | ||
| 107 | }; | ||
| 108 | |||
| 103 | static struct platform_device scif1_device = { | 109 | static struct platform_device scif1_device = { |
| 104 | .name = "sh-sci", | 110 | .name = "sh-sci", |
| 105 | .id = 1, | 111 | .id = 1, |
| 112 | .resource = scif1_resources, | ||
| 113 | .num_resources = ARRAY_SIZE(scif1_resources), | ||
| 106 | .dev = { | 114 | .dev = { |
| 107 | .platform_data = &scif1_platform_data, | 115 | .platform_data = &scif1_platform_data, |
| 108 | }, | 116 | }, |
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh770x.c b/arch/sh/kernel/cpu/sh3/setup-sh770x.c index ba26cd9ce69b..ff1465c0519c 100644 --- a/arch/sh/kernel/cpu/sh3/setup-sh770x.c +++ b/arch/sh/kernel/cpu/sh3/setup-sh770x.c | |||
| @@ -109,20 +109,24 @@ static struct platform_device rtc_device = { | |||
| 109 | }; | 109 | }; |
| 110 | 110 | ||
| 111 | static struct plat_sci_port scif0_platform_data = { | 111 | static struct plat_sci_port scif0_platform_data = { |
| 112 | .mapbase = 0xfffffe80, | ||
| 113 | .port_reg = 0xa4000136, | 112 | .port_reg = 0xa4000136, |
| 114 | .flags = UPF_BOOT_AUTOCONF, | 113 | .flags = UPF_BOOT_AUTOCONF, |
| 115 | .scscr = SCSCR_TE | SCSCR_RE, | 114 | .scscr = SCSCR_TE | SCSCR_RE, |
| 116 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 117 | .type = PORT_SCI, | 115 | .type = PORT_SCI, |
| 118 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x4e0)), | ||
| 119 | .ops = &sh770x_sci_port_ops, | 116 | .ops = &sh770x_sci_port_ops, |
| 120 | .regshift = 1, | 117 | .regshift = 1, |
| 121 | }; | 118 | }; |
| 122 | 119 | ||
| 120 | static struct resource scif0_resources[] = { | ||
| 121 | DEFINE_RES_MEM(0xfffffe80, 0x100), | ||
| 122 | DEFINE_RES_IRQ(evt2irq(0x4e0)), | ||
| 123 | }; | ||
| 124 | |||
| 123 | static struct platform_device scif0_device = { | 125 | static struct platform_device scif0_device = { |
| 124 | .name = "sh-sci", | 126 | .name = "sh-sci", |
| 125 | .id = 0, | 127 | .id = 0, |
| 128 | .resource = scif0_resources, | ||
| 129 | .num_resources = ARRAY_SIZE(scif0_resources), | ||
| 126 | .dev = { | 130 | .dev = { |
| 127 | .platform_data = &scif0_platform_data, | 131 | .platform_data = &scif0_platform_data, |
| 128 | }, | 132 | }, |
| @@ -131,19 +135,23 @@ static struct platform_device scif0_device = { | |||
| 131 | defined(CONFIG_CPU_SUBTYPE_SH7707) || \ | 135 | defined(CONFIG_CPU_SUBTYPE_SH7707) || \ |
| 132 | defined(CONFIG_CPU_SUBTYPE_SH7709) | 136 | defined(CONFIG_CPU_SUBTYPE_SH7709) |
| 133 | static struct plat_sci_port scif1_platform_data = { | 137 | static struct plat_sci_port scif1_platform_data = { |
| 134 | .mapbase = 0xa4000150, | ||
| 135 | .flags = UPF_BOOT_AUTOCONF, | 138 | .flags = UPF_BOOT_AUTOCONF, |
| 136 | .scscr = SCSCR_TE | SCSCR_RE, | 139 | .scscr = SCSCR_TE | SCSCR_RE, |
| 137 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 138 | .type = PORT_SCIF, | 140 | .type = PORT_SCIF, |
| 139 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)), | ||
| 140 | .ops = &sh770x_sci_port_ops, | 141 | .ops = &sh770x_sci_port_ops, |
| 141 | .regtype = SCIx_SH3_SCIF_REGTYPE, | 142 | .regtype = SCIx_SH3_SCIF_REGTYPE, |
| 142 | }; | 143 | }; |
| 143 | 144 | ||
| 145 | static struct resource scif1_resources[] = { | ||
| 146 | DEFINE_RES_MEM(0xa4000150, 0x100), | ||
| 147 | DEFINE_RES_IRQ(evt2irq(0x900)), | ||
| 148 | }; | ||
| 149 | |||
| 144 | static struct platform_device scif1_device = { | 150 | static struct platform_device scif1_device = { |
| 145 | .name = "sh-sci", | 151 | .name = "sh-sci", |
| 146 | .id = 1, | 152 | .id = 1, |
| 153 | .resource = scif1_resources, | ||
| 154 | .num_resources = ARRAY_SIZE(scif1_resources), | ||
| 147 | .dev = { | 155 | .dev = { |
| 148 | .platform_data = &scif1_platform_data, | 156 | .platform_data = &scif1_platform_data, |
| 149 | }, | 157 | }, |
| @@ -152,20 +160,24 @@ static struct platform_device scif1_device = { | |||
| 152 | #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \ | 160 | #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \ |
| 153 | defined(CONFIG_CPU_SUBTYPE_SH7709) | 161 | defined(CONFIG_CPU_SUBTYPE_SH7709) |
| 154 | static struct plat_sci_port scif2_platform_data = { | 162 | static struct plat_sci_port scif2_platform_data = { |
| 155 | .mapbase = 0xa4000140, | ||
| 156 | .port_reg = SCIx_NOT_SUPPORTED, | 163 | .port_reg = SCIx_NOT_SUPPORTED, |
| 157 | .flags = UPF_BOOT_AUTOCONF, | 164 | .flags = UPF_BOOT_AUTOCONF, |
| 158 | .scscr = SCSCR_TE | SCSCR_RE, | 165 | .scscr = SCSCR_TE | SCSCR_RE, |
| 159 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 160 | .type = PORT_IRDA, | 166 | .type = PORT_IRDA, |
| 161 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x880)), | ||
| 162 | .ops = &sh770x_sci_port_ops, | 167 | .ops = &sh770x_sci_port_ops, |
| 163 | .regshift = 1, | 168 | .regshift = 1, |
| 164 | }; | 169 | }; |
| 165 | 170 | ||
| 171 | static struct resource scif2_resources[] = { | ||
| 172 | DEFINE_RES_MEM(0xa4000140, 0x100), | ||
| 173 | DEFINE_RES_IRQ(evt2irq(0x880)), | ||
| 174 | }; | ||
| 175 | |||
| 166 | static struct platform_device scif2_device = { | 176 | static struct platform_device scif2_device = { |
| 167 | .name = "sh-sci", | 177 | .name = "sh-sci", |
| 168 | .id = 2, | 178 | .id = 2, |
| 179 | .resource = scif2_resources, | ||
| 180 | .num_resources = ARRAY_SIZE(scif2_resources), | ||
| 169 | .dev = { | 181 | .dev = { |
| 170 | .platform_data = &scif2_platform_data, | 182 | .platform_data = &scif2_platform_data, |
| 171 | }, | 183 | }, |
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7710.c b/arch/sh/kernel/cpu/sh3/setup-sh7710.c index 93c9c5e24a7a..e2ce9360ed5a 100644 --- a/arch/sh/kernel/cpu/sh3/setup-sh7710.c +++ b/arch/sh/kernel/cpu/sh3/setup-sh7710.c | |||
| @@ -98,36 +98,44 @@ static struct platform_device rtc_device = { | |||
| 98 | }; | 98 | }; |
| 99 | 99 | ||
| 100 | static struct plat_sci_port scif0_platform_data = { | 100 | static struct plat_sci_port scif0_platform_data = { |
| 101 | .mapbase = 0xa4400000, | ||
| 102 | .flags = UPF_BOOT_AUTOCONF, | 101 | .flags = UPF_BOOT_AUTOCONF, |
| 103 | .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE | | 102 | .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE | |
| 104 | SCSCR_CKE1 | SCSCR_CKE0, | 103 | SCSCR_CKE1 | SCSCR_CKE0, |
| 105 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 106 | .type = PORT_SCIF, | 104 | .type = PORT_SCIF, |
| 107 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x880)), | 105 | }; |
| 106 | |||
| 107 | static struct resource scif0_resources[] = { | ||
| 108 | DEFINE_RES_MEM(0xa4400000, 0x100), | ||
| 109 | DEFINE_RES_IRQ(evt2irq(0x880)), | ||
| 108 | }; | 110 | }; |
| 109 | 111 | ||
| 110 | static struct platform_device scif0_device = { | 112 | static struct platform_device scif0_device = { |
| 111 | .name = "sh-sci", | 113 | .name = "sh-sci", |
| 112 | .id = 0, | 114 | .id = 0, |
| 115 | .resource = scif0_resources, | ||
| 116 | .num_resources = ARRAY_SIZE(scif0_resources), | ||
| 113 | .dev = { | 117 | .dev = { |
| 114 | .platform_data = &scif0_platform_data, | 118 | .platform_data = &scif0_platform_data, |
| 115 | }, | 119 | }, |
| 116 | }; | 120 | }; |
| 117 | 121 | ||
| 118 | static struct plat_sci_port scif1_platform_data = { | 122 | static struct plat_sci_port scif1_platform_data = { |
| 119 | .mapbase = 0xa4410000, | ||
| 120 | .flags = UPF_BOOT_AUTOCONF, | 123 | .flags = UPF_BOOT_AUTOCONF, |
| 121 | .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE | | 124 | .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE | |
| 122 | SCSCR_CKE1 | SCSCR_CKE0, | 125 | SCSCR_CKE1 | SCSCR_CKE0, |
| 123 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 124 | .type = PORT_SCIF, | 126 | .type = PORT_SCIF, |
| 125 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)), | 127 | }; |
| 128 | |||
| 129 | static struct resource scif1_resources[] = { | ||
| 130 | DEFINE_RES_MEM(0xa4410000, 0x100), | ||
| 131 | DEFINE_RES_IRQ(evt2irq(0x900)), | ||
| 126 | }; | 132 | }; |
| 127 | 133 | ||
| 128 | static struct platform_device scif1_device = { | 134 | static struct platform_device scif1_device = { |
| 129 | .name = "sh-sci", | 135 | .name = "sh-sci", |
| 130 | .id = 1, | 136 | .id = 1, |
| 137 | .resource = scif1_resources, | ||
| 138 | .num_resources = ARRAY_SIZE(scif1_resources), | ||
| 131 | .dev = { | 139 | .dev = { |
| 132 | .platform_data = &scif1_platform_data, | 140 | .platform_data = &scif1_platform_data, |
| 133 | }, | 141 | }, |
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7720.c b/arch/sh/kernel/cpu/sh3/setup-sh7720.c index 42d991f632b1..1d5729dc0724 100644 --- a/arch/sh/kernel/cpu/sh3/setup-sh7720.c +++ b/arch/sh/kernel/cpu/sh3/setup-sh7720.c | |||
| @@ -52,38 +52,46 @@ static struct platform_device rtc_device = { | |||
| 52 | }; | 52 | }; |
| 53 | 53 | ||
| 54 | static struct plat_sci_port scif0_platform_data = { | 54 | static struct plat_sci_port scif0_platform_data = { |
| 55 | .mapbase = 0xa4430000, | ||
| 56 | .flags = UPF_BOOT_AUTOCONF, | 55 | .flags = UPF_BOOT_AUTOCONF, |
| 57 | .scscr = SCSCR_RE | SCSCR_TE, | 56 | .scscr = SCSCR_RE | SCSCR_TE, |
| 58 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
| 59 | .type = PORT_SCIF, | 57 | .type = PORT_SCIF, |
| 60 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xc00)), | ||
| 61 | .ops = &sh7720_sci_port_ops, | 58 | .ops = &sh7720_sci_port_ops, |
| 62 | .regtype = SCIx_SH7705_SCIF_REGTYPE, | 59 | .regtype = SCIx_SH7705_SCIF_REGTYPE, |
| 63 | }; | 60 | }; |
| 64 | 61 | ||
| 62 | static struct resource scif0_resources[] = { | ||
| 63 | DEFINE_RES_MEM(0xa4430000, 0x100), | ||
| 64 | DEFINE_RES_IRQ(evt2irq(0xc00)), | ||
| 65 | }; | ||
| 66 | |||
| 65 | static struct platform_device scif0_device = { | 67 | static struct platform_device scif0_device = { |
| 66 | .name = "sh-sci", | 68 | .name = "sh-sci", |
| 67 | .id = 0, | 69 | .id = 0, |
| 70 | .resource = scif0_resources, | ||
| 71 | .num_resources = ARRAY_SIZE(scif0_resources), | ||
| 68 | .dev = { | 72 | .dev = { |
| 69 | .platform_data = &scif0_platform_data, | 73 | .platform_data = &scif0_platform_data, |
| 70 | }, | 74 | }, |
| 71 | }; | 75 | }; |
| 72 | 76 | ||
| 73 | static struct plat_sci_port scif1_platform_data = { | 77 | static struct plat_sci_port scif1_platform_data = { |
| 74 | .mapbase = 0xa4438000, | ||
| 75 | .flags = UPF_BOOT_AUTOCONF, | 78 | .flags = UPF_BOOT_AUTOCONF, |
| 76 | .scscr = SCSCR_RE | SCSCR_TE, | 79 | .scscr = SCSCR_RE | SCSCR_TE, |
| 77 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
| 78 | .type = PORT_SCIF, | 80 | .type = PORT_SCIF, |
| 79 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xc20)), | ||
| 80 | .ops = &sh7720_sci_port_ops, | 81 | .ops = &sh7720_sci_port_ops, |
| 81 | .regtype = SCIx_SH7705_SCIF_REGTYPE, | 82 | .regtype = SCIx_SH7705_SCIF_REGTYPE, |
| 82 | }; | 83 | }; |
| 83 | 84 | ||
| 85 | static struct resource scif1_resources[] = { | ||
| 86 | DEFINE_RES_MEM(0xa4438000, 0x100), | ||
| 87 | DEFINE_RES_IRQ(evt2irq(0xc20)), | ||
| 88 | }; | ||
| 89 | |||
| 84 | static struct platform_device scif1_device = { | 90 | static struct platform_device scif1_device = { |
| 85 | .name = "sh-sci", | 91 | .name = "sh-sci", |
| 86 | .id = 1, | 92 | .id = 1, |
| 93 | .resource = scif1_resources, | ||
| 94 | .num_resources = ARRAY_SIZE(scif1_resources), | ||
| 87 | .dev = { | 95 | .dev = { |
| 88 | .platform_data = &scif1_platform_data, | 96 | .platform_data = &scif1_platform_data, |
| 89 | }, | 97 | }, |
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh4-202.c b/arch/sh/kernel/cpu/sh4/setup-sh4-202.c index 2a5320aa73bb..a8bd778d5ac8 100644 --- a/arch/sh/kernel/cpu/sh4/setup-sh4-202.c +++ b/arch/sh/kernel/cpu/sh4/setup-sh4-202.c | |||
| @@ -17,20 +17,24 @@ | |||
| 17 | #include <linux/io.h> | 17 | #include <linux/io.h> |
| 18 | 18 | ||
| 19 | static struct plat_sci_port scif0_platform_data = { | 19 | static struct plat_sci_port scif0_platform_data = { |
| 20 | .mapbase = 0xffe80000, | ||
| 21 | .flags = UPF_BOOT_AUTOCONF, | 20 | .flags = UPF_BOOT_AUTOCONF, |
| 22 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 21 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
| 23 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 24 | .type = PORT_SCIF, | 22 | .type = PORT_SCIF, |
| 25 | .irqs = { evt2irq(0x700), | 23 | }; |
| 26 | evt2irq(0x720), | 24 | |
| 27 | evt2irq(0x760), | 25 | static struct resource scif0_resources[] = { |
| 28 | evt2irq(0x740) }, | 26 | DEFINE_RES_MEM(0xffe80000, 0x100), |
| 27 | DEFINE_RES_IRQ(evt2irq(0x700)), | ||
| 28 | DEFINE_RES_IRQ(evt2irq(0x720)), | ||
| 29 | DEFINE_RES_IRQ(evt2irq(0x760)), | ||
| 30 | DEFINE_RES_IRQ(evt2irq(0x740)), | ||
| 29 | }; | 31 | }; |
| 30 | 32 | ||
| 31 | static struct platform_device scif0_device = { | 33 | static struct platform_device scif0_device = { |
| 32 | .name = "sh-sci", | 34 | .name = "sh-sci", |
| 33 | .id = 0, | 35 | .id = 0, |
| 36 | .resource = scif0_resources, | ||
| 37 | .num_resources = ARRAY_SIZE(scif0_resources), | ||
| 34 | .dev = { | 38 | .dev = { |
| 35 | .platform_data = &scif0_platform_data, | 39 | .platform_data = &scif0_platform_data, |
| 36 | }, | 40 | }, |
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7750.c b/arch/sh/kernel/cpu/sh4/setup-sh7750.c index 04a45512596f..a447a248491f 100644 --- a/arch/sh/kernel/cpu/sh4/setup-sh7750.c +++ b/arch/sh/kernel/cpu/sh4/setup-sh7750.c | |||
| @@ -38,36 +38,44 @@ static struct platform_device rtc_device = { | |||
| 38 | }; | 38 | }; |
| 39 | 39 | ||
| 40 | static struct plat_sci_port sci_platform_data = { | 40 | static struct plat_sci_port sci_platform_data = { |
| 41 | .mapbase = 0xffe00000, | ||
| 42 | .port_reg = 0xffe0001C, | 41 | .port_reg = 0xffe0001C, |
| 43 | .flags = UPF_BOOT_AUTOCONF, | 42 | .flags = UPF_BOOT_AUTOCONF, |
| 44 | .scscr = SCSCR_TE | SCSCR_RE, | 43 | .scscr = SCSCR_TE | SCSCR_RE, |
| 45 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 46 | .type = PORT_SCI, | 44 | .type = PORT_SCI, |
| 47 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x4e0)), | ||
| 48 | .regshift = 2, | 45 | .regshift = 2, |
| 49 | }; | 46 | }; |
| 50 | 47 | ||
| 48 | static struct resource sci_resources[] = { | ||
| 49 | DEFINE_RES_MEM(0xffe00000, 0x100), | ||
| 50 | DEFINE_RES_IRQ(evt2irq(0x4e0)), | ||
| 51 | }; | ||
| 52 | |||
| 51 | static struct platform_device sci_device = { | 53 | static struct platform_device sci_device = { |
| 52 | .name = "sh-sci", | 54 | .name = "sh-sci", |
| 53 | .id = 0, | 55 | .id = 0, |
| 56 | .resource = sci_resources, | ||
| 57 | .num_resources = ARRAY_SIZE(sci_resources), | ||
| 54 | .dev = { | 58 | .dev = { |
| 55 | .platform_data = &sci_platform_data, | 59 | .platform_data = &sci_platform_data, |
| 56 | }, | 60 | }, |
| 57 | }; | 61 | }; |
| 58 | 62 | ||
| 59 | static struct plat_sci_port scif_platform_data = { | 63 | static struct plat_sci_port scif_platform_data = { |
| 60 | .mapbase = 0xffe80000, | ||
| 61 | .flags = UPF_BOOT_AUTOCONF, | 64 | .flags = UPF_BOOT_AUTOCONF, |
| 62 | .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE, | 65 | .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE, |
| 63 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 64 | .type = PORT_SCIF, | 66 | .type = PORT_SCIF, |
| 65 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x700)), | 67 | }; |
| 68 | |||
| 69 | static struct resource scif_resources[] = { | ||
| 70 | DEFINE_RES_MEM(0xffe80000, 0x100), | ||
| 71 | DEFINE_RES_IRQ(evt2irq(0x700)), | ||
| 66 | }; | 72 | }; |
| 67 | 73 | ||
| 68 | static struct platform_device scif_device = { | 74 | static struct platform_device scif_device = { |
| 69 | .name = "sh-sci", | 75 | .name = "sh-sci", |
| 70 | .id = 1, | 76 | .id = 1, |
| 77 | .resource = scif_resources, | ||
| 78 | .num_resources = ARRAY_SIZE(scif_resources), | ||
| 71 | .dev = { | 79 | .dev = { |
| 72 | .platform_data = &scif_platform_data, | 80 | .platform_data = &scif_platform_data, |
| 73 | }, | 81 | }, |
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7760.c b/arch/sh/kernel/cpu/sh4/setup-sh7760.c index 98e075ada44e..1abd9fb4a386 100644 --- a/arch/sh/kernel/cpu/sh4/setup-sh7760.c +++ b/arch/sh/kernel/cpu/sh4/setup-sh7760.c | |||
| @@ -128,83 +128,99 @@ static DECLARE_INTC_DESC(intc_desc_irq, "sh7760-irq", vectors_irq, groups, | |||
| 128 | mask_registers, prio_registers, NULL); | 128 | mask_registers, prio_registers, NULL); |
| 129 | 129 | ||
| 130 | static struct plat_sci_port scif0_platform_data = { | 130 | static struct plat_sci_port scif0_platform_data = { |
| 131 | .mapbase = 0xfe600000, | ||
| 132 | .flags = UPF_BOOT_AUTOCONF, | 131 | .flags = UPF_BOOT_AUTOCONF, |
| 133 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 132 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
| 134 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 135 | .type = PORT_SCIF, | 133 | .type = PORT_SCIF, |
| 136 | .irqs = { evt2irq(0x880), | ||
| 137 | evt2irq(0x8a0), | ||
| 138 | evt2irq(0x8e0), | ||
| 139 | evt2irq(0x8c0) }, | ||
| 140 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 134 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
| 141 | }; | 135 | }; |
| 142 | 136 | ||
| 137 | static struct resource scif0_resources[] = { | ||
| 138 | DEFINE_RES_MEM(0xfe600000, 0x100), | ||
| 139 | DEFINE_RES_IRQ(evt2irq(0x880)), | ||
| 140 | DEFINE_RES_IRQ(evt2irq(0x8a0)), | ||
| 141 | DEFINE_RES_IRQ(evt2irq(0x8e0)), | ||
| 142 | DEFINE_RES_IRQ(evt2irq(0x8c0)), | ||
| 143 | }; | ||
| 144 | |||
| 143 | static struct platform_device scif0_device = { | 145 | static struct platform_device scif0_device = { |
| 144 | .name = "sh-sci", | 146 | .name = "sh-sci", |
| 145 | .id = 0, | 147 | .id = 0, |
| 148 | .resource = scif0_resources, | ||
| 149 | .num_resources = ARRAY_SIZE(scif0_resources), | ||
| 146 | .dev = { | 150 | .dev = { |
| 147 | .platform_data = &scif0_platform_data, | 151 | .platform_data = &scif0_platform_data, |
| 148 | }, | 152 | }, |
| 149 | }; | 153 | }; |
| 150 | 154 | ||
| 151 | static struct plat_sci_port scif1_platform_data = { | 155 | static struct plat_sci_port scif1_platform_data = { |
| 152 | .mapbase = 0xfe610000, | ||
| 153 | .flags = UPF_BOOT_AUTOCONF, | 156 | .flags = UPF_BOOT_AUTOCONF, |
| 154 | .type = PORT_SCIF, | 157 | .type = PORT_SCIF, |
| 155 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 158 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
| 156 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 157 | .irqs = { evt2irq(0xb00), | ||
| 158 | evt2irq(0xb20), | ||
| 159 | evt2irq(0xb60), | ||
| 160 | evt2irq(0xb40) }, | ||
| 161 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 159 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
| 162 | }; | 160 | }; |
| 163 | 161 | ||
| 162 | static struct resource scif1_resources[] = { | ||
| 163 | DEFINE_RES_MEM(0xfe610000, 0x100), | ||
| 164 | DEFINE_RES_IRQ(evt2irq(0xb00)), | ||
| 165 | DEFINE_RES_IRQ(evt2irq(0xb20)), | ||
| 166 | DEFINE_RES_IRQ(evt2irq(0xb60)), | ||
| 167 | DEFINE_RES_IRQ(evt2irq(0xb40)), | ||
| 168 | }; | ||
| 169 | |||
| 164 | static struct platform_device scif1_device = { | 170 | static struct platform_device scif1_device = { |
| 165 | .name = "sh-sci", | 171 | .name = "sh-sci", |
| 166 | .id = 1, | 172 | .id = 1, |
| 173 | .resource = scif1_resources, | ||
| 174 | .num_resources = ARRAY_SIZE(scif1_resources), | ||
| 167 | .dev = { | 175 | .dev = { |
| 168 | .platform_data = &scif1_platform_data, | 176 | .platform_data = &scif1_platform_data, |
| 169 | }, | 177 | }, |
| 170 | }; | 178 | }; |
| 171 | 179 | ||
| 172 | static struct plat_sci_port scif2_platform_data = { | 180 | static struct plat_sci_port scif2_platform_data = { |
| 173 | .mapbase = 0xfe620000, | ||
| 174 | .flags = UPF_BOOT_AUTOCONF, | 181 | .flags = UPF_BOOT_AUTOCONF, |
| 175 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 182 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
| 176 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 177 | .type = PORT_SCIF, | 183 | .type = PORT_SCIF, |
| 178 | .irqs = { evt2irq(0xb80), | ||
| 179 | evt2irq(0xba0), | ||
| 180 | evt2irq(0xbe0), | ||
| 181 | evt2irq(0xbc0) }, | ||
| 182 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 184 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
| 183 | }; | 185 | }; |
| 184 | 186 | ||
| 187 | static struct resource scif2_resources[] = { | ||
| 188 | DEFINE_RES_MEM(0xfe620000, 0x100), | ||
| 189 | DEFINE_RES_IRQ(evt2irq(0xb80)), | ||
| 190 | DEFINE_RES_IRQ(evt2irq(0xba0)), | ||
| 191 | DEFINE_RES_IRQ(evt2irq(0xbe0)), | ||
| 192 | DEFINE_RES_IRQ(evt2irq(0xbc0)), | ||
| 193 | }; | ||
| 194 | |||
| 185 | static struct platform_device scif2_device = { | 195 | static struct platform_device scif2_device = { |
| 186 | .name = "sh-sci", | 196 | .name = "sh-sci", |
| 187 | .id = 2, | 197 | .id = 2, |
| 198 | .resource = scif2_resources, | ||
| 199 | .num_resources = ARRAY_SIZE(scif2_resources), | ||
| 188 | .dev = { | 200 | .dev = { |
| 189 | .platform_data = &scif2_platform_data, | 201 | .platform_data = &scif2_platform_data, |
| 190 | }, | 202 | }, |
| 191 | }; | 203 | }; |
| 192 | 204 | ||
| 193 | static struct plat_sci_port scif3_platform_data = { | 205 | static struct plat_sci_port scif3_platform_data = { |
| 194 | .mapbase = 0xfe480000, | ||
| 195 | .flags = UPF_BOOT_AUTOCONF, | 206 | .flags = UPF_BOOT_AUTOCONF, |
| 196 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 207 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
| 197 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 198 | .type = PORT_SCI, | 208 | .type = PORT_SCI, |
| 199 | .irqs = { evt2irq(0xc00), | ||
| 200 | evt2irq(0xc20), | ||
| 201 | evt2irq(0xc40), }, | ||
| 202 | .regshift = 2, | 209 | .regshift = 2, |
| 203 | }; | 210 | }; |
| 204 | 211 | ||
| 212 | static struct resource scif3_resources[] = { | ||
| 213 | DEFINE_RES_MEM(0xfe480000, 0x100), | ||
| 214 | DEFINE_RES_IRQ(evt2irq(0xc00)), | ||
| 215 | DEFINE_RES_IRQ(evt2irq(0xc20)), | ||
| 216 | DEFINE_RES_IRQ(evt2irq(0xc40)), | ||
| 217 | }; | ||
| 218 | |||
| 205 | static struct platform_device scif3_device = { | 219 | static struct platform_device scif3_device = { |
| 206 | .name = "sh-sci", | 220 | .name = "sh-sci", |
| 207 | .id = 3, | 221 | .id = 3, |
| 222 | .resource = scif3_resources, | ||
| 223 | .num_resources = ARRAY_SIZE(scif3_resources), | ||
| 208 | .dev = { | 224 | .dev = { |
| 209 | .platform_data = &scif3_platform_data, | 225 | .platform_data = &scif3_platform_data, |
| 210 | }, | 226 | }, |
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c index b91ea8300a3e..245d19254489 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c | |||
| @@ -18,68 +18,84 @@ | |||
| 18 | 18 | ||
| 19 | /* Serial */ | 19 | /* Serial */ |
| 20 | static struct plat_sci_port scif0_platform_data = { | 20 | static struct plat_sci_port scif0_platform_data = { |
| 21 | .mapbase = 0xffe00000, | ||
| 22 | .flags = UPF_BOOT_AUTOCONF, | 21 | .flags = UPF_BOOT_AUTOCONF, |
| 23 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, | 22 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, |
| 24 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 25 | .type = PORT_SCIF, | 23 | .type = PORT_SCIF, |
| 26 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xc00)), | 24 | }; |
| 25 | |||
| 26 | static struct resource scif0_resources[] = { | ||
| 27 | DEFINE_RES_MEM(0xffe00000, 0x100), | ||
| 28 | DEFINE_RES_IRQ(evt2irq(0xc00)), | ||
| 27 | }; | 29 | }; |
| 28 | 30 | ||
| 29 | static struct platform_device scif0_device = { | 31 | static struct platform_device scif0_device = { |
| 30 | .name = "sh-sci", | 32 | .name = "sh-sci", |
| 31 | .id = 0, | 33 | .id = 0, |
| 34 | .resource = scif0_resources, | ||
| 35 | .num_resources = ARRAY_SIZE(scif0_resources), | ||
| 32 | .dev = { | 36 | .dev = { |
| 33 | .platform_data = &scif0_platform_data, | 37 | .platform_data = &scif0_platform_data, |
| 34 | }, | 38 | }, |
| 35 | }; | 39 | }; |
| 36 | 40 | ||
| 37 | static struct plat_sci_port scif1_platform_data = { | 41 | static struct plat_sci_port scif1_platform_data = { |
| 38 | .mapbase = 0xffe10000, | ||
| 39 | .flags = UPF_BOOT_AUTOCONF, | 42 | .flags = UPF_BOOT_AUTOCONF, |
| 40 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, | 43 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, |
| 41 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 42 | .type = PORT_SCIF, | 44 | .type = PORT_SCIF, |
| 43 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xc20)), | 45 | }; |
| 46 | |||
| 47 | static struct resource scif1_resources[] = { | ||
| 48 | DEFINE_RES_MEM(0xffe10000, 0x100), | ||
| 49 | DEFINE_RES_IRQ(evt2irq(0xc20)), | ||
| 44 | }; | 50 | }; |
| 45 | 51 | ||
| 46 | static struct platform_device scif1_device = { | 52 | static struct platform_device scif1_device = { |
| 47 | .name = "sh-sci", | 53 | .name = "sh-sci", |
| 48 | .id = 1, | 54 | .id = 1, |
| 55 | .resource = scif1_resources, | ||
| 56 | .num_resources = ARRAY_SIZE(scif1_resources), | ||
| 49 | .dev = { | 57 | .dev = { |
| 50 | .platform_data = &scif1_platform_data, | 58 | .platform_data = &scif1_platform_data, |
| 51 | }, | 59 | }, |
| 52 | }; | 60 | }; |
| 53 | 61 | ||
| 54 | static struct plat_sci_port scif2_platform_data = { | 62 | static struct plat_sci_port scif2_platform_data = { |
| 55 | .mapbase = 0xffe20000, | ||
| 56 | .flags = UPF_BOOT_AUTOCONF, | 63 | .flags = UPF_BOOT_AUTOCONF, |
| 57 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, | 64 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, |
| 58 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 59 | .type = PORT_SCIF, | 65 | .type = PORT_SCIF, |
| 60 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xc40)), | 66 | }; |
| 67 | |||
| 68 | static struct resource scif2_resources[] = { | ||
| 69 | DEFINE_RES_MEM(0xffe20000, 0x100), | ||
| 70 | DEFINE_RES_IRQ(evt2irq(0xc40)), | ||
| 61 | }; | 71 | }; |
| 62 | 72 | ||
| 63 | static struct platform_device scif2_device = { | 73 | static struct platform_device scif2_device = { |
| 64 | .name = "sh-sci", | 74 | .name = "sh-sci", |
| 65 | .id = 2, | 75 | .id = 2, |
| 76 | .resource = scif2_resources, | ||
| 77 | .num_resources = ARRAY_SIZE(scif2_resources), | ||
| 66 | .dev = { | 78 | .dev = { |
| 67 | .platform_data = &scif2_platform_data, | 79 | .platform_data = &scif2_platform_data, |
| 68 | }, | 80 | }, |
| 69 | }; | 81 | }; |
| 70 | 82 | ||
| 71 | static struct plat_sci_port scif3_platform_data = { | 83 | static struct plat_sci_port scif3_platform_data = { |
| 72 | .mapbase = 0xffe30000, | ||
| 73 | .flags = UPF_BOOT_AUTOCONF, | 84 | .flags = UPF_BOOT_AUTOCONF, |
| 74 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, | 85 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, |
| 75 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 76 | .type = PORT_SCIF, | 86 | .type = PORT_SCIF, |
| 77 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xc60)), | 87 | }; |
| 88 | |||
| 89 | static struct resource scif3_resources[] = { | ||
| 90 | DEFINE_RES_MEM(0xffe30000, 0x100), | ||
| 91 | DEFINE_RES_IRQ(evt2irq(0xc60)), | ||
| 78 | }; | 92 | }; |
| 79 | 93 | ||
| 80 | static struct platform_device scif3_device = { | 94 | static struct platform_device scif3_device = { |
| 81 | .name = "sh-sci", | 95 | .name = "sh-sci", |
| 82 | .id = 3, | 96 | .id = 3, |
| 97 | .resource = scif3_resources, | ||
| 98 | .num_resources = ARRAY_SIZE(scif3_resources), | ||
| 83 | .dev = { | 99 | .dev = { |
| 84 | .platform_data = &scif3_platform_data, | 100 | .platform_data = &scif3_platform_data, |
| 85 | }, | 101 | }, |
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c index 0bd09d51419f..6f56cbd76b20 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c | |||
| @@ -20,18 +20,22 @@ | |||
| 20 | #include <asm/clock.h> | 20 | #include <asm/clock.h> |
| 21 | 21 | ||
| 22 | static struct plat_sci_port scif0_platform_data = { | 22 | static struct plat_sci_port scif0_platform_data = { |
| 23 | .mapbase = 0xffe00000, | ||
| 24 | .port_reg = 0xa405013e, | 23 | .port_reg = 0xa405013e, |
| 25 | .flags = UPF_BOOT_AUTOCONF, | 24 | .flags = UPF_BOOT_AUTOCONF, |
| 26 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 25 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
| 27 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 28 | .type = PORT_SCIF, | 26 | .type = PORT_SCIF, |
| 29 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xc00)), | 27 | }; |
| 28 | |||
| 29 | static struct resource scif0_resources[] = { | ||
| 30 | DEFINE_RES_MEM(0xffe00000, 0x100), | ||
| 31 | DEFINE_RES_IRQ(evt2irq(0xc00)), | ||
| 30 | }; | 32 | }; |
| 31 | 33 | ||
| 32 | static struct platform_device scif0_device = { | 34 | static struct platform_device scif0_device = { |
| 33 | .name = "sh-sci", | 35 | .name = "sh-sci", |
| 34 | .id = 0, | 36 | .id = 0, |
| 37 | .resource = scif0_resources, | ||
| 38 | .num_resources = ARRAY_SIZE(scif0_resources), | ||
| 35 | .dev = { | 39 | .dev = { |
| 36 | .platform_data = &scif0_platform_data, | 40 | .platform_data = &scif0_platform_data, |
| 37 | }, | 41 | }, |
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c index 6a868b091c2d..5a94efc8d4ce 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c | |||
| @@ -179,57 +179,69 @@ struct platform_device dma_device = { | |||
| 179 | 179 | ||
| 180 | /* Serial */ | 180 | /* Serial */ |
| 181 | static struct plat_sci_port scif0_platform_data = { | 181 | static struct plat_sci_port scif0_platform_data = { |
| 182 | .mapbase = 0xffe00000, | ||
| 183 | .flags = UPF_BOOT_AUTOCONF, | 182 | .flags = UPF_BOOT_AUTOCONF, |
| 184 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 183 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
| 185 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 186 | .type = PORT_SCIF, | 184 | .type = PORT_SCIF, |
| 187 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xc00)), | ||
| 188 | .ops = &sh7722_sci_port_ops, | 185 | .ops = &sh7722_sci_port_ops, |
| 189 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, | 186 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, |
| 190 | }; | 187 | }; |
| 191 | 188 | ||
| 189 | static struct resource scif0_resources[] = { | ||
| 190 | DEFINE_RES_MEM(0xffe00000, 0x100), | ||
| 191 | DEFINE_RES_IRQ(evt2irq(0xc00)), | ||
| 192 | }; | ||
| 193 | |||
| 192 | static struct platform_device scif0_device = { | 194 | static struct platform_device scif0_device = { |
| 193 | .name = "sh-sci", | 195 | .name = "sh-sci", |
| 194 | .id = 0, | 196 | .id = 0, |
| 197 | .resource = scif0_resources, | ||
| 198 | .num_resources = ARRAY_SIZE(scif0_resources), | ||
| 195 | .dev = { | 199 | .dev = { |
| 196 | .platform_data = &scif0_platform_data, | 200 | .platform_data = &scif0_platform_data, |
| 197 | }, | 201 | }, |
| 198 | }; | 202 | }; |
| 199 | 203 | ||
| 200 | static struct plat_sci_port scif1_platform_data = { | 204 | static struct plat_sci_port scif1_platform_data = { |
| 201 | .mapbase = 0xffe10000, | ||
| 202 | .flags = UPF_BOOT_AUTOCONF, | 205 | .flags = UPF_BOOT_AUTOCONF, |
| 203 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 206 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
| 204 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 205 | .type = PORT_SCIF, | 207 | .type = PORT_SCIF, |
| 206 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xc20)), | ||
| 207 | .ops = &sh7722_sci_port_ops, | 208 | .ops = &sh7722_sci_port_ops, |
| 208 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, | 209 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, |
| 209 | }; | 210 | }; |
| 210 | 211 | ||
| 212 | static struct resource scif1_resources[] = { | ||
| 213 | DEFINE_RES_MEM(0xffe10000, 0x100), | ||
| 214 | DEFINE_RES_IRQ(evt2irq(0xc20)), | ||
| 215 | }; | ||
| 216 | |||
| 211 | static struct platform_device scif1_device = { | 217 | static struct platform_device scif1_device = { |
| 212 | .name = "sh-sci", | 218 | .name = "sh-sci", |
| 213 | .id = 1, | 219 | .id = 1, |
| 220 | .resource = scif1_resources, | ||
| 221 | .num_resources = ARRAY_SIZE(scif1_resources), | ||
| 214 | .dev = { | 222 | .dev = { |
| 215 | .platform_data = &scif1_platform_data, | 223 | .platform_data = &scif1_platform_data, |
| 216 | }, | 224 | }, |
| 217 | }; | 225 | }; |
| 218 | 226 | ||
| 219 | static struct plat_sci_port scif2_platform_data = { | 227 | static struct plat_sci_port scif2_platform_data = { |
| 220 | .mapbase = 0xffe20000, | ||
| 221 | .flags = UPF_BOOT_AUTOCONF, | 228 | .flags = UPF_BOOT_AUTOCONF, |
| 222 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 229 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
| 223 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 224 | .type = PORT_SCIF, | 230 | .type = PORT_SCIF, |
| 225 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xc40)), | ||
| 226 | .ops = &sh7722_sci_port_ops, | 231 | .ops = &sh7722_sci_port_ops, |
| 227 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, | 232 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, |
| 228 | }; | 233 | }; |
| 229 | 234 | ||
| 235 | static struct resource scif2_resources[] = { | ||
| 236 | DEFINE_RES_MEM(0xffe20000, 0x100), | ||
| 237 | DEFINE_RES_IRQ(evt2irq(0xc40)), | ||
| 238 | }; | ||
| 239 | |||
| 230 | static struct platform_device scif2_device = { | 240 | static struct platform_device scif2_device = { |
| 231 | .name = "sh-sci", | 241 | .name = "sh-sci", |
| 232 | .id = 2, | 242 | .id = 2, |
| 243 | .resource = scif2_resources, | ||
| 244 | .num_resources = ARRAY_SIZE(scif2_resources), | ||
| 233 | .dev = { | 245 | .dev = { |
| 234 | .platform_data = &scif2_platform_data, | 246 | .platform_data = &scif2_platform_data, |
| 235 | }, | 247 | }, |
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c index 28d6fd835fe0..3c5eb0993a75 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c | |||
| @@ -23,111 +23,138 @@ | |||
| 23 | 23 | ||
| 24 | /* Serial */ | 24 | /* Serial */ |
| 25 | static struct plat_sci_port scif0_platform_data = { | 25 | static struct plat_sci_port scif0_platform_data = { |
| 26 | .mapbase = 0xffe00000, | ||
| 27 | .port_reg = 0xa4050160, | 26 | .port_reg = 0xa4050160, |
| 28 | .flags = UPF_BOOT_AUTOCONF, | 27 | .flags = UPF_BOOT_AUTOCONF, |
| 29 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 28 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
| 30 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 31 | .type = PORT_SCIF, | 29 | .type = PORT_SCIF, |
| 32 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xc00)), | ||
| 33 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, | 30 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, |
| 34 | }; | 31 | }; |
| 35 | 32 | ||
| 33 | static struct resource scif0_resources[] = { | ||
| 34 | DEFINE_RES_MEM(0xffe00000, 0x100), | ||
| 35 | DEFINE_RES_IRQ(evt2irq(0xc00)), | ||
| 36 | }; | ||
| 37 | |||
| 36 | static struct platform_device scif0_device = { | 38 | static struct platform_device scif0_device = { |
| 37 | .name = "sh-sci", | 39 | .name = "sh-sci", |
| 38 | .id = 0, | 40 | .id = 0, |
| 41 | .resource = scif0_resources, | ||
| 42 | .num_resources = ARRAY_SIZE(scif0_resources), | ||
| 39 | .dev = { | 43 | .dev = { |
| 40 | .platform_data = &scif0_platform_data, | 44 | .platform_data = &scif0_platform_data, |
| 41 | }, | 45 | }, |
| 42 | }; | 46 | }; |
| 43 | 47 | ||
| 44 | static struct plat_sci_port scif1_platform_data = { | 48 | static struct plat_sci_port scif1_platform_data = { |
| 45 | .mapbase = 0xffe10000, | ||
| 46 | .port_reg = SCIx_NOT_SUPPORTED, | 49 | .port_reg = SCIx_NOT_SUPPORTED, |
| 47 | .flags = UPF_BOOT_AUTOCONF, | 50 | .flags = UPF_BOOT_AUTOCONF, |
| 48 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 51 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
| 49 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 50 | .type = PORT_SCIF, | 52 | .type = PORT_SCIF, |
| 51 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xc20)), | ||
| 52 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, | 53 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, |
| 53 | }; | 54 | }; |
| 54 | 55 | ||
| 56 | static struct resource scif1_resources[] = { | ||
| 57 | DEFINE_RES_MEM(0xffe10000, 0x100), | ||
| 58 | DEFINE_RES_IRQ(evt2irq(0xc20)), | ||
| 59 | }; | ||
| 60 | |||
| 55 | static struct platform_device scif1_device = { | 61 | static struct platform_device scif1_device = { |
| 56 | .name = "sh-sci", | 62 | .name = "sh-sci", |
| 57 | .id = 1, | 63 | .id = 1, |
| 64 | .resource = scif1_resources, | ||
| 65 | .num_resources = ARRAY_SIZE(scif1_resources), | ||
| 58 | .dev = { | 66 | .dev = { |
| 59 | .platform_data = &scif1_platform_data, | 67 | .platform_data = &scif1_platform_data, |
| 60 | }, | 68 | }, |
| 61 | }; | 69 | }; |
| 62 | 70 | ||
| 63 | static struct plat_sci_port scif2_platform_data = { | 71 | static struct plat_sci_port scif2_platform_data = { |
| 64 | .mapbase = 0xffe20000, | ||
| 65 | .port_reg = SCIx_NOT_SUPPORTED, | 72 | .port_reg = SCIx_NOT_SUPPORTED, |
| 66 | .flags = UPF_BOOT_AUTOCONF, | 73 | .flags = UPF_BOOT_AUTOCONF, |
| 67 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 74 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
| 68 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 69 | .type = PORT_SCIF, | 75 | .type = PORT_SCIF, |
| 70 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xc40)), | ||
| 71 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, | 76 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, |
| 72 | }; | 77 | }; |
| 73 | 78 | ||
| 79 | static struct resource scif2_resources[] = { | ||
| 80 | DEFINE_RES_MEM(0xffe20000, 0x100), | ||
| 81 | DEFINE_RES_IRQ(evt2irq(0xc40)), | ||
| 82 | }; | ||
| 83 | |||
| 74 | static struct platform_device scif2_device = { | 84 | static struct platform_device scif2_device = { |
| 75 | .name = "sh-sci", | 85 | .name = "sh-sci", |
| 76 | .id = 2, | 86 | .id = 2, |
| 87 | .resource = scif2_resources, | ||
| 88 | .num_resources = ARRAY_SIZE(scif2_resources), | ||
| 77 | .dev = { | 89 | .dev = { |
| 78 | .platform_data = &scif2_platform_data, | 90 | .platform_data = &scif2_platform_data, |
| 79 | }, | 91 | }, |
| 80 | }; | 92 | }; |
| 81 | 93 | ||
| 82 | static struct plat_sci_port scif3_platform_data = { | 94 | static struct plat_sci_port scif3_platform_data = { |
| 83 | .mapbase = 0xa4e30000, | ||
| 84 | .flags = UPF_BOOT_AUTOCONF, | 95 | .flags = UPF_BOOT_AUTOCONF, |
| 85 | .port_reg = SCIx_NOT_SUPPORTED, | 96 | .port_reg = SCIx_NOT_SUPPORTED, |
| 86 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 97 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
| 87 | .scbrr_algo_id = SCBRR_ALGO_3, | 98 | .sampling_rate = 8, |
| 88 | .type = PORT_SCIFA, | 99 | .type = PORT_SCIFA, |
| 89 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)), | 100 | }; |
| 101 | |||
| 102 | static struct resource scif3_resources[] = { | ||
| 103 | DEFINE_RES_MEM(0xa4e30000, 0x100), | ||
| 104 | DEFINE_RES_IRQ(evt2irq(0x900)), | ||
| 90 | }; | 105 | }; |
| 91 | 106 | ||
| 92 | static struct platform_device scif3_device = { | 107 | static struct platform_device scif3_device = { |
| 93 | .name = "sh-sci", | 108 | .name = "sh-sci", |
| 94 | .id = 3, | 109 | .id = 3, |
| 110 | .resource = scif3_resources, | ||
| 111 | .num_resources = ARRAY_SIZE(scif3_resources), | ||
| 95 | .dev = { | 112 | .dev = { |
| 96 | .platform_data = &scif3_platform_data, | 113 | .platform_data = &scif3_platform_data, |
| 97 | }, | 114 | }, |
| 98 | }; | 115 | }; |
| 99 | 116 | ||
| 100 | static struct plat_sci_port scif4_platform_data = { | 117 | static struct plat_sci_port scif4_platform_data = { |
| 101 | .mapbase = 0xa4e40000, | ||
| 102 | .port_reg = SCIx_NOT_SUPPORTED, | 118 | .port_reg = SCIx_NOT_SUPPORTED, |
| 103 | .flags = UPF_BOOT_AUTOCONF, | 119 | .flags = UPF_BOOT_AUTOCONF, |
| 104 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 120 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
| 105 | .scbrr_algo_id = SCBRR_ALGO_3, | 121 | .sampling_rate = 8, |
| 106 | .type = PORT_SCIFA, | 122 | .type = PORT_SCIFA, |
| 107 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xd00)), | 123 | }; |
| 124 | |||
| 125 | static struct resource scif4_resources[] = { | ||
| 126 | DEFINE_RES_MEM(0xa4e40000, 0x100), | ||
| 127 | DEFINE_RES_IRQ(evt2irq(0xd00)), | ||
| 108 | }; | 128 | }; |
| 109 | 129 | ||
| 110 | static struct platform_device scif4_device = { | 130 | static struct platform_device scif4_device = { |
| 111 | .name = "sh-sci", | 131 | .name = "sh-sci", |
| 112 | .id = 4, | 132 | .id = 4, |
| 133 | .resource = scif4_resources, | ||
| 134 | .num_resources = ARRAY_SIZE(scif4_resources), | ||
| 113 | .dev = { | 135 | .dev = { |
| 114 | .platform_data = &scif4_platform_data, | 136 | .platform_data = &scif4_platform_data, |
| 115 | }, | 137 | }, |
| 116 | }; | 138 | }; |
| 117 | 139 | ||
| 118 | static struct plat_sci_port scif5_platform_data = { | 140 | static struct plat_sci_port scif5_platform_data = { |
| 119 | .mapbase = 0xa4e50000, | ||
| 120 | .port_reg = SCIx_NOT_SUPPORTED, | 141 | .port_reg = SCIx_NOT_SUPPORTED, |
| 121 | .flags = UPF_BOOT_AUTOCONF, | 142 | .flags = UPF_BOOT_AUTOCONF, |
| 122 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 143 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
| 123 | .scbrr_algo_id = SCBRR_ALGO_3, | 144 | .sampling_rate = 8, |
| 124 | .type = PORT_SCIFA, | 145 | .type = PORT_SCIFA, |
| 125 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xfa0)), | 146 | }; |
| 147 | |||
| 148 | static struct resource scif5_resources[] = { | ||
| 149 | DEFINE_RES_MEM(0xa4e50000, 0x100), | ||
| 150 | DEFINE_RES_IRQ(evt2irq(0xfa0)), | ||
| 126 | }; | 151 | }; |
| 127 | 152 | ||
| 128 | static struct platform_device scif5_device = { | 153 | static struct platform_device scif5_device = { |
| 129 | .name = "sh-sci", | 154 | .name = "sh-sci", |
| 130 | .id = 5, | 155 | .id = 5, |
| 156 | .resource = scif5_resources, | ||
| 157 | .num_resources = ARRAY_SIZE(scif5_resources), | ||
| 131 | .dev = { | 158 | .dev = { |
| 132 | .platform_data = &scif5_platform_data, | 159 | .platform_data = &scif5_platform_data, |
| 133 | }, | 160 | }, |
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c index 26b74c2f9496..60ebbc6842ff 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c | |||
| @@ -290,111 +290,138 @@ static struct platform_device dma1_device = { | |||
| 290 | 290 | ||
| 291 | /* Serial */ | 291 | /* Serial */ |
| 292 | static struct plat_sci_port scif0_platform_data = { | 292 | static struct plat_sci_port scif0_platform_data = { |
| 293 | .mapbase = 0xffe00000, | ||
| 294 | .port_reg = SCIx_NOT_SUPPORTED, | 293 | .port_reg = SCIx_NOT_SUPPORTED, |
| 295 | .flags = UPF_BOOT_AUTOCONF, | 294 | .flags = UPF_BOOT_AUTOCONF, |
| 296 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 295 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
| 297 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 298 | .type = PORT_SCIF, | 296 | .type = PORT_SCIF, |
| 299 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xc00)), | ||
| 300 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, | 297 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, |
| 301 | }; | 298 | }; |
| 302 | 299 | ||
| 300 | static struct resource scif0_resources[] = { | ||
| 301 | DEFINE_RES_MEM(0xffe00000, 0x100), | ||
| 302 | DEFINE_RES_IRQ(evt2irq(0xc00)), | ||
| 303 | }; | ||
| 304 | |||
| 303 | static struct platform_device scif0_device = { | 305 | static struct platform_device scif0_device = { |
| 304 | .name = "sh-sci", | 306 | .name = "sh-sci", |
| 305 | .id = 0, | 307 | .id = 0, |
| 308 | .resource = scif0_resources, | ||
| 309 | .num_resources = ARRAY_SIZE(scif0_resources), | ||
| 306 | .dev = { | 310 | .dev = { |
| 307 | .platform_data = &scif0_platform_data, | 311 | .platform_data = &scif0_platform_data, |
| 308 | }, | 312 | }, |
| 309 | }; | 313 | }; |
| 310 | 314 | ||
| 311 | static struct plat_sci_port scif1_platform_data = { | 315 | static struct plat_sci_port scif1_platform_data = { |
| 312 | .mapbase = 0xffe10000, | ||
| 313 | .port_reg = SCIx_NOT_SUPPORTED, | 316 | .port_reg = SCIx_NOT_SUPPORTED, |
| 314 | .flags = UPF_BOOT_AUTOCONF, | 317 | .flags = UPF_BOOT_AUTOCONF, |
| 315 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 318 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
| 316 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 317 | .type = PORT_SCIF, | 319 | .type = PORT_SCIF, |
| 318 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xc20)), | ||
| 319 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, | 320 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, |
| 320 | }; | 321 | }; |
| 321 | 322 | ||
| 323 | static struct resource scif1_resources[] = { | ||
| 324 | DEFINE_RES_MEM(0xffe10000, 0x100), | ||
| 325 | DEFINE_RES_IRQ(evt2irq(0xc20)), | ||
| 326 | }; | ||
| 327 | |||
| 322 | static struct platform_device scif1_device = { | 328 | static struct platform_device scif1_device = { |
| 323 | .name = "sh-sci", | 329 | .name = "sh-sci", |
| 324 | .id = 1, | 330 | .id = 1, |
| 331 | .resource = scif1_resources, | ||
| 332 | .num_resources = ARRAY_SIZE(scif1_resources), | ||
| 325 | .dev = { | 333 | .dev = { |
| 326 | .platform_data = &scif1_platform_data, | 334 | .platform_data = &scif1_platform_data, |
| 327 | }, | 335 | }, |
| 328 | }; | 336 | }; |
| 329 | 337 | ||
| 330 | static struct plat_sci_port scif2_platform_data = { | 338 | static struct plat_sci_port scif2_platform_data = { |
| 331 | .mapbase = 0xffe20000, | ||
| 332 | .port_reg = SCIx_NOT_SUPPORTED, | 339 | .port_reg = SCIx_NOT_SUPPORTED, |
| 333 | .flags = UPF_BOOT_AUTOCONF, | 340 | .flags = UPF_BOOT_AUTOCONF, |
| 334 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 341 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
| 335 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 336 | .type = PORT_SCIF, | 342 | .type = PORT_SCIF, |
| 337 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xc40)), | ||
| 338 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, | 343 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, |
| 339 | }; | 344 | }; |
| 340 | 345 | ||
| 346 | static struct resource scif2_resources[] = { | ||
| 347 | DEFINE_RES_MEM(0xffe20000, 0x100), | ||
| 348 | DEFINE_RES_IRQ(evt2irq(0xc40)), | ||
| 349 | }; | ||
| 350 | |||
| 341 | static struct platform_device scif2_device = { | 351 | static struct platform_device scif2_device = { |
| 342 | .name = "sh-sci", | 352 | .name = "sh-sci", |
| 343 | .id = 2, | 353 | .id = 2, |
| 354 | .resource = scif2_resources, | ||
| 355 | .num_resources = ARRAY_SIZE(scif2_resources), | ||
| 344 | .dev = { | 356 | .dev = { |
| 345 | .platform_data = &scif2_platform_data, | 357 | .platform_data = &scif2_platform_data, |
| 346 | }, | 358 | }, |
| 347 | }; | 359 | }; |
| 348 | 360 | ||
| 349 | static struct plat_sci_port scif3_platform_data = { | 361 | static struct plat_sci_port scif3_platform_data = { |
| 350 | .mapbase = 0xa4e30000, | ||
| 351 | .port_reg = SCIx_NOT_SUPPORTED, | 362 | .port_reg = SCIx_NOT_SUPPORTED, |
| 352 | .flags = UPF_BOOT_AUTOCONF, | 363 | .flags = UPF_BOOT_AUTOCONF, |
| 353 | .scscr = SCSCR_RE | SCSCR_TE, | 364 | .scscr = SCSCR_RE | SCSCR_TE, |
| 354 | .scbrr_algo_id = SCBRR_ALGO_3, | 365 | .sampling_rate = 8, |
| 355 | .type = PORT_SCIFA, | 366 | .type = PORT_SCIFA, |
| 356 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)), | 367 | }; |
| 368 | |||
| 369 | static struct resource scif3_resources[] = { | ||
| 370 | DEFINE_RES_MEM(0xa4e30000, 0x100), | ||
| 371 | DEFINE_RES_IRQ(evt2irq(0x900)), | ||
| 357 | }; | 372 | }; |
| 358 | 373 | ||
| 359 | static struct platform_device scif3_device = { | 374 | static struct platform_device scif3_device = { |
| 360 | .name = "sh-sci", | 375 | .name = "sh-sci", |
| 361 | .id = 3, | 376 | .id = 3, |
| 377 | .resource = scif3_resources, | ||
| 378 | .num_resources = ARRAY_SIZE(scif3_resources), | ||
| 362 | .dev = { | 379 | .dev = { |
| 363 | .platform_data = &scif3_platform_data, | 380 | .platform_data = &scif3_platform_data, |
| 364 | }, | 381 | }, |
| 365 | }; | 382 | }; |
| 366 | 383 | ||
| 367 | static struct plat_sci_port scif4_platform_data = { | 384 | static struct plat_sci_port scif4_platform_data = { |
| 368 | .mapbase = 0xa4e40000, | ||
| 369 | .port_reg = SCIx_NOT_SUPPORTED, | 385 | .port_reg = SCIx_NOT_SUPPORTED, |
| 370 | .flags = UPF_BOOT_AUTOCONF, | 386 | .flags = UPF_BOOT_AUTOCONF, |
| 371 | .scscr = SCSCR_RE | SCSCR_TE, | 387 | .scscr = SCSCR_RE | SCSCR_TE, |
| 372 | .scbrr_algo_id = SCBRR_ALGO_3, | 388 | .sampling_rate = 8, |
| 373 | .type = PORT_SCIFA, | 389 | .type = PORT_SCIFA, |
| 374 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xd00)), | 390 | }; |
| 391 | |||
| 392 | static struct resource scif4_resources[] = { | ||
| 393 | DEFINE_RES_MEM(0xa4e40000, 0x100), | ||
| 394 | DEFINE_RES_IRQ(evt2irq(0xd00)), | ||
| 375 | }; | 395 | }; |
| 376 | 396 | ||
| 377 | static struct platform_device scif4_device = { | 397 | static struct platform_device scif4_device = { |
| 378 | .name = "sh-sci", | 398 | .name = "sh-sci", |
| 379 | .id = 4, | 399 | .id = 4, |
| 400 | .resource = scif4_resources, | ||
| 401 | .num_resources = ARRAY_SIZE(scif4_resources), | ||
| 380 | .dev = { | 402 | .dev = { |
| 381 | .platform_data = &scif4_platform_data, | 403 | .platform_data = &scif4_platform_data, |
| 382 | }, | 404 | }, |
| 383 | }; | 405 | }; |
| 384 | 406 | ||
| 385 | static struct plat_sci_port scif5_platform_data = { | 407 | static struct plat_sci_port scif5_platform_data = { |
| 386 | .mapbase = 0xa4e50000, | ||
| 387 | .port_reg = SCIx_NOT_SUPPORTED, | 408 | .port_reg = SCIx_NOT_SUPPORTED, |
| 388 | .flags = UPF_BOOT_AUTOCONF, | 409 | .flags = UPF_BOOT_AUTOCONF, |
| 389 | .scscr = SCSCR_RE | SCSCR_TE, | 410 | .scscr = SCSCR_RE | SCSCR_TE, |
| 390 | .scbrr_algo_id = SCBRR_ALGO_3, | 411 | .sampling_rate = 8, |
| 391 | .type = PORT_SCIFA, | 412 | .type = PORT_SCIFA, |
| 392 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xfa0)), | 413 | }; |
| 414 | |||
| 415 | static struct resource scif5_resources[] = { | ||
| 416 | DEFINE_RES_MEM(0xa4e50000, 0x100), | ||
| 417 | DEFINE_RES_IRQ(evt2irq(0xfa0)), | ||
| 393 | }; | 418 | }; |
| 394 | 419 | ||
| 395 | static struct platform_device scif5_device = { | 420 | static struct platform_device scif5_device = { |
| 396 | .name = "sh-sci", | 421 | .name = "sh-sci", |
| 397 | .id = 5, | 422 | .id = 5, |
| 423 | .resource = scif5_resources, | ||
| 424 | .num_resources = ARRAY_SIZE(scif5_resources), | ||
| 398 | .dev = { | 425 | .dev = { |
| 399 | .platform_data = &scif5_platform_data, | 426 | .platform_data = &scif5_platform_data, |
| 400 | }, | 427 | }, |
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7734.c b/arch/sh/kernel/cpu/sh4a/setup-sh7734.c index f799971d453c..dad4ed1b2f94 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7734.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7734.c | |||
| @@ -25,108 +25,132 @@ | |||
| 25 | 25 | ||
| 26 | /* SCIF */ | 26 | /* SCIF */ |
| 27 | static struct plat_sci_port scif0_platform_data = { | 27 | static struct plat_sci_port scif0_platform_data = { |
| 28 | .mapbase = 0xFFE40000, | ||
| 29 | .flags = UPF_BOOT_AUTOCONF, | 28 | .flags = UPF_BOOT_AUTOCONF, |
| 30 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 29 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
| 31 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 32 | .type = PORT_SCIF, | 30 | .type = PORT_SCIF, |
| 33 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x8C0)), | ||
| 34 | .regtype = SCIx_SH4_SCIF_REGTYPE, | 31 | .regtype = SCIx_SH4_SCIF_REGTYPE, |
| 35 | }; | 32 | }; |
| 36 | 33 | ||
| 34 | static struct resource scif0_resources[] = { | ||
| 35 | DEFINE_RES_MEM(0xffe40000, 0x100), | ||
| 36 | DEFINE_RES_IRQ(evt2irq(0x8c0)), | ||
| 37 | }; | ||
| 38 | |||
| 37 | static struct platform_device scif0_device = { | 39 | static struct platform_device scif0_device = { |
| 38 | .name = "sh-sci", | 40 | .name = "sh-sci", |
| 39 | .id = 0, | 41 | .id = 0, |
| 42 | .resource = scif0_resources, | ||
| 43 | .num_resources = ARRAY_SIZE(scif0_resources), | ||
| 40 | .dev = { | 44 | .dev = { |
| 41 | .platform_data = &scif0_platform_data, | 45 | .platform_data = &scif0_platform_data, |
| 42 | }, | 46 | }, |
| 43 | }; | 47 | }; |
| 44 | 48 | ||
| 45 | static struct plat_sci_port scif1_platform_data = { | 49 | static struct plat_sci_port scif1_platform_data = { |
| 46 | .mapbase = 0xFFE41000, | ||
| 47 | .flags = UPF_BOOT_AUTOCONF, | 50 | .flags = UPF_BOOT_AUTOCONF, |
| 48 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 51 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
| 49 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 50 | .type = PORT_SCIF, | 52 | .type = PORT_SCIF, |
| 51 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x8E0)), | ||
| 52 | .regtype = SCIx_SH4_SCIF_REGTYPE, | 53 | .regtype = SCIx_SH4_SCIF_REGTYPE, |
| 53 | }; | 54 | }; |
| 54 | 55 | ||
| 56 | static struct resource scif1_resources[] = { | ||
| 57 | DEFINE_RES_MEM(0xffe41000, 0x100), | ||
| 58 | DEFINE_RES_IRQ(evt2irq(0x8e0)), | ||
| 59 | }; | ||
| 60 | |||
| 55 | static struct platform_device scif1_device = { | 61 | static struct platform_device scif1_device = { |
| 56 | .name = "sh-sci", | 62 | .name = "sh-sci", |
| 57 | .id = 1, | 63 | .id = 1, |
| 64 | .resource = scif1_resources, | ||
| 65 | .num_resources = ARRAY_SIZE(scif1_resources), | ||
| 58 | .dev = { | 66 | .dev = { |
| 59 | .platform_data = &scif1_platform_data, | 67 | .platform_data = &scif1_platform_data, |
| 60 | }, | 68 | }, |
| 61 | }; | 69 | }; |
| 62 | 70 | ||
| 63 | static struct plat_sci_port scif2_platform_data = { | 71 | static struct plat_sci_port scif2_platform_data = { |
| 64 | .mapbase = 0xFFE42000, | ||
| 65 | .flags = UPF_BOOT_AUTOCONF, | 72 | .flags = UPF_BOOT_AUTOCONF, |
| 66 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 73 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
| 67 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 68 | .type = PORT_SCIF, | 74 | .type = PORT_SCIF, |
| 69 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)), | ||
| 70 | .regtype = SCIx_SH4_SCIF_REGTYPE, | 75 | .regtype = SCIx_SH4_SCIF_REGTYPE, |
| 71 | }; | 76 | }; |
| 72 | 77 | ||
| 78 | static struct resource scif2_resources[] = { | ||
| 79 | DEFINE_RES_MEM(0xffe42000, 0x100), | ||
| 80 | DEFINE_RES_IRQ(evt2irq(0x900)), | ||
| 81 | }; | ||
| 82 | |||
| 73 | static struct platform_device scif2_device = { | 83 | static struct platform_device scif2_device = { |
| 74 | .name = "sh-sci", | 84 | .name = "sh-sci", |
| 75 | .id = 2, | 85 | .id = 2, |
| 86 | .resource = scif2_resources, | ||
| 87 | .num_resources = ARRAY_SIZE(scif2_resources), | ||
| 76 | .dev = { | 88 | .dev = { |
| 77 | .platform_data = &scif2_platform_data, | 89 | .platform_data = &scif2_platform_data, |
| 78 | }, | 90 | }, |
| 79 | }; | 91 | }; |
| 80 | 92 | ||
| 81 | static struct plat_sci_port scif3_platform_data = { | 93 | static struct plat_sci_port scif3_platform_data = { |
| 82 | .mapbase = 0xFFE43000, | ||
| 83 | .flags = UPF_BOOT_AUTOCONF, | 94 | .flags = UPF_BOOT_AUTOCONF, |
| 84 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | 95 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
| 85 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 86 | .type = PORT_SCIF, | 96 | .type = PORT_SCIF, |
| 87 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x920)), | ||
| 88 | .regtype = SCIx_SH4_SCIF_REGTYPE, | 97 | .regtype = SCIx_SH4_SCIF_REGTYPE, |
| 89 | }; | 98 | }; |
| 90 | 99 | ||
| 100 | static struct resource scif3_resources[] = { | ||
| 101 | DEFINE_RES_MEM(0xffe43000, 0x100), | ||
| 102 | DEFINE_RES_IRQ(evt2irq(0x920)), | ||
| 103 | }; | ||
| 104 | |||
| 91 | static struct platform_device scif3_device = { | 105 | static struct platform_device scif3_device = { |
| 92 | .name = "sh-sci", | 106 | .name = "sh-sci", |
| 93 | .id = 3, | 107 | .id = 3, |
| 108 | .resource = scif3_resources, | ||
| 109 | .num_resources = ARRAY_SIZE(scif3_resources), | ||
| 94 | .dev = { | 110 | .dev = { |
| 95 | .platform_data = &scif3_platform_data, | 111 | .platform_data = &scif3_platform_data, |
| 96 | }, | 112 | }, |
| 97 | }; | 113 | }; |
| 98 | 114 | ||
| 99 | static struct plat_sci_port scif4_platform_data = { | 115 | static struct plat_sci_port scif4_platform_data = { |
| 100 | .mapbase = 0xFFE44000, | ||
| 101 | .flags = UPF_BOOT_AUTOCONF, | 116 | .flags = UPF_BOOT_AUTOCONF, |
| 102 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 117 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
| 103 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 104 | .type = PORT_SCIF, | 118 | .type = PORT_SCIF, |
| 105 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x940)), | ||
| 106 | .regtype = SCIx_SH4_SCIF_REGTYPE, | 119 | .regtype = SCIx_SH4_SCIF_REGTYPE, |
| 107 | }; | 120 | }; |
| 108 | 121 | ||
| 122 | static struct resource scif4_resources[] = { | ||
| 123 | DEFINE_RES_MEM(0xffe44000, 0x100), | ||
| 124 | DEFINE_RES_IRQ(evt2irq(0x940)), | ||
| 125 | }; | ||
| 126 | |||
| 109 | static struct platform_device scif4_device = { | 127 | static struct platform_device scif4_device = { |
| 110 | .name = "sh-sci", | 128 | .name = "sh-sci", |
| 111 | .id = 4, | 129 | .id = 4, |
| 130 | .resource = scif4_resources, | ||
| 131 | .num_resources = ARRAY_SIZE(scif4_resources), | ||
| 112 | .dev = { | 132 | .dev = { |
| 113 | .platform_data = &scif4_platform_data, | 133 | .platform_data = &scif4_platform_data, |
| 114 | }, | 134 | }, |
| 115 | }; | 135 | }; |
| 116 | 136 | ||
| 117 | static struct plat_sci_port scif5_platform_data = { | 137 | static struct plat_sci_port scif5_platform_data = { |
| 118 | .mapbase = 0xFFE43000, | ||
| 119 | .flags = UPF_BOOT_AUTOCONF, | 138 | .flags = UPF_BOOT_AUTOCONF, |
| 120 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 139 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
| 121 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 122 | .type = PORT_SCIF, | 140 | .type = PORT_SCIF, |
| 123 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x960)), | ||
| 124 | .regtype = SCIx_SH4_SCIF_REGTYPE, | 141 | .regtype = SCIx_SH4_SCIF_REGTYPE, |
| 125 | }; | 142 | }; |
| 126 | 143 | ||
| 144 | static struct resource scif5_resources[] = { | ||
| 145 | DEFINE_RES_MEM(0xffe43000, 0x100), | ||
| 146 | DEFINE_RES_IRQ(evt2irq(0x960)), | ||
| 147 | }; | ||
| 148 | |||
| 127 | static struct platform_device scif5_device = { | 149 | static struct platform_device scif5_device = { |
| 128 | .name = "sh-sci", | 150 | .name = "sh-sci", |
| 129 | .id = 5, | 151 | .id = 5, |
| 152 | .resource = scif5_resources, | ||
| 153 | .num_resources = ARRAY_SIZE(scif5_resources), | ||
| 130 | .dev = { | 154 | .dev = { |
| 131 | .platform_data = &scif5_platform_data, | 155 | .platform_data = &scif5_platform_data, |
| 132 | }, | 156 | }, |
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c index 9079a0f9ea9b..e43e5db53913 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c | |||
| @@ -24,51 +24,63 @@ | |||
| 24 | #include <cpu/sh7757.h> | 24 | #include <cpu/sh7757.h> |
| 25 | 25 | ||
| 26 | static struct plat_sci_port scif2_platform_data = { | 26 | static struct plat_sci_port scif2_platform_data = { |
| 27 | .mapbase = 0xfe4b0000, /* SCIF2 */ | ||
| 28 | .flags = UPF_BOOT_AUTOCONF, | 27 | .flags = UPF_BOOT_AUTOCONF, |
| 29 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 28 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
| 30 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 31 | .type = PORT_SCIF, | 29 | .type = PORT_SCIF, |
| 32 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x700)), | 30 | }; |
| 31 | |||
| 32 | static struct resource scif2_resources[] = { | ||
| 33 | DEFINE_RES_MEM(0xfe4b0000, 0x100), /* SCIF2 */ | ||
| 34 | DEFINE_RES_IRQ(evt2irq(0x700)), | ||
| 33 | }; | 35 | }; |
| 34 | 36 | ||
| 35 | static struct platform_device scif2_device = { | 37 | static struct platform_device scif2_device = { |
| 36 | .name = "sh-sci", | 38 | .name = "sh-sci", |
| 37 | .id = 0, | 39 | .id = 0, |
| 40 | .resource = scif2_resources, | ||
| 41 | .num_resources = ARRAY_SIZE(scif2_resources), | ||
| 38 | .dev = { | 42 | .dev = { |
| 39 | .platform_data = &scif2_platform_data, | 43 | .platform_data = &scif2_platform_data, |
| 40 | }, | 44 | }, |
| 41 | }; | 45 | }; |
| 42 | 46 | ||
| 43 | static struct plat_sci_port scif3_platform_data = { | 47 | static struct plat_sci_port scif3_platform_data = { |
| 44 | .mapbase = 0xfe4c0000, /* SCIF3 */ | ||
| 45 | .flags = UPF_BOOT_AUTOCONF, | 48 | .flags = UPF_BOOT_AUTOCONF, |
| 46 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 49 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
| 47 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 48 | .type = PORT_SCIF, | 50 | .type = PORT_SCIF, |
| 49 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xb80)), | 51 | }; |
| 52 | |||
| 53 | static struct resource scif3_resources[] = { | ||
| 54 | DEFINE_RES_MEM(0xfe4c0000, 0x100), /* SCIF3 */ | ||
| 55 | DEFINE_RES_IRQ(evt2irq(0xb80)), | ||
| 50 | }; | 56 | }; |
| 51 | 57 | ||
| 52 | static struct platform_device scif3_device = { | 58 | static struct platform_device scif3_device = { |
| 53 | .name = "sh-sci", | 59 | .name = "sh-sci", |
| 54 | .id = 1, | 60 | .id = 1, |
| 61 | .resource = scif3_resources, | ||
| 62 | .num_resources = ARRAY_SIZE(scif3_resources), | ||
| 55 | .dev = { | 63 | .dev = { |
| 56 | .platform_data = &scif3_platform_data, | 64 | .platform_data = &scif3_platform_data, |
| 57 | }, | 65 | }, |
| 58 | }; | 66 | }; |
| 59 | 67 | ||
| 60 | static struct plat_sci_port scif4_platform_data = { | 68 | static struct plat_sci_port scif4_platform_data = { |
| 61 | .mapbase = 0xfe4d0000, /* SCIF4 */ | ||
| 62 | .flags = UPF_BOOT_AUTOCONF, | 69 | .flags = UPF_BOOT_AUTOCONF, |
| 63 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 70 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
| 64 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 65 | .type = PORT_SCIF, | 71 | .type = PORT_SCIF, |
| 66 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xF00)), | 72 | }; |
| 73 | |||
| 74 | static struct resource scif4_resources[] = { | ||
| 75 | DEFINE_RES_MEM(0xfe4d0000, 0x100), /* SCIF4 */ | ||
| 76 | DEFINE_RES_IRQ(evt2irq(0xf00)), | ||
| 67 | }; | 77 | }; |
| 68 | 78 | ||
| 69 | static struct platform_device scif4_device = { | 79 | static struct platform_device scif4_device = { |
| 70 | .name = "sh-sci", | 80 | .name = "sh-sci", |
| 71 | .id = 2, | 81 | .id = 2, |
| 82 | .resource = scif4_resources, | ||
| 83 | .num_resources = ARRAY_SIZE(scif4_resources), | ||
| 72 | .dev = { | 84 | .dev = { |
| 73 | .platform_data = &scif4_platform_data, | 85 | .platform_data = &scif4_platform_data, |
| 74 | }, | 86 | }, |
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c index 1686acaaf45a..5eebbd7f4c21 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c | |||
| @@ -19,54 +19,66 @@ | |||
| 19 | #include <linux/usb/ohci_pdriver.h> | 19 | #include <linux/usb/ohci_pdriver.h> |
| 20 | 20 | ||
| 21 | static struct plat_sci_port scif0_platform_data = { | 21 | static struct plat_sci_port scif0_platform_data = { |
| 22 | .mapbase = 0xffe00000, | ||
| 23 | .flags = UPF_BOOT_AUTOCONF, | 22 | .flags = UPF_BOOT_AUTOCONF, |
| 24 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 23 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
| 25 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 26 | .type = PORT_SCIF, | 24 | .type = PORT_SCIF, |
| 27 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x700)), | ||
| 28 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 25 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
| 29 | }; | 26 | }; |
| 30 | 27 | ||
| 28 | static struct resource scif0_resources[] = { | ||
| 29 | DEFINE_RES_MEM(0xffe00000, 0x100), | ||
| 30 | DEFINE_RES_IRQ(evt2irq(0x700)), | ||
| 31 | }; | ||
| 32 | |||
| 31 | static struct platform_device scif0_device = { | 33 | static struct platform_device scif0_device = { |
| 32 | .name = "sh-sci", | 34 | .name = "sh-sci", |
| 33 | .id = 0, | 35 | .id = 0, |
| 36 | .resource = scif0_resources, | ||
| 37 | .num_resources = ARRAY_SIZE(scif0_resources), | ||
| 34 | .dev = { | 38 | .dev = { |
| 35 | .platform_data = &scif0_platform_data, | 39 | .platform_data = &scif0_platform_data, |
| 36 | }, | 40 | }, |
| 37 | }; | 41 | }; |
| 38 | 42 | ||
| 39 | static struct plat_sci_port scif1_platform_data = { | 43 | static struct plat_sci_port scif1_platform_data = { |
| 40 | .mapbase = 0xffe08000, | ||
| 41 | .flags = UPF_BOOT_AUTOCONF, | 44 | .flags = UPF_BOOT_AUTOCONF, |
| 42 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 45 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
| 43 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 44 | .type = PORT_SCIF, | 46 | .type = PORT_SCIF, |
| 45 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xb80)), | ||
| 46 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 47 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
| 47 | }; | 48 | }; |
| 48 | 49 | ||
| 50 | static struct resource scif1_resources[] = { | ||
| 51 | DEFINE_RES_MEM(0xffe08000, 0x100), | ||
| 52 | DEFINE_RES_IRQ(evt2irq(0xb80)), | ||
| 53 | }; | ||
| 54 | |||
| 49 | static struct platform_device scif1_device = { | 55 | static struct platform_device scif1_device = { |
| 50 | .name = "sh-sci", | 56 | .name = "sh-sci", |
| 51 | .id = 1, | 57 | .id = 1, |
| 58 | .resource = scif1_resources, | ||
| 59 | .num_resources = ARRAY_SIZE(scif1_resources), | ||
| 52 | .dev = { | 60 | .dev = { |
| 53 | .platform_data = &scif1_platform_data, | 61 | .platform_data = &scif1_platform_data, |
| 54 | }, | 62 | }, |
| 55 | }; | 63 | }; |
| 56 | 64 | ||
| 57 | static struct plat_sci_port scif2_platform_data = { | 65 | static struct plat_sci_port scif2_platform_data = { |
| 58 | .mapbase = 0xffe10000, | ||
| 59 | .flags = UPF_BOOT_AUTOCONF, | 66 | .flags = UPF_BOOT_AUTOCONF, |
| 60 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 67 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
| 61 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 62 | .type = PORT_SCIF, | 68 | .type = PORT_SCIF, |
| 63 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xf00)), | ||
| 64 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 69 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
| 65 | }; | 70 | }; |
| 66 | 71 | ||
| 72 | static struct resource scif2_resources[] = { | ||
| 73 | DEFINE_RES_MEM(0xffe10000, 0x100), | ||
| 74 | DEFINE_RES_IRQ(evt2irq(0xf00)), | ||
| 75 | }; | ||
| 76 | |||
| 67 | static struct platform_device scif2_device = { | 77 | static struct platform_device scif2_device = { |
| 68 | .name = "sh-sci", | 78 | .name = "sh-sci", |
| 69 | .id = 2, | 79 | .id = 2, |
| 80 | .resource = scif2_resources, | ||
| 81 | .num_resources = ARRAY_SIZE(scif2_resources), | ||
| 70 | .dev = { | 82 | .dev = { |
| 71 | .platform_data = &scif2_platform_data, | 83 | .platform_data = &scif2_platform_data, |
| 72 | }, | 84 | }, |
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c index 256ea7a45164..e1ba8cb74e5a 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c | |||
| @@ -16,170 +16,210 @@ | |||
| 16 | #include <linux/io.h> | 16 | #include <linux/io.h> |
| 17 | 17 | ||
| 18 | static struct plat_sci_port scif0_platform_data = { | 18 | static struct plat_sci_port scif0_platform_data = { |
| 19 | .mapbase = 0xff923000, | ||
| 20 | .flags = UPF_BOOT_AUTOCONF, | 19 | .flags = UPF_BOOT_AUTOCONF, |
| 21 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | 20 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
| 22 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 23 | .type = PORT_SCIF, | 21 | .type = PORT_SCIF, |
| 24 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x9a0)), | 22 | }; |
| 23 | |||
| 24 | static struct resource scif0_resources[] = { | ||
| 25 | DEFINE_RES_MEM(0xff923000, 0x100), | ||
| 26 | DEFINE_RES_IRQ(evt2irq(0x9a0)), | ||
| 25 | }; | 27 | }; |
| 26 | 28 | ||
| 27 | static struct platform_device scif0_device = { | 29 | static struct platform_device scif0_device = { |
| 28 | .name = "sh-sci", | 30 | .name = "sh-sci", |
| 29 | .id = 0, | 31 | .id = 0, |
| 32 | .resource = scif0_resources, | ||
| 33 | .num_resources = ARRAY_SIZE(scif0_resources), | ||
| 30 | .dev = { | 34 | .dev = { |
| 31 | .platform_data = &scif0_platform_data, | 35 | .platform_data = &scif0_platform_data, |
| 32 | }, | 36 | }, |
| 33 | }; | 37 | }; |
| 34 | 38 | ||
| 35 | static struct plat_sci_port scif1_platform_data = { | 39 | static struct plat_sci_port scif1_platform_data = { |
| 36 | .mapbase = 0xff924000, | ||
| 37 | .flags = UPF_BOOT_AUTOCONF, | 40 | .flags = UPF_BOOT_AUTOCONF, |
| 38 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | 41 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
| 39 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 40 | .type = PORT_SCIF, | 42 | .type = PORT_SCIF, |
| 41 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x9c0)), | 43 | }; |
| 44 | |||
| 45 | static struct resource scif1_resources[] = { | ||
| 46 | DEFINE_RES_MEM(0xff924000, 0x100), | ||
| 47 | DEFINE_RES_IRQ(evt2irq(0x9c0)), | ||
| 42 | }; | 48 | }; |
| 43 | 49 | ||
| 44 | static struct platform_device scif1_device = { | 50 | static struct platform_device scif1_device = { |
| 45 | .name = "sh-sci", | 51 | .name = "sh-sci", |
| 46 | .id = 1, | 52 | .id = 1, |
| 53 | .resource = scif1_resources, | ||
| 54 | .num_resources = ARRAY_SIZE(scif1_resources), | ||
| 47 | .dev = { | 55 | .dev = { |
| 48 | .platform_data = &scif1_platform_data, | 56 | .platform_data = &scif1_platform_data, |
| 49 | }, | 57 | }, |
| 50 | }; | 58 | }; |
| 51 | 59 | ||
| 52 | static struct plat_sci_port scif2_platform_data = { | 60 | static struct plat_sci_port scif2_platform_data = { |
| 53 | .mapbase = 0xff925000, | ||
| 54 | .flags = UPF_BOOT_AUTOCONF, | 61 | .flags = UPF_BOOT_AUTOCONF, |
| 55 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | 62 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
| 56 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 57 | .type = PORT_SCIF, | 63 | .type = PORT_SCIF, |
| 58 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x9e0)), | 64 | }; |
| 65 | |||
| 66 | static struct resource scif2_resources[] = { | ||
| 67 | DEFINE_RES_MEM(0xff925000, 0x100), | ||
| 68 | DEFINE_RES_IRQ(evt2irq(0x9e0)), | ||
| 59 | }; | 69 | }; |
| 60 | 70 | ||
| 61 | static struct platform_device scif2_device = { | 71 | static struct platform_device scif2_device = { |
| 62 | .name = "sh-sci", | 72 | .name = "sh-sci", |
| 63 | .id = 2, | 73 | .id = 2, |
| 74 | .resource = scif2_resources, | ||
| 75 | .num_resources = ARRAY_SIZE(scif2_resources), | ||
| 64 | .dev = { | 76 | .dev = { |
| 65 | .platform_data = &scif2_platform_data, | 77 | .platform_data = &scif2_platform_data, |
| 66 | }, | 78 | }, |
| 67 | }; | 79 | }; |
| 68 | 80 | ||
| 69 | static struct plat_sci_port scif3_platform_data = { | 81 | static struct plat_sci_port scif3_platform_data = { |
| 70 | .mapbase = 0xff926000, | ||
| 71 | .flags = UPF_BOOT_AUTOCONF, | 82 | .flags = UPF_BOOT_AUTOCONF, |
| 72 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | 83 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
| 73 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 74 | .type = PORT_SCIF, | 84 | .type = PORT_SCIF, |
| 75 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xa00)), | 85 | }; |
| 86 | |||
| 87 | static struct resource scif3_resources[] = { | ||
| 88 | DEFINE_RES_MEM(0xff926000, 0x100), | ||
| 89 | DEFINE_RES_IRQ(evt2irq(0xa00)), | ||
| 76 | }; | 90 | }; |
| 77 | 91 | ||
| 78 | static struct platform_device scif3_device = { | 92 | static struct platform_device scif3_device = { |
| 79 | .name = "sh-sci", | 93 | .name = "sh-sci", |
| 80 | .id = 3, | 94 | .id = 3, |
| 95 | .resource = scif3_resources, | ||
| 96 | .num_resources = ARRAY_SIZE(scif3_resources), | ||
| 81 | .dev = { | 97 | .dev = { |
| 82 | .platform_data = &scif3_platform_data, | 98 | .platform_data = &scif3_platform_data, |
| 83 | }, | 99 | }, |
| 84 | }; | 100 | }; |
| 85 | 101 | ||
| 86 | static struct plat_sci_port scif4_platform_data = { | 102 | static struct plat_sci_port scif4_platform_data = { |
| 87 | .mapbase = 0xff927000, | ||
| 88 | .flags = UPF_BOOT_AUTOCONF, | 103 | .flags = UPF_BOOT_AUTOCONF, |
| 89 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | 104 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
| 90 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 91 | .type = PORT_SCIF, | 105 | .type = PORT_SCIF, |
| 92 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xa20)), | 106 | }; |
| 107 | |||
| 108 | static struct resource scif4_resources[] = { | ||
| 109 | DEFINE_RES_MEM(0xff927000, 0x100), | ||
| 110 | DEFINE_RES_IRQ(evt2irq(0xa20)), | ||
| 93 | }; | 111 | }; |
| 94 | 112 | ||
| 95 | static struct platform_device scif4_device = { | 113 | static struct platform_device scif4_device = { |
| 96 | .name = "sh-sci", | 114 | .name = "sh-sci", |
| 97 | .id = 4, | 115 | .id = 4, |
| 116 | .resource = scif4_resources, | ||
| 117 | .num_resources = ARRAY_SIZE(scif4_resources), | ||
| 98 | .dev = { | 118 | .dev = { |
| 99 | .platform_data = &scif4_platform_data, | 119 | .platform_data = &scif4_platform_data, |
| 100 | }, | 120 | }, |
| 101 | }; | 121 | }; |
| 102 | 122 | ||
| 103 | static struct plat_sci_port scif5_platform_data = { | 123 | static struct plat_sci_port scif5_platform_data = { |
| 104 | .mapbase = 0xff928000, | ||
| 105 | .flags = UPF_BOOT_AUTOCONF, | 124 | .flags = UPF_BOOT_AUTOCONF, |
| 106 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | 125 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
| 107 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 108 | .type = PORT_SCIF, | 126 | .type = PORT_SCIF, |
| 109 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xa40)), | 127 | }; |
| 128 | |||
| 129 | static struct resource scif5_resources[] = { | ||
| 130 | DEFINE_RES_MEM(0xff928000, 0x100), | ||
| 131 | DEFINE_RES_IRQ(evt2irq(0xa40)), | ||
| 110 | }; | 132 | }; |
| 111 | 133 | ||
| 112 | static struct platform_device scif5_device = { | 134 | static struct platform_device scif5_device = { |
| 113 | .name = "sh-sci", | 135 | .name = "sh-sci", |
| 114 | .id = 5, | 136 | .id = 5, |
| 137 | .resource = scif5_resources, | ||
| 138 | .num_resources = ARRAY_SIZE(scif5_resources), | ||
| 115 | .dev = { | 139 | .dev = { |
| 116 | .platform_data = &scif5_platform_data, | 140 | .platform_data = &scif5_platform_data, |
| 117 | }, | 141 | }, |
| 118 | }; | 142 | }; |
| 119 | 143 | ||
| 120 | static struct plat_sci_port scif6_platform_data = { | 144 | static struct plat_sci_port scif6_platform_data = { |
| 121 | .mapbase = 0xff929000, | ||
| 122 | .flags = UPF_BOOT_AUTOCONF, | 145 | .flags = UPF_BOOT_AUTOCONF, |
| 123 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | 146 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
| 124 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 125 | .type = PORT_SCIF, | 147 | .type = PORT_SCIF, |
| 126 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xa60)), | 148 | }; |
| 149 | |||
| 150 | static struct resource scif6_resources[] = { | ||
| 151 | DEFINE_RES_MEM(0xff929000, 0x100), | ||
| 152 | DEFINE_RES_IRQ(evt2irq(0xa60)), | ||
| 127 | }; | 153 | }; |
| 128 | 154 | ||
| 129 | static struct platform_device scif6_device = { | 155 | static struct platform_device scif6_device = { |
| 130 | .name = "sh-sci", | 156 | .name = "sh-sci", |
| 131 | .id = 6, | 157 | .id = 6, |
| 158 | .resource = scif6_resources, | ||
| 159 | .num_resources = ARRAY_SIZE(scif6_resources), | ||
| 132 | .dev = { | 160 | .dev = { |
| 133 | .platform_data = &scif6_platform_data, | 161 | .platform_data = &scif6_platform_data, |
| 134 | }, | 162 | }, |
| 135 | }; | 163 | }; |
| 136 | 164 | ||
| 137 | static struct plat_sci_port scif7_platform_data = { | 165 | static struct plat_sci_port scif7_platform_data = { |
| 138 | .mapbase = 0xff92a000, | ||
| 139 | .flags = UPF_BOOT_AUTOCONF, | 166 | .flags = UPF_BOOT_AUTOCONF, |
| 140 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | 167 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
| 141 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 142 | .type = PORT_SCIF, | 168 | .type = PORT_SCIF, |
| 143 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xa80)), | 169 | }; |
| 170 | |||
| 171 | static struct resource scif7_resources[] = { | ||
| 172 | DEFINE_RES_MEM(0xff92a000, 0x100), | ||
| 173 | DEFINE_RES_IRQ(evt2irq(0xa80)), | ||
| 144 | }; | 174 | }; |
| 145 | 175 | ||
| 146 | static struct platform_device scif7_device = { | 176 | static struct platform_device scif7_device = { |
| 147 | .name = "sh-sci", | 177 | .name = "sh-sci", |
| 148 | .id = 7, | 178 | .id = 7, |
| 179 | .resource = scif7_resources, | ||
| 180 | .num_resources = ARRAY_SIZE(scif7_resources), | ||
| 149 | .dev = { | 181 | .dev = { |
| 150 | .platform_data = &scif7_platform_data, | 182 | .platform_data = &scif7_platform_data, |
| 151 | }, | 183 | }, |
| 152 | }; | 184 | }; |
| 153 | 185 | ||
| 154 | static struct plat_sci_port scif8_platform_data = { | 186 | static struct plat_sci_port scif8_platform_data = { |
| 155 | .mapbase = 0xff92b000, | ||
| 156 | .flags = UPF_BOOT_AUTOCONF, | 187 | .flags = UPF_BOOT_AUTOCONF, |
| 157 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | 188 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
| 158 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 159 | .type = PORT_SCIF, | 189 | .type = PORT_SCIF, |
| 160 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xaa0)), | 190 | }; |
| 191 | |||
| 192 | static struct resource scif8_resources[] = { | ||
| 193 | DEFINE_RES_MEM(0xff92b000, 0x100), | ||
| 194 | DEFINE_RES_IRQ(evt2irq(0xaa0)), | ||
| 161 | }; | 195 | }; |
| 162 | 196 | ||
| 163 | static struct platform_device scif8_device = { | 197 | static struct platform_device scif8_device = { |
| 164 | .name = "sh-sci", | 198 | .name = "sh-sci", |
| 165 | .id = 8, | 199 | .id = 8, |
| 200 | .resource = scif8_resources, | ||
| 201 | .num_resources = ARRAY_SIZE(scif8_resources), | ||
| 166 | .dev = { | 202 | .dev = { |
| 167 | .platform_data = &scif8_platform_data, | 203 | .platform_data = &scif8_platform_data, |
| 168 | }, | 204 | }, |
| 169 | }; | 205 | }; |
| 170 | 206 | ||
| 171 | static struct plat_sci_port scif9_platform_data = { | 207 | static struct plat_sci_port scif9_platform_data = { |
| 172 | .mapbase = 0xff92c000, | ||
| 173 | .flags = UPF_BOOT_AUTOCONF, | 208 | .flags = UPF_BOOT_AUTOCONF, |
| 174 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | 209 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
| 175 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 176 | .type = PORT_SCIF, | 210 | .type = PORT_SCIF, |
| 177 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xac0)), | 211 | }; |
| 212 | |||
| 213 | static struct resource scif9_resources[] = { | ||
| 214 | DEFINE_RES_MEM(0xff92c000, 0x100), | ||
| 215 | DEFINE_RES_IRQ(evt2irq(0xac0)), | ||
| 178 | }; | 216 | }; |
| 179 | 217 | ||
| 180 | static struct platform_device scif9_device = { | 218 | static struct platform_device scif9_device = { |
| 181 | .name = "sh-sci", | 219 | .name = "sh-sci", |
| 182 | .id = 9, | 220 | .id = 9, |
| 221 | .resource = scif9_resources, | ||
| 222 | .num_resources = ARRAY_SIZE(scif9_resources), | ||
| 183 | .dev = { | 223 | .dev = { |
| 184 | .platform_data = &scif9_platform_data, | 224 | .platform_data = &scif9_platform_data, |
| 185 | }, | 225 | }, |
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c index de45b704687a..668e54bafa86 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c | |||
| @@ -18,36 +18,44 @@ | |||
| 18 | #include <cpu/dma-register.h> | 18 | #include <cpu/dma-register.h> |
| 19 | 19 | ||
| 20 | static struct plat_sci_port scif0_platform_data = { | 20 | static struct plat_sci_port scif0_platform_data = { |
| 21 | .mapbase = 0xffe00000, | ||
| 22 | .flags = UPF_BOOT_AUTOCONF, | 21 | .flags = UPF_BOOT_AUTOCONF, |
| 23 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | 22 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, |
| 24 | .scbrr_algo_id = SCBRR_ALGO_1, | ||
| 25 | .type = PORT_SCIF, | 23 | .type = PORT_SCIF, |
| 26 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x700)), | ||
| 27 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 24 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
| 28 | }; | 25 | }; |
| 29 | 26 | ||
| 27 | static struct resource scif0_resources[] = { | ||
| 28 | DEFINE_RES_MEM(0xffe00000, 0x100), | ||
| 29 | DEFINE_RES_IRQ(evt2irq(0x700)), | ||
| 30 | }; | ||
| 31 | |||
| 30 | static struct platform_device scif0_device = { | 32 | static struct platform_device scif0_device = { |
| 31 | .name = "sh-sci", | 33 | .name = "sh-sci", |
| 32 | .id = 0, | 34 | .id = 0, |
| 35 | .resource = scif0_resources, | ||
| 36 | .num_resources = ARRAY_SIZE(scif0_resources), | ||
| 33 | .dev = { | 37 | .dev = { |
| 34 | .platform_data = &scif0_platform_data, | 38 | .platform_data = &scif0_platform_data, |
| 35 | }, | 39 | }, |
| 36 | }; | 40 | }; |
| 37 | 41 | ||
| 38 | static struct plat_sci_port scif1_platform_data = { | 42 | static struct plat_sci_port scif1_platform_data = { |
| 39 | .mapbase = 0xffe10000, | ||
| 40 | .flags = UPF_BOOT_AUTOCONF, | 43 | .flags = UPF_BOOT_AUTOCONF, |
| 41 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | 44 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, |
| 42 | .scbrr_algo_id = SCBRR_ALGO_1, | ||
| 43 | .type = PORT_SCIF, | 45 | .type = PORT_SCIF, |
| 44 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xb80)), | ||
| 45 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 46 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
| 46 | }; | 47 | }; |
| 47 | 48 | ||
| 49 | static struct resource scif1_resources[] = { | ||
| 50 | DEFINE_RES_MEM(0xffe10000, 0x100), | ||
| 51 | DEFINE_RES_IRQ(evt2irq(0xb80)), | ||
| 52 | }; | ||
| 53 | |||
| 48 | static struct platform_device scif1_device = { | 54 | static struct platform_device scif1_device = { |
| 49 | .name = "sh-sci", | 55 | .name = "sh-sci", |
| 50 | .id = 1, | 56 | .id = 1, |
| 57 | .resource = scif1_resources, | ||
| 58 | .num_resources = ARRAY_SIZE(scif1_resources), | ||
| 51 | .dev = { | 59 | .dev = { |
| 52 | .platform_data = &scif1_platform_data, | 60 | .platform_data = &scif1_platform_data, |
| 53 | }, | 61 | }, |
| @@ -409,9 +417,7 @@ void __init plat_early_device_setup(void) | |||
| 409 | { | 417 | { |
| 410 | if (mach_is_sh2007()) { | 418 | if (mach_is_sh2007()) { |
| 411 | scif0_platform_data.scscr &= ~SCSCR_CKE1; | 419 | scif0_platform_data.scscr &= ~SCSCR_CKE1; |
| 412 | scif0_platform_data.scbrr_algo_id = SCBRR_ALGO_2; | ||
| 413 | scif1_platform_data.scscr &= ~SCSCR_CKE1; | 420 | scif1_platform_data.scscr &= ~SCSCR_CKE1; |
| 414 | scif1_platform_data.scbrr_algo_id = SCBRR_ALGO_2; | ||
| 415 | } | 421 | } |
| 416 | 422 | ||
| 417 | early_platform_add_devices(sh7780_early_devices, | 423 | early_platform_add_devices(sh7780_early_devices, |
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c index 0968ecb962e6..4aa679140209 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c | |||
| @@ -20,108 +20,132 @@ | |||
| 20 | #include <cpu/dma-register.h> | 20 | #include <cpu/dma-register.h> |
| 21 | 21 | ||
| 22 | static struct plat_sci_port scif0_platform_data = { | 22 | static struct plat_sci_port scif0_platform_data = { |
| 23 | .mapbase = 0xffea0000, | ||
| 24 | .flags = UPF_BOOT_AUTOCONF, | 23 | .flags = UPF_BOOT_AUTOCONF, |
| 25 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | 24 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, |
| 26 | .scbrr_algo_id = SCBRR_ALGO_1, | ||
| 27 | .type = PORT_SCIF, | 25 | .type = PORT_SCIF, |
| 28 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x700)), | ||
| 29 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 26 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
| 30 | }; | 27 | }; |
| 31 | 28 | ||
| 29 | static struct resource scif0_resources[] = { | ||
| 30 | DEFINE_RES_MEM(0xffea0000, 0x100), | ||
| 31 | DEFINE_RES_IRQ(evt2irq(0x700)), | ||
| 32 | }; | ||
| 33 | |||
| 32 | static struct platform_device scif0_device = { | 34 | static struct platform_device scif0_device = { |
| 33 | .name = "sh-sci", | 35 | .name = "sh-sci", |
| 34 | .id = 0, | 36 | .id = 0, |
| 37 | .resource = scif0_resources, | ||
| 38 | .num_resources = ARRAY_SIZE(scif0_resources), | ||
| 35 | .dev = { | 39 | .dev = { |
| 36 | .platform_data = &scif0_platform_data, | 40 | .platform_data = &scif0_platform_data, |
| 37 | }, | 41 | }, |
| 38 | }; | 42 | }; |
| 39 | 43 | ||
| 40 | static struct plat_sci_port scif1_platform_data = { | 44 | static struct plat_sci_port scif1_platform_data = { |
| 41 | .mapbase = 0xffeb0000, | ||
| 42 | .flags = UPF_BOOT_AUTOCONF, | 45 | .flags = UPF_BOOT_AUTOCONF, |
| 43 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | 46 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, |
| 44 | .scbrr_algo_id = SCBRR_ALGO_1, | ||
| 45 | .type = PORT_SCIF, | 47 | .type = PORT_SCIF, |
| 46 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x780)), | ||
| 47 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 48 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
| 48 | }; | 49 | }; |
| 49 | 50 | ||
| 51 | static struct resource scif1_resources[] = { | ||
| 52 | DEFINE_RES_MEM(0xffeb0000, 0x100), | ||
| 53 | DEFINE_RES_IRQ(evt2irq(0x780)), | ||
| 54 | }; | ||
| 55 | |||
| 50 | static struct platform_device scif1_device = { | 56 | static struct platform_device scif1_device = { |
| 51 | .name = "sh-sci", | 57 | .name = "sh-sci", |
| 52 | .id = 1, | 58 | .id = 1, |
| 59 | .resource = scif1_resources, | ||
| 60 | .num_resources = ARRAY_SIZE(scif1_resources), | ||
| 53 | .dev = { | 61 | .dev = { |
| 54 | .platform_data = &scif1_platform_data, | 62 | .platform_data = &scif1_platform_data, |
| 55 | }, | 63 | }, |
| 56 | }; | 64 | }; |
| 57 | 65 | ||
| 58 | static struct plat_sci_port scif2_platform_data = { | 66 | static struct plat_sci_port scif2_platform_data = { |
| 59 | .mapbase = 0xffec0000, | ||
| 60 | .flags = UPF_BOOT_AUTOCONF, | 67 | .flags = UPF_BOOT_AUTOCONF, |
| 61 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | 68 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, |
| 62 | .scbrr_algo_id = SCBRR_ALGO_1, | ||
| 63 | .type = PORT_SCIF, | 69 | .type = PORT_SCIF, |
| 64 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x980)), | ||
| 65 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 70 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
| 66 | }; | 71 | }; |
| 67 | 72 | ||
| 73 | static struct resource scif2_resources[] = { | ||
| 74 | DEFINE_RES_MEM(0xffec0000, 0x100), | ||
| 75 | DEFINE_RES_IRQ(evt2irq(0x980)), | ||
| 76 | }; | ||
| 77 | |||
| 68 | static struct platform_device scif2_device = { | 78 | static struct platform_device scif2_device = { |
| 69 | .name = "sh-sci", | 79 | .name = "sh-sci", |
| 70 | .id = 2, | 80 | .id = 2, |
| 81 | .resource = scif2_resources, | ||
| 82 | .num_resources = ARRAY_SIZE(scif2_resources), | ||
| 71 | .dev = { | 83 | .dev = { |
| 72 | .platform_data = &scif2_platform_data, | 84 | .platform_data = &scif2_platform_data, |
| 73 | }, | 85 | }, |
| 74 | }; | 86 | }; |
| 75 | 87 | ||
| 76 | static struct plat_sci_port scif3_platform_data = { | 88 | static struct plat_sci_port scif3_platform_data = { |
| 77 | .mapbase = 0xffed0000, | ||
| 78 | .flags = UPF_BOOT_AUTOCONF, | 89 | .flags = UPF_BOOT_AUTOCONF, |
| 79 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | 90 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, |
| 80 | .scbrr_algo_id = SCBRR_ALGO_1, | ||
| 81 | .type = PORT_SCIF, | 91 | .type = PORT_SCIF, |
| 82 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x9a0)), | ||
| 83 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 92 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
| 84 | }; | 93 | }; |
| 85 | 94 | ||
| 95 | static struct resource scif3_resources[] = { | ||
| 96 | DEFINE_RES_MEM(0xffed0000, 0x100), | ||
| 97 | DEFINE_RES_IRQ(evt2irq(0x9a0)), | ||
| 98 | }; | ||
| 99 | |||
| 86 | static struct platform_device scif3_device = { | 100 | static struct platform_device scif3_device = { |
| 87 | .name = "sh-sci", | 101 | .name = "sh-sci", |
| 88 | .id = 3, | 102 | .id = 3, |
| 103 | .resource = scif3_resources, | ||
| 104 | .num_resources = ARRAY_SIZE(scif3_resources), | ||
| 89 | .dev = { | 105 | .dev = { |
| 90 | .platform_data = &scif3_platform_data, | 106 | .platform_data = &scif3_platform_data, |
| 91 | }, | 107 | }, |
| 92 | }; | 108 | }; |
| 93 | 109 | ||
| 94 | static struct plat_sci_port scif4_platform_data = { | 110 | static struct plat_sci_port scif4_platform_data = { |
| 95 | .mapbase = 0xffee0000, | ||
| 96 | .flags = UPF_BOOT_AUTOCONF, | 111 | .flags = UPF_BOOT_AUTOCONF, |
| 97 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | 112 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, |
| 98 | .scbrr_algo_id = SCBRR_ALGO_1, | ||
| 99 | .type = PORT_SCIF, | 113 | .type = PORT_SCIF, |
| 100 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x9c0)), | ||
| 101 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 114 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
| 102 | }; | 115 | }; |
| 103 | 116 | ||
| 117 | static struct resource scif4_resources[] = { | ||
| 118 | DEFINE_RES_MEM(0xffee0000, 0x100), | ||
| 119 | DEFINE_RES_IRQ(evt2irq(0x9c0)), | ||
| 120 | }; | ||
| 121 | |||
| 104 | static struct platform_device scif4_device = { | 122 | static struct platform_device scif4_device = { |
| 105 | .name = "sh-sci", | 123 | .name = "sh-sci", |
| 106 | .id = 4, | 124 | .id = 4, |
| 125 | .resource = scif4_resources, | ||
| 126 | .num_resources = ARRAY_SIZE(scif4_resources), | ||
| 107 | .dev = { | 127 | .dev = { |
| 108 | .platform_data = &scif4_platform_data, | 128 | .platform_data = &scif4_platform_data, |
| 109 | }, | 129 | }, |
| 110 | }; | 130 | }; |
| 111 | 131 | ||
| 112 | static struct plat_sci_port scif5_platform_data = { | 132 | static struct plat_sci_port scif5_platform_data = { |
| 113 | .mapbase = 0xffef0000, | ||
| 114 | .flags = UPF_BOOT_AUTOCONF, | 133 | .flags = UPF_BOOT_AUTOCONF, |
| 115 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | 134 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, |
| 116 | .scbrr_algo_id = SCBRR_ALGO_1, | ||
| 117 | .type = PORT_SCIF, | 135 | .type = PORT_SCIF, |
| 118 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x9e0)), | ||
| 119 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 136 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
| 120 | }; | 137 | }; |
| 121 | 138 | ||
| 139 | static struct resource scif5_resources[] = { | ||
| 140 | DEFINE_RES_MEM(0xffef0000, 0x100), | ||
| 141 | DEFINE_RES_IRQ(evt2irq(0x9e0)), | ||
| 142 | }; | ||
| 143 | |||
| 122 | static struct platform_device scif5_device = { | 144 | static struct platform_device scif5_device = { |
| 123 | .name = "sh-sci", | 145 | .name = "sh-sci", |
| 124 | .id = 5, | 146 | .id = 5, |
| 147 | .resource = scif5_resources, | ||
| 148 | .num_resources = ARRAY_SIZE(scif5_resources), | ||
| 125 | .dev = { | 149 | .dev = { |
| 126 | .platform_data = &scif5_platform_data, | 150 | .platform_data = &scif5_platform_data, |
| 127 | }, | 151 | }, |
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c index ab52d4d4484d..5d619a551a3b 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c | |||
| @@ -28,21 +28,25 @@ | |||
| 28 | #include <asm/mmzone.h> | 28 | #include <asm/mmzone.h> |
| 29 | 29 | ||
| 30 | static struct plat_sci_port scif0_platform_data = { | 30 | static struct plat_sci_port scif0_platform_data = { |
| 31 | .mapbase = 0xffea0000, | ||
| 32 | .flags = UPF_BOOT_AUTOCONF, | 31 | .flags = UPF_BOOT_AUTOCONF, |
| 33 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | 32 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, |
| 34 | .scbrr_algo_id = SCBRR_ALGO_1, | ||
| 35 | .type = PORT_SCIF, | 33 | .type = PORT_SCIF, |
| 36 | .irqs = { evt2irq(0x700), | ||
| 37 | evt2irq(0x720), | ||
| 38 | evt2irq(0x760), | ||
| 39 | evt2irq(0x740) }, | ||
| 40 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 34 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
| 41 | }; | 35 | }; |
| 42 | 36 | ||
| 37 | static struct resource scif0_resources[] = { | ||
| 38 | DEFINE_RES_MEM(0xffea0000, 0x100), | ||
| 39 | DEFINE_RES_IRQ(evt2irq(0x700)), | ||
| 40 | DEFINE_RES_IRQ(evt2irq(0x720)), | ||
| 41 | DEFINE_RES_IRQ(evt2irq(0x760)), | ||
| 42 | DEFINE_RES_IRQ(evt2irq(0x740)), | ||
| 43 | }; | ||
| 44 | |||
| 43 | static struct platform_device scif0_device = { | 45 | static struct platform_device scif0_device = { |
| 44 | .name = "sh-sci", | 46 | .name = "sh-sci", |
| 45 | .id = 0, | 47 | .id = 0, |
| 48 | .resource = scif0_resources, | ||
| 49 | .num_resources = ARRAY_SIZE(scif0_resources), | ||
| 46 | .dev = { | 50 | .dev = { |
| 47 | .platform_data = &scif0_platform_data, | 51 | .platform_data = &scif0_platform_data, |
| 48 | }, | 52 | }, |
| @@ -52,90 +56,119 @@ static struct platform_device scif0_device = { | |||
| 52 | * The rest of these all have multiplexed IRQs | 56 | * The rest of these all have multiplexed IRQs |
| 53 | */ | 57 | */ |
| 54 | static struct plat_sci_port scif1_platform_data = { | 58 | static struct plat_sci_port scif1_platform_data = { |
| 55 | .mapbase = 0xffeb0000, | ||
| 56 | .flags = UPF_BOOT_AUTOCONF, | 59 | .flags = UPF_BOOT_AUTOCONF, |
| 57 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | 60 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, |
| 58 | .scbrr_algo_id = SCBRR_ALGO_1, | ||
| 59 | .type = PORT_SCIF, | 61 | .type = PORT_SCIF, |
| 60 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x780)), | ||
| 61 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 62 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
| 62 | }; | 63 | }; |
| 63 | 64 | ||
| 65 | static struct resource scif1_resources[] = { | ||
| 66 | DEFINE_RES_MEM(0xffeb0000, 0x100), | ||
| 67 | DEFINE_RES_IRQ(evt2irq(0x780)), | ||
| 68 | }; | ||
| 69 | |||
| 70 | static struct resource scif1_demux_resources[] = { | ||
| 71 | DEFINE_RES_MEM(0xffeb0000, 0x100), | ||
| 72 | /* Placeholders, see sh7786_devices_setup() */ | ||
| 73 | DEFINE_RES_IRQ(0), | ||
| 74 | DEFINE_RES_IRQ(0), | ||
| 75 | DEFINE_RES_IRQ(0), | ||
| 76 | DEFINE_RES_IRQ(0), | ||
| 77 | }; | ||
| 78 | |||
| 64 | static struct platform_device scif1_device = { | 79 | static struct platform_device scif1_device = { |
| 65 | .name = "sh-sci", | 80 | .name = "sh-sci", |
| 66 | .id = 1, | 81 | .id = 1, |
| 82 | .resource = scif1_resources, | ||
| 83 | .num_resources = ARRAY_SIZE(scif1_resources), | ||
| 67 | .dev = { | 84 | .dev = { |
| 68 | .platform_data = &scif1_platform_data, | 85 | .platform_data = &scif1_platform_data, |
| 69 | }, | 86 | }, |
| 70 | }; | 87 | }; |
| 71 | 88 | ||
| 72 | static struct plat_sci_port scif2_platform_data = { | 89 | static struct plat_sci_port scif2_platform_data = { |
| 73 | .mapbase = 0xffec0000, | ||
| 74 | .flags = UPF_BOOT_AUTOCONF, | 90 | .flags = UPF_BOOT_AUTOCONF, |
| 75 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | 91 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, |
| 76 | .scbrr_algo_id = SCBRR_ALGO_1, | ||
| 77 | .type = PORT_SCIF, | 92 | .type = PORT_SCIF, |
| 78 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x840)), | ||
| 79 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 93 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
| 80 | }; | 94 | }; |
| 81 | 95 | ||
| 96 | static struct resource scif2_resources[] = { | ||
| 97 | DEFINE_RES_MEM(0xffec0000, 0x100), | ||
| 98 | DEFINE_RES_IRQ(evt2irq(0x840)), | ||
| 99 | }; | ||
| 100 | |||
| 82 | static struct platform_device scif2_device = { | 101 | static struct platform_device scif2_device = { |
| 83 | .name = "sh-sci", | 102 | .name = "sh-sci", |
| 84 | .id = 2, | 103 | .id = 2, |
| 104 | .resource = scif2_resources, | ||
| 105 | .num_resources = ARRAY_SIZE(scif2_resources), | ||
| 85 | .dev = { | 106 | .dev = { |
| 86 | .platform_data = &scif2_platform_data, | 107 | .platform_data = &scif2_platform_data, |
| 87 | }, | 108 | }, |
| 88 | }; | 109 | }; |
| 89 | 110 | ||
| 90 | static struct plat_sci_port scif3_platform_data = { | 111 | static struct plat_sci_port scif3_platform_data = { |
| 91 | .mapbase = 0xffed0000, | ||
| 92 | .flags = UPF_BOOT_AUTOCONF, | 112 | .flags = UPF_BOOT_AUTOCONF, |
| 93 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | 113 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, |
| 94 | .scbrr_algo_id = SCBRR_ALGO_1, | ||
| 95 | .type = PORT_SCIF, | 114 | .type = PORT_SCIF, |
| 96 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x860)), | ||
| 97 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 115 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
| 98 | }; | 116 | }; |
| 99 | 117 | ||
| 118 | static struct resource scif3_resources[] = { | ||
| 119 | DEFINE_RES_MEM(0xffed0000, 0x100), | ||
| 120 | DEFINE_RES_IRQ(evt2irq(0x860)), | ||
| 121 | }; | ||
| 122 | |||
| 100 | static struct platform_device scif3_device = { | 123 | static struct platform_device scif3_device = { |
| 101 | .name = "sh-sci", | 124 | .name = "sh-sci", |
| 102 | .id = 3, | 125 | .id = 3, |
| 126 | .resource = scif3_resources, | ||
| 127 | .num_resources = ARRAY_SIZE(scif3_resources), | ||
| 103 | .dev = { | 128 | .dev = { |
| 104 | .platform_data = &scif3_platform_data, | 129 | .platform_data = &scif3_platform_data, |
| 105 | }, | 130 | }, |
| 106 | }; | 131 | }; |
| 107 | 132 | ||
| 108 | static struct plat_sci_port scif4_platform_data = { | 133 | static struct plat_sci_port scif4_platform_data = { |
| 109 | .mapbase = 0xffee0000, | ||
| 110 | .flags = UPF_BOOT_AUTOCONF, | 134 | .flags = UPF_BOOT_AUTOCONF, |
| 111 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | 135 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, |
| 112 | .scbrr_algo_id = SCBRR_ALGO_1, | ||
| 113 | .type = PORT_SCIF, | 136 | .type = PORT_SCIF, |
| 114 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x880)), | ||
| 115 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 137 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
| 116 | }; | 138 | }; |
| 117 | 139 | ||
| 140 | static struct resource scif4_resources[] = { | ||
| 141 | DEFINE_RES_MEM(0xffee0000, 0x100), | ||
| 142 | DEFINE_RES_IRQ(evt2irq(0x880)), | ||
| 143 | }; | ||
| 144 | |||
| 118 | static struct platform_device scif4_device = { | 145 | static struct platform_device scif4_device = { |
| 119 | .name = "sh-sci", | 146 | .name = "sh-sci", |
| 120 | .id = 4, | 147 | .id = 4, |
| 148 | .resource = scif4_resources, | ||
| 149 | .num_resources = ARRAY_SIZE(scif4_resources), | ||
| 121 | .dev = { | 150 | .dev = { |
| 122 | .platform_data = &scif4_platform_data, | 151 | .platform_data = &scif4_platform_data, |
| 123 | }, | 152 | }, |
| 124 | }; | 153 | }; |
| 125 | 154 | ||
| 126 | static struct plat_sci_port scif5_platform_data = { | 155 | static struct plat_sci_port scif5_platform_data = { |
| 127 | .mapbase = 0xffef0000, | ||
| 128 | .flags = UPF_BOOT_AUTOCONF, | 156 | .flags = UPF_BOOT_AUTOCONF, |
| 129 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | 157 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, |
| 130 | .scbrr_algo_id = SCBRR_ALGO_1, | ||
| 131 | .type = PORT_SCIF, | 158 | .type = PORT_SCIF, |
| 132 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x8a0)), | ||
| 133 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 159 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
| 134 | }; | 160 | }; |
| 135 | 161 | ||
| 162 | static struct resource scif5_resources[] = { | ||
| 163 | DEFINE_RES_MEM(0xffef0000, 0x100), | ||
| 164 | DEFINE_RES_IRQ(evt2irq(0x8a0)), | ||
| 165 | }; | ||
| 166 | |||
| 136 | static struct platform_device scif5_device = { | 167 | static struct platform_device scif5_device = { |
| 137 | .name = "sh-sci", | 168 | .name = "sh-sci", |
| 138 | .id = 5, | 169 | .id = 5, |
| 170 | .resource = scif5_resources, | ||
| 171 | .num_resources = ARRAY_SIZE(scif5_resources), | ||
| 139 | .dev = { | 172 | .dev = { |
| 140 | .platform_data = &scif5_platform_data, | 173 | .platform_data = &scif5_platform_data, |
| 141 | }, | 174 | }, |
| @@ -1037,13 +1070,16 @@ static int __init sh7786_devices_setup(void) | |||
| 1037 | */ | 1070 | */ |
| 1038 | irq = intc_irq_lookup(sh7786_intc_desc.name, TXI1); | 1071 | irq = intc_irq_lookup(sh7786_intc_desc.name, TXI1); |
| 1039 | if (irq > 0) { | 1072 | if (irq > 0) { |
| 1040 | scif1_platform_data.irqs[SCIx_TXI_IRQ] = irq; | 1073 | scif1_demux_resources[1].start = |
| 1041 | scif1_platform_data.irqs[SCIx_ERI_IRQ] = | ||
| 1042 | intc_irq_lookup(sh7786_intc_desc.name, ERI1); | 1074 | intc_irq_lookup(sh7786_intc_desc.name, ERI1); |
| 1043 | scif1_platform_data.irqs[SCIx_BRI_IRQ] = | 1075 | scif1_demux_resources[2].start = |
| 1044 | intc_irq_lookup(sh7786_intc_desc.name, BRI1); | ||
| 1045 | scif1_platform_data.irqs[SCIx_RXI_IRQ] = | ||
| 1046 | intc_irq_lookup(sh7786_intc_desc.name, RXI1); | 1076 | intc_irq_lookup(sh7786_intc_desc.name, RXI1); |
| 1077 | scif1_demux_resources[3].start = irq; | ||
| 1078 | scif1_demux_resources[4].start = | ||
| 1079 | intc_irq_lookup(sh7786_intc_desc.name, BRI1); | ||
| 1080 | |||
| 1081 | scif1_device.resource = scif1_demux_resources; | ||
| 1082 | scif1_device.num_resources = ARRAY_SIZE(scif1_demux_resources); | ||
| 1047 | } | 1083 | } |
| 1048 | 1084 | ||
| 1049 | ret = platform_add_devices(sh7786_early_devices, | 1085 | ret = platform_add_devices(sh7786_early_devices, |
diff --git a/arch/sh/kernel/cpu/sh4a/setup-shx3.c b/arch/sh/kernel/cpu/sh4a/setup-shx3.c index 688f7ed1bab1..0856bcbb1da0 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-shx3.c +++ b/arch/sh/kernel/cpu/sh4a/setup-shx3.c | |||
| @@ -28,60 +28,72 @@ | |||
| 28 | * all rather than adding infrastructure to hack around it. | 28 | * all rather than adding infrastructure to hack around it. |
| 29 | */ | 29 | */ |
| 30 | static struct plat_sci_port scif0_platform_data = { | 30 | static struct plat_sci_port scif0_platform_data = { |
| 31 | .mapbase = 0xffc30000, | ||
| 32 | .flags = UPF_BOOT_AUTOCONF, | 31 | .flags = UPF_BOOT_AUTOCONF, |
| 33 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 32 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
| 34 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 35 | .type = PORT_SCIF, | 33 | .type = PORT_SCIF, |
| 36 | .irqs = { evt2irq(0x700), | 34 | }; |
| 37 | evt2irq(0x720), | 35 | |
| 38 | evt2irq(0x760), | 36 | static struct resource scif0_resources[] = { |
| 39 | evt2irq(0x740) }, | 37 | DEFINE_RES_MEM(0xffc30000, 0x100), |
| 38 | DEFINE_RES_IRQ(evt2irq(0x700)), | ||
| 39 | DEFINE_RES_IRQ(evt2irq(0x720)), | ||
| 40 | DEFINE_RES_IRQ(evt2irq(0x760)), | ||
| 41 | DEFINE_RES_IRQ(evt2irq(0x740)), | ||
| 40 | }; | 42 | }; |
| 41 | 43 | ||
| 42 | static struct platform_device scif0_device = { | 44 | static struct platform_device scif0_device = { |
| 43 | .name = "sh-sci", | 45 | .name = "sh-sci", |
| 44 | .id = 0, | 46 | .id = 0, |
| 47 | .resource = scif0_resources, | ||
| 48 | .num_resources = ARRAY_SIZE(scif0_resources), | ||
| 45 | .dev = { | 49 | .dev = { |
| 46 | .platform_data = &scif0_platform_data, | 50 | .platform_data = &scif0_platform_data, |
| 47 | }, | 51 | }, |
| 48 | }; | 52 | }; |
| 49 | 53 | ||
| 50 | static struct plat_sci_port scif1_platform_data = { | 54 | static struct plat_sci_port scif1_platform_data = { |
| 51 | .mapbase = 0xffc40000, | ||
| 52 | .flags = UPF_BOOT_AUTOCONF, | 55 | .flags = UPF_BOOT_AUTOCONF, |
| 53 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 56 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
| 54 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 55 | .type = PORT_SCIF, | 57 | .type = PORT_SCIF, |
| 56 | .irqs = { evt2irq(0x780), | 58 | }; |
| 57 | evt2irq(0x7a0), | 59 | |
| 58 | evt2irq(0x7e0), | 60 | static struct resource scif1_resources[] = { |
| 59 | evt2irq(0x7c0) }, | 61 | DEFINE_RES_MEM(0xffc40000, 0x100), |
| 62 | DEFINE_RES_IRQ(evt2irq(0x780)), | ||
| 63 | DEFINE_RES_IRQ(evt2irq(0x7a0)), | ||
| 64 | DEFINE_RES_IRQ(evt2irq(0x7e0)), | ||
| 65 | DEFINE_RES_IRQ(evt2irq(0x7c0)), | ||
| 60 | }; | 66 | }; |
| 61 | 67 | ||
| 62 | static struct platform_device scif1_device = { | 68 | static struct platform_device scif1_device = { |
| 63 | .name = "sh-sci", | 69 | .name = "sh-sci", |
| 64 | .id = 1, | 70 | .id = 1, |
| 71 | .resource = scif1_resources, | ||
| 72 | .num_resources = ARRAY_SIZE(scif1_resources), | ||
| 65 | .dev = { | 73 | .dev = { |
| 66 | .platform_data = &scif1_platform_data, | 74 | .platform_data = &scif1_platform_data, |
| 67 | }, | 75 | }, |
| 68 | }; | 76 | }; |
| 69 | 77 | ||
| 70 | static struct plat_sci_port scif2_platform_data = { | 78 | static struct plat_sci_port scif2_platform_data = { |
| 71 | .mapbase = 0xffc60000, | ||
| 72 | .flags = UPF_BOOT_AUTOCONF, | 79 | .flags = UPF_BOOT_AUTOCONF, |
| 73 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 80 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
| 74 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 75 | .type = PORT_SCIF, | 81 | .type = PORT_SCIF, |
| 76 | .irqs = { evt2irq(0x880), | 82 | }; |
| 77 | evt2irq(0x8a0), | 83 | |
| 78 | evt2irq(0x8e0), | 84 | static struct resource scif2_resources[] = { |
| 79 | evt2irq(0x8c0) }, | 85 | DEFINE_RES_MEM(0xffc60000, 0x100), |
| 86 | DEFINE_RES_IRQ(evt2irq(0x880)), | ||
| 87 | DEFINE_RES_IRQ(evt2irq(0x8a0)), | ||
| 88 | DEFINE_RES_IRQ(evt2irq(0x8e0)), | ||
| 89 | DEFINE_RES_IRQ(evt2irq(0x8c0)), | ||
| 80 | }; | 90 | }; |
| 81 | 91 | ||
| 82 | static struct platform_device scif2_device = { | 92 | static struct platform_device scif2_device = { |
| 83 | .name = "sh-sci", | 93 | .name = "sh-sci", |
| 84 | .id = 2, | 94 | .id = 2, |
| 95 | .resource = scif2_resources, | ||
| 96 | .num_resources = ARRAY_SIZE(scif2_resources), | ||
| 85 | .dev = { | 97 | .dev = { |
| 86 | .platform_data = &scif2_platform_data, | 98 | .platform_data = &scif2_platform_data, |
| 87 | }, | 99 | }, |
diff --git a/arch/sh/kernel/cpu/sh5/setup-sh5.c b/arch/sh/kernel/cpu/sh5/setup-sh5.c index 18419f1de963..14d68213d16b 100644 --- a/arch/sh/kernel/cpu/sh5/setup-sh5.c +++ b/arch/sh/kernel/cpu/sh5/setup-sh5.c | |||
| @@ -17,17 +17,23 @@ | |||
| 17 | #include <asm/addrspace.h> | 17 | #include <asm/addrspace.h> |
| 18 | 18 | ||
| 19 | static struct plat_sci_port scif0_platform_data = { | 19 | static struct plat_sci_port scif0_platform_data = { |
| 20 | .mapbase = PHYS_PERIPHERAL_BLOCK + 0x01030000, | ||
| 21 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, | 20 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, |
| 22 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 21 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
| 23 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
| 24 | .type = PORT_SCIF, | 22 | .type = PORT_SCIF, |
| 25 | .irqs = { 39, 40, 42, 0 }, | 23 | }; |
| 24 | |||
| 25 | static struct resource scif0_resources[] = { | ||
| 26 | DEFINE_RES_MEM(PHYS_PERIPHERAL_BLOCK + 0x01030000, 0x100), | ||
| 27 | DEFINE_RES_IRQ(39), | ||
| 28 | DEFINE_RES_IRQ(40), | ||
| 29 | DEFINE_RES_IRQ(42), | ||
| 26 | }; | 30 | }; |
| 27 | 31 | ||
| 28 | static struct platform_device scif0_device = { | 32 | static struct platform_device scif0_device = { |
| 29 | .name = "sh-sci", | 33 | .name = "sh-sci", |
| 30 | .id = 0, | 34 | .id = 0, |
| 35 | .resource = scif0_resources, | ||
| 36 | .num_resources = ARRAY_SIZE(scif0_resources), | ||
| 31 | .dev = { | 37 | .dev = { |
| 32 | .platform_data = &scif0_platform_data, | 38 | .platform_data = &scif0_platform_data, |
| 33 | }, | 39 | }, |
diff --git a/drivers/Makefile b/drivers/Makefile index 3cc8214f9b26..8e3b8b06c0b2 100644 --- a/drivers/Makefile +++ b/drivers/Makefile | |||
| @@ -118,7 +118,7 @@ obj-$(CONFIG_SGI_SN) += sn/ | |||
| 118 | obj-y += firmware/ | 118 | obj-y += firmware/ |
| 119 | obj-$(CONFIG_CRYPTO) += crypto/ | 119 | obj-$(CONFIG_CRYPTO) += crypto/ |
| 120 | obj-$(CONFIG_SUPERH) += sh/ | 120 | obj-$(CONFIG_SUPERH) += sh/ |
| 121 | obj-$(CONFIG_ARCH_SHMOBILE) += sh/ | 121 | obj-$(CONFIG_ARCH_SHMOBILE_LEGACY) += sh/ |
| 122 | ifndef CONFIG_ARCH_USES_GETTIMEOFFSET | 122 | ifndef CONFIG_ARCH_USES_GETTIMEOFFSET |
| 123 | obj-y += clocksource/ | 123 | obj-y += clocksource/ |
| 124 | endif | 124 | endif |
diff --git a/drivers/bus/mvebu-mbus.c b/drivers/bus/mvebu-mbus.c index 2394e9753ef5..725c46162bbd 100644 --- a/drivers/bus/mvebu-mbus.c +++ b/drivers/bus/mvebu-mbus.c | |||
| @@ -588,12 +588,6 @@ static const struct mvebu_mbus_soc_data mv78xx0_mbus_data = { | |||
| 588 | .show_cpu_target = mvebu_sdram_debug_show_orion, | 588 | .show_cpu_target = mvebu_sdram_debug_show_orion, |
| 589 | }; | 589 | }; |
| 590 | 590 | ||
| 591 | /* | ||
| 592 | * The driver doesn't yet have a DT binding because the details of | ||
| 593 | * this DT binding still need to be sorted out. However, as a | ||
| 594 | * preparation, we already use of_device_id to match a SoC description | ||
| 595 | * string against the SoC specific details of this driver. | ||
| 596 | */ | ||
| 597 | static const struct of_device_id of_mvebu_mbus_ids[] = { | 591 | static const struct of_device_id of_mvebu_mbus_ids[] = { |
| 598 | { .compatible = "marvell,armada370-mbus", | 592 | { .compatible = "marvell,armada370-mbus", |
| 599 | .data = &armada_370_xp_mbus_data, }, | 593 | .data = &armada_370_xp_mbus_data, }, |
| @@ -734,11 +728,11 @@ int __init mvebu_mbus_init(const char *soc, phys_addr_t mbuswins_phys_base, | |||
| 734 | { | 728 | { |
| 735 | const struct of_device_id *of_id; | 729 | const struct of_device_id *of_id; |
| 736 | 730 | ||
| 737 | for (of_id = of_mvebu_mbus_ids; of_id->compatible; of_id++) | 731 | for (of_id = of_mvebu_mbus_ids; of_id->compatible[0]; of_id++) |
| 738 | if (!strcmp(of_id->compatible, soc)) | 732 | if (!strcmp(of_id->compatible, soc)) |
| 739 | break; | 733 | break; |
| 740 | 734 | ||
| 741 | if (!of_id->compatible) { | 735 | if (!of_id->compatible[0]) { |
| 742 | pr_err("could not find a matching SoC family\n"); | 736 | pr_err("could not find a matching SoC family\n"); |
| 743 | return -ENODEV; | 737 | return -ENODEV; |
| 744 | } | 738 | } |
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 7a10bc9a23e7..ace7309c4369 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile | |||
| @@ -35,6 +35,7 @@ obj-$(CONFIG_ARCH_TEGRA) += tegra/ | |||
| 35 | obj-$(CONFIG_PLAT_SAMSUNG) += samsung/ | 35 | obj-$(CONFIG_PLAT_SAMSUNG) += samsung/ |
| 36 | obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o | 36 | obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o |
| 37 | obj-$(CONFIG_COMMON_CLK_KEYSTONE) += keystone/ | 37 | obj-$(CONFIG_COMMON_CLK_KEYSTONE) += keystone/ |
| 38 | obj-$(CONFIG_COMMON_CLK_AT91) += at91/ | ||
| 38 | 39 | ||
| 39 | obj-$(CONFIG_X86) += x86/ | 40 | obj-$(CONFIG_X86) += x86/ |
| 40 | 41 | ||
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile new file mode 100644 index 000000000000..0e92b716f934 --- /dev/null +++ b/drivers/clk/at91/Makefile | |||
| @@ -0,0 +1,12 @@ | |||
| 1 | # | ||
| 2 | # Makefile for at91 specific clk | ||
| 3 | # | ||
| 4 | |||
| 5 | obj-y += pmc.o | ||
| 6 | obj-y += clk-main.o clk-pll.o clk-plldiv.o clk-master.o | ||
| 7 | obj-y += clk-system.o clk-peripheral.o | ||
| 8 | |||
| 9 | obj-$(CONFIG_AT91_PROGRAMMABLE_CLOCKS) += clk-programmable.o | ||
| 10 | obj-$(CONFIG_HAVE_AT91_UTMI) += clk-utmi.o | ||
| 11 | obj-$(CONFIG_HAVE_AT91_USB_CLK) += clk-usb.o | ||
| 12 | obj-$(CONFIG_HAVE_AT91_SMD) += clk-smd.o | ||
diff --git a/drivers/clk/at91/clk-main.c b/drivers/clk/at91/clk-main.c new file mode 100644 index 000000000000..8e9e8cc0412d --- /dev/null +++ b/drivers/clk/at91/clk-main.c | |||
| @@ -0,0 +1,187 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; either version 2 of the License, or | ||
| 7 | * (at your option) any later version. | ||
| 8 | * | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/clk-provider.h> | ||
| 12 | #include <linux/clkdev.h> | ||
| 13 | #include <linux/clk/at91_pmc.h> | ||
| 14 | #include <linux/delay.h> | ||
| 15 | #include <linux/of.h> | ||
| 16 | #include <linux/of_address.h> | ||
| 17 | #include <linux/of_irq.h> | ||
| 18 | #include <linux/io.h> | ||
| 19 | #include <linux/interrupt.h> | ||
| 20 | #include <linux/irq.h> | ||
| 21 | #include <linux/sched.h> | ||
| 22 | #include <linux/wait.h> | ||
| 23 | |||
| 24 | #include "pmc.h" | ||
| 25 | |||
| 26 | #define SLOW_CLOCK_FREQ 32768 | ||
| 27 | #define MAINF_DIV 16 | ||
| 28 | #define MAINFRDY_TIMEOUT (((MAINF_DIV + 1) * USEC_PER_SEC) / \ | ||
| 29 | SLOW_CLOCK_FREQ) | ||
| 30 | #define MAINF_LOOP_MIN_WAIT (USEC_PER_SEC / SLOW_CLOCK_FREQ) | ||
| 31 | #define MAINF_LOOP_MAX_WAIT MAINFRDY_TIMEOUT | ||
| 32 | |||
| 33 | struct clk_main { | ||
| 34 | struct clk_hw hw; | ||
| 35 | struct at91_pmc *pmc; | ||
| 36 | unsigned long rate; | ||
| 37 | unsigned int irq; | ||
| 38 | wait_queue_head_t wait; | ||
| 39 | }; | ||
| 40 | |||
| 41 | #define to_clk_main(hw) container_of(hw, struct clk_main, hw) | ||
| 42 | |||
| 43 | static irqreturn_t clk_main_irq_handler(int irq, void *dev_id) | ||
| 44 | { | ||
| 45 | struct clk_main *clkmain = (struct clk_main *)dev_id; | ||
| 46 | |||
| 47 | wake_up(&clkmain->wait); | ||
| 48 | disable_irq_nosync(clkmain->irq); | ||
| 49 | |||
| 50 | return IRQ_HANDLED; | ||
| 51 | } | ||
| 52 | |||
| 53 | static int clk_main_prepare(struct clk_hw *hw) | ||
| 54 | { | ||
| 55 | struct clk_main *clkmain = to_clk_main(hw); | ||
| 56 | struct at91_pmc *pmc = clkmain->pmc; | ||
| 57 | unsigned long halt_time, timeout; | ||
| 58 | u32 tmp; | ||
| 59 | |||
| 60 | while (!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCS)) { | ||
| 61 | enable_irq(clkmain->irq); | ||
| 62 | wait_event(clkmain->wait, | ||
| 63 | pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCS); | ||
| 64 | } | ||
| 65 | |||
| 66 | if (clkmain->rate) | ||
| 67 | return 0; | ||
| 68 | |||
| 69 | timeout = jiffies + usecs_to_jiffies(MAINFRDY_TIMEOUT); | ||
| 70 | do { | ||
| 71 | halt_time = jiffies; | ||
| 72 | tmp = pmc_read(pmc, AT91_CKGR_MCFR); | ||
| 73 | if (tmp & AT91_PMC_MAINRDY) | ||
| 74 | return 0; | ||
| 75 | usleep_range(MAINF_LOOP_MIN_WAIT, MAINF_LOOP_MAX_WAIT); | ||
| 76 | } while (time_before(halt_time, timeout)); | ||
| 77 | |||
| 78 | return 0; | ||
| 79 | } | ||
| 80 | |||
| 81 | static int clk_main_is_prepared(struct clk_hw *hw) | ||
| 82 | { | ||
| 83 | struct clk_main *clkmain = to_clk_main(hw); | ||
| 84 | |||
| 85 | return !!(pmc_read(clkmain->pmc, AT91_PMC_SR) & AT91_PMC_MOSCS); | ||
| 86 | } | ||
| 87 | |||
| 88 | static unsigned long clk_main_recalc_rate(struct clk_hw *hw, | ||
| 89 | unsigned long parent_rate) | ||
| 90 | { | ||
| 91 | u32 tmp; | ||
| 92 | struct clk_main *clkmain = to_clk_main(hw); | ||
| 93 | struct at91_pmc *pmc = clkmain->pmc; | ||
| 94 | |||
| 95 | if (clkmain->rate) | ||
| 96 | return clkmain->rate; | ||
| 97 | |||
| 98 | tmp = pmc_read(pmc, AT91_CKGR_MCFR) & AT91_PMC_MAINF; | ||
| 99 | clkmain->rate = (tmp * parent_rate) / MAINF_DIV; | ||
| 100 | |||
| 101 | return clkmain->rate; | ||
| 102 | } | ||
| 103 | |||
| 104 | static const struct clk_ops main_ops = { | ||
| 105 | .prepare = clk_main_prepare, | ||
| 106 | .is_prepared = clk_main_is_prepared, | ||
| 107 | .recalc_rate = clk_main_recalc_rate, | ||
| 108 | }; | ||
| 109 | |||
| 110 | static struct clk * __init | ||
| 111 | at91_clk_register_main(struct at91_pmc *pmc, | ||
| 112 | unsigned int irq, | ||
| 113 | const char *name, | ||
| 114 | const char *parent_name, | ||
| 115 | unsigned long rate) | ||
| 116 | { | ||
| 117 | int ret; | ||
| 118 | struct clk_main *clkmain; | ||
| 119 | struct clk *clk = NULL; | ||
| 120 | struct clk_init_data init; | ||
| 121 | |||
| 122 | if (!pmc || !irq || !name) | ||
| 123 | return ERR_PTR(-EINVAL); | ||
| 124 | |||
| 125 | if (!rate && !parent_name) | ||
| 126 | return ERR_PTR(-EINVAL); | ||
| 127 | |||
| 128 | clkmain = kzalloc(sizeof(*clkmain), GFP_KERNEL); | ||
| 129 | if (!clkmain) | ||
| 130 | return ERR_PTR(-ENOMEM); | ||
| 131 | |||
| 132 | init.name = name; | ||
| 133 | init.ops = &main_ops; | ||
| 134 | init.parent_names = parent_name ? &parent_name : NULL; | ||
| 135 | init.num_parents = parent_name ? 1 : 0; | ||
| 136 | init.flags = parent_name ? 0 : CLK_IS_ROOT; | ||
| 137 | |||
| 138 | clkmain->hw.init = &init; | ||
| 139 | clkmain->rate = rate; | ||
| 140 | clkmain->pmc = pmc; | ||
| 141 | clkmain->irq = irq; | ||
| 142 | init_waitqueue_head(&clkmain->wait); | ||
| 143 | irq_set_status_flags(clkmain->irq, IRQ_NOAUTOEN); | ||
| 144 | ret = request_irq(clkmain->irq, clk_main_irq_handler, | ||
| 145 | IRQF_TRIGGER_HIGH, "clk-main", clkmain); | ||
| 146 | if (ret) | ||
| 147 | return ERR_PTR(ret); | ||
| 148 | |||
| 149 | clk = clk_register(NULL, &clkmain->hw); | ||
| 150 | if (IS_ERR(clk)) { | ||
| 151 | free_irq(clkmain->irq, clkmain); | ||
| 152 | kfree(clkmain); | ||
| 153 | } | ||
| 154 | |||
| 155 | return clk; | ||
| 156 | } | ||
| 157 | |||
| 158 | |||
| 159 | |||
| 160 | static void __init | ||
| 161 | of_at91_clk_main_setup(struct device_node *np, struct at91_pmc *pmc) | ||
| 162 | { | ||
| 163 | struct clk *clk; | ||
| 164 | unsigned int irq; | ||
| 165 | const char *parent_name; | ||
| 166 | const char *name = np->name; | ||
| 167 | u32 rate = 0; | ||
| 168 | |||
| 169 | parent_name = of_clk_get_parent_name(np, 0); | ||
| 170 | of_property_read_string(np, "clock-output-names", &name); | ||
| 171 | of_property_read_u32(np, "clock-frequency", &rate); | ||
| 172 | irq = irq_of_parse_and_map(np, 0); | ||
| 173 | if (!irq) | ||
| 174 | return; | ||
| 175 | |||
| 176 | clk = at91_clk_register_main(pmc, irq, name, parent_name, rate); | ||
| 177 | if (IS_ERR(clk)) | ||
| 178 | return; | ||
| 179 | |||
| 180 | of_clk_add_provider(np, of_clk_src_simple_get, clk); | ||
| 181 | } | ||
| 182 | |||
| 183 | void __init of_at91rm9200_clk_main_setup(struct device_node *np, | ||
| 184 | struct at91_pmc *pmc) | ||
| 185 | { | ||
| 186 | of_at91_clk_main_setup(np, pmc); | ||
| 187 | } | ||
diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c new file mode 100644 index 000000000000..bd313f7816a8 --- /dev/null +++ b/drivers/clk/at91/clk-master.c | |||
| @@ -0,0 +1,270 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; either version 2 of the License, or | ||
| 7 | * (at your option) any later version. | ||
| 8 | * | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/clk-provider.h> | ||
| 12 | #include <linux/clkdev.h> | ||
| 13 | #include <linux/clk/at91_pmc.h> | ||
| 14 | #include <linux/of.h> | ||
| 15 | #include <linux/of_address.h> | ||
| 16 | #include <linux/of_irq.h> | ||
| 17 | #include <linux/io.h> | ||
| 18 | #include <linux/wait.h> | ||
| 19 | #include <linux/sched.h> | ||
| 20 | #include <linux/interrupt.h> | ||
| 21 | #include <linux/irq.h> | ||
| 22 | |||
| 23 | #include "pmc.h" | ||
| 24 | |||
| 25 | #define MASTER_SOURCE_MAX 4 | ||
| 26 | |||
| 27 | #define MASTER_PRES_MASK 0x7 | ||
| 28 | #define MASTER_PRES_MAX MASTER_PRES_MASK | ||
| 29 | #define MASTER_DIV_SHIFT 8 | ||
| 30 | #define MASTER_DIV_MASK 0x3 | ||
| 31 | |||
| 32 | struct clk_master_characteristics { | ||
| 33 | struct clk_range output; | ||
| 34 | u32 divisors[4]; | ||
| 35 | u8 have_div3_pres; | ||
| 36 | }; | ||
| 37 | |||
| 38 | struct clk_master_layout { | ||
| 39 | u32 mask; | ||
| 40 | u8 pres_shift; | ||
| 41 | }; | ||
| 42 | |||
| 43 | #define to_clk_master(hw) container_of(hw, struct clk_master, hw) | ||
| 44 | |||
| 45 | struct clk_master { | ||
| 46 | struct clk_hw hw; | ||
| 47 | struct at91_pmc *pmc; | ||
| 48 | unsigned int irq; | ||
| 49 | wait_queue_head_t wait; | ||
| 50 | const struct clk_master_layout *layout; | ||
| 51 | const struct clk_master_characteristics *characteristics; | ||
| 52 | }; | ||
| 53 | |||
| 54 | static irqreturn_t clk_master_irq_handler(int irq, void *dev_id) | ||
| 55 | { | ||
| 56 | struct clk_master *master = (struct clk_master *)dev_id; | ||
| 57 | |||
| 58 | wake_up(&master->wait); | ||
| 59 | disable_irq_nosync(master->irq); | ||
| 60 | |||
| 61 | return IRQ_HANDLED; | ||
| 62 | } | ||
| 63 | static int clk_master_prepare(struct clk_hw *hw) | ||
| 64 | { | ||
| 65 | struct clk_master *master = to_clk_master(hw); | ||
| 66 | struct at91_pmc *pmc = master->pmc; | ||
| 67 | |||
| 68 | while (!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MCKRDY)) { | ||
| 69 | enable_irq(master->irq); | ||
| 70 | wait_event(master->wait, | ||
| 71 | pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MCKRDY); | ||
| 72 | } | ||
| 73 | |||
| 74 | return 0; | ||
| 75 | } | ||
| 76 | |||
| 77 | static int clk_master_is_prepared(struct clk_hw *hw) | ||
| 78 | { | ||
| 79 | struct clk_master *master = to_clk_master(hw); | ||
| 80 | |||
| 81 | return !!(pmc_read(master->pmc, AT91_PMC_SR) & AT91_PMC_MCKRDY); | ||
| 82 | } | ||
| 83 | |||
| 84 | static unsigned long clk_master_recalc_rate(struct clk_hw *hw, | ||
| 85 | unsigned long parent_rate) | ||
| 86 | { | ||
| 87 | u8 pres; | ||
| 88 | u8 div; | ||
| 89 | unsigned long rate = parent_rate; | ||
| 90 | struct clk_master *master = to_clk_master(hw); | ||
| 91 | struct at91_pmc *pmc = master->pmc; | ||
| 92 | const struct clk_master_layout *layout = master->layout; | ||
| 93 | const struct clk_master_characteristics *characteristics = | ||
| 94 | master->characteristics; | ||
| 95 | u32 tmp; | ||
| 96 | |||
| 97 | pmc_lock(pmc); | ||
| 98 | tmp = pmc_read(pmc, AT91_PMC_MCKR) & layout->mask; | ||
| 99 | pmc_unlock(pmc); | ||
| 100 | |||
| 101 | pres = (tmp >> layout->pres_shift) & MASTER_PRES_MASK; | ||
| 102 | div = (tmp >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; | ||
| 103 | |||
| 104 | if (characteristics->have_div3_pres && pres == MASTER_PRES_MAX) | ||
| 105 | rate /= 3; | ||
| 106 | else | ||
| 107 | rate >>= pres; | ||
| 108 | |||
| 109 | rate /= characteristics->divisors[div]; | ||
| 110 | |||
| 111 | if (rate < characteristics->output.min) | ||
| 112 | pr_warn("master clk is underclocked"); | ||
| 113 | else if (rate > characteristics->output.max) | ||
| 114 | pr_warn("master clk is overclocked"); | ||
| 115 | |||
| 116 | return rate; | ||
| 117 | } | ||
| 118 | |||
| 119 | static u8 clk_master_get_parent(struct clk_hw *hw) | ||
| 120 | { | ||
| 121 | struct clk_master *master = to_clk_master(hw); | ||
| 122 | struct at91_pmc *pmc = master->pmc; | ||
| 123 | |||
| 124 | return pmc_read(pmc, AT91_PMC_MCKR) & AT91_PMC_CSS; | ||
| 125 | } | ||
| 126 | |||
| 127 | static const struct clk_ops master_ops = { | ||
| 128 | .prepare = clk_master_prepare, | ||
| 129 | .is_prepared = clk_master_is_prepared, | ||
| 130 | .recalc_rate = clk_master_recalc_rate, | ||
| 131 | .get_parent = clk_master_get_parent, | ||
| 132 | }; | ||
| 133 | |||
| 134 | static struct clk * __init | ||
| 135 | at91_clk_register_master(struct at91_pmc *pmc, unsigned int irq, | ||
| 136 | const char *name, int num_parents, | ||
| 137 | const char **parent_names, | ||
| 138 | const struct clk_master_layout *layout, | ||
| 139 | const struct clk_master_characteristics *characteristics) | ||
| 140 | { | ||
| 141 | int ret; | ||
| 142 | struct clk_master *master; | ||
| 143 | struct clk *clk = NULL; | ||
| 144 | struct clk_init_data init; | ||
| 145 | |||
| 146 | if (!pmc || !irq || !name || !num_parents || !parent_names) | ||
| 147 | return ERR_PTR(-EINVAL); | ||
| 148 | |||
| 149 | master = kzalloc(sizeof(*master), GFP_KERNEL); | ||
| 150 | if (!master) | ||
| 151 | return ERR_PTR(-ENOMEM); | ||
| 152 | |||
| 153 | init.name = name; | ||
| 154 | init.ops = &master_ops; | ||
| 155 | init.parent_names = parent_names; | ||
| 156 | init.num_parents = num_parents; | ||
| 157 | init.flags = 0; | ||
| 158 | |||
| 159 | master->hw.init = &init; | ||
| 160 | master->layout = layout; | ||
| 161 | master->characteristics = characteristics; | ||
| 162 | master->pmc = pmc; | ||
| 163 | master->irq = irq; | ||
| 164 | init_waitqueue_head(&master->wait); | ||
| 165 | irq_set_status_flags(master->irq, IRQ_NOAUTOEN); | ||
| 166 | ret = request_irq(master->irq, clk_master_irq_handler, | ||
| 167 | IRQF_TRIGGER_HIGH, "clk-master", master); | ||
| 168 | if (ret) | ||
| 169 | return ERR_PTR(ret); | ||
| 170 | |||
| 171 | clk = clk_register(NULL, &master->hw); | ||
| 172 | if (IS_ERR(clk)) | ||
| 173 | kfree(master); | ||
| 174 | |||
| 175 | return clk; | ||
| 176 | } | ||
| 177 | |||
| 178 | |||
| 179 | static const struct clk_master_layout at91rm9200_master_layout = { | ||
| 180 | .mask = 0x31F, | ||
| 181 | .pres_shift = 2, | ||
| 182 | }; | ||
| 183 | |||
| 184 | static const struct clk_master_layout at91sam9x5_master_layout = { | ||
| 185 | .mask = 0x373, | ||
| 186 | .pres_shift = 4, | ||
| 187 | }; | ||
| 188 | |||
| 189 | |||
| 190 | static struct clk_master_characteristics * __init | ||
| 191 | of_at91_clk_master_get_characteristics(struct device_node *np) | ||
| 192 | { | ||
| 193 | struct clk_master_characteristics *characteristics; | ||
| 194 | |||
| 195 | characteristics = kzalloc(sizeof(*characteristics), GFP_KERNEL); | ||
| 196 | if (!characteristics) | ||
| 197 | return NULL; | ||
| 198 | |||
| 199 | if (of_at91_get_clk_range(np, "atmel,clk-output-range", &characteristics->output)) | ||
| 200 | goto out_free_characteristics; | ||
| 201 | |||
| 202 | of_property_read_u32_array(np, "atmel,clk-divisors", | ||
| 203 | characteristics->divisors, 4); | ||
| 204 | |||
| 205 | characteristics->have_div3_pres = | ||
| 206 | of_property_read_bool(np, "atmel,master-clk-have-div3-pres"); | ||
| 207 | |||
| 208 | return characteristics; | ||
| 209 | |||
| 210 | out_free_characteristics: | ||
| 211 | kfree(characteristics); | ||
| 212 | return NULL; | ||
| 213 | } | ||
| 214 | |||
| 215 | static void __init | ||
| 216 | of_at91_clk_master_setup(struct device_node *np, struct at91_pmc *pmc, | ||
| 217 | const struct clk_master_layout *layout) | ||
| 218 | { | ||
| 219 | struct clk *clk; | ||
| 220 | int num_parents; | ||
| 221 | int i; | ||
| 222 | unsigned int irq; | ||
| 223 | const char *parent_names[MASTER_SOURCE_MAX]; | ||
| 224 | const char *name = np->name; | ||
| 225 | struct clk_master_characteristics *characteristics; | ||
| 226 | |||
| 227 | num_parents = of_count_phandle_with_args(np, "clocks", "#clock-cells"); | ||
| 228 | if (num_parents <= 0 || num_parents > MASTER_SOURCE_MAX) | ||
| 229 | return; | ||
| 230 | |||
| 231 | for (i = 0; i < num_parents; ++i) { | ||
| 232 | parent_names[i] = of_clk_get_parent_name(np, i); | ||
| 233 | if (!parent_names[i]) | ||
| 234 | return; | ||
| 235 | } | ||
| 236 | |||
| 237 | of_property_read_string(np, "clock-output-names", &name); | ||
| 238 | |||
| 239 | characteristics = of_at91_clk_master_get_characteristics(np); | ||
| 240 | if (!characteristics) | ||
| 241 | return; | ||
| 242 | |||
| 243 | irq = irq_of_parse_and_map(np, 0); | ||
| 244 | if (!irq) | ||
| 245 | return; | ||
| 246 | |||
| 247 | clk = at91_clk_register_master(pmc, irq, name, num_parents, | ||
| 248 | parent_names, layout, | ||
| 249 | characteristics); | ||
| 250 | if (IS_ERR(clk)) | ||
| 251 | goto out_free_characteristics; | ||
| 252 | |||
| 253 | of_clk_add_provider(np, of_clk_src_simple_get, clk); | ||
| 254 | return; | ||
| 255 | |||
| 256 | out_free_characteristics: | ||
| 257 | kfree(characteristics); | ||
| 258 | } | ||
| 259 | |||
| 260 | void __init of_at91rm9200_clk_master_setup(struct device_node *np, | ||
| 261 | struct at91_pmc *pmc) | ||
| 262 | { | ||
| 263 | of_at91_clk_master_setup(np, pmc, &at91rm9200_master_layout); | ||
| 264 | } | ||
| 265 | |||
| 266 | void __init of_at91sam9x5_clk_master_setup(struct device_node *np, | ||
| 267 | struct at91_pmc *pmc) | ||
| 268 | { | ||
| 269 | of_at91_clk_master_setup(np, pmc, &at91sam9x5_master_layout); | ||
| 270 | } | ||
diff --git a/drivers/clk/at91/clk-peripheral.c b/drivers/clk/at91/clk-peripheral.c new file mode 100644 index 000000000000..597fed423d7d --- /dev/null +++ b/drivers/clk/at91/clk-peripheral.c | |||
| @@ -0,0 +1,410 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; either version 2 of the License, or | ||
| 7 | * (at your option) any later version. | ||
| 8 | * | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/clk-provider.h> | ||
| 12 | #include <linux/clkdev.h> | ||
| 13 | #include <linux/clk/at91_pmc.h> | ||
| 14 | #include <linux/of.h> | ||
| 15 | #include <linux/of_address.h> | ||
| 16 | #include <linux/io.h> | ||
| 17 | |||
| 18 | #include "pmc.h" | ||
| 19 | |||
| 20 | #define PERIPHERAL_MAX 64 | ||
| 21 | |||
| 22 | #define PERIPHERAL_AT91RM9200 0 | ||
| 23 | #define PERIPHERAL_AT91SAM9X5 1 | ||
| 24 | |||
| 25 | #define PERIPHERAL_ID_MIN 2 | ||
| 26 | #define PERIPHERAL_ID_MAX 31 | ||
| 27 | #define PERIPHERAL_MASK(id) (1 << ((id) & PERIPHERAL_ID_MAX)) | ||
| 28 | |||
| 29 | #define PERIPHERAL_RSHIFT_MASK 0x3 | ||
| 30 | #define PERIPHERAL_RSHIFT(val) (((val) >> 16) & PERIPHERAL_RSHIFT_MASK) | ||
| 31 | |||
| 32 | #define PERIPHERAL_MAX_SHIFT 4 | ||
| 33 | |||
| 34 | struct clk_peripheral { | ||
| 35 | struct clk_hw hw; | ||
| 36 | struct at91_pmc *pmc; | ||
| 37 | u32 id; | ||
| 38 | }; | ||
| 39 | |||
| 40 | #define to_clk_peripheral(hw) container_of(hw, struct clk_peripheral, hw) | ||
| 41 | |||
| 42 | struct clk_sam9x5_peripheral { | ||
| 43 | struct clk_hw hw; | ||
| 44 | struct at91_pmc *pmc; | ||
| 45 | struct clk_range range; | ||
| 46 | u32 id; | ||
| 47 | u32 div; | ||
| 48 | bool auto_div; | ||
| 49 | }; | ||
| 50 | |||
| 51 | #define to_clk_sam9x5_peripheral(hw) \ | ||
| 52 | container_of(hw, struct clk_sam9x5_peripheral, hw) | ||
| 53 | |||
| 54 | static int clk_peripheral_enable(struct clk_hw *hw) | ||
| 55 | { | ||
| 56 | struct clk_peripheral *periph = to_clk_peripheral(hw); | ||
| 57 | struct at91_pmc *pmc = periph->pmc; | ||
| 58 | int offset = AT91_PMC_PCER; | ||
| 59 | u32 id = periph->id; | ||
| 60 | |||
| 61 | if (id < PERIPHERAL_ID_MIN) | ||
| 62 | return 0; | ||
| 63 | if (id > PERIPHERAL_ID_MAX) | ||
| 64 | offset = AT91_PMC_PCER1; | ||
| 65 | pmc_write(pmc, offset, PERIPHERAL_MASK(id)); | ||
| 66 | return 0; | ||
| 67 | } | ||
| 68 | |||
| 69 | static void clk_peripheral_disable(struct clk_hw *hw) | ||
| 70 | { | ||
| 71 | struct clk_peripheral *periph = to_clk_peripheral(hw); | ||
| 72 | struct at91_pmc *pmc = periph->pmc; | ||
| 73 | int offset = AT91_PMC_PCDR; | ||
| 74 | u32 id = periph->id; | ||
| 75 | |||
| 76 | if (id < PERIPHERAL_ID_MIN) | ||
| 77 | return; | ||
| 78 | if (id > PERIPHERAL_ID_MAX) | ||
| 79 | offset = AT91_PMC_PCDR1; | ||
| 80 | pmc_write(pmc, offset, PERIPHERAL_MASK(id)); | ||
| 81 | } | ||
| 82 | |||
| 83 | static int clk_peripheral_is_enabled(struct clk_hw *hw) | ||
| 84 | { | ||
| 85 | struct clk_peripheral *periph = to_clk_peripheral(hw); | ||
| 86 | struct at91_pmc *pmc = periph->pmc; | ||
| 87 | int offset = AT91_PMC_PCSR; | ||
| 88 | u32 id = periph->id; | ||
| 89 | |||
| 90 | if (id < PERIPHERAL_ID_MIN) | ||
| 91 | return 1; | ||
| 92 | if (id > PERIPHERAL_ID_MAX) | ||
| 93 | offset = AT91_PMC_PCSR1; | ||
| 94 | return !!(pmc_read(pmc, offset) & PERIPHERAL_MASK(id)); | ||
| 95 | } | ||
| 96 | |||
| 97 | static const struct clk_ops peripheral_ops = { | ||
| 98 | .enable = clk_peripheral_enable, | ||
| 99 | .disable = clk_peripheral_disable, | ||
| 100 | .is_enabled = clk_peripheral_is_enabled, | ||
| 101 | }; | ||
| 102 | |||
| 103 | static struct clk * __init | ||
| 104 | at91_clk_register_peripheral(struct at91_pmc *pmc, const char *name, | ||
| 105 | const char *parent_name, u32 id) | ||
| 106 | { | ||
| 107 | struct clk_peripheral *periph; | ||
| 108 | struct clk *clk = NULL; | ||
| 109 | struct clk_init_data init; | ||
| 110 | |||
| 111 | if (!pmc || !name || !parent_name || id > PERIPHERAL_ID_MAX) | ||
| 112 | return ERR_PTR(-EINVAL); | ||
| 113 | |||
| 114 | periph = kzalloc(sizeof(*periph), GFP_KERNEL); | ||
| 115 | if (!periph) | ||
| 116 | return ERR_PTR(-ENOMEM); | ||
| 117 | |||
| 118 | init.name = name; | ||
| 119 | init.ops = &peripheral_ops; | ||
| 120 | init.parent_names = (parent_name ? &parent_name : NULL); | ||
| 121 | init.num_parents = (parent_name ? 1 : 0); | ||
| 122 | init.flags = 0; | ||
| 123 | |||
| 124 | periph->id = id; | ||
| 125 | periph->hw.init = &init; | ||
| 126 | periph->pmc = pmc; | ||
| 127 | |||
| 128 | clk = clk_register(NULL, &periph->hw); | ||
| 129 | if (IS_ERR(clk)) | ||
| 130 | kfree(periph); | ||
| 131 | |||
| 132 | return clk; | ||
| 133 | } | ||
| 134 | |||
| 135 | static void clk_sam9x5_peripheral_autodiv(struct clk_sam9x5_peripheral *periph) | ||
| 136 | { | ||
| 137 | struct clk *parent; | ||
| 138 | unsigned long parent_rate; | ||
| 139 | int shift = 0; | ||
| 140 | |||
| 141 | if (!periph->auto_div) | ||
| 142 | return; | ||
| 143 | |||
| 144 | if (periph->range.max) { | ||
| 145 | parent = clk_get_parent_by_index(periph->hw.clk, 0); | ||
| 146 | parent_rate = __clk_get_rate(parent); | ||
| 147 | if (!parent_rate) | ||
| 148 | return; | ||
| 149 | |||
| 150 | for (; shift < PERIPHERAL_MAX_SHIFT; shift++) { | ||
| 151 | if (parent_rate >> shift <= periph->range.max) | ||
| 152 | break; | ||
| 153 | } | ||
| 154 | } | ||
| 155 | |||
| 156 | periph->auto_div = false; | ||
| 157 | periph->div = shift; | ||
| 158 | } | ||
| 159 | |||
| 160 | static int clk_sam9x5_peripheral_enable(struct clk_hw *hw) | ||
| 161 | { | ||
| 162 | struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw); | ||
| 163 | struct at91_pmc *pmc = periph->pmc; | ||
| 164 | |||
| 165 | if (periph->id < PERIPHERAL_ID_MIN) | ||
| 166 | return 0; | ||
| 167 | |||
| 168 | pmc_write(pmc, AT91_PMC_PCR, (periph->id & AT91_PMC_PCR_PID) | | ||
| 169 | AT91_PMC_PCR_CMD | | ||
| 170 | AT91_PMC_PCR_DIV(periph->div) | | ||
| 171 | AT91_PMC_PCR_EN); | ||
| 172 | return 0; | ||
| 173 | } | ||
| 174 | |||
| 175 | static void clk_sam9x5_peripheral_disable(struct clk_hw *hw) | ||
| 176 | { | ||
| 177 | struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw); | ||
| 178 | struct at91_pmc *pmc = periph->pmc; | ||
| 179 | |||
| 180 | if (periph->id < PERIPHERAL_ID_MIN) | ||
| 181 | return; | ||
| 182 | |||
| 183 | pmc_write(pmc, AT91_PMC_PCR, (periph->id & AT91_PMC_PCR_PID) | | ||
| 184 | AT91_PMC_PCR_CMD); | ||
| 185 | } | ||
| 186 | |||
| 187 | static int clk_sam9x5_peripheral_is_enabled(struct clk_hw *hw) | ||
| 188 | { | ||
| 189 | struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw); | ||
| 190 | struct at91_pmc *pmc = periph->pmc; | ||
| 191 | int ret; | ||
| 192 | |||
| 193 | if (periph->id < PERIPHERAL_ID_MIN) | ||
| 194 | return 1; | ||
| 195 | |||
| 196 | pmc_lock(pmc); | ||
| 197 | pmc_write(pmc, AT91_PMC_PCR, (periph->id & AT91_PMC_PCR_PID)); | ||
| 198 | ret = !!(pmc_read(pmc, AT91_PMC_PCR) & AT91_PMC_PCR_EN); | ||
| 199 | pmc_unlock(pmc); | ||
| 200 | |||
| 201 | return ret; | ||
| 202 | } | ||
| 203 | |||
| 204 | static unsigned long | ||
| 205 | clk_sam9x5_peripheral_recalc_rate(struct clk_hw *hw, | ||
| 206 | unsigned long parent_rate) | ||
| 207 | { | ||
| 208 | struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw); | ||
| 209 | struct at91_pmc *pmc = periph->pmc; | ||
| 210 | u32 tmp; | ||
| 211 | |||
| 212 | if (periph->id < PERIPHERAL_ID_MIN) | ||
| 213 | return parent_rate; | ||
| 214 | |||
| 215 | pmc_lock(pmc); | ||
| 216 | pmc_write(pmc, AT91_PMC_PCR, (periph->id & AT91_PMC_PCR_PID)); | ||
| 217 | tmp = pmc_read(pmc, AT91_PMC_PCR); | ||
| 218 | pmc_unlock(pmc); | ||
| 219 | |||
| 220 | if (tmp & AT91_PMC_PCR_EN) { | ||
| 221 | periph->div = PERIPHERAL_RSHIFT(tmp); | ||
| 222 | periph->auto_div = false; | ||
| 223 | } else { | ||
| 224 | clk_sam9x5_peripheral_autodiv(periph); | ||
| 225 | } | ||
| 226 | |||
| 227 | return parent_rate >> periph->div; | ||
| 228 | } | ||
| 229 | |||
| 230 | static long clk_sam9x5_peripheral_round_rate(struct clk_hw *hw, | ||
| 231 | unsigned long rate, | ||
| 232 | unsigned long *parent_rate) | ||
| 233 | { | ||
| 234 | int shift = 0; | ||
| 235 | unsigned long best_rate; | ||
| 236 | unsigned long best_diff; | ||
| 237 | unsigned long cur_rate = *parent_rate; | ||
| 238 | unsigned long cur_diff; | ||
| 239 | struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw); | ||
| 240 | |||
| 241 | if (periph->id < PERIPHERAL_ID_MIN || !periph->range.max) | ||
| 242 | return *parent_rate; | ||
| 243 | |||
| 244 | if (periph->range.max) { | ||
| 245 | for (; shift < PERIPHERAL_MAX_SHIFT; shift++) { | ||
| 246 | cur_rate = *parent_rate >> shift; | ||
| 247 | if (cur_rate <= periph->range.max) | ||
| 248 | break; | ||
| 249 | } | ||
| 250 | } | ||
| 251 | |||
| 252 | if (rate >= cur_rate) | ||
| 253 | return cur_rate; | ||
| 254 | |||
| 255 | best_diff = cur_rate - rate; | ||
| 256 | best_rate = cur_rate; | ||
| 257 | for (; shift < PERIPHERAL_MAX_SHIFT; shift++) { | ||
| 258 | cur_rate = *parent_rate >> shift; | ||
| 259 | if (cur_rate < rate) | ||
| 260 | cur_diff = rate - cur_rate; | ||
| 261 | else | ||
| 262 | cur_diff = cur_rate - rate; | ||
| 263 | |||
| 264 | if (cur_diff < best_diff) { | ||
| 265 | best_diff = cur_diff; | ||
| 266 | best_rate = cur_rate; | ||
| 267 | } | ||
| 268 | |||
| 269 | if (!best_diff || cur_rate < rate) | ||
| 270 | break; | ||
| 271 | } | ||
| 272 | |||
| 273 | return best_rate; | ||
| 274 | } | ||
| 275 | |||
| 276 | static int clk_sam9x5_peripheral_set_rate(struct clk_hw *hw, | ||
| 277 | unsigned long rate, | ||
| 278 | unsigned long parent_rate) | ||
| 279 | { | ||
| 280 | int shift; | ||
| 281 | struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw); | ||
| 282 | if (periph->id < PERIPHERAL_ID_MIN || !periph->range.max) { | ||
| 283 | if (parent_rate == rate) | ||
| 284 | return 0; | ||
| 285 | else | ||
| 286 | return -EINVAL; | ||
| 287 | } | ||
| 288 | |||
| 289 | if (periph->range.max && rate > periph->range.max) | ||
| 290 | return -EINVAL; | ||
| 291 | |||
| 292 | for (shift = 0; shift < PERIPHERAL_MAX_SHIFT; shift++) { | ||
| 293 | if (parent_rate >> shift == rate) { | ||
| 294 | periph->auto_div = false; | ||
| 295 | periph->div = shift; | ||
| 296 | return 0; | ||
| 297 | } | ||
| 298 | } | ||
| 299 | |||
| 300 | return -EINVAL; | ||
| 301 | } | ||
| 302 | |||
| 303 | static const struct clk_ops sam9x5_peripheral_ops = { | ||
| 304 | .enable = clk_sam9x5_peripheral_enable, | ||
| 305 | .disable = clk_sam9x5_peripheral_disable, | ||
| 306 | .is_enabled = clk_sam9x5_peripheral_is_enabled, | ||
| 307 | .recalc_rate = clk_sam9x5_peripheral_recalc_rate, | ||
| 308 | .round_rate = clk_sam9x5_peripheral_round_rate, | ||
| 309 | .set_rate = clk_sam9x5_peripheral_set_rate, | ||
| 310 | }; | ||
| 311 | |||
| 312 | static struct clk * __init | ||
| 313 | at91_clk_register_sam9x5_peripheral(struct at91_pmc *pmc, const char *name, | ||
| 314 | const char *parent_name, u32 id, | ||
| 315 | const struct clk_range *range) | ||
| 316 | { | ||
| 317 | struct clk_sam9x5_peripheral *periph; | ||
| 318 | struct clk *clk = NULL; | ||
| 319 | struct clk_init_data init; | ||
| 320 | |||
| 321 | if (!pmc || !name || !parent_name) | ||
| 322 | return ERR_PTR(-EINVAL); | ||
| 323 | |||
| 324 | periph = kzalloc(sizeof(*periph), GFP_KERNEL); | ||
| 325 | if (!periph) | ||
| 326 | return ERR_PTR(-ENOMEM); | ||
| 327 | |||
| 328 | init.name = name; | ||
| 329 | init.ops = &sam9x5_peripheral_ops; | ||
| 330 | init.parent_names = (parent_name ? &parent_name : NULL); | ||
| 331 | init.num_parents = (parent_name ? 1 : 0); | ||
| 332 | init.flags = 0; | ||
| 333 | |||
| 334 | periph->id = id; | ||
| 335 | periph->hw.init = &init; | ||
| 336 | periph->div = 0; | ||
| 337 | periph->pmc = pmc; | ||
| 338 | periph->auto_div = true; | ||
| 339 | periph->range = *range; | ||
| 340 | |||
| 341 | clk = clk_register(NULL, &periph->hw); | ||
| 342 | if (IS_ERR(clk)) | ||
| 343 | kfree(periph); | ||
| 344 | else | ||
| 345 | clk_sam9x5_peripheral_autodiv(periph); | ||
| 346 | |||
| 347 | return clk; | ||
| 348 | } | ||
| 349 | |||
| 350 | static void __init | ||
| 351 | of_at91_clk_periph_setup(struct device_node *np, struct at91_pmc *pmc, u8 type) | ||
| 352 | { | ||
| 353 | int num; | ||
| 354 | u32 id; | ||
| 355 | struct clk *clk; | ||
| 356 | const char *parent_name; | ||
| 357 | const char *name; | ||
| 358 | struct device_node *periphclknp; | ||
| 359 | |||
| 360 | parent_name = of_clk_get_parent_name(np, 0); | ||
| 361 | if (!parent_name) | ||
| 362 | return; | ||
| 363 | |||
| 364 | num = of_get_child_count(np); | ||
| 365 | if (!num || num > PERIPHERAL_MAX) | ||
| 366 | return; | ||
| 367 | |||
| 368 | for_each_child_of_node(np, periphclknp) { | ||
| 369 | if (of_property_read_u32(periphclknp, "reg", &id)) | ||
| 370 | continue; | ||
| 371 | |||
| 372 | if (id >= PERIPHERAL_MAX) | ||
| 373 | continue; | ||
| 374 | |||
| 375 | if (of_property_read_string(np, "clock-output-names", &name)) | ||
| 376 | name = periphclknp->name; | ||
| 377 | |||
| 378 | if (type == PERIPHERAL_AT91RM9200) { | ||
| 379 | clk = at91_clk_register_peripheral(pmc, name, | ||
| 380 | parent_name, id); | ||
| 381 | } else { | ||
| 382 | struct clk_range range = CLK_RANGE(0, 0); | ||
| 383 | |||
| 384 | of_at91_get_clk_range(periphclknp, | ||
| 385 | "atmel,clk-output-range", | ||
| 386 | &range); | ||
| 387 | |||
| 388 | clk = at91_clk_register_sam9x5_peripheral(pmc, name, | ||
| 389 | parent_name, | ||
| 390 | id, &range); | ||
| 391 | } | ||
| 392 | |||
| 393 | if (IS_ERR(clk)) | ||
| 394 | continue; | ||
| 395 | |||
| 396 | of_clk_add_provider(periphclknp, of_clk_src_simple_get, clk); | ||
| 397 | } | ||
| 398 | } | ||
| 399 | |||
| 400 | void __init of_at91rm9200_clk_periph_setup(struct device_node *np, | ||
| 401 | struct at91_pmc *pmc) | ||
| 402 | { | ||
| 403 | of_at91_clk_periph_setup(np, pmc, PERIPHERAL_AT91RM9200); | ||
| 404 | } | ||
| 405 | |||
| 406 | void __init of_at91sam9x5_clk_periph_setup(struct device_node *np, | ||
| 407 | struct at91_pmc *pmc) | ||
| 408 | { | ||
| 409 | of_at91_clk_periph_setup(np, pmc, PERIPHERAL_AT91SAM9X5); | ||
| 410 | } | ||
diff --git a/drivers/clk/at91/clk-pll.c b/drivers/clk/at91/clk-pll.c new file mode 100644 index 000000000000..cf6ed023504c --- /dev/null +++ b/drivers/clk/at91/clk-pll.c | |||
| @@ -0,0 +1,531 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; either version 2 of the License, or | ||
| 7 | * (at your option) any later version. | ||
| 8 | * | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/clk-provider.h> | ||
| 12 | #include <linux/clkdev.h> | ||
| 13 | #include <linux/clk/at91_pmc.h> | ||
| 14 | #include <linux/of.h> | ||
| 15 | #include <linux/of_address.h> | ||
| 16 | #include <linux/of_irq.h> | ||
| 17 | #include <linux/io.h> | ||
| 18 | #include <linux/wait.h> | ||
| 19 | #include <linux/sched.h> | ||
| 20 | #include <linux/interrupt.h> | ||
| 21 | #include <linux/irq.h> | ||
| 22 | |||
| 23 | #include "pmc.h" | ||
| 24 | |||
| 25 | #define PLL_STATUS_MASK(id) (1 << (1 + (id))) | ||
| 26 | #define PLL_REG(id) (AT91_CKGR_PLLAR + ((id) * 4)) | ||
| 27 | #define PLL_DIV_MASK 0xff | ||
| 28 | #define PLL_DIV_MAX PLL_DIV_MASK | ||
| 29 | #define PLL_DIV(reg) ((reg) & PLL_DIV_MASK) | ||
| 30 | #define PLL_MUL(reg, layout) (((reg) >> (layout)->mul_shift) & \ | ||
| 31 | (layout)->mul_mask) | ||
| 32 | #define PLL_ICPR_SHIFT(id) ((id) * 16) | ||
| 33 | #define PLL_ICPR_MASK(id) (0xffff << PLL_ICPR_SHIFT(id)) | ||
| 34 | #define PLL_MAX_COUNT 0x3ff | ||
| 35 | #define PLL_COUNT_SHIFT 8 | ||
| 36 | #define PLL_OUT_SHIFT 14 | ||
| 37 | #define PLL_MAX_ID 1 | ||
| 38 | |||
| 39 | struct clk_pll_characteristics { | ||
| 40 | struct clk_range input; | ||
| 41 | int num_output; | ||
| 42 | struct clk_range *output; | ||
| 43 | u16 *icpll; | ||
| 44 | u8 *out; | ||
| 45 | }; | ||
| 46 | |||
| 47 | struct clk_pll_layout { | ||
| 48 | u32 pllr_mask; | ||
| 49 | u16 mul_mask; | ||
| 50 | u8 mul_shift; | ||
| 51 | }; | ||
| 52 | |||
| 53 | #define to_clk_pll(hw) container_of(hw, struct clk_pll, hw) | ||
| 54 | |||
| 55 | struct clk_pll { | ||
| 56 | struct clk_hw hw; | ||
| 57 | struct at91_pmc *pmc; | ||
| 58 | unsigned int irq; | ||
| 59 | wait_queue_head_t wait; | ||
| 60 | u8 id; | ||
| 61 | u8 div; | ||
| 62 | u8 range; | ||
| 63 | u16 mul; | ||
| 64 | const struct clk_pll_layout *layout; | ||
| 65 | const struct clk_pll_characteristics *characteristics; | ||
| 66 | }; | ||
| 67 | |||
| 68 | static irqreturn_t clk_pll_irq_handler(int irq, void *dev_id) | ||
| 69 | { | ||
| 70 | struct clk_pll *pll = (struct clk_pll *)dev_id; | ||
| 71 | |||
| 72 | wake_up(&pll->wait); | ||
| 73 | disable_irq_nosync(pll->irq); | ||
| 74 | |||
| 75 | return IRQ_HANDLED; | ||
| 76 | } | ||
| 77 | |||
| 78 | static int clk_pll_prepare(struct clk_hw *hw) | ||
| 79 | { | ||
| 80 | struct clk_pll *pll = to_clk_pll(hw); | ||
| 81 | struct at91_pmc *pmc = pll->pmc; | ||
| 82 | const struct clk_pll_layout *layout = pll->layout; | ||
| 83 | const struct clk_pll_characteristics *characteristics = | ||
| 84 | pll->characteristics; | ||
| 85 | u8 id = pll->id; | ||
| 86 | u32 mask = PLL_STATUS_MASK(id); | ||
| 87 | int offset = PLL_REG(id); | ||
| 88 | u8 out = 0; | ||
| 89 | u32 pllr, icpr; | ||
| 90 | u8 div; | ||
| 91 | u16 mul; | ||
| 92 | |||
| 93 | pllr = pmc_read(pmc, offset); | ||
| 94 | div = PLL_DIV(pllr); | ||
| 95 | mul = PLL_MUL(pllr, layout); | ||
| 96 | |||
| 97 | if ((pmc_read(pmc, AT91_PMC_SR) & mask) && | ||
| 98 | (div == pll->div && mul == pll->mul)) | ||
| 99 | return 0; | ||
| 100 | |||
| 101 | if (characteristics->out) | ||
| 102 | out = characteristics->out[pll->range]; | ||
| 103 | if (characteristics->icpll) { | ||
| 104 | icpr = pmc_read(pmc, AT91_PMC_PLLICPR) & ~PLL_ICPR_MASK(id); | ||
| 105 | icpr |= (characteristics->icpll[pll->range] << | ||
| 106 | PLL_ICPR_SHIFT(id)); | ||
| 107 | pmc_write(pmc, AT91_PMC_PLLICPR, icpr); | ||
| 108 | } | ||
| 109 | |||
| 110 | pllr &= ~layout->pllr_mask; | ||
| 111 | pllr |= layout->pllr_mask & | ||
| 112 | (pll->div | (PLL_MAX_COUNT << PLL_COUNT_SHIFT) | | ||
| 113 | (out << PLL_OUT_SHIFT) | | ||
| 114 | ((pll->mul & layout->mul_mask) << layout->mul_shift)); | ||
| 115 | pmc_write(pmc, offset, pllr); | ||
| 116 | |||
| 117 | while (!(pmc_read(pmc, AT91_PMC_SR) & mask)) { | ||
| 118 | enable_irq(pll->irq); | ||
| 119 | wait_event(pll->wait, | ||
| 120 | pmc_read(pmc, AT91_PMC_SR) & mask); | ||
| 121 | } | ||
| 122 | |||
| 123 | return 0; | ||
| 124 | } | ||
| 125 | |||
| 126 | static int clk_pll_is_prepared(struct clk_hw *hw) | ||
| 127 | { | ||
| 128 | struct clk_pll *pll = to_clk_pll(hw); | ||
| 129 | struct at91_pmc *pmc = pll->pmc; | ||
| 130 | |||
| 131 | return !!(pmc_read(pmc, AT91_PMC_SR) & | ||
| 132 | PLL_STATUS_MASK(pll->id)); | ||
| 133 | } | ||
| 134 | |||
| 135 | static void clk_pll_unprepare(struct clk_hw *hw) | ||
| 136 | { | ||
| 137 | struct clk_pll *pll = to_clk_pll(hw); | ||
| 138 | struct at91_pmc *pmc = pll->pmc; | ||
| 139 | const struct clk_pll_layout *layout = pll->layout; | ||
| 140 | int offset = PLL_REG(pll->id); | ||
| 141 | u32 tmp = pmc_read(pmc, offset) & ~(layout->pllr_mask); | ||
| 142 | |||
| 143 | pmc_write(pmc, offset, tmp); | ||
| 144 | } | ||
| 145 | |||
| 146 | static unsigned long clk_pll_recalc_rate(struct clk_hw *hw, | ||
| 147 | unsigned long parent_rate) | ||
| 148 | { | ||
| 149 | struct clk_pll *pll = to_clk_pll(hw); | ||
| 150 | const struct clk_pll_layout *layout = pll->layout; | ||
| 151 | struct at91_pmc *pmc = pll->pmc; | ||
| 152 | int offset = PLL_REG(pll->id); | ||
| 153 | u32 tmp = pmc_read(pmc, offset) & layout->pllr_mask; | ||
| 154 | u8 div = PLL_DIV(tmp); | ||
| 155 | u16 mul = PLL_MUL(tmp, layout); | ||
| 156 | if (!div || !mul) | ||
| 157 | return 0; | ||
| 158 | |||
| 159 | return (parent_rate * (mul + 1)) / div; | ||
| 160 | } | ||
| 161 | |||
| 162 | static long clk_pll_get_best_div_mul(struct clk_pll *pll, unsigned long rate, | ||
| 163 | unsigned long parent_rate, | ||
| 164 | u32 *div, u32 *mul, | ||
| 165 | u32 *index) { | ||
| 166 | unsigned long maxrate; | ||
| 167 | unsigned long minrate; | ||
| 168 | unsigned long divrate; | ||
| 169 | unsigned long bestdiv = 1; | ||
| 170 | unsigned long bestmul; | ||
| 171 | unsigned long tmpdiv; | ||
| 172 | unsigned long roundup; | ||
| 173 | unsigned long rounddown; | ||
| 174 | unsigned long remainder; | ||
| 175 | unsigned long bestremainder; | ||
| 176 | unsigned long maxmul; | ||
| 177 | unsigned long maxdiv; | ||
| 178 | unsigned long mindiv; | ||
| 179 | int i = 0; | ||
| 180 | const struct clk_pll_layout *layout = pll->layout; | ||
| 181 | const struct clk_pll_characteristics *characteristics = | ||
| 182 | pll->characteristics; | ||
| 183 | |||
| 184 | /* Minimum divider = 1 */ | ||
| 185 | /* Maximum multiplier = max_mul */ | ||
| 186 | maxmul = layout->mul_mask + 1; | ||
| 187 | maxrate = (parent_rate * maxmul) / 1; | ||
| 188 | |||
| 189 | /* Maximum divider = max_div */ | ||
| 190 | /* Minimum multiplier = 2 */ | ||
| 191 | maxdiv = PLL_DIV_MAX; | ||
| 192 | minrate = (parent_rate * 2) / maxdiv; | ||
| 193 | |||
| 194 | if (parent_rate < characteristics->input.min || | ||
| 195 | parent_rate < characteristics->input.max) | ||
| 196 | return -ERANGE; | ||
| 197 | |||
| 198 | if (parent_rate < minrate || parent_rate > maxrate) | ||
| 199 | return -ERANGE; | ||
| 200 | |||
| 201 | for (i = 0; i < characteristics->num_output; i++) { | ||
| 202 | if (parent_rate >= characteristics->output[i].min && | ||
| 203 | parent_rate <= characteristics->output[i].max) | ||
| 204 | break; | ||
| 205 | } | ||
| 206 | |||
| 207 | if (i >= characteristics->num_output) | ||
| 208 | return -ERANGE; | ||
| 209 | |||
| 210 | bestmul = rate / parent_rate; | ||
| 211 | rounddown = parent_rate % rate; | ||
| 212 | roundup = rate - rounddown; | ||
| 213 | bestremainder = roundup < rounddown ? roundup : rounddown; | ||
| 214 | |||
| 215 | if (!bestremainder) { | ||
| 216 | if (div) | ||
| 217 | *div = bestdiv; | ||
| 218 | if (mul) | ||
| 219 | *mul = bestmul; | ||
| 220 | if (index) | ||
| 221 | *index = i; | ||
| 222 | return rate; | ||
| 223 | } | ||
| 224 | |||
| 225 | maxdiv = 255 / (bestmul + 1); | ||
| 226 | if (parent_rate / maxdiv < characteristics->input.min) | ||
| 227 | maxdiv = parent_rate / characteristics->input.min; | ||
| 228 | mindiv = parent_rate / characteristics->input.max; | ||
| 229 | if (parent_rate % characteristics->input.max) | ||
| 230 | mindiv++; | ||
| 231 | |||
| 232 | for (tmpdiv = mindiv; tmpdiv < maxdiv; tmpdiv++) { | ||
| 233 | divrate = parent_rate / tmpdiv; | ||
| 234 | |||
| 235 | rounddown = rate % divrate; | ||
| 236 | roundup = divrate - rounddown; | ||
| 237 | remainder = roundup < rounddown ? roundup : rounddown; | ||
| 238 | |||
| 239 | if (remainder < bestremainder) { | ||
| 240 | bestremainder = remainder; | ||
| 241 | bestmul = rate / divrate; | ||
| 242 | bestdiv = tmpdiv; | ||
| 243 | } | ||
| 244 | |||
| 245 | if (!remainder) | ||
| 246 | break; | ||
| 247 | } | ||
| 248 | |||
| 249 | rate = (parent_rate / bestdiv) * bestmul; | ||
| 250 | |||
| 251 | if (div) | ||
| 252 | *div = bestdiv; | ||
| 253 | if (mul) | ||
| 254 | *mul = bestmul; | ||
| 255 | if (index) | ||
| 256 | *index = i; | ||
| 257 | |||
| 258 | return rate; | ||
| 259 | } | ||
| 260 | |||
| 261 | static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate, | ||
| 262 | unsigned long *parent_rate) | ||
| 263 | { | ||
| 264 | struct clk_pll *pll = to_clk_pll(hw); | ||
| 265 | |||
| 266 | return clk_pll_get_best_div_mul(pll, rate, *parent_rate, | ||
| 267 | NULL, NULL, NULL); | ||
| 268 | } | ||
| 269 | |||
| 270 | static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, | ||
| 271 | unsigned long parent_rate) | ||
| 272 | { | ||
| 273 | struct clk_pll *pll = to_clk_pll(hw); | ||
| 274 | long ret; | ||
| 275 | u32 div; | ||
| 276 | u32 mul; | ||
| 277 | u32 index; | ||
| 278 | |||
| 279 | ret = clk_pll_get_best_div_mul(pll, rate, parent_rate, | ||
| 280 | &div, &mul, &index); | ||
| 281 | if (ret < 0) | ||
| 282 | return ret; | ||
| 283 | |||
| 284 | pll->range = index; | ||
| 285 | pll->div = div; | ||
| 286 | pll->mul = mul; | ||
| 287 | |||
| 288 | return 0; | ||
| 289 | } | ||
| 290 | |||
| 291 | static const struct clk_ops pll_ops = { | ||
| 292 | .prepare = clk_pll_prepare, | ||
| 293 | .unprepare = clk_pll_unprepare, | ||
| 294 | .is_prepared = clk_pll_is_prepared, | ||
| 295 | .recalc_rate = clk_pll_recalc_rate, | ||
| 296 | .round_rate = clk_pll_round_rate, | ||
| 297 | .set_rate = clk_pll_set_rate, | ||
| 298 | }; | ||
| 299 | |||
| 300 | static struct clk * __init | ||
| 301 | at91_clk_register_pll(struct at91_pmc *pmc, unsigned int irq, const char *name, | ||
| 302 | const char *parent_name, u8 id, | ||
| 303 | const struct clk_pll_layout *layout, | ||
| 304 | const struct clk_pll_characteristics *characteristics) | ||
| 305 | { | ||
| 306 | struct clk_pll *pll; | ||
| 307 | struct clk *clk = NULL; | ||
| 308 | struct clk_init_data init; | ||
| 309 | int ret; | ||
| 310 | int offset = PLL_REG(id); | ||
| 311 | u32 tmp; | ||
| 312 | |||
| 313 | if (id > PLL_MAX_ID) | ||
| 314 | return ERR_PTR(-EINVAL); | ||
| 315 | |||
| 316 | pll = kzalloc(sizeof(*pll), GFP_KERNEL); | ||
| 317 | if (!pll) | ||
| 318 | return ERR_PTR(-ENOMEM); | ||
| 319 | |||
| 320 | init.name = name; | ||
| 321 | init.ops = &pll_ops; | ||
| 322 | init.parent_names = &parent_name; | ||
| 323 | init.num_parents = 1; | ||
| 324 | init.flags = CLK_SET_RATE_GATE; | ||
| 325 | |||
| 326 | pll->id = id; | ||
| 327 | pll->hw.init = &init; | ||
| 328 | pll->layout = layout; | ||
| 329 | pll->characteristics = characteristics; | ||
| 330 | pll->pmc = pmc; | ||
| 331 | pll->irq = irq; | ||
| 332 | tmp = pmc_read(pmc, offset) & layout->pllr_mask; | ||
| 333 | pll->div = PLL_DIV(tmp); | ||
| 334 | pll->mul = PLL_MUL(tmp, layout); | ||
| 335 | init_waitqueue_head(&pll->wait); | ||
| 336 | irq_set_status_flags(pll->irq, IRQ_NOAUTOEN); | ||
| 337 | ret = request_irq(pll->irq, clk_pll_irq_handler, IRQF_TRIGGER_HIGH, | ||
| 338 | id ? "clk-pllb" : "clk-plla", pll); | ||
| 339 | if (ret) | ||
| 340 | return ERR_PTR(ret); | ||
| 341 | |||
| 342 | clk = clk_register(NULL, &pll->hw); | ||
| 343 | if (IS_ERR(clk)) | ||
| 344 | kfree(pll); | ||
| 345 | |||
| 346 | return clk; | ||
| 347 | } | ||
| 348 | |||
| 349 | |||
| 350 | static const struct clk_pll_layout at91rm9200_pll_layout = { | ||
| 351 | .pllr_mask = 0x7FFFFFF, | ||
| 352 | .mul_shift = 16, | ||
| 353 | .mul_mask = 0x7FF, | ||
| 354 | }; | ||
| 355 | |||
| 356 | static const struct clk_pll_layout at91sam9g45_pll_layout = { | ||
| 357 | .pllr_mask = 0xFFFFFF, | ||
| 358 | .mul_shift = 16, | ||
| 359 | .mul_mask = 0xFF, | ||
| 360 | }; | ||
| 361 | |||
| 362 | static const struct clk_pll_layout at91sam9g20_pllb_layout = { | ||
| 363 | .pllr_mask = 0x3FFFFF, | ||
| 364 | .mul_shift = 16, | ||
| 365 | .mul_mask = 0x3F, | ||
| 366 | }; | ||
| 367 | |||
| 368 | static const struct clk_pll_layout sama5d3_pll_layout = { | ||
| 369 | .pllr_mask = 0x1FFFFFF, | ||
| 370 | .mul_shift = 18, | ||
| 371 | .mul_mask = 0x7F, | ||
| 372 | }; | ||
| 373 | |||
| 374 | |||
| 375 | static struct clk_pll_characteristics * __init | ||
| 376 | of_at91_clk_pll_get_characteristics(struct device_node *np) | ||
| 377 | { | ||
| 378 | int i; | ||
| 379 | int offset; | ||
| 380 | u32 tmp; | ||
| 381 | int num_output; | ||
| 382 | u32 num_cells; | ||
| 383 | struct clk_range input; | ||
| 384 | struct clk_range *output; | ||
| 385 | u8 *out = NULL; | ||
| 386 | u16 *icpll = NULL; | ||
| 387 | struct clk_pll_characteristics *characteristics; | ||
| 388 | |||
| 389 | if (of_at91_get_clk_range(np, "atmel,clk-input-range", &input)) | ||
| 390 | return NULL; | ||
| 391 | |||
| 392 | if (of_property_read_u32(np, "#atmel,pll-clk-output-range-cells", | ||
| 393 | &num_cells)) | ||
| 394 | return NULL; | ||
| 395 | |||
| 396 | if (num_cells < 2 || num_cells > 4) | ||
| 397 | return NULL; | ||
| 398 | |||
| 399 | if (!of_get_property(np, "atmel,pll-clk-output-ranges", &tmp)) | ||
| 400 | return NULL; | ||
| 401 | num_output = tmp / (sizeof(u32) * num_cells); | ||
| 402 | |||
| 403 | characteristics = kzalloc(sizeof(*characteristics), GFP_KERNEL); | ||
| 404 | if (!characteristics) | ||
| 405 | return NULL; | ||
| 406 | |||
| 407 | output = kzalloc(sizeof(*output) * num_output, GFP_KERNEL); | ||
| 408 | if (!output) | ||
| 409 | goto out_free_characteristics; | ||
| 410 | |||
| 411 | if (num_cells > 2) { | ||
| 412 | out = kzalloc(sizeof(*out) * num_output, GFP_KERNEL); | ||
| 413 | if (!out) | ||
| 414 | goto out_free_output; | ||
| 415 | } | ||
| 416 | |||
| 417 | if (num_cells > 3) { | ||
| 418 | icpll = kzalloc(sizeof(*icpll) * num_output, GFP_KERNEL); | ||
| 419 | if (!icpll) | ||
| 420 | goto out_free_output; | ||
| 421 | } | ||
| 422 | |||
| 423 | for (i = 0; i < num_output; i++) { | ||
| 424 | offset = i * num_cells; | ||
| 425 | if (of_property_read_u32_index(np, | ||
| 426 | "atmel,pll-clk-output-ranges", | ||
| 427 | offset, &tmp)) | ||
| 428 | goto out_free_output; | ||
| 429 | output[i].min = tmp; | ||
| 430 | if (of_property_read_u32_index(np, | ||
| 431 | "atmel,pll-clk-output-ranges", | ||
| 432 | offset + 1, &tmp)) | ||
| 433 | goto out_free_output; | ||
| 434 | output[i].max = tmp; | ||
| 435 | |||
| 436 | if (num_cells == 2) | ||
| 437 | continue; | ||
| 438 | |||
| 439 | if (of_property_read_u32_index(np, | ||
| 440 | "atmel,pll-clk-output-ranges", | ||
| 441 | offset + 2, &tmp)) | ||
| 442 | goto out_free_output; | ||
| 443 | out[i] = tmp; | ||
| 444 | |||
| 445 | if (num_cells == 3) | ||
| 446 | continue; | ||
| 447 | |||
| 448 | if (of_property_read_u32_index(np, | ||
| 449 | "atmel,pll-clk-output-ranges", | ||
| 450 | offset + 3, &tmp)) | ||
| 451 | goto out_free_output; | ||
| 452 | icpll[i] = tmp; | ||
| 453 | } | ||
| 454 | |||
| 455 | characteristics->input = input; | ||
| 456 | characteristics->num_output = num_output; | ||
| 457 | characteristics->output = output; | ||
| 458 | characteristics->out = out; | ||
| 459 | characteristics->icpll = icpll; | ||
| 460 | return characteristics; | ||
| 461 | |||
| 462 | out_free_output: | ||
| 463 | kfree(icpll); | ||
| 464 | kfree(out); | ||
| 465 | kfree(output); | ||
| 466 | out_free_characteristics: | ||
| 467 | kfree(characteristics); | ||
| 468 | return NULL; | ||
| 469 | } | ||
| 470 | |||
| 471 | static void __init | ||
| 472 | of_at91_clk_pll_setup(struct device_node *np, struct at91_pmc *pmc, | ||
| 473 | const struct clk_pll_layout *layout) | ||
| 474 | { | ||
| 475 | u32 id; | ||
| 476 | unsigned int irq; | ||
| 477 | struct clk *clk; | ||
| 478 | const char *parent_name; | ||
| 479 | const char *name = np->name; | ||
| 480 | struct clk_pll_characteristics *characteristics; | ||
| 481 | |||
| 482 | if (of_property_read_u32(np, "reg", &id)) | ||
| 483 | return; | ||
| 484 | |||
| 485 | parent_name = of_clk_get_parent_name(np, 0); | ||
| 486 | |||
| 487 | of_property_read_string(np, "clock-output-names", &name); | ||
| 488 | |||
| 489 | characteristics = of_at91_clk_pll_get_characteristics(np); | ||
| 490 | if (!characteristics) | ||
| 491 | return; | ||
| 492 | |||
| 493 | irq = irq_of_parse_and_map(np, 0); | ||
| 494 | if (!irq) | ||
| 495 | return; | ||
| 496 | |||
| 497 | clk = at91_clk_register_pll(pmc, irq, name, parent_name, id, layout, | ||
| 498 | characteristics); | ||
| 499 | if (IS_ERR(clk)) | ||
| 500 | goto out_free_characteristics; | ||
| 501 | |||
| 502 | of_clk_add_provider(np, of_clk_src_simple_get, clk); | ||
| 503 | return; | ||
| 504 | |||
| 505 | out_free_characteristics: | ||
| 506 | kfree(characteristics); | ||
| 507 | } | ||
| 508 | |||
| 509 | void __init of_at91rm9200_clk_pll_setup(struct device_node *np, | ||
| 510 | struct at91_pmc *pmc) | ||
| 511 | { | ||
| 512 | of_at91_clk_pll_setup(np, pmc, &at91rm9200_pll_layout); | ||
| 513 | } | ||
| 514 | |||
| 515 | void __init of_at91sam9g45_clk_pll_setup(struct device_node *np, | ||
| 516 | struct at91_pmc *pmc) | ||
| 517 | { | ||
| 518 | of_at91_clk_pll_setup(np, pmc, &at91sam9g45_pll_layout); | ||
| 519 | } | ||
| 520 | |||
| 521 | void __init of_at91sam9g20_clk_pllb_setup(struct device_node *np, | ||
| 522 | struct at91_pmc *pmc) | ||
| 523 | { | ||
| 524 | of_at91_clk_pll_setup(np, pmc, &at91sam9g20_pllb_layout); | ||
| 525 | } | ||
| 526 | |||
| 527 | void __init of_sama5d3_clk_pll_setup(struct device_node *np, | ||
| 528 | struct at91_pmc *pmc) | ||
| 529 | { | ||
| 530 | of_at91_clk_pll_setup(np, pmc, &sama5d3_pll_layout); | ||
| 531 | } | ||
diff --git a/drivers/clk/at91/clk-plldiv.c b/drivers/clk/at91/clk-plldiv.c new file mode 100644 index 000000000000..ea226562bb40 --- /dev/null +++ b/drivers/clk/at91/clk-plldiv.c | |||
| @@ -0,0 +1,135 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; either version 2 of the License, or | ||
| 7 | * (at your option) any later version. | ||
| 8 | * | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/clk-provider.h> | ||
| 12 | #include <linux/clkdev.h> | ||
| 13 | #include <linux/clk/at91_pmc.h> | ||
| 14 | #include <linux/of.h> | ||
| 15 | #include <linux/of_address.h> | ||
| 16 | #include <linux/io.h> | ||
| 17 | |||
| 18 | #include "pmc.h" | ||
| 19 | |||
| 20 | #define to_clk_plldiv(hw) container_of(hw, struct clk_plldiv, hw) | ||
| 21 | |||
| 22 | struct clk_plldiv { | ||
| 23 | struct clk_hw hw; | ||
| 24 | struct at91_pmc *pmc; | ||
| 25 | }; | ||
| 26 | |||
| 27 | static unsigned long clk_plldiv_recalc_rate(struct clk_hw *hw, | ||
| 28 | unsigned long parent_rate) | ||
| 29 | { | ||
| 30 | struct clk_plldiv *plldiv = to_clk_plldiv(hw); | ||
| 31 | struct at91_pmc *pmc = plldiv->pmc; | ||
| 32 | |||
| 33 | if (pmc_read(pmc, AT91_PMC_MCKR) & AT91_PMC_PLLADIV2) | ||
| 34 | return parent_rate / 2; | ||
| 35 | |||
| 36 | return parent_rate; | ||
| 37 | } | ||
| 38 | |||
| 39 | static long clk_plldiv_round_rate(struct clk_hw *hw, unsigned long rate, | ||
| 40 | unsigned long *parent_rate) | ||
| 41 | { | ||
| 42 | unsigned long div; | ||
| 43 | |||
| 44 | if (rate > *parent_rate) | ||
| 45 | return *parent_rate; | ||
| 46 | div = *parent_rate / 2; | ||
| 47 | if (rate < div) | ||
| 48 | return div; | ||
| 49 | |||
| 50 | if (rate - div < *parent_rate - rate) | ||
| 51 | return div; | ||
| 52 | |||
| 53 | return *parent_rate; | ||
| 54 | } | ||
| 55 | |||
| 56 | static int clk_plldiv_set_rate(struct clk_hw *hw, unsigned long rate, | ||
| 57 | unsigned long parent_rate) | ||
| 58 | { | ||
| 59 | struct clk_plldiv *plldiv = to_clk_plldiv(hw); | ||
| 60 | struct at91_pmc *pmc = plldiv->pmc; | ||
| 61 | u32 tmp; | ||
| 62 | |||
| 63 | if (parent_rate != rate && (parent_rate / 2) != rate) | ||
| 64 | return -EINVAL; | ||
| 65 | |||
| 66 | pmc_lock(pmc); | ||
| 67 | tmp = pmc_read(pmc, AT91_PMC_MCKR) & ~AT91_PMC_PLLADIV2; | ||
| 68 | if ((parent_rate / 2) == rate) | ||
| 69 | tmp |= AT91_PMC_PLLADIV2; | ||
| 70 | pmc_write(pmc, AT91_PMC_MCKR, tmp); | ||
| 71 | pmc_unlock(pmc); | ||
| 72 | |||
| 73 | return 0; | ||
| 74 | } | ||
| 75 | |||
| 76 | static const struct clk_ops plldiv_ops = { | ||
| 77 | .recalc_rate = clk_plldiv_recalc_rate, | ||
| 78 | .round_rate = clk_plldiv_round_rate, | ||
| 79 | .set_rate = clk_plldiv_set_rate, | ||
| 80 | }; | ||
| 81 | |||
| 82 | static struct clk * __init | ||
| 83 | at91_clk_register_plldiv(struct at91_pmc *pmc, const char *name, | ||
| 84 | const char *parent_name) | ||
| 85 | { | ||
| 86 | struct clk_plldiv *plldiv; | ||
| 87 | struct clk *clk = NULL; | ||
| 88 | struct clk_init_data init; | ||
| 89 | |||
| 90 | plldiv = kzalloc(sizeof(*plldiv), GFP_KERNEL); | ||
| 91 | if (!plldiv) | ||
| 92 | return ERR_PTR(-ENOMEM); | ||
| 93 | |||
| 94 | init.name = name; | ||
| 95 | init.ops = &plldiv_ops; | ||
| 96 | init.parent_names = parent_name ? &parent_name : NULL; | ||
| 97 | init.num_parents = parent_name ? 1 : 0; | ||
| 98 | init.flags = CLK_SET_RATE_GATE; | ||
| 99 | |||
| 100 | plldiv->hw.init = &init; | ||
| 101 | plldiv->pmc = pmc; | ||
| 102 | |||
| 103 | clk = clk_register(NULL, &plldiv->hw); | ||
| 104 | |||
| 105 | if (IS_ERR(clk)) | ||
| 106 | kfree(plldiv); | ||
| 107 | |||
| 108 | return clk; | ||
| 109 | } | ||
| 110 | |||
| 111 | static void __init | ||
| 112 | of_at91_clk_plldiv_setup(struct device_node *np, struct at91_pmc *pmc) | ||
| 113 | { | ||
| 114 | struct clk *clk; | ||
| 115 | const char *parent_name; | ||
| 116 | const char *name = np->name; | ||
| 117 | |||
| 118 | parent_name = of_clk_get_parent_name(np, 0); | ||
| 119 | |||
| 120 | of_property_read_string(np, "clock-output-names", &name); | ||
| 121 | |||
| 122 | clk = at91_clk_register_plldiv(pmc, name, parent_name); | ||
| 123 | |||
| 124 | if (IS_ERR(clk)) | ||
| 125 | return; | ||
| 126 | |||
| 127 | of_clk_add_provider(np, of_clk_src_simple_get, clk); | ||
| 128 | return; | ||
| 129 | } | ||
| 130 | |||
| 131 | void __init of_at91sam9x5_clk_plldiv_setup(struct device_node *np, | ||
| 132 | struct at91_pmc *pmc) | ||
| 133 | { | ||
| 134 | of_at91_clk_plldiv_setup(np, pmc); | ||
| 135 | } | ||
diff --git a/drivers/clk/at91/clk-programmable.c b/drivers/clk/at91/clk-programmable.c new file mode 100644 index 000000000000..fd792b203eaf --- /dev/null +++ b/drivers/clk/at91/clk-programmable.c | |||
| @@ -0,0 +1,366 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; either version 2 of the License, or | ||
| 7 | * (at your option) any later version. | ||
| 8 | * | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/clk-provider.h> | ||
| 12 | #include <linux/clkdev.h> | ||
| 13 | #include <linux/clk/at91_pmc.h> | ||
| 14 | #include <linux/of.h> | ||
| 15 | #include <linux/of_address.h> | ||
| 16 | #include <linux/of_irq.h> | ||
| 17 | #include <linux/io.h> | ||
| 18 | #include <linux/wait.h> | ||
| 19 | #include <linux/sched.h> | ||
| 20 | #include <linux/interrupt.h> | ||
| 21 | #include <linux/irq.h> | ||
| 22 | |||
| 23 | #include "pmc.h" | ||
| 24 | |||
| 25 | #define PROG_SOURCE_MAX 5 | ||
| 26 | #define PROG_ID_MAX 7 | ||
| 27 | |||
| 28 | #define PROG_STATUS_MASK(id) (1 << ((id) + 8)) | ||
| 29 | #define PROG_PRES_MASK 0x7 | ||
| 30 | #define PROG_MAX_RM9200_CSS 3 | ||
| 31 | |||
| 32 | struct clk_programmable_layout { | ||
| 33 | u8 pres_shift; | ||
| 34 | u8 css_mask; | ||
| 35 | u8 have_slck_mck; | ||
| 36 | }; | ||
| 37 | |||
| 38 | struct clk_programmable { | ||
| 39 | struct clk_hw hw; | ||
| 40 | struct at91_pmc *pmc; | ||
| 41 | unsigned int irq; | ||
| 42 | wait_queue_head_t wait; | ||
| 43 | u8 id; | ||
| 44 | u8 css; | ||
| 45 | u8 pres; | ||
| 46 | u8 slckmck; | ||
| 47 | const struct clk_programmable_layout *layout; | ||
| 48 | }; | ||
| 49 | |||
| 50 | #define to_clk_programmable(hw) container_of(hw, struct clk_programmable, hw) | ||
| 51 | |||
| 52 | |||
| 53 | static irqreturn_t clk_programmable_irq_handler(int irq, void *dev_id) | ||
| 54 | { | ||
| 55 | struct clk_programmable *prog = (struct clk_programmable *)dev_id; | ||
| 56 | |||
| 57 | wake_up(&prog->wait); | ||
| 58 | |||
| 59 | return IRQ_HANDLED; | ||
| 60 | } | ||
| 61 | |||
| 62 | static int clk_programmable_prepare(struct clk_hw *hw) | ||
| 63 | { | ||
| 64 | u32 tmp; | ||
| 65 | struct clk_programmable *prog = to_clk_programmable(hw); | ||
| 66 | struct at91_pmc *pmc = prog->pmc; | ||
| 67 | const struct clk_programmable_layout *layout = prog->layout; | ||
| 68 | u8 id = prog->id; | ||
| 69 | u32 mask = PROG_STATUS_MASK(id); | ||
| 70 | |||
| 71 | tmp = prog->css | (prog->pres << layout->pres_shift); | ||
| 72 | if (layout->have_slck_mck && prog->slckmck) | ||
| 73 | tmp |= AT91_PMC_CSSMCK_MCK; | ||
| 74 | |||
| 75 | pmc_write(pmc, AT91_PMC_PCKR(id), tmp); | ||
| 76 | |||
| 77 | while (!(pmc_read(pmc, AT91_PMC_SR) & mask)) | ||
| 78 | wait_event(prog->wait, pmc_read(pmc, AT91_PMC_SR) & mask); | ||
| 79 | |||
| 80 | return 0; | ||
| 81 | } | ||
| 82 | |||
| 83 | static int clk_programmable_is_ready(struct clk_hw *hw) | ||
| 84 | { | ||
| 85 | struct clk_programmable *prog = to_clk_programmable(hw); | ||
| 86 | struct at91_pmc *pmc = prog->pmc; | ||
| 87 | |||
| 88 | return !!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_PCKR(prog->id)); | ||
| 89 | } | ||
| 90 | |||
| 91 | static unsigned long clk_programmable_recalc_rate(struct clk_hw *hw, | ||
| 92 | unsigned long parent_rate) | ||
| 93 | { | ||
| 94 | u32 tmp; | ||
| 95 | struct clk_programmable *prog = to_clk_programmable(hw); | ||
| 96 | struct at91_pmc *pmc = prog->pmc; | ||
| 97 | const struct clk_programmable_layout *layout = prog->layout; | ||
| 98 | |||
| 99 | tmp = pmc_read(pmc, AT91_PMC_PCKR(prog->id)); | ||
| 100 | prog->pres = (tmp >> layout->pres_shift) & PROG_PRES_MASK; | ||
| 101 | |||
| 102 | return parent_rate >> prog->pres; | ||
| 103 | } | ||
| 104 | |||
| 105 | static long clk_programmable_round_rate(struct clk_hw *hw, unsigned long rate, | ||
| 106 | unsigned long *parent_rate) | ||
| 107 | { | ||
| 108 | unsigned long best_rate = *parent_rate; | ||
| 109 | unsigned long best_diff; | ||
| 110 | unsigned long new_diff; | ||
| 111 | unsigned long cur_rate; | ||
| 112 | int shift = shift; | ||
| 113 | |||
| 114 | if (rate > *parent_rate) | ||
| 115 | return *parent_rate; | ||
| 116 | else | ||
| 117 | best_diff = *parent_rate - rate; | ||
| 118 | |||
| 119 | if (!best_diff) | ||
| 120 | return best_rate; | ||
| 121 | |||
| 122 | for (shift = 1; shift < PROG_PRES_MASK; shift++) { | ||
| 123 | cur_rate = *parent_rate >> shift; | ||
| 124 | |||
| 125 | if (cur_rate > rate) | ||
| 126 | new_diff = cur_rate - rate; | ||
| 127 | else | ||
| 128 | new_diff = rate - cur_rate; | ||
| 129 | |||
| 130 | if (!new_diff) | ||
| 131 | return cur_rate; | ||
| 132 | |||
| 133 | if (new_diff < best_diff) { | ||
| 134 | best_diff = new_diff; | ||
| 135 | best_rate = cur_rate; | ||
| 136 | } | ||
| 137 | |||
| 138 | if (rate > cur_rate) | ||
| 139 | break; | ||
| 140 | } | ||
| 141 | |||
| 142 | return best_rate; | ||
| 143 | } | ||
| 144 | |||
| 145 | static int clk_programmable_set_parent(struct clk_hw *hw, u8 index) | ||
| 146 | { | ||
| 147 | struct clk_programmable *prog = to_clk_programmable(hw); | ||
| 148 | const struct clk_programmable_layout *layout = prog->layout; | ||
| 149 | if (index > layout->css_mask) { | ||
| 150 | if (index > PROG_MAX_RM9200_CSS && layout->have_slck_mck) { | ||
| 151 | prog->css = 0; | ||
| 152 | prog->slckmck = 1; | ||
| 153 | return 0; | ||
| 154 | } else { | ||
| 155 | return -EINVAL; | ||
| 156 | } | ||
| 157 | } | ||
| 158 | |||
| 159 | prog->css = index; | ||
| 160 | return 0; | ||
| 161 | } | ||
| 162 | |||
| 163 | static u8 clk_programmable_get_parent(struct clk_hw *hw) | ||
| 164 | { | ||
| 165 | u32 tmp; | ||
| 166 | u8 ret; | ||
| 167 | struct clk_programmable *prog = to_clk_programmable(hw); | ||
| 168 | struct at91_pmc *pmc = prog->pmc; | ||
| 169 | const struct clk_programmable_layout *layout = prog->layout; | ||
| 170 | |||
| 171 | tmp = pmc_read(pmc, AT91_PMC_PCKR(prog->id)); | ||
| 172 | prog->css = tmp & layout->css_mask; | ||
| 173 | ret = prog->css; | ||
| 174 | if (layout->have_slck_mck) { | ||
| 175 | prog->slckmck = !!(tmp & AT91_PMC_CSSMCK_MCK); | ||
| 176 | if (prog->slckmck && !ret) | ||
| 177 | ret = PROG_MAX_RM9200_CSS + 1; | ||
| 178 | } | ||
| 179 | |||
| 180 | return ret; | ||
| 181 | } | ||
| 182 | |||
| 183 | static int clk_programmable_set_rate(struct clk_hw *hw, unsigned long rate, | ||
| 184 | unsigned long parent_rate) | ||
| 185 | { | ||
| 186 | struct clk_programmable *prog = to_clk_programmable(hw); | ||
| 187 | unsigned long best_rate = parent_rate; | ||
| 188 | unsigned long best_diff; | ||
| 189 | unsigned long new_diff; | ||
| 190 | unsigned long cur_rate; | ||
| 191 | int shift = 0; | ||
| 192 | |||
| 193 | if (rate > parent_rate) | ||
| 194 | return parent_rate; | ||
| 195 | else | ||
| 196 | best_diff = parent_rate - rate; | ||
| 197 | |||
| 198 | if (!best_diff) { | ||
| 199 | prog->pres = shift; | ||
| 200 | return 0; | ||
| 201 | } | ||
| 202 | |||
| 203 | for (shift = 1; shift < PROG_PRES_MASK; shift++) { | ||
| 204 | cur_rate = parent_rate >> shift; | ||
| 205 | |||
| 206 | if (cur_rate > rate) | ||
| 207 | new_diff = cur_rate - rate; | ||
| 208 | else | ||
| 209 | new_diff = rate - cur_rate; | ||
| 210 | |||
| 211 | if (!new_diff) | ||
| 212 | break; | ||
| 213 | |||
| 214 | if (new_diff < best_diff) { | ||
| 215 | best_diff = new_diff; | ||
| 216 | best_rate = cur_rate; | ||
| 217 | } | ||
| 218 | |||
| 219 | if (rate > cur_rate) | ||
| 220 | break; | ||
| 221 | } | ||
| 222 | |||
| 223 | prog->pres = shift; | ||
| 224 | return 0; | ||
| 225 | } | ||
| 226 | |||
| 227 | static const struct clk_ops programmable_ops = { | ||
| 228 | .prepare = clk_programmable_prepare, | ||
| 229 | .is_prepared = clk_programmable_is_ready, | ||
| 230 | .recalc_rate = clk_programmable_recalc_rate, | ||
| 231 | .round_rate = clk_programmable_round_rate, | ||
| 232 | .get_parent = clk_programmable_get_parent, | ||
| 233 | .set_parent = clk_programmable_set_parent, | ||
| 234 | .set_rate = clk_programmable_set_rate, | ||
| 235 | }; | ||
| 236 | |||
| 237 | static struct clk * __init | ||
| 238 | at91_clk_register_programmable(struct at91_pmc *pmc, unsigned int irq, | ||
| 239 | const char *name, const char **parent_names, | ||
| 240 | u8 num_parents, u8 id, | ||
| 241 | const struct clk_programmable_layout *layout) | ||
| 242 | { | ||
| 243 | int ret; | ||
| 244 | struct clk_programmable *prog; | ||
| 245 | struct clk *clk = NULL; | ||
| 246 | struct clk_init_data init; | ||
| 247 | char irq_name[11]; | ||
| 248 | |||
| 249 | if (id > PROG_ID_MAX) | ||
| 250 | return ERR_PTR(-EINVAL); | ||
| 251 | |||
| 252 | prog = kzalloc(sizeof(*prog), GFP_KERNEL); | ||
| 253 | if (!prog) | ||
| 254 | return ERR_PTR(-ENOMEM); | ||
| 255 | |||
| 256 | init.name = name; | ||
| 257 | init.ops = &programmable_ops; | ||
| 258 | init.parent_names = parent_names; | ||
| 259 | init.num_parents = num_parents; | ||
| 260 | init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE; | ||
| 261 | |||
| 262 | prog->id = id; | ||
| 263 | prog->layout = layout; | ||
| 264 | prog->hw.init = &init; | ||
| 265 | prog->pmc = pmc; | ||
| 266 | prog->irq = irq; | ||
| 267 | init_waitqueue_head(&prog->wait); | ||
| 268 | irq_set_status_flags(prog->irq, IRQ_NOAUTOEN); | ||
| 269 | snprintf(irq_name, sizeof(irq_name), "clk-prog%d", id); | ||
| 270 | ret = request_irq(prog->irq, clk_programmable_irq_handler, | ||
| 271 | IRQF_TRIGGER_HIGH, irq_name, prog); | ||
| 272 | if (ret) | ||
| 273 | return ERR_PTR(ret); | ||
| 274 | |||
| 275 | clk = clk_register(NULL, &prog->hw); | ||
| 276 | if (IS_ERR(clk)) | ||
| 277 | kfree(prog); | ||
| 278 | |||
| 279 | return clk; | ||
| 280 | } | ||
| 281 | |||
| 282 | static const struct clk_programmable_layout at91rm9200_programmable_layout = { | ||
| 283 | .pres_shift = 2, | ||
| 284 | .css_mask = 0x3, | ||
| 285 | .have_slck_mck = 0, | ||
| 286 | }; | ||
| 287 | |||
| 288 | static const struct clk_programmable_layout at91sam9g45_programmable_layout = { | ||
| 289 | .pres_shift = 2, | ||
| 290 | .css_mask = 0x3, | ||
| 291 | .have_slck_mck = 1, | ||
| 292 | }; | ||
| 293 | |||
| 294 | static const struct clk_programmable_layout at91sam9x5_programmable_layout = { | ||
| 295 | .pres_shift = 4, | ||
| 296 | .css_mask = 0x7, | ||
| 297 | .have_slck_mck = 0, | ||
| 298 | }; | ||
| 299 | |||
| 300 | static void __init | ||
| 301 | of_at91_clk_prog_setup(struct device_node *np, struct at91_pmc *pmc, | ||
| 302 | const struct clk_programmable_layout *layout) | ||
| 303 | { | ||
| 304 | int num; | ||
| 305 | u32 id; | ||
| 306 | int i; | ||
| 307 | unsigned int irq; | ||
| 308 | struct clk *clk; | ||
| 309 | int num_parents; | ||
| 310 | const char *parent_names[PROG_SOURCE_MAX]; | ||
| 311 | const char *name; | ||
| 312 | struct device_node *progclknp; | ||
| 313 | |||
| 314 | num_parents = of_count_phandle_with_args(np, "clocks", "#clock-cells"); | ||
| 315 | if (num_parents <= 0 || num_parents > PROG_SOURCE_MAX) | ||
| 316 | return; | ||
| 317 | |||
| 318 | for (i = 0; i < num_parents; ++i) { | ||
| 319 | parent_names[i] = of_clk_get_parent_name(np, i); | ||
| 320 | if (!parent_names[i]) | ||
| 321 | return; | ||
| 322 | } | ||
| 323 | |||
| 324 | num = of_get_child_count(np); | ||
| 325 | if (!num || num > (PROG_ID_MAX + 1)) | ||
| 326 | return; | ||
| 327 | |||
| 328 | for_each_child_of_node(np, progclknp) { | ||
| 329 | if (of_property_read_u32(progclknp, "reg", &id)) | ||
| 330 | continue; | ||
| 331 | |||
| 332 | if (of_property_read_string(np, "clock-output-names", &name)) | ||
| 333 | name = progclknp->name; | ||
| 334 | |||
| 335 | irq = irq_of_parse_and_map(progclknp, 0); | ||
| 336 | if (!irq) | ||
| 337 | continue; | ||
| 338 | |||
| 339 | clk = at91_clk_register_programmable(pmc, irq, name, | ||
| 340 | parent_names, num_parents, | ||
| 341 | id, layout); | ||
| 342 | if (IS_ERR(clk)) | ||
| 343 | continue; | ||
| 344 | |||
| 345 | of_clk_add_provider(progclknp, of_clk_src_simple_get, clk); | ||
| 346 | } | ||
| 347 | } | ||
| 348 | |||
| 349 | |||
| 350 | void __init of_at91rm9200_clk_prog_setup(struct device_node *np, | ||
| 351 | struct at91_pmc *pmc) | ||
| 352 | { | ||
| 353 | of_at91_clk_prog_setup(np, pmc, &at91rm9200_programmable_layout); | ||
| 354 | } | ||
| 355 | |||
| 356 | void __init of_at91sam9g45_clk_prog_setup(struct device_node *np, | ||
| 357 | struct at91_pmc *pmc) | ||
| 358 | { | ||
| 359 | of_at91_clk_prog_setup(np, pmc, &at91sam9g45_programmable_layout); | ||
| 360 | } | ||
| 361 | |||
| 362 | void __init of_at91sam9x5_clk_prog_setup(struct device_node *np, | ||
| 363 | struct at91_pmc *pmc) | ||
| 364 | { | ||
| 365 | of_at91_clk_prog_setup(np, pmc, &at91sam9x5_programmable_layout); | ||
| 366 | } | ||
diff --git a/drivers/clk/at91/clk-smd.c b/drivers/clk/at91/clk-smd.c new file mode 100644 index 000000000000..144d47ecfe63 --- /dev/null +++ b/drivers/clk/at91/clk-smd.c | |||
| @@ -0,0 +1,171 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; either version 2 of the License, or | ||
| 7 | * (at your option) any later version. | ||
| 8 | * | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/clk-provider.h> | ||
| 12 | #include <linux/clkdev.h> | ||
| 13 | #include <linux/clk/at91_pmc.h> | ||
| 14 | #include <linux/of.h> | ||
| 15 | #include <linux/of_address.h> | ||
| 16 | #include <linux/io.h> | ||
| 17 | |||
| 18 | #include "pmc.h" | ||
| 19 | |||
| 20 | #define SMD_SOURCE_MAX 2 | ||
| 21 | |||
| 22 | #define SMD_DIV_SHIFT 8 | ||
| 23 | #define SMD_MAX_DIV 0xf | ||
| 24 | |||
| 25 | struct at91sam9x5_clk_smd { | ||
| 26 | struct clk_hw hw; | ||
| 27 | struct at91_pmc *pmc; | ||
| 28 | }; | ||
| 29 | |||
| 30 | #define to_at91sam9x5_clk_smd(hw) \ | ||
| 31 | container_of(hw, struct at91sam9x5_clk_smd, hw) | ||
| 32 | |||
| 33 | static unsigned long at91sam9x5_clk_smd_recalc_rate(struct clk_hw *hw, | ||
| 34 | unsigned long parent_rate) | ||
| 35 | { | ||
| 36 | u32 tmp; | ||
| 37 | u8 smddiv; | ||
| 38 | struct at91sam9x5_clk_smd *smd = to_at91sam9x5_clk_smd(hw); | ||
| 39 | struct at91_pmc *pmc = smd->pmc; | ||
| 40 | |||
| 41 | tmp = pmc_read(pmc, AT91_PMC_SMD); | ||
| 42 | smddiv = (tmp & AT91_PMC_SMD_DIV) >> SMD_DIV_SHIFT; | ||
| 43 | return parent_rate / (smddiv + 1); | ||
| 44 | } | ||
| 45 | |||
| 46 | static long at91sam9x5_clk_smd_round_rate(struct clk_hw *hw, unsigned long rate, | ||
| 47 | unsigned long *parent_rate) | ||
| 48 | { | ||
| 49 | unsigned long div; | ||
| 50 | unsigned long bestrate; | ||
| 51 | unsigned long tmp; | ||
| 52 | |||
| 53 | if (rate >= *parent_rate) | ||
| 54 | return *parent_rate; | ||
| 55 | |||
| 56 | div = *parent_rate / rate; | ||
| 57 | if (div > SMD_MAX_DIV) | ||
| 58 | return *parent_rate / (SMD_MAX_DIV + 1); | ||
| 59 | |||
| 60 | bestrate = *parent_rate / div; | ||
| 61 | tmp = *parent_rate / (div + 1); | ||
| 62 | if (bestrate - rate > rate - tmp) | ||
| 63 | bestrate = tmp; | ||
| 64 | |||
| 65 | return bestrate; | ||
| 66 | } | ||
| 67 | |||
| 68 | static int at91sam9x5_clk_smd_set_parent(struct clk_hw *hw, u8 index) | ||
| 69 | { | ||
| 70 | u32 tmp; | ||
| 71 | struct at91sam9x5_clk_smd *smd = to_at91sam9x5_clk_smd(hw); | ||
| 72 | struct at91_pmc *pmc = smd->pmc; | ||
| 73 | |||
| 74 | if (index > 1) | ||
| 75 | return -EINVAL; | ||
| 76 | tmp = pmc_read(pmc, AT91_PMC_SMD) & ~AT91_PMC_SMDS; | ||
| 77 | if (index) | ||
| 78 | tmp |= AT91_PMC_SMDS; | ||
| 79 | pmc_write(pmc, AT91_PMC_SMD, tmp); | ||
| 80 | return 0; | ||
| 81 | } | ||
| 82 | |||
| 83 | static u8 at91sam9x5_clk_smd_get_parent(struct clk_hw *hw) | ||
| 84 | { | ||
| 85 | struct at91sam9x5_clk_smd *smd = to_at91sam9x5_clk_smd(hw); | ||
| 86 | struct at91_pmc *pmc = smd->pmc; | ||
| 87 | |||
| 88 | return pmc_read(pmc, AT91_PMC_SMD) & AT91_PMC_SMDS; | ||
| 89 | } | ||
| 90 | |||
| 91 | static int at91sam9x5_clk_smd_set_rate(struct clk_hw *hw, unsigned long rate, | ||
| 92 | unsigned long parent_rate) | ||
| 93 | { | ||
| 94 | u32 tmp; | ||
| 95 | struct at91sam9x5_clk_smd *smd = to_at91sam9x5_clk_smd(hw); | ||
| 96 | struct at91_pmc *pmc = smd->pmc; | ||
| 97 | unsigned long div = parent_rate / rate; | ||
| 98 | |||
| 99 | if (parent_rate % rate || div < 1 || div > (SMD_MAX_DIV + 1)) | ||
| 100 | return -EINVAL; | ||
| 101 | tmp = pmc_read(pmc, AT91_PMC_SMD) & ~AT91_PMC_SMD_DIV; | ||
| 102 | tmp |= (div - 1) << SMD_DIV_SHIFT; | ||
| 103 | pmc_write(pmc, AT91_PMC_SMD, tmp); | ||
| 104 | |||
| 105 | return 0; | ||
| 106 | } | ||
| 107 | |||
| 108 | static const struct clk_ops at91sam9x5_smd_ops = { | ||
| 109 | .recalc_rate = at91sam9x5_clk_smd_recalc_rate, | ||
| 110 | .round_rate = at91sam9x5_clk_smd_round_rate, | ||
| 111 | .get_parent = at91sam9x5_clk_smd_get_parent, | ||
| 112 | .set_parent = at91sam9x5_clk_smd_set_parent, | ||
| 113 | .set_rate = at91sam9x5_clk_smd_set_rate, | ||
| 114 | }; | ||
| 115 | |||
| 116 | static struct clk * __init | ||
| 117 | at91sam9x5_clk_register_smd(struct at91_pmc *pmc, const char *name, | ||
| 118 | const char **parent_names, u8 num_parents) | ||
| 119 | { | ||
| 120 | struct at91sam9x5_clk_smd *smd; | ||
| 121 | struct clk *clk = NULL; | ||
| 122 | struct clk_init_data init; | ||
| 123 | |||
| 124 | smd = kzalloc(sizeof(*smd), GFP_KERNEL); | ||
| 125 | if (!smd) | ||
| 126 | return ERR_PTR(-ENOMEM); | ||
| 127 | |||
| 128 | init.name = name; | ||
| 129 | init.ops = &at91sam9x5_smd_ops; | ||
| 130 | init.parent_names = parent_names; | ||
| 131 | init.num_parents = num_parents; | ||
| 132 | init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE; | ||
| 133 | |||
| 134 | smd->hw.init = &init; | ||
| 135 | smd->pmc = pmc; | ||
| 136 | |||
| 137 | clk = clk_register(NULL, &smd->hw); | ||
| 138 | if (IS_ERR(clk)) | ||
| 139 | kfree(smd); | ||
| 140 | |||
| 141 | return clk; | ||
| 142 | } | ||
| 143 | |||
| 144 | void __init of_at91sam9x5_clk_smd_setup(struct device_node *np, | ||
| 145 | struct at91_pmc *pmc) | ||
| 146 | { | ||
| 147 | struct clk *clk; | ||
| 148 | int i; | ||
| 149 | int num_parents; | ||
| 150 | const char *parent_names[SMD_SOURCE_MAX]; | ||
| 151 | const char *name = np->name; | ||
| 152 | |||
| 153 | num_parents = of_count_phandle_with_args(np, "clocks", "#clock-cells"); | ||
| 154 | if (num_parents <= 0 || num_parents > SMD_SOURCE_MAX) | ||
| 155 | return; | ||
| 156 | |||
| 157 | for (i = 0; i < num_parents; i++) { | ||
| 158 | parent_names[i] = of_clk_get_parent_name(np, i); | ||
| 159 | if (!parent_names[i]) | ||
| 160 | return; | ||
| 161 | } | ||
| 162 | |||
| 163 | of_property_read_string(np, "clock-output-names", &name); | ||
| 164 | |||
| 165 | clk = at91sam9x5_clk_register_smd(pmc, name, parent_names, | ||
| 166 | num_parents); | ||
| 167 | if (IS_ERR(clk)) | ||
| 168 | return; | ||
| 169 | |||
| 170 | of_clk_add_provider(np, of_clk_src_simple_get, clk); | ||
| 171 | } | ||
diff --git a/drivers/clk/at91/clk-system.c b/drivers/clk/at91/clk-system.c new file mode 100644 index 000000000000..8f7c0434a09f --- /dev/null +++ b/drivers/clk/at91/clk-system.c | |||
| @@ -0,0 +1,135 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; either version 2 of the License, or | ||
| 7 | * (at your option) any later version. | ||
| 8 | * | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/clk-provider.h> | ||
| 12 | #include <linux/clkdev.h> | ||
| 13 | #include <linux/clk/at91_pmc.h> | ||
| 14 | #include <linux/of.h> | ||
| 15 | #include <linux/of_address.h> | ||
| 16 | #include <linux/io.h> | ||
| 17 | |||
| 18 | #include "pmc.h" | ||
| 19 | |||
| 20 | #define SYSTEM_MAX_ID 31 | ||
| 21 | |||
| 22 | #define SYSTEM_MAX_NAME_SZ 32 | ||
| 23 | |||
| 24 | #define to_clk_system(hw) container_of(hw, struct clk_system, hw) | ||
| 25 | struct clk_system { | ||
| 26 | struct clk_hw hw; | ||
| 27 | struct at91_pmc *pmc; | ||
| 28 | u8 id; | ||
| 29 | }; | ||
| 30 | |||
| 31 | static int clk_system_enable(struct clk_hw *hw) | ||
| 32 | { | ||
| 33 | struct clk_system *sys = to_clk_system(hw); | ||
| 34 | struct at91_pmc *pmc = sys->pmc; | ||
| 35 | |||
| 36 | pmc_write(pmc, AT91_PMC_SCER, 1 << sys->id); | ||
| 37 | return 0; | ||
| 38 | } | ||
| 39 | |||
| 40 | static void clk_system_disable(struct clk_hw *hw) | ||
| 41 | { | ||
| 42 | struct clk_system *sys = to_clk_system(hw); | ||
| 43 | struct at91_pmc *pmc = sys->pmc; | ||
| 44 | |||
| 45 | pmc_write(pmc, AT91_PMC_SCDR, 1 << sys->id); | ||
| 46 | } | ||
| 47 | |||
| 48 | static int clk_system_is_enabled(struct clk_hw *hw) | ||
| 49 | { | ||
| 50 | struct clk_system *sys = to_clk_system(hw); | ||
| 51 | struct at91_pmc *pmc = sys->pmc; | ||
| 52 | |||
| 53 | return !!(pmc_read(pmc, AT91_PMC_SCSR) & (1 << sys->id)); | ||
| 54 | } | ||
| 55 | |||
| 56 | static const struct clk_ops system_ops = { | ||
| 57 | .enable = clk_system_enable, | ||
| 58 | .disable = clk_system_disable, | ||
| 59 | .is_enabled = clk_system_is_enabled, | ||
| 60 | }; | ||
| 61 | |||
| 62 | static struct clk * __init | ||
| 63 | at91_clk_register_system(struct at91_pmc *pmc, const char *name, | ||
| 64 | const char *parent_name, u8 id) | ||
| 65 | { | ||
| 66 | struct clk_system *sys; | ||
| 67 | struct clk *clk = NULL; | ||
| 68 | struct clk_init_data init; | ||
| 69 | |||
| 70 | if (!parent_name || id > SYSTEM_MAX_ID) | ||
| 71 | return ERR_PTR(-EINVAL); | ||
| 72 | |||
| 73 | sys = kzalloc(sizeof(*sys), GFP_KERNEL); | ||
| 74 | if (!sys) | ||
| 75 | return ERR_PTR(-ENOMEM); | ||
| 76 | |||
| 77 | init.name = name; | ||
| 78 | init.ops = &system_ops; | ||
| 79 | init.parent_names = &parent_name; | ||
| 80 | init.num_parents = 1; | ||
| 81 | /* | ||
| 82 | * CLK_IGNORE_UNUSED is used to avoid ddrck switch off. | ||
| 83 | * TODO : we should implement a driver supporting at91 ddr controller | ||
| 84 | * (see drivers/memory) which would request and enable the ddrck clock. | ||
| 85 | * When this is done we will be able to remove CLK_IGNORE_UNUSED flag. | ||
| 86 | */ | ||
| 87 | init.flags = CLK_IGNORE_UNUSED; | ||
| 88 | |||
| 89 | sys->id = id; | ||
| 90 | sys->hw.init = &init; | ||
| 91 | sys->pmc = pmc; | ||
| 92 | |||
| 93 | clk = clk_register(NULL, &sys->hw); | ||
| 94 | if (IS_ERR(clk)) | ||
| 95 | kfree(sys); | ||
| 96 | |||
| 97 | return clk; | ||
| 98 | } | ||
| 99 | |||
| 100 | static void __init | ||
| 101 | of_at91_clk_sys_setup(struct device_node *np, struct at91_pmc *pmc) | ||
| 102 | { | ||
| 103 | int num; | ||
| 104 | u32 id; | ||
| 105 | struct clk *clk; | ||
| 106 | const char *name; | ||
| 107 | struct device_node *sysclknp; | ||
| 108 | const char *parent_name; | ||
| 109 | |||
| 110 | num = of_get_child_count(np); | ||
| 111 | if (num > (SYSTEM_MAX_ID + 1)) | ||
| 112 | return; | ||
| 113 | |||
| 114 | for_each_child_of_node(np, sysclknp) { | ||
| 115 | if (of_property_read_u32(sysclknp, "reg", &id)) | ||
| 116 | continue; | ||
| 117 | |||
| 118 | if (of_property_read_string(np, "clock-output-names", &name)) | ||
| 119 | name = sysclknp->name; | ||
| 120 | |||
| 121 | parent_name = of_clk_get_parent_name(sysclknp, 0); | ||
| 122 | |||
| 123 | clk = at91_clk_register_system(pmc, name, parent_name, id); | ||
| 124 | if (IS_ERR(clk)) | ||
| 125 | continue; | ||
| 126 | |||
| 127 | of_clk_add_provider(sysclknp, of_clk_src_simple_get, clk); | ||
| 128 | } | ||
| 129 | } | ||
| 130 | |||
| 131 | void __init of_at91rm9200_clk_sys_setup(struct device_node *np, | ||
| 132 | struct at91_pmc *pmc) | ||
| 133 | { | ||
| 134 | of_at91_clk_sys_setup(np, pmc); | ||
| 135 | } | ||
diff --git a/drivers/clk/at91/clk-usb.c b/drivers/clk/at91/clk-usb.c new file mode 100644 index 000000000000..7d1d26a4bd04 --- /dev/null +++ b/drivers/clk/at91/clk-usb.c | |||
| @@ -0,0 +1,398 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; either version 2 of the License, or | ||
| 7 | * (at your option) any later version. | ||
| 8 | * | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/clk-provider.h> | ||
| 12 | #include <linux/clkdev.h> | ||
| 13 | #include <linux/clk/at91_pmc.h> | ||
| 14 | #include <linux/of.h> | ||
| 15 | #include <linux/of_address.h> | ||
| 16 | #include <linux/io.h> | ||
| 17 | |||
| 18 | #include "pmc.h" | ||
| 19 | |||
| 20 | #define USB_SOURCE_MAX 2 | ||
| 21 | |||
| 22 | #define SAM9X5_USB_DIV_SHIFT 8 | ||
| 23 | #define SAM9X5_USB_MAX_DIV 0xf | ||
| 24 | |||
| 25 | #define RM9200_USB_DIV_SHIFT 28 | ||
| 26 | #define RM9200_USB_DIV_TAB_SIZE 4 | ||
| 27 | |||
| 28 | struct at91sam9x5_clk_usb { | ||
| 29 | struct clk_hw hw; | ||
| 30 | struct at91_pmc *pmc; | ||
| 31 | }; | ||
| 32 | |||
| 33 | #define to_at91sam9x5_clk_usb(hw) \ | ||
| 34 | container_of(hw, struct at91sam9x5_clk_usb, hw) | ||
| 35 | |||
| 36 | struct at91rm9200_clk_usb { | ||
| 37 | struct clk_hw hw; | ||
| 38 | struct at91_pmc *pmc; | ||
| 39 | u32 divisors[4]; | ||
| 40 | }; | ||
| 41 | |||
| 42 | #define to_at91rm9200_clk_usb(hw) \ | ||
| 43 | container_of(hw, struct at91rm9200_clk_usb, hw) | ||
| 44 | |||
| 45 | static unsigned long at91sam9x5_clk_usb_recalc_rate(struct clk_hw *hw, | ||
| 46 | unsigned long parent_rate) | ||
| 47 | { | ||
| 48 | u32 tmp; | ||
| 49 | u8 usbdiv; | ||
| 50 | struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw); | ||
| 51 | struct at91_pmc *pmc = usb->pmc; | ||
| 52 | |||
| 53 | tmp = pmc_read(pmc, AT91_PMC_USB); | ||
| 54 | usbdiv = (tmp & AT91_PMC_OHCIUSBDIV) >> SAM9X5_USB_DIV_SHIFT; | ||
| 55 | return parent_rate / (usbdiv + 1); | ||
| 56 | } | ||
| 57 | |||
| 58 | static long at91sam9x5_clk_usb_round_rate(struct clk_hw *hw, unsigned long rate, | ||
| 59 | unsigned long *parent_rate) | ||
| 60 | { | ||
| 61 | unsigned long div; | ||
| 62 | unsigned long bestrate; | ||
| 63 | unsigned long tmp; | ||
| 64 | |||
| 65 | if (rate >= *parent_rate) | ||
| 66 | return *parent_rate; | ||
| 67 | |||
| 68 | div = *parent_rate / rate; | ||
| 69 | if (div >= SAM9X5_USB_MAX_DIV) | ||
| 70 | return *parent_rate / (SAM9X5_USB_MAX_DIV + 1); | ||
| 71 | |||
| 72 | bestrate = *parent_rate / div; | ||
| 73 | tmp = *parent_rate / (div + 1); | ||
| 74 | if (bestrate - rate > rate - tmp) | ||
| 75 | bestrate = tmp; | ||
| 76 | |||
| 77 | return bestrate; | ||
| 78 | } | ||
| 79 | |||
| 80 | static int at91sam9x5_clk_usb_set_parent(struct clk_hw *hw, u8 index) | ||
| 81 | { | ||
| 82 | u32 tmp; | ||
| 83 | struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw); | ||
| 84 | struct at91_pmc *pmc = usb->pmc; | ||
| 85 | |||
| 86 | if (index > 1) | ||
| 87 | return -EINVAL; | ||
| 88 | tmp = pmc_read(pmc, AT91_PMC_USB) & ~AT91_PMC_USBS; | ||
| 89 | if (index) | ||
| 90 | tmp |= AT91_PMC_USBS; | ||
| 91 | pmc_write(pmc, AT91_PMC_USB, tmp); | ||
| 92 | return 0; | ||
| 93 | } | ||
| 94 | |||
| 95 | static u8 at91sam9x5_clk_usb_get_parent(struct clk_hw *hw) | ||
| 96 | { | ||
| 97 | struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw); | ||
| 98 | struct at91_pmc *pmc = usb->pmc; | ||
| 99 | |||
| 100 | return pmc_read(pmc, AT91_PMC_USB) & AT91_PMC_USBS; | ||
| 101 | } | ||
| 102 | |||
| 103 | static int at91sam9x5_clk_usb_set_rate(struct clk_hw *hw, unsigned long rate, | ||
| 104 | unsigned long parent_rate) | ||
| 105 | { | ||
| 106 | u32 tmp; | ||
| 107 | struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw); | ||
| 108 | struct at91_pmc *pmc = usb->pmc; | ||
| 109 | unsigned long div = parent_rate / rate; | ||
| 110 | |||
| 111 | if (parent_rate % rate || div < 1 || div >= SAM9X5_USB_MAX_DIV) | ||
| 112 | return -EINVAL; | ||
| 113 | |||
| 114 | tmp = pmc_read(pmc, AT91_PMC_USB) & ~AT91_PMC_OHCIUSBDIV; | ||
| 115 | tmp |= (div - 1) << SAM9X5_USB_DIV_SHIFT; | ||
| 116 | pmc_write(pmc, AT91_PMC_USB, tmp); | ||
| 117 | |||
| 118 | return 0; | ||
| 119 | } | ||
| 120 | |||
| 121 | static const struct clk_ops at91sam9x5_usb_ops = { | ||
| 122 | .recalc_rate = at91sam9x5_clk_usb_recalc_rate, | ||
| 123 | .round_rate = at91sam9x5_clk_usb_round_rate, | ||
| 124 | .get_parent = at91sam9x5_clk_usb_get_parent, | ||
| 125 | .set_parent = at91sam9x5_clk_usb_set_parent, | ||
| 126 | .set_rate = at91sam9x5_clk_usb_set_rate, | ||
| 127 | }; | ||
| 128 | |||
| 129 | static int at91sam9n12_clk_usb_enable(struct clk_hw *hw) | ||
| 130 | { | ||
| 131 | struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw); | ||
| 132 | struct at91_pmc *pmc = usb->pmc; | ||
| 133 | |||
| 134 | pmc_write(pmc, AT91_PMC_USB, | ||
| 135 | pmc_read(pmc, AT91_PMC_USB) | AT91_PMC_USBS); | ||
| 136 | return 0; | ||
| 137 | } | ||
| 138 | |||
| 139 | static void at91sam9n12_clk_usb_disable(struct clk_hw *hw) | ||
| 140 | { | ||
| 141 | struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw); | ||
| 142 | struct at91_pmc *pmc = usb->pmc; | ||
| 143 | |||
| 144 | pmc_write(pmc, AT91_PMC_USB, | ||
| 145 | pmc_read(pmc, AT91_PMC_USB) & ~AT91_PMC_USBS); | ||
| 146 | } | ||
| 147 | |||
| 148 | static int at91sam9n12_clk_usb_is_enabled(struct clk_hw *hw) | ||
| 149 | { | ||
| 150 | struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw); | ||
| 151 | struct at91_pmc *pmc = usb->pmc; | ||
| 152 | |||
| 153 | return !!(pmc_read(pmc, AT91_PMC_USB) & AT91_PMC_USBS); | ||
| 154 | } | ||
| 155 | |||
| 156 | static const struct clk_ops at91sam9n12_usb_ops = { | ||
| 157 | .enable = at91sam9n12_clk_usb_enable, | ||
| 158 | .disable = at91sam9n12_clk_usb_disable, | ||
| 159 | .is_enabled = at91sam9n12_clk_usb_is_enabled, | ||
| 160 | .recalc_rate = at91sam9x5_clk_usb_recalc_rate, | ||
| 161 | .round_rate = at91sam9x5_clk_usb_round_rate, | ||
| 162 | .set_rate = at91sam9x5_clk_usb_set_rate, | ||
| 163 | }; | ||
| 164 | |||
| 165 | static struct clk * __init | ||
| 166 | at91sam9x5_clk_register_usb(struct at91_pmc *pmc, const char *name, | ||
| 167 | const char **parent_names, u8 num_parents) | ||
| 168 | { | ||
| 169 | struct at91sam9x5_clk_usb *usb; | ||
| 170 | struct clk *clk = NULL; | ||
| 171 | struct clk_init_data init; | ||
| 172 | |||
| 173 | usb = kzalloc(sizeof(*usb), GFP_KERNEL); | ||
| 174 | if (!usb) | ||
| 175 | return ERR_PTR(-ENOMEM); | ||
| 176 | |||
| 177 | init.name = name; | ||
| 178 | init.ops = &at91sam9x5_usb_ops; | ||
| 179 | init.parent_names = parent_names; | ||
| 180 | init.num_parents = num_parents; | ||
| 181 | init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE; | ||
| 182 | |||
| 183 | usb->hw.init = &init; | ||
| 184 | usb->pmc = pmc; | ||
| 185 | |||
| 186 | clk = clk_register(NULL, &usb->hw); | ||
| 187 | if (IS_ERR(clk)) | ||
| 188 | kfree(usb); | ||
| 189 | |||
| 190 | return clk; | ||
| 191 | } | ||
| 192 | |||
| 193 | static struct clk * __init | ||
| 194 | at91sam9n12_clk_register_usb(struct at91_pmc *pmc, const char *name, | ||
| 195 | const char *parent_name) | ||
| 196 | { | ||
| 197 | struct at91sam9x5_clk_usb *usb; | ||
| 198 | struct clk *clk = NULL; | ||
| 199 | struct clk_init_data init; | ||
| 200 | |||
| 201 | usb = kzalloc(sizeof(*usb), GFP_KERNEL); | ||
| 202 | if (!usb) | ||
| 203 | return ERR_PTR(-ENOMEM); | ||
| 204 | |||
| 205 | init.name = name; | ||
| 206 | init.ops = &at91sam9n12_usb_ops; | ||
| 207 | init.parent_names = &parent_name; | ||
| 208 | init.num_parents = 1; | ||
| 209 | init.flags = CLK_SET_RATE_GATE; | ||
| 210 | |||
| 211 | usb->hw.init = &init; | ||
| 212 | usb->pmc = pmc; | ||
| 213 | |||
| 214 | clk = clk_register(NULL, &usb->hw); | ||
| 215 | if (IS_ERR(clk)) | ||
| 216 | kfree(usb); | ||
| 217 | |||
| 218 | return clk; | ||
| 219 | } | ||
| 220 | |||
| 221 | static unsigned long at91rm9200_clk_usb_recalc_rate(struct clk_hw *hw, | ||
| 222 | unsigned long parent_rate) | ||
| 223 | { | ||
| 224 | struct at91rm9200_clk_usb *usb = to_at91rm9200_clk_usb(hw); | ||
| 225 | struct at91_pmc *pmc = usb->pmc; | ||
| 226 | u32 tmp; | ||
| 227 | u8 usbdiv; | ||
| 228 | |||
| 229 | tmp = pmc_read(pmc, AT91_CKGR_PLLBR); | ||
| 230 | usbdiv = (tmp & AT91_PMC_USBDIV) >> RM9200_USB_DIV_SHIFT; | ||
| 231 | if (usb->divisors[usbdiv]) | ||
| 232 | return parent_rate / usb->divisors[usbdiv]; | ||
| 233 | |||
| 234 | return 0; | ||
| 235 | } | ||
| 236 | |||
| 237 | static long at91rm9200_clk_usb_round_rate(struct clk_hw *hw, unsigned long rate, | ||
| 238 | unsigned long *parent_rate) | ||
| 239 | { | ||
| 240 | struct at91rm9200_clk_usb *usb = to_at91rm9200_clk_usb(hw); | ||
| 241 | unsigned long bestrate = 0; | ||
| 242 | int bestdiff = -1; | ||
| 243 | unsigned long tmprate; | ||
| 244 | int tmpdiff; | ||
| 245 | int i = 0; | ||
| 246 | |||
| 247 | for (i = 0; i < 4; i++) { | ||
| 248 | if (!usb->divisors[i]) | ||
| 249 | continue; | ||
| 250 | tmprate = *parent_rate / usb->divisors[i]; | ||
| 251 | if (tmprate < rate) | ||
| 252 | tmpdiff = rate - tmprate; | ||
| 253 | else | ||
| 254 | tmpdiff = tmprate - rate; | ||
| 255 | |||
| 256 | if (bestdiff < 0 || bestdiff > tmpdiff) { | ||
| 257 | bestrate = tmprate; | ||
| 258 | bestdiff = tmpdiff; | ||
| 259 | } | ||
| 260 | |||
| 261 | if (!bestdiff) | ||
| 262 | break; | ||
| 263 | } | ||
| 264 | |||
| 265 | return bestrate; | ||
| 266 | } | ||
| 267 | |||
| 268 | static int at91rm9200_clk_usb_set_rate(struct clk_hw *hw, unsigned long rate, | ||
| 269 | unsigned long parent_rate) | ||
| 270 | { | ||
| 271 | u32 tmp; | ||
| 272 | int i; | ||
| 273 | struct at91rm9200_clk_usb *usb = to_at91rm9200_clk_usb(hw); | ||
| 274 | struct at91_pmc *pmc = usb->pmc; | ||
| 275 | unsigned long div = parent_rate / rate; | ||
| 276 | |||
| 277 | if (parent_rate % rate) | ||
| 278 | return -EINVAL; | ||
| 279 | for (i = 0; i < RM9200_USB_DIV_TAB_SIZE; i++) { | ||
| 280 | if (usb->divisors[i] == div) { | ||
| 281 | tmp = pmc_read(pmc, AT91_CKGR_PLLBR) & | ||
| 282 | ~AT91_PMC_USBDIV; | ||
| 283 | tmp |= i << RM9200_USB_DIV_SHIFT; | ||
| 284 | pmc_write(pmc, AT91_CKGR_PLLBR, tmp); | ||
| 285 | return 0; | ||
| 286 | } | ||
| 287 | } | ||
| 288 | |||
| 289 | return -EINVAL; | ||
| 290 | } | ||
| 291 | |||
| 292 | static const struct clk_ops at91rm9200_usb_ops = { | ||
| 293 | .recalc_rate = at91rm9200_clk_usb_recalc_rate, | ||
| 294 | .round_rate = at91rm9200_clk_usb_round_rate, | ||
| 295 | .set_rate = at91rm9200_clk_usb_set_rate, | ||
| 296 | }; | ||
| 297 | |||
| 298 | static struct clk * __init | ||
| 299 | at91rm9200_clk_register_usb(struct at91_pmc *pmc, const char *name, | ||
| 300 | const char *parent_name, const u32 *divisors) | ||
| 301 | { | ||
| 302 | struct at91rm9200_clk_usb *usb; | ||
| 303 | struct clk *clk = NULL; | ||
| 304 | struct clk_init_data init; | ||
| 305 | |||
| 306 | usb = kzalloc(sizeof(*usb), GFP_KERNEL); | ||
| 307 | if (!usb) | ||
| 308 | return ERR_PTR(-ENOMEM); | ||
| 309 | |||
| 310 | init.name = name; | ||
| 311 | init.ops = &at91rm9200_usb_ops; | ||
| 312 | init.parent_names = &parent_name; | ||
| 313 | init.num_parents = 1; | ||
| 314 | init.flags = 0; | ||
| 315 | |||
| 316 | usb->hw.init = &init; | ||
| 317 | usb->pmc = pmc; | ||
| 318 | memcpy(usb->divisors, divisors, sizeof(usb->divisors)); | ||
| 319 | |||
| 320 | clk = clk_register(NULL, &usb->hw); | ||
| 321 | if (IS_ERR(clk)) | ||
| 322 | kfree(usb); | ||
| 323 | |||
| 324 | return clk; | ||
| 325 | } | ||
| 326 | |||
| 327 | void __init of_at91sam9x5_clk_usb_setup(struct device_node *np, | ||
| 328 | struct at91_pmc *pmc) | ||
| 329 | { | ||
| 330 | struct clk *clk; | ||
| 331 | int i; | ||
| 332 | int num_parents; | ||
| 333 | const char *parent_names[USB_SOURCE_MAX]; | ||
| 334 | const char *name = np->name; | ||
| 335 | |||
| 336 | num_parents = of_count_phandle_with_args(np, "clocks", "#clock-cells"); | ||
| 337 | if (num_parents <= 0 || num_parents > USB_SOURCE_MAX) | ||
| 338 | return; | ||
| 339 | |||
| 340 | for (i = 0; i < num_parents; i++) { | ||
| 341 | parent_names[i] = of_clk_get_parent_name(np, i); | ||
| 342 | if (!parent_names[i]) | ||
| 343 | return; | ||
| 344 | } | ||
| 345 | |||
| 346 | of_property_read_string(np, "clock-output-names", &name); | ||
| 347 | |||
| 348 | clk = at91sam9x5_clk_register_usb(pmc, name, parent_names, num_parents); | ||
| 349 | if (IS_ERR(clk)) | ||
| 350 | return; | ||
| 351 | |||
| 352 | of_clk_add_provider(np, of_clk_src_simple_get, clk); | ||
| 353 | } | ||
| 354 | |||
| 355 | void __init of_at91sam9n12_clk_usb_setup(struct device_node *np, | ||
| 356 | struct at91_pmc *pmc) | ||
| 357 | { | ||
| 358 | struct clk *clk; | ||
| 359 | const char *parent_name; | ||
| 360 | const char *name = np->name; | ||
| 361 | |||
| 362 | parent_name = of_clk_get_parent_name(np, 0); | ||
| 363 | if (!parent_name) | ||
| 364 | return; | ||
| 365 | |||
| 366 | of_property_read_string(np, "clock-output-names", &name); | ||
| 367 | |||
| 368 | clk = at91sam9n12_clk_register_usb(pmc, name, parent_name); | ||
| 369 | if (IS_ERR(clk)) | ||
| 370 | return; | ||
| 371 | |||
| 372 | of_clk_add_provider(np, of_clk_src_simple_get, clk); | ||
| 373 | } | ||
| 374 | |||
| 375 | void __init of_at91rm9200_clk_usb_setup(struct device_node *np, | ||
| 376 | struct at91_pmc *pmc) | ||
| 377 | { | ||
| 378 | struct clk *clk; | ||
| 379 | const char *parent_name; | ||
| 380 | const char *name = np->name; | ||
| 381 | u32 divisors[4] = {0, 0, 0, 0}; | ||
| 382 | |||
| 383 | parent_name = of_clk_get_parent_name(np, 0); | ||
| 384 | if (!parent_name) | ||
| 385 | return; | ||
| 386 | |||
| 387 | of_property_read_u32_array(np, "atmel,clk-divisors", divisors, 4); | ||
| 388 | if (!divisors[0]) | ||
| 389 | return; | ||
| 390 | |||
| 391 | of_property_read_string(np, "clock-output-names", &name); | ||
| 392 | |||
| 393 | clk = at91rm9200_clk_register_usb(pmc, name, parent_name, divisors); | ||
| 394 | if (IS_ERR(clk)) | ||
| 395 | return; | ||
| 396 | |||
| 397 | of_clk_add_provider(np, of_clk_src_simple_get, clk); | ||
| 398 | } | ||
diff --git a/drivers/clk/at91/clk-utmi.c b/drivers/clk/at91/clk-utmi.c new file mode 100644 index 000000000000..ae3263bc1476 --- /dev/null +++ b/drivers/clk/at91/clk-utmi.c | |||
| @@ -0,0 +1,159 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; either version 2 of the License, or | ||
| 7 | * (at your option) any later version. | ||
| 8 | * | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/clk-provider.h> | ||
| 12 | #include <linux/clkdev.h> | ||
| 13 | #include <linux/clk/at91_pmc.h> | ||
| 14 | #include <linux/interrupt.h> | ||
| 15 | #include <linux/irq.h> | ||
| 16 | #include <linux/of.h> | ||
| 17 | #include <linux/of_address.h> | ||
| 18 | #include <linux/of_irq.h> | ||
| 19 | #include <linux/io.h> | ||
| 20 | #include <linux/sched.h> | ||
| 21 | #include <linux/wait.h> | ||
| 22 | |||
| 23 | #include "pmc.h" | ||
| 24 | |||
| 25 | #define UTMI_FIXED_MUL 40 | ||
| 26 | |||
| 27 | struct clk_utmi { | ||
| 28 | struct clk_hw hw; | ||
| 29 | struct at91_pmc *pmc; | ||
| 30 | unsigned int irq; | ||
| 31 | wait_queue_head_t wait; | ||
| 32 | }; | ||
| 33 | |||
| 34 | #define to_clk_utmi(hw) container_of(hw, struct clk_utmi, hw) | ||
| 35 | |||
| 36 | static irqreturn_t clk_utmi_irq_handler(int irq, void *dev_id) | ||
| 37 | { | ||
| 38 | struct clk_utmi *utmi = (struct clk_utmi *)dev_id; | ||
| 39 | |||
| 40 | wake_up(&utmi->wait); | ||
| 41 | disable_irq_nosync(utmi->irq); | ||
| 42 | |||
| 43 | return IRQ_HANDLED; | ||
| 44 | } | ||
| 45 | |||
| 46 | static int clk_utmi_prepare(struct clk_hw *hw) | ||
| 47 | { | ||
| 48 | struct clk_utmi *utmi = to_clk_utmi(hw); | ||
| 49 | struct at91_pmc *pmc = utmi->pmc; | ||
| 50 | u32 tmp = at91_pmc_read(AT91_CKGR_UCKR) | AT91_PMC_UPLLEN | | ||
| 51 | AT91_PMC_UPLLCOUNT | AT91_PMC_BIASEN; | ||
| 52 | |||
| 53 | pmc_write(pmc, AT91_CKGR_UCKR, tmp); | ||
| 54 | |||
| 55 | while (!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_LOCKU)) { | ||
| 56 | enable_irq(utmi->irq); | ||
| 57 | wait_event(utmi->wait, | ||
| 58 | pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_LOCKU); | ||
| 59 | } | ||
| 60 | |||
| 61 | return 0; | ||
| 62 | } | ||
| 63 | |||
| 64 | static int clk_utmi_is_prepared(struct clk_hw *hw) | ||
| 65 | { | ||
| 66 | struct clk_utmi *utmi = to_clk_utmi(hw); | ||
| 67 | struct at91_pmc *pmc = utmi->pmc; | ||
| 68 | |||
| 69 | return !!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_LOCKU); | ||
| 70 | } | ||
| 71 | |||
| 72 | static void clk_utmi_unprepare(struct clk_hw *hw) | ||
| 73 | { | ||
| 74 | struct clk_utmi *utmi = to_clk_utmi(hw); | ||
| 75 | struct at91_pmc *pmc = utmi->pmc; | ||
| 76 | u32 tmp = at91_pmc_read(AT91_CKGR_UCKR) & ~AT91_PMC_UPLLEN; | ||
| 77 | |||
| 78 | pmc_write(pmc, AT91_CKGR_UCKR, tmp); | ||
| 79 | } | ||
| 80 | |||
| 81 | static unsigned long clk_utmi_recalc_rate(struct clk_hw *hw, | ||
| 82 | unsigned long parent_rate) | ||
| 83 | { | ||
| 84 | /* UTMI clk is a fixed clk multiplier */ | ||
| 85 | return parent_rate * UTMI_FIXED_MUL; | ||
| 86 | } | ||
| 87 | |||
| 88 | static const struct clk_ops utmi_ops = { | ||
| 89 | .prepare = clk_utmi_prepare, | ||
| 90 | .unprepare = clk_utmi_unprepare, | ||
| 91 | .is_prepared = clk_utmi_is_prepared, | ||
| 92 | .recalc_rate = clk_utmi_recalc_rate, | ||
| 93 | }; | ||
| 94 | |||
| 95 | static struct clk * __init | ||
| 96 | at91_clk_register_utmi(struct at91_pmc *pmc, unsigned int irq, | ||
| 97 | const char *name, const char *parent_name) | ||
| 98 | { | ||
| 99 | int ret; | ||
| 100 | struct clk_utmi *utmi; | ||
| 101 | struct clk *clk = NULL; | ||
| 102 | struct clk_init_data init; | ||
| 103 | |||
| 104 | utmi = kzalloc(sizeof(*utmi), GFP_KERNEL); | ||
| 105 | if (!utmi) | ||
| 106 | return ERR_PTR(-ENOMEM); | ||
| 107 | |||
| 108 | init.name = name; | ||
| 109 | init.ops = &utmi_ops; | ||
| 110 | init.parent_names = parent_name ? &parent_name : NULL; | ||
| 111 | init.num_parents = parent_name ? 1 : 0; | ||
| 112 | init.flags = CLK_SET_RATE_GATE; | ||
| 113 | |||
| 114 | utmi->hw.init = &init; | ||
| 115 | utmi->pmc = pmc; | ||
| 116 | utmi->irq = irq; | ||
| 117 | init_waitqueue_head(&utmi->wait); | ||
| 118 | irq_set_status_flags(utmi->irq, IRQ_NOAUTOEN); | ||
| 119 | ret = request_irq(utmi->irq, clk_utmi_irq_handler, | ||
| 120 | IRQF_TRIGGER_HIGH, "clk-utmi", utmi); | ||
| 121 | if (ret) | ||
| 122 | return ERR_PTR(ret); | ||
| 123 | |||
| 124 | clk = clk_register(NULL, &utmi->hw); | ||
| 125 | if (IS_ERR(clk)) | ||
| 126 | kfree(utmi); | ||
| 127 | |||
| 128 | return clk; | ||
| 129 | } | ||
| 130 | |||
| 131 | static void __init | ||
| 132 | of_at91_clk_utmi_setup(struct device_node *np, struct at91_pmc *pmc) | ||
| 133 | { | ||
| 134 | unsigned int irq; | ||
| 135 | struct clk *clk; | ||
| 136 | const char *parent_name; | ||
| 137 | const char *name = np->name; | ||
| 138 | |||
| 139 | parent_name = of_clk_get_parent_name(np, 0); | ||
| 140 | |||
| 141 | of_property_read_string(np, "clock-output-names", &name); | ||
| 142 | |||
| 143 | irq = irq_of_parse_and_map(np, 0); | ||
| 144 | if (!irq) | ||
| 145 | return; | ||
| 146 | |||
| 147 | clk = at91_clk_register_utmi(pmc, irq, name, parent_name); | ||
| 148 | if (IS_ERR(clk)) | ||
| 149 | return; | ||
| 150 | |||
| 151 | of_clk_add_provider(np, of_clk_src_simple_get, clk); | ||
| 152 | return; | ||
| 153 | } | ||
| 154 | |||
| 155 | void __init of_at91sam9x5_clk_utmi_setup(struct device_node *np, | ||
| 156 | struct at91_pmc *pmc) | ||
| 157 | { | ||
| 158 | of_at91_clk_utmi_setup(np, pmc); | ||
| 159 | } | ||
diff --git a/drivers/clk/at91/pmc.c b/drivers/clk/at91/pmc.c new file mode 100644 index 000000000000..7b9db603b936 --- /dev/null +++ b/drivers/clk/at91/pmc.c | |||
| @@ -0,0 +1,397 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; either version 2 of the License, or | ||
| 7 | * (at your option) any later version. | ||
| 8 | * | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/clk-provider.h> | ||
| 12 | #include <linux/clkdev.h> | ||
| 13 | #include <linux/clk/at91_pmc.h> | ||
| 14 | #include <linux/of.h> | ||
| 15 | #include <linux/of_address.h> | ||
| 16 | #include <linux/io.h> | ||
| 17 | #include <linux/interrupt.h> | ||
| 18 | #include <linux/irq.h> | ||
| 19 | #include <linux/irqchip/chained_irq.h> | ||
| 20 | #include <linux/irqdomain.h> | ||
| 21 | #include <linux/of_irq.h> | ||
| 22 | |||
| 23 | #include <asm/proc-fns.h> | ||
| 24 | |||
| 25 | #include "pmc.h" | ||
| 26 | |||
| 27 | void __iomem *at91_pmc_base; | ||
| 28 | EXPORT_SYMBOL_GPL(at91_pmc_base); | ||
| 29 | |||
| 30 | void at91sam9_idle(void) | ||
| 31 | { | ||
| 32 | at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK); | ||
| 33 | cpu_do_idle(); | ||
| 34 | } | ||
| 35 | |||
| 36 | int of_at91_get_clk_range(struct device_node *np, const char *propname, | ||
| 37 | struct clk_range *range) | ||
| 38 | { | ||
| 39 | u32 min, max; | ||
| 40 | int ret; | ||
| 41 | |||
| 42 | ret = of_property_read_u32_index(np, propname, 0, &min); | ||
| 43 | if (ret) | ||
| 44 | return ret; | ||
| 45 | |||
| 46 | ret = of_property_read_u32_index(np, propname, 1, &max); | ||
| 47 | if (ret) | ||
| 48 | return ret; | ||
| 49 | |||
| 50 | if (range) { | ||
| 51 | range->min = min; | ||
| 52 | range->max = max; | ||
| 53 | } | ||
| 54 | |||
| 55 | return 0; | ||
| 56 | } | ||
| 57 | EXPORT_SYMBOL_GPL(of_at91_get_clk_range); | ||
| 58 | |||
| 59 | static void pmc_irq_mask(struct irq_data *d) | ||
| 60 | { | ||
| 61 | struct at91_pmc *pmc = irq_data_get_irq_chip_data(d); | ||
| 62 | |||
| 63 | pmc_write(pmc, AT91_PMC_IDR, 1 << d->hwirq); | ||
| 64 | } | ||
| 65 | |||
| 66 | static void pmc_irq_unmask(struct irq_data *d) | ||
| 67 | { | ||
| 68 | struct at91_pmc *pmc = irq_data_get_irq_chip_data(d); | ||
| 69 | |||
| 70 | pmc_write(pmc, AT91_PMC_IER, 1 << d->hwirq); | ||
| 71 | } | ||
| 72 | |||
| 73 | static int pmc_irq_set_type(struct irq_data *d, unsigned type) | ||
| 74 | { | ||
| 75 | if (type != IRQ_TYPE_LEVEL_HIGH) { | ||
| 76 | pr_warn("PMC: type not supported (support only IRQ_TYPE_LEVEL_HIGH type)\n"); | ||
| 77 | return -EINVAL; | ||
| 78 | } | ||
| 79 | |||
| 80 | return 0; | ||
| 81 | } | ||
| 82 | |||
| 83 | static struct irq_chip pmc_irq = { | ||
| 84 | .name = "PMC", | ||
| 85 | .irq_disable = pmc_irq_mask, | ||
| 86 | .irq_mask = pmc_irq_mask, | ||
| 87 | .irq_unmask = pmc_irq_unmask, | ||
| 88 | .irq_set_type = pmc_irq_set_type, | ||
| 89 | }; | ||
| 90 | |||
| 91 | static struct lock_class_key pmc_lock_class; | ||
| 92 | |||
| 93 | static int pmc_irq_map(struct irq_domain *h, unsigned int virq, | ||
| 94 | irq_hw_number_t hw) | ||
| 95 | { | ||
| 96 | struct at91_pmc *pmc = h->host_data; | ||
| 97 | |||
| 98 | irq_set_lockdep_class(virq, &pmc_lock_class); | ||
| 99 | |||
| 100 | irq_set_chip_and_handler(virq, &pmc_irq, | ||
| 101 | handle_level_irq); | ||
| 102 | set_irq_flags(virq, IRQF_VALID); | ||
| 103 | irq_set_chip_data(virq, pmc); | ||
| 104 | |||
| 105 | return 0; | ||
| 106 | } | ||
| 107 | |||
| 108 | static int pmc_irq_domain_xlate(struct irq_domain *d, | ||
| 109 | struct device_node *ctrlr, | ||
| 110 | const u32 *intspec, unsigned int intsize, | ||
| 111 | irq_hw_number_t *out_hwirq, | ||
| 112 | unsigned int *out_type) | ||
| 113 | { | ||
| 114 | struct at91_pmc *pmc = d->host_data; | ||
| 115 | const struct at91_pmc_caps *caps = pmc->caps; | ||
| 116 | |||
| 117 | if (WARN_ON(intsize < 1)) | ||
| 118 | return -EINVAL; | ||
| 119 | |||
| 120 | *out_hwirq = intspec[0]; | ||
| 121 | |||
| 122 | if (!(caps->available_irqs & (1 << *out_hwirq))) | ||
| 123 | return -EINVAL; | ||
| 124 | |||
| 125 | *out_type = IRQ_TYPE_LEVEL_HIGH; | ||
| 126 | |||
| 127 | return 0; | ||
| 128 | } | ||
| 129 | |||
| 130 | static struct irq_domain_ops pmc_irq_ops = { | ||
| 131 | .map = pmc_irq_map, | ||
| 132 | .xlate = pmc_irq_domain_xlate, | ||
| 133 | }; | ||
| 134 | |||
| 135 | static irqreturn_t pmc_irq_handler(int irq, void *data) | ||
| 136 | { | ||
| 137 | struct at91_pmc *pmc = (struct at91_pmc *)data; | ||
| 138 | unsigned long sr; | ||
| 139 | int n; | ||
| 140 | |||
| 141 | sr = pmc_read(pmc, AT91_PMC_SR) & pmc_read(pmc, AT91_PMC_IMR); | ||
| 142 | if (!sr) | ||
| 143 | return IRQ_NONE; | ||
| 144 | |||
| 145 | for_each_set_bit(n, &sr, BITS_PER_LONG) | ||
| 146 | generic_handle_irq(irq_find_mapping(pmc->irqdomain, n)); | ||
| 147 | |||
| 148 | return IRQ_HANDLED; | ||
| 149 | } | ||
| 150 | |||
| 151 | static const struct at91_pmc_caps at91rm9200_caps = { | ||
| 152 | .available_irqs = AT91_PMC_MOSCS | AT91_PMC_LOCKA | AT91_PMC_LOCKB | | ||
| 153 | AT91_PMC_MCKRDY | AT91_PMC_PCK0RDY | | ||
| 154 | AT91_PMC_PCK1RDY | AT91_PMC_PCK2RDY | | ||
| 155 | AT91_PMC_PCK3RDY, | ||
| 156 | }; | ||
| 157 | |||
| 158 | static const struct at91_pmc_caps at91sam9260_caps = { | ||
| 159 | .available_irqs = AT91_PMC_MOSCS | AT91_PMC_LOCKA | AT91_PMC_LOCKB | | ||
| 160 | AT91_PMC_MCKRDY | AT91_PMC_PCK0RDY | | ||
| 161 | AT91_PMC_PCK1RDY, | ||
| 162 | }; | ||
| 163 | |||
| 164 | static const struct at91_pmc_caps at91sam9g45_caps = { | ||
| 165 | .available_irqs = AT91_PMC_MOSCS | AT91_PMC_LOCKA | AT91_PMC_MCKRDY | | ||
| 166 | AT91_PMC_LOCKU | AT91_PMC_PCK0RDY | | ||
| 167 | AT91_PMC_PCK1RDY, | ||
| 168 | }; | ||
| 169 | |||
| 170 | static const struct at91_pmc_caps at91sam9n12_caps = { | ||
| 171 | .available_irqs = AT91_PMC_MOSCS | AT91_PMC_LOCKA | AT91_PMC_LOCKB | | ||
| 172 | AT91_PMC_MCKRDY | AT91_PMC_PCK0RDY | | ||
| 173 | AT91_PMC_PCK1RDY | AT91_PMC_MOSCSELS | | ||
| 174 | AT91_PMC_MOSCRCS | AT91_PMC_CFDEV, | ||
| 175 | }; | ||
| 176 | |||
| 177 | static const struct at91_pmc_caps at91sam9x5_caps = { | ||
| 178 | .available_irqs = AT91_PMC_MOSCS | AT91_PMC_LOCKA | AT91_PMC_MCKRDY | | ||
| 179 | AT91_PMC_LOCKU | AT91_PMC_PCK0RDY | | ||
| 180 | AT91_PMC_PCK1RDY | AT91_PMC_MOSCSELS | | ||
| 181 | AT91_PMC_MOSCRCS | AT91_PMC_CFDEV, | ||
| 182 | }; | ||
| 183 | |||
| 184 | static const struct at91_pmc_caps sama5d3_caps = { | ||
| 185 | .available_irqs = AT91_PMC_MOSCS | AT91_PMC_LOCKA | AT91_PMC_MCKRDY | | ||
| 186 | AT91_PMC_LOCKU | AT91_PMC_PCK0RDY | | ||
| 187 | AT91_PMC_PCK1RDY | AT91_PMC_PCK2RDY | | ||
| 188 | AT91_PMC_MOSCSELS | AT91_PMC_MOSCRCS | | ||
| 189 | AT91_PMC_CFDEV, | ||
| 190 | }; | ||
| 191 | |||
| 192 | static struct at91_pmc *__init at91_pmc_init(struct device_node *np, | ||
| 193 | void __iomem *regbase, int virq, | ||
| 194 | const struct at91_pmc_caps *caps) | ||
| 195 | { | ||
| 196 | struct at91_pmc *pmc; | ||
| 197 | |||
| 198 | if (!regbase || !virq || !caps) | ||
| 199 | return NULL; | ||
| 200 | |||
| 201 | at91_pmc_base = regbase; | ||
| 202 | |||
| 203 | pmc = kzalloc(sizeof(*pmc), GFP_KERNEL); | ||
| 204 | if (!pmc) | ||
| 205 | return NULL; | ||
| 206 | |||
| 207 | spin_lock_init(&pmc->lock); | ||
| 208 | pmc->regbase = regbase; | ||
| 209 | pmc->virq = virq; | ||
| 210 | pmc->caps = caps; | ||
| 211 | |||
| 212 | pmc->irqdomain = irq_domain_add_linear(np, 32, &pmc_irq_ops, pmc); | ||
| 213 | |||
| 214 | if (!pmc->irqdomain) | ||
| 215 | goto out_free_pmc; | ||
| 216 | |||
| 217 | pmc_write(pmc, AT91_PMC_IDR, 0xffffffff); | ||
| 218 | if (request_irq(pmc->virq, pmc_irq_handler, IRQF_SHARED, "pmc", pmc)) | ||
| 219 | goto out_remove_irqdomain; | ||
| 220 | |||
| 221 | return pmc; | ||
| 222 | |||
| 223 | out_remove_irqdomain: | ||
| 224 | irq_domain_remove(pmc->irqdomain); | ||
| 225 | out_free_pmc: | ||
| 226 | kfree(pmc); | ||
| 227 | |||
| 228 | return NULL; | ||
| 229 | } | ||
| 230 | |||
| 231 | static const struct of_device_id pmc_clk_ids[] __initdata = { | ||
| 232 | /* Main clock */ | ||
| 233 | { | ||
| 234 | .compatible = "atmel,at91rm9200-clk-main", | ||
| 235 | .data = of_at91rm9200_clk_main_setup, | ||
| 236 | }, | ||
| 237 | /* PLL clocks */ | ||
| 238 | { | ||
| 239 | .compatible = "atmel,at91rm9200-clk-pll", | ||
| 240 | .data = of_at91rm9200_clk_pll_setup, | ||
| 241 | }, | ||
| 242 | { | ||
| 243 | .compatible = "atmel,at91sam9g45-clk-pll", | ||
| 244 | .data = of_at91sam9g45_clk_pll_setup, | ||
| 245 | }, | ||
| 246 | { | ||
| 247 | .compatible = "atmel,at91sam9g20-clk-pllb", | ||
| 248 | .data = of_at91sam9g20_clk_pllb_setup, | ||
| 249 | }, | ||
| 250 | { | ||
| 251 | .compatible = "atmel,sama5d3-clk-pll", | ||
| 252 | .data = of_sama5d3_clk_pll_setup, | ||
| 253 | }, | ||
| 254 | { | ||
| 255 | .compatible = "atmel,at91sam9x5-clk-plldiv", | ||
| 256 | .data = of_at91sam9x5_clk_plldiv_setup, | ||
| 257 | }, | ||
| 258 | /* Master clock */ | ||
| 259 | { | ||
| 260 | .compatible = "atmel,at91rm9200-clk-master", | ||
| 261 | .data = of_at91rm9200_clk_master_setup, | ||
| 262 | }, | ||
| 263 | { | ||
| 264 | .compatible = "atmel,at91sam9x5-clk-master", | ||
| 265 | .data = of_at91sam9x5_clk_master_setup, | ||
| 266 | }, | ||
| 267 | /* System clocks */ | ||
| 268 | { | ||
| 269 | .compatible = "atmel,at91rm9200-clk-system", | ||
| 270 | .data = of_at91rm9200_clk_sys_setup, | ||
| 271 | }, | ||
| 272 | /* Peripheral clocks */ | ||
| 273 | { | ||
| 274 | .compatible = "atmel,at91rm9200-clk-peripheral", | ||
| 275 | .data = of_at91rm9200_clk_periph_setup, | ||
| 276 | }, | ||
| 277 | { | ||
| 278 | .compatible = "atmel,at91sam9x5-clk-peripheral", | ||
| 279 | .data = of_at91sam9x5_clk_periph_setup, | ||
| 280 | }, | ||
| 281 | /* Programmable clocks */ | ||
| 282 | #if defined(CONFIG_AT91_PROGRAMMABLE_CLOCKS) | ||
| 283 | { | ||
| 284 | .compatible = "atmel,at91rm9200-clk-programmable", | ||
| 285 | .data = of_at91rm9200_clk_prog_setup, | ||
| 286 | }, | ||
| 287 | { | ||
| 288 | .compatible = "atmel,at91sam9g45-clk-programmable", | ||
| 289 | .data = of_at91sam9g45_clk_prog_setup, | ||
| 290 | }, | ||
| 291 | { | ||
| 292 | .compatible = "atmel,at91sam9x5-clk-programmable", | ||
| 293 | .data = of_at91sam9x5_clk_prog_setup, | ||
| 294 | }, | ||
| 295 | #endif | ||
| 296 | /* UTMI clock */ | ||
| 297 | #if defined(CONFIG_HAVE_AT91_UTMI) | ||
| 298 | { | ||
| 299 | .compatible = "atmel,at91sam9x5-clk-utmi", | ||
| 300 | .data = of_at91sam9x5_clk_utmi_setup, | ||
| 301 | }, | ||
| 302 | #endif | ||
| 303 | /* USB clock */ | ||
| 304 | #if defined(CONFIG_HAVE_AT91_USB_CLK) | ||
| 305 | { | ||
| 306 | .compatible = "atmel,at91rm9200-clk-usb", | ||
| 307 | .data = of_at91rm9200_clk_usb_setup, | ||
| 308 | }, | ||
| 309 | { | ||
| 310 | .compatible = "atmel,at91sam9x5-clk-usb", | ||
| 311 | .data = of_at91sam9x5_clk_usb_setup, | ||
| 312 | }, | ||
| 313 | { | ||
| 314 | .compatible = "atmel,at91sam9n12-clk-usb", | ||
| 315 | .data = of_at91sam9n12_clk_usb_setup, | ||
| 316 | }, | ||
| 317 | #endif | ||
| 318 | /* SMD clock */ | ||
| 319 | #if defined(CONFIG_HAVE_AT91_SMD) | ||
| 320 | { | ||
| 321 | .compatible = "atmel,at91sam9x5-clk-smd", | ||
| 322 | .data = of_at91sam9x5_clk_smd_setup, | ||
| 323 | }, | ||
| 324 | #endif | ||
| 325 | { /*sentinel*/ } | ||
| 326 | }; | ||
| 327 | |||
| 328 | static void __init of_at91_pmc_setup(struct device_node *np, | ||
| 329 | const struct at91_pmc_caps *caps) | ||
| 330 | { | ||
| 331 | struct at91_pmc *pmc; | ||
| 332 | struct device_node *childnp; | ||
| 333 | void (*clk_setup)(struct device_node *, struct at91_pmc *); | ||
| 334 | const struct of_device_id *clk_id; | ||
| 335 | void __iomem *regbase = of_iomap(np, 0); | ||
| 336 | int virq; | ||
| 337 | |||
| 338 | if (!regbase) | ||
| 339 | return; | ||
| 340 | |||
| 341 | virq = irq_of_parse_and_map(np, 0); | ||
| 342 | if (!virq) | ||
| 343 | return; | ||
| 344 | |||
| 345 | pmc = at91_pmc_init(np, regbase, virq, caps); | ||
| 346 | if (!pmc) | ||
| 347 | return; | ||
| 348 | for_each_child_of_node(np, childnp) { | ||
| 349 | clk_id = of_match_node(pmc_clk_ids, childnp); | ||
| 350 | if (!clk_id) | ||
| 351 | continue; | ||
| 352 | clk_setup = clk_id->data; | ||
| 353 | clk_setup(childnp, pmc); | ||
| 354 | } | ||
| 355 | } | ||
| 356 | |||
| 357 | static void __init of_at91rm9200_pmc_setup(struct device_node *np) | ||
| 358 | { | ||
| 359 | of_at91_pmc_setup(np, &at91rm9200_caps); | ||
| 360 | } | ||
| 361 | CLK_OF_DECLARE(at91rm9200_clk_pmc, "atmel,at91rm9200-pmc", | ||
| 362 | of_at91rm9200_pmc_setup); | ||
| 363 | |||
| 364 | static void __init of_at91sam9260_pmc_setup(struct device_node *np) | ||
| 365 | { | ||
| 366 | of_at91_pmc_setup(np, &at91sam9260_caps); | ||
| 367 | } | ||
| 368 | CLK_OF_DECLARE(at91sam9260_clk_pmc, "atmel,at91sam9260-pmc", | ||
| 369 | of_at91sam9260_pmc_setup); | ||
| 370 | |||
| 371 | static void __init of_at91sam9g45_pmc_setup(struct device_node *np) | ||
| 372 | { | ||
| 373 | of_at91_pmc_setup(np, &at91sam9g45_caps); | ||
| 374 | } | ||
| 375 | CLK_OF_DECLARE(at91sam9g45_clk_pmc, "atmel,at91sam9g45-pmc", | ||
| 376 | of_at91sam9g45_pmc_setup); | ||
| 377 | |||
| 378 | static void __init of_at91sam9n12_pmc_setup(struct device_node *np) | ||
| 379 | { | ||
| 380 | of_at91_pmc_setup(np, &at91sam9n12_caps); | ||
| 381 | } | ||
| 382 | CLK_OF_DECLARE(at91sam9n12_clk_pmc, "atmel,at91sam9n12-pmc", | ||
| 383 | of_at91sam9n12_pmc_setup); | ||
| 384 | |||
| 385 | static void __init of_at91sam9x5_pmc_setup(struct device_node *np) | ||
| 386 | { | ||
| 387 | of_at91_pmc_setup(np, &at91sam9x5_caps); | ||
| 388 | } | ||
| 389 | CLK_OF_DECLARE(at91sam9x5_clk_pmc, "atmel,at91sam9x5-pmc", | ||
| 390 | of_at91sam9x5_pmc_setup); | ||
| 391 | |||
| 392 | static void __init of_sama5d3_pmc_setup(struct device_node *np) | ||
| 393 | { | ||
| 394 | of_at91_pmc_setup(np, &sama5d3_caps); | ||
| 395 | } | ||
| 396 | CLK_OF_DECLARE(sama5d3_clk_pmc, "atmel,sama5d3-pmc", | ||
| 397 | of_sama5d3_pmc_setup); | ||
diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h new file mode 100644 index 000000000000..ba8d14233f80 --- /dev/null +++ b/drivers/clk/at91/pmc.h | |||
| @@ -0,0 +1,116 @@ | |||
| 1 | /* | ||
| 2 | * drivers/clk/at91/pmc.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef __PMC_H_ | ||
| 13 | #define __PMC_H_ | ||
| 14 | |||
| 15 | #include <linux/io.h> | ||
| 16 | #include <linux/irqdomain.h> | ||
| 17 | #include <linux/spinlock.h> | ||
| 18 | |||
| 19 | struct clk_range { | ||
| 20 | unsigned long min; | ||
| 21 | unsigned long max; | ||
| 22 | }; | ||
| 23 | |||
| 24 | #define CLK_RANGE(MIN, MAX) {.min = MIN, .max = MAX,} | ||
| 25 | |||
| 26 | struct at91_pmc_caps { | ||
| 27 | u32 available_irqs; | ||
| 28 | }; | ||
| 29 | |||
| 30 | struct at91_pmc { | ||
| 31 | void __iomem *regbase; | ||
| 32 | int virq; | ||
| 33 | spinlock_t lock; | ||
| 34 | const struct at91_pmc_caps *caps; | ||
| 35 | struct irq_domain *irqdomain; | ||
| 36 | }; | ||
| 37 | |||
| 38 | static inline void pmc_lock(struct at91_pmc *pmc) | ||
| 39 | { | ||
| 40 | spin_lock(&pmc->lock); | ||
| 41 | } | ||
| 42 | |||
| 43 | static inline void pmc_unlock(struct at91_pmc *pmc) | ||
| 44 | { | ||
| 45 | spin_unlock(&pmc->lock); | ||
| 46 | } | ||
| 47 | |||
| 48 | static inline u32 pmc_read(struct at91_pmc *pmc, int offset) | ||
| 49 | { | ||
| 50 | return readl(pmc->regbase + offset); | ||
| 51 | } | ||
| 52 | |||
| 53 | static inline void pmc_write(struct at91_pmc *pmc, int offset, u32 value) | ||
| 54 | { | ||
| 55 | writel(value, pmc->regbase + offset); | ||
| 56 | } | ||
| 57 | |||
| 58 | int of_at91_get_clk_range(struct device_node *np, const char *propname, | ||
| 59 | struct clk_range *range); | ||
| 60 | |||
| 61 | extern void __init of_at91rm9200_clk_main_setup(struct device_node *np, | ||
| 62 | struct at91_pmc *pmc); | ||
| 63 | |||
| 64 | extern void __init of_at91rm9200_clk_pll_setup(struct device_node *np, | ||
| 65 | struct at91_pmc *pmc); | ||
| 66 | extern void __init of_at91sam9g45_clk_pll_setup(struct device_node *np, | ||
| 67 | struct at91_pmc *pmc); | ||
| 68 | extern void __init of_at91sam9g20_clk_pllb_setup(struct device_node *np, | ||
| 69 | struct at91_pmc *pmc); | ||
| 70 | extern void __init of_sama5d3_clk_pll_setup(struct device_node *np, | ||
| 71 | struct at91_pmc *pmc); | ||
| 72 | extern void __init of_at91sam9x5_clk_plldiv_setup(struct device_node *np, | ||
| 73 | struct at91_pmc *pmc); | ||
| 74 | |||
| 75 | extern void __init of_at91rm9200_clk_master_setup(struct device_node *np, | ||
| 76 | struct at91_pmc *pmc); | ||
| 77 | extern void __init of_at91sam9x5_clk_master_setup(struct device_node *np, | ||
| 78 | struct at91_pmc *pmc); | ||
| 79 | |||
| 80 | extern void __init of_at91rm9200_clk_sys_setup(struct device_node *np, | ||
| 81 | struct at91_pmc *pmc); | ||
| 82 | |||
| 83 | extern void __init of_at91rm9200_clk_periph_setup(struct device_node *np, | ||
| 84 | struct at91_pmc *pmc); | ||
| 85 | extern void __init of_at91sam9x5_clk_periph_setup(struct device_node *np, | ||
| 86 | struct at91_pmc *pmc); | ||
| 87 | |||
| 88 | #if defined(CONFIG_AT91_PROGRAMMABLE_CLOCKS) | ||
| 89 | extern void __init of_at91rm9200_clk_prog_setup(struct device_node *np, | ||
| 90 | struct at91_pmc *pmc); | ||
| 91 | extern void __init of_at91sam9g45_clk_prog_setup(struct device_node *np, | ||
| 92 | struct at91_pmc *pmc); | ||
| 93 | extern void __init of_at91sam9x5_clk_prog_setup(struct device_node *np, | ||
| 94 | struct at91_pmc *pmc); | ||
| 95 | #endif | ||
| 96 | |||
| 97 | #if defined(CONFIG_HAVE_AT91_UTMI) | ||
| 98 | extern void __init of_at91sam9x5_clk_utmi_setup(struct device_node *np, | ||
| 99 | struct at91_pmc *pmc); | ||
| 100 | #endif | ||
| 101 | |||
| 102 | #if defined(CONFIG_HAVE_AT91_USB_CLK) | ||
| 103 | extern void __init of_at91rm9200_clk_usb_setup(struct device_node *np, | ||
| 104 | struct at91_pmc *pmc); | ||
| 105 | extern void __init of_at91sam9x5_clk_usb_setup(struct device_node *np, | ||
| 106 | struct at91_pmc *pmc); | ||
| 107 | extern void __init of_at91sam9n12_clk_usb_setup(struct device_node *np, | ||
| 108 | struct at91_pmc *pmc); | ||
| 109 | #endif | ||
| 110 | |||
| 111 | #if defined(CONFIG_HAVE_AT91_SMD) | ||
| 112 | extern void __init of_at91sam9x5_clk_smd_setup(struct device_node *np, | ||
| 113 | struct at91_pmc *pmc); | ||
| 114 | #endif | ||
| 115 | |||
| 116 | #endif /* __PMC_H_ */ | ||
diff --git a/drivers/clk/samsung/clk-s3c64xx.c b/drivers/clk/samsung/clk-s3c64xx.c index 7d2c84265947..8e27aee6887e 100644 --- a/drivers/clk/samsung/clk-s3c64xx.c +++ b/drivers/clk/samsung/clk-s3c64xx.c | |||
| @@ -331,8 +331,8 @@ static struct samsung_clock_alias s3c64xx_clock_aliases[] = { | |||
| 331 | ALIAS(HCLK_HSMMC1, "s3c-sdhci.1", "mmc_busclk.0"), | 331 | ALIAS(HCLK_HSMMC1, "s3c-sdhci.1", "mmc_busclk.0"), |
| 332 | ALIAS(HCLK_HSMMC0, "s3c-sdhci.0", "hsmmc"), | 332 | ALIAS(HCLK_HSMMC0, "s3c-sdhci.0", "hsmmc"), |
| 333 | ALIAS(HCLK_HSMMC0, "s3c-sdhci.0", "mmc_busclk.0"), | 333 | ALIAS(HCLK_HSMMC0, "s3c-sdhci.0", "mmc_busclk.0"), |
| 334 | ALIAS(HCLK_DMA1, NULL, "dma1"), | 334 | ALIAS(HCLK_DMA1, "dma-pl080s.1", "apb_pclk"), |
| 335 | ALIAS(HCLK_DMA0, NULL, "dma0"), | 335 | ALIAS(HCLK_DMA0, "dma-pl080s.0", "apb_pclk"), |
| 336 | ALIAS(HCLK_CAMIF, "s3c-camif", "camif"), | 336 | ALIAS(HCLK_CAMIF, "s3c-camif", "camif"), |
| 337 | ALIAS(HCLK_LCD, "s3c-fb", "lcd"), | 337 | ALIAS(HCLK_LCD, "s3c-fb", "lcd"), |
| 338 | ALIAS(PCLK_SPI1, "s3c6410-spi.1", "spi"), | 338 | ALIAS(PCLK_SPI1, "s3c6410-spi.1", "spi"), |
diff --git a/drivers/crypto/atmel-aes.c b/drivers/crypto/atmel-aes.c index c1efd910d97b..d7c9e317423c 100644 --- a/drivers/crypto/atmel-aes.c +++ b/drivers/crypto/atmel-aes.c | |||
| @@ -30,6 +30,7 @@ | |||
| 30 | #include <linux/irq.h> | 30 | #include <linux/irq.h> |
| 31 | #include <linux/scatterlist.h> | 31 | #include <linux/scatterlist.h> |
| 32 | #include <linux/dma-mapping.h> | 32 | #include <linux/dma-mapping.h> |
| 33 | #include <linux/of_device.h> | ||
| 33 | #include <linux/delay.h> | 34 | #include <linux/delay.h> |
| 34 | #include <linux/crypto.h> | 35 | #include <linux/crypto.h> |
| 35 | #include <linux/cryptohash.h> | 36 | #include <linux/cryptohash.h> |
| @@ -39,6 +40,7 @@ | |||
| 39 | #include <crypto/hash.h> | 40 | #include <crypto/hash.h> |
| 40 | #include <crypto/internal/hash.h> | 41 | #include <crypto/internal/hash.h> |
| 41 | #include <linux/platform_data/crypto-atmel.h> | 42 | #include <linux/platform_data/crypto-atmel.h> |
| 43 | #include <dt-bindings/dma/at91.h> | ||
| 42 | #include "atmel-aes-regs.h" | 44 | #include "atmel-aes-regs.h" |
| 43 | 45 | ||
| 44 | #define CFB8_BLOCK_SIZE 1 | 46 | #define CFB8_BLOCK_SIZE 1 |
| @@ -747,59 +749,50 @@ static int atmel_aes_dma_init(struct atmel_aes_dev *dd, | |||
| 747 | struct crypto_platform_data *pdata) | 749 | struct crypto_platform_data *pdata) |
| 748 | { | 750 | { |
| 749 | int err = -ENOMEM; | 751 | int err = -ENOMEM; |
| 750 | dma_cap_mask_t mask_in, mask_out; | 752 | dma_cap_mask_t mask; |
| 753 | |||
| 754 | dma_cap_zero(mask); | ||
| 755 | dma_cap_set(DMA_SLAVE, mask); | ||
| 756 | |||
| 757 | /* Try to grab 2 DMA channels */ | ||
| 758 | dd->dma_lch_in.chan = dma_request_slave_channel_compat(mask, | ||
| 759 | atmel_aes_filter, &pdata->dma_slave->rxdata, dd->dev, "tx"); | ||
| 760 | if (!dd->dma_lch_in.chan) | ||
| 761 | goto err_dma_in; | ||
| 762 | |||
| 763 | dd->dma_lch_in.dma_conf.direction = DMA_MEM_TO_DEV; | ||
| 764 | dd->dma_lch_in.dma_conf.dst_addr = dd->phys_base + | ||
| 765 | AES_IDATAR(0); | ||
| 766 | dd->dma_lch_in.dma_conf.src_maxburst = dd->caps.max_burst_size; | ||
| 767 | dd->dma_lch_in.dma_conf.src_addr_width = | ||
| 768 | DMA_SLAVE_BUSWIDTH_4_BYTES; | ||
| 769 | dd->dma_lch_in.dma_conf.dst_maxburst = dd->caps.max_burst_size; | ||
| 770 | dd->dma_lch_in.dma_conf.dst_addr_width = | ||
| 771 | DMA_SLAVE_BUSWIDTH_4_BYTES; | ||
| 772 | dd->dma_lch_in.dma_conf.device_fc = false; | ||
| 773 | |||
| 774 | dd->dma_lch_out.chan = dma_request_slave_channel_compat(mask, | ||
| 775 | atmel_aes_filter, &pdata->dma_slave->txdata, dd->dev, "rx"); | ||
| 776 | if (!dd->dma_lch_out.chan) | ||
| 777 | goto err_dma_out; | ||
| 778 | |||
| 779 | dd->dma_lch_out.dma_conf.direction = DMA_DEV_TO_MEM; | ||
| 780 | dd->dma_lch_out.dma_conf.src_addr = dd->phys_base + | ||
| 781 | AES_ODATAR(0); | ||
| 782 | dd->dma_lch_out.dma_conf.src_maxburst = dd->caps.max_burst_size; | ||
| 783 | dd->dma_lch_out.dma_conf.src_addr_width = | ||
| 784 | DMA_SLAVE_BUSWIDTH_4_BYTES; | ||
| 785 | dd->dma_lch_out.dma_conf.dst_maxburst = dd->caps.max_burst_size; | ||
| 786 | dd->dma_lch_out.dma_conf.dst_addr_width = | ||
| 787 | DMA_SLAVE_BUSWIDTH_4_BYTES; | ||
| 788 | dd->dma_lch_out.dma_conf.device_fc = false; | ||
| 751 | 789 | ||
| 752 | if (pdata && pdata->dma_slave->txdata.dma_dev && | 790 | return 0; |
| 753 | pdata->dma_slave->rxdata.dma_dev) { | ||
| 754 | |||
| 755 | /* Try to grab 2 DMA channels */ | ||
| 756 | dma_cap_zero(mask_in); | ||
| 757 | dma_cap_set(DMA_SLAVE, mask_in); | ||
| 758 | |||
| 759 | dd->dma_lch_in.chan = dma_request_channel(mask_in, | ||
| 760 | atmel_aes_filter, &pdata->dma_slave->rxdata); | ||
| 761 | |||
| 762 | if (!dd->dma_lch_in.chan) | ||
| 763 | goto err_dma_in; | ||
| 764 | |||
| 765 | dd->dma_lch_in.dma_conf.direction = DMA_MEM_TO_DEV; | ||
| 766 | dd->dma_lch_in.dma_conf.dst_addr = dd->phys_base + | ||
| 767 | AES_IDATAR(0); | ||
| 768 | dd->dma_lch_in.dma_conf.src_maxburst = dd->caps.max_burst_size; | ||
| 769 | dd->dma_lch_in.dma_conf.src_addr_width = | ||
| 770 | DMA_SLAVE_BUSWIDTH_4_BYTES; | ||
| 771 | dd->dma_lch_in.dma_conf.dst_maxburst = dd->caps.max_burst_size; | ||
| 772 | dd->dma_lch_in.dma_conf.dst_addr_width = | ||
| 773 | DMA_SLAVE_BUSWIDTH_4_BYTES; | ||
| 774 | dd->dma_lch_in.dma_conf.device_fc = false; | ||
| 775 | |||
| 776 | dma_cap_zero(mask_out); | ||
| 777 | dma_cap_set(DMA_SLAVE, mask_out); | ||
| 778 | dd->dma_lch_out.chan = dma_request_channel(mask_out, | ||
| 779 | atmel_aes_filter, &pdata->dma_slave->txdata); | ||
| 780 | |||
| 781 | if (!dd->dma_lch_out.chan) | ||
| 782 | goto err_dma_out; | ||
| 783 | |||
| 784 | dd->dma_lch_out.dma_conf.direction = DMA_DEV_TO_MEM; | ||
| 785 | dd->dma_lch_out.dma_conf.src_addr = dd->phys_base + | ||
| 786 | AES_ODATAR(0); | ||
| 787 | dd->dma_lch_out.dma_conf.src_maxburst = dd->caps.max_burst_size; | ||
| 788 | dd->dma_lch_out.dma_conf.src_addr_width = | ||
| 789 | DMA_SLAVE_BUSWIDTH_4_BYTES; | ||
| 790 | dd->dma_lch_out.dma_conf.dst_maxburst = dd->caps.max_burst_size; | ||
| 791 | dd->dma_lch_out.dma_conf.dst_addr_width = | ||
| 792 | DMA_SLAVE_BUSWIDTH_4_BYTES; | ||
| 793 | dd->dma_lch_out.dma_conf.device_fc = false; | ||
| 794 | |||
| 795 | return 0; | ||
| 796 | } else { | ||
| 797 | return -ENODEV; | ||
| 798 | } | ||
| 799 | 791 | ||
| 800 | err_dma_out: | 792 | err_dma_out: |
| 801 | dma_release_channel(dd->dma_lch_in.chan); | 793 | dma_release_channel(dd->dma_lch_in.chan); |
| 802 | err_dma_in: | 794 | err_dma_in: |
| 795 | dev_warn(dd->dev, "no DMA channel available\n"); | ||
| 803 | return err; | 796 | return err; |
| 804 | } | 797 | } |
| 805 | 798 | ||
| @@ -1261,6 +1254,47 @@ static void atmel_aes_get_cap(struct atmel_aes_dev *dd) | |||
| 1261 | } | 1254 | } |
| 1262 | } | 1255 | } |
| 1263 | 1256 | ||
| 1257 | #if defined(CONFIG_OF) | ||
| 1258 | static const struct of_device_id atmel_aes_dt_ids[] = { | ||
| 1259 | { .compatible = "atmel,at91sam9g46-aes" }, | ||
| 1260 | { /* sentinel */ } | ||
| 1261 | }; | ||
| 1262 | MODULE_DEVICE_TABLE(of, atmel_aes_dt_ids); | ||
| 1263 | |||
| 1264 | static struct crypto_platform_data *atmel_aes_of_init(struct platform_device *pdev) | ||
| 1265 | { | ||
| 1266 | struct device_node *np = pdev->dev.of_node; | ||
| 1267 | struct crypto_platform_data *pdata; | ||
| 1268 | |||
| 1269 | if (!np) { | ||
| 1270 | dev_err(&pdev->dev, "device node not found\n"); | ||
| 1271 | return ERR_PTR(-EINVAL); | ||
| 1272 | } | ||
| 1273 | |||
| 1274 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); | ||
| 1275 | if (!pdata) { | ||
| 1276 | dev_err(&pdev->dev, "could not allocate memory for pdata\n"); | ||
| 1277 | return ERR_PTR(-ENOMEM); | ||
| 1278 | } | ||
| 1279 | |||
| 1280 | pdata->dma_slave = devm_kzalloc(&pdev->dev, | ||
| 1281 | sizeof(*(pdata->dma_slave)), | ||
| 1282 | GFP_KERNEL); | ||
| 1283 | if (!pdata->dma_slave) { | ||
| 1284 | dev_err(&pdev->dev, "could not allocate memory for dma_slave\n"); | ||
| 1285 | devm_kfree(&pdev->dev, pdata); | ||
| 1286 | return ERR_PTR(-ENOMEM); | ||
| 1287 | } | ||
| 1288 | |||
| 1289 | return pdata; | ||
| 1290 | } | ||
| 1291 | #else | ||
| 1292 | static inline struct crypto_platform_data *atmel_aes_of_init(struct platform_device *pdev) | ||
| 1293 | { | ||
| 1294 | return ERR_PTR(-EINVAL); | ||
| 1295 | } | ||
| 1296 | #endif | ||
| 1297 | |||
| 1264 | static int atmel_aes_probe(struct platform_device *pdev) | 1298 | static int atmel_aes_probe(struct platform_device *pdev) |
| 1265 | { | 1299 | { |
| 1266 | struct atmel_aes_dev *aes_dd; | 1300 | struct atmel_aes_dev *aes_dd; |
| @@ -1272,6 +1306,14 @@ static int atmel_aes_probe(struct platform_device *pdev) | |||
| 1272 | 1306 | ||
| 1273 | pdata = pdev->dev.platform_data; | 1307 | pdata = pdev->dev.platform_data; |
| 1274 | if (!pdata) { | 1308 | if (!pdata) { |
| 1309 | pdata = atmel_aes_of_init(pdev); | ||
| 1310 | if (IS_ERR(pdata)) { | ||
| 1311 | err = PTR_ERR(pdata); | ||
| 1312 | goto aes_dd_err; | ||
| 1313 | } | ||
| 1314 | } | ||
| 1315 | |||
| 1316 | if (!pdata->dma_slave) { | ||
| 1275 | err = -ENXIO; | 1317 | err = -ENXIO; |
| 1276 | goto aes_dd_err; | 1318 | goto aes_dd_err; |
| 1277 | } | 1319 | } |
| @@ -1358,7 +1400,9 @@ static int atmel_aes_probe(struct platform_device *pdev) | |||
| 1358 | if (err) | 1400 | if (err) |
| 1359 | goto err_algs; | 1401 | goto err_algs; |
| 1360 | 1402 | ||
| 1361 | dev_info(dev, "Atmel AES\n"); | 1403 | dev_info(dev, "Atmel AES - Using %s, %s for DMA transfers\n", |
| 1404 | dma_chan_name(aes_dd->dma_lch_in.chan), | ||
| 1405 | dma_chan_name(aes_dd->dma_lch_out.chan)); | ||
| 1362 | 1406 | ||
| 1363 | return 0; | 1407 | return 0; |
| 1364 | 1408 | ||
| @@ -1424,6 +1468,7 @@ static struct platform_driver atmel_aes_driver = { | |||
| 1424 | .driver = { | 1468 | .driver = { |
| 1425 | .name = "atmel_aes", | 1469 | .name = "atmel_aes", |
| 1426 | .owner = THIS_MODULE, | 1470 | .owner = THIS_MODULE, |
| 1471 | .of_match_table = of_match_ptr(atmel_aes_dt_ids), | ||
| 1427 | }, | 1472 | }, |
| 1428 | }; | 1473 | }; |
| 1429 | 1474 | ||
diff --git a/drivers/crypto/atmel-sha.c b/drivers/crypto/atmel-sha.c index eaed8bf183bc..0618be06b9fb 100644 --- a/drivers/crypto/atmel-sha.c +++ b/drivers/crypto/atmel-sha.c | |||
| @@ -30,6 +30,7 @@ | |||
| 30 | #include <linux/irq.h> | 30 | #include <linux/irq.h> |
| 31 | #include <linux/scatterlist.h> | 31 | #include <linux/scatterlist.h> |
| 32 | #include <linux/dma-mapping.h> | 32 | #include <linux/dma-mapping.h> |
| 33 | #include <linux/of_device.h> | ||
| 33 | #include <linux/delay.h> | 34 | #include <linux/delay.h> |
| 34 | #include <linux/crypto.h> | 35 | #include <linux/crypto.h> |
| 35 | #include <linux/cryptohash.h> | 36 | #include <linux/cryptohash.h> |
| @@ -1263,32 +1264,29 @@ static int atmel_sha_dma_init(struct atmel_sha_dev *dd, | |||
| 1263 | int err = -ENOMEM; | 1264 | int err = -ENOMEM; |
| 1264 | dma_cap_mask_t mask_in; | 1265 | dma_cap_mask_t mask_in; |
| 1265 | 1266 | ||
| 1266 | if (pdata && pdata->dma_slave->rxdata.dma_dev) { | 1267 | /* Try to grab DMA channel */ |
| 1267 | /* Try to grab DMA channel */ | 1268 | dma_cap_zero(mask_in); |
| 1268 | dma_cap_zero(mask_in); | 1269 | dma_cap_set(DMA_SLAVE, mask_in); |
| 1269 | dma_cap_set(DMA_SLAVE, mask_in); | ||
| 1270 | 1270 | ||
| 1271 | dd->dma_lch_in.chan = dma_request_channel(mask_in, | 1271 | dd->dma_lch_in.chan = dma_request_slave_channel_compat(mask_in, |
| 1272 | atmel_sha_filter, &pdata->dma_slave->rxdata); | 1272 | atmel_sha_filter, &pdata->dma_slave->rxdata, dd->dev, "tx"); |
| 1273 | 1273 | if (!dd->dma_lch_in.chan) { | |
| 1274 | if (!dd->dma_lch_in.chan) | 1274 | dev_warn(dd->dev, "no DMA channel available\n"); |
| 1275 | return err; | 1275 | return err; |
| 1276 | |||
| 1277 | dd->dma_lch_in.dma_conf.direction = DMA_MEM_TO_DEV; | ||
| 1278 | dd->dma_lch_in.dma_conf.dst_addr = dd->phys_base + | ||
| 1279 | SHA_REG_DIN(0); | ||
| 1280 | dd->dma_lch_in.dma_conf.src_maxburst = 1; | ||
| 1281 | dd->dma_lch_in.dma_conf.src_addr_width = | ||
| 1282 | DMA_SLAVE_BUSWIDTH_4_BYTES; | ||
| 1283 | dd->dma_lch_in.dma_conf.dst_maxburst = 1; | ||
| 1284 | dd->dma_lch_in.dma_conf.dst_addr_width = | ||
| 1285 | DMA_SLAVE_BUSWIDTH_4_BYTES; | ||
| 1286 | dd->dma_lch_in.dma_conf.device_fc = false; | ||
| 1287 | |||
| 1288 | return 0; | ||
| 1289 | } | 1276 | } |
| 1290 | 1277 | ||
| 1291 | return -ENODEV; | 1278 | dd->dma_lch_in.dma_conf.direction = DMA_MEM_TO_DEV; |
| 1279 | dd->dma_lch_in.dma_conf.dst_addr = dd->phys_base + | ||
| 1280 | SHA_REG_DIN(0); | ||
| 1281 | dd->dma_lch_in.dma_conf.src_maxburst = 1; | ||
| 1282 | dd->dma_lch_in.dma_conf.src_addr_width = | ||
| 1283 | DMA_SLAVE_BUSWIDTH_4_BYTES; | ||
| 1284 | dd->dma_lch_in.dma_conf.dst_maxburst = 1; | ||
| 1285 | dd->dma_lch_in.dma_conf.dst_addr_width = | ||
| 1286 | DMA_SLAVE_BUSWIDTH_4_BYTES; | ||
| 1287 | dd->dma_lch_in.dma_conf.device_fc = false; | ||
| 1288 | |||
| 1289 | return 0; | ||
| 1292 | } | 1290 | } |
| 1293 | 1291 | ||
| 1294 | static void atmel_sha_dma_cleanup(struct atmel_sha_dev *dd) | 1292 | static void atmel_sha_dma_cleanup(struct atmel_sha_dev *dd) |
| @@ -1326,6 +1324,48 @@ static void atmel_sha_get_cap(struct atmel_sha_dev *dd) | |||
| 1326 | } | 1324 | } |
| 1327 | } | 1325 | } |
| 1328 | 1326 | ||
| 1327 | #if defined(CONFIG_OF) | ||
| 1328 | static const struct of_device_id atmel_sha_dt_ids[] = { | ||
| 1329 | { .compatible = "atmel,at91sam9g46-sha" }, | ||
| 1330 | { /* sentinel */ } | ||
| 1331 | }; | ||
| 1332 | |||
| 1333 | MODULE_DEVICE_TABLE(of, atmel_sha_dt_ids); | ||
| 1334 | |||
| 1335 | static struct crypto_platform_data *atmel_sha_of_init(struct platform_device *pdev) | ||
| 1336 | { | ||
| 1337 | struct device_node *np = pdev->dev.of_node; | ||
| 1338 | struct crypto_platform_data *pdata; | ||
| 1339 | |||
| 1340 | if (!np) { | ||
| 1341 | dev_err(&pdev->dev, "device node not found\n"); | ||
| 1342 | return ERR_PTR(-EINVAL); | ||
| 1343 | } | ||
| 1344 | |||
| 1345 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); | ||
| 1346 | if (!pdata) { | ||
| 1347 | dev_err(&pdev->dev, "could not allocate memory for pdata\n"); | ||
| 1348 | return ERR_PTR(-ENOMEM); | ||
| 1349 | } | ||
| 1350 | |||
| 1351 | pdata->dma_slave = devm_kzalloc(&pdev->dev, | ||
| 1352 | sizeof(*(pdata->dma_slave)), | ||
| 1353 | GFP_KERNEL); | ||
| 1354 | if (!pdata->dma_slave) { | ||
| 1355 | dev_err(&pdev->dev, "could not allocate memory for dma_slave\n"); | ||
| 1356 | devm_kfree(&pdev->dev, pdata); | ||
| 1357 | return ERR_PTR(-ENOMEM); | ||
| 1358 | } | ||
| 1359 | |||
| 1360 | return pdata; | ||
| 1361 | } | ||
| 1362 | #else /* CONFIG_OF */ | ||
| 1363 | static inline struct crypto_platform_data *atmel_sha_of_init(struct platform_device *dev) | ||
| 1364 | { | ||
| 1365 | return ERR_PTR(-EINVAL); | ||
| 1366 | } | ||
| 1367 | #endif | ||
| 1368 | |||
| 1329 | static int atmel_sha_probe(struct platform_device *pdev) | 1369 | static int atmel_sha_probe(struct platform_device *pdev) |
| 1330 | { | 1370 | { |
| 1331 | struct atmel_sha_dev *sha_dd; | 1371 | struct atmel_sha_dev *sha_dd; |
| @@ -1402,13 +1442,23 @@ static int atmel_sha_probe(struct platform_device *pdev) | |||
| 1402 | if (sha_dd->caps.has_dma) { | 1442 | if (sha_dd->caps.has_dma) { |
| 1403 | pdata = pdev->dev.platform_data; | 1443 | pdata = pdev->dev.platform_data; |
| 1404 | if (!pdata) { | 1444 | if (!pdata) { |
| 1405 | dev_err(&pdev->dev, "platform data not available\n"); | 1445 | pdata = atmel_sha_of_init(pdev); |
| 1446 | if (IS_ERR(pdata)) { | ||
| 1447 | dev_err(&pdev->dev, "platform data not available\n"); | ||
| 1448 | err = PTR_ERR(pdata); | ||
| 1449 | goto err_pdata; | ||
| 1450 | } | ||
| 1451 | } | ||
| 1452 | if (!pdata->dma_slave) { | ||
| 1406 | err = -ENXIO; | 1453 | err = -ENXIO; |
| 1407 | goto err_pdata; | 1454 | goto err_pdata; |
| 1408 | } | 1455 | } |
| 1409 | err = atmel_sha_dma_init(sha_dd, pdata); | 1456 | err = atmel_sha_dma_init(sha_dd, pdata); |
| 1410 | if (err) | 1457 | if (err) |
| 1411 | goto err_sha_dma; | 1458 | goto err_sha_dma; |
| 1459 | |||
| 1460 | dev_info(dev, "using %s for DMA transfers\n", | ||
| 1461 | dma_chan_name(sha_dd->dma_lch_in.chan)); | ||
| 1412 | } | 1462 | } |
| 1413 | 1463 | ||
| 1414 | spin_lock(&atmel_sha.lock); | 1464 | spin_lock(&atmel_sha.lock); |
| @@ -1419,7 +1469,9 @@ static int atmel_sha_probe(struct platform_device *pdev) | |||
| 1419 | if (err) | 1469 | if (err) |
| 1420 | goto err_algs; | 1470 | goto err_algs; |
| 1421 | 1471 | ||
| 1422 | dev_info(dev, "Atmel SHA1/SHA256\n"); | 1472 | dev_info(dev, "Atmel SHA1/SHA256%s%s\n", |
| 1473 | sha_dd->caps.has_sha224 ? "/SHA224" : "", | ||
| 1474 | sha_dd->caps.has_sha_384_512 ? "/SHA384/SHA512" : ""); | ||
| 1423 | 1475 | ||
| 1424 | return 0; | 1476 | return 0; |
| 1425 | 1477 | ||
| @@ -1483,6 +1535,7 @@ static struct platform_driver atmel_sha_driver = { | |||
| 1483 | .driver = { | 1535 | .driver = { |
| 1484 | .name = "atmel_sha", | 1536 | .name = "atmel_sha", |
| 1485 | .owner = THIS_MODULE, | 1537 | .owner = THIS_MODULE, |
| 1538 | .of_match_table = of_match_ptr(atmel_sha_dt_ids), | ||
| 1486 | }, | 1539 | }, |
| 1487 | }; | 1540 | }; |
| 1488 | 1541 | ||
diff --git a/drivers/crypto/atmel-tdes.c b/drivers/crypto/atmel-tdes.c index 4a99564a08e6..6cde5b530c69 100644 --- a/drivers/crypto/atmel-tdes.c +++ b/drivers/crypto/atmel-tdes.c | |||
| @@ -30,6 +30,7 @@ | |||
| 30 | #include <linux/irq.h> | 30 | #include <linux/irq.h> |
| 31 | #include <linux/scatterlist.h> | 31 | #include <linux/scatterlist.h> |
| 32 | #include <linux/dma-mapping.h> | 32 | #include <linux/dma-mapping.h> |
| 33 | #include <linux/of_device.h> | ||
| 33 | #include <linux/delay.h> | 34 | #include <linux/delay.h> |
| 34 | #include <linux/crypto.h> | 35 | #include <linux/crypto.h> |
| 35 | #include <linux/cryptohash.h> | 36 | #include <linux/cryptohash.h> |
| @@ -716,59 +717,50 @@ static int atmel_tdes_dma_init(struct atmel_tdes_dev *dd, | |||
| 716 | struct crypto_platform_data *pdata) | 717 | struct crypto_platform_data *pdata) |
| 717 | { | 718 | { |
| 718 | int err = -ENOMEM; | 719 | int err = -ENOMEM; |
| 719 | dma_cap_mask_t mask_in, mask_out; | 720 | dma_cap_mask_t mask; |
| 721 | |||
| 722 | dma_cap_zero(mask); | ||
| 723 | dma_cap_set(DMA_SLAVE, mask); | ||
| 724 | |||
| 725 | /* Try to grab 2 DMA channels */ | ||
| 726 | dd->dma_lch_in.chan = dma_request_slave_channel_compat(mask, | ||
| 727 | atmel_tdes_filter, &pdata->dma_slave->rxdata, dd->dev, "tx"); | ||
| 728 | if (!dd->dma_lch_in.chan) | ||
| 729 | goto err_dma_in; | ||
| 730 | |||
| 731 | dd->dma_lch_in.dma_conf.direction = DMA_MEM_TO_DEV; | ||
| 732 | dd->dma_lch_in.dma_conf.dst_addr = dd->phys_base + | ||
| 733 | TDES_IDATA1R; | ||
| 734 | dd->dma_lch_in.dma_conf.src_maxburst = 1; | ||
| 735 | dd->dma_lch_in.dma_conf.src_addr_width = | ||
| 736 | DMA_SLAVE_BUSWIDTH_4_BYTES; | ||
| 737 | dd->dma_lch_in.dma_conf.dst_maxburst = 1; | ||
| 738 | dd->dma_lch_in.dma_conf.dst_addr_width = | ||
| 739 | DMA_SLAVE_BUSWIDTH_4_BYTES; | ||
| 740 | dd->dma_lch_in.dma_conf.device_fc = false; | ||
| 741 | |||
| 742 | dd->dma_lch_out.chan = dma_request_slave_channel_compat(mask, | ||
| 743 | atmel_tdes_filter, &pdata->dma_slave->txdata, dd->dev, "rx"); | ||
| 744 | if (!dd->dma_lch_out.chan) | ||
| 745 | goto err_dma_out; | ||
| 746 | |||
| 747 | dd->dma_lch_out.dma_conf.direction = DMA_DEV_TO_MEM; | ||
| 748 | dd->dma_lch_out.dma_conf.src_addr = dd->phys_base + | ||
| 749 | TDES_ODATA1R; | ||
| 750 | dd->dma_lch_out.dma_conf.src_maxburst = 1; | ||
| 751 | dd->dma_lch_out.dma_conf.src_addr_width = | ||
| 752 | DMA_SLAVE_BUSWIDTH_4_BYTES; | ||
| 753 | dd->dma_lch_out.dma_conf.dst_maxburst = 1; | ||
| 754 | dd->dma_lch_out.dma_conf.dst_addr_width = | ||
| 755 | DMA_SLAVE_BUSWIDTH_4_BYTES; | ||
| 756 | dd->dma_lch_out.dma_conf.device_fc = false; | ||
| 720 | 757 | ||
| 721 | if (pdata && pdata->dma_slave->txdata.dma_dev && | 758 | return 0; |
| 722 | pdata->dma_slave->rxdata.dma_dev) { | ||
| 723 | |||
| 724 | /* Try to grab 2 DMA channels */ | ||
| 725 | dma_cap_zero(mask_in); | ||
| 726 | dma_cap_set(DMA_SLAVE, mask_in); | ||
| 727 | |||
| 728 | dd->dma_lch_in.chan = dma_request_channel(mask_in, | ||
| 729 | atmel_tdes_filter, &pdata->dma_slave->rxdata); | ||
| 730 | |||
| 731 | if (!dd->dma_lch_in.chan) | ||
| 732 | goto err_dma_in; | ||
| 733 | |||
| 734 | dd->dma_lch_in.dma_conf.direction = DMA_MEM_TO_DEV; | ||
| 735 | dd->dma_lch_in.dma_conf.dst_addr = dd->phys_base + | ||
| 736 | TDES_IDATA1R; | ||
| 737 | dd->dma_lch_in.dma_conf.src_maxburst = 1; | ||
| 738 | dd->dma_lch_in.dma_conf.src_addr_width = | ||
| 739 | DMA_SLAVE_BUSWIDTH_4_BYTES; | ||
| 740 | dd->dma_lch_in.dma_conf.dst_maxburst = 1; | ||
| 741 | dd->dma_lch_in.dma_conf.dst_addr_width = | ||
| 742 | DMA_SLAVE_BUSWIDTH_4_BYTES; | ||
| 743 | dd->dma_lch_in.dma_conf.device_fc = false; | ||
| 744 | |||
| 745 | dma_cap_zero(mask_out); | ||
| 746 | dma_cap_set(DMA_SLAVE, mask_out); | ||
| 747 | dd->dma_lch_out.chan = dma_request_channel(mask_out, | ||
| 748 | atmel_tdes_filter, &pdata->dma_slave->txdata); | ||
| 749 | |||
| 750 | if (!dd->dma_lch_out.chan) | ||
| 751 | goto err_dma_out; | ||
| 752 | |||
| 753 | dd->dma_lch_out.dma_conf.direction = DMA_DEV_TO_MEM; | ||
| 754 | dd->dma_lch_out.dma_conf.src_addr = dd->phys_base + | ||
| 755 | TDES_ODATA1R; | ||
| 756 | dd->dma_lch_out.dma_conf.src_maxburst = 1; | ||
| 757 | dd->dma_lch_out.dma_conf.src_addr_width = | ||
| 758 | DMA_SLAVE_BUSWIDTH_4_BYTES; | ||
| 759 | dd->dma_lch_out.dma_conf.dst_maxburst = 1; | ||
| 760 | dd->dma_lch_out.dma_conf.dst_addr_width = | ||
| 761 | DMA_SLAVE_BUSWIDTH_4_BYTES; | ||
| 762 | dd->dma_lch_out.dma_conf.device_fc = false; | ||
| 763 | |||
| 764 | return 0; | ||
| 765 | } else { | ||
| 766 | return -ENODEV; | ||
| 767 | } | ||
| 768 | 759 | ||
| 769 | err_dma_out: | 760 | err_dma_out: |
| 770 | dma_release_channel(dd->dma_lch_in.chan); | 761 | dma_release_channel(dd->dma_lch_in.chan); |
| 771 | err_dma_in: | 762 | err_dma_in: |
| 763 | dev_warn(dd->dev, "no DMA channel available\n"); | ||
| 772 | return err; | 764 | return err; |
| 773 | } | 765 | } |
| 774 | 766 | ||
| @@ -1317,6 +1309,47 @@ static void atmel_tdes_get_cap(struct atmel_tdes_dev *dd) | |||
| 1317 | } | 1309 | } |
| 1318 | } | 1310 | } |
| 1319 | 1311 | ||
| 1312 | #if defined(CONFIG_OF) | ||
| 1313 | static const struct of_device_id atmel_tdes_dt_ids[] = { | ||
| 1314 | { .compatible = "atmel,at91sam9g46-tdes" }, | ||
| 1315 | { /* sentinel */ } | ||
| 1316 | }; | ||
| 1317 | MODULE_DEVICE_TABLE(of, atmel_tdes_dt_ids); | ||
| 1318 | |||
| 1319 | static struct crypto_platform_data *atmel_tdes_of_init(struct platform_device *pdev) | ||
| 1320 | { | ||
| 1321 | struct device_node *np = pdev->dev.of_node; | ||
| 1322 | struct crypto_platform_data *pdata; | ||
| 1323 | |||
| 1324 | if (!np) { | ||
| 1325 | dev_err(&pdev->dev, "device node not found\n"); | ||
| 1326 | return ERR_PTR(-EINVAL); | ||
| 1327 | } | ||
| 1328 | |||
| 1329 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); | ||
| 1330 | if (!pdata) { | ||
| 1331 | dev_err(&pdev->dev, "could not allocate memory for pdata\n"); | ||
| 1332 | return ERR_PTR(-ENOMEM); | ||
| 1333 | } | ||
| 1334 | |||
| 1335 | pdata->dma_slave = devm_kzalloc(&pdev->dev, | ||
| 1336 | sizeof(*(pdata->dma_slave)), | ||
| 1337 | GFP_KERNEL); | ||
| 1338 | if (!pdata->dma_slave) { | ||
| 1339 | dev_err(&pdev->dev, "could not allocate memory for dma_slave\n"); | ||
| 1340 | devm_kfree(&pdev->dev, pdata); | ||
| 1341 | return ERR_PTR(-ENOMEM); | ||
| 1342 | } | ||
| 1343 | |||
| 1344 | return pdata; | ||
| 1345 | } | ||
| 1346 | #else /* CONFIG_OF */ | ||
| 1347 | static inline struct crypto_platform_data *atmel_tdes_of_init(struct platform_device *pdev) | ||
| 1348 | { | ||
| 1349 | return ERR_PTR(-EINVAL); | ||
| 1350 | } | ||
| 1351 | #endif | ||
| 1352 | |||
| 1320 | static int atmel_tdes_probe(struct platform_device *pdev) | 1353 | static int atmel_tdes_probe(struct platform_device *pdev) |
| 1321 | { | 1354 | { |
| 1322 | struct atmel_tdes_dev *tdes_dd; | 1355 | struct atmel_tdes_dev *tdes_dd; |
| @@ -1399,13 +1432,24 @@ static int atmel_tdes_probe(struct platform_device *pdev) | |||
| 1399 | if (tdes_dd->caps.has_dma) { | 1432 | if (tdes_dd->caps.has_dma) { |
| 1400 | pdata = pdev->dev.platform_data; | 1433 | pdata = pdev->dev.platform_data; |
| 1401 | if (!pdata) { | 1434 | if (!pdata) { |
| 1402 | dev_err(&pdev->dev, "platform data not available\n"); | 1435 | pdata = atmel_tdes_of_init(pdev); |
| 1436 | if (IS_ERR(pdata)) { | ||
| 1437 | dev_err(&pdev->dev, "platform data not available\n"); | ||
| 1438 | err = PTR_ERR(pdata); | ||
| 1439 | goto err_pdata; | ||
| 1440 | } | ||
| 1441 | } | ||
| 1442 | if (!pdata->dma_slave) { | ||
| 1403 | err = -ENXIO; | 1443 | err = -ENXIO; |
| 1404 | goto err_pdata; | 1444 | goto err_pdata; |
| 1405 | } | 1445 | } |
| 1406 | err = atmel_tdes_dma_init(tdes_dd, pdata); | 1446 | err = atmel_tdes_dma_init(tdes_dd, pdata); |
| 1407 | if (err) | 1447 | if (err) |
| 1408 | goto err_tdes_dma; | 1448 | goto err_tdes_dma; |
| 1449 | |||
| 1450 | dev_info(dev, "using %s, %s for DMA transfers\n", | ||
| 1451 | dma_chan_name(tdes_dd->dma_lch_in.chan), | ||
| 1452 | dma_chan_name(tdes_dd->dma_lch_out.chan)); | ||
| 1409 | } | 1453 | } |
| 1410 | 1454 | ||
| 1411 | spin_lock(&atmel_tdes.lock); | 1455 | spin_lock(&atmel_tdes.lock); |
| @@ -1487,6 +1531,7 @@ static struct platform_driver atmel_tdes_driver = { | |||
| 1487 | .driver = { | 1531 | .driver = { |
| 1488 | .name = "atmel_tdes", | 1532 | .name = "atmel_tdes", |
| 1489 | .owner = THIS_MODULE, | 1533 | .owner = THIS_MODULE, |
| 1534 | .of_match_table = of_match_ptr(atmel_tdes_dt_ids), | ||
| 1490 | }, | 1535 | }, |
| 1491 | }; | 1536 | }; |
| 1492 | 1537 | ||
diff --git a/drivers/irqchip/exynos-combiner.c b/drivers/irqchip/exynos-combiner.c index 868ed40cb6bf..40e6440348ff 100644 --- a/drivers/irqchip/exynos-combiner.c +++ b/drivers/irqchip/exynos-combiner.c | |||
| @@ -171,8 +171,7 @@ static struct irq_domain_ops combiner_irq_domain_ops = { | |||
| 171 | 171 | ||
| 172 | static void __init combiner_init(void __iomem *combiner_base, | 172 | static void __init combiner_init(void __iomem *combiner_base, |
| 173 | struct device_node *np, | 173 | struct device_node *np, |
| 174 | unsigned int max_nr, | 174 | unsigned int max_nr) |
| 175 | int irq_base) | ||
| 176 | { | 175 | { |
| 177 | int i, irq; | 176 | int i, irq; |
| 178 | unsigned int nr_irq; | 177 | unsigned int nr_irq; |
| @@ -186,7 +185,7 @@ static void __init combiner_init(void __iomem *combiner_base, | |||
| 186 | return; | 185 | return; |
| 187 | } | 186 | } |
| 188 | 187 | ||
| 189 | combiner_irq_domain = irq_domain_add_simple(np, nr_irq, irq_base, | 188 | combiner_irq_domain = irq_domain_add_linear(np, nr_irq, |
| 190 | &combiner_irq_domain_ops, combiner_data); | 189 | &combiner_irq_domain_ops, combiner_data); |
| 191 | if (WARN_ON(!combiner_irq_domain)) { | 190 | if (WARN_ON(!combiner_irq_domain)) { |
| 192 | pr_warning("%s: irq domain init failed\n", __func__); | 191 | pr_warning("%s: irq domain init failed\n", __func__); |
| @@ -207,7 +206,6 @@ static int __init combiner_of_init(struct device_node *np, | |||
| 207 | { | 206 | { |
| 208 | void __iomem *combiner_base; | 207 | void __iomem *combiner_base; |
| 209 | unsigned int max_nr = 20; | 208 | unsigned int max_nr = 20; |
| 210 | int irq_base = -1; | ||
| 211 | 209 | ||
| 212 | combiner_base = of_iomap(np, 0); | 210 | combiner_base = of_iomap(np, 0); |
| 213 | if (!combiner_base) { | 211 | if (!combiner_base) { |
| @@ -221,14 +219,7 @@ static int __init combiner_of_init(struct device_node *np, | |||
| 221 | __func__, max_nr); | 219 | __func__, max_nr); |
| 222 | } | 220 | } |
| 223 | 221 | ||
| 224 | /* | 222 | combiner_init(combiner_base, np, max_nr); |
| 225 | * FIXME: This is a hardwired COMBINER_IRQ(0,0). Once all devices | ||
| 226 | * get their IRQ from DT, remove this in order to get dynamic | ||
| 227 | * allocation. | ||
| 228 | */ | ||
| 229 | irq_base = 160; | ||
| 230 | |||
| 231 | combiner_init(combiner_base, np, max_nr, irq_base); | ||
| 232 | 223 | ||
| 233 | return 0; | 224 | return 0; |
| 234 | } | 225 | } |
diff --git a/drivers/irqchip/irq-renesas-irqc.c b/drivers/irqchip/irq-renesas-irqc.c index 2f404ba61c6c..8777065012a5 100644 --- a/drivers/irqchip/irq-renesas-irqc.c +++ b/drivers/irqchip/irq-renesas-irqc.c | |||
| @@ -81,15 +81,12 @@ static void irqc_irq_disable(struct irq_data *d) | |||
| 81 | iowrite32(BIT(hw_irq), p->cpu_int_base + IRQC_EN_STS); | 81 | iowrite32(BIT(hw_irq), p->cpu_int_base + IRQC_EN_STS); |
| 82 | } | 82 | } |
| 83 | 83 | ||
| 84 | #define INTC_IRQ_SENSE_VALID 0x10 | ||
| 85 | #define INTC_IRQ_SENSE(x) (x + INTC_IRQ_SENSE_VALID) | ||
| 86 | |||
| 87 | static unsigned char irqc_sense[IRQ_TYPE_SENSE_MASK + 1] = { | 84 | static unsigned char irqc_sense[IRQ_TYPE_SENSE_MASK + 1] = { |
| 88 | [IRQ_TYPE_LEVEL_LOW] = INTC_IRQ_SENSE(0x01), | 85 | [IRQ_TYPE_LEVEL_LOW] = 0x01, |
| 89 | [IRQ_TYPE_LEVEL_HIGH] = INTC_IRQ_SENSE(0x02), | 86 | [IRQ_TYPE_LEVEL_HIGH] = 0x02, |
| 90 | [IRQ_TYPE_EDGE_FALLING] = INTC_IRQ_SENSE(0x04), /* Synchronous */ | 87 | [IRQ_TYPE_EDGE_FALLING] = 0x04, /* Synchronous */ |
| 91 | [IRQ_TYPE_EDGE_RISING] = INTC_IRQ_SENSE(0x08), /* Synchronous */ | 88 | [IRQ_TYPE_EDGE_RISING] = 0x08, /* Synchronous */ |
| 92 | [IRQ_TYPE_EDGE_BOTH] = INTC_IRQ_SENSE(0x0c), /* Synchronous */ | 89 | [IRQ_TYPE_EDGE_BOTH] = 0x0c, /* Synchronous */ |
| 93 | }; | 90 | }; |
| 94 | 91 | ||
| 95 | static int irqc_irq_set_type(struct irq_data *d, unsigned int type) | 92 | static int irqc_irq_set_type(struct irq_data *d, unsigned int type) |
| @@ -101,12 +98,12 @@ static int irqc_irq_set_type(struct irq_data *d, unsigned int type) | |||
| 101 | 98 | ||
| 102 | irqc_dbg(&p->irq[hw_irq], "sense"); | 99 | irqc_dbg(&p->irq[hw_irq], "sense"); |
| 103 | 100 | ||
| 104 | if (!(value & INTC_IRQ_SENSE_VALID)) | 101 | if (!value) |
| 105 | return -EINVAL; | 102 | return -EINVAL; |
| 106 | 103 | ||
| 107 | tmp = ioread32(p->iomem + IRQC_CONFIG(hw_irq)); | 104 | tmp = ioread32(p->iomem + IRQC_CONFIG(hw_irq)); |
| 108 | tmp &= ~0x3f; | 105 | tmp &= ~0x3f; |
| 109 | tmp |= value ^ INTC_IRQ_SENSE_VALID; | 106 | tmp |= value; |
| 110 | iowrite32(tmp, p->iomem + IRQC_CONFIG(hw_irq)); | 107 | iowrite32(tmp, p->iomem + IRQC_CONFIG(hw_irq)); |
| 111 | return 0; | 108 | return 0; |
| 112 | } | 109 | } |
| @@ -212,10 +209,8 @@ static int irqc_probe(struct platform_device *pdev) | |||
| 212 | irq_chip->name = name; | 209 | irq_chip->name = name; |
| 213 | irq_chip->irq_mask = irqc_irq_disable; | 210 | irq_chip->irq_mask = irqc_irq_disable; |
| 214 | irq_chip->irq_unmask = irqc_irq_enable; | 211 | irq_chip->irq_unmask = irqc_irq_enable; |
| 215 | irq_chip->irq_enable = irqc_irq_enable; | ||
| 216 | irq_chip->irq_disable = irqc_irq_disable; | ||
| 217 | irq_chip->irq_set_type = irqc_irq_set_type; | 212 | irq_chip->irq_set_type = irqc_irq_set_type; |
| 218 | irq_chip->flags = IRQCHIP_SKIP_SET_WAKE; | 213 | irq_chip->flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND; |
| 219 | 214 | ||
| 220 | p->irq_domain = irq_domain_add_simple(pdev->dev.of_node, | 215 | p->irq_domain = irq_domain_add_simple(pdev->dev.of_node, |
| 221 | p->number_of_irqs, | 216 | p->number_of_irqs, |
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 1e2d83f2b995..cc29832c9638 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile | |||
| @@ -1 +1,2 @@ | |||
| 1 | obj-$(CONFIG_RESET_CONTROLLER) += core.o | 1 | obj-$(CONFIG_RESET_CONTROLLER) += core.o |
| 2 | obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o | ||
diff --git a/drivers/reset/reset-sunxi.c b/drivers/reset/reset-sunxi.c new file mode 100644 index 000000000000..695bd3496eba --- /dev/null +++ b/drivers/reset/reset-sunxi.c | |||
| @@ -0,0 +1,175 @@ | |||
| 1 | /* | ||
| 2 | * Allwinner SoCs Reset Controller driver | ||
| 3 | * | ||
| 4 | * Copyright 2013 Maxime Ripard | ||
| 5 | * | ||
| 6 | * Maxime Ripard <maxime.ripard@free-electrons.com> | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License as published by | ||
| 10 | * the Free Software Foundation; either version 2 of the License, or | ||
| 11 | * (at your option) any later version. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #include <linux/err.h> | ||
| 15 | #include <linux/io.h> | ||
| 16 | #include <linux/module.h> | ||
| 17 | #include <linux/of.h> | ||
| 18 | #include <linux/of_address.h> | ||
| 19 | #include <linux/platform_device.h> | ||
| 20 | #include <linux/reset-controller.h> | ||
| 21 | #include <linux/slab.h> | ||
| 22 | #include <linux/spinlock.h> | ||
| 23 | #include <linux/types.h> | ||
| 24 | |||
| 25 | struct sunxi_reset_data { | ||
| 26 | spinlock_t lock; | ||
| 27 | void __iomem *membase; | ||
| 28 | struct reset_controller_dev rcdev; | ||
| 29 | }; | ||
| 30 | |||
| 31 | static int sunxi_reset_assert(struct reset_controller_dev *rcdev, | ||
| 32 | unsigned long id) | ||
| 33 | { | ||
| 34 | struct sunxi_reset_data *data = container_of(rcdev, | ||
| 35 | struct sunxi_reset_data, | ||
| 36 | rcdev); | ||
| 37 | int bank = id / BITS_PER_LONG; | ||
| 38 | int offset = id % BITS_PER_LONG; | ||
| 39 | unsigned long flags; | ||
| 40 | u32 reg; | ||
| 41 | |||
| 42 | spin_lock_irqsave(&data->lock, flags); | ||
| 43 | |||
| 44 | reg = readl(data->membase + (bank * 4)); | ||
| 45 | writel(reg & ~BIT(offset), data->membase + (bank * 4)); | ||
| 46 | |||
| 47 | spin_unlock_irqrestore(&data->lock, flags); | ||
| 48 | |||
| 49 | return 0; | ||
| 50 | } | ||
| 51 | |||
| 52 | static int sunxi_reset_deassert(struct reset_controller_dev *rcdev, | ||
| 53 | unsigned long id) | ||
| 54 | { | ||
| 55 | struct sunxi_reset_data *data = container_of(rcdev, | ||
| 56 | struct sunxi_reset_data, | ||
| 57 | rcdev); | ||
| 58 | int bank = id / BITS_PER_LONG; | ||
| 59 | int offset = id % BITS_PER_LONG; | ||
| 60 | unsigned long flags; | ||
| 61 | u32 reg; | ||
| 62 | |||
| 63 | spin_lock_irqsave(&data->lock, flags); | ||
| 64 | |||
| 65 | reg = readl(data->membase + (bank * 4)); | ||
| 66 | writel(reg | BIT(offset), data->membase + (bank * 4)); | ||
| 67 | |||
| 68 | spin_unlock_irqrestore(&data->lock, flags); | ||
| 69 | |||
| 70 | return 0; | ||
| 71 | } | ||
| 72 | |||
| 73 | static struct reset_control_ops sunxi_reset_ops = { | ||
| 74 | .assert = sunxi_reset_assert, | ||
| 75 | .deassert = sunxi_reset_deassert, | ||
| 76 | }; | ||
| 77 | |||
| 78 | static int sunxi_reset_init(struct device_node *np) | ||
| 79 | { | ||
| 80 | struct sunxi_reset_data *data; | ||
| 81 | struct resource res; | ||
| 82 | resource_size_t size; | ||
| 83 | int ret; | ||
| 84 | |||
| 85 | data = kzalloc(sizeof(*data), GFP_KERNEL); | ||
| 86 | if (!data) | ||
| 87 | return -ENOMEM; | ||
| 88 | |||
| 89 | ret = of_address_to_resource(np, 0, &res); | ||
| 90 | if (ret) | ||
| 91 | goto err_alloc; | ||
| 92 | |||
| 93 | size = resource_size(&res); | ||
| 94 | if (!request_mem_region(res.start, size, np->name)) { | ||
| 95 | ret = -EBUSY; | ||
| 96 | goto err_alloc; | ||
| 97 | } | ||
| 98 | |||
| 99 | data->membase = ioremap(res.start, size); | ||
| 100 | if (!data->membase) { | ||
| 101 | ret = -ENOMEM; | ||
| 102 | goto err_alloc; | ||
| 103 | } | ||
| 104 | |||
| 105 | data->rcdev.owner = THIS_MODULE; | ||
| 106 | data->rcdev.nr_resets = size * 32; | ||
| 107 | data->rcdev.ops = &sunxi_reset_ops; | ||
| 108 | data->rcdev.of_node = np; | ||
| 109 | reset_controller_register(&data->rcdev); | ||
| 110 | |||
| 111 | return 0; | ||
| 112 | |||
| 113 | err_alloc: | ||
| 114 | kfree(data); | ||
| 115 | return ret; | ||
| 116 | }; | ||
| 117 | |||
| 118 | /* | ||
| 119 | * These are the reset controller we need to initialize early on in | ||
| 120 | * our system, before we can even think of using a regular device | ||
| 121 | * driver for it. | ||
| 122 | */ | ||
| 123 | static const struct of_device_id sunxi_early_reset_dt_ids[] __initdata = { | ||
| 124 | { .compatible = "allwinner,sun6i-a31-ahb1-reset", }, | ||
| 125 | { /* sentinel */ }, | ||
| 126 | }; | ||
| 127 | |||
| 128 | void __init sun6i_reset_init(void) | ||
| 129 | { | ||
| 130 | struct device_node *np; | ||
| 131 | |||
| 132 | for_each_matching_node(np, sunxi_early_reset_dt_ids) | ||
| 133 | sunxi_reset_init(np); | ||
| 134 | } | ||
| 135 | |||
| 136 | /* | ||
| 137 | * And these are the controllers we can register through the regular | ||
| 138 | * device model. | ||
| 139 | */ | ||
| 140 | static const struct of_device_id sunxi_reset_dt_ids[] = { | ||
| 141 | { .compatible = "allwinner,sun6i-a31-clock-reset", }, | ||
| 142 | { /* sentinel */ }, | ||
| 143 | }; | ||
| 144 | MODULE_DEVICE_TABLE(of, sunxi_reset_dt_ids); | ||
| 145 | |||
| 146 | static int sunxi_reset_probe(struct platform_device *pdev) | ||
| 147 | { | ||
| 148 | return sunxi_reset_init(pdev->dev.of_node); | ||
| 149 | } | ||
| 150 | |||
| 151 | static int sunxi_reset_remove(struct platform_device *pdev) | ||
| 152 | { | ||
| 153 | struct sunxi_reset_data *data = platform_get_drvdata(pdev); | ||
| 154 | |||
| 155 | reset_controller_unregister(&data->rcdev); | ||
| 156 | iounmap(data->membase); | ||
| 157 | kfree(data); | ||
| 158 | |||
| 159 | return 0; | ||
| 160 | } | ||
| 161 | |||
| 162 | static struct platform_driver sunxi_reset_driver = { | ||
| 163 | .probe = sunxi_reset_probe, | ||
| 164 | .remove = sunxi_reset_remove, | ||
| 165 | .driver = { | ||
| 166 | .name = "sunxi-reset", | ||
| 167 | .owner = THIS_MODULE, | ||
| 168 | .of_match_table = sunxi_reset_dt_ids, | ||
| 169 | }, | ||
| 170 | }; | ||
| 171 | module_platform_driver(sunxi_reset_driver); | ||
| 172 | |||
| 173 | MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com"); | ||
| 174 | MODULE_DESCRIPTION("Allwinner SoCs Reset Controller Driver"); | ||
| 175 | MODULE_LICENSE("GPL"); | ||
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 007730222116..b1328a45b095 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig | |||
| @@ -304,6 +304,17 @@ config RTC_DRV_ISL12022 | |||
| 304 | This driver can also be built as a module. If so, the module | 304 | This driver can also be built as a module. If so, the module |
| 305 | will be called rtc-isl12022. | 305 | will be called rtc-isl12022. |
| 306 | 306 | ||
| 307 | config RTC_DRV_ISL12057 | ||
| 308 | depends on I2C | ||
| 309 | select REGMAP_I2C | ||
| 310 | tristate "Intersil ISL12057" | ||
| 311 | help | ||
| 312 | If you say yes here you get support for the Intersil ISL12057 | ||
| 313 | I2C RTC chip. | ||
| 314 | |||
| 315 | This driver can also be built as a module. If so, the module | ||
| 316 | will be called rtc-isl12057. | ||
| 317 | |||
| 307 | config RTC_DRV_X1205 | 318 | config RTC_DRV_X1205 |
| 308 | tristate "Xicor/Intersil X1205" | 319 | tristate "Xicor/Intersil X1205" |
| 309 | help | 320 | help |
| @@ -1104,6 +1115,13 @@ config RTC_DRV_SUN4V | |||
| 1104 | If you say Y here you will get support for the Hypervisor | 1115 | If you say Y here you will get support for the Hypervisor |
| 1105 | based RTC on SUN4V systems. | 1116 | based RTC on SUN4V systems. |
| 1106 | 1117 | ||
| 1118 | config RTC_DRV_SUNXI | ||
| 1119 | tristate "Allwinner sun4i/sun7i RTC" | ||
| 1120 | depends on ARCH_SUNXI | ||
| 1121 | help | ||
| 1122 | If you say Y here you will get support for the RTC found on | ||
| 1123 | Allwinner A10/A20. | ||
| 1124 | |||
| 1107 | config RTC_DRV_STARFIRE | 1125 | config RTC_DRV_STARFIRE |
| 1108 | bool "Starfire RTC" | 1126 | bool "Starfire RTC" |
| 1109 | depends on SPARC64 | 1127 | depends on SPARC64 |
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 27b4bd884066..c00741a0bf10 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile | |||
| @@ -58,6 +58,7 @@ obj-$(CONFIG_RTC_DRV_HID_SENSOR_TIME) += rtc-hid-sensor-time.o | |||
| 58 | obj-$(CONFIG_RTC_DRV_IMXDI) += rtc-imxdi.o | 58 | obj-$(CONFIG_RTC_DRV_IMXDI) += rtc-imxdi.o |
| 59 | obj-$(CONFIG_RTC_DRV_ISL1208) += rtc-isl1208.o | 59 | obj-$(CONFIG_RTC_DRV_ISL1208) += rtc-isl1208.o |
| 60 | obj-$(CONFIG_RTC_DRV_ISL12022) += rtc-isl12022.o | 60 | obj-$(CONFIG_RTC_DRV_ISL12022) += rtc-isl12022.o |
| 61 | obj-$(CONFIG_RTC_DRV_ISL12057) += rtc-isl12057.o | ||
| 61 | obj-$(CONFIG_RTC_DRV_JZ4740) += rtc-jz4740.o | 62 | obj-$(CONFIG_RTC_DRV_JZ4740) += rtc-jz4740.o |
| 62 | obj-$(CONFIG_RTC_DRV_LP8788) += rtc-lp8788.o | 63 | obj-$(CONFIG_RTC_DRV_LP8788) += rtc-lp8788.o |
| 63 | obj-$(CONFIG_RTC_DRV_LPC32XX) += rtc-lpc32xx.o | 64 | obj-$(CONFIG_RTC_DRV_LPC32XX) += rtc-lpc32xx.o |
| @@ -117,6 +118,7 @@ obj-$(CONFIG_RTC_DRV_STARFIRE) += rtc-starfire.o | |||
| 117 | obj-$(CONFIG_RTC_DRV_STK17TA8) += rtc-stk17ta8.o | 118 | obj-$(CONFIG_RTC_DRV_STK17TA8) += rtc-stk17ta8.o |
| 118 | obj-$(CONFIG_RTC_DRV_STMP) += rtc-stmp3xxx.o | 119 | obj-$(CONFIG_RTC_DRV_STMP) += rtc-stmp3xxx.o |
| 119 | obj-$(CONFIG_RTC_DRV_SUN4V) += rtc-sun4v.o | 120 | obj-$(CONFIG_RTC_DRV_SUN4V) += rtc-sun4v.o |
| 121 | obj-$(CONFIG_RTC_DRV_SUNXI) += rtc-sunxi.o | ||
| 120 | obj-$(CONFIG_RTC_DRV_TEGRA) += rtc-tegra.o | 122 | obj-$(CONFIG_RTC_DRV_TEGRA) += rtc-tegra.o |
| 121 | obj-$(CONFIG_RTC_DRV_TEST) += rtc-test.o | 123 | obj-$(CONFIG_RTC_DRV_TEST) += rtc-test.o |
| 122 | obj-$(CONFIG_RTC_DRV_TILE) += rtc-tile.o | 124 | obj-$(CONFIG_RTC_DRV_TILE) += rtc-tile.o |
diff --git a/drivers/rtc/rtc-isl12057.c b/drivers/rtc/rtc-isl12057.c new file mode 100644 index 000000000000..7854a656628f --- /dev/null +++ b/drivers/rtc/rtc-isl12057.c | |||
| @@ -0,0 +1,310 @@ | |||
| 1 | /* | ||
| 2 | * rtc-isl12057 - Driver for Intersil ISL12057 I2C Real Time Clock | ||
| 3 | * | ||
| 4 | * Copyright (C) 2013, Arnaud EBALARD <arno@natisbad.org> | ||
| 5 | * | ||
| 6 | * This work is largely based on Intersil ISL1208 driver developed by | ||
| 7 | * Hebert Valerio Riedel <hvr@gnu.org>. | ||
| 8 | * | ||
| 9 | * Detailed datasheet on which this development is based is available here: | ||
| 10 | * | ||
| 11 | * http://natisbad.org/NAS2/refs/ISL12057.pdf | ||
| 12 | * | ||
| 13 | * This program is free software; you can redistribute it and/or modify | ||
| 14 | * it under the terms of the GNU General Public License as published by | ||
| 15 | * the Free Software Foundation; either version 2 of the License, or | ||
| 16 | * (at your option) any later version. | ||
| 17 | * | ||
| 18 | * This program is distributed in the hope that it will be useful, | ||
| 19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 21 | * GNU General Public License for more details. | ||
| 22 | */ | ||
| 23 | |||
| 24 | #include <linux/module.h> | ||
| 25 | #include <linux/mutex.h> | ||
| 26 | #include <linux/rtc.h> | ||
| 27 | #include <linux/i2c.h> | ||
| 28 | #include <linux/bcd.h> | ||
| 29 | #include <linux/rtc.h> | ||
| 30 | #include <linux/of.h> | ||
| 31 | #include <linux/of_device.h> | ||
| 32 | #include <linux/regmap.h> | ||
| 33 | |||
| 34 | #define DRV_NAME "rtc-isl12057" | ||
| 35 | |||
| 36 | /* RTC section */ | ||
| 37 | #define ISL12057_REG_RTC_SC 0x00 /* Seconds */ | ||
| 38 | #define ISL12057_REG_RTC_MN 0x01 /* Minutes */ | ||
| 39 | #define ISL12057_REG_RTC_HR 0x02 /* Hours */ | ||
| 40 | #define ISL12057_REG_RTC_HR_PM BIT(5) /* AM/PM bit in 12h format */ | ||
| 41 | #define ISL12057_REG_RTC_HR_MIL BIT(6) /* 24h/12h format */ | ||
| 42 | #define ISL12057_REG_RTC_DW 0x03 /* Day of the Week */ | ||
| 43 | #define ISL12057_REG_RTC_DT 0x04 /* Date */ | ||
| 44 | #define ISL12057_REG_RTC_MO 0x05 /* Month */ | ||
| 45 | #define ISL12057_REG_RTC_YR 0x06 /* Year */ | ||
| 46 | #define ISL12057_RTC_SEC_LEN 7 | ||
| 47 | |||
| 48 | /* Alarm 1 section */ | ||
| 49 | #define ISL12057_REG_A1_SC 0x07 /* Alarm 1 Seconds */ | ||
| 50 | #define ISL12057_REG_A1_MN 0x08 /* Alarm 1 Minutes */ | ||
| 51 | #define ISL12057_REG_A1_HR 0x09 /* Alarm 1 Hours */ | ||
| 52 | #define ISL12057_REG_A1_HR_PM BIT(5) /* AM/PM bit in 12h format */ | ||
| 53 | #define ISL12057_REG_A1_HR_MIL BIT(6) /* 24h/12h format */ | ||
| 54 | #define ISL12057_REG_A1_DWDT 0x0A /* Alarm 1 Date / Day of the week */ | ||
| 55 | #define ISL12057_REG_A1_DWDT_B BIT(6) /* DW / DT selection bit */ | ||
| 56 | #define ISL12057_A1_SEC_LEN 4 | ||
| 57 | |||
| 58 | /* Alarm 2 section */ | ||
| 59 | #define ISL12057_REG_A2_MN 0x0B /* Alarm 2 Minutes */ | ||
| 60 | #define ISL12057_REG_A2_HR 0x0C /* Alarm 2 Hours */ | ||
| 61 | #define ISL12057_REG_A2_DWDT 0x0D /* Alarm 2 Date / Day of the week */ | ||
| 62 | #define ISL12057_A2_SEC_LEN 3 | ||
| 63 | |||
| 64 | /* Control/Status registers */ | ||
| 65 | #define ISL12057_REG_INT 0x0E | ||
| 66 | #define ISL12057_REG_INT_A1IE BIT(0) /* Alarm 1 interrupt enable bit */ | ||
| 67 | #define ISL12057_REG_INT_A2IE BIT(1) /* Alarm 2 interrupt enable bit */ | ||
| 68 | #define ISL12057_REG_INT_INTCN BIT(2) /* Interrupt control enable bit */ | ||
| 69 | #define ISL12057_REG_INT_RS1 BIT(3) /* Freq out control bit 1 */ | ||
| 70 | #define ISL12057_REG_INT_RS2 BIT(4) /* Freq out control bit 2 */ | ||
| 71 | #define ISL12057_REG_INT_EOSC BIT(7) /* Oscillator enable bit */ | ||
| 72 | |||
| 73 | #define ISL12057_REG_SR 0x0F | ||
| 74 | #define ISL12057_REG_SR_A1F BIT(0) /* Alarm 1 interrupt bit */ | ||
| 75 | #define ISL12057_REG_SR_A2F BIT(1) /* Alarm 2 interrupt bit */ | ||
| 76 | #define ISL12057_REG_SR_OSF BIT(7) /* Oscillator failure bit */ | ||
| 77 | |||
| 78 | /* Register memory map length */ | ||
| 79 | #define ISL12057_MEM_MAP_LEN 0x10 | ||
| 80 | |||
| 81 | struct isl12057_rtc_data { | ||
| 82 | struct regmap *regmap; | ||
| 83 | struct mutex lock; | ||
| 84 | }; | ||
| 85 | |||
| 86 | static void isl12057_rtc_regs_to_tm(struct rtc_time *tm, u8 *regs) | ||
| 87 | { | ||
| 88 | tm->tm_sec = bcd2bin(regs[ISL12057_REG_RTC_SC]); | ||
| 89 | tm->tm_min = bcd2bin(regs[ISL12057_REG_RTC_MN]); | ||
| 90 | |||
| 91 | if (regs[ISL12057_REG_RTC_HR] & ISL12057_REG_RTC_HR_MIL) { /* AM/PM */ | ||
| 92 | tm->tm_hour = bcd2bin(regs[ISL12057_REG_RTC_HR] & 0x0f); | ||
| 93 | if (regs[ISL12057_REG_RTC_HR] & ISL12057_REG_RTC_HR_PM) | ||
| 94 | tm->tm_hour += 12; | ||
| 95 | } else { /* 24 hour mode */ | ||
| 96 | tm->tm_hour = bcd2bin(regs[ISL12057_REG_RTC_HR] & 0x3f); | ||
| 97 | } | ||
| 98 | |||
| 99 | tm->tm_mday = bcd2bin(regs[ISL12057_REG_RTC_DT]); | ||
| 100 | tm->tm_wday = bcd2bin(regs[ISL12057_REG_RTC_DW]) - 1; /* starts at 1 */ | ||
| 101 | tm->tm_mon = bcd2bin(regs[ISL12057_REG_RTC_MO]) - 1; /* starts at 1 */ | ||
| 102 | tm->tm_year = bcd2bin(regs[ISL12057_REG_RTC_YR]) + 100; | ||
| 103 | } | ||
| 104 | |||
| 105 | static int isl12057_rtc_tm_to_regs(u8 *regs, struct rtc_time *tm) | ||
| 106 | { | ||
| 107 | /* | ||
| 108 | * The clock has an 8 bit wide bcd-coded register for the year. | ||
| 109 | * tm_year is an offset from 1900 and we are interested in the | ||
| 110 | * 2000-2099 range, so any value less than 100 is invalid. | ||
| 111 | */ | ||
| 112 | if (tm->tm_year < 100) | ||
| 113 | return -EINVAL; | ||
| 114 | |||
| 115 | regs[ISL12057_REG_RTC_SC] = bin2bcd(tm->tm_sec); | ||
| 116 | regs[ISL12057_REG_RTC_MN] = bin2bcd(tm->tm_min); | ||
| 117 | regs[ISL12057_REG_RTC_HR] = bin2bcd(tm->tm_hour); /* 24-hour format */ | ||
| 118 | regs[ISL12057_REG_RTC_DT] = bin2bcd(tm->tm_mday); | ||
| 119 | regs[ISL12057_REG_RTC_MO] = bin2bcd(tm->tm_mon + 1); | ||
| 120 | regs[ISL12057_REG_RTC_YR] = bin2bcd(tm->tm_year - 100); | ||
| 121 | regs[ISL12057_REG_RTC_DW] = bin2bcd(tm->tm_wday + 1); | ||
| 122 | |||
| 123 | return 0; | ||
| 124 | } | ||
| 125 | |||
| 126 | /* | ||
| 127 | * Try and match register bits w/ fixed null values to see whether we | ||
| 128 | * are dealing with an ISL12057. Note: this function is called early | ||
| 129 | * during init and hence does need mutex protection. | ||
| 130 | */ | ||
| 131 | static int isl12057_i2c_validate_chip(struct regmap *regmap) | ||
| 132 | { | ||
| 133 | u8 regs[ISL12057_MEM_MAP_LEN]; | ||
| 134 | static const u8 mask[ISL12057_MEM_MAP_LEN] = { 0x80, 0x80, 0x80, 0xf8, | ||
| 135 | 0xc0, 0x60, 0x00, 0x00, | ||
| 136 | 0x00, 0x00, 0x00, 0x00, | ||
| 137 | 0x00, 0x00, 0x60, 0x7c }; | ||
| 138 | int ret, i; | ||
| 139 | |||
| 140 | ret = regmap_bulk_read(regmap, 0, regs, ISL12057_MEM_MAP_LEN); | ||
| 141 | if (ret) | ||
| 142 | return ret; | ||
| 143 | |||
| 144 | for (i = 0; i < ISL12057_MEM_MAP_LEN; ++i) { | ||
| 145 | if (regs[i] & mask[i]) /* check if bits are cleared */ | ||
| 146 | return -ENODEV; | ||
| 147 | } | ||
| 148 | |||
| 149 | return 0; | ||
| 150 | } | ||
| 151 | |||
| 152 | static int isl12057_rtc_read_time(struct device *dev, struct rtc_time *tm) | ||
| 153 | { | ||
| 154 | struct isl12057_rtc_data *data = dev_get_drvdata(dev); | ||
| 155 | u8 regs[ISL12057_RTC_SEC_LEN]; | ||
| 156 | int ret; | ||
| 157 | |||
| 158 | mutex_lock(&data->lock); | ||
| 159 | ret = regmap_bulk_read(data->regmap, ISL12057_REG_RTC_SC, regs, | ||
| 160 | ISL12057_RTC_SEC_LEN); | ||
| 161 | mutex_unlock(&data->lock); | ||
| 162 | |||
| 163 | if (ret) { | ||
| 164 | dev_err(dev, "%s: RTC read failed\n", __func__); | ||
| 165 | return ret; | ||
| 166 | } | ||
| 167 | |||
| 168 | isl12057_rtc_regs_to_tm(tm, regs); | ||
| 169 | |||
| 170 | return rtc_valid_tm(tm); | ||
| 171 | } | ||
| 172 | |||
| 173 | static int isl12057_rtc_set_time(struct device *dev, struct rtc_time *tm) | ||
| 174 | { | ||
| 175 | struct isl12057_rtc_data *data = dev_get_drvdata(dev); | ||
| 176 | u8 regs[ISL12057_RTC_SEC_LEN]; | ||
| 177 | int ret; | ||
| 178 | |||
| 179 | ret = isl12057_rtc_tm_to_regs(regs, tm); | ||
| 180 | if (ret) | ||
| 181 | return ret; | ||
| 182 | |||
| 183 | mutex_lock(&data->lock); | ||
| 184 | ret = regmap_bulk_write(data->regmap, ISL12057_REG_RTC_SC, regs, | ||
| 185 | ISL12057_RTC_SEC_LEN); | ||
| 186 | mutex_unlock(&data->lock); | ||
| 187 | |||
| 188 | if (ret) | ||
| 189 | dev_err(dev, "%s: RTC write failed\n", __func__); | ||
| 190 | |||
| 191 | return ret; | ||
| 192 | } | ||
| 193 | |||
| 194 | /* | ||
| 195 | * Check current RTC status and enable/disable what needs to be. Return 0 if | ||
| 196 | * everything went ok and a negative value upon error. Note: this function | ||
| 197 | * is called early during init and hence does need mutex protection. | ||
| 198 | */ | ||
| 199 | static int isl12057_check_rtc_status(struct device *dev, struct regmap *regmap) | ||
| 200 | { | ||
| 201 | int ret; | ||
| 202 | |||
| 203 | /* Enable oscillator if not already running */ | ||
| 204 | ret = regmap_update_bits(regmap, ISL12057_REG_INT, | ||
| 205 | ISL12057_REG_INT_EOSC, 0); | ||
| 206 | if (ret < 0) { | ||
| 207 | dev_err(dev, "Unable to enable oscillator\n"); | ||
| 208 | return ret; | ||
| 209 | } | ||
| 210 | |||
| 211 | /* Clear oscillator failure bit if needed */ | ||
| 212 | ret = regmap_update_bits(regmap, ISL12057_REG_SR, | ||
| 213 | ISL12057_REG_SR_OSF, 0); | ||
| 214 | if (ret < 0) { | ||
| 215 | dev_err(dev, "Unable to clear oscillator failure bit\n"); | ||
| 216 | return ret; | ||
| 217 | } | ||
| 218 | |||
| 219 | /* Clear alarm bit if needed */ | ||
| 220 | ret = regmap_update_bits(regmap, ISL12057_REG_SR, | ||
| 221 | ISL12057_REG_SR_A1F, 0); | ||
| 222 | if (ret < 0) { | ||
| 223 | dev_err(dev, "Unable to clear alarm bit\n"); | ||
| 224 | return ret; | ||
| 225 | } | ||
| 226 | |||
| 227 | return 0; | ||
| 228 | } | ||
| 229 | |||
| 230 | static const struct rtc_class_ops rtc_ops = { | ||
| 231 | .read_time = isl12057_rtc_read_time, | ||
| 232 | .set_time = isl12057_rtc_set_time, | ||
| 233 | }; | ||
| 234 | |||
| 235 | static struct regmap_config isl12057_rtc_regmap_config = { | ||
| 236 | .reg_bits = 8, | ||
| 237 | .val_bits = 8, | ||
| 238 | }; | ||
| 239 | |||
| 240 | static int isl12057_probe(struct i2c_client *client, | ||
| 241 | const struct i2c_device_id *id) | ||
| 242 | { | ||
| 243 | struct device *dev = &client->dev; | ||
| 244 | struct isl12057_rtc_data *data; | ||
| 245 | struct rtc_device *rtc; | ||
| 246 | struct regmap *regmap; | ||
| 247 | int ret; | ||
| 248 | |||
| 249 | if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C | | ||
| 250 | I2C_FUNC_SMBUS_BYTE_DATA | | ||
| 251 | I2C_FUNC_SMBUS_I2C_BLOCK)) | ||
| 252 | return -ENODEV; | ||
| 253 | |||
| 254 | regmap = devm_regmap_init_i2c(client, &isl12057_rtc_regmap_config); | ||
| 255 | if (IS_ERR(regmap)) { | ||
| 256 | ret = PTR_ERR(regmap); | ||
| 257 | dev_err(dev, "regmap allocation failed: %d\n", ret); | ||
| 258 | return ret; | ||
| 259 | } | ||
| 260 | |||
| 261 | ret = isl12057_i2c_validate_chip(regmap); | ||
| 262 | if (ret) | ||
| 263 | return ret; | ||
| 264 | |||
| 265 | ret = isl12057_check_rtc_status(dev, regmap); | ||
| 266 | if (ret) | ||
| 267 | return ret; | ||
| 268 | |||
| 269 | data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); | ||
| 270 | if (!data) | ||
| 271 | return -ENOMEM; | ||
| 272 | |||
| 273 | mutex_init(&data->lock); | ||
| 274 | data->regmap = regmap; | ||
| 275 | dev_set_drvdata(dev, data); | ||
| 276 | |||
| 277 | rtc = devm_rtc_device_register(dev, DRV_NAME, &rtc_ops, THIS_MODULE); | ||
| 278 | if (IS_ERR(rtc)) | ||
| 279 | return PTR_ERR(rtc); | ||
| 280 | |||
| 281 | return 0; | ||
| 282 | } | ||
| 283 | |||
| 284 | #ifdef CONFIG_OF | ||
| 285 | static struct of_device_id isl12057_dt_match[] = { | ||
| 286 | { .compatible = "isl,isl12057" }, | ||
| 287 | { }, | ||
| 288 | }; | ||
| 289 | #endif | ||
| 290 | |||
| 291 | static const struct i2c_device_id isl12057_id[] = { | ||
| 292 | { "isl12057", 0 }, | ||
| 293 | { } | ||
| 294 | }; | ||
| 295 | MODULE_DEVICE_TABLE(i2c, isl12057_id); | ||
| 296 | |||
| 297 | static struct i2c_driver isl12057_driver = { | ||
| 298 | .driver = { | ||
| 299 | .name = DRV_NAME, | ||
| 300 | .owner = THIS_MODULE, | ||
| 301 | .of_match_table = of_match_ptr(isl12057_dt_match), | ||
| 302 | }, | ||
| 303 | .probe = isl12057_probe, | ||
| 304 | .id_table = isl12057_id, | ||
| 305 | }; | ||
| 306 | module_i2c_driver(isl12057_driver); | ||
| 307 | |||
| 308 | MODULE_AUTHOR("Arnaud EBALARD <arno@natisbad.org>"); | ||
| 309 | MODULE_DESCRIPTION("Intersil ISL12057 RTC driver"); | ||
| 310 | MODULE_LICENSE("GPL"); | ||
diff --git a/drivers/rtc/rtc-sunxi.c b/drivers/rtc/rtc-sunxi.c new file mode 100644 index 000000000000..68a35284e5ad --- /dev/null +++ b/drivers/rtc/rtc-sunxi.c | |||
| @@ -0,0 +1,523 @@ | |||
| 1 | /* | ||
| 2 | * An RTC driver for Allwinner A10/A20 | ||
| 3 | * | ||
| 4 | * Copyright (c) 2013, Carlo Caione <carlo.caione@gmail.com> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 14 | * more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License along | ||
| 17 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 18 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. | ||
| 19 | */ | ||
| 20 | |||
| 21 | #include <linux/delay.h> | ||
| 22 | #include <linux/err.h> | ||
| 23 | #include <linux/fs.h> | ||
| 24 | #include <linux/init.h> | ||
| 25 | #include <linux/interrupt.h> | ||
| 26 | #include <linux/io.h> | ||
| 27 | #include <linux/kernel.h> | ||
| 28 | #include <linux/module.h> | ||
| 29 | #include <linux/of.h> | ||
| 30 | #include <linux/of_address.h> | ||
| 31 | #include <linux/of_device.h> | ||
| 32 | #include <linux/platform_device.h> | ||
| 33 | #include <linux/rtc.h> | ||
| 34 | #include <linux/types.h> | ||
| 35 | |||
| 36 | #define SUNXI_LOSC_CTRL 0x0000 | ||
| 37 | #define SUNXI_LOSC_CTRL_RTC_HMS_ACC BIT(8) | ||
| 38 | #define SUNXI_LOSC_CTRL_RTC_YMD_ACC BIT(7) | ||
| 39 | |||
| 40 | #define SUNXI_RTC_YMD 0x0004 | ||
| 41 | |||
| 42 | #define SUNXI_RTC_HMS 0x0008 | ||
| 43 | |||
| 44 | #define SUNXI_ALRM_DHMS 0x000c | ||
| 45 | |||
| 46 | #define SUNXI_ALRM_EN 0x0014 | ||
| 47 | #define SUNXI_ALRM_EN_CNT_EN BIT(8) | ||
| 48 | |||
| 49 | #define SUNXI_ALRM_IRQ_EN 0x0018 | ||
| 50 | #define SUNXI_ALRM_IRQ_EN_CNT_IRQ_EN BIT(0) | ||
| 51 | |||
| 52 | #define SUNXI_ALRM_IRQ_STA 0x001c | ||
| 53 | #define SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND BIT(0) | ||
| 54 | |||
| 55 | #define SUNXI_MASK_DH 0x0000001f | ||
| 56 | #define SUNXI_MASK_SM 0x0000003f | ||
| 57 | #define SUNXI_MASK_M 0x0000000f | ||
| 58 | #define SUNXI_MASK_LY 0x00000001 | ||
| 59 | #define SUNXI_MASK_D 0x00000ffe | ||
| 60 | #define SUNXI_MASK_M 0x0000000f | ||
| 61 | |||
| 62 | #define SUNXI_GET(x, mask, shift) (((x) & ((mask) << (shift))) \ | ||
| 63 | >> (shift)) | ||
| 64 | |||
| 65 | #define SUNXI_SET(x, mask, shift) (((x) & (mask)) << (shift)) | ||
| 66 | |||
| 67 | /* | ||
| 68 | * Get date values | ||
| 69 | */ | ||
| 70 | #define SUNXI_DATE_GET_DAY_VALUE(x) SUNXI_GET(x, SUNXI_MASK_DH, 0) | ||
| 71 | #define SUNXI_DATE_GET_MON_VALUE(x) SUNXI_GET(x, SUNXI_MASK_M, 8) | ||
| 72 | #define SUNXI_DATE_GET_YEAR_VALUE(x, mask) SUNXI_GET(x, mask, 16) | ||
| 73 | |||
| 74 | /* | ||
| 75 | * Get time values | ||
| 76 | */ | ||
| 77 | #define SUNXI_TIME_GET_SEC_VALUE(x) SUNXI_GET(x, SUNXI_MASK_SM, 0) | ||
| 78 | #define SUNXI_TIME_GET_MIN_VALUE(x) SUNXI_GET(x, SUNXI_MASK_SM, 8) | ||
| 79 | #define SUNXI_TIME_GET_HOUR_VALUE(x) SUNXI_GET(x, SUNXI_MASK_DH, 16) | ||
| 80 | |||
| 81 | /* | ||
| 82 | * Get alarm values | ||
| 83 | */ | ||
| 84 | #define SUNXI_ALRM_GET_SEC_VALUE(x) SUNXI_GET(x, SUNXI_MASK_SM, 0) | ||
| 85 | #define SUNXI_ALRM_GET_MIN_VALUE(x) SUNXI_GET(x, SUNXI_MASK_SM, 8) | ||
| 86 | #define SUNXI_ALRM_GET_HOUR_VALUE(x) SUNXI_GET(x, SUNXI_MASK_DH, 16) | ||
| 87 | |||
| 88 | /* | ||
| 89 | * Set date values | ||
| 90 | */ | ||
| 91 | #define SUNXI_DATE_SET_DAY_VALUE(x) SUNXI_DATE_GET_DAY_VALUE(x) | ||
| 92 | #define SUNXI_DATE_SET_MON_VALUE(x) SUNXI_SET(x, SUNXI_MASK_M, 8) | ||
| 93 | #define SUNXI_DATE_SET_YEAR_VALUE(x, mask) SUNXI_SET(x, mask, 16) | ||
| 94 | #define SUNXI_LEAP_SET_VALUE(x, shift) SUNXI_SET(x, SUNXI_MASK_LY, shift) | ||
| 95 | |||
| 96 | /* | ||
| 97 | * Set time values | ||
| 98 | */ | ||
| 99 | #define SUNXI_TIME_SET_SEC_VALUE(x) SUNXI_TIME_GET_SEC_VALUE(x) | ||
| 100 | #define SUNXI_TIME_SET_MIN_VALUE(x) SUNXI_SET(x, SUNXI_MASK_SM, 8) | ||
| 101 | #define SUNXI_TIME_SET_HOUR_VALUE(x) SUNXI_SET(x, SUNXI_MASK_DH, 16) | ||
| 102 | |||
| 103 | /* | ||
| 104 | * Set alarm values | ||
| 105 | */ | ||
| 106 | #define SUNXI_ALRM_SET_SEC_VALUE(x) SUNXI_ALRM_GET_SEC_VALUE(x) | ||
| 107 | #define SUNXI_ALRM_SET_MIN_VALUE(x) SUNXI_SET(x, SUNXI_MASK_SM, 8) | ||
| 108 | #define SUNXI_ALRM_SET_HOUR_VALUE(x) SUNXI_SET(x, SUNXI_MASK_DH, 16) | ||
| 109 | #define SUNXI_ALRM_SET_DAY_VALUE(x) SUNXI_SET(x, SUNXI_MASK_D, 21) | ||
| 110 | |||
| 111 | /* | ||
| 112 | * Time unit conversions | ||
| 113 | */ | ||
| 114 | #define SEC_IN_MIN 60 | ||
| 115 | #define SEC_IN_HOUR (60 * SEC_IN_MIN) | ||
| 116 | #define SEC_IN_DAY (24 * SEC_IN_HOUR) | ||
| 117 | |||
| 118 | /* | ||
| 119 | * The year parameter passed to the driver is usually an offset relative to | ||
| 120 | * the year 1900. This macro is used to convert this offset to another one | ||
| 121 | * relative to the minimum year allowed by the hardware. | ||
| 122 | */ | ||
| 123 | #define SUNXI_YEAR_OFF(x) ((x)->min - 1900) | ||
| 124 | |||
| 125 | /* | ||
| 126 | * min and max year are arbitrary set considering the limited range of the | ||
| 127 | * hardware register field | ||
| 128 | */ | ||
| 129 | struct sunxi_rtc_data_year { | ||
| 130 | unsigned int min; /* min year allowed */ | ||
| 131 | unsigned int max; /* max year allowed */ | ||
| 132 | unsigned int mask; /* mask for the year field */ | ||
| 133 | unsigned char leap_shift; /* bit shift to get the leap year */ | ||
| 134 | }; | ||
| 135 | |||
| 136 | static struct sunxi_rtc_data_year data_year_param[] = { | ||
| 137 | [0] = { | ||
| 138 | .min = 2010, | ||
| 139 | .max = 2073, | ||
| 140 | .mask = 0x3f, | ||
| 141 | .leap_shift = 22, | ||
| 142 | }, | ||
| 143 | [1] = { | ||
| 144 | .min = 1970, | ||
| 145 | .max = 2225, | ||
| 146 | .mask = 0xff, | ||
| 147 | .leap_shift = 24, | ||
| 148 | }, | ||
| 149 | }; | ||
| 150 | |||
| 151 | struct sunxi_rtc_dev { | ||
| 152 | struct rtc_device *rtc; | ||
| 153 | struct device *dev; | ||
| 154 | struct sunxi_rtc_data_year *data_year; | ||
| 155 | void __iomem *base; | ||
| 156 | int irq; | ||
| 157 | }; | ||
| 158 | |||
| 159 | static irqreturn_t sunxi_rtc_alarmirq(int irq, void *id) | ||
| 160 | { | ||
| 161 | struct sunxi_rtc_dev *chip = (struct sunxi_rtc_dev *) id; | ||
| 162 | u32 val; | ||
| 163 | |||
| 164 | val = readl(chip->base + SUNXI_ALRM_IRQ_STA); | ||
| 165 | |||
| 166 | if (val & SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND) { | ||
| 167 | val |= SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND; | ||
| 168 | writel(val, chip->base + SUNXI_ALRM_IRQ_STA); | ||
| 169 | |||
| 170 | rtc_update_irq(chip->rtc, 1, RTC_AF | RTC_IRQF); | ||
| 171 | |||
| 172 | return IRQ_HANDLED; | ||
| 173 | } | ||
| 174 | |||
| 175 | return IRQ_NONE; | ||
| 176 | } | ||
| 177 | |||
| 178 | static void sunxi_rtc_setaie(int to, struct sunxi_rtc_dev *chip) | ||
| 179 | { | ||
| 180 | u32 alrm_val = 0; | ||
| 181 | u32 alrm_irq_val = 0; | ||
| 182 | |||
| 183 | if (to) { | ||
| 184 | alrm_val = readl(chip->base + SUNXI_ALRM_EN); | ||
| 185 | alrm_val |= SUNXI_ALRM_EN_CNT_EN; | ||
| 186 | |||
| 187 | alrm_irq_val = readl(chip->base + SUNXI_ALRM_IRQ_EN); | ||
| 188 | alrm_irq_val |= SUNXI_ALRM_IRQ_EN_CNT_IRQ_EN; | ||
| 189 | } else { | ||
| 190 | writel(SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND, | ||
| 191 | chip->base + SUNXI_ALRM_IRQ_STA); | ||
| 192 | } | ||
| 193 | |||
| 194 | writel(alrm_val, chip->base + SUNXI_ALRM_EN); | ||
| 195 | writel(alrm_irq_val, chip->base + SUNXI_ALRM_IRQ_EN); | ||
| 196 | } | ||
| 197 | |||
| 198 | static int sunxi_rtc_getalarm(struct device *dev, struct rtc_wkalrm *wkalrm) | ||
| 199 | { | ||
| 200 | struct sunxi_rtc_dev *chip = dev_get_drvdata(dev); | ||
| 201 | struct rtc_time *alrm_tm = &wkalrm->time; | ||
| 202 | u32 alrm; | ||
| 203 | u32 alrm_en; | ||
| 204 | u32 date; | ||
| 205 | |||
| 206 | alrm = readl(chip->base + SUNXI_ALRM_DHMS); | ||
| 207 | date = readl(chip->base + SUNXI_RTC_YMD); | ||
| 208 | |||
| 209 | alrm_tm->tm_sec = SUNXI_ALRM_GET_SEC_VALUE(alrm); | ||
| 210 | alrm_tm->tm_min = SUNXI_ALRM_GET_MIN_VALUE(alrm); | ||
| 211 | alrm_tm->tm_hour = SUNXI_ALRM_GET_HOUR_VALUE(alrm); | ||
| 212 | |||
| 213 | alrm_tm->tm_mday = SUNXI_DATE_GET_DAY_VALUE(date); | ||
| 214 | alrm_tm->tm_mon = SUNXI_DATE_GET_MON_VALUE(date); | ||
| 215 | alrm_tm->tm_year = SUNXI_DATE_GET_YEAR_VALUE(date, | ||
| 216 | chip->data_year->mask); | ||
| 217 | |||
| 218 | alrm_tm->tm_mon -= 1; | ||
| 219 | |||
| 220 | /* | ||
| 221 | * switch from (data_year->min)-relative offset to | ||
| 222 | * a (1900)-relative one | ||
| 223 | */ | ||
| 224 | alrm_tm->tm_year += SUNXI_YEAR_OFF(chip->data_year); | ||
| 225 | |||
| 226 | alrm_en = readl(chip->base + SUNXI_ALRM_IRQ_EN); | ||
| 227 | if (alrm_en & SUNXI_ALRM_EN_CNT_EN) | ||
| 228 | wkalrm->enabled = 1; | ||
| 229 | |||
| 230 | return 0; | ||
| 231 | } | ||
| 232 | |||
| 233 | static int sunxi_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm) | ||
| 234 | { | ||
| 235 | struct sunxi_rtc_dev *chip = dev_get_drvdata(dev); | ||
| 236 | u32 date, time; | ||
| 237 | |||
| 238 | /* | ||
| 239 | * read again in case it changes | ||
| 240 | */ | ||
| 241 | do { | ||
| 242 | date = readl(chip->base + SUNXI_RTC_YMD); | ||
| 243 | time = readl(chip->base + SUNXI_RTC_HMS); | ||
| 244 | } while ((date != readl(chip->base + SUNXI_RTC_YMD)) || | ||
| 245 | (time != readl(chip->base + SUNXI_RTC_HMS))); | ||
| 246 | |||
| 247 | rtc_tm->tm_sec = SUNXI_TIME_GET_SEC_VALUE(time); | ||
| 248 | rtc_tm->tm_min = SUNXI_TIME_GET_MIN_VALUE(time); | ||
| 249 | rtc_tm->tm_hour = SUNXI_TIME_GET_HOUR_VALUE(time); | ||
| 250 | |||
| 251 | rtc_tm->tm_mday = SUNXI_DATE_GET_DAY_VALUE(date); | ||
| 252 | rtc_tm->tm_mon = SUNXI_DATE_GET_MON_VALUE(date); | ||
| 253 | rtc_tm->tm_year = SUNXI_DATE_GET_YEAR_VALUE(date, | ||
| 254 | chip->data_year->mask); | ||
| 255 | |||
| 256 | rtc_tm->tm_mon -= 1; | ||
| 257 | |||
| 258 | /* | ||
| 259 | * switch from (data_year->min)-relative offset to | ||
| 260 | * a (1900)-relative one | ||
| 261 | */ | ||
| 262 | rtc_tm->tm_year += SUNXI_YEAR_OFF(chip->data_year); | ||
| 263 | |||
| 264 | return rtc_valid_tm(rtc_tm); | ||
| 265 | } | ||
| 266 | |||
| 267 | static int sunxi_rtc_setalarm(struct device *dev, struct rtc_wkalrm *wkalrm) | ||
| 268 | { | ||
| 269 | struct sunxi_rtc_dev *chip = dev_get_drvdata(dev); | ||
| 270 | struct rtc_time *alrm_tm = &wkalrm->time; | ||
| 271 | struct rtc_time tm_now; | ||
| 272 | u32 alrm = 0; | ||
| 273 | unsigned long time_now = 0; | ||
| 274 | unsigned long time_set = 0; | ||
| 275 | unsigned long time_gap = 0; | ||
| 276 | unsigned long time_gap_day = 0; | ||
| 277 | unsigned long time_gap_hour = 0; | ||
| 278 | unsigned long time_gap_min = 0; | ||
| 279 | int ret = 0; | ||
| 280 | |||
| 281 | ret = sunxi_rtc_gettime(dev, &tm_now); | ||
| 282 | if (ret < 0) { | ||
| 283 | dev_err(dev, "Error in getting time\n"); | ||
| 284 | return -EINVAL; | ||
| 285 | } | ||
| 286 | |||
| 287 | rtc_tm_to_time(alrm_tm, &time_set); | ||
| 288 | rtc_tm_to_time(&tm_now, &time_now); | ||
| 289 | if (time_set <= time_now) { | ||
| 290 | dev_err(dev, "Date to set in the past\n"); | ||
| 291 | return -EINVAL; | ||
| 292 | } | ||
| 293 | |||
| 294 | time_gap = time_set - time_now; | ||
| 295 | time_gap_day = time_gap / SEC_IN_DAY; | ||
| 296 | time_gap -= time_gap_day * SEC_IN_DAY; | ||
| 297 | time_gap_hour = time_gap / SEC_IN_HOUR; | ||
| 298 | time_gap -= time_gap_hour * SEC_IN_HOUR; | ||
| 299 | time_gap_min = time_gap / SEC_IN_MIN; | ||
| 300 | time_gap -= time_gap_min * SEC_IN_MIN; | ||
| 301 | |||
| 302 | if (time_gap_day > 255) { | ||
| 303 | dev_err(dev, "Day must be in the range 0 - 255\n"); | ||
| 304 | return -EINVAL; | ||
| 305 | } | ||
| 306 | |||
| 307 | sunxi_rtc_setaie(0, chip); | ||
| 308 | writel(0, chip->base + SUNXI_ALRM_DHMS); | ||
| 309 | usleep_range(100, 300); | ||
| 310 | |||
| 311 | alrm = SUNXI_ALRM_SET_SEC_VALUE(time_gap) | | ||
| 312 | SUNXI_ALRM_SET_MIN_VALUE(time_gap_min) | | ||
| 313 | SUNXI_ALRM_SET_HOUR_VALUE(time_gap_hour) | | ||
| 314 | SUNXI_ALRM_SET_DAY_VALUE(time_gap_day); | ||
| 315 | writel(alrm, chip->base + SUNXI_ALRM_DHMS); | ||
| 316 | |||
| 317 | writel(0, chip->base + SUNXI_ALRM_IRQ_EN); | ||
| 318 | writel(SUNXI_ALRM_IRQ_EN_CNT_IRQ_EN, chip->base + SUNXI_ALRM_IRQ_EN); | ||
| 319 | |||
| 320 | sunxi_rtc_setaie(wkalrm->enabled, chip); | ||
| 321 | |||
| 322 | return 0; | ||
| 323 | } | ||
| 324 | |||
| 325 | static int sunxi_rtc_wait(struct sunxi_rtc_dev *chip, int offset, | ||
| 326 | unsigned int mask, unsigned int ms_timeout) | ||
| 327 | { | ||
| 328 | const unsigned long timeout = jiffies + msecs_to_jiffies(ms_timeout); | ||
| 329 | u32 reg; | ||
| 330 | |||
| 331 | do { | ||
| 332 | reg = readl(chip->base + offset); | ||
| 333 | reg &= mask; | ||
| 334 | |||
| 335 | if (reg == mask) | ||
| 336 | return 0; | ||
| 337 | |||
| 338 | } while (time_before(jiffies, timeout)); | ||
| 339 | |||
| 340 | return -ETIMEDOUT; | ||
| 341 | } | ||
| 342 | |||
| 343 | static int sunxi_rtc_settime(struct device *dev, struct rtc_time *rtc_tm) | ||
| 344 | { | ||
| 345 | struct sunxi_rtc_dev *chip = dev_get_drvdata(dev); | ||
| 346 | u32 date = 0; | ||
| 347 | u32 time = 0; | ||
| 348 | int year; | ||
| 349 | |||
| 350 | /* | ||
| 351 | * the input rtc_tm->tm_year is the offset relative to 1900. We use | ||
| 352 | * the SUNXI_YEAR_OFF macro to rebase it with respect to the min year | ||
| 353 | * allowed by the hardware | ||
| 354 | */ | ||
| 355 | |||
| 356 | year = rtc_tm->tm_year + 1900; | ||
| 357 | if (year < chip->data_year->min || year > chip->data_year->max) { | ||
| 358 | dev_err(dev, "rtc only supports year in range %d - %d\n", | ||
| 359 | chip->data_year->min, chip->data_year->max); | ||
| 360 | return -EINVAL; | ||
| 361 | } | ||
| 362 | |||
| 363 | rtc_tm->tm_year -= SUNXI_YEAR_OFF(chip->data_year); | ||
| 364 | rtc_tm->tm_mon += 1; | ||
| 365 | |||
| 366 | date = SUNXI_DATE_SET_DAY_VALUE(rtc_tm->tm_mday) | | ||
| 367 | SUNXI_DATE_SET_MON_VALUE(rtc_tm->tm_mon) | | ||
| 368 | SUNXI_DATE_SET_YEAR_VALUE(rtc_tm->tm_year, | ||
| 369 | chip->data_year->mask); | ||
| 370 | |||
| 371 | if (is_leap_year(year)) | ||
| 372 | date |= SUNXI_LEAP_SET_VALUE(1, chip->data_year->leap_shift); | ||
| 373 | |||
| 374 | time = SUNXI_TIME_SET_SEC_VALUE(rtc_tm->tm_sec) | | ||
| 375 | SUNXI_TIME_SET_MIN_VALUE(rtc_tm->tm_min) | | ||
| 376 | SUNXI_TIME_SET_HOUR_VALUE(rtc_tm->tm_hour); | ||
| 377 | |||
| 378 | writel(0, chip->base + SUNXI_RTC_HMS); | ||
| 379 | writel(0, chip->base + SUNXI_RTC_YMD); | ||
| 380 | |||
| 381 | writel(time, chip->base + SUNXI_RTC_HMS); | ||
| 382 | |||
| 383 | /* | ||
| 384 | * After writing the RTC HH-MM-SS register, the | ||
| 385 | * SUNXI_LOSC_CTRL_RTC_HMS_ACC bit is set and it will not | ||
| 386 | * be cleared until the real writing operation is finished | ||
| 387 | */ | ||
| 388 | |||
| 389 | if (sunxi_rtc_wait(chip, SUNXI_LOSC_CTRL, | ||
| 390 | SUNXI_LOSC_CTRL_RTC_HMS_ACC, 50)) { | ||
| 391 | dev_err(dev, "Failed to set rtc time.\n"); | ||
| 392 | return -1; | ||
| 393 | } | ||
| 394 | |||
| 395 | writel(date, chip->base + SUNXI_RTC_YMD); | ||
| 396 | |||
| 397 | /* | ||
| 398 | * After writing the RTC YY-MM-DD register, the | ||
| 399 | * SUNXI_LOSC_CTRL_RTC_YMD_ACC bit is set and it will not | ||
| 400 | * be cleared until the real writing operation is finished | ||
| 401 | */ | ||
| 402 | |||
| 403 | if (sunxi_rtc_wait(chip, SUNXI_LOSC_CTRL, | ||
| 404 | SUNXI_LOSC_CTRL_RTC_YMD_ACC, 50)) { | ||
| 405 | dev_err(dev, "Failed to set rtc time.\n"); | ||
| 406 | return -1; | ||
| 407 | } | ||
| 408 | |||
| 409 | return 0; | ||
| 410 | } | ||
| 411 | |||
| 412 | static int sunxi_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) | ||
| 413 | { | ||
| 414 | struct sunxi_rtc_dev *chip = dev_get_drvdata(dev); | ||
| 415 | |||
| 416 | if (!enabled) | ||
| 417 | sunxi_rtc_setaie(enabled, chip); | ||
| 418 | |||
| 419 | return 0; | ||
| 420 | } | ||
| 421 | |||
| 422 | static const struct rtc_class_ops sunxi_rtc_ops = { | ||
| 423 | .read_time = sunxi_rtc_gettime, | ||
| 424 | .set_time = sunxi_rtc_settime, | ||
| 425 | .read_alarm = sunxi_rtc_getalarm, | ||
| 426 | .set_alarm = sunxi_rtc_setalarm, | ||
| 427 | .alarm_irq_enable = sunxi_rtc_alarm_irq_enable | ||
| 428 | }; | ||
| 429 | |||
| 430 | static const struct of_device_id sunxi_rtc_dt_ids[] = { | ||
| 431 | { .compatible = "allwinner,sun4i-rtc", .data = &data_year_param[0] }, | ||
| 432 | { .compatible = "allwinner,sun7i-a20-rtc", .data = &data_year_param[1] }, | ||
| 433 | { /* sentinel */ }, | ||
| 434 | }; | ||
| 435 | MODULE_DEVICE_TABLE(of, sunxi_rtc_dt_ids); | ||
| 436 | |||
| 437 | static int sunxi_rtc_probe(struct platform_device *pdev) | ||
| 438 | { | ||
| 439 | struct sunxi_rtc_dev *chip; | ||
| 440 | struct resource *res; | ||
| 441 | const struct of_device_id *of_id; | ||
| 442 | int ret; | ||
| 443 | |||
| 444 | chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); | ||
| 445 | if (!chip) | ||
| 446 | return -ENOMEM; | ||
| 447 | |||
| 448 | platform_set_drvdata(pdev, chip); | ||
| 449 | chip->dev = &pdev->dev; | ||
| 450 | |||
| 451 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
| 452 | chip->base = devm_ioremap_resource(&pdev->dev, res); | ||
| 453 | if (IS_ERR(chip->base)) | ||
| 454 | return PTR_ERR(chip->base); | ||
| 455 | |||
| 456 | chip->irq = platform_get_irq(pdev, 0); | ||
| 457 | if (chip->irq < 0) { | ||
| 458 | dev_err(&pdev->dev, "No IRQ resource\n"); | ||
| 459 | return chip->irq; | ||
| 460 | } | ||
| 461 | ret = devm_request_irq(&pdev->dev, chip->irq, sunxi_rtc_alarmirq, | ||
| 462 | 0, dev_name(&pdev->dev), chip); | ||
| 463 | if (ret) { | ||
| 464 | dev_err(&pdev->dev, "Could not request IRQ\n"); | ||
| 465 | return ret; | ||
| 466 | } | ||
| 467 | |||
| 468 | of_id = of_match_device(sunxi_rtc_dt_ids, &pdev->dev); | ||
| 469 | if (!of_id) { | ||
| 470 | dev_err(&pdev->dev, "Unable to setup RTC data\n"); | ||
| 471 | return -ENODEV; | ||
| 472 | } | ||
| 473 | chip->data_year = (struct sunxi_rtc_data_year *) of_id->data; | ||
| 474 | |||
| 475 | /* clear the alarm count value */ | ||
| 476 | writel(0, chip->base + SUNXI_ALRM_DHMS); | ||
| 477 | |||
| 478 | /* disable alarm, not generate irq pending */ | ||
| 479 | writel(0, chip->base + SUNXI_ALRM_EN); | ||
| 480 | |||
| 481 | /* disable alarm week/cnt irq, unset to cpu */ | ||
| 482 | writel(0, chip->base + SUNXI_ALRM_IRQ_EN); | ||
| 483 | |||
| 484 | /* clear alarm week/cnt irq pending */ | ||
| 485 | writel(SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND, chip->base + | ||
| 486 | SUNXI_ALRM_IRQ_STA); | ||
| 487 | |||
| 488 | chip->rtc = rtc_device_register("rtc-sunxi", &pdev->dev, | ||
| 489 | &sunxi_rtc_ops, THIS_MODULE); | ||
| 490 | if (IS_ERR(chip->rtc)) { | ||
| 491 | dev_err(&pdev->dev, "unable to register device\n"); | ||
| 492 | return PTR_ERR(chip->rtc); | ||
| 493 | } | ||
| 494 | |||
| 495 | dev_info(&pdev->dev, "RTC enabled\n"); | ||
| 496 | |||
| 497 | return 0; | ||
| 498 | } | ||
| 499 | |||
| 500 | static int sunxi_rtc_remove(struct platform_device *pdev) | ||
| 501 | { | ||
| 502 | struct sunxi_rtc_dev *chip = platform_get_drvdata(pdev); | ||
| 503 | |||
| 504 | rtc_device_unregister(chip->rtc); | ||
| 505 | |||
| 506 | return 0; | ||
| 507 | } | ||
| 508 | |||
| 509 | static struct platform_driver sunxi_rtc_driver = { | ||
| 510 | .probe = sunxi_rtc_probe, | ||
| 511 | .remove = sunxi_rtc_remove, | ||
| 512 | .driver = { | ||
| 513 | .name = "sunxi-rtc", | ||
| 514 | .owner = THIS_MODULE, | ||
| 515 | .of_match_table = sunxi_rtc_dt_ids, | ||
| 516 | }, | ||
| 517 | }; | ||
| 518 | |||
| 519 | module_platform_driver(sunxi_rtc_driver); | ||
| 520 | |||
| 521 | MODULE_DESCRIPTION("sunxi RTC driver"); | ||
| 522 | MODULE_AUTHOR("Carlo Caione <carlo.caione@gmail.com>"); | ||
| 523 | MODULE_LICENSE("GPL"); | ||
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index eb1f1ef5fa2e..e2dd2fbec5ee 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig | |||
| @@ -395,7 +395,7 @@ config SPI_S3C24XX_FIQ | |||
| 395 | config SPI_S3C64XX | 395 | config SPI_S3C64XX |
| 396 | tristate "Samsung S3C64XX series type SPI" | 396 | tristate "Samsung S3C64XX series type SPI" |
| 397 | depends on PLAT_SAMSUNG | 397 | depends on PLAT_SAMSUNG |
| 398 | select S3C64XX_DMA if ARCH_S3C64XX | 398 | select S3C64XX_PL080 if ARCH_S3C64XX |
| 399 | help | 399 | help |
| 400 | SPI driver for Samsung S3C64XX and newer SoCs. | 400 | SPI driver for Samsung S3C64XX and newer SoCs. |
| 401 | 401 | ||
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c index 7d8103cd3e2e..be33d2b0613b 100644 --- a/drivers/tty/serial/sh-sci.c +++ b/drivers/tty/serial/sh-sci.c | |||
| @@ -23,35 +23,35 @@ | |||
| 23 | 23 | ||
| 24 | #undef DEBUG | 24 | #undef DEBUG |
| 25 | 25 | ||
| 26 | #include <linux/module.h> | 26 | #include <linux/clk.h> |
| 27 | #include <linux/console.h> | ||
| 28 | #include <linux/ctype.h> | ||
| 29 | #include <linux/cpufreq.h> | ||
| 30 | #include <linux/delay.h> | ||
| 31 | #include <linux/dmaengine.h> | ||
| 32 | #include <linux/dma-mapping.h> | ||
| 33 | #include <linux/err.h> | ||
| 27 | #include <linux/errno.h> | 34 | #include <linux/errno.h> |
| 28 | #include <linux/sh_dma.h> | 35 | #include <linux/init.h> |
| 29 | #include <linux/timer.h> | ||
| 30 | #include <linux/interrupt.h> | 36 | #include <linux/interrupt.h> |
| 31 | #include <linux/tty.h> | ||
| 32 | #include <linux/tty_flip.h> | ||
| 33 | #include <linux/serial.h> | ||
| 34 | #include <linux/major.h> | ||
| 35 | #include <linux/string.h> | ||
| 36 | #include <linux/sysrq.h> | ||
| 37 | #include <linux/ioport.h> | 37 | #include <linux/ioport.h> |
| 38 | #include <linux/major.h> | ||
| 39 | #include <linux/module.h> | ||
| 38 | #include <linux/mm.h> | 40 | #include <linux/mm.h> |
| 39 | #include <linux/init.h> | ||
| 40 | #include <linux/delay.h> | ||
| 41 | #include <linux/console.h> | ||
| 42 | #include <linux/platform_device.h> | ||
| 43 | #include <linux/serial_sci.h> | ||
| 44 | #include <linux/notifier.h> | 41 | #include <linux/notifier.h> |
| 42 | #include <linux/of.h> | ||
| 43 | #include <linux/platform_device.h> | ||
| 45 | #include <linux/pm_runtime.h> | 44 | #include <linux/pm_runtime.h> |
| 46 | #include <linux/cpufreq.h> | ||
| 47 | #include <linux/clk.h> | ||
| 48 | #include <linux/ctype.h> | ||
| 49 | #include <linux/err.h> | ||
| 50 | #include <linux/dmaengine.h> | ||
| 51 | #include <linux/dma-mapping.h> | ||
| 52 | #include <linux/scatterlist.h> | 45 | #include <linux/scatterlist.h> |
| 46 | #include <linux/serial.h> | ||
| 47 | #include <linux/serial_sci.h> | ||
| 48 | #include <linux/sh_dma.h> | ||
| 53 | #include <linux/slab.h> | 49 | #include <linux/slab.h> |
| 54 | #include <linux/gpio.h> | 50 | #include <linux/string.h> |
| 51 | #include <linux/sysrq.h> | ||
| 52 | #include <linux/timer.h> | ||
| 53 | #include <linux/tty.h> | ||
| 54 | #include <linux/tty_flip.h> | ||
| 55 | 55 | ||
| 56 | #ifdef CONFIG_SUPERH | 56 | #ifdef CONFIG_SUPERH |
| 57 | #include <asm/sh_bios.h> | 57 | #include <asm/sh_bios.h> |
| @@ -59,11 +59,32 @@ | |||
| 59 | 59 | ||
| 60 | #include "sh-sci.h" | 60 | #include "sh-sci.h" |
| 61 | 61 | ||
| 62 | /* Offsets into the sci_port->irqs array */ | ||
| 63 | enum { | ||
| 64 | SCIx_ERI_IRQ, | ||
| 65 | SCIx_RXI_IRQ, | ||
| 66 | SCIx_TXI_IRQ, | ||
| 67 | SCIx_BRI_IRQ, | ||
| 68 | SCIx_NR_IRQS, | ||
| 69 | |||
| 70 | SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */ | ||
| 71 | }; | ||
| 72 | |||
| 73 | #define SCIx_IRQ_IS_MUXED(port) \ | ||
| 74 | ((port)->irqs[SCIx_ERI_IRQ] == \ | ||
| 75 | (port)->irqs[SCIx_RXI_IRQ]) || \ | ||
| 76 | ((port)->irqs[SCIx_ERI_IRQ] && \ | ||
| 77 | ((port)->irqs[SCIx_RXI_IRQ] < 0)) | ||
| 78 | |||
| 62 | struct sci_port { | 79 | struct sci_port { |
| 63 | struct uart_port port; | 80 | struct uart_port port; |
| 64 | 81 | ||
| 65 | /* Platform configuration */ | 82 | /* Platform configuration */ |
| 66 | struct plat_sci_port *cfg; | 83 | struct plat_sci_port *cfg; |
| 84 | int overrun_bit; | ||
| 85 | unsigned int error_mask; | ||
| 86 | unsigned int sampling_rate; | ||
| 87 | |||
| 67 | 88 | ||
| 68 | /* Break timer */ | 89 | /* Break timer */ |
| 69 | struct timer_list break_timer; | 90 | struct timer_list break_timer; |
| @@ -74,8 +95,8 @@ struct sci_port { | |||
| 74 | /* Function clock */ | 95 | /* Function clock */ |
| 75 | struct clk *fclk; | 96 | struct clk *fclk; |
| 76 | 97 | ||
| 98 | int irqs[SCIx_NR_IRQS]; | ||
| 77 | char *irqstr[SCIx_NR_IRQS]; | 99 | char *irqstr[SCIx_NR_IRQS]; |
| 78 | char *gpiostr[SCIx_NR_FNS]; | ||
| 79 | 100 | ||
| 80 | struct dma_chan *chan_tx; | 101 | struct dma_chan *chan_tx; |
| 81 | struct dma_chan *chan_rx; | 102 | struct dma_chan *chan_rx; |
| @@ -421,9 +442,9 @@ static void sci_port_enable(struct sci_port *sci_port) | |||
| 421 | 442 | ||
| 422 | pm_runtime_get_sync(sci_port->port.dev); | 443 | pm_runtime_get_sync(sci_port->port.dev); |
| 423 | 444 | ||
| 424 | clk_enable(sci_port->iclk); | 445 | clk_prepare_enable(sci_port->iclk); |
| 425 | sci_port->port.uartclk = clk_get_rate(sci_port->iclk); | 446 | sci_port->port.uartclk = clk_get_rate(sci_port->iclk); |
| 426 | clk_enable(sci_port->fclk); | 447 | clk_prepare_enable(sci_port->fclk); |
| 427 | } | 448 | } |
| 428 | 449 | ||
| 429 | static void sci_port_disable(struct sci_port *sci_port) | 450 | static void sci_port_disable(struct sci_port *sci_port) |
| @@ -431,8 +452,16 @@ static void sci_port_disable(struct sci_port *sci_port) | |||
| 431 | if (!sci_port->port.dev) | 452 | if (!sci_port->port.dev) |
| 432 | return; | 453 | return; |
| 433 | 454 | ||
| 434 | clk_disable(sci_port->fclk); | 455 | /* Cancel the break timer to ensure that the timer handler will not try |
| 435 | clk_disable(sci_port->iclk); | 456 | * to access the hardware with clocks and power disabled. Reset the |
| 457 | * break flag to make the break debouncing state machine ready for the | ||
| 458 | * next break. | ||
| 459 | */ | ||
| 460 | del_timer_sync(&sci_port->break_timer); | ||
| 461 | sci_port->break_flag = 0; | ||
| 462 | |||
| 463 | clk_disable_unprepare(sci_port->fclk); | ||
| 464 | clk_disable_unprepare(sci_port->iclk); | ||
| 436 | 465 | ||
| 437 | pm_runtime_put_sync(sci_port->port.dev); | 466 | pm_runtime_put_sync(sci_port->port.dev); |
| 438 | } | 467 | } |
| @@ -557,7 +586,7 @@ static inline int sci_rxd_in(struct uart_port *port) | |||
| 557 | return 1; | 586 | return 1; |
| 558 | 587 | ||
| 559 | /* Cast for ARM damage */ | 588 | /* Cast for ARM damage */ |
| 560 | return !!__raw_readb((void __iomem *)s->cfg->port_reg); | 589 | return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg); |
| 561 | } | 590 | } |
| 562 | 591 | ||
| 563 | /* ********************************************************************** * | 592 | /* ********************************************************************** * |
| @@ -733,8 +762,6 @@ static void sci_break_timer(unsigned long data) | |||
| 733 | { | 762 | { |
| 734 | struct sci_port *port = (struct sci_port *)data; | 763 | struct sci_port *port = (struct sci_port *)data; |
| 735 | 764 | ||
| 736 | sci_port_enable(port); | ||
| 737 | |||
| 738 | if (sci_rxd_in(&port->port) == 0) { | 765 | if (sci_rxd_in(&port->port) == 0) { |
| 739 | port->break_flag = 1; | 766 | port->break_flag = 1; |
| 740 | sci_schedule_break_timer(port); | 767 | sci_schedule_break_timer(port); |
| @@ -744,8 +771,6 @@ static void sci_break_timer(unsigned long data) | |||
| 744 | sci_schedule_break_timer(port); | 771 | sci_schedule_break_timer(port); |
| 745 | } else | 772 | } else |
| 746 | port->break_flag = 0; | 773 | port->break_flag = 0; |
| 747 | |||
| 748 | sci_port_disable(port); | ||
| 749 | } | 774 | } |
| 750 | 775 | ||
| 751 | static int sci_handle_errors(struct uart_port *port) | 776 | static int sci_handle_errors(struct uart_port *port) |
| @@ -755,19 +780,15 @@ static int sci_handle_errors(struct uart_port *port) | |||
| 755 | struct tty_port *tport = &port->state->port; | 780 | struct tty_port *tport = &port->state->port; |
| 756 | struct sci_port *s = to_sci_port(port); | 781 | struct sci_port *s = to_sci_port(port); |
| 757 | 782 | ||
| 758 | /* | 783 | /* Handle overruns */ |
| 759 | * Handle overruns, if supported. | 784 | if (status & (1 << s->overrun_bit)) { |
| 760 | */ | 785 | port->icount.overrun++; |
| 761 | if (s->cfg->overrun_bit != SCIx_NOT_SUPPORTED) { | ||
| 762 | if (status & (1 << s->cfg->overrun_bit)) { | ||
| 763 | port->icount.overrun++; | ||
| 764 | 786 | ||
| 765 | /* overrun error */ | 787 | /* overrun error */ |
| 766 | if (tty_insert_flip_char(tport, 0, TTY_OVERRUN)) | 788 | if (tty_insert_flip_char(tport, 0, TTY_OVERRUN)) |
| 767 | copied++; | 789 | copied++; |
| 768 | 790 | ||
| 769 | dev_notice(port->dev, "overrun error"); | 791 | dev_notice(port->dev, "overrun error"); |
| 770 | } | ||
| 771 | } | 792 | } |
| 772 | 793 | ||
| 773 | if (status & SCxSR_FER(port)) { | 794 | if (status & SCxSR_FER(port)) { |
| @@ -829,7 +850,7 @@ static int sci_handle_fifo_overrun(struct uart_port *port) | |||
| 829 | if (!reg->size) | 850 | if (!reg->size) |
| 830 | return 0; | 851 | return 0; |
| 831 | 852 | ||
| 832 | if ((serial_port_in(port, SCLSR) & (1 << s->cfg->overrun_bit))) { | 853 | if ((serial_port_in(port, SCLSR) & (1 << s->overrun_bit))) { |
| 833 | serial_port_out(port, SCLSR, 0); | 854 | serial_port_out(port, SCLSR, 0); |
| 834 | 855 | ||
| 835 | port->icount.overrun++; | 856 | port->icount.overrun++; |
| @@ -1075,19 +1096,19 @@ static int sci_request_irq(struct sci_port *port) | |||
| 1075 | 1096 | ||
| 1076 | for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) { | 1097 | for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) { |
| 1077 | struct sci_irq_desc *desc; | 1098 | struct sci_irq_desc *desc; |
| 1078 | unsigned int irq; | 1099 | int irq; |
| 1079 | 1100 | ||
| 1080 | if (SCIx_IRQ_IS_MUXED(port)) { | 1101 | if (SCIx_IRQ_IS_MUXED(port)) { |
| 1081 | i = SCIx_MUX_IRQ; | 1102 | i = SCIx_MUX_IRQ; |
| 1082 | irq = up->irq; | 1103 | irq = up->irq; |
| 1083 | } else { | 1104 | } else { |
| 1084 | irq = port->cfg->irqs[i]; | 1105 | irq = port->irqs[i]; |
| 1085 | 1106 | ||
| 1086 | /* | 1107 | /* |
| 1087 | * Certain port types won't support all of the | 1108 | * Certain port types won't support all of the |
| 1088 | * available interrupt sources. | 1109 | * available interrupt sources. |
| 1089 | */ | 1110 | */ |
| 1090 | if (unlikely(!irq)) | 1111 | if (unlikely(irq < 0)) |
| 1091 | continue; | 1112 | continue; |
| 1092 | } | 1113 | } |
| 1093 | 1114 | ||
| @@ -1112,7 +1133,7 @@ static int sci_request_irq(struct sci_port *port) | |||
| 1112 | 1133 | ||
| 1113 | out_noirq: | 1134 | out_noirq: |
| 1114 | while (--i >= 0) | 1135 | while (--i >= 0) |
| 1115 | free_irq(port->cfg->irqs[i], port); | 1136 | free_irq(port->irqs[i], port); |
| 1116 | 1137 | ||
| 1117 | out_nomem: | 1138 | out_nomem: |
| 1118 | while (--j >= 0) | 1139 | while (--j >= 0) |
| @@ -1130,16 +1151,16 @@ static void sci_free_irq(struct sci_port *port) | |||
| 1130 | * IRQ first. | 1151 | * IRQ first. |
| 1131 | */ | 1152 | */ |
| 1132 | for (i = 0; i < SCIx_NR_IRQS; i++) { | 1153 | for (i = 0; i < SCIx_NR_IRQS; i++) { |
| 1133 | unsigned int irq = port->cfg->irqs[i]; | 1154 | int irq = port->irqs[i]; |
| 1134 | 1155 | ||
| 1135 | /* | 1156 | /* |
| 1136 | * Certain port types won't support all of the available | 1157 | * Certain port types won't support all of the available |
| 1137 | * interrupt sources. | 1158 | * interrupt sources. |
| 1138 | */ | 1159 | */ |
| 1139 | if (unlikely(!irq)) | 1160 | if (unlikely(irq < 0)) |
| 1140 | continue; | 1161 | continue; |
| 1141 | 1162 | ||
| 1142 | free_irq(port->cfg->irqs[i], port); | 1163 | free_irq(port->irqs[i], port); |
| 1143 | kfree(port->irqstr[i]); | 1164 | kfree(port->irqstr[i]); |
| 1144 | 1165 | ||
| 1145 | if (SCIx_IRQ_IS_MUXED(port)) { | 1166 | if (SCIx_IRQ_IS_MUXED(port)) { |
| @@ -1149,67 +1170,6 @@ static void sci_free_irq(struct sci_port *port) | |||
| 1149 | } | 1170 | } |
| 1150 | } | 1171 | } |
| 1151 | 1172 | ||
| 1152 | static const char *sci_gpio_names[SCIx_NR_FNS] = { | ||
| 1153 | "sck", "rxd", "txd", "cts", "rts", | ||
| 1154 | }; | ||
| 1155 | |||
| 1156 | static const char *sci_gpio_str(unsigned int index) | ||
| 1157 | { | ||
| 1158 | return sci_gpio_names[index]; | ||
| 1159 | } | ||
| 1160 | |||
| 1161 | static void sci_init_gpios(struct sci_port *port) | ||
| 1162 | { | ||
| 1163 | struct uart_port *up = &port->port; | ||
| 1164 | int i; | ||
| 1165 | |||
| 1166 | if (!port->cfg) | ||
| 1167 | return; | ||
| 1168 | |||
| 1169 | for (i = 0; i < SCIx_NR_FNS; i++) { | ||
| 1170 | const char *desc; | ||
| 1171 | int ret; | ||
| 1172 | |||
| 1173 | if (!port->cfg->gpios[i]) | ||
| 1174 | continue; | ||
| 1175 | |||
| 1176 | desc = sci_gpio_str(i); | ||
| 1177 | |||
| 1178 | port->gpiostr[i] = kasprintf(GFP_KERNEL, "%s:%s", | ||
| 1179 | dev_name(up->dev), desc); | ||
| 1180 | |||
| 1181 | /* | ||
| 1182 | * If we've failed the allocation, we can still continue | ||
| 1183 | * on with a NULL string. | ||
| 1184 | */ | ||
| 1185 | if (!port->gpiostr[i]) | ||
| 1186 | dev_notice(up->dev, "%s string allocation failure\n", | ||
| 1187 | desc); | ||
| 1188 | |||
| 1189 | ret = gpio_request(port->cfg->gpios[i], port->gpiostr[i]); | ||
| 1190 | if (unlikely(ret != 0)) { | ||
| 1191 | dev_notice(up->dev, "failed %s gpio request\n", desc); | ||
| 1192 | |||
| 1193 | /* | ||
| 1194 | * If we can't get the GPIO for whatever reason, | ||
| 1195 | * no point in keeping the verbose string around. | ||
| 1196 | */ | ||
| 1197 | kfree(port->gpiostr[i]); | ||
| 1198 | } | ||
| 1199 | } | ||
| 1200 | } | ||
| 1201 | |||
| 1202 | static void sci_free_gpios(struct sci_port *port) | ||
| 1203 | { | ||
| 1204 | int i; | ||
| 1205 | |||
| 1206 | for (i = 0; i < SCIx_NR_FNS; i++) | ||
| 1207 | if (port->cfg->gpios[i]) { | ||
| 1208 | gpio_free(port->cfg->gpios[i]); | ||
| 1209 | kfree(port->gpiostr[i]); | ||
| 1210 | } | ||
| 1211 | } | ||
| 1212 | |||
| 1213 | static unsigned int sci_tx_empty(struct uart_port *port) | 1173 | static unsigned int sci_tx_empty(struct uart_port *port) |
| 1214 | { | 1174 | { |
| 1215 | unsigned short status = serial_port_in(port, SCxSR); | 1175 | unsigned short status = serial_port_in(port, SCxSR); |
| @@ -1309,7 +1269,7 @@ static int sci_dma_rx_push(struct sci_port *s, size_t count) | |||
| 1309 | } | 1269 | } |
| 1310 | 1270 | ||
| 1311 | if (room < count) | 1271 | if (room < count) |
| 1312 | dev_warn(port->dev, "Rx overrun: dropping %u bytes\n", | 1272 | dev_warn(port->dev, "Rx overrun: dropping %zu bytes\n", |
| 1313 | count - room); | 1273 | count - room); |
| 1314 | if (!room) | 1274 | if (!room) |
| 1315 | return room; | 1275 | return room; |
| @@ -1442,7 +1402,7 @@ static void work_fn_rx(struct work_struct *work) | |||
| 1442 | int count; | 1402 | int count; |
| 1443 | 1403 | ||
| 1444 | chan->device->device_control(chan, DMA_TERMINATE_ALL, 0); | 1404 | chan->device->device_control(chan, DMA_TERMINATE_ALL, 0); |
| 1445 | dev_dbg(port->dev, "Read %u bytes with cookie %d\n", | 1405 | dev_dbg(port->dev, "Read %zu bytes with cookie %d\n", |
| 1446 | sh_desc->partial, sh_desc->cookie); | 1406 | sh_desc->partial, sh_desc->cookie); |
| 1447 | 1407 | ||
| 1448 | spin_lock_irqsave(&port->lock, flags); | 1408 | spin_lock_irqsave(&port->lock, flags); |
| @@ -1655,7 +1615,7 @@ static void rx_timer_fn(unsigned long arg) | |||
| 1655 | 1615 | ||
| 1656 | if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { | 1616 | if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { |
| 1657 | scr &= ~0x4000; | 1617 | scr &= ~0x4000; |
| 1658 | enable_irq(s->cfg->irqs[1]); | 1618 | enable_irq(s->irqs[SCIx_RXI_IRQ]); |
| 1659 | } | 1619 | } |
| 1660 | serial_port_out(port, SCSCR, scr | SCSCR_RIE); | 1620 | serial_port_out(port, SCSCR, scr | SCSCR_RIE); |
| 1661 | dev_dbg(port->dev, "DMA Rx timed out\n"); | 1621 | dev_dbg(port->dev, "DMA Rx timed out\n"); |
| @@ -1691,16 +1651,17 @@ static void sci_request_dma(struct uart_port *port) | |||
| 1691 | s->chan_tx = chan; | 1651 | s->chan_tx = chan; |
| 1692 | sg_init_table(&s->sg_tx, 1); | 1652 | sg_init_table(&s->sg_tx, 1); |
| 1693 | /* UART circular tx buffer is an aligned page. */ | 1653 | /* UART circular tx buffer is an aligned page. */ |
| 1694 | BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK); | 1654 | BUG_ON((uintptr_t)port->state->xmit.buf & ~PAGE_MASK); |
| 1695 | sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf), | 1655 | sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf), |
| 1696 | UART_XMIT_SIZE, (int)port->state->xmit.buf & ~PAGE_MASK); | 1656 | UART_XMIT_SIZE, |
| 1657 | (uintptr_t)port->state->xmit.buf & ~PAGE_MASK); | ||
| 1697 | nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE); | 1658 | nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE); |
| 1698 | if (!nent) | 1659 | if (!nent) |
| 1699 | sci_tx_dma_release(s, false); | 1660 | sci_tx_dma_release(s, false); |
| 1700 | else | 1661 | else |
| 1701 | dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__, | 1662 | dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__, |
| 1702 | sg_dma_len(&s->sg_tx), | 1663 | sg_dma_len(&s->sg_tx), port->state->xmit.buf, |
| 1703 | port->state->xmit.buf, sg_dma_address(&s->sg_tx)); | 1664 | &sg_dma_address(&s->sg_tx)); |
| 1704 | 1665 | ||
| 1705 | s->sg_len_tx = nent; | 1666 | s->sg_len_tx = nent; |
| 1706 | 1667 | ||
| @@ -1740,7 +1701,7 @@ static void sci_request_dma(struct uart_port *port) | |||
| 1740 | 1701 | ||
| 1741 | sg_init_table(sg, 1); | 1702 | sg_init_table(sg, 1); |
| 1742 | sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx, | 1703 | sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx, |
| 1743 | (int)buf[i] & ~PAGE_MASK); | 1704 | (uintptr_t)buf[i] & ~PAGE_MASK); |
| 1744 | sg_dma_address(sg) = dma[i]; | 1705 | sg_dma_address(sg) = dma[i]; |
| 1745 | } | 1706 | } |
| 1746 | 1707 | ||
| @@ -1808,21 +1769,11 @@ static void sci_shutdown(struct uart_port *port) | |||
| 1808 | sci_free_irq(s); | 1769 | sci_free_irq(s); |
| 1809 | } | 1770 | } |
| 1810 | 1771 | ||
| 1811 | static unsigned int sci_scbrr_calc(unsigned int algo_id, unsigned int bps, | 1772 | static unsigned int sci_scbrr_calc(struct sci_port *s, unsigned int bps, |
| 1812 | unsigned long freq) | 1773 | unsigned long freq) |
| 1813 | { | 1774 | { |
| 1814 | switch (algo_id) { | 1775 | if (s->sampling_rate) |
| 1815 | case SCBRR_ALGO_1: | 1776 | return DIV_ROUND_CLOSEST(freq, s->sampling_rate * bps) - 1; |
| 1816 | return ((freq + 16 * bps) / (16 * bps) - 1); | ||
| 1817 | case SCBRR_ALGO_2: | ||
| 1818 | return ((freq + 16 * bps) / (32 * bps) - 1); | ||
| 1819 | case SCBRR_ALGO_3: | ||
| 1820 | return (((freq * 2) + 16 * bps) / (16 * bps) - 1); | ||
| 1821 | case SCBRR_ALGO_4: | ||
| 1822 | return (((freq * 2) + 16 * bps) / (32 * bps) - 1); | ||
| 1823 | case SCBRR_ALGO_5: | ||
| 1824 | return (((freq * 1000 / 32) / bps) - 1); | ||
| 1825 | } | ||
| 1826 | 1777 | ||
| 1827 | /* Warn, but use a safe default */ | 1778 | /* Warn, but use a safe default */ |
| 1828 | WARN_ON(1); | 1779 | WARN_ON(1); |
| @@ -1903,12 +1854,11 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios, | |||
| 1903 | 1854 | ||
| 1904 | baud = uart_get_baud_rate(port, termios, old, 0, max_baud); | 1855 | baud = uart_get_baud_rate(port, termios, old, 0, max_baud); |
| 1905 | if (likely(baud && port->uartclk)) { | 1856 | if (likely(baud && port->uartclk)) { |
| 1906 | if (s->cfg->scbrr_algo_id == SCBRR_ALGO_6) { | 1857 | if (s->cfg->type == PORT_HSCIF) { |
| 1907 | sci_baud_calc_hscif(baud, port->uartclk, &t, &srr, | 1858 | sci_baud_calc_hscif(baud, port->uartclk, &t, &srr, |
| 1908 | &cks); | 1859 | &cks); |
| 1909 | } else { | 1860 | } else { |
| 1910 | t = sci_scbrr_calc(s->cfg->scbrr_algo_id, baud, | 1861 | t = sci_scbrr_calc(s, baud, port->uartclk); |
| 1911 | port->uartclk); | ||
| 1912 | for (cks = 0; t >= 256 && cks <= 3; cks++) | 1862 | for (cks = 0; t >= 256 && cks <= 3; cks++) |
| 1913 | t >>= 2; | 1863 | t >>= 2; |
| 1914 | } | 1864 | } |
| @@ -2115,10 +2065,6 @@ static void sci_config_port(struct uart_port *port, int flags) | |||
| 2115 | 2065 | ||
| 2116 | static int sci_verify_port(struct uart_port *port, struct serial_struct *ser) | 2066 | static int sci_verify_port(struct uart_port *port, struct serial_struct *ser) |
| 2117 | { | 2067 | { |
| 2118 | struct sci_port *s = to_sci_port(port); | ||
| 2119 | |||
| 2120 | if (ser->irq != s->cfg->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs) | ||
| 2121 | return -EINVAL; | ||
| 2122 | if (ser->baud_base < 2400) | 2068 | if (ser->baud_base < 2400) |
| 2123 | /* No paper tape reader for Mitch.. */ | 2069 | /* No paper tape reader for Mitch.. */ |
| 2124 | return -EINVAL; | 2070 | return -EINVAL; |
| @@ -2151,11 +2097,13 @@ static struct uart_ops sci_uart_ops = { | |||
| 2151 | }; | 2097 | }; |
| 2152 | 2098 | ||
| 2153 | static int sci_init_single(struct platform_device *dev, | 2099 | static int sci_init_single(struct platform_device *dev, |
| 2154 | struct sci_port *sci_port, | 2100 | struct sci_port *sci_port, unsigned int index, |
| 2155 | unsigned int index, | 2101 | struct plat_sci_port *p, bool early) |
| 2156 | struct plat_sci_port *p) | ||
| 2157 | { | 2102 | { |
| 2158 | struct uart_port *port = &sci_port->port; | 2103 | struct uart_port *port = &sci_port->port; |
| 2104 | const struct resource *res; | ||
| 2105 | unsigned int sampling_rate; | ||
| 2106 | unsigned int i; | ||
| 2159 | int ret; | 2107 | int ret; |
| 2160 | 2108 | ||
| 2161 | sci_port->cfg = p; | 2109 | sci_port->cfg = p; |
| @@ -2164,31 +2112,76 @@ static int sci_init_single(struct platform_device *dev, | |||
| 2164 | port->iotype = UPIO_MEM; | 2112 | port->iotype = UPIO_MEM; |
| 2165 | port->line = index; | 2113 | port->line = index; |
| 2166 | 2114 | ||
| 2115 | res = platform_get_resource(dev, IORESOURCE_MEM, 0); | ||
| 2116 | if (res == NULL) | ||
| 2117 | return -ENOMEM; | ||
| 2118 | |||
| 2119 | port->mapbase = res->start; | ||
| 2120 | |||
| 2121 | for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) | ||
| 2122 | sci_port->irqs[i] = platform_get_irq(dev, i); | ||
| 2123 | |||
| 2124 | /* The SCI generates several interrupts. They can be muxed together or | ||
| 2125 | * connected to different interrupt lines. In the muxed case only one | ||
| 2126 | * interrupt resource is specified. In the non-muxed case three or four | ||
| 2127 | * interrupt resources are specified, as the BRI interrupt is optional. | ||
| 2128 | */ | ||
| 2129 | if (sci_port->irqs[0] < 0) | ||
| 2130 | return -ENXIO; | ||
| 2131 | |||
| 2132 | if (sci_port->irqs[1] < 0) { | ||
| 2133 | sci_port->irqs[1] = sci_port->irqs[0]; | ||
| 2134 | sci_port->irqs[2] = sci_port->irqs[0]; | ||
| 2135 | sci_port->irqs[3] = sci_port->irqs[0]; | ||
| 2136 | } | ||
| 2137 | |||
| 2138 | if (p->regtype == SCIx_PROBE_REGTYPE) { | ||
| 2139 | ret = sci_probe_regmap(p); | ||
| 2140 | if (unlikely(ret)) | ||
| 2141 | return ret; | ||
| 2142 | } | ||
| 2143 | |||
| 2167 | switch (p->type) { | 2144 | switch (p->type) { |
| 2168 | case PORT_SCIFB: | 2145 | case PORT_SCIFB: |
| 2169 | port->fifosize = 256; | 2146 | port->fifosize = 256; |
| 2147 | sci_port->overrun_bit = 9; | ||
| 2148 | sampling_rate = 16; | ||
| 2170 | break; | 2149 | break; |
| 2171 | case PORT_HSCIF: | 2150 | case PORT_HSCIF: |
| 2172 | port->fifosize = 128; | 2151 | port->fifosize = 128; |
| 2152 | sampling_rate = 0; | ||
| 2153 | sci_port->overrun_bit = 0; | ||
| 2173 | break; | 2154 | break; |
| 2174 | case PORT_SCIFA: | 2155 | case PORT_SCIFA: |
| 2175 | port->fifosize = 64; | 2156 | port->fifosize = 64; |
| 2157 | sci_port->overrun_bit = 9; | ||
| 2158 | sampling_rate = 16; | ||
| 2176 | break; | 2159 | break; |
| 2177 | case PORT_SCIF: | 2160 | case PORT_SCIF: |
| 2178 | port->fifosize = 16; | 2161 | port->fifosize = 16; |
| 2162 | if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) { | ||
| 2163 | sci_port->overrun_bit = 9; | ||
| 2164 | sampling_rate = 16; | ||
| 2165 | } else { | ||
| 2166 | sci_port->overrun_bit = 0; | ||
| 2167 | sampling_rate = 32; | ||
| 2168 | } | ||
| 2179 | break; | 2169 | break; |
| 2180 | default: | 2170 | default: |
| 2181 | port->fifosize = 1; | 2171 | port->fifosize = 1; |
| 2172 | sci_port->overrun_bit = 5; | ||
| 2173 | sampling_rate = 32; | ||
| 2182 | break; | 2174 | break; |
| 2183 | } | 2175 | } |
| 2184 | 2176 | ||
| 2185 | if (p->regtype == SCIx_PROBE_REGTYPE) { | 2177 | /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't |
| 2186 | ret = sci_probe_regmap(p); | 2178 | * match the SoC datasheet, this should be investigated. Let platform |
| 2187 | if (unlikely(ret)) | 2179 | * data override the sampling rate for now. |
| 2188 | return ret; | 2180 | */ |
| 2189 | } | 2181 | sci_port->sampling_rate = p->sampling_rate ? p->sampling_rate |
| 2182 | : sampling_rate; | ||
| 2190 | 2183 | ||
| 2191 | if (dev) { | 2184 | if (!early) { |
| 2192 | sci_port->iclk = clk_get(&dev->dev, "sci_ick"); | 2185 | sci_port->iclk = clk_get(&dev->dev, "sci_ick"); |
| 2193 | if (IS_ERR(sci_port->iclk)) { | 2186 | if (IS_ERR(sci_port->iclk)) { |
| 2194 | sci_port->iclk = clk_get(&dev->dev, "peripheral_clk"); | 2187 | sci_port->iclk = clk_get(&dev->dev, "peripheral_clk"); |
| @@ -2208,8 +2201,6 @@ static int sci_init_single(struct platform_device *dev, | |||
| 2208 | 2201 | ||
| 2209 | port->dev = &dev->dev; | 2202 | port->dev = &dev->dev; |
| 2210 | 2203 | ||
| 2211 | sci_init_gpios(sci_port); | ||
| 2212 | |||
| 2213 | pm_runtime_enable(&dev->dev); | 2204 | pm_runtime_enable(&dev->dev); |
| 2214 | } | 2205 | } |
| 2215 | 2206 | ||
| @@ -2220,32 +2211,22 @@ static int sci_init_single(struct platform_device *dev, | |||
| 2220 | /* | 2211 | /* |
| 2221 | * Establish some sensible defaults for the error detection. | 2212 | * Establish some sensible defaults for the error detection. |
| 2222 | */ | 2213 | */ |
| 2223 | if (!p->error_mask) | 2214 | sci_port->error_mask = (p->type == PORT_SCI) ? |
| 2224 | p->error_mask = (p->type == PORT_SCI) ? | ||
| 2225 | SCI_DEFAULT_ERROR_MASK : SCIF_DEFAULT_ERROR_MASK; | 2215 | SCI_DEFAULT_ERROR_MASK : SCIF_DEFAULT_ERROR_MASK; |
| 2226 | 2216 | ||
| 2227 | /* | 2217 | /* |
| 2228 | * Establish sensible defaults for the overrun detection, unless | 2218 | * Establish sensible defaults for the overrun detection, unless |
| 2229 | * the part has explicitly disabled support for it. | 2219 | * the part has explicitly disabled support for it. |
| 2230 | */ | 2220 | */ |
| 2231 | if (p->overrun_bit != SCIx_NOT_SUPPORTED) { | ||
| 2232 | if (p->type == PORT_SCI) | ||
| 2233 | p->overrun_bit = 5; | ||
| 2234 | else if (p->scbrr_algo_id == SCBRR_ALGO_4) | ||
| 2235 | p->overrun_bit = 9; | ||
| 2236 | else | ||
| 2237 | p->overrun_bit = 0; | ||
| 2238 | 2221 | ||
| 2239 | /* | 2222 | /* |
| 2240 | * Make the error mask inclusive of overrun detection, if | 2223 | * Make the error mask inclusive of overrun detection, if |
| 2241 | * supported. | 2224 | * supported. |
| 2242 | */ | 2225 | */ |
| 2243 | p->error_mask |= (1 << p->overrun_bit); | 2226 | sci_port->error_mask |= 1 << sci_port->overrun_bit; |
| 2244 | } | ||
| 2245 | 2227 | ||
| 2246 | port->mapbase = p->mapbase; | ||
| 2247 | port->type = p->type; | 2228 | port->type = p->type; |
| 2248 | port->flags = p->flags; | 2229 | port->flags = UPF_FIXED_PORT | p->flags; |
| 2249 | port->regshift = p->regshift; | 2230 | port->regshift = p->regshift; |
| 2250 | 2231 | ||
| 2251 | /* | 2232 | /* |
| @@ -2255,7 +2236,7 @@ static int sci_init_single(struct platform_device *dev, | |||
| 2255 | * | 2236 | * |
| 2256 | * For the muxed case there's nothing more to do. | 2237 | * For the muxed case there's nothing more to do. |
| 2257 | */ | 2238 | */ |
| 2258 | port->irq = p->irqs[SCIx_RXI_IRQ]; | 2239 | port->irq = sci_port->irqs[SCIx_RXI_IRQ]; |
| 2259 | port->irqflags = 0; | 2240 | port->irqflags = 0; |
| 2260 | 2241 | ||
| 2261 | port->serial_in = sci_serial_in; | 2242 | port->serial_in = sci_serial_in; |
| @@ -2270,8 +2251,6 @@ static int sci_init_single(struct platform_device *dev, | |||
| 2270 | 2251 | ||
| 2271 | static void sci_cleanup_single(struct sci_port *port) | 2252 | static void sci_cleanup_single(struct sci_port *port) |
| 2272 | { | 2253 | { |
| 2273 | sci_free_gpios(port); | ||
| 2274 | |||
| 2275 | clk_put(port->iclk); | 2254 | clk_put(port->iclk); |
| 2276 | clk_put(port->fclk); | 2255 | clk_put(port->fclk); |
| 2277 | 2256 | ||
| @@ -2387,7 +2366,7 @@ static int sci_probe_earlyprintk(struct platform_device *pdev) | |||
| 2387 | 2366 | ||
| 2388 | early_serial_console.index = pdev->id; | 2367 | early_serial_console.index = pdev->id; |
| 2389 | 2368 | ||
| 2390 | sci_init_single(NULL, &sci_ports[pdev->id], pdev->id, cfg); | 2369 | sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true); |
| 2391 | 2370 | ||
| 2392 | serial_console_setup(&early_serial_console, early_serial_buf); | 2371 | serial_console_setup(&early_serial_console, early_serial_buf); |
| 2393 | 2372 | ||
| @@ -2437,6 +2416,83 @@ static int sci_remove(struct platform_device *dev) | |||
| 2437 | return 0; | 2416 | return 0; |
| 2438 | } | 2417 | } |
| 2439 | 2418 | ||
| 2419 | struct sci_port_info { | ||
| 2420 | unsigned int type; | ||
| 2421 | unsigned int regtype; | ||
| 2422 | }; | ||
| 2423 | |||
| 2424 | static const struct of_device_id of_sci_match[] = { | ||
| 2425 | { | ||
| 2426 | .compatible = "renesas,scif", | ||
| 2427 | .data = (void *)&(const struct sci_port_info) { | ||
| 2428 | .type = PORT_SCIF, | ||
| 2429 | .regtype = SCIx_SH4_SCIF_REGTYPE, | ||
| 2430 | }, | ||
| 2431 | }, { | ||
| 2432 | .compatible = "renesas,scifa", | ||
| 2433 | .data = (void *)&(const struct sci_port_info) { | ||
| 2434 | .type = PORT_SCIFA, | ||
| 2435 | .regtype = SCIx_SCIFA_REGTYPE, | ||
| 2436 | }, | ||
| 2437 | }, { | ||
| 2438 | .compatible = "renesas,scifb", | ||
| 2439 | .data = (void *)&(const struct sci_port_info) { | ||
| 2440 | .type = PORT_SCIFB, | ||
| 2441 | .regtype = SCIx_SCIFB_REGTYPE, | ||
| 2442 | }, | ||
| 2443 | }, { | ||
| 2444 | .compatible = "renesas,hscif", | ||
| 2445 | .data = (void *)&(const struct sci_port_info) { | ||
| 2446 | .type = PORT_HSCIF, | ||
| 2447 | .regtype = SCIx_HSCIF_REGTYPE, | ||
| 2448 | }, | ||
| 2449 | }, { | ||
| 2450 | /* Terminator */ | ||
| 2451 | }, | ||
| 2452 | }; | ||
| 2453 | MODULE_DEVICE_TABLE(of, of_sci_match); | ||
| 2454 | |||
| 2455 | static struct plat_sci_port * | ||
| 2456 | sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id) | ||
| 2457 | { | ||
| 2458 | struct device_node *np = pdev->dev.of_node; | ||
| 2459 | const struct of_device_id *match; | ||
| 2460 | const struct sci_port_info *info; | ||
| 2461 | struct plat_sci_port *p; | ||
| 2462 | int id; | ||
| 2463 | |||
| 2464 | if (!IS_ENABLED(CONFIG_OF) || !np) | ||
| 2465 | return NULL; | ||
| 2466 | |||
| 2467 | match = of_match_node(of_sci_match, pdev->dev.of_node); | ||
| 2468 | if (!match) | ||
| 2469 | return NULL; | ||
| 2470 | |||
| 2471 | info = match->data; | ||
| 2472 | |||
| 2473 | p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL); | ||
| 2474 | if (!p) { | ||
| 2475 | dev_err(&pdev->dev, "failed to allocate DT config data\n"); | ||
| 2476 | return NULL; | ||
| 2477 | } | ||
| 2478 | |||
| 2479 | /* Get the line number for the aliases node. */ | ||
| 2480 | id = of_alias_get_id(np, "serial"); | ||
| 2481 | if (id < 0) { | ||
| 2482 | dev_err(&pdev->dev, "failed to get alias id (%d)\n", id); | ||
| 2483 | return NULL; | ||
| 2484 | } | ||
| 2485 | |||
| 2486 | *dev_id = id; | ||
| 2487 | |||
| 2488 | p->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF; | ||
| 2489 | p->type = info->type; | ||
| 2490 | p->regtype = info->regtype; | ||
| 2491 | p->scscr = SCSCR_RE | SCSCR_TE; | ||
| 2492 | |||
| 2493 | return p; | ||
| 2494 | } | ||
| 2495 | |||
| 2440 | static int sci_probe_single(struct platform_device *dev, | 2496 | static int sci_probe_single(struct platform_device *dev, |
| 2441 | unsigned int index, | 2497 | unsigned int index, |
| 2442 | struct plat_sci_port *p, | 2498 | struct plat_sci_port *p, |
| @@ -2454,7 +2510,7 @@ static int sci_probe_single(struct platform_device *dev, | |||
| 2454 | return -EINVAL; | 2510 | return -EINVAL; |
| 2455 | } | 2511 | } |
| 2456 | 2512 | ||
| 2457 | ret = sci_init_single(dev, sciport, index, p); | 2513 | ret = sci_init_single(dev, sciport, index, p, false); |
| 2458 | if (ret) | 2514 | if (ret) |
| 2459 | return ret; | 2515 | return ret; |
| 2460 | 2516 | ||
| @@ -2469,8 +2525,9 @@ static int sci_probe_single(struct platform_device *dev, | |||
| 2469 | 2525 | ||
| 2470 | static int sci_probe(struct platform_device *dev) | 2526 | static int sci_probe(struct platform_device *dev) |
| 2471 | { | 2527 | { |
| 2472 | struct plat_sci_port *p = dev_get_platdata(&dev->dev); | 2528 | struct plat_sci_port *p; |
| 2473 | struct sci_port *sp = &sci_ports[dev->id]; | 2529 | struct sci_port *sp; |
| 2530 | unsigned int dev_id; | ||
| 2474 | int ret; | 2531 | int ret; |
| 2475 | 2532 | ||
| 2476 | /* | 2533 | /* |
| @@ -2481,9 +2538,24 @@ static int sci_probe(struct platform_device *dev) | |||
| 2481 | if (is_early_platform_device(dev)) | 2538 | if (is_early_platform_device(dev)) |
| 2482 | return sci_probe_earlyprintk(dev); | 2539 | return sci_probe_earlyprintk(dev); |
| 2483 | 2540 | ||
| 2541 | if (dev->dev.of_node) { | ||
| 2542 | p = sci_parse_dt(dev, &dev_id); | ||
| 2543 | if (p == NULL) | ||
| 2544 | return -EINVAL; | ||
| 2545 | } else { | ||
| 2546 | p = dev->dev.platform_data; | ||
| 2547 | if (p == NULL) { | ||
| 2548 | dev_err(&dev->dev, "no platform data supplied\n"); | ||
| 2549 | return -EINVAL; | ||
| 2550 | } | ||
| 2551 | |||
| 2552 | dev_id = dev->id; | ||
| 2553 | } | ||
| 2554 | |||
| 2555 | sp = &sci_ports[dev_id]; | ||
| 2484 | platform_set_drvdata(dev, sp); | 2556 | platform_set_drvdata(dev, sp); |
| 2485 | 2557 | ||
| 2486 | ret = sci_probe_single(dev, dev->id, p, sp); | 2558 | ret = sci_probe_single(dev, dev_id, p, sp); |
| 2487 | if (ret) | 2559 | if (ret) |
| 2488 | return ret; | 2560 | return ret; |
| 2489 | 2561 | ||
| @@ -2535,6 +2607,7 @@ static struct platform_driver sci_driver = { | |||
| 2535 | .name = "sh-sci", | 2607 | .name = "sh-sci", |
| 2536 | .owner = THIS_MODULE, | 2608 | .owner = THIS_MODULE, |
| 2537 | .pm = &sci_dev_pm_ops, | 2609 | .pm = &sci_dev_pm_ops, |
| 2610 | .of_match_table = of_match_ptr(of_sci_match), | ||
| 2538 | }, | 2611 | }, |
| 2539 | }; | 2612 | }; |
| 2540 | 2613 | ||
diff --git a/drivers/tty/serial/sh-sci.h b/drivers/tty/serial/sh-sci.h index 5aca7364634c..d5db81a0a430 100644 --- a/drivers/tty/serial/sh-sci.h +++ b/drivers/tty/serial/sh-sci.h | |||
| @@ -9,7 +9,7 @@ | |||
| 9 | #define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER) | 9 | #define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER) |
| 10 | #define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK) | 10 | #define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK) |
| 11 | 11 | ||
| 12 | #define SCxSR_ERRORS(port) (to_sci_port(port)->cfg->error_mask) | 12 | #define SCxSR_ERRORS(port) (to_sci_port(port)->error_mask) |
| 13 | 13 | ||
| 14 | #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ | 14 | #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ |
| 15 | defined(CONFIG_CPU_SUBTYPE_SH7720) || \ | 15 | defined(CONFIG_CPU_SUBTYPE_SH7720) || \ |
diff --git a/drivers/usb/gadget/atmel_usba_udc.c b/drivers/usb/gadget/atmel_usba_udc.c index 2cb52e0438df..9f71d9fdcc14 100644 --- a/drivers/usb/gadget/atmel_usba_udc.c +++ b/drivers/usb/gadget/atmel_usba_udc.c | |||
| @@ -326,7 +326,7 @@ static int vbus_is_present(struct usba_udc *udc) | |||
| 326 | 326 | ||
| 327 | #if defined(CONFIG_ARCH_AT91SAM9RL) | 327 | #if defined(CONFIG_ARCH_AT91SAM9RL) |
| 328 | 328 | ||
| 329 | #include <mach/at91_pmc.h> | 329 | #include <linux/clk/at91_pmc.h> |
| 330 | 330 | ||
| 331 | static void toggle_bias(int is_on) | 331 | static void toggle_bias(int is_on) |
| 332 | { | 332 | { |
diff --git a/drivers/usb/host/r8a66597-hcd.c b/drivers/usb/host/r8a66597-hcd.c index 2ad004ae747c..a2fdd85e0c91 100644 --- a/drivers/usb/host/r8a66597-hcd.c +++ b/drivers/usb/host/r8a66597-hcd.c | |||
| @@ -95,7 +95,7 @@ static int r8a66597_clock_enable(struct r8a66597 *r8a66597) | |||
| 95 | int i = 0; | 95 | int i = 0; |
| 96 | 96 | ||
| 97 | if (r8a66597->pdata->on_chip) { | 97 | if (r8a66597->pdata->on_chip) { |
| 98 | clk_enable(r8a66597->clk); | 98 | clk_prepare_enable(r8a66597->clk); |
| 99 | do { | 99 | do { |
| 100 | r8a66597_write(r8a66597, SCKE, SYSCFG0); | 100 | r8a66597_write(r8a66597, SCKE, SYSCFG0); |
| 101 | tmp = r8a66597_read(r8a66597, SYSCFG0); | 101 | tmp = r8a66597_read(r8a66597, SYSCFG0); |
| @@ -139,7 +139,7 @@ static void r8a66597_clock_disable(struct r8a66597 *r8a66597) | |||
| 139 | udelay(1); | 139 | udelay(1); |
| 140 | 140 | ||
| 141 | if (r8a66597->pdata->on_chip) { | 141 | if (r8a66597->pdata->on_chip) { |
| 142 | clk_disable(r8a66597->clk); | 142 | clk_disable_unprepare(r8a66597->clk); |
| 143 | } else { | 143 | } else { |
| 144 | r8a66597_bclr(r8a66597, PLLC, SYSCFG0); | 144 | r8a66597_bclr(r8a66597, PLLC, SYSCFG0); |
| 145 | r8a66597_bclr(r8a66597, XCKE, SYSCFG0); | 145 | r8a66597_bclr(r8a66597, XCKE, SYSCFG0); |
diff --git a/include/dt-bindings/clk/at91.h b/include/dt-bindings/clk/at91.h new file mode 100644 index 000000000000..0b4cb999a3f7 --- /dev/null +++ b/include/dt-bindings/clk/at91.h | |||
| @@ -0,0 +1,22 @@ | |||
| 1 | /* | ||
| 2 | * This header provides constants for AT91 pmc status. | ||
| 3 | * | ||
| 4 | * The constants defined in this header are being used in dts. | ||
| 5 | * | ||
| 6 | * Licensed under GPLv2 or later. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #ifndef _DT_BINDINGS_CLK_AT91_H | ||
| 10 | #define _DT_BINDINGS_CLK_AT91_H | ||
| 11 | |||
| 12 | #define AT91_PMC_MOSCS 0 /* MOSCS Flag */ | ||
| 13 | #define AT91_PMC_LOCKA 1 /* PLLA Lock */ | ||
| 14 | #define AT91_PMC_LOCKB 2 /* PLLB Lock */ | ||
| 15 | #define AT91_PMC_MCKRDY 3 /* Master Clock */ | ||
| 16 | #define AT91_PMC_LOCKU 6 /* UPLL Lock */ | ||
| 17 | #define AT91_PMC_PCKRDY(id) (8 + (id)) /* Programmable Clock */ | ||
| 18 | #define AT91_PMC_MOSCSELS 16 /* Main Oscillator Selection */ | ||
| 19 | #define AT91_PMC_MOSCRCS 17 /* Main On-Chip RC */ | ||
| 20 | #define AT91_PMC_CFDEV 18 /* Clock Failure Detector Event */ | ||
| 21 | |||
| 22 | #endif | ||
diff --git a/include/dt-bindings/clock/r8a7790-clock.h b/include/dt-bindings/clock/r8a7790-clock.h new file mode 100644 index 000000000000..420f0b00ae1e --- /dev/null +++ b/include/dt-bindings/clock/r8a7790-clock.h | |||
| @@ -0,0 +1,100 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Ideas On Board SPRL | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; either version 2 of the License, or | ||
| 7 | * (at your option) any later version. | ||
| 8 | */ | ||
| 9 | |||
| 10 | #ifndef __DT_BINDINGS_CLOCK_R8A7790_H__ | ||
| 11 | #define __DT_BINDINGS_CLOCK_R8A7790_H__ | ||
| 12 | |||
| 13 | /* CPG */ | ||
| 14 | #define R8A7790_CLK_MAIN 0 | ||
| 15 | #define R8A7790_CLK_PLL0 1 | ||
| 16 | #define R8A7790_CLK_PLL1 2 | ||
| 17 | #define R8A7790_CLK_PLL3 3 | ||
| 18 | #define R8A7790_CLK_LB 4 | ||
| 19 | #define R8A7790_CLK_QSPI 5 | ||
| 20 | #define R8A7790_CLK_SDH 6 | ||
| 21 | #define R8A7790_CLK_SD0 7 | ||
| 22 | #define R8A7790_CLK_SD1 8 | ||
| 23 | #define R8A7790_CLK_Z 9 | ||
| 24 | |||
| 25 | /* MSTP1 */ | ||
| 26 | #define R8A7790_CLK_TMU1 11 | ||
| 27 | #define R8A7790_CLK_TMU3 21 | ||
| 28 | #define R8A7790_CLK_TMU2 22 | ||
| 29 | #define R8A7790_CLK_CMT0 24 | ||
| 30 | #define R8A7790_CLK_TMU0 25 | ||
| 31 | #define R8A7790_CLK_VSP1_DU1 27 | ||
| 32 | #define R8A7790_CLK_VSP1_DU0 28 | ||
| 33 | #define R8A7790_CLK_VSP1_RT 30 | ||
| 34 | #define R8A7790_CLK_VSP1_SY 31 | ||
| 35 | |||
| 36 | /* MSTP2 */ | ||
| 37 | #define R8A7790_CLK_SCIFA2 2 | ||
| 38 | #define R8A7790_CLK_SCIFA1 3 | ||
| 39 | #define R8A7790_CLK_SCIFA0 4 | ||
| 40 | #define R8A7790_CLK_SCIFB0 6 | ||
| 41 | #define R8A7790_CLK_SCIFB1 7 | ||
| 42 | #define R8A7790_CLK_SCIFB2 16 | ||
| 43 | #define R8A7790_CLK_SYS_DMAC0 18 | ||
| 44 | #define R8A7790_CLK_SYS_DMAC1 19 | ||
| 45 | |||
| 46 | /* MSTP3 */ | ||
| 47 | #define R8A7790_CLK_TPU0 4 | ||
| 48 | #define R8A7790_CLK_MMCIF1 5 | ||
| 49 | #define R8A7790_CLK_SDHI3 11 | ||
| 50 | #define R8A7790_CLK_SDHI2 12 | ||
| 51 | #define R8A7790_CLK_SDHI1 13 | ||
| 52 | #define R8A7790_CLK_SDHI0 14 | ||
| 53 | #define R8A7790_CLK_MMCIF0 15 | ||
| 54 | #define R8A7790_CLK_SSUSB 28 | ||
| 55 | #define R8A7790_CLK_CMT1 29 | ||
| 56 | #define R8A7790_CLK_USBDMAC0 30 | ||
| 57 | #define R8A7790_CLK_USBDMAC1 31 | ||
| 58 | |||
| 59 | /* MSTP5 */ | ||
| 60 | #define R8A7790_CLK_THERMAL 22 | ||
| 61 | #define R8A7790_CLK_PWM 23 | ||
| 62 | |||
| 63 | /* MSTP7 */ | ||
| 64 | #define R8A7790_CLK_EHCI 3 | ||
| 65 | #define R8A7790_CLK_HSUSB 4 | ||
| 66 | #define R8A7790_CLK_HSCIF1 16 | ||
| 67 | #define R8A7790_CLK_HSCIF0 17 | ||
| 68 | #define R8A7790_CLK_SCIF1 20 | ||
| 69 | #define R8A7790_CLK_SCIF0 21 | ||
| 70 | #define R8A7790_CLK_DU2 22 | ||
| 71 | #define R8A7790_CLK_DU1 23 | ||
| 72 | #define R8A7790_CLK_DU0 24 | ||
| 73 | #define R8A7790_CLK_LVDS1 25 | ||
| 74 | #define R8A7790_CLK_LVDS0 26 | ||
| 75 | |||
| 76 | /* MSTP8 */ | ||
| 77 | #define R8A7790_CLK_VIN3 8 | ||
| 78 | #define R8A7790_CLK_VIN2 9 | ||
| 79 | #define R8A7790_CLK_VIN1 10 | ||
| 80 | #define R8A7790_CLK_VIN0 11 | ||
| 81 | #define R8A7790_CLK_ETHER 13 | ||
| 82 | #define R8A7790_CLK_SATA1 14 | ||
| 83 | #define R8A7790_CLK_SATA0 15 | ||
| 84 | |||
| 85 | /* MSTP9 */ | ||
| 86 | #define R8A7790_CLK_GPIO5 7 | ||
| 87 | #define R8A7790_CLK_GPIO4 8 | ||
| 88 | #define R8A7790_CLK_GPIO3 9 | ||
| 89 | #define R8A7790_CLK_GPIO2 10 | ||
| 90 | #define R8A7790_CLK_GPIO1 11 | ||
| 91 | #define R8A7790_CLK_GPIO0 12 | ||
| 92 | #define R8A7790_CLK_RCAN1 15 | ||
| 93 | #define R8A7790_CLK_RCAN0 16 | ||
| 94 | #define R8A7790_CLK_IICDVFS 26 | ||
| 95 | #define R8A7790_CLK_I2C3 28 | ||
| 96 | #define R8A7790_CLK_I2C2 29 | ||
| 97 | #define R8A7790_CLK_I2C1 30 | ||
| 98 | #define R8A7790_CLK_I2C0 31 | ||
| 99 | |||
| 100 | #endif /* __DT_BINDINGS_CLOCK_R8A7790_H__ */ | ||
diff --git a/include/dt-bindings/clock/r8a7791-clock.h b/include/dt-bindings/clock/r8a7791-clock.h new file mode 100644 index 000000000000..df1715b77f96 --- /dev/null +++ b/include/dt-bindings/clock/r8a7791-clock.h | |||
| @@ -0,0 +1,105 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Ideas On Board SPRL | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; either version 2 of the License, or | ||
| 7 | * (at your option) any later version. | ||
| 8 | */ | ||
| 9 | |||
| 10 | #ifndef __DT_BINDINGS_CLOCK_R8A7791_H__ | ||
| 11 | #define __DT_BINDINGS_CLOCK_R8A7791_H__ | ||
| 12 | |||
| 13 | /* CPG */ | ||
| 14 | #define R8A7791_CLK_MAIN 0 | ||
| 15 | #define R8A7791_CLK_PLL0 1 | ||
| 16 | #define R8A7791_CLK_PLL1 2 | ||
| 17 | #define R8A7791_CLK_PLL3 3 | ||
| 18 | #define R8A7791_CLK_LB 4 | ||
| 19 | #define R8A7791_CLK_QSPI 5 | ||
| 20 | #define R8A7791_CLK_SDH 6 | ||
| 21 | #define R8A7791_CLK_SD0 7 | ||
| 22 | #define R8A7791_CLK_Z 8 | ||
| 23 | |||
| 24 | /* MSTP1 */ | ||
| 25 | #define R8A7791_CLK_TMU1 11 | ||
| 26 | #define R8A7791_CLK_TMU3 21 | ||
| 27 | #define R8A7791_CLK_TMU2 22 | ||
| 28 | #define R8A7791_CLK_CMT0 24 | ||
| 29 | #define R8A7791_CLK_TMU0 25 | ||
| 30 | #define R8A7791_CLK_VSP1_DU1 27 | ||
| 31 | #define R8A7791_CLK_VSP1_DU0 28 | ||
| 32 | #define R8A7791_CLK_VSP1_SY 31 | ||
| 33 | |||
| 34 | /* MSTP2 */ | ||
| 35 | #define R8A7791_CLK_SCIFA2 2 | ||
| 36 | #define R8A7791_CLK_SCIFA1 3 | ||
| 37 | #define R8A7791_CLK_SCIFA0 4 | ||
| 38 | #define R8A7791_CLK_SCIFB0 6 | ||
| 39 | #define R8A7791_CLK_SCIFB1 7 | ||
| 40 | #define R8A7791_CLK_SCIFB2 16 | ||
| 41 | #define R8A7791_CLK_DMAC 18 | ||
| 42 | |||
| 43 | /* MSTP3 */ | ||
| 44 | #define R8A7791_CLK_TPU0 4 | ||
| 45 | #define R8A7791_CLK_SDHI2 11 | ||
| 46 | #define R8A7791_CLK_SDHI1 12 | ||
| 47 | #define R8A7791_CLK_SDHI0 14 | ||
| 48 | #define R8A7791_CLK_MMCIF0 15 | ||
| 49 | #define R8A7791_CLK_SSUSB 28 | ||
| 50 | #define R8A7791_CLK_CMT1 29 | ||
| 51 | #define R8A7791_CLK_USBDMAC0 30 | ||
| 52 | #define R8A7791_CLK_USBDMAC1 31 | ||
| 53 | |||
| 54 | /* MSTP5 */ | ||
| 55 | #define R8A7791_CLK_THERMAL 22 | ||
| 56 | #define R8A7791_CLK_PWM 23 | ||
| 57 | |||
| 58 | /* MSTP7 */ | ||
| 59 | #define R8A7791_CLK_HSUSB 4 | ||
| 60 | #define R8A7791_CLK_HSCIF2 13 | ||
| 61 | #define R8A7791_CLK_SCIF5 14 | ||
| 62 | #define R8A7791_CLK_SCIF4 15 | ||
| 63 | #define R8A7791_CLK_HSCIF1 16 | ||
| 64 | #define R8A7791_CLK_HSCIF0 17 | ||
| 65 | #define R8A7791_CLK_SCIF3 18 | ||
| 66 | #define R8A7791_CLK_SCIF2 19 | ||
| 67 | #define R8A7791_CLK_SCIF1 20 | ||
| 68 | #define R8A7791_CLK_SCIF0 21 | ||
| 69 | #define R8A7791_CLK_DU1 23 | ||
| 70 | #define R8A7791_CLK_DU0 24 | ||
| 71 | #define R8A7791_CLK_LVDS0 26 | ||
| 72 | |||
| 73 | /* MSTP8 */ | ||
| 74 | #define R8A7791_CLK_VIN2 9 | ||
| 75 | #define R8A7791_CLK_VIN1 10 | ||
| 76 | #define R8A7791_CLK_VIN0 11 | ||
| 77 | #define R8A7791_CLK_ETHER 13 | ||
| 78 | #define R8A7791_CLK_SATA1 14 | ||
| 79 | #define R8A7791_CLK_SATA0 15 | ||
| 80 | |||
| 81 | /* MSTP9 */ | ||
| 82 | #define R8A7791_CLK_GPIO7 4 | ||
| 83 | #define R8A7791_CLK_GPIO6 5 | ||
| 84 | #define R8A7791_CLK_GPIO5 7 | ||
| 85 | #define R8A7791_CLK_GPIO4 8 | ||
| 86 | #define R8A7791_CLK_GPIO3 9 | ||
| 87 | #define R8A7791_CLK_GPIO2 10 | ||
| 88 | #define R8A7791_CLK_GPIO1 11 | ||
| 89 | #define R8A7791_CLK_GPIO0 12 | ||
| 90 | #define R8A7791_CLK_RCAN1 15 | ||
| 91 | #define R8A7791_CLK_RCAN0 16 | ||
| 92 | #define R8A7791_CLK_I2C5 25 | ||
| 93 | #define R8A7791_CLK_IICDVFS 26 | ||
| 94 | #define R8A7791_CLK_I2C4 27 | ||
| 95 | #define R8A7791_CLK_I2C3 28 | ||
| 96 | #define R8A7791_CLK_I2C2 29 | ||
| 97 | #define R8A7791_CLK_I2C1 30 | ||
| 98 | #define R8A7791_CLK_I2C0 31 | ||
| 99 | |||
| 100 | /* MSTP11 */ | ||
| 101 | #define R8A7791_CLK_SCIFA3 6 | ||
| 102 | #define R8A7791_CLK_SCIFA4 7 | ||
| 103 | #define R8A7791_CLK_SCIFA5 8 | ||
| 104 | |||
| 105 | #endif /* __DT_BINDINGS_CLOCK_R8A7791_H__ */ | ||
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/include/linux/clk/at91_pmc.h index c604cc69acb5..a6911ebbd02a 100644 --- a/arch/arm/mach-at91/include/mach/at91_pmc.h +++ b/include/linux/clk/at91_pmc.h | |||
| @@ -1,5 +1,5 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * arch/arm/mach-at91/include/mach/at91_pmc.h | 2 | * include/linux/clk/at91_pmc.h |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | 4 | * Copyright (C) 2005 Ivan Kokshaysky |
| 5 | * Copyright (C) SAN People | 5 | * Copyright (C) SAN People |
| @@ -164,6 +164,8 @@ extern void __iomem *at91_pmc_base; | |||
| 164 | #define AT91_PMC_CFDEV (1 << 18) /* Clock Failure Detector Event [some SAM9] */ | 164 | #define AT91_PMC_CFDEV (1 << 18) /* Clock Failure Detector Event [some SAM9] */ |
| 165 | #define AT91_PMC_IMR 0x6c /* Interrupt Mask Register */ | 165 | #define AT91_PMC_IMR 0x6c /* Interrupt Mask Register */ |
| 166 | 166 | ||
| 167 | #define AT91_PMC_PLLICPR 0x80 /* PLL Charge Pump Current Register */ | ||
| 168 | |||
| 167 | #define AT91_PMC_PROT 0xe4 /* Write Protect Mode Register [some SAM9] */ | 169 | #define AT91_PMC_PROT 0xe4 /* Write Protect Mode Register [some SAM9] */ |
| 168 | #define AT91_PMC_WPEN (0x1 << 0) /* Write Protect Enable */ | 170 | #define AT91_PMC_WPEN (0x1 << 0) /* Write Protect Enable */ |
| 169 | #define AT91_PMC_WPKEY (0xffffff << 8) /* Write Protect Key */ | 171 | #define AT91_PMC_WPKEY (0xffffff << 8) /* Write Protect Key */ |
diff --git a/include/linux/serial_sci.h b/include/linux/serial_sci.h index 50fe651da965..22b3640c9424 100644 --- a/include/linux/serial_sci.h +++ b/include/linux/serial_sci.h | |||
| @@ -10,15 +10,6 @@ | |||
| 10 | 10 | ||
| 11 | #define SCIx_NOT_SUPPORTED (-1) | 11 | #define SCIx_NOT_SUPPORTED (-1) |
| 12 | 12 | ||
| 13 | enum { | ||
| 14 | SCBRR_ALGO_1, /* ((clk + 16 * bps) / (16 * bps) - 1) */ | ||
| 15 | SCBRR_ALGO_2, /* ((clk + 16 * bps) / (32 * bps) - 1) */ | ||
| 16 | SCBRR_ALGO_3, /* (((clk * 2) + 16 * bps) / (16 * bps) - 1) */ | ||
| 17 | SCBRR_ALGO_4, /* (((clk * 2) + 16 * bps) / (32 * bps) - 1) */ | ||
| 18 | SCBRR_ALGO_5, /* (((clk * 1000 / 32) / bps) - 1) */ | ||
| 19 | SCBRR_ALGO_6, /* HSCIF variable sample rate algorithm */ | ||
| 20 | }; | ||
| 21 | |||
| 22 | #define SCSCR_TIE (1 << 7) | 13 | #define SCSCR_TIE (1 << 7) |
| 23 | #define SCSCR_RIE (1 << 6) | 14 | #define SCSCR_RIE (1 << 6) |
| 24 | #define SCSCR_TE (1 << 5) | 15 | #define SCSCR_TE (1 << 5) |
| @@ -59,28 +50,6 @@ enum { | |||
| 59 | /* HSSRR HSCIF */ | 50 | /* HSSRR HSCIF */ |
| 60 | #define HSCIF_SRE 0x8000 | 51 | #define HSCIF_SRE 0x8000 |
| 61 | 52 | ||
| 62 | /* Offsets into the sci_port->irqs array */ | ||
| 63 | enum { | ||
| 64 | SCIx_ERI_IRQ, | ||
| 65 | SCIx_RXI_IRQ, | ||
| 66 | SCIx_TXI_IRQ, | ||
| 67 | SCIx_BRI_IRQ, | ||
| 68 | SCIx_NR_IRQS, | ||
| 69 | |||
| 70 | SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */ | ||
| 71 | }; | ||
| 72 | |||
| 73 | /* Offsets into the sci_port->gpios array */ | ||
| 74 | enum { | ||
| 75 | SCIx_SCK, | ||
| 76 | SCIx_RXD, | ||
| 77 | SCIx_TXD, | ||
| 78 | SCIx_CTS, | ||
| 79 | SCIx_RTS, | ||
| 80 | |||
| 81 | SCIx_NR_FNS, | ||
| 82 | }; | ||
| 83 | |||
| 84 | enum { | 53 | enum { |
| 85 | SCIx_PROBE_REGTYPE, | 54 | SCIx_PROBE_REGTYPE, |
| 86 | 55 | ||
| @@ -99,19 +68,6 @@ enum { | |||
| 99 | SCIx_NR_REGTYPES, | 68 | SCIx_NR_REGTYPES, |
| 100 | }; | 69 | }; |
| 101 | 70 | ||
| 102 | #define SCIx_IRQ_MUXED(irq) \ | ||
| 103 | { \ | ||
| 104 | [SCIx_ERI_IRQ] = (irq), \ | ||
| 105 | [SCIx_RXI_IRQ] = (irq), \ | ||
| 106 | [SCIx_TXI_IRQ] = (irq), \ | ||
| 107 | [SCIx_BRI_IRQ] = (irq), \ | ||
| 108 | } | ||
| 109 | |||
| 110 | #define SCIx_IRQ_IS_MUXED(port) \ | ||
| 111 | ((port)->cfg->irqs[SCIx_ERI_IRQ] == \ | ||
| 112 | (port)->cfg->irqs[SCIx_RXI_IRQ]) || \ | ||
| 113 | ((port)->cfg->irqs[SCIx_ERI_IRQ] && \ | ||
| 114 | !(port)->cfg->irqs[SCIx_RXI_IRQ]) | ||
| 115 | /* | 71 | /* |
| 116 | * SCI register subset common for all port types. | 72 | * SCI register subset common for all port types. |
| 117 | * Not all registers will exist on all parts. | 73 | * Not all registers will exist on all parts. |
| @@ -140,22 +96,16 @@ struct plat_sci_port_ops { | |||
| 140 | * Platform device specific platform_data struct | 96 | * Platform device specific platform_data struct |
| 141 | */ | 97 | */ |
| 142 | struct plat_sci_port { | 98 | struct plat_sci_port { |
| 143 | unsigned long mapbase; /* resource base */ | ||
| 144 | unsigned int irqs[SCIx_NR_IRQS]; /* ERI, RXI, TXI, BRI */ | ||
| 145 | unsigned int gpios[SCIx_NR_FNS]; /* SCK, RXD, TXD, CTS, RTS */ | ||
| 146 | unsigned int type; /* SCI / SCIF / IRDA / HSCIF */ | 99 | unsigned int type; /* SCI / SCIF / IRDA / HSCIF */ |
| 147 | upf_t flags; /* UPF_* flags */ | 100 | upf_t flags; /* UPF_* flags */ |
| 148 | unsigned long capabilities; /* Port features/capabilities */ | 101 | unsigned long capabilities; /* Port features/capabilities */ |
| 149 | 102 | ||
| 150 | unsigned int scbrr_algo_id; /* SCBRR calculation algo */ | 103 | unsigned int sampling_rate; |
| 151 | unsigned int scscr; /* SCSCR initialization */ | 104 | unsigned int scscr; /* SCSCR initialization */ |
| 152 | 105 | ||
| 153 | /* | 106 | /* |
| 154 | * Platform overrides if necessary, defaults otherwise. | 107 | * Platform overrides if necessary, defaults otherwise. |
| 155 | */ | 108 | */ |
| 156 | int overrun_bit; | ||
| 157 | unsigned int error_mask; | ||
| 158 | |||
| 159 | int port_reg; | 109 | int port_reg; |
| 160 | unsigned char regshift; | 110 | unsigned char regshift; |
| 161 | unsigned char regtype; | 111 | unsigned char regtype; |