2 files changed, 28 insertions, 0 deletions

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 677eca65a4bc..1bc816f3934b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3240,6 +3240,7 @@
 
 #define GEN6_PCODE_MAILBOX                      0x138124
 #define   GEN6_PCODE_READY                      (1<<31)
+#define   GEN6_READ_OC_PARAMS                   0xc
 #define   GEN6_PCODE_WRITE_MIN_FREQ_TABLE       0x9
 #define GEN6_PCODE_DATA                         0x138128
 
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index bc829bbc14c8..efa88551cbe4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6147,6 +6147,10 @@ void intel_init_emon(struct drm_device *dev)
 
 void gen6_enable_rps(struct drm_i915_private *dev_priv)
 {
+        u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
+        u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
+        u32 pcu_mbox;
+        int cur_freq, min_freq, max_freq;
         int i;
 
         /* Here begins a magic sequence of register writes to enable
@@ -6218,6 +6222,29 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv)
                      500))
                 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
 
+        min_freq = (rp_state_cap & 0xff0000) >> 16;
+        max_freq = rp_state_cap & 0xff;
+        cur_freq = (gt_perf_status & 0xff00) >> 8;
+
+        /* Check for overclock support */
+        if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
+                     500))
+                DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
+        I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
+        pcu_mbox = I915_READ(GEN6_PCODE_DATA);
+        if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
+                     500))
+                DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
+        if (pcu_mbox & (1<<31)) { /* OC supported */
+                max_freq = pcu_mbox & 0xff;
+                DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 100);
+        }
+
+        /* In units of 100MHz */
+        dev_priv->max_delay = max_freq;
+        dev_priv->min_delay = min_freq;
+        dev_priv->cur_delay = cur_freq;
+
         /* requires MSI enabled */
         I915_WRITE(GEN6_PMIER,
                    GEN6_PM_MBOX_EVENT |