diff options
| -rw-r--r-- | drivers/bcma/bcma_private.h | 2 | ||||
| -rw-r--r-- | drivers/bcma/main.c | 13 | ||||
| -rw-r--r-- | drivers/net/ethernet/broadcom/bgmac.c | 115 | ||||
| -rw-r--r-- | drivers/net/ethernet/broadcom/bgmac.h | 55 | ||||
| -rw-r--r-- | include/linux/bcma/bcma.h | 9 |
5 files changed, 156 insertions, 38 deletions
diff --git a/drivers/bcma/bcma_private.h b/drivers/bcma/bcma_private.h index 0215f9ad755c..09b632ad0fe2 100644 --- a/drivers/bcma/bcma_private.h +++ b/drivers/bcma/bcma_private.h | |||
| @@ -33,8 +33,6 @@ int __init bcma_bus_early_register(struct bcma_bus *bus, | |||
| 33 | int bcma_bus_suspend(struct bcma_bus *bus); | 33 | int bcma_bus_suspend(struct bcma_bus *bus); |
| 34 | int bcma_bus_resume(struct bcma_bus *bus); | 34 | int bcma_bus_resume(struct bcma_bus *bus); |
| 35 | #endif | 35 | #endif |
| 36 | struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid, | ||
| 37 | u8 unit); | ||
| 38 | 36 | ||
| 39 | /* scan.c */ | 37 | /* scan.c */ |
| 40 | int bcma_bus_scan(struct bcma_bus *bus); | 38 | int bcma_bus_scan(struct bcma_bus *bus); |
diff --git a/drivers/bcma/main.c b/drivers/bcma/main.c index 5a9f6bdc88f1..34ea4c588d36 100644 --- a/drivers/bcma/main.c +++ b/drivers/bcma/main.c | |||
| @@ -78,18 +78,6 @@ static u16 bcma_cc_core_id(struct bcma_bus *bus) | |||
| 78 | return BCMA_CORE_CHIPCOMMON; | 78 | return BCMA_CORE_CHIPCOMMON; |
| 79 | } | 79 | } |
| 80 | 80 | ||
| 81 | struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid) | ||
| 82 | { | ||
| 83 | struct bcma_device *core; | ||
| 84 | |||
| 85 | list_for_each_entry(core, &bus->cores, list) { | ||
| 86 | if (core->id.id == coreid) | ||
| 87 | return core; | ||
| 88 | } | ||
| 89 | return NULL; | ||
| 90 | } | ||
| 91 | EXPORT_SYMBOL_GPL(bcma_find_core); | ||
| 92 | |||
| 93 | struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid, | 81 | struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid, |
| 94 | u8 unit) | 82 | u8 unit) |
| 95 | { | 83 | { |
| @@ -101,6 +89,7 @@ struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid, | |||
| 101 | } | 89 | } |
| 102 | return NULL; | 90 | return NULL; |
| 103 | } | 91 | } |
| 92 | EXPORT_SYMBOL_GPL(bcma_find_core_unit); | ||
| 104 | 93 | ||
| 105 | bool bcma_wait_value(struct bcma_device *core, u16 reg, u32 mask, u32 value, | 94 | bool bcma_wait_value(struct bcma_device *core, u16 reg, u32 mask, u32 value, |
| 106 | int timeout) | 95 | int timeout) |
diff --git a/drivers/net/ethernet/broadcom/bgmac.c b/drivers/net/ethernet/broadcom/bgmac.c index 39efb864267e..5d41f414e11a 100644 --- a/drivers/net/ethernet/broadcom/bgmac.c +++ b/drivers/net/ethernet/broadcom/bgmac.c | |||
| @@ -96,6 +96,19 @@ static void bgmac_dma_tx_enable(struct bgmac *bgmac, | |||
| 96 | u32 ctl; | 96 | u32 ctl; |
| 97 | 97 | ||
| 98 | ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL); | 98 | ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL); |
| 99 | if (bgmac->core->id.rev >= 4) { | ||
| 100 | ctl &= ~BGMAC_DMA_TX_BL_MASK; | ||
| 101 | ctl |= BGMAC_DMA_TX_BL_128 << BGMAC_DMA_TX_BL_SHIFT; | ||
| 102 | |||
| 103 | ctl &= ~BGMAC_DMA_TX_MR_MASK; | ||
| 104 | ctl |= BGMAC_DMA_TX_MR_2 << BGMAC_DMA_TX_MR_SHIFT; | ||
| 105 | |||
| 106 | ctl &= ~BGMAC_DMA_TX_PC_MASK; | ||
| 107 | ctl |= BGMAC_DMA_TX_PC_16 << BGMAC_DMA_TX_PC_SHIFT; | ||
| 108 | |||
| 109 | ctl &= ~BGMAC_DMA_TX_PT_MASK; | ||
| 110 | ctl |= BGMAC_DMA_TX_PT_8 << BGMAC_DMA_TX_PT_SHIFT; | ||
| 111 | } | ||
| 99 | ctl |= BGMAC_DMA_TX_ENABLE; | 112 | ctl |= BGMAC_DMA_TX_ENABLE; |
| 100 | ctl |= BGMAC_DMA_TX_PARITY_DISABLE; | 113 | ctl |= BGMAC_DMA_TX_PARITY_DISABLE; |
| 101 | bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, ctl); | 114 | bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, ctl); |
| @@ -240,6 +253,16 @@ static void bgmac_dma_rx_enable(struct bgmac *bgmac, | |||
| 240 | u32 ctl; | 253 | u32 ctl; |
| 241 | 254 | ||
| 242 | ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL); | 255 | ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL); |
| 256 | if (bgmac->core->id.rev >= 4) { | ||
| 257 | ctl &= ~BGMAC_DMA_RX_BL_MASK; | ||
| 258 | ctl |= BGMAC_DMA_RX_BL_128 << BGMAC_DMA_RX_BL_SHIFT; | ||
| 259 | |||
| 260 | ctl &= ~BGMAC_DMA_RX_PC_MASK; | ||
| 261 | ctl |= BGMAC_DMA_RX_PC_8 << BGMAC_DMA_RX_PC_SHIFT; | ||
| 262 | |||
| 263 | ctl &= ~BGMAC_DMA_RX_PT_MASK; | ||
| 264 | ctl |= BGMAC_DMA_RX_PT_1 << BGMAC_DMA_RX_PT_SHIFT; | ||
| 265 | } | ||
| 243 | ctl &= BGMAC_DMA_RX_ADDREXT_MASK; | 266 | ctl &= BGMAC_DMA_RX_ADDREXT_MASK; |
| 244 | ctl |= BGMAC_DMA_RX_ENABLE; | 267 | ctl |= BGMAC_DMA_RX_ENABLE; |
| 245 | ctl |= BGMAC_DMA_RX_PARITY_DISABLE; | 268 | ctl |= BGMAC_DMA_RX_PARITY_DISABLE; |
| @@ -745,13 +768,13 @@ static void bgmac_cmdcfg_maskset(struct bgmac *bgmac, u32 mask, u32 set, | |||
| 745 | u32 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG); | 768 | u32 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG); |
| 746 | u32 new_val = (cmdcfg & mask) | set; | 769 | u32 new_val = (cmdcfg & mask) | set; |
| 747 | 770 | ||
| 748 | bgmac_set(bgmac, BGMAC_CMDCFG, BGMAC_CMDCFG_SR); | 771 | bgmac_set(bgmac, BGMAC_CMDCFG, BGMAC_CMDCFG_SR(bgmac->core->id.rev)); |
| 749 | udelay(2); | 772 | udelay(2); |
| 750 | 773 | ||
| 751 | if (new_val != cmdcfg || force) | 774 | if (new_val != cmdcfg || force) |
| 752 | bgmac_write(bgmac, BGMAC_CMDCFG, new_val); | 775 | bgmac_write(bgmac, BGMAC_CMDCFG, new_val); |
| 753 | 776 | ||
| 754 | bgmac_mask(bgmac, BGMAC_CMDCFG, ~BGMAC_CMDCFG_SR); | 777 | bgmac_mask(bgmac, BGMAC_CMDCFG, ~BGMAC_CMDCFG_SR(bgmac->core->id.rev)); |
| 755 | udelay(2); | 778 | udelay(2); |
| 756 | } | 779 | } |
| 757 | 780 | ||
| @@ -825,6 +848,9 @@ static void bgmac_mac_speed(struct bgmac *bgmac) | |||
| 825 | case SPEED_1000: | 848 | case SPEED_1000: |
| 826 | set |= BGMAC_CMDCFG_ES_1000; | 849 | set |= BGMAC_CMDCFG_ES_1000; |
| 827 | break; | 850 | break; |
| 851 | case SPEED_2500: | ||
| 852 | set |= BGMAC_CMDCFG_ES_2500; | ||
| 853 | break; | ||
| 828 | default: | 854 | default: |
| 829 | bgmac_err(bgmac, "Unsupported speed: %d\n", bgmac->mac_speed); | 855 | bgmac_err(bgmac, "Unsupported speed: %d\n", bgmac->mac_speed); |
| 830 | } | 856 | } |
| @@ -837,12 +863,26 @@ static void bgmac_mac_speed(struct bgmac *bgmac) | |||
| 837 | 863 | ||
| 838 | static void bgmac_miiconfig(struct bgmac *bgmac) | 864 | static void bgmac_miiconfig(struct bgmac *bgmac) |
| 839 | { | 865 | { |
| 840 | u8 imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >> | 866 | struct bcma_device *core = bgmac->core; |
| 841 | BGMAC_DS_MM_SHIFT; | 867 | struct bcma_chipinfo *ci = &core->bus->chipinfo; |
| 842 | if (imode == 0 || imode == 1) { | 868 | u8 imode; |
| 843 | bgmac->mac_speed = SPEED_100; | 869 | |
| 870 | if (ci->id == BCMA_CHIP_ID_BCM4707 || | ||
| 871 | ci->id == BCMA_CHIP_ID_BCM53018) { | ||
| 872 | bcma_awrite32(core, BCMA_IOCTL, | ||
| 873 | bcma_aread32(core, BCMA_IOCTL) | 0x40 | | ||
| 874 | BGMAC_BCMA_IOCTL_SW_CLKEN); | ||
| 875 | bgmac->mac_speed = SPEED_2500; | ||
| 844 | bgmac->mac_duplex = DUPLEX_FULL; | 876 | bgmac->mac_duplex = DUPLEX_FULL; |
| 845 | bgmac_mac_speed(bgmac); | 877 | bgmac_mac_speed(bgmac); |
| 878 | } else { | ||
| 879 | imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & | ||
| 880 | BGMAC_DS_MM_MASK) >> BGMAC_DS_MM_SHIFT; | ||
| 881 | if (imode == 0 || imode == 1) { | ||
| 882 | bgmac->mac_speed = SPEED_100; | ||
| 883 | bgmac->mac_duplex = DUPLEX_FULL; | ||
| 884 | bgmac_mac_speed(bgmac); | ||
| 885 | } | ||
| 846 | } | 886 | } |
| 847 | } | 887 | } |
| 848 | 888 | ||
| @@ -852,7 +892,7 @@ static void bgmac_chip_reset(struct bgmac *bgmac) | |||
| 852 | struct bcma_device *core = bgmac->core; | 892 | struct bcma_device *core = bgmac->core; |
| 853 | struct bcma_bus *bus = core->bus; | 893 | struct bcma_bus *bus = core->bus; |
| 854 | struct bcma_chipinfo *ci = &bus->chipinfo; | 894 | struct bcma_chipinfo *ci = &bus->chipinfo; |
| 855 | u32 flags = 0; | 895 | u32 flags; |
| 856 | u32 iost; | 896 | u32 iost; |
| 857 | int i; | 897 | int i; |
| 858 | 898 | ||
| @@ -880,15 +920,21 @@ static void bgmac_chip_reset(struct bgmac *bgmac) | |||
| 880 | (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == BCMA_PKG_ID_BCM47188)) | 920 | (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == BCMA_PKG_ID_BCM47188)) |
| 881 | iost &= ~BGMAC_BCMA_IOST_ATTACHED; | 921 | iost &= ~BGMAC_BCMA_IOST_ATTACHED; |
| 882 | 922 | ||
| 883 | if (iost & BGMAC_BCMA_IOST_ATTACHED) { | 923 | /* 3GMAC: for BCM4707, only do core reset at bgmac_probe() */ |
| 884 | flags = BGMAC_BCMA_IOCTL_SW_CLKEN; | 924 | if (ci->id != BCMA_CHIP_ID_BCM4707) { |
| 885 | if (!bgmac->has_robosw) | 925 | flags = 0; |
| 886 | flags |= BGMAC_BCMA_IOCTL_SW_RESET; | 926 | if (iost & BGMAC_BCMA_IOST_ATTACHED) { |
| 927 | flags = BGMAC_BCMA_IOCTL_SW_CLKEN; | ||
| 928 | if (!bgmac->has_robosw) | ||
| 929 | flags |= BGMAC_BCMA_IOCTL_SW_RESET; | ||
| 930 | } | ||
| 931 | bcma_core_enable(core, flags); | ||
| 887 | } | 932 | } |
| 888 | 933 | ||
| 889 | bcma_core_enable(core, flags); | 934 | /* Request Misc PLL for corerev > 2 */ |
| 890 | 935 | if (core->id.rev > 2 && | |
| 891 | if (core->id.rev > 2) { | 936 | ci->id != BCMA_CHIP_ID_BCM4707 && |
| 937 | ci->id != BCMA_CHIP_ID_BCM53018) { | ||
| 892 | bgmac_set(bgmac, BCMA_CLKCTLST, | 938 | bgmac_set(bgmac, BCMA_CLKCTLST, |
| 893 | BGMAC_BCMA_CLKCTLST_MISC_PLL_REQ); | 939 | BGMAC_BCMA_CLKCTLST_MISC_PLL_REQ); |
| 894 | bgmac_wait_value(bgmac->core, BCMA_CLKCTLST, | 940 | bgmac_wait_value(bgmac->core, BCMA_CLKCTLST, |
| @@ -954,7 +1000,7 @@ static void bgmac_chip_reset(struct bgmac *bgmac) | |||
| 954 | BGMAC_CMDCFG_PROM | | 1000 | BGMAC_CMDCFG_PROM | |
| 955 | BGMAC_CMDCFG_NLC | | 1001 | BGMAC_CMDCFG_NLC | |
| 956 | BGMAC_CMDCFG_CFE | | 1002 | BGMAC_CMDCFG_CFE | |
| 957 | BGMAC_CMDCFG_SR, | 1003 | BGMAC_CMDCFG_SR(core->id.rev), |
| 958 | false); | 1004 | false); |
| 959 | bgmac->mac_speed = SPEED_UNKNOWN; | 1005 | bgmac->mac_speed = SPEED_UNKNOWN; |
| 960 | bgmac->mac_duplex = DUPLEX_UNKNOWN; | 1006 | bgmac->mac_duplex = DUPLEX_UNKNOWN; |
| @@ -997,7 +1043,7 @@ static void bgmac_enable(struct bgmac *bgmac) | |||
| 997 | 1043 | ||
| 998 | cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG); | 1044 | cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG); |
| 999 | bgmac_cmdcfg_maskset(bgmac, ~(BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE), | 1045 | bgmac_cmdcfg_maskset(bgmac, ~(BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE), |
| 1000 | BGMAC_CMDCFG_SR, true); | 1046 | BGMAC_CMDCFG_SR(bgmac->core->id.rev), true); |
| 1001 | udelay(2); | 1047 | udelay(2); |
| 1002 | cmdcfg |= BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE; | 1048 | cmdcfg |= BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE; |
| 1003 | bgmac_write(bgmac, BGMAC_CMDCFG, cmdcfg); | 1049 | bgmac_write(bgmac, BGMAC_CMDCFG, cmdcfg); |
| @@ -1026,12 +1072,16 @@ static void bgmac_enable(struct bgmac *bgmac) | |||
| 1026 | break; | 1072 | break; |
| 1027 | } | 1073 | } |
| 1028 | 1074 | ||
| 1029 | rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL); | 1075 | if (ci->id != BCMA_CHIP_ID_BCM4707 && |
| 1030 | rxq_ctl &= ~BGMAC_RXQ_CTL_MDP_MASK; | 1076 | ci->id != BCMA_CHIP_ID_BCM53018) { |
| 1031 | bp_clk = bcma_pmu_get_bus_clock(&bgmac->core->bus->drv_cc) / 1000000; | 1077 | rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL); |
| 1032 | mdp = (bp_clk * 128 / 1000) - 3; | 1078 | rxq_ctl &= ~BGMAC_RXQ_CTL_MDP_MASK; |
| 1033 | rxq_ctl |= (mdp << BGMAC_RXQ_CTL_MDP_SHIFT); | 1079 | bp_clk = bcma_pmu_get_bus_clock(&bgmac->core->bus->drv_cc) / |
| 1034 | bgmac_write(bgmac, BGMAC_RXQ_CTL, rxq_ctl); | 1080 | 1000000; |
| 1081 | mdp = (bp_clk * 128 / 1000) - 3; | ||
| 1082 | rxq_ctl |= (mdp << BGMAC_RXQ_CTL_MDP_SHIFT); | ||
| 1083 | bgmac_write(bgmac, BGMAC_RXQ_CTL, rxq_ctl); | ||
| 1084 | } | ||
| 1035 | } | 1085 | } |
| 1036 | 1086 | ||
| 1037 | /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */ | 1087 | /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */ |
| @@ -1423,6 +1473,27 @@ static int bgmac_probe(struct bcma_device *core) | |||
| 1423 | 1473 | ||
| 1424 | bgmac_chip_reset(bgmac); | 1474 | bgmac_chip_reset(bgmac); |
| 1425 | 1475 | ||
| 1476 | /* For Northstar, we have to take all GMAC core out of reset */ | ||
| 1477 | if (core->id.id == BCMA_CHIP_ID_BCM4707 || | ||
| 1478 | core->id.id == BCMA_CHIP_ID_BCM53018) { | ||
| 1479 | struct bcma_device *ns_core; | ||
| 1480 | int ns_gmac; | ||
| 1481 | |||
| 1482 | /* Northstar has 4 GMAC cores */ | ||
| 1483 | for (ns_gmac = 0; ns_gmac < 4; ns_gmac++) { | ||
| 1484 | /* As northstar requirement, we have to reset all GAMCs | ||
| 1485 | * before accessing one. bgmac_chip_reset() call | ||
| 1486 | * bcma_core_enable() for this core. Then the other | ||
| 1487 | * three GAMCs didn't reset. We do it here. | ||
| 1488 | */ | ||
| 1489 | ns_core = bcma_find_core_unit(core->bus, | ||
| 1490 | BCMA_CORE_MAC_GBIT, | ||
| 1491 | ns_gmac); | ||
| 1492 | if (ns_core && !bcma_core_is_enabled(ns_core)) | ||
| 1493 | bcma_core_enable(ns_core, 0); | ||
| 1494 | } | ||
| 1495 | } | ||
| 1496 | |||
| 1426 | err = bgmac_dma_alloc(bgmac); | 1497 | err = bgmac_dma_alloc(bgmac); |
| 1427 | if (err) { | 1498 | if (err) { |
| 1428 | bgmac_err(bgmac, "Unable to alloc memory for DMA\n"); | 1499 | bgmac_err(bgmac, "Unable to alloc memory for DMA\n"); |
diff --git a/drivers/net/ethernet/broadcom/bgmac.h b/drivers/net/ethernet/broadcom/bgmac.h index 130b16b5d355..89fa5bc69c51 100644 --- a/drivers/net/ethernet/broadcom/bgmac.h +++ b/drivers/net/ethernet/broadcom/bgmac.h | |||
| @@ -189,6 +189,7 @@ | |||
| 189 | #define BGMAC_CMDCFG_ES_10 0x00000000 | 189 | #define BGMAC_CMDCFG_ES_10 0x00000000 |
| 190 | #define BGMAC_CMDCFG_ES_100 0x00000004 | 190 | #define BGMAC_CMDCFG_ES_100 0x00000004 |
| 191 | #define BGMAC_CMDCFG_ES_1000 0x00000008 | 191 | #define BGMAC_CMDCFG_ES_1000 0x00000008 |
| 192 | #define BGMAC_CMDCFG_ES_2500 0x0000000C | ||
| 192 | #define BGMAC_CMDCFG_PROM 0x00000010 /* Set to activate promiscuous mode */ | 193 | #define BGMAC_CMDCFG_PROM 0x00000010 /* Set to activate promiscuous mode */ |
| 193 | #define BGMAC_CMDCFG_PAD_EN 0x00000020 | 194 | #define BGMAC_CMDCFG_PAD_EN 0x00000020 |
| 194 | #define BGMAC_CMDCFG_CF 0x00000040 | 195 | #define BGMAC_CMDCFG_CF 0x00000040 |
| @@ -197,7 +198,9 @@ | |||
| 197 | #define BGMAC_CMDCFG_TAI 0x00000200 | 198 | #define BGMAC_CMDCFG_TAI 0x00000200 |
| 198 | #define BGMAC_CMDCFG_HD 0x00000400 /* Set if in half duplex mode */ | 199 | #define BGMAC_CMDCFG_HD 0x00000400 /* Set if in half duplex mode */ |
| 199 | #define BGMAC_CMDCFG_HD_SHIFT 10 | 200 | #define BGMAC_CMDCFG_HD_SHIFT 10 |
| 200 | #define BGMAC_CMDCFG_SR 0x00000800 /* Set to reset mode */ | 201 | #define BGMAC_CMDCFG_SR_REV0 0x00000800 /* Set to reset mode, for other revs */ |
| 202 | #define BGMAC_CMDCFG_SR_REV4 0x00002000 /* Set to reset mode, only for core rev 4 */ | ||
| 203 | #define BGMAC_CMDCFG_SR(rev) ((rev == 4) ? BGMAC_CMDCFG_SR_REV4 : BGMAC_CMDCFG_SR_REV0) | ||
| 201 | #define BGMAC_CMDCFG_ML 0x00008000 /* Set to activate mac loopback mode */ | 204 | #define BGMAC_CMDCFG_ML 0x00008000 /* Set to activate mac loopback mode */ |
| 202 | #define BGMAC_CMDCFG_AE 0x00400000 | 205 | #define BGMAC_CMDCFG_AE 0x00400000 |
| 203 | #define BGMAC_CMDCFG_CFE 0x00800000 | 206 | #define BGMAC_CMDCFG_CFE 0x00800000 |
| @@ -237,9 +240,34 @@ | |||
| 237 | #define BGMAC_DMA_TX_SUSPEND 0x00000002 | 240 | #define BGMAC_DMA_TX_SUSPEND 0x00000002 |
| 238 | #define BGMAC_DMA_TX_LOOPBACK 0x00000004 | 241 | #define BGMAC_DMA_TX_LOOPBACK 0x00000004 |
| 239 | #define BGMAC_DMA_TX_FLUSH 0x00000010 | 242 | #define BGMAC_DMA_TX_FLUSH 0x00000010 |
| 243 | #define BGMAC_DMA_TX_MR_MASK 0x000000C0 /* Multiple outstanding reads */ | ||
| 244 | #define BGMAC_DMA_TX_MR_SHIFT 6 | ||
| 245 | #define BGMAC_DMA_TX_MR_1 0 | ||
| 246 | #define BGMAC_DMA_TX_MR_2 1 | ||
| 240 | #define BGMAC_DMA_TX_PARITY_DISABLE 0x00000800 | 247 | #define BGMAC_DMA_TX_PARITY_DISABLE 0x00000800 |
| 241 | #define BGMAC_DMA_TX_ADDREXT_MASK 0x00030000 | 248 | #define BGMAC_DMA_TX_ADDREXT_MASK 0x00030000 |
| 242 | #define BGMAC_DMA_TX_ADDREXT_SHIFT 16 | 249 | #define BGMAC_DMA_TX_ADDREXT_SHIFT 16 |
| 250 | #define BGMAC_DMA_TX_BL_MASK 0x001C0000 /* BurstLen bits */ | ||
| 251 | #define BGMAC_DMA_TX_BL_SHIFT 18 | ||
| 252 | #define BGMAC_DMA_TX_BL_16 0 | ||
| 253 | #define BGMAC_DMA_TX_BL_32 1 | ||
| 254 | #define BGMAC_DMA_TX_BL_64 2 | ||
| 255 | #define BGMAC_DMA_TX_BL_128 3 | ||
| 256 | #define BGMAC_DMA_TX_BL_256 4 | ||
| 257 | #define BGMAC_DMA_TX_BL_512 5 | ||
| 258 | #define BGMAC_DMA_TX_BL_1024 6 | ||
| 259 | #define BGMAC_DMA_TX_PC_MASK 0x00E00000 /* Prefetch control */ | ||
| 260 | #define BGMAC_DMA_TX_PC_SHIFT 21 | ||
| 261 | #define BGMAC_DMA_TX_PC_0 0 | ||
| 262 | #define BGMAC_DMA_TX_PC_4 1 | ||
| 263 | #define BGMAC_DMA_TX_PC_8 2 | ||
| 264 | #define BGMAC_DMA_TX_PC_16 3 | ||
| 265 | #define BGMAC_DMA_TX_PT_MASK 0x03000000 /* Prefetch threshold */ | ||
| 266 | #define BGMAC_DMA_TX_PT_SHIFT 24 | ||
| 267 | #define BGMAC_DMA_TX_PT_1 0 | ||
| 268 | #define BGMAC_DMA_TX_PT_2 1 | ||
| 269 | #define BGMAC_DMA_TX_PT_4 2 | ||
| 270 | #define BGMAC_DMA_TX_PT_8 3 | ||
| 243 | #define BGMAC_DMA_TX_INDEX 0x04 | 271 | #define BGMAC_DMA_TX_INDEX 0x04 |
| 244 | #define BGMAC_DMA_TX_RINGLO 0x08 | 272 | #define BGMAC_DMA_TX_RINGLO 0x08 |
| 245 | #define BGMAC_DMA_TX_RINGHI 0x0C | 273 | #define BGMAC_DMA_TX_RINGHI 0x0C |
| @@ -267,8 +295,33 @@ | |||
| 267 | #define BGMAC_DMA_RX_DIRECT_FIFO 0x00000100 | 295 | #define BGMAC_DMA_RX_DIRECT_FIFO 0x00000100 |
| 268 | #define BGMAC_DMA_RX_OVERFLOW_CONT 0x00000400 | 296 | #define BGMAC_DMA_RX_OVERFLOW_CONT 0x00000400 |
| 269 | #define BGMAC_DMA_RX_PARITY_DISABLE 0x00000800 | 297 | #define BGMAC_DMA_RX_PARITY_DISABLE 0x00000800 |
| 298 | #define BGMAC_DMA_RX_MR_MASK 0x000000C0 /* Multiple outstanding reads */ | ||
| 299 | #define BGMAC_DMA_RX_MR_SHIFT 6 | ||
| 300 | #define BGMAC_DMA_TX_MR_1 0 | ||
| 301 | #define BGMAC_DMA_TX_MR_2 1 | ||
| 270 | #define BGMAC_DMA_RX_ADDREXT_MASK 0x00030000 | 302 | #define BGMAC_DMA_RX_ADDREXT_MASK 0x00030000 |
| 271 | #define BGMAC_DMA_RX_ADDREXT_SHIFT 16 | 303 | #define BGMAC_DMA_RX_ADDREXT_SHIFT 16 |
| 304 | #define BGMAC_DMA_RX_BL_MASK 0x001C0000 /* BurstLen bits */ | ||
| 305 | #define BGMAC_DMA_RX_BL_SHIFT 18 | ||
| 306 | #define BGMAC_DMA_RX_BL_16 0 | ||
| 307 | #define BGMAC_DMA_RX_BL_32 1 | ||
| 308 | #define BGMAC_DMA_RX_BL_64 2 | ||
| 309 | #define BGMAC_DMA_RX_BL_128 3 | ||
| 310 | #define BGMAC_DMA_RX_BL_256 4 | ||
| 311 | #define BGMAC_DMA_RX_BL_512 5 | ||
| 312 | #define BGMAC_DMA_RX_BL_1024 6 | ||
| 313 | #define BGMAC_DMA_RX_PC_MASK 0x00E00000 /* Prefetch control */ | ||
| 314 | #define BGMAC_DMA_RX_PC_SHIFT 21 | ||
| 315 | #define BGMAC_DMA_RX_PC_0 0 | ||
| 316 | #define BGMAC_DMA_RX_PC_4 1 | ||
| 317 | #define BGMAC_DMA_RX_PC_8 2 | ||
| 318 | #define BGMAC_DMA_RX_PC_16 3 | ||
| 319 | #define BGMAC_DMA_RX_PT_MASK 0x03000000 /* Prefetch threshold */ | ||
| 320 | #define BGMAC_DMA_RX_PT_SHIFT 24 | ||
| 321 | #define BGMAC_DMA_RX_PT_1 0 | ||
| 322 | #define BGMAC_DMA_RX_PT_2 1 | ||
| 323 | #define BGMAC_DMA_RX_PT_4 2 | ||
| 324 | #define BGMAC_DMA_RX_PT_8 3 | ||
| 272 | #define BGMAC_DMA_RX_INDEX 0x24 | 325 | #define BGMAC_DMA_RX_INDEX 0x24 |
| 273 | #define BGMAC_DMA_RX_RINGLO 0x28 | 326 | #define BGMAC_DMA_RX_RINGLO 0x28 |
| 274 | #define BGMAC_DMA_RX_RINGHI 0x2C | 327 | #define BGMAC_DMA_RX_RINGHI 0x2C |
diff --git a/include/linux/bcma/bcma.h b/include/linux/bcma/bcma.h index 4d043c30216f..0b3bb16c705a 100644 --- a/include/linux/bcma/bcma.h +++ b/include/linux/bcma/bcma.h | |||
| @@ -418,7 +418,14 @@ static inline void bcma_maskset16(struct bcma_device *cc, | |||
| 418 | bcma_write16(cc, offset, (bcma_read16(cc, offset) & mask) | set); | 418 | bcma_write16(cc, offset, (bcma_read16(cc, offset) & mask) | set); |
| 419 | } | 419 | } |
| 420 | 420 | ||
| 421 | extern struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid); | 421 | extern struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid, |
| 422 | u8 unit); | ||
| 423 | static inline struct bcma_device *bcma_find_core(struct bcma_bus *bus, | ||
| 424 | u16 coreid) | ||
| 425 | { | ||
| 426 | return bcma_find_core_unit(bus, coreid, 0); | ||
| 427 | } | ||
| 428 | |||
| 422 | extern bool bcma_core_is_enabled(struct bcma_device *core); | 429 | extern bool bcma_core_is_enabled(struct bcma_device *core); |
| 423 | extern void bcma_core_disable(struct bcma_device *core, u32 flags); | 430 | extern void bcma_core_disable(struct bcma_device *core, u32 flags); |
| 424 | extern int bcma_core_enable(struct bcma_device *core, u32 flags); | 431 | extern int bcma_core_enable(struct bcma_device *core, u32 flags); |
