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-rw-r--r--arch/arm/Kconfig3
-rw-r--r--arch/arm/mach-mx1/mach-mx1ads.c2
-rw-r--r--arch/arm/mach-mx1/mach-scb9328.c2
-rw-r--r--arch/arm/mach-mx2/Makefile8
-rw-r--r--arch/arm/mach-mx2/devices.c643
-rw-r--r--arch/arm/mach-mx2/devices.h13
-rw-r--r--arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c2
-rw-r--r--arch/arm/mach-mx2/mach-cpuimx27.c5
-rw-r--r--arch/arm/mach-mx2/mach-imx27lite.c2
-rw-r--r--arch/arm/mach-mx2/mach-mx21ads.c4
-rw-r--r--arch/arm/mach-mx2/mach-mx27_3ds.c2
-rw-r--r--arch/arm/mach-mx2/mach-mx27ads.c4
-rw-r--r--arch/arm/mach-mx2/mach-mxt_td60.c4
-rw-r--r--arch/arm/mach-mx2/mach-pca100.c4
-rw-r--r--arch/arm/mach-mx2/mach-pcm038.c4
-rw-r--r--arch/arm/mach-mx2/mm-imx21.c83
-rw-r--r--arch/arm/mach-mx2/mm-imx27.c (renamed from arch/arm/mach-mx2/generic.c)44
-rw-r--r--arch/arm/mach-mx2/pcm970-baseboard.c2
-rw-r--r--arch/arm/mach-mx25/mach-mx25pdk.c2
-rw-r--r--arch/arm/plat-mxc/Kconfig14
-rw-r--r--arch/arm/plat-mxc/Makefile9
-rw-r--r--arch/arm/plat-mxc/audmux-v1.c14
-rw-r--r--arch/arm/plat-mxc/audmux-v2.c9
-rw-r--r--arch/arm/plat-mxc/dma-mx1-mx2.c207
-rw-r--r--arch/arm/plat-mxc/gpio.c30
-rw-r--r--arch/arm/plat-mxc/include/mach/clock.h7
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx1.h313
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx21.h210
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx25.h22
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx27.h372
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx2x.h425
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx3.h76
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx35.h2
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-v1.h103
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux.h128
-rw-r--r--arch/arm/plat-mxc/include/mach/irqs.h11
-rw-r--r--arch/arm/plat-mxc/include/mach/memory.h15
-rw-r--r--arch/arm/plat-mxc/include/mach/mtd-xip.h34
-rw-r--r--arch/arm/plat-mxc/iomux-mx1-mx2.c159
-rw-r--r--arch/arm/plat-mxc/iomux-v1.c238
40 files changed, 1580 insertions, 1651 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 233a222752c0..3bf3d48ddbf0 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -308,10 +308,9 @@ config ARCH_MXC
308 bool "Freescale MXC/iMX-based" 308 bool "Freescale MXC/iMX-based"
309 select GENERIC_TIME 309 select GENERIC_TIME
310 select GENERIC_CLOCKEVENTS 310 select GENERIC_CLOCKEVENTS
311 select ARCH_MTD_XIP
312 select GENERIC_GPIO
313 select ARCH_REQUIRE_GPIOLIB 311 select ARCH_REQUIRE_GPIOLIB
314 select HAVE_CLK 312 select HAVE_CLK
313 select COMMON_CLKDEV
315 help 314 help
316 Support for Freescale MXC/iMX-based family of processors 315 Support for Freescale MXC/iMX-based family of processors
317 316
diff --git a/arch/arm/mach-mx1/mach-mx1ads.c b/arch/arm/mach-mx1/mach-mx1ads.c
index 69831aa274ff..51f3cfd83db2 100644
--- a/arch/arm/mach-mx1/mach-mx1ads.c
+++ b/arch/arm/mach-mx1/mach-mx1ads.c
@@ -27,7 +27,7 @@
27#include <mach/hardware.h> 27#include <mach/hardware.h>
28#include <mach/i2c.h> 28#include <mach/i2c.h>
29#include <mach/imx-uart.h> 29#include <mach/imx-uart.h>
30#include <mach/iomux.h> 30#include <mach/iomux-mx1.h>
31#include <mach/irqs.h> 31#include <mach/irqs.h>
32 32
33#include "devices.h" 33#include "devices.h"
diff --git a/arch/arm/mach-mx1/mach-scb9328.c b/arch/arm/mach-mx1/mach-scb9328.c
index b9530d76e99d..7587a7a12460 100644
--- a/arch/arm/mach-mx1/mach-scb9328.c
+++ b/arch/arm/mach-mx1/mach-scb9328.c
@@ -23,7 +23,7 @@
23#include <mach/hardware.h> 23#include <mach/hardware.h>
24#include <mach/irqs.h> 24#include <mach/irqs.h>
25#include <mach/imx-uart.h> 25#include <mach/imx-uart.h>
26#include <mach/iomux.h> 26#include <mach/iomux-mx1.h>
27 27
28#include "devices.h" 28#include "devices.h"
29 29
diff --git a/arch/arm/mach-mx2/Makefile b/arch/arm/mach-mx2/Makefile
index e8910903b24f..e3254faac828 100644
--- a/arch/arm/mach-mx2/Makefile
+++ b/arch/arm/mach-mx2/Makefile
@@ -4,14 +4,12 @@
4 4
5# Object file lists. 5# Object file lists.
6 6
7obj-y := generic.o devices.o serial.o 7obj-y := devices.o serial.o
8CFLAGS_generic.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS
9CFLAGS_devices.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS
10 8
11obj-$(CONFIG_MACH_MX21) += clock_imx21.o 9obj-$(CONFIG_MACH_MX21) += clock_imx21.o mm-imx21.o
12 10
13obj-$(CONFIG_MACH_MX27) += cpu_imx27.o 11obj-$(CONFIG_MACH_MX27) += cpu_imx27.o
14obj-$(CONFIG_MACH_MX27) += clock_imx27.o 12obj-$(CONFIG_MACH_MX27) += clock_imx27.o mm-imx27.o
15 13
16obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o 14obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o
17obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o 15obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o
diff --git a/arch/arm/mach-mx2/devices.c b/arch/arm/mach-mx2/devices.c
index 3d398ce09b31..a4b809b82fa3 100644
--- a/arch/arm/mach-mx2/devices.c
+++ b/arch/arm/mach-mx2/devices.c
@@ -46,65 +46,31 @@
46 * - i.MX21: 2 channel 46 * - i.MX21: 2 channel
47 * - i.MX27: 3 channel 47 * - i.MX27: 3 channel
48 */ 48 */
49static struct resource mxc_spi_resources0[] = { 49#define DEFINE_IMX_SPI_DEVICE(n, baseaddr, irq) \
50 { 50 static struct resource mxc_spi_resources ## n[] = { \
51 .start = CSPI1_BASE_ADDR, 51 { \
52 .end = CSPI1_BASE_ADDR + SZ_4K - 1, 52 .start = baseaddr, \
53 .flags = IORESOURCE_MEM, 53 .end = baseaddr + SZ_4K - 1, \
54 }, { 54 .flags = IORESOURCE_MEM, \
55 .start = MXC_INT_CSPI1, 55 }, { \
56 .end = MXC_INT_CSPI1, 56 .start = irq, \
57 .flags = IORESOURCE_IRQ, 57 .end = irq, \
58 }, 58 .flags = IORESOURCE_IRQ, \
59}; 59 }, \
60 60 }; \
61static struct resource mxc_spi_resources1[] = { 61 \
62 { 62 struct platform_device mxc_spi_device ## n = { \
63 .start = CSPI2_BASE_ADDR, 63 .name = "spi_imx", \
64 .end = CSPI2_BASE_ADDR + SZ_4K - 1, 64 .id = n, \
65 .flags = IORESOURCE_MEM, 65 .num_resources = ARRAY_SIZE(mxc_spi_resources ## n), \
66 }, { 66 .resource = mxc_spi_resources ## n, \
67 .start = MXC_INT_CSPI2, 67 }
68 .end = MXC_INT_CSPI2,
69 .flags = IORESOURCE_IRQ,
70 },
71};
72
73#ifdef CONFIG_MACH_MX27
74static struct resource mxc_spi_resources2[] = {
75 {
76 .start = CSPI3_BASE_ADDR,
77 .end = CSPI3_BASE_ADDR + SZ_4K - 1,
78 .flags = IORESOURCE_MEM,
79 }, {
80 .start = MXC_INT_CSPI3,
81 .end = MXC_INT_CSPI3,
82 .flags = IORESOURCE_IRQ,
83 },
84};
85#endif
86
87struct platform_device mxc_spi_device0 = {
88 .name = "spi_imx",
89 .id = 0,
90 .num_resources = ARRAY_SIZE(mxc_spi_resources0),
91 .resource = mxc_spi_resources0,
92};
93 68
94struct platform_device mxc_spi_device1 = { 69DEFINE_IMX_SPI_DEVICE(0, MX2x_CSPI1_BASE_ADDR, MX2x_INT_CSPI1);
95 .name = "spi_imx", 70DEFINE_IMX_SPI_DEVICE(1, MX2x_CSPI2_BASE_ADDR, MX2x_INT_CSPI2);
96 .id = 1,
97 .num_resources = ARRAY_SIZE(mxc_spi_resources1),
98 .resource = mxc_spi_resources1,
99};
100 71
101#ifdef CONFIG_MACH_MX27 72#ifdef CONFIG_MACH_MX27
102struct platform_device mxc_spi_device2 = { 73DEFINE_IMX_SPI_DEVICE(2, MX27_CSPI3_BASE_ADDR, MX27_INT_CSPI3);
103 .name = "spi_imx",
104 .id = 2,
105 .num_resources = ARRAY_SIZE(mxc_spi_resources2),
106 .resource = mxc_spi_resources2,
107};
108#endif 74#endif
109 75
110/* 76/*
@@ -112,104 +78,34 @@ struct platform_device mxc_spi_device2 = {
112 * - i.MX21: 3 timers 78 * - i.MX21: 3 timers
113 * - i.MX27: 6 timers 79 * - i.MX27: 6 timers
114 */ 80 */
115 81#define DEFINE_IMX_GPT_DEVICE(n, baseaddr, irq) \
116/* We use gpt0 as system timer, so do not add a device for this one */ 82 static struct resource timer ## n ##_resources[] = { \
117 83 { \
118static struct resource timer1_resources[] = { 84 .start = baseaddr, \
119 { 85 .end = baseaddr + SZ_4K - 1, \
120 .start = GPT2_BASE_ADDR, 86 .flags = IORESOURCE_MEM, \
121 .end = GPT2_BASE_ADDR + 0x17, 87 }, { \
122 .flags = IORESOURCE_MEM, 88 .start = irq, \
123 }, { 89 .end = irq, \
124 .start = MXC_INT_GPT2, 90 .flags = IORESOURCE_IRQ, \
125 .end = MXC_INT_GPT2, 91 } \
126 .flags = IORESOURCE_IRQ, 92 }; \
93 \
94 struct platform_device mxc_gpt ## n = { \
95 .name = "imx_gpt", \
96 .id = n, \
97 .num_resources = ARRAY_SIZE(timer ## n ## _resources), \
98 .resource = timer ## n ## _resources, \
127 } 99 }
128};
129
130struct platform_device mxc_gpt1 = {
131 .name = "imx_gpt",
132 .id = 1,
133 .num_resources = ARRAY_SIZE(timer1_resources),
134 .resource = timer1_resources,
135};
136 100
137static struct resource timer2_resources[] = { 101/* We use gpt1 as system timer, so do not add a device for this one */
138 { 102DEFINE_IMX_GPT_DEVICE(1, MX2x_GPT2_BASE_ADDR, MX2x_INT_GPT2);
139 .start = GPT3_BASE_ADDR, 103DEFINE_IMX_GPT_DEVICE(2, MX2x_GPT3_BASE_ADDR, MX2x_INT_GPT3);
140 .end = GPT3_BASE_ADDR + 0x17,
141 .flags = IORESOURCE_MEM,
142 }, {
143 .start = MXC_INT_GPT3,
144 .end = MXC_INT_GPT3,
145 .flags = IORESOURCE_IRQ,
146 }
147};
148
149struct platform_device mxc_gpt2 = {
150 .name = "imx_gpt",
151 .id = 2,
152 .num_resources = ARRAY_SIZE(timer2_resources),
153 .resource = timer2_resources,
154};
155 104
156#ifdef CONFIG_MACH_MX27 105#ifdef CONFIG_MACH_MX27
157static struct resource timer3_resources[] = { 106DEFINE_IMX_GPT_DEVICE(3, MX27_GPT4_BASE_ADDR, MX27_INT_GPT4);
158 { 107DEFINE_IMX_GPT_DEVICE(4, MX27_GPT5_BASE_ADDR, MX27_INT_GPT5);
159 .start = GPT4_BASE_ADDR, 108DEFINE_IMX_GPT_DEVICE(5, MX27_GPT6_BASE_ADDR, MX27_INT_GPT6);
160 .end = GPT4_BASE_ADDR + 0x17,
161 .flags = IORESOURCE_MEM,
162 }, {
163 .start = MXC_INT_GPT4,
164 .end = MXC_INT_GPT4,
165 .flags = IORESOURCE_IRQ,
166 }
167};
168
169struct platform_device mxc_gpt3 = {
170 .name = "imx_gpt",
171 .id = 3,
172 .num_resources = ARRAY_SIZE(timer3_resources),
173 .resource = timer3_resources,
174};
175
176static struct resource timer4_resources[] = {
177 {
178 .start = GPT5_BASE_ADDR,
179 .end = GPT5_BASE_ADDR + 0x17,
180 .flags = IORESOURCE_MEM,
181 }, {
182 .start = MXC_INT_GPT5,
183 .end = MXC_INT_GPT5,
184 .flags = IORESOURCE_IRQ,
185 }
186};
187
188struct platform_device mxc_gpt4 = {
189 .name = "imx_gpt",
190 .id = 4,
191 .num_resources = ARRAY_SIZE(timer4_resources),
192 .resource = timer4_resources,
193};
194
195static struct resource timer5_resources[] = {
196 {
197 .start = GPT6_BASE_ADDR,
198 .end = GPT6_BASE_ADDR + 0x17,
199 .flags = IORESOURCE_MEM,
200 }, {
201 .start = MXC_INT_GPT6,
202 .end = MXC_INT_GPT6,
203 .flags = IORESOURCE_IRQ,
204 }
205};
206
207struct platform_device mxc_gpt5 = {
208 .name = "imx_gpt",
209 .id = 5,
210 .num_resources = ARRAY_SIZE(timer5_resources),
211 .resource = timer5_resources,
212};
213#endif 109#endif
214 110
215/* 111/*
@@ -220,9 +116,9 @@ struct platform_device mxc_gpt5 = {
220 */ 116 */
221static struct resource mxc_wdt_resources[] = { 117static struct resource mxc_wdt_resources[] = {
222 { 118 {
223 .start = WDOG_BASE_ADDR, 119 .start = MX2x_WDOG_BASE_ADDR,
224 .end = WDOG_BASE_ADDR + 0x30, 120 .end = MX2x_WDOG_BASE_ADDR + SZ_4K - 1,
225 .flags = IORESOURCE_MEM, 121 .flags = IORESOURCE_MEM,
226 }, 122 },
227}; 123};
228 124
@@ -235,8 +131,8 @@ struct platform_device mxc_wdt = {
235 131
236static struct resource mxc_w1_master_resources[] = { 132static struct resource mxc_w1_master_resources[] = {
237 { 133 {
238 .start = OWIRE_BASE_ADDR, 134 .start = MX2x_OWIRE_BASE_ADDR,
239 .end = OWIRE_BASE_ADDR + SZ_4K - 1, 135 .end = MX2x_OWIRE_BASE_ADDR + SZ_4K - 1,
240 .flags = IORESOURCE_MEM, 136 .flags = IORESOURCE_MEM,
241 }, 137 },
242}; 138};
@@ -248,24 +144,33 @@ struct platform_device mxc_w1_master_device = {
248 .resource = mxc_w1_master_resources, 144 .resource = mxc_w1_master_resources,
249}; 145};
250 146
251static struct resource mxc_nand_resources[] = { 147#define DEFINE_MXC_NAND_DEVICE(pfx, baseaddr, irq) \
252 { 148 static struct resource pfx ## _nand_resources[] = { \
253 .start = NFC_BASE_ADDR, 149 { \
254 .end = NFC_BASE_ADDR + 0xfff, 150 .start = baseaddr, \
255 .flags = IORESOURCE_MEM, 151 .end = baseaddr + SZ_4K - 1, \
256 }, { 152 .flags = IORESOURCE_MEM, \
257 .start = MXC_INT_NANDFC, 153 }, { \
258 .end = MXC_INT_NANDFC, 154 .start = irq, \
259 .flags = IORESOURCE_IRQ, 155 .end = irq, \
260 }, 156 .flags = IORESOURCE_IRQ, \
261}; 157 }, \
158 }; \
159 \
160 struct platform_device pfx ## _nand_device = { \
161 .name = "mxc_nand", \
162 .id = 0, \
163 .num_resources = ARRAY_SIZE(pfx ## _nand_resources), \
164 .resource = pfx ## _nand_resources, \
165 }
262 166
263struct platform_device mxc_nand_device = { 167#ifdef CONFIG_MACH_MX21
264 .name = "mxc_nand", 168DEFINE_MXC_NAND_DEVICE(imx21, MX21_NFC_BASE_ADDR, MX21_INT_NANDFC);
265 .id = 0, 169#endif
266 .num_resources = ARRAY_SIZE(mxc_nand_resources), 170
267 .resource = mxc_nand_resources, 171#ifdef CONFIG_MACH_MX27
268}; 172DEFINE_MXC_NAND_DEVICE(imx27, MX27_NFC_BASE_ADDR, MX27_INT_NANDFC);
173#endif
269 174
270/* 175/*
271 * lcdc: 176 * lcdc:
@@ -275,12 +180,12 @@ struct platform_device mxc_nand_device = {
275 */ 180 */
276static struct resource mxc_fb[] = { 181static struct resource mxc_fb[] = {
277 { 182 {
278 .start = LCDC_BASE_ADDR, 183 .start = MX2x_LCDC_BASE_ADDR,
279 .end = LCDC_BASE_ADDR + 0xFFF, 184 .end = MX2x_LCDC_BASE_ADDR + SZ_4K - 1,
280 .flags = IORESOURCE_MEM, 185 .flags = IORESOURCE_MEM,
281 }, { 186 }, {
282 .start = MXC_INT_LCDC, 187 .start = MX2x_INT_LCDC,
283 .end = MXC_INT_LCDC, 188 .end = MX2x_INT_LCDC,
284 .flags = IORESOURCE_IRQ, 189 .flags = IORESOURCE_IRQ,
285 } 190 }
286}; 191};
@@ -299,13 +204,13 @@ struct platform_device mxc_fb_device = {
299#ifdef CONFIG_MACH_MX27 204#ifdef CONFIG_MACH_MX27
300static struct resource mxc_fec_resources[] = { 205static struct resource mxc_fec_resources[] = {
301 { 206 {
302 .start = FEC_BASE_ADDR, 207 .start = MX27_FEC_BASE_ADDR,
303 .end = FEC_BASE_ADDR + 0xfff, 208 .end = MX27_FEC_BASE_ADDR + SZ_4K - 1,
304 .flags = IORESOURCE_MEM, 209 .flags = IORESOURCE_MEM,
305 }, { 210 }, {
306 .start = MXC_INT_FEC, 211 .start = MX27_INT_FEC,
307 .end = MXC_INT_FEC, 212 .end = MX27_INT_FEC,
308 .flags = IORESOURCE_IRQ, 213 .flags = IORESOURCE_IRQ,
309 }, 214 },
310}; 215};
311 216
@@ -317,55 +222,41 @@ struct platform_device mxc_fec_device = {
317}; 222};
318#endif 223#endif
319 224
320static struct resource mxc_i2c_1_resources[] = { 225#define DEFINE_IMX_I2C_DEVICE(n, baseaddr, irq) \
321 { 226 static struct resource mxc_i2c_resources ## n[] = { \
322 .start = I2C_BASE_ADDR, 227 { \
323 .end = I2C_BASE_ADDR + 0x0fff, 228 .start = baseaddr, \
324 .flags = IORESOURCE_MEM, 229 .end = baseaddr + SZ_4K - 1, \
325 }, { 230 .flags = IORESOURCE_MEM, \
326 .start = MXC_INT_I2C, 231 }, { \
327 .end = MXC_INT_I2C, 232 .start = irq, \
328 .flags = IORESOURCE_IRQ, 233 .end = irq, \
234 .flags = IORESOURCE_IRQ, \
235 } \
236 }; \
237 \
238 struct platform_device mxc_i2c_device ## n = { \
239 .name = "imx-i2c", \
240 .id = n, \
241 .num_resources = ARRAY_SIZE(mxc_i2c_resources ## n), \
242 .resource = mxc_i2c_resources ## n, \
329 } 243 }
330};
331 244
332struct platform_device mxc_i2c_device0 = { 245DEFINE_IMX_I2C_DEVICE(0, MX2x_I2C_BASE_ADDR, MX2x_INT_I2C);
333 .name = "imx-i2c",
334 .id = 0,
335 .num_resources = ARRAY_SIZE(mxc_i2c_1_resources),
336 .resource = mxc_i2c_1_resources,
337};
338 246
339#ifdef CONFIG_MACH_MX27 247#ifdef CONFIG_MACH_MX27
340static struct resource mxc_i2c_2_resources[] = { 248DEFINE_IMX_I2C_DEVICE(1, MX27_I2C2_BASE_ADDR, MX27_INT_I2C2);
341 {
342 .start = I2C2_BASE_ADDR,
343 .end = I2C2_BASE_ADDR + 0x0fff,
344 .flags = IORESOURCE_MEM,
345 }, {
346 .start = MXC_INT_I2C2,
347 .end = MXC_INT_I2C2,
348 .flags = IORESOURCE_IRQ,
349 }
350};
351
352struct platform_device mxc_i2c_device1 = {
353 .name = "imx-i2c",
354 .id = 1,
355 .num_resources = ARRAY_SIZE(mxc_i2c_2_resources),
356 .resource = mxc_i2c_2_resources,
357};
358#endif 249#endif
359 250
360static struct resource mxc_pwm_resources[] = { 251static struct resource mxc_pwm_resources[] = {
361 { 252 {
362 .start = PWM_BASE_ADDR, 253 .start = MX2x_PWM_BASE_ADDR,
363 .end = PWM_BASE_ADDR + 0x0fff, 254 .end = MX2x_PWM_BASE_ADDR + SZ_4K - 1,
364 .flags = IORESOURCE_MEM, 255 .flags = IORESOURCE_MEM,
365 }, { 256 }, {
366 .start = MXC_INT_PWM, 257 .start = MX2x_INT_PWM,
367 .end = MXC_INT_PWM, 258 .end = MX2x_INT_PWM,
368 .flags = IORESOURCE_IRQ, 259 .flags = IORESOURCE_IRQ,
369 } 260 }
370}; 261};
371 262
@@ -379,74 +270,49 @@ struct platform_device mxc_pwm_device = {
379/* 270/*
380 * Resource definition for the MXC SDHC 271 * Resource definition for the MXC SDHC
381 */ 272 */
382static struct resource mxc_sdhc1_resources[] = { 273#define DEFINE_MXC_MMC_DEVICE(n, baseaddr, irq, dmareq) \
383 { 274 static struct resource mxc_sdhc_resources ## n[] = { \
384 .start = SDHC1_BASE_ADDR, 275 { \
385 .end = SDHC1_BASE_ADDR + SZ_4K - 1, 276 .start = baseaddr, \
386 .flags = IORESOURCE_MEM, 277 .end = baseaddr + SZ_4K - 1, \
387 }, { 278 .flags = IORESOURCE_MEM, \
388 .start = MXC_INT_SDHC1, 279 }, { \
389 .end = MXC_INT_SDHC1, 280 .start = irq, \
390 .flags = IORESOURCE_IRQ, 281 .end = irq, \
391 }, { 282 .flags = IORESOURCE_IRQ, \
392 .start = DMA_REQ_SDHC1, 283 }, { \
393 .end = DMA_REQ_SDHC1, 284 .start = dmareq, \
394 .flags = IORESOURCE_DMA, 285 .end = dmareq, \
395 }, 286 .flags = IORESOURCE_DMA, \
396}; 287 }, \
397 288 }; \
398static u64 mxc_sdhc1_dmamask = 0xffffffffUL; 289 \
399 290 static u64 mxc_sdhc ## n ## _dmamask = 0xffffffffUL; \
400struct platform_device mxc_sdhc_device0 = { 291 \
401 .name = "mxc-mmc", 292 struct platform_device mxc_sdhc_device ## n = { \
402 .id = 0, 293 .name = "mxc-mmc", \
403 .dev = { 294 .id = n, \
404 .dma_mask = &mxc_sdhc1_dmamask, 295 .dev = { \
405 .coherent_dma_mask = 0xffffffff, 296 .dma_mask = &mxc_sdhc ## n ## _dmamask, \
406 }, 297 .coherent_dma_mask = 0xffffffff, \
407 .num_resources = ARRAY_SIZE(mxc_sdhc1_resources), 298 }, \
408 .resource = mxc_sdhc1_resources, 299 .num_resources = ARRAY_SIZE(mxc_sdhc_resources ## n), \
409}; 300 .resource = mxc_sdhc_resources ## n, \
410 301 }
411static struct resource mxc_sdhc2_resources[] = {
412 {
413 .start = SDHC2_BASE_ADDR,
414 .end = SDHC2_BASE_ADDR + SZ_4K - 1,
415 .flags = IORESOURCE_MEM,
416 }, {
417 .start = MXC_INT_SDHC2,
418 .end = MXC_INT_SDHC2,
419 .flags = IORESOURCE_IRQ,
420 }, {
421 .start = DMA_REQ_SDHC2,
422 .end = DMA_REQ_SDHC2,
423 .flags = IORESOURCE_DMA,
424 },
425};
426 302
427static u64 mxc_sdhc2_dmamask = 0xffffffffUL; 303DEFINE_MXC_MMC_DEVICE(0, MX2x_SDHC1_BASE_ADDR, MX2x_INT_SDHC1, MX2x_DMA_REQ_SDHC1);
428 304DEFINE_MXC_MMC_DEVICE(1, MX2x_SDHC2_BASE_ADDR, MX2x_INT_SDHC2, MX2x_DMA_REQ_SDHC2);
429struct platform_device mxc_sdhc_device1 = {
430 .name = "mxc-mmc",
431 .id = 1,
432 .dev = {
433 .dma_mask = &mxc_sdhc2_dmamask,
434 .coherent_dma_mask = 0xffffffff,
435 },
436 .num_resources = ARRAY_SIZE(mxc_sdhc2_resources),
437 .resource = mxc_sdhc2_resources,
438};
439 305
440#ifdef CONFIG_MACH_MX27 306#ifdef CONFIG_MACH_MX27
441static struct resource otg_resources[] = { 307static struct resource otg_resources[] = {
442 { 308 {
443 .start = OTG_BASE_ADDR, 309 .start = MX27_USBOTG_BASE_ADDR,
444 .end = OTG_BASE_ADDR + 0x1ff, 310 .end = MX27_USBOTG_BASE_ADDR + 0x1ff,
445 .flags = IORESOURCE_MEM, 311 .flags = IORESOURCE_MEM,
446 }, { 312 }, {
447 .start = MXC_INT_USB3, 313 .start = MX27_INT_USB3,
448 .end = MXC_INT_USB3, 314 .end = MX27_INT_USB3,
449 .flags = IORESOURCE_IRQ, 315 .flags = IORESOURCE_IRQ,
450 }, 316 },
451}; 317};
452 318
@@ -454,14 +320,14 @@ static u64 otg_dmamask = 0xffffffffUL;
454 320
455/* OTG gadget device */ 321/* OTG gadget device */
456struct platform_device mxc_otg_udc_device = { 322struct platform_device mxc_otg_udc_device = {
457 .name = "fsl-usb2-udc", 323 .name = "fsl-usb2-udc",
458 .id = -1, 324 .id = -1,
459 .dev = { 325 .dev = {
460 .dma_mask = &otg_dmamask, 326 .dma_mask = &otg_dmamask,
461 .coherent_dma_mask = 0xffffffffUL, 327 .coherent_dma_mask = 0xffffffffUL,
462 }, 328 },
463 .resource = otg_resources, 329 .resource = otg_resources,
464 .num_resources = ARRAY_SIZE(otg_resources), 330 .num_resources = ARRAY_SIZE(otg_resources),
465}; 331};
466 332
467/* OTG host */ 333/* OTG host */
@@ -482,12 +348,12 @@ static u64 usbh1_dmamask = 0xffffffffUL;
482 348
483static struct resource mxc_usbh1_resources[] = { 349static struct resource mxc_usbh1_resources[] = {
484 { 350 {
485 .start = OTG_BASE_ADDR + 0x200, 351 .start = MX27_USBOTG_BASE_ADDR + 0x200,
486 .end = OTG_BASE_ADDR + 0x3ff, 352 .end = MX27_USBOTG_BASE_ADDR + 0x3ff,
487 .flags = IORESOURCE_MEM, 353 .flags = IORESOURCE_MEM,
488 }, { 354 }, {
489 .start = MXC_INT_USB1, 355 .start = MX27_INT_USB1,
490 .end = MXC_INT_USB1, 356 .end = MX27_INT_USB1,
491 .flags = IORESOURCE_IRQ, 357 .flags = IORESOURCE_IRQ,
492 }, 358 },
493}; 359};
@@ -508,12 +374,12 @@ static u64 usbh2_dmamask = 0xffffffffUL;
508 374
509static struct resource mxc_usbh2_resources[] = { 375static struct resource mxc_usbh2_resources[] = {
510 { 376 {
511 .start = OTG_BASE_ADDR + 0x400, 377 .start = MX27_USBOTG_BASE_ADDR + 0x400,
512 .end = OTG_BASE_ADDR + 0x5ff, 378 .end = MX27_USBOTG_BASE_ADDR + 0x5ff,
513 .flags = IORESOURCE_MEM, 379 .flags = IORESOURCE_MEM,
514 }, { 380 }, {
515 .start = MXC_INT_USB2, 381 .start = MX27_INT_USB2,
516 .end = MXC_INT_USB2, 382 .end = MX27_INT_USB2,
517 .flags = IORESOURCE_IRQ, 383 .flags = IORESOURCE_IRQ,
518 }, 384 },
519}; 385};
@@ -530,115 +396,88 @@ struct platform_device mxc_usbh2 = {
530}; 396};
531#endif 397#endif
532 398
533static struct resource imx_ssi_resources0[] = { 399#define DEFINE_IMX_SSI_DMARES(_name, ssin, suffix) \
534 { 400 { \
535 .start = SSI1_BASE_ADDR, 401 .name = _name, \
536 .end = SSI1_BASE_ADDR + 0x6F, 402 .start = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \
537 .flags = IORESOURCE_MEM, 403 .end = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \
538 }, { 404 .flags = IORESOURCE_DMA, \
539 .start = MXC_INT_SSI1, 405 }
540 .end = MXC_INT_SSI1,
541 .flags = IORESOURCE_IRQ,
542 }, {
543 .name = "tx0",
544 .start = DMA_REQ_SSI1_TX0,
545 .end = DMA_REQ_SSI1_TX0,
546 .flags = IORESOURCE_DMA,
547 }, {
548 .name = "rx0",
549 .start = DMA_REQ_SSI1_RX0,
550 .end = DMA_REQ_SSI1_RX0,
551 .flags = IORESOURCE_DMA,
552 }, {
553 .name = "tx1",
554 .start = DMA_REQ_SSI1_TX1,
555 .end = DMA_REQ_SSI1_TX1,
556 .flags = IORESOURCE_DMA,
557 }, {
558 .name = "rx1",
559 .start = DMA_REQ_SSI1_RX1,
560 .end = DMA_REQ_SSI1_RX1,
561 .flags = IORESOURCE_DMA,
562 },
563};
564
565static struct resource imx_ssi_resources1[] = {
566 {
567 .start = SSI2_BASE_ADDR,
568 .end = SSI2_BASE_ADDR + 0x6F,
569 .flags = IORESOURCE_MEM,
570 }, {
571 .start = MXC_INT_SSI2,
572 .end = MXC_INT_SSI2,
573 .flags = IORESOURCE_IRQ,
574 }, {
575 .name = "tx0",
576 .start = DMA_REQ_SSI2_TX0,
577 .end = DMA_REQ_SSI2_TX0,
578 .flags = IORESOURCE_DMA,
579 }, {
580 .name = "rx0",
581 .start = DMA_REQ_SSI2_RX0,
582 .end = DMA_REQ_SSI2_RX0,
583 .flags = IORESOURCE_DMA,
584 }, {
585 .name = "tx1",
586 .start = DMA_REQ_SSI2_TX1,
587 .end = DMA_REQ_SSI2_TX1,
588 .flags = IORESOURCE_DMA,
589 }, {
590 .name = "rx1",
591 .start = DMA_REQ_SSI2_RX1,
592 .end = DMA_REQ_SSI2_RX1,
593 .flags = IORESOURCE_DMA,
594 },
595};
596 406
597struct platform_device imx_ssi_device0 = { 407#define DEFINE_IMX_SSI_DEVICE(n, ssin, baseaddr, irq) \
598 .name = "imx-ssi", 408 static struct resource imx_ssi_resources ## n[] = { \
599 .id = 0, 409 { \
600 .num_resources = ARRAY_SIZE(imx_ssi_resources0), 410 .start = MX2x_SSI ## ssin ## _BASE_ADDR, \
601 .resource = imx_ssi_resources0, 411 .end = MX2x_SSI ## ssin ## _BASE_ADDR + 0x6f, \
602}; 412 .flags = IORESOURCE_MEM, \
413 }, { \
414 .start = MX2x_INT_SSI1, \
415 .end = MX2x_INT_SSI1, \
416 .flags = IORESOURCE_IRQ, \
417 }, \
418 DEFINE_IMX_SSI_DMARES("tx0", ssin, TX0), \
419 DEFINE_IMX_SSI_DMARES("rx0", ssin, RX0), \
420 DEFINE_IMX_SSI_DMARES("tx1", ssin, TX1), \
421 DEFINE_IMX_SSI_DMARES("rx1", ssin, RX1), \
422 }; \
423 \
424 struct platform_device imx_ssi_device ## n = { \
425 .name = "imx-ssi", \
426 .id = n, \
427 .num_resources = ARRAY_SIZE(imx_ssi_resources ## n), \
428 .resource = imx_ssi_resources ## n, \
429 }
603 430
604struct platform_device imx_ssi_device1 = { 431DEFINE_IMX_SSI_DEVICE(0, 1, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
605 .name = "imx-ssi", 432DEFINE_IMX_SSI_DEVICE(1, 2, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
606 .id = 1,
607 .num_resources = ARRAY_SIZE(imx_ssi_resources1),
608 .resource = imx_ssi_resources1,
609};
610 433
611/* GPIO port description */ 434/* GPIO port description */
612static struct mxc_gpio_port imx_gpio_ports[] = { 435#define DEFINE_MXC_GPIO_PORT_IRQ(SOC, n, _irq) \
613 { 436 { \
614 .chip.label = "gpio-0", 437 .chip.label = "gpio-" #n, \
615 .irq = MXC_INT_GPIO, 438 .irq = _irq, \
616 .base = IO_ADDRESS(GPIO_BASE_ADDR), 439 .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
617 .virtual_irq_start = MXC_GPIO_IRQ_START, 440 n * 0x100), \
618 }, { 441 .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
619 .chip.label = "gpio-1",
620 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x100),
621 .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
622 }, {
623 .chip.label = "gpio-2",
624 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x200),
625 .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
626 }, {
627 .chip.label = "gpio-3",
628 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x300),
629 .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
630 }, {
631 .chip.label = "gpio-4",
632 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x400),
633 .virtual_irq_start = MXC_GPIO_IRQ_START + 128,
634 }, {
635 .chip.label = "gpio-5",
636 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x500),
637 .virtual_irq_start = MXC_GPIO_IRQ_START + 160,
638 } 442 }
639}; 443
444#define DEFINE_MXC_GPIO_PORT(SOC, n) \
445 { \
446 .chip.label = "gpio-" #n, \
447 .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
448 n * 0x100), \
449 .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
450 }
451
452#define DEFINE_MXC_GPIO_PORTS(SOC, pfx) \
453 static struct mxc_gpio_port pfx ## _gpio_ports[] = { \
454 DEFINE_MXC_GPIO_PORT_IRQ(SOC, 0, SOC ## _INT_GPIO), \
455 DEFINE_MXC_GPIO_PORT(SOC, 1), \
456 DEFINE_MXC_GPIO_PORT(SOC, 2), \
457 DEFINE_MXC_GPIO_PORT(SOC, 3), \
458 DEFINE_MXC_GPIO_PORT(SOC, 4), \
459 DEFINE_MXC_GPIO_PORT(SOC, 5), \
460 }
461
462#ifdef CONFIG_MACH_MX21
463DEFINE_MXC_GPIO_PORTS(MX21, imx21);
464#endif
465
466#ifdef CONFIG_MACH_MX27
467DEFINE_MXC_GPIO_PORTS(MX27, imx27);
468#endif
640 469
641int __init mxc_register_gpios(void) 470int __init mxc_register_gpios(void)
642{ 471{
643 return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports)); 472#ifdef CONFIG_MACH_MX21
473 if (cpu_is_mx21())
474 return mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports));
475 else
476#endif
477#ifdef CONFIG_MACH_MX27
478 if (cpu_is_mx27())
479 return mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports));
480 else
481#endif
482 return 0;
644} 483}
diff --git a/arch/arm/mach-mx2/devices.h b/arch/arm/mach-mx2/devices.h
index 97306aa18f1c..f15df2aaae4d 100644
--- a/arch/arm/mach-mx2/devices.h
+++ b/arch/arm/mach-mx2/devices.h
@@ -1,8 +1,10 @@
1extern struct platform_device mxc_gpt1; 1extern struct platform_device mxc_gpt1;
2extern struct platform_device mxc_gpt2; 2extern struct platform_device mxc_gpt2;
3#ifdef CONFIG_MACH_MX27
3extern struct platform_device mxc_gpt3; 4extern struct platform_device mxc_gpt3;
4extern struct platform_device mxc_gpt4; 5extern struct platform_device mxc_gpt4;
5extern struct platform_device mxc_gpt5; 6extern struct platform_device mxc_gpt5;
7#endif
6extern struct platform_device mxc_wdt; 8extern struct platform_device mxc_wdt;
7extern struct platform_device mxc_uart_device0; 9extern struct platform_device mxc_uart_device0;
8extern struct platform_device mxc_uart_device1; 10extern struct platform_device mxc_uart_device1;
@@ -11,12 +13,19 @@ extern struct platform_device mxc_uart_device3;
11extern struct platform_device mxc_uart_device4; 13extern struct platform_device mxc_uart_device4;
12extern struct platform_device mxc_uart_device5; 14extern struct platform_device mxc_uart_device5;
13extern struct platform_device mxc_w1_master_device; 15extern struct platform_device mxc_w1_master_device;
14extern struct platform_device mxc_nand_device; 16#ifdef CONFIG_MACH_MX21
17extern struct platform_device imx21_nand_device;
18#endif
19#ifdef CONFIG_MACH_MX27
20extern struct platform_device imx27_nand_device;
21#endif
15extern struct platform_device mxc_fb_device; 22extern struct platform_device mxc_fb_device;
16extern struct platform_device mxc_fec_device; 23extern struct platform_device mxc_fec_device;
17extern struct platform_device mxc_pwm_device; 24extern struct platform_device mxc_pwm_device;
18extern struct platform_device mxc_i2c_device0; 25extern struct platform_device mxc_i2c_device0;
26#ifdef CONFIG_MACH_MX27
19extern struct platform_device mxc_i2c_device1; 27extern struct platform_device mxc_i2c_device1;
28#endif
20extern struct platform_device mxc_sdhc_device0; 29extern struct platform_device mxc_sdhc_device0;
21extern struct platform_device mxc_sdhc_device1; 30extern struct platform_device mxc_sdhc_device1;
22extern struct platform_device mxc_otg_udc_device; 31extern struct platform_device mxc_otg_udc_device;
@@ -25,6 +34,8 @@ extern struct platform_device mxc_usbh1;
25extern struct platform_device mxc_usbh2; 34extern struct platform_device mxc_usbh2;
26extern struct platform_device mxc_spi_device0; 35extern struct platform_device mxc_spi_device0;
27extern struct platform_device mxc_spi_device1; 36extern struct platform_device mxc_spi_device1;
37#ifdef CONFIG_MACH_MX27
28extern struct platform_device mxc_spi_device2; 38extern struct platform_device mxc_spi_device2;
39#endif
29extern struct platform_device imx_ssi_device0; 40extern struct platform_device imx_ssi_device0;
30extern struct platform_device imx_ssi_device1; 41extern struct platform_device imx_ssi_device1;
diff --git a/arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c b/arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c
index 7382b6d27ee1..f3b169d5245f 100644
--- a/arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c
+++ b/arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c
@@ -28,7 +28,7 @@
28#include <asm/mach/arch.h> 28#include <asm/mach/arch.h>
29 29
30#include <mach/common.h> 30#include <mach/common.h>
31#include <mach/iomux.h> 31#include <mach/iomux-mx27.h>
32#include <mach/imxfb.h> 32#include <mach/imxfb.h>
33#include <mach/hardware.h> 33#include <mach/hardware.h>
34#include <mach/mmc.h> 34#include <mach/mmc.h>
diff --git a/arch/arm/mach-mx2/mach-cpuimx27.c b/arch/arm/mach-mx2/mach-cpuimx27.c
index 92fd1bf7a638..1f616dcaabc9 100644
--- a/arch/arm/mach-mx2/mach-cpuimx27.c
+++ b/arch/arm/mach-mx2/mach-cpuimx27.c
@@ -36,7 +36,7 @@
36#include <mach/common.h> 36#include <mach/common.h>
37#include <mach/hardware.h> 37#include <mach/hardware.h>
38#include <mach/i2c.h> 38#include <mach/i2c.h>
39#include <mach/iomux.h> 39#include <mach/iomux-mx27.h>
40#include <mach/imx-uart.h> 40#include <mach/imx-uart.h>
41#include <mach/mxc_nand.h> 41#include <mach/mxc_nand.h>
42 42
@@ -189,7 +189,8 @@ static void __init eukrea_cpuimx27_init(void)
189 189
190 mxc_register_device(&mxc_uart_device0, &uart_pdata[0]); 190 mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
191 191
192 mxc_register_device(&mxc_nand_device, &eukrea_cpuimx27_nand_board_info); 192 mxc_register_device(&imx27_nand_device,
193 &eukrea_cpuimx27_nand_board_info);
193 194
194 i2c_register_board_info(0, eukrea_cpuimx27_i2c_devices, 195 i2c_register_board_info(0, eukrea_cpuimx27_i2c_devices,
195 ARRAY_SIZE(eukrea_cpuimx27_i2c_devices)); 196 ARRAY_SIZE(eukrea_cpuimx27_i2c_devices));
diff --git a/arch/arm/mach-mx2/mach-imx27lite.c b/arch/arm/mach-mx2/mach-imx27lite.c
index 621c2c1046ea..b5710bf18b96 100644
--- a/arch/arm/mach-mx2/mach-imx27lite.c
+++ b/arch/arm/mach-mx2/mach-imx27lite.c
@@ -27,7 +27,7 @@
27#include <mach/hardware.h> 27#include <mach/hardware.h>
28#include <mach/common.h> 28#include <mach/common.h>
29#include <mach/imx-uart.h> 29#include <mach/imx-uart.h>
30#include <mach/iomux.h> 30#include <mach/iomux-mx27.h>
31#include <mach/board-mx27lite.h> 31#include <mach/board-mx27lite.h>
32 32
33#include "devices.h" 33#include "devices.h"
diff --git a/arch/arm/mach-mx2/mach-mx21ads.c b/arch/arm/mach-mx2/mach-mx21ads.c
index d5eb8065df3e..113e58d7cb40 100644
--- a/arch/arm/mach-mx2/mach-mx21ads.c
+++ b/arch/arm/mach-mx2/mach-mx21ads.c
@@ -30,7 +30,7 @@
30#include <asm/mach/map.h> 30#include <asm/mach/map.h>
31#include <mach/imx-uart.h> 31#include <mach/imx-uart.h>
32#include <mach/imxfb.h> 32#include <mach/imxfb.h>
33#include <mach/iomux.h> 33#include <mach/iomux-mx21.h>
34#include <mach/mxc_nand.h> 34#include <mach/mxc_nand.h>
35#include <mach/mmc.h> 35#include <mach/mmc.h>
36#include <mach/board-mx21ads.h> 36#include <mach/board-mx21ads.h>
@@ -268,7 +268,7 @@ static void __init mx21ads_board_init(void)
268 mxc_register_device(&mxc_uart_device3, &uart_pdata); 268 mxc_register_device(&mxc_uart_device3, &uart_pdata);
269 mxc_register_device(&mxc_fb_device, &mx21ads_fb_data); 269 mxc_register_device(&mxc_fb_device, &mx21ads_fb_data);
270 mxc_register_device(&mxc_sdhc_device0, &mx21ads_sdhc_pdata); 270 mxc_register_device(&mxc_sdhc_device0, &mx21ads_sdhc_pdata);
271 mxc_register_device(&mxc_nand_device, &mx21ads_nand_board_info); 271 mxc_register_device(&imx21_nand_device, &mx21ads_nand_board_info);
272 272
273 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); 273 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
274} 274}
diff --git a/arch/arm/mach-mx2/mach-mx27_3ds.c b/arch/arm/mach-mx2/mach-mx27_3ds.c
index 8c975f6514ad..b2f4e0db3fb3 100644
--- a/arch/arm/mach-mx2/mach-mx27_3ds.c
+++ b/arch/arm/mach-mx2/mach-mx27_3ds.c
@@ -26,7 +26,7 @@
26#include <mach/hardware.h> 26#include <mach/hardware.h>
27#include <mach/common.h> 27#include <mach/common.h>
28#include <mach/imx-uart.h> 28#include <mach/imx-uart.h>
29#include <mach/iomux.h> 29#include <mach/iomux-mx27.h>
30#include <mach/board-mx27pdk.h> 30#include <mach/board-mx27pdk.h>
31 31
32#include "devices.h" 32#include "devices.h"
diff --git a/arch/arm/mach-mx2/mach-mx27ads.c b/arch/arm/mach-mx2/mach-mx27ads.c
index 808ca271a829..6ce323669e58 100644
--- a/arch/arm/mach-mx2/mach-mx27ads.c
+++ b/arch/arm/mach-mx2/mach-mx27ads.c
@@ -33,7 +33,7 @@
33#include <asm/mach/map.h> 33#include <asm/mach/map.h>
34#include <mach/gpio.h> 34#include <mach/gpio.h>
35#include <mach/imx-uart.h> 35#include <mach/imx-uart.h>
36#include <mach/iomux.h> 36#include <mach/iomux-mx27.h>
37#include <mach/board-mx27ads.h> 37#include <mach/board-mx27ads.h>
38#include <mach/mxc_nand.h> 38#include <mach/mxc_nand.h>
39#include <mach/i2c.h> 39#include <mach/i2c.h>
@@ -290,7 +290,7 @@ static void __init mx27ads_board_init(void)
290 mxc_register_device(&mxc_uart_device3, &uart_pdata[3]); 290 mxc_register_device(&mxc_uart_device3, &uart_pdata[3]);
291 mxc_register_device(&mxc_uart_device4, &uart_pdata[4]); 291 mxc_register_device(&mxc_uart_device4, &uart_pdata[4]);
292 mxc_register_device(&mxc_uart_device5, &uart_pdata[5]); 292 mxc_register_device(&mxc_uart_device5, &uart_pdata[5]);
293 mxc_register_device(&mxc_nand_device, &mx27ads_nand_board_info); 293 mxc_register_device(&imx27_nand_device, &mx27ads_nand_board_info);
294 294
295 /* only the i2c master 1 is used on this CPU card */ 295 /* only the i2c master 1 is used on this CPU card */
296 i2c_register_board_info(1, mx27ads_i2c_devices, 296 i2c_register_board_info(1, mx27ads_i2c_devices,
diff --git a/arch/arm/mach-mx2/mach-mxt_td60.c b/arch/arm/mach-mx2/mach-mxt_td60.c
index df954d879cc3..bc3855992677 100644
--- a/arch/arm/mach-mx2/mach-mxt_td60.c
+++ b/arch/arm/mach-mx2/mach-mxt_td60.c
@@ -33,7 +33,7 @@
33#include <asm/mach/map.h> 33#include <asm/mach/map.h>
34#include <linux/gpio.h> 34#include <linux/gpio.h>
35#include <mach/imx-uart.h> 35#include <mach/imx-uart.h>
36#include <mach/iomux.h> 36#include <mach/iomux-mx27.h>
37#include <mach/mxc_nand.h> 37#include <mach/mxc_nand.h>
38#include <mach/i2c.h> 38#include <mach/i2c.h>
39#include <linux/i2c/pca953x.h> 39#include <linux/i2c/pca953x.h>
@@ -257,7 +257,7 @@ static void __init mxt_td60_board_init(void)
257 mxc_register_device(&mxc_uart_device0, &uart_pdata[0]); 257 mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
258 mxc_register_device(&mxc_uart_device1, &uart_pdata[1]); 258 mxc_register_device(&mxc_uart_device1, &uart_pdata[1]);
259 mxc_register_device(&mxc_uart_device2, &uart_pdata[2]); 259 mxc_register_device(&mxc_uart_device2, &uart_pdata[2]);
260 mxc_register_device(&mxc_nand_device, &mxt_td60_nand_board_info); 260 mxc_register_device(&imx27_nand_device, &mxt_td60_nand_board_info);
261 261
262 i2c_register_board_info(0, mxt_td60_i2c_devices, 262 i2c_register_board_info(0, mxt_td60_i2c_devices,
263 ARRAY_SIZE(mxt_td60_i2c_devices)); 263 ARRAY_SIZE(mxt_td60_i2c_devices));
diff --git a/arch/arm/mach-mx2/mach-pca100.c b/arch/arm/mach-mx2/mach-pca100.c
index d12bdb1fcabb..778fff230918 100644
--- a/arch/arm/mach-mx2/mach-pca100.c
+++ b/arch/arm/mach-mx2/mach-pca100.c
@@ -35,7 +35,7 @@
35#include <asm/mach-types.h> 35#include <asm/mach-types.h>
36#include <mach/common.h> 36#include <mach/common.h>
37#include <mach/hardware.h> 37#include <mach/hardware.h>
38#include <mach/iomux.h> 38#include <mach/iomux-mx27.h>
39#include <mach/i2c.h> 39#include <mach/i2c.h>
40#include <asm/mach/time.h> 40#include <asm/mach/time.h>
41#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE) 41#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
@@ -324,7 +324,7 @@ static void __init pca100_init(void)
324 mxc_gpio_mode(GPIO_PORTC | 29 | GPIO_GPIO | GPIO_IN); 324 mxc_gpio_mode(GPIO_PORTC | 29 | GPIO_GPIO | GPIO_IN);
325 mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata); 325 mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata);
326 326
327 mxc_register_device(&mxc_nand_device, &pca100_nand_board_info); 327 mxc_register_device(&imx27_nand_device, &pca100_nand_board_info);
328 328
329 /* only the i2c master 1 is used on this CPU card */ 329 /* only the i2c master 1 is used on this CPU card */
330 i2c_register_board_info(1, pca100_i2c_devices, 330 i2c_register_board_info(1, pca100_i2c_devices,
diff --git a/arch/arm/mach-mx2/mach-pcm038.c b/arch/arm/mach-mx2/mach-pcm038.c
index 5a0169cff20f..035fbe046ec0 100644
--- a/arch/arm/mach-mx2/mach-pcm038.c
+++ b/arch/arm/mach-mx2/mach-pcm038.c
@@ -36,7 +36,7 @@
36#include <mach/common.h> 36#include <mach/common.h>
37#include <mach/hardware.h> 37#include <mach/hardware.h>
38#include <mach/i2c.h> 38#include <mach/i2c.h>
39#include <mach/iomux.h> 39#include <mach/iomux-mx27.h>
40#include <mach/imx-uart.h> 40#include <mach/imx-uart.h>
41#include <mach/mxc_nand.h> 41#include <mach/mxc_nand.h>
42#include <mach/spi.h> 42#include <mach/spi.h>
@@ -309,7 +309,7 @@ static void __init pcm038_init(void)
309 mxc_register_device(&mxc_uart_device2, &uart_pdata[2]); 309 mxc_register_device(&mxc_uart_device2, &uart_pdata[2]);
310 310
311 mxc_gpio_mode(PE16_AF_OWIRE); 311 mxc_gpio_mode(PE16_AF_OWIRE);
312 mxc_register_device(&mxc_nand_device, &pcm038_nand_board_info); 312 mxc_register_device(&imx27_nand_device, &pcm038_nand_board_info);
313 313
314 /* only the i2c master 1 is used on this CPU card */ 314 /* only the i2c master 1 is used on this CPU card */
315 i2c_register_board_info(1, pcm038_i2c_devices, 315 i2c_register_board_info(1, pcm038_i2c_devices,
diff --git a/arch/arm/mach-mx2/mm-imx21.c b/arch/arm/mach-mx2/mm-imx21.c
new file mode 100644
index 000000000000..64134314d012
--- /dev/null
+++ b/arch/arm/mach-mx2/mm-imx21.c
@@ -0,0 +1,83 @@
1/*
2 * arch/arm/mach-mx2/mm-imx21.c
3 *
4 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
18 * MA 02110-1301, USA.
19 */
20
21#include <linux/mm.h>
22#include <linux/init.h>
23#include <mach/hardware.h>
24#include <mach/common.h>
25#include <asm/pgtable.h>
26#include <asm/mach/map.h>
27
28/* MX21 memory map definition */
29static struct map_desc imx21_io_desc[] __initdata = {
30 /*
31 * this fixed mapping covers:
32 * - AIPI1
33 * - AIPI2
34 * - AITC
35 * - ROM Patch
36 * - and some reserved space
37 */
38 {
39 .virtual = MX21_AIPI_BASE_ADDR_VIRT,
40 .pfn = __phys_to_pfn(MX21_AIPI_BASE_ADDR),
41 .length = MX21_AIPI_SIZE,
42 .type = MT_DEVICE
43 },
44 /*
45 * this fixed mapping covers:
46 * - CSI
47 * - ATA
48 */
49 {
50 .virtual = MX21_SAHB1_BASE_ADDR_VIRT,
51 .pfn = __phys_to_pfn(MX21_SAHB1_BASE_ADDR),
52 .length = MX21_SAHB1_SIZE,
53 .type = MT_DEVICE
54 },
55 /*
56 * this fixed mapping covers:
57 * - EMI
58 */
59 {
60 .virtual = MX21_X_MEMC_BASE_ADDR_VIRT,
61 .pfn = __phys_to_pfn(MX21_X_MEMC_BASE_ADDR),
62 .length = MX21_X_MEMC_SIZE,
63 .type = MT_DEVICE
64 },
65};
66
67/*
68 * Initialize the memory map. It is called during the
69 * system startup to create static physical to virtual
70 * memory map for the IO modules.
71 */
72void __init mx21_map_io(void)
73{
74 mxc_set_cpu_type(MXC_CPU_MX21);
75 mxc_arch_reset_init(MX21_IO_ADDRESS(MX21_WDOG_BASE_ADDR));
76
77 iotable_init(imx21_io_desc, ARRAY_SIZE(imx21_io_desc));
78}
79
80void __init mx21_init_irq(void)
81{
82 mxc_init_irq(MX21_IO_ADDRESS(MX21_AVIC_BASE_ADDR));
83}
diff --git a/arch/arm/mach-mx2/generic.c b/arch/arm/mach-mx2/mm-imx27.c
index ae8f759134d1..3366ed44cfd5 100644
--- a/arch/arm/mach-mx2/generic.c
+++ b/arch/arm/mach-mx2/mm-imx27.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * generic.c 2 * arch/arm/mach-mx2/mm-imx27.c
3 * 3 *
4 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) 4 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
5 * 5 *
@@ -26,7 +26,7 @@
26#include <asm/mach/map.h> 26#include <asm/mach/map.h>
27 27
28/* MX27 memory map definition */ 28/* MX27 memory map definition */
29static struct map_desc mxc_io_desc[] __initdata = { 29static struct map_desc imx27_io_desc[] __initdata = {
30 /* 30 /*
31 * this fixed mapping covers: 31 * this fixed mapping covers:
32 * - AIPI1 32 * - AIPI1
@@ -36,9 +36,9 @@ static struct map_desc mxc_io_desc[] __initdata = {
36 * - and some reserved space 36 * - and some reserved space
37 */ 37 */
38 { 38 {
39 .virtual = AIPI_BASE_ADDR_VIRT, 39 .virtual = MX27_AIPI_BASE_ADDR_VIRT,
40 .pfn = __phys_to_pfn(AIPI_BASE_ADDR), 40 .pfn = __phys_to_pfn(MX27_AIPI_BASE_ADDR),
41 .length = AIPI_SIZE, 41 .length = MX27_AIPI_SIZE,
42 .type = MT_DEVICE 42 .type = MT_DEVICE
43 }, 43 },
44 /* 44 /*
@@ -47,9 +47,9 @@ static struct map_desc mxc_io_desc[] __initdata = {
47 * - ATA 47 * - ATA
48 */ 48 */
49 { 49 {
50 .virtual = SAHB1_BASE_ADDR_VIRT, 50 .virtual = MX27_SAHB1_BASE_ADDR_VIRT,
51 .pfn = __phys_to_pfn(SAHB1_BASE_ADDR), 51 .pfn = __phys_to_pfn(MX27_SAHB1_BASE_ADDR),
52 .length = SAHB1_SIZE, 52 .length = MX27_SAHB1_SIZE,
53 .type = MT_DEVICE 53 .type = MT_DEVICE
54 }, 54 },
55 /* 55 /*
@@ -57,11 +57,11 @@ static struct map_desc mxc_io_desc[] __initdata = {
57 * - EMI 57 * - EMI
58 */ 58 */
59 { 59 {
60 .virtual = X_MEMC_BASE_ADDR_VIRT, 60 .virtual = MX27_X_MEMC_BASE_ADDR_VIRT,
61 .pfn = __phys_to_pfn(X_MEMC_BASE_ADDR), 61 .pfn = __phys_to_pfn(MX27_X_MEMC_BASE_ADDR),
62 .length = X_MEMC_SIZE, 62 .length = MX27_X_MEMC_SIZE,
63 .type = MT_DEVICE 63 .type = MT_DEVICE
64 } 64 },
65}; 65};
66 66
67/* 67/*
@@ -69,29 +69,15 @@ static struct map_desc mxc_io_desc[] __initdata = {
69 * system startup to create static physical to virtual 69 * system startup to create static physical to virtual
70 * memory map for the IO modules. 70 * memory map for the IO modules.
71 */ 71 */
72void __init mx21_map_io(void)
73{
74 mxc_set_cpu_type(MXC_CPU_MX21);
75 mxc_arch_reset_init(IO_ADDRESS(WDOG_BASE_ADDR));
76
77 iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
78}
79
80void __init mx27_map_io(void) 72void __init mx27_map_io(void)
81{ 73{
82 mxc_set_cpu_type(MXC_CPU_MX27); 74 mxc_set_cpu_type(MXC_CPU_MX27);
83 mxc_arch_reset_init(IO_ADDRESS(WDOG_BASE_ADDR)); 75 mxc_arch_reset_init(MX27_IO_ADDRESS(MX27_WDOG_BASE_ADDR));
84 76
85 iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); 77 iotable_init(imx27_io_desc, ARRAY_SIZE(imx27_io_desc));
86} 78}
87 79
88void __init mx27_init_irq(void) 80void __init mx27_init_irq(void)
89{ 81{
90 mxc_init_irq(IO_ADDRESS(AVIC_BASE_ADDR)); 82 mxc_init_irq(MX27_IO_ADDRESS(MX27_AVIC_BASE_ADDR));
91} 83}
92
93void __init mx21_init_irq(void)
94{
95 mx27_init_irq();
96}
97
diff --git a/arch/arm/mach-mx2/pcm970-baseboard.c b/arch/arm/mach-mx2/pcm970-baseboard.c
index 60d54465ada1..4aafd5b8b85b 100644
--- a/arch/arm/mach-mx2/pcm970-baseboard.c
+++ b/arch/arm/mach-mx2/pcm970-baseboard.c
@@ -24,7 +24,7 @@
24#include <asm/mach/arch.h> 24#include <asm/mach/arch.h>
25 25
26#include <mach/common.h> 26#include <mach/common.h>
27#include <mach/iomux.h> 27#include <mach/iomux-mx27.h>
28#include <mach/imxfb.h> 28#include <mach/imxfb.h>
29#include <mach/hardware.h> 29#include <mach/hardware.h>
30#include <mach/mmc.h> 30#include <mach/mmc.h>
diff --git a/arch/arm/mach-mx25/mach-mx25pdk.c b/arch/arm/mach-mx25/mach-mx25pdk.c
index 99b9463ca154..83d74109e7d8 100644
--- a/arch/arm/mach-mx25/mach-mx25pdk.c
+++ b/arch/arm/mach-mx25/mach-mx25pdk.c
@@ -37,7 +37,7 @@
37#include <mach/mxc_nand.h> 37#include <mach/mxc_nand.h>
38#include <mach/imxfb.h> 38#include <mach/imxfb.h>
39#include "devices.h" 39#include "devices.h"
40#include <mach/iomux.h> 40#include <mach/iomux-mx25.h>
41 41
42static struct imxuart_platform_data uart_pdata = { 42static struct imxuart_platform_data uart_pdata = {
43 .flags = IMXUART_HAVE_RTSCTS, 43 .flags = IMXUART_HAVE_RTSCTS,
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index 44f3a805ae56..7f7ad6f289bd 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -9,21 +9,20 @@ choice
9config ARCH_MX1 9config ARCH_MX1
10 bool "MX1-based" 10 bool "MX1-based"
11 select CPU_ARM920T 11 select CPU_ARM920T
12 select COMMON_CLKDEV 12 select IMX_HAVE_IOMUX_V1
13 help 13 help
14 This enables support for systems based on the Freescale i.MX1 family 14 This enables support for systems based on the Freescale i.MX1 family
15 15
16config ARCH_MX2 16config ARCH_MX2
17 bool "MX2-based" 17 bool "MX2-based"
18 select CPU_ARM926T 18 select CPU_ARM926T
19 select COMMON_CLKDEV 19 select IMX_HAVE_IOMUX_V1
20 help 20 help
21 This enables support for systems based on the Freescale i.MX2 family 21 This enables support for systems based on the Freescale i.MX2 family
22 22
23config ARCH_MX25 23config ARCH_MX25
24 bool "MX25-based" 24 bool "MX25-based"
25 select CPU_ARM926T 25 select CPU_ARM926T
26 select COMMON_CLKDEV
27 select ARCH_MXC_IOMUX_V3 26 select ARCH_MXC_IOMUX_V3
28 select HAVE_FB_IMX 27 select HAVE_FB_IMX
29 help 28 help
@@ -32,21 +31,18 @@ config ARCH_MX25
32config ARCH_MX3 31config ARCH_MX3
33 bool "MX3-based" 32 bool "MX3-based"
34 select CPU_V6 33 select CPU_V6
35 select COMMON_CLKDEV
36 help 34 help
37 This enables support for systems based on the Freescale i.MX3 family 35 This enables support for systems based on the Freescale i.MX3 family
38 36
39config ARCH_MXC91231 37config ARCH_MXC91231
40 bool "MXC91231-based" 38 bool "MXC91231-based"
41 select CPU_V6 39 select CPU_V6
42 select COMMON_CLKDEV
43 help 40 help
44 This enables support for systems based on the Freescale MXC91231 family 41 This enables support for systems based on the Freescale MXC91231 family
45 42
46config ARCH_MX5 43config ARCH_MX5
47 bool "MX5-based" 44 bool "MX5-based"
48 select CPU_V7 45 select CPU_V7
49 select COMMON_CLKDEV
50 help 46 help
51 This enables support for systems based on the Freescale i.MX51 family 47 This enables support for systems based on the Freescale i.MX51 family
52 48
@@ -63,7 +59,6 @@ endmenu
63 59
64config MXC_IRQ_PRIOR 60config MXC_IRQ_PRIOR
65 bool "Use IRQ priority" 61 bool "Use IRQ priority"
66 depends on ARCH_MXC
67 help 62 help
68 Select this if you want to use prioritized IRQ handling. 63 Select this if you want to use prioritized IRQ handling.
69 This feature prevents higher priority ISR to be interrupted 64 This feature prevents higher priority ISR to be interrupted
@@ -82,7 +77,6 @@ config MXC_TZIC
82 77
83config MXC_PWM 78config MXC_PWM
84 tristate "Enable PWM driver" 79 tristate "Enable PWM driver"
85 depends on ARCH_MXC
86 select HAVE_PWM 80 select HAVE_PWM
87 help 81 help
88 Enable support for the i.MX PWM controller(s). 82 Enable support for the i.MX PWM controller(s).
@@ -92,7 +86,9 @@ config MXC_ULPI
92 86
93config ARCH_HAS_RNGA 87config ARCH_HAS_RNGA
94 bool 88 bool
95 depends on ARCH_MXC 89
90config IMX_HAVE_IOMUX_V1
91 bool
96 92
97config ARCH_MXC_IOMUX_V3 93config ARCH_MXC_IOMUX_V3
98 bool 94 bool
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index a4bc6cb26aa4..a72a5e4ca20e 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -8,15 +8,12 @@ obj-y := irq.o clock.o gpio.o time.o devices.o cpu.o system.o
8# MX51 uses the TZIC interrupt controller, older platforms use AVIC (irq.o) 8# MX51 uses the TZIC interrupt controller, older platforms use AVIC (irq.o)
9obj-$(CONFIG_MXC_TZIC) += tzic.o 9obj-$(CONFIG_MXC_TZIC) += tzic.o
10 10
11obj-$(CONFIG_ARCH_MX1) += iomux-mx1-mx2.o dma-mx1-mx2.o 11obj-$(CONFIG_ARCH_MX1) += dma-mx1-mx2.o
12obj-$(CONFIG_ARCH_MX2) += iomux-mx1-mx2.o dma-mx1-mx2.o 12obj-$(CONFIG_ARCH_MX2) += dma-mx1-mx2.o
13CFLAGS_iomux-mx1-mx2.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS 13obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o
14CFLAGS_dma-mx1-mx2.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS
15obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o 14obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
16obj-$(CONFIG_MXC_PWM) += pwm.o 15obj-$(CONFIG_MXC_PWM) += pwm.o
17obj-$(CONFIG_USB_EHCI_MXC) += ehci.o 16obj-$(CONFIG_USB_EHCI_MXC) += ehci.o
18obj-$(CONFIG_MXC_ULPI) += ulpi.o 17obj-$(CONFIG_MXC_ULPI) += ulpi.o
19obj-$(CONFIG_ARCH_MXC_AUDMUX_V1) += audmux-v1.o 18obj-$(CONFIG_ARCH_MXC_AUDMUX_V1) += audmux-v1.o
20CFLAGS_audmux-v1.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS
21obj-$(CONFIG_ARCH_MXC_AUDMUX_V2) += audmux-v2.o 19obj-$(CONFIG_ARCH_MXC_AUDMUX_V2) += audmux-v2.o
22CFLAGS_audmux-v2.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS
diff --git a/arch/arm/plat-mxc/audmux-v1.c b/arch/arm/plat-mxc/audmux-v1.c
index da6387dcdf21..b62917ca3f95 100644
--- a/arch/arm/plat-mxc/audmux-v1.c
+++ b/arch/arm/plat-mxc/audmux-v1.c
@@ -50,8 +50,18 @@ EXPORT_SYMBOL_GPL(mxc_audmux_v1_configure_port);
50 50
51static int mxc_audmux_v1_init(void) 51static int mxc_audmux_v1_init(void)
52{ 52{
53 if (cpu_is_mx27() || cpu_is_mx21()) 53#ifdef CONFIG_MACH_MX21
54 audmux_base = IO_ADDRESS(AUDMUX_BASE_ADDR); 54 if (cpu_is_mx21())
55 audmux_base = MX21_IO_ADDRESS(MX21_AUDMUX_BASE_ADDR);
56 else
57#endif
58#ifdef CONFIG_MACH_MX27
59 if (cpu_is_mx27())
60 audmux_base = MX27_IO_ADDRESS(MX27_AUDMUX_BASE_ADDR);
61 else
62#endif
63 (void)0;
64
55 return 0; 65 return 0;
56} 66}
57 67
diff --git a/arch/arm/plat-mxc/audmux-v2.c b/arch/arm/plat-mxc/audmux-v2.c
index b06954a84436..d983cd6c788c 100644
--- a/arch/arm/plat-mxc/audmux-v2.c
+++ b/arch/arm/plat-mxc/audmux-v2.c
@@ -190,7 +190,10 @@ static int mxc_audmux_v2_init(void)
190{ 190{
191 int ret; 191 int ret;
192 192
193 if (cpu_is_mx35()) { 193 if (cpu_is_mx31())
194 audmux_base = MX31_IO_ADDRESS(MX31_AUDMUX_BASE_ADDR);
195
196 else if (cpu_is_mx35()) {
194 audmux_clk = clk_get(NULL, "audmux"); 197 audmux_clk = clk_get(NULL, "audmux");
195 if (IS_ERR(audmux_clk)) { 198 if (IS_ERR(audmux_clk)) {
196 ret = PTR_ERR(audmux_clk); 199 ret = PTR_ERR(audmux_clk);
@@ -198,11 +201,9 @@ static int mxc_audmux_v2_init(void)
198 ret); 201 ret);
199 return ret; 202 return ret;
200 } 203 }
204 audmux_base = MX35_IO_ADDRESS(MX35_AUDMUX_BASE_ADDR);
201 } 205 }
202 206
203 if (cpu_is_mx31() || cpu_is_mx35())
204 audmux_base = IO_ADDRESS(AUDMUX_BASE_ADDR);
205
206 audmux_debugfs_init(); 207 audmux_debugfs_init();
207 208
208 return 0; 209 return 0;
diff --git a/arch/arm/plat-mxc/dma-mx1-mx2.c b/arch/arm/plat-mxc/dma-mx1-mx2.c
index 9c1b3f9c4f4d..e16014b0d13c 100644
--- a/arch/arm/plat-mxc/dma-mx1-mx2.c
+++ b/arch/arm/plat-mxc/dma-mx1-mx2.c
@@ -128,6 +128,18 @@ struct imx_dma_channel {
128 int hw_chaining; 128 int hw_chaining;
129}; 129};
130 130
131static void __iomem *imx_dmav1_baseaddr;
132
133static void imx_dmav1_writel(unsigned val, unsigned offset)
134{
135 __raw_writel(val, imx_dmav1_baseaddr + offset);
136}
137
138static unsigned imx_dmav1_readl(unsigned offset)
139{
140 return __raw_readl(imx_dmav1_baseaddr + offset);
141}
142
131static struct imx_dma_channel imx_dma_channels[IMX_DMA_CHANNELS]; 143static struct imx_dma_channel imx_dma_channels[IMX_DMA_CHANNELS];
132 144
133static struct clk *dma_clk; 145static struct clk *dma_clk;
@@ -140,7 +152,6 @@ static int imx_dma_hw_chain(struct imx_dma_channel *imxdma)
140 return 0; 152 return 0;
141} 153}
142 154
143
144/* 155/*
145 * imx_dma_sg_next - prepare next chunk for scatter-gather DMA emulation 156 * imx_dma_sg_next - prepare next chunk for scatter-gather DMA emulation
146 */ 157 */
@@ -160,17 +171,17 @@ static inline int imx_dma_sg_next(int channel, struct scatterlist *sg)
160 imxdma->resbytes -= now; 171 imxdma->resbytes -= now;
161 172
162 if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ) 173 if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ)
163 __raw_writel(sg->dma_address, DMA_BASE + DMA_DAR(channel)); 174 imx_dmav1_writel(sg->dma_address, DMA_DAR(channel));
164 else 175 else
165 __raw_writel(sg->dma_address, DMA_BASE + DMA_SAR(channel)); 176 imx_dmav1_writel(sg->dma_address, DMA_SAR(channel));
166 177
167 __raw_writel(now, DMA_BASE + DMA_CNTR(channel)); 178 imx_dmav1_writel(now, DMA_CNTR(channel));
168 179
169 pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, " 180 pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, "
170 "size 0x%08x\n", channel, 181 "size 0x%08x\n", channel,
171 __raw_readl(DMA_BASE + DMA_DAR(channel)), 182 imx_dmav1_readl(DMA_DAR(channel)),
172 __raw_readl(DMA_BASE + DMA_SAR(channel)), 183 imx_dmav1_readl(DMA_SAR(channel)),
173 __raw_readl(DMA_BASE + DMA_CNTR(channel))); 184 imx_dmav1_readl(DMA_CNTR(channel)));
174 185
175 return now; 186 return now;
176} 187}
@@ -218,27 +229,26 @@ imx_dma_setup_single(int channel, dma_addr_t dma_address,
218 channel, __func__, (unsigned int)dma_address, 229 channel, __func__, (unsigned int)dma_address,
219 dma_length, dev_addr); 230 dma_length, dev_addr);
220 231
221 __raw_writel(dev_addr, DMA_BASE + DMA_SAR(channel)); 232 imx_dmav1_writel(dev_addr, DMA_SAR(channel));
222 __raw_writel(dma_address, DMA_BASE + DMA_DAR(channel)); 233 imx_dmav1_writel(dma_address, DMA_DAR(channel));
223 __raw_writel(imxdma->ccr_from_device, 234 imx_dmav1_writel(imxdma->ccr_from_device, DMA_CCR(channel));
224 DMA_BASE + DMA_CCR(channel));
225 } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) { 235 } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
226 pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d " 236 pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
227 "dev_addr=0x%08x for write\n", 237 "dev_addr=0x%08x for write\n",
228 channel, __func__, (unsigned int)dma_address, 238 channel, __func__, (unsigned int)dma_address,
229 dma_length, dev_addr); 239 dma_length, dev_addr);
230 240
231 __raw_writel(dma_address, DMA_BASE + DMA_SAR(channel)); 241 imx_dmav1_writel(dma_address, DMA_SAR(channel));
232 __raw_writel(dev_addr, DMA_BASE + DMA_DAR(channel)); 242 imx_dmav1_writel(dev_addr, DMA_DAR(channel));
233 __raw_writel(imxdma->ccr_to_device, 243 imx_dmav1_writel(imxdma->ccr_to_device,
234 DMA_BASE + DMA_CCR(channel)); 244 DMA_CCR(channel));
235 } else { 245 } else {
236 printk(KERN_ERR "imxdma%d: imx_dma_setup_single bad dmamode\n", 246 printk(KERN_ERR "imxdma%d: imx_dma_setup_single bad dmamode\n",
237 channel); 247 channel);
238 return -EINVAL; 248 return -EINVAL;
239 } 249 }
240 250
241 __raw_writel(dma_length, DMA_BASE + DMA_CNTR(channel)); 251 imx_dmav1_writel(dma_length, DMA_CNTR(channel));
242 252
243 return 0; 253 return 0;
244} 254}
@@ -316,17 +326,15 @@ imx_dma_setup_sg(int channel,
316 "dev_addr=0x%08x for read\n", 326 "dev_addr=0x%08x for read\n",
317 channel, __func__, sg, sgcount, dma_length, dev_addr); 327 channel, __func__, sg, sgcount, dma_length, dev_addr);
318 328
319 __raw_writel(dev_addr, DMA_BASE + DMA_SAR(channel)); 329 imx_dmav1_writel(dev_addr, DMA_SAR(channel));
320 __raw_writel(imxdma->ccr_from_device, 330 imx_dmav1_writel(imxdma->ccr_from_device, DMA_CCR(channel));
321 DMA_BASE + DMA_CCR(channel));
322 } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) { 331 } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
323 pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d " 332 pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
324 "dev_addr=0x%08x for write\n", 333 "dev_addr=0x%08x for write\n",
325 channel, __func__, sg, sgcount, dma_length, dev_addr); 334 channel, __func__, sg, sgcount, dma_length, dev_addr);
326 335
327 __raw_writel(dev_addr, DMA_BASE + DMA_DAR(channel)); 336 imx_dmav1_writel(dev_addr, DMA_DAR(channel));
328 __raw_writel(imxdma->ccr_to_device, 337 imx_dmav1_writel(imxdma->ccr_to_device, DMA_CCR(channel));
329 DMA_BASE + DMA_CCR(channel));
330 } else { 338 } else {
331 printk(KERN_ERR "imxdma%d: imx_dma_setup_sg bad dmamode\n", 339 printk(KERN_ERR "imxdma%d: imx_dma_setup_sg bad dmamode\n",
332 channel); 340 channel);
@@ -360,7 +368,7 @@ imx_dma_config_channel(int channel, unsigned int config_port,
360 imxdma->ccr_from_device = config_port | (config_mem << 2) | dreq; 368 imxdma->ccr_from_device = config_port | (config_mem << 2) | dreq;
361 imxdma->ccr_to_device = config_mem | (config_port << 2) | dreq; 369 imxdma->ccr_to_device = config_mem | (config_port << 2) | dreq;
362 370
363 __raw_writel(dmareq, DMA_BASE + DMA_RSSR(channel)); 371 imx_dmav1_writel(dmareq, DMA_RSSR(channel));
364 372
365 return 0; 373 return 0;
366} 374}
@@ -368,7 +376,7 @@ EXPORT_SYMBOL(imx_dma_config_channel);
368 376
369void imx_dma_config_burstlen(int channel, unsigned int burstlen) 377void imx_dma_config_burstlen(int channel, unsigned int burstlen)
370{ 378{
371 __raw_writel(burstlen, DMA_BASE + DMA_BLR(channel)); 379 imx_dmav1_writel(burstlen, DMA_BLR(channel));
372} 380}
373EXPORT_SYMBOL(imx_dma_config_burstlen); 381EXPORT_SYMBOL(imx_dma_config_burstlen);
374 382
@@ -398,7 +406,7 @@ imx_dma_setup_handlers(int channel,
398 } 406 }
399 407
400 local_irq_save(flags); 408 local_irq_save(flags);
401 __raw_writel(1 << channel, DMA_BASE + DMA_DISR); 409 imx_dmav1_writel(1 << channel, DMA_DISR);
402 imxdma->irq_handler = irq_handler; 410 imxdma->irq_handler = irq_handler;
403 imxdma->err_handler = err_handler; 411 imxdma->err_handler = err_handler;
404 imxdma->data = data; 412 imxdma->data = data;
@@ -462,22 +470,21 @@ void imx_dma_enable(int channel)
462 470
463 local_irq_save(flags); 471 local_irq_save(flags);
464 472
465 __raw_writel(1 << channel, DMA_BASE + DMA_DISR); 473 imx_dmav1_writel(1 << channel, DMA_DISR);
466 __raw_writel(__raw_readl(DMA_BASE + DMA_DIMR) & ~(1 << channel), 474 imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) & ~(1 << channel), DMA_DIMR);
467 DMA_BASE + DMA_DIMR); 475 imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) | CCR_CEN |
468 __raw_writel(__raw_readl(DMA_BASE + DMA_CCR(channel)) | CCR_CEN | 476 CCR_ACRPT, DMA_CCR(channel));
469 CCR_ACRPT,
470 DMA_BASE + DMA_CCR(channel));
471 477
472#ifdef CONFIG_ARCH_MX2 478#ifdef CONFIG_ARCH_MX2
473 if (imxdma->sg && imx_dma_hw_chain(imxdma)) { 479 if ((cpu_is_mx21() || cpu_is_mx27()) &&
480 imxdma->sg && imx_dma_hw_chain(imxdma)) {
474 imxdma->sg = sg_next(imxdma->sg); 481 imxdma->sg = sg_next(imxdma->sg);
475 if (imxdma->sg) { 482 if (imxdma->sg) {
476 u32 tmp; 483 u32 tmp;
477 imx_dma_sg_next(channel, imxdma->sg); 484 imx_dma_sg_next(channel, imxdma->sg);
478 tmp = __raw_readl(DMA_BASE + DMA_CCR(channel)); 485 tmp = imx_dmav1_readl(DMA_CCR(channel));
479 __raw_writel(tmp | CCR_RPT | CCR_ACRPT, 486 imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT,
480 DMA_BASE + DMA_CCR(channel)); 487 DMA_CCR(channel));
481 } 488 }
482 } 489 }
483#endif 490#endif
@@ -502,11 +509,10 @@ void imx_dma_disable(int channel)
502 del_timer(&imxdma->watchdog); 509 del_timer(&imxdma->watchdog);
503 510
504 local_irq_save(flags); 511 local_irq_save(flags);
505 __raw_writel(__raw_readl(DMA_BASE + DMA_DIMR) | (1 << channel), 512 imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) | (1 << channel), DMA_DIMR);
506 DMA_BASE + DMA_DIMR); 513 imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) & ~CCR_CEN,
507 __raw_writel(__raw_readl(DMA_BASE + DMA_CCR(channel)) & ~CCR_CEN, 514 DMA_CCR(channel));
508 DMA_BASE + DMA_CCR(channel)); 515 imx_dmav1_writel(1 << channel, DMA_DISR);
509 __raw_writel(1 << channel, DMA_BASE + DMA_DISR);
510 imxdma->in_use = 0; 516 imxdma->in_use = 0;
511 local_irq_restore(flags); 517 local_irq_restore(flags);
512} 518}
@@ -517,7 +523,7 @@ static void imx_dma_watchdog(unsigned long chno)
517{ 523{
518 struct imx_dma_channel *imxdma = &imx_dma_channels[chno]; 524 struct imx_dma_channel *imxdma = &imx_dma_channels[chno];
519 525
520 __raw_writel(0, DMA_BASE + DMA_CCR(chno)); 526 imx_dmav1_writel(0, DMA_CCR(chno));
521 imxdma->in_use = 0; 527 imxdma->in_use = 0;
522 imxdma->sg = NULL; 528 imxdma->sg = NULL;
523 529
@@ -533,17 +539,17 @@ static irqreturn_t dma_err_handler(int irq, void *dev_id)
533 unsigned int err_mask; 539 unsigned int err_mask;
534 int errcode; 540 int errcode;
535 541
536 disr = __raw_readl(DMA_BASE + DMA_DISR); 542 disr = imx_dmav1_readl(DMA_DISR);
537 543
538 err_mask = __raw_readl(DMA_BASE + DMA_DBTOSR) | 544 err_mask = imx_dmav1_readl(DMA_DBTOSR) |
539 __raw_readl(DMA_BASE + DMA_DRTOSR) | 545 imx_dmav1_readl(DMA_DRTOSR) |
540 __raw_readl(DMA_BASE + DMA_DSESR) | 546 imx_dmav1_readl(DMA_DSESR) |
541 __raw_readl(DMA_BASE + DMA_DBOSR); 547 imx_dmav1_readl(DMA_DBOSR);
542 548
543 if (!err_mask) 549 if (!err_mask)
544 return IRQ_HANDLED; 550 return IRQ_HANDLED;
545 551
546 __raw_writel(disr & err_mask, DMA_BASE + DMA_DISR); 552 imx_dmav1_writel(disr & err_mask, DMA_DISR);
547 553
548 for (i = 0; i < IMX_DMA_CHANNELS; i++) { 554 for (i = 0; i < IMX_DMA_CHANNELS; i++) {
549 if (!(err_mask & (1 << i))) 555 if (!(err_mask & (1 << i)))
@@ -551,20 +557,20 @@ static irqreturn_t dma_err_handler(int irq, void *dev_id)
551 imxdma = &imx_dma_channels[i]; 557 imxdma = &imx_dma_channels[i];
552 errcode = 0; 558 errcode = 0;
553 559
554 if (__raw_readl(DMA_BASE + DMA_DBTOSR) & (1 << i)) { 560 if (imx_dmav1_readl(DMA_DBTOSR) & (1 << i)) {
555 __raw_writel(1 << i, DMA_BASE + DMA_DBTOSR); 561 imx_dmav1_writel(1 << i, DMA_DBTOSR);
556 errcode |= IMX_DMA_ERR_BURST; 562 errcode |= IMX_DMA_ERR_BURST;
557 } 563 }
558 if (__raw_readl(DMA_BASE + DMA_DRTOSR) & (1 << i)) { 564 if (imx_dmav1_readl(DMA_DRTOSR) & (1 << i)) {
559 __raw_writel(1 << i, DMA_BASE + DMA_DRTOSR); 565 imx_dmav1_writel(1 << i, DMA_DRTOSR);
560 errcode |= IMX_DMA_ERR_REQUEST; 566 errcode |= IMX_DMA_ERR_REQUEST;
561 } 567 }
562 if (__raw_readl(DMA_BASE + DMA_DSESR) & (1 << i)) { 568 if (imx_dmav1_readl(DMA_DSESR) & (1 << i)) {
563 __raw_writel(1 << i, DMA_BASE + DMA_DSESR); 569 imx_dmav1_writel(1 << i, DMA_DSESR);
564 errcode |= IMX_DMA_ERR_TRANSFER; 570 errcode |= IMX_DMA_ERR_TRANSFER;
565 } 571 }
566 if (__raw_readl(DMA_BASE + DMA_DBOSR) & (1 << i)) { 572 if (imx_dmav1_readl(DMA_DBOSR) & (1 << i)) {
567 __raw_writel(1 << i, DMA_BASE + DMA_DBOSR); 573 imx_dmav1_writel(1 << i, DMA_DBOSR);
568 errcode |= IMX_DMA_ERR_BUFFER; 574 errcode |= IMX_DMA_ERR_BUFFER;
569 } 575 }
570 if (imxdma->name && imxdma->err_handler) { 576 if (imxdma->name && imxdma->err_handler) {
@@ -607,7 +613,7 @@ static void dma_irq_handle_channel(int chno)
607 if (imxdma->sg) { 613 if (imxdma->sg) {
608 imx_dma_sg_next(chno, imxdma->sg); 614 imx_dma_sg_next(chno, imxdma->sg);
609 615
610 tmp = __raw_readl(DMA_BASE + DMA_CCR(chno)); 616 tmp = imx_dmav1_readl(DMA_CCR(chno));
611 617
612 if (imx_dma_hw_chain(imxdma)) { 618 if (imx_dma_hw_chain(imxdma)) {
613 /* FIXME: The timeout should probably be 619 /* FIXME: The timeout should probably be
@@ -617,15 +623,13 @@ static void dma_irq_handle_channel(int chno)
617 jiffies + msecs_to_jiffies(500)); 623 jiffies + msecs_to_jiffies(500));
618 624
619 tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT; 625 tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
620 __raw_writel(tmp, DMA_BASE + 626 imx_dmav1_writel(tmp, DMA_CCR(chno));
621 DMA_CCR(chno));
622 } else { 627 } else {
623 __raw_writel(tmp & ~CCR_CEN, DMA_BASE + 628 imx_dmav1_writel(tmp & ~CCR_CEN, DMA_CCR(chno));
624 DMA_CCR(chno));
625 tmp |= CCR_CEN; 629 tmp |= CCR_CEN;
626 } 630 }
627 631
628 __raw_writel(tmp, DMA_BASE + DMA_CCR(chno)); 632 imx_dmav1_writel(tmp, DMA_CCR(chno));
629 633
630 if (imxdma->prog_handler) 634 if (imxdma->prog_handler)
631 imxdma->prog_handler(chno, imxdma->data, 635 imxdma->prog_handler(chno, imxdma->data,
@@ -640,7 +644,7 @@ static void dma_irq_handle_channel(int chno)
640 } 644 }
641 } 645 }
642 646
643 __raw_writel(0, DMA_BASE + DMA_CCR(chno)); 647 imx_dmav1_writel(0, DMA_CCR(chno));
644 imxdma->in_use = 0; 648 imxdma->in_use = 0;
645 if (imxdma->irq_handler) 649 if (imxdma->irq_handler)
646 imxdma->irq_handler(chno, imxdma->data); 650 imxdma->irq_handler(chno, imxdma->data);
@@ -651,15 +655,16 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id)
651 int i, disr; 655 int i, disr;
652 656
653#ifdef CONFIG_ARCH_MX2 657#ifdef CONFIG_ARCH_MX2
654 dma_err_handler(irq, dev_id); 658 if (cpu_is_mx21() || cpu_is_mx27())
659 dma_err_handler(irq, dev_id);
655#endif 660#endif
656 661
657 disr = __raw_readl(DMA_BASE + DMA_DISR); 662 disr = imx_dmav1_readl(DMA_DISR);
658 663
659 pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n", 664 pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n",
660 disr); 665 disr);
661 666
662 __raw_writel(disr, DMA_BASE + DMA_DISR); 667 imx_dmav1_writel(disr, DMA_DISR);
663 for (i = 0; i < IMX_DMA_CHANNELS; i++) { 668 for (i = 0; i < IMX_DMA_CHANNELS; i++) {
664 if (disr & (1 << i)) 669 if (disr & (1 << i))
665 dma_irq_handle_channel(i); 670 dma_irq_handle_channel(i);
@@ -699,17 +704,19 @@ int imx_dma_request(int channel, const char *name)
699 local_irq_restore(flags); /* request_irq() can block */ 704 local_irq_restore(flags); /* request_irq() can block */
700 705
701#ifdef CONFIG_ARCH_MX2 706#ifdef CONFIG_ARCH_MX2
702 ret = request_irq(MXC_INT_DMACH0 + channel, dma_irq_handler, 0, "DMA", 707 if (cpu_is_mx21() || cpu_is_mx27()) {
703 NULL); 708 ret = request_irq(MX2x_INT_DMACH0 + channel,
704 if (ret) { 709 dma_irq_handler, 0, "DMA", NULL);
705 imxdma->name = NULL; 710 if (ret) {
706 printk(KERN_CRIT "Can't register IRQ %d for DMA channel %d\n", 711 imxdma->name = NULL;
707 MXC_INT_DMACH0 + channel, channel); 712 pr_crit("Can't register IRQ %d for DMA channel %d\n",
708 return ret; 713 MX2x_INT_DMACH0 + channel, channel);
714 return ret;
715 }
716 init_timer(&imxdma->watchdog);
717 imxdma->watchdog.function = &imx_dma_watchdog;
718 imxdma->watchdog.data = channel;
709 } 719 }
710 init_timer(&imxdma->watchdog);
711 imxdma->watchdog.function = &imx_dma_watchdog;
712 imxdma->watchdog.data = channel;
713#endif 720#endif
714 721
715 return ret; 722 return ret;
@@ -738,7 +745,8 @@ void imx_dma_free(int channel)
738 imxdma->name = NULL; 745 imxdma->name = NULL;
739 746
740#ifdef CONFIG_ARCH_MX2 747#ifdef CONFIG_ARCH_MX2
741 free_irq(MXC_INT_DMACH0 + channel, NULL); 748 if (cpu_is_mx21() || cpu_is_mx27())
749 free_irq(MX2x_INT_DMACH0 + channel, NULL);
742#endif 750#endif
743 751
744 local_irq_restore(flags); 752 local_irq_restore(flags);
@@ -796,34 +804,53 @@ static int __init imx_dma_init(void)
796 int ret = 0; 804 int ret = 0;
797 int i; 805 int i;
798 806
807#ifdef CONFIG_ARCH_MX1
808 if (cpu_is_mx1())
809 imx_dmav1_baseaddr = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR);
810 else
811#endif
812#ifdef CONFIG_MACH_MX21
813 if (cpu_is_mx21())
814 imx_dmav1_baseaddr = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR);
815 else
816#endif
817#ifdef CONFIG_MACH_MX27
818 if (cpu_is_mx27())
819 imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR);
820 else
821#endif
822 BUG();
823
799 dma_clk = clk_get(NULL, "dma"); 824 dma_clk = clk_get(NULL, "dma");
800 clk_enable(dma_clk); 825 clk_enable(dma_clk);
801 826
802 /* reset DMA module */ 827 /* reset DMA module */
803 __raw_writel(DCR_DRST, DMA_BASE + DMA_DCR); 828 imx_dmav1_writel(DCR_DRST, DMA_DCR);
804 829
805#ifdef CONFIG_ARCH_MX1 830#ifdef CONFIG_ARCH_MX1
806 ret = request_irq(DMA_INT, dma_irq_handler, 0, "DMA", NULL); 831 if (cpu_is_mx1()) {
807 if (ret) { 832 ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", NULL);
808 printk(KERN_CRIT "Wow! Can't register IRQ for DMA\n"); 833 if (ret) {
809 return ret; 834 pr_crit("Wow! Can't register IRQ for DMA\n");
810 } 835 return ret;
836 }
811 837
812 ret = request_irq(DMA_ERR, dma_err_handler, 0, "DMA", NULL); 838 ret = request_irq(MX1_DMA_ERR, dma_err_handler, 0, "DMA", NULL);
813 if (ret) { 839 if (ret) {
814 printk(KERN_CRIT "Wow! Can't register ERRIRQ for DMA\n"); 840 pr_crit("Wow! Can't register ERRIRQ for DMA\n");
815 free_irq(DMA_INT, NULL); 841 free_irq(MX1_DMA_INT, NULL);
816 return ret; 842 return ret;
843 }
817 } 844 }
818#endif 845#endif
819 /* enable DMA module */ 846 /* enable DMA module */
820 __raw_writel(DCR_DEN, DMA_BASE + DMA_DCR); 847 imx_dmav1_writel(DCR_DEN, DMA_DCR);
821 848
822 /* clear all interrupts */ 849 /* clear all interrupts */
823 __raw_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_BASE + DMA_DISR); 850 imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
824 851
825 /* disable interrupts */ 852 /* disable interrupts */
826 __raw_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_BASE + DMA_DIMR); 853 imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
827 854
828 for (i = 0; i < IMX_DMA_CHANNELS; i++) { 855 for (i = 0; i < IMX_DMA_CHANNELS; i++) {
829 imx_dma_channels[i].sg = NULL; 856 imx_dma_channels[i].sg = NULL;
diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c
index d65ebe303b9f..70b23893f094 100644
--- a/arch/arm/plat-mxc/gpio.c
+++ b/arch/arm/plat-mxc/gpio.c
@@ -140,16 +140,13 @@ static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
140 val = __raw_readl(reg); 140 val = __raw_readl(reg);
141 edge = (val >> (bit << 1)) & 3; 141 edge = (val >> (bit << 1)) & 3;
142 val &= ~(0x3 << (bit << 1)); 142 val &= ~(0x3 << (bit << 1));
143 switch (edge) { 143 if (edge == GPIO_INT_HIGH_LEV) {
144 case GPIO_INT_HIGH_LEV:
145 edge = GPIO_INT_LOW_LEV; 144 edge = GPIO_INT_LOW_LEV;
146 pr_debug("mxc: switch GPIO %d to low trigger\n", gpio); 145 pr_debug("mxc: switch GPIO %d to low trigger\n", gpio);
147 break; 146 } else if (edge == GPIO_INT_LOW_LEV) {
148 case GPIO_INT_LOW_LEV:
149 edge = GPIO_INT_HIGH_LEV; 147 edge = GPIO_INT_HIGH_LEV;
150 pr_debug("mxc: switch GPIO %d to high trigger\n", gpio); 148 pr_debug("mxc: switch GPIO %d to high trigger\n", gpio);
151 break; 149 } else {
152 default:
153 pr_err("mxc: invalid configuration for GPIO %d: %x\n", 150 pr_err("mxc: invalid configuration for GPIO %d: %x\n",
154 gpio, edge); 151 gpio, edge);
155 return; 152 return;
@@ -157,25 +154,20 @@ static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
157 __raw_writel(val | (edge << (bit << 1)), reg); 154 __raw_writel(val | (edge << (bit << 1)), reg);
158} 155}
159 156
160/* handle n interrupts in one status register */ 157/* handle 32 interrupts in one status register */
161static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat) 158static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
162{ 159{
163 u32 gpio_irq_no; 160 u32 gpio_irq_no_base = port->virtual_irq_start;
164 161
165 gpio_irq_no = port->virtual_irq_start; 162 while (irq_stat != 0) {
166 for (; irq_stat != 0; irq_stat >>= 1, gpio_irq_no++) { 163 int irqoffset = fls(irq_stat) - 1;
167 u32 gpio = irq_to_gpio(gpio_irq_no);
168
169 if ((irq_stat & 1) == 0)
170 continue;
171 164
172 BUG_ON(!(irq_desc[gpio_irq_no].handle_irq)); 165 if (port->both_edges & (1 << irqoffset))
166 mxc_flip_edge(port, irqoffset);
173 167
174 if (port->both_edges & (1 << (gpio & 31))) 168 generic_handle_irq(gpio_irq_no_base + irqoffset);
175 mxc_flip_edge(port, gpio);
176 169
177 irq_desc[gpio_irq_no].handle_irq(gpio_irq_no, 170 irq_stat &= ~(1 << irqoffset);
178 &irq_desc[gpio_irq_no]);
179 } 171 }
180} 172}
181 173
diff --git a/arch/arm/plat-mxc/include/mach/clock.h b/arch/arm/plat-mxc/include/mach/clock.h
index 43a82d0c534d..753a5988d85c 100644
--- a/arch/arm/plat-mxc/include/mach/clock.h
+++ b/arch/arm/plat-mxc/include/mach/clock.h
@@ -26,13 +26,6 @@
26struct module; 26struct module;
27 27
28struct clk { 28struct clk {
29#ifndef CONFIG_COMMON_CLKDEV
30 /* As soon as i.MX1 and i.MX31 switched to clkdev, this
31 * block can go away */
32 struct list_head node;
33 struct module *owner;
34 const char *name;
35#endif
36 int id; 29 int id;
37 /* Source clock this clk depends on */ 30 /* Source clock this clk depends on */
38 struct clk *parent; 31 struct clk *parent;
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx1.h b/arch/arm/plat-mxc/include/mach/iomux-mx1.h
index bf23305c19cc..6b1507cf378e 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx1.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx1.h
@@ -1,166 +1,155 @@
1/* 1/*
2* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> 2 * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
3* 3 *
4* This program is free software; you can redistribute it and/or 4 * This program is free software; you can redistribute it and/or
5* modify it under the terms of the GNU General Public License 5 * modify it under the terms of the GNU General Public License
6* as published by the Free Software Foundation; either version 2 6 * as published by the Free Software Foundation; either version 2
7* of the License, or (at your option) any later version. 7 * of the License, or (at your option) any later version.
8* This program is distributed in the hope that it will be useful, 8 * This program is distributed in the hope that it will be useful,
9* but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11* GNU General Public License for more details. 11 * GNU General Public License for more details.
12* 12 *
13* You should have received a copy of the GNU General Public License 13 * You should have received a copy of the GNU General Public License
14* along with this program; if not, write to the Free Software 14 * along with this program; if not, write to the Free Software
15* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
16* MA 02110-1301, USA. 16 * MA 02110-1301, USA.
17*/ 17 */
18#ifndef __MACH_IOMUX_MX1_H__
19#define __MACH_IOMUX_MX1_H__
18 20
19#ifndef _MXC_IOMUX_MX1_H 21#include <mach/iomux-v1.h>
20#define _MXC_IOMUX_MX1_H
21 22
22#ifndef GPIO_PORTA 23#define PA0_AIN_SPI2_CLK (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 0)
23#error Please include mach/iomux.h 24#define PA0_AF_ETMTRACESYNC (GPIO_PORTA | GPIO_AF | 0)
24#endif 25#define PA1_AOUT_SPI2_RXD (GPIO_PORTA | GPIO_AOUT | GPIO_IN | 1)
26#define PA1_PF_TIN (GPIO_PORTA | GPIO_PF | 1)
27#define PA2_PF_PWM0 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 2)
28#define PA3_PF_CSI_MCLK (GPIO_PORTA | GPIO_PF | 3)
29#define PA4_PF_CSI_D0 (GPIO_PORTA | GPIO_PF | 4)
30#define PA5_PF_CSI_D1 (GPIO_PORTA | GPIO_PF | 5)
31#define PA6_PF_CSI_D2 (GPIO_PORTA | GPIO_PF | 6)
32#define PA7_PF_CSI_D3 (GPIO_PORTA | GPIO_PF | 7)
33#define PA8_PF_CSI_D4 (GPIO_PORTA | GPIO_PF | 8)
34#define PA9_PF_CSI_D5 (GPIO_PORTA | GPIO_PF | 9)
35#define PA10_PF_CSI_D6 (GPIO_PORTA | GPIO_PF | 10)
36#define PA11_PF_CSI_D7 (GPIO_PORTA | GPIO_PF | 11)
37#define PA12_PF_CSI_VSYNC (GPIO_PORTA | GPIO_PF | 12)
38#define PA13_PF_CSI_HSYNC (GPIO_PORTA | GPIO_PF | 13)
39#define PA14_PF_CSI_PIXCLK (GPIO_PORTA | GPIO_PF | 14)
40#define PA15_PF_I2C_SDA (GPIO_PORTA | GPIO_PF | GPIO_OUT | 15)
41#define PA16_PF_I2C_SCL (GPIO_PORTA | GPIO_PF | GPIO_OUT | 16)
42#define PA17_AF_ETMTRACEPKT4 (GPIO_PORTA | GPIO_AF | 17)
43#define PA17_AIN_SPI2_SS (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 17)
44#define PA18_AF_ETMTRACEPKT5 (GPIO_PORTA | GPIO_AF | 18)
45#define PA19_AF_ETMTRACEPKT6 (GPIO_PORTA | GPIO_AF | 19)
46#define PA20_AF_ETMTRACEPKT7 (GPIO_PORTA | GPIO_AF | 20)
47#define PA21_PF_A0 (GPIO_PORTA | GPIO_PF | 21)
48#define PA22_PF_CS4 (GPIO_PORTA | GPIO_PF | 22)
49#define PA23_PF_CS5 (GPIO_PORTA | GPIO_PF | 23)
50#define PA24_PF_A16 (GPIO_PORTA | GPIO_PF | 24)
51#define PA24_AF_ETMTRACEPKT0 (GPIO_PORTA | GPIO_AF | 24)
52#define PA25_PF_A17 (GPIO_PORTA | GPIO_PF | 25)
53#define PA25_AF_ETMTRACEPKT1 (GPIO_PORTA | GPIO_AF | 25)
54#define PA26_PF_A18 (GPIO_PORTA | GPIO_PF | 26)
55#define PA26_AF_ETMTRACEPKT2 (GPIO_PORTA | GPIO_AF | 26)
56#define PA27_PF_A19 (GPIO_PORTA | GPIO_PF | 27)
57#define PA27_AF_ETMTRACEPKT3 (GPIO_PORTA | GPIO_AF | 27)
58#define PA28_PF_A20 (GPIO_PORTA | GPIO_PF | 28)
59#define PA28_AF_ETMPIPESTAT0 (GPIO_PORTA | GPIO_AF | 28)
60#define PA29_PF_A21 (GPIO_PORTA | GPIO_PF | 29)
61#define PA29_AF_ETMPIPESTAT1 (GPIO_PORTA | GPIO_AF | 29)
62#define PA30_PF_A22 (GPIO_PORTA | GPIO_PF | 30)
63#define PA30_AF_ETMPIPESTAT2 (GPIO_PORTA | GPIO_AF | 30)
64#define PA31_PF_A23 (GPIO_PORTA | GPIO_PF | 31)
65#define PA31_AF_ETMTRACECLK (GPIO_PORTA | GPIO_AF | 31)
66#define PB8_PF_SD_DAT0 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8)
67#define PB8_AF_MS_PIO (GPIO_PORTB | GPIO_AF | 8)
68#define PB9_PF_SD_DAT1 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9)
69#define PB9_AF_MS_PI1 (GPIO_PORTB | GPIO_AF | 9)
70#define PB10_PF_SD_DAT2 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10)
71#define PB10_AF_MS_SCLKI (GPIO_PORTB | GPIO_AF | 10)
72#define PB11_PF_SD_DAT3 (GPIO_PORTB | GPIO_PF | 11)
73#define PB11_AF_MS_SDIO (GPIO_PORTB | GPIO_AF | 11)
74#define PB12_PF_SD_CLK (GPIO_PORTB | GPIO_PF | 12)
75#define PB12_AF_MS_SCLK0 (GPIO_PORTB | GPIO_AF | 12)
76#define PB13_PF_SD_CMD (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 13)
77#define PB13_AF_MS_BS (GPIO_PORTB | GPIO_AF | 13)
78#define PB14_AF_SSI_RXFS (GPIO_PORTB | GPIO_AF | 14)
79#define PB15_AF_SSI_RXCLK (GPIO_PORTB | GPIO_AF | 15)
80#define PB16_AF_SSI_RXDAT (GPIO_PORTB | GPIO_AF | GPIO_IN | 16)
81#define PB17_AF_SSI_TXDAT (GPIO_PORTB | GPIO_AF | GPIO_OUT | 17)
82#define PB18_AF_SSI_TXFS (GPIO_PORTB | GPIO_AF | 18)
83#define PB19_AF_SSI_TXCLK (GPIO_PORTB | GPIO_AF | 19)
84#define PB20_PF_USBD_AFE (GPIO_PORTB | GPIO_PF | 20)
85#define PB21_PF_USBD_OE (GPIO_PORTB | GPIO_PF | 21)
86#define PB22_PF_USBD_RCV (GPIO_PORTB | GPIO_PF | 22)
87#define PB23_PF_USBD_SUSPND (GPIO_PORTB | GPIO_PF | 23)
88#define PB24_PF_USBD_VP (GPIO_PORTB | GPIO_PF | 24)
89#define PB25_PF_USBD_VM (GPIO_PORTB | GPIO_PF | 25)
90#define PB26_PF_USBD_VPO (GPIO_PORTB | GPIO_PF | 26)
91#define PB27_PF_USBD_VMO (GPIO_PORTB | GPIO_PF | 27)
92#define PB28_PF_UART2_CTS (GPIO_PORTB | GPIO_PF | GPIO_OUT | 28)
93#define PB29_PF_UART2_RTS (GPIO_PORTB | GPIO_PF | GPIO_IN | 29)
94#define PB30_PF_UART2_TXD (GPIO_PORTB | GPIO_PF | GPIO_OUT | 30)
95#define PB31_PF_UART2_RXD (GPIO_PORTB | GPIO_PF | GPIO_IN | 31)
96#define PC3_PF_SSI_RXFS (GPIO_PORTC | GPIO_PF | 3)
97#define PC4_PF_SSI_RXCLK (GPIO_PORTC | GPIO_PF | 4)
98#define PC5_PF_SSI_RXDAT (GPIO_PORTC | GPIO_PF | GPIO_IN | 5)
99#define PC6_PF_SSI_TXDAT (GPIO_PORTC | GPIO_PF | GPIO_OUT | 6)
100#define PC7_PF_SSI_TXFS (GPIO_PORTC | GPIO_PF | 7)
101#define PC8_PF_SSI_TXCLK (GPIO_PORTC | GPIO_PF | 8)
102#define PC9_PF_UART1_CTS (GPIO_PORTC | GPIO_PF | GPIO_OUT | 9)
103#define PC10_PF_UART1_RTS (GPIO_PORTC | GPIO_PF | GPIO_IN | 10)
104#define PC11_PF_UART1_TXD (GPIO_PORTC | GPIO_PF | GPIO_OUT | 11)
105#define PC12_PF_UART1_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 12)
106#define PC13_PF_SPI1_SPI_RDY (GPIO_PORTC | GPIO_PF | 13)
107#define PC14_PF_SPI1_SCLK (GPIO_PORTC | GPIO_PF | 14)
108#define PC15_PF_SPI1_SS (GPIO_PORTC | GPIO_PF | 15)
109#define PC16_PF_SPI1_MISO (GPIO_PORTC | GPIO_PF | 16)
110#define PC17_PF_SPI1_MOSI (GPIO_PORTC | GPIO_PF | 17)
111#define PC24_BIN_UART3_RI (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 24)
112#define PC25_BIN_UART3_DSR (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 25)
113#define PC26_AOUT_UART3_DTR (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 26)
114#define PC27_BIN_UART3_DCD (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 27)
115#define PC28_BIN_UART3_CTS (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 28)
116#define PC29_AOUT_UART3_RTS (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 29)
117#define PC30_BIN_UART3_TX (GPIO_PORTC | GPIO_BIN | 30)
118#define PC31_AOUT_UART3_RX (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 31)
119#define PD6_PF_LSCLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 6)
120#define PD7_PF_REV (GPIO_PORTD | GPIO_PF | 7)
121#define PD7_AF_UART2_DTR (GPIO_PORTD | GPIO_AF | GPIO_IN | 7)
122#define PD7_AIN_SPI2_SCLK (GPIO_PORTD | GPIO_AIN | 7)
123#define PD8_PF_CLS (GPIO_PORTD | GPIO_PF | 8)
124#define PD8_AF_UART2_DCD (GPIO_PORTD | GPIO_AF | GPIO_OUT | 8)
125#define PD8_AIN_SPI2_SS (GPIO_PORTD | GPIO_AIN | 8)
126#define PD9_PF_PS (GPIO_PORTD | GPIO_PF | 9)
127#define PD9_AF_UART2_RI (GPIO_PORTD | GPIO_AF | GPIO_OUT | 9)
128#define PD9_AOUT_SPI2_RXD (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 9)
129#define PD10_PF_SPL_SPR (GPIO_PORTD | GPIO_PF | GPIO_OUT | 10)
130#define PD10_AF_UART2_DSR (GPIO_PORTD | GPIO_AF | GPIO_OUT | 10)
131#define PD10_AIN_SPI2_TXD (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 10)
132#define PD11_PF_CONTRAST (GPIO_PORTD | GPIO_PF | GPIO_OUT | 11)
133#define PD12_PF_ACD_OE (GPIO_PORTD | GPIO_PF | GPIO_OUT | 12)
134#define PD13_PF_LP_HSYNC (GPIO_PORTD | GPIO_PF | GPIO_OUT | 13)
135#define PD14_PF_FLM_VSYNC (GPIO_PORTD | GPIO_PF | GPIO_OUT | 14)
136#define PD15_PF_LD0 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 15)
137#define PD16_PF_LD1 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 16)
138#define PD17_PF_LD2 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 17)
139#define PD18_PF_LD3 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 18)
140#define PD19_PF_LD4 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 19)
141#define PD20_PF_LD5 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 20)
142#define PD21_PF_LD6 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 21)
143#define PD22_PF_LD7 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 22)
144#define PD23_PF_LD8 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 23)
145#define PD24_PF_LD9 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 24)
146#define PD25_PF_LD10 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 25)
147#define PD26_PF_LD11 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 26)
148#define PD27_PF_LD12 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 27)
149#define PD28_PF_LD13 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 28)
150#define PD29_PF_LD14 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 29)
151#define PD30_PF_LD15 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 30)
152#define PD31_PF_TMR2OUT (GPIO_PORTD | GPIO_PF | 31)
153#define PD31_BIN_SPI2_TXD (GPIO_PORTD | GPIO_BIN | 31)
25 154
26/* FIXME: This list is not completed. The correct directions are 155#endif /* ifndef __MACH_IOMUX_MX1_H__ */
27* missing on some (many) pins
28*/
29
30
31/* Primary GPIO pin functions */
32
33#define PA0_AIN_SPI2_CLK (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 0)
34#define PA0_AF_ETMTRACESYNC (GPIO_PORTA | GPIO_AF | 0)
35#define PA1_AOUT_SPI2_RXD (GPIO_PORTA | GPIO_AOUT | GPIO_IN | 1)
36#define PA1_PF_TIN (GPIO_PORTA | GPIO_PF | 1)
37#define PA2_PF_PWM0 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 2)
38#define PA3_PF_CSI_MCLK (GPIO_PORTA | GPIO_PF | 3)
39#define PA4_PF_CSI_D0 (GPIO_PORTA | GPIO_PF | 4)
40#define PA5_PF_CSI_D1 (GPIO_PORTA | GPIO_PF | 5)
41#define PA6_PF_CSI_D2 (GPIO_PORTA | GPIO_PF | 6)
42#define PA7_PF_CSI_D3 (GPIO_PORTA | GPIO_PF | 7)
43#define PA8_PF_CSI_D4 (GPIO_PORTA | GPIO_PF | 8)
44#define PA9_PF_CSI_D5 (GPIO_PORTA | GPIO_PF | 9)
45#define PA10_PF_CSI_D6 (GPIO_PORTA | GPIO_PF | 10)
46#define PA11_PF_CSI_D7 (GPIO_PORTA | GPIO_PF | 11)
47#define PA12_PF_CSI_VSYNC (GPIO_PORTA | GPIO_PF | 12)
48#define PA13_PF_CSI_HSYNC (GPIO_PORTA | GPIO_PF | 13)
49#define PA14_PF_CSI_PIXCLK (GPIO_PORTA | GPIO_PF | 14)
50#define PA15_PF_I2C_SDA (GPIO_PORTA | GPIO_PF | GPIO_OUT | 15)
51#define PA16_PF_I2C_SCL (GPIO_PORTA | GPIO_PF | GPIO_OUT | 16)
52#define PA17_AF_ETMTRACEPKT4 (GPIO_PORTA | GPIO_AF | 17)
53#define PA17_AIN_SPI2_SS (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 17)
54#define PA18_AF_ETMTRACEPKT5 (GPIO_PORTA | GPIO_AF | 18)
55#define PA19_AF_ETMTRACEPKT6 (GPIO_PORTA | GPIO_AF | 19)
56#define PA20_AF_ETMTRACEPKT7 (GPIO_PORTA | GPIO_AF | 20)
57#define PA21_PF_A0 (GPIO_PORTA | GPIO_PF | 21)
58#define PA22_PF_CS4 (GPIO_PORTA | GPIO_PF | 22)
59#define PA23_PF_CS5 (GPIO_PORTA | GPIO_PF | 23)
60#define PA24_PF_A16 (GPIO_PORTA | GPIO_PF | 24)
61#define PA24_AF_ETMTRACEPKT0 (GPIO_PORTA | GPIO_AF | 24)
62#define PA25_PF_A17 (GPIO_PORTA | GPIO_PF | 25)
63#define PA25_AF_ETMTRACEPKT1 (GPIO_PORTA | GPIO_AF | 25)
64#define PA26_PF_A18 (GPIO_PORTA | GPIO_PF | 26)
65#define PA26_AF_ETMTRACEPKT2 (GPIO_PORTA | GPIO_AF | 26)
66#define PA27_PF_A19 (GPIO_PORTA | GPIO_PF | 27)
67#define PA27_AF_ETMTRACEPKT3 (GPIO_PORTA | GPIO_AF | 27)
68#define PA28_PF_A20 (GPIO_PORTA | GPIO_PF | 28)
69#define PA28_AF_ETMPIPESTAT0 (GPIO_PORTA | GPIO_AF | 28)
70#define PA29_PF_A21 (GPIO_PORTA | GPIO_PF | 29)
71#define PA29_AF_ETMPIPESTAT1 (GPIO_PORTA | GPIO_AF | 29)
72#define PA30_PF_A22 (GPIO_PORTA | GPIO_PF | 30)
73#define PA30_AF_ETMPIPESTAT2 (GPIO_PORTA | GPIO_AF | 30)
74#define PA31_PF_A23 (GPIO_PORTA | GPIO_PF | 31)
75#define PA31_AF_ETMTRACECLK (GPIO_PORTA | GPIO_AF | 31)
76#define PB8_PF_SD_DAT0 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8)
77#define PB8_AF_MS_PIO (GPIO_PORTB | GPIO_AF | 8)
78#define PB9_PF_SD_DAT1 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9)
79#define PB9_AF_MS_PI1 (GPIO_PORTB | GPIO_AF | 9)
80#define PB10_PF_SD_DAT2 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10)
81#define PB10_AF_MS_SCLKI (GPIO_PORTB | GPIO_AF | 10)
82#define PB11_PF_SD_DAT3 (GPIO_PORTB | GPIO_PF | 11)
83#define PB11_AF_MS_SDIO (GPIO_PORTB | GPIO_AF | 11)
84#define PB12_PF_SD_CLK (GPIO_PORTB | GPIO_PF | 12)
85#define PB12_AF_MS_SCLK0 (GPIO_PORTB | GPIO_AF | 12)
86#define PB13_PF_SD_CMD (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 13)
87#define PB13_AF_MS_BS (GPIO_PORTB | GPIO_AF | 13)
88#define PB14_AF_SSI_RXFS (GPIO_PORTB | GPIO_AF | 14)
89#define PB15_AF_SSI_RXCLK (GPIO_PORTB | GPIO_AF | 15)
90#define PB16_AF_SSI_RXDAT (GPIO_PORTB | GPIO_AF | GPIO_IN | 16)
91#define PB17_AF_SSI_TXDAT (GPIO_PORTB | GPIO_AF | GPIO_OUT | 17)
92#define PB18_AF_SSI_TXFS (GPIO_PORTB | GPIO_AF | 18)
93#define PB19_AF_SSI_TXCLK (GPIO_PORTB | GPIO_AF | 19)
94#define PB20_PF_USBD_AFE (GPIO_PORTB | GPIO_PF | 20)
95#define PB21_PF_USBD_OE (GPIO_PORTB | GPIO_PF | 21)
96#define PB22_PF_USBD_RCV (GPIO_PORTB | GPIO_PF | 22)
97#define PB23_PF_USBD_SUSPND (GPIO_PORTB | GPIO_PF | 23)
98#define PB24_PF_USBD_VP (GPIO_PORTB | GPIO_PF | 24)
99#define PB25_PF_USBD_VM (GPIO_PORTB | GPIO_PF | 25)
100#define PB26_PF_USBD_VPO (GPIO_PORTB | GPIO_PF | 26)
101#define PB27_PF_USBD_VMO (GPIO_PORTB | GPIO_PF | 27)
102#define PB28_PF_UART2_CTS (GPIO_PORTB | GPIO_PF | GPIO_OUT | 28)
103#define PB29_PF_UART2_RTS (GPIO_PORTB | GPIO_PF | GPIO_IN | 29)
104#define PB30_PF_UART2_TXD (GPIO_PORTB | GPIO_PF | GPIO_OUT | 30)
105#define PB31_PF_UART2_RXD (GPIO_PORTB | GPIO_PF | GPIO_IN | 31)
106#define PC3_PF_SSI_RXFS (GPIO_PORTC | GPIO_PF | 3)
107#define PC4_PF_SSI_RXCLK (GPIO_PORTC | GPIO_PF | 4)
108#define PC5_PF_SSI_RXDAT (GPIO_PORTC | GPIO_PF | GPIO_IN | 5)
109#define PC6_PF_SSI_TXDAT (GPIO_PORTC | GPIO_PF | GPIO_OUT | 6)
110#define PC7_PF_SSI_TXFS (GPIO_PORTC | GPIO_PF | 7)
111#define PC8_PF_SSI_TXCLK (GPIO_PORTC | GPIO_PF | 8)
112#define PC9_PF_UART1_CTS (GPIO_PORTC | GPIO_PF | GPIO_OUT | 9)
113#define PC10_PF_UART1_RTS (GPIO_PORTC | GPIO_PF | GPIO_IN | 10)
114#define PC11_PF_UART1_TXD (GPIO_PORTC | GPIO_PF | GPIO_OUT | 11)
115#define PC12_PF_UART1_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 12)
116#define PC13_PF_SPI1_SPI_RDY (GPIO_PORTC | GPIO_PF | 13)
117#define PC14_PF_SPI1_SCLK (GPIO_PORTC | GPIO_PF | 14)
118#define PC15_PF_SPI1_SS (GPIO_PORTC | GPIO_PF | 15)
119#define PC16_PF_SPI1_MISO (GPIO_PORTC | GPIO_PF | 16)
120#define PC17_PF_SPI1_MOSI (GPIO_PORTC | GPIO_PF | 17)
121#define PC24_BIN_UART3_RI (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 24)
122#define PC25_BIN_UART3_DSR (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 25)
123#define PC26_AOUT_UART3_DTR (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 26)
124#define PC27_BIN_UART3_DCD (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 27)
125#define PC28_BIN_UART3_CTS (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 28)
126#define PC29_AOUT_UART3_RTS (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 29)
127#define PC30_BIN_UART3_TX (GPIO_PORTC | GPIO_BIN | 30)
128#define PC31_AOUT_UART3_RX (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 31)
129#define PD6_PF_LSCLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 6)
130#define PD7_PF_REV (GPIO_PORTD | GPIO_PF | 7)
131#define PD7_AF_UART2_DTR (GPIO_PORTD | GPIO_AF | GPIO_IN | 7)
132#define PD7_AIN_SPI2_SCLK (GPIO_PORTD | GPIO_AIN | 7)
133#define PD8_PF_CLS (GPIO_PORTD | GPIO_PF | 8)
134#define PD8_AF_UART2_DCD (GPIO_PORTD | GPIO_AF | GPIO_OUT | 8)
135#define PD8_AIN_SPI2_SS (GPIO_PORTD | GPIO_AIN | 8)
136#define PD9_PF_PS (GPIO_PORTD | GPIO_PF | 9)
137#define PD9_AF_UART2_RI (GPIO_PORTD | GPIO_AF | GPIO_OUT | 9)
138#define PD9_AOUT_SPI2_RXD (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 9)
139#define PD10_PF_SPL_SPR (GPIO_PORTD | GPIO_PF | GPIO_OUT | 10)
140#define PD10_AF_UART2_DSR (GPIO_PORTD | GPIO_AF | GPIO_OUT | 10)
141#define PD10_AIN_SPI2_TXD (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 10)
142#define PD11_PF_CONTRAST (GPIO_PORTD | GPIO_PF | GPIO_OUT | 11)
143#define PD12_PF_ACD_OE (GPIO_PORTD | GPIO_PF | GPIO_OUT | 12)
144#define PD13_PF_LP_HSYNC (GPIO_PORTD | GPIO_PF | GPIO_OUT | 13)
145#define PD14_PF_FLM_VSYNC (GPIO_PORTD | GPIO_PF | GPIO_OUT | 14)
146#define PD15_PF_LD0 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 15)
147#define PD16_PF_LD1 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 16)
148#define PD17_PF_LD2 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 17)
149#define PD18_PF_LD3 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 18)
150#define PD19_PF_LD4 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 19)
151#define PD20_PF_LD5 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 20)
152#define PD21_PF_LD6 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 21)
153#define PD22_PF_LD7 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 22)
154#define PD23_PF_LD8 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 23)
155#define PD24_PF_LD9 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 24)
156#define PD25_PF_LD10 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 25)
157#define PD26_PF_LD11 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 26)
158#define PD27_PF_LD12 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 27)
159#define PD28_PF_LD13 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 28)
160#define PD29_PF_LD14 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 29)
161#define PD30_PF_LD15 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 30)
162#define PD31_PF_TMR2OUT (GPIO_PORTD | GPIO_PF | 31)
163#define PD31_BIN_SPI2_TXD (GPIO_PORTD | GPIO_BIN | 31)
164
165
166#endif
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx21.h b/arch/arm/plat-mxc/include/mach/iomux-mx21.h
index 63aaa972e275..1495dfda7834 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx21.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx21.h
@@ -1,126 +1,122 @@
1/* 1/*
2* Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de> 2 * Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de>
3* 3 *
4* This program is free software; you can redistribute it and/or 4 * This program is free software; you can redistribute it and/or
5* modify it under the terms of the GNU General Public License 5 * modify it under the terms of the GNU General Public License
6* as published by the Free Software Foundation; either version 2 6 * as published by the Free Software Foundation; either version 2
7* of the License, or (at your option) any later version. 7 * of the License, or (at your option) any later version.
8* This program is distributed in the hope that it will be useful, 8 * This program is distributed in the hope that it will be useful,
9* but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11* GNU General Public License for more details. 11 * GNU General Public License for more details.
12* 12 *
13* You should have received a copy of the GNU General Public License 13 * You should have received a copy of the GNU General Public License
14* along with this program; if not, write to the Free Software 14 * along with this program; if not, write to the Free Software
15* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
16* MA 02110-1301, USA. 16 * MA 02110-1301, USA.
17*/ 17 */
18 18#ifndef __MACH_IOMUX_MX21_H__
19#ifndef _MXC_IOMUX_MX21_H 19#define __MACH_IOMUX_MX21_H__
20#define _MXC_IOMUX_MX21_H 20
21 21#include <mach/iomux-mx2x.h>
22#ifndef GPIO_PORTA 22#include <mach/iomux-v1.h>
23#error Please include mach/iomux.h
24#endif
25
26 23
27/* Primary GPIO pin functions */ 24/* Primary GPIO pin functions */
28 25
29#define PB22_PF_USBH1_BYP (GPIO_PORTB | GPIO_PF | 22) 26#define PB22_PF_USBH1_BYP (GPIO_PORTB | GPIO_PF | 22)
30#define PB25_PF_USBH1_ON (GPIO_PORTB | GPIO_PF | 25) 27#define PB25_PF_USBH1_ON (GPIO_PORTB | GPIO_PF | 25)
31#define PC5_PF_USBOTG_SDA (GPIO_PORTC | GPIO_PF | 5) 28#define PC5_PF_USBOTG_SDA (GPIO_PORTC | GPIO_PF | 5)
32#define PC6_PF_USBOTG_SCL (GPIO_PORTC | GPIO_PF | 6) 29#define PC6_PF_USBOTG_SCL (GPIO_PORTC | GPIO_PF | 6)
33#define PC7_PF_USBOTG_ON (GPIO_PORTC | GPIO_PF | 7) 30#define PC7_PF_USBOTG_ON (GPIO_PORTC | GPIO_PF | 7)
34#define PC8_PF_USBOTG_FS (GPIO_PORTC | GPIO_PF | 8) 31#define PC8_PF_USBOTG_FS (GPIO_PORTC | GPIO_PF | 8)
35#define PC9_PF_USBOTG_OE (GPIO_PORTC | GPIO_PF | 9) 32#define PC9_PF_USBOTG_OE (GPIO_PORTC | GPIO_PF | 9)
36#define PC10_PF_USBOTG_TXDM (GPIO_PORTC | GPIO_PF | 10) 33#define PC10_PF_USBOTG_TXDM (GPIO_PORTC | GPIO_PF | 10)
37#define PC11_PF_USBOTG_TXDP (GPIO_PORTC | GPIO_PF | 11) 34#define PC11_PF_USBOTG_TXDP (GPIO_PORTC | GPIO_PF | 11)
38#define PC12_PF_USBOTG_RXDM (GPIO_PORTC | GPIO_PF | 12) 35#define PC12_PF_USBOTG_RXDM (GPIO_PORTC | GPIO_PF | 12)
39#define PC13_PF_USBOTG_RXDP (GPIO_PORTC | GPIO_PF | 13) 36#define PC13_PF_USBOTG_RXDP (GPIO_PORTC | GPIO_PF | 13)
40#define PC16_PF_SAP_FS (GPIO_PORTC | GPIO_PF | 16) 37#define PC16_PF_SAP_FS (GPIO_PORTC | GPIO_PF | 16)
41#define PC17_PF_SAP_RXD (GPIO_PORTC | GPIO_PF | 17) 38#define PC17_PF_SAP_RXD (GPIO_PORTC | GPIO_PF | 17)
42#define PC18_PF_SAP_TXD (GPIO_PORTC | GPIO_PF | 18) 39#define PC18_PF_SAP_TXD (GPIO_PORTC | GPIO_PF | 18)
43#define PC19_PF_SAP_CLK (GPIO_PORTC | GPIO_PF | 19) 40#define PC19_PF_SAP_CLK (GPIO_PORTC | GPIO_PF | 19)
44#define PE0_PF_TEST_WB2 (GPIO_PORTE | GPIO_PF | 0) 41#define PE0_PF_TEST_WB2 (GPIO_PORTE | GPIO_PF | 0)
45#define PE1_PF_TEST_WB1 (GPIO_PORTE | GPIO_PF | 1) 42#define PE1_PF_TEST_WB1 (GPIO_PORTE | GPIO_PF | 1)
46#define PE2_PF_TEST_WB0 (GPIO_PORTE | GPIO_PF | 2) 43#define PE2_PF_TEST_WB0 (GPIO_PORTE | GPIO_PF | 2)
47#define PF1_PF_NFCE (GPIO_PORTF | GPIO_PF | 1) 44#define PF1_PF_NFCE (GPIO_PORTF | GPIO_PF | 1)
48#define PF3_PF_NFCLE (GPIO_PORTF | GPIO_PF | 3) 45#define PF3_PF_NFCLE (GPIO_PORTF | GPIO_PF | 3)
49#define PF7_PF_NFIO0 (GPIO_PORTF | GPIO_PF | 7) 46#define PF7_PF_NFIO0 (GPIO_PORTF | GPIO_PF | 7)
50#define PF8_PF_NFIO1 (GPIO_PORTF | GPIO_PF | 8) 47#define PF8_PF_NFIO1 (GPIO_PORTF | GPIO_PF | 8)
51#define PF9_PF_NFIO2 (GPIO_PORTF | GPIO_PF | 9) 48#define PF9_PF_NFIO2 (GPIO_PORTF | GPIO_PF | 9)
52#define PF10_PF_NFIO3 (GPIO_PORTF | GPIO_PF | 10) 49#define PF10_PF_NFIO3 (GPIO_PORTF | GPIO_PF | 10)
53#define PF11_PF_NFIO4 (GPIO_PORTF | GPIO_PF | 11) 50#define PF11_PF_NFIO4 (GPIO_PORTF | GPIO_PF | 11)
54#define PF12_PF_NFIO5 (GPIO_PORTF | GPIO_PF | 12) 51#define PF12_PF_NFIO5 (GPIO_PORTF | GPIO_PF | 12)
55#define PF13_PF_NFIO6 (GPIO_PORTF | GPIO_PF | 13) 52#define PF13_PF_NFIO6 (GPIO_PORTF | GPIO_PF | 13)
56#define PF14_PF_NFIO7 (GPIO_PORTF | GPIO_PF | 14) 53#define PF14_PF_NFIO7 (GPIO_PORTF | GPIO_PF | 14)
57#define PF16_PF_RES (GPIO_PORTF | GPIO_PF | 16) 54#define PF16_PF_RES (GPIO_PORTF | GPIO_PF | 16)
58 55
59/* Alternate GPIO pin functions */ 56/* Alternate GPIO pin functions */
60 57
61#define PA5_AF_BMI_CLK_CS (GPIO_PORTA | GPIO_AF | 5) 58#define PA5_AF_BMI_CLK_CS (GPIO_PORTA | GPIO_AF | 5)
62#define PA6_AF_BMI_D0 (GPIO_PORTA | GPIO_AF | 6) 59#define PA6_AF_BMI_D0 (GPIO_PORTA | GPIO_AF | 6)
63#define PA7_AF_BMI_D1 (GPIO_PORTA | GPIO_AF | 7) 60#define PA7_AF_BMI_D1 (GPIO_PORTA | GPIO_AF | 7)
64#define PA8_AF_BMI_D2 (GPIO_PORTA | GPIO_AF | 8) 61#define PA8_AF_BMI_D2 (GPIO_PORTA | GPIO_AF | 8)
65#define PA9_AF_BMI_D3 (GPIO_PORTA | GPIO_AF | 9) 62#define PA9_AF_BMI_D3 (GPIO_PORTA | GPIO_AF | 9)
66#define PA10_AF_BMI_D4 (GPIO_PORTA | GPIO_AF | 10) 63#define PA10_AF_BMI_D4 (GPIO_PORTA | GPIO_AF | 10)
67#define PA11_AF_BMI_D5 (GPIO_PORTA | GPIO_AF | 11) 64#define PA11_AF_BMI_D5 (GPIO_PORTA | GPIO_AF | 11)
68#define PA12_AF_BMI_D6 (GPIO_PORTA | GPIO_AF | 12) 65#define PA12_AF_BMI_D6 (GPIO_PORTA | GPIO_AF | 12)
69#define PA13_AF_BMI_D7 (GPIO_PORTA | GPIO_AF | 13) 66#define PA13_AF_BMI_D7 (GPIO_PORTA | GPIO_AF | 13)
70#define PA14_AF_BMI_D8 (GPIO_PORTA | GPIO_AF | 14) 67#define PA14_AF_BMI_D8 (GPIO_PORTA | GPIO_AF | 14)
71#define PA15_AF_BMI_D9 (GPIO_PORTA | GPIO_AF | 15) 68#define PA15_AF_BMI_D9 (GPIO_PORTA | GPIO_AF | 15)
72#define PA16_AF_BMI_D10 (GPIO_PORTA | GPIO_AF | 16) 69#define PA16_AF_BMI_D10 (GPIO_PORTA | GPIO_AF | 16)
73#define PA17_AF_BMI_D11 (GPIO_PORTA | GPIO_AF | 17) 70#define PA17_AF_BMI_D11 (GPIO_PORTA | GPIO_AF | 17)
74#define PA18_AF_BMI_D12 (GPIO_PORTA | GPIO_AF | 18) 71#define PA18_AF_BMI_D12 (GPIO_PORTA | GPIO_AF | 18)
75#define PA19_AF_BMI_D13 (GPIO_PORTA | GPIO_AF | 19) 72#define PA19_AF_BMI_D13 (GPIO_PORTA | GPIO_AF | 19)
76#define PA20_AF_BMI_D14 (GPIO_PORTA | GPIO_AF | 20) 73#define PA20_AF_BMI_D14 (GPIO_PORTA | GPIO_AF | 20)
77#define PA21_AF_BMI_D15 (GPIO_PORTA | GPIO_AF | 21) 74#define PA21_AF_BMI_D15 (GPIO_PORTA | GPIO_AF | 21)
78#define PA22_AF_BMI_READ_REQ (GPIO_PORTA | GPIO_AF | 22) 75#define PA22_AF_BMI_READ_REQ (GPIO_PORTA | GPIO_AF | 22)
79#define PA23_AF_BMI_WRITE (GPIO_PORTA | GPIO_AF | 23) 76#define PA23_AF_BMI_WRITE (GPIO_PORTA | GPIO_AF | 23)
80#define PA29_AF_BMI_RX_FULL (GPIO_PORTA | GPIO_AF | 29) 77#define PA29_AF_BMI_RX_FULL (GPIO_PORTA | GPIO_AF | 29)
81#define PA30_AF_BMI_READ (GPIO_PORTA | GPIO_AF | 30) 78#define PA30_AF_BMI_READ (GPIO_PORTA | GPIO_AF | 30)
82 79
83/* AIN GPIO pin functions */ 80/* AIN GPIO pin functions */
84 81
85#define PC14_AIN_SYS_CLK (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 14) 82#define PC14_AIN_SYS_CLK (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 14)
86#define PD21_AIN_USBH2_FS (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 21) 83#define PD21_AIN_USBH2_FS (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 21)
87#define PD22_AIN_USBH2_OE (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 22) 84#define PD22_AIN_USBH2_OE (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 22)
88#define PD23_AIN_USBH2_TXDM (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 23) 85#define PD23_AIN_USBH2_TXDM (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 23)
89#define PD24_AIN_USBH2_TXDP (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 24) 86#define PD24_AIN_USBH2_TXDP (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 24)
90#define PE8_AIN_IR_TXD (GPIO_PORTE | GPIO_AIN | GPIO_OUT | 8) 87#define PE8_AIN_IR_TXD (GPIO_PORTE | GPIO_AIN | GPIO_OUT | 8)
91#define PF0_AIN_PC_RST (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 0) 88#define PF0_AIN_PC_RST (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 0)
92#define PF1_AIN_PC_CE1 (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 1) 89#define PF1_AIN_PC_CE1 (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 1)
93#define PF2_AIN_PC_CE2 (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 2) 90#define PF2_AIN_PC_CE2 (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 2)
94#define PF3_AIN_PC_POE (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 3) 91#define PF3_AIN_PC_POE (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 3)
95#define PF4_AIN_PC_OE (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 4) 92#define PF4_AIN_PC_OE (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 4)
96#define PF5_AIN_PC_RW (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 5) 93#define PF5_AIN_PC_RW (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 5)
97 94
98/* BIN GPIO pin functions */ 95/* BIN GPIO pin functions */
99 96
100#define PC14_BIN_SYS_CLK (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 14) 97#define PC14_BIN_SYS_CLK (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 14)
101#define PD27_BIN_EXT_DMA_GRANT (GPIO_PORTD | GPIO_BIN | GPIO_OUT | 27) 98#define PD27_BIN_EXT_DMA_GRANT (GPIO_PORTD | GPIO_BIN | GPIO_OUT | 27)
102 99
103/* CIN GPIO pin functions */ 100/* CIN GPIO pin functions */
104 101
105#define PB26_CIN_USBH1_RXDAT (GPIO_PORTB | GPIO_CIN | GPIO_OUT | 26) 102#define PB26_CIN_USBH1_RXDAT (GPIO_PORTB | GPIO_CIN | GPIO_OUT | 26)
106 103
107/* AOUT GPIO pin functions */ 104/* AOUT GPIO pin functions */
108 105
109#define PA29_AOUT_BMI_WAIT (GPIO_PORTA | GPIO_AOUT | GPIO_IN | 29) 106#define PA29_AOUT_BMI_WAIT (GPIO_PORTA | GPIO_AOUT | GPIO_IN | 29)
110#define PD19_AOUT_USBH2_RXDM (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 19) 107#define PD19_AOUT_USBH2_RXDM (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 19)
111#define PD20_AOUT_USBH2_RXDP (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 20) 108#define PD20_AOUT_USBH2_RXDP (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 20)
112#define PD25_AOUT_EXT_DMAREQ (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 25) 109#define PD25_AOUT_EXT_DMAREQ (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 25)
113#define PD26_AOUT_USBOTG_RXDAT (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 26) 110#define PD26_AOUT_USBOTG_RXDAT (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 26)
114#define PE9_AOUT_IR_RXD (GPIO_PORTE | GPIO_AOUT | GPIO_IN | 9) 111#define PE9_AOUT_IR_RXD (GPIO_PORTE | GPIO_AOUT | GPIO_IN | 9)
115#define PF6_AOUT_PC_BVD2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 6) 112#define PF6_AOUT_PC_BVD2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 6)
116#define PF7_AOUT_PC_BVD1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 7) 113#define PF7_AOUT_PC_BVD1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 7)
117#define PF8_AOUT_PC_VS2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 8) 114#define PF8_AOUT_PC_VS2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 8)
118#define PF9_AOUT_PC_VS1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 9) 115#define PF9_AOUT_PC_VS1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 9)
119#define PF10_AOUT_PC_WP (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 10) 116#define PF10_AOUT_PC_WP (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 10)
120#define PF11_AOUT_PC_READY (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 11) 117#define PF11_AOUT_PC_READY (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 11)
121#define PF12_AOUT_PC_WAIT (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 12) 118#define PF12_AOUT_PC_WAIT (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 12)
122#define PF13_AOUT_PC_CD2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 13) 119#define PF13_AOUT_PC_CD2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 13)
123#define PF14_AOUT_PC_CD1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 14) 120#define PF14_AOUT_PC_CD1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 14)
124 121
125 122#endif /* ifndef __MACH_IOMUX_MX21_H__ */
126#endif
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx25.h b/arch/arm/plat-mxc/include/mach/iomux-mx25.h
index 5418d52c4a9d..f39220d1b67a 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx25.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx25.h
@@ -7,7 +7,7 @@
7 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. 7 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
8 * and 8 * and
9 * arch/arm/plat-mxc/include/mach/iomux-mx35.h 9 * arch/arm/plat-mxc/include/mach/iomux-mx35.h
10 * Copyright (C, NO_PAD_CTRL) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de> 10 * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de>
11 * 11 *
12 * The code contained herein is licensed under the GNU General Public 12 * The code contained herein is licensed under the GNU General Public
13 * License. You may obtain a copy of the GNU General Public License 13 * License. You may obtain a copy of the GNU General Public License
@@ -16,24 +16,11 @@
16 * http://www.opensource.org/licenses/gpl-license.html 16 * http://www.opensource.org/licenses/gpl-license.html
17 * http://www.gnu.org/copyleft/gpl.html 17 * http://www.gnu.org/copyleft/gpl.html
18 */ 18 */
19#ifndef __IOMUX_MX25_H__ 19#ifndef __MACH_IOMUX_MX25_H__
20#define __IOMUX_MX25_H__ 20#define __MACH_IOMUX_MX25_H__
21 21
22#include <mach/iomux-v3.h> 22#include <mach/iomux-v3.h>
23 23
24#ifndef GPIO_PORTA
25#error Please include mach/iomux.h
26#endif
27
28/*
29 *
30 * @brief MX25 I/O Pin List
31 *
32 * @ingroup GPIO_MX25
33 */
34
35#ifndef __ASSEMBLY__
36
37/* 24/*
38 * IOMUX/PAD Bit field definitions 25 * IOMUX/PAD Bit field definitions
39 */ 26 */
@@ -515,5 +502,4 @@
515#define MX25_PAD_CTL_GRP_DVS_SDHC1 IOMUX_PAD(0x458, 0x000, 0, 0, 0, NO_PAD_CTRL) 502#define MX25_PAD_CTL_GRP_DVS_SDHC1 IOMUX_PAD(0x458, 0x000, 0, 0, 0, NO_PAD_CTRL)
516#define MX25_PAD_CTL_GRP_DVS_LCD IOMUX_PAD(0x45c, 0x000, 0, 0, 0, NO_PAD_CTRL) 503#define MX25_PAD_CTL_GRP_DVS_LCD IOMUX_PAD(0x45c, 0x000, 0, 0, 0, NO_PAD_CTRL)
517 504
518#endif // __ASSEMBLY__ 505#endif /* __MACH_IOMUX_MX25_H__ */
519#endif // __IOMUX_MX25_H__
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx27.h b/arch/arm/plat-mxc/include/mach/iomux-mx27.h
index 5ac158b70f61..d9f9a6e32d80 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx27.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx27.h
@@ -1,207 +1,205 @@
1/* 1/*
2* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> 2 * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
3* Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de> 3 * Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de>
4* 4 *
5* This program is free software; you can redistribute it and/or 5 * This program is free software; you can redistribute it and/or
6* modify it under the terms of the GNU General Public License 6 * modify it under the terms of the GNU General Public License
7* as published by the Free Software Foundation; either version 2 7 * as published by the Free Software Foundation; either version 2
8* of the License, or (at your option) any later version. 8 * of the License, or (at your option) any later version.
9* This program is distributed in the hope that it will be useful, 9 * This program is distributed in the hope that it will be useful,
10* but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12* GNU General Public License for more details. 12 * GNU General Public License for more details.
13* 13 *
14* You should have received a copy of the GNU General Public License 14 * You should have received a copy of the GNU General Public License
15* along with this program; if not, write to the Free Software 15 * along with this program; if not, write to the Free Software
16* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17* MA 02110-1301, USA. 17 * MA 02110-1301, USA.
18*/ 18 */
19 19#ifndef __MACH_IOMUX_MX27_H__
20#ifndef _MXC_IOMUX_MX27_H 20#define __MACH_IOMUX_MX27_H__
21#define _MXC_IOMUX_MX27_H 21
22 22#include <mach/iomux-mx2x.h>
23#ifndef GPIO_PORTA 23#include <mach/iomux-v1.h>
24#error Please include mach/iomux.h
25#endif
26
27 24
28/* Primary GPIO pin functions */ 25/* Primary GPIO pin functions */
29 26
30#define PA0_PF_USBH2_CLK (GPIO_PORTA | GPIO_PF | 0) 27#define PA0_PF_USBH2_CLK (GPIO_PORTA | GPIO_PF | 0)
31#define PA1_PF_USBH2_DIR (GPIO_PORTA | GPIO_PF | 1) 28#define PA1_PF_USBH2_DIR (GPIO_PORTA | GPIO_PF | 1)
32#define PA2_PF_USBH2_DATA7 (GPIO_PORTA | GPIO_PF | 2) 29#define PA2_PF_USBH2_DATA7 (GPIO_PORTA | GPIO_PF | 2)
33#define PA3_PF_USBH2_NXT (GPIO_PORTA | GPIO_PF | 3) 30#define PA3_PF_USBH2_NXT (GPIO_PORTA | GPIO_PF | 3)
34#define PA4_PF_USBH2_STP (GPIO_PORTA | GPIO_PF | 4) 31#define PA4_PF_USBH2_STP (GPIO_PORTA | GPIO_PF | 4)
35#define PB22_PF_USBH1_SUSP (GPIO_PORTB | GPIO_PF | 22) 32#define PB22_PF_USBH1_SUSP (GPIO_PORTB | GPIO_PF | 22)
36#define PB25_PF_USBH1_RCV (GPIO_PORTB | GPIO_PF | 25) 33#define PB25_PF_USBH1_RCV (GPIO_PORTB | GPIO_PF | 25)
37#define PC5_PF_I2C2_SDA (GPIO_PORTC | GPIO_PF | GPIO_IN | 5) 34#define PC5_PF_I2C2_SDA (GPIO_PORTC | GPIO_PF | GPIO_IN | 5)
38#define PC6_PF_I2C2_SCL (GPIO_PORTC | GPIO_PF | GPIO_IN | 6) 35#define PC6_PF_I2C2_SCL (GPIO_PORTC | GPIO_PF | GPIO_IN | 6)
39#define PC7_PF_USBOTG_DATA5 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 7) 36#define PC7_PF_USBOTG_DATA5 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 7)
40#define PC8_PF_USBOTG_DATA6 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 8) 37#define PC8_PF_USBOTG_DATA6 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 8)
41#define PC9_PF_USBOTG_DATA0 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 9) 38#define PC9_PF_USBOTG_DATA0 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 9)
42#define PC10_PF_USBOTG_DATA2 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 10) 39#define PC10_PF_USBOTG_DATA2 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 10)
43#define PC11_PF_USBOTG_DATA1 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 11) 40#define PC11_PF_USBOTG_DATA1 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 11)
44#define PC12_PF_USBOTG_DATA4 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 12) 41#define PC12_PF_USBOTG_DATA4 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 12)
45#define PC13_PF_USBOTG_DATA3 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 13) 42#define PC13_PF_USBOTG_DATA3 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 13)
46#define PC16_PF_SSI4_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 16) 43#define PC16_PF_SSI4_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 16)
47#define PC17_PF_SSI4_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 17) 44#define PC17_PF_SSI4_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 17)
48#define PC18_PF_SSI4_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 18) 45#define PC18_PF_SSI4_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 18)
49#define PC19_PF_SSI4_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 19) 46#define PC19_PF_SSI4_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 19)
50#define PC25_AF_GPT5_TIN (GPIO_PORTC | GPIO_AF | 25) 47#define PD0_PF_SD3_CMD (GPIO_PORTD | GPIO_PF | 0)
51#define PC27_AF_GPT4_TIN (GPIO_PORTC | GPIO_AF | 27) 48#define PD1_PF_SD3_CLK (GPIO_PORTD | GPIO_PF | 1)
52#define PD0_PF_SD3_CMD (GPIO_PORTD | GPIO_PF | 0) 49#define PD2_PF_ATA_DATA0 (GPIO_PORTD | GPIO_PF | 2)
53#define PD1_PF_SD3_CLK (GPIO_PORTD | GPIO_PF | 1) 50#define PD3_PF_ATA_DATA1 (GPIO_PORTD | GPIO_PF | 3)
54#define PD2_PF_ATA_DATA0 (GPIO_PORTD | GPIO_PF | 2) 51#define PD4_PF_ATA_DATA2 (GPIO_PORTD | GPIO_PF | 4)
55#define PD3_PF_ATA_DATA1 (GPIO_PORTD | GPIO_PF | 3) 52#define PD5_PF_ATA_DATA3 (GPIO_PORTD | GPIO_PF | 5)
56#define PD4_PF_ATA_DATA2 (GPIO_PORTD | GPIO_PF | 4) 53#define PD6_PF_ATA_DATA4 (GPIO_PORTD | GPIO_PF | 6)
57#define PD5_PF_ATA_DATA3 (GPIO_PORTD | GPIO_PF | 5) 54#define PD7_PF_ATA_DATA5 (GPIO_PORTD | GPIO_PF | 7)
58#define PD6_PF_ATA_DATA4 (GPIO_PORTD | GPIO_PF | 6) 55#define PD8_PF_ATA_DATA6 (GPIO_PORTD | GPIO_PF | 8)
59#define PD7_PF_ATA_DATA5 (GPIO_PORTD | GPIO_PF | 7) 56#define PD9_PF_ATA_DATA7 (GPIO_PORTD | GPIO_PF | 9)
60#define PD8_PF_ATA_DATA6 (GPIO_PORTD | GPIO_PF | 8) 57#define PD10_PF_ATA_DATA8 (GPIO_PORTD | GPIO_PF | 10)
61#define PD9_PF_ATA_DATA7 (GPIO_PORTD | GPIO_PF | 9) 58#define PD11_PF_ATA_DATA9 (GPIO_PORTD | GPIO_PF | 11)
62#define PD10_PF_ATA_DATA8 (GPIO_PORTD | GPIO_PF | 10) 59#define PD12_PF_ATA_DATA10 (GPIO_PORTD | GPIO_PF | 12)
63#define PD11_PF_ATA_DATA9 (GPIO_PORTD | GPIO_PF | 11) 60#define PD13_PF_ATA_DATA11 (GPIO_PORTD | GPIO_PF | 13)
64#define PD12_PF_ATA_DATA10 (GPIO_PORTD | GPIO_PF | 12) 61#define PD14_PF_ATA_DATA12 (GPIO_PORTD | GPIO_PF | 14)
65#define PD13_PF_ATA_DATA11 (GPIO_PORTD | GPIO_PF | 13) 62#define PD15_PF_ATA_DATA13 (GPIO_PORTD | GPIO_PF | 15)
66#define PD14_PF_ATA_DATA12 (GPIO_PORTD | GPIO_PF | 14) 63#define PD16_PF_ATA_DATA14 (GPIO_PORTD | GPIO_PF | 16)
67#define PD15_PF_ATA_DATA13 (GPIO_PORTD | GPIO_PF | 15) 64#define PE0_PF_USBOTG_NXT (GPIO_PORTE | GPIO_PF | GPIO_OUT | 0)
68#define PD16_PF_ATA_DATA14 (GPIO_PORTD | GPIO_PF | 16) 65#define PE1_PF_USBOTG_STP (GPIO_PORTE | GPIO_PF | GPIO_OUT | 1)
69#define PE0_PF_USBOTG_NXT (GPIO_PORTE | GPIO_PF | GPIO_OUT | 0) 66#define PE2_PF_USBOTG_DIR (GPIO_PORTE | GPIO_PF | GPIO_OUT | 2)
70#define PE1_PF_USBOTG_STP (GPIO_PORTE | GPIO_PF | GPIO_OUT | 1) 67#define PE24_PF_USBOTG_CLK (GPIO_PORTE | GPIO_PF | GPIO_OUT | 24)
71#define PE2_PF_USBOTG_DIR (GPIO_PORTE | GPIO_PF | GPIO_OUT | 2) 68#define PE25_PF_USBOTG_DATA7 (GPIO_PORTE | GPIO_PF | GPIO_OUT | 25)
72#define PE24_PF_USBOTG_CLK (GPIO_PORTE | GPIO_PF | GPIO_OUT | 24) 69#define PF1_PF_NFCLE (GPIO_PORTF | GPIO_PF | 1)
73#define PE25_PF_USBOTG_DATA7 (GPIO_PORTE | GPIO_PF | GPIO_OUT | 25) 70#define PF3_PF_NFCE (GPIO_PORTF | GPIO_PF | 3)
74#define PF1_PF_NFCLE (GPIO_PORTF | GPIO_PF | 1) 71#define PF7_PF_PC_POE (GPIO_PORTF | GPIO_PF | 7)
75#define PF3_PF_NFCE (GPIO_PORTF | GPIO_PF | 3) 72#define PF8_PF_PC_RW (GPIO_PORTF | GPIO_PF | 8)
76#define PF7_PF_PC_POE (GPIO_PORTF | GPIO_PF | 7) 73#define PF9_PF_PC_IOIS16 (GPIO_PORTF | GPIO_PF | 9)
77#define PF8_PF_PC_RW (GPIO_PORTF | GPIO_PF | 8) 74#define PF10_PF_PC_RST (GPIO_PORTF | GPIO_PF | 10)
78#define PF9_PF_PC_IOIS16 (GPIO_PORTF | GPIO_PF | 9) 75#define PF11_PF_PC_BVD2 (GPIO_PORTF | GPIO_PF | 11)
79#define PF10_PF_PC_RST (GPIO_PORTF | GPIO_PF | 10) 76#define PF12_PF_PC_BVD1 (GPIO_PORTF | GPIO_PF | 12)
80#define PF11_PF_PC_BVD2 (GPIO_PORTF | GPIO_PF | 11) 77#define PF13_PF_PC_VS2 (GPIO_PORTF | GPIO_PF | 13)
81#define PF12_PF_PC_BVD1 (GPIO_PORTF | GPIO_PF | 12) 78#define PF14_PF_PC_VS1 (GPIO_PORTF | GPIO_PF | 14)
82#define PF13_PF_PC_VS2 (GPIO_PORTF | GPIO_PF | 13) 79#define PF16_PF_PC_PWRON (GPIO_PORTF | GPIO_PF | 16)
83#define PF14_PF_PC_VS1 (GPIO_PORTF | GPIO_PF | 14) 80#define PF17_PF_PC_READY (GPIO_PORTF | GPIO_PF | 17)
84#define PF16_PF_PC_PWRON (GPIO_PORTF | GPIO_PF | 16) 81#define PF18_PF_PC_WAIT (GPIO_PORTF | GPIO_PF | 18)
85#define PF17_PF_PC_READY (GPIO_PORTF | GPIO_PF | 17) 82#define PF19_PF_PC_CD2 (GPIO_PORTF | GPIO_PF | 19)
86#define PF18_PF_PC_WAIT (GPIO_PORTF | GPIO_PF | 18) 83#define PF20_PF_PC_CD1 (GPIO_PORTF | GPIO_PF | 20)
87#define PF19_PF_PC_CD2 (GPIO_PORTF | GPIO_PF | 19) 84#define PF23_PF_ATA_DATA15 (GPIO_PORTF | GPIO_PF | 23)
88#define PF20_PF_PC_CD1 (GPIO_PORTF | GPIO_PF | 20)
89#define PF23_PF_ATA_DATA15 (GPIO_PORTF | GPIO_PF | 23)
90 85
91/* Alternate GPIO pin functions */ 86/* Alternate GPIO pin functions */
92 87
93#define PB4_AF_MSHC_DATA0 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 4) 88#define PB4_AF_MSHC_DATA0 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 4)
94#define PB5_AF_MSHC_DATA1 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 5) 89#define PB5_AF_MSHC_DATA1 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 5)
95#define PB6_AF_MSHC_DATA2 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 6) 90#define PB6_AF_MSHC_DATA2 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 6)
96#define PB7_AF_MSHC_DATA4 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 7) 91#define PB7_AF_MSHC_DATA4 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 7)
97#define PB8_AF_MSHC_BS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 8) 92#define PB8_AF_MSHC_BS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 8)
98#define PB9_AF_MSHC_SCLK (GPIO_PORTB | GPIO_AF | GPIO_OUT | 9) 93#define PB9_AF_MSHC_SCLK (GPIO_PORTB | GPIO_AF | GPIO_OUT | 9)
99#define PB10_AF_UART6_TXD (GPIO_PORTB | GPIO_AF | GPIO_OUT | 10) 94#define PB10_AF_UART6_TXD (GPIO_PORTB | GPIO_AF | GPIO_OUT | 10)
100#define PB11_AF_UART6_RXD (GPIO_PORTB | GPIO_AF | GPIO_IN | 11) 95#define PB11_AF_UART6_RXD (GPIO_PORTB | GPIO_AF | GPIO_IN | 11)
101#define PB12_AF_UART6_CTS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 12) 96#define PB12_AF_UART6_CTS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 12)
102#define PB13_AF_UART6_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 13) 97#define PB13_AF_UART6_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 13)
103#define PB18_AF_UART5_TXD (GPIO_PORTB | GPIO_AF | GPIO_OUT | 18) 98#define PB18_AF_UART5_TXD (GPIO_PORTB | GPIO_AF | GPIO_OUT | 18)
104#define PB19_AF_UART5_RXD (GPIO_PORTB | GPIO_AF | GPIO_IN | 19) 99#define PB19_AF_UART5_RXD (GPIO_PORTB | GPIO_AF | GPIO_IN | 19)
105#define PB20_AF_UART5_CTS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 20) 100#define PB20_AF_UART5_CTS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 20)
106#define PB21_AF_UART5_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 21) 101#define PB21_AF_UART5_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 21)
107#define PC8_AF_FEC_MDIO (GPIO_PORTC | GPIO_AF | GPIO_IN | 8) 102#define PC8_AF_FEC_MDIO (GPIO_PORTC | GPIO_AF | GPIO_IN | 8)
108#define PC24_AF_GPT5_TOUT (GPIO_PORTC | GPIO_AF | 24) 103#define PC24_AF_GPT5_TOUT (GPIO_PORTC | GPIO_AF | 24)
109#define PC26_AF_GPT4_TOUT (GPIO_PORTC | GPIO_AF | 26) 104#define PC25_AF_GPT5_TIN (GPIO_PORTC | GPIO_AF | 25)
110#define PD1_AF_ETMTRACE_PKT15 (GPIO_PORTD | GPIO_AF | 1) 105#define PC26_AF_GPT4_TOUT (GPIO_PORTC | GPIO_AF | 26)
111#define PD6_AF_ETMTRACE_PKT14 (GPIO_PORTD | GPIO_AF | 6) 106#define PC27_AF_GPT4_TIN (GPIO_PORTC | GPIO_AF | 27)
112#define PD7_AF_ETMTRACE_PKT13 (GPIO_PORTD | GPIO_AF | 7) 107#define PD1_AF_ETMTRACE_PKT15 (GPIO_PORTD | GPIO_AF | 1)
113#define PD9_AF_ETMTRACE_PKT12 (GPIO_PORTD | GPIO_AF | 9) 108#define PD6_AF_ETMTRACE_PKT14 (GPIO_PORTD | GPIO_AF | 6)
114#define PD2_AF_SD3_D0 (GPIO_PORTD | GPIO_AF | 2) 109#define PD7_AF_ETMTRACE_PKT13 (GPIO_PORTD | GPIO_AF | 7)
115#define PD3_AF_SD3_D1 (GPIO_PORTD | GPIO_AF | 3) 110#define PD9_AF_ETMTRACE_PKT12 (GPIO_PORTD | GPIO_AF | 9)
116#define PD4_AF_SD3_D2 (GPIO_PORTD | GPIO_AF | 4) 111#define PD2_AF_SD3_D0 (GPIO_PORTD | GPIO_AF | 2)
117#define PD5_AF_SD3_D3 (GPIO_PORTD | GPIO_AF | 5) 112#define PD3_AF_SD3_D1 (GPIO_PORTD | GPIO_AF | 3)
118#define PD8_AF_FEC_MDIO (GPIO_PORTD | GPIO_AF | GPIO_IN | 8) 113#define PD4_AF_SD3_D2 (GPIO_PORTD | GPIO_AF | 4)
119#define PD10_AF_ETMTRACE_PKT11 (GPIO_PORTD | GPIO_AF | 10) 114#define PD5_AF_SD3_D3 (GPIO_PORTD | GPIO_AF | 5)
120#define PD11_AF_ETMTRACE_PKT10 (GPIO_PORTD | GPIO_AF | 11) 115#define PD8_AF_FEC_MDIO (GPIO_PORTD | GPIO_AF | GPIO_IN | 8)
121#define PD12_AF_ETMTRACE_PKT9 (GPIO_PORTD | GPIO_AF | 12) 116#define PD10_AF_ETMTRACE_PKT11 (GPIO_PORTD | GPIO_AF | 10)
122#define PD13_AF_ETMTRACE_PKT8 (GPIO_PORTD | GPIO_AF | 13) 117#define PD11_AF_ETMTRACE_PKT10 (GPIO_PORTD | GPIO_AF | 11)
123#define PD14_AF_ETMTRACE_PKT7 (GPIO_PORTD | GPIO_AF | 14) 118#define PD12_AF_ETMTRACE_PKT9 (GPIO_PORTD | GPIO_AF | 12)
124#define PD15_AF_ETMTRACE_PKT6 (GPIO_PORTD | GPIO_AF | 15) 119#define PD13_AF_ETMTRACE_PKT8 (GPIO_PORTD | GPIO_AF | 13)
125#define PD16_AF_ETMTRACE_PKT5 (GPIO_PORTD | GPIO_AF | 16) 120#define PD14_AF_ETMTRACE_PKT7 (GPIO_PORTD | GPIO_AF | 14)
126#define PF1_AF_ETMTRACE_PKT0 (GPIO_PORTF | GPIO_AF | 1) 121#define PD15_AF_ETMTRACE_PKT6 (GPIO_PORTD | GPIO_AF | 15)
127#define PF3_AF_ETMTRACE_PKT2 (GPIO_PORTF | GPIO_AF | 3) 122#define PD16_AF_ETMTRACE_PKT5 (GPIO_PORTD | GPIO_AF | 16)
128#define PF5_AF_ETMPIPESTAT11 (GPIO_PORTF | GPIO_AF | 5) 123#define PF1_AF_ETMTRACE_PKT0 (GPIO_PORTF | GPIO_AF | 1)
129#define PF7_AF_ATA_BUFFER_EN (GPIO_PORTF | GPIO_AF | 7) 124#define PF3_AF_ETMTRACE_PKT2 (GPIO_PORTF | GPIO_AF | 3)
130#define PF8_AF_ATA_IORDY (GPIO_PORTF | GPIO_AF | 8) 125#define PF5_AF_ETMPIPESTAT11 (GPIO_PORTF | GPIO_AF | 5)
131#define PF9_AF_ATA_INTRQ (GPIO_PORTF | GPIO_AF | 9) 126#define PF7_AF_ATA_BUFFER_EN (GPIO_PORTF | GPIO_AF | 7)
132#define PF10_AF_ATA_RESET (GPIO_PORTF | GPIO_AF | 10) 127#define PF8_AF_ATA_IORDY (GPIO_PORTF | GPIO_AF | 8)
133#define PF11_AF_ATA_DMACK (GPIO_PORTF | GPIO_AF | 11) 128#define PF9_AF_ATA_INTRQ (GPIO_PORTF | GPIO_AF | 9)
134#define PF12_AF_ATA_DMAREQ (GPIO_PORTF | GPIO_AF | 12) 129#define PF10_AF_ATA_RESET (GPIO_PORTF | GPIO_AF | 10)
135#define PF13_AF_ATA_DA0 (GPIO_PORTF | GPIO_AF | 13) 130#define PF11_AF_ATA_DMACK (GPIO_PORTF | GPIO_AF | 11)
136#define PF14_AF_ATA_DA1 (GPIO_PORTF | GPIO_AF | 14) 131#define PF12_AF_ATA_DMAREQ (GPIO_PORTF | GPIO_AF | 12)
137#define PF15_AF_ETMTRACE_SYNC (GPIO_PORTF | GPIO_AF | 15) 132#define PF13_AF_ATA_DA0 (GPIO_PORTF | GPIO_AF | 13)
138#define PF16_AF_ATA_DA2 (GPIO_PORTF | GPIO_AF | 16) 133#define PF14_AF_ATA_DA1 (GPIO_PORTF | GPIO_AF | 14)
139#define PF17_AF_ATA_CS0 (GPIO_PORTF | GPIO_AF | 17) 134#define PF15_AF_ETMTRACE_SYNC (GPIO_PORTF | GPIO_AF | 15)
140#define PF18_AF_ATA_CS1 (GPIO_PORTF | GPIO_AF | 18) 135#define PF16_AF_ATA_DA2 (GPIO_PORTF | GPIO_AF | 16)
141#define PF19_AF_ATA_DIOW (GPIO_PORTF | GPIO_AF | 19) 136#define PF17_AF_ATA_CS0 (GPIO_PORTF | GPIO_AF | 17)
142#define PF20_AF_ATA_DIOR (GPIO_PORTF | GPIO_AF | 20) 137#define PF18_AF_ATA_CS1 (GPIO_PORTF | GPIO_AF | 18)
143#define PF22_AF_ETMTRACE_CLK (GPIO_PORTF | GPIO_AF | 22) 138#define PF19_AF_ATA_DIOW (GPIO_PORTF | GPIO_AF | 19)
144#define PF23_AF_ETMTRACE_PKT4 (GPIO_PORTF | GPIO_AF | 23) 139#define PF20_AF_ATA_DIOR (GPIO_PORTF | GPIO_AF | 20)
140#define PF22_AF_ETMTRACE_CLK (GPIO_PORTF | GPIO_AF | 22)
141#define PF23_AF_ETMTRACE_PKT4 (GPIO_PORTF | GPIO_AF | 23)
145 142
146/* AIN GPIO pin functions */ 143/* AIN GPIO pin functions */
147 144
148#define PC14_AIN_SSI1_MCLK (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 14) 145#define PC14_AIN_SSI1_MCLK (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 14)
149#define PC15_AIN_GPT6_TOUT (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 15) 146#define PC15_AIN_GPT6_TOUT (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 15)
150#define PD0_AIN_FEC_TXD0 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 0) 147#define PD0_AIN_FEC_TXD0 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 0)
151#define PD1_AIN_FEC_TXD1 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 1) 148#define PD1_AIN_FEC_TXD1 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 1)
152#define PD2_AIN_FEC_TXD2 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 2) 149#define PD2_AIN_FEC_TXD2 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 2)
153#define PD3_AIN_FEC_TXD3 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 3) 150#define PD3_AIN_FEC_TXD3 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 3)
154#define PD9_AIN_FEC_MDC (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 9) 151#define PD9_AIN_FEC_MDC (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 9)
155#define PD16_AIN_FEC_TX_ER (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 16) 152#define PD16_AIN_FEC_TX_ER (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 16)
156#define PD27_AIN_EXT_DMA_GRANT (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 27) 153#define PD27_AIN_EXT_DMA_GRANT (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 27)
157#define PF23_AIN_FEC_TX_EN (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 23) 154#define PF23_AIN_FEC_TX_EN (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 23)
158 155
159/* BIN GPIO pin functions */ 156/* BIN GPIO pin functions */
160 157
161#define PC14_BIN_SSI2_MCLK (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 14) 158#define PC14_BIN_SSI2_MCLK (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 14)
162 159
163/* CIN GPIO pin functions */ 160/* CIN GPIO pin functions */
164 161
165#define PD2_CIN_SLCDC1_DAT0 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 2) 162#define PD2_CIN_SLCDC1_DAT0 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 2)
166#define PD3_CIN_SLCDC1_DAT1 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 3) 163#define PD3_CIN_SLCDC1_DAT1 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 3)
167#define PD4_CIN_SLCDC1_DAT2 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 4) 164#define PD4_CIN_SLCDC1_DAT2 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 4)
168#define PD5_CIN_SLCDC1_DAT3 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 5) 165#define PD5_CIN_SLCDC1_DAT3 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 5)
169#define PD6_CIN_SLCDC1_DAT4 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 6) 166#define PD6_CIN_SLCDC1_DAT4 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 6)
170#define PD7_CIN_SLCDC1_DAT5 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 7) 167#define PD7_CIN_SLCDC1_DAT5 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 7)
171#define PD8_CIN_SLCDC1_DAT6 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 8) 168#define PD8_CIN_SLCDC1_DAT6 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 8)
172#define PD9_CIN_SLCDC1_DAT7 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 9) 169#define PD9_CIN_SLCDC1_DAT7 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 9)
173#define PD10_CIN_SLCDC1_DAT8 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 10) 170#define PD10_CIN_SLCDC1_DAT8 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 10)
174#define PD11_CIN_SLCDC1_DAT9 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 11) 171#define PD11_CIN_SLCDC1_DAT9 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 11)
175#define PD12_CIN_SLCDC1_DAT10 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 12) 172#define PD12_CIN_SLCDC1_DAT10 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 12)
176#define PD13_CIN_SLCDC1_DAT11 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 13) 173#define PD13_CIN_SLCDC1_DAT11 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 13)
177#define PD14_CIN_SLCDC1_DAT12 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 14) 174#define PD14_CIN_SLCDC1_DAT12 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 14)
178#define PD15_CIN_SLCDC1_DAT13 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 15) 175#define PD15_CIN_SLCDC1_DAT13 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 15)
179#define PD16_CIN_SLCDC1_DAT14 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 16) 176#define PD16_CIN_SLCDC1_DAT14 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 16)
180#define PD23_CIN_SLCDC1_DAT15 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 23) 177#define PD23_CIN_SLCDC1_DAT15 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 23)
181#define PF27_CIN_EXT_DMA_GRANT (GPIO_PORTF | GPIO_CIN | GPIO_OUT | 27) 178#define PF27_CIN_EXT_DMA_GRANT (GPIO_PORTF | GPIO_CIN | GPIO_OUT | 27)
182/* LCDC_TESTx on PBxx omitted, because it's not clear what they do */ 179/* LCDC_TESTx on PBxx omitted, because it's not clear what they do */
183 180
184/* AOUT GPIO pin functions */ 181/* AOUT GPIO pin functions */
185 182
186#define PC14_AOUT_GPT6_TIN (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 14) 183#define PC14_AOUT_GPT6_TIN (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 14)
187#define PD4_AOUT_FEC_RX_ER (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 4) 184#define PD4_AOUT_FEC_RX_ER (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 4)
188#define PD5_AOUT_FEC_RXD1 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 5) 185#define PD5_AOUT_FEC_RXD1 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 5)
189#define PD6_AOUT_FEC_RXD2 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 6) 186#define PD6_AOUT_FEC_RXD2 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 6)
190#define PD7_AOUT_FEC_RXD3 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 7) 187#define PD7_AOUT_FEC_RXD3 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 7)
191#define PD10_AOUT_FEC_CRS (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 10) 188#define PD10_AOUT_FEC_CRS (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 10)
192#define PD11_AOUT_FEC_TX_CLK (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 11) 189#define PD11_AOUT_FEC_TX_CLK (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 11)
193#define PD12_AOUT_FEC_RXD0 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 12) 190#define PD12_AOUT_FEC_RXD0 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 12)
194#define PD13_AOUT_FEC_RX_DV (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 13) 191#define PD13_AOUT_FEC_RX_DV (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 13)
195#define PD14_AOUT_FEC_RX_CLK (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 14) 192#define PD14_AOUT_FEC_RX_CLK (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 14)
196#define PD15_AOUT_FEC_COL (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 15) 193#define PD15_AOUT_FEC_COL (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 15)
197 194
198#define PC17_BOUT_PC_IOIS16 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 17) 195/* BOUT GPIO pin functions */
199#define PC18_BOUT_PC_BVD2 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 18) 196
200#define PC19_BOUT_PC_BVD1 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 19) 197#define PC17_BOUT_PC_IOIS16 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 17)
201#define PC28_BOUT_PC_BVD2 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 28) 198#define PC18_BOUT_PC_BVD2 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 18)
202#define PC29_BOUT_PC_VS1 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 29) 199#define PC19_BOUT_PC_BVD1 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 19)
203#define PC30_BOUT_PC_READY (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 30) 200#define PC28_BOUT_PC_BVD2 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 28)
204#define PC31_BOUT_PC_WAIT (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 31) 201#define PC29_BOUT_PC_VS1 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 29)
205 202#define PC30_BOUT_PC_READY (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 30)
206 203#define PC31_BOUT_PC_WAIT (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 31)
207#endif /* _MXC_GPIO_MX1_MX2_H */ 204
205#endif /* __MACH_IOMUX_MX27_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx2x.h b/arch/arm/plat-mxc/include/mach/iomux-mx2x.h
index fb5ae638e79f..c4f116d214f2 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx2x.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx2x.h
@@ -1,237 +1,230 @@
1/* 1/*
2* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> 2 * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
3* Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de> 3 * Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de>
4* 4 *
5* This program is free software; you can redistribute it and/or 5 * This program is free software; you can redistribute it and/or
6* modify it under the terms of the GNU General Public License 6 * modify it under the terms of the GNU General Public License
7* as published by the Free Software Foundation; either version 2 7 * as published by the Free Software Foundation; either version 2
8* of the License, or (at your option) any later version. 8 * of the License, or (at your option) any later version.
9* This program is distributed in the hope that it will be useful, 9 * This program is distributed in the hope that it will be useful,
10* but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12* GNU General Public License for more details. 12 * GNU General Public License for more details.
13* 13 *
14* You should have received a copy of the GNU General Public License 14 * You should have received a copy of the GNU General Public License
15* along with this program; if not, write to the Free Software 15 * along with this program; if not, write to the Free Software
16* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17* MA 02110-1301, USA. 17 * MA 02110-1301, USA.
18*/ 18 */
19 19#ifndef __MACH_IOMUX_MX2x_H__
20#ifndef _MXC_IOMUX_MX2x_H 20#define __MACH_IOMUX_MX2x_H__
21#define _MXC_IOMUX_MX2x_H
22
23#ifndef GPIO_PORTA
24#error Please include mach/iomux.h
25#endif
26
27 21
28/* Primary GPIO pin functions */ 22/* Primary GPIO pin functions */
29 23
30#define PA5_PF_LSCLK (GPIO_PORTA | GPIO_PF | GPIO_OUT | 5) 24#define PA5_PF_LSCLK (GPIO_PORTA | GPIO_PF | GPIO_OUT | 5)
31#define PA6_PF_LD0 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 6) 25#define PA6_PF_LD0 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 6)
32#define PA7_PF_LD1 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 7) 26#define PA7_PF_LD1 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 7)
33#define PA8_PF_LD2 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 8) 27#define PA8_PF_LD2 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 8)
34#define PA9_PF_LD3 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 9) 28#define PA9_PF_LD3 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 9)
35#define PA10_PF_LD4 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 10) 29#define PA10_PF_LD4 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 10)
36#define PA11_PF_LD5 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 11) 30#define PA11_PF_LD5 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 11)
37#define PA12_PF_LD6 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 12) 31#define PA12_PF_LD6 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 12)
38#define PA13_PF_LD7 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 13) 32#define PA13_PF_LD7 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 13)
39#define PA14_PF_LD8 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 14) 33#define PA14_PF_LD8 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 14)
40#define PA15_PF_LD9 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 15) 34#define PA15_PF_LD9 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 15)
41#define PA16_PF_LD10 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 16) 35#define PA16_PF_LD10 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 16)
42#define PA17_PF_LD11 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 17) 36#define PA17_PF_LD11 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 17)
43#define PA18_PF_LD12 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 18) 37#define PA18_PF_LD12 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 18)
44#define PA19_PF_LD13 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 19) 38#define PA19_PF_LD13 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 19)
45#define PA20_PF_LD14 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 20) 39#define PA20_PF_LD14 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 20)
46#define PA21_PF_LD15 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 21) 40#define PA21_PF_LD15 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 21)
47#define PA22_PF_LD16 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 22) 41#define PA22_PF_LD16 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 22)
48#define PA23_PF_LD17 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 23) 42#define PA23_PF_LD17 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 23)
49#define PA24_PF_REV (GPIO_PORTA | GPIO_PF | GPIO_OUT | 24) 43#define PA24_PF_REV (GPIO_PORTA | GPIO_PF | GPIO_OUT | 24)
50#define PA25_PF_CLS (GPIO_PORTA | GPIO_PF | GPIO_OUT | 25) 44#define PA25_PF_CLS (GPIO_PORTA | GPIO_PF | GPIO_OUT | 25)
51#define PA26_PF_PS (GPIO_PORTA | GPIO_PF | GPIO_OUT | 26) 45#define PA26_PF_PS (GPIO_PORTA | GPIO_PF | GPIO_OUT | 26)
52#define PA27_PF_SPL_SPR (GPIO_PORTA | GPIO_PF | GPIO_OUT | 27) 46#define PA27_PF_SPL_SPR (GPIO_PORTA | GPIO_PF | GPIO_OUT | 27)
53#define PA28_PF_HSYNC (GPIO_PORTA | GPIO_PF | GPIO_OUT | 28) 47#define PA28_PF_HSYNC (GPIO_PORTA | GPIO_PF | GPIO_OUT | 28)
54#define PA29_PF_VSYNC (GPIO_PORTA | GPIO_PF | GPIO_OUT | 29) 48#define PA29_PF_VSYNC (GPIO_PORTA | GPIO_PF | GPIO_OUT | 29)
55#define PA30_PF_CONTRAST (GPIO_PORTA | GPIO_PF | GPIO_OUT | 30) 49#define PA30_PF_CONTRAST (GPIO_PORTA | GPIO_PF | GPIO_OUT | 30)
56#define PA31_PF_OE_ACD (GPIO_PORTA | GPIO_PF | GPIO_OUT | 31) 50#define PA31_PF_OE_ACD (GPIO_PORTA | GPIO_PF | GPIO_OUT | 31)
57#define PB4_PF_SD2_D0 (GPIO_PORTB | GPIO_PF | 4) 51#define PB4_PF_SD2_D0 (GPIO_PORTB | GPIO_PF | 4)
58#define PB5_PF_SD2_D1 (GPIO_PORTB | GPIO_PF | 5) 52#define PB5_PF_SD2_D1 (GPIO_PORTB | GPIO_PF | 5)
59#define PB6_PF_SD2_D2 (GPIO_PORTB | GPIO_PF | 6) 53#define PB6_PF_SD2_D2 (GPIO_PORTB | GPIO_PF | 6)
60#define PB7_PF_SD2_D3 (GPIO_PORTB | GPIO_PF | 7) 54#define PB7_PF_SD2_D3 (GPIO_PORTB | GPIO_PF | 7)
61#define PB8_PF_SD2_CMD (GPIO_PORTB | GPIO_PF | 8) 55#define PB8_PF_SD2_CMD (GPIO_PORTB | GPIO_PF | 8)
62#define PB9_PF_SD2_CLK (GPIO_PORTB | GPIO_PF | 9) 56#define PB9_PF_SD2_CLK (GPIO_PORTB | GPIO_PF | 9)
63#define PB10_PF_CSI_D0 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 10) 57#define PB10_PF_CSI_D0 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 10)
64#define PB11_PF_CSI_D1 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 11) 58#define PB11_PF_CSI_D1 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 11)
65#define PB12_PF_CSI_D2 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 12) 59#define PB12_PF_CSI_D2 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 12)
66#define PB13_PF_CSI_D3 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 13) 60#define PB13_PF_CSI_D3 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 13)
67#define PB14_PF_CSI_D4 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 14) 61#define PB14_PF_CSI_D4 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 14)
68#define PB15_PF_CSI_MCLK (GPIO_PORTB | GPIO_PF | GPIO_OUT | 15) 62#define PB15_PF_CSI_MCLK (GPIO_PORTB | GPIO_PF | GPIO_OUT | 15)
69#define PB16_PF_CSI_PIXCLK (GPIO_PORTB | GPIO_PF | GPIO_OUT | 16) 63#define PB16_PF_CSI_PIXCLK (GPIO_PORTB | GPIO_PF | GPIO_OUT | 16)
70#define PB17_PF_CSI_D5 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 17) 64#define PB17_PF_CSI_D5 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 17)
71#define PB18_PF_CSI_D6 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 18) 65#define PB18_PF_CSI_D6 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 18)
72#define PB19_PF_CSI_D7 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 19) 66#define PB19_PF_CSI_D7 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 19)
73#define PB20_PF_CSI_VSYNC (GPIO_PORTB | GPIO_PF | GPIO_OUT | 20) 67#define PB20_PF_CSI_VSYNC (GPIO_PORTB | GPIO_PF | GPIO_OUT | 20)
74#define PB21_PF_CSI_HSYNC (GPIO_PORTB | GPIO_PF | GPIO_OUT | 21) 68#define PB21_PF_CSI_HSYNC (GPIO_PORTB | GPIO_PF | GPIO_OUT | 21)
75#define PB23_PF_USB_PWR (GPIO_PORTB | GPIO_PF | 23) 69#define PB23_PF_USB_PWR (GPIO_PORTB | GPIO_PF | 23)
76#define PB24_PF_USB_OC (GPIO_PORTB | GPIO_PF | 24) 70#define PB24_PF_USB_OC (GPIO_PORTB | GPIO_PF | 24)
77#define PB26_PF_USBH1_FS (GPIO_PORTB | GPIO_PF | 26) 71#define PB26_PF_USBH1_FS (GPIO_PORTB | GPIO_PF | 26)
78#define PB27_PF_USBH1_OE (GPIO_PORTB | GPIO_PF | 27) 72#define PB27_PF_USBH1_OE (GPIO_PORTB | GPIO_PF | 27)
79#define PB28_PF_USBH1_TXDM (GPIO_PORTB | GPIO_PF | 28) 73#define PB28_PF_USBH1_TXDM (GPIO_PORTB | GPIO_PF | 28)
80#define PB29_PF_USBH1_TXDP (GPIO_PORTB | GPIO_PF | 29) 74#define PB29_PF_USBH1_TXDP (GPIO_PORTB | GPIO_PF | 29)
81#define PB30_PF_USBH1_RXDM (GPIO_PORTB | GPIO_PF | 30) 75#define PB30_PF_USBH1_RXDM (GPIO_PORTB | GPIO_PF | 30)
82#define PB31_PF_USBH1_RXDP (GPIO_PORTB | GPIO_PF | 31) 76#define PB31_PF_USBH1_RXDP (GPIO_PORTB | GPIO_PF | 31)
83#define PC14_PF_TOUT (GPIO_PORTC | GPIO_PF | 14) 77#define PC14_PF_TOUT (GPIO_PORTC | GPIO_PF | 14)
84#define PC15_PF_TIN (GPIO_PORTC | GPIO_PF | 15) 78#define PC15_PF_TIN (GPIO_PORTC | GPIO_PF | 15)
85#define PC20_PF_SSI1_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 20) 79#define PC20_PF_SSI1_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 20)
86#define PC21_PF_SSI1_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 21) 80#define PC21_PF_SSI1_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 21)
87#define PC22_PF_SSI1_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 22) 81#define PC22_PF_SSI1_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 22)
88#define PC23_PF_SSI1_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 23) 82#define PC23_PF_SSI1_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 23)
89#define PC24_PF_SSI2_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 24) 83#define PC24_PF_SSI2_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 24)
90#define PC25_PF_SSI2_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 25) 84#define PC25_PF_SSI2_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 25)
91#define PC26_PF_SSI2_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 26) 85#define PC26_PF_SSI2_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 26)
92#define PC27_PF_SSI2_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 27) 86#define PC27_PF_SSI2_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 27)
93#define PC28_PF_SSI3_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 28) 87#define PC28_PF_SSI3_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 28)
94#define PC29_PF_SSI3_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 29) 88#define PC29_PF_SSI3_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 29)
95#define PC30_PF_SSI3_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 30) 89#define PC30_PF_SSI3_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 30)
96#define PC31_PF_SSI3_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 31) 90#define PC31_PF_SSI3_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 31)
97#define PD17_PF_I2C_DATA (GPIO_PORTD | GPIO_PF | GPIO_OUT | 17) 91#define PD17_PF_I2C_DATA (GPIO_PORTD | GPIO_PF | GPIO_OUT | 17)
98#define PD18_PF_I2C_CLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 18) 92#define PD18_PF_I2C_CLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 18)
99#define PD19_PF_CSPI2_SS2 (GPIO_PORTD | GPIO_PF | 19) 93#define PD19_PF_CSPI2_SS2 (GPIO_PORTD | GPIO_PF | 19)
100#define PD20_PF_CSPI2_SS1 (GPIO_PORTD | GPIO_PF | 20) 94#define PD20_PF_CSPI2_SS1 (GPIO_PORTD | GPIO_PF | 20)
101#define PD21_PF_CSPI2_SS0 (GPIO_PORTD | GPIO_PF | 21) 95#define PD21_PF_CSPI2_SS0 (GPIO_PORTD | GPIO_PF | 21)
102#define PD22_PF_CSPI2_SCLK (GPIO_PORTD | GPIO_PF | 22) 96#define PD22_PF_CSPI2_SCLK (GPIO_PORTD | GPIO_PF | 22)
103#define PD23_PF_CSPI2_MISO (GPIO_PORTD | GPIO_PF | 23) 97#define PD23_PF_CSPI2_MISO (GPIO_PORTD | GPIO_PF | 23)
104#define PD24_PF_CSPI2_MOSI (GPIO_PORTD | GPIO_PF | 24) 98#define PD24_PF_CSPI2_MOSI (GPIO_PORTD | GPIO_PF | 24)
105#define PD25_PF_CSPI1_RDY (GPIO_PORTD | GPIO_PF | GPIO_OUT | 25) 99#define PD25_PF_CSPI1_RDY (GPIO_PORTD | GPIO_PF | GPIO_OUT | 25)
106#define PD26_PF_CSPI1_SS2 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 26) 100#define PD26_PF_CSPI1_SS2 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 26)
107#define PD27_PF_CSPI1_SS1 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 27) 101#define PD27_PF_CSPI1_SS1 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 27)
108#define PD28_PF_CSPI1_SS0 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 28) 102#define PD28_PF_CSPI1_SS0 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 28)
109#define PD29_PF_CSPI1_SCLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 29) 103#define PD29_PF_CSPI1_SCLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 29)
110#define PD30_PF_CSPI1_MISO (GPIO_PORTD | GPIO_PF | GPIO_IN | 30) 104#define PD30_PF_CSPI1_MISO (GPIO_PORTD | GPIO_PF | GPIO_IN | 30)
111#define PD31_PF_CSPI1_MOSI (GPIO_PORTD | GPIO_PF | GPIO_OUT | 31) 105#define PD31_PF_CSPI1_MOSI (GPIO_PORTD | GPIO_PF | GPIO_OUT | 31)
112#define PE3_PF_UART2_CTS (GPIO_PORTE | GPIO_PF | GPIO_OUT | 3) 106#define PE3_PF_UART2_CTS (GPIO_PORTE | GPIO_PF | GPIO_OUT | 3)
113#define PE4_PF_UART2_RTS (GPIO_PORTE | GPIO_PF | GPIO_IN | 4) 107#define PE4_PF_UART2_RTS (GPIO_PORTE | GPIO_PF | GPIO_IN | 4)
114#define PE5_PF_PWMO (GPIO_PORTE | GPIO_PF | 5) 108#define PE5_PF_PWMO (GPIO_PORTE | GPIO_PF | 5)
115#define PE6_PF_UART2_TXD (GPIO_PORTE | GPIO_PF | GPIO_OUT | 6) 109#define PE6_PF_UART2_TXD (GPIO_PORTE | GPIO_PF | GPIO_OUT | 6)
116#define PE7_PF_UART2_RXD (GPIO_PORTE | GPIO_PF | GPIO_IN | 7) 110#define PE7_PF_UART2_RXD (GPIO_PORTE | GPIO_PF | GPIO_IN | 7)
117#define PE8_PF_UART3_TXD (GPIO_PORTE | GPIO_PF | GPIO_OUT | 8) 111#define PE8_PF_UART3_TXD (GPIO_PORTE | GPIO_PF | GPIO_OUT | 8)
118#define PE9_PF_UART3_RXD (GPIO_PORTE | GPIO_PF | GPIO_IN | 9) 112#define PE9_PF_UART3_RXD (GPIO_PORTE | GPIO_PF | GPIO_IN | 9)
119#define PE10_PF_UART3_CTS (GPIO_PORTE | GPIO_PF | GPIO_OUT | 10) 113#define PE10_PF_UART3_CTS (GPIO_PORTE | GPIO_PF | GPIO_OUT | 10)
120#define PE11_PF_UART3_RTS (GPIO_PORTE | GPIO_PF | GPIO_IN | 11) 114#define PE11_PF_UART3_RTS (GPIO_PORTE | GPIO_PF | GPIO_IN | 11)
121#define PE12_PF_UART1_TXD (GPIO_PORTE | GPIO_PF | GPIO_OUT | 12) 115#define PE12_PF_UART1_TXD (GPIO_PORTE | GPIO_PF | GPIO_OUT | 12)
122#define PE13_PF_UART1_RXD (GPIO_PORTE | GPIO_PF | GPIO_IN | 13) 116#define PE13_PF_UART1_RXD (GPIO_PORTE | GPIO_PF | GPIO_IN | 13)
123#define PE14_PF_UART1_CTS (GPIO_PORTE | GPIO_PF | GPIO_OUT | 14) 117#define PE14_PF_UART1_CTS (GPIO_PORTE | GPIO_PF | GPIO_OUT | 14)
124#define PE15_PF_UART1_RTS (GPIO_PORTE | GPIO_PF | GPIO_IN | 15) 118#define PE15_PF_UART1_RTS (GPIO_PORTE | GPIO_PF | GPIO_IN | 15)
125#define PE16_PF_RTCK (GPIO_PORTE | GPIO_PF | GPIO_OUT | 16) 119#define PE16_PF_RTCK (GPIO_PORTE | GPIO_PF | GPIO_OUT | 16)
126#define PE17_PF_RESET_OUT (GPIO_PORTE | GPIO_PF | 17) 120#define PE17_PF_RESET_OUT (GPIO_PORTE | GPIO_PF | 17)
127#define PE18_PF_SD1_D0 (GPIO_PORTE | GPIO_PF | 18) 121#define PE18_PF_SD1_D0 (GPIO_PORTE | GPIO_PF | 18)
128#define PE19_PF_SD1_D1 (GPIO_PORTE | GPIO_PF | 19) 122#define PE19_PF_SD1_D1 (GPIO_PORTE | GPIO_PF | 19)
129#define PE20_PF_SD1_D2 (GPIO_PORTE | GPIO_PF | 20) 123#define PE20_PF_SD1_D2 (GPIO_PORTE | GPIO_PF | 20)
130#define PE21_PF_SD1_D3 (GPIO_PORTE | GPIO_PF | 21) 124#define PE21_PF_SD1_D3 (GPIO_PORTE | GPIO_PF | 21)
131#define PE22_PF_SD1_CMD (GPIO_PORTE | GPIO_PF | 22) 125#define PE22_PF_SD1_CMD (GPIO_PORTE | GPIO_PF | 22)
132#define PE23_PF_SD1_CLK (GPIO_PORTE | GPIO_PF | 23) 126#define PE23_PF_SD1_CLK (GPIO_PORTE | GPIO_PF | 23)
133#define PF0_PF_NRFB (GPIO_PORTF | GPIO_PF | 0) 127#define PF0_PF_NRFB (GPIO_PORTF | GPIO_PF | 0)
134#define PF2_PF_NFWP (GPIO_PORTF | GPIO_PF | 2) 128#define PF2_PF_NFWP (GPIO_PORTF | GPIO_PF | 2)
135#define PF4_PF_NFALE (GPIO_PORTF | GPIO_PF | 4) 129#define PF4_PF_NFALE (GPIO_PORTF | GPIO_PF | 4)
136#define PF5_PF_NFRE (GPIO_PORTF | GPIO_PF | 5) 130#define PF5_PF_NFRE (GPIO_PORTF | GPIO_PF | 5)
137#define PF6_PF_NFWE (GPIO_PORTF | GPIO_PF | 6) 131#define PF6_PF_NFWE (GPIO_PORTF | GPIO_PF | 6)
138#define PF15_PF_CLKO (GPIO_PORTF | GPIO_PF | 15) 132#define PF15_PF_CLKO (GPIO_PORTF | GPIO_PF | 15)
139#define PF21_PF_CS4 (GPIO_PORTF | GPIO_PF | 21) 133#define PF21_PF_CS4 (GPIO_PORTF | GPIO_PF | 21)
140#define PF22_PF_CS5 (GPIO_PORTF | GPIO_PF | 22) 134#define PF22_PF_CS5 (GPIO_PORTF | GPIO_PF | 22)
141 135
142/* Alternate GPIO pin functions */ 136/* Alternate GPIO pin functions */
143 137
144#define PB26_AF_UART4_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 26) 138#define PB26_AF_UART4_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 26)
145#define PB28_AF_UART4_TXD (GPIO_PORTB | GPIO_AF | GPIO_OUT | 28) 139#define PB28_AF_UART4_TXD (GPIO_PORTB | GPIO_AF | GPIO_OUT | 28)
146#define PB29_AF_UART4_CTS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 29) 140#define PB29_AF_UART4_CTS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 29)
147#define PB31_AF_UART4_RXD (GPIO_PORTB | GPIO_AF | GPIO_IN | 31) 141#define PB31_AF_UART4_RXD (GPIO_PORTB | GPIO_AF | GPIO_IN | 31)
148#define PC28_AF_SLCDC2_D0 (GPIO_PORTC | GPIO_AF | 28) 142#define PC28_AF_SLCDC2_D0 (GPIO_PORTC | GPIO_AF | 28)
149#define PC29_AF_SLCDC2_RS (GPIO_PORTC | GPIO_AF | 29) 143#define PC29_AF_SLCDC2_RS (GPIO_PORTC | GPIO_AF | 29)
150#define PC30_AF_SLCDC2_CS (GPIO_PORTC | GPIO_AF | 30) 144#define PC30_AF_SLCDC2_CS (GPIO_PORTC | GPIO_AF | 30)
151#define PC31_AF_SLCDC2_CLK (GPIO_PORTC | GPIO_AF | 31) 145#define PC31_AF_SLCDC2_CLK (GPIO_PORTC | GPIO_AF | 31)
152#define PD19_AF_USBH2_DATA4 (GPIO_PORTD | GPIO_AF | 19) 146#define PD19_AF_USBH2_DATA4 (GPIO_PORTD | GPIO_AF | 19)
153#define PD20_AF_USBH2_DATA3 (GPIO_PORTD | GPIO_AF | 20) 147#define PD20_AF_USBH2_DATA3 (GPIO_PORTD | GPIO_AF | 20)
154#define PD21_AF_USBH2_DATA6 (GPIO_PORTD | GPIO_AF | 21) 148#define PD21_AF_USBH2_DATA6 (GPIO_PORTD | GPIO_AF | 21)
155#define PD22_AF_USBH2_DATA0 (GPIO_PORTD | GPIO_AF | 22) 149#define PD22_AF_USBH2_DATA0 (GPIO_PORTD | GPIO_AF | 22)
156#define PD23_AF_USBH2_DATA2 (GPIO_PORTD | GPIO_AF | 23) 150#define PD23_AF_USBH2_DATA2 (GPIO_PORTD | GPIO_AF | 23)
157#define PD24_AF_USBH2_DATA1 (GPIO_PORTD | GPIO_AF | 24) 151#define PD24_AF_USBH2_DATA1 (GPIO_PORTD | GPIO_AF | 24)
158#define PD26_AF_USBH2_DATA5 (GPIO_PORTD | GPIO_AF | 26) 152#define PD26_AF_USBH2_DATA5 (GPIO_PORTD | GPIO_AF | 26)
159#define PE0_AF_KP_COL6 (GPIO_PORTE | GPIO_AF | 0) 153#define PE0_AF_KP_COL6 (GPIO_PORTE | GPIO_AF | 0)
160#define PE1_AF_KP_ROW6 (GPIO_PORTE | GPIO_AF | 1) 154#define PE1_AF_KP_ROW6 (GPIO_PORTE | GPIO_AF | 1)
161#define PE2_AF_KP_ROW7 (GPIO_PORTE | GPIO_AF | 2) 155#define PE2_AF_KP_ROW7 (GPIO_PORTE | GPIO_AF | 2)
162#define PE3_AF_KP_COL7 (GPIO_PORTE | GPIO_AF | 3) 156#define PE3_AF_KP_COL7 (GPIO_PORTE | GPIO_AF | 3)
163#define PE4_AF_KP_ROW7 (GPIO_PORTE | GPIO_AF | 4) 157#define PE4_AF_KP_ROW7 (GPIO_PORTE | GPIO_AF | 4)
164#define PE6_AF_KP_COL6 (GPIO_PORTE | GPIO_AF | 6) 158#define PE6_AF_KP_COL6 (GPIO_PORTE | GPIO_AF | 6)
165#define PE7_AF_KP_ROW6 (GPIO_PORTE | GPIO_AF | 7) 159#define PE7_AF_KP_ROW6 (GPIO_PORTE | GPIO_AF | 7)
166#define PE16_AF_OWIRE (GPIO_PORTE | GPIO_AF | 16) 160#define PE16_AF_OWIRE (GPIO_PORTE | GPIO_AF | 16)
167#define PE18_AF_CSPI3_MISO (GPIO_PORTE | GPIO_AF | GPIO_IN | 18) 161#define PE18_AF_CSPI3_MISO (GPIO_PORTE | GPIO_AF | GPIO_IN | 18)
168#define PE21_AF_CSPI3_SS (GPIO_PORTE | GPIO_AF | GPIO_OUT | 21) 162#define PE21_AF_CSPI3_SS (GPIO_PORTE | GPIO_AF | GPIO_OUT | 21)
169#define PE22_AF_CSPI3_MOSI (GPIO_PORTE | GPIO_AF | GPIO_OUT | 22) 163#define PE22_AF_CSPI3_MOSI (GPIO_PORTE | GPIO_AF | GPIO_OUT | 22)
170#define PE23_AF_CSPI3_SCLK (GPIO_PORTE | GPIO_AF | GPIO_OUT | 23) 164#define PE23_AF_CSPI3_SCLK (GPIO_PORTE | GPIO_AF | GPIO_OUT | 23)
171 165
172/* AIN GPIO pin functions */ 166/* AIN GPIO pin functions */
173 167
174#define PA6_AIN_SLCDC1_DAT0 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 6) 168#define PA6_AIN_SLCDC1_DAT0 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 6)
175#define PA7_AIN_SLCDC1_DAT1 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 7) 169#define PA7_AIN_SLCDC1_DAT1 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 7)
176#define PA8_AIN_SLCDC1_DAT2 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 8) 170#define PA8_AIN_SLCDC1_DAT2 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 8)
177#define PA0_AIN_SLCDC1_DAT3 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 0) 171#define PA0_AIN_SLCDC1_DAT3 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 0)
178#define PA11_AIN_SLCDC1_DAT5 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 11) 172#define PA11_AIN_SLCDC1_DAT5 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 11)
179#define PA13_AIN_SLCDC1_DAT7 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 13) 173#define PA13_AIN_SLCDC1_DAT7 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 13)
180#define PA15_AIN_SLCDC1_DAT9 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 15) 174#define PA15_AIN_SLCDC1_DAT9 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 15)
181#define PA17_AIN_SLCDC1_DAT11 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 17) 175#define PA17_AIN_SLCDC1_DAT11 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 17)
182#define PA19_AIN_SLCDC1_DAT13 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 19) 176#define PA19_AIN_SLCDC1_DAT13 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 19)
183#define PA21_AIN_SLCDC1_DAT15 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 21) 177#define PA21_AIN_SLCDC1_DAT15 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 21)
184#define PA22_AIN_EXT_DMAGRANT (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 22) 178#define PA22_AIN_EXT_DMAGRANT (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 22)
185#define PA24_AIN_SLCDC1_D0 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 24) 179#define PA24_AIN_SLCDC1_D0 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 24)
186#define PA25_AIN_SLCDC1_RS (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 25) 180#define PA25_AIN_SLCDC1_RS (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 25)
187#define PA26_AIN_SLCDC1_CS (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 26) 181#define PA26_AIN_SLCDC1_CS (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 26)
188#define PA27_AIN_SLCDC1_CLK (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 27) 182#define PA27_AIN_SLCDC1_CLK (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 27)
189#define PB6_AIN_SLCDC1_D0 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 6) 183#define PB6_AIN_SLCDC1_D0 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 6)
190#define PB7_AIN_SLCDC1_RS (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 7) 184#define PB7_AIN_SLCDC1_RS (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 7)
191#define PB8_AIN_SLCDC1_CS (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 8) 185#define PB8_AIN_SLCDC1_CS (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 8)
192#define PB9_AIN_SLCDC1_CLK (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 9) 186#define PB9_AIN_SLCDC1_CLK (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 9)
193#define PB25_AIN_SLCDC1_DAT0 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 25) 187#define PB25_AIN_SLCDC1_DAT0 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 25)
194#define PB26_AIN_SLCDC1_DAT1 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 26) 188#define PB26_AIN_SLCDC1_DAT1 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 26)
195#define PB27_AIN_SLCDC1_DAT2 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 27) 189#define PB27_AIN_SLCDC1_DAT2 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 27)
196#define PB28_AIN_SLCDC1_DAT3 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 28) 190#define PB28_AIN_SLCDC1_DAT3 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 28)
197#define PB29_AIN_SLCDC1_DAT4 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 29) 191#define PB29_AIN_SLCDC1_DAT4 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 29)
198#define PB30_AIN_SLCDC1_DAT5 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 30) 192#define PB30_AIN_SLCDC1_DAT5 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 30)
199#define PB31_AIN_SLCDC1_DAT6 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 31) 193#define PB31_AIN_SLCDC1_DAT6 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 31)
200#define PC5_AIN_SLCDC1_DAT7 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 5) 194#define PC5_AIN_SLCDC1_DAT7 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 5)
201#define PC6_AIN_SLCDC1_DAT8 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 6) 195#define PC6_AIN_SLCDC1_DAT8 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 6)
202#define PC7_AIN_SLCDC1_DAT9 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 7) 196#define PC7_AIN_SLCDC1_DAT9 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 7)
203#define PC8_AIN_SLCDC1_DAT10 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 8) 197#define PC8_AIN_SLCDC1_DAT10 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 8)
204#define PC9_AIN_SLCDC1_DAT11 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 9) 198#define PC9_AIN_SLCDC1_DAT11 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 9)
205#define PC10_AIN_SLCDC1_DAT12 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 10) 199#define PC10_AIN_SLCDC1_DAT12 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 10)
206#define PC11_AIN_SLCDC1_DAT13 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 11) 200#define PC11_AIN_SLCDC1_DAT13 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 11)
207#define PC12_AIN_SLCDC1_DAT14 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 12) 201#define PC12_AIN_SLCDC1_DAT14 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 12)
208#define PC13_AIN_SLCDC1_DAT15 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 13) 202#define PC13_AIN_SLCDC1_DAT15 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 13)
209#define PE5_AIN_PC_SPKOUT (GPIO_PORTE | GPIO_AIN | GPIO_OUT | 5) 203#define PE5_AIN_PC_SPKOUT (GPIO_PORTE | GPIO_AIN | GPIO_OUT | 5)
210 204
211/* BIN GPIO pin functions */ 205/* BIN GPIO pin functions */
212 206
213#define PE5_BIN_TOUT2 (GPIO_PORTE | GPIO_BIN | GPIO_OUT | 5) 207#define PE5_BIN_TOUT2 (GPIO_PORTE | GPIO_BIN | GPIO_OUT | 5)
214 208
215/* CIN GPIO pin functions */ 209/* CIN GPIO pin functions */
216 210
217#define PA14_CIN_SLCDC1_DAT0 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 14) 211#define PA14_CIN_SLCDC1_DAT0 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 14)
218#define PA15_CIN_SLCDC1_DAT1 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 15) 212#define PA15_CIN_SLCDC1_DAT1 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 15)
219#define PA16_CIN_SLCDC1_DAT2 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 16) 213#define PA16_CIN_SLCDC1_DAT2 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 16)
220#define PA17_CIN_SLCDC1_DAT3 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 17) 214#define PA17_CIN_SLCDC1_DAT3 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 17)
221#define PA18_CIN_SLCDC1_DAT4 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 18) 215#define PA18_CIN_SLCDC1_DAT4 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 18)
222#define PA19_CIN_SLCDC1_DAT5 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 19) 216#define PA19_CIN_SLCDC1_DAT5 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 19)
223#define PA20_CIN_SLCDC1_DAT6 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 20) 217#define PA20_CIN_SLCDC1_DAT6 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 20)
224#define PA21_CIN_SLCDC1_DAT7 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 21) 218#define PA21_CIN_SLCDC1_DAT7 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 21)
225#define PB30_CIN_UART4_CTS (GPIO_PORTB | GPIO_CIN | GPIO_OUT | 30) 219#define PB30_CIN_UART4_CTS (GPIO_PORTB | GPIO_CIN | GPIO_OUT | 30)
226#define PE5_CIN_TOUT3 (GPIO_PORTE | GPIO_CIN | GPIO_OUT | 5) 220#define PE5_CIN_TOUT3 (GPIO_PORTE | GPIO_CIN | GPIO_OUT | 5)
227 221
228/* AOUT GPIO pin functions */ 222/* AOUT GPIO pin functions */
229 223
230#define PB29_AOUT_UART4_RXD (GPIO_PORTB | GPIO_AOUT | GPIO_IN | 29) 224#define PB29_AOUT_UART4_RXD (GPIO_PORTB | GPIO_AOUT | GPIO_IN | 29)
231#define PB31_AOUT_UART4_RTS (GPIO_PORTB | GPIO_AOUT | GPIO_IN | 31) 225#define PB31_AOUT_UART4_RTS (GPIO_PORTB | GPIO_AOUT | GPIO_IN | 31)
232#define PC8_AOUT_USBOTG_TXR_INT (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 8) 226#define PC8_AOUT_USBOTG_TXR_INT (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 8)
233#define PC15_AOUT_WKGD (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 15) 227#define PC15_AOUT_WKGD (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 15)
234#define PF21_AOUT_DTACK (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 21) 228#define PF21_AOUT_DTACK (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 21)
235
236 229
237#endif 230#endif /* ifndef __MACH_IOMUX_MX2x_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
index e1fc6da1cd10..e51465d7b224 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
@@ -16,12 +16,10 @@
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA. 17 * MA 02110-1301, USA.
18 */ 18 */
19 19#ifndef __MACH_IOMUX_MX3_H__
20#ifndef __MACH_MX31_IOMUX_H__ 20#define __MACH_IOMUX_MX3_H__
21#define __MACH_MX31_IOMUX_H__
22 21
23#include <linux/types.h> 22#include <linux/types.h>
24
25/* 23/*
26 * various IOMUX output functions 24 * various IOMUX output functions
27 */ 25 */
@@ -34,7 +32,7 @@
34#define IOMUX_OCONFIG_ALT4 (5 << 4) /* used as alternate function 4 */ 32#define IOMUX_OCONFIG_ALT4 (5 << 4) /* used as alternate function 4 */
35#define IOMUX_OCONFIG_ALT5 (6 << 4) /* used as alternate function 5 */ 33#define IOMUX_OCONFIG_ALT5 (6 << 4) /* used as alternate function 5 */
36#define IOMUX_OCONFIG_ALT6 (7 << 4) /* used as alternate function 6 */ 34#define IOMUX_OCONFIG_ALT6 (7 << 4) /* used as alternate function 6 */
37#define IOMUX_ICONFIG_NONE 0 /* not configured for input */ 35#define IOMUX_ICONFIG_NONE 0 /* not configured for input */
38#define IOMUX_ICONFIG_GPIO 1 /* used as GPIO */ 36#define IOMUX_ICONFIG_GPIO 1 /* used as GPIO */
39#define IOMUX_ICONFIG_FUNC 2 /* used as function */ 37#define IOMUX_ICONFIG_FUNC 2 /* used as function */
40#define IOMUX_ICONFIG_ALT1 4 /* used as alternate function 1 */ 38#define IOMUX_ICONFIG_ALT1 4 /* used as alternate function 1 */
@@ -167,11 +165,6 @@ int mxc_iomux_mode(unsigned int pin_mode);
167 MXC_GPIO_IRQ_START) 165 MXC_GPIO_IRQ_START)
168 166
169/* 167/*
170 * The number of gpio devices among the pads
171 */
172#define GPIO_PORT_MAX 3
173
174/*
175 * This enumeration is constructed based on the Section 168 * This enumeration is constructed based on the Section
176 * "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated 169 * "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated
177 * value is constructed based on the rules described above. 170 * value is constructed based on the rules described above.
@@ -633,40 +626,40 @@ enum iomux_pins {
633#define MX31_PIN_TXD2__GPIO1_28 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_GPIO) 626#define MX31_PIN_TXD2__GPIO1_28 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_GPIO)
634#define MX31_PIN_CSI_D4__GPIO3_4 IOMUX_MODE(MX31_PIN_CSI_D4, IOMUX_CONFIG_GPIO) 627#define MX31_PIN_CSI_D4__GPIO3_4 IOMUX_MODE(MX31_PIN_CSI_D4, IOMUX_CONFIG_GPIO)
635#define MX31_PIN_CSI_D5__GPIO3_5 IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_GPIO) 628#define MX31_PIN_CSI_D5__GPIO3_5 IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_GPIO)
636#define MX31_PIN_USBOTG_DATA0__USBOTG_DATA0 IOMUX_MODE(MX31_PIN_USBOTG_DATA0, IOMUX_CONFIG_FUNC) 629#define MX31_PIN_USBOTG_DATA0__USBOTG_DATA0 IOMUX_MODE(MX31_PIN_USBOTG_DATA0, IOMUX_CONFIG_FUNC)
637#define MX31_PIN_USBOTG_DATA1__USBOTG_DATA1 IOMUX_MODE(MX31_PIN_USBOTG_DATA1, IOMUX_CONFIG_FUNC) 630#define MX31_PIN_USBOTG_DATA1__USBOTG_DATA1 IOMUX_MODE(MX31_PIN_USBOTG_DATA1, IOMUX_CONFIG_FUNC)
638#define MX31_PIN_USBOTG_DATA2__USBOTG_DATA2 IOMUX_MODE(MX31_PIN_USBOTG_DATA2, IOMUX_CONFIG_FUNC) 631#define MX31_PIN_USBOTG_DATA2__USBOTG_DATA2 IOMUX_MODE(MX31_PIN_USBOTG_DATA2, IOMUX_CONFIG_FUNC)
639#define MX31_PIN_USBOTG_DATA3__USBOTG_DATA3 IOMUX_MODE(MX31_PIN_USBOTG_DATA3, IOMUX_CONFIG_FUNC) 632#define MX31_PIN_USBOTG_DATA3__USBOTG_DATA3 IOMUX_MODE(MX31_PIN_USBOTG_DATA3, IOMUX_CONFIG_FUNC)
640#define MX31_PIN_USBOTG_DATA4__USBOTG_DATA4 IOMUX_MODE(MX31_PIN_USBOTG_DATA4, IOMUX_CONFIG_FUNC) 633#define MX31_PIN_USBOTG_DATA4__USBOTG_DATA4 IOMUX_MODE(MX31_PIN_USBOTG_DATA4, IOMUX_CONFIG_FUNC)
641#define MX31_PIN_USBOTG_DATA5__USBOTG_DATA5 IOMUX_MODE(MX31_PIN_USBOTG_DATA5, IOMUX_CONFIG_FUNC) 634#define MX31_PIN_USBOTG_DATA5__USBOTG_DATA5 IOMUX_MODE(MX31_PIN_USBOTG_DATA5, IOMUX_CONFIG_FUNC)
642#define MX31_PIN_USBOTG_DATA6__USBOTG_DATA6 IOMUX_MODE(MX31_PIN_USBOTG_DATA6, IOMUX_CONFIG_FUNC) 635#define MX31_PIN_USBOTG_DATA6__USBOTG_DATA6 IOMUX_MODE(MX31_PIN_USBOTG_DATA6, IOMUX_CONFIG_FUNC)
643#define MX31_PIN_USBOTG_DATA7__USBOTG_DATA7 IOMUX_MODE(MX31_PIN_USBOTG_DATA7, IOMUX_CONFIG_FUNC) 636#define MX31_PIN_USBOTG_DATA7__USBOTG_DATA7 IOMUX_MODE(MX31_PIN_USBOTG_DATA7, IOMUX_CONFIG_FUNC)
644#define MX31_PIN_USBOTG_CLK__USBOTG_CLK IOMUX_MODE(MX31_PIN_USBOTG_CLK, IOMUX_CONFIG_FUNC) 637#define MX31_PIN_USBOTG_CLK__USBOTG_CLK IOMUX_MODE(MX31_PIN_USBOTG_CLK, IOMUX_CONFIG_FUNC)
645#define MX31_PIN_USBOTG_DIR__USBOTG_DIR IOMUX_MODE(MX31_PIN_USBOTG_DIR, IOMUX_CONFIG_FUNC) 638#define MX31_PIN_USBOTG_DIR__USBOTG_DIR IOMUX_MODE(MX31_PIN_USBOTG_DIR, IOMUX_CONFIG_FUNC)
646#define MX31_PIN_USBOTG_NXT__USBOTG_NXT IOMUX_MODE(MX31_PIN_USBOTG_NXT, IOMUX_CONFIG_FUNC) 639#define MX31_PIN_USBOTG_NXT__USBOTG_NXT IOMUX_MODE(MX31_PIN_USBOTG_NXT, IOMUX_CONFIG_FUNC)
647#define MX31_PIN_USBOTG_STP__USBOTG_STP IOMUX_MODE(MX31_PIN_USBOTG_STP, IOMUX_CONFIG_FUNC) 640#define MX31_PIN_USBOTG_STP__USBOTG_STP IOMUX_MODE(MX31_PIN_USBOTG_STP, IOMUX_CONFIG_FUNC)
648#define MX31_PIN_CSPI1_MOSI__USBH1_RXDM IOMUX_MODE(MX31_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT1) 641#define MX31_PIN_CSPI1_MOSI__USBH1_RXDM IOMUX_MODE(MX31_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT1)
649#define MX31_PIN_CSPI1_MISO__USBH1_RXDP IOMUX_MODE(MX31_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT1) 642#define MX31_PIN_CSPI1_MISO__USBH1_RXDP IOMUX_MODE(MX31_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT1)
650#define MX31_PIN_CSPI1_SS0__USBH1_TXDM IOMUX_MODE(MX31_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT1) 643#define MX31_PIN_CSPI1_SS0__USBH1_TXDM IOMUX_MODE(MX31_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT1)
651#define MX31_PIN_CSPI1_SS1__USBH1_TXDP IOMUX_MODE(MX31_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT1) 644#define MX31_PIN_CSPI1_SS1__USBH1_TXDP IOMUX_MODE(MX31_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT1)
652#define MX31_PIN_CSPI1_SS2__USBH1_RCV IOMUX_MODE(MX31_PIN_CSPI1_SS2, IOMUX_CONFIG_ALT1) 645#define MX31_PIN_CSPI1_SS2__USBH1_RCV IOMUX_MODE(MX31_PIN_CSPI1_SS2, IOMUX_CONFIG_ALT1)
653#define MX31_PIN_CSPI1_SCLK__USBH1_OEB IOMUX_MODE(MX31_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT1) 646#define MX31_PIN_CSPI1_SCLK__USBH1_OEB IOMUX_MODE(MX31_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT1)
654#define MX31_PIN_CSPI1_SPI_RDY__USBH1_FS IOMUX_MODE(MX31_PIN_CSPI1_SPI_RDY, IOMUX_CONFIG_ALT1) 647#define MX31_PIN_CSPI1_SPI_RDY__USBH1_FS IOMUX_MODE(MX31_PIN_CSPI1_SPI_RDY, IOMUX_CONFIG_ALT1)
655#define MX31_PIN_SFS6__USBH1_SUSPEND IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_FUNC) 648#define MX31_PIN_SFS6__USBH1_SUSPEND IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_FUNC)
656#define MX31_PIN_NFRE_B__GPIO1_11 IOMUX_MODE(MX31_PIN_NFRE_B, IOMUX_CONFIG_GPIO) 649#define MX31_PIN_NFRE_B__GPIO1_11 IOMUX_MODE(MX31_PIN_NFRE_B, IOMUX_CONFIG_GPIO)
657#define MX31_PIN_NFALE__GPIO1_12 IOMUX_MODE(MX31_PIN_NFALE, IOMUX_CONFIG_GPIO) 650#define MX31_PIN_NFALE__GPIO1_12 IOMUX_MODE(MX31_PIN_NFALE, IOMUX_CONFIG_GPIO)
658#define MX31_PIN_USBH2_DATA0__USBH2_DATA0 IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC) 651#define MX31_PIN_USBH2_DATA0__USBH2_DATA0 IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC)
659#define MX31_PIN_USBH2_DATA1__USBH2_DATA1 IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC) 652#define MX31_PIN_USBH2_DATA1__USBH2_DATA1 IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC)
660#define MX31_PIN_STXD3__USBH2_DATA2 IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC) 653#define MX31_PIN_STXD3__USBH2_DATA2 IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC)
661#define MX31_PIN_SRXD3__USBH2_DATA3 IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC) 654#define MX31_PIN_SRXD3__USBH2_DATA3 IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC)
662#define MX31_PIN_SCK3__USBH2_DATA4 IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC) 655#define MX31_PIN_SCK3__USBH2_DATA4 IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC)
663#define MX31_PIN_SFS3__USBH2_DATA5 IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC) 656#define MX31_PIN_SFS3__USBH2_DATA5 IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC)
664#define MX31_PIN_STXD6__USBH2_DATA6 IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC) 657#define MX31_PIN_STXD6__USBH2_DATA6 IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC)
665#define MX31_PIN_SRXD6__USBH2_DATA7 IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC) 658#define MX31_PIN_SRXD6__USBH2_DATA7 IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC)
666#define MX31_PIN_USBH2_CLK__USBH2_CLK IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC) 659#define MX31_PIN_USBH2_CLK__USBH2_CLK IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC)
667#define MX31_PIN_USBH2_DIR__USBH2_DIR IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC) 660#define MX31_PIN_USBH2_DIR__USBH2_DIR IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC)
668#define MX31_PIN_USBH2_NXT__USBH2_NXT IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC) 661#define MX31_PIN_USBH2_NXT__USBH2_NXT IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC)
669#define MX31_PIN_USBH2_STP__USBH2_STP IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC) 662#define MX31_PIN_USBH2_STP__USBH2_STP IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC)
670#define MX31_PIN_SCK6__GPIO1_25 IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO) 663#define MX31_PIN_SCK6__GPIO1_25 IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO)
671#define MX31_PIN_USB_OC__GPIO1_30 IOMUX_MODE(MX31_PIN_USB_OC, IOMUX_CONFIG_GPIO) 664#define MX31_PIN_USB_OC__GPIO1_30 IOMUX_MODE(MX31_PIN_USB_OC, IOMUX_CONFIG_GPIO)
672#define MX31_PIN_I2C_DAT__I2C1_SDA IOMUX_MODE(MX31_PIN_I2C_DAT, IOMUX_CONFIG_FUNC) 665#define MX31_PIN_I2C_DAT__I2C1_SDA IOMUX_MODE(MX31_PIN_I2C_DAT, IOMUX_CONFIG_FUNC)
@@ -711,8 +704,8 @@ enum iomux_pins {
711#define MX31_PIN_DSR_DCE1__GPIO2_9 IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_GPIO) 704#define MX31_PIN_DSR_DCE1__GPIO2_9 IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_GPIO)
712#define MX31_PIN_RI_DCE1__GPIO2_10 IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_GPIO) 705#define MX31_PIN_RI_DCE1__GPIO2_10 IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_GPIO)
713#define MX31_PIN_DCD_DCE1__GPIO2_11 IOMUX_MODE(MX31_PIN_DCD_DCE1, IOMUX_CONFIG_GPIO) 706#define MX31_PIN_DCD_DCE1__GPIO2_11 IOMUX_MODE(MX31_PIN_DCD_DCE1, IOMUX_CONFIG_GPIO)
714#define MX31_PIN_STXD5__GPIO1_21 IOMUX_MODE(MX31_PIN_STXD5, IOMUX_CONFIG_GPIO) 707#define MX31_PIN_STXD5__GPIO1_21 IOMUX_MODE(MX31_PIN_STXD5, IOMUX_CONFIG_GPIO)
715#define MX31_PIN_SRXD5__GPIO1_22 IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_GPIO) 708#define MX31_PIN_SRXD5__GPIO1_22 IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_GPIO)
716#define MX31_PIN_GPIO1_3__GPIO1_3 IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO) 709#define MX31_PIN_GPIO1_3__GPIO1_3 IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO)
717#define MX31_PIN_CSPI2_SS1__CSPI3_SS1 IOMUX_MODE(MX31_PIN_CSPI2_SS1, IOMUX_CONFIG_ALT1) 710#define MX31_PIN_CSPI2_SS1__CSPI3_SS1 IOMUX_MODE(MX31_PIN_CSPI2_SS1, IOMUX_CONFIG_ALT1)
718#define MX31_PIN_RTS1__GPIO2_6 IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_GPIO) 711#define MX31_PIN_RTS1__GPIO2_6 IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_GPIO)
@@ -727,13 +720,14 @@ enum iomux_pins {
727#define MX31_PIN_SCK5__SCK5 IOMUX_MODE(MX31_PIN_SCK5, IOMUX_CONFIG_FUNC) 720#define MX31_PIN_SCK5__SCK5 IOMUX_MODE(MX31_PIN_SCK5, IOMUX_CONFIG_FUNC)
728#define MX31_PIN_SFS5__SFS5 IOMUX_MODE(MX31_PIN_SFS5, IOMUX_CONFIG_FUNC) 721#define MX31_PIN_SFS5__SFS5 IOMUX_MODE(MX31_PIN_SFS5, IOMUX_CONFIG_FUNC)
729 722
730/*XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed by cspi2_ss0, cspi2_ss1, cspi1_ss0 723/*
731 * cspi1_ss1*/ 724 * XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed with cspi2_ss0,
725 * cspi2_ss1, cspi1_ss0 cspi1_ss1
726 */
732 727
733/* 728/*
734 * This function configures the pad value for a IOMUX pin. 729 * This function configures the pad value for a IOMUX pin.
735 */ 730 */
736void mxc_iomux_set_pad(enum iomux_pins, u32); 731void mxc_iomux_set_pad(enum iomux_pins, u32);
737 732
738#endif 733#endif /* ifndef __MACH_IOMUX_MX3_H__ */
739
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx35.h b/arch/arm/plat-mxc/include/mach/iomux-mx35.h
index c88d40795f7a..2a24bae1b878 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx35.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx35.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C, NO_PAD_CTRL) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de> 2 * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de>
3 * 3 *
4 * This program is free software; you can redistribute it and/or 4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License 5 * modify it under the terms of the GNU General Public License
diff --git a/arch/arm/plat-mxc/include/mach/iomux-v1.h b/arch/arm/plat-mxc/include/mach/iomux-v1.h
new file mode 100644
index 000000000000..884f5753f279
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/iomux-v1.h
@@ -0,0 +1,103 @@
1/*
2 * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
3 * Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19#ifndef __MACH_IOMUX_V1_H__
20#define __MACH_IOMUX_V1_H__
21
22/*
23* GPIO Module and I/O Multiplexer
24* x = 0..3 for reg_A, reg_B, reg_C, reg_D
25*/
26#define MXC_DDIR(x) (0x00 + ((x) << 8))
27#define MXC_OCR1(x) (0x04 + ((x) << 8))
28#define MXC_OCR2(x) (0x08 + ((x) << 8))
29#define MXC_ICONFA1(x) (0x0c + ((x) << 8))
30#define MXC_ICONFA2(x) (0x10 + ((x) << 8))
31#define MXC_ICONFB1(x) (0x14 + ((x) << 8))
32#define MXC_ICONFB2(x) (0x18 + ((x) << 8))
33#define MXC_DR(x) (0x1c + ((x) << 8))
34#define MXC_GIUS(x) (0x20 + ((x) << 8))
35#define MXC_SSR(x) (0x24 + ((x) << 8))
36#define MXC_ICR1(x) (0x28 + ((x) << 8))
37#define MXC_ICR2(x) (0x2c + ((x) << 8))
38#define MXC_IMR(x) (0x30 + ((x) << 8))
39#define MXC_ISR(x) (0x34 + ((x) << 8))
40#define MXC_GPR(x) (0x38 + ((x) << 8))
41#define MXC_SWR(x) (0x3c + ((x) << 8))
42#define MXC_PUEN(x) (0x40 + ((x) << 8))
43
44#define MX1_NUM_GPIO_PORT 4
45#define MX21_NUM_GPIO_PORT 6
46#define MX27_NUM_GPIO_PORT 6
47
48#define GPIO_PIN_MASK 0x1f
49
50#define GPIO_PORT_SHIFT 5
51#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
52
53#define GPIO_PORTA (0 << GPIO_PORT_SHIFT)
54#define GPIO_PORTB (1 << GPIO_PORT_SHIFT)
55#define GPIO_PORTC (2 << GPIO_PORT_SHIFT)
56#define GPIO_PORTD (3 << GPIO_PORT_SHIFT)
57#define GPIO_PORTE (4 << GPIO_PORT_SHIFT)
58#define GPIO_PORTF (5 << GPIO_PORT_SHIFT)
59
60#define GPIO_OUT (1 << 8)
61#define GPIO_IN (0 << 8)
62#define GPIO_PUEN (1 << 9)
63
64#define GPIO_PF (1 << 10)
65#define GPIO_AF (1 << 11)
66
67#define GPIO_OCR_SHIFT 12
68#define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT)
69#define GPIO_AIN (0 << GPIO_OCR_SHIFT)
70#define GPIO_BIN (1 << GPIO_OCR_SHIFT)
71#define GPIO_CIN (2 << GPIO_OCR_SHIFT)
72#define GPIO_GPIO (3 << GPIO_OCR_SHIFT)
73
74#define GPIO_AOUT_SHIFT 14
75#define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT)
76#define GPIO_AOUT (0 << GPIO_AOUT_SHIFT)
77#define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT)
78#define GPIO_AOUT_0 (2 << GPIO_AOUT_SHIFT)
79#define GPIO_AOUT_1 (3 << GPIO_AOUT_SHIFT)
80
81#define GPIO_BOUT_SHIFT 16
82#define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT)
83#define GPIO_BOUT (0 << GPIO_BOUT_SHIFT)
84#define GPIO_BOUT_ISR (1 << GPIO_BOUT_SHIFT)
85#define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT)
86#define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT)
87
88/* decode irq number to use with IMR(x), ISR(x) and friends */
89#define IRQ_TO_REG(irq) ((irq - MXC_INTERNAL_IRQS) >> 5)
90
91#define IRQ_GPIOA(x) (MXC_GPIO_IRQ_START + x)
92#define IRQ_GPIOB(x) (IRQ_GPIOA(32) + x)
93#define IRQ_GPIOC(x) (IRQ_GPIOB(32) + x)
94#define IRQ_GPIOD(x) (IRQ_GPIOC(32) + x)
95#define IRQ_GPIOE(x) (IRQ_GPIOD(32) + x)
96#define IRQ_GPIOF(x) (IRQ_GPIOE(32) + x)
97
98extern int mxc_gpio_mode(int gpio_mode);
99extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
100 const char *label);
101extern void mxc_gpio_release_multiple_pins(const int *pin_list, int count);
102
103#endif /* __MACH_IOMUX_V1_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/iomux.h b/arch/arm/plat-mxc/include/mach/iomux.h
index 011cfcd8b820..3d226d7e7be2 100644
--- a/arch/arm/plat-mxc/include/mach/iomux.h
+++ b/arch/arm/plat-mxc/include/mach/iomux.h
@@ -1,102 +1,14 @@
1/* 1/*
2* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> 2 * Copyright (C) 2010 Uwe Kleine-Koenig, Pengutronix
3* Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de> 3 *
4* 4 * This program is free software; you can redistribute it and/or modify it
5* This program is free software; you can redistribute it and/or 5 * under the terms of the GNU General Public License version 2 as published by
6* modify it under the terms of the GNU General Public License 6 * the Free Software Foundation.
7* as published by the Free Software Foundation; either version 2 7 */
8* of the License, or (at your option) any later version. 8#ifndef __MACH_IOMUX_H__
9* This program is distributed in the hope that it will be useful, 9#define __MACH_IOMUX_H__
10* but WITHOUT ANY WARRANTY; without even the implied warranty of
11* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12* GNU General Public License for more details.
13*
14* You should have received a copy of the GNU General Public License
15* along with this program; if not, write to the Free Software
16* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17* MA 02110-1301, USA.
18*/
19
20#ifndef _MXC_IOMUX_H
21#define _MXC_IOMUX_H
22
23/*
24* GPIO Module and I/O Multiplexer
25* x = 0..3 for reg_A, reg_B, reg_C, reg_D
26*/
27#define VA_GPIO_BASE IO_ADDRESS(GPIO_BASE_ADDR)
28#define MXC_DDIR(x) (0x00 + ((x) << 8))
29#define MXC_OCR1(x) (0x04 + ((x) << 8))
30#define MXC_OCR2(x) (0x08 + ((x) << 8))
31#define MXC_ICONFA1(x) (0x0c + ((x) << 8))
32#define MXC_ICONFA2(x) (0x10 + ((x) << 8))
33#define MXC_ICONFB1(x) (0x14 + ((x) << 8))
34#define MXC_ICONFB2(x) (0x18 + ((x) << 8))
35#define MXC_DR(x) (0x1c + ((x) << 8))
36#define MXC_GIUS(x) (0x20 + ((x) << 8))
37#define MXC_SSR(x) (0x24 + ((x) << 8))
38#define MXC_ICR1(x) (0x28 + ((x) << 8))
39#define MXC_ICR2(x) (0x2c + ((x) << 8))
40#define MXC_IMR(x) (0x30 + ((x) << 8))
41#define MXC_ISR(x) (0x34 + ((x) << 8))
42#define MXC_GPR(x) (0x38 + ((x) << 8))
43#define MXC_SWR(x) (0x3c + ((x) << 8))
44#define MXC_PUEN(x) (0x40 + ((x) << 8))
45
46#ifdef CONFIG_ARCH_MX1
47# define GPIO_PORT_MAX 3
48#endif
49#ifdef CONFIG_ARCH_MX2
50# define GPIO_PORT_MAX 5
51#endif
52#ifdef CONFIG_ARCH_MX25
53# define GPIO_PORT_MAX 3
54#endif
55
56#ifndef GPIO_PORT_MAX
57# error "GPIO config port count unknown!"
58#endif
59
60#define GPIO_PIN_MASK 0x1f
61
62#define GPIO_PORT_SHIFT 5
63#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
64
65#define GPIO_PORTA (0 << GPIO_PORT_SHIFT)
66#define GPIO_PORTB (1 << GPIO_PORT_SHIFT)
67#define GPIO_PORTC (2 << GPIO_PORT_SHIFT)
68#define GPIO_PORTD (3 << GPIO_PORT_SHIFT)
69#define GPIO_PORTE (4 << GPIO_PORT_SHIFT)
70#define GPIO_PORTF (5 << GPIO_PORT_SHIFT)
71
72#define GPIO_OUT (1 << 8)
73#define GPIO_IN (0 << 8)
74#define GPIO_PUEN (1 << 9)
75
76#define GPIO_PF (1 << 10)
77#define GPIO_AF (1 << 11)
78
79#define GPIO_OCR_SHIFT 12
80#define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT)
81#define GPIO_AIN (0 << GPIO_OCR_SHIFT)
82#define GPIO_BIN (1 << GPIO_OCR_SHIFT)
83#define GPIO_CIN (2 << GPIO_OCR_SHIFT)
84#define GPIO_GPIO (3 << GPIO_OCR_SHIFT)
85
86#define GPIO_AOUT_SHIFT 14
87#define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT)
88#define GPIO_AOUT (0 << GPIO_AOUT_SHIFT)
89#define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT)
90#define GPIO_AOUT_0 (2 << GPIO_AOUT_SHIFT)
91#define GPIO_AOUT_1 (3 << GPIO_AOUT_SHIFT)
92
93#define GPIO_BOUT_SHIFT 16
94#define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT)
95#define GPIO_BOUT (0 << GPIO_BOUT_SHIFT)
96#define GPIO_BOUT_ISR (1 << GPIO_BOUT_SHIFT)
97#define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT)
98#define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT)
99 10
11/* This file will go away, please include mach/iomux-mx... directly */
100 12
101#ifdef CONFIG_ARCH_MX1 13#ifdef CONFIG_ARCH_MX1
102#include <mach/iomux-mx1.h> 14#include <mach/iomux-mx1.h>
@@ -110,25 +22,5 @@
110#include <mach/iomux-mx27.h> 22#include <mach/iomux-mx27.h>
111#endif 23#endif
112#endif 24#endif
113#ifdef CONFIG_ARCH_MX25
114#include <mach/iomux-mx25.h>
115#endif
116 25
117 26#endif /* __MACH_IOMUX_H__ */
118/* decode irq number to use with IMR(x), ISR(x) and friends */
119#define IRQ_TO_REG(irq) ((irq - MXC_INTERNAL_IRQS) >> 5)
120
121#define IRQ_GPIOA(x) (MXC_GPIO_IRQ_START + x)
122#define IRQ_GPIOB(x) (IRQ_GPIOA(32) + x)
123#define IRQ_GPIOC(x) (IRQ_GPIOB(32) + x)
124#define IRQ_GPIOD(x) (IRQ_GPIOC(32) + x)
125#define IRQ_GPIOE(x) (IRQ_GPIOD(32) + x)
126#define IRQ_GPIOF(x) (IRQ_GPIOE(32) + x)
127
128
129extern void mxc_gpio_mode(int gpio_mode);
130extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
131 const char *label);
132extern void mxc_gpio_release_multiple_pins(const int *pin_list, int count);
133
134#endif
diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h
index a3ad643de5a1..86781f7b0c0c 100644
--- a/arch/arm/plat-mxc/include/mach/irqs.h
+++ b/arch/arm/plat-mxc/include/mach/irqs.h
@@ -22,18 +22,19 @@
22 22
23#define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS 23#define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS
24 24
25#if defined CONFIG_ARCH_MX1 25/* these are ordered by size to support multi-SoC kernels */
26#define MXC_GPIO_IRQS (32 * 4) 26#if defined CONFIG_ARCH_MX2
27#elif defined CONFIG_ARCH_MX2
28#define MXC_GPIO_IRQS (32 * 6) 27#define MXC_GPIO_IRQS (32 * 6)
29#elif defined CONFIG_ARCH_MX3 28#elif defined CONFIG_ARCH_MX1
30#define MXC_GPIO_IRQS (32 * 3) 29#define MXC_GPIO_IRQS (32 * 4)
31#elif defined CONFIG_ARCH_MX25 30#elif defined CONFIG_ARCH_MX25
32#define MXC_GPIO_IRQS (32 * 4) 31#define MXC_GPIO_IRQS (32 * 4)
33#elif defined CONFIG_ARCH_MX5 32#elif defined CONFIG_ARCH_MX5
34#define MXC_GPIO_IRQS (32 * 4) 33#define MXC_GPIO_IRQS (32 * 4)
35#elif defined CONFIG_ARCH_MXC91231 34#elif defined CONFIG_ARCH_MXC91231
36#define MXC_GPIO_IRQS (32 * 4) 35#define MXC_GPIO_IRQS (32 * 4)
36#elif defined CONFIG_ARCH_MX3
37#define MXC_GPIO_IRQS (32 * 3)
37#endif 38#endif
38 39
39/* 40/*
diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h
index 7cae9cb6208d..c4b40c35a6a1 100644
--- a/arch/arm/plat-mxc/include/mach/memory.h
+++ b/arch/arm/plat-mxc/include/mach/memory.h
@@ -37,20 +37,19 @@
37# endif 37# endif
38#endif 38#endif
39 39
40#if defined(CONFIG_MX1_VIDEO) 40#if defined(CONFIG_MX3_VIDEO)
41/* 41/*
42 * Increase size of DMA-consistent memory region. 42 * Increase size of DMA-consistent memory region.
43 * This is required for i.MX camera driver to capture at least four VGA frames. 43 * This is required for mx3 camera driver to capture at least two QXGA frames.
44 */ 44 */
45#define CONSISTENT_DMA_SIZE SZ_4M 45#define CONSISTENT_DMA_SIZE SZ_8M
46#endif /* CONFIG_MX1_VIDEO */
47 46
48#if defined(CONFIG_MX3_VIDEO) 47#elif defined(CONFIG_MX1_VIDEO)
49/* 48/*
50 * Increase size of DMA-consistent memory region. 49 * Increase size of DMA-consistent memory region.
51 * This is required for mx3 camera driver to capture at least two QXGA frames. 50 * This is required for i.MX camera driver to capture at least four VGA frames.
52 */ 51 */
53#define CONSISTENT_DMA_SIZE SZ_8M 52#define CONSISTENT_DMA_SIZE SZ_4M
54#endif /* CONFIG_MX3_VIDEO */ 53#endif /* CONFIG_MX1_VIDEO */
55 54
56#endif /* __ASM_ARCH_MXC_MEMORY_H__ */ 55#endif /* __ASM_ARCH_MXC_MEMORY_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mtd-xip.h b/arch/arm/plat-mxc/include/mach/mtd-xip.h
deleted file mode 100644
index 1ab1bba5688d..000000000000
--- a/arch/arm/plat-mxc/include/mach/mtd-xip.h
+++ /dev/null
@@ -1,34 +0,0 @@
1/*
2 * MTD primitives for XIP support. Architecture specific functions
3 *
4 * Do not include this file directly. It's included from linux/mtd/xip.h
5 *
6 * Copyright (C) 2008 Darius Augulis <augulis.darius@gmail.com>, Teltonika, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 */
13
14#include <mach/mxc_timer.h>
15
16#ifndef __ARCH_IMX_MTD_XIP_H__
17#define __ARCH_IMX_MTD_XIP_H__
18
19#ifdef CONFIG_ARCH_MX1
20/* AITC registers */
21#define AITC_BASE IO_ADDRESS(AVIC_BASE_ADDR)
22#define NIPNDH (AITC_BASE + 0x58)
23#define NIPNDL (AITC_BASE + 0x5C)
24#define INTENABLEH (AITC_BASE + 0x10)
25#define INTENABLEL (AITC_BASE + 0x14)
26/* MTD macros */
27#define xip_irqpending() ((__raw_readl(INTENABLEH) & __raw_readl(NIPNDH)) \
28 || (__raw_readl(INTENABLEL) & __raw_readl(NIPNDL)))
29#define xip_currtime() (__raw_readl(TIMER_BASE + MXC_TCN))
30#define xip_elapsed_since(x) (signed)((__raw_readl(TIMER_BASE + MXC_TCN) - (x)) / 96)
31#define xip_cpu_idle() asm volatile ("mcr p15, 0, %0, c7, c0, 4" :: "r" (0))
32#endif /* CONFIG_ARCH_MX1 */
33
34#endif /* __ARCH_IMX_MTD_XIP_H__ */
diff --git a/arch/arm/plat-mxc/iomux-mx1-mx2.c b/arch/arm/plat-mxc/iomux-mx1-mx2.c
deleted file mode 100644
index 25023ac2f53b..000000000000
--- a/arch/arm/plat-mxc/iomux-mx1-mx2.c
+++ /dev/null
@@ -1,159 +0,0 @@
1/*
2 * arch/arm/mach-mxc/generic.c
3 *
4 * author: Sascha Hauer
5 * Created: april 20th, 2004
6 * Copyright: Synertronixx GmbH
7 *
8 * Common code for i.MX machines
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
25
26#include <linux/errno.h>
27#include <linux/init.h>
28#include <linux/kernel.h>
29#include <linux/module.h>
30#include <linux/string.h>
31#include <linux/gpio.h>
32
33#include <mach/hardware.h>
34#include <asm/mach/map.h>
35#include <mach/iomux.h>
36
37void mxc_gpio_mode(int gpio_mode)
38{
39 unsigned int pin = gpio_mode & GPIO_PIN_MASK;
40 unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
41 unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT;
42 unsigned int tmp;
43
44 /* Pullup enable */
45 tmp = __raw_readl(VA_GPIO_BASE + MXC_PUEN(port));
46 if (gpio_mode & GPIO_PUEN)
47 tmp |= (1 << pin);
48 else
49 tmp &= ~(1 << pin);
50 __raw_writel(tmp, VA_GPIO_BASE + MXC_PUEN(port));
51
52 /* Data direction */
53 tmp = __raw_readl(VA_GPIO_BASE + MXC_DDIR(port));
54 if (gpio_mode & GPIO_OUT)
55 tmp |= 1 << pin;
56 else
57 tmp &= ~(1 << pin);
58 __raw_writel(tmp, VA_GPIO_BASE + MXC_DDIR(port));
59
60 /* Primary / alternate function */
61 tmp = __raw_readl(VA_GPIO_BASE + MXC_GPR(port));
62 if (gpio_mode & GPIO_AF)
63 tmp |= (1 << pin);
64 else
65 tmp &= ~(1 << pin);
66 __raw_writel(tmp, VA_GPIO_BASE + MXC_GPR(port));
67
68 /* use as gpio? */
69 tmp = __raw_readl(VA_GPIO_BASE + MXC_GIUS(port));
70 if (gpio_mode & (GPIO_PF | GPIO_AF))
71 tmp &= ~(1 << pin);
72 else
73 tmp |= (1 << pin);
74 __raw_writel(tmp, VA_GPIO_BASE + MXC_GIUS(port));
75
76 if (pin < 16) {
77 tmp = __raw_readl(VA_GPIO_BASE + MXC_OCR1(port));
78 tmp &= ~(3 << (pin * 2));
79 tmp |= (ocr << (pin * 2));
80 __raw_writel(tmp, VA_GPIO_BASE + MXC_OCR1(port));
81
82 tmp = __raw_readl(VA_GPIO_BASE + MXC_ICONFA1(port));
83 tmp &= ~(3 << (pin * 2));
84 tmp |= ((gpio_mode >> GPIO_AOUT_SHIFT) & 3) << (pin * 2);
85 __raw_writel(tmp, VA_GPIO_BASE + MXC_ICONFA1(port));
86
87 tmp = __raw_readl(VA_GPIO_BASE + MXC_ICONFB1(port));
88 tmp &= ~(3 << (pin * 2));
89 tmp |= ((gpio_mode >> GPIO_BOUT_SHIFT) & 3) << (pin * 2);
90 __raw_writel(tmp, VA_GPIO_BASE + MXC_ICONFB1(port));
91 } else {
92 pin -= 16;
93
94 tmp = __raw_readl(VA_GPIO_BASE + MXC_OCR2(port));
95 tmp &= ~(3 << (pin * 2));
96 tmp |= (ocr << (pin * 2));
97 __raw_writel(tmp, VA_GPIO_BASE + MXC_OCR2(port));
98
99 tmp = __raw_readl(VA_GPIO_BASE + MXC_ICONFA2(port));
100 tmp &= ~(3 << (pin * 2));
101 tmp |= ((gpio_mode >> GPIO_AOUT_SHIFT) & 3) << (pin * 2);
102 __raw_writel(tmp, VA_GPIO_BASE + MXC_ICONFA2(port));
103
104 tmp = __raw_readl(VA_GPIO_BASE + MXC_ICONFB2(port));
105 tmp &= ~(3 << (pin * 2));
106 tmp |= ((gpio_mode >> GPIO_BOUT_SHIFT) & 3) << (pin * 2);
107 __raw_writel(tmp, VA_GPIO_BASE + MXC_ICONFB2(port));
108 }
109}
110EXPORT_SYMBOL(mxc_gpio_mode);
111
112int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
113 const char *label)
114{
115 const int *p = pin_list;
116 int i;
117 unsigned gpio;
118 unsigned mode;
119 int ret;
120
121 for (i = 0; i < count; i++) {
122 gpio = *p & (GPIO_PIN_MASK | GPIO_PORT_MASK);
123 mode = *p & ~(GPIO_PIN_MASK | GPIO_PORT_MASK);
124
125 if (gpio >= (GPIO_PORT_MAX + 1) * 32) {
126 ret = -EINVAL;
127 goto setup_error;
128 }
129
130 ret = gpio_request(gpio, label);
131 if (ret)
132 goto setup_error;
133
134 mxc_gpio_mode(gpio | mode);
135
136 p++;
137 }
138 return 0;
139
140setup_error:
141 mxc_gpio_release_multiple_pins(pin_list, i);
142 return ret;
143}
144EXPORT_SYMBOL(mxc_gpio_setup_multiple_pins);
145
146void mxc_gpio_release_multiple_pins(const int *pin_list, int count)
147{
148 const int *p = pin_list;
149 int i;
150
151 for (i = 0; i < count; i++) {
152 unsigned gpio = *p & (GPIO_PIN_MASK | GPIO_PORT_MASK);
153 gpio_free(gpio);
154 p++;
155 }
156
157}
158EXPORT_SYMBOL(mxc_gpio_release_multiple_pins);
159
diff --git a/arch/arm/plat-mxc/iomux-v1.c b/arch/arm/plat-mxc/iomux-v1.c
new file mode 100644
index 000000000000..960a02cbcbaf
--- /dev/null
+++ b/arch/arm/plat-mxc/iomux-v1.c
@@ -0,0 +1,238 @@
1/*
2 * arch/arm/plat-mxc/iomux-v1.c
3 *
4 * Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH
5 * Copyright (C) 2009 Uwe Kleine-Koenig, Pengutronix
6 *
7 * Common code for i.MX1, i.MX21 and i.MX27
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software Foundation, Inc.,
21 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
22 */
23
24#include <linux/errno.h>
25#include <linux/init.h>
26#include <linux/kernel.h>
27#include <linux/module.h>
28#include <linux/string.h>
29#include <linux/gpio.h>
30
31#include <mach/hardware.h>
32#include <asm/mach/map.h>
33#include <mach/iomux-v1.h>
34
35static void __iomem *imx_iomuxv1_baseaddr;
36static unsigned imx_iomuxv1_numports;
37
38static inline unsigned long imx_iomuxv1_readl(unsigned offset)
39{
40 return __raw_readl(imx_iomuxv1_baseaddr + offset);
41}
42
43static inline void imx_iomuxv1_writel(unsigned long val, unsigned offset)
44{
45 __raw_writel(val, imx_iomuxv1_baseaddr + offset);
46}
47
48static inline void imx_iomuxv1_rmwl(unsigned offset,
49 unsigned long mask, unsigned long value)
50{
51 unsigned long reg = imx_iomuxv1_readl(offset);
52
53 reg &= ~mask;
54 reg |= value;
55
56 imx_iomuxv1_writel(reg, offset);
57}
58
59static inline void imx_iomuxv1_set_puen(
60 unsigned int port, unsigned int pin, int on)
61{
62 unsigned long mask = 1 << pin;
63
64 imx_iomuxv1_rmwl(MXC_PUEN(port), mask, on ? mask : 0);
65}
66
67static inline void imx_iomuxv1_set_ddir(
68 unsigned int port, unsigned int pin, int out)
69{
70 unsigned long mask = 1 << pin;
71
72 imx_iomuxv1_rmwl(MXC_DDIR(port), mask, out ? mask : 0);
73}
74
75static inline void imx_iomuxv1_set_gpr(
76 unsigned int port, unsigned int pin, int af)
77{
78 unsigned long mask = 1 << pin;
79
80 imx_iomuxv1_rmwl(MXC_GPR(port), mask, af ? mask : 0);
81}
82
83static inline void imx_iomuxv1_set_gius(
84 unsigned int port, unsigned int pin, int inuse)
85{
86 unsigned long mask = 1 << pin;
87
88 imx_iomuxv1_rmwl(MXC_GIUS(port), mask, inuse ? mask : 0);
89}
90
91static inline void imx_iomuxv1_set_ocr(
92 unsigned int port, unsigned int pin, unsigned int ocr)
93{
94 unsigned long shift = (pin & 0xf) << 1;
95 unsigned long mask = 3 << shift;
96 unsigned long value = ocr << shift;
97 unsigned long offset = pin < 16 ? MXC_OCR1(port) : MXC_OCR2(port);
98
99 imx_iomuxv1_rmwl(offset, mask, value);
100}
101
102static inline void imx_iomuxv1_set_iconfa(
103 unsigned int port, unsigned int pin, unsigned int aout)
104{
105 unsigned long shift = (pin & 0xf) << 1;
106 unsigned long mask = 3 << shift;
107 unsigned long value = aout << shift;
108 unsigned long offset = pin < 16 ? MXC_ICONFA1(port) : MXC_ICONFA2(port);
109
110 imx_iomuxv1_rmwl(offset, mask, value);
111}
112
113static inline void imx_iomuxv1_set_iconfb(
114 unsigned int port, unsigned int pin, unsigned int bout)
115{
116 unsigned long shift = (pin & 0xf) << 1;
117 unsigned long mask = 3 << shift;
118 unsigned long value = bout << shift;
119 unsigned long offset = pin < 16 ? MXC_ICONFB1(port) : MXC_ICONFB2(port);
120
121 imx_iomuxv1_rmwl(offset, mask, value);
122}
123
124int mxc_gpio_mode(int gpio_mode)
125{
126 unsigned int pin = gpio_mode & GPIO_PIN_MASK;
127 unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
128 unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT;
129 unsigned int aout = (gpio_mode >> GPIO_AOUT_SHIFT) & 3;
130 unsigned int bout = (gpio_mode >> GPIO_BOUT_SHIFT) & 3;
131
132 if (port >= imx_iomuxv1_numports)
133 return -EINVAL;
134
135 /* Pullup enable */
136 imx_iomuxv1_set_puen(port, pin, gpio_mode & GPIO_PUEN);
137
138 /* Data direction */
139 imx_iomuxv1_set_ddir(port, pin, gpio_mode & GPIO_OUT);
140
141 /* Primary / alternate function */
142 imx_iomuxv1_set_gpr(port, pin, gpio_mode & GPIO_AF);
143
144 /* use as gpio? */
145 imx_iomuxv1_set_gius(port, pin, !(gpio_mode & (GPIO_PF | GPIO_AF)));
146
147 imx_iomuxv1_set_ocr(port, pin, ocr);
148
149 imx_iomuxv1_set_iconfa(port, pin, aout);
150
151 imx_iomuxv1_set_iconfb(port, pin, bout);
152
153 return 0;
154}
155EXPORT_SYMBOL(mxc_gpio_mode);
156
157static int imx_iomuxv1_setup_multiple(const int *list, unsigned count)
158{
159 size_t i;
160 int ret;
161
162 for (i = 0; i < count; ++i) {
163 ret = mxc_gpio_mode(list[i]);
164
165 if (ret)
166 return ret;
167 }
168
169 return ret;
170}
171
172int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
173 const char *label)
174{
175 size_t i;
176 int ret;
177
178 for (i = 0; i < count; ++i) {
179 unsigned gpio = pin_list[i] & (GPIO_PIN_MASK | GPIO_PORT_MASK);
180
181 ret = gpio_request(gpio, label);
182 if (ret)
183 goto err_gpio_request;
184 }
185
186 ret = imx_iomuxv1_setup_multiple(pin_list, count);
187 if (ret)
188 goto err_setup;
189
190 return 0;
191
192err_setup:
193 BUG_ON(i != count);
194
195err_gpio_request:
196 mxc_gpio_release_multiple_pins(pin_list, i);
197
198 return ret;
199}
200EXPORT_SYMBOL(mxc_gpio_setup_multiple_pins);
201
202void mxc_gpio_release_multiple_pins(const int *pin_list, int count)
203{
204 size_t i;
205
206 for (i = 0; i < count; ++i) {
207 unsigned gpio = pin_list[i] & (GPIO_PIN_MASK | GPIO_PORT_MASK);
208
209 gpio_free(gpio);
210 }
211}
212EXPORT_SYMBOL(mxc_gpio_release_multiple_pins);
213
214static int imx_iomuxv1_init(void)
215{
216#ifdef CONFIG_ARCH_MX1
217 if (cpu_is_mx1()) {
218 imx_iomuxv1_baseaddr = MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR);
219 imx_iomuxv1_numports = MX1_NUM_GPIO_PORT;
220 } else
221#endif
222#ifdef CONFIG_MACH_MX21
223 if (cpu_is_mx21()) {
224 imx_iomuxv1_baseaddr = MX21_IO_ADDRESS(MX21_GPIO_BASE_ADDR);
225 imx_iomuxv1_numports = MX21_NUM_GPIO_PORT;
226 } else
227#endif
228#ifdef CONFIG_MACH_MX27
229 if (cpu_is_mx27()) {
230 imx_iomuxv1_baseaddr = MX27_IO_ADDRESS(MX27_GPIO_BASE_ADDR);
231 imx_iomuxv1_numports = MX27_NUM_GPIO_PORT;
232 } else
233#endif
234 return -ENODEV;
235
236 return 0;
237}
238pure_initcall(imx_iomuxv1_init);
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-20 15:21:35 -0400