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-rw-r--r--arch/arm/mach-omap2/timer.c17
-rw-r--r--arch/arm/plat-omap/include/plat/dmtimer.h4
2 files changed, 14 insertions, 7 deletions
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 684d2fc3d485..a135d28e202c 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -108,7 +108,7 @@ static int omap2_gp_timer_set_next_event(unsigned long cycles,
108 struct clock_event_device *evt) 108 struct clock_event_device *evt)
109{ 109{
110 __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST, 110 __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST,
111 0xffffffff - cycles, 1); 111 0xffffffff - cycles, OMAP_TIMER_POSTED);
112 112
113 return 0; 113 return 0;
114} 114}
@@ -118,7 +118,7 @@ static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
118{ 118{
119 u32 period; 119 u32 period;
120 120
121 __omap_dm_timer_stop(&clkev, 1, clkev.rate); 121 __omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate);
122 122
123 switch (mode) { 123 switch (mode) {
124 case CLOCK_EVT_MODE_PERIODIC: 124 case CLOCK_EVT_MODE_PERIODIC:
@@ -126,10 +126,10 @@ static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
126 period -= 1; 126 period -= 1;
127 /* Looks like we need to first set the load value separately */ 127 /* Looks like we need to first set the load value separately */
128 __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG, 128 __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG,
129 0xffffffff - period, 1); 129 0xffffffff - period, OMAP_TIMER_POSTED);
130 __omap_dm_timer_load_start(&clkev, 130 __omap_dm_timer_load_start(&clkev,
131 OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST, 131 OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
132 0xffffffff - period, 1); 132 0xffffffff - period, OMAP_TIMER_POSTED);
133 break; 133 break;
134 case CLOCK_EVT_MODE_ONESHOT: 134 case CLOCK_EVT_MODE_ONESHOT:
135 break; 135 break;
@@ -359,7 +359,8 @@ static bool use_gptimer_clksrc;
359 */ 359 */
360static cycle_t clocksource_read_cycles(struct clocksource *cs) 360static cycle_t clocksource_read_cycles(struct clocksource *cs)
361{ 361{
362 return (cycle_t)__omap_dm_timer_read_counter(&clksrc, 1); 362 return (cycle_t)__omap_dm_timer_read_counter(&clksrc,
363 OMAP_TIMER_POSTED);
363} 364}
364 365
365static struct clocksource clocksource_gpt = { 366static struct clocksource clocksource_gpt = {
@@ -373,7 +374,8 @@ static struct clocksource clocksource_gpt = {
373static u32 notrace dmtimer_read_sched_clock(void) 374static u32 notrace dmtimer_read_sched_clock(void)
374{ 375{
375 if (clksrc.reserved) 376 if (clksrc.reserved)
376 return __omap_dm_timer_read_counter(&clksrc, 1); 377 return __omap_dm_timer_read_counter(&clksrc,
378 OMAP_TIMER_POSTED);
377 379
378 return 0; 380 return 0;
379} 381}
@@ -455,7 +457,8 @@ static void __init omap2_gptimer_clocksource_init(int gptimer_id,
455 BUG_ON(res); 457 BUG_ON(res);
456 458
457 __omap_dm_timer_load_start(&clksrc, 459 __omap_dm_timer_load_start(&clksrc,
458 OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, 1); 460 OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0,
461 OMAP_TIMER_POSTED);
459 setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate); 462 setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate);
460 463
461 if (clocksource_register_hz(&clocksource_gpt, clksrc.rate)) 464 if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index f8943c8f9dbf..1bee0ac88760 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -55,6 +55,10 @@
55#define OMAP_TIMER_TRIGGER_OVERFLOW 0x01 55#define OMAP_TIMER_TRIGGER_OVERFLOW 0x01
56#define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02 56#define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02
57 57
58/* posted mode types */
59#define OMAP_TIMER_NONPOSTED 0x00
60#define OMAP_TIMER_POSTED 0x01
61
58/* timer capabilities used in hwmod database */ 62/* timer capabilities used in hwmod database */
59#define OMAP_TIMER_SECURE 0x80000000 63#define OMAP_TIMER_SECURE 0x80000000
60#define OMAP_TIMER_ALWON 0x40000000 64#define OMAP_TIMER_ALWON 0x40000000