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-rw-r--r--arch/arm/Kconfig2
-rw-r--r--arch/arm/configs/n8x0_defconfig94
-rw-r--r--arch/arm/configs/omap2plus_defconfig (renamed from arch/arm/configs/omap3_defconfig)15
-rw-r--r--arch/arm/configs/omap_4430sdp_defconfig125
-rw-r--r--arch/arm/configs/omap_generic_2420_defconfig37
-rw-r--r--arch/arm/mach-omap1/Makefile2
-rw-r--r--arch/arm/mach-omap1/board-htcherald.c322
-rw-r--r--arch/arm/mach-omap1/pm_bus.c98
-rw-r--r--arch/arm/mach-omap2/Kconfig4
-rw-r--r--arch/arm/mach-omap2/Makefile15
-rw-r--r--arch/arm/mach-omap2/board-2430sdp.c3
-rw-r--r--arch/arm/mach-omap2/board-3430sdp.c5
-rw-r--r--arch/arm/mach-omap2/board-4430sdp.c73
-rw-r--r--arch/arm/mach-omap2/board-cm-t35.c5
-rw-r--r--arch/arm/mach-omap2/board-devkit8000.c3
-rw-r--r--arch/arm/mach-omap2/board-igep0020.c5
-rw-r--r--arch/arm/mach-omap2/board-ldp.c3
-rw-r--r--arch/arm/mach-omap2/board-n8x0.c51
-rw-r--r--arch/arm/mach-omap2/board-omap3beagle.c104
-rw-r--r--arch/arm/mach-omap2/board-omap3evm.c3
-rw-r--r--arch/arm/mach-omap2/board-omap3pandora.c7
-rw-r--r--arch/arm/mach-omap2/board-omap3stalker.c3
-rw-r--r--arch/arm/mach-omap2/board-omap3touchbook.c3
-rw-r--r--arch/arm/mach-omap2/board-omap4panda.c36
-rw-r--r--arch/arm/mach-omap2/board-overo.c5
-rw-r--r--arch/arm/mach-omap2/board-rx51-peripherals.c5
-rw-r--r--arch/arm/mach-omap2/board-zoom-peripherals.c5
-rw-r--r--arch/arm/mach-omap2/clock2420_data.c2
-rw-r--r--arch/arm/mach-omap2/clock2430_data.c2
-rw-r--r--arch/arm/mach-omap2/clock3xxx_data.c2
-rw-r--r--arch/arm/mach-omap2/clockdomain.c110
-rw-r--r--arch/arm/mach-omap2/cm4xxx.c9
-rw-r--r--arch/arm/mach-omap2/cpuidle34xx.c58
-rw-r--r--arch/arm/mach-omap2/devices.c87
-rw-r--r--arch/arm/mach-omap2/hsmmc.c16
-rw-r--r--arch/arm/mach-omap2/hsmmc.h3
-rw-r--r--arch/arm/mach-omap2/id.c38
-rw-r--r--arch/arm/mach-omap2/io.c7
-rw-r--r--arch/arm/mach-omap2/mcbsp.c39
-rw-r--r--arch/arm/mach-omap2/mux.c2
-rw-r--r--arch/arm/mach-omap2/omap4-common.c10
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c579
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_44xx_data.c482
-rw-r--r--arch/arm/mach-omap2/pm-debug.c42
-rw-r--r--arch/arm/mach-omap2/pm.c75
-rw-r--r--arch/arm/mach-omap2/pm.h4
-rw-r--r--arch/arm/mach-omap2/pm34xx.c99
-rw-r--r--arch/arm/mach-omap2/pm_bus.c85
-rw-r--r--arch/arm/mach-omap2/prcm.c29
-rw-r--r--arch/arm/mach-omap2/prm.h18
-rw-r--r--arch/arm/mach-omap2/prm2xxx_3xxx.c110
-rw-r--r--arch/arm/mach-omap2/prm44xx.c116
-rw-r--r--arch/arm/mach-omap2/timer-gp.c6
-rw-r--r--arch/arm/plat-omap/Kconfig2
-rw-r--r--arch/arm/plat-omap/Makefile2
-rw-r--r--arch/arm/plat-omap/dmtimer.c2
-rw-r--r--arch/arm/plat-omap/gpio.c10
-rw-r--r--arch/arm/plat-omap/include/plat/common.h3
-rw-r--r--arch/arm/plat-omap/include/plat/cpu.h5
-rw-r--r--arch/arm/plat-omap/include/plat/i2c.h4
-rw-r--r--arch/arm/plat-omap/include/plat/mmc.h7
-rw-r--r--arch/arm/plat-omap/include/plat/omap_device.h4
-rw-r--r--arch/arm/plat-omap/include/plat/omap_hwmod.h56
-rw-r--r--arch/arm/plat-omap/include/plat/prcm.h2
-rw-r--r--arch/arm/plat-omap/include/plat/uncompress.h1
-rw-r--r--arch/arm/plat-omap/include/plat/usb.h2
-rw-r--r--arch/arm/plat-omap/mcbsp.c13
-rw-r--r--arch/arm/plat-omap/omap_device.c110
-rw-r--r--arch/arm/plat-omap/sram.c13
-rw-r--r--drivers/mmc/host/omap.c2
-rw-r--r--drivers/mmc/host/omap_hsmmc.c18
71 files changed, 2516 insertions, 803 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 553b7cf17bfb..15b603cb577d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -813,7 +813,7 @@ config ARCH_OMAP
813 select GENERIC_CLOCKEVENTS 813 select GENERIC_CLOCKEVENTS
814 select ARCH_HAS_HOLES_MEMORYMODEL 814 select ARCH_HAS_HOLES_MEMORYMODEL
815 help 815 help
816 Support for TI's OMAP platform (OMAP1 and OMAP2). 816 Support for TI's OMAP platform (OMAP1/2/3/4).
817 817
818config PLAT_SPEAR 818config PLAT_SPEAR
819 bool "ST SPEAr" 819 bool "ST SPEAr"
diff --git a/arch/arm/configs/n8x0_defconfig b/arch/arm/configs/n8x0_defconfig
deleted file mode 100644
index 56aebb69411d..000000000000
--- a/arch/arm/configs/n8x0_defconfig
+++ /dev/null
@@ -1,94 +0,0 @@
1CONFIG_EXPERIMENTAL=y
2CONFIG_SYSVIPC=y
3CONFIG_LOG_BUF_SHIFT=14
4CONFIG_BLK_DEV_INITRD=y
5CONFIG_MODULES=y
6CONFIG_MODULE_UNLOAD=y
7# CONFIG_LBDAF is not set
8# CONFIG_BLK_DEV_BSG is not set
9# CONFIG_IOSCHED_DEADLINE is not set
10CONFIG_ARCH_OMAP=y
11CONFIG_ARCH_OMAP2=y
12CONFIG_OMAP_RESET_CLOCKS=y
13# CONFIG_OMAP_MUX is not set
14# CONFIG_OMAP_MCBSP is not set
15CONFIG_OMAP_MBOX_FWK=y
16CONFIG_OMAP_32K_TIMER=y
17CONFIG_ARCH_OMAP2420=y
18CONFIG_MACH_NOKIA_N8X0=y
19CONFIG_AEABI=y
20CONFIG_LEDS=y
21CONFIG_ZBOOT_ROM_TEXT=0x10C08000
22CONFIG_ZBOOT_ROM_BSS=0x10200000
23CONFIG_CMDLINE="root=/dev/mmcblk0p2 console=ttyS2,115200n8 debug earlyprintk rootwait"
24CONFIG_FPE_NWFPE=y
25CONFIG_VFP=y
26CONFIG_PM=y
27CONFIG_PM_RUNTIME=y
28CONFIG_NET=y
29CONFIG_UNIX=y
30CONFIG_INET=y
31# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
32# CONFIG_INET_XFRM_MODE_TUNNEL is not set
33# CONFIG_INET_XFRM_MODE_BEET is not set
34# CONFIG_INET_LRO is not set
35# CONFIG_IPV6 is not set
36CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
37CONFIG_MTD=y
38CONFIG_MTD_CMDLINE_PARTS=y
39CONFIG_MTD_ONENAND=y
40CONFIG_MTD_ONENAND_OMAP2=y
41CONFIG_MTD_ONENAND_OTP=y
42CONFIG_BLK_DEV_RAM=y
43# CONFIG_MISC_DEVICES is not set
44# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
45# CONFIG_INPUT_KEYBOARD is not set
46# CONFIG_INPUT_MOUSE is not set
47CONFIG_SERIAL_8250=y
48CONFIG_SERIAL_8250_CONSOLE=y
49# CONFIG_LEGACY_PTYS is not set
50# CONFIG_HW_RANDOM is not set
51CONFIG_I2C=y
52# CONFIG_I2C_COMPAT is not set
53# CONFIG_I2C_HELPER_AUTO is not set
54CONFIG_I2C_OMAP=y
55CONFIG_SPI=y
56CONFIG_SPI_OMAP24XX=y
57# CONFIG_HWMON is not set
58CONFIG_MENELAUS=y
59CONFIG_REGULATOR=y
60# CONFIG_VGA_CONSOLE is not set
61# CONFIG_HID_SUPPORT is not set
62CONFIG_USB=y
63CONFIG_USB_DEBUG=y
64CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
65CONFIG_USB_DEVICEFS=y
66CONFIG_USB_SUSPEND=y
67# CONFIG_USB_OTG_WHITELIST is not set
68CONFIG_USB_MUSB_HDRC=y
69CONFIG_USB_MUSB_OTG=y
70CONFIG_USB_GADGET_MUSB_HDRC=y
71# CONFIG_MUSB_PIO_ONLY is not set
72CONFIG_USB_MUSB_DEBUG=y
73CONFIG_USB_GADGET=y
74CONFIG_USB_GADGET_DEBUG=y
75CONFIG_USB_GADGET_DEBUG_FILES=y
76CONFIG_USB_ETH=m
77CONFIG_USB_ETH_EEM=y
78CONFIG_MMC=y
79CONFIG_MMC_OMAP=y
80CONFIG_EXT3_FS=y
81CONFIG_INOTIFY=y
82CONFIG_VFAT_FS=y
83CONFIG_TMPFS=y
84CONFIG_JFFS2_FS=y
85CONFIG_JFFS2_SUMMARY=y
86CONFIG_JFFS2_COMPRESSION_OPTIONS=y
87CONFIG_JFFS2_LZO=y
88CONFIG_PRINTK_TIME=y
89CONFIG_DEBUG_KERNEL=y
90CONFIG_DEBUG_INFO=y
91# CONFIG_RCU_CPU_STALL_DETECTOR is not set
92CONFIG_DEBUG_USER=y
93CONFIG_DEBUG_ERRORS=y
94CONFIG_CRC_CCITT=y
diff --git a/arch/arm/configs/omap3_defconfig b/arch/arm/configs/omap2plus_defconfig
index 5db9a6be2054..9ca8df0b5b8e 100644
--- a/arch/arm/configs/omap3_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -53,8 +53,12 @@ CONFIG_MACH_SBC3530=y
53CONFIG_MACH_OMAP_3630SDP=y 53CONFIG_MACH_OMAP_3630SDP=y
54CONFIG_MACH_OMAP_4430SDP=y 54CONFIG_MACH_OMAP_4430SDP=y
55CONFIG_ARM_THUMBEE=y 55CONFIG_ARM_THUMBEE=y
56CONFIG_ARM_L1_CACHE_SHIFT=5
57CONFIG_ARM_ERRATA_411920=y
56CONFIG_NO_HZ=y 58CONFIG_NO_HZ=y
57CONFIG_HIGH_RES_TIMERS=y 59CONFIG_HIGH_RES_TIMERS=y
60CONFIG_SMP=y
61# CONFIG_LOCAL_TIMERS is not set
58CONFIG_AEABI=y 62CONFIG_AEABI=y
59CONFIG_LEDS=y 63CONFIG_LEDS=y
60CONFIG_ZBOOT_ROM_TEXT=0x0 64CONFIG_ZBOOT_ROM_TEXT=0x0
@@ -137,6 +141,8 @@ CONFIG_SMSC_PHY=y
137CONFIG_NET_ETHERNET=y 141CONFIG_NET_ETHERNET=y
138CONFIG_SMC91X=y 142CONFIG_SMC91X=y
139CONFIG_SMSC911X=y 143CONFIG_SMSC911X=y
144CONFIG_KS8851=y
145CONFIG_KS8851_MLL=y
140CONFIG_LIBERTAS=y 146CONFIG_LIBERTAS=y
141CONFIG_LIBERTAS_USB=y 147CONFIG_LIBERTAS_USB=y
142CONFIG_LIBERTAS_SDIO=y 148CONFIG_LIBERTAS_SDIO=y
@@ -218,9 +224,9 @@ CONFIG_USB_DEVICEFS=y
218CONFIG_USB_SUSPEND=y 224CONFIG_USB_SUSPEND=y
219# CONFIG_USB_OTG_WHITELIST is not set 225# CONFIG_USB_OTG_WHITELIST is not set
220CONFIG_USB_MON=y 226CONFIG_USB_MON=y
221CONFIG_USB_MUSB_HDRC=y 227# CONFIG_USB_MUSB_HDRC is not set
222CONFIG_USB_MUSB_OTG=y 228# CONFIG_USB_MUSB_OTG is not set
223CONFIG_USB_GADGET_MUSB_HDRC=y 229# CONFIG_USB_GADGET_MUSB_HDRC is not set
224CONFIG_USB_MUSB_DEBUG=y 230CONFIG_USB_MUSB_DEBUG=y
225CONFIG_USB_WDM=y 231CONFIG_USB_WDM=y
226CONFIG_USB_STORAGE=y 232CONFIG_USB_STORAGE=y
@@ -276,12 +282,11 @@ CONFIG_DEBUG_KERNEL=y
276CONFIG_SCHEDSTATS=y 282CONFIG_SCHEDSTATS=y
277CONFIG_TIMER_STATS=y 283CONFIG_TIMER_STATS=y
278CONFIG_PROVE_LOCKING=y 284CONFIG_PROVE_LOCKING=y
279CONFIG_LOCK_STAT=y 285# CONFIG_LOCK_STAT is not set
280CONFIG_DEBUG_SPINLOCK_SLEEP=y 286CONFIG_DEBUG_SPINLOCK_SLEEP=y
281# CONFIG_DEBUG_BUGVERBOSE is not set 287# CONFIG_DEBUG_BUGVERBOSE is not set
282CONFIG_DEBUG_INFO=y 288CONFIG_DEBUG_INFO=y
283# CONFIG_RCU_CPU_STALL_DETECTOR is not set 289# CONFIG_RCU_CPU_STALL_DETECTOR is not set
284CONFIG_DEBUG_LL=y
285CONFIG_SECURITY=y 290CONFIG_SECURITY=y
286CONFIG_CRYPTO_MICHAEL_MIC=y 291CONFIG_CRYPTO_MICHAEL_MIC=y
287# CONFIG_CRYPTO_ANSI_CPRNG is not set 292# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/arm/configs/omap_4430sdp_defconfig b/arch/arm/configs/omap_4430sdp_defconfig
deleted file mode 100644
index 14c1e18c648f..000000000000
--- a/arch/arm/configs/omap_4430sdp_defconfig
+++ /dev/null
@@ -1,125 +0,0 @@
1CONFIG_EXPERIMENTAL=y
2CONFIG_SYSVIPC=y
3CONFIG_BSD_PROCESS_ACCT=y
4CONFIG_LOG_BUF_SHIFT=14
5CONFIG_BLK_DEV_INITRD=y
6CONFIG_EMBEDDED=y
7# CONFIG_SYSCTL_SYSCALL is not set
8# CONFIG_ELF_CORE is not set
9CONFIG_MODULES=y
10CONFIG_MODULE_UNLOAD=y
11CONFIG_MODVERSIONS=y
12CONFIG_MODULE_SRCVERSION_ALL=y
13# CONFIG_BLK_DEV_BSG is not set
14CONFIG_ARCH_OMAP=y
15CONFIG_ARCH_OMAP4=y
16# CONFIG_ARCH_OMAP2PLUS_TYPICAL is not set
17# CONFIG_ARCH_OMAP2 is not set
18# CONFIG_ARCH_OMAP3 is not set
19# CONFIG_OMAP_MUX is not set
20CONFIG_OMAP_32K_TIMER=y
21CONFIG_OMAP_DM_TIMER=y
22CONFIG_MACH_OMAP_4430SDP=y
23# CONFIG_ARM_THUMB is not set
24CONFIG_PL310_ERRATA_588369=y
25CONFIG_SMP=y
26CONFIG_NR_CPUS=2
27# CONFIG_LOCAL_TIMERS is not set
28CONFIG_PREEMPT=y
29CONFIG_AEABI=y
30CONFIG_ZBOOT_ROM_TEXT=0x0
31CONFIG_ZBOOT_ROM_BSS=0x0
32CONFIG_CMDLINE="root=/dev/ram0 rw mem=128M console=ttyS2,115200n8 initrd=0x81600000,20M ramdisk_size=20480"
33CONFIG_VFP=y
34CONFIG_NEON=y
35CONFIG_BINFMT_MISC=y
36CONFIG_NET=y
37CONFIG_PACKET=y
38CONFIG_INET=y
39CONFIG_IP_PNP=y
40CONFIG_IP_PNP_DHCP=y
41CONFIG_IP_PNP_BOOTP=y
42CONFIG_IP_PNP_RARP=y
43# CONFIG_IPV6 is not set
44# CONFIG_WIRELESS is not set
45CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
46# CONFIG_FW_LOADER is not set
47CONFIG_BLK_DEV_LOOP=y
48CONFIG_BLK_DEV_RAM=y
49CONFIG_BLK_DEV_RAM_SIZE=16384
50# CONFIG_MISC_DEVICES is not set
51CONFIG_NETDEVICES=y
52CONFIG_NET_ETHERNET=y
53CONFIG_KS8851=y
54# CONFIG_NETDEV_1000 is not set
55# CONFIG_NETDEV_10000 is not set
56# CONFIG_WLAN is not set
57# CONFIG_INPUT_MOUSEDEV is not set
58CONFIG_INPUT_EVDEV=y
59# CONFIG_INPUT_KEYBOARD is not set
60# CONFIG_INPUT_MOUSE is not set
61# CONFIG_SERIO is not set
62CONFIG_SERIAL_8250=y
63CONFIG_SERIAL_8250_CONSOLE=y
64CONFIG_SERIAL_8250_NR_UARTS=32
65CONFIG_SERIAL_8250_EXTENDED=y
66CONFIG_SERIAL_8250_MANY_PORTS=y
67CONFIG_SERIAL_8250_SHARE_IRQ=y
68CONFIG_SERIAL_8250_DETECT_IRQ=y
69CONFIG_SERIAL_8250_RSA=y
70# CONFIG_LEGACY_PTYS is not set
71CONFIG_HW_RANDOM=y
72CONFIG_I2C=y
73CONFIG_I2C_CHARDEV=y
74CONFIG_I2C_OMAP=y
75CONFIG_SPI=y
76CONFIG_SPI_OMAP24XX=y
77# CONFIG_HWMON is not set
78CONFIG_WATCHDOG=y
79CONFIG_OMAP_WATCHDOG=y
80CONFIG_TWL4030_CORE=y
81CONFIG_REGULATOR=y
82CONFIG_REGULATOR_TWL4030=y
83# CONFIG_VGA_CONSOLE is not set
84# CONFIG_HID_SUPPORT is not set
85# CONFIG_USB_SUPPORT is not set
86CONFIG_MMC=y
87CONFIG_MMC_OMAP_HS=y
88CONFIG_RTC_CLASS=y
89CONFIG_RTC_DRV_TWL4030=y
90CONFIG_EXT2_FS=y
91CONFIG_EXT3_FS=y
92# CONFIG_EXT3_FS_XATTR is not set
93CONFIG_INOTIFY=y
94CONFIG_QUOTA=y
95CONFIG_QFMT_V2=y
96CONFIG_MSDOS_FS=y
97CONFIG_VFAT_FS=y
98CONFIG_TMPFS=y
99CONFIG_NFS_FS=y
100CONFIG_NFS_V3=y
101CONFIG_NFS_V3_ACL=y
102CONFIG_NFS_V4=y
103CONFIG_ROOT_NFS=y
104CONFIG_PARTITION_ADVANCED=y
105CONFIG_NLS_CODEPAGE_437=y
106CONFIG_NLS_ISO8859_1=y
107# CONFIG_ENABLE_WARN_DEPRECATED is not set
108# CONFIG_ENABLE_MUST_CHECK is not set
109CONFIG_MAGIC_SYSRQ=y
110CONFIG_DEBUG_KERNEL=y
111# CONFIG_DETECT_SOFTLOCKUP is not set
112CONFIG_DETECT_HUNG_TASK=y
113# CONFIG_SCHED_DEBUG is not set
114# CONFIG_DEBUG_PREEMPT is not set
115# CONFIG_DEBUG_BUGVERBOSE is not set
116CONFIG_DEBUG_INFO=y
117# CONFIG_RCU_CPU_STALL_DETECTOR is not set
118# CONFIG_FTRACE is not set
119# CONFIG_ARM_UNWIND is not set
120CONFIG_CRYPTO_ECB=m
121CONFIG_CRYPTO_PCBC=m
122# CONFIG_CRYPTO_ANSI_CPRNG is not set
123CONFIG_CRC_CCITT=y
124CONFIG_CRC_T10DIF=y
125CONFIG_LIBCRC32C=y
diff --git a/arch/arm/configs/omap_generic_2420_defconfig b/arch/arm/configs/omap_generic_2420_defconfig
deleted file mode 100644
index ac08e51180dd..000000000000
--- a/arch/arm/configs/omap_generic_2420_defconfig
+++ /dev/null
@@ -1,37 +0,0 @@
1CONFIG_EXPERIMENTAL=y
2CONFIG_SYSVIPC=y
3CONFIG_LOG_BUF_SHIFT=14
4CONFIG_BLK_DEV_INITRD=y
5CONFIG_MODULES=y
6CONFIG_MODULE_UNLOAD=y
7# CONFIG_BLK_DEV_BSG is not set
8CONFIG_ARCH_OMAP=y
9CONFIG_ARCH_OMAP2=y
10# CONFIG_OMAP_MUX is not set
11CONFIG_MACH_OMAP_GENERIC=y
12CONFIG_ARCH_OMAP2420=y
13CONFIG_LEDS=y
14CONFIG_ZBOOT_ROM_TEXT=0x10C08000
15CONFIG_ZBOOT_ROM_BSS=0x10200000
16CONFIG_FPE_NWFPE=y
17CONFIG_BLK_DEV_RAM=y
18CONFIG_INPUT_EVDEV=y
19# CONFIG_INPUT_KEYBOARD is not set
20# CONFIG_INPUT_MOUSE is not set
21CONFIG_SERIAL_8250=y
22CONFIG_SERIAL_8250_CONSOLE=y
23# CONFIG_LEGACY_PTYS is not set
24CONFIG_WATCHDOG=y
25CONFIG_WATCHDOG_NOWAYOUT=y
26CONFIG_VIDEO_OUTPUT_CONTROL=m
27# CONFIG_VGA_CONSOLE is not set
28CONFIG_EXT2_FS=y
29CONFIG_EXT2_FS_XATTR=y
30CONFIG_INOTIFY=y
31CONFIG_ROMFS_FS=y
32CONFIG_DEBUG_KERNEL=y
33CONFIG_DEBUG_INFO=y
34CONFIG_DEBUG_USER=y
35CONFIG_DEBUG_ERRORS=y
36CONFIG_DEBUG_LL=y
37CONFIG_CRC_CCITT=y
diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile
index facfaeb1ae5c..9a304d854e33 100644
--- a/arch/arm/mach-omap1/Makefile
+++ b/arch/arm/mach-omap1/Makefile
@@ -12,7 +12,7 @@ obj-$(CONFIG_OMAP_MPU_TIMER) += time.o
12obj-$(CONFIG_OMAP_32K_TIMER) += timer32k.o 12obj-$(CONFIG_OMAP_32K_TIMER) += timer32k.o
13 13
14# Power Management 14# Power Management
15obj-$(CONFIG_PM) += pm.o sleep.o 15obj-$(CONFIG_PM) += pm.o sleep.o pm_bus.o
16 16
17# DSP 17# DSP
18obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o 18obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o
diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c
index 311899ff5ffc..7ea75c11653c 100644
--- a/arch/arm/mach-omap1/board-htcherald.c
+++ b/arch/arm/mach-omap1/board-htcherald.c
@@ -30,6 +30,13 @@
30#include <linux/input.h> 30#include <linux/input.h>
31#include <linux/io.h> 31#include <linux/io.h>
32#include <linux/gpio.h> 32#include <linux/gpio.h>
33#include <linux/gpio_keys.h>
34#include <linux/i2c.h>
35#include <linux/i2c-gpio.h>
36#include <linux/htcpld.h>
37#include <linux/leds.h>
38#include <linux/spi/spi.h>
39#include <linux/spi/ads7846.h>
33 40
34#include <asm/mach-types.h> 41#include <asm/mach-types.h>
35#include <asm/mach/arch.h> 42#include <asm/mach/arch.h>
@@ -39,6 +46,7 @@
39#include <plat/board.h> 46#include <plat/board.h>
40#include <plat/keypad.h> 47#include <plat/keypad.h>
41#include <plat/usb.h> 48#include <plat/usb.h>
49#include <plat/mmc.h>
42 50
43#include <mach/irqs.h> 51#include <mach/irqs.h>
44 52
@@ -52,13 +60,123 @@
52#define OMAP_LCDC_CTRL_LCD_EN (1 << 0) 60#define OMAP_LCDC_CTRL_LCD_EN (1 << 0)
53#define OMAP_LCDC_STAT_DONE (1 << 0) 61#define OMAP_LCDC_STAT_DONE (1 << 0)
54 62
55static struct omap_lcd_config htcherald_lcd_config __initdata = { 63/* GPIO definitions for the power button and keyboard slide switch */
56 .ctrl_name = "internal", 64#define HTCHERALD_GPIO_POWER 139
57}; 65#define HTCHERALD_GPIO_SLIDE 174
66#define HTCHERALD_GIRQ_BTNS 141
58 67
59static struct omap_board_config_kernel htcherald_config[] __initdata = { 68/* GPIO definitions for the touchscreen */
60 { OMAP_TAG_LCD, &htcherald_lcd_config }, 69#define HTCHERALD_GPIO_TS 76
61}; 70
71/* HTCPLD definitions */
72
73/*
74 * CPLD Logic
75 *
76 * Chip 3 - 0x03
77 *
78 * Function 7 6 5 4 3 2 1 0
79 * ------------------------------------
80 * DPAD light x x x x x x x 1
81 * SoundDev x x x x 1 x x x
82 * Screen white 1 x x x x x x x
83 * MMC power on x x x x x 1 x x
84 * Happy times (n) 0 x x x x 1 x x
85 *
86 * Chip 4 - 0x04
87 *
88 * Function 7 6 5 4 3 2 1 0
89 * ------------------------------------
90 * Keyboard light x x x x x x x 1
91 * LCD Bright (4) x x x x x 1 1 x
92 * LCD Bright (3) x x x x x 0 1 x
93 * LCD Bright (2) x x x x x 1 0 x
94 * LCD Bright (1) x x x x x 0 0 x
95 * LCD Off x x x x 0 x x x
96 * LCD image (fb) 1 x x x x x x x
97 * LCD image (white) 0 x x x x x x x
98 * Caps lock LED x x 1 x x x x x
99 *
100 * Chip 5 - 0x05
101 *
102 * Function 7 6 5 4 3 2 1 0
103 * ------------------------------------
104 * Red (solid) x x x x x 1 x x
105 * Red (flash) x x x x x x 1 x
106 * Green (GSM flash) x x x x 1 x x x
107 * Green (GSM solid) x x x 1 x x x x
108 * Green (wifi flash) x x 1 x x x x x
109 * Blue (bt flash) x 1 x x x x x x
110 * DPAD Int Enable 1 x x x x x x 0
111 *
112 * (Combinations of the above can be made for different colors.)
113 * The direction pad interrupt enable must be set each time the
114 * interrupt is handled.
115 *
116 * Chip 6 - 0x06
117 *
118 * Function 7 6 5 4 3 2 1 0
119 * ------------------------------------
120 * Vibrator x x x x 1 x x x
121 * Alt LED x x x 1 x x x x
122 * Screen white 1 x x x x x x x
123 * Screen white x x 1 x x x x x
124 * Screen white x 0 x x x x x x
125 * Enable kbd dpad x x x x x x 0 x
126 * Happy Times 0 1 0 x x x 0 x
127 */
128
129/*
130 * HTCPLD GPIO lines start 16 after OMAP_MAX_GPIO_LINES to account
131 * for the 16 MPUIO lines.
132 */
133#define HTCPLD_GPIO_START_OFFSET (OMAP_MAX_GPIO_LINES + 16)
134#define HTCPLD_IRQ(chip, offset) (OMAP_IRQ_END + 8 * (chip) + (offset))
135#define HTCPLD_BASE(chip, offset) \
136 (HTCPLD_GPIO_START_OFFSET + 8 * (chip) + (offset))
137
138#define HTCPLD_GPIO_LED_DPAD HTCPLD_BASE(0, 0)
139#define HTCPLD_GPIO_LED_KBD HTCPLD_BASE(1, 0)
140#define HTCPLD_GPIO_LED_CAPS HTCPLD_BASE(1, 5)
141#define HTCPLD_GPIO_LED_RED_FLASH HTCPLD_BASE(2, 1)
142#define HTCPLD_GPIO_LED_RED_SOLID HTCPLD_BASE(2, 2)
143#define HTCPLD_GPIO_LED_GREEN_FLASH HTCPLD_BASE(2, 3)
144#define HTCPLD_GPIO_LED_GREEN_SOLID HTCPLD_BASE(2, 4)
145#define HTCPLD_GPIO_LED_WIFI HTCPLD_BASE(2, 5)
146#define HTCPLD_GPIO_LED_BT HTCPLD_BASE(2, 6)
147#define HTCPLD_GPIO_LED_VIBRATE HTCPLD_BASE(3, 3)
148#define HTCPLD_GPIO_LED_ALT HTCPLD_BASE(3, 4)
149
150#define HTCPLD_GPIO_RIGHT_KBD HTCPLD_BASE(6, 7)
151#define HTCPLD_GPIO_UP_KBD HTCPLD_BASE(6, 6)
152#define HTCPLD_GPIO_LEFT_KBD HTCPLD_BASE(6, 5)
153#define HTCPLD_GPIO_DOWN_KBD HTCPLD_BASE(6, 4)
154
155#define HTCPLD_GPIO_RIGHT_DPAD HTCPLD_BASE(7, 7)
156#define HTCPLD_GPIO_UP_DPAD HTCPLD_BASE(7, 6)
157#define HTCPLD_GPIO_LEFT_DPAD HTCPLD_BASE(7, 5)
158#define HTCPLD_GPIO_DOWN_DPAD HTCPLD_BASE(7, 4)
159#define HTCPLD_GPIO_ENTER_DPAD HTCPLD_BASE(7, 3)
160
161/*
162 * The htcpld chip requires a gpio write to a specific line
163 * to re-enable interrupts after one has occurred.
164 */
165#define HTCPLD_GPIO_INT_RESET_HI HTCPLD_BASE(2, 7)
166#define HTCPLD_GPIO_INT_RESET_LO HTCPLD_BASE(2, 0)
167
168/* Chip 5 */
169#define HTCPLD_IRQ_RIGHT_KBD HTCPLD_IRQ(0, 7)
170#define HTCPLD_IRQ_UP_KBD HTCPLD_IRQ(0, 6)
171#define HTCPLD_IRQ_LEFT_KBD HTCPLD_IRQ(0, 5)
172#define HTCPLD_IRQ_DOWN_KBD HTCPLD_IRQ(0, 4)
173
174/* Chip 6 */
175#define HTCPLD_IRQ_RIGHT_DPAD HTCPLD_IRQ(1, 7)
176#define HTCPLD_IRQ_UP_DPAD HTCPLD_IRQ(1, 6)
177#define HTCPLD_IRQ_LEFT_DPAD HTCPLD_IRQ(1, 5)
178#define HTCPLD_IRQ_DOWN_DPAD HTCPLD_IRQ(1, 4)
179#define HTCPLD_IRQ_ENTER_DPAD HTCPLD_IRQ(1, 3)
62 180
63/* Keyboard definition */ 181/* Keyboard definition */
64 182
@@ -140,6 +258,129 @@ static struct platform_device kp_device = {
140 .resource = kp_resources, 258 .resource = kp_resources,
141}; 259};
142 260
261/* GPIO buttons for keyboard slide and power button */
262static struct gpio_keys_button herald_gpio_keys_table[] = {
263 {BTN_0, HTCHERALD_GPIO_POWER, 1, "POWER", EV_KEY, 1, 20},
264 {SW_LID, HTCHERALD_GPIO_SLIDE, 0, "SLIDE", EV_SW, 1, 20},
265
266 {KEY_LEFT, HTCPLD_GPIO_LEFT_KBD, 1, "LEFT", EV_KEY, 1, 20},
267 {KEY_RIGHT, HTCPLD_GPIO_RIGHT_KBD, 1, "RIGHT", EV_KEY, 1, 20},
268 {KEY_UP, HTCPLD_GPIO_UP_KBD, 1, "UP", EV_KEY, 1, 20},
269 {KEY_DOWN, HTCPLD_GPIO_DOWN_KBD, 1, "DOWN", EV_KEY, 1, 20},
270
271 {KEY_LEFT, HTCPLD_GPIO_LEFT_DPAD, 1, "DLEFT", EV_KEY, 1, 20},
272 {KEY_RIGHT, HTCPLD_GPIO_RIGHT_DPAD, 1, "DRIGHT", EV_KEY, 1, 20},
273 {KEY_UP, HTCPLD_GPIO_UP_DPAD, 1, "DUP", EV_KEY, 1, 20},
274 {KEY_DOWN, HTCPLD_GPIO_DOWN_DPAD, 1, "DDOWN", EV_KEY, 1, 20},
275 {KEY_ENTER, HTCPLD_GPIO_ENTER_DPAD, 1, "DENTER", EV_KEY, 1, 20},
276};
277
278static struct gpio_keys_platform_data herald_gpio_keys_data = {
279 .buttons = herald_gpio_keys_table,
280 .nbuttons = ARRAY_SIZE(herald_gpio_keys_table),
281 .rep = 1,
282};
283
284static struct platform_device herald_gpiokeys_device = {
285 .name = "gpio-keys",
286 .id = -1,
287 .dev = {
288 .platform_data = &herald_gpio_keys_data,
289 },
290};
291
292/* LEDs for the Herald. These connect to the HTCPLD GPIO device. */
293static struct gpio_led gpio_leds[] = {
294 {"dpad", NULL, HTCPLD_GPIO_LED_DPAD, 0, 0, LEDS_GPIO_DEFSTATE_OFF},
295 {"kbd", NULL, HTCPLD_GPIO_LED_KBD, 0, 0, LEDS_GPIO_DEFSTATE_OFF},
296 {"vibrate", NULL, HTCPLD_GPIO_LED_VIBRATE, 0, 0, LEDS_GPIO_DEFSTATE_OFF},
297 {"green_solid", NULL, HTCPLD_GPIO_LED_GREEN_SOLID, 0, 0, LEDS_GPIO_DEFSTATE_OFF},
298 {"green_flash", NULL, HTCPLD_GPIO_LED_GREEN_FLASH, 0, 0, LEDS_GPIO_DEFSTATE_OFF},
299 {"red_solid", "mmc0", HTCPLD_GPIO_LED_RED_SOLID, 0, 0, LEDS_GPIO_DEFSTATE_OFF},
300 {"red_flash", NULL, HTCPLD_GPIO_LED_RED_FLASH, 0, 0, LEDS_GPIO_DEFSTATE_OFF},
301 {"wifi", NULL, HTCPLD_GPIO_LED_WIFI, 0, 0, LEDS_GPIO_DEFSTATE_OFF},
302 {"bt", NULL, HTCPLD_GPIO_LED_BT, 0, 0, LEDS_GPIO_DEFSTATE_OFF},
303 {"caps", NULL, HTCPLD_GPIO_LED_CAPS, 0, 0, LEDS_GPIO_DEFSTATE_OFF},
304 {"alt", NULL, HTCPLD_GPIO_LED_ALT, 0, 0, LEDS_GPIO_DEFSTATE_OFF},
305};
306
307static struct gpio_led_platform_data gpio_leds_data = {
308 .leds = gpio_leds,
309 .num_leds = ARRAY_SIZE(gpio_leds),
310};
311
312static struct platform_device gpio_leds_device = {
313 .name = "leds-gpio",
314 .id = 0,
315 .dev = {
316 .platform_data = &gpio_leds_data,
317 },
318};
319
320/* HTC PLD chips */
321
322static struct resource htcpld_resources[] = {
323 [0] = {
324 .start = OMAP_GPIO_IRQ(HTCHERALD_GIRQ_BTNS),
325 .end = OMAP_GPIO_IRQ(HTCHERALD_GIRQ_BTNS),
326 .flags = IORESOURCE_IRQ,
327 },
328};
329
330struct htcpld_chip_platform_data htcpld_chips[] = {
331 [0] = {
332 .addr = 0x03,
333 .reset = 0x04,
334 .num_gpios = 8,
335 .gpio_out_base = HTCPLD_BASE(0, 0),
336 .gpio_in_base = HTCPLD_BASE(4, 0),
337 },
338 [1] = {
339 .addr = 0x04,
340 .reset = 0x8e,
341 .num_gpios = 8,
342 .gpio_out_base = HTCPLD_BASE(1, 0),
343 .gpio_in_base = HTCPLD_BASE(5, 0),
344 },
345 [2] = {
346 .addr = 0x05,
347 .reset = 0x80,
348 .num_gpios = 8,
349 .gpio_out_base = HTCPLD_BASE(2, 0),
350 .gpio_in_base = HTCPLD_BASE(6, 0),
351 .irq_base = HTCPLD_IRQ(0, 0),
352 .num_irqs = 8,
353 },
354 [3] = {
355 .addr = 0x06,
356 .reset = 0x40,
357 .num_gpios = 8,
358 .gpio_out_base = HTCPLD_BASE(3, 0),
359 .gpio_in_base = HTCPLD_BASE(7, 0),
360 .irq_base = HTCPLD_IRQ(1, 0),
361 .num_irqs = 8,
362 },
363};
364
365struct htcpld_core_platform_data htcpld_pfdata = {
366 .int_reset_gpio_hi = HTCPLD_GPIO_INT_RESET_HI,
367 .int_reset_gpio_lo = HTCPLD_GPIO_INT_RESET_LO,
368 .i2c_adapter_id = 1,
369
370 .chip = htcpld_chips,
371 .num_chip = ARRAY_SIZE(htcpld_chips),
372};
373
374static struct platform_device htcpld_device = {
375 .name = "i2c-htcpld",
376 .id = -1,
377 .resource = htcpld_resources,
378 .num_resources = ARRAY_SIZE(htcpld_resources),
379 .dev = {
380 .platform_data = &htcpld_pfdata,
381 },
382};
383
143/* USB Device */ 384/* USB Device */
144static struct omap_usb_config htcherald_usb_config __initdata = { 385static struct omap_usb_config htcherald_usb_config __initdata = {
145 .otg = 0, 386 .otg = 0,
@@ -150,14 +391,72 @@ static struct omap_usb_config htcherald_usb_config __initdata = {
150}; 391};
151 392
152/* LCD Device resources */ 393/* LCD Device resources */
394static struct omap_lcd_config htcherald_lcd_config __initdata = {
395 .ctrl_name = "internal",
396};
397
398static struct omap_board_config_kernel htcherald_config[] __initdata = {
399 { OMAP_TAG_LCD, &htcherald_lcd_config },
400};
401
153static struct platform_device lcd_device = { 402static struct platform_device lcd_device = {
154 .name = "lcd_htcherald", 403 .name = "lcd_htcherald",
155 .id = -1, 404 .id = -1,
156}; 405};
157 406
407/* MMC Card */
408#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
409static struct omap_mmc_platform_data htc_mmc1_data = {
410 .nr_slots = 1,
411 .switch_slot = NULL,
412 .slots[0] = {
413 .ocr_mask = MMC_VDD_28_29 | MMC_VDD_30_31 |
414 MMC_VDD_32_33 | MMC_VDD_33_34,
415 .name = "mmcblk",
416 .nomux = 1,
417 .wires = 4,
418 .switch_pin = -1,
419 },
420};
421
422static struct omap_mmc_platform_data *htc_mmc_data[1];
423#endif
424
425
426/* Platform devices for the Herald */
158static struct platform_device *devices[] __initdata = { 427static struct platform_device *devices[] __initdata = {
159 &kp_device, 428 &kp_device,
160 &lcd_device, 429 &lcd_device,
430 &htcpld_device,
431 &gpio_leds_device,
432 &herald_gpiokeys_device,
433};
434
435/*
436 * Touchscreen
437 */
438static const struct ads7846_platform_data htcherald_ts_platform_data = {
439 .model = 7846,
440 .keep_vref_on = 1,
441 .x_plate_ohms = 496,
442 .gpio_pendown = HTCHERALD_GPIO_TS,
443 .pressure_max = 100000,
444 .pressure_min = 5000,
445 .x_min = 528,
446 .x_max = 3760,
447 .y_min = 624,
448 .y_max = 3760,
449};
450
451static struct spi_board_info __initdata htcherald_spi_board_info[] = {
452 {
453 .modalias = "ads7846",
454 .platform_data = &htcherald_ts_platform_data,
455 .irq = OMAP_GPIO_IRQ(HTCHERALD_GPIO_TS),
456 .max_speed_hz = 2500000,
457 .bus_num = 2,
458 .chip_select = 1,
459 }
161}; 460};
162 461
163/* 462/*
@@ -278,6 +577,7 @@ static void __init htcherald_init(void)
278{ 577{
279 printk(KERN_INFO "HTC Herald init.\n"); 578 printk(KERN_INFO "HTC Herald init.\n");
280 579
580 /* Do board initialization before we register all the devices */
281 omap_gpio_init(); 581 omap_gpio_init();
282 582
283 omap_board_config = htcherald_config; 583 omap_board_config = htcherald_config;
@@ -288,6 +588,16 @@ static void __init htcherald_init(void)
288 588
289 htcherald_usb_enable(); 589 htcherald_usb_enable();
290 omap1_usb_init(&htcherald_usb_config); 590 omap1_usb_init(&htcherald_usb_config);
591
592 spi_register_board_info(htcherald_spi_board_info,
593 ARRAY_SIZE(htcherald_spi_board_info));
594
595 omap_register_i2c_bus(1, 100, NULL, 0);
596
597#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
598 htc_mmc_data[0] = &htc_mmc1_data;
599 omap1_init_mmc(htc_mmc_data, 1);
600#endif
291} 601}
292 602
293static void __init htcherald_init_irq(void) 603static void __init htcherald_init_irq(void)
diff --git a/arch/arm/mach-omap1/pm_bus.c b/arch/arm/mach-omap1/pm_bus.c
new file mode 100644
index 000000000000..8b66392be745
--- /dev/null
+++ b/arch/arm/mach-omap1/pm_bus.c
@@ -0,0 +1,98 @@
1/*
2 * Runtime PM support code for OMAP1
3 *
4 * Author: Kevin Hilman, Deep Root Systems, LLC
5 *
6 * Copyright (C) 2010 Texas Instruments, Inc.
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12#include <linux/init.h>
13#include <linux/kernel.h>
14#include <linux/io.h>
15#include <linux/pm_runtime.h>
16#include <linux/platform_device.h>
17#include <linux/mutex.h>
18#include <linux/clk.h>
19#include <linux/err.h>
20
21#include <plat/omap_device.h>
22#include <plat/omap-pm.h>
23
24#ifdef CONFIG_PM_RUNTIME
25static int omap1_pm_runtime_suspend(struct device *dev)
26{
27 struct clk *iclk, *fclk;
28 int ret = 0;
29
30 dev_dbg(dev, "%s\n", __func__);
31
32 ret = pm_generic_runtime_suspend(dev);
33
34 fclk = clk_get(dev, "fck");
35 if (!IS_ERR(fclk)) {
36 clk_disable(fclk);
37 clk_put(fclk);
38 }
39
40 iclk = clk_get(dev, "ick");
41 if (!IS_ERR(iclk)) {
42 clk_disable(iclk);
43 clk_put(iclk);
44 }
45
46 return 0;
47};
48
49static int omap1_pm_runtime_resume(struct device *dev)
50{
51 int ret = 0;
52 struct clk *iclk, *fclk;
53
54 dev_dbg(dev, "%s\n", __func__);
55
56 iclk = clk_get(dev, "ick");
57 if (!IS_ERR(iclk)) {
58 clk_enable(iclk);
59 clk_put(iclk);
60 }
61
62 fclk = clk_get(dev, "fck");
63 if (!IS_ERR(fclk)) {
64 clk_enable(fclk);
65 clk_put(fclk);
66 }
67
68 return pm_generic_runtime_resume(dev);
69};
70
71static int __init omap1_pm_runtime_init(void)
72{
73 const struct dev_pm_ops *pm;
74 struct dev_pm_ops *omap_pm;
75
76 pm = platform_bus_get_pm_ops();
77 if (!pm) {
78 pr_err("%s: unable to get dev_pm_ops from platform_bus\n",
79 __func__);
80 return -ENODEV;
81 }
82
83 omap_pm = kmemdup(pm, sizeof(struct dev_pm_ops), GFP_KERNEL);
84 if (!omap_pm) {
85 pr_err("%s: unable to alloc memory for new dev_pm_ops\n",
86 __func__);
87 return -ENOMEM;
88 }
89
90 omap_pm->runtime_suspend = omap1_pm_runtime_suspend;
91 omap_pm->runtime_resume = omap1_pm_runtime_resume;
92
93 platform_bus_set_pm_ops(omap_pm);
94
95 return 0;
96}
97core_initcall(omap1_pm_runtime_init);
98#endif /* CONFIG_PM_RUNTIME */
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index b48bacf0a7aa..bb85f24c3643 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -35,7 +35,7 @@ config ARCH_OMAP3
35 default y 35 default y
36 select CPU_V7 36 select CPU_V7
37 select USB_ARCH_HAS_EHCI 37 select USB_ARCH_HAS_EHCI
38 select ARM_L1_CACHE_SHIFT_6 38 select ARM_L1_CACHE_SHIFT_6 if !ARCH_OMAP4
39 39
40config ARCH_OMAP4 40config ARCH_OMAP4
41 bool "TI OMAP4" 41 bool "TI OMAP4"
@@ -43,6 +43,8 @@ config ARCH_OMAP4
43 depends on ARCH_OMAP2PLUS 43 depends on ARCH_OMAP2PLUS
44 select CPU_V7 44 select CPU_V7
45 select ARM_GIC 45 select ARM_GIC
46 select PL310_ERRATA_588369
47 select ARM_ERRATA_720789
46 48
47comment "OMAP Core Type" 49comment "OMAP Core Type"
48 depends on ARCH_OMAP2 50 depends on ARCH_OMAP2
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 88d3a1e920f5..e599ae2a5de4 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -5,7 +5,7 @@
5# Common support 5# Common support
6obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o pm.o 6obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o pm.o
7 7
8omap-2-3-common = irq.o sdrc.o 8omap-2-3-common = irq.o sdrc.o prm2xxx_3xxx.o
9hwmod-common = omap_hwmod.o \ 9hwmod-common = omap_hwmod.o \
10 omap_hwmod_common_data.o 10 omap_hwmod_common_data.o
11prcm-common = prcm.o powerdomain.o 11prcm-common = prcm.o powerdomain.o
@@ -15,7 +15,7 @@ clock-common = clock.o clock_common_data.o \
15 15
16obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(prcm-common) $(hwmod-common) 16obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(prcm-common) $(hwmod-common)
17obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(prcm-common) $(hwmod-common) 17obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(prcm-common) $(hwmod-common)
18obj-$(CONFIG_ARCH_OMAP4) += $(prcm-common) $(hwmod-common) 18obj-$(CONFIG_ARCH_OMAP4) += $(prcm-common) prm44xx.o $(hwmod-common)
19 19
20obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o 20obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
21 21
@@ -49,14 +49,18 @@ obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o
49# Power Management 49# Power Management
50ifeq ($(CONFIG_PM),y) 50ifeq ($(CONFIG_PM),y)
51obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o 51obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o
52obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o 52obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o pm_bus.o
53obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o cpuidle34xx.o 53obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o cpuidle34xx.o pm_bus.o
54obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o 54obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o pm_bus.o
55obj-$(CONFIG_PM_DEBUG) += pm-debug.o 55obj-$(CONFIG_PM_DEBUG) += pm-debug.o
56 56
57AFLAGS_sleep24xx.o :=-Wa,-march=armv6 57AFLAGS_sleep24xx.o :=-Wa,-march=armv6
58AFLAGS_sleep34xx.o :=-Wa,-march=armv7-a 58AFLAGS_sleep34xx.o :=-Wa,-march=armv7-a
59 59
60ifeq ($(CONFIG_PM_VERBOSE),y)
61CFLAGS_pm_bus.o += -DDEBUG
62endif
63
60endif 64endif
61 65
62# PRCM 66# PRCM
@@ -87,6 +91,7 @@ obj-$(CONFIG_ARCH_OMAP2430) += opp2430_data.o
87obj-$(CONFIG_ARCH_OMAP2420) += omap_hwmod_2420_data.o 91obj-$(CONFIG_ARCH_OMAP2420) += omap_hwmod_2420_data.o
88obj-$(CONFIG_ARCH_OMAP2430) += omap_hwmod_2430_data.o 92obj-$(CONFIG_ARCH_OMAP2430) += omap_hwmod_2430_data.o
89obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o 93obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o
94obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o
90 95
91# EMU peripherals 96# EMU peripherals
92obj-$(CONFIG_OMAP3_EMU) += emu.o 97obj-$(CONFIG_OMAP3_EMU) += emu.o
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 8538e4131d27..fc178a022dd2 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -19,6 +19,7 @@
19#include <linux/mtd/mtd.h> 19#include <linux/mtd/mtd.h>
20#include <linux/mtd/partitions.h> 20#include <linux/mtd/partitions.h>
21#include <linux/mtd/physmap.h> 21#include <linux/mtd/physmap.h>
22#include <linux/mmc/host.h>
22#include <linux/delay.h> 23#include <linux/delay.h>
23#include <linux/i2c/twl.h> 24#include <linux/i2c/twl.h>
24#include <linux/err.h> 25#include <linux/err.h>
@@ -190,7 +191,7 @@ static int __init omap2430_i2c_init(void)
190static struct omap2_hsmmc_info mmc[] __initdata = { 191static struct omap2_hsmmc_info mmc[] __initdata = {
191 { 192 {
192 .mmc = 1, 193 .mmc = 1,
193 .wires = 4, 194 .caps = MMC_CAP_4_BIT_DATA,
194 .gpio_cd = -EINVAL, 195 .gpio_cd = -EINVAL,
195 .gpio_wp = -EINVAL, 196 .gpio_wp = -EINVAL,
196 .ext_clock = 1, 197 .ext_clock = 1,
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index 67b95b5f1a2f..3eb9839e33ed 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -24,6 +24,7 @@
24#include <linux/regulator/machine.h> 24#include <linux/regulator/machine.h>
25#include <linux/io.h> 25#include <linux/io.h>
26#include <linux/gpio.h> 26#include <linux/gpio.h>
27#include <linux/mmc/host.h>
27 28
28#include <mach/hardware.h> 29#include <mach/hardware.h>
29#include <asm/mach-types.h> 30#include <asm/mach-types.h>
@@ -353,12 +354,12 @@ static struct omap2_hsmmc_info mmc[] = {
353 /* 8 bits (default) requires S6.3 == ON, 354 /* 8 bits (default) requires S6.3 == ON,
354 * so the SIM card isn't used; else 4 bits. 355 * so the SIM card isn't used; else 4 bits.
355 */ 356 */
356 .wires = 8, 357 .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
357 .gpio_wp = 4, 358 .gpio_wp = 4,
358 }, 359 },
359 { 360 {
360 .mmc = 2, 361 .mmc = 2,
361 .wires = 8, 362 .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
362 .gpio_wp = 7, 363 .gpio_wp = 7,
363 }, 364 },
364 {} /* Terminator */ 365 {} /* Terminator */
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 9447644774c2..1bed1e666a60 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -20,6 +20,7 @@
20#include <linux/usb/otg.h> 20#include <linux/usb/otg.h>
21#include <linux/spi/spi.h> 21#include <linux/spi/spi.h>
22#include <linux/i2c/twl.h> 22#include <linux/i2c/twl.h>
23#include <linux/gpio_keys.h>
23#include <linux/regulator/machine.h> 24#include <linux/regulator/machine.h>
24#include <linux/leds.h> 25#include <linux/leds.h>
25 26
@@ -40,6 +41,8 @@
40#define ETH_KS8851_IRQ 34 41#define ETH_KS8851_IRQ 34
41#define ETH_KS8851_POWER_ON 48 42#define ETH_KS8851_POWER_ON 48
42#define ETH_KS8851_QUART 138 43#define ETH_KS8851_QUART 138
44#define OMAP4_SFH7741_SENSOR_OUTPUT_GPIO 184
45#define OMAP4_SFH7741_ENABLE_GPIO 188
43 46
44static struct gpio_led sdp4430_gpio_leds[] = { 47static struct gpio_led sdp4430_gpio_leds[] = {
45 { 48 {
@@ -77,11 +80,47 @@ static struct gpio_led sdp4430_gpio_leds[] = {
77 80
78}; 81};
79 82
83static struct gpio_keys_button sdp4430_gpio_keys[] = {
84 {
85 .desc = "Proximity Sensor",
86 .type = EV_SW,
87 .code = SW_FRONT_PROXIMITY,
88 .gpio = OMAP4_SFH7741_SENSOR_OUTPUT_GPIO,
89 .active_low = 0,
90 }
91};
92
80static struct gpio_led_platform_data sdp4430_led_data = { 93static struct gpio_led_platform_data sdp4430_led_data = {
81 .leds = sdp4430_gpio_leds, 94 .leds = sdp4430_gpio_leds,
82 .num_leds = ARRAY_SIZE(sdp4430_gpio_leds), 95 .num_leds = ARRAY_SIZE(sdp4430_gpio_leds),
83}; 96};
84 97
98static int omap_prox_activate(struct device *dev)
99{
100 gpio_set_value(OMAP4_SFH7741_ENABLE_GPIO , 1);
101 return 0;
102}
103
104static void omap_prox_deactivate(struct device *dev)
105{
106 gpio_set_value(OMAP4_SFH7741_ENABLE_GPIO , 0);
107}
108
109static struct gpio_keys_platform_data sdp4430_gpio_keys_data = {
110 .buttons = sdp4430_gpio_keys,
111 .nbuttons = ARRAY_SIZE(sdp4430_gpio_keys),
112 .enable = omap_prox_activate,
113 .disable = omap_prox_deactivate,
114};
115
116static struct platform_device sdp4430_gpio_keys_device = {
117 .name = "gpio-keys",
118 .id = -1,
119 .dev = {
120 .platform_data = &sdp4430_gpio_keys_data,
121 },
122};
123
85static struct platform_device sdp4430_leds_gpio = { 124static struct platform_device sdp4430_leds_gpio = {
86 .name = "leds-gpio", 125 .name = "leds-gpio",
87 .id = -1, 126 .id = -1,
@@ -161,6 +200,7 @@ static struct platform_device sdp4430_lcd_device = {
161 200
162static struct platform_device *sdp4430_devices[] __initdata = { 201static struct platform_device *sdp4430_devices[] __initdata = {
163 &sdp4430_lcd_device, 202 &sdp4430_lcd_device,
203 &sdp4430_gpio_keys_device,
164 &sdp4430_leds_gpio, 204 &sdp4430_leds_gpio,
165}; 205};
166 206
@@ -193,12 +233,12 @@ static struct omap_musb_board_data musb_board_data = {
193static struct omap2_hsmmc_info mmc[] = { 233static struct omap2_hsmmc_info mmc[] = {
194 { 234 {
195 .mmc = 1, 235 .mmc = 1,
196 .wires = 8, 236 .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
197 .gpio_wp = -EINVAL, 237 .gpio_wp = -EINVAL,
198 }, 238 },
199 { 239 {
200 .mmc = 2, 240 .mmc = 2,
201 .wires = 8, 241 .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
202 .gpio_cd = -EINVAL, 242 .gpio_cd = -EINVAL,
203 .gpio_wp = -EINVAL, 243 .gpio_wp = -EINVAL,
204 .nonremovable = true, 244 .nonremovable = true,
@@ -412,6 +452,11 @@ static struct i2c_board_info __initdata sdp4430_i2c_3_boardinfo[] = {
412 I2C_BOARD_INFO("tmp105", 0x48), 452 I2C_BOARD_INFO("tmp105", 0x48),
413 }, 453 },
414}; 454};
455static struct i2c_board_info __initdata sdp4430_i2c_4_boardinfo[] = {
456 {
457 I2C_BOARD_INFO("hmc5843", 0x1e),
458 },
459};
415static int __init omap4_i2c_init(void) 460static int __init omap4_i2c_init(void)
416{ 461{
417 /* 462 /*
@@ -423,14 +468,36 @@ static int __init omap4_i2c_init(void)
423 omap_register_i2c_bus(2, 400, NULL, 0); 468 omap_register_i2c_bus(2, 400, NULL, 0);
424 omap_register_i2c_bus(3, 400, sdp4430_i2c_3_boardinfo, 469 omap_register_i2c_bus(3, 400, sdp4430_i2c_3_boardinfo,
425 ARRAY_SIZE(sdp4430_i2c_3_boardinfo)); 470 ARRAY_SIZE(sdp4430_i2c_3_boardinfo));
426 omap_register_i2c_bus(4, 400, NULL, 0); 471 omap_register_i2c_bus(4, 400, sdp4430_i2c_4_boardinfo,
472 ARRAY_SIZE(sdp4430_i2c_4_boardinfo));
427 return 0; 473 return 0;
428} 474}
475
476static void __init omap_sfh7741prox_init(void)
477{
478 int error;
479
480 error = gpio_request(OMAP4_SFH7741_ENABLE_GPIO, "sfh7741");
481 if (error < 0) {
482 pr_err("%s:failed to request GPIO %d, error %d\n",
483 __func__, OMAP4_SFH7741_ENABLE_GPIO, error);
484 return;
485 }
486
487 error = gpio_direction_output(OMAP4_SFH7741_ENABLE_GPIO , 0);
488 if (error < 0) {
489 pr_err("%s: GPIO configuration failed: GPIO %d,error %d\n",
490 __func__, OMAP4_SFH7741_ENABLE_GPIO, error);
491 gpio_free(OMAP4_SFH7741_ENABLE_GPIO);
492 }
493}
494
429static void __init omap_4430sdp_init(void) 495static void __init omap_4430sdp_init(void)
430{ 496{
431 int status; 497 int status;
432 498
433 omap4_i2c_init(); 499 omap4_i2c_init();
500 omap_sfh7741prox_init();
434 platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices)); 501 platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices));
435 omap_serial_init(); 502 omap_serial_init();
436 omap4_twl6030_hsmmc_init(mmc); 503 omap4_twl6030_hsmmc_init(mmc);
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index e10bc109415c..b72009a50f01 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -31,6 +31,7 @@
31#include <linux/i2c/at24.h> 31#include <linux/i2c/at24.h>
32#include <linux/i2c/twl.h> 32#include <linux/i2c/twl.h>
33#include <linux/regulator/machine.h> 33#include <linux/regulator/machine.h>
34#include <linux/mmc/host.h>
34 35
35#include <linux/spi/spi.h> 36#include <linux/spi/spi.h>
36#include <linux/spi/tdo24m.h> 37#include <linux/spi/tdo24m.h>
@@ -579,14 +580,14 @@ static struct twl4030_keypad_data cm_t35_kp_data = {
579static struct omap2_hsmmc_info mmc[] = { 580static struct omap2_hsmmc_info mmc[] = {
580 { 581 {
581 .mmc = 1, 582 .mmc = 1,
582 .wires = 4, 583 .caps = MMC_CAP_4_BIT_DATA,
583 .gpio_cd = -EINVAL, 584 .gpio_cd = -EINVAL,
584 .gpio_wp = -EINVAL, 585 .gpio_wp = -EINVAL,
585 586
586 }, 587 },
587 { 588 {
588 .mmc = 2, 589 .mmc = 2,
589 .wires = 4, 590 .caps = MMC_CAP_4_BIT_DATA,
590 .transceiver = 1, 591 .transceiver = 1,
591 .gpio_cd = -EINVAL, 592 .gpio_cd = -EINVAL,
592 .gpio_wp = -EINVAL, 593 .gpio_wp = -EINVAL,
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index a07086d6a0b2..de5e2c2f4e80 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -28,6 +28,7 @@
28#include <linux/mtd/mtd.h> 28#include <linux/mtd/mtd.h>
29#include <linux/mtd/partitions.h> 29#include <linux/mtd/partitions.h>
30#include <linux/mtd/nand.h> 30#include <linux/mtd/nand.h>
31#include <linux/mmc/host.h>
31 32
32#include <linux/regulator/machine.h> 33#include <linux/regulator/machine.h>
33#include <linux/i2c/twl.h> 34#include <linux/i2c/twl.h>
@@ -105,7 +106,7 @@ static struct omap_nand_platform_data devkit8000_nand_data = {
105static struct omap2_hsmmc_info mmc[] = { 106static struct omap2_hsmmc_info mmc[] = {
106 { 107 {
107 .mmc = 1, 108 .mmc = 1,
108 .wires = 8, 109 .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
109 .gpio_wp = 29, 110 .gpio_wp = 29,
110 }, 111 },
111 {} /* Terminator */ 112 {} /* Terminator */
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index 175f04339761..f3f028056916 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -20,6 +20,7 @@
20 20
21#include <linux/regulator/machine.h> 21#include <linux/regulator/machine.h>
22#include <linux/i2c/twl.h> 22#include <linux/i2c/twl.h>
23#include <linux/mmc/host.h>
23 24
24#include <asm/mach-types.h> 25#include <asm/mach-types.h>
25#include <asm/mach/arch.h> 26#include <asm/mach/arch.h>
@@ -248,13 +249,13 @@ static struct regulator_init_data igep2_vmmc2 = {
248static struct omap2_hsmmc_info mmc[] = { 249static struct omap2_hsmmc_info mmc[] = {
249 { 250 {
250 .mmc = 1, 251 .mmc = 1,
251 .wires = 4, 252 .caps = MMC_CAP_4_BIT_DATA,
252 .gpio_cd = -EINVAL, 253 .gpio_cd = -EINVAL,
253 .gpio_wp = -EINVAL, 254 .gpio_wp = -EINVAL,
254 }, 255 },
255 { 256 {
256 .mmc = 2, 257 .mmc = 2,
257 .wires = 4, 258 .caps = MMC_CAP_4_BIT_DATA,
258 .gpio_cd = -EINVAL, 259 .gpio_cd = -EINVAL,
259 .gpio_wp = -EINVAL, 260 .gpio_wp = -EINVAL,
260 }, 261 },
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index 00d9b13b01c5..58698e359ccf 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -27,6 +27,7 @@
27#include <linux/i2c/twl.h> 27#include <linux/i2c/twl.h>
28#include <linux/io.h> 28#include <linux/io.h>
29#include <linux/smsc911x.h> 29#include <linux/smsc911x.h>
30#include <linux/mmc/host.h>
30 31
31#include <mach/hardware.h> 32#include <mach/hardware.h>
32#include <asm/mach-types.h> 33#include <asm/mach-types.h>
@@ -362,7 +363,7 @@ static int __init omap_i2c_init(void)
362static struct omap2_hsmmc_info mmc[] __initdata = { 363static struct omap2_hsmmc_info mmc[] __initdata = {
363 { 364 {
364 .mmc = 1, 365 .mmc = 1,
365 .wires = 4, 366 .caps = MMC_CAP_4_BIT_DATA,
366 .gpio_cd = -EINVAL, 367 .gpio_cd = -EINVAL,
367 .gpio_wp = -EINVAL, 368 .gpio_wp = -EINVAL,
368 }, 369 },
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index a3e2b49aa39f..7a93bd5b24c5 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -20,6 +20,7 @@
20#include <linux/i2c.h> 20#include <linux/i2c.h>
21#include <linux/spi/spi.h> 21#include <linux/spi/spi.h>
22#include <linux/usb/musb.h> 22#include <linux/usb/musb.h>
23#include <sound/tlv320aic3x.h>
23 24
24#include <asm/mach/arch.h> 25#include <asm/mach/arch.h>
25#include <asm/mach-types.h> 26#include <asm/mach-types.h>
@@ -487,7 +488,7 @@ static struct omap_mmc_platform_data mmc1_data = {
487 .max_freq = 24000000, 488 .max_freq = 24000000,
488 .dma_mask = 0xffffffff, 489 .dma_mask = 0xffffffff,
489 .slots[0] = { 490 .slots[0] = {
490 .wires = 4, 491 .caps = MMC_CAP_4_BIT_DATA,
491 .set_power = n8x0_mmc_set_power, 492 .set_power = n8x0_mmc_set_power,
492 .set_bus_mode = n8x0_mmc_set_bus_mode, 493 .set_bus_mode = n8x0_mmc_set_bus_mode,
493 .get_cover_state = n8x0_mmc_get_cover_state, 494 .get_cover_state = n8x0_mmc_get_cover_state,
@@ -614,29 +615,35 @@ static int n8x0_menelaus_late_init(struct device *dev)
614 return 0; 615 return 0;
615} 616}
616 617
617static struct i2c_board_info __initdata n8x0_i2c_board_info_1[] = { 618#else
619static int n8x0_menelaus_late_init(struct device *dev)
620{
621 return 0;
622}
623#endif
624
625static struct menelaus_platform_data n8x0_menelaus_platform_data __initdata = {
626 .late_init = n8x0_menelaus_late_init,
627};
628
629static struct i2c_board_info __initdata n8x0_i2c_board_info_1[] __initdata = {
618 { 630 {
619 I2C_BOARD_INFO("menelaus", 0x72), 631 I2C_BOARD_INFO("menelaus", 0x72),
620 .irq = INT_24XX_SYS_NIRQ, 632 .irq = INT_24XX_SYS_NIRQ,
633 .platform_data = &n8x0_menelaus_platform_data,
621 }, 634 },
622}; 635};
623 636
624static struct menelaus_platform_data n8x0_menelaus_platform_data = { 637static struct aic3x_pdata n810_aic33_data __initdata = {
625 .late_init = n8x0_menelaus_late_init, 638 .gpio_reset = 118,
626}; 639};
627 640
628static void __init n8x0_menelaus_init(void) 641static struct i2c_board_info n810_i2c_board_info_2[] __initdata = {
629{ 642 {
630 n8x0_i2c_board_info_1[0].platform_data = &n8x0_menelaus_platform_data; 643 I2C_BOARD_INFO("tlv320aic3x", 0x18),
631 omap_register_i2c_bus(1, 400, n8x0_i2c_board_info_1, 644 .platform_data = &n810_aic33_data,
632 ARRAY_SIZE(n8x0_i2c_board_info_1)); 645 },
633} 646};
634
635#else
636static inline void __init n8x0_menelaus_init(void)
637{
638}
639#endif
640 647
641static void __init n8x0_map_io(void) 648static void __init n8x0_map_io(void)
642{ 649{
@@ -653,6 +660,11 @@ static void __init n8x0_init_irq(void)
653 660
654#ifdef CONFIG_OMAP_MUX 661#ifdef CONFIG_OMAP_MUX
655static struct omap_board_mux board_mux[] __initdata = { 662static struct omap_board_mux board_mux[] __initdata = {
663 /* I2S codec port pins for McBSP block */
664 OMAP2420_MUX(EAC_AC_SCLK, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
665 OMAP2420_MUX(EAC_AC_FS, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
666 OMAP2420_MUX(EAC_AC_DIN, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
667 OMAP2420_MUX(EAC_AC_DOUT, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT),
656 { .reg_offset = OMAP_MUX_TERMINATOR }, 668 { .reg_offset = OMAP_MUX_TERMINATOR },
657}; 669};
658#else 670#else
@@ -665,9 +677,14 @@ static void __init n8x0_init_machine(void)
665 /* FIXME: add n810 spi devices */ 677 /* FIXME: add n810 spi devices */
666 spi_register_board_info(n800_spi_board_info, 678 spi_register_board_info(n800_spi_board_info,
667 ARRAY_SIZE(n800_spi_board_info)); 679 ARRAY_SIZE(n800_spi_board_info));
680 omap_register_i2c_bus(1, 400, n8x0_i2c_board_info_1,
681 ARRAY_SIZE(n8x0_i2c_board_info_1));
682 omap_register_i2c_bus(2, 400, NULL, 0);
683 if (machine_is_nokia_n810())
684 i2c_register_board_info(2, n810_i2c_board_info_2,
685 ARRAY_SIZE(n810_i2c_board_info_2));
668 686
669 omap_serial_init(); 687 omap_serial_init();
670 n8x0_menelaus_init();
671 n8x0_onenand_init(); 688 n8x0_onenand_init();
672 n8x0_mmc_init(); 689 n8x0_mmc_init();
673 n8x0_usb_init(); 690 n8x0_usb_init();
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 87969c7df652..7e7048878649 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -27,6 +27,7 @@
27#include <linux/mtd/mtd.h> 27#include <linux/mtd/mtd.h>
28#include <linux/mtd/partitions.h> 28#include <linux/mtd/partitions.h>
29#include <linux/mtd/nand.h> 29#include <linux/mtd/nand.h>
30#include <linux/mmc/host.h>
30 31
31#include <linux/regulator/machine.h> 32#include <linux/regulator/machine.h>
32#include <linux/i2c/twl.h> 33#include <linux/i2c/twl.h>
@@ -50,6 +51,93 @@
50 51
51#define NAND_BLOCK_SIZE SZ_128K 52#define NAND_BLOCK_SIZE SZ_128K
52 53
54/*
55 * OMAP3 Beagle revision
56 * Run time detection of Beagle revision is done by reading GPIO.
57 * GPIO ID -
58 * AXBX = GPIO173, GPIO172, GPIO171: 1 1 1
59 * C1_3 = GPIO173, GPIO172, GPIO171: 1 1 0
60 * C4 = GPIO173, GPIO172, GPIO171: 1 0 1
61 * XM = GPIO173, GPIO172, GPIO171: 0 0 0
62 */
63enum {
64 OMAP3BEAGLE_BOARD_UNKN = 0,
65 OMAP3BEAGLE_BOARD_AXBX,
66 OMAP3BEAGLE_BOARD_C1_3,
67 OMAP3BEAGLE_BOARD_C4,
68 OMAP3BEAGLE_BOARD_XM,
69};
70
71static u8 omap3_beagle_version;
72
73static u8 omap3_beagle_get_rev(void)
74{
75 return omap3_beagle_version;
76}
77
78static void __init omap3_beagle_init_rev(void)
79{
80 int ret;
81 u16 beagle_rev = 0;
82
83 omap_mux_init_gpio(171, OMAP_PIN_INPUT_PULLUP);
84 omap_mux_init_gpio(172, OMAP_PIN_INPUT_PULLUP);
85 omap_mux_init_gpio(173, OMAP_PIN_INPUT_PULLUP);
86
87 ret = gpio_request(171, "rev_id_0");
88 if (ret < 0)
89 goto fail0;
90
91 ret = gpio_request(172, "rev_id_1");
92 if (ret < 0)
93 goto fail1;
94
95 ret = gpio_request(173, "rev_id_2");
96 if (ret < 0)
97 goto fail2;
98
99 gpio_direction_input(171);
100 gpio_direction_input(172);
101 gpio_direction_input(173);
102
103 beagle_rev = gpio_get_value(171) | (gpio_get_value(172) << 1)
104 | (gpio_get_value(173) << 2);
105
106 switch (beagle_rev) {
107 case 7:
108 printk(KERN_INFO "OMAP3 Beagle Rev: Ax/Bx\n");
109 omap3_beagle_version = OMAP3BEAGLE_BOARD_AXBX;
110 break;
111 case 6:
112 printk(KERN_INFO "OMAP3 Beagle Rev: C1/C2/C3\n");
113 omap3_beagle_version = OMAP3BEAGLE_BOARD_C1_3;
114 break;
115 case 5:
116 printk(KERN_INFO "OMAP3 Beagle Rev: C4\n");
117 omap3_beagle_version = OMAP3BEAGLE_BOARD_C4;
118 break;
119 case 0:
120 printk(KERN_INFO "OMAP3 Beagle Rev: xM\n");
121 omap3_beagle_version = OMAP3BEAGLE_BOARD_XM;
122 break;
123 default:
124 printk(KERN_INFO "OMAP3 Beagle Rev: unknown %hd\n", beagle_rev);
125 omap3_beagle_version = OMAP3BEAGLE_BOARD_UNKN;
126 }
127
128 return;
129
130fail2:
131 gpio_free(172);
132fail1:
133 gpio_free(171);
134fail0:
135 printk(KERN_ERR "Unable to get revision detection GPIO pins\n");
136 omap3_beagle_version = OMAP3BEAGLE_BOARD_UNKN;
137
138 return;
139}
140
53static struct mtd_partition omap3beagle_nand_partitions[] = { 141static struct mtd_partition omap3beagle_nand_partitions[] = {
54 /* All the partition sizes are listed in terms of NAND block size */ 142 /* All the partition sizes are listed in terms of NAND block size */
55 { 143 {
@@ -166,7 +254,7 @@ static void __init beagle_display_init(void)
166static struct omap2_hsmmc_info mmc[] = { 254static struct omap2_hsmmc_info mmc[] = {
167 { 255 {
168 .mmc = 1, 256 .mmc = 1,
169 .wires = 8, 257 .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
170 .gpio_wp = 29, 258 .gpio_wp = 29,
171 }, 259 },
172 {} /* Terminator */ 260 {} /* Terminator */
@@ -185,7 +273,10 @@ static struct gpio_led gpio_leds[];
185static int beagle_twl_gpio_setup(struct device *dev, 273static int beagle_twl_gpio_setup(struct device *dev,
186 unsigned gpio, unsigned ngpio) 274 unsigned gpio, unsigned ngpio)
187{ 275{
188 if (system_rev >= 0x20 && system_rev <= 0x34301000) { 276 if (omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_XM) {
277 mmc[0].gpio_wp = -EINVAL;
278 } else if ((omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_C1_3) ||
279 (omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_C4)) {
189 omap_mux_init_gpio(23, OMAP_PIN_INPUT); 280 omap_mux_init_gpio(23, OMAP_PIN_INPUT);
190 mmc[0].gpio_wp = 23; 281 mmc[0].gpio_wp = 23;
191 } else { 282 } else {
@@ -322,13 +413,19 @@ static struct i2c_board_info __initdata beagle_i2c_boardinfo[] = {
322 }, 413 },
323}; 414};
324 415
416static struct i2c_board_info __initdata beagle_i2c_eeprom[] = {
417 {
418 I2C_BOARD_INFO("eeprom", 0x50),
419 },
420};
421
325static int __init omap3_beagle_i2c_init(void) 422static int __init omap3_beagle_i2c_init(void)
326{ 423{
327 omap_register_i2c_bus(1, 2600, beagle_i2c_boardinfo, 424 omap_register_i2c_bus(1, 2600, beagle_i2c_boardinfo,
328 ARRAY_SIZE(beagle_i2c_boardinfo)); 425 ARRAY_SIZE(beagle_i2c_boardinfo));
329 /* Bus 3 is attached to the DVI port where devices like the pico DLP 426 /* Bus 3 is attached to the DVI port where devices like the pico DLP
330 * projector don't work reliably with 400kHz */ 427 * projector don't work reliably with 400kHz */
331 omap_register_i2c_bus(3, 100, NULL, 0); 428 omap_register_i2c_bus(3, 100, beagle_i2c_eeprom, ARRAY_SIZE(beagle_i2c_eeprom));
332 return 0; 429 return 0;
333} 430}
334 431
@@ -464,6 +561,7 @@ static struct omap_musb_board_data musb_board_data = {
464static void __init omap3_beagle_init(void) 561static void __init omap3_beagle_init(void)
465{ 562{
466 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); 563 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
564 omap3_beagle_init_rev();
467 omap3_beagle_i2c_init(); 565 omap3_beagle_i2c_init();
468 platform_add_devices(omap3_beagle_devices, 566 platform_add_devices(omap3_beagle_devices,
469 ARRAY_SIZE(omap3_beagle_devices)); 567 ARRAY_SIZE(omap3_beagle_devices));
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index f76d9c0a47a1..523ba551ee7b 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -31,6 +31,7 @@
31#include <linux/smsc911x.h> 31#include <linux/smsc911x.h>
32 32
33#include <linux/regulator/machine.h> 33#include <linux/regulator/machine.h>
34#include <linux/mmc/host.h>
34 35
35#include <mach/hardware.h> 36#include <mach/hardware.h>
36#include <asm/mach-types.h> 37#include <asm/mach-types.h>
@@ -370,7 +371,7 @@ static struct regulator_init_data omap3evm_vsim = {
370static struct omap2_hsmmc_info mmc[] = { 371static struct omap2_hsmmc_info mmc[] = {
371 { 372 {
372 .mmc = 1, 373 .mmc = 1,
373 .wires = 4, 374 .caps = MMC_CAP_4_BIT_DATA,
374 .gpio_cd = -EINVAL, 375 .gpio_cd = -EINVAL,
375 .gpio_wp = 63, 376 .gpio_wp = 63,
376 }, 377 },
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index dd3af2be13be..2d2e6fc127ac 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -32,6 +32,7 @@
32#include <linux/input.h> 32#include <linux/input.h>
33#include <linux/input/matrix_keypad.h> 33#include <linux/input/matrix_keypad.h>
34#include <linux/gpio_keys.h> 34#include <linux/gpio_keys.h>
35#include <linux/mmc/host.h>
35#include <linux/mmc/card.h> 36#include <linux/mmc/card.h>
36 37
37#include <asm/mach-types.h> 38#include <asm/mach-types.h>
@@ -276,14 +277,14 @@ static void pandora_wl1251_init_card(struct mmc_card *card)
276static struct omap2_hsmmc_info omap3pandora_mmc[] = { 277static struct omap2_hsmmc_info omap3pandora_mmc[] = {
277 { 278 {
278 .mmc = 1, 279 .mmc = 1,
279 .wires = 4, 280 .caps = MMC_CAP_4_BIT_DATA,
280 .gpio_cd = -EINVAL, 281 .gpio_cd = -EINVAL,
281 .gpio_wp = 126, 282 .gpio_wp = 126,
282 .ext_clock = 0, 283 .ext_clock = 0,
283 }, 284 },
284 { 285 {
285 .mmc = 2, 286 .mmc = 2,
286 .wires = 4, 287 .caps = MMC_CAP_4_BIT_DATA,
287 .gpio_cd = -EINVAL, 288 .gpio_cd = -EINVAL,
288 .gpio_wp = 127, 289 .gpio_wp = 127,
289 .ext_clock = 1, 290 .ext_clock = 1,
@@ -291,7 +292,7 @@ static struct omap2_hsmmc_info omap3pandora_mmc[] = {
291 }, 292 },
292 { 293 {
293 .mmc = 3, 294 .mmc = 3,
294 .wires = 4, 295 .caps = MMC_CAP_4_BIT_DATA,
295 .gpio_cd = -EINVAL, 296 .gpio_cd = -EINVAL,
296 .gpio_wp = -EINVAL, 297 .gpio_wp = -EINVAL,
297 .init_card = pandora_wl1251_init_card, 298 .init_card = pandora_wl1251_init_card,
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
index bcd01d278c65..c1b881d3d8ae 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -26,6 +26,7 @@
26 26
27#include <linux/regulator/machine.h> 27#include <linux/regulator/machine.h>
28#include <linux/i2c/twl.h> 28#include <linux/i2c/twl.h>
29#include <linux/mmc/host.h>
29 30
30#include <mach/hardware.h> 31#include <mach/hardware.h>
31#include <asm/mach-types.h> 32#include <asm/mach-types.h>
@@ -275,7 +276,7 @@ static struct regulator_init_data omap3stalker_vsim = {
275static struct omap2_hsmmc_info mmc[] = { 276static struct omap2_hsmmc_info mmc[] = {
276 { 277 {
277 .mmc = 1, 278 .mmc = 1,
278 .wires = 4, 279 .caps = MMC_CAP_4_BIT_DATA,
279 .gpio_cd = -EINVAL, 280 .gpio_cd = -EINVAL,
280 .gpio_wp = 23, 281 .gpio_wp = 23,
281 }, 282 },
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
index 663c62d271e8..9ab18fdd974c 100644
--- a/arch/arm/mach-omap2/board-omap3touchbook.c
+++ b/arch/arm/mach-omap2/board-omap3touchbook.c
@@ -27,6 +27,7 @@
27#include <linux/mtd/mtd.h> 27#include <linux/mtd/mtd.h>
28#include <linux/mtd/partitions.h> 28#include <linux/mtd/partitions.h>
29#include <linux/mtd/nand.h> 29#include <linux/mtd/nand.h>
30#include <linux/mmc/host.h>
30 31
31#include <plat/mcspi.h> 32#include <plat/mcspi.h>
32#include <linux/spi/spi.h> 33#include <linux/spi/spi.h>
@@ -108,7 +109,7 @@ static struct omap_nand_platform_data omap3touchbook_nand_data = {
108static struct omap2_hsmmc_info mmc[] = { 109static struct omap2_hsmmc_info mmc[] = {
109 { 110 {
110 .mmc = 1, 111 .mmc = 1,
111 .wires = 8, 112 .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
112 .gpio_wp = 29, 113 .gpio_wp = 29,
113 }, 114 },
114 {} /* Terminator */ 115 {} /* Terminator */
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index c03d1d56db56..aa8296e7e9d4 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -20,6 +20,7 @@
20#include <linux/init.h> 20#include <linux/init.h>
21#include <linux/platform_device.h> 21#include <linux/platform_device.h>
22#include <linux/io.h> 22#include <linux/io.h>
23#include <linux/leds.h>
23#include <linux/gpio.h> 24#include <linux/gpio.h>
24#include <linux/usb/otg.h> 25#include <linux/usb/otg.h>
25#include <linux/i2c/twl.h> 26#include <linux/i2c/twl.h>
@@ -40,6 +41,36 @@
40#include "hsmmc.h" 41#include "hsmmc.h"
41 42
42 43
44static struct gpio_led gpio_leds[] = {
45 {
46 .name = "pandaboard::status1",
47 .default_trigger = "heartbeat",
48 .gpio = 7,
49 },
50 {
51 .name = "pandaboard::status2",
52 .default_trigger = "mmc0",
53 .gpio = 8,
54 },
55};
56
57static struct gpio_led_platform_data gpio_led_info = {
58 .leds = gpio_leds,
59 .num_leds = ARRAY_SIZE(gpio_leds),
60};
61
62static struct platform_device leds_gpio = {
63 .name = "leds-gpio",
64 .id = -1,
65 .dev = {
66 .platform_data = &gpio_led_info,
67 },
68};
69
70static struct platform_device *panda_devices[] __initdata = {
71 &leds_gpio,
72};
73
43static void __init omap4_panda_init_irq(void) 74static void __init omap4_panda_init_irq(void)
44{ 75{
45 omap2_init_common_hw(NULL, NULL); 76 omap2_init_common_hw(NULL, NULL);
@@ -56,7 +87,7 @@ static struct omap_musb_board_data musb_board_data = {
56static struct omap2_hsmmc_info mmc[] = { 87static struct omap2_hsmmc_info mmc[] = {
57 { 88 {
58 .mmc = 1, 89 .mmc = 1,
59 .wires = 8, 90 .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
60 .gpio_wp = -EINVAL, 91 .gpio_wp = -EINVAL,
61 }, 92 },
62 {} /* Terminator */ 93 {} /* Terminator */
@@ -274,9 +305,8 @@ static int __init omap4_panda_i2c_init(void)
274} 305}
275static void __init omap4_panda_init(void) 306static void __init omap4_panda_init(void)
276{ 307{
277 int status;
278
279 omap4_panda_i2c_init(); 308 omap4_panda_i2c_init();
309 platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices));
280 omap_serial_init(); 310 omap_serial_init();
281 omap4_twl6030_hsmmc_init(mmc); 311 omap4_twl6030_hsmmc_init(mmc);
282 /* OMAP4 Panda uses internal transceiver so register nop transceiver */ 312 /* OMAP4 Panda uses internal transceiver so register nop transceiver */
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index 4c4843618350..93441e5b36ef 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -32,6 +32,7 @@
32#include <linux/mtd/mtd.h> 32#include <linux/mtd/mtd.h>
33#include <linux/mtd/nand.h> 33#include <linux/mtd/nand.h>
34#include <linux/mtd/partitions.h> 34#include <linux/mtd/partitions.h>
35#include <linux/mmc/host.h>
35 36
36#include <asm/mach-types.h> 37#include <asm/mach-types.h>
37#include <asm/mach/arch.h> 38#include <asm/mach/arch.h>
@@ -303,13 +304,13 @@ static void __init overo_flash_init(void)
303static struct omap2_hsmmc_info mmc[] = { 304static struct omap2_hsmmc_info mmc[] = {
304 { 305 {
305 .mmc = 1, 306 .mmc = 1,
306 .wires = 4, 307 .caps = MMC_CAP_4_BIT_DATA,
307 .gpio_cd = -EINVAL, 308 .gpio_cd = -EINVAL,
308 .gpio_wp = -EINVAL, 309 .gpio_wp = -EINVAL,
309 }, 310 },
310 { 311 {
311 .mmc = 2, 312 .mmc = 2,
312 .wires = 4, 313 .caps = MMC_CAP_4_BIT_DATA,
313 .gpio_cd = -EINVAL, 314 .gpio_cd = -EINVAL,
314 .gpio_wp = -EINVAL, 315 .gpio_wp = -EINVAL,
315 .transceiver = true, 316 .transceiver = true,
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index 9a5eb87425fc..a3dbaa7b8632 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -302,7 +302,7 @@ static struct omap2_hsmmc_info mmc[] __initdata = {
302 { 302 {
303 .name = "external", 303 .name = "external",
304 .mmc = 1, 304 .mmc = 1,
305 .wires = 4, 305 .caps = MMC_CAP_4_BIT_DATA,
306 .cover_only = true, 306 .cover_only = true,
307 .gpio_cd = 160, 307 .gpio_cd = 160,
308 .gpio_wp = -EINVAL, 308 .gpio_wp = -EINVAL,
@@ -311,7 +311,8 @@ static struct omap2_hsmmc_info mmc[] __initdata = {
311 { 311 {
312 .name = "internal", 312 .name = "internal",
313 .mmc = 2, 313 .mmc = 2,
314 .wires = 8, /* See also rx51_mmc2_remux */ 314 .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
315 /* See also rx51_mmc2_remux */
315 .gpio_cd = -EINVAL, 316 .gpio_cd = -EINVAL,
316 .gpio_wp = -EINVAL, 317 .gpio_wp = -EINVAL,
317 .nonremovable = true, 318 .nonremovable = true,
diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c
index 6b3984964cc5..e5eac46bbac9 100644
--- a/arch/arm/mach-omap2/board-zoom-peripherals.c
+++ b/arch/arm/mach-omap2/board-zoom-peripherals.c
@@ -16,6 +16,7 @@
16#include <linux/gpio.h> 16#include <linux/gpio.h>
17#include <linux/i2c/twl.h> 17#include <linux/i2c/twl.h>
18#include <linux/regulator/machine.h> 18#include <linux/regulator/machine.h>
19#include <linux/mmc/host.h>
19 20
20#include <asm/mach-types.h> 21#include <asm/mach-types.h>
21#include <asm/mach/arch.h> 22#include <asm/mach/arch.h>
@@ -155,14 +156,14 @@ static struct omap2_hsmmc_info mmc[] __initdata = {
155 { 156 {
156 .name = "external", 157 .name = "external",
157 .mmc = 1, 158 .mmc = 1,
158 .wires = 4, 159 .caps = MMC_CAP_4_BIT_DATA,
159 .gpio_wp = -EINVAL, 160 .gpio_wp = -EINVAL,
160 .power_saving = true, 161 .power_saving = true,
161 }, 162 },
162 { 163 {
163 .name = "internal", 164 .name = "internal",
164 .mmc = 2, 165 .mmc = 2,
165 .wires = 8, 166 .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
166 .gpio_cd = -EINVAL, 167 .gpio_cd = -EINVAL,
167 .gpio_wp = -EINVAL, 168 .gpio_wp = -EINVAL,
168 .nonremovable = true, 169 .nonremovable = true,
diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
index 37d65d62ed8f..5f2066a6ba74 100644
--- a/arch/arm/mach-omap2/clock2420_data.c
+++ b/arch/arm/mach-omap2/clock2420_data.c
@@ -1838,7 +1838,7 @@ static struct omap_clk omap2420_clks[] = {
1838 CLK(NULL, "des_ick", &des_ick, CK_242X), 1838 CLK(NULL, "des_ick", &des_ick, CK_242X),
1839 CLK("omap-sham", "ick", &sha_ick, CK_242X), 1839 CLK("omap-sham", "ick", &sha_ick, CK_242X),
1840 CLK("omap_rng", "ick", &rng_ick, CK_242X), 1840 CLK("omap_rng", "ick", &rng_ick, CK_242X),
1841 CLK(NULL, "aes_ick", &aes_ick, CK_242X), 1841 CLK("omap-aes", "ick", &aes_ick, CK_242X),
1842 CLK(NULL, "pka_ick", &pka_ick, CK_242X), 1842 CLK(NULL, "pka_ick", &pka_ick, CK_242X),
1843 CLK(NULL, "usb_fck", &usb_fck, CK_242X), 1843 CLK(NULL, "usb_fck", &usb_fck, CK_242X),
1844 CLK("musb_hdrc", "fck", &osc_ck, CK_242X), 1844 CLK("musb_hdrc", "fck", &osc_ck, CK_242X),
diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
index b33118fb6a87..701a1716019e 100644
--- a/arch/arm/mach-omap2/clock2430_data.c
+++ b/arch/arm/mach-omap2/clock2430_data.c
@@ -1926,7 +1926,7 @@ static struct omap_clk omap2430_clks[] = {
1926 CLK(NULL, "des_ick", &des_ick, CK_243X), 1926 CLK(NULL, "des_ick", &des_ick, CK_243X),
1927 CLK("omap-sham", "ick", &sha_ick, CK_243X), 1927 CLK("omap-sham", "ick", &sha_ick, CK_243X),
1928 CLK("omap_rng", "ick", &rng_ick, CK_243X), 1928 CLK("omap_rng", "ick", &rng_ick, CK_243X),
1929 CLK(NULL, "aes_ick", &aes_ick, CK_243X), 1929 CLK("omap-aes", "ick", &aes_ick, CK_243X),
1930 CLK(NULL, "pka_ick", &pka_ick, CK_243X), 1930 CLK(NULL, "pka_ick", &pka_ick, CK_243X),
1931 CLK(NULL, "usb_fck", &usb_fck, CK_243X), 1931 CLK(NULL, "usb_fck", &usb_fck, CK_243X),
1932 CLK("musb_hdrc", "ick", &usbhs_ick, CK_243X), 1932 CLK("musb_hdrc", "ick", &usbhs_ick, CK_243X),
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index dfdce2d82779..c73906d17458 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -3288,7 +3288,7 @@ static struct omap_clk omap3xxx_clks[] = {
3288 CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2 | CK_AM35XX), 3288 CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2 | CK_AM35XX),
3289 CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2 | CK_AM35XX), 3289 CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2 | CK_AM35XX),
3290 CLK(NULL, "icr_ick", &icr_ick, CK_343X), 3290 CLK(NULL, "icr_ick", &icr_ick, CK_343X),
3291 CLK(NULL, "aes2_ick", &aes2_ick, CK_343X), 3291 CLK("omap-aes", "ick", &aes2_ick, CK_343X),
3292 CLK("omap-sham", "ick", &sha12_ick, CK_343X), 3292 CLK("omap-sham", "ick", &sha12_ick, CK_343X),
3293 CLK(NULL, "des2_ick", &des2_ick, CK_343X), 3293 CLK(NULL, "des2_ick", &des2_ick, CK_343X),
3294 CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_3XXX), 3294 CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_3XXX),
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index 5d80cb897489..6fb61b1a0d46 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -258,97 +258,6 @@ static void _omap2_clkdm_set_hwsup(struct clockdomain *clkdm, int enable)
258 258
259} 259}
260 260
261/**
262 * _init_wkdep_usecount - initialize wkdep usecounts to match hardware
263 * @clkdm: clockdomain to initialize wkdep usecounts
264 *
265 * Initialize the wakeup dependency usecount variables for clockdomain @clkdm.
266 * If a wakeup dependency is present in the hardware, the usecount will be
267 * set to 1; otherwise, it will be set to 0. Software should clear all
268 * software wakeup dependencies prior to calling this function if it wishes
269 * to ensure that all usecounts start at 0. No return value.
270 */
271static void _init_wkdep_usecount(struct clockdomain *clkdm)
272{
273 u32 v;
274 struct clkdm_dep *cd;
275
276 if (!clkdm->wkdep_srcs)
277 return;
278
279 for (cd = clkdm->wkdep_srcs; cd->clkdm_name; cd++) {
280 if (!omap_chip_is(cd->omap_chip))
281 continue;
282
283 if (!cd->clkdm && cd->clkdm_name)
284 cd->clkdm = _clkdm_lookup(cd->clkdm_name);
285
286 if (!cd->clkdm) {
287 WARN(!cd->clkdm, "clockdomain: %s: wkdep clkdm %s not "
288 "found\n", clkdm->name, cd->clkdm_name);
289 continue;
290 }
291
292 v = prm_read_mod_bits_shift(clkdm->pwrdm.ptr->prcm_offs,
293 PM_WKDEP,
294 (1 << cd->clkdm->dep_bit));
295
296 if (v)
297 pr_debug("clockdomain: %s: wakeup dependency already "
298 "set to wake up when %s wakes\n",
299 clkdm->name, cd->clkdm->name);
300
301 atomic_set(&cd->wkdep_usecount, (v) ? 1 : 0);
302 }
303}
304
305/**
306 * _init_sleepdep_usecount - initialize sleepdep usecounts to match hardware
307 * @clkdm: clockdomain to initialize sleepdep usecounts
308 *
309 * Initialize the sleep dependency usecount variables for clockdomain @clkdm.
310 * If a sleep dependency is present in the hardware, the usecount will be
311 * set to 1; otherwise, it will be set to 0. Software should clear all
312 * software sleep dependencies prior to calling this function if it wishes
313 * to ensure that all usecounts start at 0. No return value.
314 */
315static void _init_sleepdep_usecount(struct clockdomain *clkdm)
316{
317 u32 v;
318 struct clkdm_dep *cd;
319
320 if (!cpu_is_omap34xx())
321 return;
322
323 if (!clkdm->sleepdep_srcs)
324 return;
325
326 for (cd = clkdm->sleepdep_srcs; cd->clkdm_name; cd++) {
327 if (!omap_chip_is(cd->omap_chip))
328 continue;
329
330 if (!cd->clkdm && cd->clkdm_name)
331 cd->clkdm = _clkdm_lookup(cd->clkdm_name);
332
333 if (!cd->clkdm) {
334 WARN(!cd->clkdm, "clockdomain: %s: sleepdep clkdm %s "
335 "not found\n", clkdm->name, cd->clkdm_name);
336 continue;
337 }
338
339 v = prm_read_mod_bits_shift(clkdm->pwrdm.ptr->prcm_offs,
340 OMAP3430_CM_SLEEPDEP,
341 (1 << cd->clkdm->dep_bit));
342
343 if (v)
344 pr_debug("clockdomain: %s: sleep dependency already "
345 "set to prevent from idling until %s "
346 "idles\n", clkdm->name, cd->clkdm->name);
347
348 atomic_set(&cd->sleepdep_usecount, (v) ? 1 : 0);
349 }
350};
351
352/* Public functions */ 261/* Public functions */
353 262
354/** 263/**
@@ -379,12 +288,17 @@ void clkdm_init(struct clockdomain **clkdms,
379 _autodep_lookup(autodep); 288 _autodep_lookup(autodep);
380 289
381 /* 290 /*
382 * Ensure that the *dep_usecount registers reflect the current 291 * Put all clockdomains into software-supervised mode; PM code
383 * state of the PRCM. 292 * should later enable hardware-supervised mode as appropriate
384 */ 293 */
385 list_for_each_entry(clkdm, &clkdm_list, node) { 294 list_for_each_entry(clkdm, &clkdm_list, node) {
386 _init_wkdep_usecount(clkdm); 295 if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
387 _init_sleepdep_usecount(clkdm); 296 omap2_clkdm_wakeup(clkdm);
297 else if (clkdm->flags & CLKDM_CAN_DISABLE_AUTO)
298 omap2_clkdm_deny_idle(clkdm);
299
300 clkdm_clear_all_wkdeps(clkdm);
301 clkdm_clear_all_sleepdeps(clkdm);
388 } 302 }
389} 303}
390 304
@@ -592,6 +506,9 @@ int clkdm_clear_all_wkdeps(struct clockdomain *clkdm)
592 if (!omap_chip_is(cd->omap_chip)) 506 if (!omap_chip_is(cd->omap_chip))
593 continue; 507 continue;
594 508
509 if (!cd->clkdm && cd->clkdm_name)
510 cd->clkdm = _clkdm_lookup(cd->clkdm_name);
511
595 /* PRM accesses are slow, so minimize them */ 512 /* PRM accesses are slow, so minimize them */
596 mask |= 1 << cd->clkdm->dep_bit; 513 mask |= 1 << cd->clkdm->dep_bit;
597 atomic_set(&cd->wkdep_usecount, 0); 514 atomic_set(&cd->wkdep_usecount, 0);
@@ -752,6 +669,9 @@ int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
752 if (!omap_chip_is(cd->omap_chip)) 669 if (!omap_chip_is(cd->omap_chip))
753 continue; 670 continue;
754 671
672 if (!cd->clkdm && cd->clkdm_name)
673 cd->clkdm = _clkdm_lookup(cd->clkdm_name);
674
755 /* PRM accesses are slow, so minimize them */ 675 /* PRM accesses are slow, so minimize them */
756 mask |= 1 << cd->clkdm->dep_bit; 676 mask |= 1 << cd->clkdm->dep_bit;
757 atomic_set(&cd->sleepdep_usecount, 0); 677 atomic_set(&cd->sleepdep_usecount, 0);
diff --git a/arch/arm/mach-omap2/cm4xxx.c b/arch/arm/mach-omap2/cm4xxx.c
index b101091e95d6..f8a660a1a4a6 100644
--- a/arch/arm/mach-omap2/cm4xxx.c
+++ b/arch/arm/mach-omap2/cm4xxx.c
@@ -43,7 +43,6 @@
43 * using separate functional clock 43 * using separate functional clock
44 * 0x3 disabled: Module is disabled and cannot be accessed 44 * 0x3 disabled: Module is disabled and cannot be accessed
45 * 45 *
46 * TODO: Need to handle module accessible in idle state
47 */ 46 */
48int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg) 47int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg)
49{ 48{
@@ -52,9 +51,11 @@ int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg)
52 if (!clkctrl_reg) 51 if (!clkctrl_reg)
53 return 0; 52 return 0;
54 53
55 omap_test_timeout(((__raw_readl(clkctrl_reg) & 54 omap_test_timeout((
56 OMAP4430_IDLEST_MASK) == 0), 55 ((__raw_readl(clkctrl_reg) & OMAP4430_IDLEST_MASK) == 0) ||
57 MAX_MODULE_READY_TIME, i); 56 (((__raw_readl(clkctrl_reg) & OMAP4430_IDLEST_MASK) >>
57 OMAP4430_IDLEST_SHIFT) == 0x2)),
58 MAX_MODULE_READY_TIME, i);
58 59
59 return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; 60 return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
60} 61}
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index 3d3d035db9af..8ea012ef0b5a 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -60,7 +60,8 @@ struct omap3_processor_cx {
60 60
61struct omap3_processor_cx omap3_power_states[OMAP3_MAX_STATES]; 61struct omap3_processor_cx omap3_power_states[OMAP3_MAX_STATES];
62struct omap3_processor_cx current_cx_state; 62struct omap3_processor_cx current_cx_state;
63struct powerdomain *mpu_pd, *core_pd; 63struct powerdomain *mpu_pd, *core_pd, *per_pd;
64struct powerdomain *cam_pd;
64 65
65/* 66/*
66 * The latencies/thresholds for various C states have 67 * The latencies/thresholds for various C states have
@@ -233,14 +234,62 @@ static int omap3_enter_idle_bm(struct cpuidle_device *dev,
233 struct cpuidle_state *state) 234 struct cpuidle_state *state)
234{ 235{
235 struct cpuidle_state *new_state = next_valid_state(dev, state); 236 struct cpuidle_state *new_state = next_valid_state(dev, state);
237 u32 core_next_state, per_next_state = 0, per_saved_state = 0;
238 u32 cam_state;
239 struct omap3_processor_cx *cx;
240 int ret;
236 241
237 if ((state->flags & CPUIDLE_FLAG_CHECK_BM) && omap3_idle_bm_check()) { 242 if ((state->flags & CPUIDLE_FLAG_CHECK_BM) && omap3_idle_bm_check()) {
238 BUG_ON(!dev->safe_state); 243 BUG_ON(!dev->safe_state);
239 new_state = dev->safe_state; 244 new_state = dev->safe_state;
245 goto select_state;
246 }
247
248 cx = cpuidle_get_statedata(state);
249 core_next_state = cx->core_state;
250
251 /*
252 * FIXME: we currently manage device-specific idle states
253 * for PER and CORE in combination with CPU-specific
254 * idle states. This is wrong, and device-specific
255 * idle managment needs to be separated out into
256 * its own code.
257 */
258
259 /*
260 * Prevent idle completely if CAM is active.
261 * CAM does not have wakeup capability in OMAP3.
262 */
263 cam_state = pwrdm_read_pwrst(cam_pd);
264 if (cam_state == PWRDM_POWER_ON) {
265 new_state = dev->safe_state;
266 goto select_state;
267 }
268
269 /*
270 * Prevent PER off if CORE is not in retention or off as this
271 * would disable PER wakeups completely.
272 */
273 per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd);
274 if ((per_next_state == PWRDM_POWER_OFF) &&
275 (core_next_state > PWRDM_POWER_RET)) {
276 per_next_state = PWRDM_POWER_RET;
277 pwrdm_set_next_pwrst(per_pd, per_next_state);
240 } 278 }
241 279
280 /* Are we changing PER target state? */
281 if (per_next_state != per_saved_state)
282 pwrdm_set_next_pwrst(per_pd, per_next_state);
283
284select_state:
242 dev->last_state = new_state; 285 dev->last_state = new_state;
243 return omap3_enter_idle(dev, new_state); 286 ret = omap3_enter_idle(dev, new_state);
287
288 /* Restore original PER state if it was modified */
289 if (per_next_state != per_saved_state)
290 pwrdm_set_next_pwrst(per_pd, per_saved_state);
291
292 return ret;
244} 293}
245 294
246DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev); 295DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
@@ -328,7 +377,8 @@ void omap_init_power_states(void)
328 cpuidle_params_table[OMAP3_STATE_C2].threshold; 377 cpuidle_params_table[OMAP3_STATE_C2].threshold;
329 omap3_power_states[OMAP3_STATE_C2].mpu_state = PWRDM_POWER_ON; 378 omap3_power_states[OMAP3_STATE_C2].mpu_state = PWRDM_POWER_ON;
330 omap3_power_states[OMAP3_STATE_C2].core_state = PWRDM_POWER_ON; 379 omap3_power_states[OMAP3_STATE_C2].core_state = PWRDM_POWER_ON;
331 omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID; 380 omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID |
381 CPUIDLE_FLAG_CHECK_BM;
332 382
333 /* C3 . MPU CSWR + Core inactive */ 383 /* C3 . MPU CSWR + Core inactive */
334 omap3_power_states[OMAP3_STATE_C3].valid = 384 omap3_power_states[OMAP3_STATE_C3].valid =
@@ -426,6 +476,8 @@ int __init omap3_idle_init(void)
426 476
427 mpu_pd = pwrdm_lookup("mpu_pwrdm"); 477 mpu_pd = pwrdm_lookup("mpu_pwrdm");
428 core_pd = pwrdm_lookup("core_pwrdm"); 478 core_pd = pwrdm_lookup("core_pwrdm");
479 per_pd = pwrdm_lookup("per_pwrdm");
480 cam_pd = pwrdm_lookup("cam_pwrdm");
429 481
430 omap_init_power_states(); 482 omap_init_power_states();
431 cpuidle_register_driver(&omap3_idle_driver); 483 cpuidle_register_driver(&omap3_idle_driver);
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 2dbb265bedd4..9e5d51bee94a 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -498,6 +498,76 @@ static void omap_init_sham(void)
498static inline void omap_init_sham(void) { } 498static inline void omap_init_sham(void) { }
499#endif 499#endif
500 500
501#if defined(CONFIG_CRYPTO_DEV_OMAP_AES) || defined(CONFIG_CRYPTO_DEV_OMAP_AES_MODULE)
502
503#ifdef CONFIG_ARCH_OMAP2
504static struct resource omap2_aes_resources[] = {
505 {
506 .start = OMAP24XX_SEC_AES_BASE,
507 .end = OMAP24XX_SEC_AES_BASE + 0x4C,
508 .flags = IORESOURCE_MEM,
509 },
510 {
511 .start = OMAP24XX_DMA_AES_TX,
512 .flags = IORESOURCE_DMA,
513 },
514 {
515 .start = OMAP24XX_DMA_AES_RX,
516 .flags = IORESOURCE_DMA,
517 }
518};
519static int omap2_aes_resources_sz = ARRAY_SIZE(omap2_aes_resources);
520#else
521#define omap2_aes_resources NULL
522#define omap2_aes_resources_sz 0
523#endif
524
525#ifdef CONFIG_ARCH_OMAP3
526static struct resource omap3_aes_resources[] = {
527 {
528 .start = OMAP34XX_SEC_AES_BASE,
529 .end = OMAP34XX_SEC_AES_BASE + 0x4C,
530 .flags = IORESOURCE_MEM,
531 },
532 {
533 .start = OMAP34XX_DMA_AES2_TX,
534 .flags = IORESOURCE_DMA,
535 },
536 {
537 .start = OMAP34XX_DMA_AES2_RX,
538 .flags = IORESOURCE_DMA,
539 }
540};
541static int omap3_aes_resources_sz = ARRAY_SIZE(omap3_aes_resources);
542#else
543#define omap3_aes_resources NULL
544#define omap3_aes_resources_sz 0
545#endif
546
547static struct platform_device aes_device = {
548 .name = "omap-aes",
549 .id = -1,
550};
551
552static void omap_init_aes(void)
553{
554 if (cpu_is_omap24xx()) {
555 aes_device.resource = omap2_aes_resources;
556 aes_device.num_resources = omap2_aes_resources_sz;
557 } else if (cpu_is_omap34xx()) {
558 aes_device.resource = omap3_aes_resources;
559 aes_device.num_resources = omap3_aes_resources_sz;
560 } else {
561 pr_err("%s: platform not supported\n", __func__);
562 return;
563 }
564 platform_device_register(&aes_device);
565}
566
567#else
568static inline void omap_init_aes(void) { }
569#endif
570
501/*-------------------------------------------------------------------------*/ 571/*-------------------------------------------------------------------------*/
502 572
503#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) 573#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
@@ -624,7 +694,7 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
624 omap_mux_init_signal("sdmmc_dat0", 0); 694 omap_mux_init_signal("sdmmc_dat0", 0);
625 omap_mux_init_signal("sdmmc_dat_dir0", 0); 695 omap_mux_init_signal("sdmmc_dat_dir0", 0);
626 omap_mux_init_signal("sdmmc_cmd_dir", 0); 696 omap_mux_init_signal("sdmmc_cmd_dir", 0);
627 if (mmc_controller->slots[0].wires == 4) { 697 if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) {
628 omap_mux_init_signal("sdmmc_dat1", 0); 698 omap_mux_init_signal("sdmmc_dat1", 0);
629 omap_mux_init_signal("sdmmc_dat2", 0); 699 omap_mux_init_signal("sdmmc_dat2", 0);
630 omap_mux_init_signal("sdmmc_dat3", 0); 700 omap_mux_init_signal("sdmmc_dat3", 0);
@@ -652,8 +722,8 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
652 OMAP_PIN_INPUT_PULLUP); 722 OMAP_PIN_INPUT_PULLUP);
653 omap_mux_init_signal("sdmmc1_dat0", 723 omap_mux_init_signal("sdmmc1_dat0",
654 OMAP_PIN_INPUT_PULLUP); 724 OMAP_PIN_INPUT_PULLUP);
655 if (mmc_controller->slots[0].wires == 4 || 725 if (mmc_controller->slots[0].caps &
656 mmc_controller->slots[0].wires == 8) { 726 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
657 omap_mux_init_signal("sdmmc1_dat1", 727 omap_mux_init_signal("sdmmc1_dat1",
658 OMAP_PIN_INPUT_PULLUP); 728 OMAP_PIN_INPUT_PULLUP);
659 omap_mux_init_signal("sdmmc1_dat2", 729 omap_mux_init_signal("sdmmc1_dat2",
@@ -661,7 +731,8 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
661 omap_mux_init_signal("sdmmc1_dat3", 731 omap_mux_init_signal("sdmmc1_dat3",
662 OMAP_PIN_INPUT_PULLUP); 732 OMAP_PIN_INPUT_PULLUP);
663 } 733 }
664 if (mmc_controller->slots[0].wires == 8) { 734 if (mmc_controller->slots[0].caps &
735 MMC_CAP_8_BIT_DATA) {
665 omap_mux_init_signal("sdmmc1_dat4", 736 omap_mux_init_signal("sdmmc1_dat4",
666 OMAP_PIN_INPUT_PULLUP); 737 OMAP_PIN_INPUT_PULLUP);
667 omap_mux_init_signal("sdmmc1_dat5", 738 omap_mux_init_signal("sdmmc1_dat5",
@@ -685,8 +756,8 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
685 * For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed 756 * For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed
686 * in the board-*.c files 757 * in the board-*.c files
687 */ 758 */
688 if (mmc_controller->slots[0].wires == 4 || 759 if (mmc_controller->slots[0].caps &
689 mmc_controller->slots[0].wires == 8) { 760 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
690 omap_mux_init_signal("sdmmc2_dat1", 761 omap_mux_init_signal("sdmmc2_dat1",
691 OMAP_PIN_INPUT_PULLUP); 762 OMAP_PIN_INPUT_PULLUP);
692 omap_mux_init_signal("sdmmc2_dat2", 763 omap_mux_init_signal("sdmmc2_dat2",
@@ -694,7 +765,8 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
694 omap_mux_init_signal("sdmmc2_dat3", 765 omap_mux_init_signal("sdmmc2_dat3",
695 OMAP_PIN_INPUT_PULLUP); 766 OMAP_PIN_INPUT_PULLUP);
696 } 767 }
697 if (mmc_controller->slots[0].wires == 8) { 768 if (mmc_controller->slots[0].caps &
769 MMC_CAP_8_BIT_DATA) {
698 omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4", 770 omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
699 OMAP_PIN_INPUT_PULLUP); 771 OMAP_PIN_INPUT_PULLUP);
700 omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5", 772 omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
@@ -854,6 +926,7 @@ static int __init omap2_init_devices(void)
854 omap_hdq_init(); 926 omap_hdq_init();
855 omap_init_sti(); 927 omap_init_sti();
856 omap_init_sham(); 928 omap_init_sham();
929 omap_init_aes();
857 omap_init_vout(); 930 omap_init_vout();
858 931
859 return 0; 932 return 0;
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index 87bdb7bfd1bf..eb92b8107d2c 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -263,7 +263,7 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
263 "mmc%islot%i", c->mmc, 1); 263 "mmc%islot%i", c->mmc, 1);
264 mmc->slots[0].name = hc->name; 264 mmc->slots[0].name = hc->name;
265 mmc->nr_slots = 1; 265 mmc->nr_slots = 1;
266 mmc->slots[0].wires = c->wires; 266 mmc->slots[0].caps = c->caps;
267 mmc->slots[0].internal_clock = !c->ext_clock; 267 mmc->slots[0].internal_clock = !c->ext_clock;
268 mmc->dma_mask = 0xffffffff; 268 mmc->dma_mask = 0xffffffff;
269 269
@@ -321,16 +321,20 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
321 } 321 }
322 322
323 /* Omap3630 HSMMC1 supports only 4-bit */ 323 /* Omap3630 HSMMC1 supports only 4-bit */
324 if (cpu_is_omap3630() && c->wires > 4) { 324 if (cpu_is_omap3630() &&
325 c->wires = 4; 325 (c->caps & MMC_CAP_8_BIT_DATA)) {
326 mmc->slots[0].wires = c->wires; 326 c->caps &= ~MMC_CAP_8_BIT_DATA;
327 c->caps |= MMC_CAP_4_BIT_DATA;
328 mmc->slots[0].caps = c->caps;
327 } 329 }
328 break; 330 break;
329 case 2: 331 case 2:
330 if (c->ext_clock) 332 if (c->ext_clock)
331 c->transceiver = 1; 333 c->transceiver = 1;
332 if (c->transceiver && c->wires > 4) 334 if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) {
333 c->wires = 4; 335 c->caps &= ~MMC_CAP_8_BIT_DATA;
336 c->caps |= MMC_CAP_4_BIT_DATA;
337 }
334 /* FALLTHROUGH */ 338 /* FALLTHROUGH */
335 case 3: 339 case 3:
336 if (mmc->slots[0].features & HSMMC_HAS_PBIAS) { 340 if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
diff --git a/arch/arm/mach-omap2/hsmmc.h b/arch/arm/mach-omap2/hsmmc.h
index 1fe6f0187177..281e97287adf 100644
--- a/arch/arm/mach-omap2/hsmmc.h
+++ b/arch/arm/mach-omap2/hsmmc.h
@@ -10,7 +10,8 @@ struct mmc_card;
10 10
11struct omap2_hsmmc_info { 11struct omap2_hsmmc_info {
12 u8 mmc; /* controller 1/2/3 */ 12 u8 mmc; /* controller 1/2/3 */
13 u8 wires; /* 1/4/8 wires */ 13 u32 caps; /* 4/8 wires and any additional host
14 * capabilities OR'd (ref. linux/mmc/host.h) */
14 bool transceiver; /* MMC-2 option */ 15 bool transceiver; /* MMC-2 option */
15 bool ext_clock; /* use external pin for input clock */ 16 bool ext_clock; /* use external pin for input clock */
16 bool cover_only; /* No card detect - just cover switch */ 17 bool cover_only; /* No card detect - just cover switch */
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 4808bc968acc..0412233da2b3 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -298,7 +298,6 @@ static void __init omap4_check_revision(void)
298 u32 idcode; 298 u32 idcode;
299 u16 hawkeye; 299 u16 hawkeye;
300 u8 rev; 300 u8 rev;
301 char *rev_name = "ES1.0";
302 301
303 /* 302 /*
304 * The IC rev detection is done with hawkeye and rev. 303 * The IC rev detection is done with hawkeye and rev.
@@ -309,14 +308,39 @@ static void __init omap4_check_revision(void)
309 hawkeye = (idcode >> 12) & 0xffff; 308 hawkeye = (idcode >> 12) & 0xffff;
310 rev = (idcode >> 28) & 0xff; 309 rev = (idcode >> 28) & 0xff;
311 310
312 if ((hawkeye == 0xb852) && (rev == 0x0)) { 311 /*
313 omap_revision = OMAP4430_REV_ES1_0; 312 * Few initial ES2.0 samples IDCODE is same as ES1.0
314 omap_chip.oc |= CHIP_IS_OMAP4430ES1; 313 * Use ARM register to detect the correct ES version
315 pr_info("OMAP%04x %s\n", omap_rev() >> 16, rev_name); 314 */
316 return; 315 if (!rev) {
316 idcode = read_cpuid(CPUID_ID);
317 rev = (idcode & 0xf) - 1;
318 }
319
320 switch (hawkeye) {
321 case 0xb852:
322 switch (rev) {
323 case 0:
324 omap_revision = OMAP4430_REV_ES1_0;
325 omap_chip.oc |= CHIP_IS_OMAP4430ES1;
326 break;
327 case 1:
328 omap_revision = OMAP4430_REV_ES2_0;
329 omap_chip.oc |= CHIP_IS_OMAP4430ES2;
330 break;
331 default:
332 omap_revision = OMAP4430_REV_ES2_0;
333 omap_chip.oc |= CHIP_IS_OMAP4430ES2;
334 }
335 break;
336 default:
337 /* Unknown default to latest silicon rev as default*/
338 omap_revision = OMAP4430_REV_ES2_0;
339 omap_chip.oc |= CHIP_IS_OMAP4430ES2;
317 } 340 }
318 341
319 pr_err("Unknown OMAP4 CPU id\n"); 342 pr_info("OMAP%04x ES%d.0\n",
343 omap_rev() >> 16, ((omap_rev() >> 12) & 0xf) + 1);
320} 344}
321 345
322#define OMAP3_SHOW_FEATURE(feat) \ 346#define OMAP3_SHOW_FEATURE(feat) \
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index b9ea70bce563..490d87082fad 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -323,6 +323,9 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
323 omap2430_hwmod_init(); 323 omap2430_hwmod_init();
324 else if (cpu_is_omap34xx()) 324 else if (cpu_is_omap34xx())
325 omap3xxx_hwmod_init(); 325 omap3xxx_hwmod_init();
326 else if (cpu_is_omap44xx())
327 omap44xx_hwmod_init();
328
326 /* The OPP tables have to be registered before a clk init */ 329 /* The OPP tables have to be registered before a clk init */
327 omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps); 330 omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps);
328 331
@@ -342,9 +345,7 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
342#ifndef CONFIG_PM_RUNTIME 345#ifndef CONFIG_PM_RUNTIME
343 skip_setup_idle = 1; 346 skip_setup_idle = 1;
344#endif 347#endif
345 if (cpu_is_omap24xx() || cpu_is_omap34xx()) /* FIXME: OMAP4 */ 348 omap_hwmod_late_init(skip_setup_idle);
346 omap_hwmod_late_init(skip_setup_idle);
347
348 if (cpu_is_omap24xx() || cpu_is_omap34xx()) { 349 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
349 omap2_sdrc_init(sdrc_cs0, sdrc_cs1); 350 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
350 _omap2_init_reprogram_sdrc(); 351 _omap2_init_reprogram_sdrc();
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index 467aae245781..88b8790e4fec 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -23,29 +23,6 @@
23#include <plat/cpu.h> 23#include <plat/cpu.h>
24#include <plat/mcbsp.h> 24#include <plat/mcbsp.h>
25 25
26#include "mux.h"
27
28static void omap2_mcbsp2_mux_setup(void)
29{
30 omap_mux_init_signal("eac_ac_sclk.mcbsp2_clkx", OMAP_PULL_ENA);
31 omap_mux_init_signal("eac_ac_fs.mcbsp2_fsx", OMAP_PULL_ENA);
32 omap_mux_init_signal("eac_ac_din.mcbsp2_dr", OMAP_PULL_ENA);
33 omap_mux_init_signal("eac_ac_dout.mcbsp2_dx", OMAP_PULL_ENA);
34 omap_mux_init_gpio(117, OMAP_PULL_ENA);
35 /*
36 * TODO: Need to add MUX settings for OMAP 2430 SDP
37 */
38}
39
40static void omap2_mcbsp_request(unsigned int id)
41{
42 if (cpu_is_omap2420() && (id == OMAP_MCBSP2))
43 omap2_mcbsp2_mux_setup();
44}
45
46static struct omap_mcbsp_ops omap2_mcbsp_ops = {
47 .request = omap2_mcbsp_request,
48};
49 26
50#ifdef CONFIG_ARCH_OMAP2420 27#ifdef CONFIG_ARCH_OMAP2420
51static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = { 28static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = {
@@ -55,7 +32,6 @@ static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = {
55 .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX, 32 .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
56 .rx_irq = INT_24XX_MCBSP1_IRQ_RX, 33 .rx_irq = INT_24XX_MCBSP1_IRQ_RX,
57 .tx_irq = INT_24XX_MCBSP1_IRQ_TX, 34 .tx_irq = INT_24XX_MCBSP1_IRQ_TX,
58 .ops = &omap2_mcbsp_ops,
59 }, 35 },
60 { 36 {
61 .phys_base = OMAP24XX_MCBSP2_BASE, 37 .phys_base = OMAP24XX_MCBSP2_BASE,
@@ -63,7 +39,6 @@ static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = {
63 .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX, 39 .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
64 .rx_irq = INT_24XX_MCBSP2_IRQ_RX, 40 .rx_irq = INT_24XX_MCBSP2_IRQ_RX,
65 .tx_irq = INT_24XX_MCBSP2_IRQ_TX, 41 .tx_irq = INT_24XX_MCBSP2_IRQ_TX,
66 .ops = &omap2_mcbsp_ops,
67 }, 42 },
68}; 43};
69#define OMAP2420_MCBSP_PDATA_SZ ARRAY_SIZE(omap2420_mcbsp_pdata) 44#define OMAP2420_MCBSP_PDATA_SZ ARRAY_SIZE(omap2420_mcbsp_pdata)
@@ -82,7 +57,6 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = {
82 .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX, 57 .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
83 .rx_irq = INT_24XX_MCBSP1_IRQ_RX, 58 .rx_irq = INT_24XX_MCBSP1_IRQ_RX,
84 .tx_irq = INT_24XX_MCBSP1_IRQ_TX, 59 .tx_irq = INT_24XX_MCBSP1_IRQ_TX,
85 .ops = &omap2_mcbsp_ops,
86 }, 60 },
87 { 61 {
88 .phys_base = OMAP24XX_MCBSP2_BASE, 62 .phys_base = OMAP24XX_MCBSP2_BASE,
@@ -90,7 +64,6 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = {
90 .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX, 64 .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
91 .rx_irq = INT_24XX_MCBSP2_IRQ_RX, 65 .rx_irq = INT_24XX_MCBSP2_IRQ_RX,
92 .tx_irq = INT_24XX_MCBSP2_IRQ_TX, 66 .tx_irq = INT_24XX_MCBSP2_IRQ_TX,
93 .ops = &omap2_mcbsp_ops,
94 }, 67 },
95 { 68 {
96 .phys_base = OMAP2430_MCBSP3_BASE, 69 .phys_base = OMAP2430_MCBSP3_BASE,
@@ -98,7 +71,6 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = {
98 .dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX, 71 .dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX,
99 .rx_irq = INT_24XX_MCBSP3_IRQ_RX, 72 .rx_irq = INT_24XX_MCBSP3_IRQ_RX,
100 .tx_irq = INT_24XX_MCBSP3_IRQ_TX, 73 .tx_irq = INT_24XX_MCBSP3_IRQ_TX,
101 .ops = &omap2_mcbsp_ops,
102 }, 74 },
103 { 75 {
104 .phys_base = OMAP2430_MCBSP4_BASE, 76 .phys_base = OMAP2430_MCBSP4_BASE,
@@ -106,7 +78,6 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = {
106 .dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX, 78 .dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX,
107 .rx_irq = INT_24XX_MCBSP4_IRQ_RX, 79 .rx_irq = INT_24XX_MCBSP4_IRQ_RX,
108 .tx_irq = INT_24XX_MCBSP4_IRQ_TX, 80 .tx_irq = INT_24XX_MCBSP4_IRQ_TX,
109 .ops = &omap2_mcbsp_ops,
110 }, 81 },
111 { 82 {
112 .phys_base = OMAP2430_MCBSP5_BASE, 83 .phys_base = OMAP2430_MCBSP5_BASE,
@@ -114,7 +85,6 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = {
114 .dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX, 85 .dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX,
115 .rx_irq = INT_24XX_MCBSP5_IRQ_RX, 86 .rx_irq = INT_24XX_MCBSP5_IRQ_RX,
116 .tx_irq = INT_24XX_MCBSP5_IRQ_TX, 87 .tx_irq = INT_24XX_MCBSP5_IRQ_TX,
117 .ops = &omap2_mcbsp_ops,
118 }, 88 },
119}; 89};
120#define OMAP2430_MCBSP_PDATA_SZ ARRAY_SIZE(omap2430_mcbsp_pdata) 90#define OMAP2430_MCBSP_PDATA_SZ ARRAY_SIZE(omap2430_mcbsp_pdata)
@@ -133,7 +103,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
133 .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX, 103 .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
134 .rx_irq = INT_24XX_MCBSP1_IRQ_RX, 104 .rx_irq = INT_24XX_MCBSP1_IRQ_RX,
135 .tx_irq = INT_24XX_MCBSP1_IRQ_TX, 105 .tx_irq = INT_24XX_MCBSP1_IRQ_TX,
136 .ops = &omap2_mcbsp_ops,
137 .buffer_size = 0x80, /* The FIFO has 128 locations */ 106 .buffer_size = 0x80, /* The FIFO has 128 locations */
138 }, 107 },
139 { 108 {
@@ -143,7 +112,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
143 .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX, 112 .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
144 .rx_irq = INT_24XX_MCBSP2_IRQ_RX, 113 .rx_irq = INT_24XX_MCBSP2_IRQ_RX,
145 .tx_irq = INT_24XX_MCBSP2_IRQ_TX, 114 .tx_irq = INT_24XX_MCBSP2_IRQ_TX,
146 .ops = &omap2_mcbsp_ops,
147 .buffer_size = 0x500, /* The FIFO has 1024 + 256 locations */ 115 .buffer_size = 0x500, /* The FIFO has 1024 + 256 locations */
148 }, 116 },
149 { 117 {
@@ -153,7 +121,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
153 .dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX, 121 .dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX,
154 .rx_irq = INT_24XX_MCBSP3_IRQ_RX, 122 .rx_irq = INT_24XX_MCBSP3_IRQ_RX,
155 .tx_irq = INT_24XX_MCBSP3_IRQ_TX, 123 .tx_irq = INT_24XX_MCBSP3_IRQ_TX,
156 .ops = &omap2_mcbsp_ops,
157 .buffer_size = 0x80, /* The FIFO has 128 locations */ 124 .buffer_size = 0x80, /* The FIFO has 128 locations */
158 }, 125 },
159 { 126 {
@@ -162,7 +129,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
162 .dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX, 129 .dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX,
163 .rx_irq = INT_24XX_MCBSP4_IRQ_RX, 130 .rx_irq = INT_24XX_MCBSP4_IRQ_RX,
164 .tx_irq = INT_24XX_MCBSP4_IRQ_TX, 131 .tx_irq = INT_24XX_MCBSP4_IRQ_TX,
165 .ops = &omap2_mcbsp_ops,
166 .buffer_size = 0x80, /* The FIFO has 128 locations */ 132 .buffer_size = 0x80, /* The FIFO has 128 locations */
167 }, 133 },
168 { 134 {
@@ -171,7 +137,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
171 .dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX, 137 .dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX,
172 .rx_irq = INT_24XX_MCBSP5_IRQ_RX, 138 .rx_irq = INT_24XX_MCBSP5_IRQ_RX,
173 .tx_irq = INT_24XX_MCBSP5_IRQ_TX, 139 .tx_irq = INT_24XX_MCBSP5_IRQ_TX,
174 .ops = &omap2_mcbsp_ops,
175 .buffer_size = 0x80, /* The FIFO has 128 locations */ 140 .buffer_size = 0x80, /* The FIFO has 128 locations */
176 }, 141 },
177}; 142};
@@ -189,28 +154,24 @@ static struct omap_mcbsp_platform_data omap44xx_mcbsp_pdata[] = {
189 .dma_rx_sync = OMAP44XX_DMA_MCBSP1_RX, 154 .dma_rx_sync = OMAP44XX_DMA_MCBSP1_RX,
190 .dma_tx_sync = OMAP44XX_DMA_MCBSP1_TX, 155 .dma_tx_sync = OMAP44XX_DMA_MCBSP1_TX,
191 .tx_irq = OMAP44XX_IRQ_MCBSP1, 156 .tx_irq = OMAP44XX_IRQ_MCBSP1,
192 .ops = &omap2_mcbsp_ops,
193 }, 157 },
194 { 158 {
195 .phys_base = OMAP44XX_MCBSP2_BASE, 159 .phys_base = OMAP44XX_MCBSP2_BASE,
196 .dma_rx_sync = OMAP44XX_DMA_MCBSP2_RX, 160 .dma_rx_sync = OMAP44XX_DMA_MCBSP2_RX,
197 .dma_tx_sync = OMAP44XX_DMA_MCBSP2_TX, 161 .dma_tx_sync = OMAP44XX_DMA_MCBSP2_TX,
198 .tx_irq = OMAP44XX_IRQ_MCBSP2, 162 .tx_irq = OMAP44XX_IRQ_MCBSP2,
199 .ops = &omap2_mcbsp_ops,
200 }, 163 },
201 { 164 {
202 .phys_base = OMAP44XX_MCBSP3_BASE, 165 .phys_base = OMAP44XX_MCBSP3_BASE,
203 .dma_rx_sync = OMAP44XX_DMA_MCBSP3_RX, 166 .dma_rx_sync = OMAP44XX_DMA_MCBSP3_RX,
204 .dma_tx_sync = OMAP44XX_DMA_MCBSP3_TX, 167 .dma_tx_sync = OMAP44XX_DMA_MCBSP3_TX,
205 .tx_irq = OMAP44XX_IRQ_MCBSP3, 168 .tx_irq = OMAP44XX_IRQ_MCBSP3,
206 .ops = &omap2_mcbsp_ops,
207 }, 169 },
208 { 170 {
209 .phys_base = OMAP44XX_MCBSP4_BASE, 171 .phys_base = OMAP44XX_MCBSP4_BASE,
210 .dma_rx_sync = OMAP44XX_DMA_MCBSP4_RX, 172 .dma_rx_sync = OMAP44XX_DMA_MCBSP4_RX,
211 .dma_tx_sync = OMAP44XX_DMA_MCBSP4_TX, 173 .dma_tx_sync = OMAP44XX_DMA_MCBSP4_TX,
212 .tx_irq = OMAP44XX_IRQ_MCBSP4, 174 .tx_irq = OMAP44XX_IRQ_MCBSP4,
213 .ops = &omap2_mcbsp_ops,
214 }, 175 },
215}; 176};
216#define OMAP44XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap44xx_mcbsp_pdata) 177#define OMAP44XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap44xx_mcbsp_pdata)
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index ab403b2ed26b..6c2f8f0c0edb 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -87,7 +87,7 @@ static char *omap_mux_options;
87int __init omap_mux_init_gpio(int gpio, int val) 87int __init omap_mux_init_gpio(int gpio, int val)
88{ 88{
89 struct omap_mux_entry *e; 89 struct omap_mux_entry *e;
90 struct omap_mux *gpio_mux; 90 struct omap_mux *gpio_mux = NULL;
91 u16 old_mode; 91 u16 old_mode;
92 u16 mux_mode; 92 u16 mux_mode;
93 int found = 0; 93 int found = 0;
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 13dc9794dcc2..923f9f5f91ce 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -61,10 +61,14 @@ static int __init omap_l2_cache_init(void)
61 omap_smc1(0x102, 0x1); 61 omap_smc1(0x102, 0x1);
62 62
63 /* 63 /*
64 * 32KB way size, 16-way associativity, 64 * 16-way associativity, parity disabled
65 * parity disabled 65 * Way size - 32KB (es1.0)
66 * Way size - 64KB (es2.0 +)
66 */ 67 */
67 l2x0_init(l2cache_base, 0x0e050000, 0xc0000fff); 68 if (omap_rev() == OMAP4430_REV_ES1_0)
69 l2x0_init(l2cache_base, 0x0e050000, 0xc0000fff);
70 else
71 l2x0_init(l2cache_base, 0x0e070000, 0xc0000fff);
68 72
69 return 0; 73 return 0;
70} 74}
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index cb911d7d1a3c..955861acc0c4 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -13,10 +13,102 @@
13 * it under the terms of the GNU General Public License version 2 as 13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation. 14 * published by the Free Software Foundation.
15 * 15 *
16 * This code manages "OMAP modules" (on-chip devices) and their 16 * Introduction
17 * integration with Linux device driver and bus code. 17 * ------------
18 * 18 * One way to view an OMAP SoC is as a collection of largely unrelated
19 * References: 19 * IP blocks connected by interconnects. The IP blocks include
20 * devices such as ARM processors, audio serial interfaces, UARTs,
21 * etc. Some of these devices, like the DSP, are created by TI;
22 * others, like the SGX, largely originate from external vendors. In
23 * TI's documentation, on-chip devices are referred to as "OMAP
24 * modules." Some of these IP blocks are identical across several
25 * OMAP versions. Others are revised frequently.
26 *
27 * These OMAP modules are tied together by various interconnects.
28 * Most of the address and data flow between modules is via OCP-based
29 * interconnects such as the L3 and L4 buses; but there are other
30 * interconnects that distribute the hardware clock tree, handle idle
31 * and reset signaling, supply power, and connect the modules to
32 * various pads or balls on the OMAP package.
33 *
34 * OMAP hwmod provides a consistent way to describe the on-chip
35 * hardware blocks and their integration into the rest of the chip.
36 * This description can be automatically generated from the TI
37 * hardware database. OMAP hwmod provides a standard, consistent API
38 * to reset, enable, idle, and disable these hardware blocks. And
39 * hwmod provides a way for other core code, such as the Linux device
40 * code or the OMAP power management and address space mapping code,
41 * to query the hardware database.
42 *
43 * Using hwmod
44 * -----------
45 * Drivers won't call hwmod functions directly. That is done by the
46 * omap_device code, and in rare occasions, by custom integration code
47 * in arch/arm/ *omap*. The omap_device code includes functions to
48 * build a struct platform_device using omap_hwmod data, and that is
49 * currently how hwmod data is communicated to drivers and to the
50 * Linux driver model. Most drivers will call omap_hwmod functions only
51 * indirectly, via pm_runtime*() functions.
52 *
53 * From a layering perspective, here is where the OMAP hwmod code
54 * fits into the kernel software stack:
55 *
56 * +-------------------------------+
57 * | Device driver code |
58 * | (e.g., drivers/) |
59 * +-------------------------------+
60 * | Linux driver model |
61 * | (platform_device / |
62 * | platform_driver data/code) |
63 * +-------------------------------+
64 * | OMAP core-driver integration |
65 * |(arch/arm/mach-omap2/devices.c)|
66 * +-------------------------------+
67 * | omap_device code |
68 * | (../plat-omap/omap_device.c) |
69 * +-------------------------------+
70 * ----> | omap_hwmod code/data | <-----
71 * | (../mach-omap2/omap_hwmod*) |
72 * +-------------------------------+
73 * | OMAP clock/PRCM/register fns |
74 * | (__raw_{read,write}l, clk*) |
75 * +-------------------------------+
76 *
77 * Device drivers should not contain any OMAP-specific code or data in
78 * them. They should only contain code to operate the IP block that
79 * the driver is responsible for. This is because these IP blocks can
80 * also appear in other SoCs, either from TI (such as DaVinci) or from
81 * other manufacturers; and drivers should be reusable across other
82 * platforms.
83 *
84 * The OMAP hwmod code also will attempt to reset and idle all on-chip
85 * devices upon boot. The goal here is for the kernel to be
86 * completely self-reliant and independent from bootloaders. This is
87 * to ensure a repeatable configuration, both to ensure consistent
88 * runtime behavior, and to make it easier for others to reproduce
89 * bugs.
90 *
91 * OMAP module activity states
92 * ---------------------------
93 * The hwmod code considers modules to be in one of several activity
94 * states. IP blocks start out in an UNKNOWN state, then once they
95 * are registered via the hwmod code, proceed to the REGISTERED state.
96 * Once their clock names are resolved to clock pointers, the module
97 * enters the CLKS_INITED state; and finally, once the module has been
98 * reset and the integration registers programmed, the INITIALIZED state
99 * is entered. The hwmod code will then place the module into either
100 * the IDLE state to save power, or in the case of a critical system
101 * module, the ENABLED state.
102 *
103 * OMAP core integration code can then call omap_hwmod*() functions
104 * directly to move the module between the IDLE, ENABLED, and DISABLED
105 * states, as needed. This is done during both the PM idle loop, and
106 * in the OMAP core integration code's implementation of the PM runtime
107 * functions.
108 *
109 * References
110 * ----------
111 * This is a partial list.
20 * - OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 (SWPU064) 112 * - OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 (SWPU064)
21 * - OMAP2430 Multimedia Device POP Silicon Revision 2.1 (SWPU090) 113 * - OMAP2430 Multimedia Device POP Silicon Revision 2.1 (SWPU090)
22 * - OMAP34xx Multimedia Device Silicon Revision 3.1 (SWPU108) 114 * - OMAP34xx Multimedia Device Silicon Revision 3.1 (SWPU108)
@@ -50,11 +142,13 @@
50#include <plat/powerdomain.h> 142#include <plat/powerdomain.h>
51#include <plat/clock.h> 143#include <plat/clock.h>
52#include <plat/omap_hwmod.h> 144#include <plat/omap_hwmod.h>
145#include <plat/prcm.h>
53 146
54#include "cm.h" 147#include "cm.h"
148#include "prm.h"
55 149
56/* Maximum microseconds to wait for OMAP module to reset */ 150/* Maximum microseconds to wait for OMAP module to softreset */
57#define MAX_MODULE_RESET_WAIT 10000 151#define MAX_MODULE_SOFTRESET_WAIT 10000
58 152
59/* Name of the OMAP hwmod for the MPU */ 153/* Name of the OMAP hwmod for the MPU */
60#define MPU_INITIATOR_NAME "mpu" 154#define MPU_INITIATOR_NAME "mpu"
@@ -544,6 +638,36 @@ static int _disable_clocks(struct omap_hwmod *oh)
544 return 0; 638 return 0;
545} 639}
546 640
641static void _enable_optional_clocks(struct omap_hwmod *oh)
642{
643 struct omap_hwmod_opt_clk *oc;
644 int i;
645
646 pr_debug("omap_hwmod: %s: enabling optional clocks\n", oh->name);
647
648 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
649 if (oc->_clk) {
650 pr_debug("omap_hwmod: enable %s:%s\n", oc->role,
651 oc->_clk->name);
652 clk_enable(oc->_clk);
653 }
654}
655
656static void _disable_optional_clocks(struct omap_hwmod *oh)
657{
658 struct omap_hwmod_opt_clk *oc;
659 int i;
660
661 pr_debug("omap_hwmod: %s: disabling optional clocks\n", oh->name);
662
663 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
664 if (oc->_clk) {
665 pr_debug("omap_hwmod: disable %s:%s\n", oc->role,
666 oc->_clk->name);
667 clk_disable(oc->_clk);
668 }
669}
670
547/** 671/**
548 * _find_mpu_port_index - find hwmod OCP slave port ID intended for MPU use 672 * _find_mpu_port_index - find hwmod OCP slave port ID intended for MPU use
549 * @oh: struct omap_hwmod * 673 * @oh: struct omap_hwmod *
@@ -622,7 +746,7 @@ static void __iomem *_find_mpu_rt_base(struct omap_hwmod *oh, u8 index)
622} 746}
623 747
624/** 748/**
625 * _sysc_enable - try to bring a module out of idle via OCP_SYSCONFIG 749 * _enable_sysc - try to bring a module out of idle via OCP_SYSCONFIG
626 * @oh: struct omap_hwmod * 750 * @oh: struct omap_hwmod *
627 * 751 *
628 * If module is marked as SWSUP_SIDLE, force the module out of slave 752 * If module is marked as SWSUP_SIDLE, force the module out of slave
@@ -630,7 +754,7 @@ static void __iomem *_find_mpu_rt_base(struct omap_hwmod *oh, u8 index)
630 * as SWSUP_MSUSPEND, force the module out of master standby; 754 * as SWSUP_MSUSPEND, force the module out of master standby;
631 * otherwise, configure it for smart-standby. No return value. 755 * otherwise, configure it for smart-standby. No return value.
632 */ 756 */
633static void _sysc_enable(struct omap_hwmod *oh) 757static void _enable_sysc(struct omap_hwmod *oh)
634{ 758{
635 u8 idlemode, sf; 759 u8 idlemode, sf;
636 u32 v; 760 u32 v;
@@ -653,14 +777,6 @@ static void _sysc_enable(struct omap_hwmod *oh)
653 _set_master_standbymode(oh, idlemode, &v); 777 _set_master_standbymode(oh, idlemode, &v);
654 } 778 }
655 779
656 if (sf & SYSC_HAS_AUTOIDLE) {
657 idlemode = (oh->flags & HWMOD_NO_OCP_AUTOIDLE) ?
658 0 : 1;
659 _set_module_autoidle(oh, idlemode, &v);
660 }
661
662 /* XXX OCP ENAWAKEUP bit? */
663
664 /* 780 /*
665 * XXX The clock framework should handle this, by 781 * XXX The clock framework should handle this, by
666 * calling into this code. But this must wait until the 782 * calling into this code. But this must wait until the
@@ -671,10 +787,25 @@ static void _sysc_enable(struct omap_hwmod *oh)
671 _set_clockactivity(oh, oh->class->sysc->clockact, &v); 787 _set_clockactivity(oh, oh->class->sysc->clockact, &v);
672 788
673 _write_sysconfig(v, oh); 789 _write_sysconfig(v, oh);
790
791 /* If slave is in SMARTIDLE, also enable wakeup */
792 if ((sf & SYSC_HAS_SIDLEMODE) && !(oh->flags & HWMOD_SWSUP_SIDLE))
793 _enable_wakeup(oh);
794
795 /*
796 * Set the autoidle bit only after setting the smartidle bit
797 * Setting this will not have any impact on the other modules.
798 */
799 if (sf & SYSC_HAS_AUTOIDLE) {
800 idlemode = (oh->flags & HWMOD_NO_OCP_AUTOIDLE) ?
801 0 : 1;
802 _set_module_autoidle(oh, idlemode, &v);
803 _write_sysconfig(v, oh);
804 }
674} 805}
675 806
676/** 807/**
677 * _sysc_idle - try to put a module into idle via OCP_SYSCONFIG 808 * _idle_sysc - try to put a module into idle via OCP_SYSCONFIG
678 * @oh: struct omap_hwmod * 809 * @oh: struct omap_hwmod *
679 * 810 *
680 * If module is marked as SWSUP_SIDLE, force the module into slave 811 * If module is marked as SWSUP_SIDLE, force the module into slave
@@ -682,7 +813,7 @@ static void _sysc_enable(struct omap_hwmod *oh)
682 * as SWSUP_MSUSPEND, force the module into master standby; otherwise, 813 * as SWSUP_MSUSPEND, force the module into master standby; otherwise,
683 * configure it for smart-standby. No return value. 814 * configure it for smart-standby. No return value.
684 */ 815 */
685static void _sysc_idle(struct omap_hwmod *oh) 816static void _idle_sysc(struct omap_hwmod *oh)
686{ 817{
687 u8 idlemode, sf; 818 u8 idlemode, sf;
688 u32 v; 819 u32 v;
@@ -709,13 +840,13 @@ static void _sysc_idle(struct omap_hwmod *oh)
709} 840}
710 841
711/** 842/**
712 * _sysc_shutdown - force a module into idle via OCP_SYSCONFIG 843 * _shutdown_sysc - force a module into idle via OCP_SYSCONFIG
713 * @oh: struct omap_hwmod * 844 * @oh: struct omap_hwmod *
714 * 845 *
715 * Force the module into slave idle and master suspend. No return 846 * Force the module into slave idle and master suspend. No return
716 * value. 847 * value.
717 */ 848 */
718static void _sysc_shutdown(struct omap_hwmod *oh) 849static void _shutdown_sysc(struct omap_hwmod *oh)
719{ 850{
720 u32 v; 851 u32 v;
721 u8 sf; 852 u8 sf;
@@ -767,10 +898,10 @@ static struct omap_hwmod *_lookup(const char *name)
767 * @data: not used; pass NULL 898 * @data: not used; pass NULL
768 * 899 *
769 * Called by omap_hwmod_late_init() (after omap2_clk_init()). 900 * Called by omap_hwmod_late_init() (after omap2_clk_init()).
770 * Resolves all clock names embedded in the hwmod. Must be called 901 * Resolves all clock names embedded in the hwmod. Returns -EINVAL if
771 * with omap_hwmod_mutex held. Returns -EINVAL if the omap_hwmod 902 * the omap_hwmod has not yet been registered or if the clocks have
772 * has not yet been registered or if the clocks have already been 903 * already been initialized, 0 on success, or a non-zero error on
773 * initialized, 0 on success, or a non-zero error on failure. 904 * failure.
774 */ 905 */
775static int _init_clocks(struct omap_hwmod *oh, void *data) 906static int _init_clocks(struct omap_hwmod *oh, void *data)
776{ 907{
@@ -834,56 +965,202 @@ static int _wait_target_ready(struct omap_hwmod *oh)
834} 965}
835 966
836/** 967/**
968 * _lookup_hardreset - return the register bit shift for this hwmod/reset line
969 * @oh: struct omap_hwmod *
970 * @name: name of the reset line in the context of this hwmod
971 *
972 * Return the bit position of the reset line that match the
973 * input name. Return -ENOENT if not found.
974 */
975static u8 _lookup_hardreset(struct omap_hwmod *oh, const char *name)
976{
977 int i;
978
979 for (i = 0; i < oh->rst_lines_cnt; i++) {
980 const char *rst_line = oh->rst_lines[i].name;
981 if (!strcmp(rst_line, name)) {
982 u8 shift = oh->rst_lines[i].rst_shift;
983 pr_debug("omap_hwmod: %s: _lookup_hardreset: %s: %d\n",
984 oh->name, rst_line, shift);
985
986 return shift;
987 }
988 }
989
990 return -ENOENT;
991}
992
993/**
994 * _assert_hardreset - assert the HW reset line of submodules
995 * contained in the hwmod module.
996 * @oh: struct omap_hwmod *
997 * @name: name of the reset line to lookup and assert
998 *
999 * Some IP like dsp, ipu or iva contain processor that require
1000 * an HW reset line to be assert / deassert in order to enable fully
1001 * the IP.
1002 */
1003static int _assert_hardreset(struct omap_hwmod *oh, const char *name)
1004{
1005 u8 shift;
1006
1007 if (!oh)
1008 return -EINVAL;
1009
1010 shift = _lookup_hardreset(oh, name);
1011 if (IS_ERR_VALUE(shift))
1012 return shift;
1013
1014 if (cpu_is_omap24xx() || cpu_is_omap34xx())
1015 return omap2_prm_assert_hardreset(oh->prcm.omap2.module_offs,
1016 shift);
1017 else if (cpu_is_omap44xx())
1018 return omap4_prm_assert_hardreset(oh->prcm.omap4.rstctrl_reg,
1019 shift);
1020 else
1021 return -EINVAL;
1022}
1023
1024/**
1025 * _deassert_hardreset - deassert the HW reset line of submodules contained
1026 * in the hwmod module.
1027 * @oh: struct omap_hwmod *
1028 * @name: name of the reset line to look up and deassert
1029 *
1030 * Some IP like dsp, ipu or iva contain processor that require
1031 * an HW reset line to be assert / deassert in order to enable fully
1032 * the IP.
1033 */
1034static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
1035{
1036 u8 shift;
1037 int r;
1038
1039 if (!oh)
1040 return -EINVAL;
1041
1042 shift = _lookup_hardreset(oh, name);
1043 if (IS_ERR_VALUE(shift))
1044 return shift;
1045
1046 if (cpu_is_omap24xx() || cpu_is_omap34xx())
1047 r = omap2_prm_deassert_hardreset(oh->prcm.omap2.module_offs,
1048 shift);
1049 else if (cpu_is_omap44xx())
1050 r = omap4_prm_deassert_hardreset(oh->prcm.omap4.rstctrl_reg,
1051 shift);
1052 else
1053 return -EINVAL;
1054
1055 if (r == -EBUSY)
1056 pr_warning("omap_hwmod: %s: failed to hardreset\n", oh->name);
1057
1058 return r;
1059}
1060
1061/**
1062 * _read_hardreset - read the HW reset line state of submodules
1063 * contained in the hwmod module
1064 * @oh: struct omap_hwmod *
1065 * @name: name of the reset line to look up and read
1066 *
1067 * Return the state of the reset line.
1068 */
1069static int _read_hardreset(struct omap_hwmod *oh, const char *name)
1070{
1071 u8 shift;
1072
1073 if (!oh)
1074 return -EINVAL;
1075
1076 shift = _lookup_hardreset(oh, name);
1077 if (IS_ERR_VALUE(shift))
1078 return shift;
1079
1080 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1081 return omap2_prm_is_hardreset_asserted(oh->prcm.omap2.module_offs,
1082 shift);
1083 } else if (cpu_is_omap44xx()) {
1084 return omap4_prm_is_hardreset_asserted(oh->prcm.omap4.rstctrl_reg,
1085 shift);
1086 } else {
1087 return -EINVAL;
1088 }
1089}
1090
1091/**
837 * _reset - reset an omap_hwmod 1092 * _reset - reset an omap_hwmod
838 * @oh: struct omap_hwmod * 1093 * @oh: struct omap_hwmod *
839 * 1094 *
840 * Resets an omap_hwmod @oh via the OCP_SYSCONFIG bit. hwmod must be 1095 * Resets an omap_hwmod @oh via the OCP_SYSCONFIG bit. hwmod must be
841 * enabled for this to work. Must be called with omap_hwmod_mutex 1096 * enabled for this to work. Returns -EINVAL if the hwmod cannot be
842 * held. Returns -EINVAL if the hwmod cannot be reset this way or if 1097 * reset this way or if the hwmod is in the wrong state, -ETIMEDOUT if
843 * the hwmod is in the wrong state, -ETIMEDOUT if the module did not 1098 * the module did not reset in time, or 0 upon success.
844 * reset in time, or 0 upon success. 1099 *
1100 * In OMAP3 a specific SYSSTATUS register is used to get the reset status.
1101 * Starting in OMAP4, some IPs does not have SYSSTATUS register and instead
1102 * use the SYSCONFIG softreset bit to provide the status.
1103 *
1104 * Note that some IP like McBSP does have a reset control but no reset status.
845 */ 1105 */
846static int _reset(struct omap_hwmod *oh) 1106static int _reset(struct omap_hwmod *oh)
847{ 1107{
848 u32 r, v; 1108 u32 v;
849 int c = 0; 1109 int c = 0;
1110 int ret = 0;
850 1111
851 if (!oh->class->sysc || 1112 if (!oh->class->sysc ||
852 !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET) || 1113 !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET))
853 (oh->class->sysc->sysc_flags & SYSS_MISSING))
854 return -EINVAL; 1114 return -EINVAL;
855 1115
856 /* clocks must be on for this operation */ 1116 /* clocks must be on for this operation */
857 if (oh->_state != _HWMOD_STATE_ENABLED) { 1117 if (oh->_state != _HWMOD_STATE_ENABLED) {
858 WARN(1, "omap_hwmod: %s: reset can only be entered from " 1118 pr_warning("omap_hwmod: %s: reset can only be entered from "
859 "enabled state\n", oh->name); 1119 "enabled state\n", oh->name);
860 return -EINVAL; 1120 return -EINVAL;
861 } 1121 }
862 1122
1123 /* For some modules, all optionnal clocks need to be enabled as well */
1124 if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET)
1125 _enable_optional_clocks(oh);
1126
863 pr_debug("omap_hwmod: %s: resetting\n", oh->name); 1127 pr_debug("omap_hwmod: %s: resetting\n", oh->name);
864 1128
865 v = oh->_sysc_cache; 1129 v = oh->_sysc_cache;
866 r = _set_softreset(oh, &v); 1130 ret = _set_softreset(oh, &v);
867 if (r) 1131 if (ret)
868 return r; 1132 goto dis_opt_clks;
869 _write_sysconfig(v, oh); 1133 _write_sysconfig(v, oh);
870 1134
871 omap_test_timeout((omap_hwmod_readl(oh, oh->class->sysc->syss_offs) & 1135 if (oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)
872 SYSS_RESETDONE_MASK), 1136 omap_test_timeout((omap_hwmod_readl(oh,
873 MAX_MODULE_RESET_WAIT, c); 1137 oh->class->sysc->syss_offs)
874 1138 & SYSS_RESETDONE_MASK),
875 if (c == MAX_MODULE_RESET_WAIT) 1139 MAX_MODULE_SOFTRESET_WAIT, c);
876 WARN(1, "omap_hwmod: %s: failed to reset in %d usec\n", 1140 else if (oh->class->sysc->sysc_flags & SYSC_HAS_RESET_STATUS)
877 oh->name, MAX_MODULE_RESET_WAIT); 1141 omap_test_timeout(!(omap_hwmod_readl(oh,
1142 oh->class->sysc->sysc_offs)
1143 & SYSC_TYPE2_SOFTRESET_MASK),
1144 MAX_MODULE_SOFTRESET_WAIT, c);
1145
1146 if (c == MAX_MODULE_SOFTRESET_WAIT)
1147 pr_warning("omap_hwmod: %s: softreset failed (waited %d usec)\n",
1148 oh->name, MAX_MODULE_SOFTRESET_WAIT);
878 else 1149 else
879 pr_debug("omap_hwmod: %s: reset in %d usec\n", oh->name, c); 1150 pr_debug("omap_hwmod: %s: softreset in %d usec\n", oh->name, c);
880 1151
881 /* 1152 /*
882 * XXX add _HWMOD_STATE_WEDGED for modules that don't come back from 1153 * XXX add _HWMOD_STATE_WEDGED for modules that don't come back from
883 * _wait_target_ready() or _reset() 1154 * _wait_target_ready() or _reset()
884 */ 1155 */
885 1156
886 return (c == MAX_MODULE_RESET_WAIT) ? -ETIMEDOUT : 0; 1157 ret = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;
1158
1159dis_opt_clks:
1160 if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET)
1161 _disable_optional_clocks(oh);
1162
1163 return ret;
887} 1164}
888 1165
889/** 1166/**
@@ -891,9 +1168,11 @@ static int _reset(struct omap_hwmod *oh)
891 * @oh: struct omap_hwmod * 1168 * @oh: struct omap_hwmod *
892 * 1169 *
893 * Enables an omap_hwmod @oh such that the MPU can access the hwmod's 1170 * Enables an omap_hwmod @oh such that the MPU can access the hwmod's
894 * register target. Must be called with omap_hwmod_mutex held. 1171 * register target. (This function has a full name --
895 * Returns -EINVAL if the hwmod is in the wrong state or passes along 1172 * _omap_hwmod_enable() rather than simply _enable() -- because it is
896 * the return value of _wait_target_ready(). 1173 * currently required by the pm34xx.c idle loop.) Returns -EINVAL if
1174 * the hwmod is in the wrong state or passes along the return value of
1175 * _wait_target_ready().
897 */ 1176 */
898int _omap_hwmod_enable(struct omap_hwmod *oh) 1177int _omap_hwmod_enable(struct omap_hwmod *oh)
899{ 1178{
@@ -909,6 +1188,15 @@ int _omap_hwmod_enable(struct omap_hwmod *oh)
909 1188
910 pr_debug("omap_hwmod: %s: enabling\n", oh->name); 1189 pr_debug("omap_hwmod: %s: enabling\n", oh->name);
911 1190
1191 /*
1192 * If an IP contains only one HW reset line, then de-assert it in order
1193 * to allow to enable the clocks. Otherwise the PRCM will return
1194 * Intransition status, and the init will failed.
1195 */
1196 if ((oh->_state == _HWMOD_STATE_INITIALIZED ||
1197 oh->_state == _HWMOD_STATE_DISABLED) && oh->rst_lines_cnt == 1)
1198 _deassert_hardreset(oh, oh->rst_lines[0].name);
1199
912 /* XXX mux balls */ 1200 /* XXX mux balls */
913 1201
914 _add_initiator_dep(oh, mpu_oh); 1202 _add_initiator_dep(oh, mpu_oh);
@@ -922,7 +1210,7 @@ int _omap_hwmod_enable(struct omap_hwmod *oh)
922 if (oh->class->sysc) { 1210 if (oh->class->sysc) {
923 if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED)) 1211 if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED))
924 _update_sysc_cache(oh); 1212 _update_sysc_cache(oh);
925 _sysc_enable(oh); 1213 _enable_sysc(oh);
926 } 1214 }
927 } else { 1215 } else {
928 pr_debug("omap_hwmod: %s: _wait_target_ready: %d\n", 1216 pr_debug("omap_hwmod: %s: _wait_target_ready: %d\n",
@@ -933,12 +1221,14 @@ int _omap_hwmod_enable(struct omap_hwmod *oh)
933} 1221}
934 1222
935/** 1223/**
936 * _idle - idle an omap_hwmod 1224 * _omap_hwmod_idle - idle an omap_hwmod
937 * @oh: struct omap_hwmod * 1225 * @oh: struct omap_hwmod *
938 * 1226 *
939 * Idles an omap_hwmod @oh. This should be called once the hwmod has 1227 * Idles an omap_hwmod @oh. This should be called once the hwmod has
940 * no further work. Returns -EINVAL if the hwmod is in the wrong 1228 * no further work. (This function has a full name --
941 * state or returns 0. 1229 * _omap_hwmod_idle() rather than simply _idle() -- because it is
1230 * currently required by the pm34xx.c idle loop.) Returns -EINVAL if
1231 * the hwmod is in the wrong state or returns 0.
942 */ 1232 */
943int _omap_hwmod_idle(struct omap_hwmod *oh) 1233int _omap_hwmod_idle(struct omap_hwmod *oh)
944{ 1234{
@@ -951,7 +1241,7 @@ int _omap_hwmod_idle(struct omap_hwmod *oh)
951 pr_debug("omap_hwmod: %s: idling\n", oh->name); 1241 pr_debug("omap_hwmod: %s: idling\n", oh->name);
952 1242
953 if (oh->class->sysc) 1243 if (oh->class->sysc)
954 _sysc_idle(oh); 1244 _idle_sysc(oh);
955 _del_initiator_dep(oh, mpu_oh); 1245 _del_initiator_dep(oh, mpu_oh);
956 _disable_clocks(oh); 1246 _disable_clocks(oh);
957 1247
@@ -981,10 +1271,21 @@ static int _shutdown(struct omap_hwmod *oh)
981 pr_debug("omap_hwmod: %s: disabling\n", oh->name); 1271 pr_debug("omap_hwmod: %s: disabling\n", oh->name);
982 1272
983 if (oh->class->sysc) 1273 if (oh->class->sysc)
984 _sysc_shutdown(oh); 1274 _shutdown_sysc(oh);
985 _del_initiator_dep(oh, mpu_oh); 1275
986 /* XXX what about the other system initiators here? DMA, tesla, d2d */ 1276 /*
987 _disable_clocks(oh); 1277 * If an IP contains only one HW reset line, then assert it
1278 * before disabling the clocks and shutting down the IP.
1279 */
1280 if (oh->rst_lines_cnt == 1)
1281 _assert_hardreset(oh, oh->rst_lines[0].name);
1282
1283 /* clocks and deps are already disabled in idle */
1284 if (oh->_state == _HWMOD_STATE_ENABLED) {
1285 _del_initiator_dep(oh, mpu_oh);
1286 /* XXX what about the other system initiators here? dma, dsp */
1287 _disable_clocks(oh);
1288 }
988 /* XXX Should this code also force-disable the optional clocks? */ 1289 /* XXX Should this code also force-disable the optional clocks? */
989 1290
990 /* XXX mux any associated balls to safe mode */ 1291 /* XXX mux any associated balls to safe mode */
@@ -1000,11 +1301,10 @@ static int _shutdown(struct omap_hwmod *oh)
1000 * @skip_setup_idle_p: do not idle hwmods at the end of the fn if 1 1301 * @skip_setup_idle_p: do not idle hwmods at the end of the fn if 1
1001 * 1302 *
1002 * Writes the CLOCKACTIVITY bits @clockact to the hwmod @oh 1303 * Writes the CLOCKACTIVITY bits @clockact to the hwmod @oh
1003 * OCP_SYSCONFIG register. Must be called with omap_hwmod_mutex held. 1304 * OCP_SYSCONFIG register. @skip_setup_idle is intended to be used on
1004 * @skip_setup_idle is intended to be used on a system that will not 1305 * a system that will not call omap_hwmod_enable() to enable devices
1005 * call omap_hwmod_enable() to enable devices (e.g., a system without 1306 * (e.g., a system without PM runtime). Returns -EINVAL if the hwmod
1006 * PM runtime). Returns -EINVAL if the hwmod is in the wrong state or 1307 * is in the wrong state or returns 0.
1007 * returns 0.
1008 */ 1308 */
1009static int _setup(struct omap_hwmod *oh, void *data) 1309static int _setup(struct omap_hwmod *oh, void *data)
1010{ 1310{
@@ -1034,8 +1334,19 @@ static int _setup(struct omap_hwmod *oh, void *data)
1034 } 1334 }
1035 } 1335 }
1036 1336
1337 mutex_init(&oh->_mutex);
1037 oh->_state = _HWMOD_STATE_INITIALIZED; 1338 oh->_state = _HWMOD_STATE_INITIALIZED;
1038 1339
1340 /*
1341 * In the case of hwmod with hardreset that should not be
1342 * de-assert at boot time, we have to keep the module
1343 * initialized, because we cannot enable it properly with the
1344 * reset asserted. Exit without warning because that behavior is
1345 * expected.
1346 */
1347 if ((oh->flags & HWMOD_INIT_NO_RESET) && oh->rst_lines_cnt == 1)
1348 return 0;
1349
1039 r = _omap_hwmod_enable(oh); 1350 r = _omap_hwmod_enable(oh);
1040 if (r) { 1351 if (r) {
1041 pr_warning("omap_hwmod: %s: cannot be enabled (%d)\n", 1352 pr_warning("omap_hwmod: %s: cannot be enabled (%d)\n",
@@ -1044,16 +1355,16 @@ static int _setup(struct omap_hwmod *oh, void *data)
1044 } 1355 }
1045 1356
1046 if (!(oh->flags & HWMOD_INIT_NO_RESET)) { 1357 if (!(oh->flags & HWMOD_INIT_NO_RESET)) {
1358 _reset(oh);
1359
1047 /* 1360 /*
1048 * XXX Do the OCP_SYSCONFIG bits need to be 1361 * OCP_SYSCONFIG bits need to be reprogrammed after a softreset.
1049 * reprogrammed after a reset? If not, then this can 1362 * The _omap_hwmod_enable() function should be split to
1050 * be removed. If they do, then probably the 1363 * avoid the rewrite of the OCP_SYSCONFIG register.
1051 * _omap_hwmod_enable() function should be split to avoid the
1052 * rewrite of the OCP_SYSCONFIG register.
1053 */ 1364 */
1054 if (oh->class->sysc) { 1365 if (oh->class->sysc) {
1055 _update_sysc_cache(oh); 1366 _update_sysc_cache(oh);
1056 _sysc_enable(oh); 1367 _enable_sysc(oh);
1057 } 1368 }
1058 } 1369 }
1059 1370
@@ -1309,7 +1620,7 @@ int omap_hwmod_unregister(struct omap_hwmod *oh)
1309 * omap_hwmod_enable - enable an omap_hwmod 1620 * omap_hwmod_enable - enable an omap_hwmod
1310 * @oh: struct omap_hwmod * 1621 * @oh: struct omap_hwmod *
1311 * 1622 *
1312 * Enable an omap_hwomd @oh. Intended to be called by omap_device_enable(). 1623 * Enable an omap_hwmod @oh. Intended to be called by omap_device_enable().
1313 * Returns -EINVAL on error or passes along the return value from _enable(). 1624 * Returns -EINVAL on error or passes along the return value from _enable().
1314 */ 1625 */
1315int omap_hwmod_enable(struct omap_hwmod *oh) 1626int omap_hwmod_enable(struct omap_hwmod *oh)
@@ -1319,9 +1630,9 @@ int omap_hwmod_enable(struct omap_hwmod *oh)
1319 if (!oh) 1630 if (!oh)
1320 return -EINVAL; 1631 return -EINVAL;
1321 1632
1322 mutex_lock(&omap_hwmod_mutex); 1633 mutex_lock(&oh->_mutex);
1323 r = _omap_hwmod_enable(oh); 1634 r = _omap_hwmod_enable(oh);
1324 mutex_unlock(&omap_hwmod_mutex); 1635 mutex_unlock(&oh->_mutex);
1325 1636
1326 return r; 1637 return r;
1327} 1638}
@@ -1331,7 +1642,7 @@ int omap_hwmod_enable(struct omap_hwmod *oh)
1331 * omap_hwmod_idle - idle an omap_hwmod 1642 * omap_hwmod_idle - idle an omap_hwmod
1332 * @oh: struct omap_hwmod * 1643 * @oh: struct omap_hwmod *
1333 * 1644 *
1334 * Idle an omap_hwomd @oh. Intended to be called by omap_device_idle(). 1645 * Idle an omap_hwmod @oh. Intended to be called by omap_device_idle().
1335 * Returns -EINVAL on error or passes along the return value from _idle(). 1646 * Returns -EINVAL on error or passes along the return value from _idle().
1336 */ 1647 */
1337int omap_hwmod_idle(struct omap_hwmod *oh) 1648int omap_hwmod_idle(struct omap_hwmod *oh)
@@ -1339,9 +1650,9 @@ int omap_hwmod_idle(struct omap_hwmod *oh)
1339 if (!oh) 1650 if (!oh)
1340 return -EINVAL; 1651 return -EINVAL;
1341 1652
1342 mutex_lock(&omap_hwmod_mutex); 1653 mutex_lock(&oh->_mutex);
1343 _omap_hwmod_idle(oh); 1654 _omap_hwmod_idle(oh);
1344 mutex_unlock(&omap_hwmod_mutex); 1655 mutex_unlock(&oh->_mutex);
1345 1656
1346 return 0; 1657 return 0;
1347} 1658}
@@ -1350,7 +1661,7 @@ int omap_hwmod_idle(struct omap_hwmod *oh)
1350 * omap_hwmod_shutdown - shutdown an omap_hwmod 1661 * omap_hwmod_shutdown - shutdown an omap_hwmod
1351 * @oh: struct omap_hwmod * 1662 * @oh: struct omap_hwmod *
1352 * 1663 *
1353 * Shutdown an omap_hwomd @oh. Intended to be called by 1664 * Shutdown an omap_hwmod @oh. Intended to be called by
1354 * omap_device_shutdown(). Returns -EINVAL on error or passes along 1665 * omap_device_shutdown(). Returns -EINVAL on error or passes along
1355 * the return value from _shutdown(). 1666 * the return value from _shutdown().
1356 */ 1667 */
@@ -1359,9 +1670,9 @@ int omap_hwmod_shutdown(struct omap_hwmod *oh)
1359 if (!oh) 1670 if (!oh)
1360 return -EINVAL; 1671 return -EINVAL;
1361 1672
1362 mutex_lock(&omap_hwmod_mutex); 1673 mutex_lock(&oh->_mutex);
1363 _shutdown(oh); 1674 _shutdown(oh);
1364 mutex_unlock(&omap_hwmod_mutex); 1675 mutex_unlock(&oh->_mutex);
1365 1676
1366 return 0; 1677 return 0;
1367} 1678}
@@ -1374,9 +1685,9 @@ int omap_hwmod_shutdown(struct omap_hwmod *oh)
1374 */ 1685 */
1375int omap_hwmod_enable_clocks(struct omap_hwmod *oh) 1686int omap_hwmod_enable_clocks(struct omap_hwmod *oh)
1376{ 1687{
1377 mutex_lock(&omap_hwmod_mutex); 1688 mutex_lock(&oh->_mutex);
1378 _enable_clocks(oh); 1689 _enable_clocks(oh);
1379 mutex_unlock(&omap_hwmod_mutex); 1690 mutex_unlock(&oh->_mutex);
1380 1691
1381 return 0; 1692 return 0;
1382} 1693}
@@ -1389,9 +1700,9 @@ int omap_hwmod_enable_clocks(struct omap_hwmod *oh)
1389 */ 1700 */
1390int omap_hwmod_disable_clocks(struct omap_hwmod *oh) 1701int omap_hwmod_disable_clocks(struct omap_hwmod *oh)
1391{ 1702{
1392 mutex_lock(&omap_hwmod_mutex); 1703 mutex_lock(&oh->_mutex);
1393 _disable_clocks(oh); 1704 _disable_clocks(oh);
1394 mutex_unlock(&omap_hwmod_mutex); 1705 mutex_unlock(&oh->_mutex);
1395 1706
1396 return 0; 1707 return 0;
1397} 1708}
@@ -1430,20 +1741,18 @@ void omap_hwmod_ocp_barrier(struct omap_hwmod *oh)
1430 * 1741 *
1431 * Under some conditions, a driver may wish to reset the entire device. 1742 * Under some conditions, a driver may wish to reset the entire device.
1432 * Called from omap_device code. Returns -EINVAL on error or passes along 1743 * Called from omap_device code. Returns -EINVAL on error or passes along
1433 * the return value from _reset()/_enable(). 1744 * the return value from _reset().
1434 */ 1745 */
1435int omap_hwmod_reset(struct omap_hwmod *oh) 1746int omap_hwmod_reset(struct omap_hwmod *oh)
1436{ 1747{
1437 int r; 1748 int r;
1438 1749
1439 if (!oh || !(oh->_state & _HWMOD_STATE_ENABLED)) 1750 if (!oh)
1440 return -EINVAL; 1751 return -EINVAL;
1441 1752
1442 mutex_lock(&omap_hwmod_mutex); 1753 mutex_lock(&oh->_mutex);
1443 r = _reset(oh); 1754 r = _reset(oh);
1444 if (!r) 1755 mutex_unlock(&oh->_mutex);
1445 r = _omap_hwmod_enable(oh);
1446 mutex_unlock(&omap_hwmod_mutex);
1447 1756
1448 return r; 1757 return r;
1449} 1758}
@@ -1468,7 +1777,7 @@ int omap_hwmod_count_resources(struct omap_hwmod *oh)
1468{ 1777{
1469 int ret, i; 1778 int ret, i;
1470 1779
1471 ret = oh->mpu_irqs_cnt + oh->sdma_chs_cnt; 1780 ret = oh->mpu_irqs_cnt + oh->sdma_reqs_cnt;
1472 1781
1473 for (i = 0; i < oh->slaves_cnt; i++) 1782 for (i = 0; i < oh->slaves_cnt; i++)
1474 ret += oh->slaves[i]->addr_cnt; 1783 ret += oh->slaves[i]->addr_cnt;
@@ -1501,10 +1810,10 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
1501 r++; 1810 r++;
1502 } 1811 }
1503 1812
1504 for (i = 0; i < oh->sdma_chs_cnt; i++) { 1813 for (i = 0; i < oh->sdma_reqs_cnt; i++) {
1505 (res + r)->name = (oh->sdma_chs + i)->name; 1814 (res + r)->name = (oh->sdma_reqs + i)->name;
1506 (res + r)->start = (oh->sdma_chs + i)->dma_ch; 1815 (res + r)->start = (oh->sdma_reqs + i)->dma_req;
1507 (res + r)->end = (oh->sdma_chs + i)->dma_ch; 1816 (res + r)->end = (oh->sdma_reqs + i)->dma_req;
1508 (res + r)->flags = IORESOURCE_DMA; 1817 (res + r)->flags = IORESOURCE_DMA;
1509 r++; 1818 r++;
1510 } 1819 }
@@ -1644,9 +1953,9 @@ int omap_hwmod_enable_wakeup(struct omap_hwmod *oh)
1644 !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) 1953 !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP))
1645 return -EINVAL; 1954 return -EINVAL;
1646 1955
1647 mutex_lock(&omap_hwmod_mutex); 1956 mutex_lock(&oh->_mutex);
1648 _enable_wakeup(oh); 1957 _enable_wakeup(oh);
1649 mutex_unlock(&omap_hwmod_mutex); 1958 mutex_unlock(&oh->_mutex);
1650 1959
1651 return 0; 1960 return 0;
1652} 1961}
@@ -1669,14 +1978,92 @@ int omap_hwmod_disable_wakeup(struct omap_hwmod *oh)
1669 !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) 1978 !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP))
1670 return -EINVAL; 1979 return -EINVAL;
1671 1980
1672 mutex_lock(&omap_hwmod_mutex); 1981 mutex_lock(&oh->_mutex);
1673 _disable_wakeup(oh); 1982 _disable_wakeup(oh);
1674 mutex_unlock(&omap_hwmod_mutex); 1983 mutex_unlock(&oh->_mutex);
1675 1984
1676 return 0; 1985 return 0;
1677} 1986}
1678 1987
1679/** 1988/**
1989 * omap_hwmod_assert_hardreset - assert the HW reset line of submodules
1990 * contained in the hwmod module.
1991 * @oh: struct omap_hwmod *
1992 * @name: name of the reset line to lookup and assert
1993 *
1994 * Some IP like dsp, ipu or iva contain processor that require
1995 * an HW reset line to be assert / deassert in order to enable fully
1996 * the IP. Returns -EINVAL if @oh is null or if the operation is not
1997 * yet supported on this OMAP; otherwise, passes along the return value
1998 * from _assert_hardreset().
1999 */
2000int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name)
2001{
2002 int ret;
2003
2004 if (!oh)
2005 return -EINVAL;
2006
2007 mutex_lock(&oh->_mutex);
2008 ret = _assert_hardreset(oh, name);
2009 mutex_unlock(&oh->_mutex);
2010
2011 return ret;
2012}
2013
2014/**
2015 * omap_hwmod_deassert_hardreset - deassert the HW reset line of submodules
2016 * contained in the hwmod module.
2017 * @oh: struct omap_hwmod *
2018 * @name: name of the reset line to look up and deassert
2019 *
2020 * Some IP like dsp, ipu or iva contain processor that require
2021 * an HW reset line to be assert / deassert in order to enable fully
2022 * the IP. Returns -EINVAL if @oh is null or if the operation is not
2023 * yet supported on this OMAP; otherwise, passes along the return value
2024 * from _deassert_hardreset().
2025 */
2026int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name)
2027{
2028 int ret;
2029
2030 if (!oh)
2031 return -EINVAL;
2032
2033 mutex_lock(&oh->_mutex);
2034 ret = _deassert_hardreset(oh, name);
2035 mutex_unlock(&oh->_mutex);
2036
2037 return ret;
2038}
2039
2040/**
2041 * omap_hwmod_read_hardreset - read the HW reset line state of submodules
2042 * contained in the hwmod module
2043 * @oh: struct omap_hwmod *
2044 * @name: name of the reset line to look up and read
2045 *
2046 * Return the current state of the hwmod @oh's reset line named @name:
2047 * returns -EINVAL upon parameter error or if this operation
2048 * is unsupported on the current OMAP; otherwise, passes along the return
2049 * value from _read_hardreset().
2050 */
2051int omap_hwmod_read_hardreset(struct omap_hwmod *oh, const char *name)
2052{
2053 int ret;
2054
2055 if (!oh)
2056 return -EINVAL;
2057
2058 mutex_lock(&oh->_mutex);
2059 ret = _read_hardreset(oh, name);
2060 mutex_unlock(&oh->_mutex);
2061
2062 return ret;
2063}
2064
2065
2066/**
1680 * omap_hwmod_for_each_by_class - call @fn for each hwmod of class @classname 2067 * omap_hwmod_for_each_by_class - call @fn for each hwmod of class @classname
1681 * @classname: struct omap_hwmod_class name to search for 2068 * @classname: struct omap_hwmod_class name to search for
1682 * @fn: callback function pointer to call for each hwmod in class @classname 2069 * @fn: callback function pointer to call for each hwmod in class @classname
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
new file mode 100644
index 000000000000..e20b0eebc6d9
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -0,0 +1,482 @@
1/*
2 * Hardware modules present on the OMAP44xx chips
3 *
4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
6 *
7 * Paul Walmsley
8 * Benoit Cousson
9 *
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20
21#include <linux/io.h>
22
23#include <plat/omap_hwmod.h>
24#include <plat/cpu.h>
25
26#include "omap_hwmod_common_data.h"
27
28#include "cm.h"
29#include "prm-regbits-44xx.h"
30
31/* Base offset for all OMAP4 interrupts external to MPUSS */
32#define OMAP44XX_IRQ_GIC_START 32
33
34/* Base offset for all OMAP4 dma requests */
35#define OMAP44XX_DMA_REQ_START 1
36
37/* Backward references (IPs with Bus Master capability) */
38static struct omap_hwmod omap44xx_dmm_hwmod;
39static struct omap_hwmod omap44xx_emif_fw_hwmod;
40static struct omap_hwmod omap44xx_l3_instr_hwmod;
41static struct omap_hwmod omap44xx_l3_main_1_hwmod;
42static struct omap_hwmod omap44xx_l3_main_2_hwmod;
43static struct omap_hwmod omap44xx_l3_main_3_hwmod;
44static struct omap_hwmod omap44xx_l4_abe_hwmod;
45static struct omap_hwmod omap44xx_l4_cfg_hwmod;
46static struct omap_hwmod omap44xx_l4_per_hwmod;
47static struct omap_hwmod omap44xx_l4_wkup_hwmod;
48static struct omap_hwmod omap44xx_mpu_hwmod;
49static struct omap_hwmod omap44xx_mpu_private_hwmod;
50
51/*
52 * Interconnects omap_hwmod structures
53 * hwmods that compose the global OMAP interconnect
54 */
55
56/*
57 * 'dmm' class
58 * instance(s): dmm
59 */
60static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
61 .name = "dmm",
62};
63
64/* dmm interface data */
65/* l3_main_1 -> dmm */
66static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
67 .master = &omap44xx_l3_main_1_hwmod,
68 .slave = &omap44xx_dmm_hwmod,
69 .clk = "l3_div_ck",
70 .user = OCP_USER_MPU | OCP_USER_SDMA,
71};
72
73/* mpu -> dmm */
74static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
75 .master = &omap44xx_mpu_hwmod,
76 .slave = &omap44xx_dmm_hwmod,
77 .clk = "l3_div_ck",
78 .user = OCP_USER_MPU | OCP_USER_SDMA,
79};
80
81/* dmm slave ports */
82static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
83 &omap44xx_l3_main_1__dmm,
84 &omap44xx_mpu__dmm,
85};
86
87static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
88 { .irq = 113 + OMAP44XX_IRQ_GIC_START },
89};
90
91static struct omap_hwmod omap44xx_dmm_hwmod = {
92 .name = "dmm",
93 .class = &omap44xx_dmm_hwmod_class,
94 .slaves = omap44xx_dmm_slaves,
95 .slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves),
96 .mpu_irqs = omap44xx_dmm_irqs,
97 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dmm_irqs),
98 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
99};
100
101/*
102 * 'emif_fw' class
103 * instance(s): emif_fw
104 */
105static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
106 .name = "emif_fw",
107};
108
109/* emif_fw interface data */
110/* dmm -> emif_fw */
111static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
112 .master = &omap44xx_dmm_hwmod,
113 .slave = &omap44xx_emif_fw_hwmod,
114 .clk = "l3_div_ck",
115 .user = OCP_USER_MPU | OCP_USER_SDMA,
116};
117
118/* l4_cfg -> emif_fw */
119static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
120 .master = &omap44xx_l4_cfg_hwmod,
121 .slave = &omap44xx_emif_fw_hwmod,
122 .clk = "l4_div_ck",
123 .user = OCP_USER_MPU | OCP_USER_SDMA,
124};
125
126/* emif_fw slave ports */
127static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
128 &omap44xx_dmm__emif_fw,
129 &omap44xx_l4_cfg__emif_fw,
130};
131
132static struct omap_hwmod omap44xx_emif_fw_hwmod = {
133 .name = "emif_fw",
134 .class = &omap44xx_emif_fw_hwmod_class,
135 .slaves = omap44xx_emif_fw_slaves,
136 .slaves_cnt = ARRAY_SIZE(omap44xx_emif_fw_slaves),
137 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
138};
139
140/*
141 * 'l3' class
142 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
143 */
144static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
145 .name = "l3",
146};
147
148/* l3_instr interface data */
149/* l3_main_3 -> l3_instr */
150static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
151 .master = &omap44xx_l3_main_3_hwmod,
152 .slave = &omap44xx_l3_instr_hwmod,
153 .clk = "l3_div_ck",
154 .user = OCP_USER_MPU | OCP_USER_SDMA,
155};
156
157/* l3_instr slave ports */
158static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
159 &omap44xx_l3_main_3__l3_instr,
160};
161
162static struct omap_hwmod omap44xx_l3_instr_hwmod = {
163 .name = "l3_instr",
164 .class = &omap44xx_l3_hwmod_class,
165 .slaves = omap44xx_l3_instr_slaves,
166 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_instr_slaves),
167 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
168};
169
170/* l3_main_2 -> l3_main_1 */
171static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
172 .master = &omap44xx_l3_main_2_hwmod,
173 .slave = &omap44xx_l3_main_1_hwmod,
174 .clk = "l3_div_ck",
175 .user = OCP_USER_MPU | OCP_USER_SDMA,
176};
177
178/* l4_cfg -> l3_main_1 */
179static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
180 .master = &omap44xx_l4_cfg_hwmod,
181 .slave = &omap44xx_l3_main_1_hwmod,
182 .clk = "l4_div_ck",
183 .user = OCP_USER_MPU | OCP_USER_SDMA,
184};
185
186/* mpu -> l3_main_1 */
187static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
188 .master = &omap44xx_mpu_hwmod,
189 .slave = &omap44xx_l3_main_1_hwmod,
190 .clk = "l3_div_ck",
191 .user = OCP_USER_MPU | OCP_USER_SDMA,
192};
193
194/* l3_main_1 slave ports */
195static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
196 &omap44xx_l3_main_2__l3_main_1,
197 &omap44xx_l4_cfg__l3_main_1,
198 &omap44xx_mpu__l3_main_1,
199};
200
201static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
202 .name = "l3_main_1",
203 .class = &omap44xx_l3_hwmod_class,
204 .slaves = omap44xx_l3_main_1_slaves,
205 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
206 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
207};
208
209/* l3_main_2 interface data */
210/* l3_main_1 -> l3_main_2 */
211static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
212 .master = &omap44xx_l3_main_1_hwmod,
213 .slave = &omap44xx_l3_main_2_hwmod,
214 .clk = "l3_div_ck",
215 .user = OCP_USER_MPU | OCP_USER_SDMA,
216};
217
218/* l4_cfg -> l3_main_2 */
219static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
220 .master = &omap44xx_l4_cfg_hwmod,
221 .slave = &omap44xx_l3_main_2_hwmod,
222 .clk = "l4_div_ck",
223 .user = OCP_USER_MPU | OCP_USER_SDMA,
224};
225
226/* l3_main_2 slave ports */
227static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
228 &omap44xx_l3_main_1__l3_main_2,
229 &omap44xx_l4_cfg__l3_main_2,
230};
231
232static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
233 .name = "l3_main_2",
234 .class = &omap44xx_l3_hwmod_class,
235 .slaves = omap44xx_l3_main_2_slaves,
236 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
237 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
238};
239
240/* l3_main_3 interface data */
241/* l3_main_1 -> l3_main_3 */
242static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
243 .master = &omap44xx_l3_main_1_hwmod,
244 .slave = &omap44xx_l3_main_3_hwmod,
245 .clk = "l3_div_ck",
246 .user = OCP_USER_MPU | OCP_USER_SDMA,
247};
248
249/* l3_main_2 -> l3_main_3 */
250static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
251 .master = &omap44xx_l3_main_2_hwmod,
252 .slave = &omap44xx_l3_main_3_hwmod,
253 .clk = "l3_div_ck",
254 .user = OCP_USER_MPU | OCP_USER_SDMA,
255};
256
257/* l4_cfg -> l3_main_3 */
258static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
259 .master = &omap44xx_l4_cfg_hwmod,
260 .slave = &omap44xx_l3_main_3_hwmod,
261 .clk = "l4_div_ck",
262 .user = OCP_USER_MPU | OCP_USER_SDMA,
263};
264
265/* l3_main_3 slave ports */
266static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
267 &omap44xx_l3_main_1__l3_main_3,
268 &omap44xx_l3_main_2__l3_main_3,
269 &omap44xx_l4_cfg__l3_main_3,
270};
271
272static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
273 .name = "l3_main_3",
274 .class = &omap44xx_l3_hwmod_class,
275 .slaves = omap44xx_l3_main_3_slaves,
276 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
277 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
278};
279
280/*
281 * 'l4' class
282 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
283 */
284static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
285 .name = "l4",
286};
287
288/* l4_abe interface data */
289/* l3_main_1 -> l4_abe */
290static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
291 .master = &omap44xx_l3_main_1_hwmod,
292 .slave = &omap44xx_l4_abe_hwmod,
293 .clk = "l3_div_ck",
294 .user = OCP_USER_MPU | OCP_USER_SDMA,
295};
296
297/* mpu -> l4_abe */
298static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
299 .master = &omap44xx_mpu_hwmod,
300 .slave = &omap44xx_l4_abe_hwmod,
301 .clk = "ocp_abe_iclk",
302 .user = OCP_USER_MPU | OCP_USER_SDMA,
303};
304
305/* l4_abe slave ports */
306static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
307 &omap44xx_l3_main_1__l4_abe,
308 &omap44xx_mpu__l4_abe,
309};
310
311static struct omap_hwmod omap44xx_l4_abe_hwmod = {
312 .name = "l4_abe",
313 .class = &omap44xx_l4_hwmod_class,
314 .slaves = omap44xx_l4_abe_slaves,
315 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_abe_slaves),
316 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
317};
318
319/* l4_cfg interface data */
320/* l3_main_1 -> l4_cfg */
321static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
322 .master = &omap44xx_l3_main_1_hwmod,
323 .slave = &omap44xx_l4_cfg_hwmod,
324 .clk = "l3_div_ck",
325 .user = OCP_USER_MPU | OCP_USER_SDMA,
326};
327
328/* l4_cfg slave ports */
329static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
330 &omap44xx_l3_main_1__l4_cfg,
331};
332
333static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
334 .name = "l4_cfg",
335 .class = &omap44xx_l4_hwmod_class,
336 .slaves = omap44xx_l4_cfg_slaves,
337 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
338 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
339};
340
341/* l4_per interface data */
342/* l3_main_2 -> l4_per */
343static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
344 .master = &omap44xx_l3_main_2_hwmod,
345 .slave = &omap44xx_l4_per_hwmod,
346 .clk = "l3_div_ck",
347 .user = OCP_USER_MPU | OCP_USER_SDMA,
348};
349
350/* l4_per slave ports */
351static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
352 &omap44xx_l3_main_2__l4_per,
353};
354
355static struct omap_hwmod omap44xx_l4_per_hwmod = {
356 .name = "l4_per",
357 .class = &omap44xx_l4_hwmod_class,
358 .slaves = omap44xx_l4_per_slaves,
359 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_per_slaves),
360 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
361};
362
363/* l4_wkup interface data */
364/* l4_cfg -> l4_wkup */
365static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
366 .master = &omap44xx_l4_cfg_hwmod,
367 .slave = &omap44xx_l4_wkup_hwmod,
368 .clk = "l4_div_ck",
369 .user = OCP_USER_MPU | OCP_USER_SDMA,
370};
371
372/* l4_wkup slave ports */
373static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
374 &omap44xx_l4_cfg__l4_wkup,
375};
376
377static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
378 .name = "l4_wkup",
379 .class = &omap44xx_l4_hwmod_class,
380 .slaves = omap44xx_l4_wkup_slaves,
381 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
382 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
383};
384
385/*
386 * 'mpu_bus' class
387 * instance(s): mpu_private
388 */
389static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
390 .name = "mpu_bus",
391};
392
393/* mpu_private interface data */
394/* mpu -> mpu_private */
395static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
396 .master = &omap44xx_mpu_hwmod,
397 .slave = &omap44xx_mpu_private_hwmod,
398 .clk = "l3_div_ck",
399 .user = OCP_USER_MPU | OCP_USER_SDMA,
400};
401
402/* mpu_private slave ports */
403static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
404 &omap44xx_mpu__mpu_private,
405};
406
407static struct omap_hwmod omap44xx_mpu_private_hwmod = {
408 .name = "mpu_private",
409 .class = &omap44xx_mpu_bus_hwmod_class,
410 .slaves = omap44xx_mpu_private_slaves,
411 .slaves_cnt = ARRAY_SIZE(omap44xx_mpu_private_slaves),
412 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
413};
414
415/*
416 * 'mpu' class
417 * mpu sub-system
418 */
419
420static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
421 .name = "mpu",
422};
423
424/* mpu */
425static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
426 { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
427 { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
428 { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
429};
430
431/* mpu master ports */
432static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
433 &omap44xx_mpu__l3_main_1,
434 &omap44xx_mpu__l4_abe,
435 &omap44xx_mpu__dmm,
436};
437
438static struct omap_hwmod omap44xx_mpu_hwmod = {
439 .name = "mpu",
440 .class = &omap44xx_mpu_hwmod_class,
441 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
442 .mpu_irqs = omap44xx_mpu_irqs,
443 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mpu_irqs),
444 .main_clk = "dpll_mpu_m2_ck",
445 .prcm = {
446 .omap4 = {
447 .clkctrl_reg = OMAP4430_CM_MPU_MPU_CLKCTRL,
448 },
449 },
450 .masters = omap44xx_mpu_masters,
451 .masters_cnt = ARRAY_SIZE(omap44xx_mpu_masters),
452 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
453};
454
455static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
456 /* dmm class */
457 &omap44xx_dmm_hwmod,
458 /* emif_fw class */
459 &omap44xx_emif_fw_hwmod,
460 /* l3 class */
461 &omap44xx_l3_instr_hwmod,
462 &omap44xx_l3_main_1_hwmod,
463 &omap44xx_l3_main_2_hwmod,
464 &omap44xx_l3_main_3_hwmod,
465 /* l4 class */
466 &omap44xx_l4_abe_hwmod,
467 &omap44xx_l4_cfg_hwmod,
468 &omap44xx_l4_per_hwmod,
469 &omap44xx_l4_wkup_hwmod,
470 /* mpu_bus class */
471 &omap44xx_mpu_private_hwmod,
472
473 /* mpu class */
474 &omap44xx_mpu_hwmod,
475 NULL,
476};
477
478int __init omap44xx_hwmod_init(void)
479{
480 return omap_hwmod_init(omap44xx_hwmods);
481}
482
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index 723b44e252fd..af00c174d7a9 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -31,12 +31,17 @@
31#include <plat/board.h> 31#include <plat/board.h>
32#include <plat/powerdomain.h> 32#include <plat/powerdomain.h>
33#include <plat/clockdomain.h> 33#include <plat/clockdomain.h>
34#include <plat/dmtimer.h>
34 35
35#include "prm.h" 36#include "prm.h"
36#include "cm.h" 37#include "cm.h"
37#include "pm.h" 38#include "pm.h"
38 39
39int omap2_pm_debug; 40int omap2_pm_debug;
41u32 enable_off_mode;
42u32 sleep_while_idle;
43u32 wakeup_timer_seconds;
44u32 wakeup_timer_milliseconds;
40 45
41#define DUMP_PRM_MOD_REG(mod, reg) \ 46#define DUMP_PRM_MOD_REG(mod, reg) \
42 regs[reg_count].name = #mod "." #reg; \ 47 regs[reg_count].name = #mod "." #reg; \
@@ -349,6 +354,23 @@ void pm_dbg_update_time(struct powerdomain *pwrdm, int prev)
349 pwrdm->timer = t; 354 pwrdm->timer = t;
350} 355}
351 356
357void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds)
358{
359 u32 tick_rate, cycles;
360
361 if (!seconds && !milliseconds)
362 return;
363
364 tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup));
365 cycles = tick_rate * seconds + tick_rate * milliseconds / 1000;
366 omap_dm_timer_stop(gptimer_wakeup);
367 omap_dm_timer_set_load_start(gptimer_wakeup, 0, 0xffffffff - cycles);
368
369 pr_info("PM: Resume timer in %u.%03u secs"
370 " (%d ticks at %d ticks/sec.)\n",
371 seconds, milliseconds, cycles, tick_rate);
372}
373
352static int clkdm_dbg_show_counter(struct clockdomain *clkdm, void *user) 374static int clkdm_dbg_show_counter(struct clockdomain *clkdm, void *user)
353{ 375{
354 struct seq_file *s = (struct seq_file *)user; 376 struct seq_file *s = (struct seq_file *)user;
@@ -494,8 +516,10 @@ int pm_dbg_regset_init(int reg_set)
494 516
495static int pwrdm_suspend_get(void *data, u64 *val) 517static int pwrdm_suspend_get(void *data, u64 *val)
496{ 518{
497 int ret; 519 int ret = -EINVAL;
498 ret = omap3_pm_get_suspend_state((struct powerdomain *)data); 520
521 if (cpu_is_omap34xx())
522 ret = omap3_pm_get_suspend_state((struct powerdomain *)data);
499 *val = ret; 523 *val = ret;
500 524
501 if (ret >= 0) 525 if (ret >= 0)
@@ -505,7 +529,10 @@ static int pwrdm_suspend_get(void *data, u64 *val)
505 529
506static int pwrdm_suspend_set(void *data, u64 val) 530static int pwrdm_suspend_set(void *data, u64 val)
507{ 531{
508 return omap3_pm_set_suspend_state((struct powerdomain *)data, (int)val); 532 if (cpu_is_omap34xx())
533 return omap3_pm_set_suspend_state(
534 (struct powerdomain *)data, (int)val);
535 return -EINVAL;
509} 536}
510 537
511DEFINE_SIMPLE_ATTRIBUTE(pwrdm_suspend_fops, pwrdm_suspend_get, 538DEFINE_SIMPLE_ATTRIBUTE(pwrdm_suspend_fops, pwrdm_suspend_get,
@@ -553,8 +580,10 @@ static int option_set(void *data, u64 val)
553 580
554 *option = val; 581 *option = val;
555 582
556 if (option == &enable_off_mode) 583 if (option == &enable_off_mode) {
557 omap3_pm_off_mode_enable(val); 584 if (cpu_is_omap34xx())
585 omap3_pm_off_mode_enable(val);
586 }
558 587
559 return 0; 588 return 0;
560} 589}
@@ -609,6 +638,9 @@ static int __init pm_dbg_init(void)
609 &sleep_while_idle, &pm_dbg_option_fops); 638 &sleep_while_idle, &pm_dbg_option_fops);
610 (void) debugfs_create_file("wakeup_timer_seconds", S_IRUGO | S_IWUGO, d, 639 (void) debugfs_create_file("wakeup_timer_seconds", S_IRUGO | S_IWUGO, d,
611 &wakeup_timer_seconds, &pm_dbg_option_fops); 640 &wakeup_timer_seconds, &pm_dbg_option_fops);
641 (void) debugfs_create_file("wakeup_timer_milliseconds",
642 S_IRUGO | S_IWUGO, d, &wakeup_timer_milliseconds,
643 &pm_dbg_option_fops);
612 pm_dbg_init_done = 1; 644 pm_dbg_init_done = 1;
613 645
614 return 0; 646 return 0;
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 68f9f2e95891..59ca03b0e691 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -18,11 +18,15 @@
18#include <plat/omap_device.h> 18#include <plat/omap_device.h>
19#include <plat/common.h> 19#include <plat/common.h>
20 20
21#include <plat/powerdomain.h>
22#include <plat/clockdomain.h>
23
21static struct omap_device_pm_latency *pm_lats; 24static struct omap_device_pm_latency *pm_lats;
22 25
23static struct device *mpu_dev; 26static struct device *mpu_dev;
24static struct device *dsp_dev; 27static struct device *iva_dev;
25static struct device *l3_dev; 28static struct device *l3_dev;
29static struct device *dsp_dev;
26 30
27struct device *omap2_get_mpuss_device(void) 31struct device *omap2_get_mpuss_device(void)
28{ 32{
@@ -30,10 +34,10 @@ struct device *omap2_get_mpuss_device(void)
30 return mpu_dev; 34 return mpu_dev;
31} 35}
32 36
33struct device *omap2_get_dsp_device(void) 37struct device *omap2_get_iva_device(void)
34{ 38{
35 WARN_ON_ONCE(!dsp_dev); 39 WARN_ON_ONCE(!iva_dev);
36 return dsp_dev; 40 return iva_dev;
37} 41}
38 42
39struct device *omap2_get_l3_device(void) 43struct device *omap2_get_l3_device(void)
@@ -42,6 +46,13 @@ struct device *omap2_get_l3_device(void)
42 return l3_dev; 46 return l3_dev;
43} 47}
44 48
49struct device *omap4_get_dsp_device(void)
50{
51 WARN_ON_ONCE(!dsp_dev);
52 return dsp_dev;
53}
54EXPORT_SYMBOL(omap4_get_dsp_device);
55
45/* static int _init_omap_device(struct omap_hwmod *oh, void *user) */ 56/* static int _init_omap_device(struct omap_hwmod *oh, void *user) */
46static int _init_omap_device(char *name, struct device **new_dev) 57static int _init_omap_device(char *name, struct device **new_dev)
47{ 58{
@@ -69,8 +80,60 @@ static int _init_omap_device(char *name, struct device **new_dev)
69static void omap2_init_processor_devices(void) 80static void omap2_init_processor_devices(void)
70{ 81{
71 _init_omap_device("mpu", &mpu_dev); 82 _init_omap_device("mpu", &mpu_dev);
72 _init_omap_device("iva", &dsp_dev); 83 _init_omap_device("iva", &iva_dev);
73 _init_omap_device("l3_main", &l3_dev); 84 if (cpu_is_omap44xx()) {
85 _init_omap_device("l3_main_1", &l3_dev);
86 _init_omap_device("dsp", &dsp_dev);
87 } else {
88 _init_omap_device("l3_main", &l3_dev);
89 }
90}
91
92/*
93 * This sets pwrdm state (other than mpu & core. Currently only ON &
94 * RET are supported. Function is assuming that clkdm doesn't have
95 * hw_sup mode enabled.
96 */
97int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
98{
99 u32 cur_state;
100 int sleep_switch = 0;
101 int ret = 0;
102
103 if (pwrdm == NULL || IS_ERR(pwrdm))
104 return -EINVAL;
105
106 while (!(pwrdm->pwrsts & (1 << state))) {
107 if (state == PWRDM_POWER_OFF)
108 return ret;
109 state--;
110 }
111
112 cur_state = pwrdm_read_next_pwrst(pwrdm);
113 if (cur_state == state)
114 return ret;
115
116 if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) {
117 omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
118 sleep_switch = 1;
119 pwrdm_wait_transition(pwrdm);
120 }
121
122 ret = pwrdm_set_next_pwrst(pwrdm, state);
123 if (ret) {
124 printk(KERN_ERR "Unable to set state of powerdomain: %s\n",
125 pwrdm->name);
126 goto err;
127 }
128
129 if (sleep_switch) {
130 omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
131 pwrdm_wait_transition(pwrdm);
132 pwrdm_state_switch(pwrdm);
133 }
134
135err:
136 return ret;
74} 137}
75 138
76static int __init omap2_common_pm_init(void) 139static int __init omap2_common_pm_init(void)
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 3de6ece23fc8..77770a13cea8 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -20,7 +20,7 @@ extern void *omap3_secure_ram_storage;
20extern void omap3_pm_off_mode_enable(int); 20extern void omap3_pm_off_mode_enable(int);
21extern void omap_sram_idle(void); 21extern void omap_sram_idle(void);
22extern int omap3_can_sleep(void); 22extern int omap3_can_sleep(void);
23extern int set_pwrdm_state(struct powerdomain *pwrdm, u32 state); 23extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
24extern int omap3_idle_init(void); 24extern int omap3_idle_init(void);
25 25
26struct cpuidle_params { 26struct cpuidle_params {
@@ -48,9 +48,11 @@ extern struct omap_dm_timer *gptimer_wakeup;
48 48
49#ifdef CONFIG_PM_DEBUG 49#ifdef CONFIG_PM_DEBUG
50extern void omap2_pm_dump(int mode, int resume, unsigned int us); 50extern void omap2_pm_dump(int mode, int resume, unsigned int us);
51extern void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds);
51extern int omap2_pm_debug; 52extern int omap2_pm_debug;
52#else 53#else
53#define omap2_pm_dump(mode, resume, us) do {} while (0); 54#define omap2_pm_dump(mode, resume, us) do {} while (0);
55#define omap2_pm_wakeup_on_timer(seconds, milliseconds) do {} while (0);
54#define omap2_pm_debug 0 56#define omap2_pm_debug 0
55#endif 57#endif
56 58
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 7b03426c72a3..d2b940c7215d 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -38,7 +38,6 @@
38#include <plat/prcm.h> 38#include <plat/prcm.h>
39#include <plat/gpmc.h> 39#include <plat/gpmc.h>
40#include <plat/dma.h> 40#include <plat/dma.h>
41#include <plat/dmtimer.h>
42 41
43#include <asm/tlbflush.h> 42#include <asm/tlbflush.h>
44 43
@@ -55,11 +54,6 @@
55#define OMAP343X_TABLE_VALUE_OFFSET 0x30 54#define OMAP343X_TABLE_VALUE_OFFSET 0x30
56#define OMAP343X_CONTROL_REG_VALUE_OFFSET 0x32 55#define OMAP343X_CONTROL_REG_VALUE_OFFSET 0x32
57 56
58u32 enable_off_mode;
59u32 sleep_while_idle;
60u32 wakeup_timer_seconds;
61u32 wakeup_timer_milliseconds;
62
63struct power_state { 57struct power_state {
64 struct powerdomain *pwrdm; 58 struct powerdomain *pwrdm;
65 u32 next_state; 59 u32 next_state;
@@ -351,7 +345,6 @@ void omap_sram_idle(void)
351 int core_next_state = PWRDM_POWER_ON; 345 int core_next_state = PWRDM_POWER_ON;
352 int core_prev_state, per_prev_state; 346 int core_prev_state, per_prev_state;
353 u32 sdrc_pwr = 0; 347 u32 sdrc_pwr = 0;
354 int per_state_modified = 0;
355 348
356 if (!_omap_sram_idle) 349 if (!_omap_sram_idle)
357 return; 350 return;
@@ -385,9 +378,9 @@ void omap_sram_idle(void)
385 /* Enable IO-PAD and IO-CHAIN wakeups */ 378 /* Enable IO-PAD and IO-CHAIN wakeups */
386 per_next_state = pwrdm_read_next_pwrst(per_pwrdm); 379 per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
387 core_next_state = pwrdm_read_next_pwrst(core_pwrdm); 380 core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
388 if (omap3_has_io_wakeup() && \ 381 if (omap3_has_io_wakeup() &&
389 (per_next_state < PWRDM_POWER_ON || 382 (per_next_state < PWRDM_POWER_ON ||
390 core_next_state < PWRDM_POWER_ON)) { 383 core_next_state < PWRDM_POWER_ON)) {
391 prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN); 384 prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
392 omap3_enable_io_chain(); 385 omap3_enable_io_chain();
393 } 386 }
@@ -396,19 +389,10 @@ void omap_sram_idle(void)
396 if (per_next_state < PWRDM_POWER_ON) { 389 if (per_next_state < PWRDM_POWER_ON) {
397 omap_uart_prepare_idle(2); 390 omap_uart_prepare_idle(2);
398 omap2_gpio_prepare_for_idle(per_next_state); 391 omap2_gpio_prepare_for_idle(per_next_state);
399 if (per_next_state == PWRDM_POWER_OFF) { 392 if (per_next_state == PWRDM_POWER_OFF)
400 if (core_next_state == PWRDM_POWER_ON) {
401 per_next_state = PWRDM_POWER_RET;
402 pwrdm_set_next_pwrst(per_pwrdm, per_next_state);
403 per_state_modified = 1;
404 } else
405 omap3_per_save_context(); 393 omap3_per_save_context();
406 }
407 } 394 }
408 395
409 if (pwrdm_read_pwrst(cam_pwrdm) == PWRDM_POWER_ON)
410 omap2_clkdm_deny_idle(mpu_pwrdm->pwrdm_clkdms[0]);
411
412 /* CORE */ 396 /* CORE */
413 if (core_next_state < PWRDM_POWER_ON) { 397 if (core_next_state < PWRDM_POWER_ON) {
414 omap_uart_prepare_idle(0); 398 omap_uart_prepare_idle(0);
@@ -475,8 +459,6 @@ void omap_sram_idle(void)
475 if (per_prev_state == PWRDM_POWER_OFF) 459 if (per_prev_state == PWRDM_POWER_OFF)
476 omap3_per_restore_context(); 460 omap3_per_restore_context();
477 omap_uart_resume_idle(2); 461 omap_uart_resume_idle(2);
478 if (per_state_modified)
479 pwrdm_set_next_pwrst(per_pwrdm, PWRDM_POWER_OFF);
480 } 462 }
481 463
482 /* Disable IO-PAD and IO-CHAIN wakeup */ 464 /* Disable IO-PAD and IO-CHAIN wakeup */
@@ -501,51 +483,6 @@ int omap3_can_sleep(void)
501 return 1; 483 return 1;
502} 484}
503 485
504/* This sets pwrdm state (other than mpu & core. Currently only ON &
505 * RET are supported. Function is assuming that clkdm doesn't have
506 * hw_sup mode enabled. */
507int set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
508{
509 u32 cur_state;
510 int sleep_switch = 0;
511 int ret = 0;
512
513 if (pwrdm == NULL || IS_ERR(pwrdm))
514 return -EINVAL;
515
516 while (!(pwrdm->pwrsts & (1 << state))) {
517 if (state == PWRDM_POWER_OFF)
518 return ret;
519 state--;
520 }
521
522 cur_state = pwrdm_read_next_pwrst(pwrdm);
523 if (cur_state == state)
524 return ret;
525
526 if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) {
527 omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
528 sleep_switch = 1;
529 pwrdm_wait_transition(pwrdm);
530 }
531
532 ret = pwrdm_set_next_pwrst(pwrdm, state);
533 if (ret) {
534 printk(KERN_ERR "Unable to set state of powerdomain: %s\n",
535 pwrdm->name);
536 goto err;
537 }
538
539 if (sleep_switch) {
540 omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
541 pwrdm_wait_transition(pwrdm);
542 pwrdm_state_switch(pwrdm);
543 }
544
545err:
546 return ret;
547}
548
549static void omap3_pm_idle(void) 486static void omap3_pm_idle(void)
550{ 487{
551 local_irq_disable(); 488 local_irq_disable();
@@ -567,23 +504,6 @@ out:
567#ifdef CONFIG_SUSPEND 504#ifdef CONFIG_SUSPEND
568static suspend_state_t suspend_state; 505static suspend_state_t suspend_state;
569 506
570static void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds)
571{
572 u32 tick_rate, cycles;
573
574 if (!seconds && !milliseconds)
575 return;
576
577 tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup));
578 cycles = tick_rate * seconds + tick_rate * milliseconds / 1000;
579 omap_dm_timer_stop(gptimer_wakeup);
580 omap_dm_timer_set_load_start(gptimer_wakeup, 0, 0xffffffff - cycles);
581
582 pr_info("PM: Resume timer in %u.%03u secs"
583 " (%d ticks at %d ticks/sec.)\n",
584 seconds, milliseconds, cycles, tick_rate);
585}
586
587static int omap3_pm_prepare(void) 507static int omap3_pm_prepare(void)
588{ 508{
589 disable_hlt(); 509 disable_hlt();
@@ -604,7 +524,7 @@ static int omap3_pm_suspend(void)
604 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm); 524 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
605 /* Set ones wanted by suspend */ 525 /* Set ones wanted by suspend */
606 list_for_each_entry(pwrst, &pwrst_list, node) { 526 list_for_each_entry(pwrst, &pwrst_list, node) {
607 if (set_pwrdm_state(pwrst->pwrdm, pwrst->next_state)) 527 if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
608 goto restore; 528 goto restore;
609 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm)) 529 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
610 goto restore; 530 goto restore;
@@ -625,7 +545,7 @@ restore:
625 pwrst->pwrdm->name, pwrst->next_state); 545 pwrst->pwrdm->name, pwrst->next_state);
626 ret = -1; 546 ret = -1;
627 } 547 }
628 set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); 548 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
629 } 549 }
630 if (ret) 550 if (ret)
631 printk(KERN_ERR "Could not enter target state in pm_suspend\n"); 551 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
@@ -974,7 +894,7 @@ void omap3_pm_off_mode_enable(int enable)
974 894
975 list_for_each_entry(pwrst, &pwrst_list, node) { 895 list_for_each_entry(pwrst, &pwrst_list, node) {
976 pwrst->next_state = state; 896 pwrst->next_state = state;
977 set_pwrdm_state(pwrst->pwrdm, state); 897 omap_set_pwrdm_state(pwrst->pwrdm, state);
978 } 898 }
979} 899}
980 900
@@ -1019,7 +939,7 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
1019 if (pwrdm_has_hdwr_sar(pwrdm)) 939 if (pwrdm_has_hdwr_sar(pwrdm))
1020 pwrdm_enable_hdwr_sar(pwrdm); 940 pwrdm_enable_hdwr_sar(pwrdm);
1021 941
1022 return set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); 942 return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
1023} 943}
1024 944
1025/* 945/*
@@ -1029,9 +949,6 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
1029 */ 949 */
1030static int __init clkdms_setup(struct clockdomain *clkdm, void *unused) 950static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
1031{ 951{
1032 clkdm_clear_all_wkdeps(clkdm);
1033 clkdm_clear_all_sleepdeps(clkdm);
1034
1035 if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO) 952 if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
1036 omap2_clkdm_allow_idle(clkdm); 953 omap2_clkdm_allow_idle(clkdm);
1037 else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && 954 else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
diff --git a/arch/arm/mach-omap2/pm_bus.c b/arch/arm/mach-omap2/pm_bus.c
new file mode 100644
index 000000000000..784989f8f2f5
--- /dev/null
+++ b/arch/arm/mach-omap2/pm_bus.c
@@ -0,0 +1,85 @@
1/*
2 * Runtime PM support code for OMAP
3 *
4 * Author: Kevin Hilman, Deep Root Systems, LLC
5 *
6 * Copyright (C) 2010 Texas Instruments, Inc.
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12#include <linux/init.h>
13#include <linux/kernel.h>
14#include <linux/io.h>
15#include <linux/pm_runtime.h>
16#include <linux/platform_device.h>
17#include <linux/mutex.h>
18
19#include <plat/omap_device.h>
20#include <plat/omap-pm.h>
21
22#ifdef CONFIG_PM_RUNTIME
23int omap_pm_runtime_suspend(struct device *dev)
24{
25 struct platform_device *pdev = to_platform_device(dev);
26 int r, ret = 0;
27
28 dev_dbg(dev, "%s\n", __func__);
29
30 ret = pm_generic_runtime_suspend(dev);
31
32 if (!ret && dev->parent == &omap_device_parent) {
33 r = omap_device_idle(pdev);
34 WARN_ON(r);
35 }
36
37 return ret;
38};
39
40int omap_pm_runtime_resume(struct device *dev)
41{
42 struct platform_device *pdev = to_platform_device(dev);
43 int r;
44
45 dev_dbg(dev, "%s\n", __func__);
46
47 if (dev->parent == &omap_device_parent) {
48 r = omap_device_enable(pdev);
49 WARN_ON(r);
50 }
51
52 return pm_generic_runtime_resume(dev);
53};
54#else
55#define omap_pm_runtime_suspend NULL
56#define omap_pm_runtime_resume NULL
57#endif /* CONFIG_PM_RUNTIME */
58
59static int __init omap_pm_runtime_init(void)
60{
61 const struct dev_pm_ops *pm;
62 struct dev_pm_ops *omap_pm;
63
64 pm = platform_bus_get_pm_ops();
65 if (!pm) {
66 pr_err("%s: unable to get dev_pm_ops from platform_bus\n",
67 __func__);
68 return -ENODEV;
69 }
70
71 omap_pm = kmemdup(pm, sizeof(struct dev_pm_ops), GFP_KERNEL);
72 if (!omap_pm) {
73 pr_err("%s: unable to alloc memory for new dev_pm_ops\n",
74 __func__);
75 return -ENOMEM;
76 }
77
78 omap_pm->runtime_suspend = omap_pm_runtime_suspend;
79 omap_pm->runtime_resume = omap_pm_runtime_resume;
80
81 platform_bus_set_pm_ops(omap_pm);
82
83 return 0;
84}
85core_initcall(omap_pm_runtime_init);
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index c20137497c92..d4388d34c26a 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -33,6 +33,7 @@
33#include "cm.h" 33#include "cm.h"
34#include "prm.h" 34#include "prm.h"
35#include "prm-regbits-24xx.h" 35#include "prm-regbits-24xx.h"
36#include "prm-regbits-44xx.h"
36 37
37static void __iomem *prm_base; 38static void __iomem *prm_base;
38static void __iomem *cm_base; 39static void __iomem *cm_base;
@@ -161,8 +162,8 @@ void omap_prcm_arch_reset(char mode, const char *cmd)
161 prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs, 162 prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs,
162 OMAP2_RM_RSTCTRL); 163 OMAP2_RM_RSTCTRL);
163 if (cpu_is_omap44xx()) 164 if (cpu_is_omap44xx())
164 prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs, 165 prm_set_mod_reg_bits(OMAP4430_RST_GLOBAL_WARM_SW_MASK,
165 OMAP4_RM_RSTCTRL); 166 prcm_offs, OMAP4_RM_RSTCTRL);
166} 167}
167 168
168static inline u32 __omap_prcm_read(void __iomem *base, s16 module, u16 reg) 169static inline u32 __omap_prcm_read(void __iomem *base, s16 module, u16 reg)
@@ -215,6 +216,30 @@ u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
215 return v; 216 return v;
216} 217}
217 218
219/* Read a PRM register, AND it, and shift the result down to bit 0 */
220u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask)
221{
222 u32 v;
223
224 v = __raw_readl(reg);
225 v &= mask;
226 v >>= __ffs(mask);
227
228 return v;
229}
230
231/* Read-modify-write a register in a PRM module. Caller must lock */
232u32 omap4_prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *reg)
233{
234 u32 v;
235
236 v = __raw_readl(reg);
237 v &= ~mask;
238 v |= bits;
239 __raw_writel(v, reg);
240
241 return v;
242}
218/* Read a register in a CM module */ 243/* Read a register in a CM module */
219u32 cm_read_mod_reg(s16 module, u16 idx) 244u32 cm_read_mod_reg(s16 module, u16 idx)
220{ 245{
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index 588873b9303a..7be040b2fdab 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -5,7 +5,7 @@
5 * OMAP2/3 Power/Reset Management (PRM) register definitions 5 * OMAP2/3 Power/Reset Management (PRM) register definitions
6 * 6 *
7 * Copyright (C) 2007-2009 Texas Instruments, Inc. 7 * Copyright (C) 2007-2009 Texas Instruments, Inc.
8 * Copyright (C) 2009 Nokia Corporation 8 * Copyright (C) 2010 Nokia Corporation
9 * 9 *
10 * Written by Paul Walmsley 10 * Written by Paul Walmsley
11 * 11 *
@@ -246,6 +246,15 @@ static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
246 return prm_rmw_mod_reg_bits(bits, 0x0, module, idx); 246 return prm_rmw_mod_reg_bits(bits, 0x0, module, idx);
247} 247}
248 248
249/* These omap2_ PRM functions apply to both OMAP2 and 3 */
250int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift);
251int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift);
252int omap2_prm_deassert_hardreset(s16 prm_mod, u8 shift);
253
254int omap4_prm_is_hardreset_asserted(void __iomem *rstctrl_reg, u8 shift);
255int omap4_prm_assert_hardreset(void __iomem *rstctrl_reg, u8 shift);
256int omap4_prm_deassert_hardreset(void __iomem *rstctrl_reg, u8 shift);
257
249#endif 258#endif
250 259
251/* 260/*
@@ -398,4 +407,11 @@ static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
398#define OMAP_POWERSTATE_MASK (0x3 << 0) 407#define OMAP_POWERSTATE_MASK (0x3 << 0)
399 408
400 409
410/*
411 * MAX_MODULE_HARDRESET_WAIT: Maximum microseconds to wait for an OMAP
412 * submodule to exit hardreset
413 */
414#define MAX_MODULE_HARDRESET_WAIT 10000
415
416
401#endif 417#endif
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c
new file mode 100644
index 000000000000..421771eee450
--- /dev/null
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c
@@ -0,0 +1,110 @@
1/*
2 * OMAP2/3 PRM module functions
3 *
4 * Copyright (C) 2010 Texas Instruments, Inc.
5 * Copyright (C) 2010 Nokia Corporation
6 * Benoît Cousson
7 * Paul Walmsley
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/kernel.h>
15#include <linux/delay.h>
16#include <linux/errno.h>
17#include <linux/err.h>
18
19#include <plat/common.h>
20#include <plat/cpu.h>
21#include <plat/prcm.h>
22
23#include "prm.h"
24#include "prm-regbits-24xx.h"
25#include "prm-regbits-34xx.h"
26
27/**
28 * omap2_prm_is_hardreset_asserted - read the HW reset line state of
29 * submodules contained in the hwmod module
30 * @prm_mod: PRM submodule base (e.g. CORE_MOD)
31 * @shift: register bit shift corresponding to the reset line to check
32 *
33 * Returns 1 if the (sub)module hardreset line is currently asserted,
34 * 0 if the (sub)module hardreset line is not currently asserted, or
35 * -EINVAL if called while running on a non-OMAP2/3 chip.
36 */
37int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift)
38{
39 if (!(cpu_is_omap24xx() || cpu_is_omap34xx()))
40 return -EINVAL;
41
42 return prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL,
43 (1 << shift));
44}
45
46/**
47 * omap2_prm_assert_hardreset - assert the HW reset line of a submodule
48 * @prm_mod: PRM submodule base (e.g. CORE_MOD)
49 * @shift: register bit shift corresponding to the reset line to assert
50 *
51 * Some IPs like dsp or iva contain processors that require an HW
52 * reset line to be asserted / deasserted in order to fully enable the
53 * IP. These modules may have multiple hard-reset lines that reset
54 * different 'submodules' inside the IP block. This function will
55 * place the submodule into reset. Returns 0 upon success or -EINVAL
56 * upon an argument error.
57 */
58int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift)
59{
60 u32 mask;
61
62 if (!(cpu_is_omap24xx() || cpu_is_omap34xx()))
63 return -EINVAL;
64
65 mask = 1 << shift;
66 prm_rmw_mod_reg_bits(mask, mask, prm_mod, OMAP2_RM_RSTCTRL);
67
68 return 0;
69}
70
71/**
72 * omap2_prm_deassert_hardreset - deassert a submodule hardreset line and wait
73 * @prm_mod: PRM submodule base (e.g. CORE_MOD)
74 * @shift: register bit shift corresponding to the reset line to deassert
75 *
76 * Some IPs like dsp or iva contain processors that require an HW
77 * reset line to be asserted / deasserted in order to fully enable the
78 * IP. These modules may have multiple hard-reset lines that reset
79 * different 'submodules' inside the IP block. This function will
80 * take the submodule out of reset and wait until the PRCM indicates
81 * that the reset has completed before returning. Returns 0 upon success or
82 * -EINVAL upon an argument error, -EEXIST if the submodule was already out
83 * of reset, or -EBUSY if the submodule did not exit reset promptly.
84 */
85int omap2_prm_deassert_hardreset(s16 prm_mod, u8 shift)
86{
87 u32 mask;
88 int c;
89
90 if (!(cpu_is_omap24xx() || cpu_is_omap34xx()))
91 return -EINVAL;
92
93 mask = 1 << shift;
94
95 /* Check the current status to avoid de-asserting the line twice */
96 if (prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, mask) == 0)
97 return -EEXIST;
98
99 /* Clear the reset status by writing 1 to the status bit */
100 prm_rmw_mod_reg_bits(0xffffffff, mask, prm_mod, OMAP2_RM_RSTST);
101 /* de-assert the reset control line */
102 prm_rmw_mod_reg_bits(mask, 0, prm_mod, OMAP2_RM_RSTCTRL);
103 /* wait the status to be set */
104 omap_test_timeout(prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTST,
105 mask),
106 MAX_MODULE_HARDRESET_WAIT, c);
107
108 return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
109}
110
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
new file mode 100644
index 000000000000..a1ff918d9bed
--- /dev/null
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -0,0 +1,116 @@
1/*
2 * OMAP4 PRM module functions
3 *
4 * Copyright (C) 2010 Texas Instruments, Inc.
5 * Copyright (C) 2010 Nokia Corporation
6 * Benoît Cousson
7 * Paul Walmsley
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/kernel.h>
15#include <linux/delay.h>
16#include <linux/errno.h>
17#include <linux/err.h>
18
19#include <plat/common.h>
20#include <plat/cpu.h>
21#include <plat/prcm.h>
22
23#include "prm.h"
24#include "prm-regbits-44xx.h"
25
26/*
27 * Address offset (in bytes) between the reset control and the reset
28 * status registers: 4 bytes on OMAP4
29 */
30#define OMAP4_RST_CTRL_ST_OFFSET 4
31
32/**
33 * omap4_prm_is_hardreset_asserted - read the HW reset line state of
34 * submodules contained in the hwmod module
35 * @rstctrl_reg: RM_RSTCTRL register address for this module
36 * @shift: register bit shift corresponding to the reset line to check
37 *
38 * Returns 1 if the (sub)module hardreset line is currently asserted,
39 * 0 if the (sub)module hardreset line is not currently asserted, or
40 * -EINVAL upon parameter error.
41 */
42int omap4_prm_is_hardreset_asserted(void __iomem *rstctrl_reg, u8 shift)
43{
44 if (!cpu_is_omap44xx() || !rstctrl_reg)
45 return -EINVAL;
46
47 return omap4_prm_read_bits_shift(rstctrl_reg, (1 << shift));
48}
49
50/**
51 * omap4_prm_assert_hardreset - assert the HW reset line of a submodule
52 * @rstctrl_reg: RM_RSTCTRL register address for this module
53 * @shift: register bit shift corresponding to the reset line to assert
54 *
55 * Some IPs like dsp, ipu or iva contain processors that require an HW
56 * reset line to be asserted / deasserted in order to fully enable the
57 * IP. These modules may have multiple hard-reset lines that reset
58 * different 'submodules' inside the IP block. This function will
59 * place the submodule into reset. Returns 0 upon success or -EINVAL
60 * upon an argument error.
61 */
62int omap4_prm_assert_hardreset(void __iomem *rstctrl_reg, u8 shift)
63{
64 u32 mask;
65
66 if (!cpu_is_omap44xx() || !rstctrl_reg)
67 return -EINVAL;
68
69 mask = 1 << shift;
70 omap4_prm_rmw_reg_bits(mask, mask, rstctrl_reg);
71
72 return 0;
73}
74
75/**
76 * omap4_prm_deassert_hardreset - deassert a submodule hardreset line and wait
77 * @rstctrl_reg: RM_RSTCTRL register address for this module
78 * @shift: register bit shift corresponding to the reset line to deassert
79 *
80 * Some IPs like dsp, ipu or iva contain processors that require an HW
81 * reset line to be asserted / deasserted in order to fully enable the
82 * IP. These modules may have multiple hard-reset lines that reset
83 * different 'submodules' inside the IP block. This function will
84 * take the submodule out of reset and wait until the PRCM indicates
85 * that the reset has completed before returning. Returns 0 upon success or
86 * -EINVAL upon an argument error, -EEXIST if the submodule was already out
87 * of reset, or -EBUSY if the submodule did not exit reset promptly.
88 */
89int omap4_prm_deassert_hardreset(void __iomem *rstctrl_reg, u8 shift)
90{
91 u32 mask;
92 void __iomem *rstst_reg;
93 int c;
94
95 if (!cpu_is_omap44xx() || !rstctrl_reg)
96 return -EINVAL;
97
98 rstst_reg = rstctrl_reg + OMAP4_RST_CTRL_ST_OFFSET;
99
100 mask = 1 << shift;
101
102 /* Check the current status to avoid de-asserting the line twice */
103 if (omap4_prm_read_bits_shift(rstctrl_reg, mask) == 0)
104 return -EEXIST;
105
106 /* Clear the reset status by writing 1 to the status bit */
107 omap4_prm_rmw_reg_bits(0xffffffff, mask, rstst_reg);
108 /* de-assert the reset control line */
109 omap4_prm_rmw_reg_bits(mask, 0, rstctrl_reg);
110 /* wait the status to be set */
111 omap_test_timeout(omap4_prm_read_bits_shift(rstst_reg, mask),
112 MAX_MODULE_HARDRESET_WAIT, c);
113
114 return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
115}
116
diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c
index 74fbed8491f2..5a3e606dc44a 100644
--- a/arch/arm/mach-omap2/timer-gp.c
+++ b/arch/arm/mach-omap2/timer-gp.c
@@ -228,8 +228,10 @@ static void __init omap2_gp_clocksource_init(void)
228static void __init omap2_gp_timer_init(void) 228static void __init omap2_gp_timer_init(void)
229{ 229{
230#ifdef CONFIG_LOCAL_TIMERS 230#ifdef CONFIG_LOCAL_TIMERS
231 twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256); 231 if (cpu_is_omap44xx()) {
232 BUG_ON(!twd_base); 232 twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
233 BUG_ON(!twd_base);
234 }
233#endif 235#endif
234 omap_dm_timer_init(); 236 omap_dm_timer_init();
235 237
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index e39a417a368d..d98c5c0e164b 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -19,7 +19,7 @@ config ARCH_OMAP2PLUS
19 bool "TI OMAP2/3/4" 19 bool "TI OMAP2/3/4"
20 select COMMON_CLKDEV 20 select COMMON_CLKDEV
21 help 21 help
22 "Systems based on omap24xx, omap34xx or omap44xx" 22 "Systems based on OMAP2, OMAP3 or OMAP4"
23 23
24endchoice 24endchoice
25 25
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index 9405831b746a..2a151917ef52 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -31,4 +31,4 @@ obj-y += $(i2c-omap-m) $(i2c-omap-y)
31# OMAP mailbox framework 31# OMAP mailbox framework
32obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox.o 32obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox.o
33 33
34obj-$(CONFIG_OMAP_PM_NOOP) += omap-pm-noop.o \ No newline at end of file 34obj-$(CONFIG_OMAP_PM_NOOP) += omap-pm-noop.o
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 44bafdab2dce..1d706cf63ca0 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -581,7 +581,7 @@ int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
581 * When the functional clock disappears, too quick writes seem 581 * When the functional clock disappears, too quick writes seem
582 * to cause an abort. XXX Is this still necessary? 582 * to cause an abort. XXX Is this still necessary?
583 */ 583 */
584 __delay(150000); 584 __delay(300000);
585 585
586 return ret; 586 return ret;
587} 587}
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 7951eefe1a0e..c05c653d1674 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -2084,9 +2084,10 @@ void omap2_gpio_prepare_for_idle(int power_state)
2084 2084
2085 for (i = min; i < gpio_bank_count; i++) { 2085 for (i = min; i < gpio_bank_count; i++) {
2086 struct gpio_bank *bank = &gpio_bank[i]; 2086 struct gpio_bank *bank = &gpio_bank[i];
2087 u32 l1, l2; 2087 u32 l1 = 0, l2 = 0;
2088 int j;
2088 2089
2089 if (bank->dbck_enable_mask) 2090 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
2090 clk_disable(bank->dbck); 2091 clk_disable(bank->dbck);
2091 2092
2092 if (power_state > PWRDM_POWER_OFF) 2093 if (power_state > PWRDM_POWER_OFF)
@@ -2151,9 +2152,10 @@ void omap2_gpio_resume_after_idle(void)
2151 min = 1; 2152 min = 1;
2152 for (i = min; i < gpio_bank_count; i++) { 2153 for (i = min; i < gpio_bank_count; i++) {
2153 struct gpio_bank *bank = &gpio_bank[i]; 2154 struct gpio_bank *bank = &gpio_bank[i];
2154 u32 l, gen, gen0, gen1; 2155 u32 l = 0, gen, gen0, gen1;
2156 int j;
2155 2157
2156 if (bank->dbck_enable_mask) 2158 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
2157 clk_enable(bank->dbck); 2159 clk_enable(bank->dbck);
2158 2160
2159 if (!workaround_enabled) 2161 if (!workaround_enabled)
diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h
index 7cd01807c1e0..2d8f98d7ae50 100644
--- a/arch/arm/plat-omap/include/plat/common.h
+++ b/arch/arm/plat-omap/include/plat/common.h
@@ -92,7 +92,8 @@ void omap3_map_io(void);
92}) 92})
93 93
94extern struct device *omap2_get_mpuss_device(void); 94extern struct device *omap2_get_mpuss_device(void);
95extern struct device *omap2_get_dsp_device(void); 95extern struct device *omap2_get_iva_device(void);
96extern struct device *omap2_get_l3_device(void); 96extern struct device *omap2_get_l3_device(void);
97extern struct device *omap4_get_dsp_device(void);
97 98
98#endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */ 99#endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index 2e2ae530fced..9b38e4bddf57 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -391,6 +391,7 @@ IS_OMAP_TYPE(3517, 0x3517)
391 391
392#define OMAP443X_CLASS 0x44300044 392#define OMAP443X_CLASS 0x44300044
393#define OMAP4430_REV_ES1_0 0x44300044 393#define OMAP4430_REV_ES1_0 0x44300044
394#define OMAP4430_REV_ES2_0 0x44301044
394 395
395/* 396/*
396 * omap_chip bits 397 * omap_chip bits
@@ -417,10 +418,12 @@ IS_OMAP_TYPE(3517, 0x3517)
417#define CHIP_IS_OMAP4430ES1 (1 << 8) 418#define CHIP_IS_OMAP4430ES1 (1 << 8)
418#define CHIP_IS_OMAP3630ES1_1 (1 << 9) 419#define CHIP_IS_OMAP3630ES1_1 (1 << 9)
419#define CHIP_IS_OMAP3630ES1_2 (1 << 10) 420#define CHIP_IS_OMAP3630ES1_2 (1 << 10)
421#define CHIP_IS_OMAP4430ES2 (1 << 11)
420 422
421#define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430) 423#define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
422 424
423#define CHIP_IS_OMAP4430 (CHIP_IS_OMAP4430ES1) 425#define CHIP_IS_OMAP4430 (CHIP_IS_OMAP4430ES1 | \
426 CHIP_IS_OMAP4430ES2)
424 427
425/* 428/*
426 * "GE" here represents "greater than or equal to" in terms of ES 429 * "GE" here represents "greater than or equal to" in terms of ES
diff --git a/arch/arm/plat-omap/include/plat/i2c.h b/arch/arm/plat-omap/include/plat/i2c.h
index 87f6bf2ea4fa..36a0befd6168 100644
--- a/arch/arm/plat-omap/include/plat/i2c.h
+++ b/arch/arm/plat-omap/include/plat/i2c.h
@@ -18,6 +18,8 @@
18 * 02110-1301 USA 18 * 02110-1301 USA
19 * 19 *
20 */ 20 */
21#ifndef __ASM__ARCH_OMAP_I2C_H
22#define __ASM__ARCH_OMAP_I2C_H
21 23
22#include <linux/i2c.h> 24#include <linux/i2c.h>
23 25
@@ -36,3 +38,5 @@ static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
36 38
37void __init omap1_i2c_mux_pins(int bus_id); 39void __init omap1_i2c_mux_pins(int bus_id);
38void __init omap2_i2c_mux_pins(int bus_id); 40void __init omap2_i2c_mux_pins(int bus_id);
41
42#endif /* __ASM__ARCH_OMAP_I2C_H */
diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h
index 9b89ec601ee2..4f819fc261b7 100644
--- a/arch/arm/plat-omap/include/plat/mmc.h
+++ b/arch/arm/plat-omap/include/plat/mmc.h
@@ -73,10 +73,9 @@ struct omap_mmc_platform_data {
73 73
74 struct omap_mmc_slot_data { 74 struct omap_mmc_slot_data {
75 75
76 /* 4 wire signaling is optional, and is used for SD/SDIO/HSMMC; 76 /* 4/8 wires and any additional host capabilities
77 * 8 wire signaling is also optional, and is used with HSMMC 77 * need to OR'd all capabilities (ref. linux/mmc/host.h) */
78 */ 78 u32 caps;
79 u8 wires;
80 79
81 /* 80 /*
82 * nomux means "standard" muxing is wrong on this board, and 81 * nomux means "standard" muxing is wrong on this board, and
diff --git a/arch/arm/plat-omap/include/plat/omap_device.h b/arch/arm/plat-omap/include/plat/omap_device.h
index 25cd9ac3b095..28e2d1a78433 100644
--- a/arch/arm/plat-omap/include/plat/omap_device.h
+++ b/arch/arm/plat-omap/include/plat/omap_device.h
@@ -36,6 +36,8 @@
36 36
37#include <plat/omap_hwmod.h> 37#include <plat/omap_hwmod.h>
38 38
39extern struct device omap_device_parent;
40
39/* omap_device._state values */ 41/* omap_device._state values */
40#define OMAP_DEVICE_STATE_UNKNOWN 0 42#define OMAP_DEVICE_STATE_UNKNOWN 0
41#define OMAP_DEVICE_STATE_ENABLED 1 43#define OMAP_DEVICE_STATE_ENABLED 1
@@ -62,7 +64,6 @@
62 * 64 *
63 */ 65 */
64struct omap_device { 66struct omap_device {
65 u32 magic;
66 struct platform_device pdev; 67 struct platform_device pdev;
67 struct omap_hwmod **hwmods; 68 struct omap_hwmod **hwmods;
68 struct omap_device_pm_latency *pm_lats; 69 struct omap_device_pm_latency *pm_lats;
@@ -82,7 +83,6 @@ int omap_device_shutdown(struct platform_device *pdev);
82 83
83/* Core code interface */ 84/* Core code interface */
84 85
85bool omap_device_is_valid(struct omap_device *od);
86int omap_device_count_resources(struct omap_device *od); 86int omap_device_count_resources(struct omap_device *od);
87int omap_device_fill_resources(struct omap_device *od, struct resource *res); 87int omap_device_fill_resources(struct omap_device *od, struct resource *res);
88 88
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index a4e508dfaba2..c1835afc238d 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -14,19 +14,16 @@
14 * 14 *
15 * These headers and macros are used to define OMAP on-chip module 15 * These headers and macros are used to define OMAP on-chip module
16 * data and their integration with other OMAP modules and Linux. 16 * data and their integration with other OMAP modules and Linux.
17 * 17 * Copious documentation and references can also be found in the
18 * References: 18 * omap_hwmod code, in arch/arm/mach-omap2/omap_hwmod.c (as of this
19 * - OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 (SWPU064) 19 * writing).
20 * - OMAP2430 Multimedia Device POP Silicon Revision 2.1 (SWPU090)
21 * - OMAP34xx Multimedia Device Silicon Revision 3.1 (SWPU108)
22 * - OMAP4430 Multimedia Device Silicon Revision 1.0 (SWPU140)
23 * - Open Core Protocol Specification 2.2
24 * 20 *
25 * To do: 21 * To do:
26 * - add interconnect error log structures 22 * - add interconnect error log structures
27 * - add pinmuxing 23 * - add pinmuxing
28 * - init_conn_id_bit (CONNID_BIT_VECTOR) 24 * - init_conn_id_bit (CONNID_BIT_VECTOR)
29 * - implement default hwmod SMS/SDRC flags? 25 * - implement default hwmod SMS/SDRC flags?
26 * - remove unused fields
30 * 27 *
31 */ 28 */
32#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H 29#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H
@@ -35,6 +32,7 @@
35#include <linux/kernel.h> 32#include <linux/kernel.h>
36#include <linux/list.h> 33#include <linux/list.h>
37#include <linux/ioport.h> 34#include <linux/ioport.h>
35#include <linux/mutex.h>
38#include <plat/cpu.h> 36#include <plat/cpu.h>
39 37
40struct omap_device; 38struct omap_device;
@@ -96,7 +94,7 @@ struct omap_hwmod_irq_info {
96/** 94/**
97 * struct omap_hwmod_dma_info - DMA channels used by the hwmod 95 * struct omap_hwmod_dma_info - DMA channels used by the hwmod
98 * @name: name of the DMA channel (module local name) 96 * @name: name of the DMA channel (module local name)
99 * @dma_ch: DMA channel ID 97 * @dma_req: DMA request ID
100 * 98 *
101 * @name should be something short, e.g., "tx" or "rx". It is for use 99 * @name should be something short, e.g., "tx" or "rx". It is for use
102 * by platform_get_resource_byname(). It is defined locally to the 100 * by platform_get_resource_byname(). It is defined locally to the
@@ -104,7 +102,20 @@ struct omap_hwmod_irq_info {
104 */ 102 */
105struct omap_hwmod_dma_info { 103struct omap_hwmod_dma_info {
106 const char *name; 104 const char *name;
107 u16 dma_ch; 105 u16 dma_req;
106};
107
108/**
109 * struct omap_hwmod_rst_info - IPs reset lines use by hwmod
110 * @name: name of the reset line (module local name)
111 * @rst_shift: Offset of the reset bit
112 *
113 * @name should be something short, e.g., "cpu0" or "rst". It is defined
114 * locally to the hwmod.
115 */
116struct omap_hwmod_rst_info {
117 const char *name;
118 u8 rst_shift;
108}; 119};
109 120
110/** 121/**
@@ -237,8 +248,9 @@ struct omap_hwmod_ocp_if {
237#define SYSC_HAS_CLOCKACTIVITY (1 << 4) 248#define SYSC_HAS_CLOCKACTIVITY (1 << 4)
238#define SYSC_HAS_SIDLEMODE (1 << 5) 249#define SYSC_HAS_SIDLEMODE (1 << 5)
239#define SYSC_HAS_MIDLEMODE (1 << 6) 250#define SYSC_HAS_MIDLEMODE (1 << 6)
240#define SYSS_MISSING (1 << 7) 251#define SYSS_HAS_RESET_STATUS (1 << 7)
241#define SYSC_NO_CACHE (1 << 8) /* XXX SW flag, belongs elsewhere */ 252#define SYSC_NO_CACHE (1 << 8) /* XXX SW flag, belongs elsewhere */
253#define SYSC_HAS_RESET_STATUS (1 << 9)
242 254
243/* omap_hwmod_sysconfig.clockact flags */ 255/* omap_hwmod_sysconfig.clockact flags */
244#define CLOCKACT_TEST_BOTH 0x0 256#define CLOCKACT_TEST_BOTH 0x0
@@ -327,10 +339,12 @@ struct omap_hwmod_omap2_prcm {
327/** 339/**
328 * struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data 340 * struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data
329 * @clkctrl_reg: PRCM address of the clock control register 341 * @clkctrl_reg: PRCM address of the clock control register
342 * @rstctrl_reg: adress of the XXX_RSTCTRL register located in the PRM
330 * @submodule_wkdep_bit: bit shift of the WKDEP range 343 * @submodule_wkdep_bit: bit shift of the WKDEP range
331 */ 344 */
332struct omap_hwmod_omap4_prcm { 345struct omap_hwmod_omap4_prcm {
333 void __iomem *clkctrl_reg; 346 void __iomem *clkctrl_reg;
347 void __iomem *rstctrl_reg;
334 u8 submodule_wkdep_bit; 348 u8 submodule_wkdep_bit;
335}; 349};
336 350
@@ -352,6 +366,10 @@ struct omap_hwmod_omap4_prcm {
352 * HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup 366 * HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup
353 * HWMOD_NO_IDLEST : this module does not have idle status - this is the case 367 * HWMOD_NO_IDLEST : this module does not have idle status - this is the case
354 * only for few initiator modules on OMAP2 & 3. 368 * only for few initiator modules on OMAP2 & 3.
369 * HWMOD_CONTROL_OPT_CLKS_IN_RESET: Enable all optional clocks during reset.
370 * This is needed for devices like DSS that require optional clocks enabled
371 * in order to complete the reset. Optional clocks will be disabled
372 * again after the reset.
355 */ 373 */
356#define HWMOD_SWSUP_SIDLE (1 << 0) 374#define HWMOD_SWSUP_SIDLE (1 << 0)
357#define HWMOD_SWSUP_MSTANDBY (1 << 1) 375#define HWMOD_SWSUP_MSTANDBY (1 << 1)
@@ -360,6 +378,7 @@ struct omap_hwmod_omap4_prcm {
360#define HWMOD_NO_OCP_AUTOIDLE (1 << 4) 378#define HWMOD_NO_OCP_AUTOIDLE (1 << 4)
361#define HWMOD_SET_DEFAULT_CLOCKACT (1 << 5) 379#define HWMOD_SET_DEFAULT_CLOCKACT (1 << 5)
362#define HWMOD_NO_IDLEST (1 << 6) 380#define HWMOD_NO_IDLEST (1 << 6)
381#define HWMOD_CONTROL_OPT_CLKS_IN_RESET (1 << 7)
363 382
364/* 383/*
365 * omap_hwmod._int_flags definitions 384 * omap_hwmod._int_flags definitions
@@ -410,7 +429,7 @@ struct omap_hwmod_class {
410 * @class: struct omap_hwmod_class * to the class of this hwmod 429 * @class: struct omap_hwmod_class * to the class of this hwmod
411 * @od: struct omap_device currently associated with this hwmod (internal use) 430 * @od: struct omap_device currently associated with this hwmod (internal use)
412 * @mpu_irqs: ptr to an array of MPU IRQs (see also mpu_irqs_cnt) 431 * @mpu_irqs: ptr to an array of MPU IRQs (see also mpu_irqs_cnt)
413 * @sdma_chs: ptr to an array of SDMA channel IDs (see also sdma_chs_cnt) 432 * @sdma_reqs: ptr to an array of System DMA request IDs (see sdma_reqs_cnt)
414 * @prcm: PRCM data pertaining to this hwmod 433 * @prcm: PRCM data pertaining to this hwmod
415 * @main_clk: main clock: OMAP clock name 434 * @main_clk: main clock: OMAP clock name
416 * @_clk: pointer to the main struct clk (filled in at runtime) 435 * @_clk: pointer to the main struct clk (filled in at runtime)
@@ -424,7 +443,7 @@ struct omap_hwmod_class {
424 * @msuspendmux_reg_id: CONTROL_MSUSPENDMUX register ID (1-6) 443 * @msuspendmux_reg_id: CONTROL_MSUSPENDMUX register ID (1-6)
425 * @msuspendmux_shift: CONTROL_MSUSPENDMUX register bit shift 444 * @msuspendmux_shift: CONTROL_MSUSPENDMUX register bit shift
426 * @mpu_irqs_cnt: number of @mpu_irqs 445 * @mpu_irqs_cnt: number of @mpu_irqs
427 * @sdma_chs_cnt: number of @sdma_chs 446 * @sdma_reqs_cnt: number of @sdma_reqs
428 * @opt_clks_cnt: number of @opt_clks 447 * @opt_clks_cnt: number of @opt_clks
429 * @master_cnt: number of @master entries 448 * @master_cnt: number of @master entries
430 * @slaves_cnt: number of @slave entries 449 * @slaves_cnt: number of @slave entries
@@ -433,6 +452,7 @@ struct omap_hwmod_class {
433 * @_state: internal-use hwmod state 452 * @_state: internal-use hwmod state
434 * @flags: hwmod flags (documented below) 453 * @flags: hwmod flags (documented below)
435 * @omap_chip: OMAP chips this hwmod is present on 454 * @omap_chip: OMAP chips this hwmod is present on
455 * @_mutex: mutex serializing operations on this hwmod
436 * @node: list node for hwmod list (internal use) 456 * @node: list node for hwmod list (internal use)
437 * 457 *
438 * @main_clk refers to this module's "main clock," which for our 458 * @main_clk refers to this module's "main clock," which for our
@@ -448,7 +468,8 @@ struct omap_hwmod {
448 struct omap_hwmod_class *class; 468 struct omap_hwmod_class *class;
449 struct omap_device *od; 469 struct omap_device *od;
450 struct omap_hwmod_irq_info *mpu_irqs; 470 struct omap_hwmod_irq_info *mpu_irqs;
451 struct omap_hwmod_dma_info *sdma_chs; 471 struct omap_hwmod_dma_info *sdma_reqs;
472 struct omap_hwmod_rst_info *rst_lines;
452 union { 473 union {
453 struct omap_hwmod_omap2_prcm omap2; 474 struct omap_hwmod_omap2_prcm omap2;
454 struct omap_hwmod_omap4_prcm omap4; 475 struct omap_hwmod_omap4_prcm omap4;
@@ -461,6 +482,7 @@ struct omap_hwmod {
461 void *dev_attr; 482 void *dev_attr;
462 u32 _sysc_cache; 483 u32 _sysc_cache;
463 void __iomem *_mpu_rt_va; 484 void __iomem *_mpu_rt_va;
485 struct mutex _mutex;
464 struct list_head node; 486 struct list_head node;
465 u16 flags; 487 u16 flags;
466 u8 _mpu_port_index; 488 u8 _mpu_port_index;
@@ -468,7 +490,8 @@ struct omap_hwmod {
468 u8 msuspendmux_shift; 490 u8 msuspendmux_shift;
469 u8 response_lat; 491 u8 response_lat;
470 u8 mpu_irqs_cnt; 492 u8 mpu_irqs_cnt;
471 u8 sdma_chs_cnt; 493 u8 sdma_reqs_cnt;
494 u8 rst_lines_cnt;
472 u8 opt_clks_cnt; 495 u8 opt_clks_cnt;
473 u8 masters_cnt; 496 u8 masters_cnt;
474 u8 slaves_cnt; 497 u8 slaves_cnt;
@@ -492,6 +515,10 @@ int omap_hwmod_idle(struct omap_hwmod *oh);
492int _omap_hwmod_idle(struct omap_hwmod *oh); 515int _omap_hwmod_idle(struct omap_hwmod *oh);
493int omap_hwmod_shutdown(struct omap_hwmod *oh); 516int omap_hwmod_shutdown(struct omap_hwmod *oh);
494 517
518int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name);
519int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name);
520int omap_hwmod_read_hardreset(struct omap_hwmod *oh, const char *name);
521
495int omap_hwmod_enable_clocks(struct omap_hwmod *oh); 522int omap_hwmod_enable_clocks(struct omap_hwmod *oh);
496int omap_hwmod_disable_clocks(struct omap_hwmod *oh); 523int omap_hwmod_disable_clocks(struct omap_hwmod *oh);
497 524
@@ -534,5 +561,6 @@ int omap_hwmod_for_each_by_class(const char *classname,
534extern int omap2420_hwmod_init(void); 561extern int omap2420_hwmod_init(void);
535extern int omap2430_hwmod_init(void); 562extern int omap2430_hwmod_init(void);
536extern int omap3xxx_hwmod_init(void); 563extern int omap3xxx_hwmod_init(void);
564extern int omap44xx_hwmod_init(void);
537 565
538#endif 566#endif
diff --git a/arch/arm/plat-omap/include/plat/prcm.h b/arch/arm/plat-omap/include/plat/prcm.h
index 9fbd91419cd1..ab77442e42ab 100644
--- a/arch/arm/plat-omap/include/plat/prcm.h
+++ b/arch/arm/plat-omap/include/plat/prcm.h
@@ -38,6 +38,8 @@ u32 prm_read_mod_reg(s16 module, u16 idx);
38void prm_write_mod_reg(u32 val, s16 module, u16 idx); 38void prm_write_mod_reg(u32 val, s16 module, u16 idx);
39u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); 39u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
40u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask); 40u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask);
41u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask);
42u32 omap4_prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *reg);
41u32 cm_read_mod_reg(s16 module, u16 idx); 43u32 cm_read_mod_reg(s16 module, u16 idx);
42void cm_write_mod_reg(u32 val, s16 module, u16 idx); 44void cm_write_mod_reg(u32 val, s16 module, u16 idx);
43u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); 45u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
index ddf723be48dc..57dffa7e3ea6 100644
--- a/arch/arm/plat-omap/include/plat/uncompress.h
+++ b/arch/arm/plat-omap/include/plat/uncompress.h
@@ -153,6 +153,7 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
153 153
154 /* omap4 based boards using UART3 */ 154 /* omap4 based boards using UART3 */
155 DEBUG_LL_OMAP4(3, omap_4430sdp); 155 DEBUG_LL_OMAP4(3, omap_4430sdp);
156 DEBUG_LL_OMAP4(3, omap4_panda);
156 157
157 /* zoom2/3 external uart */ 158 /* zoom2/3 external uart */
158 DEBUG_LL_ZOOM(omap_zoom2); 159 DEBUG_LL_ZOOM(omap_zoom2);
diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h
index 2a9427c8cc48..667456228a12 100644
--- a/arch/arm/plat-omap/include/plat/usb.h
+++ b/arch/arm/plat-omap/include/plat/usb.h
@@ -105,7 +105,7 @@ static inline void omap1_usb_init(struct omap_usb_config *pdata)
105#if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_ARCH_OMAP_OTG_MODULE) 105#if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_ARCH_OMAP_OTG_MODULE)
106void omap2_usbfs_init(struct omap_usb_config *pdata); 106void omap2_usbfs_init(struct omap_usb_config *pdata);
107#else 107#else
108static inline omap2_usbfs_init(struct omap_usb_config *pdata) 108static inline void omap2_usbfs_init(struct omap_usb_config *pdata)
109{ 109{
110} 110}
111#endif 111#endif
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
index e31496e35b0f..ecbfe398a309 100644
--- a/arch/arm/plat-omap/mcbsp.c
+++ b/arch/arm/plat-omap/mcbsp.c
@@ -878,7 +878,7 @@ EXPORT_SYMBOL(omap_mcbsp_free);
878void omap_mcbsp_start(unsigned int id, int tx, int rx) 878void omap_mcbsp_start(unsigned int id, int tx, int rx)
879{ 879{
880 struct omap_mcbsp *mcbsp; 880 struct omap_mcbsp *mcbsp;
881 int idle; 881 int enable_srg = 0;
882 u16 w; 882 u16 w;
883 883
884 if (!omap_mcbsp_check_valid_id(id)) { 884 if (!omap_mcbsp_check_valid_id(id)) {
@@ -893,10 +893,13 @@ void omap_mcbsp_start(unsigned int id, int tx, int rx)
893 mcbsp->rx_word_length = (MCBSP_READ_CACHE(mcbsp, RCR1) >> 5) & 0x7; 893 mcbsp->rx_word_length = (MCBSP_READ_CACHE(mcbsp, RCR1) >> 5) & 0x7;
894 mcbsp->tx_word_length = (MCBSP_READ_CACHE(mcbsp, XCR1) >> 5) & 0x7; 894 mcbsp->tx_word_length = (MCBSP_READ_CACHE(mcbsp, XCR1) >> 5) & 0x7;
895 895
896 idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) | 896 /* Only enable SRG, if McBSP is master */
897 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1); 897 w = MCBSP_READ_CACHE(mcbsp, PCR0);
898 if (w & (FSXM | FSRM | CLKXM | CLKRM))
899 enable_srg = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
900 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
898 901
899 if (idle) { 902 if (enable_srg) {
900 /* Start the sample generator */ 903 /* Start the sample generator */
901 w = MCBSP_READ_CACHE(mcbsp, SPCR2); 904 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
902 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6)); 905 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6));
@@ -919,7 +922,7 @@ void omap_mcbsp_start(unsigned int id, int tx, int rx)
919 */ 922 */
920 udelay(500); 923 udelay(500);
921 924
922 if (idle) { 925 if (enable_srg) {
923 /* Start frame sync */ 926 /* Start frame sync */
924 w = MCBSP_READ_CACHE(mcbsp, SPCR2); 927 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
925 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7)); 928 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index d2b160942ccc..abe933cd8f09 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -82,6 +82,7 @@
82#include <linux/slab.h> 82#include <linux/slab.h>
83#include <linux/err.h> 83#include <linux/err.h>
84#include <linux/io.h> 84#include <linux/io.h>
85#include <linux/clk.h>
85 86
86#include <plat/omap_device.h> 87#include <plat/omap_device.h>
87#include <plat/omap_hwmod.h> 88#include <plat/omap_hwmod.h>
@@ -90,12 +91,6 @@
90#define USE_WAKEUP_LAT 0 91#define USE_WAKEUP_LAT 0
91#define IGNORE_WAKEUP_LAT 1 92#define IGNORE_WAKEUP_LAT 1
92 93
93/*
94 * OMAP_DEVICE_MAGIC: used to determine whether a struct omap_device
95 * obtained via container_of() is in fact a struct omap_device
96 */
97#define OMAP_DEVICE_MAGIC 0xf00dcafe
98
99/* Private functions */ 94/* Private functions */
100 95
101/** 96/**
@@ -243,6 +238,44 @@ static inline struct omap_device *_find_by_pdev(struct platform_device *pdev)
243 return container_of(pdev, struct omap_device, pdev); 238 return container_of(pdev, struct omap_device, pdev);
244} 239}
245 240
241/**
242 * _add_optional_clock_alias - Add clock alias for hwmod optional clocks
243 * @od: struct omap_device *od
244 *
245 * For every optional clock present per hwmod per omap_device, this function
246 * adds an entry in the clocks list of the form <dev-id=dev_name, con-id=role>
247 * if an entry is already present in it with the form <dev-id=NULL, con-id=role>
248 *
249 * The function is called from inside omap_device_build_ss(), after
250 * omap_device_register.
251 *
252 * This allows drivers to get a pointer to its optional clocks based on its role
253 * by calling clk_get(<dev*>, <role>).
254 *
255 * No return value.
256 */
257static void _add_optional_clock_alias(struct omap_device *od,
258 struct omap_hwmod *oh)
259{
260 int i;
261
262 for (i = 0; i < oh->opt_clks_cnt; i++) {
263 struct omap_hwmod_opt_clk *oc;
264 int r;
265
266 oc = &oh->opt_clks[i];
267
268 if (!oc->_clk)
269 continue;
270
271 r = clk_add_alias(oc->role, dev_name(&od->pdev.dev),
272 (char *)oc->clk, &od->pdev.dev);
273 if (r)
274 pr_err("omap_device: %s: clk_add_alias for %s failed\n",
275 dev_name(&od->pdev.dev), oc->role);
276 }
277}
278
246 279
247/* Public functions for use by core code */ 280/* Public functions for use by core code */
248 281
@@ -257,12 +290,11 @@ static inline struct omap_device *_find_by_pdev(struct platform_device *pdev)
257 */ 290 */
258int omap_device_count_resources(struct omap_device *od) 291int omap_device_count_resources(struct omap_device *od)
259{ 292{
260 struct omap_hwmod *oh;
261 int c = 0; 293 int c = 0;
262 int i; 294 int i;
263 295
264 for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++) 296 for (i = 0; i < od->hwmods_cnt; i++)
265 c += omap_hwmod_count_resources(oh); 297 c += omap_hwmod_count_resources(od->hwmods[i]);
266 298
267 pr_debug("omap_device: %s: counted %d total resources across %d " 299 pr_debug("omap_device: %s: counted %d total resources across %d "
268 "hwmods\n", od->pdev.name, c, od->hwmods_cnt); 300 "hwmods\n", od->pdev.name, c, od->hwmods_cnt);
@@ -289,12 +321,11 @@ int omap_device_count_resources(struct omap_device *od)
289 */ 321 */
290int omap_device_fill_resources(struct omap_device *od, struct resource *res) 322int omap_device_fill_resources(struct omap_device *od, struct resource *res)
291{ 323{
292 struct omap_hwmod *oh;
293 int c = 0; 324 int c = 0;
294 int i, r; 325 int i, r;
295 326
296 for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++) { 327 for (i = 0; i < od->hwmods_cnt; i++) {
297 r = omap_hwmod_fill_resources(oh, res); 328 r = omap_hwmod_fill_resources(od->hwmods[i], res);
298 res += r; 329 res += r;
299 c += r; 330 c += r;
300 } 331 }
@@ -414,15 +445,15 @@ struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
414 od->pm_lats = pm_lats; 445 od->pm_lats = pm_lats;
415 od->pm_lats_cnt = pm_lats_cnt; 446 od->pm_lats_cnt = pm_lats_cnt;
416 447
417 od->magic = OMAP_DEVICE_MAGIC;
418
419 if (is_early_device) 448 if (is_early_device)
420 ret = omap_early_device_register(od); 449 ret = omap_early_device_register(od);
421 else 450 else
422 ret = omap_device_register(od); 451 ret = omap_device_register(od);
423 452
424 for (i = 0; i < oh_cnt; i++) 453 for (i = 0; i < oh_cnt; i++) {
425 hwmods[i]->od = od; 454 hwmods[i]->od = od;
455 _add_optional_clock_alias(od, hwmods[i]);
456 }
426 457
427 if (ret) 458 if (ret)
428 goto odbs_exit4; 459 goto odbs_exit4;
@@ -473,6 +504,7 @@ int omap_device_register(struct omap_device *od)
473{ 504{
474 pr_debug("omap_device: %s: registering\n", od->pdev.name); 505 pr_debug("omap_device: %s: registering\n", od->pdev.name);
475 506
507 od->pdev.dev.parent = &omap_device_parent;
476 return platform_device_register(&od->pdev); 508 return platform_device_register(&od->pdev);
477} 509}
478 510
@@ -566,7 +598,6 @@ int omap_device_shutdown(struct platform_device *pdev)
566{ 598{
567 int ret, i; 599 int ret, i;
568 struct omap_device *od; 600 struct omap_device *od;
569 struct omap_hwmod *oh;
570 601
571 od = _find_by_pdev(pdev); 602 od = _find_by_pdev(pdev);
572 603
@@ -579,8 +610,8 @@ int omap_device_shutdown(struct platform_device *pdev)
579 610
580 ret = _omap_device_deactivate(od, IGNORE_WAKEUP_LAT); 611 ret = _omap_device_deactivate(od, IGNORE_WAKEUP_LAT);
581 612
582 for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++) 613 for (i = 0; i < od->hwmods_cnt; i++)
583 omap_hwmod_shutdown(oh); 614 omap_hwmod_shutdown(od->hwmods[i]);
584 615
585 od->_state = OMAP_DEVICE_STATE_SHUTDOWN; 616 od->_state = OMAP_DEVICE_STATE_SHUTDOWN;
586 617
@@ -627,18 +658,6 @@ int omap_device_align_pm_lat(struct platform_device *pdev,
627} 658}
628 659
629/** 660/**
630 * omap_device_is_valid - Check if pointer is a valid omap_device
631 * @od: struct omap_device *
632 *
633 * Return whether struct omap_device pointer @od points to a valid
634 * omap_device.
635 */
636bool omap_device_is_valid(struct omap_device *od)
637{
638 return (od && od->magic == OMAP_DEVICE_MAGIC);
639}
640
641/**
642 * omap_device_get_pwrdm - return the powerdomain * associated with @od 661 * omap_device_get_pwrdm - return the powerdomain * associated with @od
643 * @od: struct omap_device * 662 * @od: struct omap_device *
644 * 663 *
@@ -692,11 +711,10 @@ void __iomem *omap_device_get_rt_va(struct omap_device *od)
692 */ 711 */
693int omap_device_enable_hwmods(struct omap_device *od) 712int omap_device_enable_hwmods(struct omap_device *od)
694{ 713{
695 struct omap_hwmod *oh;
696 int i; 714 int i;
697 715
698 for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++) 716 for (i = 0; i < od->hwmods_cnt; i++)
699 omap_hwmod_enable(oh); 717 omap_hwmod_enable(od->hwmods[i]);
700 718
701 /* XXX pass along return value here? */ 719 /* XXX pass along return value here? */
702 return 0; 720 return 0;
@@ -710,11 +728,10 @@ int omap_device_enable_hwmods(struct omap_device *od)
710 */ 728 */
711int omap_device_idle_hwmods(struct omap_device *od) 729int omap_device_idle_hwmods(struct omap_device *od)
712{ 730{
713 struct omap_hwmod *oh;
714 int i; 731 int i;
715 732
716 for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++) 733 for (i = 0; i < od->hwmods_cnt; i++)
717 omap_hwmod_idle(oh); 734 omap_hwmod_idle(od->hwmods[i]);
718 735
719 /* XXX pass along return value here? */ 736 /* XXX pass along return value here? */
720 return 0; 737 return 0;
@@ -729,11 +746,10 @@ int omap_device_idle_hwmods(struct omap_device *od)
729 */ 746 */
730int omap_device_disable_clocks(struct omap_device *od) 747int omap_device_disable_clocks(struct omap_device *od)
731{ 748{
732 struct omap_hwmod *oh;
733 int i; 749 int i;
734 750
735 for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++) 751 for (i = 0; i < od->hwmods_cnt; i++)
736 omap_hwmod_disable_clocks(oh); 752 omap_hwmod_disable_clocks(od->hwmods[i]);
737 753
738 /* XXX pass along return value here? */ 754 /* XXX pass along return value here? */
739 return 0; 755 return 0;
@@ -748,12 +764,22 @@ int omap_device_disable_clocks(struct omap_device *od)
748 */ 764 */
749int omap_device_enable_clocks(struct omap_device *od) 765int omap_device_enable_clocks(struct omap_device *od)
750{ 766{
751 struct omap_hwmod *oh;
752 int i; 767 int i;
753 768
754 for (i = 0, oh = *od->hwmods; i < od->hwmods_cnt; i++, oh++) 769 for (i = 0; i < od->hwmods_cnt; i++)
755 omap_hwmod_enable_clocks(oh); 770 omap_hwmod_enable_clocks(od->hwmods[i]);
756 771
757 /* XXX pass along return value here? */ 772 /* XXX pass along return value here? */
758 return 0; 773 return 0;
759} 774}
775
776struct device omap_device_parent = {
777 .init_name = "omap",
778 .parent = &platform_bus,
779};
780
781static int __init omap_device_init(void)
782{
783 return device_register(&omap_device_parent);
784}
785core_initcall(omap_device_init);
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 226b2e858d6c..98c86ff17205 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -53,7 +53,7 @@
53#define OMAP4_SRAM_PUB_PA (OMAP4_SRAM_PA + 0x4000) 53#define OMAP4_SRAM_PUB_PA (OMAP4_SRAM_PA + 0x4000)
54#define OMAP4_SRAM_PUB_VA (OMAP4_SRAM_VA + 0x4000) 54#define OMAP4_SRAM_PUB_VA (OMAP4_SRAM_VA + 0x4000)
55 55
56#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) 56#if defined(CONFIG_ARCH_OMAP2PLUS)
57#define SRAM_BOOTLOADER_SZ 0x00 57#define SRAM_BOOTLOADER_SZ 0x00
58#else 58#else
59#define SRAM_BOOTLOADER_SZ 0x80 59#define SRAM_BOOTLOADER_SZ 0x80
@@ -93,16 +93,7 @@ extern unsigned long omapfb_reserve_sram(unsigned long sram_pstart,
93 */ 93 */
94static int is_sram_locked(void) 94static int is_sram_locked(void)
95{ 95{
96 int type = 0; 96 if (OMAP2_DEVICE_TYPE_GP == omap_type()) {
97
98 if (cpu_is_omap44xx())
99 /* Not yet supported */
100 return 0;
101
102 if (cpu_is_omap242x())
103 type = omap_rev() & OMAP2_DEVICETYPE_MASK;
104
105 if (type == GP_DEVICE) {
106 /* RAMFW: R/W access to all initiators for all qualifier sets */ 97 /* RAMFW: R/W access to all initiators for all qualifier sets */
107 if (cpu_is_omap242x()) { 98 if (cpu_is_omap242x()) {
108 __raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */ 99 __raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
diff --git a/drivers/mmc/host/omap.c b/drivers/mmc/host/omap.c
index d98ddcfac5e5..a9d62cfa87a2 100644
--- a/drivers/mmc/host/omap.c
+++ b/drivers/mmc/host/omap.c
@@ -1317,7 +1317,7 @@ static int __init mmc_omap_new_slot(struct mmc_omap_host *host, int id)
1317 host->slots[id] = slot; 1317 host->slots[id] = slot;
1318 1318
1319 mmc->caps = 0; 1319 mmc->caps = 0;
1320 if (host->pdata->slots[id].wires >= 4) 1320 if (host->pdata->slots[id].caps & MMC_CAP_8_BIT_DATA)
1321 mmc->caps |= MMC_CAP_4_BIT_DATA; 1321 mmc->caps |= MMC_CAP_4_BIT_DATA;
1322 1322
1323 mmc->ops = &mmc_omap_ops; 1323 mmc->ops = &mmc_omap_ops;
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index 4526d2791f29..53f8fa599cf5 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -2116,23 +2116,9 @@ static int __init omap_hsmmc_probe(struct platform_device *pdev)
2116 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | 2116 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
2117 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE; 2117 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
2118 2118
2119 switch (mmc_slot(host).wires) { 2119 mmc->caps |= mmc_slot(host).caps;
2120 case 8: 2120 if (mmc->caps & MMC_CAP_8_BIT_DATA)
2121 mmc->caps |= MMC_CAP_8_BIT_DATA;
2122 /* Fall through */
2123 case 4:
2124 mmc->caps |= MMC_CAP_4_BIT_DATA; 2121 mmc->caps |= MMC_CAP_4_BIT_DATA;
2125 break;
2126 case 1:
2127 /* Nothing to crib here */
2128 case 0:
2129 /* Assuming nothing was given by board, Core use's 1-Bit */
2130 break;
2131 default:
2132 /* Completely unexpected.. Core goes with 1-Bit Width */
2133 dev_crit(mmc_dev(host->mmc), "Invalid width %d\n used!"
2134 "using 1 instead\n", mmc_slot(host).wires);
2135 }
2136 2122
2137 if (mmc_slot(host).nonremovable) 2123 if (mmc_slot(host).nonremovable)
2138 mmc->caps |= MMC_CAP_NONREMOVABLE; 2124 mmc->caps |= MMC_CAP_NONREMOVABLE;
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-10 09:28:53 -0400