545 files changed, 28875 insertions, 13779 deletions

diff --git a/Documentation/DocBook/stylesheet.xsl b/Documentation/DocBook/stylesheet.xsl
index 254c1d5d2e50..85b25275196f 100644
--- a/Documentation/DocBook/stylesheet.xsl
+++ b/Documentation/DocBook/stylesheet.xsl
@@ -6,4 +6,5 @@
 <param name="callout.graphics">0</param>
 <!-- <param name="paper.type">A4</param> -->
 <param name="generate.section.toc.level">2</param>
+<param name="use.id.as.filename">1</param>
 </stylesheet>
diff --git a/Documentation/block/biodoc.txt b/Documentation/block/biodoc.txt
index 508b5b2b0289..b9a83dd24732 100644
--- a/Documentation/block/biodoc.txt
+++ b/Documentation/block/biodoc.txt
@@ -7,7 +7,7 @@ Notes Written on Jan 15, 2002:
 
 Last Updated May 2, 2002
 September 2003: Updated I/O Scheduler portions
-        Nick Piggin <piggin@cyberone.com.au>
+        Nick Piggin <npiggin@kernel.dk>
 
 Introduction:
 
diff --git a/Documentation/kbuild/kbuild.txt b/Documentation/kbuild/kbuild.txt
index 634c625da8ce..0d8addbb0fae 100644
--- a/Documentation/kbuild/kbuild.txt
+++ b/Documentation/kbuild/kbuild.txt
@@ -40,15 +40,15 @@ Set the directory to look for the kernel source when building external
 modules.
 The directory can be specified in several ways:
 1) Use "M=..." on the command line
-2) Environmnet variable KBUILD_EXTMOD
-3) Environmnet variable SUBDIRS
+2) Environment variable KBUILD_EXTMOD
+3) Environment variable SUBDIRS
 The possibilities are listed in the order they take precedence.
 Using "M=..." will always override the others.
 
 KBUILD_OUTPUT
 --------------------------------------------------
 Specify the output directory when building the kernel.
-The output directory can also be specificed using "O=...".
+The output directory can also be specified using "O=...".
 Setting "O=..." takes precedence over KBUILD_OUTPUT.
 
 ARCH
@@ -90,7 +90,7 @@ The script will be called with the following arguments:
     $3 - kernel map file
     $4 - default install path (use root directory if blank)
 
-The implmentation of "make install" is architecture specific
+The implementation of "make install" is architecture specific
 and it may differ from the above.
 
 INSTALLKERNEL is provided to enable the possibility to
diff --git a/Documentation/kbuild/makefiles.txt b/Documentation/kbuild/makefiles.txt
index 71c602d61680..8abd041b605d 100644
--- a/Documentation/kbuild/makefiles.txt
+++ b/Documentation/kbuild/makefiles.txt
@@ -168,7 +168,7 @@ more details, with real examples.
                 #drivers/isdn/i4l/Makefile
                 # Makefile for the kernel ISDN subsystem and device drivers.
                 # Each configuration option enables a list of files.
-                obj-$(CONFIG_ISDN)             += isdn.o
+                obj-$(CONFIG_ISDN_I4L)         += isdn.o
                 obj-$(CONFIG_ISDN_PPP_BSDCOMP) += isdn_bsdcomp.o
 
 --- 3.3 Loadable module goals - obj-m
@@ -187,34 +187,35 @@ more details, with real examples.
         Note: In this example $(CONFIG_ISDN_PPP_BSDCOMP) evaluates to 'm'
 
         If a kernel module is built from several source files, you specify
-        that you want to build a module in the same way as above.
-
-        Kbuild needs to know which the parts that you want to build your
-        module from, so you have to tell it by setting an
-        $(<module_name>-objs) variable.
+        that you want to build a module in the same way as above; however,
+        kbuild needs to know which object files you want to build your
+        module from, so you have to tell it by setting a $(<module_name>-y)
+        variable.
 
         Example:
                 #drivers/isdn/i4l/Makefile
-                obj-$(CONFIG_ISDN) += isdn.o
-                isdn-objs := isdn_net_lib.o isdn_v110.o isdn_common.o
+                obj-$(CONFIG_ISDN_I4L) += isdn.o
+                isdn-y := isdn_net_lib.o isdn_v110.o isdn_common.o
 
         In this example, the module name will be isdn.o. Kbuild will
-        compile the objects listed in $(isdn-objs) and then run
+        compile the objects listed in $(isdn-y) and then run
         "$(LD) -r" on the list of these files to generate isdn.o.
 
-        Kbuild recognises objects used for composite objects by the suffix
-        -objs, and the suffix -y. This allows the Makefiles to use
-        the value of a CONFIG_ symbol to determine if an object is part
-        of a composite object.
+        Due to kbuild recognizing $(<module_name>-y) for composite objects,
+        you can use the value of a CONFIG_ symbol to optionally include an
+        object file as part of a composite object.
 
         Example:
                 #fs/ext2/Makefile
-                obj-$(CONFIG_EXT2_FS)        += ext2.o
-                ext2-y                       := balloc.o bitmap.o
-                ext2-$(CONFIG_EXT2_FS_XATTR) += xattr.o
+                obj-$(CONFIG_EXT2_FS) += ext2.o
+                ext2-y := balloc.o dir.o file.o ialloc.o inode.o ioctl.o \
+                          namei.o super.o symlink.o
+                ext2-$(CONFIG_EXT2_FS_XATTR) += xattr.o xattr_user.o \
+                                                xattr_trusted.o
 
-        In this example, xattr.o is only part of the composite object
-        ext2.o if $(CONFIG_EXT2_FS_XATTR) evaluates to 'y'.
+        In this example, xattr.o, xattr_user.o and xattr_trusted.o are only
+        part of the composite object ext2.o if $(CONFIG_EXT2_FS_XATTR)
+        evaluates to 'y'.
 
         Note: Of course, when you are building objects into the kernel,
         the syntax above will also work. So, if you have CONFIG_EXT2_FS=y,
@@ -244,12 +245,12 @@ more details, with real examples.
         may contain both a built-in.o and a lib.a file.
 
         Example:
-                #arch/i386/lib/Makefile
-                lib-y    := checksum.o delay.o
+                #arch/x86/lib/Makefile
+                lib-y    := delay.o
 
-        This will create a library lib.a based on checksum.o and delay.o.
-        For kbuild to actually recognize that there is a lib.a being built,
-        the directory shall be listed in libs-y.
+        This will create a library lib.a based on delay.o. For kbuild to
+        actually recognize that there is a lib.a being built, the directory
+        shall be listed in libs-y.
         See also "6.3 List directories to visit when descending".
 
         Use of lib-y is normally restricted to lib/ and arch/*/lib.
@@ -284,43 +285,40 @@ more details, with real examples.
 --- 3.7 Compilation flags
 
     ccflags-y, asflags-y and ldflags-y
-        The three flags listed above applies only to the kbuild makefile
-        where they are assigned. They are used for all the normal
-        cc, as and ld invocation happenign during a recursive build.
+        These three flags apply only to the kbuild makefile in which they
+        are assigned. They are used for all the normal cc, as and ld
+        invocations happening during a recursive build.
         Note: Flags with the same behaviour were previously named:
         EXTRA_CFLAGS, EXTRA_AFLAGS and EXTRA_LDFLAGS.
-        They are yet supported but their use are deprecated.
+        They are still supported but their usage is deprecated.
 
-        ccflags-y specifies options for compiling C files with $(CC).
+        ccflags-y specifies options for compiling with $(CC).
 
         Example:
-                # drivers/sound/emu10k1/Makefile
-                ccflags-y += -I$(obj)
-                ccflags-$(DEBUG) += -DEMU10K1_DEBUG
-
+                # drivers/acpi/Makefile
+                ccflags-y := -Os
+                ccflags-$(CONFIG_ACPI_DEBUG) += -DACPI_DEBUG_OUTPUT
 
         This variable is necessary because the top Makefile owns the
         variable $(KBUILD_CFLAGS) and uses it for compilation flags for the
         entire tree.
 
-        asflags-y is a similar string for per-directory options
-        when compiling assembly language source.
+        asflags-y specifies options for assembling with $(AS).
 
         Example:
-                #arch/x86_64/kernel/Makefile
-                asflags-y := -traditional
+                #arch/sparc/kernel/Makefile
+                asflags-y := -ansi
 
-
-        ldflags-y is a string for per-directory options to $(LD).
+        ldflags-y specifies options for linking with $(LD).
 
         Example:
-                #arch/m68k/fpsp040/Makefile
-                ldflags-y := -x
+                #arch/cris/boot/compressed/Makefile
+                ldflags-y += -T $(srctree)/$(src)/decompress_$(arch-y).lds
 
     subdir-ccflags-y, subdir-asflags-y
-        The two flags listed above are similar to ccflags-y and as-falgs-y.
-        The difference is that the subdir- variants has effect for the kbuild
-        file where tey are present and all subdirectories.
+        The two flags listed above are similar to ccflags-y and asflags-y.
+        The difference is that the subdir- variants have effect for the kbuild
+        file where they are present and all subdirectories.
         Options specified using subdir-* are added to the commandline before
         the options specified using the non-subdir variants.
 
@@ -340,18 +338,18 @@ more details, with real examples.
                 CFLAGS_aha152x.o =   -DAHA152X_STAT -DAUTOCONF
                 CFLAGS_gdth.o    = # -DDEBUG_GDTH=2 -D__SERIAL__ -D__COM2__ \
                                      -DGDTH_STATISTICS
-                CFLAGS_seagate.o =   -DARBITRATE -DPARITY -DSEAGATE_USE_ASM
 
-        These three lines specify compilation flags for aha152x.o,
-        gdth.o, and seagate.o
+        These two lines specify compilation flags for aha152x.o and gdth.o.
 
         $(AFLAGS_$@) is a similar feature for source files in assembly
         languages.
 
         Example:
                 # arch/arm/kernel/Makefile
-                AFLAGS_head-armv.o := -DTEXTADDR=$(TEXTADDR) -traditional
-                AFLAGS_head-armo.o := -DTEXTADDR=$(TEXTADDR) -traditional
+                AFLAGS_head.o        := -DTEXT_OFFSET=$(TEXT_OFFSET)
+                AFLAGS_crunch-bits.o := -Wa,-mcpu=ep9312
+                AFLAGS_iwmmxt.o      := -Wa,-mcpu=iwmmxt
+
 
 --- 3.9 Dependency tracking
 
@@ -1176,14 +1174,14 @@ When kbuild executes, the following steps are followed (roughly):
 === 7 Kbuild syntax for exported headers
 
 The kernel include a set of headers that is exported to userspace.
-Many headers can be exported as-is but other headers requires  a
+Many headers can be exported as-is but other headers require a
 minimal pre-processing before they are ready for user-space.
 The pre-processing does:
 - drop kernel specific annotations
 - drop include of compiler.h
-- drop all sections that is kernel internat (guarded by ifdef __KERNEL__)
+- drop all sections that are kernel internal (guarded by ifdef __KERNEL__)
 
-Each relevant directory contain a file name "Kbuild" which specify the
+Each relevant directory contains a file name "Kbuild" which specifies the
 headers to be exported.
 See subsequent chapter for the syntax of the Kbuild file.
 
diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
index d9239d5f3ad3..ef8b11cec6e9 100644
--- a/Documentation/kernel-parameters.txt
+++ b/Documentation/kernel-parameters.txt
@@ -116,6 +116,7 @@ parameter is applicable:
                         More X86-64 boot options can be found in
                         Documentation/x86/x86_64/boot-options.txt .
         X86     Either 32bit or 64bit x86 (same as X86-32+X86-64)
+        XEN     Xen support is enabled
 
 In addition, the following text indicates that the option:
 
@@ -2886,6 +2887,16 @@ and is between 256 and 4096 characters. It is defined in the file
         xd=             [HW,XT] Original XT pre-IDE (RLL encoded) disks.
         xd_geo=         See header of drivers/block/xd.c.
 
+        xen_emul_unplug=                [HW,X86,XEN]
+                        Unplug Xen emulated devices
+                        Format: [unplug0,][unplug1]
+                        ide-disks -- unplug primary master IDE devices
+                        aux-ide-disks -- unplug non-primary-master IDE devices
+                        nics -- unplug network devices
+                        all -- unplug all emulated devices (NICs and IDE disks)
+                        ignore -- continue loading the Xen platform PCI driver even
+                                if the version check failed
+
         xirc2ps_cs=     [NET,PCMCIA]
                         Format:
                         <irq>,<irq_mask>,<io>,<full_duplex>,<do_sound>,<lockup_hack>[,<irq2>[,<irq3>[,<irq4>]]]
diff --git a/Documentation/kprobes.txt b/Documentation/kprobes.txt
index 6653017680dd..1762b81fcdf2 100644
--- a/Documentation/kprobes.txt
+++ b/Documentation/kprobes.txt
@@ -285,6 +285,7 @@ architectures:
 - sparc64 (Return probes not yet implemented.)
 - arm
 - ppc
+- mips
 
 3. Configuring Kprobes
 
diff --git a/Documentation/powerpc/dts-bindings/fsl/diu.txt b/Documentation/powerpc/dts-bindings/fsl/diu.txt
index deb35de70988..b66cb6d31d69 100644
--- a/Documentation/powerpc/dts-bindings/fsl/diu.txt
+++ b/Documentation/powerpc/dts-bindings/fsl/diu.txt
@@ -4,10 +4,17 @@ The Freescale DIU is a LCD controller, with proper hardware, it can also
 drive DVI monitors.
 
 Required properties:
-- compatible : should be "fsl-diu".
+- compatible : should be "fsl,diu" or "fsl,mpc5121-diu".
 - reg : should contain at least address and length of the DIU register
   set.
-- Interrupts : one DIU interrupt should be describe here.
+- interrupts : one DIU interrupt should be described here.
+- interrupt-parent : the phandle for the interrupt controller that
+  services interrupts for this device.
+
+Optional properties:
+- edid : verbatim EDID data block describing attached display.
+  Data from the detailed timing descriptor will be used to
+  program the display controller.
 
 Example (MPC8610HPCD):
         display@2c000 {
@@ -16,3 +23,12 @@ Example (MPC8610HPCD):
                 interrupts = <72 2>;
                 interrupt-parent = <&mpic>;
         };
+
+Example for MPC5121:
+        display@2100 {
+                compatible = "fsl,mpc5121-diu";
+                reg = <0x2100 0x100>;
+                interrupts = <64 0x8>;
+                interrupt-parent = <&ipic>;
+                edid = [edid-data];
+        };
diff --git a/Documentation/powerpc/dts-bindings/fsl/i2c.txt b/Documentation/powerpc/dts-bindings/fsl/i2c.txt
index 50da20310585..1eacd6b20ed5 100644
--- a/Documentation/powerpc/dts-bindings/fsl/i2c.txt
+++ b/Documentation/powerpc/dts-bindings/fsl/i2c.txt
@@ -20,6 +20,7 @@ Recommended properties :
  - fsl,preserve-clocking : boolean; if defined, the clock settings
    from the bootloader are preserved (not touched).
  - clock-frequency : desired I2C bus clock frequency in Hz.
+ - fsl,timeout : I2C bus timeout in microseconds.
 
 Examples :
 
@@ -59,4 +60,5 @@ Examples :
                 interrupts = <43 2>;
                 interrupt-parent = <&mpic>;
                 clock-frequency = <400000>;
+                fsl,timeout = <10000>;
         };
diff --git a/Documentation/vm/page-types.c b/Documentation/vm/page-types.c
index 66e9358e2144..ccd951fa94ee 100644
--- a/Documentation/vm/page-types.c
+++ b/Documentation/vm/page-types.c
@@ -694,7 +694,7 @@ static void usage(void)
 #endif
 "            -l|--list                  Show page details in ranges\n"
 "            -L|--list-each             Show page details one by one\n"
-"            -N|--no-summary            Don't show summay info\n"
+"            -N|--no-summary            Don't show summary info\n"
 "            -X|--hwpoison              hwpoison pages\n"
 "            -x|--unpoison              unpoison pages\n"
 "            -h|--help                  Show this usage message\n"
diff --git a/MAINTAINERS b/MAINTAINERS
index 88ec0447a4f3..05741e0da46c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -4731,7 +4731,7 @@ T:	git git://git.kernel.org/pub/scm/linux/kernel/git/ivd/rt2x00.git
 F:      drivers/net/wireless/rt2x00/
 
 RAMDISK RAM BLOCK DEVICE DRIVER
-M:      Nick Piggin <npiggin@suse.de>
+M:      Nick Piggin <npiggin@kernel.dk>
 S:      Maintained
 F:      Documentation/blockdev/ramdisk.txt
 F:      drivers/block/brd.c
@@ -5357,7 +5357,7 @@ T:	git git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc-2.6.git
 T:      git git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc-next-2.6.git
 S:      Maintained
 F:      arch/sparc/
-F:      drivers/sbus
+F:      drivers/sbus/
 
 SPARC SERIAL DRIVERS
 M:      "David S. Miller" <davem@davemloft.net>
diff --git a/arch/ia64/configs/bigsur_defconfig b/arch/ia64/configs/bigsur_defconfig
index 312b12094a1d..c5fe20553dad 100644
--- a/arch/ia64/configs/bigsur_defconfig
+++ b/arch/ia64/configs/bigsur_defconfig
@@ -1,1358 +1,118 @@
-#
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.16-rc5
-# Mon Feb 27 16:10:42 2006
-#
-
-#
-# Code maturity level options
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_LOCK_KERNEL=y
-CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
-CONFIG_LOCALVERSION=""
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-CONFIG_POSIX_MQUEUE=y
-# CONFIG_BSD_PROCESS_ACCT is not set
-CONFIG_SYSCTL=y
-# CONFIG_AUDIT is not set
-# CONFIG_IKCONFIG is not set
-# CONFIG_CPUSETS is not set
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-# CONFIG_EMBEDDED is not set
-CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_ALL is not set
-# CONFIG_KALLSYMS_EXTRA_PASS is not set
-CONFIG_HOTPLUG=y
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_EPOLL=y
-CONFIG_SHMEM=y
-CONFIG_CC_ALIGN_FUNCTIONS=0
-CONFIG_CC_ALIGN_LABELS=0
-CONFIG_CC_ALIGN_LOOPS=0
-CONFIG_CC_ALIGN_JUMPS=0
-CONFIG_SLUB=y
-# CONFIG_TINY_SHMEM is not set
-CONFIG_BASE_SMALL=0
-# CONFIG_SLOB is not set
-
-#
-# Loadable module support
-#
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_MODULE_FORCE_UNLOAD is not set
-CONFIG_OBSOLETE_MODPARM=y
-# CONFIG_MODVERSIONS is not set
-# CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_KMOD=y
-CONFIG_STOP_MACHINE=y
-
-#
-# Block layer
-#
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-CONFIG_DEFAULT_AS=y
-# CONFIG_DEFAULT_DEADLINE is not set
-# CONFIG_DEFAULT_CFQ is not set
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="anticipatory"
-
-#
-# Processor type and features
-#
-CONFIG_IA64=y
-CONFIG_64BIT=y
-CONFIG_MMU=y
-CONFIG_SWIOTLB=y
-CONFIG_RWSEM_XCHGADD_ALGORITHM=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_GENERIC_TIME=y
-CONFIG_EFI=y
-CONFIG_GENERIC_IOMAP=y
-CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
-CONFIG_DMA_IS_DMA32=y
-# CONFIG_IA64_GENERIC is not set
-CONFIG_IA64_DIG=y
-# CONFIG_IA64_HP_ZX1 is not set
-# CONFIG_IA64_HP_ZX1_SWIOTLB is not set
-# CONFIG_IA64_SGI_SN2 is not set
-# CONFIG_IA64_HP_SIM is not set
-CONFIG_ITANIUM=y
-# CONFIG_MCKINLEY is not set
-# CONFIG_IA64_PAGE_SIZE_4KB is not set
-# CONFIG_IA64_PAGE_SIZE_8KB is not set
-CONFIG_IA64_PAGE_SIZE_16KB=y
-# CONFIG_IA64_PAGE_SIZE_64KB is not set
-CONFIG_PGTABLE_3=y
-# CONFIG_PGTABLE_4 is not set
-# CONFIG_HZ_100 is not set
-CONFIG_HZ_250=y
-# CONFIG_HZ_1000 is not set
-CONFIG_HZ=250
-CONFIG_IA64_BRL_EMU=y
-CONFIG_IA64_L1_CACHE_SHIFT=6
-# CONFIG_IA64_CYCLONE is not set
-CONFIG_IOSAPIC=y
-CONFIG_FORCE_MAX_ZONEORDER=17
-CONFIG_SMP=y
-CONFIG_NR_CPUS=2
-# CONFIG_HOTPLUG_CPU is not set
-# CONFIG_SCHED_SMT is not set
-CONFIG_PREEMPT=y
-CONFIG_SELECT_MEMORY_MODEL=y
-CONFIG_FLATMEM_MANUAL=y
-# CONFIG_DISCONTIGMEM_MANUAL is not set
-# CONFIG_SPARSEMEM_MANUAL is not set
-CONFIG_FLATMEM=y
-CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
-CONFIG_SPLIT_PTLOCK_CPUS=4
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
-CONFIG_ARCH_FLATMEM_ENABLE=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-# CONFIG_VIRTUAL_MEM_MAP is not set
-# CONFIG_IA64_MCA_RECOVERY is not set
-CONFIG_PERFMON=y
-CONFIG_IA64_PALINFO=y
-
-#
-# Firmware Drivers
-#
-CONFIG_EFI_VARS=y
-CONFIG_EFI_PCDP=y
-CONFIG_BINFMT_ELF=y
-CONFIG_BINFMT_MISC=m
-
-#
-# Power management and ACPI
-#
-CONFIG_PM=y
-CONFIG_PM_LEGACY=y
-# CONFIG_PM_DEBUG is not set
-
-#
-# ACPI (Advanced Configuration and Power Interface) Support
-#
-CONFIG_ACPI=y
 CONFIG_ACPI_BUTTON=m
 CONFIG_ACPI_FAN=m
 CONFIG_ACPI_PROCESSOR=m
-CONFIG_ACPI_THERMAL=m
-CONFIG_ACPI_BLACKLIST_YEAR=0
-# CONFIG_ACPI_DEBUG is not set
-CONFIG_ACPI_EC=y
-CONFIG_ACPI_POWER=y
-CONFIG_ACPI_SYSTEM=y
-# CONFIG_ACPI_CONTAINER is not set
-
-#
-# CPU Frequency scaling
-#
-# CONFIG_CPU_FREQ is not set
-
-#
-# Bus options (PCI, PCMCIA)
-#
-CONFIG_PCI=y
-CONFIG_PCI_DOMAINS=y
-# CONFIG_PCI_MSI is not set
-CONFIG_PCI_LEGACY_PROC=y
-# CONFIG_PCI_DEBUG is not set
-
-#
-# PCI Hotplug Support
-#
-# CONFIG_HOTPLUG_PCI is not set
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
-# CONFIG_PCCARD is not set
-
-#
-# Networking
-#
-CONFIG_NET=y
-
-#
-# Networking options
-#
-# CONFIG_NETDEBUG is not set
-CONFIG_PACKET=y
-CONFIG_PACKET_MMAP=y
-CONFIG_UNIX=y
-# CONFIG_NET_KEY is not set
-CONFIG_INET=y
-# CONFIG_IP_MULTICAST is not set
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_FIB_HASH=y
-# CONFIG_IP_PNP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_ARPD is not set
-# CONFIG_SYN_COOKIES is not set
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_TUNNEL is not set
-CONFIG_INET_DIAG=y
-CONFIG_INET_TCP_DIAG=y
-# CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TCP_CONG_BIC=y
-# CONFIG_IPV6 is not set
-# CONFIG_NETFILTER is not set
-
-#
-# DCCP Configuration (EXPERIMENTAL)
-#
-# CONFIG_IP_DCCP is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
-# CONFIG_IP_SCTP is not set
-
-#
-# TIPC Configuration (EXPERIMENTAL)
-#
-# CONFIG_TIPC is not set
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_NET_DIVERT is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
-# CONFIG_NET_SCHED is not set
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_HAMRADIO is not set
-# CONFIG_IRDA is not set
-# CONFIG_BT is not set
-# CONFIG_IEEE80211 is not set
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-# CONFIG_FW_LOADER is not set
-# CONFIG_DEBUG_DRIVER is not set
-
-#
-# Connector - unified userspace <-> kernelspace linker
-#
-# CONFIG_CONNECTOR is not set
-
-#
-# Memory Technology Devices (MTD)
-#
-# CONFIG_MTD is not set
-
-#
-# Parallel port support
-#
-# CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-CONFIG_PNP=y
-# CONFIG_PNP_DEBUG is not set
-
-#
-# Protocols
-#
-CONFIG_PNPACPI=y
-
-#
-# Block devices
-#
-# CONFIG_BLK_CPQ_DA is not set
-# CONFIG_BLK_CPQ_CISS_DA is not set
-# CONFIG_BLK_DEV_DAC960 is not set
-# CONFIG_BLK_DEV_UMEM is not set
-# CONFIG_BLK_DEV_COW_COMMON is not set
-CONFIG_BLK_DEV_LOOP=m
+CONFIG_AGP_I460=m
+CONFIG_AGP=m
+CONFIG_AUTOFS4_FS=m
+CONFIG_AUTOFS_FS=m
+CONFIG_BINFMT_MISC=m
 CONFIG_BLK_DEV_CRYPTOLOOP=m
-CONFIG_BLK_DEV_NBD=m
-# CONFIG_BLK_DEV_SX8 is not set
-# CONFIG_BLK_DEV_UB is not set
-CONFIG_BLK_DEV_RAM=m
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=4096
-# CONFIG_CDROM_PKTCDVD is not set
-# CONFIG_ATA_OVER_ETH is not set
-
-#
-# ATA/ATAPI/MFM/RLL support
-#
-CONFIG_IDE=m
-CONFIG_IDE_MAX_HWIFS=4
-CONFIG_BLK_DEV_IDE=m
-
-#
-# Please see Documentation/ide.txt for help/info on IDE drives
-#
-# CONFIG_BLK_DEV_IDE_SATA is not set
-CONFIG_BLK_DEV_IDEDISK=m
-# CONFIG_IDEDISK_MULTI_MODE is not set
-CONFIG_BLK_DEV_IDECD=m
-# CONFIG_BLK_DEV_IDETAPE is not set
-CONFIG_BLK_DEV_IDEFLOPPY=m
-# CONFIG_BLK_DEV_IDESCSI is not set
-# CONFIG_IDE_TASK_IOCTL is not set
-
-#
-# IDE chipset support/bugfixes
-#
-# CONFIG_IDE_GENERIC is not set
-# CONFIG_BLK_DEV_IDEPNP is not set
-CONFIG_BLK_DEV_IDEPCI=y
-CONFIG_IDEPCI_SHARE_IRQ=y
-# CONFIG_BLK_DEV_OFFBOARD is not set
+CONFIG_BLK_DEV_DM=m
 CONFIG_BLK_DEV_GENERIC=m
-# CONFIG_BLK_DEV_OPTI621 is not set
-CONFIG_BLK_DEV_IDEDMA_PCI=y
-# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
-CONFIG_IDEDMA_PCI_AUTO=y
-# CONFIG_IDEDMA_ONLYDISK is not set
-# CONFIG_BLK_DEV_AEC62XX is not set
-# CONFIG_BLK_DEV_ALI15X3 is not set
-# CONFIG_BLK_DEV_AMD74XX is not set
-# CONFIG_BLK_DEV_CMD64X is not set
-# CONFIG_BLK_DEV_TRIFLEX is not set
-# CONFIG_BLK_DEV_CY82C693 is not set
-# CONFIG_BLK_DEV_CS5520 is not set
-# CONFIG_BLK_DEV_CS5530 is not set
-# CONFIG_BLK_DEV_HPT34X is not set
-# CONFIG_BLK_DEV_HPT366 is not set
-# CONFIG_BLK_DEV_SC1200 is not set
+CONFIG_BLK_DEV_IDECD=m
+CONFIG_BLK_DEV_LOOP=m
+CONFIG_BLK_DEV_MD=m
+CONFIG_BLK_DEV_NBD=m
 CONFIG_BLK_DEV_PIIX=m
-# CONFIG_BLK_DEV_IT821X is not set
-# CONFIG_BLK_DEV_NS87415 is not set
-# CONFIG_BLK_DEV_PDC202XX_OLD is not set
-# CONFIG_BLK_DEV_PDC202XX_NEW is not set
-# CONFIG_BLK_DEV_SVWKS is not set
-# CONFIG_BLK_DEV_SIIMAGE is not set
-# CONFIG_BLK_DEV_SLC90E66 is not set
-# CONFIG_BLK_DEV_TRM290 is not set
-# CONFIG_BLK_DEV_VIA82CXXX is not set
-# CONFIG_IDE_ARM is not set
-CONFIG_BLK_DEV_IDEDMA=y
-# CONFIG_IDEDMA_IVB is not set
-CONFIG_IDEDMA_AUTO=y
-# CONFIG_BLK_DEV_HD is not set
-
-#
-# SCSI device support
-#
-# CONFIG_RAID_ATTRS is not set
-CONFIG_SCSI=y
-CONFIG_SCSI_PROC_FS=y
-
-#
-# SCSI support type (disk, tape, CD-ROM)
-#
+CONFIG_BLK_DEV_RAM=m
 CONFIG_BLK_DEV_SD=y
-# CONFIG_CHR_DEV_ST is not set
-# CONFIG_CHR_DEV_OSST is not set
-# CONFIG_BLK_DEV_SR is not set
-# CONFIG_CHR_DEV_SG is not set
-# CONFIG_CHR_DEV_SCH is not set
-
-#
-# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
-#
-# CONFIG_SCSI_MULTI_LUN is not set
-CONFIG_SCSI_CONSTANTS=y
-CONFIG_SCSI_LOGGING=y
-
-#
-# SCSI Transport Attributes
-#
-CONFIG_SCSI_SPI_ATTRS=m
-# CONFIG_SCSI_FC_ATTRS is not set
-# CONFIG_SCSI_ISCSI_ATTRS is not set
-# CONFIG_SCSI_SAS_ATTRS is not set
-
-#
-# SCSI low-level drivers
-#
-# CONFIG_ISCSI_TCP is not set
-# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
-# CONFIG_SCSI_3W_9XXX is not set
-# CONFIG_SCSI_ACARD is not set
-# CONFIG_SCSI_AACRAID is not set
-# CONFIG_SCSI_AIC7XXX is not set
-# CONFIG_SCSI_AIC7XXX_OLD is not set
-# CONFIG_SCSI_AIC79XX is not set
-# CONFIG_MEGARAID_NEWGEN is not set
-# CONFIG_MEGARAID_LEGACY is not set
-# CONFIG_MEGARAID_SAS is not set
-# CONFIG_SCSI_SATA is not set
-# CONFIG_SCSI_DMX3191D is not set
-# CONFIG_SCSI_FUTURE_DOMAIN is not set
-# CONFIG_SCSI_IPS is not set
-# CONFIG_SCSI_INITIO is not set
-# CONFIG_SCSI_INIA100 is not set
-# CONFIG_SCSI_SYM53C8XX_2 is not set
-# CONFIG_SCSI_IPR is not set
-# CONFIG_SCSI_QLOGIC_FC is not set
-CONFIG_SCSI_QLOGIC_1280=y
-# CONFIG_SCSI_QLA_FC is not set
-# CONFIG_SCSI_LPFC is not set
-# CONFIG_SCSI_DC395x is not set
-# CONFIG_SCSI_DC390T is not set
-# CONFIG_SCSI_DEBUG is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
-CONFIG_MD=y
-CONFIG_BLK_DEV_MD=m
-CONFIG_MD_LINEAR=m
-CONFIG_MD_RAID0=m
-CONFIG_MD_RAID1=m
-CONFIG_MD_RAID10=m
-CONFIG_MD_RAID5=m
-CONFIG_MD_RAID6=m
-CONFIG_MD_MULTIPATH=m
-# CONFIG_MD_FAULTY is not set
-CONFIG_BLK_DEV_DM=m
+CONFIG_CIFS=m
+CONFIG_CIFS_POSIX=y
+CONFIG_CIFS_STATS=y
+CONFIG_CIFS_XATTR=y
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_MD5=y
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_MUTEXES=y
 CONFIG_DM_CRYPT=m
-CONFIG_DM_SNAPSHOT=m
 CONFIG_DM_MIRROR=m
+CONFIG_DM_SNAPSHOT=m
 CONFIG_DM_ZERO=m
-# CONFIG_DM_MULTIPATH is not set
-
-#
-# Fusion MPT device support
-#
-# CONFIG_FUSION is not set
-# CONFIG_FUSION_SPI is not set
-# CONFIG_FUSION_FC is not set
-# CONFIG_FUSION_SAS is not set
-
-#
-# IEEE 1394 (FireWire) support
-#
-# CONFIG_IEEE1394 is not set
-
-#
-# I2O device support
-#
-# CONFIG_I2O is not set
-
-#
-# Network device support
-#
-CONFIG_NETDEVICES=y
-CONFIG_DUMMY=y
-# CONFIG_BONDING is not set
-# CONFIG_EQUALIZER is not set
-# CONFIG_TUN is not set
-# CONFIG_NET_SB1000 is not set
-
-#
-# ARCnet devices
-#
-# CONFIG_ARCNET is not set
-
-#
-# PHY device support
-#
-# CONFIG_PHYLIB is not set
-
-#
-# Ethernet (10 or 100Mbit)
-#
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
-# CONFIG_HAPPYMEAL is not set
-# CONFIG_SUNGEM is not set
-# CONFIG_CASSINI is not set
-# CONFIG_NET_VENDOR_3COM is not set
-
-#
-# Tulip family network device support
-#
-# CONFIG_NET_TULIP is not set
-# CONFIG_HP100 is not set
-CONFIG_NET_PCI=y
-# CONFIG_PCNET32 is not set
-# CONFIG_AMD8111_ETH is not set
-# CONFIG_ADAPTEC_STARFIRE is not set
-# CONFIG_B44 is not set
-# CONFIG_FORCEDETH is not set
-# CONFIG_DGRS is not set
-CONFIG_EEPRO100=y
-# CONFIG_E100 is not set
-# CONFIG_FEALNX is not set
-# CONFIG_NATSEMI is not set
-# CONFIG_NE2K_PCI is not set
-# CONFIG_8139CP is not set
-# CONFIG_8139TOO is not set
-# CONFIG_SIS900 is not set
-# CONFIG_EPIC100 is not set
-# CONFIG_SUNDANCE is not set
-# CONFIG_VIA_RHINE is not set
-
-#
-# Ethernet (1000 Mbit)
-#
-# CONFIG_ACENIC is not set
-# CONFIG_DL2K is not set
-# CONFIG_E1000 is not set
-# CONFIG_NS83820 is not set
-# CONFIG_HAMACHI is not set
-# CONFIG_YELLOWFIN is not set
-# CONFIG_R8169 is not set
-# CONFIG_SIS190 is not set
-# CONFIG_SKGE is not set
-# CONFIG_SKY2 is not set
-# CONFIG_SK98LIN is not set
-# CONFIG_VIA_VELOCITY is not set
-# CONFIG_TIGON3 is not set
-# CONFIG_BNX2 is not set
-
-#
-# Ethernet (10000 Mbit)
-#
-# CONFIG_CHELSIO_T1 is not set
-# CONFIG_IXGB is not set
-# CONFIG_S2IO is not set
-
-#
-# Token Ring devices
-#
-# CONFIG_TR is not set
-
-#
-# Wireless LAN (non-hamradio)
-#
-# CONFIG_NET_RADIO is not set
-
-#
-# Wan interfaces
-#
-# CONFIG_WAN is not set
-# CONFIG_FDDI is not set
-# CONFIG_HIPPI is not set
-# CONFIG_PPP is not set
-# CONFIG_SLIP is not set
-# CONFIG_NET_FC is not set
-# CONFIG_SHAPER is not set
-# CONFIG_NETCONSOLE is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
-
-#
-# ISDN subsystem
-#
-# CONFIG_ISDN is not set
-
-#
-# Telephony Support
-#
-# CONFIG_PHONE is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-
-#
-# Userland interfaces
-#
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-# CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_EVBUG is not set
-
-#
-# Input Device Drivers
-#
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_KEYBOARD_ATKBD=y
-# CONFIG_KEYBOARD_SUNKBD is not set
-# CONFIG_KEYBOARD_LKKBD is not set
-# CONFIG_KEYBOARD_XTKBD is not set
-# CONFIG_KEYBOARD_NEWTON is not set
-CONFIG_INPUT_MOUSE=y
-CONFIG_MOUSE_PS2=y
-# CONFIG_MOUSE_SERIAL is not set
-# CONFIG_MOUSE_VSXXXAA is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TOUCHSCREEN is not set
-# CONFIG_INPUT_MISC is not set
-
-#
-# Hardware I/O ports
-#
-CONFIG_SERIO=y
-CONFIG_SERIO_I8042=y
-CONFIG_SERIO_SERPORT=y
-# CONFIG_SERIO_PCIPS2 is not set
-CONFIG_SERIO_LIBPS2=y
-# CONFIG_SERIO_RAW is not set
-# CONFIG_GAMEPORT is not set
-
-#
-# Character devices
-#
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-# CONFIG_SERIAL_NONSTANDARD is not set
-
-#
-# Serial drivers
-#
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_ACPI=y
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-# CONFIG_SERIAL_8250_DETECT_IRQ is not set
-# CONFIG_SERIAL_8250_RSA is not set
-
-#
-# Non-8250 serial port support
-#
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-# CONFIG_SERIAL_JSM is not set
-CONFIG_UNIX98_PTYS=y
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
-# CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-# CONFIG_WATCHDOG is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_EFI_RTC=y
-# CONFIG_DTLK is not set
-# CONFIG_R3964 is not set
-# CONFIG_APPLICOM is not set
-
-#
-# Ftape, the floppy tape device driver
-#
-CONFIG_AGP=m
-CONFIG_AGP_I460=m
 CONFIG_DRM=m
-# CONFIG_DRM_TDFX is not set
 CONFIG_DRM_R128=m
-# CONFIG_DRM_RADEON is not set
-# CONFIG_DRM_MGA is not set
-# CONFIG_DRM_SIS is not set
-# CONFIG_DRM_VIA is not set
-# CONFIG_DRM_SAVAGE is not set
-# CONFIG_RAW_DRIVER is not set
-# CONFIG_HPET is not set
-# CONFIG_HANGCHECK_TIMER is not set
-
-#
-# TPM devices
-#
-# CONFIG_TCG_TPM is not set
-# CONFIG_TELCLOCK is not set
-
-#
-# I2C support
-#
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-
-#
-# I2C Algorithms
-#
-CONFIG_I2C_ALGOBIT=y
-# CONFIG_I2C_ALGOPCF is not set
-# CONFIG_I2C_ALGOPCA is not set
-
-#
-# I2C Hardware Bus support
-#
-# CONFIG_I2C_ALI1535 is not set
-# CONFIG_I2C_ALI1563 is not set
-# CONFIG_I2C_ALI15X3 is not set
-# CONFIG_I2C_AMD756 is not set
-# CONFIG_I2C_AMD8111 is not set
-# CONFIG_I2C_I801 is not set
-# CONFIG_I2C_I810 is not set
-# CONFIG_I2C_PIIX4 is not set
-# CONFIG_I2C_NFORCE2 is not set
-# CONFIG_I2C_PARPORT_LIGHT is not set
-# CONFIG_I2C_PROSAVAGE is not set
-# CONFIG_I2C_SAVAGE4 is not set
-# CONFIG_SCx200_ACB is not set
-# CONFIG_I2C_SIS5595 is not set
-# CONFIG_I2C_SIS630 is not set
-# CONFIG_I2C_SIS96X is not set
-# CONFIG_I2C_STUB is not set
-# CONFIG_I2C_VIA is not set
-# CONFIG_I2C_VIAPRO is not set
-# CONFIG_I2C_VOODOO3 is not set
-# CONFIG_I2C_PCA_ISA is not set
-
-#
-# Miscellaneous I2C Chip support
-#
-# CONFIG_SENSORS_DS1337 is not set
-# CONFIG_SENSORS_DS1374 is not set
-# CONFIG_EEPROM_LEGACY is not set
-# CONFIG_SENSORS_PCF8574 is not set
-# CONFIG_SENSORS_PCA9539 is not set
-# CONFIG_SENSORS_PCF8591 is not set
-# CONFIG_SENSORS_RTC8564 is not set
-# CONFIG_SENSORS_MAX6875 is not set
-# CONFIG_RTC_X1205_I2C is not set
-# CONFIG_I2C_DEBUG_CORE is not set
-# CONFIG_I2C_DEBUG_ALGO is not set
-# CONFIG_I2C_DEBUG_BUS is not set
-# CONFIG_I2C_DEBUG_CHIP is not set
-
-#
-# SPI support
-#
-# CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
-
-#
-# Dallas's 1-wire bus
-#
-# CONFIG_W1 is not set
-
-#
-# Hardware Monitoring support
-#
-CONFIG_HWMON=y
-# CONFIG_HWMON_VID is not set
-# CONFIG_SENSORS_ADM1021 is not set
-# CONFIG_SENSORS_ADM1025 is not set
-# CONFIG_SENSORS_ADM1026 is not set
-# CONFIG_SENSORS_ADM1031 is not set
-# CONFIG_SENSORS_ADM9240 is not set
-# CONFIG_SENSORS_ASB100 is not set
-# CONFIG_SENSORS_ATXP1 is not set
-# CONFIG_SENSORS_DS1621 is not set
-# CONFIG_SENSORS_F71805F is not set
-# CONFIG_SENSORS_FSCHER is not set
-# CONFIG_SENSORS_FSCPOS is not set
-# CONFIG_SENSORS_GL518SM is not set
-# CONFIG_SENSORS_GL520SM is not set
-# CONFIG_SENSORS_IT87 is not set
-# CONFIG_SENSORS_LM63 is not set
-# CONFIG_SENSORS_LM75 is not set
-# CONFIG_SENSORS_LM77 is not set
-# CONFIG_SENSORS_LM78 is not set
-# CONFIG_SENSORS_LM80 is not set
-# CONFIG_SENSORS_LM83 is not set
-# CONFIG_SENSORS_LM85 is not set
-# CONFIG_SENSORS_LM87 is not set
-# CONFIG_SENSORS_LM90 is not set
-# CONFIG_SENSORS_LM92 is not set
-# CONFIG_SENSORS_MAX1619 is not set
-# CONFIG_SENSORS_PC87360 is not set
-# CONFIG_SENSORS_SIS5595 is not set
-# CONFIG_SENSORS_SMSC47M1 is not set
-# CONFIG_SENSORS_SMSC47B397 is not set
-# CONFIG_SENSORS_VIA686A is not set
-# CONFIG_SENSORS_VT8231 is not set
-# CONFIG_SENSORS_W83781D is not set
-# CONFIG_SENSORS_W83792D is not set
-# CONFIG_SENSORS_W83L785TS is not set
-# CONFIG_SENSORS_W83627HF is not set
-# CONFIG_SENSORS_W83627EHF is not set
-# CONFIG_HWMON_DEBUG_CHIP is not set
-
-#
-# Misc devices
-#
-
-#
-# Multimedia Capabilities Port drivers
-#
-
-#
-# Multimedia devices
-#
-# CONFIG_VIDEO_DEV is not set
-
-#
-# Digital Video Broadcasting Devices
-#
-# CONFIG_DVB is not set
-
-#
-# Graphics support
-#
-# CONFIG_FB is not set
-
-#
-# Console display driver support
-#
-CONFIG_VGA_CONSOLE=y
-CONFIG_DUMMY_CONSOLE=y
-
-#
-# Sound
-#
-CONFIG_SOUND=m
-
-#
-# Advanced Linux Sound Architecture
-#
-CONFIG_SND=m
-CONFIG_SND_TIMER=m
-CONFIG_SND_PCM=m
-CONFIG_SND_HWDEP=m
-CONFIG_SND_RAWMIDI=m
-CONFIG_SND_SEQUENCER=m
-# CONFIG_SND_SEQ_DUMMY is not set
-CONFIG_SND_OSSEMUL=y
-CONFIG_SND_MIXER_OSS=m
-CONFIG_SND_PCM_OSS=m
-# CONFIG_SND_SEQUENCER_OSS is not set
-# CONFIG_SND_DYNAMIC_MINORS is not set
-CONFIG_SND_SUPPORT_OLD_API=y
-# CONFIG_SND_VERBOSE_PRINTK is not set
-# CONFIG_SND_DEBUG is not set
-
-#
-# Generic devices
-#
-CONFIG_SND_OPL3_LIB=m
-CONFIG_SND_AC97_CODEC=m
-CONFIG_SND_AC97_BUS=m
-# CONFIG_SND_DUMMY is not set
-# CONFIG_SND_VIRMIDI is not set
-# CONFIG_SND_MTPAV is not set
-# CONFIG_SND_SERIAL_U16550 is not set
-# CONFIG_SND_MPU401 is not set
-
-#
-# PCI devices
-#
-# CONFIG_SND_AD1889 is not set
-# CONFIG_SND_ALI5451 is not set
-# CONFIG_SND_ATIIXP is not set
-# CONFIG_SND_ATIIXP_MODEM is not set
-# CONFIG_SND_AU8810 is not set
-# CONFIG_SND_AU8820 is not set
-# CONFIG_SND_AU8830 is not set
-# CONFIG_SND_AZT3328 is not set
-# CONFIG_SND_BT87X is not set
-# CONFIG_SND_CA0106 is not set
-# CONFIG_SND_CMIPCI is not set
-CONFIG_SND_CS4281=m
-# CONFIG_SND_CS46XX is not set
-# CONFIG_SND_EMU10K1 is not set
-# CONFIG_SND_EMU10K1X is not set
-# CONFIG_SND_ENS1370 is not set
-# CONFIG_SND_ENS1371 is not set
-# CONFIG_SND_ES1938 is not set
-# CONFIG_SND_ES1968 is not set
-# CONFIG_SND_FM801 is not set
-# CONFIG_SND_HDA_INTEL is not set
-# CONFIG_SND_HDSP is not set
-# CONFIG_SND_HDSPM is not set
-# CONFIG_SND_ICE1712 is not set
-# CONFIG_SND_ICE1724 is not set
-# CONFIG_SND_INTEL8X0 is not set
-# CONFIG_SND_INTEL8X0M is not set
-# CONFIG_SND_KORG1212 is not set
-# CONFIG_SND_MAESTRO3 is not set
-# CONFIG_SND_MIXART is not set
-# CONFIG_SND_NM256 is not set
-# CONFIG_SND_PCXHR is not set
-# CONFIG_SND_RME32 is not set
-# CONFIG_SND_RME96 is not set
-# CONFIG_SND_RME9652 is not set
-# CONFIG_SND_SONICVIBES is not set
-# CONFIG_SND_TRIDENT is not set
-# CONFIG_SND_VIA82XX is not set
-# CONFIG_SND_VIA82XX_MODEM is not set
-# CONFIG_SND_VX222 is not set
-# CONFIG_SND_YMFPCI is not set
-
-#
-# USB devices
-#
-# CONFIG_SND_USB_AUDIO is not set
-
-#
-# Open Sound System
-#
-# CONFIG_SOUND_PRIME is not set
-
-#
-# USB support
-#
-CONFIG_USB_ARCH_HAS_HCD=y
-CONFIG_USB_ARCH_HAS_OHCI=y
-CONFIG_USB=m
-# CONFIG_USB_DEBUG is not set
-
-#
-# Miscellaneous USB options
-#
-CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_BANDWIDTH is not set
-# CONFIG_USB_DYNAMIC_MINORS is not set
-# CONFIG_USB_SUSPEND is not set
-# CONFIG_USB_OTG is not set
-
-#
-# USB Host Controller Drivers
-#
-# CONFIG_USB_EHCI_HCD is not set
-# CONFIG_USB_ISP116X_HCD is not set
-# CONFIG_USB_OHCI_HCD is not set
-CONFIG_USB_UHCI_HCD=m
-# CONFIG_USB_SL811_HCD is not set
-
-#
-# USB Device Class drivers
-#
-# CONFIG_OBSOLETE_OSS_USB_DRIVER is not set
-CONFIG_USB_ACM=m
-CONFIG_USB_PRINTER=m
-
-#
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
-#
-
-#
-# may also be needed; see USB_STORAGE Help for more information
-#
-CONFIG_USB_STORAGE=m
-# CONFIG_USB_STORAGE_DEBUG is not set
-# CONFIG_USB_STORAGE_DATAFAB is not set
-# CONFIG_USB_STORAGE_FREECOM is not set
-# CONFIG_USB_STORAGE_ISD200 is not set
-# CONFIG_USB_STORAGE_DPCM is not set
-# CONFIG_USB_STORAGE_USBAT is not set
-# CONFIG_USB_STORAGE_SDDR09 is not set
-# CONFIG_USB_STORAGE_SDDR55 is not set
-# CONFIG_USB_STORAGE_JUMPSHOT is not set
-# CONFIG_USB_STORAGE_ALAUDA is not set
-# CONFIG_USB_LIBUSUAL is not set
-
-#
-# USB Input Devices
-#
-CONFIG_USB_HID=m
-CONFIG_USB_HIDINPUT=y
-# CONFIG_USB_HIDINPUT_POWERBOOK is not set
-# CONFIG_HID_FF is not set
-CONFIG_USB_HIDDEV=y
-
-#
-# USB HID Boot Protocol drivers
-#
-# CONFIG_USB_KBD is not set
-# CONFIG_USB_MOUSE is not set
-# CONFIG_USB_AIPTEK is not set
-# CONFIG_USB_WACOM is not set
-# CONFIG_USB_ACECAD is not set
-# CONFIG_USB_KBTAB is not set
-# CONFIG_USB_POWERMATE is not set
-# CONFIG_USB_MTOUCH is not set
-# CONFIG_USB_ITMTOUCH is not set
-# CONFIG_USB_EGALAX is not set
-# CONFIG_USB_YEALINK is not set
-# CONFIG_USB_XPAD is not set
-# CONFIG_USB_ATI_REMOTE is not set
-# CONFIG_USB_ATI_REMOTE2 is not set
-# CONFIG_USB_KEYSPAN_REMOTE is not set
-# CONFIG_USB_APPLETOUCH is not set
-
-#
-# USB Imaging devices
-#
-# CONFIG_USB_MDC800 is not set
-# CONFIG_USB_MICROTEK is not set
-
-#
-# USB Multimedia devices
-#
-# CONFIG_USB_DABUSB is not set
-
-#
-# Video4Linux support is needed for USB Multimedia device support
-#
-
-#
-# USB Network Adapters
-#
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_RTL8150 is not set
-# CONFIG_USB_USBNET is not set
-CONFIG_USB_MON=y
-
-#
-# USB port drivers
-#
-
-#
-# USB Serial Converter support
-#
-# CONFIG_USB_SERIAL is not set
-
-#
-# USB Miscellaneous drivers
-#
-# CONFIG_USB_EMI62 is not set
-# CONFIG_USB_EMI26 is not set
-# CONFIG_USB_AUERSWALD is not set
-# CONFIG_USB_RIO500 is not set
-# CONFIG_USB_LEGOTOWER is not set
-# CONFIG_USB_LCD is not set
-# CONFIG_USB_LED is not set
-# CONFIG_USB_CYTHERM is not set
-# CONFIG_USB_PHIDGETKIT is not set
-# CONFIG_USB_PHIDGETSERVO is not set
-# CONFIG_USB_IDMOUSE is not set
-# CONFIG_USB_LD is not set
-# CONFIG_USB_TEST is not set
-
-#
-# USB DSL modem support
-#
-
-#
-# USB Gadget Support
-#
-# CONFIG_USB_GADGET is not set
-
-#
-# MMC/SD Card support
-#
-# CONFIG_MMC is not set
-
-#
-# InfiniBand support
-#
-# CONFIG_INFINIBAND is not set
-
-#
-# EDAC - error detection and reporting (RAS)
-#
-
-#
-# File systems
-#
+CONFIG_DUMMY=y
+CONFIG_EFI_PARTITION=y
+CONFIG_EFI_RTC=y
+CONFIG_EFI_VARS=y
+CONFIG_EXPERIMENTAL=y
 CONFIG_EXT2_FS=y
-# CONFIG_EXT2_FS_XATTR is not set
-# CONFIG_EXT2_FS_XIP is not set
 CONFIG_EXT3_FS=y
-CONFIG_EXT3_FS_XATTR=y
-# CONFIG_EXT3_FS_POSIX_ACL is not set
-# CONFIG_EXT3_FS_SECURITY is not set
-CONFIG_JBD=y
-# CONFIG_JBD_DEBUG is not set
-CONFIG_FS_MBCACHE=y
-# CONFIG_REISERFS_FS is not set
-# CONFIG_JFS_FS is not set
-CONFIG_FS_POSIX_ACL=y
-CONFIG_XFS_FS=y
-CONFIG_XFS_EXPORT=y
-CONFIG_XFS_QUOTA=y
-CONFIG_XFS_SECURITY=y
-CONFIG_XFS_POSIX_ACL=y
-# CONFIG_XFS_RT is not set
-# CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
+CONFIG_HUGETLBFS=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C=y
+CONFIG_IA64_DIG=y
+CONFIG_IA64_PALINFO=y
+CONFIG_IDE=m
+CONFIG_INET=y
 CONFIG_INOTIFY=y
-# CONFIG_QUOTA is not set
-CONFIG_QUOTACTL=y
-CONFIG_DNOTIFY=y
-CONFIG_AUTOFS_FS=m
-CONFIG_AUTOFS4_FS=m
-# CONFIG_FUSE_FS is not set
-
-#
-# CD-ROM/DVD Filesystems
-#
+CONFIG_INPUT_EVDEV=y
+# CONFIG_IPV6 is not set
 CONFIG_ISO9660_FS=m
 CONFIG_JOLIET=y
-# CONFIG_ZISOFS is not set
-CONFIG_UDF_FS=m
-CONFIG_UDF_NLS=y
-
-#
-# DOS/FAT/NT Filesystems
-#
-CONFIG_FAT_FS=y
-# CONFIG_MSDOS_FS is not set
-CONFIG_VFAT_FS=y
-CONFIG_FAT_DEFAULT_CODEPAGE=437
-CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-# CONFIG_NTFS_FS is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_KCORE=y
-CONFIG_SYSFS=y
-CONFIG_TMPFS=y
-CONFIG_HUGETLBFS=y
-CONFIG_HUGETLB_PAGE=y
-CONFIG_RAMFS=y
-# CONFIG_RELAYFS_FS is not set
-# CONFIG_CONFIGFS_FS is not set
-
-#
-# Miscellaneous filesystems
-#
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-# CONFIG_CRAMFS is not set
-# CONFIG_VXFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
+CONFIG_LOG_BUF_SHIFT=16
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MD_LINEAR=m
+CONFIG_MD_MULTIPATH=m
+CONFIG_MD_RAID0=m
+CONFIG_MD_RAID10=m
+CONFIG_MD_RAID1=m
+CONFIG_MD=y
+CONFIG_MII=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_NETDEVICES=y
+CONFIG_NET_ETHERNET=y
+CONFIG_NET_PCI=y
+CONFIG_NET=y
+CONFIG_NFSD=m
+CONFIG_NFSD_V4=y
 CONFIG_NFS_FS=m
 CONFIG_NFS_V3=y
-# CONFIG_NFS_V3_ACL is not set
 CONFIG_NFS_V4=y
-# CONFIG_NFS_DIRECTIO is not set
-CONFIG_NFSD=m
-CONFIG_NFSD_V3=y
-# CONFIG_NFSD_V3_ACL is not set
-CONFIG_NFSD_V4=y
-CONFIG_NFSD_TCP=y
-CONFIG_LOCKD=m
-CONFIG_LOCKD_V4=y
-CONFIG_EXPORTFS=y
-CONFIG_NFS_COMMON=y
-CONFIG_SUNRPC=m
-CONFIG_SUNRPC_GSS=m
-CONFIG_RPCSEC_GSS_KRB5=m
-# CONFIG_RPCSEC_GSS_SPKM3 is not set
-# CONFIG_SMB_FS is not set
-CONFIG_CIFS=m
-CONFIG_CIFS_STATS=y
-# CONFIG_CIFS_STATS2 is not set
-CONFIG_CIFS_XATTR=y
-CONFIG_CIFS_POSIX=y
-# CONFIG_CIFS_EXPERIMENTAL is not set
-# CONFIG_NCP_FS is not set
-# CONFIG_CODA_FS is not set
-# CONFIG_AFS_FS is not set
-# CONFIG_9P_FS is not set
-
-#
-# Partition Types
-#
-CONFIG_PARTITION_ADVANCED=y
-# CONFIG_ACORN_PARTITION is not set
-# CONFIG_OSF_PARTITION is not set
-# CONFIG_AMIGA_PARTITION is not set
-# CONFIG_ATARI_PARTITION is not set
-# CONFIG_MAC_PARTITION is not set
-CONFIG_MSDOS_PARTITION=y
-# CONFIG_BSD_DISKLABEL is not set
-# CONFIG_MINIX_SUBPARTITION is not set
-# CONFIG_SOLARIS_X86_PARTITION is not set
-# CONFIG_UNIXWARE_DISKLABEL is not set
-# CONFIG_LDM_PARTITION is not set
-CONFIG_SGI_PARTITION=y
-# CONFIG_ULTRIX_PARTITION is not set
-# CONFIG_SUN_PARTITION is not set
-# CONFIG_KARMA_PARTITION is not set
-CONFIG_EFI_PARTITION=y
-
-#
-# Native Language Support
-#
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="iso8859-1"
 CONFIG_NLS_CODEPAGE_437=y
-# CONFIG_NLS_CODEPAGE_737 is not set
-# CONFIG_NLS_CODEPAGE_775 is not set
-# CONFIG_NLS_CODEPAGE_850 is not set
-# CONFIG_NLS_CODEPAGE_852 is not set
-# CONFIG_NLS_CODEPAGE_855 is not set
-# CONFIG_NLS_CODEPAGE_857 is not set
-# CONFIG_NLS_CODEPAGE_860 is not set
-# CONFIG_NLS_CODEPAGE_861 is not set
-# CONFIG_NLS_CODEPAGE_862 is not set
-# CONFIG_NLS_CODEPAGE_863 is not set
-# CONFIG_NLS_CODEPAGE_864 is not set
-# CONFIG_NLS_CODEPAGE_865 is not set
-# CONFIG_NLS_CODEPAGE_866 is not set
-# CONFIG_NLS_CODEPAGE_869 is not set
-# CONFIG_NLS_CODEPAGE_936 is not set
-# CONFIG_NLS_CODEPAGE_950 is not set
-# CONFIG_NLS_CODEPAGE_932 is not set
-# CONFIG_NLS_CODEPAGE_949 is not set
-# CONFIG_NLS_CODEPAGE_874 is not set
-# CONFIG_NLS_ISO8859_8 is not set
-# CONFIG_NLS_CODEPAGE_1250 is not set
-# CONFIG_NLS_CODEPAGE_1251 is not set
-# CONFIG_NLS_ASCII is not set
 CONFIG_NLS_ISO8859_1=y
-# CONFIG_NLS_ISO8859_2 is not set
-# CONFIG_NLS_ISO8859_3 is not set
-# CONFIG_NLS_ISO8859_4 is not set
-# CONFIG_NLS_ISO8859_5 is not set
-# CONFIG_NLS_ISO8859_6 is not set
-# CONFIG_NLS_ISO8859_7 is not set
-# CONFIG_NLS_ISO8859_9 is not set
-# CONFIG_NLS_ISO8859_13 is not set
-# CONFIG_NLS_ISO8859_14 is not set
-# CONFIG_NLS_ISO8859_15 is not set
-# CONFIG_NLS_KOI8_R is not set
-# CONFIG_NLS_KOI8_U is not set
 CONFIG_NLS_UTF8=m
-
-#
-# Library routines
-#
-# CONFIG_CRC_CCITT is not set
-# CONFIG_CRC16 is not set
-CONFIG_CRC32=y
-# CONFIG_LIBCRC32C is not set
-CONFIG_GENERIC_HARDIRQS=y
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_GENERIC_PENDING_IRQ=y
-
-#
-# Instrumentation Support
-#
-CONFIG_PROFILING=y
+CONFIG_NR_CPUS=2
 CONFIG_OPROFILE=y
-# CONFIG_KPROBES is not set
-
-#
-# Kernel hacking
-#
-# CONFIG_PRINTK_TIME is not set
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_LOG_BUF_SHIFT=16
-CONFIG_DETECT_SOFTLOCKUP=y
-# CONFIG_SCHEDSTATS is not set
-# CONFIG_DEBUG_SLAB is not set
-CONFIG_DEBUG_PREEMPT=y
-CONFIG_DEBUG_MUTEXES=y
-# CONFIG_DEBUG_SPINLOCK is not set
-# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-# CONFIG_DEBUG_KOBJECT is not set
-# CONFIG_DEBUG_INFO is not set
-# CONFIG_DEBUG_FS is not set
-# CONFIG_DEBUG_VM is not set
-CONFIG_FORCED_INLINING=y
-# CONFIG_RCU_TORTURE_TEST is not set
-# CONFIG_IA64_GRANULE_16MB is not set
-CONFIG_IA64_GRANULE_64MB=y
-# CONFIG_IA64_PRINT_HAZARDS is not set
-# CONFIG_DISABLE_VHPT is not set
-# CONFIG_IA64_DEBUG_CMPXCHG is not set
-# CONFIG_IA64_DEBUG_IRQ is not set
-CONFIG_SYSVIPC_COMPAT=y
-
-#
-# Security options
-#
-# CONFIG_KEYS is not set
-# CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_HMAC is not set
-# CONFIG_CRYPTO_NULL is not set
-# CONFIG_CRYPTO_MD4 is not set
-CONFIG_CRYPTO_MD5=y
-# CONFIG_CRYPTO_SHA1 is not set
-# CONFIG_CRYPTO_SHA256 is not set
-# CONFIG_CRYPTO_SHA512 is not set
-# CONFIG_CRYPTO_WP512 is not set
-# CONFIG_CRYPTO_TGR192 is not set
-CONFIG_CRYPTO_DES=y
-# CONFIG_CRYPTO_BLOWFISH is not set
-# CONFIG_CRYPTO_TWOFISH is not set
-# CONFIG_CRYPTO_SERPENT is not set
-# CONFIG_CRYPTO_AES is not set
-# CONFIG_CRYPTO_CAST5 is not set
-# CONFIG_CRYPTO_CAST6 is not set
-# CONFIG_CRYPTO_TEA is not set
-# CONFIG_CRYPTO_ARC4 is not set
-# CONFIG_CRYPTO_KHAZAD is not set
-# CONFIG_CRYPTO_ANUBIS is not set
-# CONFIG_CRYPTO_DEFLATE is not set
-# CONFIG_CRYPTO_MICHAEL_MIC is not set
-# CONFIG_CRYPTO_CRC32C is not set
-# CONFIG_CRYPTO_TEST is not set
-
-#
-# Hardware crypto devices
-#
+CONFIG_PACKET=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_PERFMON=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_PREEMPT=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROFILING=y
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_LOGGING=y
+CONFIG_SCSI_QLOGIC_1280=y
+CONFIG_SCSI_SPI_ATTRS=m
+CONFIG_SCSI=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250=y
+CONFIG_SGI_PARTITION=y
+CONFIG_SMP=y
+CONFIG_SND_CS4281=m
+CONFIG_SND=m
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_PCM_OSS=m
+CONFIG_SND_SEQUENCER=m
+CONFIG_SOUND=m
+CONFIG_SYSVIPC=y
+CONFIG_TMPFS=y
+CONFIG_UDF_FS=m
+CONFIG_UNIX=y
+CONFIG_USB_ACM=m
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_HIDDEV=y
+CONFIG_USB=m
+CONFIG_USB_MON=m
+CONFIG_USB_PRINTER=m
+CONFIG_USB_STORAGE=m
+CONFIG_USB_UHCI_HCD=m
+CONFIG_VFAT_FS=y
+# CONFIG_VIRTUAL_MEM_MAP is not set
+CONFIG_XFS_FS=y
+CONFIG_XFS_POSIX_ACL=y
+CONFIG_XFS_QUOTA=y
diff --git a/arch/ia64/configs/generic_defconfig b/arch/ia64/configs/generic_defconfig
index 6a4cc506fb5f..01ba5305e98c 100644
--- a/arch/ia64/configs/generic_defconfig
+++ b/arch/ia64/configs/generic_defconfig
@@ -1,1455 +1,133 @@
-#
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.28-rc7
-# Mon Dec  8 08:12:07 2008
-#
-CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-
-#
-# General setup
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_LOCK_KERNEL=y
-CONFIG_INIT_ENV_ARG_LIMIT=32
-CONFIG_LOCALVERSION=""
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-CONFIG_SYSVIPC_SYSCTL=y
-CONFIG_POSIX_MQUEUE=y
-# CONFIG_BSD_PROCESS_ACCT is not set
-# CONFIG_TASKSTATS is not set
-# CONFIG_AUDIT is not set
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=20
-CONFIG_CGROUPS=y
-# CONFIG_CGROUP_DEBUG is not set
-# CONFIG_CGROUP_NS is not set
-# CONFIG_CGROUP_FREEZER is not set
-# CONFIG_CGROUP_DEVICE is not set
-CONFIG_CPUSETS=y
-# CONFIG_GROUP_SCHED is not set
-# CONFIG_CGROUP_CPUACCT is not set
-# CONFIG_RESOURCE_COUNTERS is not set
-CONFIG_SYSFS_DEPRECATED=y
-CONFIG_SYSFS_DEPRECATED_V2=y
-CONFIG_PROC_PID_CPUSET=y
-# CONFIG_RELAY is not set
-CONFIG_NAMESPACES=y
-# CONFIG_UTS_NS is not set
-# CONFIG_IPC_NS is not set
-# CONFIG_USER_NS is not set
-# CONFIG_PID_NS is not set
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_SYSCTL=y
-# CONFIG_EMBEDDED is not set
-CONFIG_SYSCTL_SYSCALL=y
-CONFIG_KALLSYMS=y
-CONFIG_KALLSYMS_ALL=y
-# CONFIG_KALLSYMS_EXTRA_PASS is not set
-CONFIG_HOTPLUG=y
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-CONFIG_COMPAT_BRK=y
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_ANON_INODES=y
-CONFIG_EPOLL=y
-CONFIG_SIGNALFD=y
-CONFIG_TIMERFD=y
-CONFIG_EVENTFD=y
-CONFIG_SHMEM=y
-CONFIG_AIO=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_PCI_QUIRKS=y
-CONFIG_SLUB_DEBUG=y
-# CONFIG_SLAB is not set
-CONFIG_SLUB=y
-# CONFIG_SLOB is not set
-# CONFIG_PROFILING is not set
-# CONFIG_MARKERS is not set
-CONFIG_HAVE_OPROFILE=y
-# CONFIG_KPROBES is not set
-CONFIG_HAVE_KPROBES=y
-CONFIG_HAVE_KRETPROBES=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_USE_GENERIC_SMP_HELPERS=y
-# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
-CONFIG_SLABINFO=y
-CONFIG_RT_MUTEXES=y
-# CONFIG_TINY_SHMEM is not set
-CONFIG_BASE_SMALL=0
-CONFIG_MODULES=y
-# CONFIG_MODULE_FORCE_LOAD is not set
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_MODULE_FORCE_UNLOAD is not set
-CONFIG_MODVERSIONS=y
-# CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_KMOD=y
-CONFIG_STOP_MACHINE=y
-CONFIG_BLOCK=y
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_BLK_DEV_INTEGRITY is not set
-CONFIG_BLOCK_COMPAT=y
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-CONFIG_DEFAULT_AS=y
-# CONFIG_DEFAULT_DEADLINE is not set
-# CONFIG_DEFAULT_CFQ is not set
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="anticipatory"
-CONFIG_CLASSIC_RCU=y
-# CONFIG_FREEZER is not set
-
-#
-# Processor type and features
-#
-CONFIG_IA64=y
-CONFIG_64BIT=y
-CONFIG_ZONE_DMA=y
-CONFIG_QUICKLIST=y
-CONFIG_MMU=y
-CONFIG_SWIOTLB=y
-CONFIG_IOMMU_HELPER=y
-CONFIG_RWSEM_XCHGADD_ALGORITHM=y
-CONFIG_HUGETLB_PAGE_SIZE_VARIABLE=y
-CONFIG_GENERIC_FIND_NEXT_BIT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_GENERIC_TIME=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_HAVE_SETUP_PER_CPU_AREA=y
-CONFIG_DMI=y
-CONFIG_EFI=y
-CONFIG_GENERIC_IOMAP=y
-CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
-CONFIG_IA64_UNCACHED_ALLOCATOR=y
-CONFIG_AUDIT_ARCH=y
-# CONFIG_PARAVIRT_GUEST is not set
-CONFIG_IA64_GENERIC=y
-# CONFIG_IA64_DIG is not set
-# CONFIG_IA64_DIG_VTD is not set
-# CONFIG_IA64_HP_ZX1 is not set
-# CONFIG_IA64_HP_ZX1_SWIOTLB is not set
-# CONFIG_IA64_SGI_SN2 is not set
-# CONFIG_IA64_SGI_UV is not set
-# CONFIG_IA64_HP_SIM is not set
-# CONFIG_IA64_XEN_GUEST is not set
-# CONFIG_ITANIUM is not set
-CONFIG_MCKINLEY=y
-# CONFIG_IA64_PAGE_SIZE_4KB is not set
-# CONFIG_IA64_PAGE_SIZE_8KB is not set
-# CONFIG_IA64_PAGE_SIZE_16KB is not set
-CONFIG_IA64_PAGE_SIZE_64KB=y
-CONFIG_PGTABLE_3=y
-# CONFIG_PGTABLE_4 is not set
-CONFIG_HZ=250
-# CONFIG_HZ_100 is not set
-CONFIG_HZ_250=y
-# CONFIG_HZ_300 is not set
-# CONFIG_HZ_1000 is not set
-# CONFIG_SCHED_HRTICK is not set
-CONFIG_IA64_L1_CACHE_SHIFT=7
-CONFIG_IA64_CYCLONE=y
-CONFIG_IOSAPIC=y
-CONFIG_FORCE_MAX_ZONEORDER=17
-# CONFIG_VIRT_CPU_ACCOUNTING is not set
-CONFIG_SMP=y
-CONFIG_NR_CPUS=4096
-CONFIG_HOTPLUG_CPU=y
-CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
-CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
-# CONFIG_SCHED_SMT is not set
-# CONFIG_PERMIT_BSP_REMOVE is not set
-CONFIG_PREEMPT_NONE=y
-# CONFIG_PREEMPT_VOLUNTARY is not set
-# CONFIG_PREEMPT is not set
-CONFIG_SELECT_MEMORY_MODEL=y
-# CONFIG_FLATMEM_MANUAL is not set
-CONFIG_DISCONTIGMEM_MANUAL=y
-# CONFIG_SPARSEMEM_MANUAL is not set
-CONFIG_DISCONTIGMEM=y
-CONFIG_FLAT_NODE_MEM_MAP=y
-CONFIG_NEED_MULTIPLE_NODES=y
-CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_SPLIT_PTLOCK_CPUS=4
-CONFIG_MIGRATION=y
-CONFIG_RESOURCES_64BIT=y
-CONFIG_PHYS_ADDR_T_64BIT=y
-CONFIG_ZONE_DMA_FLAG=1
-CONFIG_BOUNCE=y
-CONFIG_NR_QUICK=1
-CONFIG_VIRT_TO_BUS=y
-CONFIG_UNEVICTABLE_LRU=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
-CONFIG_ARCH_FLATMEM_ENABLE=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_DISCONTIGMEM_DEFAULT=y
-CONFIG_NUMA=y
-CONFIG_NODES_SHIFT=10
-CONFIG_ARCH_POPULATES_NODE_MAP=y
-CONFIG_VIRTUAL_MEM_MAP=y
-CONFIG_HOLES_IN_ZONE=y
-CONFIG_HAVE_ARCH_EARLY_PFN_TO_NID=y
-CONFIG_HAVE_ARCH_NODEDATA_EXTENSION=y
-CONFIG_COMPAT_FOR_U64_ALIGNMENT=y
-CONFIG_IA64_MCA_RECOVERY=y
-CONFIG_PERFMON=y
-CONFIG_IA64_PALINFO=y
-# CONFIG_IA64_MC_ERR_INJECT is not set
-CONFIG_SGI_SN=y
-# CONFIG_IA64_ESI is not set
-# CONFIG_IA64_HP_AML_NFW is not set
-
-#
-# SN Devices
-#
-CONFIG_SGI_IOC3=m
-CONFIG_KEXEC=y
-CONFIG_CRASH_DUMP=y
-
-#
-# Firmware Drivers
-#
-# CONFIG_FIRMWARE_MEMMAP is not set
-CONFIG_EFI_VARS=y
-CONFIG_EFI_PCDP=y
-CONFIG_DMIID=y
-CONFIG_BINFMT_ELF=y
-# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-# CONFIG_HAVE_AOUT is not set
-CONFIG_BINFMT_MISC=m
-
-#
-# Power management and ACPI options
-#
-CONFIG_PM=y
-# CONFIG_PM_DEBUG is not set
-CONFIG_ACPI=y
-CONFIG_ACPI_PROCFS=y
-CONFIG_ACPI_PROCFS_POWER=y
-CONFIG_ACPI_SYSFS_POWER=y
-CONFIG_ACPI_PROC_EVENT=y
 CONFIG_ACPI_BUTTON=m
-CONFIG_ACPI_FAN=m
+CONFIG_ACPI_CONTAINER=m
 CONFIG_ACPI_DOCK=y
+CONFIG_ACPI_FAN=m
 CONFIG_ACPI_PROCESSOR=m
-CONFIG_ACPI_HOTPLUG_CPU=y
-CONFIG_ACPI_THERMAL=m
-CONFIG_ACPI_NUMA=y
-# CONFIG_ACPI_CUSTOM_DSDT is not set
-CONFIG_ACPI_BLACKLIST_YEAR=0
-# CONFIG_ACPI_DEBUG is not set
-# CONFIG_ACPI_PCI_SLOT is not set
-CONFIG_ACPI_SYSTEM=y
-CONFIG_ACPI_CONTAINER=m
-
-#
-# CPU Frequency scaling
-#
-# CONFIG_CPU_FREQ is not set
-
-#
-# Bus options (PCI, PCMCIA)
-#
-CONFIG_PCI=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_SYSCALL=y
-# CONFIG_PCIEPORTBUS is not set
-CONFIG_ARCH_SUPPORTS_MSI=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_LEGACY=y
-# CONFIG_PCI_DEBUG is not set
-CONFIG_HOTPLUG_PCI=m
-# CONFIG_HOTPLUG_PCI_FAKE is not set
-CONFIG_HOTPLUG_PCI_ACPI=m
-# CONFIG_HOTPLUG_PCI_ACPI_IBM is not set
-# CONFIG_HOTPLUG_PCI_CPCI is not set
-# CONFIG_HOTPLUG_PCI_SHPC is not set
-# CONFIG_HOTPLUG_PCI_SGI is not set
-# CONFIG_PCCARD is not set
-CONFIG_DMAR=y
-CONFIG_NET=y
-
-#
-# Networking options
-#
-CONFIG_PACKET=y
-# CONFIG_PACKET_MMAP is not set
-CONFIG_UNIX=y
-CONFIG_XFRM=y
-# CONFIG_XFRM_USER is not set
-# CONFIG_XFRM_SUB_POLICY is not set
-# CONFIG_XFRM_MIGRATE is not set
-# CONFIG_XFRM_STATISTICS is not set
-# CONFIG_NET_KEY is not set
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_FIB_HASH=y
-# CONFIG_IP_PNP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_IP_MROUTE is not set
+CONFIG_ACPI_PROCFS=y
+CONFIG_AGP_HP_ZX1=m
+CONFIG_AGP_I460=m
+CONFIG_AGP=m
+CONFIG_AGP_SGI_TIOCA=m
 CONFIG_ARPD=y
-CONFIG_SYN_COOKIES=y
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_XFRM_TUNNEL is not set
-# CONFIG_INET_TUNNEL is not set
-CONFIG_INET_XFRM_MODE_TRANSPORT=y
-CONFIG_INET_XFRM_MODE_TUNNEL=y
-CONFIG_INET_XFRM_MODE_BEET=y
-CONFIG_INET_LRO=m
-CONFIG_INET_DIAG=y
-CONFIG_INET_TCP_DIAG=y
-# CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TCP_CONG_CUBIC=y
-CONFIG_DEFAULT_TCP_CONG="cubic"
-# CONFIG_TCP_MD5SIG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_NETWORK_SECMARK is not set
-# CONFIG_NETFILTER is not set
-# CONFIG_IP_DCCP is not set
-# CONFIG_IP_SCTP is not set
-# CONFIG_TIPC is not set
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_NET_DSA is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-# CONFIG_NET_SCHED is not set
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_HAMRADIO is not set
-# CONFIG_CAN is not set
-# CONFIG_IRDA is not set
-# CONFIG_BT is not set
-# CONFIG_AF_RXRPC is not set
-# CONFIG_PHONET is not set
-CONFIG_WIRELESS=y
-# CONFIG_CFG80211 is not set
-CONFIG_WIRELESS_OLD_REGULATORY=y
-# CONFIG_WIRELESS_EXT is not set
-# CONFIG_MAC80211 is not set
-# CONFIG_IEEE80211 is not set
-# CONFIG_RFKILL is not set
-# CONFIG_NET_9P is not set
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=y
-CONFIG_FIRMWARE_IN_KERNEL=y
-CONFIG_EXTRA_FIRMWARE=""
-# CONFIG_DEBUG_DRIVER is not set
-# CONFIG_DEBUG_DEVRES is not set
-# CONFIG_SYS_HYPERVISOR is not set
-CONFIG_CONNECTOR=y
-CONFIG_PROC_EVENTS=y
-# CONFIG_MTD is not set
-# CONFIG_PARPORT is not set
-CONFIG_PNP=y
-# CONFIG_PNP_DEBUG_MESSAGES is not set
-
-#
-# Protocols
-#
-CONFIG_PNPACPI=y
-CONFIG_BLK_DEV=y
-# CONFIG_BLK_CPQ_DA is not set
-# CONFIG_BLK_CPQ_CISS_DA is not set
-# CONFIG_BLK_DEV_DAC960 is not set
-# CONFIG_BLK_DEV_UMEM is not set
-# CONFIG_BLK_DEV_COW_COMMON is not set
-CONFIG_BLK_DEV_LOOP=m
+CONFIG_ATA_PIIX=y
+CONFIG_ATA=y
+CONFIG_AUTOFS4_FS=m
+CONFIG_AUTOFS_FS=m
+CONFIG_BINFMT_MISC=m
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_BLK_DEV_CMD64X=y
 CONFIG_BLK_DEV_CRYPTOLOOP=m
-CONFIG_BLK_DEV_NBD=m
-# CONFIG_BLK_DEV_SX8 is not set
-# CONFIG_BLK_DEV_UB is not set
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=4096
-# CONFIG_BLK_DEV_XIP is not set
-# CONFIG_CDROM_PKTCDVD is not set
-# CONFIG_ATA_OVER_ETH is not set
-# CONFIG_BLK_DEV_HD is not set
-CONFIG_MISC_DEVICES=y
-# CONFIG_PHANTOM is not set
-# CONFIG_EEPROM_93CX6 is not set
-CONFIG_SGI_IOC4=y
-# CONFIG_TIFM_CORE is not set
-# CONFIG_ENCLOSURE_SERVICES is not set
-CONFIG_SGI_XP=m
-# CONFIG_HP_ILO is not set
-# CONFIG_C2PORT is not set
-CONFIG_HAVE_IDE=y
-CONFIG_IDE=y
-
-#
-# Please see Documentation/ide/ide.txt for help/info on IDE drives
-#
-CONFIG_IDE_TIMINGS=y
-CONFIG_IDE_ATAPI=y
-# CONFIG_BLK_DEV_IDE_SATA is not set
-CONFIG_IDE_GD=y
-CONFIG_IDE_GD_ATA=y
-# CONFIG_IDE_GD_ATAPI is not set
-CONFIG_BLK_DEV_IDECD=y
-CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y
-# CONFIG_BLK_DEV_IDETAPE is not set
-CONFIG_BLK_DEV_IDESCSI=m
-# CONFIG_BLK_DEV_IDEACPI is not set
-# CONFIG_IDE_TASK_IOCTL is not set
-CONFIG_IDE_PROC_FS=y
-
-#
-# IDE chipset support/bugfixes
-#
-# CONFIG_IDE_GENERIC is not set
-# CONFIG_BLK_DEV_PLATFORM is not set
-# CONFIG_BLK_DEV_IDEPNP is not set
-CONFIG_BLK_DEV_IDEDMA_SFF=y
-
-#
-# PCI IDE chipsets support
-#
-CONFIG_BLK_DEV_IDEPCI=y
-CONFIG_IDEPCI_PCIBUS_ORDER=y
-# CONFIG_BLK_DEV_OFFBOARD is not set
+CONFIG_BLK_DEV_DM=m
 CONFIG_BLK_DEV_GENERIC=y
-# CONFIG_BLK_DEV_OPTI621 is not set
-CONFIG_BLK_DEV_IDEDMA_PCI=y
-# CONFIG_BLK_DEV_AEC62XX is not set
-# CONFIG_BLK_DEV_ALI15X3 is not set
-# CONFIG_BLK_DEV_AMD74XX is not set
-CONFIG_BLK_DEV_CMD64X=y
-# CONFIG_BLK_DEV_TRIFLEX is not set
-# CONFIG_BLK_DEV_CS5520 is not set
-# CONFIG_BLK_DEV_CS5530 is not set
-# CONFIG_BLK_DEV_HPT366 is not set
-# CONFIG_BLK_DEV_JMICRON is not set
-# CONFIG_BLK_DEV_SC1200 is not set
+CONFIG_BLK_DEV_IDECD=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_BLK_DEV_LOOP=m
+CONFIG_BLK_DEV_MD=m
+CONFIG_BLK_DEV_NBD=m
 CONFIG_BLK_DEV_PIIX=y
-# CONFIG_BLK_DEV_IT8213 is not set
-# CONFIG_BLK_DEV_IT821X is not set
-# CONFIG_BLK_DEV_NS87415 is not set
-# CONFIG_BLK_DEV_PDC202XX_OLD is not set
-# CONFIG_BLK_DEV_PDC202XX_NEW is not set
-# CONFIG_BLK_DEV_SVWKS is not set
-CONFIG_BLK_DEV_SGIIOC4=y
-# CONFIG_BLK_DEV_SIIMAGE is not set
-# CONFIG_BLK_DEV_SLC90E66 is not set
-# CONFIG_BLK_DEV_TRM290 is not set
-# CONFIG_BLK_DEV_VIA82CXXX is not set
-# CONFIG_BLK_DEV_TC86C001 is not set
-CONFIG_BLK_DEV_IDEDMA=y
-
-#
-# SCSI device support
-#
-# CONFIG_RAID_ATTRS is not set
-CONFIG_SCSI=y
-CONFIG_SCSI_DMA=y
-# CONFIG_SCSI_TGT is not set
-CONFIG_SCSI_NETLINK=y
-CONFIG_SCSI_PROC_FS=y
-
-#
-# SCSI support type (disk, tape, CD-ROM)
-#
+CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_SD=y
-CONFIG_CHR_DEV_ST=m
-# CONFIG_CHR_DEV_OSST is not set
+CONFIG_BLK_DEV_SGIIOC4=y
 CONFIG_BLK_DEV_SR=m
-# CONFIG_BLK_DEV_SR_VENDOR is not set
+CONFIG_CGROUPS=y
 CONFIG_CHR_DEV_SG=m
-# CONFIG_CHR_DEV_SCH is not set
-
-#
-# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
-#
-# CONFIG_SCSI_MULTI_LUN is not set
-# CONFIG_SCSI_CONSTANTS is not set
-# CONFIG_SCSI_LOGGING is not set
-# CONFIG_SCSI_SCAN_ASYNC is not set
-CONFIG_SCSI_WAIT_SCAN=m
-
-#
-# SCSI Transports
-#
-CONFIG_SCSI_SPI_ATTRS=y
-CONFIG_SCSI_FC_ATTRS=y
-# CONFIG_SCSI_ISCSI_ATTRS is not set
-CONFIG_SCSI_SAS_ATTRS=y
-# CONFIG_SCSI_SAS_LIBSAS is not set
-# CONFIG_SCSI_SRP_ATTRS is not set
-CONFIG_SCSI_LOWLEVEL=y
-# CONFIG_ISCSI_TCP is not set
-# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
-# CONFIG_SCSI_3W_9XXX is not set
-# CONFIG_SCSI_ACARD is not set
-# CONFIG_SCSI_AACRAID is not set
-# CONFIG_SCSI_AIC7XXX is not set
-# CONFIG_SCSI_AIC7XXX_OLD is not set
-# CONFIG_SCSI_AIC79XX is not set
-# CONFIG_SCSI_AIC94XX is not set
-# CONFIG_SCSI_DPT_I2O is not set
-# CONFIG_SCSI_ADVANSYS is not set
-# CONFIG_SCSI_ARCMSR is not set
-# CONFIG_MEGARAID_NEWGEN is not set
-# CONFIG_MEGARAID_LEGACY is not set
-# CONFIG_MEGARAID_SAS is not set
-# CONFIG_SCSI_HPTIOP is not set
-# CONFIG_SCSI_DMX3191D is not set
-# CONFIG_SCSI_FUTURE_DOMAIN is not set
-# CONFIG_SCSI_IPS is not set
-# CONFIG_SCSI_INITIO is not set
-# CONFIG_SCSI_INIA100 is not set
-# CONFIG_SCSI_MVSAS is not set
-# CONFIG_SCSI_STEX is not set
-CONFIG_SCSI_SYM53C8XX_2=y
-CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1
-CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16
-CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64
-CONFIG_SCSI_SYM53C8XX_MMIO=y
-# CONFIG_SCSI_IPR is not set
-CONFIG_SCSI_QLOGIC_1280=y
-# CONFIG_SCSI_QLA_FC is not set
-# CONFIG_SCSI_QLA_ISCSI is not set
-# CONFIG_SCSI_LPFC is not set
-# CONFIG_SCSI_DC395x is not set
-# CONFIG_SCSI_DC390T is not set
-# CONFIG_SCSI_DEBUG is not set
-# CONFIG_SCSI_SRP is not set
-# CONFIG_SCSI_DH is not set
-CONFIG_ATA=y
-CONFIG_ATA_NONSTANDARD=y
-CONFIG_ATA_ACPI=y
-CONFIG_SATA_PMP=y
-# CONFIG_SATA_AHCI is not set
-# CONFIG_SATA_SIL24 is not set
-CONFIG_ATA_SFF=y
-# CONFIG_SATA_SVW is not set
-CONFIG_ATA_PIIX=y
-# CONFIG_SATA_MV is not set
-# CONFIG_SATA_NV is not set
-# CONFIG_PDC_ADMA is not set
-# CONFIG_SATA_QSTOR is not set
-# CONFIG_SATA_PROMISE is not set
-# CONFIG_SATA_SX4 is not set
-# CONFIG_SATA_SIL is not set
-# CONFIG_SATA_SIS is not set
-# CONFIG_SATA_ULI is not set
-# CONFIG_SATA_VIA is not set
-CONFIG_SATA_VITESSE=y
-# CONFIG_SATA_INIC162X is not set
-# CONFIG_PATA_ACPI is not set
-# CONFIG_PATA_ALI is not set
-# CONFIG_PATA_AMD is not set
-# CONFIG_PATA_ARTOP is not set
-# CONFIG_PATA_ATIIXP is not set
-# CONFIG_PATA_CMD640_PCI is not set
-# CONFIG_PATA_CMD64X is not set
-# CONFIG_PATA_CS5520 is not set
-# CONFIG_PATA_CS5530 is not set
-# CONFIG_PATA_CYPRESS is not set
-# CONFIG_PATA_EFAR is not set
-# CONFIG_ATA_GENERIC is not set
-# CONFIG_PATA_HPT366 is not set
-# CONFIG_PATA_HPT37X is not set
-# CONFIG_PATA_HPT3X2N is not set
-# CONFIG_PATA_HPT3X3 is not set
-# CONFIG_PATA_IT821X is not set
-# CONFIG_PATA_IT8213 is not set
-# CONFIG_PATA_JMICRON is not set
-# CONFIG_PATA_TRIFLEX is not set
-# CONFIG_PATA_MARVELL is not set
-# CONFIG_PATA_MPIIX is not set
-# CONFIG_PATA_OLDPIIX is not set
-# CONFIG_PATA_NETCELL is not set
-# CONFIG_PATA_NINJA32 is not set
-# CONFIG_PATA_NS87410 is not set
-# CONFIG_PATA_NS87415 is not set
-# CONFIG_PATA_OPTI is not set
-# CONFIG_PATA_OPTIDMA is not set
-# CONFIG_PATA_PDC_OLD is not set
-# CONFIG_PATA_RADISYS is not set
-# CONFIG_PATA_RZ1000 is not set
-# CONFIG_PATA_SC1200 is not set
-# CONFIG_PATA_SERVERWORKS is not set
-# CONFIG_PATA_PDC2027X is not set
-# CONFIG_PATA_SIL680 is not set
-# CONFIG_PATA_SIS is not set
-# CONFIG_PATA_VIA is not set
-# CONFIG_PATA_WINBOND is not set
-# CONFIG_PATA_SCH is not set
-CONFIG_MD=y
-CONFIG_BLK_DEV_MD=m
-CONFIG_MD_LINEAR=m
-CONFIG_MD_RAID0=m
-CONFIG_MD_RAID1=m
-# CONFIG_MD_RAID10 is not set
-# CONFIG_MD_RAID456 is not set
-CONFIG_MD_MULTIPATH=m
-# CONFIG_MD_FAULTY is not set
-CONFIG_BLK_DEV_DM=m
-# CONFIG_DM_DEBUG is not set
+CONFIG_CHR_DEV_ST=m
+CONFIG_CIFS=m
+CONFIG_CONNECTOR=y
+CONFIG_CPUSETS=y
+CONFIG_CRASH_DUMP=y
+CONFIG_CRC_T10DIF=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_ECB=m
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_PCBC=m
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_MUTEXES=y
 CONFIG_DM_CRYPT=m
-CONFIG_DM_SNAPSHOT=m
 CONFIG_DM_MIRROR=m
-CONFIG_DM_ZERO=m
 CONFIG_DM_MULTIPATH=m
-# CONFIG_DM_DELAY is not set
-# CONFIG_DM_UEVENT is not set
-CONFIG_FUSION=y
-CONFIG_FUSION_SPI=y
-CONFIG_FUSION_FC=m
-CONFIG_FUSION_SAS=y
-CONFIG_FUSION_MAX_SGE=128
-# CONFIG_FUSION_CTL is not set
-# CONFIG_FUSION_LOGGING is not set
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# Enable only one of the two stacks, unless you know what you are doing
-#
-# CONFIG_FIREWIRE is not set
-# CONFIG_IEEE1394 is not set
-# CONFIG_I2O is not set
-CONFIG_NETDEVICES=y
-CONFIG_DUMMY=m
-# CONFIG_BONDING is not set
-# CONFIG_MACVLAN is not set
-# CONFIG_EQUALIZER is not set
-# CONFIG_TUN is not set
-# CONFIG_VETH is not set
-# CONFIG_NET_SB1000 is not set
-# CONFIG_ARCNET is not set
-CONFIG_PHYLIB=y
-
-#
-# MII PHY device drivers
-#
-# CONFIG_MARVELL_PHY is not set
-# CONFIG_DAVICOM_PHY is not set
-# CONFIG_QSEMI_PHY is not set
-# CONFIG_LXT_PHY is not set
-# CONFIG_CICADA_PHY is not set
-# CONFIG_VITESSE_PHY is not set
-# CONFIG_SMSC_PHY is not set
-# CONFIG_BROADCOM_PHY is not set
-# CONFIG_ICPLUS_PHY is not set
-# CONFIG_REALTEK_PHY is not set
-# CONFIG_FIXED_PHY is not set
-# CONFIG_MDIO_BITBANG is not set
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=m
-# CONFIG_HAPPYMEAL is not set
-# CONFIG_SUNGEM is not set
-# CONFIG_CASSINI is not set
-# CONFIG_NET_VENDOR_3COM is not set
-CONFIG_NET_TULIP=y
-# CONFIG_DE2104X is not set
-CONFIG_TULIP=m
-# CONFIG_TULIP_MWI is not set
-# CONFIG_TULIP_MMIO is not set
-# CONFIG_TULIP_NAPI is not set
-# CONFIG_DE4X5 is not set
-# CONFIG_WINBOND_840 is not set
-# CONFIG_DM9102 is not set
-# CONFIG_ULI526X is not set
-# CONFIG_HP100 is not set
-# CONFIG_IBM_NEW_EMAC_ZMII is not set
-# CONFIG_IBM_NEW_EMAC_RGMII is not set
-# CONFIG_IBM_NEW_EMAC_TAH is not set
-# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
-# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
-# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
-CONFIG_NET_PCI=y
-# CONFIG_PCNET32 is not set
-# CONFIG_AMD8111_ETH is not set
-# CONFIG_ADAPTEC_STARFIRE is not set
-# CONFIG_B44 is not set
-# CONFIG_FORCEDETH is not set
-CONFIG_EEPRO100=m
-CONFIG_E100=m
-# CONFIG_FEALNX is not set
-# CONFIG_NATSEMI is not set
-# CONFIG_NE2K_PCI is not set
-# CONFIG_8139CP is not set
-# CONFIG_8139TOO is not set
-# CONFIG_R6040 is not set
-# CONFIG_SIS900 is not set
-# CONFIG_EPIC100 is not set
-# CONFIG_SUNDANCE is not set
-# CONFIG_TLAN is not set
-# CONFIG_VIA_RHINE is not set
-# CONFIG_SC92031 is not set
-# CONFIG_ATL2 is not set
-CONFIG_NETDEV_1000=y
-# CONFIG_ACENIC is not set
-# CONFIG_DL2K is not set
-CONFIG_E1000=y
-# CONFIG_E1000E is not set
-# CONFIG_IP1000 is not set
-CONFIG_IGB=y
-# CONFIG_IGB_LRO is not set
-# CONFIG_NS83820 is not set
-# CONFIG_HAMACHI is not set
-# CONFIG_YELLOWFIN is not set
-# CONFIG_R8169 is not set
-# CONFIG_SIS190 is not set
-# CONFIG_SKGE is not set
-# CONFIG_SKY2 is not set
-# CONFIG_VIA_VELOCITY is not set
-CONFIG_TIGON3=y
-# CONFIG_BNX2 is not set
-# CONFIG_QLA3XXX is not set
-# CONFIG_ATL1 is not set
-# CONFIG_ATL1E is not set
-# CONFIG_JME is not set
-CONFIG_NETDEV_10000=y
-# CONFIG_CHELSIO_T1 is not set
-# CONFIG_CHELSIO_T3 is not set
-# CONFIG_ENIC is not set
-# CONFIG_IXGBE is not set
-# CONFIG_IXGB is not set
-# CONFIG_S2IO is not set
-# CONFIG_MYRI10GE is not set
-# CONFIG_NETXEN_NIC is not set
-# CONFIG_NIU is not set
-# CONFIG_MLX4_EN is not set
-# CONFIG_MLX4_CORE is not set
-# CONFIG_TEHUTI is not set
-# CONFIG_BNX2X is not set
-# CONFIG_QLGE is not set
-# CONFIG_SFC is not set
-# CONFIG_TR is not set
-
-#
-# Wireless LAN
-#
-# CONFIG_WLAN_PRE80211 is not set
-# CONFIG_WLAN_80211 is not set
-# CONFIG_IWLWIFI_LEDS is not set
-
-#
-# USB Network Adapters
-#
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_RTL8150 is not set
-# CONFIG_USB_USBNET is not set
-# CONFIG_WAN is not set
-# CONFIG_FDDI is not set
-# CONFIG_HIPPI is not set
-# CONFIG_PPP is not set
-# CONFIG_SLIP is not set
-# CONFIG_NET_FC is not set
-CONFIG_NETCONSOLE=y
-# CONFIG_NETCONSOLE_DYNAMIC is not set
-CONFIG_NETPOLL=y
-# CONFIG_NETPOLL_TRAP is not set
-CONFIG_NET_POLL_CONTROLLER=y
-# CONFIG_ISDN is not set
-# CONFIG_PHONE is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-# CONFIG_INPUT_FF_MEMLESS is not set
-# CONFIG_INPUT_POLLDEV is not set
-
-#
-# Userland interfaces
-#
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-# CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_EVDEV is not set
-# CONFIG_INPUT_EVBUG is not set
-
-#
-# Input Device Drivers
-#
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_KEYBOARD_ATKBD=y
-# CONFIG_KEYBOARD_SUNKBD is not set
-# CONFIG_KEYBOARD_LKKBD is not set
-# CONFIG_KEYBOARD_XTKBD is not set
-# CONFIG_KEYBOARD_NEWTON is not set
-# CONFIG_KEYBOARD_STOWAWAY is not set
-CONFIG_INPUT_MOUSE=y
-CONFIG_MOUSE_PS2=y
-CONFIG_MOUSE_PS2_ALPS=y
-CONFIG_MOUSE_PS2_LOGIPS2PP=y
-CONFIG_MOUSE_PS2_SYNAPTICS=y
-CONFIG_MOUSE_PS2_LIFEBOOK=y
-CONFIG_MOUSE_PS2_TRACKPOINT=y
-# CONFIG_MOUSE_PS2_ELANTECH is not set
-# CONFIG_MOUSE_PS2_TOUCHKIT is not set
-# CONFIG_MOUSE_SERIAL is not set
-# CONFIG_MOUSE_APPLETOUCH is not set
-# CONFIG_MOUSE_BCM5974 is not set
-# CONFIG_MOUSE_VSXXXAA is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TABLET is not set
-# CONFIG_INPUT_TOUCHSCREEN is not set
-# CONFIG_INPUT_MISC is not set
-
-#
-# Hardware I/O ports
-#
-CONFIG_SERIO=y
-CONFIG_SERIO_I8042=y
-# CONFIG_SERIO_SERPORT is not set
-# CONFIG_SERIO_PCIPS2 is not set
-CONFIG_SERIO_LIBPS2=y
-# CONFIG_SERIO_RAW is not set
-CONFIG_GAMEPORT=m
-# CONFIG_GAMEPORT_NS558 is not set
-# CONFIG_GAMEPORT_L4 is not set
-# CONFIG_GAMEPORT_EMU10K1 is not set
-# CONFIG_GAMEPORT_FM801 is not set
-
-#
-# Character devices
-#
-CONFIG_VT=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
-CONFIG_DEVKMEM=y
-CONFIG_SERIAL_NONSTANDARD=y
-# CONFIG_COMPUTONE is not set
-# CONFIG_ROCKETPORT is not set
-# CONFIG_CYCLADES is not set
-# CONFIG_DIGIEPCA is not set
-# CONFIG_MOXA_INTELLIO is not set
-# CONFIG_MOXA_SMARTIO is not set
-# CONFIG_ISI is not set
-# CONFIG_SYNCLINKMP is not set
-# CONFIG_SYNCLINK_GT is not set
-# CONFIG_N_HDLC is not set
-# CONFIG_RISCOM8 is not set
-# CONFIG_SPECIALIX is not set
-# CONFIG_SX is not set
-# CONFIG_RIO is not set
-# CONFIG_STALDRV is not set
-# CONFIG_NOZOMI is not set
-CONFIG_SGI_SNSC=y
-CONFIG_SGI_TIOCX=y
-CONFIG_SGI_MBCS=m
-
-#
-# Serial drivers
-#
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_PCI=y
-CONFIG_SERIAL_8250_PNP=y
-CONFIG_SERIAL_8250_NR_UARTS=6
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-# CONFIG_SERIAL_8250_DETECT_IRQ is not set
-# CONFIG_SERIAL_8250_RSA is not set
-
-#
-# Non-8250 serial port support
-#
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-CONFIG_SERIAL_SGI_L1_CONSOLE=y
-# CONFIG_SERIAL_JSM is not set
-CONFIG_SERIAL_SGI_IOC4=y
-# CONFIG_SERIAL_SGI_IOC3 is not set
-CONFIG_UNIX98_PTYS=y
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-# CONFIG_IPMI_HANDLER is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_EFI_RTC=y
-# CONFIG_R3964 is not set
-# CONFIG_APPLICOM is not set
-CONFIG_RAW_DRIVER=m
-CONFIG_MAX_RAW_DEVS=256
-CONFIG_HPET=y
-CONFIG_HPET_MMAP=y
-# CONFIG_HANGCHECK_TIMER is not set
-CONFIG_MMTIMER=y
-# CONFIG_TCG_TPM is not set
-CONFIG_DEVPORT=y
-# CONFIG_I2C is not set
-# CONFIG_SPI is not set
-# CONFIG_W1 is not set
-CONFIG_POWER_SUPPLY=y
-# CONFIG_POWER_SUPPLY_DEBUG is not set
-# CONFIG_PDA_POWER is not set
-# CONFIG_BATTERY_DS2760 is not set
-CONFIG_HWMON=y
-# CONFIG_HWMON_VID is not set
-# CONFIG_SENSORS_I5K_AMB is not set
-# CONFIG_SENSORS_F71805F is not set
-# CONFIG_SENSORS_F71882FG is not set
-# CONFIG_SENSORS_IT87 is not set
-# CONFIG_SENSORS_PC87360 is not set
-# CONFIG_SENSORS_PC87427 is not set
-# CONFIG_SENSORS_SIS5595 is not set
-# CONFIG_SENSORS_SMSC47M1 is not set
-# CONFIG_SENSORS_SMSC47B397 is not set
-# CONFIG_SENSORS_VIA686A is not set
-# CONFIG_SENSORS_VT1211 is not set
-# CONFIG_SENSORS_VT8231 is not set
-# CONFIG_SENSORS_W83627HF is not set
-# CONFIG_SENSORS_W83627EHF is not set
-# CONFIG_SENSORS_LIS3LV02D is not set
-# CONFIG_HWMON_DEBUG_CHIP is not set
-CONFIG_THERMAL=m
-# CONFIG_THERMAL_HWMON is not set
-# CONFIG_WATCHDOG is not set
-CONFIG_SSB_POSSIBLE=y
-
-#
-# Sonics Silicon Backplane
-#
-# CONFIG_SSB is not set
-
-#
-# Multifunction device drivers
-#
-# CONFIG_MFD_CORE is not set
-# CONFIG_MFD_SM501 is not set
-# CONFIG_HTC_PASIC3 is not set
-# CONFIG_MFD_TMIO is not set
-# CONFIG_REGULATOR is not set
-
-#
-# Multimedia devices
-#
-
-#
-# Multimedia core support
-#
-# CONFIG_VIDEO_DEV is not set
-# CONFIG_DVB_CORE is not set
-# CONFIG_VIDEO_MEDIA is not set
-
-#
-# Multimedia drivers
-#
-CONFIG_DAB=y
-# CONFIG_USB_DABUSB is not set
-
-#
-# Graphics support
-#
-CONFIG_AGP=m
-CONFIG_AGP_I460=m
-CONFIG_AGP_HP_ZX1=m
-CONFIG_AGP_SGI_TIOCA=m
+CONFIG_DM_SNAPSHOT=m
+CONFIG_DM_ZERO=m
 CONFIG_DRM=m
-CONFIG_DRM_TDFX=m
+CONFIG_DRM_MGA=m
 CONFIG_DRM_R128=m
 CONFIG_DRM_RADEON=m
-CONFIG_DRM_MGA=m
 CONFIG_DRM_SIS=m
-# CONFIG_DRM_VIA is not set
-# CONFIG_DRM_SAVAGE is not set
-# CONFIG_VGASTATE is not set
-# CONFIG_VIDEO_OUTPUT_CONTROL is not set
-# CONFIG_FB is not set
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
-#
-# Display device support
-#
-# CONFIG_DISPLAY_SUPPORT is not set
-
-#
-# Console display driver support
-#
-CONFIG_VGA_CONSOLE=y
-# CONFIG_VGACON_SOFT_SCROLLBACK is not set
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_SOUND=m
-CONFIG_SOUND_OSS_CORE=y
-CONFIG_SND=m
-CONFIG_SND_TIMER=m
-CONFIG_SND_PCM=m
-CONFIG_SND_HWDEP=m
-CONFIG_SND_RAWMIDI=m
-CONFIG_SND_SEQUENCER=m
-CONFIG_SND_SEQ_DUMMY=m
-CONFIG_SND_OSSEMUL=y
-CONFIG_SND_MIXER_OSS=m
-CONFIG_SND_PCM_OSS=m
-CONFIG_SND_PCM_OSS_PLUGINS=y
-CONFIG_SND_SEQUENCER_OSS=y
-# CONFIG_SND_DYNAMIC_MINORS is not set
-CONFIG_SND_SUPPORT_OLD_API=y
-CONFIG_SND_VERBOSE_PROCFS=y
-CONFIG_SND_VERBOSE_PRINTK=y
-# CONFIG_SND_DEBUG is not set
-CONFIG_SND_VMASTER=y
-CONFIG_SND_MPU401_UART=m
-CONFIG_SND_OPL3_LIB=m
-CONFIG_SND_AC97_CODEC=m
-CONFIG_SND_DRIVERS=y
-CONFIG_SND_DUMMY=m
-CONFIG_SND_VIRMIDI=m
-CONFIG_SND_MTPAV=m
-CONFIG_SND_SERIAL_U16550=m
-CONFIG_SND_MPU401=m
-# CONFIG_SND_AC97_POWER_SAVE is not set
-CONFIG_SND_PCI=y
-# CONFIG_SND_AD1889 is not set
-# CONFIG_SND_ALS300 is not set
-# CONFIG_SND_ALI5451 is not set
-# CONFIG_SND_ATIIXP is not set
-# CONFIG_SND_ATIIXP_MODEM is not set
-# CONFIG_SND_AU8810 is not set
-# CONFIG_SND_AU8820 is not set
-# CONFIG_SND_AU8830 is not set
-# CONFIG_SND_AW2 is not set
-# CONFIG_SND_AZT3328 is not set
-# CONFIG_SND_BT87X is not set
-# CONFIG_SND_CA0106 is not set
-# CONFIG_SND_CMIPCI is not set
-# CONFIG_SND_OXYGEN is not set
-CONFIG_SND_CS4281=m
-CONFIG_SND_CS46XX=m
-CONFIG_SND_CS46XX_NEW_DSP=y
-# CONFIG_SND_DARLA20 is not set
-# CONFIG_SND_GINA20 is not set
-# CONFIG_SND_LAYLA20 is not set
-# CONFIG_SND_DARLA24 is not set
-# CONFIG_SND_GINA24 is not set
-# CONFIG_SND_LAYLA24 is not set
-# CONFIG_SND_MONA is not set
-# CONFIG_SND_MIA is not set
-# CONFIG_SND_ECHO3G is not set
-# CONFIG_SND_INDIGO is not set
-# CONFIG_SND_INDIGOIO is not set
-# CONFIG_SND_INDIGODJ is not set
-CONFIG_SND_EMU10K1=m
-# CONFIG_SND_EMU10K1X is not set
-# CONFIG_SND_ENS1370 is not set
-# CONFIG_SND_ENS1371 is not set
-# CONFIG_SND_ES1938 is not set
-# CONFIG_SND_ES1968 is not set
-CONFIG_SND_FM801=m
-# CONFIG_SND_HDA_INTEL is not set
-# CONFIG_SND_HDSP is not set
-# CONFIG_SND_HDSPM is not set
-# CONFIG_SND_HIFIER is not set
-# CONFIG_SND_ICE1712 is not set
-# CONFIG_SND_ICE1724 is not set
-# CONFIG_SND_INTEL8X0 is not set
-# CONFIG_SND_INTEL8X0M is not set
-# CONFIG_SND_KORG1212 is not set
-# CONFIG_SND_MAESTRO3 is not set
-# CONFIG_SND_MIXART is not set
-# CONFIG_SND_NM256 is not set
-# CONFIG_SND_PCXHR is not set
-# CONFIG_SND_RIPTIDE is not set
-# CONFIG_SND_RME32 is not set
-# CONFIG_SND_RME96 is not set
-# CONFIG_SND_RME9652 is not set
-# CONFIG_SND_SONICVIBES is not set
-# CONFIG_SND_TRIDENT is not set
-# CONFIG_SND_VIA82XX is not set
-# CONFIG_SND_VIA82XX_MODEM is not set
-# CONFIG_SND_VIRTUOSO is not set
-# CONFIG_SND_VX222 is not set
-# CONFIG_SND_YMFPCI is not set
-CONFIG_SND_USB=y
-# CONFIG_SND_USB_AUDIO is not set
-# CONFIG_SND_USB_CAIAQ is not set
-# CONFIG_SND_SOC is not set
-# CONFIG_SOUND_PRIME is not set
-CONFIG_AC97_BUS=m
-CONFIG_HID_SUPPORT=y
-CONFIG_HID=y
-# CONFIG_HID_DEBUG is not set
-# CONFIG_HIDRAW is not set
-
-#
-# USB Input Devices
-#
-CONFIG_USB_HID=m
-# CONFIG_HID_PID is not set
-# CONFIG_USB_HIDDEV is not set
-
-#
-# USB HID Boot Protocol drivers
-#
-# CONFIG_USB_KBD is not set
-# CONFIG_USB_MOUSE is not set
-
-#
-# Special HID drivers
-#
-CONFIG_HID_COMPAT=y
-CONFIG_HID_A4TECH=m
-CONFIG_HID_APPLE=m
-CONFIG_HID_BELKIN=m
-CONFIG_HID_BRIGHT=m
-CONFIG_HID_CHERRY=m
-CONFIG_HID_CHICONY=m
-CONFIG_HID_CYPRESS=m
-CONFIG_HID_DELL=m
-CONFIG_HID_EZKEY=m
+CONFIG_DRM_TDFX=m
+CONFIG_DUMMY=m
+CONFIG_E1000=y
+CONFIG_E100=m
+CONFIG_EFI_PARTITION=y
+CONFIG_EFI_RTC=y
+CONFIG_EFI_VARS=y
+CONFIG_EXPERIMENTAL=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+CONFIG_EXT3_FS=y
+CONFIG_FUSION_FC=m
+CONFIG_FUSION_SAS=y
+CONFIG_FUSION_SPI=y
+CONFIG_FUSION=y
+CONFIG_GAMEPORT=m
 CONFIG_HID_GYRATION=m
-CONFIG_HID_LOGITECH=m
-# CONFIG_LOGITECH_FF is not set
-# CONFIG_LOGIRUMBLEPAD2_FF is not set
-CONFIG_HID_MICROSOFT=m
-CONFIG_HID_MONTEREY=m
 CONFIG_HID_PANTHERLORD=m
-# CONFIG_PANTHERLORD_FF is not set
 CONFIG_HID_PETALYNX=m
 CONFIG_HID_SAMSUNG=m
 CONFIG_HID_SONY=m
 CONFIG_HID_SUNPLUS=m
-# CONFIG_THRUSTMASTER_FF is not set
-# CONFIG_ZEROPLUS_FF is not set
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_ARCH_HAS_HCD=y
-CONFIG_USB_ARCH_HAS_OHCI=y
-CONFIG_USB_ARCH_HAS_EHCI=y
-CONFIG_USB=m
-# CONFIG_USB_DEBUG is not set
-# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
-
-#
-# Miscellaneous USB options
-#
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_DEVICE_CLASS=y
-# CONFIG_USB_DYNAMIC_MINORS is not set
-# CONFIG_USB_SUSPEND is not set
-# CONFIG_USB_OTG is not set
-CONFIG_USB_MON=y
-# CONFIG_USB_WUSB is not set
-# CONFIG_USB_WUSB_CBAF is not set
-
-#
-# USB Host Controller Drivers
-#
-# CONFIG_USB_C67X00_HCD is not set
-CONFIG_USB_EHCI_HCD=m
-# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
-# CONFIG_USB_EHCI_TT_NEWSCHED is not set
-# CONFIG_USB_ISP116X_HCD is not set
-# CONFIG_USB_ISP1760_HCD is not set
-CONFIG_USB_OHCI_HCD=m
-# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
-# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
-CONFIG_USB_OHCI_LITTLE_ENDIAN=y
-CONFIG_USB_UHCI_HCD=m
-# CONFIG_USB_SL811_HCD is not set
-# CONFIG_USB_R8A66597_HCD is not set
-# CONFIG_USB_WHCI_HCD is not set
-# CONFIG_USB_HWA_HCD is not set
-
-#
-# Enable Host or Gadget support to see Inventra options
-#
-
-#
-# USB Device Class drivers
-#
-# CONFIG_USB_ACM is not set
-# CONFIG_USB_PRINTER is not set
-# CONFIG_USB_WDM is not set
-# CONFIG_USB_TMC is not set
-
-#
-# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
-#
-
-#
-# see USB_STORAGE Help for more information
-#
-CONFIG_USB_STORAGE=m
-# CONFIG_USB_STORAGE_DEBUG is not set
-# CONFIG_USB_STORAGE_DATAFAB is not set
-# CONFIG_USB_STORAGE_FREECOM is not set
-# CONFIG_USB_STORAGE_ISD200 is not set
-# CONFIG_USB_STORAGE_DPCM is not set
-# CONFIG_USB_STORAGE_USBAT is not set
-# CONFIG_USB_STORAGE_SDDR09 is not set
-# CONFIG_USB_STORAGE_SDDR55 is not set
-# CONFIG_USB_STORAGE_JUMPSHOT is not set
-# CONFIG_USB_STORAGE_ALAUDA is not set
-# CONFIG_USB_STORAGE_ONETOUCH is not set
-# CONFIG_USB_STORAGE_KARMA is not set
-# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
-# CONFIG_USB_LIBUSUAL is not set
-
-#
-# USB Imaging devices
-#
-# CONFIG_USB_MDC800 is not set
-# CONFIG_USB_MICROTEK is not set
-
-#
-# USB port drivers
-#
-# CONFIG_USB_SERIAL is not set
-
-#
-# USB Miscellaneous drivers
-#
-# CONFIG_USB_EMI62 is not set
-# CONFIG_USB_EMI26 is not set
-# CONFIG_USB_ADUTUX is not set
-# CONFIG_USB_SEVSEG is not set
-# CONFIG_USB_RIO500 is not set
-# CONFIG_USB_LEGOTOWER is not set
-# CONFIG_USB_LCD is not set
-# CONFIG_USB_BERRY_CHARGE is not set
-# CONFIG_USB_LED is not set
-# CONFIG_USB_CYPRESS_CY7C63 is not set
-# CONFIG_USB_CYTHERM is not set
-# CONFIG_USB_PHIDGET is not set
-# CONFIG_USB_IDMOUSE is not set
-# CONFIG_USB_FTDI_ELAN is not set
-# CONFIG_USB_APPLEDISPLAY is not set
-# CONFIG_USB_SISUSBVGA is not set
-# CONFIG_USB_LD is not set
-# CONFIG_USB_TRANCEVIBRATOR is not set
-# CONFIG_USB_IOWARRIOR is not set
-# CONFIG_USB_TEST is not set
-# CONFIG_USB_ISIGHTFW is not set
-# CONFIG_USB_VST is not set
-# CONFIG_USB_GADGET is not set
-# CONFIG_UWB is not set
-# CONFIG_MMC is not set
-# CONFIG_MEMSTICK is not set
-# CONFIG_NEW_LEDS is not set
-# CONFIG_ACCESSIBILITY is not set
+CONFIG_HOTPLUG_CPU=y
+CONFIG_HOTPLUG_PCI_ACPI=m
+CONFIG_HOTPLUG_PCI=m
+CONFIG_HPET=y
+CONFIG_HUGETLBFS=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_IA64_CYCLONE=y
+CONFIG_IA64_MCA_RECOVERY=y
+CONFIG_IA64_PAGE_SIZE_64KB=y
+CONFIG_IA64_PALINFO=y
+CONFIG_IDE=y
+CONFIG_IGB=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_IKCONFIG=y
+CONFIG_INET=y
+CONFIG_INFINIBAND_IPOIB=m
 CONFIG_INFINIBAND=m
-# CONFIG_INFINIBAND_USER_MAD is not set
-# CONFIG_INFINIBAND_USER_ACCESS is not set
-CONFIG_INFINIBAND_ADDR_TRANS=y
 CONFIG_INFINIBAND_MTHCA=m
-CONFIG_INFINIBAND_MTHCA_DEBUG=y
-# CONFIG_INFINIBAND_IPATH is not set
-# CONFIG_INFINIBAND_AMSO1100 is not set
-# CONFIG_MLX4_INFINIBAND is not set
-# CONFIG_INFINIBAND_NES is not set
-CONFIG_INFINIBAND_IPOIB=m
-# CONFIG_INFINIBAND_IPOIB_CM is not set
-CONFIG_INFINIBAND_IPOIB_DEBUG=y
-# CONFIG_INFINIBAND_IPOIB_DEBUG_DATA is not set
-# CONFIG_INFINIBAND_SRP is not set
-# CONFIG_INFINIBAND_ISER is not set
-# CONFIG_RTC_CLASS is not set
-# CONFIG_DMADEVICES is not set
-# CONFIG_UIO is not set
-# CONFIG_STAGING is not set
-CONFIG_STAGING_EXCLUDE_BUILD=y
-
-#
-# HP Simulator drivers
-#
-# CONFIG_HP_SIMETH is not set
-# CONFIG_HP_SIMSERIAL is not set
-# CONFIG_HP_SIMSCSI is not set
-CONFIG_MSPEC=m
-
-#
-# File systems
-#
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT2_FS_POSIX_ACL=y
-CONFIG_EXT2_FS_SECURITY=y
-# CONFIG_EXT2_FS_XIP is not set
-CONFIG_EXT3_FS=y
-CONFIG_EXT3_FS_XATTR=y
-CONFIG_EXT3_FS_POSIX_ACL=y
-CONFIG_EXT3_FS_SECURITY=y
-# CONFIG_EXT4_FS is not set
-CONFIG_JBD=y
-CONFIG_FS_MBCACHE=y
-CONFIG_REISERFS_FS=y
-# CONFIG_REISERFS_CHECK is not set
-# CONFIG_REISERFS_PROC_INFO is not set
-CONFIG_REISERFS_FS_XATTR=y
-CONFIG_REISERFS_FS_POSIX_ACL=y
-CONFIG_REISERFS_FS_SECURITY=y
-# CONFIG_JFS_FS is not set
-CONFIG_FS_POSIX_ACL=y
-CONFIG_FILE_LOCKING=y
-CONFIG_XFS_FS=y
-# CONFIG_XFS_QUOTA is not set
-# CONFIG_XFS_POSIX_ACL is not set
-# CONFIG_XFS_RT is not set
-# CONFIG_XFS_DEBUG is not set
-# CONFIG_GFS2_FS is not set
-# CONFIG_OCFS2_FS is not set
-CONFIG_DNOTIFY=y
 CONFIG_INOTIFY=y
-CONFIG_INOTIFY_USER=y
-# CONFIG_QUOTA is not set
-CONFIG_AUTOFS_FS=m
-CONFIG_AUTOFS4_FS=m
-# CONFIG_FUSE_FS is not set
-
-#
-# CD-ROM/DVD Filesystems
-#
+CONFIG_IP_MULTICAST=y
+# CONFIG_IPV6 is not set
 CONFIG_ISO9660_FS=m
 CONFIG_JOLIET=y
-# CONFIG_ZISOFS is not set
-CONFIG_UDF_FS=m
-CONFIG_UDF_NLS=y
-
-#
-# DOS/FAT/NT Filesystems
-#
-CONFIG_FAT_FS=y
-# CONFIG_MSDOS_FS is not set
-CONFIG_VFAT_FS=y
-CONFIG_FAT_DEFAULT_CODEPAGE=437
-CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-CONFIG_NTFS_FS=m
-# CONFIG_NTFS_DEBUG is not set
-# CONFIG_NTFS_RW is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_KCORE=y
-CONFIG_PROC_VMCORE=y
-CONFIG_PROC_SYSCTL=y
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_SYSFS=y
-CONFIG_TMPFS=y
-# CONFIG_TMPFS_POSIX_ACL is not set
-CONFIG_HUGETLBFS=y
-CONFIG_HUGETLB_PAGE=y
-# CONFIG_CONFIGFS_FS is not set
-
-#
-# Miscellaneous filesystems
-#
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-# CONFIG_CRAMFS is not set
-# CONFIG_VXFS_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_OMFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_ROMFS_FS is not set
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_KEXEC=y
+CONFIG_LOG_BUF_SHIFT=20
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MCKINLEY=y
+CONFIG_MD_LINEAR=m
+CONFIG_MD_MULTIPATH=m
+CONFIG_MD_RAID0=m
+CONFIG_MD_RAID1=m
+CONFIG_MD=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_MSPEC=m
+CONFIG_NETCONSOLE=y
+CONFIG_NETDEVICES=y
+CONFIG_NET_ETHERNET=y
+CONFIG_NET_PCI=y
+CONFIG_NET_TULIP=y
+CONFIG_NFSD=m
+CONFIG_NFSD_V4=y
 CONFIG_NFS_FS=m
 CONFIG_NFS_V3=y
-# CONFIG_NFS_V3_ACL is not set
 CONFIG_NFS_V4=y
-CONFIG_NFSD=m
-CONFIG_NFSD_V3=y
-# CONFIG_NFSD_V3_ACL is not set
-CONFIG_NFSD_V4=y
-CONFIG_LOCKD=m
-CONFIG_LOCKD_V4=y
-CONFIG_EXPORTFS=m
-CONFIG_NFS_COMMON=y
-CONFIG_SUNRPC=m
-CONFIG_SUNRPC_GSS=m
-CONFIG_SUNRPC_XPRT_RDMA=m
-# CONFIG_SUNRPC_REGISTER_V4 is not set
-CONFIG_RPCSEC_GSS_KRB5=m
-# CONFIG_RPCSEC_GSS_SPKM3 is not set
-CONFIG_SMB_FS=m
-CONFIG_SMB_NLS_DEFAULT=y
-CONFIG_SMB_NLS_REMOTE="cp437"
-CONFIG_CIFS=m
-# CONFIG_CIFS_STATS is not set
-# CONFIG_CIFS_WEAK_PW_HASH is not set
-# CONFIG_CIFS_XATTR is not set
-# CONFIG_CIFS_DEBUG2 is not set
-# CONFIG_CIFS_EXPERIMENTAL is not set
-# CONFIG_NCP_FS is not set
-# CONFIG_CODA_FS is not set
-# CONFIG_AFS_FS is not set
-
-#
-# Partition Types
-#
-CONFIG_PARTITION_ADVANCED=y
-# CONFIG_ACORN_PARTITION is not set
-# CONFIG_OSF_PARTITION is not set
-# CONFIG_AMIGA_PARTITION is not set
-# CONFIG_ATARI_PARTITION is not set
-# CONFIG_MAC_PARTITION is not set
-CONFIG_MSDOS_PARTITION=y
-# CONFIG_BSD_DISKLABEL is not set
-# CONFIG_MINIX_SUBPARTITION is not set
-# CONFIG_SOLARIS_X86_PARTITION is not set
-# CONFIG_UNIXWARE_DISKLABEL is not set
-# CONFIG_LDM_PARTITION is not set
-CONFIG_SGI_PARTITION=y
-# CONFIG_ULTRIX_PARTITION is not set
-# CONFIG_SUN_PARTITION is not set
-# CONFIG_KARMA_PARTITION is not set
-CONFIG_EFI_PARTITION=y
-# CONFIG_SYSV68_PARTITION is not set
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_1250=m
+CONFIG_NLS_CODEPAGE_1251=m
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_737=m
 CONFIG_NLS_CODEPAGE_775=m
@@ -1465,15 +143,14 @@ CONFIG_NLS_CODEPAGE_864=m
 CONFIG_NLS_CODEPAGE_865=m
 CONFIG_NLS_CODEPAGE_866=m
 CONFIG_NLS_CODEPAGE_869=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_CODEPAGE_950=m
+CONFIG_NLS_CODEPAGE_874=m
 CONFIG_NLS_CODEPAGE_932=m
+CONFIG_NLS_CODEPAGE_936=m
 CONFIG_NLS_CODEPAGE_949=m
-CONFIG_NLS_CODEPAGE_874=m
-CONFIG_NLS_ISO8859_8=m
-CONFIG_NLS_CODEPAGE_1250=m
-CONFIG_NLS_CODEPAGE_1251=m
-# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_CODEPAGE_950=m
+CONFIG_NLS_ISO8859_13=m
+CONFIG_NLS_ISO8859_14=m
+CONFIG_NLS_ISO8859_15=m
 CONFIG_NLS_ISO8859_1=y
 CONFIG_NLS_ISO8859_2=m
 CONFIG_NLS_ISO8859_3=m
@@ -1481,194 +158,79 @@ CONFIG_NLS_ISO8859_4=m
 CONFIG_NLS_ISO8859_5=m
 CONFIG_NLS_ISO8859_6=m
 CONFIG_NLS_ISO8859_7=m
+CONFIG_NLS_ISO8859_8=m
 CONFIG_NLS_ISO8859_9=m
-CONFIG_NLS_ISO8859_13=m
-CONFIG_NLS_ISO8859_14=m
-CONFIG_NLS_ISO8859_15=m
 CONFIG_NLS_KOI8_R=m
 CONFIG_NLS_KOI8_U=m
 CONFIG_NLS_UTF8=m
-# CONFIG_DLM is not set
-
-#
-# Kernel hacking
-#
-# CONFIG_PRINTK_TIME is not set
-CONFIG_ENABLE_WARN_DEPRECATED=y
-CONFIG_ENABLE_MUST_CHECK=y
-CONFIG_FRAME_WARN=2048
-CONFIG_MAGIC_SYSRQ=y
-# CONFIG_UNUSED_SYMBOLS is not set
-# CONFIG_DEBUG_FS is not set
-# CONFIG_HEADERS_CHECK is not set
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DEBUG_SHIRQ is not set
-CONFIG_DETECT_SOFTLOCKUP=y
-# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
-CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
-CONFIG_SCHED_DEBUG=y
-# CONFIG_SCHEDSTATS is not set
-# CONFIG_TIMER_STATS is not set
-# CONFIG_DEBUG_OBJECTS is not set
-# CONFIG_SLUB_DEBUG_ON is not set
-# CONFIG_SLUB_STATS is not set
-# CONFIG_DEBUG_RT_MUTEXES is not set
-# CONFIG_RT_MUTEX_TESTER is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-CONFIG_DEBUG_MUTEXES=y
-# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-# CONFIG_DEBUG_KOBJECT is not set
-# CONFIG_DEBUG_INFO is not set
-# CONFIG_DEBUG_VM is not set
-# CONFIG_DEBUG_WRITECOUNT is not set
-CONFIG_DEBUG_MEMORY_INIT=y
-# CONFIG_DEBUG_LIST is not set
-# CONFIG_DEBUG_SG is not set
-# CONFIG_BOOT_PRINTK_DELAY is not set
-# CONFIG_RCU_TORTURE_TEST is not set
+CONFIG_NTFS_FS=m
+CONFIG_PACKET=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_PERFMON=y
+# CONFIG_PNP_DEBUG_MESSAGES is not set
+CONFIG_POSIX_MQUEUE=y
+CONFIG_PROC_KCORE=y
+CONFIG_RAW_DRIVER=m
 # CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_BACKTRACE_SELF_TEST is not set
-# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
-# CONFIG_FAULT_INJECTION is not set
+CONFIG_REISERFS_FS_POSIX_ACL=y
+CONFIG_REISERFS_FS_SECURITY=y
+CONFIG_REISERFS_FS_XATTR=y
+CONFIG_REISERFS_FS=y
+CONFIG_SATA_VITESSE=y
+CONFIG_SCSI_FC_ATTRS=y
+CONFIG_SCSI_QLOGIC_1280=y
+CONFIG_SCSI_SYM53C8XX_2=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_NR_UARTS=6
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_NONSTANDARD=y
+CONFIG_SERIAL_SGI_IOC4=y
+CONFIG_SERIAL_SGI_L1_CONSOLE=y
+# CONFIG_SERIO_SERPORT is not set
+CONFIG_SGI_IOC4=y
+CONFIG_SGI_MBCS=m
+CONFIG_SGI_PARTITION=y
+CONFIG_SGI_SNSC=y
+CONFIG_SGI_TIOCX=y
+CONFIG_SGI_XP=m
+CONFIG_SMB_FS=m
+CONFIG_SMB_NLS_DEFAULT=y
+CONFIG_SMP=y
+CONFIG_SND_CS4281=m
+CONFIG_SND_CS46XX=m
+CONFIG_SND_DUMMY=m
+CONFIG_SND_EMU10K1=m
+CONFIG_SND_FM801=m
+CONFIG_SND=m
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_MPU401=m
+CONFIG_SND_MTPAV=m
+CONFIG_SND_PCM_OSS=m
+CONFIG_SND_SEQ_DUMMY=m
+CONFIG_SND_SEQUENCER=m
+CONFIG_SND_SEQUENCER_OSS=y
+CONFIG_SND_SERIAL_U16550=m
+CONFIG_SND_VERBOSE_PRINTK=y
+CONFIG_SND_VIRMIDI=m
+CONFIG_SOUND=m
+CONFIG_SYN_COOKIES=y
 CONFIG_SYSCTL_SYSCALL_CHECK=y
-
-#
-# Tracers
-#
-# CONFIG_SCHED_TRACER is not set
-# CONFIG_CONTEXT_SWITCH_TRACER is not set
-# CONFIG_BOOT_TRACER is not set
-# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
-# CONFIG_SAMPLES is not set
-CONFIG_IA64_GRANULE_16MB=y
-# CONFIG_IA64_GRANULE_64MB is not set
-# CONFIG_IA64_PRINT_HAZARDS is not set
-# CONFIG_DISABLE_VHPT is not set
-# CONFIG_IA64_DEBUG_CMPXCHG is not set
-# CONFIG_IA64_DEBUG_IRQ is not set
-CONFIG_SYSVIPC_COMPAT=y
-
-#
-# Security options
-#
-# CONFIG_KEYS is not set
-# CONFIG_SECURITY is not set
-# CONFIG_SECURITYFS is not set
-# CONFIG_SECURITY_FILE_CAPABILITIES is not set
-CONFIG_CRYPTO=y
-
-#
-# Crypto core or helper
-#
-# CONFIG_CRYPTO_FIPS is not set
-CONFIG_CRYPTO_ALGAPI=y
-CONFIG_CRYPTO_AEAD=m
-CONFIG_CRYPTO_BLKCIPHER=m
-CONFIG_CRYPTO_HASH=m
-CONFIG_CRYPTO_RNG=m
-CONFIG_CRYPTO_MANAGER=m
-# CONFIG_CRYPTO_GF128MUL is not set
-# CONFIG_CRYPTO_NULL is not set
-# CONFIG_CRYPTO_CRYPTD is not set
-# CONFIG_CRYPTO_AUTHENC is not set
-# CONFIG_CRYPTO_TEST is not set
-
-#
-# Authenticated Encryption with Associated Data
-#
-# CONFIG_CRYPTO_CCM is not set
-# CONFIG_CRYPTO_GCM is not set
-# CONFIG_CRYPTO_SEQIV is not set
-
-#
-# Block modes
-#
-CONFIG_CRYPTO_CBC=m
-# CONFIG_CRYPTO_CTR is not set
-# CONFIG_CRYPTO_CTS is not set
-CONFIG_CRYPTO_ECB=m
-# CONFIG_CRYPTO_LRW is not set
-CONFIG_CRYPTO_PCBC=m
-# CONFIG_CRYPTO_XTS is not set
-
-#
-# Hash modes
-#
-# CONFIG_CRYPTO_HMAC is not set
-# CONFIG_CRYPTO_XCBC is not set
-
-#
-# Digest
-#
-# CONFIG_CRYPTO_CRC32C is not set
-# CONFIG_CRYPTO_MD4 is not set
-CONFIG_CRYPTO_MD5=y
-# CONFIG_CRYPTO_MICHAEL_MIC is not set
-# CONFIG_CRYPTO_RMD128 is not set
-# CONFIG_CRYPTO_RMD160 is not set
-# CONFIG_CRYPTO_RMD256 is not set
-# CONFIG_CRYPTO_RMD320 is not set
-# CONFIG_CRYPTO_SHA1 is not set
-# CONFIG_CRYPTO_SHA256 is not set
-# CONFIG_CRYPTO_SHA512 is not set
-# CONFIG_CRYPTO_TGR192 is not set
-# CONFIG_CRYPTO_WP512 is not set
-
-#
-# Ciphers
-#
-# CONFIG_CRYPTO_AES is not set
-# CONFIG_CRYPTO_ANUBIS is not set
-# CONFIG_CRYPTO_ARC4 is not set
-# CONFIG_CRYPTO_BLOWFISH is not set
-# CONFIG_CRYPTO_CAMELLIA is not set
-# CONFIG_CRYPTO_CAST5 is not set
-# CONFIG_CRYPTO_CAST6 is not set
-CONFIG_CRYPTO_DES=m
-# CONFIG_CRYPTO_FCRYPT is not set
-# CONFIG_CRYPTO_KHAZAD is not set
-# CONFIG_CRYPTO_SALSA20 is not set
-# CONFIG_CRYPTO_SEED is not set
-# CONFIG_CRYPTO_SERPENT is not set
-# CONFIG_CRYPTO_TEA is not set
-# CONFIG_CRYPTO_TWOFISH is not set
-
-#
-# Compression
-#
-# CONFIG_CRYPTO_DEFLATE is not set
-# CONFIG_CRYPTO_LZO is not set
-
-#
-# Random Number Generation
-#
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRYPTO_HW=y
-# CONFIG_CRYPTO_DEV_HIFN_795X is not set
-CONFIG_HAVE_KVM=y
-CONFIG_VIRTUALIZATION=y
-# CONFIG_KVM is not set
-# CONFIG_VIRTIO_PCI is not set
-# CONFIG_VIRTIO_BALLOON is not set
-
-#
-# Library routines
-#
-CONFIG_BITREVERSE=y
-# CONFIG_CRC_CCITT is not set
-# CONFIG_CRC16 is not set
-CONFIG_CRC_T10DIF=y
-CONFIG_CRC_ITU_T=m
-CONFIG_CRC32=y
-# CONFIG_CRC7 is not set
-# CONFIG_LIBCRC32C is not set
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_PLIST=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HAS_DMA=y
-CONFIG_GENERIC_HARDIRQS=y
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_GENERIC_PENDING_IRQ=y
-CONFIG_IRQ_PER_CPU=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_SYSVIPC=y
+CONFIG_TIGON3=y
+CONFIG_TMPFS=y
+CONFIG_TULIP=m
+CONFIG_UDF_FS=m
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_UNIX=y
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_EHCI_HCD=m
+CONFIG_USB=m
+CONFIG_USB_MON=m
+CONFIG_USB_OHCI_HCD=m
+CONFIG_USB_STORAGE=m
+CONFIG_USB_UHCI_HCD=m
+CONFIG_VFAT_FS=y
+CONFIG_XFS_FS=y
diff --git a/arch/ia64/configs/gensparse_defconfig b/arch/ia64/configs/gensparse_defconfig
index 2dc185b0f9a3..18989a084143 100644
--- a/arch/ia64/configs/gensparse_defconfig
+++ b/arch/ia64/configs/gensparse_defconfig
@@ -1,1267 +1,110 @@
-#
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.16-rc5
-# Thu Mar  2 16:39:10 2006
-#
-
-#
-# Code maturity level options
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_LOCK_KERNEL=y
-CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
-CONFIG_LOCALVERSION=""
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-CONFIG_POSIX_MQUEUE=y
-# CONFIG_BSD_PROCESS_ACCT is not set
-CONFIG_SYSCTL=y
-# CONFIG_AUDIT is not set
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-# CONFIG_CPUSETS is not set
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-# CONFIG_EMBEDDED is not set
-CONFIG_KALLSYMS=y
-CONFIG_KALLSYMS_ALL=y
-# CONFIG_KALLSYMS_EXTRA_PASS is not set
-CONFIG_HOTPLUG=y
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_EPOLL=y
-CONFIG_SHMEM=y
-CONFIG_CC_ALIGN_FUNCTIONS=0
-CONFIG_CC_ALIGN_LABELS=0
-CONFIG_CC_ALIGN_LOOPS=0
-CONFIG_CC_ALIGN_JUMPS=0
-CONFIG_SLUB=y
-# CONFIG_TINY_SHMEM is not set
-CONFIG_BASE_SMALL=0
-# CONFIG_SLOB is not set
-
-#
-# Loadable module support
-#
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_MODULE_FORCE_UNLOAD is not set
-CONFIG_OBSOLETE_MODPARM=y
-CONFIG_MODVERSIONS=y
-# CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_KMOD=y
-CONFIG_STOP_MACHINE=y
-
-#
-# Block layer
-#
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-CONFIG_DEFAULT_AS=y
-# CONFIG_DEFAULT_DEADLINE is not set
-# CONFIG_DEFAULT_CFQ is not set
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="anticipatory"
-
-#
-# Processor type and features
-#
-CONFIG_IA64=y
-CONFIG_64BIT=y
-CONFIG_MMU=y
-CONFIG_SWIOTLB=y
-CONFIG_RWSEM_XCHGADD_ALGORITHM=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_GENERIC_TIME=y
-CONFIG_EFI=y
-CONFIG_GENERIC_IOMAP=y
-CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
-CONFIG_DMA_IS_DMA32=y
-CONFIG_IA64_GENERIC=y
-# CONFIG_IA64_DIG is not set
-# CONFIG_IA64_HP_ZX1 is not set
-# CONFIG_IA64_HP_ZX1_SWIOTLB is not set
-# CONFIG_IA64_SGI_SN2 is not set
-# CONFIG_IA64_HP_SIM is not set
-# CONFIG_ITANIUM is not set
-CONFIG_MCKINLEY=y
-# CONFIG_IA64_PAGE_SIZE_4KB is not set
-# CONFIG_IA64_PAGE_SIZE_8KB is not set
-CONFIG_IA64_PAGE_SIZE_16KB=y
-# CONFIG_IA64_PAGE_SIZE_64KB is not set
-CONFIG_PGTABLE_3=y
-# CONFIG_PGTABLE_4 is not set
-# CONFIG_HZ_100 is not set
-CONFIG_HZ_250=y
-# CONFIG_HZ_1000 is not set
-CONFIG_HZ=250
-CONFIG_IA64_L1_CACHE_SHIFT=7
-CONFIG_IA64_CYCLONE=y
-CONFIG_IOSAPIC=y
-# CONFIG_IA64_SGI_SN_XP is not set
-CONFIG_FORCE_MAX_ZONEORDER=17
-CONFIG_SMP=y
-CONFIG_NR_CPUS=512
-CONFIG_IA64_NR_NODES=256
-CONFIG_HOTPLUG_CPU=y
-# CONFIG_SCHED_SMT is not set
-# CONFIG_PREEMPT is not set
-CONFIG_SELECT_MEMORY_MODEL=y
-# CONFIG_FLATMEM_MANUAL is not set
-# CONFIG_DISCONTIGMEM_MANUAL is not set
-CONFIG_SPARSEMEM_MANUAL=y
-CONFIG_SPARSEMEM=y
-CONFIG_NEED_MULTIPLE_NODES=y
-CONFIG_HAVE_MEMORY_PRESENT=y
-# CONFIG_SPARSEMEM_STATIC is not set
-CONFIG_SPARSEMEM_EXTREME=y
-# CONFIG_MEMORY_HOTPLUG is not set
-CONFIG_SPLIT_PTLOCK_CPUS=4
-CONFIG_MIGRATION=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
-CONFIG_ARCH_FLATMEM_ENABLE=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_DISCONTIGMEM_DEFAULT=y
-CONFIG_NUMA=y
-CONFIG_HAVE_ARCH_EARLY_PFN_TO_NID=y
-CONFIG_IA64_MCA_RECOVERY=y
-CONFIG_PERFMON=y
-CONFIG_IA64_PALINFO=y
-CONFIG_SGI_SN=y
-
-#
-# Firmware Drivers
-#
-CONFIG_EFI_VARS=y
-CONFIG_EFI_PCDP=y
-CONFIG_BINFMT_ELF=y
-CONFIG_BINFMT_MISC=m
-
-#
-# Power management and ACPI
-#
-CONFIG_PM=y
-CONFIG_PM_LEGACY=y
-# CONFIG_PM_DEBUG is not set
-
-#
-# ACPI (Advanced Configuration and Power Interface) Support
-#
-CONFIG_ACPI=y
 CONFIG_ACPI_BUTTON=m
+CONFIG_ACPI_CONTAINER=m
 CONFIG_ACPI_FAN=m
 CONFIG_ACPI_PROCESSOR=m
-CONFIG_ACPI_HOTPLUG_CPU=y
-CONFIG_ACPI_THERMAL=m
-CONFIG_ACPI_NUMA=y
-CONFIG_ACPI_BLACKLIST_YEAR=0
-# CONFIG_ACPI_DEBUG is not set
-CONFIG_ACPI_EC=y
-CONFIG_ACPI_POWER=y
-CONFIG_ACPI_SYSTEM=y
-CONFIG_ACPI_CONTAINER=m
-
-#
-# CPU Frequency scaling
-#
-# CONFIG_CPU_FREQ is not set
-
-#
-# Bus options (PCI, PCMCIA)
-#
-CONFIG_PCI=y
-CONFIG_PCI_DOMAINS=y
-# CONFIG_PCI_MSI is not set
-CONFIG_PCI_LEGACY_PROC=y
-# CONFIG_PCI_DEBUG is not set
-
-#
-# PCI Hotplug Support
-#
-CONFIG_HOTPLUG_PCI=m
-# CONFIG_HOTPLUG_PCI_FAKE is not set
-CONFIG_HOTPLUG_PCI_ACPI=m
-# CONFIG_HOTPLUG_PCI_ACPI_IBM is not set
-# CONFIG_HOTPLUG_PCI_CPCI is not set
-# CONFIG_HOTPLUG_PCI_SHPC is not set
-# CONFIG_HOTPLUG_PCI_SGI is not set
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
-# CONFIG_PCCARD is not set
-
-#
-# Networking
-#
-CONFIG_NET=y
-
-#
-# Networking options
-#
-# CONFIG_NETDEBUG is not set
-CONFIG_PACKET=y
-# CONFIG_PACKET_MMAP is not set
-CONFIG_UNIX=y
-# CONFIG_NET_KEY is not set
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_FIB_HASH=y
-# CONFIG_IP_PNP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_IP_MROUTE is not set
+CONFIG_AGP_HP_ZX1=m
+CONFIG_AGP_I460=m
+CONFIG_AGP=m
+CONFIG_AGP_SGI_TIOCA=m
 CONFIG_ARPD=y
-CONFIG_SYN_COOKIES=y
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_TUNNEL is not set
-CONFIG_INET_DIAG=y
-CONFIG_INET_TCP_DIAG=y
-# CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TCP_CONG_BIC=y
-# CONFIG_IPV6 is not set
-# CONFIG_NETFILTER is not set
-
-#
-# DCCP Configuration (EXPERIMENTAL)
-#
-# CONFIG_IP_DCCP is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
-# CONFIG_IP_SCTP is not set
-
-#
-# TIPC Configuration (EXPERIMENTAL)
-#
-# CONFIG_TIPC is not set
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_NET_DIVERT is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
-# CONFIG_NET_SCHED is not set
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_HAMRADIO is not set
-# CONFIG_IRDA is not set
-# CONFIG_BT is not set
-# CONFIG_IEEE80211 is not set
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=m
-# CONFIG_DEBUG_DRIVER is not set
-
-#
-# Connector - unified userspace <-> kernelspace linker
-#
-# CONFIG_CONNECTOR is not set
-
-#
-# Memory Technology Devices (MTD)
-#
-# CONFIG_MTD is not set
-
-#
-# Parallel port support
-#
-# CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-CONFIG_PNP=y
-# CONFIG_PNP_DEBUG is not set
-
-#
-# Protocols
-#
-CONFIG_PNPACPI=y
-
-#
-# Block devices
-#
-# CONFIG_BLK_CPQ_DA is not set
-# CONFIG_BLK_CPQ_CISS_DA is not set
-# CONFIG_BLK_DEV_DAC960 is not set
-# CONFIG_BLK_DEV_UMEM is not set
-# CONFIG_BLK_DEV_COW_COMMON is not set
-CONFIG_BLK_DEV_LOOP=m
+CONFIG_AUTOFS4_FS=y
+CONFIG_AUTOFS_FS=y
+CONFIG_BINFMT_MISC=m
+CONFIG_BLK_DEV_CMD64X=y
 CONFIG_BLK_DEV_CRYPTOLOOP=m
-CONFIG_BLK_DEV_NBD=m
-# CONFIG_BLK_DEV_SX8 is not set
-# CONFIG_BLK_DEV_UB is not set
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=4096
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CDROM_PKTCDVD is not set
-# CONFIG_ATA_OVER_ETH is not set
-
-#
-# ATA/ATAPI/MFM/RLL support
-#
-CONFIG_IDE=y
-CONFIG_IDE_MAX_HWIFS=4
-CONFIG_BLK_DEV_IDE=y
-
-#
-# Please see Documentation/ide.txt for help/info on IDE drives
-#
-# CONFIG_BLK_DEV_IDE_SATA is not set
-CONFIG_BLK_DEV_IDEDISK=y
-# CONFIG_IDEDISK_MULTI_MODE is not set
-CONFIG_BLK_DEV_IDECD=y
-# CONFIG_BLK_DEV_IDETAPE is not set
-CONFIG_BLK_DEV_IDEFLOPPY=y
-CONFIG_BLK_DEV_IDESCSI=m
-# CONFIG_IDE_TASK_IOCTL is not set
-
-#
-# IDE chipset support/bugfixes
-#
-CONFIG_IDE_GENERIC=y
-# CONFIG_BLK_DEV_IDEPNP is not set
-CONFIG_BLK_DEV_IDEPCI=y
-# CONFIG_IDEPCI_SHARE_IRQ is not set
-# CONFIG_BLK_DEV_OFFBOARD is not set
+CONFIG_BLK_DEV_DM=m
 CONFIG_BLK_DEV_GENERIC=y
-# CONFIG_BLK_DEV_OPTI621 is not set
-CONFIG_BLK_DEV_IDEDMA_PCI=y
-# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
-CONFIG_IDEDMA_PCI_AUTO=y
-# CONFIG_IDEDMA_ONLYDISK is not set
-# CONFIG_BLK_DEV_AEC62XX is not set
-# CONFIG_BLK_DEV_ALI15X3 is not set
-# CONFIG_BLK_DEV_AMD74XX is not set
-CONFIG_BLK_DEV_CMD64X=y
-# CONFIG_BLK_DEV_TRIFLEX is not set
-# CONFIG_BLK_DEV_CY82C693 is not set
-# CONFIG_BLK_DEV_CS5520 is not set
-# CONFIG_BLK_DEV_CS5530 is not set
-# CONFIG_BLK_DEV_HPT34X is not set
-# CONFIG_BLK_DEV_HPT366 is not set
-# CONFIG_BLK_DEV_SC1200 is not set
+CONFIG_BLK_DEV_IDECD=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_BLK_DEV_LOOP=m
+CONFIG_BLK_DEV_MD=m
+CONFIG_BLK_DEV_NBD=m
 CONFIG_BLK_DEV_PIIX=y
-# CONFIG_BLK_DEV_IT821X is not set
-# CONFIG_BLK_DEV_NS87415 is not set
-# CONFIG_BLK_DEV_PDC202XX_OLD is not set
-# CONFIG_BLK_DEV_PDC202XX_NEW is not set
-# CONFIG_BLK_DEV_SVWKS is not set
-CONFIG_BLK_DEV_SGIIOC4=y
-# CONFIG_BLK_DEV_SIIMAGE is not set
-# CONFIG_BLK_DEV_SLC90E66 is not set
-# CONFIG_BLK_DEV_TRM290 is not set
-# CONFIG_BLK_DEV_VIA82CXXX is not set
-# CONFIG_IDE_ARM is not set
-CONFIG_BLK_DEV_IDEDMA=y
-# CONFIG_IDEDMA_IVB is not set
-CONFIG_IDEDMA_AUTO=y
-# CONFIG_BLK_DEV_HD is not set
-
-#
-# SCSI device support
-#
-# CONFIG_RAID_ATTRS is not set
-CONFIG_SCSI=y
-CONFIG_SCSI_PROC_FS=y
-
-#
-# SCSI support type (disk, tape, CD-ROM)
-#
+CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_SD=y
-CONFIG_CHR_DEV_ST=m
-# CONFIG_CHR_DEV_OSST is not set
+CONFIG_BLK_DEV_SGIIOC4=y
 CONFIG_BLK_DEV_SR=m
-# CONFIG_BLK_DEV_SR_VENDOR is not set
 CONFIG_CHR_DEV_SG=m
-# CONFIG_CHR_DEV_SCH is not set
-
-#
-# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
-#
-# CONFIG_SCSI_MULTI_LUN is not set
-# CONFIG_SCSI_CONSTANTS is not set
-# CONFIG_SCSI_LOGGING is not set
-
-#
-# SCSI Transport Attributes
-#
-CONFIG_SCSI_SPI_ATTRS=y
-CONFIG_SCSI_FC_ATTRS=y
-# CONFIG_SCSI_ISCSI_ATTRS is not set
-# CONFIG_SCSI_SAS_ATTRS is not set
-
-#
-# SCSI low-level drivers
-#
-# CONFIG_ISCSI_TCP is not set
-# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
-# CONFIG_SCSI_3W_9XXX is not set
-# CONFIG_SCSI_ACARD is not set
-# CONFIG_SCSI_AACRAID is not set
-# CONFIG_SCSI_AIC7XXX is not set
-# CONFIG_SCSI_AIC7XXX_OLD is not set
-# CONFIG_SCSI_AIC79XX is not set
-# CONFIG_MEGARAID_NEWGEN is not set
-# CONFIG_MEGARAID_LEGACY is not set
-# CONFIG_MEGARAID_SAS is not set
-CONFIG_SCSI_SATA=y
-# CONFIG_SCSI_SATA_AHCI is not set
-# CONFIG_SCSI_SATA_SVW is not set
-# CONFIG_SCSI_ATA_PIIX is not set
-# CONFIG_SCSI_SATA_MV is not set
-# CONFIG_SCSI_SATA_NV is not set
-# CONFIG_SCSI_PDC_ADMA is not set
-# CONFIG_SCSI_SATA_QSTOR is not set
-# CONFIG_SCSI_SATA_PROMISE is not set
-# CONFIG_SCSI_SATA_SX4 is not set
-# CONFIG_SCSI_SATA_SIL is not set
-# CONFIG_SCSI_SATA_SIL24 is not set
-# CONFIG_SCSI_SATA_SIS is not set
-# CONFIG_SCSI_SATA_ULI is not set
-# CONFIG_SCSI_SATA_VIA is not set
-CONFIG_SCSI_SATA_VITESSE=y
-# CONFIG_SCSI_DMX3191D is not set
-# CONFIG_SCSI_FUTURE_DOMAIN is not set
-# CONFIG_SCSI_IPS is not set
-# CONFIG_SCSI_INITIO is not set
-# CONFIG_SCSI_INIA100 is not set
-CONFIG_SCSI_SYM53C8XX_2=y
-CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1
-CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16
-CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64
-# CONFIG_SCSI_SYM53C8XX_IOMAPPED is not set
-# CONFIG_SCSI_IPR is not set
-# CONFIG_SCSI_QLOGIC_FC is not set
-CONFIG_SCSI_QLOGIC_1280=y
-# CONFIG_SCSI_QLA_FC is not set
-# CONFIG_SCSI_LPFC is not set
-# CONFIG_SCSI_DC395x is not set
-# CONFIG_SCSI_DC390T is not set
-# CONFIG_SCSI_DEBUG is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
-CONFIG_MD=y
-CONFIG_BLK_DEV_MD=m
-CONFIG_MD_LINEAR=m
-CONFIG_MD_RAID0=m
-CONFIG_MD_RAID1=m
-# CONFIG_MD_RAID10 is not set
-CONFIG_MD_RAID5=m
-CONFIG_MD_RAID6=m
-CONFIG_MD_MULTIPATH=m
-# CONFIG_MD_FAULTY is not set
-CONFIG_BLK_DEV_DM=m
+CONFIG_CHR_DEV_ST=m
+CONFIG_CIFS=m
+CONFIG_CRYPTO_MD5=y
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_MUTEXES=y
 CONFIG_DM_CRYPT=m
-CONFIG_DM_SNAPSHOT=m
 CONFIG_DM_MIRROR=m
-CONFIG_DM_ZERO=m
 CONFIG_DM_MULTIPATH=m
-# CONFIG_DM_MULTIPATH_EMC is not set
-
-#
-# Fusion MPT device support
-#
-CONFIG_FUSION=y
-CONFIG_FUSION_SPI=y
-CONFIG_FUSION_FC=m
-# CONFIG_FUSION_SAS is not set
-CONFIG_FUSION_MAX_SGE=128
-# CONFIG_FUSION_CTL is not set
-
-#
-# IEEE 1394 (FireWire) support
-#
-# CONFIG_IEEE1394 is not set
-
-#
-# I2O device support
-#
-# CONFIG_I2O is not set
-
-#
-# Network device support
-#
-CONFIG_NETDEVICES=y
-CONFIG_DUMMY=m
-# CONFIG_BONDING is not set
-# CONFIG_EQUALIZER is not set
-# CONFIG_TUN is not set
-# CONFIG_NET_SB1000 is not set
-
-#
-# ARCnet devices
-#
-# CONFIG_ARCNET is not set
-
-#
-# PHY device support
-#
-# CONFIG_PHYLIB is not set
-
-#
-# Ethernet (10 or 100Mbit)
-#
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=m
-# CONFIG_HAPPYMEAL is not set
-# CONFIG_SUNGEM is not set
-# CONFIG_CASSINI is not set
-# CONFIG_NET_VENDOR_3COM is not set
-
-#
-# Tulip family network device support
-#
-CONFIG_NET_TULIP=y
-# CONFIG_DE2104X is not set
-CONFIG_TULIP=m
-# CONFIG_TULIP_MWI is not set
-# CONFIG_TULIP_MMIO is not set
-# CONFIG_TULIP_NAPI is not set
-# CONFIG_DE4X5 is not set
-# CONFIG_WINBOND_840 is not set
-# CONFIG_DM9102 is not set
-# CONFIG_ULI526X is not set
-# CONFIG_HP100 is not set
-CONFIG_NET_PCI=y
-# CONFIG_PCNET32 is not set
-# CONFIG_AMD8111_ETH is not set
-# CONFIG_ADAPTEC_STARFIRE is not set
-# CONFIG_B44 is not set
-# CONFIG_FORCEDETH is not set
-# CONFIG_DGRS is not set
-CONFIG_EEPRO100=m
-CONFIG_E100=m
-# CONFIG_FEALNX is not set
-# CONFIG_NATSEMI is not set
-# CONFIG_NE2K_PCI is not set
-# CONFIG_8139CP is not set
-# CONFIG_8139TOO is not set
-# CONFIG_SIS900 is not set
-# CONFIG_EPIC100 is not set
-# CONFIG_SUNDANCE is not set
-# CONFIG_VIA_RHINE is not set
-
-#
-# Ethernet (1000 Mbit)
-#
-# CONFIG_ACENIC is not set
-# CONFIG_DL2K is not set
-CONFIG_E1000=y
-# CONFIG_E1000_NAPI is not set
-# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set
-# CONFIG_NS83820 is not set
-# CONFIG_HAMACHI is not set
-# CONFIG_YELLOWFIN is not set
-# CONFIG_R8169 is not set
-# CONFIG_SIS190 is not set
-# CONFIG_SKGE is not set
-# CONFIG_SKY2 is not set
-# CONFIG_SK98LIN is not set
-# CONFIG_VIA_VELOCITY is not set
-CONFIG_TIGON3=y
-# CONFIG_BNX2 is not set
-
-#
-# Ethernet (10000 Mbit)
-#
-# CONFIG_CHELSIO_T1 is not set
-# CONFIG_IXGB is not set
-# CONFIG_S2IO is not set
-
-#
-# Token Ring devices
-#
-# CONFIG_TR is not set
-
-#
-# Wireless LAN (non-hamradio)
-#
-# CONFIG_NET_RADIO is not set
-
-#
-# Wan interfaces
-#
-# CONFIG_WAN is not set
-# CONFIG_FDDI is not set
-# CONFIG_HIPPI is not set
-# CONFIG_PPP is not set
-# CONFIG_SLIP is not set
-# CONFIG_NET_FC is not set
-# CONFIG_SHAPER is not set
-CONFIG_NETCONSOLE=y
-CONFIG_NETPOLL=y
-# CONFIG_NETPOLL_RX is not set
-# CONFIG_NETPOLL_TRAP is not set
-CONFIG_NET_POLL_CONTROLLER=y
-
-#
-# ISDN subsystem
-#
-# CONFIG_ISDN is not set
-
-#
-# Telephony Support
-#
-# CONFIG_PHONE is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-
-#
-# Userland interfaces
-#
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-# CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
-# CONFIG_INPUT_EVDEV is not set
-# CONFIG_INPUT_EVBUG is not set
-
-#
-# Input Device Drivers
-#
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_KEYBOARD_ATKBD=y
-# CONFIG_KEYBOARD_SUNKBD is not set
-# CONFIG_KEYBOARD_LKKBD is not set
-# CONFIG_KEYBOARD_XTKBD is not set
-# CONFIG_KEYBOARD_NEWTON is not set
-CONFIG_INPUT_MOUSE=y
-CONFIG_MOUSE_PS2=y
-# CONFIG_MOUSE_SERIAL is not set
-# CONFIG_MOUSE_VSXXXAA is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TOUCHSCREEN is not set
-# CONFIG_INPUT_MISC is not set
-
-#
-# Hardware I/O ports
-#
-CONFIG_SERIO=y
-CONFIG_SERIO_I8042=y
-# CONFIG_SERIO_SERPORT is not set
-# CONFIG_SERIO_PCIPS2 is not set
-CONFIG_SERIO_LIBPS2=y
-# CONFIG_SERIO_RAW is not set
-CONFIG_GAMEPORT=m
-# CONFIG_GAMEPORT_NS558 is not set
-# CONFIG_GAMEPORT_L4 is not set
-# CONFIG_GAMEPORT_EMU10K1 is not set
-# CONFIG_GAMEPORT_FM801 is not set
-
-#
-# Character devices
-#
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-CONFIG_SERIAL_NONSTANDARD=y
-# CONFIG_COMPUTONE is not set
-# CONFIG_ROCKETPORT is not set
-# CONFIG_CYCLADES is not set
-# CONFIG_DIGIEPCA is not set
-# CONFIG_MOXA_INTELLIO is not set
-# CONFIG_MOXA_SMARTIO is not set
-# CONFIG_ISI is not set
-# CONFIG_SYNCLINKMP is not set
-# CONFIG_SYNCLINK_GT is not set
-# CONFIG_N_HDLC is not set
-# CONFIG_SPECIALIX is not set
-# CONFIG_SX is not set
-# CONFIG_STALDRV is not set
-CONFIG_SGI_SNSC=y
-CONFIG_SGI_TIOCX=y
-CONFIG_SGI_MBCS=m
-
-#
-# Serial drivers
-#
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_ACPI=y
-CONFIG_SERIAL_8250_NR_UARTS=6
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-# CONFIG_SERIAL_8250_DETECT_IRQ is not set
-# CONFIG_SERIAL_8250_RSA is not set
-
-#
-# Non-8250 serial port support
-#
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-CONFIG_SERIAL_SGI_L1_CONSOLE=y
-# CONFIG_SERIAL_JSM is not set
-CONFIG_SERIAL_SGI_IOC4=y
-CONFIG_SERIAL_SGI_IOC3=y
-CONFIG_UNIX98_PTYS=y
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
-# CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-# CONFIG_WATCHDOG is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_EFI_RTC=y
-# CONFIG_DTLK is not set
-# CONFIG_R3964 is not set
-# CONFIG_APPLICOM is not set
-
-#
-# Ftape, the floppy tape device driver
-#
-CONFIG_AGP=m
-CONFIG_AGP_I460=m
-CONFIG_AGP_HP_ZX1=m
-CONFIG_AGP_SGI_TIOCA=m
+CONFIG_DM_SNAPSHOT=m
+CONFIG_DM_ZERO=m
 CONFIG_DRM=m
-CONFIG_DRM_TDFX=m
+CONFIG_DRM_MGA=m
 CONFIG_DRM_R128=m
 CONFIG_DRM_RADEON=m
-CONFIG_DRM_MGA=m
 CONFIG_DRM_SIS=m
-# CONFIG_DRM_VIA is not set
-# CONFIG_DRM_SAVAGE is not set
-CONFIG_RAW_DRIVER=m
-CONFIG_MAX_RAW_DEVS=256
-CONFIG_HPET=y
-# CONFIG_HPET_RTC_IRQ is not set
-CONFIG_HPET_MMAP=y
-# CONFIG_HANGCHECK_TIMER is not set
-CONFIG_MMTIMER=y
-
-#
-# TPM devices
-#
-# CONFIG_TCG_TPM is not set
-# CONFIG_TELCLOCK is not set
-
-#
-# I2C support
-#
-# CONFIG_I2C is not set
-
-#
-# SPI support
-#
-# CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
-
-#
-# Dallas's 1-wire bus
-#
-# CONFIG_W1 is not set
-
-#
-# Hardware Monitoring support
-#
-CONFIG_HWMON=y
-# CONFIG_HWMON_VID is not set
-# CONFIG_SENSORS_F71805F is not set
-# CONFIG_HWMON_DEBUG_CHIP is not set
-
-#
-# Misc devices
-#
-
-#
-# Multimedia Capabilities Port drivers
-#
-
-#
-# Multimedia devices
-#
-# CONFIG_VIDEO_DEV is not set
-
-#
-# Digital Video Broadcasting Devices
-#
-# CONFIG_DVB is not set
-
-#
-# Graphics support
-#
-# CONFIG_FB is not set
-
-#
-# Console display driver support
-#
-CONFIG_VGA_CONSOLE=y
-CONFIG_DUMMY_CONSOLE=y
-
-#
-# Sound
-#
-CONFIG_SOUND=m
-
-#
-# Advanced Linux Sound Architecture
-#
-CONFIG_SND=m
-CONFIG_SND_TIMER=m
-CONFIG_SND_PCM=m
-CONFIG_SND_HWDEP=m
-CONFIG_SND_RAWMIDI=m
-CONFIG_SND_SEQUENCER=m
-CONFIG_SND_SEQ_DUMMY=m
-CONFIG_SND_OSSEMUL=y
-CONFIG_SND_MIXER_OSS=m
-CONFIG_SND_PCM_OSS=m
-CONFIG_SND_SEQUENCER_OSS=y
-# CONFIG_SND_DYNAMIC_MINORS is not set
-CONFIG_SND_SUPPORT_OLD_API=y
-CONFIG_SND_VERBOSE_PRINTK=y
-# CONFIG_SND_DEBUG is not set
-
-#
-# Generic devices
-#
-CONFIG_SND_MPU401_UART=m
-CONFIG_SND_OPL3_LIB=m
-CONFIG_SND_AC97_CODEC=m
-CONFIG_SND_AC97_BUS=m
-CONFIG_SND_DUMMY=m
-CONFIG_SND_VIRMIDI=m
-CONFIG_SND_MTPAV=m
-CONFIG_SND_SERIAL_U16550=m
-CONFIG_SND_MPU401=m
-
-#
-# PCI devices
-#
-# CONFIG_SND_AD1889 is not set
-# CONFIG_SND_ALI5451 is not set
-# CONFIG_SND_ATIIXP is not set
-# CONFIG_SND_ATIIXP_MODEM is not set
-# CONFIG_SND_AU8810 is not set
-# CONFIG_SND_AU8820 is not set
-# CONFIG_SND_AU8830 is not set
-# CONFIG_SND_AZT3328 is not set
-# CONFIG_SND_BT87X is not set
-# CONFIG_SND_CA0106 is not set
-# CONFIG_SND_CMIPCI is not set
-CONFIG_SND_CS4281=m
-CONFIG_SND_CS46XX=m
-CONFIG_SND_CS46XX_NEW_DSP=y
-CONFIG_SND_EMU10K1=m
-# CONFIG_SND_EMU10K1X is not set
-# CONFIG_SND_ENS1370 is not set
-# CONFIG_SND_ENS1371 is not set
-# CONFIG_SND_ES1938 is not set
-# CONFIG_SND_ES1968 is not set
-CONFIG_SND_FM801=m
-# CONFIG_SND_FM801_TEA575X is not set
-# CONFIG_SND_HDA_INTEL is not set
-# CONFIG_SND_HDSP is not set
-# CONFIG_SND_HDSPM is not set
-# CONFIG_SND_ICE1712 is not set
-# CONFIG_SND_ICE1724 is not set
-# CONFIG_SND_INTEL8X0 is not set
-# CONFIG_SND_INTEL8X0M is not set
-# CONFIG_SND_KORG1212 is not set
-# CONFIG_SND_MAESTRO3 is not set
-# CONFIG_SND_MIXART is not set
-# CONFIG_SND_NM256 is not set
-# CONFIG_SND_PCXHR is not set
-# CONFIG_SND_RME32 is not set
-# CONFIG_SND_RME96 is not set
-# CONFIG_SND_RME9652 is not set
-# CONFIG_SND_SONICVIBES is not set
-# CONFIG_SND_TRIDENT is not set
-# CONFIG_SND_VIA82XX is not set
-# CONFIG_SND_VIA82XX_MODEM is not set
-# CONFIG_SND_VX222 is not set
-# CONFIG_SND_YMFPCI is not set
-
-#
-# USB devices
-#
-# CONFIG_SND_USB_AUDIO is not set
-
-#
-# Open Sound System
-#
-# CONFIG_SOUND_PRIME is not set
-
-#
-# USB support
-#
-CONFIG_USB_ARCH_HAS_HCD=y
-CONFIG_USB_ARCH_HAS_OHCI=y
-CONFIG_USB=m
-# CONFIG_USB_DEBUG is not set
-
-#
-# Miscellaneous USB options
-#
-CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_BANDWIDTH is not set
-# CONFIG_USB_DYNAMIC_MINORS is not set
-# CONFIG_USB_SUSPEND is not set
-# CONFIG_USB_OTG is not set
-
-#
-# USB Host Controller Drivers
-#
-CONFIG_USB_EHCI_HCD=m
-# CONFIG_USB_EHCI_SPLIT_ISO is not set
-# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
-# CONFIG_USB_ISP116X_HCD is not set
-CONFIG_USB_OHCI_HCD=m
-# CONFIG_USB_OHCI_BIG_ENDIAN is not set
-CONFIG_USB_OHCI_LITTLE_ENDIAN=y
-CONFIG_USB_UHCI_HCD=m
-# CONFIG_USB_SL811_HCD is not set
-
-#
-# USB Device Class drivers
-#
-# CONFIG_OBSOLETE_OSS_USB_DRIVER is not set
-# CONFIG_USB_ACM is not set
-# CONFIG_USB_PRINTER is not set
-
-#
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
-#
-
-#
-# may also be needed; see USB_STORAGE Help for more information
-#
-CONFIG_USB_STORAGE=m
-# CONFIG_USB_STORAGE_DEBUG is not set
-# CONFIG_USB_STORAGE_DATAFAB is not set
-# CONFIG_USB_STORAGE_FREECOM is not set
-# CONFIG_USB_STORAGE_ISD200 is not set
-# CONFIG_USB_STORAGE_DPCM is not set
-# CONFIG_USB_STORAGE_USBAT is not set
-# CONFIG_USB_STORAGE_SDDR09 is not set
-# CONFIG_USB_STORAGE_SDDR55 is not set
-# CONFIG_USB_STORAGE_JUMPSHOT is not set
-# CONFIG_USB_STORAGE_ALAUDA is not set
-# CONFIG_USB_LIBUSUAL is not set
-
-#
-# USB Input Devices
-#
-CONFIG_USB_HID=m
-CONFIG_USB_HIDINPUT=y
-# CONFIG_USB_HIDINPUT_POWERBOOK is not set
-# CONFIG_HID_FF is not set
-# CONFIG_USB_HIDDEV is not set
-
-#
-# USB HID Boot Protocol drivers
-#
-# CONFIG_USB_KBD is not set
-# CONFIG_USB_MOUSE is not set
-# CONFIG_USB_AIPTEK is not set
-# CONFIG_USB_WACOM is not set
-# CONFIG_USB_ACECAD is not set
-# CONFIG_USB_KBTAB is not set
-# CONFIG_USB_POWERMATE is not set
-# CONFIG_USB_MTOUCH is not set
-# CONFIG_USB_ITMTOUCH is not set
-# CONFIG_USB_EGALAX is not set
-# CONFIG_USB_YEALINK is not set
-# CONFIG_USB_XPAD is not set
-# CONFIG_USB_ATI_REMOTE is not set
-# CONFIG_USB_ATI_REMOTE2 is not set
-# CONFIG_USB_KEYSPAN_REMOTE is not set
-# CONFIG_USB_APPLETOUCH is not set
-
-#
-# USB Imaging devices
-#
-# CONFIG_USB_MDC800 is not set
-# CONFIG_USB_MICROTEK is not set
-
-#
-# USB Multimedia devices
-#
-# CONFIG_USB_DABUSB is not set
-
-#
-# Video4Linux support is needed for USB Multimedia device support
-#
-
-#
-# USB Network Adapters
-#
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_RTL8150 is not set
-# CONFIG_USB_USBNET is not set
-CONFIG_USB_MON=y
-
-#
-# USB port drivers
-#
-
-#
-# USB Serial Converter support
-#
-# CONFIG_USB_SERIAL is not set
-
-#
-# USB Miscellaneous drivers
-#
-# CONFIG_USB_EMI62 is not set
-# CONFIG_USB_EMI26 is not set
-# CONFIG_USB_AUERSWALD is not set
-# CONFIG_USB_RIO500 is not set
-# CONFIG_USB_LEGOTOWER is not set
-# CONFIG_USB_LCD is not set
-# CONFIG_USB_LED is not set
-# CONFIG_USB_CYTHERM is not set
-# CONFIG_USB_PHIDGETKIT is not set
-# CONFIG_USB_PHIDGETSERVO is not set
-# CONFIG_USB_IDMOUSE is not set
-# CONFIG_USB_SISUSBVGA is not set
-# CONFIG_USB_LD is not set
-# CONFIG_USB_TEST is not set
-
-#
-# USB DSL modem support
-#
-
-#
-# USB Gadget Support
-#
-# CONFIG_USB_GADGET is not set
-
-#
-# MMC/SD Card support
-#
-# CONFIG_MMC is not set
-
-#
-# InfiniBand support
-#
-CONFIG_INFINIBAND=m
-# CONFIG_INFINIBAND_USER_MAD is not set
-# CONFIG_INFINIBAND_USER_ACCESS is not set
-CONFIG_INFINIBAND_MTHCA=m
-# CONFIG_INFINIBAND_MTHCA_DEBUG is not set
-CONFIG_INFINIBAND_IPOIB=m
-# CONFIG_INFINIBAND_IPOIB_DEBUG is not set
-# CONFIG_INFINIBAND_SRP is not set
-
-#
-# SN Devices
-#
-CONFIG_SGI_IOC4=y
-CONFIG_SGI_IOC3=y
-
-#
-# EDAC - error detection and reporting (RAS)
-#
-
-#
-# File systems
-#
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
+CONFIG_DRM_TDFX=m
+CONFIG_DUMMY=m
+CONFIG_E1000=y
+CONFIG_E100=m
+CONFIG_EFI_PARTITION=y
+CONFIG_EFI_RTC=y
+CONFIG_EFI_VARS=y
+CONFIG_EXPERIMENTAL=y
 CONFIG_EXT2_FS_POSIX_ACL=y
 CONFIG_EXT2_FS_SECURITY=y
-# CONFIG_EXT2_FS_XIP is not set
-CONFIG_EXT3_FS=y
-CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS_POSIX_ACL=y
 CONFIG_EXT3_FS_SECURITY=y
-CONFIG_JBD=y
-# CONFIG_JBD_DEBUG is not set
-CONFIG_FS_MBCACHE=y
-CONFIG_REISERFS_FS=y
-# CONFIG_REISERFS_CHECK is not set
-# CONFIG_REISERFS_PROC_INFO is not set
-CONFIG_REISERFS_FS_XATTR=y
-CONFIG_REISERFS_FS_POSIX_ACL=y
-CONFIG_REISERFS_FS_SECURITY=y
-# CONFIG_JFS_FS is not set
-CONFIG_FS_POSIX_ACL=y
-CONFIG_XFS_FS=y
-CONFIG_XFS_EXPORT=y
-# CONFIG_XFS_QUOTA is not set
-# CONFIG_XFS_SECURITY is not set
-# CONFIG_XFS_POSIX_ACL is not set
-# CONFIG_XFS_RT is not set
-# CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
+CONFIG_EXT3_FS=y
+CONFIG_FUSION_FC=m
+CONFIG_FUSION_SPI=y
+CONFIG_FUSION=y
+CONFIG_GAMEPORT=m
+CONFIG_HOTPLUG_CPU=y
+CONFIG_HOTPLUG_PCI_ACPI=m
+CONFIG_HOTPLUG_PCI=m
+CONFIG_HPET=y
+CONFIG_HUGETLBFS=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_IA64_CYCLONE=y
+CONFIG_IA64_MCA_RECOVERY=y
+CONFIG_IA64_PALINFO=y
+CONFIG_IDE_GENERIC=y
+CONFIG_IDE=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_IKCONFIG=y
+CONFIG_INET=y
+CONFIG_INFINIBAND_IPOIB=m
+CONFIG_INFINIBAND=m
+CONFIG_INFINIBAND_MTHCA=m
 CONFIG_INOTIFY=y
-# CONFIG_QUOTA is not set
-CONFIG_DNOTIFY=y
-CONFIG_AUTOFS_FS=y
-CONFIG_AUTOFS4_FS=y
-# CONFIG_FUSE_FS is not set
-
-#
-# CD-ROM/DVD Filesystems
-#
+CONFIG_IP_MULTICAST=y
+# CONFIG_IPV6 is not set
 CONFIG_ISO9660_FS=m
 CONFIG_JOLIET=y
-# CONFIG_ZISOFS is not set
-CONFIG_UDF_FS=m
-CONFIG_UDF_NLS=y
-
-#
-# DOS/FAT/NT Filesystems
-#
-CONFIG_FAT_FS=y
-# CONFIG_MSDOS_FS is not set
-CONFIG_VFAT_FS=y
-CONFIG_FAT_DEFAULT_CODEPAGE=437
-CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-CONFIG_NTFS_FS=m
-# CONFIG_NTFS_DEBUG is not set
-# CONFIG_NTFS_RW is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_KCORE=y
-CONFIG_SYSFS=y
-CONFIG_TMPFS=y
-CONFIG_HUGETLBFS=y
-CONFIG_HUGETLB_PAGE=y
-CONFIG_RAMFS=y
-# CONFIG_RELAYFS_FS is not set
-# CONFIG_CONFIGFS_FS is not set
-
-#
-# Miscellaneous filesystems
-#
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-# CONFIG_CRAMFS is not set
-# CONFIG_VXFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
+CONFIG_KALLSYMS_ALL=y
+CONFIG_LOG_BUF_SHIFT=20
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MCKINLEY=y
+CONFIG_MD_LINEAR=m
+CONFIG_MD_MULTIPATH=m
+CONFIG_MD_RAID0=m
+CONFIG_MD_RAID1=m
+CONFIG_MD=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_NETCONSOLE=y
+CONFIG_NETDEVICES=y
+CONFIG_NET_ETHERNET=y
+CONFIG_NET_PCI=y
+CONFIG_NET_TULIP=y
+CONFIG_NFSD=m
+CONFIG_NFSD_V4=y
 CONFIG_NFS_FS=m
 CONFIG_NFS_V3=y
-# CONFIG_NFS_V3_ACL is not set
 CONFIG_NFS_V4=y
-CONFIG_NFS_DIRECTIO=y
-CONFIG_NFSD=m
-CONFIG_NFSD_V3=y
-# CONFIG_NFSD_V3_ACL is not set
-CONFIG_NFSD_V4=y
-CONFIG_NFSD_TCP=y
-CONFIG_LOCKD=m
-CONFIG_LOCKD_V4=y
-CONFIG_EXPORTFS=y
-CONFIG_NFS_COMMON=y
-CONFIG_SUNRPC=m
-CONFIG_SUNRPC_GSS=m
-CONFIG_RPCSEC_GSS_KRB5=m
-# CONFIG_RPCSEC_GSS_SPKM3 is not set
-CONFIG_SMB_FS=m
-CONFIG_SMB_NLS_DEFAULT=y
-CONFIG_SMB_NLS_REMOTE="cp437"
-CONFIG_CIFS=m
-# CONFIG_CIFS_STATS is not set
-# CONFIG_CIFS_XATTR is not set
-# CONFIG_CIFS_EXPERIMENTAL is not set
-# CONFIG_NCP_FS is not set
-# CONFIG_CODA_FS is not set
-# CONFIG_AFS_FS is not set
-# CONFIG_9P_FS is not set
-
-#
-# Partition Types
-#
-CONFIG_PARTITION_ADVANCED=y
-# CONFIG_ACORN_PARTITION is not set
-# CONFIG_OSF_PARTITION is not set
-# CONFIG_AMIGA_PARTITION is not set
-# CONFIG_ATARI_PARTITION is not set
-# CONFIG_MAC_PARTITION is not set
-CONFIG_MSDOS_PARTITION=y
-# CONFIG_BSD_DISKLABEL is not set
-# CONFIG_MINIX_SUBPARTITION is not set
-# CONFIG_SOLARIS_X86_PARTITION is not set
-# CONFIG_UNIXWARE_DISKLABEL is not set
-# CONFIG_LDM_PARTITION is not set
-CONFIG_SGI_PARTITION=y
-# CONFIG_ULTRIX_PARTITION is not set
-# CONFIG_SUN_PARTITION is not set
-# CONFIG_KARMA_PARTITION is not set
-CONFIG_EFI_PARTITION=y
-
-#
-# Native Language Support
-#
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_1250=m
+CONFIG_NLS_CODEPAGE_1251=m
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_737=m
 CONFIG_NLS_CODEPAGE_775=m
@@ -1277,15 +120,14 @@ CONFIG_NLS_CODEPAGE_864=m
 CONFIG_NLS_CODEPAGE_865=m
 CONFIG_NLS_CODEPAGE_866=m
 CONFIG_NLS_CODEPAGE_869=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_CODEPAGE_950=m
+CONFIG_NLS_CODEPAGE_874=m
 CONFIG_NLS_CODEPAGE_932=m
+CONFIG_NLS_CODEPAGE_936=m
 CONFIG_NLS_CODEPAGE_949=m
-CONFIG_NLS_CODEPAGE_874=m
-CONFIG_NLS_ISO8859_8=m
-CONFIG_NLS_CODEPAGE_1250=m
-CONFIG_NLS_CODEPAGE_1251=m
-# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_CODEPAGE_950=m
+CONFIG_NLS_ISO8859_13=m
+CONFIG_NLS_ISO8859_14=m
+CONFIG_NLS_ISO8859_15=m
 CONFIG_NLS_ISO8859_1=y
 CONFIG_NLS_ISO8859_2=m
 CONFIG_NLS_ISO8859_3=m
@@ -1293,100 +135,77 @@ CONFIG_NLS_ISO8859_4=m
 CONFIG_NLS_ISO8859_5=m
 CONFIG_NLS_ISO8859_6=m
 CONFIG_NLS_ISO8859_7=m
+CONFIG_NLS_ISO8859_8=m
 CONFIG_NLS_ISO8859_9=m
-CONFIG_NLS_ISO8859_13=m
-CONFIG_NLS_ISO8859_14=m
-CONFIG_NLS_ISO8859_15=m
 CONFIG_NLS_KOI8_R=m
 CONFIG_NLS_KOI8_U=m
 CONFIG_NLS_UTF8=m
-
-#
-# Library routines
-#
-# CONFIG_CRC_CCITT is not set
-# CONFIG_CRC16 is not set
-CONFIG_CRC32=y
-# CONFIG_LIBCRC32C is not set
-CONFIG_GENERIC_HARDIRQS=y
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_GENERIC_PENDING_IRQ=y
-
-#
-# HP Simulator drivers
-#
-# CONFIG_HP_SIMETH is not set
-# CONFIG_HP_SIMSERIAL is not set
-# CONFIG_HP_SIMSCSI is not set
-
-#
-# Instrumentation Support
-#
-# CONFIG_PROFILING is not set
-# CONFIG_KPROBES is not set
-
-#
-# Kernel hacking
-#
-# CONFIG_PRINTK_TIME is not set
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_LOG_BUF_SHIFT=20
-CONFIG_DETECT_SOFTLOCKUP=y
-# CONFIG_SCHEDSTATS is not set
-# CONFIG_DEBUG_SLAB is not set
-CONFIG_DEBUG_MUTEXES=y
-# CONFIG_DEBUG_SPINLOCK is not set
-# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-# CONFIG_DEBUG_KOBJECT is not set
-# CONFIG_DEBUG_INFO is not set
-# CONFIG_DEBUG_FS is not set
-# CONFIG_DEBUG_VM is not set
-CONFIG_FORCED_INLINING=y
-# CONFIG_RCU_TORTURE_TEST is not set
-CONFIG_IA64_GRANULE_16MB=y
-# CONFIG_IA64_GRANULE_64MB is not set
-# CONFIG_IA64_PRINT_HAZARDS is not set
-# CONFIG_DISABLE_VHPT is not set
-# CONFIG_IA64_DEBUG_CMPXCHG is not set
-# CONFIG_IA64_DEBUG_IRQ is not set
-CONFIG_SYSVIPC_COMPAT=y
-
-#
-# Security options
-#
-# CONFIG_KEYS is not set
-# CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
-CONFIG_CRYPTO=y
-# CONFIG_CRYPTO_HMAC is not set
-# CONFIG_CRYPTO_NULL is not set
-# CONFIG_CRYPTO_MD4 is not set
-CONFIG_CRYPTO_MD5=y
-# CONFIG_CRYPTO_SHA1 is not set
-# CONFIG_CRYPTO_SHA256 is not set
-# CONFIG_CRYPTO_SHA512 is not set
-# CONFIG_CRYPTO_WP512 is not set
-# CONFIG_CRYPTO_TGR192 is not set
-CONFIG_CRYPTO_DES=m
-# CONFIG_CRYPTO_BLOWFISH is not set
-# CONFIG_CRYPTO_TWOFISH is not set
-# CONFIG_CRYPTO_SERPENT is not set
-# CONFIG_CRYPTO_AES is not set
-# CONFIG_CRYPTO_CAST5 is not set
-# CONFIG_CRYPTO_CAST6 is not set
-# CONFIG_CRYPTO_TEA is not set
-# CONFIG_CRYPTO_ARC4 is not set
-# CONFIG_CRYPTO_KHAZAD is not set
-# CONFIG_CRYPTO_ANUBIS is not set
-# CONFIG_CRYPTO_DEFLATE is not set
-# CONFIG_CRYPTO_MICHAEL_MIC is not set
-# CONFIG_CRYPTO_CRC32C is not set
-# CONFIG_CRYPTO_TEST is not set
-
-#
-# Hardware crypto devices
-#
+CONFIG_NR_CPUS=512
+CONFIG_NTFS_FS=m
+CONFIG_PACKET=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_PERFMON=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_PROC_KCORE=y
+CONFIG_RAW_DRIVER=m
+CONFIG_REISERFS_FS_POSIX_ACL=y
+CONFIG_REISERFS_FS_SECURITY=y
+CONFIG_REISERFS_FS_XATTR=y
+CONFIG_REISERFS_FS=y
+CONFIG_SCSI_FC_ATTRS=y
+CONFIG_SCSI_QLOGIC_1280=y
+CONFIG_SCSI_SYM53C8XX_2=y
+CONFIG_SCSI=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_NR_UARTS=6
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_NONSTANDARD=y
+CONFIG_SERIAL_SGI_IOC3=y
+CONFIG_SERIAL_SGI_IOC4=y
+CONFIG_SERIAL_SGI_L1_CONSOLE=y
+# CONFIG_SERIO_SERPORT is not set
+CONFIG_SGI_IOC3=y
+CONFIG_SGI_IOC4=y
+CONFIG_SGI_MBCS=m
+CONFIG_SGI_PARTITION=y
+CONFIG_SGI_SNSC=y
+CONFIG_SGI_TIOCX=y
+CONFIG_SMB_FS=m
+CONFIG_SMB_NLS_DEFAULT=y
+CONFIG_SMP=y
+CONFIG_SND_CS4281=m
+CONFIG_SND_CS46XX=m
+CONFIG_SND_DUMMY=m
+CONFIG_SND_EMU10K1=m
+CONFIG_SND_FM801=m
+CONFIG_SND=m
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_MPU401=m
+CONFIG_SND_MTPAV=m
+CONFIG_SND_PCM_OSS=m
+CONFIG_SND_SEQ_DUMMY=m
+CONFIG_SND_SEQUENCER=m
+CONFIG_SND_SEQUENCER_OSS=y
+CONFIG_SND_SERIAL_U16550=m
+CONFIG_SND_VERBOSE_PRINTK=y
+CONFIG_SND_VIRMIDI=m
+CONFIG_SOUND=m
+CONFIG_SPARSEMEM_MANUAL=y
+CONFIG_SYN_COOKIES=y
+CONFIG_SYSVIPC=y
+CONFIG_TIGON3=y
+CONFIG_TMPFS=y
+CONFIG_TULIP=m
+CONFIG_UDF_FS=m
+CONFIG_UNIX=y
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_EHCI_HCD=m
+CONFIG_USB=m
+CONFIG_USB_MON=m
+CONFIG_USB_OHCI_HCD=m
+CONFIG_USB_STORAGE=m
+CONFIG_USB_UHCI_HCD=m
+CONFIG_VFAT_FS=y
+CONFIG_XFS_FS=y
diff --git a/arch/ia64/configs/sim_defconfig b/arch/ia64/configs/sim_defconfig
index 21a23cdfd41c..585222b368c3 100644
--- a/arch/ia64/configs/sim_defconfig
+++ b/arch/ia64/configs/sim_defconfig
@@ -1,723 +1,57 @@
-#
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.16-rc5
-# Mon Feb 27 16:13:41 2006
-#
-
-#
-# Code maturity level options
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_LOCK_KERNEL=y
-CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
-CONFIG_LOCALVERSION=""
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-# CONFIG_POSIX_MQUEUE is not set
-# CONFIG_BSD_PROCESS_ACCT is not set
-CONFIG_SYSCTL=y
-# CONFIG_AUDIT is not set
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-# CONFIG_CPUSETS is not set
-CONFIG_INITRAMFS_SOURCE=""
+CONFIG_BINFMT_MISC=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_SD=y
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-# CONFIG_EMBEDDED is not set
-CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_ALL is not set
-# CONFIG_KALLSYMS_EXTRA_PASS is not set
-CONFIG_HOTPLUG=y
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_EPOLL=y
-CONFIG_SHMEM=y
-CONFIG_CC_ALIGN_FUNCTIONS=0
-CONFIG_CC_ALIGN_LABELS=0
-CONFIG_CC_ALIGN_LOOPS=0
-CONFIG_CC_ALIGN_JUMPS=0
-CONFIG_SLUB=y
-# CONFIG_TINY_SHMEM is not set
-CONFIG_BASE_SMALL=0
-# CONFIG_SLOB is not set
-
-#
-# Loadable module support
-#
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_OBSOLETE_MODPARM=y
-CONFIG_MODVERSIONS=y
-# CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_KMOD=y
-CONFIG_STOP_MACHINE=y
-
-#
-# Block layer
-#
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-CONFIG_DEFAULT_AS=y
-# CONFIG_DEFAULT_DEADLINE is not set
-# CONFIG_DEFAULT_CFQ is not set
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="anticipatory"
-
-#
-# Processor type and features
-#
-CONFIG_IA64=y
-CONFIG_64BIT=y
-CONFIG_MMU=y
-CONFIG_SWIOTLB=y
-CONFIG_RWSEM_XCHGADD_ALGORITHM=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_GENERIC_TIME=y
-CONFIG_EFI=y
-CONFIG_GENERIC_IOMAP=y
-CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
-CONFIG_DMA_IS_DMA32=y
-# CONFIG_IA64_GENERIC is not set
-# CONFIG_IA64_DIG is not set
-# CONFIG_IA64_HP_ZX1 is not set
-# CONFIG_IA64_HP_ZX1_SWIOTLB is not set
-# CONFIG_IA64_SGI_SN2 is not set
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_MUTEXES=y
+CONFIG_EFI_PARTITION=y
+CONFIG_EFI_RTC=y
+CONFIG_EFI_VARS=y
+CONFIG_EXPERIMENTAL=y
+CONFIG_EXT2_FS=y
+# CONFIG_EXT3_FS_XATTR is not set
+CONFIG_EXT3_FS=y
+CONFIG_HP_SIMETH=y
+CONFIG_HP_SIMSCSI=y
+CONFIG_HP_SIMSERIAL_CONSOLE=y
+CONFIG_HP_SIMSERIAL=y
+CONFIG_HUGETLBFS=y
 CONFIG_IA64_HP_SIM=y
-# CONFIG_ITANIUM is not set
-CONFIG_MCKINLEY=y
-# CONFIG_IA64_PAGE_SIZE_4KB is not set
-# CONFIG_IA64_PAGE_SIZE_8KB is not set
-# CONFIG_IA64_PAGE_SIZE_16KB is not set
 CONFIG_IA64_PAGE_SIZE_64KB=y
-CONFIG_PGTABLE_3=y
-# CONFIG_PGTABLE_4 is not set
-# CONFIG_HZ_100 is not set
-CONFIG_HZ_250=y
-# CONFIG_HZ_1000 is not set
-CONFIG_HZ=250
-CONFIG_IA64_L1_CACHE_SHIFT=7
-# CONFIG_IA64_CYCLONE is not set
-CONFIG_FORCE_MAX_ZONEORDER=17
-CONFIG_SMP=y
-CONFIG_NR_CPUS=64
-# CONFIG_HOTPLUG_CPU is not set
-# CONFIG_SCHED_SMT is not set
-CONFIG_PREEMPT=y
-CONFIG_SELECT_MEMORY_MODEL=y
-CONFIG_FLATMEM_MANUAL=y
-# CONFIG_DISCONTIGMEM_MANUAL is not set
-# CONFIG_SPARSEMEM_MANUAL is not set
-CONFIG_FLATMEM=y
-CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
-CONFIG_SPLIT_PTLOCK_CPUS=4
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
-CONFIG_ARCH_FLATMEM_ENABLE=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-# CONFIG_VIRTUAL_MEM_MAP is not set
-# CONFIG_IA64_MCA_RECOVERY is not set
-# CONFIG_PERFMON is not set
 CONFIG_IA64_PALINFO=m
-
-#
-# Firmware Drivers
-#
-CONFIG_EFI_VARS=y
-CONFIG_BINFMT_ELF=y
-CONFIG_BINFMT_MISC=y
-
-#
-# Power management and ACPI
-#
-
-#
-# Networking
-#
-CONFIG_NET=y
-
-#
-# Networking options
-#
-# CONFIG_NETDEBUG is not set
-CONFIG_PACKET=y
-# CONFIG_PACKET_MMAP is not set
-# CONFIG_UNIX is not set
-# CONFIG_NET_KEY is not set
+CONFIG_IKCONFIG_PROC=y
+CONFIG_IKCONFIG=y
 CONFIG_INET=y
+CONFIG_INOTIFY=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
 CONFIG_IP_MULTICAST=y
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_FIB_HASH=y
-# CONFIG_IP_PNP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_IP_MROUTE is not set
-# CONFIG_ARPD is not set
-# CONFIG_SYN_COOKIES is not set
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_TUNNEL is not set
-CONFIG_INET_DIAG=y
-CONFIG_INET_TCP_DIAG=y
-# CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TCP_CONG_BIC=y
 # CONFIG_IPV6 is not set
-# CONFIG_NETFILTER is not set
-
-#
-# DCCP Configuration (EXPERIMENTAL)
-#
-# CONFIG_IP_DCCP is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
-# CONFIG_IP_SCTP is not set
-
-#
-# TIPC Configuration (EXPERIMENTAL)
-#
-# CONFIG_TIPC is not set
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_NET_DIVERT is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
-# CONFIG_NET_SCHED is not set
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_HAMRADIO is not set
-# CONFIG_IRDA is not set
-# CONFIG_BT is not set
-# CONFIG_IEEE80211 is not set
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-# CONFIG_STANDALONE is not set
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-# CONFIG_FW_LOADER is not set
-# CONFIG_DEBUG_DRIVER is not set
-
-#
-# Connector - unified userspace <-> kernelspace linker
-#
-# CONFIG_CONNECTOR is not set
-
-#
-# Memory Technology Devices (MTD)
-#
-# CONFIG_MTD is not set
-
-#
-# Parallel port support
-#
-# CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-
-#
-# Block devices
-#
-# CONFIG_BLK_DEV_COW_COMMON is not set
-CONFIG_BLK_DEV_LOOP=y
-# CONFIG_BLK_DEV_CRYPTOLOOP is not set
-# CONFIG_BLK_DEV_NBD is not set
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=4096
-# CONFIG_BLK_DEV_INITRD is not set
-# CONFIG_CDROM_PKTCDVD is not set
-# CONFIG_ATA_OVER_ETH is not set
-
-#
-# ATA/ATAPI/MFM/RLL support
-#
-# CONFIG_IDE is not set
-
-#
-# SCSI device support
-#
-# CONFIG_RAID_ATTRS is not set
-CONFIG_SCSI=y
-CONFIG_SCSI_PROC_FS=y
-
-#
-# SCSI support type (disk, tape, CD-ROM)
-#
-CONFIG_BLK_DEV_SD=y
-# CONFIG_CHR_DEV_ST is not set
-# CONFIG_CHR_DEV_OSST is not set
-# CONFIG_BLK_DEV_SR is not set
-# CONFIG_CHR_DEV_SG is not set
-# CONFIG_CHR_DEV_SCH is not set
-
-#
-# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
-#
-CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_LOG_BUF_SHIFT=16
+CONFIG_MCKINLEY=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_NET=y
+CONFIG_NFSD_V3=y
+CONFIG_NFSD=y
+CONFIG_NFS_FS=y
+CONFIG_NR_CPUS=64
+CONFIG_PACKET=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_PREEMPT=y
+CONFIG_PROC_KCORE=y
 CONFIG_SCSI_CONSTANTS=y
 CONFIG_SCSI_LOGGING=y
-
-#
-# SCSI Transport Attributes
-#
+CONFIG_SCSI_MULTI_LUN=y
 CONFIG_SCSI_SPI_ATTRS=y
-# CONFIG_SCSI_FC_ATTRS is not set
-# CONFIG_SCSI_ISCSI_ATTRS is not set
-# CONFIG_SCSI_SAS_ATTRS is not set
-
-#
-# SCSI low-level drivers
-#
-# CONFIG_ISCSI_TCP is not set
-# CONFIG_SCSI_SATA is not set
-# CONFIG_SCSI_DEBUG is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
-# CONFIG_MD is not set
-
-#
-# Fusion MPT device support
-#
-# CONFIG_FUSION is not set
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# I2O device support
-#
-
-#
-# Network device support
-#
-# CONFIG_NETDEVICES is not set
-# CONFIG_DUMMY is not set
-# CONFIG_BONDING is not set
-# CONFIG_EQUALIZER is not set
-# CONFIG_TUN is not set
-
-#
-# PHY device support
-#
-
-#
-# Ethernet (10 or 100Mbit)
-#
-# CONFIG_NET_ETHERNET is not set
-
-#
-# Ethernet (1000 Mbit)
-#
-
-#
-# Ethernet (10000 Mbit)
-#
-# CONFIG_PPP is not set
-# CONFIG_SLIP is not set
-# CONFIG_SHAPER is not set
-# CONFIG_NETCONSOLE is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
-
-#
-# ISDN subsystem
-#
-# CONFIG_ISDN is not set
-
-#
-# Telephony Support
-#
-# CONFIG_PHONE is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-
-#
-# Userland interfaces
-#
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-# CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
-# CONFIG_INPUT_EVDEV is not set
-# CONFIG_INPUT_EVBUG is not set
-
-#
-# Input Device Drivers
-#
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TOUCHSCREEN is not set
-# CONFIG_INPUT_MISC is not set
-
-#
-# Hardware I/O ports
-#
-CONFIG_SERIO=y
+CONFIG_SCSI=y
 # CONFIG_SERIO_I8042 is not set
-CONFIG_SERIO_SERPORT=y
-# CONFIG_SERIO_RAW is not set
-# CONFIG_GAMEPORT is not set
-
-#
-# Character devices
-#
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-# CONFIG_SERIAL_NONSTANDARD is not set
-
-#
-# Serial drivers
-#
-# CONFIG_SERIAL_8250 is not set
-
-#
-# Non-8250 serial port support
-#
-CONFIG_UNIX98_PTYS=y
-# CONFIG_LEGACY_PTYS is not set
-
-#
-# IPMI
-#
-# CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-# CONFIG_WATCHDOG is not set
-CONFIG_EFI_RTC=y
-# CONFIG_DTLK is not set
-# CONFIG_R3964 is not set
-
-#
-# Ftape, the floppy tape device driver
-#
-# CONFIG_AGP is not set
-# CONFIG_RAW_DRIVER is not set
-# CONFIG_HANGCHECK_TIMER is not set
-
-#
-# TPM devices
-#
-# CONFIG_TCG_TPM is not set
-# CONFIG_TELCLOCK is not set
-
-#
-# I2C support
-#
-# CONFIG_I2C is not set
-
-#
-# SPI support
-#
-# CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
-
-#
-# Dallas's 1-wire bus
-#
-# CONFIG_W1 is not set
-
-#
-# Hardware Monitoring support
-#
-CONFIG_HWMON=y
-# CONFIG_HWMON_VID is not set
-# CONFIG_SENSORS_F71805F is not set
-# CONFIG_HWMON_DEBUG_CHIP is not set
-
-#
-# Misc devices
-#
-
-#
-# Multimedia Capabilities Port drivers
-#
-
-#
-# Multimedia devices
-#
-# CONFIG_VIDEO_DEV is not set
-
-#
-# Digital Video Broadcasting Devices
-#
-# CONFIG_DVB is not set
-
-#
-# Graphics support
-#
-# CONFIG_FB is not set
-
-#
-# Console display driver support
-#
+CONFIG_SMP=y
+# CONFIG_STANDALONE is not set
+CONFIG_SYSVIPC=y
 # CONFIG_VGA_CONSOLE is not set
-CONFIG_DUMMY_CONSOLE=y
-
-#
-# Sound
-#
-# CONFIG_SOUND is not set
-
-#
-# USB support
-#
-# CONFIG_USB_ARCH_HAS_HCD is not set
-# CONFIG_USB_ARCH_HAS_OHCI is not set
-
-#
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
-#
-
-#
-# USB Gadget Support
-#
-# CONFIG_USB_GADGET is not set
-
-#
-# MMC/SD Card support
-#
-# CONFIG_MMC is not set
-
-#
-# InfiniBand support
-#
-
-#
-# EDAC - error detection and reporting (RAS)
-#
-
-#
-# File systems
-#
-CONFIG_EXT2_FS=y
-# CONFIG_EXT2_FS_XATTR is not set
-# CONFIG_EXT2_FS_XIP is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_JBD=y
-# CONFIG_JBD_DEBUG is not set
-# CONFIG_REISERFS_FS is not set
-# CONFIG_JFS_FS is not set
-# CONFIG_FS_POSIX_ACL is not set
-# CONFIG_XFS_FS is not set
-# CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
-CONFIG_INOTIFY=y
-# CONFIG_QUOTA is not set
-CONFIG_DNOTIFY=y
-# CONFIG_AUTOFS_FS is not set
-# CONFIG_AUTOFS4_FS is not set
-# CONFIG_FUSE_FS is not set
-
-#
-# CD-ROM/DVD Filesystems
-#
-# CONFIG_ISO9660_FS is not set
-# CONFIG_UDF_FS is not set
-
-#
-# DOS/FAT/NT Filesystems
-#
-# CONFIG_MSDOS_FS is not set
-# CONFIG_VFAT_FS is not set
-# CONFIG_NTFS_FS is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_KCORE=y
-CONFIG_SYSFS=y
-# CONFIG_TMPFS is not set
-CONFIG_HUGETLBFS=y
-CONFIG_HUGETLB_PAGE=y
-CONFIG_RAMFS=y
-# CONFIG_RELAYFS_FS is not set
-# CONFIG_CONFIGFS_FS is not set
-
-#
-# Miscellaneous filesystems
-#
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-# CONFIG_CRAMFS is not set
-# CONFIG_VXFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
-CONFIG_NFS_FS=y
-# CONFIG_NFS_V3 is not set
-# CONFIG_NFS_V4 is not set
-CONFIG_NFS_DIRECTIO=y
-CONFIG_NFSD=y
-CONFIG_NFSD_V3=y
-# CONFIG_NFSD_V3_ACL is not set
-# CONFIG_NFSD_V4 is not set
-# CONFIG_NFSD_TCP is not set
-CONFIG_LOCKD=y
-CONFIG_LOCKD_V4=y
-CONFIG_EXPORTFS=y
-CONFIG_NFS_COMMON=y
-CONFIG_SUNRPC=y
-# CONFIG_RPCSEC_GSS_KRB5 is not set
-# CONFIG_RPCSEC_GSS_SPKM3 is not set
-# CONFIG_SMB_FS is not set
-# CONFIG_CIFS is not set
-# CONFIG_NCP_FS is not set
-# CONFIG_CODA_FS is not set
-# CONFIG_AFS_FS is not set
-# CONFIG_9P_FS is not set
-
-#
-# Partition Types
-#
-CONFIG_PARTITION_ADVANCED=y
-# CONFIG_ACORN_PARTITION is not set
-# CONFIG_OSF_PARTITION is not set
-# CONFIG_AMIGA_PARTITION is not set
-# CONFIG_ATARI_PARTITION is not set
-# CONFIG_MAC_PARTITION is not set
-CONFIG_MSDOS_PARTITION=y
-# CONFIG_BSD_DISKLABEL is not set
-# CONFIG_MINIX_SUBPARTITION is not set
-# CONFIG_SOLARIS_X86_PARTITION is not set
-# CONFIG_UNIXWARE_DISKLABEL is not set
-# CONFIG_LDM_PARTITION is not set
-# CONFIG_SGI_PARTITION is not set
-# CONFIG_ULTRIX_PARTITION is not set
-# CONFIG_SUN_PARTITION is not set
-# CONFIG_KARMA_PARTITION is not set
-CONFIG_EFI_PARTITION=y
-
-#
-# Native Language Support
-#
-# CONFIG_NLS is not set
-
-#
-# Library routines
-#
-# CONFIG_CRC_CCITT is not set
-# CONFIG_CRC16 is not set
-CONFIG_CRC32=y
-# CONFIG_LIBCRC32C is not set
-CONFIG_GENERIC_HARDIRQS=y
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_GENERIC_PENDING_IRQ=y
-
-#
-# HP Simulator drivers
-#
-CONFIG_HP_SIMETH=y
-CONFIG_HP_SIMSERIAL=y
-CONFIG_HP_SIMSERIAL_CONSOLE=y
-CONFIG_HP_SIMSCSI=y
-
-#
-# Instrumentation Support
-#
-# CONFIG_PROFILING is not set
-# CONFIG_KPROBES is not set
-
-#
-# Kernel hacking
-#
-# CONFIG_PRINTK_TIME is not set
-# CONFIG_MAGIC_SYSRQ is not set
-CONFIG_DEBUG_KERNEL=y
-CONFIG_LOG_BUF_SHIFT=16
-CONFIG_DETECT_SOFTLOCKUP=y
-# CONFIG_SCHEDSTATS is not set
-# CONFIG_DEBUG_SLAB is not set
-CONFIG_DEBUG_PREEMPT=y
-CONFIG_DEBUG_MUTEXES=y
-# CONFIG_DEBUG_SPINLOCK is not set
-# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-# CONFIG_DEBUG_KOBJECT is not set
-CONFIG_DEBUG_INFO=y
-# CONFIG_DEBUG_FS is not set
-# CONFIG_DEBUG_VM is not set
-CONFIG_FORCED_INLINING=y
-# CONFIG_RCU_TORTURE_TEST is not set
-# CONFIG_IA64_GRANULE_16MB is not set
-CONFIG_IA64_GRANULE_64MB=y
-# CONFIG_IA64_PRINT_HAZARDS is not set
-# CONFIG_DISABLE_VHPT is not set
-# CONFIG_IA64_DEBUG_CMPXCHG is not set
-# CONFIG_IA64_DEBUG_IRQ is not set
-CONFIG_SYSVIPC_COMPAT=y
-
-#
-# Security options
-#
-# CONFIG_KEYS is not set
-# CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
-# CONFIG_CRYPTO is not set
-
-#
-# Hardware crypto devices
-#
diff --git a/arch/ia64/configs/tiger_defconfig b/arch/ia64/configs/tiger_defconfig
index c5a5ea9d54ae..498618ea00ea 100644
--- a/arch/ia64/configs/tiger_defconfig
+++ b/arch/ia64/configs/tiger_defconfig
@@ -1,1134 +1,113 @@
-#
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.22
-# Thu Jul 19 13:54:47 2007
-#
-CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-
-#
-# Code maturity level options
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_LOCK_KERNEL=y
-CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
-CONFIG_LOCALVERSION=""
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-CONFIG_SYSVIPC_SYSCTL=y
-CONFIG_POSIX_MQUEUE=y
-# CONFIG_BSD_PROCESS_ACCT is not set
-# CONFIG_TASKSTATS is not set
-# CONFIG_USER_NS is not set
-# CONFIG_AUDIT is not set
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=20
-# CONFIG_CPUSETS is not set
-CONFIG_SYSFS_DEPRECATED=y
-# CONFIG_RELAY is not set
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_SYSCTL=y
-# CONFIG_EMBEDDED is not set
-CONFIG_SYSCTL_SYSCALL=y
-CONFIG_KALLSYMS=y
-CONFIG_KALLSYMS_ALL=y
-# CONFIG_KALLSYMS_EXTRA_PASS is not set
-CONFIG_HOTPLUG=y
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_ANON_INODES=y
-CONFIG_EPOLL=y
-CONFIG_SIGNALFD=y
-CONFIG_TIMERFD=y
-CONFIG_EVENTFD=y
-CONFIG_SHMEM=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_SLUB=y
-# CONFIG_SLUB is not set
-# CONFIG_SLOB is not set
-CONFIG_RT_MUTEXES=y
-# CONFIG_TINY_SHMEM is not set
-CONFIG_BASE_SMALL=0
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_MODULE_FORCE_UNLOAD is not set
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-CONFIG_KMOD=y
-CONFIG_STOP_MACHINE=y
-CONFIG_BLOCK=y
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_BLK_DEV_BSG is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-CONFIG_DEFAULT_AS=y
-# CONFIG_DEFAULT_DEADLINE is not set
-# CONFIG_DEFAULT_CFQ is not set
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="anticipatory"
-
-#
-# Processor type and features
-#
-CONFIG_IA64=y
-CONFIG_64BIT=y
-CONFIG_ZONE_DMA=y
-CONFIG_QUICKLIST=y
-CONFIG_MMU=y
-CONFIG_SWIOTLB=y
-CONFIG_RWSEM_XCHGADD_ALGORITHM=y
-# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-CONFIG_GENERIC_FIND_NEXT_BIT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_GENERIC_TIME=y
-CONFIG_DMI=y
-CONFIG_EFI=y
-CONFIG_GENERIC_IOMAP=y
-CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
-CONFIG_AUDIT_ARCH=y
-# CONFIG_IA64_GENERIC is not set
-CONFIG_IA64_DIG=y
-# CONFIG_IA64_HP_ZX1 is not set
-# CONFIG_IA64_HP_ZX1_SWIOTLB is not set
-# CONFIG_IA64_SGI_SN2 is not set
-# CONFIG_IA64_HP_SIM is not set
-# CONFIG_ITANIUM is not set
-CONFIG_MCKINLEY=y
-# CONFIG_IA64_PAGE_SIZE_4KB is not set
-# CONFIG_IA64_PAGE_SIZE_8KB is not set
-# CONFIG_IA64_PAGE_SIZE_16KB is not set
-CONFIG_IA64_PAGE_SIZE_64KB=y
-CONFIG_PGTABLE_3=y
-# CONFIG_PGTABLE_4 is not set
-# CONFIG_HZ_100 is not set
-CONFIG_HZ_250=y
-# CONFIG_HZ_300 is not set
-# CONFIG_HZ_1000 is not set
-CONFIG_HZ=250
-CONFIG_IA64_L1_CACHE_SHIFT=7
-CONFIG_IA64_CYCLONE=y
-CONFIG_IOSAPIC=y
-CONFIG_FORCE_MAX_ZONEORDER=17
-CONFIG_SMP=y
-CONFIG_NR_CPUS=16
-CONFIG_HOTPLUG_CPU=y
-CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
-# CONFIG_SCHED_SMT is not set
-CONFIG_PERMIT_BSP_REMOVE=y
-CONFIG_FORCE_CPEI_RETARGET=y
-# CONFIG_PREEMPT is not set
-CONFIG_SELECT_MEMORY_MODEL=y
-CONFIG_FLATMEM_MANUAL=y
-# CONFIG_DISCONTIGMEM_MANUAL is not set
-# CONFIG_SPARSEMEM_MANUAL is not set
-CONFIG_FLATMEM=y
-CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
-CONFIG_SPLIT_PTLOCK_CPUS=4
-CONFIG_RESOURCES_64BIT=y
-CONFIG_ZONE_DMA_FLAG=1
-CONFIG_BOUNCE=y
-CONFIG_NR_QUICK=1
-CONFIG_VIRT_TO_BUS=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
-CONFIG_ARCH_FLATMEM_ENABLE=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_POPULATES_NODE_MAP=y
-CONFIG_VIRTUAL_MEM_MAP=y
-CONFIG_HOLES_IN_ZONE=y
-CONFIG_IA64_MCA_RECOVERY=y
-CONFIG_PERFMON=y
-CONFIG_IA64_PALINFO=y
-# CONFIG_IA64_MC_ERR_INJECT is not set
-# CONFIG_IA64_ESI is not set
-CONFIG_KEXEC=y
-# CONFIG_CRASH_DUMP is not set
-
-#
-# Firmware Drivers
-#
-CONFIG_EFI_VARS=y
-CONFIG_EFI_PCDP=y
-CONFIG_DMIID=y
-CONFIG_BINFMT_ELF=y
-CONFIG_BINFMT_MISC=m
-
-# CONFIG_DMAR is not set
-
-#
-# Power management and ACPI
-#
-CONFIG_PM=y
-CONFIG_PM_LEGACY=y
-# CONFIG_PM_DEBUG is not set
-
-#
-# ACPI (Advanced Configuration and Power Interface) Support
-#
-CONFIG_ACPI=y
-CONFIG_ACPI_PROCFS=y
 CONFIG_ACPI_BUTTON=m
+CONFIG_ACPI_CONTAINER=m
 CONFIG_ACPI_FAN=m
-# CONFIG_ACPI_DOCK is not set
 CONFIG_ACPI_PROCESSOR=m
-CONFIG_ACPI_HOTPLUG_CPU=y
-CONFIG_ACPI_THERMAL=m
-CONFIG_ACPI_BLACKLIST_YEAR=0
-# CONFIG_ACPI_DEBUG is not set
-CONFIG_ACPI_EC=y
-CONFIG_ACPI_POWER=y
-CONFIG_ACPI_SYSTEM=y
-CONFIG_ACPI_CONTAINER=m
-
-#
-# CPU Frequency scaling
-#
-# CONFIG_CPU_FREQ is not set
-
-#
-# Bus options (PCI, PCMCIA)
-#
-CONFIG_PCI=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_SYSCALL=y
-# CONFIG_PCIEPORTBUS is not set
-CONFIG_ARCH_SUPPORTS_MSI=y
-# CONFIG_PCI_MSI is not set
-# CONFIG_PCI_DEBUG is not set
-CONFIG_HOTPLUG_PCI=m
-# CONFIG_HOTPLUG_PCI_FAKE is not set
-CONFIG_HOTPLUG_PCI_ACPI=m
-# CONFIG_HOTPLUG_PCI_ACPI_IBM is not set
-# CONFIG_HOTPLUG_PCI_CPCI is not set
-# CONFIG_HOTPLUG_PCI_SHPC is not set
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
-# CONFIG_PCCARD is not set
-
-#
-# Networking
-#
-CONFIG_NET=y
-
-#
-# Networking options
-#
-CONFIG_PACKET=y
-# CONFIG_PACKET_MMAP is not set
-CONFIG_UNIX=y
-CONFIG_XFRM=y
-# CONFIG_XFRM_USER is not set
-# CONFIG_XFRM_SUB_POLICY is not set
-# CONFIG_XFRM_MIGRATE is not set
-# CONFIG_NET_KEY is not set
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_FIB_HASH=y
-# CONFIG_IP_PNP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_IP_MROUTE is not set
+CONFIG_ACPI_PROCFS=y
+CONFIG_AGP_I460=m
+CONFIG_AGP=m
 CONFIG_ARPD=y
-CONFIG_SYN_COOKIES=y
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_XFRM_TUNNEL is not set
-# CONFIG_INET_TUNNEL is not set
-CONFIG_INET_XFRM_MODE_TRANSPORT=y
-CONFIG_INET_XFRM_MODE_TUNNEL=y
-CONFIG_INET_XFRM_MODE_BEET=y
-CONFIG_INET_DIAG=y
-CONFIG_INET_TCP_DIAG=y
-# CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TCP_CONG_CUBIC=y
-CONFIG_DEFAULT_TCP_CONG="cubic"
-# CONFIG_TCP_MD5SIG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_INET6_XFRM_TUNNEL is not set
-# CONFIG_INET6_TUNNEL is not set
-# CONFIG_NETWORK_SECMARK is not set
-# CONFIG_NETFILTER is not set
-# CONFIG_IP_DCCP is not set
-# CONFIG_IP_SCTP is not set
-# CONFIG_TIPC is not set
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
-# CONFIG_NET_SCHED is not set
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_HAMRADIO is not set
-# CONFIG_IRDA is not set
-# CONFIG_BT is not set
-# CONFIG_AF_RXRPC is not set
-
-#
-# Wireless
-#
-# CONFIG_CFG80211 is not set
-# CONFIG_WIRELESS_EXT is not set
-# CONFIG_MAC80211 is not set
-# CONFIG_IEEE80211 is not set
-# CONFIG_RFKILL is not set
-# CONFIG_NET_9P is not set
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=m
-# CONFIG_DEBUG_DRIVER is not set
-# CONFIG_DEBUG_DEVRES is not set
-# CONFIG_SYS_HYPERVISOR is not set
-# CONFIG_CONNECTOR is not set
-# CONFIG_MTD is not set
-# CONFIG_PARPORT is not set
-CONFIG_PNP=y
-# CONFIG_PNP_DEBUG is not set
-
-#
-# Protocols
-#
-CONFIG_PNPACPI=y
-CONFIG_BLK_DEV=y
-# CONFIG_BLK_CPQ_DA is not set
-# CONFIG_BLK_CPQ_CISS_DA is not set
-# CONFIG_BLK_DEV_DAC960 is not set
-# CONFIG_BLK_DEV_UMEM is not set
-# CONFIG_BLK_DEV_COW_COMMON is not set
-CONFIG_BLK_DEV_LOOP=m
+CONFIG_AUTOFS4_FS=y
+CONFIG_AUTOFS_FS=y
+CONFIG_BINFMT_MISC=m
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_BLK_DEV_CMD64X=y
 CONFIG_BLK_DEV_CRYPTOLOOP=m
-CONFIG_BLK_DEV_NBD=m
-# CONFIG_BLK_DEV_SX8 is not set
-# CONFIG_BLK_DEV_UB is not set
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=4096
-CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
-# CONFIG_CDROM_PKTCDVD is not set
-# CONFIG_ATA_OVER_ETH is not set
-CONFIG_MISC_DEVICES=y
-# CONFIG_PHANTOM is not set
-# CONFIG_EEPROM_93CX6 is not set
-# CONFIG_SGI_IOC4 is not set
-# CONFIG_TIFM_CORE is not set
-CONFIG_IDE=y
-CONFIG_IDE_MAX_HWIFS=4
-CONFIG_BLK_DEV_IDE=y
-
-#
-# Please see Documentation/ide.txt for help/info on IDE drives
-#
-# CONFIG_BLK_DEV_IDE_SATA is not set
-CONFIG_BLK_DEV_IDEDISK=y
-# CONFIG_IDEDISK_MULTI_MODE is not set
-CONFIG_BLK_DEV_IDECD=y
-# CONFIG_BLK_DEV_IDETAPE is not set
-CONFIG_BLK_DEV_IDEFLOPPY=y
-CONFIG_BLK_DEV_IDESCSI=m
-# CONFIG_BLK_DEV_IDEACPI is not set
-# CONFIG_IDE_TASK_IOCTL is not set
-CONFIG_IDE_PROC_FS=y
-
-#
-# IDE chipset support/bugfixes
-#
-# CONFIG_IDE_GENERIC is not set
-# CONFIG_BLK_DEV_IDEPNP is not set
-CONFIG_BLK_DEV_IDEPCI=y
-# CONFIG_IDEPCI_SHARE_IRQ is not set
-CONFIG_IDEPCI_PCIBUS_ORDER=y
-# CONFIG_BLK_DEV_OFFBOARD is not set
+CONFIG_BLK_DEV_DM=m
 CONFIG_BLK_DEV_GENERIC=y
-# CONFIG_BLK_DEV_OPTI621 is not set
-CONFIG_BLK_DEV_IDEDMA_PCI=y
-# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
-# CONFIG_IDEDMA_ONLYDISK is not set
-# CONFIG_BLK_DEV_AEC62XX is not set
-# CONFIG_BLK_DEV_ALI15X3 is not set
-# CONFIG_BLK_DEV_AMD74XX is not set
-CONFIG_BLK_DEV_CMD64X=y
-# CONFIG_BLK_DEV_TRIFLEX is not set
-# CONFIG_BLK_DEV_CY82C693 is not set
-# CONFIG_BLK_DEV_CS5520 is not set
-# CONFIG_BLK_DEV_CS5530 is not set
-# CONFIG_BLK_DEV_HPT34X is not set
-# CONFIG_BLK_DEV_HPT366 is not set
-# CONFIG_BLK_DEV_JMICRON is not set
-# CONFIG_BLK_DEV_SC1200 is not set
+CONFIG_BLK_DEV_IDECD=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_BLK_DEV_LOOP=m
+CONFIG_BLK_DEV_MD=m
+CONFIG_BLK_DEV_NBD=m
 CONFIG_BLK_DEV_PIIX=y
-# CONFIG_BLK_DEV_IT8213 is not set
-# CONFIG_BLK_DEV_IT821X is not set
-# CONFIG_BLK_DEV_NS87415 is not set
-# CONFIG_BLK_DEV_PDC202XX_OLD is not set
-# CONFIG_BLK_DEV_PDC202XX_NEW is not set
-# CONFIG_BLK_DEV_SVWKS is not set
-# CONFIG_BLK_DEV_SIIMAGE is not set
-# CONFIG_BLK_DEV_SLC90E66 is not set
-# CONFIG_BLK_DEV_TRM290 is not set
-# CONFIG_BLK_DEV_VIA82CXXX is not set
-# CONFIG_BLK_DEV_TC86C001 is not set
-# CONFIG_IDE_ARM is not set
-CONFIG_BLK_DEV_IDEDMA=y
-# CONFIG_IDEDMA_IVB is not set
-# CONFIG_BLK_DEV_HD is not set
-
-#
-# SCSI device support
-#
-# CONFIG_RAID_ATTRS is not set
-CONFIG_SCSI=y
-CONFIG_SCSI_DMA=y
-# CONFIG_SCSI_TGT is not set
-CONFIG_SCSI_NETLINK=y
-CONFIG_SCSI_PROC_FS=y
-
-#
-# SCSI support type (disk, tape, CD-ROM)
-#
+CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_SD=y
-CONFIG_CHR_DEV_ST=m
-# CONFIG_CHR_DEV_OSST is not set
 CONFIG_BLK_DEV_SR=m
-# CONFIG_BLK_DEV_SR_VENDOR is not set
 CONFIG_CHR_DEV_SG=m
-# CONFIG_CHR_DEV_SCH is not set
-
-#
-# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
-#
-# CONFIG_SCSI_MULTI_LUN is not set
-# CONFIG_SCSI_CONSTANTS is not set
-# CONFIG_SCSI_LOGGING is not set
-# CONFIG_SCSI_SCAN_ASYNC is not set
-CONFIG_SCSI_WAIT_SCAN=m
-
-#
-# SCSI Transports
-#
-CONFIG_SCSI_SPI_ATTRS=y
-CONFIG_SCSI_FC_ATTRS=y
-# CONFIG_SCSI_ISCSI_ATTRS is not set
-# CONFIG_SCSI_SAS_ATTRS is not set
-# CONFIG_SCSI_SAS_LIBSAS is not set
-
-#
-# SCSI low-level drivers
-#
-# CONFIG_ISCSI_TCP is not set
-# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
-# CONFIG_SCSI_3W_9XXX is not set
-# CONFIG_SCSI_ACARD is not set
-# CONFIG_SCSI_AACRAID is not set
-# CONFIG_SCSI_AIC7XXX is not set
-# CONFIG_SCSI_AIC7XXX_OLD is not set
-# CONFIG_SCSI_AIC79XX is not set
-# CONFIG_SCSI_AIC94XX is not set
-# CONFIG_SCSI_ARCMSR is not set
-# CONFIG_MEGARAID_NEWGEN is not set
-# CONFIG_MEGARAID_LEGACY is not set
-# CONFIG_MEGARAID_SAS is not set
-# CONFIG_SCSI_HPTIOP is not set
-# CONFIG_SCSI_DMX3191D is not set
-# CONFIG_SCSI_FUTURE_DOMAIN is not set
-# CONFIG_SCSI_IPS is not set
-# CONFIG_SCSI_INITIO is not set
-# CONFIG_SCSI_INIA100 is not set
-# CONFIG_SCSI_STEX is not set
-CONFIG_SCSI_SYM53C8XX_2=y
-CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1
-CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16
-CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64
-CONFIG_SCSI_SYM53C8XX_MMIO=y
-CONFIG_SCSI_QLOGIC_1280=y
-# CONFIG_SCSI_QLA_FC is not set
-# CONFIG_SCSI_QLA_ISCSI is not set
-# CONFIG_SCSI_LPFC is not set
-# CONFIG_SCSI_DC395x is not set
-# CONFIG_SCSI_DC390T is not set
-# CONFIG_SCSI_DEBUG is not set
-# CONFIG_SCSI_SRP is not set
-# CONFIG_ATA is not set
-CONFIG_MD=y
-CONFIG_BLK_DEV_MD=m
-CONFIG_MD_LINEAR=m
-CONFIG_MD_RAID0=m
-CONFIG_MD_RAID1=m
-# CONFIG_MD_RAID10 is not set
-# CONFIG_MD_RAID456 is not set
-CONFIG_MD_MULTIPATH=m
-# CONFIG_MD_FAULTY is not set
-CONFIG_BLK_DEV_DM=m
-# CONFIG_DM_DEBUG is not set
+CONFIG_CHR_DEV_ST=m
+CONFIG_CIFS=m
+CONFIG_CRYPTO_ECB=m
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_PCBC=m
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_MUTEXES=y
 CONFIG_DM_CRYPT=m
-CONFIG_DM_SNAPSHOT=m
 CONFIG_DM_MIRROR=m
+CONFIG_DM_SNAPSHOT=m
 CONFIG_DM_ZERO=m
-# CONFIG_DM_MULTIPATH is not set
-# CONFIG_DM_DELAY is not set
-
-#
-# Fusion MPT device support
-#
-CONFIG_FUSION=y
-CONFIG_FUSION_SPI=y
-CONFIG_FUSION_FC=y
-# CONFIG_FUSION_SAS is not set
-CONFIG_FUSION_MAX_SGE=128
-CONFIG_FUSION_CTL=y
-
-#
-# IEEE 1394 (FireWire) support
-#
-# CONFIG_FIREWIRE is not set
-# CONFIG_IEEE1394 is not set
-# CONFIG_I2O is not set
-CONFIG_NETDEVICES=y
-# CONFIG_NETDEVICES_MULTIQUEUE is not set
-CONFIG_DUMMY=m
-# CONFIG_BONDING is not set
-# CONFIG_MACVLAN is not set
-# CONFIG_EQUALIZER is not set
-# CONFIG_TUN is not set
-# CONFIG_NET_SB1000 is not set
-# CONFIG_ARCNET is not set
-# CONFIG_PHYLIB is not set
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=m
-# CONFIG_HAPPYMEAL is not set
-# CONFIG_SUNGEM is not set
-# CONFIG_CASSINI is not set
-# CONFIG_NET_VENDOR_3COM is not set
-CONFIG_NET_TULIP=y
-# CONFIG_DE2104X is not set
-CONFIG_TULIP=m
-# CONFIG_TULIP_MWI is not set
-# CONFIG_TULIP_MMIO is not set
-# CONFIG_TULIP_NAPI is not set
-# CONFIG_DE4X5 is not set
-# CONFIG_WINBOND_840 is not set
-# CONFIG_DM9102 is not set
-# CONFIG_ULI526X is not set
-# CONFIG_HP100 is not set
-CONFIG_NET_PCI=y
-# CONFIG_PCNET32 is not set
-# CONFIG_AMD8111_ETH is not set
-# CONFIG_ADAPTEC_STARFIRE is not set
-# CONFIG_B44 is not set
-# CONFIG_FORCEDETH is not set
-# CONFIG_DGRS is not set
-CONFIG_EEPRO100=m
-CONFIG_E100=m
-# CONFIG_FEALNX is not set
-# CONFIG_NATSEMI is not set
-# CONFIG_NE2K_PCI is not set
-# CONFIG_8139CP is not set
-# CONFIG_8139TOO is not set
-# CONFIG_SIS900 is not set
-# CONFIG_EPIC100 is not set
-# CONFIG_SUNDANCE is not set
-# CONFIG_VIA_RHINE is not set
-# CONFIG_SC92031 is not set
-CONFIG_NETDEV_1000=y
-# CONFIG_ACENIC is not set
-# CONFIG_DL2K is not set
-CONFIG_E1000=y
-# CONFIG_E1000_NAPI is not set
-# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set
-# CONFIG_NS83820 is not set
-# CONFIG_HAMACHI is not set
-# CONFIG_YELLOWFIN is not set
-# CONFIG_R8169 is not set
-# CONFIG_SIS190 is not set
-# CONFIG_SKGE is not set
-# CONFIG_SKY2 is not set
-# CONFIG_VIA_VELOCITY is not set
-CONFIG_TIGON3=y
-# CONFIG_BNX2 is not set
-# CONFIG_QLA3XXX is not set
-# CONFIG_ATL1 is not set
-CONFIG_NETDEV_10000=y
-# CONFIG_CHELSIO_T1 is not set
-# CONFIG_CHELSIO_T3 is not set
-# CONFIG_IXGB is not set
-# CONFIG_S2IO is not set
-# CONFIG_MYRI10GE is not set
-# CONFIG_NETXEN_NIC is not set
-# CONFIG_MLX4_CORE is not set
-# CONFIG_TR is not set
-
-#
-# Wireless LAN
-#
-# CONFIG_WLAN_PRE80211 is not set
-# CONFIG_WLAN_80211 is not set
-
-#
-# USB Network Adapters
-#
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_RTL8150 is not set
-# CONFIG_USB_USBNET_MII is not set
-# CONFIG_USB_USBNET is not set
-# CONFIG_WAN is not set
-# CONFIG_FDDI is not set
-# CONFIG_HIPPI is not set
-# CONFIG_PPP is not set
-# CONFIG_SLIP is not set
-# CONFIG_NET_FC is not set
-# CONFIG_SHAPER is not set
-CONFIG_NETCONSOLE=y
-CONFIG_NETPOLL=y
-# CONFIG_NETPOLL_TRAP is not set
-CONFIG_NET_POLL_CONTROLLER=y
-# CONFIG_ISDN is not set
-# CONFIG_PHONE is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-# CONFIG_INPUT_FF_MEMLESS is not set
-# CONFIG_INPUT_POLLDEV is not set
-
-#
-# Userland interfaces
-#
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-# CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
-# CONFIG_INPUT_EVDEV is not set
-# CONFIG_INPUT_EVBUG is not set
-
-#
-# Input Device Drivers
-#
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_KEYBOARD_ATKBD=y
-# CONFIG_KEYBOARD_SUNKBD is not set
-# CONFIG_KEYBOARD_LKKBD is not set
-# CONFIG_KEYBOARD_XTKBD is not set
-# CONFIG_KEYBOARD_NEWTON is not set
-# CONFIG_KEYBOARD_STOWAWAY is not set
-CONFIG_INPUT_MOUSE=y
-CONFIG_MOUSE_PS2=y
-CONFIG_MOUSE_PS2_ALPS=y
-CONFIG_MOUSE_PS2_LOGIPS2PP=y
-CONFIG_MOUSE_PS2_SYNAPTICS=y
-CONFIG_MOUSE_PS2_LIFEBOOK=y
-CONFIG_MOUSE_PS2_TRACKPOINT=y
-# CONFIG_MOUSE_PS2_TOUCHKIT is not set
-# CONFIG_MOUSE_SERIAL is not set
-# CONFIG_MOUSE_APPLETOUCH is not set
-# CONFIG_MOUSE_VSXXXAA is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TABLET is not set
-# CONFIG_INPUT_TOUCHSCREEN is not set
-# CONFIG_INPUT_MISC is not set
-
-#
-# Hardware I/O ports
-#
-CONFIG_SERIO=y
-CONFIG_SERIO_I8042=y
-# CONFIG_SERIO_SERPORT is not set
-# CONFIG_SERIO_PCIPS2 is not set
-CONFIG_SERIO_LIBPS2=y
-# CONFIG_SERIO_RAW is not set
-CONFIG_GAMEPORT=m
-# CONFIG_GAMEPORT_NS558 is not set
-# CONFIG_GAMEPORT_L4 is not set
-# CONFIG_GAMEPORT_EMU10K1 is not set
-# CONFIG_GAMEPORT_FM801 is not set
-
-#
-# Character devices
-#
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
-CONFIG_SERIAL_NONSTANDARD=y
-# CONFIG_COMPUTONE is not set
-# CONFIG_ROCKETPORT is not set
-# CONFIG_CYCLADES is not set
-# CONFIG_DIGIEPCA is not set
-# CONFIG_MOXA_INTELLIO is not set
-# CONFIG_MOXA_SMARTIO is not set
-# CONFIG_MOXA_SMARTIO_NEW is not set
-# CONFIG_ISI is not set
-# CONFIG_SYNCLINKMP is not set
-# CONFIG_SYNCLINK_GT is not set
-# CONFIG_N_HDLC is not set
-# CONFIG_SPECIALIX is not set
-# CONFIG_SX is not set
-# CONFIG_RIO is not set
-# CONFIG_STALDRV is not set
-
-#
-# Serial drivers
-#
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_PCI=y
-CONFIG_SERIAL_8250_PNP=y
-CONFIG_SERIAL_8250_NR_UARTS=6
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-# CONFIG_SERIAL_8250_DETECT_IRQ is not set
-# CONFIG_SERIAL_8250_RSA is not set
-
-#
-# Non-8250 serial port support
-#
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-# CONFIG_SERIAL_JSM is not set
-CONFIG_UNIX98_PTYS=y
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-# CONFIG_IPMI_HANDLER is not set
-# CONFIG_WATCHDOG is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_EFI_RTC=y
-# CONFIG_R3964 is not set
-# CONFIG_APPLICOM is not set
-CONFIG_AGP=m
-CONFIG_AGP_I460=m
 CONFIG_DRM=m
-CONFIG_DRM_TDFX=m
+CONFIG_DRM_MGA=m
 CONFIG_DRM_R128=m
 CONFIG_DRM_RADEON=m
-CONFIG_DRM_MGA=m
 CONFIG_DRM_SIS=m
-# CONFIG_DRM_VIA is not set
-# CONFIG_DRM_SAVAGE is not set
-CONFIG_RAW_DRIVER=m
-CONFIG_MAX_RAW_DEVS=256
-CONFIG_HPET=y
-# CONFIG_HPET_RTC_IRQ is not set
-CONFIG_HPET_MMAP=y
-# CONFIG_HANGCHECK_TIMER is not set
-# CONFIG_TCG_TPM is not set
-CONFIG_DEVPORT=y
-# CONFIG_I2C is not set
-
-#
-# SPI support
-#
-# CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
-# CONFIG_W1 is not set
-# CONFIG_POWER_SUPPLY is not set
-CONFIG_HWMON=y
-# CONFIG_HWMON_VID is not set
-# CONFIG_SENSORS_ABITUGURU is not set
-# CONFIG_SENSORS_F71805F is not set
-# CONFIG_SENSORS_PC87427 is not set
-# CONFIG_SENSORS_SMSC47M1 is not set
-# CONFIG_SENSORS_SMSC47B397 is not set
-# CONFIG_SENSORS_VT1211 is not set
-# CONFIG_SENSORS_W83627HF is not set
-# CONFIG_HWMON_DEBUG_CHIP is not set
-
-#
-# Multifunction device drivers
-#
-# CONFIG_MFD_SM501 is not set
-
-#
-# Multimedia devices
-#
-# CONFIG_VIDEO_DEV is not set
-# CONFIG_DVB_CORE is not set
-CONFIG_DAB=y
-# CONFIG_USB_DABUSB is not set
-
-#
-# Graphics support
-#
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
-#
-# Display device support
-#
-# CONFIG_DISPLAY_SUPPORT is not set
-# CONFIG_VGASTATE is not set
-# CONFIG_FB is not set
-
-#
-# Console display driver support
-#
-CONFIG_VGA_CONSOLE=y
-# CONFIG_VGACON_SOFT_SCROLLBACK is not set
-CONFIG_DUMMY_CONSOLE=y
-
-#
-# Sound
-#
-# CONFIG_SOUND is not set
-CONFIG_HID_SUPPORT=y
-CONFIG_HID=y
-# CONFIG_HID_DEBUG is not set
-
-#
-# USB Input Devices
-#
-CONFIG_USB_HID=y
-# CONFIG_USB_HIDINPUT_POWERBOOK is not set
-# CONFIG_HID_FF is not set
-# CONFIG_USB_HIDDEV is not set
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_ARCH_HAS_HCD=y
-CONFIG_USB_ARCH_HAS_OHCI=y
-CONFIG_USB_ARCH_HAS_EHCI=y
-CONFIG_USB=y
-# CONFIG_USB_DEBUG is not set
-
-#
-# Miscellaneous USB options
-#
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_DEVICE_CLASS=y
-# CONFIG_USB_DYNAMIC_MINORS is not set
-# CONFIG_USB_SUSPEND is not set
-# CONFIG_USB_PERSIST is not set
-# CONFIG_USB_OTG is not set
-
-#
-# USB Host Controller Drivers
-#
-CONFIG_USB_EHCI_HCD=m
-# CONFIG_USB_EHCI_SPLIT_ISO is not set
-# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
-# CONFIG_USB_EHCI_TT_NEWSCHED is not set
-# CONFIG_USB_ISP116X_HCD is not set
-CONFIG_USB_OHCI_HCD=m
-# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
-# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
-CONFIG_USB_OHCI_LITTLE_ENDIAN=y
-CONFIG_USB_UHCI_HCD=y
-# CONFIG_USB_SL811_HCD is not set
-# CONFIG_USB_R8A66597_HCD is not set
-
-#
-# USB Device Class drivers
-#
-# CONFIG_USB_ACM is not set
-# CONFIG_USB_PRINTER is not set
-
-#
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
-#
-
-#
-# may also be needed; see USB_STORAGE Help for more information
-#
-CONFIG_USB_STORAGE=m
-# CONFIG_USB_STORAGE_DEBUG is not set
-# CONFIG_USB_STORAGE_DATAFAB is not set
-# CONFIG_USB_STORAGE_FREECOM is not set
-# CONFIG_USB_STORAGE_ISD200 is not set
-# CONFIG_USB_STORAGE_DPCM is not set
-# CONFIG_USB_STORAGE_USBAT is not set
-# CONFIG_USB_STORAGE_SDDR09 is not set
-# CONFIG_USB_STORAGE_SDDR55 is not set
-# CONFIG_USB_STORAGE_JUMPSHOT is not set
-# CONFIG_USB_STORAGE_ALAUDA is not set
-# CONFIG_USB_STORAGE_KARMA is not set
-# CONFIG_USB_LIBUSUAL is not set
-
-#
-# USB Imaging devices
-#
-# CONFIG_USB_MDC800 is not set
-# CONFIG_USB_MICROTEK is not set
-# CONFIG_USB_MON is not set
-
-#
-# USB port drivers
-#
-
-#
-# USB Serial Converter support
-#
-# CONFIG_USB_SERIAL is not set
-
-#
-# USB Miscellaneous drivers
-#
-# CONFIG_USB_EMI62 is not set
-# CONFIG_USB_EMI26 is not set
-# CONFIG_USB_ADUTUX is not set
-# CONFIG_USB_AUERSWALD is not set
-# CONFIG_USB_RIO500 is not set
-# CONFIG_USB_LEGOTOWER is not set
-# CONFIG_USB_LCD is not set
-# CONFIG_USB_BERRY_CHARGE is not set
-# CONFIG_USB_LED is not set
-# CONFIG_USB_CYPRESS_CY7C63 is not set
-# CONFIG_USB_CYTHERM is not set
-# CONFIG_USB_PHIDGET is not set
-# CONFIG_USB_IDMOUSE is not set
-# CONFIG_USB_FTDI_ELAN is not set
-# CONFIG_USB_APPLEDISPLAY is not set
-# CONFIG_USB_SISUSBVGA is not set
-# CONFIG_USB_LD is not set
-# CONFIG_USB_TRANCEVIBRATOR is not set
-# CONFIG_USB_IOWARRIOR is not set
-# CONFIG_USB_TEST is not set
-
-#
-# USB DSL modem support
-#
-
-#
-# USB Gadget Support
-#
-# CONFIG_USB_GADGET is not set
-# CONFIG_MMC is not set
-
-#
-# LED devices
-#
-# CONFIG_NEW_LEDS is not set
-
-#
-# LED drivers
-#
-
-#
-# LED Triggers
-#
-# CONFIG_INFINIBAND is not set
-
-#
-# Real Time Clock
-#
-# CONFIG_RTC_CLASS is not set
-
-#
-# DMA Engine support
-#
-# CONFIG_DMA_ENGINE is not set
-
-#
-# DMA Clients
-#
-
-#
-# DMA Devices
-#
-
-#
-# Userspace I/O
-#
-# CONFIG_UIO is not set
-# CONFIG_MSPEC is not set
-
-#
-# File systems
-#
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
+CONFIG_DRM_TDFX=m
+CONFIG_DUMMY=m
+CONFIG_E1000=y
+CONFIG_E100=m
+CONFIG_EFI_PARTITION=y
+CONFIG_EFI_RTC=y
+CONFIG_EFI_VARS=y
+CONFIG_EXPERIMENTAL=y
 CONFIG_EXT2_FS_POSIX_ACL=y
 CONFIG_EXT2_FS_SECURITY=y
-# CONFIG_EXT2_FS_XIP is not set
-CONFIG_EXT3_FS=y
-CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS_POSIX_ACL=y
 CONFIG_EXT3_FS_SECURITY=y
-# CONFIG_EXT4DEV_FS is not set
-CONFIG_JBD=y
-# CONFIG_JBD_DEBUG is not set
-CONFIG_FS_MBCACHE=y
-CONFIG_REISERFS_FS=y
-# CONFIG_REISERFS_CHECK is not set
-# CONFIG_REISERFS_PROC_INFO is not set
-CONFIG_REISERFS_FS_XATTR=y
-CONFIG_REISERFS_FS_POSIX_ACL=y
-CONFIG_REISERFS_FS_SECURITY=y
-# CONFIG_JFS_FS is not set
-CONFIG_FS_POSIX_ACL=y
-CONFIG_XFS_FS=y
-# CONFIG_XFS_QUOTA is not set
-# CONFIG_XFS_SECURITY is not set
-# CONFIG_XFS_POSIX_ACL is not set
-# CONFIG_XFS_RT is not set
-# CONFIG_GFS2_FS is not set
-# CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
+CONFIG_EXT3_FS=y
+CONFIG_FORCE_CPEI_RETARGET=y
+CONFIG_FUSION_CTL=y
+CONFIG_FUSION_FC=y
+CONFIG_FUSION_SPI=y
+CONFIG_FUSION=y
+CONFIG_GAMEPORT=m
+CONFIG_HOTPLUG_CPU=y
+CONFIG_HOTPLUG_PCI_ACPI=m
+CONFIG_HOTPLUG_PCI=m
+CONFIG_HPET=y
+CONFIG_HUGETLBFS=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_IA64_CYCLONE=y
+CONFIG_IA64_DIG=y
+CONFIG_IA64_GRANULE_16MB=y
+CONFIG_IA64_MCA_RECOVERY=y
+CONFIG_IA64_PAGE_SIZE_64KB=y
+CONFIG_IA64_PALINFO=y
+CONFIG_IDE=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_IKCONFIG=y
+CONFIG_INET=y
 CONFIG_INOTIFY=y
-CONFIG_INOTIFY_USER=y
-# CONFIG_QUOTA is not set
-CONFIG_DNOTIFY=y
-CONFIG_AUTOFS_FS=y
-CONFIG_AUTOFS4_FS=y
-# CONFIG_FUSE_FS is not set
-
-#
-# CD-ROM/DVD Filesystems
-#
+CONFIG_IP_MULTICAST=y
+# CONFIG_IPV6 is not set
 CONFIG_ISO9660_FS=m
 CONFIG_JOLIET=y
-# CONFIG_ZISOFS is not set
-CONFIG_UDF_FS=m
-CONFIG_UDF_NLS=y
-
-#
-# DOS/FAT/NT Filesystems
-#
-CONFIG_FAT_FS=y
-# CONFIG_MSDOS_FS is not set
-CONFIG_VFAT_FS=y
-CONFIG_FAT_DEFAULT_CODEPAGE=437
-CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-CONFIG_NTFS_FS=m
-# CONFIG_NTFS_DEBUG is not set
-# CONFIG_NTFS_RW is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_KCORE=y
-CONFIG_PROC_SYSCTL=y
-CONFIG_SYSFS=y
-CONFIG_TMPFS=y
-# CONFIG_TMPFS_POSIX_ACL is not set
-CONFIG_HUGETLBFS=y
-CONFIG_HUGETLB_PAGE=y
-CONFIG_RAMFS=y
-# CONFIG_CONFIGFS_FS is not set
-
-#
-# Miscellaneous filesystems
-#
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-# CONFIG_CRAMFS is not set
-# CONFIG_VXFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
+CONFIG_KALLSYMS_ALL=y
+CONFIG_KEXEC=y
+CONFIG_LOG_BUF_SHIFT=20
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MCKINLEY=y
+CONFIG_MD_LINEAR=m
+CONFIG_MD_MULTIPATH=m
+CONFIG_MD_RAID0=m
+CONFIG_MD_RAID1=m
+CONFIG_MD=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_NETCONSOLE=y
+CONFIG_NETDEVICES=y
+CONFIG_NET_ETHERNET=y
+CONFIG_NET_PCI=y
+CONFIG_NET_TULIP=y
+CONFIG_NFSD=m
+CONFIG_NFSD_V4=y
 CONFIG_NFS_FS=m
 CONFIG_NFS_V3=y
-# CONFIG_NFS_V3_ACL is not set
 CONFIG_NFS_V4=y
-CONFIG_NFS_DIRECTIO=y
-CONFIG_NFSD=m
-CONFIG_NFSD_V3=y
-# CONFIG_NFSD_V3_ACL is not set
-CONFIG_NFSD_V4=y
-CONFIG_NFSD_TCP=y
-CONFIG_LOCKD=m
-CONFIG_LOCKD_V4=y
-CONFIG_EXPORTFS=m
-CONFIG_NFS_COMMON=y
-CONFIG_SUNRPC=m
-CONFIG_SUNRPC_GSS=m
-# CONFIG_SUNRPC_BIND34 is not set
-CONFIG_RPCSEC_GSS_KRB5=y
-# CONFIG_RPCSEC_GSS_SPKM3 is not set
-CONFIG_SMB_FS=m
-CONFIG_SMB_NLS_DEFAULT=y
-CONFIG_SMB_NLS_REMOTE="cp437"
-CONFIG_CIFS=m
-# CONFIG_CIFS_STATS is not set
-# CONFIG_CIFS_WEAK_PW_HASH is not set
-# CONFIG_CIFS_XATTR is not set
-# CONFIG_CIFS_DEBUG2 is not set
-# CONFIG_CIFS_EXPERIMENTAL is not set
-# CONFIG_NCP_FS is not set
-# CONFIG_CODA_FS is not set
-# CONFIG_AFS_FS is not set
-
-#
-# Partition Types
-#
-CONFIG_PARTITION_ADVANCED=y
-# CONFIG_ACORN_PARTITION is not set
-# CONFIG_OSF_PARTITION is not set
-# CONFIG_AMIGA_PARTITION is not set
-# CONFIG_ATARI_PARTITION is not set
-# CONFIG_MAC_PARTITION is not set
-CONFIG_MSDOS_PARTITION=y
-# CONFIG_BSD_DISKLABEL is not set
-# CONFIG_MINIX_SUBPARTITION is not set
-# CONFIG_SOLARIS_X86_PARTITION is not set
-# CONFIG_UNIXWARE_DISKLABEL is not set
-# CONFIG_LDM_PARTITION is not set
-CONFIG_SGI_PARTITION=y
-# CONFIG_ULTRIX_PARTITION is not set
-# CONFIG_SUN_PARTITION is not set
-# CONFIG_KARMA_PARTITION is not set
-CONFIG_EFI_PARTITION=y
-# CONFIG_SYSV68_PARTITION is not set
-
-#
-# Native Language Support
-#
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_1250=m
+CONFIG_NLS_CODEPAGE_1251=m
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_737=m
 CONFIG_NLS_CODEPAGE_775=m
@@ -1144,15 +123,14 @@ CONFIG_NLS_CODEPAGE_864=m
 CONFIG_NLS_CODEPAGE_865=m
 CONFIG_NLS_CODEPAGE_866=m
 CONFIG_NLS_CODEPAGE_869=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_CODEPAGE_950=m
+CONFIG_NLS_CODEPAGE_874=m
 CONFIG_NLS_CODEPAGE_932=m
+CONFIG_NLS_CODEPAGE_936=m
 CONFIG_NLS_CODEPAGE_949=m
-CONFIG_NLS_CODEPAGE_874=m
-CONFIG_NLS_ISO8859_8=m
-CONFIG_NLS_CODEPAGE_1250=m
-CONFIG_NLS_CODEPAGE_1251=m
-# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_CODEPAGE_950=m
+CONFIG_NLS_ISO8859_13=m
+CONFIG_NLS_ISO8859_14=m
+CONFIG_NLS_ISO8859_15=m
 CONFIG_NLS_ISO8859_1=y
 CONFIG_NLS_ISO8859_2=m
 CONFIG_NLS_ISO8859_3=m
@@ -1160,120 +138,50 @@ CONFIG_NLS_ISO8859_4=m
 CONFIG_NLS_ISO8859_5=m
 CONFIG_NLS_ISO8859_6=m
 CONFIG_NLS_ISO8859_7=m
+CONFIG_NLS_ISO8859_8=m
 CONFIG_NLS_ISO8859_9=m
-CONFIG_NLS_ISO8859_13=m
-CONFIG_NLS_ISO8859_14=m
-CONFIG_NLS_ISO8859_15=m
 CONFIG_NLS_KOI8_R=m
 CONFIG_NLS_KOI8_U=m
 CONFIG_NLS_UTF8=m
-
-#
-# Distributed Lock Manager
-#
-# CONFIG_DLM is not set
-
-#
-# Library routines
-#
-CONFIG_BITREVERSE=y
-# CONFIG_CRC_CCITT is not set
-# CONFIG_CRC16 is not set
-# CONFIG_CRC_ITU_T is not set
-CONFIG_CRC32=y
-# CONFIG_CRC7 is not set
-# CONFIG_LIBCRC32C is not set
-CONFIG_PLIST=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HAS_DMA=y
-CONFIG_GENERIC_HARDIRQS=y
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_GENERIC_PENDING_IRQ=y
-CONFIG_IRQ_PER_CPU=y
-
-#
-# Instrumentation Support
-#
-# CONFIG_PROFILING is not set
-# CONFIG_KPROBES is not set
-
-#
-# Kernel hacking
-#
-# CONFIG_PRINTK_TIME is not set
-CONFIG_ENABLE_MUST_CHECK=y
-CONFIG_MAGIC_SYSRQ=y
-# CONFIG_UNUSED_SYMBOLS is not set
-# CONFIG_DEBUG_FS is not set
-# CONFIG_HEADERS_CHECK is not set
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DEBUG_SHIRQ is not set
-CONFIG_DETECT_SOFTLOCKUP=y
-CONFIG_SCHED_DEBUG=y
-# CONFIG_SCHEDSTATS is not set
-# CONFIG_TIMER_STATS is not set
-# CONFIG_DEBUG_SLAB is not set
-# CONFIG_DEBUG_RT_MUTEXES is not set
-# CONFIG_RT_MUTEX_TESTER is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-CONFIG_DEBUG_MUTEXES=y
-# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-# CONFIG_DEBUG_KOBJECT is not set
-# CONFIG_DEBUG_INFO is not set
-# CONFIG_DEBUG_VM is not set
-# CONFIG_DEBUG_LIST is not set
-CONFIG_FORCED_INLINING=y
-# CONFIG_RCU_TORTURE_TEST is not set
-# CONFIG_FAULT_INJECTION is not set
-CONFIG_IA64_GRANULE_16MB=y
-# CONFIG_IA64_GRANULE_64MB is not set
-# CONFIG_IA64_PRINT_HAZARDS is not set
-# CONFIG_DISABLE_VHPT is not set
-# CONFIG_IA64_DEBUG_CMPXCHG is not set
-# CONFIG_IA64_DEBUG_IRQ is not set
-
-#
-# Security options
-#
-# CONFIG_KEYS is not set
-# CONFIG_SECURITY is not set
-CONFIG_CRYPTO=y
-CONFIG_CRYPTO_ALGAPI=y
-CONFIG_CRYPTO_BLKCIPHER=m
-CONFIG_CRYPTO_MANAGER=m
-# CONFIG_CRYPTO_HMAC is not set
-# CONFIG_CRYPTO_XCBC is not set
-# CONFIG_CRYPTO_NULL is not set
-# CONFIG_CRYPTO_MD4 is not set
-CONFIG_CRYPTO_MD5=y
-# CONFIG_CRYPTO_SHA1 is not set
-# CONFIG_CRYPTO_SHA256 is not set
-# CONFIG_CRYPTO_SHA512 is not set
-# CONFIG_CRYPTO_WP512 is not set
-# CONFIG_CRYPTO_TGR192 is not set
-# CONFIG_CRYPTO_GF128MUL is not set
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_CBC=m
-CONFIG_CRYPTO_PCBC=m
-# CONFIG_CRYPTO_LRW is not set
-# CONFIG_CRYPTO_CRYPTD is not set
-CONFIG_CRYPTO_DES=m
-# CONFIG_CRYPTO_FCRYPT is not set
-# CONFIG_CRYPTO_BLOWFISH is not set
-# CONFIG_CRYPTO_TWOFISH is not set
-# CONFIG_CRYPTO_SERPENT is not set
-# CONFIG_CRYPTO_AES is not set
-# CONFIG_CRYPTO_CAST5 is not set
-# CONFIG_CRYPTO_CAST6 is not set
-# CONFIG_CRYPTO_TEA is not set
-# CONFIG_CRYPTO_ARC4 is not set
-# CONFIG_CRYPTO_KHAZAD is not set
-# CONFIG_CRYPTO_ANUBIS is not set
-# CONFIG_CRYPTO_DEFLATE is not set
-# CONFIG_CRYPTO_MICHAEL_MIC is not set
-# CONFIG_CRYPTO_CRC32C is not set
-# CONFIG_CRYPTO_CAMELLIA is not set
-# CONFIG_CRYPTO_TEST is not set
-CONFIG_CRYPTO_HW=y
+CONFIG_NR_CPUS=16
+CONFIG_NTFS_FS=m
+CONFIG_PACKET=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_PERFMON=y
+CONFIG_PERMIT_BSP_REMOVE=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_PROC_KCORE=y
+CONFIG_RAW_DRIVER=m
+CONFIG_REISERFS_FS_POSIX_ACL=y
+CONFIG_REISERFS_FS_SECURITY=y
+CONFIG_REISERFS_FS_XATTR=y
+CONFIG_REISERFS_FS=y
+CONFIG_SCSI_QLOGIC_1280=y
+CONFIG_SCSI_SYM53C8XX_2=y
+CONFIG_SCSI=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_NR_UARTS=6
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_NONSTANDARD=y
+# CONFIG_SERIO_SERPORT is not set
+CONFIG_SGI_PARTITION=y
+CONFIG_SMB_FS=m
+CONFIG_SMB_NLS_DEFAULT=y
+CONFIG_SMP=y
+CONFIG_SYN_COOKIES=y
+CONFIG_SYSVIPC=y
+CONFIG_TIGON3=y
+CONFIG_TMPFS=y
+CONFIG_TULIP=m
+CONFIG_UDF_FS=m
+CONFIG_UNIX=y
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_EHCI_HCD=m
+CONFIG_USB_OHCI_HCD=m
+CONFIG_USB_STORAGE=m
+CONFIG_USB_UHCI_HCD=y
+CONFIG_USB=y
+CONFIG_VFAT_FS=y
+CONFIG_XFS_FS=y
diff --git a/arch/ia64/configs/xen_domu_defconfig b/arch/ia64/configs/xen_domu_defconfig
index c67eafc4bb38..5f6d284723a4 100644
--- a/arch/ia64/configs/xen_domu_defconfig
+++ b/arch/ia64/configs/xen_domu_defconfig
@@ -1,1374 +1,121 @@
-#
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.29-rc1
-# Fri Jan 16 11:49:59 2009
-#
-CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-
-#
-# General setup
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_LOCK_KERNEL=y
-CONFIG_INIT_ENV_ARG_LIMIT=32
-CONFIG_LOCALVERSION=""
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-CONFIG_SYSVIPC_SYSCTL=y
-CONFIG_POSIX_MQUEUE=y
-# CONFIG_BSD_PROCESS_ACCT is not set
-# CONFIG_TASKSTATS is not set
-# CONFIG_AUDIT is not set
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=20
-CONFIG_HAVE_UNSTABLE_SCHED_CLOCK=y
-# CONFIG_GROUP_SCHED is not set
-
-#
-# Control Group support
-#
-# CONFIG_CGROUPS is not set
-CONFIG_SYSFS_DEPRECATED=y
-CONFIG_SYSFS_DEPRECATED_V2=y
-# CONFIG_RELAY is not set
-CONFIG_NAMESPACES=y
-# CONFIG_UTS_NS is not set
-# CONFIG_IPC_NS is not set
-# CONFIG_USER_NS is not set
-# CONFIG_PID_NS is not set
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_SYSCTL=y
-# CONFIG_EMBEDDED is not set
-CONFIG_SYSCTL_SYSCALL=y
-CONFIG_KALLSYMS=y
-CONFIG_KALLSYMS_ALL=y
-CONFIG_KALLSYMS_STRIP_GENERATED=y
-# CONFIG_KALLSYMS_EXTRA_PASS is not set
-CONFIG_HOTPLUG=y
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-CONFIG_COMPAT_BRK=y
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_ANON_INODES=y
-CONFIG_EPOLL=y
-CONFIG_SIGNALFD=y
-CONFIG_TIMERFD=y
-CONFIG_EVENTFD=y
-CONFIG_SHMEM=y
-CONFIG_AIO=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_PCI_QUIRKS=y
-CONFIG_SLUB_DEBUG=y
-# CONFIG_SLAB is not set
-CONFIG_SLUB=y
-# CONFIG_SLOB is not set
-# CONFIG_PROFILING is not set
-CONFIG_HAVE_OPROFILE=y
-# CONFIG_KPROBES is not set
-CONFIG_HAVE_KPROBES=y
-CONFIG_HAVE_KRETPROBES=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_USE_GENERIC_SMP_HELPERS=y
-# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
-CONFIG_SLABINFO=y
-CONFIG_RT_MUTEXES=y
-CONFIG_BASE_SMALL=0
-CONFIG_MODULES=y
-# CONFIG_MODULE_FORCE_LOAD is not set
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_MODULE_FORCE_UNLOAD is not set
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-CONFIG_STOP_MACHINE=y
-CONFIG_BLOCK=y
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_BLK_DEV_INTEGRITY is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-CONFIG_DEFAULT_AS=y
-# CONFIG_DEFAULT_DEADLINE is not set
-# CONFIG_DEFAULT_CFQ is not set
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="anticipatory"
-CONFIG_CLASSIC_RCU=y
-# CONFIG_TREE_RCU is not set
-# CONFIG_PREEMPT_RCU is not set
-# CONFIG_TREE_RCU_TRACE is not set
-# CONFIG_PREEMPT_RCU_TRACE is not set
-CONFIG_FREEZER=y
-
-#
-# Processor type and features
-#
-CONFIG_IA64=y
-CONFIG_64BIT=y
-CONFIG_ZONE_DMA=y
-CONFIG_QUICKLIST=y
-CONFIG_MMU=y
-CONFIG_SWIOTLB=y
-CONFIG_IOMMU_HELPER=y
-CONFIG_RWSEM_XCHGADD_ALGORITHM=y
-CONFIG_HUGETLB_PAGE_SIZE_VARIABLE=y
-CONFIG_GENERIC_FIND_NEXT_BIT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_GENERIC_TIME=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_HAVE_SETUP_PER_CPU_AREA=y
-CONFIG_DMI=y
-CONFIG_EFI=y
-CONFIG_GENERIC_IOMAP=y
-CONFIG_SCHED_OMIT_FRAME_POINTER=y
-CONFIG_AUDIT_ARCH=y
-CONFIG_PARAVIRT_GUEST=y
-CONFIG_PARAVIRT=y
-CONFIG_XEN=y
-CONFIG_XEN_XENCOMM=y
-CONFIG_NO_IDLE_HZ=y
-# CONFIG_IA64_GENERIC is not set
-# CONFIG_IA64_DIG is not set
-# CONFIG_IA64_DIG_VTD is not set
-# CONFIG_IA64_HP_ZX1 is not set
-# CONFIG_IA64_HP_ZX1_SWIOTLB is not set
-# CONFIG_IA64_SGI_SN2 is not set
-# CONFIG_IA64_SGI_UV is not set
-# CONFIG_IA64_HP_SIM is not set
-CONFIG_IA64_XEN_GUEST=y
-# CONFIG_ITANIUM is not set
-CONFIG_MCKINLEY=y
-# CONFIG_IA64_PAGE_SIZE_4KB is not set
-# CONFIG_IA64_PAGE_SIZE_8KB is not set
-CONFIG_IA64_PAGE_SIZE_16KB=y
-# CONFIG_IA64_PAGE_SIZE_64KB is not set
-CONFIG_PGTABLE_3=y
-# CONFIG_PGTABLE_4 is not set
-CONFIG_HZ=250
-# CONFIG_HZ_100 is not set
-CONFIG_HZ_250=y
-# CONFIG_HZ_300 is not set
-# CONFIG_HZ_1000 is not set
-# CONFIG_SCHED_HRTICK is not set
-CONFIG_IA64_L1_CACHE_SHIFT=7
-CONFIG_IA64_CYCLONE=y
-CONFIG_IOSAPIC=y
-CONFIG_FORCE_MAX_ZONEORDER=17
-# CONFIG_VIRT_CPU_ACCOUNTING is not set
-CONFIG_SMP=y
-CONFIG_NR_CPUS=16
-CONFIG_HOTPLUG_CPU=y
-CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
-CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
-# CONFIG_SCHED_SMT is not set
-CONFIG_PERMIT_BSP_REMOVE=y
-CONFIG_FORCE_CPEI_RETARGET=y
-CONFIG_PREEMPT_NONE=y
-# CONFIG_PREEMPT_VOLUNTARY is not set
-# CONFIG_PREEMPT is not set
-CONFIG_SELECT_MEMORY_MODEL=y
-CONFIG_FLATMEM_MANUAL=y
-# CONFIG_DISCONTIGMEM_MANUAL is not set
-# CONFIG_SPARSEMEM_MANUAL is not set
-CONFIG_FLATMEM=y
-CONFIG_FLAT_NODE_MEM_MAP=y
-CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_SPLIT_PTLOCK_CPUS=4
-CONFIG_MIGRATION=y
-CONFIG_PHYS_ADDR_T_64BIT=y
-CONFIG_ZONE_DMA_FLAG=1
-CONFIG_BOUNCE=y
-CONFIG_NR_QUICK=1
-CONFIG_VIRT_TO_BUS=y
-CONFIG_UNEVICTABLE_LRU=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
-CONFIG_ARCH_FLATMEM_ENABLE=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_POPULATES_NODE_MAP=y
-CONFIG_VIRTUAL_MEM_MAP=y
-CONFIG_HOLES_IN_ZONE=y
-CONFIG_IA64_MCA_RECOVERY=y
-CONFIG_PERFMON=y
-CONFIG_IA64_PALINFO=y
-# CONFIG_IA64_MC_ERR_INJECT is not set
-# CONFIG_IA64_ESI is not set
-# CONFIG_IA64_HP_AML_NFW is not set
-CONFIG_KEXEC=y
-# CONFIG_CRASH_DUMP is not set
-
-#
-# Firmware Drivers
-#
-# CONFIG_FIRMWARE_MEMMAP is not set
-CONFIG_EFI_VARS=y
-CONFIG_EFI_PCDP=y
-CONFIG_DMIID=y
-CONFIG_BINFMT_ELF=y
-# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-# CONFIG_HAVE_AOUT is not set
-CONFIG_BINFMT_MISC=m
-
-#
-# Power management and ACPI options
-#
-CONFIG_PM=y
-# CONFIG_PM_DEBUG is not set
-CONFIG_PM_SLEEP=y
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-CONFIG_ACPI=y
-CONFIG_ACPI_SLEEP=y
-CONFIG_ACPI_PROCFS=y
-CONFIG_ACPI_PROCFS_POWER=y
-CONFIG_ACPI_SYSFS_POWER=y
-CONFIG_ACPI_PROC_EVENT=y
 CONFIG_ACPI_BUTTON=m
+CONFIG_ACPI_CONTAINER=m
 CONFIG_ACPI_FAN=m
-# CONFIG_ACPI_DOCK is not set
 CONFIG_ACPI_PROCESSOR=m
-CONFIG_ACPI_HOTPLUG_CPU=y
-CONFIG_ACPI_THERMAL=m
-# CONFIG_ACPI_CUSTOM_DSDT is not set
-CONFIG_ACPI_BLACKLIST_YEAR=0
-# CONFIG_ACPI_DEBUG is not set
-# CONFIG_ACPI_PCI_SLOT is not set
-CONFIG_ACPI_SYSTEM=y
-CONFIG_ACPI_CONTAINER=m
-
-#
-# CPU Frequency scaling
-#
-# CONFIG_CPU_FREQ is not set
-
-#
-# Bus options (PCI, PCMCIA)
-#
-CONFIG_PCI=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_SYSCALL=y
-# CONFIG_PCIEPORTBUS is not set
-CONFIG_ARCH_SUPPORTS_MSI=y
-# CONFIG_PCI_MSI is not set
-CONFIG_PCI_LEGACY=y
-# CONFIG_PCI_DEBUG is not set
-# CONFIG_PCI_STUB is not set
-CONFIG_HOTPLUG_PCI=m
-# CONFIG_HOTPLUG_PCI_FAKE is not set
-CONFIG_HOTPLUG_PCI_ACPI=m
-# CONFIG_HOTPLUG_PCI_ACPI_IBM is not set
-# CONFIG_HOTPLUG_PCI_CPCI is not set
-# CONFIG_HOTPLUG_PCI_SHPC is not set
-# CONFIG_PCCARD is not set
-CONFIG_NET=y
-
-#
-# Networking options
-#
-# CONFIG_NET_NS is not set
-CONFIG_COMPAT_NET_DEV_OPS=y
-CONFIG_PACKET=y
-# CONFIG_PACKET_MMAP is not set
-CONFIG_UNIX=y
-CONFIG_XFRM=y
-# CONFIG_XFRM_USER is not set
-# CONFIG_XFRM_SUB_POLICY is not set
-# CONFIG_XFRM_MIGRATE is not set
-# CONFIG_XFRM_STATISTICS is not set
-# CONFIG_NET_KEY is not set
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_FIB_HASH=y
-# CONFIG_IP_PNP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_IP_MROUTE is not set
+CONFIG_ACPI_PROCFS=y
+CONFIG_AGP=m
 CONFIG_ARPD=y
-CONFIG_SYN_COOKIES=y
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_XFRM_TUNNEL is not set
-# CONFIG_INET_TUNNEL is not set
-CONFIG_INET_XFRM_MODE_TRANSPORT=y
-CONFIG_INET_XFRM_MODE_TUNNEL=y
-CONFIG_INET_XFRM_MODE_BEET=y
-# CONFIG_INET_LRO is not set
-CONFIG_INET_DIAG=y
-CONFIG_INET_TCP_DIAG=y
-# CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TCP_CONG_CUBIC=y
-CONFIG_DEFAULT_TCP_CONG="cubic"
-# CONFIG_TCP_MD5SIG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_NETWORK_SECMARK is not set
-# CONFIG_NETFILTER is not set
-# CONFIG_IP_DCCP is not set
-# CONFIG_IP_SCTP is not set
-# CONFIG_TIPC is not set
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_NET_DSA is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-# CONFIG_NET_SCHED is not set
-# CONFIG_DCB is not set
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_HAMRADIO is not set
-# CONFIG_CAN is not set
-# CONFIG_IRDA is not set
-# CONFIG_BT is not set
-# CONFIG_AF_RXRPC is not set
-# CONFIG_PHONET is not set
-# CONFIG_WIRELESS is not set
-# CONFIG_WIMAX is not set
-# CONFIG_RFKILL is not set
-# CONFIG_NET_9P is not set
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=y
-CONFIG_FIRMWARE_IN_KERNEL=y
-CONFIG_EXTRA_FIRMWARE=""
-# CONFIG_DEBUG_DRIVER is not set
-# CONFIG_DEBUG_DEVRES is not set
-# CONFIG_SYS_HYPERVISOR is not set
-# CONFIG_CONNECTOR is not set
-# CONFIG_MTD is not set
-# CONFIG_PARPORT is not set
-CONFIG_PNP=y
-CONFIG_PNP_DEBUG_MESSAGES=y
-
-#
-# Protocols
-#
-CONFIG_PNPACPI=y
-CONFIG_BLK_DEV=y
-# CONFIG_BLK_CPQ_DA is not set
-# CONFIG_BLK_CPQ_CISS_DA is not set
-# CONFIG_BLK_DEV_DAC960 is not set
-# CONFIG_BLK_DEV_UMEM is not set
-# CONFIG_BLK_DEV_COW_COMMON is not set
-CONFIG_BLK_DEV_LOOP=m
+CONFIG_AUTOFS4_FS=y
+CONFIG_AUTOFS_FS=y
+CONFIG_BINFMT_MISC=m
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_BLK_DEV_CMD64X=y
 CONFIG_BLK_DEV_CRYPTOLOOP=m
-CONFIG_BLK_DEV_NBD=m
-# CONFIG_BLK_DEV_SX8 is not set
-# CONFIG_BLK_DEV_UB is not set
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=4096
-# CONFIG_BLK_DEV_XIP is not set
-# CONFIG_CDROM_PKTCDVD is not set
-# CONFIG_ATA_OVER_ETH is not set
-CONFIG_XEN_BLKDEV_FRONTEND=y
-# CONFIG_BLK_DEV_HD is not set
-CONFIG_MISC_DEVICES=y
-# CONFIG_PHANTOM is not set
-# CONFIG_EEPROM_93CX6 is not set
-# CONFIG_SGI_IOC4 is not set
-# CONFIG_TIFM_CORE is not set
-# CONFIG_ICS932S401 is not set
-# CONFIG_ENCLOSURE_SERVICES is not set
-# CONFIG_HP_ILO is not set
-# CONFIG_C2PORT is not set
-CONFIG_HAVE_IDE=y
-CONFIG_IDE=y
-
-#
-# Please see Documentation/ide/ide.txt for help/info on IDE drives
-#
-CONFIG_IDE_TIMINGS=y
-CONFIG_IDE_ATAPI=y
-# CONFIG_BLK_DEV_IDE_SATA is not set
-CONFIG_IDE_GD=y
-CONFIG_IDE_GD_ATA=y
-# CONFIG_IDE_GD_ATAPI is not set
-CONFIG_BLK_DEV_IDECD=y
-CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y
-# CONFIG_BLK_DEV_IDETAPE is not set
-# CONFIG_BLK_DEV_IDEACPI is not set
-# CONFIG_IDE_TASK_IOCTL is not set
-CONFIG_IDE_PROC_FS=y
-
-#
-# IDE chipset support/bugfixes
-#
-# CONFIG_IDE_GENERIC is not set
-# CONFIG_BLK_DEV_PLATFORM is not set
-# CONFIG_BLK_DEV_IDEPNP is not set
-CONFIG_BLK_DEV_IDEDMA_SFF=y
-
-#
-# PCI IDE chipsets support
-#
-CONFIG_BLK_DEV_IDEPCI=y
-CONFIG_IDEPCI_PCIBUS_ORDER=y
-# CONFIG_BLK_DEV_OFFBOARD is not set
+CONFIG_BLK_DEV_DM=m
 CONFIG_BLK_DEV_GENERIC=y
-# CONFIG_BLK_DEV_OPTI621 is not set
-CONFIG_BLK_DEV_IDEDMA_PCI=y
-# CONFIG_BLK_DEV_AEC62XX is not set
-# CONFIG_BLK_DEV_ALI15X3 is not set
-# CONFIG_BLK_DEV_AMD74XX is not set
-CONFIG_BLK_DEV_CMD64X=y
-# CONFIG_BLK_DEV_TRIFLEX is not set
-# CONFIG_BLK_DEV_CS5520 is not set
-# CONFIG_BLK_DEV_CS5530 is not set
-# CONFIG_BLK_DEV_HPT366 is not set
-# CONFIG_BLK_DEV_JMICRON is not set
-# CONFIG_BLK_DEV_SC1200 is not set
+CONFIG_BLK_DEV_IDECD=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_BLK_DEV_LOOP=m
+CONFIG_BLK_DEV_MD=m
+CONFIG_BLK_DEV_NBD=m
 CONFIG_BLK_DEV_PIIX=y
-# CONFIG_BLK_DEV_IT8172 is not set
-# CONFIG_BLK_DEV_IT8213 is not set
-# CONFIG_BLK_DEV_IT821X is not set
-# CONFIG_BLK_DEV_NS87415 is not set
-# CONFIG_BLK_DEV_PDC202XX_OLD is not set
-# CONFIG_BLK_DEV_PDC202XX_NEW is not set
-# CONFIG_BLK_DEV_SVWKS is not set
-# CONFIG_BLK_DEV_SIIMAGE is not set
-# CONFIG_BLK_DEV_SLC90E66 is not set
-# CONFIG_BLK_DEV_TRM290 is not set
-# CONFIG_BLK_DEV_VIA82CXXX is not set
-# CONFIG_BLK_DEV_TC86C001 is not set
-CONFIG_BLK_DEV_IDEDMA=y
-
-#
-# SCSI device support
-#
-# CONFIG_RAID_ATTRS is not set
-CONFIG_SCSI=y
-CONFIG_SCSI_DMA=y
-# CONFIG_SCSI_TGT is not set
-CONFIG_SCSI_NETLINK=y
-CONFIG_SCSI_PROC_FS=y
-
-#
-# SCSI support type (disk, tape, CD-ROM)
-#
+CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_SD=y
-CONFIG_CHR_DEV_ST=m
-# CONFIG_CHR_DEV_OSST is not set
 CONFIG_BLK_DEV_SR=m
-# CONFIG_BLK_DEV_SR_VENDOR is not set
 CONFIG_CHR_DEV_SG=m
-# CONFIG_CHR_DEV_SCH is not set
-
-#
-# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
-#
-# CONFIG_SCSI_MULTI_LUN is not set
-# CONFIG_SCSI_CONSTANTS is not set
-# CONFIG_SCSI_LOGGING is not set
-# CONFIG_SCSI_SCAN_ASYNC is not set
-CONFIG_SCSI_WAIT_SCAN=m
-
-#
-# SCSI Transports
-#
-CONFIG_SCSI_SPI_ATTRS=y
-CONFIG_SCSI_FC_ATTRS=y
-# CONFIG_SCSI_ISCSI_ATTRS is not set
-# CONFIG_SCSI_SAS_LIBSAS is not set
-# CONFIG_SCSI_SRP_ATTRS is not set
-CONFIG_SCSI_LOWLEVEL=y
-# CONFIG_ISCSI_TCP is not set
-# CONFIG_SCSI_CXGB3_ISCSI is not set
-# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
-# CONFIG_SCSI_3W_9XXX is not set
-# CONFIG_SCSI_ACARD is not set
-# CONFIG_SCSI_AACRAID is not set
-# CONFIG_SCSI_AIC7XXX is not set
-# CONFIG_SCSI_AIC7XXX_OLD is not set
-# CONFIG_SCSI_AIC79XX is not set
-# CONFIG_SCSI_AIC94XX is not set
-# CONFIG_SCSI_DPT_I2O is not set
-# CONFIG_SCSI_ADVANSYS is not set
-# CONFIG_SCSI_ARCMSR is not set
-# CONFIG_MEGARAID_NEWGEN is not set
-# CONFIG_MEGARAID_LEGACY is not set
-# CONFIG_MEGARAID_SAS is not set
-# CONFIG_SCSI_HPTIOP is not set
-# CONFIG_LIBFC is not set
-# CONFIG_FCOE is not set
-# CONFIG_SCSI_DMX3191D is not set
-# CONFIG_SCSI_FUTURE_DOMAIN is not set
-# CONFIG_SCSI_IPS is not set
-# CONFIG_SCSI_INITIO is not set
-# CONFIG_SCSI_INIA100 is not set
-# CONFIG_SCSI_MVSAS is not set
-# CONFIG_SCSI_STEX is not set
-CONFIG_SCSI_SYM53C8XX_2=y
-CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1
-CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16
-CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64
-CONFIG_SCSI_SYM53C8XX_MMIO=y
-CONFIG_SCSI_QLOGIC_1280=y
-# CONFIG_SCSI_QLA_FC is not set
-# CONFIG_SCSI_QLA_ISCSI is not set
-# CONFIG_SCSI_LPFC is not set
-# CONFIG_SCSI_DC395x is not set
-# CONFIG_SCSI_DC390T is not set
-# CONFIG_SCSI_DEBUG is not set
-# CONFIG_SCSI_SRP is not set
-# CONFIG_SCSI_DH is not set
-# CONFIG_ATA is not set
-CONFIG_MD=y
-CONFIG_BLK_DEV_MD=m
-CONFIG_MD_LINEAR=m
-CONFIG_MD_RAID0=m
-CONFIG_MD_RAID1=m
-# CONFIG_MD_RAID10 is not set
-# CONFIG_MD_RAID456 is not set
-CONFIG_MD_MULTIPATH=m
-# CONFIG_MD_FAULTY is not set
-CONFIG_BLK_DEV_DM=m
-# CONFIG_DM_DEBUG is not set
+CONFIG_CHR_DEV_ST=m
+CONFIG_CIFS=m
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_ECB=m
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_PCBC=m
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_MUTEXES=y
 CONFIG_DM_CRYPT=m
-CONFIG_DM_SNAPSHOT=m
 CONFIG_DM_MIRROR=m
+CONFIG_DM_SNAPSHOT=m
 CONFIG_DM_ZERO=m
-# CONFIG_DM_MULTIPATH is not set
-# CONFIG_DM_DELAY is not set
-# CONFIG_DM_UEVENT is not set
-CONFIG_FUSION=y
-CONFIG_FUSION_SPI=y
-CONFIG_FUSION_FC=y
-# CONFIG_FUSION_SAS is not set
-CONFIG_FUSION_MAX_SGE=128
-CONFIG_FUSION_CTL=y
-# CONFIG_FUSION_LOGGING is not set
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# Enable only one of the two stacks, unless you know what you are doing
-#
-# CONFIG_FIREWIRE is not set
-# CONFIG_IEEE1394 is not set
-# CONFIG_I2O is not set
-CONFIG_NETDEVICES=y
-CONFIG_DUMMY=m
-# CONFIG_BONDING is not set
-# CONFIG_MACVLAN is not set
-# CONFIG_EQUALIZER is not set
-# CONFIG_TUN is not set
-# CONFIG_VETH is not set
-# CONFIG_NET_SB1000 is not set
-# CONFIG_ARCNET is not set
-CONFIG_PHYLIB=y
-
-#
-# MII PHY device drivers
-#
-# CONFIG_MARVELL_PHY is not set
-# CONFIG_DAVICOM_PHY is not set
-# CONFIG_QSEMI_PHY is not set
-# CONFIG_LXT_PHY is not set
-# CONFIG_CICADA_PHY is not set
-# CONFIG_VITESSE_PHY is not set
-# CONFIG_SMSC_PHY is not set
-# CONFIG_BROADCOM_PHY is not set
-# CONFIG_ICPLUS_PHY is not set
-# CONFIG_REALTEK_PHY is not set
-# CONFIG_NATIONAL_PHY is not set
-# CONFIG_STE10XP is not set
-# CONFIG_LSI_ET1011C_PHY is not set
-# CONFIG_FIXED_PHY is not set
-# CONFIG_MDIO_BITBANG is not set
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=m
-# CONFIG_HAPPYMEAL is not set
-# CONFIG_SUNGEM is not set
-# CONFIG_CASSINI is not set
-# CONFIG_NET_VENDOR_3COM is not set
-CONFIG_NET_TULIP=y
-# CONFIG_DE2104X is not set
-CONFIG_TULIP=m
-# CONFIG_TULIP_MWI is not set
-# CONFIG_TULIP_MMIO is not set
-# CONFIG_TULIP_NAPI is not set
-# CONFIG_DE4X5 is not set
-# CONFIG_WINBOND_840 is not set
-# CONFIG_DM9102 is not set
-# CONFIG_ULI526X is not set
-# CONFIG_HP100 is not set
-# CONFIG_IBM_NEW_EMAC_ZMII is not set
-# CONFIG_IBM_NEW_EMAC_RGMII is not set
-# CONFIG_IBM_NEW_EMAC_TAH is not set
-# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
-# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
-# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
-CONFIG_NET_PCI=y
-# CONFIG_PCNET32 is not set
-# CONFIG_AMD8111_ETH is not set
-# CONFIG_ADAPTEC_STARFIRE is not set
-# CONFIG_B44 is not set
-# CONFIG_FORCEDETH is not set
-CONFIG_E100=m
-# CONFIG_FEALNX is not set
-# CONFIG_NATSEMI is not set
-# CONFIG_NE2K_PCI is not set
-# CONFIG_8139CP is not set
-# CONFIG_8139TOO is not set
-# CONFIG_R6040 is not set
-# CONFIG_SIS900 is not set
-# CONFIG_EPIC100 is not set
-# CONFIG_SMSC9420 is not set
-# CONFIG_SUNDANCE is not set
-# CONFIG_TLAN is not set
-# CONFIG_VIA_RHINE is not set
-# CONFIG_SC92031 is not set
-# CONFIG_ATL2 is not set
-CONFIG_NETDEV_1000=y
-# CONFIG_ACENIC is not set
-# CONFIG_DL2K is not set
-CONFIG_E1000=y
-# CONFIG_E1000E is not set
-# CONFIG_IP1000 is not set
-# CONFIG_IGB is not set
-# CONFIG_NS83820 is not set
-# CONFIG_HAMACHI is not set
-# CONFIG_YELLOWFIN is not set
-# CONFIG_R8169 is not set
-# CONFIG_SIS190 is not set
-# CONFIG_SKGE is not set
-# CONFIG_SKY2 is not set
-# CONFIG_VIA_VELOCITY is not set
-CONFIG_TIGON3=y
-# CONFIG_BNX2 is not set
-# CONFIG_QLA3XXX is not set
-# CONFIG_ATL1 is not set
-# CONFIG_ATL1E is not set
-# CONFIG_JME is not set
-CONFIG_NETDEV_10000=y
-# CONFIG_CHELSIO_T1 is not set
-CONFIG_CHELSIO_T3_DEPENDS=y
-# CONFIG_CHELSIO_T3 is not set
-# CONFIG_ENIC is not set
-# CONFIG_IXGBE is not set
-# CONFIG_IXGB is not set
-# CONFIG_S2IO is not set
-# CONFIG_MYRI10GE is not set
-# CONFIG_NETXEN_NIC is not set
-# CONFIG_NIU is not set
-# CONFIG_MLX4_EN is not set
-# CONFIG_MLX4_CORE is not set
-# CONFIG_TEHUTI is not set
-# CONFIG_BNX2X is not set
-# CONFIG_QLGE is not set
-# CONFIG_SFC is not set
-# CONFIG_TR is not set
-
-#
-# Wireless LAN
-#
-# CONFIG_WLAN_PRE80211 is not set
-# CONFIG_WLAN_80211 is not set
-# CONFIG_IWLWIFI_LEDS is not set
-
-#
-# Enable WiMAX (Networking options) to see the WiMAX drivers
-#
-
-#
-# USB Network Adapters
-#
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_RTL8150 is not set
-# CONFIG_USB_USBNET is not set
-# CONFIG_WAN is not set
-CONFIG_XEN_NETDEV_FRONTEND=y
-# CONFIG_FDDI is not set
-# CONFIG_HIPPI is not set
-# CONFIG_PPP is not set
-# CONFIG_SLIP is not set
-# CONFIG_NET_FC is not set
-CONFIG_NETCONSOLE=y
-# CONFIG_NETCONSOLE_DYNAMIC is not set
-CONFIG_NETPOLL=y
-# CONFIG_NETPOLL_TRAP is not set
-CONFIG_NET_POLL_CONTROLLER=y
-# CONFIG_ISDN is not set
-# CONFIG_PHONE is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-# CONFIG_INPUT_FF_MEMLESS is not set
-# CONFIG_INPUT_POLLDEV is not set
-
-#
-# Userland interfaces
-#
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-# CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_EVDEV is not set
-# CONFIG_INPUT_EVBUG is not set
-
-#
-# Input Device Drivers
-#
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_KEYBOARD_ATKBD=y
-# CONFIG_KEYBOARD_SUNKBD is not set
-# CONFIG_KEYBOARD_LKKBD is not set
-# CONFIG_KEYBOARD_XTKBD is not set
-# CONFIG_KEYBOARD_NEWTON is not set
-# CONFIG_KEYBOARD_STOWAWAY is not set
-CONFIG_INPUT_MOUSE=y
-CONFIG_MOUSE_PS2=y
-CONFIG_MOUSE_PS2_ALPS=y
-CONFIG_MOUSE_PS2_LOGIPS2PP=y
-CONFIG_MOUSE_PS2_SYNAPTICS=y
-CONFIG_MOUSE_PS2_LIFEBOOK=y
-CONFIG_MOUSE_PS2_TRACKPOINT=y
-# CONFIG_MOUSE_PS2_ELANTECH is not set
-# CONFIG_MOUSE_PS2_TOUCHKIT is not set
-# CONFIG_MOUSE_SERIAL is not set
-# CONFIG_MOUSE_APPLETOUCH is not set
-# CONFIG_MOUSE_BCM5974 is not set
-# CONFIG_MOUSE_VSXXXAA is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TABLET is not set
-# CONFIG_INPUT_TOUCHSCREEN is not set
-# CONFIG_INPUT_MISC is not set
-
-#
-# Hardware I/O ports
-#
-CONFIG_SERIO=y
-CONFIG_SERIO_I8042=y
-# CONFIG_SERIO_SERPORT is not set
-# CONFIG_SERIO_PCIPS2 is not set
-CONFIG_SERIO_LIBPS2=y
-# CONFIG_SERIO_RAW is not set
-CONFIG_GAMEPORT=m
-# CONFIG_GAMEPORT_NS558 is not set
-# CONFIG_GAMEPORT_L4 is not set
-# CONFIG_GAMEPORT_EMU10K1 is not set
-# CONFIG_GAMEPORT_FM801 is not set
-
-#
-# Character devices
-#
-CONFIG_VT=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
-CONFIG_DEVKMEM=y
-CONFIG_SERIAL_NONSTANDARD=y
-# CONFIG_COMPUTONE is not set
-# CONFIG_ROCKETPORT is not set
-# CONFIG_CYCLADES is not set
-# CONFIG_DIGIEPCA is not set
-# CONFIG_MOXA_INTELLIO is not set
-# CONFIG_MOXA_SMARTIO is not set
-# CONFIG_ISI is not set
-# CONFIG_SYNCLINKMP is not set
-# CONFIG_SYNCLINK_GT is not set
-# CONFIG_N_HDLC is not set
-# CONFIG_RISCOM8 is not set
-# CONFIG_SPECIALIX is not set
-# CONFIG_SX is not set
-# CONFIG_RIO is not set
-# CONFIG_STALDRV is not set
-# CONFIG_NOZOMI is not set
-
-#
-# Serial drivers
-#
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_PCI=y
-CONFIG_SERIAL_8250_PNP=y
-CONFIG_SERIAL_8250_NR_UARTS=6
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-# CONFIG_SERIAL_8250_DETECT_IRQ is not set
-# CONFIG_SERIAL_8250_RSA is not set
-
-#
-# Non-8250 serial port support
-#
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-# CONFIG_SERIAL_JSM is not set
-CONFIG_UNIX98_PTYS=y
-# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-CONFIG_HVC_DRIVER=y
-CONFIG_HVC_IRQ=y
-CONFIG_HVC_XEN=y
-# CONFIG_IPMI_HANDLER is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_EFI_RTC=y
-# CONFIG_R3964 is not set
-# CONFIG_APPLICOM is not set
-CONFIG_RAW_DRIVER=m
-CONFIG_MAX_RAW_DEVS=256
-CONFIG_HPET=y
-CONFIG_HPET_MMAP=y
-# CONFIG_HANGCHECK_TIMER is not set
-# CONFIG_TCG_TPM is not set
-CONFIG_DEVPORT=y
-CONFIG_I2C=m
-CONFIG_I2C_BOARDINFO=y
-# CONFIG_I2C_CHARDEV is not set
-CONFIG_I2C_HELPER_AUTO=y
-CONFIG_I2C_ALGOBIT=m
-
-#
-# I2C Hardware Bus support
-#
-
-#
-# PC SMBus host controller drivers
-#
-# CONFIG_I2C_ALI1535 is not set
-# CONFIG_I2C_ALI1563 is not set
-# CONFIG_I2C_ALI15X3 is not set
-# CONFIG_I2C_AMD756 is not set
-# CONFIG_I2C_AMD8111 is not set
-# CONFIG_I2C_I801 is not set
-# CONFIG_I2C_ISCH is not set
-# CONFIG_I2C_PIIX4 is not set
-# CONFIG_I2C_NFORCE2 is not set
-# CONFIG_I2C_SIS5595 is not set
-# CONFIG_I2C_SIS630 is not set
-# CONFIG_I2C_SIS96X is not set
-# CONFIG_I2C_VIA is not set
-# CONFIG_I2C_VIAPRO is not set
-
-#
-# I2C system bus drivers (mostly embedded / system-on-chip)
-#
-# CONFIG_I2C_OCORES is not set
-# CONFIG_I2C_SIMTEC is not set
-
-#
-# External I2C/SMBus adapter drivers
-#
-# CONFIG_I2C_PARPORT_LIGHT is not set
-# CONFIG_I2C_TAOS_EVM is not set
-# CONFIG_I2C_TINY_USB is not set
-
-#
-# Graphics adapter I2C/DDC channel drivers
-#
-# CONFIG_I2C_VOODOO3 is not set
-
-#
-# Other I2C/SMBus bus drivers
-#
-# CONFIG_I2C_PCA_PLATFORM is not set
-# CONFIG_I2C_STUB is not set
-
-#
-# Miscellaneous I2C Chip support
-#
-# CONFIG_DS1682 is not set
-# CONFIG_AT24 is not set
-# CONFIG_SENSORS_EEPROM is not set
-# CONFIG_SENSORS_PCF8574 is not set
-# CONFIG_PCF8575 is not set
-# CONFIG_SENSORS_PCA9539 is not set
-# CONFIG_SENSORS_PCF8591 is not set
-# CONFIG_SENSORS_MAX6875 is not set
-# CONFIG_SENSORS_TSL2550 is not set
-# CONFIG_I2C_DEBUG_CORE is not set
-# CONFIG_I2C_DEBUG_ALGO is not set
-# CONFIG_I2C_DEBUG_BUS is not set
-# CONFIG_I2C_DEBUG_CHIP is not set
-# CONFIG_SPI is not set
-# CONFIG_W1 is not set
-CONFIG_POWER_SUPPLY=y
-# CONFIG_POWER_SUPPLY_DEBUG is not set
-# CONFIG_PDA_POWER is not set
-# CONFIG_BATTERY_DS2760 is not set
-# CONFIG_BATTERY_BQ27x00 is not set
-CONFIG_HWMON=y
-# CONFIG_HWMON_VID is not set
-# CONFIG_SENSORS_AD7414 is not set
-# CONFIG_SENSORS_AD7418 is not set
-# CONFIG_SENSORS_ADM1021 is not set
-# CONFIG_SENSORS_ADM1025 is not set
-# CONFIG_SENSORS_ADM1026 is not set
-# CONFIG_SENSORS_ADM1029 is not set
-# CONFIG_SENSORS_ADM1031 is not set
-# CONFIG_SENSORS_ADM9240 is not set
-# CONFIG_SENSORS_ADT7462 is not set
-# CONFIG_SENSORS_ADT7470 is not set
-# CONFIG_SENSORS_ADT7473 is not set
-# CONFIG_SENSORS_ATXP1 is not set
-# CONFIG_SENSORS_DS1621 is not set
-# CONFIG_SENSORS_I5K_AMB is not set
-# CONFIG_SENSORS_F71805F is not set
-# CONFIG_SENSORS_F71882FG is not set
-# CONFIG_SENSORS_F75375S is not set
-# CONFIG_SENSORS_GL518SM is not set
-# CONFIG_SENSORS_GL520SM is not set
-# CONFIG_SENSORS_IT87 is not set
-# CONFIG_SENSORS_LM63 is not set
-# CONFIG_SENSORS_LM75 is not set
-# CONFIG_SENSORS_LM77 is not set
-# CONFIG_SENSORS_LM78 is not set
-# CONFIG_SENSORS_LM80 is not set
-# CONFIG_SENSORS_LM83 is not set
-# CONFIG_SENSORS_LM85 is not set
-# CONFIG_SENSORS_LM87 is not set
-# CONFIG_SENSORS_LM90 is not set
-# CONFIG_SENSORS_LM92 is not set
-# CONFIG_SENSORS_LM93 is not set
-# CONFIG_SENSORS_LTC4245 is not set
-# CONFIG_SENSORS_MAX1619 is not set
-# CONFIG_SENSORS_MAX6650 is not set
-# CONFIG_SENSORS_PC87360 is not set
-# CONFIG_SENSORS_PC87427 is not set
-# CONFIG_SENSORS_SIS5595 is not set
-# CONFIG_SENSORS_DME1737 is not set
-# CONFIG_SENSORS_SMSC47M1 is not set
-# CONFIG_SENSORS_SMSC47M192 is not set
-# CONFIG_SENSORS_SMSC47B397 is not set
-# CONFIG_SENSORS_ADS7828 is not set
-# CONFIG_SENSORS_THMC50 is not set
-# CONFIG_SENSORS_VIA686A is not set
-# CONFIG_SENSORS_VT1211 is not set
-# CONFIG_SENSORS_VT8231 is not set
-# CONFIG_SENSORS_W83781D is not set
-# CONFIG_SENSORS_W83791D is not set
-# CONFIG_SENSORS_W83792D is not set
-# CONFIG_SENSORS_W83793 is not set
-# CONFIG_SENSORS_W83L785TS is not set
-# CONFIG_SENSORS_W83L786NG is not set
-# CONFIG_SENSORS_W83627HF is not set
-# CONFIG_SENSORS_W83627EHF is not set
-# CONFIG_SENSORS_LIS3LV02D is not set
-# CONFIG_HWMON_DEBUG_CHIP is not set
-CONFIG_THERMAL=m
-# CONFIG_THERMAL_HWMON is not set
-# CONFIG_WATCHDOG is not set
-CONFIG_SSB_POSSIBLE=y
-
-#
-# Sonics Silicon Backplane
-#
-# CONFIG_SSB is not set
-
-#
-# Multifunction device drivers
-#
-# CONFIG_MFD_CORE is not set
-# CONFIG_MFD_SM501 is not set
-# CONFIG_HTC_PASIC3 is not set
-# CONFIG_MFD_TMIO is not set
-# CONFIG_MFD_WM8400 is not set
-# CONFIG_MFD_WM8350_I2C is not set
-# CONFIG_MFD_PCF50633 is not set
-# CONFIG_REGULATOR is not set
-
-#
-# Multimedia devices
-#
-
-#
-# Multimedia core support
-#
-# CONFIG_VIDEO_DEV is not set
-# CONFIG_DVB_CORE is not set
-# CONFIG_VIDEO_MEDIA is not set
-
-#
-# Multimedia drivers
-#
-CONFIG_DAB=y
-# CONFIG_USB_DABUSB is not set
-
-#
-# Graphics support
-#
-CONFIG_AGP=m
 CONFIG_DRM=m
-CONFIG_DRM_TDFX=m
+CONFIG_DRM_MGA=m
 CONFIG_DRM_R128=m
 CONFIG_DRM_RADEON=m
-CONFIG_DRM_MGA=m
 CONFIG_DRM_SIS=m
-# CONFIG_DRM_VIA is not set
-# CONFIG_DRM_SAVAGE is not set
-# CONFIG_VGASTATE is not set
-# CONFIG_VIDEO_OUTPUT_CONTROL is not set
-# CONFIG_FB is not set
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
-#
-# Display device support
-#
-# CONFIG_DISPLAY_SUPPORT is not set
-
-#
-# Console display driver support
-#
-CONFIG_VGA_CONSOLE=y
-# CONFIG_VGACON_SOFT_SCROLLBACK is not set
-CONFIG_DUMMY_CONSOLE=y
-# CONFIG_SOUND is not set
-CONFIG_HID_SUPPORT=y
-CONFIG_HID=y
-# CONFIG_HID_DEBUG is not set
-# CONFIG_HIDRAW is not set
-
-#
-# USB Input Devices
-#
-CONFIG_USB_HID=y
-# CONFIG_HID_PID is not set
-# CONFIG_USB_HIDDEV is not set
-
-#
-# Special HID drivers
-#
-CONFIG_HID_COMPAT=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_EZKEY=y
+CONFIG_DRM_TDFX=m
+CONFIG_DUMMY=m
+CONFIG_E1000=y
+CONFIG_E100=m
+CONFIG_EFI_PARTITION=y
+CONFIG_EFI_RTC=y
+CONFIG_EFI_VARS=y
+CONFIG_EXPERIMENTAL=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+CONFIG_EXT3_FS=y
+CONFIG_FORCE_CPEI_RETARGET=y
+CONFIG_FUSION_CTL=y
+CONFIG_FUSION_FC=y
+CONFIG_FUSION_SPI=y
+CONFIG_FUSION=y
+CONFIG_GAMEPORT=m
 CONFIG_HID_GYRATION=y
-CONFIG_HID_LOGITECH=y
-# CONFIG_LOGITECH_FF is not set
-# CONFIG_LOGIRUMBLEPAD2_FF is not set
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
 CONFIG_HID_NTRIG=y
 CONFIG_HID_PANTHERLORD=y
-# CONFIG_PANTHERLORD_FF is not set
 CONFIG_HID_PETALYNX=y
 CONFIG_HID_SAMSUNG=y
 CONFIG_HID_SONY=y
 CONFIG_HID_SUNPLUS=y
-# CONFIG_GREENASIA_FF is not set
 CONFIG_HID_TOPSEED=y
-# CONFIG_THRUSTMASTER_FF is not set
-# CONFIG_ZEROPLUS_FF is not set
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_ARCH_HAS_HCD=y
-CONFIG_USB_ARCH_HAS_OHCI=y
-CONFIG_USB_ARCH_HAS_EHCI=y
-CONFIG_USB=y
-# CONFIG_USB_DEBUG is not set
-# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
-
-#
-# Miscellaneous USB options
-#
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_DEVICE_CLASS=y
-# CONFIG_USB_DYNAMIC_MINORS is not set
-# CONFIG_USB_SUSPEND is not set
-# CONFIG_USB_OTG is not set
-# CONFIG_USB_MON is not set
-# CONFIG_USB_WUSB is not set
-# CONFIG_USB_WUSB_CBAF is not set
-
-#
-# USB Host Controller Drivers
-#
-# CONFIG_USB_C67X00_HCD is not set
-CONFIG_USB_EHCI_HCD=m
-# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
-# CONFIG_USB_EHCI_TT_NEWSCHED is not set
-# CONFIG_USB_OXU210HP_HCD is not set
-# CONFIG_USB_ISP116X_HCD is not set
-# CONFIG_USB_ISP1760_HCD is not set
-CONFIG_USB_OHCI_HCD=m
-# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
-# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
-CONFIG_USB_OHCI_LITTLE_ENDIAN=y
-CONFIG_USB_UHCI_HCD=y
-# CONFIG_USB_SL811_HCD is not set
-# CONFIG_USB_R8A66597_HCD is not set
-# CONFIG_USB_WHCI_HCD is not set
-# CONFIG_USB_HWA_HCD is not set
-
-#
-# USB Device Class drivers
-#
-# CONFIG_USB_ACM is not set
-# CONFIG_USB_PRINTER is not set
-# CONFIG_USB_WDM is not set
-# CONFIG_USB_TMC is not set
-
-#
-# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
-#
-
-#
-# see USB_STORAGE Help for more information
-#
-CONFIG_USB_STORAGE=m
-# CONFIG_USB_STORAGE_DEBUG is not set
-# CONFIG_USB_STORAGE_DATAFAB is not set
-# CONFIG_USB_STORAGE_FREECOM is not set
-# CONFIG_USB_STORAGE_ISD200 is not set
-# CONFIG_USB_STORAGE_USBAT is not set
-# CONFIG_USB_STORAGE_SDDR09 is not set
-# CONFIG_USB_STORAGE_SDDR55 is not set
-# CONFIG_USB_STORAGE_JUMPSHOT is not set
-# CONFIG_USB_STORAGE_ALAUDA is not set
-# CONFIG_USB_STORAGE_ONETOUCH is not set
-# CONFIG_USB_STORAGE_KARMA is not set
-# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
-# CONFIG_USB_LIBUSUAL is not set
-
-#
-# USB Imaging devices
-#
-# CONFIG_USB_MDC800 is not set
-# CONFIG_USB_MICROTEK is not set
-
-#
-# USB port drivers
-#
-# CONFIG_USB_SERIAL is not set
-
-#
-# USB Miscellaneous drivers
-#
-# CONFIG_USB_EMI62 is not set
-# CONFIG_USB_EMI26 is not set
-# CONFIG_USB_ADUTUX is not set
-# CONFIG_USB_SEVSEG is not set
-# CONFIG_USB_RIO500 is not set
-# CONFIG_USB_LEGOTOWER is not set
-# CONFIG_USB_LCD is not set
-# CONFIG_USB_BERRY_CHARGE is not set
-# CONFIG_USB_LED is not set
-# CONFIG_USB_CYPRESS_CY7C63 is not set
-# CONFIG_USB_CYTHERM is not set
-# CONFIG_USB_PHIDGET is not set
-# CONFIG_USB_IDMOUSE is not set
-# CONFIG_USB_FTDI_ELAN is not set
-# CONFIG_USB_APPLEDISPLAY is not set
-# CONFIG_USB_SISUSBVGA is not set
-# CONFIG_USB_LD is not set
-# CONFIG_USB_TRANCEVIBRATOR is not set
-# CONFIG_USB_IOWARRIOR is not set
-# CONFIG_USB_TEST is not set
-# CONFIG_USB_ISIGHTFW is not set
-# CONFIG_USB_VST is not set
-# CONFIG_USB_GADGET is not set
-
-#
-# OTG and related infrastructure
-#
-# CONFIG_UWB is not set
-# CONFIG_MMC is not set
-# CONFIG_MEMSTICK is not set
-# CONFIG_NEW_LEDS is not set
-# CONFIG_ACCESSIBILITY is not set
-# CONFIG_INFINIBAND is not set
-# CONFIG_RTC_CLASS is not set
-# CONFIG_DMADEVICES is not set
-# CONFIG_UIO is not set
-CONFIG_XEN_BALLOON=y
-CONFIG_XEN_SCRUB_PAGES=y
-CONFIG_XENFS=y
-CONFIG_XEN_COMPAT_XENFS=y
-# CONFIG_STAGING is not set
-# CONFIG_MSPEC is not set
-
-#
-# File systems
-#
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT2_FS_POSIX_ACL=y
-CONFIG_EXT2_FS_SECURITY=y
-# CONFIG_EXT2_FS_XIP is not set
-CONFIG_EXT3_FS=y
-CONFIG_EXT3_FS_XATTR=y
-CONFIG_EXT3_FS_POSIX_ACL=y
-CONFIG_EXT3_FS_SECURITY=y
-# CONFIG_EXT4_FS is not set
-CONFIG_JBD=y
-CONFIG_FS_MBCACHE=y
-CONFIG_REISERFS_FS=y
-# CONFIG_REISERFS_CHECK is not set
-# CONFIG_REISERFS_PROC_INFO is not set
-CONFIG_REISERFS_FS_XATTR=y
-CONFIG_REISERFS_FS_POSIX_ACL=y
-CONFIG_REISERFS_FS_SECURITY=y
-# CONFIG_JFS_FS is not set
-CONFIG_FS_POSIX_ACL=y
-CONFIG_FILE_LOCKING=y
-CONFIG_XFS_FS=y
-# CONFIG_XFS_QUOTA is not set
-# CONFIG_XFS_POSIX_ACL is not set
-# CONFIG_XFS_RT is not set
-# CONFIG_XFS_DEBUG is not set
-# CONFIG_GFS2_FS is not set
-# CONFIG_OCFS2_FS is not set
-# CONFIG_BTRFS_FS is not set
-CONFIG_DNOTIFY=y
+CONFIG_HOTPLUG_CPU=y
+CONFIG_HOTPLUG_PCI_ACPI=m
+CONFIG_HOTPLUG_PCI=m
+CONFIG_HPET=y
+CONFIG_HUGETLBFS=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_IA64_CYCLONE=y
+CONFIG_IA64_GRANULE_16MB=y
+CONFIG_IA64_MCA_RECOVERY=y
+CONFIG_IA64_PALINFO=y
+CONFIG_IA64_XEN_GUEST=y
+CONFIG_IDE=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_IKCONFIG=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET=y
 CONFIG_INOTIFY=y
-CONFIG_INOTIFY_USER=y
-# CONFIG_QUOTA is not set
-CONFIG_AUTOFS_FS=y
-CONFIG_AUTOFS4_FS=y
-# CONFIG_FUSE_FS is not set
-
-#
-# CD-ROM/DVD Filesystems
-#
+CONFIG_IP_MULTICAST=y
+# CONFIG_IPV6 is not set
 CONFIG_ISO9660_FS=m
 CONFIG_JOLIET=y
-# CONFIG_ZISOFS is not set
-CONFIG_UDF_FS=m
-CONFIG_UDF_NLS=y
-
-#
-# DOS/FAT/NT Filesystems
-#
-CONFIG_FAT_FS=y
-# CONFIG_MSDOS_FS is not set
-CONFIG_VFAT_FS=y
-CONFIG_FAT_DEFAULT_CODEPAGE=437
-CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-CONFIG_NTFS_FS=m
-# CONFIG_NTFS_DEBUG is not set
-# CONFIG_NTFS_RW is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_KCORE=y
-CONFIG_PROC_SYSCTL=y
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_SYSFS=y
-CONFIG_TMPFS=y
-# CONFIG_TMPFS_POSIX_ACL is not set
-CONFIG_HUGETLBFS=y
-CONFIG_HUGETLB_PAGE=y
-# CONFIG_CONFIGFS_FS is not set
-CONFIG_MISC_FILESYSTEMS=y
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-# CONFIG_CRAMFS is not set
-# CONFIG_SQUASHFS is not set
-# CONFIG_VXFS_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_OMFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_ROMFS_FS is not set
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_KEXEC=y
+CONFIG_LOG_BUF_SHIFT=20
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MCKINLEY=y
+CONFIG_MD_LINEAR=m
+CONFIG_MD_MULTIPATH=m
+CONFIG_MD_RAID0=m
+CONFIG_MD_RAID1=m
+CONFIG_MD=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_NETCONSOLE=y
+CONFIG_NETDEVICES=y
+CONFIG_NET_ETHERNET=y
+CONFIG_NET_PCI=y
+CONFIG_NET_TULIP=y
+CONFIG_NFSD=m
+CONFIG_NFSD_V4=y
 CONFIG_NFS_FS=m
 CONFIG_NFS_V3=y
-# CONFIG_NFS_V3_ACL is not set
 CONFIG_NFS_V4=y
-CONFIG_NFSD=m
-CONFIG_NFSD_V3=y
-# CONFIG_NFSD_V3_ACL is not set
-CONFIG_NFSD_V4=y
-CONFIG_LOCKD=m
-CONFIG_LOCKD_V4=y
-CONFIG_EXPORTFS=m
-CONFIG_NFS_COMMON=y
-CONFIG_SUNRPC=m
-CONFIG_SUNRPC_GSS=m
-# CONFIG_SUNRPC_REGISTER_V4 is not set
-CONFIG_RPCSEC_GSS_KRB5=m
-# CONFIG_RPCSEC_GSS_SPKM3 is not set
-CONFIG_SMB_FS=m
-CONFIG_SMB_NLS_DEFAULT=y
-CONFIG_SMB_NLS_REMOTE="cp437"
-CONFIG_CIFS=m
-# CONFIG_CIFS_STATS is not set
-# CONFIG_CIFS_WEAK_PW_HASH is not set
-# CONFIG_CIFS_XATTR is not set
-# CONFIG_CIFS_DEBUG2 is not set
-# CONFIG_CIFS_EXPERIMENTAL is not set
-# CONFIG_NCP_FS is not set
-# CONFIG_CODA_FS is not set
-# CONFIG_AFS_FS is not set
-
-#
-# Partition Types
-#
-CONFIG_PARTITION_ADVANCED=y
-# CONFIG_ACORN_PARTITION is not set
-# CONFIG_OSF_PARTITION is not set
-# CONFIG_AMIGA_PARTITION is not set
-# CONFIG_ATARI_PARTITION is not set
-# CONFIG_MAC_PARTITION is not set
-CONFIG_MSDOS_PARTITION=y
-# CONFIG_BSD_DISKLABEL is not set
-# CONFIG_MINIX_SUBPARTITION is not set
-# CONFIG_SOLARIS_X86_PARTITION is not set
-# CONFIG_UNIXWARE_DISKLABEL is not set
-# CONFIG_LDM_PARTITION is not set
-CONFIG_SGI_PARTITION=y
-# CONFIG_ULTRIX_PARTITION is not set
-# CONFIG_SUN_PARTITION is not set
-# CONFIG_KARMA_PARTITION is not set
-CONFIG_EFI_PARTITION=y
-# CONFIG_SYSV68_PARTITION is not set
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_1250=m
+CONFIG_NLS_CODEPAGE_1251=m
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_737=m
 CONFIG_NLS_CODEPAGE_775=m
@@ -1384,15 +131,14 @@ CONFIG_NLS_CODEPAGE_864=m
 CONFIG_NLS_CODEPAGE_865=m
 CONFIG_NLS_CODEPAGE_866=m
 CONFIG_NLS_CODEPAGE_869=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_CODEPAGE_950=m
+CONFIG_NLS_CODEPAGE_874=m
 CONFIG_NLS_CODEPAGE_932=m
+CONFIG_NLS_CODEPAGE_936=m
 CONFIG_NLS_CODEPAGE_949=m
-CONFIG_NLS_CODEPAGE_874=m
-CONFIG_NLS_ISO8859_8=m
-CONFIG_NLS_CODEPAGE_1250=m
-CONFIG_NLS_CODEPAGE_1251=m
-# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_CODEPAGE_950=m
+CONFIG_NLS_ISO8859_13=m
+CONFIG_NLS_ISO8859_14=m
+CONFIG_NLS_ISO8859_15=m
 CONFIG_NLS_ISO8859_1=y
 CONFIG_NLS_ISO8859_2=m
 CONFIG_NLS_ISO8859_3=m
@@ -1400,200 +146,54 @@ CONFIG_NLS_ISO8859_4=m
 CONFIG_NLS_ISO8859_5=m
 CONFIG_NLS_ISO8859_6=m
 CONFIG_NLS_ISO8859_7=m
+CONFIG_NLS_ISO8859_8=m
 CONFIG_NLS_ISO8859_9=m
-CONFIG_NLS_ISO8859_13=m
-CONFIG_NLS_ISO8859_14=m
-CONFIG_NLS_ISO8859_15=m
 CONFIG_NLS_KOI8_R=m
 CONFIG_NLS_KOI8_U=m
 CONFIG_NLS_UTF8=m
-# CONFIG_DLM is not set
-
-#
-# Kernel hacking
-#
-# CONFIG_PRINTK_TIME is not set
-CONFIG_ENABLE_WARN_DEPRECATED=y
-CONFIG_ENABLE_MUST_CHECK=y
-CONFIG_FRAME_WARN=2048
-CONFIG_MAGIC_SYSRQ=y
-# CONFIG_UNUSED_SYMBOLS is not set
-# CONFIG_DEBUG_FS is not set
-# CONFIG_HEADERS_CHECK is not set
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DEBUG_SHIRQ is not set
-CONFIG_DETECT_SOFTLOCKUP=y
-# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
-CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
-CONFIG_SCHED_DEBUG=y
-# CONFIG_SCHEDSTATS is not set
-# CONFIG_TIMER_STATS is not set
-# CONFIG_DEBUG_OBJECTS is not set
-# CONFIG_SLUB_DEBUG_ON is not set
-# CONFIG_SLUB_STATS is not set
-# CONFIG_DEBUG_RT_MUTEXES is not set
-# CONFIG_RT_MUTEX_TESTER is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-CONFIG_DEBUG_MUTEXES=y
-# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-# CONFIG_DEBUG_KOBJECT is not set
-# CONFIG_DEBUG_INFO is not set
-# CONFIG_DEBUG_VM is not set
-# CONFIG_DEBUG_WRITECOUNT is not set
-CONFIG_DEBUG_MEMORY_INIT=y
-# CONFIG_DEBUG_LIST is not set
-# CONFIG_DEBUG_SG is not set
-# CONFIG_DEBUG_NOTIFIERS is not set
-# CONFIG_BOOT_PRINTK_DELAY is not set
-# CONFIG_RCU_TORTURE_TEST is not set
+CONFIG_NR_CPUS=16
+CONFIG_NTFS_FS=m
+CONFIG_PACKET=y
+CONFIG_PARAVIRT_GUEST=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_PERFMON=y
+CONFIG_PERMIT_BSP_REMOVE=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_PROC_KCORE=y
+CONFIG_RAW_DRIVER=m
 # CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_BACKTRACE_SELF_TEST is not set
-# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
-# CONFIG_FAULT_INJECTION is not set
-# CONFIG_SYSCTL_SYSCALL_CHECK is not set
-
-#
-# Tracers
-#
-# CONFIG_SCHED_TRACER is not set
-# CONFIG_CONTEXT_SWITCH_TRACER is not set
-# CONFIG_BOOT_TRACER is not set
-# CONFIG_TRACE_BRANCH_PROFILING is not set
-# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
-# CONFIG_SAMPLES is not set
-CONFIG_IA64_GRANULE_16MB=y
-# CONFIG_IA64_GRANULE_64MB is not set
-# CONFIG_IA64_PRINT_HAZARDS is not set
-# CONFIG_DISABLE_VHPT is not set
-# CONFIG_IA64_DEBUG_CMPXCHG is not set
-# CONFIG_IA64_DEBUG_IRQ is not set
-
-#
-# Security options
-#
-# CONFIG_KEYS is not set
-# CONFIG_SECURITY is not set
-# CONFIG_SECURITYFS is not set
-# CONFIG_SECURITY_FILE_CAPABILITIES is not set
-CONFIG_CRYPTO=y
-
-#
-# Crypto core or helper
-#
-# CONFIG_CRYPTO_FIPS is not set
-CONFIG_CRYPTO_ALGAPI=y
-CONFIG_CRYPTO_ALGAPI2=y
-CONFIG_CRYPTO_AEAD2=y
-CONFIG_CRYPTO_BLKCIPHER=m
-CONFIG_CRYPTO_BLKCIPHER2=y
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_HASH2=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_MANAGER=m
-CONFIG_CRYPTO_MANAGER2=y
-# CONFIG_CRYPTO_GF128MUL is not set
-# CONFIG_CRYPTO_NULL is not set
-# CONFIG_CRYPTO_CRYPTD is not set
-# CONFIG_CRYPTO_AUTHENC is not set
-# CONFIG_CRYPTO_TEST is not set
-
-#
-# Authenticated Encryption with Associated Data
-#
-# CONFIG_CRYPTO_CCM is not set
-# CONFIG_CRYPTO_GCM is not set
-# CONFIG_CRYPTO_SEQIV is not set
-
-#
-# Block modes
-#
-CONFIG_CRYPTO_CBC=m
-# CONFIG_CRYPTO_CTR is not set
-# CONFIG_CRYPTO_CTS is not set
-CONFIG_CRYPTO_ECB=m
-# CONFIG_CRYPTO_LRW is not set
-CONFIG_CRYPTO_PCBC=m
-# CONFIG_CRYPTO_XTS is not set
-
-#
-# Hash modes
-#
-# CONFIG_CRYPTO_HMAC is not set
-# CONFIG_CRYPTO_XCBC is not set
-
-#
-# Digest
-#
-# CONFIG_CRYPTO_CRC32C is not set
-# CONFIG_CRYPTO_MD4 is not set
-CONFIG_CRYPTO_MD5=y
-# CONFIG_CRYPTO_MICHAEL_MIC is not set
-# CONFIG_CRYPTO_RMD128 is not set
-# CONFIG_CRYPTO_RMD160 is not set
-# CONFIG_CRYPTO_RMD256 is not set
-# CONFIG_CRYPTO_RMD320 is not set
-# CONFIG_CRYPTO_SHA1 is not set
-# CONFIG_CRYPTO_SHA256 is not set
-# CONFIG_CRYPTO_SHA512 is not set
-# CONFIG_CRYPTO_TGR192 is not set
-# CONFIG_CRYPTO_WP512 is not set
-
-#
-# Ciphers
-#
-# CONFIG_CRYPTO_AES is not set
-# CONFIG_CRYPTO_ANUBIS is not set
-# CONFIG_CRYPTO_ARC4 is not set
-# CONFIG_CRYPTO_BLOWFISH is not set
-# CONFIG_CRYPTO_CAMELLIA is not set
-# CONFIG_CRYPTO_CAST5 is not set
-# CONFIG_CRYPTO_CAST6 is not set
-CONFIG_CRYPTO_DES=m
-# CONFIG_CRYPTO_FCRYPT is not set
-# CONFIG_CRYPTO_KHAZAD is not set
-# CONFIG_CRYPTO_SALSA20 is not set
-# CONFIG_CRYPTO_SEED is not set
-# CONFIG_CRYPTO_SERPENT is not set
-# CONFIG_CRYPTO_TEA is not set
-# CONFIG_CRYPTO_TWOFISH is not set
-
-#
-# Compression
-#
-# CONFIG_CRYPTO_DEFLATE is not set
-# CONFIG_CRYPTO_LZO is not set
-
-#
-# Random Number Generation
-#
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRYPTO_HW=y
-# CONFIG_CRYPTO_DEV_HIFN_795X is not set
-CONFIG_HAVE_KVM=y
-CONFIG_VIRTUALIZATION=y
-# CONFIG_KVM is not set
-# CONFIG_VIRTIO_PCI is not set
-# CONFIG_VIRTIO_BALLOON is not set
-
-#
-# Library routines
-#
-CONFIG_BITREVERSE=y
-CONFIG_GENERIC_FIND_LAST_BIT=y
-# CONFIG_CRC_CCITT is not set
-# CONFIG_CRC16 is not set
-# CONFIG_CRC_T10DIF is not set
-CONFIG_CRC_ITU_T=m
-CONFIG_CRC32=y
-# CONFIG_CRC7 is not set
-# CONFIG_LIBCRC32C is not set
-CONFIG_PLIST=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HAS_DMA=y
-CONFIG_GENERIC_HARDIRQS=y
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_GENERIC_PENDING_IRQ=y
-CONFIG_IRQ_PER_CPU=y
-# CONFIG_IOMMU_API is not set
+CONFIG_REISERFS_FS_POSIX_ACL=y
+CONFIG_REISERFS_FS_SECURITY=y
+CONFIG_REISERFS_FS_XATTR=y
+CONFIG_REISERFS_FS=y
+CONFIG_SCSI_QLOGIC_1280=y
+CONFIG_SCSI_SYM53C8XX_2=y
+CONFIG_SCSI=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_NR_UARTS=6
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_NONSTANDARD=y
+# CONFIG_SERIO_SERPORT is not set
+CONFIG_SGI_PARTITION=y
+CONFIG_SMB_FS=m
+CONFIG_SMB_NLS_DEFAULT=y
+CONFIG_SMP=y
+CONFIG_SYN_COOKIES=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_SYSVIPC=y
+CONFIG_TIGON3=y
+CONFIG_TMPFS=y
+CONFIG_TULIP=m
+CONFIG_UDF_FS=m
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_UNIX=y
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_EHCI_HCD=m
+CONFIG_USB_OHCI_HCD=m
+CONFIG_USB_STORAGE=m
+CONFIG_USB_UHCI_HCD=y
+CONFIG_USB=y
+CONFIG_VFAT_FS=y
+CONFIG_XFS_FS=y
diff --git a/arch/ia64/configs/zx1_defconfig b/arch/ia64/configs/zx1_defconfig
index 3cec65b534c2..de0b68e0d48e 100644
--- a/arch/ia64/configs/zx1_defconfig
+++ b/arch/ia64/configs/zx1_defconfig
@@ -1,1460 +1,85 @@
-#
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.21-rc3
-# Thu Mar  8 11:04:20 2007
-#
-CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-
-#
-# Code maturity level options
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_LOCK_KERNEL=y
-CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
-CONFIG_LOCALVERSION=""
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-# CONFIG_IPC_NS is not set
-CONFIG_SYSVIPC_SYSCTL=y
-# CONFIG_POSIX_MQUEUE is not set
-CONFIG_BSD_PROCESS_ACCT=y
-# CONFIG_BSD_PROCESS_ACCT_V3 is not set
-# CONFIG_TASKSTATS is not set
-# CONFIG_UTS_NS is not set
-# CONFIG_AUDIT is not set
-# CONFIG_IKCONFIG is not set
-# CONFIG_CPUSETS is not set
-CONFIG_SYSFS_DEPRECATED=y
-# CONFIG_RELAY is not set
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_SYSCTL=y
-# CONFIG_EMBEDDED is not set
-CONFIG_SYSCTL_SYSCALL=y
-CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_ALL is not set
-# CONFIG_KALLSYMS_EXTRA_PASS is not set
-CONFIG_HOTPLUG=y
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_EPOLL=y
-CONFIG_SHMEM=y
-CONFIG_SLUB=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_RT_MUTEXES=y
-# CONFIG_TINY_SHMEM is not set
-CONFIG_BASE_SMALL=0
-# CONFIG_SLOB is not set
-
-#
-# Loadable module support
-#
-CONFIG_MODULES=y
-# CONFIG_MODULE_UNLOAD is not set
-# CONFIG_MODVERSIONS is not set
-# CONFIG_MODULE_SRCVERSION_ALL is not set
-# CONFIG_KMOD is not set
-CONFIG_STOP_MACHINE=y
-
-#
-# Block layer
-#
-CONFIG_BLOCK=y
-# CONFIG_BLK_DEV_IO_TRACE is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-CONFIG_DEFAULT_AS=y
-# CONFIG_DEFAULT_DEADLINE is not set
-# CONFIG_DEFAULT_CFQ is not set
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="anticipatory"
-
-#
-# Processor type and features
-#
-CONFIG_IA64=y
-CONFIG_64BIT=y
-CONFIG_ZONE_DMA=y
-CONFIG_MMU=y
-CONFIG_RWSEM_XCHGADD_ALGORITHM=y
-# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-CONFIG_GENERIC_FIND_NEXT_BIT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_GENERIC_TIME=y
-CONFIG_DMI=y
-CONFIG_EFI=y
-CONFIG_GENERIC_IOMAP=y
-CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
-CONFIG_AUDIT_ARCH=y
-# CONFIG_IA64_GENERIC is not set
-# CONFIG_IA64_DIG is not set
-CONFIG_IA64_HP_ZX1=y
-# CONFIG_IA64_HP_ZX1_SWIOTLB is not set
-# CONFIG_IA64_SGI_SN2 is not set
-# CONFIG_IA64_HP_SIM is not set
-# CONFIG_ITANIUM is not set
-CONFIG_MCKINLEY=y
-# CONFIG_IA64_PAGE_SIZE_4KB is not set
-# CONFIG_IA64_PAGE_SIZE_8KB is not set
-CONFIG_IA64_PAGE_SIZE_16KB=y
-# CONFIG_IA64_PAGE_SIZE_64KB is not set
-CONFIG_PGTABLE_3=y
-# CONFIG_PGTABLE_4 is not set
-# CONFIG_HZ_100 is not set
-CONFIG_HZ_250=y
-# CONFIG_HZ_300 is not set
-# CONFIG_HZ_1000 is not set
-CONFIG_HZ=250
-CONFIG_IA64_L1_CACHE_SHIFT=7
-# CONFIG_IA64_CYCLONE is not set
-CONFIG_IOSAPIC=y
-CONFIG_FORCE_MAX_ZONEORDER=17
-CONFIG_SMP=y
-CONFIG_NR_CPUS=16
-CONFIG_HOTPLUG_CPU=y
-CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
-# CONFIG_SCHED_SMT is not set
-# CONFIG_PERMIT_BSP_REMOVE is not set
-# CONFIG_PREEMPT is not set
-CONFIG_SELECT_MEMORY_MODEL=y
-CONFIG_FLATMEM_MANUAL=y
-# CONFIG_DISCONTIGMEM_MANUAL is not set
-# CONFIG_SPARSEMEM_MANUAL is not set
-CONFIG_FLATMEM=y
-CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
-CONFIG_SPLIT_PTLOCK_CPUS=4
-CONFIG_RESOURCES_64BIT=y
-CONFIG_ZONE_DMA_FLAG=1
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
-CONFIG_ARCH_FLATMEM_ENABLE=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_DISCONTIGMEM_DEFAULT=y
-CONFIG_ARCH_POPULATES_NODE_MAP=y
-CONFIG_VIRTUAL_MEM_MAP=y
-CONFIG_HOLES_IN_ZONE=y
-CONFIG_IA64_MCA_RECOVERY=y
-CONFIG_PERFMON=y
-CONFIG_IA64_PALINFO=y
-# CONFIG_IA64_ESI is not set
-# CONFIG_KEXEC is not set
-CONFIG_CRASH_DUMP=y
-
-#
-# Firmware Drivers
-#
-CONFIG_EFI_VARS=y
-CONFIG_EFI_PCDP=y
-CONFIG_BINFMT_ELF=y
-CONFIG_BINFMT_MISC=y
-
-#
-# Power management and ACPI
-#
-CONFIG_PM=y
-CONFIG_PM_LEGACY=y
-# CONFIG_PM_DEBUG is not set
-# CONFIG_PM_SYSFS_DEPRECATED is not set
-
-#
-# ACPI (Advanced Configuration and Power Interface) Support
-#
-CONFIG_ACPI=y
 CONFIG_ACPI_PROCFS=y
-CONFIG_ACPI_BUTTON=y
-CONFIG_ACPI_FAN=y
-# CONFIG_ACPI_DOCK is not set
-CONFIG_ACPI_PROCESSOR=y
-CONFIG_ACPI_HOTPLUG_CPU=y
-CONFIG_ACPI_THERMAL=y
-CONFIG_ACPI_BLACKLIST_YEAR=0
-# CONFIG_ACPI_DEBUG is not set
-CONFIG_ACPI_EC=y
-CONFIG_ACPI_POWER=y
-CONFIG_ACPI_SYSTEM=y
-CONFIG_ACPI_CONTAINER=y
-
-#
-# CPU Frequency scaling
-#
-# CONFIG_CPU_FREQ is not set
-
-#
-# Bus options (PCI, PCMCIA)
-#
-CONFIG_PCI=y
-CONFIG_PCI_DOMAINS=y
-# CONFIG_PCIEPORTBUS is not set
-# CONFIG_PCI_MSI is not set
-# CONFIG_PCI_DEBUG is not set
-
-#
-# PCI Hotplug Support
-#
-CONFIG_HOTPLUG_PCI=y
-# CONFIG_HOTPLUG_PCI_FAKE is not set
-CONFIG_HOTPLUG_PCI_ACPI=y
-# CONFIG_HOTPLUG_PCI_ACPI_IBM is not set
-# CONFIG_HOTPLUG_PCI_CPCI is not set
-# CONFIG_HOTPLUG_PCI_SHPC is not set
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
-# CONFIG_PCCARD is not set
-
-#
-# Networking
-#
-CONFIG_NET=y
-
-#
-# Networking options
-#
-# CONFIG_NETDEBUG is not set
-CONFIG_PACKET=y
-# CONFIG_PACKET_MMAP is not set
-CONFIG_UNIX=y
-CONFIG_XFRM=y
-# CONFIG_XFRM_USER is not set
-# CONFIG_XFRM_SUB_POLICY is not set
-# CONFIG_XFRM_MIGRATE is not set
-# CONFIG_NET_KEY is not set
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_FIB_HASH=y
-# CONFIG_IP_PNP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_IP_MROUTE is not set
-# CONFIG_ARPD is not set
-# CONFIG_SYN_COOKIES is not set
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_XFRM_TUNNEL is not set
-# CONFIG_INET_TUNNEL is not set
-CONFIG_INET_XFRM_MODE_TRANSPORT=y
-CONFIG_INET_XFRM_MODE_TUNNEL=y
-CONFIG_INET_XFRM_MODE_BEET=y
-CONFIG_INET_DIAG=y
-CONFIG_INET_TCP_DIAG=y
-# CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TCP_CONG_CUBIC=y
-CONFIG_DEFAULT_TCP_CONG="cubic"
-# CONFIG_TCP_MD5SIG is not set
-
-#
-# IP: Virtual Server Configuration
-#
-# CONFIG_IP_VS is not set
-# CONFIG_IPV6 is not set
-# CONFIG_INET6_XFRM_TUNNEL is not set
-# CONFIG_INET6_TUNNEL is not set
-# CONFIG_NETWORK_SECMARK is not set
-CONFIG_NETFILTER=y
-# CONFIG_NETFILTER_DEBUG is not set
-
-#
-# Core Netfilter Configuration
-#
-# CONFIG_NETFILTER_NETLINK is not set
-# CONFIG_NF_CONNTRACK_ENABLED is not set
-# CONFIG_NETFILTER_XTABLES is not set
-
-#
-# IP: Netfilter Configuration
-#
-# CONFIG_IP_NF_QUEUE is not set
-# CONFIG_IP_NF_IPTABLES is not set
-# CONFIG_IP_NF_ARPTABLES is not set
-
-#
-# DCCP Configuration (EXPERIMENTAL)
-#
-# CONFIG_IP_DCCP is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
-# CONFIG_IP_SCTP is not set
-
-#
-# TIPC Configuration (EXPERIMENTAL)
-#
-# CONFIG_TIPC is not set
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
-# CONFIG_NET_SCHED is not set
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_NET_TCPPROBE is not set
-# CONFIG_HAMRADIO is not set
-# CONFIG_IRDA is not set
-# CONFIG_BT is not set
-# CONFIG_IEEE80211 is not set
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-# CONFIG_FW_LOADER is not set
-# CONFIG_DEBUG_DRIVER is not set
-# CONFIG_DEBUG_DEVRES is not set
-# CONFIG_SYS_HYPERVISOR is not set
-
-#
-# Connector - unified userspace <-> kernelspace linker
-#
-# CONFIG_CONNECTOR is not set
-
-#
-# Memory Technology Devices (MTD)
-#
-# CONFIG_MTD is not set
-
-#
-# Parallel port support
-#
-# CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-CONFIG_PNP=y
-# CONFIG_PNP_DEBUG is not set
-
-#
-# Protocols
-#
-CONFIG_PNPACPI=y
-
-#
-# Block devices
-#
-# CONFIG_BLK_CPQ_DA is not set
-# CONFIG_BLK_CPQ_CISS_DA is not set
-# CONFIG_BLK_DEV_DAC960 is not set
-# CONFIG_BLK_DEV_UMEM is not set
-# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_AGP_HP_ZX1=y
+CONFIG_AGP=y
+CONFIG_AUTOFS_FS=y
+CONFIG_BINFMT_MISC=y
+CONFIG_BLK_DEV_CMD64X=y
+CONFIG_BLK_DEV_GENERIC=y
+CONFIG_BLK_DEV_IDECD=y
+CONFIG_BLK_DEV_INITRD=y
 CONFIG_BLK_DEV_LOOP=y
-# CONFIG_BLK_DEV_CRYPTOLOOP is not set
-# CONFIG_BLK_DEV_NBD is not set
-# CONFIG_BLK_DEV_SX8 is not set
-# CONFIG_BLK_DEV_UB is not set
 CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=4096
-CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
-# CONFIG_CDROM_PKTCDVD is not set
-# CONFIG_ATA_OVER_ETH is not set
-
-#
-# Misc devices
-#
-# CONFIG_SGI_IOC4 is not set
-# CONFIG_TIFM_CORE is not set
-
-#
-# ATA/ATAPI/MFM/RLL support
-#
-CONFIG_IDE=y
-CONFIG_IDE_MAX_HWIFS=4
-CONFIG_BLK_DEV_IDE=y
-
-#
-# Please see Documentation/ide.txt for help/info on IDE drives
-#
-# CONFIG_BLK_DEV_IDE_SATA is not set
-CONFIG_BLK_DEV_IDEDISK=y
-# CONFIG_IDEDISK_MULTI_MODE is not set
-CONFIG_BLK_DEV_IDECD=y
-# CONFIG_BLK_DEV_IDETAPE is not set
-# CONFIG_BLK_DEV_IDEFLOPPY is not set
-# CONFIG_BLK_DEV_IDESCSI is not set
-# CONFIG_BLK_DEV_IDEACPI is not set
-# CONFIG_IDE_TASK_IOCTL is not set
-
-#
-# IDE chipset support/bugfixes
-#
-# CONFIG_IDE_GENERIC is not set
-# CONFIG_BLK_DEV_IDEPNP is not set
-CONFIG_BLK_DEV_IDEPCI=y
-CONFIG_IDEPCI_SHARE_IRQ=y
-# CONFIG_BLK_DEV_OFFBOARD is not set
-CONFIG_BLK_DEV_GENERIC=y
-# CONFIG_BLK_DEV_OPTI621 is not set
-CONFIG_BLK_DEV_IDEDMA_PCI=y
-# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
-# CONFIG_IDEDMA_PCI_AUTO is not set
-# CONFIG_BLK_DEV_AEC62XX is not set
-# CONFIG_BLK_DEV_ALI15X3 is not set
-# CONFIG_BLK_DEV_AMD74XX is not set
-CONFIG_BLK_DEV_CMD64X=y
-# CONFIG_BLK_DEV_TRIFLEX is not set
-# CONFIG_BLK_DEV_CY82C693 is not set
-# CONFIG_BLK_DEV_CS5520 is not set
-# CONFIG_BLK_DEV_CS5530 is not set
-# CONFIG_BLK_DEV_HPT34X is not set
-# CONFIG_BLK_DEV_HPT366 is not set
-# CONFIG_BLK_DEV_JMICRON is not set
-# CONFIG_BLK_DEV_SC1200 is not set
-# CONFIG_BLK_DEV_PIIX is not set
-# CONFIG_BLK_DEV_IT8213 is not set
-# CONFIG_BLK_DEV_IT821X is not set
-# CONFIG_BLK_DEV_NS87415 is not set
-# CONFIG_BLK_DEV_PDC202XX_OLD is not set
-# CONFIG_BLK_DEV_PDC202XX_NEW is not set
-# CONFIG_BLK_DEV_SVWKS is not set
-# CONFIG_BLK_DEV_SIIMAGE is not set
-# CONFIG_BLK_DEV_SLC90E66 is not set
-# CONFIG_BLK_DEV_TRM290 is not set
-# CONFIG_BLK_DEV_VIA82CXXX is not set
-# CONFIG_BLK_DEV_TC86C001 is not set
-# CONFIG_IDE_ARM is not set
-CONFIG_BLK_DEV_IDEDMA=y
-# CONFIG_IDEDMA_IVB is not set
-# CONFIG_IDEDMA_AUTO is not set
-# CONFIG_BLK_DEV_HD is not set
-
-#
-# SCSI device support
-#
-# CONFIG_RAID_ATTRS is not set
-CONFIG_SCSI=y
-# CONFIG_SCSI_TGT is not set
-CONFIG_SCSI_NETLINK=y
-CONFIG_SCSI_PROC_FS=y
-
-#
-# SCSI support type (disk, tape, CD-ROM)
-#
 CONFIG_BLK_DEV_SD=y
-CONFIG_CHR_DEV_ST=y
-CONFIG_CHR_DEV_OSST=y
-CONFIG_BLK_DEV_SR=y
 CONFIG_BLK_DEV_SR_VENDOR=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_CHR_DEV_OSST=y
 CONFIG_CHR_DEV_SG=y
-# CONFIG_CHR_DEV_SCH is not set
-
-#
-# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
-#
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_SCSI_CONSTANTS=y
-CONFIG_SCSI_LOGGING=y
-# CONFIG_SCSI_SCAN_ASYNC is not set
-
-#
-# SCSI Transports
-#
-CONFIG_SCSI_SPI_ATTRS=y
-CONFIG_SCSI_FC_ATTRS=y
-# CONFIG_SCSI_ISCSI_ATTRS is not set
-# CONFIG_SCSI_SAS_ATTRS is not set
-# CONFIG_SCSI_SAS_LIBSAS is not set
-
-#
-# SCSI low-level drivers
-#
-# CONFIG_ISCSI_TCP is not set
-# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
-# CONFIG_SCSI_3W_9XXX is not set
-# CONFIG_SCSI_ACARD is not set
-# CONFIG_SCSI_AACRAID is not set
-# CONFIG_SCSI_AIC7XXX is not set
-# CONFIG_SCSI_AIC7XXX_OLD is not set
-# CONFIG_SCSI_AIC79XX is not set
-# CONFIG_SCSI_AIC94XX is not set
-# CONFIG_SCSI_ARCMSR is not set
-# CONFIG_MEGARAID_NEWGEN is not set
-# CONFIG_MEGARAID_LEGACY is not set
-# CONFIG_MEGARAID_SAS is not set
-# CONFIG_SCSI_HPTIOP is not set
-# CONFIG_SCSI_DMX3191D is not set
-# CONFIG_SCSI_FUTURE_DOMAIN is not set
-# CONFIG_SCSI_IPS is not set
-# CONFIG_SCSI_INITIO is not set
-# CONFIG_SCSI_INIA100 is not set
-# CONFIG_SCSI_STEX is not set
-CONFIG_SCSI_SYM53C8XX_2=y
-CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1
-CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16
-CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64
-CONFIG_SCSI_SYM53C8XX_MMIO=y
-CONFIG_SCSI_QLOGIC_1280=y
-# CONFIG_SCSI_QLA_FC is not set
-# CONFIG_SCSI_QLA_ISCSI is not set
-# CONFIG_SCSI_LPFC is not set
-# CONFIG_SCSI_DC395x is not set
-# CONFIG_SCSI_DC390T is not set
-# CONFIG_SCSI_DEBUG is not set
-# CONFIG_SCSI_SRP is not set
-
-#
-# Serial ATA (prod) and Parallel ATA (experimental) drivers
-#
-# CONFIG_ATA is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
-# CONFIG_MD is not set
-
-#
-# Fusion MPT device support
-#
-CONFIG_FUSION=y
-CONFIG_FUSION_SPI=y
-CONFIG_FUSION_FC=y
-# CONFIG_FUSION_SAS is not set
-CONFIG_FUSION_MAX_SGE=128
-CONFIG_FUSION_CTL=m
-
-#
-# IEEE 1394 (FireWire) support
-#
-# CONFIG_IEEE1394 is not set
-
-#
-# I2O device support
-#
-# CONFIG_I2O is not set
-
-#
-# Network device support
-#
-CONFIG_NETDEVICES=y
+CONFIG_CHR_DEV_ST=y
+CONFIG_CRASH_DUMP=y
+CONFIG_CRYPTO_ECB=m
+CONFIG_CRYPTO_PCBC=m
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_MUTEXES=y
+CONFIG_DRM_RADEON=y
+CONFIG_DRM=y
 CONFIG_DUMMY=y
-# CONFIG_BONDING is not set
-# CONFIG_EQUALIZER is not set
-# CONFIG_TUN is not set
-# CONFIG_NET_SB1000 is not set
-
-#
-# ARCnet devices
-#
-# CONFIG_ARCNET is not set
-
-#
-# PHY device support
-#
-# CONFIG_PHYLIB is not set
-
-#
-# Ethernet (10 or 100Mbit)
-#
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
-# CONFIG_HAPPYMEAL is not set
-# CONFIG_SUNGEM is not set
-# CONFIG_CASSINI is not set
-# CONFIG_NET_VENDOR_3COM is not set
-
-#
-# Tulip family network device support
-#
-CONFIG_NET_TULIP=y
-# CONFIG_DE2104X is not set
-CONFIG_TULIP=y
-CONFIG_TULIP_MWI=y
-CONFIG_TULIP_MMIO=y
-CONFIG_TULIP_NAPI=y
-CONFIG_TULIP_NAPI_HW_MITIGATION=y
-# CONFIG_DE4X5 is not set
-# CONFIG_WINBOND_840 is not set
-# CONFIG_DM9102 is not set
-# CONFIG_ULI526X is not set
-# CONFIG_HP100 is not set
-CONFIG_NET_PCI=y
-# CONFIG_PCNET32 is not set
-# CONFIG_AMD8111_ETH is not set
-# CONFIG_ADAPTEC_STARFIRE is not set
-# CONFIG_B44 is not set
-# CONFIG_FORCEDETH is not set
-# CONFIG_DGRS is not set
-# CONFIG_EEPRO100 is not set
-CONFIG_E100=y
-# CONFIG_FEALNX is not set
-# CONFIG_NATSEMI is not set
-# CONFIG_NE2K_PCI is not set
-# CONFIG_8139CP is not set
-# CONFIG_8139TOO is not set
-# CONFIG_SIS900 is not set
-# CONFIG_EPIC100 is not set
-# CONFIG_SUNDANCE is not set
-# CONFIG_VIA_RHINE is not set
-# CONFIG_SC92031 is not set
-
-#
-# Ethernet (1000 Mbit)
-#
-# CONFIG_ACENIC is not set
-# CONFIG_DL2K is not set
 CONFIG_E1000=y
-# CONFIG_E1000_NAPI is not set
-# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set
-# CONFIG_NS83820 is not set
-# CONFIG_HAMACHI is not set
-# CONFIG_YELLOWFIN is not set
-# CONFIG_R8169 is not set
-# CONFIG_SIS190 is not set
-# CONFIG_SKGE is not set
-# CONFIG_SKY2 is not set
-# CONFIG_SK98LIN is not set
-# CONFIG_VIA_VELOCITY is not set
-CONFIG_TIGON3=y
-# CONFIG_BNX2 is not set
-# CONFIG_QLA3XXX is not set
-# CONFIG_ATL1 is not set
-
-#
-# Ethernet (10000 Mbit)
-#
-# CONFIG_CHELSIO_T1 is not set
-# CONFIG_CHELSIO_T3 is not set
-# CONFIG_IXGB is not set
-# CONFIG_S2IO is not set
-# CONFIG_MYRI10GE is not set
-# CONFIG_NETXEN_NIC is not set
-
-#
-# Token Ring devices
-#
-# CONFIG_TR is not set
-
-#
-# Wireless LAN (non-hamradio)
-#
-# CONFIG_NET_RADIO is not set
-
-#
-# Wan interfaces
-#
-# CONFIG_WAN is not set
-# CONFIG_FDDI is not set
-# CONFIG_HIPPI is not set
-# CONFIG_PPP is not set
-# CONFIG_SLIP is not set
-# CONFIG_NET_FC is not set
-# CONFIG_SHAPER is not set
-# CONFIG_NETCONSOLE is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
-
-#
-# ISDN subsystem
-#
-# CONFIG_ISDN is not set
-
-#
-# Telephony Support
-#
-# CONFIG_PHONE is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-# CONFIG_INPUT_FF_MEMLESS is not set
-
-#
-# Userland interfaces
-#
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-CONFIG_INPUT_JOYDEV=y
-# CONFIG_INPUT_TSDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_EVBUG is not set
-
-#
-# Input Device Drivers
-#
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TOUCHSCREEN is not set
-# CONFIG_INPUT_MISC is not set
-
-#
-# Hardware I/O ports
-#
-CONFIG_SERIO=y
-# CONFIG_SERIO_I8042 is not set
-# CONFIG_SERIO_SERPORT is not set
-# CONFIG_SERIO_PCIPS2 is not set
-# CONFIG_SERIO_RAW is not set
-# CONFIG_GAMEPORT is not set
-
-#
-# Character devices
-#
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
-# CONFIG_SERIAL_NONSTANDARD is not set
-
-#
-# Serial drivers
-#
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_PCI=y
-CONFIG_SERIAL_8250_PNP=y
-CONFIG_SERIAL_8250_NR_UARTS=8
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-# CONFIG_SERIAL_8250_DETECT_IRQ is not set
-# CONFIG_SERIAL_8250_RSA is not set
-
-#
-# Non-8250 serial port support
-#
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-# CONFIG_SERIAL_JSM is not set
-CONFIG_UNIX98_PTYS=y
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
-# CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-# CONFIG_WATCHDOG is not set
-# CONFIG_HW_RANDOM is not set
+CONFIG_E100=y
+CONFIG_EFI_PARTITION=y
 CONFIG_EFI_RTC=y
-# CONFIG_DTLK is not set
-# CONFIG_R3964 is not set
-# CONFIG_APPLICOM is not set
-CONFIG_AGP=y
-CONFIG_AGP_HP_ZX1=y
-CONFIG_DRM=y
-# CONFIG_DRM_TDFX is not set
-# CONFIG_DRM_R128 is not set
-CONFIG_DRM_RADEON=y
-# CONFIG_DRM_MGA is not set
-# CONFIG_DRM_SIS is not set
-# CONFIG_DRM_VIA is not set
-# CONFIG_DRM_SAVAGE is not set
-# CONFIG_RAW_DRIVER is not set
-# CONFIG_HPET is not set
-# CONFIG_HANGCHECK_TIMER is not set
-
-#
-# TPM devices
-#
-# CONFIG_TCG_TPM is not set
-
-#
-# I2C support
-#
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-
-#
-# I2C Algorithms
-#
-CONFIG_I2C_ALGOBIT=y
-CONFIG_I2C_ALGOPCF=y
-# CONFIG_I2C_ALGOPCA is not set
-
-#
-# I2C Hardware Bus support
-#
-# CONFIG_I2C_ALI1535 is not set
-# CONFIG_I2C_ALI1563 is not set
-# CONFIG_I2C_ALI15X3 is not set
-# CONFIG_I2C_AMD756 is not set
-# CONFIG_I2C_AMD8111 is not set
-# CONFIG_I2C_I801 is not set
-# CONFIG_I2C_I810 is not set
-# CONFIG_I2C_PIIX4 is not set
-# CONFIG_I2C_NFORCE2 is not set
-# CONFIG_I2C_OCORES is not set
-# CONFIG_I2C_PARPORT_LIGHT is not set
-# CONFIG_I2C_PASEMI is not set
-# CONFIG_I2C_PROSAVAGE is not set
-# CONFIG_I2C_SAVAGE4 is not set
-# CONFIG_I2C_SIS5595 is not set
-# CONFIG_I2C_SIS630 is not set
-# CONFIG_I2C_SIS96X is not set
-# CONFIG_I2C_STUB is not set
-# CONFIG_I2C_VIA is not set
-# CONFIG_I2C_VIAPRO is not set
-# CONFIG_I2C_VOODOO3 is not set
-# CONFIG_I2C_PCA_ISA is not set
-
-#
-# Miscellaneous I2C Chip support
-#
-# CONFIG_SENSORS_DS1337 is not set
-# CONFIG_SENSORS_DS1374 is not set
-# CONFIG_EEPROM_LEGACY is not set
-# CONFIG_SENSORS_PCF8574 is not set
-# CONFIG_SENSORS_PCA9539 is not set
-# CONFIG_SENSORS_PCF8591 is not set
-# CONFIG_SENSORS_MAX6875 is not set
-# CONFIG_I2C_DEBUG_CORE is not set
-# CONFIG_I2C_DEBUG_ALGO is not set
-# CONFIG_I2C_DEBUG_BUS is not set
-# CONFIG_I2C_DEBUG_CHIP is not set
-
-#
-# SPI support
-#
-# CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
-
-#
-# Dallas's 1-wire bus
-#
-# CONFIG_W1 is not set
-
-#
-# Hardware Monitoring support
-#
-# CONFIG_HWMON is not set
-# CONFIG_HWMON_VID is not set
-
-#
-# Multifunction device drivers
-#
-# CONFIG_MFD_SM501 is not set
-
-#
-# Multimedia devices
-#
-CONFIG_VIDEO_DEV=y
-CONFIG_VIDEO_V4L1=y
-CONFIG_VIDEO_V4L1_COMPAT=y
-CONFIG_VIDEO_V4L2=y
-
-#
-# Video Capture Adapters
-#
-
-#
-# Video Capture Adapters
-#
-# CONFIG_VIDEO_ADV_DEBUG is not set
-CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
-# CONFIG_VIDEO_VIVI is not set
-# CONFIG_VIDEO_BT848 is not set
-# CONFIG_VIDEO_CPIA is not set
-# CONFIG_VIDEO_CPIA2 is not set
-# CONFIG_VIDEO_SAA5246A is not set
-# CONFIG_VIDEO_SAA5249 is not set
-# CONFIG_TUNER_3036 is not set
-# CONFIG_VIDEO_STRADIS is not set
-# CONFIG_VIDEO_ZORAN is not set
-# CONFIG_VIDEO_SAA7134 is not set
-# CONFIG_VIDEO_MXB is not set
-# CONFIG_VIDEO_DPC is not set
-# CONFIG_VIDEO_HEXIUM_ORION is not set
-# CONFIG_VIDEO_HEXIUM_GEMINI is not set
-# CONFIG_VIDEO_CX88 is not set
-# CONFIG_VIDEO_CAFE_CCIC is not set
-
-#
-# V4L USB devices
-#
-# CONFIG_VIDEO_PVRUSB2 is not set
-# CONFIG_VIDEO_EM28XX is not set
-# CONFIG_VIDEO_USBVISION is not set
-# CONFIG_USB_VICAM is not set
-# CONFIG_USB_IBMCAM is not set
-# CONFIG_USB_KONICAWC is not set
-# CONFIG_USB_QUICKCAM_MESSENGER is not set
-# CONFIG_USB_ET61X251 is not set
-# CONFIG_VIDEO_OVCAMCHIP is not set
-# CONFIG_USB_W9968CF is not set
-# CONFIG_USB_OV511 is not set
-# CONFIG_USB_SE401 is not set
-# CONFIG_USB_SN9C102 is not set
-# CONFIG_USB_STV680 is not set
-# CONFIG_USB_ZC0301 is not set
-# CONFIG_USB_PWC is not set
-
-#
-# Radio Adapters
-#
-# CONFIG_RADIO_GEMTEK_PCI is not set
-# CONFIG_RADIO_MAXIRADIO is not set
-# CONFIG_RADIO_MAESTRO is not set
-# CONFIG_USB_DSBR is not set
-
-#
-# Digital Video Broadcasting Devices
-#
-# CONFIG_DVB is not set
-# CONFIG_USB_DABUSB is not set
-
-#
-# Graphics support
-#
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_LCD_CLASS_DEVICE=m
-CONFIG_FB=y
-# CONFIG_FIRMWARE_EDID is not set
-CONFIG_FB_DDC=y
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-# CONFIG_FB_SVGALIB is not set
-# CONFIG_FB_MACMODES is not set
-CONFIG_FB_BACKLIGHT=y
-CONFIG_FB_MODE_HELPERS=y
-# CONFIG_FB_TILEBLITTING is not set
-
-#
-# Frambuffer hardware drivers
-#
-# CONFIG_FB_CIRRUS is not set
-# CONFIG_FB_PM2 is not set
-# CONFIG_FB_CYBER2000 is not set
-# CONFIG_FB_ASILIANT is not set
-# CONFIG_FB_IMSTT is not set
-# CONFIG_FB_S1D13XXX is not set
-# CONFIG_FB_NVIDIA is not set
-# CONFIG_FB_RIVA is not set
-# CONFIG_FB_MATROX is not set
-CONFIG_FB_RADEON=y
-CONFIG_FB_RADEON_I2C=y
-CONFIG_FB_RADEON_BACKLIGHT=y
-CONFIG_FB_RADEON_DEBUG=y
-# CONFIG_FB_ATY128 is not set
-# CONFIG_FB_ATY is not set
-# CONFIG_FB_S3 is not set
-# CONFIG_FB_SAVAGE is not set
-# CONFIG_FB_SIS is not set
-# CONFIG_FB_NEOMAGIC is not set
-# CONFIG_FB_KYRO is not set
-# CONFIG_FB_3DFX is not set
-# CONFIG_FB_VOODOO1 is not set
-# CONFIG_FB_TRIDENT is not set
-# CONFIG_FB_VIRTUAL is not set
-
-#
-# Console display driver support
-#
-CONFIG_VGA_CONSOLE=y
-# CONFIG_VGACON_SOFT_SCROLLBACK is not set
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
-# CONFIG_FONTS is not set
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-
-#
-# Logo configuration
-#
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_LOGO_LINUX_CLUT224=y
-
-#
-# Sound
-#
-CONFIG_SOUND=y
-
-#
-# Advanced Linux Sound Architecture
-#
-CONFIG_SND=y
-CONFIG_SND_TIMER=y
-CONFIG_SND_PCM=y
-CONFIG_SND_HWDEP=y
-CONFIG_SND_RAWMIDI=y
-CONFIG_SND_SEQUENCER=y
-# CONFIG_SND_SEQ_DUMMY is not set
-CONFIG_SND_OSSEMUL=y
-CONFIG_SND_MIXER_OSS=y
-CONFIG_SND_PCM_OSS=y
-CONFIG_SND_PCM_OSS_PLUGINS=y
-CONFIG_SND_SEQUENCER_OSS=y
-# CONFIG_SND_DYNAMIC_MINORS is not set
-CONFIG_SND_SUPPORT_OLD_API=y
-CONFIG_SND_VERBOSE_PROCFS=y
-# CONFIG_SND_VERBOSE_PRINTK is not set
-# CONFIG_SND_DEBUG is not set
-
-#
-# Generic devices
-#
-CONFIG_SND_MPU401_UART=y
-CONFIG_SND_OPL3_LIB=y
-CONFIG_SND_AC97_CODEC=y
-# CONFIG_SND_DUMMY is not set
-# CONFIG_SND_VIRMIDI is not set
-# CONFIG_SND_MTPAV is not set
-# CONFIG_SND_SERIAL_U16550 is not set
-# CONFIG_SND_MPU401 is not set
-
-#
-# PCI devices
-#
-# CONFIG_SND_AD1889 is not set
-# CONFIG_SND_ALS300 is not set
-# CONFIG_SND_ALI5451 is not set
-# CONFIG_SND_ATIIXP is not set
-# CONFIG_SND_ATIIXP_MODEM is not set
-# CONFIG_SND_AU8810 is not set
-# CONFIG_SND_AU8820 is not set
-# CONFIG_SND_AU8830 is not set
-# CONFIG_SND_AZT3328 is not set
-# CONFIG_SND_BT87X is not set
-# CONFIG_SND_CA0106 is not set
-# CONFIG_SND_CMIPCI is not set
-# CONFIG_SND_CS4281 is not set
-# CONFIG_SND_CS46XX is not set
-# CONFIG_SND_DARLA20 is not set
-# CONFIG_SND_GINA20 is not set
-# CONFIG_SND_LAYLA20 is not set
-# CONFIG_SND_DARLA24 is not set
-# CONFIG_SND_GINA24 is not set
-# CONFIG_SND_LAYLA24 is not set
-# CONFIG_SND_MONA is not set
-# CONFIG_SND_MIA is not set
-# CONFIG_SND_ECHO3G is not set
-# CONFIG_SND_INDIGO is not set
-# CONFIG_SND_INDIGOIO is not set
-# CONFIG_SND_INDIGODJ is not set
-# CONFIG_SND_EMU10K1 is not set
-# CONFIG_SND_EMU10K1X is not set
-# CONFIG_SND_ENS1370 is not set
-# CONFIG_SND_ENS1371 is not set
-# CONFIG_SND_ES1938 is not set
-# CONFIG_SND_ES1968 is not set
-CONFIG_SND_FM801=y
-# CONFIG_SND_FM801_TEA575X_BOOL is not set
-# CONFIG_SND_HDA_INTEL is not set
-# CONFIG_SND_HDSP is not set
-# CONFIG_SND_HDSPM is not set
-# CONFIG_SND_ICE1712 is not set
-# CONFIG_SND_ICE1724 is not set
-# CONFIG_SND_INTEL8X0 is not set
-# CONFIG_SND_INTEL8X0M is not set
-# CONFIG_SND_KORG1212 is not set
-# CONFIG_SND_MAESTRO3 is not set
-# CONFIG_SND_MIXART is not set
-# CONFIG_SND_NM256 is not set
-# CONFIG_SND_PCXHR is not set
-# CONFIG_SND_RIPTIDE is not set
-# CONFIG_SND_RME32 is not set
-# CONFIG_SND_RME96 is not set
-# CONFIG_SND_RME9652 is not set
-# CONFIG_SND_SONICVIBES is not set
-# CONFIG_SND_TRIDENT is not set
-# CONFIG_SND_VIA82XX is not set
-# CONFIG_SND_VIA82XX_MODEM is not set
-# CONFIG_SND_VX222 is not set
-# CONFIG_SND_YMFPCI is not set
-# CONFIG_SND_AC97_POWER_SAVE is not set
-
-#
-# USB devices
-#
-# CONFIG_SND_USB_AUDIO is not set
-
-#
-# SoC audio support
-#
-# CONFIG_SND_SOC is not set
-
-#
-# Open Sound System
-#
-# CONFIG_SOUND_PRIME is not set
-CONFIG_AC97_BUS=y
-
-#
-# HID Devices
-#
-CONFIG_HID=y
-# CONFIG_HID_DEBUG is not set
-
-#
-# USB support
-#
-CONFIG_USB_ARCH_HAS_HCD=y
-CONFIG_USB_ARCH_HAS_OHCI=y
-CONFIG_USB_ARCH_HAS_EHCI=y
-CONFIG_USB=y
-# CONFIG_USB_DEBUG is not set
-
-#
-# Miscellaneous USB options
-#
-# CONFIG_USB_DEVICEFS is not set
-# CONFIG_USB_DYNAMIC_MINORS is not set
-# CONFIG_USB_SUSPEND is not set
-# CONFIG_USB_OTG is not set
-
-#
-# USB Host Controller Drivers
-#
-CONFIG_USB_EHCI_HCD=y
-# CONFIG_USB_EHCI_SPLIT_ISO is not set
-# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
-# CONFIG_USB_EHCI_TT_NEWSCHED is not set
-# CONFIG_USB_EHCI_BIG_ENDIAN_MMIO is not set
-# CONFIG_USB_ISP116X_HCD is not set
-CONFIG_USB_OHCI_HCD=y
-# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
-# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
-CONFIG_USB_OHCI_LITTLE_ENDIAN=y
-CONFIG_USB_UHCI_HCD=y
-# CONFIG_USB_SL811_HCD is not set
-
-#
-# USB Device Class drivers
-#
-# CONFIG_USB_ACM is not set
-# CONFIG_USB_PRINTER is not set
-
-#
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
-#
-
-#
-# may also be needed; see USB_STORAGE Help for more information
-#
-CONFIG_USB_STORAGE=y
-# CONFIG_USB_STORAGE_DEBUG is not set
-# CONFIG_USB_STORAGE_DATAFAB is not set
-# CONFIG_USB_STORAGE_FREECOM is not set
-# CONFIG_USB_STORAGE_ISD200 is not set
-# CONFIG_USB_STORAGE_DPCM is not set
-# CONFIG_USB_STORAGE_USBAT is not set
-# CONFIG_USB_STORAGE_SDDR09 is not set
-# CONFIG_USB_STORAGE_SDDR55 is not set
-# CONFIG_USB_STORAGE_JUMPSHOT is not set
-# CONFIG_USB_STORAGE_ALAUDA is not set
-# CONFIG_USB_STORAGE_KARMA is not set
-# CONFIG_USB_LIBUSUAL is not set
-
-#
-# USB Input Devices
-#
-CONFIG_USB_HID=y
-# CONFIG_USB_HIDINPUT_POWERBOOK is not set
-# CONFIG_HID_FF is not set
-CONFIG_USB_HIDDEV=y
-# CONFIG_USB_AIPTEK is not set
-# CONFIG_USB_WACOM is not set
-# CONFIG_USB_ACECAD is not set
-# CONFIG_USB_KBTAB is not set
-# CONFIG_USB_POWERMATE is not set
-# CONFIG_USB_TOUCHSCREEN is not set
-# CONFIG_USB_YEALINK is not set
-# CONFIG_USB_XPAD is not set
-# CONFIG_USB_ATI_REMOTE is not set
-# CONFIG_USB_ATI_REMOTE2 is not set
-# CONFIG_USB_KEYSPAN_REMOTE is not set
-# CONFIG_USB_APPLETOUCH is not set
-# CONFIG_USB_GTCO is not set
-
-#
-# USB Imaging devices
-#
-# CONFIG_USB_MDC800 is not set
-# CONFIG_USB_MICROTEK is not set
-
-#
-# USB Network Adapters
-#
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_RTL8150 is not set
-# CONFIG_USB_USBNET_MII is not set
-# CONFIG_USB_USBNET is not set
-CONFIG_USB_MON=y
-
-#
-# USB port drivers
-#
-
-#
-# USB Serial Converter support
-#
-# CONFIG_USB_SERIAL is not set
-
-#
-# USB Miscellaneous drivers
-#
-# CONFIG_USB_EMI62 is not set
-# CONFIG_USB_EMI26 is not set
-# CONFIG_USB_ADUTUX is not set
-# CONFIG_USB_AUERSWALD is not set
-# CONFIG_USB_RIO500 is not set
-# CONFIG_USB_LEGOTOWER is not set
-# CONFIG_USB_LCD is not set
-# CONFIG_USB_BERRY_CHARGE is not set
-# CONFIG_USB_LED is not set
-# CONFIG_USB_CYPRESS_CY7C63 is not set
-# CONFIG_USB_CYTHERM is not set
-# CONFIG_USB_PHIDGET is not set
-# CONFIG_USB_IDMOUSE is not set
-# CONFIG_USB_FTDI_ELAN is not set
-# CONFIG_USB_APPLEDISPLAY is not set
-# CONFIG_USB_SISUSBVGA is not set
-# CONFIG_USB_LD is not set
-# CONFIG_USB_TRANCEVIBRATOR is not set
-# CONFIG_USB_IOWARRIOR is not set
-
-#
-# USB DSL modem support
-#
-
-#
-# USB Gadget Support
-#
-# CONFIG_USB_GADGET is not set
-
-#
-# MMC/SD Card support
-#
-# CONFIG_MMC is not set
-
-#
-# LED devices
-#
-# CONFIG_NEW_LEDS is not set
-
-#
-# LED drivers
-#
-
-#
-# LED Triggers
-#
-
-#
-# InfiniBand support
-#
-# CONFIG_INFINIBAND is not set
-
-#
-# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
-#
-
-#
-# Real Time Clock
-#
-# CONFIG_RTC_CLASS is not set
-
-#
-# DMA Engine support
-#
-# CONFIG_DMA_ENGINE is not set
-
-#
-# DMA Clients
-#
-
-#
-# DMA Devices
-#
-
-#
-# Auxiliary Display support
-#
-
-#
-# Virtualization
-#
-# CONFIG_MSPEC is not set
-
-#
-# File systems
-#
-CONFIG_EXT2_FS=y
+CONFIG_EFI_VARS=y
+CONFIG_EXPERIMENTAL=y
 CONFIG_EXT2_FS_XATTR=y
-# CONFIG_EXT2_FS_POSIX_ACL is not set
-# CONFIG_EXT2_FS_SECURITY is not set
-# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
-CONFIG_EXT3_FS_XATTR=y
-# CONFIG_EXT3_FS_POSIX_ACL is not set
-# CONFIG_EXT3_FS_SECURITY is not set
-# CONFIG_EXT4DEV_FS is not set
-CONFIG_JBD=y
-# CONFIG_JBD_DEBUG is not set
-CONFIG_FS_MBCACHE=y
-# CONFIG_REISERFS_FS is not set
-# CONFIG_JFS_FS is not set
-# CONFIG_FS_POSIX_ACL is not set
-# CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
-# CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
-# CONFIG_INOTIFY is not set
-# CONFIG_QUOTA is not set
-CONFIG_DNOTIFY=y
-CONFIG_AUTOFS_FS=y
-# CONFIG_AUTOFS4_FS is not set
-# CONFIG_FUSE_FS is not set
-
-#
-# CD-ROM/DVD Filesystems
-#
+CONFIG_FB_RADEON_DEBUG=y
+CONFIG_FB_RADEON=y
+CONFIG_FLATMEM_MANUAL=y
+CONFIG_FUSION_CTL=m
+CONFIG_FUSION_FC=y
+CONFIG_FUSION_SPI=y
+CONFIG_FUSION=y
+CONFIG_HOTPLUG_CPU=y
+CONFIG_HOTPLUG_PCI_ACPI=y
+CONFIG_HOTPLUG_PCI=y
+CONFIG_HUGETLBFS=y
+# CONFIG_HWMON is not set
+# CONFIG_HW_RANDOM is not set
+CONFIG_I2C_CHARDEV=y
+CONFIG_IA64_HP_ZX1=y
+CONFIG_IA64_MCA_RECOVERY=y
+CONFIG_IA64_PALINFO=y
+CONFIG_IA64_PRINT_HAZARDS=y
+CONFIG_IDE=y
+CONFIG_INET=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_INPUT_JOYDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_IP_MULTICAST=y
+# CONFIG_IPV6 is not set
 CONFIG_ISO9660_FS=y
 CONFIG_JOLIET=y
-# CONFIG_ZISOFS is not set
-CONFIG_UDF_FS=y
-CONFIG_UDF_NLS=y
-
-#
-# DOS/FAT/NT Filesystems
-#
-CONFIG_FAT_FS=y
+CONFIG_KPROBES=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+CONFIG_LOGO=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MCKINLEY=y
+CONFIG_MODULES=y
 CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_FAT_DEFAULT_CODEPAGE=437
-CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-# CONFIG_NTFS_FS is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_KCORE=y
-CONFIG_PROC_VMCORE=y
-CONFIG_PROC_SYSCTL=y
-CONFIG_SYSFS=y
-CONFIG_TMPFS=y
-# CONFIG_TMPFS_POSIX_ACL is not set
-CONFIG_HUGETLBFS=y
-CONFIG_HUGETLB_PAGE=y
-CONFIG_RAMFS=y
-# CONFIG_CONFIGFS_FS is not set
-
-#
-# Miscellaneous filesystems
-#
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-# CONFIG_CRAMFS is not set
-# CONFIG_VXFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
+CONFIG_NETDEVICES=y
+CONFIG_NET_ETHERNET=y
+CONFIG_NETFILTER=y
+CONFIG_NET_PCI=y
+CONFIG_NET_TULIP=y
+CONFIG_NFSD_V3=y
+CONFIG_NFSD=y
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
-# CONFIG_NFS_V3_ACL is not set
 CONFIG_NFS_V4=y
-# CONFIG_NFS_DIRECTIO is not set
-CONFIG_NFSD=y
-CONFIG_NFSD_V3=y
-# CONFIG_NFSD_V3_ACL is not set
-# CONFIG_NFSD_V4 is not set
-# CONFIG_NFSD_TCP is not set
-CONFIG_LOCKD=y
-CONFIG_LOCKD_V4=y
-CONFIG_EXPORTFS=y
-CONFIG_NFS_COMMON=y
-CONFIG_SUNRPC=y
-CONFIG_SUNRPC_GSS=y
-CONFIG_RPCSEC_GSS_KRB5=y
-# CONFIG_RPCSEC_GSS_SPKM3 is not set
-# CONFIG_SMB_FS is not set
-# CONFIG_CIFS is not set
-# CONFIG_NCP_FS is not set
-# CONFIG_CODA_FS is not set
-# CONFIG_AFS_FS is not set
-# CONFIG_9P_FS is not set
-
-#
-# Partition Types
-#
-CONFIG_PARTITION_ADVANCED=y
-# CONFIG_ACORN_PARTITION is not set
-# CONFIG_OSF_PARTITION is not set
-# CONFIG_AMIGA_PARTITION is not set
-# CONFIG_ATARI_PARTITION is not set
-# CONFIG_MAC_PARTITION is not set
-CONFIG_MSDOS_PARTITION=y
-# CONFIG_BSD_DISKLABEL is not set
-# CONFIG_MINIX_SUBPARTITION is not set
-# CONFIG_SOLARIS_X86_PARTITION is not set
-# CONFIG_UNIXWARE_DISKLABEL is not set
-# CONFIG_LDM_PARTITION is not set
-# CONFIG_SGI_PARTITION is not set
-# CONFIG_ULTRIX_PARTITION is not set
-# CONFIG_SUN_PARTITION is not set
-# CONFIG_KARMA_PARTITION is not set
-CONFIG_EFI_PARTITION=y
-
-#
-# Native Language Support
-#
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_1251=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_737=y
 CONFIG_NLS_CODEPAGE_775=y
@@ -1470,15 +95,14 @@ CONFIG_NLS_CODEPAGE_864=y
 CONFIG_NLS_CODEPAGE_865=y
 CONFIG_NLS_CODEPAGE_866=y
 CONFIG_NLS_CODEPAGE_869=y
-CONFIG_NLS_CODEPAGE_936=y
-CONFIG_NLS_CODEPAGE_950=y
+CONFIG_NLS_CODEPAGE_874=y
 CONFIG_NLS_CODEPAGE_932=y
+CONFIG_NLS_CODEPAGE_936=y
 CONFIG_NLS_CODEPAGE_949=y
-CONFIG_NLS_CODEPAGE_874=y
-CONFIG_NLS_ISO8859_8=y
-# CONFIG_NLS_CODEPAGE_1250 is not set
-CONFIG_NLS_CODEPAGE_1251=y
-# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_CODEPAGE_950=y
+CONFIG_NLS_ISO8859_13=y
+CONFIG_NLS_ISO8859_14=y
+CONFIG_NLS_ISO8859_15=y
 CONFIG_NLS_ISO8859_1=y
 CONFIG_NLS_ISO8859_2=y
 CONFIG_NLS_ISO8859_3=y
@@ -1486,125 +110,52 @@ CONFIG_NLS_ISO8859_4=y
 CONFIG_NLS_ISO8859_5=y
 CONFIG_NLS_ISO8859_6=y
 CONFIG_NLS_ISO8859_7=y
+CONFIG_NLS_ISO8859_8=y
 CONFIG_NLS_ISO8859_9=y
-CONFIG_NLS_ISO8859_13=y
-CONFIG_NLS_ISO8859_14=y
-CONFIG_NLS_ISO8859_15=y
 CONFIG_NLS_KOI8_R=y
 CONFIG_NLS_KOI8_U=y
 CONFIG_NLS_UTF8=y
-
-#
-# Distributed Lock Manager
-#
-# CONFIG_DLM is not set
-
-#
-# Library routines
-#
-CONFIG_BITREVERSE=y
-# CONFIG_CRC_CCITT is not set
-# CONFIG_CRC16 is not set
-CONFIG_CRC32=y
-# CONFIG_LIBCRC32C is not set
-CONFIG_PLIST=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_GENERIC_HARDIRQS=y
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_GENERIC_PENDING_IRQ=y
-CONFIG_IRQ_PER_CPU=y
-
-#
-# Instrumentation Support
-#
-# CONFIG_PROFILING is not set
-CONFIG_KPROBES=y
-
-#
-# Kernel hacking
-#
-# CONFIG_PRINTK_TIME is not set
-CONFIG_ENABLE_MUST_CHECK=y
-CONFIG_MAGIC_SYSRQ=y
-# CONFIG_UNUSED_SYMBOLS is not set
-# CONFIG_DEBUG_FS is not set
-# CONFIG_HEADERS_CHECK is not set
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DEBUG_SHIRQ is not set
-CONFIG_LOG_BUF_SHIFT=17
-CONFIG_DETECT_SOFTLOCKUP=y
-# CONFIG_SCHEDSTATS is not set
-# CONFIG_TIMER_STATS is not set
-# CONFIG_DEBUG_SLAB is not set
-# CONFIG_DEBUG_RT_MUTEXES is not set
-# CONFIG_RT_MUTEX_TESTER is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-CONFIG_DEBUG_MUTEXES=y
-# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-# CONFIG_DEBUG_KOBJECT is not set
-# CONFIG_DEBUG_INFO is not set
-# CONFIG_DEBUG_VM is not set
-# CONFIG_DEBUG_LIST is not set
-CONFIG_FORCED_INLINING=y
-# CONFIG_RCU_TORTURE_TEST is not set
-# CONFIG_LKDTM is not set
-# CONFIG_FAULT_INJECTION is not set
-CONFIG_IA64_GRANULE_16MB=y
-# CONFIG_IA64_GRANULE_64MB is not set
-CONFIG_IA64_PRINT_HAZARDS=y
-# CONFIG_DISABLE_VHPT is not set
-# CONFIG_IA64_DEBUG_CMPXCHG is not set
-# CONFIG_IA64_DEBUG_IRQ is not set
-CONFIG_SYSVIPC_COMPAT=y
-
-#
-# Security options
-#
-# CONFIG_KEYS is not set
-# CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
-CONFIG_CRYPTO=y
-CONFIG_CRYPTO_ALGAPI=y
-CONFIG_CRYPTO_BLKCIPHER=y
-CONFIG_CRYPTO_MANAGER=y
-# CONFIG_CRYPTO_HMAC is not set
-# CONFIG_CRYPTO_XCBC is not set
-# CONFIG_CRYPTO_NULL is not set
-# CONFIG_CRYPTO_MD4 is not set
-CONFIG_CRYPTO_MD5=y
-# CONFIG_CRYPTO_SHA1 is not set
-# CONFIG_CRYPTO_SHA256 is not set
-# CONFIG_CRYPTO_SHA512 is not set
-# CONFIG_CRYPTO_WP512 is not set
-# CONFIG_CRYPTO_TGR192 is not set
-# CONFIG_CRYPTO_GF128MUL is not set
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_CBC=y
-CONFIG_CRYPTO_PCBC=m
-# CONFIG_CRYPTO_LRW is not set
-CONFIG_CRYPTO_DES=y
-# CONFIG_CRYPTO_FCRYPT is not set
-# CONFIG_CRYPTO_BLOWFISH is not set
-# CONFIG_CRYPTO_TWOFISH is not set
-# CONFIG_CRYPTO_SERPENT is not set
-# CONFIG_CRYPTO_AES is not set
-# CONFIG_CRYPTO_CAST5 is not set
-# CONFIG_CRYPTO_CAST6 is not set
-# CONFIG_CRYPTO_TEA is not set
-# CONFIG_CRYPTO_ARC4 is not set
-# CONFIG_CRYPTO_KHAZAD is not set
-# CONFIG_CRYPTO_ANUBIS is not set
-# CONFIG_CRYPTO_DEFLATE is not set
-# CONFIG_CRYPTO_MICHAEL_MIC is not set
-# CONFIG_CRYPTO_CRC32C is not set
-# CONFIG_CRYPTO_CAMELLIA is not set
-# CONFIG_CRYPTO_TEST is not set
-
-#
-# Hardware crypto devices
-#
+CONFIG_NR_CPUS=16
+CONFIG_PACKET=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_PERFMON=y
+CONFIG_PROC_KCORE=y
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_LOGGING=y
+CONFIG_SCSI_MULTI_LUN=y
+CONFIG_SCSI_QLOGIC_1280=y
+CONFIG_SCSI_SYM53C8XX_2=y
+CONFIG_SCSI=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_NR_UARTS=8
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIO_I8042 is not set
+# CONFIG_SERIO_SERPORT is not set
+CONFIG_SMP=y
+CONFIG_SND_FM801=y
+CONFIG_SND_MIXER_OSS=y
+CONFIG_SND_PCM_OSS=y
+CONFIG_SND_SEQUENCER_OSS=y
+CONFIG_SND_SEQUENCER=y
+CONFIG_SND=y
+CONFIG_SOUND=y
+CONFIG_SYSVIPC=y
+CONFIG_TIGON3=y
+CONFIG_TMPFS=y
+CONFIG_TULIP_MMIO=y
+CONFIG_TULIP_MWI=y
+CONFIG_TULIP_NAPI_HW_MITIGATION=y
+CONFIG_TULIP_NAPI=y
+CONFIG_TULIP=y
+CONFIG_UDF_FS=y
+CONFIG_UNIX=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_HIDDEV=y
+CONFIG_USB_MON=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_UHCI_HCD=y
+CONFIG_USB=y
+CONFIG_VFAT_FS=y
diff --git a/arch/ia64/include/asm/page.h b/arch/ia64/include/asm/page.h
index 5f271bc712ee..41b6d31110fd 100644
--- a/arch/ia64/include/asm/page.h
+++ b/arch/ia64/include/asm/page.h
@@ -41,7 +41,7 @@
 #define PAGE_SIZE               (__IA64_UL_CONST(1) << PAGE_SHIFT)
 #define PAGE_MASK               (~(PAGE_SIZE - 1))
 
-#define PERCPU_PAGE_SHIFT       16      /* log2() of max. size of per-CPU area */
+#define PERCPU_PAGE_SHIFT       18      /* log2() of max. size of per-CPU area */
 #define PERCPU_PAGE_SIZE        (__IA64_UL_CONST(1) << PERCPU_PAGE_SHIFT)
 
 
diff --git a/arch/ia64/kernel/perfmon.c b/arch/ia64/kernel/perfmon.c
index ab985f785c14..744329072f33 100644
--- a/arch/ia64/kernel/perfmon.c
+++ b/arch/ia64/kernel/perfmon.c
@@ -1696,8 +1696,8 @@ pfm_poll(struct file *filp, poll_table * wait)
         return mask;
 }
 
-static int
-pfm_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
+static long
+pfm_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
 {
         DPRINT(("pfm_ioctl called\n"));
         return -EINVAL;
@@ -2174,15 +2174,15 @@ pfm_no_open(struct inode *irrelevant, struct file *dontcare)
 
 
 static const struct file_operations pfm_file_ops = {
-        .llseek   = no_llseek,
-        .read     = pfm_read,
-        .write    = pfm_write,
-        .poll     = pfm_poll,
-        .ioctl    = pfm_ioctl,
-        .open     = pfm_no_open,        /* special open code to disallow open via /proc */
-        .fasync   = pfm_fasync,
-        .release  = pfm_close,
-        .flush    = pfm_flush
+        .llseek         = no_llseek,
+        .read           = pfm_read,
+        .write          = pfm_write,
+        .poll           = pfm_poll,
+        .unlocked_ioctl = pfm_ioctl,
+        .open           = pfm_no_open,  /* special open code to disallow open via /proc */
+        .fasync         = pfm_fasync,
+        .release        = pfm_close,
+        .flush          = pfm_flush
 };
 
 static int
diff --git a/arch/ia64/kernel/vmlinux.lds.S b/arch/ia64/kernel/vmlinux.lds.S
index e07218a2577f..5a4d044dcb1c 100644
--- a/arch/ia64/kernel/vmlinux.lds.S
+++ b/arch/ia64/kernel/vmlinux.lds.S
@@ -6,204 +6,209 @@
 
 #include <asm-generic/vmlinux.lds.h>
 
-#define IVT_TEXT                                                        \
-                VMLINUX_SYMBOL(__start_ivt_text) = .;                   \
-                *(.text..ivt)                                           \
-                VMLINUX_SYMBOL(__end_ivt_text) = .;
-
 OUTPUT_FORMAT("elf64-ia64-little")
 OUTPUT_ARCH(ia64)
 ENTRY(phys_start)
 jiffies = jiffies_64;
+
 PHDRS {
-  code   PT_LOAD;
-  percpu PT_LOAD;
-  data   PT_LOAD;
-  note   PT_NOTE;
-  unwind 0x70000001; /* PT_IA_64_UNWIND, but ld doesn't match the name */
+        code   PT_LOAD;
+        percpu PT_LOAD;
+        data   PT_LOAD;
+        note   PT_NOTE;
+        unwind 0x70000001; /* PT_IA_64_UNWIND, but ld doesn't match the name */
 }
-SECTIONS
-{
-  /* unwind exit sections must be discarded before the rest of the
-     sections get included. */
-  /DISCARD/ : {
-        *(.IA_64.unwind.exit.text)
-        *(.IA_64.unwind_info.exit.text)
-        *(.comment)
-        *(.note)
-  }
-
-  v = PAGE_OFFSET;      /* this symbol is here to make debugging easier... */
-  phys_start = _start - LOAD_OFFSET;
-
-  code : { } :code
-  . = KERNEL_START;
-
-  _text = .;
-  _stext = .;
-
-  .text : AT(ADDR(.text) - LOAD_OFFSET)
-    {
-        IVT_TEXT
-        TEXT_TEXT
-        SCHED_TEXT
-        LOCK_TEXT
-        KPROBES_TEXT
-        *(.gnu.linkonce.t*)
-    }
-  .text2 : AT(ADDR(.text2) - LOAD_OFFSET)
-        { *(.text2) }
-#ifdef CONFIG_SMP
-  .text..lock : AT(ADDR(.text..lock) - LOAD_OFFSET)
-        { *(.text..lock) }
-#endif
-  _etext = .;
 
-  /* Read-only data */
+SECTIONS {
+        /*
+         * unwind exit sections must be discarded before
+         * the rest of the sections get included.
+         */
+        /DISCARD/ : {
+                *(.IA_64.unwind.exit.text)
+                *(.IA_64.unwind_info.exit.text)
+                *(.comment)
+                *(.note)
+        }
 
-  NOTES :code :note             /* put .notes in text and mark in PT_NOTE  */
-  code_continues : {} :code     /* switch back to regular program...  */
+        v = PAGE_OFFSET; /* this symbol is here to make debugging easier... */
+        phys_start = _start - LOAD_OFFSET;
+
+        code : {
+        } :code
+        . = KERNEL_START;
+
+        _text = .;
+        _stext = .;
+
+        .text : AT(ADDR(.text) - LOAD_OFFSET) {
+                __start_ivt_text = .;
+                *(.text..ivt)
+                __end_ivt_text = .;
+                TEXT_TEXT
+                SCHED_TEXT
+                LOCK_TEXT
+                KPROBES_TEXT
+                *(.gnu.linkonce.t*)
+        }
 
-  EXCEPTION_TABLE(16)
+        .text2 : AT(ADDR(.text2) - LOAD_OFFSET) {
+                *(.text2)
+        }
 
-  /* MCA table */
-  . = ALIGN(16);
-  __mca_table : AT(ADDR(__mca_table) - LOAD_OFFSET)
-        {
-          __start___mca_table = .;
-          *(__mca_table)
-          __stop___mca_table = .;
+#ifdef CONFIG_SMP
+        .text..lock : AT(ADDR(.text..lock) - LOAD_OFFSET) {
+                *(.text..lock)
+        }
+#endif
+        _etext = .;
+
+        /*
+         * Read-only data
+         */
+        NOTES :code :note       /* put .notes in text and mark in PT_NOTE  */
+        code_continues : {
+        } : code               /* switch back to regular program...  */
+
+        EXCEPTION_TABLE(16)
+
+        /* MCA table */
+        . = ALIGN(16);
+        __mca_table : AT(ADDR(__mca_table) - LOAD_OFFSET) {
+                __start___mca_table = .;
+                *(__mca_table)
+                __stop___mca_table = .;
         }
 
-  .data..patch.phys_stack_reg : AT(ADDR(.data..patch.phys_stack_reg) - LOAD_OFFSET)
-        {
-          __start___phys_stack_reg_patchlist = .;
-          *(.data..patch.phys_stack_reg)
-          __end___phys_stack_reg_patchlist = .;
+        .data..patch.phys_stack_reg : AT(ADDR(.data..patch.phys_stack_reg) - LOAD_OFFSET) {
+                __start___phys_stack_reg_patchlist = .;
+                *(.data..patch.phys_stack_reg)
+                __end___phys_stack_reg_patchlist = .;
         }
 
-  /* Global data */
-  _data = .;
+        /*
+         * Global data
+         */
+        _data = .;
 
-  /* Unwind info & table: */
-  . = ALIGN(8);
-  .IA_64.unwind_info : AT(ADDR(.IA_64.unwind_info) - LOAD_OFFSET)
-        { *(.IA_64.unwind_info*) }
-  .IA_64.unwind : AT(ADDR(.IA_64.unwind) - LOAD_OFFSET)
-        {
-          __start_unwind = .;
-          *(.IA_64.unwind*)
-          __end_unwind = .;
+        /* Unwind info & table: */
+        . = ALIGN(8);
+        .IA_64.unwind_info : AT(ADDR(.IA_64.unwind_info) - LOAD_OFFSET) {
+                *(.IA_64.unwind_info*)
+        }
+        .IA_64.unwind : AT(ADDR(.IA_64.unwind) - LOAD_OFFSET) {
+                __start_unwind = .;
+                *(.IA_64.unwind*)
+                __end_unwind = .;
         } :code :unwind
-  code_continues2 : {} : code
+        code_continues2 : {
+        } : code
 
-  RODATA
+        RODATA
 
-  .opd : AT(ADDR(.opd) - LOAD_OFFSET)
-        { *(.opd) }
-
-  /* Initialization code and data: */
+        .opd : AT(ADDR(.opd) - LOAD_OFFSET) {
+                *(.opd)
+        }
 
-  . = ALIGN(PAGE_SIZE);
-  __init_begin = .;
+        /*
+         * Initialization code and data:
+         */
+        . = ALIGN(PAGE_SIZE);
+        __init_begin = .;
 
-  INIT_TEXT_SECTION(PAGE_SIZE)
-  INIT_DATA_SECTION(16)
+        INIT_TEXT_SECTION(PAGE_SIZE)
+        INIT_DATA_SECTION(16)
 
-  .data..patch.vtop : AT(ADDR(.data..patch.vtop) - LOAD_OFFSET)
-        {
-          __start___vtop_patchlist = .;
-          *(.data..patch.vtop)
-          __end___vtop_patchlist = .;
+        .data..patch.vtop : AT(ADDR(.data..patch.vtop) - LOAD_OFFSET) {
+                __start___vtop_patchlist = .;
+                *(.data..patch.vtop)
+                __end___vtop_patchlist = .;
         }
 
-  .data..patch.rse : AT(ADDR(.data..patch.rse) - LOAD_OFFSET)
-        {
-          __start___rse_patchlist = .;
-          *(.data..patch.rse)
-          __end___rse_patchlist = .;
+        .data..patch.rse : AT(ADDR(.data..patch.rse) - LOAD_OFFSET) {
+                __start___rse_patchlist = .;
+                *(.data..patch.rse)
+                __end___rse_patchlist = .;
         }
 
-  .data..patch.mckinley_e9 : AT(ADDR(.data..patch.mckinley_e9) - LOAD_OFFSET)
-        {
-          __start___mckinley_e9_bundles = .;
-          *(.data..patch.mckinley_e9)
-          __end___mckinley_e9_bundles = .;
+        .data..patch.mckinley_e9 : AT(ADDR(.data..patch.mckinley_e9) - LOAD_OFFSET) {
+                __start___mckinley_e9_bundles = .;
+                *(.data..patch.mckinley_e9)
+                __end___mckinley_e9_bundles = .;
         }
 
 #if defined(CONFIG_PARAVIRT)
-  . = ALIGN(16);
-  .paravirt_bundles : AT(ADDR(.paravirt_bundles) - LOAD_OFFSET)
-        {
-          __start_paravirt_bundles = .;
-          *(.paravirt_bundles)
-          __stop_paravirt_bundles = .;
-        }
-  . = ALIGN(16);
-  .paravirt_insts : AT(ADDR(.paravirt_insts) - LOAD_OFFSET)
-        {
-          __start_paravirt_insts = .;
-          *(.paravirt_insts)
-          __stop_paravirt_insts = .;
-        }
-  . = ALIGN(16);
-  .paravirt_branches : AT(ADDR(.paravirt_branches) - LOAD_OFFSET)
-        {
-          __start_paravirt_branches = .;
-          *(.paravirt_branches)
-          __stop_paravirt_branches = .;
+        . = ALIGN(16);
+        .paravirt_bundles : AT(ADDR(.paravirt_bundles) - LOAD_OFFSET) {
+                __start_paravirt_bundles = .;
+                *(.paravirt_bundles)
+                __stop_paravirt_bundles = .;
+        }
+        . = ALIGN(16);
+        .paravirt_insts : AT(ADDR(.paravirt_insts) - LOAD_OFFSET) {
+                __start_paravirt_insts = .;
+                *(.paravirt_insts)
+                __stop_paravirt_insts = .;
+        }
+        . = ALIGN(16);
+        .paravirt_branches : AT(ADDR(.paravirt_branches) - LOAD_OFFSET) {
+                __start_paravirt_branches = .;
+                *(.paravirt_branches)
+                __stop_paravirt_branches = .;
         }
 #endif
 
 #if defined(CONFIG_IA64_GENERIC)
-  /* Machine Vector */
-  . = ALIGN(16);
-  .machvec : AT(ADDR(.machvec) - LOAD_OFFSET)
-        {
-          machvec_start = .;
-          *(.machvec)
-          machvec_end = .;
+        /* Machine Vector */
+        . = ALIGN(16);
+        .machvec : AT(ADDR(.machvec) - LOAD_OFFSET) {
+                machvec_start = .;
+                *(.machvec)
+                machvec_end = .;
         }
 #endif
 
 #ifdef  CONFIG_SMP
-  . = ALIGN(PERCPU_PAGE_SIZE);
-  __cpu0_per_cpu = .;
-  . = . + PERCPU_PAGE_SIZE;     /* cpu0 per-cpu space */
+        . = ALIGN(PERCPU_PAGE_SIZE);
+        __cpu0_per_cpu = .;
+        . = . + PERCPU_PAGE_SIZE;   /* cpu0 per-cpu space */
 #endif
 
-  . = ALIGN(PAGE_SIZE);
-  __init_end = .;
+        . = ALIGN(PAGE_SIZE);
+        __init_end = .;
 
-  .data..page_aligned : AT(ADDR(.data..page_aligned) - LOAD_OFFSET)
-        {
-        PAGE_ALIGNED_DATA(PAGE_SIZE)
-          . = ALIGN(PAGE_SIZE);
-          __start_gate_section = .;
-          *(.data..gate)
-          __stop_gate_section = .;
+        .data..page_aligned : AT(ADDR(.data..page_aligned) - LOAD_OFFSET) {
+                PAGE_ALIGNED_DATA(PAGE_SIZE)
+                . = ALIGN(PAGE_SIZE);
+                __start_gate_section = .;
+                *(.data..gate)
+                __stop_gate_section = .;
 #ifdef CONFIG_XEN
-          . = ALIGN(PAGE_SIZE);
-          __xen_start_gate_section = .;
-          *(.data..gate.xen)
-          __xen_stop_gate_section = .;
+                . = ALIGN(PAGE_SIZE);
+                __xen_start_gate_section = .;
+                *(.data..gate.xen)
+                __xen_stop_gate_section = .;
 #endif
         }
-  . = ALIGN(PAGE_SIZE);         /* make sure the gate page doesn't expose
-                                 * kernel data
-                                 */
-
-  /* Per-cpu data: */
-  . = ALIGN(PERCPU_PAGE_SIZE);
-  PERCPU_VADDR(PERCPU_ADDR, :percpu)
-  __phys_per_cpu_start = __per_cpu_load;
-  . = __phys_per_cpu_start + PERCPU_PAGE_SIZE;  /* ensure percpu data fits
-                                                 * into percpu page size
-                                                 */
-
-  data : { } :data
-  .data : AT(ADDR(.data) - LOAD_OFFSET)
-        {
+        /*
+         * make sure the gate page doesn't expose
+         * kernel data
+         */
+        . = ALIGN(PAGE_SIZE);
+
+        /* Per-cpu data: */
+        . = ALIGN(PERCPU_PAGE_SIZE);
+        PERCPU_VADDR(PERCPU_ADDR, :percpu)
+        __phys_per_cpu_start = __per_cpu_load;
+        /*
+         * ensure percpu data fits
+         * into percpu page size
+         */
+        . = __phys_per_cpu_start + PERCPU_PAGE_SIZE;
+
+        data : {
+        } :data
+        .data : AT(ADDR(.data) - LOAD_OFFSET) {
                 INIT_TASK_DATA(PAGE_SIZE)
                 CACHELINE_ALIGNED_DATA(SMP_CACHE_BYTES)
                 READ_MOSTLY_DATA(SMP_CACHE_BYTES)
@@ -213,26 +218,37 @@ SECTIONS
                 CONSTRUCTORS
         }
 
-  . = ALIGN(16);        /* gp must be 16-byte aligned for exc. table */
-  .got : AT(ADDR(.got) - LOAD_OFFSET)
-        { *(.got.plt) *(.got) }
-  __gp = ADDR(.got) + 0x200000;
-  /* We want the small data sections together, so single-instruction offsets
-     can access them all, and initialized data all before uninitialized, so
-     we can shorten the on-disk segment size.  */
-  .sdata : AT(ADDR(.sdata) - LOAD_OFFSET)
-        { *(.sdata) *(.sdata1) *(.srdata) }
-  _edata  =  .;
+        . = ALIGN(16);  /* gp must be 16-byte aligned for exc. table */
+        .got : AT(ADDR(.got) - LOAD_OFFSET) {
+                *(.got.plt)
+                *(.got)
+        }
+        __gp = ADDR(.got) + 0x200000;
+
+        /*
+         * We want the small data sections together,
+         * so single-instruction offsets can access
+         * them all, and initialized data all before
+         * uninitialized, so we can shorten the
+         * on-disk segment size.
+         */
+        .sdata : AT(ADDR(.sdata) - LOAD_OFFSET) {
+                *(.sdata)
+                *(.sdata1)
+                *(.srdata)
+        }
+        _edata  =  .;
 
-  BSS_SECTION(0, 0, 0)
+        BSS_SECTION(0, 0, 0)
 
-  _end = .;
+        _end = .;
 
-  code : { } :code
+        code : {
+        } :code
 
-  STABS_DEBUG
-  DWARF_DEBUG
+        STABS_DEBUG
+        DWARF_DEBUG
 
-  /* Default discards */
-  DISCARDS
+        /* Default discards */
+        DISCARDS
 }
diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
index 505a08592423..be3855250db6 100644
--- a/arch/microblaze/Kconfig
+++ b/arch/microblaze/Kconfig
@@ -14,6 +14,7 @@ config MICROBLAZE
         select USB_ARCH_HAS_EHCI
         select ARCH_WANT_OPTIONAL_GPIOLIB
         select HAVE_OPROFILE
+        select HAVE_ARCH_KGDB
         select HAVE_DMA_ATTRS
         select HAVE_DMA_API_DEBUG
         select TRACING_SUPPORT
@@ -223,6 +224,36 @@ config TASK_SIZE
         hex "Size of user task space" if TASK_SIZE_BOOL
         default "0x80000000"
 
+choice
+        prompt "Page size"
+        default MICROBLAZE_4K_PAGES
+        depends on ADVANCED_OPTIONS && !MMU
+        help
+          Select the kernel logical page size. Increasing the page size
+          will reduce software overhead at each page boundary, allow
+          hardware prefetch mechanisms to be more effective, and allow
+          larger dma transfers increasing IO efficiency and reducing
+          overhead. However the utilization of memory will increase.
+          For example, each cached file will using a multiple of the
+          page size to hold its contents and the difference between the
+          end of file and the end of page is wasted.
+
+          If unsure, choose 4K_PAGES.
+
+config MICROBLAZE_4K_PAGES
+        bool "4k page size"
+
+config MICROBLAZE_8K_PAGES
+        bool "8k page size"
+
+config MICROBLAZE_16K_PAGES
+        bool "16k page size"
+
+config MICROBLAZE_32K_PAGES
+        bool "32k page size"
+
+endchoice
+
 endmenu
 
 source "mm/Kconfig"
diff --git a/arch/microblaze/Kconfig.debug b/arch/microblaze/Kconfig.debug
index 9dc708a7f700..e6e5e0da28c3 100644
--- a/arch/microblaze/Kconfig.debug
+++ b/arch/microblaze/Kconfig.debug
@@ -10,6 +10,7 @@ source "lib/Kconfig.debug"
 
 config EARLY_PRINTK
         bool "Early printk function for kernel"
+        depends on SERIAL_UARTLITE_CONSOLE
         default n
         help
           This option turns on/off early printk messages to console.
diff --git a/arch/microblaze/boot/Makefile b/arch/microblaze/boot/Makefile
index 57f50c2371c6..be01d78750d9 100644
--- a/arch/microblaze/boot/Makefile
+++ b/arch/microblaze/boot/Makefile
@@ -35,13 +35,14 @@ quiet_cmd_cp = CP      $< $@$2
         cmd_cp = cat $< >$@$2 || (rm -f $@ && echo false)
 
 quiet_cmd_strip = STRIP   $@
-      cmd_strip = $(STRIP) -K _start -K _end -K __log_buf -K _fdt_start vmlinux -o $@
+        cmd_strip = $(STRIP) -K microblaze_start -K _end -K __log_buf \
+                                -K _fdt_start vmlinux -o $@
 
 quiet_cmd_uimage = UIMAGE  $@.ub
-      cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A microblaze -O linux -T kernel \
-                   -C none -n 'Linux-$(KERNELRELEASE)' \
-                   -a $(CONFIG_KERNEL_BASE_ADDR) -e $(CONFIG_KERNEL_BASE_ADDR) \
-                   -d $@ $@.ub
+        cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A microblaze -O linux -T kernel \
+                -C none -n 'Linux-$(KERNELRELEASE)' \
+                -a $(CONFIG_KERNEL_BASE_ADDR) -e $(CONFIG_KERNEL_BASE_ADDR) \
+                -d $@ $@.ub
 
 $(obj)/simpleImage.%: vmlinux FORCE
         $(call if_changed,cp,.unstrip)
diff --git a/arch/microblaze/include/asm/cacheflush.h b/arch/microblaze/include/asm/cacheflush.h
index a6edd356cd08..7ebd955460d9 100644
--- a/arch/microblaze/include/asm/cacheflush.h
+++ b/arch/microblaze/include/asm/cacheflush.h
@@ -17,6 +17,7 @@
 
 /* Somebody depends on this; sigh... */
 #include <linux/mm.h>
+#include <linux/io.h>
 
 /* Look at Documentation/cachetlb.txt */
 
@@ -60,7 +61,6 @@ void microblaze_cache_init(void);
 #define invalidate_icache()                             mbc->iin();
 #define invalidate_icache_range(start, end)             mbc->iinr(start, end);
 
-
 #define flush_icache_user_range(vma, pg, adr, len)      flush_icache();
 #define flush_icache_page(vma, pg)                      do { } while (0)
 
@@ -72,9 +72,15 @@ void microblaze_cache_init(void);
 #define flush_dcache()                                  mbc->dfl();
 #define flush_dcache_range(start, end)                  mbc->dflr(start, end);
 
-#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
-/* D-cache aliasing problem can't happen - cache is between MMU and ram */
-#define flush_dcache_page(page)                 do { } while (0)
+#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
+/* MS: We have to implement it because of rootfs-jffs2 issue on WB */
+#define flush_dcache_page(page) \
+do { \
+        unsigned long addr = (unsigned long) page_address(page); /* virtual */ \
+        addr = (u32)virt_to_phys((void *)addr); \
+        flush_dcache_range((unsigned) (addr), (unsigned) (addr) + PAGE_SIZE); \
+} while (0);
+
 #define flush_dcache_mmap_lock(mapping)         do { } while (0)
 #define flush_dcache_mmap_unlock(mapping)       do { } while (0)
 
@@ -97,8 +103,10 @@ void microblaze_cache_init(void);
 
 #define copy_to_user_page(vma, page, vaddr, dst, src, len)              \
 do {                                                                    \
+        u32 addr = virt_to_phys(dst);                                   \
+        invalidate_icache_range((unsigned) (addr), (unsigned) (addr) + (len));\
         memcpy((dst), (src), (len));                                    \
-        flush_icache_range((unsigned) (dst), (unsigned) (dst) + (len)); \
+        flush_dcache_range((unsigned) (addr), (unsigned) (addr) + (len));\
 } while (0)
 
 #define copy_from_user_page(vma, page, vaddr, dst, src, len)            \
diff --git a/arch/microblaze/include/asm/dma-mapping.h b/arch/microblaze/include/asm/dma-mapping.h
index 18b3731c8509..507389580709 100644
--- a/arch/microblaze/include/asm/dma-mapping.h
+++ b/arch/microblaze/include/asm/dma-mapping.h
@@ -79,12 +79,6 @@ static inline int dma_supported(struct device *dev, u64 mask)
         return ops->dma_supported(dev, mask);
 }
 
-#ifdef CONFIG_PCI
-/* We have our own implementation of pci_set_dma_mask() */
-#define HAVE_ARCH_PCI_SET_DMA_MASK
-
-#endif
-
 static inline int dma_set_mask(struct device *dev, u64 dma_mask)
 {
         struct dma_map_ops *ops = get_dma_ops(dev);
diff --git a/arch/microblaze/include/asm/elf.h b/arch/microblaze/include/asm/elf.h
index 7d4acf2b278e..732caf1be741 100644
--- a/arch/microblaze/include/asm/elf.h
+++ b/arch/microblaze/include/asm/elf.h
@@ -77,7 +77,7 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
 #define ELF_DATA        ELFDATA2MSB
 #endif
 
-#define ELF_EXEC_PAGESIZE       4096
+#define ELF_EXEC_PAGESIZE       PAGE_SIZE
 
 
 #define ELF_CORE_COPY_REGS(_dest, _regs)                        \
diff --git a/arch/microblaze/include/asm/exceptions.h b/arch/microblaze/include/asm/exceptions.h
index 4c7b5d037c88..6479097b802b 100644
--- a/arch/microblaze/include/asm/exceptions.h
+++ b/arch/microblaze/include/asm/exceptions.h
@@ -14,6 +14,11 @@
 #define _ASM_MICROBLAZE_EXCEPTIONS_H
 
 #ifdef __KERNEL__
+
+#ifndef CONFIG_MMU
+#define EX_HANDLER_STACK_SIZ    (4*19)
+#endif
+
 #ifndef __ASSEMBLY__
 
 /* Macros to enable and disable HW exceptions in the MSR */
@@ -64,22 +69,6 @@ asmlinkage void full_exception(struct pt_regs *regs, unsigned int type,
 void die(const char *str, struct pt_regs *fp, long err);
 void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr);
 
-#if defined(CONFIG_KGDB)
-void (*debugger)(struct pt_regs *regs);
-int (*debugger_bpt)(struct pt_regs *regs);
-int (*debugger_sstep)(struct pt_regs *regs);
-int (*debugger_iabr_match)(struct pt_regs *regs);
-int (*debugger_dabr_match)(struct pt_regs *regs);
-void (*debugger_fault_handler)(struct pt_regs *regs);
-#else
-#define debugger(regs)                  do { } while (0)
-#define debugger_bpt(regs)              0
-#define debugger_sstep(regs)            0
-#define debugger_iabr_match(regs)       0
-#define debugger_dabr_match(regs)       0
-#define debugger_fault_handler          ((void (*)(struct pt_regs *))0)
-#endif
-
 #endif /*__ASSEMBLY__ */
 #endif /* __KERNEL__ */
 #endif /* _ASM_MICROBLAZE_EXCEPTIONS_H */
diff --git a/arch/microblaze/include/asm/kgdb.h b/arch/microblaze/include/asm/kgdb.h
new file mode 100644
index 000000000000..78b17d40b235
--- /dev/null
+++ b/arch/microblaze/include/asm/kgdb.h
@@ -0,0 +1,28 @@
+#ifdef __KERNEL__
+#ifndef __MICROBLAZE_KGDB_H__
+#define __MICROBLAZE_KGDB_H__
+
+#ifndef __ASSEMBLY__
+
+#define CACHE_FLUSH_IS_SAFE     1
+#define BUFMAX                  2048
+
+/*
+ * 32 32-bit general purpose registers (r0-r31)
+ *  6 32-bit special registers (pc, msr, ear, esr, fsr, btr)
+ * 12 32-bit PVR
+ *   7 32-bit MMU Regs (redr, rpid, rzpr, rtlbx, rtlbsx, rtlblo, rtlbhi)
+ * ------
+ *  57 registers
+ */
+#define NUMREGBYTES     (57 * 4)
+
+#define BREAK_INSTR_SIZE        4
+static inline void arch_kgdb_breakpoint(void)
+{
+        __asm__ __volatile__("brki r16, 0x18;");
+}
+
+#endif /* __ASSEMBLY__ */
+#endif /* __MICROBLAZE_KGDB_H__ */
+#endif /* __KERNEL__ */
diff --git a/arch/microblaze/include/asm/page.h b/arch/microblaze/include/asm/page.h
index 464ff32bee3d..c12c6dfafd9f 100644
--- a/arch/microblaze/include/asm/page.h
+++ b/arch/microblaze/include/asm/page.h
@@ -23,8 +23,16 @@
 #ifdef __KERNEL__
 
 /* PAGE_SHIFT determines the page size */
-#define PAGE_SHIFT      (12)
-#define PAGE_SIZE       (_AC(1, UL) << PAGE_SHIFT)
+#if defined(CONFIG_MICROBLAZE_32K_PAGES)
+#define PAGE_SHIFT              15
+#elif defined(CONFIG_MICROBLAZE_16K_PAGES)
+#define PAGE_SHIFT              14
+#elif defined(CONFIG_MICROBLAZE_8K_PAGES)
+#define PAGE_SHIFT              13
+#else
+#define PAGE_SHIFT              12
+#endif
+#define PAGE_SIZE       (ASM_CONST(1) << PAGE_SHIFT)
 #define PAGE_MASK       (~(PAGE_SIZE-1))
 
 #define LOAD_OFFSET     ASM_CONST((CONFIG_KERNEL_START-CONFIG_KERNEL_BASE_ADDR))
diff --git a/arch/microblaze/include/asm/pvr.h b/arch/microblaze/include/asm/pvr.h
index e38abc7714b6..9578666e98ba 100644
--- a/arch/microblaze/include/asm/pvr.h
+++ b/arch/microblaze/include/asm/pvr.h
@@ -16,7 +16,7 @@
 #define PVR_MSR_BIT 0x400
 
 struct pvr_s {
-        unsigned pvr[16];
+        unsigned pvr[12];
 };
 
 /* The following taken from Xilinx's standalone BSP pvr.h */
diff --git a/arch/microblaze/include/asm/setup.h b/arch/microblaze/include/asm/setup.h
index 7f31394985e0..782b5c89248e 100644
--- a/arch/microblaze/include/asm/setup.h
+++ b/arch/microblaze/include/asm/setup.h
@@ -28,8 +28,6 @@ void disable_early_printk(void);
 void heartbeat(void);
 void setup_heartbeat(void);
 
-unsigned long long sched_clock(void);
-
 #   ifdef CONFIG_MMU
 extern void mmu_reset(void);
 extern void early_console_reg_tlb_alloc(unsigned int addr);
diff --git a/arch/microblaze/include/asm/system.h b/arch/microblaze/include/asm/system.h
index 81e1f7d5b4cb..e6a2284571dc 100644
--- a/arch/microblaze/include/asm/system.h
+++ b/arch/microblaze/include/asm/system.h
@@ -45,7 +45,6 @@ extern struct task_struct *_switch_to(struct thread_info *prev,
 #define smp_rmb()               rmb()
 #define smp_wmb()               wmb()
 
-void show_trace(struct task_struct *task, unsigned long *stack);
 void __bad_xchg(volatile void *ptr, int size);
 
 static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
diff --git a/arch/microblaze/include/asm/uaccess.h b/arch/microblaze/include/asm/uaccess.h
index 26460d15b338..d840f4a2d3c9 100644
--- a/arch/microblaze/include/asm/uaccess.h
+++ b/arch/microblaze/include/asm/uaccess.h
@@ -359,7 +359,7 @@ extern long __user_bad(void);
         __copy_tofrom_user((__force void __user *)(to), \
                                 (void __user *)(from), (n))
 #define __copy_from_user_inatomic(to, from, n) \
-                copy_from_user((to), (from), (n))
+                __copy_from_user((to), (from), (n))
 
 static inline long copy_from_user(void *to,
                 const void __user *from, unsigned long n)
@@ -373,7 +373,7 @@ static inline long copy_from_user(void *to,
 #define __copy_to_user(to, from, n)     \
                 __copy_tofrom_user((void __user *)(to), \
                         (__force const void __user *)(from), (n))
-#define __copy_to_user_inatomic(to, from, n)    copy_to_user((to), (from), (n))
+#define __copy_to_user_inatomic(to, from, n) __copy_to_user((to), (from), (n))
 
 static inline long copy_to_user(void __user *to,
                 const void *from, unsigned long n)
diff --git a/arch/microblaze/include/asm/unwind.h b/arch/microblaze/include/asm/unwind.h
new file mode 100644
index 000000000000..d248b7de4b13
--- /dev/null
+++ b/arch/microblaze/include/asm/unwind.h
@@ -0,0 +1,29 @@
+/*
+ * Backtrace support for Microblaze
+ *
+ * Copyright (C) 2010  Digital Design Corporation
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef __MICROBLAZE_UNWIND_H
+#define __MICROBLAZE_UNWIND_H
+
+struct stack_trace;
+
+struct trap_handler_info {
+        unsigned long start_addr;
+        unsigned long end_addr;
+        const char    *trap_name;
+};
+extern struct trap_handler_info microblaze_trap_handlers;
+
+extern const char _hw_exception_handler;
+extern const char ex_handler_unhandled;
+
+void microblaze_unwind(struct task_struct *task, struct stack_trace *trace);
+
+#endif  /* __MICROBLAZE_UNWIND_H */
+
diff --git a/arch/microblaze/kernel/Makefile b/arch/microblaze/kernel/Makefile
index e51bc1520825..5eecc9f1fbd9 100644
--- a/arch/microblaze/kernel/Makefile
+++ b/arch/microblaze/kernel/Makefile
@@ -17,7 +17,7 @@ extra-y := head.o vmlinux.lds
 obj-y += dma.o exceptions.o \
         hw_exception_handler.o init_task.o intc.o irq.o of_device.o \
         of_platform.o process.o prom.o prom_parse.o ptrace.o \
-        setup.o signal.o sys_microblaze.o timer.o traps.o reset.o
+        reset.o setup.o signal.o sys_microblaze.o timer.o traps.o unwind.o
 
 obj-y += cpu/
 
@@ -28,5 +28,6 @@ obj-$(CONFIG_MODULES)		+= microblaze_ksyms.o module.o
 obj-$(CONFIG_MMU)               += misc.o
 obj-$(CONFIG_STACKTRACE)        += stacktrace.o
 obj-$(CONFIG_FUNCTION_TRACER)   += ftrace.o mcount.o
+obj-$(CONFIG_KGDB)              += kgdb.o
 
 obj-y   += entry$(MMU).o
diff --git a/arch/microblaze/kernel/cpu/mb.c b/arch/microblaze/kernel/cpu/mb.c
index 4216eb1eaa32..7086e3564281 100644
--- a/arch/microblaze/kernel/cpu/mb.c
+++ b/arch/microblaze/kernel/cpu/mb.c
@@ -126,6 +126,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
                         cpuinfo.pvr_user1,
                         cpuinfo.pvr_user2);
 
+        count += seq_printf(m, "Page size:\t%lu\n", PAGE_SIZE);
         return 0;
 }
 
diff --git a/arch/microblaze/kernel/entry-nommu.S b/arch/microblaze/kernel/entry-nommu.S
index 8cc18cd2cce6..ca84368570b6 100644
--- a/arch/microblaze/kernel/entry-nommu.S
+++ b/arch/microblaze/kernel/entry-nommu.S
@@ -588,3 +588,31 @@ sys_rt_sigsuspend_wrapper:
 #include "syscall_table.S"
 
 syscall_table_size=(.-sys_call_table)
+
+type_SYSCALL:
+        .ascii "SYSCALL\0"
+type_IRQ:
+        .ascii "IRQ\0"
+type_IRQ_PREEMPT:
+        .ascii "IRQ (PREEMPTED)\0"
+type_SYSCALL_PREEMPT:
+        .ascii " SYSCALL (PREEMPTED)\0"
+
+        /*
+         * Trap decoding for stack unwinder
+         * Tuples are (start addr, end addr, string)
+         * If return address lies on [start addr, end addr],
+         * unwinder displays 'string'
+         */
+
+        .align 4
+.global microblaze_trap_handlers
+microblaze_trap_handlers:
+        /* Exact matches come first */
+        .word ret_to_user  ; .word ret_to_user    ; .word type_SYSCALL
+        .word ret_from_intr; .word ret_from_intr  ; .word type_IRQ
+        /* Fuzzy matches go here */
+        .word ret_from_intr; .word no_intr_resched; .word type_IRQ_PREEMPT
+        .word work_pending ; .word no_work_pending; .word type_SYSCALL_PREEMPT
+        /* End of table */
+        .word 0             ; .word 0               ; .word 0
diff --git a/arch/microblaze/kernel/entry.S b/arch/microblaze/kernel/entry.S
index c0ede25c5b99..304882e56459 100644
--- a/arch/microblaze/kernel/entry.S
+++ b/arch/microblaze/kernel/entry.S
@@ -48,128 +48,107 @@
  */
 #if CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR
         .macro  clear_bip
-        msrclr  r11, MSR_BIP
-        nop
+        msrclr  r0, MSR_BIP
         .endm
 
         .macro  set_bip
-        msrset  r11, MSR_BIP
-        nop
+        msrset  r0, MSR_BIP
         .endm
 
         .macro  clear_eip
-        msrclr  r11, MSR_EIP
-        nop
+        msrclr  r0, MSR_EIP
         .endm
 
         .macro  set_ee
-        msrset  r11, MSR_EE
-        nop
+        msrset  r0, MSR_EE
         .endm
 
         .macro  disable_irq
-        msrclr  r11, MSR_IE
-        nop
+        msrclr  r0, MSR_IE
         .endm
 
         .macro  enable_irq
-        msrset  r11, MSR_IE
-        nop
+        msrset  r0, MSR_IE
         .endm
 
         .macro  set_ums
-        msrset  r11, MSR_UMS
-        nop
-        msrclr  r11, MSR_VMS
-        nop
+        msrset  r0, MSR_UMS
+        msrclr  r0, MSR_VMS
         .endm
 
         .macro  set_vms
-        msrclr  r11, MSR_UMS
-        nop
-        msrset  r11, MSR_VMS
-        nop
+        msrclr  r0, MSR_UMS
+        msrset  r0, MSR_VMS
+        .endm
+
+        .macro  clear_ums
+        msrclr  r0, MSR_UMS
         .endm
 
         .macro  clear_vms_ums
-        msrclr  r11, MSR_VMS
-        nop
-        msrclr  r11, MSR_UMS
-        nop
+        msrclr  r0, MSR_VMS | MSR_UMS
         .endm
 #else
         .macro  clear_bip
         mfs     r11, rmsr
-        nop
         andi    r11, r11, ~MSR_BIP
         mts     rmsr, r11
-        nop
         .endm
 
         .macro  set_bip
         mfs     r11, rmsr
-        nop
         ori     r11, r11, MSR_BIP
         mts     rmsr, r11
-        nop
         .endm
 
         .macro  clear_eip
         mfs     r11, rmsr
-        nop
         andi    r11, r11, ~MSR_EIP
         mts     rmsr, r11
-        nop
         .endm
 
         .macro  set_ee
         mfs     r11, rmsr
-        nop
         ori     r11, r11, MSR_EE
         mts     rmsr, r11
-        nop
         .endm
 
         .macro  disable_irq
         mfs     r11, rmsr
-        nop
         andi    r11, r11, ~MSR_IE
         mts     rmsr, r11
-        nop
         .endm
 
         .macro  enable_irq
         mfs     r11, rmsr
-        nop
         ori     r11, r11, MSR_IE
         mts     rmsr, r11
-        nop
         .endm
 
         .macro set_ums
         mfs     r11, rmsr
-        nop
         ori     r11, r11, MSR_VMS
         andni   r11, r11, MSR_UMS
         mts     rmsr, r11
-        nop
         .endm
 
         .macro  set_vms
         mfs     r11, rmsr
-        nop
         ori     r11, r11, MSR_VMS
         andni   r11, r11, MSR_UMS
         mts     rmsr, r11
-        nop
+        .endm
+
+        .macro  clear_ums
+        mfs     r11, rmsr
+        andni   r11, r11, MSR_UMS
+        mts     rmsr,r11
         .endm
 
         .macro  clear_vms_ums
         mfs     r11, rmsr
-        nop
         andni   r11, r11, (MSR_VMS|MSR_UMS)
         mts     rmsr,r11
-        nop
         .endm
 #endif
 
@@ -180,18 +159,22 @@
 
 /* turn on virtual protected mode save */
 #define VM_ON           \
-        set_ums;                \
+        set_ums;        \
         rted    r0, 2f; \
-2: nop;
+        nop; \
+2:
 
 /* turn off virtual protected mode save and user mode save*/
 #define VM_OFF                  \
-        clear_vms_ums;                  \
+        clear_vms_ums;          \
         rted    r0, TOPHYS(1f); \
-1: nop;
+        nop; \
+1:
 
 #define SAVE_REGS \
         swi     r2, r1, PTO+PT_R2;      /* Save SDA */                  \
+        swi     r3, r1, PTO+PT_R3;                                      \
+        swi     r4, r1, PTO+PT_R4;                                      \
         swi     r5, r1, PTO+PT_R5;                                      \
         swi     r6, r1, PTO+PT_R6;                                      \
         swi     r7, r1, PTO+PT_R7;                                      \
@@ -218,14 +201,14 @@
         swi     r30, r1, PTO+PT_R30;                                    \
         swi     r31, r1, PTO+PT_R31;    /* Save current task reg */     \
         mfs     r11, rmsr;              /* save MSR */                  \
-        nop;                                                            \
         swi     r11, r1, PTO+PT_MSR;
 
 #define RESTORE_REGS \
         lwi     r11, r1, PTO+PT_MSR;                                    \
         mts     rmsr , r11;                                             \
-        nop;                                                            \
         lwi     r2, r1, PTO+PT_R2;      /* restore SDA */               \
+        lwi     r3, r1, PTO+PT_R3;                                      \
+        lwi     r4, r1, PTO+PT_R4;                                      \
         lwi     r5, r1, PTO+PT_R5;                                      \
         lwi     r6, r1, PTO+PT_R6;                                      \
         lwi     r7, r1, PTO+PT_R7;                                      \
@@ -252,6 +235,39 @@
         lwi     r30, r1, PTO+PT_R30;                                    \
         lwi     r31, r1, PTO+PT_R31;    /* Restore cur task reg */
 
+#define SAVE_STATE      \
+        swi     r1, r0, TOPHYS(PER_CPU(ENTRY_SP)); /* save stack */     \
+        /* See if already in kernel mode.*/                             \
+        mfs     r1, rmsr;                                               \
+        andi    r1, r1, MSR_UMS;                                        \
+        bnei    r1, 1f;                                         \
+        /* Kernel-mode state save.  */                                  \
+        /* Reload kernel stack-ptr. */                                  \
+        lwi     r1, r0, TOPHYS(PER_CPU(ENTRY_SP));                      \
+        /* FIXME: I can add these two lines to one */                   \
+        /* tophys(r1,r1); */                                            \
+        /* addik        r1, r1, -STATE_SAVE_SIZE; */                    \
+        addik   r1, r1, CONFIG_KERNEL_BASE_ADDR - CONFIG_KERNEL_START - STATE_SAVE_SIZE; \
+        SAVE_REGS                                                       \
+        brid    2f;                                                     \
+        swi     r1, r1, PTO+PT_MODE;                                    \
+1:      /* User-mode state save.  */                                    \
+        lwi     r1, r0, TOPHYS(PER_CPU(CURRENT_SAVE)); /* get saved current */\
+        tophys(r1,r1);                                                  \
+        lwi     r1, r1, TS_THREAD_INFO; /* get the thread info */       \
+        /* MS these three instructions can be added to one */           \
+        /* addik        r1, r1, THREAD_SIZE; */                         \
+        /* tophys(r1,r1); */                                            \
+        /* addik        r1, r1, -STATE_SAVE_SIZE; */                    \
+        addik r1, r1, THREAD_SIZE + CONFIG_KERNEL_BASE_ADDR - CONFIG_KERNEL_START - STATE_SAVE_SIZE; \
+        SAVE_REGS                                                       \
+        lwi     r11, r0, TOPHYS(PER_CPU(ENTRY_SP));                     \
+        swi     r11, r1, PTO+PT_R1; /* Store user SP.  */               \
+        swi     r0, r1, PTO + PT_MODE; /* Was in user-mode.  */         \
+        /* MS: I am clearing UMS even in case when I come from kernel space */ \
+        clear_ums;                                                      \
+2:      lwi     CURRENT_TASK, r0, TOPHYS(PER_CPU(CURRENT_SAVE));
+
 .text
 
 /*
@@ -267,45 +283,23 @@
  * are masked. This is nice, means we don't have to CLI before state save
  */
 C_ENTRY(_user_exception):
-        swi     r1, r0, TOPHYS(PER_CPU(ENTRY_SP)) /* save stack */
         addi    r14, r14, 4     /* return address is 4 byte after call */
-        swi     r11, r0, TOPHYS(r0_ram + PTO + PT_R11); /* Save r11 */
-
-        lwi     r11, r0, TOPHYS(PER_CPU(KM));/* See if already in kernel mode.*/
-        beqi    r11, 1f;                /* Jump ahead if coming from user */
-/* Kernel-mode state save. */
-        lwi     r11, r0, TOPHYS(PER_CPU(ENTRY_SP)); /* Reload kernel stack-ptr*/
-        tophys(r1,r11);
-        swi     r11, r1, (PT_R1-PT_SIZE); /* Save original SP. */
-        lwi     r11, r0, TOPHYS(r0_ram + PTO + PT_R11); /* restore r11 */
-
-        addik   r1, r1, -STATE_SAVE_SIZE; /* Make room on the stack. */
-        SAVE_REGS
-
-        addi    r11, r0, 1;             /* Was in kernel-mode. */
-        swi     r11, r1, PTO+PT_MODE; /* pt_regs -> kernel mode */
-        brid    2f;
-        nop;                            /* Fill delay slot */
+        swi     r1, r0, TOPHYS(PER_CPU(ENTRY_SP)) /* save stack */
 
-/* User-mode state save.  */
-1:
-        lwi     r11, r0, TOPHYS(r0_ram + PTO + PT_R11); /* restore r11 */
         lwi     r1, r0, TOPHYS(PER_CPU(CURRENT_SAVE)); /* get saved current */
         tophys(r1,r1);
         lwi     r1, r1, TS_THREAD_INFO; /* get stack from task_struct */
-/* calculate kernel stack pointer from task struct 8k */
-        addik   r1, r1, THREAD_SIZE;
-        tophys(r1,r1);
-
-        addik   r1, r1, -STATE_SAVE_SIZE; /* Make room on the stack.  */
+        /* MS these three instructions can be added to one */
+        /* addik        r1, r1, THREAD_SIZE; */
+        /* tophys(r1,r1); */
+        /* addik        r1, r1, -STATE_SAVE_SIZE; */
+        addik r1, r1, THREAD_SIZE + CONFIG_KERNEL_BASE_ADDR - CONFIG_KERNEL_START - STATE_SAVE_SIZE;
         SAVE_REGS
 
-        swi     r0, r1, PTO+PT_MODE;                    /* Was in user-mode. */
         lwi     r11, r0, TOPHYS(PER_CPU(ENTRY_SP));
         swi     r11, r1, PTO+PT_R1;             /* Store user SP.  */
-        addi    r11, r0, 1;
-        swi     r11, r0, TOPHYS(PER_CPU(KM));   /* Now we're in kernel-mode.  */
-2:      lwi     CURRENT_TASK, r0, TOPHYS(PER_CPU(CURRENT_SAVE));
+        clear_ums;
+        lwi     CURRENT_TASK, r0, TOPHYS(PER_CPU(CURRENT_SAVE));
         /* Save away the syscall number.  */
         swi     r12, r1, PTO+PT_R0;
         tovirt(r1,r1)
@@ -316,10 +310,8 @@ C_ENTRY(_user_exception):
  * register should point to the location where
  * the called function should return.  [note that MAKE_SYS_CALL uses label 1] */
 
-        # Step into virtual mode.
-        set_vms;
-        addik   r11, r0, 3f
-        rtid    r11, 0
+        /* Step into virtual mode */
+        rtbd    r0, 3f
         nop
 3:
         lwi     r11, CURRENT_TASK, TS_THREAD_INFO /* get thread info */
@@ -363,24 +355,17 @@ C_ENTRY(_user_exception):
         # Find and jump into the syscall handler.
         lwi     r12, r12, sys_call_table
         /* where the trap should return need -8 to adjust for rtsd r15, 8 */
-        la      r15, r0, ret_from_trap-8
+        addi    r15, r0, ret_from_trap-8
         bra     r12
 
         /* The syscall number is invalid, return an error.  */
 5:
+        rtsd    r15, 8;         /* looks like a normal subroutine return */
         addi    r3, r0, -ENOSYS;
-        rtsd    r15,8;          /* looks like a normal subroutine return */
-        or      r0, r0, r0
-
 
 /* Entry point used to return from a syscall/trap */
 /* We re-enable BIP bit before state restore */
 C_ENTRY(ret_from_trap):
-        set_bip;                        /*  Ints masked for state restore*/
-        lwi     r11, r1, PTO+PT_MODE;
-/* See if returning to kernel mode, if so, skip resched &c.  */
-        bnei    r11, 2f;
-
         swi     r3, r1, PTO + PT_R3
         swi     r4, r1, PTO + PT_R4
 
@@ -413,32 +398,19 @@ C_ENTRY(ret_from_trap):
         andi    r11, r11, _TIF_SIGPENDING;
         beqi    r11, 1f;                /* Signals to handle, handle them */
 
-        la      r5, r1, PTO;            /* Arg 1: struct pt_regs *regs */
+        addik   r5, r1, PTO;            /* Arg 1: struct pt_regs *regs */
         addi    r7, r0, 1;              /* Arg 3: int in_syscall */
         bralid  r15, do_signal; /* Handle any signals */
         add     r6, r0, r0;             /* Arg 2: sigset_t *oldset */
 
 /* Finally, return to user state.  */
-1:
-        lwi     r3, r1, PTO + PT_R3; /* restore syscall result */
-        lwi     r4, r1, PTO + PT_R4;
-
-        swi     r0, r0, PER_CPU(KM);    /* Now officially in user state. */
+1:      set_bip;                        /*  Ints masked for state restore */
         swi     CURRENT_TASK, r0, PER_CPU(CURRENT_SAVE); /* save current */
         VM_OFF;
         tophys(r1,r1);
         RESTORE_REGS;
         addik   r1, r1, STATE_SAVE_SIZE         /* Clean up stack space.  */
         lwi     r1, r1, PT_R1 - PT_SIZE;/* Restore user stack pointer. */
-        bri     6f;
-
-/* Return to kernel state.  */
-2:      VM_OFF;
-        tophys(r1,r1);
-        RESTORE_REGS;
-        addik   r1, r1, STATE_SAVE_SIZE         /* Clean up stack space.  */
-        tovirt(r1,r1);
-6:
 TRAP_return:            /* Make global symbol for debugging */
         rtbd    r14, 0; /* Instructions to return from an IRQ */
         nop;
@@ -450,12 +422,11 @@ TRAP_return:		/* Make global symbol for debugging */
 C_ENTRY(sys_fork_wrapper):
         addi    r5, r0, SIGCHLD                 /* Arg 0: flags */
         lwi     r6, r1, PTO+PT_R1       /* Arg 1: child SP (use parent's) */
-        la      r7, r1, PTO                     /* Arg 2: parent context */
+        addik   r7, r1, PTO                     /* Arg 2: parent context */
         add     r8. r0, r0                      /* Arg 3: (unused) */
         add     r9, r0, r0;                     /* Arg 4: (unused) */
-        add     r10, r0, r0;                    /* Arg 5: (unused) */
         brid    do_fork         /* Do real work (tail-call) */
-        nop;
+        add     r10, r0, r0;                    /* Arg 5: (unused) */
 
 /* This the initial entry point for a new child thread, with an appropriate
    stack in place that makes it look the the child is in the middle of an
@@ -466,35 +437,31 @@ C_ENTRY(ret_from_fork):
         bralid  r15, schedule_tail; /* ...which is schedule_tail's arg */
         add     r3, r5, r0;     /* switch_thread returns the prev task */
                                 /* ( in the delay slot ) */
-        add     r3, r0, r0;     /* Child's fork call should return 0. */
         brid    ret_from_trap;  /* Do normal trap return */
-        nop;
+        add     r3, r0, r0;     /* Child's fork call should return 0. */
 
 C_ENTRY(sys_vfork):
         brid    microblaze_vfork        /* Do real work (tail-call) */
-        la      r5, r1, PTO
+        addik   r5, r1, PTO
 
 C_ENTRY(sys_clone):
         bnei    r6, 1f;                 /* See if child SP arg (arg 1) is 0. */
-        lwi     r6, r1, PTO+PT_R1;      /* If so, use paret's stack ptr */
-1:      la      r7, r1, PTO;                    /* Arg 2: parent context */
+        lwi     r6, r1, PTO + PT_R1;    /* If so, use paret's stack ptr */
+1:      addik   r7, r1, PTO;                    /* Arg 2: parent context */
         add     r8, r0, r0;                     /* Arg 3: (unused) */
         add     r9, r0, r0;                     /* Arg 4: (unused) */
-        add     r10, r0, r0;                    /* Arg 5: (unused) */
         brid    do_fork         /* Do real work (tail-call) */
-        nop;
+        add     r10, r0, r0;                    /* Arg 5: (unused) */
 
 C_ENTRY(sys_execve):
-        la      r8, r1, PTO;            /* add user context as 4th arg */
         brid    microblaze_execve;      /* Do real work (tail-call).*/
-        nop;
+        addik   r8, r1, PTO;            /* add user context as 4th arg */
 
 C_ENTRY(sys_rt_sigreturn_wrapper):
         swi     r3, r1, PTO+PT_R3; /* restore saved r3, r4 registers */
         swi     r4, r1, PTO+PT_R4;
-        la      r5, r1, PTO;            /* add user context as 1st arg */
         brlid   r15, sys_rt_sigreturn   /* Do real work */
-        nop;
+        addik   r5, r1, PTO;            /* add user context as 1st arg */
         lwi     r3, r1, PTO+PT_R3; /* restore saved r3, r4 registers */
         lwi     r4, r1, PTO+PT_R4;
         bri ret_from_trap /* fall through will not work here due to align */
@@ -503,83 +470,23 @@ C_ENTRY(sys_rt_sigreturn_wrapper):
 /*
  * HW EXCEPTION rutine start
  */
-
-#define SAVE_STATE      \
-        swi     r11, r0, TOPHYS(r0_ram + PTO + PT_R11); /* Save r11 */  \
-        set_bip;        /*equalize initial state for all possible entries*/\
-        clear_eip;                                                      \
-        enable_irq;                                                     \
-        set_ee;                                                         \
-        /* See if already in kernel mode.*/                             \
-        lwi     r11, r0, TOPHYS(PER_CPU(KM));                           \
-        beqi    r11, 1f;                /* Jump ahead if coming from user */\
-        /* Kernel-mode state save.  */                                  \
-        /* Reload kernel stack-ptr. */                                  \
-        lwi     r11, r0, TOPHYS(PER_CPU(ENTRY_SP));                     \
-        tophys(r1,r11);                                                 \
-        swi     r11, r1, (PT_R1-PT_SIZE); /* Save original SP. */       \
-        lwi     r11, r0, TOPHYS(r0_ram + PTO + PT_R11); /* restore r11 */\
-        addik   r1, r1, -STATE_SAVE_SIZE; /* Make room on the stack.  */\
-        /* store return registers separately because                    \
-         * this macros is use for others exceptions */                  \
-        swi     r3, r1, PTO + PT_R3;                                    \
-        swi     r4, r1, PTO + PT_R4;                                    \
-        SAVE_REGS                                                       \
-        /* PC, before IRQ/trap - this is one instruction above */       \
-        swi     r17, r1, PTO+PT_PC;                                     \
-                                                                        \
-        addi    r11, r0, 1;             /* Was in kernel-mode.  */      \
-        swi     r11, r1, PTO+PT_MODE;                                   \
-        brid    2f;                                                     \
-        nop;                            /* Fill delay slot */           \
-1:      /* User-mode state save.  */                                    \
-        lwi     r11, r0, TOPHYS(r0_ram + PTO + PT_R11); /* restore r11 */\
-        lwi     r1, r0, TOPHYS(PER_CPU(CURRENT_SAVE)); /* get saved current */\
-        tophys(r1,r1);                                                  \
-        lwi     r1, r1, TS_THREAD_INFO; /* get the thread info */       \
-        addik   r1, r1, THREAD_SIZE;    /* calculate kernel stack pointer */\
-        tophys(r1,r1);                                                  \
-                                                                        \
-        addik   r1, r1, -STATE_SAVE_SIZE; /* Make room on the stack.  */\
-        /* store return registers separately because this macros        \
-         * is use for others exceptions */                              \
-        swi     r3, r1, PTO + PT_R3;                                    \
-        swi     r4, r1, PTO + PT_R4;                                    \
-        SAVE_REGS                                                       \
-        /* PC, before IRQ/trap - this is one instruction above FIXME*/  \
-        swi     r17, r1, PTO+PT_PC;                                     \
-                                                                        \
-        swi     r0, r1, PTO+PT_MODE; /* Was in user-mode.  */           \
-        lwi     r11, r0, TOPHYS(PER_CPU(ENTRY_SP));                     \
-        swi     r11, r1, PTO+PT_R1; /* Store user SP.  */               \
-        addi    r11, r0, 1;                                             \
-        swi     r11, r0, TOPHYS(PER_CPU(KM)); /* Now we're in kernel-mode.*/\
-2:      lwi     CURRENT_TASK, r0, TOPHYS(PER_CPU(CURRENT_SAVE));        \
-        /* Save away the syscall number.  */                            \
-        swi     r0, r1, PTO+PT_R0;                                      \
-        tovirt(r1,r1)
-
 C_ENTRY(full_exception_trap):
-        swi     r1, r0, TOPHYS(PER_CPU(ENTRY_SP)) /* save stack */
         /* adjust exception address for privileged instruction
          * for finding where is it */
         addik   r17, r17, -4
         SAVE_STATE /* Save registers */
+        /* PC, before IRQ/trap - this is one instruction above */
+        swi     r17, r1, PTO+PT_PC;
+        tovirt(r1,r1)
         /* FIXME this can be store directly in PT_ESR reg.
          * I tested it but there is a fault */
         /* where the trap should return need -8 to adjust for rtsd r15, 8 */
-        la      r15, r0, ret_from_exc - 8
-        la      r5, r1, PTO              /* parameter struct pt_regs * regs */
+        addik   r15, r0, ret_from_exc - 8
         mfs     r6, resr
-        nop
         mfs     r7, rfsr;               /* save FSR */
-        nop
         mts     rfsr, r0;       /* Clear sticky fsr */
-        nop
-        la      r12, r0, full_exception
-        set_vms;
-        rtbd    r12, 0;
-        nop;
+        rted    r0, full_exception
+        addik   r5, r1, PTO              /* parameter struct pt_regs * regs */
 
 /*
  * Unaligned data trap.
@@ -592,19 +499,27 @@ C_ENTRY(full_exception_trap):
  * The assembler routine is in "arch/microblaze/kernel/hw_exception_handler.S"
  */
 C_ENTRY(unaligned_data_trap):
-        swi     r1, r0, TOPHYS(PER_CPU(ENTRY_SP)) /* save stack */
+        /* MS: I have to save r11 value and then restore it because
+         * set_bit, clear_eip, set_ee use r11 as temp register if MSR
+         * instructions are not used. We don't need to do if MSR instructions
+         * are used and they use r0 instead of r11.
+         * I am using ENTRY_SP which should be primary used only for stack
+         * pointer saving. */
+        swi     r11, r0, TOPHYS(PER_CPU(ENTRY_SP));
+        set_bip;        /* equalize initial state for all possible entries */
+        clear_eip;
+        set_ee;
+        lwi     r11, r0, TOPHYS(PER_CPU(ENTRY_SP));
         SAVE_STATE              /* Save registers.*/
+        /* PC, before IRQ/trap - this is one instruction above */
+        swi     r17, r1, PTO+PT_PC;
+        tovirt(r1,r1)
         /* where the trap should return need -8 to adjust for rtsd r15, 8 */
-        la      r15, r0, ret_from_exc-8
+        addik   r15, r0, ret_from_exc-8
         mfs     r3, resr                /* ESR */
-        nop
         mfs     r4, rear                /* EAR */
-        nop
-        la      r7, r1, PTO             /* parameter struct pt_regs * regs */
-        la      r12, r0, _unaligned_data_exception
-        set_vms;
-        rtbd    r12, 0; /* interrupts enabled */
-        nop;
+        rtbd    r0, _unaligned_data_exception
+        addik   r7, r1, PTO             /* parameter struct pt_regs * regs */
 
 /*
  * Page fault traps.
@@ -625,38 +540,32 @@ C_ENTRY(unaligned_data_trap):
  */
 /* data and intruction trap - which is choose is resolved int fault.c */
 C_ENTRY(page_fault_data_trap):
-        swi     r1, r0, TOPHYS(PER_CPU(ENTRY_SP)) /* save stack */
         SAVE_STATE              /* Save registers.*/
+        /* PC, before IRQ/trap - this is one instruction above */
+        swi     r17, r1, PTO+PT_PC;
+        tovirt(r1,r1)
         /* where the trap should return need -8 to adjust for rtsd r15, 8 */
-        la      r15, r0, ret_from_exc-8
-        la      r5, r1, PTO             /* parameter struct pt_regs * regs */
+        addik   r15, r0, ret_from_exc-8
         mfs     r6, rear                /* parameter unsigned long address */
-        nop
         mfs     r7, resr                /* parameter unsigned long error_code */
-        nop
-        la      r12, r0, do_page_fault
-        set_vms;
-        rtbd    r12, 0; /* interrupts enabled */
-        nop;
+        rted    r0, do_page_fault
+        addik   r5, r1, PTO             /* parameter struct pt_regs * regs */
 
 C_ENTRY(page_fault_instr_trap):
-        swi     r1, r0, TOPHYS(PER_CPU(ENTRY_SP)) /* save stack */
         SAVE_STATE              /* Save registers.*/
+        /* PC, before IRQ/trap - this is one instruction above */
+        swi     r17, r1, PTO+PT_PC;
+        tovirt(r1,r1)
         /* where the trap should return need -8 to adjust for rtsd r15, 8 */
-        la      r15, r0, ret_from_exc-8
-        la      r5, r1, PTO             /* parameter struct pt_regs * regs */
+        addik   r15, r0, ret_from_exc-8
         mfs     r6, rear                /* parameter unsigned long address */
-        nop
         ori     r7, r0, 0               /* parameter unsigned long error_code */
-        la      r12, r0, do_page_fault
-        set_vms;
-        rtbd    r12, 0; /* interrupts enabled */
-        nop;
+        rted    r0, do_page_fault
+        addik   r5, r1, PTO             /* parameter struct pt_regs * regs */
 
 /* Entry point used to return from an exception.  */
 C_ENTRY(ret_from_exc):
-        set_bip;                        /*  Ints masked for state restore*/
-        lwi     r11, r1, PTO+PT_MODE;
+        lwi     r11, r1, PTO + PT_MODE;
         bnei    r11, 2f;                /* See if returning to kernel mode, */
                                         /* ... if so, skip resched &c.  */
 
@@ -687,32 +596,27 @@ C_ENTRY(ret_from_exc):
          * traps), but signal handlers may want to examine or change the
          * complete register state.  Here we save anything not saved by
          * the normal entry sequence, so that it may be safely restored
-         * (in a possibly modified form) after do_signal returns.
-         * store return registers separately because this macros is use
-         * for others exceptions */
-        la      r5, r1, PTO;            /* Arg 1: struct pt_regs *regs */
+         * (in a possibly modified form) after do_signal returns. */
+        addik   r5, r1, PTO;            /* Arg 1: struct pt_regs *regs */
         addi    r7, r0, 0;              /* Arg 3: int in_syscall */
         bralid  r15, do_signal; /* Handle any signals */
         add     r6, r0, r0;             /* Arg 2: sigset_t *oldset */
 
 /* Finally, return to user state.  */
-1:      swi     r0, r0, PER_CPU(KM);    /* Now officially in user state. */
+1:      set_bip;                        /* Ints masked for state restore */
         swi     CURRENT_TASK, r0, PER_CPU(CURRENT_SAVE); /* save current */
         VM_OFF;
         tophys(r1,r1);
 
-        lwi     r3, r1, PTO+PT_R3; /* restore saved r3, r4 registers */
-        lwi     r4, r1, PTO+PT_R4;
         RESTORE_REGS;
         addik   r1, r1, STATE_SAVE_SIZE         /* Clean up stack space.  */
 
         lwi     r1, r1, PT_R1 - PT_SIZE; /* Restore user stack pointer. */
         bri     6f;
 /* Return to kernel state.  */
-2:      VM_OFF;
+2:      set_bip;                        /* Ints masked for state restore */
+        VM_OFF;
         tophys(r1,r1);
-        lwi     r3, r1, PTO+PT_R3; /* restore saved r3, r4 registers */
-        lwi     r4, r1, PTO+PT_R4;
         RESTORE_REGS;
         addik   r1, r1, STATE_SAVE_SIZE         /* Clean up stack space.  */
 
@@ -736,36 +640,23 @@ C_ENTRY(_interrupt):
 /* MS: we are in physical address */
 /* Save registers, switch to proper stack, convert SP to virtual.*/
         swi     r1, r0, TOPHYS(PER_CPU(ENTRY_SP))
-        swi     r11, r0, TOPHYS(PER_CPU(R11_SAVE));
         /* MS: See if already in kernel mode. */
-        lwi     r11, r0, TOPHYS(PER_CPU(KM));
-        beqi    r11, 1f; /* MS: Jump ahead if coming from user */
+        mfs     r1, rmsr
+        nop
+        andi    r1, r1, MSR_UMS
+        bnei    r1, 1f
 
 /* Kernel-mode state save. */
-        or      r11, r1, r0
-        tophys(r1,r11); /* MS: I have in r1 physical address where stack is */
-/* MS: Save original SP - position PT_R1 to next stack frame 4 *1 - 152*/
-        swi     r11, r1, (PT_R1 - PT_SIZE);
-/* MS: restore r11 because of saving in SAVE_REGS */
-        lwi     r11, r0, TOPHYS(PER_CPU(R11_SAVE));
+        lwi     r1, r0, TOPHYS(PER_CPU(ENTRY_SP))
+        tophys(r1,r1); /* MS: I have in r1 physical address where stack is */
         /* save registers */
 /* MS: Make room on the stack -> activation record */
         addik   r1, r1, -STATE_SAVE_SIZE;
-/* MS: store return registers separately because
- * this macros is use for others exceptions */
-        swi     r3, r1, PTO + PT_R3;
-        swi     r4, r1, PTO + PT_R4;
         SAVE_REGS
-        /* MS: store mode */
-        addi    r11, r0, 1; /* MS: Was in kernel-mode. */
-        swi     r11, r1, PTO + PT_MODE; /* MS: and save it */
         brid    2f;
-        nop; /* MS: Fill delay slot */
-
+        swi     r1, r1, PTO + PT_MODE; /* 0 - user mode, 1 - kernel mode */
 1:
 /* User-mode state save. */
-/* MS: restore r11 -> FIXME move before SAVE_REG */
-        lwi     r11, r0, TOPHYS(PER_CPU(R11_SAVE));
  /* MS: get the saved current */
         lwi     r1, r0, TOPHYS(PER_CPU(CURRENT_SAVE));
         tophys(r1,r1);
@@ -774,27 +665,18 @@ C_ENTRY(_interrupt):
         tophys(r1,r1);
         /* save registers */
         addik   r1, r1, -STATE_SAVE_SIZE;
-        swi     r3, r1, PTO+PT_R3;
-        swi     r4, r1, PTO+PT_R4;
         SAVE_REGS
         /* calculate mode */
         swi     r0, r1, PTO + PT_MODE;
         lwi     r11, r0, TOPHYS(PER_CPU(ENTRY_SP));
         swi     r11, r1, PTO+PT_R1;
-        /* setup kernel mode to KM */
-        addi    r11, r0, 1;
-        swi     r11, r0, TOPHYS(PER_CPU(KM));
-
+        clear_ums;
 2:
         lwi     CURRENT_TASK, r0, TOPHYS(PER_CPU(CURRENT_SAVE));
-        swi     r0, r1, PTO + PT_R0;
         tovirt(r1,r1)
-        la      r5, r1, PTO;
-        set_vms;
-        la      r11, r0, do_IRQ;
-        la      r15, r0, irq_call;
-irq_call:rtbd   r11, 0;
-        nop;
+        addik   r15, r0, irq_call;
+irq_call:rtbd   r0, do_IRQ;
+        addik   r5, r1, PTO;
 
 /* MS: we are in virtual mode */
 ret_from_irq:
@@ -815,7 +697,7 @@ ret_from_irq:
         beqid   r11, no_intr_resched
 /* Handle a signal return; Pending signals should be in r18. */
         addi    r7, r0, 0; /* Arg 3: int in_syscall */
-        la      r5, r1, PTO; /* Arg 1: struct pt_regs *regs */
+        addik   r5, r1, PTO; /* Arg 1: struct pt_regs *regs */
         bralid  r15, do_signal; /* Handle any signals */
         add     r6, r0, r0; /* Arg 2: sigset_t *oldset */
 
@@ -823,12 +705,9 @@ ret_from_irq:
 no_intr_resched:
     /* Disable interrupts, we are now committed to the state restore */
         disable_irq
-        swi     r0, r0, PER_CPU(KM); /* MS: Now officially in user state. */
         swi     CURRENT_TASK, r0, PER_CPU(CURRENT_SAVE);
         VM_OFF;
         tophys(r1,r1);
-        lwi     r3, r1, PTO + PT_R3; /* MS: restore saved r3, r4 registers */
-        lwi     r4, r1, PTO + PT_R4;
         RESTORE_REGS
         addik   r1, r1, STATE_SAVE_SIZE /* MS: Clean up stack space. */
         lwi     r1, r1, PT_R1 - PT_SIZE;
@@ -857,8 +736,6 @@ restore:
 #endif
         VM_OFF /* MS: turn off MMU */
         tophys(r1,r1)
-        lwi     r3, r1, PTO + PT_R3; /* MS: restore saved r3, r4 registers */
-        lwi     r4, r1, PTO + PT_R4;
         RESTORE_REGS
         addik   r1, r1, STATE_SAVE_SIZE /* MS: Clean up stack space. */
         tovirt(r1,r1);
@@ -868,86 +745,91 @@ IRQ_return: /* MS: Make global symbol for debugging */
         nop
 
 /*
- * `Debug' trap
- *  We enter dbtrap in "BIP" (breakpoint) mode.
- *  So we exit the breakpoint mode with an 'rtbd' and proceed with the
- *  original dbtrap.
- *  however, wait to save state first
+ * Debug trap for KGDB. Enter to _debug_exception by brki r16, 0x18
+ * and call handling function with saved pt_regs
  */
 C_ENTRY(_debug_exception):
         /* BIP bit is set on entry, no interrupts can occur */
         swi     r1, r0, TOPHYS(PER_CPU(ENTRY_SP))
 
-        swi     r11, r0, TOPHYS(r0_ram + PTO + PT_R11); /* Save r11 */
-        set_bip;        /*equalize initial state for all possible entries*/
-        clear_eip;
-        enable_irq;
-        lwi     r11, r0, TOPHYS(PER_CPU(KM));/* See if already in kernel mode.*/
-        beqi    r11, 1f;                /* Jump ahead if coming from user */
-        /* Kernel-mode state save.  */
-        lwi     r11, r0, TOPHYS(PER_CPU(ENTRY_SP)); /* Reload kernel stack-ptr*/
-        tophys(r1,r11);
-        swi     r11, r1, (PT_R1-PT_SIZE); /* Save original SP. */
-        lwi     r11, r0, TOPHYS(r0_ram + PTO + PT_R11); /* restore r11 */
+        mfs     r1, rmsr
+        nop
+        andi    r1, r1, MSR_UMS
+        bnei    r1, 1f
+/* MS: Kernel-mode state save - kgdb */
+        lwi     r1, r0, TOPHYS(PER_CPU(ENTRY_SP)); /* Reload kernel stack-ptr*/
 
-        addik   r1, r1, -STATE_SAVE_SIZE; /* Make room on the stack.  */
-        swi     r3, r1, PTO + PT_R3;
-        swi     r4, r1, PTO + PT_R4;
+        /* BIP bit is set on entry, no interrupts can occur */
+        addik   r1, r1, CONFIG_KERNEL_BASE_ADDR - CONFIG_KERNEL_START - STATE_SAVE_SIZE;
         SAVE_REGS;
+        /* save all regs to pt_reg structure */
+        swi     r0, r1, PTO+PT_R0;      /* R0 must be saved too */
+        swi     r14, r1, PTO+PT_R14     /* rewrite saved R14 value */
+        swi     r16, r1, PTO+PT_R16
+        swi     r16, r1, PTO+PT_PC; /* PC and r16 are the same */
+        swi     r17, r1, PTO+PT_R17
+        /* save special purpose registers to pt_regs */
+        mfs     r11, rear;
+        swi     r11, r1, PTO+PT_EAR;
+        mfs     r11, resr;
+        swi     r11, r1, PTO+PT_ESR;
+        mfs     r11, rfsr;
+        swi     r11, r1, PTO+PT_FSR;
+
+        /* stack pointer is in physical address at it is decrease
+         * by STATE_SAVE_SIZE but we need to get correct R1 value */
+        addik   r11, r1, CONFIG_KERNEL_START - CONFIG_KERNEL_BASE_ADDR + STATE_SAVE_SIZE;
+        swi     r11, r1, PTO+PT_R1
+        /* MS: r31 - current pointer isn't changed */
+        tovirt(r1,r1)
+#ifdef CONFIG_KGDB
+        addi    r5, r1, PTO /* pass pt_reg address as the first arg */
+        la      r15, r0, dbtrap_call; /* return address */
+        rtbd    r0, microblaze_kgdb_break
+        nop;
+#endif
+        /* MS: Place handler for brki from kernel space if KGDB is OFF.
+         * It is very unlikely that another brki instruction is called. */
+        bri 0
 
-        addi    r11, r0, 1;             /* Was in kernel-mode.  */
-        swi     r11, r1, PTO + PT_MODE;
-        brid    2f;
-        nop;                            /* Fill delay slot */
-1:      /* User-mode state save.  */
-        lwi     r11, r0, TOPHYS(r0_ram + PTO + PT_R11); /* restore r11 */
-        lwi     r1, r0, TOPHYS(PER_CPU(CURRENT_SAVE)); /* get saved current */
+/* MS: User-mode state save - gdb */
+1:      lwi     r1, r0, TOPHYS(PER_CPU(CURRENT_SAVE)); /* get saved current */
         tophys(r1,r1);
         lwi     r1, r1, TS_THREAD_INFO; /* get the thread info */
         addik   r1, r1, THREAD_SIZE;    /* calculate kernel stack pointer */
         tophys(r1,r1);
 
         addik   r1, r1, -STATE_SAVE_SIZE; /* Make room on the stack.  */
-        swi     r3, r1, PTO + PT_R3;
-        swi     r4, r1, PTO + PT_R4;
         SAVE_REGS;
-
-        swi     r0, r1, PTO+PT_MODE; /* Was in user-mode.  */
+        swi     r17, r1, PTO+PT_R17;
+        swi     r16, r1, PTO+PT_R16;
+        swi     r16, r1, PTO+PT_PC;     /* Save LP */
+        swi     r0, r1, PTO + PT_MODE; /* Was in user-mode.  */
         lwi     r11, r0, TOPHYS(PER_CPU(ENTRY_SP));
         swi     r11, r1, PTO+PT_R1; /* Store user SP.  */
-        addi    r11, r0, 1;
-        swi     r11, r0, TOPHYS(PER_CPU(KM));   /* Now we're in kernel-mode.  */
-2:      lwi     CURRENT_TASK, r0, TOPHYS(PER_CPU(CURRENT_SAVE));
-        /* Save away the syscall number.  */
-        swi     r0, r1, PTO+PT_R0;
+        lwi     CURRENT_TASK, r0, TOPHYS(PER_CPU(CURRENT_SAVE));
         tovirt(r1,r1)
-
-        addi    r5, r0, SIGTRAP              /* send the trap signal */
-        add     r6, r0, CURRENT_TASK; /* Get current task ptr into r11 */
-        addk    r7, r0, r0                   /* 3rd param zero */
-
         set_vms;
-        la      r11, r0, send_sig;
-        la      r15, r0, dbtrap_call;
-dbtrap_call:    rtbd    r11, 0;
-        nop;
+        addik   r5, r1, PTO;
+        addik   r15, r0, dbtrap_call;
+dbtrap_call: /* Return point for kernel/user entry + 8 because of rtsd r15, 8 */
+        rtbd    r0, sw_exception
+        nop
 
-        set_bip;                        /*  Ints masked for state restore*/
-        lwi     r11, r1, PTO+PT_MODE;
+        /* MS: The first instruction for the second part of the gdb/kgdb */
+        set_bip; /* Ints masked for state restore */
+        lwi     r11, r1, PTO + PT_MODE;
         bnei    r11, 2f;
-
+/* MS: Return to user space - gdb */
         /* Get current task ptr into r11 */
         lwi     r11, CURRENT_TASK, TS_THREAD_INFO;      /* get thread info */
         lwi     r11, r11, TI_FLAGS;     /* get flags in thread info */
         andi    r11, r11, _TIF_NEED_RESCHED;
         beqi    r11, 5f;
 
-/* Call the scheduler before returning from a syscall/trap. */
-
+        /* Call the scheduler before returning from a syscall/trap. */
         bralid  r15, schedule;  /* Call scheduler */
         nop;                            /* delay slot */
-        /* XXX Is PT_DTRACE handling needed here? */
-        /* XXX m68knommu also checks TASK_STATE & TASK_COUNTER here.  */
 
         /* Maybe handle a signal */
 5:      lwi     r11, CURRENT_TASK, TS_THREAD_INFO;      /* get thread info */
@@ -955,54 +837,40 @@ dbtrap_call:	rtbd	r11, 0;
         andi    r11, r11, _TIF_SIGPENDING;
         beqi    r11, 1f;                /* Signals to handle, handle them */
 
-/* Handle a signal return; Pending signals should be in r18.  */
-        /* Not all registers are saved by the normal trap/interrupt entry
-           points (for instance, call-saved registers (because the normal
-           C-compiler calling sequence in the kernel makes sure they're
-           preserved), and call-clobbered registers in the case of
-           traps), but signal handlers may want to examine or change the
-           complete register state.  Here we save anything not saved by
-           the normal entry sequence, so that it may be safely restored
-           (in a possibly modified form) after do_signal returns.  */
-
-        la      r5, r1, PTO;            /* Arg 1: struct pt_regs *regs */
+        addik   r5, r1, PTO;            /* Arg 1: struct pt_regs *regs */
         addi  r7, r0, 0;        /* Arg 3: int in_syscall */
         bralid  r15, do_signal; /* Handle any signals */
         add     r6, r0, r0;             /* Arg 2: sigset_t *oldset */
 
-
 /* Finally, return to user state.  */
-1:      swi     r0, r0, PER_CPU(KM);    /* Now officially in user state. */
-        swi     CURRENT_TASK, r0, PER_CPU(CURRENT_SAVE); /* save current */
+1:      swi     CURRENT_TASK, r0, PER_CPU(CURRENT_SAVE); /* save current */
         VM_OFF;
         tophys(r1,r1);
-
-        lwi     r3, r1, PTO+PT_R3; /* restore saved r3, r4 registers */
-        lwi     r4, r1, PTO+PT_R4;
+        /* MS: Restore all regs */
         RESTORE_REGS
-        addik   r1, r1, STATE_SAVE_SIZE         /* Clean up stack space.  */
-
-
-        lwi     r1, r1, PT_R1 - PT_SIZE;
-                                        /* Restore user stack pointer. */
-        bri     6f;
+        lwi     r17, r1, PTO+PT_R17;
+        lwi     r16, r1, PTO+PT_R16;
+        addik   r1, r1, STATE_SAVE_SIZE  /* Clean up stack space */
+        lwi     r1, r1, PT_R1 - PT_SIZE; /* Restore user stack pointer */
+DBTRAP_return_user: /* MS: Make global symbol for debugging */
+        rtbd    r16, 0; /* MS: Instructions to return from a debug trap */
+        nop;
 
-/* Return to kernel state.  */
+/* MS: Return to kernel state - kgdb */
 2:      VM_OFF;
         tophys(r1,r1);
-        lwi     r3, r1, PTO+PT_R3; /* restore saved r3, r4 registers */
-        lwi     r4, r1, PTO+PT_R4;
+        /* MS: Restore all regs */
         RESTORE_REGS
-        addik   r1, r1, STATE_SAVE_SIZE         /* Clean up stack space.  */
-
+        lwi     r14, r1, PTO+PT_R14;
+        lwi     r16, r1, PTO+PT_PC;
+        lwi     r17, r1, PTO+PT_R17;
+        addik   r1, r1, STATE_SAVE_SIZE; /* MS: Clean up stack space */
         tovirt(r1,r1);
-6:
-DBTRAP_return:          /* Make global symbol for debugging */
-        rtbd    r14, 0; /* Instructions to return from an IRQ */
+DBTRAP_return_kernel: /* MS: Make global symbol for debugging */
+        rtbd    r16, 0; /* MS: Instructions to return from a debug trap */
         nop;
 
 
-
 ENTRY(_switch_to)
         /* prepare return value */
         addk    r3, r0, CURRENT_TASK
@@ -1037,16 +905,12 @@ ENTRY(_switch_to)
         swi     r30, r11, CC_R30
         /* special purpose registers */
         mfs     r12, rmsr
-        nop
         swi     r12, r11, CC_MSR
         mfs     r12, rear
-        nop
         swi     r12, r11, CC_EAR
         mfs     r12, resr
-        nop
         swi     r12, r11, CC_ESR
         mfs     r12, rfsr
-        nop
         swi     r12, r11, CC_FSR
 
         /* update r31, the current-give me pointer to task which will be next */
@@ -1085,10 +949,8 @@ ENTRY(_switch_to)
         /* special purpose registers */
         lwi     r12, r11, CC_FSR
         mts     rfsr, r12
-        nop
         lwi     r12, r11, CC_MSR
         mts     rmsr, r12
-        nop
 
         rtsd    r15, 8
         nop
@@ -1096,15 +958,6 @@ ENTRY(_switch_to)
 ENTRY(_reset)
         brai    0x70; /* Jump back to FS-boot */
 
-ENTRY(_break)
-        mfs     r5, rmsr
-        nop
-        swi     r5, r0, 0x250 + TOPHYS(r0_ram)
-        mfs     r5, resr
-        nop
-        swi     r5, r0, 0x254 + TOPHYS(r0_ram)
-        bri     0
-
         /* These are compiled and loaded into high memory, then
          * copied into place in mach_early_setup */
         .section        .init.ivt, "ax"
@@ -1116,14 +969,38 @@ ENTRY(_break)
         nop
         brai    TOPHYS(_user_exception); /* syscall handler */
         brai    TOPHYS(_interrupt);     /* Interrupt handler */
-        brai    TOPHYS(_break);         /* nmi trap handler */
+        brai    TOPHYS(_debug_exception);       /* debug trap handler */
         brai    TOPHYS(_hw_exception_handler);  /* HW exception handler */
 
-        .org    0x60
-        brai    TOPHYS(_debug_exception);       /* debug trap handler*/
-
 .section .rodata,"a"
 #include "syscall_table.S"
 
 syscall_table_size=(.-sys_call_table)
 
+type_SYSCALL:
+        .ascii "SYSCALL\0"
+type_IRQ:
+        .ascii "IRQ\0"
+type_IRQ_PREEMPT:
+        .ascii "IRQ (PREEMPTED)\0"
+type_SYSCALL_PREEMPT:
+        .ascii " SYSCALL (PREEMPTED)\0"
+
+        /*
+         * Trap decoding for stack unwinder
+         * Tuples are (start addr, end addr, string)
+         * If return address lies on [start addr, end addr],
+         * unwinder displays 'string'
+         */
+
+        .align 4
+.global microblaze_trap_handlers
+microblaze_trap_handlers:
+        /* Exact matches come first */
+        .word ret_from_trap; .word ret_from_trap   ; .word type_SYSCALL
+        .word ret_from_irq ; .word ret_from_irq    ; .word type_IRQ
+        /* Fuzzy matches go here */
+        .word ret_from_irq ; .word no_intr_resched ; .word type_IRQ_PREEMPT
+        .word ret_from_trap; .word TRAP_return     ; .word type_SYSCALL_PREEMPT
+        /* End of table */
+        .word 0               ; .word 0               ; .word 0
diff --git a/arch/microblaze/kernel/exceptions.c b/arch/microblaze/kernel/exceptions.c
index 02cbdfe5aa8d..b98ee8d0c1cd 100644
--- a/arch/microblaze/kernel/exceptions.c
+++ b/arch/microblaze/kernel/exceptions.c
@@ -48,12 +48,17 @@ void die(const char *str, struct pt_regs *fp, long err)
         do_exit(err);
 }
 
+/* for user application debugging */
+void sw_exception(struct pt_regs *regs)
+{
+        _exception(SIGTRAP, regs, TRAP_BRKPT, regs->r16);
+}
+
 void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
 {
         siginfo_t info;
 
         if (kernel_mode(regs)) {
-                debugger(regs);
                 die("Exception in kernel mode", regs, signr);
         }
         info.si_signo = signr;
@@ -143,7 +148,7 @@ asmlinkage void full_exception(struct pt_regs *regs, unsigned int type,
 #ifdef CONFIG_MMU
         case MICROBLAZE_PRIVILEGED_EXCEPTION:
                 pr_debug(KERN_WARNING "Privileged exception\n");
-                /* "brk r0,r0" - used as debug breakpoint */
+                /* "brk r0,r0" - used as debug breakpoint - old toolchain */
                 if (get_user(code, (unsigned long *)regs->pc) == 0
                         && code == 0x980c0000) {
                         _exception(SIGTRAP, regs, TRAP_BRKPT, addr);
diff --git a/arch/microblaze/kernel/head.S b/arch/microblaze/kernel/head.S
index 1bf739888260..42434008209e 100644
--- a/arch/microblaze/kernel/head.S
+++ b/arch/microblaze/kernel/head.S
@@ -43,10 +43,10 @@
 .global empty_zero_page
 .align 12
 empty_zero_page:
-        .space  4096
+        .space  PAGE_SIZE
 .global swapper_pg_dir
 swapper_pg_dir:
-        .space  4096
+        .space  PAGE_SIZE
 
 #endif /* CONFIG_MMU */
 
diff --git a/arch/microblaze/kernel/hw_exception_handler.S b/arch/microblaze/kernel/hw_exception_handler.S
index 995a2123635b..781195438ee6 100644
--- a/arch/microblaze/kernel/hw_exception_handler.S
+++ b/arch/microblaze/kernel/hw_exception_handler.S
@@ -78,9 +78,6 @@
 #include <asm/asm-offsets.h>
 
 /* Helpful Macros */
-#ifndef CONFIG_MMU
-#define EX_HANDLER_STACK_SIZ    (4*19)
-#endif
 #define NUM_TO_REG(num)         r ## num
 
 #ifdef CONFIG_MMU
@@ -988,6 +985,7 @@ ex_unaligned_fixup:
 .end _unaligned_data_exception
 #endif /* CONFIG_MMU */
 
+.global ex_handler_unhandled
 ex_handler_unhandled:
 /* FIXME add handle function for unhandled exception - dump register */
         bri 0
diff --git a/arch/microblaze/kernel/irq.c b/arch/microblaze/kernel/irq.c
index 8f120aca123d..598f1fd61c89 100644
--- a/arch/microblaze/kernel/irq.c
+++ b/arch/microblaze/kernel/irq.c
@@ -37,6 +37,7 @@ void __irq_entry do_IRQ(struct pt_regs *regs)
 {
         unsigned int irq;
         struct pt_regs *old_regs = set_irq_regs(regs);
+        trace_hardirqs_off();
 
         irq_enter();
         irq = get_irq(regs);
@@ -53,6 +54,7 @@ next_irq:
 
         irq_exit();
         set_irq_regs(old_regs);
+        trace_hardirqs_on();
 }
 
 int show_interrupts(struct seq_file *p, void *v)
diff --git a/arch/microblaze/kernel/kgdb.c b/arch/microblaze/kernel/kgdb.c
new file mode 100644
index 000000000000..bfc006b7f2d8
--- /dev/null
+++ b/arch/microblaze/kernel/kgdb.c
@@ -0,0 +1,147 @@
+/*
+ * Microblaze KGDB support
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/kgdb.h>
+#include <linux/kdebug.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <asm/cacheflush.h>
+#include <asm/asm-offsets.h>
+#include <asm/pvr.h>
+
+#define GDB_REG         0
+#define GDB_PC          32
+#define GDB_MSR         33
+#define GDB_EAR         34
+#define GDB_ESR         35
+#define GDB_FSR         36
+#define GDB_BTR         37
+#define GDB_PVR         38
+#define GDB_REDR        50
+#define GDB_RPID        51
+#define GDB_RZPR        52
+#define GDB_RTLBX       53
+#define GDB_RTLBSX      54 /* mfs can't read it */
+#define GDB_RTLBLO      55
+#define GDB_RTLBHI      56
+
+/* keep pvr separately because it is unchangeble */
+struct pvr_s pvr;
+
+void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs)
+{
+        int i;
+        unsigned long *pt_regb = (unsigned long *)regs;
+        int temp;
+        /* registers r0 - r31, pc, msr, ear, esr, fsr + do not save pt_mode */
+        for (i = 0; i < (sizeof(struct pt_regs) / 4) - 1; i++)
+                gdb_regs[i] = pt_regb[i];
+
+        /* Branch target register can't be changed */
+        __asm__ __volatile__ ("mfs %0, rbtr;" : "=r"(temp) : );
+        gdb_regs[GDB_BTR] = temp;
+
+        /* pvr part  - we have 11 pvr regs */
+        for (i = 0; i < sizeof(struct pvr_s)/4; i++)
+                gdb_regs[GDB_PVR + i] = pvr.pvr[i];
+
+        /* read special registers - can't be changed */
+        __asm__ __volatile__ ("mfs %0, redr;" : "=r"(temp) : );
+        gdb_regs[GDB_REDR] = temp;
+        __asm__ __volatile__ ("mfs %0, rpid;" : "=r"(temp) : );
+        gdb_regs[GDB_RPID] = temp;
+        __asm__ __volatile__ ("mfs %0, rzpr;" : "=r"(temp) : );
+        gdb_regs[GDB_RZPR] = temp;
+        __asm__ __volatile__ ("mfs %0, rtlbx;" : "=r"(temp) : );
+        gdb_regs[GDB_RTLBX] = temp;
+        __asm__ __volatile__ ("mfs %0, rtlblo;" : "=r"(temp) : );
+        gdb_regs[GDB_RTLBLO] = temp;
+        __asm__ __volatile__ ("mfs %0, rtlbhi;" : "=r"(temp) : );
+        gdb_regs[GDB_RTLBHI] = temp;
+}
+
+void gdb_regs_to_pt_regs(unsigned long *gdb_regs, struct pt_regs *regs)
+{
+        int i;
+        unsigned long *pt_regb = (unsigned long *)regs;
+
+        /* pt_regs and gdb_regs have the same 37 values.
+         * The rest of gdb_regs are unused and can't be changed.
+         * r0 register value can't be changed too. */
+        for (i = 1; i < (sizeof(struct pt_regs) / 4) - 1; i++)
+                pt_regb[i] = gdb_regs[i];
+}
+
+void microblaze_kgdb_break(struct pt_regs *regs)
+{
+        if (kgdb_handle_exception(1, SIGTRAP, 0, regs) != 0)
+                return 0;
+
+        /* Jump over the first arch_kgdb_breakpoint which is barrier to
+         * get kgdb work. The same solution is used for powerpc */
+        if (*(u32 *) (regs->pc) == *(u32 *) (&arch_kgdb_ops.gdb_bpt_instr))
+                regs->pc += BREAK_INSTR_SIZE;
+}
+
+/* untested */
+void sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *p)
+{
+        int i;
+        unsigned long *pt_regb = (unsigned long *)(p->thread.regs);
+
+        /* registers r0 - r31, pc, msr, ear, esr, fsr + do not save pt_mode */
+        for (i = 0; i < (sizeof(struct pt_regs) / 4) - 1; i++)
+                gdb_regs[i] = pt_regb[i];
+
+        /* pvr part  - we have 11 pvr regs */
+        for (i = 0; i < sizeof(struct pvr_s)/4; i++)
+                gdb_regs[GDB_PVR + i] = pvr.pvr[i];
+}
+
+void kgdb_arch_set_pc(struct pt_regs *regs, unsigned long ip)
+{
+        regs->pc = ip;
+}
+
+int kgdb_arch_handle_exception(int vector, int signo, int err_code,
+                               char *remcom_in_buffer, char *remcom_out_buffer,
+                               struct pt_regs *regs)
+{
+        char *ptr;
+        unsigned long address;
+        int cpu = smp_processor_id();
+
+        switch (remcom_in_buffer[0]) {
+        case 'c':
+                /* handle the optional parameter */
+                ptr = &remcom_in_buffer[1];
+                if (kgdb_hex2long(&ptr, &address))
+                        regs->pc = address;
+
+                return 0;
+        }
+        return -1; /* this means that we do not want to exit from the handler */
+}
+
+int kgdb_arch_init(void)
+{
+        get_pvr(&pvr); /* Fill PVR structure */
+        return 0;
+}
+
+void kgdb_arch_exit(void)
+{
+        /* Nothing to do */
+}
+
+/*
+ * Global data
+ */
+struct kgdb_arch arch_kgdb_ops = {
+        .gdb_bpt_instr = {0xba, 0x0c, 0x00, 0x18}, /* brki r16, 0x18 */
+};
diff --git a/arch/microblaze/kernel/misc.S b/arch/microblaze/kernel/misc.S
index 0fb5fc6c1fc2..206da3da361f 100644
--- a/arch/microblaze/kernel/misc.S
+++ b/arch/microblaze/kernel/misc.S
@@ -76,7 +76,7 @@ early_console_reg_tlb_alloc:
          * the UARTs nice and early.  We use a 4k real==virtual mapping.
          */
         ori     r4, r0, MICROBLAZE_TLB_SIZE - 1
-        mts     rtlbx, r4 /* TLB slot 2 */
+        mts     rtlbx, r4 /* TLB slot 63 */
 
         or      r4,r5,r0
         andi    r4,r4,0xfffff000
diff --git a/arch/microblaze/kernel/process.c b/arch/microblaze/kernel/process.c
index 09bed44dfcd3..ba7c4b16ed35 100644
--- a/arch/microblaze/kernel/process.c
+++ b/arch/microblaze/kernel/process.c
@@ -76,8 +76,11 @@ __setup("hlt", hlt_setup);
 void default_idle(void)
 {
         if (likely(hlt_counter)) {
-                while (!need_resched())
-                        cpu_relax();
+                local_irq_disable();
+                stop_critical_timings();
+                cpu_relax();
+                start_critical_timings();
+                local_irq_enable();
         } else {
                 clear_thread_flag(TIF_POLLING_NRFLAG);
                 smp_mb__after_clear_bit();
diff --git a/arch/microblaze/kernel/ptrace.c b/arch/microblaze/kernel/ptrace.c
index a4a7770c6140..dc03ffc8174a 100644
--- a/arch/microblaze/kernel/ptrace.c
+++ b/arch/microblaze/kernel/ptrace.c
@@ -38,6 +38,8 @@
 #include <asm/processor.h>
 #include <linux/uaccess.h>
 #include <asm/asm-offsets.h>
+#include <asm/cacheflush.h>
+#include <asm/io.h>
 
 /* Returns the address where the register at REG_OFFS in P is stashed away. */
 static microblaze_reg_t *reg_save_addr(unsigned reg_offs,
@@ -101,8 +103,21 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
                         microblaze_reg_t *reg_addr = reg_save_addr(addr, child);
                         if (request == PTRACE_PEEKUSR)
                                 val = *reg_addr;
-                        else
+                        else {
+#if 1
                                 *reg_addr = data;
+#else
+                                /* MS potential problem on WB system
+                                 * Be aware that reg_addr is virtual address
+                                 * virt_to_phys conversion is necessary.
+                                 * This could be sensible solution.
+                                 */
+                                u32 paddr = virt_to_phys((u32)reg_addr);
+                                invalidate_icache_range(paddr, paddr + 4);
+                                *reg_addr = data;
+                                flush_dcache_range(paddr, paddr + 4);
+#endif
+                        }
                 } else
                         rval = -EIO;
 
diff --git a/arch/microblaze/kernel/stacktrace.c b/arch/microblaze/kernel/stacktrace.c
index 123692f22647..84bc6686102c 100644
--- a/arch/microblaze/kernel/stacktrace.c
+++ b/arch/microblaze/kernel/stacktrace.c
@@ -14,52 +14,18 @@
 #include <linux/thread_info.h>
 #include <linux/ptrace.h>
 #include <linux/module.h>
+#include <asm/unwind.h>
 
-/* FIXME initial support */
 void save_stack_trace(struct stack_trace *trace)
 {
-        unsigned long *sp;
-        unsigned long addr;
-        asm("addik %0, r1, 0" : "=r" (sp));
-
-        while (!kstack_end(sp)) {
-                addr = *sp++;
-                if (__kernel_text_address(addr)) {
-                        if (trace->skip > 0)
-                                trace->skip--;
-                        else
-                                trace->entries[trace->nr_entries++] = addr;
-
-                        if (trace->nr_entries >= trace->max_entries)
-                                break;
-                }
-        }
+        /* Exclude our helper functions from the trace*/
+        trace->skip += 2;
+        microblaze_unwind(NULL, trace);
 }
 EXPORT_SYMBOL_GPL(save_stack_trace);
 
 void save_stack_trace_tsk(struct task_struct *tsk, struct stack_trace *trace)
 {
-        unsigned int *sp;
-        unsigned long addr;
-
-        struct thread_info *ti = task_thread_info(tsk);
-
-        if (tsk == current)
-                asm("addik %0, r1, 0" : "=r" (sp));
-        else
-                sp = (unsigned int *)ti->cpu_context.r1;
-
-        while (!kstack_end(sp)) {
-                addr = *sp++;
-                if (__kernel_text_address(addr)) {
-                        if (trace->skip > 0)
-                                trace->skip--;
-                        else
-                                trace->entries[trace->nr_entries++] = addr;
-
-                        if (trace->nr_entries >= trace->max_entries)
-                                break;
-                }
-        }
+        microblaze_unwind(tsk, trace);
 }
 EXPORT_SYMBOL_GPL(save_stack_trace_tsk);
diff --git a/arch/microblaze/kernel/timer.c b/arch/microblaze/kernel/timer.c
index ed61b2f17719..b1380ae93ae1 100644
--- a/arch/microblaze/kernel/timer.c
+++ b/arch/microblaze/kernel/timer.c
@@ -28,6 +28,7 @@
 #include <asm/prom.h>
 #include <asm/irq.h>
 #include <asm/system.h>
+#include <linux/cnt32_to_63.h>
 
 #ifdef CONFIG_SELFMOD_TIMER
 #include <asm/selfmod.h>
@@ -135,7 +136,7 @@ static void microblaze_timer_set_mode(enum clock_event_mode mode,
 static struct clock_event_device clockevent_microblaze_timer = {
         .name           = "microblaze_clockevent",
         .features       = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
-        .shift          = 24,
+        .shift          = 8,
         .rating         = 300,
         .set_next_event = microblaze_timer_set_next_event,
         .set_mode       = microblaze_timer_set_mode,
@@ -195,7 +196,7 @@ static cycle_t microblaze_cc_read(const struct cyclecounter *cc)
 static struct cyclecounter microblaze_cc = {
         .read = microblaze_cc_read,
         .mask = CLOCKSOURCE_MASK(32),
-        .shift = 24,
+        .shift = 8,
 };
 
 int __init init_microblaze_timecounter(void)
@@ -213,7 +214,7 @@ static struct clocksource clocksource_microblaze = {
         .rating         = 300,
         .read           = microblaze_read,
         .mask           = CLOCKSOURCE_MASK(32),
-        .shift          = 24, /* I can shift it */
+        .shift          = 8, /* I can shift it */
         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
@@ -235,6 +236,12 @@ static int __init microblaze_clocksource_init(void)
         return 0;
 }
 
+/*
+ * We have to protect accesses before timer initialization
+ * and return 0 for sched_clock function below.
+ */
+static int timer_initialized;
+
 void __init time_init(void)
 {
         u32 irq, i = 0;
@@ -289,4 +296,15 @@ void __init time_init(void)
 #endif
         microblaze_clocksource_init();
         microblaze_clockevent_init();
+        timer_initialized = 1;
+}
+
+unsigned long long notrace sched_clock(void)
+{
+        if (timer_initialized) {
+                struct clocksource *cs = &clocksource_microblaze;
+                cycle_t cyc = cnt32_to_63(cs->read(NULL));
+                return clocksource_cyc2ns(cyc, cs->mult, cs->shift);
+        }
+        return 0;
 }
diff --git a/arch/microblaze/kernel/traps.c b/arch/microblaze/kernel/traps.c
index 75e49202a5ed..ba034d421ec2 100644
--- a/arch/microblaze/kernel/traps.c
+++ b/arch/microblaze/kernel/traps.c
@@ -16,13 +16,14 @@
 
 #include <asm/exceptions.h>
 #include <asm/system.h>
+#include <asm/unwind.h>
 
 void trap_init(void)
 {
         __enable_hw_exceptions();
 }
 
-static unsigned long kstack_depth_to_print = 24;
+static unsigned long kstack_depth_to_print;     /* 0 == entire stack */
 
 static int __init kstack_setup(char *s)
 {
@@ -30,31 +31,47 @@ static int __init kstack_setup(char *s)
 }
 __setup("kstack=", kstack_setup);
 
-void show_trace(struct task_struct *task, unsigned long *stack)
+void show_stack(struct task_struct *task, unsigned long *sp)
 {
-        unsigned long addr;
-
-        if (!stack)
-                stack = (unsigned long *)&stack;
+        unsigned long words_to_show;
+        u32 fp = (u32) sp;
+
+        if (fp == 0) {
+                if (task) {
+                        fp = ((struct thread_info *)
+                                (task->stack))->cpu_context.r1;
+                } else {
+                        /* Pick up caller of dump_stack() */
+                        fp = (u32)&sp - 8;
+                }
+        }
 
-        printk(KERN_NOTICE "Call Trace: ");
-#ifdef CONFIG_KALLSYMS
-        printk(KERN_NOTICE "\n");
-#endif
-        while (!kstack_end(stack)) {
-                addr = *stack++;
-                /*
-                 * If the address is either in the text segment of the
-                 * kernel, or in the region which contains vmalloc'ed
-                 * memory, it *may* be the address of a calling
-                 * routine; if so, print it so that someone tracing
-                 * down the cause of the crash will be able to figure
-                 * out the call path that was taken.
-                 */
-                if (kernel_text_address(addr))
-                        print_ip_sym(addr);
+        words_to_show = (THREAD_SIZE - (fp & (THREAD_SIZE - 1))) >> 2;
+        if (kstack_depth_to_print && (words_to_show > kstack_depth_to_print))
+                words_to_show = kstack_depth_to_print;
+
+        pr_info("Kernel Stack:\n");
+
+        /*
+         * Make the first line an 'odd' size if necessary to get
+         * remaining lines to start at an address multiple of 0x10
+         */
+        if (fp & 0xF) {
+                unsigned long line1_words = (0x10 - (fp & 0xF)) >> 2;
+                if (line1_words < words_to_show) {
+                        print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS, 32,
+                                       4, (void *)fp, line1_words << 2, 0);
+                        fp += line1_words << 2;
+                        words_to_show -= line1_words;
+                }
         }
-        printk(KERN_NOTICE "\n");
+        print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS, 32, 4, (void *)fp,
+                       words_to_show << 2, 0);
+        printk(KERN_INFO "\n\n");
+
+        pr_info("Call Trace:\n");
+        microblaze_unwind(task, NULL);
+        pr_info("\n");
 
         if (!task)
                 task = current;
@@ -62,34 +79,6 @@ void show_trace(struct task_struct *task, unsigned long *stack)
         debug_show_held_locks(task);
 }
 
-void show_stack(struct task_struct *task, unsigned long *sp)
-{
-        unsigned long *stack;
-        int i;
-
-        if (sp == NULL) {
-                if (task)
-                        sp = (unsigned long *) ((struct thread_info *)
-                                                (task->stack))->cpu_context.r1;
-                else
-                        sp = (unsigned long *)&sp;
-        }
-
-        stack = sp;
-
-        printk(KERN_INFO "\nStack:\n  ");
-
-        for (i = 0; i < kstack_depth_to_print; i++) {
-                if (kstack_end(sp))
-                        break;
-                if (i && ((i % 8) == 0))
-                        printk("\n  ");
-                printk("%08lx ", *sp++);
-        }
-        printk("\n");
-        show_trace(task, stack);
-}
-
 void dump_stack(void)
 {
         show_stack(NULL, NULL);
diff --git a/arch/microblaze/kernel/unwind.c b/arch/microblaze/kernel/unwind.c
new file mode 100644
index 000000000000..fefac5c33586
--- /dev/null
+++ b/arch/microblaze/kernel/unwind.c
@@ -0,0 +1,318 @@
+/*
+ * Backtrace support for Microblaze
+ *
+ * Copyright (C) 2010  Digital Design Corporation
+ *
+ * Based on arch/sh/kernel/cpu/sh5/unwind.c code which is:
+ * Copyright (C) 2004  Paul Mundt
+ * Copyright (C) 2004  Richard Curnow
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+/* #define DEBUG 1 */
+#include <linux/kallsyms.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/stacktrace.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/module.h>
+#include <linux/io.h>
+#include <asm/sections.h>
+#include <asm/exceptions.h>
+#include <asm/unwind.h>
+
+struct stack_trace;
+
+/*
+ * On Microblaze, finding the previous stack frame is a little tricky.
+ * At this writing (3/2010), Microblaze does not support CONFIG_FRAME_POINTERS,
+ * and even if it did, gcc (4.1.2) does not store the frame pointer at
+ * a consistent offset within each frame. To determine frame size, it is
+ * necessary to search for the assembly instruction that creates or reclaims
+ * the frame and extract the size from it.
+ *
+ * Microblaze stores the stack pointer in r1, and creates a frame via
+ *
+ *     addik r1, r1, -FRAME_SIZE
+ *
+ * The frame is reclaimed via
+ *
+ *     addik r1, r1, FRAME_SIZE
+ *
+ * Frame creation occurs at or near the top of a function.
+ * Depending on the compiler, reclaim may occur at the end, or before
+ * a mid-function return.
+ *
+ * A stack frame is usually not created in a leaf function.
+ *
+ */
+
+/**
+ * get_frame_size - Extract the stack adjustment from an
+ *                  "addik r1, r1, adjust" instruction
+ * @instr : Microblaze instruction
+ *
+ * Return - Number of stack bytes the instruction reserves or reclaims
+ */
+inline long get_frame_size(unsigned long instr)
+{
+        return abs((s16)(instr & 0xFFFF));
+}
+
+/**
+ * find_frame_creation - Search backward to find the instruction that creates
+ *                       the stack frame (hopefully, for the same function the
+ *                       initial PC is in).
+ * @pc : Program counter at which to begin the search
+ *
+ * Return - PC at which stack frame creation occurs
+ *          NULL if this cannot be found, i.e. a leaf function
+ */
+static unsigned long *find_frame_creation(unsigned long *pc)
+{
+        int i;
+
+        /* NOTE: Distance to search is arbitrary
+         *       250 works well for most things,
+         *       750 picks up things like tcp_recvmsg(),
+         *      1000 needed for fat_fill_super()
+         */
+        for (i = 0; i < 1000; i++, pc--) {
+                unsigned long instr;
+                s16 frame_size;
+
+                if (!kernel_text_address((unsigned long) pc))
+                        return NULL;
+
+                instr = *pc;
+
+                /* addik r1, r1, foo ? */
+                if ((instr & 0xFFFF0000) != 0x30210000)
+                        continue;       /* No */
+
+                frame_size = get_frame_size(instr);
+                if ((frame_size < 8) || (frame_size & 3)) {
+                        pr_debug("    Invalid frame size %d at 0x%p\n",
+                                 frame_size, pc);
+                        return NULL;
+                }
+
+                pr_debug("    Found frame creation at 0x%p, size %d\n", pc,
+                         frame_size);
+                return pc;
+        }
+
+        return NULL;
+}
+
+/**
+ * lookup_prev_stack_frame - Find the stack frame of the previous function.
+ * @fp          : Frame (stack) pointer for current function
+ * @pc          : Program counter within current function
+ * @leaf_return : r15 value within current function. If the current function
+ *                is a leaf, this is the caller's return address.
+ * @pprev_fp    : On exit, set to frame (stack) pointer for previous function
+ * @pprev_pc    : On exit, set to current function caller's return address
+ *
+ * Return - 0 on success, -EINVAL if the previous frame cannot be found
+ */
+static int lookup_prev_stack_frame(unsigned long fp, unsigned long pc,
+                                   unsigned long leaf_return,
+                                   unsigned long *pprev_fp,
+                                   unsigned long *pprev_pc)
+{
+        unsigned long *prologue = NULL;
+
+        /* _switch_to is a special leaf function */
+        if (pc != (unsigned long) &_switch_to)
+                prologue = find_frame_creation((unsigned long *)pc);
+
+        if (prologue) {
+                long frame_size = get_frame_size(*prologue);
+
+                *pprev_fp = fp + frame_size;
+                *pprev_pc = *(unsigned long *)fp;
+        } else {
+                if (!leaf_return)
+                        return -EINVAL;
+                *pprev_pc = leaf_return;
+                *pprev_fp = fp;
+        }
+
+        /* NOTE: don't check kernel_text_address here, to allow display
+         *       of userland return address
+         */
+        return (!*pprev_pc || (*pprev_pc & 3)) ? -EINVAL : 0;
+}
+
+static void microblaze_unwind_inner(struct task_struct *task,
+                                    unsigned long pc, unsigned long fp,
+                                    unsigned long leaf_return,
+                                    struct stack_trace *trace);
+
+/**
+ * unwind_trap - Unwind through a system trap, that stored previous state
+ *               on the stack.
+ */
+#ifdef CONFIG_MMU
+static inline void unwind_trap(struct task_struct *task, unsigned long pc,
+                                unsigned long fp, struct stack_trace *trace)
+{
+        /* To be implemented */
+}
+#else
+static inline void unwind_trap(struct task_struct *task, unsigned long pc,
+                                unsigned long fp, struct stack_trace *trace)
+{
+        const struct pt_regs *regs = (const struct pt_regs *) fp;
+        microblaze_unwind_inner(task, regs->pc, regs->r1, regs->r15, trace);
+}
+#endif
+
+/**
+ * microblaze_unwind_inner - Unwind the stack from the specified point
+ * @task  : Task whose stack we are to unwind (may be NULL)
+ * @pc    : Program counter from which we start unwinding
+ * @fp    : Frame (stack) pointer from which we start unwinding
+ * @leaf_return : Value of r15 at pc. If the function is a leaf, this is
+ *                                the caller's return address.
+ * @trace : Where to store stack backtrace (PC values).
+ *          NULL == print backtrace to kernel log
+ */
+void microblaze_unwind_inner(struct task_struct *task,
+                             unsigned long pc, unsigned long fp,
+                             unsigned long leaf_return,
+                             struct stack_trace *trace)
+{
+        int ofs = 0;
+
+        pr_debug("    Unwinding with PC=%p, FP=%p\n", (void *)pc, (void *)fp);
+        if (!pc || !fp || (pc & 3) || (fp & 3)) {
+                pr_debug("    Invalid state for unwind, aborting\n");
+                return;
+        }
+        for (; pc != 0;) {
+                unsigned long next_fp, next_pc = 0;
+                unsigned long return_to = pc +  2 * sizeof(unsigned long);
+                const struct trap_handler_info *handler =
+                        &microblaze_trap_handlers;
+
+                /* Is previous function the HW exception handler? */
+                if ((return_to >= (unsigned long)&_hw_exception_handler)
+                    &&(return_to < (unsigned long)&ex_handler_unhandled)) {
+                        /*
+                         * HW exception handler doesn't save all registers,
+                         * so we open-code a special case of unwind_trap()
+                         */
+#ifndef CONFIG_MMU
+                        const struct pt_regs *regs =
+                                (const struct pt_regs *) fp;
+#endif
+                        pr_info("HW EXCEPTION\n");
+#ifndef CONFIG_MMU
+                        microblaze_unwind_inner(task, regs->r17 - 4,
+                                                fp + EX_HANDLER_STACK_SIZ,
+                                                regs->r15, trace);
+#endif
+                        return;
+                }
+
+                /* Is previous function a trap handler? */
+                for (; handler->start_addr; ++handler) {
+                        if ((return_to >= handler->start_addr)
+                            && (return_to <= handler->end_addr)) {
+                                if (!trace)
+                                        pr_info("%s\n", handler->trap_name);
+                                unwind_trap(task, pc, fp, trace);
+                                return;
+                        }
+                }
+                pc -= ofs;
+
+                if (trace) {
+#ifdef CONFIG_STACKTRACE
+                        if (trace->skip > 0)
+                                trace->skip--;
+                        else
+                                trace->entries[trace->nr_entries++] = pc;
+
+                        if (trace->nr_entries >= trace->max_entries)
+                                break;
+#endif
+                } else {
+                        /* Have we reached userland? */
+                        if (unlikely(pc == task_pt_regs(task)->pc)) {
+                                pr_info("[<%p>] PID %lu [%s]\n",
+                                        (void *) pc,
+                                        (unsigned long) task->pid,
+                                        task->comm);
+                                break;
+                        } else
+                                print_ip_sym(pc);
+                }
+
+                /* Stop when we reach anything not part of the kernel */
+                if (!kernel_text_address(pc))
+                        break;
+
+                if (lookup_prev_stack_frame(fp, pc, leaf_return, &next_fp,
+                                            &next_pc) == 0) {
+                        ofs = sizeof(unsigned long);
+                        pc = next_pc & ~3;
+                        fp = next_fp;
+                        leaf_return = 0;
+                } else {
+                        pr_debug("    Failed to find previous stack frame\n");
+                        break;
+                }
+
+                pr_debug("    Next PC=%p, next FP=%p\n",
+                         (void *)next_pc, (void *)next_fp);
+        }
+}
+
+/**
+ * microblaze_unwind - Stack unwinder for Microblaze (external entry point)
+ * @task  : Task whose stack we are to unwind (NULL == current)
+ * @trace : Where to store stack backtrace (PC values).
+ *          NULL == print backtrace to kernel log
+ */
+void microblaze_unwind(struct task_struct *task, struct stack_trace *trace)
+{
+        if (task) {
+                if (task == current) {
+                        const struct pt_regs *regs = task_pt_regs(task);
+                        microblaze_unwind_inner(task, regs->pc, regs->r1,
+                                                regs->r15, trace);
+                } else {
+                        struct thread_info *thread_info =
+                                (struct thread_info *)(task->stack);
+                        const struct cpu_context *cpu_context =
+                                &thread_info->cpu_context;
+
+                        microblaze_unwind_inner(task,
+                                                (unsigned long) &_switch_to,
+                                                cpu_context->r1,
+                                                cpu_context->r15, trace);
+                }
+        } else {
+                unsigned long pc, fp;
+
+                __asm__ __volatile__ ("or %0, r1, r0" : "=r" (fp));
+
+                __asm__ __volatile__ (
+                        "brlid %0, 0f;"
+                        "nop;"
+                        "0:"
+                        : "=r" (pc)
+                );
+
+                /* Since we are not a leaf function, use leaf_return = 0 */
+                microblaze_unwind_inner(current, pc, fp, 0, trace);
+        }
+}
+
diff --git a/arch/microblaze/kernel/vmlinux.lds.S b/arch/microblaze/kernel/vmlinux.lds.S
index db72d7124602..a09f2962fbec 100644
--- a/arch/microblaze/kernel/vmlinux.lds.S
+++ b/arch/microblaze/kernel/vmlinux.lds.S
@@ -10,7 +10,7 @@
 
 OUTPUT_FORMAT("elf32-microblaze", "elf32-microblaze", "elf32-microblaze")
 OUTPUT_ARCH(microblaze)
-ENTRY(_start)
+ENTRY(microblaze_start)
 
 #include <asm/page.h>
 #include <asm-generic/vmlinux.lds.h>
@@ -20,7 +20,7 @@ jiffies = jiffies_64 + 4;
 
 SECTIONS {
         . = CONFIG_KERNEL_START;
-        _start = CONFIG_KERNEL_BASE_ADDR;
+        microblaze_start = CONFIG_KERNEL_BASE_ADDR;
         .text : AT(ADDR(.text) - LOAD_OFFSET) {
                 _text = . ;
                 _stext = . ;
@@ -55,7 +55,7 @@ SECTIONS {
          */
         .sdata2 : AT(ADDR(.sdata2) - LOAD_OFFSET) {
                 _ssrw = .;
-                . = ALIGN(4096); /* page aligned when MMU used - origin 0x8 */
+                . = ALIGN(PAGE_SIZE); /* page aligned when MMU used */
                 *(.sdata2)
         . = ALIGN(8);
         _essrw = .;
@@ -70,7 +70,7 @@ SECTIONS {
         /* Reserve some low RAM for r0 based memory references */
         . = ALIGN(0x4) ;
         r0_ram = . ;
-        . = . +  4096;  /* a page should be enough */
+        . = . +  PAGE_SIZE;     /* a page should be enough */
 
         /* Under the microblaze ABI, .sdata and .sbss must be contiguous */
         . = ALIGN(8);
@@ -120,7 +120,7 @@ SECTIONS {
 
         __init_end_before_initramfs = .;
 
-        .init.ramfs ALIGN(4096) : AT(ADDR(.init.ramfs) - LOAD_OFFSET) {
+        .init.ramfs ALIGN(PAGE_SIZE) : AT(ADDR(.init.ramfs) - LOAD_OFFSET) {
                 __initramfs_start = .;
                 *(.init.ramfs)
                 __initramfs_end = .;
@@ -132,11 +132,11 @@ SECTIONS {
  * so that __init_end == __bss_start. This will make image.elf
  * consistent with the image.bin
  */
-                /* . = ALIGN(4096); */
+                /* . = ALIGN(PAGE_SIZE); */
         }
         __init_end = .;
 
-        .bss ALIGN (4096) : AT(ADDR(.bss) - LOAD_OFFSET) {
+        .bss ALIGN (PAGE_SIZE) : AT(ADDR(.bss) - LOAD_OFFSET) {
                 /* page aligned when MMU used */
                 __bss_start = . ;
                         *(.bss*)
@@ -145,7 +145,7 @@ SECTIONS {
                 __bss_stop = . ;
                 _ebss = . ;
         }
-        . = ALIGN(4096);
+        . = ALIGN(PAGE_SIZE);
         _end = .;
 
         DISCARDS
diff --git a/arch/microblaze/mm/fault.c b/arch/microblaze/mm/fault.c
index bab922993185..57bd2a09610c 100644
--- a/arch/microblaze/mm/fault.c
+++ b/arch/microblaze/mm/fault.c
@@ -37,10 +37,6 @@
 #include <linux/uaccess.h>
 #include <asm/exceptions.h>
 
-#if defined(CONFIG_KGDB)
-int debugger_kernel_faults = 1;
-#endif
-
 static unsigned long pte_misses;        /* updated by do_page_fault() */
 static unsigned long pte_errors;        /* updated by do_page_fault() */
 
@@ -81,10 +77,6 @@ void bad_page_fault(struct pt_regs *regs, unsigned long address, int sig)
         }
 
         /* kernel has accessed a bad area */
-#if defined(CONFIG_KGDB)
-        if (debugger_kernel_faults)
-                debugger(regs);
-#endif
         die("kernel access of bad area", regs, sig);
 }
 
@@ -115,13 +107,6 @@ void do_page_fault(struct pt_regs *regs, unsigned long address,
         if ((error_code & 0x13) == 0x13 || (error_code & 0x11) == 0x11)
                 is_write = 0;
 
-#if defined(CONFIG_KGDB)
-        if (debugger_fault_handler && regs->trap == 0x300) {
-                debugger_fault_handler(regs);
-                return;
-        }
-#endif /* CONFIG_KGDB */
-
         if (unlikely(in_atomic() || !mm)) {
                 if (kernel_mode(regs))
                         goto bad_area_nosemaphore;
@@ -226,7 +211,6 @@ good_area:
          * make sure we exit gracefully rather than endlessly redo
          * the fault.
          */
-survive:
         fault = handle_mm_fault(mm, vma, address, is_write ? FAULT_FLAG_WRITE : 0);
         if (unlikely(fault & VM_FAULT_ERROR)) {
                 if (fault & VM_FAULT_OOM)
diff --git a/arch/microblaze/mm/init.c b/arch/microblaze/mm/init.c
index db5934989926..65eb00419d19 100644
--- a/arch/microblaze/mm/init.c
+++ b/arch/microblaze/mm/init.c
@@ -134,13 +134,8 @@ void __init setup_memory(void)
          * for 4GB of memory, using 4kB pages), plus 1 page
          * (in case the address isn't page-aligned).
          */
-#ifndef CONFIG_MMU
-        map_size = init_bootmem_node(NODE_DATA(0), PFN_UP(TOPHYS((u32)klimit)),
-                                        min_low_pfn, max_low_pfn);
-#else
-        map_size = init_bootmem_node(&contig_page_data,
+        map_size = init_bootmem_node(NODE_DATA(0),
                 PFN_UP(TOPHYS((u32)klimit)), min_low_pfn, max_low_pfn);
-#endif
         memblock_reserve(PFN_UP(TOPHYS((u32)klimit)) << PAGE_SHIFT, map_size);
 
         /* free bootmem is whole main memory */
diff --git a/arch/mips/Kbuild b/arch/mips/Kbuild
new file mode 100644
index 000000000000..e322d65f33a4
--- /dev/null
+++ b/arch/mips/Kbuild
@@ -0,0 +1,15 @@
+# Fail on warnings - also for files referenced in subdirs
+# -Werror can be disabled for specific files using:
+# CFLAGS_<file.o> := -Wno-error
+subdir-ccflags-y := -Werror
+
+# platform specific definitions
+include arch/mips/Kbuild.platforms
+obj-y := $(platform-y)
+
+# mips object files
+# The object files are linked as core-y files would be linked
+
+obj-y += kernel/
+obj-y += mm/
+obj-y += math-emu/
diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms
new file mode 100644
index 000000000000..78439b8a83c4
--- /dev/null
+++ b/arch/mips/Kbuild.platforms
@@ -0,0 +1,32 @@
+# All platforms listed in alphabetic order
+
+platforms += alchemy
+platforms += ar7
+platforms += bcm47xx
+platforms += bcm63xx
+platforms += cavium-octeon
+platforms += cobalt
+platforms += dec
+platforms += emma
+platforms += jazz
+platforms += jz4740
+platforms += lasat
+platforms += loongson
+platforms += mipssim
+platforms += mti-malta
+platforms += pmc-sierra
+platforms += pnx833x
+platforms += pnx8550
+platforms += powertv
+platforms += rb532
+platforms += sgi-ip22
+platforms += sgi-ip27
+platforms += sgi-ip32
+platforms += sibyte
+platforms += sni
+platforms += txx9
+platforms += vr41xx
+platforms += wrppmc
+
+# include the platform specific files
+include $(patsubst %, $(srctree)/arch/mips/%/Platform, $(platforms))
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index cdaae942623d..36642df7d5f6 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -10,6 +10,8 @@ config MIPS
         select HAVE_DYNAMIC_FTRACE
         select HAVE_FTRACE_MCOUNT_RECORD
         select HAVE_FUNCTION_GRAPH_TRACER
+        select HAVE_KPROBES
+        select HAVE_KRETPROBES
         select RTC_LIB if !MACH_LOONGSON
 
 mainmenu "Linux/MIPS Kernel Configuration"
@@ -23,8 +25,17 @@ choice
         prompt "System type"
         default SGI_IP22
 
-config MACH_ALCHEMY
+config MIPS_ALCHEMY
         bool "Alchemy processor based machines"
+        select 64BIT_PHYS_ADDR
+        select CEVT_R4K_LIB
+        select CSRC_R4K_LIB
+        select IRQ_CPU
+        select SYS_HAS_CPU_MIPS32_R1
+        select SYS_SUPPORTS_32BIT_KERNEL
+        select SYS_SUPPORTS_APM_EMULATION
+        select GENERIC_GPIO
+        select ARCH_WANT_OPTIONAL_GPIOLIB
         select SYS_SUPPORTS_ZBOOT
 
 config AR7
@@ -62,6 +73,7 @@ config BCM47XX
         select SSB_DRIVER_MIPS
         select SSB_DRIVER_EXTIF
         select SSB_EMBEDDED
+        select SSB_B43_PCI_BRIDGE if PCI
         select SSB_PCICORE_HOSTMODE if PCI
         select GENERIC_GPIO
         select SYS_HAS_EARLY_PRINTK
@@ -162,6 +174,18 @@ config MACH_JAZZ
          Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
          Olivetti M700-10 workstations.
 
+config MACH_JZ4740
+        bool "Ingenic JZ4740 based machines"
+        select SYS_HAS_CPU_MIPS32_R1
+        select SYS_SUPPORTS_32BIT_KERNEL
+        select SYS_SUPPORTS_LITTLE_ENDIAN
+        select DMA_NONCOHERENT
+        select IRQ_CPU
+        select GENERIC_GPIO
+        select ARCH_REQUIRE_GPIOLIB
+        select SYS_HAS_EARLY_PRINTK
+        select HAVE_PWM
+
 config LASAT
         bool "LASAT Networks platforms"
         select CEVT_R4K
@@ -686,6 +710,7 @@ endchoice
 source "arch/mips/alchemy/Kconfig"
 source "arch/mips/bcm63xx/Kconfig"
 source "arch/mips/jazz/Kconfig"
+source "arch/mips/jz4740/Kconfig"
 source "arch/mips/lasat/Kconfig"
 source "arch/mips/pmc-sierra/Kconfig"
 source "arch/mips/powertv/Kconfig"
@@ -892,6 +917,9 @@ config CPU_LITTLE_ENDIAN
 
 endchoice
 
+config EXPORT_UASM
+        bool
+
 config SYS_SUPPORTS_APM_EMULATION
         bool
 
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 0b9c01add0a0..f0d196090e94 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -130,26 +130,6 @@ cflags-$(CONFIG_CPU_R4300)	+= -march=r4300 -Wa,--trap
 cflags-$(CONFIG_CPU_VR41XX)     += -march=r4100 -Wa,--trap
 cflags-$(CONFIG_CPU_R4X00)      += -march=r4600 -Wa,--trap
 cflags-$(CONFIG_CPU_TX49XX)     += -march=r4600 -Wa,--trap
-# only gcc >= 4.4 have the loongson-specific support
-cflags-$(CONFIG_CPU_LOONGSON2)  += -Wa,--trap
-cflags-$(CONFIG_CPU_LOONGSON2E) += \
-        $(call cc-option,-march=loongson2e,-march=r4600)
-cflags-$(CONFIG_CPU_LOONGSON2F) += \
-        $(call cc-option,-march=loongson2f,-march=r4600)
-# enable the workarounds for loongson2f
-ifdef CONFIG_CPU_LOONGSON2F_WORKAROUNDS
-  ifeq ($(call as-option,-Wa$(comma)-mfix-loongson2f-nop,),)
-    $(error only binutils >= 2.20.2 have needed option -mfix-loongson2f-nop)
-  else
-    cflags-$(CONFIG_CPU_NOP_WORKAROUNDS) += -Wa$(comma)-mfix-loongson2f-nop
-  endif
-  ifeq ($(call as-option,-Wa$(comma)-mfix-loongson2f-jump,),)
-    $(error only binutils >= 2.20.2 have needed option -mfix-loongson2f-jump)
-  else
-    cflags-$(CONFIG_CPU_JUMP_WORKAROUNDS) += -Wa$(comma)-mfix-loongson2f-jump
-  endif
-endif
-
 cflags-$(CONFIG_CPU_MIPS32_R1)  += $(call cc-option,-march=mips32,-mips32 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \
                         -Wa,-mips32 -Wa,--trap
 cflags-$(CONFIG_CPU_MIPS32_R2)  += $(call cc-option,-march=mips32r2,-mips32r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \
@@ -209,455 +189,7 @@ endif
 #
 # Board-dependent options and extra files
 #
-
-#
-# Texas Instruments AR7
-#
-core-$(CONFIG_AR7)              += arch/mips/ar7/
-cflags-$(CONFIG_AR7)            += -I$(srctree)/arch/mips/include/asm/mach-ar7
-load-$(CONFIG_AR7)              += 0xffffffff94100000
-
-#
-# Acer PICA 61, Mips Magnum 4000 and Olivetti M700.
-#
-core-$(CONFIG_MACH_JAZZ)        += arch/mips/jazz/
-cflags-$(CONFIG_MACH_JAZZ)      += -I$(srctree)/arch/mips/include/asm/mach-jazz
-load-$(CONFIG_MACH_JAZZ)        += 0xffffffff80080000
-
-#
-# Common Alchemy Au1x00 stuff
-#
-core-$(CONFIG_SOC_AU1X00)       += arch/mips/alchemy/common/
-
-#
-# AMD Alchemy Pb1000 eval board
-#
-core-$(CONFIG_MIPS_PB1000)      += arch/mips/alchemy/devboards/
-cflags-$(CONFIG_MIPS_PB1000)    += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
-load-$(CONFIG_MIPS_PB1000)      += 0xffffffff80100000
-
-#
-# AMD Alchemy Pb1100 eval board
-#
-core-$(CONFIG_MIPS_PB1100)      += arch/mips/alchemy/devboards/
-cflags-$(CONFIG_MIPS_PB1100)    += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
-load-$(CONFIG_MIPS_PB1100)      += 0xffffffff80100000
-
-#
-# AMD Alchemy Pb1500 eval board
-#
-core-$(CONFIG_MIPS_PB1500)      += arch/mips/alchemy/devboards/
-cflags-$(CONFIG_MIPS_PB1500)    += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
-load-$(CONFIG_MIPS_PB1500)      += 0xffffffff80100000
-
-#
-# AMD Alchemy Pb1550 eval board
-#
-core-$(CONFIG_MIPS_PB1550)      += arch/mips/alchemy/devboards/
-cflags-$(CONFIG_MIPS_PB1550)    += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
-load-$(CONFIG_MIPS_PB1550)      += 0xffffffff80100000
-
-#
-# AMD Alchemy Pb1200 eval board
-#
-core-$(CONFIG_MIPS_PB1200)      += arch/mips/alchemy/devboards/
-cflags-$(CONFIG_MIPS_PB1200)    += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
-load-$(CONFIG_MIPS_PB1200)      += 0xffffffff80100000
-
-#
-# AMD Alchemy Db1000 eval board
-#
-core-$(CONFIG_MIPS_DB1000)      += arch/mips/alchemy/devboards/
-cflags-$(CONFIG_MIPS_DB1000)    += -I$(srctree)/arch/mips/include/asm/mach-db1x00
-load-$(CONFIG_MIPS_DB1000)      += 0xffffffff80100000
-
-#
-# AMD Alchemy Db1100 eval board
-#
-core-$(CONFIG_MIPS_DB1100)      += arch/mips/alchemy/devboards/
-cflags-$(CONFIG_MIPS_DB1100)    += -I$(srctree)/arch/mips/include/asm/mach-db1x00
-load-$(CONFIG_MIPS_DB1100)      += 0xffffffff80100000
-
-#
-# AMD Alchemy Db1500 eval board
-#
-core-$(CONFIG_MIPS_DB1500)      += arch/mips/alchemy/devboards/
-cflags-$(CONFIG_MIPS_DB1500)    += -I$(srctree)/arch/mips/include/asm/mach-db1x00
-load-$(CONFIG_MIPS_DB1500)      += 0xffffffff80100000
-
-#
-# AMD Alchemy Db1550 eval board
-#
-core-$(CONFIG_MIPS_DB1550)      += arch/mips/alchemy/devboards/
-cflags-$(CONFIG_MIPS_DB1550)    += -I$(srctree)/arch/mips/include/asm/mach-db1x00
-load-$(CONFIG_MIPS_DB1550)      += 0xffffffff80100000
-
-#
-# AMD Alchemy Db1200 eval board
-#
-core-$(CONFIG_MIPS_DB1200)      += arch/mips/alchemy/devboards/
-cflags-$(CONFIG_MIPS_DB1200)    += -I$(srctree)/arch/mips/include/asm/mach-db1x00
-load-$(CONFIG_MIPS_DB1200)      += 0xffffffff80100000
-
-#
-# AMD Alchemy Bosporus eval board
-#
-core-$(CONFIG_MIPS_BOSPORUS)    += arch/mips/alchemy/devboards/
-cflags-$(CONFIG_MIPS_BOSPORUS)  += -I$(srctree)/arch/mips/include/asm/mach-db1x00
-load-$(CONFIG_MIPS_BOSPORUS)    += 0xffffffff80100000
-
-#
-# AMD Alchemy Mirage eval board
-#
-core-$(CONFIG_MIPS_MIRAGE)      += arch/mips/alchemy/devboards/
-cflags-$(CONFIG_MIPS_MIRAGE)    += -I$(srctree)/arch/mips/include/asm/mach-db1x00
-load-$(CONFIG_MIPS_MIRAGE)      += 0xffffffff80100000
-
-#
-# 4G-Systems eval board
-#
-libs-$(CONFIG_MIPS_MTX1)        += arch/mips/alchemy/mtx-1/
-load-$(CONFIG_MIPS_MTX1)        += 0xffffffff80100000
-
-#
-# MyCable eval board
-#
-libs-$(CONFIG_MIPS_XXS1500)     += arch/mips/alchemy/xxs1500/
-load-$(CONFIG_MIPS_XXS1500)     += 0xffffffff80100000
-
-# must be last for Alchemy systems for GPIO to work properly
-cflags-$(CONFIG_SOC_AU1X00)     += -I$(srctree)/arch/mips/include/asm/mach-au1x00
-
-
-#
-# Cobalt Server
-#
-core-$(CONFIG_MIPS_COBALT)      += arch/mips/cobalt/
-cflags-$(CONFIG_MIPS_COBALT)    += -I$(srctree)/arch/mips/include/asm/mach-cobalt
-load-$(CONFIG_MIPS_COBALT)      += 0xffffffff80080000
-
-#
-# DECstation family
-#
-core-$(CONFIG_MACH_DECSTATION)  += arch/mips/dec/
-cflags-$(CONFIG_MACH_DECSTATION)+= -I$(srctree)/arch/mips/include/asm/mach-dec
-libs-$(CONFIG_MACH_DECSTATION)  += arch/mips/dec/prom/
-load-$(CONFIG_MACH_DECSTATION)  += 0xffffffff80040000
-
-#
-# Wind River PPMC Board (4KC + GT64120)
-#
-core-$(CONFIG_WR_PPMC)          += arch/mips/gt64120/wrppmc/
-cflags-$(CONFIG_WR_PPMC)                += -I$(srctree)/arch/mips/include/asm/mach-wrppmc
-load-$(CONFIG_WR_PPMC)          += 0xffffffff80100000
-
-#
-# Loongson family
-#
-core-$(CONFIG_MACH_LOONGSON) += arch/mips/loongson/
-cflags-$(CONFIG_MACH_LOONGSON) += -I$(srctree)/arch/mips/include/asm/mach-loongson \
-                    -mno-branch-likely
-load-$(CONFIG_LEMOTE_FULOONG2E) += 0xffffffff80100000
-load-$(CONFIG_LEMOTE_MACH2F) += 0xffffffff80200000
-
-#
-# MIPS Malta board
-#
-core-$(CONFIG_MIPS_MALTA)       += arch/mips/mti-malta/
-cflags-$(CONFIG_MIPS_MALTA)     += -I$(srctree)/arch/mips/include/asm/mach-malta
-load-$(CONFIG_MIPS_MALTA)       += 0xffffffff80100000
-all-$(CONFIG_MIPS_MALTA)        := $(COMPRESSION_FNAME).bin
-
-#
-# MIPS SIM
-#
-core-$(CONFIG_MIPS_SIM)         += arch/mips/mipssim/
-cflags-$(CONFIG_MIPS_SIM)       += -I$(srctree)/arch/mips/include/asm/mach-mipssim
-load-$(CONFIG_MIPS_SIM)         += 0x80100000
-
-#
-# PMC-Sierra MSP SOCs
-#
-core-$(CONFIG_PMC_MSP)          += arch/mips/pmc-sierra/msp71xx/
-cflags-$(CONFIG_PMC_MSP)        += -I$(srctree)/arch/mips/include/asm/pmc-sierra/msp71xx \
-                                        -mno-branch-likely
-load-$(CONFIG_PMC_MSP)          += 0xffffffff80100000
-
-#
-# PMC-Sierra Yosemite
-#
-core-$(CONFIG_PMC_YOSEMITE)     += arch/mips/pmc-sierra/yosemite/
-cflags-$(CONFIG_PMC_YOSEMITE)   += -I$(srctree)/arch/mips/include/asm/mach-yosemite
-load-$(CONFIG_PMC_YOSEMITE)     += 0xffffffff80100000
-
-#
-# LASAT platforms
-#
-core-$(CONFIG_LASAT)            += arch/mips/lasat/
-cflags-$(CONFIG_LASAT)          += -I$(srctree)/arch/mips/include/asm/mach-lasat
-load-$(CONFIG_LASAT)            += 0xffffffff80000000
-
-#
-# Common VR41xx
-#
-core-$(CONFIG_MACH_VR41XX)      += arch/mips/vr41xx/common/
-cflags-$(CONFIG_MACH_VR41XX)    += -I$(srctree)/arch/mips/include/asm/mach-vr41xx
-
-#
-# ZAO Networks Capcella (VR4131)
-#
-load-$(CONFIG_ZAO_CAPCELLA)     += 0xffffffff80000000
-
-#
-# Victor MP-C303/304 (VR4122)
-#
-load-$(CONFIG_VICTOR_MPC30X)    += 0xffffffff80001000
-
-#
-# IBM WorkPad z50 (VR4121)
-#
-core-$(CONFIG_IBM_WORKPAD)      += arch/mips/vr41xx/ibm-workpad/
-load-$(CONFIG_IBM_WORKPAD)      += 0xffffffff80004000
-
-#
-# CASIO CASSIPEIA E-55/65 (VR4111)
-#
-core-$(CONFIG_CASIO_E55)        += arch/mips/vr41xx/casio-e55/
-load-$(CONFIG_CASIO_E55)        += 0xffffffff80004000
-
-#
-# TANBAC VR4131 multichip module(TB0225) and TANBAC VR4131DIMM(TB0229) (VR4131)
-#
-load-$(CONFIG_TANBAC_TB022X)    += 0xffffffff80000000
-
-# NXP STB225
-core-$(CONFIG_SOC_PNX833X)              += arch/mips/nxp/pnx833x/common/
-cflags-$(CONFIG_SOC_PNX833X)    += -Iarch/mips/include/asm/mach-pnx833x
-libs-$(CONFIG_NXP_STB220)               += arch/mips/nxp/pnx833x/stb22x/
-load-$(CONFIG_NXP_STB220)               += 0xffffffff80001000
-libs-$(CONFIG_NXP_STB225)               += arch/mips/nxp/pnx833x/stb22x/
-load-$(CONFIG_NXP_STB225)               += 0xffffffff80001000
-
-#
-# Common NXP PNX8550
-#
-core-$(CONFIG_SOC_PNX8550)      += arch/mips/nxp/pnx8550/common/
-cflags-$(CONFIG_SOC_PNX8550)    += -I$(srctree)/arch/mips/include/asm/mach-pnx8550
-
-#
-# NXP PNX8550 JBS board
-#
-libs-$(CONFIG_PNX8550_JBS)      += arch/mips/nxp/pnx8550/jbs/
-#cflags-$(CONFIG_PNX8550_JBS)   += -I$(srctree)/arch/mips/include/asm/mach-pnx8550
-load-$(CONFIG_PNX8550_JBS)      += 0xffffffff80060000
-
-# NXP PNX8550 STB810 board
-#
-libs-$(CONFIG_PNX8550_STB810)   += arch/mips/nxp/pnx8550/stb810/
-load-$(CONFIG_PNX8550_STB810)   += 0xffffffff80060000
-
-#
-# Common NEC EMMAXXX
-#
-core-$(CONFIG_SOC_EMMA2RH)      += arch/mips/emma/common/
-cflags-$(CONFIG_SOC_EMMA2RH)    += -I$(srctree)/arch/mips/include/asm/mach-emma2rh
-
-#
-# NEC EMMA2RH Mark-eins
-#
-core-$(CONFIG_NEC_MARKEINS)     += arch/mips/emma/markeins/
-load-$(CONFIG_NEC_MARKEINS)     += 0xffffffff88100000
-
-#
-# Cisco PowerTV Platform
-#
-core-$(CONFIG_POWERTV)          += arch/mips/powertv/
-cflags-$(CONFIG_POWERTV)        += -I$(srctree)/arch/mips/include/asm/mach-powertv
-load-$(CONFIG_POWERTV)          += 0xffffffff90800000
-
-#
-# SGI IP22 (Indy/Indigo2)
-#
-# Set the load address to >= 0xffffffff88069000 if you want to leave space for
-# symmon, 0xffffffff80002000 for production kernels.  Note that the value must
-# be aligned to a multiple of the kernel stack size or the handling of the
-# current variable will break so for 64-bit kernels we have to raise the start
-# address by 8kb.
-#
-core-$(CONFIG_SGI_IP22)         += arch/mips/sgi-ip22/
-cflags-$(CONFIG_SGI_IP22)       += -I$(srctree)/arch/mips/include/asm/mach-ip22
-ifdef CONFIG_32BIT
-load-$(CONFIG_SGI_IP22)         += 0xffffffff88002000
-endif
-ifdef CONFIG_64BIT
-load-$(CONFIG_SGI_IP22)         += 0xffffffff88004000
-endif
-
-#
-# SGI-IP27 (Origin200/2000)
-#
-# Set the load address to >= 0xc000000000300000 if you want to leave space for
-# symmon, 0xc00000000001c000 for production kernels.  Note that the value must
-# be 16kb aligned or the handling of the current variable will break.
-#
-ifdef CONFIG_SGI_IP27
-core-$(CONFIG_SGI_IP27)         += arch/mips/sgi-ip27/
-cflags-$(CONFIG_SGI_IP27)       += -I$(srctree)/arch/mips/include/asm/mach-ip27
-ifdef CONFIG_MAPPED_KERNEL
-load-$(CONFIG_SGI_IP27)         += 0xc00000004001c000
-OBJCOPYFLAGS                    := --change-addresses=0x3fffffff80000000
-dataoffset-$(CONFIG_SGI_IP27)   += 0x01000000
-else
-load-$(CONFIG_SGI_IP27)         += 0xa80000000001c000
-OBJCOPYFLAGS                    := --change-addresses=0x57ffffff80000000
-endif
-endif
-
-#
-# SGI IP28 (Indigo2 R10k)
-#
-# Set the load address to >= 0xa800000020080000 if you want to leave space for
-# symmon, 0xa800000020004000 for production kernels ?  Note that the value must
-# be 16kb aligned or the handling of the current variable will break.
-# Simplified: what IP22 does at 128MB+ in ksegN, IP28 does at 512MB+ in xkphys
-#
-ifdef CONFIG_SGI_IP28
-  ifeq ($(call cc-option-yn,-mr10k-cache-barrier=store), n)
-      $(error gcc doesn't support needed option -mr10k-cache-barrier=store)
-  endif
-endif
-core-$(CONFIG_SGI_IP28)         += arch/mips/sgi-ip22/
-cflags-$(CONFIG_SGI_IP28)       += -mr10k-cache-barrier=store -I$(srctree)/arch/mips/include/asm/mach-ip28
-load-$(CONFIG_SGI_IP28)         += 0xa800000020004000
-
-#
-# SGI-IP32 (O2)
-#
-# Set the load address to >= 80069000 if you want to leave space for symmon,
-# 0xffffffff80004000 for production kernels.  Note that the value must be aligned to
-# a multiple of the kernel stack size or the handling of the current variable
-# will break.
-#
-core-$(CONFIG_SGI_IP32)         += arch/mips/sgi-ip32/
-cflags-$(CONFIG_SGI_IP32)       += -I$(srctree)/arch/mips/include/asm/mach-ip32
-load-$(CONFIG_SGI_IP32)         += 0xffffffff80004000
-
-#
-# Sibyte SB1250/BCM1480 SOC
-#
-# This is a LIB so that it links at the end, and initcalls are later
-# the sequence; but it is built as an object so that modules don't get
-# removed (as happens, even if they have __initcall/module_init)
-#
-core-$(CONFIG_SIBYTE_BCM112X)   += arch/mips/sibyte/sb1250/
-core-$(CONFIG_SIBYTE_BCM112X)   += arch/mips/sibyte/common/
-cflags-$(CONFIG_SIBYTE_BCM112X) += -I$(srctree)/arch/mips/include/asm/mach-sibyte \
-                        -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1250_112x_ALL
-
-core-$(CONFIG_SIBYTE_SB1250)    += arch/mips/sibyte/sb1250/
-core-$(CONFIG_SIBYTE_SB1250)    += arch/mips/sibyte/common/
-cflags-$(CONFIG_SIBYTE_SB1250)  += -I$(srctree)/arch/mips/include/asm/mach-sibyte \
-                        -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1250_112x_ALL
-
-core-$(CONFIG_SIBYTE_BCM1x55)   += arch/mips/sibyte/bcm1480/
-core-$(CONFIG_SIBYTE_BCM1x55)   += arch/mips/sibyte/common/
-cflags-$(CONFIG_SIBYTE_BCM1x55) += -I$(srctree)/arch/mips/include/asm/mach-sibyte \
-                        -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1480_ALL
-
-core-$(CONFIG_SIBYTE_BCM1x80)   += arch/mips/sibyte/bcm1480/
-core-$(CONFIG_SIBYTE_BCM1x80)   += arch/mips/sibyte/common/
-cflags-$(CONFIG_SIBYTE_BCM1x80) += -I$(srctree)/arch/mips/include/asm/mach-sibyte \
-                        -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1480_ALL
-
-#
-# Sibyte BCM91120x (Carmel) board
-# Sibyte BCM91120C (CRhine) board
-# Sibyte BCM91125C (CRhone) board
-# Sibyte BCM91125E (Rhone) board
-# Sibyte SWARM board
-# Sibyte BCM91x80 (BigSur) board
-#
-core-$(CONFIG_SIBYTE_CARMEL)    += arch/mips/sibyte/swarm/
-load-$(CONFIG_SIBYTE_CARMEL)    := 0xffffffff80100000
-core-$(CONFIG_SIBYTE_CRHINE)    += arch/mips/sibyte/swarm/
-load-$(CONFIG_SIBYTE_CRHINE)    := 0xffffffff80100000
-core-$(CONFIG_SIBYTE_CRHONE)    += arch/mips/sibyte/swarm/
-load-$(CONFIG_SIBYTE_CRHONE)    := 0xffffffff80100000
-core-$(CONFIG_SIBYTE_RHONE)     += arch/mips/sibyte/swarm/
-load-$(CONFIG_SIBYTE_RHONE)     := 0xffffffff80100000
-core-$(CONFIG_SIBYTE_SENTOSA)   += arch/mips/sibyte/swarm/
-load-$(CONFIG_SIBYTE_SENTOSA)   := 0xffffffff80100000
-core-$(CONFIG_SIBYTE_SWARM)     += arch/mips/sibyte/swarm/
-load-$(CONFIG_SIBYTE_SWARM)     := 0xffffffff80100000
-core-$(CONFIG_SIBYTE_BIGSUR)    += arch/mips/sibyte/swarm/
-load-$(CONFIG_SIBYTE_BIGSUR)    := 0xffffffff80100000
-
-#
-# Broadcom BCM47XX boards
-#
-core-$(CONFIG_BCM47XX)          += arch/mips/bcm47xx/
-cflags-$(CONFIG_BCM47XX)        += -I$(srctree)/arch/mips/include/asm/mach-bcm47xx
-load-$(CONFIG_BCM47XX)          := 0xffffffff80001000
-
-#
-# Broadcom BCM63XX boards
-#
-core-$(CONFIG_BCM63XX)          += arch/mips/bcm63xx/
-cflags-$(CONFIG_BCM63XX)        += -I$(srctree)/arch/mips/include/asm/mach-bcm63xx/
-load-$(CONFIG_BCM63XX)          := 0xffffffff80010000
-
-#
-# SNI RM
-#
-core-$(CONFIG_SNI_RM)           += arch/mips/sni/
-cflags-$(CONFIG_SNI_RM)         += -I$(srctree)/arch/mips/include/asm/mach-rm
-ifdef CONFIG_CPU_LITTLE_ENDIAN
-load-$(CONFIG_SNI_RM)           += 0xffffffff80600000
-else
-load-$(CONFIG_SNI_RM)           += 0xffffffff80030000
-endif
-all-$(CONFIG_SNI_RM)            := $(COMPRESSION_FNAME).ecoff
-
-#
-# Common TXx9
-#
-core-$(CONFIG_MACH_TX39XX)      += arch/mips/txx9/generic/
-cflags-$(CONFIG_MACH_TX39XX) += -I$(srctree)/arch/mips/include/asm/mach-tx39xx
-load-$(CONFIG_MACH_TX39XX)      += 0xffffffff80050000
-core-$(CONFIG_MACH_TX49XX)      += arch/mips/txx9/generic/
-cflags-$(CONFIG_MACH_TX49XX) += -I$(srctree)/arch/mips/include/asm/mach-tx49xx
-load-$(CONFIG_MACH_TX49XX)      += 0xffffffff80100000
-
-#
-# Toshiba JMR-TX3927 board
-#
-core-$(CONFIG_TOSHIBA_JMR3927)  += arch/mips/txx9/jmr3927/
-
-#
-# Routerboard 532 board
-#
-core-$(CONFIG_MIKROTIK_RB532)   += arch/mips/rb532/
-cflags-$(CONFIG_MIKROTIK_RB532) += -I$(srctree)/arch/mips/include/asm/mach-rc32434
-load-$(CONFIG_MIKROTIK_RB532)   += 0xffffffff80101000
-
-#
-# Toshiba RBTX49XX boards
-#
-core-$(CONFIG_TOSHIBA_RBTX4927) += arch/mips/txx9/rbtx4927/
-core-$(CONFIG_TOSHIBA_RBTX4938) += arch/mips/txx9/rbtx4938/
-core-$(CONFIG_TOSHIBA_RBTX4939) += arch/mips/txx9/rbtx4939/
-
-#
-# Cavium Octeon
-#
-core-$(CONFIG_CPU_CAVIUM_OCTEON)        += arch/mips/cavium-octeon/
-cflags-$(CONFIG_CPU_CAVIUM_OCTEON)      += -I$(srctree)/arch/mips/include/asm/mach-cavium-octeon
-core-$(CONFIG_CPU_CAVIUM_OCTEON)        += arch/mips/cavium-octeon/executive/
-ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
-load-$(CONFIG_CPU_CAVIUM_OCTEON)        += 0xffffffff84100000
-else
-load-$(CONFIG_CPU_CAVIUM_OCTEON)        += 0xffffffff81100000
-endif
+include $(srctree)/arch/mips/Kbuild.platforms
 
 cflags-y                        += -I$(srctree)/arch/mips/include/asm/mach-generic
 drivers-$(CONFIG_PCI)           += arch/mips/pci/
@@ -706,7 +238,8 @@ head-y := arch/mips/kernel/head.o arch/mips/kernel/init_task.o
 
 libs-y                  += arch/mips/lib/
 
-core-y                  += arch/mips/kernel/ arch/mips/mm/ arch/mips/math-emu/
+# See arch/mips/Kbuild for content of core part of the kernel
+core-y += arch/mips/
 
 drivers-$(CONFIG_OPROFILE)      += arch/mips/oprofile/
 
@@ -726,6 +259,9 @@ endif
 vmlinux.32: vmlinux
         $(OBJCOPY) -O $(32bit-bfd) $(OBJCOPYFLAGS) $< $@
 
+
+#obj-$(CONFIG_KPROBES)          += kprobes.o
+
 #
 # The 64-bit ELF tools are pretty broken so at this time we generate 64-bit
 # ELF files from 32-bit files by conversion.
@@ -733,35 +269,19 @@ vmlinux.32: vmlinux
 vmlinux.64: vmlinux
         $(OBJCOPY) -O $(64bit-bfd) $(OBJCOPYFLAGS) $< $@
 
-makeboot =$(Q)$(MAKE) $(build)=arch/mips/boot VMLINUX=$(vmlinux-32) $(1)
-makezboot =$(Q)$(MAKE) $(build)=arch/mips/boot/compressed \
-           VMLINUX_LOAD_ADDRESS=$(load-y) 32bit-bfd=$(32bit-bfd) $(1)
-
 all:    $(all-y)
 
-vmlinuz: vmlinux FORCE
-        +@$(call makezboot,$@)
+# boot
+vmlinux.bin vmlinux.ecoff vmlinux.srec: $(vmlinux-32) FORCE
+        $(Q)$(MAKE) $(build)=arch/mips/boot VMLINUX=$(vmlinux-32) arch/mips/boot/$@
 
-vmlinuz.bin: vmlinux
-        +@$(call makezboot,$@)
+# boot/compressed
+vmlinuz vmlinuz.bin vmlinuz.ecoff vmlinuz.srec: $(vmlinux-32) FORCE
+        $(Q)$(MAKE) $(build)=arch/mips/boot/compressed \
+           VMLINUX_LOAD_ADDRESS=$(load-y) 32bit-bfd=$(32bit-bfd) $@
 
-vmlinuz.ecoff: vmlinux
-        +@$(call makezboot,$@)
 
-vmlinuz.srec: vmlinux
-        +@$(call makezboot,$@)
-
-vmlinux.bin: $(vmlinux-32)
-        +@$(call makeboot,$@)
-
-vmlinux.ecoff: $(vmlinux-32)
-        +@$(call makeboot,$@)
-
-vmlinux.srec: $(vmlinux-32)
-        +@$(call makeboot,$@)
-
-CLEAN_FILES += vmlinux.ecoff \
-               vmlinux.srec
+CLEAN_FILES += vmlinux.32 vmlinux.64
 
 archprepare:
 ifdef CONFIG_MIPS32_N32
@@ -780,9 +300,9 @@ install:
         $(Q)install -D -m 644 System.map $(INSTALL_PATH)/System.map-$(KERNELRELEASE)
 
 archclean:
-        @$(MAKE) $(clean)=arch/mips/boot
-        @$(MAKE) $(clean)=arch/mips/boot/compressed
-        @$(MAKE) $(clean)=arch/mips/lasat
+        $(Q)$(MAKE) $(clean)=arch/mips/boot
+        $(Q)$(MAKE) $(clean)=arch/mips/boot/compressed
+        $(Q)$(MAKE) $(clean)=arch/mips/lasat
 
 define archhelp
         echo '  install              - install kernel into $(INSTALL_PATH)'
@@ -796,11 +316,3 @@ define archhelp
         echo
         echo '  These will be default as apropriate for a configured platform.'
 endef
-
-CLEAN_FILES += vmlinux.32 \
-               vmlinux.64 \
-               vmlinux.ecoff \
-               vmlinuz \
-               vmlinuz.ecoff \
-               vmlinuz.bin \
-               vmlinuz.srec
diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig
index df3b1a7eb15d..2ccfd4a135bc 100644
--- a/arch/mips/alchemy/Kconfig
+++ b/arch/mips/alchemy/Kconfig
@@ -11,7 +11,7 @@ config ALCHEMY_GPIO_INDIRECT
 
 choice
         prompt "Machine type"
-        depends on MACH_ALCHEMY
+        depends on MIPS_ALCHEMY
         default MIPS_DB1000
 
 config MIPS_MTX1
@@ -128,41 +128,33 @@ config MIPS_XXS1500
         select SYS_SUPPORTS_LITTLE_ENDIAN
         select SYS_HAS_EARLY_PRINTK
 
+config MIPS_GPR
+        bool "Trapeze ITS GPR board"
+        select SOC_AU1550
+        select HW_HAS_PCI
+        select DMA_NONCOHERENT
+        select MIPS_DISABLE_OBSOLETE_IDE
+        select SYS_SUPPORTS_LITTLE_ENDIAN
+        select SYS_HAS_EARLY_PRINTK
+
 endchoice
 
 config SOC_AU1000
         bool
-        select SOC_AU1X00
         select ALCHEMY_GPIOINT_AU1000
 
 config SOC_AU1100
         bool
-        select SOC_AU1X00
         select ALCHEMY_GPIOINT_AU1000
 
 config SOC_AU1500
         bool
-        select SOC_AU1X00
         select ALCHEMY_GPIOINT_AU1000
 
 config SOC_AU1550
         bool
-        select SOC_AU1X00
         select ALCHEMY_GPIOINT_AU1000
 
 config SOC_AU1200
         bool
-        select SOC_AU1X00
         select ALCHEMY_GPIOINT_AU1000
-
-config SOC_AU1X00
-        bool
-        select 64BIT_PHYS_ADDR
-        select CEVT_R4K_LIB
-        select CSRC_R4K_LIB
-        select IRQ_CPU
-        select SYS_HAS_CPU_MIPS32_R1
-        select SYS_SUPPORTS_32BIT_KERNEL
-        select SYS_SUPPORTS_APM_EMULATION
-        select GENERIC_GPIO
-        select ARCH_WANT_OPTIONAL_GPIOLIB
diff --git a/arch/mips/alchemy/Platform b/arch/mips/alchemy/Platform
new file mode 100644
index 000000000000..96e9e41f1b2a
--- /dev/null
+++ b/arch/mips/alchemy/Platform
@@ -0,0 +1,114 @@
+#
+# Core Alchemy code
+#
+platform-$(CONFIG_MIPS_ALCHEMY) += alchemy/common/
+
+
+#
+# AMD Alchemy Pb1000 eval board
+#
+platform-$(CONFIG_MIPS_PB1000)  += alchemy/devboards/
+cflags-$(CONFIG_MIPS_PB1000)    += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
+load-$(CONFIG_MIPS_PB1000)      += 0xffffffff80100000
+
+#
+# AMD Alchemy Pb1100 eval board
+#
+platform-$(CONFIG_MIPS_PB1100)  += alchemy/devboards/
+cflags-$(CONFIG_MIPS_PB1100)    += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
+load-$(CONFIG_MIPS_PB1100)      += 0xffffffff80100000
+
+#
+# AMD Alchemy Pb1500 eval board
+#
+platform-$(CONFIG_MIPS_PB1500)  += alchemy/devboards/
+cflags-$(CONFIG_MIPS_PB1500)    += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
+load-$(CONFIG_MIPS_PB1500)      += 0xffffffff80100000
+
+#
+# AMD Alchemy Pb1550 eval board
+#
+platform-$(CONFIG_MIPS_PB1550)  += alchemy/devboards/
+cflags-$(CONFIG_MIPS_PB1550)    += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
+load-$(CONFIG_MIPS_PB1550)      += 0xffffffff80100000
+
+#
+# AMD Alchemy Pb1200 eval board
+#
+platform-$(CONFIG_MIPS_PB1200)  += alchemy/devboards/
+cflags-$(CONFIG_MIPS_PB1200)    += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
+load-$(CONFIG_MIPS_PB1200)      += 0xffffffff80100000
+
+#
+# AMD Alchemy Db1000 eval board
+#
+platform-$(CONFIG_MIPS_DB1000)  += alchemy/devboards/
+cflags-$(CONFIG_MIPS_DB1000)    += -I$(srctree)/arch/mips/include/asm/mach-db1x00
+load-$(CONFIG_MIPS_DB1000)      += 0xffffffff80100000
+
+#
+# AMD Alchemy Db1100 eval board
+#
+platform-$(CONFIG_MIPS_DB1100)  += alchemy/devboards/
+cflags-$(CONFIG_MIPS_DB1100)    += -I$(srctree)/arch/mips/include/asm/mach-db1x00
+load-$(CONFIG_MIPS_DB1100)      += 0xffffffff80100000
+
+#
+# AMD Alchemy Db1500 eval board
+#
+platform-$(CONFIG_MIPS_DB1500)  += alchemy/devboards/
+cflags-$(CONFIG_MIPS_DB1500)    += -I$(srctree)/arch/mips/include/asm/mach-db1x00
+load-$(CONFIG_MIPS_DB1500)      += 0xffffffff80100000
+
+#
+# AMD Alchemy Db1550 eval board
+#
+platform-$(CONFIG_MIPS_DB1550)  += alchemy/devboards/
+cflags-$(CONFIG_MIPS_DB1550)    += -I$(srctree)/arch/mips/include/asm/mach-db1x00
+load-$(CONFIG_MIPS_DB1550)      += 0xffffffff80100000
+
+#
+# AMD Alchemy Db1200 eval board
+#
+platform-$(CONFIG_MIPS_DB1200)  += alchemy/devboards/
+cflags-$(CONFIG_MIPS_DB1200)    += -I$(srctree)/arch/mips/include/asm/mach-db1x00
+load-$(CONFIG_MIPS_DB1200)      += 0xffffffff80100000
+
+#
+# AMD Alchemy Bosporus eval board
+#
+platform-$(CONFIG_MIPS_BOSPORUS) += alchemy/devboards/
+cflags-$(CONFIG_MIPS_BOSPORUS)   += -I$(srctree)/arch/mips/include/asm/mach-db1x00
+load-$(CONFIG_MIPS_BOSPORUS)     += 0xffffffff80100000
+
+#
+# AMD Alchemy Mirage eval board
+#
+platform-$(CONFIG_MIPS_MIRAGE)  += alchemy/devboards/
+cflags-$(CONFIG_MIPS_MIRAGE)    += -I$(srctree)/arch/mips/include/asm/mach-db1x00
+load-$(CONFIG_MIPS_MIRAGE)      += 0xffffffff80100000
+
+#
+# 4G-Systems eval board
+#
+platform-$(CONFIG_MIPS_MTX1)    += alchemy/mtx-1/
+load-$(CONFIG_MIPS_MTX1)        += 0xffffffff80100000
+
+#
+# MyCable eval board
+#
+platform-$(CONFIG_MIPS_XXS1500) += alchemy/xxs1500/
+load-$(CONFIG_MIPS_XXS1500)     += 0xffffffff80100000
+
+#
+# Trapeze ITS GRP board
+#
+platform-$(CONFIG_MIPS_GPR)     += alchemy/gpr/
+load-$(CONFIG_MIPS_GPR)         += 0xffffffff80100000
+
+# boards can specify their own <gpio.h> in one of their include dirs.
+# If they do, placing this line here at the end will make sure the
+# compiler picks the board one.  If they don't, it will make sure
+# the alchemy generic gpio header is picked up.
+
+cflags-$(CONFIG_MIPS_ALCHEMY)   += -I$(srctree)/arch/mips/include/asm/mach-au1x00
diff --git a/arch/mips/alchemy/common/Makefile b/arch/mips/alchemy/common/Makefile
index 06c0e65a54b5..27811fe341d6 100644
--- a/arch/mips/alchemy/common/Makefile
+++ b/arch/mips/alchemy/common/Makefile
@@ -18,5 +18,3 @@ ifeq ($(CONFIG_ALCHEMY_GPIO_INDIRECT),)
 endif
 
 obj-$(CONFIG_PCI)               += pci.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/alchemy/common/clocks.c b/arch/mips/alchemy/common/clocks.c
index 460c6285c1bb..af0fe41055af 100644
--- a/arch/mips/alchemy/common/clocks.c
+++ b/arch/mips/alchemy/common/clocks.c
@@ -89,11 +89,7 @@ unsigned long au1xxx_calc_clock(void)
          * over backwards trying to determine the frequency.
          */
         if (au1xxx_cpu_has_pll_wo())
-#ifdef CONFIG_SOC_AU1000_FREQUENCY
-                cpu_speed = CONFIG_SOC_AU1000_FREQUENCY;
-#else
                 cpu_speed = 396000000;
-#endif
         else
                 cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK;
 
diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c
index f9e5622ebc95..1dc55ee2681b 100644
--- a/arch/mips/alchemy/common/platform.c
+++ b/arch/mips/alchemy/common/platform.c
@@ -12,6 +12,7 @@
  */
 
 #include <linux/dma-mapping.h>
+#include <linux/etherdevice.h>
 #include <linux/platform_device.h>
 #include <linux/serial_8250.h>
 #include <linux/init.h>
@@ -21,6 +22,8 @@
 #include <asm/mach-au1x00/au1100_mmc.h>
 #include <asm/mach-au1x00/au1xxx_eth.h>
 
+#include <prom.h>
+
 #define PORT(_base, _irq)                                       \
         {                                                       \
                 .mapbase        = _base,                        \
@@ -33,7 +36,6 @@
         }
 
 static struct plat_serial8250_port au1x00_uart_data[] = {
-#if defined(CONFIG_SERIAL_8250_AU1X00)
 #if defined(CONFIG_SOC_AU1000)
         PORT(UART0_PHYS_ADDR, AU1000_UART0_INT),
         PORT(UART1_PHYS_ADDR, AU1000_UART1_INT),
@@ -54,7 +56,6 @@ static struct plat_serial8250_port au1x00_uart_data[] = {
         PORT(UART0_PHYS_ADDR, AU1200_UART0_INT),
         PORT(UART1_PHYS_ADDR, AU1200_UART1_INT),
 #endif
-#endif  /* CONFIG_SERIAL_8250_AU1X00 */
         { },
 };
 
@@ -436,17 +437,27 @@ static int __init au1xxx_platform_init(void)
 {
         unsigned int uartclk = get_au1x00_uart_baud_base() * 16;
         int err, i;
+        unsigned char ethaddr[6];
 
         /* Fill up uartclk. */
         for (i = 0; au1x00_uart_data[i].flags; i++)
                 au1x00_uart_data[i].uartclk = uartclk;
 
+        /* use firmware-provided mac addr if available and necessary */
+        i = prom_get_ethernet_addr(ethaddr);
+        if (!i && !is_valid_ether_addr(au1xxx_eth0_platform_data.mac))
+                memcpy(au1xxx_eth0_platform_data.mac, ethaddr, 6);
+
         err = platform_add_devices(au1xxx_platform_devices,
                                    ARRAY_SIZE(au1xxx_platform_devices));
 #ifndef CONFIG_SOC_AU1100
+        ethaddr[5] += 1;        /* next addr for 2nd MAC */
+        if (!i && !is_valid_ether_addr(au1xxx_eth1_platform_data.mac))
+                memcpy(au1xxx_eth1_platform_data.mac, ethaddr, 6);
+
         /* Register second MAC if enabled in pinfunc */
         if (!err && !(au_readl(SYS_PINFUNC) & (u32)SYS_PF_NI2))
-                platform_device_register(&au1xxx_eth1_device);
+                err = platform_device_register(&au1xxx_eth1_device);
 #endif
 
         return err;
diff --git a/arch/mips/alchemy/devboards/Makefile b/arch/mips/alchemy/devboards/Makefile
index ecbd37f9ee87..826449c817c3 100644
--- a/arch/mips/alchemy/devboards/Makefile
+++ b/arch/mips/alchemy/devboards/Makefile
@@ -16,5 +16,3 @@ obj-$(CONFIG_MIPS_DB1500)	+= db1x00/
 obj-$(CONFIG_MIPS_DB1550)       += db1x00/
 obj-$(CONFIG_MIPS_BOSPORUS)     += db1x00/
 obj-$(CONFIG_MIPS_MIRAGE)       += db1x00/
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/alchemy/devboards/db1200/platform.c b/arch/mips/alchemy/devboards/db1200/platform.c
index 3cb95a98ab31..3fa34c3abc04 100644
--- a/arch/mips/alchemy/devboards/db1200/platform.c
+++ b/arch/mips/alchemy/devboards/db1200/platform.c
@@ -216,14 +216,14 @@ static struct resource db1200_ide_res[] = {
         }
 };
 
-static u64 ide_dmamask = DMA_32BIT_MASK;
+static u64 ide_dmamask = DMA_BIT_MASK(32);
 
 static struct platform_device db1200_ide_dev = {
         .name           = "au1200-ide",
         .id             = 0,
         .dev = {
                 .dma_mask               = &ide_dmamask,
-                .coherent_dma_mask      = DMA_32BIT_MASK,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
         },
         .num_resources  = ARRAY_SIZE(db1200_ide_res),
         .resource       = db1200_ide_res,
@@ -385,12 +385,12 @@ static struct au1550_spi_info db1200_spi_platdata = {
         .activate_cs    = db1200_spi_cs_en,
 };
 
-static u64 spi_dmamask = DMA_32BIT_MASK;
+static u64 spi_dmamask = DMA_BIT_MASK(32);
 
 static struct platform_device db1200_spi_dev = {
         .dev    = {
                 .dma_mask               = &spi_dmamask,
-                .coherent_dma_mask      = DMA_32BIT_MASK,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
                 .platform_data          = &db1200_spi_platdata,
         },
         .name           = "au1550-spi",
diff --git a/arch/mips/alchemy/devboards/db1x00/board_setup.c b/arch/mips/alchemy/devboards/db1x00/board_setup.c
index 50c9bef99daa..9e45971343ed 100644
--- a/arch/mips/alchemy/devboards/db1x00/board_setup.c
+++ b/arch/mips/alchemy/devboards/db1x00/board_setup.c
@@ -79,7 +79,6 @@ static struct au1000_eth_platform_data eth0_pdata = {
 
 static void bosporus_power_off(void)
 {
-        printk(KERN_INFO "It's now safe to turn off power\n");
         while (1)
                 asm volatile (".set mips3 ; wait ; .set mips0");
 }
diff --git a/arch/mips/alchemy/devboards/pb1000/board_setup.c b/arch/mips/alchemy/devboards/pb1000/board_setup.c
index 4ef50d86b181..f6540ec47a64 100644
--- a/arch/mips/alchemy/devboards/pb1000/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1000/board_setup.c
@@ -47,9 +47,11 @@ static void board_reset(char *c)
 
 static void board_power_off(void)
 {
-        printk(KERN_ALERT "It's now safe to remove power\n");
         while (1)
-                asm volatile (".set mips3 ; wait ; .set mips1");
+                asm volatile (
+                "       .set    mips32                                  \n"
+                "       wait                                            \n"
+                "       .set    mips0                                   \n");
 }
 
 void __init board_setup(void)
diff --git a/arch/mips/alchemy/devboards/pb1200/Makefile b/arch/mips/alchemy/devboards/pb1200/Makefile
index 2ea9b02ef09f..18c1bd53e4c0 100644
--- a/arch/mips/alchemy/devboards/pb1200/Makefile
+++ b/arch/mips/alchemy/devboards/pb1200/Makefile
@@ -3,5 +3,3 @@
 #
 
 obj-y := board_setup.o platform.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/alchemy/gpr/Makefile b/arch/mips/alchemy/gpr/Makefile
new file mode 100644
index 000000000000..cb73fe256dce
--- /dev/null
+++ b/arch/mips/alchemy/gpr/Makefile
@@ -0,0 +1,8 @@
+#
+#  Copyright 2003 MontaVista Software Inc.
+#  Author: MontaVista Software, Inc. <source@mvista.com>
+#
+# Makefile for Trapeze ITS GPR board.
+#
+
+obj-y += board_setup.o init.o platform.o
diff --git a/arch/mips/alchemy/gpr/board_setup.c b/arch/mips/alchemy/gpr/board_setup.c
new file mode 100644
index 000000000000..ad2e3f137933
--- /dev/null
+++ b/arch/mips/alchemy/gpr/board_setup.c
@@ -0,0 +1,93 @@
+/*
+ * Copyright 2010 Wolfgang Grandegger <wg@denx.de>
+ *
+ * Copyright 2000-2003, 2008 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc. <source@mvista.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/gpio.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <linux/pm.h>
+
+#include <asm/reboot.h>
+#include <asm/mach-au1x00/au1000.h>
+
+#include <prom.h>
+
+#define UART1_ADDR      KSEG1ADDR(UART1_PHYS_ADDR)
+#define UART3_ADDR      KSEG1ADDR(UART3_PHYS_ADDR)
+
+char irq_tab_alchemy[][5] __initdata = {
+        [0] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff },
+};
+
+static void gpr_reset(char *c)
+{
+        /* switch System-LED to orange (red# and green# on) */
+        alchemy_gpio_direction_output(4, 0);
+        alchemy_gpio_direction_output(5, 0);
+
+        /* trigger watchdog to reset board in 200ms */
+        printk(KERN_EMERG "Triggering watchdog soft reset...\n");
+        raw_local_irq_disable();
+        alchemy_gpio_direction_output(1, 0);
+        udelay(1);
+        alchemy_gpio_set_value(1, 1);
+        while (1)
+                cpu_wait();
+}
+
+static void gpr_power_off(void)
+{
+        while (1)
+                cpu_wait();
+}
+
+void __init board_setup(void)
+{
+        printk(KERN_INFO "Tarpeze ITS GPR board\n");
+
+        pm_power_off = gpr_power_off;
+        _machine_halt = gpr_power_off;
+        _machine_restart = gpr_reset;
+
+        /* Enable UART3 */
+        au_writel(0x1, UART3_ADDR + UART_MOD_CNTRL);/* clock enable (CE) */
+        au_writel(0x3, UART3_ADDR + UART_MOD_CNTRL); /* CE and "enable" */
+        /* Enable UART1 */
+        au_writel(0x1, UART1_ADDR + UART_MOD_CNTRL); /* clock enable (CE) */
+        au_writel(0x3, UART1_ADDR + UART_MOD_CNTRL); /* CE and "enable" */
+
+        /* Take away Reset of UMTS-card */
+        alchemy_gpio_direction_output(215, 1);
+
+#ifdef CONFIG_PCI
+#if defined(__MIPSEB__)
+        au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG);
+#else
+        au_writel(0xf, Au1500_PCI_CFG);
+#endif
+#endif
+}
diff --git a/arch/mips/alchemy/gpr/init.c b/arch/mips/alchemy/gpr/init.c
new file mode 100644
index 000000000000..f044f4c541d7
--- /dev/null
+++ b/arch/mips/alchemy/gpr/init.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright 2010 Wolfgang Grandegger <wg@denx.de>
+ *
+ * Copyright 2003, 2008 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc. <source@mvista.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+
+#include <asm/bootinfo.h>
+#include <asm/mach-au1x00/au1000.h>
+
+#include <prom.h>
+
+const char *get_system_type(void)
+{
+        return "GPR";
+}
+
+void __init prom_init(void)
+{
+        unsigned char *memsize_str;
+        unsigned long memsize;
+
+        prom_argc = fw_arg0;
+        prom_argv = (char **)fw_arg1;
+        prom_envp = (char **)fw_arg2;
+
+        prom_init_cmdline();
+
+        memsize_str = prom_getenv("memsize");
+        if (!memsize_str)
+                memsize = 0x04000000;
+        else
+                strict_strtoul(memsize_str, 0, &memsize);
+        add_memory_region(0, memsize, BOOT_MEM_RAM);
+}
+
+void prom_putchar(unsigned char c)
+{
+        alchemy_uart_putchar(UART0_PHYS_ADDR, c);
+}
diff --git a/arch/mips/alchemy/gpr/platform.c b/arch/mips/alchemy/gpr/platform.c
new file mode 100644
index 000000000000..14b46629cfc8
--- /dev/null
+++ b/arch/mips/alchemy/gpr/platform.c
@@ -0,0 +1,183 @@
+/*
+ * GPR board platform device registration
+ *
+ * Copyright (C) 2010 Wolfgang Grandegger <wg@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
+#include <linux/leds.h>
+#include <linux/gpio.h>
+#include <linux/i2c.h>
+#include <linux/i2c-gpio.h>
+
+#include <asm/mach-au1x00/au1000.h>
+
+/*
+ * Watchdog
+ */
+static struct resource gpr_wdt_resource[] = {
+        [0] = {
+                .start  = 1,
+                .end    = 1,
+                .name   = "gpr-adm6320-wdt",
+                .flags  = IORESOURCE_IRQ,
+        }
+};
+
+static struct platform_device gpr_wdt_device = {
+        .name = "adm6320-wdt",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(gpr_wdt_resource),
+        .resource = gpr_wdt_resource,
+};
+
+/*
+ * FLASH
+ *
+ * 0x00000000-0x00200000 : "kernel"
+ * 0x00200000-0x00a00000 : "rootfs"
+ * 0x01d00000-0x01f00000 : "config"
+ * 0x01c00000-0x01d00000 : "yamon"
+ * 0x01d00000-0x01d40000 : "yamon env vars"
+ * 0x00000000-0x00a00000 : "kernel+rootfs"
+ */
+static struct mtd_partition gpr_mtd_partitions[] = {
+        {
+                .name   = "kernel",
+                .size   = 0x00200000,
+                .offset = 0,
+        },
+        {
+                .name   = "rootfs",
+                .size   = 0x00800000,
+                .offset = MTDPART_OFS_APPEND,
+                .mask_flags = MTD_WRITEABLE,
+        },
+        {
+                .name   = "config",
+                .size   = 0x00200000,
+                .offset = 0x01d00000,
+        },
+        {
+                .name   = "yamon",
+                .size   = 0x00100000,
+                .offset = 0x01c00000,
+        },
+        {
+                .name   = "yamon env vars",
+                .size   = 0x00040000,
+                .offset = MTDPART_OFS_APPEND,
+        },
+        {
+                .name   = "kernel+rootfs",
+                .size   = 0x00a00000,
+                .offset = 0,
+        },
+};
+
+static struct physmap_flash_data gpr_flash_data = {
+        .width          = 4,
+        .nr_parts       = ARRAY_SIZE(gpr_mtd_partitions),
+        .parts          = gpr_mtd_partitions,
+};
+
+static struct resource gpr_mtd_resource = {
+        .start  = 0x1e000000,
+        .end    = 0x1fffffff,
+        .flags  = IORESOURCE_MEM,
+};
+
+static struct platform_device gpr_mtd_device = {
+        .name           = "physmap-flash",
+        .dev            = {
+                .platform_data  = &gpr_flash_data,
+        },
+        .num_resources  = 1,
+        .resource       = &gpr_mtd_resource,
+};
+
+/*
+ * LEDs
+ */
+static struct gpio_led gpr_gpio_leds[] = {
+        {       /* green */
+                .name                   = "gpr:green",
+                .gpio                   = 4,
+                .active_low             = 1,
+        },
+        {       /* red */
+                .name                   = "gpr:red",
+                .gpio                   = 5,
+                .active_low             = 1,
+        }
+};
+
+static struct gpio_led_platform_data gpr_led_data = {
+        .num_leds = ARRAY_SIZE(gpr_gpio_leds),
+        .leds = gpr_gpio_leds,
+};
+
+static struct platform_device gpr_led_devices = {
+        .name = "leds-gpio",
+        .id = -1,
+        .dev = {
+                .platform_data = &gpr_led_data,
+        }
+};
+
+/*
+ * I2C
+ */
+static struct i2c_gpio_platform_data gpr_i2c_data = {
+        .sda_pin                = 209,
+        .sda_is_open_drain      = 1,
+        .scl_pin                = 210,
+        .scl_is_open_drain      = 1,
+        .udelay                 = 2,            /* ~100 kHz */
+        .timeout                = HZ,
+ };
+
+static struct platform_device gpr_i2c_device = {
+        .name                   = "i2c-gpio",
+        .id                     = -1,
+        .dev.platform_data      = &gpr_i2c_data,
+};
+
+static struct i2c_board_info gpr_i2c_info[] __initdata = {
+        {
+                I2C_BOARD_INFO("lm83", 0x18),
+                .type = "lm83"
+        }
+};
+
+static struct platform_device *gpr_devices[] __initdata = {
+        &gpr_wdt_device,
+        &gpr_mtd_device,
+        &gpr_i2c_device,
+        &gpr_led_devices,
+};
+
+static int __init gpr_dev_init(void)
+{
+        i2c_register_board_info(0, gpr_i2c_info, ARRAY_SIZE(gpr_i2c_info));
+
+        return platform_add_devices(gpr_devices, ARRAY_SIZE(gpr_devices));
+}
+device_initcall(gpr_dev_init);
diff --git a/arch/mips/alchemy/mtx-1/Makefile b/arch/mips/alchemy/mtx-1/Makefile
index 4a53815b3c6c..81b540ceaf88 100644
--- a/arch/mips/alchemy/mtx-1/Makefile
+++ b/arch/mips/alchemy/mtx-1/Makefile
@@ -6,7 +6,4 @@
 # Makefile for 4G Systems MTX-1 board.
 #
 
-lib-y := init.o board_setup.o
-obj-y := platform.o
-
-EXTRA_CFLAGS += -Werror
+obj-y += init.o board_setup.o platform.o
diff --git a/arch/mips/alchemy/mtx-1/board_setup.c b/arch/mips/alchemy/mtx-1/board_setup.c
index 52d883d37dd7..6398fa95905c 100644
--- a/arch/mips/alchemy/mtx-1/board_setup.c
+++ b/arch/mips/alchemy/mtx-1/board_setup.c
@@ -60,9 +60,11 @@ static void mtx1_reset(char *c)
 
 static void mtx1_power_off(void)
 {
-        printk(KERN_ALERT "It's now safe to remove power\n");
         while (1)
-                asm volatile (".set mips3 ; wait ; .set mips1");
+                asm volatile (
+                "       .set    mips32                                  \n"
+                "       wait                                            \n"
+                "       .set    mips0                                   \n");
 }
 
 void __init board_setup(void)
@@ -105,14 +107,10 @@ void __init board_setup(void)
 int
 mtx1_pci_idsel(unsigned int devsel, int assert)
 {
-#define MTX_IDSEL_ONLY_0_AND_3 0
-#if MTX_IDSEL_ONLY_0_AND_3
-        if (devsel != 0 && devsel != 3) {
-                printk(KERN_ERR "*** not 0 or 3\n");
-                return 0;
-        }
-#endif
-
+        /* This function is only necessary to support a proprietary Cardbus
+         * adapter on the mtx-1 "singleboard" variant. It triggers a custom
+         * logic chip connected to EXT_IO3 (GPIO1) to suppress IDSEL signals.
+         */
         if (assert && devsel != 0)
                 /* Suppress signal to Cardbus */
                 alchemy_gpio_set_value(1, 0);   /* set EXT_IO3 OFF */
diff --git a/arch/mips/alchemy/xxs1500/Makefile b/arch/mips/alchemy/xxs1500/Makefile
index 4dc81d794cb8..91defcf4f335 100644
--- a/arch/mips/alchemy/xxs1500/Makefile
+++ b/arch/mips/alchemy/xxs1500/Makefile
@@ -5,6 +5,4 @@
 # Makefile for MyCable XXS1500 board.
 #
 
-lib-y := init.o board_setup.o platform.o
-
-EXTRA_CFLAGS += -Werror
+obj-y += init.o board_setup.o platform.o
diff --git a/arch/mips/alchemy/xxs1500/board_setup.c b/arch/mips/alchemy/xxs1500/board_setup.c
index 47b42927607b..b43c918925d3 100644
--- a/arch/mips/alchemy/xxs1500/board_setup.c
+++ b/arch/mips/alchemy/xxs1500/board_setup.c
@@ -42,9 +42,11 @@ static void xxs1500_reset(char *c)
 
 static void xxs1500_power_off(void)
 {
-        printk(KERN_ALERT "It's now safe to remove power\n");
         while (1)
-                asm volatile (".set mips3 ; wait ; .set mips1");
+                asm volatile (
+                "       .set    mips32                                  \n"
+                "       wait                                            \n"
+                "       .set    mips0                                   \n");
 }
 
 void __init board_setup(void)
diff --git a/arch/mips/ar7/Makefile b/arch/mips/ar7/Makefile
index 26bc5da18997..7435e44b3964 100644
--- a/arch/mips/ar7/Makefile
+++ b/arch/mips/ar7/Makefile
@@ -8,4 +8,3 @@ obj-y := \
         platform.o \
         gpio.o \
         clock.o
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/ar7/Platform b/arch/mips/ar7/Platform
new file mode 100644
index 000000000000..0bf85c416c6c
--- /dev/null
+++ b/arch/mips/ar7/Platform
@@ -0,0 +1,6 @@
+#
+# Texas Instruments AR7
+#
+platform-$(CONFIG_AR7)          += ar7/
+cflags-$(CONFIG_AR7)            += -I$(srctree)/arch/mips/include/asm/mach-ar7
+load-$(CONFIG_AR7)              += 0xffffffff94100000
diff --git a/arch/mips/ar7/platform.c b/arch/mips/ar7/platform.c
index 8f31d1d59683..0da5b2b8dd88 100644
--- a/arch/mips/ar7/platform.c
+++ b/arch/mips/ar7/platform.c
@@ -292,40 +292,28 @@ static struct platform_device cpmac_high = {
         .num_resources  = ARRAY_SIZE(cpmac_high_res),
 };
 
-static inline unsigned char char2hex(char h)
+static void __init cpmac_get_mac(int instance, unsigned char *dev_addr)
 {
-        switch (h) {
-        case '0': case '1': case '2': case '3': case '4':
-        case '5': case '6': case '7': case '8': case '9':
-                return h - '0';
-        case 'A': case 'B': case 'C': case 'D': case 'E': case 'F':
-                return h - 'A' + 10;
-        case 'a': case 'b': case 'c': case 'd': case 'e': case 'f':
-                return h - 'a' + 10;
-        default:
-                return 0;
-        }
-}
-
-static void cpmac_get_mac(int instance, unsigned char *dev_addr)
-{
-        int i;
-        char name[5], default_mac[ETH_ALEN], *mac;
+        char name[5], *mac;
 
-        mac = NULL;
         sprintf(name, "mac%c", 'a' + instance);
         mac = prom_getenv(name);
-        if (!mac) {
+        if (!mac && instance) {
                 sprintf(name, "mac%c", 'a');
                 mac = prom_getenv(name);
         }
-        if (!mac) {
-                random_ether_addr(default_mac);
-                mac = default_mac;
-        }
-        for (i = 0; i < 6; i++)
-                dev_addr[i] = (char2hex(mac[i * 3]) << 4) +
-                        char2hex(mac[i * 3 + 1]);
+
+        if (mac) {
+                if (sscanf(mac, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx",
+                                        &dev_addr[0], &dev_addr[1],
+                                        &dev_addr[2], &dev_addr[3],
+                                        &dev_addr[4], &dev_addr[5]) != 6) {
+                        pr_warning("cannot parse mac address, "
+                                        "using random address\n");
+                        random_ether_addr(dev_addr);
+                }
+        } else
+                random_ether_addr(dev_addr);
 }
 
 /*****************************************************************************
diff --git a/arch/mips/bcm47xx/Platform b/arch/mips/bcm47xx/Platform
new file mode 100644
index 000000000000..874b7ca4cd11
--- /dev/null
+++ b/arch/mips/bcm47xx/Platform
@@ -0,0 +1,7 @@
+#
+# Broadcom BCM47XX boards
+#
+platform-$(CONFIG_BCM47XX)      += bcm47xx/
+cflags-$(CONFIG_BCM47XX)        +=                                      \
+                -I$(srctree)/arch/mips/include/asm/mach-bcm47xx
+load-$(CONFIG_BCM47XX)          := 0xffffffff80001000
diff --git a/arch/mips/bcm47xx/nvram.c b/arch/mips/bcm47xx/nvram.c
index 06e03b222f6d..e5b6615731e5 100644
--- a/arch/mips/bcm47xx/nvram.c
+++ b/arch/mips/bcm47xx/nvram.c
@@ -69,7 +69,7 @@ int nvram_getenv(char *name, char *val, size_t val_len)
         char *var, *value, *end, *eq;
 
         if (!name)
-                return 1;
+                return NVRAM_ERR_INV_PARAM;
 
         if (!nvram_buf[0])
                 early_nvram_init();
@@ -89,6 +89,6 @@ int nvram_getenv(char *name, char *val, size_t val_len)
                         return 0;
                 }
         }
-        return 1;
+        return NVRAM_ERR_ENVNOTFOUND;
 }
 EXPORT_SYMBOL(nvram_getenv);
diff --git a/arch/mips/bcm47xx/prom.c b/arch/mips/bcm47xx/prom.c
index 0fa646c5a844..f6e9063cc4c2 100644
--- a/arch/mips/bcm47xx/prom.c
+++ b/arch/mips/bcm47xx/prom.c
@@ -126,6 +126,7 @@ static __init void prom_init_cmdline(void)
 static __init void prom_init_mem(void)
 {
         unsigned long mem;
+        unsigned long max;
 
         /* Figure out memory size by finding aliases.
          *
@@ -134,21 +135,26 @@ static __init void prom_init_mem(void)
          * want to reuse the memory used by CFE (around 4MB). That means cfe_*
          * functions stop to work at some point during the boot, we should only
          * call them at the beginning of the boot.
+         *
+         * BCM47XX uses 128MB for addressing the ram, if the system contains
+         * less that that amount of ram it remaps the ram more often into the
+         * available space.
+         * Accessing memory after 128MB will cause an exception.
+         * max contains the biggest possible address supported by the platform.
+         * If the method wants to try something above we assume 128MB ram.
          */
+        max = ((unsigned long)(prom_init) | ((128 << 20) - 1));
         for (mem = (1 << 20); mem < (128 << 20); mem += (1 << 20)) {
+                if (((unsigned long)(prom_init) + mem) > max) {
+                        mem = (128 << 20);
+                        printk(KERN_DEBUG "assume 128MB RAM\n");
+                        break;
+                }
                 if (*(unsigned long *)((unsigned long)(prom_init) + mem) ==
                     *(unsigned long *)(prom_init))
                         break;
         }
 
-        /* Ignoring the last page when ddr size is 128M. Cached
-         * accesses to last page is causing the processor to prefetch
-         * using address above 128M stepping out of the ddr address
-         * space.
-         */
-        if (mem == 0x8000000)
-                mem -= 0x1000;
-
         add_memory_region(0, mem, BOOT_MEM_RAM);
 }
 
diff --git a/arch/mips/bcm63xx/Makefile b/arch/mips/bcm63xx/Makefile
index 00064b660809..6dfdc69928ac 100644
--- a/arch/mips/bcm63xx/Makefile
+++ b/arch/mips/bcm63xx/Makefile
@@ -3,5 +3,3 @@ obj-y		+= clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \
 obj-$(CONFIG_EARLY_PRINTK)      += early_printk.o
 
 obj-y           += boards/
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/bcm63xx/Platform b/arch/mips/bcm63xx/Platform
new file mode 100644
index 000000000000..5f86b2fff6de
--- /dev/null
+++ b/arch/mips/bcm63xx/Platform
@@ -0,0 +1,7 @@
+#
+# Broadcom BCM63XX boards
+#
+platform-$(CONFIG_BCM63XX)      += bcm63xx/
+cflags-$(CONFIG_BCM63XX)        +=                                      \
+                -I$(srctree)/arch/mips/include/asm/mach-bcm63xx/
+load-$(CONFIG_BCM63XX)          := 0xffffffff80010000
diff --git a/arch/mips/boot/.gitignore b/arch/mips/boot/.gitignore
index 4667a5f9280b..f210b09ececc 100644
--- a/arch/mips/boot/.gitignore
+++ b/arch/mips/boot/.gitignore
@@ -3,3 +3,4 @@ elf2ecoff
 vmlinux.*
 zImage
 zImage.tmp
+calc_vmlinuz_load_addr
diff --git a/arch/mips/boot/Makefile b/arch/mips/boot/Makefile
index e39a08edcaaa..85bcb5adc7cb 100644
--- a/arch/mips/boot/Makefile
+++ b/arch/mips/boot/Makefile
@@ -11,35 +11,32 @@
 # Some DECstations need all possible sections of an ECOFF executable
 #
 ifdef CONFIG_MACH_DECSTATION
-  E2EFLAGS = -a
-else
-  E2EFLAGS =
+  e2eflag := -a
 endif
 
 #
 # Drop some uninteresting sections in the kernel.
 # This is only relevant for ELF kernels but doesn't hurt a.out
 #
-drop-sections   = .reginfo .mdebug .comment .note .pdr .options .MIPS.options
-strip-flags     = $(addprefix --remove-section=,$(drop-sections))
-
-VMLINUX = vmlinux
-
-all: vmlinux.ecoff vmlinux.srec
-
-vmlinux.ecoff: $(obj)/elf2ecoff $(VMLINUX)
-        $(obj)/elf2ecoff $(VMLINUX) $(obj)/vmlinux.ecoff $(E2EFLAGS)
-
-$(obj)/elf2ecoff: $(obj)/elf2ecoff.c
-        $(HOSTCC) -o $@ $^
-
-vmlinux.bin: $(VMLINUX)
-        $(OBJCOPY) -O binary $(strip-flags) $(VMLINUX) $(obj)/vmlinux.bin
-
-vmlinux.srec: $(VMLINUX)
-        $(OBJCOPY) -S -O srec $(strip-flags) $(VMLINUX) $(obj)/vmlinux.srec
-
-clean-files += elf2ecoff \
-               vmlinux.bin \
-               vmlinux.ecoff \
-               vmlinux.srec
+drop-sections := .reginfo .mdebug .comment .note .pdr .options .MIPS.options
+strip-flags   := $(addprefix --remove-section=,$(drop-sections))
+
+hostprogs-y := elf2ecoff
+
+targets := vmlinux.ecoff
+quiet_cmd_ecoff = ECOFF   $@
+      cmd_ecoff = $(obj)/elf2ecoff $(VMLINUX) $@ $(e2eflag)
+$(obj)/vmlinux.ecoff: $(obj)/elf2ecoff $(VMLINUX) FORCE
+        $(call if_changed,ecoff)
+
+targets += vmlinux.bin
+quiet_cmd_bin = OBJCOPY $@
+      cmd_bin = $(OBJCOPY) -O binary $(strip-flags) $(VMLINUX) $@
+$(obj)/vmlinux.bin: $(VMLINUX) FORCE
+        $(call if_changed,bin)
+
+targets += vmlinux.srec
+quiet_cmd_srec = OBJCOPY $@
+      cmd_srec = $(OBJCOPY) -S -O srec $(strip-flags) $(VMLINUX) $@
+$(obj)/vmlinux.srec: $(VMLINUX) FORCE
+        $(call if_changed,srec)
diff --git a/arch/mips/boot/compressed/Makefile b/arch/mips/boot/compressed/Makefile
index 790ddd397620..ed9bb709c9a3 100644
--- a/arch/mips/boot/compressed/Makefile
+++ b/arch/mips/boot/compressed/Makefile
@@ -12,14 +12,6 @@
 # Author: Wu Zhangjin <wuzhangjin@gmail.com>
 #
 
-# compressed kernel load addr: VMLINUZ_LOAD_ADDRESS > VMLINUX_LOAD_ADDRESS + VMLINUX_SIZE
-VMLINUX_SIZE := $(shell wc -c $(objtree)/$(KBUILD_IMAGE) 2>/dev/null | cut -d' ' -f1)
-VMLINUX_SIZE := $(shell [ -n "$(VMLINUX_SIZE)" ] && echo -n $$(($(VMLINUX_SIZE) + (65536 - $(VMLINUX_SIZE) % 65536))))
-# VMLINUZ_LOAD_ADDRESS = concat "high32 of VMLINUX_LOAD_ADDRESS" and "(low32 of VMLINUX_LOAD_ADDRESS) + VMLINUX_SIZE"
-HIGH32 := $(shell A=$(VMLINUX_LOAD_ADDRESS); [ $${\#A} -gt 10 ] && expr substr "$(VMLINUX_LOAD_ADDRESS)" 3 $$(($${\#A} - 10)))
-LOW32 := $(shell [ -n "$(HIGH32)" ] && A=11 || A=3; expr substr "$(VMLINUX_LOAD_ADDRESS)" $${A} 8)
-VMLINUZ_LOAD_ADDRESS := 0x$(shell [ -n "$(VMLINUX_SIZE)" -a -n "$(LOW32)" ] && printf "$(HIGH32)%08x" $$(($(VMLINUX_SIZE) + 0x$(LOW32))))
-
 # set the default size of the mallocing area for decompressing
 BOOT_HEAP_SIZE := 0x400000
 
@@ -33,49 +25,61 @@ KBUILD_AFLAGS := $(LINUXINCLUDE) $(KBUILD_AFLAGS) -D__ASSEMBLY__ \
         -DBOOT_HEAP_SIZE=$(BOOT_HEAP_SIZE) \
         -DKERNEL_ENTRY=0x$(shell $(NM) $(objtree)/$(KBUILD_IMAGE) 2>/dev/null | grep " kernel_entry" | cut -f1 -d \ )
 
-obj-y := $(obj)/head.o $(obj)/decompress.o $(obj)/dbg.o
+targets := head.o decompress.o dbg.o uart-16550.o uart-alchemy.o
+
+# decompressor objects (linked with vmlinuz)
+vmlinuzobjs-y := $(obj)/head.o $(obj)/decompress.o $(obj)/dbg.o
 
 ifdef CONFIG_DEBUG_ZBOOT
-obj-$(CONFIG_SYS_SUPPORTS_ZBOOT_UART16550) += $(obj)/uart-16550.o
-obj-$(CONFIG_MACH_ALCHEMY)                 += $(obj)/uart-alchemy.o
+vmlinuzobjs-$(CONFIG_SYS_SUPPORTS_ZBOOT_UART16550) += $(obj)/uart-16550.o
+vmlinuzobjs-$(CONFIG_MIPS_ALCHEMY)                 += $(obj)/uart-alchemy.o
 endif
 
+targets += vmlinux.bin
 OBJCOPYFLAGS_vmlinux.bin := $(OBJCOPYFLAGS) -O binary -R .comment -S
-$(obj)/vmlinux.bin: $(KBUILD_IMAGE)
+$(obj)/vmlinux.bin: $(KBUILD_IMAGE) FORCE
         $(call if_changed,objcopy)
 
-suffix_$(CONFIG_KERNEL_GZIP)  = gz
-suffix_$(CONFIG_KERNEL_BZIP2) = bz2
-suffix_$(CONFIG_KERNEL_LZMA)  = lzma
-suffix_$(CONFIG_KERNEL_LZO)   = lzo
 tool_$(CONFIG_KERNEL_GZIP)    = gzip
 tool_$(CONFIG_KERNEL_BZIP2)   = bzip2
 tool_$(CONFIG_KERNEL_LZMA)    = lzma
 tool_$(CONFIG_KERNEL_LZO)     = lzo
-$(obj)/vmlinux.$(suffix_y): $(obj)/vmlinux.bin
+
+targets += vmlinux.bin.z
+$(obj)/vmlinux.bin.z: $(obj)/vmlinux.bin FORCE
         $(call if_changed,$(tool_y))
 
-$(obj)/piggy.o: $(obj)/vmlinux.$(suffix_y) $(obj)/dummy.o
-        $(Q)$(OBJCOPY) $(OBJCOPYFLAGS) \
-                --add-section=.image=$< \
-                --set-section-flags=.image=contents,alloc,load,readonly,data \
-                $(obj)/dummy.o $@
+targets += piggy.o
+OBJCOPYFLAGS_piggy.o := --add-section=.image=$(obj)/vmlinux.bin.z \
+                        --set-section-flags=.image=contents,alloc,load,readonly,data
+$(obj)/piggy.o: $(obj)/dummy.o $(obj)/vmlinux.bin.z FORCE
+        $(call if_changed,objcopy)
+
+# Calculate the load address of the compressed kernel image
+hostprogs-y := calc_vmlinuz_load_addr
+
+VMLINUZ_LOAD_ADDRESS = $(shell $(obj)/calc_vmlinuz_load_addr \
+                $(objtree)/$(KBUILD_IMAGE) $(VMLINUX_LOAD_ADDRESS))
 
-LDFLAGS_vmlinuz := $(LDFLAGS) -Ttext $(VMLINUZ_LOAD_ADDRESS) -T
-vmlinuz: $(src)/ld.script $(obj-y) $(obj)/piggy.o
-        $(call if_changed,ld)
-        $(Q)$(OBJCOPY) $(OBJCOPYFLAGS) $@
+vmlinuzobjs-y += $(obj)/piggy.o
+
+quiet_cmd_zld = LD      $@
+      cmd_zld = $(LD) $(LDFLAGS) -Ttext $(VMLINUZ_LOAD_ADDRESS) -T $< $(vmlinuzobjs-y) -o $@
+quiet_cmd_strip = STRIP   $@
+      cmd_strip = $(STRIP) -s $@
+vmlinuz: $(src)/ld.script $(vmlinuzobjs-y) $(obj)/calc_vmlinuz_load_addr
+        $(call cmd,zld)
+        $(call cmd,strip)
 
 #
 # Some DECstations need all possible sections of an ECOFF executable
 #
 ifdef CONFIG_MACH_DECSTATION
-  E2EFLAGS = -a
-else
-  E2EFLAGS =
+  e2eflag := -a
 endif
 
 # elf2ecoff can only handle 32bit image
+hostprogs-y += ../elf2ecoff
 
 ifdef CONFIG_32BIT
         VMLINUZ = vmlinuz
@@ -83,23 +87,22 @@ else
         VMLINUZ = vmlinuz.32
 endif
 
+quiet_cmd_32 = OBJCOPY $@
+      cmd_32 = $(OBJCOPY) -O $(32bit-bfd) $(OBJCOPYFLAGS) $< $@
 vmlinuz.32: vmlinuz
-        $(Q)$(OBJCOPY) -O $(32bit-bfd) $(OBJCOPYFLAGS) $< $@
+        $(call cmd,32)
 
+quiet_cmd_ecoff = ECOFF   $@
+      cmd_ecoff = $< $(VMLINUZ) $@ $(e2eflag)
 vmlinuz.ecoff: $(obj)/../elf2ecoff $(VMLINUZ)
-        $(Q)$(obj)/../elf2ecoff $(VMLINUZ) vmlinuz.ecoff $(E2EFLAGS)
-
-$(obj)/../elf2ecoff: $(src)/../elf2ecoff.c
-        $(Q)$(HOSTCC) -o $@ $^
+        $(call cmd,ecoff)
 
 OBJCOPYFLAGS_vmlinuz.bin := $(OBJCOPYFLAGS) -O binary
 vmlinuz.bin: vmlinuz
-        $(call if_changed,objcopy)
+        $(call cmd,objcopy)
 
 OBJCOPYFLAGS_vmlinuz.srec := $(OBJCOPYFLAGS) -S -O srec
 vmlinuz.srec: vmlinuz
-        $(call if_changed,objcopy)
+        $(call cmd,objcopy)
 
-clean:
-clean-files += *.o \
-               vmlinu*
+clean-files := $(objtree)/vmlinuz.*
diff --git a/arch/mips/boot/compressed/calc_vmlinuz_load_addr.c b/arch/mips/boot/compressed/calc_vmlinuz_load_addr.c
new file mode 100644
index 000000000000..88c9d963be88
--- /dev/null
+++ b/arch/mips/boot/compressed/calc_vmlinuz_load_addr.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2010 "Wu Zhangjin" <wuzhangjin@gmail.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <errno.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+
+int main(int argc, char *argv[])
+{
+        struct stat sb;
+        uint64_t vmlinux_size, vmlinux_load_addr, vmlinuz_load_addr;
+
+        if (argc != 3) {
+                fprintf(stderr, "Usage: %s <pathname> <vmlinux_load_addr>\n",
+                                argv[0]);
+                return EXIT_FAILURE;
+        }
+
+        if (stat(argv[1], &sb) == -1) {
+                perror("stat");
+                return EXIT_FAILURE;
+        }
+
+        /* Convert hex characters to dec number */
+        errno = 0;
+        if (sscanf(argv[2], "%llx", &vmlinux_load_addr) != 1) {
+                if (errno != 0)
+                        perror("sscanf");
+                else
+                        fprintf(stderr, "No matching characters\n");
+
+                return EXIT_FAILURE;
+        }
+
+        vmlinux_size = (uint64_t)sb.st_size;
+        vmlinuz_load_addr = vmlinux_load_addr + vmlinux_size;
+
+        /*
+         * Align with 16 bytes: "greater than that used for any standard data
+         * types by a MIPS compiler." -- See MIPS Run Linux (Second Edition).
+         */
+
+        vmlinuz_load_addr += (16 - vmlinux_size % 16);
+
+        printf("0x%llx\n", vmlinuz_load_addr);
+
+        return EXIT_SUCCESS;
+}
diff --git a/arch/mips/boot/compressed/decompress.c b/arch/mips/boot/compressed/decompress.c
index 5db43c58b1bf..5cad0faefa17 100644
--- a/arch/mips/boot/compressed/decompress.c
+++ b/arch/mips/boot/compressed/decompress.c
@@ -1,9 +1,6 @@
 /*
- * Misc. bootloader code for many machines.
- *
  * Copyright 2001 MontaVista Software Inc.
- * Author: Matt Porter <mporter@mvista.com> Derived from
- * arch/ppc/boot/prep/misc.c
+ * Author: Matt Porter <mporter@mvista.com>
  *
  * Copyright (C) 2009 Lemote, Inc.
  * Author: Wu Zhangjin <wuzhangjin@gmail.com>
@@ -19,12 +16,12 @@
 
 #include <asm/addrspace.h>
 
-/* These two variables specify the free mem region
+/*
+ * These two variables specify the free mem region
  * that can be used for temporary malloc area
  */
 unsigned long free_mem_ptr;
 unsigned long free_mem_end_ptr;
-char *zimage_start;
 
 /* The linker tells us where the image is. */
 extern unsigned char __image_begin, __image_end;
@@ -83,38 +80,31 @@ void *memset(void *s, int c, size_t n)
 
 void decompress_kernel(unsigned long boot_heap_start)
 {
-        int zimage_size;
-
-        /*
-         * We link ourself to an arbitrary low address.  When we run, we
-         * relocate outself to that address.  __image_beign points to
-         * the part of the image where the zImage is. -- Tom
-         */
-        zimage_start = (char *)(unsigned long)(&__image_begin);
+        unsigned long zimage_start, zimage_size;
+
+        zimage_start = (unsigned long)(&__image_begin);
         zimage_size = (unsigned long)(&__image_end) -
             (unsigned long)(&__image_begin);
 
-        /*
-         * The zImage and initrd will be between start and _end, so they've
-         * already been moved once.  We're good to go now. -- Tom
-         */
         puts("zimage at:     ");
-        puthex((unsigned long)zimage_start);
+        puthex(zimage_start);
         puts(" ");
-        puthex((unsigned long)(zimage_size + zimage_start));
+        puthex(zimage_size + zimage_start);
         puts("\n");
 
-        /* this area are prepared for mallocing when decompressing */
+        /* This area are prepared for mallocing when decompressing */
         free_mem_ptr = boot_heap_start;
         free_mem_end_ptr = boot_heap_start + BOOT_HEAP_SIZE;
 
-        /* Display standard Linux/MIPS boot prompt for kernel args */
+        /* Display standard Linux/MIPS boot prompt */
         puts("Uncompressing Linux at load address ");
         puthex(VMLINUX_LOAD_ADDRESS_ULL);
         puts("\n");
+
         /* Decompress the kernel with according algorithm */
-        decompress(zimage_start, zimage_size, 0, 0,
+        decompress((char *)zimage_start, zimage_size, 0, 0,
                    (void *)VMLINUX_LOAD_ADDRESS_ULL, 0, error);
-        /* FIXME: is there a need to flush cache here? */
+
+        /* FIXME: should we flush cache here? */
         puts("Now, booting the kernel...\n");
 }
diff --git a/arch/mips/boot/compressed/ld.script b/arch/mips/boot/compressed/ld.script
index 613a35b02f50..8e6b07ca2f5e 100644
--- a/arch/mips/boot/compressed/ld.script
+++ b/arch/mips/boot/compressed/ld.script
@@ -2,61 +2,44 @@
  * ld.script for compressed kernel support of MIPS
  *
  * Copyright (C) 2009 Lemote Inc.
- * Author: Wu Zhangjin <wuzj@lemote.com>
+ * Author: Wu Zhangjin <wuzhanjing@gmail.com>
+ * Copyright (C) 2010 "Wu Zhangjin" <wuzhanjing@gmail.com>
  */
 
 OUTPUT_ARCH(mips)
 ENTRY(start)
 SECTIONS
 {
-        /* . = VMLINUZ_LOAD_ADDRESS */
-        /* read-only */
-        _text = .;      /* Text and read-only data */
-        .text   : {
-                _ftext = . ;
+        /* Text and read-only data */
+        /* . = VMLINUZ_LOAD_ADDRESS; */
+        .text : {
                 *(.text)
                 *(.rodata)
-        } = 0
-        _etext = .;     /* End of text section */
+        }
+        /* End of text section */
 
-        /* writable */
-        .data   : {     /* Data */
-                _fdata = . ;
+        /* Writable data */
+        .data : {
                 *(.data)
-                /* Put the compressed image here, so bss is on the end. */
+                /* Put the compressed image here */
                 __image_begin = .;
                 *(.image)
                 __image_end = .;
                 CONSTRUCTORS
         }
-        .sdata  : { *(.sdata) }
-        . = ALIGN(4);
-        _edata  =  .;   /* End of data section */
+        . = ALIGN(16);
+        _edata = .;
+        /* End of data section */
 
         /* BSS */
-        __bss_start = .;
-        _fbss = .;
-        .sbss   : { *(.sbss) *(.scommon) }
-        .bss    : {
-                *(.dynbss)
+        .bss : {
                 *(.bss)
-                *(COMMON)
         }
-        .  = ALIGN(4);
-        _end = . ;
-
-        /* These are needed for ELF backends which have not yet been converted
-         * to the new style linker.  */
-
-        .stab 0 : { *(.stab) }
-        .stabstr 0 : { *(.stabstr) }
-
-        /* These must appear regardless of  .  */
-        .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }
-        .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }
+        . = ALIGN(16);
+        _end = .;
 
         /* Sections to be discarded */
-        /DISCARD/       : {
+        /DISCARD/ : {
                 *(.MIPS.options)
                 *(.options)
                 *(.pdr)
diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile
index 3e9876317e61..19eb0434269f 100644
--- a/arch/mips/cavium-octeon/Makefile
+++ b/arch/mips/cavium-octeon/Makefile
@@ -12,7 +12,6 @@
 obj-y := cpu.o setup.o serial.o octeon-platform.o octeon-irq.o csrc-octeon.o
 obj-y += dma-octeon.o flash_setup.o
 obj-y += octeon-memcpy.o
+obj-y += executive/
 
 obj-$(CONFIG_SMP)                     += smp.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/cavium-octeon/Platform b/arch/mips/cavium-octeon/Platform
new file mode 100644
index 000000000000..1e43ccf1a792
--- /dev/null
+++ b/arch/mips/cavium-octeon/Platform
@@ -0,0 +1,11 @@
+#
+# Cavium Octeon
+#
+platform-$(CONFIG_CPU_CAVIUM_OCTEON)    += cavium-octeon/
+cflags-$(CONFIG_CPU_CAVIUM_OCTEON)      +=                              \
+                -I$(srctree)/arch/mips/include/asm/mach-cavium-octeon
+ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
+load-$(CONFIG_CPU_CAVIUM_OCTEON)        += 0xffffffff84100000
+else
+load-$(CONFIG_CPU_CAVIUM_OCTEON)        += 0xffffffff81100000
+endif
diff --git a/arch/mips/cavium-octeon/cpu.c b/arch/mips/cavium-octeon/cpu.c
index b6df5387e855..c664c8cc2b42 100644
--- a/arch/mips/cavium-octeon/cpu.c
+++ b/arch/mips/cavium-octeon/cpu.c
@@ -41,12 +41,8 @@ static int cnmips_cu2_call(struct notifier_block *nfb, unsigned long action,
         return NOTIFY_OK;               /* Let default notifier send signals */
 }
 
-static struct notifier_block cnmips_cu2_notifier = {
-        .notifier_call = cnmips_cu2_call,
-};
-
 static int cnmips_cu2_setup(void)
 {
-        return register_cu2_notifier(&cnmips_cu2_notifier);
+        return cu2_notifier(cnmips_cu2_call, 0);
 }
 early_initcall(cnmips_cu2_setup);
diff --git a/arch/mips/cavium-octeon/csrc-octeon.c b/arch/mips/cavium-octeon/csrc-octeon.c
index 0bf4bbe04ae2..b6847c8e0ddd 100644
--- a/arch/mips/cavium-octeon/csrc-octeon.c
+++ b/arch/mips/cavium-octeon/csrc-octeon.c
@@ -53,7 +53,6 @@ static struct clocksource clocksource_mips = {
 unsigned long long notrace sched_clock(void)
 {
         /* 64-bit arithmatic can overflow, so use 128-bit.  */
-#if (__GNUC__ < 4) || ((__GNUC__ == 4) && (__GNUC_MINOR__ <= 3))
         u64 t1, t2, t3;
         unsigned long long rv;
         u64 mult = clocksource_mips.mult;
@@ -73,13 +72,6 @@ unsigned long long notrace sched_clock(void)
                 : [cnt] "r" (cnt), [mult] "r" (mult), [shift] "r" (shift)
                 : "hi", "lo");
         return rv;
-#else
-        /* GCC > 4.3 do it the easy way.  */
-        unsigned int __attribute__((mode(TI))) t;
-        t = read_c0_cvmcount();
-        t = t * clocksource_mips.mult;
-        return (unsigned long long)(t >> clocksource_mips.shift);
-#endif
 }
 
 void __init plat_time_init(void)
@@ -88,3 +80,58 @@ void __init plat_time_init(void)
         clocksource_set_clock(&clocksource_mips, mips_hpt_frequency);
         clocksource_register(&clocksource_mips);
 }
+
+static u64 octeon_udelay_factor;
+static u64 octeon_ndelay_factor;
+
+void __init octeon_setup_delays(void)
+{
+        octeon_udelay_factor = octeon_get_clock_rate() / 1000000;
+        /*
+         * For __ndelay we divide by 2^16, so the factor is multiplied
+         * by the same amount.
+         */
+        octeon_ndelay_factor = (octeon_udelay_factor * 0x10000ull) / 1000ull;
+
+        preset_lpj = octeon_get_clock_rate() / HZ;
+}
+
+void __udelay(unsigned long us)
+{
+        u64 cur, end, inc;
+
+        cur = read_c0_cvmcount();
+
+        inc = us * octeon_udelay_factor;
+        end = cur + inc;
+
+        while (end > cur)
+                cur = read_c0_cvmcount();
+}
+EXPORT_SYMBOL(__udelay);
+
+void __ndelay(unsigned long ns)
+{
+        u64 cur, end, inc;
+
+        cur = read_c0_cvmcount();
+
+        inc = ((ns * octeon_ndelay_factor) >> 16);
+        end = cur + inc;
+
+        while (end > cur)
+                cur = read_c0_cvmcount();
+}
+EXPORT_SYMBOL(__ndelay);
+
+void __delay(unsigned long loops)
+{
+        u64 cur, end;
+
+        cur = read_c0_cvmcount();
+        end = cur + loops;
+
+        while (end > cur)
+                cur = read_c0_cvmcount();
+}
+EXPORT_SYMBOL(__delay);
diff --git a/arch/mips/cavium-octeon/dma-octeon.c b/arch/mips/cavium-octeon/dma-octeon.c
index be531ec1f206..d22b5a2d64f4 100644
--- a/arch/mips/cavium-octeon/dma-octeon.c
+++ b/arch/mips/cavium-octeon/dma-octeon.c
@@ -99,13 +99,16 @@ dma_addr_t octeon_map_dma_mem(struct device *dev, void *ptr, size_t size)
                         panic("dma_map_single: "
                               "Attempt to map illegal memory address 0x%llx\n",
                               physical);
-                else if ((physical + size >=
-                          (4ull<<30) - (OCTEON_PCI_BAR1_HOLE_SIZE<<20))
-                         && physical < (4ull<<30))
-                        pr_warning("dma_map_single: Warning: "
-                                   "Mapping memory address that might "
-                                   "conflict with devices 0x%llx-0x%llx\n",
-                                   physical, physical+size-1);
+                else if (physical >= CVMX_PCIE_BAR1_PHYS_BASE &&
+                         physical + size < (CVMX_PCIE_BAR1_PHYS_BASE + CVMX_PCIE_BAR1_PHYS_SIZE)) {
+                        result = physical - CVMX_PCIE_BAR1_PHYS_BASE + CVMX_PCIE_BAR1_RC_BASE;
+
+                        if (((result+size-1) & dma_mask) != result+size-1)
+                                panic("dma_map_single: Attempt to map address 0x%llx-0x%llx, which can't be accessed according to the dma mask 0x%llx\n",
+                                      physical, physical+size-1, dma_mask);
+                        goto done;
+                }
+
                 /* The 2nd 256MB is mapped at 256<<20 instead of 0x410000000 */
                 if ((physical >= 0x410000000ull) && physical < 0x420000000ull)
                         result = physical - 0x400000000ull;
diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c
index c424cd158dc6..ce7500cdf5b7 100644
--- a/arch/mips/cavium-octeon/octeon-irq.c
+++ b/arch/mips/cavium-octeon/octeon-irq.c
@@ -3,15 +3,13 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 2004-2008 Cavium Networks
+ * Copyright (C) 2004-2008, 2009, 2010 Cavium Networks
  */
 #include <linux/irq.h>
 #include <linux/interrupt.h>
 #include <linux/smp.h>
 
 #include <asm/octeon/octeon.h>
-#include <asm/octeon/cvmx-pexp-defs.h>
-#include <asm/octeon/cvmx-npi-defs.h>
 
 static DEFINE_RAW_SPINLOCK(octeon_irq_ciu0_lock);
 static DEFINE_RAW_SPINLOCK(octeon_irq_ciu1_lock);
@@ -41,14 +39,14 @@ static void octeon_irq_core_ack(unsigned int irq)
 
 static void octeon_irq_core_eoi(unsigned int irq)
 {
-        struct irq_desc *desc = irq_desc + irq;
+        struct irq_desc *desc = irq_to_desc(irq);
         unsigned int bit = irq - OCTEON_IRQ_SW0;
         /*
          * If an IRQ is being processed while we are disabling it the
          * handler will attempt to unmask the interrupt after it has
          * been disabled.
          */
-        if (desc->status & IRQ_DISABLED)
+        if ((unlikely(desc->status & IRQ_DISABLED)))
                 return;
         /*
          * We don't need to disable IRQs to make these atomic since
@@ -106,6 +104,29 @@ static struct irq_chip octeon_irq_chip_core = {
 
 static void octeon_irq_ciu0_ack(unsigned int irq)
 {
+        switch (irq) {
+        case OCTEON_IRQ_GMX_DRP0:
+        case OCTEON_IRQ_GMX_DRP1:
+        case OCTEON_IRQ_IPD_DRP:
+        case OCTEON_IRQ_KEY_ZERO:
+        case OCTEON_IRQ_TIMER0:
+        case OCTEON_IRQ_TIMER1:
+        case OCTEON_IRQ_TIMER2:
+        case OCTEON_IRQ_TIMER3:
+        {
+                int index = cvmx_get_core_num() * 2;
+                u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
+                /*
+                 * CIU timer type interrupts must be acknoleged by
+                 * writing a '1' bit to their sum0 bit.
+                 */
+                cvmx_write_csr(CVMX_CIU_INTX_SUM0(index), mask);
+                break;
+        }
+        default:
+                break;
+        }
+
         /*
          * In order to avoid any locking accessing the CIU, we
          * acknowledge CIU interrupts by disabling all of them.  This
@@ -130,8 +151,54 @@ static void octeon_irq_ciu0_eoi(unsigned int irq)
         set_c0_status(0x100 << 2);
 }
 
+static int next_coreid_for_irq(struct irq_desc *desc)
+{
+
+#ifdef CONFIG_SMP
+        int coreid;
+        int weight = cpumask_weight(desc->affinity);
+
+        if (weight > 1) {
+                int cpu = smp_processor_id();
+                for (;;) {
+                        cpu = cpumask_next(cpu, desc->affinity);
+                        if (cpu >= nr_cpu_ids) {
+                                cpu = -1;
+                                continue;
+                        } else if (cpumask_test_cpu(cpu, cpu_online_mask)) {
+                                break;
+                        }
+                }
+                coreid = octeon_coreid_for_cpu(cpu);
+        } else if (weight == 1) {
+                coreid = octeon_coreid_for_cpu(cpumask_first(desc->affinity));
+        } else {
+                coreid = cvmx_get_core_num();
+        }
+        return coreid;
+#else
+        return cvmx_get_core_num();
+#endif
+}
+
 static void octeon_irq_ciu0_enable(unsigned int irq)
 {
+        struct irq_desc *desc = irq_to_desc(irq);
+        int coreid = next_coreid_for_irq(desc);
+        unsigned long flags;
+        uint64_t en0;
+        int bit = irq - OCTEON_IRQ_WORKQ0;      /* Bit 0-63 of EN0 */
+
+        raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags);
+        en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
+        en0 |= 1ull << bit;
+        cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0);
+        cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
+        raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags);
+}
+
+static void octeon_irq_ciu0_enable_mbox(unsigned int irq)
+{
         int coreid = cvmx_get_core_num();
         unsigned long flags;
         uint64_t en0;
@@ -167,63 +234,76 @@ static void octeon_irq_ciu0_disable(unsigned int irq)
 }
 
 /*
- * Enable the irq on the current core for chips that have the EN*_W1{S,C}
- * registers.
+ * Enable the irq on the next core in the affinity set for chips that
+ * have the EN*_W1{S,C} registers.
  */
 static void octeon_irq_ciu0_enable_v2(unsigned int irq)
 {
-        int index = cvmx_get_core_num() * 2;
+        int index;
         u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
+        struct irq_desc *desc = irq_to_desc(irq);
 
-        cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
+        if ((desc->status & IRQ_DISABLED) == 0) {
+                index = next_coreid_for_irq(desc) * 2;
+                cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
+        }
 }
 
 /*
- * Disable the irq on the current core for chips that have the EN*_W1{S,C}
- * registers.
+ * Enable the irq on the current CPU for chips that
+ * have the EN*_W1{S,C} registers.
  */
-static void octeon_irq_ciu0_ack_v2(unsigned int irq)
+static void octeon_irq_ciu0_enable_mbox_v2(unsigned int irq)
 {
-        int index = cvmx_get_core_num() * 2;
+        int index;
         u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
 
-        cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
+        index = cvmx_get_core_num() * 2;
+        cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
 }
 
 /*
- * CIU timer type interrupts must be acknoleged by writing a '1' bit
- * to their sum0 bit.
+ * Disable the irq on the current core for chips that have the EN*_W1{S,C}
+ * registers.
  */
-static void octeon_irq_ciu0_timer_ack(unsigned int irq)
+static void octeon_irq_ciu0_ack_v2(unsigned int irq)
 {
         int index = cvmx_get_core_num() * 2;
-        uint64_t mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
-        cvmx_write_csr(CVMX_CIU_INTX_SUM0(index), mask);
-}
+        u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
 
-static void octeon_irq_ciu0_timer_ack_v1(unsigned int irq)
-{
-        octeon_irq_ciu0_timer_ack(irq);
-        octeon_irq_ciu0_ack(irq);
-}
+        switch (irq) {
+        case OCTEON_IRQ_GMX_DRP0:
+        case OCTEON_IRQ_GMX_DRP1:
+        case OCTEON_IRQ_IPD_DRP:
+        case OCTEON_IRQ_KEY_ZERO:
+        case OCTEON_IRQ_TIMER0:
+        case OCTEON_IRQ_TIMER1:
+        case OCTEON_IRQ_TIMER2:
+        case OCTEON_IRQ_TIMER3:
+                /*
+                 * CIU timer type interrupts must be acknoleged by
+                 * writing a '1' bit to their sum0 bit.
+                 */
+                cvmx_write_csr(CVMX_CIU_INTX_SUM0(index), mask);
+                break;
+        default:
+                break;
+        }
 
-static void octeon_irq_ciu0_timer_ack_v2(unsigned int irq)
-{
-        octeon_irq_ciu0_timer_ack(irq);
-        octeon_irq_ciu0_ack_v2(irq);
+        cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
 }
 
 /*
  * Enable the irq on the current core for chips that have the EN*_W1{S,C}
  * registers.
  */
-static void octeon_irq_ciu0_eoi_v2(unsigned int irq)
+static void octeon_irq_ciu0_eoi_mbox_v2(unsigned int irq)
 {
-        struct irq_desc *desc = irq_desc + irq;
+        struct irq_desc *desc = irq_to_desc(irq);
         int index = cvmx_get_core_num() * 2;
         u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
 
-        if ((desc->status & IRQ_DISABLED) == 0)
+        if (likely((desc->status & IRQ_DISABLED) == 0))
                 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
 }
 
@@ -246,18 +326,30 @@ static void octeon_irq_ciu0_disable_all_v2(unsigned int irq)
 static int octeon_irq_ciu0_set_affinity(unsigned int irq, const struct cpumask *dest)
 {
         int cpu;
+        struct irq_desc *desc = irq_to_desc(irq);
+        int enable_one = (desc->status & IRQ_DISABLED) == 0;
         unsigned long flags;
         int bit = irq - OCTEON_IRQ_WORKQ0;      /* Bit 0-63 of EN0 */
 
+        /*
+         * For non-v2 CIU, we will allow only single CPU affinity.
+         * This removes the need to do locking in the .ack/.eoi
+         * functions.
+         */
+        if (cpumask_weight(dest) != 1)
+                return -EINVAL;
+
         raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags);
         for_each_online_cpu(cpu) {
                 int coreid = octeon_coreid_for_cpu(cpu);
                 uint64_t en0 =
                         cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
-                if (cpumask_test_cpu(cpu, dest))
+                if (cpumask_test_cpu(cpu, dest) && enable_one) {
+                        enable_one = 0;
                         en0 |= 1ull << bit;
-                else
+                } else {
                         en0 &= ~(1ull << bit);
+                }
                 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0);
         }
         /*
@@ -279,13 +371,18 @@ static int octeon_irq_ciu0_set_affinity_v2(unsigned int irq,
 {
         int cpu;
         int index;
+        struct irq_desc *desc = irq_to_desc(irq);
+        int enable_one = (desc->status & IRQ_DISABLED) == 0;
         u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
+
         for_each_online_cpu(cpu) {
                 index = octeon_coreid_for_cpu(cpu) * 2;
-                if (cpumask_test_cpu(cpu, dest))
+                if (cpumask_test_cpu(cpu, dest) && enable_one) {
+                        enable_one = 0;
                         cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
-                else
+                } else {
                         cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
+                }
         }
         return 0;
 }
@@ -298,8 +395,7 @@ static struct irq_chip octeon_irq_chip_ciu0_v2 = {
         .name = "CIU0",
         .enable = octeon_irq_ciu0_enable_v2,
         .disable = octeon_irq_ciu0_disable_all_v2,
-        .ack = octeon_irq_ciu0_ack_v2,
-        .eoi = octeon_irq_ciu0_eoi_v2,
+        .eoi = octeon_irq_ciu0_enable_v2,
 #ifdef CONFIG_SMP
         .set_affinity = octeon_irq_ciu0_set_affinity_v2,
 #endif
@@ -309,36 +405,27 @@ static struct irq_chip octeon_irq_chip_ciu0 = {
         .name = "CIU0",
         .enable = octeon_irq_ciu0_enable,
         .disable = octeon_irq_ciu0_disable,
-        .ack = octeon_irq_ciu0_ack,
         .eoi = octeon_irq_ciu0_eoi,
 #ifdef CONFIG_SMP
         .set_affinity = octeon_irq_ciu0_set_affinity,
 #endif
 };
 
-static struct irq_chip octeon_irq_chip_ciu0_timer_v2 = {
-        .name = "CIU0-T",
-        .enable = octeon_irq_ciu0_enable_v2,
-        .disable = octeon_irq_ciu0_disable_all_v2,
-        .ack = octeon_irq_ciu0_timer_ack_v2,
-        .eoi = octeon_irq_ciu0_eoi_v2,
-#ifdef CONFIG_SMP
-        .set_affinity = octeon_irq_ciu0_set_affinity_v2,
-#endif
+/* The mbox versions don't do any affinity or round-robin. */
+static struct irq_chip octeon_irq_chip_ciu0_mbox_v2 = {
+        .name = "CIU0-M",
+        .enable = octeon_irq_ciu0_enable_mbox_v2,
+        .disable = octeon_irq_ciu0_disable,
+        .eoi = octeon_irq_ciu0_eoi_mbox_v2,
 };
 
-static struct irq_chip octeon_irq_chip_ciu0_timer = {
-        .name = "CIU0-T",
-        .enable = octeon_irq_ciu0_enable,
+static struct irq_chip octeon_irq_chip_ciu0_mbox = {
+        .name = "CIU0-M",
+        .enable = octeon_irq_ciu0_enable_mbox,
         .disable = octeon_irq_ciu0_disable,
-        .ack = octeon_irq_ciu0_timer_ack_v1,
         .eoi = octeon_irq_ciu0_eoi,
-#ifdef CONFIG_SMP
-        .set_affinity = octeon_irq_ciu0_set_affinity,
-#endif
 };
 
-
 static void octeon_irq_ciu1_ack(unsigned int irq)
 {
         /*
@@ -365,10 +452,30 @@ static void octeon_irq_ciu1_eoi(unsigned int irq)
 
 static void octeon_irq_ciu1_enable(unsigned int irq)
 {
-        int coreid = cvmx_get_core_num();
+        struct irq_desc *desc = irq_to_desc(irq);
+        int coreid = next_coreid_for_irq(desc);
+        unsigned long flags;
+        uint64_t en1;
+        int bit = irq - OCTEON_IRQ_WDOG0;       /* Bit 0-63 of EN1 */
+
+        raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
+        en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
+        en1 |= 1ull << bit;
+        cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1);
+        cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
+        raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags);
+}
+
+/*
+ * Watchdog interrupts are special.  They are associated with a single
+ * core, so we hardwire the affinity to that core.
+ */
+static void octeon_irq_ciu1_wd_enable(unsigned int irq)
+{
         unsigned long flags;
         uint64_t en1;
         int bit = irq - OCTEON_IRQ_WDOG0;       /* Bit 0-63 of EN1 */
+        int coreid = bit;
 
         raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
         en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
@@ -405,36 +512,43 @@ static void octeon_irq_ciu1_disable(unsigned int irq)
  */
 static void octeon_irq_ciu1_enable_v2(unsigned int irq)
 {
-        int index = cvmx_get_core_num() * 2 + 1;
+        int index;
         u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
+        struct irq_desc *desc = irq_to_desc(irq);
 
-        cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
+        if ((desc->status & IRQ_DISABLED) == 0) {
+                index = next_coreid_for_irq(desc) * 2 + 1;
+                cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
+        }
 }
 
 /*
- * Disable the irq on the current core for chips that have the EN*_W1{S,C}
- * registers.
+ * Watchdog interrupts are special.  They are associated with a single
+ * core, so we hardwire the affinity to that core.
  */
-static void octeon_irq_ciu1_ack_v2(unsigned int irq)
+static void octeon_irq_ciu1_wd_enable_v2(unsigned int irq)
 {
-        int index = cvmx_get_core_num() * 2 + 1;
+        int index;
+        int coreid = irq - OCTEON_IRQ_WDOG0;
         u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
+        struct irq_desc *desc = irq_to_desc(irq);
 
-        cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
+        if ((desc->status & IRQ_DISABLED) == 0) {
+                index = coreid * 2 + 1;
+                cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
+        }
 }
 
 /*
- * Enable the irq on the current core for chips that have the EN*_W1{S,C}
+ * Disable the irq on the current core for chips that have the EN*_W1{S,C}
  * registers.
  */
-static void octeon_irq_ciu1_eoi_v2(unsigned int irq)
+static void octeon_irq_ciu1_ack_v2(unsigned int irq)
 {
-        struct irq_desc *desc = irq_desc + irq;
         int index = cvmx_get_core_num() * 2 + 1;
         u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
 
-        if ((desc->status & IRQ_DISABLED) == 0)
-                cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
+        cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
 }
 
 /*
@@ -457,19 +571,30 @@ static int octeon_irq_ciu1_set_affinity(unsigned int irq,
                                         const struct cpumask *dest)
 {
         int cpu;
+        struct irq_desc *desc = irq_to_desc(irq);
+        int enable_one = (desc->status & IRQ_DISABLED) == 0;
         unsigned long flags;
         int bit = irq - OCTEON_IRQ_WDOG0;       /* Bit 0-63 of EN1 */
 
+        /*
+         * For non-v2 CIU, we will allow only single CPU affinity.
+         * This removes the need to do locking in the .ack/.eoi
+         * functions.
+         */
+        if (cpumask_weight(dest) != 1)
+                return -EINVAL;
+
         raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
         for_each_online_cpu(cpu) {
                 int coreid = octeon_coreid_for_cpu(cpu);
                 uint64_t en1 =
-                        cvmx_read_csr(CVMX_CIU_INTX_EN1
-                                (coreid * 2 + 1));
-                if (cpumask_test_cpu(cpu, dest))
+                        cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
+                if (cpumask_test_cpu(cpu, dest) && enable_one) {
+                        enable_one = 0;
                         en1 |= 1ull << bit;
-                else
+                } else {
                         en1 &= ~(1ull << bit);
+                }
                 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1);
         }
         /*
@@ -491,13 +616,17 @@ static int octeon_irq_ciu1_set_affinity_v2(unsigned int irq,
 {
         int cpu;
         int index;
+        struct irq_desc *desc = irq_to_desc(irq);
+        int enable_one = (desc->status & IRQ_DISABLED) == 0;
         u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
         for_each_online_cpu(cpu) {
                 index = octeon_coreid_for_cpu(cpu) * 2 + 1;
-                if (cpumask_test_cpu(cpu, dest))
+                if (cpumask_test_cpu(cpu, dest) && enable_one) {
+                        enable_one = 0;
                         cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
-                else
+                } else {
                         cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
+                }
         }
         return 0;
 }
@@ -507,11 +636,10 @@ static int octeon_irq_ciu1_set_affinity_v2(unsigned int irq,
  * Newer octeon chips have support for lockless CIU operation.
  */
 static struct irq_chip octeon_irq_chip_ciu1_v2 = {
-        .name = "CIU0",
+        .name = "CIU1",
         .enable = octeon_irq_ciu1_enable_v2,
         .disable = octeon_irq_ciu1_disable_all_v2,
-        .ack = octeon_irq_ciu1_ack_v2,
-        .eoi = octeon_irq_ciu1_eoi_v2,
+        .eoi = octeon_irq_ciu1_enable_v2,
 #ifdef CONFIG_SMP
         .set_affinity = octeon_irq_ciu1_set_affinity_v2,
 #endif
@@ -521,103 +649,36 @@ static struct irq_chip octeon_irq_chip_ciu1 = {
         .name = "CIU1",
         .enable = octeon_irq_ciu1_enable,
         .disable = octeon_irq_ciu1_disable,
-        .ack = octeon_irq_ciu1_ack,
         .eoi = octeon_irq_ciu1_eoi,
 #ifdef CONFIG_SMP
         .set_affinity = octeon_irq_ciu1_set_affinity,
 #endif
 };
 
-#ifdef CONFIG_PCI_MSI
-
-static DEFINE_RAW_SPINLOCK(octeon_irq_msi_lock);
-
-static void octeon_irq_msi_ack(unsigned int irq)
-{
-        if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) {
-                /* These chips have PCI */
-                cvmx_write_csr(CVMX_NPI_NPI_MSI_RCV,
-                               1ull << (irq - OCTEON_IRQ_MSI_BIT0));
-        } else {
-                /*
-                 * These chips have PCIe. Thankfully the ACK doesn't
-                 * need any locking.
-                 */
-                cvmx_write_csr(CVMX_PEXP_NPEI_MSI_RCV0,
-                               1ull << (irq - OCTEON_IRQ_MSI_BIT0));
-        }
-}
-
-static void octeon_irq_msi_eoi(unsigned int irq)
-{
-        /* Nothing needed */
-}
-
-static void octeon_irq_msi_enable(unsigned int irq)
-{
-        if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) {
-                /*
-                 * Octeon PCI doesn't have the ability to mask/unmask
-                 * MSI interrupts individually.  Instead of
-                 * masking/unmasking them in groups of 16, we simple
-                 * assume MSI devices are well behaved.  MSI
-                 * interrupts are always enable and the ACK is assumed
-                 * to be enough.
-                 */
-        } else {
-                /* These chips have PCIe.  Note that we only support
-                 * the first 64 MSI interrupts.  Unfortunately all the
-                 * MSI enables are in the same register.  We use
-                 * MSI0's lock to control access to them all.
-                 */
-                uint64_t en;
-                unsigned long flags;
-                raw_spin_lock_irqsave(&octeon_irq_msi_lock, flags);
-                en = cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0);
-                en |= 1ull << (irq - OCTEON_IRQ_MSI_BIT0);
-                cvmx_write_csr(CVMX_PEXP_NPEI_MSI_ENB0, en);
-                cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0);
-                raw_spin_unlock_irqrestore(&octeon_irq_msi_lock, flags);
-        }
-}
-
-static void octeon_irq_msi_disable(unsigned int irq)
-{
-        if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) {
-                /* See comment in enable */
-        } else {
-                /*
-                 * These chips have PCIe.  Note that we only support
-                 * the first 64 MSI interrupts.  Unfortunately all the
-                 * MSI enables are in the same register.  We use
-                 * MSI0's lock to control access to them all.
-                 */
-                uint64_t en;
-                unsigned long flags;
-                raw_spin_lock_irqsave(&octeon_irq_msi_lock, flags);
-                en = cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0);
-                en &= ~(1ull << (irq - OCTEON_IRQ_MSI_BIT0));
-                cvmx_write_csr(CVMX_PEXP_NPEI_MSI_ENB0, en);
-                cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0);
-                raw_spin_unlock_irqrestore(&octeon_irq_msi_lock, flags);
-        }
-}
+static struct irq_chip octeon_irq_chip_ciu1_wd_v2 = {
+        .name = "CIU1-W",
+        .enable = octeon_irq_ciu1_wd_enable_v2,
+        .disable = octeon_irq_ciu1_disable_all_v2,
+        .eoi = octeon_irq_ciu1_wd_enable_v2,
+};
 
-static struct irq_chip octeon_irq_chip_msi = {
-        .name = "MSI",
-        .enable = octeon_irq_msi_enable,
-        .disable = octeon_irq_msi_disable,
-        .ack = octeon_irq_msi_ack,
-        .eoi = octeon_irq_msi_eoi,
+static struct irq_chip octeon_irq_chip_ciu1_wd = {
+        .name = "CIU1-W",
+        .enable = octeon_irq_ciu1_wd_enable,
+        .disable = octeon_irq_ciu1_disable,
+        .eoi = octeon_irq_ciu1_eoi,
 };
-#endif
+
+static void (*octeon_ciu0_ack)(unsigned int);
+static void (*octeon_ciu1_ack)(unsigned int);
 
 void __init arch_init_irq(void)
 {
-        int irq;
+        unsigned int irq;
         struct irq_chip *chip0;
-        struct irq_chip *chip0_timer;
+        struct irq_chip *chip0_mbox;
         struct irq_chip *chip1;
+        struct irq_chip *chip1_wd;
 
 #ifdef CONFIG_SMP
         /* Set the default affinity to the boot cpu. */
@@ -631,13 +692,19 @@ void __init arch_init_irq(void)
         if (OCTEON_IS_MODEL(OCTEON_CN58XX_PASS2_X) ||
             OCTEON_IS_MODEL(OCTEON_CN56XX_PASS2_X) ||
             OCTEON_IS_MODEL(OCTEON_CN52XX_PASS2_X)) {
+                octeon_ciu0_ack = octeon_irq_ciu0_ack_v2;
+                octeon_ciu1_ack = octeon_irq_ciu1_ack_v2;
                 chip0 = &octeon_irq_chip_ciu0_v2;
-                chip0_timer = &octeon_irq_chip_ciu0_timer_v2;
+                chip0_mbox = &octeon_irq_chip_ciu0_mbox_v2;
                 chip1 = &octeon_irq_chip_ciu1_v2;
+                chip1_wd = &octeon_irq_chip_ciu1_wd_v2;
         } else {
+                octeon_ciu0_ack = octeon_irq_ciu0_ack;
+                octeon_ciu1_ack = octeon_irq_ciu1_ack;
                 chip0 = &octeon_irq_chip_ciu0;
-                chip0_timer = &octeon_irq_chip_ciu0_timer;
+                chip0_mbox = &octeon_irq_chip_ciu0_mbox;
                 chip1 = &octeon_irq_chip_ciu1;
+                chip1_wd = &octeon_irq_chip_ciu1_wd;
         }
 
         /* 0 - 15 reserved for i8259 master and slave controller. */
@@ -651,34 +718,23 @@ void __init arch_init_irq(void)
         /* 24 - 87 CIU_INT_SUM0 */
         for (irq = OCTEON_IRQ_WORKQ0; irq <= OCTEON_IRQ_BOOTDMA; irq++) {
                 switch (irq) {
-                case OCTEON_IRQ_GMX_DRP0:
-                case OCTEON_IRQ_GMX_DRP1:
-                case OCTEON_IRQ_IPD_DRP:
-                case OCTEON_IRQ_KEY_ZERO:
-                case OCTEON_IRQ_TIMER0:
-                case OCTEON_IRQ_TIMER1:
-                case OCTEON_IRQ_TIMER2:
-                case OCTEON_IRQ_TIMER3:
-                        set_irq_chip_and_handler(irq, chip0_timer, handle_percpu_irq);
+                case OCTEON_IRQ_MBOX0:
+                case OCTEON_IRQ_MBOX1:
+                        set_irq_chip_and_handler(irq, chip0_mbox, handle_percpu_irq);
                         break;
                 default:
-                        set_irq_chip_and_handler(irq, chip0, handle_percpu_irq);
+                        set_irq_chip_and_handler(irq, chip0, handle_fasteoi_irq);
                         break;
                 }
         }
 
         /* 88 - 151 CIU_INT_SUM1 */
-        for (irq = OCTEON_IRQ_WDOG0; irq <= OCTEON_IRQ_RESERVED151; irq++) {
-                set_irq_chip_and_handler(irq, chip1, handle_percpu_irq);
-        }
+        for (irq = OCTEON_IRQ_WDOG0; irq <= OCTEON_IRQ_WDOG15; irq++)
+                set_irq_chip_and_handler(irq, chip1_wd, handle_fasteoi_irq);
+
+        for (irq = OCTEON_IRQ_UART2; irq <= OCTEON_IRQ_RESERVED151; irq++)
+                set_irq_chip_and_handler(irq, chip1, handle_fasteoi_irq);
 
-#ifdef CONFIG_PCI_MSI
-        /* 152 - 215 PCI/PCIe MSI interrupts */
-        for (irq = OCTEON_IRQ_MSI_BIT0; irq <= OCTEON_IRQ_MSI_BIT63; irq++) {
-                set_irq_chip_and_handler(irq, &octeon_irq_chip_msi,
-                                         handle_percpu_irq);
-        }
-#endif
         set_c0_status(0x300 << 2);
 }
 
@@ -693,6 +749,7 @@ asmlinkage void plat_irq_dispatch(void)
         unsigned long cop0_status;
         uint64_t ciu_en;
         uint64_t ciu_sum;
+        unsigned int irq;
 
         while (1) {
                 cop0_cause = read_c0_cause();
@@ -704,18 +761,24 @@ asmlinkage void plat_irq_dispatch(void)
                         ciu_sum = cvmx_read_csr(ciu_sum0_address);
                         ciu_en = cvmx_read_csr(ciu_en0_address);
                         ciu_sum &= ciu_en;
-                        if (likely(ciu_sum))
-                                do_IRQ(fls64(ciu_sum) + OCTEON_IRQ_WORKQ0 - 1);
-                        else
+                        if (likely(ciu_sum)) {
+                                irq = fls64(ciu_sum) + OCTEON_IRQ_WORKQ0 - 1;
+                                octeon_ciu0_ack(irq);
+                                do_IRQ(irq);
+                        } else {
                                 spurious_interrupt();
+                        }
                 } else if (unlikely(cop0_cause & STATUSF_IP3)) {
                         ciu_sum = cvmx_read_csr(ciu_sum1_address);
                         ciu_en = cvmx_read_csr(ciu_en1_address);
                         ciu_sum &= ciu_en;
-                        if (likely(ciu_sum))
-                                do_IRQ(fls64(ciu_sum) + OCTEON_IRQ_WDOG0 - 1);
-                        else
+                        if (likely(ciu_sum)) {
+                                irq = fls64(ciu_sum) + OCTEON_IRQ_WDOG0 - 1;
+                                octeon_ciu1_ack(irq);
+                                do_IRQ(irq);
+                        } else {
                                 spurious_interrupt();
+                        }
                 } else if (likely(cop0_cause)) {
                         do_IRQ(fls(cop0_cause) - 9 + MIPS_CPU_IRQ_BASE);
                 } else {
@@ -725,54 +788,84 @@ asmlinkage void plat_irq_dispatch(void)
 }
 
 #ifdef CONFIG_HOTPLUG_CPU
-static int is_irq_enabled_on_cpu(unsigned int irq, unsigned int cpu)
-{
-        unsigned int isset;
-        int coreid = octeon_coreid_for_cpu(cpu);
-        int bit = (irq < OCTEON_IRQ_WDOG0) ?
-                   irq - OCTEON_IRQ_WORKQ0 : irq - OCTEON_IRQ_WDOG0;
-       if (irq < 64) {
-                isset = (cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)) &
-                        (1ull << bit)) >> bit;
-       } else {
-               isset = (cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)) &
-                        (1ull << bit)) >> bit;
-       }
-       return isset;
-}
 
 void fixup_irqs(void)
 {
-       int irq;
+        int irq;
+        struct irq_desc *desc;
+        cpumask_t new_affinity;
+        unsigned long flags;
+        int do_set_affinity;
+        int cpu;
+
+        cpu = smp_processor_id();
 
         for (irq = OCTEON_IRQ_SW0; irq <= OCTEON_IRQ_TIMER; irq++)
                 octeon_irq_core_disable_local(irq);
 
-        for (irq = OCTEON_IRQ_WORKQ0; irq <= OCTEON_IRQ_GPIO15; irq++) {
-                if (is_irq_enabled_on_cpu(irq, smp_processor_id())) {
-                        /* ciu irq migrates to next cpu */
-                        octeon_irq_chip_ciu0.disable(irq);
-                        octeon_irq_ciu0_set_affinity(irq, &cpu_online_map);
-                }
-        }
-
-#if 0
-        for (irq = OCTEON_IRQ_MBOX0; irq <= OCTEON_IRQ_MBOX1; irq++)
-                octeon_irq_mailbox_mask(irq);
-#endif
-        for (irq = OCTEON_IRQ_UART0; irq <= OCTEON_IRQ_BOOTDMA; irq++) {
-                if (is_irq_enabled_on_cpu(irq, smp_processor_id())) {
-                        /* ciu irq migrates to next cpu */
-                        octeon_irq_chip_ciu0.disable(irq);
-                        octeon_irq_ciu0_set_affinity(irq, &cpu_online_map);
-                }
-        }
+        for (irq = OCTEON_IRQ_WORKQ0; irq < OCTEON_IRQ_LAST; irq++) {
+                desc = irq_to_desc(irq);
+                switch (irq) {
+                case OCTEON_IRQ_MBOX0:
+                case OCTEON_IRQ_MBOX1:
+                        /* The eoi function will disable them on this CPU. */
+                        desc->chip->eoi(irq);
+                        break;
+                case OCTEON_IRQ_WDOG0:
+                case OCTEON_IRQ_WDOG1:
+                case OCTEON_IRQ_WDOG2:
+                case OCTEON_IRQ_WDOG3:
+                case OCTEON_IRQ_WDOG4:
+                case OCTEON_IRQ_WDOG5:
+                case OCTEON_IRQ_WDOG6:
+                case OCTEON_IRQ_WDOG7:
+                case OCTEON_IRQ_WDOG8:
+                case OCTEON_IRQ_WDOG9:
+                case OCTEON_IRQ_WDOG10:
+                case OCTEON_IRQ_WDOG11:
+                case OCTEON_IRQ_WDOG12:
+                case OCTEON_IRQ_WDOG13:
+                case OCTEON_IRQ_WDOG14:
+                case OCTEON_IRQ_WDOG15:
+                        /*
+                         * These have special per CPU semantics and
+                         * are handled in the watchdog driver.
+                         */
+                        break;
+                default:
+                        raw_spin_lock_irqsave(&desc->lock, flags);
+                        /*
+                         * If this irq has an action, it is in use and
+                         * must be migrated if it has affinity to this
+                         * cpu.
+                         */
+                        if (desc->action && cpumask_test_cpu(cpu, desc->affinity)) {
+                                if (cpumask_weight(desc->affinity) > 1) {
+                                        /*
+                                         * It has multi CPU affinity,
+                                         * just remove this CPU from
+                                         * the affinity set.
+                                         */
+                                        cpumask_copy(&new_affinity, desc->affinity);
+                                        cpumask_clear_cpu(cpu, &new_affinity);
+                                } else {
+                                        /*
+                                         * Otherwise, put it on lowest
+                                         * numbered online CPU.
+                                         */
+                                        cpumask_clear(&new_affinity);
+                                        cpumask_set_cpu(cpumask_first(cpu_online_mask), &new_affinity);
+                                }
+                                do_set_affinity = 1;
+                        } else {
+                                do_set_affinity = 0;
+                        }
+                        raw_spin_unlock_irqrestore(&desc->lock, flags);
+
+                        if (do_set_affinity)
+                                irq_set_affinity(irq, &new_affinity);
 
-        for (irq = OCTEON_IRQ_UART2; irq <= OCTEON_IRQ_RESERVED135; irq++) {
-                if (is_irq_enabled_on_cpu(irq, smp_processor_id())) {
-                        /* ciu irq migrates to next cpu */
-                        octeon_irq_chip_ciu1.disable(irq);
-                        octeon_irq_ciu1_set_affinity(irq, &cpu_online_map);
+                        break;
                 }
         }
 }
diff --git a/arch/mips/cavium-octeon/octeon_boot.h b/arch/mips/cavium-octeon/octeon_boot.h
index 0f7f84accf9a..428864b2ba41 100644
--- a/arch/mips/cavium-octeon/octeon_boot.h
+++ b/arch/mips/cavium-octeon/octeon_boot.h
@@ -23,14 +23,16 @@
 #include <linux/types.h>
 
 struct boot_init_vector {
-        uint32_t stack_addr;
-        uint32_t code_addr;
+        /* First stage address - in ram instead of flash */
+        uint64_t code_addr;
+        /* Setup code for application, NOT application entry point */
         uint32_t app_start_func_addr;
+        /* k0 is used for global data - needs to be passed to other cores */
         uint32_t k0_val;
-        uint32_t flags;
-        uint32_t boot_info_addr;
+        /* Address of boot info block structure */
+        uint64_t boot_info_addr;
+        uint32_t flags;         /* flags */
         uint32_t pad;
-        uint32_t pad2;
 };
 
 /* similar to bootloader's linux_app_boot_info but without global data */
@@ -40,7 +42,7 @@ struct linux_app_boot_info {
         uint32_t avail_coremask;
         uint32_t pci_console_active;
         uint32_t icache_prefetch_disable;
-        uint32_t InitTLBStart_addr;
+        uint64_t InitTLBStart_addr;
         uint32_t start_app_addr;
         uint32_t cur_exception_base;
         uint32_t no_mark_private_data;
@@ -58,7 +60,7 @@ struct linux_app_boot_info {
 
 #define LINUX_APP_BOOT_BLOCK_NAME "linux-app-boot"
 
-#define LABI_SIGNATURE 0xAABBCCDD
+#define LABI_SIGNATURE 0xAABBCC01
 
 /*  from uboot-headers/octeon_mem_map.h */
 #define EXCEPTION_BASE_INCR     (4 * 1024)
diff --git a/arch/mips/cavium-octeon/serial.c b/arch/mips/cavium-octeon/serial.c
index 83eac37a1ff9..638adab02842 100644
--- a/arch/mips/cavium-octeon/serial.c
+++ b/arch/mips/cavium-octeon/serial.c
@@ -18,11 +18,7 @@
 
 #include <asm/octeon/octeon.h>
 
-#ifdef CONFIG_GDB_CONSOLE
-#define DEBUG_UART 0
-#else
 #define DEBUG_UART 1
-#endif
 
 unsigned int octeon_serial_in(struct uart_port *up, int offset)
 {
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index d1b5ffaf0281..69197cb6c7ea 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -32,6 +32,7 @@
 #include <asm/time.h>
 
 #include <asm/octeon/octeon.h>
+#include <asm/octeon/pci-octeon.h>
 
 #ifdef CONFIG_CAVIUM_DECODE_RSL
 extern void cvmx_interrupt_rsl_decode(void);
@@ -578,9 +579,6 @@ void __init prom_init(void)
         }
 
         if (strstr(arcs_cmdline, "console=") == NULL) {
-#ifdef CONFIG_GDB_CONSOLE
-                strcat(arcs_cmdline, " console=gdb");
-#else
 #ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
                 strcat(arcs_cmdline, " console=ttyS0,115200");
 #else
@@ -589,7 +587,6 @@ void __init prom_init(void)
                 else
                         strcat(arcs_cmdline, " console=ttyS0,115200");
 #endif
-#endif
         }
 
         if (octeon_is_simulation()) {
@@ -598,13 +595,13 @@ void __init prom_init(void)
                  * the filesystem. Also specify the calibration delay
                  * to avoid calculating it every time.
                  */
-                strcat(arcs_cmdline, " rw root=1f00"
-                       " lpj=60176 slram=root,0x40000000,+1073741824");
+                strcat(arcs_cmdline, " rw root=1f00 slram=root,0x40000000,+1073741824");
         }
 
         mips_hpt_frequency = octeon_get_clock_rate();
 
         octeon_init_cvmcount();
+        octeon_setup_delays();
 
         _machine_restart = octeon_restart;
         _machine_halt = octeon_halt;
@@ -613,6 +610,22 @@ void __init prom_init(void)
         register_smp_ops(&octeon_smp_ops);
 }
 
+/* Exclude a single page from the regions obtained in plat_mem_setup. */
+static __init void memory_exclude_page(u64 addr, u64 *mem, u64 *size)
+{
+        if (addr > *mem && addr < *mem + *size) {
+                u64 inc = addr - *mem;
+                add_memory_region(*mem, inc, BOOT_MEM_RAM);
+                *mem += inc;
+                *size -= inc;
+        }
+
+        if (addr == *mem && *size > PAGE_SIZE) {
+                *mem += PAGE_SIZE;
+                *size -= PAGE_SIZE;
+        }
+}
+
 void __init plat_mem_setup(void)
 {
         uint64_t mem_alloc_size;
@@ -663,12 +676,27 @@ void __init plat_mem_setup(void)
                                                 CVMX_BOOTMEM_FLAG_NO_LOCKING);
 #endif
                 if (memory >= 0) {
+                        u64 size = mem_alloc_size;
+
+                        /*
+                         * exclude a page at the beginning and end of
+                         * the 256MB PCIe 'hole' so the kernel will not
+                         * try to allocate multi-page buffers that
+                         * span the discontinuity.
+                         */
+                        memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE,
+                                            &memory, &size);
+                        memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE +
+                                            CVMX_PCIE_BAR1_PHYS_SIZE,
+                                            &memory, &size);
+
                         /*
                          * This function automatically merges address
                          * regions next to each other if they are
                          * received in incrementing order.
                          */
-                        add_memory_region(memory, mem_alloc_size, BOOT_MEM_RAM);
+                        if (size)
+                                add_memory_region(memory, size, BOOT_MEM_RAM);
                         total += mem_alloc_size;
                 } else {
                         break;
@@ -691,7 +719,10 @@ void __init plat_mem_setup(void)
                       "cvmx_bootmem_phy_alloc\n");
 }
 
-
+/*
+ * Emit one character to the boot UART.  Exported for use by the
+ * watchdog timer.
+ */
 int prom_putchar(char c)
 {
         uint64_t lsrval;
@@ -705,6 +736,7 @@ int prom_putchar(char c)
         cvmx_write_csr(CVMX_MIO_UARTX_THR(octeon_uart), c & 0xffull);
         return 1;
 }
+EXPORT_SYMBOL(prom_putchar);
 
 void prom_free_prom_memory(void)
 {
diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c
index 6d99b9d8887d..391cefe556b3 100644
--- a/arch/mips/cavium-octeon/smp.c
+++ b/arch/mips/cavium-octeon/smp.c
@@ -3,7 +3,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 2004-2008 Cavium Networks
+ * Copyright (C) 2004-2008, 2009, 2010 Cavium Networks
  */
 #include <linux/cpu.h>
 #include <linux/init.h>
@@ -27,7 +27,8 @@ volatile unsigned long octeon_processor_sp;
 volatile unsigned long octeon_processor_gp;
 
 #ifdef CONFIG_HOTPLUG_CPU
-static unsigned int InitTLBStart_addr;
+uint64_t octeon_bootloader_entry_addr;
+EXPORT_SYMBOL(octeon_bootloader_entry_addr);
 #endif
 
 static irqreturn_t mailbox_interrupt(int irq, void *dev_id)
@@ -80,20 +81,13 @@ static inline void octeon_send_ipi_mask(const struct cpumask *mask,
 static void octeon_smp_hotplug_setup(void)
 {
 #ifdef CONFIG_HOTPLUG_CPU
-        uint32_t labi_signature;
-
-        labi_signature =
-                cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
-                                        LABI_ADDR_IN_BOOTLOADER +
-                                        offsetof(struct linux_app_boot_info,
-                                                    labi_signature)));
-        if (labi_signature != LABI_SIGNATURE)
-                pr_err("The bootloader version on this board is incorrect\n");
-        InitTLBStart_addr =
-                cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
-                                   LABI_ADDR_IN_BOOTLOADER +
-                                           offsetof(struct linux_app_boot_info,
-                                                    InitTLBStart_addr)));
+        struct linux_app_boot_info *labi;
+
+        labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
+        if (labi->labi_signature != LABI_SIGNATURE)
+                panic("The bootloader version on this board is incorrect.");
+
+        octeon_bootloader_entry_addr = labi->InitTLBStart_addr;
 #endif
 }
 
@@ -102,24 +96,47 @@ static void octeon_smp_setup(void)
         const int coreid = cvmx_get_core_num();
         int cpus;
         int id;
-
         int core_mask = octeon_get_boot_coremask();
+#ifdef CONFIG_HOTPLUG_CPU
+        unsigned int num_cores = cvmx_octeon_num_cores();
+#endif
+
+        /* The present CPUs are initially just the boot cpu (CPU 0). */
+        for (id = 0; id < NR_CPUS; id++) {
+                set_cpu_possible(id, id == 0);
+                set_cpu_present(id, id == 0);
+        }
 
-        cpus_clear(cpu_possible_map);
         __cpu_number_map[coreid] = 0;
         __cpu_logical_map[0] = coreid;
-        cpu_set(0, cpu_possible_map);
 
+        /* The present CPUs get the lowest CPU numbers. */
         cpus = 1;
-        for (id = 0; id < 16; id++) {
+        for (id = 0; id < NR_CPUS; id++) {
                 if ((id != coreid) && (core_mask & (1 << id))) {
-                        cpu_set(cpus, cpu_possible_map);
+                        set_cpu_possible(cpus, true);
+                        set_cpu_present(cpus, true);
                         __cpu_number_map[id] = cpus;
                         __cpu_logical_map[cpus] = id;
                         cpus++;
                 }
         }
-        cpu_present_map = cpu_possible_map;
+
+#ifdef CONFIG_HOTPLUG_CPU
+        /*
+         * The possible CPUs are all those present on the chip.  We
+         * will assign CPU numbers for possible cores as well.  Cores
+         * are always consecutively numberd from 0.
+         */
+        for (id = 0; id < num_cores && id < NR_CPUS; id++) {
+                if (!(core_mask & (1 << id))) {
+                        set_cpu_possible(cpus, true);
+                        __cpu_number_map[id] = cpus;
+                        __cpu_logical_map[cpus] = id;
+                        cpus++;
+                }
+        }
+#endif
 
         octeon_smp_hotplug_setup();
 }
@@ -158,18 +175,21 @@ static void octeon_init_secondary(void)
 {
         const int coreid = cvmx_get_core_num();
         union cvmx_ciu_intx_sum0 interrupt_enable;
+        unsigned int sr;
 
 #ifdef CONFIG_HOTPLUG_CPU
-        unsigned int cur_exception_base;
-
-        cur_exception_base = cvmx_read64_uint32(
-                CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
-                             LABI_ADDR_IN_BOOTLOADER +
-                             offsetof(struct linux_app_boot_info,
-                                      cur_exception_base)));
-        /* cur_exception_base is incremented in bootloader after setting */
-        write_c0_ebase((unsigned int)(cur_exception_base - EXCEPTION_BASE_INCR));
+        struct linux_app_boot_info *labi;
+
+        labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
+
+        if (labi->labi_signature != LABI_SIGNATURE)
+                panic("The bootloader version on this board is incorrect.");
 #endif
+
+        sr = set_c0_status(ST0_BEV);
+        write_c0_ebase((u32)ebase);
+        write_c0_status(sr);
+
         octeon_check_cpu_bist();
         octeon_init_cvmcount();
         /*
@@ -276,8 +296,8 @@ static int octeon_cpu_disable(void)
 static void octeon_cpu_die(unsigned int cpu)
 {
         int coreid = cpu_logical_map(cpu);
-        uint32_t avail_coremask;
-        struct cvmx_bootmem_named_block_desc *block_desc;
+        uint32_t mask, new_mask;
+        const struct cvmx_bootmem_named_block_desc *block_desc;
 
         while (per_cpu(cpu_state, cpu) != CPU_DEAD)
                 cpu_relax();
@@ -286,52 +306,40 @@ static void octeon_cpu_die(unsigned int cpu)
          * This is a bit complicated strategics of getting/settig available
          * cores mask, copied from bootloader
          */
+
+        mask = 1 << coreid;
         /* LINUX_APP_BOOT_BLOCK is initialized in bootoct binary */
         block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME);
 
         if (!block_desc) {
-                avail_coremask =
-                        cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
-                                                   LABI_ADDR_IN_BOOTLOADER +
-                                                   offsetof
-                                                   (struct linux_app_boot_info,
-                                                    avail_coremask)));
-        } else {                       /* alternative, already initialized */
-               avail_coremask =
-                   cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
-                                                   block_desc->base_addr +
-                                                  AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK));
-        }
+                struct linux_app_boot_info *labi;
 
-        avail_coremask |= 1 << coreid;
+                labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
 
-        /* Setting avail_coremask for bootoct binary */
-        if (!block_desc) {
-                cvmx_write64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
-                                                LABI_ADDR_IN_BOOTLOADER +
-                                                offsetof(struct linux_app_boot_info,
-                                                         avail_coremask)),
-                                   avail_coremask);
-        } else {
-                cvmx_write64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
-                                                block_desc->base_addr +
-                                                AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK),
-                                   avail_coremask);
+                labi->avail_coremask |= mask;
+                new_mask = labi->avail_coremask;
+        } else {                       /* alternative, already initialized */
+                uint32_t *p = (uint32_t *)PHYS_TO_XKSEG_CACHED(block_desc->base_addr +
+                                                               AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK);
+                *p |= mask;
+                new_mask = *p;
         }
 
-        pr_info("Reset core %d. Available Coremask = %x\n", coreid,
-                avail_coremask);
+        pr_info("Reset core %d. Available Coremask = 0x%x \n", coreid, new_mask);
+        mb();
         cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
         cvmx_write_csr(CVMX_CIU_PP_RST, 0);
 }
 
 void play_dead(void)
 {
-        int coreid = cvmx_get_core_num();
+        int cpu = cpu_number_map(cvmx_get_core_num());
 
         idle_task_exit();
         octeon_processor_boot = 0xff;
-        per_cpu(cpu_state, coreid) = CPU_DEAD;
+        per_cpu(cpu_state, cpu) = CPU_DEAD;
+
+        mb();
 
         while (1)       /* core will be reset here */
                 ;
@@ -344,29 +352,27 @@ static void start_after_reset(void)
         kernel_entry(0, 0, 0);  /* set a2 = 0 for secondary core */
 }
 
-int octeon_update_boot_vector(unsigned int cpu)
+static int octeon_update_boot_vector(unsigned int cpu)
 {
 
         int coreid = cpu_logical_map(cpu);
-        unsigned int avail_coremask;
-        struct cvmx_bootmem_named_block_desc *block_desc;
+        uint32_t avail_coremask;
+        const struct cvmx_bootmem_named_block_desc *block_desc;
         struct boot_init_vector *boot_vect =
-                (struct boot_init_vector *) cvmx_phys_to_ptr(0x0 +
-                                                  BOOTLOADER_BOOT_VECTOR);
+                (struct boot_init_vector *)PHYS_TO_XKSEG_CACHED(BOOTLOADER_BOOT_VECTOR);
 
         block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME);
 
         if (!block_desc) {
-                avail_coremask =
-                        cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
-                                           LABI_ADDR_IN_BOOTLOADER +
-                                                offsetof(struct linux_app_boot_info,
-                                                avail_coremask)));
+                struct linux_app_boot_info *labi;
+
+                labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
+
+                avail_coremask = labi->avail_coremask;
+                labi->avail_coremask &= ~(1 << coreid);
         } else {                       /* alternative, already initialized */
-               avail_coremask =
-                   cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
-                                                   block_desc->base_addr +
-                                                   AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK));
+                avail_coremask = *(uint32_t *)PHYS_TO_XKSEG_CACHED(
+                        block_desc->base_addr + AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK);
         }
 
         if (!(avail_coremask & (1 << coreid))) {
@@ -377,9 +383,9 @@ int octeon_update_boot_vector(unsigned int cpu)
 
         boot_vect[coreid].app_start_func_addr =
                 (uint32_t) (unsigned long) start_after_reset;
-        boot_vect[coreid].code_addr = InitTLBStart_addr;
+        boot_vect[coreid].code_addr = octeon_bootloader_entry_addr;
 
-        CVMX_SYNC;
+        mb();
 
         cvmx_write_csr(CVMX_CIU_NMI, (1 << coreid) & avail_coremask);
 
@@ -405,17 +411,11 @@ static int __cpuinit octeon_cpu_callback(struct notifier_block *nfb,
         return NOTIFY_OK;
 }
 
-static struct notifier_block __cpuinitdata octeon_cpu_notifier = {
-        .notifier_call = octeon_cpu_callback,
-};
-
 static int __cpuinit register_cavium_notifier(void)
 {
-        register_hotcpu_notifier(&octeon_cpu_notifier);
-
+        hotcpu_notifier(octeon_cpu_callback, 0);
         return 0;
 }
-
 late_initcall(register_cavium_notifier);
 
 #endif  /* CONFIG_HOTPLUG_CPU */
diff --git a/arch/mips/cobalt/Makefile b/arch/mips/cobalt/Makefile
index 237926288d6d..61a334ac43ac 100644
--- a/arch/mips/cobalt/Makefile
+++ b/arch/mips/cobalt/Makefile
@@ -7,5 +7,3 @@ obj-y := buttons.o irq.o lcd.o led.o reset.o rtc.o serial.o setup.o time.o
 obj-$(CONFIG_PCI)               += pci.o
 obj-$(CONFIG_EARLY_PRINTK)      += console.o
 obj-$(CONFIG_MTD_PHYSMAP)       += mtd.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/cobalt/Platform b/arch/mips/cobalt/Platform
new file mode 100644
index 000000000000..34123efd6dfe
--- /dev/null
+++ b/arch/mips/cobalt/Platform
@@ -0,0 +1,6 @@
+#
+# Cobalt Server
+#
+platform-$(CONFIG_MIPS_COBALT)  += cobalt/
+cflags-$(CONFIG_MIPS_COBALT)    += -I$(srctree)/arch/mips/include/asm/mach-cobalt
+load-$(CONFIG_MIPS_COBALT)      += 0xffffffff80080000
diff --git a/arch/mips/configs/db1000_defconfig b/arch/mips/configs/db1000_defconfig
index f66d406aadce..3a9ec6ccd40d 100644
--- a/arch/mips/configs/db1000_defconfig
+++ b/arch/mips/configs/db1000_defconfig
@@ -8,7 +8,7 @@ CONFIG_MIPS=y
 #
 # Machine selection
 #
-CONFIG_MACH_ALCHEMY=y
+CONFIG_MIPS_ALCHEMY=y
 # CONFIG_AR7 is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_BCM63XX is not set
@@ -64,7 +64,6 @@ CONFIG_MIPS_DB1000=y
 # CONFIG_MIPS_PB1550 is not set
 # CONFIG_MIPS_XXS1500 is not set
 CONFIG_SOC_AU1000=y
-CONFIG_SOC_AU1X00=y
 CONFIG_LOONGSON_UART_BASE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
diff --git a/arch/mips/configs/db1100_defconfig b/arch/mips/configs/db1100_defconfig
index abb9a5805adc..4589b84301f3 100644
--- a/arch/mips/configs/db1100_defconfig
+++ b/arch/mips/configs/db1100_defconfig
@@ -8,7 +8,7 @@ CONFIG_MIPS=y
 #
 # Machine selection
 #
-CONFIG_MACH_ALCHEMY=y
+CONFIG_MIPS_ALCHEMY=y
 # CONFIG_AR7 is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_BCM63XX is not set
@@ -64,7 +64,6 @@ CONFIG_MIPS_DB1100=y
 # CONFIG_MIPS_PB1550 is not set
 # CONFIG_MIPS_XXS1500 is not set
 CONFIG_SOC_AU1100=y
-CONFIG_SOC_AU1X00=y
 CONFIG_LOONGSON_UART_BASE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
diff --git a/arch/mips/configs/db1200_defconfig b/arch/mips/configs/db1200_defconfig
index 991c20adf471..9950f2aabd31 100644
--- a/arch/mips/configs/db1200_defconfig
+++ b/arch/mips/configs/db1200_defconfig
@@ -8,7 +8,7 @@ CONFIG_MIPS=y
 #
 # Machine selection
 #
-CONFIG_MACH_ALCHEMY=y
+CONFIG_MIPS_ALCHEMY=y
 # CONFIG_AR7 is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_BCM63XX is not set
@@ -64,7 +64,6 @@ CONFIG_MIPS_DB1200=y
 # CONFIG_MIPS_PB1550 is not set
 # CONFIG_MIPS_XXS1500 is not set
 CONFIG_SOC_AU1200=y
-CONFIG_SOC_AU1X00=y
 CONFIG_LOONGSON_UART_BASE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
diff --git a/arch/mips/configs/db1500_defconfig b/arch/mips/configs/db1500_defconfig
index 5424c9167bf2..346ae631d1ef 100644
--- a/arch/mips/configs/db1500_defconfig
+++ b/arch/mips/configs/db1500_defconfig
@@ -8,7 +8,7 @@ CONFIG_MIPS=y
 #
 # Machine selection
 #
-CONFIG_MACH_ALCHEMY=y
+CONFIG_MIPS_ALCHEMY=y
 # CONFIG_AR7 is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_BCM63XX is not set
@@ -64,7 +64,6 @@ CONFIG_MIPS_DB1500=y
 # CONFIG_MIPS_PB1550 is not set
 # CONFIG_MIPS_XXS1500 is not set
 CONFIG_SOC_AU1500=y
-CONFIG_SOC_AU1X00=y
 CONFIG_LOONGSON_UART_BASE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
diff --git a/arch/mips/configs/db1550_defconfig b/arch/mips/configs/db1550_defconfig
index 949b6dcf634b..10eafb942af3 100644
--- a/arch/mips/configs/db1550_defconfig
+++ b/arch/mips/configs/db1550_defconfig
@@ -8,7 +8,7 @@ CONFIG_MIPS=y
 #
 # Machine selection
 #
-CONFIG_MACH_ALCHEMY=y
+CONFIG_MIPS_ALCHEMY=y
 # CONFIG_AR7 is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_BCM63XX is not set
@@ -64,7 +64,6 @@ CONFIG_MIPS_DB1550=y
 # CONFIG_MIPS_PB1550 is not set
 # CONFIG_MIPS_XXS1500 is not set
 CONFIG_SOC_AU1550=y
-CONFIG_SOC_AU1X00=y
 CONFIG_LOONGSON_UART_BASE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
diff --git a/arch/mips/configs/gpr_defconfig b/arch/mips/configs/gpr_defconfig
new file mode 100644
index 000000000000..17e2e624d03f
--- /dev/null
+++ b/arch/mips/configs/gpr_defconfig
@@ -0,0 +1,2060 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.35-rc6
+# Fri Jul 23 19:28:52 2010
+#
+CONFIG_MIPS=y
+
+#
+# Machine selection
+#
+CONFIG_MIPS_ALCHEMY=y
+# CONFIG_AR7 is not set
+# CONFIG_BCM47XX is not set
+# CONFIG_BCM63XX is not set
+# CONFIG_MIPS_COBALT is not set
+# CONFIG_MACH_DECSTATION is not set
+# CONFIG_MACH_JAZZ is not set
+# CONFIG_LASAT is not set
+# CONFIG_MACH_LOONGSON is not set
+# CONFIG_MIPS_MALTA is not set
+# CONFIG_MIPS_SIM is not set
+# CONFIG_NEC_MARKEINS is not set
+# CONFIG_MACH_VR41XX is not set
+# CONFIG_NXP_STB220 is not set
+# CONFIG_NXP_STB225 is not set
+# CONFIG_PNX8550_JBS is not set
+# CONFIG_PNX8550_STB810 is not set
+# CONFIG_PMC_MSP is not set
+# CONFIG_PMC_YOSEMITE is not set
+# CONFIG_POWERTV is not set
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP28 is not set
+# CONFIG_SGI_IP32 is not set
+# CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CARMEL is not set
+# CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_SWARM is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_BIGSUR is not set
+# CONFIG_SNI_RM is not set
+# CONFIG_MACH_TX39XX is not set
+# CONFIG_MACH_TX49XX is not set
+# CONFIG_MIKROTIK_RB532 is not set
+# CONFIG_WR_PPMC is not set
+# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
+# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set
+CONFIG_ALCHEMY_GPIOINT_AU1000=y
+# CONFIG_ALCHEMY_GPIO_INDIRECT is not set
+# CONFIG_MIPS_MTX1 is not set
+# CONFIG_MIPS_BOSPORUS is not set
+# CONFIG_MIPS_DB1000 is not set
+# CONFIG_MIPS_DB1100 is not set
+# CONFIG_MIPS_DB1200 is not set
+# CONFIG_MIPS_DB1500 is not set
+# CONFIG_MIPS_DB1550 is not set
+# CONFIG_MIPS_MIRAGE is not set
+# CONFIG_MIPS_PB1000 is not set
+# CONFIG_MIPS_PB1100 is not set
+# CONFIG_MIPS_PB1200 is not set
+# CONFIG_MIPS_PB1500 is not set
+# CONFIG_MIPS_PB1550 is not set
+# CONFIG_MIPS_XXS1500 is not set
+CONFIG_MIPS_GPR=y
+CONFIG_SOC_AU1550=y
+CONFIG_LOONGSON_UART_BASE=y
+# CONFIG_LOONGSON_MC146818 is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_SUPPORTS_OPROFILE=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_SCHED_OMIT_FRAME_POINTER=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_CEVT_R4K_LIB=y
+CONFIG_CSRC_R4K_LIB=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_GPIO=y
+# CONFIG_CPU_BIG_ENDIAN is not set
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_IRQ_CPU=y
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+
+#
+# CPU selection
+#
+# CONFIG_CPU_LOONGSON2E is not set
+# CONFIG_CPU_LOONGSON2F is not set
+CONFIG_CPU_MIPS32_R1=y
+# CONFIG_CPU_MIPS32_R2 is not set
+# CONFIG_CPU_MIPS64_R1 is not set
+# CONFIG_CPU_MIPS64_R2 is not set
+# CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_TX39XX is not set
+# CONFIG_CPU_VR41XX is not set
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_R5000 is not set
+# CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_R5500 is not set
+# CONFIG_CPU_R6000 is not set
+# CONFIG_CPU_NEVADA is not set
+# CONFIG_CPU_R8000 is not set
+# CONFIG_CPU_R10000 is not set
+# CONFIG_CPU_RM7000 is not set
+# CONFIG_CPU_RM9000 is not set
+# CONFIG_CPU_SB1 is not set
+# CONFIG_CPU_CAVIUM_OCTEON is not set
+CONFIG_SYS_SUPPORTS_ZBOOT=y
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_CPU_MIPS32=y
+CONFIG_CPU_MIPSR1=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_HARDWARE_WATCHPOINTS=y
+
+#
+# Kernel type
+#
+CONFIG_32BIT=y
+# CONFIG_64BIT is not set
+CONFIG_PAGE_SIZE_4KB=y
+# CONFIG_PAGE_SIZE_8KB is not set
+# CONFIG_PAGE_SIZE_16KB is not set
+# CONFIG_PAGE_SIZE_32KB is not set
+# CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_MIPS_MT_DISABLED=y
+# CONFIG_MIPS_MT_SMP is not set
+# CONFIG_MIPS_MT_SMTC is not set
+CONFIG_64BIT_PHYS_ADDR=y
+CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_TICK_ONESHOT=y
+# CONFIG_NO_HZ is not set
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_HZ_48 is not set
+# CONFIG_HZ_100 is not set
+# CONFIG_HZ_128 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_256 is not set
+# CONFIG_HZ_1000 is not set
+# CONFIG_HZ_1024 is not set
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_HZ=250
+# CONFIG_PREEMPT_NONE is not set
+CONFIG_PREEMPT_VOLUNTARY=y
+# CONFIG_PREEMPT is not set
+# CONFIG_KEXEC is not set
+CONFIG_SECCOMP=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_CROSS_COMPILE=""
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_BZIP2=y
+CONFIG_HAVE_KERNEL_LZMA=y
+CONFIG_HAVE_KERNEL_LZO=y
+CONFIG_KERNEL_GZIP=y
+# CONFIG_KERNEL_BZIP2 is not set
+# CONFIG_KERNEL_LZMA is not set
+# CONFIG_KERNEL_LZO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_TINY_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=17
+# CONFIG_CGROUPS is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+CONFIG_RELAY=y
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+# CONFIG_RD_LZO is not set
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EMBEDDED=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_PCSPKR_PLATFORM=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_PCI_QUIRKS=y
+CONFIG_COMPAT_BRK=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+# CONFIG_OPROFILE is not set
+CONFIG_HAVE_OPROFILE=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+CONFIG_INLINE_SPIN_UNLOCK=y
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+CONFIG_INLINE_READ_UNLOCK=y
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+CONFIG_INLINE_READ_UNLOCK_IRQ=y
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+CONFIG_INLINE_WRITE_UNLOCK=y
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+# CONFIG_MUTEX_SPIN_ON_OWNER is not set
+# CONFIG_FREEZER is not set
+
+#
+# Bus options (PCI, PCMCIA, EISA, ISA, TC)
+#
+CONFIG_HW_HAS_PCI=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCI_STUB is not set
+# CONFIG_PCI_IOV is not set
+CONFIG_MMU=y
+# CONFIG_PCCARD is not set
+# CONFIG_HOTPLUG_PCI is not set
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_HAVE_AOUT is not set
+CONFIG_BINFMT_MISC=m
+CONFIG_TRAD_SIGNALS=y
+
+#
+# Power management options
+#
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+# CONFIG_PM is not set
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_ASK_IP_FIB_HASH=y
+# CONFIG_IP_FIB_TRIE is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+CONFIG_INET_LRO=y
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+CONFIG_NETWORK_SECMARK=y
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+CONFIG_BRIDGE_NETFILTER=y
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=m
+CONFIG_NETFILTER_NETLINK_QUEUE=m
+CONFIG_NETFILTER_NETLINK_LOG=m
+# CONFIG_NF_CONNTRACK is not set
+# CONFIG_NETFILTER_TPROXY is not set
+CONFIG_NETFILTER_XTABLES=m
+
+#
+# Xtables combined modules
+#
+CONFIG_NETFILTER_XT_MARK=m
+
+#
+# Xtables targets
+#
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
+CONFIG_NETFILTER_XT_TARGET_DSCP=m
+CONFIG_NETFILTER_XT_TARGET_HL=m
+# CONFIG_NETFILTER_XT_TARGET_LED is not set
+CONFIG_NETFILTER_XT_TARGET_MARK=m
+# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
+# CONFIG_NETFILTER_XT_TARGET_TEE is not set
+# CONFIG_NETFILTER_XT_TARGET_TRACE is not set
+CONFIG_NETFILTER_XT_TARGET_SECMARK=m
+# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set
+# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set
+
+#
+# Xtables matches
+#
+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
+CONFIG_NETFILTER_XT_MATCH_DCCP=m
+CONFIG_NETFILTER_XT_MATCH_DSCP=m
+CONFIG_NETFILTER_XT_MATCH_ESP=m
+# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set
+CONFIG_NETFILTER_XT_MATCH_HL=m
+# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set
+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
+CONFIG_NETFILTER_XT_MATCH_MAC=m
+CONFIG_NETFILTER_XT_MATCH_MARK=m
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+# CONFIG_NETFILTER_XT_MATCH_OSF is not set
+# CONFIG_NETFILTER_XT_MATCH_OWNER is not set
+CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
+CONFIG_NETFILTER_XT_MATCH_QUOTA=m
+# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
+CONFIG_NETFILTER_XT_MATCH_REALM=m
+# CONFIG_NETFILTER_XT_MATCH_RECENT is not set
+CONFIG_NETFILTER_XT_MATCH_SCTP=m
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
+CONFIG_NETFILTER_XT_MATCH_STRING=m
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
+# CONFIG_NETFILTER_XT_MATCH_TIME is not set
+# CONFIG_NETFILTER_XT_MATCH_U32 is not set
+CONFIG_IP_VS=m
+# CONFIG_IP_VS_DEBUG is not set
+CONFIG_IP_VS_TAB_BITS=12
+
+#
+# IPVS transport protocol load balancing support
+#
+CONFIG_IP_VS_PROTO_TCP=y
+CONFIG_IP_VS_PROTO_UDP=y
+CONFIG_IP_VS_PROTO_AH_ESP=y
+CONFIG_IP_VS_PROTO_ESP=y
+CONFIG_IP_VS_PROTO_AH=y
+# CONFIG_IP_VS_PROTO_SCTP is not set
+
+#
+# IPVS scheduler
+#
+CONFIG_IP_VS_RR=m
+CONFIG_IP_VS_WRR=m
+CONFIG_IP_VS_LC=m
+CONFIG_IP_VS_WLC=m
+CONFIG_IP_VS_LBLC=m
+CONFIG_IP_VS_LBLCR=m
+CONFIG_IP_VS_DH=m
+CONFIG_IP_VS_SH=m
+CONFIG_IP_VS_SED=m
+CONFIG_IP_VS_NQ=m
+
+#
+# IPVS application helper
+#
+CONFIG_IP_VS_FTP=m
+
+#
+# IP: Netfilter Configuration
+#
+# CONFIG_NF_DEFRAG_IPV4 is not set
+CONFIG_IP_NF_QUEUE=m
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_MATCH_ADDRTYPE=m
+CONFIG_IP_NF_MATCH_AH=m
+CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_TTL=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_TARGET_LOG=m
+CONFIG_IP_NF_TARGET_ULOG=m
+CONFIG_IP_NF_MANGLE=m
+CONFIG_IP_NF_TARGET_ECN=m
+CONFIG_IP_NF_TARGET_TTL=m
+CONFIG_IP_NF_RAW=m
+CONFIG_IP_NF_ARPTABLES=m
+CONFIG_IP_NF_ARPFILTER=m
+CONFIG_IP_NF_ARP_MANGLE=m
+
+#
+# DECnet: Netfilter Configuration
+#
+CONFIG_DECNET_NF_GRABULATOR=m
+CONFIG_BRIDGE_NF_EBTABLES=m
+CONFIG_BRIDGE_EBT_BROUTE=m
+CONFIG_BRIDGE_EBT_T_FILTER=m
+CONFIG_BRIDGE_EBT_T_NAT=m
+CONFIG_BRIDGE_EBT_802_3=m
+CONFIG_BRIDGE_EBT_AMONG=m
+CONFIG_BRIDGE_EBT_ARP=m
+CONFIG_BRIDGE_EBT_IP=m
+CONFIG_BRIDGE_EBT_LIMIT=m
+CONFIG_BRIDGE_EBT_MARK=m
+CONFIG_BRIDGE_EBT_PKTTYPE=m
+CONFIG_BRIDGE_EBT_STP=m
+CONFIG_BRIDGE_EBT_VLAN=m
+CONFIG_BRIDGE_EBT_ARPREPLY=m
+CONFIG_BRIDGE_EBT_DNAT=m
+CONFIG_BRIDGE_EBT_MARK_T=m
+CONFIG_BRIDGE_EBT_REDIRECT=m
+CONFIG_BRIDGE_EBT_SNAT=m
+CONFIG_BRIDGE_EBT_LOG=m
+CONFIG_BRIDGE_EBT_ULOG=m
+# CONFIG_BRIDGE_EBT_NFLOG is not set
+CONFIG_IP_DCCP=m
+CONFIG_INET_DCCP_DIAG=m
+
+#
+# DCCP CCIDs Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_DCCP_CCID2_DEBUG is not set
+CONFIG_IP_DCCP_CCID3=y
+# CONFIG_IP_DCCP_CCID3_DEBUG is not set
+CONFIG_IP_DCCP_CCID3_RTO=100
+CONFIG_IP_DCCP_TFRC_LIB=y
+CONFIG_IP_SCTP=m
+# CONFIG_SCTP_DBG_MSG is not set
+# CONFIG_SCTP_DBG_OBJCNT is not set
+# CONFIG_SCTP_HMAC_NONE is not set
+# CONFIG_SCTP_HMAC_SHA1 is not set
+CONFIG_SCTP_HMAC_MD5=y
+# CONFIG_RDS is not set
+CONFIG_TIPC=m
+# CONFIG_TIPC_ADVANCED is not set
+# CONFIG_TIPC_DEBUG is not set
+CONFIG_ATM=y
+CONFIG_ATM_CLIP=y
+# CONFIG_ATM_CLIP_NO_ICMP is not set
+CONFIG_ATM_LANE=m
+CONFIG_ATM_MPOA=m
+CONFIG_ATM_BR2684=m
+# CONFIG_ATM_BR2684_IPFILTER is not set
+# CONFIG_L2TP is not set
+CONFIG_STP=m
+CONFIG_BRIDGE=m
+CONFIG_BRIDGE_IGMP_SNOOPING=y
+# CONFIG_NET_DSA is not set
+CONFIG_VLAN_8021Q=m
+# CONFIG_VLAN_8021Q_GVRP is not set
+CONFIG_DECNET=m
+# CONFIG_DECNET_ROUTER is not set
+CONFIG_LLC=m
+CONFIG_LLC2=m
+CONFIG_IPX=m
+# CONFIG_IPX_INTERN is not set
+CONFIG_ATALK=m
+CONFIG_DEV_APPLETALK=m
+CONFIG_IPDDP=m
+CONFIG_IPDDP_ENCAP=y
+CONFIG_IPDDP_DECAP=y
+CONFIG_X25=m
+CONFIG_LAPB=m
+CONFIG_ECONET=m
+CONFIG_ECONET_AUNUDP=y
+CONFIG_ECONET_NATIVE=y
+CONFIG_WAN_ROUTER=m
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+CONFIG_NET_SCHED=y
+
+#
+# Queueing/Scheduling
+#
+CONFIG_NET_SCH_CBQ=m
+CONFIG_NET_SCH_HTB=m
+CONFIG_NET_SCH_HFSC=m
+CONFIG_NET_SCH_ATM=m
+CONFIG_NET_SCH_PRIO=m
+# CONFIG_NET_SCH_MULTIQ is not set
+CONFIG_NET_SCH_RED=m
+CONFIG_NET_SCH_SFQ=m
+CONFIG_NET_SCH_TEQL=m
+CONFIG_NET_SCH_TBF=m
+CONFIG_NET_SCH_GRED=m
+CONFIG_NET_SCH_DSMARK=m
+CONFIG_NET_SCH_NETEM=m
+# CONFIG_NET_SCH_DRR is not set
+CONFIG_NET_SCH_INGRESS=m
+
+#
+# Classification
+#
+CONFIG_NET_CLS=y
+CONFIG_NET_CLS_BASIC=m
+CONFIG_NET_CLS_TCINDEX=m
+CONFIG_NET_CLS_ROUTE4=m
+CONFIG_NET_CLS_ROUTE=y
+CONFIG_NET_CLS_FW=m
+CONFIG_NET_CLS_U32=m
+# CONFIG_CLS_U32_PERF is not set
+CONFIG_CLS_U32_MARK=y
+CONFIG_NET_CLS_RSVP=m
+CONFIG_NET_CLS_RSVP6=m
+# CONFIG_NET_CLS_FLOW is not set
+CONFIG_NET_EMATCH=y
+CONFIG_NET_EMATCH_STACK=32
+CONFIG_NET_EMATCH_CMP=m
+CONFIG_NET_EMATCH_NBYTE=m
+CONFIG_NET_EMATCH_U32=m
+CONFIG_NET_EMATCH_META=m
+CONFIG_NET_EMATCH_TEXT=m
+CONFIG_NET_CLS_ACT=y
+CONFIG_NET_ACT_POLICE=y
+# CONFIG_NET_ACT_GACT is not set
+# CONFIG_NET_ACT_MIRRED is not set
+# CONFIG_NET_ACT_IPT is not set
+# CONFIG_NET_ACT_NAT is not set
+# CONFIG_NET_ACT_PEDIT is not set
+# CONFIG_NET_ACT_SIMP is not set
+# CONFIG_NET_ACT_SKBEDIT is not set
+# CONFIG_NET_CLS_IND is not set
+CONFIG_NET_SCH_FIFO=y
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+CONFIG_NET_PKTGEN=m
+CONFIG_HAMRADIO=y
+
+#
+# Packet Radio protocols
+#
+CONFIG_AX25=m
+# CONFIG_AX25_DAMA_SLAVE is not set
+CONFIG_NETROM=m
+CONFIG_ROSE=m
+
+#
+# AX.25 network device drivers
+#
+CONFIG_MKISS=m
+CONFIG_6PACK=m
+CONFIG_BPQETHER=m
+CONFIG_BAYCOM_SER_FDX=m
+CONFIG_BAYCOM_SER_HDX=m
+CONFIG_YAM=m
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+CONFIG_FIB_RULES=y
+CONFIG_WIRELESS=y
+CONFIG_WEXT_CORE=y
+CONFIG_WEXT_PROC=y
+CONFIG_CFG80211=y
+# CONFIG_NL80211_TESTMODE is not set
+# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
+# CONFIG_CFG80211_REG_DEBUG is not set
+CONFIG_CFG80211_DEFAULT_PS=y
+# CONFIG_CFG80211_DEBUGFS is not set
+# CONFIG_CFG80211_INTERNAL_REGDB is not set
+CONFIG_CFG80211_WEXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+# CONFIG_LIB80211 is not set
+CONFIG_MAC80211=y
+CONFIG_MAC80211_HAS_RC=y
+# CONFIG_MAC80211_RC_PID is not set
+CONFIG_MAC80211_RC_MINSTREL=y
+# CONFIG_MAC80211_RC_DEFAULT_PID is not set
+CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
+CONFIG_MAC80211_RC_DEFAULT="minstrel"
+# CONFIG_MAC80211_MESH is not set
+CONFIG_MAC80211_LEDS=y
+# CONFIG_MAC80211_DEBUGFS is not set
+# CONFIG_MAC80211_DEBUG_MENU is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+# CONFIG_CAIF is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH=""
+# CONFIG_DEVTMPFS is not set
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_SM_FTL is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_RAM=m
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+CONFIG_MTD_PHYSMAP=y
+# CONFIG_MTD_PHYSMAP_COMPAT is not set
+# CONFIG_MTD_PCI is not set
+# CONFIG_MTD_GPIO_ADDR is not set
+# CONFIG_MTD_INTEL_VR_NOR is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+
+#
+# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
+#
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=65536
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_AD525X_DPOT is not set
+# CONFIG_PHANTOM is not set
+# CONFIG_SGI_IOC4 is not set
+CONFIG_TIFM_CORE=m
+CONFIG_TIFM_7XX1=m
+# CONFIG_ICS932S401 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_HP_ILO is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_CB710_CORE is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+CONFIG_SCSI_MOD=m
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=m
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+CONFIG_SCSI_NETLINK=y
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=m
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+CONFIG_CHR_DEV_SG=m
+# CONFIG_CHR_DEV_SCH is not set
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+CONFIG_SCSI_LOGGING=y
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+CONFIG_SCSI_SPI_ATTRS=m
+CONFIG_SCSI_FC_ATTRS=m
+CONFIG_SCSI_ISCSI_ATTRS=m
+CONFIG_SCSI_SAS_ATTRS=m
+CONFIG_SCSI_SAS_LIBSAS=m
+CONFIG_SCSI_SAS_HOST_SMP=y
+# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+
+#
+# You can enable one or both FireWire driver stacks.
+#
+
+#
+# The newer stack is recommended.
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_IEEE1394 is not set
+# CONFIG_I2O is not set
+CONFIG_NETDEVICES=y
+# CONFIG_IFB is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_ARCNET is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+CONFIG_MARVELL_PHY=m
+CONFIG_DAVICOM_PHY=m
+CONFIG_QSEMI_PHY=m
+CONFIG_LXT_PHY=m
+CONFIG_CICADA_PHY=m
+CONFIG_VITESSE_PHY=m
+CONFIG_SMSC_PHY=m
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+# CONFIG_MICREL_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+CONFIG_MIPS_AU1X00_ENET=y
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_ETHOC is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_DNET is not set
+# CONFIG_NET_TULIP is not set
+# CONFIG_HP100 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_NET_PCI is not set
+# CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_KS8851_MLL is not set
+# CONFIG_ATL2 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_TR is not set
+CONFIG_WLAN=y
+# CONFIG_LIBERTAS_THINFIRM is not set
+# CONFIG_ATMEL is not set
+# CONFIG_AT76C50X_USB is not set
+# CONFIG_PRISM54 is not set
+# CONFIG_USB_ZD1201 is not set
+# CONFIG_USB_NET_RNDIS_WLAN is not set
+# CONFIG_RTL8180 is not set
+# CONFIG_RTL8187 is not set
+# CONFIG_ADM8211 is not set
+# CONFIG_MAC80211_HWSIM is not set
+# CONFIG_MWL8K is not set
+CONFIG_ATH_COMMON=y
+CONFIG_ATH_DEBUG=y
+CONFIG_ATH5K=y
+CONFIG_ATH5K_DEBUG=y
+# CONFIG_ATH9K is not set
+# CONFIG_ATH9K_HTC is not set
+# CONFIG_AR9170_USB is not set
+# CONFIG_B43 is not set
+# CONFIG_B43LEGACY is not set
+# CONFIG_HOSTAP is not set
+# CONFIG_IPW2100 is not set
+# CONFIG_IPW2200 is not set
+# CONFIG_IWLWIFI is not set
+# CONFIG_LIBERTAS is not set
+# CONFIG_HERMES is not set
+# CONFIG_P54_COMMON is not set
+# CONFIG_RT2X00 is not set
+# CONFIG_WL12XX is not set
+# CONFIG_ZD1211RW is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_USB_IPHETH is not set
+CONFIG_WAN=y
+CONFIG_LANMEDIA=m
+CONFIG_HDLC=m
+CONFIG_HDLC_RAW=m
+CONFIG_HDLC_RAW_ETH=m
+CONFIG_HDLC_CISCO=m
+CONFIG_HDLC_FR=m
+CONFIG_HDLC_PPP=m
+CONFIG_HDLC_X25=m
+CONFIG_PCI200SYN=m
+CONFIG_WANXL=m
+# CONFIG_PC300TOO is not set
+CONFIG_FARSYNC=m
+CONFIG_DSCC4=m
+CONFIG_DSCC4_PCISYNC=y
+CONFIG_DSCC4_PCI_RST=y
+CONFIG_DLCI=m
+CONFIG_DLCI_MAX=8
+CONFIG_WAN_ROUTER_DRIVERS=m
+CONFIG_CYCLADES_SYNC=m
+CONFIG_CYCLOMX_X25=y
+CONFIG_LAPBETHER=m
+CONFIG_X25_ASY=m
+CONFIG_ATM_DRIVERS=y
+# CONFIG_ATM_DUMMY is not set
+CONFIG_ATM_TCP=m
+CONFIG_ATM_LANAI=m
+CONFIG_ATM_ENI=m
+# CONFIG_ATM_ENI_DEBUG is not set
+# CONFIG_ATM_ENI_TUNE_BURST is not set
+CONFIG_ATM_FIRESTREAM=m
+CONFIG_ATM_ZATM=m
+# CONFIG_ATM_ZATM_DEBUG is not set
+CONFIG_ATM_NICSTAR=m
+# CONFIG_ATM_NICSTAR_USE_SUNI is not set
+# CONFIG_ATM_NICSTAR_USE_IDT77105 is not set
+CONFIG_ATM_IDT77252=m
+# CONFIG_ATM_IDT77252_DEBUG is not set
+# CONFIG_ATM_IDT77252_RCV_ALL is not set
+CONFIG_ATM_IDT77252_USE_SUNI=y
+CONFIG_ATM_AMBASSADOR=m
+# CONFIG_ATM_AMBASSADOR_DEBUG is not set
+CONFIG_ATM_HORIZON=m
+# CONFIG_ATM_HORIZON_DEBUG is not set
+CONFIG_ATM_IA=m
+# CONFIG_ATM_IA_DEBUG is not set
+CONFIG_ATM_FORE200E=m
+# CONFIG_ATM_FORE200E_USE_TASKLET is not set
+CONFIG_ATM_FORE200E_TX_RETRY=16
+CONFIG_ATM_FORE200E_DEBUG=0
+CONFIG_ATM_HE=m
+CONFIG_ATM_HE_USE_SUNI=y
+# CONFIG_ATM_SOLOS is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+CONFIG_PPP=m
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_MPPE=m
+CONFIG_PPPOE=m
+CONFIG_PPPOATM=m
+CONFIG_SLIP=m
+CONFIG_SLIP_COMPRESSED=y
+CONFIG_SLHC=m
+CONFIG_SLIP_SMART=y
+CONFIG_SLIP_MODE_SLIP6=y
+CONFIG_NET_FC=y
+CONFIG_NETCONSOLE=m
+# CONFIG_NETCONSOLE_DYNAMIC is not set
+CONFIG_NETPOLL=y
+# CONFIG_NETPOLL_TRAP is not set
+CONFIG_NET_POLL_CONTROLLER=y
+# CONFIG_VMXNET3 is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+# CONFIG_INPUT_SPARSEKMAP is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_N_GSM is not set
+# CONFIG_NOZOMI is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_SERIAL_8250_PCI is not set
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+# CONFIG_SERIAL_TIMBERDALE is not set
+# CONFIG_SERIAL_ALTERA_JTAGUART is not set
+# CONFIG_SERIAL_ALTERA_UART is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_HW_RANDOM_TIMERIOMEM is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+# CONFIG_RAMOOPS is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_ALGOBIT=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# PC SMBus host controller drivers
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_ISCH is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_AU1550 is not set
+CONFIG_I2C_GPIO=y
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_XILINX is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_SPI is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
+
+#
+# Memory mapped GPIO expanders:
+#
+# CONFIG_GPIO_IT8761E is not set
+# CONFIG_GPIO_SCH is not set
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX7300 is not set
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+# CONFIG_GPIO_ADP5588 is not set
+
+#
+# PCI GPIO expanders:
+#
+# CONFIG_GPIO_CS5535 is not set
+# CONFIG_GPIO_BT8XX is not set
+# CONFIG_GPIO_LANGWELL is not set
+# CONFIG_GPIO_RDC321X is not set
+
+#
+# SPI GPIO expanders:
+#
+
+#
+# AC97 GPIO expanders:
+#
+
+#
+# MODULbus GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Native drivers
+#
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7411 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7475 is not set
+# CONFIG_SENSORS_ASC7621 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_I5K_AMB is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_G760A is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM73 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+CONFIG_SENSORS_LM83=y
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_LTC4215 is not set
+# CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_LM95241 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_SHT15 is not set
+# CONFIG_SENSORS_SIS5595 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_EMC1403 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_AMC6821 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_TMP102 is not set
+# CONFIG_SENSORS_TMP401 is not set
+# CONFIG_SENSORS_TMP421 is not set
+# CONFIG_SENSORS_VIA686A is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_VT8231 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_SENSORS_LIS3_I2C is not set
+# CONFIG_THERMAL is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+# CONFIG_ALIM7101_WDT is not set
+
+#
+# PCI-based Watchdog Cards
+#
+# CONFIG_PCIPCWATCHDOG is not set
+# CONFIG_WDTPCI is not set
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB=m
+CONFIG_SSB_SPROM=y
+CONFIG_SSB_PCIHOST_POSSIBLE=y
+CONFIG_SSB_PCIHOST=y
+# CONFIG_SSB_B43_PCI_BRIDGE is not set
+# CONFIG_SSB_SILENT is not set
+# CONFIG_SSB_DEBUG is not set
+CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
+CONFIG_SSB_DRIVER_PCICORE=y
+# CONFIG_SSB_DRIVER_MIPS is not set
+CONFIG_MFD_SUPPORT=y
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_88PM860X is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_HTC_I2CPLD is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TPS6507X is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TC35892 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_PMIC_ADP5520 is not set
+# CONFIG_MFD_MAX8925 is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_WM8994 is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_ABX500_CORE is not set
+# CONFIG_MFD_TIMBERDALE is not set
+# CONFIG_LPC_SCH is not set
+# CONFIG_MFD_RDC321X is not set
+# CONFIG_MFD_JANZ_CMODIO is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGA_ARB is not set
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+# CONFIG_LCD_CLASS_DEVICE is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_GENERIC is not set
+# CONFIG_BACKLIGHT_ADP8860 is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=m
+# CONFIG_HID_PID is not set
+CONFIG_USB_HIDDEV=y
+
+#
+# USB HID Boot Protocol drivers
+#
+CONFIG_USB_KBD=m
+CONFIG_USB_MOUSE=m
+
+#
+# Special HID drivers
+#
+# CONFIG_HID_3M_PCT is not set
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_APPLE is not set
+# CONFIG_HID_BELKIN is not set
+# CONFIG_HID_CANDO is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_CHICONY is not set
+# CONFIG_HID_CYPRESS is not set
+# CONFIG_HID_DRAGONRISE is not set
+# CONFIG_HID_EGALAX is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_KYE is not set
+# CONFIG_HID_GYRATION is not set
+# CONFIG_HID_TWINHAN is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_LOGITECH is not set
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MOSART is not set
+# CONFIG_HID_MONTEREY is not set
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_ORTEK is not set
+# CONFIG_HID_PANTHERLORD is not set
+# CONFIG_HID_PETALYNX is not set
+# CONFIG_HID_PICOLCD is not set
+# CONFIG_HID_QUANTA is not set
+# CONFIG_HID_ROCCAT is not set
+# CONFIG_HID_ROCCAT_KONE is not set
+# CONFIG_HID_SAMSUNG is not set
+# CONFIG_HID_SONY is not set
+# CONFIG_HID_STANTUM is not set
+# CONFIG_HID_SUNPLUS is not set
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_HID_THRUSTMASTER is not set
+# CONFIG_HID_ZEROPLUS is not set
+# CONFIG_HID_ZYDACRON is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+# CONFIG_USB_DEVICEFS is not set
+# CONFIG_USB_DEVICE_CLASS is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+CONFIG_USB_MON=y
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_XHCI_HCD is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_EHCI_TT_NEWSCHED=y
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_UHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_WHCI_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=m
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+CONFIG_USB_LIBUSUAL=y
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+CONFIG_USB_SERIAL=y
+# CONFIG_USB_SERIAL_CONSOLE is not set
+CONFIG_USB_EZUSB=y
+CONFIG_USB_SERIAL_GENERIC=y
+# CONFIG_USB_SERIAL_AIRCABLE is not set
+# CONFIG_USB_SERIAL_ARK3116 is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_CH341 is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_CP210X is not set
+# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_FUNSOFT is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IPAQ is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
+# CONFIG_USB_SERIAL_GARMIN is not set
+# CONFIG_USB_SERIAL_IPW is not set
+# CONFIG_USB_SERIAL_IUU is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KLSI is not set
+# CONFIG_USB_SERIAL_KOBIL_SCT is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_MOS7720 is not set
+# CONFIG_USB_SERIAL_MOS7840 is not set
+# CONFIG_USB_SERIAL_MOTOROLA is not set
+# CONFIG_USB_SERIAL_NAVMAN is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_OTI6858 is not set
+# CONFIG_USB_SERIAL_QCAUX is not set
+# CONFIG_USB_SERIAL_QUALCOMM is not set
+# CONFIG_USB_SERIAL_SPCP8X5 is not set
+# CONFIG_USB_SERIAL_HP4X is not set
+# CONFIG_USB_SERIAL_SAFE is not set
+# CONFIG_USB_SERIAL_SIEMENS_MPI is not set
+CONFIG_USB_SERIAL_SIERRAWIRELESS=y
+# CONFIG_USB_SERIAL_SYMBOL is not set
+# CONFIG_USB_SERIAL_TI is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OPTION is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+# CONFIG_USB_SERIAL_OPTICON is not set
+# CONFIG_USB_SERIAL_VIVOPAY_SERIAL is not set
+# CONFIG_USB_SERIAL_ZIO is not set
+# CONFIG_USB_SERIAL_DEBUG is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_ATM is not set
+# CONFIG_USB_GADGET is not set
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_NOP_USB_XCEIV is not set
+# CONFIG_UWB is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+# CONFIG_LEDS_PCA9532 is not set
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_GPIO_PLATFORM=y
+# CONFIG_LEDS_LP3944 is not set
+# CONFIG_LEDS_PCA955X is not set
+# CONFIG_LEDS_BD2802 is not set
+# CONFIG_LEDS_LT3593 is not set
+CONFIG_LEDS_TRIGGERS=y
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
+# CONFIG_LEDS_TRIGGER_GPIO is not set
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+
+#
+# iptables trigger is under Netfilter config (LED target)
+#
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_INFINIBAND is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+# CONFIG_FSNOTIFY is not set
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY is not set
+# CONFIG_INOTIFY_USER is not set
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=m
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=m
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_ECRYPT_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+CONFIG_JFFS2_RUBIN=y
+# CONFIG_JFFS2_CMODE_NONE is not set
+CONFIG_JFFS2_CMODE_PRIORITY=y
+# CONFIG_JFFS2_CMODE_SIZE is not set
+# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
+# CONFIG_LOGFS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+CONFIG_NFS_V4=y
+# CONFIG_NFS_V4_1 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+CONFIG_RPCSEC_GSS_KRB5=y
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CEPH_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+CONFIG_NLS_CODEPAGE_850=y
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+CONFIG_RCU_CPU_STALL_DETECTOR=y
+# CONFIG_LKDTM is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+# CONFIG_ATOMIC64_SELFTEST is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE="console=ttyS0,115200 root=/dev/nfs rw ip=auto"
+# CONFIG_CMDLINE_OVERRIDE is not set
+# CONFIG_SPINLOCK_TEST is not set
+
+#
+# Security options
+#
+CONFIG_KEYS=y
+# CONFIG_KEYS_DEBUG_PROC_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_DEFAULT_SECURITY_SELINUX is not set
+# CONFIG_DEFAULT_SECURITY_SMACK is not set
+# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD=m
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=m
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_GF128MUL is not set
+CONFIG_CRYPTO_NULL=m
+CONFIG_CRYPTO_WORKQUEUE=y
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_AUTHENC=m
+CONFIG_CRYPTO_TEST=m
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=y
+# CONFIG_CRYPTO_LRW is not set
+CONFIG_CRYPTO_PCBC=m
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=y
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=m
+# CONFIG_CRYPTO_GHASH is not set
+CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=m
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=m
+CONFIG_CRYPTO_SHA256=m
+CONFIG_CRYPTO_SHA512=m
+CONFIG_CRYPTO_TGR192=m
+CONFIG_CRYPTO_WP512=m
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_ARC4=y
+CONFIG_CRYPTO_BLOWFISH=m
+# CONFIG_CRYPTO_CAMELLIA is not set
+CONFIG_CRYPTO_CAST5=m
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+CONFIG_CRYPTO_KHAZAD=m
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_TEA=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=m
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+CONFIG_CRYPTO_ANSI_CPRNG=m
+CONFIG_CRYPTO_HW=y
+# CONFIG_CRYPTO_DEV_HIFN_795X is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+CONFIG_CRC_CCITT=m
+CONFIG_CRC16=m
+# CONFIG_CRC_T10DIF is not set
+CONFIG_CRC_ITU_T=m
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+CONFIG_LIBCRC32C=m
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_TEXTSEARCH=y
+CONFIG_TEXTSEARCH_KMP=m
+CONFIG_TEXTSEARCH_BM=m
+CONFIG_TEXTSEARCH_FSM=m
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/mips/configs/mtx1_defconfig b/arch/mips/configs/mtx1_defconfig
index cff8f4c0e57c..10d20aa731d3 100644
--- a/arch/mips/configs/mtx1_defconfig
+++ b/arch/mips/configs/mtx1_defconfig
@@ -8,7 +8,7 @@ CONFIG_MIPS=y
 #
 # Machine selection
 #
-CONFIG_MACH_ALCHEMY=y
+CONFIG_MIPS_ALCHEMY=y
 # CONFIG_AR7 is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_BCM63XX is not set
@@ -64,7 +64,6 @@ CONFIG_MIPS_MTX1=y
 # CONFIG_MIPS_PB1550 is not set
 # CONFIG_MIPS_XXS1500 is not set
 CONFIG_SOC_AU1500=y
-CONFIG_SOC_AU1X00=y
 CONFIG_LOONGSON_UART_BASE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
diff --git a/arch/mips/configs/pb1100_defconfig b/arch/mips/configs/pb1100_defconfig
index 97382b698b9b..778f726af8e0 100644
--- a/arch/mips/configs/pb1100_defconfig
+++ b/arch/mips/configs/pb1100_defconfig
@@ -8,7 +8,7 @@ CONFIG_MIPS=y
 #
 # Machine selection
 #
-CONFIG_MACH_ALCHEMY=y
+CONFIG_MIPS_ALCHEMY=y
 # CONFIG_AR7 is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_BCM63XX is not set
@@ -64,7 +64,6 @@ CONFIG_MIPS_PB1100=y
 # CONFIG_MIPS_PB1550 is not set
 # CONFIG_MIPS_XXS1500 is not set
 CONFIG_SOC_AU1100=y
-CONFIG_SOC_AU1X00=y
 CONFIG_LOONGSON_UART_BASE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
diff --git a/arch/mips/configs/pb1200_defconfig b/arch/mips/configs/pb1200_defconfig
index e9ad77320f16..0f908c692111 100644
--- a/arch/mips/configs/pb1200_defconfig
+++ b/arch/mips/configs/pb1200_defconfig
@@ -8,7 +8,7 @@ CONFIG_MIPS=y
 #
 # Machine selection
 #
-CONFIG_MACH_ALCHEMY=y
+CONFIG_MIPS_ALCHEMY=y
 # CONFIG_AR7 is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_BCM63XX is not set
@@ -64,7 +64,6 @@ CONFIG_MIPS_PB1200=y
 # CONFIG_MIPS_PB1550 is not set
 # CONFIG_MIPS_XXS1500 is not set
 CONFIG_SOC_AU1200=y
-CONFIG_SOC_AU1X00=y
 CONFIG_LOONGSON_UART_BASE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
diff --git a/arch/mips/configs/pb1500_defconfig b/arch/mips/configs/pb1500_defconfig
index 7497d3306b91..1c5fe6f06c0e 100644
--- a/arch/mips/configs/pb1500_defconfig
+++ b/arch/mips/configs/pb1500_defconfig
@@ -8,7 +8,7 @@ CONFIG_MIPS=y
 #
 # Machine selection
 #
-CONFIG_MACH_ALCHEMY=y
+CONFIG_MIPS_ALCHEMY=y
 # CONFIG_AR7 is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_BCM63XX is not set
@@ -64,7 +64,6 @@ CONFIG_MIPS_PB1500=y
 # CONFIG_MIPS_PB1550 is not set
 # CONFIG_MIPS_XXS1500 is not set
 CONFIG_SOC_AU1500=y
-CONFIG_SOC_AU1X00=y
 CONFIG_LOONGSON_UART_BASE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
diff --git a/arch/mips/configs/pb1550_defconfig b/arch/mips/configs/pb1550_defconfig
index aa526f53cb1b..49494b01138b 100644
--- a/arch/mips/configs/pb1550_defconfig
+++ b/arch/mips/configs/pb1550_defconfig
@@ -8,7 +8,7 @@ CONFIG_MIPS=y
 #
 # Machine selection
 #
-CONFIG_MACH_ALCHEMY=y
+CONFIG_MIPS_ALCHEMY=y
 # CONFIG_AR7 is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_BCM63XX is not set
@@ -64,7 +64,6 @@ CONFIG_ALCHEMY_GPIOINT_AU1000=y
 CONFIG_MIPS_PB1550=y
 # CONFIG_MIPS_XXS1500 is not set
 CONFIG_SOC_AU1550=y
-CONFIG_SOC_AU1X00=y
 CONFIG_LOONGSON_UART_BASE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
diff --git a/arch/mips/configs/powertv_defconfig b/arch/mips/configs/powertv_defconfig
index 7291633d81cc..af0ab73bfce8 100644
--- a/arch/mips/configs/powertv_defconfig
+++ b/arch/mips/configs/powertv_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.31-rc5
-# Fri Aug 28 14:49:33 2009
+# Linux kernel version: 2.6.35-rc3
+# Thu Jul  1 11:03:28 2010
 #
 CONFIG_MIPS=y
 
@@ -11,11 +11,12 @@ CONFIG_MIPS=y
 # CONFIG_MACH_ALCHEMY is not set
 # CONFIG_AR7 is not set
 # CONFIG_BCM47XX is not set
+# CONFIG_BCM63XX is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MACH_JAZZ is not set
 # CONFIG_LASAT is not set
-# CONFIG_LEMOTE_FULONG is not set
+# CONFIG_MACH_LOONGSON is not set
 # CONFIG_MIPS_MALTA is not set
 # CONFIG_MIPS_SIM is not set
 # CONFIG_NEC_MARKEINS is not set
@@ -50,7 +51,6 @@ CONFIG_POWERTV=y
 # CONFIG_MIN_RUNTIME_RESOURCES is not set
 # CONFIG_BOOTLOADER_DRIVER is not set
 CONFIG_BOOTLOADER_FAMILY="R2"
-CONFIG_CSRC_POWERTV=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
 # CONFIG_ARCH_HAS_ILOG2_U64 is not set
@@ -65,9 +65,9 @@ CONFIG_SCHED_OMIT_FRAME_POINTER=y
 CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
 CONFIG_CEVT_R4K_LIB=y
 CONFIG_CEVT_R4K=y
+CONFIG_CSRC_POWERTV=y
 CONFIG_DMA_NONCOHERENT=y
-CONFIG_DMA_NEED_PCI_MAP_STATE=y
-# CONFIG_EARLY_PRINTK is not set
+CONFIG_NEED_DMA_MAP_STATE=y
 CONFIG_SYS_HAS_EARLY_PRINTK=y
 # CONFIG_NO_IOPORT is not set
 CONFIG_CPU_BIG_ENDIAN=y
@@ -79,7 +79,8 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
 #
 # CPU selection
 #
-# CONFIG_CPU_LOONGSON2 is not set
+# CONFIG_CPU_LOONGSON2E is not set
+# CONFIG_CPU_LOONGSON2F is not set
 # CONFIG_CPU_MIPS32_R1 is not set
 CONFIG_CPU_MIPS32_R2=y
 # CONFIG_CPU_MIPS64_R1 is not set
@@ -122,7 +123,7 @@ CONFIG_CPU_HAS_PREFETCH=y
 CONFIG_MIPS_MT_DISABLED=y
 # CONFIG_MIPS_MT_SMP is not set
 # CONFIG_MIPS_MT_SMTC is not set
-CONFIG_CPU_HAS_LLSC=y
+# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
 CONFIG_CPU_MIPSR2_IRQ_VI=y
 CONFIG_CPU_MIPSR2_IRQ_EI=y
 CONFIG_CPU_HAS_SYNC=y
@@ -144,8 +145,7 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=0
 CONFIG_VIRT_TO_BUS=y
-CONFIG_HAVE_MLOCK=y
-CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+# CONFIG_KSM is not set
 CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
 CONFIG_TICK_ONESHOT=y
 CONFIG_NO_HZ=y
@@ -177,6 +177,7 @@ CONFIG_EXPERIMENTAL=y
 CONFIG_BROKEN_ON_SMP=y
 CONFIG_LOCK_KERNEL=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_CROSS_COMPILE="mips-linux-"
 CONFIG_LOCALVERSION=""
 CONFIG_LOCALVERSION_AUTO=y
 # CONFIG_SWAP is not set
@@ -190,19 +191,15 @@ CONFIG_SYSVIPC_SYSCTL=y
 #
 # RCU Subsystem
 #
-CONFIG_CLASSIC_RCU=y
-# CONFIG_TREE_RCU is not set
-# CONFIG_PREEMPT_RCU is not set
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_TINY_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
 # CONFIG_TREE_RCU_TRACE is not set
-# CONFIG_PREEMPT_RCU_TRACE is not set
 # CONFIG_IKCONFIG is not set
 CONFIG_LOG_BUF_SHIFT=16
-CONFIG_GROUP_SCHED=y
-CONFIG_FAIR_GROUP_SCHED=y
-# CONFIG_RT_GROUP_SCHED is not set
-CONFIG_USER_SCHED=y
-# CONFIG_CGROUP_SCHED is not set
-# CONFIG_CGROUPS is not set
 # CONFIG_SYSFS_DEPRECATED_V2 is not set
 CONFIG_RELAY=y
 # CONFIG_NAMESPACES is not set
@@ -211,6 +208,7 @@ CONFIG_INITRAMFS_SOURCE=""
 # CONFIG_RD_GZIP is not set
 # CONFIG_RD_BZIP2 is not set
 # CONFIG_RD_LZMA is not set
+# CONFIG_RD_LZO is not set
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_SYSCTL=y
 CONFIG_ANON_INODES=y
@@ -234,18 +232,16 @@ CONFIG_SHMEM=y
 CONFIG_AIO=y
 
 #
-# Performance Counters
+# Kernel Performance Events And Counters
 #
 # CONFIG_VM_EVENT_COUNTERS is not set
 CONFIG_PCI_QUIRKS=y
 # CONFIG_SLUB_DEBUG is not set
-# CONFIG_STRIP_ASM_SYMS is not set
 CONFIG_COMPAT_BRK=y
 # CONFIG_SLAB is not set
 CONFIG_SLUB=y
 # CONFIG_SLOB is not set
 # CONFIG_PROFILING is not set
-# CONFIG_MARKERS is not set
 CONFIG_HAVE_OPROFILE=y
 
 #
@@ -253,7 +249,7 @@ CONFIG_HAVE_OPROFILE=y
 #
 # CONFIG_GCOV_KERNEL is not set
 # CONFIG_SLOW_WORK is not set
-# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
 CONFIG_RT_MUTEXES=y
 CONFIG_BASE_SMALL=0
 CONFIG_MODULES=y
@@ -271,15 +267,41 @@ CONFIG_LBDAF=y
 # IO Schedulers
 #
 CONFIG_IOSCHED_NOOP=y
-# CONFIG_IOSCHED_AS is not set
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
-# CONFIG_DEFAULT_AS is not set
 # CONFIG_DEFAULT_DEADLINE is not set
 # CONFIG_DEFAULT_CFQ is not set
 CONFIG_DEFAULT_NOOP=y
 CONFIG_DEFAULT_IOSCHED="noop"
-# CONFIG_PROBE_INITRD_HEADER is not set
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_SPIN_UNLOCK is not set
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_READ_UNLOCK is not set
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+# CONFIG_INLINE_READ_UNLOCK_IRQ is not set
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_WRITE_UNLOCK is not set
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+# CONFIG_MUTEX_SPIN_ON_OWNER is not set
 # CONFIG_FREEZER is not set
 
 #
@@ -289,7 +311,6 @@ CONFIG_HW_HAS_PCI=y
 CONFIG_PCI=y
 CONFIG_PCI_DOMAINS=y
 # CONFIG_ARCH_SUPPORTS_MSI is not set
-# CONFIG_PCI_LEGACY is not set
 # CONFIG_PCI_DEBUG is not set
 # CONFIG_PCI_STUB is not set
 # CONFIG_PCI_IOV is not set
@@ -318,7 +339,6 @@ CONFIG_NET=y
 # Networking options
 #
 CONFIG_PACKET=y
-CONFIG_PACKET_MMAP=y
 CONFIG_UNIX=y
 CONFIG_XFRM=y
 # CONFIG_XFRM_USER is not set
@@ -390,12 +410,26 @@ CONFIG_NETFILTER_ADVANCED=y
 # CONFIG_NETFILTER_NETLINK_LOG is not set
 # CONFIG_NF_CONNTRACK is not set
 CONFIG_NETFILTER_XTABLES=y
+
+#
+# Xtables combined modules
+#
+# CONFIG_NETFILTER_XT_MARK is not set
+
+#
+# Xtables targets
+#
 # CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set
 # CONFIG_NETFILTER_XT_TARGET_MARK is not set
 # CONFIG_NETFILTER_XT_TARGET_NFLOG is not set
 # CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set
 # CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
+# CONFIG_NETFILTER_XT_TARGET_TEE is not set
 # CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set
+
+#
+# Xtables matches
+#
 # CONFIG_NETFILTER_XT_MATCH_COMMENT is not set
 # CONFIG_NETFILTER_XT_MATCH_DCCP is not set
 # CONFIG_NETFILTER_XT_MATCH_DSCP is not set
@@ -465,10 +499,13 @@ CONFIG_IP6_NF_FILTER=y
 # CONFIG_IP6_NF_RAW is not set
 # CONFIG_IP_DCCP is not set
 # CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
+# CONFIG_L2TP is not set
 CONFIG_STP=y
 CONFIG_BRIDGE=y
+CONFIG_BRIDGE_IGMP_SNOOPING=y
 # CONFIG_NET_DSA is not set
 # CONFIG_VLAN_8021Q is not set
 # CONFIG_DECNET is not set
@@ -526,10 +563,21 @@ CONFIG_NET_SCH_FIFO=y
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
 # CONFIG_AF_RXRPC is not set
-# CONFIG_WIRELESS is not set
+CONFIG_WIRELESS=y
+# CONFIG_CFG80211 is not set
+# CONFIG_LIB80211 is not set
+
+#
+# CFG80211 needs to be enabled for MAC80211
+#
+
+#
+# Some wireless drivers require a rate control algorithm
+#
 # CONFIG_WIMAX is not set
 # CONFIG_RFKILL is not set
 # CONFIG_NET_9P is not set
+# CONFIG_CAIF is not set
 
 #
 # Device Drivers
@@ -539,6 +587,7 @@ CONFIG_NET_SCH_FIFO=y
 # Generic Driver Options
 #
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 CONFIG_FW_LOADER=y
@@ -550,9 +599,9 @@ CONFIG_EXTRA_FIRMWARE=""
 # CONFIG_CONNECTOR is not set
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
 # CONFIG_MTD_CONCAT is not set
 CONFIG_MTD_PARTITIONS=y
-# CONFIG_MTD_TESTS is not set
 # CONFIG_MTD_REDBOOT_PARTS is not set
 CONFIG_MTD_CMDLINE_PARTS=y
 # CONFIG_MTD_AR7_PARTS is not set
@@ -568,6 +617,7 @@ CONFIG_MTD_BLOCK=y
 # CONFIG_INFTL is not set
 # CONFIG_RFD_FTL is not set
 # CONFIG_SSFDC is not set
+# CONFIG_SM_FTL is not set
 # CONFIG_MTD_OOPS is not set
 
 #
@@ -611,11 +661,16 @@ CONFIG_MTD_CFI_I2=y
 # CONFIG_MTD_DOC2000 is not set
 # CONFIG_MTD_DOC2001 is not set
 # CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND_ECC=y
+# CONFIG_MTD_NAND_ECC_SMC is not set
 CONFIG_MTD_NAND=y
 # CONFIG_MTD_NAND_VERIFY_WRITE is not set
-# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_SM_COMMON is not set
 # CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_DENALI is not set
+CONFIG_MTD_NAND_DENALI_SCRATCH_REG_ADDR=0xFF108018
 CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_RICOH is not set
 # CONFIG_MTD_NAND_DISKONCHIP is not set
 # CONFIG_MTD_NAND_CAFE is not set
 # CONFIG_MTD_NAND_NANDSIM is not set
@@ -641,6 +696,10 @@ CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_COW_COMMON is not set
 CONFIG_BLK_DEV_LOOP=y
 # CONFIG_BLK_DEV_CRYPTOLOOP is not set
+
+#
+# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
+#
 # CONFIG_BLK_DEV_NBD is not set
 # CONFIG_BLK_DEV_SX8 is not set
 # CONFIG_BLK_DEV_UB is not set
@@ -658,6 +717,7 @@ CONFIG_HAVE_IDE=y
 #
 # SCSI device support
 #
+CONFIG_SCSI_MOD=y
 # CONFIG_RAID_ATTRS is not set
 CONFIG_SCSI=y
 CONFIG_SCSI_DMA=y
@@ -693,64 +753,95 @@ CONFIG_SCSI_WAIT_SCAN=m
 # CONFIG_SCSI_OSD_INITIATOR is not set
 CONFIG_ATA=y
 # CONFIG_ATA_NONSTANDARD is not set
+CONFIG_ATA_VERBOSE_ERROR=y
 CONFIG_SATA_PMP=y
+
+#
+# Controllers with non-SFF native interface
+#
 # CONFIG_SATA_AHCI is not set
+# CONFIG_SATA_AHCI_PLATFORM is not set
+# CONFIG_SATA_INIC162X is not set
 # CONFIG_SATA_SIL24 is not set
 CONFIG_ATA_SFF=y
-# CONFIG_SATA_SVW is not set
+
+#
+# SFF controllers with custom DMA interface
+#
+# CONFIG_PDC_ADMA is not set
+# CONFIG_SATA_QSTOR is not set
+# CONFIG_SATA_SX4 is not set
+CONFIG_ATA_BMDMA=y
+
+#
+# SATA SFF controllers with BMDMA
+#
 # CONFIG_ATA_PIIX is not set
 # CONFIG_SATA_MV is not set
 # CONFIG_SATA_NV is not set
-# CONFIG_PDC_ADMA is not set
-# CONFIG_SATA_QSTOR is not set
 # CONFIG_SATA_PROMISE is not set
-# CONFIG_SATA_SX4 is not set
 # CONFIG_SATA_SIL is not set
 # CONFIG_SATA_SIS is not set
+# CONFIG_SATA_SVW is not set
 # CONFIG_SATA_ULI is not set
 # CONFIG_SATA_VIA is not set
 # CONFIG_SATA_VITESSE is not set
-# CONFIG_SATA_INIC162X is not set
+
+#
+# PATA SFF controllers with BMDMA
+#
 # CONFIG_PATA_ALI is not set
 # CONFIG_PATA_AMD is not set
 # CONFIG_PATA_ARTOP is not set
 # CONFIG_PATA_ATIIXP is not set
-# CONFIG_PATA_CMD640_PCI is not set
+# CONFIG_PATA_ATP867X is not set
 # CONFIG_PATA_CMD64X is not set
 # CONFIG_PATA_CS5520 is not set
 # CONFIG_PATA_CS5530 is not set
 # CONFIG_PATA_CYPRESS is not set
 # CONFIG_PATA_EFAR is not set
-# CONFIG_ATA_GENERIC is not set
 # CONFIG_PATA_HPT366 is not set
 # CONFIG_PATA_HPT37X is not set
 # CONFIG_PATA_HPT3X2N is not set
 # CONFIG_PATA_HPT3X3 is not set
-# CONFIG_PATA_IT821X is not set
 # CONFIG_PATA_IT8213 is not set
+# CONFIG_PATA_IT821X is not set
 # CONFIG_PATA_JMICRON is not set
-# CONFIG_PATA_TRIFLEX is not set
 # CONFIG_PATA_MARVELL is not set
-# CONFIG_PATA_MPIIX is not set
-# CONFIG_PATA_OLDPIIX is not set
 # CONFIG_PATA_NETCELL is not set
 # CONFIG_PATA_NINJA32 is not set
-# CONFIG_PATA_NS87410 is not set
 # CONFIG_PATA_NS87415 is not set
-# CONFIG_PATA_OPTI is not set
+# CONFIG_PATA_OLDPIIX is not set
 # CONFIG_PATA_OPTIDMA is not set
+# CONFIG_PATA_PDC2027X is not set
 # CONFIG_PATA_PDC_OLD is not set
 # CONFIG_PATA_RADISYS is not set
-# CONFIG_PATA_RZ1000 is not set
+# CONFIG_PATA_RDC is not set
 # CONFIG_PATA_SC1200 is not set
+# CONFIG_PATA_SCH is not set
 # CONFIG_PATA_SERVERWORKS is not set
-# CONFIG_PATA_PDC2027X is not set
 # CONFIG_PATA_SIL680 is not set
 # CONFIG_PATA_SIS is not set
+# CONFIG_PATA_TOSHIBA is not set
+# CONFIG_PATA_TRIFLEX is not set
 # CONFIG_PATA_VIA is not set
 # CONFIG_PATA_WINBOND is not set
+
+#
+# PIO-only SFF controllers
+#
+# CONFIG_PATA_CMD640_PCI is not set
+# CONFIG_PATA_MPIIX is not set
+# CONFIG_PATA_NS87410 is not set
+# CONFIG_PATA_OPTI is not set
 # CONFIG_PATA_PLATFORM is not set
-# CONFIG_PATA_SCH is not set
+# CONFIG_PATA_RZ1000 is not set
+
+#
+# Generic fallback / legacy drivers
+#
+# CONFIG_ATA_GENERIC is not set
+# CONFIG_PATA_LEGACY is not set
 # CONFIG_MD is not set
 # CONFIG_FUSION is not set
 
@@ -763,7 +854,7 @@ CONFIG_ATA_SFF=y
 #
 
 #
-# See the help texts for more information.
+# The newer stack is recommended.
 #
 # CONFIG_FIREWIRE is not set
 # CONFIG_IEEE1394 is not set
@@ -787,6 +878,7 @@ CONFIG_MII=y
 # CONFIG_SMC91X is not set
 # CONFIG_DM9000 is not set
 # CONFIG_ETHOC is not set
+# CONFIG_SMSC911X is not set
 # CONFIG_DNET is not set
 # CONFIG_NET_TULIP is not set
 # CONFIG_HP100 is not set
@@ -800,6 +892,7 @@ CONFIG_MII=y
 # CONFIG_NET_PCI is not set
 # CONFIG_B44 is not set
 # CONFIG_KS8842 is not set
+# CONFIG_KS8851_MLL is not set
 # CONFIG_ATL2 is not set
 CONFIG_NETDEV_1000=y
 # CONFIG_ACENIC is not set
@@ -829,6 +922,8 @@ CONFIG_NETDEV_10000=y
 # CONFIG_CHELSIO_T1 is not set
 CONFIG_CHELSIO_T3_DEPENDS=y
 # CONFIG_CHELSIO_T3 is not set
+CONFIG_CHELSIO_T4_DEPENDS=y
+# CONFIG_CHELSIO_T4 is not set
 # CONFIG_ENIC is not set
 # CONFIG_IXGBE is not set
 # CONFIG_IXGB is not set
@@ -841,16 +936,12 @@ CONFIG_CHELSIO_T3_DEPENDS=y
 # CONFIG_MLX4_CORE is not set
 # CONFIG_TEHUTI is not set
 # CONFIG_BNX2X is not set
+# CONFIG_QLCNIC is not set
 # CONFIG_QLGE is not set
 # CONFIG_SFC is not set
 # CONFIG_BE2NET is not set
 # CONFIG_TR is not set
-
-#
-# Wireless LAN
-#
-# CONFIG_WLAN_PRE80211 is not set
-# CONFIG_WLAN_80211 is not set
+# CONFIG_WLAN is not set
 
 #
 # Enable WiMAX (Networking options) to see the WiMAX drivers
@@ -864,6 +955,7 @@ CONFIG_CHELSIO_T3_DEPENDS=y
 # CONFIG_USB_PEGASUS is not set
 CONFIG_USB_RTL8150=y
 # CONFIG_USB_USBNET is not set
+# CONFIG_USB_IPHETH is not set
 # CONFIG_WAN is not set
 # CONFIG_FDDI is not set
 # CONFIG_HIPPI is not set
@@ -873,6 +965,7 @@ CONFIG_USB_RTL8150=y
 # CONFIG_NETCONSOLE is not set
 # CONFIG_NETPOLL is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_VMXNET3 is not set
 # CONFIG_ISDN is not set
 # CONFIG_PHONE is not set
 
@@ -882,6 +975,7 @@ CONFIG_USB_RTL8150=y
 CONFIG_INPUT=y
 # CONFIG_INPUT_FF_MEMLESS is not set
 # CONFIG_INPUT_POLLDEV is not set
+# CONFIG_INPUT_SPARSEKMAP is not set
 
 #
 # Userland interfaces
@@ -913,6 +1007,7 @@ CONFIG_INPUT_EVDEV=y
 # CONFIG_VT is not set
 # CONFIG_DEVKMEM is not set
 # CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_N_GSM is not set
 # CONFIG_NOZOMI is not set
 
 #
@@ -924,6 +1019,9 @@ CONFIG_INPUT_EVDEV=y
 # Non-8250 serial port support
 #
 # CONFIG_SERIAL_JSM is not set
+# CONFIG_SERIAL_TIMBERDALE is not set
+# CONFIG_SERIAL_ALTERA_JTAGUART is not set
+# CONFIG_SERIAL_ALTERA_UART is not set
 CONFIG_UNIX98_PTYS=y
 # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
 # CONFIG_LEGACY_PTYS is not set
@@ -934,6 +1032,7 @@ CONFIG_UNIX98_PTYS=y
 # CONFIG_RAW_DRIVER is not set
 # CONFIG_TCG_TPM is not set
 CONFIG_DEVPORT=y
+# CONFIG_RAMOOPS is not set
 # CONFIG_I2C is not set
 # CONFIG_SPI is not set
 
@@ -945,7 +1044,6 @@ CONFIG_DEVPORT=y
 # CONFIG_POWER_SUPPLY is not set
 # CONFIG_HWMON is not set
 # CONFIG_THERMAL is not set
-# CONFIG_THERMAL_HWMON is not set
 # CONFIG_WATCHDOG is not set
 CONFIG_SSB_POSSIBLE=y
 
@@ -953,20 +1051,14 @@ CONFIG_SSB_POSSIBLE=y
 # Sonics Silicon Backplane
 #
 # CONFIG_SSB is not set
-
-#
-# Multifunction device drivers
-#
-# CONFIG_MFD_CORE is not set
-# CONFIG_MFD_SM501 is not set
-# CONFIG_HTC_PASIC3 is not set
-# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_SUPPORT is not set
 # CONFIG_REGULATOR is not set
 # CONFIG_MEDIA_SUPPORT is not set
 
 #
 # Graphics support
 #
+# CONFIG_VGA_ARB is not set
 # CONFIG_DRM is not set
 # CONFIG_VGASTATE is not set
 # CONFIG_VIDEO_OUTPUT_CONTROL is not set
@@ -980,7 +1072,6 @@ CONFIG_SSB_POSSIBLE=y
 # CONFIG_SOUND is not set
 CONFIG_HID_SUPPORT=y
 CONFIG_HID=y
-# CONFIG_HID_DEBUG is not set
 # CONFIG_HIDRAW is not set
 
 #
@@ -993,31 +1084,43 @@ CONFIG_USB_HIDDEV=y
 #
 # Special HID drivers
 #
+# CONFIG_HID_3M_PCT is not set
 # CONFIG_HID_A4TECH is not set
 # CONFIG_HID_APPLE is not set
 # CONFIG_HID_BELKIN is not set
+# CONFIG_HID_CANDO is not set
 # CONFIG_HID_CHERRY is not set
 # CONFIG_HID_CHICONY is not set
 # CONFIG_HID_CYPRESS is not set
 # CONFIG_HID_DRAGONRISE is not set
+# CONFIG_HID_EGALAX is not set
 # CONFIG_HID_EZKEY is not set
 # CONFIG_HID_KYE is not set
 # CONFIG_HID_GYRATION is not set
+# CONFIG_HID_TWINHAN is not set
 # CONFIG_HID_KENSINGTON is not set
 # CONFIG_HID_LOGITECH is not set
 # CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MOSART is not set
 # CONFIG_HID_MONTEREY is not set
 # CONFIG_HID_NTRIG is not set
+# CONFIG_HID_ORTEK is not set
 # CONFIG_HID_PANTHERLORD is not set
 # CONFIG_HID_PETALYNX is not set
+# CONFIG_HID_PICOLCD is not set
+# CONFIG_HID_QUANTA is not set
+# CONFIG_HID_ROCCAT is not set
+# CONFIG_HID_ROCCAT_KONE is not set
 # CONFIG_HID_SAMSUNG is not set
 # CONFIG_HID_SONY is not set
+# CONFIG_HID_STANTUM is not set
 # CONFIG_HID_SUNPLUS is not set
 # CONFIG_HID_GREENASIA is not set
 # CONFIG_HID_SMARTJOYPLUS is not set
 # CONFIG_HID_TOPSEED is not set
 # CONFIG_HID_THRUSTMASTER is not set
 # CONFIG_HID_ZEROPLUS is not set
+# CONFIG_HID_ZYDACRON is not set
 CONFIG_USB_SUPPORT=y
 CONFIG_USB_ARCH_HAS_HCD=y
 CONFIG_USB_ARCH_HAS_OHCI=y
@@ -1032,7 +1135,6 @@ CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
 CONFIG_USB_DEVICEFS=y
 # CONFIG_USB_DEVICE_CLASS is not set
 # CONFIG_USB_DYNAMIC_MINORS is not set
-# CONFIG_USB_OTG is not set
 # CONFIG_USB_OTG_WHITELIST is not set
 # CONFIG_USB_OTG_BLACKLIST_HUB is not set
 # CONFIG_USB_MON is not set
@@ -1050,6 +1152,7 @@ CONFIG_USB_EHCI_HCD=y
 # CONFIG_USB_OXU210HP_HCD is not set
 # CONFIG_USB_ISP116X_HCD is not set
 # CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
 CONFIG_USB_OHCI_HCD=y
 # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
 # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
@@ -1133,6 +1236,7 @@ CONFIG_USB_SERIAL_CP210X=y
 # CONFIG_USB_SERIAL_NAVMAN is not set
 # CONFIG_USB_SERIAL_PL2303 is not set
 # CONFIG_USB_SERIAL_OTI6858 is not set
+# CONFIG_USB_SERIAL_QCAUX is not set
 # CONFIG_USB_SERIAL_QUALCOMM is not set
 # CONFIG_USB_SERIAL_SPCP8X5 is not set
 # CONFIG_USB_SERIAL_HP4X is not set
@@ -1146,6 +1250,8 @@ CONFIG_USB_SERIAL_CP210X=y
 # CONFIG_USB_SERIAL_OPTION is not set
 # CONFIG_USB_SERIAL_OMNINET is not set
 # CONFIG_USB_SERIAL_OPTICON is not set
+# CONFIG_USB_SERIAL_VIVOPAY_SERIAL is not set
+# CONFIG_USB_SERIAL_ZIO is not set
 # CONFIG_USB_SERIAL_DEBUG is not set
 
 #
@@ -1158,7 +1264,6 @@ CONFIG_USB_SERIAL_CP210X=y
 # CONFIG_USB_RIO500 is not set
 # CONFIG_USB_LEGOTOWER is not set
 # CONFIG_USB_LCD is not set
-# CONFIG_USB_BERRY_CHARGE is not set
 # CONFIG_USB_LED is not set
 # CONFIG_USB_CYPRESS_CY7C63 is not set
 # CONFIG_USB_CYTHERM is not set
@@ -1171,7 +1276,6 @@ CONFIG_USB_SERIAL_CP210X=y
 # CONFIG_USB_IOWARRIOR is not set
 # CONFIG_USB_TEST is not set
 # CONFIG_USB_ISIGHTFW is not set
-# CONFIG_USB_VST is not set
 # CONFIG_USB_GADGET is not set
 
 #
@@ -1189,10 +1293,6 @@ CONFIG_RTC_LIB=y
 # CONFIG_DMADEVICES is not set
 # CONFIG_AUXDISPLAY is not set
 # CONFIG_UIO is not set
-
-#
-# TI VLYNQ
-#
 # CONFIG_STAGING is not set
 
 #
@@ -1214,6 +1314,7 @@ CONFIG_JBD=y
 # CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
 # CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
 CONFIG_FILE_LOCKING=y
 CONFIG_FSNOTIFY=y
 # CONFIG_DNOTIFY is not set
@@ -1274,6 +1375,7 @@ CONFIG_JFFS2_ZLIB=y
 # CONFIG_JFFS2_LZO is not set
 CONFIG_JFFS2_RTIME=y
 # CONFIG_JFFS2_RUBIN is not set
+# CONFIG_LOGFS is not set
 CONFIG_CRAMFS=y
 # CONFIG_SQUASHFS is not set
 # CONFIG_VXFS_FS is not set
@@ -1284,7 +1386,6 @@ CONFIG_CRAMFS=y
 # CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
-# CONFIG_NILFS2_FS is not set
 CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
@@ -1299,6 +1400,7 @@ CONFIG_SUNRPC=y
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 # CONFIG_SMB_FS is not set
+# CONFIG_CEPH_FS is not set
 # CONFIG_CIFS is not set
 # CONFIG_NCP_FS is not set
 # CONFIG_CODA_FS is not set
@@ -1360,6 +1462,7 @@ CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_ENABLE_MUST_CHECK=y
 CONFIG_FRAME_WARN=1024
 # CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_STRIP_ASM_SYMS is not set
 # CONFIG_UNUSED_SYMBOLS is not set
 CONFIG_DEBUG_FS=y
 # CONFIG_HEADERS_CHECK is not set
@@ -1393,15 +1496,25 @@ CONFIG_DEBUG_INFO=y
 # CONFIG_DEBUG_LIST is not set
 # CONFIG_DEBUG_SG is not set
 # CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
 # CONFIG_BOOT_PRINTK_DELAY is not set
 # CONFIG_RCU_TORTURE_TEST is not set
 # CONFIG_RCU_CPU_STALL_DETECTOR is not set
 # CONFIG_BACKTRACE_SELF_TEST is not set
 # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_LKDTM is not set
 # CONFIG_FAULT_INJECTION is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
 # CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
 CONFIG_TRACING_SUPPORT=y
 CONFIG_FTRACE=y
+# CONFIG_FUNCTION_TRACER is not set
 # CONFIG_IRQSOFF_TRACER is not set
 # CONFIG_PREEMPT_TRACER is not set
 # CONFIG_SCHED_TRACER is not set
@@ -1410,19 +1523,22 @@ CONFIG_FTRACE=y
 CONFIG_BRANCH_PROFILE_NONE=y
 # CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
 # CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_STACK_TRACER is not set
 # CONFIG_KMEMTRACE is not set
 # CONFIG_WORKQUEUE_TRACER is not set
 # CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_DYNAMIC_DEBUG is not set
+# CONFIG_ATOMIC64_SELFTEST is not set
 # CONFIG_SAMPLES is not set
 CONFIG_HAVE_ARCH_KGDB=y
 # CONFIG_KGDB is not set
-# CONFIG_KMEMCHECK is not set
+# CONFIG_EARLY_PRINTK is not set
 CONFIG_CMDLINE_BOOL=y
-CONFIG_CMDLINE="rw dhash_entries=1024 ihash_entries=1024 ip=10.0.1.3:10.0.1.1:10.0.1.1:255.255.255.0:zeus:eth0: root=/dev/nfs nfsroot=/nfsroot/cramfs,wsize=512,rsize=512,tcp nokgdb console=ttyUSB0,115200 memsize=252M"
+CONFIG_CMDLINE=""
 # CONFIG_CMDLINE_OVERRIDE is not set
 # CONFIG_DEBUG_STACK_USAGE is not set
 # CONFIG_RUNTIME_DEBUG is not set
+# CONFIG_SPINLOCK_TEST is not set
 
 #
 # Security options
@@ -1430,13 +1546,16 @@ CONFIG_CMDLINE="rw dhash_entries=1024 ihash_entries=1024 ip=10.0.1.3:10.0.1.1:10
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
 # CONFIG_SECURITYFS is not set
-# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_DEFAULT_SECURITY_SELINUX is not set
+# CONFIG_DEFAULT_SECURITY_SMACK is not set
+# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
 CONFIG_CRYPTO=y
 
 #
 # Crypto core or helper
 #
-# CONFIG_CRYPTO_FIPS is not set
 CONFIG_CRYPTO_ALGAPI=y
 CONFIG_CRYPTO_ALGAPI2=y
 CONFIG_CRYPTO_AEAD=y
@@ -1479,11 +1598,13 @@ CONFIG_CRYPTO_CBC=y
 #
 CONFIG_CRYPTO_HMAC=y
 # CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
 
 #
 # Digest
 #
 # CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_GHASH is not set
 # CONFIG_CRYPTO_MD4 is not set
 CONFIG_CRYPTO_MD5=y
 # CONFIG_CRYPTO_MICHAEL_MIC is not set
diff --git a/arch/mips/dec/Makefile b/arch/mips/dec/Makefile
index c530208ee154..9eb2f9c036aa 100644
--- a/arch/mips/dec/Makefile
+++ b/arch/mips/dec/Makefile
@@ -8,5 +8,3 @@ obj-y		:= ecc-berr.o int-handler.o ioasic-irq.o kn01-berr.o \
 obj-$(CONFIG_PROM_CONSOLE)      += promcon.o
 obj-$(CONFIG_TC)                += tc.o
 obj-$(CONFIG_CPU_HAS_WB)        += wbflush.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/dec/Platform b/arch/mips/dec/Platform
new file mode 100644
index 000000000000..3adbcbd95db1
--- /dev/null
+++ b/arch/mips/dec/Platform
@@ -0,0 +1,8 @@
+#
+# DECstation family
+#
+platform-$(CONFIG_MACH_DECSTATION)      = dec/
+cflags-$(CONFIG_MACH_DECSTATION)        += \
+                        -I$(srctree)/arch/mips/include/asm/mach-dec
+libs-$(CONFIG_MACH_DECSTATION)          += arch/mips/dec/prom/
+load-$(CONFIG_MACH_DECSTATION)          += 0xffffffff80040000
diff --git a/arch/mips/dec/promcon.c b/arch/mips/dec/promcon.c
index 9f0972f5a702..c239c25b79ff 100644
--- a/arch/mips/dec/promcon.c
+++ b/arch/mips/dec/promcon.c
@@ -33,8 +33,7 @@ static int __init prom_console_setup(struct console *co, char *options)
         return 0;
 }
 
-static struct console sercons =
-{
+static struct console sercons = {
         .name   = "ttyS",
         .write  = prom_console_write,
         .setup  = prom_console_setup,
diff --git a/arch/mips/emma/Makefile b/arch/mips/emma/Makefile
new file mode 100644
index 000000000000..4254a31edb09
--- /dev/null
+++ b/arch/mips/emma/Makefile
@@ -0,0 +1,6 @@
+obj-$(CONFIG_SOC_EMMA2RH)       += common/
+
+#
+# NEC EMMA2RH Mark-eins
+#
+obj-$(CONFIG_NEC_MARKEINS)      += markeins/
diff --git a/arch/mips/emma/Platform b/arch/mips/emma/Platform
new file mode 100644
index 000000000000..0282f7f99b88
--- /dev/null
+++ b/arch/mips/emma/Platform
@@ -0,0 +1,4 @@
+platform-$(CONFIG_SOC_EMMA2RH)  += emma/
+cflags-$(CONFIG_SOC_EMMA2RH)    +=                                      \
+                -I$(srctree)/arch/mips/include/asm/mach-emma2rh
+load-$(CONFIG_NEC_MARKEINS)     += 0xffffffff88100000
diff --git a/arch/mips/emma/markeins/irq.c b/arch/mips/emma/markeins/irq.c
index 9504b7ee0b7c..3a96799eb65f 100644
--- a/arch/mips/emma/markeins/irq.c
+++ b/arch/mips/emma/markeins/irq.c
@@ -301,7 +301,7 @@ void __init arch_init_irq(void)
         /* setup cascade interrupts */
         setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_SW_CASCADE, &irq_cascade);
         setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_GPIO_CASCADE, &irq_cascade);
-        setup_irq(CPU_IRQ_BASE + CPU_EMMA2RH_CASCADE, &irq_cascade);
+        setup_irq(MIPS_CPU_IRQ_BASE + 2, &irq_cascade);
 }
 
 asmlinkage void plat_irq_dispatch(void)
@@ -309,13 +309,13 @@ asmlinkage void plat_irq_dispatch(void)
         unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
 
         if (pending & STATUSF_IP7)
-                do_IRQ(CPU_IRQ_BASE + 7);
+                do_IRQ(MIPS_CPU_IRQ_BASE + 7);
         else if (pending & STATUSF_IP2)
                 emma2rh_irq_dispatch();
         else if (pending & STATUSF_IP1)
-                do_IRQ(CPU_IRQ_BASE + 1);
+                do_IRQ(MIPS_CPU_IRQ_BASE + 1);
         else if (pending & STATUSF_IP0)
-                do_IRQ(CPU_IRQ_BASE + 0);
+                do_IRQ(MIPS_CPU_IRQ_BASE + 0);
         else
                 spurious_interrupt();
 }
diff --git a/arch/mips/emma/markeins/setup.c b/arch/mips/emma/markeins/setup.c
index 9b3f51e5f140..feceebcfff42 100644
--- a/arch/mips/emma/markeins/setup.c
+++ b/arch/mips/emma/markeins/setup.c
@@ -52,7 +52,6 @@ static void markeins_machine_halt(void)
 
 static void markeins_machine_power_off(void)
 {
-        printk("EMMA2RH Mark-eins halted. Please turn off the power.\n");
         markeins_led("poweroff.");
         while (1) ;
 }
diff --git a/arch/mips/include/asm/arch_hweight.h b/arch/mips/include/asm/arch_hweight.h
new file mode 100644
index 000000000000..712a7445ee93
--- /dev/null
+++ b/arch/mips/include/asm/arch_hweight.h
@@ -0,0 +1,38 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ */
+#ifndef _ASM_ARCH_HWEIGHT_H
+#define _ASM_ARCH_HWEIGHT_H
+
+#ifdef ARCH_HAS_USABLE_BUILTIN_POPCOUNT
+
+#include <asm/types.h>
+
+static inline unsigned int __arch_hweight32(unsigned int w)
+{
+        return __builtin_popcount(w);
+}
+
+static inline unsigned int __arch_hweight16(unsigned int w)
+{
+        return __builtin_popcount(w & 0xffff);
+}
+
+static inline unsigned int __arch_hweight8(unsigned int w)
+{
+        return __builtin_popcount(w & 0xff);
+}
+
+static inline unsigned long __arch_hweight64(__u64 w)
+{
+        return __builtin_popcountll(w);
+}
+
+#else
+#include <asm-generic/bitops/arch_hweight.h>
+#endif
+
+#endif /* _ASM_ARCH_HWEIGHT_H */
diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h
index 9255cfbee459..b0ce7ca2851f 100644
--- a/arch/mips/include/asm/bitops.h
+++ b/arch/mips/include/asm/bitops.h
@@ -700,7 +700,10 @@ static inline int ffs(int word)
 #ifdef __KERNEL__
 
 #include <asm-generic/bitops/sched.h>
-#include <asm-generic/bitops/hweight.h>
+
+#include <asm/arch_hweight.h>
+#include <asm-generic/bitops/const_hweight.h>
+
 #include <asm-generic/bitops/ext2-non-atomic.h>
 #include <asm-generic/bitops/ext2-atomic.h>
 #include <asm-generic/bitops/minix.h>
diff --git a/arch/mips/include/asm/bootinfo.h b/arch/mips/include/asm/bootinfo.h
index 09eee09780f2..15a8ef0707c6 100644
--- a/arch/mips/include/asm/bootinfo.h
+++ b/arch/mips/include/asm/bootinfo.h
@@ -71,6 +71,12 @@
 #define MACH_LEMOTE_LL2F       7
 #define MACH_LOONGSON_END      8
 
+/*
+ * Valid machtype for group INGENIC
+ */
+#define  MACH_INGENIC_JZ4730    0       /* JZ4730 SOC           */
+#define  MACH_INGENIC_JZ4740    1       /* JZ4740 SOC           */
+
 extern char *system_type;
 const char *get_system_type(void);
 
diff --git a/arch/mips/include/asm/break.h b/arch/mips/include/asm/break.h
index 44437ed765e8..9161e684cb4c 100644
--- a/arch/mips/include/asm/break.h
+++ b/arch/mips/include/asm/break.h
@@ -30,6 +30,8 @@
 #define BRK_BUG         512     /* Used by BUG() */
 #define BRK_KDB         513     /* Used in KDB_ENTER() */
 #define BRK_MEMU        514     /* Used by FPU emulator */
+#define BRK_KPROBE_BP   515     /* Kprobe break */
+#define BRK_KPROBE_SSTEPBP 516  /* Kprobe single step software implementation */
 #define BRK_MULOVF      1023    /* Multiply overflow */
 
 #endif /* __ASM_BREAK_H */
diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h
index 256ad2cc6eb8..8f99c11ab665 100644
--- a/arch/mips/include/asm/cacheops.h
+++ b/arch/mips/include/asm/cacheops.h
@@ -62,6 +62,8 @@
  * RM7000-specific cacheops
  */
 #define Page_Invalidate_T       0x16
+#define Index_Store_Tag_T       0x0a
+#define Index_Load_Tag_T        0x06
 
 /*
  * R10000-specific cacheops
diff --git a/arch/mips/include/asm/cop2.h b/arch/mips/include/asm/cop2.h
index 6b04c98b7fad..2cb2f0c2c4f8 100644
--- a/arch/mips/include/asm/cop2.h
+++ b/arch/mips/include/asm/cop2.h
@@ -9,6 +9,8 @@
 #ifndef __ASM_COP2_H
 #define __ASM_COP2_H
 
+#include <linux/notifier.h>
+
 enum cu2_ops {
         CU2_EXCEPTION,
         CU2_LWC2_OP,
@@ -20,4 +22,14 @@ enum cu2_ops {
 extern int register_cu2_notifier(struct notifier_block *nb);
 extern int cu2_notifier_call_chain(unsigned long val, void *v);
 
+#define cu2_notifier(fn, pri)                                           \
+({                                                                      \
+        static struct notifier_block fn##_nb __cpuinitdata = {          \
+                .notifier_call = fn,                                    \
+                .priority = pri                                         \
+        };                                                              \
+                                                                        \
+        register_cu2_notifier(&fn##_nb);                                \
+})
+
 #endif /* __ASM_COP2_H */
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index ac73cede3a0a..ca400f7c3f59 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -159,7 +159,8 @@
 
 /*
  * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other
- * pre-MIPS32/MIPS53 processors have CLO, CLZ.  For 64-bit kernels
+ * pre-MIPS32/MIPS53 processors have CLO, CLZ.  The IDT RC64574 is 64-bit and
+ * has CLO and CLZ but not DCLO nor DCLZ.  For 64-bit kernels
  * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ.
  */
 # ifndef cpu_has_clo_clz
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index a5acda416946..b201a8f5b127 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -34,7 +34,7 @@
 #define PRID_COMP_LSI           0x080000
 #define PRID_COMP_LEXRA         0x0b0000
 #define PRID_COMP_CAVIUM        0x0d0000
-
+#define PRID_COMP_INGENIC       0xd00000
 
 /*
  * Assigned values for the product ID register.  In order to detect a
@@ -133,6 +133,12 @@
 #define PRID_IMP_CAVIUM_CN52XX 0x0700
 
 /*
+ * These are the PRID's for when 23:16 == PRID_COMP_INGENIC
+ */
+
+#define PRID_IMP_JZRISC        0x0200
+
+/*
  * Definitions for 7:0 on legacy processors
  */
 
@@ -219,6 +225,7 @@ enum cpu_type_enum {
         CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
         CPU_ALCHEMY, CPU_PR4450, CPU_BCM3302, CPU_BCM4710,
         CPU_BCM6338, CPU_BCM6345, CPU_BCM6348, CPU_BCM6358,
+        CPU_JZRISC,
 
         /*
          * MIPS64 class processors
diff --git a/arch/mips/include/asm/elf.h b/arch/mips/include/asm/elf.h
index ea77a42c5f8c..fd1d39eb7431 100644
--- a/arch/mips/include/asm/elf.h
+++ b/arch/mips/include/asm/elf.h
@@ -372,4 +372,9 @@ extern const char *__elf_platform;
 struct linux_binprm;
 extern int arch_setup_additional_pages(struct linux_binprm *bprm,
                                        int uses_interp);
+
+struct mm_struct;
+extern unsigned long arch_randomize_brk(struct mm_struct *mm);
+#define arch_randomize_brk arch_randomize_brk
+
 #endif /* _ASM_ELF_H */
diff --git a/arch/mips/include/asm/emma/emma2rh.h b/arch/mips/include/asm/emma/emma2rh.h
index 2afb2fe11b30..c1449d20ef0e 100644
--- a/arch/mips/include/asm/emma/emma2rh.h
+++ b/arch/mips/include/asm/emma/emma2rh.h
@@ -99,88 +99,22 @@
 #define EMMA2RH_PCI_CONFIG_BASE EMMA2RH_PCI_IO_BASE
 #define EMMA2RH_PCI_CONFIG_SIZE EMMA2RH_PCI_IO_SIZE
 
-#define NUM_CPU_IRQ             8
 #define NUM_EMMA2RH_IRQ         96
 
-#define CPU_EMMA2RH_CASCADE     2
-#define CPU_IRQ_BASE            MIPS_CPU_IRQ_BASE
-#define EMMA2RH_IRQ_BASE        (CPU_IRQ_BASE + NUM_CPU_IRQ)
+#define EMMA2RH_IRQ_BASE        (MIPS_CPU_IRQ_BASE + 8)
 
 /*
  * emma2rh irq defs
  */
 
-#define EMMA2RH_IRQ_INT0        (0 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT1        (1 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT2        (2 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT3        (3 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT4        (4 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT5        (5 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT6        (6 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT7        (7 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT8        (8 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT9        (9 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT10       (10 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT11       (11 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT12       (12 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT13       (13 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT14       (14 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT15       (15 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT16       (16 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT17       (17 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT18       (18 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT19       (19 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT20       (20 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT21       (21 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT22       (22 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT23       (23 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT24       (24 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT25       (25 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT26       (26 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT27       (27 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT28       (28 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT29       (29 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT30       (30 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT31       (31 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT32       (32 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT33       (33 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT34       (34 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT35       (35 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT36       (36 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT37       (37 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT38       (38 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT39       (39 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT40       (40 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT41       (41 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT42       (42 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT43       (43 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT44       (44 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT45       (45 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT46       (46 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT47       (47 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT48       (48 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT49       (49 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT50       (50 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT51       (51 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT52       (52 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT53       (53 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT54       (54 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT55       (55 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT56       (56 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT57       (57 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT58       (58 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT59       (59 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT60       (60 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT61       (61 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT62       (62 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT63       (63 + EMMA2RH_IRQ_BASE)
-
-#define EMMA2RH_IRQ_PFUR0       EMMA2RH_IRQ_INT49
-#define EMMA2RH_IRQ_PFUR1       EMMA2RH_IRQ_INT50
-#define EMMA2RH_IRQ_PFUR2       EMMA2RH_IRQ_INT51
-#define EMMA2RH_IRQ_PIIC0       EMMA2RH_IRQ_INT56
-#define EMMA2RH_IRQ_PIIC1       EMMA2RH_IRQ_INT57
-#define EMMA2RH_IRQ_PIIC2       EMMA2RH_IRQ_INT58
+#define EMMA2RH_IRQ_INT(n)      (EMMA2RH_IRQ_BASE + (n))
+
+#define EMMA2RH_IRQ_PFUR0       EMMA2RH_IRQ_INT(49)
+#define EMMA2RH_IRQ_PFUR1       EMMA2RH_IRQ_INT(50)
+#define EMMA2RH_IRQ_PFUR2       EMMA2RH_IRQ_INT(51)
+#define EMMA2RH_IRQ_PIIC0       EMMA2RH_IRQ_INT(56)
+#define EMMA2RH_IRQ_PIIC1       EMMA2RH_IRQ_INT(57)
+#define EMMA2RH_IRQ_PIIC2       EMMA2RH_IRQ_INT(58)
 
 /*
  *  EMMA2RH Register Access
diff --git a/arch/mips/include/asm/emma/markeins.h b/arch/mips/include/asm/emma/markeins.h
index 2618bf230248..bf2d229c2dae 100644
--- a/arch/mips/include/asm/emma/markeins.h
+++ b/arch/mips/include/asm/emma/markeins.h
@@ -25,44 +25,13 @@
 #define NUM_EMMA2RH_IRQ_SW      32
 #define NUM_EMMA2RH_IRQ_GPIO    32
 
-#define EMMA2RH_SW_CASCADE      (EMMA2RH_IRQ_INT7 - EMMA2RH_IRQ_INT0)
-#define EMMA2RH_GPIO_CASCADE    (EMMA2RH_IRQ_INT46 - EMMA2RH_IRQ_INT0)
+#define EMMA2RH_SW_CASCADE      (EMMA2RH_IRQ_INT(7) - EMMA2RH_IRQ_INT(0))
+#define EMMA2RH_GPIO_CASCADE    (EMMA2RH_IRQ_INT(46) - EMMA2RH_IRQ_INT(0))
 
 #define EMMA2RH_SW_IRQ_BASE     (EMMA2RH_IRQ_BASE + NUM_EMMA2RH_IRQ)
 #define EMMA2RH_GPIO_IRQ_BASE   (EMMA2RH_SW_IRQ_BASE + NUM_EMMA2RH_IRQ_SW)
 
-#define EMMA2RH_SW_IRQ_INT0     (0+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT1     (1+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT2     (2+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT3     (3+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT4     (4+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT5     (5+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT6     (6+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT7     (7+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT8     (8+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT9     (9+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT10    (10+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT11    (11+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT12    (12+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT13    (13+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT14    (14+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT15    (15+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT16    (16+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT17    (17+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT18    (18+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT19    (19+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT20    (20+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT21    (21+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT22    (22+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT23    (23+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT24    (24+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT25    (25+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT26    (26+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT27    (27+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT28    (28+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT29    (29+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT30    (30+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT31    (31+EMMA2RH_SW_IRQ_BASE)
+#define EMMA2RH_SW_IRQ_INT(n)   (EMMA2RH_SW_IRQ_BASE + (n))
 
 #define MARKEINS_PCI_IRQ_INTA   EMMA2RH_GPIO_IRQ_BASE+15
 #define MARKEINS_PCI_IRQ_INTB   EMMA2RH_GPIO_IRQ_BASE+16
diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h
index 0eaf77ffbc4f..4e332165d7b7 100644
--- a/arch/mips/include/asm/hazards.h
+++ b/arch/mips/include/asm/hazards.h
@@ -87,7 +87,7 @@ do {									\
         : "=r" (tmp));                                                  \
 } while (0)
 
-#elif defined(CONFIG_CPU_MIPSR1) && !defined(CONFIG_MACH_ALCHEMY)
+#elif defined(CONFIG_CPU_MIPSR1) && !defined(CONFIG_MIPS_ALCHEMY)
 
 /*
  * These are slightly complicated by the fact that we guarantee R1 kernels to
@@ -138,7 +138,7 @@ do {									\
                 __instruction_hazard();                                 \
 } while (0)
 
-#elif defined(CONFIG_MACH_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \
+#elif defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \
       defined(CONFIG_CPU_LOONGSON2) || defined(CONFIG_CPU_R10000) || \
       defined(CONFIG_CPU_R5500)
 
diff --git a/arch/mips/include/asm/inst.h b/arch/mips/include/asm/inst.h
index 6489f00731ca..444ff71aa0e8 100644
--- a/arch/mips/include/asm/inst.h
+++ b/arch/mips/include/asm/inst.h
@@ -247,6 +247,12 @@ struct ma_format {	/* FPU multipy and add format (MIPS IV) */
         unsigned int fmt : 2;
 };
 
+struct b_format { /* BREAK and SYSCALL */
+        unsigned int opcode:6;
+        unsigned int code:20;
+        unsigned int func:6;
+};
+
 #elif defined(__MIPSEL__)
 
 struct j_format {       /* Jump format */
@@ -314,6 +320,12 @@ struct ma_format {	/* FPU multipy and add format (MIPS IV) */
         unsigned int opcode : 6;
 };
 
+struct b_format { /* BREAK and SYSCALL */
+        unsigned int func:6;
+        unsigned int code:20;
+        unsigned int opcode:6;
+};
+
 #else /* !defined (__MIPSEB__) && !defined (__MIPSEL__) */
 #error "MIPS but neither __MIPSEL__ nor __MIPSEB__?"
 #endif
@@ -328,7 +340,8 @@ union mips_instruction {
         struct c_format c_format;
         struct r_format r_format;
         struct f_format f_format;
-        struct ma_format ma_format;
+        struct ma_format ma_format;
+        struct b_format b_format;
 };
 
 /* HACHACHAHCAHC ...  */
diff --git a/arch/mips/include/asm/kdebug.h b/arch/mips/include/asm/kdebug.h
index 5bf62aafc890..6a9af5fcb5d7 100644
--- a/arch/mips/include/asm/kdebug.h
+++ b/arch/mips/include/asm/kdebug.h
@@ -8,6 +8,9 @@ enum die_val {
         DIE_FP,
         DIE_TRAP,
         DIE_RI,
+        DIE_PAGE_FAULT,
+        DIE_BREAK,
+        DIE_SSTEPBP
 };
 
 #endif /* _ASM_MIPS_KDEBUG_H */
diff --git a/arch/mips/include/asm/kprobes.h b/arch/mips/include/asm/kprobes.h
new file mode 100644
index 000000000000..e6ea4d4d7205
--- /dev/null
+++ b/arch/mips/include/asm/kprobes.h
@@ -0,0 +1,92 @@
+/*
+ *  Kernel Probes (KProbes)
+ *  include/asm-mips/kprobes.h
+ *
+ *  Copyright 2006 Sony Corp.
+ *  Copyright 2010 Cavium Networks
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; version 2 of the License.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef _ASM_KPROBES_H
+#define _ASM_KPROBES_H
+
+#include <linux/ptrace.h>
+#include <linux/types.h>
+
+#include <asm/cacheflush.h>
+#include <asm/kdebug.h>
+#include <asm/inst.h>
+
+#define  __ARCH_WANT_KPROBES_INSN_SLOT
+
+struct kprobe;
+struct pt_regs;
+
+typedef union mips_instruction kprobe_opcode_t;
+
+#define MAX_INSN_SIZE 2
+
+#define flush_insn_slot(p)                                              \
+do {                                                                    \
+        flush_icache_range((unsigned long)p->addr,                      \
+                           (unsigned long)p->addr +                     \
+                           (MAX_INSN_SIZE * sizeof(kprobe_opcode_t)));  \
+} while (0)
+
+
+#define kretprobe_blacklist_size 0
+
+void arch_remove_kprobe(struct kprobe *p);
+
+/* Architecture specific copy of original instruction*/
+struct arch_specific_insn {
+        /* copy of the original instruction */
+        kprobe_opcode_t *insn;
+};
+
+struct prev_kprobe {
+        struct kprobe *kp;
+        unsigned long status;
+        unsigned long old_SR;
+        unsigned long saved_SR;
+        unsigned long saved_epc;
+};
+
+#define MAX_JPROBES_STACK_SIZE 128
+#define MAX_JPROBES_STACK_ADDR \
+        (((unsigned long)current_thread_info()) + THREAD_SIZE - 32 - sizeof(struct pt_regs))
+
+#define MIN_JPROBES_STACK_SIZE(ADDR)                                    \
+        ((((ADDR) + MAX_JPROBES_STACK_SIZE) > MAX_JPROBES_STACK_ADDR)   \
+                ? MAX_JPROBES_STACK_ADDR - (ADDR)                       \
+                : MAX_JPROBES_STACK_SIZE)
+
+
+/* per-cpu kprobe control block */
+struct kprobe_ctlblk {
+        unsigned long kprobe_status;
+        unsigned long kprobe_old_SR;
+        unsigned long kprobe_saved_SR;
+        unsigned long kprobe_saved_epc;
+        unsigned long jprobe_saved_sp;
+        struct pt_regs jprobe_saved_regs;
+        u8 jprobes_stack[MAX_JPROBES_STACK_SIZE];
+        struct prev_kprobe prev_kprobe;
+};
+
+extern int kprobe_exceptions_notify(struct notifier_block *self,
+                                    unsigned long val, void *data);
+
+#endif                          /* _ASM_KPROBES_H */
diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_eth.h b/arch/mips/include/asm/mach-au1x00/au1xxx_eth.h
index bae9b758fcde..49dc8d9db186 100644
--- a/arch/mips/include/asm/mach-au1x00/au1xxx_eth.h
+++ b/arch/mips/include/asm/mach-au1x00/au1xxx_eth.h
@@ -9,6 +9,7 @@ struct au1000_eth_platform_data {
         int phy_addr;
         int phy_busid;
         int phy_irq;
+        char mac[6];
 };
 
 void __init au1xxx_override_eth_cfg(unsigned port,
diff --git a/arch/mips/include/asm/mach-bcm47xx/nvram.h b/arch/mips/include/asm/mach-bcm47xx/nvram.h
index 0d8cc146f7a4..c58ebd8bc155 100644
--- a/arch/mips/include/asm/mach-bcm47xx/nvram.h
+++ b/arch/mips/include/asm/mach-bcm47xx/nvram.h
@@ -31,6 +31,9 @@ struct nvram_header {
 #define NVRAM_MAX_VALUE_LEN 255
 #define NVRAM_MAX_PARAM_LEN 64
 
+#define NVRAM_ERR_INV_PARAM     -8
+#define NVRAM_ERR_ENVNOTFOUND   -9
+
 extern int nvram_getenv(char *name, char *val, size_t val_len);
 
 #endif
diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
index bbf054042395..b952fc7215e2 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
@@ -61,21 +61,18 @@
 
 #define kernel_uses_smartmips_rixi (cpu_data[0].cputype == CPU_CAVIUM_OCTEON_PLUS)
 
-#define ARCH_HAS_READ_CURRENT_TIMER 1
 #define ARCH_HAS_IRQ_PER_CPU    1
 #define ARCH_HAS_SPINLOCK_PREFETCH 1
 #define spin_lock_prefetch(x) prefetch(x)
 #define PREFETCH_STRIDE 128
 
-static inline int read_current_timer(unsigned long *result)
-{
-        asm volatile ("rdhwr %0,$31\n"
-#ifndef CONFIG_64BIT
-                      "\tsll %0, 0"
+#ifdef __OCTEON__
+/*
+ * All gcc versions that have OCTEON support define __OCTEON__ and have the
+ *  __builtin_popcount support.
+ */
+#define ARCH_HAS_USABLE_BUILTIN_POPCOUNT 1
 #endif
-                      : "=r" (*result));
-        return 0;
-}
 
 static inline int octeon_has_saa(void)
 {
diff --git a/arch/mips/include/asm/mach-cavium-octeon/irq.h b/arch/mips/include/asm/mach-cavium-octeon/irq.h
index d32220fbf4f1..6ddab8aef644 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/irq.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/irq.h
@@ -172,71 +172,9 @@
 #ifdef CONFIG_PCI_MSI
 /* 152 - 215 represent the MSI interrupts 0-63 */
 #define OCTEON_IRQ_MSI_BIT0     152
-#define OCTEON_IRQ_MSI_BIT1     153
-#define OCTEON_IRQ_MSI_BIT2     154
-#define OCTEON_IRQ_MSI_BIT3     155
-#define OCTEON_IRQ_MSI_BIT4     156
-#define OCTEON_IRQ_MSI_BIT5     157
-#define OCTEON_IRQ_MSI_BIT6     158
-#define OCTEON_IRQ_MSI_BIT7     159
-#define OCTEON_IRQ_MSI_BIT8     160
-#define OCTEON_IRQ_MSI_BIT9     161
-#define OCTEON_IRQ_MSI_BIT10    162
-#define OCTEON_IRQ_MSI_BIT11    163
-#define OCTEON_IRQ_MSI_BIT12    164
-#define OCTEON_IRQ_MSI_BIT13    165
-#define OCTEON_IRQ_MSI_BIT14    166
-#define OCTEON_IRQ_MSI_BIT15    167
-#define OCTEON_IRQ_MSI_BIT16    168
-#define OCTEON_IRQ_MSI_BIT17    169
-#define OCTEON_IRQ_MSI_BIT18    170
-#define OCTEON_IRQ_MSI_BIT19    171
-#define OCTEON_IRQ_MSI_BIT20    172
-#define OCTEON_IRQ_MSI_BIT21    173
-#define OCTEON_IRQ_MSI_BIT22    174
-#define OCTEON_IRQ_MSI_BIT23    175
-#define OCTEON_IRQ_MSI_BIT24    176
-#define OCTEON_IRQ_MSI_BIT25    177
-#define OCTEON_IRQ_MSI_BIT26    178
-#define OCTEON_IRQ_MSI_BIT27    179
-#define OCTEON_IRQ_MSI_BIT28    180
-#define OCTEON_IRQ_MSI_BIT29    181
-#define OCTEON_IRQ_MSI_BIT30    182
-#define OCTEON_IRQ_MSI_BIT31    183
-#define OCTEON_IRQ_MSI_BIT32    184
-#define OCTEON_IRQ_MSI_BIT33    185
-#define OCTEON_IRQ_MSI_BIT34    186
-#define OCTEON_IRQ_MSI_BIT35    187
-#define OCTEON_IRQ_MSI_BIT36    188
-#define OCTEON_IRQ_MSI_BIT37    189
-#define OCTEON_IRQ_MSI_BIT38    190
-#define OCTEON_IRQ_MSI_BIT39    191
-#define OCTEON_IRQ_MSI_BIT40    192
-#define OCTEON_IRQ_MSI_BIT41    193
-#define OCTEON_IRQ_MSI_BIT42    194
-#define OCTEON_IRQ_MSI_BIT43    195
-#define OCTEON_IRQ_MSI_BIT44    196
-#define OCTEON_IRQ_MSI_BIT45    197
-#define OCTEON_IRQ_MSI_BIT46    198
-#define OCTEON_IRQ_MSI_BIT47    199
-#define OCTEON_IRQ_MSI_BIT48    200
-#define OCTEON_IRQ_MSI_BIT49    201
-#define OCTEON_IRQ_MSI_BIT50    202
-#define OCTEON_IRQ_MSI_BIT51    203
-#define OCTEON_IRQ_MSI_BIT52    204
-#define OCTEON_IRQ_MSI_BIT53    205
-#define OCTEON_IRQ_MSI_BIT54    206
-#define OCTEON_IRQ_MSI_BIT55    207
-#define OCTEON_IRQ_MSI_BIT56    208
-#define OCTEON_IRQ_MSI_BIT57    209
-#define OCTEON_IRQ_MSI_BIT58    210
-#define OCTEON_IRQ_MSI_BIT59    211
-#define OCTEON_IRQ_MSI_BIT60    212
-#define OCTEON_IRQ_MSI_BIT61    213
-#define OCTEON_IRQ_MSI_BIT62    214
-#define OCTEON_IRQ_MSI_BIT63    215
+#define OCTEON_IRQ_MSI_LAST     (OCTEON_IRQ_MSI_BIT0 + 255)
 
-#define OCTEON_IRQ_LAST         216
+#define OCTEON_IRQ_LAST         (OCTEON_IRQ_MSI_LAST + 1)
 #else
 #define OCTEON_IRQ_LAST         152
 #endif
diff --git a/arch/mips/include/asm/mach-jz4740/base.h b/arch/mips/include/asm/mach-jz4740/base.h
new file mode 100644
index 000000000000..f37318605452
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4740/base.h
@@ -0,0 +1,26 @@
+#ifndef __ASM_MACH_JZ4740_BASE_H__
+#define __ASM_MACH_JZ4740_BASE_H__
+
+#define JZ4740_CPM_BASE_ADDR    0x10000000
+#define JZ4740_INTC_BASE_ADDR   0x10001000
+#define JZ4740_WDT_BASE_ADDR    0x10002000
+#define JZ4740_TCU_BASE_ADDR    0x10002010
+#define JZ4740_RTC_BASE_ADDR    0x10003000
+#define JZ4740_GPIO_BASE_ADDR   0x10010000
+#define JZ4740_AIC_BASE_ADDR    0x10020000
+#define JZ4740_MSC_BASE_ADDR    0x10021000
+#define JZ4740_UART0_BASE_ADDR  0x10030000
+#define JZ4740_UART1_BASE_ADDR  0x10031000
+#define JZ4740_I2C_BASE_ADDR    0x10042000
+#define JZ4740_SSI_BASE_ADDR    0x10043000
+#define JZ4740_SADC_BASE_ADDR   0x10070000
+#define JZ4740_EMC_BASE_ADDR    0x13010000
+#define JZ4740_DMAC_BASE_ADDR   0x13020000
+#define JZ4740_UHC_BASE_ADDR    0x13030000
+#define JZ4740_UDC_BASE_ADDR    0x13040000
+#define JZ4740_LCD_BASE_ADDR    0x13050000
+#define JZ4740_SLCD_BASE_ADDR   0x13050000
+#define JZ4740_CIM_BASE_ADDR    0x13060000
+#define JZ4740_IPU_BASE_ADDR    0x13080000
+
+#endif
diff --git a/arch/mips/include/asm/mach-jz4740/clock.h b/arch/mips/include/asm/mach-jz4740/clock.h
new file mode 100644
index 000000000000..1b7408dd0e23
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4740/clock.h
@@ -0,0 +1,28 @@
+/*
+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under  the terms of the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __ASM_JZ4740_CLOCK_H__
+#define __ASM_JZ4740_CLOCK_H__
+
+enum jz4740_wait_mode {
+        JZ4740_WAIT_MODE_IDLE,
+        JZ4740_WAIT_MODE_SLEEP,
+};
+
+void jz4740_clock_set_wait_mode(enum jz4740_wait_mode mode);
+
+void jz4740_clock_udc_enable_auto_suspend(void);
+void jz4740_clock_udc_disable_auto_suspend(void);
+
+#endif
diff --git a/arch/mips/include/asm/mach-jz4740/cpu-feature-overrides.h b/arch/mips/include/asm/mach-jz4740/cpu-feature-overrides.h
new file mode 100644
index 000000000000..d12e5c6477b9
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4740/cpu-feature-overrides.h
@@ -0,0 +1,51 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ */
+#ifndef __ASM_MACH_JZ4740_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_JZ4740_CPU_FEATURE_OVERRIDES_H
+
+#define cpu_has_tlb 1
+#define cpu_has_4kex            1
+#define cpu_has_3k_cache        0
+#define cpu_has_4k_cache        1
+#define cpu_has_tx39_cache      0
+#define cpu_has_fpu             0
+#define cpu_has_32fpr   0
+#define cpu_has_counter         0
+#define cpu_has_watch           1
+#define cpu_has_divec           1
+#define cpu_has_vce             0
+#define cpu_has_cache_cdex_p    0
+#define cpu_has_cache_cdex_s    0
+#define cpu_has_prefetch        1
+#define cpu_has_mcheck 1
+#define cpu_has_ejtag 1
+#define cpu_has_llsc            1
+#define cpu_has_mips16 0
+#define cpu_has_mdmx 0
+#define cpu_has_mips3d 0
+#define cpu_has_smartmips 0
+#define kernel_uses_llsc        1
+#define cpu_has_vtag_icache     1
+#define cpu_has_dc_aliases      0
+#define cpu_has_ic_fills_f_dc   0
+#define cpu_has_pindexed_dcache 0
+#define cpu_has_mips32r1        1
+#define cpu_has_mips32r2        0
+#define cpu_has_mips64r1        0
+#define cpu_has_mips64r2        0
+#define cpu_has_dsp             0
+#define cpu_has_mipsmt          0
+#define cpu_has_userlocal       0
+#define cpu_has_nofpuex 0
+#define cpu_has_64bits          0
+#define cpu_has_64bit_zero_reg 0
+#define cpu_has_inclusive_pcaches 0
+
+#define cpu_dcache_line_size()  32
+#define cpu_icache_line_size()  32
+
+#endif
diff --git a/arch/mips/include/asm/mach-jz4740/dma.h b/arch/mips/include/asm/mach-jz4740/dma.h
new file mode 100644
index 000000000000..a3be12183599
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4740/dma.h
@@ -0,0 +1,90 @@
+/*
+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ *  JZ7420/JZ4740 DMA definitions
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under  the terms of the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __ASM_MACH_JZ4740_DMA_H__
+#define __ASM_MACH_JZ4740_DMA_H__
+
+struct jz4740_dma_chan;
+
+enum jz4740_dma_request_type {
+        JZ4740_DMA_TYPE_AUTO_REQUEST    = 8,
+        JZ4740_DMA_TYPE_UART_TRANSMIT   = 20,
+        JZ4740_DMA_TYPE_UART_RECEIVE    = 21,
+        JZ4740_DMA_TYPE_SPI_TRANSMIT    = 22,
+        JZ4740_DMA_TYPE_SPI_RECEIVE     = 23,
+        JZ4740_DMA_TYPE_AIC_TRANSMIT    = 24,
+        JZ4740_DMA_TYPE_AIC_RECEIVE     = 25,
+        JZ4740_DMA_TYPE_MMC_TRANSMIT    = 26,
+        JZ4740_DMA_TYPE_MMC_RECEIVE     = 27,
+        JZ4740_DMA_TYPE_TCU             = 28,
+        JZ4740_DMA_TYPE_SADC            = 29,
+        JZ4740_DMA_TYPE_SLCD            = 30,
+};
+
+enum jz4740_dma_width {
+        JZ4740_DMA_WIDTH_32BIT  = 0,
+        JZ4740_DMA_WIDTH_8BIT   = 1,
+        JZ4740_DMA_WIDTH_16BIT  = 2,
+};
+
+enum jz4740_dma_transfer_size {
+        JZ4740_DMA_TRANSFER_SIZE_4BYTE  = 0,
+        JZ4740_DMA_TRANSFER_SIZE_1BYTE  = 1,
+        JZ4740_DMA_TRANSFER_SIZE_2BYTE  = 2,
+        JZ4740_DMA_TRANSFER_SIZE_16BYTE = 3,
+        JZ4740_DMA_TRANSFER_SIZE_32BYTE = 4,
+};
+
+enum jz4740_dma_flags {
+        JZ4740_DMA_SRC_AUTOINC = 0x2,
+        JZ4740_DMA_DST_AUTOINC = 0x1,
+};
+
+enum jz4740_dma_mode {
+        JZ4740_DMA_MODE_SINGLE  = 0,
+        JZ4740_DMA_MODE_BLOCK   = 1,
+};
+
+struct jz4740_dma_config {
+        enum jz4740_dma_width src_width;
+        enum jz4740_dma_width dst_width;
+        enum jz4740_dma_transfer_size transfer_size;
+        enum jz4740_dma_request_type request_type;
+        enum jz4740_dma_flags flags;
+        enum jz4740_dma_mode mode;
+};
+
+typedef void (*jz4740_dma_complete_callback_t)(struct jz4740_dma_chan *, int, void *);
+
+struct jz4740_dma_chan *jz4740_dma_request(void *dev, const char *name);
+void jz4740_dma_free(struct jz4740_dma_chan *dma);
+
+void jz4740_dma_configure(struct jz4740_dma_chan *dma,
+        const struct jz4740_dma_config *config);
+
+
+void jz4740_dma_enable(struct jz4740_dma_chan *dma);
+void jz4740_dma_disable(struct jz4740_dma_chan *dma);
+
+void jz4740_dma_set_src_addr(struct jz4740_dma_chan *dma, dma_addr_t src);
+void jz4740_dma_set_dst_addr(struct jz4740_dma_chan *dma, dma_addr_t dst);
+void jz4740_dma_set_transfer_count(struct jz4740_dma_chan *dma, uint32_t count);
+
+uint32_t jz4740_dma_get_residue(const struct jz4740_dma_chan *dma);
+
+void jz4740_dma_set_complete_cb(struct jz4740_dma_chan *dma,
+        jz4740_dma_complete_callback_t cb);
+
+#endif  /* __ASM_JZ4740_DMA_H__ */
diff --git a/arch/mips/include/asm/mach-jz4740/gpio.h b/arch/mips/include/asm/mach-jz4740/gpio.h
new file mode 100644
index 000000000000..7b74703745bb
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4740/gpio.h
@@ -0,0 +1,398 @@
+/*
+ *  Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
+ *  JZ4740 GPIO pin definitions
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under  the terms of the GNU General Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef _JZ_GPIO_H
+#define _JZ_GPIO_H
+
+#include <linux/types.h>
+
+enum jz_gpio_function {
+    JZ_GPIO_FUNC_NONE,
+    JZ_GPIO_FUNC1,
+    JZ_GPIO_FUNC2,
+    JZ_GPIO_FUNC3,
+};
+
+
+/*
+ Usually a driver for a SoC component has to request several gpio pins and
+ configure them as funcion pins.
+ jz_gpio_bulk_request can be used to ease this process.
+ Usually one would do something like:
+
+ const static struct jz_gpio_bulk_request i2c_pins[] = {
+        JZ_GPIO_BULK_PIN(I2C_SDA),
+        JZ_GPIO_BULK_PIN(I2C_SCK),
+ };
+
+ inside the probe function:
+
+    ret = jz_gpio_bulk_request(i2c_pins, ARRAY_SIZE(i2c_pins));
+    if (ret) {
+        ...
+
+ inside the remove function:
+
+    jz_gpio_bulk_free(i2c_pins, ARRAY_SIZE(i2c_pins));
+
+
+*/
+struct jz_gpio_bulk_request {
+        int gpio;
+        const char *name;
+        enum jz_gpio_function function;
+};
+
+#define JZ_GPIO_BULK_PIN(pin) { \
+    .gpio = JZ_GPIO_ ## pin, \
+    .name = #pin, \
+    .function = JZ_GPIO_FUNC_ ## pin \
+}
+
+int jz_gpio_bulk_request(const struct jz_gpio_bulk_request *request, size_t num);
+void jz_gpio_bulk_free(const struct jz_gpio_bulk_request *request, size_t num);
+void jz_gpio_bulk_suspend(const struct jz_gpio_bulk_request *request, size_t num);
+void jz_gpio_bulk_resume(const struct jz_gpio_bulk_request *request, size_t num);
+void jz_gpio_enable_pullup(unsigned gpio);
+void jz_gpio_disable_pullup(unsigned gpio);
+int jz_gpio_set_function(int gpio, enum jz_gpio_function function);
+
+int jz_gpio_port_direction_input(int port, uint32_t mask);
+int jz_gpio_port_direction_output(int port, uint32_t mask);
+void jz_gpio_port_set_value(int port, uint32_t value, uint32_t mask);
+uint32_t jz_gpio_port_get_value(int port, uint32_t mask);
+
+#include <asm/mach-generic/gpio.h>
+
+#define JZ_GPIO_PORTA(x) ((x) + 32 * 0)
+#define JZ_GPIO_PORTB(x) ((x) + 32 * 1)
+#define JZ_GPIO_PORTC(x) ((x) + 32 * 2)
+#define JZ_GPIO_PORTD(x) ((x) + 32 * 3)
+
+/* Port A function pins */
+#define JZ_GPIO_MEM_DATA0               JZ_GPIO_PORTA(0)
+#define JZ_GPIO_MEM_DATA1               JZ_GPIO_PORTA(1)
+#define JZ_GPIO_MEM_DATA2               JZ_GPIO_PORTA(2)
+#define JZ_GPIO_MEM_DATA3               JZ_GPIO_PORTA(3)
+#define JZ_GPIO_MEM_DATA4               JZ_GPIO_PORTA(4)
+#define JZ_GPIO_MEM_DATA5               JZ_GPIO_PORTA(5)
+#define JZ_GPIO_MEM_DATA6               JZ_GPIO_PORTA(6)
+#define JZ_GPIO_MEM_DATA7               JZ_GPIO_PORTA(7)
+#define JZ_GPIO_MEM_DATA8               JZ_GPIO_PORTA(8)
+#define JZ_GPIO_MEM_DATA9               JZ_GPIO_PORTA(9)
+#define JZ_GPIO_MEM_DATA10              JZ_GPIO_PORTA(10)
+#define JZ_GPIO_MEM_DATA11              JZ_GPIO_PORTA(11)
+#define JZ_GPIO_MEM_DATA12              JZ_GPIO_PORTA(12)
+#define JZ_GPIO_MEM_DATA13              JZ_GPIO_PORTA(13)
+#define JZ_GPIO_MEM_DATA14              JZ_GPIO_PORTA(14)
+#define JZ_GPIO_MEM_DATA15              JZ_GPIO_PORTA(15)
+#define JZ_GPIO_MEM_DATA16              JZ_GPIO_PORTA(16)
+#define JZ_GPIO_MEM_DATA17              JZ_GPIO_PORTA(17)
+#define JZ_GPIO_MEM_DATA18              JZ_GPIO_PORTA(18)
+#define JZ_GPIO_MEM_DATA19              JZ_GPIO_PORTA(19)
+#define JZ_GPIO_MEM_DATA20              JZ_GPIO_PORTA(20)
+#define JZ_GPIO_MEM_DATA21              JZ_GPIO_PORTA(21)
+#define JZ_GPIO_MEM_DATA22              JZ_GPIO_PORTA(22)
+#define JZ_GPIO_MEM_DATA23              JZ_GPIO_PORTA(23)
+#define JZ_GPIO_MEM_DATA24              JZ_GPIO_PORTA(24)
+#define JZ_GPIO_MEM_DATA25              JZ_GPIO_PORTA(25)
+#define JZ_GPIO_MEM_DATA26              JZ_GPIO_PORTA(26)
+#define JZ_GPIO_MEM_DATA27              JZ_GPIO_PORTA(27)
+#define JZ_GPIO_MEM_DATA28              JZ_GPIO_PORTA(28)
+#define JZ_GPIO_MEM_DATA29              JZ_GPIO_PORTA(29)
+#define JZ_GPIO_MEM_DATA30              JZ_GPIO_PORTA(30)
+#define JZ_GPIO_MEM_DATA31              JZ_GPIO_PORTA(31)
+
+#define JZ_GPIO_FUNC_MEM_DATA0          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA1          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA2          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA3          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA4          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA5          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA6          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA7          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA8          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA9          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA10         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA11         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA12         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA13         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA14         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA15         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA16         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA17         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA18         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA19         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA20         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA21         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA22         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA23         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA24         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA25         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA26         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA27         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA28         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA29         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA30         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DATA31         JZ_GPIO_FUNC1
+
+/* Port B function pins */
+#define JZ_GPIO_MEM_ADDR0               JZ_GPIO_PORTB(0)
+#define JZ_GPIO_MEM_ADDR1               JZ_GPIO_PORTB(1)
+#define JZ_GPIO_MEM_ADDR2               JZ_GPIO_PORTB(2)
+#define JZ_GPIO_MEM_ADDR3               JZ_GPIO_PORTB(3)
+#define JZ_GPIO_MEM_ADDR4               JZ_GPIO_PORTB(4)
+#define JZ_GPIO_MEM_ADDR5               JZ_GPIO_PORTB(5)
+#define JZ_GPIO_MEM_ADDR6               JZ_GPIO_PORTB(6)
+#define JZ_GPIO_MEM_ADDR7               JZ_GPIO_PORTB(7)
+#define JZ_GPIO_MEM_ADDR8               JZ_GPIO_PORTB(8)
+#define JZ_GPIO_MEM_ADDR9               JZ_GPIO_PORTB(9)
+#define JZ_GPIO_MEM_ADDR10              JZ_GPIO_PORTB(10)
+#define JZ_GPIO_MEM_ADDR11              JZ_GPIO_PORTB(11)
+#define JZ_GPIO_MEM_ADDR12              JZ_GPIO_PORTB(12)
+#define JZ_GPIO_MEM_ADDR13              JZ_GPIO_PORTB(13)
+#define JZ_GPIO_MEM_ADDR14              JZ_GPIO_PORTB(14)
+#define JZ_GPIO_MEM_ADDR15              JZ_GPIO_PORTB(15)
+#define JZ_GPIO_MEM_ADDR16              JZ_GPIO_PORTB(16)
+#define JZ_GPIO_LCD_CLS                 JZ_GPIO_PORTB(17)
+#define JZ_GPIO_LCD_SPL                 JZ_GPIO_PORTB(18)
+#define JZ_GPIO_MEM_DCS                 JZ_GPIO_PORTB(19)
+#define JZ_GPIO_MEM_RAS                 JZ_GPIO_PORTB(20)
+#define JZ_GPIO_MEM_CAS                 JZ_GPIO_PORTB(21)
+#define JZ_GPIO_MEM_SDWE                JZ_GPIO_PORTB(22)
+#define JZ_GPIO_MEM_CKE                 JZ_GPIO_PORTB(23)
+#define JZ_GPIO_MEM_CKO                 JZ_GPIO_PORTB(24)
+#define JZ_GPIO_MEM_CS0                 JZ_GPIO_PORTB(25)
+#define JZ_GPIO_MEM_CS1                 JZ_GPIO_PORTB(26)
+#define JZ_GPIO_MEM_CS2                 JZ_GPIO_PORTB(27)
+#define JZ_GPIO_MEM_CS3                 JZ_GPIO_PORTB(28)
+#define JZ_GPIO_MEM_RD                  JZ_GPIO_PORTB(29)
+#define JZ_GPIO_MEM_WR                  JZ_GPIO_PORTB(30)
+#define JZ_GPIO_MEM_WE0                 JZ_GPIO_PORTB(31)
+
+#define JZ_GPIO_FUNC_MEM_ADDR0          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR1          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR2          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR3          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR4          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR5          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR6          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR7          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR8          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR9          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR10         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR11         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR12         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR13         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR14         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR15         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_ADDR16         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_CLS            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_SPL            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_DCS            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_RAS            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_CAS            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_SDWE           JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_CKE            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_CKO            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_CS0            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_CS1            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_CS2            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_CS3            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_RD             JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_WR             JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_WE0            JZ_GPIO_FUNC1
+
+
+#define JZ_GPIO_MEM_ADDR21              JZ_GPIO_PORTB(17)
+#define JZ_GPIO_MEM_ADDR22              JZ_GPIO_PORTB(18)
+
+#define JZ_GPIO_FUNC_MEM_ADDR21         JZ_GPIO_FUNC2
+#define JZ_GPIO_FUNC_MEM_ADDR22         JZ_GPIO_FUNC2
+
+/* Port C function pins */
+#define JZ_GPIO_LCD_DATA0               JZ_GPIO_PORTC(0)
+#define JZ_GPIO_LCD_DATA1               JZ_GPIO_PORTC(1)
+#define JZ_GPIO_LCD_DATA2               JZ_GPIO_PORTC(2)
+#define JZ_GPIO_LCD_DATA3               JZ_GPIO_PORTC(3)
+#define JZ_GPIO_LCD_DATA4               JZ_GPIO_PORTC(4)
+#define JZ_GPIO_LCD_DATA5               JZ_GPIO_PORTC(5)
+#define JZ_GPIO_LCD_DATA6               JZ_GPIO_PORTC(6)
+#define JZ_GPIO_LCD_DATA7               JZ_GPIO_PORTC(7)
+#define JZ_GPIO_LCD_DATA8               JZ_GPIO_PORTC(8)
+#define JZ_GPIO_LCD_DATA9               JZ_GPIO_PORTC(9)
+#define JZ_GPIO_LCD_DATA10              JZ_GPIO_PORTC(10)
+#define JZ_GPIO_LCD_DATA11              JZ_GPIO_PORTC(11)
+#define JZ_GPIO_LCD_DATA12              JZ_GPIO_PORTC(12)
+#define JZ_GPIO_LCD_DATA13              JZ_GPIO_PORTC(13)
+#define JZ_GPIO_LCD_DATA14              JZ_GPIO_PORTC(14)
+#define JZ_GPIO_LCD_DATA15              JZ_GPIO_PORTC(15)
+#define JZ_GPIO_LCD_DATA16              JZ_GPIO_PORTC(16)
+#define JZ_GPIO_LCD_DATA17              JZ_GPIO_PORTC(17)
+#define JZ_GPIO_LCD_PCLK                JZ_GPIO_PORTC(18)
+#define JZ_GPIO_LCD_HSYNC               JZ_GPIO_PORTC(19)
+#define JZ_GPIO_LCD_VSYNC               JZ_GPIO_PORTC(20)
+#define JZ_GPIO_LCD_DE                  JZ_GPIO_PORTC(21)
+#define JZ_GPIO_LCD_PS                  JZ_GPIO_PORTC(22)
+#define JZ_GPIO_LCD_REV                 JZ_GPIO_PORTC(23)
+#define JZ_GPIO_MEM_WE1                 JZ_GPIO_PORTC(24)
+#define JZ_GPIO_MEM_WE2                 JZ_GPIO_PORTC(25)
+#define JZ_GPIO_MEM_WE3                 JZ_GPIO_PORTC(26)
+#define JZ_GPIO_MEM_WAIT                JZ_GPIO_PORTC(27)
+#define JZ_GPIO_MEM_FRE                 JZ_GPIO_PORTC(28)
+#define JZ_GPIO_MEM_FWE                 JZ_GPIO_PORTC(29)
+
+#define JZ_GPIO_FUNC_LCD_DATA0          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA1          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA2          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA3          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA4          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA5          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA6          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA7          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA8          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA9          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA10         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA11         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA12         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA13         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA14         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA15         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA16         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DATA17         JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_PCLK           JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_VSYNC          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_HSYNC          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_DE             JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_PS             JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_REV            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_WE1            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_WE2            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_WE3            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_WAIT           JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_FRE            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MEM_FWE            JZ_GPIO_FUNC1
+
+
+#define JZ_GPIO_MEM_ADDR19              JZ_GPIO_PORTB(22)
+#define JZ_GPIO_MEM_ADDR20              JZ_GPIO_PORTB(23)
+
+#define JZ_GPIO_FUNC_MEM_ADDR19         JZ_GPIO_FUNC2
+#define JZ_GPIO_FUNC_MEM_ADDR20         JZ_GPIO_FUNC2
+
+/* Port D function pins */
+#define JZ_GPIO_CIM_DATA0               JZ_GPIO_PORTD(0)
+#define JZ_GPIO_CIM_DATA1               JZ_GPIO_PORTD(1)
+#define JZ_GPIO_CIM_DATA2               JZ_GPIO_PORTD(2)
+#define JZ_GPIO_CIM_DATA3               JZ_GPIO_PORTD(3)
+#define JZ_GPIO_CIM_DATA4               JZ_GPIO_PORTD(4)
+#define JZ_GPIO_CIM_DATA5               JZ_GPIO_PORTD(5)
+#define JZ_GPIO_CIM_DATA6               JZ_GPIO_PORTD(6)
+#define JZ_GPIO_CIM_DATA7               JZ_GPIO_PORTD(7)
+#define JZ_GPIO_MSC_CMD                 JZ_GPIO_PORTD(8)
+#define JZ_GPIO_MSC_CLK                 JZ_GPIO_PORTD(9)
+#define JZ_GPIO_MSC_DATA0               JZ_GPIO_PORTD(10)
+#define JZ_GPIO_MSC_DATA1               JZ_GPIO_PORTD(11)
+#define JZ_GPIO_MSC_DATA2               JZ_GPIO_PORTD(12)
+#define JZ_GPIO_MSC_DATA3               JZ_GPIO_PORTD(13)
+#define JZ_GPIO_CIM_MCLK                JZ_GPIO_PORTD(14)
+#define JZ_GPIO_CIM_PCLK                JZ_GPIO_PORTD(15)
+#define JZ_GPIO_CIM_VSYNC               JZ_GPIO_PORTD(16)
+#define JZ_GPIO_CIM_HSYNC               JZ_GPIO_PORTD(17)
+#define JZ_GPIO_SPI_CLK                 JZ_GPIO_PORTD(18)
+#define JZ_GPIO_SPI_CE0                 JZ_GPIO_PORTD(19)
+#define JZ_GPIO_SPI_DT                  JZ_GPIO_PORTD(20)
+#define JZ_GPIO_SPI_DR                  JZ_GPIO_PORTD(21)
+#define JZ_GPIO_SPI_CE1                 JZ_GPIO_PORTD(22)
+#define JZ_GPIO_PWM0                    JZ_GPIO_PORTD(23)
+#define JZ_GPIO_PWM1                    JZ_GPIO_PORTD(24)
+#define JZ_GPIO_PWM2                    JZ_GPIO_PORTD(25)
+#define JZ_GPIO_PWM3                    JZ_GPIO_PORTD(26)
+#define JZ_GPIO_PWM4                    JZ_GPIO_PORTD(27)
+#define JZ_GPIO_PWM5                    JZ_GPIO_PORTD(28)
+#define JZ_GPIO_PWM6                    JZ_GPIO_PORTD(30)
+#define JZ_GPIO_PWM7                    JZ_GPIO_PORTD(31)
+
+#define JZ_GPIO_FUNC_CIM_DATA           JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_CIM_DATA0          JZ_GPIO_FUNC_CIM_DATA
+#define JZ_GPIO_FUNC_CIM_DATA1          JZ_GPIO_FUNC_CIM_DATA
+#define JZ_GPIO_FUNC_CIM_DATA2          JZ_GPIO_FUNC_CIM_DATA
+#define JZ_GPIO_FUNC_CIM_DATA3          JZ_GPIO_FUNC_CIM_DATA
+#define JZ_GPIO_FUNC_CIM_DATA4          JZ_GPIO_FUNC_CIM_DATA
+#define JZ_GPIO_FUNC_CIM_DATA5          JZ_GPIO_FUNC_CIM_DATA
+#define JZ_GPIO_FUNC_CIM_DATA6          JZ_GPIO_FUNC_CIM_DATA
+#define JZ_GPIO_FUNC_CIM_DATA7          JZ_GPIO_FUNC_CIM_DATA
+#define JZ_GPIO_FUNC_MSC_CMD            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MSC_CLK            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MSC_DATA           JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_MSC_DATA0          JZ_GPIO_FUNC_MSC_DATA
+#define JZ_GPIO_FUNC_MSC_DATA1          JZ_GPIO_FUNC_MSC_DATA
+#define JZ_GPIO_FUNC_MSC_DATA2          JZ_GPIO_FUNC_MSC_DATA
+#define JZ_GPIO_FUNC_MSC_DATA3          JZ_GPIO_FUNC_MSC_DATA
+#define JZ_GPIO_FUNC_CIM_MCLK           JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_CIM_PCLK           JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_CIM_VSYNC          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_CIM_HSYNC          JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_SPI_CLK            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_SPI_CE0            JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_SPI_DT             JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_SPI_DR             JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_SPI_CE1            JZ_GPIO_FUNC1
+
+#define JZ_GPIO_FUNC_PWM                JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_PWM0               JZ_GPIO_FUNC_PWM
+#define JZ_GPIO_FUNC_PWM1               JZ_GPIO_FUNC_PWM
+#define JZ_GPIO_FUNC_PWM2               JZ_GPIO_FUNC_PWM
+#define JZ_GPIO_FUNC_PWM3               JZ_GPIO_FUNC_PWM
+#define JZ_GPIO_FUNC_PWM4               JZ_GPIO_FUNC_PWM
+#define JZ_GPIO_FUNC_PWM5               JZ_GPIO_FUNC_PWM
+#define JZ_GPIO_FUNC_PWM6               JZ_GPIO_FUNC_PWM
+#define JZ_GPIO_FUNC_PWM7               JZ_GPIO_FUNC_PWM
+
+#define JZ_GPIO_MEM_SCLK_RSTN           JZ_GPIO_PORTD(18)
+#define JZ_GPIO_MEM_BCLK                JZ_GPIO_PORTD(19)
+#define JZ_GPIO_MEM_SDATO               JZ_GPIO_PORTD(20)
+#define JZ_GPIO_MEM_SDATI               JZ_GPIO_PORTD(21)
+#define JZ_GPIO_MEM_SYNC                JZ_GPIO_PORTD(22)
+#define JZ_GPIO_I2C_SDA                 JZ_GPIO_PORTD(23)
+#define JZ_GPIO_I2C_SCK                 JZ_GPIO_PORTD(24)
+#define JZ_GPIO_UART0_TXD               JZ_GPIO_PORTD(25)
+#define JZ_GPIO_UART0_RXD               JZ_GPIO_PORTD(26)
+#define JZ_GPIO_MEM_ADDR17              JZ_GPIO_PORTD(27)
+#define JZ_GPIO_MEM_ADDR18              JZ_GPIO_PORTD(28)
+#define JZ_GPIO_UART0_CTS               JZ_GPIO_PORTD(30)
+#define JZ_GPIO_UART0_RTS               JZ_GPIO_PORTD(31)
+
+#define JZ_GPIO_FUNC_MEM_SCLK_RSTN      JZ_GPIO_FUNC2
+#define JZ_GPIO_FUNC_MEM_BCLK           JZ_GPIO_FUNC2
+#define JZ_GPIO_FUNC_MEM_SDATO          JZ_GPIO_FUNC2
+#define JZ_GPIO_FUNC_MEM_SDATI          JZ_GPIO_FUNC2
+#define JZ_GPIO_FUNC_MEM_SYNC           JZ_GPIO_FUNC2
+#define JZ_GPIO_FUNC_I2C_SDA            JZ_GPIO_FUNC2
+#define JZ_GPIO_FUNC_I2C_SCK            JZ_GPIO_FUNC2
+#define JZ_GPIO_FUNC_UART0_TXD          JZ_GPIO_FUNC2
+#define JZ_GPIO_FUNC_UART0_RXD          JZ_GPIO_FUNC2
+#define JZ_GPIO_FUNC_MEM_ADDR17         JZ_GPIO_FUNC2
+#define JZ_GPIO_FUNC_MEM_ADDR18         JZ_GPIO_FUNC2
+#define JZ_GPIO_FUNC_UART0_CTS          JZ_GPIO_FUNC2
+#define JZ_GPIO_FUNC_UART0_RTS          JZ_GPIO_FUNC2
+
+#define JZ_GPIO_UART1_RXD               JZ_GPIO_PORTD(30)
+#define JZ_GPIO_UART1_TXD               JZ_GPIO_PORTD(31)
+
+#define JZ_GPIO_FUNC_UART1_RXD          JZ_GPIO_FUNC3
+#define JZ_GPIO_FUNC_UART1_TXD          JZ_GPIO_FUNC3
+
+#endif
diff --git a/arch/mips/include/asm/mach-jz4740/irq.h b/arch/mips/include/asm/mach-jz4740/irq.h
new file mode 100644
index 000000000000..a865c983c70a
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4740/irq.h
@@ -0,0 +1,57 @@
+/*
+ *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
+ *  JZ4740 IRQ definitions
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under  the terms of the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __ASM_MACH_JZ4740_IRQ_H__
+#define __ASM_MACH_JZ4740_IRQ_H__
+
+#define MIPS_CPU_IRQ_BASE 0
+#define JZ4740_IRQ_BASE 8
+
+/* 1st-level interrupts */
+#define JZ4740_IRQ(x)           (JZ4740_IRQ_BASE + (x))
+#define JZ4740_IRQ_I2C          JZ4740_IRQ(1)
+#define JZ4740_IRQ_UHC          JZ4740_IRQ(3)
+#define JZ4740_IRQ_UART1        JZ4740_IRQ(8)
+#define JZ4740_IRQ_UART0        JZ4740_IRQ(9)
+#define JZ4740_IRQ_SADC         JZ4740_IRQ(12)
+#define JZ4740_IRQ_MSC          JZ4740_IRQ(14)
+#define JZ4740_IRQ_RTC          JZ4740_IRQ(15)
+#define JZ4740_IRQ_SSI          JZ4740_IRQ(16)
+#define JZ4740_IRQ_CIM          JZ4740_IRQ(17)
+#define JZ4740_IRQ_AIC          JZ4740_IRQ(18)
+#define JZ4740_IRQ_ETH          JZ4740_IRQ(19)
+#define JZ4740_IRQ_DMAC         JZ4740_IRQ(20)
+#define JZ4740_IRQ_TCU2         JZ4740_IRQ(21)
+#define JZ4740_IRQ_TCU1         JZ4740_IRQ(22)
+#define JZ4740_IRQ_TCU0         JZ4740_IRQ(23)
+#define JZ4740_IRQ_UDC          JZ4740_IRQ(24)
+#define JZ4740_IRQ_GPIO3        JZ4740_IRQ(25)
+#define JZ4740_IRQ_GPIO2        JZ4740_IRQ(26)
+#define JZ4740_IRQ_GPIO1        JZ4740_IRQ(27)
+#define JZ4740_IRQ_GPIO0        JZ4740_IRQ(28)
+#define JZ4740_IRQ_IPU          JZ4740_IRQ(29)
+#define JZ4740_IRQ_LCD          JZ4740_IRQ(30)
+
+/* 2nd-level interrupts */
+#define JZ4740_IRQ_DMA(x)       (JZ4740_IRQ(32) + (X))
+
+#define JZ4740_IRQ_INTC_GPIO(x) (JZ4740_IRQ_GPIO0 - (x))
+#define JZ4740_IRQ_GPIO(x)      (JZ4740_IRQ(48) + (x))
+
+#define JZ4740_IRQ_ADC_BASE     JZ4740_IRQ(176)
+
+#define NR_IRQS (JZ4740_IRQ_ADC_BASE + 6)
+
+#endif
diff --git a/arch/mips/include/asm/mach-jz4740/jz4740_fb.h b/arch/mips/include/asm/mach-jz4740/jz4740_fb.h
new file mode 100644
index 000000000000..6a50e6f7a21a
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4740/jz4740_fb.h
@@ -0,0 +1,67 @@
+/*
+ *  Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __ASM_MACH_JZ4740_JZ4740_FB_H__
+#define __ASM_MACH_JZ4740_JZ4740_FB_H__
+
+#include <linux/fb.h>
+
+enum jz4740_fb_lcd_type {
+        JZ_LCD_TYPE_GENERIC_16_BIT = 0,
+        JZ_LCD_TYPE_GENERIC_18_BIT = 0 | (1 << 4),
+        JZ_LCD_TYPE_SPECIAL_TFT_1 = 1,
+        JZ_LCD_TYPE_SPECIAL_TFT_2 = 2,
+        JZ_LCD_TYPE_SPECIAL_TFT_3 = 3,
+        JZ_LCD_TYPE_NON_INTERLACED_CCIR656 = 5,
+        JZ_LCD_TYPE_INTERLACED_CCIR656 = 7,
+        JZ_LCD_TYPE_SINGLE_COLOR_STN = 8,
+        JZ_LCD_TYPE_SINGLE_MONOCHROME_STN = 9,
+        JZ_LCD_TYPE_DUAL_COLOR_STN = 10,
+        JZ_LCD_TYPE_DUAL_MONOCHROME_STN = 11,
+        JZ_LCD_TYPE_8BIT_SERIAL = 12,
+};
+
+#define JZ4740_FB_SPECIAL_TFT_CONFIG(start, stop) (((start) << 16) | (stop))
+
+/*
+* width: width of the lcd display in mm
+* height: height of the lcd display in mm
+* num_modes: size of modes
+* modes: list of valid video modes
+* bpp: bits per pixel for the lcd
+* lcd_type: lcd type
+*/
+
+struct jz4740_fb_platform_data {
+        unsigned int width;
+        unsigned int height;
+
+        size_t num_modes;
+        struct fb_videomode *modes;
+
+        unsigned int bpp;
+        enum jz4740_fb_lcd_type lcd_type;
+
+        struct {
+                uint32_t spl;
+                uint32_t cls;
+                uint32_t ps;
+                uint32_t rev;
+        } special_tft_config;
+
+        unsigned pixclk_falling_edge:1;
+        unsigned date_enable_active_low:1;
+};
+
+#endif
diff --git a/arch/mips/include/asm/mach-jz4740/jz4740_mmc.h b/arch/mips/include/asm/mach-jz4740/jz4740_mmc.h
new file mode 100644
index 000000000000..8543f432b4b3
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4740/jz4740_mmc.h
@@ -0,0 +1,15 @@
+#ifndef __LINUX_MMC_JZ4740_MMC
+#define __LINUX_MMC_JZ4740_MMC
+
+struct jz4740_mmc_platform_data {
+        int gpio_power;
+        int gpio_card_detect;
+        int gpio_read_only;
+        unsigned card_detect_active_low:1;
+        unsigned read_only_active_low:1;
+        unsigned power_active_low:1;
+
+        unsigned data_1bit:1;
+};
+
+#endif
diff --git a/arch/mips/include/asm/mach-jz4740/jz4740_nand.h b/arch/mips/include/asm/mach-jz4740/jz4740_nand.h
new file mode 100644
index 000000000000..bb5b9a4e29c8
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4740/jz4740_nand.h
@@ -0,0 +1,34 @@
+/*
+ *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
+ *  JZ4740 SoC NAND controller driver
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __ASM_MACH_JZ4740_JZ4740_NAND_H__
+#define __ASM_MACH_JZ4740_JZ4740_NAND_H__
+
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
+
+struct jz_nand_platform_data {
+        int                     num_partitions;
+        struct mtd_partition    *partitions;
+
+        struct nand_ecclayout   *ecc_layout;
+
+        unsigned int busy_gpio;
+
+        void (*ident_callback)(struct platform_device *, struct nand_chip *,
+                                struct mtd_partition **, int *num_partitions);
+};
+
+#endif
diff --git a/arch/mips/include/asm/mach-jz4740/platform.h b/arch/mips/include/asm/mach-jz4740/platform.h
new file mode 100644
index 000000000000..8987a76e9676
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4740/platform.h
@@ -0,0 +1,36 @@
+/*
+ *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
+ *  JZ4740 platform device definitions
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under  the terms of the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+
+#ifndef __JZ4740_PLATFORM_H
+#define __JZ4740_PLATFORM_H
+
+#include <linux/platform_device.h>
+
+extern struct platform_device jz4740_usb_ohci_device;
+extern struct platform_device jz4740_udc_device;
+extern struct platform_device jz4740_mmc_device;
+extern struct platform_device jz4740_rtc_device;
+extern struct platform_device jz4740_i2c_device;
+extern struct platform_device jz4740_nand_device;
+extern struct platform_device jz4740_framebuffer_device;
+extern struct platform_device jz4740_i2s_device;
+extern struct platform_device jz4740_pcm_device;
+extern struct platform_device jz4740_codec_device;
+extern struct platform_device jz4740_adc_device;
+
+void jz4740_serial_device_register(void);
+
+#endif
diff --git a/arch/mips/include/asm/mach-jz4740/timer.h b/arch/mips/include/asm/mach-jz4740/timer.h
new file mode 100644
index 000000000000..9baa03ce748c
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4740/timer.h
@@ -0,0 +1,22 @@
+/*
+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ *  JZ4740 platform timer support
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under  the terms of the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __ASM_MACH_JZ4740_TIMER
+#define __ASM_MACH_JZ4740_TIMER
+
+void jz4740_timer_enable_watchdog(void);
+void jz4740_timer_disable_watchdog(void);
+
+#endif
diff --git a/arch/mips/include/asm/mach-jz4740/war.h b/arch/mips/include/asm/mach-jz4740/war.h
new file mode 100644
index 000000000000..3a5bc17e28fe
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4740/war.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MIPS_MACH_JZ4740_WAR_H
+#define __ASM_MIPS_MACH_JZ4740_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR     0
+#define R4600_V1_HIT_CACHEOP_WAR        0
+#define R4600_V2_HIT_CACHEOP_WAR        0
+#define R5432_CP0_INTERRUPT_WAR         0
+#define BCM1250_M3_WAR                  0
+#define SIBYTE_1956_WAR                 0
+#define MIPS4K_ICACHE_REFILL_WAR        0
+#define MIPS_CACHE_SYNC_WAR             0
+#define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
+#define ICACHE_REFILLS_WORKAROUND_WAR   0
+#define R10000_LLSC_WAR                 0
+#define MIPS34K_MISSED_ITLB_WAR         0
+
+#endif /* __ASM_MIPS_MACH_JZ4740_WAR_H */
diff --git a/arch/mips/include/asm/mach-loongson/loongson.h b/arch/mips/include/asm/mach-loongson/loongson.h
index fcdbe3a4ce1f..cb6985f24303 100644
--- a/arch/mips/include/asm/mach-loongson/loongson.h
+++ b/arch/mips/include/asm/mach-loongson/loongson.h
@@ -45,7 +45,6 @@ static inline void prom_init_uart_base(void)
 /* irq operation functions */
 extern void bonito_irqdispatch(void);
 extern void __init bonito_irq_init(void);
-extern void __init set_irq_trigger_mode(void);
 extern void __init mach_init_irq(void);
 extern void mach_irq_dispatch(unsigned int pending);
 extern int mach_i8259_irq(void);
@@ -63,6 +62,14 @@ extern int mach_i8259_irq(void);
 #define LOONGSON_IRQ_BASE       32
 #define LOONGSON2_PERFCNT_IRQ   (MIPS_CPU_IRQ_BASE + 6) /* cpu perf counter */
 
+#include <linux/interrupt.h>
+static inline void do_perfcnt_IRQ(void)
+{
+#if defined(CONFIG_OPROFILE) || defined(CONFIG_OPROFILE_MODULE)
+        do_IRQ(LOONGSON2_PERFCNT_IRQ);
+#endif
+}
+
 #define LOONGSON_FLASH_BASE     0x1c000000
 #define LOONGSON_FLASH_SIZE     0x02000000      /* 32M */
 #define LOONGSON_FLASH_TOP      (LOONGSON_FLASH_BASE+LOONGSON_FLASH_SIZE-1)
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1550.h b/arch/mips/include/asm/mach-pb1x00/pb1550.h
index 58796410bd6e..fc4d766641ce 100644
--- a/arch/mips/include/asm/mach-pb1x00/pb1550.h
+++ b/arch/mips/include/asm/mach-pb1x00/pb1550.h
@@ -40,14 +40,6 @@
 #define SMBUS_PSC_BASE          PSC2_BASE_ADDR
 #define I2S_PSC_BASE            PSC3_BASE_ADDR
 
-#if defined(CONFIG_MTD_PB1550_BOOT) && defined(CONFIG_MTD_PB1550_USER)
-#define PB1550_BOTH_BANKS
-#elif defined(CONFIG_MTD_PB1550_BOOT) && !defined(CONFIG_MTD_PB1550_USER)
-#define PB1550_BOOT_ONLY
-#elif !defined(CONFIG_MTD_PB1550_BOOT) && defined(CONFIG_MTD_PB1550_USER)
-#define PB1550_USER_ONLY
-#endif
-
 /*
  * Timing values as described in databook, * ns value stripped of
  * lower 2 bits.
diff --git a/arch/mips/include/asm/mach-powertv/asic.h b/arch/mips/include/asm/mach-powertv/asic.h
index bcad43a93ebf..c7077a64b9a7 100644
--- a/arch/mips/include/asm/mach-powertv/asic.h
+++ b/arch/mips/include/asm/mach-powertv/asic.h
@@ -20,6 +20,7 @@
 #define _ASM_MACH_POWERTV_ASIC_H
 
 #include <linux/ioport.h>
+#include <linux/platform_device.h>
 #include <asm/mach-powertv/asic_regs.h>
 
 #define DVR_CAPABLE     (1<<0)
@@ -40,19 +41,23 @@ enum family_type {
         FAMILY_8600VZB,
         FAMILY_1500VZE,
         FAMILY_1500VZF,
+        FAMILY_8700,
         FAMILIES
 };
 
 /* Register maps for each ASIC */
 extern const struct register_map calliope_register_map;
 extern const struct register_map cronus_register_map;
+extern const struct register_map gaia_register_map;
 extern const struct register_map zeus_register_map;
 
 extern struct resource dvr_cronus_resources[];
+extern struct resource dvr_gaia_resources[];
 extern struct resource dvr_zeus_resources[];
 extern struct resource non_dvr_calliope_resources[];
 extern struct resource non_dvr_cronus_resources[];
 extern struct resource non_dvr_cronuslite_resources[];
+extern struct resource non_dvr_gaia_resources[];
 extern struct resource non_dvr_vz_calliope_resources[];
 extern struct resource non_dvr_vze_calliope_resources[];
 extern struct resource non_dvr_vzf_calliope_resources[];
@@ -67,16 +72,24 @@ extern int platform_supports_ffs(void);
 extern int platform_supports_pcie(void);
 extern int platform_supports_display(void);
 extern void configure_platform(void);
-extern void platform_configure_usb_ehci(void);
-extern void platform_unconfigure_usb_ehci(void);
-extern void platform_configure_usb_ohci(void);
-extern void platform_unconfigure_usb_ohci(void);
 
 /* Platform Resources */
 #define ASIC_RESOURCE_GET_EXISTS 1
 extern struct resource *asic_resource_get(const char *name);
 extern void platform_release_memory(void *baddr, int size);
 
+/* USB configuration */
+struct usb_hcd;                 /* Forward reference */
+extern void platform_configure_usb_ehci(void);
+extern void platform_unconfigure_usb_ehci(void);
+extern void platform_configure_usb_ohci(void);
+extern void platform_unconfigure_usb_ohci(void);
+
+/* Resource for ASIC registers */
+extern struct resource asic_resource;
+extern int platform_usb_devices_init(struct platform_device **echi_dev,
+        struct platform_device **ohci_dev);
+
 /* Reboot Cause */
 extern void set_reboot_cause(char code, unsigned int data, unsigned int data2);
 extern void set_locked_reboot_cause(char code, unsigned int data,
diff --git a/arch/mips/include/asm/mach-powertv/asic_reg_map.h b/arch/mips/include/asm/mach-powertv/asic_reg_map.h
index 6f26cb09828e..20348e817b09 100644
--- a/arch/mips/include/asm/mach-powertv/asic_reg_map.h
+++ b/arch/mips/include/asm/mach-powertv/asic_reg_map.h
@@ -64,7 +64,7 @@ REGISTER_MAP_ELEMENT(int_level_0_1)
 REGISTER_MAP_ELEMENT(int_level_0_0)
 REGISTER_MAP_ELEMENT(int_docsis_en)
 REGISTER_MAP_ELEMENT(mips_pll_setup)
-REGISTER_MAP_ELEMENT(usb_fs)
+REGISTER_MAP_ELEMENT(fs432x4b4_usb_ctl)
 REGISTER_MAP_ELEMENT(test_bus)
 REGISTER_MAP_ELEMENT(crt_spare)
 REGISTER_MAP_ELEMENT(usb2_ohci_int_mask)
diff --git a/arch/mips/include/asm/mach-powertv/asic_regs.h b/arch/mips/include/asm/mach-powertv/asic_regs.h
index 1e11236c6dbc..deecb26a077e 100644
--- a/arch/mips/include/asm/mach-powertv/asic_regs.h
+++ b/arch/mips/include/asm/mach-powertv/asic_regs.h
@@ -27,7 +27,8 @@ enum asic_type {
         ASIC_CALLIOPE,
         ASIC_CRONUS,
         ASIC_CRONUSLITE,
-        ASICS
+        ASIC_GAIA,
+        ASICS                   /* Number of supported ASICs */
 };
 
 /* hardcoded values read from Chip Version registers */
@@ -37,6 +38,7 @@ enum asic_type {
 
 #define NAND_FLASH_BASE         0x03000000
 #define CALLIOPE_IO_BASE        0x08000000
+#define GAIA_IO_BASE            0x09000000
 #define CRONUS_IO_BASE          0x09000000
 #define ZEUS_IO_BASE            0x09000000
 
@@ -99,6 +101,7 @@ static inline void register_map_virtualize(struct register_map *map)
 }
 
 extern struct register_map _asic_register_map;
+extern unsigned long asic_phy_base;
 
 /*
  * Macros to interface to registers through their ioremapped address
diff --git a/arch/mips/include/asm/mach-powertv/dma-coherence.h b/arch/mips/include/asm/mach-powertv/dma-coherence.h
index 5b8d5ebeb838..f76029c2406e 100644
--- a/arch/mips/include/asm/mach-powertv/dma-coherence.h
+++ b/arch/mips/include/asm/mach-powertv/dma-coherence.h
@@ -65,21 +65,21 @@ static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
         size_t size)
 {
         if (is_kseg2(addr))
-                return phys_to_bus(virt_to_phys_from_pte(addr));
+                return phys_to_dma(virt_to_phys_from_pte(addr));
         else
-                return phys_to_bus(virt_to_phys(addr));
+                return phys_to_dma(virt_to_phys(addr));
 }
 
 static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
         struct page *page)
 {
-        return phys_to_bus(page_to_phys(page));
+        return phys_to_dma(page_to_phys(page));
 }
 
 static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
         dma_addr_t dma_addr)
 {
-        return bus_to_phys(dma_addr);
+        return dma_to_phys(dma_addr);
 }
 
 static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
diff --git a/arch/mips/include/asm/mach-powertv/ioremap.h b/arch/mips/include/asm/mach-powertv/ioremap.h
index e6276d5146e8..076f2eeaa575 100644
--- a/arch/mips/include/asm/mach-powertv/ioremap.h
+++ b/arch/mips/include/asm/mach-powertv/ioremap.h
@@ -10,64 +10,101 @@
 #define __ASM_MACH_POWERTV_IOREMAP_H
 
 #include <linux/types.h>
+#include <linux/log2.h>
+#include <linux/compiler.h>
 
-#define LOW_MEM_BOUNDARY_PHYS   0x20000000
-#define LOW_MEM_BOUNDARY_MASK   (~(LOW_MEM_BOUNDARY_PHYS - 1))
+#include <asm/pgtable-bits.h>
+#include <asm/addrspace.h>
+
+/* We're going to mess with bits, so get sizes */
+#define IOR_BPC                 8                       /* Bits per char */
+#define IOR_PHYS_BITS           (IOR_BPC * sizeof(phys_addr_t))
+#define IOR_DMA_BITS            (IOR_BPC * sizeof(dma_addr_t))
 
 /*
- * The bus addresses are different than the physical addresses that
- * the processor sees by an offset. This offset varies by ASIC
- * version. Define a variable to hold the offset and some macros to
- * make the conversion simpler. */
-extern unsigned long phys_to_bus_offset;
-
-#ifdef CONFIG_HIGHMEM
-#define MEM_GAP_PHYS            0x60000000
+ * Define the granularity of physical/DMA mapping in terms of the number
+ * of bits that defines the offset within a grain. These will be the
+ * least significant bits of the address. The rest of a physical or DMA
+ * address will be used to index into an appropriate table to find the
+ * offset to add to the address to yield the corresponding DMA or physical
+ * address, respectively.
+ */
+#define IOR_LSBITS              22                      /* Bits in a grain */
+
 /*
- * TODO: We will use the hard code for conversion between physical and
- * bus until the bootloader releases their device tree to us.
+ * Compute the number of most significant address bits after removing those
+ * used for the offset within a grain and then compute the number of table
+ * entries for the conversion.
  */
-#define phys_to_bus(x) (((x) < LOW_MEM_BOUNDARY_PHYS) ? \
-        ((x) + phys_to_bus_offset) : (x))
-#define bus_to_phys(x) (((x) < MEM_GAP_PHYS_ADDR) ? \
-        ((x) - phys_to_bus_offset) : (x))
-#else
-#define phys_to_bus(x) ((x) + phys_to_bus_offset)
-#define bus_to_phys(x) ((x) - phys_to_bus_offset)
-#endif
+#define IOR_PHYS_MSBITS         (IOR_PHYS_BITS - IOR_LSBITS)
+#define IOR_NUM_PHYS_TO_DMA     ((phys_addr_t) 1 << IOR_PHYS_MSBITS)
+
+#define IOR_DMA_MSBITS          (IOR_DMA_BITS - IOR_LSBITS)
+#define IOR_NUM_DMA_TO_PHYS     ((dma_addr_t) 1 << IOR_DMA_MSBITS)
 
 /*
- * Determine whether the address we are given is for an ASIC device
- * Params:  addr    Address to check
- * Returns: Zero if the address is not for ASIC devices, non-zero
- *      if it is.
+ * Define data structures used as elements in the arrays for the conversion
+ * between physical and DMA addresses. We do some slightly fancy math to
+ * compute the width of the offset element of the conversion tables so
+ * that we can have the smallest conversion tables. Next, round up the
+ * sizes to the next higher power of two, i.e. the offset element will have
+ * 8, 16, 32, 64, etc. bits. This eliminates the need to mask off any
+ * bits.  Finally, we compute a shift value that puts the most significant
+ * bits of the offset into the most significant bits of the offset element.
+ * This makes it more efficient on processors without barrel shifters and
+ * easier to see the values if the conversion table is dumped in binary.
  */
-static inline int asic_is_device_addr(phys_t addr)
+#define _IOR_OFFSET_WIDTH(n)    (1 << order_base_2(n))
+#define IOR_OFFSET_WIDTH(n) \
+        (_IOR_OFFSET_WIDTH(n) < 8 ? 8 : _IOR_OFFSET_WIDTH(n))
+
+#define IOR_PHYS_OFFSET_BITS    IOR_OFFSET_WIDTH(IOR_PHYS_MSBITS)
+#define IOR_PHYS_SHIFT          (IOR_PHYS_BITS - IOR_PHYS_OFFSET_BITS)
+
+#define IOR_DMA_OFFSET_BITS     IOR_OFFSET_WIDTH(IOR_DMA_MSBITS)
+#define IOR_DMA_SHIFT           (IOR_DMA_BITS - IOR_DMA_OFFSET_BITS)
+
+struct ior_phys_to_dma {
+        dma_addr_t offset:IOR_DMA_OFFSET_BITS __packed
+                __aligned((IOR_DMA_OFFSET_BITS / IOR_BPC));
+};
+
+struct ior_dma_to_phys {
+        dma_addr_t offset:IOR_PHYS_OFFSET_BITS __packed
+                __aligned((IOR_PHYS_OFFSET_BITS / IOR_BPC));
+};
+
+extern struct ior_phys_to_dma _ior_phys_to_dma[IOR_NUM_PHYS_TO_DMA];
+extern struct ior_dma_to_phys _ior_dma_to_phys[IOR_NUM_DMA_TO_PHYS];
+
+static inline dma_addr_t _phys_to_dma_offset_raw(phys_addr_t phys)
 {
-        return !((phys_t)addr & (phys_t) LOW_MEM_BOUNDARY_MASK);
+        return (dma_addr_t)_ior_phys_to_dma[phys >> IOR_LSBITS].offset;
 }
 
-/*
- * Determine whether the address we are given is external RAM mappable
- * into KSEG1.
- * Params:  addr    Address to check
- * Returns: Zero if the address is not for external RAM and
- */
-static inline int asic_is_lowmem_ram_addr(phys_t addr)
+static inline dma_addr_t _dma_to_phys_offset_raw(dma_addr_t dma)
 {
-        /*
-         * The RAM always starts at the following address in the processor's
-         * physical address space
-         */
-        static const phys_t phys_ram_base = 0x10000000;
-        phys_t bus_ram_base;
+        return (dma_addr_t)_ior_dma_to_phys[dma >> IOR_LSBITS].offset;
+}
 
-        bus_ram_base = phys_to_bus_offset + phys_ram_base;
+/* These are not portable and should not be used in drivers. Drivers should
+ * be using ioremap() and friends to map physical addreses to virtual
+ * addresses and dma_map*() and friends to map virtual addresses into DMA
+ * addresses and back.
+ */
+static inline dma_addr_t phys_to_dma(phys_addr_t phys)
+{
+        return phys + (_phys_to_dma_offset_raw(phys) << IOR_PHYS_SHIFT);
+}
 
-        return addr >= bus_ram_base &&
-                addr < (bus_ram_base + (LOW_MEM_BOUNDARY_PHYS - phys_ram_base));
+static inline phys_addr_t dma_to_phys(dma_addr_t dma)
+{
+        return dma + (_dma_to_phys_offset_raw(dma) << IOR_DMA_SHIFT);
 }
 
+extern void ioremap_add_map(dma_addr_t phys, phys_addr_t alias,
+        dma_addr_t size);
+
 /*
  * Allow physical addresses to be fixed up to help peripherals located
  * outside the low 32-bit range -- generic pass-through version.
@@ -77,10 +114,50 @@ static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
         return phys_addr;
 }
 
-static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size,
+/*
+ * Handle the special case of addresses the area aliased into the first
+ * 512 MiB of the processor's physical address space. These turn into either
+ * kseg0 or kseg1 addresses, depending on flags.
+ */
+static inline void __iomem *plat_ioremap(phys_t start, unsigned long size,
         unsigned long flags)
 {
-        return NULL;
+        phys_addr_t start_offset;
+        void __iomem *result = NULL;
+
+        /* Start by checking to see whether this is an aliased address */
+        start_offset = _dma_to_phys_offset_raw(start);
+
+        /*
+         * If:
+         * o    the memory is aliased into the first 512 MiB, and
+         * o    the start and end are in the same RAM bank, and
+         * o    we don't have a zero size or wrap around, and
+         * o    we are supposed to create an uncached mapping,
+         *      handle this is a kseg0 or kseg1 address
+         */
+        if (start_offset != 0) {
+                phys_addr_t last;
+                dma_addr_t dma_to_phys_offset;
+
+                last = start + size - 1;
+                dma_to_phys_offset =
+                        _dma_to_phys_offset_raw(last) << IOR_DMA_SHIFT;
+
+                if (dma_to_phys_offset == start_offset &&
+                        size != 0 && start <= last) {
+                        phys_t adjusted_start;
+                        adjusted_start = start + start_offset;
+                        if (flags == _CACHE_UNCACHED)
+                                result = (void __iomem *) (unsigned long)
+                                        CKSEG1ADDR(adjusted_start);
+                        else
+                                result = (void __iomem *) (unsigned long)
+                                        CKSEG0ADDR(adjusted_start);
+                }
+        }
+
+        return result;
 }
 
 static inline int plat_iounmap(const volatile void __iomem *addr)
diff --git a/arch/mips/include/asm/mach-tx49xx/kmalloc.h b/arch/mips/include/asm/mach-tx49xx/kmalloc.h
index 913ff196259d..b74caf65482b 100644
--- a/arch/mips/include/asm/mach-tx49xx/kmalloc.h
+++ b/arch/mips/include/asm/mach-tx49xx/kmalloc.h
@@ -1,8 +1,6 @@
 #ifndef __ASM_MACH_TX49XX_KMALLOC_H
 #define __ASM_MACH_TX49XX_KMALLOC_H
 
-/*
- * All happy, no need to define ARCH_KMALLOC_MINALIGN
- */
+#define ARCH_KMALLOC_MINALIGN   L1_CACHE_BYTES
 
 #endif /* __ASM_MACH_TX49XX_KMALLOC_H */
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index c6e3c93ce7c7..335474c155f6 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -408,6 +408,7 @@
 #define  STATUSB_IP15           7
 #define  STATUSF_IP15           (_ULCAST_(1) <<  7)
 #define ST0_CH                  0x00040000
+#define ST0_NMI                 0x00080000
 #define ST0_SR                  0x00100000
 #define ST0_TS                  0x00200000
 #define ST0_BEV                 0x00400000
diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h
index ca6214b5ccb9..917a6c413b1a 100644
--- a/arch/mips/include/asm/octeon/octeon.h
+++ b/arch/mips/include/asm/octeon/octeon.h
@@ -50,6 +50,7 @@ extern void octeon_crypto_disable(struct octeon_cop2_state *state,
 extern asmlinkage void octeon_cop2_restore(struct octeon_cop2_state *task);
 
 extern void octeon_init_cvmcount(void);
+extern void octeon_setup_delays(void);
 
 #define OCTEON_ARGV_MAX_ARGS    64
 #define OCTOEN_SERIAL_LEN       20
@@ -253,4 +254,6 @@ static inline uint32_t octeon_npi_read32(uint64_t address)
 
 extern struct cvmx_bootinfo *octeon_bootinfo;
 
+extern uint64_t octeon_bootloader_entry_addr;
+
 #endif /* __ASM_OCTEON_OCTEON_H */
diff --git a/arch/mips/include/asm/octeon/pci-octeon.h b/arch/mips/include/asm/octeon/pci-octeon.h
index 6ac5d3e3398e..ece78043acf6 100644
--- a/arch/mips/include/asm/octeon/pci-octeon.h
+++ b/arch/mips/include/asm/octeon/pci-octeon.h
@@ -15,6 +15,19 @@
 #define PCI_CONFIG_SPACE_DELAY 10000
 
 /*
+ * The physical memory base mapped by BAR1.  256MB at the end of the
+ * first 4GB.
+ */
+#define CVMX_PCIE_BAR1_PHYS_BASE ((1ull << 32) - (1ull << 28))
+#define CVMX_PCIE_BAR1_PHYS_SIZE (1ull << 28)
+
+/*
+ * The RC base of BAR1.  gen1 has a 39-bit BAR2, gen2 has 41-bit BAR2,
+ * place BAR1 so it is the same for both.
+ */
+#define CVMX_PCIE_BAR1_RC_BASE (1ull << 41)
+
+/*
  * pcibios_map_irq() is defined inside pci-octeon.c. All it does is
  * call the Octeon specific version pointed to by this variable. This
  * function needs to change for PCI or PCIe based hosts.
diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h
index 3beea1479b43..576397c69920 100644
--- a/arch/mips/include/asm/pci.h
+++ b/arch/mips/include/asm/pci.h
@@ -140,6 +140,11 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
         return channel ? 15 : 14;
 }
 
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+/* MSI arch hook for OCTEON */
+#define arch_setup_msi_irqs arch_setup_msi_irqs
+#endif
+
 extern int pci_probe_only;
 
 extern char * (*pcibios_plat_setup)(char *str);
diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_prom.h b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_prom.h
index 54ef1a96d7ce..786d82daf8d6 100644
--- a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_prom.h
+++ b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_prom.h
@@ -124,10 +124,6 @@ extern void prom_meminit(void);
 extern void prom_fixup_mem_map(unsigned long start_mem,
                                unsigned long end_mem);
 
-#ifdef CONFIG_MTD_PMC_MSP_RAMROOT
-extern bool get_ramroot(void **start, unsigned long *size);
-#endif
-
 extern int get_ethernet_addr(char *ethaddr_name, char *ethernet_addr);
 extern unsigned long get_deviceid(void);
 extern char identify_enet(unsigned long interface_num);
diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h
index 5d33b727acf5..0d629bb93cbe 100644
--- a/arch/mips/include/asm/processor.h
+++ b/arch/mips/include/asm/processor.h
@@ -34,6 +34,11 @@ extern void (*cpu_wait)(void);
 extern unsigned int vced_count, vcei_count;
 
 /*
+ * MIPS does have an arch_pick_mmap_layout()
+ */
+#define HAVE_ARCH_PICK_MMAP_LAYOUT 1
+
+/*
  * A special page (the vdso) is mapped into all processes at the very
  * top of the virtual memory space.
  */
@@ -52,6 +57,9 @@ extern unsigned int vced_count, vcei_count;
  * space during mmap's.
  */
 #define TASK_UNMAPPED_BASE      ((TASK_SIZE / 3) & ~(PAGE_SIZE))
+
+#define TASK_IS_32BIT_ADDR 1
+
 #endif
 
 #ifdef CONFIG_64BIT
@@ -77,6 +85,9 @@ extern unsigned int vced_count, vcei_count;
                 PAGE_ALIGN(TASK_SIZE32 / 3) : PAGE_ALIGN(TASK_SIZE / 3))
 #define TASK_SIZE_OF(tsk)                                               \
         (test_tsk_thread_flag(tsk, TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE)
+
+#define TASK_IS_32BIT_ADDR test_thread_flag(TIF_32BIT_ADDR)
+
 #endif
 
 #ifdef __KERNEL__
@@ -218,7 +229,6 @@ struct thread_struct {
         unsigned long cp0_badvaddr;     /* Last user fault */
         unsigned long cp0_baduaddr;     /* Last kernel fault accessing USEG */
         unsigned long error_code;
-        unsigned long trap_no;
         unsigned long irix_trampoline;  /* Wheee... */
         unsigned long irix_oldctx;
 #ifdef CONFIG_CPU_CAVIUM_OCTEON
@@ -290,7 +300,6 @@ struct thread_struct {
         .cp0_badvaddr           = 0,                            \
         .cp0_baduaddr           = 0,                            \
         .error_code             = 0,                            \
-        .trap_no                = 0,                            \
         .irix_trampoline        = 0,                            \
         .irix_oldctx            = 0,                            \
         /*                                                      \
diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h
index cdc6a46efd98..9f1b8dba2c81 100644
--- a/arch/mips/include/asm/ptrace.h
+++ b/arch/mips/include/asm/ptrace.h
@@ -137,6 +137,7 @@ extern int ptrace_set_watch_regs(struct task_struct *child,
  */
 #define user_mode(regs) (((regs)->cp0_status & KU_MASK) == KU_USER)
 
+#define regs_return_value(_regs) ((_regs)->regs[2])
 #define instruction_pointer(regs) ((regs)->cp0_epc)
 #define profile_pc(regs) instruction_pointer(regs)
 
diff --git a/arch/mips/include/asm/sn/agent.h b/arch/mips/include/asm/sn/agent.h
index ac4ea85c3a5c..dc81114d4742 100644
--- a/arch/mips/include/asm/sn/agent.h
+++ b/arch/mips/include/asm/sn/agent.h
@@ -11,7 +11,6 @@
 #ifndef _ASM_SGI_SN_AGENT_H
 #define _ASM_SGI_SN_AGENT_H
 
-#include <linux/topology.h>
 #include <asm/sn/addrs.h>
 #include <asm/sn/arch.h>
 
diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h
index 697e40c06497..892062d6d748 100644
--- a/arch/mips/include/asm/uasm.h
+++ b/arch/mips/include/asm/uasm.h
@@ -10,44 +10,55 @@
 
 #include <linux/types.h>
 
+#ifdef CONFIG_EXPORT_UASM
+#include <linux/module.h>
+#define __uasminit
+#define __uasminitdata
+#define UASM_EXPORT_SYMBOL(sym) EXPORT_SYMBOL(sym)
+#else
+#define __uasminit __cpuinit
+#define __uasminitdata __cpuinitdata
+#define UASM_EXPORT_SYMBOL(sym)
+#endif
+
 #define Ip_u1u2u3(op)                                                   \
-void __cpuinit                                                          \
+void __uasminit                                                         \
 uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
 
 #define Ip_u2u1u3(op)                                                   \
-void __cpuinit                                                          \
+void __uasminit                                                         \
 uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
 
 #define Ip_u3u1u2(op)                                                   \
-void __cpuinit                                                          \
+void __uasminit                                                         \
 uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
 
 #define Ip_u1u2s3(op)                                                   \
-void __cpuinit                                                          \
+void __uasminit                                                         \
 uasm_i##op(u32 **buf, unsigned int a, unsigned int b, signed int c)
 
 #define Ip_u2s3u1(op)                                                   \
-void __cpuinit                                                          \
+void __uasminit                                                         \
 uasm_i##op(u32 **buf, unsigned int a, signed int b, unsigned int c)
 
 #define Ip_u2u1s3(op)                                                   \
-void __cpuinit                                                          \
+void __uasminit                                                         \
 uasm_i##op(u32 **buf, unsigned int a, unsigned int b, signed int c)
 
 #define Ip_u2u1msbu3(op)                                                \
-void __cpuinit                                                          \
+void __uasminit                                                         \
 uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c,   \
            unsigned int d)
 
 #define Ip_u1u2(op)                                                     \
-void __cpuinit uasm_i##op(u32 **buf, unsigned int a, unsigned int b)
+void __uasminit uasm_i##op(u32 **buf, unsigned int a, unsigned int b)
 
 #define Ip_u1s2(op)                                                     \
-void __cpuinit uasm_i##op(u32 **buf, unsigned int a, signed int b)
+void __uasminit uasm_i##op(u32 **buf, unsigned int a, signed int b)
 
-#define Ip_u1(op) void __cpuinit uasm_i##op(u32 **buf, unsigned int a)
+#define Ip_u1(op) void __uasminit uasm_i##op(u32 **buf, unsigned int a)
 
-#define Ip_0(op) void __cpuinit uasm_i##op(u32 **buf)
+#define Ip_0(op) void __uasminit uasm_i##op(u32 **buf)
 
 Ip_u2u1s3(_addiu);
 Ip_u3u1u2(_addu);
@@ -71,6 +82,7 @@ Ip_u2u1u3(_dsra);
 Ip_u2u1u3(_dsrl);
 Ip_u2u1u3(_dsrl32);
 Ip_u2u1u3(_drotr);
+Ip_u2u1u3(_drotr32);
 Ip_u3u1u2(_dsubu);
 Ip_0(_eret);
 Ip_u1(_j);
@@ -111,7 +123,7 @@ struct uasm_label {
         int lab;
 };
 
-void __cpuinit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid);
+void __uasminit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid);
 #ifdef CONFIG_64BIT
 int uasm_in_compat_space_p(long addr);
 #endif
@@ -121,7 +133,7 @@ void UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr);
 void UASM_i_LA(u32 **buf, unsigned int rs, long addr);
 
 #define UASM_L_LA(lb)                                                   \
-static inline void __cpuinit uasm_l##lb(struct uasm_label **lab, u32 *addr) \
+static inline void __uasminit uasm_l##lb(struct uasm_label **lab, u32 *addr) \
 {                                                                       \
         uasm_build_label(lab, addr, label##lb);                         \
 }
@@ -176,6 +188,15 @@ static inline void uasm_i_dsrl_safe(u32 **p, unsigned int a1,
                 uasm_i_dsrl32(p, a1, a2, a3 - 32);
 }
 
+static inline void uasm_i_drotr_safe(u32 **p, unsigned int a1,
+                                     unsigned int a2, unsigned int a3)
+{
+        if (a3 < 32)
+                uasm_i_drotr(p, a1, a2, a3);
+        else
+                uasm_i_drotr32(p, a1, a2, a3 - 32);
+}
+
 static inline void uasm_i_dsll_safe(u32 **p, unsigned int a1,
                                     unsigned int a2, unsigned int a3)
 {
@@ -213,3 +234,7 @@ void uasm_il_bne(u32 **p, struct uasm_reloc **r, unsigned int reg1,
 void uasm_il_bnez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
 void uasm_il_bgezl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
 void uasm_il_bgez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
+void uasm_il_bbit0(u32 **p, struct uasm_reloc **r, unsigned int reg,
+                   unsigned int bit, int lid);
+void uasm_il_bbit1(u32 **p, struct uasm_reloc **r, unsigned int reg,
+                   unsigned int bit, int lid);
diff --git a/arch/mips/jazz/Makefile b/arch/mips/jazz/Makefile
index 5aee0c266d18..dd9d99bfcf7a 100644
--- a/arch/mips/jazz/Makefile
+++ b/arch/mips/jazz/Makefile
@@ -3,5 +3,3 @@
 #
 
 obj-y           := irq.o jazzdma.o reset.o setup.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/jazz/Platform b/arch/mips/jazz/Platform
new file mode 100644
index 000000000000..3373788acca1
--- /dev/null
+++ b/arch/mips/jazz/Platform
@@ -0,0 +1,6 @@
+#
+# Acer PICA 61, Mips Magnum 4000 and Olivetti M700.
+#
+platform-$(CONFIG_MACH_JAZZ)    += jazz/
+cflags-$(CONFIG_MACH_JAZZ)      += -I$(srctree)/arch/mips/include/asm/mach-jazz
+load-$(CONFIG_MACH_JAZZ)        += 0xffffffff80080000
diff --git a/arch/mips/jz4740/Kconfig b/arch/mips/jz4740/Kconfig
new file mode 100644
index 000000000000..3e7141f0746c
--- /dev/null
+++ b/arch/mips/jz4740/Kconfig
@@ -0,0 +1,12 @@
+choice
+        prompt "Machine type"
+        depends on MACH_JZ4740
+        default JZ4740_QI_LB60
+
+config JZ4740_QI_LB60
+        bool "Qi Hardware Ben NanoNote"
+
+endchoice
+
+config HAVE_PWM
+        bool
diff --git a/arch/mips/jz4740/Makefile b/arch/mips/jz4740/Makefile
new file mode 100644
index 000000000000..a604eaeb6c08
--- /dev/null
+++ b/arch/mips/jz4740/Makefile
@@ -0,0 +1,20 @@
+#
+# Makefile for the Ingenic JZ4740.
+#
+
+# Object file lists.
+
+obj-y += prom.o irq.o time.o reset.o setup.o dma.o \
+        gpio.o clock.o platform.o timer.o pwm.o serial.o
+
+obj-$(CONFIG_DEBUG_FS) += clock-debugfs.o
+
+# board specific support
+
+obj-$(CONFIG_JZ4740_QI_LB60)    += board-qi_lb60.o
+
+# PM support
+
+obj-$(CONFIG_PM) += pm.o
+
+EXTRA_CFLAGS += -Werror -Wall
diff --git a/arch/mips/jz4740/Platform b/arch/mips/jz4740/Platform
new file mode 100644
index 000000000000..6a97230e3d05
--- /dev/null
+++ b/arch/mips/jz4740/Platform
@@ -0,0 +1,3 @@
+core-$(CONFIG_MACH_JZ4740)      += arch/mips/jz4740/
+cflags-$(CONFIG_MACH_JZ4740)    += -I$(srctree)/arch/mips/include/asm/mach-jz4740
+load-$(CONFIG_MACH_JZ4740)      += 0xffffffff80010000
diff --git a/arch/mips/jz4740/board-qi_lb60.c b/arch/mips/jz4740/board-qi_lb60.c
new file mode 100644
index 000000000000..5742bb4d78f4
--- /dev/null
+++ b/arch/mips/jz4740/board-qi_lb60.c
@@ -0,0 +1,471 @@
+/*
+ * linux/arch/mips/jz4740/board-qi_lb60.c
+ *
+ * QI_LB60 board support
+ *
+ * Copyright (c) 2009 Qi Hardware inc.,
+ * Author: Xiangfu Liu <xiangfu@qi-hardware.com>
+ * Copyright 2010, Lars-Petrer Clausen <lars@metafoo.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 or later
+ * as published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/gpio.h>
+
+#include <linux/input.h>
+#include <linux/gpio_keys.h>
+#include <linux/input/matrix_keypad.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/spi_gpio.h>
+#include <linux/power_supply.h>
+#include <linux/power/jz4740-battery.h>
+
+#include <asm/mach-jz4740/jz4740_fb.h>
+#include <asm/mach-jz4740/jz4740_mmc.h>
+#include <asm/mach-jz4740/jz4740_nand.h>
+
+#include <linux/regulator/fixed.h>
+#include <linux/regulator/machine.h>
+
+#include <linux/leds_pwm.h>
+
+#include <asm/mach-jz4740/platform.h>
+
+#include "clock.h"
+
+static bool is_avt2;
+
+/* GPIOs */
+#define QI_LB60_GPIO_SD_CD              JZ_GPIO_PORTD(0)
+#define QI_LB60_GPIO_SD_VCC_EN_N        JZ_GPIO_PORTD(2)
+
+#define QI_LB60_GPIO_KEYOUT(x)          (JZ_GPIO_PORTC(10) + (x))
+#define QI_LB60_GPIO_KEYIN(x)           (JZ_GPIO_PORTD(18) + (x))
+#define QI_LB60_GPIO_KEYIN8             JZ_GPIO_PORTD(26)
+
+/* NAND */
+static struct nand_ecclayout qi_lb60_ecclayout_1gb = {
+/*      .eccbytes = 36,
+        .eccpos = {
+                6,  7,  8,  9,  10, 11, 12, 13,
+                14, 15, 16, 17, 18, 19, 20, 21,
+                22, 23, 24, 25, 26, 27, 28, 29,
+                30, 31, 32, 33, 34, 35, 36, 37,
+                38, 39, 40, 41
+        },*/
+        .oobfree = {
+                { .offset = 2, .length = 4 },
+                { .offset = 42, .length = 22 }
+        },
+};
+
+/* Early prototypes of the QI LB60 had only 1GB of NAND.
+ * In order to support these devices aswell the partition and ecc layout is
+ * initalized depending on the NAND size */
+static struct mtd_partition qi_lb60_partitions_1gb[] = {
+        {
+                .name = "NAND BOOT partition",
+                .offset = 0 * 0x100000,
+                .size = 4 * 0x100000,
+        },
+        {
+                .name = "NAND KERNEL partition",
+                .offset = 4 * 0x100000,
+                .size = 4 * 0x100000,
+        },
+        {
+                .name = "NAND ROOTFS partition",
+                .offset = 8 * 0x100000,
+                .size = (504 + 512) * 0x100000,
+        },
+};
+
+static struct nand_ecclayout qi_lb60_ecclayout_2gb = {
+/*      .eccbytes = 72,
+        .eccpos = {
+                12, 13, 14, 15, 16, 17, 18, 19,
+                20, 21, 22, 23, 24, 25, 26, 27,
+                28, 29, 30, 31, 32, 33, 34, 35,
+                36, 37, 38, 39, 40, 41, 42, 43,
+                44, 45, 46, 47, 48, 49, 50, 51,
+                52, 53, 54, 55, 56, 57, 58, 59,
+                60, 61, 62, 63, 64, 65, 66, 67,
+                68, 69, 70, 71, 72, 73, 74, 75,
+                76, 77, 78, 79, 80, 81, 82, 83
+        },*/
+        .oobfree = {
+                { .offset = 2, .length = 10 },
+                { .offset = 84, .length = 44 },
+        },
+};
+
+static struct mtd_partition qi_lb60_partitions_2gb[] = {
+        {
+                .name = "NAND BOOT partition",
+                .offset = 0 * 0x100000,
+                .size = 4 * 0x100000,
+        },
+        {
+                .name = "NAND KERNEL partition",
+                .offset = 4 * 0x100000,
+                .size = 4 * 0x100000,
+        },
+        {
+                .name = "NAND ROOTFS partition",
+                .offset = 8 * 0x100000,
+                .size = (504 + 512 + 1024) * 0x100000,
+        },
+};
+
+static void qi_lb60_nand_ident(struct platform_device *pdev,
+                struct nand_chip *chip, struct mtd_partition **partitions,
+                int *num_partitions)
+{
+        if (chip->page_shift == 12) {
+                chip->ecc.layout = &qi_lb60_ecclayout_2gb;
+                *partitions = qi_lb60_partitions_2gb;
+                *num_partitions = ARRAY_SIZE(qi_lb60_partitions_2gb);
+        } else {
+                chip->ecc.layout = &qi_lb60_ecclayout_1gb;
+                *partitions = qi_lb60_partitions_1gb;
+                *num_partitions = ARRAY_SIZE(qi_lb60_partitions_1gb);
+        }
+}
+
+static struct jz_nand_platform_data qi_lb60_nand_pdata = {
+        .ident_callback = qi_lb60_nand_ident,
+        .busy_gpio = 94,
+};
+
+/* Keyboard*/
+
+#define KEY_QI_QI       KEY_F13
+#define KEY_QI_UPRED    KEY_RIGHTALT
+#define KEY_QI_VOLUP    KEY_VOLUMEUP
+#define KEY_QI_VOLDOWN  KEY_VOLUMEDOWN
+#define KEY_QI_FN       KEY_LEFTCTRL
+
+static const uint32_t qi_lb60_keymap[] = {
+        KEY(0, 0, KEY_F1),      /* S2 */
+        KEY(0, 1, KEY_F2),      /* S3 */
+        KEY(0, 2, KEY_F3),      /* S4 */
+        KEY(0, 3, KEY_F4),      /* S5 */
+        KEY(0, 4, KEY_F5),      /* S6 */
+        KEY(0, 5, KEY_F6),      /* S7 */
+        KEY(0, 6, KEY_F7),      /* S8 */
+
+        KEY(1, 0, KEY_Q),       /* S10 */
+        KEY(1, 1, KEY_W),       /* S11 */
+        KEY(1, 2, KEY_E),       /* S12 */
+        KEY(1, 3, KEY_R),       /* S13 */
+        KEY(1, 4, KEY_T),       /* S14 */
+        KEY(1, 5, KEY_Y),       /* S15 */
+        KEY(1, 6, KEY_U),       /* S16 */
+        KEY(1, 7, KEY_I),       /* S17 */
+        KEY(2, 0, KEY_A),       /* S18 */
+        KEY(2, 1, KEY_S),       /* S19 */
+        KEY(2, 2, KEY_D),       /* S20 */
+        KEY(2, 3, KEY_F),       /* S21 */
+        KEY(2, 4, KEY_G),       /* S22 */
+        KEY(2, 5, KEY_H),       /* S23 */
+        KEY(2, 6, KEY_J),       /* S24 */
+        KEY(2, 7, KEY_K),       /* S25 */
+        KEY(3, 0, KEY_ESC),     /* S26 */
+        KEY(3, 1, KEY_Z),       /* S27 */
+        KEY(3, 2, KEY_X),       /* S28 */
+        KEY(3, 3, KEY_C),       /* S29 */
+        KEY(3, 4, KEY_V),       /* S30 */
+        KEY(3, 5, KEY_B),       /* S31 */
+        KEY(3, 6, KEY_N),       /* S32 */
+        KEY(3, 7, KEY_M),       /* S33 */
+        KEY(4, 0, KEY_TAB),     /* S34 */
+        KEY(4, 1, KEY_CAPSLOCK),        /* S35 */
+        KEY(4, 2, KEY_BACKSLASH),       /* S36 */
+        KEY(4, 3, KEY_APOSTROPHE),      /* S37 */
+        KEY(4, 4, KEY_COMMA),   /* S38 */
+        KEY(4, 5, KEY_DOT),     /* S39 */
+        KEY(4, 6, KEY_SLASH),   /* S40 */
+        KEY(4, 7, KEY_UP),      /* S41 */
+        KEY(5, 0, KEY_O),       /* S42 */
+        KEY(5, 1, KEY_L),       /* S43 */
+        KEY(5, 2, KEY_EQUAL),   /* S44 */
+        KEY(5, 3, KEY_QI_UPRED),        /* S45 */
+        KEY(5, 4, KEY_SPACE),   /* S46 */
+        KEY(5, 5, KEY_QI_QI),   /* S47 */
+        KEY(5, 6, KEY_RIGHTCTRL),       /* S48 */
+        KEY(5, 7, KEY_LEFT),    /* S49 */
+        KEY(6, 0, KEY_F8),      /* S50 */
+        KEY(6, 1, KEY_P),       /* S51 */
+        KEY(6, 2, KEY_BACKSPACE),/* S52 */
+        KEY(6, 3, KEY_ENTER),   /* S53 */
+        KEY(6, 4, KEY_QI_VOLUP),        /* S54 */
+        KEY(6, 5, KEY_QI_VOLDOWN),      /* S55 */
+        KEY(6, 6, KEY_DOWN),    /* S56 */
+        KEY(6, 7, KEY_RIGHT),   /* S57 */
+
+        KEY(7, 0, KEY_LEFTSHIFT),       /* S58 */
+        KEY(7, 1, KEY_LEFTALT), /* S59 */
+        KEY(7, 2, KEY_QI_FN),   /* S60 */
+};
+
+static const struct matrix_keymap_data qi_lb60_keymap_data = {
+        .keymap         = qi_lb60_keymap,
+        .keymap_size    = ARRAY_SIZE(qi_lb60_keymap),
+};
+
+static const unsigned int qi_lb60_keypad_cols[] = {
+        QI_LB60_GPIO_KEYOUT(0),
+        QI_LB60_GPIO_KEYOUT(1),
+        QI_LB60_GPIO_KEYOUT(2),
+        QI_LB60_GPIO_KEYOUT(3),
+        QI_LB60_GPIO_KEYOUT(4),
+        QI_LB60_GPIO_KEYOUT(5),
+        QI_LB60_GPIO_KEYOUT(6),
+        QI_LB60_GPIO_KEYOUT(7),
+};
+
+static const unsigned int qi_lb60_keypad_rows[] = {
+        QI_LB60_GPIO_KEYIN(0),
+        QI_LB60_GPIO_KEYIN(1),
+        QI_LB60_GPIO_KEYIN(2),
+        QI_LB60_GPIO_KEYIN(3),
+        QI_LB60_GPIO_KEYIN(4),
+        QI_LB60_GPIO_KEYIN(5),
+        QI_LB60_GPIO_KEYIN(7),
+        QI_LB60_GPIO_KEYIN8,
+};
+
+static struct matrix_keypad_platform_data qi_lb60_pdata = {
+        .keymap_data = &qi_lb60_keymap_data,
+        .col_gpios      = qi_lb60_keypad_cols,
+        .row_gpios      = qi_lb60_keypad_rows,
+        .num_col_gpios  = ARRAY_SIZE(qi_lb60_keypad_cols),
+        .num_row_gpios  = ARRAY_SIZE(qi_lb60_keypad_rows),
+        .col_scan_delay_us      = 10,
+        .debounce_ms            = 10,
+        .wakeup                 = 1,
+        .active_low             = 1,
+};
+
+static struct platform_device qi_lb60_keypad = {
+        .name           = "matrix-keypad",
+        .id             = -1,
+        .dev            = {
+                .platform_data = &qi_lb60_pdata,
+        },
+};
+
+/* Display */
+static struct fb_videomode qi_lb60_video_modes[] = {
+        {
+                .name = "320x240",
+                .xres = 320,
+                .yres = 240,
+                .refresh = 30,
+                .left_margin = 140,
+                .right_margin = 273,
+                .upper_margin = 20,
+                .lower_margin = 2,
+                .hsync_len = 1,
+                .vsync_len = 1,
+                .sync = 0,
+                .vmode = FB_VMODE_NONINTERLACED,
+        },
+};
+
+static struct jz4740_fb_platform_data qi_lb60_fb_pdata = {
+        .width          = 60,
+        .height         = 45,
+        .num_modes      = ARRAY_SIZE(qi_lb60_video_modes),
+        .modes          = qi_lb60_video_modes,
+        .bpp            = 24,
+        .lcd_type       = JZ_LCD_TYPE_8BIT_SERIAL,
+        .pixclk_falling_edge = 1,
+};
+
+struct spi_gpio_platform_data spigpio_platform_data = {
+        .sck = JZ_GPIO_PORTC(23),
+        .mosi = JZ_GPIO_PORTC(22),
+        .miso = -1,
+        .num_chipselect = 1,
+};
+
+static struct platform_device spigpio_device = {
+        .name = "spi_gpio",
+        .id   = 1,
+        .dev = {
+                .platform_data = &spigpio_platform_data,
+        },
+};
+
+static struct spi_board_info qi_lb60_spi_board_info[] = {
+        {
+                .modalias = "ili8960",
+                .controller_data = (void *)JZ_GPIO_PORTC(21),
+                .chip_select = 0,
+                .bus_num = 1,
+                .max_speed_hz = 30 * 1000,
+                .mode = SPI_3WIRE,
+        },
+};
+
+/* Battery */
+static struct jz_battery_platform_data qi_lb60_battery_pdata = {
+        .gpio_charge =  JZ_GPIO_PORTC(27),
+        .gpio_charge_active_low = 1,
+        .info = {
+                .name = "battery",
+                .technology = POWER_SUPPLY_TECHNOLOGY_LIPO,
+                .voltage_max_design = 4200000,
+                .voltage_min_design = 3600000,
+        },
+};
+
+/* GPIO Key: power */
+static struct gpio_keys_button qi_lb60_gpio_keys_buttons[] = {
+        [0] = {
+                .code           = KEY_POWER,
+                .gpio           = JZ_GPIO_PORTD(29),
+                .active_low     = 1,
+                .desc           = "Power",
+                .wakeup         = 1,
+        },
+};
+
+static struct gpio_keys_platform_data qi_lb60_gpio_keys_data = {
+        .nbuttons = ARRAY_SIZE(qi_lb60_gpio_keys_buttons),
+        .buttons = qi_lb60_gpio_keys_buttons,
+};
+
+static struct platform_device qi_lb60_gpio_keys = {
+        .name = "gpio-keys",
+        .id =   -1,
+        .dev = {
+                .platform_data = &qi_lb60_gpio_keys_data,
+        }
+};
+
+static struct jz4740_mmc_platform_data qi_lb60_mmc_pdata = {
+        .gpio_card_detect       = QI_LB60_GPIO_SD_CD,
+        .gpio_read_only         = -1,
+        .gpio_power             = QI_LB60_GPIO_SD_VCC_EN_N,
+        .power_active_low       = 1,
+};
+
+/* OHCI */
+static struct regulator_consumer_supply avt2_usb_regulator_consumer =
+        REGULATOR_SUPPLY("vbus", "jz4740-ohci");
+
+static struct regulator_init_data avt2_usb_regulator_init_data = {
+        .num_consumer_supplies = 1,
+        .consumer_supplies = &avt2_usb_regulator_consumer,
+        .constraints = {
+                .name = "USB power",
+                .min_uV = 5000000,
+                .max_uV = 5000000,
+                .valid_modes_mask = REGULATOR_MODE_NORMAL,
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+        },
+};
+
+static struct fixed_voltage_config avt2_usb_regulator_data = {
+        .supply_name = "USB power",
+        .microvolts = 5000000,
+        .gpio = JZ_GPIO_PORTB(17),
+        .init_data = &avt2_usb_regulator_init_data,
+};
+
+static struct platform_device avt2_usb_regulator_device = {
+        .name = "reg-fixed-voltage",
+        .id = -1,
+        .dev = {
+                .platform_data = &avt2_usb_regulator_data,
+        }
+};
+
+/* beeper */
+static struct platform_device qi_lb60_pwm_beeper = {
+        .name = "pwm-beeper",
+        .id = -1,
+        .dev = {
+                .platform_data = (void *)4,
+        },
+};
+
+static struct platform_device *jz_platform_devices[] __initdata = {
+        &jz4740_udc_device,
+        &jz4740_mmc_device,
+        &jz4740_nand_device,
+        &qi_lb60_keypad,
+        &spigpio_device,
+        &jz4740_framebuffer_device,
+        &jz4740_pcm_device,
+        &jz4740_i2s_device,
+        &jz4740_codec_device,
+        &jz4740_rtc_device,
+        &jz4740_adc_device,
+        &qi_lb60_gpio_keys,
+        &qi_lb60_pwm_beeper,
+};
+
+static void __init board_gpio_setup(void)
+{
+        /* We only need to enable/disable pullup here for pins used in generic
+         * drivers. Everything else is done by the drivers themselfs. */
+        jz_gpio_disable_pullup(QI_LB60_GPIO_SD_VCC_EN_N);
+        jz_gpio_disable_pullup(QI_LB60_GPIO_SD_CD);
+}
+
+static int __init qi_lb60_init_platform_devices(void)
+{
+        jz4740_framebuffer_device.dev.platform_data = &qi_lb60_fb_pdata;
+        jz4740_nand_device.dev.platform_data = &qi_lb60_nand_pdata;
+        jz4740_adc_device.dev.platform_data = &qi_lb60_battery_pdata;
+        jz4740_mmc_device.dev.platform_data = &qi_lb60_mmc_pdata;
+
+        jz4740_serial_device_register();
+
+        spi_register_board_info(qi_lb60_spi_board_info,
+                                ARRAY_SIZE(qi_lb60_spi_board_info));
+
+        if (is_avt2) {
+                platform_device_register(&avt2_usb_regulator_device);
+                platform_device_register(&jz4740_usb_ohci_device);
+        }
+
+        return platform_add_devices(jz_platform_devices,
+                                        ARRAY_SIZE(jz_platform_devices));
+
+}
+
+struct jz4740_clock_board_data jz4740_clock_bdata = {
+        .ext_rate = 12000000,
+        .rtc_rate = 32768,
+};
+
+static __init int board_avt2(char *str)
+{
+        qi_lb60_mmc_pdata.card_detect_active_low = 1;
+        is_avt2 = true;
+
+        return 1;
+}
+__setup("avt2", board_avt2);
+
+static int __init qi_lb60_board_setup(void)
+{
+        printk(KERN_INFO "Qi Hardware JZ4740 QI %s setup\n",
+                is_avt2 ? "AVT2" : "LB60");
+
+        board_gpio_setup();
+
+        if (qi_lb60_init_platform_devices())
+                panic("Failed to initalize platform devices\n");
+
+        return 0;
+}
+arch_initcall(qi_lb60_board_setup);
diff --git a/arch/mips/jz4740/clock-debugfs.c b/arch/mips/jz4740/clock-debugfs.c
new file mode 100644
index 000000000000..330a0f2bf17b
--- /dev/null
+++ b/arch/mips/jz4740/clock-debugfs.c
@@ -0,0 +1,109 @@
+/*
+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ *  JZ4740 SoC clock support debugfs entries
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under  the terms of the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+
+#include <linux/debugfs.h>
+#include <linux/uaccess.h>
+
+#include <asm/mach-jz4740/clock.h>
+#include "clock.h"
+
+static struct dentry *jz4740_clock_debugfs;
+
+static int jz4740_clock_debugfs_show_enabled(void *data, uint64_t *value)
+{
+        struct clk *clk = data;
+        *value = clk_is_enabled(clk);
+
+        return 0;
+}
+
+static int jz4740_clock_debugfs_set_enabled(void *data, uint64_t value)
+{
+        struct clk *clk = data;
+
+        if (value)
+                return clk_enable(clk);
+        else
+                clk_disable(clk);
+
+        return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(jz4740_clock_debugfs_ops_enabled,
+        jz4740_clock_debugfs_show_enabled,
+        jz4740_clock_debugfs_set_enabled,
+        "%llu\n");
+
+static int jz4740_clock_debugfs_show_rate(void *data, uint64_t *value)
+{
+        struct clk *clk = data;
+        *value = clk_get_rate(clk);
+
+        return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(jz4740_clock_debugfs_ops_rate,
+        jz4740_clock_debugfs_show_rate,
+        NULL,
+        "%llu\n");
+
+void jz4740_clock_debugfs_add_clk(struct clk *clk)
+{
+        if (!jz4740_clock_debugfs)
+                return;
+
+        clk->debugfs_entry = debugfs_create_dir(clk->name, jz4740_clock_debugfs);
+        debugfs_create_file("rate", S_IWUGO | S_IRUGO, clk->debugfs_entry, clk,
+                                &jz4740_clock_debugfs_ops_rate);
+        debugfs_create_file("enabled", S_IRUGO, clk->debugfs_entry, clk,
+                                &jz4740_clock_debugfs_ops_enabled);
+
+        if (clk->parent) {
+                char parent_path[100];
+                snprintf(parent_path, 100, "../%s", clk->parent->name);
+                clk->debugfs_parent_entry = debugfs_create_symlink("parent",
+                                                clk->debugfs_entry,
+                                                parent_path);
+        }
+}
+
+/* TODO: Locking */
+void jz4740_clock_debugfs_update_parent(struct clk *clk)
+{
+        if (clk->debugfs_parent_entry)
+                debugfs_remove(clk->debugfs_parent_entry);
+
+        if (clk->parent) {
+                char parent_path[100];
+                snprintf(parent_path, 100, "../%s", clk->parent->name);
+                clk->debugfs_parent_entry = debugfs_create_symlink("parent",
+                                                clk->debugfs_entry,
+                                                parent_path);
+        } else {
+                clk->debugfs_parent_entry = NULL;
+        }
+}
+
+void jz4740_clock_debugfs_init(void)
+{
+        jz4740_clock_debugfs = debugfs_create_dir("jz4740-clock", NULL);
+        if (IS_ERR(jz4740_clock_debugfs))
+                jz4740_clock_debugfs = NULL;
+}
diff --git a/arch/mips/jz4740/clock.c b/arch/mips/jz4740/clock.c
new file mode 100644
index 000000000000..118a8a5562dd
--- /dev/null
+++ b/arch/mips/jz4740/clock.c
@@ -0,0 +1,924 @@
+/*
+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ *  JZ4740 SoC clock support
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under  the terms of the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/clk.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/list.h>
+#include <linux/err.h>
+
+#include <asm/mach-jz4740/clock.h>
+#include <asm/mach-jz4740/base.h>
+
+#include "clock.h"
+
+#define JZ_REG_CLOCK_CTRL       0x00
+#define JZ_REG_CLOCK_LOW_POWER  0x04
+#define JZ_REG_CLOCK_PLL        0x10
+#define JZ_REG_CLOCK_GATE       0x20
+#define JZ_REG_CLOCK_SLEEP_CTRL 0x24
+#define JZ_REG_CLOCK_I2S        0x60
+#define JZ_REG_CLOCK_LCD        0x64
+#define JZ_REG_CLOCK_MMC        0x68
+#define JZ_REG_CLOCK_UHC        0x6C
+#define JZ_REG_CLOCK_SPI        0x74
+
+#define JZ_CLOCK_CTRL_I2S_SRC_PLL       BIT(31)
+#define JZ_CLOCK_CTRL_KO_ENABLE         BIT(30)
+#define JZ_CLOCK_CTRL_UDC_SRC_PLL       BIT(29)
+#define JZ_CLOCK_CTRL_UDIV_MASK         0x1f800000
+#define JZ_CLOCK_CTRL_CHANGE_ENABLE     BIT(22)
+#define JZ_CLOCK_CTRL_PLL_HALF          BIT(21)
+#define JZ_CLOCK_CTRL_LDIV_MASK         0x001f0000
+#define JZ_CLOCK_CTRL_UDIV_OFFSET       23
+#define JZ_CLOCK_CTRL_LDIV_OFFSET       16
+#define JZ_CLOCK_CTRL_MDIV_OFFSET       12
+#define JZ_CLOCK_CTRL_PDIV_OFFSET        8
+#define JZ_CLOCK_CTRL_HDIV_OFFSET        4
+#define JZ_CLOCK_CTRL_CDIV_OFFSET        0
+
+#define JZ_CLOCK_GATE_UART0     BIT(0)
+#define JZ_CLOCK_GATE_TCU       BIT(1)
+#define JZ_CLOCK_GATE_RTC       BIT(2)
+#define JZ_CLOCK_GATE_I2C       BIT(3)
+#define JZ_CLOCK_GATE_SPI       BIT(4)
+#define JZ_CLOCK_GATE_AIC       BIT(5)
+#define JZ_CLOCK_GATE_I2S       BIT(6)
+#define JZ_CLOCK_GATE_MMC       BIT(7)
+#define JZ_CLOCK_GATE_ADC       BIT(8)
+#define JZ_CLOCK_GATE_CIM       BIT(9)
+#define JZ_CLOCK_GATE_LCD       BIT(10)
+#define JZ_CLOCK_GATE_UDC       BIT(11)
+#define JZ_CLOCK_GATE_DMAC      BIT(12)
+#define JZ_CLOCK_GATE_IPU       BIT(13)
+#define JZ_CLOCK_GATE_UHC       BIT(14)
+#define JZ_CLOCK_GATE_UART1     BIT(15)
+
+#define JZ_CLOCK_I2S_DIV_MASK           0x01ff
+
+#define JZ_CLOCK_LCD_DIV_MASK           0x01ff
+
+#define JZ_CLOCK_MMC_DIV_MASK           0x001f
+
+#define JZ_CLOCK_UHC_DIV_MASK           0x000f
+
+#define JZ_CLOCK_SPI_SRC_PLL            BIT(31)
+#define JZ_CLOCK_SPI_DIV_MASK           0x000f
+
+#define JZ_CLOCK_PLL_M_MASK             0x01ff
+#define JZ_CLOCK_PLL_N_MASK             0x001f
+#define JZ_CLOCK_PLL_OD_MASK            0x0003
+#define JZ_CLOCK_PLL_STABLE             BIT(10)
+#define JZ_CLOCK_PLL_BYPASS             BIT(9)
+#define JZ_CLOCK_PLL_ENABLED            BIT(8)
+#define JZ_CLOCK_PLL_STABLIZE_MASK      0x000f
+#define JZ_CLOCK_PLL_M_OFFSET           23
+#define JZ_CLOCK_PLL_N_OFFSET           18
+#define JZ_CLOCK_PLL_OD_OFFSET          16
+
+#define JZ_CLOCK_LOW_POWER_MODE_DOZE BIT(2)
+#define JZ_CLOCK_LOW_POWER_MODE_SLEEP BIT(0)
+
+#define JZ_CLOCK_SLEEP_CTRL_SUSPEND_UHC BIT(7)
+#define JZ_CLOCK_SLEEP_CTRL_ENABLE_UDC BIT(6)
+
+static void __iomem *jz_clock_base;
+static spinlock_t jz_clock_lock;
+static LIST_HEAD(jz_clocks);
+
+struct main_clk {
+        struct clk clk;
+        uint32_t div_offset;
+};
+
+struct divided_clk {
+        struct clk clk;
+        uint32_t reg;
+        uint32_t mask;
+};
+
+struct static_clk {
+        struct clk clk;
+        unsigned long rate;
+};
+
+static uint32_t jz_clk_reg_read(int reg)
+{
+        return readl(jz_clock_base + reg);
+}
+
+static void jz_clk_reg_write_mask(int reg, uint32_t val, uint32_t mask)
+{
+        uint32_t val2;
+
+        spin_lock(&jz_clock_lock);
+        val2 = readl(jz_clock_base + reg);
+        val2 &= ~mask;
+        val2 |= val;
+        writel(val2, jz_clock_base + reg);
+        spin_unlock(&jz_clock_lock);
+}
+
+static void jz_clk_reg_set_bits(int reg, uint32_t mask)
+{
+        uint32_t val;
+
+        spin_lock(&jz_clock_lock);
+        val = readl(jz_clock_base + reg);
+        val |= mask;
+        writel(val, jz_clock_base + reg);
+        spin_unlock(&jz_clock_lock);
+}
+
+static void jz_clk_reg_clear_bits(int reg, uint32_t mask)
+{
+        uint32_t val;
+
+        spin_lock(&jz_clock_lock);
+        val = readl(jz_clock_base + reg);
+        val &= ~mask;
+        writel(val, jz_clock_base + reg);
+        spin_unlock(&jz_clock_lock);
+}
+
+static int jz_clk_enable_gating(struct clk *clk)
+{
+        if (clk->gate_bit == JZ4740_CLK_NOT_GATED)
+                return -EINVAL;
+
+        jz_clk_reg_clear_bits(JZ_REG_CLOCK_GATE, clk->gate_bit);
+        return 0;
+}
+
+static int jz_clk_disable_gating(struct clk *clk)
+{
+        if (clk->gate_bit == JZ4740_CLK_NOT_GATED)
+                return -EINVAL;
+
+        jz_clk_reg_set_bits(JZ_REG_CLOCK_GATE, clk->gate_bit);
+        return 0;
+}
+
+static int jz_clk_is_enabled_gating(struct clk *clk)
+{
+        if (clk->gate_bit == JZ4740_CLK_NOT_GATED)
+                return 1;
+
+        return !(jz_clk_reg_read(JZ_REG_CLOCK_GATE) & clk->gate_bit);
+}
+
+static unsigned long jz_clk_static_get_rate(struct clk *clk)
+{
+        return ((struct static_clk *)clk)->rate;
+}
+
+static int jz_clk_ko_enable(struct clk *clk)
+{
+        jz_clk_reg_set_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_KO_ENABLE);
+        return 0;
+}
+
+static int jz_clk_ko_disable(struct clk *clk)
+{
+        jz_clk_reg_clear_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_KO_ENABLE);
+        return 0;
+}
+
+static int jz_clk_ko_is_enabled(struct clk *clk)
+{
+        return !!(jz_clk_reg_read(JZ_REG_CLOCK_CTRL) & JZ_CLOCK_CTRL_KO_ENABLE);
+}
+
+static const int pllno[] = {1, 2, 2, 4};
+
+static unsigned long jz_clk_pll_get_rate(struct clk *clk)
+{
+        uint32_t val;
+        int m;
+        int n;
+        int od;
+
+        val = jz_clk_reg_read(JZ_REG_CLOCK_PLL);
+
+        if (val & JZ_CLOCK_PLL_BYPASS)
+                return clk_get_rate(clk->parent);
+
+        m = ((val >> 23) & 0x1ff) + 2;
+        n = ((val >> 18) & 0x1f) + 2;
+        od = (val >> 16) & 0x3;
+
+        return ((clk_get_rate(clk->parent) / n) * m) / pllno[od];
+}
+
+static unsigned long jz_clk_pll_half_get_rate(struct clk *clk)
+{
+        uint32_t reg;
+
+        reg = jz_clk_reg_read(JZ_REG_CLOCK_CTRL);
+        if (reg & JZ_CLOCK_CTRL_PLL_HALF)
+                return jz_clk_pll_get_rate(clk->parent);
+        return jz_clk_pll_get_rate(clk->parent) >> 1;
+}
+
+static const int jz_clk_main_divs[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
+
+static unsigned long jz_clk_main_round_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned long parent_rate = jz_clk_pll_get_rate(clk->parent);
+        int div;
+
+        div = parent_rate / rate;
+        if (div > 32)
+                return parent_rate / 32;
+        else if (div < 1)
+                return parent_rate;
+
+        div &= (0x3 << (ffs(div) - 1));
+
+        return parent_rate / div;
+}
+
+static unsigned long jz_clk_main_get_rate(struct clk *clk)
+{
+        struct main_clk *mclk = (struct main_clk *)clk;
+        uint32_t div;
+
+        div = jz_clk_reg_read(JZ_REG_CLOCK_CTRL);
+
+        div >>= mclk->div_offset;
+        div &= 0xf;
+
+        if (div >= ARRAY_SIZE(jz_clk_main_divs))
+                div = ARRAY_SIZE(jz_clk_main_divs) - 1;
+
+        return jz_clk_pll_get_rate(clk->parent) / jz_clk_main_divs[div];
+}
+
+static int jz_clk_main_set_rate(struct clk *clk, unsigned long rate)
+{
+        struct main_clk *mclk = (struct main_clk *)clk;
+        int i;
+        int div;
+        unsigned long parent_rate = jz_clk_pll_get_rate(clk->parent);
+
+        rate = jz_clk_main_round_rate(clk, rate);
+
+        div = parent_rate / rate;
+
+        i = (ffs(div) - 1) << 1;
+        if (i > 0 && !(div & BIT(i-1)))
+                i -= 1;
+
+        jz_clk_reg_write_mask(JZ_REG_CLOCK_CTRL, i << mclk->div_offset,
+                                0xf << mclk->div_offset);
+
+        return 0;
+}
+
+static struct clk_ops jz_clk_static_ops = {
+        .get_rate = jz_clk_static_get_rate,
+        .enable = jz_clk_enable_gating,
+        .disable = jz_clk_disable_gating,
+        .is_enabled = jz_clk_is_enabled_gating,
+};
+
+static struct static_clk jz_clk_ext = {
+        .clk = {
+                .name = "ext",
+                .gate_bit = JZ4740_CLK_NOT_GATED,
+                .ops = &jz_clk_static_ops,
+        },
+};
+
+static struct clk_ops jz_clk_pll_ops = {
+        .get_rate = jz_clk_pll_get_rate,
+};
+
+static struct clk jz_clk_pll = {
+        .name = "pll",
+        .parent = &jz_clk_ext.clk,
+        .ops = &jz_clk_pll_ops,
+};
+
+static struct clk_ops jz_clk_pll_half_ops = {
+        .get_rate = jz_clk_pll_half_get_rate,
+};
+
+static struct clk jz_clk_pll_half = {
+        .name = "pll half",
+        .parent = &jz_clk_pll,
+        .ops = &jz_clk_pll_half_ops,
+};
+
+static const struct clk_ops jz_clk_main_ops = {
+        .get_rate = jz_clk_main_get_rate,
+        .set_rate = jz_clk_main_set_rate,
+        .round_rate = jz_clk_main_round_rate,
+};
+
+static struct main_clk jz_clk_cpu = {
+        .clk = {
+                .name = "cclk",
+                .parent = &jz_clk_pll,
+                .ops = &jz_clk_main_ops,
+        },
+        .div_offset = JZ_CLOCK_CTRL_CDIV_OFFSET,
+};
+
+static struct main_clk jz_clk_memory = {
+        .clk = {
+                .name = "mclk",
+                .parent = &jz_clk_pll,
+                .ops = &jz_clk_main_ops,
+        },
+        .div_offset = JZ_CLOCK_CTRL_MDIV_OFFSET,
+};
+
+static struct main_clk jz_clk_high_speed_peripheral = {
+        .clk = {
+                .name = "hclk",
+                .parent = &jz_clk_pll,
+                .ops = &jz_clk_main_ops,
+        },
+        .div_offset = JZ_CLOCK_CTRL_HDIV_OFFSET,
+};
+
+
+static struct main_clk jz_clk_low_speed_peripheral = {
+        .clk = {
+                .name = "pclk",
+                .parent = &jz_clk_pll,
+                .ops = &jz_clk_main_ops,
+        },
+        .div_offset = JZ_CLOCK_CTRL_PDIV_OFFSET,
+};
+
+static const struct clk_ops jz_clk_ko_ops = {
+        .enable = jz_clk_ko_enable,
+        .disable = jz_clk_ko_disable,
+        .is_enabled = jz_clk_ko_is_enabled,
+};
+
+static struct clk jz_clk_ko = {
+        .name = "cko",
+        .parent = &jz_clk_memory.clk,
+        .ops = &jz_clk_ko_ops,
+};
+
+static int jz_clk_spi_set_parent(struct clk *clk, struct clk *parent)
+{
+        if (parent == &jz_clk_pll)
+                jz_clk_reg_set_bits(JZ_CLOCK_SPI_SRC_PLL, JZ_REG_CLOCK_SPI);
+        else if (parent == &jz_clk_ext.clk)
+                jz_clk_reg_clear_bits(JZ_CLOCK_SPI_SRC_PLL, JZ_REG_CLOCK_SPI);
+        else
+                return -EINVAL;
+
+        clk->parent = parent;
+
+        return 0;
+}
+
+static int jz_clk_i2s_set_parent(struct clk *clk, struct clk *parent)
+{
+        if (parent == &jz_clk_pll_half)
+                jz_clk_reg_set_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_I2S_SRC_PLL);
+        else if (parent == &jz_clk_ext.clk)
+                jz_clk_reg_clear_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_I2S_SRC_PLL);
+        else
+                return -EINVAL;
+
+        clk->parent = parent;
+
+        return 0;
+}
+
+static int jz_clk_udc_enable(struct clk *clk)
+{
+        jz_clk_reg_set_bits(JZ_REG_CLOCK_SLEEP_CTRL,
+                        JZ_CLOCK_SLEEP_CTRL_ENABLE_UDC);
+
+        return 0;
+}
+
+static int jz_clk_udc_disable(struct clk *clk)
+{
+        jz_clk_reg_clear_bits(JZ_REG_CLOCK_SLEEP_CTRL,
+                        JZ_CLOCK_SLEEP_CTRL_ENABLE_UDC);
+
+        return 0;
+}
+
+static int jz_clk_udc_is_enabled(struct clk *clk)
+{
+        return !!(jz_clk_reg_read(JZ_REG_CLOCK_SLEEP_CTRL) &
+                        JZ_CLOCK_SLEEP_CTRL_ENABLE_UDC);
+}
+
+static int jz_clk_udc_set_parent(struct clk *clk, struct clk *parent)
+{
+        if (parent == &jz_clk_pll_half)
+                jz_clk_reg_set_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_UDC_SRC_PLL);
+        else if (parent == &jz_clk_ext.clk)
+                jz_clk_reg_clear_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_UDC_SRC_PLL);
+        else
+                return -EINVAL;
+
+        clk->parent = parent;
+
+        return 0;
+}
+
+static int jz_clk_udc_set_rate(struct clk *clk, unsigned long rate)
+{
+        int div;
+
+        if (clk->parent == &jz_clk_ext.clk)
+                return -EINVAL;
+
+        div = clk_get_rate(clk->parent) / rate - 1;
+
+        if (div < 0)
+                div = 0;
+        else if (div > 63)
+                div = 63;
+
+        jz_clk_reg_write_mask(JZ_REG_CLOCK_CTRL, div << JZ_CLOCK_CTRL_UDIV_OFFSET,
+                                JZ_CLOCK_CTRL_UDIV_MASK);
+        return 0;
+}
+
+static unsigned long jz_clk_udc_get_rate(struct clk *clk)
+{
+        int div;
+
+        if (clk->parent == &jz_clk_ext.clk)
+                return clk_get_rate(clk->parent);
+
+        div = (jz_clk_reg_read(JZ_REG_CLOCK_CTRL) & JZ_CLOCK_CTRL_UDIV_MASK);
+        div >>= JZ_CLOCK_CTRL_UDIV_OFFSET;
+        div += 1;
+
+        return clk_get_rate(clk->parent) / div;
+}
+
+static unsigned long jz_clk_divided_get_rate(struct clk *clk)
+{
+        struct divided_clk *dclk = (struct divided_clk *)clk;
+        int div;
+
+        if (clk->parent == &jz_clk_ext.clk)
+                return clk_get_rate(clk->parent);
+
+        div = (jz_clk_reg_read(dclk->reg) & dclk->mask) + 1;
+
+        return clk_get_rate(clk->parent) / div;
+}
+
+static int jz_clk_divided_set_rate(struct clk *clk, unsigned long rate)
+{
+        struct divided_clk *dclk = (struct divided_clk *)clk;
+        int div;
+
+        if (clk->parent == &jz_clk_ext.clk)
+                return -EINVAL;
+
+        div = clk_get_rate(clk->parent) / rate - 1;
+
+        if (div < 0)
+                div = 0;
+        else if (div > dclk->mask)
+                div = dclk->mask;
+
+        jz_clk_reg_write_mask(dclk->reg, div, dclk->mask);
+
+        return 0;
+}
+
+static unsigned long jz_clk_ldclk_round_rate(struct clk *clk, unsigned long rate)
+{
+        int div;
+        unsigned long parent_rate = jz_clk_pll_half_get_rate(clk->parent);
+
+        if (rate > 150000000)
+                return 150000000;
+
+        div = parent_rate / rate;
+        if (div < 1)
+                div = 1;
+        else if (div > 32)
+                div = 32;
+
+        return parent_rate / div;
+}
+
+static int jz_clk_ldclk_set_rate(struct clk *clk, unsigned long rate)
+{
+        int div;
+
+        if (rate > 150000000)
+                return -EINVAL;
+
+        div = jz_clk_pll_half_get_rate(clk->parent) / rate - 1;
+        if (div < 0)
+                div = 0;
+        else if (div > 31)
+                div = 31;
+
+        jz_clk_reg_write_mask(JZ_REG_CLOCK_CTRL, div << JZ_CLOCK_CTRL_LDIV_OFFSET,
+                                JZ_CLOCK_CTRL_LDIV_MASK);
+
+        return 0;
+}
+
+static unsigned long jz_clk_ldclk_get_rate(struct clk *clk)
+{
+        int div;
+
+        div = jz_clk_reg_read(JZ_REG_CLOCK_CTRL) & JZ_CLOCK_CTRL_LDIV_MASK;
+        div >>= JZ_CLOCK_CTRL_LDIV_OFFSET;
+
+        return jz_clk_pll_half_get_rate(clk->parent) / (div + 1);
+}
+
+static const struct clk_ops jz_clk_ops_ld = {
+        .set_rate = jz_clk_ldclk_set_rate,
+        .get_rate = jz_clk_ldclk_get_rate,
+        .round_rate = jz_clk_ldclk_round_rate,
+        .enable = jz_clk_enable_gating,
+        .disable = jz_clk_disable_gating,
+        .is_enabled = jz_clk_is_enabled_gating,
+};
+
+static struct clk jz_clk_ld = {
+        .name = "lcd",
+        .gate_bit = JZ_CLOCK_GATE_LCD,
+        .parent = &jz_clk_pll_half,
+        .ops = &jz_clk_ops_ld,
+};
+
+static const struct clk_ops jz_clk_i2s_ops = {
+        .set_rate = jz_clk_divided_set_rate,
+        .get_rate = jz_clk_divided_get_rate,
+        .enable = jz_clk_enable_gating,
+        .disable = jz_clk_disable_gating,
+        .is_enabled = jz_clk_is_enabled_gating,
+        .set_parent = jz_clk_i2s_set_parent,
+};
+
+static const struct clk_ops jz_clk_spi_ops = {
+        .set_rate = jz_clk_divided_set_rate,
+        .get_rate = jz_clk_divided_get_rate,
+        .enable = jz_clk_enable_gating,
+        .disable = jz_clk_disable_gating,
+        .is_enabled = jz_clk_is_enabled_gating,
+        .set_parent = jz_clk_spi_set_parent,
+};
+
+static const struct clk_ops jz_clk_divided_ops = {
+        .set_rate = jz_clk_divided_set_rate,
+        .get_rate = jz_clk_divided_get_rate,
+        .enable = jz_clk_enable_gating,
+        .disable = jz_clk_disable_gating,
+        .is_enabled = jz_clk_is_enabled_gating,
+};
+
+static struct divided_clk jz4740_clock_divided_clks[] = {
+        [0] = {
+                .clk = {
+                        .name = "i2s",
+                        .parent = &jz_clk_ext.clk,
+                        .gate_bit = JZ_CLOCK_GATE_I2S,
+                        .ops = &jz_clk_i2s_ops,
+                },
+                .reg = JZ_REG_CLOCK_I2S,
+                .mask = JZ_CLOCK_I2S_DIV_MASK,
+        },
+        [1] = {
+                .clk = {
+                        .name = "spi",
+                        .parent = &jz_clk_ext.clk,
+                        .gate_bit = JZ_CLOCK_GATE_SPI,
+                        .ops = &jz_clk_spi_ops,
+                },
+                .reg = JZ_REG_CLOCK_SPI,
+                .mask = JZ_CLOCK_SPI_DIV_MASK,
+        },
+        [2] = {
+                .clk = {
+                        .name = "lcd_pclk",
+                        .parent = &jz_clk_pll_half,
+                        .gate_bit = JZ4740_CLK_NOT_GATED,
+                        .ops = &jz_clk_divided_ops,
+                },
+                .reg = JZ_REG_CLOCK_LCD,
+                .mask = JZ_CLOCK_LCD_DIV_MASK,
+        },
+        [3] = {
+                .clk = {
+                        .name = "mmc",
+                        .parent = &jz_clk_pll_half,
+                        .gate_bit = JZ_CLOCK_GATE_MMC,
+                        .ops = &jz_clk_divided_ops,
+                },
+                .reg = JZ_REG_CLOCK_MMC,
+                .mask = JZ_CLOCK_MMC_DIV_MASK,
+        },
+        [4] = {
+                .clk = {
+                        .name = "uhc",
+                        .parent = &jz_clk_pll_half,
+                        .gate_bit = JZ_CLOCK_GATE_UHC,
+                        .ops = &jz_clk_divided_ops,
+                },
+                .reg = JZ_REG_CLOCK_UHC,
+                .mask = JZ_CLOCK_UHC_DIV_MASK,
+        },
+};
+
+static const struct clk_ops jz_clk_udc_ops = {
+        .set_parent = jz_clk_udc_set_parent,
+        .set_rate = jz_clk_udc_set_rate,
+        .get_rate = jz_clk_udc_get_rate,
+        .enable = jz_clk_udc_enable,
+        .disable = jz_clk_udc_disable,
+        .is_enabled = jz_clk_udc_is_enabled,
+};
+
+static const struct clk_ops jz_clk_simple_ops = {
+        .enable = jz_clk_enable_gating,
+        .disable = jz_clk_disable_gating,
+        .is_enabled = jz_clk_is_enabled_gating,
+};
+
+static struct clk jz4740_clock_simple_clks[] = {
+        [0] = {
+                .name = "udc",
+                .parent = &jz_clk_ext.clk,
+                .ops = &jz_clk_udc_ops,
+        },
+        [1] = {
+                .name = "uart0",
+                .parent = &jz_clk_ext.clk,
+                .gate_bit = JZ_CLOCK_GATE_UART0,
+                .ops = &jz_clk_simple_ops,
+        },
+        [2] = {
+                .name = "uart1",
+                .parent = &jz_clk_ext.clk,
+                .gate_bit = JZ_CLOCK_GATE_UART1,
+                .ops = &jz_clk_simple_ops,
+        },
+        [3] = {
+                .name = "dma",
+                .parent = &jz_clk_high_speed_peripheral.clk,
+                .gate_bit = JZ_CLOCK_GATE_UART0,
+                .ops = &jz_clk_simple_ops,
+        },
+        [4] = {
+                .name = "ipu",
+                .parent = &jz_clk_high_speed_peripheral.clk,
+                .gate_bit = JZ_CLOCK_GATE_IPU,
+                .ops = &jz_clk_simple_ops,
+        },
+        [5] = {
+                .name = "adc",
+                .parent = &jz_clk_ext.clk,
+                .gate_bit = JZ_CLOCK_GATE_ADC,
+                .ops = &jz_clk_simple_ops,
+        },
+        [6] = {
+                .name = "i2c",
+                .parent = &jz_clk_ext.clk,
+                .gate_bit = JZ_CLOCK_GATE_I2C,
+                .ops = &jz_clk_simple_ops,
+        },
+        [7] = {
+                .name = "aic",
+                .parent = &jz_clk_ext.clk,
+                .gate_bit = JZ_CLOCK_GATE_AIC,
+                .ops = &jz_clk_simple_ops,
+        },
+};
+
+static struct static_clk jz_clk_rtc = {
+        .clk = {
+                .name = "rtc",
+                .gate_bit = JZ_CLOCK_GATE_RTC,
+                .ops = &jz_clk_static_ops,
+        },
+        .rate = 32768,
+};
+
+int clk_enable(struct clk *clk)
+{
+        if (!clk->ops->enable)
+                return -EINVAL;
+
+        return clk->ops->enable(clk);
+}
+EXPORT_SYMBOL_GPL(clk_enable);
+
+void clk_disable(struct clk *clk)
+{
+        if (clk->ops->disable)
+                clk->ops->disable(clk);
+}
+EXPORT_SYMBOL_GPL(clk_disable);
+
+int clk_is_enabled(struct clk *clk)
+{
+        if (clk->ops->is_enabled)
+                return clk->ops->is_enabled(clk);
+
+        return 1;
+}
+
+unsigned long clk_get_rate(struct clk *clk)
+{
+        if (clk->ops->get_rate)
+                return clk->ops->get_rate(clk);
+        if (clk->parent)
+                return clk_get_rate(clk->parent);
+
+        return -EINVAL;
+}
+EXPORT_SYMBOL_GPL(clk_get_rate);
+
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+        if (!clk->ops->set_rate)
+                return -EINVAL;
+        return clk->ops->set_rate(clk, rate);
+}
+EXPORT_SYMBOL_GPL(clk_set_rate);
+
+long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+        if (clk->ops->round_rate)
+                return clk->ops->round_rate(clk, rate);
+
+        return -EINVAL;
+}
+EXPORT_SYMBOL_GPL(clk_round_rate);
+
+int clk_set_parent(struct clk *clk, struct clk *parent)
+{
+        int ret;
+        int enabled;
+
+        if (!clk->ops->set_parent)
+                return -EINVAL;
+
+        enabled = clk_is_enabled(clk);
+        if (enabled)
+                clk_disable(clk);
+        ret = clk->ops->set_parent(clk, parent);
+        if (enabled)
+                clk_enable(clk);
+
+        jz4740_clock_debugfs_update_parent(clk);
+
+        return ret;
+}
+EXPORT_SYMBOL_GPL(clk_set_parent);
+
+struct clk *clk_get(struct device *dev, const char *name)
+{
+        struct clk *clk;
+
+        list_for_each_entry(clk, &jz_clocks, list) {
+                if (strcmp(clk->name, name) == 0)
+                        return clk;
+        }
+        return ERR_PTR(-ENXIO);
+}
+EXPORT_SYMBOL_GPL(clk_get);
+
+void clk_put(struct clk *clk)
+{
+}
+EXPORT_SYMBOL_GPL(clk_put);
+
+static inline void clk_add(struct clk *clk)
+{
+        list_add_tail(&clk->list, &jz_clocks);
+
+        jz4740_clock_debugfs_add_clk(clk);
+}
+
+static void clk_register_clks(void)
+{
+        size_t i;
+
+        clk_add(&jz_clk_ext.clk);
+        clk_add(&jz_clk_pll);
+        clk_add(&jz_clk_pll_half);
+        clk_add(&jz_clk_cpu.clk);
+        clk_add(&jz_clk_high_speed_peripheral.clk);
+        clk_add(&jz_clk_low_speed_peripheral.clk);
+        clk_add(&jz_clk_ko);
+        clk_add(&jz_clk_ld);
+        clk_add(&jz_clk_rtc.clk);
+
+        for (i = 0; i < ARRAY_SIZE(jz4740_clock_divided_clks); ++i)
+                clk_add(&jz4740_clock_divided_clks[i].clk);
+
+        for (i = 0; i < ARRAY_SIZE(jz4740_clock_simple_clks); ++i)
+                clk_add(&jz4740_clock_simple_clks[i]);
+}
+
+void jz4740_clock_set_wait_mode(enum jz4740_wait_mode mode)
+{
+        switch (mode) {
+        case JZ4740_WAIT_MODE_IDLE:
+                jz_clk_reg_clear_bits(JZ_REG_CLOCK_LOW_POWER, JZ_CLOCK_LOW_POWER_MODE_SLEEP);
+                break;
+        case JZ4740_WAIT_MODE_SLEEP:
+                jz_clk_reg_set_bits(JZ_REG_CLOCK_LOW_POWER, JZ_CLOCK_LOW_POWER_MODE_SLEEP);
+                break;
+        }
+}
+
+void jz4740_clock_udc_disable_auto_suspend(void)
+{
+        jz_clk_reg_clear_bits(JZ_REG_CLOCK_GATE, JZ_CLOCK_GATE_UDC);
+}
+EXPORT_SYMBOL_GPL(jz4740_clock_udc_disable_auto_suspend);
+
+void jz4740_clock_udc_enable_auto_suspend(void)
+{
+        jz_clk_reg_set_bits(JZ_REG_CLOCK_GATE, JZ_CLOCK_GATE_UDC);
+}
+EXPORT_SYMBOL_GPL(jz4740_clock_udc_enable_auto_suspend);
+
+void jz4740_clock_suspend(void)
+{
+        jz_clk_reg_set_bits(JZ_REG_CLOCK_GATE,
+                JZ_CLOCK_GATE_TCU | JZ_CLOCK_GATE_DMAC | JZ_CLOCK_GATE_UART0);
+
+        jz_clk_reg_clear_bits(JZ_REG_CLOCK_PLL, JZ_CLOCK_PLL_ENABLED);
+}
+
+void jz4740_clock_resume(void)
+{
+        uint32_t pll;
+
+        jz_clk_reg_set_bits(JZ_REG_CLOCK_PLL, JZ_CLOCK_PLL_ENABLED);
+
+        do {
+                pll = jz_clk_reg_read(JZ_REG_CLOCK_PLL);
+        } while (!(pll & JZ_CLOCK_PLL_STABLE));
+
+        jz_clk_reg_clear_bits(JZ_REG_CLOCK_GATE,
+                JZ_CLOCK_GATE_TCU | JZ_CLOCK_GATE_DMAC | JZ_CLOCK_GATE_UART0);
+}
+
+static int jz4740_clock_init(void)
+{
+        uint32_t val;
+
+        jz_clock_base = ioremap(JZ4740_CPM_BASE_ADDR, 0x100);
+        if (!jz_clock_base)
+                return -EBUSY;
+
+        spin_lock_init(&jz_clock_lock);
+
+        jz_clk_ext.rate = jz4740_clock_bdata.ext_rate;
+        jz_clk_rtc.rate = jz4740_clock_bdata.rtc_rate;
+
+        val = jz_clk_reg_read(JZ_REG_CLOCK_SPI);
+
+        if (val & JZ_CLOCK_SPI_SRC_PLL)
+                jz4740_clock_divided_clks[1].clk.parent = &jz_clk_pll_half;
+
+        val = jz_clk_reg_read(JZ_REG_CLOCK_CTRL);
+
+        if (val & JZ_CLOCK_CTRL_I2S_SRC_PLL)
+                jz4740_clock_divided_clks[0].clk.parent = &jz_clk_pll_half;
+
+        if (val & JZ_CLOCK_CTRL_UDC_SRC_PLL)
+                jz4740_clock_simple_clks[0].parent = &jz_clk_pll_half;
+
+        jz4740_clock_debugfs_init();
+
+        clk_register_clks();
+
+        return 0;
+}
+arch_initcall(jz4740_clock_init);
diff --git a/arch/mips/jz4740/clock.h b/arch/mips/jz4740/clock.h
new file mode 100644
index 000000000000..5d07499d7461
--- /dev/null
+++ b/arch/mips/jz4740/clock.h
@@ -0,0 +1,76 @@
+/*
+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ *  JZ4740 SoC clock support
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __MIPS_JZ4740_CLOCK_H__
+#define __MIPS_JZ4740_CLOCK_H__
+
+#include <linux/list.h>
+
+struct jz4740_clock_board_data {
+        unsigned long ext_rate;
+        unsigned long rtc_rate;
+};
+
+extern struct jz4740_clock_board_data jz4740_clock_bdata;
+
+void jz4740_clock_suspend(void);
+void jz4740_clock_resume(void);
+
+struct clk;
+
+struct clk_ops {
+        unsigned long (*get_rate)(struct clk *clk);
+        unsigned long (*round_rate)(struct clk *clk, unsigned long rate);
+        int (*set_rate)(struct clk *clk, unsigned long rate);
+        int (*enable)(struct clk *clk);
+        int (*disable)(struct clk *clk);
+        int (*is_enabled)(struct clk *clk);
+
+        int (*set_parent)(struct clk *clk, struct clk *parent);
+
+};
+
+struct clk {
+        const char *name;
+        struct clk *parent;
+
+        uint32_t gate_bit;
+
+        const struct clk_ops *ops;
+
+        struct list_head list;
+
+#ifdef CONFIG_DEBUG_FS
+        struct dentry *debugfs_entry;
+        struct dentry *debugfs_parent_entry;
+#endif
+
+};
+
+#define JZ4740_CLK_NOT_GATED ((uint32_t)-1)
+
+int clk_is_enabled(struct clk *clk);
+
+#ifdef CONFIG_DEBUG_FS
+void jz4740_clock_debugfs_init(void);
+void jz4740_clock_debugfs_add_clk(struct clk *clk);
+void jz4740_clock_debugfs_update_parent(struct clk *clk);
+#else
+static inline void jz4740_clock_debugfs_init(void) {};
+static inline void jz4740_clock_debugfs_add_clk(struct clk *clk) {};
+static inline void jz4740_clock_debugfs_update_parent(struct clk *clk) {};
+#endif
+
+#endif
diff --git a/arch/mips/jz4740/dma.c b/arch/mips/jz4740/dma.c
new file mode 100644
index 000000000000..5ebe75a68350
--- /dev/null
+++ b/arch/mips/jz4740/dma.c
@@ -0,0 +1,289 @@
+/*
+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ *  JZ4740 SoC DMA support
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under  the terms of the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/spinlock.h>
+#include <linux/interrupt.h>
+
+#include <linux/dma-mapping.h>
+#include <asm/mach-jz4740/dma.h>
+#include <asm/mach-jz4740/base.h>
+
+#define JZ_REG_DMA_SRC_ADDR(x)          (0x00 + (x) * 0x20)
+#define JZ_REG_DMA_DST_ADDR(x)          (0x04 + (x) * 0x20)
+#define JZ_REG_DMA_TRANSFER_COUNT(x)    (0x08 + (x) * 0x20)
+#define JZ_REG_DMA_REQ_TYPE(x)          (0x0C + (x) * 0x20)
+#define JZ_REG_DMA_STATUS_CTRL(x)       (0x10 + (x) * 0x20)
+#define JZ_REG_DMA_CMD(x)               (0x14 + (x) * 0x20)
+#define JZ_REG_DMA_DESC_ADDR(x)         (0x18 + (x) * 0x20)
+
+#define JZ_REG_DMA_CTRL                 0x300
+#define JZ_REG_DMA_IRQ                  0x304
+#define JZ_REG_DMA_DOORBELL             0x308
+#define JZ_REG_DMA_DOORBELL_SET         0x30C
+
+#define JZ_DMA_STATUS_CTRL_NO_DESC              BIT(31)
+#define JZ_DMA_STATUS_CTRL_DESC_INV             BIT(6)
+#define JZ_DMA_STATUS_CTRL_ADDR_ERR             BIT(4)
+#define JZ_DMA_STATUS_CTRL_TRANSFER_DONE        BIT(3)
+#define JZ_DMA_STATUS_CTRL_HALT                 BIT(2)
+#define JZ_DMA_STATUS_CTRL_COUNT_TERMINATE      BIT(1)
+#define JZ_DMA_STATUS_CTRL_ENABLE               BIT(0)
+
+#define JZ_DMA_CMD_SRC_INC                      BIT(23)
+#define JZ_DMA_CMD_DST_INC                      BIT(22)
+#define JZ_DMA_CMD_RDIL_MASK                    (0xf << 16)
+#define JZ_DMA_CMD_SRC_WIDTH_MASK               (0x3 << 14)
+#define JZ_DMA_CMD_DST_WIDTH_MASK               (0x3 << 12)
+#define JZ_DMA_CMD_INTERVAL_LENGTH_MASK         (0x7 << 8)
+#define JZ_DMA_CMD_BLOCK_MODE                   BIT(7)
+#define JZ_DMA_CMD_DESC_VALID                   BIT(4)
+#define JZ_DMA_CMD_DESC_VALID_MODE              BIT(3)
+#define JZ_DMA_CMD_VALID_IRQ_ENABLE             BIT(2)
+#define JZ_DMA_CMD_TRANSFER_IRQ_ENABLE          BIT(1)
+#define JZ_DMA_CMD_LINK_ENABLE                  BIT(0)
+
+#define JZ_DMA_CMD_FLAGS_OFFSET 22
+#define JZ_DMA_CMD_RDIL_OFFSET 16
+#define JZ_DMA_CMD_SRC_WIDTH_OFFSET 14
+#define JZ_DMA_CMD_DST_WIDTH_OFFSET 12
+#define JZ_DMA_CMD_TRANSFER_SIZE_OFFSET 8
+#define JZ_DMA_CMD_MODE_OFFSET 7
+
+#define JZ_DMA_CTRL_PRIORITY_MASK       (0x3 << 8)
+#define JZ_DMA_CTRL_HALT                BIT(3)
+#define JZ_DMA_CTRL_ADDRESS_ERROR       BIT(2)
+#define JZ_DMA_CTRL_ENABLE              BIT(0)
+
+
+static void __iomem *jz4740_dma_base;
+static spinlock_t jz4740_dma_lock;
+
+static inline uint32_t jz4740_dma_read(size_t reg)
+{
+        return readl(jz4740_dma_base + reg);
+}
+
+static inline void jz4740_dma_write(size_t reg, uint32_t val)
+{
+        writel(val, jz4740_dma_base + reg);
+}
+
+static inline void jz4740_dma_write_mask(size_t reg, uint32_t val, uint32_t mask)
+{
+        uint32_t val2;
+        val2 = jz4740_dma_read(reg);
+        val2 &= ~mask;
+        val2 |= val;
+        jz4740_dma_write(reg, val2);
+}
+
+struct jz4740_dma_chan {
+        unsigned int id;
+        void *dev;
+        const char *name;
+
+        enum jz4740_dma_flags flags;
+        uint32_t transfer_shift;
+
+        jz4740_dma_complete_callback_t complete_cb;
+
+        unsigned used:1;
+};
+
+#define JZ4740_DMA_CHANNEL(_id) { .id = _id }
+
+struct jz4740_dma_chan jz4740_dma_channels[] = {
+        JZ4740_DMA_CHANNEL(0),
+        JZ4740_DMA_CHANNEL(1),
+        JZ4740_DMA_CHANNEL(2),
+        JZ4740_DMA_CHANNEL(3),
+        JZ4740_DMA_CHANNEL(4),
+        JZ4740_DMA_CHANNEL(5),
+};
+
+struct jz4740_dma_chan *jz4740_dma_request(void *dev, const char *name)
+{
+        unsigned int i;
+        struct jz4740_dma_chan *dma = NULL;
+
+        spin_lock(&jz4740_dma_lock);
+
+        for (i = 0; i < ARRAY_SIZE(jz4740_dma_channels); ++i) {
+                if (!jz4740_dma_channels[i].used) {
+                        dma = &jz4740_dma_channels[i];
+                        dma->used = 1;
+                        break;
+                }
+        }
+
+        spin_unlock(&jz4740_dma_lock);
+
+        if (!dma)
+                return NULL;
+
+        dma->dev = dev;
+        dma->name = name;
+
+        return dma;
+}
+EXPORT_SYMBOL_GPL(jz4740_dma_request);
+
+void jz4740_dma_configure(struct jz4740_dma_chan *dma,
+        const struct jz4740_dma_config *config)
+{
+        uint32_t cmd;
+
+        switch (config->transfer_size) {
+        case JZ4740_DMA_TRANSFER_SIZE_2BYTE:
+                dma->transfer_shift = 1;
+                break;
+        case JZ4740_DMA_TRANSFER_SIZE_4BYTE:
+                dma->transfer_shift = 2;
+                break;
+        case JZ4740_DMA_TRANSFER_SIZE_16BYTE:
+                dma->transfer_shift = 4;
+                break;
+        case JZ4740_DMA_TRANSFER_SIZE_32BYTE:
+                dma->transfer_shift = 5;
+                break;
+        default:
+                dma->transfer_shift = 0;
+                break;
+        }
+
+        cmd = config->flags << JZ_DMA_CMD_FLAGS_OFFSET;
+        cmd |= config->src_width << JZ_DMA_CMD_SRC_WIDTH_OFFSET;
+        cmd |= config->dst_width << JZ_DMA_CMD_DST_WIDTH_OFFSET;
+        cmd |= config->transfer_size << JZ_DMA_CMD_TRANSFER_SIZE_OFFSET;
+        cmd |= config->mode << JZ_DMA_CMD_MODE_OFFSET;
+        cmd |= JZ_DMA_CMD_TRANSFER_IRQ_ENABLE;
+
+        jz4740_dma_write(JZ_REG_DMA_CMD(dma->id), cmd);
+        jz4740_dma_write(JZ_REG_DMA_STATUS_CTRL(dma->id), 0);
+        jz4740_dma_write(JZ_REG_DMA_REQ_TYPE(dma->id), config->request_type);
+}
+EXPORT_SYMBOL_GPL(jz4740_dma_configure);
+
+void jz4740_dma_set_src_addr(struct jz4740_dma_chan *dma, dma_addr_t src)
+{
+        jz4740_dma_write(JZ_REG_DMA_SRC_ADDR(dma->id), src);
+}
+EXPORT_SYMBOL_GPL(jz4740_dma_set_src_addr);
+
+void jz4740_dma_set_dst_addr(struct jz4740_dma_chan *dma, dma_addr_t dst)
+{
+        jz4740_dma_write(JZ_REG_DMA_DST_ADDR(dma->id), dst);
+}
+EXPORT_SYMBOL_GPL(jz4740_dma_set_dst_addr);
+
+void jz4740_dma_set_transfer_count(struct jz4740_dma_chan *dma, uint32_t count)
+{
+        count >>= dma->transfer_shift;
+        jz4740_dma_write(JZ_REG_DMA_TRANSFER_COUNT(dma->id), count);
+}
+EXPORT_SYMBOL_GPL(jz4740_dma_set_transfer_count);
+
+void jz4740_dma_set_complete_cb(struct jz4740_dma_chan *dma,
+        jz4740_dma_complete_callback_t cb)
+{
+        dma->complete_cb = cb;
+}
+EXPORT_SYMBOL_GPL(jz4740_dma_set_complete_cb);
+
+void jz4740_dma_free(struct jz4740_dma_chan *dma)
+{
+        dma->dev = NULL;
+        dma->complete_cb = NULL;
+        dma->used = 0;
+}
+EXPORT_SYMBOL_GPL(jz4740_dma_free);
+
+void jz4740_dma_enable(struct jz4740_dma_chan *dma)
+{
+        jz4740_dma_write_mask(JZ_REG_DMA_STATUS_CTRL(dma->id),
+                        JZ_DMA_STATUS_CTRL_NO_DESC | JZ_DMA_STATUS_CTRL_ENABLE,
+                        JZ_DMA_STATUS_CTRL_HALT | JZ_DMA_STATUS_CTRL_NO_DESC |
+                        JZ_DMA_STATUS_CTRL_ENABLE);
+
+        jz4740_dma_write_mask(JZ_REG_DMA_CTRL,
+                        JZ_DMA_CTRL_ENABLE,
+                        JZ_DMA_CTRL_HALT | JZ_DMA_CTRL_ENABLE);
+}
+EXPORT_SYMBOL_GPL(jz4740_dma_enable);
+
+void jz4740_dma_disable(struct jz4740_dma_chan *dma)
+{
+        jz4740_dma_write_mask(JZ_REG_DMA_STATUS_CTRL(dma->id), 0,
+                        JZ_DMA_STATUS_CTRL_ENABLE);
+}
+EXPORT_SYMBOL_GPL(jz4740_dma_disable);
+
+uint32_t jz4740_dma_get_residue(const struct jz4740_dma_chan *dma)
+{
+        uint32_t residue;
+        residue = jz4740_dma_read(JZ_REG_DMA_TRANSFER_COUNT(dma->id));
+        return residue << dma->transfer_shift;
+}
+EXPORT_SYMBOL_GPL(jz4740_dma_get_residue);
+
+static void jz4740_dma_chan_irq(struct jz4740_dma_chan *dma)
+{
+        uint32_t status;
+
+        status = jz4740_dma_read(JZ_REG_DMA_STATUS_CTRL(dma->id));
+
+        jz4740_dma_write_mask(JZ_REG_DMA_STATUS_CTRL(dma->id), 0,
+                JZ_DMA_STATUS_CTRL_ENABLE | JZ_DMA_STATUS_CTRL_TRANSFER_DONE);
+
+        if (dma->complete_cb)
+                dma->complete_cb(dma, 0, dma->dev);
+}
+
+static irqreturn_t jz4740_dma_irq(int irq, void *dev_id)
+{
+        uint32_t irq_status;
+        unsigned int i;
+
+        irq_status = readl(jz4740_dma_base + JZ_REG_DMA_IRQ);
+
+        for (i = 0; i < 6; ++i) {
+                if (irq_status & (1 << i))
+                        jz4740_dma_chan_irq(&jz4740_dma_channels[i]);
+        }
+
+        return IRQ_HANDLED;
+}
+
+static int jz4740_dma_init(void)
+{
+        unsigned int ret;
+
+        jz4740_dma_base = ioremap(JZ4740_DMAC_BASE_ADDR, 0x400);
+
+        if (!jz4740_dma_base)
+                return -EBUSY;
+
+        spin_lock_init(&jz4740_dma_lock);
+
+        ret = request_irq(JZ4740_IRQ_DMAC, jz4740_dma_irq, 0, "DMA", NULL);
+
+        if (ret)
+                printk(KERN_ERR "JZ4740 DMA: Failed to request irq: %d\n", ret);
+
+        return ret;
+}
+arch_initcall(jz4740_dma_init);
diff --git a/arch/mips/jz4740/gpio.c b/arch/mips/jz4740/gpio.c
new file mode 100644
index 000000000000..38f60f35156c
--- /dev/null
+++ b/arch/mips/jz4740/gpio.c
@@ -0,0 +1,604 @@
+/*
+ *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
+ *  JZ4740 platform GPIO support
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under  the terms of the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+
+#include <linux/spinlock.h>
+#include <linux/sysdev.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/bitops.h>
+
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+
+#include <asm/mach-jz4740/base.h>
+
+#define JZ4740_GPIO_BASE_A (32*0)
+#define JZ4740_GPIO_BASE_B (32*1)
+#define JZ4740_GPIO_BASE_C (32*2)
+#define JZ4740_GPIO_BASE_D (32*3)
+
+#define JZ4740_GPIO_NUM_A 32
+#define JZ4740_GPIO_NUM_B 32
+#define JZ4740_GPIO_NUM_C 31
+#define JZ4740_GPIO_NUM_D 32
+
+#define JZ4740_IRQ_GPIO_BASE_A (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_A)
+#define JZ4740_IRQ_GPIO_BASE_B (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_B)
+#define JZ4740_IRQ_GPIO_BASE_C (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_C)
+#define JZ4740_IRQ_GPIO_BASE_D (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_D)
+
+#define JZ_REG_GPIO_PIN                 0x00
+#define JZ_REG_GPIO_DATA                0x10
+#define JZ_REG_GPIO_DATA_SET            0x14
+#define JZ_REG_GPIO_DATA_CLEAR          0x18
+#define JZ_REG_GPIO_MASK                0x20
+#define JZ_REG_GPIO_MASK_SET            0x24
+#define JZ_REG_GPIO_MASK_CLEAR          0x28
+#define JZ_REG_GPIO_PULL                0x30
+#define JZ_REG_GPIO_PULL_SET            0x34
+#define JZ_REG_GPIO_PULL_CLEAR          0x38
+#define JZ_REG_GPIO_FUNC                0x40
+#define JZ_REG_GPIO_FUNC_SET            0x44
+#define JZ_REG_GPIO_FUNC_CLEAR          0x48
+#define JZ_REG_GPIO_SELECT              0x50
+#define JZ_REG_GPIO_SELECT_SET          0x54
+#define JZ_REG_GPIO_SELECT_CLEAR        0x58
+#define JZ_REG_GPIO_DIRECTION           0x60
+#define JZ_REG_GPIO_DIRECTION_SET       0x64
+#define JZ_REG_GPIO_DIRECTION_CLEAR     0x68
+#define JZ_REG_GPIO_TRIGGER             0x70
+#define JZ_REG_GPIO_TRIGGER_SET         0x74
+#define JZ_REG_GPIO_TRIGGER_CLEAR       0x78
+#define JZ_REG_GPIO_FLAG                0x80
+#define JZ_REG_GPIO_FLAG_CLEAR          0x14
+
+#define GPIO_TO_BIT(gpio) BIT(gpio & 0x1f)
+#define GPIO_TO_REG(gpio, reg) (gpio_to_jz_gpio_chip(gpio)->base + (reg))
+#define CHIP_TO_REG(chip, reg) (gpio_chip_to_jz_gpio_chip(chip)->base + (reg))
+
+struct jz_gpio_chip {
+        unsigned int irq;
+        unsigned int irq_base;
+        uint32_t wakeup;
+        uint32_t suspend_mask;
+        uint32_t edge_trigger_both;
+
+        void __iomem *base;
+
+        spinlock_t lock;
+
+        struct gpio_chip gpio_chip;
+        struct irq_chip irq_chip;
+        struct sys_device sysdev;
+};
+
+static struct jz_gpio_chip jz4740_gpio_chips[];
+
+static inline struct jz_gpio_chip *gpio_to_jz_gpio_chip(unsigned int gpio)
+{
+        return &jz4740_gpio_chips[gpio >> 5];
+}
+
+static inline struct jz_gpio_chip *gpio_chip_to_jz_gpio_chip(struct gpio_chip *gpio_chip)
+{
+        return container_of(gpio_chip, struct jz_gpio_chip, gpio_chip);
+}
+
+static inline struct jz_gpio_chip *irq_to_jz_gpio_chip(unsigned int irq)
+{
+        return get_irq_chip_data(irq);
+}
+
+static inline void jz_gpio_write_bit(unsigned int gpio, unsigned int reg)
+{
+        writel(GPIO_TO_BIT(gpio), GPIO_TO_REG(gpio, reg));
+}
+
+int jz_gpio_set_function(int gpio, enum jz_gpio_function function)
+{
+        if (function == JZ_GPIO_FUNC_NONE) {
+                jz_gpio_write_bit(gpio, JZ_REG_GPIO_FUNC_CLEAR);
+                jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_CLEAR);
+                jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_CLEAR);
+        } else {
+                jz_gpio_write_bit(gpio, JZ_REG_GPIO_FUNC_SET);
+                jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_CLEAR);
+                switch (function) {
+                case JZ_GPIO_FUNC1:
+                        jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_CLEAR);
+                        break;
+                case JZ_GPIO_FUNC3:
+                        jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_SET);
+                case JZ_GPIO_FUNC2: /* Falltrough */
+                        jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_SET);
+                        break;
+                default:
+                        BUG();
+                        break;
+                }
+        }
+
+        return 0;
+}
+EXPORT_SYMBOL_GPL(jz_gpio_set_function);
+
+int jz_gpio_bulk_request(const struct jz_gpio_bulk_request *request, size_t num)
+{
+        size_t i;
+        int ret;
+
+        for (i = 0; i < num; ++i, ++request) {
+                ret = gpio_request(request->gpio, request->name);
+                if (ret)
+                        goto err;
+                jz_gpio_set_function(request->gpio, request->function);
+        }
+
+        return 0;
+
+err:
+        for (--request; i > 0; --i, --request) {
+                gpio_free(request->gpio);
+                jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE);
+        }
+
+        return ret;
+}
+EXPORT_SYMBOL_GPL(jz_gpio_bulk_request);
+
+void jz_gpio_bulk_free(const struct jz_gpio_bulk_request *request, size_t num)
+{
+        size_t i;
+
+        for (i = 0; i < num; ++i, ++request) {
+                gpio_free(request->gpio);
+                jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE);
+        }
+
+}
+EXPORT_SYMBOL_GPL(jz_gpio_bulk_free);
+
+void jz_gpio_bulk_suspend(const struct jz_gpio_bulk_request *request, size_t num)
+{
+        size_t i;
+
+        for (i = 0; i < num; ++i, ++request) {
+                jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE);
+                jz_gpio_write_bit(request->gpio, JZ_REG_GPIO_DIRECTION_CLEAR);
+                jz_gpio_write_bit(request->gpio, JZ_REG_GPIO_PULL_SET);
+        }
+}
+EXPORT_SYMBOL_GPL(jz_gpio_bulk_suspend);
+
+void jz_gpio_bulk_resume(const struct jz_gpio_bulk_request *request, size_t num)
+{
+        size_t i;
+
+        for (i = 0; i < num; ++i, ++request)
+                jz_gpio_set_function(request->gpio, request->function);
+}
+EXPORT_SYMBOL_GPL(jz_gpio_bulk_resume);
+
+void jz_gpio_enable_pullup(unsigned gpio)
+{
+        jz_gpio_write_bit(gpio, JZ_REG_GPIO_PULL_CLEAR);
+}
+EXPORT_SYMBOL_GPL(jz_gpio_enable_pullup);
+
+void jz_gpio_disable_pullup(unsigned gpio)
+{
+        jz_gpio_write_bit(gpio, JZ_REG_GPIO_PULL_SET);
+}
+EXPORT_SYMBOL_GPL(jz_gpio_disable_pullup);
+
+static int jz_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
+{
+        return !!(readl(CHIP_TO_REG(chip, JZ_REG_GPIO_PIN)) & BIT(gpio));
+}
+
+static void jz_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
+{
+        uint32_t __iomem *reg = CHIP_TO_REG(chip, JZ_REG_GPIO_DATA_SET);
+        reg += !value;
+        writel(BIT(gpio), reg);
+}
+
+static int jz_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
+        int value)
+{
+        writel(BIT(gpio), CHIP_TO_REG(chip, JZ_REG_GPIO_DIRECTION_SET));
+        jz_gpio_set_value(chip, gpio, value);
+
+        return 0;
+}
+
+static int jz_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
+{
+        writel(BIT(gpio), CHIP_TO_REG(chip, JZ_REG_GPIO_DIRECTION_CLEAR));
+
+        return 0;
+}
+
+int jz_gpio_port_direction_input(int port, uint32_t mask)
+{
+        writel(mask, GPIO_TO_REG(port, JZ_REG_GPIO_DIRECTION_CLEAR));
+
+        return 0;
+}
+EXPORT_SYMBOL(jz_gpio_port_direction_input);
+
+int jz_gpio_port_direction_output(int port, uint32_t mask)
+{
+        writel(mask, GPIO_TO_REG(port, JZ_REG_GPIO_DIRECTION_SET));
+
+        return 0;
+}
+EXPORT_SYMBOL(jz_gpio_port_direction_output);
+
+void jz_gpio_port_set_value(int port, uint32_t value, uint32_t mask)
+{
+        writel(~value & mask, GPIO_TO_REG(port, JZ_REG_GPIO_DATA_CLEAR));
+        writel(value & mask, GPIO_TO_REG(port, JZ_REG_GPIO_DATA_SET));
+}
+EXPORT_SYMBOL(jz_gpio_port_set_value);
+
+uint32_t jz_gpio_port_get_value(int port, uint32_t mask)
+{
+        uint32_t value = readl(GPIO_TO_REG(port, JZ_REG_GPIO_PIN));
+
+        return value & mask;
+}
+EXPORT_SYMBOL(jz_gpio_port_get_value);
+
+int gpio_to_irq(unsigned gpio)
+{
+        return JZ4740_IRQ_GPIO(0) + gpio;
+}
+EXPORT_SYMBOL_GPL(gpio_to_irq);
+
+int irq_to_gpio(unsigned irq)
+{
+        return irq - JZ4740_IRQ_GPIO(0);
+}
+EXPORT_SYMBOL_GPL(irq_to_gpio);
+
+#define IRQ_TO_BIT(irq) BIT(irq_to_gpio(irq) & 0x1f)
+
+static void jz_gpio_check_trigger_both(struct jz_gpio_chip *chip, unsigned int irq)
+{
+        uint32_t value;
+        void __iomem *reg;
+        uint32_t mask = IRQ_TO_BIT(irq);
+
+        if (!(chip->edge_trigger_both & mask))
+                return;
+
+        reg = chip->base;
+
+        value = readl(chip->base + JZ_REG_GPIO_PIN);
+        if (value & mask)
+                reg += JZ_REG_GPIO_DIRECTION_CLEAR;
+        else
+                reg += JZ_REG_GPIO_DIRECTION_SET;
+
+        writel(mask, reg);
+}
+
+static void jz_gpio_irq_demux_handler(unsigned int irq, struct irq_desc *desc)
+{
+        uint32_t flag;
+        unsigned int gpio_irq;
+        unsigned int gpio_bank;
+        struct jz_gpio_chip *chip = get_irq_desc_data(desc);
+
+        gpio_bank = JZ4740_IRQ_GPIO0 - irq;
+
+        flag = readl(chip->base + JZ_REG_GPIO_FLAG);
+
+        if (!flag)
+                return;
+
+        gpio_irq = __fls(flag);
+
+        jz_gpio_check_trigger_both(chip, irq);
+
+        gpio_irq += (gpio_bank << 5) + JZ4740_IRQ_GPIO(0);
+
+        generic_handle_irq(gpio_irq);
+};
+
+static inline void jz_gpio_set_irq_bit(unsigned int irq, unsigned int reg)
+{
+        struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(irq);
+        writel(IRQ_TO_BIT(irq), chip->base + reg);
+}
+
+static void jz_gpio_irq_mask(unsigned int irq)
+{
+        jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_MASK_SET);
+};
+
+static void jz_gpio_irq_unmask(unsigned int irq)
+{
+        struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(irq);
+
+        jz_gpio_check_trigger_both(chip, irq);
+
+        jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_MASK_CLEAR);
+};
+
+/* TODO: Check if function is gpio */
+static unsigned int jz_gpio_irq_startup(unsigned int irq)
+{
+        struct irq_desc *desc = irq_to_desc(irq);
+
+        jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_SELECT_SET);
+
+        desc->status &= ~IRQ_MASKED;
+        jz_gpio_irq_unmask(irq);
+
+        return 0;
+}
+
+static void jz_gpio_irq_shutdown(unsigned int irq)
+{
+        struct irq_desc *desc = irq_to_desc(irq);
+
+        jz_gpio_irq_mask(irq);
+        desc->status |= IRQ_MASKED;
+
+        /* Set direction to input */
+        jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_CLEAR);
+        jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_SELECT_CLEAR);
+}
+
+static void jz_gpio_irq_ack(unsigned int irq)
+{
+        jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_FLAG_CLEAR);
+};
+
+static int jz_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
+{
+        struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(irq);
+        struct irq_desc *desc = irq_to_desc(irq);
+
+        jz_gpio_irq_mask(irq);
+
+        if (flow_type == IRQ_TYPE_EDGE_BOTH) {
+                uint32_t value = readl(chip->base + JZ_REG_GPIO_PIN);
+                if (value & IRQ_TO_BIT(irq))
+                        flow_type = IRQ_TYPE_EDGE_FALLING;
+                else
+                        flow_type = IRQ_TYPE_EDGE_RISING;
+                chip->edge_trigger_both |= IRQ_TO_BIT(irq);
+        } else {
+                chip->edge_trigger_both &= ~IRQ_TO_BIT(irq);
+        }
+
+        switch (flow_type) {
+        case IRQ_TYPE_EDGE_RISING:
+                jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_SET);
+                jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_SET);
+                break;
+        case IRQ_TYPE_EDGE_FALLING:
+                jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_CLEAR);
+                jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_SET);
+                break;
+        case IRQ_TYPE_LEVEL_HIGH:
+                jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_SET);
+                jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_CLEAR);
+                break;
+        case IRQ_TYPE_LEVEL_LOW:
+                jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_CLEAR);
+                jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_CLEAR);
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        if (!(desc->status & IRQ_MASKED))
+                jz_gpio_irq_unmask(irq);
+
+        return 0;
+}
+
+static int jz_gpio_irq_set_wake(unsigned int irq, unsigned int on)
+{
+        struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(irq);
+        spin_lock(&chip->lock);
+        if (on)
+                chip->wakeup |= IRQ_TO_BIT(irq);
+        else
+                chip->wakeup &= ~IRQ_TO_BIT(irq);
+        spin_unlock(&chip->lock);
+
+        set_irq_wake(chip->irq, on);
+        return 0;
+}
+
+/*
+ * This lock class tells lockdep that GPIO irqs are in a different
+ * category than their parents, so it won't report false recursion.
+ */
+static struct lock_class_key gpio_lock_class;
+
+#define JZ4740_GPIO_CHIP(_bank) { \
+        .irq_base = JZ4740_IRQ_GPIO_BASE_ ## _bank, \
+        .gpio_chip = { \
+                .label = "Bank " # _bank, \
+                .owner = THIS_MODULE, \
+                .set = jz_gpio_set_value, \
+                .get = jz_gpio_get_value, \
+                .direction_output = jz_gpio_direction_output, \
+                .direction_input = jz_gpio_direction_input, \
+                .base = JZ4740_GPIO_BASE_ ## _bank, \
+                .ngpio = JZ4740_GPIO_NUM_ ## _bank, \
+        }, \
+        .irq_chip =  { \
+                .name = "GPIO Bank " # _bank, \
+                .mask = jz_gpio_irq_mask, \
+                .unmask = jz_gpio_irq_unmask, \
+                .ack = jz_gpio_irq_ack, \
+                .startup = jz_gpio_irq_startup, \
+                .shutdown = jz_gpio_irq_shutdown, \
+                .set_type = jz_gpio_irq_set_type, \
+                .set_wake = jz_gpio_irq_set_wake, \
+        }, \
+}
+
+static struct jz_gpio_chip jz4740_gpio_chips[] = {
+        JZ4740_GPIO_CHIP(A),
+        JZ4740_GPIO_CHIP(B),
+        JZ4740_GPIO_CHIP(C),
+        JZ4740_GPIO_CHIP(D),
+};
+
+static inline struct jz_gpio_chip *sysdev_to_chip(struct sys_device *dev)
+{
+        return container_of(dev, struct jz_gpio_chip, sysdev);
+}
+
+static int jz4740_gpio_suspend(struct sys_device *dev, pm_message_t state)
+{
+        struct jz_gpio_chip *chip = sysdev_to_chip(dev);
+
+        chip->suspend_mask = readl(chip->base + JZ_REG_GPIO_MASK);
+        writel(~(chip->wakeup), chip->base + JZ_REG_GPIO_MASK_SET);
+        writel(chip->wakeup, chip->base + JZ_REG_GPIO_MASK_CLEAR);
+
+        return 0;
+}
+
+static int jz4740_gpio_resume(struct sys_device *dev)
+{
+        struct jz_gpio_chip *chip = sysdev_to_chip(dev);
+        uint32_t mask = chip->suspend_mask;
+
+        writel(~mask, chip->base + JZ_REG_GPIO_MASK_CLEAR);
+        writel(mask, chip->base + JZ_REG_GPIO_MASK_SET);
+
+        return 0;
+}
+
+static struct sysdev_class jz4740_gpio_sysdev_class = {
+        .name = "gpio",
+        .suspend = jz4740_gpio_suspend,
+        .resume = jz4740_gpio_resume,
+};
+
+static int jz4740_gpio_chip_init(struct jz_gpio_chip *chip, unsigned int id)
+{
+        int ret, irq;
+
+        chip->sysdev.id = id;
+        chip->sysdev.cls = &jz4740_gpio_sysdev_class;
+        ret = sysdev_register(&chip->sysdev);
+
+        if (ret)
+                return ret;
+
+        spin_lock_init(&chip->lock);
+
+        chip->base = ioremap(JZ4740_GPIO_BASE_ADDR + (id * 0x100), 0x100);
+
+        gpiochip_add(&chip->gpio_chip);
+
+        chip->irq = JZ4740_IRQ_INTC_GPIO(id);
+        set_irq_data(chip->irq, chip);
+        set_irq_chained_handler(chip->irq, jz_gpio_irq_demux_handler);
+
+        for (irq = chip->irq_base; irq < chip->irq_base + chip->gpio_chip.ngpio; ++irq) {
+                lockdep_set_class(&irq_desc[irq].lock, &gpio_lock_class);
+                set_irq_chip_data(irq, chip);
+                set_irq_chip_and_handler(irq, &chip->irq_chip, handle_level_irq);
+        }
+
+        return 0;
+}
+
+static int __init jz4740_gpio_init(void)
+{
+        unsigned int i;
+        int ret;
+
+        ret = sysdev_class_register(&jz4740_gpio_sysdev_class);
+        if (ret)
+                return ret;
+
+        for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); ++i)
+                jz4740_gpio_chip_init(&jz4740_gpio_chips[i], i);
+
+        printk(KERN_INFO "JZ4740 GPIO initalized\n");
+
+        return 0;
+}
+arch_initcall(jz4740_gpio_init);
+
+#ifdef CONFIG_DEBUG_FS
+
+static inline void gpio_seq_reg(struct seq_file *s, struct jz_gpio_chip *chip,
+        const char *name, unsigned int reg)
+{
+        seq_printf(s, "\t%s: %08x\n", name, readl(chip->base + reg));
+}
+
+static int gpio_regs_show(struct seq_file *s, void *unused)
+{
+        struct jz_gpio_chip *chip = jz4740_gpio_chips;
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); ++i, ++chip) {
+                seq_printf(s, "==GPIO %d==\n", i);
+                gpio_seq_reg(s, chip, "Pin", JZ_REG_GPIO_PIN);
+                gpio_seq_reg(s, chip, "Data", JZ_REG_GPIO_DATA);
+                gpio_seq_reg(s, chip, "Mask", JZ_REG_GPIO_MASK);
+                gpio_seq_reg(s, chip, "Pull", JZ_REG_GPIO_PULL);
+                gpio_seq_reg(s, chip, "Func", JZ_REG_GPIO_FUNC);
+                gpio_seq_reg(s, chip, "Select", JZ_REG_GPIO_SELECT);
+                gpio_seq_reg(s, chip, "Direction", JZ_REG_GPIO_DIRECTION);
+                gpio_seq_reg(s, chip, "Trigger", JZ_REG_GPIO_TRIGGER);
+                gpio_seq_reg(s, chip, "Flag", JZ_REG_GPIO_FLAG);
+        }
+
+        return 0;
+}
+
+static int gpio_regs_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, gpio_regs_show, NULL);
+}
+
+static const struct file_operations gpio_regs_operations = {
+        .open           = gpio_regs_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+};
+
+static int __init gpio_debugfs_init(void)
+{
+        (void) debugfs_create_file("jz_regs_gpio", S_IFREG | S_IRUGO,
+                                NULL, NULL, &gpio_regs_operations);
+        return 0;
+}
+subsys_initcall(gpio_debugfs_init);
+
+#endif
diff --git a/arch/mips/jz4740/irq.c b/arch/mips/jz4740/irq.c
new file mode 100644
index 000000000000..7d33ff83580f
--- /dev/null
+++ b/arch/mips/jz4740/irq.c
@@ -0,0 +1,167 @@
+/*
+ *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
+ *  JZ4740 platform IRQ support
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under  the terms of the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/timex.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+
+#include <asm/io.h>
+#include <asm/mipsregs.h>
+#include <asm/irq_cpu.h>
+
+#include <asm/mach-jz4740/base.h>
+
+static void __iomem *jz_intc_base;
+static uint32_t jz_intc_wakeup;
+static uint32_t jz_intc_saved;
+
+#define JZ_REG_INTC_STATUS      0x00
+#define JZ_REG_INTC_MASK        0x04
+#define JZ_REG_INTC_SET_MASK    0x08
+#define JZ_REG_INTC_CLEAR_MASK  0x0c
+#define JZ_REG_INTC_PENDING     0x10
+
+#define IRQ_BIT(x) BIT((x) - JZ4740_IRQ_BASE)
+
+static void intc_irq_unmask(unsigned int irq)
+{
+        writel(IRQ_BIT(irq), jz_intc_base + JZ_REG_INTC_CLEAR_MASK);
+}
+
+static void intc_irq_mask(unsigned int irq)
+{
+        writel(IRQ_BIT(irq), jz_intc_base + JZ_REG_INTC_SET_MASK);
+}
+
+static int intc_irq_set_wake(unsigned int irq, unsigned int on)
+{
+        if (on)
+                jz_intc_wakeup |= IRQ_BIT(irq);
+        else
+                jz_intc_wakeup &= ~IRQ_BIT(irq);
+
+        return 0;
+}
+
+static struct irq_chip intc_irq_type = {
+        .name =         "INTC",
+        .mask =         intc_irq_mask,
+        .mask_ack =     intc_irq_mask,
+        .unmask =       intc_irq_unmask,
+        .set_wake =     intc_irq_set_wake,
+};
+
+static irqreturn_t jz4740_cascade(int irq, void *data)
+{
+        uint32_t irq_reg;
+
+        irq_reg = readl(jz_intc_base + JZ_REG_INTC_PENDING);
+
+        if (irq_reg)
+                generic_handle_irq(__fls(irq_reg) + JZ4740_IRQ_BASE);
+
+        return IRQ_HANDLED;
+}
+
+static struct irqaction jz4740_cascade_action = {
+        .handler = jz4740_cascade,
+        .name = "JZ4740 cascade interrupt",
+};
+
+void __init arch_init_irq(void)
+{
+        int i;
+        mips_cpu_irq_init();
+
+        jz_intc_base = ioremap(JZ4740_INTC_BASE_ADDR, 0x14);
+
+        for (i = JZ4740_IRQ_BASE; i < JZ4740_IRQ_BASE + 32; i++) {
+                intc_irq_mask(i);
+                set_irq_chip_and_handler(i, &intc_irq_type, handle_level_irq);
+        }
+
+        setup_irq(2, &jz4740_cascade_action);
+}
+
+asmlinkage void plat_irq_dispatch(void)
+{
+        unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
+        if (pending & STATUSF_IP2)
+                do_IRQ(2);
+        else if (pending & STATUSF_IP3)
+                do_IRQ(3);
+        else
+                spurious_interrupt();
+}
+
+void jz4740_intc_suspend(void)
+{
+        jz_intc_saved = readl(jz_intc_base + JZ_REG_INTC_MASK);
+        writel(~jz_intc_wakeup, jz_intc_base + JZ_REG_INTC_SET_MASK);
+        writel(jz_intc_wakeup, jz_intc_base + JZ_REG_INTC_CLEAR_MASK);
+}
+
+void jz4740_intc_resume(void)
+{
+        writel(~jz_intc_saved, jz_intc_base + JZ_REG_INTC_CLEAR_MASK);
+        writel(jz_intc_saved, jz_intc_base + JZ_REG_INTC_SET_MASK);
+}
+
+#ifdef CONFIG_DEBUG_FS
+
+static inline void intc_seq_reg(struct seq_file *s, const char *name,
+        unsigned int reg)
+{
+        seq_printf(s, "%s:\t\t%08x\n", name, readl(jz_intc_base + reg));
+}
+
+static int intc_regs_show(struct seq_file *s, void *unused)
+{
+        intc_seq_reg(s, "Status", JZ_REG_INTC_STATUS);
+        intc_seq_reg(s, "Mask", JZ_REG_INTC_MASK);
+        intc_seq_reg(s, "Pending", JZ_REG_INTC_PENDING);
+
+        return 0;
+}
+
+static int intc_regs_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, intc_regs_show, NULL);
+}
+
+static const struct file_operations intc_regs_operations = {
+        .open           = intc_regs_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+};
+
+static int __init intc_debugfs_init(void)
+{
+        (void) debugfs_create_file("jz_regs_intc", S_IFREG | S_IRUGO,
+                                NULL, NULL, &intc_regs_operations);
+        return 0;
+}
+subsys_initcall(intc_debugfs_init);
+
+#endif
diff --git a/arch/mips/jz4740/irq.h b/arch/mips/jz4740/irq.h
new file mode 100644
index 000000000000..56b5eadd1fa2
--- /dev/null
+++ b/arch/mips/jz4740/irq.h
@@ -0,0 +1,21 @@
+/*
+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under  the terms of the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __MIPS_JZ4740_IRQ_H__
+#define __MIPS_JZ4740_IRQ_H__
+
+extern void jz4740_intc_suspend(void);
+extern void jz4740_intc_resume(void);
+
+#endif
diff --git a/arch/mips/jz4740/platform.c b/arch/mips/jz4740/platform.c
new file mode 100644
index 000000000000..95bc2b5b14f1
--- /dev/null
+++ b/arch/mips/jz4740/platform.c
@@ -0,0 +1,291 @@
+/*
+ *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
+ *  JZ4740 platform devices
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under  the terms of the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/resource.h>
+
+#include <linux/dma-mapping.h>
+
+#include <asm/mach-jz4740/platform.h>
+#include <asm/mach-jz4740/base.h>
+#include <asm/mach-jz4740/irq.h>
+
+#include <linux/serial_core.h>
+#include <linux/serial_8250.h>
+
+#include "serial.h"
+#include "clock.h"
+
+/* OHCI controller */
+static struct resource jz4740_usb_ohci_resources[] = {
+        {
+                .start  = JZ4740_UHC_BASE_ADDR,
+                .end    = JZ4740_UHC_BASE_ADDR + 0x1000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = JZ4740_IRQ_UHC,
+                .end    = JZ4740_IRQ_UHC,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device jz4740_usb_ohci_device = {
+        .name           = "jz4740-ohci",
+        .id             = -1,
+        .dev = {
+                .dma_mask = &jz4740_usb_ohci_device.dev.coherent_dma_mask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+        },
+        .num_resources  = ARRAY_SIZE(jz4740_usb_ohci_resources),
+        .resource       = jz4740_usb_ohci_resources,
+};
+
+/* UDC (USB gadget controller) */
+static struct resource jz4740_usb_gdt_resources[] = {
+        {
+                .start  = JZ4740_UDC_BASE_ADDR,
+                .end    = JZ4740_UDC_BASE_ADDR + 0x1000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = JZ4740_IRQ_UDC,
+                .end    = JZ4740_IRQ_UDC,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device jz4740_udc_device = {
+        .name           = "jz-udc",
+        .id             = -1,
+        .dev = {
+                .dma_mask = &jz4740_udc_device.dev.coherent_dma_mask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+        },
+        .num_resources  = ARRAY_SIZE(jz4740_usb_gdt_resources),
+        .resource       = jz4740_usb_gdt_resources,
+};
+
+/* MMC/SD controller */
+static struct resource jz4740_mmc_resources[] = {
+        {
+                .start  = JZ4740_MSC_BASE_ADDR,
+                .end    = JZ4740_MSC_BASE_ADDR + 0x1000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = JZ4740_IRQ_MSC,
+                .end    = JZ4740_IRQ_MSC,
+                .flags  = IORESOURCE_IRQ,
+        }
+};
+
+struct platform_device jz4740_mmc_device = {
+        .name           = "jz4740-mmc",
+        .id             = 0,
+        .dev = {
+                .dma_mask = &jz4740_mmc_device.dev.coherent_dma_mask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+        },
+        .num_resources  = ARRAY_SIZE(jz4740_mmc_resources),
+        .resource       = jz4740_mmc_resources,
+};
+
+/* RTC controller */
+static struct resource jz4740_rtc_resources[] = {
+        {
+                .start  = JZ4740_RTC_BASE_ADDR,
+                .end    = JZ4740_RTC_BASE_ADDR + 0x38 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = JZ4740_IRQ_RTC,
+                .end    = JZ4740_IRQ_RTC,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device jz4740_rtc_device = {
+        .name           = "jz4740-rtc",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(jz4740_rtc_resources),
+        .resource       = jz4740_rtc_resources,
+};
+
+/* I2C controller */
+static struct resource jz4740_i2c_resources[] = {
+        {
+                .start  = JZ4740_I2C_BASE_ADDR,
+                .end    = JZ4740_I2C_BASE_ADDR + 0x1000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = JZ4740_IRQ_I2C,
+                .end    = JZ4740_IRQ_I2C,
+                .flags  = IORESOURCE_IRQ,
+        }
+};
+
+struct platform_device jz4740_i2c_device = {
+        .name           = "jz4740-i2c",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(jz4740_i2c_resources),
+        .resource       = jz4740_i2c_resources,
+};
+
+/* NAND controller */
+static struct resource jz4740_nand_resources[] = {
+        {
+                .name   = "mmio",
+                .start  = JZ4740_EMC_BASE_ADDR,
+                .end    = JZ4740_EMC_BASE_ADDR + 0x1000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "bank",
+                .start  = 0x18000000,
+                .end    = 0x180C0000 - 1,
+                .flags = IORESOURCE_MEM,
+        },
+};
+
+struct platform_device jz4740_nand_device = {
+        .name = "jz4740-nand",
+        .num_resources = ARRAY_SIZE(jz4740_nand_resources),
+        .resource = jz4740_nand_resources,
+};
+
+/* LCD controller */
+static struct resource jz4740_framebuffer_resources[] = {
+        {
+                .start  = JZ4740_LCD_BASE_ADDR,
+                .end    = JZ4740_LCD_BASE_ADDR + 0x1000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+struct platform_device jz4740_framebuffer_device = {
+        .name           = "jz4740-fb",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(jz4740_framebuffer_resources),
+        .resource       = jz4740_framebuffer_resources,
+        .dev = {
+                .dma_mask = &jz4740_framebuffer_device.dev.coherent_dma_mask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+        },
+};
+
+/* I2S controller */
+static struct resource jz4740_i2s_resources[] = {
+        {
+                .start  = JZ4740_AIC_BASE_ADDR,
+                .end    = JZ4740_AIC_BASE_ADDR + 0x38 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+struct platform_device jz4740_i2s_device = {
+        .name           = "jz4740-i2s",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(jz4740_i2s_resources),
+        .resource       = jz4740_i2s_resources,
+};
+
+/* PCM */
+struct platform_device jz4740_pcm_device = {
+        .name           = "jz4740-pcm",
+        .id             = -1,
+};
+
+/* Codec */
+static struct resource jz4740_codec_resources[] = {
+        {
+                .start  = JZ4740_AIC_BASE_ADDR + 0x80,
+                .end    = JZ4740_AIC_BASE_ADDR + 0x88 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+struct platform_device jz4740_codec_device = {
+        .name           = "jz4740-codec",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(jz4740_codec_resources),
+        .resource       = jz4740_codec_resources,
+};
+
+/* ADC controller */
+static struct resource jz4740_adc_resources[] = {
+        {
+                .start  = JZ4740_SADC_BASE_ADDR,
+                .end    = JZ4740_SADC_BASE_ADDR + 0x30,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = JZ4740_IRQ_SADC,
+                .end    = JZ4740_IRQ_SADC,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .start  = JZ4740_IRQ_ADC_BASE,
+                .end    = JZ4740_IRQ_ADC_BASE,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device jz4740_adc_device = {
+        .name           = "jz4740-adc",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(jz4740_adc_resources),
+        .resource       = jz4740_adc_resources,
+};
+
+/* Serial */
+#define JZ4740_UART_DATA(_id) \
+        { \
+                .flags = UPF_SKIP_TEST | UPF_IOREMAP | UPF_FIXED_TYPE, \
+                .iotype = UPIO_MEM, \
+                .regshift = 2, \
+                .serial_out = jz4740_serial_out, \
+                .type = PORT_16550, \
+                .mapbase = JZ4740_UART ## _id ## _BASE_ADDR, \
+                .irq = JZ4740_IRQ_UART ## _id, \
+        }
+
+static struct plat_serial8250_port jz4740_uart_data[] = {
+        JZ4740_UART_DATA(0),
+        JZ4740_UART_DATA(1),
+        {},
+};
+
+static struct platform_device jz4740_uart_device = {
+        .name = "serial8250",
+        .id = 0,
+        .dev = {
+                .platform_data = jz4740_uart_data,
+        },
+};
+
+void jz4740_serial_device_register(void)
+{
+        struct plat_serial8250_port *p;
+
+        for (p = jz4740_uart_data; p->flags != 0; ++p)
+                p->uartclk = jz4740_clock_bdata.ext_rate;
+
+        platform_device_register(&jz4740_uart_device);
+}
diff --git a/arch/mips/jz4740/pm.c b/arch/mips/jz4740/pm.c
new file mode 100644
index 000000000000..a9994585424d
--- /dev/null
+++ b/arch/mips/jz4740/pm.c
@@ -0,0 +1,56 @@
+/*
+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ *      JZ4740 SoC power management support
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under  the terms of the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/pm.h>
+#include <linux/delay.h>
+#include <linux/suspend.h>
+
+#include <asm/mach-jz4740/clock.h>
+
+#include "clock.h"
+#include "irq.h"
+
+static int jz4740_pm_enter(suspend_state_t state)
+{
+        jz4740_intc_suspend();
+        jz4740_clock_suspend();
+
+        jz4740_clock_set_wait_mode(JZ4740_WAIT_MODE_SLEEP);
+
+        __asm__(".set\tmips3\n\t"
+                "wait\n\t"
+                ".set\tmips0");
+
+        jz4740_clock_set_wait_mode(JZ4740_WAIT_MODE_IDLE);
+
+        jz4740_clock_resume();
+        jz4740_intc_resume();
+
+        return 0;
+}
+
+static struct platform_suspend_ops jz4740_pm_ops = {
+        .valid          = suspend_valid_only_mem,
+        .enter          = jz4740_pm_enter,
+};
+
+static int __init jz4740_pm_init(void)
+{
+        suspend_set_ops(&jz4740_pm_ops);
+        return 0;
+
+}
+late_initcall(jz4740_pm_init);
diff --git a/arch/mips/jz4740/prom.c b/arch/mips/jz4740/prom.c
new file mode 100644
index 000000000000..cfeac15eb2e4
--- /dev/null
+++ b/arch/mips/jz4740/prom.c
@@ -0,0 +1,68 @@
+/*
+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ *  JZ4740 SoC prom code
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under  the terms of the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/string.h>
+
+#include <linux/serial_reg.h>
+
+#include <asm/bootinfo.h>
+#include <asm/mach-jz4740/base.h>
+
+void jz4740_init_cmdline(int argc, char *argv[])
+{
+        unsigned int count = COMMAND_LINE_SIZE - 1;
+        int i;
+        char *dst = &(arcs_cmdline[0]);
+        char *src;
+
+        for (i = 1; i < argc && count; ++i) {
+                src = argv[i];
+                while (*src && count) {
+                        *dst++ = *src++;
+                        --count;
+                }
+                *dst++ = ' ';
+        }
+        if (i > 1)
+                --dst;
+
+        *dst = 0;
+}
+
+void __init prom_init(void)
+{
+        jz4740_init_cmdline((int)fw_arg0, (char **)fw_arg1);
+        mips_machtype = MACH_INGENIC_JZ4740;
+}
+
+void __init prom_free_prom_memory(void)
+{
+}
+
+#define UART_REG(_reg) ((void __iomem *)CKSEG1ADDR(JZ4740_UART0_BASE_ADDR + (_reg << 2)))
+
+void prom_putchar(char c)
+{
+        uint8_t lsr;
+
+        do {
+                lsr = readb(UART_REG(UART_LSR));
+        } while ((lsr & UART_LSR_TEMT) == 0);
+
+        writeb(c, UART_REG(UART_TX));
+}
diff --git a/arch/mips/jz4740/pwm.c b/arch/mips/jz4740/pwm.c
new file mode 100644
index 000000000000..a26a6faec9a6
--- /dev/null
+++ b/arch/mips/jz4740/pwm.c
@@ -0,0 +1,177 @@
+/*
+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ *  JZ4740 platform PWM support
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under  the terms of the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#include <linux/kernel.h>
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/pwm.h>
+#include <linux/gpio.h>
+
+#include <asm/mach-jz4740/gpio.h>
+#include "timer.h"
+
+static struct clk *jz4740_pwm_clk;
+
+DEFINE_MUTEX(jz4740_pwm_mutex);
+
+struct pwm_device {
+        unsigned int id;
+        unsigned int gpio;
+        bool used;
+};
+
+static struct pwm_device jz4740_pwm_list[] = {
+        { 2, JZ_GPIO_PWM2, false },
+        { 3, JZ_GPIO_PWM3, false },
+        { 4, JZ_GPIO_PWM4, false },
+        { 5, JZ_GPIO_PWM5, false },
+        { 6, JZ_GPIO_PWM6, false },
+        { 7, JZ_GPIO_PWM7, false },
+};
+
+struct pwm_device *pwm_request(int id, const char *label)
+{
+        int ret = 0;
+        struct pwm_device *pwm;
+
+        if (id < 2 || id > 7 || !jz4740_pwm_clk)
+                return ERR_PTR(-ENODEV);
+
+        mutex_lock(&jz4740_pwm_mutex);
+
+        pwm = &jz4740_pwm_list[id - 2];
+        if (pwm->used)
+                ret = -EBUSY;
+        else
+                pwm->used = true;
+
+        mutex_unlock(&jz4740_pwm_mutex);
+
+        if (ret)
+                return ERR_PTR(ret);
+
+        ret = gpio_request(pwm->gpio, label);
+
+        if (ret) {
+                printk(KERN_ERR "Failed to request pwm gpio: %d\n", ret);
+                pwm->used = false;
+                return ERR_PTR(ret);
+        }
+
+        jz_gpio_set_function(pwm->gpio, JZ_GPIO_FUNC_PWM);
+
+        jz4740_timer_start(id);
+
+        return pwm;
+}
+
+void pwm_free(struct pwm_device *pwm)
+{
+        pwm_disable(pwm);
+        jz4740_timer_set_ctrl(pwm->id, 0);
+
+        jz_gpio_set_function(pwm->gpio, JZ_GPIO_FUNC_NONE);
+        gpio_free(pwm->gpio);
+
+        jz4740_timer_stop(pwm->id);
+
+        pwm->used = false;
+}
+
+int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
+{
+        unsigned long long tmp;
+        unsigned long period, duty;
+        unsigned int prescaler = 0;
+        unsigned int id = pwm->id;
+        uint16_t ctrl;
+        bool is_enabled;
+
+        if (duty_ns < 0 || duty_ns > period_ns)
+                return -EINVAL;
+
+        tmp = (unsigned long long)clk_get_rate(jz4740_pwm_clk) * period_ns;
+        do_div(tmp, 1000000000);
+        period = tmp;
+
+        while (period > 0xffff && prescaler < 6) {
+                period >>= 2;
+                ++prescaler;
+        }
+
+        if (prescaler == 6)
+                return -EINVAL;
+
+        tmp = (unsigned long long)period * duty_ns;
+        do_div(tmp, period_ns);
+        duty = period - tmp;
+
+        if (duty >= period)
+                duty = period - 1;
+
+        is_enabled = jz4740_timer_is_enabled(id);
+        if (is_enabled)
+                pwm_disable(pwm);
+
+        jz4740_timer_set_count(id, 0);
+        jz4740_timer_set_duty(id, duty);
+        jz4740_timer_set_period(id, period);
+
+        ctrl = JZ_TIMER_CTRL_PRESCALER(prescaler) | JZ_TIMER_CTRL_SRC_EXT |
+                JZ_TIMER_CTRL_PWM_ABBRUPT_SHUTDOWN;
+
+        jz4740_timer_set_ctrl(id, ctrl);
+
+        if (is_enabled)
+                pwm_enable(pwm);
+
+        return 0;
+}
+
+int pwm_enable(struct pwm_device *pwm)
+{
+        uint32_t ctrl = jz4740_timer_get_ctrl(pwm->id);
+
+        ctrl |= JZ_TIMER_CTRL_PWM_ENABLE;
+        jz4740_timer_set_ctrl(pwm->id, ctrl);
+        jz4740_timer_enable(pwm->id);
+
+        return 0;
+}
+
+void pwm_disable(struct pwm_device *pwm)
+{
+        uint32_t ctrl = jz4740_timer_get_ctrl(pwm->id);
+
+        ctrl &= ~JZ_TIMER_CTRL_PWM_ENABLE;
+        jz4740_timer_disable(pwm->id);
+        jz4740_timer_set_ctrl(pwm->id, ctrl);
+}
+
+static int __init jz4740_pwm_init(void)
+{
+        int ret = 0;
+
+        jz4740_pwm_clk = clk_get(NULL, "ext");
+
+        if (IS_ERR(jz4740_pwm_clk)) {
+                ret = PTR_ERR(jz4740_pwm_clk);
+                jz4740_pwm_clk = NULL;
+        }
+
+        return ret;
+}
+subsys_initcall(jz4740_pwm_init);
diff --git a/arch/mips/jz4740/reset.c b/arch/mips/jz4740/reset.c
new file mode 100644
index 000000000000..5f1fb95c0d0d
--- /dev/null
+++ b/arch/mips/jz4740/reset.c
@@ -0,0 +1,79 @@
+/*
+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under  the terms of the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/pm.h>
+
+#include <asm/reboot.h>
+
+#include <asm/mach-jz4740/base.h>
+#include <asm/mach-jz4740/timer.h>
+
+static void jz4740_halt(void)
+{
+        while (1) {
+                __asm__(".set push;\n"
+                        ".set mips3;\n"
+                        "wait;\n"
+                        ".set pop;\n"
+                );
+        }
+}
+
+#define JZ_REG_WDT_DATA 0x00
+#define JZ_REG_WDT_COUNTER_ENABLE 0x04
+#define JZ_REG_WDT_COUNTER 0x08
+#define JZ_REG_WDT_CTRL 0x0c
+
+static void jz4740_restart(char *command)
+{
+        void __iomem *wdt_base = ioremap(JZ4740_WDT_BASE_ADDR, 0x0f);
+
+        jz4740_timer_enable_watchdog();
+
+        writeb(0, wdt_base + JZ_REG_WDT_COUNTER_ENABLE);
+
+        writew(0, wdt_base + JZ_REG_WDT_COUNTER);
+        writew(0, wdt_base + JZ_REG_WDT_DATA);
+        writew(BIT(2), wdt_base + JZ_REG_WDT_CTRL);
+
+        writeb(1, wdt_base + JZ_REG_WDT_COUNTER_ENABLE);
+        jz4740_halt();
+}
+
+#define JZ_REG_RTC_CTRL         0x00
+#define JZ_REG_RTC_HIBERNATE    0x20
+
+#define JZ_RTC_CTRL_WRDY        BIT(7)
+
+static void jz4740_power_off(void)
+{
+        void __iomem *rtc_base = ioremap(JZ4740_RTC_BASE_ADDR, 0x24);
+        uint32_t ctrl;
+
+        do {
+                ctrl = readl(rtc_base + JZ_REG_RTC_CTRL);
+        } while (!(ctrl & JZ_RTC_CTRL_WRDY));
+
+        writel(1, rtc_base + JZ_REG_RTC_HIBERNATE);
+        jz4740_halt();
+}
+
+void jz4740_reset_init(void)
+{
+        _machine_restart = jz4740_restart;
+        _machine_halt = jz4740_halt;
+        pm_power_off = jz4740_power_off;
+}
diff --git a/arch/mips/jz4740/reset.h b/arch/mips/jz4740/reset.h
new file mode 100644
index 000000000000..5202ab4ad9db
--- /dev/null
+++ b/arch/mips/jz4740/reset.h
@@ -0,0 +1,6 @@
+#ifndef __MIPS_JZ4740_RESET_H__
+#define __MIPS_JZ4740_RESET_H__
+
+extern void jz4740_reset_init(void);
+
+#endif
diff --git a/arch/mips/jz4740/serial.c b/arch/mips/jz4740/serial.c
new file mode 100644
index 000000000000..d23de45826d1
--- /dev/null
+++ b/arch/mips/jz4740/serial.c
@@ -0,0 +1,33 @@
+/*
+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ *  JZ4740 serial support
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#include <linux/io.h>
+#include <linux/serial_core.h>
+#include <linux/serial_reg.h>
+
+void jz4740_serial_out(struct uart_port *p, int offset, int value)
+{
+        switch (offset) {
+        case UART_FCR:
+                value |= 0x10; /* Enable uart module */
+                break;
+        case UART_IER:
+                value |= (value & 0x4) << 2;
+                break;
+        default:
+                break;
+        }
+        writeb(value, p->membase + (offset << p->regshift));
+}
diff --git a/arch/mips/jz4740/serial.h b/arch/mips/jz4740/serial.h
new file mode 100644
index 000000000000..b9fe3ade0289
--- /dev/null
+++ b/arch/mips/jz4740/serial.h
@@ -0,0 +1,20 @@
+/*
+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ *  JZ4740 serial support
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __MIPS_JZ4740_SERIAL_H__
+
+void jz4740_serial_out(struct uart_port *p, int offset, int value);
+
+#endif
diff --git a/arch/mips/jz4740/setup.c b/arch/mips/jz4740/setup.c
new file mode 100644
index 000000000000..6a9e14dab91e
--- /dev/null
+++ b/arch/mips/jz4740/setup.c
@@ -0,0 +1,29 @@
+/*
+ *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
+ *  JZ4740 setup code
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under  the terms of the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+
+#include "reset.h"
+
+void __init plat_mem_setup(void)
+{
+        jz4740_reset_init();
+}
+
+const char *get_system_type(void)
+{
+        return "JZ4740";
+}
diff --git a/arch/mips/jz4740/time.c b/arch/mips/jz4740/time.c
new file mode 100644
index 000000000000..fe01678d94fd
--- /dev/null
+++ b/arch/mips/jz4740/time.c
@@ -0,0 +1,144 @@
+/*
+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ *  JZ4740 platform time support
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under  the terms of the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/time.h>
+
+#include <linux/clockchips.h>
+
+#include <asm/mach-jz4740/irq.h>
+#include <asm/time.h>
+
+#include "clock.h"
+#include "timer.h"
+
+#define TIMER_CLOCKEVENT 0
+#define TIMER_CLOCKSOURCE 1
+
+static uint16_t jz4740_jiffies_per_tick;
+
+static cycle_t jz4740_clocksource_read(struct clocksource *cs)
+{
+        return jz4740_timer_get_count(TIMER_CLOCKSOURCE);
+}
+
+static struct clocksource jz4740_clocksource = {
+        .name = "jz4740-timer",
+        .rating = 200,
+        .read = jz4740_clocksource_read,
+        .mask = CLOCKSOURCE_MASK(16),
+        .flags = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+static irqreturn_t jz4740_clockevent_irq(int irq, void *devid)
+{
+        struct clock_event_device *cd = devid;
+
+        jz4740_timer_ack_full(TIMER_CLOCKEVENT);
+
+        if (cd->mode != CLOCK_EVT_MODE_PERIODIC)
+                jz4740_timer_disable(TIMER_CLOCKEVENT);
+
+        cd->event_handler(cd);
+
+        return IRQ_HANDLED;
+}
+
+static void jz4740_clockevent_set_mode(enum clock_event_mode mode,
+        struct clock_event_device *cd)
+{
+        switch (mode) {
+        case CLOCK_EVT_MODE_PERIODIC:
+                jz4740_timer_set_count(TIMER_CLOCKEVENT, 0);
+                jz4740_timer_set_period(TIMER_CLOCKEVENT, jz4740_jiffies_per_tick);
+        case CLOCK_EVT_MODE_RESUME:
+                jz4740_timer_irq_full_enable(TIMER_CLOCKEVENT);
+                jz4740_timer_enable(TIMER_CLOCKEVENT);
+                break;
+        case CLOCK_EVT_MODE_ONESHOT:
+        case CLOCK_EVT_MODE_SHUTDOWN:
+                jz4740_timer_disable(TIMER_CLOCKEVENT);
+                break;
+        default:
+                break;
+        }
+}
+
+static int jz4740_clockevent_set_next(unsigned long evt,
+        struct clock_event_device *cd)
+{
+        jz4740_timer_set_count(TIMER_CLOCKEVENT, 0);
+        jz4740_timer_set_period(TIMER_CLOCKEVENT, evt);
+        jz4740_timer_enable(TIMER_CLOCKEVENT);
+
+        return 0;
+}
+
+static struct clock_event_device jz4740_clockevent = {
+        .name = "jz4740-timer",
+        .features = CLOCK_EVT_FEAT_PERIODIC,
+        .set_next_event = jz4740_clockevent_set_next,
+        .set_mode = jz4740_clockevent_set_mode,
+        .rating = 200,
+        .irq = JZ4740_IRQ_TCU0,
+};
+
+static struct irqaction timer_irqaction = {
+        .handler        = jz4740_clockevent_irq,
+        .flags          = IRQF_PERCPU | IRQF_TIMER,
+        .name           = "jz4740-timerirq",
+        .dev_id         = &jz4740_clockevent,
+};
+
+void __init plat_time_init(void)
+{
+        int ret;
+        uint32_t clk_rate;
+        uint16_t ctrl;
+
+        jz4740_timer_init();
+
+        clk_rate = jz4740_clock_bdata.ext_rate >> 4;
+        jz4740_jiffies_per_tick = DIV_ROUND_CLOSEST(clk_rate, HZ);
+
+        clockevent_set_clock(&jz4740_clockevent, clk_rate);
+        jz4740_clockevent.min_delta_ns = clockevent_delta2ns(100, &jz4740_clockevent);
+        jz4740_clockevent.max_delta_ns = clockevent_delta2ns(0xffff, &jz4740_clockevent);
+        jz4740_clockevent.cpumask = cpumask_of(0);
+
+        clockevents_register_device(&jz4740_clockevent);
+
+        clocksource_set_clock(&jz4740_clocksource, clk_rate);
+        ret = clocksource_register(&jz4740_clocksource);
+
+        if (ret)
+                printk(KERN_ERR "Failed to register clocksource: %d\n", ret);
+
+        setup_irq(JZ4740_IRQ_TCU0, &timer_irqaction);
+
+        ctrl = JZ_TIMER_CTRL_PRESCALE_16 | JZ_TIMER_CTRL_SRC_EXT;
+
+        jz4740_timer_set_ctrl(TIMER_CLOCKEVENT, ctrl);
+        jz4740_timer_set_ctrl(TIMER_CLOCKSOURCE, ctrl);
+
+        jz4740_timer_set_period(TIMER_CLOCKEVENT, jz4740_jiffies_per_tick);
+        jz4740_timer_irq_full_enable(TIMER_CLOCKEVENT);
+
+        jz4740_timer_set_period(TIMER_CLOCKSOURCE, 0xffff);
+
+        jz4740_timer_enable(TIMER_CLOCKEVENT);
+        jz4740_timer_enable(TIMER_CLOCKSOURCE);
+}
diff --git a/arch/mips/jz4740/timer.c b/arch/mips/jz4740/timer.c
new file mode 100644
index 000000000000..b2c015129055
--- /dev/null
+++ b/arch/mips/jz4740/timer.c
@@ -0,0 +1,48 @@
+/*
+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ *  JZ4740 platform timer support
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under  the terms of the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+
+#include "timer.h"
+
+#include <asm/mach-jz4740/base.h>
+
+void __iomem *jz4740_timer_base;
+
+void jz4740_timer_enable_watchdog(void)
+{
+        writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR);
+}
+
+void jz4740_timer_disable_watchdog(void)
+{
+        writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
+}
+
+void __init jz4740_timer_init(void)
+{
+        jz4740_timer_base = ioremap(JZ4740_TCU_BASE_ADDR, 0x100);
+
+        if (!jz4740_timer_base)
+                panic("Failed to ioremap timer registers");
+
+        /* Disable all timer clocks except for those used as system timers */
+        writel(0x000100fc, jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
+
+        /* Timer irqs are unmasked by default, mask them */
+        writel(0x00ff00ff, jz4740_timer_base + JZ_REG_TIMER_MASK_SET);
+}
diff --git a/arch/mips/jz4740/timer.h b/arch/mips/jz4740/timer.h
new file mode 100644
index 000000000000..fca3994f2e6d
--- /dev/null
+++ b/arch/mips/jz4740/timer.h
@@ -0,0 +1,136 @@
+/*
+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ *  JZ4740 platform timer support
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under  the terms of the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __MIPS_JZ4740_TIMER_H__
+#define __MIPS_JZ4740_TIMER_H__
+
+#include <linux/module.h>
+#include <linux/io.h>
+
+#define JZ_REG_TIMER_STOP               0x0C
+#define JZ_REG_TIMER_STOP_SET           0x1C
+#define JZ_REG_TIMER_STOP_CLEAR         0x2C
+#define JZ_REG_TIMER_ENABLE             0x00
+#define JZ_REG_TIMER_ENABLE_SET         0x04
+#define JZ_REG_TIMER_ENABLE_CLEAR       0x08
+#define JZ_REG_TIMER_FLAG               0x10
+#define JZ_REG_TIMER_FLAG_SET           0x14
+#define JZ_REG_TIMER_FLAG_CLEAR         0x18
+#define JZ_REG_TIMER_MASK               0x20
+#define JZ_REG_TIMER_MASK_SET           0x24
+#define JZ_REG_TIMER_MASK_CLEAR         0x28
+
+#define JZ_REG_TIMER_DFR(x) (((x) * 0x10) + 0x30)
+#define JZ_REG_TIMER_DHR(x) (((x) * 0x10) + 0x34)
+#define JZ_REG_TIMER_CNT(x) (((x) * 0x10) + 0x38)
+#define JZ_REG_TIMER_CTRL(x) (((x) * 0x10) + 0x3C)
+
+#define JZ_TIMER_IRQ_HALF(x) BIT((x) + 0x10)
+#define JZ_TIMER_IRQ_FULL(x) BIT(x)
+
+#define JZ_TIMER_CTRL_PWM_ABBRUPT_SHUTDOWN      BIT(9)
+#define JZ_TIMER_CTRL_PWM_ACTIVE_LOW            BIT(8)
+#define JZ_TIMER_CTRL_PWM_ENABLE                BIT(7)
+#define JZ_TIMER_CTRL_PRESCALE_MASK             0x1c
+#define JZ_TIMER_CTRL_PRESCALE_OFFSET           0x3
+#define JZ_TIMER_CTRL_PRESCALE_1                (0 << 3)
+#define JZ_TIMER_CTRL_PRESCALE_4                (1 << 3)
+#define JZ_TIMER_CTRL_PRESCALE_16               (2 << 3)
+#define JZ_TIMER_CTRL_PRESCALE_64               (3 << 3)
+#define JZ_TIMER_CTRL_PRESCALE_256              (4 << 3)
+#define JZ_TIMER_CTRL_PRESCALE_1024             (5 << 3)
+
+#define JZ_TIMER_CTRL_PRESCALER(x) ((x) << JZ_TIMER_CTRL_PRESCALE_OFFSET)
+
+#define JZ_TIMER_CTRL_SRC_EXT           BIT(2)
+#define JZ_TIMER_CTRL_SRC_RTC           BIT(1)
+#define JZ_TIMER_CTRL_SRC_PCLK          BIT(0)
+
+extern void __iomem *jz4740_timer_base;
+void __init jz4740_timer_init(void);
+
+static inline void jz4740_timer_stop(unsigned int timer)
+{
+        writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
+}
+
+static inline void jz4740_timer_start(unsigned int timer)
+{
+        writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR);
+}
+
+static inline bool jz4740_timer_is_enabled(unsigned int timer)
+{
+        return readb(jz4740_timer_base + JZ_REG_TIMER_ENABLE) & BIT(timer);
+}
+
+static inline void jz4740_timer_enable(unsigned int timer)
+{
+        writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_SET);
+}
+
+static inline void jz4740_timer_disable(unsigned int timer)
+{
+        writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_CLEAR);
+}
+
+
+static inline void jz4740_timer_set_period(unsigned int timer, uint16_t period)
+{
+        writew(period, jz4740_timer_base + JZ_REG_TIMER_DFR(timer));
+}
+
+static inline void jz4740_timer_set_duty(unsigned int timer, uint16_t duty)
+{
+        writew(duty, jz4740_timer_base + JZ_REG_TIMER_DHR(timer));
+}
+
+static inline void jz4740_timer_set_count(unsigned int timer, uint16_t count)
+{
+        writew(count, jz4740_timer_base + JZ_REG_TIMER_CNT(timer));
+}
+
+static inline uint16_t jz4740_timer_get_count(unsigned int timer)
+{
+        return readw(jz4740_timer_base + JZ_REG_TIMER_CNT(timer));
+}
+
+static inline void jz4740_timer_ack_full(unsigned int timer)
+{
+        writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
+}
+
+static inline void jz4740_timer_irq_full_enable(unsigned int timer)
+{
+        writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
+        writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_CLEAR);
+}
+
+static inline void jz4740_timer_irq_full_disable(unsigned int timer)
+{
+        writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_SET);
+}
+
+static inline void jz4740_timer_set_ctrl(unsigned int timer, uint16_t ctrl)
+{
+        writew(ctrl, jz4740_timer_base + JZ_REG_TIMER_CTRL(timer));
+}
+
+static inline uint16_t jz4740_timer_get_ctrl(unsigned int timer)
+{
+        return readw(jz4740_timer_base + JZ_REG_TIMER_CTRL(timer));
+}
+
+#endif
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index 7a6ac501cbb5..06f848299785 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -76,6 +76,7 @@ obj-$(CONFIG_IRQ_TXX9)		+= irq_txx9.o
 obj-$(CONFIG_IRQ_GT641XX)       += irq-gt641xx.o
 obj-$(CONFIG_IRQ_GIC)           += irq-gic.o
 
+obj-$(CONFIG_KPROBES)           += kprobes.o
 obj-$(CONFIG_32BIT)             += scall32-o32.o
 obj-$(CONFIG_64BIT)             += scall64-64.o
 obj-$(CONFIG_MIPS32_COMPAT)     += linux32.o ptrace32.o signal32.o
@@ -101,6 +102,4 @@ obj-$(CONFIG_HAVE_STD_PC_SERIAL_PORT)	+= 8250-platform.o
 
 obj-$(CONFIG_MIPS_CPUFREQ)      += cpufreq/
 
-EXTRA_CFLAGS += -Werror
-
 CPPFLAGS_vmlinux.lds            := $(KBUILD_CFLAGS)
diff --git a/arch/mips/kernel/asm-offsets.c b/arch/mips/kernel/asm-offsets.c
index ca6c83218caa..6b30fb2caa67 100644
--- a/arch/mips/kernel/asm-offsets.c
+++ b/arch/mips/kernel/asm-offsets.c
@@ -126,7 +126,6 @@ void output_thread_defines(void)
                thread.cp0_baduaddr);
         OFFSET(THREAD_ECODE, task_struct, \
                thread.error_code);
-        OFFSET(THREAD_TRAPNO, task_struct, thread.trap_no);
         OFFSET(THREAD_TRAMP, task_struct, \
                thread.irix_trampoline);
         OFFSET(THREAD_OLDCTX, task_struct, \
diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c
index 0b2450ceb13f..2a4d50ff5e2c 100644
--- a/arch/mips/kernel/cevt-r4k.c
+++ b/arch/mips/kernel/cevt-r4k.c
@@ -163,7 +163,6 @@ int c0_compare_int_usable(void)
 
 int __cpuinit r4k_clockevent_init(void)
 {
-        uint64_t mips_freq = mips_hpt_frequency;
         unsigned int cpu = smp_processor_id();
         struct clock_event_device *cd;
         unsigned int irq;
@@ -188,9 +187,9 @@ int __cpuinit r4k_clockevent_init(void)
         cd->name                = "MIPS";
         cd->features            = CLOCK_EVT_FEAT_ONESHOT;
 
+        clockevent_set_clock(cd, mips_hpt_frequency);
+
         /* Calculate the min / max delta */
-        cd->mult        = div_sc((unsigned long) mips_freq, NSEC_PER_SEC, 32);
-        cd->shift               = 32;
         cd->max_delta_ns        = clockevent_delta2ns(0x7fffffff, cd);
         cd->min_delta_ns        = clockevent_delta2ns(0x300, cd);
 
diff --git a/arch/mips/kernel/cpu-bugs64.c b/arch/mips/kernel/cpu-bugs64.c
index 408d0a07b3a3..b8bb8ba60869 100644
--- a/arch/mips/kernel/cpu-bugs64.c
+++ b/arch/mips/kernel/cpu-bugs64.c
@@ -239,7 +239,7 @@ static inline void check_daddi(void)
         panic(bug64hit, !DADDI_WAR ? daddiwar : nowar);
 }
 
-int daddiu_bug __cpuinitdata = -1;
+int daddiu_bug  = -1;
 
 static inline void check_daddiu(void)
 {
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 3562b854f2cd..b1b304ea2128 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -187,6 +187,7 @@ void __init check_wait(void)
         case CPU_BCM6358:
         case CPU_CAVIUM_OCTEON:
         case CPU_CAVIUM_OCTEON_PLUS:
+        case CPU_JZRISC:
                 cpu_wait = r4k_wait;
                 break;
 
@@ -760,6 +761,9 @@ static void __cpuinit decode_configs(struct cpuinfo_mips *c)
                 ok = decode_config4(c);
 
         mips_probe_watch_registers(c);
+
+        if (cpu_has_mips_r2)
+                c->core = read_c0_ebase() & 0x3ff;
 }
 
 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
@@ -956,6 +960,22 @@ platform:
         }
 }
 
+static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
+{
+        decode_configs(c);
+        /* JZRISC does not implement the CP0 counter. */
+        c->options &= ~MIPS_CPU_COUNTER;
+        switch (c->processor_id & 0xff00) {
+        case PRID_IMP_JZRISC:
+                c->cputype = CPU_JZRISC;
+                __cpu_name[cpu] = "Ingenic JZRISC";
+                break;
+        default:
+                panic("Unknown Ingenic Processor ID!");
+                break;
+        }
+}
+
 const char *__cpu_name[NR_CPUS];
 const char *__elf_platform;
 
@@ -994,6 +1014,9 @@ __cpuinit void cpu_probe(void)
         case PRID_COMP_CAVIUM:
                 cpu_probe_cavium(c, cpu);
                 break;
+        case PRID_COMP_INGENIC:
+                cpu_probe_ingenic(c, cpu);
+                break;
         }
 
         BUG_ON(!__cpu_name[cpu]);
diff --git a/arch/mips/kernel/kprobes.c b/arch/mips/kernel/kprobes.c
new file mode 100644
index 000000000000..ee28683fc2ac
--- /dev/null
+++ b/arch/mips/kernel/kprobes.c
@@ -0,0 +1,557 @@
+/*
+ *  Kernel Probes (KProbes)
+ *  arch/mips/kernel/kprobes.c
+ *
+ *  Copyright 2006 Sony Corp.
+ *  Copyright 2010 Cavium Networks
+ *
+ *  Some portions copied from the powerpc version.
+ *
+ *   Copyright (C) IBM Corporation, 2002, 2004
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; version 2 of the License.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/kprobes.h>
+#include <linux/preempt.h>
+#include <linux/kdebug.h>
+#include <linux/slab.h>
+
+#include <asm/ptrace.h>
+#include <asm/break.h>
+#include <asm/inst.h>
+
+static const union mips_instruction breakpoint_insn = {
+        .b_format = {
+                .opcode = spec_op,
+                .code = BRK_KPROBE_BP,
+                .func = break_op
+        }
+};
+
+static const union mips_instruction breakpoint2_insn = {
+        .b_format = {
+                .opcode = spec_op,
+                .code = BRK_KPROBE_SSTEPBP,
+                .func = break_op
+        }
+};
+
+DEFINE_PER_CPU(struct kprobe *, current_kprobe);
+DEFINE_PER_CPU(struct kprobe_ctlblk, kprobe_ctlblk);
+
+static int __kprobes insn_has_delayslot(union mips_instruction insn)
+{
+        switch (insn.i_format.opcode) {
+
+                /*
+                 * This group contains:
+                 * jr and jalr are in r_format format.
+                 */
+        case spec_op:
+                switch (insn.r_format.func) {
+                case jr_op:
+                case jalr_op:
+                        break;
+                default:
+                        goto insn_ok;
+                }
+
+                /*
+                 * This group contains:
+                 * bltz_op, bgez_op, bltzl_op, bgezl_op,
+                 * bltzal_op, bgezal_op, bltzall_op, bgezall_op.
+                 */
+        case bcond_op:
+
+                /*
+                 * These are unconditional and in j_format.
+                 */
+        case jal_op:
+        case j_op:
+
+                /*
+                 * These are conditional and in i_format.
+                 */
+        case beq_op:
+        case beql_op:
+        case bne_op:
+        case bnel_op:
+        case blez_op:
+        case blezl_op:
+        case bgtz_op:
+        case bgtzl_op:
+
+                /*
+                 * These are the FPA/cp1 branch instructions.
+                 */
+        case cop1_op:
+
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+        case lwc2_op: /* This is bbit0 on Octeon */
+        case ldc2_op: /* This is bbit032 on Octeon */
+        case swc2_op: /* This is bbit1 on Octeon */
+        case sdc2_op: /* This is bbit132 on Octeon */
+#endif
+                return 1;
+        default:
+                break;
+        }
+insn_ok:
+        return 0;
+}
+
+int __kprobes arch_prepare_kprobe(struct kprobe *p)
+{
+        union mips_instruction insn;
+        union mips_instruction prev_insn;
+        int ret = 0;
+
+        prev_insn = p->addr[-1];
+        insn = p->addr[0];
+
+        if (insn_has_delayslot(insn) || insn_has_delayslot(prev_insn)) {
+                pr_notice("Kprobes for branch and jump instructions are not supported\n");
+                ret = -EINVAL;
+                goto out;
+        }
+
+        /* insn: must be on special executable page on mips. */
+        p->ainsn.insn = get_insn_slot();
+        if (!p->ainsn.insn) {
+                ret = -ENOMEM;
+                goto out;
+        }
+
+        /*
+         * In the kprobe->ainsn.insn[] array we store the original
+         * instruction at index zero and a break trap instruction at
+         * index one.
+         */
+
+        memcpy(&p->ainsn.insn[0], p->addr, sizeof(kprobe_opcode_t));
+        p->ainsn.insn[1] = breakpoint2_insn;
+        p->opcode = *p->addr;
+
+out:
+        return ret;
+}
+
+void __kprobes arch_arm_kprobe(struct kprobe *p)
+{
+        *p->addr = breakpoint_insn;
+        flush_insn_slot(p);
+}
+
+void __kprobes arch_disarm_kprobe(struct kprobe *p)
+{
+        *p->addr = p->opcode;
+        flush_insn_slot(p);
+}
+
+void __kprobes arch_remove_kprobe(struct kprobe *p)
+{
+        free_insn_slot(p->ainsn.insn, 0);
+}
+
+static void save_previous_kprobe(struct kprobe_ctlblk *kcb)
+{
+        kcb->prev_kprobe.kp = kprobe_running();
+        kcb->prev_kprobe.status = kcb->kprobe_status;
+        kcb->prev_kprobe.old_SR = kcb->kprobe_old_SR;
+        kcb->prev_kprobe.saved_SR = kcb->kprobe_saved_SR;
+        kcb->prev_kprobe.saved_epc = kcb->kprobe_saved_epc;
+}
+
+static void restore_previous_kprobe(struct kprobe_ctlblk *kcb)
+{
+        __get_cpu_var(current_kprobe) = kcb->prev_kprobe.kp;
+        kcb->kprobe_status = kcb->prev_kprobe.status;
+        kcb->kprobe_old_SR = kcb->prev_kprobe.old_SR;
+        kcb->kprobe_saved_SR = kcb->prev_kprobe.saved_SR;
+        kcb->kprobe_saved_epc = kcb->prev_kprobe.saved_epc;
+}
+
+static void set_current_kprobe(struct kprobe *p, struct pt_regs *regs,
+                               struct kprobe_ctlblk *kcb)
+{
+        __get_cpu_var(current_kprobe) = p;
+        kcb->kprobe_saved_SR = kcb->kprobe_old_SR = (regs->cp0_status & ST0_IE);
+        kcb->kprobe_saved_epc = regs->cp0_epc;
+}
+
+static void prepare_singlestep(struct kprobe *p, struct pt_regs *regs)
+{
+        regs->cp0_status &= ~ST0_IE;
+
+        /* single step inline if the instruction is a break */
+        if (p->opcode.word == breakpoint_insn.word ||
+            p->opcode.word == breakpoint2_insn.word)
+                regs->cp0_epc = (unsigned long)p->addr;
+        else
+                regs->cp0_epc = (unsigned long)&p->ainsn.insn[0];
+}
+
+static int __kprobes kprobe_handler(struct pt_regs *regs)
+{
+        struct kprobe *p;
+        int ret = 0;
+        kprobe_opcode_t *addr;
+        struct kprobe_ctlblk *kcb;
+
+        addr = (kprobe_opcode_t *) regs->cp0_epc;
+
+        /*
+         * We don't want to be preempted for the entire
+         * duration of kprobe processing
+         */
+        preempt_disable();
+        kcb = get_kprobe_ctlblk();
+
+        /* Check we're not actually recursing */
+        if (kprobe_running()) {
+                p = get_kprobe(addr);
+                if (p) {
+                        if (kcb->kprobe_status == KPROBE_HIT_SS &&
+                            p->ainsn.insn->word == breakpoint_insn.word) {
+                                regs->cp0_status &= ~ST0_IE;
+                                regs->cp0_status |= kcb->kprobe_saved_SR;
+                                goto no_kprobe;
+                        }
+                        /*
+                         * We have reentered the kprobe_handler(), since
+                         * another probe was hit while within the handler.
+                         * We here save the original kprobes variables and
+                         * just single step on the instruction of the new probe
+                         * without calling any user handlers.
+                         */
+                        save_previous_kprobe(kcb);
+                        set_current_kprobe(p, regs, kcb);
+                        kprobes_inc_nmissed_count(p);
+                        prepare_singlestep(p, regs);
+                        kcb->kprobe_status = KPROBE_REENTER;
+                        return 1;
+                } else {
+                        if (addr->word != breakpoint_insn.word) {
+                                /*
+                                 * The breakpoint instruction was removed by
+                                 * another cpu right after we hit, no further
+                                 * handling of this interrupt is appropriate
+                                 */
+                                ret = 1;
+                                goto no_kprobe;
+                        }
+                        p = __get_cpu_var(current_kprobe);
+                        if (p->break_handler && p->break_handler(p, regs))
+                                goto ss_probe;
+                }
+                goto no_kprobe;
+        }
+
+        p = get_kprobe(addr);
+        if (!p) {
+                if (addr->word != breakpoint_insn.word) {
+                        /*
+                         * The breakpoint instruction was removed right
+                         * after we hit it.  Another cpu has removed
+                         * either a probepoint or a debugger breakpoint
+                         * at this address.  In either case, no further
+                         * handling of this interrupt is appropriate.
+                         */
+                        ret = 1;
+                }
+                /* Not one of ours: let kernel handle it */
+                goto no_kprobe;
+        }
+
+        set_current_kprobe(p, regs, kcb);
+        kcb->kprobe_status = KPROBE_HIT_ACTIVE;
+
+        if (p->pre_handler && p->pre_handler(p, regs)) {
+                /* handler has already set things up, so skip ss setup */
+                return 1;
+        }
+
+ss_probe:
+        prepare_singlestep(p, regs);
+        kcb->kprobe_status = KPROBE_HIT_SS;
+        return 1;
+
+no_kprobe:
+        preempt_enable_no_resched();
+        return ret;
+
+}
+
+/*
+ * Called after single-stepping.  p->addr is the address of the
+ * instruction whose first byte has been replaced by the "break 0"
+ * instruction.  To avoid the SMP problems that can occur when we
+ * temporarily put back the original opcode to single-step, we
+ * single-stepped a copy of the instruction.  The address of this
+ * copy is p->ainsn.insn.
+ *
+ * This function prepares to return from the post-single-step
+ * breakpoint trap.
+ */
+static void __kprobes resume_execution(struct kprobe *p,
+                                       struct pt_regs *regs,
+                                       struct kprobe_ctlblk *kcb)
+{
+        unsigned long orig_epc = kcb->kprobe_saved_epc;
+        regs->cp0_epc = orig_epc + 4;
+}
+
+static inline int post_kprobe_handler(struct pt_regs *regs)
+{
+        struct kprobe *cur = kprobe_running();
+        struct kprobe_ctlblk *kcb = get_kprobe_ctlblk();
+
+        if (!cur)
+                return 0;
+
+        if ((kcb->kprobe_status != KPROBE_REENTER) && cur->post_handler) {
+                kcb->kprobe_status = KPROBE_HIT_SSDONE;
+                cur->post_handler(cur, regs, 0);
+        }
+
+        resume_execution(cur, regs, kcb);
+
+        regs->cp0_status |= kcb->kprobe_saved_SR;
+
+        /* Restore back the original saved kprobes variables and continue. */
+        if (kcb->kprobe_status == KPROBE_REENTER) {
+                restore_previous_kprobe(kcb);
+                goto out;
+        }
+        reset_current_kprobe();
+out:
+        preempt_enable_no_resched();
+
+        return 1;
+}
+
+static inline int kprobe_fault_handler(struct pt_regs *regs, int trapnr)
+{
+        struct kprobe *cur = kprobe_running();
+        struct kprobe_ctlblk *kcb = get_kprobe_ctlblk();
+
+        if (cur->fault_handler && cur->fault_handler(cur, regs, trapnr))
+                return 1;
+
+        if (kcb->kprobe_status & KPROBE_HIT_SS) {
+                resume_execution(cur, regs, kcb);
+                regs->cp0_status |= kcb->kprobe_old_SR;
+
+                reset_current_kprobe();
+                preempt_enable_no_resched();
+        }
+        return 0;
+}
+
+/*
+ * Wrapper routine for handling exceptions.
+ */
+int __kprobes kprobe_exceptions_notify(struct notifier_block *self,
+                                       unsigned long val, void *data)
+{
+
+        struct die_args *args = (struct die_args *)data;
+        int ret = NOTIFY_DONE;
+
+        switch (val) {
+        case DIE_BREAK:
+                if (kprobe_handler(args->regs))
+                        ret = NOTIFY_STOP;
+                break;
+        case DIE_SSTEPBP:
+                if (post_kprobe_handler(args->regs))
+                        ret = NOTIFY_STOP;
+                break;
+
+        case DIE_PAGE_FAULT:
+                /* kprobe_running() needs smp_processor_id() */
+                preempt_disable();
+
+                if (kprobe_running()
+                    && kprobe_fault_handler(args->regs, args->trapnr))
+                        ret = NOTIFY_STOP;
+                preempt_enable();
+                break;
+        default:
+                break;
+        }
+        return ret;
+}
+
+int __kprobes setjmp_pre_handler(struct kprobe *p, struct pt_regs *regs)
+{
+        struct jprobe *jp = container_of(p, struct jprobe, kp);
+        struct kprobe_ctlblk *kcb = get_kprobe_ctlblk();
+
+        kcb->jprobe_saved_regs = *regs;
+        kcb->jprobe_saved_sp = regs->regs[29];
+
+        memcpy(kcb->jprobes_stack, (void *)kcb->jprobe_saved_sp,
+               MIN_JPROBES_STACK_SIZE(kcb->jprobe_saved_sp));
+
+        regs->cp0_epc = (unsigned long)(jp->entry);
+
+        return 1;
+}
+
+/* Defined in the inline asm below. */
+void jprobe_return_end(void);
+
+void __kprobes jprobe_return(void)
+{
+        /* Assembler quirk necessitates this '0,code' business.  */
+        asm volatile(
+                "break 0,%0\n\t"
+                ".globl jprobe_return_end\n"
+                "jprobe_return_end:\n"
+                : : "n" (BRK_KPROBE_BP) : "memory");
+}
+
+int __kprobes longjmp_break_handler(struct kprobe *p, struct pt_regs *regs)
+{
+        struct kprobe_ctlblk *kcb = get_kprobe_ctlblk();
+
+        if (regs->cp0_epc >= (unsigned long)jprobe_return &&
+            regs->cp0_epc <= (unsigned long)jprobe_return_end) {
+                *regs = kcb->jprobe_saved_regs;
+                memcpy((void *)kcb->jprobe_saved_sp, kcb->jprobes_stack,
+                       MIN_JPROBES_STACK_SIZE(kcb->jprobe_saved_sp));
+                preempt_enable_no_resched();
+
+                return 1;
+        }
+        return 0;
+}
+
+/*
+ * Function return probe trampoline:
+ *      - init_kprobes() establishes a probepoint here
+ *      - When the probed function returns, this probe causes the
+ *        handlers to fire
+ */
+static void __used kretprobe_trampoline_holder(void)
+{
+        asm volatile(
+                ".set push\n\t"
+                /* Keep the assembler from reordering and placing JR here. */
+                ".set noreorder\n\t"
+                "nop\n\t"
+                ".global kretprobe_trampoline\n"
+                "kretprobe_trampoline:\n\t"
+                "nop\n\t"
+                ".set pop"
+                : : : "memory");
+}
+
+void kretprobe_trampoline(void);
+
+void __kprobes arch_prepare_kretprobe(struct kretprobe_instance *ri,
+                                      struct pt_regs *regs)
+{
+        ri->ret_addr = (kprobe_opcode_t *) regs->regs[31];
+
+        /* Replace the return addr with trampoline addr */
+        regs->regs[31] = (unsigned long)kretprobe_trampoline;
+}
+
+/*
+ * Called when the probe at kretprobe trampoline is hit
+ */
+static int __kprobes trampoline_probe_handler(struct kprobe *p,
+                                                struct pt_regs *regs)
+{
+        struct kretprobe_instance *ri = NULL;
+        struct hlist_head *head, empty_rp;
+        struct hlist_node *node, *tmp;
+        unsigned long flags, orig_ret_address = 0;
+        unsigned long trampoline_address = (unsigned long)kretprobe_trampoline;
+
+        INIT_HLIST_HEAD(&empty_rp);
+        kretprobe_hash_lock(current, &head, &flags);
+
+        /*
+         * It is possible to have multiple instances associated with a given
+         * task either because an multiple functions in the call path
+         * have a return probe installed on them, and/or more than one return
+         * return probe was registered for a target function.
+         *
+         * We can handle this because:
+         *     - instances are always inserted at the head of the list
+         *     - when multiple return probes are registered for the same
+         *       function, the first instance's ret_addr will point to the
+         *       real return address, and all the rest will point to
+         *       kretprobe_trampoline
+         */
+        hlist_for_each_entry_safe(ri, node, tmp, head, hlist) {
+                if (ri->task != current)
+                        /* another task is sharing our hash bucket */
+                        continue;
+
+                if (ri->rp && ri->rp->handler)
+                        ri->rp->handler(ri, regs);
+
+                orig_ret_address = (unsigned long)ri->ret_addr;
+                recycle_rp_inst(ri, &empty_rp);
+
+                if (orig_ret_address != trampoline_address)
+                        /*
+                         * This is the real return address. Any other
+                         * instances associated with this task are for
+                         * other calls deeper on the call stack
+                         */
+                        break;
+        }
+
+        kretprobe_assert(ri, orig_ret_address, trampoline_address);
+        instruction_pointer(regs) = orig_ret_address;
+
+        reset_current_kprobe();
+        kretprobe_hash_unlock(current, &flags);
+        preempt_enable_no_resched();
+
+        hlist_for_each_entry_safe(ri, node, tmp, &empty_rp, hlist) {
+                hlist_del(&ri->hlist);
+                kfree(ri);
+        }
+        /*
+         * By returning a non-zero value, we are telling
+         * kprobe_handler() that we don't want the post_handler
+         * to run (and have re-enabled preemption)
+         */
+        return 1;
+}
+
+int __kprobes arch_trampoline_kprobe(struct kprobe *p)
+{
+        if (p->addr == (kprobe_opcode_t *)kretprobe_trampoline)
+                return 1;
+
+        return 0;
+}
+
+static struct kprobe trampoline_p = {
+        .addr = (kprobe_opcode_t *)kretprobe_trampoline,
+        .pre_handler = trampoline_probe_handler
+};
+
+int __init arch_init_kprobes(void)
+{
+        return register_kprobe(&trampoline_p);
+}
diff --git a/arch/mips/kernel/mcount.S b/arch/mips/kernel/mcount.S
index 6bfcb7a00ec6..4c968e7efb74 100644
--- a/arch/mips/kernel/mcount.S
+++ b/arch/mips/kernel/mcount.S
@@ -165,12 +165,12 @@ NESTED(ftrace_graph_caller, PT_SIZE, ra)
 
         /* arg3: Get frame pointer of current stack */
 #ifdef CONFIG_FRAME_POINTER
-         move   a2, fp
+        move    a2, fp
 #else /* ! CONFIG_FRAME_POINTER */
 #ifdef CONFIG_64BIT
-         PTR_LA a2, PT_SIZE(sp)
+        PTR_LA  a2, PT_SIZE(sp)
 #else
-         PTR_LA a2, (PT_SIZE+8)(sp)
+        PTR_LA  a2, (PT_SIZE+8)(sp)
 #endif
 #endif
 
diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S
index a4faceea9d88..a3d66137731a 100644
--- a/arch/mips/kernel/scall64-n32.S
+++ b/arch/mips/kernel/scall64-n32.S
@@ -400,22 +400,22 @@ EXPORT(sysn32_call_table)
         PTR     sys_ioprio_set
         PTR     sys_ioprio_get
         PTR     compat_sys_utimensat
-        PTR     compat_sys_signalfd             /* 5280 */
+        PTR     compat_sys_signalfd             /* 6280 */
         PTR     sys_ni_syscall
         PTR     sys_eventfd
         PTR     sys_fallocate
         PTR     sys_timerfd_create
-        PTR     compat_sys_timerfd_gettime      /* 5285 */
+        PTR     compat_sys_timerfd_gettime      /* 6285 */
         PTR     compat_sys_timerfd_settime
         PTR     sys_signalfd4
         PTR     sys_eventfd2
         PTR     sys_epoll_create1
-        PTR     sys_dup3                        /* 5290 */
+        PTR     sys_dup3                        /* 6290 */
         PTR     sys_pipe2
         PTR     sys_inotify_init1
         PTR     sys_preadv
         PTR     sys_pwritev
-        PTR     compat_sys_rt_tgsigqueueinfo    /* 5295 */
+        PTR     compat_sys_rt_tgsigqueueinfo    /* 6295 */
         PTR     sys_perf_event_open
         PTR     sys_accept4
         PTR     compat_sys_recvmmsg
diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c
index 6cdca1956b77..383aeb95cb49 100644
--- a/arch/mips/kernel/smp.c
+++ b/arch/mips/kernel/smp.c
@@ -47,8 +47,12 @@
 #endif /* CONFIG_MIPS_MT_SMTC */
 
 volatile cpumask_t cpu_callin_map;      /* Bitmask of started secondaries */
+
 int __cpu_number_map[NR_CPUS];          /* Map physical to logical */
+EXPORT_SYMBOL(__cpu_number_map);
+
 int __cpu_logical_map[NR_CPUS];         /* Map logical to physical */
+EXPORT_SYMBOL(__cpu_logical_map);
 
 /* Number of TCs (or siblings in Intel speak) per CPU core */
 int smp_num_siblings = 1;
diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
index a95dea5459c4..cfeb2c155896 100644
--- a/arch/mips/kernel/smtc.c
+++ b/arch/mips/kernel/smtc.c
@@ -975,8 +975,7 @@ void ipi_decode(struct smtc_ipi *pipi)
                         ipi_call_interrupt();
                         break;
                 default:
-                        printk("Impossible SMTC IPI Argument 0x%x\n",
-                                (int)arg_copy);
+                        printk("Impossible SMTC IPI Argument %p\n", arg_copy);
                         break;
                 }
                 break;
diff --git a/arch/mips/kernel/syscall.c b/arch/mips/kernel/syscall.c
index dd81b0f87518..58bab2ef257f 100644
--- a/arch/mips/kernel/syscall.c
+++ b/arch/mips/kernel/syscall.c
@@ -29,6 +29,8 @@
 #include <linux/ipc.h>
 #include <linux/uaccess.h>
 #include <linux/slab.h>
+#include <linux/random.h>
+#include <linux/elf.h>
 
 #include <asm/asm.h>
 #include <asm/branch.h>
@@ -116,7 +118,7 @@ unsigned long arch_get_unmapped_area(struct file *filp, unsigned long addr,
                     (!vmm || addr + len <= vmm->vm_start))
                         return addr;
         }
-        addr = TASK_UNMAPPED_BASE;
+        addr = current->mm->mmap_base;
         if (do_color_align)
                 addr = COLOUR_ALIGN(addr, pgoff);
         else
@@ -134,6 +136,51 @@ unsigned long arch_get_unmapped_area(struct file *filp, unsigned long addr,
         }
 }
 
+void arch_pick_mmap_layout(struct mm_struct *mm)
+{
+        unsigned long random_factor = 0UL;
+
+        if (current->flags & PF_RANDOMIZE) {
+                random_factor = get_random_int();
+                random_factor = random_factor << PAGE_SHIFT;
+                if (TASK_IS_32BIT_ADDR)
+                        random_factor &= 0xfffffful;
+                else
+                        random_factor &= 0xffffffful;
+        }
+
+        mm->mmap_base = TASK_UNMAPPED_BASE + random_factor;
+        mm->get_unmapped_area = arch_get_unmapped_area;
+        mm->unmap_area = arch_unmap_area;
+}
+
+static inline unsigned long brk_rnd(void)
+{
+        unsigned long rnd = get_random_int();
+
+        rnd = rnd << PAGE_SHIFT;
+        /* 8MB for 32bit, 256MB for 64bit */
+        if (TASK_IS_32BIT_ADDR)
+                rnd = rnd & 0x7ffffful;
+        else
+                rnd = rnd & 0xffffffful;
+
+        return rnd;
+}
+
+unsigned long arch_randomize_brk(struct mm_struct *mm)
+{
+        unsigned long base = mm->brk;
+        unsigned long ret;
+
+        ret = PAGE_ALIGN(base + brk_rnd());
+
+        if (ret < mm->brk)
+                return mm->brk;
+
+        return ret;
+}
+
 SYSCALL_DEFINE6(mips_mmap, unsigned long, addr, unsigned long, len,
         unsigned long, prot, unsigned long, flags, unsigned long,
         fd, off_t, offset)
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 852780868fb4..03ec0019032b 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -25,6 +25,7 @@
 #include <linux/ptrace.h>
 #include <linux/kgdb.h>
 #include <linux/kdebug.h>
+#include <linux/kprobes.h>
 #include <linux/notifier.h>
 #include <linux/kdb.h>
 
@@ -334,7 +335,7 @@ void show_regs(struct pt_regs *regs)
         __show_regs((struct pt_regs *)regs);
 }
 
-void show_registers(const struct pt_regs *regs)
+void show_registers(struct pt_regs *regs)
 {
         const int field = 2 * sizeof(unsigned long);
 
@@ -356,9 +357,14 @@ void show_registers(const struct pt_regs *regs)
         printk("\n");
 }
 
+static int regs_to_trapnr(struct pt_regs *regs)
+{
+        return (regs->cp0_cause >> 2) & 0x1f;
+}
+
 static DEFINE_SPINLOCK(die_lock);
 
-void __noreturn die(const char * str, struct pt_regs * regs)
+void __noreturn die(const char *str, struct pt_regs *regs)
 {
         static int die_counter;
         int sig = SIGSEGV;
@@ -366,7 +372,7 @@ void __noreturn die(const char * str, struct pt_regs * regs)
         unsigned long dvpret = dvpe();
 #endif /* CONFIG_MIPS_MT_SMTC */
 
-        notify_die(DIE_OOPS, str, (struct pt_regs *)regs, SIGSEGV, 0, 0);
+        notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs), SIGSEGV);
 
         console_verbose();
         spin_lock_irq(&die_lock);
@@ -375,7 +381,7 @@ void __noreturn die(const char * str, struct pt_regs * regs)
         mips_mt_regdump(dvpret);
 #endif /* CONFIG_MIPS_MT_SMTC */
 
-        if (notify_die(DIE_OOPS, str, regs, 0, current->thread.trap_no, SIGSEGV) == NOTIFY_STOP)
+        if (notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs), SIGSEGV) == NOTIFY_STOP)
                 sig = 0;
 
         printk("%s[#%d]:\n", str, ++die_counter);
@@ -449,7 +455,7 @@ asmlinkage void do_be(struct pt_regs *regs)
         printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
                data ? "Data" : "Instruction",
                field, regs->cp0_epc, field, regs->regs[31]);
-        if (notify_die(DIE_OOPS, "bus error", regs, SIGBUS, 0, 0)
+        if (notify_die(DIE_OOPS, "bus error", regs, 0, regs_to_trapnr(regs), SIGBUS)
             == NOTIFY_STOP)
                 return;
 
@@ -650,7 +656,7 @@ asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
 {
         siginfo_t info;
 
-        if (notify_die(DIE_FP, "FP exception", regs, SIGFPE, 0, 0)
+        if (notify_die(DIE_FP, "FP exception", regs, 0, regs_to_trapnr(regs), SIGFPE)
             == NOTIFY_STOP)
                 return;
         die_if_kernel("FP exception in kernel code", regs);
@@ -713,11 +719,11 @@ static void do_trap_or_bp(struct pt_regs *regs, unsigned int code,
         char b[40];
 
 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
-        if (kgdb_ll_trap(DIE_TRAP, str, regs, code, 0, 0) == NOTIFY_STOP)
+        if (kgdb_ll_trap(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
                 return;
 #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
 
-        if (notify_die(DIE_TRAP, str, regs, code, 0, 0) == NOTIFY_STOP)
+        if (notify_die(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
                 return;
 
         /*
@@ -783,6 +789,25 @@ asmlinkage void do_bp(struct pt_regs *regs)
         if (bcode >= (1 << 10))
                 bcode >>= 10;
 
+        /*
+         * notify the kprobe handlers, if instruction is likely to
+         * pertain to them.
+         */
+        switch (bcode) {
+        case BRK_KPROBE_BP:
+                if (notify_die(DIE_BREAK, "debug", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
+                        return;
+                else
+                        break;
+        case BRK_KPROBE_SSTEPBP:
+                if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
+                        return;
+                else
+                        break;
+        default:
+                break;
+        }
+
         do_trap_or_bp(regs, bcode, "Break");
         return;
 
@@ -815,7 +840,7 @@ asmlinkage void do_ri(struct pt_regs *regs)
         unsigned int opcode = 0;
         int status = -1;
 
-        if (notify_die(DIE_RI, "RI Fault", regs, SIGSEGV, 0, 0)
+        if (notify_die(DIE_RI, "RI Fault", regs, 0, regs_to_trapnr(regs), SIGILL)
             == NOTIFY_STOP)
                 return;
 
@@ -907,11 +932,6 @@ static int default_cu2_call(struct notifier_block *nfb, unsigned long action,
         return NOTIFY_OK;
 }
 
-static struct notifier_block default_cu2_notifier = {
-        .notifier_call  = default_cu2_call,
-        .priority       = 0x80000000,           /* Run last  */
-};
-
 asmlinkage void do_cpu(struct pt_regs *regs)
 {
         unsigned int __user *epc;
@@ -1734,5 +1754,5 @@ void __init trap_init(void)
 
         sort_extable(__start___dbe_table, __stop___dbe_table);
 
-        register_cu2_notifier(&default_cu2_notifier);
+        cu2_notifier(default_cu2_call, 0x80000000);     /* Run last  */
 }
diff --git a/arch/mips/lasat/Makefile b/arch/mips/lasat/Makefile
index 33791609fe99..9cc4e4db8b99 100644
--- a/arch/mips/lasat/Makefile
+++ b/arch/mips/lasat/Makefile
@@ -12,5 +12,3 @@ obj-$(CONFIG_PICVUE_PROC)	+= picvue_proc.o
 
 clean:
         make -C image clean
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/lasat/Platform b/arch/mips/lasat/Platform
new file mode 100644
index 000000000000..760252828bf1
--- /dev/null
+++ b/arch/mips/lasat/Platform
@@ -0,0 +1,7 @@
+#
+# LASAT platforms
+#
+platform-$(CONFIG_LASAT)        += lasat/
+cflags-$(CONFIG_LASAT)          +=                                      \
+                -I$(srctree)/arch/mips/include/asm/mach-lasat
+load-$(CONFIG_LASAT)            += 0xffffffff80000000
diff --git a/arch/mips/loongson/Platform b/arch/mips/loongson/Platform
new file mode 100644
index 000000000000..29692e5433b1
--- /dev/null
+++ b/arch/mips/loongson/Platform
@@ -0,0 +1,32 @@
+#
+# Loongson Processors' Support
+#
+
+# Only gcc >= 4.4 have Loongson specific support
+cflags-$(CONFIG_CPU_LOONGSON2)  += -Wa,--trap
+cflags-$(CONFIG_CPU_LOONGSON2E) += \
+        $(call cc-option,-march=loongson2e,-march=r4600)
+cflags-$(CONFIG_CPU_LOONGSON2F) += \
+        $(call cc-option,-march=loongson2f,-march=r4600)
+# Enable the workarounds for Loongson2f
+ifdef CONFIG_CPU_LOONGSON2F_WORKAROUNDS
+  ifeq ($(call as-option,-Wa$(comma)-mfix-loongson2f-nop,),)
+    $(error only binutils >= 2.20.2 have needed option -mfix-loongson2f-nop)
+  else
+    cflags-$(CONFIG_CPU_NOP_WORKAROUNDS) += -Wa$(comma)-mfix-loongson2f-nop
+  endif
+  ifeq ($(call as-option,-Wa$(comma)-mfix-loongson2f-jump,),)
+    $(error only binutils >= 2.20.2 have needed option -mfix-loongson2f-jump)
+  else
+    cflags-$(CONFIG_CPU_JUMP_WORKAROUNDS) += -Wa$(comma)-mfix-loongson2f-jump
+  endif
+endif
+
+#
+# Loongson Machines' Support
+#
+
+platform-$(CONFIG_MACH_LOONGSON) += loongson/
+cflags-$(CONFIG_MACH_LOONGSON) += -I$(srctree)/arch/mips/include/asm/mach-loongson -mno-branch-likely
+load-$(CONFIG_LEMOTE_FULOONG2E) += 0xffffffff80100000
+load-$(CONFIG_LEMOTE_MACH2F) += 0xffffffff80200000
diff --git a/arch/mips/loongson/common/cs5536/Makefile b/arch/mips/loongson/common/cs5536/Makefile
index 510d4cdc2378..f12e64007347 100644
--- a/arch/mips/loongson/common/cs5536/Makefile
+++ b/arch/mips/loongson/common/cs5536/Makefile
@@ -9,5 +9,3 @@ obj-$(CONFIG_CS5536) += cs5536_pci.o cs5536_ide.o cs5536_acc.o cs5536_ohci.o \
 # Enable cs5536 mfgpt Timer
 #
 obj-$(CONFIG_CS5536_MFGPT) += cs5536_mfgpt.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/loongson/common/irq.c b/arch/mips/loongson/common/irq.c
index 20e732831978..5897471dedca 100644
--- a/arch/mips/loongson/common/irq.c
+++ b/arch/mips/loongson/common/irq.c
@@ -21,19 +21,16 @@ void bonito_irqdispatch(void)
 
         /* workaround the IO dma problem: let cpu looping to allow DMA finish */
         int_status = LOONGSON_INTISR;
-        if (int_status & (1 << 10)) {
-                while (int_status & (1 << 10)) {
-                        udelay(1);
-                        int_status = LOONGSON_INTISR;
-                }
+        while (int_status & (1 << 10)) {
+                udelay(1);
+                int_status = LOONGSON_INTISR;
         }
 
         /* Get pending sources, masked by current enables */
         int_status = LOONGSON_INTISR & LOONGSON_INTEN;
 
-        if (int_status != 0) {
+        if (int_status) {
                 i = __ffs(int_status);
-                int_status &= ~(1 << i);
                 do_IRQ(LOONGSON_IRQ_BASE + i);
         }
 }
@@ -56,9 +53,6 @@ void __init arch_init_irq(void)
          */
         clear_c0_status(ST0_IM | ST0_BEV);
 
-        /* setting irq trigger mode */
-        set_irq_trigger_mode();
-
         /* no steer */
         LOONGSON_INTSTEER = 0;
 
diff --git a/arch/mips/loongson/fuloong-2e/Makefile b/arch/mips/loongson/fuloong-2e/Makefile
index 3aba5fcc09dc..b7622720c1ad 100644
--- a/arch/mips/loongson/fuloong-2e/Makefile
+++ b/arch/mips/loongson/fuloong-2e/Makefile
@@ -3,5 +3,3 @@
 #
 
 obj-y += irq.o reset.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/loongson/fuloong-2e/irq.c b/arch/mips/loongson/fuloong-2e/irq.c
index 320e9379bdd7..d61a04222b87 100644
--- a/arch/mips/loongson/fuloong-2e/irq.c
+++ b/arch/mips/loongson/fuloong-2e/irq.c
@@ -30,7 +30,7 @@ asmlinkage void mach_irq_dispatch(unsigned int pending)
         if (pending & CAUSEF_IP7)
                 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
         else if (pending & CAUSEF_IP6) /* perf counter loverflow */
-                do_IRQ(LOONGSON2_PERFCNT_IRQ);
+                do_perfcnt_IRQ();
         else if (pending & CAUSEF_IP5)
                 i8259_irqdispatch();
         else if (pending & CAUSEF_IP2)
@@ -44,13 +44,6 @@ static struct irqaction cascade_irqaction = {
         .name = "cascade",
 };
 
-void __init set_irq_trigger_mode(void)
-{
-        /* most bonito irq should be level triggered */
-        LOONGSON_INTEDGE = LOONGSON_ICU_SYSTEMERR | LOONGSON_ICU_MASTERERR |
-            LOONGSON_ICU_RETRYERR | LOONGSON_ICU_MBOXES;
-}
-
 void __init mach_init_irq(void)
 {
         /* init all controller
@@ -59,6 +52,10 @@ void __init mach_init_irq(void)
          *   32-63        ------> bonito irq
          */
 
+        /* most bonito irq should be level triggered */
+        LOONGSON_INTEDGE = LOONGSON_ICU_SYSTEMERR | LOONGSON_ICU_MASTERERR |
+            LOONGSON_ICU_RETRYERR | LOONGSON_ICU_MBOXES;
+
         /* Sets the first-level interrupt dispatcher. */
         mips_cpu_irq_init();
         init_i8259_irqs();
diff --git a/arch/mips/loongson/lemote-2f/irq.c b/arch/mips/loongson/lemote-2f/irq.c
index 1d8b4d28a058..081db102bb98 100644
--- a/arch/mips/loongson/lemote-2f/irq.c
+++ b/arch/mips/loongson/lemote-2f/irq.c
@@ -19,7 +19,6 @@
 #include <machine.h>
 
 #define LOONGSON_TIMER_IRQ      (MIPS_CPU_IRQ_BASE + 7) /* cpu timer */
-#define LOONGSON_PERFCNT_IRQ    (MIPS_CPU_IRQ_BASE + 6) /* cpu perf counter */
 #define LOONGSON_NORTH_BRIDGE_IRQ       (MIPS_CPU_IRQ_BASE + 6) /* bonito */
 #define LOONGSON_UART_IRQ       (MIPS_CPU_IRQ_BASE + 3) /* cpu serial port */
 #define LOONGSON_SOUTH_BRIDGE_IRQ       (MIPS_CPU_IRQ_BASE + 2) /* i8259 */
@@ -79,9 +78,7 @@ void mach_irq_dispatch(unsigned int pending)
         if (pending & CAUSEF_IP7)
                 do_IRQ(LOONGSON_TIMER_IRQ);
         else if (pending & CAUSEF_IP6) {        /* North Bridge, Perf counter */
-#if defined(CONFIG_OPROFILE) || defined(CONFIG_OPROFILE_MODULE)
-                do_IRQ(LOONGSON2_PERFCNT_IRQ);
-#endif
+                do_perfcnt_IRQ();
                 bonito_irqdispatch();
         } else if (pending & CAUSEF_IP3)        /* CPU UART */
                 do_IRQ(LOONGSON_UART_IRQ);
@@ -91,13 +88,6 @@ void mach_irq_dispatch(unsigned int pending)
                 spurious_interrupt();
 }
 
-void __init set_irq_trigger_mode(void)
-{
-        /* setup cs5536 as high level trigger */
-        LOONGSON_INTPOL = LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1;
-        LOONGSON_INTEDGE &= ~(LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1);
-}
-
 static irqreturn_t ip6_action(int cpl, void *dev_id)
 {
         return IRQ_HANDLED;
@@ -122,6 +112,10 @@ void __init mach_init_irq(void)
          *   32-63        ------> bonito irq
          */
 
+        /* setup cs5536 as high level trigger */
+        LOONGSON_INTPOL = LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1;
+        LOONGSON_INTEDGE &= ~(LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1);
+
         /* Sets the first-level interrupt dispatcher. */
         mips_cpu_irq_init();
         init_i8259_irqs();
diff --git a/arch/mips/math-emu/Makefile b/arch/mips/math-emu/Makefile
index d547efdeedc2..96607230d9ea 100644
--- a/arch/mips/math-emu/Makefile
+++ b/arch/mips/math-emu/Makefile
@@ -10,4 +10,3 @@ obj-y	:= cp1emu.o ieee754m.o ieee754d.o ieee754dp.o ieee754sp.o ieee754.o \
            sp_scalb.o sp_simple.o sp_tint.o sp_fint.o sp_tlong.o sp_flong.o \
            dp_sqrt.o sp_sqrt.o kernel_linkage.o dsemul.o
 
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/math-emu/dp_modf.c b/arch/mips/math-emu/dp_modf.c
index 25861a42c36f..a8570e5c3efc 100644
--- a/arch/mips/math-emu/dp_modf.c
+++ b/arch/mips/math-emu/dp_modf.c
@@ -29,7 +29,7 @@
 
 /* modf function is always exact for a finite number
 */
-ieee754dp ieee754dp_modf(ieee754dp x, ieee754dp * ip)
+ieee754dp ieee754dp_modf(ieee754dp x, ieee754dp *ip)
 {
         COMPXDP;
 
diff --git a/arch/mips/math-emu/dp_tint.c b/arch/mips/math-emu/dp_tint.c
index 77b2b7ccf28a..24478623c117 100644
--- a/arch/mips/math-emu/dp_tint.c
+++ b/arch/mips/math-emu/dp_tint.c
@@ -69,8 +69,7 @@ int ieee754dp_tint(ieee754dp x)
                         round = 0;
                         sticky = residue != 0;
                         xm = 0;
-                }
-                else {
+                } else {
                         residue = xm << (64 - DP_MBITS + xe);
                         round = (residue >> 63) != 0;
                         sticky = (residue << 1) != 0;
diff --git a/arch/mips/math-emu/dp_tlong.c b/arch/mips/math-emu/dp_tlong.c
index d71113e07164..0f07ec2be3f9 100644
--- a/arch/mips/math-emu/dp_tlong.c
+++ b/arch/mips/math-emu/dp_tlong.c
@@ -71,8 +71,7 @@ s64 ieee754dp_tlong(ieee754dp x)
                         round = 0;
                         sticky = residue != 0;
                         xm = 0;
-                }
-                else {
+                } else {
                         /* Shifting a u64 64 times does not work,
                         * so we do it in two steps. Be aware that xe
                         * may be -1 */
diff --git a/arch/mips/math-emu/sp_modf.c b/arch/mips/math-emu/sp_modf.c
index 4b1dbac796f8..76568946b4c0 100644
--- a/arch/mips/math-emu/sp_modf.c
+++ b/arch/mips/math-emu/sp_modf.c
@@ -29,7 +29,7 @@
 
 /* modf function is always exact for a finite number
 */
-ieee754sp ieee754sp_modf(ieee754sp x, ieee754sp * ip)
+ieee754sp ieee754sp_modf(ieee754sp x, ieee754sp *ip)
 {
         COMPXSP;
 
diff --git a/arch/mips/math-emu/sp_tint.c b/arch/mips/math-emu/sp_tint.c
index 1d73d2abe0b5..352dc3a5f1af 100644
--- a/arch/mips/math-emu/sp_tint.c
+++ b/arch/mips/math-emu/sp_tint.c
@@ -72,8 +72,7 @@ int ieee754sp_tint(ieee754sp x)
                         round = 0;
                         sticky = residue != 0;
                         xm = 0;
-                }
-                else {
+                } else {
                         /* Shifting a u32 32 times does not work,
                         * so we do it in two steps. Be aware that xe
                         * may be -1 */
diff --git a/arch/mips/math-emu/sp_tlong.c b/arch/mips/math-emu/sp_tlong.c
index 4be21aa81fbf..92cd9c511a10 100644
--- a/arch/mips/math-emu/sp_tlong.c
+++ b/arch/mips/math-emu/sp_tlong.c
@@ -71,8 +71,7 @@ s64 ieee754sp_tlong(ieee754sp x)
                         round = 0;
                         sticky = residue != 0;
                         xm = 0;
-                }
-                else {
+                } else {
                         residue = xm << (32 - SP_MBITS + xe);
                         round = (residue >> 31) != 0;
                         sticky = (residue << 1) != 0;
diff --git a/arch/mips/mipssim/Makefile b/arch/mips/mipssim/Makefile
index 41b96571315e..01410a3f1729 100644
--- a/arch/mips/mipssim/Makefile
+++ b/arch/mips/mipssim/Makefile
@@ -21,5 +21,3 @@ obj-y := sim_platform.o sim_setup.o sim_mem.o sim_time.o sim_int.o
 
 obj-$(CONFIG_EARLY_PRINTK) += sim_console.o
 obj-$(CONFIG_MIPS_MT_SMTC) += sim_smtc.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/mipssim/Platform b/arch/mips/mipssim/Platform
new file mode 100644
index 000000000000..3df60b8a12ef
--- /dev/null
+++ b/arch/mips/mipssim/Platform
@@ -0,0 +1,6 @@
+#
+# MIPS SIM
+#
+platform-$(CONFIG_MIPS_SIM)     += mipssim/
+cflags-$(CONFIG_MIPS_SIM)       += -I$(srctree)/arch/mips/include/asm/mach-mipssim
+load-$(CONFIG_MIPS_SIM)         += 0x80100000
diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile
index f0e435599707..d679c772d082 100644
--- a/arch/mips/mm/Makefile
+++ b/arch/mips/mm/Makefile
@@ -34,5 +34,3 @@ obj-$(CONFIG_IP22_CPU_SCACHE)	+= sc-ip22.o
 obj-$(CONFIG_R5000_CPU_SCACHE)  += sc-r5k.o
 obj-$(CONFIG_RM7000_CPU_SCACHE) += sc-rm7k.o
 obj-$(CONFIG_MIPS_CPU_SCACHE)   += sc-mips.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/mm/fault.c b/arch/mips/mm/fault.c
index b78f7d913ca4..783ad0065fdf 100644
--- a/arch/mips/mm/fault.c
+++ b/arch/mips/mm/fault.c
@@ -16,8 +16,8 @@
 #include <linux/mman.h>
 #include <linux/mm.h>
 #include <linux/smp.h>
-#include <linux/vt_kern.h>              /* For unblank_screen() */
 #include <linux/module.h>
+#include <linux/kprobes.h>
 
 #include <asm/branch.h>
 #include <asm/mmu_context.h>
@@ -25,13 +25,14 @@
 #include <asm/uaccess.h>
 #include <asm/ptrace.h>
 #include <asm/highmem.h>                /* For VMALLOC_END */
+#include <linux/kdebug.h>
 
 /*
  * This routine handles page faults.  It determines the address,
  * and the problem, and then passes it off to one of the appropriate
  * routines.
  */
-asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long write,
+asmlinkage void __kprobes do_page_fault(struct pt_regs *regs, unsigned long write,
                               unsigned long address)
 {
         struct vm_area_struct * vma = NULL;
@@ -47,6 +48,17 @@ asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long write,
                field, regs->cp0_epc);
 #endif
 
+#ifdef CONFIG_KPROBES
+        /*
+         * This is to notify the fault handler of the kprobes.  The
+         * exception code is redundant as it is also carried in REGS,
+         * but we pass it anyhow.
+         */
+        if (notify_die(DIE_PAGE_FAULT, "page fault", regs, -1,
+                       (regs->cp0_cause >> 2) & 0x1f, SIGSEGV) == NOTIFY_STOP)
+                return;
+#endif
+
         info.si_code = SEGV_MAPERR;
 
         /*
diff --git a/arch/mips/mm/sc-rm7k.c b/arch/mips/mm/sc-rm7k.c
index de69bfbf506e..1ef75cd80a0d 100644
--- a/arch/mips/mm/sc-rm7k.c
+++ b/arch/mips/mm/sc-rm7k.c
@@ -16,6 +16,7 @@
 #include <asm/cacheops.h>
 #include <asm/mipsregs.h>
 #include <asm/processor.h>
+#include <asm/sections.h>
 #include <asm/cacheflush.h> /* for run_uncached() */
 
 /* Primary cache parameters. */
@@ -25,11 +26,15 @@
 /* Secondary cache parameters. */
 #define scache_size     (256*1024)      /* Fixed to 256KiB on RM7000 */
 
+/* Tertiary cache parameters */
+#define tc_lsize        32
+
 extern unsigned long icache_way_size, dcache_way_size;
+unsigned long tcache_size;
 
 #include <asm/r4kcache.h>
 
-static int rm7k_tcache_enabled;
+static int rm7k_tcache_init;
 
 /*
  * Writeback and invalidate the primary cache dcache before DMA.
@@ -46,7 +51,7 @@ static void rm7k_sc_wback_inv(unsigned long addr, unsigned long size)
 
         blast_scache_range(addr, addr + size);
 
-        if (!rm7k_tcache_enabled)
+        if (!rm7k_tcache_init)
                 return;
 
         a = addr & ~(tc_pagesize - 1);
@@ -70,7 +75,7 @@ static void rm7k_sc_inv(unsigned long addr, unsigned long size)
 
         blast_inv_scache_range(addr, addr + size);
 
-        if (!rm7k_tcache_enabled)
+        if (!rm7k_tcache_init)
                 return;
 
         a = addr & ~(tc_pagesize - 1);
@@ -83,6 +88,45 @@ static void rm7k_sc_inv(unsigned long addr, unsigned long size)
         }
 }
 
+static void blast_rm7k_tcache(void)
+{
+        unsigned long start = CKSEG0ADDR(0);
+        unsigned long end = start + tcache_size;
+
+        write_c0_taglo(0);
+
+        while (start < end) {
+                cache_op(Page_Invalidate_T, start);
+                start += tc_pagesize;
+        }
+}
+
+/*
+ * This function is executed in uncached address space.
+ */
+static __cpuinit void __rm7k_tc_enable(void)
+{
+        int i;
+
+        set_c0_config(RM7K_CONF_TE);
+
+        write_c0_taglo(0);
+        write_c0_taghi(0);
+
+        for (i = 0; i < tcache_size; i += tc_lsize)
+                cache_op(Index_Store_Tag_T, CKSEG0ADDR(i));
+}
+
+static __cpuinit void rm7k_tc_enable(void)
+{
+        if (read_c0_config() & RM7K_CONF_TE)
+                return;
+
+        BUG_ON(tcache_size == 0);
+
+        run_uncached(__rm7k_tc_enable);
+}
+
 /*
  * This function is executed in uncached address space.
  */
@@ -95,16 +139,8 @@ static __cpuinit void __rm7k_sc_enable(void)
         write_c0_taglo(0);
         write_c0_taghi(0);
 
-        for (i = 0; i < scache_size; i += sc_lsize) {
-                __asm__ __volatile__ (
-                      ".set noreorder\n\t"
-                      ".set mips3\n\t"
-                      "cache %1, (%0)\n\t"
-                      ".set mips0\n\t"
-                      ".set reorder"
-                      :
-                      : "r" (CKSEG0ADDR(i)), "i" (Index_Store_Tag_SD));
-        }
+        for (i = 0; i < scache_size; i += sc_lsize)
+                cache_op(Index_Store_Tag_SD, CKSEG0ADDR(i));
 }
 
 static __cpuinit void rm7k_sc_enable(void)
@@ -112,13 +148,29 @@ static __cpuinit void rm7k_sc_enable(void)
         if (read_c0_config() & RM7K_CONF_SE)
                 return;
 
-        printk(KERN_INFO "Enabling secondary cache...\n");
+        pr_info("Enabling secondary cache...\n");
         run_uncached(__rm7k_sc_enable);
+
+        if (rm7k_tcache_init)
+                rm7k_tc_enable();
+}
+
+static void rm7k_tc_disable(void)
+{
+        unsigned long flags;
+
+        local_irq_save(flags);
+        blast_rm7k_tcache();
+        clear_c0_config(RM7K_CONF_TE);
+        local_irq_save(flags);
 }
 
 static void rm7k_sc_disable(void)
 {
         clear_c0_config(RM7K_CONF_SE);
+
+        if (rm7k_tcache_init)
+                rm7k_tc_disable();
 }
 
 static struct bcache_ops rm7k_sc_ops = {
@@ -128,6 +180,52 @@ static struct bcache_ops rm7k_sc_ops = {
         .bc_inv = rm7k_sc_inv
 };
 
+/*
+ * This is a probing function like the one found in c-r4k.c, we look for the
+ * wrap around point with different addresses.
+ */
+static __cpuinit void __probe_tcache(void)
+{
+        unsigned long flags, addr, begin, end, pow2;
+
+        begin = (unsigned long) &_stext;
+        begin  &= ~((8 * 1024 * 1024) - 1);
+        end = begin + (8 * 1024 * 1024);
+
+        local_irq_save(flags);
+
+        set_c0_config(RM7K_CONF_TE);
+
+        /* Fill size-multiple lines with a valid tag */
+        pow2 = (256 * 1024);
+        for (addr = begin; addr <= end; addr = (begin + pow2)) {
+                unsigned long *p = (unsigned long *) addr;
+                __asm__ __volatile__("nop" : : "r" (*p));
+                pow2 <<= 1;
+        }
+
+        /* Load first line with a 0 tag, to check after */
+        write_c0_taglo(0);
+        write_c0_taghi(0);
+        cache_op(Index_Store_Tag_T, begin);
+
+        /* Look for the wrap-around */
+        pow2 = (512 * 1024);
+        for (addr = begin + (512 * 1024); addr <= end; addr = begin + pow2) {
+                cache_op(Index_Load_Tag_T, addr);
+                if (!read_c0_taglo())
+                        break;
+                pow2 <<= 1;
+        }
+
+        addr -= begin;
+        tcache_size = addr;
+
+        clear_c0_config(RM7K_CONF_TE);
+
+        local_irq_restore(flags);
+}
+
 void __cpuinit rm7k_sc_init(void)
 {
         struct cpuinfo_mips *c = &current_cpu_data;
@@ -147,27 +245,26 @@ void __cpuinit rm7k_sc_init(void)
         if (!(config & RM7K_CONF_SE))
                 rm7k_sc_enable();
 
+        bcops = &rm7k_sc_ops;
+
         /*
          * While we're at it let's deal with the tertiary cache.
          */
-        if (!(config & RM7K_CONF_TC)) {
-
-                /*
-                 * We can't enable the L3 cache yet. There may be board-specific
-                 * magic necessary to turn it on, and blindly asking the CPU to
-                 * start using it would may give cache errors.
-                 *
-                 * Also, board-specific knowledge may allow us to use the
-                 * CACHE Flash_Invalidate_T instruction if the tag RAM supports
-                 * it, and may specify the size of the L3 cache so we don't have
-                 * to probe it.
-                 */
-                printk(KERN_INFO "Tertiary cache present, %s enabled\n",
-                       (config & RM7K_CONF_TE) ? "already" : "not (yet)");
-
-                if ((config & RM7K_CONF_TE))
-                        rm7k_tcache_enabled = 1;
-        }
 
-        bcops = &rm7k_sc_ops;
+        rm7k_tcache_init = 0;
+        tcache_size = 0;
+
+        if (config & RM7K_CONF_TC)
+                return;
+
+        /*
+         * No efficient way to ask the hardware for the size of the tcache,
+         * so must probe for it.
+         */
+        run_uncached(__probe_tcache);
+        rm7k_tc_enable();
+        rm7k_tcache_init = 1;
+        c->tcache.linesz = tc_lsize;
+        c->tcache.ways = 1;
+        pr_info("Tertiary cache size %ldK.\n", (tcache_size >> 10));
 }
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 86f004dc8355..4510e61883eb 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -409,6 +409,11 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
                 tlbw(p);
                 break;
 
+        case CPU_JZRISC:
+                tlbw(p);
+                uasm_i_nop(p);
+                break;
+
         default:
                 panic("No TLB refill handler yet (CPU type: %d)",
                       current_cpu_data.cputype);
diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c
index 611d564fdcf1..d2647a4e012b 100644
--- a/arch/mips/mm/uasm.c
+++ b/arch/mips/mm/uasm.c
@@ -62,12 +62,13 @@ enum opcode {
         insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
         insn_bne, insn_cache, insn_daddu, insn_daddiu, insn_dmfc0,
         insn_dmtc0, insn_dsll, insn_dsll32, insn_dsra, insn_dsrl,
-        insn_dsrl32, insn_drotr, insn_dsubu, insn_eret, insn_j, insn_jal,
-        insn_jr, insn_ld, insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0,
-        insn_mtc0, insn_or, insn_ori, insn_pref, insn_rfe, insn_sc, insn_scd,
-        insn_sd, insn_sll, insn_sra, insn_srl, insn_rotr, insn_subu, insn_sw,
-        insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori,
-        insn_dins, insn_syscall
+        insn_dsrl32, insn_drotr, insn_drotr32, insn_dsubu, insn_eret,
+        insn_j, insn_jal, insn_jr, insn_ld, insn_ll, insn_lld,
+        insn_lui, insn_lw, insn_mfc0, insn_mtc0, insn_or, insn_ori,
+        insn_pref, insn_rfe, insn_sc, insn_scd, insn_sd, insn_sll,
+        insn_sra, insn_srl, insn_rotr, insn_subu, insn_sw, insn_tlbp,
+        insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori,
+        insn_dins, insn_syscall, insn_bbit0, insn_bbit1
 };
 
 struct insn {
@@ -85,7 +86,7 @@ struct insn {
          | (e) << RE_SH                                         \
          | (f) << FUNC_SH)
 
-static struct insn insn_table[] __cpuinitdata = {
+static struct insn insn_table[] __uasminitdata = {
         { insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
         { insn_addu, M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD },
         { insn_and, M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD },
@@ -108,6 +109,7 @@ static struct insn insn_table[] __cpuinitdata = {
         { insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE },
         { insn_dsrl32, M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE },
         { insn_drotr, M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE },
+        { insn_drotr32, M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE },
         { insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD },
         { insn_eret,  M(cop0_op, cop_op, 0, 0, 0, eret_op),  0 },
         { insn_j,  M(j_op, 0, 0, 0, 0, 0),  JIMM },
@@ -141,12 +143,14 @@ static struct insn insn_table[] __cpuinitdata = {
         { insn_xori,  M(xori_op, 0, 0, 0, 0, 0),  RS | RT | UIMM },
         { insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE },
         { insn_syscall, M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM},
+        { insn_bbit0, M(lwc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
+        { insn_bbit1, M(swc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
         { insn_invalid, 0, 0 }
 };
 
 #undef M
 
-static inline __cpuinit u32 build_rs(u32 arg)
+static inline __uasminit u32 build_rs(u32 arg)
 {
         if (arg & ~RS_MASK)
                 printk(KERN_WARNING "Micro-assembler field overflow\n");
@@ -154,7 +158,7 @@ static inline __cpuinit u32 build_rs(u32 arg)
         return (arg & RS_MASK) << RS_SH;
 }
 
-static inline __cpuinit u32 build_rt(u32 arg)
+static inline __uasminit u32 build_rt(u32 arg)
 {
         if (arg & ~RT_MASK)
                 printk(KERN_WARNING "Micro-assembler field overflow\n");
@@ -162,7 +166,7 @@ static inline __cpuinit u32 build_rt(u32 arg)
         return (arg & RT_MASK) << RT_SH;
 }
 
-static inline __cpuinit u32 build_rd(u32 arg)
+static inline __uasminit u32 build_rd(u32 arg)
 {
         if (arg & ~RD_MASK)
                 printk(KERN_WARNING "Micro-assembler field overflow\n");
@@ -170,7 +174,7 @@ static inline __cpuinit u32 build_rd(u32 arg)
         return (arg & RD_MASK) << RD_SH;
 }
 
-static inline __cpuinit u32 build_re(u32 arg)
+static inline __uasminit u32 build_re(u32 arg)
 {
         if (arg & ~RE_MASK)
                 printk(KERN_WARNING "Micro-assembler field overflow\n");
@@ -178,7 +182,7 @@ static inline __cpuinit u32 build_re(u32 arg)
         return (arg & RE_MASK) << RE_SH;
 }
 
-static inline __cpuinit u32 build_simm(s32 arg)
+static inline __uasminit u32 build_simm(s32 arg)
 {
         if (arg > 0x7fff || arg < -0x8000)
                 printk(KERN_WARNING "Micro-assembler field overflow\n");
@@ -186,7 +190,7 @@ static inline __cpuinit u32 build_simm(s32 arg)
         return arg & 0xffff;
 }
 
-static inline __cpuinit u32 build_uimm(u32 arg)
+static inline __uasminit u32 build_uimm(u32 arg)
 {
         if (arg & ~IMM_MASK)
                 printk(KERN_WARNING "Micro-assembler field overflow\n");
@@ -194,7 +198,7 @@ static inline __cpuinit u32 build_uimm(u32 arg)
         return arg & IMM_MASK;
 }
 
-static inline __cpuinit u32 build_bimm(s32 arg)
+static inline __uasminit u32 build_bimm(s32 arg)
 {
         if (arg > 0x1ffff || arg < -0x20000)
                 printk(KERN_WARNING "Micro-assembler field overflow\n");
@@ -205,7 +209,7 @@ static inline __cpuinit u32 build_bimm(s32 arg)
         return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff);
 }
 
-static inline __cpuinit u32 build_jimm(u32 arg)
+static inline __uasminit u32 build_jimm(u32 arg)
 {
         if (arg & ~((JIMM_MASK) << 2))
                 printk(KERN_WARNING "Micro-assembler field overflow\n");
@@ -213,7 +217,7 @@ static inline __cpuinit u32 build_jimm(u32 arg)
         return (arg >> 2) & JIMM_MASK;
 }
 
-static inline __cpuinit u32 build_scimm(u32 arg)
+static inline __uasminit u32 build_scimm(u32 arg)
 {
         if (arg & ~SCIMM_MASK)
                 printk(KERN_WARNING "Micro-assembler field overflow\n");
@@ -221,7 +225,7 @@ static inline __cpuinit u32 build_scimm(u32 arg)
         return (arg & SCIMM_MASK) << SCIMM_SH;
 }
 
-static inline __cpuinit u32 build_func(u32 arg)
+static inline __uasminit u32 build_func(u32 arg)
 {
         if (arg & ~FUNC_MASK)
                 printk(KERN_WARNING "Micro-assembler field overflow\n");
@@ -229,7 +233,7 @@ static inline __cpuinit u32 build_func(u32 arg)
         return arg & FUNC_MASK;
 }
 
-static inline __cpuinit u32 build_set(u32 arg)
+static inline __uasminit u32 build_set(u32 arg)
 {
         if (arg & ~SET_MASK)
                 printk(KERN_WARNING "Micro-assembler field overflow\n");
@@ -241,7 +245,7 @@ static inline __cpuinit u32 build_set(u32 arg)
  * The order of opcode arguments is implicitly left to right,
  * starting with RS and ending with FUNC or IMM.
  */
-static void __cpuinit build_insn(u32 **buf, enum opcode opc, ...)
+static void __uasminit build_insn(u32 **buf, enum opcode opc, ...)
 {
         struct insn *ip = NULL;
         unsigned int i;
@@ -291,67 +295,78 @@ static void __cpuinit build_insn(u32 **buf, enum opcode opc, ...)
 Ip_u1u2u3(op)                                           \
 {                                                       \
         build_insn(buf, insn##op, a, b, c);             \
-}
+}                                                       \
+UASM_EXPORT_SYMBOL(uasm_i##op);
 
 #define I_u2u1u3(op)                                    \
 Ip_u2u1u3(op)                                           \
 {                                                       \
         build_insn(buf, insn##op, b, a, c);             \
-}
+}                                                       \
+UASM_EXPORT_SYMBOL(uasm_i##op);
 
 #define I_u3u1u2(op)                                    \
 Ip_u3u1u2(op)                                           \
 {                                                       \
         build_insn(buf, insn##op, b, c, a);             \
-}
+}                                                       \
+UASM_EXPORT_SYMBOL(uasm_i##op);
 
 #define I_u1u2s3(op)                                    \
 Ip_u1u2s3(op)                                           \
 {                                                       \
         build_insn(buf, insn##op, a, b, c);             \
-}
+}                                                       \
+UASM_EXPORT_SYMBOL(uasm_i##op);
 
 #define I_u2s3u1(op)                                    \
 Ip_u2s3u1(op)                                           \
 {                                                       \
         build_insn(buf, insn##op, c, a, b);             \
-}
+}                                                       \
+UASM_EXPORT_SYMBOL(uasm_i##op);
 
 #define I_u2u1s3(op)                                    \
 Ip_u2u1s3(op)                                           \
 {                                                       \
         build_insn(buf, insn##op, b, a, c);             \
-}
+}                                                       \
+UASM_EXPORT_SYMBOL(uasm_i##op);
 
 #define I_u2u1msbu3(op)                                 \
 Ip_u2u1msbu3(op)                                        \
 {                                                       \
         build_insn(buf, insn##op, b, a, c+d-1, c);      \
-}
+}                                                       \
+UASM_EXPORT_SYMBOL(uasm_i##op);
 
 #define I_u1u2(op)                                      \
 Ip_u1u2(op)                                             \
 {                                                       \
         build_insn(buf, insn##op, a, b);                \
-}
+}                                                       \
+UASM_EXPORT_SYMBOL(uasm_i##op);
 
 #define I_u1s2(op)                                      \
 Ip_u1s2(op)                                             \
 {                                                       \
         build_insn(buf, insn##op, a, b);                \
-}
+}                                                       \
+UASM_EXPORT_SYMBOL(uasm_i##op);
 
 #define I_u1(op)                                        \
 Ip_u1(op)                                               \
 {                                                       \
         build_insn(buf, insn##op, a);                   \
-}
+}                                                       \
+UASM_EXPORT_SYMBOL(uasm_i##op);
 
 #define I_0(op)                                         \
 Ip_0(op)                                                \
 {                                                       \
         build_insn(buf, insn##op);                      \
-}
+}                                                       \
+UASM_EXPORT_SYMBOL(uasm_i##op);
 
 I_u2u1s3(_addiu)
 I_u3u1u2(_addu)
@@ -375,6 +390,7 @@ I_u2u1u3(_dsra)
 I_u2u1u3(_dsrl)
 I_u2u1u3(_dsrl32)
 I_u2u1u3(_drotr)
+I_u2u1u3(_drotr32)
 I_u3u1u2(_dsubu)
 I_0(_eret)
 I_u1(_j)
@@ -408,16 +424,19 @@ I_u3u1u2(_xor)
 I_u2u1u3(_xori)
 I_u2u1msbu3(_dins);
 I_u1(_syscall);
+I_u1u2s3(_bbit0);
+I_u1u2s3(_bbit1);
 
 /* Handle labels. */
-void __cpuinit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid)
+void __uasminit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid)
 {
         (*lab)->addr = addr;
         (*lab)->lab = lid;
         (*lab)++;
 }
+UASM_EXPORT_SYMBOL(uasm_build_label);
 
-int __cpuinit uasm_in_compat_space_p(long addr)
+int __uasminit uasm_in_compat_space_p(long addr)
 {
         /* Is this address in 32bit compat space? */
 #ifdef CONFIG_64BIT
@@ -426,8 +445,9 @@ int __cpuinit uasm_in_compat_space_p(long addr)
         return 1;
 #endif
 }
+UASM_EXPORT_SYMBOL(uasm_in_compat_space_p);
 
-static int __cpuinit uasm_rel_highest(long val)
+static int __uasminit uasm_rel_highest(long val)
 {
 #ifdef CONFIG_64BIT
         return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000;
@@ -436,7 +456,7 @@ static int __cpuinit uasm_rel_highest(long val)
 #endif
 }
 
-static int __cpuinit uasm_rel_higher(long val)
+static int __uasminit uasm_rel_higher(long val)
 {
 #ifdef CONFIG_64BIT
         return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000;
@@ -445,17 +465,19 @@ static int __cpuinit uasm_rel_higher(long val)
 #endif
 }
 
-int __cpuinit uasm_rel_hi(long val)
+int __uasminit uasm_rel_hi(long val)
 {
         return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000;
 }
+UASM_EXPORT_SYMBOL(uasm_rel_hi);
 
-int __cpuinit uasm_rel_lo(long val)
+int __uasminit uasm_rel_lo(long val)
 {
         return ((val & 0xffff) ^ 0x8000) - 0x8000;
 }
+UASM_EXPORT_SYMBOL(uasm_rel_lo);
 
-void __cpuinit UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr)
+void __uasminit UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr)
 {
         if (!uasm_in_compat_space_p(addr)) {
                 uasm_i_lui(buf, rs, uasm_rel_highest(addr));
@@ -470,8 +492,9 @@ void __cpuinit UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr)
         } else
                 uasm_i_lui(buf, rs, uasm_rel_hi(addr));
 }
+UASM_EXPORT_SYMBOL(UASM_i_LA_mostly);
 
-void __cpuinit UASM_i_LA(u32 **buf, unsigned int rs, long addr)
+void __uasminit UASM_i_LA(u32 **buf, unsigned int rs, long addr)
 {
         UASM_i_LA_mostly(buf, rs, addr);
         if (uasm_rel_lo(addr)) {
@@ -481,9 +504,10 @@ void __cpuinit UASM_i_LA(u32 **buf, unsigned int rs, long addr)
                         uasm_i_addiu(buf, rs, rs, uasm_rel_lo(addr));
         }
 }
+UASM_EXPORT_SYMBOL(UASM_i_LA);
 
 /* Handle relocations. */
-void __cpuinit
+void __uasminit
 uasm_r_mips_pc16(struct uasm_reloc **rel, u32 *addr, int lid)
 {
         (*rel)->addr = addr;
@@ -491,8 +515,9 @@ uasm_r_mips_pc16(struct uasm_reloc **rel, u32 *addr, int lid)
         (*rel)->lab = lid;
         (*rel)++;
 }
+UASM_EXPORT_SYMBOL(uasm_r_mips_pc16);
 
-static inline void __cpuinit
+static inline void __uasminit
 __resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab)
 {
         long laddr = (long)lab->addr;
@@ -509,7 +534,7 @@ __resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab)
         }
 }
 
-void __cpuinit
+void __uasminit
 uasm_resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab)
 {
         struct uasm_label *l;
@@ -519,24 +544,27 @@ uasm_resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab)
                         if (rel->lab == l->lab)
                                 __resolve_relocs(rel, l);
 }
+UASM_EXPORT_SYMBOL(uasm_resolve_relocs);
 
-void __cpuinit
+void __uasminit
 uasm_move_relocs(struct uasm_reloc *rel, u32 *first, u32 *end, long off)
 {
         for (; rel->lab != UASM_LABEL_INVALID; rel++)
                 if (rel->addr >= first && rel->addr < end)
                         rel->addr += off;
 }
+UASM_EXPORT_SYMBOL(uasm_move_relocs);
 
-void __cpuinit
+void __uasminit
 uasm_move_labels(struct uasm_label *lab, u32 *first, u32 *end, long off)
 {
         for (; lab->lab != UASM_LABEL_INVALID; lab++)
                 if (lab->addr >= first && lab->addr < end)
                         lab->addr += off;
 }
+UASM_EXPORT_SYMBOL(uasm_move_labels);
 
-void __cpuinit
+void __uasminit
 uasm_copy_handler(struct uasm_reloc *rel, struct uasm_label *lab, u32 *first,
                   u32 *end, u32 *target)
 {
@@ -547,8 +575,9 @@ uasm_copy_handler(struct uasm_reloc *rel, struct uasm_label *lab, u32 *first,
         uasm_move_relocs(rel, first, end, off);
         uasm_move_labels(lab, first, end, off);
 }
+UASM_EXPORT_SYMBOL(uasm_copy_handler);
 
-int __cpuinit uasm_insn_has_bdelay(struct uasm_reloc *rel, u32 *addr)
+int __uasminit uasm_insn_has_bdelay(struct uasm_reloc *rel, u32 *addr)
 {
         for (; rel->lab != UASM_LABEL_INVALID; rel++) {
                 if (rel->addr == addr
@@ -559,61 +588,88 @@ int __cpuinit uasm_insn_has_bdelay(struct uasm_reloc *rel, u32 *addr)
 
         return 0;
 }
+UASM_EXPORT_SYMBOL(uasm_insn_has_bdelay);
 
 /* Convenience functions for labeled branches. */
-void __cpuinit
+void __uasminit
 uasm_il_bltz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
 {
         uasm_r_mips_pc16(r, *p, lid);
         uasm_i_bltz(p, reg, 0);
 }
+UASM_EXPORT_SYMBOL(uasm_il_bltz);
 
-void __cpuinit
+void __uasminit
 uasm_il_b(u32 **p, struct uasm_reloc **r, int lid)
 {
         uasm_r_mips_pc16(r, *p, lid);
         uasm_i_b(p, 0);
 }
+UASM_EXPORT_SYMBOL(uasm_il_b);
 
-void __cpuinit
+void __uasminit
 uasm_il_beqz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
 {
         uasm_r_mips_pc16(r, *p, lid);
         uasm_i_beqz(p, reg, 0);
 }
+UASM_EXPORT_SYMBOL(uasm_il_beqz);
 
-void __cpuinit
+void __uasminit
 uasm_il_beqzl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
 {
         uasm_r_mips_pc16(r, *p, lid);
         uasm_i_beqzl(p, reg, 0);
 }
+UASM_EXPORT_SYMBOL(uasm_il_beqzl);
 
-void __cpuinit
+void __uasminit
 uasm_il_bne(u32 **p, struct uasm_reloc **r, unsigned int reg1,
         unsigned int reg2, int lid)
 {
         uasm_r_mips_pc16(r, *p, lid);
         uasm_i_bne(p, reg1, reg2, 0);
 }
+UASM_EXPORT_SYMBOL(uasm_il_bne);
 
-void __cpuinit
+void __uasminit
 uasm_il_bnez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
 {
         uasm_r_mips_pc16(r, *p, lid);
         uasm_i_bnez(p, reg, 0);
 }
+UASM_EXPORT_SYMBOL(uasm_il_bnez);
 
-void __cpuinit
+void __uasminit
 uasm_il_bgezl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
 {
         uasm_r_mips_pc16(r, *p, lid);
         uasm_i_bgezl(p, reg, 0);
 }
+UASM_EXPORT_SYMBOL(uasm_il_bgezl);
 
-void __cpuinit
+void __uasminit
 uasm_il_bgez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
 {
         uasm_r_mips_pc16(r, *p, lid);
         uasm_i_bgez(p, reg, 0);
 }
+UASM_EXPORT_SYMBOL(uasm_il_bgez);
+
+void __uasminit
+uasm_il_bbit0(u32 **p, struct uasm_reloc **r, unsigned int reg,
+              unsigned int bit, int lid)
+{
+        uasm_r_mips_pc16(r, *p, lid);
+        uasm_i_bbit0(p, reg, bit, 0);
+}
+UASM_EXPORT_SYMBOL(uasm_il_bbit0);
+
+void __uasminit
+uasm_il_bbit1(u32 **p, struct uasm_reloc **r, unsigned int reg,
+              unsigned int bit, int lid)
+{
+        uasm_r_mips_pc16(r, *p, lid);
+        uasm_i_bbit1(p, reg, bit, 0);
+}
+UASM_EXPORT_SYMBOL(uasm_il_bbit1);
diff --git a/arch/mips/mti-malta/Makefile b/arch/mips/mti-malta/Makefile
index 32e847808df1..6079ef33b5f0 100644
--- a/arch/mips/mti-malta/Makefile
+++ b/arch/mips/mti-malta/Makefile
@@ -15,5 +15,3 @@ obj-$(CONFIG_PCI)		+= malta-pci.o
 
 # FIXME FIXME FIXME
 obj-$(CONFIG_MIPS_MT_SMTC)      += malta-smtc.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/mti-malta/Platform b/arch/mips/mti-malta/Platform
new file mode 100644
index 000000000000..5b548b5a4fcf
--- /dev/null
+++ b/arch/mips/mti-malta/Platform
@@ -0,0 +1,7 @@
+#
+# MIPS Malta board
+#
+platform-$(CONFIG_MIPS_MALTA)   += mti-malta/
+cflags-$(CONFIG_MIPS_MALTA)     += -I$(srctree)/arch/mips/include/asm/mach-malta
+load-$(CONFIG_MIPS_MALTA)       += 0xffffffff80100000
+all-$(CONFIG_MIPS_MALTA)        := $(COMPRESSION_FNAME).bin
diff --git a/arch/mips/nxp/pnx833x/stb22x/Makefile b/arch/mips/nxp/pnx833x/stb22x/Makefile
deleted file mode 100644
index f81c5801f455..000000000000
--- a/arch/mips/nxp/pnx833x/stb22x/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-lib-y := board.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/nxp/pnx8550/jbs/Makefile b/arch/mips/nxp/pnx8550/jbs/Makefile
deleted file mode 100644
index ad6a8ca7d8ce..000000000000
--- a/arch/mips/nxp/pnx8550/jbs/Makefile
+++ /dev/null
@@ -1,4 +0,0 @@
-
-# Makefile for the NXP JBS Board.
-
-lib-y := init.o board_setup.o irqmap.o
diff --git a/arch/mips/nxp/pnx8550/stb810/Makefile b/arch/mips/nxp/pnx8550/stb810/Makefile
deleted file mode 100644
index ab91d72c5664..000000000000
--- a/arch/mips/nxp/pnx8550/stb810/Makefile
+++ /dev/null
@@ -1,4 +0,0 @@
-
-# Makefile for the NXP STB810 Board.
-
-lib-y := prom_init.o board_setup.o irqmap.o
diff --git a/arch/mips/pci/msi-octeon.c b/arch/mips/pci/msi-octeon.c
index 03742e647657..d8080499872a 100644
--- a/arch/mips/pci/msi-octeon.c
+++ b/arch/mips/pci/msi-octeon.c
@@ -3,7 +3,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 2005-2009 Cavium Networks
+ * Copyright (C) 2005-2009, 2010 Cavium Networks
  */
 #include <linux/kernel.h>
 #include <linux/init.h>
@@ -22,7 +22,7 @@
  * Each bit in msi_free_irq_bitmask represents a MSI interrupt that is
  * in use.
  */
-static uint64_t msi_free_irq_bitmask;
+static u64 msi_free_irq_bitmask[4];
 
 /*
  * Each bit in msi_multiple_irq_bitmask tells that the device using
@@ -30,7 +30,7 @@ static uint64_t msi_free_irq_bitmask;
  * is used so we can disable all of the MSI interrupts when a device
  * uses multiple.
  */
-static uint64_t msi_multiple_irq_bitmask;
+static u64 msi_multiple_irq_bitmask[4];
 
 /*
  * This lock controls updates to msi_free_irq_bitmask and
@@ -38,6 +38,11 @@ static uint64_t msi_multiple_irq_bitmask;
  */
 static DEFINE_SPINLOCK(msi_free_irq_bitmask_lock);
 
+/*
+ * Number of MSI IRQs used. This variable is set up in
+ * the module init time.
+ */
+static int msi_irq_size;
 
 /**
  * Called when a driver request MSI interrupts instead of the
@@ -54,12 +59,13 @@ static DEFINE_SPINLOCK(msi_free_irq_bitmask_lock);
 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
 {
         struct msi_msg msg;
-        uint16_t control;
+        u16 control;
         int configured_private_bits;
         int request_private_bits;
-        int irq;
+        int irq = 0;
         int irq_step;
-        uint64_t search_mask;
+        u64 search_mask;
+        int index;
 
         /*
          * Read the MSI config to figure out how many IRQs this device
@@ -111,29 +117,31 @@ try_only_one:
          * use.
          */
         spin_lock(&msi_free_irq_bitmask_lock);
-        for (irq = 0; irq < 64; irq += irq_step) {
-                if ((msi_free_irq_bitmask & (search_mask << irq)) == 0) {
-                        msi_free_irq_bitmask |= search_mask << irq;
-                        msi_multiple_irq_bitmask |= (search_mask >> 1) << irq;
-                        break;
+        for (index = 0; index < msi_irq_size/64; index++) {
+                for (irq = 0; irq < 64; irq += irq_step) {
+                        if ((msi_free_irq_bitmask[index] & (search_mask << irq)) == 0) {
+                                msi_free_irq_bitmask[index] |= search_mask << irq;
+                                msi_multiple_irq_bitmask[index] |= (search_mask >> 1) << irq;
+                                goto msi_irq_allocated;
+                        }
                 }
         }
+msi_irq_allocated:
         spin_unlock(&msi_free_irq_bitmask_lock);
 
         /* Make sure the search for available interrupts didn't fail */
         if (irq >= 64) {
                 if (request_private_bits) {
-                        pr_err("arch_setup_msi_irq: Unable to find %d free "
-                               "interrupts, trying just one",
+                        pr_err("arch_setup_msi_irq: Unable to find %d free interrupts, trying just one",
                                1 << request_private_bits);
                         request_private_bits = 0;
                         goto try_only_one;
                 } else
-                        panic("arch_setup_msi_irq: Unable to find a free MSI "
-                              "interrupt");
+                        panic("arch_setup_msi_irq: Unable to find a free MSI interrupt");
         }
 
         /* MSI interrupts start at logical IRQ OCTEON_IRQ_MSI_BIT0 */
+        irq += index*64;
         irq += OCTEON_IRQ_MSI_BIT0;
 
         switch (octeon_dma_bar_type) {
@@ -169,6 +177,34 @@ try_only_one:
         return 0;
 }
 
+int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
+{
+        struct msi_desc *entry;
+        int ret;
+
+        /*
+         * MSI-X is not supported.
+         */
+        if (type == PCI_CAP_ID_MSIX)
+                return -EINVAL;
+
+        /*
+         * If an architecture wants to support multiple MSI, it needs to
+         * override arch_setup_msi_irqs()
+         */
+        if (type == PCI_CAP_ID_MSI && nvec > 1)
+                return 1;
+
+        list_for_each_entry(entry, &dev->msi_list, list) {
+                ret = arch_setup_msi_irq(dev, entry);
+                if (ret < 0)
+                        return ret;
+                if (ret > 0)
+                        return -ENOSPC;
+        }
+
+        return 0;
+}
 
 /**
  * Called when a device no longer needs its MSI interrupts. All
@@ -179,12 +215,18 @@ try_only_one:
 void arch_teardown_msi_irq(unsigned int irq)
 {
         int number_irqs;
-        uint64_t bitmask;
+        u64 bitmask;
+        int index = 0;
+        int irq0;
 
-        if ((irq < OCTEON_IRQ_MSI_BIT0) || (irq > OCTEON_IRQ_MSI_BIT63))
+        if ((irq < OCTEON_IRQ_MSI_BIT0)
+                || (irq > msi_irq_size + OCTEON_IRQ_MSI_BIT0))
                 panic("arch_teardown_msi_irq: Attempted to teardown illegal "
                       "MSI interrupt (%d)", irq);
+
         irq -= OCTEON_IRQ_MSI_BIT0;
+        index = irq / 64;
+        irq0 = irq % 64;
 
         /*
          * Count the number of IRQs we need to free by looking at the
@@ -192,97 +234,198 @@ void arch_teardown_msi_irq(unsigned int irq)
          * IRQ is also owned by this device.
          */
         number_irqs = 0;
-        while ((irq+number_irqs < 64) &&
-               (msi_multiple_irq_bitmask & (1ull << (irq + number_irqs))))
+        while ((irq0 + number_irqs < 64) &&
+               (msi_multiple_irq_bitmask[index]
+                & (1ull << (irq0 + number_irqs))))
                 number_irqs++;
         number_irqs++;
         /* Mask with one bit for each IRQ */
         bitmask = (1 << number_irqs) - 1;
         /* Shift the mask to the correct bit location */
-        bitmask <<= irq;
-        if ((msi_free_irq_bitmask & bitmask) != bitmask)
+        bitmask <<= irq0;
+        if ((msi_free_irq_bitmask[index] & bitmask) != bitmask)
                 panic("arch_teardown_msi_irq: Attempted to teardown MSI "
                       "interrupt (%d) not in use", irq);
 
         /* Checks are done, update the in use bitmask */
         spin_lock(&msi_free_irq_bitmask_lock);
-        msi_free_irq_bitmask &= ~bitmask;
-        msi_multiple_irq_bitmask &= ~bitmask;
+        msi_free_irq_bitmask[index] &= ~bitmask;
+        msi_multiple_irq_bitmask[index] &= ~bitmask;
         spin_unlock(&msi_free_irq_bitmask_lock);
 }
 
+static DEFINE_RAW_SPINLOCK(octeon_irq_msi_lock);
+
+static u64 msi_rcv_reg[4];
+static u64 mis_ena_reg[4];
+
+static void octeon_irq_msi_enable_pcie(unsigned int irq)
+{
+        u64 en;
+        unsigned long flags;
+        int msi_number = irq - OCTEON_IRQ_MSI_BIT0;
+        int irq_index = msi_number >> 6;
+        int irq_bit = msi_number & 0x3f;
+
+        raw_spin_lock_irqsave(&octeon_irq_msi_lock, flags);
+        en = cvmx_read_csr(mis_ena_reg[irq_index]);
+        en |= 1ull << irq_bit;
+        cvmx_write_csr(mis_ena_reg[irq_index], en);
+        cvmx_read_csr(mis_ena_reg[irq_index]);
+        raw_spin_unlock_irqrestore(&octeon_irq_msi_lock, flags);
+}
+
+static void octeon_irq_msi_disable_pcie(unsigned int irq)
+{
+        u64 en;
+        unsigned long flags;
+        int msi_number = irq - OCTEON_IRQ_MSI_BIT0;
+        int irq_index = msi_number >> 6;
+        int irq_bit = msi_number & 0x3f;
+
+        raw_spin_lock_irqsave(&octeon_irq_msi_lock, flags);
+        en = cvmx_read_csr(mis_ena_reg[irq_index]);
+        en &= ~(1ull << irq_bit);
+        cvmx_write_csr(mis_ena_reg[irq_index], en);
+        cvmx_read_csr(mis_ena_reg[irq_index]);
+        raw_spin_unlock_irqrestore(&octeon_irq_msi_lock, flags);
+}
+
+static struct irq_chip octeon_irq_chip_msi_pcie = {
+        .name = "MSI",
+        .enable = octeon_irq_msi_enable_pcie,
+        .disable = octeon_irq_msi_disable_pcie,
+};
+
+static void octeon_irq_msi_enable_pci(unsigned int irq)
+{
+        /*
+         * Octeon PCI doesn't have the ability to mask/unmask MSI
+         * interrupts individually. Instead of masking/unmasking them
+         * in groups of 16, we simple assume MSI devices are well
+         * behaved. MSI interrupts are always enable and the ACK is
+         * assumed to be enough
+         */
+}
+
+static void octeon_irq_msi_disable_pci(unsigned int irq)
+{
+        /* See comment in enable */
+}
+
+static struct irq_chip octeon_irq_chip_msi_pci = {
+        .name = "MSI",
+        .enable = octeon_irq_msi_enable_pci,
+        .disable = octeon_irq_msi_disable_pci,
+};
 
 /*
  * Called by the interrupt handling code when an MSI interrupt
  * occurs.
  */
-static irqreturn_t octeon_msi_interrupt(int cpl, void *dev_id)
+static irqreturn_t __octeon_msi_do_interrupt(int index, u64 msi_bits)
 {
-        uint64_t msi_bits;
         int irq;
+        int bit;
 
-        if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_PCIE)
-                msi_bits = cvmx_read_csr(CVMX_PEXP_NPEI_MSI_RCV0);
-        else
-                msi_bits = cvmx_read_csr(CVMX_NPI_NPI_MSI_RCV);
-        irq = fls64(msi_bits);
-        if (irq) {
-                irq += OCTEON_IRQ_MSI_BIT0 - 1;
-                if (irq_desc[irq].action) {
-                        do_IRQ(irq);
-                        return IRQ_HANDLED;
-                } else {
-                        pr_err("Spurious MSI interrupt %d\n", irq);
-                        if (octeon_has_feature(OCTEON_FEATURE_PCIE)) {
-                                /* These chips have PCIe */
-                                cvmx_write_csr(CVMX_PEXP_NPEI_MSI_RCV0,
-                                               1ull << (irq -
-                                                        OCTEON_IRQ_MSI_BIT0));
-                        } else {
-                                /* These chips have PCI */
-                                cvmx_write_csr(CVMX_NPI_NPI_MSI_RCV,
-                                               1ull << (irq -
-                                                        OCTEON_IRQ_MSI_BIT0));
-                        }
-                }
+        bit = fls64(msi_bits);
+        if (bit) {
+                bit--;
+                /* Acknowledge it first. */
+                cvmx_write_csr(msi_rcv_reg[index], 1ull << bit);
+
+                irq = bit + OCTEON_IRQ_MSI_BIT0 + 64 * index;
+                do_IRQ(irq);
+                return IRQ_HANDLED;
         }
         return IRQ_NONE;
 }
 
+#define OCTEON_MSI_INT_HANDLER_X(x)                                     \
+static irqreturn_t octeon_msi_interrupt##x(int cpl, void *dev_id)       \
+{                                                                       \
+        u64 msi_bits = cvmx_read_csr(msi_rcv_reg[(x)]);                 \
+        return __octeon_msi_do_interrupt((x), msi_bits);                \
+}
+
+/*
+ * Create octeon_msi_interrupt{0-3} function body
+ */
+OCTEON_MSI_INT_HANDLER_X(0);
+OCTEON_MSI_INT_HANDLER_X(1);
+OCTEON_MSI_INT_HANDLER_X(2);
+OCTEON_MSI_INT_HANDLER_X(3);
 
 /*
  * Initializes the MSI interrupt handling code
  */
-int octeon_msi_initialize(void)
+int __init octeon_msi_initialize(void)
 {
+        int irq;
+        struct irq_chip *msi;
+
+        if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_PCIE) {
+                msi_rcv_reg[0] = CVMX_PEXP_NPEI_MSI_RCV0;
+                msi_rcv_reg[1] = CVMX_PEXP_NPEI_MSI_RCV1;
+                msi_rcv_reg[2] = CVMX_PEXP_NPEI_MSI_RCV2;
+                msi_rcv_reg[3] = CVMX_PEXP_NPEI_MSI_RCV3;
+                mis_ena_reg[0] = CVMX_PEXP_NPEI_MSI_ENB0;
+                mis_ena_reg[1] = CVMX_PEXP_NPEI_MSI_ENB1;
+                mis_ena_reg[2] = CVMX_PEXP_NPEI_MSI_ENB2;
+                mis_ena_reg[3] = CVMX_PEXP_NPEI_MSI_ENB3;
+                msi = &octeon_irq_chip_msi_pcie;
+        } else {
+                msi_rcv_reg[0] = CVMX_NPI_NPI_MSI_RCV;
+#define INVALID_GENERATE_ADE 0x8700000000000000ULL;
+                msi_rcv_reg[1] = INVALID_GENERATE_ADE;
+                msi_rcv_reg[2] = INVALID_GENERATE_ADE;
+                msi_rcv_reg[3] = INVALID_GENERATE_ADE;
+                mis_ena_reg[0] = INVALID_GENERATE_ADE;
+                mis_ena_reg[1] = INVALID_GENERATE_ADE;
+                mis_ena_reg[2] = INVALID_GENERATE_ADE;
+                mis_ena_reg[3] = INVALID_GENERATE_ADE;
+                msi = &octeon_irq_chip_msi_pci;
+        }
+
+        for (irq = OCTEON_IRQ_MSI_BIT0; irq <= OCTEON_IRQ_MSI_LAST; irq++)
+                set_irq_chip_and_handler(irq, msi, handle_simple_irq);
+
         if (octeon_has_feature(OCTEON_FEATURE_PCIE)) {
-                if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt,
-                                IRQF_SHARED,
-                                "MSI[0:63]", octeon_msi_interrupt))
+                if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt0,
+                                0, "MSI[0:63]", octeon_msi_interrupt0))
                         panic("request_irq(OCTEON_IRQ_PCI_MSI0) failed");
+
+                if (request_irq(OCTEON_IRQ_PCI_MSI1, octeon_msi_interrupt1,
+                                0, "MSI[64:127]", octeon_msi_interrupt1))
+                        panic("request_irq(OCTEON_IRQ_PCI_MSI1) failed");
+
+                if (request_irq(OCTEON_IRQ_PCI_MSI2, octeon_msi_interrupt2,
+                                0, "MSI[127:191]", octeon_msi_interrupt2))
+                        panic("request_irq(OCTEON_IRQ_PCI_MSI2) failed");
+
+                if (request_irq(OCTEON_IRQ_PCI_MSI3, octeon_msi_interrupt3,
+                                0, "MSI[192:255]", octeon_msi_interrupt3))
+                        panic("request_irq(OCTEON_IRQ_PCI_MSI3) failed");
+
+                msi_irq_size = 256;
         } else if (octeon_is_pci_host()) {
-                if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt,
-                                IRQF_SHARED,
-                                "MSI[0:15]", octeon_msi_interrupt))
+                if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt0,
+                                0, "MSI[0:15]", octeon_msi_interrupt0))
                         panic("request_irq(OCTEON_IRQ_PCI_MSI0) failed");
 
-                if (request_irq(OCTEON_IRQ_PCI_MSI1, octeon_msi_interrupt,
-                                IRQF_SHARED,
-                                "MSI[16:31]", octeon_msi_interrupt))
+                if (request_irq(OCTEON_IRQ_PCI_MSI1, octeon_msi_interrupt0,
+                                0, "MSI[16:31]", octeon_msi_interrupt0))
                         panic("request_irq(OCTEON_IRQ_PCI_MSI1) failed");
 
-                if (request_irq(OCTEON_IRQ_PCI_MSI2, octeon_msi_interrupt,
-                                IRQF_SHARED,
-                                "MSI[32:47]", octeon_msi_interrupt))
+                if (request_irq(OCTEON_IRQ_PCI_MSI2, octeon_msi_interrupt0,
+                                0, "MSI[32:47]", octeon_msi_interrupt0))
                         panic("request_irq(OCTEON_IRQ_PCI_MSI2) failed");
 
-                if (request_irq(OCTEON_IRQ_PCI_MSI3, octeon_msi_interrupt,
-                                IRQF_SHARED,
-                                "MSI[48:63]", octeon_msi_interrupt))
+                if (request_irq(OCTEON_IRQ_PCI_MSI3, octeon_msi_interrupt0,
+                                0, "MSI[48:63]", octeon_msi_interrupt0))
                         panic("request_irq(OCTEON_IRQ_PCI_MSI3) failed");
-
+                msi_irq_size = 64;
         }
         return 0;
 }
-
 subsys_initcall(octeon_msi_initialize);
diff --git a/arch/mips/pci/ops-titan-ht.c b/arch/mips/pci/ops-titan-ht.c
index 749c1922d420..57d54adc9e20 100644
--- a/arch/mips/pci/ops-titan-ht.c
+++ b/arch/mips/pci/ops-titan-ht.c
@@ -32,7 +32,7 @@
 #include <asm/titan_dep.h>
 
 static int titan_ht_config_read_dword(struct pci_bus *bus, unsigned int devfn,
-        int offset, u32 * val)
+        int offset, u32 *val)
 {
         volatile uint32_t address;
         int busno;
@@ -64,7 +64,7 @@ static int titan_ht_config_read_dword(struct pci_bus *bus, unsigned int devfn,
 }
 
 static int titan_ht_config_read(struct pci_bus *bus, unsigned int devfn,
-        int offset, int size, u32 * val)
+        int offset, int size, u32 *val)
 {
         uint32_t dword;
 
diff --git a/arch/mips/pci/pcie-octeon.c b/arch/mips/pci/pcie-octeon.c
index 6aa5c542d52d..861361e0c9af 100644
--- a/arch/mips/pci/pcie-octeon.c
+++ b/arch/mips/pci/pcie-octeon.c
@@ -402,6 +402,10 @@ static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
         npei_ctl_status2.s.mps = 0;
         /* Max read request size = 128 bytes for best Octeon DMA performance */
         npei_ctl_status2.s.mrrs = 0;
+        if (pcie_port)
+                npei_ctl_status2.s.c1_b1_s = 3; /* Port1 BAR1 Size 256MB */
+        else
+                npei_ctl_status2.s.c0_b1_s = 3; /* Port0 BAR1 Size 256MB */
         cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS2, npei_ctl_status2.u64);
 
         /* ECRC Generation (PCIE*_CFG070[GE,CE]) */
@@ -666,6 +670,8 @@ static int __cvmx_pcie_rc_initialize_link(int pcie_port)
 static int cvmx_pcie_rc_initialize(int pcie_port)
 {
         int i;
+        int base;
+        u64 addr_swizzle;
         union cvmx_ciu_soft_prst ciu_soft_prst;
         union cvmx_pescx_bist_status pescx_bist_status;
         union cvmx_pescx_bist_status2 pescx_bist_status2;
@@ -674,6 +680,7 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
         union cvmx_npei_mem_access_subidx mem_access_subid;
         union cvmx_npei_dbg_data npei_dbg_data;
         union cvmx_pescx_ctl_status2 pescx_ctl_status2;
+        union cvmx_npei_bar1_indexx bar1_index;
 
         /*
          * Make sure we aren't trying to setup a target mode interface
@@ -918,12 +925,30 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
         /* Set Octeon's BAR0 to decode 0-16KB. It overlaps with Bar2 */
         cvmx_write_csr(CVMX_PESCX_P2N_BAR0_START(pcie_port), 0);
 
-        /*
-         * Disable Octeon's BAR1. It isn't needed in RC mode since
-         * BAR2 maps all of memory. BAR2 also maps 256MB-512MB into
-         * the 2nd 256MB of memory.
-         */
-        cvmx_write_csr(CVMX_PESCX_P2N_BAR1_START(pcie_port), -1);
+        /* BAR1 follows BAR2 with a gap. */
+        cvmx_write_csr(CVMX_PESCX_P2N_BAR1_START(pcie_port), CVMX_PCIE_BAR1_RC_BASE);
+
+        bar1_index.u32 = 0;
+        bar1_index.s.addr_idx = (CVMX_PCIE_BAR1_PHYS_BASE >> 22);
+        bar1_index.s.ca = 1;       /* Not Cached */
+        bar1_index.s.end_swp = 1;  /* Endian Swap mode */
+        bar1_index.s.addr_v = 1;   /* Valid entry */
+
+        base = pcie_port ? 16 : 0;
+
+        /* Big endian swizzle for 32-bit PEXP_NCB register. */
+#ifdef __MIPSEB__
+        addr_swizzle = 4;
+#else
+        addr_swizzle = 0;
+#endif
+        for (i = 0; i < 16; i++) {
+                cvmx_write64_uint32((CVMX_PEXP_NPEI_BAR1_INDEXX(base) ^ addr_swizzle),
+                                    bar1_index.u32);
+                base++;
+                /* 256MB / 16 >> 22 == 4 */
+                bar1_index.s.addr_idx += (((1ull << 28) / 16ull) >> 22);
+        }
 
         /*
          * Set Octeon's BAR2 to decode 0-2^39. Bar0 and Bar1 take
diff --git a/arch/mips/pmc-sierra/Platform b/arch/mips/pmc-sierra/Platform
new file mode 100644
index 000000000000..f092f2524c5f
--- /dev/null
+++ b/arch/mips/pmc-sierra/Platform
@@ -0,0 +1,14 @@
+#
+# PMC-Sierra MSP SOCs
+#
+platform-$(CONFIG_PMC_MSP)      += pmc-sierra/msp71xx/
+cflags-$(CONFIG_PMC_MSP)        += -I$(srctree)/arch/mips/include/asm/pmc-sierra/msp71xx \
+                                        -mno-branch-likely
+load-$(CONFIG_PMC_MSP)          += 0xffffffff80100000
+
+#
+# PMC-Sierra Yosemite
+#
+platform-$(CONFIG_PMC_YOSEMITE) += pmc-sierra/yosemite/
+cflags-$(CONFIG_PMC_YOSEMITE)   += -I$(srctree)/arch/mips/include/asm/mach-yosemite
+load-$(CONFIG_PMC_YOSEMITE)     += 0xffffffff80100000
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_hwbutton.c b/arch/mips/pmc-sierra/msp71xx/msp_hwbutton.c
index 11769b55438c..c841f083a7f5 100644
--- a/arch/mips/pmc-sierra/msp71xx/msp_hwbutton.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_hwbutton.c
@@ -32,9 +32,6 @@
 #include <msp_int.h>
 #include <msp_regs.h>
 #include <msp_regops.h>
-#ifdef CONFIG_PMCTWILED
-#include <msp_led_macros.h>
-#endif
 
 /* For hwbutton_interrupt->initial_state */
 #define HWBUTTON_HI     0x1
@@ -82,10 +79,6 @@ static void standby_on(void *data)
         printk(KERN_WARNING "STANDBY switch was set to ON (not implemented)\n");
 
         /* TODO: Put board in standby mode */
-#ifdef CONFIG_PMCTWILED
-        msp_led_turn_off(MSP_LED_PWRSTANDBY_GREEN);
-        msp_led_turn_on(MSP_LED_PWRSTANDBY_RED);
-#endif
 }
 
 static void standby_off(void *data)
@@ -94,10 +87,6 @@ static void standby_off(void *data)
                 "STANDBY switch was set to OFF (not implemented)\n");
 
         /* TODO: Take out of standby mode */
-#ifdef CONFIG_PMCTWILED
-        msp_led_turn_on(MSP_LED_PWRSTANDBY_GREEN);
-        msp_led_turn_off(MSP_LED_PWRSTANDBY_RED);
-#endif
 }
 
 static struct hwbutton_interrupt softreset_sw = {
diff --git a/arch/mips/pmc-sierra/yosemite/ht-irq.c b/arch/mips/pmc-sierra/yosemite/ht-irq.c
index 5aec4057314e..86b98e98fb4f 100644
--- a/arch/mips/pmc-sierra/yosemite/ht-irq.c
+++ b/arch/mips/pmc-sierra/yosemite/ht-irq.c
@@ -35,18 +35,17 @@
  */
 void __init titan_ht_pcibios_fixup_bus(struct pci_bus *bus)
 {
-        struct pci_bus *current_bus = bus;
-        struct pci_dev *devices;
-        struct list_head *devices_link;
+        struct pci_bus *current_bus = bus;
+        struct pci_dev *devices;
+        struct list_head *devices_link;
 
         list_for_each(devices_link, &(current_bus->devices)) {
-                devices = pci_dev_b(devices_link);
-                if (devices == NULL)
-                        continue;
+                devices = pci_dev_b(devices_link);
+                if (devices == NULL)
+                        continue;
         }
 
         /*
          * PLX and SPKT related changes go here
          */
-
 }
diff --git a/arch/mips/pmc-sierra/yosemite/irq.c b/arch/mips/pmc-sierra/yosemite/irq.c
index 51021cfd04bc..25bbbf428be9 100644
--- a/arch/mips/pmc-sierra/yosemite/irq.c
+++ b/arch/mips/pmc-sierra/yosemite/irq.c
@@ -150,8 +150,4 @@ void __init arch_init_irq(void)
         mips_cpu_irq_init();
         rm7k_cpu_irq_init();
         rm9k_cpu_irq_init();
-
-#ifdef CONFIG_GDB_CONSOLE
-        register_gdb_console();
-#endif
 }
diff --git a/arch/mips/pnx833x/Makefile b/arch/mips/pnx833x/Makefile
new file mode 100644
index 000000000000..02c4698cab05
--- /dev/null
+++ b/arch/mips/pnx833x/Makefile
@@ -0,0 +1,3 @@
+obj-$(CONFIG_SOC_PNX833X)       += common/
+obj-$(CONFIG_NXP_STB220)        += stb22x/
+obj-$(CONFIG_NXP_STB225)        += stb22x/
diff --git a/arch/mips/pnx833x/Platform b/arch/mips/pnx833x/Platform
new file mode 100644
index 000000000000..7e6ec4dbc8dd
--- /dev/null
+++ b/arch/mips/pnx833x/Platform
@@ -0,0 +1,5 @@
+# NXP STB225
+platform-$(CONFIG_SOC_PNX833X)  += pnx833x/
+cflags-$(CONFIG_SOC_PNX833X)    += -Iarch/mips/include/asm/mach-pnx833x
+load-$(CONFIG_NXP_STB220)       += 0xffffffff80001000
+load-$(CONFIG_NXP_STB225)       += 0xffffffff80001000
diff --git a/arch/mips/nxp/pnx833x/common/Makefile b/arch/mips/pnx833x/common/Makefile
index 4a16f3b503b5..1a46dd291b16 100644
--- a/arch/mips/nxp/pnx833x/common/Makefile
+++ b/arch/mips/pnx833x/common/Makefile
@@ -1,3 +1 @@
 obj-y := interrupts.o platform.o prom.o setup.o reset.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/nxp/pnx833x/common/interrupts.c b/arch/mips/pnx833x/common/interrupts.c
index 941916f8aaff..941916f8aaff 100644
--- a/arch/mips/nxp/pnx833x/common/interrupts.c
+++ b/arch/mips/pnx833x/common/interrupts.c
diff --git a/arch/mips/nxp/pnx833x/common/platform.c b/arch/mips/pnx833x/common/platform.c
index 01f8345a2069..01f8345a2069 100644
--- a/arch/mips/nxp/pnx833x/common/platform.c
+++ b/arch/mips/pnx833x/common/platform.c
diff --git a/arch/mips/nxp/pnx833x/common/prom.c b/arch/mips/pnx833x/common/prom.c
index 29969f90a6b0..29969f90a6b0 100644
--- a/arch/mips/nxp/pnx833x/common/prom.c
+++ b/arch/mips/pnx833x/common/prom.c
diff --git a/arch/mips/nxp/pnx833x/common/reset.c b/arch/mips/pnx833x/common/reset.c
index e0ea96d29fde..e0ea96d29fde 100644
--- a/arch/mips/nxp/pnx833x/common/reset.c
+++ b/arch/mips/pnx833x/common/reset.c
diff --git a/arch/mips/nxp/pnx833x/common/setup.c b/arch/mips/pnx833x/common/setup.c
index e51fbc4b644d..e51fbc4b644d 100644
--- a/arch/mips/nxp/pnx833x/common/setup.c
+++ b/arch/mips/pnx833x/common/setup.c
diff --git a/arch/mips/pnx833x/stb22x/Makefile b/arch/mips/pnx833x/stb22x/Makefile
new file mode 100644
index 000000000000..7b580060de50
--- /dev/null
+++ b/arch/mips/pnx833x/stb22x/Makefile
@@ -0,0 +1 @@
+obj-y := board.o
diff --git a/arch/mips/nxp/pnx833x/stb22x/board.c b/arch/mips/pnx833x/stb22x/board.c
index 644eb7c3210f..644eb7c3210f 100644
--- a/arch/mips/nxp/pnx833x/stb22x/board.c
+++ b/arch/mips/pnx833x/stb22x/board.c
diff --git a/arch/mips/pnx8550/Makefile b/arch/mips/pnx8550/Makefile
new file mode 100644
index 000000000000..3f7e8561437b
--- /dev/null
+++ b/arch/mips/pnx8550/Makefile
@@ -0,0 +1,3 @@
+obj-$(CONFIG_SOC_PNX8550)       += common/
+obj-$(CONFIG_PNX8550_JBS)       += jbs/
+obj-$(CONFIG_PNX8550_STB810)    += stb810/
diff --git a/arch/mips/pnx8550/Platform b/arch/mips/pnx8550/Platform
new file mode 100644
index 000000000000..0e7fbde768d5
--- /dev/null
+++ b/arch/mips/pnx8550/Platform
@@ -0,0 +1,7 @@
+platform-$(CONFIG_SOC_PNX8550)  += pnx8550/
+
+cflags-$(CONFIG_SOC_PNX8550)    +=                                      \
+                -I$(srctree)/arch/mips/include/asm/mach-pnx8550
+
+load-$(CONFIG_PNX8550_JBS)      += 0xffffffff80060000
+load-$(CONFIG_PNX8550_STB810)   += 0xffffffff80060000
diff --git a/arch/mips/nxp/pnx8550/common/Makefile b/arch/mips/pnx8550/common/Makefile
index dd9e7b1f7fd3..f8ce695dc54f 100644
--- a/arch/mips/nxp/pnx8550/common/Makefile
+++ b/arch/mips/pnx8550/common/Makefile
@@ -24,5 +24,3 @@
 
 obj-y := setup.o prom.o int.o reset.o time.o proc.o platform.o
 obj-$(CONFIG_PCI) += pci.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/nxp/pnx8550/common/int.c b/arch/mips/pnx8550/common/int.c
index cfed5051dc6d..cfed5051dc6d 100644
--- a/arch/mips/nxp/pnx8550/common/int.c
+++ b/arch/mips/pnx8550/common/int.c
diff --git a/arch/mips/pnx8550/common/pci.c b/arch/mips/pnx8550/common/pci.c
new file mode 100644
index 000000000000..98e86ddb86cc
--- /dev/null
+++ b/arch/mips/pnx8550/common/pci.c
@@ -0,0 +1,134 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *
+ * Author: source@mvista.com
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ */
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <pci.h>
+#include <glb.h>
+#include <nand.h>
+
+static struct resource pci_io_resource = {
+        .start  = PNX8550_PCIIO + 0x1000,       /* reserve regacy I/O space */
+        .end    = PNX8550_PCIIO + PNX8550_PCIIO_SIZE,
+        .name   = "pci IO space",
+        .flags  = IORESOURCE_IO
+};
+
+static struct resource pci_mem_resource = {
+        .start  = PNX8550_PCIMEM,
+        .end    = PNX8550_PCIMEM + PNX8550_PCIMEM_SIZE - 1,
+        .name   = "pci memory space",
+        .flags  = IORESOURCE_MEM
+};
+
+extern struct pci_ops pnx8550_pci_ops;
+
+static struct pci_controller pnx8550_controller = {
+        .pci_ops        = &pnx8550_pci_ops,
+        .io_map_base    = PNX8550_PORT_BASE,
+        .io_resource    = &pci_io_resource,
+        .mem_resource   = &pci_mem_resource,
+};
+
+/* Return the total size of DRAM-memory, (RANK0 + RANK1) */
+static inline unsigned long get_system_mem_size(void)
+{
+        /* Read IP2031_RANK0_ADDR_LO */
+        unsigned long dram_r0_lo = inl(PCI_BASE | 0x65010);
+        /* Read IP2031_RANK1_ADDR_HI */
+        unsigned long dram_r1_hi = inl(PCI_BASE | 0x65018);
+
+        return dram_r1_hi - dram_r0_lo + 1;
+}
+
+static int __init pnx8550_pci_setup(void)
+{
+        int pci_mem_code;
+        int mem_size = get_system_mem_size() >> 20;
+
+        /* Clear the Global 2 Register, PCI Inta Output Enable Registers
+           Bit 1:Enable DAC Powerdown
+          -> 0:DACs are enabled and are working normally
+             1:DACs are powerdown
+           Bit 0:Enable of PCI inta output
+          -> 0 = Disable PCI inta output
+             1 = Enable PCI inta output
+        */
+        PNX8550_GLB2_ENAB_INTA_O = 0;
+
+        /* Calc the PCI mem size code */
+        if (mem_size >= 128)
+                pci_mem_code = SIZE_128M;
+        else if (mem_size >= 64)
+                pci_mem_code = SIZE_64M;
+        else if (mem_size >= 32)
+                pci_mem_code = SIZE_32M;
+        else
+                pci_mem_code = SIZE_16M;
+
+        /* Set PCI_XIO registers */
+        outl(pci_mem_resource.start, PCI_BASE | PCI_BASE1_LO);
+        outl(pci_mem_resource.end + 1, PCI_BASE | PCI_BASE1_HI);
+        outl(pci_io_resource.start, PCI_BASE | PCI_BASE2_LO);
+        outl(pci_io_resource.end, PCI_BASE | PCI_BASE2_HI);
+
+        /* Send memory transaction via PCI_BASE2 */
+        outl(0x00000001, PCI_BASE | PCI_IO);
+
+        /* Unlock the setup register */
+        outl(0xca, PCI_BASE | PCI_UNLOCKREG);
+
+        /*
+         * BAR0 of PNX8550 (pci base 10) must be zero in order for ide
+         * to work, and in order for bus_to_baddr to work without any
+         * hacks.
+         */
+        outl(0x00000000, PCI_BASE | PCI_BASE10);
+
+        /*
+         *These two bars are set by default or the boot code.
+         * However, it's safer to set them here so we're not boot
+         * code dependent.
+         */
+        outl(0x1be00000, PCI_BASE | PCI_BASE14);  /* PNX MMIO */
+        outl(PNX8550_NAND_BASE_ADDR, PCI_BASE | PCI_BASE18);  /* XIO      */
+
+        outl(PCI_EN_TA |
+             PCI_EN_PCI2MMI |
+             PCI_EN_XIO |
+             PCI_SETUP_BASE18_SIZE(SIZE_32M) |
+             PCI_SETUP_BASE18_EN |
+             PCI_SETUP_BASE14_EN |
+             PCI_SETUP_BASE10_PREF |
+             PCI_SETUP_BASE10_SIZE(pci_mem_code) |
+             PCI_SETUP_CFGMANAGE_EN |
+             PCI_SETUP_PCIARB_EN,
+             PCI_BASE |
+             PCI_SETUP);        /* PCI_SETUP */
+        outl(0x00000000, PCI_BASE | PCI_CTRL);  /* PCI_CONTROL */
+
+        register_pci_controller(&pnx8550_controller);
+
+        return 0;
+}
+
+arch_initcall(pnx8550_pci_setup);
diff --git a/arch/mips/nxp/pnx8550/common/platform.c b/arch/mips/pnx8550/common/platform.c
index 5264cc09a27b..5264cc09a27b 100644
--- a/arch/mips/nxp/pnx8550/common/platform.c
+++ b/arch/mips/pnx8550/common/platform.c
diff --git a/arch/mips/nxp/pnx8550/common/proc.c b/arch/mips/pnx8550/common/proc.c
index 3bba5ec828e8..3bba5ec828e8 100644
--- a/arch/mips/nxp/pnx8550/common/proc.c
+++ b/arch/mips/pnx8550/common/proc.c
diff --git a/arch/mips/nxp/pnx8550/common/prom.c b/arch/mips/pnx8550/common/prom.c
index 32f70097c3c7..32f70097c3c7 100644
--- a/arch/mips/nxp/pnx8550/common/prom.c
+++ b/arch/mips/pnx8550/common/prom.c
diff --git a/arch/mips/nxp/pnx8550/common/reset.c b/arch/mips/pnx8550/common/reset.c
index fadd8744a6bc..fadd8744a6bc 100644
--- a/arch/mips/nxp/pnx8550/common/reset.c
+++ b/arch/mips/pnx8550/common/reset.c
diff --git a/arch/mips/pnx8550/common/setup.c b/arch/mips/pnx8550/common/setup.c
new file mode 100644
index 000000000000..64246c9c875c
--- /dev/null
+++ b/arch/mips/pnx8550/common/setup.c
@@ -0,0 +1,145 @@
+/*
+ *
+ * 2.6 port, Embedded Alley Solutions, Inc
+ *
+ *  Based on Per Hallsmark, per.hallsmark@mvista.com
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ */
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/ioport.h>
+#include <linux/irq.h>
+#include <linux/mm.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/serial_pnx8xxx.h>
+#include <linux/pm.h>
+
+#include <asm/cpu.h>
+#include <asm/bootinfo.h>
+#include <asm/irq.h>
+#include <asm/mipsregs.h>
+#include <asm/reboot.h>
+#include <asm/pgtable.h>
+#include <asm/time.h>
+
+#include <glb.h>
+#include <int.h>
+#include <pci.h>
+#include <uart.h>
+#include <nand.h>
+
+extern void __init board_setup(void);
+extern void pnx8550_machine_restart(char *);
+extern void pnx8550_machine_halt(void);
+extern void pnx8550_machine_power_off(void);
+extern struct resource ioport_resource;
+extern struct resource iomem_resource;
+extern char *prom_getcmdline(void);
+
+struct resource standard_io_resources[] = {
+        {
+                .start  = 0x00,
+                .end    = 0x1f,
+                .name   = "dma1",
+                .flags  = IORESOURCE_BUSY
+        }, {
+                .start  = 0x40,
+                .end    = 0x5f,
+                .name   = "timer",
+                .flags  = IORESOURCE_BUSY
+        }, {
+                .start  = 0x80,
+                .end    = 0x8f,
+                .name   = "dma page reg",
+                .flags  = IORESOURCE_BUSY
+        }, {
+                .start  = 0xc0,
+                .end    = 0xdf,
+                .name   = "dma2",
+                .flags  = IORESOURCE_BUSY
+        },
+};
+
+#define STANDARD_IO_RESOURCES ARRAY_SIZE(standard_io_resources)
+
+extern struct resource pci_io_resource;
+extern struct resource pci_mem_resource;
+
+/* Return the total size of DRAM-memory, (RANK0 + RANK1) */
+unsigned long get_system_mem_size(void)
+{
+        /* Read IP2031_RANK0_ADDR_LO */
+        unsigned long dram_r0_lo = inl(PCI_BASE | 0x65010);
+        /* Read IP2031_RANK1_ADDR_HI */
+        unsigned long dram_r1_hi = inl(PCI_BASE | 0x65018);
+
+        return dram_r1_hi - dram_r0_lo + 1;
+}
+
+int pnx8550_console_port = -1;
+
+void __init plat_mem_setup(void)
+{
+        int i;
+        char* argptr;
+
+        board_setup();  /* board specific setup */
+
+        _machine_restart = pnx8550_machine_restart;
+        _machine_halt = pnx8550_machine_halt;
+        pm_power_off = pnx8550_machine_power_off;
+
+        /* Clear the Global 2 Register, PCI Inta Output Enable Registers
+           Bit 1:Enable DAC Powerdown
+          -> 0:DACs are enabled and are working normally
+             1:DACs are powerdown
+           Bit 0:Enable of PCI inta output
+          -> 0 = Disable PCI inta output
+             1 = Enable PCI inta output
+        */
+        PNX8550_GLB2_ENAB_INTA_O = 0;
+
+        /* IO/MEM resources. */
+        set_io_port_base(PNX8550_PORT_BASE);
+        ioport_resource.start = 0;
+        ioport_resource.end = ~0;
+        iomem_resource.start = 0;
+        iomem_resource.end = ~0;
+
+        /* Request I/O space for devices on this board */
+        for (i = 0; i < STANDARD_IO_RESOURCES; i++)
+                request_resource(&ioport_resource, standard_io_resources + i);
+
+        /* Place the Mode Control bit for GPIO pin 16 in primary function */
+        /* Pin 16 is used by UART1, UA1_TX                                */
+        outl((PNX8550_GPIO_MODE_PRIMOP << PNX8550_GPIO_MC_16_BIT) |
+                        (PNX8550_GPIO_MODE_PRIMOP << PNX8550_GPIO_MC_17_BIT),
+                        PNX8550_GPIO_MC1);
+
+        argptr = prom_getcmdline();
+        if ((argptr = strstr(argptr, "console=ttyS")) != NULL) {
+                argptr += strlen("console=ttyS");
+                pnx8550_console_port = *argptr == '0' ? 0 : 1;
+
+                /* We must initialize the UART (console) before early printk */
+                /* Set LCR to 8-bit and BAUD to 38400 (no 5)                */
+                ip3106_lcr(UART_BASE, pnx8550_console_port) =
+                        PNX8XXX_UART_LCR_8BIT;
+                ip3106_baud(UART_BASE, pnx8550_console_port) = 5;
+        }
+
+        return;
+}
diff --git a/arch/mips/nxp/pnx8550/common/time.c b/arch/mips/pnx8550/common/time.c
index 8836c6203df0..8836c6203df0 100644
--- a/arch/mips/nxp/pnx8550/common/time.c
+++ b/arch/mips/pnx8550/common/time.c
diff --git a/arch/mips/pnx8550/jbs/Makefile b/arch/mips/pnx8550/jbs/Makefile
new file mode 100644
index 000000000000..c4dc3d53eb5c
--- /dev/null
+++ b/arch/mips/pnx8550/jbs/Makefile
@@ -0,0 +1,4 @@
+
+# Makefile for the NXP JBS Board.
+
+obj-y := init.o board_setup.o irqmap.o
diff --git a/arch/mips/nxp/pnx8550/jbs/board_setup.c b/arch/mips/pnx8550/jbs/board_setup.c
index 57dd903ca408..57dd903ca408 100644
--- a/arch/mips/nxp/pnx8550/jbs/board_setup.c
+++ b/arch/mips/pnx8550/jbs/board_setup.c
diff --git a/arch/mips/nxp/pnx8550/jbs/init.c b/arch/mips/pnx8550/jbs/init.c
index d59b4a4e5e8b..d59b4a4e5e8b 100644
--- a/arch/mips/nxp/pnx8550/jbs/init.c
+++ b/arch/mips/pnx8550/jbs/init.c
diff --git a/arch/mips/nxp/pnx8550/jbs/irqmap.c b/arch/mips/pnx8550/jbs/irqmap.c
index 7fc89842002c..7fc89842002c 100644
--- a/arch/mips/nxp/pnx8550/jbs/irqmap.c
+++ b/arch/mips/pnx8550/jbs/irqmap.c
diff --git a/arch/mips/pnx8550/stb810/Makefile b/arch/mips/pnx8550/stb810/Makefile
new file mode 100644
index 000000000000..cb4ff022f1fb
--- /dev/null
+++ b/arch/mips/pnx8550/stb810/Makefile
@@ -0,0 +1,4 @@
+
+# Makefile for the NXP STB810 Board.
+
+obj-y := prom_init.o board_setup.o irqmap.o
diff --git a/arch/mips/nxp/pnx8550/stb810/board_setup.c b/arch/mips/pnx8550/stb810/board_setup.c
index af2a55e0b4e9..af2a55e0b4e9 100644
--- a/arch/mips/nxp/pnx8550/stb810/board_setup.c
+++ b/arch/mips/pnx8550/stb810/board_setup.c
diff --git a/arch/mips/nxp/pnx8550/stb810/irqmap.c b/arch/mips/pnx8550/stb810/irqmap.c
index 8c034963ddcd..8c034963ddcd 100644
--- a/arch/mips/nxp/pnx8550/stb810/irqmap.c
+++ b/arch/mips/pnx8550/stb810/irqmap.c
diff --git a/arch/mips/nxp/pnx8550/stb810/prom_init.c b/arch/mips/pnx8550/stb810/prom_init.c
index ca7f4ada0640..ca7f4ada0640 100644
--- a/arch/mips/nxp/pnx8550/stb810/prom_init.c
+++ b/arch/mips/pnx8550/stb810/prom_init.c
diff --git a/arch/mips/powertv/Makefile b/arch/mips/powertv/Makefile
index 0a0d73c0564f..baf6e9092a9f 100644
--- a/arch/mips/powertv/Makefile
+++ b/arch/mips/powertv/Makefile
@@ -23,6 +23,9 @@
 # under Linux.
 #
 
-obj-y += init.o memory.o reset.o time.o powertv_setup.o asic/ pci/
+obj-y += init.o ioremap.o memory.o powertv_setup.o reset.o time.o \
+        asic/ pci/
 
-EXTRA_CFLAGS += -Wall -Werror
+obj-$(CONFIG_USB) += powertv-usb.o
+
+EXTRA_CFLAGS += -Wall
diff --git a/arch/mips/powertv/Platform b/arch/mips/powertv/Platform
new file mode 100644
index 000000000000..4eb5af1d8eea
--- /dev/null
+++ b/arch/mips/powertv/Platform
@@ -0,0 +1,7 @@
+#
+# Cisco PowerTV Platform
+#
+platform-$(CONFIG_POWERTV)      += powertv/
+cflags-$(CONFIG_POWERTV)        +=                                      \
+                -I$(srctree)/arch/mips/include/asm/mach-powertv
+load-$(CONFIG_POWERTV)          += 0xffffffff90800000
diff --git a/arch/mips/powertv/asic/Makefile b/arch/mips/powertv/asic/Makefile
index bebfdcff0443..f0e95dc0ac97 100644
--- a/arch/mips/powertv/asic/Makefile
+++ b/arch/mips/powertv/asic/Makefile
@@ -16,8 +16,8 @@
 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 #
 
-obj-y += asic-calliope.o asic-cronus.o asic-zeus.o asic_devices.o asic_int.o \
-         irq_asic.o prealloc-calliope.o prealloc-cronus.o \
-         prealloc-cronuslite.o prealloc-zeus.o
+obj-y += asic-calliope.o asic-cronus.o asic-gaia.o asic-zeus.o \
+        asic_devices.o asic_int.o irq_asic.o prealloc-calliope.o \
+        prealloc-cronus.o prealloc-cronuslite.o prealloc-gaia.o prealloc-zeus.o
 
 EXTRA_CFLAGS += -Wall -Werror
diff --git a/arch/mips/powertv/asic/asic-calliope.c b/arch/mips/powertv/asic/asic-calliope.c
index 1ae6623444b2..0a170e0ffeaa 100644
--- a/arch/mips/powertv/asic/asic-calliope.c
+++ b/arch/mips/powertv/asic/asic-calliope.c
@@ -77,7 +77,7 @@ const struct register_map calliope_register_map __initdata = {
         .int_docsis_en = {.phys = CALLIOPE_ADDR(0xA028F4)},
 
         .mips_pll_setup = {.phys = CALLIOPE_ADDR(0x980000)},
-        .usb_fs = {.phys = CALLIOPE_ADDR(0x980030)},
+        .fs432x4b4_usb_ctl = {.phys = CALLIOPE_ADDR(0x980030)},
         .test_bus = {.phys = CALLIOPE_ADDR(0x9800CC)},
         .crt_spare = {.phys = CALLIOPE_ADDR(0x9800d4)},
         .usb2_ohci_int_mask = {.phys = CALLIOPE_ADDR(0x9A000c)},
diff --git a/arch/mips/powertv/asic/asic-cronus.c b/arch/mips/powertv/asic/asic-cronus.c
index 5bb64bfb508b..bbc0c122be5e 100644
--- a/arch/mips/powertv/asic/asic-cronus.c
+++ b/arch/mips/powertv/asic/asic-cronus.c
@@ -77,13 +77,13 @@ const struct register_map cronus_register_map __initdata = {
         .int_docsis_en = {.phys = CRONUS_ADDR(0x2A28F4)},
 
         .mips_pll_setup = {.phys = CRONUS_ADDR(0x1C0000)},
-        .usb_fs = {.phys = CRONUS_ADDR(0x1C0018)},
+        .fs432x4b4_usb_ctl = {.phys = CRONUS_ADDR(0x1C0028)},
         .test_bus = {.phys = CRONUS_ADDR(0x1C00CC)},
         .crt_spare = {.phys = CRONUS_ADDR(0x1c00d4)},
         .usb2_ohci_int_mask = {.phys = CRONUS_ADDR(0x20000C)},
         .usb2_strap = {.phys = CRONUS_ADDR(0x200014)},
         .ehci_hcapbase = {.phys = CRONUS_ADDR(0x21FE00)},
-        .ohci_hc_revision = {.phys = CRONUS_ADDR(0x1E0000)},
+        .ohci_hc_revision = {.phys = CRONUS_ADDR(0x21fc00)},
         .bcm1_bs_lmi_steer = {.phys = CRONUS_ADDR(0x2E0008)},
         .usb2_control = {.phys = CRONUS_ADDR(0x2E004C)},
         .usb2_stbus_obc = {.phys = CRONUS_ADDR(0x21FF00)},
diff --git a/arch/mips/powertv/asic/asic-gaia.c b/arch/mips/powertv/asic/asic-gaia.c
new file mode 100644
index 000000000000..91dda682752c
--- /dev/null
+++ b/arch/mips/powertv/asic/asic-gaia.c
@@ -0,0 +1,96 @@
+/*
+ * Locations of devices in the Gaia ASIC
+ *
+ * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ * Author:       David VomLehn
+ */
+
+#include <linux/init.h>
+#include <asm/mach-powertv/asic.h>
+
+const struct register_map gaia_register_map __initdata = {
+        .eic_slow0_strt_add = {.phys = GAIA_IO_BASE + 0x000000},
+        .eic_cfg_bits = {.phys = GAIA_IO_BASE + 0x000038},
+        .eic_ready_status = {.phys = GAIA_IO_BASE + 0x00004C},
+
+        .chipver3 = {.phys = GAIA_IO_BASE + 0x2A0800},
+        .chipver2 = {.phys = GAIA_IO_BASE + 0x2A0804},
+        .chipver1 = {.phys = GAIA_IO_BASE + 0x2A0808},
+        .chipver0 = {.phys = GAIA_IO_BASE + 0x2A080C},
+
+        /* The registers of IRBlaster */
+        .uart1_intstat = {.phys = GAIA_IO_BASE + 0x2A1800},
+        .uart1_inten = {.phys = GAIA_IO_BASE + 0x2A1804},
+        .uart1_config1 = {.phys = GAIA_IO_BASE + 0x2A1808},
+        .uart1_config2 = {.phys = GAIA_IO_BASE + 0x2A180C},
+        .uart1_divisorhi = {.phys = GAIA_IO_BASE + 0x2A1810},
+        .uart1_divisorlo = {.phys = GAIA_IO_BASE + 0x2A1814},
+        .uart1_data = {.phys = GAIA_IO_BASE + 0x2A1818},
+        .uart1_status = {.phys = GAIA_IO_BASE + 0x2A181C},
+
+        .int_stat_3 = {.phys = GAIA_IO_BASE + 0x2A2800},
+        .int_stat_2 = {.phys = GAIA_IO_BASE + 0x2A2804},
+        .int_stat_1 = {.phys = GAIA_IO_BASE + 0x2A2808},
+        .int_stat_0 = {.phys = GAIA_IO_BASE + 0x2A280C},
+        .int_config = {.phys = GAIA_IO_BASE + 0x2A2810},
+        .int_int_scan = {.phys = GAIA_IO_BASE + 0x2A2818},
+        .ien_int_3 = {.phys = GAIA_IO_BASE + 0x2A2830},
+        .ien_int_2 = {.phys = GAIA_IO_BASE + 0x2A2834},
+        .ien_int_1 = {.phys = GAIA_IO_BASE + 0x2A2838},
+        .ien_int_0 = {.phys = GAIA_IO_BASE + 0x2A283C},
+        .int_level_3_3 = {.phys = GAIA_IO_BASE + 0x2A2880},
+        .int_level_3_2 = {.phys = GAIA_IO_BASE + 0x2A2884},
+        .int_level_3_1 = {.phys = GAIA_IO_BASE + 0x2A2888},
+        .int_level_3_0 = {.phys = GAIA_IO_BASE + 0x2A288C},
+        .int_level_2_3 = {.phys = GAIA_IO_BASE + 0x2A2890},
+        .int_level_2_2 = {.phys = GAIA_IO_BASE + 0x2A2894},
+        .int_level_2_1 = {.phys = GAIA_IO_BASE + 0x2A2898},
+        .int_level_2_0 = {.phys = GAIA_IO_BASE + 0x2A289C},
+        .int_level_1_3 = {.phys = GAIA_IO_BASE + 0x2A28A0},
+        .int_level_1_2 = {.phys = GAIA_IO_BASE + 0x2A28A4},
+        .int_level_1_1 = {.phys = GAIA_IO_BASE + 0x2A28A8},
+        .int_level_1_0 = {.phys = GAIA_IO_BASE + 0x2A28AC},
+        .int_level_0_3 = {.phys = GAIA_IO_BASE + 0x2A28B0},
+        .int_level_0_2 = {.phys = GAIA_IO_BASE + 0x2A28B4},
+        .int_level_0_1 = {.phys = GAIA_IO_BASE + 0x2A28B8},
+        .int_level_0_0 = {.phys = GAIA_IO_BASE + 0x2A28BC},
+        .int_docsis_en = {.phys = GAIA_IO_BASE + 0x2A28F4},
+
+        .mips_pll_setup = {.phys = GAIA_IO_BASE + 0x1C0000},
+        .fs432x4b4_usb_ctl = {.phys = GAIA_IO_BASE + 0x1C0024},
+        .test_bus = {.phys = GAIA_IO_BASE + 0x1C00CC},
+        .crt_spare = {.phys = GAIA_IO_BASE + 0x1c0108},
+        .usb2_ohci_int_mask = {.phys = GAIA_IO_BASE + 0x20000C},
+        .usb2_strap = {.phys = GAIA_IO_BASE + 0x200014},
+        .ehci_hcapbase = {.phys = GAIA_IO_BASE + 0x21FE00},
+        .ohci_hc_revision = {.phys = GAIA_IO_BASE + 0x21fc00},
+        .bcm1_bs_lmi_steer = {.phys = GAIA_IO_BASE + 0x2E0004},
+        .usb2_control = {.phys = GAIA_IO_BASE + 0x2E004C},
+        .usb2_stbus_obc = {.phys = GAIA_IO_BASE + 0x21FF00},
+        .usb2_stbus_mess_size = {.phys = GAIA_IO_BASE + 0x21FF04},
+        .usb2_stbus_chunk_size = {.phys = GAIA_IO_BASE + 0x21FF08},
+
+        .pcie_regs = {.phys = GAIA_IO_BASE + 0x220000},
+        .tim_ch = {.phys = GAIA_IO_BASE + 0x2A2C10},
+        .tim_cl = {.phys = GAIA_IO_BASE + 0x2A2C14},
+        .gpio_dout = {.phys = GAIA_IO_BASE + 0x2A2C20},
+        .gpio_din = {.phys = GAIA_IO_BASE + 0x2A2C24},
+        .gpio_dir = {.phys = GAIA_IO_BASE + 0x2A2C2C},
+        .watchdog = {.phys = GAIA_IO_BASE + 0x2A2C30},
+        .front_panel = {.phys = GAIA_IO_BASE + 0x2A3800},
+};
diff --git a/arch/mips/powertv/asic/asic-zeus.c b/arch/mips/powertv/asic/asic-zeus.c
index 095cbe10ebb9..4a05bb096476 100644
--- a/arch/mips/powertv/asic/asic-zeus.c
+++ b/arch/mips/powertv/asic/asic-zeus.c
@@ -77,7 +77,7 @@ const struct register_map zeus_register_map __initdata = {
         .int_docsis_en = {.phys = ZEUS_ADDR(0x2828F4)},
 
         .mips_pll_setup = {.phys = ZEUS_ADDR(0x1a0000)},
-        .usb_fs = {.phys = ZEUS_ADDR(0x1a0018)},
+        .fs432x4b4_usb_ctl = {.phys = ZEUS_ADDR(0x1a0018)},
         .test_bus = {.phys = ZEUS_ADDR(0x1a0238)},
         .crt_spare = {.phys = ZEUS_ADDR(0x1a0090)},
         .usb2_ohci_int_mask = {.phys = ZEUS_ADDR(0x1e000c)},
diff --git a/arch/mips/powertv/asic/asic_devices.c b/arch/mips/powertv/asic/asic_devices.c
index 9ec523e4dd06..e56fa61b3991 100644
--- a/arch/mips/powertv/asic/asic_devices.c
+++ b/arch/mips/powertv/asic/asic_devices.c
@@ -1,7 +1,6 @@
 /*
- *                   ASIC Device List Intialization
  *
- * Description:  Defines the platform resources for the SA settop.
+ * Description:  Defines the platform resources for Gaia-based settops.
  *
  * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
  *
@@ -19,11 +18,6 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  *
- * Author:       Ken Eppinett
- *               David Schleef <ds@schleef.org>
- *
- * Description:  Defines the platform resources for the SA settop.
- *
  * NOTE: The bootloader allocates persistent memory at an address which is
  * 16 MiB below the end of the highest address in KSEG0. All fixed
  * address memory reservations must avoid this region.
@@ -39,7 +33,6 @@
 #include <linux/mm.h>
 #include <linux/platform_device.h>
 #include <linux/module.h>
-#include <linux/gfp.h>
 #include <asm/page.h>
 #include <linux/swap.h>
 #include <linux/highmem.h>
@@ -74,14 +67,13 @@ unsigned long asic_phy_base;
 unsigned long asic_base;
 EXPORT_SYMBOL(asic_base);                       /* Exported for testing */
 struct resource *gp_resources;
-static bool usb_configured;
 
 /*
  * Don't recommend to use it directly, it is usually used by kernel internally.
  * Portable code should be using interfaces such as ioremp, dma_map_single, etc.
  */
-unsigned long phys_to_bus_offset;
-EXPORT_SYMBOL(phys_to_bus_offset);
+unsigned long phys_to_dma_offset;
+EXPORT_SYMBOL(phys_to_dma_offset);
 
 /*
  *
@@ -97,101 +89,19 @@ struct resource asic_resource = {
 };
 
 /*
- *
- * USB Host Resource Definition
- *
- */
-
-static struct resource ehci_resources[] = {
-        {
-                .parent = &asic_resource,
-                .start  = 0,
-                .end    = 0xff,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = irq_usbehci,
-                .end    = irq_usbehci,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static u64 ehci_dmamask = DMA_BIT_MASK(32);
-
-static struct platform_device ehci_device = {
-        .name = "powertv-ehci",
-        .id = 0,
-        .num_resources = 2,
-        .resource = ehci_resources,
-        .dev = {
-                .dma_mask = &ehci_dmamask,
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-        },
-};
-
-static struct resource ohci_resources[] = {
-        {
-                .parent = &asic_resource,
-                .start  = 0,
-                .end    = 0xff,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = irq_usbohci,
-                .end    = irq_usbohci,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static u64 ohci_dmamask = DMA_BIT_MASK(32);
-
-static struct platform_device ohci_device = {
-        .name = "powertv-ohci",
-        .id = 0,
-        .num_resources = 2,
-        .resource = ohci_resources,
-        .dev = {
-                .dma_mask = &ohci_dmamask,
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-        },
-};
-
-static struct platform_device *platform_devices[] = {
-        &ehci_device,
-        &ohci_device,
-};
-
-/*
- *
- * Platform Configuration and Device Initialization
- *
- */
-static void __init fs_update(int pe, int md, int sdiv, int disable_div_by_3)
-{
-        int en_prg, byp, pwr, nsb, val;
-        int sout;
-
-        sout = 1;
-        en_prg = 1;
-        byp = 0;
-        nsb = 1;
-        pwr = 1;
-
-        val = ((sdiv << 29) | (md << 24) | (pe<<8) | (sout<<3) | (byp<<2) |
-                (nsb<<1) | (disable_div_by_3<<5));
-
-        asic_write(val, usb_fs);
-        asic_write(val | (en_prg<<4), usb_fs);
-        asic_write(val | (en_prg<<4) | pwr, usb_fs);
-}
-
-/*
  * Allow override of bootloader-specified model
+ * Returns zero on success, a negative errno value on failure.  This parameter
+ * allows overriding of the bootloader-specified model.
  */
 static char __initdata cmdline[COMMAND_LINE_SIZE];
 
 #define FORCEFAMILY_PARAM       "forcefamily"
 
+/*
+ * check_forcefamily - check for, and parse, forcefamily command line parameter
+ * @forced_family:      Pointer to two-character array in which to store the
+ *                      value of the forcedfamily parameter, if any.
+ */
 static __init int check_forcefamily(unsigned char forced_family[2])
 {
         const char *p;
@@ -231,14 +141,10 @@ static __init int check_forcefamily(unsigned char forced_family[2])
  */
 static __init noinline void platform_set_family(void)
 {
-#define BOOTLDRFAMILY(byte1, byte0) (((byte1) << 8) | (byte0))
-
         unsigned char forced_family[2];
         unsigned short bootldr_family;
 
-        check_forcefamily(forced_family);
-
-        if (forced_family[0] != '\0' && forced_family[1] != '\0')
+        if (check_forcefamily(forced_family) == 0)
                 bootldr_family = BOOTLDRFAMILY(forced_family[0],
                         forced_family[1]);
         else {
@@ -289,6 +195,9 @@ static __init noinline void platform_set_family(void)
         case BOOTLDRFAMILY('F', '1'):
                 platform_family = FAMILY_1500VZF;
                 break;
+        case BOOTLDRFAMILY('8', '7'):
+                platform_family = FAMILY_8700;
+                break;
         default:
                 platform_family = -1;
         }
@@ -301,24 +210,9 @@ unsigned int platform_get_family(void)
 EXPORT_SYMBOL(platform_get_family);
 
 /*
- * \brief usb_eye_configure() for optimizing the USB eye on Calliope.
- *
- * \param     unsigned int value saved to the register.
- *
- * \return    none
- *
- */
-static void __init usb_eye_configure(unsigned int value)
-{
-        asic_write(asic_read(crt_spare) | value, crt_spare);
-}
-
-/*
  * platform_get_asic - determine the ASIC type.
  *
- * \param     none
- *
- * \return    ASIC type; ASIC_UNKNOWN if none
+ * Returns the ASIC type, or ASIC_UNKNOWN if unknown
  *
  */
 enum asic_type platform_get_asic(void)
@@ -328,93 +222,10 @@ enum asic_type platform_get_asic(void)
 EXPORT_SYMBOL(platform_get_asic);
 
 /*
- * platform_configure_usb - usb configuration based on platform type.
- * @bcm1_usb2_ctl:      value for the BCM1_USB2_CTL register, which is
- *                      quirky
- */
-static void __init platform_configure_usb(void)
-{
-        u32 bcm1_usb2_ctl;
-
-        if (usb_configured)
-                return;
-
-        switch (asic) {
-        case ASIC_ZEUS:
-        case ASIC_CRONUS:
-        case ASIC_CRONUSLITE:
-                fs_update(0x0000, 0x11, 0x02, 0);
-                bcm1_usb2_ctl = 0x803;
-                break;
-
-        case ASIC_CALLIOPE:
-                fs_update(0x0000, 0x11, 0x02, 1);
-
-                switch (platform_family) {
-                case FAMILY_1500VZE:
-                        break;
-
-                case FAMILY_1500VZF:
-                        usb_eye_configure(0x003c0000);
-                        break;
-
-                default:
-                        usb_eye_configure(0x00300000);
-                        break;
-                }
-
-                bcm1_usb2_ctl = 0x803;
-                break;
-
-        default:
-                pr_err("Unknown ASIC type: %d\n", asic);
-                break;
-        }
-
-        /* turn on USB power */
-        asic_write(0, usb2_strap);
-        /* Enable all OHCI interrupts */
-        asic_write(bcm1_usb2_ctl, usb2_control);
-        /* USB2_STBUS_OBC store32/load32 */
-        asic_write(3, usb2_stbus_obc);
-        /* USB2_STBUS_MESS_SIZE 2 packets */
-        asic_write(1, usb2_stbus_mess_size);
-        /* USB2_STBUS_CHUNK_SIZE 2 packets */
-        asic_write(1, usb2_stbus_chunk_size);
-
-        usb_configured = true;
-}
-
-/*
- * Set up the USB EHCI interface
+ * set_register_map - set ASIC register configuration
+ * @phys_base:  Physical address of the base of the ASIC registers
+ * @map:        Description of key ASIC registers
  */
-void platform_configure_usb_ehci()
-{
-        platform_configure_usb();
-}
-
-/*
- * Set up the USB OHCI interface
- */
-void platform_configure_usb_ohci()
-{
-        platform_configure_usb();
-}
-
-/*
- * Shut the USB EHCI interface down--currently a NOP
- */
-void platform_unconfigure_usb_ehci()
-{
-}
-
-/*
- * Shut the USB OHCI interface down--currently a NOP
- */
-void platform_unconfigure_usb_ohci()
-{
-}
-
 static void __init set_register_map(unsigned long phys_base,
         const struct register_map *map)
 {
@@ -526,6 +337,15 @@ void __init configure_platform(void)
                         "DVR_CAPABLE\n");
                 break;
 
+        case FAMILY_8700:
+                platform_features = FFS_CAPABLE | PCIE_CAPABLE;
+                asic = ASIC_GAIA;
+                set_register_map(GAIA_IO_BASE, &gaia_register_map);
+                gp_resources = dvr_gaia_resources;
+
+                pr_info("Platform: 8700 - GAIA, DVR_CAPABLE\n");
+                break;
+
         default:
                 pr_crit("Platform:  UNKNOWN PLATFORM\n");
                 break;
@@ -533,10 +353,10 @@ void __init configure_platform(void)
 
         switch (asic) {
         case ASIC_ZEUS:
-                phys_to_bus_offset = 0x30000000;
+                phys_to_dma_offset = 0x30000000;
                 break;
         case ASIC_CALLIOPE:
-                phys_to_bus_offset = 0x10000000;
+                phys_to_dma_offset = 0x10000000;
                 break;
         case ASIC_CRONUSLITE:
                 /* Fall through */
@@ -546,42 +366,16 @@ void __init configure_platform(void)
                  * 0x2XXXXXXX. If 0x10000000 aliases into 0x60000000-
                  * 0x6XXXXXXX, the offset should be 0x50000000, not 0x10000000.
                  */
-                phys_to_bus_offset = 0x10000000;
+                phys_to_dma_offset = 0x10000000;
                 break;
         default:
-                phys_to_bus_offset = 0x00000000;
+                phys_to_dma_offset = 0x00000000;
                 break;
         }
 }
 
-/**
- * platform_devices_init - sets up USB device resourse.
- */
-static int __init platform_devices_init(void)
-{
-        pr_notice("%s: ----- Initializing USB resources -----\n", __func__);
-
-        asic_resource.start = asic_phy_base;
-        asic_resource.end += asic_resource.start;
-
-        ehci_resources[0].start = asic_reg_phys_addr(ehci_hcapbase);
-        ehci_resources[0].end += ehci_resources[0].start;
-
-        ohci_resources[0].start = asic_reg_phys_addr(ohci_hc_revision);
-        ohci_resources[0].end += ohci_resources[0].start;
-
-        set_io_port_base(0);
-
-        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
-
-        return 0;
-}
-
-arch_initcall(platform_devices_init);
-
 /*
- *
- * BOOTMEM ALLOCATION
+ * RESOURCE ALLOCATION
  *
  */
 /*
@@ -603,7 +397,7 @@ void __init platform_alloc_bootmem(void)
                 int size = gp_resources[i].end - gp_resources[i].start + 1;
                 if ((gp_resources[i].start != 0) &&
                         ((gp_resources[i].flags & IORESOURCE_MEM) != 0)) {
-                        reserve_bootmem(bus_to_phys(gp_resources[i].start),
+                        reserve_bootmem(dma_to_phys(gp_resources[i].start),
                                 size, 0);
                         total += gp_resources[i].end -
                                 gp_resources[i].start + 1;
@@ -627,7 +421,7 @@ void __init platform_alloc_bootmem(void)
 
                         else {
                                 gp_resources[i].start =
-                                        phys_to_bus(virt_to_phys(mem));
+                                        phys_to_dma(virt_to_phys(mem));
                                 gp_resources[i].end =
                                         gp_resources[i].start + size - 1;
                                 total += size;
@@ -691,7 +485,7 @@ static void __init pmem_setup_resource(void)
         if (resource && pmemaddr && pmemlen) {
                 /* The address provided by bootloader is in kseg0. Convert to
                  * a bus address. */
-                resource->start = phys_to_bus(pmemaddr - 0x80000000);
+                resource->start = phys_to_dma(pmemaddr - 0x80000000);
                 resource->end = resource->start + pmemlen - 1;
 
                 pr_info("persistent memory: start=0x%x  end=0x%x\n",
diff --git a/arch/mips/powertv/asic/prealloc-gaia.c b/arch/mips/powertv/asic/prealloc-gaia.c
new file mode 100644
index 000000000000..8ac8c7aeb986
--- /dev/null
+++ b/arch/mips/powertv/asic/prealloc-gaia.c
@@ -0,0 +1,589 @@
+/*
+ * Memory pre-allocations for Gaia boxes.
+ *
+ * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ * Author:       David VomLehn
+ */
+
+#include <linux/init.h>
+#include <asm/mach-powertv/asic.h>
+
+/*
+ * DVR_CAPABLE GAIA RESOURCES
+ */
+struct resource dvr_gaia_resources[] __initdata = {
+        /*
+         *
+         * VIDEO1 / LX1
+         *
+         */
+        {
+                .name   = "ST231aImage",        /* Delta-Mu 1 image and ram */
+                .start  = 0x24000000,
+                .end    = 0x241FFFFF,           /* 2MiB */
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ST231aMonitor",      /* 8KiB block ST231a monitor */
+                .start  = 0x24200000,
+                .end    = 0x24201FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "MediaMemory1",
+                .start  = 0x24202000,
+                .end    = 0x25FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * VIDEO2 / LX2
+         *
+         */
+        {
+                .name   = "ST231bImage",        /* Delta-Mu 2 image and ram */
+                .start  = 0x60000000,
+                .end    = 0x601FFFFF,           /* 2MiB */
+                .flags  = IORESOURCE_IO,
+        },
+        {
+                .name   = "ST231bMonitor",      /* 8KiB block ST231b monitor */
+                .start  = 0x60200000,
+                .end    = 0x60201FFF,
+                .flags  = IORESOURCE_IO,
+        },
+        {
+                .name   = "MediaMemory2",
+                .start  = 0x60202000,
+                .end    = 0x61FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * Sysaudio Driver
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  DSP_Image_Buff - DSP code and data images (1MB)
+         *  ADSC_CPU_PCM_Buff - ADSC CPU PCM buffer (40KB)
+         *  ADSC_AUX_Buff - ADSC AUX buffer (16KB)
+         *  ADSC_Main_Buff - ADSC Main buffer (16KB)
+         *
+         */
+        {
+                .name   = "DSP_Image_Buff",
+                .start  = 0x00000000,
+                .end    = 0x000FFFFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_CPU_PCM_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00009FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_AUX_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00003FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_Main_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00003FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * STAVEM driver/STAPI
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  This memory area is used for allocating buffers for Video decoding
+         *  purposes.  Allocation/De-allocation within this buffer is managed
+         *  by the STAVMEM driver of the STAPI.  They could be Decimated
+         *  Picture Buffers, Intermediate Buffers, as deemed necessary for
+         *  video decoding purposes, for any video decoders on Zeus.
+         *
+         */
+        {
+                .name   = "AVMEMPartition0",
+                .start  = 0x63580000,
+                .end    = 0x64180000 - 1,  /* 12 MB total */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * DOCSIS Subsystem
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Docsis -
+         *
+         */
+        {
+                .name   = "Docsis",
+                .start  = 0x62000000,
+                .end    = 0x62700000 - 1,       /* 7 MB total */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * GHW HAL Driver
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  GraphicsHeap - PowerTV Graphics Heap
+         *
+         */
+        {
+                .name   = "GraphicsHeap",
+                .start  = 0x62700000,
+                .end    = 0x63500000 - 1,       /* 14 MB total */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * multi com buffer area
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Docsis -
+         *
+         */
+        {
+                .name   = "MulticomSHM",
+                .start  = 0x26000000,
+                .end    = 0x26020000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * DMA Ring buffer
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Docsis -
+         *
+         */
+        {
+                .name   = "BMM_Buffer",
+                .start  = 0x00000000,
+                .end    = 0x00280000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * Display bins buffer for unit0
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Display Bins for unit0
+         *
+         */
+        {
+                .name   = "DisplayBins0",
+                .start  = 0x00000000,
+                .end    = 0x00000FFF,           /* 4 KB total */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * Display bins buffer
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Display Bins for unit1
+         *
+         */
+        {
+                .name   = "DisplayBins1",
+                .start  = 0x64AD4000,
+                .end    = 0x64AD5000 - 1,  /* 4 KB total */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * ITFS
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Docsis -
+         *
+         */
+        {
+                .name   = "ITFS",
+                .start  = 0x64180000,
+                /* 815,104 bytes each for 2 ITFS partitions. */
+                .end    = 0x6430DFFF,
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * AVFS
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Docsis -
+         *
+         */
+        {
+                .name   = "AvfsDmaMem",
+                .start  = 0x6430E000,
+                /* (945K * 8) = (128K *3) 5 playbacks / 3 server */
+                .end    = 0x64AD0000 - 1,
+                .flags  = IORESOURCE_IO,
+        },
+        {
+                .name   = "AvfsFileSys",
+                .start  = 0x64AD0000,
+                .end    = 0x64AD1000 - 1,  /* 4K */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * Smartcard
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Read and write buffers for Internal/External cards
+         *
+         */
+        {
+                .name   = "SmartCardInfo",
+                .start  = 0x64AD1000,
+                .end    = 0x64AD3800 - 1,
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * KAVNET
+         *    NP Reset Vector - must be of the form xxCxxxxx
+         *         NP Image - must be video bank 1
+         *         NP IPC - must be video bank 2
+         */
+        {
+                .name   = "NP_Reset_Vector",
+                .start  = 0x27c00000,
+                .end    = 0x27c01000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "NP_Image",
+                .start  = 0x27020000,
+                .end    = 0x27060000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "NP_IPC",
+                .start  = 0x63500000,
+                .end    = 0x63580000 - 1,
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         * Add other resources here
+         */
+        { },
+};
+
+/*
+ * NON_DVR_CAPABLE GAIA RESOURCES
+ */
+struct resource non_dvr_gaia_resources[] __initdata = {
+        /*
+         *
+         * VIDEO1 / LX1
+         *
+         */
+        {
+                .name   = "ST231aImage",        /* Delta-Mu 1 image and ram */
+                .start  = 0x24000000,
+                .end    = 0x241FFFFF,           /* 2MiB */
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ST231aMonitor",      /* 8KiB block ST231a monitor */
+                .start  = 0x24200000,
+                .end    = 0x24201FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "MediaMemory1",
+                .start  = 0x24202000,
+                .end    = 0x25FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * VIDEO2 / LX2
+         *
+         */
+        {
+                .name   = "ST231bImage",        /* Delta-Mu 2 image and ram */
+                .start  = 0x60000000,
+                .end    = 0x601FFFFF,           /* 2MiB */
+                .flags  = IORESOURCE_IO,
+        },
+        {
+                .name   = "ST231bMonitor",      /* 8KiB block ST231b monitor */
+                .start  = 0x60200000,
+                .end    = 0x60201FFF,
+                .flags  = IORESOURCE_IO,
+        },
+        {
+                .name   = "MediaMemory2",
+                .start  = 0x60202000,
+                .end    = 0x61FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * Sysaudio Driver
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  DSP_Image_Buff - DSP code and data images (1MB)
+         *  ADSC_CPU_PCM_Buff - ADSC CPU PCM buffer (40KB)
+         *  ADSC_AUX_Buff - ADSC AUX buffer (16KB)
+         *  ADSC_Main_Buff - ADSC Main buffer (16KB)
+         *
+         */
+        {
+                .name   = "DSP_Image_Buff",
+                .start  = 0x00000000,
+                .end    = 0x000FFFFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_CPU_PCM_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00009FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_AUX_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00003FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "ADSC_Main_Buff",
+                .start  = 0x00000000,
+                .end    = 0x00003FFF,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * STAVEM driver/STAPI
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  This memory area is used for allocating buffers for Video decoding
+         *  purposes.  Allocation/De-allocation within this buffer is managed
+         *  by the STAVMEM driver of the STAPI.  They could be Decimated
+         *  Picture Buffers, Intermediate Buffers, as deemed necessary for
+         *  video decoding purposes, for any video decoders on Zeus.
+         *
+         */
+        {
+                .name   = "AVMEMPartition0",
+                .start  = 0x63580000,
+                .end    = 0x64180000 - 1,  /* 12 MB total */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * DOCSIS Subsystem
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Docsis -
+         *
+         */
+        {
+                .name   = "Docsis",
+                .start  = 0x62000000,
+                .end    = 0x62700000 - 1,       /* 7 MB total */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * GHW HAL Driver
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  GraphicsHeap - PowerTV Graphics Heap
+         *
+         */
+        {
+                .name   = "GraphicsHeap",
+                .start  = 0x62700000,
+                .end    = 0x63500000 - 1,       /* 14 MB total */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * multi com buffer area
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Docsis -
+         *
+         */
+        {
+                .name   = "MulticomSHM",
+                .start  = 0x26000000,
+                .end    = 0x26020000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * DMA Ring buffer
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Docsis -
+         *
+         */
+        {
+                .name   = "BMM_Buffer",
+                .start  = 0x00000000,
+                .end    = 0x000AA000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * Display bins buffer for unit0
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Display Bins for unit0
+         *
+         */
+        {
+                .name   = "DisplayBins0",
+                .start  = 0x00000000,
+                .end    = 0x00000FFF,           /* 4 KB total */
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * Display bins buffer
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Display Bins for unit1
+         *
+         */
+        {
+                .name   = "DisplayBins1",
+                .start  = 0x64AD4000,
+                .end    = 0x64AD5000 - 1,  /* 4 KB total */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * AVFS: player HAL memory
+         *
+         *
+         */
+        {
+                .name   = "AvfsDmaMem",
+                .start  = 0x6430E000,
+                .end    = 0x645D2C00 - 1,  /* 945K * 3 for playback */
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * PMEM
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Persistent memory for diagnostics.
+         *
+         */
+        {
+                .name   = "DiagPersistentMemory",
+                .start  = 0x00000000,
+                .end    = 0x10000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         *
+         * Smartcard
+         *
+         * This driver requires:
+         *
+         * Arbitrary Based Buffers:
+         *  Read and write buffers for Internal/External cards
+         *
+         */
+        {
+                .name   = "SmartCardInfo",
+                .start  = 0x64AD1000,
+                .end    = 0x64AD3800 - 1,
+                .flags  = IORESOURCE_IO,
+        },
+        /*
+         *
+         * KAVNET
+         *    NP Reset Vector - must be of the form xxCxxxxx
+         *         NP Image - must be video bank 1
+         *         NP IPC - must be video bank 2
+         */
+        {
+                .name   = "NP_Reset_Vector",
+                .start  = 0x27c00000,
+                .end    = 0x27c01000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "NP_Image",
+                .start  = 0x27020000,
+                .end    = 0x27060000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "NP_IPC",
+                .start  = 0x63500000,
+                .end    = 0x63580000 - 1,
+                .flags  = IORESOURCE_IO,
+        },
+        { },
+};
diff --git a/arch/mips/powertv/init.c b/arch/mips/powertv/init.c
index 0afe227f1d0a..83552288e802 100644
--- a/arch/mips/powertv/init.c
+++ b/arch/mips/powertv/init.c
@@ -117,8 +117,10 @@ void __init prom_init(void)
         board_nmi_handler_setup = mips_nmi_setup;
         board_ejtag_handler_setup = mips_ejtag_setup;
 
-        if (prom_argc == 1)
+        if (prom_argc == 1) {
+                strlcat(arcs_cmdline, " ", COMMAND_LINE_SIZE);
                 strlcat(arcs_cmdline, prom_argv, COMMAND_LINE_SIZE);
+        }
 
         configure_platform();
         prom_meminit();
diff --git a/arch/mips/powertv/ioremap.c b/arch/mips/powertv/ioremap.c
new file mode 100644
index 000000000000..a77c6f62fe23
--- /dev/null
+++ b/arch/mips/powertv/ioremap.c
@@ -0,0 +1,136 @@
+/*
+ *                      ioremap.c
+ *
+ * Support for mapping between dma_addr_t values a phys_addr_t values.
+ *
+ * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ * Author:       David VomLehn <dvomlehn@cisco.com>
+ *
+ * Description:  Defines the platform resources for the SA settop.
+ *
+ * NOTE: The bootloader allocates persistent memory at an address which is
+ * 16 MiB below the end of the highest address in KSEG0. All fixed
+ * address memory reservations must avoid this region.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+
+#include <asm/mach-powertv/ioremap.h>
+
+/*
+ * Define the sizes of and masks for grains in physical and DMA space. The
+ * values are the same but the types are not.
+ */
+#define IOR_PHYS_GRAIN          ((phys_addr_t) 1 << IOR_LSBITS)
+#define IOR_PHYS_GRAIN_MASK     (IOR_PHYS_GRAIN - 1)
+
+#define IOR_DMA_GRAIN           ((dma_addr_t) 1 << IOR_LSBITS)
+#define IOR_DMA_GRAIN_MASK      (IOR_DMA_GRAIN - 1)
+
+/*
+ * Values that, when accessed by an index derived from a phys_addr_t and
+ * added to phys_addr_t value, yield a DMA address
+ */
+struct ior_phys_to_dma _ior_phys_to_dma[IOR_NUM_PHYS_TO_DMA];
+EXPORT_SYMBOL(_ior_phys_to_dma);
+
+/*
+ * Values that, when accessed by an index derived from a dma_addr_t and
+ * added to that dma_addr_t value, yield a physical address
+ */
+struct ior_dma_to_phys _ior_dma_to_phys[IOR_NUM_DMA_TO_PHYS];
+EXPORT_SYMBOL(_ior_dma_to_phys);
+
+/**
+ * setup_dma_to_phys - set up conversion from DMA to physical addresses
+ * @dma_idx:    Top IOR_LSBITS bits of the DMA address, i.e. an index
+ *              into the array _dma_to_phys.
+ * @delta:      Value that, when added to the DMA address, will yield the
+ *              physical address
+ * @s:          Number of bytes in the section of memory with the given delta
+ *              between DMA and physical addresses.
+ */
+static void setup_dma_to_phys(dma_addr_t dma, phys_addr_t delta, dma_addr_t s)
+{
+        int dma_idx, first_idx, last_idx;
+        phys_addr_t first, last;
+
+        /*
+         * Calculate the first and last indices, rounding the first up and
+         * the second down.
+         */
+        first = dma & ~IOR_DMA_GRAIN_MASK;
+        last = (dma + s - 1) & ~IOR_DMA_GRAIN_MASK;
+        first_idx = first >> IOR_LSBITS;                /* Convert to indices */
+        last_idx = last >> IOR_LSBITS;
+
+        for (dma_idx = first_idx; dma_idx <= last_idx; dma_idx++)
+                _ior_dma_to_phys[dma_idx].offset = delta >> IOR_DMA_SHIFT;
+}
+
+/**
+ * setup_phys_to_dma - set up conversion from DMA to physical addresses
+ * @phys_idx:   Top IOR_LSBITS bits of the DMA address, i.e. an index
+ *              into the array _phys_to_dma.
+ * @delta:      Value that, when added to the DMA address, will yield the
+ *              physical address
+ * @s:          Number of bytes in the section of memory with the given delta
+ *              between DMA and physical addresses.
+ */
+static void setup_phys_to_dma(phys_addr_t phys, dma_addr_t delta, phys_addr_t s)
+{
+        int phys_idx, first_idx, last_idx;
+        phys_addr_t first, last;
+
+        /*
+         * Calculate the first and last indices, rounding the first up and
+         * the second down.
+         */
+        first = phys & ~IOR_PHYS_GRAIN_MASK;
+        last = (phys + s - 1) & ~IOR_PHYS_GRAIN_MASK;
+        first_idx = first >> IOR_LSBITS;                /* Convert to indices */
+        last_idx = last >> IOR_LSBITS;
+
+        for (phys_idx = first_idx; phys_idx <= last_idx; phys_idx++)
+                _ior_phys_to_dma[phys_idx].offset = delta >> IOR_PHYS_SHIFT;
+}
+
+/**
+ * ioremap_add_map - add to the physical and DMA address conversion arrays
+ * @phys:       Process's view of the address of the start of the memory chunk
+ * @dma:        DMA address of the start of the memory chunk
+ * @size:       Size, in bytes, of the chunk of memory
+ *
+ * NOTE: It might be obvious, but the assumption is that all @size bytes have
+ * the same offset between the physical address and the DMA address.
+ */
+void ioremap_add_map(phys_addr_t phys, phys_addr_t dma, phys_addr_t size)
+{
+        if (size == 0)
+                return;
+
+        if ((dma & IOR_DMA_GRAIN_MASK) != 0 ||
+                (phys & IOR_PHYS_GRAIN_MASK) != 0 ||
+                (size & IOR_PHYS_GRAIN_MASK) != 0)
+                pr_crit("Memory allocation must be in chunks of 0x%x bytes\n",
+                        IOR_PHYS_GRAIN);
+
+        setup_dma_to_phys(dma, phys - dma, size);
+        setup_phys_to_dma(phys, dma - phys, size);
+}
diff --git a/arch/mips/powertv/memory.c b/arch/mips/powertv/memory.c
index f49eb3d0358b..73880ad29bc2 100644
--- a/arch/mips/powertv/memory.c
+++ b/arch/mips/powertv/memory.c
@@ -30,28 +30,141 @@
 #include <asm/sections.h>
 
 #include <asm/mips-boards/prom.h>
+#include <asm/mach-powertv/asic.h>
+#include <asm/mach-powertv/ioremap.h>
 
 #include "init.h"
 
 /* Memory constants */
 #define KIBIBYTE(n)             ((n) * 1024)    /* Number of kibibytes */
 #define MEBIBYTE(n)             ((n) * KIBIBYTE(1024)) /* Number of mebibytes */
-#define DEFAULT_MEMSIZE         MEBIBYTE(256)   /* If no memsize provided */
-#define LOW_MEM_MAX             MEBIBYTE(252)   /* Max usable low mem */
-#define RES_BOOTLDR_MEMSIZE     MEBIBYTE(1)     /* Memory reserved for bldr */
-#define BOOT_MEM_SIZE           KIBIBYTE(256)   /* Memory reserved for bldr */
-#define PHYS_MEM_START          0x10000000      /* Start of physical memory */
+#define DEFAULT_MEMSIZE         MEBIBYTE(128)   /* If no memsize provided */
 
-char __initdata cmdline[COMMAND_LINE_SIZE];
+#define BLDR_SIZE       KIBIBYTE(256)           /* Memory reserved for bldr */
+#define RV_SIZE         MEBIBYTE(4)             /* Size of reset vector */
 
-void __init prom_meminit(void)
+#define LOW_MEM_END     0x20000000              /* Highest low memory address */
+#define BLDR_ALIAS      0x10000000              /* Bootloader address */
+#define RV_PHYS         0x1fc00000              /* Reset vector address */
+#define LOW_RAM_END     RV_PHYS                 /* End of real RAM in low mem */
+
+/*
+ * Very low-level conversion from processor physical address to device
+ * DMA address for the first bank of memory.
+ */
+#define PHYS_TO_DMA(paddr)      ((paddr) + (CONFIG_LOW_RAM_DMA - LOW_RAM_ALIAS))
+
+unsigned long ptv_memsize;
+
+/*
+ * struct low_mem_reserved - Items in low memmory that are reserved
+ * @start:      Physical address of item
+ * @size:       Size, in bytes, of this item
+ * @is_aliased: True if this is RAM aliased from another location. If false,
+ *              it is something other than aliased RAM and the RAM in the
+ *              unaliased address is still visible outside of low memory.
+ */
+struct low_mem_reserved {
+        phys_addr_t     start;
+        phys_addr_t     size;
+        bool            is_aliased;
+};
+
+/*
+ * Must be in ascending address order
+ */
+struct low_mem_reserved low_mem_reserved[] = {
+        {BLDR_ALIAS, BLDR_SIZE, true},  /* Bootloader RAM */
+        {RV_PHYS, RV_SIZE, false},      /* Reset vector */
+};
+
+/*
+ * struct mem_layout - layout of a piece of the system RAM
+ * @phys:       Physical address of the start of this piece of RAM. This is the
+ *              address at which both the processor and I/O devices see the
+ *              RAM.
+ * @alias:      Alias of this piece of memory in order to make it appear in
+ *              the low memory part of the processor's address space. I/O
+ *              devices don't see anything here.
+ * @size:       Size, in bytes, of this piece of RAM
+ */
+struct mem_layout {
+        phys_addr_t     phys;
+        phys_addr_t     alias;
+        phys_addr_t     size;
+};
+
+/*
+ * struct mem_layout_list - list descriptor for layouts of system RAM pieces
+ * @family:     Specifies the family being described
+ * @n:          Number of &struct mem_layout elements
+ * @layout:     Pointer to the list of &mem_layout structures
+ */
+struct mem_layout_list {
+        enum family_type        family;
+        size_t                  n;
+        struct mem_layout       *layout;
+};
+
+static struct mem_layout f1500_layout[] = {
+        {0x20000000, 0x10000000, MEBIBYTE(256)},
+};
+
+static struct mem_layout f4500_layout[] = {
+        {0x40000000, 0x10000000, MEBIBYTE(256)},
+        {0x20000000, 0x20000000, MEBIBYTE(32)},
+};
+
+static struct mem_layout f8500_layout[] = {
+        {0x40000000, 0x10000000, MEBIBYTE(256)},
+        {0x20000000, 0x20000000, MEBIBYTE(32)},
+        {0x30000000, 0x30000000, MEBIBYTE(32)},
+};
+
+static struct mem_layout fx600_layout[] = {
+        {0x20000000, 0x10000000, MEBIBYTE(256)},
+        {0x60000000, 0x60000000, MEBIBYTE(128)},
+};
+
+static struct mem_layout_list layout_list[] = {
+        {FAMILY_1500, ARRAY_SIZE(f1500_layout), f1500_layout},
+        {FAMILY_1500VZE, ARRAY_SIZE(f1500_layout), f1500_layout},
+        {FAMILY_1500VZF, ARRAY_SIZE(f1500_layout), f1500_layout},
+        {FAMILY_4500, ARRAY_SIZE(f4500_layout), f4500_layout},
+        {FAMILY_8500, ARRAY_SIZE(f8500_layout), f8500_layout},
+        {FAMILY_8500RNG, ARRAY_SIZE(f8500_layout), f8500_layout},
+        {FAMILY_4600, ARRAY_SIZE(fx600_layout), fx600_layout},
+        {FAMILY_4600VZA, ARRAY_SIZE(fx600_layout), fx600_layout},
+        {FAMILY_8600, ARRAY_SIZE(fx600_layout), fx600_layout},
+        {FAMILY_8600VZB, ARRAY_SIZE(fx600_layout), fx600_layout},
+};
+
+/* If we can't determine the layout, use this */
+static struct mem_layout default_layout[] = {
+        {0x20000000, 0x10000000, MEBIBYTE(128)},
+};
+
+/**
+ * register_non_ram - register low memory not available for RAM usage
+ */
+static __init void register_non_ram(void)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(low_mem_reserved); i++)
+                add_memory_region(low_mem_reserved[i].start,
+                        low_mem_reserved[i].size, BOOT_MEM_RESERVED);
+}
+
+/**
+ * get_memsize - get the size of memory as a single bank
+ */
+static phys_addr_t get_memsize(void)
 {
+        static char cmdline[COMMAND_LINE_SIZE] __initdata;
+        phys_addr_t memsize = 0;
         char *memsize_str;
-        unsigned long memsize = 0;
-        unsigned int physend;
         char *ptr;
-        int low_mem;
-        int high_mem;
 
         /* Check the command line first for a memsize directive */
         strcpy(cmdline, arcs_cmdline);
@@ -73,96 +186,156 @@ void __init prom_meminit(void)
                 if (memsize == 0) {
                         if (_prom_memsize != 0) {
                                 memsize = _prom_memsize;
-                                pr_info("_prom_memsize = 0x%lx\n", memsize);
+                                pr_info("_prom_memsize = 0x%x\n", memsize);
                                 /* add in memory that the bootloader doesn't
                                  * report */
-                                memsize += BOOT_MEM_SIZE;
+                                memsize += BLDR_SIZE;
                         } else {
                                 memsize = DEFAULT_MEMSIZE;
                                 pr_info("Memsize not passed by bootloader, "
-                                        "defaulting to 0x%lx\n", memsize);
+                                        "defaulting to 0x%x\n", memsize);
                         }
                 }
         }
 
-        physend = PFN_ALIGN(&_end) - 0x80000000;
-        if (memsize > LOW_MEM_MAX) {
-                low_mem = LOW_MEM_MAX;
-                high_mem = memsize - low_mem;
-        } else {
-                low_mem = memsize;
-                high_mem = 0;
+        return memsize;
+}
+
+/**
+ * register_low_ram - register an aliased section of RAM
+ * @p:          Alias address of memory
+ * @n:          Number of bytes in this section of memory
+ *
+ * Returns the number of bytes registered
+ *
+ */
+static __init phys_addr_t register_low_ram(phys_addr_t p, phys_addr_t n)
+{
+        phys_addr_t s;
+        int i;
+        phys_addr_t orig_n;
+
+        orig_n = n;
+
+        BUG_ON(p + n > RV_PHYS);
+
+        for (i = 0; n != 0 && i < ARRAY_SIZE(low_mem_reserved); i++) {
+                phys_addr_t start;
+                phys_addr_t size;
+
+                start = low_mem_reserved[i].start;
+                size = low_mem_reserved[i].size;
+
+                /* Handle memory before this low memory section */
+                if (p < start) {
+                        phys_addr_t s;
+                        s = min(n, start - p);
+                        add_memory_region(p, s, BOOT_MEM_RAM);
+                        p += s;
+                        n -= s;
+                }
+
+                /* Handle the low memory section itself. If it's aliased,
+                 * we reduce the number of byes left, but if not, the RAM
+                 * is available elsewhere and we don't reduce the number of
+                 * bytes remaining. */
+                if (p == start) {
+                        if (low_mem_reserved[i].is_aliased) {
+                                s = min(n, size);
+                                n -= s;
+                                p += s;
+                        } else
+                                p += n;
+                }
         }
 
+        return orig_n - n;
+}
+
 /*
- * TODO: We will use the hard code for memory configuration until
- * the bootloader releases their device tree to us.
+ * register_ram - register real RAM
+ * @p:  Address of memory as seen by devices
+ * @alias:      If the memory is seen at an additional address by the processor,
+ *              this will be the address, otherwise it is the same as @p.
+ * @n:          Number of bytes in this section of memory
  */
+static __init void register_ram(phys_addr_t p, phys_addr_t alias,
+        phys_addr_t n)
+{
         /*
-         * Add the memory reserved for use by the bootloader to the
-         * memory map.
-         */
-        add_memory_region(PHYS_MEM_START, RES_BOOTLDR_MEMSIZE,
-                BOOT_MEM_RESERVED);
-#ifdef CONFIG_HIGHMEM_256_128
-        /*
-         * Add memory in low for general use by the kernel and its friends
-         * (like drivers, applications, etc).
-         */
-        add_memory_region(PHYS_MEM_START + RES_BOOTLDR_MEMSIZE,
-                LOW_MEM_MAX - RES_BOOTLDR_MEMSIZE, BOOT_MEM_RAM);
-        /*
-         * Add the memory reserved for reset vector.
-         */
-        add_memory_region(0x1fc00000, MEBIBYTE(4), BOOT_MEM_RESERVED);
-        /*
-         * Add the memory reserved.
-         */
-        add_memory_region(0x20000000, MEBIBYTE(1024 + 75), BOOT_MEM_RESERVED);
-        /*
-         * Add memory in high for general use by the kernel and its friends
-         * (like drivers, applications, etc).
-         *
-         * 75MB is reserved for devices which are using the memory in high.
-         */
-        add_memory_region(0x60000000 + MEBIBYTE(75), MEBIBYTE(128 - 75),
-                BOOT_MEM_RAM);
-#elif defined CONFIG_HIGHMEM_128_128
-        /*
-         * Add memory in low for general use by the kernel and its friends
-         * (like drivers, applications, etc).
-         */
-        add_memory_region(PHYS_MEM_START + RES_BOOTLDR_MEMSIZE,
-                MEBIBYTE(128) - RES_BOOTLDR_MEMSIZE, BOOT_MEM_RAM);
-        /*
-         * Add the memory reserved.
-         */
-        add_memory_region(PHYS_MEM_START + MEBIBYTE(128),
-                MEBIBYTE(128 + 1024 + 75), BOOT_MEM_RESERVED);
-        /*
-         * Add memory in high for general use by the kernel and its friends
-         * (like drivers, applications, etc).
-         *
-         * 75MB is reserved for devices which are using the memory in high.
-         */
-        add_memory_region(0x60000000 + MEBIBYTE(75), MEBIBYTE(128 - 75),
-                BOOT_MEM_RAM);
-#else
-        /* Add low memory regions for either:
-         *   - no-highmemory configuration case -OR-
-         *   - highmemory "HIGHMEM_LOWBANK_ONLY" case
-         */
-        /*
-         * Add memory for general use by the kernel and its friends
-         * (like drivers, applications, etc).
+         * If some or all of this memory has an alias, break it into the
+         * aliased and non-aliased portion.
          */
-        add_memory_region(PHYS_MEM_START + RES_BOOTLDR_MEMSIZE,
-                low_mem - RES_BOOTLDR_MEMSIZE, BOOT_MEM_RAM);
+        if (p != alias) {
+                phys_addr_t alias_size;
+                phys_addr_t registered;
+
+                alias_size = min(n, LOW_RAM_END - alias);
+                registered = register_low_ram(alias, alias_size);
+                ioremap_add_map(alias, p, n);
+                n -= registered;
+                p += registered;
+        }
+
+#ifdef CONFIG_HIGHMEM
+        if (n != 0) {
+                add_memory_region(p, n, BOOT_MEM_RAM);
+                ioremap_add_map(p, p, n);
+        }
+#endif
+}
+
+/**
+ * register_address_space - register things in the address space
+ * @memsize:    Number of bytes of RAM installed
+ *
+ * Takes the given number of bytes of RAM and registers as many of the regions,
+ * or partial regions, as it can. So, the default configuration might have
+ * two regions with 256 MiB each. If the memsize passed in on the command line
+ * is 384 MiB, it will register the first region with 256 MiB and the second
+ * with 128 MiB.
+ */
+static __init void register_address_space(phys_addr_t memsize)
+{
+        int i;
+        phys_addr_t size;
+        size_t n;
+        struct mem_layout *layout;
+        enum family_type family;
+
         /*
-         * Add the memory reserved for reset vector.
+         * Register all of the things that aren't available to the kernel as
+         * memory.
          */
-        add_memory_region(0x1fc00000, MEBIBYTE(4), BOOT_MEM_RESERVED);
-#endif
+        register_non_ram();
+
+        /* Find the appropriate memory description */
+        family = platform_get_family();
+
+        for (i = 0; i < ARRAY_SIZE(layout_list); i++) {
+                if (layout_list[i].family == family)
+                        break;
+        }
+
+        if (i == ARRAY_SIZE(layout_list)) {
+                n = ARRAY_SIZE(default_layout);
+                layout = default_layout;
+        } else {
+                n = layout_list[i].n;
+                layout = layout_list[i].layout;
+        }
+
+        for (i = 0; memsize != 0 && i < n; i++) {
+                size = min(memsize, layout[i].size);
+                register_ram(layout[i].phys, layout[i].alias, size);
+                memsize -= size;
+        }
+}
+
+void __init prom_meminit(void)
+{
+        ptv_memsize = get_memsize();
+        register_address_space(ptv_memsize);
 }
 
 void __init prom_free_prom_memory(void)
diff --git a/arch/mips/powertv/powertv-usb.c b/arch/mips/powertv/powertv-usb.c
new file mode 100644
index 000000000000..6ac85cf7aa20
--- /dev/null
+++ b/arch/mips/powertv/powertv-usb.c
@@ -0,0 +1,403 @@
+/*
+ *                              powertv-usb.c
+ *
+ * Description:  ASIC-specific USB device setup and shutdown
+ *
+ * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
+ * Copyright (C) 2009 Cisco Systems, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ * Author:       Ken Eppinett
+ *               David Schleef <ds@schleef.org>
+ *
+ * NOTE: The bootloader allocates persistent memory at an address which is
+ * 16 MiB below the end of the highest address in KSEG0. All fixed
+ * address memory reservations must avoid this region.
+ */
+
+#include <linux/kernel.h>
+#include <linux/ioport.h>
+#include <linux/platform_device.h>
+#include <asm/mach-powertv/asic.h>
+#include <asm/mach-powertv/interrupts.h>
+
+/* misc_clk_ctl1 values */
+#define MCC1_30MHZ_POWERUP_SELECT       (1 << 14)
+#define MCC1_DIV9                       (1 << 13)
+#define MCC1_ETHMIPS_POWERUP_SELECT     (1 << 11)
+#define MCC1_USB_POWERUP_SELECT         (1 << 1)
+#define MCC1_CLOCK108_POWERUP_SELECT    (1 << 0)
+
+/* Possible values for clock select */
+#define MCC1_USB_CLOCK_HIGH_Z           (0 << 4)
+#define MCC1_USB_CLOCK_48MHZ            (1 << 4)
+#define MCC1_USB_CLOCK_24MHZ            (2 << 4)
+#define MCC1_USB_CLOCK_6MHZ             (3 << 4)
+
+#define MCC1_CONFIG     (MCC1_30MHZ_POWERUP_SELECT |            \
+                         MCC1_DIV9 |                            \
+                         MCC1_ETHMIPS_POWERUP_SELECT |          \
+                         MCC1_USB_POWERUP_SELECT |              \
+                         MCC1_CLOCK108_POWERUP_SELECT)
+
+/* misc_clk_ctl2 values */
+#define MCC2_GMII_GCLK_TO_PAD           (1 << 31)
+#define MCC2_ETHER125_0_CLOCK_SELECT    (1 << 29)
+#define MCC2_RMII_0_CLOCK_SELECT        (1 << 28)
+#define MCC2_GMII_TX0_CLOCK_SELECT      (1 << 27)
+#define MCC2_GMII_RX0_CLOCK_SELECT      (1 << 26)
+#define MCC2_ETHER125_1_CLOCK_SELECT    (1 << 24)
+#define MCC2_RMII_1_CLOCK_SELECT        (1 << 23)
+#define MCC2_GMII_TX1_CLOCK_SELECT      (1 << 22)
+#define MCC2_GMII_RX1_CLOCK_SELECT      (1 << 21)
+#define MCC2_ETHER125_2_CLOCK_SELECT    (1 << 19)
+#define MCC2_RMII_2_CLOCK_SELECT        (1 << 18)
+#define MCC2_GMII_TX2_CLOCK_SELECT      (1 << 17)
+#define MCC2_GMII_RX2_CLOCK_SELECT      (1 << 16)
+
+#define ETHER_CLK_CONFIG        (MCC2_GMII_GCLK_TO_PAD |        \
+                                 MCC2_ETHER125_0_CLOCK_SELECT | \
+                                 MCC2_RMII_0_CLOCK_SELECT |     \
+                                 MCC2_GMII_TX0_CLOCK_SELECT |   \
+                                 MCC2_GMII_RX0_CLOCK_SELECT |   \
+                                 MCC2_ETHER125_1_CLOCK_SELECT | \
+                                 MCC2_RMII_1_CLOCK_SELECT |     \
+                                 MCC2_GMII_TX1_CLOCK_SELECT |   \
+                                 MCC2_GMII_RX1_CLOCK_SELECT |   \
+                                 MCC2_ETHER125_2_CLOCK_SELECT | \
+                                 MCC2_RMII_2_CLOCK_SELECT |     \
+                                 MCC2_GMII_TX2_CLOCK_SELECT |   \
+                                 MCC2_GMII_RX2_CLOCK_SELECT)
+
+/* misc_clk_ctl2 definitions for Gaia */
+#define FSX4A_REF_SELECT                (1 << 16)
+#define FSX4B_REF_SELECT                (1 << 17)
+#define FSX4C_REF_SELECT                (1 << 18)
+#define DDR_PLL_REF_SELECT              (1 << 19)
+#define MIPS_PLL_REF_SELECT             (1 << 20)
+
+/* Definitions for the QAM frequency select register FS432X4A4_QAM_CTL */
+#define QAM_FS_SDIV_SHIFT               29
+#define QAM_FS_MD_SHIFT                 24
+#define QAM_FS_MD_MASK                  0x1f    /* Cut down to 5 bits */
+#define QAM_FS_PE_SHIFT                 8
+
+#define QAM_FS_DISABLE_DIVIDE_BY_3              (1 << 5)
+#define QAM_FS_ENABLE_PROGRAM                   (1 << 4)
+#define QAM_FS_ENABLE_OUTPUT                    (1 << 3)
+#define QAM_FS_SELECT_TEST_BYPASS               (1 << 2)
+#define QAM_FS_DISABLE_DIGITAL_STANDBY          (1 << 1)
+#define QAM_FS_CHOOSE_FS                        (1 << 0)
+
+/* Definitions for fs432x4a_ctl register */
+#define QAM_FS_NSDIV_54MHZ                      (1 << 2)
+
+/* Definitions for bcm1_usb2_ctl register */
+#define BCM1_USB2_CTL_BISTOK                            (1 << 11)
+#define BCM1_USB2_CTL_PORT2_SHIFT_JK                    (1 << 7)
+#define BCM1_USB2_CTL_PORT1_SHIFT_JK                    (1 << 6)
+#define BCM1_USB2_CTL_PORT2_FAST_EDGE                   (1 << 5)
+#define BCM1_USB2_CTL_PORT1_FAST_EDGE                   (1 << 4)
+#define BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH          (1 << 1)
+#define BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH     (1 << 0)
+
+/* Definitions for crt_spare register */
+#define CRT_SPARE_PORT2_SHIFT_JK                        (1 << 21)
+#define CRT_SPARE_PORT1_SHIFT_JK                        (1 << 20)
+#define CRT_SPARE_PORT2_FAST_EDGE                       (1 << 19)
+#define CRT_SPARE_PORT1_FAST_EDGE                       (1 << 18)
+#define CRT_SPARE_DIVIDE_BY_9_FROM_432                  (1 << 17)
+#define CRT_SPARE_USB_DIVIDE_BY_9                       (1 << 16)
+
+/* Definitions for usb2_stbus_obc register */
+#define USB_STBUS_OBC_STORE32_LOAD32                    0x3
+
+/* Definitions for usb2_stbus_mess_size register */
+#define USB2_STBUS_MESS_SIZE_2                          0x1     /* 2 packets */
+
+/* Definitions for usb2_stbus_chunk_size register */
+#define USB2_STBUS_CHUNK_SIZE_2                         0x1     /* 2 packets */
+
+/* Definitions for usb2_strap register */
+#define USB2_STRAP_HFREQ_SELECT                         0x1
+
+/*
+ * USB Host Resource Definition
+ */
+
+static struct resource ehci_resources[] = {
+        {
+                .parent = &asic_resource,
+                .start  = 0,
+                .end    = 0xff,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = irq_usbehci,
+                .end    = irq_usbehci,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static u64 ehci_dmamask = 0xffffffffULL;
+
+static struct platform_device ehci_device = {
+        .name = "powertv-ehci",
+        .id = 0,
+        .num_resources = 2,
+        .resource = ehci_resources,
+        .dev = {
+                .dma_mask = &ehci_dmamask,
+                .coherent_dma_mask = 0xffffffff,
+        },
+};
+
+static struct resource ohci_resources[] = {
+        {
+                .parent = &asic_resource,
+                .start  = 0,
+                .end    = 0xff,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = irq_usbohci,
+                .end    = irq_usbohci,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static u64 ohci_dmamask = 0xffffffffULL;
+
+static struct platform_device ohci_device = {
+        .name = "powertv-ohci",
+        .id = 0,
+        .num_resources = 2,
+        .resource = ohci_resources,
+        .dev = {
+                .dma_mask = &ohci_dmamask,
+                .coherent_dma_mask = 0xffffffff,
+        },
+};
+
+static unsigned usb_users;
+static DEFINE_SPINLOCK(usb_regs_lock);
+
+/*
+ *
+ * fs_update - set frequency synthesizer for USB
+ * @pe_bits             Phase tap setting
+ * @md_bits             Coarse selector bus for algorithm of phase tap
+ * @sdiv_bits           Output divider setting
+ * @disable_div_by_3    Either QAM_FS_DISABLE_DIVIDE_BY_3 or zero
+ * @standby             Either QAM_FS_DISABLE_DIGITAL_STANDBY or zero
+ *
+ * QAM frequency selection code, which affects the frequency at which USB
+ * runs. The frequency is calculated as:
+ *                             2^15 * ndiv * Fin
+ * Fout = ------------------------------------------------------------
+ *        (sdiv * (ipe * (1 + md/32) - (ipe - 2^15)*(1 + (md + 1)/32)))
+ * where:
+ * Fin          54 MHz
+ * ndiv         QAM_FS_NSDIV_54MHZ ? 8 : 16
+ * sdiv         1 << (sdiv_bits + 1)
+ * ipe          Same as pe_bits
+ * md           A five-bit, two's-complement integer (range [-16, 15]), which
+ *              is the lower 5 bits of md_bits.
+ */
+static void fs_update(u32 pe_bits, int md_bits, u32 sdiv_bits,
+        u32 disable_div_by_3, u32 standby)
+{
+        u32 val;
+
+        val = ((sdiv_bits << QAM_FS_SDIV_SHIFT) |
+                ((md_bits & QAM_FS_MD_MASK) << QAM_FS_MD_SHIFT) |
+                (pe_bits << QAM_FS_PE_SHIFT) |
+                QAM_FS_ENABLE_OUTPUT |
+                standby |
+                disable_div_by_3);
+        asic_write(val, fs432x4b4_usb_ctl);
+        asic_write(val | QAM_FS_ENABLE_PROGRAM, fs432x4b4_usb_ctl);
+        asic_write(val | QAM_FS_ENABLE_PROGRAM | QAM_FS_CHOOSE_FS,
+                fs432x4b4_usb_ctl);
+}
+
+/*
+ * usb_eye_configure - for optimizing the shape USB eye waveform
+ * @set:        Bits to set in the register
+ * @clear:      Bits to clear in the register; each bit with a one will
+ *              be set in the register, zero bits will not be modified
+ */
+static void usb_eye_configure(u32 set, u32 clear)
+{
+        u32 old;
+
+        old = asic_read(crt_spare);
+        old |= set;
+        old &= ~clear;
+        asic_write(old, crt_spare);
+}
+
+/*
+ * platform_configure_usb - usb configuration based on platform type.
+ */
+static void platform_configure_usb(void)
+{
+        u32 bcm1_usb2_ctl_value;
+        enum asic_type asic_type;
+        unsigned long flags;
+
+        spin_lock_irqsave(&usb_regs_lock, flags);
+        usb_users++;
+
+        if (usb_users != 1) {
+                spin_unlock_irqrestore(&usb_regs_lock, flags);
+                return;
+        }
+
+        asic_type = platform_get_asic();
+
+        switch (asic_type) {
+        case ASIC_ZEUS:
+                fs_update(0x0000, -15, 0x02, 0, 0);
+                bcm1_usb2_ctl_value = BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH |
+                        BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH;
+                break;
+
+        case ASIC_CRONUS:
+        case ASIC_CRONUSLITE:
+                usb_eye_configure(0, CRT_SPARE_USB_DIVIDE_BY_9);
+                fs_update(0x8000, -14, 0x03, QAM_FS_DISABLE_DIVIDE_BY_3,
+                        QAM_FS_DISABLE_DIGITAL_STANDBY);
+                bcm1_usb2_ctl_value = BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH |
+                        BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH;
+                break;
+
+        case ASIC_CALLIOPE:
+                fs_update(0x0000, -15, 0x02, QAM_FS_DISABLE_DIVIDE_BY_3,
+                        QAM_FS_DISABLE_DIGITAL_STANDBY);
+
+                switch (platform_get_family()) {
+                case FAMILY_1500VZE:
+                        break;
+
+                case FAMILY_1500VZF:
+                        usb_eye_configure(CRT_SPARE_PORT2_SHIFT_JK |
+                                CRT_SPARE_PORT1_SHIFT_JK |
+                                CRT_SPARE_PORT2_FAST_EDGE |
+                                CRT_SPARE_PORT1_FAST_EDGE, 0);
+                        break;
+
+                default:
+                        usb_eye_configure(CRT_SPARE_PORT2_SHIFT_JK |
+                                CRT_SPARE_PORT1_SHIFT_JK, 0);
+                        break;
+                }
+
+                bcm1_usb2_ctl_value = BCM1_USB2_CTL_BISTOK |
+                        BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH |
+                        BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH;
+                break;
+
+        case ASIC_GAIA:
+                fs_update(0x8000, -14, 0x03, QAM_FS_DISABLE_DIVIDE_BY_3,
+                        QAM_FS_DISABLE_DIGITAL_STANDBY);
+                bcm1_usb2_ctl_value = BCM1_USB2_CTL_BISTOK |
+                        BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH |
+                        BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH;
+                break;
+
+        default:
+                pr_err("Unknown ASIC type: %d\n", asic_type);
+                bcm1_usb2_ctl_value = 0;
+                break;
+        }
+
+        /* turn on USB power */
+        asic_write(0, usb2_strap);
+        /* Enable all OHCI interrupts */
+        asic_write(bcm1_usb2_ctl_value, usb2_control);
+        /* usb2_stbus_obc store32/load32 */
+        asic_write(USB_STBUS_OBC_STORE32_LOAD32, usb2_stbus_obc);
+        /* usb2_stbus_mess_size 2 packets */
+        asic_write(USB2_STBUS_MESS_SIZE_2, usb2_stbus_mess_size);
+        /* usb2_stbus_chunk_size 2 packets */
+        asic_write(USB2_STBUS_CHUNK_SIZE_2, usb2_stbus_chunk_size);
+        spin_unlock_irqrestore(&usb_regs_lock, flags);
+}
+
+static void platform_unconfigure_usb(void)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&usb_regs_lock, flags);
+        usb_users--;
+        if (usb_users == 0)
+                asic_write(USB2_STRAP_HFREQ_SELECT, usb2_strap);
+        spin_unlock_irqrestore(&usb_regs_lock, flags);
+}
+
+/*
+ * Set up the USB EHCI interface
+ */
+void platform_configure_usb_ehci()
+{
+        platform_configure_usb();
+}
+EXPORT_SYMBOL(platform_configure_usb_ehci);
+
+/*
+ * Set up the USB OHCI interface
+ */
+void platform_configure_usb_ohci()
+{
+        platform_configure_usb();
+}
+EXPORT_SYMBOL(platform_configure_usb_ohci);
+
+/*
+ * Shut the USB EHCI interface down
+ */
+void platform_unconfigure_usb_ehci()
+{
+        platform_unconfigure_usb();
+}
+EXPORT_SYMBOL(platform_unconfigure_usb_ehci);
+
+/*
+ * Shut the USB OHCI interface down
+ */
+void platform_unconfigure_usb_ohci()
+{
+        platform_unconfigure_usb();
+}
+EXPORT_SYMBOL(platform_unconfigure_usb_ohci);
+
+/**
+ * platform_devices_init - sets up USB device resourse.
+ */
+int __init platform_usb_devices_init(struct platform_device **ehci_dev,
+        struct platform_device **ohci_dev)
+{
+        *ehci_dev = &ehci_device;
+        ehci_resources[0].start = asic_reg_phys_addr(ehci_hcapbase);
+        ehci_resources[0].end += ehci_resources[0].start;
+
+        *ohci_dev = &ohci_device;
+        ohci_resources[0].start = asic_reg_phys_addr(ohci_hc_revision);
+        ohci_resources[0].end += ohci_resources[0].start;
+
+        return 0;
+}
diff --git a/arch/mips/powertv/powertv_setup.c b/arch/mips/powertv/powertv_setup.c
index af2cae0a5ab3..3933c373a438 100644
--- a/arch/mips/powertv/powertv_setup.c
+++ b/arch/mips/powertv/powertv_setup.c
@@ -199,14 +199,8 @@ static int panic_handler(struct notifier_block *notifier_block,
                 my_regs.cp0_status = read_c0_status();
         }
 
-#ifdef CONFIG_DIAGNOSTICS
-        failure_report((char *) cause_string,
-                have_die_regs ? &die_regs : &my_regs);
-        have_die_regs = false;
-#else
         pr_crit("I'm feeling a bit sleepy. hmmmmm... perhaps a nap would... "
                 "zzzz... \n");
-#endif
 
         return NOTIFY_DONE;
 }
diff --git a/arch/mips/rb532/Makefile b/arch/mips/rb532/Makefile
index 8f0b6b6a1625..efdecdb6e3ea 100644
--- a/arch/mips/rb532/Makefile
+++ b/arch/mips/rb532/Makefile
@@ -3,5 +3,3 @@
 #
 
 obj-y    += irq.o time.o setup.o serial.o prom.o gpio.o devices.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/rb532/Platform b/arch/mips/rb532/Platform
new file mode 100644
index 000000000000..aeec45a7cbb3
--- /dev/null
+++ b/arch/mips/rb532/Platform
@@ -0,0 +1,7 @@
+#
+# Routerboard 532
+#
+platform-$(CONFIG_MIKROTIK_RB532)       += rb532/
+cflags-$(CONFIG_MIKROTIK_RB532)         +=                              \
+                -I$(srctree)/arch/mips/include/asm/mach-rc32434
+load-$(CONFIG_MIKROTIK_RB532)           += 0xffffffff80101000
diff --git a/arch/mips/sgi-ip22/Makefile b/arch/mips/sgi-ip22/Makefile
index 416b18f9fa72..cc538493cae1 100644
--- a/arch/mips/sgi-ip22/Makefile
+++ b/arch/mips/sgi-ip22/Makefile
@@ -9,5 +9,3 @@ obj-y	+= ip22-mc.o ip22-hpc.o ip22-int.o ip22-time.o ip22-nvram.o \
 obj-$(CONFIG_SGI_IP22) += ip22-berr.o
 obj-$(CONFIG_SGI_IP28) += ip28-berr.o
 obj-$(CONFIG_EISA)      += ip22-eisa.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/sgi-ip22/Platform b/arch/mips/sgi-ip22/Platform
new file mode 100644
index 000000000000..b7a4b7e04c38
--- /dev/null
+++ b/arch/mips/sgi-ip22/Platform
@@ -0,0 +1,34 @@
+#
+# SGI IP22 (Indy/Indigo2)
+#
+# Set the load address to >= 0xffffffff88069000 if you want to leave space for
+# symmon, 0xffffffff80002000 for production kernels.  Note that the value must
+# be aligned to a multiple of the kernel stack size or the handling of the
+# current variable will break so for 64-bit kernels we have to raise the start
+# address by 8kb.
+#
+platform-$(CONFIG_SGI_IP22)             += sgi-ip22/
+cflags-$(CONFIG_SGI_IP22)       += -I$(srctree)/arch/mips/include/asm/mach-ip22
+ifdef CONFIG_32BIT
+load-$(CONFIG_SGI_IP22)         += 0xffffffff88002000
+endif
+ifdef CONFIG_64BIT
+load-$(CONFIG_SGI_IP22)         += 0xffffffff88004000
+endif
+
+#
+# SGI IP28 (Indigo2 R10k)
+#
+# Set the load address to >= 0xa800000020080000 if you want to leave space for
+# symmon, 0xa800000020004000 for production kernels ?  Note that the value must
+# be 16kb aligned or the handling of the current variable will break.
+# Simplified: what IP22 does at 128MB+ in ksegN, IP28 does at 512MB+ in xkphys
+#
+ifdef CONFIG_SGI_IP28
+  ifeq ($(call cc-option-yn,-mr10k-cache-barrier=store), n)
+      $(error gcc doesn't support needed option -mr10k-cache-barrier=store)
+  endif
+endif
+platform-$(CONFIG_SGI_IP28)             += sgi-ip22/
+cflags-$(CONFIG_SGI_IP28)       += -mr10k-cache-barrier=store -I$(srctree)/arch/mips/include/asm/mach-ip28
+load-$(CONFIG_SGI_IP28)         += 0xa800000020004000
diff --git a/arch/mips/sgi-ip27/Makefile b/arch/mips/sgi-ip27/Makefile
index 31f4931b8484..1f29e761d691 100644
--- a/arch/mips/sgi-ip27/Makefile
+++ b/arch/mips/sgi-ip27/Makefile
@@ -8,5 +8,3 @@ obj-y	:= ip27-berr.o ip27-irq.o ip27-init.o ip27-klconfig.o ip27-klnuma.o \
 
 obj-$(CONFIG_EARLY_PRINTK)      += ip27-console.o
 obj-$(CONFIG_SMP)               += ip27-smp.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/sgi-ip27/Platform b/arch/mips/sgi-ip27/Platform
new file mode 100644
index 000000000000..1fb9c2ea7c8f
--- /dev/null
+++ b/arch/mips/sgi-ip27/Platform
@@ -0,0 +1,19 @@
+#
+# SGI-IP27 (Origin200/2000)
+#
+# Set the load address to >= 0xc000000000300000 if you want to leave space for
+# symmon, 0xc00000000001c000 for production kernels.  Note that the value must
+# be 16kb aligned or the handling of the current variable will break.
+#
+ifdef CONFIG_SGI_IP27
+platform-$(CONFIG_SGI_IP27)     += sgi-ip27/
+cflags-$(CONFIG_SGI_IP27)       += -I$(srctree)/arch/mips/include/asm/mach-ip27
+ifdef CONFIG_MAPPED_KERNEL
+load-$(CONFIG_SGI_IP27)         += 0xc00000004001c000
+OBJCOPYFLAGS                    := --change-addresses=0x3fffffff80000000
+dataoffset-$(CONFIG_SGI_IP27)   += 0x01000000
+else
+load-$(CONFIG_SGI_IP27)         += 0xa80000000001c000
+OBJCOPYFLAGS                    := --change-addresses=0x57ffffff80000000
+endif
+endif
diff --git a/arch/mips/sgi-ip27/ip27-klconfig.c b/arch/mips/sgi-ip27/ip27-klconfig.c
index dd830b3670d1..7afe14688003 100644
--- a/arch/mips/sgi-ip27/ip27-klconfig.c
+++ b/arch/mips/sgi-ip27/ip27-klconfig.c
@@ -48,7 +48,7 @@ klinfo_t *find_first_component(lboard_t *brd, unsigned char struct_type)
         return find_component(brd, (klinfo_t *)NULL, struct_type);
 }
 
-lboard_t * find_lboard(lboard_t *start, unsigned char brd_type)
+lboard_t *find_lboard(lboard_t *start, unsigned char brd_type)
 {
         /* Search all boards stored on this node. */
         while (start) {
@@ -60,7 +60,7 @@ lboard_t * find_lboard(lboard_t *start, unsigned char brd_type)
         return (lboard_t *)NULL;
 }
 
-lboard_t * find_lboard_class(lboard_t *start, unsigned char brd_type)
+lboard_t *find_lboard_class(lboard_t *start, unsigned char brd_type)
 {
         /* Search all boards stored on this node. */
         while (start) {
@@ -78,7 +78,7 @@ cnodeid_t get_cpu_cnode(cpuid_t cpu)
         return CPUID_TO_COMPACT_NODEID(cpu);
 }
 
-klcpu_t * nasid_slice_to_cpuinfo(nasid_t nasid, int slice)
+klcpu_t *nasid_slice_to_cpuinfo(nasid_t nasid, int slice)
 {
         lboard_t *brd;
         klcpu_t *acpu;
@@ -97,7 +97,7 @@ klcpu_t * nasid_slice_to_cpuinfo(nasid_t nasid, int slice)
         return (klcpu_t *)NULL;
 }
 
-klcpu_t * sn_get_cpuinfo(cpuid_t cpu)
+klcpu_t *sn_get_cpuinfo(cpuid_t cpu)
 {
         nasid_t nasid;
         int slice;
diff --git a/arch/mips/sgi-ip32/Makefile b/arch/mips/sgi-ip32/Makefile
index 31c9aa1bcb40..60f0227425e7 100644
--- a/arch/mips/sgi-ip32/Makefile
+++ b/arch/mips/sgi-ip32/Makefile
@@ -5,5 +5,3 @@
 
 obj-y   += ip32-berr.o ip32-irq.o ip32-platform.o ip32-setup.o ip32-reset.o \
            crime.o ip32-memory.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/sgi-ip32/Platform b/arch/mips/sgi-ip32/Platform
new file mode 100644
index 000000000000..0fea556f3641
--- /dev/null
+++ b/arch/mips/sgi-ip32/Platform
@@ -0,0 +1,11 @@
+#
+# SGI-IP32 (O2)
+#
+# Set the load address to >= 80069000 if you want to leave space for symmon,
+# 0xffffffff80004000 for production kernels.  Note that the value must be aligned to
+# a multiple of the kernel stack size or the handling of the current variable
+# will break.
+#
+platform-$(CONFIG_SGI_IP32)     += sgi-ip32/
+cflags-$(CONFIG_SGI_IP32)       += -I$(srctree)/arch/mips/include/asm/mach-ip32
+load-$(CONFIG_SGI_IP32)         += 0xffffffff80004000
diff --git a/arch/mips/sibyte/Makefile b/arch/mips/sibyte/Makefile
new file mode 100644
index 000000000000..c8ed2c807e69
--- /dev/null
+++ b/arch/mips/sibyte/Makefile
@@ -0,0 +1,27 @@
+#
+# Sibyte SB1250 / BCM1480 family of SOCs
+#
+obj-$(CONFIG_SIBYTE_BCM112X)    += sb1250/
+obj-$(CONFIG_SIBYTE_BCM112X)    += common/
+obj-$(CONFIG_SIBYTE_SB1250)     += sb1250/
+obj-$(CONFIG_SIBYTE_SB1250)     += common/
+obj-$(CONFIG_SIBYTE_BCM1x55)    += bcm1480/
+obj-$(CONFIG_SIBYTE_BCM1x55)    += common/
+obj-$(CONFIG_SIBYTE_BCM1x80)    += bcm1480/
+obj-$(CONFIG_SIBYTE_BCM1x80)    += common/
+
+#
+# Sibyte BCM91120x (Carmel) board
+# Sibyte BCM91120C (CRhine) board
+# Sibyte BCM91125C (CRhone) board
+# Sibyte BCM91125E (Rhone) board
+# Sibyte SWARM board
+# Sibyte BCM91x80 (BigSur) board
+#
+obj-$(CONFIG_SIBYTE_CARMEL)     += swarm/
+obj-$(CONFIG_SIBYTE_CRHINE)     += swarm/
+obj-$(CONFIG_SIBYTE_CRHONE)     += swarm/
+obj-$(CONFIG_SIBYTE_RHONE)      += swarm/
+obj-$(CONFIG_SIBYTE_SENTOSA)    += swarm/
+obj-$(CONFIG_SIBYTE_SWARM)      += swarm/
+obj-$(CONFIG_SIBYTE_BIGSUR)     += swarm/
diff --git a/arch/mips/sibyte/Platform b/arch/mips/sibyte/Platform
new file mode 100644
index 000000000000..911dfe39c631
--- /dev/null
+++ b/arch/mips/sibyte/Platform
@@ -0,0 +1,43 @@
+#
+# These are all rather similar so we consider them a single platform
+#
+platform-$(CONFIG_SIBYTE_BCM112X)       += sibyte/
+platform-$(CONFIG_SIBYTE_SB1250)        += sibyte/
+platform-$(CONFIG_SIBYTE_BCM1x55)       += sibyte/
+platform-$(CONFIG_SIBYTE_BCM1x80)       += sibyte/
+
+#
+# Sibyte SB1250 / BCM1480 family of SOCs
+#
+cflags-$(CONFIG_SIBYTE_BCM112X) +=                                      \
+                -I$(srctree)/arch/mips/include/asm/mach-sibyte          \
+                -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1250_112x_ALL
+
+platform-$(CONFIG_SIBYTE_SB1250)        += sibyte/
+cflags-$(CONFIG_SIBYTE_SB1250)  +=                                      \
+                -I$(srctree)/arch/mips/include/asm/mach-sibyte          \
+                -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1250_112x_ALL
+
+cflags-$(CONFIG_SIBYTE_BCM1x55) +=                                      \
+                -I$(srctree)/arch/mips/include/asm/mach-sibyte          \
+                -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1480_ALL
+
+cflags-$(CONFIG_SIBYTE_BCM1x80) +=                                      \
+                -I$(srctree)/arch/mips/include/asm/mach-sibyte          \
+                -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1480_ALL
+
+#
+# Sibyte BCM91120x (Carmel) board
+# Sibyte BCM91120C (CRhine) board
+# Sibyte BCM91125C (CRhone) board
+# Sibyte BCM91125E (Rhone) board
+# Sibyte SWARM board
+# Sibyte BCM91x80 (BigSur) board
+#
+load-$(CONFIG_SIBYTE_CARMEL)    := 0xffffffff80100000
+load-$(CONFIG_SIBYTE_CRHINE)    := 0xffffffff80100000
+load-$(CONFIG_SIBYTE_CRHONE)    := 0xffffffff80100000
+load-$(CONFIG_SIBYTE_RHONE)     := 0xffffffff80100000
+load-$(CONFIG_SIBYTE_SENTOSA)   := 0xffffffff80100000
+load-$(CONFIG_SIBYTE_SWARM)     := 0xffffffff80100000
+load-$(CONFIG_SIBYTE_BIGSUR)    := 0xffffffff80100000
diff --git a/arch/mips/sibyte/bcm1480/Makefile b/arch/mips/sibyte/bcm1480/Makefile
index f292f7df0cfb..cdc4c56c3e29 100644
--- a/arch/mips/sibyte/bcm1480/Makefile
+++ b/arch/mips/sibyte/bcm1480/Makefile
@@ -1,5 +1,3 @@
 obj-y := setup.o irq.o time.o
 
 obj-$(CONFIG_SMP)                       += smp.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/sibyte/common/Makefile b/arch/mips/sibyte/common/Makefile
index 4f659837c7c6..36aa700cc40c 100644
--- a/arch/mips/sibyte/common/Makefile
+++ b/arch/mips/sibyte/common/Makefile
@@ -1,5 +1,3 @@
 obj-y := cfe.o
 obj-$(CONFIG_SIBYTE_CFE_CONSOLE)        += cfe_console.o
 obj-$(CONFIG_SIBYTE_TBPROF)             += sb_tbprof.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/sibyte/sb1250/Makefile b/arch/mips/sibyte/sb1250/Makefile
index 1896f4e77a30..d3d969de407b 100644
--- a/arch/mips/sibyte/sb1250/Makefile
+++ b/arch/mips/sibyte/sb1250/Makefile
@@ -2,5 +2,3 @@ obj-y := setup.o irq.o time.o
 
 obj-$(CONFIG_SMP)                       += smp.o
 obj-$(CONFIG_SIBYTE_BUS_WATCHER)        += bus_watcher.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/sni/Makefile b/arch/mips/sni/Makefile
index a7dbeebe7fe6..9d3bad3200ce 100644
--- a/arch/mips/sni/Makefile
+++ b/arch/mips/sni/Makefile
@@ -4,5 +4,3 @@
 
 obj-y += irq.o reset.o setup.o a20r.o rm200.o pcimt.o pcit.o time.o
 obj-$(CONFIG_EISA) += eisa.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/sni/Platform b/arch/mips/sni/Platform
new file mode 100644
index 000000000000..2644a9d63c0f
--- /dev/null
+++ b/arch/mips/sni/Platform
@@ -0,0 +1,11 @@
+#
+# SNI RM
+#
+platform-$(CONFIG_SNI_RM)               += sni/
+cflags-$(CONFIG_SNI_RM)         += -I$(srctree)/arch/mips/include/asm/mach-rm
+ifdef CONFIG_CPU_LITTLE_ENDIAN
+load-$(CONFIG_SNI_RM)           += 0xffffffff80600000
+else
+load-$(CONFIG_SNI_RM)           += 0xffffffff80030000
+endif
+all-$(CONFIG_SNI_RM)            := $(COMPRESSION_FNAME).ecoff
diff --git a/arch/mips/txx9/Makefile b/arch/mips/txx9/Makefile
new file mode 100644
index 000000000000..34787dabff06
--- /dev/null
+++ b/arch/mips/txx9/Makefile
@@ -0,0 +1,17 @@
+#
+# Common TXx9
+#
+obj-$(CONFIG_MACH_TX39XX)      += generic/
+obj-$(CONFIG_MACH_TX49XX)      += generic/
+
+#
+# Toshiba JMR-TX3927 board
+#
+obj-$(CONFIG_TOSHIBA_JMR3927)  += jmr3927/
+
+#
+# Toshiba RBTX49XX boards
+#
+obj-$(CONFIG_TOSHIBA_RBTX4927) += rbtx4927/
+obj-$(CONFIG_TOSHIBA_RBTX4938) += rbtx4938/
+obj-$(CONFIG_TOSHIBA_RBTX4939) += rbtx4939/
diff --git a/arch/mips/txx9/Platform b/arch/mips/txx9/Platform
new file mode 100644
index 000000000000..a801abbe138b
--- /dev/null
+++ b/arch/mips/txx9/Platform
@@ -0,0 +1,10 @@
+platform-$(CONFIG_MACH_TX39XX)  += txx9/
+platform-$(CONFIG_MACH_TX49XX)  += txx9/
+
+cflags-$(CONFIG_MACH_TX39XX)    +=                                      \
+                -I$(srctree)/arch/mips/include/asm/mach-tx39xx
+cflags-$(CONFIG_MACH_TX49XX)    +=                                      \
+                 -I$(srctree)/arch/mips/include/asm/mach-tx49xx
+
+load-$(CONFIG_MACH_TX39XX)      += 0xffffffff80050000
+load-$(CONFIG_MACH_TX49XX)      += 0xffffffff80100000
diff --git a/arch/mips/txx9/generic/Makefile b/arch/mips/txx9/generic/Makefile
index f2579ce054a1..1863c167e66e 100644
--- a/arch/mips/txx9/generic/Makefile
+++ b/arch/mips/txx9/generic/Makefile
@@ -11,5 +11,3 @@ obj-$(CONFIG_SOC_TX4939)	+= setup_tx4939.o irq_tx4939.o
 obj-$(CONFIG_TOSHIBA_FPCIB0)    += smsc_fdc37m81x.o
 obj-$(CONFIG_SPI)               += spi_eeprom.o
 obj-$(CONFIG_TXX9_7SEGLED)      += 7segled.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/txx9/jmr3927/Makefile b/arch/mips/txx9/jmr3927/Makefile
index 20d61ac543e5..9f5d5b623839 100644
--- a/arch/mips/txx9/jmr3927/Makefile
+++ b/arch/mips/txx9/jmr3927/Makefile
@@ -3,5 +3,3 @@
 #
 
 obj-y   += prom.o irq.o setup.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/txx9/rbtx4927/Makefile b/arch/mips/txx9/rbtx4927/Makefile
index f3e1f597b4f1..60b24c8f7e63 100644
--- a/arch/mips/txx9/rbtx4927/Makefile
+++ b/arch/mips/txx9/rbtx4927/Makefile
@@ -1,3 +1 @@
 obj-y   += prom.o setup.o irq.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/txx9/rbtx4938/Makefile b/arch/mips/txx9/rbtx4938/Makefile
index f3e1f597b4f1..60b24c8f7e63 100644
--- a/arch/mips/txx9/rbtx4938/Makefile
+++ b/arch/mips/txx9/rbtx4938/Makefile
@@ -1,3 +1 @@
 obj-y   += prom.o setup.o irq.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/txx9/rbtx4939/Makefile b/arch/mips/txx9/rbtx4939/Makefile
index 3232cd03a7d6..5c84625a3f1c 100644
--- a/arch/mips/txx9/rbtx4939/Makefile
+++ b/arch/mips/txx9/rbtx4939/Makefile
@@ -1,3 +1 @@
 obj-y    += irq.o setup.o prom.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/vr41xx/Platform b/arch/mips/vr41xx/Platform
new file mode 100644
index 000000000000..b6c8d5c08ddb
--- /dev/null
+++ b/arch/mips/vr41xx/Platform
@@ -0,0 +1,32 @@
+#
+# NEC VR4100 series based machines
+#
+platform-$(CONFIG_MACH_VR41XX)  += vr41xx/common/
+cflags-$(CONFIG_MACH_VR41XX)    += -I$(srctree)/arch/mips/include/asm/mach-vr41xx
+
+#
+# CASIO CASSIPEIA E-55/65 (VR4111)
+#
+platform-$(CONFIG_CASIO_E55)    += vr41xx/casio-e55/
+load-$(CONFIG_CASIO_E55)        += 0xffffffff80004000
+
+#
+# IBM WorkPad z50 (VR4121)
+#
+platform-$(CONFIG_IBM_WORKPAD)  += vr41xx/ibm-workpad/
+load-$(CONFIG_IBM_WORKPAD)      += 0xffffffff80004000
+
+#
+# TANBAC VR4131 multichip module(TB0225) and TANBAC VR4131DIMM(TB0229) (VR4131)
+#
+load-$(CONFIG_TANBAC_TB022X)    += 0xffffffff80000000
+
+#
+# Victor MP-C303/304 (VR4122)
+#
+load-$(CONFIG_VICTOR_MPC30X)    += 0xffffffff80001000
+
+#
+# ZAO Networks Capcella (VR4131)
+#
+load-$(CONFIG_ZAO_CAPCELLA)     += 0xffffffff80000000
diff --git a/arch/mips/vr41xx/common/Makefile b/arch/mips/vr41xx/common/Makefile
index 7d5d83b8c582..d0d84ec8d63d 100644
--- a/arch/mips/vr41xx/common/Makefile
+++ b/arch/mips/vr41xx/common/Makefile
@@ -3,5 +3,3 @@
 #
 
 obj-y   += bcu.o cmu.o giu.o icu.o init.o irq.o pmu.o rtc.o siu.o type.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/gt64120/wrppmc/Makefile b/arch/mips/wrppmc/Makefile
index b49d282bee8a..307cc6920ce6 100644
--- a/arch/mips/gt64120/wrppmc/Makefile
+++ b/arch/mips/wrppmc/Makefile
@@ -6,9 +6,7 @@
 # Copyright 2006 Wind River System, Inc.
 # Author: Rongkai.Zhan <rongkai.zhan@windriver.com>
 #
-# Makefile for the Wind River MIPS 4KC PPMC Eval Board
+# Makefile for the Wind River MIPS 4Kc PPMC Eval Board
 #
 
 obj-y += irq.o pci.o reset.o serial.o setup.o time.o
-
-EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/wrppmc/Platform b/arch/mips/wrppmc/Platform
new file mode 100644
index 000000000000..e758645e9681
--- /dev/null
+++ b/arch/mips/wrppmc/Platform
@@ -0,0 +1,7 @@
+#
+# Wind River PPMC Board (4KC + GT64120)
+#
+platform-$(CONFIG_WR_PPMC)      += wrppmc/
+cflags-$(CONFIG_WR_PPMC)        +=                                      \
+                -I$(srctree)/arch/mips/include/asm/mach-wrppmc
+load-$(CONFIG_WR_PPMC)          += 0xffffffff80100000
diff --git a/arch/mips/gt64120/wrppmc/irq.c b/arch/mips/wrppmc/irq.c
index c6e706274db4..c6e706274db4 100644
--- a/arch/mips/gt64120/wrppmc/irq.c
+++ b/arch/mips/wrppmc/irq.c
diff --git a/arch/mips/gt64120/wrppmc/pci.c b/arch/mips/wrppmc/pci.c
index d06192faeb7c..d06192faeb7c 100644
--- a/arch/mips/gt64120/wrppmc/pci.c
+++ b/arch/mips/wrppmc/pci.c
diff --git a/arch/mips/gt64120/wrppmc/reset.c b/arch/mips/wrppmc/reset.c
index cc5474b24f06..cc5474b24f06 100644
--- a/arch/mips/gt64120/wrppmc/reset.c
+++ b/arch/mips/wrppmc/reset.c
diff --git a/arch/mips/gt64120/wrppmc/serial.c b/arch/mips/wrppmc/serial.c
index 6f9d0858f596..6f9d0858f596 100644
--- a/arch/mips/gt64120/wrppmc/serial.c
+++ b/arch/mips/wrppmc/serial.c
diff --git a/arch/mips/gt64120/wrppmc/setup.c b/arch/mips/wrppmc/setup.c
index ca65c84031a7..ca65c84031a7 100644
--- a/arch/mips/gt64120/wrppmc/setup.c
+++ b/arch/mips/wrppmc/setup.c
diff --git a/arch/mips/gt64120/wrppmc/time.c b/arch/mips/wrppmc/time.c
index 668dbd5f12c5..668dbd5f12c5 100644
--- a/arch/mips/gt64120/wrppmc/time.c
+++ b/arch/mips/wrppmc/time.c
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 2031a2846865..e4545f85ee9f 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -141,6 +141,7 @@ config PPC
         select GENERIC_ATOMIC64 if PPC32
         select HAVE_PERF_EVENTS
         select HAVE_REGS_AND_STACK_ACCESS_API
+        select HAVE_HW_BREAKPOINT if PERF_EVENTS && PPC_BOOK3S_64
 
 config EARLY_PRINTK
         bool
@@ -218,7 +219,7 @@ config ARCH_HIBERNATION_POSSIBLE
 config ARCH_SUSPEND_POSSIBLE
         def_bool y
         depends on ADB_PMU || PPC_EFIKA || PPC_LITE5200 || PPC_83xx || \
-                   PPC_85xx || PPC_86xx
+                   PPC_85xx || PPC_86xx || PPC_PSERIES
 
 config PPC_DCR_NATIVE
         bool
@@ -351,7 +352,7 @@ config ARCH_ENABLE_MEMORY_HOTREMOVE
 
 config KEXEC
         bool "kexec system call (EXPERIMENTAL)"
-        depends on (PPC_BOOK3S || (FSL_BOOKE && !SMP)) && EXPERIMENTAL
+        depends on (PPC_BOOK3S || FSL_BOOKE) && EXPERIMENTAL
         help
           kexec is a system call that implements the ability to shutdown your
           current kernel, and to start another kernel.  It is like a reboot
@@ -368,8 +369,8 @@ config KEXEC
 
 config CRASH_DUMP
         bool "Build a kdump crash kernel"
-        depends on PPC64 || 6xx
-        select RELOCATABLE if PPC64
+        depends on PPC64 || 6xx || FSL_BOOKE
+        select RELOCATABLE if PPC64 || FSL_BOOKE
         help
           Build a kernel suitable for use as a kdump capture kernel.
           The same kernel binary can be used as production kernel and dump
@@ -668,7 +669,7 @@ config NEED_SG_DMA_LENGTH
 
 config GENERIC_ISA_DMA
         bool
-        depends on PPC64 || POWER4 || 6xx && !CPM2
+        depends on ISA_DMA_API
         default y
 
 config PPC_INDIRECT_PCI
@@ -897,7 +898,7 @@ config KERNEL_START_BOOL
 config KERNEL_START
         hex "Virtual address of kernel base" if KERNEL_START_BOOL
         default PAGE_OFFSET if PAGE_OFFSET_BOOL
-        default "0xc2000000" if CRASH_DUMP
+        default "0xc2000000" if CRASH_DUMP && !RELOCATABLE
         default "0xc0000000"
 
 config PHYSICAL_START_BOOL
@@ -910,7 +911,7 @@ config PHYSICAL_START_BOOL
 
 config PHYSICAL_START
         hex "Physical address where the kernel is loaded" if PHYSICAL_START_BOOL
-        default "0x02000000" if PPC_STD_MMU && CRASH_DUMP
+        default "0x02000000" if PPC_STD_MMU && CRASH_DUMP && !RELOCATABLE
         default "0x00000000"
 
 config PHYSICAL_ALIGN
diff --git a/arch/powerpc/boot/dts/canyonlands.dts b/arch/powerpc/boot/dts/canyonlands.dts
index cd56bb5b347b..5806ef0b860b 100644
--- a/arch/powerpc/boot/dts/canyonlands.dts
+++ b/arch/powerpc/boot/dts/canyonlands.dts
@@ -270,7 +270,7 @@
                                 clock-frequency = <0>; /* Filled in by U-Boot */
                                 current-speed = <0>; /* Filled in by U-Boot */
                                 interrupt-parent = <&UIC1>;
-                                interrupts = <0x1d 0x4>;
+                                interrupts = <28 0x4>;
                         };
 
                         UART3: serial@ef600600 {
@@ -281,7 +281,7 @@
                                 clock-frequency = <0>; /* Filled in by U-Boot */
                                 current-speed = <0>; /* Filled in by U-Boot */
                                 interrupt-parent = <&UIC1>;
-                                interrupts = <0x1e 0x4>;
+                                interrupts = <29 0x4>;
                         };
 
                         IIC0: i2c@ef600700 {
diff --git a/arch/powerpc/boot/dts/glacier.dts b/arch/powerpc/boot/dts/glacier.dts
index d62a4fb6f93c..e618fc4cbc9e 100644
--- a/arch/powerpc/boot/dts/glacier.dts
+++ b/arch/powerpc/boot/dts/glacier.dts
@@ -259,7 +259,7 @@
                                 clock-frequency = <0>; /* Filled in by U-Boot */
                                 current-speed = <0>; /* Filled in by U-Boot */
                                 interrupt-parent = <&UIC1>;
-                                interrupts = <0x1d 0x4>;
+                                interrupts = <28 0x4>;
                         };
 
                         UART3: serial@ef600600 {
@@ -270,7 +270,7 @@
                                 clock-frequency = <0>; /* Filled in by U-Boot */
                                 current-speed = <0>; /* Filled in by U-Boot */
                                 interrupt-parent = <&UIC1>;
-                                interrupts = <0x1e 0x4>;
+                                interrupts = <29 0x4>;
                         };
 
                         IIC0: i2c@ef600700 {
diff --git a/arch/powerpc/boot/dts/mpc8308rdb.dts b/arch/powerpc/boot/dts/mpc8308rdb.dts
new file mode 100644
index 000000000000..a97eb2db5a18
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8308rdb.dts
@@ -0,0 +1,303 @@
+/*
+ * MPC8308RDB Device Tree Source
+ *
+ * Copyright 2009 Freescale Semiconductor Inc.
+ * Copyright 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+
+/ {
+        compatible = "fsl,mpc8308rdb";
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        aliases {
+                ethernet0 = &enet0;
+                ethernet1 = &enet1;
+                serial0 = &serial0;
+                serial1 = &serial1;
+                pci0 = &pci0;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                PowerPC,8308@0 {
+                        device_type = "cpu";
+                        reg = <0x0>;
+                        d-cache-line-size = <32>;
+                        i-cache-line-size = <32>;
+                        d-cache-size = <16384>;
+                        i-cache-size = <16384>;
+                        timebase-frequency = <0>;       // from bootloader
+                        bus-frequency = <0>;            // from bootloader
+                        clock-frequency = <0>;          // from bootloader
+                };
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x08000000>;  // 128MB at 0
+        };
+
+        localbus@e0005000 {
+                #address-cells = <2>;
+                #size-cells = <1>;
+                compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";
+                reg = <0xe0005000 0x1000>;
+                interrupts = <77 0x8>;
+                interrupt-parent = <&ipic>;
+
+                // CS0 and CS1 are swapped when
+                // booting from nand, but the
+                // addresses are the same.
+                ranges = <0x0 0x0 0xfe000000 0x00800000
+                          0x1 0x0 0xe0600000 0x00002000
+                          0x2 0x0 0xf0000000 0x00020000
+                          0x3 0x0 0xfa000000 0x00008000>;
+
+                flash@0,0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "cfi-flash";
+                        reg = <0x0 0x0 0x800000>;
+                        bank-width = <2>;
+                        device-width = <1>;
+
+                        u-boot@0 {
+                                reg = <0x0 0x60000>;
+                                read-only;
+                        };
+                        env@60000 {
+                                reg = <0x60000 0x10000>;
+                        };
+                        env1@70000 {
+                                reg = <0x70000 0x10000>;
+                        };
+                        kernel@80000 {
+                                reg = <0x80000 0x200000>;
+                        };
+                        dtb@280000 {
+                                reg = <0x280000 0x10000>;
+                        };
+                        ramdisk@290000 {
+                                reg = <0x290000 0x570000>;
+                        };
+                };
+
+                nand@1,0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "fsl,mpc8315-fcm-nand",
+                                     "fsl,elbc-fcm-nand";
+                        reg = <0x1 0x0 0x2000>;
+
+                        jffs2@0 {
+                                reg = <0x0 0x2000000>;
+                        };
+                };
+        };
+
+        immr@e0000000 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                device_type = "soc";
+                compatible = "fsl,mpc8315-immr", "simple-bus";
+                ranges = <0 0xe0000000 0x00100000>;
+                reg = <0xe0000000 0x00000200>;
+                bus-frequency = <0>;
+
+                i2c@3000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        cell-index = <0>;
+                        compatible = "fsl-i2c";
+                        reg = <0x3000 0x100>;
+                        interrupts = <14 0x8>;
+                        interrupt-parent = <&ipic>;
+                        dfsrr;
+                        rtc@68 {
+                                compatible = "dallas,ds1339";
+                                reg = <0x68>;
+                        };
+                };
+
+                usb@23000 {
+                        compatible = "fsl-usb2-dr";
+                        reg = <0x23000 0x1000>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        interrupt-parent = <&ipic>;
+                        interrupts = <38 0x8>;
+                        dr_mode = "peripheral";
+                        phy_type = "ulpi";
+                };
+
+                enet0: ethernet@24000 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0x0 0x24000 0x1000>;
+
+                        cell-index = <0>;
+                        device_type = "network";
+                        model = "eTSEC";
+                        compatible = "gianfar";
+                        reg = <0x24000 0x1000>;
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        interrupts = <32 0x8 33 0x8 34 0x8>;
+                        interrupt-parent = <&ipic>;
+                        tbi-handle = < &tbi0 >;
+                        phy-handle = < &phy2 >;
+                        fsl,magic-packet;
+
+                        mdio@520 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,gianfar-mdio";
+                                reg = <0x520 0x20>;
+                                phy2: ethernet-phy@2 {
+                                        interrupt-parent = <&ipic>;
+                                        interrupts = <17 0x8>;
+                                        reg = <0x2>;
+                                        device_type = "ethernet-phy";
+                                };
+                                tbi0: tbi-phy@11 {
+                                        reg = <0x11>;
+                                        device_type = "tbi-phy";
+                                };
+                        };
+                };
+
+                enet1: ethernet@25000 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        cell-index = <1>;
+                        device_type = "network";
+                        model = "eTSEC";
+                        compatible = "gianfar";
+                        reg = <0x25000 0x1000>;
+                        ranges = <0x0 0x25000 0x1000>;
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        interrupts = <35 0x8 36 0x8 37 0x8>;
+                        interrupt-parent = <&ipic>;
+                        tbi-handle = < &tbi1 >;
+                        /* Vitesse 7385 isn't on the MDIO bus */
+                        fixed-link = <1 1 1000 0 0>;
+                        fsl,magic-packet;
+
+                        mdio@520 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,gianfar-tbi";
+                                reg = <0x520 0x20>;
+
+                                tbi1: tbi-phy@11 {
+                                        reg = <0x11>;
+                                        device_type = "tbi-phy";
+                                };
+                        };
+                };
+
+                serial0: serial@4500 {
+                        cell-index = <0>;
+                        device_type = "serial";
+                        compatible = "ns16550";
+                        reg = <0x4500 0x100>;
+                        clock-frequency = <133333333>;
+                        interrupts = <9 0x8>;
+                        interrupt-parent = <&ipic>;
+                };
+
+                serial1: serial@4600 {
+                        cell-index = <1>;
+                        device_type = "serial";
+                        compatible = "ns16550";
+                        reg = <0x4600 0x100>;
+                        clock-frequency = <133333333>;
+                        interrupts = <10 0x8>;
+                        interrupt-parent = <&ipic>;
+                };
+
+                gpio@c00 {
+                        #gpio-cells = <2>;
+                        device_type = "gpio";
+                        compatible = "fsl,mpc8308-gpio", "fsl,mpc8349-gpio";
+                        reg = <0xc00 0x18>;
+                        interrupts = <74 0x8>;
+                        interrupt-parent = <&ipic>;
+                        gpio-controller;
+                };
+
+                /* IPIC
+                 * interrupts cell = <intr #, sense>
+                 * sense values match linux IORESOURCE_IRQ_* defines:
+                 * sense == 8: Level, low assertion
+                 * sense == 2: Edge, high-to-low change
+                 */
+                ipic: interrupt-controller@700 {
+                        compatible = "fsl,ipic";
+                        interrupt-controller;
+                        #address-cells = <0>;
+                        #interrupt-cells = <2>;
+                        reg = <0x700 0x100>;
+                        device_type = "ipic";
+                };
+
+                ipic-msi@7c0 {
+                        compatible = "fsl,ipic-msi";
+                        reg = <0x7c0 0x40>;
+                        msi-available-ranges = <0x0 0x100>;
+                        interrupts = < 0x43 0x8
+                                        0x4  0x8
+                                        0x51 0x8
+                                        0x52 0x8
+                                        0x56 0x8
+                                        0x57 0x8
+                                        0x58 0x8
+                                        0x59 0x8 >;
+                        interrupt-parent = < &ipic >;
+                };
+
+        };
+
+        pci0: pcie@e0009000 {
+                #address-cells = <3>;
+                #size-cells = <2>;
+                #interrupt-cells = <1>;
+                device_type = "pci";
+                compatible = "fsl,mpc8308-pcie", "fsl,mpc8314-pcie";
+                reg = <0xe0009000 0x00001000
+                        0xb0000000 0x01000000>;
+                ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
+                          0x01000000 0 0x00000000 0xb1000000 0 0x00800000>;
+                bus-range = <0 0>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <0 0 0 1 &ipic 1 8
+                                 0 0 0 2 &ipic 1 8
+                                 0 0 0 3 &ipic 1 8
+                                 0 0 0 4 &ipic 1 8>;
+                interrupts = <0x1 0x8>;
+                interrupt-parent = <&ipic>;
+                clock-frequency = <0>;
+
+                pcie@0 {
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+                        device_type = "pci";
+                        reg = <0 0 0 0 0>;
+                        ranges = <0x02000000 0 0xa0000000
+                                  0x02000000 0 0xa0000000
+                                  0 0x10000000
+                                  0x01000000 0 0x00000000
+                                  0x01000000 0 0x00000000
+                                  0 0x00800000>;
+                };
+        };
+};
diff --git a/arch/powerpc/boot/dts/mpc8540ads.dts b/arch/powerpc/boot/dts/mpc8540ads.dts
index 9dc292962a9a..8d1bf0fd9268 100644
--- a/arch/powerpc/boot/dts/mpc8540ads.dts
+++ b/arch/powerpc/boot/dts/mpc8540ads.dts
@@ -71,14 +71,14 @@
                 };
 
                 memory-controller@2000 {
-                        compatible = "fsl,8540-memory-controller";
+                        compatible = "fsl,mpc8540-memory-controller";
                         reg = <0x2000 0x1000>;
                         interrupt-parent = <&mpic>;
                         interrupts = <18 2>;
                 };
 
                 L2: l2-cache-controller@20000 {
-                        compatible = "fsl,8540-l2-cache-controller";
+                        compatible = "fsl,mpc8540-l2-cache-controller";
                         reg = <0x20000 0x1000>;
                         cache-line-size = <32>; // 32 bytes
                         cache-size = <0x40000>; // L2, 256K
diff --git a/arch/powerpc/boot/dts/mpc8541cds.dts b/arch/powerpc/boot/dts/mpc8541cds.dts
index 9a3ad311aedf..87ff96549fac 100644
--- a/arch/powerpc/boot/dts/mpc8541cds.dts
+++ b/arch/powerpc/boot/dts/mpc8541cds.dts
@@ -71,14 +71,14 @@
                 };
 
                 memory-controller@2000 {
-                        compatible = "fsl,8541-memory-controller";
+                        compatible = "fsl,mpc8541-memory-controller";
                         reg = <0x2000 0x1000>;
                         interrupt-parent = <&mpic>;
                         interrupts = <18 2>;
                 };
 
                 L2: l2-cache-controller@20000 {
-                        compatible = "fsl,8541-l2-cache-controller";
+                        compatible = "fsl,mpc8541-l2-cache-controller";
                         reg = <0x20000 0x1000>;
                         cache-line-size = <32>; // 32 bytes
                         cache-size = <0x40000>; // L2, 256K
diff --git a/arch/powerpc/boot/dts/mpc8544ds.dts b/arch/powerpc/boot/dts/mpc8544ds.dts
index 98e94b465662..d793968743c9 100644
--- a/arch/powerpc/boot/dts/mpc8544ds.dts
+++ b/arch/powerpc/boot/dts/mpc8544ds.dts
@@ -73,14 +73,14 @@
                 };
 
                 memory-controller@2000 {
-                        compatible = "fsl,8544-memory-controller";
+                        compatible = "fsl,mpc8544-memory-controller";
                         reg = <0x2000 0x1000>;
                         interrupt-parent = <&mpic>;
                         interrupts = <18 2>;
                 };
 
                 L2: l2-cache-controller@20000 {
-                        compatible = "fsl,8544-l2-cache-controller";
+                        compatible = "fsl,mpc8544-l2-cache-controller";
                         reg = <0x20000 0x1000>;
                         cache-line-size = <32>; // 32 bytes
                         cache-size = <0x40000>; // L2, 256K
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts
index 0f5262452682..a17a5572fb73 100644
--- a/arch/powerpc/boot/dts/mpc8548cds.dts
+++ b/arch/powerpc/boot/dts/mpc8548cds.dts
@@ -74,14 +74,14 @@
                 };
 
                 memory-controller@2000 {
-                        compatible = "fsl,8548-memory-controller";
+                        compatible = "fsl,mpc8548-memory-controller";
                         reg = <0x2000 0x1000>;
                         interrupt-parent = <&mpic>;
                         interrupts = <18 2>;
                 };
 
                 L2: l2-cache-controller@20000 {
-                        compatible = "fsl,8548-l2-cache-controller";
+                        compatible = "fsl,mpc8548-l2-cache-controller";
                         reg = <0x20000 0x1000>;
                         cache-line-size = <32>; // 32 bytes
                         cache-size = <0x80000>; // L2, 512K
diff --git a/arch/powerpc/boot/dts/mpc8555cds.dts b/arch/powerpc/boot/dts/mpc8555cds.dts
index 065b2f093de2..5c5614f9eb17 100644
--- a/arch/powerpc/boot/dts/mpc8555cds.dts
+++ b/arch/powerpc/boot/dts/mpc8555cds.dts
@@ -71,14 +71,14 @@
                 };
 
                 memory-controller@2000 {
-                        compatible = "fsl,8555-memory-controller";
+                        compatible = "fsl,mpc8555-memory-controller";
                         reg = <0x2000 0x1000>;
                         interrupt-parent = <&mpic>;
                         interrupts = <18 2>;
                 };
 
                 L2: l2-cache-controller@20000 {
-                        compatible = "fsl,8555-l2-cache-controller";
+                        compatible = "fsl,mpc8555-l2-cache-controller";
                         reg = <0x20000 0x1000>;
                         cache-line-size = <32>; // 32 bytes
                         cache-size = <0x40000>; // L2, 256K
diff --git a/arch/powerpc/boot/dts/mpc8560ads.dts b/arch/powerpc/boot/dts/mpc8560ads.dts
index a5bb1ec70a5a..6e85e1ba0851 100644
--- a/arch/powerpc/boot/dts/mpc8560ads.dts
+++ b/arch/powerpc/boot/dts/mpc8560ads.dts
@@ -71,14 +71,14 @@
                 };
 
                 memory-controller@2000 {
-                        compatible = "fsl,8540-memory-controller";
+                        compatible = "fsl,mpc8540-memory-controller";
                         reg = <0x2000 0x1000>;
                         interrupt-parent = <&mpic>;
                         interrupts = <18 2>;
                 };
 
                 L2: l2-cache-controller@20000 {
-                        compatible = "fsl,8540-l2-cache-controller";
+                        compatible = "fsl,mpc8540-l2-cache-controller";
                         reg = <0x20000 0x1000>;
                         cache-line-size = <32>; // 32 bytes
                         cache-size = <0x40000>; // L2, 256K
diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts
index 92fb17876e7d..30cf0e098bb9 100644
--- a/arch/powerpc/boot/dts/mpc8568mds.dts
+++ b/arch/powerpc/boot/dts/mpc8568mds.dts
@@ -124,14 +124,14 @@
                 };
 
                 memory-controller@2000 {
-                        compatible = "fsl,8568-memory-controller";
+                        compatible = "fsl,mpc8568-memory-controller";
                         reg = <0x2000 0x1000>;
                         interrupt-parent = <&mpic>;
                         interrupts = <18 2>;
                 };
 
                 L2: l2-cache-controller@20000 {
-                        compatible = "fsl,8568-l2-cache-controller";
+                        compatible = "fsl,mpc8568-l2-cache-controller";
                         reg = <0x20000 0x1000>;
                         cache-line-size = <32>; // 32 bytes
                         cache-size = <0x80000>; // L2, 512K
diff --git a/arch/powerpc/boot/dts/p1021mds.dts b/arch/powerpc/boot/dts/p1021mds.dts
index 7fad2df25981..ad5b85269004 100644
--- a/arch/powerpc/boot/dts/p1021mds.dts
+++ b/arch/powerpc/boot/dts/p1021mds.dts
@@ -617,6 +617,7 @@
                 bus-frequency = <0>;
                 fsl,qe-num-riscs = <1>;
                 fsl,qe-num-snums = <28>;
+                status = "disabled"; /* no firmware loaded */
 
                 qeic: interrupt-controller@80 {
                         interrupt-controller;
diff --git a/arch/powerpc/boot/dts/p1022ds.dts b/arch/powerpc/boot/dts/p1022ds.dts
new file mode 100644
index 000000000000..8bcb10b92677
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1022ds.dts
@@ -0,0 +1,633 @@
+/*
+ * P1022 DS 36Bit Physical Address Map Device Tree Source
+ *
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/dts-v1/;
+/ {
+        model = "fsl,P1022";
+        compatible = "fsl,P1022DS";
+        #address-cells = <2>;
+        #size-cells = <2>;
+        interrupt-parent = <&mpic>;
+
+        aliases {
+                ethernet0 = &enet0;
+                ethernet1 = &enet1;
+                serial0 = &serial0;
+                serial1 = &serial1;
+                pci0 = &pci0;
+                pci1 = &pci1;
+                pci2 = &pci2;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                PowerPC,P1022@0 {
+                        device_type = "cpu";
+                        reg = <0x0>;
+                        next-level-cache = <&L2>;
+                };
+
+                PowerPC,P1022@1 {
+                        device_type = "cpu";
+                        reg = <0x1>;
+                        next-level-cache = <&L2>;
+                };
+        };
+
+        memory {
+                device_type = "memory";
+        };
+
+        localbus@fffe05000 {
+                #address-cells = <2>;
+                #size-cells = <1>;
+                compatible = "fsl,p1022-elbc", "fsl,elbc", "simple-bus";
+                reg = <0 0xffe05000 0 0x1000>;
+                interrupts = <19 2>;
+
+                ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
+                          0x1 0x0 0xf 0xe0000000 0x08000000
+                          0x2 0x0 0x0 0xffa00000 0x00040000
+                          0x3 0x0 0xf 0xffdf0000 0x00008000>;
+
+                nor@0,0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "cfi-flash";
+                        reg = <0x0 0x0 0x8000000>;
+                        bank-width = <2>;
+                        device-width = <1>;
+
+                        partition@0 {
+                                reg = <0x0 0x03000000>;
+                                label = "ramdisk-nor";
+                                read-only;
+                        };
+
+                        partition@3000000 {
+                                reg = <0x03000000 0x00e00000>;
+                                label = "diagnostic-nor";
+                                read-only;
+                        };
+
+                        partition@3e00000 {
+                                reg = <0x03e00000 0x00200000>;
+                                label = "dink-nor";
+                                read-only;
+                        };
+
+                        partition@4000000 {
+                                reg = <0x04000000 0x00400000>;
+                                label = "kernel-nor";
+                                read-only;
+                        };
+
+                        partition@4400000 {
+                                reg = <0x04400000 0x03b00000>;
+                                label = "jffs2-nor";
+                        };
+
+                        partition@7f00000 {
+                                reg = <0x07f00000 0x00080000>;
+                                label = "dtb-nor";
+                                read-only;
+                        };
+
+                        partition@7f80000 {
+                                reg = <0x07f80000 0x00080000>;
+                                label = "u-boot-nor";
+                                read-only;
+                        };
+                };
+
+                nand@2,0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "fsl,elbc-fcm-nand";
+                        reg = <0x2 0x0 0x40000>;
+
+                        partition@0 {
+                                reg = <0x0 0x02000000>;
+                                label = "u-boot-nand";
+                                read-only;
+                        };
+
+                        partition@2000000 {
+                                reg = <0x02000000 0x10000000>;
+                                label = "jffs2-nand";
+                        };
+
+                        partition@12000000 {
+                                reg = <0x12000000 0x10000000>;
+                                label = "ramdisk-nand";
+                                read-only;
+                        };
+
+                        partition@22000000 {
+                                reg = <0x22000000 0x04000000>;
+                                label = "kernel-nand";
+                        };
+
+                        partition@26000000 {
+                                reg = <0x26000000 0x01000000>;
+                                label = "dtb-nand";
+                                read-only;
+                        };
+
+                        partition@27000000 {
+                                reg = <0x27000000 0x19000000>;
+                                label = "reserved-nand";
+                        };
+                };
+        };
+
+        soc@fffe00000 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                device_type = "soc";
+                compatible = "fsl,p1022-immr", "simple-bus";
+                ranges = <0x0 0xf 0xffe00000 0x100000>;
+                bus-frequency = <0>;            // Filled out by uboot.
+
+                ecm-law@0 {
+                        compatible = "fsl,ecm-law";
+                        reg = <0x0 0x1000>;
+                        fsl,num-laws = <12>;
+                };
+
+                ecm@1000 {
+                        compatible = "fsl,p1022-ecm", "fsl,ecm";
+                        reg = <0x1000 0x1000>;
+                        interrupts = <16 2>;
+                };
+
+                memory-controller@2000 {
+                        compatible = "fsl,p1022-memory-controller";
+                        reg = <0x2000 0x1000>;
+                        interrupts = <16 2>;
+                };
+
+                i2c@3000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        cell-index = <0>;
+                        compatible = "fsl-i2c";
+                        reg = <0x3000 0x100>;
+                        interrupts = <43 2>;
+                        dfsrr;
+                };
+
+                i2c@3100 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        cell-index = <1>;
+                        compatible = "fsl-i2c";
+                        reg = <0x3100 0x100>;
+                        interrupts = <43 2>;
+                        dfsrr;
+
+                        wm8776:codec@1a {
+                                compatible = "wlf,wm8776";
+                                reg = <0x1a>;
+                                /* MCLK source is a stand-alone oscillator */
+                                clock-frequency = <12288000>;
+                        };
+                };
+
+                serial0: serial@4500 {
+                        cell-index = <0>;
+                        device_type = "serial";
+                        compatible = "ns16550";
+                        reg = <0x4500 0x100>;
+                        clock-frequency = <0>;
+                        interrupts = <42 2>;
+                };
+
+                serial1: serial@4600 {
+                        cell-index = <1>;
+                        device_type = "serial";
+                        compatible = "ns16550";
+                        reg = <0x4600 0x100>;
+                        clock-frequency = <0>;
+                        interrupts = <42 2>;
+                };
+
+                spi@7000 {
+                        cell-index = <0>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "fsl,espi";
+                        reg = <0x7000 0x1000>;
+                        interrupts = <59 0x2>;
+                        espi,num-ss-bits = <4>;
+                        mode = "cpu";
+
+                        fsl_m25p80@0 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                compatible = "fsl,espi-flash";
+                                reg = <0>;
+                                linux,modalias = "fsl_m25p80";
+                                spi-max-frequency = <40000000>; /* input clock */
+                                partition@0 {
+                                        label = "u-boot-spi";
+                                        reg = <0x00000000 0x00100000>;
+                                        read-only;
+                                };
+                                partition@100000 {
+                                        label = "kernel-spi";
+                                        reg = <0x00100000 0x00500000>;
+                                        read-only;
+                                };
+                                partition@600000 {
+                                        label = "dtb-spi";
+                                        reg = <0x00600000 0x00100000>;
+                                        read-only;
+                                };
+                                partition@700000 {
+                                        label = "file system-spi";
+                                        reg = <0x00700000 0x00900000>;
+                                };
+                        };
+                };
+
+                ssi@15000 {
+                        compatible = "fsl,mpc8610-ssi";
+                        cell-index = <0>;
+                        reg = <0x15000 0x100>;
+                        interrupts = <75 2>;
+                        fsl,mode = "i2s-slave";
+                        codec-handle = <&wm8776>;
+                        fsl,playback-dma = <&dma00>;
+                        fsl,capture-dma = <&dma01>;
+                        fsl,fifo-depth = <16>;
+                };
+
+                dma@c300 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "fsl,eloplus-dma";
+                        reg = <0xc300 0x4>;
+                        ranges = <0x0 0xc100 0x200>;
+                        cell-index = <1>;
+                        dma00: dma-channel@0 {
+                                compatible = "fsl,eloplus-dma-channel";
+                                reg = <0x0 0x80>;
+                                cell-index = <0>;
+                                interrupts = <76 2>;
+                        };
+                        dma01: dma-channel@80 {
+                                compatible = "fsl,eloplus-dma-channel";
+                                reg = <0x80 0x80>;
+                                cell-index = <1>;
+                                interrupts = <77 2>;
+                        };
+                        dma-channel@100 {
+                                compatible = "fsl,eloplus-dma-channel";
+                                reg = <0x100 0x80>;
+                                cell-index = <2>;
+                                interrupts = <78 2>;
+                        };
+                        dma-channel@180 {
+                                compatible = "fsl,eloplus-dma-channel";
+                                reg = <0x180 0x80>;
+                                cell-index = <3>;
+                                interrupts = <79 2>;
+                        };
+                };
+
+                gpio: gpio-controller@f000 {
+                        #gpio-cells = <2>;
+                        compatible = "fsl,mpc8572-gpio";
+                        reg = <0xf000 0x100>;
+                        interrupts = <47 0x2>;
+                        gpio-controller;
+                };
+
+                L2: l2-cache-controller@20000 {
+                        compatible = "fsl,p1022-l2-cache-controller";
+                        reg = <0x20000 0x1000>;
+                        cache-line-size = <32>; // 32 bytes
+                        cache-size = <0x40000>; // L2, 256K
+                        interrupts = <16 2>;
+                };
+
+                dma@21300 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "fsl,eloplus-dma";
+                        reg = <0x21300 0x4>;
+                        ranges = <0x0 0x21100 0x200>;
+                        cell-index = <0>;
+                        dma-channel@0 {
+                                compatible = "fsl,eloplus-dma-channel";
+                                reg = <0x0 0x80>;
+                                cell-index = <0>;
+                                interrupts = <20 2>;
+                        };
+                        dma-channel@80 {
+                                compatible = "fsl,eloplus-dma-channel";
+                                reg = <0x80 0x80>;
+                                cell-index = <1>;
+                                interrupts = <21 2>;
+                        };
+                        dma-channel@100 {
+                                compatible = "fsl,eloplus-dma-channel";
+                                reg = <0x100 0x80>;
+                                cell-index = <2>;
+                                interrupts = <22 2>;
+                        };
+                        dma-channel@180 {
+                                compatible = "fsl,eloplus-dma-channel";
+                                reg = <0x180 0x80>;
+                                cell-index = <3>;
+                                interrupts = <23 2>;
+                        };
+                };
+
+                usb@22000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "fsl-usb2-dr";
+                        reg = <0x22000 0x1000>;
+                        interrupts = <28 0x2>;
+                        phy_type = "ulpi";
+                };
+
+                mdio@24000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "fsl,etsec2-mdio";
+                        reg = <0x24000 0x1000 0xb0030 0x4>;
+
+                        phy0: ethernet-phy@0 {
+                                interrupts = <3 1>;
+                                reg = <0x1>;
+                        };
+                        phy1: ethernet-phy@1 {
+                                interrupts = <9 1>;
+                                reg = <0x2>;
+                        };
+                };
+
+                mdio@25000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "fsl,etsec2-mdio";
+                        reg = <0x25000 0x1000 0xb1030 0x4>;
+                };
+
+                enet0: ethernet@B0000 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        cell-index = <0>;
+                        device_type = "network";
+                        model = "eTSEC";
+                        compatible = "fsl,etsec2";
+                        fsl,num_rx_queues = <0x8>;
+                        fsl,num_tx_queues = <0x8>;
+                        fsl,magic-packet;
+                        fsl,wake-on-filer;
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        fixed-link = <1 1 1000 0 0>;
+                        phy-handle = <&phy0>;
+                        phy-connection-type = "rgmii-id";
+                        queue-group@0{
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                reg = <0xB0000 0x1000>;
+                                interrupts = <29 2 30 2 34 2>;
+                        };
+                        queue-group@1{
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                reg = <0xB4000 0x1000>;
+                                interrupts = <17 2 18 2 24 2>;
+                        };
+                };
+
+                enet1: ethernet@B1000 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        cell-index = <0>;
+                        device_type = "network";
+                        model = "eTSEC";
+                        compatible = "fsl,etsec2";
+                        fsl,num_rx_queues = <0x8>;
+                        fsl,num_tx_queues = <0x8>;
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        fixed-link = <1 1 1000 0 0>;
+                        phy-handle = <&phy1>;
+                        phy-connection-type = "rgmii-id";
+                        queue-group@0{
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                reg = <0xB1000 0x1000>;
+                                interrupts = <35 2 36 2 40 2>;
+                        };
+                        queue-group@1{
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                reg = <0xB5000 0x1000>;
+                                interrupts = <51 2 52 2 67 2>;
+                        };
+                };
+
+                sdhci@2e000 {
+                        compatible = "fsl,p1022-esdhc", "fsl,esdhc";
+                        reg = <0x2e000 0x1000>;
+                        interrupts = <72 0x2>;
+                        fsl,sdhci-auto-cmd12;
+                        /* Filled in by U-Boot */
+                        clock-frequency = <0>;
+                };
+
+                crypto@30000 {
+                        compatible = "fsl,sec3.3", "fsl,sec3.1", "fsl,sec3.0",
+                                     "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1",
+                                     "fsl,sec2.0";
+                        reg = <0x30000 0x10000>;
+                        interrupts = <45 2 58 2>;
+                        fsl,num-channels = <4>;
+                        fsl,channel-fifo-len = <24>;
+                        fsl,exec-units-mask = <0x97c>;
+                        fsl,descriptor-types-mask = <0x3a30abf>;
+                };
+
+                sata@18000 {
+                        compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
+                        reg = <0x18000 0x1000>;
+                        cell-index = <1>;
+                        interrupts = <74 0x2>;
+                };
+
+                sata@19000 {
+                        compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
+                        reg = <0x19000 0x1000>;
+                        cell-index = <2>;
+                        interrupts = <41 0x2>;
+                };
+
+                power@e0070{
+                        compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc";
+                        reg = <0xe0070 0x20>;
+                };
+
+                display@10000 {
+                        compatible = "fsl,diu", "fsl,p1022-diu";
+                        reg = <0x10000 1000>;
+                        interrupts = <64 2>;
+                };
+
+                timer@41100 {
+                        compatible = "fsl,mpic-global-timer";
+                        reg = <0x41100 0x204>;
+                        interrupts = <0xf7 0x2>;
+                };
+
+                mpic: pic@40000 {
+                        interrupt-controller;
+                        #address-cells = <0>;
+                        #interrupt-cells = <2>;
+                        reg = <0x40000 0x40000>;
+                        compatible = "chrp,open-pic";
+                        device_type = "open-pic";
+                };
+
+                msi@41600 {
+                        compatible = "fsl,p1022-msi", "fsl,mpic-msi";
+                        reg = <0x41600 0x80>;
+                        msi-available-ranges = <0 0x100>;
+                        interrupts = <
+                                0xe0 0
+                                0xe1 0
+                                0xe2 0
+                                0xe3 0
+                                0xe4 0
+                                0xe5 0
+                                0xe6 0
+                                0xe7 0>;
+                };
+
+                global-utilities@e0000 {        //global utilities block
+                        compatible = "fsl,p1022-guts";
+                        reg = <0xe0000 0x1000>;
+                        fsl,has-rstcr;
+                };
+        };
+
+        pci0: pcie@fffe09000 {
+                compatible = "fsl,p1022-pcie";
+                device_type = "pci";
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                reg = <0xf 0xffe09000 0 0x1000>;
+                bus-range = <0 255>;
+                ranges = <0x2000000 0x0 0xa0000000 0xc 0x20000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
+                clock-frequency = <33333333>;
+                interrupts = <16 2>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0 0 1 &mpic 4 1
+                        0000 0 0 2 &mpic 5 1
+                        0000 0 0 3 &mpic 6 1
+                        0000 0 0 4 &mpic 7 1
+                        >;
+                pcie@0 {
+                        reg = <0x0 0x0 0x0 0x0 0x0>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        device_type = "pci";
+                        ranges = <0x2000000 0x0 0xe0000000
+                                  0x2000000 0x0 0xe0000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                };
+        };
+
+        pci1: pcie@fffe0a000 {
+                compatible = "fsl,p1022-pcie";
+                device_type = "pci";
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                reg = <0xf 0xffe0a000 0 0x1000>;
+                bus-range = <0 255>;
+                ranges = <0x2000000 0x0 0xc0000000 0xc 0x40000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x10000>;
+                clock-frequency = <33333333>;
+                interrupts = <16 2>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0 0 1 &mpic 0 1
+                        0000 0 0 2 &mpic 1 1
+                        0000 0 0 3 &mpic 2 1
+                        0000 0 0 4 &mpic 3 1
+                        >;
+                pcie@0 {
+                        reg = <0x0 0x0 0x0 0x0 0x0>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        device_type = "pci";
+                        ranges = <0x2000000 0x0 0xe0000000
+                                  0x2000000 0x0 0xe0000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                };
+        };
+
+
+        pci2: pcie@fffe0b000 {
+                compatible = "fsl,p1022-pcie";
+                device_type = "pci";
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                reg = <0xf 0xffe0b000 0 0x1000>;
+                bus-range = <0 255>;
+                ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
+                clock-frequency = <33333333>;
+                interrupts = <16 2>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0 0 1 &mpic 8 1
+                        0000 0 0 2 &mpic 9 1
+                        0000 0 0 3 &mpic 10 1
+                        0000 0 0 4 &mpic 11 1
+                        >;
+                pcie@0 {
+                        reg = <0x0 0x0 0x0 0x0 0x0>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        device_type = "pci";
+                        ranges = <0x2000000 0x0 0xe0000000
+                                  0x2000000 0x0 0xe0000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                };
+        };
+};
diff --git a/arch/powerpc/boot/dts/pdm360ng.dts b/arch/powerpc/boot/dts/pdm360ng.dts
new file mode 100644
index 000000000000..94dfa5c9a7f9
--- /dev/null
+++ b/arch/powerpc/boot/dts/pdm360ng.dts
@@ -0,0 +1,410 @@
+/*
+ * Device Tree Source for IFM PDM360NG.
+ *
+ * Copyright 2009 - 2010 DENX Software Engineering.
+ * Anatolij Gustschin <agust@denx.de>
+ *
+ * Based on MPC5121E ADS dts.
+ * Copyright 2008 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+
+/ {
+        model = "pdm360ng";
+        compatible = "ifm,pdm360ng";
+        #address-cells = <1>;
+        #size-cells = <1>;
+        interrupt-parent = <&ipic>;
+
+        aliases {
+                ethernet0 = &eth0;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                PowerPC,5121@0 {
+                        device_type = "cpu";
+                        reg = <0>;
+                        d-cache-line-size = <0x20>;     // 32 bytes
+                        i-cache-line-size = <0x20>;     // 32 bytes
+                        d-cache-size = <0x8000>;        // L1, 32K
+                        i-cache-size = <0x8000>;        // L1, 32K
+                        timebase-frequency = <49500000>;// 49.5 MHz (csb/4)
+                        bus-frequency = <198000000>;    // 198 MHz csb bus
+                        clock-frequency = <396000000>;  // 396 MHz ppc core
+                };
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x20000000>;  // 512MB at 0
+        };
+
+        nfc@40000000 {
+                compatible = "fsl,mpc5121-nfc";
+                reg = <0x40000000 0x100000>;
+                interrupts = <0x6 0x8>;
+                #address-cells = <0x1>;
+                #size-cells = <0x1>;
+                bank-width = <0x1>;
+                chips = <0x1>;
+
+                partition@0 {
+                        label = "nand0";
+                        reg = <0x0 0x40000000>;
+                };
+        };
+
+        sram@50000000 {
+                compatible = "fsl,mpc5121-sram";
+                reg = <0x50000000 0x20000>;     // 128K at 0x50000000
+        };
+
+        localbus@80000020 {
+                compatible = "fsl,mpc5121-localbus";
+                #address-cells = <2>;
+                #size-cells = <1>;
+                reg = <0x80000020 0x40>;
+
+                ranges = <0x0 0x0 0xf0000000 0x10000000   /* Flash */
+                          0x2 0x0 0x50040000 0x00020000>; /* CS2: MRAM */
+
+                flash@0,0 {
+                        compatible = "amd,s29gl01gp", "cfi-flash";
+                        reg = <0 0x00000000 0x08000000
+                               0 0x08000000 0x08000000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        bank-width = <4>;
+                        device-width = <2>;
+
+                        partition@0 {
+                                label = "u-boot";
+                                reg = <0x00000000 0x00080000>;
+                                read-only;
+                        };
+                        partition@80000 {
+                                label = "environment";
+                                reg = <0x00080000 0x00080000>;
+                                read-only;
+                        };
+                        partition@100000 {
+                                label = "splash-image";
+                                reg = <0x00100000 0x00080000>;
+                                read-only;
+                        };
+                        partition@180000 {
+                                label = "device-tree";
+                                reg = <0x00180000 0x00040000>;
+                        };
+                        partition@1c0000 {
+                                label = "kernel";
+                                reg = <0x001c0000 0x00500000>;
+                        };
+                        partition@6c0000 {
+                                label = "filesystem";
+                                reg = <0x006c0000 0x07940000>;
+                        };
+                };
+
+                mram0@2,0 {
+                        compatible = "mtd-ram";
+                        reg = <2 0x00000 0x10000>;
+                        bank-width = <2>;
+                };
+
+                mram1@2,10000 {
+                        compatible = "mtd-ram";
+                        reg = <2 0x010000 0x10000>;
+                        bank-width = <2>;
+                };
+        };
+
+        soc@80000000 {
+                compatible = "fsl,mpc5121-immr";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                #interrupt-cells = <2>;
+                ranges = <0x0 0x80000000 0x400000>;
+                reg = <0x80000000 0x400000>;
+                bus-frequency = <66000000>;     // 66 MHz ips bus
+
+                // IPIC
+                // interrupts cell = <intr #, sense>
+                // sense values match linux IORESOURCE_IRQ_* defines:
+                // sense == 8: Level, low assertion
+                // sense == 2: Edge, high-to-low change
+                //
+                ipic: interrupt-controller@c00 {
+                        compatible = "fsl,mpc5121-ipic", "fsl,ipic";
+                        interrupt-controller;
+                        #address-cells = <0>;
+                        #interrupt-cells = <2>;
+                        reg = <0xc00 0x100>;
+                };
+
+                rtc@a00 {       // Real time clock
+                        compatible = "fsl,mpc5121-rtc";
+                        reg = <0xa00 0x100>;
+                        interrupts = <79 0x8 80 0x8>;
+                };
+
+                reset@e00 {     // Reset module
+                        compatible = "fsl,mpc5121-reset";
+                        reg = <0xe00 0x100>;
+                };
+
+                clock@f00 {     // Clock control
+                        compatible = "fsl,mpc5121-clock";
+                        reg = <0xf00 0x100>;
+                };
+
+                pmc@1000{       //Power Management Controller
+                        compatible = "fsl,mpc5121-pmc";
+                        reg = <0x1000 0x100>;
+                        interrupts = <83 0x2>;
+                };
+
+                gpio@1100 {
+                        compatible = "fsl,mpc5121-gpio";
+                        reg = <0x1100 0x100>;
+                        interrupts = <78 0x8>;
+                };
+
+                can@1300 {
+                        compatible = "fsl,mpc5121-mscan";
+                        interrupts = <12 0x8>;
+                        reg = <0x1300 0x80>;
+                };
+
+                can@1380 {
+                        compatible = "fsl,mpc5121-mscan";
+                        interrupts = <13 0x8>;
+                        reg = <0x1380 0x80>;
+                };
+
+                i2c@1700 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "fsl,mpc5121-i2c";
+                        reg = <0x1700 0x20>;
+                        interrupts = <0x9 0x8>;
+                        fsl,preserve-clocking;
+
+                        eeprom@50 {
+                                compatible = "at,24c01";
+                                reg = <0x50>;
+                        };
+
+                        rtc@68 {
+                                compatible = "stm,m41t00";
+                                reg = <0x68>;
+                        };
+                };
+
+                i2c@1740 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "fsl,mpc5121-i2c";
+                        reg = <0x1740 0x20>;
+                        interrupts = <0xb 0x8>;
+                        fsl,preserve-clocking;
+                };
+
+                i2ccontrol@1760 {
+                        compatible = "fsl,mpc5121-i2c-ctrl";
+                        reg = <0x1760 0x8>;
+                };
+
+                axe@2000 {
+                        compatible = "fsl,mpc5121-axe";
+                        reg = <0x2000 0x100>;
+                        interrupts = <42 0x8>;
+                };
+
+                display@2100 {
+                        compatible = "fsl,mpc5121-diu";
+                        reg = <0x2100 0x100>;
+                        interrupts = <64 0x8>;
+                };
+
+                can@2300 {
+                        compatible = "fsl,mpc5121-mscan";
+                        interrupts = <90 0x8>;
+                        reg = <0x2300 0x80>;
+                };
+
+                can@2380 {
+                        compatible = "fsl,mpc5121-mscan";
+                        interrupts = <91 0x8>;
+                        reg = <0x2380 0x80>;
+                };
+
+                viu@2400 {
+                        compatible = "fsl,mpc5121-viu";
+                        reg = <0x2400 0x400>;
+                        interrupts = <67 0x8>;
+                };
+
+                mdio@2800 {
+                        compatible = "fsl,mpc5121-fec-mdio";
+                        reg = <0x2800 0x200>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        phy: ethernet-phy@0 {
+                                compatible = "smsc,lan8700";
+                                reg = <0x1f>;
+                        };
+                };
+
+                eth0: ethernet@2800 {
+                        compatible = "fsl,mpc5121-fec";
+                        reg = <0x2800 0x200>;
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        interrupts = <4 0x8>;
+                        phy-handle = < &phy >;
+                };
+
+                // USB1 using external ULPI PHY
+                usb@3000 {
+                        compatible = "fsl,mpc5121-usb2-dr";
+                        reg = <0x3000 0x600>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        interrupts = <43 0x8>;
+                        dr_mode = "host";
+                        phy_type = "ulpi";
+                };
+
+                // USB0 using internal UTMI PHY
+                usb@4000 {
+                        compatible = "fsl,mpc5121-usb2-dr";
+                        reg = <0x4000 0x600>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        interrupts = <44 0x8>;
+                        dr_mode = "otg";
+                        phy_type = "utmi_wide";
+                        fsl,invert-pwr-fault;
+                };
+
+                // IO control
+                ioctl@a000 {
+                        compatible = "fsl,mpc5121-ioctl";
+                        reg = <0xA000 0x1000>;
+                };
+
+                // 512x PSCs are not 52xx PSCs compatible
+                serial@11000 {
+                        compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
+                        cell-index = <0>;
+                        reg = <0x11000 0x100>;
+                        interrupts = <40 0x8>;
+                        fsl,rx-fifo-size = <16>;
+                        fsl,tx-fifo-size = <16>;
+                };
+
+                serial@11100 {
+                        compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
+                        cell-index = <1>;
+                        reg = <0x11100 0x100>;
+                        interrupts = <40 0x8>;
+                        fsl,rx-fifo-size = <16>;
+                        fsl,tx-fifo-size = <16>;
+                };
+
+                serial@11200 {
+                        compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
+                        cell-index = <2>;
+                        reg = <0x11200 0x100>;
+                        interrupts = <40 0x8>;
+                        fsl,rx-fifo-size = <16>;
+                        fsl,tx-fifo-size = <16>;
+                };
+
+                serial@11300 {
+                        compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
+                        cell-index = <3>;
+                        reg = <0x11300 0x100>;
+                        interrupts = <40 0x8>;
+                        fsl,rx-fifo-size = <16>;
+                        fsl,tx-fifo-size = <16>;
+                };
+
+                serial@11400 {
+                        compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
+                        cell-index = <4>;
+                        reg = <0x11400 0x100>;
+                        interrupts = <40 0x8>;
+                        fsl,rx-fifo-size = <16>;
+                        fsl,tx-fifo-size = <16>;
+                };
+
+                serial@11600 {
+                        compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
+                        cell-index = <6>;
+                        reg = <0x11600 0x100>;
+                        interrupts = <40 0x8>;
+                        fsl,rx-fifo-size = <16>;
+                        fsl,tx-fifo-size = <16>;
+                };
+
+                serial@11800 {
+                        compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
+                        cell-index = <8>;
+                        reg = <0x11800 0x100>;
+                        interrupts = <40 0x8>;
+                        fsl,rx-fifo-size = <16>;
+                        fsl,tx-fifo-size = <16>;
+                };
+
+                serial@11B00 {
+                        compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
+                        cell-index = <11>;
+                        reg = <0x11B00 0x100>;
+                        interrupts = <40 0x8>;
+                        fsl,rx-fifo-size = <16>;
+                        fsl,tx-fifo-size = <16>;
+                };
+
+                pscfifo@11f00 {
+                        compatible = "fsl,mpc5121-psc-fifo";
+                        reg = <0x11f00 0x100>;
+                        interrupts = <40 0x8>;
+                };
+
+                spi@11900 {
+                        compatible = "fsl,mpc5121-psc-spi", "fsl,mpc5121-psc";
+                        cell-index = <9>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x11900 0x100>;
+                        interrupts = <40 0x8>;
+                        fsl,rx-fifo-size = <16>;
+                        fsl,tx-fifo-size = <16>;
+
+                        // 7845 touch screen controller
+                        ts@0 {
+                                compatible = "ti,ads7846";
+                                reg = <0x0>;
+                                spi-max-frequency = <3000000>;
+                                // pen irq is GPIO25
+                                interrupts = <78 0x8>;
+                        };
+                };
+
+                dma@14000 {
+                        compatible = "fsl,mpc5121-dma";
+                        reg = <0x14000 0x1800>;
+                        interrupts = <65 0x8>;
+                };
+        };
+};
diff --git a/arch/powerpc/boot/dts/stxssa8555.dts b/arch/powerpc/boot/dts/stxssa8555.dts
new file mode 100644
index 000000000000..49efd44057d7
--- /dev/null
+++ b/arch/powerpc/boot/dts/stxssa8555.dts
@@ -0,0 +1,380 @@
+/*
+ * MPC8555-based STx GP3 Device Tree Source
+ *
+ * Copyright 2006, 2008 Freescale Semiconductor Inc.
+ *
+ * Copyright 2010 Silicon Turnkey Express LLC.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+
+/ {
+        model = "stx,gp3";
+        compatible = "stx,gp3-8560", "stx,gp3";
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        aliases {
+                ethernet0 = &enet0;
+                ethernet1 = &enet1;
+                serial0 = &serial0;
+                serial1 = &serial1;
+                pci0 = &pci0;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                PowerPC,8555@0 {
+                        device_type = "cpu";
+                        reg = <0x0>;
+                        d-cache-line-size = <32>;       // 32 bytes
+                        i-cache-line-size = <32>;       // 32 bytes
+                        d-cache-size = <0x8000>;                // L1, 32K
+                        i-cache-size = <0x8000>;                // L1, 32K
+                        timebase-frequency = <0>;       //  33 MHz, from uboot
+                        bus-frequency = <0>;    // 166 MHz
+                        clock-frequency = <0>;  // 825 MHz, from uboot
+                        next-level-cache = <&L2>;
+                };
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x10000000>;
+        };
+
+        soc8555@e0000000 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                device_type = "soc";
+                compatible = "simple-bus";
+                ranges = <0x0 0xe0000000 0x100000>;
+                bus-frequency = <0>;
+
+                ecm-law@0 {
+                        compatible = "fsl,ecm-law";
+                        reg = <0x0 0x1000>;
+                        fsl,num-laws = <8>;
+                };
+
+                ecm@1000 {
+                        compatible = "fsl,mpc8555-ecm", "fsl,ecm";
+                        reg = <0x1000 0x1000>;
+                        interrupts = <17 2>;
+                        interrupt-parent = <&mpic>;
+                };
+
+                memory-controller@2000 {
+                        compatible = "fsl,mpc8555-memory-controller";
+                        reg = <0x2000 0x1000>;
+                        interrupt-parent = <&mpic>;
+                        interrupts = <18 2>;
+                };
+
+                L2: l2-cache-controller@20000 {
+                        compatible = "fsl,mpc8555-l2-cache-controller";
+                        reg = <0x20000 0x1000>;
+                        cache-line-size = <32>; // 32 bytes
+                        cache-size = <0x40000>; // L2, 256K
+                        interrupt-parent = <&mpic>;
+                        interrupts = <16 2>;
+                };
+
+                i2c@3000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        cell-index = <0>;
+                        compatible = "fsl-i2c";
+                        reg = <0x3000 0x100>;
+                        interrupts = <43 2>;
+                        interrupt-parent = <&mpic>;
+                        dfsrr;
+                };
+
+                dma@21300 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "fsl,mpc8555-dma", "fsl,eloplus-dma";
+                        reg = <0x21300 0x4>;
+                        ranges = <0x0 0x21100 0x200>;
+                        cell-index = <0>;
+                        dma-channel@0 {
+                                compatible = "fsl,mpc8555-dma-channel",
+                                                "fsl,eloplus-dma-channel";
+                                reg = <0x0 0x80>;
+                                cell-index = <0>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <20 2>;
+                        };
+                        dma-channel@80 {
+                                compatible = "fsl,mpc8555-dma-channel",
+                                                "fsl,eloplus-dma-channel";
+                                reg = <0x80 0x80>;
+                                cell-index = <1>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <21 2>;
+                        };
+                        dma-channel@100 {
+                                compatible = "fsl,mpc8555-dma-channel",
+                                                "fsl,eloplus-dma-channel";
+                                reg = <0x100 0x80>;
+                                cell-index = <2>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <22 2>;
+                        };
+                        dma-channel@180 {
+                                compatible = "fsl,mpc8555-dma-channel",
+                                                "fsl,eloplus-dma-channel";
+                                reg = <0x180 0x80>;
+                                cell-index = <3>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <23 2>;
+                        };
+                };
+
+                enet0: ethernet@24000 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        cell-index = <0>;
+                        device_type = "network";
+                        model = "TSEC";
+                        compatible = "gianfar";
+                        reg = <0x24000 0x1000>;
+                        ranges = <0x0 0x24000 0x1000>;
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        interrupts = <29 2 30 2 34 2>;
+                        interrupt-parent = <&mpic>;
+                        tbi-handle = <&tbi0>;
+                        phy-handle = <&phy0>;
+
+                        mdio@520 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,gianfar-mdio";
+                                reg = <0x520 0x20>;
+
+                                phy0: ethernet-phy@2 {
+                                        interrupt-parent = <&mpic>;
+                                        interrupts = <5 1>;
+                                        reg = <0x2>;
+                                        device_type = "ethernet-phy";
+                                };
+                                phy1: ethernet-phy@4 {
+                                        interrupt-parent = <&mpic>;
+                                        interrupts = <5 1>;
+                                        reg = <0x4>;
+                                        device_type = "ethernet-phy";
+                                };
+                                tbi0: tbi-phy@11 {
+                                        reg = <0x11>;
+                                        device_type = "tbi-phy";
+                                };
+                        };
+                };
+
+                enet1: ethernet@25000 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        cell-index = <1>;
+                        device_type = "network";
+                        model = "TSEC";
+                        compatible = "gianfar";
+                        reg = <0x25000 0x1000>;
+                        ranges = <0x0 0x25000 0x1000>;
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        interrupts = <35 2 36 2 40 2>;
+                        interrupt-parent = <&mpic>;
+                        tbi-handle = <&tbi1>;
+                        phy-handle = <&phy1>;
+
+                        mdio@520 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,gianfar-tbi";
+                                reg = <0x520 0x20>;
+
+                                tbi1: tbi-phy@11 {
+                                        reg = <0x11>;
+                                        device_type = "tbi-phy";
+                                };
+                        };
+                };
+
+                serial0: serial@4500 {
+                        cell-index = <0>;
+                        device_type = "serial";
+                        compatible = "ns16550";
+                        reg = <0x4500 0x100>;   // reg base, size
+                        clock-frequency = <0>;  // should we fill in in uboot?
+                        interrupts = <42 2>;
+                        interrupt-parent = <&mpic>;
+                };
+
+                serial1: serial@4600 {
+                        cell-index = <1>;
+                        device_type = "serial";
+                        compatible = "ns16550";
+                        reg = <0x4600 0x100>;   // reg base, size
+                        clock-frequency = <0>;  // should we fill in in uboot?
+                        interrupts = <42 2>;
+                        interrupt-parent = <&mpic>;
+                };
+
+                crypto@30000 {
+                        compatible = "fsl,sec2.0";
+                        reg = <0x30000 0x10000>;
+                        interrupts = <45 2>;
+                        interrupt-parent = <&mpic>;
+                        fsl,num-channels = <4>;
+                        fsl,channel-fifo-len = <24>;
+                        fsl,exec-units-mask = <0x7e>;
+                        fsl,descriptor-types-mask = <0x01010ebf>;
+                };
+
+                mpic: pic@40000 {
+                        interrupt-controller;
+                        #address-cells = <0>;
+                        #interrupt-cells = <2>;
+                        reg = <0x40000 0x40000>;
+                        compatible = "chrp,open-pic";
+                        device_type = "open-pic";
+                };
+
+                cpm@919c0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "fsl,mpc8555-cpm", "fsl,cpm2";
+                        reg = <0x919c0 0x30>;
+                        ranges;
+
+                        muram@80000 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                ranges = <0x0 0x80000 0x10000>;
+
+                                data@0 {
+                                        compatible = "fsl,cpm-muram-data";
+                                        reg = <0x0 0x2000 0x9000 0x1000>;
+                                };
+                        };
+
+                        brg@919f0 {
+                                compatible = "fsl,mpc8555-brg",
+                                             "fsl,cpm2-brg",
+                                             "fsl,cpm-brg";
+                                reg = <0x919f0 0x10 0x915f0 0x10>;
+                        };
+
+                        cpmpic: pic@90c00 {
+                                interrupt-controller;
+                                #address-cells = <0>;
+                                #interrupt-cells = <2>;
+                                interrupts = <46 2>;
+                                interrupt-parent = <&mpic>;
+                                reg = <0x90c00 0x80>;
+                                compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic";
+                        };
+                };
+        };
+
+        pci0: pci@e0008000 {
+                interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
+                interrupt-map = <
+
+                        /* IDSEL 0x10 */
+                        0x8000 0x0 0x0 0x1 &mpic 0x0 0x1
+                        0x8000 0x0 0x0 0x2 &mpic 0x1 0x1
+                        0x8000 0x0 0x0 0x3 &mpic 0x2 0x1
+                        0x8000 0x0 0x0 0x4 &mpic 0x3 0x1
+
+                        /* IDSEL 0x11 */
+                        0x8800 0x0 0x0 0x1 &mpic 0x0 0x1
+                        0x8800 0x0 0x0 0x2 &mpic 0x1 0x1
+                        0x8800 0x0 0x0 0x3 &mpic 0x2 0x1
+                        0x8800 0x0 0x0 0x4 &mpic 0x3 0x1
+
+                        /* IDSEL 0x12 (Slot 1) */
+                        0x9000 0x0 0x0 0x1 &mpic 0x0 0x1
+                        0x9000 0x0 0x0 0x2 &mpic 0x1 0x1
+                        0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
+                        0x9000 0x0 0x0 0x4 &mpic 0x3 0x1
+
+                        /* IDSEL 0x13 (Slot 2) */
+                        0x9800 0x0 0x0 0x1 &mpic 0x1 0x1
+                        0x9800 0x0 0x0 0x2 &mpic 0x2 0x1
+                        0x9800 0x0 0x0 0x3 &mpic 0x3 0x1
+                        0x9800 0x0 0x0 0x4 &mpic 0x0 0x1
+
+                        /* IDSEL 0x14 (Slot 3) */
+                        0xa000 0x0 0x0 0x1 &mpic 0x2 0x1
+                        0xa000 0x0 0x0 0x2 &mpic 0x3 0x1
+                        0xa000 0x0 0x0 0x3 &mpic 0x0 0x1
+                        0xa000 0x0 0x0 0x4 &mpic 0x1 0x1
+
+                        /* IDSEL 0x15 (Slot 4) */
+                        0xa800 0x0 0x0 0x1 &mpic 0x3 0x1
+                        0xa800 0x0 0x0 0x2 &mpic 0x0 0x1
+                        0xa800 0x0 0x0 0x3 &mpic 0x1 0x1
+                        0xa800 0x0 0x0 0x4 &mpic 0x2 0x1
+
+                        /* Bus 1 (Tundra Bridge) */
+                        /* IDSEL 0x12 (ISA bridge) */
+                        0x19000 0x0 0x0 0x1 &mpic 0x0 0x1
+                        0x19000 0x0 0x0 0x2 &mpic 0x1 0x1
+                        0x19000 0x0 0x0 0x3 &mpic 0x2 0x1
+                        0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>;
+                interrupt-parent = <&mpic>;
+                interrupts = <24 2>;
+                bus-range = <0 0>;
+                ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
+                          0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
+                clock-frequency = <66666666>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                reg = <0xe0008000 0x1000>;
+                compatible = "fsl,mpc8540-pci";
+                device_type = "pci";
+
+                i8259@19000 {
+                        interrupt-controller;
+                        device_type = "interrupt-controller";
+                        reg = <0x19000 0x0 0x0 0x0 0x1>;
+                        #address-cells = <0>;
+                        #interrupt-cells = <2>;
+                        compatible = "chrp,iic";
+                        interrupts = <1>;
+                        interrupt-parent = <&pci0>;
+                };
+        };
+
+        pci1: pci@e0009000 {
+                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+                interrupt-map = <
+
+                        /* IDSEL 0x15 */
+                        0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
+                        0xa800 0x0 0x0 0x2 &mpic 0xb 0x1
+                        0xa800 0x0 0x0 0x3 &mpic 0xb 0x1
+                        0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>;
+                interrupt-parent = <&mpic>;
+                interrupts = <25 2>;
+                bus-range = <0 0>;
+                ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
+                          0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
+                clock-frequency = <66666666>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                reg = <0xe0009000 0x1000>;
+                compatible = "fsl,mpc8540-pci";
+                device_type = "pci";
+        };
+};
diff --git a/arch/powerpc/boot/dts/tqm8540.dts b/arch/powerpc/boot/dts/tqm8540.dts
index 71347537b83e..15ca731bc24e 100644
--- a/arch/powerpc/boot/dts/tqm8540.dts
+++ b/arch/powerpc/boot/dts/tqm8540.dts
@@ -289,7 +289,14 @@
                 interrupt-map = <
                                 /* IDSEL 28 */
                                  0xe000 0 0 1 &mpic 2 1
-                                 0xe000 0 0 2 &mpic 3 1>;
+                                 0xe000 0 0 2 &mpic 3 1
+                                 0xe000 0 0 3 &mpic 6 1
+                                 0xe000 0 0 4 &mpic 5 1
+
+                                /* IDSEL 11 */
+                                 0x5800 0 0 1 &mpic 6 1
+                                 0x5800 0 0 2 &mpic 5 1
+                                 >;
 
                 interrupt-parent = <&mpic>;
                 interrupts = <24 2>;
diff --git a/arch/powerpc/boot/dts/tqm8541.dts b/arch/powerpc/boot/dts/tqm8541.dts
index b30f63753d41..f49d09181312 100644
--- a/arch/powerpc/boot/dts/tqm8541.dts
+++ b/arch/powerpc/boot/dts/tqm8541.dts
@@ -311,7 +311,14 @@
                 interrupt-map = <
                                 /* IDSEL 28 */
                                  0xe000 0 0 1 &mpic 2 1
-                                 0xe000 0 0 2 &mpic 3 1>;
+                                 0xe000 0 0 2 &mpic 3 1
+                                 0xe000 0 0 3 &mpic 6 1
+                                 0xe000 0 0 4 &mpic 5 1
+
+                                /* IDSEL 11 */
+                                 0x5800 0 0 1 &mpic 6 1
+                                 0x5800 0 0 2 &mpic 5 1
+                                 >;
 
                 interrupt-parent = <&mpic>;
                 interrupts = <24 2>;
diff --git a/arch/powerpc/boot/dts/tqm8548-bigflash.dts b/arch/powerpc/boot/dts/tqm8548-bigflash.dts
index 61f25e15fd66..5dbb36edb038 100644
--- a/arch/powerpc/boot/dts/tqm8548-bigflash.dts
+++ b/arch/powerpc/boot/dts/tqm8548-bigflash.dts
@@ -442,7 +442,14 @@
                 interrupt-map = <
                                 /* IDSEL 28 */
                                  0xe000 0 0 1 &mpic 2 1
-                                 0xe000 0 0 2 &mpic 3 1>;
+                                 0xe000 0 0 2 &mpic 3 1
+                                 0xe000 0 0 3 &mpic 6 1
+                                 0xe000 0 0 4 &mpic 5 1
+
+                                /* IDSEL 11 */
+                                 0x5800 0 0 1 &mpic 6 1
+                                 0x5800 0 0 2 &mpic 5 1
+                                 >;
 
                 interrupt-parent = <&mpic>;
                 interrupts = <24 2>;
diff --git a/arch/powerpc/boot/dts/tqm8548.dts b/arch/powerpc/boot/dts/tqm8548.dts
index 025759c7c955..a050ae427108 100644
--- a/arch/powerpc/boot/dts/tqm8548.dts
+++ b/arch/powerpc/boot/dts/tqm8548.dts
@@ -442,7 +442,14 @@
                 interrupt-map = <
                                 /* IDSEL 28 */
                                  0xe000 0 0 1 &mpic 2 1
-                                 0xe000 0 0 2 &mpic 3 1>;
+                                 0xe000 0 0 2 &mpic 3 1
+                                 0xe000 0 0 3 &mpic 6 1
+                                 0xe000 0 0 4 &mpic 5 1
+
+                                /* IDSEL 11 */
+                                 0x5800 0 0 1 &mpic 6 1
+                                 0x5800 0 0 2 &mpic 5 1
+                                 >;
 
                 interrupt-parent = <&mpic>;
                 interrupts = <24 2>;
diff --git a/arch/powerpc/boot/dts/tqm8555.dts b/arch/powerpc/boot/dts/tqm8555.dts
index 95e287381836..81bad8cd3756 100644
--- a/arch/powerpc/boot/dts/tqm8555.dts
+++ b/arch/powerpc/boot/dts/tqm8555.dts
@@ -311,7 +311,14 @@
                 interrupt-map = <
                                 /* IDSEL 28 */
                                  0xe000 0 0 1 &mpic 2 1
-                                 0xe000 0 0 2 &mpic 3 1>;
+                                 0xe000 0 0 2 &mpic 3 1
+                                 0xe000 0 0 3 &mpic 6 1
+                                 0xe000 0 0 4 &mpic 5 1
+
+                                /* IDSEL 11 */
+                                 0x5800 0 0 1 &mpic 6 1
+                                 0x5800 0 0 2 &mpic 5 1
+                                 >;
 
                 interrupt-parent = <&mpic>;
                 interrupts = <24 2>;
diff --git a/arch/powerpc/boot/dts/tqm8560.dts b/arch/powerpc/boot/dts/tqm8560.dts
index ff70580a8f4c..22ec39b5beeb 100644
--- a/arch/powerpc/boot/dts/tqm8560.dts
+++ b/arch/powerpc/boot/dts/tqm8560.dts
@@ -382,7 +382,14 @@
                 interrupt-map = <
                                 /* IDSEL 28 */
                                  0xe000 0 0 1 &mpic 2 1
-                                 0xe000 0 0 2 &mpic 3 1>;
+                                 0xe000 0 0 2 &mpic 3 1
+                                 0xe000 0 0 3 &mpic 6 1
+                                 0xe000 0 0 4 &mpic 5 1
+
+                                /* IDSEL 11 */
+                                 0x5800 0 0 1 &mpic 6 1
+                                 0x5800 0 0 2 &mpic 5 1
+                                 >;
 
                 interrupt-parent = <&mpic>;
                 interrupts = <24 2>;
diff --git a/arch/powerpc/boot/dts/tqm8xx.dts b/arch/powerpc/boot/dts/tqm8xx.dts
new file mode 100644
index 000000000000..f6da7ec49a8e
--- /dev/null
+++ b/arch/powerpc/boot/dts/tqm8xx.dts
@@ -0,0 +1,172 @@
+/*
+ * TQM8XX Device Tree Source
+ *
+ * Heiko Schocher <hs@denx.de>
+ * 2010 DENX Software Engineering GmbH
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+
+/ {
+        model = "TQM8xx";
+        compatible = "tqc,tqm8xx";
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        aliases {
+                ethernet0 = &eth0;
+                ethernet1 = &eth1;
+                mdio1 = &phy1;
+                serial0 = &smc1;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                PowerPC,860@0 {
+                        device_type = "cpu";
+                        reg = <0x0>;
+                        d-cache-line-size = <16>;       // 16 bytes
+                        i-cache-line-size = <16>;       // 16 bytes
+                        d-cache-size = <0x1000>;                // L1, 4K
+                        i-cache-size = <0x1000>;                // L1, 4K
+                        timebase-frequency = <0>;
+                        bus-frequency = <0>;
+                        clock-frequency = <0>;
+                        interrupts = <15 2>;    // decrementer interrupt
+                        interrupt-parent = <&PIC>;
+                };
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x0 0x2000000>;
+        };
+
+        localbus@fff00100 {
+                compatible = "fsl,mpc860-localbus", "fsl,pq1-localbus";
+                #address-cells = <2>;
+                #size-cells = <1>;
+                reg = <0xfff00100 0x40>;
+
+                ranges = <
+                        0x0 0x0 0x40000000 0x800000
+                >;
+
+                flash@0,0 {
+                        compatible = "cfi-flash";
+                        reg = <0 0 0x800000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        bank-width = <4>;
+                        device-width = <2>;
+                };
+        };
+
+        soc@fff00000 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                device_type = "soc";
+                ranges = <0x0 0xfff00000 0x00004000>;
+
+                phy1: mdio@e00 {
+                        compatible = "fsl,mpc866-fec-mdio", "fsl,pq1-fec-mdio";
+                        reg = <0xe00 0x188>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        PHY: ethernet-phy@f {
+                                reg = <0xf>;
+                                device_type = "ethernet-phy";
+                        };
+                };
+
+                eth1: ethernet@e00 {
+                        device_type = "network";
+                        compatible = "fsl,mpc866-fec-enet",
+                                     "fsl,pq1-fec-enet";
+                        reg = <0xe00 0x188>;
+                        interrupts = <3 1>;
+                        interrupt-parent = <&PIC>;
+                        phy-handle = <&PHY>;
+                        linux,network-index = <1>;
+                };
+
+                PIC: pic@0 {
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        reg = <0x0 0x24>;
+                        compatible = "fsl,mpc860-pic", "fsl,pq1-pic";
+                };
+
+                cpm@9c0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "fsl,mpc860-cpm", "fsl,cpm1";
+                        ranges;
+                        reg = <0x9c0 0x40>;
+                        brg-frequency = <0>;
+                        interrupts = <0 2>;     // cpm error interrupt
+                        interrupt-parent = <&CPM_PIC>;
+
+                        muram@2000 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                ranges = <0x0 0x2000 0x2000>;
+
+                                data@0 {
+                                        compatible = "fsl,cpm-muram-data";
+                                        reg = <0x0 0x2000>;
+                                };
+                        };
+
+                        brg@9f0 {
+                                compatible = "fsl,mpc860-brg",
+                                             "fsl,cpm1-brg",
+                                             "fsl,cpm-brg";
+                                reg = <0x9f0 0x10>;
+                                clock-frequency = <0>;
+                        };
+
+                        CPM_PIC: pic@930 {
+                                interrupt-controller;
+                                #address-cells = <0>;
+                                #interrupt-cells = <1>;
+                                interrupts = <5 2 0 2>;
+                                interrupt-parent = <&PIC>;
+                                reg = <0x930 0x20>;
+                                compatible = "fsl,mpc860-cpm-pic",
+                                             "fsl,cpm1-pic";
+                        };
+
+
+                        smc1: serial@a80 {
+                                device_type = "serial";
+                                compatible = "fsl,mpc860-smc-uart",
+                                             "fsl,cpm1-smc-uart";
+                                reg = <0xa80 0x10 0x3e80 0x40>;
+                                interrupts = <4>;
+                                interrupt-parent = <&CPM_PIC>;
+                                fsl,cpm-brg = <1>;
+                                fsl,cpm-command = <0x90>;
+                        };
+
+                        eth0: ethernet@a00 {
+                                device_type = "network";
+                                compatible = "fsl,mpc860-scc-enet",
+                                             "fsl,cpm1-scc-enet";
+                                reg = <0xa00 0x18 0x3c00 0x100>;
+                                interrupts = <30>;
+                                interrupt-parent = <&CPM_PIC>;
+                                fsl,cpm-command = <0000>;
+                                linux,network-index = <0>;
+                                fixed-link = <0 0 10 0 0>;
+                        };
+                };
+        };
+};
diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig
index cfebef9f9123..d32f31a03f58 100644
--- a/arch/powerpc/configs/mpc85xx_defconfig
+++ b/arch/powerpc/configs/mpc85xx_defconfig
@@ -19,7 +19,8 @@ CONFIG_E500=y
 CONFIG_FSL_EMB_PERFMON=y
 CONFIG_BOOKE=y
 CONFIG_FSL_BOOKE=y
-# CONFIG_PHYS_64BIT is not set
+CONFIG_PTE_64BIT=y
+CONFIG_PHYS_64BIT=y
 CONFIG_SPE=y
 CONFIG_PPC_MMU_NOHASH=y
 CONFIG_PPC_MMU_NOHASH_32=y
@@ -28,7 +29,7 @@ CONFIG_PPC_BOOK3E_MMU=y
 # CONFIG_SMP is not set
 CONFIG_PPC32=y
 CONFIG_WORD_SIZE=32
-# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
+CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
 CONFIG_MMU=y
 CONFIG_GENERIC_CMOS_UPDATE=y
 CONFIG_GENERIC_TIME=y
@@ -239,6 +240,7 @@ CONFIG_MPC85xx_MDS=y
 CONFIG_MPC8536_DS=y
 CONFIG_MPC85xx_DS=y
 CONFIG_MPC85xx_RDB=y
+CONFIG_P1022_DS=y
 CONFIG_SOCRATES=y
 CONFIG_KSI8560=y
 CONFIG_XES_MPC85xx=y
@@ -311,7 +313,7 @@ CONFIG_FLAT_NODE_MEM_MAP=y
 CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
 CONFIG_MIGRATION=y
-# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_PHYS_ADDR_T_64BIT=y
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_BOUNCE=y
 CONFIG_VIRT_TO_BUS=y
@@ -321,7 +323,7 @@ CONFIG_PPC_4K_PAGES=y
 # CONFIG_PPC_16K_PAGES is not set
 # CONFIG_PPC_64K_PAGES is not set
 # CONFIG_PPC_256K_PAGES is not set
-CONFIG_FORCE_MAX_ZONEORDER=11
+CONFIG_FORCE_MAX_ZONEORDER=12
 CONFIG_PROC_DEVICETREE=y
 # CONFIG_CMDLINE_BOOL is not set
 CONFIG_EXTRA_TARGETS=""
@@ -1122,16 +1124,13 @@ CONFIG_VGA_CONSOLE=y
 # CONFIG_VGACON_SOFT_SCROLLBACK is not set
 CONFIG_DUMMY_CONSOLE=y
 CONFIG_SOUND=y
-CONFIG_SOUND_OSS_CORE=y
-CONFIG_SOUND_OSS_CORE_PRECLAIM=y
+# CONFIG_SOUND_OSS_CORE is not set
 CONFIG_SND=y
 CONFIG_SND_TIMER=y
 CONFIG_SND_PCM=y
 # CONFIG_SND_SEQUENCER is not set
-CONFIG_SND_OSSEMUL=y
-CONFIG_SND_MIXER_OSS=y
-CONFIG_SND_PCM_OSS=y
-CONFIG_SND_PCM_OSS_PLUGINS=y
+# CONFIG_SND_MIXER_OSS is not set
+# CONFIG_SND_PCM_OSS is not set
 # CONFIG_SND_HRTIMER is not set
 # CONFIG_SND_DYNAMIC_MINORS is not set
 # CONFIG_SND_SUPPORT_OLD_API is not set
@@ -1145,12 +1144,7 @@ CONFIG_SND_VMASTER=y
 # CONFIG_SND_SBAWE_SEQ is not set
 # CONFIG_SND_EMU10K1_SEQ is not set
 CONFIG_SND_AC97_CODEC=y
-CONFIG_SND_DRIVERS=y
-# CONFIG_SND_DUMMY is not set
-# CONFIG_SND_MTPAV is not set
-# CONFIG_SND_SERIAL_U16550 is not set
-# CONFIG_SND_MPU401 is not set
-# CONFIG_SND_AC97_POWER_SAVE is not set
+# CONFIG_SND_DRIVERS is not set
 CONFIG_SND_PCI=y
 # CONFIG_SND_AD1889 is not set
 # CONFIG_SND_ALS300 is not set
@@ -1218,12 +1212,8 @@ CONFIG_SND_INTEL8X0=y
 # CONFIG_SND_VIRTUOSO is not set
 # CONFIG_SND_VX222 is not set
 # CONFIG_SND_YMFPCI is not set
-CONFIG_SND_PPC=y
-CONFIG_SND_USB=y
-# CONFIG_SND_USB_AUDIO is not set
-# CONFIG_SND_USB_UA101 is not set
-# CONFIG_SND_USB_USX2Y is not set
-# CONFIG_SND_USB_CAIAQ is not set
+# CONFIG_SND_PPC is not set
+# CONFIG_SND_USB is not set
 # CONFIG_SND_SOC is not set
 # CONFIG_SOUND_PRIME is not set
 CONFIG_AC97_BUS=y
diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig b/arch/powerpc/configs/mpc85xx_smp_defconfig
index f5451d80f19b..f93de10adcda 100644
--- a/arch/powerpc/configs/mpc85xx_smp_defconfig
+++ b/arch/powerpc/configs/mpc85xx_smp_defconfig
@@ -19,7 +19,8 @@ CONFIG_E500=y
 CONFIG_FSL_EMB_PERFMON=y
 CONFIG_BOOKE=y
 CONFIG_FSL_BOOKE=y
-# CONFIG_PHYS_64BIT is not set
+CONFIG_PTE_64BIT=y
+CONFIG_PHYS_64BIT=y
 CONFIG_SPE=y
 CONFIG_PPC_MMU_NOHASH=y
 CONFIG_PPC_MMU_NOHASH_32=y
@@ -29,7 +30,7 @@ CONFIG_SMP=y
 CONFIG_NR_CPUS=8
 CONFIG_PPC32=y
 CONFIG_WORD_SIZE=32
-# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
+CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
 CONFIG_MMU=y
 CONFIG_GENERIC_CMOS_UPDATE=y
 CONFIG_GENERIC_TIME=y
@@ -243,6 +244,7 @@ CONFIG_MPC85xx_MDS=y
 CONFIG_MPC8536_DS=y
 CONFIG_MPC85xx_DS=y
 CONFIG_MPC85xx_RDB=y
+CONFIG_P1022_DS=y
 CONFIG_SOCRATES=y
 CONFIG_KSI8560=y
 CONFIG_XES_MPC85xx=y
@@ -316,7 +318,7 @@ CONFIG_FLAT_NODE_MEM_MAP=y
 CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
 CONFIG_MIGRATION=y
-# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_PHYS_ADDR_T_64BIT=y
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_BOUNCE=y
 CONFIG_VIRT_TO_BUS=y
@@ -326,7 +328,7 @@ CONFIG_PPC_4K_PAGES=y
 # CONFIG_PPC_16K_PAGES is not set
 # CONFIG_PPC_64K_PAGES is not set
 # CONFIG_PPC_256K_PAGES is not set
-CONFIG_FORCE_MAX_ZONEORDER=11
+CONFIG_FORCE_MAX_ZONEORDER=12
 CONFIG_PROC_DEVICETREE=y
 # CONFIG_CMDLINE_BOOL is not set
 CONFIG_EXTRA_TARGETS=""
@@ -1127,16 +1129,13 @@ CONFIG_VGA_CONSOLE=y
 # CONFIG_VGACON_SOFT_SCROLLBACK is not set
 CONFIG_DUMMY_CONSOLE=y
 CONFIG_SOUND=y
-CONFIG_SOUND_OSS_CORE=y
-CONFIG_SOUND_OSS_CORE_PRECLAIM=y
+# CONFIG_SOUND_OSS_CORE is not set
 CONFIG_SND=y
 CONFIG_SND_TIMER=y
 CONFIG_SND_PCM=y
 # CONFIG_SND_SEQUENCER is not set
-CONFIG_SND_OSSEMUL=y
-CONFIG_SND_MIXER_OSS=y
-CONFIG_SND_PCM_OSS=y
-CONFIG_SND_PCM_OSS_PLUGINS=y
+# CONFIG_SND_MIXER_OSS is not set
+# CONFIG_SND_PCM_OSS is not set
 # CONFIG_SND_HRTIMER is not set
 # CONFIG_SND_DYNAMIC_MINORS is not set
 # CONFIG_SND_SUPPORT_OLD_API is not set
@@ -1150,12 +1149,7 @@ CONFIG_SND_VMASTER=y
 # CONFIG_SND_SBAWE_SEQ is not set
 # CONFIG_SND_EMU10K1_SEQ is not set
 CONFIG_SND_AC97_CODEC=y
-CONFIG_SND_DRIVERS=y
-# CONFIG_SND_DUMMY is not set
-# CONFIG_SND_MTPAV is not set
-# CONFIG_SND_SERIAL_U16550 is not set
-# CONFIG_SND_MPU401 is not set
-# CONFIG_SND_AC97_POWER_SAVE is not set
+# CONFIG_SND_DRIVERS is not set
 CONFIG_SND_PCI=y
 # CONFIG_SND_AD1889 is not set
 # CONFIG_SND_ALS300 is not set
@@ -1223,12 +1217,8 @@ CONFIG_SND_INTEL8X0=y
 # CONFIG_SND_VIRTUOSO is not set
 # CONFIG_SND_VX222 is not set
 # CONFIG_SND_YMFPCI is not set
-CONFIG_SND_PPC=y
-CONFIG_SND_USB=y
-# CONFIG_SND_USB_AUDIO is not set
-# CONFIG_SND_USB_UA101 is not set
-# CONFIG_SND_USB_USX2Y is not set
-# CONFIG_SND_USB_CAIAQ is not set
+# CONFIG_SND_PPC is not set
+# CONFIG_SND_USB is not set
 # CONFIG_SND_SOC is not set
 # CONFIG_SOUND_PRIME is not set
 CONFIG_AC97_BUS=y
diff --git a/arch/powerpc/configs/tqm8xx_defconfig b/arch/powerpc/configs/tqm8xx_defconfig
new file mode 100644
index 000000000000..85e654b64874
--- /dev/null
+++ b/arch/powerpc/configs/tqm8xx_defconfig
@@ -0,0 +1,934 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.34-rc1
+# Tue Mar 23 08:22:15 2010
+#
+# CONFIG_PPC64 is not set
+
+#
+# Processor support
+#
+# CONFIG_PPC_BOOK3S_32 is not set
+# CONFIG_PPC_85xx is not set
+CONFIG_PPC_8xx=y
+# CONFIG_40x is not set
+# CONFIG_44x is not set
+# CONFIG_E200 is not set
+CONFIG_8xx=y
+CONFIG_PPC_MMU_NOHASH=y
+CONFIG_PPC_MMU_NOHASH_32=y
+# CONFIG_PPC_MM_SLICES is not set
+CONFIG_NOT_COHERENT_CACHE=y
+CONFIG_PPC32=y
+CONFIG_WORD_SIZE=32
+# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
+CONFIG_MMU=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
+# CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK is not set
+CONFIG_IRQ_PER_CPU=y
+CONFIG_NR_IRQS=512
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_ARCH_HAS_ILOG2_U32=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+# CONFIG_ARCH_NO_VIRT_TO_BUS is not set
+CONFIG_PPC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_GENERIC_NVRAM=y
+CONFIG_SCHED_OMIT_FRAME_POINTER=y
+CONFIG_ARCH_MAY_HAVE_PC_FDC=y
+CONFIG_PPC_OF=y
+CONFIG_OF=y
+# CONFIG_PPC_UDBG_16550 is not set
+# CONFIG_GENERIC_TBSYNC is not set
+CONFIG_AUDIT_ARCH=y
+CONFIG_GENERIC_BUG=y
+CONFIG_DTC=y
+# CONFIG_DEFAULT_UIMAGE is not set
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+# CONFIG_PPC_DCR_NATIVE is not set
+# CONFIG_PPC_DCR_MMIO is not set
+CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_TINY_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EMBEDDED=y
+# CONFIG_SYSCTL_SYSCALL is not set
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+# CONFIG_ELF_CORE is not set
+# CONFIG_BASE_FULL is not set
+# CONFIG_FUTEX is not set
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_HAVE_PERF_EVENTS=y
+
+#
+# Kernel Performance Events And Counters
+#
+# CONFIG_PERF_EVENTS is not set
+# CONFIG_PERF_COUNTERS is not set
+# CONFIG_VM_EVENT_COUNTERS is not set
+CONFIG_SLUB_DEBUG=y
+CONFIG_COMPAT_BRK=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
+CONFIG_HAVE_IOREMAP_PROT=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+CONFIG_HAVE_DMA_ATTRS=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_SLOW_WORK is not set
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
+CONFIG_SLABINFO=y
+CONFIG_BASE_SMALL=1
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_DEADLINE=y
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_DEFAULT_DEADLINE=y
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="deadline"
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+CONFIG_INLINE_SPIN_UNLOCK=y
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+CONFIG_INLINE_READ_UNLOCK=y
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+CONFIG_INLINE_READ_UNLOCK_IRQ=y
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+CONFIG_INLINE_WRITE_UNLOCK=y
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+# CONFIG_MUTEX_SPIN_ON_OWNER is not set
+# CONFIG_FREEZER is not set
+
+#
+# Platform support
+#
+# CONFIG_PPC_CELL is not set
+# CONFIG_PPC_CELL_NATIVE is not set
+CONFIG_CPM1=y
+# CONFIG_MPC8XXFADS is not set
+# CONFIG_MPC86XADS is not set
+# CONFIG_MPC885ADS is not set
+# CONFIG_PPC_EP88XC is not set
+# CONFIG_PPC_ADDER875 is not set
+# CONFIG_PPC_MGSUVD is not set
+CONFIG_TQM8XX=y
+
+#
+# MPC8xx CPM Options
+#
+
+#
+# Generic MPC8xx Options
+#
+CONFIG_8xx_COPYBACK=y
+# CONFIG_8xx_GPIO is not set
+# CONFIG_8xx_CPU6 is not set
+# CONFIG_8xx_CPU15 is not set
+CONFIG_NO_UCODE_PATCH=y
+# CONFIG_USB_SOF_UCODE_PATCH is not set
+# CONFIG_I2C_SPI_UCODE_PATCH is not set
+# CONFIG_I2C_SPI_SMC1_UCODE_PATCH is not set
+# CONFIG_PQ2ADS is not set
+# CONFIG_IPIC is not set
+# CONFIG_MPIC is not set
+# CONFIG_MPIC_WEIRD is not set
+# CONFIG_PPC_I8259 is not set
+# CONFIG_PPC_RTAS is not set
+# CONFIG_MMIO_NVRAM is not set
+# CONFIG_PPC_MPC106 is not set
+# CONFIG_PPC_970_NAP is not set
+# CONFIG_PPC_INDIRECT_IO is not set
+# CONFIG_GENERIC_IOMAP is not set
+# CONFIG_CPU_FREQ is not set
+# CONFIG_QUICC_ENGINE is not set
+# CONFIG_FSL_ULI1575 is not set
+CONFIG_CPM=y
+# CONFIG_SIMPLE_GPIO is not set
+
+#
+# Kernel options
+#
+# CONFIG_HIGHMEM is not set
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_HZ_100=y
+# CONFIG_HZ_250 is not set
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=100
+CONFIG_SCHED_HRTICK=y
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_HAVE_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_MATH_EMULATION is not set
+CONFIG_8XX_MINIMAL_FPEMU=y
+# CONFIG_IOMMU_HELPER is not set
+# CONFIG_SWIOTLB is not set
+CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
+CONFIG_ARCH_HAS_WALK_MEMORY=y
+CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_MAX_ACTIVE_REGIONS=32
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_MIGRATION=y
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_PPC_4K_PAGES=y
+# CONFIG_PPC_16K_PAGES is not set
+# CONFIG_PPC_64K_PAGES is not set
+# CONFIG_PPC_256K_PAGES is not set
+CONFIG_FORCE_MAX_ZONEORDER=11
+CONFIG_PROC_DEVICETREE=y
+# CONFIG_CMDLINE_BOOL is not set
+CONFIG_EXTRA_TARGETS=""
+# CONFIG_PM is not set
+# CONFIG_SECCOMP is not set
+CONFIG_ISA_DMA_API=y
+
+#
+# Bus options
+#
+CONFIG_ZONE_DMA=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_FSL_SOC=y
+# CONFIG_PCI is not set
+# CONFIG_PCI_DOMAINS is not set
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_PCI_QSPAN is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+# CONFIG_HAS_RAPIDIO is not set
+
+#
+# Advanced setup
+#
+# CONFIG_ADVANCED_OPTIONS is not set
+
+#
+# Default settings for advanced configuration options are used
+#
+CONFIG_LOWMEM_SIZE=0x30000000
+CONFIG_PAGE_OFFSET=0xc0000000
+CONFIG_KERNEL_START=0xc0000000
+CONFIG_PHYSICAL_START=0x00000000
+CONFIG_TASK_SIZE=0x80000000
+CONFIG_CONSISTENT_SIZE=0x00200000
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_OF_PARTS=y
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+CONFIG_MTD_PHYSMAP_OF=y
+# CONFIG_MTD_CFI_FLAGADM is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_DYNAMIC=y
+CONFIG_OF_DEVICE=y
+CONFIG_OF_MDIO=y
+# CONFIG_PARPORT is not set
+# CONFIG_BLK_DEV is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_MACINTOSH_DRIVERS is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+CONFIG_DAVICOM_PHY=y
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+CONFIG_FIXED_PHY=y
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_ETHOC is not set
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_KS8851_MLL is not set
+# CONFIG_XILINX_EMACLITE is not set
+CONFIG_FS_ENET=y
+CONFIG_FS_ENET_HAS_SCC=y
+CONFIG_FS_ENET_HAS_FEC=y
+CONFIG_FS_ENET_MDIO_FEC=y
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_WLAN is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+# CONFIG_INPUT is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_UARTLITE is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_SERIAL_CPM=y
+CONFIG_SERIAL_CPM_CONSOLE=y
+# CONFIG_SERIAL_TIMBERDALE is not set
+# CONFIG_SERIAL_GRLIB_GAISLER_APBUART is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_HVC_UDBG is not set
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_HW_RANDOM_TIMERIOMEM is not set
+# CONFIG_NVRAM is not set
+CONFIG_GEN_RTC=y
+# CONFIG_GEN_RTC_X is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
+# CONFIG_GPIOLIB is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+# CONFIG_SOUND is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_EDAC is not set
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+
+#
+# TI VLYNQ
+#
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY is not set
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+# CONFIG_PROC_KCORE is not set
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_LOGFS is not set
+CONFIG_CRAMFS=y
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+# CONFIG_NLS is not set
+# CONFIG_DLM is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+# CONFIG_CRC32 is not set
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_HAVE_LMB=y
+CONFIG_NLATTR=y
+CONFIG_GENERIC_ATOMIC64=y
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_KMEMLEAK is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_DEBUG_PAGEALLOC is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_TRACING_SUPPORT=y
+CONFIG_FTRACE=y
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
+# CONFIG_BOOT_TRACER is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_DMA_API_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_PPC_DISABLE_WERROR is not set
+CONFIG_PPC_WERROR=y
+CONFIG_PRINT_STACK_DEPTH=64
+# CONFIG_DEBUG_STACKOVERFLOW is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_CODE_PATCHING_SELFTEST is not set
+# CONFIG_FTR_FIXUP_SELFTEST is not set
+# CONFIG_MSI_BITMAP_SELFTEST is not set
+# CONFIG_XMON is not set
+# CONFIG_IRQSTACKS is not set
+# CONFIG_BDI_SWITCH is not set
+# CONFIG_PPC_EARLY_DEBUG is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_DEFAULT_SECURITY_SELINUX is not set
+# CONFIG_DEFAULT_SECURITY_SMACK is not set
+# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
+# CONFIG_CRYPTO is not set
+CONFIG_PPC_CLOCK=y
+CONFIG_PPC_LIB_RHEAP=y
+# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/powerpc/include/asm/abs_addr.h b/arch/powerpc/include/asm/abs_addr.h
index 9a846efe6382..5ab0b71531be 100644
--- a/arch/powerpc/include/asm/abs_addr.h
+++ b/arch/powerpc/include/asm/abs_addr.h
@@ -69,7 +69,7 @@ static inline unsigned long phys_to_abs(unsigned long pa)
  * Legacy iSeries Hypervisor calls
  */
 #define iseries_hv_addr(virtaddr)       \
-        (0x8000000000000000 | virt_to_abs(virtaddr))
+        (0x8000000000000000UL | virt_to_abs(virtaddr))
 
 #endif /* __KERNEL__ */
 #endif /* _ASM_POWERPC_ABS_ADDR_H */
diff --git a/arch/powerpc/include/asm/asm-compat.h b/arch/powerpc/include/asm/asm-compat.h
index 2048a6aeea91..decad950f11a 100644
--- a/arch/powerpc/include/asm/asm-compat.h
+++ b/arch/powerpc/include/asm/asm-compat.h
@@ -30,6 +30,7 @@
 #define PPC_STLCX       stringify_in_c(stdcx.)
 #define PPC_CNTLZL      stringify_in_c(cntlzd)
 #define PPC_LR_STKOFF   16
+#define PPC_MIN_STKFRM  112
 
 /* Move to CR, single-entry optimized version. Only available
  * on POWER4 and later.
@@ -55,6 +56,7 @@
 #define PPC_CNTLZL      stringify_in_c(cntlzw)
 #define PPC_MTOCRF      stringify_in_c(mtcrf)
 #define PPC_LR_STKOFF   4
+#define PPC_MIN_STKFRM  16
 
 #endif
 
diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
index b0b21134f61a..5e2e2cfcc81b 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -517,6 +517,10 @@ static inline int cpu_has_feature(unsigned long feature)
                 & feature);
 }
 
+#ifdef CONFIG_HAVE_HW_BREAKPOINT
+#define HBP_NUM 1
+#endif /* CONFIG_HAVE_HW_BREAKPOINT */
+
 #endif /* !__ASSEMBLY__ */
 
 #endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/dbell.h b/arch/powerpc/include/asm/dbell.h
index 501189a543d1..0893ab9343a6 100644
--- a/arch/powerpc/include/asm/dbell.h
+++ b/arch/powerpc/include/asm/dbell.h
@@ -27,10 +27,10 @@ enum ppc_dbell {
         PPC_G_DBELL_MC = 4,     /* guest mcheck doorbell */
 };
 
-#ifdef CONFIG_SMP
-extern unsigned long dbell_smp_message[NR_CPUS];
-extern void smp_dbell_message_pass(int target, int msg);
-#endif
+extern void doorbell_message_pass(int target, int msg);
+extern void doorbell_exception(struct pt_regs *regs);
+extern void doorbell_check_self(void);
+extern void doorbell_setup_this_cpu(void);
 
 static inline void ppc_msgsnd(enum ppc_dbell type, u32 flags, u32 tag)
 {
diff --git a/arch/powerpc/include/asm/hvcall.h b/arch/powerpc/include/asm/hvcall.h
index 5119b7db3142..de03ca58db5d 100644
--- a/arch/powerpc/include/asm/hvcall.h
+++ b/arch/powerpc/include/asm/hvcall.h
@@ -74,6 +74,7 @@
 #define H_NOT_ENOUGH_RESOURCES -44
 #define H_R_STATE       -45
 #define H_RESCINDEND    -46
+#define H_MULTI_THREADS_ACTIVE -9005
 
 
 /* Long Busy is a condition that can be returned by the firmware
diff --git a/arch/powerpc/include/asm/hw_breakpoint.h b/arch/powerpc/include/asm/hw_breakpoint.h
new file mode 100644
index 000000000000..1c33ec17ca36
--- /dev/null
+++ b/arch/powerpc/include/asm/hw_breakpoint.h
@@ -0,0 +1,74 @@
+/*
+ * PowerPC BookIII S hardware breakpoint definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright 2010, IBM Corporation.
+ * Author: K.Prasad <prasad@linux.vnet.ibm.com>
+ *
+ */
+
+#ifndef _PPC_BOOK3S_64_HW_BREAKPOINT_H
+#define _PPC_BOOK3S_64_HW_BREAKPOINT_H
+
+#ifdef  __KERNEL__
+#ifdef CONFIG_HAVE_HW_BREAKPOINT
+
+struct arch_hw_breakpoint {
+        bool            extraneous_interrupt;
+        u8              len; /* length of the target data symbol */
+        int             type;
+        unsigned long   address;
+};
+
+#include <linux/kdebug.h>
+#include <asm/reg.h>
+#include <asm/system.h>
+
+struct perf_event;
+struct pmu;
+struct perf_sample_data;
+
+#define HW_BREAKPOINT_ALIGN 0x7
+/* Maximum permissible length of any HW Breakpoint */
+#define HW_BREAKPOINT_LEN 0x8
+
+extern int hw_breakpoint_slots(int type);
+extern int arch_bp_generic_fields(int type, int *gen_bp_type);
+extern int arch_check_bp_in_kernelspace(struct perf_event *bp);
+extern int arch_validate_hwbkpt_settings(struct perf_event *bp);
+extern int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
+                                                unsigned long val, void *data);
+int arch_install_hw_breakpoint(struct perf_event *bp);
+void arch_uninstall_hw_breakpoint(struct perf_event *bp);
+void hw_breakpoint_pmu_read(struct perf_event *bp);
+extern void flush_ptrace_hw_breakpoint(struct task_struct *tsk);
+
+extern struct pmu perf_ops_bp;
+extern void ptrace_triggered(struct perf_event *bp, int nmi,
+                        struct perf_sample_data *data, struct pt_regs *regs);
+static inline void hw_breakpoint_disable(void)
+{
+        set_dabr(0);
+}
+extern void thread_change_pc(struct task_struct *tsk, struct pt_regs *regs);
+
+#else   /* CONFIG_HAVE_HW_BREAKPOINT */
+static inline void hw_breakpoint_disable(void) { }
+static inline void thread_change_pc(struct task_struct *tsk,
+                                        struct pt_regs *regs) { }
+#endif  /* CONFIG_HAVE_HW_BREAKPOINT */
+#endif  /* __KERNEL__ */
+#endif  /* _PPC_BOOK3S_64_HW_BREAKPOINT_H */
diff --git a/arch/powerpc/include/asm/machdep.h b/arch/powerpc/include/asm/machdep.h
index 9f0fc9e6ce0d..adc8e6cdf339 100644
--- a/arch/powerpc/include/asm/machdep.h
+++ b/arch/powerpc/include/asm/machdep.h
@@ -266,6 +266,7 @@ struct machdep_calls {
         void (*suspend_disable_irqs)(void);
         void (*suspend_enable_irqs)(void);
 #endif
+        int (*suspend_disable_cpu)(void);
 
 #ifdef CONFIG_ARCH_CPU_PROBE_RELEASE
         ssize_t (*cpu_probe)(const char *, size_t);
@@ -277,6 +278,7 @@ extern void e500_idle(void);
 extern void power4_idle(void);
 extern void power4_cpu_offline_powersave(void);
 extern void ppc6xx_idle(void);
+extern void book3e_idle(void);
 
 /*
  * ppc_md contains a copy of the machine description structure for the
@@ -366,8 +368,5 @@ static inline void log_error(char *buf, unsigned int err_type, int fatal)
 #define machine_late_initcall(mach,fn)          __define_machine_initcall(mach,"7",fn,7)
 #define machine_late_initcall_sync(mach,fn)     __define_machine_initcall(mach,"7s",fn,7s)
 
-void generic_suspend_disable_irqs(void);
-void generic_suspend_enable_irqs(void);
-
 #endif /* __KERNEL__ */
 #endif /* _ASM_POWERPC_MACHDEP_H */
diff --git a/arch/powerpc/include/asm/mmu-book3e.h b/arch/powerpc/include/asm/mmu-book3e.h
index 74695816205c..87a1d787c5b6 100644
--- a/arch/powerpc/include/asm/mmu-book3e.h
+++ b/arch/powerpc/include/asm/mmu-book3e.h
@@ -193,6 +193,10 @@ struct mmu_psize_def
 {
         unsigned int    shift;  /* number of bits */
         unsigned int    enc;    /* PTE encoding */
+        unsigned int    ind;    /* Corresponding indirect page size shift */
+        unsigned int    flags;
+#define MMU_PAGE_SIZE_DIRECT    0x1     /* Supported as a direct size */
+#define MMU_PAGE_SIZE_INDIRECT  0x2     /* Supported as an indirect size */
 };
 extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
 
diff --git a/arch/powerpc/include/asm/mpc5121.h b/arch/powerpc/include/asm/mpc5121.h
index e6a30bb1d16a..8c0ab2ca689c 100644
--- a/arch/powerpc/include/asm/mpc5121.h
+++ b/arch/powerpc/include/asm/mpc5121.h
@@ -21,4 +21,36 @@ struct mpc512x_reset_module {
         u32     rcer;   /* Reset Control Enable Register */
 };
 
+/*
+ * Clock Control Module
+ */
+struct mpc512x_ccm {
+        u32     spmr;   /* System PLL Mode Register */
+        u32     sccr1;  /* System Clock Control Register 1 */
+        u32     sccr2;  /* System Clock Control Register 2 */
+        u32     scfr1;  /* System Clock Frequency Register 1 */
+        u32     scfr2;  /* System Clock Frequency Register 2 */
+        u32     scfr2s; /* System Clock Frequency Shadow Register 2 */
+        u32     bcr;    /* Bread Crumb Register */
+        u32     p0ccr;  /* PSC0 Clock Control Register */
+        u32     p1ccr;  /* PSC1 CCR */
+        u32     p2ccr;  /* PSC2 CCR */
+        u32     p3ccr;  /* PSC3 CCR */
+        u32     p4ccr;  /* PSC4 CCR */
+        u32     p5ccr;  /* PSC5 CCR */
+        u32     p6ccr;  /* PSC6 CCR */
+        u32     p7ccr;  /* PSC7 CCR */
+        u32     p8ccr;  /* PSC8 CCR */
+        u32     p9ccr;  /* PSC9 CCR */
+        u32     p10ccr; /* PSC10 CCR */
+        u32     p11ccr; /* PSC11 CCR */
+        u32     spccr;  /* SPDIF Clock Control Register */
+        u32     cccr;   /* CFM Clock Control Register */
+        u32     dccr;   /* DIU Clock Control Register */
+        u32     m1ccr;  /* MSCAN1 CCR */
+        u32     m2ccr;  /* MSCAN2 CCR */
+        u32     m3ccr;  /* MSCAN3 CCR */
+        u32     m4ccr;  /* MSCAN4 CCR */
+        u8      res[0x98]; /* Reserved */
+};
 #endif /* __ASM_POWERPC_MPC5121_H__ */
diff --git a/arch/powerpc/include/asm/paca.h b/arch/powerpc/include/asm/paca.h
index 8ce7963ad41d..1ff6662f7faf 100644
--- a/arch/powerpc/include/asm/paca.h
+++ b/arch/powerpc/include/asm/paca.h
@@ -146,7 +146,7 @@ struct paca_struct {
 extern struct paca_struct *paca;
 extern __initdata struct paca_struct boot_paca;
 extern void initialise_paca(struct paca_struct *new_paca, int cpu);
-
+extern void setup_paca(struct paca_struct *new_paca);
 extern void allocate_pacas(void);
 extern void free_unused_pacas(void);
 
diff --git a/arch/powerpc/include/asm/percpu.h b/arch/powerpc/include/asm/percpu.h
index f879252b7ea6..2cedefddba37 100644
--- a/arch/powerpc/include/asm/percpu.h
+++ b/arch/powerpc/include/asm/percpu.h
@@ -1,7 +1,6 @@
 #ifndef _ASM_POWERPC_PERCPU_H_
 #define _ASM_POWERPC_PERCPU_H_
 #ifdef __powerpc64__
-#include <linux/compiler.h>
 
 /*
  * Same as asm-generic/percpu.h, except that we store the per cpu offset
@@ -12,9 +11,7 @@
 
 #include <asm/paca.h>
 
-#define __per_cpu_offset(cpu) (paca[cpu].data_offset)
 #define __my_cpu_offset local_paca->data_offset
-#define per_cpu_offset(x) (__per_cpu_offset(x))
 
 #endif /* CONFIG_SMP */
 #endif /* __powerpc64__ */
diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
index d553bbeb726c..43adc8b819ed 100644
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -52,13 +52,17 @@
 #define PPC_INST_WAIT                   0x7c00007c
 #define PPC_INST_TLBIVAX                0x7c000624
 #define PPC_INST_TLBSRX_DOT             0x7c0006a5
+#define PPC_INST_XXLOR                  0xf0000510
 
 /* macros to insert fields into opcodes */
 #define __PPC_RA(a)     (((a) & 0x1f) << 16)
 #define __PPC_RB(b)     (((b) & 0x1f) << 11)
 #define __PPC_RS(s)     (((s) & 0x1f) << 21)
 #define __PPC_RT(s)     __PPC_RS(s)
+#define __PPC_XA(a)     ((((a) & 0x1f) << 16) | (((a) & 0x20) >> 3))
+#define __PPC_XB(b)     ((((b) & 0x1f) << 11) | (((b) & 0x20) >> 4))
 #define __PPC_XS(s)     ((((s) & 0x1f) << 21) | (((s) & 0x20) >> 5))
+#define __PPC_XT(s)     __PPC_XS(s)
 #define __PPC_T_TLB(t)  (((t) & 0x3) << 21)
 #define __PPC_WC(w)     (((w) & 0x3) << 21)
 /*
@@ -106,9 +110,12 @@
  * the 128 bit load store instructions based on that.
  */
 #define VSX_XX1(s, a, b)        (__PPC_XS(s) | __PPC_RA(a) | __PPC_RB(b))
+#define VSX_XX3(t, a, b)        (__PPC_XT(t) | __PPC_XA(a) | __PPC_XB(b))
 #define STXVD2X(s, a, b)        stringify_in_c(.long PPC_INST_STXVD2X | \
                                                VSX_XX1((s), (a), (b)))
 #define LXVD2X(s, a, b)         stringify_in_c(.long PPC_INST_LXVD2X | \
                                                VSX_XX1((s), (a), (b)))
+#define XXLOR(t, a, b)          stringify_in_c(.long PPC_INST_XXLOR | \
+                                               VSX_XX3((t), (a), (b)))
 
 #endif /* _ASM_POWERPC_PPC_OPCODE_H */
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 7492fe8ad6e4..19c05b0f74be 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -209,6 +209,14 @@ struct thread_struct {
 #ifdef CONFIG_PPC64
         unsigned long   start_tb;       /* Start purr when proc switched in */
         unsigned long   accum_tb;       /* Total accumilated purr for process */
+#ifdef CONFIG_HAVE_HW_BREAKPOINT
+        struct perf_event *ptrace_bps[HBP_NUM];
+        /*
+         * Helps identify source of single-step exception and subsequent
+         * hw-breakpoint enablement
+         */
+        struct perf_event *last_hit_ubp;
+#endif /* CONFIG_HAVE_HW_BREAKPOINT */
 #endif
         unsigned long   dabr;           /* Data address breakpoint register */
 #ifdef CONFIG_ALTIVEC
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index d62fdf4e504b..d8be016d2ede 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -890,7 +890,7 @@
 #ifndef __ASSEMBLY__
 #define mfmsr()         ({unsigned long rval; \
                         asm volatile("mfmsr %0" : "=r" (rval)); rval;})
-#ifdef CONFIG_PPC64
+#ifdef CONFIG_PPC_BOOK3S_64
 #define __mtmsrd(v, l)  asm volatile("mtmsrd %0," __stringify(l) \
                                      : : "r" (v) : "memory")
 #define mtmsrd(v)       __mtmsrd((v), 0)
diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h
index 2360317179a9..667a498eaee1 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -29,8 +29,8 @@
 #if defined(CONFIG_PPC_BOOK3E_64)
 #define MSR_            MSR_ME | MSR_CE
 #define MSR_KERNEL      MSR_ | MSR_CM
-#define MSR_USER32      MSR_ | MSR_PR | MSR_EE
-#define MSR_USER64      MSR_USER32 | MSR_CM
+#define MSR_USER32      MSR_ | MSR_PR | MSR_EE | MSR_DE
+#define MSR_USER64      MSR_USER32 | MSR_CM | MSR_DE
 #elif defined (CONFIG_40x)
 #define MSR_KERNEL      (MSR_ME|MSR_RI|MSR_IR|MSR_DR|MSR_CE)
 #define MSR_USER        (MSR_KERNEL|MSR_PR|MSR_EE)
@@ -62,6 +62,7 @@
 #define SPRN_TLB0PS     0x158   /* TLB 0 Page Size Register */
 #define SPRN_MAS5_MAS6  0x15c   /* MMU Assist Register 5 || 6 */
 #define SPRN_MAS8_MAS1  0x15d   /* MMU Assist Register 8 || 1 */
+#define SPRN_EPTCFG     0x15e   /* Embedded Page Table Config */
 #define SPRN_MAS7_MAS3  0x174   /* MMU Assist Register 7 || 3 */
 #define SPRN_MAS0_MAS1  0x175   /* MMU Assist Register 0 || 1 */
 #define SPRN_IVOR0      0x190   /* Interrupt Vector Offset Register 0 */
diff --git a/arch/powerpc/include/asm/rtas.h b/arch/powerpc/include/asm/rtas.h
index 20de73c36682..3d35f8ae377e 100644
--- a/arch/powerpc/include/asm/rtas.h
+++ b/arch/powerpc/include/asm/rtas.h
@@ -63,6 +63,14 @@ struct rtas_t {
         struct device_node *dev;        /* virtual address pointer */
 };
 
+struct rtas_suspend_me_data {
+        atomic_t working; /* number of cpus accessing this struct */
+        atomic_t done;
+        int token; /* ibm,suspend-me */
+        atomic_t error;
+        struct completion *complete; /* wait on this until working == 0 */
+};
+
 /* RTAS event classes */
 #define RTAS_INTERNAL_ERROR             0x80000000 /* set bit 0 */
 #define RTAS_EPOW_WARNING               0x40000000 /* set bit 1 */
@@ -137,6 +145,9 @@ struct rtas_t {
 #define RTAS_TYPE_PMGM_CONFIG_CHANGE    0x70
 #define RTAS_TYPE_PMGM_SERVICE_PROC     0x71
 
+/* RTAS check-exception vector offset */
+#define RTAS_VECTOR_EXTERNAL_INTERRUPT  0x500
+
 struct rtas_error_log {
         unsigned long version:8;                /* Architectural version */
         unsigned long severity:3;               /* Severity level of error */
@@ -174,6 +185,8 @@ extern int rtas_set_indicator(int indicator, int index, int new_value);
 extern int rtas_set_indicator_fast(int indicator, int index, int new_value);
 extern void rtas_progress(char *s, unsigned short hex);
 extern void rtas_initialize(void);
+extern int rtas_suspend_cpu(struct rtas_suspend_me_data *data);
+extern int rtas_suspend_last_cpu(struct rtas_suspend_me_data *data);
 
 struct rtc_time;
 extern unsigned long rtas_get_boot_time(void);
diff --git a/arch/powerpc/include/asm/time.h b/arch/powerpc/include/asm/time.h
index 27ccb764fdab..dc779dfcf258 100644
--- a/arch/powerpc/include/asm/time.h
+++ b/arch/powerpc/include/asm/time.h
@@ -28,16 +28,12 @@
 extern unsigned long tb_ticks_per_jiffy;
 extern unsigned long tb_ticks_per_usec;
 extern unsigned long tb_ticks_per_sec;
-extern u64 tb_to_xs;
-extern unsigned      tb_to_us;
 
 struct rtc_time;
 extern void to_tm(int tim, struct rtc_time * tm);
 extern void GregorianDay(struct rtc_time *tm);
-extern time_t last_rtc_update;
 
 extern void generic_calibrate_decr(void);
-extern void wakeup_decrementer(void);
 extern void snapshot_timebase(void);
 
 extern void set_dec_cpu6(unsigned int val);
@@ -204,9 +200,6 @@ static inline unsigned long tb_ticks_since(unsigned long tstamp)
 extern u64 mulhdu(u64, u64);
 #endif
 
-extern void smp_space_timers(unsigned int);
-
-extern unsigned mulhwu_scale_factor(unsigned, unsigned);
 extern void div128_by_32(u64 dividend_high, u64 dividend_low,
                          unsigned divisor, struct div_result *dr);
 
diff --git a/arch/powerpc/include/asm/topology.h b/arch/powerpc/include/asm/topology.h
index 32adf7280720..3033c1b30745 100644
--- a/arch/powerpc/include/asm/topology.h
+++ b/arch/powerpc/include/asm/topology.h
@@ -87,6 +87,9 @@ static inline int pcibus_to_node(struct pci_bus *bus)
         .balance_interval       = 1,                                    \
 }
 
+extern int __node_distance(int, int);
+#define node_distance(a, b) __node_distance(a, b)
+
 extern void __init dump_numa_cpu_topology(void);
 
 extern int sysfs_add_device_to_node(struct sys_device *dev, int nid);
diff --git a/arch/powerpc/include/asm/vdso_datapage.h b/arch/powerpc/include/asm/vdso_datapage.h
index 13c2c283e178..08679c5319b8 100644
--- a/arch/powerpc/include/asm/vdso_datapage.h
+++ b/arch/powerpc/include/asm/vdso_datapage.h
@@ -85,6 +85,7 @@ struct vdso_data {
         __s32 wtom_clock_sec;                   /* Wall to monotonic clock */
         __s32 wtom_clock_nsec;
         struct timespec stamp_xtime;    /* xtime as at tb_orig_stamp */
+        __u32 stamp_sec_fraction;       /* fractional seconds of stamp_xtime */
         __u32 syscall_map_64[SYSCALL_MAP_SIZE]; /* map of syscalls  */
         __u32 syscall_map_32[SYSCALL_MAP_SIZE]; /* map of syscalls */
 };
@@ -105,6 +106,7 @@ struct vdso_data {
         __s32 wtom_clock_sec;                   /* Wall to monotonic clock */
         __s32 wtom_clock_nsec;
         struct timespec stamp_xtime;    /* xtime as at tb_orig_stamp */
+        __u32 stamp_sec_fraction;       /* fractional seconds of stamp_xtime */
         __u32 syscall_map_32[SYSCALL_MAP_SIZE]; /* map of syscalls */
         __u32 dcache_block_size;        /* L1 d-cache block size     */
         __u32 icache_block_size;        /* L1 i-cache block size     */
diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
index 58d0572de6f9..77d831a1cc32 100644
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -34,9 +34,10 @@ obj-y				+= vdso32/
 obj-$(CONFIG_PPC64)             += setup_64.o sys_ppc32.o \
                                    signal_64.o ptrace32.o \
                                    paca.o nvram_64.o firmware.o
+obj-$(CONFIG_HAVE_HW_BREAKPOINT)        += hw_breakpoint.o
 obj-$(CONFIG_PPC_BOOK3S_64)     += cpu_setup_ppc970.o cpu_setup_pa6t.o
 obj64-$(CONFIG_RELOCATABLE)     += reloc_64.o
-obj-$(CONFIG_PPC_BOOK3E_64)     += exceptions-64e.o
+obj-$(CONFIG_PPC_BOOK3E_64)     += exceptions-64e.o idle_book3e.o
 obj-$(CONFIG_PPC64)             += vdso64/
 obj-$(CONFIG_ALTIVEC)           += vecemu.o
 obj-$(CONFIG_PPC_970_NAP)       += idle_power4.o
@@ -67,6 +68,7 @@ obj64-$(CONFIG_HIBERNATION)	+= swsusp_asm64.o
 obj-$(CONFIG_MODULES)           += module.o module_$(CONFIG_WORD_SIZE).o
 obj-$(CONFIG_44x)               += cpu_setup_44x.o
 obj-$(CONFIG_FSL_BOOKE)         += cpu_setup_fsl_booke.o dbell.o
+obj-$(CONFIG_PPC_BOOK3E_64)     += dbell.o
 
 extra-y                         := head_$(CONFIG_WORD_SIZE).o
 extra-$(CONFIG_PPC_BOOK3E_32)   := head_new_booke.o
diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c
index 496cc5b3984f..1c0607ddccc0 100644
--- a/arch/powerpc/kernel/asm-offsets.c
+++ b/arch/powerpc/kernel/asm-offsets.c
@@ -194,7 +194,6 @@ int main(void)
         DEFINE(PACA_STARTSPURR, offsetof(struct paca_struct, startspurr));
         DEFINE(PACA_USER_TIME, offsetof(struct paca_struct, user_time));
         DEFINE(PACA_SYSTEM_TIME, offsetof(struct paca_struct, system_time));
-        DEFINE(PACA_DATA_OFFSET, offsetof(struct paca_struct, data_offset));
         DEFINE(PACA_TRAP_SAVE, offsetof(struct paca_struct, trap_save));
 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
         DEFINE(PACA_KVM_SVCPU, offsetof(struct paca_struct, shadow_vcpu));
@@ -342,6 +341,7 @@ int main(void)
         DEFINE(WTOM_CLOCK_SEC, offsetof(struct vdso_data, wtom_clock_sec));
         DEFINE(WTOM_CLOCK_NSEC, offsetof(struct vdso_data, wtom_clock_nsec));
         DEFINE(STAMP_XTIME, offsetof(struct vdso_data, stamp_xtime));
+        DEFINE(STAMP_SEC_FRAC, offsetof(struct vdso_data, stamp_sec_fraction));
         DEFINE(CFG_ICACHE_BLOCKSZ, offsetof(struct vdso_data, icache_block_size));
         DEFINE(CFG_DCACHE_BLOCKSZ, offsetof(struct vdso_data, dcache_block_size));
         DEFINE(CFG_ICACHE_LOGBLOCKSZ, offsetof(struct vdso_data, icache_log_block_size));
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index 87aa0f3c6047..65e2b4e10f97 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -1364,10 +1364,10 @@ static struct cpu_spec __initdata cpu_specs[] = {
                 .machine_check          = machine_check_4xx,
                 .platform               = "ppc405",
         },
-        {       /* 405EX */
-                .pvr_mask               = 0xffff0004,
-                .pvr_value              = 0x12910004,
-                .cpu_name               = "405EX",
+        {       /* 405EX Rev. A/B with Security */
+                .pvr_mask               = 0xffff000f,
+                .pvr_value              = 0x12910007,
+                .cpu_name               = "405EX Rev. A/B",
                 .cpu_features           = CPU_FTRS_40X,
                 .cpu_user_features      = PPC_FEATURE_32 |
                         PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
@@ -1377,10 +1377,114 @@ static struct cpu_spec __initdata cpu_specs[] = {
                 .machine_check          = machine_check_4xx,
                 .platform               = "ppc405",
         },
-        {       /* 405EXr */
-                .pvr_mask               = 0xffff0004,
+        {       /* 405EX Rev. C without Security */
+                .pvr_mask               = 0xffff000f,
+                .pvr_value              = 0x1291000d,
+                .cpu_name               = "405EX Rev. C",
+                .cpu_features           = CPU_FTRS_40X,
+                .cpu_user_features      = PPC_FEATURE_32 |
+                        PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
+                .mmu_features           = MMU_FTR_TYPE_40x,
+                .icache_bsize           = 32,
+                .dcache_bsize           = 32,
+                .machine_check          = machine_check_4xx,
+                .platform               = "ppc405",
+        },
+        {       /* 405EX Rev. C with Security */
+                .pvr_mask               = 0xffff000f,
+                .pvr_value              = 0x1291000f,
+                .cpu_name               = "405EX Rev. C",
+                .cpu_features           = CPU_FTRS_40X,
+                .cpu_user_features      = PPC_FEATURE_32 |
+                        PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
+                .mmu_features           = MMU_FTR_TYPE_40x,
+                .icache_bsize           = 32,
+                .dcache_bsize           = 32,
+                .machine_check          = machine_check_4xx,
+                .platform               = "ppc405",
+        },
+        {       /* 405EX Rev. D without Security */
+                .pvr_mask               = 0xffff000f,
+                .pvr_value              = 0x12910003,
+                .cpu_name               = "405EX Rev. D",
+                .cpu_features           = CPU_FTRS_40X,
+                .cpu_user_features      = PPC_FEATURE_32 |
+                        PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
+                .mmu_features           = MMU_FTR_TYPE_40x,
+                .icache_bsize           = 32,
+                .dcache_bsize           = 32,
+                .machine_check          = machine_check_4xx,
+                .platform               = "ppc405",
+        },
+        {       /* 405EX Rev. D with Security */
+                .pvr_mask               = 0xffff000f,
+                .pvr_value              = 0x12910005,
+                .cpu_name               = "405EX Rev. D",
+                .cpu_features           = CPU_FTRS_40X,
+                .cpu_user_features      = PPC_FEATURE_32 |
+                        PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
+                .mmu_features           = MMU_FTR_TYPE_40x,
+                .icache_bsize           = 32,
+                .dcache_bsize           = 32,
+                .machine_check          = machine_check_4xx,
+                .platform               = "ppc405",
+        },
+        {       /* 405EXr Rev. A/B without Security */
+                .pvr_mask               = 0xffff000f,
+                .pvr_value              = 0x12910001,
+                .cpu_name               = "405EXr Rev. A/B",
+                .cpu_features           = CPU_FTRS_40X,
+                .cpu_user_features      = PPC_FEATURE_32 |
+                        PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
+                .mmu_features           = MMU_FTR_TYPE_40x,
+                .icache_bsize           = 32,
+                .dcache_bsize           = 32,
+                .machine_check          = machine_check_4xx,
+                .platform               = "ppc405",
+        },
+        {       /* 405EXr Rev. C without Security */
+                .pvr_mask               = 0xffff000f,
+                .pvr_value              = 0x12910009,
+                .cpu_name               = "405EXr Rev. C",
+                .cpu_features           = CPU_FTRS_40X,
+                .cpu_user_features      = PPC_FEATURE_32 |
+                        PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
+                .mmu_features           = MMU_FTR_TYPE_40x,
+                .icache_bsize           = 32,
+                .dcache_bsize           = 32,
+                .machine_check          = machine_check_4xx,
+                .platform               = "ppc405",
+        },
+        {       /* 405EXr Rev. C with Security */
+                .pvr_mask               = 0xffff000f,
+                .pvr_value              = 0x1291000b,
+                .cpu_name               = "405EXr Rev. C",
+                .cpu_features           = CPU_FTRS_40X,
+                .cpu_user_features      = PPC_FEATURE_32 |
+                        PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
+                .mmu_features           = MMU_FTR_TYPE_40x,
+                .icache_bsize           = 32,
+                .dcache_bsize           = 32,
+                .machine_check          = machine_check_4xx,
+                .platform               = "ppc405",
+        },
+        {       /* 405EXr Rev. D without Security */
+                .pvr_mask               = 0xffff000f,
                 .pvr_value              = 0x12910000,
-                .cpu_name               = "405EXr",
+                .cpu_name               = "405EXr Rev. D",
+                .cpu_features           = CPU_FTRS_40X,
+                .cpu_user_features      = PPC_FEATURE_32 |
+                        PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
+                .mmu_features           = MMU_FTR_TYPE_40x,
+                .icache_bsize           = 32,
+                .dcache_bsize           = 32,
+                .machine_check          = machine_check_4xx,
+                .platform               = "ppc405",
+        },
+        {       /* 405EXr Rev. D with Security */
+                .pvr_mask               = 0xffff000f,
+                .pvr_value              = 0x12910002,
+                .cpu_name               = "405EXr Rev. D",
                 .cpu_features           = CPU_FTRS_40X,
                 .cpu_user_features      = PPC_FEATURE_32 |
                         PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
diff --git a/arch/powerpc/kernel/crash_dump.c b/arch/powerpc/kernel/crash_dump.c
index 40f524643ba6..8e05c16344e4 100644
--- a/arch/powerpc/kernel/crash_dump.c
+++ b/arch/powerpc/kernel/crash_dump.c
@@ -128,9 +128,9 @@ ssize_t copy_oldmem_page(unsigned long pfn, char *buf,
         if (!csize)
                 return 0;
 
-        csize = min(csize, PAGE_SIZE);
+        csize = min_t(size_t, csize, PAGE_SIZE);
 
-        if (pfn < max_pfn) {
+        if ((min_low_pfn < pfn) && (pfn < max_pfn)) {
                 vaddr = __va(pfn << PAGE_SHIFT);
                 csize = copy_oldmem_vaddr(vaddr, buf, csize, offset, userbuf);
         } else {
diff --git a/arch/powerpc/kernel/dbell.c b/arch/powerpc/kernel/dbell.c
index 1493734cd871..3307a52d797f 100644
--- a/arch/powerpc/kernel/dbell.c
+++ b/arch/powerpc/kernel/dbell.c
@@ -13,32 +13,88 @@
 #include <linux/kernel.h>
 #include <linux/smp.h>
 #include <linux/threads.h>
+#include <linux/percpu.h>
 
 #include <asm/dbell.h>
+#include <asm/irq_regs.h>
 
 #ifdef CONFIG_SMP
-unsigned long dbell_smp_message[NR_CPUS];
+struct doorbell_cpu_info {
+        unsigned long   messages;       /* current messages bits */
+        unsigned int    tag;            /* tag value */
+};
 
-void smp_dbell_message_pass(int target, int msg)
+static DEFINE_PER_CPU(struct doorbell_cpu_info, doorbell_cpu_info);
+
+void doorbell_setup_this_cpu(void)
+{
+        struct doorbell_cpu_info *info = &__get_cpu_var(doorbell_cpu_info);
+
+        info->messages = 0;
+        info->tag = mfspr(SPRN_PIR) & 0x3fff;
+}
+
+void doorbell_message_pass(int target, int msg)
 {
+        struct doorbell_cpu_info *info;
         int i;
 
-        if(target < NR_CPUS) {
-                set_bit(msg, &dbell_smp_message[target]);
-                ppc_msgsnd(PPC_DBELL, 0, target);
+        if (target < NR_CPUS) {
+                info = &per_cpu(doorbell_cpu_info, target);
+                set_bit(msg, &info->messages);
+                ppc_msgsnd(PPC_DBELL, 0, info->tag);
         }
-        else if(target == MSG_ALL_BUT_SELF) {
+        else if (target == MSG_ALL_BUT_SELF) {
                 for_each_online_cpu(i) {
                         if (i == smp_processor_id())
                                 continue;
-                        set_bit(msg, &dbell_smp_message[i]);
-                        ppc_msgsnd(PPC_DBELL, 0, i);
+                        info = &per_cpu(doorbell_cpu_info, i);
+                        set_bit(msg, &info->messages);
+                        ppc_msgsnd(PPC_DBELL, 0, info->tag);
                 }
         }
         else { /* target == MSG_ALL */
-                for_each_online_cpu(i)
-                        set_bit(msg, &dbell_smp_message[i]);
+                for_each_online_cpu(i) {
+                        info = &per_cpu(doorbell_cpu_info, i);
+                        set_bit(msg, &info->messages);
+                }
                 ppc_msgsnd(PPC_DBELL, PPC_DBELL_MSG_BRDCAST, 0);
         }
 }
-#endif
+
+void doorbell_exception(struct pt_regs *regs)
+{
+        struct pt_regs *old_regs = set_irq_regs(regs);
+        struct doorbell_cpu_info *info = &__get_cpu_var(doorbell_cpu_info);
+        int msg;
+
+        /* Warning: regs can be NULL when called from irq enable */
+
+        if (!info->messages || (num_online_cpus() < 2))
+                goto out;
+
+        for (msg = 0; msg < 4; msg++)
+                if (test_and_clear_bit(msg, &info->messages))
+                        smp_message_recv(msg);
+
+out:
+        set_irq_regs(old_regs);
+}
+
+void doorbell_check_self(void)
+{
+        struct doorbell_cpu_info *info = &__get_cpu_var(doorbell_cpu_info);
+
+        if (!info->messages)
+                return;
+
+        ppc_msgsnd(PPC_DBELL, 0, info->tag);
+}
+
+#else /* CONFIG_SMP */
+void doorbell_exception(struct pt_regs *regs)
+{
+        printk(KERN_WARNING "Received doorbell on non-smp system\n");
+}
+#endif /* CONFIG_SMP */
+
diff --git a/arch/powerpc/kernel/exceptions-64e.S b/arch/powerpc/kernel/exceptions-64e.S
index 24dcc0ecf246..5c43063d2506 100644
--- a/arch/powerpc/kernel/exceptions-64e.S
+++ b/arch/powerpc/kernel/exceptions-64e.S
@@ -191,6 +191,12 @@ exc_##n##_bad_stack:							    \
         sth     r1,PACA_TRAP_SAVE(r13); /* store trap */                    \
         b       bad_stack_book3e;       /* bad stack error */
 
+/* WARNING: If you change the layout of this stub, make sure you chcek
+        *   the debug exception handler which handles single stepping
+        *   into exceptions from userspace, and the MM code in
+        *   arch/powerpc/mm/tlb_nohash.c which patches the branch here
+        *   and would need to be updated if that branch is moved
+        */
 #define EXCEPTION_STUB(loc, label)                                      \
         . = interrupt_base_book3e + loc;                                \
         nop;    /* To make debug interrupts happy */                    \
@@ -204,11 +210,30 @@ exc_##n##_bad_stack:							    \
         lis     r,TSR_FIS@h;                                            \
         mtspr   SPRN_TSR,r
 
+/* Used by asynchronous interrupt that may happen in the idle loop.
+ *
+ * This check if the thread was in the idle loop, and if yes, returns
+ * to the caller rather than the PC. This is to avoid a race if
+ * interrupts happen before the wait instruction.
+ */
+#define CHECK_NAPPING()                                                 \
+        clrrdi  r11,r1,THREAD_SHIFT;                                    \
+        ld      r10,TI_LOCAL_FLAGS(r11);                                \
+        andi.   r9,r10,_TLF_NAPPING;                                    \
+        beq+    1f;                                                     \
+        ld      r8,_LINK(r1);                                           \
+        rlwinm  r7,r10,0,~_TLF_NAPPING;                                 \
+        std     r8,_NIP(r1);                                            \
+        std     r7,TI_LOCAL_FLAGS(r11);                                 \
+1:
+
+
 #define MASKABLE_EXCEPTION(trapnum, label, hdlr, ack)                   \
         START_EXCEPTION(label);                                         \
         NORMAL_EXCEPTION_PROLOG(trapnum, PROLOG_ADDITION_MASKABLE)      \
         EXCEPTION_COMMON(trapnum, PACA_EXGEN, INTS_DISABLE_ALL)         \
         ack(r8);                                                        \
+        CHECK_NAPPING();                                                \
         addi    r3,r1,STACK_FRAME_OVERHEAD;                             \
         bl      hdlr;                                                   \
         b       .ret_from_except_lite;
@@ -246,11 +271,9 @@ interrupt_base_book3e:					/* fake trap */
         EXCEPTION_STUB(0x1a0, watchdog)                 /* 0x09f0 */
         EXCEPTION_STUB(0x1c0, data_tlb_miss)
         EXCEPTION_STUB(0x1e0, instruction_tlb_miss)
+        EXCEPTION_STUB(0x280, doorbell)
+        EXCEPTION_STUB(0x2a0, doorbell_crit)
 
-#if 0
-        EXCEPTION_STUB(0x280, processor_doorbell)
-        EXCEPTION_STUB(0x220, processor_doorbell_crit)
-#endif
         .globl interrupt_end_book3e
 interrupt_end_book3e:
 
@@ -259,6 +282,7 @@ interrupt_end_book3e:
         CRIT_EXCEPTION_PROLOG(0x100, PROLOG_ADDITION_NONE)
 //      EXCEPTION_COMMON(0x100, PACA_EXCRIT, INTS_DISABLE_ALL)
 //      bl      special_reg_save_crit
+//      CHECK_NAPPING();
 //      addi    r3,r1,STACK_FRAME_OVERHEAD
 //      bl      .critical_exception
 //      b       ret_from_crit_except
@@ -270,6 +294,7 @@ interrupt_end_book3e:
 //      EXCEPTION_COMMON(0x200, PACA_EXMC, INTS_DISABLE_ALL)
 //      bl      special_reg_save_mc
 //      addi    r3,r1,STACK_FRAME_OVERHEAD
+//      CHECK_NAPPING();
 //      bl      .machine_check_exception
 //      b       ret_from_mc_except
         b       .
@@ -340,6 +365,7 @@ interrupt_end_book3e:
         CRIT_EXCEPTION_PROLOG(0x9f0, PROLOG_ADDITION_NONE)
 //      EXCEPTION_COMMON(0x9f0, PACA_EXCRIT, INTS_DISABLE_ALL)
 //      bl      special_reg_save_crit
+//      CHECK_NAPPING();
 //      addi    r3,r1,STACK_FRAME_OVERHEAD
 //      bl      .unknown_exception
 //      b       ret_from_crit_except
@@ -428,6 +454,20 @@ interrupt_end_book3e:
 kernel_dbg_exc:
         b       .       /* NYI */
 
+/* Doorbell interrupt */
+        MASKABLE_EXCEPTION(0x2070, doorbell, .doorbell_exception, ACK_NONE)
+
+/* Doorbell critical Interrupt */
+        START_EXCEPTION(doorbell_crit);
+        CRIT_EXCEPTION_PROLOG(0x2080, PROLOG_ADDITION_NONE)
+//      EXCEPTION_COMMON(0x2080, PACA_EXCRIT, INTS_DISABLE_ALL)
+//      bl      special_reg_save_crit
+//      CHECK_NAPPING();
+//      addi    r3,r1,STACK_FRAME_OVERHEAD
+//      bl      .doorbell_critical_exception
+//      b       ret_from_crit_except
+        b       .
+
 
 /*
  * An interrupt came in while soft-disabled; clear EE in SRR1,
@@ -563,6 +603,8 @@ BAD_STACK_TRAMPOLINE(0xd00)
 BAD_STACK_TRAMPOLINE(0xe00)
 BAD_STACK_TRAMPOLINE(0xf00)
 BAD_STACK_TRAMPOLINE(0xf20)
+BAD_STACK_TRAMPOLINE(0x2070)
+BAD_STACK_TRAMPOLINE(0x2080)
 
         .globl  bad_stack_book3e
 bad_stack_book3e:
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index 3e423fbad6bc..f53029a01554 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -828,6 +828,7 @@ END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES)
 
 /* We have a data breakpoint exception - handle it */
 handle_dabr_fault:
+        bl      .save_nvgprs
         ld      r4,_DAR(r1)
         ld      r5,_DSISR(r1)
         addi    r3,r1,STACK_FRAME_OVERHEAD
diff --git a/arch/powerpc/kernel/hw_breakpoint.c b/arch/powerpc/kernel/hw_breakpoint.c
new file mode 100644
index 000000000000..5ecd0401cdb1
--- /dev/null
+++ b/arch/powerpc/kernel/hw_breakpoint.c
@@ -0,0 +1,364 @@
+/*
+ * HW_breakpoint: a unified kernel/user-space hardware breakpoint facility,
+ * using the CPU's debug registers. Derived from
+ * "arch/x86/kernel/hw_breakpoint.c"
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright 2010 IBM Corporation
+ * Author: K.Prasad <prasad@linux.vnet.ibm.com>
+ *
+ */
+
+#include <linux/hw_breakpoint.h>
+#include <linux/notifier.h>
+#include <linux/kprobes.h>
+#include <linux/percpu.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/init.h>
+#include <linux/smp.h>
+
+#include <asm/hw_breakpoint.h>
+#include <asm/processor.h>
+#include <asm/sstep.h>
+#include <asm/uaccess.h>
+
+/*
+ * Stores the breakpoints currently in use on each breakpoint address
+ * register for every cpu
+ */
+static DEFINE_PER_CPU(struct perf_event *, bp_per_reg);
+
+/*
+ * Returns total number of data or instruction breakpoints available.
+ */
+int hw_breakpoint_slots(int type)
+{
+        if (type == TYPE_DATA)
+                return HBP_NUM;
+        return 0;               /* no instruction breakpoints available */
+}
+
+/*
+ * Install a perf counter breakpoint.
+ *
+ * We seek a free debug address register and use it for this
+ * breakpoint.
+ *
+ * Atomic: we hold the counter->ctx->lock and we only handle variables
+ * and registers local to this cpu.
+ */
+int arch_install_hw_breakpoint(struct perf_event *bp)
+{
+        struct arch_hw_breakpoint *info = counter_arch_bp(bp);
+        struct perf_event **slot = &__get_cpu_var(bp_per_reg);
+
+        *slot = bp;
+
+        /*
+         * Do not install DABR values if the instruction must be single-stepped.
+         * If so, DABR will be populated in single_step_dabr_instruction().
+         */
+        if (current->thread.last_hit_ubp != bp)
+                set_dabr(info->address | info->type | DABR_TRANSLATION);
+
+        return 0;
+}
+
+/*
+ * Uninstall the breakpoint contained in the given counter.
+ *
+ * First we search the debug address register it uses and then we disable
+ * it.
+ *
+ * Atomic: we hold the counter->ctx->lock and we only handle variables
+ * and registers local to this cpu.
+ */
+void arch_uninstall_hw_breakpoint(struct perf_event *bp)
+{
+        struct perf_event **slot = &__get_cpu_var(bp_per_reg);
+
+        if (*slot != bp) {
+                WARN_ONCE(1, "Can't find the breakpoint");
+                return;
+        }
+
+        *slot = NULL;
+        set_dabr(0);
+}
+
+/*
+ * Perform cleanup of arch-specific counters during unregistration
+ * of the perf-event
+ */
+void arch_unregister_hw_breakpoint(struct perf_event *bp)
+{
+        /*
+         * If the breakpoint is unregistered between a hw_breakpoint_handler()
+         * and the single_step_dabr_instruction(), then cleanup the breakpoint
+         * restoration variables to prevent dangling pointers.
+         */
+        if (bp->ctx->task)
+                bp->ctx->task->thread.last_hit_ubp = NULL;
+}
+
+/*
+ * Check for virtual address in kernel space.
+ */
+int arch_check_bp_in_kernelspace(struct perf_event *bp)
+{
+        struct arch_hw_breakpoint *info = counter_arch_bp(bp);
+
+        return is_kernel_addr(info->address);
+}
+
+int arch_bp_generic_fields(int type, int *gen_bp_type)
+{
+        switch (type) {
+        case DABR_DATA_READ:
+                *gen_bp_type = HW_BREAKPOINT_R;
+                break;
+        case DABR_DATA_WRITE:
+                *gen_bp_type = HW_BREAKPOINT_W;
+                break;
+        case (DABR_DATA_WRITE | DABR_DATA_READ):
+                *gen_bp_type = (HW_BREAKPOINT_W | HW_BREAKPOINT_R);
+                break;
+        default:
+                return -EINVAL;
+        }
+        return 0;
+}
+
+/*
+ * Validate the arch-specific HW Breakpoint register settings
+ */
+int arch_validate_hwbkpt_settings(struct perf_event *bp)
+{
+        int ret = -EINVAL;
+        struct arch_hw_breakpoint *info = counter_arch_bp(bp);
+
+        if (!bp)
+                return ret;
+
+        switch (bp->attr.bp_type) {
+        case HW_BREAKPOINT_R:
+                info->type = DABR_DATA_READ;
+                break;
+        case HW_BREAKPOINT_W:
+                info->type = DABR_DATA_WRITE;
+                break;
+        case HW_BREAKPOINT_R | HW_BREAKPOINT_W:
+                info->type = (DABR_DATA_READ | DABR_DATA_WRITE);
+                break;
+        default:
+                return ret;
+        }
+
+        info->address = bp->attr.bp_addr;
+        info->len = bp->attr.bp_len;
+
+        /*
+         * Since breakpoint length can be a maximum of HW_BREAKPOINT_LEN(8)
+         * and breakpoint addresses are aligned to nearest double-word
+         * HW_BREAKPOINT_ALIGN by rounding off to the lower address, the
+         * 'symbolsize' should satisfy the check below.
+         */
+        if (info->len >
+            (HW_BREAKPOINT_LEN - (info->address & HW_BREAKPOINT_ALIGN)))
+                return -EINVAL;
+        return 0;
+}
+
+/*
+ * Restores the breakpoint on the debug registers.
+ * Invoke this function if it is known that the execution context is
+ * about to change to cause loss of MSR_SE settings.
+ */
+void thread_change_pc(struct task_struct *tsk, struct pt_regs *regs)
+{
+        struct arch_hw_breakpoint *info;
+
+        if (likely(!tsk->thread.last_hit_ubp))
+                return;
+
+        info = counter_arch_bp(tsk->thread.last_hit_ubp);
+        regs->msr &= ~MSR_SE;
+        set_dabr(info->address | info->type | DABR_TRANSLATION);
+        tsk->thread.last_hit_ubp = NULL;
+}
+
+/*
+ * Handle debug exception notifications.
+ */
+int __kprobes hw_breakpoint_handler(struct die_args *args)
+{
+        int rc = NOTIFY_STOP;
+        struct perf_event *bp;
+        struct pt_regs *regs = args->regs;
+        int stepped = 1;
+        struct arch_hw_breakpoint *info;
+        unsigned int instr;
+        unsigned long dar = regs->dar;
+
+        /* Disable breakpoints during exception handling */
+        set_dabr(0);
+
+        /*
+         * The counter may be concurrently released but that can only
+         * occur from a call_rcu() path. We can then safely fetch
+         * the breakpoint, use its callback, touch its counter
+         * while we are in an rcu_read_lock() path.
+         */
+        rcu_read_lock();
+
+        bp = __get_cpu_var(bp_per_reg);
+        if (!bp)
+                goto out;
+        info = counter_arch_bp(bp);
+
+        /*
+         * Return early after invoking user-callback function without restoring
+         * DABR if the breakpoint is from ptrace which always operates in
+         * one-shot mode. The ptrace-ed process will receive the SIGTRAP signal
+         * generated in do_dabr().
+         */
+        if (bp->overflow_handler == ptrace_triggered) {
+                perf_bp_event(bp, regs);
+                rc = NOTIFY_DONE;
+                goto out;
+        }
+
+        /*
+         * Verify if dar lies within the address range occupied by the symbol
+         * being watched to filter extraneous exceptions.  If it doesn't,
+         * we still need to single-step the instruction, but we don't
+         * generate an event.
+         */
+        info->extraneous_interrupt = !((bp->attr.bp_addr <= dar) &&
+                        (dar - bp->attr.bp_addr < bp->attr.bp_len));
+
+        /* Do not emulate user-space instructions, instead single-step them */
+        if (user_mode(regs)) {
+                bp->ctx->task->thread.last_hit_ubp = bp;
+                regs->msr |= MSR_SE;
+                goto out;
+        }
+
+        stepped = 0;
+        instr = 0;
+        if (!__get_user_inatomic(instr, (unsigned int *) regs->nip))
+                stepped = emulate_step(regs, instr);
+
+        /*
+         * emulate_step() could not execute it. We've failed in reliably
+         * handling the hw-breakpoint. Unregister it and throw a warning
+         * message to let the user know about it.
+         */
+        if (!stepped) {
+                WARN(1, "Unable to handle hardware breakpoint. Breakpoint at "
+                        "0x%lx will be disabled.", info->address);
+                perf_event_disable(bp);
+                goto out;
+        }
+        /*
+         * As a policy, the callback is invoked in a 'trigger-after-execute'
+         * fashion
+         */
+        if (!info->extraneous_interrupt)
+                perf_bp_event(bp, regs);
+
+        set_dabr(info->address | info->type | DABR_TRANSLATION);
+out:
+        rcu_read_unlock();
+        return rc;
+}
+
+/*
+ * Handle single-step exceptions following a DABR hit.
+ */
+int __kprobes single_step_dabr_instruction(struct die_args *args)
+{
+        struct pt_regs *regs = args->regs;
+        struct perf_event *bp = NULL;
+        struct arch_hw_breakpoint *bp_info;
+
+        bp = current->thread.last_hit_ubp;
+        /*
+         * Check if we are single-stepping as a result of a
+         * previous HW Breakpoint exception
+         */
+        if (!bp)
+                return NOTIFY_DONE;
+
+        bp_info = counter_arch_bp(bp);
+
+        /*
+         * We shall invoke the user-defined callback function in the single
+         * stepping handler to confirm to 'trigger-after-execute' semantics
+         */
+        if (!bp_info->extraneous_interrupt)
+                perf_bp_event(bp, regs);
+
+        set_dabr(bp_info->address | bp_info->type | DABR_TRANSLATION);
+        current->thread.last_hit_ubp = NULL;
+
+        /*
+         * If the process was being single-stepped by ptrace, let the
+         * other single-step actions occur (e.g. generate SIGTRAP).
+         */
+        if (test_thread_flag(TIF_SINGLESTEP))
+                return NOTIFY_DONE;
+
+        return NOTIFY_STOP;
+}
+
+/*
+ * Handle debug exception notifications.
+ */
+int __kprobes hw_breakpoint_exceptions_notify(
+                struct notifier_block *unused, unsigned long val, void *data)
+{
+        int ret = NOTIFY_DONE;
+
+        switch (val) {
+        case DIE_DABR_MATCH:
+                ret = hw_breakpoint_handler(data);
+                break;
+        case DIE_SSTEP:
+                ret = single_step_dabr_instruction(data);
+                break;
+        }
+
+        return ret;
+}
+
+/*
+ * Release the user breakpoints used by ptrace
+ */
+void flush_ptrace_hw_breakpoint(struct task_struct *tsk)
+{
+        struct thread_struct *t = &tsk->thread;
+
+        unregister_hw_breakpoint(t->ptrace_bps[0]);
+        t->ptrace_bps[0] = NULL;
+}
+
+void hw_breakpoint_pmu_read(struct perf_event *bp)
+{
+        /* TODO */
+}
diff --git a/arch/powerpc/kernel/idle_book3e.S b/arch/powerpc/kernel/idle_book3e.S
new file mode 100644
index 000000000000..16c002d6bdf1
--- /dev/null
+++ b/arch/powerpc/kernel/idle_book3e.S
@@ -0,0 +1,86 @@
+/*
+ * Copyright 2010 IBM Corp, Benjamin Herrenschmidt <benh@kernel.crashing.org>
+ *
+ * Generic idle routine for Book3E processors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/threads.h>
+#include <asm/reg.h>
+#include <asm/ppc_asm.h>
+#include <asm/asm-offsets.h>
+#include <asm/ppc-opcode.h>
+#include <asm/processor.h>
+#include <asm/thread_info.h>
+
+/* 64-bit version only for now */
+#ifdef CONFIG_PPC64
+
+_GLOBAL(book3e_idle)
+        /* Save LR for later */
+        mflr    r0
+        std     r0,16(r1)
+
+        /* Hard disable interrupts */
+        wrteei  0
+
+        /* Now check if an interrupt came in while we were soft disabled
+         * since we may otherwise lose it (doorbells etc...). We know
+         * that since PACAHARDIRQEN will have been cleared in that case.
+         */
+        lbz     r3,PACAHARDIRQEN(r13)
+        cmpwi   cr0,r3,0
+        beqlr
+
+        /* Now we are going to mark ourselves as soft and hard enables in
+         * order to be able to take interrupts while asleep. We inform lockdep
+         * of that. We don't actually turn interrupts on just yet tho.
+         */
+#ifdef CONFIG_TRACE_IRQFLAGS
+        stdu    r1,-128(r1)
+        bl      .trace_hardirqs_on
+#endif
+        li      r0,1
+        stb     r0,PACASOFTIRQEN(r13)
+        stb     r0,PACAHARDIRQEN(r13)
+        
+        /* Interrupts will make use return to LR, so get something we want
+         * in there
+         */
+        bl      1f
+
+        /* Hard disable interrupts again */
+        wrteei  0
+
+        /* Mark them off again in the PACA as well */
+        li      r0,0
+        stb     r0,PACASOFTIRQEN(r13)
+        stb     r0,PACAHARDIRQEN(r13)
+
+        /* Tell lockdep about it */
+#ifdef CONFIG_TRACE_IRQFLAGS
+        bl      .trace_hardirqs_off
+        addi    r1,r1,128
+#endif
+        ld      r0,16(r1)
+        mtlr    r0
+        blr
+
+1:      /* Let's set the _TLF_NAPPING flag so interrupts make us return
+         * to the right spot
+        */
+        clrrdi  r11,r1,THREAD_SHIFT
+        ld      r10,TI_LOCAL_FLAGS(r11)
+        ori     r10,r10,_TLF_NAPPING
+        std     r10,TI_LOCAL_FLAGS(r11)
+
+        /* We can now re-enable hard interrupts and go to sleep */
+        wrteei  1
+1:      PPC_WAIT(0)
+        b       1b
+
+#endif /* CONFIG_PPC64 */
diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c
index 77be3d058a65..8f96d3198905 100644
--- a/arch/powerpc/kernel/irq.c
+++ b/arch/powerpc/kernel/irq.c
@@ -64,6 +64,8 @@
 #include <asm/ptrace.h>
 #include <asm/machdep.h>
 #include <asm/udbg.h>
+#include <asm/dbell.h>
+
 #ifdef CONFIG_PPC64
 #include <asm/paca.h>
 #include <asm/firmware.h>
@@ -153,14 +155,28 @@ notrace void raw_local_irq_restore(unsigned long en)
         if (get_hard_enabled())
                 return;
 
+#if defined(CONFIG_BOOKE) && defined(CONFIG_SMP)
+        /* Check for pending doorbell interrupts and resend to ourself */
+        doorbell_check_self();
+#endif
+
         /*
          * Need to hard-enable interrupts here.  Since currently disabled,
          * no need to take further asm precautions against preemption; but
          * use local_paca instead of get_paca() to avoid preemption checking.
          */
         local_paca->hard_enabled = en;
+
+#ifndef CONFIG_BOOKE
+        /* On server, re-trigger the decrementer if it went negative since
+         * some processors only trigger on edge transitions of the sign bit.
+         *
+         * BookE has a level sensitive decrementer (latches in TSR) so we
+         * don't need that
+         */
         if ((int)mfspr(SPRN_DEC) < 0)
                 mtspr(SPRN_DEC, 1);
+#endif /* CONFIG_BOOKE */
 
         /*
          * Force the delivery of pending soft-disabled interrupts on PS3.
diff --git a/arch/powerpc/kernel/machine_kexec.c b/arch/powerpc/kernel/machine_kexec.c
index 89f005116aac..dd6c141f1662 100644
--- a/arch/powerpc/kernel/machine_kexec.c
+++ b/arch/powerpc/kernel/machine_kexec.c
@@ -45,6 +45,18 @@ void machine_kexec_cleanup(struct kimage *image)
                 ppc_md.machine_kexec_cleanup(image);
 }
 
+void arch_crash_save_vmcoreinfo(void)
+{
+
+#ifdef CONFIG_NEED_MULTIPLE_NODES
+        VMCOREINFO_SYMBOL(node_data);
+        VMCOREINFO_LENGTH(node_data, MAX_NUMNODES);
+#endif
+#ifndef CONFIG_NEED_MULTIPLE_NODES
+        VMCOREINFO_SYMBOL(contig_page_data);
+#endif
+}
+
 /*
  * Do not allocate memory (or fail in any way) in machine_kexec().
  * We are past the point of no return, committed to rebooting now.
@@ -144,24 +156,24 @@ int overlaps_crashkernel(unsigned long start, unsigned long size)
 }
 
 /* Values we need to export to the second kernel via the device tree. */
-static unsigned long kernel_end;
-static unsigned long crashk_size;
+static phys_addr_t kernel_end;
+static phys_addr_t crashk_size;
 
 static struct property kernel_end_prop = {
         .name = "linux,kernel-end",
-        .length = sizeof(unsigned long),
+        .length = sizeof(phys_addr_t),
         .value = &kernel_end,
 };
 
 static struct property crashk_base_prop = {
         .name = "linux,crashkernel-base",
-        .length = sizeof(unsigned long),
+        .length = sizeof(phys_addr_t),
         .value = &crashk_res.start,
 };
 
 static struct property crashk_size_prop = {
         .name = "linux,crashkernel-size",
-        .length = sizeof(unsigned long),
+        .length = sizeof(phys_addr_t),
         .value = &crashk_size,
 };
 
diff --git a/arch/powerpc/kernel/machine_kexec_64.c b/arch/powerpc/kernel/machine_kexec_64.c
index ed31a29c4ff7..583af70c4b14 100644
--- a/arch/powerpc/kernel/machine_kexec_64.c
+++ b/arch/powerpc/kernel/machine_kexec_64.c
@@ -15,6 +15,8 @@
 #include <linux/thread_info.h>
 #include <linux/init_task.h>
 #include <linux/errno.h>
+#include <linux/kernel.h>
+#include <linux/cpu.h>
 
 #include <asm/page.h>
 #include <asm/current.h>
@@ -25,6 +27,7 @@
 #include <asm/sections.h>       /* _end */
 #include <asm/prom.h>
 #include <asm/smp.h>
+#include <asm/hw_breakpoint.h>
 
 int default_machine_kexec_prepare(struct kimage *image)
 {
@@ -165,6 +168,7 @@ static void kexec_smp_down(void *arg)
         while(kexec_all_irq_disabled == 0)
                 cpu_relax();
         mb(); /* make sure all irqs are disabled before this */
+        hw_breakpoint_disable();
         /*
          * Now every CPU has IRQs off, we can clear out any pending
          * IPIs and be sure that no more will come in after this.
@@ -180,8 +184,22 @@ static void kexec_prepare_cpus_wait(int wait_state)
 {
         int my_cpu, i, notified=-1;
 
+        hw_breakpoint_disable();
         my_cpu = get_cpu();
-        /* Make sure each CPU has atleast made it to the state we need */
+        /* Make sure each CPU has at least made it to the state we need.
+         *
+         * FIXME: There is a (slim) chance of a problem if not all of the CPUs
+         * are correctly onlined.  If somehow we start a CPU on boot with RTAS
+         * start-cpu, but somehow that CPU doesn't write callin_cpu_map[] in
+         * time, the boot CPU will timeout.  If it does eventually execute
+         * stuff, the secondary will start up (paca[].cpu_start was written) and
+         * get into a peculiar state.  If the platform supports
+         * smp_ops->take_timebase(), the secondary CPU will probably be spinning
+         * in there.  If not (i.e. pseries), the secondary will continue on and
+         * try to online itself/idle/etc. If it survives that, we need to find
+         * these possible-but-not-online-but-should-be CPUs and chaperone them
+         * into kexec_smp_wait().
+         */
         for_each_online_cpu(i) {
                 if (i == my_cpu)
                         continue;
@@ -189,9 +207,9 @@ static void kexec_prepare_cpus_wait(int wait_state)
                 while (paca[i].kexec_state < wait_state) {
                         barrier();
                         if (i != notified) {
-                                printk( "kexec: waiting for cpu %d (physical"
-                                                " %d) to enter %i state\n",
-                                        i, paca[i].hw_cpu_id, wait_state);
+                                printk(KERN_INFO "kexec: waiting for cpu %d "
+                                       "(physical %d) to enter %i state\n",
+                                       i, paca[i].hw_cpu_id, wait_state);
                                 notified = i;
                         }
                 }
@@ -199,9 +217,32 @@ static void kexec_prepare_cpus_wait(int wait_state)
         mb();
 }
 
-static void kexec_prepare_cpus(void)
+/*
+ * We need to make sure each present CPU is online.  The next kernel will scan
+ * the device tree and assume primary threads are online and query secondary
+ * threads via RTAS to online them if required.  If we don't online primary
+ * threads, they will be stuck.  However, we also online secondary threads as we
+ * may be using 'cede offline'.  In this case RTAS doesn't see the secondary
+ * threads as offline -- and again, these CPUs will be stuck.
+ *
+ * So, we online all CPUs that should be running, including secondary threads.
+ */
+static void wake_offline_cpus(void)
 {
+        int cpu = 0;
 
+        for_each_present_cpu(cpu) {
+                if (!cpu_online(cpu)) {
+                        printk(KERN_INFO "kexec: Waking offline cpu %d.\n",
+                               cpu);
+                        cpu_up(cpu);
+                }
+        }
+}
+
+static void kexec_prepare_cpus(void)
+{
+        wake_offline_cpus();
         smp_call_function(kexec_smp_down, NULL, /* wait */0);
         local_irq_disable();
         mb(); /* make sure IRQs are disabled before we say they are */
@@ -215,7 +256,10 @@ static void kexec_prepare_cpus(void)
         if (ppc_md.kexec_cpu_down)
                 ppc_md.kexec_cpu_down(0, 0);
 
-        /* Before removing MMU mapings make sure all CPUs have entered real mode */
+        /*
+         * Before removing MMU mappings make sure all CPUs have entered real
+         * mode:
+         */
         kexec_prepare_cpus_wait(KEXEC_STATE_REAL_MODE);
 
         put_cpu();
@@ -257,6 +301,12 @@ static void kexec_prepare_cpus(void)
 static union thread_union kexec_stack __init_task_data =
         { };
 
+/*
+ * For similar reasons to the stack above, the kexecing CPU needs to be on a
+ * static PACA; we switch to kexec_paca.
+ */
+struct paca_struct kexec_paca;
+
 /* Our assembly helper, in kexec_stub.S */
 extern NORET_TYPE void kexec_sequence(void *newstack, unsigned long start,
                                         void *image, void *control,
@@ -278,12 +328,28 @@ void default_machine_kexec(struct kimage *image)
         if (crashing_cpu == -1)
                 kexec_prepare_cpus();
 
+        pr_debug("kexec: Starting switchover sequence.\n");
+
         /* switch to a staticly allocated stack.  Based on irq stack code.
          * XXX: the task struct will likely be invalid once we do the copy!
          */
         kexec_stack.thread_info.task = current_thread_info()->task;
         kexec_stack.thread_info.flags = 0;
 
+        /* We need a static PACA, too; copy this CPU's PACA over and switch to
+         * it.  Also poison per_cpu_offset to catch anyone using non-static
+         * data.
+         */
+        memcpy(&kexec_paca, get_paca(), sizeof(struct paca_struct));
+        kexec_paca.data_offset = 0xedeaddeadeeeeeeeUL;
+        paca = (struct paca_struct *)RELOC_HIDE(&kexec_paca, 0) -
+                kexec_paca.paca_index;
+        setup_paca(&kexec_paca);
+
+        /* XXX: If anyone does 'dynamic lppacas' this will also need to be
+         * switched to a static version!
+         */
+
         /* Some things are best done in assembly.  Finding globals with
          * a toc is easier in C, so pass in what we can.
          */
diff --git a/arch/powerpc/kernel/paca.c b/arch/powerpc/kernel/paca.c
index 139a773853f4..d0a26f1770fe 100644
--- a/arch/powerpc/kernel/paca.c
+++ b/arch/powerpc/kernel/paca.c
@@ -105,6 +105,16 @@ void __init initialise_paca(struct paca_struct *new_paca, int cpu)
 #endif /* CONFIG_PPC_STD_MMU_64 */
 }
 
+/* Put the paca pointer into r13 and SPRG_PACA */
+void setup_paca(struct paca_struct *new_paca)
+{
+        local_paca = new_paca;
+        mtspr(SPRN_SPRG_PACA, local_paca);
+#ifdef CONFIG_PPC_BOOK3E
+        mtspr(SPRN_SPRG_TLB_EXFRAME, local_paca->extlb);
+#endif
+}
+
 static int __initdata paca_size;
 
 void __init allocate_pacas(void)
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index 773424df828a..551f6713ff42 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -37,6 +37,7 @@
 #include <linux/kernel_stat.h>
 #include <linux/personality.h>
 #include <linux/random.h>
+#include <linux/hw_breakpoint.h>
 
 #include <asm/pgtable.h>
 #include <asm/uaccess.h>
@@ -462,14 +463,42 @@ struct task_struct *__switch_to(struct task_struct *prev,
 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
         switch_booke_debug_regs(&new->thread);
 #else
+/*
+ * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
+ * schedule DABR
+ */
+#ifndef CONFIG_HAVE_HW_BREAKPOINT
         if (unlikely(__get_cpu_var(current_dabr) != new->thread.dabr))
                 set_dabr(new->thread.dabr);
+#endif /* CONFIG_HAVE_HW_BREAKPOINT */
 #endif
 
 
         new_thread = &new->thread;
         old_thread = &current->thread;
 
+#if defined(CONFIG_PPC_BOOK3E_64)
+        /* XXX Current Book3E code doesn't deal with kernel side DBCR0,
+         * we always hold the user values, so we set it now.
+         *
+         * However, we ensure the kernel MSR:DE is appropriately cleared too
+         * to avoid spurrious single step exceptions in the kernel.
+         *
+         * This will have to change to merge with the ppc32 code at some point,
+         * but I don't like much what ppc32 is doing today so there's some
+         * thinking needed there
+         */
+        if ((new_thread->dbcr0 | old_thread->dbcr0) & DBCR0_IDM) {
+                u32 dbcr0;
+
+                mtmsr(mfmsr() & ~MSR_DE);
+                isync();
+                dbcr0 = mfspr(SPRN_DBCR0);
+                dbcr0 = (dbcr0 & DBCR0_EDM) | new_thread->dbcr0;
+                mtspr(SPRN_DBCR0, dbcr0);
+        }
+#endif /* CONFIG_PPC64_BOOK3E */
+
 #ifdef CONFIG_PPC64
         /*
          * Collect processor utilization data per process
@@ -642,7 +671,11 @@ void flush_thread(void)
 {
         discard_lazy_cpu_state();
 
+#ifdef CONFIG_HAVE_HW_BREAKPOINTS
+        flush_ptrace_hw_breakpoint(current);
+#else /* CONFIG_HAVE_HW_BREAKPOINTS */
         set_debug_reg_defaults(&current->thread);
+#endif /* CONFIG_HAVE_HW_BREAKPOINTS */
 }
 
 void
@@ -660,6 +693,9 @@ void prepare_to_copy(struct task_struct *tsk)
         flush_altivec_to_thread(current);
         flush_vsx_to_thread(current);
         flush_spe_to_thread(current);
+#ifdef CONFIG_HAVE_HW_BREAKPOINT
+        flush_ptrace_hw_breakpoint(tsk);
+#endif /* CONFIG_HAVE_HW_BREAKPOINT */
 }
 
 /*
diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c
index 3b6f8ae9b8cc..941ff4dbc567 100644
--- a/arch/powerpc/kernel/prom_init.c
+++ b/arch/powerpc/kernel/prom_init.c
@@ -311,6 +311,24 @@ static void __init prom_print_hex(unsigned long val)
         call_prom("write", 3, 1, _prom->stdout, buf, nibbles);
 }
 
+/* max number of decimal digits in an unsigned long */
+#define UL_DIGITS 21
+static void __init prom_print_dec(unsigned long val)
+{
+        int i, size;
+        char buf[UL_DIGITS+1];
+        struct prom_t *_prom = &RELOC(prom);
+
+        for (i = UL_DIGITS-1; i >= 0;  i--) {
+                buf[i] = (val % 10) + '0';
+                val = val/10;
+                if (val == 0)
+                        break;
+        }
+        /* shift stuff down */
+        size = UL_DIGITS - i;
+        call_prom("write", 3, 1, _prom->stdout, buf+i, size);
+}
 
 static void __init prom_printf(const char *format, ...)
 {
@@ -350,6 +368,14 @@ static void __init prom_printf(const char *format, ...)
                         v = va_arg(args, unsigned long);
                         prom_print_hex(v);
                         break;
+                case 'l':
+                        ++q;
+                        if (*q == 'u') { /* '%lu' */
+                                ++q;
+                                v = va_arg(args, unsigned long);
+                                prom_print_dec(v);
+                        }
+                        break;
                 }
         }
 }
@@ -835,11 +861,11 @@ static int __init prom_count_smt_threads(void)
                 if (plen == PROM_ERROR)
                         break;
                 plen >>= 2;
-                prom_debug("Found 0x%x smt threads per core\n", (unsigned long)plen);
+                prom_debug("Found %lu smt threads per core\n", (unsigned long)plen);
 
                 /* Sanity check */
                 if (plen < 1 || plen > 64) {
-                        prom_printf("Threads per core 0x%x out of bounds, assuming 1\n",
+                        prom_printf("Threads per core %lu out of bounds, assuming 1\n",
                                     (unsigned long)plen);
                         return 1;
                 }
@@ -869,12 +895,12 @@ static void __init prom_send_capabilities(void)
                 cores = (u32 *)PTRRELOC(&ibm_architecture_vec[IBM_ARCH_VEC_NRCORES_OFFSET]);
                 if (*cores != NR_CPUS) {
                         prom_printf("WARNING ! "
-                                    "ibm_architecture_vec structure inconsistent: 0x%x !\n",
+                                    "ibm_architecture_vec structure inconsistent: %lu!\n",
                                     *cores);
                 } else {
                         *cores = DIV_ROUND_UP(NR_CPUS, prom_count_smt_threads());
-                        prom_printf("Max number of cores passed to firmware: 0x%x\n",
-                                    (unsigned long)*cores);
+                        prom_printf("Max number of cores passed to firmware: %lu (NR_CPUS = %lu)\n",
+                                    *cores, NR_CPUS);
                 }
 
                 /* try calling the ibm,client-architecture-support method */
@@ -1482,7 +1508,7 @@ static void __init prom_hold_cpus(void)
                 reg = -1;
                 prom_getprop(node, "reg", &reg, sizeof(reg));
 
-                prom_debug("cpu hw idx   = 0x%x\n", reg);
+                prom_debug("cpu hw idx   = %lu\n", reg);
 
                 /* Init the acknowledge var which will be reset by
                  * the secondary cpu when it awakens from its OF
@@ -1492,7 +1518,7 @@ static void __init prom_hold_cpus(void)
 
                 if (reg != _prom->cpu) {
                         /* Primary Thread of non-boot cpu */
-                        prom_printf("starting cpu hw idx %x... ", reg);
+                        prom_printf("starting cpu hw idx %lu... ", reg);
                         call_prom("start-cpu", 3, 0, node,
                                   secondary_hold, reg);
 
@@ -1507,7 +1533,7 @@ static void __init prom_hold_cpus(void)
                 }
 #ifdef CONFIG_SMP
                 else
-                        prom_printf("boot cpu hw idx %x\n", reg);
+                        prom_printf("boot cpu hw idx %lu\n", reg);
 #endif /* CONFIG_SMP */
         }
 
@@ -2420,7 +2446,7 @@ static void __init prom_find_boot_cpu(void)
         prom_getprop(cpu_pkg, "reg", &getprop_rval, sizeof(getprop_rval));
         _prom->cpu = getprop_rval;
 
-        prom_debug("Booting CPU hw index = 0x%x\n", _prom->cpu);
+        prom_debug("Booting CPU hw index = %lu\n", _prom->cpu);
 }
 
 static void __init prom_check_initrd(unsigned long r3, unsigned long r4)
diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c
index 7a0c0199ea28..11f3cd9c832f 100644
--- a/arch/powerpc/kernel/ptrace.c
+++ b/arch/powerpc/kernel/ptrace.c
@@ -32,6 +32,8 @@
 #ifdef CONFIG_PPC32
 #include <linux/module.h>
 #endif
+#include <linux/hw_breakpoint.h>
+#include <linux/perf_event.h>
 
 #include <asm/uaccess.h>
 #include <asm/page.h>
@@ -866,9 +868,34 @@ void user_disable_single_step(struct task_struct *task)
         clear_tsk_thread_flag(task, TIF_SINGLESTEP);
 }
 
+#ifdef CONFIG_HAVE_HW_BREAKPOINT
+void ptrace_triggered(struct perf_event *bp, int nmi,
+                      struct perf_sample_data *data, struct pt_regs *regs)
+{
+        struct perf_event_attr attr;
+
+        /*
+         * Disable the breakpoint request here since ptrace has defined a
+         * one-shot behaviour for breakpoint exceptions in PPC64.
+         * The SIGTRAP signal is generated automatically for us in do_dabr().
+         * We don't have to do anything about that here
+         */
+        attr = bp->attr;
+        attr.disabled = true;
+        modify_user_hw_breakpoint(bp, &attr);
+}
+#endif /* CONFIG_HAVE_HW_BREAKPOINT */
+
 int ptrace_set_debugreg(struct task_struct *task, unsigned long addr,
                                unsigned long data)
 {
+#ifdef CONFIG_HAVE_HW_BREAKPOINT
+        int ret;
+        struct thread_struct *thread = &(task->thread);
+        struct perf_event *bp;
+        struct perf_event_attr attr;
+#endif /* CONFIG_HAVE_HW_BREAKPOINT */
+
         /* For ppc64 we support one DABR and no IABR's at the moment (ppc64).
          *  For embedded processors we support one DAC and no IAC's at the
          *  moment.
@@ -896,6 +923,43 @@ int ptrace_set_debugreg(struct task_struct *task, unsigned long addr,
         /* Ensure breakpoint translation bit is set */
         if (data && !(data & DABR_TRANSLATION))
                 return -EIO;
+#ifdef CONFIG_HAVE_HW_BREAKPOINT
+        bp = thread->ptrace_bps[0];
+        if ((!data) || !(data & (DABR_DATA_WRITE | DABR_DATA_READ))) {
+                if (bp) {
+                        unregister_hw_breakpoint(bp);
+                        thread->ptrace_bps[0] = NULL;
+                }
+                return 0;
+        }
+        if (bp) {
+                attr = bp->attr;
+                attr.bp_addr = data & ~HW_BREAKPOINT_ALIGN;
+                arch_bp_generic_fields(data &
+                                        (DABR_DATA_WRITE | DABR_DATA_READ),
+                                                        &attr.bp_type);
+                ret =  modify_user_hw_breakpoint(bp, &attr);
+                if (ret)
+                        return ret;
+                thread->ptrace_bps[0] = bp;
+                thread->dabr = data;
+                return 0;
+        }
+
+        /* Create a new breakpoint request if one doesn't exist already */
+        hw_breakpoint_init(&attr);
+        attr.bp_addr = data & ~HW_BREAKPOINT_ALIGN;
+        arch_bp_generic_fields(data & (DABR_DATA_WRITE | DABR_DATA_READ),
+                                                                &attr.bp_type);
+
+        thread->ptrace_bps[0] = bp = register_user_hw_breakpoint(&attr,
+                                                        ptrace_triggered, task);
+        if (IS_ERR(bp)) {
+                thread->ptrace_bps[0] = NULL;
+                return PTR_ERR(bp);
+        }
+
+#endif /* CONFIG_HAVE_HW_BREAKPOINT */
 
         /* Move contents to the DABR register */
         task->thread.dabr = data;
diff --git a/arch/powerpc/kernel/rtas.c b/arch/powerpc/kernel/rtas.c
index d0516dbee762..41048de3c6c3 100644
--- a/arch/powerpc/kernel/rtas.c
+++ b/arch/powerpc/kernel/rtas.c
@@ -47,14 +47,6 @@ struct rtas_t rtas = {
 };
 EXPORT_SYMBOL(rtas);
 
-struct rtas_suspend_me_data {
-        atomic_t working; /* number of cpus accessing this struct */
-        atomic_t done;
-        int token; /* ibm,suspend-me */
-        int error;
-        struct completion *complete; /* wait on this until working == 0 */
-};
-
 DEFINE_SPINLOCK(rtas_data_buf_lock);
 EXPORT_SYMBOL(rtas_data_buf_lock);
 
@@ -714,14 +706,53 @@ void rtas_os_term(char *str)
 
 static int ibm_suspend_me_token = RTAS_UNKNOWN_SERVICE;
 #ifdef CONFIG_PPC_PSERIES
-static void rtas_percpu_suspend_me(void *info)
+static int __rtas_suspend_last_cpu(struct rtas_suspend_me_data *data, int wake_when_done)
+{
+        u16 slb_size = mmu_slb_size;
+        int rc = H_MULTI_THREADS_ACTIVE;
+        int cpu;
+
+        slb_set_size(SLB_MIN_SIZE);
+        printk(KERN_DEBUG "calling ibm,suspend-me on cpu %i\n", smp_processor_id());
+
+        while (rc == H_MULTI_THREADS_ACTIVE && !atomic_read(&data->done) &&
+               !atomic_read(&data->error))
+                rc = rtas_call(data->token, 0, 1, NULL);
+
+        if (rc || atomic_read(&data->error)) {
+                printk(KERN_DEBUG "ibm,suspend-me returned %d\n", rc);
+                slb_set_size(slb_size);
+        }
+
+        if (atomic_read(&data->error))
+                rc = atomic_read(&data->error);
+
+        atomic_set(&data->error, rc);
+
+        if (wake_when_done) {
+                atomic_set(&data->done, 1);
+
+                for_each_online_cpu(cpu)
+                        plpar_hcall_norets(H_PROD, get_hard_smp_processor_id(cpu));
+        }
+
+        if (atomic_dec_return(&data->working) == 0)
+                complete(data->complete);
+
+        return rc;
+}
+
+int rtas_suspend_last_cpu(struct rtas_suspend_me_data *data)
+{
+        atomic_inc(&data->working);
+        return __rtas_suspend_last_cpu(data, 0);
+}
+
+static int __rtas_suspend_cpu(struct rtas_suspend_me_data *data, int wake_when_done)
 {
         long rc = H_SUCCESS;
         unsigned long msr_save;
-        u16 slb_size = mmu_slb_size;
         int cpu;
-        struct rtas_suspend_me_data *data =
-                (struct rtas_suspend_me_data *)info;
 
         atomic_inc(&data->working);
 
@@ -729,7 +760,7 @@ static void rtas_percpu_suspend_me(void *info)
         msr_save = mfmsr();
         mtmsr(msr_save & ~(MSR_EE));
 
-        while (rc == H_SUCCESS && !atomic_read(&data->done))
+        while (rc == H_SUCCESS && !atomic_read(&data->done) && !atomic_read(&data->error))
                 rc = plpar_hcall_norets(H_JOIN);
 
         mtmsr(msr_save);
@@ -741,33 +772,37 @@ static void rtas_percpu_suspend_me(void *info)
                 /* All other cpus are in H_JOIN, this cpu does
                  * the suspend.
                  */
-                slb_set_size(SLB_MIN_SIZE);
-                printk(KERN_DEBUG "calling ibm,suspend-me on cpu %i\n",
-                       smp_processor_id());
-                data->error = rtas_call(data->token, 0, 1, NULL);
-
-                if (data->error) {
-                        printk(KERN_DEBUG "ibm,suspend-me returned %d\n",
-                               data->error);
-                        slb_set_size(slb_size);
-                }
+                return __rtas_suspend_last_cpu(data, wake_when_done);
         } else {
                 printk(KERN_ERR "H_JOIN on cpu %i failed with rc = %ld\n",
                        smp_processor_id(), rc);
-                data->error = rc;
+                atomic_set(&data->error, rc);
         }
 
-        atomic_set(&data->done, 1);
+        if (wake_when_done) {
+                atomic_set(&data->done, 1);
 
-        /* This cpu did the suspend or got an error; in either case,
-         * we need to prod all other other cpus out of join state.
-         * Extra prods are harmless.
-         */
-        for_each_online_cpu(cpu)
-                plpar_hcall_norets(H_PROD, get_hard_smp_processor_id(cpu));
+                /* This cpu did the suspend or got an error; in either case,
+                 * we need to prod all other other cpus out of join state.
+                 * Extra prods are harmless.
+                 */
+                for_each_online_cpu(cpu)
+                        plpar_hcall_norets(H_PROD, get_hard_smp_processor_id(cpu));
+        }
 out:
         if (atomic_dec_return(&data->working) == 0)
                 complete(data->complete);
+        return rc;
+}
+
+int rtas_suspend_cpu(struct rtas_suspend_me_data *data)
+{
+        return __rtas_suspend_cpu(data, 0);
+}
+
+static void rtas_percpu_suspend_me(void *info)
+{
+        __rtas_suspend_cpu((struct rtas_suspend_me_data *)info, 1);
 }
 
 static int rtas_ibm_suspend_me(struct rtas_args *args)
@@ -802,22 +837,22 @@ static int rtas_ibm_suspend_me(struct rtas_args *args)
 
         atomic_set(&data.working, 0);
         atomic_set(&data.done, 0);
+        atomic_set(&data.error, 0);
         data.token = rtas_token("ibm,suspend-me");
-        data.error = 0;
         data.complete = &done;
 
         /* Call function on all CPUs.  One of us will make the
          * rtas call
          */
         if (on_each_cpu(rtas_percpu_suspend_me, &data, 0))
-                data.error = -EINVAL;
+                atomic_set(&data.error, -EINVAL);
 
         wait_for_completion(&done);
 
-        if (data.error != 0)
+        if (atomic_read(&data.error) != 0)
                 printk(KERN_ERR "Error doing global join\n");
 
-        return data.error;
+        return atomic_read(&data.error);
 }
 #else /* CONFIG_PPC_PSERIES */
 static int rtas_ibm_suspend_me(struct rtas_args *args)
diff --git a/arch/powerpc/kernel/setup-common.c b/arch/powerpc/kernel/setup-common.c
index b7e6c7e193ae..70decd8068ca 100644
--- a/arch/powerpc/kernel/setup-common.c
+++ b/arch/powerpc/kernel/setup-common.c
@@ -94,6 +94,10 @@ struct screen_info screen_info = {
         .orig_video_points = 16
 };
 
+/* Variables required to store legacy IO irq routing */
+int of_i8042_kbd_irq;
+int of_i8042_aux_irq;
+
 #ifdef __DO_IRQ_CANON
 /* XXX should go elsewhere eventually */
 int ppc_do_canonicalize_irqs;
@@ -575,6 +579,15 @@ int check_legacy_ioport(unsigned long base_port)
                         np = of_find_compatible_node(NULL, NULL, "pnpPNP,f03");
                 if (np) {
                         parent = of_get_parent(np);
+
+                        of_i8042_kbd_irq = irq_of_parse_and_map(parent, 0);
+                        if (!of_i8042_kbd_irq)
+                                of_i8042_kbd_irq = 1;
+
+                        of_i8042_aux_irq = irq_of_parse_and_map(parent, 1);
+                        if (!of_i8042_aux_irq)
+                                of_i8042_aux_irq = 12;
+
                         of_node_put(np);
                         np = parent;
                         break;
diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
index d135f93cb0f6..1bee4b68fa45 100644
--- a/arch/powerpc/kernel/setup_64.c
+++ b/arch/powerpc/kernel/setup_64.c
@@ -142,16 +142,6 @@ early_param("smt-enabled", early_smt_enabled);
 #define check_smt_enabled()
 #endif /* CONFIG_SMP */
 
-/* Put the paca pointer into r13 and SPRG_PACA */
-static void __init setup_paca(struct paca_struct *new_paca)
-{
-        local_paca = new_paca;
-        mtspr(SPRN_SPRG_PACA, local_paca);
-#ifdef CONFIG_PPC_BOOK3E
-        mtspr(SPRN_SPRG_TLB_EXFRAME, local_paca->extlb);
-#endif
-}
-
 /*
  * Early initialization entry point. This is called by head.S
  * with MMU translation disabled. We rely on the "feature" of
@@ -600,6 +590,9 @@ static int pcpu_cpu_distance(unsigned int from, unsigned int to)
                 return REMOTE_DISTANCE;
 }
 
+unsigned long __per_cpu_offset[NR_CPUS] __read_mostly;
+EXPORT_SYMBOL(__per_cpu_offset);
+
 void __init setup_per_cpu_areas(void)
 {
         const size_t dyn_size = PERCPU_MODULE_RESERVE + PERCPU_DYNAMIC_RESERVE;
@@ -624,8 +617,10 @@ void __init setup_per_cpu_areas(void)
                 panic("cannot initialize percpu area (err=%d)", rc);
 
         delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start;
-        for_each_possible_cpu(cpu)
-                paca[cpu].data_offset = delta + pcpu_unit_offsets[cpu];
+        for_each_possible_cpu(cpu) {
+                __per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu];
+                paca[cpu].data_offset = __per_cpu_offset[cpu];
+        }
 }
 #endif
 
diff --git a/arch/powerpc/kernel/signal.c b/arch/powerpc/kernel/signal.c
index a0afb555a7c9..7109f5b1baa8 100644
--- a/arch/powerpc/kernel/signal.c
+++ b/arch/powerpc/kernel/signal.c
@@ -11,6 +11,7 @@
 
 #include <linux/tracehook.h>
 #include <linux/signal.h>
+#include <asm/hw_breakpoint.h>
 #include <asm/uaccess.h>
 #include <asm/unistd.h>
 
@@ -149,6 +150,8 @@ static int do_signal_pending(sigset_t *oldset, struct pt_regs *regs)
         if (current->thread.dabr)
                 set_dabr(current->thread.dabr);
 #endif
+        /* Re-enable the breakpoints for the signal stack */
+        thread_change_pc(current, regs);
 
         if (is32) {
                 if (ka.sa.sa_flags & SA_SIGINFO)
diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
index 5c196d1086d9..a61b3ddd7bb3 100644
--- a/arch/powerpc/kernel/smp.c
+++ b/arch/powerpc/kernel/smp.c
@@ -288,8 +288,6 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
                         max_cpus = NR_CPUS;
         else
                 max_cpus = 1;
- 
-        smp_space_timers(max_cpus);
 
         for_each_possible_cpu(cpu)
                 if (cpu != boot_cpuid)
@@ -501,14 +499,6 @@ int __devinit start_secondary(void *unused)
         current->active_mm = &init_mm;
 
         smp_store_cpu_info(cpu);
-
-#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
-        /* Clear any pending timer interrupts */
-        mtspr(SPRN_TSR, TSR_ENW | TSR_WIS | TSR_DIS | TSR_FIS);
-
-        /* Enable decrementer interrupt */
-        mtspr(SPRN_TCR, TCR_DIE);
-#endif
         set_dec(tb_ticks_per_jiffy);
         preempt_disable();
         cpu_callin_map[cpu] = 1;
diff --git a/arch/powerpc/kernel/time.c b/arch/powerpc/kernel/time.c
index 0441bbdadbd1..ccb8759c8532 100644
--- a/arch/powerpc/kernel/time.c
+++ b/arch/powerpc/kernel/time.c
@@ -149,16 +149,6 @@ unsigned long tb_ticks_per_usec = 100; /* sane default */
 EXPORT_SYMBOL(tb_ticks_per_usec);
 unsigned long tb_ticks_per_sec;
 EXPORT_SYMBOL(tb_ticks_per_sec);        /* for cputime_t conversions */
-u64 tb_to_xs;
-unsigned tb_to_us;
-
-#define TICKLEN_SCALE   NTP_SCALE_SHIFT
-static u64 last_tick_len;       /* units are ns / 2^TICKLEN_SCALE */
-static u64 ticklen_to_xs;       /* 0.64 fraction */
-
-/* If last_tick_len corresponds to about 1/HZ seconds, then
-   last_tick_len << TICKLEN_SHIFT will be about 2^63. */
-#define TICKLEN_SHIFT   (63 - 30 - TICKLEN_SCALE + SHIFT_HZ)
 
 DEFINE_SPINLOCK(rtc_lock);
 EXPORT_SYMBOL_GPL(rtc_lock);
@@ -174,7 +164,6 @@ unsigned long ppc_proc_freq;
 EXPORT_SYMBOL(ppc_proc_freq);
 unsigned long ppc_tb_freq;
 
-static u64 tb_last_jiffy __cacheline_aligned_in_smp;
 static DEFINE_PER_CPU(u64, last_jiffy);
 
 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
@@ -423,30 +412,6 @@ void udelay(unsigned long usecs)
 }
 EXPORT_SYMBOL(udelay);
 
-static inline void update_gtod(u64 new_tb_stamp, u64 new_stamp_xsec,
-                               u64 new_tb_to_xs)
-{
-        /*
-         * tb_update_count is used to allow the userspace gettimeofday code
-         * to assure itself that it sees a consistent view of the tb_to_xs and
-         * stamp_xsec variables.  It reads the tb_update_count, then reads
-         * tb_to_xs and stamp_xsec and then reads tb_update_count again.  If
-         * the two values of tb_update_count match and are even then the
-         * tb_to_xs and stamp_xsec values are consistent.  If not, then it
-         * loops back and reads them again until this criteria is met.
-         * We expect the caller to have done the first increment of
-         * vdso_data->tb_update_count already.
-         */
-        vdso_data->tb_orig_stamp = new_tb_stamp;
-        vdso_data->stamp_xsec = new_stamp_xsec;
-        vdso_data->tb_to_xs = new_tb_to_xs;
-        vdso_data->wtom_clock_sec = wall_to_monotonic.tv_sec;
-        vdso_data->wtom_clock_nsec = wall_to_monotonic.tv_nsec;
-        vdso_data->stamp_xtime = xtime;
-        smp_wmb();
-        ++(vdso_data->tb_update_count);
-}
-
 #ifdef CONFIG_SMP
 unsigned long profile_pc(struct pt_regs *regs)
 {
@@ -470,7 +435,6 @@ EXPORT_SYMBOL(profile_pc);
 
 static int __init iSeries_tb_recal(void)
 {
-        struct div_result divres;
         unsigned long titan, tb;
 
         /* Make sure we only run on iSeries */
@@ -501,10 +465,7 @@ static int __init iSeries_tb_recal(void)
                                 tb_ticks_per_jiffy = new_tb_ticks_per_jiffy;
                                 tb_ticks_per_sec   = new_tb_ticks_per_sec;
                                 calc_cputime_factors();
-                                div128_by_32( XSEC_PER_SEC, 0, tb_ticks_per_sec, &divres );
-                                tb_to_xs = divres.result_low;
                                 vdso_data->tb_ticks_per_sec = tb_ticks_per_sec;
-                                vdso_data->tb_to_xs = tb_to_xs;
                                 setup_cputime_one_jiffy();
                         }
                         else {
@@ -667,27 +628,9 @@ void timer_interrupt(struct pt_regs * regs)
         trace_timer_interrupt_exit(regs);
 }
 
-void wakeup_decrementer(void)
-{
-        unsigned long ticks;
-
-        /*
-         * The timebase gets saved on sleep and restored on wakeup,
-         * so all we need to do is to reset the decrementer.
-         */
-        ticks = tb_ticks_since(__get_cpu_var(last_jiffy));
-        if (ticks < tb_ticks_per_jiffy)
-                ticks = tb_ticks_per_jiffy - ticks;
-        else
-                ticks = 1;
-        set_dec(ticks);
-}
-
 #ifdef CONFIG_SUSPEND
-void generic_suspend_disable_irqs(void)
+static void generic_suspend_disable_irqs(void)
 {
-        preempt_disable();
-
         /* Disable the decrementer, so that it doesn't interfere
          * with suspending.
          */
@@ -697,12 +640,9 @@ void generic_suspend_disable_irqs(void)
         set_dec(0x7fffffff);
 }
 
-void generic_suspend_enable_irqs(void)
+static void generic_suspend_enable_irqs(void)
 {
-        wakeup_decrementer();
-
         local_irq_enable();
-        preempt_enable();
 }
 
 /* Overrides the weak version in kernel/power/main.c */
@@ -722,23 +662,6 @@ void arch_suspend_enable_irqs(void)
 }
 #endif
 
-#ifdef CONFIG_SMP
-void __init smp_space_timers(unsigned int max_cpus)
-{
-        int i;
-        u64 previous_tb = per_cpu(last_jiffy, boot_cpuid);
-
-        /* make sure tb > per_cpu(last_jiffy, cpu) for all cpus always */
-        previous_tb -= tb_ticks_per_jiffy;
-
-        for_each_possible_cpu(i) {
-                if (i == boot_cpuid)
-                        continue;
-                per_cpu(last_jiffy, i) = previous_tb;
-        }
-}
-#endif
-
 /*
  * Scheduler clock - returns current time in nanosec units.
  *
@@ -873,10 +796,37 @@ static cycle_t timebase_read(struct clocksource *cs)
         return (cycle_t)get_tb();
 }
 
+static inline void update_gtod(u64 new_tb_stamp, u64 new_stamp_xsec,
+                               u64 new_tb_to_xs, struct timespec *now,
+                               u32 frac_sec)
+{
+        /*
+         * tb_update_count is used to allow the userspace gettimeofday code
+         * to assure itself that it sees a consistent view of the tb_to_xs and
+         * stamp_xsec variables.  It reads the tb_update_count, then reads
+         * tb_to_xs and stamp_xsec and then reads tb_update_count again.  If
+         * the two values of tb_update_count match and are even then the
+         * tb_to_xs and stamp_xsec values are consistent.  If not, then it
+         * loops back and reads them again until this criteria is met.
+         * We expect the caller to have done the first increment of
+         * vdso_data->tb_update_count already.
+         */
+        vdso_data->tb_orig_stamp = new_tb_stamp;
+        vdso_data->stamp_xsec = new_stamp_xsec;
+        vdso_data->tb_to_xs = new_tb_to_xs;
+        vdso_data->wtom_clock_sec = wall_to_monotonic.tv_sec;
+        vdso_data->wtom_clock_nsec = wall_to_monotonic.tv_nsec;
+        vdso_data->stamp_xtime = *now;
+        vdso_data->stamp_sec_fraction = frac_sec;
+        smp_wmb();
+        ++(vdso_data->tb_update_count);
+}
+
 void update_vsyscall(struct timespec *wall_time, struct clocksource *clock,
                      u32 mult)
 {
         u64 t2x, stamp_xsec;
+        u32 frac_sec;
 
         if (clock != &clocksource_timebase)
                 return;
@@ -888,10 +838,14 @@ void update_vsyscall(struct timespec *wall_time, struct clocksource *clock,
         /* XXX this assumes clock->shift == 22 */
         /* 4611686018 ~= 2^(20+64-22) / 1e9 */
         t2x = (u64) mult * 4611686018ULL;
-        stamp_xsec = (u64) xtime.tv_nsec * XSEC_PER_SEC;
+        stamp_xsec = (u64) wall_time->tv_nsec * XSEC_PER_SEC;
         do_div(stamp_xsec, 1000000000);
-        stamp_xsec += (u64) xtime.tv_sec * XSEC_PER_SEC;
-        update_gtod(clock->cycle_last, stamp_xsec, t2x);
+        stamp_xsec += (u64) wall_time->tv_sec * XSEC_PER_SEC;
+
+        BUG_ON(wall_time->tv_nsec >= NSEC_PER_SEC);
+        /* this is tv_nsec / 1e9 as a 0.32 fraction */
+        frac_sec = ((u64) wall_time->tv_nsec * 18446744073ULL) >> 32;
+        update_gtod(clock->cycle_last, stamp_xsec, t2x, wall_time, frac_sec);
 }
 
 void update_vsyscall_tz(void)
@@ -1007,15 +961,13 @@ void secondary_cpu_time_init(void)
 /* This function is only called on the boot processor */
 void __init time_init(void)
 {
-        unsigned long flags;
         struct div_result res;
-        u64 scale, x;
+        u64 scale;
         unsigned shift;
 
         if (__USE_RTC()) {
                 /* 601 processor: dec counts down by 128 every 128ns */
                 ppc_tb_freq = 1000000000;
-                tb_last_jiffy = get_rtcl();
         } else {
                 /* Normal PowerPC with timebase register */
                 ppc_md.calibrate_decr();
@@ -1023,50 +975,15 @@ void __init time_init(void)
                        ppc_tb_freq / 1000000, ppc_tb_freq % 1000000);
                 printk(KERN_DEBUG "time_init: processor frequency   = %lu.%.6lu MHz\n",
                        ppc_proc_freq / 1000000, ppc_proc_freq % 1000000);
-                tb_last_jiffy = get_tb();
         }
 
         tb_ticks_per_jiffy = ppc_tb_freq / HZ;
         tb_ticks_per_sec = ppc_tb_freq;
         tb_ticks_per_usec = ppc_tb_freq / 1000000;
-        tb_to_us = mulhwu_scale_factor(ppc_tb_freq, 1000000);
         calc_cputime_factors();
         setup_cputime_one_jiffy();
 
         /*
-         * Calculate the length of each tick in ns.  It will not be
-         * exactly 1e9/HZ unless ppc_tb_freq is divisible by HZ.
-         * We compute 1e9 * tb_ticks_per_jiffy / ppc_tb_freq,
-         * rounded up.
-         */
-        x = (u64) NSEC_PER_SEC * tb_ticks_per_jiffy + ppc_tb_freq - 1;
-        do_div(x, ppc_tb_freq);
-        tick_nsec = x;
-        last_tick_len = x << TICKLEN_SCALE;
-
-        /*
-         * Compute ticklen_to_xs, which is a factor which gets multiplied
-         * by (last_tick_len << TICKLEN_SHIFT) to get a tb_to_xs value.
-         * It is computed as:
-         * ticklen_to_xs = 2^N / (tb_ticks_per_jiffy * 1e9)
-         * where N = 64 + 20 - TICKLEN_SCALE - TICKLEN_SHIFT
-         * which turns out to be N = 51 - SHIFT_HZ.
-         * This gives the result as a 0.64 fixed-point fraction.
-         * That value is reduced by an offset amounting to 1 xsec per
-         * 2^31 timebase ticks to avoid problems with time going backwards
-         * by 1 xsec when we do timer_recalc_offset due to losing the
-         * fractional xsec.  That offset is equal to ppc_tb_freq/2^51
-         * since there are 2^20 xsec in a second.
-         */
-        div128_by_32((1ULL << 51) - ppc_tb_freq, 0,
-                     tb_ticks_per_jiffy << SHIFT_HZ, &res);
-        div128_by_32(res.result_high, res.result_low, NSEC_PER_SEC, &res);
-        ticklen_to_xs = res.result_low;
-
-        /* Compute tb_to_xs from tick_nsec */
-        tb_to_xs = mulhdu(last_tick_len << TICKLEN_SHIFT, ticklen_to_xs);
-
-        /*
          * Compute scale factor for sched_clock.
          * The calibrate_decr() function has set tb_ticks_per_sec,
          * which is the timebase frequency.
@@ -1087,21 +1004,14 @@ void __init time_init(void)
         /* Save the current timebase to pretty up CONFIG_PRINTK_TIME */
         boot_tb = get_tb_or_rtc();
 
-        write_seqlock_irqsave(&xtime_lock, flags);
-
         /* If platform provided a timezone (pmac), we correct the time */
         if (timezone_offset) {
                 sys_tz.tz_minuteswest = -timezone_offset / 60;
                 sys_tz.tz_dsttime = 0;
         }
 
-        vdso_data->tb_orig_stamp = tb_last_jiffy;
         vdso_data->tb_update_count = 0;
         vdso_data->tb_ticks_per_sec = tb_ticks_per_sec;
-        vdso_data->stamp_xsec = (u64) xtime.tv_sec * XSEC_PER_SEC;
-        vdso_data->tb_to_xs = tb_to_xs;
-
-        write_sequnlock_irqrestore(&xtime_lock, flags);
 
         /* Start the decrementer on CPUs that have manual control
          * such as BookE
@@ -1195,39 +1105,6 @@ void to_tm(int tim, struct rtc_time * tm)
         GregorianDay(tm);
 }
 
-/* Auxiliary function to compute scaling factors */
-/* Actually the choice of a timebase running at 1/4 the of the bus
- * frequency giving resolution of a few tens of nanoseconds is quite nice.
- * It makes this computation very precise (27-28 bits typically) which
- * is optimistic considering the stability of most processor clock
- * oscillators and the precision with which the timebase frequency
- * is measured but does not harm.
- */
-unsigned mulhwu_scale_factor(unsigned inscale, unsigned outscale)
-{
-        unsigned mlt=0, tmp, err;
-        /* No concern for performance, it's done once: use a stupid
-         * but safe and compact method to find the multiplier.
-         */
-  
-        for (tmp = 1U<<31; tmp != 0; tmp >>= 1) {
-                if (mulhwu(inscale, mlt|tmp) < outscale)
-                        mlt |= tmp;
-        }
-  
-        /* We might still be off by 1 for the best approximation.
-         * A side effect of this is that if outscale is too large
-         * the returned value will be zero.
-         * Many corner cases have been checked and seem to work,
-         * some might have been forgotten in the test however.
-         */
-  
-        err = inscale * (mlt+1);
-        if (err <= inscale/2)
-                mlt++;
-        return mlt;
-}
-
 /*
  * Divide a 128-bit dividend by a 32-bit divisor, leaving a 128 bit
  * result.
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index 25fc33984c2b..a45a63c3a0c7 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -55,9 +55,6 @@
 #endif
 #include <asm/kexec.h>
 #include <asm/ppc-opcode.h>
-#ifdef CONFIG_FSL_BOOKE
-#include <asm/dbell.h>
-#endif
 
 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
 int (*__debugger)(struct pt_regs *regs) __read_mostly;
@@ -688,7 +685,7 @@ void RunModeException(struct pt_regs *regs)
 
 void __kprobes single_step_exception(struct pt_regs *regs)
 {
-        regs->msr &= ~(MSR_SE | MSR_BE);  /* Turn off 'trace' bits */
+        clear_single_step(regs);
 
         if (notify_die(DIE_SSTEP, "single_step", regs, 5,
                                         5, SIGTRAP) == NOTIFY_STOP)
@@ -707,10 +704,8 @@ void __kprobes single_step_exception(struct pt_regs *regs)
  */
 static void emulate_single_step(struct pt_regs *regs)
 {
-        if (single_stepping(regs)) {
-                clear_single_step(regs);
-                _exception(SIGTRAP, regs, TRAP_TRACE, 0);
-        }
+        if (single_stepping(regs))
+                single_step_exception(regs);
 }
 
 static inline int __parse_fpscr(unsigned long fpscr)
@@ -1344,24 +1339,6 @@ void vsx_assist_exception(struct pt_regs *regs)
 #endif /* CONFIG_VSX */
 
 #ifdef CONFIG_FSL_BOOKE
-
-void doorbell_exception(struct pt_regs *regs)
-{
-#ifdef CONFIG_SMP
-        int cpu = smp_processor_id();
-        int msg;
-
-        if (num_online_cpus() < 2)
-                return;
-
-        for (msg = 0; msg < 4; msg++)
-                if (test_and_clear_bit(msg, &dbell_smp_message[cpu]))
-                        smp_message_recv(msg);
-#else
-        printk(KERN_WARNING "Received doorbell on non-smp system\n");
-#endif
-}
-
 void CacheLockingException(struct pt_regs *regs, unsigned long address,
                            unsigned long error_code)
 {
diff --git a/arch/powerpc/kernel/vdso32/gettimeofday.S b/arch/powerpc/kernel/vdso32/gettimeofday.S
index ee038d4bf252..4ee09ee2e836 100644
--- a/arch/powerpc/kernel/vdso32/gettimeofday.S
+++ b/arch/powerpc/kernel/vdso32/gettimeofday.S
@@ -19,8 +19,10 @@
 /* Offset for the low 32-bit part of a field of long type */
 #ifdef CONFIG_PPC64
 #define LOPART  4
+#define TSPEC_TV_SEC    TSPC64_TV_SEC+LOPART
 #else
 #define LOPART  0
+#define TSPEC_TV_SEC    TSPC32_TV_SEC
 #endif
 
         .text
@@ -41,23 +43,11 @@ V_FUNCTION_BEGIN(__kernel_gettimeofday)
         mr      r9, r3                  /* datapage ptr in r9 */
         cmplwi  r10,0                   /* check if tv is NULL */
         beq     3f
-        bl      __do_get_xsec@local     /* get xsec from tb & kernel */
-        bne-    2f                      /* out of line -> do syscall */
-
-        /* seconds are xsec >> 20 */
-        rlwinm  r5,r4,12,20,31
-        rlwimi  r5,r3,12,0,19
-        stw     r5,TVAL32_TV_SEC(r10)
-
-        /* get remaining xsec and convert to usec. we scale
-         * up remaining xsec by 12 bits and get the top 32 bits
-         * of the multiplication
-         */
-        rlwinm  r5,r4,12,0,19
-        lis     r6,1000000@h
-        ori     r6,r6,1000000@l
-        mulhwu  r5,r5,r6
-        stw     r5,TVAL32_TV_USEC(r10)
+        lis     r7,1000000@ha           /* load up USEC_PER_SEC */
+        addi    r7,r7,1000000@l         /* so we get microseconds in r4 */
+        bl      __do_get_tspec@local    /* get sec/usec from tb & kernel */
+        stw     r3,TVAL32_TV_SEC(r10)
+        stw     r4,TVAL32_TV_USEC(r10)
 
 3:      cmplwi  r11,0                   /* check if tz is NULL */
         beq     1f
@@ -70,14 +60,6 @@ V_FUNCTION_BEGIN(__kernel_gettimeofday)
         crclr   cr0*4+so
         li      r3,0
         blr
-
-2:
-        mtlr    r12
-        mr      r3,r10
-        mr      r4,r11
-        li      r0,__NR_gettimeofday
-        sc
-        blr
   .cfi_endproc
 V_FUNCTION_END(__kernel_gettimeofday)
 
@@ -100,7 +82,8 @@ V_FUNCTION_BEGIN(__kernel_clock_gettime)
         mr      r11,r4                  /* r11 saves tp */
         bl      __get_datapage@local    /* get data page */
         mr      r9,r3                   /* datapage ptr in r9 */
-
+        lis     r7,NSEC_PER_SEC@h       /* want nanoseconds */
+        ori     r7,r7,NSEC_PER_SEC@l
 50:     bl      __do_get_tspec@local    /* get sec/nsec from tb & kernel */
         bne     cr1,80f                 /* not monotonic -> all done */
 
@@ -198,83 +181,12 @@ V_FUNCTION_END(__kernel_clock_getres)
 
 
 /*
- * This is the core of gettimeofday() & friends, it returns the xsec
- * value in r3 & r4 and expects the datapage ptr (non clobbered)
- * in r9. clobbers r0,r4,r5,r6,r7,r8.
- * When returning, r8 contains the counter value that can be reused
- * by the monotonic clock implementation
- */
-__do_get_xsec:
-  .cfi_startproc
-        /* Check for update count & load values. We use the low
-         * order 32 bits of the update count
-         */
-1:      lwz     r8,(CFG_TB_UPDATE_COUNT+LOPART)(r9)
-        andi.   r0,r8,1                 /* pending update ? loop */
-        bne-    1b
-        xor     r0,r8,r8                /* create dependency */
-        add     r9,r9,r0
-
-        /* Load orig stamp (offset to TB) */
-        lwz     r5,CFG_TB_ORIG_STAMP(r9)
-        lwz     r6,(CFG_TB_ORIG_STAMP+4)(r9)
-
-        /* Get a stable TB value */
-2:      mftbu   r3
-        mftbl   r4
-        mftbu   r0
-        cmpl    cr0,r3,r0
-        bne-    2b
-
-        /* Substract tb orig stamp. If the high part is non-zero, we jump to
-         * the slow path which call the syscall.
-         * If it's ok, then we have our 32 bits tb_ticks value in r7
-         */
-        subfc   r7,r6,r4
-        subfe.  r0,r5,r3
-        bne-    3f
-
-        /* Load scale factor & do multiplication */
-        lwz     r5,CFG_TB_TO_XS(r9)     /* load values */
-        lwz     r6,(CFG_TB_TO_XS+4)(r9)
-        mulhwu  r4,r7,r5
-        mulhwu  r6,r7,r6
-        mullw   r0,r7,r5
-        addc    r6,r6,r0
-
-        /* At this point, we have the scaled xsec value in r4 + XER:CA
-         * we load & add the stamp since epoch
-         */
-        lwz     r5,CFG_STAMP_XSEC(r9)
-        lwz     r6,(CFG_STAMP_XSEC+4)(r9)
-        adde    r4,r4,r6
-        addze   r3,r5
-
-        /* We now have our result in r3,r4. We create a fake dependency
-         * on that result and re-check the counter
-         */
-        or      r6,r4,r3
-        xor     r0,r6,r6
-        add     r9,r9,r0
-        lwz     r0,(CFG_TB_UPDATE_COUNT+LOPART)(r9)
-        cmpl    cr0,r8,r0               /* check if updated */
-        bne-    1b
-
-        /* Warning ! The caller expects CR:EQ to be set to indicate a
-         * successful calculation (so it won't fallback to the syscall
-         * method). We have overriden that CR bit in the counter check,
-         * but fortunately, the loop exit condition _is_ CR:EQ set, so
-         * we can exit safely here. If you change this code, be careful
-         * of that side effect.
-         */
-3:      blr
-  .cfi_endproc
-
-/*
- * This is the core of clock_gettime(), it returns the current
- * time in seconds and nanoseconds in r3 and r4.
+ * This is the core of clock_gettime() and gettimeofday(),
+ * it returns the current time in r3 (seconds) and r4.
+ * On entry, r7 gives the resolution of r4, either USEC_PER_SEC
+ * or NSEC_PER_SEC, giving r4 in microseconds or nanoseconds.
  * It expects the datapage ptr in r9 and doesn't clobber it.
- * It clobbers r0, r5, r6, r10 and returns NSEC_PER_SEC in r7.
+ * It clobbers r0, r5 and r6.
  * On return, r8 contains the counter value that can be reused.
  * This clobbers cr0 but not any other cr field.
  */
@@ -297,70 +209,58 @@ __do_get_tspec:
 2:      mftbu   r3
         mftbl   r4
         mftbu   r0
-        cmpl    cr0,r3,r0
+        cmplw   cr0,r3,r0
         bne-    2b
 
         /* Subtract tb orig stamp and shift left 12 bits.
          */
-        subfc   r7,r6,r4
+        subfc   r4,r6,r4
         subfe   r0,r5,r3
         slwi    r0,r0,12
-        rlwimi. r0,r7,12,20,31
-        slwi    r7,r7,12
+        rlwimi. r0,r4,12,20,31
+        slwi    r4,r4,12
 
-        /* Load scale factor & do multiplication */
+        /*
+         * Load scale factor & do multiplication.
+         * We only use the high 32 bits of the tb_to_xs value.
+         * Even with a 1GHz timebase clock, the high 32 bits of
+         * tb_to_xs will be at least 4 million, so the error from
+         * ignoring the low 32 bits will be no more than 0.25ppm.
+         * The error will just make the clock run very very slightly
+         * slow until the next time the kernel updates the VDSO data,
+         * at which point the clock will catch up to the kernel's value,
+         * so there is no long-term error accumulation.
+         */
         lwz     r5,CFG_TB_TO_XS(r9)     /* load values */
-        lwz     r6,(CFG_TB_TO_XS+4)(r9)
-        mulhwu  r3,r7,r6
-        mullw   r10,r7,r5
-        mulhwu  r4,r7,r5
-        addc    r10,r3,r10
+        mulhwu  r4,r4,r5
         li      r3,0
 
         beq+    4f                      /* skip high part computation if 0 */
         mulhwu  r3,r0,r5
-        mullw   r7,r0,r5
-        mulhwu  r5,r0,r6
-        mullw   r6,r0,r6
-        adde    r4,r4,r7
-        addze   r3,r3
+        mullw   r5,r0,r5
         addc    r4,r4,r5
         addze   r3,r3
-        addc    r10,r10,r6
-
-4:      addze   r4,r4                   /* add in carry */
-        lis     r7,NSEC_PER_SEC@h
-        ori     r7,r7,NSEC_PER_SEC@l
-        mulhwu  r4,r4,r7                /* convert to nanoseconds */
-
-        /* At this point, we have seconds & nanoseconds since the xtime
-         * stamp in r3+CA and r4.  Load & add the xtime stamp.
+4:
+        /* At this point, we have seconds since the xtime stamp
+         * as a 32.32 fixed-point number in r3 and r4.
+         * Load & add the xtime stamp.
          */
-#ifdef CONFIG_PPC64
-        lwz     r5,STAMP_XTIME+TSPC64_TV_SEC+LOPART(r9)
-        lwz     r6,STAMP_XTIME+TSPC64_TV_NSEC+LOPART(r9)
-#else
-        lwz     r5,STAMP_XTIME+TSPC32_TV_SEC(r9)
-        lwz     r6,STAMP_XTIME+TSPC32_TV_NSEC(r9)
-#endif
-        add     r4,r4,r6
+        lwz     r5,STAMP_XTIME+TSPEC_TV_SEC(r9)
+        lwz     r6,STAMP_SEC_FRAC(r9)
+        addc    r4,r4,r6
         adde    r3,r3,r5
 
-        /* We now have our result in r3,r4. We create a fake dependency
-         * on that result and re-check the counter
+        /* We create a fake dependency on the result in r3/r4
+         * and re-check the counter
          */
         or      r6,r4,r3
         xor     r0,r6,r6
         add     r9,r9,r0
         lwz     r0,(CFG_TB_UPDATE_COUNT+LOPART)(r9)
-        cmpl    cr0,r8,r0               /* check if updated */
+        cmplw   cr0,r8,r0               /* check if updated */
         bne-    1b
 
-        /* check for nanosecond overflow and adjust if necessary */
-        cmpw    r4,r7
-        bltlr                           /* all done if no overflow */
-        subf    r4,r7,r4                /* adjust if overflow */
-        addi    r3,r3,1
+        mulhwu  r4,r4,r7                /* convert to micro or nanoseconds */
 
         blr
   .cfi_endproc
diff --git a/arch/powerpc/kernel/vdso64/gettimeofday.S b/arch/powerpc/kernel/vdso64/gettimeofday.S
index 262cd5857a56..e97a9a0dc4ac 100644
--- a/arch/powerpc/kernel/vdso64/gettimeofday.S
+++ b/arch/powerpc/kernel/vdso64/gettimeofday.S
@@ -33,18 +33,11 @@ V_FUNCTION_BEGIN(__kernel_gettimeofday)
         bl      V_LOCAL_FUNC(__get_datapage)    /* get data page */
         cmpldi  r11,0                   /* check if tv is NULL */
         beq     2f
-        bl      V_LOCAL_FUNC(__do_get_xsec)     /* get xsec from tb & kernel */
-        lis     r7,15                   /* r7 = 1000000 = USEC_PER_SEC */
-        ori     r7,r7,16960
-        rldicl  r5,r4,44,20             /* r5 = sec = xsec / XSEC_PER_SEC */
-        rldicr  r6,r5,20,43             /* r6 = sec * XSEC_PER_SEC */
-        std     r5,TVAL64_TV_SEC(r11)   /* store sec in tv */
-        subf    r0,r6,r4                /* r0 = xsec = (xsec - r6) */
-        mulld   r0,r0,r7                /* usec = (xsec * USEC_PER_SEC) /
-                                         * XSEC_PER_SEC
-                                         */
-        rldicl  r0,r0,44,20
-        std     r0,TVAL64_TV_USEC(r11)  /* store usec in tv */
+        lis     r7,1000000@ha           /* load up USEC_PER_SEC */
+        addi    r7,r7,1000000@l
+        bl      V_LOCAL_FUNC(__do_get_tspec) /* get sec/us from tb & kernel */
+        std     r4,TVAL64_TV_SEC(r11)   /* store sec in tv */
+        std     r5,TVAL64_TV_USEC(r11)  /* store usec in tv */
 2:      cmpldi  r10,0                   /* check if tz is NULL */
         beq     1f
         lwz     r4,CFG_TZ_MINUTEWEST(r3)/* fill tz */
@@ -77,6 +70,8 @@ V_FUNCTION_BEGIN(__kernel_clock_gettime)
   .cfi_register lr,r12
         mr      r11,r4                  /* r11 saves tp */
         bl      V_LOCAL_FUNC(__get_datapage)    /* get data page */
+        lis     r7,NSEC_PER_SEC@h       /* want nanoseconds */
+        ori     r7,r7,NSEC_PER_SEC@l
 50:     bl      V_LOCAL_FUNC(__do_get_tspec)    /* get time from tb & kernel */
         bne     cr1,80f                 /* if not monotonic, all done */
 
@@ -171,49 +166,12 @@ V_FUNCTION_END(__kernel_clock_getres)
 
 
 /*
- * This is the core of gettimeofday(), it returns the xsec
- * value in r4 and expects the datapage ptr (non clobbered)
- * in r3. clobbers r0,r4,r5,r6,r7,r8
- * When returning, r8 contains the counter value that can be reused
- */
-V_FUNCTION_BEGIN(__do_get_xsec)
-  .cfi_startproc
-        /* check for update count & load values */
-1:      ld      r8,CFG_TB_UPDATE_COUNT(r3)
-        andi.   r0,r8,1                 /* pending update ? loop */
-        bne-    1b
-        xor     r0,r8,r8                /* create dependency */
-        add     r3,r3,r0
-
-        /* Get TB & offset it. We use the MFTB macro which will generate
-         * workaround code for Cell.
-         */
-        MFTB(r7)
-        ld      r9,CFG_TB_ORIG_STAMP(r3)
-        subf    r7,r9,r7
-
-        /* Scale result */
-        ld      r5,CFG_TB_TO_XS(r3)
-        mulhdu  r7,r7,r5
-
-        /* Add stamp since epoch */
-        ld      r6,CFG_STAMP_XSEC(r3)
-        add     r4,r6,r7
-
-        xor     r0,r4,r4
-        add     r3,r3,r0
-        ld      r0,CFG_TB_UPDATE_COUNT(r3)
-        cmpld   cr0,r0,r8               /* check if updated */
-        bne-    1b
-        blr
-  .cfi_endproc
-V_FUNCTION_END(__do_get_xsec)
-
-/*
- * This is the core of clock_gettime(), it returns the current
- * time in seconds and nanoseconds in r4 and r5.
+ * This is the core of clock_gettime() and gettimeofday(),
+ * it returns the current time in r4 (seconds) and r5.
+ * On entry, r7 gives the resolution of r5, either USEC_PER_SEC
+ * or NSEC_PER_SEC, giving r5 in microseconds or nanoseconds.
  * It expects the datapage ptr in r3 and doesn't clobber it.
- * It clobbers r0 and r6 and returns NSEC_PER_SEC in r7.
+ * It clobbers r0, r6 and r9.
  * On return, r8 contains the counter value that can be reused.
  * This clobbers cr0 but not any other cr field.
  */
@@ -229,18 +187,18 @@ V_FUNCTION_BEGIN(__do_get_tspec)
         /* Get TB & offset it. We use the MFTB macro which will generate
          * workaround code for Cell.
          */
-        MFTB(r7)
+        MFTB(r6)
         ld      r9,CFG_TB_ORIG_STAMP(r3)
-        subf    r7,r9,r7
+        subf    r6,r9,r6
 
         /* Scale result */
         ld      r5,CFG_TB_TO_XS(r3)
-        sldi    r7,r7,12                /* compute time since stamp_xtime */
-        mulhdu  r6,r7,r5                /* in units of 2^-32 seconds */
+        sldi    r6,r6,12                /* compute time since stamp_xtime */
+        mulhdu  r6,r6,r5                /* in units of 2^-32 seconds */
 
         /* Add stamp since epoch */
         ld      r4,STAMP_XTIME+TSPC64_TV_SEC(r3)
-        ld      r5,STAMP_XTIME+TSPC64_TV_NSEC(r3)
+        lwz     r5,STAMP_SEC_FRAC(r3)
         or      r0,r4,r5
         or      r0,r0,r6
         xor     r0,r0,r0
@@ -250,17 +208,11 @@ V_FUNCTION_BEGIN(__do_get_tspec)
         bne-    1b                      /* reload if so */
 
         /* convert to seconds & nanoseconds and add to stamp */
-        lis     r7,NSEC_PER_SEC@h
-        ori     r7,r7,NSEC_PER_SEC@l
-        mulhwu  r0,r6,r7                /* compute nanoseconds and */
+        add     r6,r6,r5                /* add on fractional seconds of xtime */
+        mulhwu  r5,r6,r7                /* compute micro or nanoseconds and */
         srdi    r6,r6,32                /* seconds since stamp_xtime */
-        clrldi  r0,r0,32
-        add     r5,r5,r0                /* add nanoseconds together */
-        cmpd    r5,r7                   /* overflow? */
+        clrldi  r5,r5,32
         add     r4,r4,r6
-        bltlr                           /* all done if no overflow */
-        subf    r5,r7,r5                /* if overflow, adjust */
-        addi    r4,r4,1
         blr
   .cfi_endproc
 V_FUNCTION_END(__do_get_tspec)
diff --git a/arch/powerpc/kvm/timing.c b/arch/powerpc/kvm/timing.c
index 70378551c0cc..46fa04f12a9b 100644
--- a/arch/powerpc/kvm/timing.c
+++ b/arch/powerpc/kvm/timing.c
@@ -182,7 +182,7 @@ static ssize_t kvmppc_exit_timing_write(struct file *file,
         }
 
         if (c == 'c') {
-                struct seq_file *seqf = (struct seq_file *)file->private_data;
+                struct seq_file *seqf = file->private_data;
                 struct kvm_vcpu *vcpu = seqf->private;
                 /* Write does not affect our buffers previously generated with
                  * show. seq_file is locked here to prevent races of init with
diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile
index 111da1c03a11..5bb89c828070 100644
--- a/arch/powerpc/lib/Makefile
+++ b/arch/powerpc/lib/Makefile
@@ -18,8 +18,9 @@ obj-$(CONFIG_HAS_IOMEM)	+= devres.o
 
 obj-$(CONFIG_PPC64)     += copypage_64.o copyuser_64.o \
                            memcpy_64.o usercopy_64.o mem_64.o string.o
-obj-$(CONFIG_XMON)      += sstep.o
-obj-$(CONFIG_KPROBES)   += sstep.o
+obj-$(CONFIG_XMON)      += sstep.o ldstfp.o
+obj-$(CONFIG_KPROBES)   += sstep.o ldstfp.o
+obj-$(CONFIG_HAVE_HW_BREAKPOINT)        += sstep.o ldstfp.o
 
 ifeq ($(CONFIG_PPC64),y)
 obj-$(CONFIG_SMP)       += locks.o
diff --git a/arch/powerpc/lib/ldstfp.S b/arch/powerpc/lib/ldstfp.S
new file mode 100644
index 000000000000..f6448636baf5
--- /dev/null
+++ b/arch/powerpc/lib/ldstfp.S
@@ -0,0 +1,375 @@
+/*
+ * Floating-point, VMX/Altivec and VSX loads and stores
+ * for use in instruction emulation.
+ *
+ * Copyright 2010 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  as published by the Free Software Foundation; either version
+ *  2 of the License, or (at your option) any later version.
+ */
+
+#include <asm/processor.h>
+#include <asm/ppc_asm.h>
+#include <asm/ppc-opcode.h>
+#include <asm/reg.h>
+#include <asm/asm-offsets.h>
+#include <linux/errno.h>
+
+#define STKFRM  (PPC_MIN_STKFRM + 16)
+
+        .macro  extab   instr,handler
+        .section __ex_table,"a"
+        PPC_LONG \instr,\handler
+        .previous
+        .endm
+
+        .macro  inst32  op
+reg = 0
+        .rept   32
+20:     \op     reg,0,r4
+        b       3f
+        extab   20b,99f
+reg = reg + 1
+        .endr
+        .endm
+
+/* Get the contents of frN into fr0; N is in r3. */
+_GLOBAL(get_fpr)
+        mflr    r0
+        rlwinm  r3,r3,3,0xf8
+        bcl     20,31,1f
+        blr                     /* fr0 is already in fr0 */
+        nop
+reg = 1
+        .rept   31
+        fmr     fr0,reg
+        blr
+reg = reg + 1
+        .endr
+1:      mflr    r5
+        add     r5,r3,r5
+        mtctr   r5
+        mtlr    r0
+        bctr
+
+/* Put the contents of fr0 into frN; N is in r3. */
+_GLOBAL(put_fpr)
+        mflr    r0
+        rlwinm  r3,r3,3,0xf8
+        bcl     20,31,1f
+        blr                     /* fr0 is already in fr0 */
+        nop
+reg = 1
+        .rept   31
+        fmr     reg,fr0
+        blr
+reg = reg + 1
+        .endr
+1:      mflr    r5
+        add     r5,r3,r5
+        mtctr   r5
+        mtlr    r0
+        bctr
+
+/* Load FP reg N from float at *p.  N is in r3, p in r4. */
+_GLOBAL(do_lfs)
+        PPC_STLU r1,-STKFRM(r1)
+        mflr    r0
+        PPC_STL r0,STKFRM+PPC_LR_STKOFF(r1)
+        mfmsr   r6
+        ori     r7,r6,MSR_FP
+        cmpwi   cr7,r3,0
+        mtmsrd  r7
+        isync
+        beq     cr7,1f
+        stfd    fr0,STKFRM-16(r1)
+1:      li      r9,-EFAULT
+2:      lfs     fr0,0(r4)
+        li      r9,0
+3:      bl      put_fpr
+        beq     cr7,4f
+        lfd     fr0,STKFRM-16(r1)
+4:      PPC_LL  r0,STKFRM+PPC_LR_STKOFF(r1)
+        mtlr    r0
+        mtmsrd  r6
+        isync
+        mr      r3,r9
+        addi    r1,r1,STKFRM
+        blr
+        extab   2b,3b
+
+/* Load FP reg N from double at *p.  N is in r3, p in r4. */
+_GLOBAL(do_lfd)
+        PPC_STLU r1,-STKFRM(r1)
+        mflr    r0
+        PPC_STL r0,STKFRM+PPC_LR_STKOFF(r1)
+        mfmsr   r6
+        ori     r7,r6,MSR_FP
+        cmpwi   cr7,r3,0
+        mtmsrd  r7
+        isync
+        beq     cr7,1f
+        stfd    fr0,STKFRM-16(r1)
+1:      li      r9,-EFAULT
+2:      lfd     fr0,0(r4)
+        li      r9,0
+3:      beq     cr7,4f
+        bl      put_fpr
+        lfd     fr0,STKFRM-16(r1)
+4:      PPC_LL  r0,STKFRM+PPC_LR_STKOFF(r1)
+        mtlr    r0
+        mtmsrd  r6
+        isync
+        mr      r3,r9
+        addi    r1,r1,STKFRM
+        blr
+        extab   2b,3b
+
+/* Store FP reg N to float at *p.  N is in r3, p in r4. */
+_GLOBAL(do_stfs)
+        PPC_STLU r1,-STKFRM(r1)
+        mflr    r0
+        PPC_STL r0,STKFRM+PPC_LR_STKOFF(r1)
+        mfmsr   r6
+        ori     r7,r6,MSR_FP
+        cmpwi   cr7,r3,0
+        mtmsrd  r7
+        isync
+        beq     cr7,1f
+        stfd    fr0,STKFRM-16(r1)
+        bl      get_fpr
+1:      li      r9,-EFAULT
+2:      stfs    fr0,0(r4)
+        li      r9,0
+3:      beq     cr7,4f
+        lfd     fr0,STKFRM-16(r1)
+4:      PPC_LL  r0,STKFRM+PPC_LR_STKOFF(r1)
+        mtlr    r0
+        mtmsrd  r6
+        isync
+        mr      r3,r9
+        addi    r1,r1,STKFRM
+        blr
+        extab   2b,3b
+
+/* Store FP reg N to double at *p.  N is in r3, p in r4. */
+_GLOBAL(do_stfd)
+        PPC_STLU r1,-STKFRM(r1)
+        mflr    r0
+        PPC_STL r0,STKFRM+PPC_LR_STKOFF(r1)
+        mfmsr   r6
+        ori     r7,r6,MSR_FP
+        cmpwi   cr7,r3,0
+        mtmsrd  r7
+        isync
+        beq     cr7,1f
+        stfd    fr0,STKFRM-16(r1)
+        bl      get_fpr
+1:      li      r9,-EFAULT
+2:      stfd    fr0,0(r4)
+        li      r9,0
+3:      beq     cr7,4f
+        lfd     fr0,STKFRM-16(r1)
+4:      PPC_LL  r0,STKFRM+PPC_LR_STKOFF(r1)
+        mtlr    r0
+        mtmsrd  r6
+        isync
+        mr      r3,r9
+        addi    r1,r1,STKFRM
+        blr
+        extab   2b,3b
+
+#ifdef CONFIG_ALTIVEC
+/* Get the contents of vrN into vr0; N is in r3. */
+_GLOBAL(get_vr)
+        mflr    r0
+        rlwinm  r3,r3,3,0xf8
+        bcl     20,31,1f
+        blr                     /* vr0 is already in vr0 */
+        nop
+reg = 1
+        .rept   31
+        vor     vr0,reg,reg     /* assembler doesn't know vmr? */
+        blr
+reg = reg + 1
+        .endr
+1:      mflr    r5
+        add     r5,r3,r5
+        mtctr   r5
+        mtlr    r0
+        bctr
+
+/* Put the contents of vr0 into vrN; N is in r3. */
+_GLOBAL(put_vr)
+        mflr    r0
+        rlwinm  r3,r3,3,0xf8
+        bcl     20,31,1f
+        blr                     /* vr0 is already in vr0 */
+        nop
+reg = 1
+        .rept   31
+        vor     reg,vr0,vr0
+        blr
+reg = reg + 1
+        .endr
+1:      mflr    r5
+        add     r5,r3,r5
+        mtctr   r5
+        mtlr    r0
+        bctr
+
+/* Load vector reg N from *p.  N is in r3, p in r4. */
+_GLOBAL(do_lvx)
+        PPC_STLU r1,-STKFRM(r1)
+        mflr    r0
+        PPC_STL r0,STKFRM+PPC_LR_STKOFF(r1)
+        mfmsr   r6
+        oris    r7,r6,MSR_VEC@h
+        cmpwi   cr7,r3,0
+        li      r8,STKFRM-16
+        mtmsrd  r7
+        isync
+        beq     cr7,1f
+        stvx    vr0,r1,r8
+1:      li      r9,-EFAULT
+2:      lvx     vr0,0,r4
+        li      r9,0
+3:      beq     cr7,4f
+        bl      put_vr
+        lvx     vr0,r1,r8
+4:      PPC_LL  r0,STKFRM+PPC_LR_STKOFF(r1)
+        mtlr    r0
+        mtmsrd  r6
+        isync
+        mr      r3,r9
+        addi    r1,r1,STKFRM
+        blr
+        extab   2b,3b
+
+/* Store vector reg N to *p.  N is in r3, p in r4. */
+_GLOBAL(do_stvx)
+        PPC_STLU r1,-STKFRM(r1)
+        mflr    r0
+        PPC_STL r0,STKFRM+PPC_LR_STKOFF(r1)
+        mfmsr   r6
+        oris    r7,r6,MSR_VEC@h
+        cmpwi   cr7,r3,0
+        li      r8,STKFRM-16
+        mtmsrd  r7
+        isync
+        beq     cr7,1f
+        stvx    vr0,r1,r8
+        bl      get_vr
+1:      li      r9,-EFAULT
+2:      stvx    vr0,0,r4
+        li      r9,0
+3:      beq     cr7,4f
+        lvx     vr0,r1,r8
+4:      PPC_LL  r0,STKFRM+PPC_LR_STKOFF(r1)
+        mtlr    r0
+        mtmsrd  r6
+        isync
+        mr      r3,r9
+        addi    r1,r1,STKFRM
+        blr
+        extab   2b,3b
+#endif /* CONFIG_ALTIVEC */
+
+#ifdef CONFIG_VSX
+/* Get the contents of vsrN into vsr0; N is in r3. */
+_GLOBAL(get_vsr)
+        mflr    r0
+        rlwinm  r3,r3,3,0x1f8
+        bcl     20,31,1f
+        blr                     /* vsr0 is already in vsr0 */
+        nop
+reg = 1
+        .rept   63
+        XXLOR(0,reg,reg)
+        blr
+reg = reg + 1
+        .endr
+1:      mflr    r5
+        add     r5,r3,r5
+        mtctr   r5
+        mtlr    r0
+        bctr
+
+/* Put the contents of vsr0 into vsrN; N is in r3. */
+_GLOBAL(put_vsr)
+        mflr    r0
+        rlwinm  r3,r3,3,0x1f8
+        bcl     20,31,1f
+        blr                     /* vr0 is already in vr0 */
+        nop
+reg = 1
+        .rept   63
+        XXLOR(reg,0,0)
+        blr
+reg = reg + 1
+        .endr
+1:      mflr    r5
+        add     r5,r3,r5
+        mtctr   r5
+        mtlr    r0
+        bctr
+
+/* Load VSX reg N from vector doubleword *p.  N is in r3, p in r4. */
+_GLOBAL(do_lxvd2x)
+        PPC_STLU r1,-STKFRM(r1)
+        mflr    r0
+        PPC_STL r0,STKFRM+PPC_LR_STKOFF(r1)
+        mfmsr   r6
+        oris    r7,r6,MSR_VSX@h
+        cmpwi   cr7,r3,0
+        li      r8,STKFRM-16
+        mtmsrd  r7
+        isync
+        beq     cr7,1f
+        STXVD2X(0,r1,r8)
+1:      li      r9,-EFAULT
+2:      LXVD2X(0,0,r4)
+        li      r9,0
+3:      beq     cr7,4f
+        bl      put_vsr
+        LXVD2X(0,r1,r8)
+4:      PPC_LL  r0,STKFRM+PPC_LR_STKOFF(r1)
+        mtlr    r0
+        mtmsrd  r6
+        isync
+        mr      r3,r9
+        addi    r1,r1,STKFRM
+        blr
+        extab   2b,3b
+
+/* Store VSX reg N to vector doubleword *p.  N is in r3, p in r4. */
+_GLOBAL(do_stxvd2x)
+        PPC_STLU r1,-STKFRM(r1)
+        mflr    r0
+        PPC_STL r0,STKFRM+PPC_LR_STKOFF(r1)
+        mfmsr   r6
+        oris    r7,r6,MSR_VSX@h
+        cmpwi   cr7,r3,0
+        li      r8,STKFRM-16
+        mtmsrd  r7
+        isync
+        beq     cr7,1f
+        STXVD2X(0,r1,r8)
+        bl      get_vsr
+1:      li      r9,-EFAULT
+2:      STXVD2X(0,0,r4)
+        li      r9,0
+3:      beq     cr7,4f
+        LXVD2X(0,r1,r8)
+4:      PPC_LL  r0,STKFRM+PPC_LR_STKOFF(r1)
+        mtlr    r0
+        mtmsrd  r6
+        isync
+        mr      r3,r9
+        addi    r1,r1,STKFRM
+        blr
+        extab   2b,3b
+
+#endif /* CONFIG_VSX */
diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c
index 13b7d54f185b..e0a9858d537e 100644
--- a/arch/powerpc/lib/sstep.c
+++ b/arch/powerpc/lib/sstep.c
@@ -13,6 +13,8 @@
 #include <linux/ptrace.h>
 #include <asm/sstep.h>
 #include <asm/processor.h>
+#include <asm/uaccess.h>
+#include <asm/cputable.h>
 
 extern char system_call_common[];
 
@@ -23,6 +25,23 @@ extern char system_call_common[];
 #define MSR_MASK        0x87c0ffff
 #endif
 
+/* Bits in XER */
+#define XER_SO          0x80000000U
+#define XER_OV          0x40000000U
+#define XER_CA          0x20000000U
+
+/*
+ * Functions in ldstfp.S
+ */
+extern int do_lfs(int rn, unsigned long ea);
+extern int do_lfd(int rn, unsigned long ea);
+extern int do_stfs(int rn, unsigned long ea);
+extern int do_stfd(int rn, unsigned long ea);
+extern int do_lvx(int rn, unsigned long ea);
+extern int do_stvx(int rn, unsigned long ea);
+extern int do_lxvd2x(int rn, unsigned long ea);
+extern int do_stxvd2x(int rn, unsigned long ea);
+
 /*
  * Determine whether a conditional branch instruction would branch.
  */
@@ -46,16 +65,499 @@ static int __kprobes branch_taken(unsigned int instr, struct pt_regs *regs)
         return 1;
 }
 
+
+static long __kprobes address_ok(struct pt_regs *regs, unsigned long ea, int nb)
+{
+        if (!user_mode(regs))
+                return 1;
+        return __access_ok(ea, nb, USER_DS);
+}
+
+/*
+ * Calculate effective address for a D-form instruction
+ */
+static unsigned long __kprobes dform_ea(unsigned int instr, struct pt_regs *regs)
+{
+        int ra;
+        unsigned long ea;
+
+        ra = (instr >> 16) & 0x1f;
+        ea = (signed short) instr;              /* sign-extend */
+        if (ra) {
+                ea += regs->gpr[ra];
+                if (instr & 0x04000000)         /* update forms */
+                        regs->gpr[ra] = ea;
+        }
+#ifdef __powerpc64__
+        if (!(regs->msr & MSR_SF))
+                ea &= 0xffffffffUL;
+#endif
+        return ea;
+}
+
+#ifdef __powerpc64__
+/*
+ * Calculate effective address for a DS-form instruction
+ */
+static unsigned long __kprobes dsform_ea(unsigned int instr, struct pt_regs *regs)
+{
+        int ra;
+        unsigned long ea;
+
+        ra = (instr >> 16) & 0x1f;
+        ea = (signed short) (instr & ~3);       /* sign-extend */
+        if (ra) {
+                ea += regs->gpr[ra];
+                if ((instr & 3) == 1)           /* update forms */
+                        regs->gpr[ra] = ea;
+        }
+        if (!(regs->msr & MSR_SF))
+                ea &= 0xffffffffUL;
+        return ea;
+}
+#endif /* __powerpc64 */
+
+/*
+ * Calculate effective address for an X-form instruction
+ */
+static unsigned long __kprobes xform_ea(unsigned int instr, struct pt_regs *regs,
+                                     int do_update)
+{
+        int ra, rb;
+        unsigned long ea;
+
+        ra = (instr >> 16) & 0x1f;
+        rb = (instr >> 11) & 0x1f;
+        ea = regs->gpr[rb];
+        if (ra) {
+                ea += regs->gpr[ra];
+                if (do_update)          /* update forms */
+                        regs->gpr[ra] = ea;
+        }
+#ifdef __powerpc64__
+        if (!(regs->msr & MSR_SF))
+                ea &= 0xffffffffUL;
+#endif
+        return ea;
+}
+
+/*
+ * Return the largest power of 2, not greater than sizeof(unsigned long),
+ * such that x is a multiple of it.
+ */
+static inline unsigned long max_align(unsigned long x)
+{
+        x |= sizeof(unsigned long);
+        return x & -x;          /* isolates rightmost bit */
+}
+
+
+static inline unsigned long byterev_2(unsigned long x)
+{
+        return ((x >> 8) & 0xff) | ((x & 0xff) << 8);
+}
+
+static inline unsigned long byterev_4(unsigned long x)
+{
+        return ((x >> 24) & 0xff) | ((x >> 8) & 0xff00) |
+                ((x & 0xff00) << 8) | ((x & 0xff) << 24);
+}
+
+#ifdef __powerpc64__
+static inline unsigned long byterev_8(unsigned long x)
+{
+        return (byterev_4(x) << 32) | byterev_4(x >> 32);
+}
+#endif
+
+static int __kprobes read_mem_aligned(unsigned long *dest, unsigned long ea,
+                                      int nb)
+{
+        int err = 0;
+        unsigned long x = 0;
+
+        switch (nb) {
+        case 1:
+                err = __get_user(x, (unsigned char __user *) ea);
+                break;
+        case 2:
+                err = __get_user(x, (unsigned short __user *) ea);
+                break;
+        case 4:
+                err = __get_user(x, (unsigned int __user *) ea);
+                break;
+#ifdef __powerpc64__
+        case 8:
+                err = __get_user(x, (unsigned long __user *) ea);
+                break;
+#endif
+        }
+        if (!err)
+                *dest = x;
+        return err;
+}
+
+static int __kprobes read_mem_unaligned(unsigned long *dest, unsigned long ea,
+                                        int nb, struct pt_regs *regs)
+{
+        int err;
+        unsigned long x, b, c;
+
+        /* unaligned, do this in pieces */
+        x = 0;
+        for (; nb > 0; nb -= c) {
+                c = max_align(ea);
+                if (c > nb)
+                        c = max_align(nb);
+                err = read_mem_aligned(&b, ea, c);
+                if (err)
+                        return err;
+                x = (x << (8 * c)) + b;
+                ea += c;
+        }
+        *dest = x;
+        return 0;
+}
+
+/*
+ * Read memory at address ea for nb bytes, return 0 for success
+ * or -EFAULT if an error occurred.
+ */
+static int __kprobes read_mem(unsigned long *dest, unsigned long ea, int nb,
+                              struct pt_regs *regs)
+{
+        if (!address_ok(regs, ea, nb))
+                return -EFAULT;
+        if ((ea & (nb - 1)) == 0)
+                return read_mem_aligned(dest, ea, nb);
+        return read_mem_unaligned(dest, ea, nb, regs);
+}
+
+static int __kprobes write_mem_aligned(unsigned long val, unsigned long ea,
+                                       int nb)
+{
+        int err = 0;
+
+        switch (nb) {
+        case 1:
+                err = __put_user(val, (unsigned char __user *) ea);
+                break;
+        case 2:
+                err = __put_user(val, (unsigned short __user *) ea);
+                break;
+        case 4:
+                err = __put_user(val, (unsigned int __user *) ea);
+                break;
+#ifdef __powerpc64__
+        case 8:
+                err = __put_user(val, (unsigned long __user *) ea);
+                break;
+#endif
+        }
+        return err;
+}
+
+static int __kprobes write_mem_unaligned(unsigned long val, unsigned long ea,
+                                         int nb, struct pt_regs *regs)
+{
+        int err;
+        unsigned long c;
+
+        /* unaligned or little-endian, do this in pieces */
+        for (; nb > 0; nb -= c) {
+                c = max_align(ea);
+                if (c > nb)
+                        c = max_align(nb);
+                err = write_mem_aligned(val >> (nb - c) * 8, ea, c);
+                if (err)
+                        return err;
+                ++ea;
+        }
+        return 0;
+}
+
+/*
+ * Write memory at address ea for nb bytes, return 0 for success
+ * or -EFAULT if an error occurred.
+ */
+static int __kprobes write_mem(unsigned long val, unsigned long ea, int nb,
+                               struct pt_regs *regs)
+{
+        if (!address_ok(regs, ea, nb))
+                return -EFAULT;
+        if ((ea & (nb - 1)) == 0)
+                return write_mem_aligned(val, ea, nb);
+        return write_mem_unaligned(val, ea, nb, regs);
+}
+
 /*
- * Emulate instructions that cause a transfer of control.
+ * Check the address and alignment, and call func to do the actual
+ * load or store.
+ */
+static int __kprobes do_fp_load(int rn, int (*func)(int, unsigned long),
+                                unsigned long ea, int nb,
+                                struct pt_regs *regs)
+{
+        int err;
+        unsigned long val[sizeof(double) / sizeof(long)];
+        unsigned long ptr;
+
+        if (!address_ok(regs, ea, nb))
+                return -EFAULT;
+        if ((ea & 3) == 0)
+                return (*func)(rn, ea);
+        ptr = (unsigned long) &val[0];
+        if (sizeof(unsigned long) == 8 || nb == 4) {
+                err = read_mem_unaligned(&val[0], ea, nb, regs);
+                ptr += sizeof(unsigned long) - nb;
+        } else {
+                /* reading a double on 32-bit */
+                err = read_mem_unaligned(&val[0], ea, 4, regs);
+                if (!err)
+                        err = read_mem_unaligned(&val[1], ea + 4, 4, regs);
+        }
+        if (err)
+                return err;
+        return (*func)(rn, ptr);
+}
+
+static int __kprobes do_fp_store(int rn, int (*func)(int, unsigned long),
+                                 unsigned long ea, int nb,
+                                 struct pt_regs *regs)
+{
+        int err;
+        unsigned long val[sizeof(double) / sizeof(long)];
+        unsigned long ptr;
+
+        if (!address_ok(regs, ea, nb))
+                return -EFAULT;
+        if ((ea & 3) == 0)
+                return (*func)(rn, ea);
+        ptr = (unsigned long) &val[0];
+        if (sizeof(unsigned long) == 8 || nb == 4) {
+                ptr += sizeof(unsigned long) - nb;
+                err = (*func)(rn, ptr);
+                if (err)
+                        return err;
+                err = write_mem_unaligned(val[0], ea, nb, regs);
+        } else {
+                /* writing a double on 32-bit */
+                err = (*func)(rn, ptr);
+                if (err)
+                        return err;
+                err = write_mem_unaligned(val[0], ea, 4, regs);
+                if (!err)
+                        err = write_mem_unaligned(val[1], ea + 4, 4, regs);
+        }
+        return err;
+}
+
+#ifdef CONFIG_ALTIVEC
+/* For Altivec/VMX, no need to worry about alignment */
+static int __kprobes do_vec_load(int rn, int (*func)(int, unsigned long),
+                                 unsigned long ea, struct pt_regs *regs)
+{
+        if (!address_ok(regs, ea & ~0xfUL, 16))
+                return -EFAULT;
+        return (*func)(rn, ea);
+}
+
+static int __kprobes do_vec_store(int rn, int (*func)(int, unsigned long),
+                                  unsigned long ea, struct pt_regs *regs)
+{
+        if (!address_ok(regs, ea & ~0xfUL, 16))
+                return -EFAULT;
+        return (*func)(rn, ea);
+}
+#endif /* CONFIG_ALTIVEC */
+
+#ifdef CONFIG_VSX
+static int __kprobes do_vsx_load(int rn, int (*func)(int, unsigned long),
+                                 unsigned long ea, struct pt_regs *regs)
+{
+        int err;
+        unsigned long val[2];
+
+        if (!address_ok(regs, ea, 16))
+                return -EFAULT;
+        if ((ea & 3) == 0)
+                return (*func)(rn, ea);
+        err = read_mem_unaligned(&val[0], ea, 8, regs);
+        if (!err)
+                err = read_mem_unaligned(&val[1], ea + 8, 8, regs);
+        if (!err)
+                err = (*func)(rn, (unsigned long) &val[0]);
+        return err;
+}
+
+static int __kprobes do_vsx_store(int rn, int (*func)(int, unsigned long),
+                                 unsigned long ea, struct pt_regs *regs)
+{
+        int err;
+        unsigned long val[2];
+
+        if (!address_ok(regs, ea, 16))
+                return -EFAULT;
+        if ((ea & 3) == 0)
+                return (*func)(rn, ea);
+        err = (*func)(rn, (unsigned long) &val[0]);
+        if (err)
+                return err;
+        err = write_mem_unaligned(val[0], ea, 8, regs);
+        if (!err)
+                err = write_mem_unaligned(val[1], ea + 8, 8, regs);
+        return err;
+}
+#endif /* CONFIG_VSX */
+
+#define __put_user_asmx(x, addr, err, op, cr)           \
+        __asm__ __volatile__(                           \
+                "1:     " op " %2,0,%3\n"               \
+                "       mfcr    %1\n"                   \
+                "2:\n"                                  \
+                ".section .fixup,\"ax\"\n"              \
+                "3:     li      %0,%4\n"                \
+                "       b       2b\n"                   \
+                ".previous\n"                           \
+                ".section __ex_table,\"a\"\n"           \
+                        PPC_LONG_ALIGN "\n"             \
+                        PPC_LONG "1b,3b\n"              \
+                ".previous"                             \
+                : "=r" (err), "=r" (cr)                 \
+                : "r" (x), "r" (addr), "i" (-EFAULT), "0" (err))
+
+#define __get_user_asmx(x, addr, err, op)               \
+        __asm__ __volatile__(                           \
+                "1:     "op" %1,0,%2\n"                 \
+                "2:\n"                                  \
+                ".section .fixup,\"ax\"\n"              \
+                "3:     li      %0,%3\n"                \
+                "       b       2b\n"                   \
+                ".previous\n"                           \
+                ".section __ex_table,\"a\"\n"           \
+                        PPC_LONG_ALIGN "\n"             \
+                        PPC_LONG "1b,3b\n"              \
+                ".previous"                             \
+                : "=r" (err), "=r" (x)                  \
+                : "r" (addr), "i" (-EFAULT), "0" (err))
+
+#define __cacheop_user_asmx(addr, err, op)              \
+        __asm__ __volatile__(                           \
+                "1:     "op" 0,%1\n"                    \
+                "2:\n"                                  \
+                ".section .fixup,\"ax\"\n"              \
+                "3:     li      %0,%3\n"                \
+                "       b       2b\n"                   \
+                ".previous\n"                           \
+                ".section __ex_table,\"a\"\n"           \
+                        PPC_LONG_ALIGN "\n"             \
+                        PPC_LONG "1b,3b\n"              \
+                ".previous"                             \
+                : "=r" (err)                            \
+                : "r" (addr), "i" (-EFAULT), "0" (err))
+
+static void __kprobes set_cr0(struct pt_regs *regs, int rd)
+{
+        long val = regs->gpr[rd];
+
+        regs->ccr = (regs->ccr & 0x0fffffff) | ((regs->xer >> 3) & 0x10000000);
+#ifdef __powerpc64__
+        if (!(regs->msr & MSR_SF))
+                val = (int) val;
+#endif
+        if (val < 0)
+                regs->ccr |= 0x80000000;
+        else if (val > 0)
+                regs->ccr |= 0x40000000;
+        else
+                regs->ccr |= 0x20000000;
+}
+
+static void __kprobes add_with_carry(struct pt_regs *regs, int rd,
+                                     unsigned long val1, unsigned long val2,
+                                     unsigned long carry_in)
+{
+        unsigned long val = val1 + val2;
+
+        if (carry_in)
+                ++val;
+        regs->gpr[rd] = val;
+#ifdef __powerpc64__
+        if (!(regs->msr & MSR_SF)) {
+                val = (unsigned int) val;
+                val1 = (unsigned int) val1;
+        }
+#endif
+        if (val < val1 || (carry_in && val == val1))
+                regs->xer |= XER_CA;
+        else
+                regs->xer &= ~XER_CA;
+}
+
+static void __kprobes do_cmp_signed(struct pt_regs *regs, long v1, long v2,
+                                    int crfld)
+{
+        unsigned int crval, shift;
+
+        crval = (regs->xer >> 31) & 1;          /* get SO bit */
+        if (v1 < v2)
+                crval |= 8;
+        else if (v1 > v2)
+                crval |= 4;
+        else
+                crval |= 2;
+        shift = (7 - crfld) * 4;
+        regs->ccr = (regs->ccr & ~(0xf << shift)) | (crval << shift);
+}
+
+static void __kprobes do_cmp_unsigned(struct pt_regs *regs, unsigned long v1,
+                                      unsigned long v2, int crfld)
+{
+        unsigned int crval, shift;
+
+        crval = (regs->xer >> 31) & 1;          /* get SO bit */
+        if (v1 < v2)
+                crval |= 8;
+        else if (v1 > v2)
+                crval |= 4;
+        else
+                crval |= 2;
+        shift = (7 - crfld) * 4;
+        regs->ccr = (regs->ccr & ~(0xf << shift)) | (crval << shift);
+}
+
+/*
+ * Elements of 32-bit rotate and mask instructions.
+ */
+#define MASK32(mb, me)  ((0xffffffffUL >> (mb)) + \
+                         ((signed long)-0x80000000L >> (me)) + ((me) >= (mb)))
+#ifdef __powerpc64__
+#define MASK64_L(mb)    (~0UL >> (mb))
+#define MASK64_R(me)    ((signed long)-0x8000000000000000L >> (me))
+#define MASK64(mb, me)  (MASK64_L(mb) + MASK64_R(me) + ((me) >= (mb)))
+#define DATA32(x)       (((x) & 0xffffffffUL) | (((x) & 0xffffffffUL) << 32))
+#else
+#define DATA32(x)       (x)
+#endif
+#define ROTATE(x, n)    ((n) ? (((x) << (n)) | ((x) >> (8 * sizeof(long) - (n)))) : (x))
+
+/*
+ * Emulate instructions that cause a transfer of control,
+ * loads and stores, and a few other instructions.
  * Returns 1 if the step was emulated, 0 if not,
  * or -1 if the instruction is one that should not be stepped,
  * such as an rfid, or a mtmsrd that would clear MSR_RI.
  */
 int __kprobes emulate_step(struct pt_regs *regs, unsigned int instr)
 {
-        unsigned int opcode, rs, rb, rd, spr;
+        unsigned int opcode, ra, rb, rd, spr, u;
         unsigned long int imm;
+        unsigned long int val, val2;
+        unsigned long int ea;
+        unsigned int cr, mb, me, sh;
+        int err;
+        unsigned long old_ra;
+        long ival;
 
         opcode = instr >> 26;
         switch (opcode) {
@@ -78,7 +580,13 @@ int __kprobes emulate_step(struct pt_regs *regs, unsigned int instr)
                  * entry code works.  If that is changed, this will
                  * need to be changed also.
                  */
+                if (regs->gpr[0] == 0x1ebe &&
+                    cpu_has_feature(CPU_FTR_REAL_LE)) {
+                        regs->msr ^= MSR_LE;
+                        goto instr_done;
+                }
                 regs->gpr[9] = regs->gpr[13];
+                regs->gpr[10] = MSR_KERNEL;
                 regs->gpr[11] = regs->nip + 4;
                 regs->gpr[12] = regs->msr & MSR_MASK;
                 regs->gpr[13] = (unsigned long) get_paca();
@@ -102,9 +610,9 @@ int __kprobes emulate_step(struct pt_regs *regs, unsigned int instr)
                 regs->nip = imm;
                 return 1;
         case 19:
-                switch (instr & 0x7fe) {
-                case 0x20:      /* bclr */
-                case 0x420:     /* bcctr */
+                switch ((instr >> 1) & 0x3ff) {
+                case 16:        /* bclr */
+                case 528:       /* bcctr */
                         imm = (instr & 0x400)? regs->ctr: regs->link;
                         regs->nip += 4;
                         if ((regs->msr & MSR_SF) == 0) {
@@ -116,30 +624,233 @@ int __kprobes emulate_step(struct pt_regs *regs, unsigned int instr)
                         if (branch_taken(instr, regs))
                                 regs->nip = imm;
                         return 1;
-                case 0x24:      /* rfid, scary */
+
+                case 18:        /* rfid, scary */
                         return -1;
+
+                case 150:       /* isync */
+                        isync();
+                        goto instr_done;
+
+                case 33:        /* crnor */
+                case 129:       /* crandc */
+                case 193:       /* crxor */
+                case 225:       /* crnand */
+                case 257:       /* crand */
+                case 289:       /* creqv */
+                case 417:       /* crorc */
+                case 449:       /* cror */
+                        ra = (instr >> 16) & 0x1f;
+                        rb = (instr >> 11) & 0x1f;
+                        rd = (instr >> 21) & 0x1f;
+                        ra = (regs->ccr >> (31 - ra)) & 1;
+                        rb = (regs->ccr >> (31 - rb)) & 1;
+                        val = (instr >> (6 + ra * 2 + rb)) & 1;
+                        regs->ccr = (regs->ccr & ~(1UL << (31 - rd))) |
+                                (val << (31 - rd));
+                        goto instr_done;
+                }
+                break;
+        case 31:
+                switch ((instr >> 1) & 0x3ff) {
+                case 598:       /* sync */
+#ifdef __powerpc64__
+                        switch ((instr >> 21) & 3) {
+                        case 1:         /* lwsync */
+                                asm volatile("lwsync" : : : "memory");
+                                goto instr_done;
+                        case 2:         /* ptesync */
+                                asm volatile("ptesync" : : : "memory");
+                                goto instr_done;
+                        }
+#endif
+                        mb();
+                        goto instr_done;
+
+                case 854:       /* eieio */
+                        eieio();
+                        goto instr_done;
+                }
+                break;
+        }
+
+        /* Following cases refer to regs->gpr[], so we need all regs */
+        if (!FULL_REGS(regs))
+                return 0;
+
+        rd = (instr >> 21) & 0x1f;
+        ra = (instr >> 16) & 0x1f;
+        rb = (instr >> 11) & 0x1f;
+
+        switch (opcode) {
+        case 7:         /* mulli */
+                regs->gpr[rd] = regs->gpr[ra] * (short) instr;
+                goto instr_done;
+
+        case 8:         /* subfic */
+                imm = (short) instr;
+                add_with_carry(regs, rd, ~regs->gpr[ra], imm, 1);
+                goto instr_done;
+
+        case 10:        /* cmpli */
+                imm = (unsigned short) instr;
+                val = regs->gpr[ra];
+#ifdef __powerpc64__
+                if ((rd & 1) == 0)
+                        val = (unsigned int) val;
+#endif
+                do_cmp_unsigned(regs, val, imm, rd >> 2);
+                goto instr_done;
+
+        case 11:        /* cmpi */
+                imm = (short) instr;
+                val = regs->gpr[ra];
+#ifdef __powerpc64__
+                if ((rd & 1) == 0)
+                        val = (int) val;
+#endif
+                do_cmp_signed(regs, val, imm, rd >> 2);
+                goto instr_done;
+
+        case 12:        /* addic */
+                imm = (short) instr;
+                add_with_carry(regs, rd, regs->gpr[ra], imm, 0);
+                goto instr_done;
+
+        case 13:        /* addic. */
+                imm = (short) instr;
+                add_with_carry(regs, rd, regs->gpr[ra], imm, 0);
+                set_cr0(regs, rd);
+                goto instr_done;
+
+        case 14:        /* addi */
+                imm = (short) instr;
+                if (ra)
+                        imm += regs->gpr[ra];
+                regs->gpr[rd] = imm;
+                goto instr_done;
+
+        case 15:        /* addis */
+                imm = ((short) instr) << 16;
+                if (ra)
+                        imm += regs->gpr[ra];
+                regs->gpr[rd] = imm;
+                goto instr_done;
+
+        case 20:        /* rlwimi */
+                mb = (instr >> 6) & 0x1f;
+                me = (instr >> 1) & 0x1f;
+                val = DATA32(regs->gpr[rd]);
+                imm = MASK32(mb, me);
+                regs->gpr[ra] = (regs->gpr[ra] & ~imm) | (ROTATE(val, rb) & imm);
+                goto logical_done;
+
+        case 21:        /* rlwinm */
+                mb = (instr >> 6) & 0x1f;
+                me = (instr >> 1) & 0x1f;
+                val = DATA32(regs->gpr[rd]);
+                regs->gpr[ra] = ROTATE(val, rb) & MASK32(mb, me);
+                goto logical_done;
+
+        case 23:        /* rlwnm */
+                mb = (instr >> 6) & 0x1f;
+                me = (instr >> 1) & 0x1f;
+                rb = regs->gpr[rb] & 0x1f;
+                val = DATA32(regs->gpr[rd]);
+                regs->gpr[ra] = ROTATE(val, rb) & MASK32(mb, me);
+                goto logical_done;
+
+        case 24:        /* ori */
+                imm = (unsigned short) instr;
+                regs->gpr[ra] = regs->gpr[rd] | imm;
+                goto instr_done;
+
+        case 25:        /* oris */
+                imm = (unsigned short) instr;
+                regs->gpr[ra] = regs->gpr[rd] | (imm << 16);
+                goto instr_done;
+
+        case 26:        /* xori */
+                imm = (unsigned short) instr;
+                regs->gpr[ra] = regs->gpr[rd] ^ imm;
+                goto instr_done;
+
+        case 27:        /* xoris */
+                imm = (unsigned short) instr;
+                regs->gpr[ra] = regs->gpr[rd] ^ (imm << 16);
+                goto instr_done;
+
+        case 28:        /* andi. */
+                imm = (unsigned short) instr;
+                regs->gpr[ra] = regs->gpr[rd] & imm;
+                set_cr0(regs, ra);
+                goto instr_done;
+
+        case 29:        /* andis. */
+                imm = (unsigned short) instr;
+                regs->gpr[ra] = regs->gpr[rd] & (imm << 16);
+                set_cr0(regs, ra);
+                goto instr_done;
+
+#ifdef __powerpc64__
+        case 30:        /* rld* */
+                mb = ((instr >> 6) & 0x1f) | (instr & 0x20);
+                val = regs->gpr[rd];
+                if ((instr & 0x10) == 0) {
+                        sh = rb | ((instr & 2) << 4);
+                        val = ROTATE(val, sh);
+                        switch ((instr >> 2) & 3) {
+                        case 0:         /* rldicl */
+                                regs->gpr[ra] = val & MASK64_L(mb);
+                                goto logical_done;
+                        case 1:         /* rldicr */
+                                regs->gpr[ra] = val & MASK64_R(mb);
+                                goto logical_done;
+                        case 2:         /* rldic */
+                                regs->gpr[ra] = val & MASK64(mb, 63 - sh);
+                                goto logical_done;
+                        case 3:         /* rldimi */
+                                imm = MASK64(mb, 63 - sh);
+                                regs->gpr[ra] = (regs->gpr[ra] & ~imm) |
+                                        (val & imm);
+                                goto logical_done;
+                        }
+                } else {
+                        sh = regs->gpr[rb] & 0x3f;
+                        val = ROTATE(val, sh);
+                        switch ((instr >> 1) & 7) {
+                        case 0:         /* rldcl */
+                                regs->gpr[ra] = val & MASK64_L(mb);
+                                goto logical_done;
+                        case 1:         /* rldcr */
+                                regs->gpr[ra] = val & MASK64_R(mb);
+                                goto logical_done;
+                        }
                 }
+#endif
+
         case 31:
-                rd = (instr >> 21) & 0x1f;
-                switch (instr & 0x7fe) {
-                case 0xa6:      /* mfmsr */
+                switch ((instr >> 1) & 0x3ff) {
+                case 83:        /* mfmsr */
+                        if (regs->msr & MSR_PR)
+                                break;
                         regs->gpr[rd] = regs->msr & MSR_MASK;
-                        regs->nip += 4;
-                        if ((regs->msr & MSR_SF) == 0)
-                                regs->nip &= 0xffffffffUL;
-                        return 1;
-                case 0x124:     /* mtmsr */
+                        goto instr_done;
+                case 146:       /* mtmsr */
+                        if (regs->msr & MSR_PR)
+                                break;
                         imm = regs->gpr[rd];
                         if ((imm & MSR_RI) == 0)
                                 /* can't step mtmsr that would clear MSR_RI */
                                 return -1;
                         regs->msr = imm;
-                        regs->nip += 4;
-                        return 1;
+                        goto instr_done;
 #ifdef CONFIG_PPC64
-                case 0x164:     /* mtmsrd */
+                case 178:       /* mtmsrd */
                         /* only MSR_EE and MSR_RI get changed if bit 15 set */
                         /* mtmsrd doesn't change MSR_HV and MSR_ME */
+                        if (regs->msr & MSR_PR)
+                                break;
                         imm = (instr & 0x10000)? 0x8002: 0xefffffffffffefffUL;
                         imm = (regs->msr & MSR_MASK & ~imm)
                                 | (regs->gpr[rd] & imm);
@@ -147,57 +858,770 @@ int __kprobes emulate_step(struct pt_regs *regs, unsigned int instr)
                                 /* can't step mtmsrd that would clear MSR_RI */
                                 return -1;
                         regs->msr = imm;
-                        regs->nip += 4;
-                        if ((imm & MSR_SF) == 0)
-                                regs->nip &= 0xffffffffUL;
-                        return 1;
+                        goto instr_done;
 #endif
-                case 0x26:      /* mfcr */
+                case 19:        /* mfcr */
                         regs->gpr[rd] = regs->ccr;
                         regs->gpr[rd] &= 0xffffffffUL;
-                        goto mtspr_out;
-                case 0x2a6:     /* mfspr */
+                        goto instr_done;
+
+                case 144:       /* mtcrf */
+                        imm = 0xf0000000UL;
+                        val = regs->gpr[rd];
+                        for (sh = 0; sh < 8; ++sh) {
+                                if (instr & (0x80000 >> sh))
+                                        regs->ccr = (regs->ccr & ~imm) |
+                                                (val & imm);
+                                imm >>= 4;
+                        }
+                        goto instr_done;
+
+                case 339:       /* mfspr */
                         spr = (instr >> 11) & 0x3ff;
                         switch (spr) {
                         case 0x20:      /* mfxer */
                                 regs->gpr[rd] = regs->xer;
                                 regs->gpr[rd] &= 0xffffffffUL;
-                                goto mtspr_out;
+                                goto instr_done;
                         case 0x100:     /* mflr */
                                 regs->gpr[rd] = regs->link;
-                                goto mtspr_out;
+                                goto instr_done;
                         case 0x120:     /* mfctr */
                                 regs->gpr[rd] = regs->ctr;
-                                goto mtspr_out;
-                        }
-                        break;
-                case 0x378:     /* orx */
-                        if (instr & 1)
-                                break;
-                        rs = (instr >> 21) & 0x1f;
-                        rb = (instr >> 11) & 0x1f;
-                        if (rs == rb) {         /* mr */
-                                rd = (instr >> 16) & 0x1f;
-                                regs->gpr[rd] = regs->gpr[rs];
-                                goto mtspr_out;
+                                goto instr_done;
                         }
                         break;
-                case 0x3a6:     /* mtspr */
+
+                case 467:       /* mtspr */
                         spr = (instr >> 11) & 0x3ff;
                         switch (spr) {
                         case 0x20:      /* mtxer */
                                 regs->xer = (regs->gpr[rd] & 0xffffffffUL);
-                                goto mtspr_out;
+                                goto instr_done;
                         case 0x100:     /* mtlr */
                                 regs->link = regs->gpr[rd];
-                                goto mtspr_out;
+                                goto instr_done;
                         case 0x120:     /* mtctr */
                                 regs->ctr = regs->gpr[rd];
-mtspr_out:
-                                regs->nip += 4;
-                                return 1;
+                                goto instr_done;
                         }
+                        break;
+
+/*
+ * Compare instructions
+ */
+                case 0: /* cmp */
+                        val = regs->gpr[ra];
+                        val2 = regs->gpr[rb];
+#ifdef __powerpc64__
+                        if ((rd & 1) == 0) {
+                                /* word (32-bit) compare */
+                                val = (int) val;
+                                val2 = (int) val2;
+                        }
+#endif
+                        do_cmp_signed(regs, val, val2, rd >> 2);
+                        goto instr_done;
+
+                case 32:        /* cmpl */
+                        val = regs->gpr[ra];
+                        val2 = regs->gpr[rb];
+#ifdef __powerpc64__
+                        if ((rd & 1) == 0) {
+                                /* word (32-bit) compare */
+                                val = (unsigned int) val;
+                                val2 = (unsigned int) val2;
+                        }
+#endif
+                        do_cmp_unsigned(regs, val, val2, rd >> 2);
+                        goto instr_done;
+
+/*
+ * Arithmetic instructions
+ */
+                case 8: /* subfc */
+                        add_with_carry(regs, rd, ~regs->gpr[ra],
+                                       regs->gpr[rb], 1);
+                        goto arith_done;
+#ifdef __powerpc64__
+                case 9: /* mulhdu */
+                        asm("mulhdu %0,%1,%2" : "=r" (regs->gpr[rd]) :
+                            "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
+                        goto arith_done;
+#endif
+                case 10:        /* addc */
+                        add_with_carry(regs, rd, regs->gpr[ra],
+                                       regs->gpr[rb], 0);
+                        goto arith_done;
+
+                case 11:        /* mulhwu */
+                        asm("mulhwu %0,%1,%2" : "=r" (regs->gpr[rd]) :
+                            "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
+                        goto arith_done;
+
+                case 40:        /* subf */
+                        regs->gpr[rd] = regs->gpr[rb] - regs->gpr[ra];
+                        goto arith_done;
+#ifdef __powerpc64__
+                case 73:        /* mulhd */
+                        asm("mulhd %0,%1,%2" : "=r" (regs->gpr[rd]) :
+                            "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
+                        goto arith_done;
+#endif
+                case 75:        /* mulhw */
+                        asm("mulhw %0,%1,%2" : "=r" (regs->gpr[rd]) :
+                            "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
+                        goto arith_done;
+
+                case 104:       /* neg */
+                        regs->gpr[rd] = -regs->gpr[ra];
+                        goto arith_done;
+
+                case 136:       /* subfe */
+                        add_with_carry(regs, rd, ~regs->gpr[ra], regs->gpr[rb],
+                                       regs->xer & XER_CA);
+                        goto arith_done;
+
+                case 138:       /* adde */
+                        add_with_carry(regs, rd, regs->gpr[ra], regs->gpr[rb],
+                                       regs->xer & XER_CA);
+                        goto arith_done;
+
+                case 200:       /* subfze */
+                        add_with_carry(regs, rd, ~regs->gpr[ra], 0L,
+                                       regs->xer & XER_CA);
+                        goto arith_done;
+
+                case 202:       /* addze */
+                        add_with_carry(regs, rd, regs->gpr[ra], 0L,
+                                       regs->xer & XER_CA);
+                        goto arith_done;
+
+                case 232:       /* subfme */
+                        add_with_carry(regs, rd, ~regs->gpr[ra], -1L,
+                                       regs->xer & XER_CA);
+                        goto arith_done;
+#ifdef __powerpc64__
+                case 233:       /* mulld */
+                        regs->gpr[rd] = regs->gpr[ra] * regs->gpr[rb];
+                        goto arith_done;
+#endif
+                case 234:       /* addme */
+                        add_with_carry(regs, rd, regs->gpr[ra], -1L,
+                                       regs->xer & XER_CA);
+                        goto arith_done;
+
+                case 235:       /* mullw */
+                        regs->gpr[rd] = (unsigned int) regs->gpr[ra] *
+                                (unsigned int) regs->gpr[rb];
+                        goto arith_done;
+
+                case 266:       /* add */
+                        regs->gpr[rd] = regs->gpr[ra] + regs->gpr[rb];
+                        goto arith_done;
+#ifdef __powerpc64__
+                case 457:       /* divdu */
+                        regs->gpr[rd] = regs->gpr[ra] / regs->gpr[rb];
+                        goto arith_done;
+#endif
+                case 459:       /* divwu */
+                        regs->gpr[rd] = (unsigned int) regs->gpr[ra] /
+                                (unsigned int) regs->gpr[rb];
+                        goto arith_done;
+#ifdef __powerpc64__
+                case 489:       /* divd */
+                        regs->gpr[rd] = (long int) regs->gpr[ra] /
+                                (long int) regs->gpr[rb];
+                        goto arith_done;
+#endif
+                case 491:       /* divw */
+                        regs->gpr[rd] = (int) regs->gpr[ra] /
+                                (int) regs->gpr[rb];
+                        goto arith_done;
+
+
+/*
+ * Logical instructions
+ */
+                case 26:        /* cntlzw */
+                        asm("cntlzw %0,%1" : "=r" (regs->gpr[ra]) :
+                            "r" (regs->gpr[rd]));
+                        goto logical_done;
+#ifdef __powerpc64__
+                case 58:        /* cntlzd */
+                        asm("cntlzd %0,%1" : "=r" (regs->gpr[ra]) :
+                            "r" (regs->gpr[rd]));
+                        goto logical_done;
+#endif
+                case 28:        /* and */
+                        regs->gpr[ra] = regs->gpr[rd] & regs->gpr[rb];
+                        goto logical_done;
+
+                case 60:        /* andc */
+                        regs->gpr[ra] = regs->gpr[rd] & ~regs->gpr[rb];
+                        goto logical_done;
+
+                case 124:       /* nor */
+                        regs->gpr[ra] = ~(regs->gpr[rd] | regs->gpr[rb]);
+                        goto logical_done;
+
+                case 284:       /* xor */
+                        regs->gpr[ra] = ~(regs->gpr[rd] ^ regs->gpr[rb]);
+                        goto logical_done;
+
+                case 316:       /* xor */
+                        regs->gpr[ra] = regs->gpr[rd] ^ regs->gpr[rb];
+                        goto logical_done;
+
+                case 412:       /* orc */
+                        regs->gpr[ra] = regs->gpr[rd] | ~regs->gpr[rb];
+                        goto logical_done;
+
+                case 444:       /* or */
+                        regs->gpr[ra] = regs->gpr[rd] | regs->gpr[rb];
+                        goto logical_done;
+
+                case 476:       /* nand */
+                        regs->gpr[ra] = ~(regs->gpr[rd] & regs->gpr[rb]);
+                        goto logical_done;
+
+                case 922:       /* extsh */
+                        regs->gpr[ra] = (signed short) regs->gpr[rd];
+                        goto logical_done;
+
+                case 954:       /* extsb */
+                        regs->gpr[ra] = (signed char) regs->gpr[rd];
+                        goto logical_done;
+#ifdef __powerpc64__
+                case 986:       /* extsw */
+                        regs->gpr[ra] = (signed int) regs->gpr[rd];
+                        goto logical_done;
+#endif
+
+/*
+ * Shift instructions
+ */
+                case 24:        /* slw */
+                        sh = regs->gpr[rb] & 0x3f;
+                        if (sh < 32)
+                                regs->gpr[ra] = (regs->gpr[rd] << sh) & 0xffffffffUL;
+                        else
+                                regs->gpr[ra] = 0;
+                        goto logical_done;
+
+                case 536:       /* srw */
+                        sh = regs->gpr[rb] & 0x3f;
+                        if (sh < 32)
+                                regs->gpr[ra] = (regs->gpr[rd] & 0xffffffffUL) >> sh;
+                        else
+                                regs->gpr[ra] = 0;
+                        goto logical_done;
+
+                case 792:       /* sraw */
+                        sh = regs->gpr[rb] & 0x3f;
+                        ival = (signed int) regs->gpr[rd];
+                        regs->gpr[ra] = ival >> (sh < 32 ? sh : 31);
+                        if (ival < 0 && (sh >= 32 || (ival & ((1 << sh) - 1)) != 0))
+                                regs->xer |= XER_CA;
+                        else
+                                regs->xer &= ~XER_CA;
+                        goto logical_done;
+
+                case 824:       /* srawi */
+                        sh = rb;
+                        ival = (signed int) regs->gpr[rd];
+                        regs->gpr[ra] = ival >> sh;
+                        if (ival < 0 && (ival & ((1 << sh) - 1)) != 0)
+                                regs->xer |= XER_CA;
+                        else
+                                regs->xer &= ~XER_CA;
+                        goto logical_done;
+
+#ifdef __powerpc64__
+                case 27:        /* sld */
+                        sh = regs->gpr[rd] & 0x7f;
+                        if (sh < 64)
+                                regs->gpr[ra] = regs->gpr[rd] << sh;
+                        else
+                                regs->gpr[ra] = 0;
+                        goto logical_done;
+
+                case 539:       /* srd */
+                        sh = regs->gpr[rb] & 0x7f;
+                        if (sh < 64)
+                                regs->gpr[ra] = regs->gpr[rd] >> sh;
+                        else
+                                regs->gpr[ra] = 0;
+                        goto logical_done;
+
+                case 794:       /* srad */
+                        sh = regs->gpr[rb] & 0x7f;
+                        ival = (signed long int) regs->gpr[rd];
+                        regs->gpr[ra] = ival >> (sh < 64 ? sh : 63);
+                        if (ival < 0 && (sh >= 64 || (ival & ((1 << sh) - 1)) != 0))
+                                regs->xer |= XER_CA;
+                        else
+                                regs->xer &= ~XER_CA;
+                        goto logical_done;
+
+                case 826:       /* sradi with sh_5 = 0 */
+                case 827:       /* sradi with sh_5 = 1 */
+                        sh = rb | ((instr & 2) << 4);
+                        ival = (signed long int) regs->gpr[rd];
+                        regs->gpr[ra] = ival >> sh;
+                        if (ival < 0 && (ival & ((1 << sh) - 1)) != 0)
+                                regs->xer |= XER_CA;
+                        else
+                                regs->xer &= ~XER_CA;
+                        goto logical_done;
+#endif /* __powerpc64__ */
+
+/*
+ * Cache instructions
+ */
+                case 54:        /* dcbst */
+                        ea = xform_ea(instr, regs, 0);
+                        if (!address_ok(regs, ea, 8))
+                                return 0;
+                        err = 0;
+                        __cacheop_user_asmx(ea, err, "dcbst");
+                        if (err)
+                                return 0;
+                        goto instr_done;
+
+                case 86:        /* dcbf */
+                        ea = xform_ea(instr, regs, 0);
+                        if (!address_ok(regs, ea, 8))
+                                return 0;
+                        err = 0;
+                        __cacheop_user_asmx(ea, err, "dcbf");
+                        if (err)
+                                return 0;
+                        goto instr_done;
+
+                case 246:       /* dcbtst */
+                        if (rd == 0) {
+                                ea = xform_ea(instr, regs, 0);
+                                prefetchw((void *) ea);
+                        }
+                        goto instr_done;
+
+                case 278:       /* dcbt */
+                        if (rd == 0) {
+                                ea = xform_ea(instr, regs, 0);
+                                prefetch((void *) ea);
+                        }
+                        goto instr_done;
+
                 }
+                break;
         }
-        return 0;
+
+        /*
+         * Following cases are for loads and stores, so bail out
+         * if we're in little-endian mode.
+         */
+        if (regs->msr & MSR_LE)
+                return 0;
+
+        /*
+         * Save register RA in case it's an update form load or store
+         * and the access faults.
+         */
+        old_ra = regs->gpr[ra];
+
+        switch (opcode) {
+        case 31:
+                u = instr & 0x40;
+                switch ((instr >> 1) & 0x3ff) {
+                case 20:        /* lwarx */
+                        ea = xform_ea(instr, regs, 0);
+                        if (ea & 3)
+                                break;          /* can't handle misaligned */
+                        err = -EFAULT;
+                        if (!address_ok(regs, ea, 4))
+                                goto ldst_done;
+                        err = 0;
+                        __get_user_asmx(val, ea, err, "lwarx");
+                        if (!err)
+                                regs->gpr[rd] = val;
+                        goto ldst_done;
+
+                case 150:       /* stwcx. */
+                        ea = xform_ea(instr, regs, 0);
+                        if (ea & 3)
+                                break;          /* can't handle misaligned */
+                        err = -EFAULT;
+                        if (!address_ok(regs, ea, 4))
+                                goto ldst_done;
+                        err = 0;
+                        __put_user_asmx(regs->gpr[rd], ea, err, "stwcx.", cr);
+                        if (!err)
+                                regs->ccr = (regs->ccr & 0x0fffffff) |
+                                        (cr & 0xe0000000) |
+                                        ((regs->xer >> 3) & 0x10000000);
+                        goto ldst_done;
+
+#ifdef __powerpc64__
+                case 84:        /* ldarx */
+                        ea = xform_ea(instr, regs, 0);
+                        if (ea & 7)
+                                break;          /* can't handle misaligned */
+                        err = -EFAULT;
+                        if (!address_ok(regs, ea, 8))
+                                goto ldst_done;
+                        err = 0;
+                        __get_user_asmx(val, ea, err, "ldarx");
+                        if (!err)
+                                regs->gpr[rd] = val;
+                        goto ldst_done;
+
+                case 214:       /* stdcx. */
+                        ea = xform_ea(instr, regs, 0);
+                        if (ea & 7)
+                                break;          /* can't handle misaligned */
+                        err = -EFAULT;
+                        if (!address_ok(regs, ea, 8))
+                                goto ldst_done;
+                        err = 0;
+                        __put_user_asmx(regs->gpr[rd], ea, err, "stdcx.", cr);
+                        if (!err)
+                                regs->ccr = (regs->ccr & 0x0fffffff) |
+                                        (cr & 0xe0000000) |
+                                        ((regs->xer >> 3) & 0x10000000);
+                        goto ldst_done;
+
+                case 21:        /* ldx */
+                case 53:        /* ldux */
+                        err = read_mem(&regs->gpr[rd], xform_ea(instr, regs, u),
+                                       8, regs);
+                        goto ldst_done;
+#endif
+
+                case 23:        /* lwzx */
+                case 55:        /* lwzux */
+                        err = read_mem(&regs->gpr[rd], xform_ea(instr, regs, u),
+                                       4, regs);
+                        goto ldst_done;
+
+                case 87:        /* lbzx */
+                case 119:       /* lbzux */
+                        err = read_mem(&regs->gpr[rd], xform_ea(instr, regs, u),
+                                       1, regs);
+                        goto ldst_done;
+
+#ifdef CONFIG_ALTIVEC
+                case 103:       /* lvx */
+                case 359:       /* lvxl */
+                        if (!(regs->msr & MSR_VEC))
+                                break;
+                        ea = xform_ea(instr, regs, 0);
+                        err = do_vec_load(rd, do_lvx, ea, regs);
+                        goto ldst_done;
+
+                case 231:       /* stvx */
+                case 487:       /* stvxl */
+                        if (!(regs->msr & MSR_VEC))
+                                break;
+                        ea = xform_ea(instr, regs, 0);
+                        err = do_vec_store(rd, do_stvx, ea, regs);
+                        goto ldst_done;
+#endif /* CONFIG_ALTIVEC */
+
+#ifdef __powerpc64__
+                case 149:       /* stdx */
+                case 181:       /* stdux */
+                        val = regs->gpr[rd];
+                        err = write_mem(val, xform_ea(instr, regs, u), 8, regs);
+                        goto ldst_done;
+#endif
+
+                case 151:       /* stwx */
+                case 183:       /* stwux */
+                        val = regs->gpr[rd];
+                        err = write_mem(val, xform_ea(instr, regs, u), 4, regs);
+                        goto ldst_done;
+
+                case 215:       /* stbx */
+                case 247:       /* stbux */
+                        val = regs->gpr[rd];
+                        err = write_mem(val, xform_ea(instr, regs, u), 1, regs);
+                        goto ldst_done;
+
+                case 279:       /* lhzx */
+                case 311:       /* lhzux */
+                        err = read_mem(&regs->gpr[rd], xform_ea(instr, regs, u),
+                                       2, regs);
+                        goto ldst_done;
+
+#ifdef __powerpc64__
+                case 341:       /* lwax */
+                case 373:       /* lwaux */
+                        err = read_mem(&regs->gpr[rd], xform_ea(instr, regs, u),
+                                       4, regs);
+                        if (!err)
+                                regs->gpr[rd] = (signed int) regs->gpr[rd];
+                        goto ldst_done;
+#endif
+
+                case 343:       /* lhax */
+                case 375:       /* lhaux */
+                        err = read_mem(&regs->gpr[rd], xform_ea(instr, regs, u),
+                                       2, regs);
+                        if (!err)
+                                regs->gpr[rd] = (signed short) regs->gpr[rd];
+                        goto ldst_done;
+
+                case 407:       /* sthx */
+                case 439:       /* sthux */
+                        val = regs->gpr[rd];
+                        err = write_mem(val, xform_ea(instr, regs, u), 2, regs);
+                        goto ldst_done;
+
+#ifdef __powerpc64__
+                case 532:       /* ldbrx */
+                        err = read_mem(&val, xform_ea(instr, regs, 0), 8, regs);
+                        if (!err)
+                                regs->gpr[rd] = byterev_8(val);
+                        goto ldst_done;
+
+#endif
+
+                case 534:       /* lwbrx */
+                        err = read_mem(&val, xform_ea(instr, regs, 0), 4, regs);
+                        if (!err)
+                                regs->gpr[rd] = byterev_4(val);
+                        goto ldst_done;
+
+                case 535:       /* lfsx */
+                case 567:       /* lfsux */
+                        if (!(regs->msr & MSR_FP))
+                                break;
+                        ea = xform_ea(instr, regs, u);
+                        err = do_fp_load(rd, do_lfs, ea, 4, regs);
+                        goto ldst_done;
+
+                case 599:       /* lfdx */
+                case 631:       /* lfdux */
+                        if (!(regs->msr & MSR_FP))
+                                break;
+                        ea = xform_ea(instr, regs, u);
+                        err = do_fp_load(rd, do_lfd, ea, 8, regs);
+                        goto ldst_done;
+
+                case 663:       /* stfsx */
+                case 695:       /* stfsux */
+                        if (!(regs->msr & MSR_FP))
+                                break;
+                        ea = xform_ea(instr, regs, u);
+                        err = do_fp_store(rd, do_stfs, ea, 4, regs);
+                        goto ldst_done;
+
+                case 727:       /* stfdx */
+                case 759:       /* stfdux */
+                        if (!(regs->msr & MSR_FP))
+                                break;
+                        ea = xform_ea(instr, regs, u);
+                        err = do_fp_store(rd, do_stfd, ea, 8, regs);
+                        goto ldst_done;
+
+#ifdef __powerpc64__
+                case 660:       /* stdbrx */
+                        val = byterev_8(regs->gpr[rd]);
+                        err = write_mem(val, xform_ea(instr, regs, 0), 8, regs);
+                        goto ldst_done;
+
+#endif
+                case 662:       /* stwbrx */
+                        val = byterev_4(regs->gpr[rd]);
+                        err = write_mem(val, xform_ea(instr, regs, 0), 4, regs);
+                        goto ldst_done;
+
+                case 790:       /* lhbrx */
+                        err = read_mem(&val, xform_ea(instr, regs, 0), 2, regs);
+                        if (!err)
+                                regs->gpr[rd] = byterev_2(val);
+                        goto ldst_done;
+
+                case 918:       /* sthbrx */
+                        val = byterev_2(regs->gpr[rd]);
+                        err = write_mem(val, xform_ea(instr, regs, 0), 2, regs);
+                        goto ldst_done;
+
+#ifdef CONFIG_VSX
+                case 844:       /* lxvd2x */
+                case 876:       /* lxvd2ux */
+                        if (!(regs->msr & MSR_VSX))
+                                break;
+                        rd |= (instr & 1) << 5;
+                        ea = xform_ea(instr, regs, u);
+                        err = do_vsx_load(rd, do_lxvd2x, ea, regs);
+                        goto ldst_done;
+
+                case 972:       /* stxvd2x */
+                case 1004:      /* stxvd2ux */
+                        if (!(regs->msr & MSR_VSX))
+                                break;
+                        rd |= (instr & 1) << 5;
+                        ea = xform_ea(instr, regs, u);
+                        err = do_vsx_store(rd, do_stxvd2x, ea, regs);
+                        goto ldst_done;
+
+#endif /* CONFIG_VSX */
+                }
+                break;
+
+        case 32:        /* lwz */
+        case 33:        /* lwzu */
+                err = read_mem(&regs->gpr[rd], dform_ea(instr, regs), 4, regs);
+                goto ldst_done;
+
+        case 34:        /* lbz */
+        case 35:        /* lbzu */
+                err = read_mem(&regs->gpr[rd], dform_ea(instr, regs), 1, regs);
+                goto ldst_done;
+
+        case 36:        /* stw */
+        case 37:        /* stwu */
+                val = regs->gpr[rd];
+                err = write_mem(val, dform_ea(instr, regs), 4, regs);
+                goto ldst_done;
+
+        case 38:        /* stb */
+        case 39:        /* stbu */
+                val = regs->gpr[rd];
+                err = write_mem(val, dform_ea(instr, regs), 1, regs);
+                goto ldst_done;
+
+        case 40:        /* lhz */
+        case 41:        /* lhzu */
+                err = read_mem(&regs->gpr[rd], dform_ea(instr, regs), 2, regs);
+                goto ldst_done;
+
+        case 42:        /* lha */
+        case 43:        /* lhau */
+                err = read_mem(&regs->gpr[rd], dform_ea(instr, regs), 2, regs);
+                if (!err)
+                        regs->gpr[rd] = (signed short) regs->gpr[rd];
+                goto ldst_done;
+
+        case 44:        /* sth */
+        case 45:        /* sthu */
+                val = regs->gpr[rd];
+                err = write_mem(val, dform_ea(instr, regs), 2, regs);
+                goto ldst_done;
+
+        case 46:        /* lmw */
+                ra = (instr >> 16) & 0x1f;
+                if (ra >= rd)
+                        break;          /* invalid form, ra in range to load */
+                ea = dform_ea(instr, regs);
+                do {
+                        err = read_mem(&regs->gpr[rd], ea, 4, regs);
+                        if (err)
+                                return 0;
+                        ea += 4;
+                } while (++rd < 32);
+                goto instr_done;
+
+        case 47:        /* stmw */
+                ea = dform_ea(instr, regs);
+                do {
+                        err = write_mem(regs->gpr[rd], ea, 4, regs);
+                        if (err)
+                                return 0;
+                        ea += 4;
+                } while (++rd < 32);
+                goto instr_done;
+
+        case 48:        /* lfs */
+        case 49:        /* lfsu */
+                if (!(regs->msr & MSR_FP))
+                        break;
+                ea = dform_ea(instr, regs);
+                err = do_fp_load(rd, do_lfs, ea, 4, regs);
+                goto ldst_done;
+
+        case 50:        /* lfd */
+        case 51:        /* lfdu */
+                if (!(regs->msr & MSR_FP))
+                        break;
+                ea = dform_ea(instr, regs);
+                err = do_fp_load(rd, do_lfd, ea, 8, regs);
+                goto ldst_done;
+
+        case 52:        /* stfs */
+        case 53:        /* stfsu */
+                if (!(regs->msr & MSR_FP))
+                        break;
+                ea = dform_ea(instr, regs);
+                err = do_fp_store(rd, do_stfs, ea, 4, regs);
+                goto ldst_done;
+
+        case 54:        /* stfd */
+        case 55:        /* stfdu */
+                if (!(regs->msr & MSR_FP))
+                        break;
+                ea = dform_ea(instr, regs);
+                err = do_fp_store(rd, do_stfd, ea, 8, regs);
+                goto ldst_done;
+
+#ifdef __powerpc64__
+        case 58:        /* ld[u], lwa */
+                switch (instr & 3) {
+                case 0:         /* ld */
+                        err = read_mem(&regs->gpr[rd], dsform_ea(instr, regs),
+                                       8, regs);
+                        goto ldst_done;
+                case 1:         /* ldu */
+                        err = read_mem(&regs->gpr[rd], dsform_ea(instr, regs),
+                                       8, regs);
+                        goto ldst_done;
+                case 2:         /* lwa */
+                        err = read_mem(&regs->gpr[rd], dsform_ea(instr, regs),
+                                       4, regs);
+                        if (!err)
+                                regs->gpr[rd] = (signed int) regs->gpr[rd];
+                        goto ldst_done;
+                }
+                break;
+
+        case 62:        /* std[u] */
+                val = regs->gpr[rd];
+                switch (instr & 3) {
+                case 0:         /* std */
+                        err = write_mem(val, dsform_ea(instr, regs), 8, regs);
+                        goto ldst_done;
+                case 1:         /* stdu */
+                        err = write_mem(val, dsform_ea(instr, regs), 8, regs);
+                        goto ldst_done;
+                }
+                break;
+#endif /* __powerpc64__ */
+
+        }
+        err = -EINVAL;
+
+ ldst_done:
+        if (err) {
+                regs->gpr[ra] = old_ra;
+                return 0;       /* invoke DSI if -EFAULT? */
+        }
+ instr_done:
+        regs->nip += 4;
+#ifdef __powerpc64__
+        if ((regs->msr & MSR_SF) == 0)
+                regs->nip &= 0xffffffffUL;
+#endif
+        return 1;
+
+ logical_done:
+        if (instr & 1)
+                set_cr0(regs, ra);
+        goto instr_done;
+
+ arith_done:
+        if (instr & 1)
+                set_cr0(regs, rd);
+        goto instr_done;
 }
diff --git a/arch/powerpc/mm/fsl_booke_mmu.c b/arch/powerpc/mm/fsl_booke_mmu.c
index cdc7526e9c93..4b66a1ece6d8 100644
--- a/arch/powerpc/mm/fsl_booke_mmu.c
+++ b/arch/powerpc/mm/fsl_booke_mmu.c
@@ -104,9 +104,10 @@ unsigned long p_mapped_by_tlbcam(phys_addr_t pa)
 }
 
 /*
- * Set up one of the I/D BAT (block address translation) register pairs.
- * The parameters are not checked; in particular size must be a power
- * of 4 between 4k and 256M.
+ * Set up a variable-size TLB entry (tlbcam). The parameters are not checked;
+ * in particular size must be a power of 4 between 4k and 256M (or 1G, for cpus
+ * that support extended page sizes).  Note that while some cpus support a
+ * page size of 4G, we don't allow its use here.
  */
 static void settlbcam(int index, unsigned long virt, phys_addr_t phys,
                 unsigned long size, unsigned long flags, unsigned int pid)
diff --git a/arch/powerpc/mm/numa.c b/arch/powerpc/mm/numa.c
index aa731af720c0..002878ccf90b 100644
--- a/arch/powerpc/mm/numa.c
+++ b/arch/powerpc/mm/numa.c
@@ -42,6 +42,12 @@ EXPORT_SYMBOL(node_data);
 
 static int min_common_depth;
 static int n_mem_addr_cells, n_mem_size_cells;
+static int form1_affinity;
+
+#define MAX_DISTANCE_REF_POINTS 4
+static int distance_ref_points_depth;
+static const unsigned int *distance_ref_points;
+static int distance_lookup_table[MAX_NUMNODES][MAX_DISTANCE_REF_POINTS];
 
 /*
  * Allocate node_to_cpumask_map based on number of available nodes
@@ -204,6 +210,39 @@ static const u32 *of_get_usable_memory(struct device_node *memory)
         return prop;
 }
 
+int __node_distance(int a, int b)
+{
+        int i;
+        int distance = LOCAL_DISTANCE;
+
+        if (!form1_affinity)
+                return distance;
+
+        for (i = 0; i < distance_ref_points_depth; i++) {
+                if (distance_lookup_table[a][i] == distance_lookup_table[b][i])
+                        break;
+
+                /* Double the distance for each NUMA level */
+                distance *= 2;
+        }
+
+        return distance;
+}
+
+static void initialize_distance_lookup_table(int nid,
+                const unsigned int *associativity)
+{
+        int i;
+
+        if (!form1_affinity)
+                return;
+
+        for (i = 0; i < distance_ref_points_depth; i++) {
+                distance_lookup_table[nid][i] =
+                        associativity[distance_ref_points[i]];
+        }
+}
+
 /* Returns nid in the range [0..MAX_NUMNODES-1], or -1 if no useful numa
  * info is found.
  */
@@ -225,6 +264,10 @@ static int of_node_to_nid_single(struct device_node *device)
         /* POWER4 LPAR uses 0xffff as invalid node */
         if (nid == 0xffff || nid >= MAX_NUMNODES)
                 nid = -1;
+
+        if (nid > 0 && tmp[0] >= distance_ref_points_depth)
+                initialize_distance_lookup_table(nid, tmp);
+
 out:
         return nid;
 }
@@ -251,26 +294,10 @@ int of_node_to_nid(struct device_node *device)
 }
 EXPORT_SYMBOL_GPL(of_node_to_nid);
 
-/*
- * In theory, the "ibm,associativity" property may contain multiple
- * associativity lists because a resource may be multiply connected
- * into the machine.  This resource then has different associativity
- * characteristics relative to its multiple connections.  We ignore
- * this for now.  We also assume that all cpu and memory sets have
- * their distances represented at a common level.  This won't be
- * true for hierarchical NUMA.
- *
- * In any case the ibm,associativity-reference-points should give
- * the correct depth for a normal NUMA system.
- *
- * - Dave Hansen <haveblue@us.ibm.com>
- */
 static int __init find_min_common_depth(void)
 {
-        int depth, index;
-        const unsigned int *ref_points;
+        int depth;
         struct device_node *rtas_root;
-        unsigned int len;
         struct device_node *chosen;
         const char *vec5;
 
@@ -280,18 +307,28 @@ static int __init find_min_common_depth(void)
                 return -1;
 
         /*
-         * this property is 2 32-bit integers, each representing a level of
-         * depth in the associativity nodes.  The first is for an SMP
-         * configuration (should be all 0's) and the second is for a normal
-         * NUMA configuration.
+         * This property is a set of 32-bit integers, each representing
+         * an index into the ibm,associativity nodes.
+         *
+         * With form 0 affinity the first integer is for an SMP configuration
+         * (should be all 0's) and the second is for a normal NUMA
+         * configuration. We have only one level of NUMA.
+         *
+         * With form 1 affinity the first integer is the most significant
+         * NUMA boundary and the following are progressively less significant
+         * boundaries. There can be more than one level of NUMA.
          */
-        index = 1;
-        ref_points = of_get_property(rtas_root,
-                        "ibm,associativity-reference-points", &len);
+        distance_ref_points = of_get_property(rtas_root,
+                                        "ibm,associativity-reference-points",
+                                        &distance_ref_points_depth);
+
+        if (!distance_ref_points) {
+                dbg("NUMA: ibm,associativity-reference-points not found.\n");
+                goto err;
+        }
+
+        distance_ref_points_depth /= sizeof(int);
 
-        /*
-         * For form 1 affinity information we want the first field
-         */
 #define VEC5_AFFINITY_BYTE      5
 #define VEC5_AFFINITY           0x80
         chosen = of_find_node_by_path("/chosen");
@@ -299,19 +336,38 @@ static int __init find_min_common_depth(void)
                 vec5 = of_get_property(chosen, "ibm,architecture-vec-5", NULL);
                 if (vec5 && (vec5[VEC5_AFFINITY_BYTE] & VEC5_AFFINITY)) {
                         dbg("Using form 1 affinity\n");
-                        index = 0;
+                        form1_affinity = 1;
                 }
         }
 
-        if ((len >= 2 * sizeof(unsigned int)) && ref_points) {
-                depth = ref_points[index];
+        if (form1_affinity) {
+                depth = distance_ref_points[0];
         } else {
-                dbg("NUMA: ibm,associativity-reference-points not found.\n");
-                depth = -1;
+                if (distance_ref_points_depth < 2) {
+                        printk(KERN_WARNING "NUMA: "
+                                "short ibm,associativity-reference-points\n");
+                        goto err;
+                }
+
+                depth = distance_ref_points[1];
         }
-        of_node_put(rtas_root);
 
+        /*
+         * Warn and cap if the hardware supports more than
+         * MAX_DISTANCE_REF_POINTS domains.
+         */
+        if (distance_ref_points_depth > MAX_DISTANCE_REF_POINTS) {
+                printk(KERN_WARNING "NUMA: distance array capped at "
+                        "%d entries\n", MAX_DISTANCE_REF_POINTS);
+                distance_ref_points_depth = MAX_DISTANCE_REF_POINTS;
+        }
+
+        of_node_put(rtas_root);
         return depth;
+
+err:
+        of_node_put(rtas_root);
+        return -1;
 }
 
 static void __init get_n_mem_cells(int *n_addr_cells, int *n_size_cells)
diff --git a/arch/powerpc/mm/pgtable.c b/arch/powerpc/mm/pgtable.c
index ebc2f38eb381..2c7e801ab20b 100644
--- a/arch/powerpc/mm/pgtable.c
+++ b/arch/powerpc/mm/pgtable.c
@@ -92,7 +92,6 @@ static void pte_free_rcu_callback(struct rcu_head *head)
 
 static void pte_free_submit(struct pte_freelist_batch *batch)
 {
-        INIT_RCU_HEAD(&batch->rcu);
         call_rcu(&batch->rcu, pte_free_rcu_callback);
 }
 
diff --git a/arch/powerpc/mm/tlb_hash32.c b/arch/powerpc/mm/tlb_hash32.c
index 8aaa8b7eb324..690566b66e8e 100644
--- a/arch/powerpc/mm/tlb_hash32.c
+++ b/arch/powerpc/mm/tlb_hash32.c
@@ -89,17 +89,6 @@ void tlb_flush(struct mmu_gather *tlb)
  *    -- Cort
  */
 
-/*
- * 750 SMP is a Bad Idea because the 750 doesn't broadcast all
- * the cache operations on the bus.  Hence we need to use an IPI
- * to get the other CPU(s) to invalidate their TLBs.
- */
-#ifdef CONFIG_SMP_750
-#define FINISH_FLUSH    smp_send_tlb_invalidate(0)
-#else
-#define FINISH_FLUSH    do { } while (0)
-#endif
-
 static void flush_range(struct mm_struct *mm, unsigned long start,
                         unsigned long end)
 {
@@ -138,7 +127,6 @@ static void flush_range(struct mm_struct *mm, unsigned long start,
 void flush_tlb_kernel_range(unsigned long start, unsigned long end)
 {
         flush_range(&init_mm, start, end);
-        FINISH_FLUSH;
 }
 EXPORT_SYMBOL(flush_tlb_kernel_range);
 
@@ -162,7 +150,6 @@ void flush_tlb_mm(struct mm_struct *mm)
          */
         for (mp = mm->mmap; mp != NULL; mp = mp->vm_next)
                 flush_range(mp->vm_mm, mp->vm_start, mp->vm_end);
-        FINISH_FLUSH;
 }
 EXPORT_SYMBOL(flush_tlb_mm);
 
@@ -179,7 +166,6 @@ void flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
         pmd = pmd_offset(pud_offset(pgd_offset(mm, vmaddr), vmaddr), vmaddr);
         if (!pmd_none(*pmd))
                 flush_hash_pages(mm->context.id, vmaddr, pmd_val(*pmd), 1);
-        FINISH_FLUSH;
 }
 EXPORT_SYMBOL(flush_tlb_page);
 
@@ -192,6 +178,5 @@ void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
                      unsigned long end)
 {
         flush_range(vma->vm_mm, start, end);
-        FINISH_FLUSH;
 }
 EXPORT_SYMBOL(flush_tlb_range);
diff --git a/arch/powerpc/mm/tlb_nohash.c b/arch/powerpc/mm/tlb_nohash.c
index d8695b02a968..fe391e942521 100644
--- a/arch/powerpc/mm/tlb_nohash.c
+++ b/arch/powerpc/mm/tlb_nohash.c
@@ -46,6 +46,7 @@
 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT] = {
         [MMU_PAGE_4K] = {
                 .shift  = 12,
+                .ind    = 20,
                 .enc    = BOOK3E_PAGESZ_4K,
         },
         [MMU_PAGE_16K] = {
@@ -54,6 +55,7 @@ struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT] = {
         },
         [MMU_PAGE_64K] = {
                 .shift  = 16,
+                .ind    = 28,
                 .enc    = BOOK3E_PAGESZ_64K,
         },
         [MMU_PAGE_1M] = {
@@ -62,6 +64,7 @@ struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT] = {
         },
         [MMU_PAGE_16M] = {
                 .shift  = 24,
+                .ind    = 36,
                 .enc    = BOOK3E_PAGESZ_16M,
         },
         [MMU_PAGE_256M] = {
@@ -344,16 +347,108 @@ void tlb_flush_pgtable(struct mmu_gather *tlb, unsigned long address)
         }
 }
 
-/*
- * Early initialization of the MMU TLB code
- */
-static void __early_init_mmu(int boot_cpu)
+static void setup_page_sizes(void)
+{
+        unsigned int tlb0cfg = mfspr(SPRN_TLB0CFG);
+        unsigned int tlb0ps = mfspr(SPRN_TLB0PS);
+        unsigned int eptcfg = mfspr(SPRN_EPTCFG);
+        int i, psize;
+
+        /* Look for supported direct sizes */
+        for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) {
+                struct mmu_psize_def *def = &mmu_psize_defs[psize];
+
+                if (tlb0ps & (1U << (def->shift - 10)))
+                        def->flags |= MMU_PAGE_SIZE_DIRECT;
+        }
+
+        /* Indirect page sizes supported ? */
+        if ((tlb0cfg & TLBnCFG_IND) == 0)
+                goto no_indirect;
+
+        /* Now, we only deal with one IND page size for each
+         * direct size. Hopefully all implementations today are
+         * unambiguous, but we might want to be careful in the
+         * future.
+         */
+        for (i = 0; i < 3; i++) {
+                unsigned int ps, sps;
+
+                sps = eptcfg & 0x1f;
+                eptcfg >>= 5;
+                ps = eptcfg & 0x1f;
+                eptcfg >>= 5;
+                if (!ps || !sps)
+                        continue;
+                for (psize = 0; psize < MMU_PAGE_COUNT; psize++) {
+                        struct mmu_psize_def *def = &mmu_psize_defs[psize];
+
+                        if (ps == (def->shift - 10))
+                                def->flags |= MMU_PAGE_SIZE_INDIRECT;
+                        if (sps == (def->shift - 10))
+                                def->ind = ps + 10;
+                }
+        }
+ no_indirect:
+
+        /* Cleanup array and print summary */
+        pr_info("MMU: Supported page sizes\n");
+        for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) {
+                struct mmu_psize_def *def = &mmu_psize_defs[psize];
+                const char *__page_type_names[] = {
+                        "unsupported",
+                        "direct",
+                        "indirect",
+                        "direct & indirect"
+                };
+                if (def->flags == 0) {
+                        def->shift = 0; 
+                        continue;
+                }
+                pr_info("  %8ld KB as %s\n", 1ul << (def->shift - 10),
+                        __page_type_names[def->flags & 0x3]);
+        }
+}
+
+static void setup_mmu_htw(void)
 {
         extern unsigned int interrupt_base_book3e;
         extern unsigned int exc_data_tlb_miss_htw_book3e;
         extern unsigned int exc_instruction_tlb_miss_htw_book3e;
 
         unsigned int *ibase = &interrupt_base_book3e;
+
+        /* Check if HW tablewalk is present, and if yes, enable it by:
+         *
+         * - patching the TLB miss handlers to branch to the
+         *   one dedicates to it
+         *
+         * - setting the global book3e_htw_enabled
+         */
+        unsigned int tlb0cfg = mfspr(SPRN_TLB0CFG);
+
+        if ((tlb0cfg & TLBnCFG_IND) &&
+            (tlb0cfg & TLBnCFG_PT)) {
+                /* Our exceptions vectors start with a NOP and -then- a branch
+                 * to deal with single stepping from userspace which stops on
+                 * the second instruction. Thus we need to patch the second
+                 * instruction of the exception, not the first one
+                 */
+                patch_branch(ibase + (0x1c0 / 4) + 1,
+                             (unsigned long)&exc_data_tlb_miss_htw_book3e, 0);
+                patch_branch(ibase + (0x1e0 / 4) + 1,
+                             (unsigned long)&exc_instruction_tlb_miss_htw_book3e, 0);
+                book3e_htw_enabled = 1;
+        }
+        pr_info("MMU: Book3E Page Tables %s\n",
+                book3e_htw_enabled ? "Enabled" : "Disabled");
+}
+
+/*
+ * Early initialization of the MMU TLB code
+ */
+static void __early_init_mmu(int boot_cpu)
+{
         unsigned int mas4;
 
         /* XXX This will have to be decided at runtime, but right
@@ -370,35 +465,17 @@ static void __early_init_mmu(int boot_cpu)
          */
         mmu_vmemmap_psize = MMU_PAGE_16M;
 
-        /* Check if HW tablewalk is present, and if yes, enable it by:
-         *
-         * - patching the TLB miss handlers to branch to the
-         *   one dedicates to it
-         *
-         * - setting the global book3e_htw_enabled
-         *
-         * - Set MAS4:INDD and default page size
-         */
-
         /* XXX This code only checks for TLB 0 capabilities and doesn't
          *     check what page size combos are supported by the HW. It
          *     also doesn't handle the case where a separate array holds
          *     the IND entries from the array loaded by the PT.
          */
         if (boot_cpu) {
-                unsigned int tlb0cfg = mfspr(SPRN_TLB0CFG);
+                /* Look for supported page sizes */
+                setup_page_sizes();
 
-                /* Check if HW loader is supported */
-                if ((tlb0cfg & TLBnCFG_IND) &&
-                    (tlb0cfg & TLBnCFG_PT)) {
-                        patch_branch(ibase + (0x1c0 / 4),
-                             (unsigned long)&exc_data_tlb_miss_htw_book3e, 0);
-                        patch_branch(ibase + (0x1e0 / 4),
-                             (unsigned long)&exc_instruction_tlb_miss_htw_book3e, 0);
-                        book3e_htw_enabled = 1;
-                }
-                pr_info("MMU: Book3E Page Tables %s\n",
-                        book3e_htw_enabled ? "Enabled" : "Disabled");
+                /* Look for HW tablewalk support */
+                setup_mmu_htw();
         }
 
         /* Set MAS4 based on page table setting */
diff --git a/arch/powerpc/oprofile/Makefile b/arch/powerpc/oprofile/Makefile
index 73e1c2ca0552..e219ca43962d 100644
--- a/arch/powerpc/oprofile/Makefile
+++ b/arch/powerpc/oprofile/Makefile
@@ -16,6 +16,6 @@ oprofile-y := $(DRIVER_OBJS) common.o backtrace.o
 oprofile-$(CONFIG_OPROFILE_CELL) += op_model_cell.o \
                 cell/spu_profiler.o cell/vma_map.o \
                 cell/spu_task_sync.o
-oprofile-$(CONFIG_PPC64) += op_model_rs64.o op_model_power4.o op_model_pa6t.o
+oprofile-$(CONFIG_PPC_BOOK3S_64) += op_model_rs64.o op_model_power4.o op_model_pa6t.o
 oprofile-$(CONFIG_FSL_EMB_PERFMON) += op_model_fsl_emb.o
 oprofile-$(CONFIG_6xx) += op_model_7450.o
diff --git a/arch/powerpc/oprofile/common.c b/arch/powerpc/oprofile/common.c
index 21f16edf6c8d..d65e68f3cb25 100644
--- a/arch/powerpc/oprofile/common.c
+++ b/arch/powerpc/oprofile/common.c
@@ -199,7 +199,7 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
                 return -ENODEV;
 
         switch (cur_cpu_spec->oprofile_type) {
-#ifdef CONFIG_PPC64
+#ifdef CONFIG_PPC_BOOK3S_64
 #ifdef CONFIG_OPROFILE_CELL
                 case PPC_OPROFILE_CELL:
                         if (firmware_has_feature(FW_FEATURE_LPAR))
diff --git a/arch/powerpc/platforms/40x/Kconfig b/arch/powerpc/platforms/40x/Kconfig
index ec64264f7a50..b72176434ebe 100644
--- a/arch/powerpc/platforms/40x/Kconfig
+++ b/arch/powerpc/platforms/40x/Kconfig
@@ -71,22 +71,6 @@ config MAKALU
         help
           This option enables support for the AMCC PPC405EX board.
 
-#config REDWOOD_5
-#       bool "Redwood-5"
-#       depends on 40x
-#       default n
-#       select STB03xxx
-#       help
-#         This option enables support for the IBM STB04 evaluation board.
-
-#config REDWOOD_6
-#       bool "Redwood-6"
-#       depends on 40x
-#       default n
-#       select STB03xxx
-#       help
-#         This option enables support for the IBM STBx25xx evaluation board.
-
 #config SYCAMORE
 #       bool "Sycamore"
 #       depends on 40x
diff --git a/arch/powerpc/platforms/512x/Kconfig b/arch/powerpc/platforms/512x/Kconfig
index 4dac9b0525a4..27b0651221d1 100644
--- a/arch/powerpc/platforms/512x/Kconfig
+++ b/arch/powerpc/platforms/512x/Kconfig
@@ -1,32 +1,34 @@
 config PPC_MPC512x
-        bool
+        bool "512x-based boards"
+        depends on 6xx
         select FSL_SOC
         select IPIC
         select PPC_CLOCK
         select PPC_PCI_CHOICE
         select FSL_PCI if PCI
 
-config PPC_MPC5121
-        bool
-        select PPC_MPC512x
-
 config MPC5121_ADS
         bool "Freescale MPC5121E ADS"
-        depends on 6xx
+        depends on PPC_MPC512x
         select DEFAULT_UIMAGE
-        select PPC_MPC5121
         select MPC5121_ADS_CPLD
         help
           This option enables support for the MPC5121E ADS board.
 
 config MPC5121_GENERIC
         bool "Generic support for simple MPC5121 based boards"
-        depends on 6xx
+        depends on PPC_MPC512x
         select DEFAULT_UIMAGE
-        select PPC_MPC5121
         help
           This option enables support for simple MPC5121 based boards
           which do not need custom platform specific setup.
 
           Compatible boards include:  Protonic LVT base boards (ZANMCU
           and VICVT2).
+
+config PDM360NG
+        bool "ifm PDM360NG board"
+        depends on PPC_MPC512x
+        select DEFAULT_UIMAGE
+        help
+          This option enables support for the PDM360NG board.
diff --git a/arch/powerpc/platforms/512x/Makefile b/arch/powerpc/platforms/512x/Makefile
index 90be2f5717e6..4efc1c4b6fb5 100644
--- a/arch/powerpc/platforms/512x/Makefile
+++ b/arch/powerpc/platforms/512x/Makefile
@@ -4,3 +4,4 @@
 obj-y                           += clock.o mpc512x_shared.o
 obj-$(CONFIG_MPC5121_ADS)       += mpc5121_ads.o mpc5121_ads_cpld.o
 obj-$(CONFIG_MPC5121_GENERIC)   += mpc5121_generic.o
+obj-$(CONFIG_PDM360NG)          += pdm360ng.o
diff --git a/arch/powerpc/platforms/512x/clock.c b/arch/powerpc/platforms/512x/clock.c
index 4c42246b86a7..e1c5cd6650b1 100644
--- a/arch/powerpc/platforms/512x/clock.c
+++ b/arch/powerpc/platforms/512x/clock.c
@@ -292,6 +292,15 @@ static void diu_clk_calc(struct clk *clk)
         clk->rate = rate;
 }
 
+static void viu_clk_calc(struct clk *clk)
+{
+        unsigned long rate;
+
+        rate = sys_clk.rate;
+        rate /= 2;
+        clk->rate = rate;
+}
+
 static void half_clk_calc(struct clk *clk)
 {
         clk->rate = clk->parent->rate / 2;
@@ -412,6 +421,14 @@ static struct clk diu_clk = {
         .calc = diu_clk_calc,
 };
 
+static struct clk viu_clk = {
+        .name = "viu_clk",
+        .flags = CLK_HAS_CTRL,
+        .reg = 1,
+        .bit = 18,
+        .calc = viu_clk_calc,
+};
+
 static struct clk axe_clk = {
         .name = "axe_clk",
         .flags = CLK_HAS_CTRL,
@@ -535,6 +552,7 @@ struct clk *rate_clks[] = {
         &ref_clk,
         &sys_clk,
         &diu_clk,
+        &viu_clk,
         &csb_clk,
         &e300_clk,
         &ips_clk,
diff --git a/arch/powerpc/platforms/512x/mpc5121_ads.c b/arch/powerpc/platforms/512x/mpc5121_ads.c
index ee6ae129c25c..dcef6ade48e1 100644
--- a/arch/powerpc/platforms/512x/mpc5121_ads.c
+++ b/arch/powerpc/platforms/512x/mpc5121_ads.c
@@ -42,6 +42,7 @@ static void __init mpc5121_ads_setup_arch(void)
         for_each_compatible_node(np, "pci", "fsl,mpc5121-pci")
                 mpc83xx_add_bridge(np);
 #endif
+        mpc512x_setup_diu();
 }
 
 static void __init mpc5121_ads_init_IRQ(void)
@@ -65,6 +66,7 @@ define_machine(mpc5121_ads) {
         .probe                  = mpc5121_ads_probe,
         .setup_arch             = mpc5121_ads_setup_arch,
         .init                   = mpc512x_init,
+        .init_early             = mpc512x_init_diu,
         .init_IRQ               = mpc5121_ads_init_IRQ,
         .get_irq                = ipic_get_irq,
         .calibrate_decr         = generic_calibrate_decr,
diff --git a/arch/powerpc/platforms/512x/mpc5121_generic.c b/arch/powerpc/platforms/512x/mpc5121_generic.c
index a6c0e3a2615d..e487eb06ec6b 100644
--- a/arch/powerpc/platforms/512x/mpc5121_generic.c
+++ b/arch/powerpc/platforms/512x/mpc5121_generic.c
@@ -52,6 +52,8 @@ define_machine(mpc5121_generic) {
         .name                   = "MPC5121 generic",
         .probe                  = mpc5121_generic_probe,
         .init                   = mpc512x_init,
+        .init_early             = mpc512x_init_diu,
+        .setup_arch             = mpc512x_setup_diu,
         .init_IRQ               = mpc512x_init_IRQ,
         .get_irq                = ipic_get_irq,
         .calibrate_decr         = generic_calibrate_decr,
diff --git a/arch/powerpc/platforms/512x/mpc512x.h b/arch/powerpc/platforms/512x/mpc512x.h
index b2daca0d1488..1ab6d11d0b19 100644
--- a/arch/powerpc/platforms/512x/mpc512x.h
+++ b/arch/powerpc/platforms/512x/mpc512x.h
@@ -16,4 +16,6 @@ extern void __init mpc512x_init(void);
 extern int __init mpc5121_clk_init(void);
 void __init mpc512x_declare_of_platform_devices(void);
 extern void mpc512x_restart(char *cmd);
+extern void mpc512x_init_diu(void);
+extern void mpc512x_setup_diu(void);
 #endif                          /* __MPC512X_H__ */
diff --git a/arch/powerpc/platforms/512x/mpc512x_shared.c b/arch/powerpc/platforms/512x/mpc512x_shared.c
index 707e572b7c40..e41ebbdb3e12 100644
--- a/arch/powerpc/platforms/512x/mpc512x_shared.c
+++ b/arch/powerpc/platforms/512x/mpc512x_shared.c
@@ -16,7 +16,11 @@
 #include <linux/io.h>
 #include <linux/irq.h>
 #include <linux/of_platform.h>
+#include <linux/fsl-diu-fb.h>
+#include <linux/bootmem.h>
+#include <sysdev/fsl_soc.h>
 
+#include <asm/cacheflush.h>
 #include <asm/machdep.h>
 #include <asm/ipic.h>
 #include <asm/prom.h>
@@ -54,6 +58,286 @@ void mpc512x_restart(char *cmd)
                 ;
 }
 
+struct fsl_diu_shared_fb {
+        u8              gamma[0x300];   /* 32-bit aligned! */
+        struct diu_ad   ad0;            /* 32-bit aligned! */
+        phys_addr_t     fb_phys;
+        size_t          fb_len;
+        bool            in_use;
+};
+
+unsigned int mpc512x_get_pixel_format(unsigned int bits_per_pixel,
+                                      int monitor_port)
+{
+        switch (bits_per_pixel) {
+        case 32:
+                return 0x88883316;
+        case 24:
+                return 0x88082219;
+        case 16:
+                return 0x65053118;
+        }
+        return 0x00000400;
+}
+
+void mpc512x_set_gamma_table(int monitor_port, char *gamma_table_base)
+{
+}
+
+void mpc512x_set_monitor_port(int monitor_port)
+{
+}
+
+#define DIU_DIV_MASK    0x000000ff
+void mpc512x_set_pixel_clock(unsigned int pixclock)
+{
+        unsigned long bestval, bestfreq, speed, busfreq;
+        unsigned long minpixclock, maxpixclock, pixval;
+        struct mpc512x_ccm __iomem *ccm;
+        struct device_node *np;
+        u32 temp;
+        long err;
+        int i;
+
+        np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-clock");
+        if (!np) {
+                pr_err("Can't find clock control module.\n");
+                return;
+        }
+
+        ccm = of_iomap(np, 0);
+        of_node_put(np);
+        if (!ccm) {
+                pr_err("Can't map clock control module reg.\n");
+                return;
+        }
+
+        np = of_find_node_by_type(NULL, "cpu");
+        if (np) {
+                const unsigned int *prop =
+                        of_get_property(np, "bus-frequency", NULL);
+
+                of_node_put(np);
+                if (prop) {
+                        busfreq = *prop;
+                } else {
+                        pr_err("Can't get bus-frequency property\n");
+                        return;
+                }
+        } else {
+                pr_err("Can't find 'cpu' node.\n");
+                return;
+        }
+
+        /* Pixel Clock configuration */
+        pr_debug("DIU: Bus Frequency = %lu\n", busfreq);
+        speed = busfreq * 4; /* DIU_DIV ratio is 4 * CSB_CLK / DIU_CLK */
+
+        /* Calculate the pixel clock with the smallest error */
+        /* calculate the following in steps to avoid overflow */
+        pr_debug("DIU pixclock in ps - %d\n", pixclock);
+        temp = (1000000000 / pixclock) * 1000;
+        pixclock = temp;
+        pr_debug("DIU pixclock freq - %u\n", pixclock);
+
+        temp = temp / 20; /* pixclock * 0.05 */
+        pr_debug("deviation = %d\n", temp);
+        minpixclock = pixclock - temp;
+        maxpixclock = pixclock + temp;
+        pr_debug("DIU minpixclock - %lu\n", minpixclock);
+        pr_debug("DIU maxpixclock - %lu\n", maxpixclock);
+        pixval = speed/pixclock;
+        pr_debug("DIU pixval = %lu\n", pixval);
+
+        err = LONG_MAX;
+        bestval = pixval;
+        pr_debug("DIU bestval = %lu\n", bestval);
+
+        bestfreq = 0;
+        for (i = -1; i <= 1; i++) {
+                temp = speed / (pixval+i);
+                pr_debug("DIU test pixval i=%d, pixval=%lu, temp freq. = %u\n",
+                        i, pixval, temp);
+                if ((temp < minpixclock) || (temp > maxpixclock))
+                        pr_debug("DIU exceeds monitor range (%lu to %lu)\n",
+                                minpixclock, maxpixclock);
+                else if (abs(temp - pixclock) < err) {
+                        pr_debug("Entered the else if block %d\n", i);
+                        err = abs(temp - pixclock);
+                        bestval = pixval + i;
+                        bestfreq = temp;
+                }
+        }
+
+        pr_debug("DIU chose = %lx\n", bestval);
+        pr_debug("DIU error = %ld\n NomPixClk ", err);
+        pr_debug("DIU: Best Freq = %lx\n", bestfreq);
+        /* Modify DIU_DIV in CCM SCFR1 */
+        temp = in_be32(&ccm->scfr1);
+        pr_debug("DIU: Current value of SCFR1: 0x%08x\n", temp);
+        temp &= ~DIU_DIV_MASK;
+        temp |= (bestval & DIU_DIV_MASK);
+        out_be32(&ccm->scfr1, temp);
+        pr_debug("DIU: Modified value of SCFR1: 0x%08x\n", temp);
+        iounmap(ccm);
+}
+
+ssize_t mpc512x_show_monitor_port(int monitor_port, char *buf)
+{
+        return sprintf(buf, "0 - 5121 LCD\n");
+}
+
+int mpc512x_set_sysfs_monitor_port(int val)
+{
+        return 0;
+}
+
+static struct fsl_diu_shared_fb __attribute__ ((__aligned__(8))) diu_shared_fb;
+
+#if defined(CONFIG_FB_FSL_DIU) || \
+    defined(CONFIG_FB_FSL_DIU_MODULE)
+static inline void mpc512x_free_bootmem(struct page *page)
+{
+        __ClearPageReserved(page);
+        BUG_ON(PageTail(page));
+        BUG_ON(atomic_read(&page->_count) > 1);
+        atomic_set(&page->_count, 1);
+        __free_page(page);
+        totalram_pages++;
+}
+
+void mpc512x_release_bootmem(void)
+{
+        unsigned long addr = diu_shared_fb.fb_phys & PAGE_MASK;
+        unsigned long size = diu_shared_fb.fb_len;
+        unsigned long start, end;
+
+        if (diu_shared_fb.in_use) {
+                start = PFN_UP(addr);
+                end = PFN_DOWN(addr + size);
+
+                for (; start < end; start++)
+                        mpc512x_free_bootmem(pfn_to_page(start));
+
+                diu_shared_fb.in_use = false;
+        }
+        diu_ops.release_bootmem = NULL;
+}
+#endif
+
+/*
+ * Check if DIU was pre-initialized. If so, perform steps
+ * needed to continue displaying through the whole boot process.
+ * Move area descriptor and gamma table elsewhere, they are
+ * destroyed by bootmem allocator otherwise. The frame buffer
+ * address range will be reserved in setup_arch() after bootmem
+ * allocator is up.
+ */
+void __init mpc512x_init_diu(void)
+{
+        struct device_node *np;
+        struct diu __iomem *diu_reg;
+        phys_addr_t desc;
+        void __iomem *vaddr;
+        unsigned long mode, pix_fmt, res, bpp;
+        unsigned long dst;
+
+        np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-diu");
+        if (!np) {
+                pr_err("No DIU node\n");
+                return;
+        }
+
+        diu_reg = of_iomap(np, 0);
+        of_node_put(np);
+        if (!diu_reg) {
+                pr_err("Can't map DIU\n");
+                return;
+        }
+
+        mode = in_be32(&diu_reg->diu_mode);
+        if (mode != MFB_MODE1) {
+                pr_info("%s: DIU OFF\n", __func__);
+                goto out;
+        }
+
+        desc = in_be32(&diu_reg->desc[0]);
+        vaddr = ioremap(desc, sizeof(struct diu_ad));
+        if (!vaddr) {
+                pr_err("Can't map DIU area desc.\n");
+                goto out;
+        }
+        memcpy(&diu_shared_fb.ad0, vaddr, sizeof(struct diu_ad));
+        /* flush fb area descriptor */
+        dst = (unsigned long)&diu_shared_fb.ad0;
+        flush_dcache_range(dst, dst + sizeof(struct diu_ad) - 1);
+
+        res = in_be32(&diu_reg->disp_size);
+        pix_fmt = in_le32(vaddr);
+        bpp = ((pix_fmt >> 16) & 0x3) + 1;
+        diu_shared_fb.fb_phys = in_le32(vaddr + 4);
+        diu_shared_fb.fb_len = ((res & 0xfff0000) >> 16) * (res & 0xfff) * bpp;
+        diu_shared_fb.in_use = true;
+        iounmap(vaddr);
+
+        desc = in_be32(&diu_reg->gamma);
+        vaddr = ioremap(desc, sizeof(diu_shared_fb.gamma));
+        if (!vaddr) {
+                pr_err("Can't map DIU area desc.\n");
+                diu_shared_fb.in_use = false;
+                goto out;
+        }
+        memcpy(&diu_shared_fb.gamma, vaddr, sizeof(diu_shared_fb.gamma));
+        /* flush gamma table */
+        dst = (unsigned long)&diu_shared_fb.gamma;
+        flush_dcache_range(dst, dst + sizeof(diu_shared_fb.gamma) - 1);
+
+        iounmap(vaddr);
+        out_be32(&diu_reg->gamma, virt_to_phys(&diu_shared_fb.gamma));
+        out_be32(&diu_reg->desc[1], 0);
+        out_be32(&diu_reg->desc[2], 0);
+        out_be32(&diu_reg->desc[0], virt_to_phys(&diu_shared_fb.ad0));
+
+out:
+        iounmap(diu_reg);
+}
+
+void __init mpc512x_setup_diu(void)
+{
+        int ret;
+
+        /*
+         * We do not allocate and configure new area for bitmap buffer
+         * because it would requere copying bitmap data (splash image)
+         * and so negatively affect boot time. Instead we reserve the
+         * already configured frame buffer area so that it won't be
+         * destroyed. The starting address of the area to reserve and
+         * also it's length is passed to reserve_bootmem(). It will be
+         * freed later on first open of fbdev, when splash image is not
+         * needed any more.
+         */
+        if (diu_shared_fb.in_use) {
+                ret = reserve_bootmem(diu_shared_fb.fb_phys,
+                                      diu_shared_fb.fb_len,
+                                      BOOTMEM_EXCLUSIVE);
+                if (ret) {
+                        pr_err("%s: reserve bootmem failed\n", __func__);
+                        diu_shared_fb.in_use = false;
+                }
+        }
+
+#if defined(CONFIG_FB_FSL_DIU) || \
+    defined(CONFIG_FB_FSL_DIU_MODULE)
+        diu_ops.get_pixel_format        = mpc512x_get_pixel_format;
+        diu_ops.set_gamma_table         = mpc512x_set_gamma_table;
+        diu_ops.set_monitor_port        = mpc512x_set_monitor_port;
+        diu_ops.set_pixel_clock         = mpc512x_set_pixel_clock;
+        diu_ops.show_monitor_port       = mpc512x_show_monitor_port;
+        diu_ops.set_sysfs_monitor_port  = mpc512x_set_sysfs_monitor_port;
+        diu_ops.release_bootmem         = mpc512x_release_bootmem;
+#endif
+}
+
 void __init mpc512x_init_IRQ(void)
 {
         struct device_node *np;
diff --git a/arch/powerpc/platforms/512x/pdm360ng.c b/arch/powerpc/platforms/512x/pdm360ng.c
new file mode 100644
index 000000000000..0575e858291c
--- /dev/null
+++ b/arch/powerpc/platforms/512x/pdm360ng.c
@@ -0,0 +1,129 @@
+/*
+ * Copyright (C) 2010 DENX Software Engineering
+ *
+ * Anatolij Gustschin, <agust@denx.de>
+ *
+ * PDM360NG board setup
+ *
+ * This is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/of_platform.h>
+
+#include <asm/machdep.h>
+#include <asm/ipic.h>
+
+#include "mpc512x.h"
+
+#if defined(CONFIG_TOUCHSCREEN_ADS7846) || \
+    defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
+#include <linux/interrupt.h>
+#include <linux/spi/ads7846.h>
+#include <linux/spi/spi.h>
+#include <linux/notifier.h>
+
+static void *pdm360ng_gpio_base;
+
+static int pdm360ng_get_pendown_state(void)
+{
+        u32 reg;
+
+        reg = in_be32(pdm360ng_gpio_base + 0xc);
+        if (reg & 0x40)
+                setbits32(pdm360ng_gpio_base + 0xc, 0x40);
+
+        reg = in_be32(pdm360ng_gpio_base + 0x8);
+
+        /* return 1 if pen is down */
+        return (reg & 0x40) == 0;
+}
+
+static struct ads7846_platform_data pdm360ng_ads7846_pdata = {
+        .model                  = 7845,
+        .get_pendown_state      = pdm360ng_get_pendown_state,
+        .irq_flags              = IRQF_TRIGGER_LOW,
+};
+
+static int __init pdm360ng_penirq_init(void)
+{
+        struct device_node *np;
+
+        np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-gpio");
+        if (!np) {
+                pr_err("%s: Can't find 'mpc5121-gpio' node\n", __func__);
+                return -ENODEV;
+        }
+
+        pdm360ng_gpio_base = of_iomap(np, 0);
+        of_node_put(np);
+        if (!pdm360ng_gpio_base) {
+                pr_err("%s: Can't map gpio regs.\n", __func__);
+                return -ENODEV;
+        }
+        out_be32(pdm360ng_gpio_base + 0xc, 0xffffffff);
+        setbits32(pdm360ng_gpio_base + 0x18, 0x2000);
+        setbits32(pdm360ng_gpio_base + 0x10, 0x40);
+
+        return 0;
+}
+
+static int pdm360ng_touchscreen_notifier_call(struct notifier_block *nb,
+                                        unsigned long event, void *__dev)
+{
+        struct device *dev = __dev;
+
+        if ((event == BUS_NOTIFY_ADD_DEVICE) &&
+            of_device_is_compatible(dev->of_node, "ti,ads7846")) {
+                dev->platform_data = &pdm360ng_ads7846_pdata;
+                return NOTIFY_OK;
+        }
+        return NOTIFY_DONE;
+}
+
+static struct notifier_block pdm360ng_touchscreen_nb = {
+        .notifier_call = pdm360ng_touchscreen_notifier_call,
+};
+
+static void __init pdm360ng_touchscreen_init(void)
+{
+        if (pdm360ng_penirq_init())
+                return;
+
+        bus_register_notifier(&spi_bus_type, &pdm360ng_touchscreen_nb);
+}
+#else
+static inline void __init pdm360ng_touchscreen_init(void)
+{
+}
+#endif /* CONFIG_TOUCHSCREEN_ADS7846 */
+
+void __init pdm360ng_init(void)
+{
+        mpc512x_init();
+        pdm360ng_touchscreen_init();
+}
+
+static int __init pdm360ng_probe(void)
+{
+        unsigned long root = of_get_flat_dt_root();
+
+        return of_flat_dt_is_compatible(root, "ifm,pdm360ng");
+}
+
+define_machine(pdm360ng) {
+        .name                   = "PDM360NG",
+        .probe                  = pdm360ng_probe,
+        .setup_arch             = mpc512x_setup_diu,
+        .init                   = pdm360ng_init,
+        .init_early             = mpc512x_init_diu,
+        .init_IRQ               = mpc512x_init_IRQ,
+        .get_irq                = ipic_get_irq,
+        .calibrate_decr         = generic_calibrate_decr,
+        .restart                = mpc512x_restart,
+};
diff --git a/arch/powerpc/platforms/52xx/lite5200_pm.c b/arch/powerpc/platforms/52xx/lite5200_pm.c
index b5c753db125e..80234e5921f5 100644
--- a/arch/powerpc/platforms/52xx/lite5200_pm.c
+++ b/arch/powerpc/platforms/52xx/lite5200_pm.c
@@ -216,9 +216,6 @@ static int lite5200_pm_enter(suspend_state_t state)
 
         lite5200_restore_regs();
 
-        /* restart jiffies */
-        wakeup_decrementer();
-
         iounmap(mbar);
         return 0;
 }
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_pm.c b/arch/powerpc/platforms/52xx/mpc52xx_pm.c
index 76722532bd95..568cef636275 100644
--- a/arch/powerpc/platforms/52xx/mpc52xx_pm.c
+++ b/arch/powerpc/platforms/52xx/mpc52xx_pm.c
@@ -171,9 +171,6 @@ int mpc52xx_pm_enter(suspend_state_t state)
         /* restore SRAM */
         memcpy(sram, saved_sram, sram_size);
 
-        /* restart jiffies */
-        wakeup_decrementer();
-
         /* reenable interrupts in PIC */
         out_be32(&intr->main_mask, intr_main_mask);
 
diff --git a/arch/powerpc/platforms/83xx/Kconfig b/arch/powerpc/platforms/83xx/Kconfig
index f49a2548c5ff..021763a32c2f 100644
--- a/arch/powerpc/platforms/83xx/Kconfig
+++ b/arch/powerpc/platforms/83xx/Kconfig
@@ -9,6 +9,14 @@ menuconfig PPC_83xx
 
 if PPC_83xx
 
+config MPC830x_RDB
+        bool "Freescale MPC830x RDB"
+        select DEFAULT_UIMAGE
+        select PPC_MPC831x
+        select FSL_GTM
+        help
+          This option enables support for the MPC8308 RDB board.
+
 config MPC831x_RDB
         bool "Freescale MPC831x RDB"
         select DEFAULT_UIMAGE
diff --git a/arch/powerpc/platforms/83xx/Makefile b/arch/powerpc/platforms/83xx/Makefile
index e139c36572ec..6e8bbbbcfdf8 100644
--- a/arch/powerpc/platforms/83xx/Makefile
+++ b/arch/powerpc/platforms/83xx/Makefile
@@ -4,6 +4,7 @@
 obj-y                           := misc.o usb.o
 obj-$(CONFIG_SUSPEND)           += suspend.o suspend-asm.o
 obj-$(CONFIG_MCU_MPC8349EMITX)  += mcu_mpc8349emitx.o
+obj-$(CONFIG_MPC830x_RDB)       += mpc830x_rdb.o
 obj-$(CONFIG_MPC831x_RDB)       += mpc831x_rdb.o
 obj-$(CONFIG_MPC832x_RDB)       += mpc832x_rdb.o
 obj-$(CONFIG_MPC834x_MDS)       += mpc834x_mds.o
diff --git a/arch/powerpc/platforms/83xx/mpc830x_rdb.c b/arch/powerpc/platforms/83xx/mpc830x_rdb.c
new file mode 100644
index 000000000000..ac102ee9abe8
--- /dev/null
+++ b/arch/powerpc/platforms/83xx/mpc830x_rdb.c
@@ -0,0 +1,94 @@
+/*
+ * arch/powerpc/platforms/83xx/mpc830x_rdb.c
+ *
+ * Description: MPC830x RDB board specific routines.
+ * This file is based on mpc831x_rdb.c
+ *
+ * Copyright (C) Freescale Semiconductor, Inc. 2009. All rights reserved.
+ * Copyright (C) 2010. Ilya Yanok, Emcraft Systems, yanok@emcraft.com
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/pci.h>
+#include <linux/of_platform.h>
+#include <asm/time.h>
+#include <asm/ipic.h>
+#include <asm/udbg.h>
+#include <sysdev/fsl_pci.h>
+#include <sysdev/fsl_soc.h>
+#include "mpc83xx.h"
+
+/*
+ * Setup the architecture
+ */
+static void __init mpc830x_rdb_setup_arch(void)
+{
+#ifdef CONFIG_PCI
+        struct device_node *np;
+#endif
+
+        if (ppc_md.progress)
+                ppc_md.progress("mpc830x_rdb_setup_arch()", 0);
+
+#ifdef CONFIG_PCI
+        for_each_compatible_node(np, "pci", "fsl,mpc8308-pcie")
+                mpc83xx_add_bridge(np);
+#endif
+        mpc831x_usb_cfg();
+}
+
+static void __init mpc830x_rdb_init_IRQ(void)
+{
+        struct device_node *np;
+
+        np = of_find_node_by_type(NULL, "ipic");
+        if (!np)
+                return;
+
+        ipic_init(np, 0);
+
+        /* Initialize the default interrupt mapping priorities,
+         * in case the boot rom changed something on us.
+         */
+        ipic_set_default_priority();
+}
+
+/*
+ * Called very early, MMU is off, device-tree isn't unflattened
+ */
+static int __init mpc830x_rdb_probe(void)
+{
+        unsigned long root = of_get_flat_dt_root();
+
+        return of_flat_dt_is_compatible(root, "MPC8308RDB") ||
+               of_flat_dt_is_compatible(root, "fsl,mpc8308rdb");
+}
+
+static struct of_device_id __initdata of_bus_ids[] = {
+        { .compatible = "simple-bus" },
+        { .compatible = "gianfar" },
+        {},
+};
+
+static int __init declare_of_platform_devices(void)
+{
+        of_platform_bus_probe(NULL, of_bus_ids, NULL);
+        return 0;
+}
+machine_device_initcall(mpc830x_rdb, declare_of_platform_devices);
+
+define_machine(mpc830x_rdb) {
+        .name                   = "MPC830x RDB",
+        .probe                  = mpc830x_rdb_probe,
+        .setup_arch             = mpc830x_rdb_setup_arch,
+        .init_IRQ               = mpc830x_rdb_init_IRQ,
+        .get_irq                = ipic_get_irq,
+        .restart                = mpc83xx_restart,
+        .time_init              = mpc83xx_time_init,
+        .calibrate_decr         = generic_calibrate_decr,
+        .progress               = udbg_progress,
+};
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index 3a2ade2e443f..bea1f5905ad4 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -65,6 +65,14 @@ config MPC85xx_RDB
         help
           This option enables support for the MPC85xx RDB (P2020 RDB) board
 
+config P1022_DS
+        bool "Freescale P1022 DS"
+        select DEFAULT_UIMAGE
+        select CONFIG_PHYS_64BIT        # The DTS has 36-bit addresses
+        select SWIOTLB
+        help
+          This option enables support for the Freescale P1022DS reference board.
+
 config SOCRATES
         bool "Socrates"
         select DEFAULT_UIMAGE
diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
index 387c128f2c8c..a2ec3f8f4d06 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_MPC8536_DS)  += mpc8536_ds.o
 obj-$(CONFIG_MPC85xx_DS)  += mpc85xx_ds.o
 obj-$(CONFIG_MPC85xx_MDS) += mpc85xx_mds.o
 obj-$(CONFIG_MPC85xx_RDB) += mpc85xx_rdb.o
+obj-$(CONFIG_P1022_DS)    += p1022_ds.o
 obj-$(CONFIG_P4080_DS)    += p4080_ds.o corenet_ds.o
 obj-$(CONFIG_STX_GP3)     += stx_gp3.o
 obj-$(CONFIG_TQM85xx)     += tqm85xx.o
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index 494513682d70..da64be19d099 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -158,51 +158,108 @@ static int mpc8568_mds_phy_fixups(struct phy_device *phydev)
 extern void __init mpc85xx_smp_init(void);
 #endif
 
-static void __init mpc85xx_mds_setup_arch(void)
+#ifdef CONFIG_QUICC_ENGINE
+static struct of_device_id mpc85xx_qe_ids[] __initdata = {
+        { .type = "qe", },
+        { .compatible = "fsl,qe", },
+        { },
+};
+
+static void __init mpc85xx_publish_qe_devices(void)
 {
         struct device_node *np;
-        static u8 __iomem *bcsr_regs = NULL;
-#ifdef CONFIG_PCI
-        struct pci_controller *hose;
-#endif
-        dma_addr_t max = 0xffffffff;
 
-        if (ppc_md.progress)
-                ppc_md.progress("mpc85xx_mds_setup_arch()", 0);
+        np = of_find_compatible_node(NULL, NULL, "fsl,qe");
+        if (!of_device_is_available(np)) {
+                of_node_put(np);
+                return;
+        }
+
+        of_platform_bus_probe(NULL, mpc85xx_qe_ids, NULL);
+}
+
+static void __init mpc85xx_mds_reset_ucc_phys(void)
+{
+        struct device_node *np;
+        static u8 __iomem *bcsr_regs;
 
         /* Map BCSR area */
         np = of_find_node_by_name(NULL, "bcsr");
-        if (np != NULL) {
-                struct resource res;
+        if (!np)
+                return;
 
-                of_address_to_resource(np, 0, &res);
-                bcsr_regs = ioremap(res.start, res.end - res.start +1);
-                of_node_put(np);
-        }
+        bcsr_regs = of_iomap(np, 0);
+        of_node_put(np);
+        if (!bcsr_regs)
+                return;
 
-#ifdef CONFIG_PCI
-        for_each_node_by_type(np, "pci") {
-                if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
-                    of_device_is_compatible(np, "fsl,mpc8548-pcie")) {
-                        struct resource rsrc;
-                        of_address_to_resource(np, 0, &rsrc);
-                        if ((rsrc.start & 0xfffff) == 0x8000)
-                                fsl_add_bridge(np, 1);
-                        else
-                                fsl_add_bridge(np, 0);
+        if (machine_is(mpc8568_mds)) {
+#define BCSR_UCC1_GETH_EN       (0x1 << 7)
+#define BCSR_UCC2_GETH_EN       (0x1 << 7)
+#define BCSR_UCC1_MODE_MSK      (0x3 << 4)
+#define BCSR_UCC2_MODE_MSK      (0x3 << 0)
 
-                        hose = pci_find_hose_for_OF_device(np);
-                        max = min(max, hose->dma_window_base_cur +
-                                        hose->dma_window_size);
+                /* Turn off UCC1 & UCC2 */
+                clrbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
+                clrbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
+
+                /* Mode is RGMII, all bits clear */
+                clrbits8(&bcsr_regs[11], BCSR_UCC1_MODE_MSK |
+                                         BCSR_UCC2_MODE_MSK);
+
+                /* Turn UCC1 & UCC2 on */
+                setbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
+                setbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
+        } else if (machine_is(mpc8569_mds)) {
+#define BCSR7_UCC12_GETHnRST    (0x1 << 2)
+#define BCSR8_UEM_MARVELL_RST   (0x1 << 1)
+#define BCSR_UCC_RGMII          (0x1 << 6)
+#define BCSR_UCC_RTBI           (0x1 << 5)
+                /*
+                 * U-Boot mangles interrupt polarity for Marvell PHYs,
+                 * so reset built-in and UEM Marvell PHYs, this puts
+                 * the PHYs into their normal state.
+                 */
+                clrbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
+                setbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
+
+                setbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
+                clrbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
+
+                for (np = NULL; (np = of_find_compatible_node(np,
+                                                "network",
+                                                "ucc_geth")) != NULL;) {
+                        const unsigned int *prop;
+                        int ucc_num;
+
+                        prop = of_get_property(np, "cell-index", NULL);
+                        if (prop == NULL)
+                                continue;
+
+                        ucc_num = *prop - 1;
+
+                        prop = of_get_property(np, "phy-connection-type", NULL);
+                        if (prop == NULL)
+                                continue;
+
+                        if (strcmp("rtbi", (const char *)prop) == 0)
+                                clrsetbits_8(&bcsr_regs[7 + ucc_num],
+                                        BCSR_UCC_RGMII, BCSR_UCC_RTBI);
                 }
+        } else if (machine_is(p1021_mds)) {
+#define BCSR11_ENET_MICRST     (0x1 << 5)
+                /* Reset Micrel PHY */
+                clrbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
+                setbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
         }
-#endif
 
-#ifdef CONFIG_SMP
-        mpc85xx_smp_init();
-#endif
+        iounmap(bcsr_regs);
+}
+
+static void __init mpc85xx_mds_qe_init(void)
+{
+        struct device_node *np;
 
-#ifdef CONFIG_QUICC_ENGINE
         np = of_find_compatible_node(NULL, NULL, "fsl,qe");
         if (!np) {
                 np = of_find_node_by_name(NULL, "qe");
@@ -210,6 +267,11 @@ static void __init mpc85xx_mds_setup_arch(void)
                         return;
         }
 
+        if (!of_device_is_available(np)) {
+                of_node_put(np);
+                return;
+        }
+
         qe_reset();
         of_node_put(np);
 
@@ -224,70 +286,7 @@ static void __init mpc85xx_mds_setup_arch(void)
                         par_io_of_config(ucc);
         }
 
-        if (bcsr_regs) {
-                if (machine_is(mpc8568_mds)) {
-#define BCSR_UCC1_GETH_EN       (0x1 << 7)
-#define BCSR_UCC2_GETH_EN       (0x1 << 7)
-#define BCSR_UCC1_MODE_MSK      (0x3 << 4)
-#define BCSR_UCC2_MODE_MSK      (0x3 << 0)
-
-                        /* Turn off UCC1 & UCC2 */
-                        clrbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
-                        clrbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
-
-                        /* Mode is RGMII, all bits clear */
-                        clrbits8(&bcsr_regs[11], BCSR_UCC1_MODE_MSK |
-                                                 BCSR_UCC2_MODE_MSK);
-
-                        /* Turn UCC1 & UCC2 on */
-                        setbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
-                        setbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
-                } else if (machine_is(mpc8569_mds)) {
-#define BCSR7_UCC12_GETHnRST    (0x1 << 2)
-#define BCSR8_UEM_MARVELL_RST   (0x1 << 1)
-#define BCSR_UCC_RGMII          (0x1 << 6)
-#define BCSR_UCC_RTBI           (0x1 << 5)
-                        /*
-                         * U-Boot mangles interrupt polarity for Marvell PHYs,
-                         * so reset built-in and UEM Marvell PHYs, this puts
-                         * the PHYs into their normal state.
-                         */
-                        clrbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
-                        setbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
-
-                        setbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
-                        clrbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
-
-                        for (np = NULL; (np = of_find_compatible_node(np,
-                                                        "network",
-                                                        "ucc_geth")) != NULL;) {
-                                const unsigned int *prop;
-                                int ucc_num;
-
-                                prop = of_get_property(np, "cell-index", NULL);
-                                if (prop == NULL)
-                                        continue;
-
-                                ucc_num = *prop - 1;
-
-                                prop = of_get_property(np, "phy-connection-type", NULL);
-                                if (prop == NULL)
-                                        continue;
-
-                                if (strcmp("rtbi", (const char *)prop) == 0)
-                                        clrsetbits_8(&bcsr_regs[7 + ucc_num],
-                                                BCSR_UCC_RGMII, BCSR_UCC_RTBI);
-                        }
-
-                } else if (machine_is(p1021_mds)) {
-#define BCSR11_ENET_MICRST     (0x1 << 5)
-                        /* Reset Micrel PHY */
-                        clrbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
-                        setbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
-                }
-
-                iounmap(bcsr_regs);
-        }
+        mpc85xx_mds_reset_ucc_phys();
 
         if (machine_is(p1021_mds)) {
 #define MPC85xx_PMUXCR_OFFSET           0x60
@@ -322,8 +321,72 @@ static void __init mpc85xx_mds_setup_arch(void)
                 }
 
         }
+}
+
+static void __init mpc85xx_mds_qeic_init(void)
+{
+        struct device_node *np;
+
+        np = of_find_compatible_node(NULL, NULL, "fsl,qe");
+        if (!of_device_is_available(np)) {
+                of_node_put(np);
+                return;
+        }
+
+        np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
+        if (!np) {
+                np = of_find_node_by_type(NULL, "qeic");
+                if (!np)
+                        return;
+        }
+
+        if (machine_is(p1021_mds))
+                qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
+                                qe_ic_cascade_high_mpic);
+        else
+                qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
+        of_node_put(np);
+}
+#else
+static void __init mpc85xx_publish_qe_devices(void) { }
+static void __init mpc85xx_mds_qe_init(void) { }
+static void __init mpc85xx_mds_qeic_init(void) { }
 #endif  /* CONFIG_QUICC_ENGINE */
 
+static void __init mpc85xx_mds_setup_arch(void)
+{
+#ifdef CONFIG_PCI
+        struct pci_controller *hose;
+#endif
+        dma_addr_t max = 0xffffffff;
+
+        if (ppc_md.progress)
+                ppc_md.progress("mpc85xx_mds_setup_arch()", 0);
+
+#ifdef CONFIG_PCI
+        for_each_node_by_type(np, "pci") {
+                if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
+                    of_device_is_compatible(np, "fsl,mpc8548-pcie")) {
+                        struct resource rsrc;
+                        of_address_to_resource(np, 0, &rsrc);
+                        if ((rsrc.start & 0xfffff) == 0x8000)
+                                fsl_add_bridge(np, 1);
+                        else
+                                fsl_add_bridge(np, 0);
+
+                        hose = pci_find_hose_for_OF_device(np);
+                        max = min(max, hose->dma_window_base_cur +
+                                        hose->dma_window_size);
+                }
+        }
+#endif
+
+#ifdef CONFIG_SMP
+        mpc85xx_smp_init();
+#endif
+
+        mpc85xx_mds_qe_init();
+
 #ifdef CONFIG_SWIOTLB
         if (memblock_end_of_DRAM() > max) {
                 ppc_swiotlb_enable = 1;
@@ -369,8 +432,6 @@ static struct of_device_id mpc85xx_ids[] = {
         { .type = "soc", },
         { .compatible = "soc", },
         { .compatible = "simple-bus", },
-        { .type = "qe", },
-        { .compatible = "fsl,qe", },
         { .compatible = "gianfar", },
         { .compatible = "fsl,rapidio-delta", },
         { .compatible = "fsl,mpc8548-guts", },
@@ -382,8 +443,6 @@ static struct of_device_id p1021_ids[] = {
         { .type = "soc", },
         { .compatible = "soc", },
         { .compatible = "simple-bus", },
-        { .type = "qe", },
-        { .compatible = "fsl,qe", },
         { .compatible = "gianfar", },
         {},
 };
@@ -395,16 +454,16 @@ static int __init mpc85xx_publish_devices(void)
         if (machine_is(mpc8569_mds))
                 simple_gpiochip_init("fsl,mpc8569mds-bcsr-gpio");
 
-        /* Publish the QE devices */
         of_platform_bus_probe(NULL, mpc85xx_ids, NULL);
+        mpc85xx_publish_qe_devices();
 
         return 0;
 }
 
 static int __init p1021_publish_devices(void)
 {
-        /* Publish the QE devices */
         of_platform_bus_probe(NULL, p1021_ids, NULL);
+        mpc85xx_publish_qe_devices();
 
         return 0;
 }
@@ -441,21 +500,7 @@ static void __init mpc85xx_mds_pic_init(void)
         of_node_put(np);
 
         mpic_init(mpic);
-
-#ifdef CONFIG_QUICC_ENGINE
-        np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
-        if (!np) {
-                np = of_find_node_by_type(NULL, "qeic");
-                if (!np)
-                        return;
-        }
-        if (machine_is(p1021_mds))
-                qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
-                                qe_ic_cascade_high_mpic);
-        else
-                qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
-        of_node_put(np);
-#endif                          /* CONFIG_QUICC_ENGINE */
+        mpc85xx_mds_qeic_init();
 }
 
 static int __init mpc85xx_mds_probe(void)
diff --git a/arch/powerpc/platforms/85xx/p1022_ds.c b/arch/powerpc/platforms/85xx/p1022_ds.c
new file mode 100644
index 000000000000..e1467c937450
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/p1022_ds.c
@@ -0,0 +1,148 @@
+/*
+ * P1022DS board specific routines
+ *
+ * Authors: Travis Wheatley <travis.wheatley@freescale.com>
+ *          Dave Liu <daveliu@freescale.com>
+ *          Timur Tabi <timur@freescale.com>
+ *
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * This file is taken from the Freescale P1022DS BSP, with modifications:
+ * 1) No DIU support (pending rewrite of DIU code)
+ * 2) No AMP support
+ * 3) No PCI endpoint support
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <linux/pci.h>
+#include <linux/of_platform.h>
+#include <linux/lmb.h>
+
+#include <asm/mpic.h>
+#include <asm/swiotlb.h>
+
+#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
+
+void __init p1022_ds_pic_init(void)
+{
+        struct mpic *mpic;
+        struct resource r;
+        struct device_node *np;
+
+        np = of_find_node_by_type(NULL, "open-pic");
+        if (!np) {
+                pr_err("Could not find open-pic node\n");
+                return;
+        }
+
+        if (of_address_to_resource(np, 0, &r)) {
+                pr_err("Failed to map mpic register space\n");
+                of_node_put(np);
+                return;
+        }
+
+        mpic = mpic_alloc(np, r.start,
+                MPIC_PRIMARY | MPIC_WANTS_RESET |
+                MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
+                MPIC_SINGLE_DEST_CPU,
+                0, 256, " OpenPIC  ");
+
+        BUG_ON(mpic == NULL);
+        of_node_put(np);
+
+        mpic_init(mpic);
+}
+
+#ifdef CONFIG_SMP
+void __init mpc85xx_smp_init(void);
+#endif
+
+/*
+ * Setup the architecture
+ */
+static void __init p1022_ds_setup_arch(void)
+{
+#ifdef CONFIG_PCI
+        struct device_node *np;
+#endif
+        dma_addr_t max = 0xffffffff;
+
+        if (ppc_md.progress)
+                ppc_md.progress("p1022_ds_setup_arch()", 0);
+
+#ifdef CONFIG_PCI
+        for_each_compatible_node(np, "pci", "fsl,p1022-pcie") {
+                struct resource rsrc;
+                struct pci_controller *hose;
+
+                of_address_to_resource(np, 0, &rsrc);
+
+                if ((rsrc.start & 0xfffff) == 0x8000)
+                        fsl_add_bridge(np, 1);
+                else
+                        fsl_add_bridge(np, 0);
+
+                hose = pci_find_hose_for_OF_device(np);
+                max = min(max, hose->dma_window_base_cur +
+                          hose->dma_window_size);
+        }
+#endif
+
+#ifdef CONFIG_SMP
+        mpc85xx_smp_init();
+#endif
+
+#ifdef CONFIG_SWIOTLB
+        if (lmb_end_of_DRAM() > max) {
+                ppc_swiotlb_enable = 1;
+                set_pci_dma_ops(&swiotlb_dma_ops);
+                ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
+        }
+#endif
+
+        pr_info("Freescale P1022 DS reference board\n");
+}
+
+static struct of_device_id __initdata p1022_ds_ids[] = {
+        { .type = "soc", },
+        { .compatible = "soc", },
+        { .compatible = "simple-bus", },
+        { .compatible = "gianfar", },
+        {},
+};
+
+static int __init p1022_ds_publish_devices(void)
+{
+        return of_platform_bus_probe(NULL, p1022_ds_ids, NULL);
+}
+machine_device_initcall(p1022_ds, p1022_ds_publish_devices);
+
+machine_arch_initcall(p1022_ds, swiotlb_setup_bus_notifier);
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init p1022_ds_probe(void)
+{
+        unsigned long root = of_get_flat_dt_root();
+
+        return of_flat_dt_is_compatible(root, "fsl,p1022ds");
+}
+
+define_machine(p1022_ds) {
+        .name                   = "P1022 DS",
+        .probe                  = p1022_ds_probe,
+        .setup_arch             = p1022_ds_setup_arch,
+        .init_IRQ               = p1022_ds_pic_init,
+#ifdef CONFIG_PCI
+        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+#endif
+        .get_irq                = mpic_get_irq,
+        .restart                = fsl_rstcr_restart,
+        .calibrate_decr         = generic_calibrate_decr,
+        .progress               = udbg_progress,
+};
diff --git a/arch/powerpc/platforms/85xx/smp.c b/arch/powerpc/platforms/85xx/smp.c
index a15f582300d8..a6b106557be4 100644
--- a/arch/powerpc/platforms/85xx/smp.c
+++ b/arch/powerpc/platforms/85xx/smp.c
@@ -15,6 +15,7 @@
 #include <linux/init.h>
 #include <linux/delay.h>
 #include <linux/of.h>
+#include <linux/kexec.h>
 
 #include <asm/machdep.h>
 #include <asm/pgtable.h>
@@ -24,6 +25,7 @@
 #include <asm/dbell.h>
 
 #include <sysdev/fsl_soc.h>
+#include <sysdev/mpic.h>
 
 extern void __early_start(void);
 
@@ -99,12 +101,70 @@ static void __init
 smp_85xx_setup_cpu(int cpu_nr)
 {
         mpic_setup_this_cpu();
+        if (cpu_has_feature(CPU_FTR_DBELL))
+                doorbell_setup_this_cpu();
 }
 
 struct smp_ops_t smp_85xx_ops = {
         .kick_cpu = smp_85xx_kick_cpu,
+#ifdef CONFIG_KEXEC
+        .give_timebase  = smp_generic_give_timebase,
+        .take_timebase  = smp_generic_take_timebase,
+#endif
 };
 
+#ifdef CONFIG_KEXEC
+static int kexec_down_cpus = 0;
+
+void mpc85xx_smp_kexec_cpu_down(int crash_shutdown, int secondary)
+{
+        mpic_teardown_this_cpu(1);
+
+        /* When crashing, this gets called on all CPU's we only
+         * take down the non-boot cpus */
+        if (smp_processor_id() != boot_cpuid)
+        {
+                local_irq_disable();
+                kexec_down_cpus++;
+
+                while (1);
+        }
+}
+
+static void mpc85xx_smp_kexec_down(void *arg)
+{
+        if (ppc_md.kexec_cpu_down)
+                ppc_md.kexec_cpu_down(0,1);
+}
+
+static void mpc85xx_smp_machine_kexec(struct kimage *image)
+{
+        int timeout = 2000;
+        int i;
+
+        set_cpus_allowed(current, cpumask_of_cpu(boot_cpuid));
+
+        smp_call_function(mpc85xx_smp_kexec_down, NULL, 0);
+
+        while ( (kexec_down_cpus != (num_online_cpus() - 1)) &&
+                ( timeout > 0 ) )
+        {
+                timeout--;
+        }
+
+        if ( !timeout )
+                printk(KERN_ERR "Unable to bring down secondary cpu(s)");
+
+        for (i = 0; i < num_present_cpus(); i++)
+        {
+                if ( i == smp_processor_id() ) continue;
+                mpic_reset_core(i);
+        }
+
+        default_machine_kexec(image);
+}
+#endif /* CONFIG_KEXEC */
+
 void __init mpc85xx_smp_init(void)
 {
         struct device_node *np;
@@ -117,9 +177,14 @@ void __init mpc85xx_smp_init(void)
         }
 
         if (cpu_has_feature(CPU_FTR_DBELL))
-                smp_85xx_ops.message_pass = smp_dbell_message_pass;
+                smp_85xx_ops.message_pass = doorbell_message_pass;
 
         BUG_ON(!smp_85xx_ops.message_pass);
 
         smp_ops = &smp_85xx_ops;
+
+#ifdef CONFIG_KEXEC
+        ppc_md.kexec_cpu_down = mpc85xx_smp_kexec_cpu_down;
+        ppc_md.machine_kexec = mpc85xx_smp_machine_kexec;
+#endif
 }
diff --git a/arch/powerpc/platforms/85xx/tqm85xx.c b/arch/powerpc/platforms/85xx/tqm85xx.c
index 5b0ab9966e90..8f29bbce5360 100644
--- a/arch/powerpc/platforms/85xx/tqm85xx.c
+++ b/arch/powerpc/platforms/85xx/tqm85xx.c
@@ -151,6 +151,27 @@ static void tqm85xx_show_cpuinfo(struct seq_file *m)
         seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
 }
 
+static void __init tqm85xx_ti1520_fixup(struct pci_dev *pdev)
+{
+        unsigned int val;
+
+        /* Do not do the fixup on other platforms! */
+        if (!machine_is(tqm85xx))
+                return;
+
+        dev_info(&pdev->dev, "Using TI 1520 fixup on TQM85xx\n");
+
+        /*
+         * Enable P2CCLK bit in system control register
+         * to enable CLOCK output to power chip
+         */
+        pci_read_config_dword(pdev, 0x80, &val);
+        pci_write_config_dword(pdev, 0x80, val | (1 << 27));
+
+}
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1520,
+                tqm85xx_ti1520_fixup);
+
 static struct of_device_id __initdata of_bus_ids[] = {
         { .compatible = "simple-bus", },
         { .compatible = "gianfar", },
diff --git a/arch/powerpc/platforms/8xx/Kconfig b/arch/powerpc/platforms/8xx/Kconfig
index 48a920a98e7b..dd35ce081cff 100644
--- a/arch/powerpc/platforms/8xx/Kconfig
+++ b/arch/powerpc/platforms/8xx/Kconfig
@@ -55,6 +55,12 @@ config PPC_MGSUVD
         help
           This enables support for the Keymile MGSUVD board.
 
+config TQM8XX
+        bool "TQM8XX"
+        select CPM1
+        help
+          support for the mpc8xx based boards from TQM.
+
 endchoice
 
 menu "Freescale Ethernet driver platform-specific options"
diff --git a/arch/powerpc/platforms/8xx/Makefile b/arch/powerpc/platforms/8xx/Makefile
index bdbfd7496018..a491fe6b94fc 100644
--- a/arch/powerpc/platforms/8xx/Makefile
+++ b/arch/powerpc/platforms/8xx/Makefile
@@ -7,3 +7,4 @@ obj-$(CONFIG_MPC86XADS)   += mpc86xads_setup.o
 obj-$(CONFIG_PPC_EP88XC)  += ep88xc.o
 obj-$(CONFIG_PPC_ADDER875) += adder875.o
 obj-$(CONFIG_PPC_MGSUVD) += mgsuvd.o
+obj-$(CONFIG_TQM8XX)      += tqm8xx_setup.o
diff --git a/arch/powerpc/platforms/8xx/tqm8xx_setup.c b/arch/powerpc/platforms/8xx/tqm8xx_setup.c
new file mode 100644
index 000000000000..b71c650fbb11
--- /dev/null
+++ b/arch/powerpc/platforms/8xx/tqm8xx_setup.c
@@ -0,0 +1,156 @@
+/*
+ * Platform setup for the MPC8xx based boards from TQM.
+ *
+ * Heiko Schocher <hs@denx.de>
+ * Copyright 2010 DENX Software Engineering GmbH
+ *
+ * based on:
+ * Vitaly Bordug <vbordug@ru.mvista.com>
+ *
+ * Copyright 2005 MontaVista Software Inc.
+ *
+ * Heavily modified by Scott Wood <scottwood@freescale.com>
+ * Copyright 2007 Freescale Semiconductor, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/param.h>
+#include <linux/string.h>
+#include <linux/ioport.h>
+#include <linux/device.h>
+#include <linux/delay.h>
+
+#include <linux/fs_enet_pd.h>
+#include <linux/fs_uart_pd.h>
+#include <linux/fsl_devices.h>
+#include <linux/mii.h>
+#include <linux/of_platform.h>
+
+#include <asm/delay.h>
+#include <asm/io.h>
+#include <asm/machdep.h>
+#include <asm/page.h>
+#include <asm/processor.h>
+#include <asm/system.h>
+#include <asm/time.h>
+#include <asm/mpc8xx.h>
+#include <asm/8xx_immap.h>
+#include <asm/cpm1.h>
+#include <asm/fs_pd.h>
+#include <asm/udbg.h>
+
+#include "mpc8xx.h"
+
+struct cpm_pin {
+        int port, pin, flags;
+};
+
+static struct __initdata cpm_pin tqm8xx_pins[] = {
+        /* SMC1 */
+        {CPM_PORTB, 24, CPM_PIN_INPUT}, /* RX */
+        {CPM_PORTB, 25, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* TX */
+
+        /* SCC1 */
+        {CPM_PORTA, 5, CPM_PIN_INPUT}, /* CLK1 */
+        {CPM_PORTA, 7, CPM_PIN_INPUT}, /* CLK2 */
+        {CPM_PORTA, 14, CPM_PIN_INPUT}, /* TX */
+        {CPM_PORTA, 15, CPM_PIN_INPUT}, /* RX */
+        {CPM_PORTC, 15, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* TENA */
+        {CPM_PORTC, 10, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_GPIO},
+        {CPM_PORTC, 11, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_GPIO},
+};
+
+static struct __initdata cpm_pin tqm8xx_fec_pins[] = {
+        /* MII */
+        {CPM_PORTD, 3, CPM_PIN_OUTPUT},
+        {CPM_PORTD, 4, CPM_PIN_OUTPUT},
+        {CPM_PORTD, 5, CPM_PIN_OUTPUT},
+        {CPM_PORTD, 6, CPM_PIN_OUTPUT},
+        {CPM_PORTD, 7, CPM_PIN_OUTPUT},
+        {CPM_PORTD, 8, CPM_PIN_OUTPUT},
+        {CPM_PORTD, 9, CPM_PIN_OUTPUT},
+        {CPM_PORTD, 10, CPM_PIN_OUTPUT},
+        {CPM_PORTD, 11, CPM_PIN_OUTPUT},
+        {CPM_PORTD, 12, CPM_PIN_OUTPUT},
+        {CPM_PORTD, 13, CPM_PIN_OUTPUT},
+        {CPM_PORTD, 14, CPM_PIN_OUTPUT},
+        {CPM_PORTD, 15, CPM_PIN_OUTPUT},
+};
+
+static void __init init_pins(int n, struct cpm_pin *pin)
+{
+        int i;
+
+        for (i = 0; i < n; i++) {
+                cpm1_set_pin(pin->port, pin->pin, pin->flags);
+                pin++;
+        }
+}
+
+static void __init init_ioports(void)
+{
+        struct device_node *dnode;
+        struct property *prop;
+        int     len;
+
+        init_pins(ARRAY_SIZE(tqm8xx_pins), &tqm8xx_pins[0]);
+
+        cpm1_clk_setup(CPM_CLK_SMC1, CPM_BRG1, CPM_CLK_RTX);
+
+        dnode = of_find_node_by_name(NULL, "aliases");
+        if (dnode == NULL)
+                return;
+        prop = of_find_property(dnode, "ethernet1", &len);
+        if (prop == NULL)
+                return;
+
+        /* init FEC pins */
+        init_pins(ARRAY_SIZE(tqm8xx_fec_pins), &tqm8xx_fec_pins[0]);
+}
+
+static void __init tqm8xx_setup_arch(void)
+{
+        cpm_reset();
+        init_ioports();
+}
+
+static int __init tqm8xx_probe(void)
+{
+        unsigned long node = of_get_flat_dt_root();
+
+        return of_flat_dt_is_compatible(node, "tqc,tqm8xx");
+}
+
+static struct of_device_id __initdata of_bus_ids[] = {
+        { .name = "soc", },
+        { .name = "cpm", },
+        { .name = "localbus", },
+        { .compatible = "simple-bus" },
+        {},
+};
+
+static int __init declare_of_platform_devices(void)
+{
+        of_platform_bus_probe(NULL, of_bus_ids, NULL);
+
+        return 0;
+}
+machine_device_initcall(tqm8xx, declare_of_platform_devices);
+
+define_machine(tqm8xx) {
+        .name                   = "TQM8xx",
+        .probe                  = tqm8xx_probe,
+        .setup_arch             = tqm8xx_setup_arch,
+        .init_IRQ               = mpc8xx_pics_init,
+        .get_irq                = mpc8xx_get_irq,
+        .restart                = mpc8xx_restart,
+        .calibrate_decr         = mpc8xx_calibrate_decr,
+        .set_rtc_time           = mpc8xx_set_rtc_time,
+        .get_rtc_time           = mpc8xx_get_rtc_time,
+        .progress               = udbg_progress,
+};
diff --git a/arch/powerpc/platforms/iseries/vio.c b/arch/powerpc/platforms/iseries/vio.c
index 00b6730bc48f..b6db7cef83b4 100644
--- a/arch/powerpc/platforms/iseries/vio.c
+++ b/arch/powerpc/platforms/iseries/vio.c
@@ -87,12 +87,11 @@ static struct device_node *new_node(const char *path,
 
         if (!np)
                 return NULL;
-        np->full_name = kmalloc(strlen(path) + 1, GFP_KERNEL);
+        np->full_name = kstrdup(path, GFP_KERNEL);
         if (!np->full_name) {
                 kfree(np);
                 return NULL;
         }
-        strcpy(np->full_name, path);
         of_node_set_flag(np, OF_DYNAMIC);
         kref_init(&np->kref);
         np->parent = of_node_get(parent);
diff --git a/arch/powerpc/platforms/powermac/cpufreq_32.c b/arch/powerpc/platforms/powermac/cpufreq_32.c
index 1e9eba175ff0..415ca6d6b273 100644
--- a/arch/powerpc/platforms/powermac/cpufreq_32.c
+++ b/arch/powerpc/platforms/powermac/cpufreq_32.c
@@ -310,8 +310,12 @@ static int pmu_set_cpu_speed(int low_speed)
         /* Restore low level PMU operations */
         pmu_unlock();
 
-        /* Restore decrementer */
-        wakeup_decrementer();
+        /*
+         * Restore decrementer; we'll take a decrementer interrupt
+         * as soon as interrupts are re-enabled and the generic
+         * clockevents code will reprogram it with the right value.
+         */
+        set_dec(1);
 
         /* Restore interrupts */
         mpic_cpu_set_priority(pic_prio);
diff --git a/arch/powerpc/platforms/powermac/feature.c b/arch/powerpc/platforms/powermac/feature.c
index 9e1b9fd75206..79bd3e89dbaf 100644
--- a/arch/powerpc/platforms/powermac/feature.c
+++ b/arch/powerpc/platforms/powermac/feature.c
@@ -2191,7 +2191,11 @@ static struct pmac_mb_def pmac_mb_defs[] = {
                 PMAC_TYPE_UNKNOWN_INTREPID,     intrepid_features,
                 PMAC_MB_MAY_SLEEP,
         },
-        {       "iMac,1",                       "iMac (first generation)",
+        {       "PowerMac10,2",                 "Mac mini (Late 2005)",
+                PMAC_TYPE_UNKNOWN_INTREPID,     intrepid_features,
+                PMAC_MB_MAY_SLEEP,
+        },
+        {       "iMac,1",                       "iMac (first generation)",
                 PMAC_TYPE_ORIG_IMAC,            paddington_features,
                 0
         },
diff --git a/arch/powerpc/platforms/pseries/Makefile b/arch/powerpc/platforms/pseries/Makefile
index 3dbef309bc8d..046ace9c4381 100644
--- a/arch/powerpc/platforms/pseries/Makefile
+++ b/arch/powerpc/platforms/pseries/Makefile
@@ -26,3 +26,7 @@ obj-$(CONFIG_HCALL_STATS)	+= hvCall_inst.o
 obj-$(CONFIG_PHYP_DUMP) += phyp_dump.o
 obj-$(CONFIG_CMM)               += cmm.o
 obj-$(CONFIG_DTL)               += dtl.o
+
+ifeq ($(CONFIG_PPC_PSERIES),y)
+obj-$(CONFIG_SUSPEND)           += suspend.o
+endif
diff --git a/arch/powerpc/platforms/pseries/dlpar.c b/arch/powerpc/platforms/pseries/dlpar.c
index d71e58584086..227c1c3d585e 100644
--- a/arch/powerpc/platforms/pseries/dlpar.c
+++ b/arch/powerpc/platforms/pseries/dlpar.c
@@ -463,6 +463,7 @@ static int dlpar_offline_cpu(struct device_node *dn)
                                 break;
 
                         if (get_cpu_current_state(cpu) == CPU_STATE_ONLINE) {
+                                set_preferred_offline_state(cpu, CPU_STATE_OFFLINE);
                                 cpu_maps_update_done();
                                 rc = cpu_down(cpu);
                                 if (rc)
diff --git a/arch/powerpc/platforms/pseries/eeh_cache.c b/arch/powerpc/platforms/pseries/eeh_cache.c
index 30b987b73c20..8ed0d2d0e1b5 100644
--- a/arch/powerpc/platforms/pseries/eeh_cache.c
+++ b/arch/powerpc/platforms/pseries/eeh_cache.c
@@ -288,8 +288,7 @@ void __init pci_addr_cache_build(void)
 
         spin_lock_init(&pci_io_addr_cache_root.piar_lock);
 
-        while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
-
+        for_each_pci_dev(dev) {
                 pci_addr_cache_insert_device(dev);
 
                 dn = pci_device_to_OF_node(dev);
diff --git a/arch/powerpc/platforms/pseries/event_sources.c b/arch/powerpc/platforms/pseries/event_sources.c
index e889c9d9586a..2605c310166a 100644
--- a/arch/powerpc/platforms/pseries/event_sources.c
+++ b/arch/powerpc/platforms/pseries/event_sources.c
@@ -41,9 +41,12 @@ void request_event_sources_irqs(struct device_node *np,
                         if (count > 15)
                                 break;
                         virqs[count] = irq_create_mapping(NULL, *(opicprop++));
-                        if (virqs[count] == NO_IRQ)
-                                printk(KERN_ERR "Unable to allocate interrupt "
-                                       "number for %s\n", np->full_name);
+                        if (virqs[count] == NO_IRQ) {
+                                pr_err("event-sources: Unable to allocate "
+                                       "interrupt number for %s\n",
+                                       np->full_name);
+                                WARN_ON(1);
+                        }
                         else
                                 count++;
 
@@ -59,9 +62,12 @@ void request_event_sources_irqs(struct device_node *np,
                         virqs[count] = irq_create_of_mapping(oirq.controller,
                                                             oirq.specifier,
                                                             oirq.size);
-                        if (virqs[count] == NO_IRQ)
-                                printk(KERN_ERR "Unable to allocate interrupt "
-                                       "number for %s\n", np->full_name);
+                        if (virqs[count] == NO_IRQ) {
+                                pr_err("event-sources: Unable to allocate "
+                                       "interrupt number for %s\n",
+                                       np->full_name);
+                                WARN_ON(1);
+                        }
                         else
                                 count++;
                 }
@@ -70,8 +76,9 @@ void request_event_sources_irqs(struct device_node *np,
         /* Now request them */
         for (i = 0; i < count; i++) {
                 if (request_irq(virqs[i], handler, 0, name, NULL)) {
-                        printk(KERN_ERR "Unable to request interrupt %d for "
-                               "%s\n", virqs[i], np->full_name);
+                        pr_err("event-sources: Unable to request interrupt "
+                               "%d for %s\n", virqs[i], np->full_name);
+                        WARN_ON(1);
                         return;
                 }
         }
diff --git a/arch/powerpc/platforms/pseries/hotplug-cpu.c b/arch/powerpc/platforms/pseries/hotplug-cpu.c
index 8f85f399ab9f..fd50ccd4bac1 100644
--- a/arch/powerpc/platforms/pseries/hotplug-cpu.c
+++ b/arch/powerpc/platforms/pseries/hotplug-cpu.c
@@ -116,6 +116,9 @@ static void pseries_mach_cpu_die(void)
 
         if (get_preferred_offline_state(cpu) == CPU_STATE_INACTIVE) {
                 set_cpu_current_state(cpu, CPU_STATE_INACTIVE);
+                if (ppc_md.suspend_disable_cpu)
+                        ppc_md.suspend_disable_cpu();
+
                 cede_latency_hint = 2;
 
                 get_lppaca()->idle = 1;
@@ -190,12 +193,12 @@ static void pseries_cpu_die(unsigned int cpu)
 
         if (get_preferred_offline_state(cpu) == CPU_STATE_INACTIVE) {
                 cpu_status = 1;
-                for (tries = 0; tries < 1000; tries++) {
+                for (tries = 0; tries < 5000; tries++) {
                         if (get_cpu_current_state(cpu) == CPU_STATE_INACTIVE) {
                                 cpu_status = 0;
                                 break;
                         }
-                        cpu_relax();
+                        msleep(1);
                 }
         } else if (get_preferred_offline_state(cpu) == CPU_STATE_OFFLINE) {
 
diff --git a/arch/powerpc/platforms/pseries/ras.c b/arch/powerpc/platforms/pseries/ras.c
index 41a3e9a039ed..a4fc6da87c2e 100644
--- a/arch/powerpc/platforms/pseries/ras.c
+++ b/arch/powerpc/platforms/pseries/ras.c
@@ -61,7 +61,6 @@ static int ras_check_exception_token;
 
 #define EPOW_SENSOR_TOKEN       9
 #define EPOW_SENSOR_INDEX       0
-#define RAS_VECTOR_OFFSET       0x500
 
 static irqreturn_t ras_epow_interrupt(int irq, void *dev_id);
 static irqreturn_t ras_error_interrupt(int irq, void *dev_id);
@@ -121,7 +120,7 @@ static irqreturn_t ras_epow_interrupt(int irq, void *dev_id)
         spin_lock(&ras_log_buf_lock);
 
         status = rtas_call(ras_check_exception_token, 6, 1, NULL,
-                           RAS_VECTOR_OFFSET,
+                           RTAS_VECTOR_EXTERNAL_INTERRUPT,
                            irq_map[irq].hwirq,
                            RTAS_EPOW_WARNING | RTAS_POWERMGM_EVENTS,
                            critical, __pa(&ras_log_buf),
@@ -156,7 +155,7 @@ static irqreturn_t ras_error_interrupt(int irq, void *dev_id)
         spin_lock(&ras_log_buf_lock);
 
         status = rtas_call(ras_check_exception_token, 6, 1, NULL,
-                           RAS_VECTOR_OFFSET,
+                           RTAS_VECTOR_EXTERNAL_INTERRUPT,
                            irq_map[irq].hwirq,
                            RTAS_INTERNAL_ERROR, 1 /*Time Critical */,
                            __pa(&ras_log_buf),
diff --git a/arch/powerpc/platforms/pseries/reconfig.c b/arch/powerpc/platforms/pseries/reconfig.c
index 1a58637bcea5..57ddbb43b33a 100644
--- a/arch/powerpc/platforms/pseries/reconfig.c
+++ b/arch/powerpc/platforms/pseries/reconfig.c
@@ -118,12 +118,10 @@ static int pSeries_reconfig_add_node(const char *path, struct property *proplist
         if (!np)
                 goto out_err;
 
-        np->full_name = kmalloc(strlen(path) + 1, GFP_KERNEL);
+        np->full_name = kstrdup(path, GFP_KERNEL);
         if (!np->full_name)
                 goto out_err;
 
-        strcpy(np->full_name, path);
-
         np->properties = proplist;
         of_node_set_flag(np, OF_DYNAMIC);
         kref_init(&np->kref);
diff --git a/arch/powerpc/platforms/pseries/suspend.c b/arch/powerpc/platforms/pseries/suspend.c
new file mode 100644
index 000000000000..ed72098bb4e3
--- /dev/null
+++ b/arch/powerpc/platforms/pseries/suspend.c
@@ -0,0 +1,214 @@
+/*
+  * Copyright (C) 2010 Brian King IBM Corporation
+  *
+  * This program is free software; you can redistribute it and/or modify
+  * it under the terms of the GNU General Public License as published by
+  * the Free Software Foundation; either version 2 of the License, or
+  * (at your option) any later version.
+  *
+  * This program is distributed in the hope that it will be useful,
+  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  * GNU General Public License for more details.
+  *
+  * You should have received a copy of the GNU General Public License
+  * along with this program; if not, write to the Free Software
+  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+  */
+
+#include <linux/delay.h>
+#include <linux/suspend.h>
+#include <asm/firmware.h>
+#include <asm/hvcall.h>
+#include <asm/machdep.h>
+#include <asm/mmu.h>
+#include <asm/rtas.h>
+
+static u64 stream_id;
+static struct sys_device suspend_sysdev;
+static DECLARE_COMPLETION(suspend_work);
+static struct rtas_suspend_me_data suspend_data;
+static atomic_t suspending;
+
+/**
+ * pseries_suspend_begin - First phase of hibernation
+ *
+ * Check to ensure we are in a valid state to hibernate
+ *
+ * Return value:
+ *      0 on success / other on failure
+ **/
+static int pseries_suspend_begin(suspend_state_t state)
+{
+        long vasi_state, rc;
+        unsigned long retbuf[PLPAR_HCALL_BUFSIZE];
+
+        /* Make sure the state is valid */
+        rc = plpar_hcall(H_VASI_STATE, retbuf, stream_id);
+
+        vasi_state = retbuf[0];
+
+        if (rc) {
+                pr_err("pseries_suspend_begin: vasi_state returned %ld\n",rc);
+                return rc;
+        } else if (vasi_state == H_VASI_ENABLED) {
+                return -EAGAIN;
+        } else if (vasi_state != H_VASI_SUSPENDING) {
+                pr_err("pseries_suspend_begin: vasi_state returned state %ld\n",
+                       vasi_state);
+                return -EIO;
+        }
+
+        return 0;
+}
+
+/**
+ * pseries_suspend_cpu - Suspend a single CPU
+ *
+ * Makes the H_JOIN call to suspend the CPU
+ *
+ **/
+static int pseries_suspend_cpu(void)
+{
+        if (atomic_read(&suspending))
+                return rtas_suspend_cpu(&suspend_data);
+        return 0;
+}
+
+/**
+ * pseries_suspend_enter - Final phase of hibernation
+ *
+ * Return value:
+ *      0 on success / other on failure
+ **/
+static int pseries_suspend_enter(suspend_state_t state)
+{
+        int rc = rtas_suspend_last_cpu(&suspend_data);
+
+        atomic_set(&suspending, 0);
+        atomic_set(&suspend_data.done, 1);
+        return rc;
+}
+
+/**
+ * pseries_prepare_late - Prepare to suspend all other CPUs
+ *
+ * Return value:
+ *      0 on success / other on failure
+ **/
+static int pseries_prepare_late(void)
+{
+        atomic_set(&suspending, 1);
+        atomic_set(&suspend_data.working, 0);
+        atomic_set(&suspend_data.done, 0);
+        atomic_set(&suspend_data.error, 0);
+        suspend_data.complete = &suspend_work;
+        INIT_COMPLETION(suspend_work);
+        return 0;
+}
+
+/**
+ * store_hibernate - Initiate partition hibernation
+ * @classdev:   sysdev class struct
+ * @attr:               class device attribute struct
+ * @buf:                buffer
+ * @count:              buffer size
+ *
+ * Write the stream ID received from the HMC to this file
+ * to trigger hibernating the partition
+ *
+ * Return value:
+ *      number of bytes printed to buffer / other on failure
+ **/
+static ssize_t store_hibernate(struct sysdev_class *classdev,
+                               struct sysdev_class_attribute *attr,
+                               const char *buf, size_t count)
+{
+        int rc;
+
+        if (!capable(CAP_SYS_ADMIN))
+                return -EPERM;
+
+        stream_id = simple_strtoul(buf, NULL, 16);
+
+        do {
+                rc = pseries_suspend_begin(PM_SUSPEND_MEM);
+                if (rc == -EAGAIN)
+                        ssleep(1);
+        } while (rc == -EAGAIN);
+
+        if (!rc)
+                rc = pm_suspend(PM_SUSPEND_MEM);
+
+        stream_id = 0;
+
+        if (!rc)
+                rc = count;
+        return rc;
+}
+
+static SYSDEV_CLASS_ATTR(hibernate, S_IWUSR, NULL, store_hibernate);
+
+static struct sysdev_class suspend_sysdev_class = {
+        .name = "power",
+};
+
+static struct platform_suspend_ops pseries_suspend_ops = {
+        .valid          = suspend_valid_only_mem,
+        .begin          = pseries_suspend_begin,
+        .prepare_late   = pseries_prepare_late,
+        .enter          = pseries_suspend_enter,
+};
+
+/**
+ * pseries_suspend_sysfs_register - Register with sysfs
+ *
+ * Return value:
+ *      0 on success / other on failure
+ **/
+static int pseries_suspend_sysfs_register(struct sys_device *sysdev)
+{
+        int rc;
+
+        if ((rc = sysdev_class_register(&suspend_sysdev_class)))
+                return rc;
+
+        sysdev->id = 0;
+        sysdev->cls = &suspend_sysdev_class;
+
+        if ((rc = sysdev_class_create_file(&suspend_sysdev_class, &attr_hibernate)))
+                goto class_unregister;
+
+        return 0;
+
+class_unregister:
+        sysdev_class_unregister(&suspend_sysdev_class);
+        return rc;
+}
+
+/**
+ * pseries_suspend_init - initcall for pSeries suspend
+ *
+ * Return value:
+ *      0 on success / other on failure
+ **/
+static int __init pseries_suspend_init(void)
+{
+        int rc;
+
+        if (!machine_is(pseries) || !firmware_has_feature(FW_FEATURE_LPAR))
+                return 0;
+
+        suspend_data.token = rtas_token("ibm,suspend-me");
+        if (suspend_data.token == RTAS_UNKNOWN_SERVICE)
+                return 0;
+
+        if ((rc = pseries_suspend_sysfs_register(&suspend_sysdev)))
+                return rc;
+
+        ppc_md.suspend_disable_cpu = pseries_suspend_cpu;
+        suspend_set_ops(&pseries_suspend_ops);
+        return 0;
+}
+
+__initcall(pseries_suspend_init);
diff --git a/arch/powerpc/platforms/pseries/xics.c b/arch/powerpc/platforms/pseries/xics.c
index f19d19468393..5b22b07c8f67 100644
--- a/arch/powerpc/platforms/pseries/xics.c
+++ b/arch/powerpc/platforms/pseries/xics.c
@@ -549,8 +549,6 @@ static irqreturn_t xics_ipi_dispatch(int cpu)
 {
         unsigned long *tgt = &per_cpu(xics_ipi_message, cpu);
 
-        WARN_ON(cpu_is_offline(cpu));
-
         mb();   /* order mmio clearing qirr */
         while (*tgt) {
                 if (test_and_clear_bit(PPC_MSG_CALL_FUNCTION, tgt)) {
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 356c6a0e1b23..209384b6e039 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -412,6 +412,7 @@ DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4080, quirk_fsl_pcie_header);
 #endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */
 
 #if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x)
+DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8308, quirk_fsl_pcie_header);
 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8314E, quirk_fsl_pcie_header);
 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8314, quirk_fsl_pcie_header);
 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8315E, quirk_fsl_pcie_header);
diff --git a/arch/powerpc/sysdev/fsl_soc.h b/arch/powerpc/sysdev/fsl_soc.h
index 42381bb6cd51..53609489a62b 100644
--- a/arch/powerpc/sysdev/fsl_soc.h
+++ b/arch/powerpc/sysdev/fsl_soc.h
@@ -30,6 +30,7 @@ struct platform_diu_data_ops {
         void (*set_pixel_clock) (unsigned int pixclock);
         ssize_t (*show_monitor_port) (int monitor_port, char *buf);
         int (*set_sysfs_monitor_port) (int val);
+        void (*release_bootmem) (void);
 };
 
 extern struct platform_diu_data_ops diu_ops;
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index 20b73c025a45..7c1342618a30 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -1636,6 +1636,24 @@ void __devinit smp_mpic_setup_cpu(int cpu)
 {
         mpic_setup_this_cpu();
 }
+
+void mpic_reset_core(int cpu)
+{
+        struct mpic *mpic = mpic_primary;
+        u32 pir;
+        int cpuid = get_hard_smp_processor_id(cpu);
+
+        /* Set target bit for core reset */
+        pir = mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
+        pir |= (1 << cpuid);
+        mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
+        mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
+
+        /* Restore target bit after reset complete */
+        pir &= ~(1 << cpuid);
+        mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
+        mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
+}
 #endif /* CONFIG_SMP */
 
 #ifdef CONFIG_PM
diff --git a/arch/powerpc/sysdev/mpic.h b/arch/powerpc/sysdev/mpic.h
index eff433c322a0..e4a6df77b8d7 100644
--- a/arch/powerpc/sysdev/mpic.h
+++ b/arch/powerpc/sysdev/mpic.h
@@ -37,5 +37,6 @@ static inline int mpic_pasemi_msi_init(struct mpic *mpic)
 extern int mpic_set_irq_type(unsigned int virq, unsigned int flow_type);
 extern void mpic_set_vector(unsigned int virq, unsigned int vector);
 extern int mpic_set_affinity(unsigned int irq, const struct cpumask *cpumask);
+extern void mpic_reset_core(int cpu);
 
 #endif /* _POWERPC_SYSDEV_MPIC_H */
diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
index 8bad7d5f32af..0554445200bf 100644
--- a/arch/powerpc/xmon/xmon.c
+++ b/arch/powerpc/xmon/xmon.c
@@ -155,6 +155,9 @@ static int do_spu_cmd(void);
 #ifdef CONFIG_44x
 static void dump_tlb_44x(void);
 #endif
+#ifdef CONFIG_PPC_BOOK3E
+static void dump_tlb_book3e(void);
+#endif
 
 static int xmon_no_auto_backtrace;
 
@@ -888,6 +891,11 @@ cmds(struct pt_regs *excp)
                         dump_tlb_44x();
                         break;
 #endif
+#ifdef CONFIG_PPC_BOOK3E
+                case 'u':
+                        dump_tlb_book3e();
+                        break;
+#endif
                 default:
                         printf("Unrecognized command: ");
                         do {
@@ -2701,6 +2709,150 @@ static void dump_tlb_44x(void)
 }
 #endif /* CONFIG_44x */
 
+#ifdef CONFIG_PPC_BOOK3E
+static void dump_tlb_book3e(void)
+{
+        u32 mmucfg, pidmask, lpidmask;
+        u64 ramask;
+        int i, tlb, ntlbs, pidsz, lpidsz, rasz, lrat = 0;
+        int mmu_version;
+        static const char *pgsz_names[] = {
+                "  1K",
+                "  2K",
+                "  4K",
+                "  8K",
+                " 16K",
+                " 32K",
+                " 64K",
+                "128K",
+                "256K",
+                "512K",
+                "  1M",
+                "  2M",
+                "  4M",
+                "  8M",
+                " 16M",
+                " 32M",
+                " 64M",
+                "128M",
+                "256M",
+                "512M",
+                "  1G",
+                "  2G",
+                "  4G",
+                "  8G",
+                " 16G",
+                " 32G",
+                " 64G",
+                "128G",
+                "256G",
+                "512G",
+                "  1T",
+                "  2T",
+        };
+
+        /* Gather some infos about the MMU */
+        mmucfg = mfspr(SPRN_MMUCFG);
+        mmu_version = (mmucfg & 3) + 1;
+        ntlbs = ((mmucfg >> 2) & 3) + 1;
+        pidsz = ((mmucfg >> 6) & 0x1f) + 1;
+        lpidsz = (mmucfg >> 24) & 0xf;
+        rasz = (mmucfg >> 16) & 0x7f;
+        if ((mmu_version > 1) && (mmucfg & 0x10000))
+                lrat = 1;
+        printf("Book3E MMU MAV=%d.0,%d TLBs,%d-bit PID,%d-bit LPID,%d-bit RA\n",
+               mmu_version, ntlbs, pidsz, lpidsz, rasz);
+        pidmask = (1ul << pidsz) - 1;
+        lpidmask = (1ul << lpidsz) - 1;
+        ramask = (1ull << rasz) - 1;
+
+        for (tlb = 0; tlb < ntlbs; tlb++) {
+                u32 tlbcfg;
+                int nent, assoc, new_cc = 1;
+                printf("TLB %d:\n------\n", tlb);
+                switch(tlb) {
+                case 0:
+                        tlbcfg = mfspr(SPRN_TLB0CFG);
+                        break;
+                case 1:
+                        tlbcfg = mfspr(SPRN_TLB1CFG);
+                        break;
+                case 2:
+                        tlbcfg = mfspr(SPRN_TLB2CFG);
+                        break;
+                case 3:
+                        tlbcfg = mfspr(SPRN_TLB3CFG);
+                        break;
+                default:
+                        printf("Unsupported TLB number !\n");
+                        continue;
+                }
+                nent = tlbcfg & 0xfff;
+                assoc = (tlbcfg >> 24) & 0xff;
+                for (i = 0; i < nent; i++) {
+                        u32 mas0 = MAS0_TLBSEL(tlb);
+                        u32 mas1 = MAS1_TSIZE(BOOK3E_PAGESZ_4K);
+                        u64 mas2 = 0;
+                        u64 mas7_mas3;
+                        int esel = i, cc = i;
+
+                        if (assoc != 0) {
+                                cc = i / assoc;
+                                esel = i % assoc;
+                                mas2 = cc * 0x1000;
+                        }
+
+                        mas0 |= MAS0_ESEL(esel);
+                        mtspr(SPRN_MAS0, mas0);
+                        mtspr(SPRN_MAS1, mas1);
+                        mtspr(SPRN_MAS2, mas2);
+                        asm volatile("tlbre  0,0,0" : : : "memory");
+                        mas1 = mfspr(SPRN_MAS1);
+                        mas2 = mfspr(SPRN_MAS2);
+                        mas7_mas3 = mfspr(SPRN_MAS7_MAS3);
+                        if (assoc && (i % assoc) == 0)
+                                new_cc = 1;
+                        if (!(mas1 & MAS1_VALID))
+                                continue;
+                        if (assoc == 0)
+                                printf("%04x- ", i);
+                        else if (new_cc)
+                                printf("%04x-%c", cc, 'A' + esel);
+                        else
+                                printf("    |%c", 'A' + esel);
+                        new_cc = 0;
+                        printf(" %016llx %04x %s %c%c AS%c",
+                               mas2 & ~0x3ffull,
+                               (mas1 >> 16) & 0x3fff,
+                               pgsz_names[(mas1 >> 7) & 0x1f],
+                               mas1 & MAS1_IND ? 'I' : ' ',
+                               mas1 & MAS1_IPROT ? 'P' : ' ',
+                               mas1 & MAS1_TS ? '1' : '0');
+                        printf(" %c%c%c%c%c%c%c",
+                               mas2 & MAS2_X0 ? 'a' : ' ',
+                               mas2 & MAS2_X1 ? 'v' : ' ',
+                               mas2 & MAS2_W  ? 'w' : ' ',
+                               mas2 & MAS2_I  ? 'i' : ' ',
+                               mas2 & MAS2_M  ? 'm' : ' ',
+                               mas2 & MAS2_G  ? 'g' : ' ',
+                               mas2 & MAS2_E  ? 'e' : ' ');
+                        printf(" %016llx", mas7_mas3 & ramask & ~0x7ffull);
+                        if (mas1 & MAS1_IND)
+                                printf(" %s\n",
+                                       pgsz_names[(mas7_mas3 >> 1) & 0x1f]);
+                        else
+                                printf(" U%c%c%c S%c%c%c\n",
+                                       mas7_mas3 & MAS3_UX ? 'x' : ' ',
+                                       mas7_mas3 & MAS3_UW ? 'w' : ' ',
+                                       mas7_mas3 & MAS3_UR ? 'r' : ' ',
+                                       mas7_mas3 & MAS3_SX ? 'x' : ' ',
+                                       mas7_mas3 & MAS3_SW ? 'w' : ' ',
+                                       mas7_mas3 & MAS3_SR ? 'r' : ' ');
+                }
+        }
+}
+#endif /* CONFIG_PPC_BOOK3E */
+
 static void xmon_init(int enable)
 {
 #ifdef CONFIG_PPC_ISERIES
diff --git a/arch/sparc/mm/iommu.c b/arch/sparc/mm/iommu.c
index b2e6e73888b5..0e8ae298b3c3 100644
--- a/arch/sparc/mm/iommu.c
+++ b/arch/sparc/mm/iommu.c
@@ -63,7 +63,7 @@ static void __init sbus_iommu_init(struct of_device *op)
         unsigned long *bitmap;
         unsigned long tmp;
 
-        iommu = kmalloc(sizeof(struct iommu_struct), GFP_ATOMIC);
+        iommu = kmalloc(sizeof(struct iommu_struct), GFP_KERNEL);
         if (!iommu) {
                 prom_printf("Unable to allocate iommu structure\n");
                 prom_halt();
diff --git a/arch/x86/include/asm/hypervisor.h b/arch/x86/include/asm/hypervisor.h
index 70abda7058c8..ff2546ce7178 100644
--- a/arch/x86/include/asm/hypervisor.h
+++ b/arch/x86/include/asm/hypervisor.h
@@ -45,5 +45,6 @@ extern const struct hypervisor_x86 *x86_hyper;
 /* Recognized hypervisors */
 extern const struct hypervisor_x86 x86_hyper_vmware;
 extern const struct hypervisor_x86 x86_hyper_ms_hyperv;
+extern const struct hypervisor_x86 x86_hyper_xen_hvm;
 
 #endif
diff --git a/arch/x86/include/asm/irq_vectors.h b/arch/x86/include/asm/irq_vectors.h
index 8767d99c4f64..e2ca30092557 100644
--- a/arch/x86/include/asm/irq_vectors.h
+++ b/arch/x86/include/asm/irq_vectors.h
@@ -125,6 +125,9 @@
  */
 #define MCE_SELF_VECTOR                 0xeb
 
+/* Xen vector callback to receive events in a HVM domain */
+#define XEN_HVM_EVTCHN_CALLBACK         0xe9
+
 #define NR_VECTORS                       256
 
 #define FPU_IRQ                           13
diff --git a/arch/x86/include/asm/setup.h b/arch/x86/include/asm/setup.h
index 86b1506f4179..ef292c792d74 100644
--- a/arch/x86/include/asm/setup.h
+++ b/arch/x86/include/asm/setup.h
@@ -82,7 +82,7 @@ void *extend_brk(size_t size, size_t align);
  * executable.)
  */
 #define RESERVE_BRK(name,sz)                                            \
-        static void __section(.discard) __used                          \
+        static void __section(.discard.text) __used                     \
         __brk_reservation_fn_##name##__(void) {                         \
                 asm volatile (                                          \
                         ".pushsection .brk_reservation,\"aw\",@nobits;" \
diff --git a/arch/x86/include/asm/xen/hypercall.h b/arch/x86/include/asm/xen/hypercall.h
index 9c371e4a9fa6..7fda040a76cd 100644
--- a/arch/x86/include/asm/xen/hypercall.h
+++ b/arch/x86/include/asm/xen/hypercall.h
@@ -417,6 +417,12 @@ HYPERVISOR_nmi_op(unsigned long op, unsigned long arg)
         return _hypercall2(int, nmi_op, op, arg);
 }
 
+static inline unsigned long __must_check
+HYPERVISOR_hvm_op(int op, void *arg)
+{
+       return _hypercall2(unsigned long, hvm_op, op, arg);
+}
+
 static inline void
 MULTI_fpu_taskswitch(struct multicall_entry *mcl, int set)
 {
diff --git a/arch/x86/kernel/cpu/hypervisor.c b/arch/x86/kernel/cpu/hypervisor.c
index dd531cc56a8f..8095f8611f8a 100644
--- a/arch/x86/kernel/cpu/hypervisor.c
+++ b/arch/x86/kernel/cpu/hypervisor.c
@@ -34,6 +34,9 @@ static const __initconst struct hypervisor_x86 * const hypervisors[] =
 {
         &x86_hyper_vmware,
         &x86_hyper_ms_hyperv,
+#ifdef CONFIG_XEN_PVHVM
+        &x86_hyper_xen_hvm,
+#endif
 };
 
 const struct hypervisor_x86 *x86_hyper;
diff --git a/arch/x86/kernel/entry_32.S b/arch/x86/kernel/entry_32.S
index cd49141cf153..6b196834a0dd 100644
--- a/arch/x86/kernel/entry_32.S
+++ b/arch/x86/kernel/entry_32.S
@@ -1166,6 +1166,9 @@ ENTRY(xen_failsafe_callback)
 .previous
 ENDPROC(xen_failsafe_callback)
 
+BUILD_INTERRUPT3(xen_hvm_callback_vector, XEN_HVM_EVTCHN_CALLBACK,
+                xen_evtchn_do_upcall)
+
 #endif  /* CONFIG_XEN */
 
 #ifdef CONFIG_FUNCTION_TRACER
diff --git a/arch/x86/kernel/entry_64.S b/arch/x86/kernel/entry_64.S
index 4db7c4d12ffa..649ed17f7009 100644
--- a/arch/x86/kernel/entry_64.S
+++ b/arch/x86/kernel/entry_64.S
@@ -1329,6 +1329,9 @@ ENTRY(xen_failsafe_callback)
         CFI_ENDPROC
 END(xen_failsafe_callback)
 
+apicinterrupt XEN_HVM_EVTCHN_CALLBACK \
+        xen_hvm_callback_vector xen_evtchn_do_upcall
+
 #endif /* CONFIG_XEN */
 
 /*
diff --git a/arch/x86/xen/Kconfig b/arch/x86/xen/Kconfig
index b83e119fbeb0..68128a1b401a 100644
--- a/arch/x86/xen/Kconfig
+++ b/arch/x86/xen/Kconfig
@@ -13,6 +13,11 @@ config XEN
           kernel to boot in a paravirtualized environment under the
           Xen hypervisor.
 
+config XEN_PVHVM
+        def_bool y
+        depends on XEN
+        depends on X86_LOCAL_APIC
+
 config XEN_MAX_DOMAIN_MEMORY
        int "Maximum allowed size of a domain in gigabytes"
        default 8 if X86_32
diff --git a/arch/x86/xen/Makefile b/arch/x86/xen/Makefile
index 3bb4fc21f4f2..930954685980 100644
--- a/arch/x86/xen/Makefile
+++ b/arch/x86/xen/Makefile
@@ -12,7 +12,7 @@ CFLAGS_mmu.o			:= $(nostackp)
 
 obj-y           := enlighten.o setup.o multicalls.o mmu.o irq.o \
                         time.o xen-asm.o xen-asm_$(BITS).o \
-                        grant-table.o suspend.o
+                        grant-table.o suspend.o platform-pci-unplug.o
 
 obj-$(CONFIG_SMP)               += smp.o
 obj-$(CONFIG_PARAVIRT_SPINLOCKS)+= spinlock.o
diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c
index 65d8d79b46a8..d4ff5e83621d 100644
--- a/arch/x86/xen/enlighten.c
+++ b/arch/x86/xen/enlighten.c
@@ -11,6 +11,7 @@
  * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007
  */
 
+#include <linux/cpu.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/smp.h>
@@ -35,8 +36,10 @@
 #include <xen/interface/version.h>
 #include <xen/interface/physdev.h>
 #include <xen/interface/vcpu.h>
+#include <xen/interface/memory.h>
 #include <xen/features.h>
 #include <xen/page.h>
+#include <xen/hvm.h>
 #include <xen/hvc-console.h>
 
 #include <asm/paravirt.h>
@@ -55,7 +58,9 @@
 #include <asm/pgtable.h>
 #include <asm/tlbflush.h>
 #include <asm/reboot.h>
+#include <asm/setup.h>
 #include <asm/stackprotector.h>
+#include <asm/hypervisor.h>
 
 #include "xen-ops.h"
 #include "mmu.h"
@@ -76,6 +81,10 @@ struct shared_info xen_dummy_shared_info;
 
 void *xen_initial_gdt;
 
+RESERVE_BRK(shared_info_page_brk, PAGE_SIZE);
+__read_mostly int xen_have_vector_callback;
+EXPORT_SYMBOL_GPL(xen_have_vector_callback);
+
 /*
  * Point at some empty memory to start with. We map the real shared_info
  * page as soon as fixmap is up and running.
@@ -97,6 +106,14 @@ struct shared_info *HYPERVISOR_shared_info = (void *)&xen_dummy_shared_info;
  */
 static int have_vcpu_info_placement = 1;
 
+static void clamp_max_cpus(void)
+{
+#ifdef CONFIG_SMP
+        if (setup_max_cpus > MAX_VIRT_CPUS)
+                setup_max_cpus = MAX_VIRT_CPUS;
+#endif
+}
+
 static void xen_vcpu_setup(int cpu)
 {
         struct vcpu_register_vcpu_info info;
@@ -104,13 +121,17 @@ static void xen_vcpu_setup(int cpu)
         struct vcpu_info *vcpup;
 
         BUG_ON(HYPERVISOR_shared_info == &xen_dummy_shared_info);
-        per_cpu(xen_vcpu, cpu) = &HYPERVISOR_shared_info->vcpu_info[cpu];
 
-        if (!have_vcpu_info_placement)
-                return;         /* already tested, not available */
+        if (cpu < MAX_VIRT_CPUS)
+                per_cpu(xen_vcpu,cpu) = &HYPERVISOR_shared_info->vcpu_info[cpu];
 
-        vcpup = &per_cpu(xen_vcpu_info, cpu);
+        if (!have_vcpu_info_placement) {
+                if (cpu >= MAX_VIRT_CPUS)
+                        clamp_max_cpus();
+                return;
+        }
 
+        vcpup = &per_cpu(xen_vcpu_info, cpu);
         info.mfn = arbitrary_virt_to_mfn(vcpup);
         info.offset = offset_in_page(vcpup);
 
@@ -125,6 +146,7 @@ static void xen_vcpu_setup(int cpu)
         if (err) {
                 printk(KERN_DEBUG "register_vcpu_info failed: err=%d\n", err);
                 have_vcpu_info_placement = 0;
+                clamp_max_cpus();
         } else {
                 /* This cpu is using the registered vcpu info, even if
                    later ones fail to. */
@@ -731,7 +753,6 @@ static void set_xen_basic_apic_ops(void)
 
 #endif
 
-
 static void xen_clts(void)
 {
         struct multicall_space mcs;
@@ -926,10 +947,6 @@ static const struct pv_init_ops xen_init_ops __initdata = {
         .patch = xen_patch,
 };
 
-static const struct pv_time_ops xen_time_ops __initdata = {
-        .sched_clock = xen_sched_clock,
-};
-
 static const struct pv_cpu_ops xen_cpu_ops __initdata = {
         .cpuid = xen_cpuid,
 
@@ -1028,6 +1045,23 @@ static void xen_crash_shutdown(struct pt_regs *regs)
         xen_reboot(SHUTDOWN_crash);
 }
 
+static int
+xen_panic_event(struct notifier_block *this, unsigned long event, void *ptr)
+{
+        xen_reboot(SHUTDOWN_crash);
+        return NOTIFY_DONE;
+}
+
+static struct notifier_block xen_panic_block = {
+        .notifier_call= xen_panic_event,
+};
+
+int xen_panic_handler_init(void)
+{
+        atomic_notifier_chain_register(&panic_notifier_list, &xen_panic_block);
+        return 0;
+}
+
 static const struct machine_ops __initdata xen_machine_ops = {
         .restart = xen_restart,
         .halt = xen_machine_halt,
@@ -1067,7 +1101,6 @@ asmlinkage void __init xen_start_kernel(void)
         /* Install Xen paravirt ops */
         pv_info = xen_info;
         pv_init_ops = xen_init_ops;
-        pv_time_ops = xen_time_ops;
         pv_cpu_ops = xen_cpu_ops;
         pv_apic_ops = xen_apic_ops;
 
@@ -1075,13 +1108,7 @@ asmlinkage void __init xen_start_kernel(void)
         x86_init.oem.arch_setup = xen_arch_setup;
         x86_init.oem.banner = xen_banner;
 
-        x86_init.timers.timer_init = xen_time_init;
-        x86_init.timers.setup_percpu_clockev = x86_init_noop;
-        x86_cpuinit.setup_percpu_clockev = x86_init_noop;
-
-        x86_platform.calibrate_tsc = xen_tsc_khz;
-        x86_platform.get_wallclock = xen_get_wallclock;
-        x86_platform.set_wallclock = xen_set_wallclock;
+        xen_init_time_ops();
 
         /*
          * Set up some pagetable state before starting to set any ptes.
@@ -1206,3 +1233,139 @@ asmlinkage void __init xen_start_kernel(void)
         x86_64_start_reservations((char *)__pa_symbol(&boot_params));
 #endif
 }
+
+static uint32_t xen_cpuid_base(void)
+{
+        uint32_t base, eax, ebx, ecx, edx;
+        char signature[13];
+
+        for (base = 0x40000000; base < 0x40010000; base += 0x100) {
+                cpuid(base, &eax, &ebx, &ecx, &edx);
+                *(uint32_t *)(signature + 0) = ebx;
+                *(uint32_t *)(signature + 4) = ecx;
+                *(uint32_t *)(signature + 8) = edx;
+                signature[12] = 0;
+
+                if (!strcmp("XenVMMXenVMM", signature) && ((eax - base) >= 2))
+                        return base;
+        }
+
+        return 0;
+}
+
+static int init_hvm_pv_info(int *major, int *minor)
+{
+        uint32_t eax, ebx, ecx, edx, pages, msr, base;
+        u64 pfn;
+
+        base = xen_cpuid_base();
+        cpuid(base + 1, &eax, &ebx, &ecx, &edx);
+
+        *major = eax >> 16;
+        *minor = eax & 0xffff;
+        printk(KERN_INFO "Xen version %d.%d.\n", *major, *minor);
+
+        cpuid(base + 2, &pages, &msr, &ecx, &edx);
+
+        pfn = __pa(hypercall_page);
+        wrmsr_safe(msr, (u32)pfn, (u32)(pfn >> 32));
+
+        xen_setup_features();
+
+        pv_info = xen_info;
+        pv_info.kernel_rpl = 0;
+
+        xen_domain_type = XEN_HVM_DOMAIN;
+
+        return 0;
+}
+
+void xen_hvm_init_shared_info(void)
+{
+        int cpu;
+        struct xen_add_to_physmap xatp;
+        static struct shared_info *shared_info_page = 0;
+
+        if (!shared_info_page)
+                shared_info_page = (struct shared_info *)
+                        extend_brk(PAGE_SIZE, PAGE_SIZE);
+        xatp.domid = DOMID_SELF;
+        xatp.idx = 0;
+        xatp.space = XENMAPSPACE_shared_info;
+        xatp.gpfn = __pa(shared_info_page) >> PAGE_SHIFT;
+        if (HYPERVISOR_memory_op(XENMEM_add_to_physmap, &xatp))
+                BUG();
+
+        HYPERVISOR_shared_info = (struct shared_info *)shared_info_page;
+
+        /* xen_vcpu is a pointer to the vcpu_info struct in the shared_info
+         * page, we use it in the event channel upcall and in some pvclock
+         * related functions. We don't need the vcpu_info placement
+         * optimizations because we don't use any pv_mmu or pv_irq op on
+         * HVM.
+         * When xen_hvm_init_shared_info is run at boot time only vcpu 0 is
+         * online but xen_hvm_init_shared_info is run at resume time too and
+         * in that case multiple vcpus might be online. */
+        for_each_online_cpu(cpu) {
+                per_cpu(xen_vcpu, cpu) = &HYPERVISOR_shared_info->vcpu_info[cpu];
+        }
+}
+
+#ifdef CONFIG_XEN_PVHVM
+static int __cpuinit xen_hvm_cpu_notify(struct notifier_block *self,
+                                    unsigned long action, void *hcpu)
+{
+        int cpu = (long)hcpu;
+        switch (action) {
+        case CPU_UP_PREPARE:
+                per_cpu(xen_vcpu, cpu) = &HYPERVISOR_shared_info->vcpu_info[cpu];
+                break;
+        default:
+                break;
+        }
+        return NOTIFY_OK;
+}
+
+static struct notifier_block __cpuinitdata xen_hvm_cpu_notifier = {
+        .notifier_call  = xen_hvm_cpu_notify,
+};
+
+static void __init xen_hvm_guest_init(void)
+{
+        int r;
+        int major, minor;
+
+        r = init_hvm_pv_info(&major, &minor);
+        if (r < 0)
+                return;
+
+        xen_hvm_init_shared_info();
+
+        if (xen_feature(XENFEAT_hvm_callback_vector))
+                xen_have_vector_callback = 1;
+        register_cpu_notifier(&xen_hvm_cpu_notifier);
+        xen_unplug_emulated_devices();
+        have_vcpu_info_placement = 0;
+        x86_init.irqs.intr_init = xen_init_IRQ;
+        xen_hvm_init_time_ops();
+        xen_hvm_init_mmu_ops();
+}
+
+static bool __init xen_hvm_platform(void)
+{
+        if (xen_pv_domain())
+                return false;
+
+        if (!xen_cpuid_base())
+                return false;
+
+        return true;
+}
+
+const __refconst struct hypervisor_x86 x86_hyper_xen_hvm = {
+        .name                   = "Xen HVM",
+        .detect                 = xen_hvm_platform,
+        .init_platform          = xen_hvm_guest_init,
+};
+EXPORT_SYMBOL(x86_hyper_xen_hvm);
+#endif
diff --git a/arch/x86/xen/mmu.c b/arch/x86/xen/mmu.c
index 914f04695ce5..413b19b3d0fe 100644
--- a/arch/x86/xen/mmu.c
+++ b/arch/x86/xen/mmu.c
@@ -58,6 +58,7 @@
 
 #include <xen/page.h>
 #include <xen/interface/xen.h>
+#include <xen/interface/hvm/hvm_op.h>
 #include <xen/interface/version.h>
 #include <xen/hvc-console.h>
 
@@ -1941,6 +1942,40 @@ void __init xen_init_mmu_ops(void)
         pv_mmu_ops = xen_mmu_ops;
 }
 
+#ifdef CONFIG_XEN_PVHVM
+static void xen_hvm_exit_mmap(struct mm_struct *mm)
+{
+        struct xen_hvm_pagetable_dying a;
+        int rc;
+
+        a.domid = DOMID_SELF;
+        a.gpa = __pa(mm->pgd);
+        rc = HYPERVISOR_hvm_op(HVMOP_pagetable_dying, &a);
+        WARN_ON_ONCE(rc < 0);
+}
+
+static int is_pagetable_dying_supported(void)
+{
+        struct xen_hvm_pagetable_dying a;
+        int rc = 0;
+
+        a.domid = DOMID_SELF;
+        a.gpa = 0x00;
+        rc = HYPERVISOR_hvm_op(HVMOP_pagetable_dying, &a);
+        if (rc < 0) {
+                printk(KERN_DEBUG "HVMOP_pagetable_dying not supported\n");
+                return 0;
+        }
+        return 1;
+}
+
+void __init xen_hvm_init_mmu_ops(void)
+{
+        if (is_pagetable_dying_supported())
+                pv_mmu_ops.exit_mmap = xen_hvm_exit_mmap;
+}
+#endif
+
 #ifdef CONFIG_XEN_DEBUG_FS
 
 static struct dentry *d_mmu_debug;
diff --git a/arch/x86/xen/mmu.h b/arch/x86/xen/mmu.h
index 5fe6bc7f5ecf..fa938c4aa2f7 100644
--- a/arch/x86/xen/mmu.h
+++ b/arch/x86/xen/mmu.h
@@ -60,4 +60,5 @@ void  xen_ptep_modify_prot_commit(struct mm_struct *mm, unsigned long addr,
 unsigned long xen_read_cr2_direct(void);
 
 extern void xen_init_mmu_ops(void);
+extern void xen_hvm_init_mmu_ops(void);
 #endif  /* _XEN_MMU_H */
diff --git a/arch/x86/xen/platform-pci-unplug.c b/arch/x86/xen/platform-pci-unplug.c
new file mode 100644
index 000000000000..554c002a1e1a
--- /dev/null
+++ b/arch/x86/xen/platform-pci-unplug.c
@@ -0,0 +1,137 @@
+/******************************************************************************
+ * platform-pci-unplug.c
+ *
+ * Xen platform PCI device driver
+ * Copyright (c) 2010, Citrix
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
+ * Place - Suite 330, Boston, MA 02111-1307 USA.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+
+#include <xen/platform_pci.h>
+
+#define XEN_PLATFORM_ERR_MAGIC -1
+#define XEN_PLATFORM_ERR_PROTOCOL -2
+#define XEN_PLATFORM_ERR_BLACKLIST -3
+
+/* store the value of xen_emul_unplug after the unplug is done */
+int xen_platform_pci_unplug;
+EXPORT_SYMBOL_GPL(xen_platform_pci_unplug);
+#ifdef CONFIG_XEN_PVHVM
+static int xen_emul_unplug;
+
+static int __init check_platform_magic(void)
+{
+        short magic;
+        char protocol;
+
+        magic = inw(XEN_IOPORT_MAGIC);
+        if (magic != XEN_IOPORT_MAGIC_VAL) {
+                printk(KERN_ERR "Xen Platform PCI: unrecognised magic value\n");
+                return XEN_PLATFORM_ERR_MAGIC;
+        }
+
+        protocol = inb(XEN_IOPORT_PROTOVER);
+
+        printk(KERN_DEBUG "Xen Platform PCI: I/O protocol version %d\n",
+                        protocol);
+
+        switch (protocol) {
+        case 1:
+                outw(XEN_IOPORT_LINUX_PRODNUM, XEN_IOPORT_PRODNUM);
+                outl(XEN_IOPORT_LINUX_DRVVER, XEN_IOPORT_DRVVER);
+                if (inw(XEN_IOPORT_MAGIC) != XEN_IOPORT_MAGIC_VAL) {
+                        printk(KERN_ERR "Xen Platform: blacklisted by host\n");
+                        return XEN_PLATFORM_ERR_BLACKLIST;
+                }
+                break;
+        default:
+                printk(KERN_WARNING "Xen Platform PCI: unknown I/O protocol version");
+                return XEN_PLATFORM_ERR_PROTOCOL;
+        }
+
+        return 0;
+}
+
+void __init xen_unplug_emulated_devices(void)
+{
+        int r;
+
+        /* check the version of the xen platform PCI device */
+        r = check_platform_magic();
+        /* If the version matches enable the Xen platform PCI driver.
+         * Also enable the Xen platform PCI driver if the version is really old
+         * and the user told us to ignore it. */
+        if (r && !(r == XEN_PLATFORM_ERR_MAGIC &&
+                        (xen_emul_unplug & XEN_UNPLUG_IGNORE)))
+                return;
+        /* Set the default value of xen_emul_unplug depending on whether or
+         * not the Xen PV frontends and the Xen platform PCI driver have
+         * been compiled for this kernel (modules or built-in are both OK). */
+        if (!xen_emul_unplug) {
+                if (xen_must_unplug_nics()) {
+                        printk(KERN_INFO "Netfront and the Xen platform PCI driver have "
+                                        "been compiled for this kernel: unplug emulated NICs.\n");
+                        xen_emul_unplug |= XEN_UNPLUG_ALL_NICS;
+                }
+                if (xen_must_unplug_disks()) {
+                        printk(KERN_INFO "Blkfront and the Xen platform PCI driver have "
+                                        "been compiled for this kernel: unplug emulated disks.\n"
+                                        "You might have to change the root device\n"
+                                        "from /dev/hd[a-d] to /dev/xvd[a-d]\n"
+                                        "in your root= kernel command line option\n");
+                        xen_emul_unplug |= XEN_UNPLUG_ALL_IDE_DISKS;
+                }
+        }
+        /* Now unplug the emulated devices */
+        if (!(xen_emul_unplug & XEN_UNPLUG_IGNORE))
+                outw(xen_emul_unplug, XEN_IOPORT_UNPLUG);
+        xen_platform_pci_unplug = xen_emul_unplug;
+}
+
+static int __init parse_xen_emul_unplug(char *arg)
+{
+        char *p, *q;
+        int l;
+
+        for (p = arg; p; p = q) {
+                q = strchr(p, ',');
+                if (q) {
+                        l = q - p;
+                        q++;
+                } else {
+                        l = strlen(p);
+                }
+                if (!strncmp(p, "all", l))
+                        xen_emul_unplug |= XEN_UNPLUG_ALL;
+                else if (!strncmp(p, "ide-disks", l))
+                        xen_emul_unplug |= XEN_UNPLUG_ALL_IDE_DISKS;
+                else if (!strncmp(p, "aux-ide-disks", l))
+                        xen_emul_unplug |= XEN_UNPLUG_AUX_IDE_DISKS;
+                else if (!strncmp(p, "nics", l))
+                        xen_emul_unplug |= XEN_UNPLUG_ALL_NICS;
+                else if (!strncmp(p, "ignore", l))
+                        xen_emul_unplug |= XEN_UNPLUG_IGNORE;
+                else
+                        printk(KERN_WARNING "unrecognised option '%s' "
+                                 "in parameter 'xen_emul_unplug'\n", p);
+        }
+        return 0;
+}
+early_param("xen_emul_unplug", parse_xen_emul_unplug);
+#endif
diff --git a/arch/x86/xen/setup.c b/arch/x86/xen/setup.c
index ad0047f47cd4..328b00305426 100644
--- a/arch/x86/xen/setup.c
+++ b/arch/x86/xen/setup.c
@@ -20,6 +20,7 @@
 #include <xen/page.h>
 #include <xen/interface/callback.h>
 #include <xen/interface/physdev.h>
+#include <xen/interface/memory.h>
 #include <xen/features.h>
 
 #include "xen-ops.h"
@@ -32,6 +33,73 @@ extern void xen_sysenter_target(void);
 extern void xen_syscall_target(void);
 extern void xen_syscall32_target(void);
 
+static unsigned long __init xen_release_chunk(phys_addr_t start_addr,
+                                              phys_addr_t end_addr)
+{
+        struct xen_memory_reservation reservation = {
+                .address_bits = 0,
+                .extent_order = 0,
+                .domid        = DOMID_SELF
+        };
+        unsigned long start, end;
+        unsigned long len = 0;
+        unsigned long pfn;
+        int ret;
+
+        start = PFN_UP(start_addr);
+        end = PFN_DOWN(end_addr);
+
+        if (end <= start)
+                return 0;
+
+        printk(KERN_INFO "xen_release_chunk: looking at area pfn %lx-%lx: ",
+               start, end);
+        for(pfn = start; pfn < end; pfn++) {
+                unsigned long mfn = pfn_to_mfn(pfn);
+
+                /* Make sure pfn exists to start with */
+                if (mfn == INVALID_P2M_ENTRY || mfn_to_pfn(mfn) != pfn)
+                        continue;
+
+                set_xen_guest_handle(reservation.extent_start, &mfn);
+                reservation.nr_extents = 1;
+
+                ret = HYPERVISOR_memory_op(XENMEM_decrease_reservation,
+                                           &reservation);
+                WARN(ret != 1, "Failed to release memory %lx-%lx err=%d\n",
+                     start, end, ret);
+                if (ret == 1) {
+                        set_phys_to_machine(pfn, INVALID_P2M_ENTRY);
+                        len++;
+                }
+        }
+        printk(KERN_CONT "%ld pages freed\n", len);
+
+        return len;
+}
+
+static unsigned long __init xen_return_unused_memory(unsigned long max_pfn,
+                                                     const struct e820map *e820)
+{
+        phys_addr_t max_addr = PFN_PHYS(max_pfn);
+        phys_addr_t last_end = 0;
+        unsigned long released = 0;
+        int i;
+
+        for (i = 0; i < e820->nr_map && last_end < max_addr; i++) {
+                phys_addr_t end = e820->map[i].addr;
+                end = min(max_addr, end);
+
+                released += xen_release_chunk(last_end, end);
+                last_end = e820->map[i].addr + e820->map[i].size;
+        }
+
+        if (last_end < max_addr)
+                released += xen_release_chunk(last_end, max_addr);
+
+        printk(KERN_INFO "released %ld pages of unused memory\n", released);
+        return released;
+}
 
 /**
  * machine_specific_memory_setup - Hook for machine specific memory setup.
@@ -67,6 +135,8 @@ char * __init xen_memory_setup(void)
 
         sanitize_e820_map(e820.map, ARRAY_SIZE(e820.map), &e820.nr_map);
 
+        xen_return_unused_memory(xen_start_info->nr_pages, &e820);
+
         return "Xen";
 }
 
@@ -156,6 +226,8 @@ void __init xen_arch_setup(void)
         struct physdev_set_iopl set_iopl;
         int rc;
 
+        xen_panic_handler_init();
+
         HYPERVISOR_vm_assist(VMASST_CMD_enable, VMASST_TYPE_4gb_segments);
         HYPERVISOR_vm_assist(VMASST_CMD_enable, VMASST_TYPE_writable_pagetables);
 
diff --git a/arch/x86/xen/smp.c b/arch/x86/xen/smp.c
index a29693fd3138..25f232b18a82 100644
--- a/arch/x86/xen/smp.c
+++ b/arch/x86/xen/smp.c
@@ -394,6 +394,8 @@ static void stop_self(void *v)
         load_cr3(swapper_pg_dir);
         /* should set up a minimal gdt */
 
+        set_cpu_online(cpu, false);
+
         HYPERVISOR_vcpu_op(VCPUOP_down, cpu, NULL);
         BUG();
 }
diff --git a/arch/x86/xen/suspend.c b/arch/x86/xen/suspend.c
index a9c661108034..1d789d56877c 100644
--- a/arch/x86/xen/suspend.c
+++ b/arch/x86/xen/suspend.c
@@ -26,6 +26,18 @@ void xen_pre_suspend(void)
                 BUG();
 }
 
+void xen_hvm_post_suspend(int suspend_cancelled)
+{
+        int cpu;
+        xen_hvm_init_shared_info();
+        xen_callback_vector();
+        if (xen_feature(XENFEAT_hvm_safe_pvclock)) {
+                for_each_online_cpu(cpu) {
+                        xen_setup_runstate_info(cpu);
+                }
+        }
+}
+
 void xen_post_suspend(int suspend_cancelled)
 {
         xen_build_mfn_list_list();
diff --git a/arch/x86/xen/time.c b/arch/x86/xen/time.c
index b3c6c59ed302..1a5353a753fc 100644
--- a/arch/x86/xen/time.c
+++ b/arch/x86/xen/time.c
@@ -20,6 +20,7 @@
 #include <asm/xen/hypercall.h>
 
 #include <xen/events.h>
+#include <xen/features.h>
 #include <xen/interface/xen.h>
 #include <xen/interface/vcpu.h>
 
@@ -155,47 +156,8 @@ static void do_stolen_accounting(void)
         account_idle_ticks(ticks);
 }
 
-/*
- * Xen sched_clock implementation.  Returns the number of unstolen
- * nanoseconds, which is nanoseconds the VCPU spent in RUNNING+BLOCKED
- * states.
- */
-unsigned long long xen_sched_clock(void)
-{
-        struct vcpu_runstate_info state;
-        cycle_t now;
-        u64 ret;
-        s64 offset;
-
-        /*
-         * Ideally sched_clock should be called on a per-cpu basis
-         * anyway, so preempt should already be disabled, but that's
-         * not current practice at the moment.
-         */
-        preempt_disable();
-
-        now = xen_clocksource_read();
-
-        get_runstate_snapshot(&state);
-
-        WARN_ON(state.state != RUNSTATE_running);
-
-        offset = now - state.state_entry_time;
-        if (offset < 0)
-                offset = 0;
-
-        ret = state.time[RUNSTATE_blocked] +
-                state.time[RUNSTATE_running] +
-                offset;
-
-        preempt_enable();
-
-        return ret;
-}
-
-
 /* Get the TSC speed from Xen */
-unsigned long xen_tsc_khz(void)
+static unsigned long xen_tsc_khz(void)
 {
         struct pvclock_vcpu_time_info *info =
                 &HYPERVISOR_shared_info->vcpu_info[0].time;
@@ -230,7 +192,7 @@ static void xen_read_wallclock(struct timespec *ts)
         put_cpu_var(xen_vcpu);
 }
 
-unsigned long xen_get_wallclock(void)
+static unsigned long xen_get_wallclock(void)
 {
         struct timespec ts;
 
@@ -238,7 +200,7 @@ unsigned long xen_get_wallclock(void)
         return ts.tv_sec;
 }
 
-int xen_set_wallclock(unsigned long now)
+static int xen_set_wallclock(unsigned long now)
 {
         /* do nothing for domU */
         return -1;
@@ -473,7 +435,11 @@ void xen_timer_resume(void)
         }
 }
 
-__init void xen_time_init(void)
+static const struct pv_time_ops xen_time_ops __initdata = {
+        .sched_clock = xen_clocksource_read,
+};
+
+static __init void xen_time_init(void)
 {
         int cpu = smp_processor_id();
         struct timespec tp;
@@ -497,3 +463,47 @@ __init void xen_time_init(void)
         xen_setup_timer(cpu);
         xen_setup_cpu_clockevents();
 }
+
+__init void xen_init_time_ops(void)
+{
+        pv_time_ops = xen_time_ops;
+
+        x86_init.timers.timer_init = xen_time_init;
+        x86_init.timers.setup_percpu_clockev = x86_init_noop;
+        x86_cpuinit.setup_percpu_clockev = x86_init_noop;
+
+        x86_platform.calibrate_tsc = xen_tsc_khz;
+        x86_platform.get_wallclock = xen_get_wallclock;
+        x86_platform.set_wallclock = xen_set_wallclock;
+}
+
+#ifdef CONFIG_XEN_PVHVM
+static void xen_hvm_setup_cpu_clockevents(void)
+{
+        int cpu = smp_processor_id();
+        xen_setup_runstate_info(cpu);
+        xen_setup_timer(cpu);
+        xen_setup_cpu_clockevents();
+}
+
+__init void xen_hvm_init_time_ops(void)
+{
+        /* vector callback is needed otherwise we cannot receive interrupts
+         * on cpu > 0 */
+        if (!xen_have_vector_callback && num_present_cpus() > 1)
+                return;
+        if (!xen_feature(XENFEAT_hvm_safe_pvclock)) {
+                printk(KERN_INFO "Xen doesn't support pvclock on HVM,"
+                                "disable pv timer\n");
+                return;
+        }
+
+        pv_time_ops = xen_time_ops;
+        x86_init.timers.setup_percpu_clockev = xen_time_init;
+        x86_cpuinit.setup_percpu_clockev = xen_hvm_setup_cpu_clockevents;
+
+        x86_platform.calibrate_tsc = xen_tsc_khz;
+        x86_platform.get_wallclock = xen_get_wallclock;
+        x86_platform.set_wallclock = xen_set_wallclock;
+}
+#endif
diff --git a/arch/x86/xen/xen-ops.h b/arch/x86/xen/xen-ops.h
index f9153a300bce..7c8ab86163e9 100644
--- a/arch/x86/xen/xen-ops.h
+++ b/arch/x86/xen/xen-ops.h
@@ -38,6 +38,10 @@ void xen_enable_sysenter(void);
 void xen_enable_syscall(void);
 void xen_vcpu_restore(void);
 
+void xen_callback_vector(void);
+void xen_hvm_init_shared_info(void);
+void __init xen_unplug_emulated_devices(void);
+
 void __init xen_build_dynamic_phys_to_machine(void);
 
 void xen_init_irq_ops(void);
@@ -46,11 +50,8 @@ void xen_setup_runstate_info(int cpu);
 void xen_teardown_timer(int cpu);
 cycle_t xen_clocksource_read(void);
 void xen_setup_cpu_clockevents(void);
-unsigned long xen_tsc_khz(void);
-void __init xen_time_init(void);
-unsigned long xen_get_wallclock(void);
-int xen_set_wallclock(unsigned long time);
-unsigned long long xen_sched_clock(void);
+void __init xen_init_time_ops(void);
+void __init xen_hvm_init_time_ops(void);
 
 irqreturn_t xen_debug_interrupt(int irq, void *dev_id);
 
@@ -101,4 +102,6 @@ void xen_sysret32(void);
 void xen_sysret64(void);
 void xen_adjust_exception_frame(void);
 
+extern int xen_panic_handler_init(void);
+
 #endif /* XEN_OPS_H */
diff --git a/arch/xtensa/Makefile b/arch/xtensa/Makefile
index 4caffac3ca2e..7608559de93a 100644
--- a/arch/xtensa/Makefile
+++ b/arch/xtensa/Makefile
@@ -35,6 +35,8 @@ KBUILD_CFLAGS += -ffreestanding
 
 KBUILD_CFLAGS += -pipe -mlongcalls
 
+KBUILD_CFLAGS += $(call cc-option,-mforce-no-pic,)
+
 vardirs := $(patsubst %,arch/xtensa/variants/%/,$(variant-y))
 plfdirs := $(patsubst %,arch/xtensa/platforms/%/,$(platform-y))
 
diff --git a/arch/xtensa/configs/iss_defconfig b/arch/xtensa/configs/iss_defconfig
index f19854035e61..7368164843b9 100644
--- a/arch/xtensa/configs/iss_defconfig
+++ b/arch/xtensa/configs/iss_defconfig
@@ -1,193 +1,214 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.11-rc2
-# Fri Feb 25 19:21:24 2005
+# Linux kernel version: 2.6.34-rc6
+# Tue Aug  3 00:10:54 2010
 #
-CONFIG_FRAME_POINTER=y
+# CONFIG_FRAME_POINTER is not set
+CONFIG_ZONE_DMA=y
 CONFIG_XTENSA=y
-# CONFIG_UID16 is not set
 CONFIG_RWSEM_XCHGADD_ALGORITHM=y
-CONFIG_HAVE_DEC_LOCK=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_GPIO=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_NO_IOPORT=y
+CONFIG_HZ=100
+CONFIG_GENERIC_TIME=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
 
 #
-# Code maturity level options
+# General setup
 #
 CONFIG_EXPERIMENTAL=y
-CONFIG_CLEAN_COMPILE=y
 CONFIG_BROKEN_ON_SMP=y
-
-#
-# General setup
-#
+CONFIG_INIT_ENV_ARG_LIMIT=32
 CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
 CONFIG_SWAP=y
 CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_POSIX_MQUEUE is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
-CONFIG_SYSCTL=y
+# CONFIG_TASKSTATS is not set
 # CONFIG_AUDIT is not set
-CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_HOTPLUG is not set
-# CONFIG_KOBJECT_UEVENT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_TINY_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
 # CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
 CONFIG_EMBEDDED=y
+CONFIG_SYSCTL_SYSCALL=y
 CONFIG_KALLSYMS=y
 # CONFIG_KALLSYMS_ALL is not set
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
+# CONFIG_HOTPLUG is not set
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
 CONFIG_EPOLL=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
-CONFIG_CC_ALIGN_FUNCTIONS=0
-CONFIG_CC_ALIGN_LABELS=0
-CONFIG_CC_ALIGN_LOOPS=0
-CONFIG_CC_ALIGN_JUMPS=0
-# CONFIG_TINY_SHMEM is not set
+CONFIG_AIO=y
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+CONFIG_COMPAT_BRK=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
 
 #
-# Loadable module support
+# GCOV-based kernel profiling
 #
+# CONFIG_SLOW_WORK is not set
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
 # CONFIG_MODULES is not set
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+CONFIG_BLK_DEV_BSG=y
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+CONFIG_DEFAULT_NOOP=y
+CONFIG_DEFAULT_IOSCHED="noop"
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+CONFIG_INLINE_SPIN_UNLOCK=y
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+CONFIG_INLINE_READ_UNLOCK=y
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+CONFIG_INLINE_READ_UNLOCK_IRQ=y
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+CONFIG_INLINE_WRITE_UNLOCK=y
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+# CONFIG_MUTEX_SPIN_ON_OWNER is not set
+# CONFIG_FREEZER is not set
+CONFIG_MMU=y
+# CONFIG_VARIANT_IRQ_SWITCH is not set
 
 #
 # Processor type and features
 #
 CONFIG_XTENSA_VARIANT_FSF=y
-CONFIG_MMU=y
+# CONFIG_XTENSA_VARIANT_DC232B is not set
+# CONFIG_XTENSA_VARIANT_S6000 is not set
 # CONFIG_XTENSA_UNALIGNED_USER is not set
 # CONFIG_PREEMPT is not set
 # CONFIG_MATH_EMULATION is not set
-# CONFIG_HIGHMEM is not set
-
-#
-# Platform options
-#
-CONFIG_XTENSA_PLATFORM_ISS=y
-# CONFIG_XTENSA_PLATFORM_XT2000 is not set
-# CONFIG_XTENSA_PLATFORM_ARUBA is not set
-# CONFIG_XTENSA_CALIBRATE_CCOUNT is not set
-CONFIG_XTENSA_CPU_CLOCK=10
-# CONFIG_GENERIC_CALIBRATE_DELAY is not set
-CONFIG_CMDLINE_BOOL=y
-CONFIG_CMDLINE="console=ttyS0,38400 eth0=tuntap,,tap0 ip=192.168.168.5:192.168.168.1 root=nfs nfsroot=192.168.168.1:/opt/montavista/pro/devkit/xtensa/linux_be/target"
+CONFIG_XTENSA_CALIBRATE_CCOUNT=y
 CONFIG_SERIAL_CONSOLE=y
 CONFIG_XTENSA_ISS_NETWORK=y
 
 #
 # Bus options
 #
+# CONFIG_PCI is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
 
 #
-# PCCARD (PCMCIA/CardBus) support
-#
-# CONFIG_PCCARD is not set
-
-#
-# PC-card bridges
-#
-
-#
-# PCI Hotplug Support
-#
-
+# Platform options
 #
-# Exectuable file formats
+CONFIG_XTENSA_PLATFORM_ISS=y
+# CONFIG_XTENSA_PLATFORM_XT2000 is not set
+# CONFIG_XTENSA_PLATFORM_S6105 is not set
+# CONFIG_GENERIC_CALIBRATE_DELAY is not set
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE="console=ttyS0,38400 eth0=tuntap,,tap0 ip=192.168.168.5:192.168.168.1 root=nfs nfsroot=192.168.168.1:/opt/montavista/pro/devkit/xtensa/linux_be/target"
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+
+#
+# Executable file formats
 #
 CONFIG_KCORE_ELF=y
 CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_HAVE_AOUT is not set
 # CONFIG_BINFMT_MISC is not set
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-# CONFIG_STANDALONE is not set
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-# CONFIG_FW_LOADER is not set
-# CONFIG_DEBUG_DRIVER is not set
-
-#
-# Memory Technology Devices (MTD)
-#
-# CONFIG_MTD is not set
-
-#
-# Parallel port support
-#
-# CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-
-#
-# Block devices
-#
-# CONFIG_BLK_DEV_FD is not set
-# CONFIG_BLK_DEV_COW_COMMON is not set
-# CONFIG_BLK_DEV_LOOP is not set
-# CONFIG_BLK_DEV_NBD is not set
-# CONFIG_BLK_DEV_RAM is not set
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_INITRAMFS_SOURCE=""
-# CONFIG_CDROM_PKTCDVD is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-# CONFIG_IOSCHED_AS is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-# CONFIG_ATA_OVER_ETH is not set
-
-#
-# ATA/ATAPI/MFM/RLL support
-#
-# CONFIG_IDE is not set
-
-#
-# SCSI device support
-#
-# CONFIG_SCSI is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
-# CONFIG_MD is not set
-
-#
-# Fusion MPT device support
-#
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# I2O device support
-#
-
-#
-# Networking support
-#
 CONFIG_NET=y
 
 #
 # Networking options
 #
 CONFIG_PACKET=y
-# CONFIG_PACKET_MMAP is not set
-# CONFIG_NETLINK_DEV is not set
 CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
 # CONFIG_NET_KEY is not set
 CONFIG_INET=y
 # CONFIG_IP_MULTICAST is not set
 # CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
 CONFIG_IP_PNP=y
 CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
@@ -199,21 +220,28 @@ CONFIG_IP_PNP_RARP=y
 # CONFIG_INET_AH is not set
 # CONFIG_INET_ESP is not set
 # CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
 # CONFIG_INET_TUNNEL is not set
-# CONFIG_IP_TCPDIAG is not set
-# CONFIG_IP_TCPDIAG_IPV6 is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_INET_LRO=y
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
 # CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
 # CONFIG_NETFILTER is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
+# CONFIG_IP_DCCP is not set
 # CONFIG_IP_SCTP is not set
-# CONFIG_SCTP_HMAC_NONE is not set
-# CONFIG_SCTP_HMAC_SHA1 is not set
-# CONFIG_SCTP_HMAC_MD5 is not set
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
 # CONFIG_VLAN_8021Q is not set
 # CONFIG_DECNET is not set
 # CONFIG_LLC2 is not set
@@ -221,77 +249,126 @@ CONFIG_IP_PNP_RARP=y
 # CONFIG_ATALK is not set
 # CONFIG_X25 is not set
 # CONFIG_LAPB is not set
-# CONFIG_NET_DIVERT is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
 # CONFIG_NET_SCHED is not set
-# CONFIG_NET_SCH_CLK_JIFFIES is not set
-# CONFIG_NET_SCH_CLK_GETTIMEOFDAY is not set
-# CONFIG_NET_SCH_CLK_CPU is not set
-# CONFIG_NET_CLS_ROUTE is not set
+# CONFIG_DCB is not set
 
 #
 # Network testing
 #
 # CONFIG_NET_PKTGEN is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
 # CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
-# CONFIG_NETDEVICES is not set
+# CONFIG_AF_RXRPC is not set
+CONFIG_WIRELESS=y
+# CONFIG_CFG80211 is not set
+# CONFIG_LIB80211 is not set
 
 #
-# ISDN subsystem
+# CFG80211 needs to be enabled for MAC80211
 #
-# CONFIG_ISDN is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+# CONFIG_STANDALONE is not set
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+# CONFIG_MTD is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
 
 #
-# Telephony Support
+# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
+#
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
 #
+# SCSI device support
+#
+CONFIG_SCSI_MOD=y
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_NETDEVICES is not set
+# CONFIG_ISDN is not set
 # CONFIG_PHONE is not set
 
 #
 # Input device support
 #
 CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+# CONFIG_INPUT_SPARSEKMAP is not set
 
 #
 # Userland interfaces
 #
 # CONFIG_INPUT_MOUSEDEV is not set
 # CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
 # CONFIG_INPUT_EVDEV is not set
 # CONFIG_INPUT_EVBUG is not set
 
 #
-# Input I/O drivers
-#
-# CONFIG_GAMEPORT is not set
-CONFIG_SOUND_GAMEPORT=y
-# CONFIG_SERIO is not set
-# CONFIG_SERIO_I8042 is not set
-
-#
 # Input Device Drivers
 #
 # CONFIG_INPUT_KEYBOARD is not set
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
 # CONFIG_INPUT_TOUCHSCREEN is not set
 # CONFIG_INPUT_MISC is not set
 
 #
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
 # Character devices
 #
 CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
 # CONFIG_SERIAL_NONSTANDARD is not set
 
 #
@@ -302,117 +379,159 @@ CONFIG_HW_CONSOLE=y
 #
 # Non-8250 serial port support
 #
+# CONFIG_SERIAL_TIMBERDALE is not set
 CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
 CONFIG_LEGACY_PTYS=y
 CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
 # CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-
-#
-# Watchdog Device Drivers
-#
-CONFIG_SOFT_WATCHDOG=y
+CONFIG_HW_RANDOM=y
+# CONFIG_HW_RANDOM_TIMERIOMEM is not set
 # CONFIG_RTC is not set
 # CONFIG_GEN_RTC is not set
-# CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
-
-#
-# Ftape, the floppy tape device driver
-#
-# CONFIG_DRM is not set
 # CONFIG_RAW_DRIVER is not set
-
-#
-# I2C support
-#
+# CONFIG_TCG_TPM is not set
 # CONFIG_I2C is not set
+# CONFIG_SPI is not set
 
 #
-# Dallas's 1-wire bus
+# PPS support
 #
+# CONFIG_PPS is not set
 # CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Native drivers
+#
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_SHT15 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_THERMAL is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
 
 #
-# Misc devices
+# Watchdog Device Drivers
 #
+CONFIG_SOFT_WATCHDOG=y
+CONFIG_SSB_POSSIBLE=y
 
 #
-# Multimedia devices
+# Sonics Silicon Backplane
 #
-# CONFIG_VIDEO_DEV is not set
+# CONFIG_SSB is not set
 
 #
-# Digital Video Broadcasting Devices
+# Multifunction device drivers
 #
-# CONFIG_DVB is not set
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
 
 #
 # Graphics support
 #
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
 # CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 
 #
-# Console display driver support
+# Display device support
 #
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_DUMMY_CONSOLE=y
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+# CONFIG_DISPLAY_SUPPORT is not set
 
 #
-# Sound
+# Console display driver support
 #
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
 # CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HIDRAW is not set
+# CONFIG_HID_PID is not set
 
 #
-# USB support
+# Special HID drivers
 #
+CONFIG_USB_SUPPORT=y
 # CONFIG_USB_ARCH_HAS_HCD is not set
 # CONFIG_USB_ARCH_HAS_OHCI is not set
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
 
 #
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
+# Enable Host or Gadget support to see Inventra options
 #
 
 #
-# USB Gadget Support
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
 #
 # CONFIG_USB_GADGET is not set
 
 #
-# MMC/SD Card support
+# OTG and related infrastructure
 #
 # CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
 
 #
-# InfiniBand support
+# TI VLYNQ
 #
-# CONFIG_INFINIBAND is not set
+# CONFIG_STAGING is not set
 
 #
 # File systems
 #
 # CONFIG_EXT2_FS is not set
 # CONFIG_EXT3_FS is not set
-# CONFIG_JBD is not set
+# CONFIG_EXT4_FS is not set
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
 # CONFIG_XFS_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
-# CONFIG_QUOTA is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
 # CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY is not set
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
 # CONFIG_AUTOFS_FS is not set
 # CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
 
 #
 # CD-ROM/DVD Filesystems
@@ -432,19 +551,14 @@ CONFIG_DUMMY_CONSOLE=y
 #
 CONFIG_PROC_FS=y
 CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
 CONFIG_SYSFS=y
-CONFIG_DEVFS_FS=y
-CONFIG_DEVFS_MOUNT=y
-# CONFIG_DEVFS_DEBUG is not set
-# CONFIG_DEVPTS_FS_XATTR is not set
 CONFIG_TMPFS=y
-# CONFIG_TMPFS_XATTR is not set
+# CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
-
-#
-# Miscellaneous filesystems
-#
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
 # CONFIG_ADFS_FS is not set
 # CONFIG_AFFS_FS is not set
 # CONFIG_HFS_FS is not set
@@ -452,29 +566,22 @@ CONFIG_RAMFS=y
 # CONFIG_BEFS_FS is not set
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set
+# CONFIG_LOGFS is not set
 # CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
 # CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-# CONFIG_NFS_V4 is not set
-CONFIG_NFS_DIRECTIO=y
+CONFIG_NETWORK_FILESYSTEMS=y
+# CONFIG_NFS_FS is not set
 # CONFIG_NFSD is not set
-CONFIG_ROOT_NFS=y
-CONFIG_LOCKD=y
-CONFIG_LOCKD_V4=y
-# CONFIG_EXPORTFS is not set
-CONFIG_SUNRPC=y
-# CONFIG_RPCSEC_GSS_KRB5 is not set
-# CONFIG_RPCSEC_GSS_SPKM3 is not set
 # CONFIG_SMB_FS is not set
+# CONFIG_CEPH_FS is not set
 # CONFIG_CIFS is not set
 # CONFIG_NCP_FS is not set
 # CONFIG_CODA_FS is not set
@@ -485,43 +592,175 @@ CONFIG_SUNRPC=y
 #
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
 # CONFIG_NLS is not set
+# CONFIG_DLM is not set
 
 #
 # Kernel hacking
 #
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DEBUG_STACKOVERFLOW is not set
-# CONFIG_DEBUG_SLAB is not set
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
 # CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
 # CONFIG_DEBUG_SPINLOCK is not set
-# CONFIG_DEBUG_PAGEALLOC is not set
-# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_MUTEXES is not set
 # CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-# CONFIG_KGDB is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+CONFIG_RCU_CPU_STALL_DETECTOR=y
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_PAGE_POISONING is not set
+# CONFIG_SAMPLES is not set
 
 #
 # Security options
 #
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_DEFAULT_SECURITY_SELINUX is not set
+# CONFIG_DEFAULT_SECURITY_SMACK is not set
+# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+# CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_MANAGER2 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_GHASH is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
 
 #
-# Cryptographic options
+# Compression
 #
-# CONFIG_CRYPTO is not set
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
 
 #
-# Hardware crypto devices
+# Random Number Generation
 #
+CONFIG_CRYPTO_ANSI_CPRNG=y
+CONFIG_CRYPTO_HW=y
+# CONFIG_BINARY_PRINTF is not set
 
 #
 # Library routines
 #
+CONFIG_GENERIC_FIND_LAST_BIT=y
 # CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
 # CONFIG_CRC32 is not set
+# CONFIG_CRC7 is not set
 # CONFIG_LIBCRC32C is not set
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/xtensa/include/asm/cacheflush.h b/arch/xtensa/include/asm/cacheflush.h
index a508f2f73bd7..376cd9d5f455 100644
--- a/arch/xtensa/include/asm/cacheflush.h
+++ b/arch/xtensa/include/asm/cacheflush.h
@@ -115,6 +115,7 @@ extern void flush_cache_page(struct vm_area_struct*, unsigned long, unsigned lon
 #define flush_cache_vmap(start,end)                     do { } while (0)
 #define flush_cache_vunmap(start,end)                   do { } while (0)
 
+#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
 #define flush_dcache_page(page)                         do { } while (0)
 
 #define flush_cache_page(vma,addr,pfn)                  do { } while (0)
diff --git a/arch/xtensa/include/asm/coprocessor.h b/arch/xtensa/include/asm/coprocessor.h
index 65a285d8d3fb..75c94a1658b0 100644
--- a/arch/xtensa/include/asm/coprocessor.h
+++ b/arch/xtensa/include/asm/coprocessor.h
@@ -13,6 +13,7 @@
 #define _XTENSA_COPROCESSOR_H
 
 #include <linux/stringify.h>
+#include <variant/core.h>
 #include <variant/tie.h>
 #include <asm/types.h>
 
diff --git a/arch/xtensa/include/asm/elf.h b/arch/xtensa/include/asm/elf.h
index 5eb6d695e987..6e65eadaae14 100644
--- a/arch/xtensa/include/asm/elf.h
+++ b/arch/xtensa/include/asm/elf.h
@@ -14,6 +14,7 @@
 #define _XTENSA_ELF_H
 
 #include <asm/ptrace.h>
+#include <asm/coprocessor.h>
 
 /* Xtensa processor ELF architecture-magic number */
 
diff --git a/arch/xtensa/include/asm/pgalloc.h b/arch/xtensa/include/asm/pgalloc.h
index 4f4a7987eded..40cf9bceda2c 100644
--- a/arch/xtensa/include/asm/pgalloc.h
+++ b/arch/xtensa/include/asm/pgalloc.h
@@ -14,6 +14,7 @@
 #ifdef __KERNEL__
 
 #include <linux/highmem.h>
+#include <linux/slab.h>
 
 /*
  * Allocating and freeing a pmd is trivial: the 1-entry pmd is
diff --git a/arch/xtensa/include/asm/processor.h b/arch/xtensa/include/asm/processor.h
index 0ea4937c0b61..3acb26e8dead 100644
--- a/arch/xtensa/include/asm/processor.h
+++ b/arch/xtensa/include/asm/processor.h
@@ -12,7 +12,6 @@
 #define _XTENSA_PROCESSOR_H
 
 #include <variant/core.h>
-#include <asm/coprocessor.h>
 #include <platform/hardware.h>
 
 #include <linux/compiler.h>
diff --git a/arch/xtensa/include/asm/ptrace.h b/arch/xtensa/include/asm/ptrace.h
index 3c549f798727..0d42c934b66f 100644
--- a/arch/xtensa/include/asm/ptrace.h
+++ b/arch/xtensa/include/asm/ptrace.h
@@ -77,6 +77,8 @@
 
 #ifndef __ASSEMBLY__
 
+#include <asm/coprocessor.h>
+
 /*
  * This struct defines the way the registers are stored on the
  * kernel stack during a system call or other kernel entry.
diff --git a/arch/xtensa/kernel/Makefile b/arch/xtensa/kernel/Makefile
index 6f56d95f2c1e..2d2728b3e862 100644
--- a/arch/xtensa/kernel/Makefile
+++ b/arch/xtensa/kernel/Makefile
@@ -23,8 +23,8 @@ obj-$(CONFIG_MODULES) += xtensa_ksyms.o module.o
 #
 # Replicate rules in scripts/Makefile.build
 
-sed-y = -e 's/(\(\.[a-z]*it\|\.ref\|\)\.text)/(\1.literal \1.text)/g'   \
-        -e 's/(\(\.text\.[a-z]*\))/(\1.literal \1)/g'
+sed-y = -e 's/\*(\(\.[a-z]*it\|\.ref\|\)\.text)/*(\1.literal \1.text)/g'    \
+        -e 's/\*(\(\.text\.[a-z]*\))/*(\1.literal \1)/g'
 
 quiet_cmd__cpp_lds_S = LDS     $@
       cmd__cpp_lds_S = $(CPP) $(cpp_flags) -P -C -Uxtensa -D__ASSEMBLY__ $< \
diff --git a/arch/xtensa/kernel/asm-offsets.c b/arch/xtensa/kernel/asm-offsets.c
index 070ff8af3a21..7dc3f9157185 100644
--- a/arch/xtensa/kernel/asm-offsets.c
+++ b/arch/xtensa/kernel/asm-offsets.c
@@ -13,6 +13,7 @@
  */
 
 #include <asm/processor.h>
+#include <asm/coprocessor.h>
 
 #include <linux/types.h>
 #include <linux/stddef.h>
diff --git a/arch/xtensa/kernel/entry.S b/arch/xtensa/kernel/entry.S
index 77fc9f6dc016..5fd01f6aaf37 100644
--- a/arch/xtensa/kernel/entry.S
+++ b/arch/xtensa/kernel/entry.S
@@ -16,6 +16,7 @@
 #include <linux/linkage.h>
 #include <asm/asm-offsets.h>
 #include <asm/processor.h>
+#include <asm/coprocessor.h>
 #include <asm/thread_info.h>
 #include <asm/uaccess.h>
 #include <asm/unistd.h>
diff --git a/arch/xtensa/kernel/head.S b/arch/xtensa/kernel/head.S
index d215adcfd4ea..3ef91a73652d 100644
--- a/arch/xtensa/kernel/head.S
+++ b/arch/xtensa/kernel/head.S
@@ -184,8 +184,8 @@ _startup:
          * Now clear the BSS segment.
          */
 
-        movi    a2, _bss_start  # start of BSS
-        movi    a3, _bss_end    # end of BSS
+        movi    a2, __bss_start # start of BSS
+        movi    a3, __bss_stop  # end of BSS
 
         __loopt a2, a3, a4, 2
         s32i    a0, a2, 0
diff --git a/arch/xtensa/platforms/iss/network.c b/arch/xtensa/platforms/iss/network.c
index 87e218f98ef4..f717e20d961b 100644
--- a/arch/xtensa/platforms/iss/network.c
+++ b/arch/xtensa/platforms/iss/network.c
@@ -623,6 +623,19 @@ static struct platform_driver iss_net_driver = {
 
 static int driver_registered;
 
+static const struct net_device_ops iss_netdev_ops = {
+        .ndo_open               = iss_net_open,
+        .ndo_stop               = iss_net_close,
+        .ndo_get_stats          = iss_net_get_stats,
+        .ndo_start_xmit         = iss_net_start_xmit,
+        .ndo_validate_addr      = eth_validate_addr,
+        .ndo_change_mtu         = iss_net_change_mtu,
+        .ndo_set_mac_address    = iss_net_set_mac,
+        //.ndo_do_ioctl         = iss_net_ioctl,
+        .ndo_tx_timeout         = iss_net_tx_timeout,
+        .ndo_set_multicast_list = iss_net_set_multicast_list,
+};
+
 static int iss_net_configure(int index, char *init)
 {
         struct net_device *dev;
@@ -686,15 +699,8 @@ static int iss_net_configure(int index, char *init)
          */
         snprintf(dev->name, sizeof dev->name, "eth%d", index);
 
+        dev->netdev_ops = &iss_netdev_ops;
         dev->mtu = lp->mtu;
-        dev->open = iss_net_open;
-        dev->hard_start_xmit = iss_net_start_xmit;
-        dev->stop = iss_net_close;
-        dev->get_stats = iss_net_get_stats;
-        dev->set_multicast_list = iss_net_set_multicast_list;
-        dev->tx_timeout = iss_net_tx_timeout;
-        dev->set_mac_address = iss_net_set_mac;
-        dev->change_mtu = iss_net_change_mtu;
         dev->watchdog_timeo = (HZ >> 1);
         dev->irq = -1;
 
diff --git a/drivers/block/virtio_blk.c b/drivers/block/virtio_blk.c
index 258bc2ae2885..23b7c48df843 100644
--- a/drivers/block/virtio_blk.c
+++ b/drivers/block/virtio_blk.c
@@ -225,16 +225,6 @@ static int virtblk_ioctl(struct block_device *bdev, fmode_t mode,
         struct gendisk *disk = bdev->bd_disk;
         struct virtio_blk *vblk = disk->private_data;
 
-        if (cmd == 0x56424944) { /* 'VBID' */
-                void __user *usr_data = (void __user *)data;
-                char id_str[VIRTIO_BLK_ID_BYTES];
-                int err;
-
-                err = virtblk_get_id(disk, id_str);
-                if (!err && copy_to_user(usr_data, id_str, VIRTIO_BLK_ID_BYTES))
-                        err = -EFAULT;
-                return err;
-        }
         /*
          * Only allow the generic SCSI ioctls if the host can support it.
          */
@@ -281,6 +271,27 @@ static int index_to_minor(int index)
         return index << PART_BITS;
 }
 
+static ssize_t virtblk_serial_show(struct device *dev,
+                                struct device_attribute *attr, char *buf)
+{
+        struct gendisk *disk = dev_to_disk(dev);
+        int err;
+
+        /* sysfs gives us a PAGE_SIZE buffer */
+        BUILD_BUG_ON(PAGE_SIZE < VIRTIO_BLK_ID_BYTES);
+
+        buf[VIRTIO_BLK_ID_BYTES] = '\0';
+        err = virtblk_get_id(disk, buf);
+        if (!err)
+                return strlen(buf);
+
+        if (err == -EIO) /* Unsupported? Make it empty. */
+                return 0;
+
+        return err;
+}
+DEVICE_ATTR(serial, S_IRUGO, virtblk_serial_show, NULL);
+
 static int __devinit virtblk_probe(struct virtio_device *vdev)
 {
         struct virtio_blk *vblk;
@@ -366,12 +377,32 @@ static int __devinit virtblk_probe(struct virtio_device *vdev)
         vblk->disk->driverfs_dev = &vdev->dev;
         index++;
 
-        /* If barriers are supported, tell block layer that queue is ordered */
-        if (virtio_has_feature(vdev, VIRTIO_BLK_F_FLUSH))
+        if (virtio_has_feature(vdev, VIRTIO_BLK_F_FLUSH)) {
+                /*
+                 * If the FLUSH feature is supported we do have support for
+                 * flushing a volatile write cache on the host.  Use that
+                 * to implement write barrier support.
+                 */
                 blk_queue_ordered(q, QUEUE_ORDERED_DRAIN_FLUSH,
                                   virtblk_prepare_flush);
-        else if (virtio_has_feature(vdev, VIRTIO_BLK_F_BARRIER))
+        } else if (virtio_has_feature(vdev, VIRTIO_BLK_F_BARRIER)) {
+                /*
+                 * If the BARRIER feature is supported the host expects us
+                 * to order request by tags.  This implies there is not
+                 * volatile write cache on the host, and that the host
+                 * never re-orders outstanding I/O.  This feature is not
+                 * useful for real life scenarious and deprecated.
+                 */
                 blk_queue_ordered(q, QUEUE_ORDERED_TAG, NULL);
+        } else {
+                /*
+                 * If the FLUSH feature is not supported we must assume that
+                 * the host does not perform any kind of volatile write
+                 * caching. We still need to drain the queue to provider
+                 * proper barrier semantics.
+                 */
+                blk_queue_ordered(q, QUEUE_ORDERED_DRAIN, NULL);
+        }
 
         /* If disk is read-only in the host, the guest should obey */
         if (virtio_has_feature(vdev, VIRTIO_BLK_F_RO))
@@ -445,8 +476,15 @@ static int __devinit virtblk_probe(struct virtio_device *vdev)
 
 
         add_disk(vblk->disk);
+        err = device_create_file(disk_to_dev(vblk->disk), &dev_attr_serial);
+        if (err)
+                goto out_del_disk;
+
         return 0;
 
+out_del_disk:
+        del_gendisk(vblk->disk);
+        blk_cleanup_queue(vblk->disk->queue);
 out_put_disk:
         put_disk(vblk->disk);
 out_mempool:
diff --git a/drivers/block/xen-blkfront.c b/drivers/block/xen-blkfront.c
index 82ed403147c0..f63ac3d1f8a4 100644
--- a/drivers/block/xen-blkfront.c
+++ b/drivers/block/xen-blkfront.c
@@ -48,6 +48,7 @@
 #include <xen/grant_table.h>
 #include <xen/events.h>
 #include <xen/page.h>
+#include <xen/platform_pci.h>
 
 #include <xen/interface/grant_table.h>
 #include <xen/interface/io/blkif.h>
@@ -737,6 +738,35 @@ static int blkfront_probe(struct xenbus_device *dev,
                 }
         }
 
+        if (xen_hvm_domain()) {
+                char *type;
+                int len;
+                /* no unplug has been done: do not hook devices != xen vbds */
+                if (xen_platform_pci_unplug & XEN_UNPLUG_IGNORE) {
+                        int major;
+
+                        if (!VDEV_IS_EXTENDED(vdevice))
+                                major = BLKIF_MAJOR(vdevice);
+                        else
+                                major = XENVBD_MAJOR;
+
+                        if (major != XENVBD_MAJOR) {
+                                printk(KERN_INFO
+                                                "%s: HVM does not support vbd %d as xen block device\n",
+                                                __FUNCTION__, vdevice);
+                                return -ENODEV;
+                        }
+                }
+                /* do not create a PV cdrom device if we are an HVM guest */
+                type = xenbus_read(XBT_NIL, dev->nodename, "device-type", &len);
+                if (IS_ERR(type))
+                        return -ENODEV;
+                if (strncmp(type, "cdrom", 5) == 0) {
+                        kfree(type);
+                        return -ENODEV;
+                }
+                kfree(type);
+        }
         info = kzalloc(sizeof(*info), GFP_KERNEL);
         if (!info) {
                 xenbus_dev_fatal(dev, -ENOMEM, "allocating info structure");
diff --git a/drivers/char/hvc_console.c b/drivers/char/hvc_console.c
index 35cca4c7fb18..fa27d1676ee5 100644
--- a/drivers/char/hvc_console.c
+++ b/drivers/char/hvc_console.c
@@ -194,7 +194,7 @@ static int __init hvc_console_setup(struct console *co, char *options)
         return 0;
 }
 
-static struct console hvc_con_driver = {
+static struct console hvc_console = {
         .name           = "hvc",
         .write          = hvc_console_print,
         .device         = hvc_console_device,
@@ -220,7 +220,7 @@ static struct console hvc_con_driver = {
  */
 static int __init hvc_console_init(void)
 {
-        register_console(&hvc_con_driver);
+        register_console(&hvc_console);
         return 0;
 }
 console_initcall(hvc_console_init);
@@ -276,8 +276,8 @@ int hvc_instantiate(uint32_t vtermno, int index, const struct hv_ops *ops)
          * now (setup won't fail at this point).  It's ok to just
          * call register again if previously .setup failed.
          */
-        if (index == hvc_con_driver.index)
-                register_console(&hvc_con_driver);
+        if (index == hvc_console.index)
+                register_console(&hvc_console);
 
         return 0;
 }
@@ -641,7 +641,7 @@ int hvc_poll(struct hvc_struct *hp)
                 }
                 for (i = 0; i < n; ++i) {
 #ifdef CONFIG_MAGIC_SYSRQ
-                        if (hp->index == hvc_con_driver.index) {
+                        if (hp->index == hvc_console.index) {
                                 /* Handle the SysRq Hack */
                                 /* XXX should support a sequence */
                                 if (buf[i] == '\x0f') { /* ^O */
@@ -909,7 +909,7 @@ static void __exit hvc_exit(void)
                 tty_unregister_driver(hvc_driver);
                 /* return tty_struct instances allocated in hvc_init(). */
                 put_tty_driver(hvc_driver);
-                unregister_console(&hvc_con_driver);
+                unregister_console(&hvc_console);
         }
 }
 module_exit(hvc_exit);
diff --git a/drivers/char/hvsi.c b/drivers/char/hvsi.c
index d4b14ff1c4c1..1f4b6de65a2d 100644
--- a/drivers/char/hvsi.c
+++ b/drivers/char/hvsi.c
@@ -1255,7 +1255,7 @@ static int __init hvsi_console_setup(struct console *console, char *options)
         return 0;
 }
 
-static struct console hvsi_con_driver = {
+static struct console hvsi_console = {
         .name           = "hvsi",
         .write          = hvsi_console_print,
         .device         = hvsi_console_device,
@@ -1308,7 +1308,7 @@ static int __init hvsi_console_init(void)
         }
 
         if (hvsi_count)
-                register_console(&hvsi_con_driver);
+                register_console(&hvsi_console);
         return 0;
 }
 console_initcall(hvsi_console_init);
diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
index e19cf8eb6ccf..c57e530d07c7 100644
--- a/drivers/hwmon/Kconfig
+++ b/drivers/hwmon/Kconfig
@@ -446,6 +446,16 @@ config SENSORS_IT87
           This driver can also be built as a module.  If so, the module
           will be called it87.
 
+config SENSORS_JZ4740
+        tristate "Ingenic JZ4740 SoC ADC driver"
+        depends on MACH_JZ4740 && MFD_JZ4740_ADC
+        help
+          If you say yes here you get support for reading adc values from the ADCIN
+          pin on Ingenic JZ4740 SoC based boards.
+
+          This driver can also be build as a module. If so, the module will be
+          called jz4740-hwmon.
+
 config SENSORS_LM63
         tristate "National Semiconductor LM63 and LM64"
         depends on I2C
diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
index 2138ceb1a713..c5057745b068 100644
--- a/drivers/hwmon/Makefile
+++ b/drivers/hwmon/Makefile
@@ -55,6 +55,7 @@ obj-$(CONFIG_SENSORS_I5K_AMB)	+= i5k_amb.o
 obj-$(CONFIG_SENSORS_IBMAEM)    += ibmaem.o
 obj-$(CONFIG_SENSORS_IBMPEX)    += ibmpex.o
 obj-$(CONFIG_SENSORS_IT87)      += it87.o
+obj-$(CONFIG_SENSORS_JZ4740)    += jz4740-hwmon.o
 obj-$(CONFIG_SENSORS_K8TEMP)    += k8temp.o
 obj-$(CONFIG_SENSORS_K10TEMP)   += k10temp.o
 obj-$(CONFIG_SENSORS_LIS3LV02D) += lis3lv02d.o hp_accel.o
diff --git a/drivers/hwmon/jz4740-hwmon.c b/drivers/hwmon/jz4740-hwmon.c
new file mode 100644
index 000000000000..1c8b3d9e2051
--- /dev/null
+++ b/drivers/hwmon/jz4740-hwmon.c
@@ -0,0 +1,230 @@
+/*
+ * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
+ * JZ4740 SoC HWMON driver
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under  the terms of the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#include <linux/err.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include <linux/completion.h>
+#include <linux/mfd/core.h>
+
+#include <linux/hwmon.h>
+
+struct jz4740_hwmon {
+        struct resource *mem;
+        void __iomem *base;
+
+        int irq;
+
+        struct mfd_cell *cell;
+        struct device *hwmon;
+
+        struct completion read_completion;
+
+        struct mutex lock;
+};
+
+static ssize_t jz4740_hwmon_show_name(struct device *dev,
+        struct device_attribute *dev_attr, char *buf)
+{
+        return sprintf(buf, "jz4740\n");
+}
+
+static irqreturn_t jz4740_hwmon_irq(int irq, void *data)
+{
+        struct jz4740_hwmon *hwmon = data;
+
+        complete(&hwmon->read_completion);
+        return IRQ_HANDLED;
+}
+
+static ssize_t jz4740_hwmon_read_adcin(struct device *dev,
+        struct device_attribute *dev_attr, char *buf)
+{
+        struct jz4740_hwmon *hwmon = dev_get_drvdata(dev);
+        struct completion *completion = &hwmon->read_completion;
+        unsigned long t;
+        unsigned long val;
+        int ret;
+
+        mutex_lock(&hwmon->lock);
+
+        INIT_COMPLETION(*completion);
+
+        enable_irq(hwmon->irq);
+        hwmon->cell->enable(to_platform_device(dev));
+
+        t = wait_for_completion_interruptible_timeout(completion, HZ);
+
+        if (t > 0) {
+                val = readw(hwmon->base) & 0xfff;
+                val = (val * 3300) >> 12;
+                ret = sprintf(buf, "%lu\n", val);
+        } else {
+                ret = t ? t : -ETIMEDOUT;
+        }
+
+        hwmon->cell->disable(to_platform_device(dev));
+        disable_irq(hwmon->irq);
+
+        mutex_unlock(&hwmon->lock);
+
+        return ret;
+}
+
+static DEVICE_ATTR(name, S_IRUGO, jz4740_hwmon_show_name, NULL);
+static DEVICE_ATTR(in0_input, S_IRUGO, jz4740_hwmon_read_adcin, NULL);
+
+static struct attribute *jz4740_hwmon_attributes[] = {
+        &dev_attr_name.attr,
+        &dev_attr_in0_input.attr,
+        NULL
+};
+
+static const struct attribute_group jz4740_hwmon_attr_group = {
+        .attrs = jz4740_hwmon_attributes,
+};
+
+static int __devinit jz4740_hwmon_probe(struct platform_device *pdev)
+{
+        int ret;
+        struct jz4740_hwmon *hwmon;
+
+        hwmon = kmalloc(sizeof(*hwmon), GFP_KERNEL);
+        if (!hwmon) {
+                dev_err(&pdev->dev, "Failed to allocate driver structure\n");
+                return -ENOMEM;
+        }
+
+        hwmon->cell = pdev->dev.platform_data;
+
+        hwmon->irq = platform_get_irq(pdev, 0);
+        if (hwmon->irq < 0) {
+                ret = hwmon->irq;
+                dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret);
+                goto err_free;
+        }
+
+        hwmon->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!hwmon->mem) {
+                ret = -ENOENT;
+                dev_err(&pdev->dev, "Failed to get platform mmio resource\n");
+                goto err_free;
+        }
+
+        hwmon->mem = request_mem_region(hwmon->mem->start,
+                        resource_size(hwmon->mem), pdev->name);
+        if (!hwmon->mem) {
+                ret = -EBUSY;
+                dev_err(&pdev->dev, "Failed to request mmio memory region\n");
+                goto err_free;
+        }
+
+        hwmon->base = ioremap_nocache(hwmon->mem->start,
+                        resource_size(hwmon->mem));
+        if (!hwmon->base) {
+                ret = -EBUSY;
+                dev_err(&pdev->dev, "Failed to ioremap mmio memory\n");
+                goto err_release_mem_region;
+        }
+
+        init_completion(&hwmon->read_completion);
+        mutex_init(&hwmon->lock);
+
+        platform_set_drvdata(pdev, hwmon);
+
+        ret = request_irq(hwmon->irq, jz4740_hwmon_irq, 0, pdev->name, hwmon);
+        if (ret) {
+                dev_err(&pdev->dev, "Failed to request irq: %d\n", ret);
+                goto err_iounmap;
+        }
+        disable_irq(hwmon->irq);
+
+        ret = sysfs_create_group(&pdev->dev.kobj, &jz4740_hwmon_attr_group);
+        if (ret) {
+                dev_err(&pdev->dev, "Failed to create sysfs group: %d\n", ret);
+                goto err_free_irq;
+        }
+
+        hwmon->hwmon = hwmon_device_register(&pdev->dev);
+        if (IS_ERR(hwmon->hwmon)) {
+                ret = PTR_ERR(hwmon->hwmon);
+                goto err_remove_file;
+        }
+
+        return 0;
+
+err_remove_file:
+        sysfs_remove_group(&pdev->dev.kobj, &jz4740_hwmon_attr_group);
+err_free_irq:
+        free_irq(hwmon->irq, hwmon);
+err_iounmap:
+        platform_set_drvdata(pdev, NULL);
+        iounmap(hwmon->base);
+err_release_mem_region:
+        release_mem_region(hwmon->mem->start, resource_size(hwmon->mem));
+err_free:
+        kfree(hwmon);
+
+        return ret;
+}
+
+static int __devexit jz4740_hwmon_remove(struct platform_device *pdev)
+{
+        struct jz4740_hwmon *hwmon = platform_get_drvdata(pdev);
+
+        hwmon_device_unregister(hwmon->hwmon);
+        sysfs_remove_group(&pdev->dev.kobj, &jz4740_hwmon_attr_group);
+
+        free_irq(hwmon->irq, hwmon);
+
+        iounmap(hwmon->base);
+        release_mem_region(hwmon->mem->start, resource_size(hwmon->mem));
+
+        platform_set_drvdata(pdev, NULL);
+        kfree(hwmon);
+
+        return 0;
+}
+
+struct platform_driver jz4740_hwmon_driver = {
+        .probe  = jz4740_hwmon_probe,
+        .remove = __devexit_p(jz4740_hwmon_remove),
+        .driver = {
+                .name = "jz4740-hwmon",
+                .owner = THIS_MODULE,
+        },
+};
+
+static int __init jz4740_hwmon_init(void)
+{
+        return platform_driver_register(&jz4740_hwmon_driver);
+}
+module_init(jz4740_hwmon_init);
+
+static void __exit jz4740_hwmon_exit(void)
+{
+        platform_driver_unregister(&jz4740_hwmon_driver);
+}
+module_exit(jz4740_hwmon_exit);
+
+MODULE_DESCRIPTION("JZ4740 SoC HWMON driver");
+MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:jz4740-hwmon");
diff --git a/drivers/i2c/busses/i2c-mpc.c b/drivers/i2c/busses/i2c-mpc.c
index df00eb1f11f9..54247d475fc3 100644
--- a/drivers/i2c/busses/i2c-mpc.c
+++ b/drivers/i2c/busses/i2c-mpc.c
@@ -63,6 +63,7 @@ struct mpc_i2c {
         wait_queue_head_t queue;
         struct i2c_adapter adap;
         int irq;
+        u32 real_clk;
 };
 
 struct mpc_i2c_divider {
@@ -96,20 +97,23 @@ static irqreturn_t mpc_i2c_isr(int irq, void *dev_id)
 /* Sometimes 9th clock pulse isn't generated, and slave doesn't release
  * the bus, because it wants to send ACK.
  * Following sequence of enabling/disabling and sending start/stop generates
- * the pulse, so it's all OK.
+ * the 9 pulses, so it's all OK.
  */
 static void mpc_i2c_fixup(struct mpc_i2c *i2c)
 {
-        writeccr(i2c, 0);
-        udelay(30);
-        writeccr(i2c, CCR_MEN);
-        udelay(30);
-        writeccr(i2c, CCR_MSTA | CCR_MTX);
-        udelay(30);
-        writeccr(i2c, CCR_MSTA | CCR_MTX | CCR_MEN);
-        udelay(30);
-        writeccr(i2c, CCR_MEN);
-        udelay(30);
+        int k;
+        u32 delay_val = 1000000 / i2c->real_clk + 1;
+
+        if (delay_val < 2)
+                delay_val = 2;
+
+        for (k = 9; k; k--) {
+                writeccr(i2c, 0);
+                writeccr(i2c, CCR_MSTA | CCR_MTX | CCR_MEN);
+                udelay(delay_val);
+                writeccr(i2c, CCR_MEN);
+                udelay(delay_val << 1);
+        }
 }
 
 static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout, int writing)
@@ -190,15 +194,18 @@ static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] __devinitconst = {
 };
 
 static int __devinit mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock,
-                                          int prescaler)
+                                          int prescaler, u32 *real_clk)
 {
         const struct mpc_i2c_divider *div = NULL;
         unsigned int pvr = mfspr(SPRN_PVR);
         u32 divider;
         int i;
 
-        if (clock == MPC_I2C_CLOCK_LEGACY)
+        if (clock == MPC_I2C_CLOCK_LEGACY) {
+                /* see below - default fdr = 0x3f -> div = 2048 */
+                *real_clk = mpc5xxx_get_bus_frequency(node) / 2048;
                 return -EINVAL;
+        }
 
         /* Determine divider value */
         divider = mpc5xxx_get_bus_frequency(node) / clock;
@@ -216,7 +223,8 @@ static int __devinit mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock,
                         break;
         }
 
-        return div ? (int)div->fdr : -EINVAL;
+        *real_clk = mpc5xxx_get_bus_frequency(node) / div->divider;
+        return (int)div->fdr;
 }
 
 static void __devinit mpc_i2c_setup_52xx(struct device_node *node,
@@ -231,13 +239,14 @@ static void __devinit mpc_i2c_setup_52xx(struct device_node *node,
                 return;
         }
 
-        ret = mpc_i2c_get_fdr_52xx(node, clock, prescaler);
+        ret = mpc_i2c_get_fdr_52xx(node, clock, prescaler, &i2c->real_clk);
         fdr = (ret >= 0) ? ret : 0x3f; /* backward compatibility */
 
         writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);
 
         if (ret >= 0)
-                dev_info(i2c->dev, "clock %d Hz (fdr=%d)\n", clock, fdr);
+                dev_info(i2c->dev, "clock %u Hz (fdr=%d)\n", i2c->real_clk,
+                         fdr);
 }
 #else /* !(CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x) */
 static void __devinit mpc_i2c_setup_52xx(struct device_node *node,
@@ -334,14 +343,17 @@ static u32 __devinit mpc_i2c_get_sec_cfg_8xxx(void)
 }
 
 static int __devinit mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock,
-                                          u32 prescaler)
+                                          u32 prescaler, u32 *real_clk)
 {
         const struct mpc_i2c_divider *div = NULL;
         u32 divider;
         int i;
 
-        if (clock == MPC_I2C_CLOCK_LEGACY)
+        if (clock == MPC_I2C_CLOCK_LEGACY) {
+                /* see below - default fdr = 0x1031 -> div = 16 * 3072 */
+                *real_clk = fsl_get_sys_freq() / prescaler / (16 * 3072);
                 return -EINVAL;
+        }
 
         /* Determine proper divider value */
         if (of_device_is_compatible(node, "fsl,mpc8544-i2c"))
@@ -364,6 +376,7 @@ static int __devinit mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock,
                         break;
         }
 
+        *real_clk = fsl_get_sys_freq() / prescaler / div->divider;
         return div ? (int)div->fdr : -EINVAL;
 }
 
@@ -380,7 +393,7 @@ static void __devinit mpc_i2c_setup_8xxx(struct device_node *node,
                 return;
         }
 
-        ret = mpc_i2c_get_fdr_8xxx(node, clock, prescaler);
+        ret = mpc_i2c_get_fdr_8xxx(node, clock, prescaler, &i2c->real_clk);
         fdr = (ret >= 0) ? ret : 0x1031; /* backward compatibility */
 
         writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);
@@ -388,7 +401,7 @@ static void __devinit mpc_i2c_setup_8xxx(struct device_node *node,
 
         if (ret >= 0)
                 dev_info(i2c->dev, "clock %d Hz (dfsrr=%d fdr=%d)\n",
-                         clock, fdr >> 8, fdr & 0xff);
+                         i2c->real_clk, fdr >> 8, fdr & 0xff);
 }
 
 #else /* !CONFIG_FSL_SOC */
@@ -500,10 +513,14 @@ static int mpc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
                         return -EINTR;
                 }
                 if (time_after(jiffies, orig_jiffies + HZ)) {
+                        u8 status = readb(i2c->base + MPC_I2C_SR);
+
                         dev_dbg(i2c->dev, "timeout\n");
-                        if (readb(i2c->base + MPC_I2C_SR) ==
-                            (CSR_MCF | CSR_MBB | CSR_RXAK))
+                        if ((status & (CSR_MCF | CSR_MBB | CSR_RXAK)) != 0) {
+                                writeb(status & ~CSR_MAL,
+                                       i2c->base + MPC_I2C_SR);
                                 mpc_i2c_fixup(i2c);
+                        }
                         return -EIO;
                 }
                 schedule();
@@ -595,6 +612,14 @@ static int __devinit fsl_i2c_probe(struct of_device *op,
                         mpc_i2c_setup_8xxx(op->dev.of_node, i2c, clock, 0);
         }
 
+        prop = of_get_property(op->dev.of_node, "fsl,timeout", &plen);
+        if (prop && plen == sizeof(u32)) {
+                mpc_ops.timeout = *prop * HZ / 1000000;
+                if (mpc_ops.timeout < 5)
+                        mpc_ops.timeout = 5;
+        }
+        dev_info(i2c->dev, "timeout %u us\n", mpc_ops.timeout * 1000000 / HZ);
+
         dev_set_drvdata(&op->dev, i2c);
 
         i2c->adap = mpc_ops;
diff --git a/drivers/input/serio/i8042-io.h b/drivers/input/serio/i8042-io.h
index 847f4aad7ed5..5d48bb66aa73 100644
--- a/drivers/input/serio/i8042-io.h
+++ b/drivers/input/serio/i8042-io.h
@@ -27,6 +27,11 @@
 #include <asm/irq.h>
 #elif defined(CONFIG_SH_CAYMAN)
 #include <asm/irq.h>
+#elif defined(CONFIG_PPC)
+extern int of_i8042_kbd_irq;
+extern int of_i8042_aux_irq;
+# define I8042_KBD_IRQ  of_i8042_kbd_irq
+# define I8042_AUX_IRQ  of_i8042_aux_irq
 #else
 # define I8042_KBD_IRQ  1
 # define I8042_AUX_IRQ  12
diff --git a/drivers/input/xen-kbdfront.c b/drivers/input/xen-kbdfront.c
index e14081675bb2..ebb11907d402 100644
--- a/drivers/input/xen-kbdfront.c
+++ b/drivers/input/xen-kbdfront.c
@@ -339,7 +339,7 @@ static struct xenbus_driver xenkbd_driver = {
 
 static int __init xenkbd_init(void)
 {
-        if (!xen_domain())
+        if (!xen_pv_domain())
                 return -ENODEV;
 
         /* Nothing to do if running in dom0. */
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index f06d06e7fdfa..d25e22cee4c4 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -432,3 +432,12 @@ config MMC_SH_MMCIF
           This selects the MMC Host Interface controler (MMCIF).
 
           This driver supports MMCIF in sh7724/sh7757/sh7372.
+
+config MMC_JZ4740
+        tristate "JZ4740 SD/Multimedia Card Interface support"
+        depends on MACH_JZ4740
+        help
+          This selects support for the SD/MMC controller on Ingenic JZ4740
+          SoCs.
+          If you have a board based on such a SoC and with a SD/MMC slot,
+          say Y or M here.
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index e30c2ee48894..f4e53c98d944 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_MMC_CB710)	+= cb710-mmc.o
 obj-$(CONFIG_MMC_VIA_SDMMC)     += via-sdmmc.o
 obj-$(CONFIG_SDH_BFIN)          += bfin_sdh.o
 obj-$(CONFIG_MMC_SH_MMCIF)      += sh_mmcif.o
+obj-$(CONFIG_MMC_JZ4740)        += jz4740_mmc.o
 
 obj-$(CONFIG_MMC_SDHCI_OF)      += sdhci-of.o
 sdhci-of-y                              := sdhci-of-core.o
diff --git a/drivers/mmc/host/jz4740_mmc.c b/drivers/mmc/host/jz4740_mmc.c
new file mode 100644
index 000000000000..ad4f9870e3ca
--- /dev/null
+++ b/drivers/mmc/host/jz4740_mmc.c
@@ -0,0 +1,1029 @@
+/*
+ *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
+ *  JZ4740 SD/MMC controller driver
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#include <linux/mmc/host.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/scatterlist.h>
+#include <linux/clk.h>
+
+#include <linux/bitops.h>
+#include <linux/gpio.h>
+#include <asm/mach-jz4740/gpio.h>
+#include <asm/cacheflush.h>
+#include <linux/dma-mapping.h>
+
+#include <asm/mach-jz4740/jz4740_mmc.h>
+
+#define JZ_REG_MMC_STRPCL       0x00
+#define JZ_REG_MMC_STATUS       0x04
+#define JZ_REG_MMC_CLKRT        0x08
+#define JZ_REG_MMC_CMDAT        0x0C
+#define JZ_REG_MMC_RESTO        0x10
+#define JZ_REG_MMC_RDTO         0x14
+#define JZ_REG_MMC_BLKLEN       0x18
+#define JZ_REG_MMC_NOB          0x1C
+#define JZ_REG_MMC_SNOB         0x20
+#define JZ_REG_MMC_IMASK        0x24
+#define JZ_REG_MMC_IREG         0x28
+#define JZ_REG_MMC_CMD          0x2C
+#define JZ_REG_MMC_ARG          0x30
+#define JZ_REG_MMC_RESP_FIFO    0x34
+#define JZ_REG_MMC_RXFIFO       0x38
+#define JZ_REG_MMC_TXFIFO       0x3C
+
+#define JZ_MMC_STRPCL_EXIT_MULTIPLE BIT(7)
+#define JZ_MMC_STRPCL_EXIT_TRANSFER BIT(6)
+#define JZ_MMC_STRPCL_START_READWAIT BIT(5)
+#define JZ_MMC_STRPCL_STOP_READWAIT BIT(4)
+#define JZ_MMC_STRPCL_RESET BIT(3)
+#define JZ_MMC_STRPCL_START_OP BIT(2)
+#define JZ_MMC_STRPCL_CLOCK_CONTROL (BIT(1) | BIT(0))
+#define JZ_MMC_STRPCL_CLOCK_STOP BIT(0)
+#define JZ_MMC_STRPCL_CLOCK_START BIT(1)
+
+
+#define JZ_MMC_STATUS_IS_RESETTING BIT(15)
+#define JZ_MMC_STATUS_SDIO_INT_ACTIVE BIT(14)
+#define JZ_MMC_STATUS_PRG_DONE BIT(13)
+#define JZ_MMC_STATUS_DATA_TRAN_DONE BIT(12)
+#define JZ_MMC_STATUS_END_CMD_RES BIT(11)
+#define JZ_MMC_STATUS_DATA_FIFO_AFULL BIT(10)
+#define JZ_MMC_STATUS_IS_READWAIT BIT(9)
+#define JZ_MMC_STATUS_CLK_EN BIT(8)
+#define JZ_MMC_STATUS_DATA_FIFO_FULL BIT(7)
+#define JZ_MMC_STATUS_DATA_FIFO_EMPTY BIT(6)
+#define JZ_MMC_STATUS_CRC_RES_ERR BIT(5)
+#define JZ_MMC_STATUS_CRC_READ_ERROR BIT(4)
+#define JZ_MMC_STATUS_TIMEOUT_WRITE BIT(3)
+#define JZ_MMC_STATUS_CRC_WRITE_ERROR BIT(2)
+#define JZ_MMC_STATUS_TIMEOUT_RES BIT(1)
+#define JZ_MMC_STATUS_TIMEOUT_READ BIT(0)
+
+#define JZ_MMC_STATUS_READ_ERROR_MASK (BIT(4) | BIT(0))
+#define JZ_MMC_STATUS_WRITE_ERROR_MASK (BIT(3) | BIT(2))
+
+
+#define JZ_MMC_CMDAT_IO_ABORT BIT(11)
+#define JZ_MMC_CMDAT_BUS_WIDTH_4BIT BIT(10)
+#define JZ_MMC_CMDAT_DMA_EN BIT(8)
+#define JZ_MMC_CMDAT_INIT BIT(7)
+#define JZ_MMC_CMDAT_BUSY BIT(6)
+#define JZ_MMC_CMDAT_STREAM BIT(5)
+#define JZ_MMC_CMDAT_WRITE BIT(4)
+#define JZ_MMC_CMDAT_DATA_EN BIT(3)
+#define JZ_MMC_CMDAT_RESPONSE_FORMAT (BIT(2) | BIT(1) | BIT(0))
+#define JZ_MMC_CMDAT_RSP_R1 1
+#define JZ_MMC_CMDAT_RSP_R2 2
+#define JZ_MMC_CMDAT_RSP_R3 3
+
+#define JZ_MMC_IRQ_SDIO BIT(7)
+#define JZ_MMC_IRQ_TXFIFO_WR_REQ BIT(6)
+#define JZ_MMC_IRQ_RXFIFO_RD_REQ BIT(5)
+#define JZ_MMC_IRQ_END_CMD_RES BIT(2)
+#define JZ_MMC_IRQ_PRG_DONE BIT(1)
+#define JZ_MMC_IRQ_DATA_TRAN_DONE BIT(0)
+
+
+#define JZ_MMC_CLK_RATE 24000000
+
+enum jz4740_mmc_state {
+        JZ4740_MMC_STATE_READ_RESPONSE,
+        JZ4740_MMC_STATE_TRANSFER_DATA,
+        JZ4740_MMC_STATE_SEND_STOP,
+        JZ4740_MMC_STATE_DONE,
+};
+
+struct jz4740_mmc_host {
+        struct mmc_host *mmc;
+        struct platform_device *pdev;
+        struct jz4740_mmc_platform_data *pdata;
+        struct clk *clk;
+
+        int irq;
+        int card_detect_irq;
+
+        struct resource *mem;
+        void __iomem *base;
+        struct mmc_request *req;
+        struct mmc_command *cmd;
+
+        unsigned long waiting;
+
+        uint32_t cmdat;
+
+        uint16_t irq_mask;
+
+        spinlock_t lock;
+
+        struct timer_list timeout_timer;
+        struct sg_mapping_iter miter;
+        enum jz4740_mmc_state state;
+};
+
+static void jz4740_mmc_set_irq_enabled(struct jz4740_mmc_host *host,
+        unsigned int irq, bool enabled)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&host->lock, flags);
+        if (enabled)
+                host->irq_mask &= ~irq;
+        else
+                host->irq_mask |= irq;
+        spin_unlock_irqrestore(&host->lock, flags);
+
+        writew(host->irq_mask, host->base + JZ_REG_MMC_IMASK);
+}
+
+static void jz4740_mmc_clock_enable(struct jz4740_mmc_host *host,
+        bool start_transfer)
+{
+        uint16_t val = JZ_MMC_STRPCL_CLOCK_START;
+
+        if (start_transfer)
+                val |= JZ_MMC_STRPCL_START_OP;
+
+        writew(val, host->base + JZ_REG_MMC_STRPCL);
+}
+
+static void jz4740_mmc_clock_disable(struct jz4740_mmc_host *host)
+{
+        uint32_t status;
+        unsigned int timeout = 1000;
+
+        writew(JZ_MMC_STRPCL_CLOCK_STOP, host->base + JZ_REG_MMC_STRPCL);
+        do {
+                status = readl(host->base + JZ_REG_MMC_STATUS);
+        } while (status & JZ_MMC_STATUS_CLK_EN && --timeout);
+}
+
+static void jz4740_mmc_reset(struct jz4740_mmc_host *host)
+{
+        uint32_t status;
+        unsigned int timeout = 1000;
+
+        writew(JZ_MMC_STRPCL_RESET, host->base + JZ_REG_MMC_STRPCL);
+        udelay(10);
+        do {
+                status = readl(host->base + JZ_REG_MMC_STATUS);
+        } while (status & JZ_MMC_STATUS_IS_RESETTING && --timeout);
+}
+
+static void jz4740_mmc_request_done(struct jz4740_mmc_host *host)
+{
+        struct mmc_request *req;
+
+        req = host->req;
+        host->req = NULL;
+
+        mmc_request_done(host->mmc, req);
+}
+
+static unsigned int jz4740_mmc_poll_irq(struct jz4740_mmc_host *host,
+        unsigned int irq)
+{
+        unsigned int timeout = 0x800;
+        uint16_t status;
+
+        do {
+                status = readw(host->base + JZ_REG_MMC_IREG);
+        } while (!(status & irq) && --timeout);
+
+        if (timeout == 0) {
+                set_bit(0, &host->waiting);
+                mod_timer(&host->timeout_timer, jiffies + 5*HZ);
+                jz4740_mmc_set_irq_enabled(host, irq, true);
+                return true;
+        }
+
+        return false;
+}
+
+static void jz4740_mmc_transfer_check_state(struct jz4740_mmc_host *host,
+        struct mmc_data *data)
+{
+        int status;
+
+        status = readl(host->base + JZ_REG_MMC_STATUS);
+        if (status & JZ_MMC_STATUS_WRITE_ERROR_MASK) {
+                if (status & (JZ_MMC_STATUS_TIMEOUT_WRITE)) {
+                        host->req->cmd->error = -ETIMEDOUT;
+                        data->error = -ETIMEDOUT;
+                } else {
+                        host->req->cmd->error = -EIO;
+                        data->error = -EIO;
+                }
+        }
+}
+
+static bool jz4740_mmc_write_data(struct jz4740_mmc_host *host,
+        struct mmc_data *data)
+{
+        struct sg_mapping_iter *miter = &host->miter;
+        void __iomem *fifo_addr = host->base + JZ_REG_MMC_TXFIFO;
+        uint32_t *buf;
+        bool timeout;
+        size_t i, j;
+
+        while (sg_miter_next(miter)) {
+                buf = miter->addr;
+                i = miter->length / 4;
+                j = i / 8;
+                i = i & 0x7;
+                while (j) {
+                        timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ);
+                        if (unlikely(timeout))
+                                goto poll_timeout;
+
+                        writel(buf[0], fifo_addr);
+                        writel(buf[1], fifo_addr);
+                        writel(buf[2], fifo_addr);
+                        writel(buf[3], fifo_addr);
+                        writel(buf[4], fifo_addr);
+                        writel(buf[5], fifo_addr);
+                        writel(buf[6], fifo_addr);
+                        writel(buf[7], fifo_addr);
+                        buf += 8;
+                        --j;
+                }
+                if (unlikely(i)) {
+                        timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ);
+                        if (unlikely(timeout))
+                                goto poll_timeout;
+
+                        while (i) {
+                                writel(*buf, fifo_addr);
+                                ++buf;
+                                --i;
+                        }
+                }
+                data->bytes_xfered += miter->length;
+        }
+        sg_miter_stop(miter);
+
+        return false;
+
+poll_timeout:
+        miter->consumed = (void *)buf - miter->addr;
+        data->bytes_xfered += miter->consumed;
+        sg_miter_stop(miter);
+
+        return true;
+}
+
+static bool jz4740_mmc_read_data(struct jz4740_mmc_host *host,
+                                struct mmc_data *data)
+{
+        struct sg_mapping_iter *miter = &host->miter;
+        void __iomem *fifo_addr = host->base + JZ_REG_MMC_RXFIFO;
+        uint32_t *buf;
+        uint32_t d;
+        uint16_t status;
+        size_t i, j;
+        unsigned int timeout;
+
+        while (sg_miter_next(miter)) {
+                buf = miter->addr;
+                i = miter->length;
+                j = i / 32;
+                i = i & 0x1f;
+                while (j) {
+                        timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_RXFIFO_RD_REQ);
+                        if (unlikely(timeout))
+                                goto poll_timeout;
+
+                        buf[0] = readl(fifo_addr);
+                        buf[1] = readl(fifo_addr);
+                        buf[2] = readl(fifo_addr);
+                        buf[3] = readl(fifo_addr);
+                        buf[4] = readl(fifo_addr);
+                        buf[5] = readl(fifo_addr);
+                        buf[6] = readl(fifo_addr);
+                        buf[7] = readl(fifo_addr);
+
+                        buf += 8;
+                        --j;
+                }
+
+                if (unlikely(i)) {
+                        timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_RXFIFO_RD_REQ);
+                        if (unlikely(timeout))
+                                goto poll_timeout;
+
+                        while (i >= 4) {
+                                *buf++ = readl(fifo_addr);
+                                i -= 4;
+                        }
+                        if (unlikely(i > 0)) {
+                                d = readl(fifo_addr);
+                                memcpy(buf, &d, i);
+                        }
+                }
+                data->bytes_xfered += miter->length;
+
+                /* This can go away once MIPS implements
+                 * flush_kernel_dcache_page */
+                flush_dcache_page(miter->page);
+        }
+        sg_miter_stop(miter);
+
+        /* For whatever reason there is sometime one word more in the fifo then
+         * requested */
+        timeout = 1000;
+        status = readl(host->base + JZ_REG_MMC_STATUS);
+        while (!(status & JZ_MMC_STATUS_DATA_FIFO_EMPTY) && --timeout) {
+                d = readl(fifo_addr);
+                status = readl(host->base + JZ_REG_MMC_STATUS);
+        }
+
+        return false;
+
+poll_timeout:
+        miter->consumed = (void *)buf - miter->addr;
+        data->bytes_xfered += miter->consumed;
+        sg_miter_stop(miter);
+
+        return true;
+}
+
+static void jz4740_mmc_timeout(unsigned long data)
+{
+        struct jz4740_mmc_host *host = (struct jz4740_mmc_host *)data;
+
+        if (!test_and_clear_bit(0, &host->waiting))
+                return;
+
+        jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_END_CMD_RES, false);
+
+        host->req->cmd->error = -ETIMEDOUT;
+        jz4740_mmc_request_done(host);
+}
+
+static void jz4740_mmc_read_response(struct jz4740_mmc_host *host,
+        struct mmc_command *cmd)
+{
+        int i;
+        uint16_t tmp;
+        void __iomem *fifo_addr = host->base + JZ_REG_MMC_RESP_FIFO;
+
+        if (cmd->flags & MMC_RSP_136) {
+                tmp = readw(fifo_addr);
+                for (i = 0; i < 4; ++i) {
+                        cmd->resp[i] = tmp << 24;
+                        tmp = readw(fifo_addr);
+                        cmd->resp[i] |= tmp << 8;
+                        tmp = readw(fifo_addr);
+                        cmd->resp[i] |= tmp >> 8;
+                }
+        } else {
+                cmd->resp[0] = readw(fifo_addr) << 24;
+                cmd->resp[0] |= readw(fifo_addr) << 8;
+                cmd->resp[0] |= readw(fifo_addr) & 0xff;
+        }
+}
+
+static void jz4740_mmc_send_command(struct jz4740_mmc_host *host,
+        struct mmc_command *cmd)
+{
+        uint32_t cmdat = host->cmdat;
+
+        host->cmdat &= ~JZ_MMC_CMDAT_INIT;
+        jz4740_mmc_clock_disable(host);
+
+        host->cmd = cmd;
+
+        if (cmd->flags & MMC_RSP_BUSY)
+                cmdat |= JZ_MMC_CMDAT_BUSY;
+
+        switch (mmc_resp_type(cmd)) {
+        case MMC_RSP_R1B:
+        case MMC_RSP_R1:
+                cmdat |= JZ_MMC_CMDAT_RSP_R1;
+                break;
+        case MMC_RSP_R2:
+                cmdat |= JZ_MMC_CMDAT_RSP_R2;
+                break;
+        case MMC_RSP_R3:
+                cmdat |= JZ_MMC_CMDAT_RSP_R3;
+                break;
+        default:
+                break;
+        }
+
+        if (cmd->data) {
+                cmdat |= JZ_MMC_CMDAT_DATA_EN;
+                if (cmd->data->flags & MMC_DATA_WRITE)
+                        cmdat |= JZ_MMC_CMDAT_WRITE;
+                if (cmd->data->flags & MMC_DATA_STREAM)
+                        cmdat |= JZ_MMC_CMDAT_STREAM;
+
+                writew(cmd->data->blksz, host->base + JZ_REG_MMC_BLKLEN);
+                writew(cmd->data->blocks, host->base + JZ_REG_MMC_NOB);
+        }
+
+        writeb(cmd->opcode, host->base + JZ_REG_MMC_CMD);
+        writel(cmd->arg, host->base + JZ_REG_MMC_ARG);
+        writel(cmdat, host->base + JZ_REG_MMC_CMDAT);
+
+        jz4740_mmc_clock_enable(host, 1);
+}
+
+static void jz_mmc_prepare_data_transfer(struct jz4740_mmc_host *host)
+{
+        struct mmc_command *cmd = host->req->cmd;
+        struct mmc_data *data = cmd->data;
+        int direction;
+
+        if (data->flags & MMC_DATA_READ)
+                direction = SG_MITER_TO_SG;
+        else
+                direction = SG_MITER_FROM_SG;
+
+        sg_miter_start(&host->miter, data->sg, data->sg_len, direction);
+}
+
+
+static irqreturn_t jz_mmc_irq_worker(int irq, void *devid)
+{
+        struct jz4740_mmc_host *host = (struct jz4740_mmc_host *)devid;
+        struct mmc_command *cmd = host->req->cmd;
+        struct mmc_request *req = host->req;
+        bool timeout = false;
+
+        if (cmd->error)
+                host->state = JZ4740_MMC_STATE_DONE;
+
+        switch (host->state) {
+        case JZ4740_MMC_STATE_READ_RESPONSE:
+                if (cmd->flags & MMC_RSP_PRESENT)
+                        jz4740_mmc_read_response(host, cmd);
+
+                if (!cmd->data)
+                        break;
+
+                jz_mmc_prepare_data_transfer(host);
+
+        case JZ4740_MMC_STATE_TRANSFER_DATA:
+                if (cmd->data->flags & MMC_DATA_READ)
+                        timeout = jz4740_mmc_read_data(host, cmd->data);
+                else
+                        timeout = jz4740_mmc_write_data(host, cmd->data);
+
+                if (unlikely(timeout)) {
+                        host->state = JZ4740_MMC_STATE_TRANSFER_DATA;
+                        break;
+                }
+
+                jz4740_mmc_transfer_check_state(host, cmd->data);
+
+                timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_DATA_TRAN_DONE);
+                if (unlikely(timeout)) {
+                        host->state = JZ4740_MMC_STATE_SEND_STOP;
+                        break;
+                }
+                writew(JZ_MMC_IRQ_DATA_TRAN_DONE, host->base + JZ_REG_MMC_IREG);
+
+        case JZ4740_MMC_STATE_SEND_STOP:
+                if (!req->stop)
+                        break;
+
+                jz4740_mmc_send_command(host, req->stop);
+
+                timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_PRG_DONE);
+                if (timeout) {
+                        host->state = JZ4740_MMC_STATE_DONE;
+                        break;
+                }
+        case JZ4740_MMC_STATE_DONE:
+                break;
+        }
+
+        if (!timeout)
+                jz4740_mmc_request_done(host);
+
+        return IRQ_HANDLED;
+}
+
+static irqreturn_t jz_mmc_irq(int irq, void *devid)
+{
+        struct jz4740_mmc_host *host = devid;
+        struct mmc_command *cmd = host->cmd;
+        uint16_t irq_reg, status, tmp;
+
+        irq_reg = readw(host->base + JZ_REG_MMC_IREG);
+
+        tmp = irq_reg;
+        irq_reg &= ~host->irq_mask;
+
+        tmp &= ~(JZ_MMC_IRQ_TXFIFO_WR_REQ | JZ_MMC_IRQ_RXFIFO_RD_REQ |
+                JZ_MMC_IRQ_PRG_DONE | JZ_MMC_IRQ_DATA_TRAN_DONE);
+
+        if (tmp != irq_reg)
+                writew(tmp & ~irq_reg, host->base + JZ_REG_MMC_IREG);
+
+        if (irq_reg & JZ_MMC_IRQ_SDIO) {
+                writew(JZ_MMC_IRQ_SDIO, host->base + JZ_REG_MMC_IREG);
+                mmc_signal_sdio_irq(host->mmc);
+                irq_reg &= ~JZ_MMC_IRQ_SDIO;
+        }
+
+        if (host->req && cmd && irq_reg) {
+                if (test_and_clear_bit(0, &host->waiting)) {
+                        del_timer(&host->timeout_timer);
+
+                        status = readl(host->base + JZ_REG_MMC_STATUS);
+
+                        if (status & JZ_MMC_STATUS_TIMEOUT_RES) {
+                                        cmd->error = -ETIMEDOUT;
+                        } else if (status & JZ_MMC_STATUS_CRC_RES_ERR) {
+                                        cmd->error = -EIO;
+                        } else if (status & (JZ_MMC_STATUS_CRC_READ_ERROR |
+                                    JZ_MMC_STATUS_CRC_WRITE_ERROR)) {
+                                        if (cmd->data)
+                                                        cmd->data->error = -EIO;
+                                        cmd->error = -EIO;
+                        } else if (status & (JZ_MMC_STATUS_CRC_READ_ERROR |
+                                        JZ_MMC_STATUS_CRC_WRITE_ERROR)) {
+                                        if (cmd->data)
+                                                        cmd->data->error = -EIO;
+                                        cmd->error = -EIO;
+                        }
+
+                        jz4740_mmc_set_irq_enabled(host, irq_reg, false);
+                        writew(irq_reg, host->base + JZ_REG_MMC_IREG);
+
+                        return IRQ_WAKE_THREAD;
+                }
+        }
+
+        return IRQ_HANDLED;
+}
+
+static int jz4740_mmc_set_clock_rate(struct jz4740_mmc_host *host, int rate)
+{
+        int div = 0;
+        int real_rate;
+
+        jz4740_mmc_clock_disable(host);
+        clk_set_rate(host->clk, JZ_MMC_CLK_RATE);
+
+        real_rate = clk_get_rate(host->clk);
+
+        while (real_rate > rate && div < 7) {
+                ++div;
+                real_rate >>= 1;
+        }
+
+        writew(div, host->base + JZ_REG_MMC_CLKRT);
+        return real_rate;
+}
+
+static void jz4740_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
+{
+        struct jz4740_mmc_host *host = mmc_priv(mmc);
+
+        host->req = req;
+
+        writew(0xffff, host->base + JZ_REG_MMC_IREG);
+
+        writew(JZ_MMC_IRQ_END_CMD_RES, host->base + JZ_REG_MMC_IREG);
+        jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_END_CMD_RES, true);
+
+        host->state = JZ4740_MMC_STATE_READ_RESPONSE;
+        set_bit(0, &host->waiting);
+        mod_timer(&host->timeout_timer, jiffies + 5*HZ);
+        jz4740_mmc_send_command(host, req->cmd);
+}
+
+static void jz4740_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
+{
+        struct jz4740_mmc_host *host = mmc_priv(mmc);
+        if (ios->clock)
+                jz4740_mmc_set_clock_rate(host, ios->clock);
+
+        switch (ios->power_mode) {
+        case MMC_POWER_UP:
+                jz4740_mmc_reset(host);
+                if (gpio_is_valid(host->pdata->gpio_power))
+                        gpio_set_value(host->pdata->gpio_power,
+                                        !host->pdata->power_active_low);
+                host->cmdat |= JZ_MMC_CMDAT_INIT;
+                clk_enable(host->clk);
+                break;
+        case MMC_POWER_ON:
+                break;
+        default:
+                if (gpio_is_valid(host->pdata->gpio_power))
+                        gpio_set_value(host->pdata->gpio_power,
+                                        host->pdata->power_active_low);
+                clk_disable(host->clk);
+                break;
+        }
+
+        switch (ios->bus_width) {
+        case MMC_BUS_WIDTH_1:
+                host->cmdat &= ~JZ_MMC_CMDAT_BUS_WIDTH_4BIT;
+                break;
+        case MMC_BUS_WIDTH_4:
+                host->cmdat |= JZ_MMC_CMDAT_BUS_WIDTH_4BIT;
+                break;
+        default:
+                break;
+        }
+}
+
+static int jz4740_mmc_get_ro(struct mmc_host *mmc)
+{
+        struct jz4740_mmc_host *host = mmc_priv(mmc);
+        if (!gpio_is_valid(host->pdata->gpio_read_only))
+                return -ENOSYS;
+
+        return gpio_get_value(host->pdata->gpio_read_only) ^
+                host->pdata->read_only_active_low;
+}
+
+static int jz4740_mmc_get_cd(struct mmc_host *mmc)
+{
+        struct jz4740_mmc_host *host = mmc_priv(mmc);
+        if (!gpio_is_valid(host->pdata->gpio_card_detect))
+                return -ENOSYS;
+
+        return gpio_get_value(host->pdata->gpio_card_detect) ^
+                        host->pdata->card_detect_active_low;
+}
+
+static irqreturn_t jz4740_mmc_card_detect_irq(int irq, void *devid)
+{
+        struct jz4740_mmc_host *host = devid;
+
+        mmc_detect_change(host->mmc, HZ / 2);
+
+        return IRQ_HANDLED;
+}
+
+static void jz4740_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
+{
+        struct jz4740_mmc_host *host = mmc_priv(mmc);
+        jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_SDIO, enable);
+}
+
+static const struct mmc_host_ops jz4740_mmc_ops = {
+        .request        = jz4740_mmc_request,
+        .set_ios        = jz4740_mmc_set_ios,
+        .get_ro         = jz4740_mmc_get_ro,
+        .get_cd         = jz4740_mmc_get_cd,
+        .enable_sdio_irq = jz4740_mmc_enable_sdio_irq,
+};
+
+static const struct jz_gpio_bulk_request jz4740_mmc_pins[] = {
+        JZ_GPIO_BULK_PIN(MSC_CMD),
+        JZ_GPIO_BULK_PIN(MSC_CLK),
+        JZ_GPIO_BULK_PIN(MSC_DATA0),
+        JZ_GPIO_BULK_PIN(MSC_DATA1),
+        JZ_GPIO_BULK_PIN(MSC_DATA2),
+        JZ_GPIO_BULK_PIN(MSC_DATA3),
+};
+
+static int __devinit jz4740_mmc_request_gpio(struct device *dev, int gpio,
+        const char *name, bool output, int value)
+{
+        int ret;
+
+        if (!gpio_is_valid(gpio))
+                return 0;
+
+        ret = gpio_request(gpio, name);
+        if (ret) {
+                dev_err(dev, "Failed to request %s gpio: %d\n", name, ret);
+                return ret;
+        }
+
+        if (output)
+                gpio_direction_output(gpio, value);
+        else
+                gpio_direction_input(gpio);
+
+        return 0;
+}
+
+static int __devinit jz4740_mmc_request_gpios(struct platform_device *pdev)
+{
+        int ret;
+        struct jz4740_mmc_platform_data *pdata = pdev->dev.platform_data;
+
+        if (!pdata)
+                return 0;
+
+        ret = jz4740_mmc_request_gpio(&pdev->dev, pdata->gpio_card_detect,
+                        "MMC detect change", false, 0);
+        if (ret)
+                goto err;
+
+        ret = jz4740_mmc_request_gpio(&pdev->dev, pdata->gpio_read_only,
+                        "MMC read only", false, 0);
+        if (ret)
+                goto err_free_gpio_card_detect;
+
+        ret = jz4740_mmc_request_gpio(&pdev->dev, pdata->gpio_power,
+                        "MMC read only", true, pdata->power_active_low);
+        if (ret)
+                goto err_free_gpio_read_only;
+
+        return 0;
+
+err_free_gpio_read_only:
+        if (gpio_is_valid(pdata->gpio_read_only))
+                gpio_free(pdata->gpio_read_only);
+err_free_gpio_card_detect:
+        if (gpio_is_valid(pdata->gpio_card_detect))
+                gpio_free(pdata->gpio_card_detect);
+err:
+        return ret;
+}
+
+static int __devinit jz4740_mmc_request_cd_irq(struct platform_device *pdev,
+        struct jz4740_mmc_host *host)
+{
+        struct jz4740_mmc_platform_data *pdata = pdev->dev.platform_data;
+
+        if (!gpio_is_valid(pdata->gpio_card_detect))
+                return 0;
+
+        host->card_detect_irq = gpio_to_irq(pdata->gpio_card_detect);
+        if (host->card_detect_irq < 0) {
+                dev_warn(&pdev->dev, "Failed to get card detect irq\n");
+                return 0;
+        }
+
+        return request_irq(host->card_detect_irq, jz4740_mmc_card_detect_irq,
+                        IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
+                        "MMC card detect", host);
+}
+
+static void jz4740_mmc_free_gpios(struct platform_device *pdev)
+{
+        struct jz4740_mmc_platform_data *pdata = pdev->dev.platform_data;
+
+        if (!pdata)
+                return;
+
+        if (gpio_is_valid(pdata->gpio_power))
+                gpio_free(pdata->gpio_power);
+        if (gpio_is_valid(pdata->gpio_read_only))
+                gpio_free(pdata->gpio_read_only);
+        if (gpio_is_valid(pdata->gpio_card_detect))
+                gpio_free(pdata->gpio_card_detect);
+}
+
+static inline size_t jz4740_mmc_num_pins(struct jz4740_mmc_host *host)
+{
+        size_t num_pins = ARRAY_SIZE(jz4740_mmc_pins);
+        if (host->pdata && host->pdata->data_1bit)
+                num_pins -= 3;
+
+        return num_pins;
+}
+
+static int __devinit jz4740_mmc_probe(struct platform_device* pdev)
+{
+        int ret;
+        struct mmc_host *mmc;
+        struct jz4740_mmc_host *host;
+        struct jz4740_mmc_platform_data *pdata;
+
+        pdata = pdev->dev.platform_data;
+
+        mmc = mmc_alloc_host(sizeof(struct jz4740_mmc_host), &pdev->dev);
+        if (!mmc) {
+                dev_err(&pdev->dev, "Failed to alloc mmc host structure\n");
+                return -ENOMEM;
+        }
+
+        host = mmc_priv(mmc);
+        host->pdata = pdata;
+
+        host->irq = platform_get_irq(pdev, 0);
+        if (host->irq < 0) {
+                ret = host->irq;
+                dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret);
+                goto err_free_host;
+        }
+
+        host->clk = clk_get(&pdev->dev, "mmc");
+        if (!host->clk) {
+                ret = -ENOENT;
+                dev_err(&pdev->dev, "Failed to get mmc clock\n");
+                goto err_free_host;
+        }
+
+        host->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!host->mem) {
+                ret = -ENOENT;
+                dev_err(&pdev->dev, "Failed to get base platform memory\n");
+                goto err_clk_put;
+        }
+
+        host->mem = request_mem_region(host->mem->start,
+                                        resource_size(host->mem), pdev->name);
+        if (!host->mem) {
+                ret = -EBUSY;
+                dev_err(&pdev->dev, "Failed to request base memory region\n");
+                goto err_clk_put;
+        }
+
+        host->base = ioremap_nocache(host->mem->start, resource_size(host->mem));
+        if (!host->base) {
+                ret = -EBUSY;
+                dev_err(&pdev->dev, "Failed to ioremap base memory\n");
+                goto err_release_mem_region;
+        }
+
+        ret = jz_gpio_bulk_request(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
+        if (ret) {
+                dev_err(&pdev->dev, "Failed to request mmc pins: %d\n", ret);
+                goto err_iounmap;
+        }
+
+        ret = jz4740_mmc_request_gpios(pdev);
+        if (ret)
+                goto err_gpio_bulk_free;
+
+        mmc->ops = &jz4740_mmc_ops;
+        mmc->f_min = JZ_MMC_CLK_RATE / 128;
+        mmc->f_max = JZ_MMC_CLK_RATE;
+        mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
+        mmc->caps = (pdata && pdata->data_1bit) ? 0 : MMC_CAP_4_BIT_DATA;
+        mmc->caps |= MMC_CAP_SDIO_IRQ;
+
+        mmc->max_blk_size = (1 << 10) - 1;
+        mmc->max_blk_count = (1 << 15) - 1;
+        mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
+
+        mmc->max_phys_segs = 128;
+        mmc->max_hw_segs = 128;
+        mmc->max_seg_size = mmc->max_req_size;
+
+        host->mmc = mmc;
+        host->pdev = pdev;
+        spin_lock_init(&host->lock);
+        host->irq_mask = 0xffff;
+
+        ret = jz4740_mmc_request_cd_irq(pdev, host);
+        if (ret) {
+                dev_err(&pdev->dev, "Failed to request card detect irq\n");
+                goto err_free_gpios;
+        }
+
+        ret = request_threaded_irq(host->irq, jz_mmc_irq, jz_mmc_irq_worker, 0,
+                        dev_name(&pdev->dev), host);
+        if (ret) {
+                dev_err(&pdev->dev, "Failed to request irq: %d\n", ret);
+                goto err_free_card_detect_irq;
+        }
+
+        jz4740_mmc_reset(host);
+        jz4740_mmc_clock_disable(host);
+        setup_timer(&host->timeout_timer, jz4740_mmc_timeout,
+                        (unsigned long)host);
+        /* It is not important when it times out, it just needs to timeout. */
+        set_timer_slack(&host->timeout_timer, HZ);
+
+        platform_set_drvdata(pdev, host);
+        ret = mmc_add_host(mmc);
+
+        if (ret) {
+                dev_err(&pdev->dev, "Failed to add mmc host: %d\n", ret);
+                goto err_free_irq;
+        }
+        dev_info(&pdev->dev, "JZ SD/MMC card driver registered\n");
+
+        return 0;
+
+err_free_irq:
+        free_irq(host->irq, host);
+err_free_card_detect_irq:
+        if (host->card_detect_irq >= 0)
+                free_irq(host->card_detect_irq, host);
+err_free_gpios:
+        jz4740_mmc_free_gpios(pdev);
+err_gpio_bulk_free:
+        jz_gpio_bulk_free(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
+err_iounmap:
+        iounmap(host->base);
+err_release_mem_region:
+        release_mem_region(host->mem->start, resource_size(host->mem));
+err_clk_put:
+        clk_put(host->clk);
+err_free_host:
+        platform_set_drvdata(pdev, NULL);
+        mmc_free_host(mmc);
+
+        return ret;
+}
+
+static int __devexit jz4740_mmc_remove(struct platform_device *pdev)
+{
+        struct jz4740_mmc_host *host = platform_get_drvdata(pdev);
+
+        del_timer_sync(&host->timeout_timer);
+        jz4740_mmc_set_irq_enabled(host, 0xff, false);
+        jz4740_mmc_reset(host);
+
+        mmc_remove_host(host->mmc);
+
+        free_irq(host->irq, host);
+        if (host->card_detect_irq >= 0)
+                free_irq(host->card_detect_irq, host);
+
+        jz4740_mmc_free_gpios(pdev);
+        jz_gpio_bulk_free(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
+
+        iounmap(host->base);
+        release_mem_region(host->mem->start, resource_size(host->mem));
+
+        clk_put(host->clk);
+
+        platform_set_drvdata(pdev, NULL);
+        mmc_free_host(host->mmc);
+
+        return 0;
+}
+
+#ifdef CONFIG_PM
+
+static int jz4740_mmc_suspend(struct device *dev)
+{
+        struct jz4740_mmc_host *host = dev_get_drvdata(dev);
+
+        mmc_suspend_host(host->mmc);
+
+        jz_gpio_bulk_suspend(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
+
+        return 0;
+}
+
+static int jz4740_mmc_resume(struct device *dev)
+{
+        struct jz4740_mmc_host *host = dev_get_drvdata(dev);
+
+        jz_gpio_bulk_resume(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
+
+        mmc_resume_host(host->mmc);
+
+        return 0;
+}
+
+const struct dev_pm_ops jz4740_mmc_pm_ops = {
+        .suspend        = jz4740_mmc_suspend,
+        .resume         = jz4740_mmc_resume,
+        .poweroff       = jz4740_mmc_suspend,
+        .restore        = jz4740_mmc_resume,
+};
+
+#define JZ4740_MMC_PM_OPS (&jz4740_mmc_pm_ops)
+#else
+#define JZ4740_MMC_PM_OPS NULL
+#endif
+
+static struct platform_driver jz4740_mmc_driver = {
+        .probe = jz4740_mmc_probe,
+        .remove = __devexit_p(jz4740_mmc_remove),
+        .driver = {
+                .name = "jz4740-mmc",
+                .owner = THIS_MODULE,
+                .pm = JZ4740_MMC_PM_OPS,
+        },
+};
+
+static int __init jz4740_mmc_init(void)
+{
+        return platform_driver_register(&jz4740_mmc_driver);
+}
+module_init(jz4740_mmc_init);
+
+static void __exit jz4740_mmc_exit(void)
+{
+        platform_driver_unregister(&jz4740_mmc_driver);
+}
+module_exit(jz4740_mmc_exit);
+
+MODULE_DESCRIPTION("JZ4740 SD/MMC controller driver");
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
diff --git a/drivers/mtd/maps/Kconfig b/drivers/mtd/maps/Kconfig
index f22bc9f05ddb..6629d09f3b38 100644
--- a/drivers/mtd/maps/Kconfig
+++ b/drivers/mtd/maps/Kconfig
@@ -321,7 +321,7 @@ config MTD_CFI_FLAGADM
 
 config MTD_REDWOOD
         tristate "CFI Flash devices mapped on IBM Redwood"
-        depends on MTD_CFI && ( REDWOOD_4 || REDWOOD_5 || REDWOOD_6 )
+        depends on MTD_CFI
         help
           This enables access routines for the flash chips on the IBM
           Redwood board. If you have one of these boards and would like to
diff --git a/drivers/mtd/maps/redwood.c b/drivers/mtd/maps/redwood.c
index 933c0b63b016..d2c9db00db0c 100644
--- a/drivers/mtd/maps/redwood.c
+++ b/drivers/mtd/maps/redwood.c
@@ -22,8 +22,6 @@
 
 #include <asm/io.h>
 
-#if !defined (CONFIG_REDWOOD_6)
-
 #define WINDOW_ADDR 0xffc00000
 #define WINDOW_SIZE 0x00400000
 
@@ -69,47 +67,6 @@ static struct mtd_partition redwood_flash_partitions[] = {
         }
 };
 
-#else /* CONFIG_REDWOOD_6 */
-/* FIXME: the window is bigger - armin */
-#define WINDOW_ADDR 0xff800000
-#define WINDOW_SIZE 0x00800000
-
-#define RW_PART0_OF     0
-#define RW_PART0_SZ     0x400000        /* 4 MiB data */
-#define RW_PART1_OF     RW_PART0_OF + RW_PART0_SZ
-#define RW_PART1_SZ     0x10000         /* 64K VPD */
-#define RW_PART2_OF     RW_PART1_OF + RW_PART1_SZ
-#define RW_PART2_SZ     0x400000 - (0x10000 + 0x20000)
-#define RW_PART3_OF     RW_PART2_OF + RW_PART2_SZ
-#define RW_PART3_SZ     0x20000
-
-static struct mtd_partition redwood_flash_partitions[] = {
-        {
-                .name = "Redwood filesystem",
-                .offset = RW_PART0_OF,
-                .size = RW_PART0_SZ
-        },
-        {
-                .name = "Redwood OpenBIOS Vital Product Data",
-                .offset = RW_PART1_OF,
-                .size = RW_PART1_SZ,
-                .mask_flags = MTD_WRITEABLE     /* force read-only */
-        },
-        {
-                .name = "Redwood kernel",
-                .offset = RW_PART2_OF,
-                .size = RW_PART2_SZ
-        },
-        {
-                .name = "Redwood OpenBIOS",
-                .offset = RW_PART3_OF,
-                .size = RW_PART3_SZ,
-                .mask_flags = MTD_WRITEABLE     /* force read-only */
-        }
-};
-
-#endif /* CONFIG_REDWOOD_6 */
-
 struct map_info redwood_flash_map = {
         .name = "IBM Redwood",
         .size = WINDOW_SIZE,
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index ffc3720929f1..362d177efe1b 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -526,4 +526,10 @@ config MTD_NAND_NUC900
           This enables the driver for the NAND Flash on evaluation board based
           on w90p910 / NUC9xx.
 
+config MTD_NAND_JZ4740
+        tristate "Support for JZ4740 SoC NAND controller"
+        depends on MACH_JZ4740
+        help
+                Enables support for NAND Flash on JZ4740 SoC based boards.
+
 endif # MTD_NAND
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index e8ab884ba47b..ac83dcdac5d6 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -46,5 +46,6 @@ obj-$(CONFIG_MTD_NAND_NOMADIK)		+= nomadik_nand.o
 obj-$(CONFIG_MTD_NAND_BCM_UMI)          += bcm_umi_nand.o nand_bcm_umi.o
 obj-$(CONFIG_MTD_NAND_MPC5121_NFC)      += mpc5121_nfc.o
 obj-$(CONFIG_MTD_NAND_RICOH)            += r852.o
+obj-$(CONFIG_MTD_NAND_JZ4740)           += jz4740_nand.o
 
 nand-objs := nand_base.o nand_bbt.o
diff --git a/drivers/mtd/nand/jz4740_nand.c b/drivers/mtd/nand/jz4740_nand.c
new file mode 100644
index 000000000000..67343fc31bd5
--- /dev/null
+++ b/drivers/mtd/nand/jz4740_nand.c
@@ -0,0 +1,516 @@
+/*
+ *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
+ *  JZ4740 SoC NAND controller driver
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under  the terms of the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#include <linux/ioport.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
+
+#include <linux/gpio.h>
+
+#include <asm/mach-jz4740/jz4740_nand.h>
+
+#define JZ_REG_NAND_CTRL        0x50
+#define JZ_REG_NAND_ECC_CTRL    0x100
+#define JZ_REG_NAND_DATA        0x104
+#define JZ_REG_NAND_PAR0        0x108
+#define JZ_REG_NAND_PAR1        0x10C
+#define JZ_REG_NAND_PAR2        0x110
+#define JZ_REG_NAND_IRQ_STAT    0x114
+#define JZ_REG_NAND_IRQ_CTRL    0x118
+#define JZ_REG_NAND_ERR(x)      (0x11C + ((x) << 2))
+
+#define JZ_NAND_ECC_CTRL_PAR_READY      BIT(4)
+#define JZ_NAND_ECC_CTRL_ENCODING       BIT(3)
+#define JZ_NAND_ECC_CTRL_RS             BIT(2)
+#define JZ_NAND_ECC_CTRL_RESET          BIT(1)
+#define JZ_NAND_ECC_CTRL_ENABLE         BIT(0)
+
+#define JZ_NAND_STATUS_ERR_COUNT        (BIT(31) | BIT(30) | BIT(29))
+#define JZ_NAND_STATUS_PAD_FINISH       BIT(4)
+#define JZ_NAND_STATUS_DEC_FINISH       BIT(3)
+#define JZ_NAND_STATUS_ENC_FINISH       BIT(2)
+#define JZ_NAND_STATUS_UNCOR_ERROR      BIT(1)
+#define JZ_NAND_STATUS_ERROR            BIT(0)
+
+#define JZ_NAND_CTRL_ENABLE_CHIP(x) BIT((x) << 1)
+#define JZ_NAND_CTRL_ASSERT_CHIP(x) BIT(((x) << 1) + 1)
+
+#define JZ_NAND_MEM_ADDR_OFFSET 0x10000
+#define JZ_NAND_MEM_CMD_OFFSET 0x08000
+
+struct jz_nand {
+        struct mtd_info mtd;
+        struct nand_chip chip;
+        void __iomem *base;
+        struct resource *mem;
+
+        void __iomem *bank_base;
+        struct resource *bank_mem;
+
+        struct jz_nand_platform_data *pdata;
+        bool is_reading;
+};
+
+static inline struct jz_nand *mtd_to_jz_nand(struct mtd_info *mtd)
+{
+        return container_of(mtd, struct jz_nand, mtd);
+}
+
+static void jz_nand_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl)
+{
+        struct jz_nand *nand = mtd_to_jz_nand(mtd);
+        struct nand_chip *chip = mtd->priv;
+        uint32_t reg;
+
+        if (ctrl & NAND_CTRL_CHANGE) {
+                BUG_ON((ctrl & NAND_ALE) && (ctrl & NAND_CLE));
+                if (ctrl & NAND_ALE)
+                        chip->IO_ADDR_W = nand->bank_base + JZ_NAND_MEM_ADDR_OFFSET;
+                else if (ctrl & NAND_CLE)
+                        chip->IO_ADDR_W = nand->bank_base + JZ_NAND_MEM_CMD_OFFSET;
+                else
+                        chip->IO_ADDR_W = nand->bank_base;
+
+                reg = readl(nand->base + JZ_REG_NAND_CTRL);
+                if (ctrl & NAND_NCE)
+                        reg |= JZ_NAND_CTRL_ASSERT_CHIP(0);
+                else
+                        reg &= ~JZ_NAND_CTRL_ASSERT_CHIP(0);
+                writel(reg, nand->base + JZ_REG_NAND_CTRL);
+        }
+        if (dat != NAND_CMD_NONE)
+                writeb(dat, chip->IO_ADDR_W);
+}
+
+static int jz_nand_dev_ready(struct mtd_info *mtd)
+{
+        struct jz_nand *nand = mtd_to_jz_nand(mtd);
+        return gpio_get_value_cansleep(nand->pdata->busy_gpio);
+}
+
+static void jz_nand_hwctl(struct mtd_info *mtd, int mode)
+{
+        struct jz_nand *nand = mtd_to_jz_nand(mtd);
+        uint32_t reg;
+
+        writel(0, nand->base + JZ_REG_NAND_IRQ_STAT);
+        reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
+
+        reg |= JZ_NAND_ECC_CTRL_RESET;
+        reg |= JZ_NAND_ECC_CTRL_ENABLE;
+        reg |= JZ_NAND_ECC_CTRL_RS;
+
+        switch (mode) {
+        case NAND_ECC_READ:
+                reg &= ~JZ_NAND_ECC_CTRL_ENCODING;
+                nand->is_reading = true;
+                break;
+        case NAND_ECC_WRITE:
+                reg |= JZ_NAND_ECC_CTRL_ENCODING;
+                nand->is_reading = false;
+                break;
+        default:
+                break;
+        }
+
+        writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
+}
+
+static int jz_nand_calculate_ecc_rs(struct mtd_info *mtd, const uint8_t *dat,
+        uint8_t *ecc_code)
+{
+        struct jz_nand *nand = mtd_to_jz_nand(mtd);
+        uint32_t reg, status;
+        int i;
+        unsigned int timeout = 1000;
+        static uint8_t empty_block_ecc[] = {0xcd, 0x9d, 0x90, 0x58, 0xf4,
+                                                0x8b, 0xff, 0xb7, 0x6f};
+
+        if (nand->is_reading)
+                return 0;
+
+        do {
+                status = readl(nand->base + JZ_REG_NAND_IRQ_STAT);
+        } while (!(status & JZ_NAND_STATUS_ENC_FINISH) && --timeout);
+
+        if (timeout == 0)
+            return -1;
+
+        reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
+        reg &= ~JZ_NAND_ECC_CTRL_ENABLE;
+        writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
+
+        for (i = 0; i < 9; ++i)
+                ecc_code[i] = readb(nand->base + JZ_REG_NAND_PAR0 + i);
+
+        /* If the written data is completly 0xff, we also want to write 0xff as
+         * ecc, otherwise we will get in trouble when doing subpage writes. */
+        if (memcmp(ecc_code, empty_block_ecc, 9) == 0)
+                memset(ecc_code, 0xff, 9);
+
+        return 0;
+}
+
+static void jz_nand_correct_data(uint8_t *dat, int index, int mask)
+{
+        int offset = index & 0x7;
+        uint16_t data;
+
+        index += (index >> 3);
+
+        data = dat[index];
+        data |= dat[index+1] << 8;
+
+        mask ^= (data >> offset) & 0x1ff;
+        data &= ~(0x1ff << offset);
+        data |= (mask << offset);
+
+        dat[index] = data & 0xff;
+        dat[index+1] = (data >> 8) & 0xff;
+}
+
+static int jz_nand_correct_ecc_rs(struct mtd_info *mtd, uint8_t *dat,
+        uint8_t *read_ecc, uint8_t *calc_ecc)
+{
+        struct jz_nand *nand = mtd_to_jz_nand(mtd);
+        int i, error_count, index;
+        uint32_t reg, status, error;
+        uint32_t t;
+        unsigned int timeout = 1000;
+
+        t = read_ecc[0];
+
+        if (t == 0xff) {
+                for (i = 1; i < 9; ++i)
+                        t &= read_ecc[i];
+
+                t &= dat[0];
+                t &= dat[nand->chip.ecc.size / 2];
+                t &= dat[nand->chip.ecc.size - 1];
+
+                if (t == 0xff) {
+                        for (i = 1; i < nand->chip.ecc.size - 1; ++i)
+                                t &= dat[i];
+                        if (t == 0xff)
+                                return 0;
+                }
+        }
+
+        for (i = 0; i < 9; ++i)
+                writeb(read_ecc[i], nand->base + JZ_REG_NAND_PAR0 + i);
+
+        reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
+        reg |= JZ_NAND_ECC_CTRL_PAR_READY;
+        writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
+
+        do {
+                status = readl(nand->base + JZ_REG_NAND_IRQ_STAT);
+        } while (!(status & JZ_NAND_STATUS_DEC_FINISH) && --timeout);
+
+        if (timeout == 0)
+            return -1;
+
+        reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL);
+        reg &= ~JZ_NAND_ECC_CTRL_ENABLE;
+        writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL);
+
+        if (status & JZ_NAND_STATUS_ERROR) {
+                if (status & JZ_NAND_STATUS_UNCOR_ERROR)
+                        return -1;
+
+                error_count = (status & JZ_NAND_STATUS_ERR_COUNT) >> 29;
+
+                for (i = 0; i < error_count; ++i) {
+                        error = readl(nand->base + JZ_REG_NAND_ERR(i));
+                        index = ((error >> 16) & 0x1ff) - 1;
+                        if (index >= 0 && index < 512)
+                                jz_nand_correct_data(dat, index, error & 0x1ff);
+                }
+
+                return error_count;
+        }
+
+        return 0;
+}
+
+
+/* Copy paste of nand_read_page_hwecc_oob_first except for different eccpos
+ * handling. The ecc area is for 4k chips 72 bytes long and thus does not fit
+ * into the eccpos array. */
+static int jz_nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
+        struct nand_chip *chip, uint8_t *buf, int page)
+{
+        int i, eccsize = chip->ecc.size;
+        int eccbytes = chip->ecc.bytes;
+        int eccsteps = chip->ecc.steps;
+        uint8_t *p = buf;
+        unsigned int ecc_offset = chip->page_shift;
+
+        /* Read the OOB area first */
+        chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
+        chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
+        chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
+
+        for (i = ecc_offset; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+                int stat;
+
+                chip->ecc.hwctl(mtd, NAND_ECC_READ);
+                chip->read_buf(mtd, p, eccsize);
+
+                stat = chip->ecc.correct(mtd, p, &chip->oob_poi[i], NULL);
+                if (stat < 0)
+                        mtd->ecc_stats.failed++;
+                else
+                        mtd->ecc_stats.corrected += stat;
+        }
+        return 0;
+}
+
+/* Copy-and-paste of nand_write_page_hwecc with different eccpos handling. */
+static void jz_nand_write_page_hwecc(struct mtd_info *mtd,
+        struct nand_chip *chip, const uint8_t *buf)
+{
+        int i, eccsize = chip->ecc.size;
+        int eccbytes = chip->ecc.bytes;
+        int eccsteps = chip->ecc.steps;
+        const uint8_t *p = buf;
+        unsigned int ecc_offset = chip->page_shift;
+
+        for (i = ecc_offset; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+                chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
+                chip->write_buf(mtd, p, eccsize);
+                chip->ecc.calculate(mtd, p, &chip->oob_poi[i]);
+        }
+
+        chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
+}
+
+#ifdef CONFIG_MTD_CMDLINE_PARTS
+static const char *part_probes[] = {"cmdline", NULL};
+#endif
+
+static int jz_nand_ioremap_resource(struct platform_device *pdev,
+        const char *name, struct resource **res, void __iomem **base)
+{
+        int ret;
+
+        *res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
+        if (!*res) {
+                dev_err(&pdev->dev, "Failed to get platform %s memory\n", name);
+                ret = -ENXIO;
+                goto err;
+        }
+
+        *res = request_mem_region((*res)->start, resource_size(*res),
+                                pdev->name);
+        if (!*res) {
+                dev_err(&pdev->dev, "Failed to request %s memory region\n", name);
+                ret = -EBUSY;
+                goto err;
+        }
+
+        *base = ioremap((*res)->start, resource_size(*res));
+        if (!*base) {
+                dev_err(&pdev->dev, "Failed to ioremap %s memory region\n", name);
+                ret = -EBUSY;
+                goto err_release_mem;
+        }
+
+        return 0;
+
+err_release_mem:
+        release_mem_region((*res)->start, resource_size(*res));
+err:
+        *res = NULL;
+        *base = NULL;
+        return ret;
+}
+
+static int __devinit jz_nand_probe(struct platform_device *pdev)
+{
+        int ret;
+        struct jz_nand *nand;
+        struct nand_chip *chip;
+        struct mtd_info *mtd;
+        struct jz_nand_platform_data *pdata = pdev->dev.platform_data;
+#ifdef CONFIG_MTD_PARTITIONS
+        struct mtd_partition *partition_info;
+        int num_partitions = 0;
+#endif
+
+        nand = kzalloc(sizeof(*nand), GFP_KERNEL);
+        if (!nand) {
+                dev_err(&pdev->dev, "Failed to allocate device structure.\n");
+                return -ENOMEM;
+        }
+
+        ret = jz_nand_ioremap_resource(pdev, "mmio", &nand->mem, &nand->base);
+        if (ret)
+                goto err_free;
+        ret = jz_nand_ioremap_resource(pdev, "bank", &nand->bank_mem,
+                        &nand->bank_base);
+        if (ret)
+                goto err_iounmap_mmio;
+
+        if (pdata && gpio_is_valid(pdata->busy_gpio)) {
+                ret = gpio_request(pdata->busy_gpio, "NAND busy pin");
+                if (ret) {
+                        dev_err(&pdev->dev,
+                                "Failed to request busy gpio %d: %d\n",
+                                pdata->busy_gpio, ret);
+                        goto err_iounmap_mem;
+                }
+        }
+
+        mtd             = &nand->mtd;
+        chip            = &nand->chip;
+        mtd->priv       = chip;
+        mtd->owner      = THIS_MODULE;
+        mtd->name       = "jz4740-nand";
+
+        chip->ecc.hwctl         = jz_nand_hwctl;
+        chip->ecc.calculate     = jz_nand_calculate_ecc_rs;
+        chip->ecc.correct       = jz_nand_correct_ecc_rs;
+        chip->ecc.mode          = NAND_ECC_HW_OOB_FIRST;
+        chip->ecc.size          = 512;
+        chip->ecc.bytes         = 9;
+
+        chip->ecc.read_page     = jz_nand_read_page_hwecc_oob_first;
+        chip->ecc.write_page    = jz_nand_write_page_hwecc;
+
+        if (pdata)
+                chip->ecc.layout = pdata->ecc_layout;
+
+        chip->chip_delay = 50;
+        chip->cmd_ctrl = jz_nand_cmd_ctrl;
+
+        if (pdata && gpio_is_valid(pdata->busy_gpio))
+                chip->dev_ready = jz_nand_dev_ready;
+
+        chip->IO_ADDR_R = nand->bank_base;
+        chip->IO_ADDR_W = nand->bank_base;
+
+        nand->pdata = pdata;
+        platform_set_drvdata(pdev, nand);
+
+        writel(JZ_NAND_CTRL_ENABLE_CHIP(0), nand->base + JZ_REG_NAND_CTRL);
+
+        ret = nand_scan_ident(mtd, 1, NULL);
+        if (ret) {
+                dev_err(&pdev->dev,  "Failed to scan nand\n");
+                goto err_gpio_free;
+        }
+
+        if (pdata && pdata->ident_callback) {
+                pdata->ident_callback(pdev, chip, &pdata->partitions,
+                                        &pdata->num_partitions);
+        }
+
+        ret = nand_scan_tail(mtd);
+        if (ret) {
+                dev_err(&pdev->dev,  "Failed to scan nand\n");
+                goto err_gpio_free;
+        }
+
+#ifdef CONFIG_MTD_PARTITIONS
+#ifdef CONFIG_MTD_CMDLINE_PARTS
+        num_partitions = parse_mtd_partitions(mtd, part_probes,
+                                                &partition_info, 0);
+#endif
+        if (num_partitions <= 0 && pdata) {
+                num_partitions = pdata->num_partitions;
+                partition_info = pdata->partitions;
+        }
+
+        if (num_partitions > 0)
+                ret = add_mtd_partitions(mtd, partition_info, num_partitions);
+        else
+#endif
+        ret = add_mtd_device(mtd);
+
+        if (ret) {
+                dev_err(&pdev->dev, "Failed to add mtd device\n");
+                goto err_nand_release;
+        }
+
+        dev_info(&pdev->dev, "Successfully registered JZ4740 NAND driver\n");
+
+        return 0;
+
+err_nand_release:
+        nand_release(&nand->mtd);
+err_gpio_free:
+        platform_set_drvdata(pdev, NULL);
+        gpio_free(pdata->busy_gpio);
+err_iounmap_mem:
+        iounmap(nand->bank_base);
+err_iounmap_mmio:
+        iounmap(nand->base);
+err_free:
+        kfree(nand);
+        return ret;
+}
+
+static int __devexit jz_nand_remove(struct platform_device *pdev)
+{
+        struct jz_nand *nand = platform_get_drvdata(pdev);
+
+        nand_release(&nand->mtd);
+
+        /* Deassert and disable all chips */
+        writel(0, nand->base + JZ_REG_NAND_CTRL);
+
+        iounmap(nand->bank_base);
+        release_mem_region(nand->bank_mem->start, resource_size(nand->bank_mem));
+        iounmap(nand->base);
+        release_mem_region(nand->mem->start, resource_size(nand->mem));
+
+        platform_set_drvdata(pdev, NULL);
+        kfree(nand);
+
+        return 0;
+}
+
+struct platform_driver jz_nand_driver = {
+        .probe = jz_nand_probe,
+        .remove = __devexit_p(jz_nand_remove),
+        .driver = {
+                .name = "jz4740-nand",
+                .owner = THIS_MODULE,
+        },
+};
+
+static int __init jz_nand_init(void)
+{
+        return platform_driver_register(&jz_nand_driver);
+}
+module_init(jz_nand_init);
+
+static void __exit jz_nand_exit(void)
+{
+        platform_driver_unregister(&jz_nand_driver);
+}
+module_exit(jz_nand_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
+MODULE_DESCRIPTION("NAND controller driver for JZ4740 SoC");
+MODULE_ALIAS("platform:jz4740-nand");
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index ebe68395ecf8..5a6895320b48 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -484,7 +484,7 @@ config XTENSA_XT2000_SONIC
 
 config MIPS_AU1X00_ENET
         tristate "MIPS AU1000 Ethernet support"
-        depends on SOC_AU1X00
+        depends on MIPS_ALCHEMY
         select PHYLIB
         select CRC32
         help
@@ -914,7 +914,7 @@ config SMC91X
         tristate "SMC 91C9x/91C1xxx support"
         select CRC32
         select MII
-        depends on ARM || REDWOOD_5 || REDWOOD_6 || M32R || SUPERH || \
+        depends on ARM || M32R || SUPERH || \
                 MIPS || BLACKFIN || MN10300 || COLDFIRE
         help
           This is a driver for SMC's 91x series of Ethernet chipsets,
diff --git a/drivers/net/au1000_eth.c b/drivers/net/au1000_eth.c
index 386d4feec652..15ae6df2ff00 100644
--- a/drivers/net/au1000_eth.c
+++ b/drivers/net/au1000_eth.c
@@ -104,14 +104,6 @@ MODULE_VERSION(DRV_VERSION);
  * complete immediately.
  */
 
-/* These addresses are only used if yamon doesn't tell us what
- * the mac address is, and the mac address is not passed on the
- * command line.
- */
-static unsigned char au1000_mac_addr[6] __devinitdata = {
-        0x00, 0x50, 0xc2, 0x0c, 0x30, 0x00
-};
-
 struct au1000_private *au_macs[NUM_ETH_INTERFACES];
 
 /*
@@ -1002,7 +994,6 @@ static int __devinit au1000_probe(struct platform_device *pdev)
         db_dest_t *pDB, *pDBfree;
         int irq, i, err = 0;
         struct resource *base, *macen;
-        char ethaddr[6];
 
         base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
         if (!base) {
@@ -1079,24 +1070,13 @@ static int __devinit au1000_probe(struct platform_device *pdev)
         }
         aup->mac_id = pdev->id;
 
-        if (pdev->id == 0) {
-                if (prom_get_ethernet_addr(ethaddr) == 0)
-                        memcpy(au1000_mac_addr, ethaddr, sizeof(au1000_mac_addr));
-                else {
-                        netdev_info(dev, "No MAC address found\n");
-                                /* Use the hard coded MAC addresses */
-                }
-
+        if (pdev->id == 0)
                 au1000_setup_hw_rings(aup, MAC0_RX_DMA_ADDR, MAC0_TX_DMA_ADDR);
-        } else if (pdev->id == 1)
+        else if (pdev->id == 1)
                 au1000_setup_hw_rings(aup, MAC1_RX_DMA_ADDR, MAC1_TX_DMA_ADDR);
 
-        /*
-         * Assign to the Ethernet ports two consecutive MAC addresses
-         * to match those that are printed on their stickers
-         */
-        memcpy(dev->dev_addr, au1000_mac_addr, sizeof(au1000_mac_addr));
-        dev->dev_addr[5] += pdev->id;
+        /* set a random MAC now in case platform_data doesn't provide one */
+        random_ether_addr(dev->dev_addr);
 
         *aup->enable = 0;
         aup->mac_enabled = 0;
@@ -1106,6 +1086,9 @@ static int __devinit au1000_probe(struct platform_device *pdev)
                 dev_info(&pdev->dev, "no platform_data passed, PHY search on MAC0\n");
                 aup->phy1_search_mac0 = 1;
         } else {
+                if (is_valid_ether_addr(pd->mac))
+                        memcpy(dev->dev_addr, pd->mac, 6);
+
                 aup->phy_static_config = pd->phy_static_config;
                 aup->phy_search_highest_addr = pd->phy_search_highest_addr;
                 aup->phy1_search_mac0 = pd->phy1_search_mac0;
diff --git a/drivers/net/smc91x.h b/drivers/net/smc91x.h
index 8d2772cc42f2..ee747919a766 100644
--- a/drivers/net/smc91x.h
+++ b/drivers/net/smc91x.h
@@ -83,43 +83,6 @@ static inline void SMC_outw(u16 val, void __iomem *ioaddr, int reg)
         }
 }
 
-#elif defined(CONFIG_REDWOOD_5) || defined(CONFIG_REDWOOD_6)
-
-/* We can only do 16-bit reads and writes in the static memory space. */
-#define SMC_CAN_USE_8BIT        0
-#define SMC_CAN_USE_16BIT       1
-#define SMC_CAN_USE_32BIT       0
-#define SMC_NOWAIT              1
-
-#define SMC_IO_SHIFT            0
-
-#define SMC_inw(a, r)           in_be16((volatile u16 *)((a) + (r)))
-#define SMC_outw(v, a, r)       out_be16((volatile u16 *)((a) + (r)), v)
-#define SMC_insw(a, r, p, l)                                            \
-        do {                                                            \
-                unsigned long __port = (a) + (r);                       \
-                u16 *__p = (u16 *)(p);                                  \
-                int __l = (l);                                          \
-                insw(__port, __p, __l);                                 \
-                while (__l > 0) {                                       \
-                        *__p = swab16(*__p);                            \
-                        __p++;                                          \
-                        __l--;                                          \
-                }                                                       \
-        } while (0)
-#define SMC_outsw(a, r, p, l)                                           \
-        do {                                                            \
-                unsigned long __port = (a) + (r);                       \
-                u16 *__p = (u16 *)(p);                                  \
-                int __l = (l);                                          \
-                while (__l > 0) {                                       \
-                        /* Believe it or not, the swab isn't needed. */ \
-                        outw( /* swab16 */ (*__p++), __port);           \
-                        __l--;                                          \
-                }                                                       \
-        } while (0)
-#define SMC_IRQ_FLAGS           (0)
-
 #elif defined(CONFIG_SA1100_PLEB)
 /* We can only do 16-bit reads and writes in the static memory space. */
 #define SMC_CAN_USE_8BIT        1
diff --git a/drivers/pcmcia/Kconfig b/drivers/pcmcia/Kconfig
index d0f5ad306078..c988514eb551 100644
--- a/drivers/pcmcia/Kconfig
+++ b/drivers/pcmcia/Kconfig
@@ -157,11 +157,11 @@ config PCMCIA_M8XX
 
 config PCMCIA_AU1X00
         tristate "Au1x00 pcmcia support"
-        depends on SOC_AU1X00 && PCMCIA
+        depends on MIPS_ALCHEMY && PCMCIA
 
 config PCMCIA_ALCHEMY_DEVBOARD
         tristate "Alchemy Db/Pb1xxx PCMCIA socket services"
-        depends on SOC_AU1X00 && PCMCIA
+        depends on MIPS_ALCHEMY && PCMCIA
         select 64BIT_PHYS_ADDR
         help
           Enable this driver of you want PCMCIA support on your Alchemy
diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
index 8e9ba177d817..1e5506be39b4 100644
--- a/drivers/power/Kconfig
+++ b/drivers/power/Kconfig
@@ -142,4 +142,15 @@ config CHARGER_PCF50633
         help
          Say Y to include support for NXP PCF50633 Main Battery Charger.
 
+config BATTERY_JZ4740
+        tristate "Ingenic JZ4740 battery"
+        depends on MACH_JZ4740
+        depends on MFD_JZ4740_ADC
+        help
+          Say Y to enable support for the battery on Ingenic JZ4740 based
+          boards.
+
+          This driver can be build as a module. If so, the module will be
+          called jz4740-battery.
+
 endif # POWER_SUPPLY
diff --git a/drivers/power/Makefile b/drivers/power/Makefile
index 00050809a6c7..cf95009d9bcd 100644
--- a/drivers/power/Makefile
+++ b/drivers/power/Makefile
@@ -34,3 +34,4 @@ obj-$(CONFIG_BATTERY_DA9030)	+= da9030_battery.o
 obj-$(CONFIG_BATTERY_MAX17040)  += max17040_battery.o
 obj-$(CONFIG_BATTERY_Z2)        += z2_battery.o
 obj-$(CONFIG_CHARGER_PCF50633)  += pcf50633-charger.o
+obj-$(CONFIG_BATTERY_JZ4740)    += jz4740-battery.o
diff --git a/drivers/power/jz4740-battery.c b/drivers/power/jz4740-battery.c
new file mode 100644
index 000000000000..20c4b952e9bd
--- /dev/null
+++ b/drivers/power/jz4740-battery.c
@@ -0,0 +1,445 @@
+/*
+ * Battery measurement code for Ingenic JZ SOC.
+ *
+ * Copyright (C) 2009 Jiejing Zhang <kzjeef@gmail.com>
+ * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ *
+ * based on tosa_battery.c
+ *
+ * Copyright (C) 2008 Marek Vasut <marek.vasut@gmail.com>
+*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/mfd/core.h>
+#include <linux/power_supply.h>
+
+#include <linux/power/jz4740-battery.h>
+#include <linux/jz4740-adc.h>
+
+struct jz_battery {
+        struct jz_battery_platform_data *pdata;
+        struct platform_device *pdev;
+
+        struct resource *mem;
+        void __iomem *base;
+
+        int irq;
+        int charge_irq;
+
+        struct mfd_cell *cell;
+
+        int status;
+        long voltage;
+
+        struct completion read_completion;
+
+        struct power_supply battery;
+        struct delayed_work work;
+};
+
+static inline struct jz_battery *psy_to_jz_battery(struct power_supply *psy)
+{
+        return container_of(psy, struct jz_battery, battery);
+}
+
+static irqreturn_t jz_battery_irq_handler(int irq, void *devid)
+{
+        struct jz_battery *battery = devid;
+
+        complete(&battery->read_completion);
+        return IRQ_HANDLED;
+}
+
+static long jz_battery_read_voltage(struct jz_battery *battery)
+{
+        unsigned long t;
+        unsigned long val;
+        long voltage;
+
+        INIT_COMPLETION(battery->read_completion);
+
+        enable_irq(battery->irq);
+        battery->cell->enable(battery->pdev);
+
+        t = wait_for_completion_interruptible_timeout(&battery->read_completion,
+                HZ);
+
+        if (t > 0) {
+                val = readw(battery->base) & 0xfff;
+
+                if (battery->pdata->info.voltage_max_design <= 2500000)
+                        val = (val * 78125UL) >> 7UL;
+                else
+                        val = ((val * 924375UL) >> 9UL) + 33000;
+                voltage = (long)val;
+        } else {
+                voltage = t ? t : -ETIMEDOUT;
+        }
+
+        battery->cell->disable(battery->pdev);
+        disable_irq(battery->irq);
+
+        return voltage;
+}
+
+static int jz_battery_get_capacity(struct power_supply *psy)
+{
+        struct jz_battery *jz_battery = psy_to_jz_battery(psy);
+        struct power_supply_info *info = &jz_battery->pdata->info;
+        long voltage;
+        int ret;
+        int voltage_span;
+
+        voltage = jz_battery_read_voltage(jz_battery);
+
+        if (voltage < 0)
+                return voltage;
+
+        voltage_span = info->voltage_max_design - info->voltage_min_design;
+        ret = ((voltage - info->voltage_min_design) * 100) / voltage_span;
+
+        if (ret > 100)
+                ret = 100;
+        else if (ret < 0)
+                ret = 0;
+
+        return ret;
+}
+
+static int jz_battery_get_property(struct power_supply *psy,
+        enum power_supply_property psp, union power_supply_propval *val)
+{
+        struct jz_battery *jz_battery = psy_to_jz_battery(psy);
+        struct power_supply_info *info = &jz_battery->pdata->info;
+        long voltage;
+
+        switch (psp) {
+        case POWER_SUPPLY_PROP_STATUS:
+                val->intval = jz_battery->status;
+                break;
+        case POWER_SUPPLY_PROP_TECHNOLOGY:
+                val->intval = jz_battery->pdata->info.technology;
+                break;
+        case POWER_SUPPLY_PROP_HEALTH:
+                voltage = jz_battery_read_voltage(jz_battery);
+                if (voltage < info->voltage_min_design)
+                        val->intval = POWER_SUPPLY_HEALTH_DEAD;
+                else
+                        val->intval = POWER_SUPPLY_HEALTH_GOOD;
+                break;
+        case POWER_SUPPLY_PROP_CAPACITY:
+                val->intval = jz_battery_get_capacity(psy);
+                break;
+        case POWER_SUPPLY_PROP_VOLTAGE_NOW:
+                val->intval = jz_battery_read_voltage(jz_battery);
+                if (val->intval < 0)
+                        return val->intval;
+                break;
+        case POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN:
+                val->intval = info->voltage_max_design;
+                break;
+        case POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN:
+                val->intval = info->voltage_min_design;
+                break;
+        case POWER_SUPPLY_PROP_PRESENT:
+                val->intval = 1;
+                break;
+        default:
+                return -EINVAL;
+        }
+        return 0;
+}
+
+static void jz_battery_external_power_changed(struct power_supply *psy)
+{
+        struct jz_battery *jz_battery = psy_to_jz_battery(psy);
+
+        cancel_delayed_work(&jz_battery->work);
+        schedule_delayed_work(&jz_battery->work, 0);
+}
+
+static irqreturn_t jz_battery_charge_irq(int irq, void *data)
+{
+        struct jz_battery *jz_battery = data;
+
+        cancel_delayed_work(&jz_battery->work);
+        schedule_delayed_work(&jz_battery->work, 0);
+
+        return IRQ_HANDLED;
+}
+
+static void jz_battery_update(struct jz_battery *jz_battery)
+{
+        int status;
+        long voltage;
+        bool has_changed = false;
+        int is_charging;
+
+        if (gpio_is_valid(jz_battery->pdata->gpio_charge)) {
+                is_charging = gpio_get_value(jz_battery->pdata->gpio_charge);
+                is_charging ^= jz_battery->pdata->gpio_charge_active_low;
+                if (is_charging)
+                        status = POWER_SUPPLY_STATUS_CHARGING;
+                else
+                        status = POWER_SUPPLY_STATUS_NOT_CHARGING;
+
+                if (status != jz_battery->status) {
+                        jz_battery->status = status;
+                        has_changed = true;
+                }
+        }
+
+        voltage = jz_battery_read_voltage(jz_battery);
+        if (abs(voltage - jz_battery->voltage) < 50000) {
+                jz_battery->voltage = voltage;
+                has_changed = true;
+        }
+
+        if (has_changed)
+                power_supply_changed(&jz_battery->battery);
+}
+
+static enum power_supply_property jz_battery_properties[] = {
+        POWER_SUPPLY_PROP_STATUS,
+        POWER_SUPPLY_PROP_TECHNOLOGY,
+        POWER_SUPPLY_PROP_HEALTH,
+        POWER_SUPPLY_PROP_CAPACITY,
+        POWER_SUPPLY_PROP_VOLTAGE_NOW,
+        POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN,
+        POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN,
+        POWER_SUPPLY_PROP_PRESENT,
+};
+
+static void jz_battery_work(struct work_struct *work)
+{
+        /* Too small interval will increase system workload */
+        const int interval = HZ * 30;
+        struct jz_battery *jz_battery = container_of(work, struct jz_battery,
+                                            work.work);
+
+        jz_battery_update(jz_battery);
+        schedule_delayed_work(&jz_battery->work, interval);
+}
+
+static int __devinit jz_battery_probe(struct platform_device *pdev)
+{
+        int ret = 0;
+        struct jz_battery_platform_data *pdata = pdev->dev.parent->platform_data;
+        struct jz_battery *jz_battery;
+        struct power_supply *battery;
+
+        jz_battery = kzalloc(sizeof(*jz_battery), GFP_KERNEL);
+        if (!jz_battery) {
+                dev_err(&pdev->dev, "Failed to allocate driver structure\n");
+                return -ENOMEM;
+        }
+
+        jz_battery->cell = pdev->dev.platform_data;
+
+        jz_battery->irq = platform_get_irq(pdev, 0);
+        if (jz_battery->irq < 0) {
+                ret = jz_battery->irq;
+                dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret);
+                goto err_free;
+        }
+
+        jz_battery->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!jz_battery->mem) {
+                ret = -ENOENT;
+                dev_err(&pdev->dev, "Failed to get platform mmio resource\n");
+                goto err_free;
+        }
+
+        jz_battery->mem = request_mem_region(jz_battery->mem->start,
+                                resource_size(jz_battery->mem), pdev->name);
+        if (!jz_battery->mem) {
+                ret = -EBUSY;
+                dev_err(&pdev->dev, "Failed to request mmio memory region\n");
+                goto err_free;
+        }
+
+        jz_battery->base = ioremap_nocache(jz_battery->mem->start,
+                                resource_size(jz_battery->mem));
+        if (!jz_battery->base) {
+                ret = -EBUSY;
+                dev_err(&pdev->dev, "Failed to ioremap mmio memory\n");
+                goto err_release_mem_region;
+        }
+
+        battery = &jz_battery->battery;
+        battery->name = pdata->info.name;
+        battery->type = POWER_SUPPLY_TYPE_BATTERY;
+        battery->properties     = jz_battery_properties;
+        battery->num_properties = ARRAY_SIZE(jz_battery_properties);
+        battery->get_property = jz_battery_get_property;
+        battery->external_power_changed = jz_battery_external_power_changed;
+        battery->use_for_apm = 1;
+
+        jz_battery->pdata = pdata;
+        jz_battery->pdev = pdev;
+
+        init_completion(&jz_battery->read_completion);
+
+        INIT_DELAYED_WORK(&jz_battery->work, jz_battery_work);
+
+        ret = request_irq(jz_battery->irq, jz_battery_irq_handler, 0, pdev->name,
+                        jz_battery);
+        if (ret) {
+                dev_err(&pdev->dev, "Failed to request irq %d\n", ret);
+                goto err_iounmap;
+        }
+        disable_irq(jz_battery->irq);
+
+        if (gpio_is_valid(pdata->gpio_charge)) {
+                ret = gpio_request(pdata->gpio_charge, dev_name(&pdev->dev));
+                if (ret) {
+                        dev_err(&pdev->dev, "charger state gpio request failed.\n");
+                        goto err_free_irq;
+                }
+                ret = gpio_direction_input(pdata->gpio_charge);
+                if (ret) {
+                        dev_err(&pdev->dev, "charger state gpio set direction failed.\n");
+                        goto err_free_gpio;
+                }
+
+                jz_battery->charge_irq = gpio_to_irq(pdata->gpio_charge);
+
+                if (jz_battery->charge_irq >= 0) {
+                        ret = request_irq(jz_battery->charge_irq,
+                                    jz_battery_charge_irq,
+                                    IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
+                                    dev_name(&pdev->dev), jz_battery);
+                        if (ret) {
+                                dev_err(&pdev->dev, "Failed to request charge irq: %d\n", ret);
+                                goto err_free_gpio;
+                        }
+                }
+        } else {
+                jz_battery->charge_irq = -1;
+        }
+
+        if (jz_battery->pdata->info.voltage_max_design <= 2500000)
+                jz4740_adc_set_config(pdev->dev.parent, JZ_ADC_CONFIG_BAT_MB,
+                        JZ_ADC_CONFIG_BAT_MB);
+        else
+                jz4740_adc_set_config(pdev->dev.parent, JZ_ADC_CONFIG_BAT_MB, 0);
+
+        ret = power_supply_register(&pdev->dev, &jz_battery->battery);
+        if (ret) {
+                dev_err(&pdev->dev, "power supply battery register failed.\n");
+                goto err_free_charge_irq;
+        }
+
+        platform_set_drvdata(pdev, jz_battery);
+        schedule_delayed_work(&jz_battery->work, 0);
+
+        return 0;
+
+err_free_charge_irq:
+        if (jz_battery->charge_irq >= 0)
+                free_irq(jz_battery->charge_irq, jz_battery);
+err_free_gpio:
+        if (gpio_is_valid(pdata->gpio_charge))
+                gpio_free(jz_battery->pdata->gpio_charge);
+err_free_irq:
+        free_irq(jz_battery->irq, jz_battery);
+err_iounmap:
+        platform_set_drvdata(pdev, NULL);
+        iounmap(jz_battery->base);
+err_release_mem_region:
+        release_mem_region(jz_battery->mem->start, resource_size(jz_battery->mem));
+err_free:
+        kfree(jz_battery);
+        return ret;
+}
+
+static int __devexit jz_battery_remove(struct platform_device *pdev)
+{
+        struct jz_battery *jz_battery = platform_get_drvdata(pdev);
+
+        cancel_delayed_work_sync(&jz_battery->work);
+
+        if (gpio_is_valid(jz_battery->pdata->gpio_charge)) {
+                if (jz_battery->charge_irq >= 0)
+                        free_irq(jz_battery->charge_irq, jz_battery);
+                gpio_free(jz_battery->pdata->gpio_charge);
+        }
+
+        power_supply_unregister(&jz_battery->battery);
+
+        free_irq(jz_battery->irq, jz_battery);
+
+        iounmap(jz_battery->base);
+        release_mem_region(jz_battery->mem->start, resource_size(jz_battery->mem));
+
+        return 0;
+}
+
+#ifdef CONFIG_PM
+static int jz_battery_suspend(struct device *dev)
+{
+        struct jz_battery *jz_battery = dev_get_drvdata(dev);
+
+        cancel_delayed_work_sync(&jz_battery->work);
+        jz_battery->status = POWER_SUPPLY_STATUS_UNKNOWN;
+
+        return 0;
+}
+
+static int jz_battery_resume(struct device *dev)
+{
+        struct jz_battery *jz_battery = dev_get_drvdata(dev);
+
+        schedule_delayed_work(&jz_battery->work, 0);
+
+        return 0;
+}
+
+static const struct dev_pm_ops jz_battery_pm_ops = {
+        .suspend        = jz_battery_suspend,
+        .resume         = jz_battery_resume,
+};
+
+#define JZ_BATTERY_PM_OPS (&jz_battery_pm_ops)
+#else
+#define JZ_BATTERY_PM_OPS NULL
+#endif
+
+static struct platform_driver jz_battery_driver = {
+        .probe          = jz_battery_probe,
+        .remove         = __devexit_p(jz_battery_remove),
+        .driver = {
+                .name = "jz4740-battery",
+                .owner = THIS_MODULE,
+                .pm = JZ_BATTERY_PM_OPS,
+        },
+};
+
+static int __init jz_battery_init(void)
+{
+        return platform_driver_register(&jz_battery_driver);
+}
+module_init(jz_battery_init);
+
+static void __exit jz_battery_exit(void)
+{
+        platform_driver_unregister(&jz_battery_driver);
+}
+module_exit(jz_battery_exit);
+
+MODULE_ALIAS("platform:jz4740-battery");
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
+MODULE_DESCRIPTION("JZ4740 SoC battery driver");
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 10ba12c8c5e0..4301a6c7ed3b 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -774,7 +774,7 @@ config RTC_DRV_AT91SAM9_GPBR
 
 config RTC_DRV_AU1XXX
         tristate "Au1xxx Counter0 RTC support"
-        depends on SOC_AU1X00
+        depends on MIPS_ALCHEMY
         help
           This is a driver for the Au1xxx on-chip Counter0 (Time-Of-Year
           counter) to be used as a RTC.
@@ -905,4 +905,15 @@ config RTC_DRV_MPC5121
           This driver can also be built as a module. If so, the module
           will be called rtc-mpc5121.
 
+config RTC_DRV_JZ4740
+        tristate "Ingenic JZ4740 SoC"
+        depends on RTC_CLASS
+        depends on MACH_JZ4740
+        help
+          If you say yes here you get support for the Ingenic JZ4740 SoC RTC
+          controller.
+
+          This driver can also be buillt as a module. If so, the module
+          will be called rtc-jz4740.
+
 endif # RTC_CLASS
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 5adbba7cf89c..fedf9bb36593 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -47,6 +47,7 @@ obj-$(CONFIG_RTC_DRV_EP93XX)	+= rtc-ep93xx.o
 obj-$(CONFIG_RTC_DRV_FM3130)    += rtc-fm3130.o
 obj-$(CONFIG_RTC_DRV_GENERIC)   += rtc-generic.o
 obj-$(CONFIG_RTC_DRV_ISL1208)   += rtc-isl1208.o
+obj-$(CONFIG_RTC_DRV_JZ4740)    += rtc-jz4740.o
 obj-$(CONFIG_RTC_DRV_M41T80)    += rtc-m41t80.o
 obj-$(CONFIG_RTC_DRV_M41T94)    += rtc-m41t94.o
 obj-$(CONFIG_RTC_DRV_M48T35)    += rtc-m48t35.o
diff --git a/drivers/rtc/rtc-jz4740.c b/drivers/rtc/rtc-jz4740.c
new file mode 100644
index 000000000000..2619d57b91d7
--- /dev/null
+++ b/drivers/rtc/rtc-jz4740.c
@@ -0,0 +1,345 @@
+/*
+ *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
+ *       JZ4740 SoC RTC driver
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under  the terms of  the GNU General Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/rtc.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+
+#define JZ_REG_RTC_CTRL         0x00
+#define JZ_REG_RTC_SEC          0x04
+#define JZ_REG_RTC_SEC_ALARM    0x08
+#define JZ_REG_RTC_REGULATOR    0x0C
+#define JZ_REG_RTC_HIBERNATE    0x20
+#define JZ_REG_RTC_SCRATCHPAD   0x34
+
+#define JZ_RTC_CTRL_WRDY        BIT(7)
+#define JZ_RTC_CTRL_1HZ         BIT(6)
+#define JZ_RTC_CTRL_1HZ_IRQ     BIT(5)
+#define JZ_RTC_CTRL_AF          BIT(4)
+#define JZ_RTC_CTRL_AF_IRQ      BIT(3)
+#define JZ_RTC_CTRL_AE          BIT(2)
+#define JZ_RTC_CTRL_ENABLE      BIT(0)
+
+struct jz4740_rtc {
+        struct resource *mem;
+        void __iomem *base;
+
+        struct rtc_device *rtc;
+
+        unsigned int irq;
+
+        spinlock_t lock;
+};
+
+static inline uint32_t jz4740_rtc_reg_read(struct jz4740_rtc *rtc, size_t reg)
+{
+        return readl(rtc->base + reg);
+}
+
+static int jz4740_rtc_wait_write_ready(struct jz4740_rtc *rtc)
+{
+        uint32_t ctrl;
+        int timeout = 1000;
+
+        do {
+                ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
+        } while (!(ctrl & JZ_RTC_CTRL_WRDY) && --timeout);
+
+        return timeout ? 0 : -EIO;
+}
+
+static inline int jz4740_rtc_reg_write(struct jz4740_rtc *rtc, size_t reg,
+        uint32_t val)
+{
+        int ret;
+        ret = jz4740_rtc_wait_write_ready(rtc);
+        if (ret == 0)
+                writel(val, rtc->base + reg);
+
+        return ret;
+}
+
+static int jz4740_rtc_ctrl_set_bits(struct jz4740_rtc *rtc, uint32_t mask,
+        bool set)
+{
+        int ret;
+        unsigned long flags;
+        uint32_t ctrl;
+
+        spin_lock_irqsave(&rtc->lock, flags);
+
+        ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
+
+        /* Don't clear interrupt flags by accident */
+        ctrl |= JZ_RTC_CTRL_1HZ | JZ_RTC_CTRL_AF;
+
+        if (set)
+                ctrl |= mask;
+        else
+                ctrl &= ~mask;
+
+        ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_CTRL, ctrl);
+
+        spin_unlock_irqrestore(&rtc->lock, flags);
+
+        return ret;
+}
+
+static int jz4740_rtc_read_time(struct device *dev, struct rtc_time *time)
+{
+        struct jz4740_rtc *rtc = dev_get_drvdata(dev);
+        uint32_t secs, secs2;
+        int timeout = 5;
+
+        /* If the seconds register is read while it is updated, it can contain a
+         * bogus value. This can be avoided by making sure that two consecutive
+         * reads have the same value.
+         */
+        secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
+        secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
+
+        while (secs != secs2 && --timeout) {
+                secs = secs2;
+                secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
+        }
+
+        if (timeout == 0)
+                return -EIO;
+
+        rtc_time_to_tm(secs, time);
+
+        return rtc_valid_tm(time);
+}
+
+static int jz4740_rtc_set_mmss(struct device *dev, unsigned long secs)
+{
+        struct jz4740_rtc *rtc = dev_get_drvdata(dev);
+
+        return jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC, secs);
+}
+
+static int jz4740_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
+{
+        struct jz4740_rtc *rtc = dev_get_drvdata(dev);
+        uint32_t secs;
+        uint32_t ctrl;
+
+        secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC_ALARM);
+
+        ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
+
+        alrm->enabled = !!(ctrl & JZ_RTC_CTRL_AE);
+        alrm->pending = !!(ctrl & JZ_RTC_CTRL_AF);
+
+        rtc_time_to_tm(secs, &alrm->time);
+
+        return rtc_valid_tm(&alrm->time);
+}
+
+static int jz4740_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
+{
+        int ret;
+        struct jz4740_rtc *rtc = dev_get_drvdata(dev);
+        unsigned long secs;
+
+        rtc_tm_to_time(&alrm->time, &secs);
+
+        ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC_ALARM, secs);
+        if (!ret)
+                ret = jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_AE, alrm->enabled);
+
+        return ret;
+}
+
+static int jz4740_rtc_update_irq_enable(struct device *dev, unsigned int enable)
+{
+        struct jz4740_rtc *rtc = dev_get_drvdata(dev);
+        return jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_1HZ_IRQ, enable);
+}
+
+static int jz4740_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
+{
+        struct jz4740_rtc *rtc = dev_get_drvdata(dev);
+        return jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_AF_IRQ, enable);
+}
+
+static struct rtc_class_ops jz4740_rtc_ops = {
+        .read_time      = jz4740_rtc_read_time,
+        .set_mmss       = jz4740_rtc_set_mmss,
+        .read_alarm     = jz4740_rtc_read_alarm,
+        .set_alarm      = jz4740_rtc_set_alarm,
+        .update_irq_enable = jz4740_rtc_update_irq_enable,
+        .alarm_irq_enable = jz4740_rtc_alarm_irq_enable,
+};
+
+static irqreturn_t jz4740_rtc_irq(int irq, void *data)
+{
+        struct jz4740_rtc *rtc = data;
+        uint32_t ctrl;
+        unsigned long events = 0;
+
+        ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
+
+        if (ctrl & JZ_RTC_CTRL_1HZ)
+                events |= (RTC_UF | RTC_IRQF);
+
+        if (ctrl & JZ_RTC_CTRL_AF)
+                events |= (RTC_AF | RTC_IRQF);
+
+        rtc_update_irq(rtc->rtc, 1, events);
+
+        jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_1HZ | JZ_RTC_CTRL_AF, false);
+
+        return IRQ_HANDLED;
+}
+
+void jz4740_rtc_poweroff(struct device *dev)
+{
+        struct jz4740_rtc *rtc = dev_get_drvdata(dev);
+        jz4740_rtc_reg_write(rtc, JZ_REG_RTC_HIBERNATE, 1);
+}
+EXPORT_SYMBOL_GPL(jz4740_rtc_poweroff);
+
+static int __devinit jz4740_rtc_probe(struct platform_device *pdev)
+{
+        int ret;
+        struct jz4740_rtc *rtc;
+        uint32_t scratchpad;
+
+        rtc = kzalloc(sizeof(*rtc), GFP_KERNEL);
+        if (!rtc)
+                return -ENOMEM;
+
+        rtc->irq = platform_get_irq(pdev, 0);
+        if (rtc->irq < 0) {
+                ret = -ENOENT;
+                dev_err(&pdev->dev, "Failed to get platform irq\n");
+                goto err_free;
+        }
+
+        rtc->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!rtc->mem) {
+                ret = -ENOENT;
+                dev_err(&pdev->dev, "Failed to get platform mmio memory\n");
+                goto err_free;
+        }
+
+        rtc->mem = request_mem_region(rtc->mem->start, resource_size(rtc->mem),
+                                        pdev->name);
+        if (!rtc->mem) {
+                ret = -EBUSY;
+                dev_err(&pdev->dev, "Failed to request mmio memory region\n");
+                goto err_free;
+        }
+
+        rtc->base = ioremap_nocache(rtc->mem->start, resource_size(rtc->mem));
+        if (!rtc->base) {
+                ret = -EBUSY;
+                dev_err(&pdev->dev, "Failed to ioremap mmio memory\n");
+                goto err_release_mem_region;
+        }
+
+        spin_lock_init(&rtc->lock);
+
+        platform_set_drvdata(pdev, rtc);
+
+        rtc->rtc = rtc_device_register(pdev->name, &pdev->dev, &jz4740_rtc_ops,
+                                        THIS_MODULE);
+        if (IS_ERR(rtc->rtc)) {
+                ret = PTR_ERR(rtc->rtc);
+                dev_err(&pdev->dev, "Failed to register rtc device: %d\n", ret);
+                goto err_iounmap;
+        }
+
+        ret = request_irq(rtc->irq, jz4740_rtc_irq, 0,
+                                pdev->name, rtc);
+        if (ret) {
+                dev_err(&pdev->dev, "Failed to request rtc irq: %d\n", ret);
+                goto err_unregister_rtc;
+        }
+
+        scratchpad = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SCRATCHPAD);
+        if (scratchpad != 0x12345678) {
+                ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SCRATCHPAD, 0x12345678);
+                ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC, 0);
+                if (ret) {
+                        dev_err(&pdev->dev, "Could not write write to RTC registers\n");
+                        goto err_free_irq;
+                }
+        }
+
+        return 0;
+
+err_free_irq:
+        free_irq(rtc->irq, rtc);
+err_unregister_rtc:
+        rtc_device_unregister(rtc->rtc);
+err_iounmap:
+        platform_set_drvdata(pdev, NULL);
+        iounmap(rtc->base);
+err_release_mem_region:
+        release_mem_region(rtc->mem->start, resource_size(rtc->mem));
+err_free:
+        kfree(rtc);
+
+        return ret;
+}
+
+static int __devexit jz4740_rtc_remove(struct platform_device *pdev)
+{
+        struct jz4740_rtc *rtc = platform_get_drvdata(pdev);
+
+        free_irq(rtc->irq, rtc);
+
+        rtc_device_unregister(rtc->rtc);
+
+        iounmap(rtc->base);
+        release_mem_region(rtc->mem->start, resource_size(rtc->mem));
+
+        kfree(rtc);
+
+        platform_set_drvdata(pdev, NULL);
+
+        return 0;
+}
+
+struct platform_driver jz4740_rtc_driver = {
+        .probe = jz4740_rtc_probe,
+        .remove = __devexit_p(jz4740_rtc_remove),
+        .driver = {
+                .name = "jz4740-rtc",
+                .owner = THIS_MODULE,
+        },
+};
+
+static int __init jz4740_rtc_init(void)
+{
+        return platform_driver_register(&jz4740_rtc_driver);
+}
+module_init(jz4740_rtc_init);
+
+static void __exit jz4740_rtc_exit(void)
+{
+        platform_driver_unregister(&jz4740_rtc_driver);
+}
+module_exit(jz4740_rtc_exit);
+
+MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("RTC driver for the JZ4740 SoC\n");
+MODULE_ALIAS("platform:jz4740-rtc");
diff --git a/drivers/sbus/char/display7seg.c b/drivers/sbus/char/display7seg.c
index 7baf1b644039..4ad4d2c91075 100644
--- a/drivers/sbus/char/display7seg.c
+++ b/drivers/sbus/char/display7seg.c
@@ -13,7 +13,7 @@
 #include <linux/miscdevice.h>
 #include <linux/ioport.h>               /* request_region */
 #include <linux/slab.h>
-#include <linux/smp_lock.h>
+#include <linux/mutex.h>
 #include <linux/of.h>
 #include <linux/of_device.h>
 #include <asm/atomic.h>
@@ -26,6 +26,7 @@
 #define DRIVER_NAME     "d7s"
 #define PFX             DRIVER_NAME ": "
 
+static DEFINE_MUTEX(d7s_mutex);
 static int sol_compat = 0;              /* Solaris compatibility mode   */
 
 /* Solaris compatibility flag -
@@ -74,7 +75,6 @@ static int d7s_open(struct inode *inode, struct file *f)
 {
         if (D7S_MINOR != iminor(inode))
                 return -ENODEV;
-        cycle_kernel_lock();
         atomic_inc(&d7s_users);
         return 0;
 }
@@ -110,7 +110,7 @@ static long d7s_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
         if (D7S_MINOR != iminor(file->f_path.dentry->d_inode))
                 return -ENODEV;
 
-        lock_kernel();
+        mutex_lock(&d7s_mutex);
         switch (cmd) {
         case D7SIOCWR:
                 /* assign device register values we mask-out D7S_FLIP
@@ -151,7 +151,7 @@ static long d7s_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
                 writeb(regs, p->regs);
                 break;
         };
-        unlock_kernel();
+        mutex_unlock(&d7s_mutex);
 
         return error;
 }
diff --git a/drivers/sbus/char/envctrl.c b/drivers/sbus/char/envctrl.c
index c8166ecf5276..bd0bbc621351 100644
--- a/drivers/sbus/char/envctrl.c
+++ b/drivers/sbus/char/envctrl.c
@@ -27,7 +27,6 @@
 #include <linux/kmod.h>
 #include <linux/reboot.h>
 #include <linux/slab.h>
-#include <linux/smp_lock.h>
 #include <linux/of.h>
 #include <linux/of_device.h>
 
@@ -699,7 +698,6 @@ envctrl_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
 static int
 envctrl_open(struct inode *inode, struct file *file)
 {
-        cycle_kernel_lock();
         file->private_data = NULL;
         return 0;
 }
diff --git a/drivers/sbus/char/flash.c b/drivers/sbus/char/flash.c
index 368d66294d83..ed9494e18859 100644
--- a/drivers/sbus/char/flash.c
+++ b/drivers/sbus/char/flash.c
@@ -10,7 +10,7 @@
 #include <linux/fcntl.h>
 #include <linux/poll.h>
 #include <linux/init.h>
-#include <linux/smp_lock.h>
+#include <linux/mutex.h>
 #include <linux/spinlock.h>
 #include <linux/mm.h>
 #include <linux/of.h>
@@ -22,6 +22,7 @@
 #include <asm/io.h>
 #include <asm/upa.h>
 
+static DEFINE_MUTEX(flash_mutex);
 static DEFINE_SPINLOCK(flash_lock);
 static struct {
         unsigned long read_base;        /* Physical read address */
@@ -80,7 +81,7 @@ flash_mmap(struct file *file, struct vm_area_struct *vma)
 static long long
 flash_llseek(struct file *file, long long offset, int origin)
 {
-        lock_kernel();
+        mutex_lock(&flash_mutex);
         switch (origin) {
                 case 0:
                         file->f_pos = offset;
@@ -94,10 +95,10 @@ flash_llseek(struct file *file, long long offset, int origin)
                         file->f_pos = flash.read_size;
                         break;
                 default:
-                        unlock_kernel();
+                        mutex_unlock(&flash_mutex);
                         return -EINVAL;
         }
-        unlock_kernel();
+        mutex_unlock(&flash_mutex);
         return file->f_pos;
 }
 
@@ -125,13 +126,13 @@ flash_read(struct file * file, char __user * buf,
 static int
 flash_open(struct inode *inode, struct file *file)
 {
-        lock_kernel();
+        mutex_lock(&flash_mutex);
         if (test_and_set_bit(0, (void *)&flash.busy) != 0) {
-                unlock_kernel();
+                mutex_unlock(&flash_mutex);
                 return -EBUSY;
         }
 
-        unlock_kernel();
+        mutex_unlock(&flash_mutex);
         return 0;
 }
 
diff --git a/drivers/sbus/char/openprom.c b/drivers/sbus/char/openprom.c
index aacbe14e2e7a..8d6e508222b8 100644
--- a/drivers/sbus/char/openprom.c
+++ b/drivers/sbus/char/openprom.c
@@ -33,7 +33,7 @@
 #include <linux/kernel.h>
 #include <linux/errno.h>
 #include <linux/slab.h>
-#include <linux/smp_lock.h>
+#include <linux/mutex.h>
 #include <linux/string.h>
 #include <linux/miscdevice.h>
 #include <linux/init.h>
@@ -61,6 +61,7 @@ typedef struct openprom_private_data
 } DATA;
 
 /* ID of the PROM node containing all of the EEPROM options. */
+static DEFINE_MUTEX(openprom_mutex);
 static struct device_node *options_node;
 
 /*
@@ -316,7 +317,7 @@ static long openprom_sunos_ioctl(struct file * file,
         if (bufsize < 0)
                 return bufsize;
 
-        lock_kernel();
+        mutex_lock(&openprom_mutex);
 
         switch (cmd) {
         case OPROMGETOPT:
@@ -367,7 +368,7 @@ static long openprom_sunos_ioctl(struct file * file,
         }
 
         kfree(opp);
-        unlock_kernel();
+        mutex_unlock(&openprom_mutex);
 
         return error;
 }
@@ -558,7 +559,7 @@ static int openprom_bsd_ioctl(struct file * file,
         void __user *argp = (void __user *)arg;
         int err;
 
-        lock_kernel();
+        mutex_lock(&openprom_mutex);
         switch (cmd) {
         case OPIOCGET:
                 err = opiocget(argp, data);
@@ -589,7 +590,7 @@ static int openprom_bsd_ioctl(struct file * file,
                 err = -EINVAL;
                 break;
         };
-        unlock_kernel();
+        mutex_unlock(&openprom_mutex);
 
         return err;
 }
@@ -697,11 +698,11 @@ static int openprom_open(struct inode * inode, struct file * file)
         if (!data)
                 return -ENOMEM;
 
-        lock_kernel();
+        mutex_lock(&openprom_mutex);
         data->current_node = of_find_node_by_path("/");
         data->lastnode = data->current_node;
         file->private_data = (void *) data;
-        unlock_kernel();
+        mutex_unlock(&openprom_mutex);
 
         return 0;
 }
diff --git a/drivers/sbus/char/uctrl.c b/drivers/sbus/char/uctrl.c
index 5f253665a1da..079da4cb45a5 100644
--- a/drivers/sbus/char/uctrl.c
+++ b/drivers/sbus/char/uctrl.c
@@ -9,7 +9,7 @@
 #include <linux/delay.h>
 #include <linux/interrupt.h>
 #include <linux/slab.h>
-#include <linux/smp_lock.h>
+#include <linux/mutex.h>
 #include <linux/ioport.h>
 #include <linux/init.h>
 #include <linux/miscdevice.h>
@@ -72,6 +72,7 @@ struct ts102_regs {
 #define UCTRL_STAT_RXNE_STA        0x04    /* receive FIFO not empty status */
 #define UCTRL_STAT_RXO_STA         0x08    /* receive FIFO overflow status */
 
+static DEFINE_MUTEX(uctrl_mutex);
 static const char *uctrl_extstatus[16] = {
         "main power available",
         "internal battery attached",
@@ -210,10 +211,10 @@ uctrl_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
 static int
 uctrl_open(struct inode *inode, struct file *file)
 {
-        lock_kernel();
+        mutex_lock(&uctrl_mutex);
         uctrl_get_event_status(global_driver);
         uctrl_get_external_status(global_driver);
-        unlock_kernel();
+        mutex_unlock(&uctrl_mutex);
         return 0;
 }
 
diff --git a/drivers/serial/8250.c b/drivers/serial/8250.c
index 891e1dd65f24..09ef57034c9c 100644
--- a/drivers/serial/8250.c
+++ b/drivers/serial/8250.c
@@ -302,7 +302,7 @@ static const struct serial8250_config uart_config[] = {
         },
 };
 
-#if defined (CONFIG_SERIAL_8250_AU1X00)
+#if defined(CONFIG_MIPS_ALCHEMY)
 
 /* Au1x00 UART hardware has a weird register layout */
 static const u8 au_io_in_map[] = {
@@ -422,7 +422,6 @@ static unsigned int mem32_serial_in(struct uart_port *p, int offset)
         return readl(p->membase + offset);
 }
 
-#ifdef CONFIG_SERIAL_8250_AU1X00
 static unsigned int au_serial_in(struct uart_port *p, int offset)
 {
         offset = map_8250_in_reg(p, offset) << p->regshift;
@@ -434,7 +433,6 @@ static void au_serial_out(struct uart_port *p, int offset, int value)
         offset = map_8250_out_reg(p, offset) << p->regshift;
         __raw_writel(value, p->membase + offset);
 }
-#endif
 
 static unsigned int tsi_serial_in(struct uart_port *p, int offset)
 {
@@ -503,12 +501,11 @@ static void set_io_from_upio(struct uart_port *p)
                 p->serial_out = mem32_serial_out;
                 break;
 
-#ifdef CONFIG_SERIAL_8250_AU1X00
         case UPIO_AU:
                 p->serial_in = au_serial_in;
                 p->serial_out = au_serial_out;
                 break;
-#endif
+
         case UPIO_TSI:
                 p->serial_in = tsi_serial_in;
                 p->serial_out = tsi_serial_out;
@@ -535,9 +532,7 @@ serial_out_sync(struct uart_8250_port *up, int offset, int value)
         switch (p->iotype) {
         case UPIO_MEM:
         case UPIO_MEM32:
-#ifdef CONFIG_SERIAL_8250_AU1X00
         case UPIO_AU:
-#endif
         case UPIO_DWAPB:
                 p->serial_out(p, offset, value);
                 p->serial_in(p, UART_LCR);      /* safe, no side-effects */
@@ -573,7 +568,7 @@ static inline void _serial_dl_write(struct uart_8250_port *up, int value)
         serial_outp(up, UART_DLM, value >> 8 & 0xff);
 }
 
-#if defined(CONFIG_SERIAL_8250_AU1X00)
+#if defined(CONFIG_MIPS_ALCHEMY)
 /* Au1x00 haven't got a standard divisor latch */
 static int serial_dl_read(struct uart_8250_port *up)
 {
@@ -2596,11 +2591,9 @@ static void serial8250_config_port(struct uart_port *port, int flags)
         if (flags & UART_CONFIG_TYPE)
                 autoconfig(up, probeflags);
 
-#ifdef CONFIG_SERIAL_8250_AU1X00
         /* if access method is AU, it is a 16550 with a quirk */
         if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
                 up->bugs |= UART_BUG_NOMSR;
-#endif
 
         if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
                 autoconfig_irq(up);
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 8b23165bc5dc..e437ce8c1748 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -258,14 +258,6 @@ config SERIAL_8250_ACORN
           system, say Y to this option.  The driver can handle 1, 2, or 3 port
           cards.  If unsure, say N.
 
-config SERIAL_8250_AU1X00
-        bool "Au1x00 serial port support"
-        depends on SERIAL_8250 != n && SOC_AU1X00
-        help
-          If you have an Au1x00 SOC based board and want to use the serial port,
-          say Y to this option. The driver can handle up to 4 serial ports,
-          depending on the SOC. If unsure, say N.
-
 config SERIAL_8250_RM9K
         bool "Support for MIPS RM9xxx integrated serial port"
         depends on SERIAL_8250 != n && SERIAL_RM9000
diff --git a/drivers/serial/mpc52xx_uart.c b/drivers/serial/mpc52xx_uart.c
index 84a35f699016..1a88b363005c 100644
--- a/drivers/serial/mpc52xx_uart.c
+++ b/drivers/serial/mpc52xx_uart.c
@@ -113,7 +113,9 @@ struct psc_ops {
         unsigned char   (*read_char)(struct uart_port *port);
         void            (*cw_disable_ints)(struct uart_port *port);
         void            (*cw_restore_ints)(struct uart_port *port);
-        unsigned long   (*getuartclk)(void *p);
+        unsigned int    (*set_baudrate)(struct uart_port *port,
+                                        struct ktermios *new,
+                                        struct ktermios *old);
         int             (*clock)(struct uart_port *port, int enable);
         int             (*fifoc_init)(void);
         void            (*fifoc_uninit)(void);
@@ -121,6 +123,16 @@ struct psc_ops {
         irqreturn_t     (*handle_irq)(struct uart_port *port);
 };
 
+/* setting the prescaler and divisor reg is common for all chips */
+static inline void mpc52xx_set_divisor(struct mpc52xx_psc __iomem *psc,
+                                       u16 prescaler, unsigned int divisor)
+{
+        /* select prescaler */
+        out_be16(&psc->mpc52xx_psc_clock_select, prescaler);
+        out_8(&psc->ctur, divisor >> 8);
+        out_8(&psc->ctlr, divisor & 0xff);
+}
+
 #ifdef CONFIG_PPC_MPC52xx
 #define FIFO_52xx(port) ((struct mpc52xx_psc_fifo __iomem *)(PSC(port)+1))
 static void mpc52xx_psc_fifo_init(struct uart_port *port)
@@ -128,9 +140,6 @@ static void mpc52xx_psc_fifo_init(struct uart_port *port)
         struct mpc52xx_psc __iomem *psc = PSC(port);
         struct mpc52xx_psc_fifo __iomem *fifo = FIFO_52xx(port);
 
-        /* /32 prescaler */
-        out_be16(&psc->mpc52xx_psc_clock_select, 0xdd00);
-
         out_8(&fifo->rfcntl, 0x00);
         out_be16(&fifo->rfalarm, 0x1ff);
         out_8(&fifo->tfcntl, 0x07);
@@ -219,15 +228,47 @@ static void mpc52xx_psc_cw_restore_ints(struct uart_port *port)
         out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
 }
 
-/* Search for bus-frequency property in this node or a parent */
-static unsigned long mpc52xx_getuartclk(void *p)
+static unsigned int mpc5200_psc_set_baudrate(struct uart_port *port,
+                                             struct ktermios *new,
+                                             struct ktermios *old)
 {
-        /*
-         * 5200 UARTs have a / 32 prescaler
-         * but the generic serial code assumes 16
-         * so return ipb freq / 2
-         */
-        return mpc5xxx_get_bus_frequency(p) / 2;
+        unsigned int baud;
+        unsigned int divisor;
+
+        /* The 5200 has a fixed /32 prescaler, uartclk contains the ipb freq */
+        baud = uart_get_baud_rate(port, new, old,
+                                  port->uartclk / (32 * 0xffff) + 1,
+                                  port->uartclk / 32);
+        divisor = (port->uartclk + 16 * baud) / (32 * baud);
+
+        /* enable the /32 prescaler and set the divisor */
+        mpc52xx_set_divisor(PSC(port), 0xdd00, divisor);
+        return baud;
+}
+
+static unsigned int mpc5200b_psc_set_baudrate(struct uart_port *port,
+                                              struct ktermios *new,
+                                              struct ktermios *old)
+{
+        unsigned int baud;
+        unsigned int divisor;
+        u16 prescaler;
+
+        /* The 5200B has a selectable /4 or /32 prescaler, uartclk contains the
+         * ipb freq */
+        baud = uart_get_baud_rate(port, new, old,
+                                  port->uartclk / (32 * 0xffff) + 1,
+                                  port->uartclk / 4);
+        divisor = (port->uartclk + 2 * baud) / (4 * baud);
+
+        /* select the proper prescaler and set the divisor */
+        if (divisor > 0xffff) {
+                divisor = (divisor + 4) / 8;
+                prescaler = 0xdd00; /* /32 */
+        } else
+                prescaler = 0xff00; /* /4 */
+        mpc52xx_set_divisor(PSC(port), prescaler, divisor);
+        return baud;
 }
 
 static void mpc52xx_psc_get_irq(struct uart_port *port, struct device_node *np)
@@ -258,7 +299,28 @@ static struct psc_ops mpc52xx_psc_ops = {
         .read_char = mpc52xx_psc_read_char,
         .cw_disable_ints = mpc52xx_psc_cw_disable_ints,
         .cw_restore_ints = mpc52xx_psc_cw_restore_ints,
-        .getuartclk = mpc52xx_getuartclk,
+        .set_baudrate = mpc5200_psc_set_baudrate,
+        .get_irq = mpc52xx_psc_get_irq,
+        .handle_irq = mpc52xx_psc_handle_irq,
+};
+
+static struct psc_ops mpc5200b_psc_ops = {
+        .fifo_init = mpc52xx_psc_fifo_init,
+        .raw_rx_rdy = mpc52xx_psc_raw_rx_rdy,
+        .raw_tx_rdy = mpc52xx_psc_raw_tx_rdy,
+        .rx_rdy = mpc52xx_psc_rx_rdy,
+        .tx_rdy = mpc52xx_psc_tx_rdy,
+        .tx_empty = mpc52xx_psc_tx_empty,
+        .stop_rx = mpc52xx_psc_stop_rx,
+        .start_tx = mpc52xx_psc_start_tx,
+        .stop_tx = mpc52xx_psc_stop_tx,
+        .rx_clr_irq = mpc52xx_psc_rx_clr_irq,
+        .tx_clr_irq = mpc52xx_psc_tx_clr_irq,
+        .write_char = mpc52xx_psc_write_char,
+        .read_char = mpc52xx_psc_read_char,
+        .cw_disable_ints = mpc52xx_psc_cw_disable_ints,
+        .cw_restore_ints = mpc52xx_psc_cw_restore_ints,
+        .set_baudrate = mpc5200b_psc_set_baudrate,
         .get_irq = mpc52xx_psc_get_irq,
         .handle_irq = mpc52xx_psc_handle_irq,
 };
@@ -392,9 +454,35 @@ static void mpc512x_psc_cw_restore_ints(struct uart_port *port)
         out_be32(&FIFO_512x(port)->rximr, port->read_status_mask & 0x7f);
 }
 
-static unsigned long mpc512x_getuartclk(void *p)
+static unsigned int mpc512x_psc_set_baudrate(struct uart_port *port,
+                                             struct ktermios *new,
+                                             struct ktermios *old)
 {
-        return mpc5xxx_get_bus_frequency(p);
+        unsigned int baud;
+        unsigned int divisor;
+
+        /*
+         * The "MPC5121e Microcontroller Reference Manual, Rev. 3" says on
+         * pg. 30-10 that the chip supports a /32 and a /10 prescaler.
+         * Furthermore, it states that "After reset, the prescaler by 10
+         * for the UART mode is selected", but the reset register value is
+         * 0x0000 which means a /32 prescaler. This is wrong.
+         *
+         * In reality using /32 prescaler doesn't work, as it is not supported!
+         * Use /16 or /10 prescaler, see "MPC5121e Hardware Design Guide",
+         * Chapter 4.1 PSC in UART Mode.
+         * Calculate with a /16 prescaler here.
+         */
+
+        /* uartclk contains the ips freq */
+        baud = uart_get_baud_rate(port, new, old,
+                                  port->uartclk / (16 * 0xffff) + 1,
+                                  port->uartclk / 16);
+        divisor = (port->uartclk + 8 * baud) / (16 * baud);
+
+        /* enable the /16 prescaler and set the divisor */
+        mpc52xx_set_divisor(PSC(port), 0xdd00, divisor);
+        return baud;
 }
 
 /* Init PSC FIFO Controller */
@@ -498,7 +586,7 @@ static struct psc_ops mpc512x_psc_ops = {
         .read_char = mpc512x_psc_read_char,
         .cw_disable_ints = mpc512x_psc_cw_disable_ints,
         .cw_restore_ints = mpc512x_psc_cw_restore_ints,
-        .getuartclk = mpc512x_getuartclk,
+        .set_baudrate = mpc512x_psc_set_baudrate,
         .clock = mpc512x_psc_clock,
         .fifoc_init = mpc512x_psc_fifoc_init,
         .fifoc_uninit = mpc512x_psc_fifoc_uninit,
@@ -666,8 +754,8 @@ mpc52xx_uart_set_termios(struct uart_port *port, struct ktermios *new,
         struct mpc52xx_psc __iomem *psc = PSC(port);
         unsigned long flags;
         unsigned char mr1, mr2;
-        unsigned short ctr;
-        unsigned int j, baud, quot;
+        unsigned int j;
+        unsigned int baud;
 
         /* Prepare what we're gonna write */
         mr1 = 0;
@@ -704,16 +792,9 @@ mpc52xx_uart_set_termios(struct uart_port *port, struct ktermios *new,
                 mr2 |= MPC52xx_PSC_MODE_TXCTS;
         }
 
-        baud = uart_get_baud_rate(port, new, old, 0, port->uartclk/16);
-        quot = uart_get_divisor(port, baud);
-        ctr = quot & 0xffff;
-
         /* Get the lock */
         spin_lock_irqsave(&port->lock, flags);
 
-        /* Update the per-port timeout */
-        uart_update_timeout(port, new->c_cflag, baud);
-
         /* Do our best to flush TX & RX, so we don't lose anything */
         /* But we don't wait indefinitely ! */
         j = 5000000;    /* Maximum wait */
@@ -737,8 +818,10 @@ mpc52xx_uart_set_termios(struct uart_port *port, struct ktermios *new,
         out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);
         out_8(&psc->mode, mr1);
         out_8(&psc->mode, mr2);
-        out_8(&psc->ctur, ctr >> 8);
-        out_8(&psc->ctlr, ctr & 0xff);
+        baud = psc_ops->set_baudrate(port, new, old);
+
+        /* Update the per-port timeout */
+        uart_update_timeout(port, new->c_cflag, baud);
 
         if (UART_ENABLE_MS(port, new->c_cflag))
                 mpc52xx_uart_enable_ms(port);
@@ -1118,7 +1201,7 @@ mpc52xx_console_setup(struct console *co, char *options)
                 return ret;
         }
 
-        uartclk = psc_ops->getuartclk(np);
+        uartclk = mpc5xxx_get_bus_frequency(np);
         if (uartclk == 0) {
                 pr_debug("Could not find uart clock frequency!\n");
                 return -EINVAL;
@@ -1201,6 +1284,7 @@ static struct uart_driver mpc52xx_uart_driver = {
 
 static struct of_device_id mpc52xx_uart_of_match[] = {
 #ifdef CONFIG_PPC_MPC52xx
+        { .compatible = "fsl,mpc5200b-psc-uart", .data = &mpc5200b_psc_ops, },
         { .compatible = "fsl,mpc5200-psc-uart", .data = &mpc52xx_psc_ops, },
         /* binding used by old lite5200 device trees: */
         { .compatible = "mpc5200-psc-uart", .data = &mpc52xx_psc_ops, },
@@ -1233,7 +1317,10 @@ mpc52xx_uart_of_probe(struct of_device *op, const struct of_device_id *match)
         pr_debug("Found %s assigned to ttyPSC%x\n",
                  mpc52xx_uart_nodes[idx]->full_name, idx);
 
-        uartclk = psc_ops->getuartclk(op->dev.of_node);
+        /* set the uart clock to the input clock of the psc, the different
+         * prescalers are taken into account in the set_baudrate() methods
+         * of the respective chip */
+        uartclk = mpc5xxx_get_bus_frequency(op->dev.of_node);
         if (uartclk == 0) {
                 dev_dbg(&op->dev, "Could not find uart clock frequency!\n");
                 return -EINVAL;
diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
index 6a58cb1330c1..4aa00e6e57ad 100644
--- a/drivers/usb/Kconfig
+++ b/drivers/usb/Kconfig
@@ -45,7 +45,8 @@ config USB_ARCH_HAS_OHCI
         default y if STB03xxx
         default y if PPC_MPC52xx
         # MIPS:
-        default y if SOC_AU1X00
+        default y if MIPS_ALCHEMY
+        default y if MACH_JZ4740
         # SH:
         default y if CPU_SUBTYPE_SH7720
         default y if CPU_SUBTYPE_SH7721
diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
index fc576557d8a5..02864a237a2c 100644
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -1031,7 +1031,7 @@ MODULE_LICENSE ("GPL");
 #define PLATFORM_DRIVER         ohci_hcd_ep93xx_driver
 #endif
 
-#ifdef CONFIG_SOC_AU1X00
+#ifdef CONFIG_MIPS_ALCHEMY
 #include "ohci-au1xxx.c"
 #define PLATFORM_DRIVER         ohci_hcd_au1xxx_driver
 #endif
@@ -1095,6 +1095,11 @@ MODULE_LICENSE ("GPL");
 #define TMIO_OHCI_DRIVER        ohci_hcd_tmio_driver
 #endif
 
+#ifdef CONFIG_MACH_JZ4740
+#include "ohci-jz4740.c"
+#define PLATFORM_DRIVER ohci_hcd_jz4740_driver
+#endif
+
 #if     !defined(PCI_DRIVER) &&         \
         !defined(PLATFORM_DRIVER) &&    \
         !defined(OMAP1_PLATFORM_DRIVER) &&      \
diff --git a/drivers/usb/host/ohci-jz4740.c b/drivers/usb/host/ohci-jz4740.c
new file mode 100644
index 000000000000..10e1872f3ab9
--- /dev/null
+++ b/drivers/usb/host/ohci-jz4740.c
@@ -0,0 +1,276 @@
+/*
+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under  the terms of the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/regulator/consumer.h>
+
+struct jz4740_ohci_hcd {
+        struct ohci_hcd ohci_hcd;
+
+        struct regulator *vbus;
+        bool vbus_enabled;
+        struct clk *clk;
+};
+
+static inline struct jz4740_ohci_hcd *hcd_to_jz4740_hcd(struct usb_hcd *hcd)
+{
+        return (struct jz4740_ohci_hcd *)(hcd->hcd_priv);
+}
+
+static inline struct usb_hcd *jz4740_hcd_to_hcd(struct jz4740_ohci_hcd *jz4740_ohci)
+{
+        return container_of((void *)jz4740_ohci, struct usb_hcd, hcd_priv);
+}
+
+static int ohci_jz4740_start(struct usb_hcd *hcd)
+{
+        struct ohci_hcd *ohci = hcd_to_ohci(hcd);
+        int     ret;
+
+        ret = ohci_init(ohci);
+        if (ret < 0)
+                return ret;
+
+        ohci->num_ports = 1;
+
+        ret = ohci_run(ohci);
+        if (ret < 0) {
+                dev_err(hcd->self.controller, "Can not start %s",
+                        hcd->self.bus_name);
+                ohci_stop(hcd);
+                return ret;
+        }
+        return 0;
+}
+
+static int ohci_jz4740_set_vbus_power(struct jz4740_ohci_hcd *jz4740_ohci,
+        bool enabled)
+{
+        int ret = 0;
+
+        if (!jz4740_ohci->vbus)
+                return 0;
+
+        if (enabled && !jz4740_ohci->vbus_enabled) {
+                ret = regulator_enable(jz4740_ohci->vbus);
+                if (ret)
+                        dev_err(jz4740_hcd_to_hcd(jz4740_ohci)->self.controller,
+                                "Could not power vbus\n");
+        } else if (!enabled && jz4740_ohci->vbus_enabled) {
+                ret = regulator_disable(jz4740_ohci->vbus);
+        }
+
+        if (ret == 0)
+                jz4740_ohci->vbus_enabled = enabled;
+
+        return ret;
+}
+
+static int ohci_jz4740_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
+        u16 wIndex, char *buf, u16 wLength)
+{
+        struct jz4740_ohci_hcd *jz4740_ohci = hcd_to_jz4740_hcd(hcd);
+        int ret;
+
+        switch (typeReq) {
+        case SetHubFeature:
+                if (wValue == USB_PORT_FEAT_POWER)
+                        ret = ohci_jz4740_set_vbus_power(jz4740_ohci, true);
+                break;
+        case ClearHubFeature:
+                if (wValue == USB_PORT_FEAT_POWER)
+                        ret = ohci_jz4740_set_vbus_power(jz4740_ohci, false);
+                break;
+        }
+
+        if (ret)
+                return ret;
+
+        return ohci_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength);
+}
+
+
+static const struct hc_driver ohci_jz4740_hc_driver = {
+        .description =          hcd_name,
+        .product_desc =         "JZ4740 OHCI",
+        .hcd_priv_size =        sizeof(struct jz4740_ohci_hcd),
+
+        /*
+         * generic hardware linkage
+         */
+        .irq =                  ohci_irq,
+        .flags =                HCD_USB11 | HCD_MEMORY,
+
+        /*
+         * basic lifecycle operations
+         */
+        .start =                ohci_jz4740_start,
+        .stop =                 ohci_stop,
+        .shutdown =             ohci_shutdown,
+
+        /*
+         * managing i/o requests and associated device resources
+         */
+        .urb_enqueue =          ohci_urb_enqueue,
+        .urb_dequeue =          ohci_urb_dequeue,
+        .endpoint_disable =     ohci_endpoint_disable,
+
+        /*
+         * scheduling support
+         */
+        .get_frame_number =     ohci_get_frame,
+
+        /*
+         * root hub support
+         */
+        .hub_status_data =      ohci_hub_status_data,
+        .hub_control =          ohci_jz4740_hub_control,
+#ifdef  CONFIG_PM
+        .bus_suspend =          ohci_bus_suspend,
+        .bus_resume =           ohci_bus_resume,
+#endif
+        .start_port_reset =     ohci_start_port_reset,
+};
+
+
+static __devinit int jz4740_ohci_probe(struct platform_device *pdev)
+{
+        int ret;
+        struct usb_hcd *hcd;
+        struct jz4740_ohci_hcd *jz4740_ohci;
+        struct resource *res;
+        int irq;
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+        if (!res) {
+                dev_err(&pdev->dev, "Failed to get platform resource\n");
+                return -ENOENT;
+        }
+
+        irq = platform_get_irq(pdev, 0);
+        if (irq < 0) {
+                dev_err(&pdev->dev, "Failed to get platform irq\n");
+                return irq;
+        }
+
+        hcd = usb_create_hcd(&ohci_jz4740_hc_driver, &pdev->dev, "jz4740");
+        if (!hcd) {
+                dev_err(&pdev->dev, "Failed to create hcd.\n");
+                return -ENOMEM;
+        }
+
+        jz4740_ohci = hcd_to_jz4740_hcd(hcd);
+
+        res = request_mem_region(res->start, resource_size(res), hcd_name);
+        if (!res) {
+                dev_err(&pdev->dev, "Failed to request mem region.\n");
+                ret = -EBUSY;
+                goto err_free;
+        }
+
+        hcd->rsrc_start = res->start;
+        hcd->rsrc_len = resource_size(res);
+        hcd->regs = ioremap(res->start, resource_size(res));
+
+        if (!hcd->regs) {
+                dev_err(&pdev->dev, "Failed to ioremap registers.\n");
+                ret = -EBUSY;
+                goto err_release_mem;
+        }
+
+        jz4740_ohci->clk = clk_get(&pdev->dev, "uhc");
+        if (IS_ERR(jz4740_ohci->clk)) {
+                ret = PTR_ERR(jz4740_ohci->clk);
+                dev_err(&pdev->dev, "Failed to get clock: %d\n", ret);
+                goto err_iounmap;
+        }
+
+        jz4740_ohci->vbus = regulator_get(&pdev->dev, "vbus");
+        if (IS_ERR(jz4740_ohci->vbus))
+                jz4740_ohci->vbus = NULL;
+
+
+        clk_set_rate(jz4740_ohci->clk, 48000000);
+        clk_enable(jz4740_ohci->clk);
+        if (jz4740_ohci->vbus)
+                ohci_jz4740_set_vbus_power(jz4740_ohci, true);
+
+        platform_set_drvdata(pdev, hcd);
+
+        ohci_hcd_init(hcd_to_ohci(hcd));
+
+        ret = usb_add_hcd(hcd, irq, 0);
+        if (ret) {
+                dev_err(&pdev->dev, "Failed to add hcd: %d\n", ret);
+                goto err_disable;
+        }
+
+        return 0;
+
+err_disable:
+        platform_set_drvdata(pdev, NULL);
+        if (jz4740_ohci->vbus) {
+                regulator_disable(jz4740_ohci->vbus);
+                regulator_put(jz4740_ohci->vbus);
+        }
+        clk_disable(jz4740_ohci->clk);
+
+        clk_put(jz4740_ohci->clk);
+err_iounmap:
+        iounmap(hcd->regs);
+err_release_mem:
+        release_mem_region(res->start, resource_size(res));
+err_free:
+        usb_put_hcd(hcd);
+
+        return ret;
+}
+
+static __devexit int jz4740_ohci_remove(struct platform_device *pdev)
+{
+        struct usb_hcd *hcd = platform_get_drvdata(pdev);
+        struct jz4740_ohci_hcd *jz4740_ohci = hcd_to_jz4740_hcd(hcd);
+
+        usb_remove_hcd(hcd);
+
+        platform_set_drvdata(pdev, NULL);
+
+        if (jz4740_ohci->vbus) {
+                regulator_disable(jz4740_ohci->vbus);
+                regulator_put(jz4740_ohci->vbus);
+        }
+
+        clk_disable(jz4740_ohci->clk);
+        clk_put(jz4740_ohci->clk);
+
+        iounmap(hcd->regs);
+        release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
+
+        usb_put_hcd(hcd);
+
+        return 0;
+}
+
+static struct platform_driver ohci_hcd_jz4740_driver = {
+        .probe = jz4740_ohci_probe,
+        .remove = __devexit_p(jz4740_ohci_remove),
+        .driver = {
+                .name = "jz4740-ohci",
+                .owner = THIS_MODULE,
+        },
+};
+
+MODULE_ALIAS("platfrom:jz4740-ohci");
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 3d94a1471724..7b11ea68c80e 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -1871,6 +1871,7 @@ config FB_MBX_DEBUG
 config FB_FSL_DIU
         tristate "Freescale DIU framebuffer support"
         depends on FB && FSL_SOC
+        select FB_MODE_HELPERS
         select FB_CFB_FILLRECT
         select FB_CFB_COPYAREA
         select FB_CFB_IMAGEBLIT
@@ -2229,6 +2230,15 @@ config FB_BROADSHEET
           and could also have been called by other names when coupled with
           a bridge adapter.
 
+config FB_JZ4740
+        tristate "JZ4740 LCD framebuffer support"
+        depends on FB && MACH_JZ4740
+        select FB_SYS_FILLRECT
+        select FB_SYS_COPYAREA
+        select FB_SYS_IMAGEBLIT
+        help
+          Framebuffer support for the JZ4740 SoC.
+
 source "drivers/video/omap/Kconfig"
 source "drivers/video/omap2/Kconfig"
 
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index ddc2af2ba45b..f56a9cae2157 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -131,6 +131,7 @@ obj-$(CONFIG_FB_CARMINE)          += carminefb.o
 obj-$(CONFIG_FB_MB862XX)          += mb862xx/
 obj-$(CONFIG_FB_MSM)              += msm/
 obj-$(CONFIG_FB_NUC900)           += nuc900fb.o
+obj-$(CONFIG_FB_JZ4740)           += jz4740_fb.o
 
 # Platform or fallback drivers go here
 obj-$(CONFIG_FB_UVESA)            += uvesafb.o
diff --git a/drivers/video/fsl-diu-fb.c b/drivers/video/fsl-diu-fb.c
index 27455ce298b7..e38ad2224540 100644
--- a/drivers/video/fsl-diu-fb.c
+++ b/drivers/video/fsl-diu-fb.c
@@ -34,7 +34,8 @@
 #include <linux/of_platform.h>
 
 #include <sysdev/fsl_soc.h>
-#include "fsl-diu-fb.h"
+#include <linux/fsl-diu-fb.h>
+#include "edid.h"
 
 /*
  * These parameters give default parameters
@@ -217,6 +218,7 @@ struct mfb_info {
         int x_aoi_d;            /* aoi display x offset to physical screen */
         int y_aoi_d;            /* aoi display y offset to physical screen */
         struct fsl_diu_data *parent;
+        u8 *edid_data;
 };
 
 
@@ -317,6 +319,17 @@ static void fsl_diu_free(void *virt, size_t size)
                 free_pages_exact(virt, size);
 }
 
+/*
+ * Workaround for failed writing desc register of planes.
+ * Needed with MPC5121 DIU rev 2.0 silicon.
+ */
+void wr_reg_wa(u32 *reg, u32 val)
+{
+        do {
+                out_be32(reg, val);
+        } while (in_be32(reg) != val);
+}
+
 static int fsl_diu_enable_panel(struct fb_info *info)
 {
         struct mfb_info *pmfbi, *cmfbi, *mfbi = info->par;
@@ -330,7 +343,7 @@ static int fsl_diu_enable_panel(struct fb_info *info)
                 switch (mfbi->index) {
                 case 0:                         /* plane 0 */
                         if (hw->desc[0] != ad->paddr)
-                                out_be32(&hw->desc[0], ad->paddr);
+                                wr_reg_wa(&hw->desc[0], ad->paddr);
                         break;
                 case 1:                         /* plane 1 AOI 0 */
                         cmfbi = machine_data->fsl_diu_info[2]->par;
@@ -340,7 +353,7 @@ static int fsl_diu_enable_panel(struct fb_info *info)
                                                 cpu_to_le32(cmfbi->ad->paddr);
                                 else
                                         ad->next_ad = 0;
-                                out_be32(&hw->desc[1], ad->paddr);
+                                wr_reg_wa(&hw->desc[1], ad->paddr);
                         }
                         break;
                 case 3:                         /* plane 2 AOI 0 */
@@ -351,14 +364,14 @@ static int fsl_diu_enable_panel(struct fb_info *info)
                                                 cpu_to_le32(cmfbi->ad->paddr);
                                 else
                                         ad->next_ad = 0;
-                                out_be32(&hw->desc[2], ad->paddr);
+                                wr_reg_wa(&hw->desc[2], ad->paddr);
                         }
                         break;
                 case 2:                         /* plane 1 AOI 1 */
                         pmfbi = machine_data->fsl_diu_info[1]->par;
                         ad->next_ad = 0;
                         if (hw->desc[1] == machine_data->dummy_ad->paddr)
-                                out_be32(&hw->desc[1], ad->paddr);
+                                wr_reg_wa(&hw->desc[1], ad->paddr);
                         else                                    /* AOI0 open */
                                 pmfbi->ad->next_ad = cpu_to_le32(ad->paddr);
                         break;
@@ -366,7 +379,7 @@ static int fsl_diu_enable_panel(struct fb_info *info)
                         pmfbi = machine_data->fsl_diu_info[3]->par;
                         ad->next_ad = 0;
                         if (hw->desc[2] == machine_data->dummy_ad->paddr)
-                                out_be32(&hw->desc[2], ad->paddr);
+                                wr_reg_wa(&hw->desc[2], ad->paddr);
                         else                            /* AOI0 was open */
                                 pmfbi->ad->next_ad = cpu_to_le32(ad->paddr);
                         break;
@@ -390,27 +403,24 @@ static int fsl_diu_disable_panel(struct fb_info *info)
         switch (mfbi->index) {
         case 0:                                 /* plane 0 */
                 if (hw->desc[0] != machine_data->dummy_ad->paddr)
-                        out_be32(&hw->desc[0],
-                                machine_data->dummy_ad->paddr);
+                        wr_reg_wa(&hw->desc[0], machine_data->dummy_ad->paddr);
                 break;
         case 1:                                 /* plane 1 AOI 0 */
                 cmfbi = machine_data->fsl_diu_info[2]->par;
                 if (cmfbi->count > 0)   /* AOI1 is open */
-                        out_be32(&hw->desc[1], cmfbi->ad->paddr);
+                        wr_reg_wa(&hw->desc[1], cmfbi->ad->paddr);
                                         /* move AOI1 to the first */
                 else                    /* AOI1 was closed */
-                        out_be32(&hw->desc[1],
-                                machine_data->dummy_ad->paddr);
+                        wr_reg_wa(&hw->desc[1], machine_data->dummy_ad->paddr);
                                         /* close AOI 0 */
                 break;
         case 3:                                 /* plane 2 AOI 0 */
                 cmfbi = machine_data->fsl_diu_info[4]->par;
                 if (cmfbi->count > 0)   /* AOI1 is open */
-                        out_be32(&hw->desc[2], cmfbi->ad->paddr);
+                        wr_reg_wa(&hw->desc[2], cmfbi->ad->paddr);
                                         /* move AOI1 to the first */
                 else                    /* AOI1 was closed */
-                        out_be32(&hw->desc[2],
-                                machine_data->dummy_ad->paddr);
+                        wr_reg_wa(&hw->desc[2], machine_data->dummy_ad->paddr);
                                         /* close AOI 0 */
                 break;
         case 2:                                 /* plane 1 AOI 1 */
@@ -421,7 +431,7 @@ static int fsl_diu_disable_panel(struct fb_info *info)
                                         /* AOI0 is open, must be the first */
                                 pmfbi->ad->next_ad = 0;
                 } else                  /* AOI1 is the first in the chain */
-                        out_be32(&hw->desc[1], machine_data->dummy_ad->paddr);
+                        wr_reg_wa(&hw->desc[1], machine_data->dummy_ad->paddr);
                                         /* close AOI 1 */
                 break;
         case 4:                                 /* plane 2 AOI 1 */
@@ -432,7 +442,7 @@ static int fsl_diu_disable_panel(struct fb_info *info)
                                 /* AOI0 is open, must be the first */
                                 pmfbi->ad->next_ad = 0;
                 } else          /* AOI1 is the first in the chain */
-                        out_be32(&hw->desc[2], machine_data->dummy_ad->paddr);
+                        wr_reg_wa(&hw->desc[2], machine_data->dummy_ad->paddr);
                                 /* close AOI 1 */
                 break;
         default:
@@ -1100,6 +1110,10 @@ static int fsl_diu_open(struct fb_info *info, int user)
         struct mfb_info *mfbi = info->par;
         int res = 0;
 
+        /* free boot splash memory on first /dev/fb0 open */
+        if (!mfbi->index && diu_ops.release_bootmem)
+                diu_ops.release_bootmem();
+
         spin_lock(&diu_lock);
         mfbi->count++;
         if (mfbi->count == 1) {
@@ -1173,18 +1187,30 @@ static int __devinit install_fb(struct fb_info *info)
         int rc;
         struct mfb_info *mfbi = info->par;
         const char *aoi_mode, *init_aoi_mode = "320x240";
+        struct fb_videomode *db = fsl_diu_mode_db;
+        unsigned int dbsize = ARRAY_SIZE(fsl_diu_mode_db);
+        int has_default_mode = 1;
 
         if (init_fbinfo(info))
                 return -EINVAL;
 
-        if (mfbi->index == 0)   /* plane 0 */
+        if (mfbi->index == 0) { /* plane 0 */
+                if (mfbi->edid_data) {
+                        /* Now build modedb from EDID */
+                        fb_edid_to_monspecs(mfbi->edid_data, &info->monspecs);
+                        fb_videomode_to_modelist(info->monspecs.modedb,
+                                                 info->monspecs.modedb_len,
+                                                 &info->modelist);
+                        db = info->monspecs.modedb;
+                        dbsize = info->monspecs.modedb_len;
+                }
                 aoi_mode = fb_mode;
-        else
+        } else {
                 aoi_mode = init_aoi_mode;
+        }
         pr_debug("mode used = %s\n", aoi_mode);
-        rc = fb_find_mode(&info->var, info, aoi_mode, fsl_diu_mode_db,
-             ARRAY_SIZE(fsl_diu_mode_db), &fsl_diu_default_mode, default_bpp);
-
+        rc = fb_find_mode(&info->var, info, aoi_mode, db, dbsize,
+                          &fsl_diu_default_mode, default_bpp);
         switch (rc) {
         case 1:
                 pr_debug("using mode specified in @mode\n");
@@ -1202,10 +1228,50 @@ static int __devinit install_fb(struct fb_info *info)
         default:
                 pr_debug("rc = %d\n", rc);
                 pr_debug("failed to find mode\n");
-                return -EINVAL;
+                /*
+                 * For plane 0 we continue and look into
+                 * driver's internal modedb.
+                 */
+                if (mfbi->index == 0 && mfbi->edid_data)
+                        has_default_mode = 0;
+                else
+                        return -EINVAL;
                 break;
         }
 
+        if (!has_default_mode) {
+                rc = fb_find_mode(&info->var, info, aoi_mode, fsl_diu_mode_db,
+                                  ARRAY_SIZE(fsl_diu_mode_db),
+                                  &fsl_diu_default_mode,
+                                  default_bpp);
+                if (rc > 0 && rc < 5)
+                        has_default_mode = 1;
+        }
+
+        /* Still not found, use preferred mode from database if any */
+        if (!has_default_mode && info->monspecs.modedb) {
+                struct fb_monspecs *specs = &info->monspecs;
+                struct fb_videomode *modedb = &specs->modedb[0];
+
+                /*
+                 * Get preferred timing. If not found,
+                 * first mode in database will be used.
+                 */
+                if (specs->misc & FB_MISC_1ST_DETAIL) {
+                        int i;
+
+                        for (i = 0; i < specs->modedb_len; i++) {
+                                if (specs->modedb[i].flag & FB_MODE_IS_FIRST) {
+                                        modedb = &specs->modedb[i];
+                                        break;
+                                }
+                        }
+                }
+
+                info->var.bits_per_pixel = default_bpp;
+                fb_videomode_to_var(&info->var, modedb);
+        }
+
         pr_debug("xres_virtual %d\n", info->var.xres_virtual);
         pr_debug("bits_per_pixel %d\n", info->var.bits_per_pixel);
 
@@ -1244,6 +1310,9 @@ static void uninstall_fb(struct fb_info *info)
         if (!mfbi->registered)
                 return;
 
+        if (mfbi->index == 0)
+                kfree(mfbi->edid_data);
+
         unregister_framebuffer(info);
         unmap_video_memory(info);
         if (&info->cmap)
@@ -1427,6 +1496,7 @@ static int __devinit fsl_diu_probe(struct of_device *ofdev,
         int ret, i, error = 0;
         struct resource res;
         struct fsl_diu_data *machine_data;
+        int diu_mode;
 
         machine_data = kzalloc(sizeof(struct fsl_diu_data), GFP_KERNEL);
         if (!machine_data)
@@ -1443,6 +1513,17 @@ static int __devinit fsl_diu_probe(struct of_device *ofdev,
                 mfbi = machine_data->fsl_diu_info[i]->par;
                 memcpy(mfbi, &mfb_template[i], sizeof(struct mfb_info));
                 mfbi->parent = machine_data;
+
+                if (mfbi->index == 0) {
+                        const u8 *prop;
+                        int len;
+
+                        /* Get EDID */
+                        prop = of_get_property(np, "edid", &len);
+                        if (prop && len == EDID_LENGTH)
+                                mfbi->edid_data = kmemdup(prop, EDID_LENGTH,
+                                                          GFP_KERNEL);
+                }
         }
 
         ret = of_address_to_resource(np, 0, &res);
@@ -1463,7 +1544,9 @@ static int __devinit fsl_diu_probe(struct of_device *ofdev,
                 goto error2;
         }
 
-        out_be32(&dr.diu_reg->diu_mode, 0);             /* disable DIU anyway*/
+        diu_mode = in_be32(&dr.diu_reg->diu_mode);
+        if (diu_mode != MFB_MODE1)
+                out_be32(&dr.diu_reg->diu_mode, 0);     /* disable DIU */
 
         /* Get the IRQ of the DIU */
         machine_data->irq = irq_of_parse_and_map(np, 0);
@@ -1511,7 +1594,13 @@ static int __devinit fsl_diu_probe(struct of_device *ofdev,
         machine_data->dummy_ad->offset_xyd = 0;
         machine_data->dummy_ad->next_ad = 0;
 
-        out_be32(&dr.diu_reg->desc[0], machine_data->dummy_ad->paddr);
+        /*
+         * Let DIU display splash screen if it was pre-initialized
+         * by the bootloader, set dummy area descriptor otherwise.
+         */
+        if (diu_mode != MFB_MODE1)
+                out_be32(&dr.diu_reg->desc[0], machine_data->dummy_ad->paddr);
+
         out_be32(&dr.diu_reg->desc[1], machine_data->dummy_ad->paddr);
         out_be32(&dr.diu_reg->desc[2], machine_data->dummy_ad->paddr);
 
diff --git a/drivers/video/jz4740_fb.c b/drivers/video/jz4740_fb.c
new file mode 100644
index 000000000000..670ecaa0385a
--- /dev/null
+++ b/drivers/video/jz4740_fb.c
@@ -0,0 +1,847 @@
+/*
+ *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
+ *      JZ4740 SoC LCD framebuffer driver
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under  the terms of  the GNU General Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/platform_device.h>
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+
+#include <linux/console.h>
+#include <linux/fb.h>
+
+#include <linux/dma-mapping.h>
+
+#include <asm/mach-jz4740/jz4740_fb.h>
+#include <asm/mach-jz4740/gpio.h>
+
+#define JZ_REG_LCD_CFG          0x00
+#define JZ_REG_LCD_VSYNC        0x04
+#define JZ_REG_LCD_HSYNC        0x08
+#define JZ_REG_LCD_VAT          0x0C
+#define JZ_REG_LCD_DAH          0x10
+#define JZ_REG_LCD_DAV          0x14
+#define JZ_REG_LCD_PS           0x18
+#define JZ_REG_LCD_CLS          0x1C
+#define JZ_REG_LCD_SPL          0x20
+#define JZ_REG_LCD_REV          0x24
+#define JZ_REG_LCD_CTRL         0x30
+#define JZ_REG_LCD_STATE        0x34
+#define JZ_REG_LCD_IID          0x38
+#define JZ_REG_LCD_DA0          0x40
+#define JZ_REG_LCD_SA0          0x44
+#define JZ_REG_LCD_FID0         0x48
+#define JZ_REG_LCD_CMD0         0x4C
+#define JZ_REG_LCD_DA1          0x50
+#define JZ_REG_LCD_SA1          0x54
+#define JZ_REG_LCD_FID1         0x58
+#define JZ_REG_LCD_CMD1         0x5C
+
+#define JZ_LCD_CFG_SLCD                 BIT(31)
+#define JZ_LCD_CFG_PS_DISABLE           BIT(23)
+#define JZ_LCD_CFG_CLS_DISABLE          BIT(22)
+#define JZ_LCD_CFG_SPL_DISABLE          BIT(21)
+#define JZ_LCD_CFG_REV_DISABLE          BIT(20)
+#define JZ_LCD_CFG_HSYNCM               BIT(19)
+#define JZ_LCD_CFG_PCLKM                BIT(18)
+#define JZ_LCD_CFG_INV                  BIT(17)
+#define JZ_LCD_CFG_SYNC_DIR             BIT(16)
+#define JZ_LCD_CFG_PS_POLARITY          BIT(15)
+#define JZ_LCD_CFG_CLS_POLARITY         BIT(14)
+#define JZ_LCD_CFG_SPL_POLARITY         BIT(13)
+#define JZ_LCD_CFG_REV_POLARITY         BIT(12)
+#define JZ_LCD_CFG_HSYNC_ACTIVE_LOW     BIT(11)
+#define JZ_LCD_CFG_PCLK_FALLING_EDGE    BIT(10)
+#define JZ_LCD_CFG_DE_ACTIVE_LOW        BIT(9)
+#define JZ_LCD_CFG_VSYNC_ACTIVE_LOW     BIT(8)
+#define JZ_LCD_CFG_18_BIT               BIT(7)
+#define JZ_LCD_CFG_PDW                  (BIT(5) | BIT(4))
+#define JZ_LCD_CFG_MODE_MASK 0xf
+
+#define JZ_LCD_CTRL_BURST_4             (0x0 << 28)
+#define JZ_LCD_CTRL_BURST_8             (0x1 << 28)
+#define JZ_LCD_CTRL_BURST_16            (0x2 << 28)
+#define JZ_LCD_CTRL_RGB555              BIT(27)
+#define JZ_LCD_CTRL_OFUP                BIT(26)
+#define JZ_LCD_CTRL_FRC_GRAYSCALE_16    (0x0 << 24)
+#define JZ_LCD_CTRL_FRC_GRAYSCALE_4     (0x1 << 24)
+#define JZ_LCD_CTRL_FRC_GRAYSCALE_2     (0x2 << 24)
+#define JZ_LCD_CTRL_PDD_MASK            (0xff << 16)
+#define JZ_LCD_CTRL_EOF_IRQ             BIT(13)
+#define JZ_LCD_CTRL_SOF_IRQ             BIT(12)
+#define JZ_LCD_CTRL_OFU_IRQ             BIT(11)
+#define JZ_LCD_CTRL_IFU0_IRQ            BIT(10)
+#define JZ_LCD_CTRL_IFU1_IRQ            BIT(9)
+#define JZ_LCD_CTRL_DD_IRQ              BIT(8)
+#define JZ_LCD_CTRL_QDD_IRQ             BIT(7)
+#define JZ_LCD_CTRL_REVERSE_ENDIAN      BIT(6)
+#define JZ_LCD_CTRL_LSB_FISRT           BIT(5)
+#define JZ_LCD_CTRL_DISABLE             BIT(4)
+#define JZ_LCD_CTRL_ENABLE              BIT(3)
+#define JZ_LCD_CTRL_BPP_1               0x0
+#define JZ_LCD_CTRL_BPP_2               0x1
+#define JZ_LCD_CTRL_BPP_4               0x2
+#define JZ_LCD_CTRL_BPP_8               0x3
+#define JZ_LCD_CTRL_BPP_15_16           0x4
+#define JZ_LCD_CTRL_BPP_18_24           0x5
+
+#define JZ_LCD_CMD_SOF_IRQ BIT(15)
+#define JZ_LCD_CMD_EOF_IRQ BIT(16)
+#define JZ_LCD_CMD_ENABLE_PAL BIT(12)
+
+#define JZ_LCD_SYNC_MASK 0x3ff
+
+#define JZ_LCD_STATE_DISABLED BIT(0)
+
+struct jzfb_framedesc {
+        uint32_t next;
+        uint32_t addr;
+        uint32_t id;
+        uint32_t cmd;
+} __packed;
+
+struct jzfb {
+        struct fb_info *fb;
+        struct platform_device *pdev;
+        void __iomem *base;
+        struct resource *mem;
+        struct jz4740_fb_platform_data *pdata;
+
+        size_t vidmem_size;
+        void *vidmem;
+        dma_addr_t vidmem_phys;
+        struct jzfb_framedesc *framedesc;
+        dma_addr_t framedesc_phys;
+
+        struct clk *ldclk;
+        struct clk *lpclk;
+
+        unsigned is_enabled:1;
+        struct mutex lock;
+
+        uint32_t pseudo_palette[16];
+};
+
+static const struct fb_fix_screeninfo jzfb_fix __devinitdata = {
+        .id             = "JZ4740 FB",
+        .type           = FB_TYPE_PACKED_PIXELS,
+        .visual         = FB_VISUAL_TRUECOLOR,
+        .xpanstep       = 0,
+        .ypanstep       = 0,
+        .ywrapstep      = 0,
+        .accel          = FB_ACCEL_NONE,
+};
+
+static const struct jz_gpio_bulk_request jz_lcd_ctrl_pins[] = {
+        JZ_GPIO_BULK_PIN(LCD_PCLK),
+        JZ_GPIO_BULK_PIN(LCD_HSYNC),
+        JZ_GPIO_BULK_PIN(LCD_VSYNC),
+        JZ_GPIO_BULK_PIN(LCD_DE),
+        JZ_GPIO_BULK_PIN(LCD_PS),
+        JZ_GPIO_BULK_PIN(LCD_REV),
+        JZ_GPIO_BULK_PIN(LCD_CLS),
+        JZ_GPIO_BULK_PIN(LCD_SPL),
+};
+
+static const struct jz_gpio_bulk_request jz_lcd_data_pins[] = {
+        JZ_GPIO_BULK_PIN(LCD_DATA0),
+        JZ_GPIO_BULK_PIN(LCD_DATA1),
+        JZ_GPIO_BULK_PIN(LCD_DATA2),
+        JZ_GPIO_BULK_PIN(LCD_DATA3),
+        JZ_GPIO_BULK_PIN(LCD_DATA4),
+        JZ_GPIO_BULK_PIN(LCD_DATA5),
+        JZ_GPIO_BULK_PIN(LCD_DATA6),
+        JZ_GPIO_BULK_PIN(LCD_DATA7),
+        JZ_GPIO_BULK_PIN(LCD_DATA8),
+        JZ_GPIO_BULK_PIN(LCD_DATA9),
+        JZ_GPIO_BULK_PIN(LCD_DATA10),
+        JZ_GPIO_BULK_PIN(LCD_DATA11),
+        JZ_GPIO_BULK_PIN(LCD_DATA12),
+        JZ_GPIO_BULK_PIN(LCD_DATA13),
+        JZ_GPIO_BULK_PIN(LCD_DATA14),
+        JZ_GPIO_BULK_PIN(LCD_DATA15),
+        JZ_GPIO_BULK_PIN(LCD_DATA16),
+        JZ_GPIO_BULK_PIN(LCD_DATA17),
+};
+
+static unsigned int jzfb_num_ctrl_pins(struct jzfb *jzfb)
+{
+        unsigned int num;
+
+        switch (jzfb->pdata->lcd_type) {
+        case JZ_LCD_TYPE_GENERIC_16_BIT:
+                num = 4;
+                break;
+        case JZ_LCD_TYPE_GENERIC_18_BIT:
+                num = 4;
+                break;
+        case JZ_LCD_TYPE_8BIT_SERIAL:
+                num = 3;
+                break;
+        case JZ_LCD_TYPE_SPECIAL_TFT_1:
+        case JZ_LCD_TYPE_SPECIAL_TFT_2:
+        case JZ_LCD_TYPE_SPECIAL_TFT_3:
+                num = 8;
+                break;
+        default:
+                num = 0;
+                break;
+        }
+        return num;
+}
+
+static unsigned int jzfb_num_data_pins(struct jzfb *jzfb)
+{
+        unsigned int num;
+
+        switch (jzfb->pdata->lcd_type) {
+        case JZ_LCD_TYPE_GENERIC_16_BIT:
+                num = 16;
+                break;
+        case JZ_LCD_TYPE_GENERIC_18_BIT:
+                num = 18;
+                break;
+        case JZ_LCD_TYPE_8BIT_SERIAL:
+                num = 8;
+                break;
+        case JZ_LCD_TYPE_SPECIAL_TFT_1:
+        case JZ_LCD_TYPE_SPECIAL_TFT_2:
+        case JZ_LCD_TYPE_SPECIAL_TFT_3:
+                if (jzfb->pdata->bpp == 18)
+                        num = 18;
+                else
+                        num = 16;
+                break;
+        default:
+                num = 0;
+                break;
+        }
+        return num;
+}
+
+/* Based on CNVT_TOHW macro from skeletonfb.c */
+static inline uint32_t jzfb_convert_color_to_hw(unsigned val,
+        struct fb_bitfield *bf)
+{
+        return (((val << bf->length) + 0x7FFF - val) >> 16) << bf->offset;
+}
+
+static int jzfb_setcolreg(unsigned regno, unsigned red, unsigned green,
+                        unsigned blue, unsigned transp, struct fb_info *fb)
+{
+        uint32_t color;
+
+        if (regno >= 16)
+                return -EINVAL;
+
+        color = jzfb_convert_color_to_hw(red, &fb->var.red);
+        color |= jzfb_convert_color_to_hw(green, &fb->var.green);
+        color |= jzfb_convert_color_to_hw(blue, &fb->var.blue);
+        color |= jzfb_convert_color_to_hw(transp, &fb->var.transp);
+
+        ((uint32_t *)(fb->pseudo_palette))[regno] = color;
+
+        return 0;
+}
+
+static int jzfb_get_controller_bpp(struct jzfb *jzfb)
+{
+        switch (jzfb->pdata->bpp) {
+        case 18:
+        case 24:
+                return 32;
+        case 15:
+                return 16;
+        default:
+                return jzfb->pdata->bpp;
+        }
+}
+
+static struct fb_videomode *jzfb_get_mode(struct jzfb *jzfb,
+        struct fb_var_screeninfo *var)
+{
+        size_t i;
+        struct fb_videomode *mode = jzfb->pdata->modes;
+
+        for (i = 0; i < jzfb->pdata->num_modes; ++i, ++mode) {
+                if (mode->xres == var->xres && mode->yres == var->yres)
+                        return mode;
+        }
+
+        return NULL;
+}
+
+static int jzfb_check_var(struct fb_var_screeninfo *var, struct fb_info *fb)
+{
+        struct jzfb *jzfb = fb->par;
+        struct fb_videomode *mode;
+
+        if (var->bits_per_pixel != jzfb_get_controller_bpp(jzfb) &&
+                var->bits_per_pixel != jzfb->pdata->bpp)
+                return -EINVAL;
+
+        mode = jzfb_get_mode(jzfb, var);
+        if (mode == NULL)
+                return -EINVAL;
+
+        fb_videomode_to_var(var, mode);
+
+        switch (jzfb->pdata->bpp) {
+        case 8:
+                break;
+        case 15:
+                var->red.offset = 10;
+                var->red.length = 5;
+                var->green.offset = 6;
+                var->green.length = 5;
+                var->blue.offset = 0;
+                var->blue.length = 5;
+                break;
+        case 16:
+                var->red.offset = 11;
+                var->red.length = 5;
+                var->green.offset = 5;
+                var->green.length = 6;
+                var->blue.offset = 0;
+                var->blue.length = 5;
+                break;
+        case 18:
+                var->red.offset = 16;
+                var->red.length = 6;
+                var->green.offset = 8;
+                var->green.length = 6;
+                var->blue.offset = 0;
+                var->blue.length = 6;
+                var->bits_per_pixel = 32;
+                break;
+        case 32:
+        case 24:
+                var->transp.offset = 24;
+                var->transp.length = 8;
+                var->red.offset = 16;
+                var->red.length = 8;
+                var->green.offset = 8;
+                var->green.length = 8;
+                var->blue.offset = 0;
+                var->blue.length = 8;
+                var->bits_per_pixel = 32;
+                break;
+        default:
+                break;
+        }
+
+        return 0;
+}
+
+static int jzfb_set_par(struct fb_info *info)
+{
+        struct jzfb *jzfb = info->par;
+        struct jz4740_fb_platform_data *pdata = jzfb->pdata;
+        struct fb_var_screeninfo *var = &info->var;
+        struct fb_videomode *mode;
+        uint16_t hds, vds;
+        uint16_t hde, vde;
+        uint16_t ht, vt;
+        uint32_t ctrl;
+        uint32_t cfg;
+        unsigned long rate;
+
+        mode = jzfb_get_mode(jzfb, var);
+        if (mode == NULL)
+                return -EINVAL;
+
+        if (mode == info->mode)
+                return 0;
+
+        info->mode = mode;
+
+        hds = mode->hsync_len + mode->left_margin;
+        hde = hds + mode->xres;
+        ht = hde + mode->right_margin;
+
+        vds = mode->vsync_len + mode->upper_margin;
+        vde = vds + mode->yres;
+        vt = vde + mode->lower_margin;
+
+        ctrl = JZ_LCD_CTRL_OFUP | JZ_LCD_CTRL_BURST_16;
+
+        switch (pdata->bpp) {
+        case 1:
+                ctrl |= JZ_LCD_CTRL_BPP_1;
+                break;
+        case 2:
+                ctrl |= JZ_LCD_CTRL_BPP_2;
+                break;
+        case 4:
+                ctrl |= JZ_LCD_CTRL_BPP_4;
+                break;
+        case 8:
+                ctrl |= JZ_LCD_CTRL_BPP_8;
+        break;
+        case 15:
+                ctrl |= JZ_LCD_CTRL_RGB555; /* Falltrough */
+        case 16:
+                ctrl |= JZ_LCD_CTRL_BPP_15_16;
+                break;
+        case 18:
+        case 24:
+        case 32:
+                ctrl |= JZ_LCD_CTRL_BPP_18_24;
+                break;
+        default:
+                break;
+        }
+
+        cfg = pdata->lcd_type & 0xf;
+
+        if (!(mode->sync & FB_SYNC_HOR_HIGH_ACT))
+                cfg |= JZ_LCD_CFG_HSYNC_ACTIVE_LOW;
+
+        if (!(mode->sync & FB_SYNC_VERT_HIGH_ACT))
+                cfg |= JZ_LCD_CFG_VSYNC_ACTIVE_LOW;
+
+        if (pdata->pixclk_falling_edge)
+                cfg |= JZ_LCD_CFG_PCLK_FALLING_EDGE;
+
+        if (pdata->date_enable_active_low)
+                cfg |= JZ_LCD_CFG_DE_ACTIVE_LOW;
+
+        if (pdata->lcd_type == JZ_LCD_TYPE_GENERIC_18_BIT)
+                cfg |= JZ_LCD_CFG_18_BIT;
+
+        if (mode->pixclock) {
+                rate = PICOS2KHZ(mode->pixclock) * 1000;
+                mode->refresh = rate / vt / ht;
+        } else {
+                if (pdata->lcd_type == JZ_LCD_TYPE_8BIT_SERIAL)
+                        rate = mode->refresh * (vt + 2 * mode->xres) * ht;
+                else
+                        rate = mode->refresh * vt * ht;
+
+                mode->pixclock = KHZ2PICOS(rate / 1000);
+        }
+
+        mutex_lock(&jzfb->lock);
+        if (!jzfb->is_enabled)
+                clk_enable(jzfb->ldclk);
+        else
+                ctrl |= JZ_LCD_CTRL_ENABLE;
+
+        switch (pdata->lcd_type) {
+        case JZ_LCD_TYPE_SPECIAL_TFT_1:
+        case JZ_LCD_TYPE_SPECIAL_TFT_2:
+        case JZ_LCD_TYPE_SPECIAL_TFT_3:
+                writel(pdata->special_tft_config.spl, jzfb->base + JZ_REG_LCD_SPL);
+                writel(pdata->special_tft_config.cls, jzfb->base + JZ_REG_LCD_CLS);
+                writel(pdata->special_tft_config.ps, jzfb->base + JZ_REG_LCD_PS);
+                writel(pdata->special_tft_config.ps, jzfb->base + JZ_REG_LCD_REV);
+                break;
+        default:
+                cfg |= JZ_LCD_CFG_PS_DISABLE;
+                cfg |= JZ_LCD_CFG_CLS_DISABLE;
+                cfg |= JZ_LCD_CFG_SPL_DISABLE;
+                cfg |= JZ_LCD_CFG_REV_DISABLE;
+                break;
+        }
+
+        writel(mode->hsync_len, jzfb->base + JZ_REG_LCD_HSYNC);
+        writel(mode->vsync_len, jzfb->base + JZ_REG_LCD_VSYNC);
+
+        writel((ht << 16) | vt, jzfb->base + JZ_REG_LCD_VAT);
+
+        writel((hds << 16) | hde, jzfb->base + JZ_REG_LCD_DAH);
+        writel((vds << 16) | vde, jzfb->base + JZ_REG_LCD_DAV);
+
+        writel(cfg, jzfb->base + JZ_REG_LCD_CFG);
+
+        writel(ctrl, jzfb->base + JZ_REG_LCD_CTRL);
+
+        if (!jzfb->is_enabled)
+                clk_disable(jzfb->ldclk);
+
+        mutex_unlock(&jzfb->lock);
+
+        clk_set_rate(jzfb->lpclk, rate);
+        clk_set_rate(jzfb->ldclk, rate * 3);
+
+        return 0;
+}
+
+static void jzfb_enable(struct jzfb *jzfb)
+{
+        uint32_t ctrl;
+
+        clk_enable(jzfb->ldclk);
+
+        jz_gpio_bulk_resume(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb));
+        jz_gpio_bulk_resume(jz_lcd_data_pins, jzfb_num_data_pins(jzfb));
+
+        writel(0, jzfb->base + JZ_REG_LCD_STATE);
+
+        writel(jzfb->framedesc->next, jzfb->base + JZ_REG_LCD_DA0);
+
+        ctrl = readl(jzfb->base + JZ_REG_LCD_CTRL);
+        ctrl |= JZ_LCD_CTRL_ENABLE;
+        ctrl &= ~JZ_LCD_CTRL_DISABLE;
+        writel(ctrl, jzfb->base + JZ_REG_LCD_CTRL);
+}
+
+static void jzfb_disable(struct jzfb *jzfb)
+{
+        uint32_t ctrl;
+
+        ctrl = readl(jzfb->base + JZ_REG_LCD_CTRL);
+        ctrl |= JZ_LCD_CTRL_DISABLE;
+        writel(ctrl, jzfb->base + JZ_REG_LCD_CTRL);
+        do {
+                ctrl = readl(jzfb->base + JZ_REG_LCD_STATE);
+        } while (!(ctrl & JZ_LCD_STATE_DISABLED));
+
+        jz_gpio_bulk_suspend(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb));
+        jz_gpio_bulk_suspend(jz_lcd_data_pins, jzfb_num_data_pins(jzfb));
+
+        clk_disable(jzfb->ldclk);
+}
+
+static int jzfb_blank(int blank_mode, struct fb_info *info)
+{
+        struct jzfb *jzfb = info->par;
+
+        switch (blank_mode) {
+        case FB_BLANK_UNBLANK:
+                mutex_lock(&jzfb->lock);
+                if (jzfb->is_enabled) {
+                        mutex_unlock(&jzfb->lock);
+                        return 0;
+                }
+
+                jzfb_enable(jzfb);
+                jzfb->is_enabled = 1;
+
+                mutex_unlock(&jzfb->lock);
+                break;
+        default:
+                mutex_lock(&jzfb->lock);
+                if (!jzfb->is_enabled) {
+                        mutex_unlock(&jzfb->lock);
+                        return 0;
+                }
+
+                jzfb_disable(jzfb);
+                jzfb->is_enabled = 0;
+
+                mutex_unlock(&jzfb->lock);
+                break;
+        }
+
+        return 0;
+}
+
+static int jzfb_alloc_devmem(struct jzfb *jzfb)
+{
+        int max_videosize = 0;
+        struct fb_videomode *mode = jzfb->pdata->modes;
+        void *page;
+        int i;
+
+        for (i = 0; i < jzfb->pdata->num_modes; ++mode, ++i) {
+                if (max_videosize < mode->xres * mode->yres)
+                        max_videosize = mode->xres * mode->yres;
+        }
+
+        max_videosize *= jzfb_get_controller_bpp(jzfb) >> 3;
+
+        jzfb->framedesc = dma_alloc_coherent(&jzfb->pdev->dev,
+                                        sizeof(*jzfb->framedesc),
+                                        &jzfb->framedesc_phys, GFP_KERNEL);
+
+        if (!jzfb->framedesc)
+                return -ENOMEM;
+
+        jzfb->vidmem_size = PAGE_ALIGN(max_videosize);
+        jzfb->vidmem = dma_alloc_coherent(&jzfb->pdev->dev,
+                                        jzfb->vidmem_size,
+                                        &jzfb->vidmem_phys, GFP_KERNEL);
+
+        if (!jzfb->vidmem)
+                goto err_free_framedesc;
+
+        for (page = jzfb->vidmem;
+                 page < jzfb->vidmem + PAGE_ALIGN(jzfb->vidmem_size);
+                 page += PAGE_SIZE) {
+                SetPageReserved(virt_to_page(page));
+        }
+
+        jzfb->framedesc->next = jzfb->framedesc_phys;
+        jzfb->framedesc->addr = jzfb->vidmem_phys;
+        jzfb->framedesc->id = 0xdeafbead;
+        jzfb->framedesc->cmd = 0;
+        jzfb->framedesc->cmd |= max_videosize / 4;
+
+        return 0;
+
+err_free_framedesc:
+        dma_free_coherent(&jzfb->pdev->dev, sizeof(*jzfb->framedesc),
+                                jzfb->framedesc, jzfb->framedesc_phys);
+        return -ENOMEM;
+}
+
+static void jzfb_free_devmem(struct jzfb *jzfb)
+{
+        dma_free_coherent(&jzfb->pdev->dev, jzfb->vidmem_size,
+                                jzfb->vidmem, jzfb->vidmem_phys);
+        dma_free_coherent(&jzfb->pdev->dev, sizeof(*jzfb->framedesc),
+                                jzfb->framedesc, jzfb->framedesc_phys);
+}
+
+static struct  fb_ops jzfb_ops = {
+        .owner = THIS_MODULE,
+        .fb_check_var = jzfb_check_var,
+        .fb_set_par = jzfb_set_par,
+        .fb_blank = jzfb_blank,
+        .fb_fillrect    = sys_fillrect,
+        .fb_copyarea    = sys_copyarea,
+        .fb_imageblit   = sys_imageblit,
+        .fb_setcolreg = jzfb_setcolreg,
+};
+
+static int __devinit jzfb_probe(struct platform_device *pdev)
+{
+        int ret;
+        struct jzfb *jzfb;
+        struct fb_info *fb;
+        struct jz4740_fb_platform_data *pdata = pdev->dev.platform_data;
+        struct resource *mem;
+
+        if (!pdata) {
+                dev_err(&pdev->dev, "Missing platform data\n");
+                return -ENXIO;
+        }
+
+        mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!mem) {
+                dev_err(&pdev->dev, "Failed to get register memory resource\n");
+                return -ENXIO;
+        }
+
+        mem = request_mem_region(mem->start, resource_size(mem), pdev->name);
+        if (!mem) {
+                dev_err(&pdev->dev, "Failed to request register memory region\n");
+                return -EBUSY;
+        }
+
+        fb = framebuffer_alloc(sizeof(struct jzfb), &pdev->dev);
+        if (!fb) {
+                dev_err(&pdev->dev, "Failed to allocate framebuffer device\n");
+                ret = -ENOMEM;
+                goto err_release_mem_region;
+        }
+
+        fb->fbops = &jzfb_ops;
+        fb->flags = FBINFO_DEFAULT;
+
+        jzfb = fb->par;
+        jzfb->pdev = pdev;
+        jzfb->pdata = pdata;
+        jzfb->mem = mem;
+
+        jzfb->ldclk = clk_get(&pdev->dev, "lcd");
+        if (IS_ERR(jzfb->ldclk)) {
+                ret = PTR_ERR(jzfb->ldclk);
+                dev_err(&pdev->dev, "Failed to get lcd clock: %d\n", ret);
+                goto err_framebuffer_release;
+        }
+
+        jzfb->lpclk = clk_get(&pdev->dev, "lcd_pclk");
+        if (IS_ERR(jzfb->lpclk)) {
+                ret = PTR_ERR(jzfb->lpclk);
+                dev_err(&pdev->dev, "Failed to get lcd pixel clock: %d\n", ret);
+                goto err_put_ldclk;
+        }
+
+        jzfb->base = ioremap(mem->start, resource_size(mem));
+        if (!jzfb->base) {
+                dev_err(&pdev->dev, "Failed to ioremap register memory region\n");
+                ret = -EBUSY;
+                goto err_put_lpclk;
+        }
+
+        platform_set_drvdata(pdev, jzfb);
+
+        mutex_init(&jzfb->lock);
+
+        fb_videomode_to_modelist(pdata->modes, pdata->num_modes,
+                                 &fb->modelist);
+        fb_videomode_to_var(&fb->var, pdata->modes);
+        fb->var.bits_per_pixel = pdata->bpp;
+        jzfb_check_var(&fb->var, fb);
+
+        ret = jzfb_alloc_devmem(jzfb);
+        if (ret) {
+                dev_err(&pdev->dev, "Failed to allocate video memory\n");
+                goto err_iounmap;
+        }
+
+        fb->fix = jzfb_fix;
+        fb->fix.line_length = fb->var.bits_per_pixel * fb->var.xres / 8;
+        fb->fix.mmio_start = mem->start;
+        fb->fix.mmio_len = resource_size(mem);
+        fb->fix.smem_start = jzfb->vidmem_phys;
+        fb->fix.smem_len =  fb->fix.line_length * fb->var.yres;
+        fb->screen_base = jzfb->vidmem;
+        fb->pseudo_palette = jzfb->pseudo_palette;
+
+        fb_alloc_cmap(&fb->cmap, 256, 0);
+
+        clk_enable(jzfb->ldclk);
+        jzfb->is_enabled = 1;
+
+        writel(jzfb->framedesc->next, jzfb->base + JZ_REG_LCD_DA0);
+
+        fb->mode = NULL;
+        jzfb_set_par(fb);
+
+        jz_gpio_bulk_request(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb));
+        jz_gpio_bulk_request(jz_lcd_data_pins, jzfb_num_data_pins(jzfb));
+
+        ret = register_framebuffer(fb);
+        if (ret) {
+                dev_err(&pdev->dev, "Failed to register framebuffer: %d\n", ret);
+                goto err_free_devmem;
+        }
+
+        jzfb->fb = fb;
+
+        return 0;
+
+err_free_devmem:
+        jz_gpio_bulk_free(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb));
+        jz_gpio_bulk_free(jz_lcd_data_pins, jzfb_num_data_pins(jzfb));
+
+        fb_dealloc_cmap(&fb->cmap);
+        jzfb_free_devmem(jzfb);
+err_iounmap:
+        iounmap(jzfb->base);
+err_put_lpclk:
+        clk_put(jzfb->lpclk);
+err_put_ldclk:
+        clk_put(jzfb->ldclk);
+err_framebuffer_release:
+        framebuffer_release(fb);
+err_release_mem_region:
+        release_mem_region(mem->start, resource_size(mem));
+        return ret;
+}
+
+static int __devexit jzfb_remove(struct platform_device *pdev)
+{
+        struct jzfb *jzfb = platform_get_drvdata(pdev);
+
+        jzfb_blank(FB_BLANK_POWERDOWN, jzfb->fb);
+
+        jz_gpio_bulk_free(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb));
+        jz_gpio_bulk_free(jz_lcd_data_pins, jzfb_num_data_pins(jzfb));
+
+        iounmap(jzfb->base);
+        release_mem_region(jzfb->mem->start, resource_size(jzfb->mem));
+
+        fb_dealloc_cmap(&jzfb->fb->cmap);
+        jzfb_free_devmem(jzfb);
+
+        platform_set_drvdata(pdev, NULL);
+
+        clk_put(jzfb->lpclk);
+        clk_put(jzfb->ldclk);
+
+        framebuffer_release(jzfb->fb);
+
+        return 0;
+}
+
+#ifdef CONFIG_PM
+
+static int jzfb_suspend(struct device *dev)
+{
+        struct jzfb *jzfb = dev_get_drvdata(dev);
+
+        acquire_console_sem();
+        fb_set_suspend(jzfb->fb, 1);
+        release_console_sem();
+
+        mutex_lock(&jzfb->lock);
+        if (jzfb->is_enabled)
+                jzfb_disable(jzfb);
+        mutex_unlock(&jzfb->lock);
+
+        return 0;
+}
+
+static int jzfb_resume(struct device *dev)
+{
+        struct jzfb *jzfb = dev_get_drvdata(dev);
+        clk_enable(jzfb->ldclk);
+
+        mutex_lock(&jzfb->lock);
+        if (jzfb->is_enabled)
+                jzfb_enable(jzfb);
+        mutex_unlock(&jzfb->lock);
+
+        acquire_console_sem();
+        fb_set_suspend(jzfb->fb, 0);
+        release_console_sem();
+
+        return 0;
+}
+
+static const struct dev_pm_ops jzfb_pm_ops = {
+        .suspend        = jzfb_suspend,
+        .resume         = jzfb_resume,
+        .poweroff       = jzfb_suspend,
+        .restore        = jzfb_resume,
+};
+
+#define JZFB_PM_OPS (&jzfb_pm_ops)
+
+#else
+#define JZFB_PM_OPS NULL
+#endif
+
+static struct platform_driver jzfb_driver = {
+        .probe = jzfb_probe,
+        .remove = __devexit_p(jzfb_remove),
+        .driver = {
+                .name = "jz4740-fb",
+                .pm = JZFB_PM_OPS,
+        },
+};
+
+static int __init jzfb_init(void)
+{
+        return platform_driver_register(&jzfb_driver);
+}
+module_init(jzfb_init);
+
+static void __exit jzfb_exit(void)
+{
+        platform_driver_unregister(&jzfb_driver);
+}
+module_exit(jzfb_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
+MODULE_DESCRIPTION("JZ4740 SoC LCD framebuffer driver");
+MODULE_ALIAS("platform:jz4740-fb");
diff --git a/drivers/video/tdfxfb.c b/drivers/video/tdfxfb.c
index 980548390048..3ee5e63cfa4f 100644
--- a/drivers/video/tdfxfb.c
+++ b/drivers/video/tdfxfb.c
@@ -1571,8 +1571,8 @@ out_err_iobase:
         if (default_par->mtrr_handle >= 0)
                 mtrr_del(default_par->mtrr_handle, info->fix.smem_start,
                          info->fix.smem_len);
-        release_mem_region(pci_resource_start(pdev, 2),
-                           pci_resource_len(pdev, 2));
+        release_region(pci_resource_start(pdev, 2),
+                       pci_resource_len(pdev, 2));
 out_err_screenbase:
         if (info->screen_base)
                 iounmap(info->screen_base);
diff --git a/drivers/video/xen-fbfront.c b/drivers/video/xen-fbfront.c
index fa97d3e7c21a..7c7f42a12796 100644
--- a/drivers/video/xen-fbfront.c
+++ b/drivers/video/xen-fbfront.c
@@ -684,7 +684,7 @@ static struct xenbus_driver xenfb_driver = {
 
 static int __init xenfb_init(void)
 {
-        if (!xen_domain())
+        if (!xen_pv_domain())
                 return -ENODEV;
 
         /* Nothing to do if running in dom0. */
diff --git a/drivers/video/xilinxfb.c b/drivers/video/xilinxfb.c
index 574dc54e12d4..29b5daacc217 100644
--- a/drivers/video/xilinxfb.c
+++ b/drivers/video/xilinxfb.c
@@ -485,6 +485,8 @@ static int __devexit xilinxfb_of_remove(struct of_device *op)
 /* Match table for of_platform binding */
 static struct of_device_id xilinxfb_of_match[] __devinitdata = {
         { .compatible = "xlnx,xps-tft-1.00.a", },
+        { .compatible = "xlnx,xps-tft-2.00.a", },
+        { .compatible = "xlnx,xps-tft-2.01.a", },
         { .compatible = "xlnx,plb-tft-cntlr-ref-1.00.a", },
         { .compatible = "xlnx,plb-dvi-cntlr-ref-1.00.c", },
         {},
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index afcfacc9bbe2..b04b18468932 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -875,6 +875,24 @@ config TXX9_WDT
         help
           Hardware driver for the built-in watchdog timer on TXx9 MIPS SoCs.
 
+config OCTEON_WDT
+        tristate "Cavium OCTEON SOC family Watchdog Timer"
+        depends on CPU_CAVIUM_OCTEON
+        default y
+        select EXPORT_UASM if OCTEON_WDT = m
+        help
+          Hardware driver for OCTEON's on chip watchdog timer.
+          Enables the watchdog for all cores running Linux. It
+          installs a NMI handler and pokes the watchdog based on an
+          interrupt.  On first expiration of the watchdog, the
+          interrupt handler pokes it.  The second expiration causes an
+          NMI that prints a message. The third expiration causes a
+          global soft reset.
+
+          When userspace has /dev/watchdog open, no poking is done
+          from the first interrupt, it is then only poked when the
+          device is written.
+
 # PARISC Architecture
 
 # POWERPC Architecture
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 72f3e2073f8e..e30289a5e367 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -114,6 +114,8 @@ obj-$(CONFIG_PNX833X_WDT) += pnx833x_wdt.o
 obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o
 obj-$(CONFIG_AR7_WDT) += ar7_wdt.o
 obj-$(CONFIG_TXX9_WDT) += txx9wdt.o
+obj-$(CONFIG_OCTEON_WDT) += octeon-wdt.o
+octeon-wdt-y := octeon-wdt-main.o octeon-wdt-nmi.o
 
 # PARISC Architecture
 
diff --git a/drivers/watchdog/octeon-wdt-main.c b/drivers/watchdog/octeon-wdt-main.c
new file mode 100644
index 000000000000..2a410170eca6
--- /dev/null
+++ b/drivers/watchdog/octeon-wdt-main.c
@@ -0,0 +1,745 @@
+/*
+ * Octeon Watchdog driver
+ *
+ * Copyright (C) 2007, 2008, 2009, 2010 Cavium Networks
+ *
+ * Some parts derived from wdt.c
+ *
+ *      (c) Copyright 1996-1997 Alan Cox <alan@lxorguk.ukuu.org.uk>,
+ *                                              All Rights Reserved.
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ *
+ *      Neither Alan Cox nor CymruNet Ltd. admit liability nor provide
+ *      warranty for any of this software. This material is provided
+ *      "AS-IS" and at no charge.
+ *
+ *      (c) Copyright 1995    Alan Cox <alan@lxorguk.ukuu.org.uk>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ *
+ * The OCTEON watchdog has a maximum timeout of 2^32 * io_clock.
+ * For most systems this is less than 10 seconds, so to allow for
+ * software to request longer watchdog heartbeats, we maintain software
+ * counters to count multiples of the base rate.  If the system locks
+ * up in such a manner that we can not run the software counters, the
+ * only result is a watchdog reset sooner than was requested.  But
+ * that is OK, because in this case userspace would likely not be able
+ * to do anything anyhow.
+ *
+ * The hardware watchdog interval we call the period.  The OCTEON
+ * watchdog goes through several stages, after the first period an
+ * irq is asserted, then if it is not reset, after the next period NMI
+ * is asserted, then after an additional period a chip wide soft reset.
+ * So for the software counters, we reset watchdog after each period
+ * and decrement the counter.  But for the last two periods we need to
+ * let the watchdog progress to the NMI stage so we disable the irq
+ * and let it proceed.  Once in the NMI, we print the register state
+ * to the serial port and then wait for the reset.
+ *
+ * A watchdog is maintained for each CPU in the system, that way if
+ * one CPU suffers a lockup, we also get a register dump and reset.
+ * The userspace ping resets the watchdog on all CPUs.
+ *
+ * Before userspace opens the watchdog device, we still run the
+ * watchdogs to catch any lockups that may be kernel related.
+ *
+ */
+
+#include <linux/miscdevice.h>
+#include <linux/interrupt.h>
+#include <linux/watchdog.h>
+#include <linux/cpumask.h>
+#include <linux/bitops.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/string.h>
+#include <linux/delay.h>
+#include <linux/cpu.h>
+#include <linux/smp.h>
+#include <linux/fs.h>
+
+#include <asm/mipsregs.h>
+#include <asm/uasm.h>
+
+#include <asm/octeon/octeon.h>
+
+/* The count needed to achieve timeout_sec. */
+static unsigned int timeout_cnt;
+
+/* The maximum period supported. */
+static unsigned int max_timeout_sec;
+
+/* The current period.  */
+static unsigned int timeout_sec;
+
+/* Set to non-zero when userspace countdown mode active */
+static int do_coundown;
+static unsigned int countdown_reset;
+static unsigned int per_cpu_countdown[NR_CPUS];
+
+static cpumask_t irq_enabled_cpus;
+
+#define WD_TIMO 60                      /* Default heartbeat = 60 seconds */
+
+static int heartbeat = WD_TIMO;
+module_param(heartbeat, int, S_IRUGO);
+MODULE_PARM_DESC(heartbeat,
+        "Watchdog heartbeat in seconds. (0 < heartbeat, default="
+                                __MODULE_STRING(WD_TIMO) ")");
+
+static int nowayout = WATCHDOG_NOWAYOUT;
+module_param(nowayout, int, S_IRUGO);
+MODULE_PARM_DESC(nowayout,
+        "Watchdog cannot be stopped once started (default="
+                                __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
+
+static unsigned long octeon_wdt_is_open;
+static char expect_close;
+
+static u32 __initdata nmi_stage1_insns[64];
+/* We need one branch and therefore one relocation per target label. */
+static struct uasm_label __initdata labels[5];
+static struct uasm_reloc __initdata relocs[5];
+
+enum lable_id {
+        label_enter_bootloader = 1
+};
+
+/* Some CP0 registers */
+#define K0              26
+#define C0_CVMMEMCTL 11, 7
+#define C0_STATUS 12, 0
+#define C0_EBASE 15, 1
+#define C0_DESAVE 31, 0
+
+void octeon_wdt_nmi_stage2(void);
+
+static void __init octeon_wdt_build_stage1(void)
+{
+        int i;
+        int len;
+        u32 *p = nmi_stage1_insns;
+#ifdef CONFIG_HOTPLUG_CPU
+        struct uasm_label *l = labels;
+        struct uasm_reloc *r = relocs;
+#endif
+
+        /*
+         * For the next few instructions running the debugger may
+         * cause corruption of k0 in the saved registers. Since we're
+         * about to crash, nobody probably cares.
+         *
+         * Save K0 into the debug scratch register
+         */
+        uasm_i_dmtc0(&p, K0, C0_DESAVE);
+
+        uasm_i_mfc0(&p, K0, C0_STATUS);
+#ifdef CONFIG_HOTPLUG_CPU
+        uasm_il_bbit0(&p, &r, K0, ilog2(ST0_NMI), label_enter_bootloader);
+#endif
+        /* Force 64-bit addressing enabled */
+        uasm_i_ori(&p, K0, K0, ST0_UX | ST0_SX | ST0_KX);
+        uasm_i_mtc0(&p, K0, C0_STATUS);
+
+#ifdef CONFIG_HOTPLUG_CPU
+        uasm_i_mfc0(&p, K0, C0_EBASE);
+        /* Coreid number in K0 */
+        uasm_i_andi(&p, K0, K0, 0xf);
+        /* 8 * coreid in bits 16-31 */
+        uasm_i_dsll_safe(&p, K0, K0, 3 + 16);
+        uasm_i_ori(&p, K0, K0, 0x8001);
+        uasm_i_dsll_safe(&p, K0, K0, 16);
+        uasm_i_ori(&p, K0, K0, 0x0700);
+        uasm_i_drotr_safe(&p, K0, K0, 32);
+        /*
+         * Should result in: 0x8001,0700,0000,8*coreid which is
+         * CVMX_CIU_WDOGX(coreid) - 0x0500
+         *
+         * Now ld K0, CVMX_CIU_WDOGX(coreid)
+         */
+        uasm_i_ld(&p, K0, 0x500, K0);
+        /*
+         * If bit one set handle the NMI as a watchdog event.
+         * otherwise transfer control to bootloader.
+         */
+        uasm_il_bbit0(&p, &r, K0, 1, label_enter_bootloader);
+        uasm_i_nop(&p);
+#endif
+
+        /* Clear Dcache so cvmseg works right. */
+        uasm_i_cache(&p, 1, 0, 0);
+
+        /* Use K0 to do a read/modify/write of CVMMEMCTL */
+        uasm_i_dmfc0(&p, K0, C0_CVMMEMCTL);
+        /* Clear out the size of CVMSEG */
+        uasm_i_dins(&p, K0, 0, 0, 6);
+        /* Set CVMSEG to its largest value */
+        uasm_i_ori(&p, K0, K0, 0x1c0 | 54);
+        /* Store the CVMMEMCTL value */
+        uasm_i_dmtc0(&p, K0, C0_CVMMEMCTL);
+
+        /* Load the address of the second stage handler */
+        UASM_i_LA(&p, K0, (long)octeon_wdt_nmi_stage2);
+        uasm_i_jr(&p, K0);
+        uasm_i_dmfc0(&p, K0, C0_DESAVE);
+
+#ifdef CONFIG_HOTPLUG_CPU
+        uasm_build_label(&l, p, label_enter_bootloader);
+        /* Jump to the bootloader and restore K0 */
+        UASM_i_LA(&p, K0, (long)octeon_bootloader_entry_addr);
+        uasm_i_jr(&p, K0);
+        uasm_i_dmfc0(&p, K0, C0_DESAVE);
+#endif
+        uasm_resolve_relocs(relocs, labels);
+
+        len = (int)(p - nmi_stage1_insns);
+        pr_debug("Synthesized NMI stage 1 handler (%d instructions).\n", len);
+
+        pr_debug("\t.set push\n");
+        pr_debug("\t.set noreorder\n");
+        for (i = 0; i < len; i++)
+                pr_debug("\t.word 0x%08x\n", nmi_stage1_insns[i]);
+        pr_debug("\t.set pop\n");
+
+        if (len > 32)
+                panic("NMI stage 1 handler exceeds 32 instructions, was %d\n", len);
+}
+
+static int cpu2core(int cpu)
+{
+#ifdef CONFIG_SMP
+        return cpu_logical_map(cpu);
+#else
+        return cvmx_get_core_num();
+#endif
+}
+
+static int core2cpu(int coreid)
+{
+#ifdef CONFIG_SMP
+        return cpu_number_map(coreid);
+#else
+        return 0;
+#endif
+}
+
+/**
+ * Poke the watchdog when an interrupt is received
+ *
+ * @cpl:
+ * @dev_id:
+ *
+ * Returns
+ */
+static irqreturn_t octeon_wdt_poke_irq(int cpl, void *dev_id)
+{
+        unsigned int core = cvmx_get_core_num();
+        int cpu = core2cpu(core);
+
+        if (do_coundown) {
+                if (per_cpu_countdown[cpu] > 0) {
+                        /* We're alive, poke the watchdog */
+                        cvmx_write_csr(CVMX_CIU_PP_POKEX(core), 1);
+                        per_cpu_countdown[cpu]--;
+                } else {
+                        /* Bad news, you are about to reboot. */
+                        disable_irq_nosync(cpl);
+                        cpumask_clear_cpu(cpu, &irq_enabled_cpus);
+                }
+        } else {
+                /* Not open, just ping away... */
+                cvmx_write_csr(CVMX_CIU_PP_POKEX(core), 1);
+        }
+        return IRQ_HANDLED;
+}
+
+/* From setup.c */
+extern int prom_putchar(char c);
+
+/**
+ * Write a string to the uart
+ *
+ * @str:        String to write
+ */
+static void octeon_wdt_write_string(const char *str)
+{
+        /* Just loop writing one byte at a time */
+        while (*str)
+                prom_putchar(*str++);
+}
+
+/**
+ * Write a hex number out of the uart
+ *
+ * @value:      Number to display
+ * @digits:     Number of digits to print (1 to 16)
+ */
+static void octeon_wdt_write_hex(u64 value, int digits)
+{
+        int d;
+        int v;
+        for (d = 0; d < digits; d++) {
+                v = (value >> ((digits - d - 1) * 4)) & 0xf;
+                if (v >= 10)
+                        prom_putchar('a' + v - 10);
+                else
+                        prom_putchar('0' + v);
+        }
+}
+
+const char *reg_name[] = {
+        "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
+        "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
+        "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
+        "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
+};
+
+/**
+ * NMI stage 3 handler. NMIs are handled in the following manner:
+ * 1) The first NMI handler enables CVMSEG and transfers from
+ * the bootbus region into normal memory. It is careful to not
+ * destroy any registers.
+ * 2) The second stage handler uses CVMSEG to save the registers
+ * and create a stack for C code. It then calls the third level
+ * handler with one argument, a pointer to the register values.
+ * 3) The third, and final, level handler is the following C
+ * function that prints out some useful infomration.
+ *
+ * @reg:    Pointer to register state before the NMI
+ */
+void octeon_wdt_nmi_stage3(u64 reg[32])
+{
+        u64 i;
+
+        unsigned int coreid = cvmx_get_core_num();
+        /*
+         * Save status and cause early to get them before any changes
+         * might happen.
+         */
+        u64 cp0_cause = read_c0_cause();
+        u64 cp0_status = read_c0_status();
+        u64 cp0_error_epc = read_c0_errorepc();
+        u64 cp0_epc = read_c0_epc();
+
+        /* Delay so output from all cores output is not jumbled together. */
+        __delay(100000000ull * coreid);
+
+        octeon_wdt_write_string("\r\n*** NMI Watchdog interrupt on Core 0x");
+        octeon_wdt_write_hex(coreid, 1);
+        octeon_wdt_write_string(" ***\r\n");
+        for (i = 0; i < 32; i++) {
+                octeon_wdt_write_string("\t");
+                octeon_wdt_write_string(reg_name[i]);
+                octeon_wdt_write_string("\t0x");
+                octeon_wdt_write_hex(reg[i], 16);
+                if (i & 1)
+                        octeon_wdt_write_string("\r\n");
+        }
+        octeon_wdt_write_string("\terr_epc\t0x");
+        octeon_wdt_write_hex(cp0_error_epc, 16);
+
+        octeon_wdt_write_string("\tepc\t0x");
+        octeon_wdt_write_hex(cp0_epc, 16);
+        octeon_wdt_write_string("\r\n");
+
+        octeon_wdt_write_string("\tstatus\t0x");
+        octeon_wdt_write_hex(cp0_status, 16);
+        octeon_wdt_write_string("\tcause\t0x");
+        octeon_wdt_write_hex(cp0_cause, 16);
+        octeon_wdt_write_string("\r\n");
+
+        octeon_wdt_write_string("\tsum0\t0x");
+        octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU_INTX_SUM0(coreid * 2)), 16);
+        octeon_wdt_write_string("\ten0\t0x");
+        octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)), 16);
+        octeon_wdt_write_string("\r\n");
+
+        octeon_wdt_write_string("*** Chip soft reset soon ***\r\n");
+}
+
+static void octeon_wdt_disable_interrupt(int cpu)
+{
+        unsigned int core;
+        unsigned int irq;
+        union cvmx_ciu_wdogx ciu_wdog;
+
+        core = cpu2core(cpu);
+
+        irq = OCTEON_IRQ_WDOG0 + core;
+
+        /* Poke the watchdog to clear out its state */
+        cvmx_write_csr(CVMX_CIU_PP_POKEX(core), 1);
+
+        /* Disable the hardware. */
+        ciu_wdog.u64 = 0;
+        cvmx_write_csr(CVMX_CIU_WDOGX(core), ciu_wdog.u64);
+
+        free_irq(irq, octeon_wdt_poke_irq);
+}
+
+static void octeon_wdt_setup_interrupt(int cpu)
+{
+        unsigned int core;
+        unsigned int irq;
+        union cvmx_ciu_wdogx ciu_wdog;
+
+        core = cpu2core(cpu);
+
+        /* Disable it before doing anything with the interrupts. */
+        ciu_wdog.u64 = 0;
+        cvmx_write_csr(CVMX_CIU_WDOGX(core), ciu_wdog.u64);
+
+        per_cpu_countdown[cpu] = countdown_reset;
+
+        irq = OCTEON_IRQ_WDOG0 + core;
+
+        if (request_irq(irq, octeon_wdt_poke_irq,
+                        IRQF_DISABLED, "octeon_wdt", octeon_wdt_poke_irq))
+                panic("octeon_wdt: Couldn't obtain irq %d", irq);
+
+        cpumask_set_cpu(cpu, &irq_enabled_cpus);
+
+        /* Poke the watchdog to clear out its state */
+        cvmx_write_csr(CVMX_CIU_PP_POKEX(core), 1);
+
+        /* Finally enable the watchdog now that all handlers are installed */
+        ciu_wdog.u64 = 0;
+        ciu_wdog.s.len = timeout_cnt;
+        ciu_wdog.s.mode = 3;    /* 3 = Interrupt + NMI + Soft-Reset */
+        cvmx_write_csr(CVMX_CIU_WDOGX(core), ciu_wdog.u64);
+}
+
+static int octeon_wdt_cpu_callback(struct notifier_block *nfb,
+                                           unsigned long action, void *hcpu)
+{
+        unsigned int cpu = (unsigned long)hcpu;
+
+        switch (action) {
+        case CPU_DOWN_PREPARE:
+                octeon_wdt_disable_interrupt(cpu);
+                break;
+        case CPU_ONLINE:
+        case CPU_DOWN_FAILED:
+                octeon_wdt_setup_interrupt(cpu);
+                break;
+        default:
+                break;
+        }
+        return NOTIFY_OK;
+}
+
+static void octeon_wdt_ping(void)
+{
+        int cpu;
+        int coreid;
+
+        for_each_online_cpu(cpu) {
+                coreid = cpu2core(cpu);
+                cvmx_write_csr(CVMX_CIU_PP_POKEX(coreid), 1);
+                per_cpu_countdown[cpu] = countdown_reset;
+                if ((countdown_reset || !do_coundown) &&
+                    !cpumask_test_cpu(cpu, &irq_enabled_cpus)) {
+                        /* We have to enable the irq */
+                        int irq = OCTEON_IRQ_WDOG0 + coreid;
+                        enable_irq(irq);
+                        cpumask_set_cpu(cpu, &irq_enabled_cpus);
+                }
+        }
+}
+
+static void octeon_wdt_calc_parameters(int t)
+{
+        unsigned int periods;
+
+        timeout_sec = max_timeout_sec;
+
+
+        /*
+         * Find the largest interrupt period, that can evenly divide
+         * the requested heartbeat time.
+         */
+        while ((t % timeout_sec) != 0)
+                timeout_sec--;
+
+        periods = t / timeout_sec;
+
+        /*
+         * The last two periods are after the irq is disabled, and
+         * then to the nmi, so we subtract them off.
+         */
+
+        countdown_reset = periods > 2 ? periods - 2 : 0;
+        heartbeat = t;
+        timeout_cnt = ((octeon_get_clock_rate() >> 8) * timeout_sec) >> 8;
+}
+
+static int octeon_wdt_set_heartbeat(int t)
+{
+        int cpu;
+        int coreid;
+        union cvmx_ciu_wdogx ciu_wdog;
+
+        if (t <= 0)
+                return -1;
+
+        octeon_wdt_calc_parameters(t);
+
+        for_each_online_cpu(cpu) {
+                coreid = cpu2core(cpu);
+                cvmx_write_csr(CVMX_CIU_PP_POKEX(coreid), 1);
+                ciu_wdog.u64 = 0;
+                ciu_wdog.s.len = timeout_cnt;
+                ciu_wdog.s.mode = 3;    /* 3 = Interrupt + NMI + Soft-Reset */
+                cvmx_write_csr(CVMX_CIU_WDOGX(coreid), ciu_wdog.u64);
+                cvmx_write_csr(CVMX_CIU_PP_POKEX(coreid), 1);
+        }
+        octeon_wdt_ping(); /* Get the irqs back on. */
+        return 0;
+}
+
+/**
+ *      octeon_wdt_write:
+ *      @file: file handle to the watchdog
+ *      @buf: buffer to write (unused as data does not matter here
+ *      @count: count of bytes
+ *      @ppos: pointer to the position to write. No seeks allowed
+ *
+ *      A write to a watchdog device is defined as a keepalive signal. Any
+ *      write of data will do, as we we don't define content meaning.
+ */
+
+static ssize_t octeon_wdt_write(struct file *file, const char __user *buf,
+                                size_t count, loff_t *ppos)
+{
+        if (count) {
+                if (!nowayout) {
+                        size_t i;
+
+                        /* In case it was set long ago */
+                        expect_close = 0;
+
+                        for (i = 0; i != count; i++) {
+                                char c;
+                                if (get_user(c, buf + i))
+                                        return -EFAULT;
+                                if (c == 'V')
+                                        expect_close = 1;
+                        }
+                }
+                octeon_wdt_ping();
+        }
+        return count;
+}
+
+/**
+ *      octeon_wdt_ioctl:
+ *      @file: file handle to the device
+ *      @cmd: watchdog command
+ *      @arg: argument pointer
+ *
+ *      The watchdog API defines a common set of functions for all
+ *      watchdogs according to their available features. We only
+ *      actually usefully support querying capabilities and setting
+ *      the timeout.
+ */
+
+static long octeon_wdt_ioctl(struct file *file, unsigned int cmd,
+                             unsigned long arg)
+{
+        void __user *argp = (void __user *)arg;
+        int __user *p = argp;
+        int new_heartbeat;
+
+        static struct watchdog_info ident = {
+                .options =              WDIOF_SETTIMEOUT|
+                                        WDIOF_MAGICCLOSE|
+                                        WDIOF_KEEPALIVEPING,
+                .firmware_version =     1,
+                .identity =             "OCTEON",
+        };
+
+        switch (cmd) {
+        case WDIOC_GETSUPPORT:
+                return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0;
+        case WDIOC_GETSTATUS:
+        case WDIOC_GETBOOTSTATUS:
+                return put_user(0, p);
+        case WDIOC_KEEPALIVE:
+                octeon_wdt_ping();
+                return 0;
+        case WDIOC_SETTIMEOUT:
+                if (get_user(new_heartbeat, p))
+                        return -EFAULT;
+                if (octeon_wdt_set_heartbeat(new_heartbeat))
+                        return -EINVAL;
+                /* Fall through. */
+        case WDIOC_GETTIMEOUT:
+                return put_user(heartbeat, p);
+        default:
+                return -ENOTTY;
+        }
+}
+
+/**
+ *      octeon_wdt_open:
+ *      @inode: inode of device
+ *      @file: file handle to device
+ *
+ *      The watchdog device has been opened. The watchdog device is single
+ *      open and on opening we do a ping to reset the counters.
+ */
+
+static int octeon_wdt_open(struct inode *inode, struct file *file)
+{
+        if (test_and_set_bit(0, &octeon_wdt_is_open))
+                return -EBUSY;
+        /*
+         *      Activate
+         */
+        octeon_wdt_ping();
+        do_coundown = 1;
+        return nonseekable_open(inode, file);
+}
+
+/**
+ *      octeon_wdt_release:
+ *      @inode: inode to board
+ *      @file: file handle to board
+ *
+ *      The watchdog has a configurable API. There is a religious dispute
+ *      between people who want their watchdog to be able to shut down and
+ *      those who want to be sure if the watchdog manager dies the machine
+ *      reboots. In the former case we disable the counters, in the latter
+ *      case you have to open it again very soon.
+ */
+
+static int octeon_wdt_release(struct inode *inode, struct file *file)
+{
+        if (expect_close) {
+                do_coundown = 0;
+                octeon_wdt_ping();
+        } else {
+                pr_crit("octeon_wdt: WDT device closed unexpectedly.  WDT will not stop!\n");
+        }
+        clear_bit(0, &octeon_wdt_is_open);
+        expect_close = 0;
+        return 0;
+}
+
+static const struct file_operations octeon_wdt_fops = {
+        .owner          = THIS_MODULE,
+        .llseek         = no_llseek,
+        .write          = octeon_wdt_write,
+        .unlocked_ioctl = octeon_wdt_ioctl,
+        .open           = octeon_wdt_open,
+        .release        = octeon_wdt_release,
+};
+
+static struct miscdevice octeon_wdt_miscdev = {
+        .minor  = WATCHDOG_MINOR,
+        .name   = "watchdog",
+        .fops   = &octeon_wdt_fops,
+};
+
+static struct notifier_block octeon_wdt_cpu_notifier = {
+        .notifier_call = octeon_wdt_cpu_callback,
+};
+
+
+/**
+ * Module/ driver initialization.
+ *
+ * Returns Zero on success
+ */
+static int __init octeon_wdt_init(void)
+{
+        int i;
+        int ret;
+        int cpu;
+        u64 *ptr;
+
+        /*
+         * Watchdog time expiration length = The 16 bits of LEN
+         * represent the most significant bits of a 24 bit decrementer
+         * that decrements every 256 cycles.
+         *
+         * Try for a timeout of 5 sec, if that fails a smaller number
+         * of even seconds,
+         */
+        max_timeout_sec = 6;
+        do {
+                max_timeout_sec--;
+                timeout_cnt = ((octeon_get_clock_rate() >> 8) * max_timeout_sec) >> 8;
+        } while (timeout_cnt > 65535);
+
+        BUG_ON(timeout_cnt == 0);
+
+        octeon_wdt_calc_parameters(heartbeat);
+
+        pr_info("octeon_wdt: Initial granularity %d Sec.\n", timeout_sec);
+
+        ret = misc_register(&octeon_wdt_miscdev);
+        if (ret) {
+                pr_err("octeon_wdt: cannot register miscdev on minor=%d (err=%d)\n",
+                        WATCHDOG_MINOR, ret);
+                goto out;
+        }
+
+        /* Build the NMI handler ... */
+        octeon_wdt_build_stage1();
+
+        /* ... and install it. */
+        ptr = (u64 *) nmi_stage1_insns;
+        for (i = 0; i < 16; i++) {
+                cvmx_write_csr(CVMX_MIO_BOOT_LOC_ADR, i * 8);
+                cvmx_write_csr(CVMX_MIO_BOOT_LOC_DAT, ptr[i]);
+        }
+        cvmx_write_csr(CVMX_MIO_BOOT_LOC_CFGX(0), 0x81fc0000);
+
+        cpumask_clear(&irq_enabled_cpus);
+
+        for_each_online_cpu(cpu)
+                octeon_wdt_setup_interrupt(cpu);
+
+        register_hotcpu_notifier(&octeon_wdt_cpu_notifier);
+out:
+        return ret;
+}
+
+/**
+ * Module / driver shutdown
+ */
+static void __exit octeon_wdt_cleanup(void)
+{
+        int cpu;
+
+        misc_deregister(&octeon_wdt_miscdev);
+
+        unregister_hotcpu_notifier(&octeon_wdt_cpu_notifier);
+
+        for_each_online_cpu(cpu) {
+                int core = cpu2core(cpu);
+                /* Disable the watchdog */
+                cvmx_write_csr(CVMX_CIU_WDOGX(core), 0);
+                /* Free the interrupt handler */
+                free_irq(OCTEON_IRQ_WDOG0 + core, octeon_wdt_poke_irq);
+        }
+        /*
+         * Disable the boot-bus memory, the code it points to is soon
+         * to go missing.
+         */
+        cvmx_write_csr(CVMX_MIO_BOOT_LOC_CFGX(0), 0);
+}
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Cavium Networks <support@caviumnetworks.com>");
+MODULE_DESCRIPTION("Cavium Networks Octeon Watchdog driver.");
+module_init(octeon_wdt_init);
+module_exit(octeon_wdt_cleanup);
diff --git a/drivers/watchdog/octeon-wdt-nmi.S b/drivers/watchdog/octeon-wdt-nmi.S
new file mode 100644
index 000000000000..8a900a5e3233
--- /dev/null
+++ b/drivers/watchdog/octeon-wdt-nmi.S
@@ -0,0 +1,64 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2007 Cavium Networks
+ */
+#include <asm/asm.h>
+#include <asm/regdef.h>
+
+#define SAVE_REG(r)     sd $r, -32768+6912-(32-r)*8($0)
+
+        NESTED(octeon_wdt_nmi_stage2, 0, sp)
+        .set    push
+        .set    noreorder
+        .set    noat
+        /* Save all registers to the top CVMSEG. This shouldn't
+         * corrupt any state used by the kernel. Also all registers
+         * should have the value right before the NMI. */
+        SAVE_REG(0)
+        SAVE_REG(1)
+        SAVE_REG(2)
+        SAVE_REG(3)
+        SAVE_REG(4)
+        SAVE_REG(5)
+        SAVE_REG(6)
+        SAVE_REG(7)
+        SAVE_REG(8)
+        SAVE_REG(9)
+        SAVE_REG(10)
+        SAVE_REG(11)
+        SAVE_REG(12)
+        SAVE_REG(13)
+        SAVE_REG(14)
+        SAVE_REG(15)
+        SAVE_REG(16)
+        SAVE_REG(17)
+        SAVE_REG(18)
+        SAVE_REG(19)
+        SAVE_REG(20)
+        SAVE_REG(21)
+        SAVE_REG(22)
+        SAVE_REG(23)
+        SAVE_REG(24)
+        SAVE_REG(25)
+        SAVE_REG(26)
+        SAVE_REG(27)
+        SAVE_REG(28)
+        SAVE_REG(29)
+        SAVE_REG(30)
+        SAVE_REG(31)
+        /* Set the stack to begin right below the registers */
+        li      sp, -32768+6912-32*8
+        /* Load the address of the third stage handler */
+        dla     a0, octeon_wdt_nmi_stage3
+        /* Call the third stage handler */
+        jal     a0
+        /* a0 is the address of the saved registers */
+         move   a0, sp
+        /* Loop forvever if we get here. */
+1:      b       1b
+        nop
+        .set pop
+        END(octeon_wdt_nmi_stage2)
diff --git a/drivers/xen/Kconfig b/drivers/xen/Kconfig
index fad3df2c1276..0a8826936639 100644
--- a/drivers/xen/Kconfig
+++ b/drivers/xen/Kconfig
@@ -62,4 +62,13 @@ config XEN_SYS_HYPERVISOR
          virtual environment, /sys/hypervisor will still be present,
          but will have no xen contents.
 
+config XEN_PLATFORM_PCI
+        tristate "xen platform pci device driver"
+        depends on XEN_PVHVM
+        default m
+        help
+          Driver for the Xen PCI Platform device: it is responsible for
+          initializing xenbus and grant_table when running in a Xen HVM
+          domain. As a consequence this driver is required to run any Xen PV
+          frontend on Xen HVM.
 endmenu
diff --git a/drivers/xen/Makefile b/drivers/xen/Makefile
index 7c284342f30f..e392fb776af3 100644
--- a/drivers/xen/Makefile
+++ b/drivers/xen/Makefile
@@ -9,4 +9,5 @@ obj-$(CONFIG_XEN_XENCOMM)	+= xencomm.o
 obj-$(CONFIG_XEN_BALLOON)       += balloon.o
 obj-$(CONFIG_XEN_DEV_EVTCHN)    += evtchn.o
 obj-$(CONFIG_XENFS)             += xenfs/
-obj-$(CONFIG_XEN_SYS_HYPERVISOR)        += sys-hypervisor.o
\ No newline at end of file
+obj-$(CONFIG_XEN_SYS_HYPERVISOR)        += sys-hypervisor.o
+obj-$(CONFIG_XEN_PLATFORM_PCI)  += platform-pci.o
diff --git a/drivers/xen/events.c b/drivers/xen/events.c
index db8f506817f0..5e1f34892dcc 100644
--- a/drivers/xen/events.c
+++ b/drivers/xen/events.c
@@ -29,6 +29,7 @@
 #include <linux/bootmem.h>
 #include <linux/slab.h>
 
+#include <asm/desc.h>
 #include <asm/ptrace.h>
 #include <asm/irq.h>
 #include <asm/idle.h>
@@ -36,10 +37,14 @@
 #include <asm/xen/hypercall.h>
 #include <asm/xen/hypervisor.h>
 
+#include <xen/xen.h>
+#include <xen/hvm.h>
 #include <xen/xen-ops.h>
 #include <xen/events.h>
 #include <xen/interface/xen.h>
 #include <xen/interface/event_channel.h>
+#include <xen/interface/hvm/hvm_op.h>
+#include <xen/interface/hvm/params.h>
 
 /*
  * This lock protects updates to the following mapping and reference-count
@@ -335,9 +340,18 @@ static int find_unbound_irq(void)
         int irq;
         struct irq_desc *desc;
 
-        for (irq = 0; irq < nr_irqs; irq++)
+        for (irq = 0; irq < nr_irqs; irq++) {
+                desc = irq_to_desc(irq);
+                /* only 0->15 have init'd desc; handle irq > 16 */
+                if (desc == NULL)
+                        break;
+                if (desc->chip == &no_irq_chip)
+                        break;
+                if (desc->chip != &xen_dynamic_chip)
+                        continue;
                 if (irq_info[irq].type == IRQT_UNBOUND)
                         break;
+        }
 
         if (irq == nr_irqs)
                 panic("No available IRQ to bind to: increase nr_irqs!\n");
@@ -346,7 +360,7 @@ static int find_unbound_irq(void)
         if (WARN_ON(desc == NULL))
                 return -1;
 
-        dynamic_irq_init(irq);
+        dynamic_irq_init_keep_chip_data(irq);
 
         return irq;
 }
@@ -617,17 +631,13 @@ static DEFINE_PER_CPU(unsigned, xed_nesting_count);
  * a bitset of words which contain pending event bits.  The second
  * level is a bitset of pending events themselves.
  */
-void xen_evtchn_do_upcall(struct pt_regs *regs)
+static void __xen_evtchn_do_upcall(void)
 {
         int cpu = get_cpu();
-        struct pt_regs *old_regs = set_irq_regs(regs);
         struct shared_info *s = HYPERVISOR_shared_info;
         struct vcpu_info *vcpu_info = __get_cpu_var(xen_vcpu);
         unsigned count;
 
-        exit_idle();
-        irq_enter();
-
         do {
                 unsigned long pending_words;
 
@@ -664,14 +674,31 @@ void xen_evtchn_do_upcall(struct pt_regs *regs)
 
                 count = __get_cpu_var(xed_nesting_count);
                 __get_cpu_var(xed_nesting_count) = 0;
-        } while(count != 1);
+        } while (count != 1 || vcpu_info->evtchn_upcall_pending);
 
 out:
+
+        put_cpu();
+}
+
+void xen_evtchn_do_upcall(struct pt_regs *regs)
+{
+        struct pt_regs *old_regs = set_irq_regs(regs);
+
+        exit_idle();
+        irq_enter();
+
+        __xen_evtchn_do_upcall();
+
         irq_exit();
         set_irq_regs(old_regs);
+}
 
-        put_cpu();
+void xen_hvm_evtchn_do_upcall(void)
+{
+        __xen_evtchn_do_upcall();
 }
+EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall);
 
 /* Rebind a new event channel to an existing irq. */
 void rebind_evtchn_irq(int evtchn, int irq)
@@ -708,7 +735,10 @@ static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu)
         struct evtchn_bind_vcpu bind_vcpu;
         int evtchn = evtchn_from_irq(irq);
 
-        if (!VALID_EVTCHN(evtchn))
+        /* events delivered via platform PCI interrupts are always
+         * routed to vcpu 0 */
+        if (!VALID_EVTCHN(evtchn) ||
+                (xen_hvm_domain() && !xen_have_vector_callback))
                 return -1;
 
         /* Send future instances of this interrupt to other vcpu. */
@@ -933,6 +963,44 @@ static struct irq_chip xen_dynamic_chip __read_mostly = {
         .retrigger      = retrigger_dynirq,
 };
 
+int xen_set_callback_via(uint64_t via)
+{
+        struct xen_hvm_param a;
+        a.domid = DOMID_SELF;
+        a.index = HVM_PARAM_CALLBACK_IRQ;
+        a.value = via;
+        return HYPERVISOR_hvm_op(HVMOP_set_param, &a);
+}
+EXPORT_SYMBOL_GPL(xen_set_callback_via);
+
+#ifdef CONFIG_XEN_PVHVM
+/* Vector callbacks are better than PCI interrupts to receive event
+ * channel notifications because we can receive vector callbacks on any
+ * vcpu and we don't need PCI support or APIC interactions. */
+void xen_callback_vector(void)
+{
+        int rc;
+        uint64_t callback_via;
+        if (xen_have_vector_callback) {
+                callback_via = HVM_CALLBACK_VECTOR(XEN_HVM_EVTCHN_CALLBACK);
+                rc = xen_set_callback_via(callback_via);
+                if (rc) {
+                        printk(KERN_ERR "Request for Xen HVM callback vector"
+                                        " failed.\n");
+                        xen_have_vector_callback = 0;
+                        return;
+                }
+                printk(KERN_INFO "Xen HVM callback vector for event delivery is "
+                                "enabled\n");
+                /* in the restore case the vector has already been allocated */
+                if (!test_bit(XEN_HVM_EVTCHN_CALLBACK, used_vectors))
+                        alloc_intr_gate(XEN_HVM_EVTCHN_CALLBACK, xen_hvm_callback_vector);
+        }
+}
+#else
+void xen_callback_vector(void) {}
+#endif
+
 void __init xen_init_IRQ(void)
 {
         int i;
@@ -947,5 +1015,10 @@ void __init xen_init_IRQ(void)
         for (i = 0; i < NR_EVENT_CHANNELS; i++)
                 mask_evtchn(i);
 
-        irq_ctx_init(smp_processor_id());
+        if (xen_hvm_domain()) {
+                xen_callback_vector();
+                native_init_IRQ();
+        } else {
+                irq_ctx_init(smp_processor_id());
+        }
 }
diff --git a/drivers/xen/grant-table.c b/drivers/xen/grant-table.c
index f66db3b91d61..6c4531816496 100644
--- a/drivers/xen/grant-table.c
+++ b/drivers/xen/grant-table.c
@@ -37,11 +37,13 @@
 #include <linux/slab.h>
 #include <linux/vmalloc.h>
 #include <linux/uaccess.h>
+#include <linux/io.h>
 
 #include <xen/xen.h>
 #include <xen/interface/xen.h>
 #include <xen/page.h>
 #include <xen/grant_table.h>
+#include <xen/interface/memory.h>
 #include <asm/xen/hypercall.h>
 
 #include <asm/pgtable.h>
@@ -59,6 +61,8 @@ static unsigned int boot_max_nr_grant_frames;
 static int gnttab_free_count;
 static grant_ref_t gnttab_free_head;
 static DEFINE_SPINLOCK(gnttab_list_lock);
+unsigned long xen_hvm_resume_frames;
+EXPORT_SYMBOL_GPL(xen_hvm_resume_frames);
 
 static struct grant_entry *shared;
 
@@ -433,7 +437,7 @@ static unsigned int __max_nr_grant_frames(void)
         return query.max_nr_frames;
 }
 
-static inline unsigned int max_nr_grant_frames(void)
+unsigned int gnttab_max_grant_frames(void)
 {
         unsigned int xen_max = __max_nr_grant_frames();
 
@@ -441,6 +445,7 @@ static inline unsigned int max_nr_grant_frames(void)
                 return boot_max_nr_grant_frames;
         return xen_max;
 }
+EXPORT_SYMBOL_GPL(gnttab_max_grant_frames);
 
 static int gnttab_map(unsigned int start_idx, unsigned int end_idx)
 {
@@ -449,6 +454,30 @@ static int gnttab_map(unsigned int start_idx, unsigned int end_idx)
         unsigned int nr_gframes = end_idx + 1;
         int rc;
 
+        if (xen_hvm_domain()) {
+                struct xen_add_to_physmap xatp;
+                unsigned int i = end_idx;
+                rc = 0;
+                /*
+                 * Loop backwards, so that the first hypercall has the largest
+                 * index, ensuring that the table will grow only once.
+                 */
+                do {
+                        xatp.domid = DOMID_SELF;
+                        xatp.idx = i;
+                        xatp.space = XENMAPSPACE_grant_table;
+                        xatp.gpfn = (xen_hvm_resume_frames >> PAGE_SHIFT) + i;
+                        rc = HYPERVISOR_memory_op(XENMEM_add_to_physmap, &xatp);
+                        if (rc != 0) {
+                                printk(KERN_WARNING
+                                                "grant table add_to_physmap failed, err=%d\n", rc);
+                                break;
+                        }
+                } while (i-- > start_idx);
+
+                return rc;
+        }
+
         frames = kmalloc(nr_gframes * sizeof(unsigned long), GFP_ATOMIC);
         if (!frames)
                 return -ENOMEM;
@@ -465,7 +494,7 @@ static int gnttab_map(unsigned int start_idx, unsigned int end_idx)
 
         BUG_ON(rc || setup.status);
 
-        rc = arch_gnttab_map_shared(frames, nr_gframes, max_nr_grant_frames(),
+        rc = arch_gnttab_map_shared(frames, nr_gframes, gnttab_max_grant_frames(),
                                     &shared);
         BUG_ON(rc);
 
@@ -476,9 +505,27 @@ static int gnttab_map(unsigned int start_idx, unsigned int end_idx)
 
 int gnttab_resume(void)
 {
-        if (max_nr_grant_frames() < nr_grant_frames)
+        unsigned int max_nr_gframes;
+
+        max_nr_gframes = gnttab_max_grant_frames();
+        if (max_nr_gframes < nr_grant_frames)
                 return -ENOSYS;
-        return gnttab_map(0, nr_grant_frames - 1);
+
+        if (xen_pv_domain())
+                return gnttab_map(0, nr_grant_frames - 1);
+
+        if (!shared) {
+                shared = ioremap(xen_hvm_resume_frames, PAGE_SIZE * max_nr_gframes);
+                if (shared == NULL) {
+                        printk(KERN_WARNING
+                                        "Failed to ioremap gnttab share frames!");
+                        return -ENOMEM;
+                }
+        }
+
+        gnttab_map(0, nr_grant_frames - 1);
+
+        return 0;
 }
 
 int gnttab_suspend(void)
@@ -495,7 +542,7 @@ static int gnttab_expand(unsigned int req_entries)
         cur = nr_grant_frames;
         extra = ((req_entries + (GREFS_PER_GRANT_FRAME-1)) /
                  GREFS_PER_GRANT_FRAME);
-        if (cur + extra > max_nr_grant_frames())
+        if (cur + extra > gnttab_max_grant_frames())
                 return -ENOSPC;
 
         rc = gnttab_map(cur, cur + extra - 1);
@@ -505,15 +552,12 @@ static int gnttab_expand(unsigned int req_entries)
         return rc;
 }
 
-static int __devinit gnttab_init(void)
+int gnttab_init(void)
 {
         int i;
         unsigned int max_nr_glist_frames, nr_glist_frames;
         unsigned int nr_init_grefs;
 
-        if (!xen_domain())
-                return -ENODEV;
-
         nr_grant_frames = 1;
         boot_max_nr_grant_frames = __max_nr_grant_frames();
 
@@ -556,5 +600,18 @@ static int __devinit gnttab_init(void)
         kfree(gnttab_list);
         return -ENOMEM;
 }
+EXPORT_SYMBOL_GPL(gnttab_init);
+
+static int __devinit __gnttab_init(void)
+{
+        /* Delay grant-table initialization in the PV on HVM case */
+        if (xen_hvm_domain())
+                return 0;
+
+        if (!xen_pv_domain())
+                return -ENODEV;
+
+        return gnttab_init();
+}
 
-core_initcall(gnttab_init);
+core_initcall(__gnttab_init);
diff --git a/drivers/xen/manage.c b/drivers/xen/manage.c
index 07e857b0de13..1799bd890315 100644
--- a/drivers/xen/manage.c
+++ b/drivers/xen/manage.c
@@ -9,6 +9,7 @@
 #include <linux/stop_machine.h>
 #include <linux/freezer.h>
 
+#include <xen/xen.h>
 #include <xen/xenbus.h>
 #include <xen/grant_table.h>
 #include <xen/events.h>
@@ -17,6 +18,7 @@
 
 #include <asm/xen/hypercall.h>
 #include <asm/xen/page.h>
+#include <asm/xen/hypervisor.h>
 
 enum shutdown_state {
         SHUTDOWN_INVALID = -1,
@@ -33,10 +35,30 @@ enum shutdown_state {
 static enum shutdown_state shutting_down = SHUTDOWN_INVALID;
 
 #ifdef CONFIG_PM_SLEEP
-static int xen_suspend(void *data)
+static int xen_hvm_suspend(void *data)
 {
+        struct sched_shutdown r = { .reason = SHUTDOWN_suspend };
         int *cancelled = data;
+
+        BUG_ON(!irqs_disabled());
+
+        *cancelled = HYPERVISOR_sched_op(SCHEDOP_shutdown, &r);
+
+        xen_hvm_post_suspend(*cancelled);
+        gnttab_resume();
+
+        if (!*cancelled) {
+                xen_irq_resume();
+                xen_timer_resume();
+        }
+
+        return 0;
+}
+
+static int xen_suspend(void *data)
+{
         int err;
+        int *cancelled = data;
 
         BUG_ON(!irqs_disabled());
 
@@ -106,7 +128,10 @@ static void do_suspend(void)
                 goto out_resume;
         }
 
-        err = stop_machine(xen_suspend, &cancelled, cpumask_of(0));
+        if (xen_hvm_domain())
+                err = stop_machine(xen_hvm_suspend, &cancelled, cpumask_of(0));
+        else
+                err = stop_machine(xen_suspend, &cancelled, cpumask_of(0));
 
         dpm_resume_noirq(PMSG_RESUME);
 
@@ -255,7 +280,19 @@ static int shutdown_event(struct notifier_block *notifier,
         return NOTIFY_DONE;
 }
 
-static int __init setup_shutdown_event(void)
+static int __init __setup_shutdown_event(void)
+{
+        /* Delay initialization in the PV on HVM case */
+        if (xen_hvm_domain())
+                return 0;
+
+        if (!xen_pv_domain())
+                return -ENODEV;
+
+        return xen_setup_shutdown_event();
+}
+
+int xen_setup_shutdown_event(void)
 {
         static struct notifier_block xenstore_notifier = {
                 .notifier_call = shutdown_event
@@ -264,5 +301,6 @@ static int __init setup_shutdown_event(void)
 
         return 0;
 }
+EXPORT_SYMBOL_GPL(xen_setup_shutdown_event);
 
-subsys_initcall(setup_shutdown_event);
+subsys_initcall(__setup_shutdown_event);
diff --git a/drivers/xen/platform-pci.c b/drivers/xen/platform-pci.c
new file mode 100644
index 000000000000..c01b5ddce529
--- /dev/null
+++ b/drivers/xen/platform-pci.c
@@ -0,0 +1,207 @@
+/******************************************************************************
+ * platform-pci.c
+ *
+ * Xen platform PCI device driver
+ * Copyright (c) 2005, Intel Corporation.
+ * Copyright (c) 2007, XenSource Inc.
+ * Copyright (c) 2010, Citrix
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
+ * Place - Suite 330, Boston, MA 02111-1307 USA.
+ *
+ */
+
+
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+
+#include <xen/platform_pci.h>
+#include <xen/grant_table.h>
+#include <xen/xenbus.h>
+#include <xen/events.h>
+#include <xen/hvm.h>
+#include <xen/xen-ops.h>
+
+#define DRV_NAME    "xen-platform-pci"
+
+MODULE_AUTHOR("ssmith@xensource.com and stefano.stabellini@eu.citrix.com");
+MODULE_DESCRIPTION("Xen platform PCI device");
+MODULE_LICENSE("GPL");
+
+static unsigned long platform_mmio;
+static unsigned long platform_mmio_alloc;
+static unsigned long platform_mmiolen;
+static uint64_t callback_via;
+
+unsigned long alloc_xen_mmio(unsigned long len)
+{
+        unsigned long addr;
+
+        addr = platform_mmio + platform_mmio_alloc;
+        platform_mmio_alloc += len;
+        BUG_ON(platform_mmio_alloc > platform_mmiolen);
+
+        return addr;
+}
+
+static uint64_t get_callback_via(struct pci_dev *pdev)
+{
+        u8 pin;
+        int irq;
+
+        irq = pdev->irq;
+        if (irq < 16)
+                return irq; /* ISA IRQ */
+
+        pin = pdev->pin;
+
+        /* We don't know the GSI. Specify the PCI INTx line instead. */
+        return ((uint64_t)0x01 << 56) | /* PCI INTx identifier */
+                ((uint64_t)pci_domain_nr(pdev->bus) << 32) |
+                ((uint64_t)pdev->bus->number << 16) |
+                ((uint64_t)(pdev->devfn & 0xff) << 8) |
+                ((uint64_t)(pin - 1) & 3);
+}
+
+static irqreturn_t do_hvm_evtchn_intr(int irq, void *dev_id)
+{
+        xen_hvm_evtchn_do_upcall();
+        return IRQ_HANDLED;
+}
+
+static int xen_allocate_irq(struct pci_dev *pdev)
+{
+        return request_irq(pdev->irq, do_hvm_evtchn_intr,
+                        IRQF_DISABLED | IRQF_NOBALANCING | IRQF_TRIGGER_RISING,
+                        "xen-platform-pci", pdev);
+}
+
+static int platform_pci_resume(struct pci_dev *pdev)
+{
+        int err;
+        if (xen_have_vector_callback)
+                return 0;
+        err = xen_set_callback_via(callback_via);
+        if (err) {
+                dev_err(&pdev->dev, "platform_pci_resume failure!\n");
+                return err;
+        }
+        return 0;
+}
+
+static int __devinit platform_pci_init(struct pci_dev *pdev,
+                                       const struct pci_device_id *ent)
+{
+        int i, ret;
+        long ioaddr, iolen;
+        long mmio_addr, mmio_len;
+        unsigned int max_nr_gframes;
+
+        i = pci_enable_device(pdev);
+        if (i)
+                return i;
+
+        ioaddr = pci_resource_start(pdev, 0);
+        iolen = pci_resource_len(pdev, 0);
+
+        mmio_addr = pci_resource_start(pdev, 1);
+        mmio_len = pci_resource_len(pdev, 1);
+
+        if (mmio_addr == 0 || ioaddr == 0) {
+                dev_err(&pdev->dev, "no resources found\n");
+                ret = -ENOENT;
+                goto pci_out;
+        }
+
+        if (request_mem_region(mmio_addr, mmio_len, DRV_NAME) == NULL) {
+                dev_err(&pdev->dev, "MEM I/O resource 0x%lx @ 0x%lx busy\n",
+                       mmio_addr, mmio_len);
+                ret = -EBUSY;
+                goto pci_out;
+        }
+
+        if (request_region(ioaddr, iolen, DRV_NAME) == NULL) {
+                dev_err(&pdev->dev, "I/O resource 0x%lx @ 0x%lx busy\n",
+                       iolen, ioaddr);
+                ret = -EBUSY;
+                goto mem_out;
+        }
+
+        platform_mmio = mmio_addr;
+        platform_mmiolen = mmio_len;
+
+        if (!xen_have_vector_callback) {
+                ret = xen_allocate_irq(pdev);
+                if (ret) {
+                        dev_warn(&pdev->dev, "request_irq failed err=%d\n", ret);
+                        goto out;
+                }
+                callback_via = get_callback_via(pdev);
+                ret = xen_set_callback_via(callback_via);
+                if (ret) {
+                        dev_warn(&pdev->dev, "Unable to set the evtchn callback "
+                                         "err=%d\n", ret);
+                        goto out;
+                }
+        }
+
+        max_nr_gframes = gnttab_max_grant_frames();
+        xen_hvm_resume_frames = alloc_xen_mmio(PAGE_SIZE * max_nr_gframes);
+        ret = gnttab_init();
+        if (ret)
+                goto out;
+        xenbus_probe(NULL);
+        ret = xen_setup_shutdown_event();
+        if (ret)
+                goto out;
+        return 0;
+
+out:
+        release_region(ioaddr, iolen);
+mem_out:
+        release_mem_region(mmio_addr, mmio_len);
+pci_out:
+        pci_disable_device(pdev);
+        return ret;
+}
+
+static struct pci_device_id platform_pci_tbl[] __devinitdata = {
+        {PCI_VENDOR_ID_XEN, PCI_DEVICE_ID_XEN_PLATFORM,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
+        {0,}
+};
+
+MODULE_DEVICE_TABLE(pci, platform_pci_tbl);
+
+static struct pci_driver platform_driver = {
+        .name =           DRV_NAME,
+        .probe =          platform_pci_init,
+        .id_table =       platform_pci_tbl,
+#ifdef CONFIG_PM
+        .resume_early =   platform_pci_resume,
+#endif
+};
+
+static int __init platform_pci_module_init(void)
+{
+        /* no unplug has been done, IGNORE hasn't been specified: just
+         * return now */
+        if (!xen_platform_pci_unplug)
+                return -ENODEV;
+
+        return pci_register_driver(&platform_driver);
+}
+
+module_init(platform_pci_module_init);
diff --git a/drivers/xen/xenbus/xenbus_probe.c b/drivers/xen/xenbus/xenbus_probe.c
index 3479332113e9..29bac5118877 100644
--- a/drivers/xen/xenbus/xenbus_probe.c
+++ b/drivers/xen/xenbus/xenbus_probe.c
@@ -56,6 +56,9 @@
 #include <xen/events.h>
 #include <xen/page.h>
 
+#include <xen/platform_pci.h>
+#include <xen/hvm.h>
+
 #include "xenbus_comms.h"
 #include "xenbus_probe.h"
 
@@ -752,10 +755,7 @@ int register_xenstore_notifier(struct notifier_block *nb)
 {
         int ret = 0;
 
-        if (xenstored_ready > 0)
-                ret = nb->notifier_call(nb, 0, NULL);
-        else
-                blocking_notifier_chain_register(&xenstore_chain, nb);
+        blocking_notifier_chain_register(&xenstore_chain, nb);
 
         return ret;
 }
@@ -779,8 +779,23 @@ void xenbus_probe(struct work_struct *unused)
         /* Notify others that xenstore is up */
         blocking_notifier_call_chain(&xenstore_chain, 0, NULL);
 }
+EXPORT_SYMBOL_GPL(xenbus_probe);
+
+static int __init xenbus_probe_initcall(void)
+{
+        if (!xen_domain())
+                return -ENODEV;
+
+        if (xen_initial_domain() || xen_hvm_domain())
+                return 0;
+
+        xenbus_probe(NULL);
+        return 0;
+}
+
+device_initcall(xenbus_probe_initcall);
 
-static int __init xenbus_probe_init(void)
+static int __init xenbus_init(void)
 {
         int err = 0;
 
@@ -805,11 +820,24 @@ static int __init xenbus_probe_init(void)
         if (xen_initial_domain()) {
                 /* dom0 not yet supported */
         } else {
+                if (xen_hvm_domain()) {
+                        uint64_t v = 0;
+                        err = hvm_get_parameter(HVM_PARAM_STORE_EVTCHN, &v);
+                        if (err)
+                                goto out_error;
+                        xen_store_evtchn = (int)v;
+                        err = hvm_get_parameter(HVM_PARAM_STORE_PFN, &v);
+                        if (err)
+                                goto out_error;
+                        xen_store_mfn = (unsigned long)v;
+                        xen_store_interface = ioremap(xen_store_mfn << PAGE_SHIFT, PAGE_SIZE);
+                } else {
+                        xen_store_evtchn = xen_start_info->store_evtchn;
+                        xen_store_mfn = xen_start_info->store_mfn;
+                        xen_store_interface = mfn_to_virt(xen_store_mfn);
+                }
                 xenstored_ready = 1;
-                xen_store_evtchn = xen_start_info->store_evtchn;
-                xen_store_mfn = xen_start_info->store_mfn;
         }
-        xen_store_interface = mfn_to_virt(xen_store_mfn);
 
         /* Initialize the interface to xenstore. */
         err = xs_init();
@@ -819,9 +847,6 @@ static int __init xenbus_probe_init(void)
                 goto out_unreg_back;
         }
 
-        if (!xen_initial_domain())
-                xenbus_probe(NULL);
-
 #ifdef CONFIG_XEN_COMPAT_XENFS
         /*
          * Create xenfs mountpoint in /proc for compatibility with
@@ -842,7 +867,7 @@ static int __init xenbus_probe_init(void)
         return err;
 }
 
-postcore_initcall(xenbus_probe_init);
+postcore_initcall(xenbus_init);
 
 MODULE_LICENSE("GPL");
 
@@ -950,6 +975,9 @@ static void wait_for_devices(struct xenbus_driver *xendrv)
 #ifndef MODULE
 static int __init boot_wait_for_devices(void)
 {
+        if (xen_hvm_domain() && !xen_platform_pci_unplug)
+                return -ENODEV;
+
         ready_to_wait_for_devices = 1;
         wait_for_devices(NULL);
         return 0;
diff --git a/drivers/xen/xenbus/xenbus_xs.c b/drivers/xen/xenbus/xenbus_xs.c
index 7b547f53f65e..5534690075af 100644
--- a/drivers/xen/xenbus/xenbus_xs.c
+++ b/drivers/xen/xenbus/xenbus_xs.c
@@ -76,6 +76,14 @@ struct xs_handle {
         /*
          * Mutex ordering: transaction_mutex -> watch_mutex -> request_mutex.
          * response_mutex is never taken simultaneously with the other three.
+         *
+         * transaction_mutex must be held before incrementing
+         * transaction_count. The mutex is held when a suspend is in
+         * progress to prevent new transactions starting.
+         *
+         * When decrementing transaction_count to zero the wait queue
+         * should be woken up, the suspend code waits for count to
+         * reach zero.
          */
 
         /* One request at a time. */
@@ -85,7 +93,9 @@ struct xs_handle {
         struct mutex response_mutex;
 
         /* Protect transactions against save/restore. */
-        struct rw_semaphore transaction_mutex;
+        struct mutex transaction_mutex;
+        atomic_t transaction_count;
+        wait_queue_head_t transaction_wq;
 
         /* Protect watch (de)register against save/restore. */
         struct rw_semaphore watch_mutex;
@@ -157,6 +167,31 @@ static void *read_reply(enum xsd_sockmsg_type *type, unsigned int *len)
         return body;
 }
 
+static void transaction_start(void)
+{
+        mutex_lock(&xs_state.transaction_mutex);
+        atomic_inc(&xs_state.transaction_count);
+        mutex_unlock(&xs_state.transaction_mutex);
+}
+
+static void transaction_end(void)
+{
+        if (atomic_dec_and_test(&xs_state.transaction_count))
+                wake_up(&xs_state.transaction_wq);
+}
+
+static void transaction_suspend(void)
+{
+        mutex_lock(&xs_state.transaction_mutex);
+        wait_event(xs_state.transaction_wq,
+                   atomic_read(&xs_state.transaction_count) == 0);
+}
+
+static void transaction_resume(void)
+{
+        mutex_unlock(&xs_state.transaction_mutex);
+}
+
 void *xenbus_dev_request_and_reply(struct xsd_sockmsg *msg)
 {
         void *ret;
@@ -164,7 +199,7 @@ void *xenbus_dev_request_and_reply(struct xsd_sockmsg *msg)
         int err;
 
         if (req_msg.type == XS_TRANSACTION_START)
-                down_read(&xs_state.transaction_mutex);
+                transaction_start();
 
         mutex_lock(&xs_state.request_mutex);
 
@@ -180,7 +215,7 @@ void *xenbus_dev_request_and_reply(struct xsd_sockmsg *msg)
         if ((msg->type == XS_TRANSACTION_END) ||
             ((req_msg.type == XS_TRANSACTION_START) &&
              (msg->type == XS_ERROR)))
-                up_read(&xs_state.transaction_mutex);
+                transaction_end();
 
         return ret;
 }
@@ -432,11 +467,11 @@ int xenbus_transaction_start(struct xenbus_transaction *t)
 {
         char *id_str;
 
-        down_read(&xs_state.transaction_mutex);
+        transaction_start();
 
         id_str = xs_single(XBT_NIL, XS_TRANSACTION_START, "", NULL);
         if (IS_ERR(id_str)) {
-                up_read(&xs_state.transaction_mutex);
+                transaction_end();
                 return PTR_ERR(id_str);
         }
 
@@ -461,7 +496,7 @@ int xenbus_transaction_end(struct xenbus_transaction t, int abort)
 
         err = xs_error(xs_single(t, XS_TRANSACTION_END, abortstr, NULL));
 
-        up_read(&xs_state.transaction_mutex);
+        transaction_end();
 
         return err;
 }
@@ -662,7 +697,7 @@ EXPORT_SYMBOL_GPL(unregister_xenbus_watch);
 
 void xs_suspend(void)
 {
-        down_write(&xs_state.transaction_mutex);
+        transaction_suspend();
         down_write(&xs_state.watch_mutex);
         mutex_lock(&xs_state.request_mutex);
         mutex_lock(&xs_state.response_mutex);
@@ -677,7 +712,7 @@ void xs_resume(void)
 
         mutex_unlock(&xs_state.response_mutex);
         mutex_unlock(&xs_state.request_mutex);
-        up_write(&xs_state.transaction_mutex);
+        transaction_resume();
 
         /* No need for watches_lock: the watch_mutex is sufficient. */
         list_for_each_entry(watch, &watches, list) {
@@ -693,7 +728,7 @@ void xs_suspend_cancel(void)
         mutex_unlock(&xs_state.response_mutex);
         mutex_unlock(&xs_state.request_mutex);
         up_write(&xs_state.watch_mutex);
-        up_write(&xs_state.transaction_mutex);
+        mutex_unlock(&xs_state.transaction_mutex);
 }
 
 static int xenwatch_thread(void *unused)
@@ -843,8 +878,10 @@ int xs_init(void)
 
         mutex_init(&xs_state.request_mutex);
         mutex_init(&xs_state.response_mutex);
-        init_rwsem(&xs_state.transaction_mutex);
+        mutex_init(&xs_state.transaction_mutex);
         init_rwsem(&xs_state.watch_mutex);
+        atomic_set(&xs_state.transaction_count, 0);
+        init_waitqueue_head(&xs_state.transaction_wq);
 
         /* Initialize the shared memory rings to talk to xenstored */
         err = xb_init_comms();
diff --git a/drivers/xen/xenfs/super.c b/drivers/xen/xenfs/super.c
index 8924d93136f1..78bfab0700ba 100644
--- a/drivers/xen/xenfs/super.c
+++ b/drivers/xen/xenfs/super.c
@@ -65,7 +65,7 @@ static struct file_system_type xenfs_type = {
 
 static int __init xenfs_init(void)
 {
-        if (xen_pv_domain())
+        if (xen_domain())
                 return register_filesystem(&xenfs_type);
 
         printk(KERN_INFO "XENFS: not registering filesystem on non-xen platform\n");
@@ -74,7 +74,7 @@ static int __init xenfs_init(void)
 
 static void __exit xenfs_exit(void)
 {
-        if (xen_pv_domain())
+        if (xen_domain())
                 unregister_filesystem(&xenfs_type);
 }
 
diff --git a/drivers/xen/xenfs/xenbus.c b/drivers/xen/xenfs/xenbus.c
index f28ece397361..3b39c3752e21 100644
--- a/drivers/xen/xenfs/xenbus.c
+++ b/drivers/xen/xenfs/xenbus.c
@@ -124,6 +124,9 @@ static ssize_t xenbus_file_read(struct file *filp,
         mutex_lock(&u->reply_mutex);
         while (list_empty(&u->read_buffers)) {
                 mutex_unlock(&u->reply_mutex);
+                if (filp->f_flags & O_NONBLOCK)
+                        return -EAGAIN;
+
                 ret = wait_event_interruptible(u->read_waitq,
                                                !list_empty(&u->read_buffers));
                 if (ret)
diff --git a/fs/aio.c b/fs/aio.c
index 1ccf25cef1f0..3006b5bc33d6 100644
--- a/fs/aio.c
+++ b/fs/aio.c
@@ -1277,7 +1277,7 @@ out:
 /* sys_io_destroy:
  *      Destroy the aio_context specified.  May cancel any outstanding 
  *      AIOs and block on completion.  Will fail with -ENOSYS if not
- *      implemented.  May fail with -EFAULT if the context pointed to
+ *      implemented.  May fail with -EINVAL if the context pointed to
  *      is invalid.
  */
 SYSCALL_DEFINE1(io_destroy, aio_context_t, ctx)
@@ -1795,15 +1795,16 @@ SYSCALL_DEFINE3(io_cancel, aio_context_t, ctx_id, struct iocb __user *, iocb,
 
 /* io_getevents:
  *      Attempts to read at least min_nr events and up to nr events from
- *      the completion queue for the aio_context specified by ctx_id.  May
- *      fail with -EINVAL if ctx_id is invalid, if min_nr is out of range,
- *      if nr is out of range, if when is out of range.  May fail with
- *      -EFAULT if any of the memory specified to is invalid.  May return
- *      0 or < min_nr if no events are available and the timeout specified
- *      by when has elapsed, where when == NULL specifies an infinite
- *      timeout.  Note that the timeout pointed to by when is relative and
- *      will be updated if not NULL and the operation blocks.  Will fail
- *      with -ENOSYS if not implemented.
+ *      the completion queue for the aio_context specified by ctx_id. If
+ *      it succeeds, the number of read events is returned. May fail with
+ *      -EINVAL if ctx_id is invalid, if min_nr is out of range, if nr is
+ *      out of range, if timeout is out of range.  May fail with -EFAULT
+ *      if any of the memory specified is invalid.  May return 0 or
+ *      < min_nr if the timeout specified by timeout has elapsed
+ *      before sufficient events are available, where timeout == NULL
+ *      specifies an infinite timeout. Note that the timeout pointed to by
+ *      timeout is relative and will be updated if not NULL and the
+ *      operation blocks. Will fail with -ENOSYS if not implemented.
  */
 SYSCALL_DEFINE5(io_getevents, aio_context_t, ctx_id,
                 long, min_nr,
diff --git a/include/asm-generic/vmlinux.lds.h b/include/asm-generic/vmlinux.lds.h
index 030a954ed292..4e7ae6002056 100644
--- a/include/asm-generic/vmlinux.lds.h
+++ b/include/asm-generic/vmlinux.lds.h
@@ -653,6 +653,7 @@
         EXIT_DATA                                                       \
         EXIT_CALL                                                       \
         *(.discard)                                                     \
+        *(.discard.*)                                                   \
         }
 
 /**
diff --git a/drivers/video/fsl-diu-fb.h b/include/linux/fsl-diu-fb.h
index fc295d7ea463..fc295d7ea463 100644
--- a/drivers/video/fsl-diu-fb.h
+++ b/include/linux/fsl-diu-fb.h
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index e69612cace61..40c804d484ca 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -2264,6 +2264,7 @@
 #define PCI_DEVICE_ID_TDI_EHCI          0x0101
 
 #define PCI_VENDOR_ID_FREESCALE         0x1957
+#define PCI_DEVICE_ID_MPC8308           0xc006
 #define PCI_DEVICE_ID_MPC8315E          0x00b4
 #define PCI_DEVICE_ID_MPC8315           0x00b5
 #define PCI_DEVICE_ID_MPC8314E          0x00b6
@@ -2772,3 +2773,6 @@
 #define PCI_DEVICE_ID_RME_DIGI32        0x9896
 #define PCI_DEVICE_ID_RME_DIGI32_PRO    0x9897
 #define PCI_DEVICE_ID_RME_DIGI32_8      0x9898
+
+#define PCI_VENDOR_ID_XEN               0x5853
+#define PCI_DEVICE_ID_XEN_PLATFORM      0x0001
diff --git a/include/linux/power/jz4740-battery.h b/include/linux/power/jz4740-battery.h
new file mode 100644
index 000000000000..19c9610c720a
--- /dev/null
+++ b/include/linux/power/jz4740-battery.h
@@ -0,0 +1,24 @@
+/*
+ *  Copyright (C) 2009, Jiejing Zhang <kzjeef@gmail.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __JZ4740_BATTERY_H
+#define __JZ4740_BATTERY_H
+
+struct jz_battery_platform_data {
+        struct power_supply_info info;
+        int gpio_charge;        /* GPIO port of Charger state */
+        int gpio_charge_active_low;
+};
+
+#endif
diff --git a/include/xen/events.h b/include/xen/events.h
index e68d59a90ca8..a15d93262e30 100644
--- a/include/xen/events.h
+++ b/include/xen/events.h
@@ -56,4 +56,11 @@ void xen_poll_irq(int irq);
 /* Determine the IRQ which is bound to an event channel */
 unsigned irq_from_evtchn(unsigned int evtchn);
 
+/* Xen HVM evtchn vector callback */
+extern void xen_hvm_callback_vector(void);
+extern int xen_have_vector_callback;
+int xen_set_callback_via(uint64_t via);
+void xen_evtchn_do_upcall(struct pt_regs *regs);
+void xen_hvm_evtchn_do_upcall(void);
+
 #endif  /* _XEN_EVENTS_H */
diff --git a/include/xen/grant_table.h b/include/xen/grant_table.h
index a40f1cd91be1..9a731706a016 100644
--- a/include/xen/grant_table.h
+++ b/include/xen/grant_table.h
@@ -51,6 +51,7 @@ struct gnttab_free_callback {
         u16 count;
 };
 
+int gnttab_init(void);
 int gnttab_suspend(void);
 int gnttab_resume(void);
 
@@ -112,6 +113,9 @@ int arch_gnttab_map_shared(unsigned long *frames, unsigned long nr_gframes,
 void arch_gnttab_unmap_shared(struct grant_entry *shared,
                               unsigned long nr_gframes);
 
+extern unsigned long xen_hvm_resume_frames;
+unsigned int gnttab_max_grant_frames(void);
+
 #define gnttab_map_vaddr(map) ((void *)(map.host_virt_addr))
 
 #endif /* __ASM_GNTTAB_H__ */
diff --git a/include/xen/hvm.h b/include/xen/hvm.h
new file mode 100644
index 000000000000..b193fa2f9fdd
--- /dev/null
+++ b/include/xen/hvm.h
@@ -0,0 +1,30 @@
+/* Simple wrappers around HVM functions */
+#ifndef XEN_HVM_H__
+#define XEN_HVM_H__
+
+#include <xen/interface/hvm/params.h>
+#include <asm/xen/hypercall.h>
+
+static inline int hvm_get_parameter(int idx, uint64_t *value)
+{
+        struct xen_hvm_param xhv;
+        int r;
+
+        xhv.domid = DOMID_SELF;
+        xhv.index = idx;
+        r = HYPERVISOR_hvm_op(HVMOP_get_param, &xhv);
+        if (r < 0) {
+                printk(KERN_ERR "Cannot get hvm parameter %d: %d!\n",
+                        idx, r);
+                return r;
+        }
+        *value = xhv.value;
+        return r;
+}
+
+#define HVM_CALLBACK_VIA_TYPE_VECTOR 0x2
+#define HVM_CALLBACK_VIA_TYPE_SHIFT 56
+#define HVM_CALLBACK_VECTOR(x) (((uint64_t)HVM_CALLBACK_VIA_TYPE_VECTOR)<<\
+                HVM_CALLBACK_VIA_TYPE_SHIFT | (x))
+
+#endif /* XEN_HVM_H__ */
diff --git a/include/xen/interface/features.h b/include/xen/interface/features.h
index f51b6413b054..70d2563ab166 100644
--- a/include/xen/interface/features.h
+++ b/include/xen/interface/features.h
@@ -41,6 +41,12 @@
 /* x86: Does this Xen host support the MMU_PT_UPDATE_PRESERVE_AD hypercall? */
 #define XENFEAT_mmu_pt_update_preserve_ad  5
 
+/* x86: Does this Xen host support the HVM callback vector type? */
+#define XENFEAT_hvm_callback_vector        8
+
+/* x86: pvclock algorithm is safe to use on HVM */
+#define XENFEAT_hvm_safe_pvclock           9
+
 #define XENFEAT_NR_SUBMAPS 1
 
 #endif /* __XEN_PUBLIC_FEATURES_H__ */
diff --git a/include/xen/interface/grant_table.h b/include/xen/interface/grant_table.h
index 39da93c21de0..39e571796e32 100644
--- a/include/xen/interface/grant_table.h
+++ b/include/xen/interface/grant_table.h
@@ -28,6 +28,7 @@
 #ifndef __XEN_PUBLIC_GRANT_TABLE_H__
 #define __XEN_PUBLIC_GRANT_TABLE_H__
 
+#include <xen/interface/xen.h>
 
 /***********************************
  * GRANT TABLE REPRESENTATION
diff --git a/include/xen/interface/hvm/hvm_op.h b/include/xen/interface/hvm/hvm_op.h
new file mode 100644
index 000000000000..a4827f46ee97
--- /dev/null
+++ b/include/xen/interface/hvm/hvm_op.h
@@ -0,0 +1,46 @@
+/*
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __XEN_PUBLIC_HVM_HVM_OP_H__
+#define __XEN_PUBLIC_HVM_HVM_OP_H__
+
+/* Get/set subcommands: the second argument of the hypercall is a
+ * pointer to a xen_hvm_param struct. */
+#define HVMOP_set_param           0
+#define HVMOP_get_param           1
+struct xen_hvm_param {
+    domid_t  domid;    /* IN */
+    uint32_t index;    /* IN */
+    uint64_t value;    /* IN/OUT */
+};
+DEFINE_GUEST_HANDLE_STRUCT(xen_hvm_param);
+
+/* Hint from PV drivers for pagetable destruction. */
+#define HVMOP_pagetable_dying       9
+struct xen_hvm_pagetable_dying {
+    /* Domain with a pagetable about to be destroyed. */
+    domid_t  domid;
+    /* guest physical address of the toplevel pagetable dying */
+    aligned_u64 gpa;
+};
+typedef struct xen_hvm_pagetable_dying xen_hvm_pagetable_dying_t;
+DEFINE_GUEST_HANDLE_STRUCT(xen_hvm_pagetable_dying_t);
+ 
+#endif /* __XEN_PUBLIC_HVM_HVM_OP_H__ */
diff --git a/include/xen/interface/hvm/params.h b/include/xen/interface/hvm/params.h
new file mode 100644
index 000000000000..1888d8c157e6
--- /dev/null
+++ b/include/xen/interface/hvm/params.h
@@ -0,0 +1,95 @@
+/*
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
+ * deal in the Software without restriction, including without limitation the
+ * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __XEN_PUBLIC_HVM_PARAMS_H__
+#define __XEN_PUBLIC_HVM_PARAMS_H__
+
+#include "hvm_op.h"
+
+/*
+ * Parameter space for HVMOP_{set,get}_param.
+ */
+
+/*
+ * How should CPU0 event-channel notifications be delivered?
+ * val[63:56] == 0: val[55:0] is a delivery GSI (Global System Interrupt).
+ * val[63:56] == 1: val[55:0] is a delivery PCI INTx line, as follows:
+ *                  Domain = val[47:32], Bus  = val[31:16],
+ *                  DevFn  = val[15: 8], IntX = val[ 1: 0]
+ * val[63:56] == 2: val[7:0] is a vector number.
+ * If val == 0 then CPU0 event-channel notifications are not delivered.
+ */
+#define HVM_PARAM_CALLBACK_IRQ 0
+
+#define HVM_PARAM_STORE_PFN    1
+#define HVM_PARAM_STORE_EVTCHN 2
+
+#define HVM_PARAM_PAE_ENABLED  4
+
+#define HVM_PARAM_IOREQ_PFN    5
+
+#define HVM_PARAM_BUFIOREQ_PFN 6
+
+/*
+ * Set mode for virtual timers (currently x86 only):
+ *  delay_for_missed_ticks (default):
+ *   Do not advance a vcpu's time beyond the correct delivery time for
+ *   interrupts that have been missed due to preemption. Deliver missed
+ *   interrupts when the vcpu is rescheduled and advance the vcpu's virtual
+ *   time stepwise for each one.
+ *  no_delay_for_missed_ticks:
+ *   As above, missed interrupts are delivered, but guest time always tracks
+ *   wallclock (i.e., real) time while doing so.
+ *  no_missed_ticks_pending:
+ *   No missed interrupts are held pending. Instead, to ensure ticks are
+ *   delivered at some non-zero rate, if we detect missed ticks then the
+ *   internal tick alarm is not disabled if the VCPU is preempted during the
+ *   next tick period.
+ *  one_missed_tick_pending:
+ *   Missed interrupts are collapsed together and delivered as one 'late tick'.
+ *   Guest time always tracks wallclock (i.e., real) time.
+ */
+#define HVM_PARAM_TIMER_MODE   10
+#define HVMPTM_delay_for_missed_ticks    0
+#define HVMPTM_no_delay_for_missed_ticks 1
+#define HVMPTM_no_missed_ticks_pending   2
+#define HVMPTM_one_missed_tick_pending   3
+
+/* Boolean: Enable virtual HPET (high-precision event timer)? (x86-only) */
+#define HVM_PARAM_HPET_ENABLED 11
+
+/* Identity-map page directory used by Intel EPT when CR0.PG=0. */
+#define HVM_PARAM_IDENT_PT     12
+
+/* Device Model domain, defaults to 0. */
+#define HVM_PARAM_DM_DOMAIN    13
+
+/* ACPI S state: currently support S0 and S3 on x86. */
+#define HVM_PARAM_ACPI_S_STATE 14
+
+/* TSS used on Intel when CR0.PE=0. */
+#define HVM_PARAM_VM86_TSS     15
+
+/* Boolean: Enable aligning all periodic vpts to reduce interrupts */
+#define HVM_PARAM_VPT_ALIGN    16
+
+#define HVM_NR_PARAMS          17
+
+#endif /* __XEN_PUBLIC_HVM_PARAMS_H__ */
diff --git a/include/xen/platform_pci.h b/include/xen/platform_pci.h
new file mode 100644
index 000000000000..ce9d671c636c
--- /dev/null
+++ b/include/xen/platform_pci.h
@@ -0,0 +1,49 @@
+#ifndef _XEN_PLATFORM_PCI_H
+#define _XEN_PLATFORM_PCI_H
+
+#define XEN_IOPORT_MAGIC_VAL 0x49d2
+#define XEN_IOPORT_LINUX_PRODNUM 0x0003
+#define XEN_IOPORT_LINUX_DRVVER  0x0001
+
+#define XEN_IOPORT_BASE 0x10
+
+#define XEN_IOPORT_PLATFLAGS    (XEN_IOPORT_BASE + 0) /* 1 byte access (R/W) */
+#define XEN_IOPORT_MAGIC        (XEN_IOPORT_BASE + 0) /* 2 byte access (R) */
+#define XEN_IOPORT_UNPLUG       (XEN_IOPORT_BASE + 0) /* 2 byte access (W) */
+#define XEN_IOPORT_DRVVER       (XEN_IOPORT_BASE + 0) /* 4 byte access (W) */
+
+#define XEN_IOPORT_SYSLOG       (XEN_IOPORT_BASE + 2) /* 1 byte access (W) */
+#define XEN_IOPORT_PROTOVER     (XEN_IOPORT_BASE + 2) /* 1 byte access (R) */
+#define XEN_IOPORT_PRODNUM      (XEN_IOPORT_BASE + 2) /* 2 byte access (W) */
+
+#define XEN_UNPLUG_ALL_IDE_DISKS 1
+#define XEN_UNPLUG_ALL_NICS 2
+#define XEN_UNPLUG_AUX_IDE_DISKS 4
+#define XEN_UNPLUG_ALL 7
+#define XEN_UNPLUG_IGNORE 8
+
+static inline int xen_must_unplug_nics(void) {
+#if (defined(CONFIG_XEN_NETDEV_FRONTEND) || \
+                defined(CONFIG_XEN_NETDEV_FRONTEND_MODULE)) && \
+                (defined(CONFIG_XEN_PLATFORM_PCI) || \
+                 defined(CONFIG_XEN_PLATFORM_PCI_MODULE))
+        return 1;
+#else
+        return 0;
+#endif
+}
+
+static inline int xen_must_unplug_disks(void) {
+#if (defined(CONFIG_XEN_BLKDEV_FRONTEND) || \
+                defined(CONFIG_XEN_BLKDEV_FRONTEND_MODULE)) && \
+                (defined(CONFIG_XEN_PLATFORM_PCI) || \
+                 defined(CONFIG_XEN_PLATFORM_PCI_MODULE))
+        return 1;
+#else
+        return 0;
+#endif
+}
+
+extern int xen_platform_pci_unplug;
+
+#endif /* _XEN_PLATFORM_PCI_H */
diff --git a/include/xen/xen-ops.h b/include/xen/xen-ops.h
index 883a21bba24b..46bc81ef74c6 100644
--- a/include/xen/xen-ops.h
+++ b/include/xen/xen-ops.h
@@ -7,6 +7,7 @@ DECLARE_PER_CPU(struct vcpu_info *, xen_vcpu);
 
 void xen_pre_suspend(void);
 void xen_post_suspend(int suspend_cancelled);
+void xen_hvm_post_suspend(int suspend_cancelled);
 
 void xen_mm_pin_all(void);
 void xen_mm_unpin_all(void);
@@ -14,4 +15,6 @@ void xen_mm_unpin_all(void);
 void xen_timer_resume(void);
 void xen_arch_resume(void);
 
+int xen_setup_shutdown_event(void);
+
 #endif /* INCLUDE_XEN_OPS_H */
diff --git a/kernel/hw_breakpoint.c b/kernel/hw_breakpoint.c
index 7a56b22e0602..71ed3ce29e12 100644
--- a/kernel/hw_breakpoint.c
+++ b/kernel/hw_breakpoint.c
@@ -242,6 +242,17 @@ toggle_bp_slot(struct perf_event *bp, bool enable, enum bp_type_idx type,
 }
 
 /*
+ * Function to perform processor-specific cleanup during unregistration
+ */
+__weak void arch_unregister_hw_breakpoint(struct perf_event *bp)
+{
+        /*
+         * A weak stub function here for those archs that don't define
+         * it inside arch/.../kernel/hw_breakpoint.c
+         */
+}
+
+/*
  * Contraints to check before allowing this new breakpoint counter:
  *
  *  == Non-pinned counter == (Considered as pinned for now)
@@ -339,6 +350,7 @@ void release_bp_slot(struct perf_event *bp)
 {
         mutex_lock(&nr_bp_mutex);
 
+        arch_unregister_hw_breakpoint(bp);
         __release_bp_slot(bp);
 
         mutex_unlock(&nr_bp_mutex);
diff --git a/kernel/printk.c b/kernel/printk.c
index 444b770c9595..4ab0164bcf84 100644
--- a/kernel/printk.c
+++ b/kernel/printk.c
@@ -37,6 +37,8 @@
 #include <linux/ratelimit.h>
 #include <linux/kmsg_dump.h>
 #include <linux/syslog.h>
+#include <linux/cpu.h>
+#include <linux/notifier.h>
 
 #include <asm/uaccess.h>
 
@@ -985,6 +987,32 @@ void resume_console(void)
 }
 
 /**
+ * console_cpu_notify - print deferred console messages after CPU hotplug
+ * @self: notifier struct
+ * @action: CPU hotplug event
+ * @hcpu: unused
+ *
+ * If printk() is called from a CPU that is not online yet, the messages
+ * will be spooled but will not show up on the console.  This function is
+ * called when a new CPU comes online (or fails to come up), and ensures
+ * that any such output gets printed.
+ */
+static int __cpuinit console_cpu_notify(struct notifier_block *self,
+        unsigned long action, void *hcpu)
+{
+        switch (action) {
+        case CPU_ONLINE:
+        case CPU_DEAD:
+        case CPU_DYING:
+        case CPU_DOWN_FAILED:
+        case CPU_UP_CANCELED:
+                acquire_console_sem();
+                release_console_sem();
+        }
+        return NOTIFY_OK;
+}
+
+/**
  * acquire_console_sem - lock the console system for exclusive use.
  *
  * Acquires a semaphore which guarantees that the caller has
@@ -1371,7 +1399,7 @@ int unregister_console(struct console *console)
 }
 EXPORT_SYMBOL(unregister_console);
 
-static int __init disable_boot_consoles(void)
+static int __init printk_late_init(void)
 {
         struct console *con;
 
@@ -1382,9 +1410,10 @@ static int __init disable_boot_consoles(void)
                         unregister_console(con);
                 }
         }
+        hotcpu_notifier(console_cpu_notify, 0);
         return 0;
 }
-late_initcall(disable_boot_consoles);
+late_initcall(printk_late_init);
 
 #if defined CONFIG_PRINTK
 
diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug
index dfdc0347b05d..154ff43aaa81 100644
--- a/lib/Kconfig.debug
+++ b/lib/Kconfig.debug
@@ -528,7 +528,7 @@ config LOCKDEP
         bool
         depends on DEBUG_KERNEL && TRACE_IRQFLAGS_SUPPORT && STACKTRACE_SUPPORT && LOCKDEP_SUPPORT
         select STACKTRACE
-        select FRAME_POINTER if !MIPS && !PPC && !ARM_UNWIND && !S390
+        select FRAME_POINTER if !MIPS && !PPC && !ARM_UNWIND && !S390 && !MICROBLAZE
         select KALLSYMS
         select KALLSYMS_ALL
 
@@ -958,13 +958,13 @@ config FAULT_INJECTION_STACKTRACE_FILTER
         depends on FAULT_INJECTION_DEBUG_FS && STACKTRACE_SUPPORT
         depends on !X86_64
         select STACKTRACE
-        select FRAME_POINTER if !PPC && !S390
+        select FRAME_POINTER if !PPC && !S390 && !MICROBLAZE
         help
           Provide stacktrace filter for fault-injection capabilities
 
 config LATENCYTOP
         bool "Latency measuring infrastructure"
-        select FRAME_POINTER if !MIPS && !PPC && !S390
+        select FRAME_POINTER if !MIPS && !PPC && !S390 && !MICROBLAZE
         select KALLSYMS
         select KALLSYMS_ALL
         select STACKTRACE
diff --git a/samples/kprobes/kprobe_example.c b/samples/kprobes/kprobe_example.c
index a681998a871c..ebf5e0c368ea 100644
--- a/samples/kprobes/kprobe_example.c
+++ b/samples/kprobes/kprobe_example.c
@@ -32,6 +32,11 @@ static int handler_pre(struct kprobe *p, struct pt_regs *regs)
                         " msr = 0x%lx\n",
                 p->addr, regs->nip, regs->msr);
 #endif
+#ifdef CONFIG_MIPS
+        printk(KERN_INFO "pre_handler: p->addr = 0x%p, epc = 0x%lx,"
+                        " status = 0x%lx\n",
+                p->addr, regs->cp0_epc, regs->cp0_status);
+#endif
 
         /* A dump_stack() here will give a stack backtrace */
         return 0;
@@ -49,6 +54,10 @@ static void handler_post(struct kprobe *p, struct pt_regs *regs,
         printk(KERN_INFO "post_handler: p->addr = 0x%p, msr = 0x%lx\n",
                 p->addr, regs->msr);
 #endif
+#ifdef CONFIG_MIPS
+        printk(KERN_INFO "post_handler: p->addr = 0x%p, status = 0x%lx\n",
+                p->addr, regs->cp0_status);
+#endif
 }
 
 /*