1 files changed, 129 insertions, 0 deletions

diff --git a/include/linux/mmc/sh_mmcif.h b/include/linux/mmc/sh_mmcif.h
index e079c6beeb98..d4a2ebbdab4b 100644
--- a/include/linux/mmc/sh_mmcif.h
+++ b/include/linux/mmc/sh_mmcif.h
@@ -68,4 +68,133 @@ extern inline void sh_mmcif_writel(void __iomem *addr, int reg, u32 val)
         writel(val, addr + reg);
 }
 
+#define SH_MMCIF_BBS 512 /* boot block size */
+
+extern inline void sh_mmcif_boot_cmd_send(void __iomem *base,
+                                          unsigned long cmd, unsigned long arg)
+{
+        sh_mmcif_writel(base, MMCIF_CE_INT, 0);
+        sh_mmcif_writel(base, MMCIF_CE_ARG, arg);
+        sh_mmcif_writel(base, MMCIF_CE_CMD_SET, cmd);
+}
+
+extern inline int sh_mmcif_boot_cmd_poll(void __iomem *base, unsigned long mask)
+{
+        unsigned long tmp;
+        int cnt;
+
+        for (cnt = 0; cnt < 1000000; cnt++) {
+                tmp = sh_mmcif_readl(base, MMCIF_CE_INT);
+                if (tmp & mask) {
+                        sh_mmcif_writel(base, MMCIF_CE_INT, tmp & ~mask);
+                        return 0;
+                }
+        }
+
+        return -1;
+}
+
+extern inline int sh_mmcif_boot_cmd(void __iomem *base,
+                                    unsigned long cmd, unsigned long arg)
+{
+        sh_mmcif_boot_cmd_send(base, cmd, arg);
+        return sh_mmcif_boot_cmd_poll(base, 0x00010000);
+}
+
+extern inline int sh_mmcif_boot_do_read_single(void __iomem *base,
+                                               unsigned int block_nr,
+                                               unsigned long *buf)
+{
+        int k;
+
+        /* CMD13 - Status */
+        sh_mmcif_boot_cmd(base, 0x0d400000, 0x00010000);
+
+        if (sh_mmcif_readl(base, MMCIF_CE_RESP0) != 0x0900)
+                return -1;
+
+        /* CMD17 - Read */
+        sh_mmcif_boot_cmd(base, 0x11480000, block_nr * SH_MMCIF_BBS);
+        if (sh_mmcif_boot_cmd_poll(base, 0x00100000) < 0)
+                return -1;
+
+        for (k = 0; k < (SH_MMCIF_BBS / 4); k++)
+                buf[k] = sh_mmcif_readl(base, MMCIF_CE_DATA);
+
+        return 0;
+}
+
+extern inline int sh_mmcif_boot_do_read(void __iomem *base,
+                                        unsigned long first_block,
+                                        unsigned long nr_blocks,
+                                        void *buf)
+{
+        unsigned long k;
+        int ret = 0;
+
+        /* CMD16 - Set the block size */
+        sh_mmcif_boot_cmd(base, 0x10400000, SH_MMCIF_BBS);
+
+        for (k = 0; !ret && k < nr_blocks; k++)
+                ret = sh_mmcif_boot_do_read_single(base, first_block + k,
+                                                   buf + (k * SH_MMCIF_BBS));
+
+        return ret;
+}
+
+extern inline void sh_mmcif_boot_init(void __iomem *base)
+{
+        unsigned long tmp;
+
+        /* reset */
+        tmp = sh_mmcif_readl(base, MMCIF_CE_VERSION);
+        sh_mmcif_writel(base, MMCIF_CE_VERSION, tmp | 0x80000000);
+        sh_mmcif_writel(base, MMCIF_CE_VERSION, tmp & ~0x80000000);
+
+        /* byte swap */
+        sh_mmcif_writel(base, MMCIF_CE_BUF_ACC, 0x00010000);
+
+        /* Set block size in MMCIF hardware */
+        sh_mmcif_writel(base, MMCIF_CE_BLOCK_SET, SH_MMCIF_BBS);
+
+        /* Enable the clock, set it to Bus clock/256 (about 325Khz)*/
+        sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL, 0x01072fff);
+
+        /* CMD0 */
+        sh_mmcif_boot_cmd(base, 0x00000040, 0);
+
+        /* CMD1 - Get OCR */
+        do {
+                sh_mmcif_boot_cmd(base, 0x01405040, 0x40300000); /* CMD1 */
+        } while ((sh_mmcif_readl(base, MMCIF_CE_RESP0) & 0x80000000)
+                 != 0x80000000);
+
+        /* CMD2 - Get CID */
+        sh_mmcif_boot_cmd(base, 0x02806040, 0);
+
+        /* CMD3 - Set card relative address */
+        sh_mmcif_boot_cmd(base, 0x03400040, 0x00010000);
+}
+
+extern inline void sh_mmcif_boot_slurp(void __iomem *base,
+                                       unsigned char *buf,
+                                       unsigned long no_bytes)
+{
+        unsigned long tmp;
+
+        /* In data transfer mode: Set clock to Bus clock/4 (about 20Mhz) */
+        sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL, 0x01012fff);
+
+        /* CMD9 - Get CSD */
+        sh_mmcif_boot_cmd(base, 0x09806000, 0x00010000);
+
+        /* CMD7 - Select the card */
+        sh_mmcif_boot_cmd(base, 0x07400000, 0x00010000);
+
+        tmp = no_bytes / SH_MMCIF_BBS;
+        tmp += (no_bytes % SH_MMCIF_BBS) ? 1 : 0;
+
+        sh_mmcif_boot_do_read(base, 512, tmp, buf);
+}
+
 #endif /* __SH_MMCIF_H__ */