diff options
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_reg.h | 7 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nv50_display.c | 21 |
2 files changed, 19 insertions, 9 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_reg.h b/drivers/gpu/drm/nouveau/nouveau_reg.h index 21a6e453b975..4b813284fdcf 100644 --- a/drivers/gpu/drm/nouveau/nouveau_reg.h +++ b/drivers/gpu/drm/nouveau/nouveau_reg.h | |||
@@ -785,15 +785,12 @@ | |||
785 | #define NV50_PDISPLAY_DAC_MODE_CTRL_C(i) (0x00610b5c + (i) * 0x8) | 785 | #define NV50_PDISPLAY_DAC_MODE_CTRL_C(i) (0x00610b5c + (i) * 0x8) |
786 | #define NV50_PDISPLAY_SOR_MODE_CTRL_P(i) (0x00610b70 + (i) * 0x8) | 786 | #define NV50_PDISPLAY_SOR_MODE_CTRL_P(i) (0x00610b70 + (i) * 0x8) |
787 | #define NV50_PDISPLAY_SOR_MODE_CTRL_C(i) (0x00610b74 + (i) * 0x8) | 787 | #define NV50_PDISPLAY_SOR_MODE_CTRL_C(i) (0x00610b74 + (i) * 0x8) |
788 | #define NV50_PDISPLAY_EXT_MODE_CTRL_P(i) (0x00610b80 + (i) * 0x8) | ||
789 | #define NV50_PDISPLAY_EXT_MODE_CTRL_C(i) (0x00610b84 + (i) * 0x8) | ||
788 | #define NV50_PDISPLAY_DAC_MODE_CTRL2_P(i) (0x00610bdc + (i) * 0x8) | 790 | #define NV50_PDISPLAY_DAC_MODE_CTRL2_P(i) (0x00610bdc + (i) * 0x8) |
789 | #define NV50_PDISPLAY_DAC_MODE_CTRL2_C(i) (0x00610be0 + (i) * 0x8) | 791 | #define NV50_PDISPLAY_DAC_MODE_CTRL2_C(i) (0x00610be0 + (i) * 0x8) |
790 | |||
791 | #define NV90_PDISPLAY_SOR_MODE_CTRL_P(i) (0x00610794 + (i) * 0x8) | 792 | #define NV90_PDISPLAY_SOR_MODE_CTRL_P(i) (0x00610794 + (i) * 0x8) |
792 | #define NV90_PDISPLAY_SOR_MODE_CTRL_C(i) (0x00610798 + (i) * 0x8) | 793 | #define NV90_PDISPLAY_SOR_MODE_CTRL_C(i) (0x00610798 + (i) * 0x8) |
793 | #define NV90_PDISPLAY_DAC_MODE_CTRL_P(i) (0x00610b58 + (i) * 0x8) | ||
794 | #define NV90_PDISPLAY_DAC_MODE_CTRL_C(i) (0x00610b5c + (i) * 0x8) | ||
795 | #define NV90_PDISPLAY_DAC_MODE_CTRL2_P(i) (0x00610b80 + (i) * 0x8) | ||
796 | #define NV90_PDISPLAY_DAC_MODE_CTRL2_C(i) (0x00610b84 + (i) * 0x8) | ||
797 | 794 | ||
798 | #define NV50_PDISPLAY_CRTC_CLK 0x00614000 | 795 | #define NV50_PDISPLAY_CRTC_CLK 0x00614000 |
799 | #define NV50_PDISPLAY_CRTC_CLK_CTRL1(i) ((i) * 0x800 + 0x614100) | 796 | #define NV50_PDISPLAY_CRTC_CLK_CTRL1(i) ((i) * 0x800 + 0x614100) |
diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c index b65d2ddd415d..c11a2fa43c7f 100644 --- a/drivers/gpu/drm/nouveau/nv50_display.c +++ b/drivers/gpu/drm/nouveau/nv50_display.c | |||
@@ -33,6 +33,19 @@ | |||
33 | #include "nouveau_ramht.h" | 33 | #include "nouveau_ramht.h" |
34 | #include "drm_crtc_helper.h" | 34 | #include "drm_crtc_helper.h" |
35 | 35 | ||
36 | static inline int | ||
37 | nv50_sor_nr(struct drm_device *dev) | ||
38 | { | ||
39 | struct drm_nouveau_private *dev_priv = dev->dev_private; | ||
40 | |||
41 | if (dev_priv->chipset < 0x90 || | ||
42 | dev_priv->chipset == 0x92 || | ||
43 | dev_priv->chipset == 0xa0) | ||
44 | return 2; | ||
45 | |||
46 | return 4; | ||
47 | } | ||
48 | |||
36 | static void | 49 | static void |
37 | nv50_evo_channel_del(struct nouveau_channel **pchan) | 50 | nv50_evo_channel_del(struct nouveau_channel **pchan) |
38 | { | 51 | { |
@@ -233,11 +246,11 @@ nv50_display_init(struct drm_device *dev) | |||
233 | nv_wr32(dev, 0x006101d0 + (i * 0x04), val); | 246 | nv_wr32(dev, 0x006101d0 + (i * 0x04), val); |
234 | } | 247 | } |
235 | /* SOR */ | 248 | /* SOR */ |
236 | for (i = 0; i < 4; i++) { | 249 | for (i = 0; i < nv50_sor_nr(dev); i++) { |
237 | val = nv_rd32(dev, 0x0061c000 + (i * 0x800)); | 250 | val = nv_rd32(dev, 0x0061c000 + (i * 0x800)); |
238 | nv_wr32(dev, 0x006101e0 + (i * 0x04), val); | 251 | nv_wr32(dev, 0x006101e0 + (i * 0x04), val); |
239 | } | 252 | } |
240 | /* Something not yet in use, tv-out maybe. */ | 253 | /* EXT */ |
241 | for (i = 0; i < 3; i++) { | 254 | for (i = 0; i < 3; i++) { |
242 | val = nv_rd32(dev, 0x0061e000 + (i * 0x800)); | 255 | val = nv_rd32(dev, 0x0061e000 + (i * 0x800)); |
243 | nv_wr32(dev, 0x006101f0 + (i * 0x04), val); | 256 | nv_wr32(dev, 0x006101f0 + (i * 0x04), val); |
@@ -716,7 +729,7 @@ nv50_display_unk10_handler(struct drm_device *dev) | |||
716 | or = i; | 729 | or = i; |
717 | } | 730 | } |
718 | 731 | ||
719 | for (i = 0; type == OUTPUT_ANY && i < 4; i++) { | 732 | for (i = 0; type == OUTPUT_ANY && i < nv50_sor_nr(dev); i++) { |
720 | if (dev_priv->chipset < 0x90 || | 733 | if (dev_priv->chipset < 0x90 || |
721 | dev_priv->chipset == 0x92 || | 734 | dev_priv->chipset == 0x92 || |
722 | dev_priv->chipset == 0xa0) | 735 | dev_priv->chipset == 0xa0) |
@@ -847,7 +860,7 @@ nv50_display_unk20_handler(struct drm_device *dev) | |||
847 | or = i; | 860 | or = i; |
848 | } | 861 | } |
849 | 862 | ||
850 | for (i = 0; type == OUTPUT_ANY && i < 4; i++) { | 863 | for (i = 0; type == OUTPUT_ANY && i < nv50_sor_nr(dev); i++) { |
851 | if (dev_priv->chipset < 0x90 || | 864 | if (dev_priv->chipset < 0x90 || |
852 | dev_priv->chipset == 0x92 || | 865 | dev_priv->chipset == 0x92 || |
853 | dev_priv->chipset == 0xa0) | 866 | dev_priv->chipset == 0xa0) |