2 files changed, 481 insertions, 17 deletions

diff --git a/sound/soc/codecs/pcm512x.c b/sound/soc/codecs/pcm512x.c
index 874723c36d65..526e6b30cdde 100644
--- a/sound/soc/codecs/pcm512x.c
+++ b/sound/soc/codecs/pcm512x.c
@@ -23,6 +23,7 @@
 #include <linux/regulator/consumer.h>
 #include <sound/soc.h>
 #include <sound/soc-dapm.h>
+#include <sound/pcm_params.h>
 #include <sound/tlv.h>
 
 #include "pcm512x.h"
@@ -39,6 +40,7 @@ struct pcm512x_priv {
         struct clk *sclk;
         struct regulator_bulk_data supplies[PCM512x_NUM_SUPPLIES];
         struct notifier_block supply_nb[PCM512x_NUM_SUPPLIES];
+        int fmt;
 };
 
 /*
@@ -69,6 +71,7 @@ static const struct reg_default pcm512x_reg_defaults[] = {
         { PCM512x_MUTE,              0x00 },
         { PCM512x_DSP,               0x00 },
         { PCM512x_PLL_REF,           0x00 },
+        { PCM512x_DAC_REF,           0x00 },
         { PCM512x_DAC_ROUTING,       0x11 },
         { PCM512x_DSP_PROGRAM,       0x01 },
         { PCM512x_CLKDET,            0x00 },
@@ -87,6 +90,18 @@ static const struct reg_default pcm512x_reg_defaults[] = {
         { PCM512x_ANALOG_GAIN_BOOST, 0x00 },
         { PCM512x_VCOM_CTRL_1,       0x00 },
         { PCM512x_VCOM_CTRL_2,       0x01 },
+        { PCM512x_BCLK_LRCLK_CFG,    0x00 },
+        { PCM512x_MASTER_MODE,       0x7c },
+        { PCM512x_SYNCHRONIZE,       0x10 },
+        { PCM512x_DSP_CLKDIV,        0x00 },
+        { PCM512x_DAC_CLKDIV,        0x00 },
+        { PCM512x_NCP_CLKDIV,        0x00 },
+        { PCM512x_OSR_CLKDIV,        0x00 },
+        { PCM512x_MASTER_CLKDIV_1,   0x00 },
+        { PCM512x_MASTER_CLKDIV_2,   0x00 },
+        { PCM512x_FS_SPEED_MODE,     0x00 },
+        { PCM512x_IDAC_1,            0x01 },
+        { PCM512x_IDAC_2,            0x00 },
 };
 
 static bool pcm512x_readable(struct device *dev, unsigned int reg)
@@ -103,6 +118,8 @@ static bool pcm512x_readable(struct device *dev, unsigned int reg)
         case PCM512x_DSP_GPIO_INPUT:
         case PCM512x_MASTER_MODE:
         case PCM512x_PLL_REF:
+        case PCM512x_DAC_REF:
+        case PCM512x_SYNCHRONIZE:
         case PCM512x_PLL_COEFF_0:
         case PCM512x_PLL_COEFF_1:
         case PCM512x_PLL_COEFF_2:
@@ -303,6 +320,94 @@ static const struct snd_soc_dapm_route pcm512x_dapm_routes[] = {
         { "OUTR", NULL, "DACR" },
 };
 
+static const u32 pcm512x_dai_rates[] = {
+        8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000,
+        88200, 96000, 176400, 192000, 384000,
+};
+
+static const struct snd_pcm_hw_constraint_list constraints_slave = {
+        .count = ARRAY_SIZE(pcm512x_dai_rates),
+        .list  = pcm512x_dai_rates,
+};
+
+static int pcm512x_dai_startup_master(struct snd_pcm_substream *substream,
+                                      struct snd_soc_dai *dai)
+{
+        struct snd_soc_codec *codec = dai->codec;
+        struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec);
+        struct device *dev = dai->dev;
+        struct snd_pcm_hw_constraint_ratnums *constraints_no_pll;
+        struct snd_ratnum *rats_no_pll;
+
+        if (IS_ERR(pcm512x->sclk)) {
+                dev_err(dev, "Need SCLK for master mode: %ld\n",
+                        PTR_ERR(pcm512x->sclk));
+                return PTR_ERR(pcm512x->sclk);
+        }
+
+        constraints_no_pll = devm_kzalloc(dev, sizeof(*constraints_no_pll),
+                                          GFP_KERNEL);
+        if (!constraints_no_pll)
+                return -ENOMEM;
+        constraints_no_pll->nrats = 1;
+        rats_no_pll = devm_kzalloc(dev, sizeof(*rats_no_pll), GFP_KERNEL);
+        if (!rats_no_pll)
+                return -ENOMEM;
+        constraints_no_pll->rats = rats_no_pll;
+        rats_no_pll->num = clk_get_rate(pcm512x->sclk) / 64;
+        rats_no_pll->den_min = 1;
+        rats_no_pll->den_max = 128;
+        rats_no_pll->den_step = 1;
+
+        return snd_pcm_hw_constraint_ratnums(substream->runtime, 0,
+                                             SNDRV_PCM_HW_PARAM_RATE,
+                                             constraints_no_pll);
+}
+
+static int pcm512x_dai_startup_slave(struct snd_pcm_substream *substream,
+                                     struct snd_soc_dai *dai)
+{
+        struct snd_soc_codec *codec = dai->codec;
+        struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec);
+        struct device *dev = dai->dev;
+        struct regmap *regmap = pcm512x->regmap;
+
+        if (IS_ERR(pcm512x->sclk)) {
+                dev_info(dev, "No SCLK, using BCLK: %ld\n",
+                         PTR_ERR(pcm512x->sclk));
+
+                /* Disable reporting of missing SCLK as an error */
+                regmap_update_bits(regmap, PCM512x_ERROR_DETECT,
+                                   PCM512x_IDCH, PCM512x_IDCH);
+
+                /* Switch PLL input to BCLK */
+                regmap_update_bits(regmap, PCM512x_PLL_REF,
+                                   PCM512x_SREF, PCM512x_SREF_BCK);
+        }
+
+        return snd_pcm_hw_constraint_list(substream->runtime, 0,
+                                          SNDRV_PCM_HW_PARAM_RATE,
+                                          &constraints_slave);
+}
+
+static int pcm512x_dai_startup(struct snd_pcm_substream *substream,
+                               struct snd_soc_dai *dai)
+{
+        struct snd_soc_codec *codec = dai->codec;
+        struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec);
+
+        switch (pcm512x->fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+        case SND_SOC_DAIFMT_CBM_CFM:
+                return pcm512x_dai_startup_master(substream, dai);
+
+        case SND_SOC_DAIFMT_CBS_CFS:
+                return pcm512x_dai_startup_slave(substream, dai);
+
+        default:
+                return -EINVAL;
+        }
+}
+
 static int pcm512x_set_bias_level(struct snd_soc_codec *codec,
                                   enum snd_soc_bias_level level)
 {
@@ -340,17 +445,333 @@ static int pcm512x_set_bias_level(struct snd_soc_codec *codec,
         return 0;
 }
 
+static int pcm512x_set_dividers(struct snd_soc_dai *dai,
+                                struct snd_pcm_hw_params *params)
+{
+        struct device *dev = dai->dev;
+        struct snd_soc_codec *codec = dai->codec;
+        struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec);
+        unsigned long sck_rate;
+        unsigned long mck_rate;
+        unsigned long bclk_rate;
+        unsigned long sample_rate;
+        unsigned long osr_rate;
+        int bclk_div;
+        int lrclk_div;
+        int dsp_div;
+        int dac_div;
+        unsigned long dac_rate;
+        int ncp_div;
+        int osr_div;
+        unsigned long dac_mul;
+        unsigned long sck_mul;
+        int ret;
+        int idac;
+        int fssp;
+
+        lrclk_div = snd_soc_params_to_frame_size(params);
+        if (lrclk_div == 0) {
+                dev_err(dev, "No LRCLK?\n");
+                return -EINVAL;
+        }
+
+        sck_rate = clk_get_rate(pcm512x->sclk);
+        bclk_div = params->rate_den * 64 / lrclk_div;
+        bclk_rate = DIV_ROUND_CLOSEST(sck_rate, bclk_div);
+
+        mck_rate = sck_rate;
+
+        if (bclk_div > 128) {
+                dev_err(dev, "Failed to find BCLK divider\n");
+                return -EINVAL;
+        }
+
+        /* the actual rate */
+        sample_rate = sck_rate / bclk_div / lrclk_div;
+        osr_rate = 16 * sample_rate;
+
+        /* run DSP no faster than 50 MHz */
+        dsp_div = mck_rate > 50000000 ? 2 : 1;
+
+        /* run DAC no faster than 6144000 Hz */
+        dac_mul = 6144000 / osr_rate;
+        sck_mul = sck_rate / osr_rate;
+        for (; dac_mul; dac_mul--) {
+                if (!(sck_mul % dac_mul))
+                        break;
+        }
+        if (!dac_mul) {
+                dev_err(dev, "Failed to find DAC rate\n");
+                return -EINVAL;
+        }
+
+        dac_rate = dac_mul * osr_rate;
+        dev_dbg(dev, "dac_rate %lu sample_rate %lu\n", dac_rate, sample_rate);
+
+        dac_div = DIV_ROUND_CLOSEST(sck_rate, dac_rate);
+        if (dac_div > 128) {
+                dev_err(dev, "Failed to find DAC divider\n");
+                return -EINVAL;
+        }
+
+        ncp_div = DIV_ROUND_CLOSEST(sck_rate / dac_div, 1536000);
+        if (ncp_div > 128 || sck_rate / dac_div / ncp_div > 2048000) {
+                /* run NCP no faster than 2048000 Hz, but why? */
+                ncp_div = DIV_ROUND_UP(sck_rate / dac_div, 2048000);
+                if (ncp_div > 128) {
+                        dev_err(dev, "Failed to find NCP divider\n");
+                        return -EINVAL;
+                }
+        }
+
+        osr_div = DIV_ROUND_CLOSEST(dac_rate, osr_rate);
+        if (osr_div > 128) {
+                dev_err(dev, "Failed to find OSR divider\n");
+                return -EINVAL;
+        }
+
+        idac = mck_rate / (dsp_div * sample_rate);
+
+        ret = regmap_write(pcm512x->regmap, PCM512x_DSP_CLKDIV, dsp_div - 1);
+        if (ret != 0) {
+                dev_err(dev, "Failed to write DSP divider: %d\n", ret);
+                return ret;
+        }
+
+        ret = regmap_write(pcm512x->regmap, PCM512x_DAC_CLKDIV, dac_div - 1);
+        if (ret != 0) {
+                dev_err(dev, "Failed to write DAC divider: %d\n", ret);
+                return ret;
+        }
+
+        ret = regmap_write(pcm512x->regmap, PCM512x_NCP_CLKDIV, ncp_div - 1);
+        if (ret != 0) {
+                dev_err(dev, "Failed to write NCP divider: %d\n", ret);
+                return ret;
+        }
+
+        ret = regmap_write(pcm512x->regmap, PCM512x_OSR_CLKDIV, osr_div - 1);
+        if (ret != 0) {
+                dev_err(dev, "Failed to write OSR divider: %d\n", ret);
+                return ret;
+        }
+
+        ret = regmap_write(pcm512x->regmap,
+                           PCM512x_MASTER_CLKDIV_1, bclk_div - 1);
+        if (ret != 0) {
+                dev_err(dev, "Failed to write BCLK divider: %d\n", ret);
+                return ret;
+        }
+
+        ret = regmap_write(pcm512x->regmap,
+                           PCM512x_MASTER_CLKDIV_2, lrclk_div - 1);
+        if (ret != 0) {
+                dev_err(dev, "Failed to write LRCLK divider: %d\n", ret);
+                return ret;
+        }
+
+        ret = regmap_write(pcm512x->regmap, PCM512x_IDAC_1, idac >> 8);
+        if (ret != 0) {
+                dev_err(dev, "Failed to write IDAC msb divider: %d\n", ret);
+                return ret;
+        }
+
+        ret = regmap_write(pcm512x->regmap, PCM512x_IDAC_2, idac & 0xff);
+        if (ret != 0) {
+                dev_err(dev, "Failed to write IDAC lsb divider: %d\n", ret);
+                return ret;
+        }
+
+        if (sample_rate <= 48000)
+                fssp = PCM512x_FSSP_48KHZ;
+        else if (sample_rate <= 96000)
+                fssp = PCM512x_FSSP_96KHZ;
+        else if (sample_rate <= 192000)
+                fssp = PCM512x_FSSP_192KHZ;
+        else
+                fssp = PCM512x_FSSP_384KHZ;
+        ret = regmap_update_bits(pcm512x->regmap, PCM512x_FS_SPEED_MODE,
+                                 PCM512x_FSSP, fssp);
+        if (ret != 0) {
+                dev_err(codec->dev, "Failed to set fs speed: %d\n", ret);
+                return ret;
+        }
+
+        dev_dbg(codec->dev, "DSP divider %d\n", dsp_div);
+        dev_dbg(codec->dev, "DAC divider %d\n", dac_div);
+        dev_dbg(codec->dev, "NCP divider %d\n", ncp_div);
+        dev_dbg(codec->dev, "OSR divider %d\n", osr_div);
+        dev_dbg(codec->dev, "BCK divider %d\n", bclk_div);
+        dev_dbg(codec->dev, "LRCK divider %d\n", lrclk_div);
+        dev_dbg(codec->dev, "IDAC %d\n", idac);
+        dev_dbg(codec->dev, "1<<FSSP %d\n", 1 << fssp);
+
+        return 0;
+}
+
+static int pcm512x_hw_params(struct snd_pcm_substream *substream,
+                             struct snd_pcm_hw_params *params,
+                             struct snd_soc_dai *dai)
+{
+        struct snd_soc_codec *codec = dai->codec;
+        struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec);
+        int alen;
+        int ret;
+
+        dev_dbg(codec->dev, "hw_params %u Hz, %u channels\n",
+                params_rate(params),
+                params_channels(params));
+
+        switch (snd_pcm_format_width(params_format(params))) {
+        case 16:
+                alen = PCM512x_ALEN_16;
+                break;
+        case 20:
+                alen = PCM512x_ALEN_20;
+                break;
+        case 24:
+                alen = PCM512x_ALEN_24;
+                break;
+        case 32:
+                alen = PCM512x_ALEN_32;
+                break;
+        default:
+                dev_err(codec->dev, "Bad frame size: %d\n",
+                        snd_pcm_format_width(params_format(params)));
+                return -EINVAL;
+        }
+
+        switch (pcm512x->fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+        case SND_SOC_DAIFMT_CBS_CFS:
+                ret = regmap_update_bits(pcm512x->regmap,
+                                         PCM512x_BCLK_LRCLK_CFG,
+                                         PCM512x_BCKP
+                                         | PCM512x_BCKO | PCM512x_LRKO,
+                                         0);
+                if (ret != 0) {
+                        dev_err(codec->dev,
+                                "Failed to enable slave mode: %d\n", ret);
+                        return ret;
+                }
+
+                ret = regmap_update_bits(pcm512x->regmap, PCM512x_ERROR_DETECT,
+                                         PCM512x_DCAS, 0);
+                if (ret != 0) {
+                        dev_err(codec->dev,
+                                "Failed to enable clock divider autoset: %d\n",
+                                ret);
+                        return ret;
+                }
+                return 0;
+        case SND_SOC_DAIFMT_CBM_CFM:
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        ret = regmap_update_bits(pcm512x->regmap, PCM512x_I2S_1,
+                                 PCM512x_ALEN, alen);
+        if (ret != 0) {
+                dev_err(codec->dev, "Failed to set frame size: %d\n", ret);
+                return ret;
+        }
+
+        ret = regmap_update_bits(pcm512x->regmap, PCM512x_ERROR_DETECT,
+                                 PCM512x_IDFS | PCM512x_IDBK
+                                 | PCM512x_IDSK | PCM512x_IDCH
+                                 | PCM512x_IDCM | PCM512x_DCAS
+                                 | PCM512x_IPLK,
+                                 PCM512x_IDFS | PCM512x_IDBK
+                                 | PCM512x_IDSK | PCM512x_IDCH
+                                 | PCM512x_DCAS | PCM512x_IPLK);
+        if (ret != 0) {
+                dev_err(codec->dev,
+                        "Failed to ignore auto-clock failures: %d\n",
+                        ret);
+                return ret;
+        }
+
+        ret = regmap_update_bits(pcm512x->regmap, PCM512x_PLL_EN,
+                                 PCM512x_PLLE, 0);
+        if (ret != 0) {
+                dev_err(codec->dev, "Failed to disable pll: %d\n", ret);
+                return ret;
+        }
+
+        ret = pcm512x_set_dividers(dai, params);
+        if (ret != 0)
+                return ret;
+
+        ret = regmap_update_bits(pcm512x->regmap, PCM512x_DAC_REF,
+                                 PCM512x_SDAC, PCM512x_SDAC_SCK);
+        if (ret != 0) {
+                dev_err(codec->dev, "Failed to set sck as dacref: %d\n", ret);
+                return ret;
+        }
+
+        ret = regmap_update_bits(pcm512x->regmap, PCM512x_BCLK_LRCLK_CFG,
+                                 PCM512x_BCKP | PCM512x_BCKO | PCM512x_LRKO,
+                                 PCM512x_BCKO | PCM512x_LRKO);
+        if (ret != 0) {
+                dev_err(codec->dev, "Failed to enable clock output: %d\n", ret);
+                return ret;
+        }
+
+        ret = regmap_update_bits(pcm512x->regmap, PCM512x_MASTER_MODE,
+                                 PCM512x_RLRK | PCM512x_RBCK,
+                                 PCM512x_RLRK | PCM512x_RBCK);
+        if (ret != 0) {
+                dev_err(codec->dev, "Failed to enable master mode: %d\n", ret);
+                return ret;
+        }
+
+        ret = regmap_update_bits(pcm512x->regmap, PCM512x_SYNCHRONIZE,
+                                 PCM512x_RQSY, PCM512x_RQSY_HALT);
+        if (ret != 0) {
+                dev_err(codec->dev, "Failed to halt clocks: %d\n", ret);
+                return ret;
+        }
+
+        ret = regmap_update_bits(pcm512x->regmap, PCM512x_SYNCHRONIZE,
+                                 PCM512x_RQSY, PCM512x_RQSY_RESUME);
+        if (ret != 0) {
+                dev_err(codec->dev, "Failed to resume clocks: %d\n", ret);
+                return ret;
+        }
+
+        return 0;
+}
+
+static int pcm512x_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
+{
+        struct snd_soc_codec *codec = dai->codec;
+        struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec);
+
+        pcm512x->fmt = fmt;
+
+        return 0;
+}
+
+static const struct snd_soc_dai_ops pcm512x_dai_ops = {
+        .startup = pcm512x_dai_startup,
+        .hw_params = pcm512x_hw_params,
+        .set_fmt = pcm512x_set_fmt,
+};
+
 static struct snd_soc_dai_driver pcm512x_dai = {
         .name = "pcm512x-hifi",
         .playback = {
                 .stream_name = "Playback",
                 .channels_min = 2,
                 .channels_max = 2,
-                .rates = SNDRV_PCM_RATE_8000_192000,
+                .rates = SNDRV_PCM_RATE_CONTINUOUS,
+                .rate_min = 8000,
+                .rate_max = 384000,
                 .formats = SNDRV_PCM_FMTBIT_S16_LE |
                            SNDRV_PCM_FMTBIT_S24_LE |
                            SNDRV_PCM_FMTBIT_S32_LE
         },
+        .ops = &pcm512x_dai_ops,
 };
 
 static struct snd_soc_codec_driver pcm512x_codec_driver = {
@@ -448,21 +869,9 @@ int pcm512x_probe(struct device *dev, struct regmap *regmap)
         }
 
         pcm512x->sclk = devm_clk_get(dev, NULL);
-        if (IS_ERR(pcm512x->sclk)) {
-                if (PTR_ERR(pcm512x->sclk) == -EPROBE_DEFER)
-                        return -EPROBE_DEFER;
-
-                dev_info(dev, "No SCLK, using BCLK: %ld\n",
-                         PTR_ERR(pcm512x->sclk));
-
-                /* Disable reporting of missing SCLK as an error */
-                regmap_update_bits(regmap, PCM512x_ERROR_DETECT,
-                                   PCM512x_IDCH, PCM512x_IDCH);
-
-                /* Switch PLL input to BCLK */
-                regmap_update_bits(regmap, PCM512x_PLL_REF,
-                                   PCM512x_SREF, PCM512x_SREF);
-        } else {
+        if (PTR_ERR(pcm512x->sclk) == -EPROBE_DEFER)
+                return -EPROBE_DEFER;
+        if (!IS_ERR(pcm512x->sclk)) {
                 ret = clk_prepare_enable(pcm512x->sclk);
                 if (ret != 0) {
                         dev_err(dev, "Failed to enable SCLK: %d\n", ret);
diff --git a/sound/soc/codecs/pcm512x.h b/sound/soc/codecs/pcm512x.h
index 28b3dfd302bc..fa538d5aabf2 100644
--- a/sound/soc/codecs/pcm512x.h
+++ b/sound/soc/codecs/pcm512x.h
@@ -37,6 +37,8 @@
 #define PCM512x_DSP_GPIO_INPUT    (PCM512x_PAGE_BASE(0) +  10)
 #define PCM512x_MASTER_MODE       (PCM512x_PAGE_BASE(0) +  12)
 #define PCM512x_PLL_REF           (PCM512x_PAGE_BASE(0) +  13)
+#define PCM512x_DAC_REF           (PCM512x_PAGE_BASE(0) +  14)
+#define PCM512x_SYNCHRONIZE       (PCM512x_PAGE_BASE(0) +  19)
 #define PCM512x_PLL_COEFF_0       (PCM512x_PAGE_BASE(0) +  20)
 #define PCM512x_PLL_COEFF_1       (PCM512x_PAGE_BASE(0) +  21)
 #define PCM512x_PLL_COEFF_2       (PCM512x_PAGE_BASE(0) +  22)
@@ -119,8 +121,47 @@
 #define PCM512x_DEMP       (1 << 4)
 #define PCM512x_DEMP_SHIFT 4
 
+/* Page 0, Register 9 - BCK, LRCLK configuration */
+#define PCM512x_LRKO       (1 << 0)
+#define PCM512x_LRKO_SHIFT 0
+#define PCM512x_BCKO       (1 << 4)
+#define PCM512x_BCKO_SHIFT 4
+#define PCM512x_BCKP       (1 << 5)
+#define PCM512x_BCKP_SHIFT 5
+
+/* Page 0, Register 12 - Master mode BCK, LRCLK reset */
+#define PCM512x_RLRK       (1 << 0)
+#define PCM512x_RLRK_SHIFT 0
+#define PCM512x_RBCK       (1 << 1)
+#define PCM512x_RBCK_SHIFT 1
+
 /* Page 0, Register 13 - PLL reference */
-#define PCM512x_SREF (1 << 4)
+#define PCM512x_SREF        (7 << 4)
+#define PCM512x_SREF_SHIFT  4
+#define PCM512x_SREF_SCK    (0 << 4)
+#define PCM512x_SREF_BCK    (1 << 4)
+#define PCM512x_SREF_GPIO   (3 << 4)
+
+/* Page 0, Register 14 - DAC reference */
+#define PCM512x_SDAC        (7 << 4)
+#define PCM512x_SDAC_SHIFT  4
+#define PCM512x_SDAC_MCK    (0 << 4)
+#define PCM512x_SDAC_PLL    (1 << 4)
+#define PCM512x_SDAC_SCK    (3 << 4)
+#define PCM512x_SDAC_BCK    (4 << 4)
+
+/* Page 0, Register 19 - synchronize */
+#define PCM512x_RQSY        (1 << 0)
+#define PCM512x_RQSY_RESUME (0 << 0)
+#define PCM512x_RQSY_HALT   (1 << 0)
+
+/* Page 0, Register 34 - fs speed mode */
+#define PCM512x_FSSP        (3 << 0)
+#define PCM512x_FSSP_SHIFT  0
+#define PCM512x_FSSP_48KHZ  (0 << 0)
+#define PCM512x_FSSP_96KHZ  (1 << 0)
+#define PCM512x_FSSP_192KHZ (2 << 0)
+#define PCM512x_FSSP_384KHZ (3 << 0)
 
 /* Page 0, Register 37 - Error detection */
 #define PCM512x_IPLK (1 << 0)
@@ -131,6 +172,20 @@
 #define PCM512x_IDBK (1 << 5)
 #define PCM512x_IDFS (1 << 6)
 
+/* Page 0, Register 40 - I2S configuration */
+#define PCM512x_ALEN       (3 << 0)
+#define PCM512x_ALEN_SHIFT 0
+#define PCM512x_ALEN_16    (0 << 0)
+#define PCM512x_ALEN_20    (1 << 0)
+#define PCM512x_ALEN_24    (2 << 0)
+#define PCM512x_ALEN_32    (3 << 0)
+#define PCM512x_AFMT       (3 << 4)
+#define PCM512x_AFMT_SHIFT 4
+#define PCM512x_AFMT_I2S   (0 << 4)
+#define PCM512x_AFMT_DSP   (1 << 4)
+#define PCM512x_AFMT_RTJ   (2 << 4)
+#define PCM512x_AFMT_LTJ   (3 << 4)
+
 /* Page 0, Register 42 - DAC routing */
 #define PCM512x_AUPR_SHIFT 0
 #define PCM512x_AUPL_SHIFT 4